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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
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a87b3269 1/* tc-m68k.c All the m68020 specific stuff in one convenient, huge,
fecd2382 2 slow to compile, easy to find file.
f8701a3f 3
a87b3269 4 Copyright (C) 1987, 1991, 1992 Free Software Foundation, Inc.
a39116f1
RP		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
fecd2382
RP		 21
22#include <ctype.h>
f8701a3f 23#define NO_RELOC 0
fecd2382
RP		 24#include "as.h"
25
26#include "obstack.h"
27
a39116f1 28/* note that this file includes real declarations and thus can only be included by one source file per executable. */
e0982afe 29#include "opcode/m68k.h"
f6e504fe
RP		 30#ifdef TE_SUN
31/* This variable contains the value to write out at the beginning of
32 the a.out file. The 2<<16 means that this is a 68020 file instead
33 of an old-style 68000 file */
34
35long omagic = 2<<16|OMAGIC; /* Magic byte for header file */
36#else
37long omagic = OMAGIC;
38#endif
fecd2382
RP		 39
40/* This array holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful */
42const char comment_chars[] = "|";
43
44/* This array holds the chars that only start a comment at the beginning of
45 a line. If the line seems to have the form '# 123 filename'
46 .line and .file directives will appear in the pre-processed output */
47/* Note that input_file.c hand checks for '#' at the beginning of the
48 first line of the input file. This is because the compiler outputs
49 #NO_APP at the beginning of its output. */
50/* Also note that comments like this one will always work. */
51const char line_comment_chars[] = "#";
52
53/* Chars that can be used to separate mant from exp in floating point nums */
54const char EXP_CHARS[] = "eE";
55
56/* Chars that mean this number is a floating point constant */
57/* As in 0f12.456 */
58/* or 0d1.2345e12 */
59
60const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
61
62/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
63 changed in read.c . Ideally it shouldn't have to know about it at all,
64 but nothing is ideal around here.
a39116f1 65 */
fecd2382
RP		 66
67int md_reloc_size = 8; /* Size of relocation record */
68
69/* Its an arbitrary name: This means I don't approve of it */
70/* See flames below */
71static struct obstack robyn;
72
73#define TAB(x,y) (((x)<<2)+(y))
74#define TABTYPE(xy) ((xy) >> 2)
75#define BYTE 0
76#define SHORT 1
77#define LONG 2
78#define SZ_UNDEF 3
79
80#define BRANCH 1
81#define FBRANCH 2
82#define PCREL 3
83#define BCC68000 4
84#define DBCC 5
85#define PCLEA 6
86
f6e504fe 87/* Operands we can parse: (And associated modes)
a39116f1
RP		 88
89 numb: 8 bit num
90 numw: 16 bit num
91 numl: 32 bit num
92 dreg: data reg 0-7
93 reg: address or data register
94 areg: address register
95 apc: address register, PC, ZPC or empty string
96 num: 16 or 32 bit num
97 num2: like num
98 sz: w or l if omitted, l assumed
99 scale: 1 2 4 or 8 if omitted, 1 assumed
100
101 7.4 IMMED #num --> NUM
102 0.? DREG dreg --> dreg
103 1.? AREG areg --> areg
104 2.? AINDR areg@ --> *(areg)
105 3.? AINC areg@+ --> *(areg++)
106 4.? ADEC areg@- --> *(--areg)
107 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
108 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
109 6.? AINDX apc@(reg:sz:scale) --> same, with num=0
110 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
111 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
112 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
113 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
114 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
115 7.0 ABSL num:sz --> *(num)
116 num --> *(num) (sz L assumed)
117 *** MSCR otherreg --> Magic
118 With -l option
119 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
120
121 examples:
122 #foo #0x35 #12
123 d2
124 a4
125 a3@
126 a5@+
127 a6@-
128 a2@(12) pc@(14)
129 a1@(5,d2:w:1) @(45,d6:l:4)
130 pc@(a2) @(d4)
131 etc . . .
132
133
134 #name@(numw) -->turn into PC rel mode
135 apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
136
137 */
f6e504fe
RP		 138
139enum operand_type {
f8701a3f
SC		 140 IMMED = 1,
141 DREG,
142 AREG,
143 AINDR,
144 ADEC,
145 AINC,
146 AOFF,
147 AINDX,
148 APODX,
149 AMIND,
150 APRDX,
151 ABSL,
152 MSCR,
153 REGLST,
f6e504fe
RP		 154};
155
156
fecd2382 157struct m68k_exp {
f8701a3f
SC		 158 char *e_beg;
159 char *e_end;
160 expressionS e_exp;
161 short e_siz; /* 0== default 1==short/byte 2==word 3==long */
fecd2382
RP		 162};
163
7c15cbe8
RP		 164/* DATA and ADDR have to be contiguous, so that reg-DATA gives 0-7==data reg,
165 8-15==addr reg for operands that take both types */
166
167enum _register {
f8701a3f
SC		 168 DATA = 1, /* 1- 8 == data registers 0-7 */
169 DATA0 = DATA,
170 DATA1,
171 DATA2,
172 DATA3,
173 DATA4,
174 DATA5,
175 DATA6,
176 DATA7,
177
178 ADDR,
179 ADDR0 = ADDR,
180 ADDR1,
181 ADDR2,
182 ADDR3,
183 ADDR4,
184 ADDR5,
185 ADDR6,
186 ADDR7,
187
188 /* Note that COPNUM==processor #1 -- COPNUM+7==#8, which stores as 000 */
189 /* I think. . . */
190
191 SP = ADDR7,
192
193 FPREG, /* Eight FP registers */
194 FP0 = FPREG,
195 FP1,
196 FP2,
197 FP3,
198 FP4,
199 FP5,
200 FP6,
201 FP7,
202 COPNUM = (FPREG+8), /* Co-processor #1-#8 */
203 COP0 = COPNUM,
204 COP1,
205 COP2,
206 COP3,
207 COP4,
208 COP5,
209 COP6,
210 COP7,
211 PC, /* Program counter */
212 ZPC, /* Hack for Program space, but 0 addressing */
213 SR, /* Status Reg */
214 CCR, /* Condition code Reg */
215
216 /* These have to be in order for the movec instruction to work. */
217 USP, /* User Stack Pointer */
218 ISP, /* Interrupt stack pointer */
219 SFC,
220 DFC,
221 CACR,
222 VBR,
223 CAAR,
224 MSP,
225 ITT0,
226 ITT1,
227 DTT0,
228 DTT1,
229 MMUSR,
230 TC,
231 SRP,
232 URP,
233 /* end of movec ordering constraints */
234
235 FPI,
236 FPS,
237 FPC,
238
239 DRP,
240 CRP,
241 CAL,
242 VAL,
243 SCC,
244 AC,
245 BAD,
246 BAD0 = BAD,
247 BAD1,
248 BAD2,
249 BAD3,
250 BAD4,
251 BAD5,
252 BAD6,
253 BAD7,
254 BAC,
255 BAC0 = BAC,
256 BAC1,
257 BAC2,
258 BAC3,
259 BAC4,
260 BAC5,
261 BAC6,
262 BAC7,
263 PSR,
264 PCSR,
265
266 IC, /* instruction cache token */
267 DC, /* data cache token */
268 NC, /* no cache token */
269 BC, /* both caches token */
270
7c15cbe8
RP		 271};
272
fecd2382
RP		 273/* Internal form of an operand. */
274struct m68k_op {
f8701a3f
SC		 275 char *error; /* Couldn't parse it */
276 enum operand_type mode; /* What mode this instruction is in. */
277 enum _register reg; /* Base register */
278 struct m68k_exp *con1;
279 int ireg; /* Index register */
280 int isiz; /* 0==unspec 1==byte(?) 2==short 3==long */
281 int imul; /* Multipy ireg by this (1,2,4,or 8) */
282 struct m68k_exp *con2;
fecd2382
RP		 283};
284
285/* internal form of a 68020 instruction */
7c15cbe8 286struct m68k_it {
f8701a3f
SC		 287 char *error;
288 char *args; /* list of opcode info */
289 int numargs;
290
291 int numo; /* Number of shorts in opcode */
292 short opcode[11];
293
294 struct m68k_op operands[6];
295
296 int nexp; /* number of exprs in use */
297 struct m68k_exp exprs[4];
298
299 int nfrag; /* Number of frags we have to produce */
300 struct {
301 int fragoff; /* Where in the current opcode[] the frag ends */
302 symbolS *fadd;
303 long foff;
304 int fragty;
305 } fragb[4];
306
307 int nrel; /* Num of reloc strucs in use */
308 struct {
309 int n;
310 symbolS *add,
311 *sub;
312 long off;
313 char wid;
314 char pcrel;
315 } reloc[5]; /* Five is enough??? */
fecd2382
RP		 316};
317
865a2edf
MT		 318#define cpu_of_arch(x) ((x) & m68000up)
319#define float_of_arch(x) ((x) & mfloat)
320#define mmu_of_arch(x) ((x) & mmmu)
321
7c15cbe8 322static struct m68k_it the_ins; /* the instruction being assembled */
fecd2382 323
7c15cbe8 324/* Macros for adding things to the m68k_it struct */
fecd2382
RP		 325
326#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
327
328/* Like addword, but goes BEFORE general operands */
329#define insop(w) {int z;\
a39116f1
RP		 330 for(z=the_ins.numo;z>opcode->m_codenum;--z)\
331 the_ins.opcode[z]=the_ins.opcode[z-1];\
332 for(z=0;z<the_ins.nrel;z++)\
333 the_ins.reloc[z].n+=2;\
334 the_ins.opcode[opcode->m_codenum]=w;\
335 the_ins.numo++;\
f8701a3f 336 }
fecd2382
RP		 337
338
339#define add_exp(beg,end) (\
a39116f1
RP		 340 the_ins.exprs[the_ins.nexp].e_beg=beg,\
341 the_ins.exprs[the_ins.nexp].e_end=end,\
342 &the_ins.exprs[the_ins.nexp++]\
343 )
fecd2382
RP		 344
345
346/* The numo+1 kludge is so we can hit the low order byte of the prev word. Blecch*/
347#define add_fix(width,exp,pc_rel) {\
a39116f1
RP		 348 the_ins.reloc[the_ins.nrel].n= ((width)=='B') ? (the_ins.numo*2-1) : \
349 (((width)=='b') ? ((the_ins.numo-1)*2) : (the_ins.numo*2));\
350 the_ins.reloc[the_ins.nrel].add=adds((exp));\
351 the_ins.reloc[the_ins.nrel].sub=subs((exp));\
352 the_ins.reloc[the_ins.nrel].off=offs((exp));\
353 the_ins.reloc[the_ins.nrel].wid=width;\
354 the_ins.reloc[the_ins.nrel++].pcrel=pc_rel;\
f8701a3f 355 }
fecd2382
RP		 356
357#define add_frag(add,off,type) {\
a39116f1
RP		 358 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;\
359 the_ins.fragb[the_ins.nfrag].fadd=add;\
360 the_ins.fragb[the_ins.nfrag].foff=off;\
361 the_ins.fragb[the_ins.nfrag++].fragty=type;\
f8701a3f 362 }
fecd2382
RP		 363
364#define isvar(exp) ((exp) && (adds(exp) || subs(exp)))
365
366#define seg(exp) ((exp)->e_exp.X_seg)
367#define adds(exp) ((exp)->e_exp.X_add_symbol)
368#define subs(exp) ((exp)->e_exp.X_subtract_symbol)
369#define offs(exp) ((exp)->e_exp.X_add_number)
370
371
7c15cbe8 372struct m68k_incant {
f8701a3f
SC		 373 char *m_operands;
374 unsigned long m_opcode;
375 short m_opnum;
376 short m_codenum;
377 enum m68k_architecture m_arch;
378 struct m68k_incant *m_next;
fecd2382
RP		 379};
380
381#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
382#define gettwo(x) (((x)->m_opcode)&0xffff)
383
384
a87b3269 385#if __STDC__ == 1
fecd2382
RP		 386
387static char *crack_operand(char *str, struct m68k_op *opP);
388static int get_num(struct m68k_exp *exp, int ok);
389static int get_regs(int i, char *str, struct m68k_op *opP);
390static int reverse_16_bits(int in);
391static int reverse_8_bits(int in);
392static int try_index(char **s, struct m68k_op *opP);
393static void install_gen_operand(int mode, int val);
394static void install_operand(int mode, int val);
a933d598 395 void s_bss(void);
fecd2382
RP		 396static void s_data1(void);
397static void s_data2(void);
398static void s_even(void);
399static void s_proc(void);
400
a87b3269 401#else /* not __STDC__ */
fecd2382
RP		 402
403static char *crack_operand();
404static int get_num();
405static int get_regs();
406static int reverse_16_bits();
407static int reverse_8_bits();
408static int try_index();
409static void install_gen_operand();
410static void install_operand();
a933d598 411 void s_bss();
fecd2382
RP		 412static void s_data1();
413static void s_data2();
414static void s_even();
415static void s_proc();
416
a87b3269 417#endif /* not __STDC__ */
fecd2382 418
865a2edf 419static enum m68k_architecture current_architecture = 0;
7c15cbe8 420
fecd2382
RP		 421/* BCC68000 is for patching in an extra jmp instruction for long offsets
422 on the 68000. The 68000 doesn't support long branches with branchs */
423
424/* This table desribes how you change sizes for the various types of variable
425 size expressions. This version only supports two kinds. */
426
427/* Note that calls to frag_var need to specify the maximum expansion needed */
428/* This is currently 10 bytes for DBCC */
429
430/* The fields are:
a39116f1
RP		 431 How far Forward this mode will reach:
432 How far Backward this mode will reach:
433 How many bytes this mode will add to the size of the frag
434 Which mode to go to if the offset won't fit in this one
435 */
fecd2382 436const relax_typeS
a39116f1 437 md_relax_table[] = {
f8701a3f
SC		 438 { 1, 1, 0, 0 }, /* First entries aren't used */
439 { 1, 1, 0, 0 }, /* For no good reason except */
440 { 1, 1, 0, 0 }, /* that the VAX doesn't either */
441 { 1, 1, 0, 0 },
442
443 { (127), (-128), 0, TAB(BRANCH,SHORT)},
444 { (32767), (-32768), 2, TAB(BRANCH,LONG) },
445 { 0, 0, 4, 0 },
446 { 1, 1, 0, 0 },
447
448 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */
449 { (32767), (-32768), 2, TAB(FBRANCH,LONG)},
450 { 0, 0, 4, 0 },
451 { 1, 1, 0, 0 },
452
453 { 1, 1, 0, 0 }, /* PCREL doesn't come BYTE */
454 { (32767), (-32768), 2, TAB(PCREL,LONG)},
455 { 0, 0, 4, 0 },
456 { 1, 1, 0, 0 },
457
458 { (127), (-128), 0, TAB(BCC68000,SHORT)},
459 { (32767), (-32768), 2, TAB(BCC68000,LONG) },
460 { 0, 0, 6, 0 }, /* jmp long space */
461 { 1, 1, 0, 0 },
462
463 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
464 { (32767), (-32768), 2, TAB(DBCC,LONG) },
465 { 0, 0, 10, 0 }, /* bra/jmp long space */
466 { 1, 1, 0, 0 },
467
468 { 1, 1, 0, 0 }, /* PCLEA doesn't come BYTE */
469 { 32767, -32768, 2, TAB(PCLEA,LONG) },
470 { 0, 0, 6, 0 },
471 { 1, 1, 0, 0 },
472
473 };
fecd2382
RP		 474
475/* These are the machine dependent pseudo-ops. These are included so
476 the assembler can work on the output from the SUN C compiler, which
477 generates these.
a39116f1 478 */
fecd2382
RP		 479
480/* This table describes all the machine specific pseudo-ops the assembler
481 has to support. The fields are:
a39116f1
RP		 482 pseudo-op name without dot
483 function to call to execute this pseudo-op
484 Integer arg to pass to the function
485 */
fecd2382 486const pseudo_typeS md_pseudo_table[] = {
f8701a3f
SC		 487 { "data1", s_data1, 0 },
488 { "data2", s_data2, 0 },
489 { "bss", s_bss, 0 },
490 { "even", s_even, 0 },
491 { "skip", s_space, 0 },
492 { "proc", s_proc, 0 },
493 { 0, 0, 0 }
fecd2382
RP		 494};
495
496
497/* #define isbyte(x) ((x)>=-128 && (x)<=127) */
498/* #define isword(x) ((x)>=-32768 && (x)<=32767) */
499
500#define issbyte(x) ((x)>=-128 && (x)<=127)
501#define isubyte(x) ((x)>=0 && (x)<=255)
502#define issword(x) ((x)>=-32768 && (x)<=32767)
503#define isuword(x) ((x)>=0 && (x)<=65535)
f8701a3f 504
fecd2382
RP		 505#define isbyte(x) ((x)>=-128 && (x)<=255)
506#define isword(x) ((x)>=-32768 && (x)<=65535)
507#define islong(x) (1)
f8701a3f
SC		 508
509extern char *input_line_pointer;
fecd2382 510
7c15cbe8 511enum {
f8701a3f
SC		 512 FAIL = 0,
513 OK = 1,
7c15cbe8 514};
fecd2382
RP		 515
516/* JF these tables here are for speed at the expense of size */
517/* You can replace them with the #if 0 versions if you really
518 need space and don't mind it running a bit slower */
519
520static char mklower_table[256];
521#define mklower(c) (mklower_table[(unsigned char)(c)])
f8701a3f 522static char notend_table[256];
fecd2382
RP		 523static char alt_notend_table[256];
524#define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
a39116f1 525 alt_notend_table[(unsigned char)(s[1])])))
fecd2382
RP		 526
527#if 0
528#define mklower(c) (isupper(c) ? tolower(c) : c)
529#endif
f8701a3f
SC		 530
531
532/* JF modified this to handle cases where the first part of a symbol name
533 looks like a register */
534
535/*
536 * m68k_reg_parse() := if it looks like a register, return it's token &
537 * advance the pointer.
538 */
539
540enum _register m68k_reg_parse(ccp)
fecd2382
RP		 541register char **ccp;
542{
f8701a3f
SC		 543 char *start = *ccp;
544
545 if (isalpha(*start) && is_name_beginner(*start))
546 {
547 char c;
548 char *p = start;
549 symbolS *symbolP;
a39116f1 550
f8701a3f
SC		 551 while (is_part_of_name(c = *p++))
552 ;
553 * -- p = 0;
554 symbolP = symbol_find(start);
555 *p = c;
556
557 if (symbolP && S_GET_SEGMENT(symbolP) == SEG_REGISTER)
a39116f1 558 {
f8701a3f
SC		 559 *ccp = p;
560 return S_GET_VALUE(symbolP);
a39116f1 561 }
f8701a3f
SC		 562 }
563 return FAIL;
564
565
fecd2382
RP		 566}
567
568#define SKIP_WHITE() { str++; if(*str==' ') str++;}
569
7c15cbe8
RP		 570/*
571 * m68k_ip_op := '#' + <anything>
572 * | <register> + range_sep + get_regs
573 * ;
574 *
575 * range_sep := '/' | '-' ;
576 *
577 * SKIP_WHITE := <empty> | ' ' ;
578 *
579 */
580
fecd2382 581int
a39116f1 582 m68k_ip_op(str,opP)
fecd2382
RP		 583char *str;
584register struct m68k_op *opP;
585{
f8701a3f
SC		 586 char *strend;
587 long i;
588 char *parse_index();
a933d598 589 int needp;
f8701a3f
SC		 590 if (*str==' ') {
591 str++;
592 } /* Find the beginning of the string */
a39116f1 593
f8701a3f
SC		 594 if(!*str) {
595 opP->error="Missing operand";
fecd2382 596 return FAIL;
f8701a3f
SC		 597 } /* Out of gas */
598
599 for(strend = str; *strend; strend++) ;;
600
601 --strend;
602
603 if(*str=='#') {
604 str++;
605 opP->con1=add_exp(str,strend);
606 opP->mode=IMMED;
607 return OK;
608 } /* Guess what: A constant. Shar and enjoy */
609
610 i = m68k_reg_parse(&str);
611
612 /* is a register, is exactly a register, and is followed by '@' */
613
614 if((i==FAIL || *str!='\0') && *str!='@') {
615 char *stmp;
616
617 if(i!=FAIL && (*str=='/' || *str=='-')) {
618 opP->mode=REGLST;
619 return(get_regs(i,str,opP));
620 }
621 if ((stmp=strchr(str,'@')) != '\0') {
622 opP->con1=add_exp(str,stmp-1);
623 if(stmp==strend) {
624 opP->mode=AINDX;
625 return(OK);
626 }
627
628 if ((current_architecture & m68020up) == 0) {
629 return(FAIL);
630 } /* if target is not a '20 or better */
631
632 stmp++;
633 if(*stmp++!='(' || *strend--!=')') {
634 opP->error="Malformed operand";
635 return(FAIL);
636 }
637 i=try_index(&stmp,opP);
638 opP->con2=add_exp(stmp,strend);
639
640 if (i == FAIL) {
641 opP->mode=AMIND;
642 } else {
643 opP->mode=APODX;
644 }
645 return(OK);
646 } /* if there's an '@' */
647 opP->mode = ABSL;
648 opP->con1 = add_exp(str,strend);
649 return(OK);
650 } /* not a register, not exactly a register, or no '@' */
651
652 opP->reg=i;
653
654 if (*str=='\0') {
655 if(i>=DATA+0 && i<=DATA+7)
656 opP->mode=DREG;
657 else if(i>=ADDR+0 && i<=ADDR+7)
658 opP->mode=AREG;
659 else
660 opP->mode=MSCR;
661 return OK;
fecd2382 662 }
f8701a3f
SC		 663
664 if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL) { /* Can't indirect off non address regs */
665 opP->error="Invalid indirect register";
a39116f1 666 return FAIL;
fecd2382 667 }
f8701a3f 668 know(*str == '@');
a39116f1 669
f8701a3f
SC		 670 str++;
671 switch(*str) {
672 case '\0':
673 opP->mode=AINDR;
674 return OK;
675 case '-':
676 opP->mode=ADEC;
677 return OK;
678 case '+':
679 opP->mode=AINC;
680 return OK;
681 case '(':
682 str++;
683 break;
684 default:
685 opP->error="Junk after indirect";
686 return FAIL;
fecd2382 687 }
f8701a3f
SC		 688 /* Some kind of indexing involved. Lets find out how bad it is */
689 i=try_index(&str,opP);
690 /* Didn't start with an index reg, maybe its offset or offset,reg */
691 if(i==FAIL) {
692 char *beg_str;
693
694 beg_str=str;
695 for(i=1;i;) {
696 switch(*str++) {
697 case '\0':
698 opP->error="Missing )";
699 return FAIL;
700 case ',': i=0; break;
701 case '(': i++; break;
702 case ')': --i; break;
703 }
704 }
705 /* if(str[-3]==':') {
706 int siz;
707
708 switch(str[-2]) {
709 case 'b':
710 case 'B':
711 siz=1;
712 break;
713 case 'w':
714 case 'W':
715 siz=2;
716 break;
717 case 'l':
718 case 'L':
719 siz=3;
720 break;
721 default:
722 opP->error="Specified size isn't :w or :l";
723 return FAIL;
724 }
725 opP->con1=add_exp(beg_str,str-4);
726 opP->con1->e_siz=siz;
727 } else */
728 opP->con1=add_exp(beg_str,str-2);
729 /* Should be offset,reg */
730 if(str[-1]==',') {
731 i=try_index(&str,opP);
732 if(i==FAIL) {
733 opP->error="Malformed index reg";
734 return FAIL;
735 }
736 }
737 }
738 /* We've now got offset) offset,reg) or reg) */
a39116f1 739
f8701a3f
SC		 740 if (*str == '\0') {
741 /* Th-the-thats all folks */
742 if (opP->reg == FAIL) opP->mode = AINDX; /* Other form of indirect */
743 else if(opP->ireg == FAIL) opP->mode = AOFF;
744 else opP->mode = AINDX;
745 return(OK);
746 }
747 /* Next thing had better be another @ */
a933d598
SC		 748 if (*str == '@') {
749 if (str[1] == '(') {
750 needp = 1;
751 str+=2;
752 }
753 else {
754 needp = 0;
755 str++;
756 }
fecd2382 757 }
865a2edf 758
f8701a3f 759 if ((current_architecture & m68020up) == 0) {
a39116f1 760 return(FAIL);
f8701a3f
SC		 761 } /* if target is not a '20 or better */
762
f8701a3f
SC		 763
764 if(opP->ireg != FAIL) {
765 opP->mode = APRDX;
766
767 i = try_index(&str, opP);
768 if (i != FAIL) {
769 opP->error = "Two index registers! not allowed!";
770 return(FAIL);
771 }
865a2edf 772 } else {
f8701a3f 773 i = try_index(&str, opP);
865a2edf 774 }
f8701a3f
SC		 775
776 if (i == FAIL) {
777 char *beg_str;
778
779 beg_str = str;
780
781 for (i = 1; i; ) {
782 switch(*str++) {
783 case '\0':
a933d598 784 if (needp)
f8701a3f
SC		 785 opP->error="Missing )";
786 return(FAIL);
a933d598 787 break;
f8701a3f
SC		 788 case ',': i=0; break;
789 case '(': i++; break;
790 case ')': --i; break;
791 }
792 }
793
794 opP->con2=add_exp(beg_str,str-2);
795
796 if (str[-1] == ',') {
797 if (opP->ireg != FAIL) {
798 opP->error = "Can't have two index regs";
799 return(FAIL);
800 }
801
802 i = try_index(&str, opP);
803
804 if (i == FAIL) {
805 opP->error = "malformed index reg";
806 return(FAIL);
807 }
808
809 opP->mode = APODX;
810 } else if (opP->ireg != FAIL) {
811 opP->mode = APRDX;
812 } else {
813 opP->mode = AMIND;
814 }
815 } else {
816 opP->mode = APODX;
817 }
818
819 if(*str!='\0') {
820 opP->error="Junk after indirect";
821 return FAIL;
822 }
823 return(OK);
a39116f1 824} /* m68k_ip_op() */
fecd2382 825
7c15cbe8
RP		 826/*
827 *
828 * try_index := data_or_address_register + ')' + SKIP_W
829 * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W
830 *
831 * multiplier := <empty>
832 * | ':' + multiplier_number
833 * ;
834 *
835 * multiplier_number := '1' | '2' | '4' | '8' ;
836 *
837 * size_spec := 'l' | 'L' | 'w' | 'W' ;
838 *
839 * SKIP_W := <empty> | ' ' ;
840 *
841 */
842
fecd2382 843static int try_index(s,opP)
f8701a3f
SC		 844char **s;
845struct m68k_op *opP;
fecd2382 846{
f8701a3f
SC		 847 register int i;
848 char *ss;
7c15cbe8 849#define SKIP_W() { ss++; if (*ss==' ') ss++;}
f8701a3f
SC		 850
851 ss= *s;
852 /* SKIP_W(); */
853 i=m68k_reg_parse(&ss);
854 if(!(i>=DATA+0 && i<=ADDR+7)) { /* if i is not DATA or ADDR reg */
855 *s=ss;
856 return FAIL;
857 }
858 opP->ireg=i;
859 /* SKIP_W(); */
860 if(*ss==')') {
861 opP->isiz=0;
862 opP->imul=1;
863 SKIP_W();
864 *s=ss;
865 return OK;
866 }
867 if(*ss!=':') {
868 opP->error="Missing : in index register";
869 *s=ss;
870 return FAIL;
871 }
fecd2382
RP		 872 SKIP_W();
873 switch(*ss) {
f8701a3f
SC		 874 case 'w':
875 case 'W':
876 opP->isiz=2;
877 break;
878 case 'l':
879 case 'L':
880 opP->isiz=3;
881 break;
fecd2382 882 default:
f8701a3f
SC		 883 opP->error="Index register size spec not :w or :l";
884 *s=ss;
885 return FAIL;
886 }
887 SKIP_W();
888 if(*ss==':') {
889 SKIP_W();
890 switch(*ss) {
891 case '1':
892 case '2':
893 case '4':
894 case '8':
895 opP->imul= *ss-'0';
896 break;
897 default:
898 opP->error="index multiplier not 1, 2, 4 or 8";
899 *s=ss;
900 return FAIL;
901 }
902 SKIP_W();
903 } else opP->imul=1;
904 if(*ss!=')') {
905 opP->error="Missing )";
906 *s=ss;
907 return FAIL;
fecd2382
RP		 908 }
909 SKIP_W();
910 *s=ss;
f8701a3f 911 return OK;
fecd2382
RP		 912} /* try_index() */
913
914#ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
915main()
916{
f8701a3f
SC		 917 char buf[128];
918 struct m68k_op thark;
919
920 for(;;) {
921 if(!gets(buf))
922 break;
923 memset(&thark, '\0', sizeof(thark));
924 if(!m68k_ip_op(buf,&thark)) printf("FAIL:");
925 if(thark.error)
926 printf("op1 error %s in %s\n",thark.error,buf);
927 printf("mode %d, reg %d, ",thark.mode,thark.reg);
928 if(thark.b_const)
929 printf("Constant: '%.*s',",1+thark.e_const-thark.b_const,thark.b_const);
930 printf("ireg %d, isiz %d, imul %d ",thark.ireg,thark.isiz,thark.imul);
931 if(thark.b_iadd)
932 printf("Iadd: '%.*s'",1+thark.e_iadd-thark.b_iadd,thark.b_iadd);
933 printf("\n");
934 }
935 exit(0);
fecd2382
RP		 936}
937
938#endif
939
940
941static struct hash_control* op_hash = NULL; /* handle of the OPCODE hash table
a39116f1
RP		 942 NULL means any use before m68k_ip_begin()
943 will crash */
fecd2382
RP		 944
945\f
946/*
7c15cbe8 947 * m 6 8 k _ i p ( )
fecd2382
RP		 948 *
949 * This converts a string into a 68k instruction.
950 * The string must be a bare single instruction in sun format
951 * with RMS-style 68020 indirects
952 * (example: )
953 *
954 * It provides some error messages: at most one fatal error message (which
955 * stops the scan) and at most one warning message for each operand.
956 * The 68k instruction is returned in exploded form, since we have no
957 * knowledge of how you parse (or evaluate) your expressions.
958 * We do however strip off and decode addressing modes and operation
959 * mnemonic.
960 *
961 * This function's value is a string. If it is not "" then an internal
962 * logic error was found: read this code to assign meaning to the string.
963 * No argument string should generate such an error string:
964 * it means a bug in our code, not in the user's text.
965 *
7c15cbe8 966 * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using
fecd2382
RP		 967 * this function.
968 */
969
970/* JF this function no longer returns a useful value. Sorry */
7c15cbe8 971void m68k_ip (instring)
f8701a3f 972char *instring;
fecd2382 973{
f8701a3f
SC		 974 register char *p;
975 register struct m68k_op *opP;
976 register struct m68k_incant *opcode;
977 register char *s;
978 register int tmpreg = 0,
979 baseo = 0,
980 outro = 0,
981 nextword;
982 int siz1,
983 siz2;
984 char c;
985 int losing;
986 int opsfound;
987 char *crack_operand();
988 LITTLENUM_TYPE words[6];
989 LITTLENUM_TYPE *wordp;
990
991 if (*instring == ' ')
992 instring++; /* skip leading whitespace */
993
994 /* Scan up to end of operation-code, which MUST end in end-of-string
995 or exactly 1 space. */
996 for (p = instring; *p != '\0'; p++)
997 if (*p == ' ')
998 break;
7c15cbe8 999
7c15cbe8 1000
f8701a3f
SC		 1001 if (p == instring) {
1002 the_ins.error = "No operator";
1003 the_ins.opcode[0] = NULL;
1004 /* the_ins.numo=1; */
1005 return;
fecd2382 1006 }
7c15cbe8 1007
f8701a3f
SC		 1008 /* p now points to the end of the opcode name, probably whitespace.
1009 make sure the name is null terminated by clobbering the whitespace,
1010 look it up in the hash table, then fix it back. */
1011 c = *p;
1012 *p = '\0';
1013 opcode = (struct m68k_incant *)hash_find (op_hash, instring);
1014 *p = c;
7c15cbe8 1015
f8701a3f
SC		 1016 if (opcode == NULL) {
1017 the_ins.error = "Unknown operator";
1018 the_ins.opcode[0] = NULL;
1019 /* the_ins.numo=1; */
1020 return;
1021 }
1022
1023 /* found a legitimate opcode, start matching operands */
1024 while (*p == ' ') ++p;
1025
1026 for(opP = &the_ins.operands[0]; *p; opP++) {
1027
1028 p = crack_operand(p, opP);
1029
1030 if (opP->error) {
1031 the_ins.error=opP->error;
1032 return;
1033 }
1034 }
1035
1036 opsfound = opP - &the_ins.operands[0];
1037
1038 /* This ugly hack is to support the floating pt opcodes in their standard form */
1039 /* Essentially, we fake a first enty of type COP#1 */
1040 if (opcode->m_operands[0]=='I') {
1041 int n;
1042
1043 for(n=opsfound;n>0;--n)
1044 the_ins.operands[n]=the_ins.operands[n-1];
1045
1046 /* memcpy((char *)(&the_ins.operands[1]), (char *)(&the_ins.operands[0]), opsfound*sizeof(the_ins.operands[0])); */
1047 memset((char *)(&the_ins.operands[0]), '\0', sizeof(the_ins.operands[0]));
1048 the_ins.operands[0].mode=MSCR;
1049 the_ins.operands[0].reg=COPNUM; /* COP #1 */
1050 opsfound++;
1051 }
1052
1053 /* We've got the operands. Find an opcode that'll accept them */
1054 for (losing = 0; ; ) {
1055 /* if we didn't get the right number of ops,
1056 or we have no common model with this pattern
1057 then reject this pattern. */
1058
1059 if (opsfound != opcode->m_opnum
1060 || ((opcode->m_arch & current_architecture) == 0)) {
7c15cbe8 1061
f8701a3f
SC		 1062 ++losing;
1063
1064 } else {
1065 for (s=opcode->m_operands, opP = &the_ins.operands[0]; *s && !losing; s += 2, opP++) {
1066 /* Warning: this switch is huge! */
1067 /* I've tried to organize the cases into this order:
1068 non-alpha first, then alpha by letter. lower-case goes directly
1069 before uppercase counterpart. */
1070 /* Code with multiple case ...: gets sorted by the lowest case ...
1071 it belongs to. I hope this makes sense. */
1072 switch(*s) {
1073 case '!':
1074 if (opP->mode == MSCR || opP->mode == IMMED
1075 || opP->mode == DREG || opP->mode == AREG
1076 || opP->mode == AINC || opP->mode == ADEC
1077 || opP->mode == REGLST)
1078 losing++;
1079 break;
1080
1081 case '#':
1082 if(opP->mode!=IMMED)
1083 losing++;
1084 else {
1085 long t;
1086
1087 t=get_num(opP->con1,80);
1088 if(s[1]=='b' && !isbyte(t))
1089 losing++;
1090 else if(s[1]=='w' && !isword(t))
1091 losing++;
1092 }
1093 break;
1094
1095 case '^':
1096 case 'T':
1097 if(opP->mode!=IMMED)
1098 losing++;
1099 break;
1100
1101 case '$':
1102 if(opP->mode==MSCR || opP->mode==AREG ||
1103 opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST)
1104 losing++;
1105 break;
1106
1107 case '%':
1108 if(opP->mode==MSCR || opP->reg==PC ||
1109 opP->reg==ZPC || opP->mode==REGLST)
1110 losing++;
1111 break;
1112
1113
1114 case '&':
1115 if(opP->mode==MSCR || opP->mode==DREG ||
1116 opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC ||
1117 opP->mode==AINC || opP->mode==ADEC || opP->mode==REGLST)
1118 losing++;
1119 break;
1120
1121 case '*':
1122 if(opP->mode==MSCR || opP->mode==REGLST)
1123 losing++;
1124 break;
1125
1126 case '+':
1127 if(opP->mode!=AINC)
1128 losing++;
1129 break;
1130
1131 case '-':
1132 if(opP->mode!=ADEC)
1133 losing++;
1134 break;
1135
1136 case '/':
1137 if(opP->mode==MSCR || opP->mode==AREG ||
1138 opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->mode==REGLST)
1139 losing++;
1140 break;
1141
1142 case ';':
1143 if(opP->mode==MSCR || opP->mode==AREG || opP->mode==REGLST)
1144 losing++;
1145 break;
1146
1147 case '?':
1148 if(opP->mode==MSCR || opP->mode==AREG ||
1149 opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->reg==PC ||
1150 opP->reg==ZPC || opP->mode==REGLST)
1151 losing++;
1152 break;
1153
1154 case '@':
1155 if(opP->mode==MSCR || opP->mode==AREG ||
1156 opP->mode==IMMED || opP->mode==REGLST)
1157 losing++;
1158 break;
1159
1160 case '~': /* For now! (JF FOO is this right?) */
1161 if(opP->mode==MSCR || opP->mode==DREG ||
1162 opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST)
1163 losing++;
1164 break;
1165
1166 case 'A':
1167 if(opP->mode!=AREG)
1168 losing++;
1169 break;
1170 case 'a':
1171 if (opP->mode != AINDR) {
1172 ++losing;
1173 } /* if not address register indirect */
1174 break;
1175 case 'B': /* FOO */
1176 if(opP->mode!=ABSL || (flagseen['S'] && instring[0] == 'j'
1177 && instring[1] == 'b'
1178 && instring[2] == 's'
1179 && instring[3] == 'r'))
1180 losing++;
1181 break;
1182
1183 case 'C':
1184 if(opP->mode!=MSCR || opP->reg!=CCR)
1185 losing++;
1186 break;
1187
1188 case 'd': /* FOO This mode is a KLUDGE!! */
1189 if(opP->mode!=AOFF && (opP->mode!=ABSL ||
1190 opP->con1->e_beg[0]!='(' || opP->con1->e_end[0]!=')'))
1191 losing++;
1192 break;
1193
1194 case 'D':
1195 if(opP->mode!=DREG)
1196 losing++;
1197 break;
1198
1199 case 'F':
1200 if(opP->mode!=MSCR || opP->reg<(FPREG+0) || opP->reg>(FPREG+7))
1201 losing++;
1202 break;
1203
1204 case 'I':
1205 if(opP->mode!=MSCR || opP->reg<COPNUM ||
1206 opP->reg>=COPNUM+7)
1207 losing++;
1208 break;
1209
1210 case 'J':
1211 if (opP->mode != MSCR
1212 || opP->reg < USP
1213 || opP->reg > URP
1214 || cpu_of_arch(current_architecture) < m68010 /* before 68010 had none */
1215 || (cpu_of_arch(current_architecture) < m68020
1216 && opP->reg != SFC
1217 && opP->reg != DFC
1218 && opP->reg != USP
1219 && opP->reg != VBR) /* 68010's had only these */
1220 || (cpu_of_arch(current_architecture) < m68040
1221 && opP->reg != SFC
1222 && opP->reg != DFC
1223 && opP->reg != USP
1224 && opP->reg != VBR
1225 && opP->reg != CACR
1226 && opP->reg != CAAR
1227 && opP->reg != MSP
1228 && opP->reg != ISP) /* 680[23]0's have only these */
1229 || (cpu_of_arch(current_architecture) == m68040 /* 68040 has all but this */
1230 && opP->reg == CAAR)) {
1231 losing++;
1232 } /* doesn't cut it */
1233 break;
1234
1235 case 'k':
1236 if(opP->mode!=IMMED)
1237 losing++;
1238 break;
1239
1240 case 'l':
1241 case 'L':
1242 if(opP->mode==DREG || opP->mode==AREG || opP->mode==FPREG) {
1243 if(s[1]=='8')
1244 losing++;
1245 else {
1246 opP->mode=REGLST;
1247 opP->reg=1<<(opP->reg-DATA);
1248 }
1249 } else if(opP->mode!=REGLST) {
1250 losing++;
1251 } else if(s[1]=='8' && opP->reg&0x0FFffFF)
1252 losing++;
1253 else if(s[1]=='3' && opP->reg&0x7000000)
1254 losing++;
1255 break;
1256
1257 case 'M':
1258 if(opP->mode!=IMMED)
1259 losing++;
1260 else {
1261 long t;
1262
1263 t=get_num(opP->con1,80);
1264 if(!issbyte(t) || isvar(opP->con1))
1265 losing++;
1266 }
1267 break;
1268
1269 case 'O':
1270 if(opP->mode!=DREG && opP->mode!=IMMED)
1271 losing++;
1272 break;
1273
1274 case 'Q':
1275 if(opP->mode!=IMMED)
1276 losing++;
1277 else {
1278 long t;
1279
1280 t=get_num(opP->con1,80);
1281 if(t<1 || t>8 || isvar(opP->con1))
1282 losing++;
1283 }
1284 break;
1285
1286 case 'R':
1287 if(opP->mode!=DREG && opP->mode!=AREG)
1288 losing++;
1289 break;
1290
1291 case 's':
1292 if(opP->mode!=MSCR || !(opP->reg==FPI || opP->reg==FPS || opP->reg==FPC))
1293 losing++;
1294 break;
1295
1296 case 'S':
1297 if(opP->mode!=MSCR || opP->reg!=SR)
1298 losing++;
1299 break;
1300
1301 case 'U':
1302 if(opP->mode!=MSCR || opP->reg!=USP)
1303 losing++;
1304 break;
1305
1306 /* JF these are out of order. We could put them
1307 in order if we were willing to put up with
1308 bunches of #ifdef m68851s in the code */
1309#ifndef NO_68851
1310 /* Memory addressing mode used by pflushr */
1311 case '|':
1312 if(opP->mode==MSCR || opP->mode==DREG ||
1313 opP->mode==AREG || opP->mode==REGLST)
1314 losing++;
1315 break;
1316
1317 case 'f':
1318 if (opP->mode != MSCR || (opP->reg != SFC && opP->reg != DFC))
1319 losing++;
1320 break;
1321
1322 case 'P':
1323 if (opP->mode != MSCR || (opP->reg != TC && opP->reg != CAL &&
1324 opP->reg != VAL && opP->reg != SCC && opP->reg != AC))
1325 losing++;
1326 break;
1327
1328 case 'V':
1329 if (opP->reg != VAL)
1330 losing++;
1331 break;
1332
1333 case 'W':
1334 if (opP->mode != MSCR || (opP->reg != DRP && opP->reg != SRP &&
1335 opP->reg != CRP))
1336 losing++;
1337 break;
1338
1339 case 'X':
1340 if (opP->mode != MSCR ||
1341 (!(opP->reg >= BAD && opP->reg <= BAD+7) &&
1342 !(opP->reg >= BAC && opP->reg <= BAC+7)))
1343 losing++;
1344 break;
1345
1346 case 'Y':
1347 if (opP->reg != PSR)
1348 losing++;
1349 break;
1350
1351 case 'Z':
1352 if (opP->reg != PCSR)
1353 losing++;
1354 break;
1355#endif
1356 case 'c':
1357 if (opP->reg != NC
1358 && opP->reg != IC
1359 && opP->reg != DC
1360 && opP->reg != BC) {
1361 losing++;
1362 } /* not a cache specifier. */
1363 break;
1364
1365 case '_':
1366 if (opP->mode != ABSL) {
1367 ++losing;
1368 } /* not absolute */
1369 break;
1370
1371 default:
1372 as_fatal("Internal error: Operand mode %c unknown in line %s of file \"%s\"",
1373 *s, __LINE__, __FILE__);
1374 } /* switch on type of operand */
1375
1376 if (losing) break;
1377 } /* for each operand */
1378 } /* if immediately wrong */
1379
1380 if (!losing) {
1381 break;
1382 } /* got it. */
1383
1384 opcode = opcode->m_next;
1385
1386 if (!opcode) {
1387 the_ins.error = "instruction/operands mismatch";
1388 return;
1389 } /* Fell off the end */
1390
1391 losing = 0;
1392 }
1393
1394 /* now assemble it */
1395
1396 the_ins.args=opcode->m_operands;
1397 the_ins.numargs=opcode->m_opnum;
1398 the_ins.numo=opcode->m_codenum;
1399 the_ins.opcode[0]=getone(opcode);
1400 the_ins.opcode[1]=gettwo(opcode);
1401
1402 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++) {
1403 /* This switch is a doozy.
1404 Watch the first step; its a big one! */
1405 switch(s[0]) {
1406
1407 case '*':
1408 case '~':
a39116f1 1409 case '%':
f8701a3f
SC		 1410 case ';':
1411 case '@':
1412 case '!':
a39116f1 1413 case '&':
f8701a3f
SC		 1414 case '$':
1415 case '?':
1416 case '/':
1417#ifndef NO_68851
1418 case '|':
1419#endif
1420 switch(opP->mode) {
1421 case IMMED:
1422 tmpreg=0x3c; /* 7.4 */
1423 if (strchr("bwl",s[1])) nextword=get_num(opP->con1,80);
1424 else nextword=nextword=get_num(opP->con1,0);
1425 if(isvar(opP->con1))
1426 add_fix(s[1],opP->con1,0);
1427 switch(s[1]) {
1428 case 'b':
1429 if(!isbyte(nextword))
1430 opP->error="operand out of range";
1431 addword(nextword);
1432 baseo=0;
1433 break;
1434 case 'w':
1435 if(!isword(nextword))
1436 opP->error="operand out of range";
1437 addword(nextword);
1438 baseo=0;
1439 break;
1440 case 'l':
1441 addword(nextword>>16);
1442 addword(nextword);
1443 baseo=0;
1444 break;
1445
1446 case 'f':
1447 baseo=2;
1448 outro=8;
1449 break;
1450 case 'F':
1451 baseo=4;
1452 outro=11;
1453 break;
1454 case 'x':
1455 baseo=6;
1456 outro=15;
1457 break;
1458 case 'p':
1459 baseo=6;
1460 outro= -1;
1461 break;
1462 default:
1463 as_fatal("Internal error: Can't decode %c%c in line %s of file \"%s\"",
1464 *s, s[1], __LINE__, __FILE__);
1465 }
1466 if(!baseo)
1467 break;
1468
1469 /* We gotta put out some float */
1470 if(seg(opP->con1)!=SEG_BIG) {
1471 int_to_gen(nextword);
1472 gen_to_words(words,baseo,(long int)outro);
1473 for(wordp=words;baseo--;wordp++)
1474 addword(*wordp);
1475 break;
1476 } /* Its BIG */
1477 if(offs(opP->con1)>0) {
1478 as_warn("Bignum assumed to be binary bit-pattern");
1479 if(offs(opP->con1)>baseo) {
1480 as_warn("Bignum too big for %c format; truncated",s[1]);
1481 offs(opP->con1)=baseo;
1482 }
1483 baseo-=offs(opP->con1);
1484 for(wordp=generic_bignum+offs(opP->con1)-1;offs(opP->con1)--;--wordp)
1485 addword(*wordp);
1486 while(baseo--)
1487 addword(0);
1488 break;
1489 }
1490 gen_to_words(words,baseo,(long)outro);
1491 for (wordp=words;baseo--;wordp++)
1492 addword(*wordp);
1493 break;
1494 case DREG:
1495 tmpreg=opP->reg-DATA; /* 0.dreg */
1496 break;
1497 case AREG:
1498 tmpreg=0x08+opP->reg-ADDR; /* 1.areg */
1499 break;
1500 case AINDR:
1501 tmpreg=0x10+opP->reg-ADDR; /* 2.areg */
1502 break;
1503 case ADEC:
1504 tmpreg=0x20+opP->reg-ADDR; /* 4.areg */
1505 break;
1506 case AINC:
1507 tmpreg=0x18+opP->reg-ADDR; /* 3.areg */
1508 break;
1509 case AOFF:
1510
1511 nextword=get_num(opP->con1,80);
1512 /* Force into index mode. Hope this works */
1513
1514 /* We do the first bit for 32-bit displacements,
1515 and the second bit for 16 bit ones. It is
1516 possible that we should make the default be
1517 WORD instead of LONG, but I think that'd
1518 break GCC, so we put up with a little
1519 inefficiency for the sake of working output.
1520 */
1521
1522 if( !issword(nextword)
1523 || ( isvar(opP->con1)
1524 && ( ( opP->con1->e_siz==0
1525 && flagseen['l']==0)
1526 || opP->con1->e_siz==3))) {
1527
1528 if(opP->reg==PC)
1529 tmpreg=0x3B; /* 7.3 */
1530 else
1531 tmpreg=0x30+opP->reg-ADDR; /* 6.areg */
1532 if(isvar(opP->con1)) {
1533 if(opP->reg==PC) {
1534 add_frag(adds(opP->con1),
1535 offs(opP->con1),
1536 TAB(PCLEA,SZ_UNDEF));
1537 break;
1538 } else {
1539 addword(0x0170);
1540 add_fix('l',opP->con1,1);
1541 }
1542 } else
1543 addword(0x0170);
1544 addword(nextword>>16);
1545 } else {
1546 if(opP->reg==PC)
1547 tmpreg=0x3A; /* 7.2 */
1548 else
1549 tmpreg=0x28+opP->reg-ADDR; /* 5.areg */
1550
1551 if(isvar(opP->con1)) {
1552 if(opP->reg==PC) {
1553 add_fix('w',opP->con1,1);
1554 } else
1555 add_fix('w',opP->con1,0);
1556 }
1557 }
1558 addword(nextword);
1559 break;
1560
1561 case APODX:
1562 case AMIND:
1563 case APRDX:
1564 know(current_architecture & m68020up);
1565 /* intentional fall-through */
1566 case AINDX:
1567 nextword=0;
1568 baseo=get_num(opP->con1,80);
1569 outro=get_num(opP->con2,80);
1570 /* Figure out the 'addressing mode' */
1571 /* Also turn on the BASE_DISABLE bit, if needed */
1572 if(opP->reg==PC || opP->reg==ZPC) {
1573 tmpreg=0x3b; /* 7.3 */
1574 if(opP->reg==ZPC)
1575 nextword|=0x80;
1576 } else if(opP->reg==FAIL) {
1577 nextword|=0x80;
1578 tmpreg=0x30; /* 6.garbage */
1579 } else tmpreg=0x30+opP->reg-ADDR; /* 6.areg */
1580
1581 siz1= (opP->con1) ? opP->con1->e_siz : 0;
1582 siz2= (opP->con2) ? opP->con2->e_siz : 0;
1583
1584 /* Index register stuff */
1585 if(opP->ireg>=DATA+0 && opP->ireg<=ADDR+7) {
1586 nextword|=(opP->ireg-DATA)<<12;
1587
1588 if(opP->isiz==0 || opP->isiz==3)
1589 nextword|=0x800;
1590 switch(opP->imul) {
1591 case 1: break;
1592 case 2: nextword|=0x200; break;
1593 case 4: nextword|=0x400; break;
1594 case 8: nextword|=0x600; break;
1595 default: as_fatal("failed sanity check.");
1596 }
1597 /* IF its simple,
1598 GET US OUT OF HERE! */
1599
1600 /* Must be INDEX, with an index
1601 register. Address register
1602 cannot be ZERO-PC, and either
1603 :b was forced, or we know
1604 it will fit */
1605 if( opP->mode==AINDX
1606 && opP->reg!=FAIL
1607 && opP->reg!=ZPC
1608 && ( siz1==1
1609 || ( issbyte(baseo)
1610 && !isvar(opP->con1)))) {
1611 nextword +=baseo&0xff;
1612 addword(nextword);
1613 if(isvar(opP->con1))
1614 add_fix('B',opP->con1,0);
1615 break;
1616 }
1617 } else
1618 nextword|=0x40; /* No index reg */
1619
1620 /* It aint simple */
1621 nextword|=0x100;
1622 /* If the guy specified a width, we assume that
1623 it is wide enough. Maybe it isn't. If so, we lose
1624 */
1625 switch(siz1) {
1626 case 0:
1627 if(isvar(opP->con1) || !issword(baseo)) {
1628 siz1=3;
1629 nextword|=0x30;
1630 } else if(baseo==0)
1631 nextword|=0x10;
1632 else {
1633 nextword|=0x20;
1634 siz1=2;
1635 }
1636 break;
1637 case 1:
1638 as_warn("Byte dispacement won't work. Defaulting to :w");
1639 case 2:
1640 nextword|=0x20;
1641 break;
1642 case 3:
1643 nextword|=0x30;
1644 break;
1645 }
1646
1647 /* Figure out innner displacement stuff */
1648 if(opP->mode!=AINDX) {
1649 switch(siz2) {
1650 case 0:
1651 if(isvar(opP->con2) || !issword(outro)) {
1652 siz2=3;
1653 nextword|=0x3;
1654 } else if(outro==0)
1655 nextword|=0x1;
1656 else {
1657 nextword|=0x2;
1658 siz2=2;
1659 }
1660 break;
1661 case 1:
1662 as_warn("Byte dispacement won't work. Defaulting to :w");
1663 case 2:
1664 nextword|=0x2;
1665 break;
1666 case 3:
1667 nextword|=0x3;
1668 break;
1669 }
1670 if(opP->mode==APODX) nextword|=0x04;
1671 else if(opP->mode==AMIND) nextword|=0x40;
1672 }
1673 addword(nextword);
1674
1675 if(isvar(opP->con1)) {
1676 if(opP->reg==PC || opP->reg==ZPC) {
1677 add_fix(siz1==3 ? 'l' : 'w',opP->con1,1);
1678 opP->con1->e_exp.X_add_number+=6;
1679 } else
1680 add_fix(siz1==3 ? 'l' : 'w',opP->con1,0);
1681 }
1682 if(siz1==3)
1683 addword(baseo>>16);
1684 if(siz1)
1685 addword(baseo);
1686
1687 if(isvar(opP->con2)) {
1688 if(opP->reg==PC || opP->reg==ZPC) {
1689 add_fix(siz2==3 ? 'l' : 'w',opP->con2,1);
1690 opP->con1->e_exp.X_add_number+=6;
1691 } else
1692 add_fix(siz2==3 ? 'l' : 'w',opP->con2,0);
1693 }
1694 if(siz2==3)
1695 addword(outro>>16);
1696 if(siz2)
1697 addword(outro);
1698
1699 break;
1700
1701 case ABSL:
1702 nextword=get_num(opP->con1,80);
1703 switch(opP->con1->e_siz) {
1704 default:
1705 as_warn("Unknown size for absolute reference");
1706 case 0:
1707 if(!isvar(opP->con1) && issword(offs(opP->con1))) {
1708 tmpreg=0x38; /* 7.0 */
1709 addword(nextword);
1710 break;
1711 }
1712 /* Don't generate pc relative code
1713 on 68010 and 68000 */
1714 if(isvar(opP->con1)
1715 && !subs(opP->con1)
1716 && seg(opP->con1) == SEG_TEXT
1717 && now_seg == SEG_TEXT
a1765cf0 1718 && cpu_of_arch(current_architecture) >= m68020
f8701a3f
SC		 1719 && !flagseen['S']
1720 && !strchr("~%&$?", s[0])) {
1721 tmpreg=0x3A; /* 7.2 */
1722 add_frag(adds(opP->con1),
1723 offs(opP->con1),
1724 TAB(PCREL,SZ_UNDEF));
1725 break;
1726 }
1727 case 3: /* Fall through into long */
1728 if(isvar(opP->con1))
1729 add_fix('l',opP->con1,0);
1730
1731 tmpreg=0x39; /* 7.1 mode */
1732 addword(nextword>>16);
1733 addword(nextword);
1734 break;
1735
1736 case 2: /* Word */
1737 if(isvar(opP->con1))
1738 add_fix('w',opP->con1,0);
1739
1740 tmpreg=0x38; /* 7.0 mode */
1741 addword(nextword);
1742 break;
1743 }
1744 break;
1745 case MSCR:
1746 default:
1747 as_bad("unknown/incorrect operand");
1748 /* abort(); */
1749 }
1750 install_gen_operand(s[1],tmpreg);
1751 break;
1752
1753 case '#':
1754 case '^':
1755 switch(s[1]) { /* JF: I hate floating point! */
1756 case 'j':
1757 tmpreg=70;
1758 break;
1759 case '8':
1760 tmpreg=20;
1761 break;
1762 case 'C':
1763 tmpreg=50;
1764 break;
1765 case '3':
1766 default:
1767 tmpreg=80;
1768 break;
1769 }
1770 tmpreg=get_num(opP->con1,tmpreg);
1771 if(isvar(opP->con1))
1772 add_fix(s[1],opP->con1,0);
1773 switch(s[1]) {
1774 case 'b': /* Danger: These do no check for
1775 certain types of overflow.
1776 user beware! */
1777 if(!isbyte(tmpreg))
1778 opP->error="out of range";
1779 insop(tmpreg);
1780 if(isvar(opP->con1))
1781 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
1782 break;
1783 case 'w':
1784 if(!isword(tmpreg))
1785 opP->error="out of range";
1786 insop(tmpreg);
1787 if(isvar(opP->con1))
1788 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
1789 break;
1790 case 'l':
1791 insop(tmpreg); /* Because of the way insop works, we put these two out backwards */
1792 insop(tmpreg>>16);
1793 if(isvar(opP->con1))
1794 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
1795 break;
1796 case '3':
1797 tmpreg&=0xFF;
1798 case '8':
1799 case 'C':
1800 install_operand(s[1],tmpreg);
1801 break;
1802 default:
1803 as_fatal("Internal error: Unknown mode #%c in line %s of file \"%s\"", s[1], __LINE__, __FILE__);
1804 }
1805 break;
1806
fecd2382
RP		 1807 case '+':
1808 case '-':
1809 case 'A':
7c15cbe8 1810 case 'a':
f8701a3f
SC		 1811 install_operand(s[1],opP->reg-ADDR);
1812 break;
1813
1814 case 'B':
1815 tmpreg=get_num(opP->con1,80);
1816 switch(s[1]) {
1817 case 'B':
1818 /* Needs no offsetting */
1819 add_fix('B',opP->con1,1);
1820 break;
1821 case 'W':
1822 /* Offset the displacement to be relative to byte disp location */
1823 opP->con1->e_exp.X_add_number+=2;
1824 add_fix('w',opP->con1,1);
1825 addword(0);
1826 break;
1827 case 'L':
1828 long_branch:
1829 if (cpu_of_arch(current_architecture) < m68020) /* 68000 or 010 */
1830 as_warn("Can't use long branches on 68000/68010");
1831 the_ins.opcode[the_ins.numo-1]|=0xff;
1832 /* Offset the displacement to be relative to byte disp location */
1833 opP->con1->e_exp.X_add_number+=4;
1834 add_fix('l',opP->con1,1);
1835 addword(0);
1836 addword(0);
1837 break;
1838 case 'g':
1839 if(subs(opP->con1)) /* We can't relax it */
1840 goto long_branch;
1841
1842 /* This could either be a symbol, or an
1843 absolute address. No matter, the
1844 frag hacking will finger it out.
1845 Not quite: it can't switch from
1846 BRANCH to BCC68000 for the case
1847 where opnd is absolute (it needs
1848 to use the 68000 hack since no
1849 conditional abs jumps). */
1850 if (((cpu_of_arch(current_architecture) < m68020) || (0==adds(opP->con1)))
1851 && (the_ins.opcode[0] >= 0x6200)
1852 && (the_ins.opcode[0] <= 0x6f00)) {
1853 add_frag(adds(opP->con1),offs(opP->con1),TAB(BCC68000,SZ_UNDEF));
1854 } else {
1855 add_frag(adds(opP->con1),offs(opP->con1),TAB(BRANCH,SZ_UNDEF));
1856 }
1857 break;
1858 case 'w':
1859 if(isvar(opP->con1)) {
1860 /* check for DBcc instruction */
1861 if ((the_ins.opcode[0] & 0xf0f8) ==0x50c8) {
1862 /* size varies if patch */
1863 /* needed for long form */
1864 add_frag(adds(opP->con1),offs(opP->con1),TAB(DBCC,SZ_UNDEF));
1865 break;
1866 }
1867
1868 /* Don't ask! */
1869 opP->con1->e_exp.X_add_number+=2;
1870 add_fix('w',opP->con1,1);
1871 }
1872 addword(0);
1873 break;
1874 case 'C': /* Fixed size LONG coproc branches */
1875 the_ins.opcode[the_ins.numo-1]|=0x40;
1876 /* Offset the displacement to be relative to byte disp location */
1877 /* Coproc branches don't have a byte disp option, but they are
1878 compatible with the ordinary branches, which do... */
1879 opP->con1->e_exp.X_add_number+=4;
1880 add_fix('l',opP->con1,1);
1881 addword(0);
1882 addword(0);
1883 break;
1884 case 'c': /* Var size Coprocesssor branches */
1885 if(subs(opP->con1)) {
1886 add_fix('l',opP->con1,1);
1887 add_frag((symbolS *)0,(long)0,TAB(FBRANCH,LONG));
1888 } else if(adds(opP->con1)) {
1889 add_frag(adds(opP->con1),offs(opP->con1),TAB(FBRANCH,SZ_UNDEF));
1890 } else {
1891 /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
1892 the_ins.opcode[the_ins.numo-1]|=0x40;
1893 add_fix('l',opP->con1,1);
1894 addword(0);
1895 addword(4);
1896 }
1897 break;
1898 default:
1899 as_fatal("Internal error: operand type B%c unknown in line %s of file \"%s\"",
1900 s[1], __LINE__, __FILE__);
1901 }
1902 break;
1903
1904 case 'C': /* Ignore it */
1905 break;
1906
1907 case 'd': /* JF this is a kludge */
1908 if(opP->mode==AOFF) {
1909 install_operand('s',opP->reg-ADDR);
1910 } else {
1911 char *tmpP;
1912
1913 tmpP=opP->con1->e_end-2;
1914 opP->con1->e_beg++;
1915 opP->con1->e_end-=4; /* point to the , */
1916 baseo=m68k_reg_parse(&tmpP);
1917 if(baseo<ADDR+0 || baseo>ADDR+7) {
1918 as_bad("Unknown address reg, using A0");
1919 baseo=0;
1920 } else baseo-=ADDR;
1921 install_operand('s',baseo);
1922 }
1923 tmpreg=get_num(opP->con1,80);
1924 if(!issword(tmpreg)) {
1925 as_warn("Expression out of range, using 0");
1926 tmpreg=0;
1927 }
1928 addword(tmpreg);
1929 break;
1930
fecd2382 1931 case 'D':
f8701a3f
SC		 1932 install_operand(s[1],opP->reg-DATA);
1933 break;
1934
fecd2382 1935 case 'F':
f8701a3f
SC		 1936 install_operand(s[1],opP->reg-FPREG);
1937 break;
1938
fecd2382 1939 case 'I':
f8701a3f
SC		 1940 tmpreg=1+opP->reg-COPNUM;
1941 if(tmpreg==8)
1942 tmpreg=0;
1943 install_operand(s[1],tmpreg);
1944 break;
1945
1946 case 'J': /* JF foo */
1947 switch(opP->reg) {
1948 case SFC: tmpreg=0x000; break;
1949 case DFC: tmpreg=0x001; break;
1950 case CACR: tmpreg=0x002; break;
1951 case TC: tmpreg=0x003; break;
1952 case ITT0: tmpreg=0x004; break;
1953 case ITT1: tmpreg=0x005; break;
1954 case DTT0: tmpreg=0x006; break;
1955 case DTT1: tmpreg=0x007; break;
1956
1957 case USP: tmpreg=0x800; break;
1958 case VBR: tmpreg=0x801; break;
1959 case CAAR: tmpreg=0x802; break;
1960 case MSP: tmpreg=0x803; break;
1961 case ISP: tmpreg=0x804; break;
1962 case MMUSR: tmpreg=0x805; break;
1963 case URP: tmpreg=0x806; break;
1964 case SRP: tmpreg=0x807; break;
1965 default:
1966 as_fatal("failed sanity check.");
1967 }
1968 install_operand(s[1],tmpreg);
1969 break;
1970
fecd2382 1971 case 'k':
f8701a3f
SC		 1972 tmpreg=get_num(opP->con1,55);
1973 install_operand(s[1],tmpreg&0x7f);
1974 break;
1975
fecd2382 1976 case 'l':
f8701a3f
SC		 1977 tmpreg=opP->reg;
1978 if(s[1]=='w') {
1979 if(tmpreg&0x7FF0000)
1980 as_bad("Floating point register in register list");
1981 insop(reverse_16_bits(tmpreg));
1982 } else {
1983 if(tmpreg&0x700FFFF)
1984 as_bad("Wrong register in floating-point reglist");
1985 install_operand(s[1],reverse_8_bits(tmpreg>>16));
1986 }
1987 break;
1988
fecd2382 1989 case 'L':
f8701a3f
SC		 1990 tmpreg=opP->reg;
1991 if(s[1]=='w') {
1992 if(tmpreg&0x7FF0000)
1993 as_bad("Floating point register in register list");
1994 insop(tmpreg);
1995 } else if(s[1]=='8') {
1996 if(tmpreg&0x0FFFFFF)
1997 as_bad("incorrect register in reglist");
1998 install_operand(s[1],tmpreg>>24);
1999 } else {
2000 if(tmpreg&0x700FFFF)
2001 as_bad("wrong register in floating-point reglist");
2002 else
2003 install_operand(s[1],tmpreg>>16);
fecd2382 2004 }
f8701a3f
SC		 2005 break;
2006
fecd2382 2007 case 'M':
f8701a3f
SC		 2008 install_operand(s[1],get_num(opP->con1,60));
2009 break;
7c15cbe8 2010
fecd2382 2011 case 'O':
f8701a3f
SC		 2012 tmpreg= (opP->mode==DREG)
2013 ? 0x20+opP->reg-DATA
2014 : (get_num(opP->con1,40)&0x1F);
2015 install_operand(s[1],tmpreg);
2016 break;
2017
fecd2382 2018 case 'Q':
f8701a3f
SC		 2019 tmpreg=get_num(opP->con1,10);
2020 if(tmpreg==8)
2021 tmpreg=0;
2022 install_operand(s[1],tmpreg);
2023 break;
7c15cbe8 2024
fecd2382 2025 case 'R':
f8701a3f
SC		 2026 /* This depends on the fact that ADDR registers are
2027 eight more than their corresponding DATA regs, so
2028 the result will have the ADDR_REG bit set */
2029 install_operand(s[1],opP->reg-DATA);
2030 break;
2031
fecd2382 2032 case 's':
f8701a3f
SC		 2033 if(opP->reg==FPI) tmpreg=0x1;
2034 else if(opP->reg==FPS) tmpreg=0x2;
2035 else if(opP->reg==FPC) tmpreg=0x4;
2036 else as_fatal("failed sanity check.");
2037 install_operand(s[1],tmpreg);
2038 break;
2039
2040 case 'S': /* Ignore it */
2041 break;
2042
2043 case 'T':
2044 install_operand(s[1],get_num(opP->con1,30));
2045 break;
2046
2047 case 'U': /* Ignore it */
2048 break;
2049
a39116f1 2050 case 'c':
f8701a3f
SC		 2051 switch (opP->reg) {
2052 case NC: tmpreg = 0; break;
2053 case DC: tmpreg = 1; break;
2054 case IC: tmpreg = 2; break;
2055 case BC: tmpreg = 3; break;
2056 default:
2057 as_fatal("failed sanity check");
2058 } /* switch on cache token */
2059 install_operand(s[1], tmpreg);
2060 break;
a39116f1 2061#ifndef NO_68851
f8701a3f 2062 /* JF: These are out of order, I fear. */
a39116f1 2063 case 'f':
f8701a3f
SC		 2064 switch (opP->reg) {
2065 case SFC:
2066 tmpreg=0;
2067 break;
2068 case DFC:
2069 tmpreg=1;
2070 break;
2071 default:
2072 as_fatal("failed sanity check.");
fecd2382 2073 }
f8701a3f 2074 install_operand(s[1],tmpreg);
fecd2382 2075 break;
f8701a3f
SC		 2076
2077 case 'P':
2078 switch(opP->reg) {
2079 case TC:
2080 tmpreg=0;
2081 break;
2082 case CAL:
2083 tmpreg=4;
2084 break;
2085 case VAL:
2086 tmpreg=5;
2087 break;
2088 case SCC:
2089 tmpreg=6;
2090 break;
2091 case AC:
2092 tmpreg=7;
2093 break;
2094 default:
2095 as_fatal("failed sanity check.");
a39116f1 2096 }
f8701a3f 2097 install_operand(s[1],tmpreg);
7c15cbe8 2098 break;
f8701a3f
SC		 2099
2100 case 'V':
2101 if (opP->reg == VAL)
2102 break;
2103 as_fatal("failed sanity check.");
2104
2105 case 'W':
2106 switch(opP->reg) {
2107
2108 case DRP:
2109 tmpreg=1;
2110 break;
2111 case SRP:
2112 tmpreg=2;
2113 break;
2114 case CRP:
2115 tmpreg=3;
2116 break;
2117 default:
2118 as_fatal("failed sanity check.");
2119 }
2120 install_operand(s[1],tmpreg);
7c15cbe8 2121 break;
f8701a3f
SC		 2122
2123 case 'X':
2124 switch (opP->reg) {
2125 case BAD: case BAD+1: case BAD+2: case BAD+3:
2126 case BAD+4: case BAD+5: case BAD+6: case BAD+7:
2127 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2128 break;
2129
2130 case BAC: case BAC+1: case BAC+2: case BAC+3:
2131 case BAC+4: case BAC+5: case BAC+6: case BAC+7:
2132 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2133 break;
2134
2135 default:
2136 as_fatal("failed sanity check.");
2137 }
2138 install_operand(s[1], tmpreg);
7c15cbe8 2139 break;
f8701a3f
SC		 2140 case 'Y':
2141 know(opP->reg == PSR);
a39116f1 2142 break;
f8701a3f
SC		 2143 case 'Z':
2144 know(opP->reg == PCSR);
a39116f1 2145 break;
f8701a3f
SC		 2146#endif /* m68851 */
2147 case '_':
2148 tmpreg=get_num(opP->con1,80);
2149 install_operand(s[1], tmpreg);
a39116f1 2150 break;
f8701a3f
SC		 2151 default:
2152 as_fatal("Internal error: Operand type %c unknown in line %s of file \"%s\"", s[0], __LINE__, __FILE__);
a39116f1 2153 }
fecd2382 2154 }
f8701a3f
SC		 2155 /* By the time whe get here (FINALLY) the_ins contains the complete
2156 instruction, ready to be emitted. . . */
7c15cbe8
RP		 2157} /* m68k_ip() */
2158
2159/*
2160 * get_regs := '/' + ?
2161 * | '-' + <register>
2162 * | '-' + <register> + ?
2163 * | <empty>
2164 * ;
2165 *
a39116f1 2166
7c15cbe8
RP		 2167 * The idea here must be to scan in a set of registers but I don't
2168 * understand it. Looks awfully sloppy to me but I don't have any doc on
2169 * this format so...
a39116f1 2170
7c15cbe8
RP		 2171 *
2172 *
2173 */
fecd2382
RP		 2174
2175static int get_regs(i,str,opP)
f8701a3f
SC		 2176int i;
2177struct m68k_op *opP;
2178char *str;
fecd2382 2179{
f8701a3f
SC		 2180 /* 26, 25, 24, 23-16, 15-8, 0-7 */
2181 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
2182 unsigned long cur_regs = 0;
2183 int reg1,
2184 reg2;
2185
fecd2382 2186#define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
a39116f1
RP		 2187else if(x==FPS) cur_regs|=(1<<25);\
2188else if(x==FPC) cur_regs|=(1<<26);\
2189else cur_regs|=(1<<(x-1)); }
f8701a3f
SC		 2190
2191 reg1=i;
2192 for(;;) {
2193 if(*str=='/') {
2194 ADD_REG(reg1);
2195 str++;
2196 } else if(*str=='-') {
2197 str++;
2198 reg2=m68k_reg_parse(&str);
2199 if(reg2<DATA || reg2>=FPREG+8 || reg1==FPI || reg1==FPS || reg1==FPC) {
2200 opP->error="unknown register in register list";
2201 return FAIL;
2202 }
2203 while(reg1<=reg2) {
2204 ADD_REG(reg1);
2205 reg1++;
2206 }
2207 if(*str=='\0')
2208 break;
2209 } else if(*str=='\0') {
2210 ADD_REG(reg1);
2211 break;
2212 } else {
2213 opP->error="unknow character in register list";
2214 return FAIL;
2215 }
2216 /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
2217 if (*str=='/')
2218 str ++;
2219 reg1=m68k_reg_parse(&str);
2220 if((reg1<DATA || reg1>=FPREG+8) && !(reg1==FPI || reg1==FPS || reg1==FPC)) {
2221 opP->error="unknown register in register list";
2222 return FAIL;
2223 }
a39116f1 2224 }
f8701a3f
SC		 2225 opP->reg=cur_regs;
2226 return OK;
fecd2382
RP		 2227} /* get_regs() */
2228
2229static int reverse_16_bits(in)
f8701a3f 2230int in;
fecd2382 2231{
f8701a3f
SC		 2232 int out=0;
2233 int n;
2234
2235 static int mask[16] = {
2236 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,
2237 0x0100,0x0200,0x0400,0x0800,0x1000,0x2000,0x4000,0x8000
2238 };
2239 for(n=0;n<16;n++) {
2240 if(in&mask[n])
2241 out|=mask[15-n];
2242 }
2243 return out;
fecd2382
RP		 2244} /* reverse_16_bits() */
2245
2246static int reverse_8_bits(in)
f8701a3f 2247int in;
fecd2382 2248{
f8701a3f
SC		 2249 int out=0;
2250 int n;
2251
2252 static int mask[8] = {
2253 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,
2254 };
2255
2256 for(n=0;n<8;n++) {
2257 if(in&mask[n])
2258 out|=mask[7-n];
2259 }
2260 return out;
fecd2382
RP		 2261} /* reverse_8_bits() */
2262
2263static void install_operand(mode,val)
f8701a3f
SC		 2264int mode;
2265int val;
fecd2382 2266{
f8701a3f
SC		 2267 switch(mode) {
2268 case 's':
2269 the_ins.opcode[0]|=val & 0xFF; /* JF FF is for M kludge */
2270 break;
2271 case 'd':
2272 the_ins.opcode[0]|=val<<9;
2273 break;
2274 case '1':
2275 the_ins.opcode[1]|=val<<12;
2276 break;
2277 case '2':
2278 the_ins.opcode[1]|=val<<6;
2279 break;
2280 case '3':
2281 the_ins.opcode[1]|=val;
2282 break;
2283 case '4':
2284 the_ins.opcode[2]|=val<<12;
2285 break;
2286 case '5':
2287 the_ins.opcode[2]|=val<<6;
2288 break;
2289 case '6':
2290 /* DANGER! This is a hack to force cas2l and cas2w cmds
2291 to be three words long! */
2292 the_ins.numo++;
2293 the_ins.opcode[2]|=val;
2294 break;
2295 case '7':
2296 the_ins.opcode[1]|=val<<7;
2297 break;
2298 case '8':
2299 the_ins.opcode[1]|=val<<10;
2300 break;
2301#ifndef NO_68851
2302 case '9':
2303 the_ins.opcode[1]|=val<<5;
2304 break;
2305#endif
2306
2307 case 't':
2308 the_ins.opcode[1]|=(val<<10)|(val<<7);
2309 break;
2310 case 'D':
2311 the_ins.opcode[1]|=(val<<12)|val;
2312 break;
2313 case 'g':
2314 the_ins.opcode[0]|=val=0xff;
2315 break;
2316 case 'i':
2317 the_ins.opcode[0]|=val<<9;
2318 break;
2319 case 'C':
2320 the_ins.opcode[1]|=val;
2321 break;
2322 case 'j':
2323 the_ins.opcode[1]|=val;
2324 the_ins.numo++; /* What a hack */
2325 break;
2326 case 'k':
2327 the_ins.opcode[1]|=val<<4;
2328 break;
2329 case 'b':
2330 case 'w':
2331 case 'l':
2332 break;
2333 case 'e':
2334 the_ins.opcode[0] |= (val << 6);
2335 break;
2336 case 'L':
2337 the_ins.opcode[1] = (val >> 16);
2338 the_ins.opcode[2] = val & 0xffff;
2339 break;
2340 case 'c':
2341 default:
2342 as_fatal("failed sanity check.");
2343 }
fecd2382
RP		 2344} /* install_operand() */
2345
2346static void install_gen_operand(mode,val)
f8701a3f
SC		 2347int mode;
2348int val;
fecd2382 2349{
f8701a3f
SC		 2350 switch(mode) {
2351 case 's':
2352 the_ins.opcode[0]|=val;
2353 break;
2354 case 'd':
2355 /* This is a kludge!!! */
2356 the_ins.opcode[0]|=(val&0x07)<<9|(val&0x38)<<3;
2357 break;
2358 case 'b':
2359 case 'w':
2360 case 'l':
2361 case 'f':
2362 case 'F':
2363 case 'x':
2364 case 'p':
2365 the_ins.opcode[0]|=val;
2366 break;
2367 /* more stuff goes here */
2368 default:
2369 as_fatal("failed sanity check.");
2370 }
fecd2382
RP		 2371} /* install_gen_operand() */
2372
7c15cbe8
RP		 2373/*
2374 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2375 * then deal with the bitfield hack.
2376 */
2377
fecd2382 2378static char *crack_operand(str,opP)
f8701a3f
SC		 2379register char *str;
2380register struct m68k_op *opP;
fecd2382 2381{
f8701a3f
SC		 2382 register int parens;
2383 register int c;
2384 register char *beg_str;
2385
2386 if(!str) {
2387 return str;
2388 }
2389 beg_str=str;
2390 for(parens=0;*str && (parens>0 || notend(str));str++) {
2391 if(*str=='(') parens++;
2392 else if(*str==')') {
2393 if(!parens) { /* ERROR */
2394 opP->error="Extra )";
2395 return str;
2396 }
2397 --parens;
2398 }
2399 }
2400 if(!*str && parens) { /* ERROR */
2401 opP->error="Missing )";
2402 return str;
2403 }
2404 c= *str;
2405 *str='\0';
2406 if(m68k_ip_op(beg_str,opP)==FAIL) {
2407 *str=c;
fecd2382
RP		 2408 return str;
2409 }
2410 *str=c;
f8701a3f
SC		 2411 if(c=='}')
2412 c= *++str; /* JF bitfield hack */
2413 if(c) {
2414 c= *++str;
2415 if(!c)
2416 as_bad("Missing operand");
2417 }
fecd2382
RP		 2418 return str;
2419}
2420
2421/* See the comment up above where the #define notend(... is */
2422#if 0
2423notend(s)
f8701a3f 2424char *s;
fecd2382 2425{
f8701a3f
SC		 2426 if(*s==',') return 0;
2427 if(*s=='{' || *s=='}')
2428 return 0;
2429 if(*s!=':') return 1;
2430 /* This kludge here is for the division cmd, which is a kludge */
2431 if(index("aAdD#",s[1])) return 0;
2432 return 1;
fecd2382
RP		 2433}
2434#endif
2435
2436/* This is the guts of the machine-dependent assembler. STR points to a
7c15cbe8 2437 machine dependent instruction. This function is supposed to emit
fecd2382 2438 the frags/bytes it assembles to.
a39116f1 2439 */
a933d598
SC		 2440
2441void
2442insert_reg(regname, regnum)
2443char *regname;
2444int regnum;
2445{
2446 char buf[100];
2447 int i;
2448 symbol_table_insert(symbol_new(regname, SEG_REGISTER, regnum, &zero_address_frag));
2449
2450 for (i = 0; regname[i]; i++)
2451 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2452 buf[i] = '\0';
2453
2454 symbol_table_insert(symbol_new(buf, SEG_REGISTER, regnum, &zero_address_frag));
2455}
2456
2457static struct {
2458char *name;
2459int number;
2460} init_table[] =
2461{
2462 "d0", DATA0,
2463 "d1", DATA1,
2464 "d2", DATA2,
2465 "d3", DATA3,
2466 "d4", DATA4,
2467 "d5", DATA5,
2468 "d6", DATA6,
2469 "d7", DATA7,
2470 "a0", ADDR0,
2471 "a1", ADDR1,
2472 "a2", ADDR2,
2473 "a3", ADDR3,
2474 "a4", ADDR4,
2475 "a5", ADDR5,
2476 "a6", ADDR6,
2477 "fp", ADDR6,
2478 "a7", ADDR7,
2479 "sp", ADDR7,
2480 "fp0", FP0,
2481 "fp1", FP1,
2482 "fp2", FP2,
2483 "fp3", FP3,
2484 "fp4", FP4,
2485 "fp5", FP5,
2486 "fp6", FP6,
2487 "fp7", FP7,
2488 "fpi", FPI,
2489 "fpiar", FPI,
2490 "fpc", FPI,
2491 "fps", FPS,
2492 "fpsr", FPS,
2493 "fpc", FPC,
2494 "fpcr", FPC,
2495
2496 "cop0", COP0,
2497 "cop1", COP1,
2498 "cop2", COP2,
2499 "cop3", COP3,
2500 "cop4", COP4,
2501 "cop5", COP5,
2502 "cop6", COP6,
2503 "cop7", COP7,
2504 "pc", PC,
2505 "zpc", ZPC,
2506 "sr", SR,
2507
2508 "ccr", CCR,
2509 "cc", CCR,
2510
2511 "usp", USP,
2512 "isp", ISP,
2513 "sfc", SFC,
2514 "dfc", DFC,
2515 "cacr", CACR,
2516 "caar", CAAR,
2517
2518 "vbr", VBR,
2519
2520 "msp", MSP,
2521 "itt0", ITT0,
2522 "itt1", ITT1,
2523 "dtt0", DTT0,
2524 "dtt1", DTT1,
2525 "mmusr", MMUSR,
2526 "tc", TC,
2527 "srp", SRP,
2528 "urp", URP,
2529
2530#ifndef NO_68851
2531 "ac", AC,
2532 "bc", BC,
2533 "cal", CAL,
2534 "crp", CRP,
2535 "drp", DRP,
2536 "pcsr", PCSR,
2537 "psr", PSR,
2538 "scc", SCC,
2539 "val", VAL,
2540 "bad0", BAD0,
2541 "bad1", BAD1,
2542 "bad2", BAD2,
2543 "bad3", BAD3,
2544 "bad4", BAD4,
2545 "bad5", BAD5,
2546 "bad6", BAD6,
2547 "bad7", BAD7,
2548 "bac0", BAC0,
2549 "bac1", BAC1,
2550 "bac2", BAC2,
2551 "bac3", BAC3,
2552 "bac4", BAC4,
2553 "bac5", BAC5,
2554 "bac6", BAC6,
2555 "bac7", BAC7,
2556#endif
2557
2558 "ic", IC,
2559 "dc", DC,
2560 "nc", NC,
2561
2562 0,
2563
2564};
2565
2566
2567void
2568init_regtable()
2569{
2570 int i;
2571 for (i = 0; init_table[i].name; i++)
2572 {
2573 insert_reg(init_table[i].name, init_table[i].number);
2574 }
2575}
2576
2577
fecd2382 2578void
a39116f1 2579 md_assemble(str)
fecd2382
RP		 2580char *str;
2581{
f8701a3f
SC		 2582 char *er;
2583 short *fromP;
2584 char *toP = NULL;
2585 int m,n = 0;
2586 char *to_beg_P;
2587 int shorts_this_frag;
2588
2589
2590 if (current_architecture == 0) {
2591 current_architecture = (m68020
865a2edf 2592#ifndef NO_68881
f8701a3f 2593 | m68881
865a2edf
MT		 2594#endif
2595#ifndef NO_68851
f8701a3f 2596 | m68851
865a2edf 2597#endif
f8701a3f
SC		 2598 );
2599 } /* default current_architecture */
2600
2601 memset((char *)(&the_ins), '\0', sizeof(the_ins)); /* JF for paranoia sake */
2602 m68k_ip(str);
2603 er=the_ins.error;
2604 if(!er) {
2605 for(n=the_ins.numargs;n;--n)
2606 if(the_ins.operands[n].error) {
2607 er=the_ins.operands[n].error;
2608 break;
2609 }
fecd2382 2610 }
f8701a3f
SC		 2611 if(er) {
2612 as_bad("\"%s\" -- Statement '%s' ignored",er,str);
2613 return;
fecd2382 2614 }
f8701a3f
SC		 2615
2616 if(the_ins.nfrag==0) { /* No frag hacking involved; just put it out */
2617 toP=frag_more(2*the_ins.numo);
2618 fromP= &the_ins.opcode[0];
2619 for(m=the_ins.numo;m;--m) {
2620 md_number_to_chars(toP,(long)(*fromP),2);
2621 toP+=2;
2622 fromP++;
2623 }
2624 /* put out symbol-dependent info */
2625 for(m=0;m<the_ins.nrel;m++) {
2626 switch(the_ins.reloc[m].wid) {
2627 case 'B':
2628 n=1;
2629 break;
2630 case 'b':
2631 n=1;
2632 break;
2633 case '3':
2634 n=2;
2635 break;
2636 case 'w':
2637 n=2;
2638 break;
2639 case 'l':
2640 n=4;
2641 break;
2642 default:
2643 as_fatal("Don't know how to figure width of %c in md_assemble()",the_ins.reloc[m].wid);
2644 }
2645
2646 fix_new(frag_now,
2647 (toP-frag_now->fr_literal)-the_ins.numo*2+the_ins.reloc[m].n,
2648 n,
2649 the_ins.reloc[m].add,
2650 the_ins.reloc[m].sub,
2651 the_ins.reloc[m].off,
2652 the_ins.reloc[m].pcrel,
2653 NO_RELOC);
2654 }
2655 return;
2656 }
2657
2658 /* There's some frag hacking */
2659 for(n=0,fromP= &the_ins.opcode[0];n<the_ins.nfrag;n++) {
2660 int wid;
2661
2662 if(n==0) wid=2*the_ins.fragb[n].fragoff;
2663 else wid=2*(the_ins.numo-the_ins.fragb[n-1].fragoff);
2664 toP=frag_more(wid);
2665 to_beg_P=toP;
2666 shorts_this_frag=0;
2667 for(m=wid/2;m;--m) {
2668 md_number_to_chars(toP,(long)(*fromP),2);
2669 toP+=2;
2670 fromP++;
2671 shorts_this_frag++;
2672 }
2673 for(m=0;m<the_ins.nrel;m++) {
2674 if((the_ins.reloc[m].n)>= 2*shorts_this_frag /* 2*the_ins.fragb[n].fragoff */) {
2675 the_ins.reloc[m].n-= 2*shorts_this_frag /* 2*the_ins.fragb[n].fragoff */;
2676 break;
2677 }
2678 wid=the_ins.reloc[m].wid;
2679 if(wid==0)
2680 continue;
2681 the_ins.reloc[m].wid=0;
2682 wid = (wid=='b') ? 1 : (wid=='w') ? 2 : (wid=='l') ? 4 : 4000;
2683
2684 fix_new(frag_now,
2685 (toP-frag_now->fr_literal)-the_ins.numo*2+the_ins.reloc[m].n,
2686 wid,
2687 the_ins.reloc[m].add,
2688 the_ins.reloc[m].sub,
2689 the_ins.reloc[m].off,
2690 the_ins.reloc[m].pcrel,
2691 NO_RELOC);
2692 }
2693 /* know(the_ins.fragb[n].fadd); */
2694 (void)frag_var(rs_machine_dependent,10,0,(relax_substateT)(the_ins.fragb[n].fragty),
2695 the_ins.fragb[n].fadd,the_ins.fragb[n].foff,to_beg_P);
2696 }
2697 n=(the_ins.numo-the_ins.fragb[n-1].fragoff);
fecd2382 2698 shorts_this_frag=0;
f8701a3f
SC		 2699 if(n) {
2700 toP=frag_more(n*sizeof(short));
2701 while(n--) {
2702 md_number_to_chars(toP,(long)(*fromP),2);
2703 toP+=2;
2704 fromP++;
2705 shorts_this_frag++;
2706 }
fecd2382
RP		 2707 }
2708 for(m=0;m<the_ins.nrel;m++) {
f8701a3f
SC		 2709 int wid;
2710
2711 wid=the_ins.reloc[m].wid;
2712 if(wid==0)
2713 continue;
2714 the_ins.reloc[m].wid=0;
2715 wid = (wid=='b') ? 1 : (wid=='w') ? 2 : (wid=='l') ? 4 : 4000;
2716
2717 fix_new(frag_now,
2718 (the_ins.reloc[m].n + toP-frag_now->fr_literal)-/* the_ins.numo */ shorts_this_frag*2,
2719 wid,
2720 the_ins.reloc[m].add,
2721 the_ins.reloc[m].sub,
2722 the_ins.reloc[m].off,
2723 the_ins.reloc[m].pcrel,
2724 NO_RELOC);
fecd2382
RP		 2725 }
2726}
2727
2728/* This function is called once, at assembler startup time. This should
2729 set up all the tables, etc that the MD part of the assembler needs
a39116f1 2730 */
f8701a3f
SC		 2731
2732void
2733insert_reg(regname, regnum)
2734char *regname;
2735int regnum;
2736{
2737 char buf[100];
2738 int i;
2739 symbol_table_insert(symbol_new(regname, SEG_REGISTER, regnum, &zero_address_frag));
2740
2741 for (i = 0; regname[i]; i++)
2742 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2743 buf[i] = '\0';
2744
2745 symbol_table_insert(symbol_new(buf, SEG_REGISTER, regnum, &zero_address_frag));
2746}
2747
2748static struct {
2749char *name;
2750int number;
2751} init_table[] =
2752{
2753 "d0", DATA0,
2754 "d1", DATA1,
2755 "d2", DATA2,
2756 "d3", DATA3,
2757 "d4", DATA4,
2758 "d5", DATA5,
2759 "d6", DATA6,
2760 "d7", DATA7,
2761 "a0", ADDR0,
2762 "a1", ADDR1,
2763 "a2", ADDR2,
2764 "a3", ADDR3,
2765 "a4", ADDR4,
2766 "a5", ADDR5,
2767 "a6", ADDR6,
2768 "fp", ADDR6,
2769 "a7", ADDR7,
2770 "sp", ADDR7,
2771 "fp0", FP0,
2772 "fp1", FP1,
2773 "fp2", FP2,
2774 "fp3", FP3,
2775 "fp4", FP4,
2776 "fp5", FP5,
2777 "fp6", FP6,
2778 "fp7", FP7,
2779 "fpi", FPI,
2780 "fps", FPS,
2781 "fpc", FPC,
2782
2783 "cop0", COP0,
2784 "cop1", COP1,
2785 "cop2", COP2,
2786 "cop3", COP3,
2787 "cop4", COP4,
2788 "cop5", COP5,
2789 "cop6", COP6,
2790 "cop7", COP7,
2791 "pc", PC,
2792 "zpc", ZPC,
2793 "sr", SR,
2794
2795 "ccr", CCR,
2796 "cc", CCR,
2797
2798 "usp", USP,
2799 "isp", ISP,
2800 "sfc", SFC,
2801 "dfc", DFC,
2802 "cacr", CACR,
2803 "caar", CAAR,
2804
2805 "vbr", VBR,
2806
2807 "msp", MSP,
2808 "itt0", ITT0,
2809 "itt1", ITT1,
2810 "dtt0", DTT0,
2811 "dtt1", DTT1,
2812 "mmusr", MMUSR,
2813 "tc", TC,
2814 "srp", SRP,
2815 "urp", URP,
2816
2817#ifndef NO_68851
2818 "ac", AC,
2819 "bc", BC,
2820 "cal", CAL,
2821 "crp", CRP,
2822 "drp", DRP,
2823 "pcsr", PCSR,
2824 "psr", PSR,
2825 "scc", SCC,
2826 "val", VAL,
2827 "bad0", BAD0,
2828 "bad1", BAD1,
2829 "bad2", BAD2,
2830 "bad3", BAD3,
2831 "bad4", BAD4,
2832 "bad5", BAD5,
2833 "bad6", BAD6,
2834 "bad7", BAD7,
2835 "bac0", BAC0,
2836 "bac1", BAC1,
2837 "bac2", BAC2,
2838 "bac3", BAC3,
2839 "bac4", BAC4,
2840 "bac5", BAC5,
2841 "bac6", BAC6,
2842 "bac7", BAC7,
2843#endif
2844
2845 "ic", IC,
2846 "dc", DC,
2847 "nc", NC,
2848
2849 0,
2850
2851};
2852
2853
2854void
2855init_regtable()
2856{
2857 int i;
2858 for (i = 0; init_table[i].name; i++)
2859 {
2860 insert_reg(init_table[i].name, init_table[i].number);
2861 }
2862}
2863
2864
fecd2382 2865void
a39116f1 2866 md_begin()
fecd2382 2867{
f8701a3f
SC		 2868 /*
2869 * md_begin -- set up hash tables with 68000 instructions.
2870 * similar to what the vax assembler does. ---phr
2871 */
2872 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
2873 a copy of it at runtime, adding in the information we want but isn't
2874 there. I think it'd be better to have an awk script hack the table
2875 at compile time. Or even just xstr the table and use it as-is. But
2876 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
2877 names. */
2878
2879 register const struct m68k_opcode *ins;
2880 register struct m68k_incant *hack,
2881 *slak;
2882 register char *retval = 0; /* empty string, or error msg text */
2883 register unsigned int i;
2884 register char c;
2885
2886 if ((op_hash = hash_new()) == NULL)
2887 as_fatal("Virtual memory exhausted");
2888
2889 obstack_begin(&robyn,4000);
2890 for (ins = m68k_opcodes; ins < endop; ins++) {
2891 hack=slak=(struct m68k_incant *)obstack_alloc(&robyn,sizeof(struct m68k_incant));
2892 do {
2893 /* we *could* ignore insns that don't match our
2894 arch here but just leaving them out of the
2895 hash. */
2896 slak->m_operands=ins->args;
2897 slak->m_opnum=strlen(slak->m_operands)/2;
2898 slak->m_arch = ins->arch;
2899 slak->m_opcode=ins->opcode;
2900 /* This is kludgey */
2901 slak->m_codenum=((ins->match)&0xffffL) ? 2 : 1;
2902 if((ins+1)!=endop && !strcmp(ins->name,(ins+1)->name)) {
2903 slak->m_next=(struct m68k_incant *) obstack_alloc(&robyn,sizeof(struct m68k_incant));
2904 ins++;
2905 } else
2906 slak->m_next=0;
2907 slak=slak->m_next;
2908 } while(slak);
2909
2910 retval = hash_insert (op_hash, ins->name,(char *)hack);
2911 /* Didn't his mommy tell him about null pointers? */
2912 if(retval && *retval)
2913 as_fatal("Internal Error: Can't hash %s: %s",ins->name,retval);
2914 }
2915
2916 for (i = 0; i < sizeof(mklower_table) ; i++)
2917 mklower_table[i] = (isupper(c = (char) i)) ? tolower(c) : c;
2918
2919 for (i = 0 ; i < sizeof(notend_table) ; i++) {
2920 notend_table[i] = 0;
2921 alt_notend_table[i] = 0;
2922 }
2923 notend_table[','] = 1;
2924 notend_table['{'] = 1;
2925 notend_table['}'] = 1;
2926 alt_notend_table['a'] = 1;
2927 alt_notend_table['A'] = 1;
2928 alt_notend_table['d'] = 1;
2929 alt_notend_table['D'] = 1;
2930 alt_notend_table['#'] = 1;
2931 alt_notend_table['f'] = 1;
2932 alt_notend_table['F'] = 1;
fecd2382 2933#ifdef REGISTER_PREFIX
f8701a3f 2934 alt_notend_table[REGISTER_PREFIX] = 1;
fecd2382 2935#endif
f8701a3f
SC		 2936
2937 init_regtable();
fecd2382
RP		 2938}
2939
2940#if 0
2941#define notend(s) ((*s == ',' || *s == '}' || *s == '{' \
a39116f1
RP		 2942 || (*s == ':' && strchr("aAdD#", s[1]))) \
2943 ? 0 : 1)
fecd2382
RP		 2944#endif
2945
2946/* This funciton is called once, before the assembler exits. It is
2947 supposed to do any final cleanup for this part of the assembler.
a39116f1 2948 */
fecd2382 2949void
a39116f1 2950 md_end()
fecd2382
RP		 2951{
2952}
2953
2954/* Equal to MAX_PRECISION in atof-ieee.c */
2955#define MAX_LITTLENUMS 6
2956
2957/* Turn a string in input_line_pointer into a floating point constant of type
2958 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
2959 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
a39116f1 2960 */
fecd2382 2961char *
a39116f1 2962 md_atof(type,litP,sizeP)
fecd2382
RP		 2963char type;
2964char *litP;
2965int *sizeP;
2966{
f8701a3f
SC		 2967 int prec;
2968 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2969 LITTLENUM_TYPE *wordP;
2970 char *t;
2971 char *atof_ieee();
a39116f1 2972
f8701a3f
SC		 2973 switch(type) {
2974 case 'f':
2975 case 'F':
2976 case 's':
2977 case 'S':
2978 prec = 2;
2979 break;
2980
2981 case 'd':
2982 case 'D':
2983 case 'r':
2984 case 'R':
2985 prec = 4;
2986 break;
2987
2988 case 'x':
2989 case 'X':
2990 prec = 6;
2991 break;
2992
2993 case 'p':
2994 case 'P':
2995 prec = 6;
2996 break;
2997
2998 default:
2999 *sizeP=0;
3000 return "Bad call to MD_ATOF()";
3001 }
3002 t=atof_ieee(input_line_pointer,type,words);
3003 if(t)
3004 input_line_pointer=t;
a39116f1 3005
f8701a3f
SC		 3006 *sizeP=prec * sizeof(LITTLENUM_TYPE);
3007 for(wordP=words;prec--;) {
3008 md_number_to_chars(litP,(long)(*wordP++),sizeof(LITTLENUM_TYPE));
3009 litP+=sizeof(LITTLENUM_TYPE);
3010 }
3011 return ""; /* Someone should teach Dean about null pointers */
fecd2382
RP		 3012}
3013
3014/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
3015 for use in the a.out file, and stores them in the array pointed to by buf.
3016 This knows about the endian-ness of the target machine and does
3017 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
3018 2 (short) and 4 (long) Floating numbers are put out as a series of
3019 LITTLENUMS (shorts, here at least)
a39116f1 3020 */
fecd2382 3021void
a39116f1 3022 md_number_to_chars(buf,val,n)
fecd2382
RP		 3023char *buf;
3024long val;
3025int n;
3026{
f8701a3f
SC		 3027 switch(n) {
3028 case 1:
3029 *buf++=val;
3030 break;
3031 case 2:
3032 *buf++=(val>>8);
3033 *buf++=val;
3034 break;
3035 case 4:
3036 *buf++=(val>>24);
3037 *buf++=(val>>16);
3038 *buf++=(val>>8);
3039 *buf++=val;
3040 break;
3041 default:
3042 as_fatal("failed sanity check.");
3043 }
fecd2382
RP		 3044}
3045
3046void
a39116f1
RP		 3047 md_apply_fix(fixP, val)
3048fixS *fixP;
3049long val;
fecd2382 3050{
f8701a3f
SC		 3051 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3052
3053 switch(fixP->fx_size) {
3054 case 1:
3055 *buf++=val;
3056 break;
3057 case 2:
3058 *buf++=(val>>8);
3059 *buf++=val;
3060 break;
3061 case 4:
3062 *buf++=(val>>24);
3063 *buf++=(val>>16);
3064 *buf++=(val>>8);
3065 *buf++=val;
3066 break;
3067 default:
3068 BAD_CASE (fixP->fx_size);
3069 }
fecd2382
RP		 3070}
3071
3072
3073/* *fragP has been relaxed to its final size, and now needs to have
3074 the bytes inside it modified to conform to the new size There is UGLY
3075 MAGIC here. ..
a39116f1 3076 */
fecd2382 3077void
a39116f1 3078 md_convert_frag(headers, fragP)
f6e504fe 3079object_headers *headers;
fecd2382
RP		 3080register fragS *fragP;
3081{
f8701a3f
SC		 3082 long disp;
3083 long ext = 0;
3084
3085 /* Address in object code of the displacement. */
3086 register int object_address = fragP -> fr_fix + fragP -> fr_address;
3087
f6e504fe 3088#ifdef IBM_COMPILER_SUX
f8701a3f
SC		 3089 /* This is wrong but it convinces the native rs6000 compiler to
3090 generate the code we want. */
3091 register char *buffer_address = fragP -> fr_literal;
3092 buffer_address += fragP -> fr_fix;
f6e504fe 3093#else /* IBM_COMPILER_SUX */
f8701a3f
SC		 3094 /* Address in gas core of the place to store the displacement. */
3095 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
f6e504fe 3096#endif /* IBM_COMPILER_SUX */
f8701a3f
SC		 3097
3098 /* No longer true: know(fragP->fr_symbol); */
3099
3100 /* The displacement of the address, from current location. */
3101 disp = fragP->fr_symbol ? S_GET_VALUE(fragP->fr_symbol) : 0;
3102 disp = (disp + fragP->fr_offset) - object_address;
3103
3104 switch(fragP->fr_subtype) {
3105 case TAB(BCC68000,BYTE):
a39116f1
RP		 3106 case TAB(BRANCH,BYTE):
3107 know(issbyte(disp));
3108 if(disp==0)
3109 as_bad("short branch with zero offset: use :w");
3110 fragP->fr_opcode[1]=disp;
fecd2382 3111 ext=0;
a39116f1 3112 break;
f8701a3f
SC		 3113 case TAB(DBCC,SHORT):
3114 know(issword(disp));
a39116f1
RP		 3115 ext=2;
3116 break;
f8701a3f
SC		 3117 case TAB(BCC68000,SHORT):
3118 case TAB(BRANCH,SHORT):
3119 know(issword(disp));
a39116f1
RP		 3120 fragP->fr_opcode[1]=0x00;
3121 ext=2;
3122 break;
f8701a3f
SC		 3123 case TAB(BRANCH,LONG):
3124 if (cpu_of_arch(current_architecture) < m68020) {
3125 if (fragP->fr_opcode[0]==0x61) {
3126 fragP->fr_opcode[0]= 0x4E;
3127 fragP->fr_opcode[1]= 0xB9; /* JBSR with ABSL LONG offset */
3128 subseg_change(SEG_TEXT, 0);
3129
3130 fix_new(fragP,
3131 fragP->fr_fix,
3132 4,
3133 fragP->fr_symbol,
3134 0,
3135 fragP->fr_offset,
3136 0,
3137 NO_RELOC);
3138
3139 fragP->fr_fix+=4;
3140 ext=0;
3141 } else if (fragP->fr_opcode[0]==0x60) {
3142 fragP->fr_opcode[0]= 0x4E;
3143 fragP->fr_opcode[1]= 0xF9; /* JMP with ABSL LONG offset */
3144 subseg_change(SEG_TEXT, 0);
3145 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset,0,
3146 NO_RELOC);
3147 fragP->fr_fix+=4;
3148 ext=0;
3149 } else {
3150 as_bad("Long branch offset not supported.");
3151 }
3152 } else {
3153 fragP->fr_opcode[1]=0xff;
3154 ext=4;
3155 }
3156 break;
3157 case TAB(BCC68000,LONG):
3158 /* only Bcc 68000 instructions can come here */
3159 /* change bcc into b!cc/jmp absl long */
3160 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
fecd2382 3161 fragP->fr_opcode[1] = 0x6; /* branch offset = 6 */
a39116f1 3162
fecd2382
RP		 3163 /* JF: these used to be fr_opcode[2,3], but they may be in a
3164 different frag, in which case refering to them is a no-no.
3165 Only fr_opcode[0,1] are guaranteed to work. */
3166 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3167 *buffer_address++ = 0xf9;
3168 fragP->fr_fix += 2; /* account for jmp instruction */
3169 subseg_change(SEG_TEXT,0);
3170 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
a39116f1
RP		 3171 fragP->fr_offset,0,
3172 NO_RELOC);
fecd2382
RP		 3173 fragP->fr_fix += 4;
3174 ext=0;
3175 break;
f8701a3f
SC		 3176 case TAB(DBCC,LONG):
3177 /* only DBcc 68000 instructions can come here */
3178 /* change dbcc into dbcc/jmp absl long */
3179 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3180 *buffer_address++ = 0x00; /* branch offset = 4 */
fecd2382
RP		 3181 *buffer_address++ = 0x04;
3182 *buffer_address++ = 0x60; /* put in bra pc+6 */
3183 *buffer_address++ = 0x06;
3184 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3185 *buffer_address++ = 0xf9;
a39116f1 3186
fecd2382
RP		 3187 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3188 subseg_change(SEG_TEXT,0);
3189 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
a39116f1
RP		 3190 fragP->fr_offset,0,
3191 NO_RELOC);
fecd2382
RP		 3192 fragP->fr_fix += 4;
3193 ext=0;
a39116f1 3194 break;
f8701a3f
SC		 3195 case TAB(FBRANCH,SHORT):
3196 know((fragP->fr_opcode[1]&0x40)==0);
a39116f1
RP		 3197 ext=2;
3198 break;
f8701a3f
SC		 3199 case TAB(FBRANCH,LONG):
3200 fragP->fr_opcode[1]|=0x40; /* Turn on LONG bit */
a39116f1
RP		 3201 ext=4;
3202 break;
f8701a3f
SC		 3203 case TAB(PCREL,SHORT):
3204 ext=2;
a39116f1 3205 break;
f8701a3f
SC		 3206 case TAB(PCREL,LONG):
3207 /* The thing to do here is force it to ABSOLUTE LONG, since
3208 PCREL is really trying to shorten an ABSOLUTE address anyway */
3209 /* JF FOO This code has not been tested */
3210 subseg_change(SEG_TEXT,0);
a39116f1
RP		 3211 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3212 if((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3213 as_bad("Internal error (long PC-relative operand) for insn 0x%04lx at 0x%lx",
3214 fragP->fr_opcode[0],fragP->fr_address);
3215 fragP->fr_opcode[1]&= ~0x3F;
3216 fragP->fr_opcode[1]|=0x39; /* Mode 7.1 */
3217 fragP->fr_fix+=4;
3218 /* md_number_to_chars(buffer_address,
3219 (long)(fragP->fr_symbol->sy_value + fragP->fr_offset),
3220 4); */
3221 ext=0;
3222 break;
f8701a3f
SC		 3223 case TAB(PCLEA,SHORT):
3224 subseg_change(SEG_TEXT,0);
a39116f1
RP		 3225 fix_new(fragP,(int)(fragP->fr_fix),2,fragP->fr_symbol,(symbolS *)0,fragP->fr_offset,1,
3226 NO_RELOC);
3227 fragP->fr_opcode[1] &= ~0x3F;
3228 fragP->fr_opcode[1] |= 0x3A;
3229 ext=2;
3230 break;
f8701a3f
SC		 3231 case TAB(PCLEA,LONG):
3232 subseg_change(SEG_TEXT,0);
3233 fix_new(fragP,(int)(fragP->fr_fix)+2,4,fragP->fr_symbol,(symbolS *)0,fragP->fr_offset+2,1,
3234 NO_RELOC);
3235 *buffer_address++ = 0x01;
3236 *buffer_address++ = 0x70;
3237 fragP->fr_fix+=2;
3238 /* buffer_address+=2; */
3239 ext=4;
a39116f1 3240 break;
a39116f1 3241
f8701a3f 3242} /* switch on subtype */
a39116f1 3243
f8701a3f
SC		 3244 if (ext) {
3245 md_number_to_chars(buffer_address, (long) disp, (int) ext);
3246 fragP->fr_fix += ext;
3247 /* H_SET_TEXT_SIZE(headers, H_GET_TEXT_SIZE(headers) + ext); */
3248 } /* if extending */
a39116f1 3249
f8701a3f
SC		 3250 return;
3251} /* md_convert_frag() */
3252
3253/* Force truly undefined symbols to their maximum size, and generally set up
3254 the frag list to be relaxed
3255 */
3256int md_estimate_size_before_relax(fragP, segment)
3257register fragS *fragP;
3258segT segment;
3259{
3260 int old_fix;
3261 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
a39116f1 3262
f8701a3f 3263 old_fix = fragP->fr_fix;
a39116f1 3264
f8701a3f
SC		 3265 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3266 switch (fragP->fr_subtype) {
3267
3268 case TAB(BRANCH,SZ_UNDEF): {
3269 if((fragP->fr_symbol != NULL) /* Not absolute */
3270 && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3271 fragP->fr_subtype=TAB(TABTYPE(fragP->fr_subtype),BYTE);
3272 break;
3273 } else if((fragP->fr_symbol == 0) || (cpu_of_arch(current_architecture) < m68020)) {
3274 /* On 68000, or for absolute value, switch to abs long */
3275 /* FIXME, we should check abs val, pick short or long */
3276 if(fragP->fr_opcode[0]==0x61) {
3277 fragP->fr_opcode[0]= 0x4E;
3278 fragP->fr_opcode[1]= 0xB9; /* JBSR with ABSL LONG offset */
3279 subseg_change(SEG_TEXT, 0);
3280 fix_new(fragP, fragP->fr_fix, 4,
3281 fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3282 fragP->fr_fix+=4;
3283 frag_wane(fragP);
3284 } else if(fragP->fr_opcode[0]==0x60) {
3285 fragP->fr_opcode[0]= 0x4E;
3286 fragP->fr_opcode[1]= 0xF9; /* JMP with ABSL LONG offset */
3287 subseg_change(SEG_TEXT, 0);
3288 fix_new(fragP, fragP->fr_fix, 4,
3289 fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3290 fragP->fr_fix+=4;
3291 frag_wane(fragP);
3292 } else {
3293 as_warn("Long branch offset to extern symbol not supported.");
3294 }
3295 } else { /* Symbol is still undefined. Make it simple */
3296 fix_new(fragP, (int)(fragP->fr_fix), 4, fragP->fr_symbol,
3297 (symbolS *)0, fragP->fr_offset+4, 1, NO_RELOC);
3298 fragP->fr_fix+=4;
3299 fragP->fr_opcode[1]=0xff;
3300 frag_wane(fragP);
3301 break;
3302 }
3303
3304 break;
3305 } /* case TAB(BRANCH,SZ_UNDEF) */
3306
3307 case TAB(FBRANCH,SZ_UNDEF): {
3308 if(S_GET_SEGMENT(fragP->fr_symbol) == segment || flagseen['l']) {
3309 fragP->fr_subtype = TAB(FBRANCH,SHORT);
3310 fragP->fr_var += 2;
3311 } else {
3312 fragP->fr_subtype = TAB(FBRANCH,LONG);
3313 fragP->fr_var += 4;
3314 }
3315 break;
3316 } /* TAB(FBRANCH,SZ_UNDEF) */
3317
3318 case TAB(PCREL,SZ_UNDEF): {
3319 if(S_GET_SEGMENT(fragP->fr_symbol) == segment || flagseen['l']) {
3320 fragP->fr_subtype = TAB(PCREL,SHORT);
3321 fragP->fr_var += 2;
3322 } else {
3323 fragP->fr_subtype = TAB(PCREL,LONG);
3324 fragP->fr_var += 4;
3325 }
3326 break;
3327 } /* TAB(PCREL,SZ_UNDEF) */
3328
3329 case TAB(BCC68000,SZ_UNDEF): {
3330 if((fragP->fr_symbol != NULL)
3331 && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3332 fragP->fr_subtype=TAB(BCC68000,BYTE);
3333 break;
3334 }
3335 /* only Bcc 68000 instructions can come here */
3336 /* change bcc into b!cc/jmp absl long */
3337 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3338 if(flagseen['l']) {
3339 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
3340 /* JF: these were fr_opcode[2,3] */
3341 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3342 buffer_address[1] = 0xf8;
3343 fragP->fr_fix += 2; /* account for jmp instruction */
3344 subseg_change(SEG_TEXT,0);
3345 fix_new(fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0,
3346 fragP->fr_offset, 0, NO_RELOC);
3347 fragP->fr_fix += 2;
3348 } else {
3349 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
3350 /* JF: these were fr_opcode[2,3] */
a1765cf0
SC		 3351 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3352 buffer_address[1] = 0xf9;
f8701a3f
SC		 3353 fragP->fr_fix += 2; /* account for jmp instruction */
3354 subseg_change(SEG_TEXT,0);
3355 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
3356 fragP->fr_offset, 0, NO_RELOC);
3357 fragP->fr_fix += 4;
3358 }
3359 frag_wane(fragP);
3360 break;
3361 } /* case TAB(BCC68000,SZ_UNDEF) */
3362
3363 case TAB(DBCC,SZ_UNDEF): {
3364 if (fragP->fr_symbol != NULL && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3365 fragP->fr_subtype=TAB(DBCC,SHORT);
3366 fragP->fr_var+=2;
3367 break;
3368 }
3369 /* only DBcc 68000 instructions can come here */
3370 /* change dbcc into dbcc/jmp absl long */
3371 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3372 buffer_address[0] = 0x00; /* branch offset = 4 */
3373 buffer_address[1] = 0x04;
3374 buffer_address[2] = 0x60; /* put in bra pc + ... */
3375
3376 if(flagseen['l']) {
3377 /* JF: these were fr_opcode[5-7] */
3378 buffer_address[3] = 0x04; /* plus 4 */
3379 buffer_address[4] = 0x4e;/* Put in Jump Word */
3380 buffer_address[5] = 0xf8;
3381 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3382 subseg_change(SEG_TEXT,0);
3383 fix_new(fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0,
a933d598
SC		 3384
3385
f8701a3f
SC		 3386 fragP->fr_offset, 0, NO_RELOC);
3387 fragP->fr_fix += 2;
3388 } else {
3389 /* JF: these were fr_opcode[5-7] */
3390 buffer_address[3] = 0x06; /* Plus 6 */
3391 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
3392 buffer_address[5] = 0xf9;
3393 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3394 subseg_change(SEG_TEXT,0);
3395 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
3396 fragP->fr_offset, 0, NO_RELOC);
3397 fragP->fr_fix += 4;
3398 }
3399
3400 frag_wane(fragP);
3401 break;
3402 } /* case TAB(DBCC,SZ_UNDEF) */
3403
3404 case TAB(PCLEA,SZ_UNDEF): {
3405 if ((S_GET_SEGMENT(fragP->fr_symbol))==segment || flagseen['l']) {
3406 fragP->fr_subtype=TAB(PCLEA,SHORT);
3407 fragP->fr_var+=2;
3408 } else {
3409 fragP->fr_subtype=TAB(PCLEA,LONG);
3410 fragP->fr_var+=6;
3411 }
3412 break;
3413 } /* TAB(PCLEA,SZ_UNDEF) */
3414
3415 default:
3416 break;
3417
3418 } /* switch on subtype looking for SZ_UNDEF's. */
a39116f1 3419
f8701a3f
SC		 3420 /* now that SZ_UNDEF are taken care of, check others */
3421 switch (fragP->fr_subtype) {
3422 case TAB(BCC68000,BYTE):
a39116f1
RP		 3423 case TAB(BRANCH,BYTE):
3424 /* We can't do a short jump to the next instruction,
3425 so we force word mode. */
3426 if (fragP->fr_symbol && S_GET_VALUE(fragP->fr_symbol)==0 &&
3427 fragP->fr_symbol->sy_frag==fragP->fr_next) {
f8701a3f
SC		 3428 fragP->fr_subtype=TAB(TABTYPE(fragP->fr_subtype),SHORT);
3429 fragP->fr_var+=2;
fecd2382 3430 }
a39116f1 3431 break;
f8701a3f 3432 default:
a39116f1 3433 break;
f8701a3f
SC		 3434}
3435 return fragP->fr_var + fragP->fr_fix - old_fix;
fecd2382
RP		 3436}
3437
3438#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
3439/* the bit-field entries in the relocation_info struct plays hell
3440 with the byte-order problems of cross-assembly. So as a hack,
3441 I added this mach. dependent ri twiddler. Ugly, but it gets
3442 you there. -KWK */
3443/* on m68k: first 4 bytes are normal unsigned long, next three bytes
a39116f1
RP		 3444 are symbolnum, most sig. byte first. Last byte is broken up with
3445 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3446 nibble as nuthin. (on Sun 3 at least) */
fecd2382
RP		 3447/* Translate the internal relocation information into target-specific
3448 format. */
a79c6033 3449#ifdef comment
fecd2382 3450void
a39116f1
RP		 3451 md_ri_to_chars(the_bytes, ri)
3452char *the_bytes;
3453struct reloc_info_generic *ri;
fecd2382 3454{
f8701a3f
SC		 3455 /* this is easy */
3456 md_number_to_chars(the_bytes, ri->r_address, 4);
3457 /* now the fun stuff */
3458 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
3459 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
3460 the_bytes[6] = ri->r_symbolnum & 0x0ff;
3461 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
3462 ((ri->r_extern << 4) & 0x10));
fecd2382 3463}
a79c6033
RP		 3464#endif /* comment */
3465
3466void tc_aout_fix_to_chars(where, fixP, segment_address_in_file)
f8701a3f
SC		 3467char *where;
3468fixS *fixP;
3469relax_addressT segment_address_in_file;
a79c6033 3470{
f8701a3f
SC		 3471 /*
3472 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3473 * Out: GNU LD relocation length code: 0, 1, or 2.
3474 */
3475
3476 static unsigned char nbytes_r_length [] = { 42, 0, 1, 42, 2 };
3477 long r_symbolnum;
3478
3479 know(fixP->fx_addsy != NULL);
3480
3481 md_number_to_chars(where,
3482 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
3483 4);
3484
3485 r_symbolnum = (S_IS_DEFINED(fixP->fx_addsy)
3486 ? S_GET_TYPE(fixP->fx_addsy)
3487 : fixP->fx_addsy->sy_number);
3488
3489 where[4] = (r_symbolnum >> 16) & 0x0ff;
3490 where[5] = (r_symbolnum >> 8) & 0x0ff;
3491 where[6] = r_symbolnum & 0x0ff;
3492 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
3493 (((!S_IS_DEFINED(fixP->fx_addsy)) << 4) & 0x10));
3494
3495 return;
a79c6033
RP		 3496} /* tc_aout_fix_to_chars() */
3497
fecd2382
RP		 3498#endif /* OBJ_AOUT or OBJ_BOUT */
3499
3500#ifndef WORKING_DOT_WORD
3501const int md_short_jump_size = 4;
3502const int md_long_jump_size = 6;
3503
3504void
a39116f1 3505 md_create_short_jump(ptr,from_addr,to_addr,frag,to_symbol)
fecd2382
RP		 3506char *ptr;
3507long from_addr,
a39116f1 3508 to_addr;
fecd2382
RP		 3509fragS *frag;
3510symbolS *to_symbol;
3511{
f8701a3f
SC		 3512 long offset;
3513
3514 offset = to_addr - (from_addr+2);
3515
3516 md_number_to_chars(ptr ,(long)0x6000,2);
3517 md_number_to_chars(ptr+2,(long)offset,2);
fecd2382
RP		 3518}
3519
3520void
a39116f1 3521 md_create_long_jump(ptr,from_addr,to_addr,frag,to_symbol)
fecd2382
RP		 3522char *ptr;
3523long from_addr,
a39116f1 3524 to_addr;
fecd2382
RP		 3525fragS *frag;
3526symbolS *to_symbol;
3527{
f8701a3f
SC		 3528 long offset;
3529
3530 if (cpu_of_arch(current_architecture) < m68020) {
3531 offset=to_addr-S_GET_VALUE(to_symbol);
3532 md_number_to_chars(ptr ,(long)0x4EF9,2);
3533 md_number_to_chars(ptr+2,(long)offset,4);
3534 fix_new(frag,(ptr+2)-frag->fr_literal,4,to_symbol,(symbolS *)0,(long)0,0,
3535 NO_RELOC);
3536 } else {
3537 offset=to_addr - (from_addr+2);
3538 md_number_to_chars(ptr ,(long)0x60ff,2);
3539 md_number_to_chars(ptr+2,(long)offset,4);
3540 }
fecd2382
RP		 3541}
3542
3543#endif
3544/* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
a39116f1
RP		 3545
3546 0: Everything is OK
3547 10: Absolute 1:8 only
3548 20: Absolute 0:7 only
3549 30: absolute 0:15 only
3550 40: Absolute 0:31 only
3551 50: absolute 0:127 only
3552 55: absolute -64:63 only
3553 60: absolute -128:127 only
3554 70: absolute 0:4095 only
3555 80: No bignums
3556
3557 */
fecd2382
RP		 3558
3559static int get_num(exp,ok)
f8701a3f
SC		 3560struct m68k_exp *exp;
3561int ok;
fecd2382
RP		 3562{
3563#ifdef TEST2
f8701a3f
SC		 3564 long l = 0;
3565
3566 if(!exp->e_beg)
3567 return 0;
3568 if(*exp->e_beg=='0') {
3569 if(exp->e_beg[1]=='x')
3570 sscanf(exp->e_beg+2,"%x",&l);
3571 else
3572 sscanf(exp->e_beg+1,"%O",&l);
3573 return l;
3574 }
3575 return atol(exp->e_beg);
fecd2382 3576#else
f8701a3f
SC		 3577 char *save_in;
3578 char c_save;
3579
3580 if(!exp) {
3581 /* Can't do anything */
3582 return 0;
3583 }
3584 if(!exp->e_beg || !exp->e_end) {
3585 seg(exp)=SEG_ABSOLUTE;
3586 adds(exp)=0;
3587 subs(exp)=0;
3588 offs(exp)= (ok==10) ? 1 : 0;
3589 as_warn("Null expression defaults to %ld",offs(exp));
3590 return 0;
fecd2382 3591 }
a39116f1 3592
f8701a3f
SC		 3593 exp->e_siz=0;
3594 if(/* ok!=80 && */exp->e_end[-1]==':' && (exp->e_end-exp->e_beg)>=2) {
3595 switch(exp->e_end[0]) {
3596 case 's':
3597 case 'S':
3598 case 'b':
3599 case 'B':
3600 exp->e_siz=1;
3601 break;
3602 case 'w':
3603 case 'W':
3604 exp->e_siz=2;
3605 break;
3606 case 'l':
3607 case 'L':
3608 exp->e_siz=3;
3609 break;
3610 default:
3611 as_bad("Unknown size for expression \"%c\"",exp->e_end[0]);
3612 }
3613 exp->e_end-=2;
fecd2382 3614 }
f8701a3f
SC		 3615 c_save=exp->e_end[1];
3616 exp->e_end[1]='\0';
3617 save_in=input_line_pointer;
3618 input_line_pointer=exp->e_beg;
3619 switch(expression(&(exp->e_exp))) {
3620 case SEG_PASS1:
3621 seg(exp)=SEG_ABSOLUTE;
3622 adds(exp)=0;
3623 subs(exp)=0;
3624 offs(exp)= (ok==10) ? 1 : 0;
3625 as_warn("Unknown expression: '%s' defaulting to %d",exp->e_beg,offs(exp));
3626 break;
3627
3628 case SEG_ABSENT:
3629 /* Do the same thing the VAX asm does */
3630 seg(exp)=SEG_ABSOLUTE;
3631 adds(exp)=0;
3632 subs(exp)=0;
fecd2382 3633 offs(exp)=0;
f8701a3f
SC		 3634 if(ok==10) {
3635 as_warn("expression out of range: defaulting to 1");
3636 offs(exp)=1;
3637 }
3638 break;
3639 case SEG_ABSOLUTE:
3640 switch(ok) {
3641 case 10:
3642 if(offs(exp)<1 || offs(exp)>8) {
3643 as_warn("expression out of range: defaulting to 1");
3644 offs(exp)=1;
3645 }
3646 break;
3647 case 20:
3648 if(offs(exp)<0 || offs(exp)>7)
3649 goto outrange;
3650 break;
3651 case 30:
3652 if(offs(exp)<0 || offs(exp)>15)
3653 goto outrange;
3654 break;
3655 case 40:
3656 if(offs(exp)<0 || offs(exp)>32)
3657 goto outrange;
3658 break;
3659 case 50:
3660 if(offs(exp)<0 || offs(exp)>127)
3661 goto outrange;
3662 break;
3663 case 55:
3664 if(offs(exp)<-64 || offs(exp)>63)
3665 goto outrange;
3666 break;
3667 case 60:
3668 if(offs(exp)<-128 || offs(exp)>127)
3669 goto outrange;
3670 break;
3671 case 70:
3672 if(offs(exp)<0 || offs(exp)>4095) {
3673 outrange:
3674 as_warn("expression out of range: defaulting to 0");
3675 offs(exp)=0;
3676 }
3677 break;
3678 default:
3679 break;
3680 }
3681 break;
3682 case SEG_TEXT:
3683 case SEG_DATA:
3684 case SEG_BSS:
3685 case SEG_UNKNOWN:
3686 case SEG_DIFFERENCE:
3687 if(ok>=10 && ok<=70) {
3688 seg(exp)=SEG_ABSOLUTE;
3689 adds(exp)=0;
3690 subs(exp)=0;
3691 offs(exp)= (ok==10) ? 1 : 0;
3692 as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp->e_beg,offs(exp));
3693 }
3694 break;
3695 case SEG_BIG:
3696 if(ok==80 && offs(exp)<0) { /* HACK! Turn it into a long */
3697 LITTLENUM_TYPE words[6];
3698
3699 gen_to_words(words,2,8L);/* These numbers are magic! */
3700 seg(exp)=SEG_ABSOLUTE;
3701 adds(exp)=0;
3702 subs(exp)=0;
3703 offs(exp)=words[1]|(words[0]<<16);
3704 } else if(ok!=0) {
3705 seg(exp)=SEG_ABSOLUTE;
3706 adds(exp)=0;
3707 subs(exp)=0;
3708 offs(exp)= (ok==10) ? 1 : 0;
3709 as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp->e_beg,offs(exp));
3710 }
3711 break;
fecd2382 3712 default:
f8701a3f 3713 as_fatal("failed sanity check.");
a39116f1 3714 }
f8701a3f
SC		 3715 if(input_line_pointer!=exp->e_end+1)
3716 as_bad("Ignoring junk after expression");
3717 exp->e_end[1]=c_save;
3718 input_line_pointer=save_in;
3719 if(exp->e_siz) {
3720 switch(exp->e_siz) {
3721 case 1:
3722 if(!isbyte(offs(exp)))
3723 as_warn("expression doesn't fit in BYTE");
3724 break;
3725 case 2:
3726 if(!isword(offs(exp)))
3727 as_warn("expression doesn't fit in WORD");
3728 break;
3729 }
a39116f1 3730 }
f8701a3f 3731 return offs(exp);
fecd2382
RP		 3732#endif
3733} /* get_num() */
3734
3735/* These are the back-ends for the various machine dependent pseudo-ops. */
f6e504fe 3736void demand_empty_rest_of_line(); /* Hate those extra verbose names */
fecd2382
RP		 3737
3738static void s_data1() {
f8701a3f
SC		 3739 subseg_new(SEG_DATA,1);
3740 demand_empty_rest_of_line();
fecd2382
RP		 3741} /* s_data1() */
3742
3743static void s_data2() {
f8701a3f
SC		 3744 subseg_new(SEG_DATA,2);
3745 demand_empty_rest_of_line();
fecd2382
RP		 3746} /* s_data2() */
3747
a1765cf0
SC		 3748static void s_bss()
3749{
3750 /* We don't support putting frags in the BSS segment, we fake it
3751 by marking in_bss, then looking at s_skip for clues */
3752
3753 subseg_new(SEG_BSS, 0);
f8701a3f 3754 demand_empty_rest_of_line();
fecd2382
RP		 3755} /* s_bss() */
3756
3757static void s_even() {
f8701a3f
SC		 3758 register int temp;
3759 register long temp_fill;
3760
3761 temp = 1; /* JF should be 2? */
3762 temp_fill = get_absolute_expression ();
3763 if ( ! need_pass_2 ) /* Never make frag if expect extra pass. */
3764 frag_align (temp, (int)temp_fill);
3765 demand_empty_rest_of_line();
fecd2382
RP		 3766} /* s_even() */
3767
3768static void s_proc() {
f8701a3f 3769 demand_empty_rest_of_line();
fecd2382
RP		 3770} /* s_proc() */
3771
3772/* s_space is defined in read.c .skip is simply an alias to it. */
3773
7c15cbe8
RP		 3774/*
3775 * md_parse_option
3776 * Invocation line includes a switch not recognized by the base assembler.
3777 * See if it's a processor-specific option. These are:
3778 *
3779 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
3780 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
3781 * Select the architecture. Instructions or features not
3782 * supported by the selected architecture cause fatal
3783 * errors. More than one may be specified. The default is
3784 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
3785 * for -m68000, and -m68882 is a synonym for -m68881.
3786 *
a39116f1
RP		 3787 * MAYBE_FLOAT_TOO is defined below so that specifying a processor type
3788 * (e.g. m68020) also requests that float instructions be included. This
3789 * is the default setup, mostly to avoid hassling users. A better
3790 * rearrangement of this structure would be to add an option to DENY
3791 * floating point opcodes, for people who want to really know there's none
3792 * of that funny floaty stuff going on. FIXME-later.
7c15cbe8 3793 */
a39116f1
RP		 3794#ifndef MAYBE_FLOAT_TOO
3795#define MAYBE_FLOAT_TOO m68881
3796#endif
7c15cbe8
RP		 3797
3798int md_parse_option(argP,cntP,vecP)
f8701a3f
SC		 3799char **argP;
3800int *cntP;
3801char ***vecP;
fecd2382 3802{
f8701a3f
SC		 3803 switch(**argP) {
3804 case 'l': /* -l means keep external to 2 bit offset
3805 rather than 16 bit one */
3806 break;
3807
3808 case 'S': /* -S means that jbsr's always turn into jsr's. */
3809 break;
3810
3811 case 'A':
3812 (*argP)++;
3813 /* intentional fall-through */
3814 case 'm':
3815 (*argP)++;
3816
3817 if (**argP=='c') {
3818 (*argP)++;
3819 } /* allow an optional "c" */
3820
3821 if (!strcmp(*argP, "68000")
3822 || !strcmp(*argP, "68008")) {
3823 current_architecture |= m68000;
3824 } else if (!strcmp(*argP, "68010")) {
fecd2382 3825#ifdef TE_SUN
f8701a3f 3826 omagic= 1<<16|OMAGIC;
fecd2382 3827#endif
f8701a3f
SC		 3828 current_architecture |= m68010;
3829
3830 } else if (!strcmp(*argP, "68020")) {
3831 current_architecture |= m68020 | MAYBE_FLOAT_TOO;
3832
3833 } else if (!strcmp(*argP, "68030")) {
3834 current_architecture |= m68030 | MAYBE_FLOAT_TOO;
3835
3836 } else if (!strcmp(*argP, "68040")) {
3837 current_architecture |= m68040 | MAYBE_FLOAT_TOO;
3838
7c15cbe8 3839#ifndef NO_68881
f8701a3f
SC		 3840 } else if (!strcmp(*argP, "68881")) {
3841 current_architecture |= m68881;
3842
3843 } else if (!strcmp(*argP, "68882")) {
3844 current_architecture |= m68882;
3845
7c15cbe8
RP		 3846#endif /* NO_68881 */
3847#ifndef NO_68851
f8701a3f
SC		 3848 } else if (!strcmp(*argP,"68851")) {
3849 current_architecture |= m68851;
3850
7c15cbe8 3851#endif /* NO_68851 */
f8701a3f
SC		 3852 } else {
3853 as_warn("Unknown architecture, \"%s\". option ignored", *argP);
3854 } /* switch on architecture */
3855
3856 while(**argP) (*argP)++;
3857
3858 break;
3859
3860 case 'p':
3861 if (!strcmp(*argP,"pic")) {
3862 (*argP) += 3;
3863 break; /* -pic, Position Independent Code */
3864 } else {
3865 return(0);
3866 } /* pic or not */
3867
3868 default:
3869 return 0;
3870 }
3871 return 1;
fecd2382
RP		 3872}
3873
3874
3875#ifdef TEST2
3876
3877/* TEST2: Test md_assemble() */
3878/* Warning, this routine probably doesn't work anymore */
3879
3880main()
3881{
f8701a3f
SC		 3882 struct m68k_it the_ins;
3883 char buf[120];
3884 char *cp;
3885 int n;
3886
3887 m68k_ip_begin();
3888 for(;;) {
3889 if(!gets(buf) || !*buf)
3890 break;
3891 if(buf[0]=='|' || buf[1]=='.')
3892 continue;
3893 for(cp=buf;*cp;cp++)
3894 if(*cp=='\t')
3895 *cp=' ';
3896 if(is_label(buf))
3897 continue;
3898 memset(&the_ins, '\0', sizeof(the_ins));
3899 m68k_ip(&the_ins,buf);
3900 if(the_ins.error) {
3901 printf("Error %s in %s\n",the_ins.error,buf);
3902 } else {
3903 printf("Opcode(%d.%s): ",the_ins.numo,the_ins.args);
3904 for(n=0;n<the_ins.numo;n++)
3905 printf(" 0x%x",the_ins.opcode[n]&0xffff);
3906 printf(" ");
3907 print_the_insn(&the_ins.opcode[0],stdout);
3908 (void)putchar('\n');
3909 }
3910 for(n=0;n<strlen(the_ins.args)/2;n++) {
3911 if(the_ins.operands[n].error) {
3912 printf("op%d Error %s in %s\n",n,the_ins.operands[n].error,buf);
3913 continue;
3914 }
3915 printf("mode %d, reg %d, ",the_ins.operands[n].mode,the_ins.operands[n].reg);
3916 if(the_ins.operands[n].b_const)
3917 printf("Constant: '%.*s', ",1+the_ins.operands[n].e_const-the_ins.operands[n].b_const,the_ins.operands[n].b_const);
3918 printf("ireg %d, isiz %d, imul %d, ",the_ins.operands[n].ireg,the_ins.operands[n].isiz,the_ins.operands[n].imul);
3919 if(the_ins.operands[n].b_iadd)
3920 printf("Iadd: '%.*s',",1+the_ins.operands[n].e_iadd-the_ins.operands[n].b_iadd,the_ins.operands[n].b_iadd);
3921 (void)putchar('\n');
3922 }
a39116f1 3923 }
f8701a3f
SC		 3924 m68k_ip_end();
3925 return 0;
fecd2382
RP		 3926}
3927
3928is_label(str)
f8701a3f 3929char *str;
fecd2382 3930{
f8701a3f
SC		 3931 while(*str==' ')
3932 str++;
3933 while(*str && *str!=' ')
3934 str++;
3935 if(str[-1]==':' || str[1]=='=')
3936 return 1;
3937 return 0;
fecd2382
RP		 3938}
3939
3940#endif
3941
3942/* Possible states for relaxation:
a39116f1
RP		 3943
3944 0 0 branch offset byte (bra, etc)
3945 0 1 word
3946 0 2 long
3947
3948 1 0 indexed offsets byte a0@(32,d4:w:1) etc
3949 1 1 word
3950 1 2 long
3951
3952 2 0 two-offset index word-word a0@(32,d4)@(45) etc
3953 2 1 word-long
3954 2 2 long-word
3955 2 3 long-long
3956
3957 */
fecd2382
RP		 3958
3959
3960
3961#ifdef DONTDEF
3962abort()
3963{
f8701a3f
SC		 3964 printf("ABORT!\n");
3965 exit(12);
fecd2382
RP		 3966}
3967
3968print_frags()
3969{
f8701a3f
SC		 3970 fragS *fragP;
3971 extern fragS *text_frag_root;
3972
3973 for(fragP=text_frag_root;fragP;fragP=fragP->fr_next) {
3974 printf("addr %lu next 0x%x fix %ld var %ld symbol 0x%x offset %ld\n",
3975 fragP->fr_address,fragP->fr_next,fragP->fr_fix,fragP->fr_var,fragP->fr_symbol,fragP->fr_offset);
3976 printf("opcode 0x%x type %d subtype %d\n\n",fragP->fr_opcode,fragP->fr_type,fragP->fr_subtype);
3977 }
3978 fflush(stdout);
3979 return 0;
fecd2382
RP		 3980}
3981#endif
3982
3983#ifdef DONTDEF
3984/*VARARGS1*/
3985panic(format,args)
f8701a3f 3986char *format;
fecd2382 3987{
f8701a3f
SC		 3988 fputs("Internal error:",stderr);
3989 _doprnt(format,&args,stderr);
3990 (void)putc('\n',stderr);
3991 as_where();
3992 abort();
fecd2382
RP		 3993}
3994#endif
3995
3996/* We have no need to default values of symbols. */
3997
3998/* ARGSUSED */
3999symbolS *
a39116f1
RP		 4000 md_undefined_symbol (name)
4001char *name;
fecd2382 4002{
f8701a3f 4003 return 0;
fecd2382
RP		 4004}
4005
4006/* Parse an operand that is machine-specific.
4007 We just return without modifying the expression if we have nothing
4008 to do. */
4009
4010/* ARGSUSED */
4011void
a39116f1
RP		 4012 md_operand (expressionP)
4013expressionS *expressionP;
fecd2382
RP		 4014{
4015}
4016
4017/* Round up a section size to the appropriate boundary. */
4018long
a39116f1
RP		 4019 md_section_align (segment, size)
4020segT segment;
4021long size;
fecd2382 4022{
f8701a3f 4023 return size; /* Byte alignment is fine */
fecd2382
RP		 4024}
4025
4026/* Exactly what point is a PC-relative offset relative TO?
4027 On the 68k, they're relative to the address of the offset, plus
4028 its size. (??? Is this right? FIXME-SOON!) */
4029long
a39116f1
RP		 4030 md_pcrel_from (fixP)
4031fixS *fixP;
fecd2382 4032{
f8701a3f 4033 return(fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address);
fecd2382
RP		 4034}
4035
fecd2382
RP		 4036/*
4037 * Local Variables:
4038 * comment-column: 0
4039 * fill-column: 131
4040 * End:
4041 */
4042
4043/* end of tc-m68k.c */
GDB Binutils - Deliverables
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