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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
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252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
266abb8f 3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
252b5132
RH		 4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
252b5132 21
252b5132 22#include "as.h"
3882b010 23#include "safe-ctype.h"
252b5132
RH		 24#include "obstack.h"
25#include "subsegs.h"
f27a3839 26#include "dwarf2dbg.h"
c04898f8 27#include "dw2gencfi.h"
252b5132
RH		 28
29#include "opcode/m68k.h"
30#include "m68k-parse.h"
31
0d96863f
CM		 32#if defined (OBJ_ELF)
33#include "elf/m68k.h"
34#endif
35
31302357
AS		 36#ifdef M68KCOFF
37#include "obj-coff.h"
38#endif
39
252b5132
RH		 40/* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44#if defined (TE_SVR4) || defined (TE_DELTA)
45const char *m68k_comment_chars = "|#";
46#else
47const char *m68k_comment_chars = "|";
48#endif
49
50/* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53/* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
92774660
KH		 55 #NO_APP at the beginning of its output. */
56/* Also note that comments like this one will always work. */
252b5132
RH		 57const char line_comment_chars[] = "#*";
58
63a0b638 59const char line_separator_chars[] = ";";
252b5132 60
36759679 61/* Chars that can be used to separate mant from exp in floating point nums. */
5a38dc70 62const char EXP_CHARS[] = "eE";
252b5132
RH		 63
64/* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
5a38dc70 67const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 68
69/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
252b5132
RH		 73/* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
92774660 75 references. Not implemented. For ELF there are other means
252b5132
RH		 76 to denote pic relocations. */
77int flag_want_pic;
78
36759679
NC		 79static int flag_short_refs; /* -l option. */
80static int flag_long_jumps; /* -S option. */
28e7409f 81static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 82
83#ifdef REGISTER_PREFIX_OPTIONAL
84int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85#else
86int flag_reg_prefix_optional;
87#endif
88
89/* Whether --register-prefix-optional was used on the command line. */
90static int reg_prefix_optional_seen;
91
92/* The floating point coprocessor to use by default. */
93static enum m68k_register m68k_float_copnum = COP1;
94
95/* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97static int m68k_abspcadd;
98
99/* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101static int m68k_quick = 1;
102
103/* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106static int m68k_rel32 = 1;
107
108/* This is non-zero if m68k_rel32 was set from the command line. */
109static int m68k_rel32_from_cmdline;
110
111/* The default width to use for an index register when using a base
112 displacement. */
113static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115/* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
252b5132
RH		 118struct label_line
119{
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125};
126
127/* The list of labels. */
128
129static struct label_line *labels;
130
131/* The current label. */
132
133static struct label_line *current_label;
134
60fed2d3
NC		 135/* Pointer to list holding the opcodes sorted by name. */
136static struct m68k_opcode const ** m68k_sorted_opcodes;
137
36759679
NC		 138/* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
252b5132
RH		 140static struct obstack robyn;
141
252b5132
RH		 142struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153#define gettwo(x) (((x)->m_opcode)&0xffff)
154
2da12c60
NS		 155static const enum m68k_register m68000_ctrl[] = { 0 };
156static const enum m68k_register m68010_ctrl[] = {
252b5132
RH		 157 SFC, DFC, USP, VBR,
158 0
159};
2da12c60 160static const enum m68k_register m68020_ctrl[] = {
252b5132
RH		 161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163};
2da12c60 164static const enum m68k_register m68040_ctrl[] = {
252b5132
RH		 165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168};
2da12c60 169static const enum m68k_register m68060_ctrl[] = {
252b5132
RH		 170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173};
2da12c60 174static const enum m68k_register mcf_ctrl[] = {
3e602632 175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
252b5132
RH		 176 RAMBAR0, RAMBAR1, MBAR,
177 0
178};
2da12c60 179static const enum m68k_register mcf5208_ctrl[] = {
266abb8f
NS		 180 CACR, ACR0, ACR1, VBR, RAMBAR1,
181 0
182};
2da12c60 183static const enum m68k_register mcf5213_ctrl[] = {
266abb8f
NS		 184 VBR, RAMBAR, FLASHBAR,
185 0
186};
2da12c60
NS		 187static const enum m68k_register mcf5216_ctrl[] = {
188 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
266abb8f
NS		 189 0
190};
2da12c60
NS		 191static const enum m68k_register mcf5235_ctrl[] = {
192 VBR, CACR, ACR0, ACR1, RAMBAR,
e80e0390
NC		 193 0
194};
2da12c60
NS		 195static const enum m68k_register mcf5249_ctrl[] = {
196 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR, MBAR2,
3e602632
NC		 197 0
198};
2da12c60
NS		 199static const enum m68k_register mcf5250_ctrl[] = {
200 VBR,
201 0
202};
203static const enum m68k_register mcf5271_ctrl[] = {
204 VBR, CACR, ACR0, ACR1, RAMBAR,
205 0
206};
207static const enum m68k_register mcf5272_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, MBAR,
209 0
210};
211static const enum m68k_register mcf5275_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, RAMBAR,
213 0
214};
215static const enum m68k_register mcf5282_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
217 0
218};
219static const enum m68k_register mcf5329_ctrl[] = {
220 VBR, CACR, ACR0, ACR1, RAMBAR,
221 0
222};
223static const enum m68k_register mcf5373_ctrl[] = {
224 VBR, CACR, ACR0, ACR1, RAMBAR,
225 0
226};
227static const enum m68k_register mcfv4e_ctrl[] = {
3e602632
NC		 228 CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
229 ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
230 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
231 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
232 0
233};
2da12c60 234#define cpu32_ctrl m68010_ctrl
252b5132
RH		 235
236static const enum m68k_register *control_regs;
237
36759679 238/* Internal form of a 68020 instruction. */
252b5132
RH		 239struct m68k_it
240{
241 const char *error;
36759679 242 const char *args; /* List of opcode info. */
252b5132
RH		 243 int numargs;
244
36759679 245 int numo; /* Number of shorts in opcode. */
252b5132
RH		 246 short opcode[11];
247
248 struct m68k_op operands[6];
249
36759679 250 int nexp; /* Number of exprs in use. */
252b5132
RH		 251 struct m68k_exp exprs[4];
252
36759679 253 int nfrag; /* Number of frags we have to produce. */
252b5132
RH		 254 struct
255 {
36759679 256 int fragoff; /* Where in the current opcode the frag ends. */
252b5132
RH		 257 symbolS *fadd;
258 offsetT foff;
259 int fragty;
260 }
261 fragb[4];
262
36759679 263 int nrel; /* Num of reloc strucs in use. */
252b5132
RH		 264 struct
265 {
266 int n;
267 expressionS exp;
268 char wid;
269 char pcrel;
270 /* In a pc relative address the difference between the address
271 of the offset and the address that the offset is relative
272 to. This depends on the addressing mode. Basically this
273 is the value to put in the offset field to address the
274 first byte of the offset, without regarding the special
275 significance of some values (in the branch instruction, for
276 example). */
277 int pcrel_fix;
278#ifdef OBJ_ELF
279 /* Whether this expression needs special pic relocation, and if
280 so, which. */
281 enum pic_relocation pic_reloc;
282#endif
283 }
36759679 284 reloc[5]; /* Five is enough??? */
252b5132
RH		 285};
286
6b6e92f4 287#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a))
252b5132
RH		 288#define float_of_arch(x) ((x) & mfloat)
289#define mmu_of_arch(x) ((x) & mmmu)
6b6e92f4
NC		 290#define arch_coldfire_p(x) ((x) & mcfisa_a)
291#define arch_coldfire_fpu(x) ((x) & cfloat)
252b5132 292
36759679 293/* Macros for determining if cpu supports a specific addressing mode. */
6b6e92f4 294#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
252b5132 295
36759679 296static struct m68k_it the_ins; /* The instruction being assembled. */
252b5132
RH		 297
298#define op(ex) ((ex)->exp.X_op)
299#define adds(ex) ((ex)->exp.X_add_symbol)
300#define subs(ex) ((ex)->exp.X_op_symbol)
301#define offs(ex) ((ex)->exp.X_add_number)
302
36759679 303/* Macros for adding things to the m68k_it struct. */
31302357 304#define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
252b5132 305
36759679
NC		 306/* Like addword, but goes BEFORE general operands. */
307
252b5132 308static void
31302357 309insop (int w, const struct m68k_incant *opcode)
252b5132
RH		 310{
311 int z;
07726851 312 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 313 the_ins.opcode[z] = the_ins.opcode[z - 1];
314 for (z = 0; z < the_ins.nrel; z++)
315 the_ins.reloc[z].n += 2;
252b5132
RH		 316 for (z = 0; z < the_ins.nfrag; z++)
317 the_ins.fragb[z].fragoff++;
8a104df9 318 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 319 the_ins.numo++;
320}
321
322/* The numo+1 kludge is so we can hit the low order byte of the prev word.
323 Blecch. */
324static void
31302357 325add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
252b5132 326{
31302357
AS		 327 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
328 ? the_ins.numo * 2 - 1
329 : (width == 'b'
330 ? the_ins.numo * 2 + 1
331 : the_ins.numo * 2));
252b5132
RH		 332 the_ins.reloc[the_ins.nrel].exp = exp->exp;
333 the_ins.reloc[the_ins.nrel].wid = width;
334 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
335#ifdef OBJ_ELF
336 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
337#endif
338 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
339}
340
341/* Cause an extra frag to be generated here, inserting up to 10 bytes
342 (that value is chosen in the frag_var call in md_assemble). TYPE
343 is the subtype of the frag to be generated; its primary type is
344 rs_machine_dependent.
345
346 The TYPE parameter is also used by md_convert_frag_1 and
347 md_estimate_size_before_relax. The appropriate type of fixup will
348 be emitted by md_convert_frag_1.
349
350 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
351static void
31302357 352add_frag (symbolS *add, offsetT off, int type)
252b5132 353{
8a104df9
KH		 354 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
355 the_ins.fragb[the_ins.nfrag].fadd = add;
356 the_ins.fragb[the_ins.nfrag].foff = off;
357 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 358}
359
360#define isvar(ex) \
361 (op (ex) != O_constant && op (ex) != O_big)
362
31302357
AS		 363static char *crack_operand (char *str, struct m68k_op *opP);
364static int get_num (struct m68k_exp *exp, int ok);
365static int reverse_16_bits (int in);
366static int reverse_8_bits (int in);
367static void install_gen_operand (int mode, int val);
368static void install_operand (int mode, int val);
369static void s_bss (int);
370static void s_data1 (int);
371static void s_data2 (int);
372static void s_even (int);
373static void s_proc (int);
374static void s_chip (int);
375static void s_fopt (int);
376static void s_opt (int);
377static void s_reg (int);
378static void s_restore (int);
379static void s_save (int);
380static void s_mri_if (int);
381static void s_mri_else (int);
382static void s_mri_endi (int);
383static void s_mri_break (int);
384static void s_mri_next (int);
385static void s_mri_for (int);
386static void s_mri_endf (int);
387static void s_mri_repeat (int);
388static void s_mri_until (int);
389static void s_mri_while (int);
390static void s_mri_endw (int);
266abb8f
NS		 391static void s_m68k_cpu (int);
392static void s_m68k_arch (int);
393
394struct m68k_cpu
395{
396 unsigned long arch; /* Architecture features. */
2da12c60 397 const enum m68k_register *control_regs; /* Control regs on chip */
266abb8f 398 const char *name; /* Name */
0b2e31dc
NS		 399 int alias; /* Alias for a cannonical name. If 1, then
400 succeeds canonical name, if -1 then
401 succeeds canonical name, if <-1 ||>1 this is a
402 deprecated name, and the next/previous name
403 should be used. */
266abb8f 404};
252b5132 405
266abb8f
NS		 406/* We hold flags for features explicitly enabled and explicitly
407 disabled. */
252b5132 408static int current_architecture;
266abb8f 409static int not_current_architecture;
266abb8f
NS		 410static const struct m68k_cpu *selected_arch;
411static const struct m68k_cpu *selected_cpu;
412static int initialized;
252b5132 413
266abb8f
NS		 414/* Architecture models. */
415static const struct m68k_cpu m68k_archs[] =
416{
2da12c60
NS		 417 {m68000, m68000_ctrl, "68000", 0},
418 {m68010, m68010_ctrl, "68010", 0},
419 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
420 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
421 {m68040, m68040_ctrl, "68040", 0},
422 {m68060, m68060_ctrl, "68060", 0},
423 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
424 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
425 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
426 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
427 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
428 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
266abb8f
NS		 429 {0,0,NULL, 0}
430};
252b5132 431
0b2e31dc
NS		 432/* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
433 for either. */
266abb8f
NS		 434static const struct m68k_cpu m68k_extensions[] =
435{
2da12c60
NS		 436 {m68851, NULL, "68851", -1},
437 {m68881, NULL, "68881", -1},
438 {m68881, NULL, "68882", -1},
0b2e31dc 439
2da12c60 440 {cfloat|m68881, NULL, "float", 0},
266abb8f 441
2da12c60
NS		 442 {mcfhwdiv, NULL, "div", 1},
443 {mcfusp, NULL, "usp", 1},
444 {mcfmac, NULL, "mac", 1},
445 {mcfemac, NULL, "emac", 1},
266abb8f 446
2da12c60 447 {0,NULL,NULL, 0}
266abb8f
NS		 448};
449
450/* Processor list */
451static const struct m68k_cpu m68k_cpus[] =
452{
2da12c60
NS		 453 {m68000, m68000_ctrl, "68000", 0},
454 {m68000, m68000_ctrl, "68ec000", 1},
455 {m68000, m68000_ctrl, "68hc000", 1},
456 {m68000, m68000_ctrl, "68hc001", 1},
457 {m68000, m68000_ctrl, "68008", 1},
458 {m68000, m68000_ctrl, "68302", 1},
459 {m68000, m68000_ctrl, "68306", 1},
460 {m68000, m68000_ctrl, "68307", 1},
461 {m68000, m68000_ctrl, "68322", 1},
462 {m68000, m68000_ctrl, "68356", 1},
463 {m68010, m68010_ctrl, "68010", 0},
464 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
465 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
466 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
467 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
468 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
469 {m68040, m68040_ctrl, "68040", 0},
470 {m68040, m68040_ctrl, "68ec040", 1},
471 {m68060, m68060_ctrl, "68060", 0},
472 {m68060, m68060_ctrl, "68ec060", 1},
473
474 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
475 {cpu32|m68881, cpu32_ctrl, "68330", 1},
476 {cpu32|m68881, cpu32_ctrl, "68331", 1},
477 {cpu32|m68881, cpu32_ctrl, "68332", 1},
478 {cpu32|m68881, cpu32_ctrl, "68333", 1},
479 {cpu32|m68881, cpu32_ctrl, "68334", 1},
480 {cpu32|m68881, cpu32_ctrl, "68336", 1},
481 {cpu32|m68881, cpu32_ctrl, "68340", 1},
482 {cpu32|m68881, cpu32_ctrl, "68341", 1},
483 {cpu32|m68881, cpu32_ctrl, "68349", 1},
484 {cpu32|m68881, cpu32_ctrl, "68360", 1},
485
486 {mcfisa_a, mcf_ctrl, "5200", 0},
487 {mcfisa_a, mcf_ctrl, "5202", 1},
488 {mcfisa_a, mcf_ctrl, "5204", 1},
489 {mcfisa_a, mcf_ctrl, "5206", 1},
490
491 {mcfisa_a|mcfhwdiv|mcfmac, mcf_ctrl, "5206e", 0},
492
493 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
494 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
495
496 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
497 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
498 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
499
500 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
501 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
502 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
503
504 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
505 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
506 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
507 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
508 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
509
510 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
511 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
512
513 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
514 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
515
516 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
517
518 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
519 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
520
521 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
522 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
523 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
524 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
525
526 {mcfisa_a|mcfhwdiv|mcfmac, mcf_ctrl, "5307", 0},
527
528 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
529 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
530 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
531 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
532
533 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
534 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
535 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
536
537 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
538
539 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5470", -1},
540 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5471", -1},
541 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5472", -1},
542 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5473", -1},
543 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5474", -1},
544 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5475", -1},
545 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "547x", 0},
546
547 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5480", -1},
548 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5481", -1},
549 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5482", -1},
550 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5483", -1},
551 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5484", -1},
552 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5485", -1},
553 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "548x", 0},
554
555 {0,NULL,NULL, 0}
dc84e067 556 };
252b5132 557
266abb8f
NS		 558static const struct m68k_cpu *m68k_lookup_cpu
559(const char *, const struct m68k_cpu *, int, int *);
560static int m68k_set_arch (const char *, int, int);
561static int m68k_set_cpu (const char *, int, int);
562static int m68k_set_extension (const char *, int, int);
563static void m68k_init_arch (void);
252b5132 564
151337e8
NC		 565/* This is the assembler relaxation table for m68k. m68k is a rich CISC
566 architecture and we have a lot of relaxation modes. */
252b5132 567
151337e8
NC		 568/* Macros used in the relaxation code. */
569#define TAB(x,y) (((x) << 2) + (y))
570#define TABTYPE(x) ((x) >> 2)
571
572/* Relaxation states. */
573#define BYTE 0
574#define SHORT 1
575#define LONG 2
576#define SZ_UNDEF 3
577
578/* Here are all the relaxation modes we support. First we can relax ordinary
579 branches. On 68020 and higher and on CPU32 all branch instructions take
580 three forms, so on these CPUs all branches always remain as such. When we
581 have to expand to the LONG form on a 68000, though, we substitute an
582 absolute jump instead. This is a direct replacement for unconditional
583 branches and a branch over a jump for conditional branches. However, if the
584 user requires PIC and disables this with --pcrel, we can only relax between
585 BYTE and SHORT forms, punting if that isn't enough. This gives us four
586 different relaxation modes for branches: */
587
36759679
NC		 588#define BRANCHBWL 0 /* Branch byte, word, or long. */
589#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
590#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
591#define BRANCHBW 3 /* Branch byte or word. */
151337e8
NC		 592
593/* We also relax coprocessor branches and DBcc's. All CPUs that support
594 coprocessor branches support them in word and long forms, so we have only
595 one relaxation mode for them. DBcc's are word only on all CPUs. We can
596 relax them to the LONG form with a branch-around sequence. This sequence
597 can use a long branch (if available) or an absolute jump (if acceptable).
598 This gives us two relaxation modes. If long branches are not available and
599 absolute jumps are not acceptable, we don't relax DBcc's. */
600
36759679
NC		 601#define FBRANCH 4 /* Coprocessor branch. */
602#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
603#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
151337e8
NC		 604
605/* That's all for instruction relaxation. However, we also relax PC-relative
606 operands. Specifically, we have three operand relaxation modes. On the
607 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
608 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
609 two. Also PC+displacement+index operands in their simple form (with a non-
610 suppressed index without memory indirection) are supported on all CPUs, but
611 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
612 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
613 form of the PC+displacement+index operand. Finally, some absolute operands
614 can be relaxed down to 16-bit PC-relative. */
615
36759679
NC		 616#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
617#define PCINDEX 8 /* PC + displacement + index. */
618#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
252b5132
RH		 619
620/* Note that calls to frag_var need to specify the maximum expansion
621 needed; this is currently 10 bytes for DBCC. */
622
623/* The fields are:
624 How far Forward this mode will reach:
625 How far Backward this mode will reach:
626 How many bytes this mode will add to the size of the frag
627 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 628
629 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 630relax_typeS md_relax_table[] =
631{
ac62c346
AM		 632 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
633 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
634 { 0, 0, 4, 0 },
635 { 1, 1, 0, 0 },
636
637 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
638 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
639 { 0, 0, 4, 0 },
640 { 1, 1, 0, 0 },
641
642 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
643 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
644 { 0, 0, 6, 0 },
645 { 1, 1, 0, 0 },
646
647 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
648 { 0, 0, 2, 0 },
649 { 1, 1, 0, 0 },
650 { 1, 1, 0, 0 },
651
36759679 652 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
ac62c346
AM		 653 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
654 { 0, 0, 4, 0 },
655 { 1, 1, 0, 0 },
656
36759679 657 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 658 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
659 { 0, 0, 10, 0 },
660 { 1, 1, 0, 0 },
661
36759679 662 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 663 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
664 { 0, 0, 10, 0 },
665 { 1, 1, 0, 0 },
666
36759679 667 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
ac62c346
AM		 668 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
669 { 0, 0, 6, 0 },
670 { 1, 1, 0, 0 },
671
672 { 125, -130, 0, TAB (PCINDEX, SHORT) },
673 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
674 { 0, 0, 4, 0 },
675 { 1, 1, 0, 0 },
676
36759679 677 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
ac62c346
AM		 678 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
679 { 0, 0, 4, 0 },
680 { 1, 1, 0, 0 },
252b5132
RH		 681};
682
683/* These are the machine dependent pseudo-ops. These are included so
684 the assembler can work on the output from the SUN C compiler, which
36759679 685 generates these. */
252b5132
RH		 686
687/* This table describes all the machine specific pseudo-ops the assembler
688 has to support. The fields are:
689 pseudo-op name without dot
690 function to call to execute this pseudo-op
36759679 691 Integer arg to pass to the function. */
252b5132
RH		 692const pseudo_typeS md_pseudo_table[] =
693{
694 {"data1", s_data1, 0},
695 {"data2", s_data2, 0},
696 {"bss", s_bss, 0},
697 {"even", s_even, 0},
698 {"skip", s_space, 0},
699 {"proc", s_proc, 0},
700#if defined (TE_SUN3) || defined (OBJ_ELF)
701 {"align", s_align_bytes, 0},
702#endif
703#ifdef OBJ_ELF
704 {"swbeg", s_ignore, 0},
705#endif
706 {"extend", float_cons, 'x'},
707 {"ldouble", float_cons, 'x'},
708
266abb8f
NS		 709 {"arch", s_m68k_arch, 0},
710 {"cpu", s_m68k_cpu, 0},
711
252b5132
RH		 712 /* The following pseudo-ops are supported for MRI compatibility. */
713 {"chip", s_chip, 0},
714 {"comline", s_space, 1},
715 {"fopt", s_fopt, 0},
716 {"mask2", s_ignore, 0},
717 {"opt", s_opt, 0},
718 {"reg", s_reg, 0},
719 {"restore", s_restore, 0},
720 {"save", s_save, 0},
721
722 {"if", s_mri_if, 0},
723 {"if.b", s_mri_if, 'b'},
724 {"if.w", s_mri_if, 'w'},
725 {"if.l", s_mri_if, 'l'},
726 {"else", s_mri_else, 0},
727 {"else.s", s_mri_else, 's'},
728 {"else.l", s_mri_else, 'l'},
729 {"endi", s_mri_endi, 0},
730 {"break", s_mri_break, 0},
731 {"break.s", s_mri_break, 's'},
732 {"break.l", s_mri_break, 'l'},
733 {"next", s_mri_next, 0},
734 {"next.s", s_mri_next, 's'},
735 {"next.l", s_mri_next, 'l'},
736 {"for", s_mri_for, 0},
737 {"for.b", s_mri_for, 'b'},
738 {"for.w", s_mri_for, 'w'},
739 {"for.l", s_mri_for, 'l'},
740 {"endf", s_mri_endf, 0},
741 {"repeat", s_mri_repeat, 0},
742 {"until", s_mri_until, 0},
743 {"until.b", s_mri_until, 'b'},
744 {"until.w", s_mri_until, 'w'},
745 {"until.l", s_mri_until, 'l'},
746 {"while", s_mri_while, 0},
747 {"while.b", s_mri_while, 'b'},
748 {"while.w", s_mri_while, 'w'},
749 {"while.l", s_mri_while, 'l'},
750 {"endw", s_mri_endw, 0},
751
752 {0, 0, 0}
753};
754
252b5132 755/* The mote pseudo ops are put into the opcode table, since they
31302357 756 don't start with a . they look like opcodes to gas. */
252b5132 757
5a38dc70 758const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 759{
760
761 {"dcl", cons, 4},
762 {"dc", cons, 2},
763 {"dcw", cons, 2},
764 {"dcb", cons, 1},
765
766 {"dsl", s_space, 4},
767 {"ds", s_space, 2},
768 {"dsw", s_space, 2},
769 {"dsb", s_space, 1},
770
771 {"xdef", s_globl, 0},
772#ifdef OBJ_ELF
773 {"align", s_align_bytes, 0},
774#else
775 {"align", s_align_ptwo, 0},
776#endif
777#ifdef M68KCOFF
778 {"sect", obj_coff_section, 0},
779 {"section", obj_coff_section, 0},
780#endif
781 {0, 0, 0}
782};
783
bd17c2c3
AM		 784/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
785 gives identical results to a 32-bit host. */
786#define TRUNC(X) ((valueT) (X) & 0xffffffff)
787#define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
788
789#define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
790#define isubyte(x) ((valueT) TRUNC (x) < 0x100)
791#define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
792#define isuword(x) ((valueT) TRUNC (x) < 0x10000)
793
794#define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
795#define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
252b5132
RH		 796#define islong(x) (1)
797
252b5132
RH		 798static char notend_table[256];
799static char alt_notend_table[256];
800#define notend(s) \
801 (! (notend_table[(unsigned char) *s] \
802 || (*s == ':' \
803 && alt_notend_table[(unsigned char) s[1]])))
804
6b6e92f4
NC		 805/* Return a human readable string holding the list of chips that are
806 valid for a particular architecture, suppressing aliases (unless
807 there is only one of them). */
808
809static char *
810find_cf_chip (int architecture)
811{
812 static char buf[1024];
6b6e92f4 813 char *cp;
2da12c60
NS		 814 const struct m68k_cpu *cpu;
815 int any = 0;
816
6b6e92f4
NC		 817 strcpy (buf, " (");
818 cp = buf + strlen (buf);
819
2da12c60
NS		 820 for (cpu = m68k_cpus; cpu->name; cpu++)
821 if (!cpu->alias && (cpu->arch & architecture))
6b6e92f4 822 {
2da12c60
NS		 823 const struct m68k_cpu *alias;
824 if (any)
6b6e92f4 825 {
2da12c60
NS		 826 strcpy (cp, ", ");
827 cp += 2;
828 }
829 any = 0;
830 strcpy (cp, cpu->name);
831 cp += strlen (cp);
832 strcpy (cp, " [");
833 cp += 2;
834 if (cpu != m68k_cpus)
835 for (alias = cpu - 1; alias->alias; alias--)
836 {
837 if (any)
838 {
839 strcpy (cp, ", ");
840 cp += 2;
841 }
842 strcpy (cp, alias->name);
843 cp += strlen (cp);
844 any = 1;
845 }
846 for (alias = cpu + 1; alias->alias; alias++)
847 {
848 if (any)
6b6e92f4 849 {
2da12c60
NS		 850 strcpy (cp, ", ");
851 cp += 2;
6b6e92f4 852 }
2da12c60
NS		 853 strcpy (cp, alias->name);
854 cp += strlen (cp);
855 any = 1;
6b6e92f4 856 }
2da12c60
NS		 857
858 strcpy (cp, "]");
859 any = 1;
860 if ((unsigned)(cp - buf) >= sizeof (buf))
861 as_fatal (_("coldfire string overflow"));
6b6e92f4 862 }
2da12c60 863 strcat (cp, ")");
6b6e92f4
NC		 864
865 return buf;
866}
867
252b5132
RH		 868#ifdef OBJ_ELF
869
c801568a
AM		 870/* Return zero if the reference to SYMBOL from within the same segment may
871 be relaxed. */
872
873/* On an ELF system, we can't relax an externally visible symbol,
874 because it may be overridden by a shared library. However, if
875 TARGET_OS is "elf", then we presume that we are assembling for an
876 embedded system, in which case we don't have to worry about shared
877 libraries, and we can relax any external sym. */
878
879#define relaxable_symbol(symbol) \
6358301e 880 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
c801568a
AM		 881 || S_IS_WEAK (symbol)))
882
252b5132
RH		 883/* Compute the relocation code for a fixup of SIZE bytes, using pc
884 relative relocation if PCREL is non-zero. PIC says whether a special
885 pic relocation was requested. */
886
252b5132 887static bfd_reloc_code_real_type
31302357 888get_reloc_code (int size, int pcrel, enum pic_relocation pic)
252b5132
RH		 889{
890 switch (pic)
891 {
892 case pic_got_pcrel:
893 switch (size)
894 {
895 case 1:
896 return BFD_RELOC_8_GOT_PCREL;
897 case 2:
898 return BFD_RELOC_16_GOT_PCREL;
899 case 4:
900 return BFD_RELOC_32_GOT_PCREL;
901 }
902 break;
903
904 case pic_got_off:
905 switch (size)
906 {
907 case 1:
908 return BFD_RELOC_8_GOTOFF;
909 case 2:
910 return BFD_RELOC_16_GOTOFF;
911 case 4:
912 return BFD_RELOC_32_GOTOFF;
913 }
914 break;
915
916 case pic_plt_pcrel:
917 switch (size)
918 {
919 case 1:
920 return BFD_RELOC_8_PLT_PCREL;
921 case 2:
922 return BFD_RELOC_16_PLT_PCREL;
923 case 4:
924 return BFD_RELOC_32_PLT_PCREL;
925 }
926 break;
927
928 case pic_plt_off:
929 switch (size)
930 {
931 case 1:
932 return BFD_RELOC_8_PLTOFF;
933 case 2:
934 return BFD_RELOC_16_PLTOFF;
935 case 4:
936 return BFD_RELOC_32_PLTOFF;
937 }
938 break;
939
940 case pic_none:
941 if (pcrel)
942 {
943 switch (size)
944 {
945 case 1:
946 return BFD_RELOC_8_PCREL;
947 case 2:
948 return BFD_RELOC_16_PCREL;
949 case 4:
950 return BFD_RELOC_32_PCREL;
951 }
952 }
953 else
954 {
955 switch (size)
956 {
957 case 1:
958 return BFD_RELOC_8;
959 case 2:
960 return BFD_RELOC_16;
961 case 4:
962 return BFD_RELOC_32;
963 }
964 }
965 }
966
967 if (pcrel)
968 {
969 if (pic == pic_none)
970 as_bad (_("Can not do %d byte pc-relative relocation"), size);
971 else
972 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
973 }
974 else
975 {
976 if (pic == pic_none)
977 as_bad (_("Can not do %d byte relocation"), size);
978 else
979 as_bad (_("Can not do %d byte pic relocation"), size);
980 }
981
982 return BFD_RELOC_NONE;
983}
984
985/* Here we decide which fixups can be adjusted to make them relative
986 to the beginning of the section instead of the symbol. Basically
987 we need to make sure that the dynamic relocations are done
988 correctly, so in some cases we force the original symbol to be
989 used. */
990int
31302357 991tc_m68k_fix_adjustable (fixS *fixP)
252b5132 992{
36759679 993 /* Adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 994 switch (fixP->fx_r_type)
995 {
996 case BFD_RELOC_8_GOT_PCREL:
997 case BFD_RELOC_16_GOT_PCREL:
998 case BFD_RELOC_32_GOT_PCREL:
999 case BFD_RELOC_8_GOTOFF:
1000 case BFD_RELOC_16_GOTOFF:
1001 case BFD_RELOC_32_GOTOFF:
1002 case BFD_RELOC_8_PLT_PCREL:
1003 case BFD_RELOC_16_PLT_PCREL:
1004 case BFD_RELOC_32_PLT_PCREL:
1005 case BFD_RELOC_8_PLTOFF:
1006 case BFD_RELOC_16_PLTOFF:
1007 case BFD_RELOC_32_PLTOFF:
1008 return 0;
1009
1010 case BFD_RELOC_VTABLE_INHERIT:
1011 case BFD_RELOC_VTABLE_ENTRY:
1012 return 0;
1013
1014 default:
1015 return 1;
1016 }
1017}
1018
1019#else /* !OBJ_ELF */
1020
1021#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1022
c801568a
AM		 1023#define relaxable_symbol(symbol) 1
1024
252b5132
RH		 1025#endif /* OBJ_ELF */
1026
252b5132 1027arelent *
31302357 1028tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 1029{
1030 arelent *reloc;
1031 bfd_reloc_code_real_type code;
1032
8ec6253e
NC		 1033 /* If the tcbit is set, then this was a fixup of a negative value
1034 that was never resolved. We do not have a reloc to handle this,
1035 so just return. We assume that other code will have detected this
1036 situation and produced a helpful error message, so we just tell the
1037 user that the reloc cannot be produced. */
252b5132 1038 if (fixp->fx_tcbit)
8ec6253e
NC		 1039 {
1040 if (fixp->fx_addsy)
b091f402
AM		 1041 as_bad_where (fixp->fx_file, fixp->fx_line,
1042 _("Unable to produce reloc against symbol '%s'"),
1043 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 1044 return NULL;
1045 }
252b5132
RH		 1046
1047 if (fixp->fx_r_type != BFD_RELOC_NONE)
1048 {
1049 code = fixp->fx_r_type;
1050
1051 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1052 that fixup_segment converted a non-PC relative reloc into a
1053 PC relative reloc. In such a case, we need to convert the
1054 reloc code. */
1055 if (fixp->fx_pcrel)
1056 {
1057 switch (code)
1058 {
1059 case BFD_RELOC_8:
1060 code = BFD_RELOC_8_PCREL;
1061 break;
1062 case BFD_RELOC_16:
1063 code = BFD_RELOC_16_PCREL;
1064 break;
1065 case BFD_RELOC_32:
1066 code = BFD_RELOC_32_PCREL;
1067 break;
1068 case BFD_RELOC_8_PCREL:
1069 case BFD_RELOC_16_PCREL:
1070 case BFD_RELOC_32_PCREL:
1071 case BFD_RELOC_8_GOT_PCREL:
1072 case BFD_RELOC_16_GOT_PCREL:
1073 case BFD_RELOC_32_GOT_PCREL:
1074 case BFD_RELOC_8_GOTOFF:
1075 case BFD_RELOC_16_GOTOFF:
1076 case BFD_RELOC_32_GOTOFF:
1077 case BFD_RELOC_8_PLT_PCREL:
1078 case BFD_RELOC_16_PLT_PCREL:
1079 case BFD_RELOC_32_PLT_PCREL:
1080 case BFD_RELOC_8_PLTOFF:
1081 case BFD_RELOC_16_PLTOFF:
1082 case BFD_RELOC_32_PLTOFF:
1083 break;
1084 default:
1085 as_bad_where (fixp->fx_file, fixp->fx_line,
1086 _("Cannot make %s relocation PC relative"),
1087 bfd_get_reloc_code_name (code));
1088 }
1089 }
1090 }
1091 else
1092 {
1093#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1094 switch (F (fixp->fx_size, fixp->fx_pcrel))
1095 {
1096#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1097 MAP (1, 0, BFD_RELOC_8);
1098 MAP (2, 0, BFD_RELOC_16);
1099 MAP (4, 0, BFD_RELOC_32);
1100 MAP (1, 1, BFD_RELOC_8_PCREL);
1101 MAP (2, 1, BFD_RELOC_16_PCREL);
1102 MAP (4, 1, BFD_RELOC_32_PCREL);
1103 default:
1104 abort ();
1105 }
1106 }
1107#undef F
1108#undef MAP
1109
1110 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 1111 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1112 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 1113 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1114#ifndef OBJ_ELF
1115 if (fixp->fx_pcrel)
1116 reloc->addend = fixp->fx_addnumber;
1117 else
1118 reloc->addend = 0;
1119#else
1120 if (!fixp->fx_pcrel)
1121 reloc->addend = fixp->fx_addnumber;
1122 else
1123 reloc->addend = (section->vma
8390138c
AS		 1124 /* Explicit sign extension in case char is
1125 unsigned. */
1126 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 1127 + fixp->fx_addnumber
1128 + md_pcrel_from (fixp));
1129#endif
1130
1131 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1132 assert (reloc->howto != 0);
1133
1134 return reloc;
1135}
1136
252b5132
RH		 1137/* Handle of the OPCODE hash table. NULL means any use before
1138 m68k_ip_begin() will crash. */
1139static struct hash_control *op_hash;
1140\f
1141/* Assemble an m68k instruction. */
1142
1143static void
31302357 1144m68k_ip (char *instring)
252b5132
RH		 1145{
1146 register char *p;
1147 register struct m68k_op *opP;
1148 register const struct m68k_incant *opcode;
1149 register const char *s;
1150 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1151 char *pdot, *pdotmove;
1152 enum m68k_size siz1, siz2;
1153 char c;
1154 int losing;
1155 int opsfound;
03b13e59 1156 struct m68k_op operands_backup[6];
252b5132
RH		 1157 LITTLENUM_TYPE words[6];
1158 LITTLENUM_TYPE *wordp;
1159 unsigned long ok_arch = 0;
1160
1161 if (*instring == ' ')
36759679 1162 instring++; /* Skip leading whitespace. */
252b5132
RH		 1163
1164 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1165 or exactly 1 space. */
252b5132
RH		 1166 pdot = 0;
1167 for (p = instring; *p != '\0'; p++)
1168 {
1169 if (*p == ' ')
1170 break;
1171 if (*p == '.')
1172 pdot = p;
1173 }
1174
1175 if (p == instring)
1176 {
1177 the_ins.error = _("No operator");
1178 return;
1179 }
1180
1181 /* p now points to the end of the opcode name, probably whitespace.
1182 Make sure the name is null terminated by clobbering the
1183 whitespace, look it up in the hash table, then fix it back.
1184 Remove a dot, first, since the opcode tables have none. */
1185 if (pdot != NULL)
1186 {
1187 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1188 *pdotmove = pdotmove[1];
1189 p--;
1190 }
1191
1192 c = *p;
1193 *p = '\0';
1194 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1195 *p = c;
1196
1197 if (pdot != NULL)
1198 {
1199 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1200 *pdotmove = pdotmove[-1];
1201 *pdot = '.';
1202 ++p;
1203 }
1204
1205 if (opcode == NULL)
1206 {
1207 the_ins.error = _("Unknown operator");
1208 return;
1209 }
1210
36759679 1211 /* Found a legitimate opcode, start matching operands. */
252b5132
RH		 1212 while (*p == ' ')
1213 ++p;
1214
1215 if (opcode->m_operands == 0)
1216 {
1217 char *old = input_line_pointer;
1218 *old = '\n';
1219 input_line_pointer = p;
36759679 1220 /* Ahh - it's a motorola style psuedo op. */
252b5132
RH		 1221 mote_pseudo_table[opcode->m_opnum].poc_handler
1222 (mote_pseudo_table[opcode->m_opnum].poc_val);
1223 input_line_pointer = old;
1224 *old = 0;
1225
1226 return;
1227 }
1228
1229 if (flag_mri && opcode->m_opnum == 0)
1230 {
1231 /* In MRI mode, random garbage is allowed after an instruction
1232 which accepts no operands. */
1233 the_ins.args = opcode->m_operands;
1234 the_ins.numargs = opcode->m_opnum;
1235 the_ins.numo = opcode->m_codenum;
1236 the_ins.opcode[0] = getone (opcode);
1237 the_ins.opcode[1] = gettwo (opcode);
1238 return;
1239 }
1240
1241 for (opP = &the_ins.operands[0]; *p; opP++)
1242 {
1243 p = crack_operand (p, opP);
1244
1245 if (opP->error)
1246 {
1247 the_ins.error = opP->error;
1248 return;
1249 }
1250 }
1251
1252 opsfound = opP - &the_ins.operands[0];
1253
1254 /* This ugly hack is to support the floating pt opcodes in their
1255 standard form. Essentially, we fake a first enty of type COP#1 */
1256 if (opcode->m_operands[0] == 'I')
1257 {
1258 int n;
1259
1260 for (n = opsfound; n > 0; --n)
1261 the_ins.operands[n] = the_ins.operands[n - 1];
1262
31302357 1263 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
252b5132
RH		 1264 the_ins.operands[0].mode = CONTROL;
1265 the_ins.operands[0].reg = m68k_float_copnum;
1266 opsfound++;
1267 }
1268
36759679 1269 /* We've got the operands. Find an opcode that'll accept them. */
252b5132
RH		 1270 for (losing = 0;;)
1271 {
1272 /* If we didn't get the right number of ops, or we have no
92774660 1273 common model with this pattern then reject this pattern. */
252b5132
RH		 1274
1275 ok_arch |= opcode->m_arch;
1276 if (opsfound != opcode->m_opnum
1277 || ((opcode->m_arch & current_architecture) == 0))
1278 ++losing;
1279 else
1280 {
03b13e59
NC		 1281 int i;
1282
1283 /* Make a copy of the operands of this insn so that
1284 we can modify them safely, should we want to. */
1285 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1286 for (i = 0; i < opsfound; i++)
1287 operands_backup[i] = the_ins.operands[i];
1288
1289 for (s = opcode->m_operands, opP = &operands_backup[0];
252b5132
RH		 1290 *s && !losing;
1291 s += 2, opP++)
1292 {
1293 /* Warning: this switch is huge! */
1294 /* I've tried to organize the cases into this order:
1295 non-alpha first, then alpha by letter. Lower-case
1296 goes directly before uppercase counterpart. */
1297 /* Code with multiple case ...: gets sorted by the lowest
1298 case ... it belongs to. I hope this makes sense. */
1299 switch (*s)
1300 {
1301 case '!':
1302 switch (opP->mode)
1303 {
1304 case IMMED:
1305 case DREG:
1306 case AREG:
1307 case FPREG:
1308 case CONTROL:
1309 case AINC:
1310 case ADEC:
1311 case REGLST:
1312 losing++;
1313 break;
1314 default:
1315 break;
1316 }
1317 break;
1318
1319 case '<':
1320 switch (opP->mode)
1321 {
1322 case DREG:
1323 case AREG:
1324 case FPREG:
1325 case CONTROL:
1326 case IMMED:
1327 case ADEC:
1328 case REGLST:
1329 losing++;
1330 break;
1331 default:
1332 break;
1333 }
1334 break;
1335
1336 case '>':
1337 switch (opP->mode)
1338 {
1339 case DREG:
1340 case AREG:
1341 case FPREG:
1342 case CONTROL:
1343 case IMMED:
1344 case AINC:
1345 case REGLST:
1346 losing++;
1347 break;
1348 case ABSL:
1349 break;
1350 default:
1351 if (opP->reg == PC
1352 || opP->reg == ZPC)
1353 losing++;
1354 break;
1355 }
1356 break;
1357
1358 case 'm':
1359 switch (opP->mode)
1360 {
1361 case DREG:
1362 case AREG:
1363 case AINDR:
1364 case AINC:
1365 case ADEC:
1366 break;
1367 default:
1368 losing++;
1369 }
8a104df9 1370 break;
252b5132
RH		 1371
1372 case 'n':
1373 switch (opP->mode)
1374 {
1375 case DISP:
1376 break;
1377 default:
1378 losing++;
1379 }
8a104df9 1380 break;
252b5132
RH		 1381
1382 case 'o':
1383 switch (opP->mode)
1384 {
1385 case BASE:
1386 case ABSL:
1387 case IMMED:
1388 break;
1389 default:
1390 losing++;
1391 }
8a104df9 1392 break;
252b5132
RH		 1393
1394 case 'p':
1395 switch (opP->mode)
1396 {
1397 case DREG:
1398 case AREG:
1399 case AINDR:
1400 case AINC:
1401 case ADEC:
1402 break;
1403 case DISP:
1404 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1405 losing++;
252b5132
RH		 1406 break;
1407 default:
1408 losing++;
1409 }
8a104df9 1410 break;
252b5132
RH		 1411
1412 case 'q':
1413 switch (opP->mode)
1414 {
1415 case DREG:
1416 case AINDR:
1417 case AINC:
1418 case ADEC:
1419 break;
1420 case DISP:
1421 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1422 losing++;
252b5132
RH		 1423 break;
1424 default:
1425 losing++;
1426 break;
1427 }
8a104df9 1428 break;
252b5132
RH		 1429
1430 case 'v':
1431 switch (opP->mode)
1432 {
1433 case DREG:
1434 case AINDR:
1435 case AINC:
1436 case ADEC:
1437 case ABSL:
1438 break;
1439 case DISP:
1440 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1441 losing++;
252b5132
RH		 1442 break;
1443 default:
1444 losing++;
1445 break;
1446 }
1447 break;
1448
1449 case '#':
1450 if (opP->mode != IMMED)
1451 losing++;
1452 else if (s[1] == 'b'
1453 && ! isvar (&opP->disp)
1454 && (opP->disp.exp.X_op != O_constant
1455 || ! isbyte (opP->disp.exp.X_add_number)))
1456 losing++;
1457 else if (s[1] == 'B'
1458 && ! isvar (&opP->disp)
1459 && (opP->disp.exp.X_op != O_constant
1460 || ! issbyte (opP->disp.exp.X_add_number)))
1461 losing++;
1462 else if (s[1] == 'w'
1463 && ! isvar (&opP->disp)
1464 && (opP->disp.exp.X_op != O_constant
1465 || ! isword (opP->disp.exp.X_add_number)))
1466 losing++;
1467 else if (s[1] == 'W'
1468 && ! isvar (&opP->disp)
1469 && (opP->disp.exp.X_op != O_constant
1470 || ! issword (opP->disp.exp.X_add_number)))
1471 losing++;
1472 break;
1473
1474 case '^':
1475 case 'T':
1476 if (opP->mode != IMMED)
1477 losing++;
1478 break;
1479
1480 case '$':
1481 if (opP->mode == AREG
1482 || opP->mode == CONTROL
1483 || opP->mode == FPREG
1484 || opP->mode == IMMED
1485 || opP->mode == REGLST
1486 || (opP->mode != ABSL
1487 && (opP->reg == PC
1488 || opP->reg == ZPC)))
1489 losing++;
1490 break;
1491
1492 case '%':
1493 if (opP->mode == CONTROL
1494 || opP->mode == FPREG
1495 || opP->mode == REGLST
1496 || opP->mode == IMMED
1497 || (opP->mode != ABSL
1498 && (opP->reg == PC
1499 || opP->reg == ZPC)))
1500 losing++;
1501 break;
1502
1503 case '&':
1504 switch (opP->mode)
1505 {
1506 case DREG:
1507 case AREG:
1508 case FPREG:
1509 case CONTROL:
1510 case IMMED:
1511 case AINC:
1512 case ADEC:
1513 case REGLST:
1514 losing++;
1515 break;
1516 case ABSL:
1517 break;
1518 default:
1519 if (opP->reg == PC
1520 || opP->reg == ZPC)
1521 losing++;
1522 break;
1523 }
1524 break;
1525
1526 case '*':
1527 if (opP->mode == CONTROL
1528 || opP->mode == FPREG
1529 || opP->mode == REGLST)
1530 losing++;
1531 break;
1532
1533 case '+':
1534 if (opP->mode != AINC)
1535 losing++;
1536 break;
1537
1538 case '-':
1539 if (opP->mode != ADEC)
1540 losing++;
1541 break;
1542
1543 case '/':
1544 switch (opP->mode)
1545 {
1546 case AREG:
1547 case CONTROL:
1548 case FPREG:
1549 case AINC:
1550 case ADEC:
1551 case IMMED:
1552 case REGLST:
1553 losing++;
1554 break;
1555 default:
1556 break;
1557 }
1558 break;
1559
1560 case ';':
1561 switch (opP->mode)
1562 {
1563 case AREG:
1564 case CONTROL:
1565 case FPREG:
1566 case REGLST:
1567 losing++;
1568 break;
1569 default:
1570 break;
1571 }
1572 break;
1573
1574 case '?':
1575 switch (opP->mode)
1576 {
1577 case AREG:
1578 case CONTROL:
1579 case FPREG:
1580 case AINC:
1581 case ADEC:
1582 case IMMED:
1583 case REGLST:
1584 losing++;
1585 break;
1586 case ABSL:
1587 break;
1588 default:
1589 if (opP->reg == PC || opP->reg == ZPC)
1590 losing++;
1591 break;
1592 }
1593 break;
1594
1595 case '@':
1596 switch (opP->mode)
1597 {
1598 case AREG:
1599 case CONTROL:
1600 case FPREG:
1601 case IMMED:
1602 case REGLST:
1603 losing++;
1604 break;
1605 default:
1606 break;
1607 }
1608 break;
1609
1610 case '~': /* For now! (JF FOO is this right?) */
1611 switch (opP->mode)
1612 {
1613 case DREG:
1614 case AREG:
1615 case CONTROL:
1616 case FPREG:
1617 case IMMED:
1618 case REGLST:
1619 losing++;
1620 break;
1621 case ABSL:
1622 break;
1623 default:
1624 if (opP->reg == PC
1625 || opP->reg == ZPC)
1626 losing++;
1627 break;
1628 }
1629 break;
1630
1631 case '3':
1632 if (opP->mode != CONTROL
1633 || (opP->reg != TT0 && opP->reg != TT1))
1634 losing++;
1635 break;
1636
1637 case 'A':
1638 if (opP->mode != AREG)
1639 losing++;
1640 break;
1641
1642 case 'a':
1643 if (opP->mode != AINDR)
1644 ++losing;
1645 break;
1646
fd99574b
NC		 1647 case '4':
1648 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1649 && (opP->mode != DISP
1650 || opP->reg < ADDR0
1651 || opP->reg > ADDR7))
1652 ++losing;
1653 break;
1654
252b5132
RH		 1655 case 'B': /* FOO */
1656 if (opP->mode != ABSL
1657 || (flag_long_jumps
1658 && strncmp (instring, "jbsr", 4) == 0))
1659 losing++;
1660 break;
1661
3e602632
NC		 1662 case 'b':
1663 switch (opP->mode)
1664 {
1665 case IMMED:
1666 case ABSL:
1667 case AREG:
1668 case FPREG:
1669 case CONTROL:
1670 case POST:
1671 case PRE:
1672 case REGLST:
1673 losing++;
1674 break;
1675 default:
1676 break;
1677 }
1678 break;
1679
252b5132
RH		 1680 case 'C':
1681 if (opP->mode != CONTROL || opP->reg != CCR)
1682 losing++;
1683 break;
1684
1685 case 'd':
1686 if (opP->mode != DISP
1687 || opP->reg < ADDR0
1688 || opP->reg > ADDR7)
1689 losing++;
1690 break;
1691
1692 case 'D':
1693 if (opP->mode != DREG)
1694 losing++;
1695 break;
1696
6da466c7
ILT		 1697 case 'E':
1698 if (opP->reg != ACC)
1699 losing++;
1700 break;
1701
fd99574b
NC		 1702 case 'e':
1703 if (opP->reg != ACC && opP->reg != ACC1
1704 && opP->reg != ACC2 && opP->reg != ACC3)
1705 losing++;
1706 break;
1707
252b5132
RH		 1708 case 'F':
1709 if (opP->mode != FPREG)
1710 losing++;
1711 break;
1712
6da466c7
ILT		 1713 case 'G':
1714 if (opP->reg != MACSR)
1715 losing++;
1716 break;
1717
fd99574b
NC		 1718 case 'g':
1719 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1720 losing++;
1721 break;
1722
6da466c7
ILT		 1723 case 'H':
1724 if (opP->reg != MASK)
1725 losing++;
1726 break;
1727
252b5132
RH		 1728 case 'I':
1729 if (opP->mode != CONTROL
1730 || opP->reg < COP0
1731 || opP->reg > COP7)
1732 losing++;
1733 break;
1734
fd99574b
NC		 1735 case 'i':
1736 if (opP->mode != LSH && opP->mode != RSH)
1737 losing++;
1738 break;
1739
252b5132
RH		 1740 case 'J':
1741 if (opP->mode != CONTROL
1742 || opP->reg < USP
0b2e31dc
NS		 1743 || opP->reg > last_movec_reg
1744 || !control_regs)
252b5132
RH		 1745 losing++;
1746 else
1747 {
1748 const enum m68k_register *rp;
0b2e31dc 1749
252b5132
RH		 1750 for (rp = control_regs; *rp; rp++)
1751 if (*rp == opP->reg)
1752 break;
1753 if (*rp == 0)
1754 losing++;
1755 }
1756 break;
1757
1758 case 'k':
1759 if (opP->mode != IMMED)
1760 losing++;
1761 break;
1762
1763 case 'l':
1764 case 'L':
1765 if (opP->mode == DREG
1766 || opP->mode == AREG
1767 || opP->mode == FPREG)
1768 {
1769 if (s[1] == '8')
1770 losing++;
1771 else
1772 {
1773 switch (opP->mode)
1774 {
1775 case DREG:
1776 opP->mask = 1 << (opP->reg - DATA0);
1777 break;
1778 case AREG:
1779 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1780 break;
1781 case FPREG:
1782 opP->mask = 1 << (opP->reg - FP0 + 16);
1783 break;
1784 default:
1785 abort ();
1786 }
1787 opP->mode = REGLST;
1788 }
1789 }
1790 else if (opP->mode == CONTROL)
1791 {
1792 if (s[1] != '8')
1793 losing++;
1794 else
1795 {
1796 switch (opP->reg)
1797 {
1798 case FPI:
1799 opP->mask = 1 << 24;
1800 break;
1801 case FPS:
1802 opP->mask = 1 << 25;
1803 break;
1804 case FPC:
1805 opP->mask = 1 << 26;
1806 break;
1807 default:
1808 losing++;
1809 break;
1810 }
1811 opP->mode = REGLST;
1812 }
1813 }
1814 else if (opP->mode != REGLST)
1815 losing++;
1816 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1817 losing++;
1818 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1819 losing++;
1820 break;
1821
1822 case 'M':
1823 if (opP->mode != IMMED)
1824 losing++;
1825 else if (opP->disp.exp.X_op != O_constant
1826 || ! issbyte (opP->disp.exp.X_add_number))
1827 losing++;
1828 else if (! m68k_quick
1829 && instring[3] != 'q'
1830 && instring[4] != 'q')
1831 losing++;
1832 break;
1833
1834 case 'O':
1835 if (opP->mode != DREG
1836 && opP->mode != IMMED
1837 && opP->mode != ABSL)
1838 losing++;
1839 break;
1840
1841 case 'Q':
1842 if (opP->mode != IMMED)
1843 losing++;
1844 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 1845 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
252b5132
RH		 1846 losing++;
1847 else if (! m68k_quick
1848 && (strncmp (instring, "add", 3) == 0
1849 || strncmp (instring, "sub", 3) == 0)
1850 && instring[3] != 'q')
1851 losing++;
1852 break;
1853
1854 case 'R':
1855 if (opP->mode != DREG && opP->mode != AREG)
1856 losing++;
1857 break;
1858
1859 case 'r':
1860 if (opP->mode != AINDR
1861 && (opP->mode != BASE
1862 || (opP->reg != 0
1863 && opP->reg != ZADDR0)
1864 || opP->disp.exp.X_op != O_absent
1865 || ((opP->index.reg < DATA0
1866 || opP->index.reg > DATA7)
1867 && (opP->index.reg < ADDR0
1868 || opP->index.reg > ADDR7))
1869 || opP->index.size != SIZE_UNSPEC
1870 || opP->index.scale != 1))
1871 losing++;
1872 break;
1873
1874 case 's':
1875 if (opP->mode != CONTROL
1876 || ! (opP->reg == FPI
1877 || opP->reg == FPS
1878 || opP->reg == FPC))
1879 losing++;
1880 break;
1881
1882 case 'S':
1883 if (opP->mode != CONTROL || opP->reg != SR)
1884 losing++;
1885 break;
1886
1887 case 't':
1888 if (opP->mode != IMMED)
1889 losing++;
1890 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 1891 || TRUNC (opP->disp.exp.X_add_number) > 7)
252b5132
RH		 1892 losing++;
1893 break;
1894
1895 case 'U':
1896 if (opP->mode != CONTROL || opP->reg != USP)
1897 losing++;
1898 break;
1899
3e602632
NC		 1900 case 'x':
1901 if (opP->mode != IMMED)
1902 losing++;
1903 else if (opP->disp.exp.X_op != O_constant
bd17c2c3
AM		 1904 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1905 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
3e602632
NC		 1906 losing++;
1907 break;
1908
252b5132
RH		 1909 /* JF these are out of order. We could put them
1910 in order if we were willing to put up with
1911 bunches of #ifdef m68851s in the code.
1912
1913 Don't forget that you need these operands
1914 to use 68030 MMU instructions. */
1915#ifndef NO_68851
36759679 1916 /* Memory addressing mode used by pflushr. */
252b5132
RH		 1917 case '|':
1918 if (opP->mode == CONTROL
1919 || opP->mode == FPREG
1920 || opP->mode == DREG
1921 || opP->mode == AREG
1922 || opP->mode == REGLST)
1923 losing++;
1924 /* We should accept immediate operands, but they
1925 supposedly have to be quad word, and we don't
1926 handle that. I would like to see what a Motorola
1927 assembler does before doing something here. */
1928 if (opP->mode == IMMED)
1929 losing++;
1930 break;
1931
1932 case 'f':
1933 if (opP->mode != CONTROL
1934 || (opP->reg != SFC && opP->reg != DFC))
1935 losing++;
1936 break;
1937
1938 case '0':
1939 if (opP->mode != CONTROL || opP->reg != TC)
1940 losing++;
1941 break;
1942
1943 case '1':
1944 if (opP->mode != CONTROL || opP->reg != AC)
1945 losing++;
1946 break;
1947
1948 case '2':
1949 if (opP->mode != CONTROL
1950 || (opP->reg != CAL
1951 && opP->reg != VAL
1952 && opP->reg != SCC))
1953 losing++;
1954 break;
1955
1956 case 'V':
1957 if (opP->mode != CONTROL
1958 || opP->reg != VAL)
1959 losing++;
1960 break;
1961
1962 case 'W':
1963 if (opP->mode != CONTROL
1964 || (opP->reg != DRP
1965 && opP->reg != SRP
1966 && opP->reg != CRP))
1967 losing++;
1968 break;
1969
3e602632
NC		 1970 case 'w':
1971 switch (opP->mode)
1972 {
1973 case IMMED:
1974 case ABSL:
1975 case AREG:
1976 case DREG:
1977 case FPREG:
1978 case CONTROL:
1979 case POST:
1980 case PRE:
1981 case REGLST:
1982 losing++;
1983 break;
1984 default:
1985 break;
1986 }
1987 break;
1988
252b5132
RH		 1989 case 'X':
1990 if (opP->mode != CONTROL
1991 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1992 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1993 losing++;
1994 break;
1995
1996 case 'Y':
1997 if (opP->mode != CONTROL || opP->reg != PSR)
1998 losing++;
1999 break;
2000
2001 case 'Z':
2002 if (opP->mode != CONTROL || opP->reg != PCSR)
2003 losing++;
2004 break;
2005#endif
2006 case 'c':
2007 if (opP->mode != CONTROL
2008 || (opP->reg != NC
2009 && opP->reg != IC
2010 && opP->reg != DC
2011 && opP->reg != BC))
36759679 2012 losing++;
252b5132
RH		 2013 break;
2014
2015 case '_':
2016 if (opP->mode != ABSL)
2017 ++losing;
2018 break;
2019
6da466c7
ILT		 2020 case 'u':
2021 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2022 losing++;
2023 /* FIXME: kludge instead of fixing parser:
2024 upper/lower registers are *not* CONTROL
92774660 2025 registers, but ordinary ones. */
6da466c7
ILT		 2026 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2027 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2028 opP->mode = DREG;
2029 else
2030 opP->mode = AREG;
2031 break;
2032
3e602632
NC		 2033 case 'y':
2034 if (!(opP->mode == AINDR
31302357
AS		 2035 || (opP->mode == DISP
2036 && !(opP->reg == PC || opP->reg == ZPC))))
3e602632
NC		 2037 losing++;
2038 break;
2039
2040 case 'z':
2041 if (!(opP->mode == AINDR || opP->mode == DISP))
2042 losing++;
2043 break;
2044
252b5132
RH		 2045 default:
2046 abort ();
36759679 2047 }
252b5132
RH		 2048
2049 if (losing)
2050 break;
36759679 2051 }
03b13e59
NC		 2052
2053 /* Since we have found the correct instruction, copy
2054 in the modifications that we may have made. */
2055 if (!losing)
2056 for (i = 0; i < opsfound; i++)
2057 the_ins.operands[i] = operands_backup[i];
36759679 2058 }
252b5132
RH		 2059
2060 if (!losing)
36759679 2061 break;
252b5132
RH		 2062
2063 opcode = opcode->m_next;
2064
2065 if (!opcode)
2066 {
2067 if (ok_arch
2068 && !(ok_arch & current_architecture))
2069 {
2070 char buf[200], *cp;
2071
6b6e92f4 2072 strncpy (buf,
31302357
AS		 2073 _("invalid instruction for this architecture; needs "),
2074 sizeof (buf));
252b5132
RH		 2075 cp = buf + strlen (buf);
2076 switch (ok_arch)
2077 {
6b6e92f4 2078 case mcfisa_a:
31302357
AS		 2079 strncpy (cp, _("ColdFire ISA_A"),
2080 sizeof (buf) - (cp - buf));
6b6e92f4 2081 cp += strlen (cp);
31302357
AS		 2082 strncpy (cp, find_cf_chip (ok_arch),
2083 sizeof (buf) - (cp - buf));
6b6e92f4
NC		 2084 cp += strlen (cp);
2085 break;
2086 case mcfhwdiv:
31302357
AS		 2087 strncpy (cp, _("ColdFire hardware divide"),
2088 sizeof (buf) - (cp - buf));
6b6e92f4 2089 cp += strlen (cp);
31302357
AS		 2090 strncpy (cp, find_cf_chip (ok_arch),
2091 sizeof (buf) - (cp - buf));
6b6e92f4
NC		 2092 cp += strlen (cp);
2093 break;
2094 case mcfisa_aa:
31302357
AS		 2095 strncpy (cp, _("ColdFire ISA_A+"),
2096 sizeof (buf) - (cp - buf));
6b6e92f4 2097 cp += strlen (cp);
31302357
AS		 2098 strncpy (cp, find_cf_chip (ok_arch),
2099 sizeof (buf) - (cp - buf));
6b6e92f4
NC		 2100 cp += strlen (cp);
2101 break;
2102 case mcfisa_b:
31302357
AS		 2103 strncpy (cp, _("ColdFire ISA_B"),
2104 sizeof (buf) - (cp - buf));
6b6e92f4 2105 cp += strlen (cp);
31302357
AS		 2106 strncpy (cp, find_cf_chip (ok_arch),
2107 sizeof (buf) - (cp - buf));
6b6e92f4
NC		 2108 cp += strlen (cp);
2109 break;
3e602632 2110 case cfloat:
31302357 2111 strncpy (cp, _("ColdFire fpu"), sizeof (buf) - (cp - buf));
6b6e92f4 2112 cp += strlen (cp);
31302357
AS		 2113 strncpy (cp, find_cf_chip (ok_arch),
2114 sizeof (buf) - (cp - buf));
6b6e92f4 2115 cp += strlen (cp);
3e602632 2116 break;
252b5132
RH		 2117 case mfloat:
2118 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
2119 break;
2120 case mmmu:
2121 strcpy (cp, _("mmu (68030 or 68851)"));
2122 break;
2123 case m68020up:
2124 strcpy (cp, _("68020 or higher"));
2125 break;
2126 case m68000up:
2127 strcpy (cp, _("68000 or higher"));
2128 break;
2129 case m68010up:
2130 strcpy (cp, _("68010 or higher"));
2131 break;
2132 default:
2133 {
2134 int got_one = 0, idx;
6b6e92f4 2135
266abb8f 2136 for (idx = 0; m68k_cpus[idx].name; idx++)
252b5132 2137 {
266abb8f
NS		 2138 if ((m68k_cpus[idx].arch & ok_arch)
2139 && ! m68k_cpus[idx].alias)
252b5132
RH		 2140 {
2141 if (got_one)
2142 {
2143 strcpy (cp, " or ");
2144 cp += strlen (cp);
2145 }
2146 got_one = 1;
266abb8f 2147 strcpy (cp, m68k_cpus[idx].name);
252b5132
RH		 2148 cp += strlen (cp);
2149 }
2150 }
2151 }
2152 }
2153 cp = xmalloc (strlen (buf) + 1);
2154 strcpy (cp, buf);
2155 the_ins.error = cp;
2156 }
2157 else
2158 the_ins.error = _("operands mismatch");
2159 return;
36759679 2160 }
252b5132
RH		 2161
2162 losing = 0;
2163 }
2164
36759679 2165 /* Now assemble it. */
252b5132
RH		 2166 the_ins.args = opcode->m_operands;
2167 the_ins.numargs = opcode->m_opnum;
2168 the_ins.numo = opcode->m_codenum;
2169 the_ins.opcode[0] = getone (opcode);
2170 the_ins.opcode[1] = gettwo (opcode);
2171
2172 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2173 {
2174 /* This switch is a doozy.
31302357 2175 Watch the first step; its a big one! */
252b5132
RH		 2176 switch (s[0])
2177 {
2178
2179 case '*':
2180 case '~':
2181 case '%':
2182 case ';':
2183 case '@':
2184 case '!':
2185 case '&':
2186 case '$':
2187 case '?':
2188 case '/':
2189 case '<':
2190 case '>':
3e602632 2191 case 'b':
252b5132
RH		 2192 case 'm':
2193 case 'n':
2194 case 'o':
2195 case 'p':
2196 case 'q':
2197 case 'v':
3e602632
NC		 2198 case 'w':
2199 case 'y':
2200 case 'z':
fd99574b 2201 case '4':
252b5132
RH		 2202#ifndef NO_68851
2203 case '|':
2204#endif
2205 switch (opP->mode)
2206 {
2207 case IMMED:
2208 tmpreg = 0x3c; /* 7.4 */
2209 if (strchr ("bwl", s[1]))
3e602632 2210 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2211 else
2212 nextword = get_num (&opP->disp, 0);
2213 if (isvar (&opP->disp))
2214 add_fix (s[1], &opP->disp, 0, 0);
2215 switch (s[1])
2216 {
2217 case 'b':
2218 if (!isbyte (nextword))
2219 opP->error = _("operand out of range");
2220 addword (nextword);
2221 baseo = 0;
2222 break;
2223 case 'w':
2224 if (!isword (nextword))
2225 opP->error = _("operand out of range");
2226 addword (nextword);
2227 baseo = 0;
2228 break;
2229 case 'W':
2230 if (!issword (nextword))
2231 opP->error = _("operand out of range");
2232 addword (nextword);
2233 baseo = 0;
2234 break;
2235 case 'l':
2236 addword (nextword >> 16);
2237 addword (nextword);
2238 baseo = 0;
2239 break;
2240
2241 case 'f':
2242 baseo = 2;
2243 outro = 8;
2244 break;
2245 case 'F':
2246 baseo = 4;
2247 outro = 11;
2248 break;
2249 case 'x':
2250 baseo = 6;
2251 outro = 15;
2252 break;
2253 case 'p':
2254 baseo = 6;
2255 outro = -1;
2256 break;
2257 default:
2258 abort ();
2259 }
2260 if (!baseo)
2261 break;
2262
36759679 2263 /* We gotta put out some float. */
252b5132
RH		 2264 if (op (&opP->disp) != O_big)
2265 {
2266 valueT val;
2267 int gencnt;
2268
2269 /* Can other cases happen here? */
2270 if (op (&opP->disp) != O_constant)
2271 abort ();
2272
2273 val = (valueT) offs (&opP->disp);
2274 gencnt = 0;
2275 do
2276 {
2277 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2278 val >>= LITTLENUM_NUMBER_OF_BITS;
2279 ++gencnt;
2280 }
2281 while (val != 0);
2282 offs (&opP->disp) = gencnt;
2283 }
2284 if (offs (&opP->disp) > 0)
2285 {
2286 if (offs (&opP->disp) > baseo)
2287 {
2288 as_warn (_("Bignum too big for %c format; truncated"),
2289 s[1]);
2290 offs (&opP->disp) = baseo;
2291 }
2292 baseo -= offs (&opP->disp);
2293 while (baseo--)
2294 addword (0);
2295 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2296 offs (&opP->disp)--;
2297 --wordp)
2298 addword (*wordp);
2299 break;
2300 }
2301 gen_to_words (words, baseo, (long) outro);
2302 for (wordp = words; baseo--; wordp++)
2303 addword (*wordp);
2304 break;
2305 case DREG:
2306 tmpreg = opP->reg - DATA; /* 0.dreg */
2307 break;
2308 case AREG:
2309 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2310 break;
2311 case AINDR:
2312 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2313 break;
2314 case ADEC:
2315 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2316 break;
2317 case AINC:
2318 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2319 break;
2320 case DISP:
2321
3e602632 2322 nextword = get_num (&opP->disp, 90);
252b5132 2323
580b9172
NC		 2324 /* Convert mode 5 addressing with a zero offset into
2325 mode 2 addressing to reduce the instruction size by a
2326 word. */
2327 if (! isvar (&opP->disp)
2328 && (nextword == 0)
2329 && (opP->disp.size == SIZE_UNSPEC)
2330 && (opP->reg >= ADDR0)
2331 && (opP->reg <= ADDR7))
2332 {
2333 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2334 break;
2335 }
2336
252b5132
RH		 2337 if (opP->reg == PC
2338 && ! isvar (&opP->disp)
2339 && m68k_abspcadd)
2340 {
2341 opP->disp.exp.X_op = O_symbol;
252b5132
RH		 2342 opP->disp.exp.X_add_symbol =
2343 section_symbol (absolute_section);
252b5132
RH		 2344 }
2345
36759679 2346 /* Force into index mode. Hope this works. */
252b5132
RH		 2347
2348 /* We do the first bit for 32-bit displacements, and the
2349 second bit for 16 bit ones. It is possible that we
2350 should make the default be WORD instead of LONG, but
2351 I think that'd break GCC, so we put up with a little
2352 inefficiency for the sake of working output. */
2353
2354 if (!issword (nextword)
2355 || (isvar (&opP->disp)
2356 && ((opP->disp.size == SIZE_UNSPEC
2357 && flag_short_refs == 0
2358 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2359 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2360 || opP->disp.size == SIZE_LONG)))
2361 {
2362 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2363 || arch_coldfire_p (current_architecture))
252b5132
RH		 2364 opP->error =
2365 _("displacement too large for this architecture; needs 68020 or higher");
2366 if (opP->reg == PC)
2367 tmpreg = 0x3B; /* 7.3 */
2368 else
2369 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2370 if (isvar (&opP->disp))
2371 {
2372 if (opP->reg == PC)
2373 {
2374 if (opP->disp.size == SIZE_LONG
2375#ifdef OBJ_ELF
2376 /* If the displacement needs pic
2377 relocation it cannot be relaxed. */
2378 || opP->disp.pic_reloc != pic_none
2379#endif
2380 )
2381 {
2382 addword (0x0170);
2383 add_fix ('l', &opP->disp, 1, 2);
2384 }
2385 else
2386 {
2387 add_frag (adds (&opP->disp),
bd17c2c3 2388 SEXT (offs (&opP->disp)),
151337e8 2389 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2390 break;
2391 }
2392 }
2393 else
2394 {
2395 addword (0x0170);
2396 add_fix ('l', &opP->disp, 0, 0);
2397 }
2398 }
2399 else
2400 addword (0x0170);
2401 addword (nextword >> 16);
2402 }
2403 else
2404 {
2405 if (opP->reg == PC)
2406 tmpreg = 0x3A; /* 7.2 */
2407 else
2408 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2409
2410 if (isvar (&opP->disp))
2411 {
2412 if (opP->reg == PC)
2413 {
2414 add_fix ('w', &opP->disp, 1, 0);
2415 }
2416 else
2417 add_fix ('w', &opP->disp, 0, 0);
2418 }
2419 }
2420 addword (nextword);
2421 break;
2422
2423 case POST:
2424 case PRE:
2425 case BASE:
2426 nextword = 0;
3e602632 2427 baseo = get_num (&opP->disp, 90);
252b5132 2428 if (opP->mode == POST || opP->mode == PRE)
3e602632 2429 outro = get_num (&opP->odisp, 90);
252b5132
RH		 2430 /* Figure out the `addressing mode'.
2431 Also turn on the BASE_DISABLE bit, if needed. */
2432 if (opP->reg == PC || opP->reg == ZPC)
2433 {
2434 tmpreg = 0x3b; /* 7.3 */
2435 if (opP->reg == ZPC)
2436 nextword |= 0x80;
2437 }
2438 else if (opP->reg == 0)
2439 {
2440 nextword |= 0x80;
2441 tmpreg = 0x30; /* 6.garbage */
2442 }
2443 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2444 {
2445 nextword |= 0x80;
2446 tmpreg = 0x30 + opP->reg - ZADDR0;
2447 }
2448 else
2449 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2450
2451 siz1 = opP->disp.size;
2452 if (opP->mode == POST || opP->mode == PRE)
2453 siz2 = opP->odisp.size;
2454 else
2455 siz2 = SIZE_UNSPEC;
2456
36759679 2457 /* Index register stuff. */
252b5132
RH		 2458 if (opP->index.reg != 0
2459 && opP->index.reg >= DATA
2460 && opP->index.reg <= ADDR7)
2461 {
2462 nextword |= (opP->index.reg - DATA) << 12;
2463
2464 if (opP->index.size == SIZE_LONG
2465 || (opP->index.size == SIZE_UNSPEC
2466 && m68k_index_width_default == SIZE_LONG))
2467 nextword |= 0x800;
2468
92774660 2469 if ((opP->index.scale != 1
252b5132 2470 && cpu_of_arch (current_architecture) < m68020)
92774660 2471 || (opP->index.scale == 8
3e602632 2472 && (arch_coldfire_p (current_architecture)
6b6e92f4 2473 && !arch_coldfire_fpu (current_architecture))))
252b5132
RH		 2474 {
2475 opP->error =
2476 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2477 }
2478
6da466c7
ILT		 2479 if (arch_coldfire_p (current_architecture)
2480 && opP->index.size == SIZE_WORD)
2481 opP->error = _("invalid index size for coldfire");
2482
252b5132
RH		 2483 switch (opP->index.scale)
2484 {
2485 case 1:
2486 break;
2487 case 2:
2488 nextword |= 0x200;
2489 break;
2490 case 4:
2491 nextword |= 0x400;
2492 break;
2493 case 8:
2494 nextword |= 0x600;
2495 break;
2496 default:
2497 abort ();
2498 }
2499 /* IF its simple,
2500 GET US OUT OF HERE! */
2501
2502 /* Must be INDEX, with an index register. Address
2503 register cannot be ZERO-PC, and either :b was
2504 forced, or we know it will fit. For a 68000 or
2505 68010, force this mode anyways, because the
2506 larger modes aren't supported. */
2507 if (opP->mode == BASE
2508 && ((opP->reg >= ADDR0
2509 && opP->reg <= ADDR7)
2510 || opP->reg == PC))
2511 {
2512 if (siz1 == SIZE_BYTE
2513 || cpu_of_arch (current_architecture) < m68020
6da466c7 2514 || arch_coldfire_p (current_architecture)
252b5132
RH		 2515 || (siz1 == SIZE_UNSPEC
2516 && ! isvar (&opP->disp)
2517 && issbyte (baseo)))
2518 {
2519 nextword += baseo & 0xff;
2520 addword (nextword);
2521 if (isvar (&opP->disp))
2522 {
2523 /* Do a byte relocation. If it doesn't
2524 fit (possible on m68000) let the
2525 fixup processing complain later. */
2526 if (opP->reg == PC)
2527 add_fix ('B', &opP->disp, 1, 1);
2528 else
2529 add_fix ('B', &opP->disp, 0, 0);
2530 }
2531 else if (siz1 != SIZE_BYTE)
2532 {
2533 if (siz1 != SIZE_UNSPEC)
2534 as_warn (_("Forcing byte displacement"));
2535 if (! issbyte (baseo))
2536 opP->error = _("byte displacement out of range");
2537 }
2538
2539 break;
2540 }
2541 else if (siz1 == SIZE_UNSPEC
2542 && opP->reg == PC
2543 && isvar (&opP->disp)
2544 && subs (&opP->disp) == NULL
2545#ifdef OBJ_ELF
2546 /* If the displacement needs pic
2547 relocation it cannot be relaxed. */
2548 && opP->disp.pic_reloc == pic_none
2549#endif
2550 )
2551 {
2552 /* The code in md_convert_frag_1 needs to be
2553 able to adjust nextword. Call frag_grow
2554 to ensure that we have enough space in
2555 the frag obstack to make all the bytes
2556 contiguous. */
2557 frag_grow (14);
8a104df9
KH		 2558 nextword += baseo & 0xff;
2559 addword (nextword);
bd17c2c3
AM		 2560 add_frag (adds (&opP->disp),
2561 SEXT (offs (&opP->disp)),
8a104df9 2562 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2563
2564 break;
8a104df9 2565 }
252b5132
RH		 2566 }
2567 }
2568 else
2569 {
36759679 2570 nextword |= 0x40; /* No index reg. */
252b5132
RH		 2571 if (opP->index.reg >= ZDATA0
2572 && opP->index.reg <= ZDATA7)
2573 nextword |= (opP->index.reg - ZDATA0) << 12;
2574 else if (opP->index.reg >= ZADDR0
2575 || opP->index.reg <= ZADDR7)
2576 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2577 }
2578
2579 /* It isn't simple. */
2580
2581 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2582 || arch_coldfire_p (current_architecture))
252b5132
RH		 2583 opP->error =
2584 _("invalid operand mode for this architecture; needs 68020 or higher");
2585
2586 nextword |= 0x100;
2587 /* If the guy specified a width, we assume that it is
2588 wide enough. Maybe it isn't. If so, we lose. */
2589 switch (siz1)
2590 {
2591 case SIZE_UNSPEC:
2592 if (isvar (&opP->disp)
2593 ? m68k_rel32
2594 : ! issword (baseo))
2595 {
2596 siz1 = SIZE_LONG;
2597 nextword |= 0x30;
2598 }
2599 else if (! isvar (&opP->disp) && baseo == 0)
2600 nextword |= 0x10;
2601 else
2602 {
2603 nextword |= 0x20;
2604 siz1 = SIZE_WORD;
2605 }
2606 break;
2607 case SIZE_BYTE:
2608 as_warn (_(":b not permitted; defaulting to :w"));
2609 /* Fall through. */
2610 case SIZE_WORD:
2611 nextword |= 0x20;
2612 break;
2613 case SIZE_LONG:
2614 nextword |= 0x30;
2615 break;
2616 }
2617
67c1ffbe 2618 /* Figure out inner displacement stuff. */
252b5132
RH		 2619 if (opP->mode == POST || opP->mode == PRE)
2620 {
2621 if (cpu_of_arch (current_architecture) & cpu32)
2622 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2623 switch (siz2)
2624 {
2625 case SIZE_UNSPEC:
2626 if (isvar (&opP->odisp)
2627 ? m68k_rel32
2628 : ! issword (outro))
2629 {
2630 siz2 = SIZE_LONG;
2631 nextword |= 0x3;
2632 }
2633 else if (! isvar (&opP->odisp) && outro == 0)
2634 nextword |= 0x1;
2635 else
2636 {
2637 nextword |= 0x2;
2638 siz2 = SIZE_WORD;
2639 }
2640 break;
2641 case 1:
2642 as_warn (_(":b not permitted; defaulting to :w"));
2643 /* Fall through. */
2644 case 2:
2645 nextword |= 0x2;
2646 break;
2647 case 3:
2648 nextword |= 0x3;
2649 break;
2650 }
2651 if (opP->mode == POST
2652 && (nextword & 0x40) == 0)
2653 nextword |= 0x04;
2654 }
2655 addword (nextword);
2656
2657 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2658 {
2659 if (opP->reg == PC || opP->reg == ZPC)
2660 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2661 else
2662 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2663 }
2664 if (siz1 == SIZE_LONG)
2665 addword (baseo >> 16);
2666 if (siz1 != SIZE_UNSPEC)
2667 addword (baseo);
2668
2669 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2670 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2671 if (siz2 == SIZE_LONG)
2672 addword (outro >> 16);
2673 if (siz2 != SIZE_UNSPEC)
2674 addword (outro);
2675
2676 break;
2677
2678 case ABSL:
3e602632 2679 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2680 switch (opP->disp.size)
2681 {
2682 default:
2683 abort ();
2684 case SIZE_UNSPEC:
2685 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2686 {
2687 tmpreg = 0x38; /* 7.0 */
2688 addword (nextword);
2689 break;
2690 }
252b5132
RH		 2691 if (isvar (&opP->disp)
2692 && !subs (&opP->disp)
2693 && adds (&opP->disp)
2694#ifdef OBJ_ELF
2695 /* If the displacement needs pic relocation it
2696 cannot be relaxed. */
2697 && opP->disp.pic_reloc == pic_none
2698#endif
252b5132
RH		 2699 && !flag_long_jumps
2700 && !strchr ("~%&$?", s[0]))
2701 {
2702 tmpreg = 0x3A; /* 7.2 */
2703 add_frag (adds (&opP->disp),
bd17c2c3 2704 SEXT (offs (&opP->disp)),
151337e8 2705 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2706 break;
2707 }
36759679 2708 /* Fall through into long. */
252b5132
RH		 2709 case SIZE_LONG:
2710 if (isvar (&opP->disp))
2711 add_fix ('l', &opP->disp, 0, 0);
2712
2713 tmpreg = 0x39;/* 7.1 mode */
2714 addword (nextword >> 16);
2715 addword (nextword);
2716 break;
2717
2718 case SIZE_BYTE:
2719 as_bad (_("unsupported byte value; use a different suffix"));
2720 /* Fall through. */
36759679
NC		 2721
2722 case SIZE_WORD:
252b5132
RH		 2723 if (isvar (&opP->disp))
2724 add_fix ('w', &opP->disp, 0, 0);
2725
2726 tmpreg = 0x38;/* 7.0 mode */
2727 addword (nextword);
2728 break;
2729 }
2730 break;
2731 case CONTROL:
2732 case FPREG:
2733 default:
2734 as_bad (_("unknown/incorrect operand"));
bc805888 2735 /* abort (); */
252b5132 2736 }
fd99574b
NC		 2737
2738 /* If s[0] is '4', then this is for the mac instructions
2739 that can have a trailing_ampersand set. If so, set 0x100
2740 bit on tmpreg so install_gen_operand can check for it and
2741 set the appropriate bit (word2, bit 5). */
2742 if (s[0] == '4')
2743 {
2744 if (opP->trailing_ampersand)
2745 tmpreg |= 0x100;
2746 }
252b5132
RH		 2747 install_gen_operand (s[1], tmpreg);
2748 break;
2749
2750 case '#':
2751 case '^':
2752 switch (s[1])
2753 { /* JF: I hate floating point! */
2754 case 'j':
2755 tmpreg = 70;
2756 break;
2757 case '8':
2758 tmpreg = 20;
2759 break;
2760 case 'C':
2761 tmpreg = 50;
2762 break;
2763 case '3':
2764 default:
3e602632 2765 tmpreg = 90;
252b5132
RH		 2766 break;
2767 }
2768 tmpreg = get_num (&opP->disp, tmpreg);
2769 if (isvar (&opP->disp))
2770 add_fix (s[1], &opP->disp, 0, 0);
2771 switch (s[1])
2772 {
2773 case 'b': /* Danger: These do no check for
2774 certain types of overflow.
2775 user beware! */
2776 if (!isbyte (tmpreg))
2777 opP->error = _("out of range");
2778 insop (tmpreg, opcode);
2779 if (isvar (&opP->disp))
2780 the_ins.reloc[the_ins.nrel - 1].n =
2781 (opcode->m_codenum) * 2 + 1;
2782 break;
2783 case 'B':
2784 if (!issbyte (tmpreg))
2785 opP->error = _("out of range");
2786 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2787 if (isvar (&opP->disp))
2788 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2789 break;
2790 case 'w':
2791 if (!isword (tmpreg))
2792 opP->error = _("out of range");
2793 insop (tmpreg, opcode);
2794 if (isvar (&opP->disp))
2795 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2796 break;
2797 case 'W':
2798 if (!issword (tmpreg))
2799 opP->error = _("out of range");
2800 insop (tmpreg, opcode);
2801 if (isvar (&opP->disp))
2802 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2803 break;
2804 case 'l':
2805 /* Because of the way insop works, we put these two out
2806 backwards. */
2807 insop (tmpreg, opcode);
2808 insop (tmpreg >> 16, opcode);
2809 if (isvar (&opP->disp))
2810 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2811 break;
2812 case '3':
2813 tmpreg &= 0xFF;
2814 case '8':
2815 case 'C':
2816 case 'j':
2817 install_operand (s[1], tmpreg);
2818 break;
2819 default:
2820 abort ();
2821 }
2822 break;
2823
2824 case '+':
2825 case '-':
2826 case 'A':
2827 case 'a':
2828 install_operand (s[1], opP->reg - ADDR);
2829 break;
2830
2831 case 'B':
3e602632 2832 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2833 switch (s[1])
2834 {
2835 case 'B':
8390138c 2836 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 2837 break;
2838 case 'W':
2839 add_fix ('w', &opP->disp, 1, 0);
2840 addword (0);
2841 break;
2842 case 'L':
2843 long_branch:
151337e8 2844 if (! HAVE_LONG_BRANCH (current_architecture))
81d4177b 2845 as_warn (_("Can't use long branches on 68000/68010/5200"));
151337e8 2846 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2847 add_fix ('l', &opP->disp, 1, 0);
2848 addword (0);
2849 addword (0);
2850 break;
2851 case 'g':
36759679 2852 if (subs (&opP->disp)) /* We can't relax it. */
252b5132
RH		 2853 goto long_branch;
2854
2855#ifdef OBJ_ELF
2856 /* If the displacement needs pic relocation it cannot be
2857 relaxed. */
2858 if (opP->disp.pic_reloc != pic_none)
2859 goto long_branch;
2860#endif
252b5132 2861 /* This could either be a symbol, or an absolute
151337e8
NC		 2862 address. If it's an absolute address, turn it into
2863 an absolute jump right here and keep it out of the
2864 relaxer. */
2865 if (adds (&opP->disp) == 0)
2866 {
2867 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 2868 the_ins.opcode[0] = 0x4EF9;
151337e8 2869 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 2870 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 2871 else /* jCC */
2872 {
2873 the_ins.opcode[0] ^= 0x0100;
2874 the_ins.opcode[0] |= 0x0006;
18566f55 2875 addword (0x4EF9);
151337e8
NC		 2876 }
2877 add_fix ('l', &opP->disp, 0, 0);
2878 addword (0);
2879 addword (0);
2880 break;
2881 }
2882
2883 /* Now we know it's going into the relaxer. Now figure
2884 out which mode. We try in this order of preference:
2885 long branch, absolute jump, byte/word branches only. */
2886 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 2887 add_frag (adds (&opP->disp),
2888 SEXT (offs (&opP->disp)),
151337e8
NC		 2889 TAB (BRANCHBWL, SZ_UNDEF));
2890 else if (! flag_keep_pcrel)
2891 {
2892 if ((the_ins.opcode[0] == 0x6000)
2893 || (the_ins.opcode[0] == 0x6100))
bd17c2c3
AM		 2894 add_frag (adds (&opP->disp),
2895 SEXT (offs (&opP->disp)),
151337e8
NC		 2896 TAB (BRABSJUNC, SZ_UNDEF));
2897 else
bd17c2c3
AM		 2898 add_frag (adds (&opP->disp),
2899 SEXT (offs (&opP->disp)),
151337e8
NC		 2900 TAB (BRABSJCOND, SZ_UNDEF));
2901 }
252b5132 2902 else
bd17c2c3
AM		 2903 add_frag (adds (&opP->disp),
2904 SEXT (offs (&opP->disp)),
151337e8 2905 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 2906 break;
2907 case 'w':
2908 if (isvar (&opP->disp))
2909 {
151337e8
NC		 2910 /* Check for DBcc instructions. We can relax them,
2911 but only if we have long branches and/or absolute
2912 jumps. */
2913 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2914 && (HAVE_LONG_BRANCH (current_architecture)
2915 || (! flag_keep_pcrel)))
252b5132 2916 {
151337e8 2917 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 2918 add_frag (adds (&opP->disp),
2919 SEXT (offs (&opP->disp)),
151337e8
NC		 2920 TAB (DBCCLBR, SZ_UNDEF));
2921 else
bd17c2c3
AM		 2922 add_frag (adds (&opP->disp),
2923 SEXT (offs (&opP->disp)),
151337e8 2924 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 2925 break;
2926 }
252b5132
RH		 2927 add_fix ('w', &opP->disp, 1, 0);
2928 }
2929 addword (0);
2930 break;
36759679 2931 case 'C': /* Fixed size LONG coproc branches. */
252b5132
RH		 2932 add_fix ('l', &opP->disp, 1, 0);
2933 addword (0);
2934 addword (0);
2935 break;
36759679 2936 case 'c': /* Var size Coprocesssor branches. */
151337e8 2937 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 2938 {
252b5132
RH		 2939 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2940 add_fix ('l', &opP->disp, 1, 0);
2941 addword (0);
2942 addword (0);
2943 }
151337e8 2944 else
bd17c2c3
AM		 2945 add_frag (adds (&opP->disp),
2946 SEXT (offs (&opP->disp)),
151337e8 2947 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 2948 break;
2949 default:
2950 abort ();
2951 }
2952 break;
2953
36759679 2954 case 'C': /* Ignore it. */
252b5132
RH		 2955 break;
2956
36759679 2957 case 'd': /* JF this is a kludge. */
252b5132 2958 install_operand ('s', opP->reg - ADDR);
3e602632 2959 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2960 if (!issword (tmpreg))
2961 {
2962 as_warn (_("Expression out of range, using 0"));
2963 tmpreg = 0;
2964 }
2965 addword (tmpreg);
2966 break;
2967
2968 case 'D':
2969 install_operand (s[1], opP->reg - DATA);
2970 break;
2971
fd99574b
NC		 2972 case 'e': /* EMAC ACCx, reg/reg. */
2973 install_operand (s[1], opP->reg - ACC);
2974 break;
2975
36759679 2976 case 'E': /* Ignore it. */
6da466c7
ILT		 2977 break;
2978
252b5132
RH		 2979 case 'F':
2980 install_operand (s[1], opP->reg - FP0);
2981 break;
2982
fd99574b
NC		 2983 case 'g': /* EMAC ACCEXTx. */
2984 install_operand (s[1], opP->reg - ACCEXT01);
2985 break;
2986
36759679 2987 case 'G': /* Ignore it. */
6da466c7
ILT		 2988 case 'H':
2989 break;
2990
252b5132
RH		 2991 case 'I':
2992 tmpreg = opP->reg - COP0;
2993 install_operand (s[1], tmpreg);
2994 break;
2995
fd99574b
NC		 2996 case 'i': /* MAC/EMAC scale factor. */
2997 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
2998 break;
2999
36759679 3000 case 'J': /* JF foo. */
252b5132
RH		 3001 switch (opP->reg)
3002 {
3003 case SFC:
3004 tmpreg = 0x000;
3005 break;
3006 case DFC:
3007 tmpreg = 0x001;
3008 break;
3009 case CACR:
3010 tmpreg = 0x002;
3011 break;
3012 case TC:
3013 tmpreg = 0x003;
3014 break;
3e602632 3015 case ACR0:
252b5132
RH		 3016 case ITT0:
3017 tmpreg = 0x004;
3018 break;
3e602632 3019 case ACR1:
252b5132
RH		 3020 case ITT1:
3021 tmpreg = 0x005;
3022 break;
3e602632 3023 case ACR2:
252b5132
RH		 3024 case DTT0:
3025 tmpreg = 0x006;
3026 break;
3e602632 3027 case ACR3:
252b5132
RH		 3028 case DTT1:
3029 tmpreg = 0x007;
3030 break;
3031 case BUSCR:
3032 tmpreg = 0x008;
3033 break;
3034
3035 case USP:
3036 tmpreg = 0x800;
3037 break;
3038 case VBR:
3039 tmpreg = 0x801;
3040 break;
3041 case CAAR:
3042 tmpreg = 0x802;
3043 break;
3044 case MSP:
3045 tmpreg = 0x803;
3046 break;
3047 case ISP:
3048 tmpreg = 0x804;
3049 break;
3050 case MMUSR:
3051 tmpreg = 0x805;
3052 break;
3053 case URP:
3054 tmpreg = 0x806;
3055 break;
3056 case SRP:
3057 tmpreg = 0x807;
3058 break;
3059 case PCR:
3060 tmpreg = 0x808;
3061 break;
3062 case ROMBAR:
3063 tmpreg = 0xC00;
3064 break;
3e602632
NC		 3065 case ROMBAR1:
3066 tmpreg = 0xC01;
3067 break;
3068 case FLASHBAR:
252b5132
RH		 3069 case RAMBAR0:
3070 tmpreg = 0xC04;
3071 break;
3e602632 3072 case RAMBAR:
252b5132
RH		 3073 case RAMBAR1:
3074 tmpreg = 0xC05;
3075 break;
3e602632
NC		 3076 case MPCR:
3077 tmpreg = 0xC0C;
3078 break;
3079 case EDRAMBAR:
3080 tmpreg = 0xC0D;
3081 break;
3082 case MBAR0:
e80e0390 3083 case MBAR2:
3e602632
NC		 3084 case SECMBAR:
3085 tmpreg = 0xC0E;
3086 break;
3087 case MBAR1:
252b5132
RH		 3088 case MBAR:
3089 tmpreg = 0xC0F;
3090 break;
3e602632
NC		 3091 case PCR1U0:
3092 tmpreg = 0xD02;
3093 break;
3094 case PCR1L0:
3095 tmpreg = 0xD03;
3096 break;
3097 case PCR2U0:
3098 tmpreg = 0xD04;
3099 break;
3100 case PCR2L0:
3101 tmpreg = 0xD05;
3102 break;
3103 case PCR3U0:
3104 tmpreg = 0xD06;
3105 break;
3106 case PCR3L0:
3107 tmpreg = 0xD07;
3108 break;
3109 case PCR1L1:
3110 tmpreg = 0xD0A;
3111 break;
3112 case PCR1U1:
3113 tmpreg = 0xD0B;
3114 break;
3115 case PCR2L1:
3116 tmpreg = 0xD0C;
3117 break;
3118 case PCR2U1:
3119 tmpreg = 0xD0D;
3120 break;
3121 case PCR3L1:
3122 tmpreg = 0xD0E;
3123 break;
3124 case PCR3U1:
3125 tmpreg = 0xD0F;
3126 break;
252b5132
RH		 3127 default:
3128 abort ();
3129 }
3130 install_operand (s[1], tmpreg);
3131 break;
3132
3133 case 'k':
3134 tmpreg = get_num (&opP->disp, 55);
3135 install_operand (s[1], tmpreg & 0x7f);
3136 break;
3137
3138 case 'l':
3139 tmpreg = opP->mask;
3140 if (s[1] == 'w')
3141 {
3142 if (tmpreg & 0x7FF0000)
3143 as_bad (_("Floating point register in register list"));
3144 insop (reverse_16_bits (tmpreg), opcode);
3145 }
3146 else
3147 {
3148 if (tmpreg & 0x700FFFF)
3149 as_bad (_("Wrong register in floating-point reglist"));
3150 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3151 }
3152 break;
3153
3154 case 'L':
3155 tmpreg = opP->mask;
3156 if (s[1] == 'w')
3157 {
3158 if (tmpreg & 0x7FF0000)
3159 as_bad (_("Floating point register in register list"));
3160 insop (tmpreg, opcode);
3161 }
3162 else if (s[1] == '8')
3163 {
3164 if (tmpreg & 0x0FFFFFF)
3165 as_bad (_("incorrect register in reglist"));
3166 install_operand (s[1], tmpreg >> 24);
3167 }
3168 else
3169 {
3170 if (tmpreg & 0x700FFFF)
3171 as_bad (_("wrong register in floating-point reglist"));
3172 else
3173 install_operand (s[1], tmpreg >> 16);
3174 }
3175 break;
3176
3177 case 'M':
3178 install_operand (s[1], get_num (&opP->disp, 60));
3179 break;
3180
3181 case 'O':
3182 tmpreg = ((opP->mode == DREG)
8fce3f5e 3183 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 3184 : (get_num (&opP->disp, 40) & 0x1F));
3185 install_operand (s[1], tmpreg);
3186 break;
3187
3188 case 'Q':
3189 tmpreg = get_num (&opP->disp, 10);
3190 if (tmpreg == 8)
3191 tmpreg = 0;
3192 install_operand (s[1], tmpreg);
3193 break;
3194
3195 case 'R':
3196 /* This depends on the fact that ADDR registers are eight
3197 more than their corresponding DATA regs, so the result
36759679 3198 will have the ADDR_REG bit set. */
252b5132
RH		 3199 install_operand (s[1], opP->reg - DATA);
3200 break;
3201
3202 case 'r':
3203 if (opP->mode == AINDR)
3204 install_operand (s[1], opP->reg - DATA);
3205 else
3206 install_operand (s[1], opP->index.reg - DATA);
3207 break;
3208
3209 case 's':
3210 if (opP->reg == FPI)
3211 tmpreg = 0x1;
3212 else if (opP->reg == FPS)
3213 tmpreg = 0x2;
3214 else if (opP->reg == FPC)
3215 tmpreg = 0x4;
3216 else
3217 abort ();
3218 install_operand (s[1], tmpreg);
3219 break;
3220
36759679 3221 case 'S': /* Ignore it. */
252b5132
RH		 3222 break;
3223
3224 case 'T':
3225 install_operand (s[1], get_num (&opP->disp, 30));
3226 break;
3227
36759679 3228 case 'U': /* Ignore it. */
252b5132
RH		 3229 break;
3230
3231 case 'c':
3232 switch (opP->reg)
3233 {
3234 case NC:
3235 tmpreg = 0;
3236 break;
3237 case DC:
3238 tmpreg = 1;
3239 break;
3240 case IC:
3241 tmpreg = 2;
3242 break;
3243 case BC:
3244 tmpreg = 3;
3245 break;
3246 default:
3247 as_fatal (_("failed sanity check"));
36759679 3248 } /* switch on cache token. */
252b5132
RH		 3249 install_operand (s[1], tmpreg);
3250 break;
3251#ifndef NO_68851
92774660 3252 /* JF: These are out of order, I fear. */
252b5132
RH		 3253 case 'f':
3254 switch (opP->reg)
3255 {
3256 case SFC:
3257 tmpreg = 0;
3258 break;
3259 case DFC:
3260 tmpreg = 1;
3261 break;
3262 default:
3263 abort ();
3264 }
3265 install_operand (s[1], tmpreg);
3266 break;
3267
3268 case '0':
3269 case '1':
3270 case '2':
3271 switch (opP->reg)
3272 {
3273 case TC:
3274 tmpreg = 0;
3275 break;
3276 case CAL:
3277 tmpreg = 4;
3278 break;
3279 case VAL:
3280 tmpreg = 5;
3281 break;
3282 case SCC:
3283 tmpreg = 6;
3284 break;
3285 case AC:
3286 tmpreg = 7;
3287 break;
3288 default:
3289 abort ();
3290 }
3291 install_operand (s[1], tmpreg);
3292 break;
3293
3294 case 'V':
3295 if (opP->reg == VAL)
3296 break;
3297 abort ();
3298
3299 case 'W':
3300 switch (opP->reg)
3301 {
3302 case DRP:
3303 tmpreg = 1;
3304 break;
3305 case SRP:
3306 tmpreg = 2;
3307 break;
3308 case CRP:
3309 tmpreg = 3;
3310 break;
3311 default:
3312 abort ();
3313 }
3314 install_operand (s[1], tmpreg);
3315 break;
3316
3317 case 'X':
3318 switch (opP->reg)
3319 {
3320 case BAD:
3321 case BAD + 1:
3322 case BAD + 2:
3323 case BAD + 3:
3324 case BAD + 4:
3325 case BAD + 5:
3326 case BAD + 6:
3327 case BAD + 7:
3328 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3329 break;
3330
3331 case BAC:
3332 case BAC + 1:
3333 case BAC + 2:
3334 case BAC + 3:
3335 case BAC + 4:
3336 case BAC + 5:
3337 case BAC + 6:
3338 case BAC + 7:
3339 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3340 break;
3341
3342 default:
3343 abort ();
3344 }
3345 install_operand (s[1], tmpreg);
3346 break;
3347 case 'Y':
3348 know (opP->reg == PSR);
3349 break;
3350 case 'Z':
3351 know (opP->reg == PCSR);
3352 break;
3353#endif /* m68851 */
3354 case '3':
3355 switch (opP->reg)
3356 {
3357 case TT0:
3358 tmpreg = 2;
3359 break;
3360 case TT1:
3361 tmpreg = 3;
3362 break;
3363 default:
3364 abort ();
3365 }
3366 install_operand (s[1], tmpreg);
3367 break;
3368 case 't':
3369 tmpreg = get_num (&opP->disp, 20);
3370 install_operand (s[1], tmpreg);
3371 break;
36759679 3372 case '_': /* used only for move16 absolute 32-bit address. */
252b5132
RH		 3373 if (isvar (&opP->disp))
3374 add_fix ('l', &opP->disp, 0, 0);
3e602632 3375 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3376 addword (tmpreg >> 16);
3377 addword (tmpreg & 0xFFFF);
3378 break;
6da466c7
ILT		 3379 case 'u':
3380 install_operand (s[1], opP->reg - DATA0L);
3381 opP->reg -= (DATA0L);
36759679 3382 opP->reg &= 0x0F; /* remove upper/lower bit. */
6da466c7 3383 break;
3e602632
NC		 3384 case 'x':
3385 tmpreg = get_num (&opP->disp, 80);
3386 if (tmpreg == -1)
3387 tmpreg = 0;
3388 install_operand (s[1], tmpreg);
3389 break;
252b5132
RH		 3390 default:
3391 abort ();
3392 }
3393 }
3394
3395 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3396 instruction, ready to be emitted. . . */
252b5132
RH		 3397}
3398
3399static int
31302357 3400reverse_16_bits (int in)
252b5132
RH		 3401{
3402 int out = 0;
3403 int n;
3404
3405 static int mask[16] =
3406 {
3407 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3408 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3409 };
3410 for (n = 0; n < 16; n++)
3411 {
3412 if (in & mask[n])
3413 out |= mask[15 - n];
3414 }
3415 return out;
3416} /* reverse_16_bits() */
3417
3418static int
31302357 3419reverse_8_bits (int in)
252b5132
RH		 3420{
3421 int out = 0;
3422 int n;
3423
3424 static int mask[8] =
3425 {
3426 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3427 };
3428
3429 for (n = 0; n < 8; n++)
3430 {
3431 if (in & mask[n])
3432 out |= mask[7 - n];
3433 }
3434 return out;
3435} /* reverse_8_bits() */
3436
3437/* Cause an extra frag to be generated here, inserting up to 10 bytes
3438 (that value is chosen in the frag_var call in md_assemble). TYPE
3439 is the subtype of the frag to be generated; its primary type is
3440 rs_machine_dependent.
3441
3442 The TYPE parameter is also used by md_convert_frag_1 and
3443 md_estimate_size_before_relax. The appropriate type of fixup will
3444 be emitted by md_convert_frag_1.
3445
3446 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3447static void
31302357 3448install_operand (int mode, int val)
252b5132
RH		 3449{
3450 switch (mode)
3451 {
3452 case 's':
36759679 3453 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
252b5132
RH		 3454 break;
3455 case 'd':
3456 the_ins.opcode[0] |= val << 9;
3457 break;
3458 case '1':
3459 the_ins.opcode[1] |= val << 12;
3460 break;
3461 case '2':
3462 the_ins.opcode[1] |= val << 6;
3463 break;
3464 case '3':
3465 the_ins.opcode[1] |= val;
3466 break;
3467 case '4':
3468 the_ins.opcode[2] |= val << 12;
3469 break;
3470 case '5':
3471 the_ins.opcode[2] |= val << 6;
3472 break;
3473 case '6':
3474 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3475 three words long! */
3476 the_ins.numo++;
3477 the_ins.opcode[2] |= val;
3478 break;
3479 case '7':
3480 the_ins.opcode[1] |= val << 7;
3481 break;
3482 case '8':
3483 the_ins.opcode[1] |= val << 10;
3484 break;
3485#ifndef NO_68851
3486 case '9':
3487 the_ins.opcode[1] |= val << 5;
3488 break;
3489#endif
3490
3491 case 't':
3492 the_ins.opcode[1] |= (val << 10) | (val << 7);
3493 break;
3494 case 'D':
3495 the_ins.opcode[1] |= (val << 12) | val;
3496 break;
3497 case 'g':
3498 the_ins.opcode[0] |= val = 0xff;
3499 break;
3500 case 'i':
3501 the_ins.opcode[0] |= val << 9;
3502 break;
3503 case 'C':
3504 the_ins.opcode[1] |= val;
3505 break;
3506 case 'j':
3507 the_ins.opcode[1] |= val;
36759679 3508 the_ins.numo++; /* What a hack. */
252b5132
RH		 3509 break;
3510 case 'k':
3511 the_ins.opcode[1] |= val << 4;
3512 break;
3513 case 'b':
3514 case 'w':
3515 case 'W':
3516 case 'l':
3517 break;
3518 case 'e':
3519 the_ins.opcode[0] |= (val << 6);
3520 break;
3521 case 'L':
3522 the_ins.opcode[1] = (val >> 16);
3523 the_ins.opcode[2] = val & 0xffff;
3524 break;
6da466c7
ILT		 3525 case 'm':
3526 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3527 the_ins.opcode[0] |= ((val & 0x7) << 9);
3528 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3529 break;
fd99574b 3530 case 'n': /* MAC/EMAC Rx on !load. */
6da466c7
ILT		 3531 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3532 the_ins.opcode[0] |= ((val & 0x7) << 9);
fd99574b 3533 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
6da466c7 3534 break;
fd99574b 3535 case 'o': /* MAC/EMAC Rx on load. */
6da466c7
ILT		 3536 the_ins.opcode[1] |= val << 12;
3537 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3538 break;
fd99574b 3539 case 'M': /* MAC/EMAC Ry on !load. */
6da466c7
ILT		 3540 the_ins.opcode[0] |= (val & 0xF);
3541 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3542 break;
fd99574b 3543 case 'N': /* MAC/EMAC Ry on load. */
6da466c7
ILT		 3544 the_ins.opcode[1] |= (val & 0xF);
3545 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3546 break;
3547 case 'h':
3548 the_ins.opcode[1] |= ((val != 1) << 10);
3549 break;
fd99574b
NC		 3550 case 'F':
3551 the_ins.opcode[0] |= ((val & 0x3) << 9);
3552 break;
3553 case 'f':
3554 the_ins.opcode[0] |= ((val & 0x3) << 0);
3555 break;
be8c092b 3556 case 'G': /* EMAC accumulator in a EMAC load instruction. */
fd99574b
NC		 3557 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3558 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3559 break;
be8c092b 3560 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
fd99574b
NC		 3561 the_ins.opcode[0] |= ((val & 0x1) << 7);
3562 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3563 break;
3564 case 'I':
3565 the_ins.opcode[1] |= ((val & 0x3) << 9);
3566 break;
3567 case ']':
3568 the_ins.opcode[0] |= (val & 0x1) <<10;
3569 break;
252b5132
RH		 3570 case 'c':
3571 default:
3572 as_fatal (_("failed sanity check."));
3573 }
6b6e92f4 3574}
252b5132
RH		 3575
3576static void
31302357 3577install_gen_operand (int mode, int val)
252b5132
RH		 3578{
3579 switch (mode)
3580 {
fd99574b
NC		 3581 case '/': /* Special for mask loads for mac/msac insns with
3582 possible mask; trailing_ampersend set in bit 8. */
3583 the_ins.opcode[0] |= (val & 0x3f);
3584 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3585 break;
252b5132
RH		 3586 case 's':
3587 the_ins.opcode[0] |= val;
3588 break;
3589 case 'd':
3590 /* This is a kludge!!! */
3591 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3592 break;
3593 case 'b':
3594 case 'w':
3595 case 'l':
3596 case 'f':
3597 case 'F':
3598 case 'x':
3599 case 'p':
3600 the_ins.opcode[0] |= val;
3601 break;
36759679 3602 /* more stuff goes here. */
252b5132
RH		 3603 default:
3604 as_fatal (_("failed sanity check."));
3605 }
6b6e92f4 3606}
252b5132 3607
6b6e92f4
NC		 3608/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3609 then deal with the bitfield hack. */
252b5132
RH		 3610
3611static char *
31302357 3612crack_operand (char *str, struct m68k_op *opP)
252b5132
RH		 3613{
3614 register int parens;
3615 register int c;
3616 register char *beg_str;
3617 int inquote = 0;
3618
3619 if (!str)
3620 {
3621 return str;
3622 }
3623 beg_str = str;
3624 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3625 {
3626 if (! inquote)
3627 {
3628 if (*str == '(')
3629 parens++;
3630 else if (*str == ')')
3631 {
3632 if (!parens)
36759679 3633 { /* ERROR. */
252b5132
RH		 3634 opP->error = _("Extra )");
3635 return str;
3636 }
3637 --parens;
3638 }
3639 }
3640 if (flag_mri && *str == '\'')
3641 inquote = ! inquote;
3642 }
3643 if (!*str && parens)
36759679 3644 { /* ERROR. */
252b5132
RH		 3645 opP->error = _("Missing )");
3646 return str;
3647 }
3648 c = *str;
3649 *str = '\0';
3650 if (m68k_ip_op (beg_str, opP) != 0)
3651 {
3652 *str = c;
3653 return str;
3654 }
3655 *str = c;
3656 if (c == '}')
36759679 3657 c = *++str; /* JF bitfield hack. */
252b5132
RH		 3658 if (c)
3659 {
3660 c = *++str;
3661 if (!c)
3662 as_bad (_("Missing operand"));
3663 }
3664
3665 /* Detect MRI REG symbols and convert them to REGLSTs. */
3666 if (opP->mode == CONTROL && (int)opP->reg < 0)
3667 {
3668 opP->mode = REGLST;
3669 opP->mask = ~(int)opP->reg;
3670 opP->reg = 0;
3671 }
3672
3673 return str;
3674}
3675
3676/* This is the guts of the machine-dependent assembler. STR points to a
3677 machine dependent instruction. This function is supposed to emit
3678 the frags/bytes it assembles to.
3679 */
3680
3681static void
31302357 3682insert_reg (const char *regname, int regnum)
252b5132
RH		 3683{
3684 char buf[100];
3685 int i;
3686
3687#ifdef REGISTER_PREFIX
3688 if (!flag_reg_prefix_optional)
3689 {
3690 buf[0] = REGISTER_PREFIX;
3691 strcpy (buf + 1, regname);
3692 regname = buf;
3693 }
3694#endif
3695
3696 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3697 &zero_address_frag));
3698
3699 for (i = 0; regname[i]; i++)
3882b010 3700 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 3701 buf[i] = '\0';
3702
3703 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3704 &zero_address_frag));
3705}
3706
3707struct init_entry
3708 {
3709 const char *name;
3710 int number;
3711 };
3712
3713static const struct init_entry init_table[] =
3714{
3715 { "d0", DATA0 },
3716 { "d1", DATA1 },
3717 { "d2", DATA2 },
3718 { "d3", DATA3 },
3719 { "d4", DATA4 },
3720 { "d5", DATA5 },
3721 { "d6", DATA6 },
3722 { "d7", DATA7 },
3723 { "a0", ADDR0 },
3724 { "a1", ADDR1 },
3725 { "a2", ADDR2 },
3726 { "a3", ADDR3 },
3727 { "a4", ADDR4 },
3728 { "a5", ADDR5 },
3729 { "a6", ADDR6 },
3730 { "fp", ADDR6 },
3731 { "a7", ADDR7 },
3732 { "sp", ADDR7 },
3733 { "ssp", ADDR7 },
3734 { "fp0", FP0 },
3735 { "fp1", FP1 },
3736 { "fp2", FP2 },
3737 { "fp3", FP3 },
3738 { "fp4", FP4 },
3739 { "fp5", FP5 },
3740 { "fp6", FP6 },
3741 { "fp7", FP7 },
3742 { "fpi", FPI },
3743 { "fpiar", FPI },
3744 { "fpc", FPI },
3745 { "fps", FPS },
3746 { "fpsr", FPS },
3747 { "fpc", FPC },
3748 { "fpcr", FPC },
3749 { "control", FPC },
3750 { "status", FPS },
3751 { "iaddr", FPI },
3752
3753 { "cop0", COP0 },
3754 { "cop1", COP1 },
3755 { "cop2", COP2 },
3756 { "cop3", COP3 },
3757 { "cop4", COP4 },
3758 { "cop5", COP5 },
3759 { "cop6", COP6 },
3760 { "cop7", COP7 },
3761 { "pc", PC },
3762 { "zpc", ZPC },
3763 { "sr", SR },
3764
3765 { "ccr", CCR },
3766 { "cc", CCR },
3767
6da466c7 3768 { "acc", ACC },
fd99574b
NC		 3769 { "acc0", ACC },
3770 { "acc1", ACC1 },
3771 { "acc2", ACC2 },
3772 { "acc3", ACC3 },
3773 { "accext01", ACCEXT01 },
3774 { "accext23", ACCEXT23 },
6da466c7
ILT		 3775 { "macsr", MACSR },
3776 { "mask", MASK },
3777
36759679
NC		 3778 /* Control registers. */
3779 { "sfc", SFC }, /* Source Function Code. */
252b5132 3780 { "sfcr", SFC },
36759679 3781 { "dfc", DFC }, /* Destination Function Code. */
252b5132 3782 { "dfcr", DFC },
36759679
NC		 3783 { "cacr", CACR }, /* Cache Control Register. */
3784 { "caar", CAAR }, /* Cache Address Register. */
252b5132 3785
36759679
NC		 3786 { "usp", USP }, /* User Stack Pointer. */
3787 { "vbr", VBR }, /* Vector Base Register. */
3788 { "msp", MSP }, /* Master Stack Pointer. */
3789 { "isp", ISP }, /* Interrupt Stack Pointer. */
252b5132 3790
36759679
NC		 3791 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3792 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3793 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3794 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
252b5132
RH		 3795
3796 /* 68ec040 versions of same */
36759679
NC		 3797 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3798 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3799 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3800 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
252b5132
RH		 3801
3802 /* mcf5200 versions of same. The ColdFire programmer's reference
3803 manual indicated that the order is 2,3,0,1, but Ken Rose
3804 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3e602632
NC		 3805 { "acr0", ACR0 }, /* Access Control Unit 0. */
3806 { "acr1", ACR1 }, /* Access Control Unit 1. */
3807 { "acr2", ACR2 }, /* Access Control Unit 2. */
3808 { "acr3", ACR3 }, /* Access Control Unit 3. */
252b5132 3809
36759679 3810 { "tc", TC }, /* MMU Translation Control Register. */
252b5132
RH		 3811 { "tcr", TC },
3812
36759679
NC		 3813 { "mmusr", MMUSR }, /* MMU Status Register. */
3814 { "srp", SRP }, /* User Root Pointer. */
3815 { "urp", URP }, /* Supervisor Root Pointer. */
252b5132
RH		 3816
3817 { "buscr", BUSCR },
3818 { "pcr", PCR },
3819
36759679
NC		 3820 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3821 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3822 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3823 { "mbar", MBAR }, /* Module Base Address Register. */
3e602632
NC		 3824
3825 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3826 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3827 { "rombar0", ROMBAR }, /* mcfv4e registers. */
3828 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3829 { "mpcr", MPCR }, /* mcfv4e registers. */
3830 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3831 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3832 { "asid", TC }, /* mcfv4e registers. */
3833 { "mmubar", BUSCR }, /* mcfv4e registers. */
3834 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3835 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3836 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3837 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3838 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3839 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3840 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3841 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3842 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3843 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3844 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3845 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3846
3847 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3848 { "rambar", RAMBAR }, /* mcf528x registers. */
e80e0390
NC		 3849
3850 { "mbar2", MBAR2 }, /* mcf5249 registers. */
36759679 3851 /* End of control registers. */
252b5132
RH		 3852
3853 { "ac", AC },
3854 { "bc", BC },
3855 { "cal", CAL },
3856 { "crp", CRP },
3857 { "drp", DRP },
3858 { "pcsr", PCSR },
3859 { "psr", PSR },
3860 { "scc", SCC },
3861 { "val", VAL },
3862 { "bad0", BAD0 },
3863 { "bad1", BAD1 },
3864 { "bad2", BAD2 },
3865 { "bad3", BAD3 },
3866 { "bad4", BAD4 },
3867 { "bad5", BAD5 },
3868 { "bad6", BAD6 },
3869 { "bad7", BAD7 },
3870 { "bac0", BAC0 },
3871 { "bac1", BAC1 },
3872 { "bac2", BAC2 },
3873 { "bac3", BAC3 },
3874 { "bac4", BAC4 },
3875 { "bac5", BAC5 },
3876 { "bac6", BAC6 },
3877 { "bac7", BAC7 },
3878
3879 { "ic", IC },
3880 { "dc", DC },
3881 { "nc", NC },
3882
3883 { "tt0", TT0 },
3884 { "tt1", TT1 },
36759679 3885 /* 68ec030 versions of same. */
252b5132
RH		 3886 { "ac0", TT0 },
3887 { "ac1", TT1 },
36759679 3888 /* 68ec030 access control unit, identical to 030 MMU status reg. */
252b5132
RH		 3889 { "acusr", PSR },
3890
3891 /* Suppressed data and address registers. */
3892 { "zd0", ZDATA0 },
3893 { "zd1", ZDATA1 },
3894 { "zd2", ZDATA2 },
3895 { "zd3", ZDATA3 },
3896 { "zd4", ZDATA4 },
3897 { "zd5", ZDATA5 },
3898 { "zd6", ZDATA6 },
3899 { "zd7", ZDATA7 },
3900 { "za0", ZADDR0 },
3901 { "za1", ZADDR1 },
3902 { "za2", ZADDR2 },
3903 { "za3", ZADDR3 },
3904 { "za4", ZADDR4 },
3905 { "za5", ZADDR5 },
3906 { "za6", ZADDR6 },
3907 { "za7", ZADDR7 },
3908
92774660 3909 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 3910 { "d0l", DATA0L },
3911 { "d1l", DATA1L },
3912 { "d2l", DATA2L },
3913 { "d3l", DATA3L },
3914 { "d4l", DATA4L },
3915 { "d5l", DATA5L },
3916 { "d6l", DATA6L },
3917 { "d7l", DATA7L },
3918
3919 { "a0l", ADDR0L },
3920 { "a1l", ADDR1L },
3921 { "a2l", ADDR2L },
3922 { "a3l", ADDR3L },
3923 { "a4l", ADDR4L },
3924 { "a5l", ADDR5L },
3925 { "a6l", ADDR6L },
3926 { "a7l", ADDR7L },
3927
3928 { "d0u", DATA0U },
3929 { "d1u", DATA1U },
3930 { "d2u", DATA2U },
3931 { "d3u", DATA3U },
3932 { "d4u", DATA4U },
3933 { "d5u", DATA5U },
3934 { "d6u", DATA6U },
3935 { "d7u", DATA7U },
3936
3937 { "a0u", ADDR0U },
3938 { "a1u", ADDR1U },
3939 { "a2u", ADDR2U },
3940 { "a3u", ADDR3U },
3941 { "a4u", ADDR4U },
3942 { "a5u", ADDR5U },
3943 { "a6u", ADDR6U },
3944 { "a7u", ADDR7U },
3945
252b5132
RH		 3946 { 0, 0 }
3947};
3948
3949static void
31302357 3950init_regtable (void)
252b5132
RH		 3951{
3952 int i;
3953 for (i = 0; init_table[i].name; i++)
3954 insert_reg (init_table[i].name, init_table[i].number);
3955}
3956
252b5132 3957void
31302357 3958md_assemble (char *str)
252b5132
RH		 3959{
3960 const char *er;
3961 short *fromP;
3962 char *toP = NULL;
3963 int m, n = 0;
3964 char *to_beg_P;
3965 int shorts_this_frag;
3966 fixS *fixP;
3967
266abb8f
NS		 3968 if (!selected_cpu && !selected_arch)
3969 {
3970 /* We've not selected an architecture yet. Set the default
3971 now. We do this lazily so that an initial .cpu or .arch directive
3972 can specify. */
3973 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
3974 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
3975 }
3976 if (!initialized)
3977 m68k_init_arch ();
3978
252b5132
RH		 3979 /* In MRI mode, the instruction and operands are separated by a
3980 space. Anything following the operands is a comment. The label
3981 has already been removed. */
3982 if (flag_mri)
3983 {
3984 char *s;
3985 int fields = 0;
3986 int infield = 0;
3987 int inquote = 0;
3988
3989 for (s = str; *s != '\0'; s++)
3990 {
3991 if ((*s == ' ' || *s == '\t') && ! inquote)
3992 {
3993 if (infield)
3994 {
3995 ++fields;
3996 if (fields >= 2)
3997 {
3998 *s = '\0';
3999 break;
4000 }
4001 infield = 0;
4002 }
4003 }
4004 else
4005 {
4006 if (! infield)
4007 infield = 1;
4008 if (*s == '\'')
4009 inquote = ! inquote;
4010 }
4011 }
4012 }
4013
31302357 4014 memset (&the_ins, '\0', sizeof (the_ins));
252b5132
RH		 4015 m68k_ip (str);
4016 er = the_ins.error;
4017 if (!er)
4018 {
4019 for (n = 0; n < the_ins.numargs; n++)
4020 if (the_ins.operands[n].error)
4021 {
4022 er = the_ins.operands[n].error;
4023 break;
4024 }
4025 }
4026 if (er)
4027 {
4028 as_bad (_("%s -- statement `%s' ignored"), er, str);
4029 return;
4030 }
4031
4032 /* If there is a current label, record that it marks an instruction. */
4033 if (current_label != NULL)
4034 {
4035 current_label->text = 1;
4036 current_label = NULL;
4037 }
4038
f27a3839
AS		 4039#ifdef OBJ_ELF
4040 /* Tie dwarf2 debug info to the address at the start of the insn. */
4041 dwarf2_emit_insn (0);
4042#endif
4043
252b5132
RH		 4044 if (the_ins.nfrag == 0)
4045 {
36759679 4046 /* No frag hacking involved; just put it out. */
252b5132
RH		 4047 toP = frag_more (2 * the_ins.numo);
4048 fromP = &the_ins.opcode[0];
4049 for (m = the_ins.numo; m; --m)
4050 {
4051 md_number_to_chars (toP, (long) (*fromP), 2);
4052 toP += 2;
4053 fromP++;
4054 }
36759679 4055 /* Put out symbol-dependent info. */
252b5132
RH		 4056 for (m = 0; m < the_ins.nrel; m++)
4057 {
4058 switch (the_ins.reloc[m].wid)
4059 {
4060 case 'B':
4061 n = 1;
4062 break;
4063 case 'b':
4064 n = 1;
4065 break;
4066 case '3':
4067 n = 1;
4068 break;
4069 case 'w':
4070 case 'W':
4071 n = 2;
4072 break;
4073 case 'l':
4074 n = 4;
4075 break;
4076 default:
4077 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4078 the_ins.reloc[m].wid);
4079 }
4080
4081 fixP = fix_new_exp (frag_now,
4082 ((toP - frag_now->fr_literal)
4083 - the_ins.numo * 2 + the_ins.reloc[m].n),
4084 n,
4085 &the_ins.reloc[m].exp,
4086 the_ins.reloc[m].pcrel,
4087 get_reloc_code (n, the_ins.reloc[m].pcrel,
4088 the_ins.reloc[m].pic_reloc));
4089 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4090 if (the_ins.reloc[m].wid == 'B')
4091 fixP->fx_signed = 1;
4092 }
4093 return;
4094 }
4095
36759679 4096 /* There's some frag hacking. */
fbe572f9
AM		 4097 {
4098 /* Calculate the max frag size. */
4099 int wid;
4100
4101 wid = 2 * the_ins.fragb[0].fragoff;
4102 for (n = 1; n < the_ins.nfrag; n++)
4103 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4104 /* frag_var part. */
4105 wid += 10;
4106 /* Make sure the whole insn fits in one chunk, in particular that
4107 the var part is attached, as we access one byte before the
4108 variable frag for byte branches. */
4109 frag_grow (wid);
4110 }
4111
252b5132
RH		 4112 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4113 {
4114 int wid;
4115
4116 if (n == 0)
4117 wid = 2 * the_ins.fragb[n].fragoff;
4118 else
4119 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4120 toP = frag_more (wid);
4121 to_beg_P = toP;
4122 shorts_this_frag = 0;
4123 for (m = wid / 2; m; --m)
4124 {
4125 md_number_to_chars (toP, (long) (*fromP), 2);
4126 toP += 2;
4127 fromP++;
4128 shorts_this_frag++;
4129 }
4130 for (m = 0; m < the_ins.nrel; m++)
4131 {
4132 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4133 {
4134 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4135 break;
4136 }
4137 wid = the_ins.reloc[m].wid;
4138 if (wid == 0)
4139 continue;
4140 the_ins.reloc[m].wid = 0;
4141 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4142
4143 fixP = fix_new_exp (frag_now,
4144 ((toP - frag_now->fr_literal)
4145 - the_ins.numo * 2 + the_ins.reloc[m].n),
4146 wid,
4147 &the_ins.reloc[m].exp,
4148 the_ins.reloc[m].pcrel,
4149 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4150 the_ins.reloc[m].pic_reloc));
4151 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4152 }
4153 (void) frag_var (rs_machine_dependent, 10, 0,
4154 (relax_substateT) (the_ins.fragb[n].fragty),
4155 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4156 }
4157 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4158 shorts_this_frag = 0;
4159 if (n)
4160 {
055d1eb0 4161 toP = frag_more (n * 2);
252b5132
RH		 4162 while (n--)
4163 {
4164 md_number_to_chars (toP, (long) (*fromP), 2);
4165 toP += 2;
4166 fromP++;
4167 shorts_this_frag++;
4168 }
4169 }
4170 for (m = 0; m < the_ins.nrel; m++)
4171 {
4172 int wid;
4173
4174 wid = the_ins.reloc[m].wid;
4175 if (wid == 0)
4176 continue;
4177 the_ins.reloc[m].wid = 0;
4178 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4179
4180 fixP = fix_new_exp (frag_now,
4181 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4182 - shorts_this_frag * 2),
4183 wid,
4184 &the_ins.reloc[m].exp,
4185 the_ins.reloc[m].pcrel,
4186 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4187 the_ins.reloc[m].pic_reloc));
4188 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4189 }
4190}
4191
60fed2d3
NC		 4192/* Comparison function used by qsort to rank the opcode entries by name. */
4193
4194static int
4195m68k_compare_opcode (const void * v1, const void * v2)
4196{
4197 struct m68k_opcode * op1, * op2;
4198 int ret;
4199
03b13e59
NC		 4200 if (v1 == v2)
4201 return 0;
4202
60fed2d3
NC		 4203 op1 = *(struct m68k_opcode **) v1;
4204 op2 = *(struct m68k_opcode **) v2;
4205
4206 /* Compare the two names. If different, return the comparison.
4207 If the same, return the order they are in the opcode table. */
4208 ret = strcmp (op1->name, op2->name);
4209 if (ret)
4210 return ret;
4211 if (op1 < op2)
4212 return -1;
03b13e59 4213 return 1;
60fed2d3
NC		 4214}
4215
252b5132 4216void
60fed2d3 4217md_begin (void)
252b5132 4218{
60fed2d3
NC		 4219 const struct m68k_opcode *ins;
4220 struct m68k_incant *hack, *slak;
4221 const char *retval = 0; /* Empty string, or error msg text. */
4222 int i;
4223
4224 /* Set up hash tables with 68000 instructions.
4225 similar to what the vax assembler does. */
252b5132
RH		 4226 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4227 a copy of it at runtime, adding in the information we want but isn't
4228 there. I think it'd be better to have an awk script hack the table
4229 at compile time. Or even just xstr the table and use it as-is. But
4230 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4231 names. */
4232
252b5132
RH		 4233 if (flag_mri)
4234 {
4235 flag_reg_prefix_optional = 1;
4236 m68k_abspcadd = 1;
4237 if (! m68k_rel32_from_cmdline)
4238 m68k_rel32 = 0;
4239 }
4240
60fed2d3
NC		 4241 /* First sort the opcode table into alphabetical order to seperate
4242 the order that the assembler wants to see the opcodes from the
4243 order that the disassembler wants to see them. */
4244 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4245 if (!m68k_sorted_opcodes)
4246 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
045b540e 4247 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
60fed2d3
NC		 4248
4249 for (i = m68k_numopcodes; i--;)
4250 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4251
4252 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4253 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4254
252b5132
RH		 4255 op_hash = hash_new ();
4256
4257 obstack_begin (&robyn, 4000);
4258 for (i = 0; i < m68k_numopcodes; i++)
4259 {
4260 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4261 do
4262 {
60fed2d3
NC		 4263 ins = m68k_sorted_opcodes[i];
4264
4265 /* We *could* ignore insns that don't match our
4266 arch here by just leaving them out of the hash. */
252b5132
RH		 4267 slak->m_operands = ins->args;
4268 slak->m_opnum = strlen (slak->m_operands) / 2;
4269 slak->m_arch = ins->arch;
4270 slak->m_opcode = ins->opcode;
36759679 4271 /* This is kludgey. */
252b5132
RH		 4272 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4273 if (i + 1 != m68k_numopcodes
60fed2d3 4274 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
252b5132 4275 {
60fed2d3 4276 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4277 i++;
4278 }
4279 else
4280 slak->m_next = 0;
4281 slak = slak->m_next;
4282 }
4283 while (slak);
4284
4285 retval = hash_insert (op_hash, ins->name, (char *) hack);
4286 if (retval)
4287 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4288 }
4289
4290 for (i = 0; i < m68k_numaliases; i++)
4291 {
4292 const char *name = m68k_opcode_aliases[i].primary;
4293 const char *alias = m68k_opcode_aliases[i].alias;
4294 PTR val = hash_find (op_hash, name);
60fed2d3 4295
252b5132
RH		 4296 if (!val)
4297 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4298 retval = hash_insert (op_hash, alias, val);
4299 if (retval)
4300 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4301 }
4302
4303 /* In MRI mode, all unsized branches are variable sized. Normally,
4304 they are word sized. */
4305 if (flag_mri)
4306 {
4307 static struct m68k_opcode_alias mri_aliases[] =
4308 {
4309 { "bhi", "jhi", },
4310 { "bls", "jls", },
4311 { "bcc", "jcc", },
4312 { "bcs", "jcs", },
4313 { "bne", "jne", },
4314 { "beq", "jeq", },
4315 { "bvc", "jvc", },
4316 { "bvs", "jvs", },
4317 { "bpl", "jpl", },
4318 { "bmi", "jmi", },
4319 { "bge", "jge", },
4320 { "blt", "jlt", },
4321 { "bgt", "jgt", },
4322 { "ble", "jle", },
4323 { "bra", "jra", },
4324 { "bsr", "jbsr", },
4325 };
4326
8fce3f5e
AM		 4327 for (i = 0;
4328 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4329 i++)
252b5132
RH		 4330 {
4331 const char *name = mri_aliases[i].primary;
4332 const char *alias = mri_aliases[i].alias;
4333 PTR val = hash_find (op_hash, name);
60fed2d3 4334
252b5132
RH		 4335 if (!val)
4336 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4337 retval = hash_jam (op_hash, alias, val);
4338 if (retval)
4339 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4340 }
4341 }
4342
8fce3f5e 4343 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 4344 {
4345 notend_table[i] = 0;
4346 alt_notend_table[i] = 0;
4347 }
60fed2d3 4348
252b5132
RH		 4349 notend_table[','] = 1;
4350 notend_table['{'] = 1;
4351 notend_table['}'] = 1;
4352 alt_notend_table['a'] = 1;
4353 alt_notend_table['A'] = 1;
4354 alt_notend_table['d'] = 1;
4355 alt_notend_table['D'] = 1;
4356 alt_notend_table['#'] = 1;
4357 alt_notend_table['&'] = 1;
4358 alt_notend_table['f'] = 1;
4359 alt_notend_table['F'] = 1;
4360#ifdef REGISTER_PREFIX
4361 alt_notend_table[REGISTER_PREFIX] = 1;
4362#endif
4363
4364 /* We need to put '(' in alt_notend_table to handle
60fed2d3 4365 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
252b5132
RH		 4366 alt_notend_table['('] = 1;
4367
4368 /* We need to put '@' in alt_notend_table to handle
60fed2d3 4369 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
252b5132
RH		 4370 alt_notend_table['@'] = 1;
4371
4372 /* We need to put digits in alt_notend_table to handle
60fed2d3 4373 bfextu %d0{24:1},%d0 */
252b5132
RH		 4374 alt_notend_table['0'] = 1;
4375 alt_notend_table['1'] = 1;
4376 alt_notend_table['2'] = 1;
4377 alt_notend_table['3'] = 1;
4378 alt_notend_table['4'] = 1;
4379 alt_notend_table['5'] = 1;
4380 alt_notend_table['6'] = 1;
4381 alt_notend_table['7'] = 1;
4382 alt_notend_table['8'] = 1;
4383 alt_notend_table['9'] = 1;
4384
4385#ifndef MIT_SYNTAX_ONLY
4386 /* Insert pseudo ops, these have to go into the opcode table since
36759679 4387 gas expects pseudo ops to start with a dot. */
252b5132
RH		 4388 {
4389 int n = 0;
60fed2d3 4390
252b5132
RH		 4391 while (mote_pseudo_table[n].poc_name)
4392 {
60fed2d3 4393 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4394 hash_insert (op_hash,
4395 mote_pseudo_table[n].poc_name, (char *) hack);
4396 hack->m_operands = 0;
4397 hack->m_opnum = n;
4398 n++;
4399 }
4400 }
4401#endif
4402
4403 init_regtable ();
4404
4405#ifdef OBJ_ELF
4406 record_alignment (text_section, 2);
4407 record_alignment (data_section, 2);
4408 record_alignment (bss_section, 2);
4409#endif
4410}
4411
252b5132
RH		 4412\f
4413/* This is called when a label is defined. */
4414
4415void
31302357 4416m68k_frob_label (symbolS *sym)
252b5132
RH		 4417{
4418 struct label_line *n;
4419
4420 n = (struct label_line *) xmalloc (sizeof *n);
4421 n->next = labels;
4422 n->label = sym;
4423 as_where (&n->file, &n->line);
4424 n->text = 0;
4425 labels = n;
4426 current_label = n;
07a53e5c
RH		 4427
4428#ifdef OBJ_ELF
4429 dwarf2_emit_label (sym);
4430#endif
252b5132
RH		 4431}
4432
4433/* This is called when a value that is not an instruction is emitted. */
4434
4435void
31302357 4436m68k_flush_pending_output (void)
252b5132
RH		 4437{
4438 current_label = NULL;
4439}
4440
4441/* This is called at the end of the assembly, when the final value of
4442 the label is known. We warn if this is a text symbol aligned at an
4443 odd location. */
4444
4445void
31302357 4446m68k_frob_symbol (symbolS *sym)
252b5132
RH		 4447{
4448 if (S_GET_SEGMENT (sym) == reg_section
4449 && (int) S_GET_VALUE (sym) < 0)
4450 {
4451 S_SET_SEGMENT (sym, absolute_section);
4452 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4453 }
4454 else if ((S_GET_VALUE (sym) & 1) != 0)
4455 {
4456 struct label_line *l;
4457
4458 for (l = labels; l != NULL; l = l->next)
4459 {
4460 if (l->label == sym)
4461 {
4462 if (l->text)
4463 as_warn_where (l->file, l->line,
4464 _("text label `%s' aligned to odd boundary"),
4465 S_GET_NAME (sym));
4466 break;
4467 }
4468 }
4469 }
4470}
4471\f
4472/* This is called if we go in or out of MRI mode because of the .mri
4473 pseudo-op. */
4474
4475void
31302357 4476m68k_mri_mode_change (int on)
252b5132
RH		 4477{
4478 if (on)
4479 {
4480 if (! flag_reg_prefix_optional)
4481 {
4482 flag_reg_prefix_optional = 1;
4483#ifdef REGISTER_PREFIX
4484 init_regtable ();
4485#endif
4486 }
4487 m68k_abspcadd = 1;
4488 if (! m68k_rel32_from_cmdline)
4489 m68k_rel32 = 0;
4490 }
4491 else
4492 {
4493 if (! reg_prefix_optional_seen)
4494 {
4495#ifdef REGISTER_PREFIX_OPTIONAL
4496 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4497#else
4498 flag_reg_prefix_optional = 0;
4499#endif
4500#ifdef REGISTER_PREFIX
4501 init_regtable ();
4502#endif
4503 }
4504 m68k_abspcadd = 0;
4505 if (! m68k_rel32_from_cmdline)
4506 m68k_rel32 = 1;
4507 }
4508}
4509
36759679 4510/* Equal to MAX_PRECISION in atof-ieee.c. */
252b5132
RH		 4511#define MAX_LITTLENUMS 6
4512
4513/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4514 of type TYPE, and store the appropriate bytes in *LITP. The number
4515 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4516 returned, or NULL on OK. */
4517
4518char *
31302357 4519md_atof (int type, char *litP, int *sizeP)
252b5132
RH		 4520{
4521 int prec;
4522 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4523 LITTLENUM_TYPE *wordP;
4524 char *t;
4525
4526 switch (type)
4527 {
4528 case 'f':
4529 case 'F':
4530 case 's':
4531 case 'S':
4532 prec = 2;
4533 break;
4534
4535 case 'd':
4536 case 'D':
4537 case 'r':
4538 case 'R':
4539 prec = 4;
4540 break;
4541
4542 case 'x':
4543 case 'X':
4544 prec = 6;
4545 break;
4546
4547 case 'p':
4548 case 'P':
4549 prec = 6;
4550 break;
4551
4552 default:
4553 *sizeP = 0;
4554 return _("Bad call to MD_ATOF()");
4555 }
4556 t = atof_ieee (input_line_pointer, type, words);
4557 if (t)
4558 input_line_pointer = t;
4559
4560 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4561 for (wordP = words; prec--;)
4562 {
4563 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4564 litP += sizeof (LITTLENUM_TYPE);
4565 }
4566 return 0;
4567}
4568
4569void
31302357 4570md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH		 4571{
4572 number_to_chars_bigendian (buf, val, n);
4573}
4574
94f592af 4575void
55cf6793 4576md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 4577{
bbe8ef22 4578 offsetT val = *valP;
252b5132
RH		 4579 addressT upper_limit;
4580 offsetT lower_limit;
4581
4582 /* This is unnecessary but it convinces the native rs6000 compiler
4583 to generate the code we want. */
4584 char *buf = fixP->fx_frag->fr_literal;
4585 buf += fixP->fx_where;
36759679 4586 /* End ibm compiler workaround. */
252b5132 4587
bd17c2c3 4588 val = SEXT (val);
252b5132 4589
94f592af
NC		 4590 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4591 fixP->fx_done = 1;
4592
252b5132
RH		 4593#ifdef OBJ_ELF
4594 if (fixP->fx_addsy)
4595 {
4596 memset (buf, 0, fixP->fx_size);
36759679 4597 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 4598
4599 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4600 && !S_IS_DEFINED (fixP->fx_addsy)
4601 && !S_IS_WEAK (fixP->fx_addsy))
4602 S_SET_WEAK (fixP->fx_addsy);
4603 return;
4604 }
4605#endif
4606
252b5132
RH		 4607 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4608 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4609 return;
252b5132
RH		 4610
4611 switch (fixP->fx_size)
4612 {
94f592af
NC		 4613 /* The cast to offsetT below are necessary to make code
4614 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4615 case 1:
4616 *buf++ = val;
4617 upper_limit = 0x7f;
4618 lower_limit = - (offsetT) 0x80;
4619 break;
4620 case 2:
4621 *buf++ = (val >> 8);
4622 *buf++ = val;
4623 upper_limit = 0x7fff;
4624 lower_limit = - (offsetT) 0x8000;
4625 break;
4626 case 4:
4627 *buf++ = (val >> 24);
4628 *buf++ = (val >> 16);
4629 *buf++ = (val >> 8);
4630 *buf++ = val;
4631 upper_limit = 0x7fffffff;
36759679 4632 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
252b5132
RH		 4633 break;
4634 default:
4635 BAD_CASE (fixP->fx_size);
4636 }
4637
4638 /* Fix up a negative reloc. */
4639 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4640 {
4641 fixP->fx_addsy = fixP->fx_subsy;
4642 fixP->fx_subsy = NULL;
4643 fixP->fx_tcbit = 1;
4644 }
4645
4646 /* For non-pc-relative values, it's conceivable we might get something
4647 like "0xff" for a byte field. So extend the upper part of the range
4648 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4649 so that we can do any range checking at all. */
4650 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4651 upper_limit = upper_limit * 2 + 1;
4652
4653 if ((addressT) val > upper_limit
4654 && (val > 0 || val < lower_limit))
4655 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4656
4657 /* A one byte PC-relative reloc means a short branch. We can't use
4658 a short branch with a value of 0 or -1, because those indicate
4659 different opcodes (branches with longer offsets). fixup_segment
4660 in write.c may have clobbered fx_pcrel, so we need to examine the
4661 reloc type. */
4662 if ((fixP->fx_pcrel
7be1c489 4663 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
252b5132
RH		 4664 && fixP->fx_size == 1
4665 && (fixP->fx_addsy == NULL
4666 || S_IS_DEFINED (fixP->fx_addsy))
4667 && (val == 0 || val == -1))
4668 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4669}
4670
252b5132
RH		 4671/* *fragP has been relaxed to its final size, and now needs to have
4672 the bytes inside it modified to conform to the new size There is UGLY
4673 MAGIC here. ..
4674 */
4675static void
31302357 4676md_convert_frag_1 (fragS *fragP)
252b5132
RH		 4677{
4678 long disp;
252b5132
RH		 4679 fixS *fixP;
4680
4681 /* Address in object code of the displacement. */
4682 register int object_address = fragP->fr_fix + fragP->fr_address;
4683
4684 /* Address in gas core of the place to store the displacement. */
4685 /* This convinces the native rs6000 compiler to generate the code we
92774660 4686 want. */
252b5132
RH		 4687 register char *buffer_address = fragP->fr_literal;
4688 buffer_address += fragP->fr_fix;
36759679 4689 /* End ibm compiler workaround. */
252b5132
RH		 4690
4691 /* The displacement of the address, from current location. */
4692 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4693 disp = (disp + fragP->fr_offset) - object_address;
4694
252b5132
RH		 4695 switch (fragP->fr_subtype)
4696 {
151337e8
NC		 4697 case TAB (BRANCHBWL, BYTE):
4698 case TAB (BRABSJUNC, BYTE):
4699 case TAB (BRABSJCOND, BYTE):
4700 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4701 know (issbyte (disp));
4702 if (disp == 0)
b091f402
AM		 4703 as_bad_where (fragP->fr_file, fragP->fr_line,
4704 _("short branch with zero offset: use :w"));
151337e8 4705 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4706 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4707 fixP->fx_pcrel_adjust = -1;
252b5132 4708 break;
151337e8
NC		 4709 case TAB (BRANCHBWL, SHORT):
4710 case TAB (BRABSJUNC, SHORT):
4711 case TAB (BRABSJCOND, SHORT):
4712 case TAB (BRANCHBW, SHORT):
252b5132 4713 fragP->fr_opcode[1] = 0x00;
151337e8 4714 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4715 1, RELAX_RELOC_PC16);
151337e8
NC		 4716 fragP->fr_fix += 2;
4717 break;
4718 case TAB (BRANCHBWL, LONG):
4719 fragP->fr_opcode[1] = (char) 0xFF;
4720 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4721 1, RELAX_RELOC_PC32);
151337e8 4722 fragP->fr_fix += 4;
252b5132 4723 break;
151337e8
NC		 4724 case TAB (BRABSJUNC, LONG):
4725 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4726 {
36759679 4727 if (flag_keep_pcrel)
6b6e92f4 4728 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
151337e8 4729 fragP->fr_opcode[0] = 0x4E;
36759679 4730 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
151337e8 4731 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3ae647a0 4732 0, RELAX_RELOC_ABS32);
151337e8
NC		 4733 fragP->fr_fix += 4;
4734 }
4735 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4736 {
36759679 4737 if (flag_keep_pcrel)
6b6e92f4 4738 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
151337e8 4739 fragP->fr_opcode[0] = 0x4E;
36759679 4740 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
151337e8 4741 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4742 0, RELAX_RELOC_ABS32);
151337e8 4743 fragP->fr_fix += 4;
252b5132
RH		 4744 }
4745 else
4746 {
151337e8
NC		 4747 /* This cannot happen, because jbsr and jbra are the only two
4748 unconditional branches. */
4749 abort ();
252b5132
RH		 4750 }
4751 break;
151337e8 4752 case TAB (BRABSJCOND, LONG):
36759679 4753 if (flag_keep_pcrel)
6b6e92f4 4754 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
92774660 4755
36759679
NC		 4756 /* Only Bcc 68000 instructions can come here
4757 Change bcc into b!cc/jmp absl long. */
4758 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4759 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
252b5132
RH		 4760
4761 /* JF: these used to be fr_opcode[2,3], but they may be in a
67c1ffbe 4762 different frag, in which case referring to them is a no-no.
92774660 4763 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4764 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4765 *buffer_address++ = (char) 0xf9;
36759679 4766 fragP->fr_fix += 2; /* Account for jmp instruction. */
252b5132 4767 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5cbdaa77 4768 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4769 fragP->fr_fix += 4;
4770 break;
4771 case TAB (FBRANCH, SHORT):
4772 know ((fragP->fr_opcode[1] & 0x40) == 0);
4773 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4774 1, RELAX_RELOC_PC16);
151337e8
NC		 4775 fragP->fr_fix += 2;
4776 break;
4777 case TAB (FBRANCH, LONG):
36759679 4778 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
151337e8 4779 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4780 1, RELAX_RELOC_PC32);
252b5132 4781 fragP->fr_fix += 4;
252b5132 4782 break;
151337e8
NC		 4783 case TAB (DBCCLBR, SHORT):
4784 case TAB (DBCCABSJ, SHORT):
4785 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4786 1, RELAX_RELOC_PC16);
151337e8
NC		 4787 fragP->fr_fix += 2;
4788 break;
4789 case TAB (DBCCLBR, LONG):
36759679
NC		 4790 /* Only DBcc instructions can come here.
4791 Change dbcc into dbcc/bral.
4792 JF: these used to be fr_opcode[2-7], but that's wrong. */
4793 if (flag_keep_pcrel)
6b6e92f4 4794 as_fatal (_("Tried to convert DBcc to absolute jump"));
28e7409f 4795
36759679 4796 *buffer_address++ = 0x00; /* Branch offset = 4. */
252b5132 4797 *buffer_address++ = 0x04;
36759679 4798 *buffer_address++ = 0x60; /* Put in bra pc+6. */
252b5132 4799 *buffer_address++ = 0x06;
151337e8
NC		 4800 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4801 *buffer_address++ = (char) 0xff;
252b5132 4802
36759679 4803 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4804 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
5cbdaa77 4805 RELAX_RELOC_PC32);
252b5132 4806 fragP->fr_fix += 4;
252b5132 4807 break;
151337e8 4808 case TAB (DBCCABSJ, LONG):
36759679
NC		 4809 /* Only DBcc instructions can come here.
4810 Change dbcc into dbcc/jmp.
4811 JF: these used to be fr_opcode[2-7], but that's wrong. */
4812 if (flag_keep_pcrel)
6b6e92f4 4813 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4814
36759679 4815 *buffer_address++ = 0x00; /* Branch offset = 4. */
151337e8 4816 *buffer_address++ = 0x04;
36759679 4817 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
151337e8 4818 *buffer_address++ = 0x06;
36759679 4819 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
151337e8
NC		 4820 *buffer_address++ = (char) 0xf9;
4821
36759679 4822 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4823 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
5cbdaa77 4824 RELAX_RELOC_ABS32);
252b5132 4825 fragP->fr_fix += 4;
252b5132 4826 break;
151337e8 4827 case TAB (PCREL1632, SHORT):
252b5132
RH		 4828 fragP->fr_opcode[1] &= ~0x3F;
4829 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
151337e8 4830 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4831 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 4832 fragP->fr_fix += 2;
252b5132 4833 break;
151337e8 4834 case TAB (PCREL1632, LONG):
252b5132
RH		 4835 /* Already set to mode 7.3; this indicates: PC indirect with
4836 suppressed index, 32-bit displacement. */
4837 *buffer_address++ = 0x01;
4838 *buffer_address++ = 0x70;
4839 fragP->fr_fix += 2;
151337e8 4840 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4841 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4842 fixP->fx_pcrel_adjust = 2;
4843 fragP->fr_fix += 4;
252b5132 4844 break;
252b5132 4845 case TAB (PCINDEX, BYTE):
252b5132
RH		 4846 assert (fragP->fr_fix >= 2);
4847 buffer_address[-2] &= ~1;
151337e8 4848 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4849 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4850 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 4851 break;
4852 case TAB (PCINDEX, SHORT):
252b5132
RH		 4853 assert (fragP->fr_fix >= 2);
4854 buffer_address[-2] |= 0x1;
4855 buffer_address[-1] = 0x20;
4856 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4857 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 4858 fixP->fx_pcrel_adjust = 2;
151337e8 4859 fragP->fr_fix += 2;
252b5132
RH		 4860 break;
4861 case TAB (PCINDEX, LONG):
252b5132
RH		 4862 assert (fragP->fr_fix >= 2);
4863 buffer_address[-2] |= 0x1;
4864 buffer_address[-1] = 0x30;
151337e8 4865 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4866 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4867 fixP->fx_pcrel_adjust = 2;
4868 fragP->fr_fix += 4;
4869 break;
4870 case TAB (ABSTOPCREL, SHORT):
4871 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4872 1, RELAX_RELOC_PC16);
151337e8
NC		 4873 fragP->fr_fix += 2;
4874 break;
4875 case TAB (ABSTOPCREL, LONG):
36759679 4876 if (flag_keep_pcrel)
6b6e92f4 4877 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4878 /* The thing to do here is force it to ABSOLUTE LONG, since
36759679 4879 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
151337e8
NC		 4880 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4881 abort ();
4882 fragP->fr_opcode[1] &= ~0x3F;
4883 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4884 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4885 0, RELAX_RELOC_ABS32);
151337e8 4886 fragP->fr_fix += 4;
252b5132 4887 break;
252b5132
RH		 4888 }
4889}
4890
252b5132 4891void
31302357
AS		 4892md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4893 segT sec ATTRIBUTE_UNUSED,
4894 fragS *fragP)
252b5132
RH		 4895{
4896 md_convert_frag_1 (fragP);
4897}
252b5132
RH		 4898
4899/* Force truly undefined symbols to their maximum size, and generally set up
4900 the frag list to be relaxed
4901 */
4902int
31302357 4903md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 4904{
151337e8 4905 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 4906 switch (fragP->fr_subtype)
4907 {
151337e8
NC		 4908 case TAB (BRANCHBWL, SZ_UNDEF):
4909 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 4910 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 4911 {
151337e8
NC		 4912 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4913 && relaxable_symbol (fragP->fr_symbol))
252b5132 4914 {
151337e8
NC		 4915 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4916 }
4917 else if (flag_short_refs)
4918 {
4919 /* Symbol is undefined and we want short ref. */
4920 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4921 }
4922 else
4923 {
151337e8
NC		 4924 /* Symbol is still undefined. Make it LONG. */
4925 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4926 }
4927 break;
151337e8 4928 }
252b5132 4929
151337e8 4930 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 4931 {
151337e8
NC		 4932 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4933 && relaxable_symbol (fragP->fr_symbol))
252b5132 4934 {
151337e8 4935 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 4936 }
4937 else
4938 {
151337e8
NC		 4939 /* Symbol is undefined and we don't have long branches. */
4940 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4941 }
4942 break;
151337e8 4943 }
252b5132 4944
151337e8 4945 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 4946 case TAB (DBCCLBR, SZ_UNDEF):
4947 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 4948 case TAB (PCREL1632, SZ_UNDEF):
252b5132 4949 {
8ec6253e
NC		 4950 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4951 && relaxable_symbol (fragP->fr_symbol))
151337e8 4952 || flag_short_refs)
252b5132 4953 {
151337e8 4954 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4955 }
4956 else
4957 {
151337e8 4958 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4959 }
4960 break;
151337e8 4961 }
81d4177b 4962
252b5132
RH		 4963 case TAB (PCINDEX, SZ_UNDEF):
4964 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 4965 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 4966 {
4967 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4968 }
4969 else
4970 {
4971 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 4972 }
4973 break;
4974
151337e8
NC		 4975 case TAB (ABSTOPCREL, SZ_UNDEF):
4976 {
4977 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4978 && relaxable_symbol (fragP->fr_symbol)))
4979 {
4980 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 4981 }
4982 else
4983 {
4984 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 4985 }
4986 break;
4987 }
4988
252b5132
RH		 4989 default:
4990 break;
4991 }
4992
151337e8 4993 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 4994 switch (fragP->fr_subtype)
4995 {
151337e8
NC		 4996 case TAB (BRANCHBWL, BYTE):
4997 case TAB (BRABSJUNC, BYTE):
4998 case TAB (BRABSJCOND, BYTE):
4999 case TAB (BRANCHBW, BYTE):
252b5132 5000 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 5001 case we force word mode. If the symbol is at the start of a
5002 frag, and it is the next frag with any data in it (usually
5003 this is just the next frag, but assembler listings may
5004 introduce empty frags), we must use word mode. */
5005 if (fragP->fr_symbol)
252b5132 5006 {
ac62c346 5007 fragS *sym_frag;
252b5132 5008
ac62c346
AM		 5009 sym_frag = symbol_get_frag (fragP->fr_symbol);
5010 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 5011 {
ac62c346
AM		 5012 fragS *l;
5013
23b7f870 5014 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 5015 if (l->fr_fix != 0)
5016 break;
5017 if (l == sym_frag)
5018 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5019 }
5020 }
5021 break;
5022 default:
5023 break;
5024 }
ac62c346 5025 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 5026}
5027
5028#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5029/* the bit-field entries in the relocation_info struct plays hell
5030 with the byte-order problems of cross-assembly. So as a hack,
5031 I added this mach. dependent ri twiddler. Ugly, but it gets
36759679 5032 you there. -KWK */
252b5132
RH		 5033/* on m68k: first 4 bytes are normal unsigned long, next three bytes
5034 are symbolnum, most sig. byte first. Last byte is broken up with
5035 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5036 nibble as nuthin. (on Sun 3 at least) */
5037/* Translate the internal relocation information into target-specific
92774660 5038 format. */
252b5132
RH		 5039#ifdef comment
5040void
31302357 5041md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
252b5132 5042{
36759679 5043 /* This is easy. */
252b5132 5044 md_number_to_chars (the_bytes, ri->r_address, 4);
36759679 5045 /* Now the fun stuff. */
252b5132 5046 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
36759679
NC		 5047 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5048 the_bytes[6] = ri->r_symbolnum & 0x0ff;
31302357
AS		 5049 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5050 | ((ri->r_length << 5) & 0x60)
5051 | ((ri->r_extern << 4) & 0x10));
252b5132
RH		 5052}
5053
36759679 5054#endif
252b5132 5055
252b5132
RH		 5056#endif /* OBJ_AOUT or OBJ_BOUT */
5057
5058#ifndef WORKING_DOT_WORD
2b4f075a
HPN		 5059int md_short_jump_size = 4;
5060int md_long_jump_size = 6;
252b5132
RH		 5061
5062void
31302357
AS		 5063md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5064 fragS *frag ATTRIBUTE_UNUSED,
5065 symbolS *to_symbol ATTRIBUTE_UNUSED)
252b5132
RH		 5066{
5067 valueT offset;
5068
5069 offset = to_addr - (from_addr + 2);
5070
5071 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5072 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5073}
5074
5075void
31302357
AS		 5076md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5077 fragS *frag, symbolS *to_symbol)
252b5132
RH		 5078{
5079 valueT offset;
5080
6b6e92f4 5081 if (!HAVE_LONG_BRANCH (current_architecture))
252b5132 5082 {
36759679 5083 if (flag_keep_pcrel)
6b6e92f4 5084 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 5085 offset = to_addr - S_GET_VALUE (to_symbol);
5086 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5087 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5088 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5089 0, NO_RELOC);
5090 }
5091 else
5092 {
5093 offset = to_addr - (from_addr + 2);
5094 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5095 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5096 }
5097}
5098
5099#endif
5100
5101/* Different values of OK tell what its OK to return. Things that
5102 aren't OK are an error (what a shock, no?)
5103
5104 0: Everything is OK
3e602632
NC		 5105 10: Absolute 1:8 only
5106 20: Absolute 0:7 only
5107 30: absolute 0:15 only
5108 40: Absolute 0:31 only
5109 50: absolute 0:127 only
252b5132 5110 55: absolute -64:63 only
3e602632
NC		 5111 60: absolute -128:127 only
5112 70: absolute 0:4095 only
5113 80: absolute -1, 1:7 only
5114 90: No bignums. */
252b5132
RH		 5115
5116static int
31302357 5117get_num (struct m68k_exp *exp, int ok)
252b5132
RH		 5118{
5119 if (exp->exp.X_op == O_absent)
5120 {
36759679 5121 /* Do the same thing the VAX asm does. */
252b5132
RH		 5122 op (exp) = O_constant;
5123 adds (exp) = 0;
5124 subs (exp) = 0;
5125 offs (exp) = 0;
5126 if (ok == 10)
5127 {
5128 as_warn (_("expression out of range: defaulting to 1"));
5129 offs (exp) = 1;
5130 }
5131 }
5132 else if (exp->exp.X_op == O_constant)
5133 {
5134 switch (ok)
5135 {
5136 case 10:
bd17c2c3 5137 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
252b5132
RH		 5138 {
5139 as_warn (_("expression out of range: defaulting to 1"));
5140 offs (exp) = 1;
5141 }
5142 break;
5143 case 20:
bd17c2c3 5144 if ((valueT) TRUNC (offs (exp)) > 7)
252b5132
RH		 5145 goto outrange;
5146 break;
5147 case 30:
bd17c2c3 5148 if ((valueT) TRUNC (offs (exp)) > 15)
252b5132
RH		 5149 goto outrange;
5150 break;
5151 case 40:
bd17c2c3 5152 if ((valueT) TRUNC (offs (exp)) > 32)
252b5132
RH		 5153 goto outrange;
5154 break;
5155 case 50:
bd17c2c3 5156 if ((valueT) TRUNC (offs (exp)) > 127)
252b5132
RH		 5157 goto outrange;
5158 break;
5159 case 55:
bd17c2c3 5160 if ((valueT) SEXT (offs (exp)) + 64 > 127)
252b5132
RH		 5161 goto outrange;
5162 break;
5163 case 60:
bd17c2c3 5164 if ((valueT) SEXT (offs (exp)) + 128 > 255)
252b5132
RH		 5165 goto outrange;
5166 break;
5167 case 70:
bd17c2c3 5168 if ((valueT) TRUNC (offs (exp)) > 4095)
252b5132
RH		 5169 {
5170 outrange:
5171 as_warn (_("expression out of range: defaulting to 0"));
5172 offs (exp) = 0;
5173 }
5174 break;
3e602632 5175 case 80:
bd17c2c3
AM		 5176 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5177 && (valueT) TRUNC (offs (exp)) - 1 > 6)
3e602632
NC		 5178 {
5179 as_warn (_("expression out of range: defaulting to 1"));
5180 offs (exp) = 1;
5181 }
5182 break;
252b5132
RH		 5183 default:
5184 break;
5185 }
5186 }
5187 else if (exp->exp.X_op == O_big)
5188 {
36759679 5189 if (offs (exp) <= 0 /* flonum. */
3e602632 5190 && (ok == 90 /* no bignums */
36759679 5191 || (ok > 10 /* Small-int ranges including 0 ok. */
252b5132
RH		 5192 /* If we have a flonum zero, a zero integer should
5193 do as well (e.g., in moveq). */
5194 && generic_floating_point_number.exponent == 0
5195 && generic_floating_point_number.low[0] == 0)))
5196 {
36759679 5197 /* HACK! Turn it into a long. */
252b5132
RH		 5198 LITTLENUM_TYPE words[6];
5199
36759679 5200 gen_to_words (words, 2, 8L); /* These numbers are magic! */
252b5132
RH		 5201 op (exp) = O_constant;
5202 adds (exp) = 0;
5203 subs (exp) = 0;
5204 offs (exp) = words[1] | (words[0] << 16);
5205 }
5206 else if (ok != 0)
5207 {
5208 op (exp) = O_constant;
5209 adds (exp) = 0;
5210 subs (exp) = 0;
5211 offs (exp) = (ok == 10) ? 1 : 0;
5212 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5213 (long) offs (exp));
252b5132
RH		 5214 }
5215 }
5216 else
5217 {
3e602632 5218 if (ok >= 10 && ok <= 80)
252b5132
RH		 5219 {
5220 op (exp) = O_constant;
5221 adds (exp) = 0;
5222 subs (exp) = 0;
5223 offs (exp) = (ok == 10) ? 1 : 0;
5224 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5225 (long) offs (exp));
252b5132
RH		 5226 }
5227 }
5228
5229 if (exp->size != SIZE_UNSPEC)
5230 {
5231 switch (exp->size)
5232 {
5233 case SIZE_UNSPEC:
5234 case SIZE_LONG:
5235 break;
5236 case SIZE_BYTE:
5237 if (!isbyte (offs (exp)))
5238 as_warn (_("expression doesn't fit in BYTE"));
5239 break;
5240 case SIZE_WORD:
5241 if (!isword (offs (exp)))
5242 as_warn (_("expression doesn't fit in WORD"));
5243 break;
5244 }
5245 }
5246
5247 return offs (exp);
5248}
5249
5250/* These are the back-ends for the various machine dependent pseudo-ops. */
5251
5252static void
31302357 5253s_data1 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5254{
5255 subseg_set (data_section, 1);
5256 demand_empty_rest_of_line ();
5257}
5258
5259static void
31302357 5260s_data2 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5261{
5262 subseg_set (data_section, 2);
5263 demand_empty_rest_of_line ();
5264}
5265
5266static void
31302357 5267s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5268{
5269 /* We don't support putting frags in the BSS segment, we fake it
5270 by marking in_bss, then looking at s_skip for clues. */
5271
5272 subseg_set (bss_section, 0);
5273 demand_empty_rest_of_line ();
5274}
5275
5276static void
31302357 5277s_even (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5278{
5279 register int temp;
5280 register long temp_fill;
5281
5282 temp = 1; /* JF should be 2? */
5283 temp_fill = get_absolute_expression ();
92774660 5284 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5285 frag_align (temp, (int) temp_fill, 0);
5286 demand_empty_rest_of_line ();
5287 record_alignment (now_seg, temp);
5288}
5289
5290static void
31302357 5291s_proc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5292{
5293 demand_empty_rest_of_line ();
5294}
5295\f
5296/* Pseudo-ops handled for MRI compatibility. */
5297
5298/* This function returns non-zero if the argument is a conditional
5299 pseudo-op. This is called when checking whether a pending
5300 alignment is needed. */
5301
5302int
31302357 5303m68k_conditional_pseudoop (pseudo_typeS *pop)
252b5132
RH		 5304{
5305 return (pop->poc_handler == s_mri_if
5306 || pop->poc_handler == s_mri_else);
5307}
5308
5309/* Handle an MRI style chip specification. */
5310
5311static void
31302357 5312mri_chip (void)
252b5132
RH		 5313{
5314 char *s;
5315 char c;
5316 int i;
5317
5318 s = input_line_pointer;
5319 /* We can't use get_symbol_end since the processor names are not proper
5320 symbols. */
5321 while (is_part_of_name (c = *input_line_pointer++))
5322 ;
5323 *--input_line_pointer = 0;
266abb8f
NS		 5324 for (i = 0; m68k_cpus[i].name; i++)
5325 if (strcasecmp (s, m68k_cpus[i].name) == 0)
252b5132 5326 break;
266abb8f 5327 if (!m68k_cpus[i].name)
252b5132
RH		 5328 {
5329 as_bad (_("%s: unrecognized processor name"), s);
5330 *input_line_pointer = c;
5331 ignore_rest_of_line ();
5332 return;
5333 }
5334 *input_line_pointer = c;
5335
5336 if (*input_line_pointer == '/')
5337 current_architecture = 0;
5338 else
5339 current_architecture &= m68881 | m68851;
266abb8f 5340 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
2da12c60 5341 control_regs = m68k_cpus[i].control_regs;
252b5132
RH		 5342
5343 while (*input_line_pointer == '/')
5344 {
5345 ++input_line_pointer;
5346 s = input_line_pointer;
5347 /* We can't use get_symbol_end since the processor names are not
5348 proper symbols. */
5349 while (is_part_of_name (c = *input_line_pointer++))
5350 ;
5351 *--input_line_pointer = 0;
5352 if (strcmp (s, "68881") == 0)
5353 current_architecture |= m68881;
5354 else if (strcmp (s, "68851") == 0)
5355 current_architecture |= m68851;
5356 *input_line_pointer = c;
5357 }
252b5132
RH		 5358}
5359
5360/* The MRI CHIP pseudo-op. */
5361
5362static void
31302357 5363s_chip (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5364{
5365 char *stop = NULL;
5366 char stopc;
5367
5368 if (flag_mri)
5369 stop = mri_comment_field (&stopc);
5370 mri_chip ();
5371 if (flag_mri)
5372 mri_comment_end (stop, stopc);
5373 demand_empty_rest_of_line ();
5374}
5375
5376/* The MRI FOPT pseudo-op. */
5377
5378static void
31302357 5379s_fopt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5380{
5381 SKIP_WHITESPACE ();
5382
5383 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5384 {
5385 int temp;
5386
5387 input_line_pointer += 3;
5388 temp = get_absolute_expression ();
5389 if (temp < 0 || temp > 7)
5390 as_bad (_("bad coprocessor id"));
5391 else
5392 m68k_float_copnum = COP0 + temp;
5393 }
5394 else
5395 {
5396 as_bad (_("unrecognized fopt option"));
5397 ignore_rest_of_line ();
5398 return;
5399 }
5400
5401 demand_empty_rest_of_line ();
5402}
5403
5404/* The structure used to handle the MRI OPT pseudo-op. */
5405
5406struct opt_action
5407{
5408 /* The name of the option. */
5409 const char *name;
5410
5411 /* If this is not NULL, just call this function. The first argument
5412 is the ARG field of this structure, the second argument is
5413 whether the option was negated. */
31302357 5414 void (*pfn) (int arg, int on);
252b5132
RH		 5415
5416 /* If this is not NULL, and the PFN field is NULL, set the variable
5417 this points to. Set it to the ARG field if the option was not
5418 negated, and the NOTARG field otherwise. */
5419 int *pvar;
5420
5421 /* The value to pass to PFN or to assign to *PVAR. */
5422 int arg;
5423
5424 /* The value to assign to *PVAR if the option is negated. If PFN is
5425 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5426 the option may not be negated. */
5427 int notarg;
5428};
5429
5430/* The table used to handle the MRI OPT pseudo-op. */
5431
31302357
AS		 5432static void skip_to_comma (int, int);
5433static void opt_nest (int, int);
5434static void opt_chip (int, int);
5435static void opt_list (int, int);
5436static void opt_list_symbols (int, int);
252b5132
RH		 5437
5438static const struct opt_action opt_table[] =
5439{
5440 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5441
5442 /* We do relaxing, so there is little use for these options. */
5443 { "b", 0, 0, 0, 0 },
5444 { "brs", 0, 0, 0, 0 },
5445 { "brb", 0, 0, 0, 0 },
5446 { "brl", 0, 0, 0, 0 },
5447 { "brw", 0, 0, 0, 0 },
5448
5449 { "c", 0, 0, 0, 0 },
5450 { "cex", 0, 0, 0, 0 },
5451 { "case", 0, &symbols_case_sensitive, 1, 0 },
5452 { "cl", 0, 0, 0, 0 },
5453 { "cre", 0, 0, 0, 0 },
5454 { "d", 0, &flag_keep_locals, 1, 0 },
5455 { "e", 0, 0, 0, 0 },
5456 { "f", 0, &flag_short_refs, 1, 0 },
5457 { "frs", 0, &flag_short_refs, 1, 0 },
5458 { "frl", 0, &flag_short_refs, 0, 1 },
5459 { "g", 0, 0, 0, 0 },
5460 { "i", 0, 0, 0, 0 },
5461 { "m", 0, 0, 0, 0 },
5462 { "mex", 0, 0, 0, 0 },
5463 { "mc", 0, 0, 0, 0 },
5464 { "md", 0, 0, 0, 0 },
5465 { "nest", opt_nest, 0, 0, 0 },
5466 { "next", skip_to_comma, 0, 0, 0 },
5467 { "o", 0, 0, 0, 0 },
5468 { "old", 0, 0, 0, 0 },
5469 { "op", skip_to_comma, 0, 0, 0 },
5470 { "pco", 0, 0, 0, 0 },
5471 { "p", opt_chip, 0, 0, 0 },
5472 { "pcr", 0, 0, 0, 0 },
5473 { "pcs", 0, 0, 0, 0 },
5474 { "r", 0, 0, 0, 0 },
5475 { "quick", 0, &m68k_quick, 1, 0 },
5476 { "rel32", 0, &m68k_rel32, 1, 0 },
5477 { "s", opt_list, 0, 0, 0 },
5478 { "t", opt_list_symbols, 0, 0, 0 },
5479 { "w", 0, &flag_no_warnings, 0, 1 },
5480 { "x", 0, 0, 0, 0 }
5481};
5482
8fce3f5e 5483#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5484
5485/* The MRI OPT pseudo-op. */
5486
5487static void
31302357 5488s_opt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5489{
5490 do
5491 {
5492 int t;
5493 char *s;
5494 char c;
5495 int i;
5496 const struct opt_action *o;
5497
5498 SKIP_WHITESPACE ();
5499
5500 t = 1;
5501 if (*input_line_pointer == '-')
5502 {
5503 ++input_line_pointer;
5504 t = 0;
5505 }
5506 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5507 {
5508 input_line_pointer += 2;
5509 t = 0;
5510 }
5511
5512 s = input_line_pointer;
5513 c = get_symbol_end ();
5514
5515 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5516 {
5517 if (strcasecmp (s, o->name) == 0)
5518 {
5519 if (o->pfn)
5520 {
5521 /* Restore input_line_pointer now in case the option
5522 takes arguments. */
5523 *input_line_pointer = c;
5524 (*o->pfn) (o->arg, t);
5525 }
5526 else if (o->pvar != NULL)
5527 {
5528 if (! t && o->arg == o->notarg)
5529 as_bad (_("option `%s' may not be negated"), s);
5530 *input_line_pointer = c;
5531 *o->pvar = t ? o->arg : o->notarg;
5532 }
5533 else
5534 *input_line_pointer = c;
5535 break;
5536 }
5537 }
5538 if (i >= OPTCOUNT)
5539 {
5540 as_bad (_("option `%s' not recognized"), s);
5541 *input_line_pointer = c;
5542 }
5543 }
5544 while (*input_line_pointer++ == ',');
5545
5546 /* Move back to terminating character. */
5547 --input_line_pointer;
5548 demand_empty_rest_of_line ();
5549}
5550
5551/* Skip ahead to a comma. This is used for OPT options which we do
67c1ffbe 5552 not support and which take arguments. */
252b5132
RH		 5553
5554static void
31302357 5555skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5556{
5557 while (*input_line_pointer != ','
5558 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5559 ++input_line_pointer;
5560}
5561
5562/* Handle the OPT NEST=depth option. */
5563
5564static void
31302357 5565opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5566{
5567 if (*input_line_pointer != '=')
5568 {
5569 as_bad (_("bad format of OPT NEST=depth"));
5570 return;
5571 }
5572
5573 ++input_line_pointer;
5574 max_macro_nest = get_absolute_expression ();
5575}
5576
5577/* Handle the OPT P=chip option. */
5578
5579static void
31302357 5580opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5581{
5582 if (*input_line_pointer != '=')
5583 {
5584 /* This is just OPT P, which we do not support. */
5585 return;
5586 }
5587
5588 ++input_line_pointer;
5589 mri_chip ();
5590}
5591
5592/* Handle the OPT S option. */
5593
5594static void
31302357 5595opt_list (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5596{
5597 listing_list (on);
5598}
5599
5600/* Handle the OPT T option. */
5601
5602static void
31302357 5603opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5604{
5605 if (on)
5606 listing |= LISTING_SYMBOLS;
5607 else
8a104df9 5608 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5609}
5610
5611/* Handle the MRI REG pseudo-op. */
5612
5613static void
31302357 5614s_reg (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5615{
5616 char *s;
5617 int c;
5618 struct m68k_op rop;
5619 int mask;
5620 char *stop = NULL;
5621 char stopc;
5622
5623 if (line_label == NULL)
5624 {
5625 as_bad (_("missing label"));
5626 ignore_rest_of_line ();
5627 return;
5628 }
5629
5630 if (flag_mri)
5631 stop = mri_comment_field (&stopc);
5632
5633 SKIP_WHITESPACE ();
5634
5635 s = input_line_pointer;
3882b010 5636 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5637#ifdef REGISTER_PREFIX
5638 || *input_line_pointer == REGISTER_PREFIX
5639#endif
5640 || *input_line_pointer == '/'
5641 || *input_line_pointer == '-')
5642 ++input_line_pointer;
5643 c = *input_line_pointer;
5644 *input_line_pointer = '\0';
5645
5646 if (m68k_ip_op (s, &rop) != 0)
5647 {
5648 if (rop.error == NULL)
5649 as_bad (_("bad register list"));
5650 else
5651 as_bad (_("bad register list: %s"), rop.error);
5652 *input_line_pointer = c;
5653 ignore_rest_of_line ();
5654 return;
5655 }
5656
5657 *input_line_pointer = c;
5658
5659 if (rop.mode == REGLST)
5660 mask = rop.mask;
5661 else if (rop.mode == DREG)
5662 mask = 1 << (rop.reg - DATA0);
5663 else if (rop.mode == AREG)
5664 mask = 1 << (rop.reg - ADDR0 + 8);
5665 else if (rop.mode == FPREG)
5666 mask = 1 << (rop.reg - FP0 + 16);
5667 else if (rop.mode == CONTROL
5668 && rop.reg == FPI)
5669 mask = 1 << 24;
5670 else if (rop.mode == CONTROL
5671 && rop.reg == FPS)
5672 mask = 1 << 25;
5673 else if (rop.mode == CONTROL
5674 && rop.reg == FPC)
5675 mask = 1 << 26;
5676 else
5677 {
5678 as_bad (_("bad register list"));
5679 ignore_rest_of_line ();
5680 return;
5681 }
5682
5683 S_SET_SEGMENT (line_label, reg_section);
5684 S_SET_VALUE (line_label, ~mask);
49309057 5685 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5686
5687 if (flag_mri)
5688 mri_comment_end (stop, stopc);
5689
5690 demand_empty_rest_of_line ();
5691}
5692
5693/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5694
5695struct save_opts
5696{
5697 struct save_opts *next;
5698 int abspcadd;
5699 int symbols_case_sensitive;
5700 int keep_locals;
5701 int short_refs;
5702 int architecture;
2da12c60 5703 const enum m68k_register *control_regs;
252b5132
RH		 5704 int quick;
5705 int rel32;
5706 int listing;
5707 int no_warnings;
5708 /* FIXME: We don't save OPT S. */
5709};
5710
5711/* This variable holds the stack of saved options. */
5712
5713static struct save_opts *save_stack;
5714
5715/* The MRI SAVE pseudo-op. */
5716
5717static void
31302357 5718s_save (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5719{
5720 struct save_opts *s;
5721
5722 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5723 s->abspcadd = m68k_abspcadd;
5724 s->symbols_case_sensitive = symbols_case_sensitive;
5725 s->keep_locals = flag_keep_locals;
5726 s->short_refs = flag_short_refs;
5727 s->architecture = current_architecture;
2da12c60 5728 s->control_regs = control_regs;
252b5132
RH		 5729 s->quick = m68k_quick;
5730 s->rel32 = m68k_rel32;
5731 s->listing = listing;
5732 s->no_warnings = flag_no_warnings;
5733
5734 s->next = save_stack;
5735 save_stack = s;
5736
5737 demand_empty_rest_of_line ();
5738}
5739
5740/* The MRI RESTORE pseudo-op. */
5741
5742static void
31302357 5743s_restore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5744{
5745 struct save_opts *s;
5746
5747 if (save_stack == NULL)
5748 {
5749 as_bad (_("restore without save"));
5750 ignore_rest_of_line ();
5751 return;
5752 }
5753
5754 s = save_stack;
5755 save_stack = s->next;
5756
5757 m68k_abspcadd = s->abspcadd;
5758 symbols_case_sensitive = s->symbols_case_sensitive;
5759 flag_keep_locals = s->keep_locals;
5760 flag_short_refs = s->short_refs;
5761 current_architecture = s->architecture;
2da12c60 5762 control_regs = s->control_regs;
252b5132
RH		 5763 m68k_quick = s->quick;
5764 m68k_rel32 = s->rel32;
5765 listing = s->listing;
5766 flag_no_warnings = s->no_warnings;
5767
5768 free (s);
5769
5770 demand_empty_rest_of_line ();
5771}
5772
5773/* Types of MRI structured control directives. */
5774
5775enum mri_control_type
5776{
5777 mri_for,
5778 mri_if,
5779 mri_repeat,
5780 mri_while
5781};
5782
5783/* This structure is used to stack the MRI structured control
5784 directives. */
5785
5786struct mri_control_info
5787{
5788 /* The directive within which this one is enclosed. */
5789 struct mri_control_info *outer;
5790
5791 /* The type of directive. */
5792 enum mri_control_type type;
5793
5794 /* Whether an ELSE has been in an IF. */
5795 int else_seen;
5796
5797 /* The add or sub statement at the end of a FOR. */
5798 char *incr;
5799
5800 /* The label of the top of a FOR or REPEAT loop. */
5801 char *top;
5802
5803 /* The label to jump to for the next iteration, or the else
5804 expression of a conditional. */
5805 char *next;
5806
5807 /* The label to jump to to break out of the loop, or the label past
5808 the end of a conditional. */
5809 char *bottom;
5810};
5811
5812/* The stack of MRI structured control directives. */
5813
5814static struct mri_control_info *mri_control_stack;
5815
5816/* The current MRI structured control directive index number, used to
5817 generate label names. */
5818
5819static int mri_control_index;
5820
252b5132
RH		 5821/* Assemble an instruction for an MRI structured control directive. */
5822
5823static void
31302357 5824mri_assemble (char *str)
252b5132
RH		 5825{
5826 char *s;
5827
5828 /* md_assemble expects the opcode to be in lower case. */
5829 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 5830 *s = TOLOWER (*s);
252b5132
RH		 5831
5832 md_assemble (str);
5833}
5834
5835/* Generate a new MRI label structured control directive label name. */
5836
5837static char *
31302357 5838mri_control_label (void)
252b5132
RH		 5839{
5840 char *n;
5841
5842 n = (char *) xmalloc (20);
5843 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5844 ++mri_control_index;
5845 return n;
5846}
5847
5848/* Create a new MRI structured control directive. */
5849
5850static struct mri_control_info *
31302357 5851push_mri_control (enum mri_control_type type)
252b5132
RH		 5852{
5853 struct mri_control_info *n;
5854
5855 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5856
5857 n->type = type;
5858 n->else_seen = 0;
5859 if (type == mri_if || type == mri_while)
5860 n->top = NULL;
5861 else
5862 n->top = mri_control_label ();
5863 n->next = mri_control_label ();
5864 n->bottom = mri_control_label ();
5865
5866 n->outer = mri_control_stack;
5867 mri_control_stack = n;
5868
5869 return n;
5870}
5871
5872/* Pop off the stack of MRI structured control directives. */
5873
5874static void
31302357 5875pop_mri_control (void)
252b5132
RH		 5876{
5877 struct mri_control_info *n;
5878
5879 n = mri_control_stack;
5880 mri_control_stack = n->outer;
5881 if (n->top != NULL)
5882 free (n->top);
5883 free (n->next);
5884 free (n->bottom);
5885 free (n);
5886}
5887
5888/* Recognize a condition code in an MRI structured control expression. */
5889
5890static int
31302357 5891parse_mri_condition (int *pcc)
252b5132
RH		 5892{
5893 char c1, c2;
5894
5895 know (*input_line_pointer == '<');
5896
5897 ++input_line_pointer;
5898 c1 = *input_line_pointer++;
5899 c2 = *input_line_pointer++;
5900
5901 if (*input_line_pointer != '>')
5902 {
5903 as_bad (_("syntax error in structured control directive"));
5904 return 0;
5905 }
5906
5907 ++input_line_pointer;
5908 SKIP_WHITESPACE ();
5909
3882b010
L		 5910 c1 = TOLOWER (c1);
5911 c2 = TOLOWER (c2);
252b5132
RH		 5912
5913 *pcc = (c1 << 8) | c2;
5914
5915 return 1;
5916}
5917
5918/* Parse a single operand in an MRI structured control expression. */
5919
5920static int
31302357
AS		 5921parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
5922 char **rightstart, char **rightstop)
252b5132
RH		 5923{
5924 char *s;
5925
5926 SKIP_WHITESPACE ();
5927
5928 *pcc = -1;
5929 *leftstart = NULL;
5930 *leftstop = NULL;
5931 *rightstart = NULL;
5932 *rightstop = NULL;
5933
5934 if (*input_line_pointer == '<')
5935 {
5936 /* It's just a condition code. */
5937 return parse_mri_condition (pcc);
5938 }
5939
5940 /* Look ahead for the condition code. */
5941 for (s = input_line_pointer; *s != '\0'; ++s)
5942 {
5943 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5944 break;
5945 }
5946 if (*s == '\0')
5947 {
5948 as_bad (_("missing condition code in structured control directive"));
5949 return 0;
5950 }
5951
5952 *leftstart = input_line_pointer;
5953 *leftstop = s;
5954 if (*leftstop > *leftstart
5955 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5956 --*leftstop;
5957
5958 input_line_pointer = s;
5959 if (! parse_mri_condition (pcc))
5960 return 0;
5961
5962 /* Look ahead for AND or OR or end of line. */
5963 for (s = input_line_pointer; *s != '\0'; ++s)
5964 {
e1f44d10
NC		 5965 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5966 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5967 ^^^ ^^ */
8a104df9
KH		 5968 if ((s == input_line_pointer
5969 || *(s-1) == ' '
5970 || *(s-1) == '\t')
5971 && ((strncasecmp (s, "AND", 3) == 0
5972 && (s[3] == '.' || ! is_part_of_name (s[3])))
5973 || (strncasecmp (s, "OR", 2) == 0
5974 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5975 break;
252b5132
RH		 5976 }
5977
5978 *rightstart = input_line_pointer;
5979 *rightstop = s;
5980 if (*rightstop > *rightstart
5981 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5982 --*rightstop;
5983
5984 input_line_pointer = s;
5985
5986 return 1;
5987}
5988
5989#define MCC(b1, b2) (((b1) << 8) | (b2))
5990
5991/* Swap the sense of a condition. This changes the condition so that
5992 it generates the same result when the operands are swapped. */
5993
5994static int
31302357 5995swap_mri_condition (int cc)
252b5132
RH		 5996{
5997 switch (cc)
5998 {
5999 case MCC ('h', 'i'): return MCC ('c', 's');
6000 case MCC ('l', 's'): return MCC ('c', 'c');
36759679 6001 /* <HS> is an alias for <CC>. */
e1f44d10 6002 case MCC ('h', 's'):
252b5132 6003 case MCC ('c', 'c'): return MCC ('l', 's');
36759679 6004 /* <LO> is an alias for <CS>. */
e1f44d10 6005 case MCC ('l', 'o'):
252b5132
RH		 6006 case MCC ('c', 's'): return MCC ('h', 'i');
6007 case MCC ('p', 'l'): return MCC ('m', 'i');
6008 case MCC ('m', 'i'): return MCC ('p', 'l');
6009 case MCC ('g', 'e'): return MCC ('l', 'e');
6010 case MCC ('l', 't'): return MCC ('g', 't');
6011 case MCC ('g', 't'): return MCC ('l', 't');
6012 case MCC ('l', 'e'): return MCC ('g', 'e');
36759679 6013 /* Issue a warning for conditions we can not swap. */
e1f44d10
NC		 6014 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6015 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6016 case MCC ('v', 'c'):
6017 case MCC ('v', 's'):
6018 default :
6019 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6020 (char) (cc >> 8), (char) (cc));
6021 break;
252b5132
RH		 6022 }
6023 return cc;
6024}
6025
6026/* Reverse the sense of a condition. */
6027
6028static int
31302357 6029reverse_mri_condition (int cc)
252b5132
RH		 6030{
6031 switch (cc)
6032 {
6033 case MCC ('h', 'i'): return MCC ('l', 's');
6034 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 6035 /* <HS> is an alias for <CC> */
6036 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 6037 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 6038 /* <LO> is an alias for <CS> */
6039 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 6040 case MCC ('c', 's'): return MCC ('c', 'c');
6041 case MCC ('n', 'e'): return MCC ('e', 'q');
6042 case MCC ('e', 'q'): return MCC ('n', 'e');
6043 case MCC ('v', 'c'): return MCC ('v', 's');
6044 case MCC ('v', 's'): return MCC ('v', 'c');
6045 case MCC ('p', 'l'): return MCC ('m', 'i');
6046 case MCC ('m', 'i'): return MCC ('p', 'l');
6047 case MCC ('g', 'e'): return MCC ('l', 't');
6048 case MCC ('l', 't'): return MCC ('g', 'e');
6049 case MCC ('g', 't'): return MCC ('l', 'e');
6050 case MCC ('l', 'e'): return MCC ('g', 't');
6051 }
6052 return cc;
6053}
6054
6055/* Build an MRI structured control expression. This generates test
6056 and branch instructions. It goes to TRUELAB if the condition is
6057 true, and to FALSELAB if the condition is false. Exactly one of
6058 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6059 is the size qualifier for the expression. EXTENT is the size to
6060 use for the branch. */
6061
6062static void
31302357
AS		 6063build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6064 char *rightstart, char *rightstop,
6065 const char *truelab, const char *falselab,
6066 int extent)
252b5132
RH		 6067{
6068 char *buf;
6069 char *s;
6070
6071 if (leftstart != NULL)
6072 {
6073 struct m68k_op leftop, rightop;
6074 char c;
6075
6076 /* Swap the compare operands, if necessary, to produce a legal
6077 m68k compare instruction. Comparing a register operand with
6078 a non-register operand requires the register to be on the
6079 right (cmp, cmpa). Comparing an immediate value with
6080 anything requires the immediate value to be on the left
6081 (cmpi). */
6082
6083 c = *leftstop;
6084 *leftstop = '\0';
6085 (void) m68k_ip_op (leftstart, &leftop);
6086 *leftstop = c;
6087
6088 c = *rightstop;
6089 *rightstop = '\0';
6090 (void) m68k_ip_op (rightstart, &rightop);
6091 *rightstop = c;
6092
6093 if (rightop.mode == IMMED
6094 || ((leftop.mode == DREG || leftop.mode == AREG)
6095 && (rightop.mode != DREG && rightop.mode != AREG)))
6096 {
6097 char *temp;
6098
31302357
AS		 6099 /* Correct conditional handling:
6100 if #1 <lt> d0 then ;means if (1 < d0)
6101 ...
6102 endi
e1f44d10 6103
31302357 6104 should assemble to:
e1f44d10 6105
31302357
AS		 6106 cmp #1,d0 if we do *not* swap the operands
6107 bgt true we need the swapped condition!
6108 ble false
6109 true:
6110 ...
6111 false:
6112 */
252b5132
RH		 6113 temp = leftstart;
6114 leftstart = rightstart;
6115 rightstart = temp;
6116 temp = leftstop;
6117 leftstop = rightstop;
6118 rightstop = temp;
8a104df9
KH		 6119 }
6120 else
6121 {
e1f44d10 6122 cc = swap_mri_condition (cc);
252b5132
RH		 6123 }
6124 }
6125
6126 if (truelab == NULL)
6127 {
6128 cc = reverse_mri_condition (cc);
6129 truelab = falselab;
6130 }
92774660 6131
252b5132
RH		 6132 if (leftstart != NULL)
6133 {
6134 buf = (char *) xmalloc (20
6135 + (leftstop - leftstart)
6136 + (rightstop - rightstart));
6137 s = buf;
6138 *s++ = 'c';
6139 *s++ = 'm';
6140 *s++ = 'p';
6141 if (qual != '\0')
3882b010 6142 *s++ = TOLOWER (qual);
252b5132
RH		 6143 *s++ = ' ';
6144 memcpy (s, leftstart, leftstop - leftstart);
6145 s += leftstop - leftstart;
6146 *s++ = ',';
6147 memcpy (s, rightstart, rightstop - rightstart);
6148 s += rightstop - rightstart;
6149 *s = '\0';
6150 mri_assemble (buf);
6151 free (buf);
6152 }
92774660 6153
252b5132
RH		 6154 buf = (char *) xmalloc (20 + strlen (truelab));
6155 s = buf;
6156 *s++ = 'b';
6157 *s++ = cc >> 8;
6158 *s++ = cc & 0xff;
6159 if (extent != '\0')
3882b010 6160 *s++ = TOLOWER (extent);
252b5132
RH		 6161 *s++ = ' ';
6162 strcpy (s, truelab);
6163 mri_assemble (buf);
6164 free (buf);
6165}
6166
6167/* Parse an MRI structured control expression. This generates test
6168 and branch instructions. STOP is where the expression ends. It
6169 goes to TRUELAB if the condition is true, and to FALSELAB if the
6170 condition is false. Exactly one of TRUELAB and FALSELAB will be
6171 NULL, meaning to fall through. QUAL is the size qualifier for the
6172 expression. EXTENT is the size to use for the branch. */
6173
6174static void
31302357
AS		 6175parse_mri_control_expression (char *stop, int qual, const char *truelab,
6176 const char *falselab, int extent)
252b5132
RH		 6177{
6178 int c;
6179 int cc;
6180 char *leftstart;
6181 char *leftstop;
6182 char *rightstart;
6183 char *rightstop;
6184
6185 c = *stop;
6186 *stop = '\0';
6187
6188 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6189 &rightstart, &rightstop))
6190 {
6191 *stop = c;
6192 return;
6193 }
6194
6195 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6196 {
6197 const char *flab;
6198
6199 if (falselab != NULL)
6200 flab = falselab;
6201 else
6202 flab = mri_control_label ();
6203
6204 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6205 rightstop, (const char *) NULL, flab, extent);
6206
6207 input_line_pointer += 3;
6208 if (*input_line_pointer != '.'
6209 || input_line_pointer[1] == '\0')
6210 qual = '\0';
6211 else
6212 {
6213 qual = input_line_pointer[1];
6214 input_line_pointer += 2;
6215 }
6216
6217 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6218 &rightstart, &rightstop))
6219 {
6220 *stop = c;
6221 return;
6222 }
6223
6224 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6225 rightstop, truelab, falselab, extent);
6226
6227 if (falselab == NULL)
6228 colon (flab);
6229 }
6230 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6231 {
6232 const char *tlab;
6233
6234 if (truelab != NULL)
6235 tlab = truelab;
6236 else
6237 tlab = mri_control_label ();
6238
6239 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6240 rightstop, tlab, (const char *) NULL, extent);
6241
6242 input_line_pointer += 2;
6243 if (*input_line_pointer != '.'
6244 || input_line_pointer[1] == '\0')
6245 qual = '\0';
6246 else
6247 {
6248 qual = input_line_pointer[1];
6249 input_line_pointer += 2;
6250 }
6251
6252 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6253 &rightstart, &rightstop))
6254 {
6255 *stop = c;
6256 return;
6257 }
6258
6259 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6260 rightstop, truelab, falselab, extent);
6261
6262 if (truelab == NULL)
6263 colon (tlab);
6264 }
6265 else
6266 {
6267 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6268 rightstop, truelab, falselab, extent);
6269 }
6270
6271 *stop = c;
6272 if (input_line_pointer != stop)
6273 as_bad (_("syntax error in structured control directive"));
6274}
6275
6276/* Handle the MRI IF pseudo-op. This may be a structured control
6277 directive, or it may be a regular assembler conditional, depending
6278 on its operands. */
6279
6280static void
31302357 6281s_mri_if (int qual)
252b5132
RH		 6282{
6283 char *s;
6284 int c;
6285 struct mri_control_info *n;
6286
6287 /* A structured control directive must end with THEN with an
6288 optional qualifier. */
6289 s = input_line_pointer;
e1f44d10
NC		 6290 /* We only accept '*' as introduction of comments if preceded by white space
6291 or at first column of a line (I think this can't actually happen here?)
6292 This is important when assembling:
6293 if d0 <ne> 12(a0,d0*2) then
36759679 6294 if d0 <ne> #CONST*20 then. */
31302357
AS		 6295 while (! (is_end_of_line[(unsigned char) *s]
6296 || (flag_mri
6297 && *s == '*'
6298 && (s == input_line_pointer
6299 || *(s-1) == ' '
6300 || *(s-1) == '\t'))))
252b5132
RH		 6301 ++s;
6302 --s;
6303 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6304 --s;
6305
6306 if (s - input_line_pointer > 1
6307 && s[-1] == '.')
6308 s -= 2;
6309
6310 if (s - input_line_pointer < 3
6311 || strncasecmp (s - 3, "THEN", 4) != 0)
6312 {
6313 if (qual != '\0')
6314 {
6315 as_bad (_("missing then"));
6316 ignore_rest_of_line ();
6317 return;
6318 }
6319
6320 /* It's a conditional. */
6321 s_if (O_ne);
6322 return;
6323 }
6324
6325 /* Since this might be a conditional if, this pseudo-op will be
6326 called even if we are supported to be ignoring input. Double
6327 check now. Clobber *input_line_pointer so that ignore_input
6328 thinks that this is not a special pseudo-op. */
6329 c = *input_line_pointer;
6330 *input_line_pointer = 0;
6331 if (ignore_input ())
6332 {
6333 *input_line_pointer = c;
6334 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6335 ++input_line_pointer;
6336 demand_empty_rest_of_line ();
6337 return;
6338 }
6339 *input_line_pointer = c;
6340
6341 n = push_mri_control (mri_if);
6342
6343 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6344 n->next, s[1] == '.' ? s[2] : '\0');
6345
6346 if (s[1] == '.')
6347 input_line_pointer = s + 3;
6348 else
6349 input_line_pointer = s + 1;
6350
6351 if (flag_mri)
6352 {
6353 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6354 ++input_line_pointer;
6355 }
6356
6357 demand_empty_rest_of_line ();
6358}
6359
6360/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6361 structured IF, associate the ELSE with the IF. Otherwise, assume
6362 it is a conditional else. */
6363
6364static void
31302357 6365s_mri_else (int qual)
252b5132
RH		 6366{
6367 int c;
6368 char *buf;
6369 char q[2];
6370
6371 if (qual == '\0'
6372 && (mri_control_stack == NULL
6373 || mri_control_stack->type != mri_if
6374 || mri_control_stack->else_seen))
6375 {
6376 s_else (0);
6377 return;
6378 }
6379
6380 c = *input_line_pointer;
6381 *input_line_pointer = 0;
6382 if (ignore_input ())
6383 {
6384 *input_line_pointer = c;
6385 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6386 ++input_line_pointer;
6387 demand_empty_rest_of_line ();
6388 return;
6389 }
6390 *input_line_pointer = c;
6391
6392 if (mri_control_stack == NULL
6393 || mri_control_stack->type != mri_if
6394 || mri_control_stack->else_seen)
6395 {
6396 as_bad (_("else without matching if"));
6397 ignore_rest_of_line ();
6398 return;
6399 }
6400
6401 mri_control_stack->else_seen = 1;
6402
6403 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6404 q[0] = TOLOWER (qual);
252b5132
RH		 6405 q[1] = '\0';
6406 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6407 mri_assemble (buf);
6408 free (buf);
6409
6410 colon (mri_control_stack->next);
6411
6412 if (flag_mri)
6413 {
6414 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6415 ++input_line_pointer;
6416 }
6417
6418 demand_empty_rest_of_line ();
6419}
6420
6421/* Handle the MRI ENDI pseudo-op. */
6422
6423static void
31302357 6424s_mri_endi (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6425{
6426 if (mri_control_stack == NULL
6427 || mri_control_stack->type != mri_if)
6428 {
6429 as_bad (_("endi without matching if"));
6430 ignore_rest_of_line ();
6431 return;
6432 }
6433
6434 /* ignore_input will not return true for ENDI, so we don't need to
6435 worry about checking it again here. */
6436
6437 if (! mri_control_stack->else_seen)
6438 colon (mri_control_stack->next);
6439 colon (mri_control_stack->bottom);
6440
6441 pop_mri_control ();
6442
6443 if (flag_mri)
6444 {
6445 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6446 ++input_line_pointer;
6447 }
6448
6449 demand_empty_rest_of_line ();
6450}
6451
6452/* Handle the MRI BREAK pseudo-op. */
6453
6454static void
31302357 6455s_mri_break (int extent)
252b5132
RH		 6456{
6457 struct mri_control_info *n;
6458 char *buf;
6459 char ex[2];
6460
6461 n = mri_control_stack;
6462 while (n != NULL
6463 && n->type != mri_for
6464 && n->type != mri_repeat
6465 && n->type != mri_while)
6466 n = n->outer;
6467 if (n == NULL)
6468 {
6469 as_bad (_("break outside of structured loop"));
6470 ignore_rest_of_line ();
6471 return;
6472 }
6473
6474 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6475 ex[0] = TOLOWER (extent);
252b5132
RH		 6476 ex[1] = '\0';
6477 sprintf (buf, "bra%s %s", ex, n->bottom);
6478 mri_assemble (buf);
6479 free (buf);
6480
6481 if (flag_mri)
6482 {
6483 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6484 ++input_line_pointer;
6485 }
6486
6487 demand_empty_rest_of_line ();
6488}
6489
6490/* Handle the MRI NEXT pseudo-op. */
6491
6492static void
31302357 6493s_mri_next (int extent)
252b5132
RH		 6494{
6495 struct mri_control_info *n;
6496 char *buf;
6497 char ex[2];
6498
6499 n = mri_control_stack;
6500 while (n != NULL
6501 && n->type != mri_for
6502 && n->type != mri_repeat
6503 && n->type != mri_while)
6504 n = n->outer;
6505 if (n == NULL)
6506 {
6507 as_bad (_("next outside of structured loop"));
6508 ignore_rest_of_line ();
6509 return;
6510 }
6511
6512 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6513 ex[0] = TOLOWER (extent);
252b5132
RH		 6514 ex[1] = '\0';
6515 sprintf (buf, "bra%s %s", ex, n->next);
6516 mri_assemble (buf);
6517 free (buf);
6518
6519 if (flag_mri)
6520 {
6521 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6522 ++input_line_pointer;
6523 }
6524
6525 demand_empty_rest_of_line ();
6526}
6527
6528/* Handle the MRI FOR pseudo-op. */
6529
6530static void
31302357 6531s_mri_for (int qual)
252b5132
RH		 6532{
6533 const char *varstart, *varstop;
6534 const char *initstart, *initstop;
6535 const char *endstart, *endstop;
6536 const char *bystart, *bystop;
6537 int up;
6538 int by;
6539 int extent;
6540 struct mri_control_info *n;
6541 char *buf;
6542 char *s;
6543 char ex[2];
6544
6545 /* The syntax is
6546 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6547 */
6548
6549 SKIP_WHITESPACE ();
6550 varstart = input_line_pointer;
6551
6552 /* Look for the '='. */
6553 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6554 && *input_line_pointer != '=')
6555 ++input_line_pointer;
6556 if (*input_line_pointer != '=')
6557 {
6558 as_bad (_("missing ="));
6559 ignore_rest_of_line ();
6560 return;
6561 }
6562
6563 varstop = input_line_pointer;
6564 if (varstop > varstart
6565 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6566 --varstop;
6567
6568 ++input_line_pointer;
6569
6570 initstart = input_line_pointer;
6571
6572 /* Look for TO or DOWNTO. */
6573 up = 1;
6574 initstop = NULL;
6575 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6576 {
6577 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6578 && ! is_part_of_name (input_line_pointer[2]))
6579 {
6580 initstop = input_line_pointer;
6581 input_line_pointer += 2;
6582 break;
6583 }
6584 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6585 && ! is_part_of_name (input_line_pointer[6]))
6586 {
6587 initstop = input_line_pointer;
6588 up = 0;
6589 input_line_pointer += 6;
6590 break;
6591 }
6592 ++input_line_pointer;
6593 }
6594 if (initstop == NULL)
6595 {
6596 as_bad (_("missing to or downto"));
6597 ignore_rest_of_line ();
6598 return;
6599 }
6600 if (initstop > initstart
6601 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6602 --initstop;
6603
6604 SKIP_WHITESPACE ();
6605 endstart = input_line_pointer;
6606
6607 /* Look for BY or DO. */
6608 by = 0;
6609 endstop = NULL;
6610 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6611 {
6612 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6613 && ! is_part_of_name (input_line_pointer[2]))
6614 {
6615 endstop = input_line_pointer;
6616 by = 1;
6617 input_line_pointer += 2;
6618 break;
6619 }
6620 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6621 && (input_line_pointer[2] == '.'
6622 || ! is_part_of_name (input_line_pointer[2])))
6623 {
6624 endstop = input_line_pointer;
6625 input_line_pointer += 2;
6626 break;
6627 }
6628 ++input_line_pointer;
6629 }
6630 if (endstop == NULL)
6631 {
6632 as_bad (_("missing do"));
6633 ignore_rest_of_line ();
6634 return;
6635 }
6636 if (endstop > endstart
6637 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6638 --endstop;
6639
6640 if (! by)
6641 {
6642 bystart = "#1";
6643 bystop = bystart + 2;
6644 }
6645 else
6646 {
6647 SKIP_WHITESPACE ();
6648 bystart = input_line_pointer;
6649
6650 /* Look for DO. */
6651 bystop = NULL;
6652 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6653 {
6654 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6655 && (input_line_pointer[2] == '.'
6656 || ! is_part_of_name (input_line_pointer[2])))
6657 {
6658 bystop = input_line_pointer;
6659 input_line_pointer += 2;
6660 break;
6661 }
6662 ++input_line_pointer;
6663 }
6664 if (bystop == NULL)
6665 {
6666 as_bad (_("missing do"));
6667 ignore_rest_of_line ();
6668 return;
6669 }
6670 if (bystop > bystart
6671 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6672 --bystop;
6673 }
6674
6675 if (*input_line_pointer != '.')
6676 extent = '\0';
6677 else
6678 {
6679 extent = input_line_pointer[1];
6680 input_line_pointer += 2;
6681 }
6682
6683 /* We have fully parsed the FOR operands. Now build the loop. */
252b5132
RH		 6684 n = push_mri_control (mri_for);
6685
6686 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6687
36759679 6688 /* Move init,var. */
252b5132
RH		 6689 s = buf;
6690 *s++ = 'm';
6691 *s++ = 'o';
6692 *s++ = 'v';
6693 *s++ = 'e';
6694 if (qual != '\0')
3882b010 6695 *s++ = TOLOWER (qual);
252b5132
RH		 6696 *s++ = ' ';
6697 memcpy (s, initstart, initstop - initstart);
6698 s += initstop - initstart;
6699 *s++ = ',';
6700 memcpy (s, varstart, varstop - varstart);
6701 s += varstop - varstart;
6702 *s = '\0';
6703 mri_assemble (buf);
6704
6705 colon (n->top);
6706
36759679 6707 /* cmp end,var. */
252b5132
RH		 6708 s = buf;
6709 *s++ = 'c';
6710 *s++ = 'm';
6711 *s++ = 'p';
6712 if (qual != '\0')
3882b010 6713 *s++ = TOLOWER (qual);
252b5132
RH		 6714 *s++ = ' ';
6715 memcpy (s, endstart, endstop - endstart);
6716 s += endstop - endstart;
6717 *s++ = ',';
6718 memcpy (s, varstart, varstop - varstart);
6719 s += varstop - varstart;
6720 *s = '\0';
6721 mri_assemble (buf);
6722
36759679 6723 /* bcc bottom. */
3882b010 6724 ex[0] = TOLOWER (extent);
252b5132
RH		 6725 ex[1] = '\0';
6726 if (up)
6727 sprintf (buf, "blt%s %s", ex, n->bottom);
6728 else
6729 sprintf (buf, "bgt%s %s", ex, n->bottom);
6730 mri_assemble (buf);
6731
6732 /* Put together the add or sub instruction used by ENDF. */
6733 s = buf;
6734 if (up)
6735 strcpy (s, "add");
6736 else
6737 strcpy (s, "sub");
6738 s += 3;
6739 if (qual != '\0')
3882b010 6740 *s++ = TOLOWER (qual);
252b5132
RH		 6741 *s++ = ' ';
6742 memcpy (s, bystart, bystop - bystart);
6743 s += bystop - bystart;
6744 *s++ = ',';
6745 memcpy (s, varstart, varstop - varstart);
6746 s += varstop - varstart;
6747 *s = '\0';
6748 n->incr = buf;
6749
6750 if (flag_mri)
6751 {
6752 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6753 ++input_line_pointer;
6754 }
6755
6756 demand_empty_rest_of_line ();
6757}
6758
6759/* Handle the MRI ENDF pseudo-op. */
6760
6761static void
31302357 6762s_mri_endf (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6763{
6764 if (mri_control_stack == NULL
6765 || mri_control_stack->type != mri_for)
6766 {
6767 as_bad (_("endf without for"));
6768 ignore_rest_of_line ();
6769 return;
6770 }
6771
6772 colon (mri_control_stack->next);
6773
6774 mri_assemble (mri_control_stack->incr);
6775
6776 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6777 mri_assemble (mri_control_stack->incr);
6778
6779 free (mri_control_stack->incr);
6780
6781 colon (mri_control_stack->bottom);
6782
6783 pop_mri_control ();
6784
6785 if (flag_mri)
6786 {
6787 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6788 ++input_line_pointer;
6789 }
6790
6791 demand_empty_rest_of_line ();
6792}
6793
6794/* Handle the MRI REPEAT pseudo-op. */
6795
6796static void
31302357 6797s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6798{
6799 struct mri_control_info *n;
6800
6801 n = push_mri_control (mri_repeat);
6802 colon (n->top);
6803 if (flag_mri)
6804 {
6805 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6806 ++input_line_pointer;
6807 }
6808 demand_empty_rest_of_line ();
6809}
6810
6811/* Handle the MRI UNTIL pseudo-op. */
6812
6813static void
31302357 6814s_mri_until (int qual)
252b5132
RH		 6815{
6816 char *s;
6817
6818 if (mri_control_stack == NULL
6819 || mri_control_stack->type != mri_repeat)
6820 {
6821 as_bad (_("until without repeat"));
6822 ignore_rest_of_line ();
6823 return;
6824 }
6825
6826 colon (mri_control_stack->next);
6827
6828 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6829 ;
6830
6831 parse_mri_control_expression (s, qual, (const char *) NULL,
6832 mri_control_stack->top, '\0');
6833
6834 colon (mri_control_stack->bottom);
6835
6836 input_line_pointer = s;
6837
6838 pop_mri_control ();
6839
6840 if (flag_mri)
6841 {
6842 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6843 ++input_line_pointer;
6844 }
6845
6846 demand_empty_rest_of_line ();
6847}
6848
6849/* Handle the MRI WHILE pseudo-op. */
6850
6851static void
31302357 6852s_mri_while (int qual)
252b5132
RH		 6853{
6854 char *s;
6855
6856 struct mri_control_info *n;
6857
6858 s = input_line_pointer;
e1f44d10
NC		 6859 /* We only accept '*' as introduction of comments if preceded by white space
6860 or at first column of a line (I think this can't actually happen here?)
6861 This is important when assembling:
6862 while d0 <ne> 12(a0,d0*2) do
36759679 6863 while d0 <ne> #CONST*20 do. */
8a104df9
KH		 6864 while (! (is_end_of_line[(unsigned char) *s]
6865 || (flag_mri
6866 && *s == '*'
6867 && (s == input_line_pointer
6868 || *(s-1) == ' '
6869 || *(s-1) == '\t'))))
252b5132
RH		 6870 s++;
6871 --s;
6872 while (*s == ' ' || *s == '\t')
6873 --s;
6874 if (s - input_line_pointer > 1
6875 && s[-1] == '.')
6876 s -= 2;
6877 if (s - input_line_pointer < 2
6878 || strncasecmp (s - 1, "DO", 2) != 0)
6879 {
6880 as_bad (_("missing do"));
6881 ignore_rest_of_line ();
6882 return;
6883 }
6884
6885 n = push_mri_control (mri_while);
6886
6887 colon (n->next);
6888
6889 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6890 s[1] == '.' ? s[2] : '\0');
6891
6892 input_line_pointer = s + 1;
6893 if (*input_line_pointer == '.')
6894 input_line_pointer += 2;
6895
6896 if (flag_mri)
6897 {
6898 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6899 ++input_line_pointer;
6900 }
6901
6902 demand_empty_rest_of_line ();
6903}
6904
6905/* Handle the MRI ENDW pseudo-op. */
6906
6907static void
31302357 6908s_mri_endw (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6909{
6910 char *buf;
6911
6912 if (mri_control_stack == NULL
6913 || mri_control_stack->type != mri_while)
6914 {
6915 as_bad (_("endw without while"));
6916 ignore_rest_of_line ();
6917 return;
6918 }
6919
6920 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6921 sprintf (buf, "bra %s", mri_control_stack->next);
6922 mri_assemble (buf);
6923 free (buf);
6924
6925 colon (mri_control_stack->bottom);
6926
6927 pop_mri_control ();
6928
6929 if (flag_mri)
6930 {
6931 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6932 ++input_line_pointer;
6933 }
6934
6935 demand_empty_rest_of_line ();
6936}
6937\f
266abb8f
NS		 6938/* Parse a .cpu directive. */
6939
6940static void
6941s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
6942{
6943 char saved_char;
6944 char *name;
6945
6946 if (initialized)
6947 {
6948 as_bad (_("already assembled instructions"));
6949 ignore_rest_of_line ();
6950 return;
6951 }
6952
6953 name = input_line_pointer;
6954 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
6955 input_line_pointer++;
6956 saved_char = *input_line_pointer;
6957 *input_line_pointer = 0;
6958
6959 m68k_set_cpu (name, 1, 0);
6960
6961 *input_line_pointer = saved_char;
6962 demand_empty_rest_of_line ();
6963 return;
6964}
6965
6966/* Parse a .arch directive. */
6967
6968static void
6969s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
6970{
6971 char saved_char;
6972 char *name;
6973
6974 if (initialized)
6975 {
6976 as_bad (_("already assembled instructions"));
6977 ignore_rest_of_line ();
6978 return;
6979 }
6980
6981 name = input_line_pointer;
6982 while (*input_line_pointer && *input_line_pointer != ','
6983 && !ISSPACE (*input_line_pointer))
6984 input_line_pointer++;
6985 saved_char = *input_line_pointer;
6986 *input_line_pointer = 0;
6987
6988 if (m68k_set_arch (name, 1, 0))
6989 {
6990 /* Scan extensions. */
6991 do
6992 {
6993 *input_line_pointer++ = saved_char;
6994 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
6995 break;
6996 name = input_line_pointer;
6997 while (*input_line_pointer && *input_line_pointer != ','
6998 && !ISSPACE (*input_line_pointer))
6999 input_line_pointer++;
7000 saved_char = *input_line_pointer;
7001 *input_line_pointer = 0;
7002 }
7003 while (m68k_set_extension (name, 1, 0));
7004 }
7005
7006 *input_line_pointer = saved_char;
7007 demand_empty_rest_of_line ();
7008 return;
7009}
7010\f
7011/* Lookup a cpu name in TABLE and return the slot found. Return NULL
7012 if none is found, the caller is responsible for emitting an error
7013 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7014 cpu name, if it begins with a '6' (possibly skipping an intervening
7015 'c'. We also allow a 'c' in the same place. if NEGATED is
7016 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7017 the option is indeed negated. */
7018
7019static const struct m68k_cpu *
7020m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7021 int allow_m, int *negated)
7022{
7023 /* allow negated value? */
7024 if (negated)
7025 {
7026 *negated = 0;
7027
7028 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7029 {
7030 arg += 3;
7031 *negated = 1;
7032 }
7033 }
7034
7035 /* Remove 'm' or 'mc' prefix from 68k variants. */
7036 if (allow_m)
7037 {
7038 if (arg[0] == 'm')
7039 {
7040 if (arg[1] == '6')
7041 arg += 1;
7042 else if (arg[1] == 'c' && arg[2] == '6')
7043 arg += 2;
7044 }
7045 }
7046 else if (arg[0] == 'c' && arg[1] == '6')
7047 arg += 1;
7048
7049 for (; table->name; table++)
7050 if (!strcmp (arg, table->name))
2da12c60
NS		 7051 {
7052 if (table->alias < -1 || table->alias > 1)
7053 as_bad (_("`%s' is deprecated, use `%s'"),
7054 table->name, table[table->alias < 0 ? 1 : -1].name);
7055 return table;
7056 }
266abb8f
NS		 7057 return 0;
7058}
7059
7060/* Set the cpu, issuing errors if it is unrecognized, or invalid */
7061
7062static int
7063m68k_set_cpu (char const *name, int allow_m, int silent)
7064{
7065 const struct m68k_cpu *cpu;
7066
7067 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7068
7069 if (!cpu)
7070 {
7071 if (!silent)
7072 as_bad (_("cpu `%s' unrecognized"), name);
7073 return 0;
7074 }
7075
7076 if (selected_cpu && selected_cpu != cpu)
7077 {
7078 as_bad (_("already selected `%s' processor"),
7079 selected_cpu->name);
7080 return 0;
7081 }
7082 selected_cpu = cpu;
7083 return 1;
7084}
7085
7086/* Set the architecture, issuing errors if it is unrecognized, or invalid */
7087
7088static int
7089m68k_set_arch (char const *name, int allow_m, int silent)
7090{
7091 const struct m68k_cpu *arch;
7092
7093 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7094
7095 if (!arch)
7096 {
7097 if (!silent)
7098 as_bad (_("architecture `%s' unrecognized"), name);
7099 return 0;
7100 }
7101
7102 if (selected_arch && selected_arch != arch)
7103 {
7104 as_bad (_("already selected `%s' architecture"),
7105 selected_arch->name);
7106 return 0;
7107 }
7108
7109 selected_arch = arch;
7110 return 1;
7111}
7112
7113/* Set the architecture extension, issuing errors if it is
7114 unrecognized, or invalid */
7115
7116static int
7117m68k_set_extension (char const *name, int allow_m, int silent)
7118{
7119 int negated;
7120 const struct m68k_cpu *ext;
7121
7122 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7123
7124 if (!ext)
7125 {
7126 if (!silent)
7127 as_bad (_("extension `%s' unrecognized"), name);
7128 return 0;
7129 }
7130
7131 if (negated)
7132 not_current_architecture |= ext->arch;
7133 else
7134 current_architecture |= ext->arch;
7135 return 1;
7136}
7137
31302357
AS		 7138/* md_parse_option
7139 Invocation line includes a switch not recognized by the base assembler.
266abb8f 7140 */
252b5132
RH		 7141
7142#ifdef OBJ_ELF
5a38dc70 7143const char *md_shortopts = "lSA:m:kQ:V";
252b5132 7144#else
5a38dc70 7145const char *md_shortopts = "lSA:m:k";
252b5132
RH		 7146#endif
7147
7148struct option md_longopts[] = {
7149#define OPTION_PIC (OPTION_MD_BASE)
7150 {"pic", no_argument, NULL, OPTION_PIC},
7151#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7152 {"register-prefix-optional", no_argument, NULL,
7153 OPTION_REGISTER_PREFIX_OPTIONAL},
7154#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7155 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7156#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7157 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7158#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7159 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7160#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7161 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7162#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7163 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 7164#define OPTION_PCREL (OPTION_MD_BASE + 7)
7165 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 7166 {NULL, no_argument, NULL, 0}
7167};
bc805888 7168size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 7169
7170int
31302357 7171md_parse_option (int c, char *arg)
252b5132
RH		 7172{
7173 switch (c)
7174 {
7175 case 'l': /* -l means keep external to 2 bit offset
36759679 7176 rather than 16 bit one. */
252b5132
RH		 7177 flag_short_refs = 1;
7178 break;
7179
7180 case 'S': /* -S means that jbsr's always turn into
7181 jsr's. */
7182 flag_long_jumps = 1;
7183 break;
7184
28e7409f
NC		 7185 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7186 branches into absolute jumps. */
7187 flag_keep_pcrel = 1;
7188 break;
7189
252b5132
RH		 7190 case OPTION_PIC:
7191 case 'k':
7192 flag_want_pic = 1;
36759679 7193 break; /* -pic, Position Independent Code. */
252b5132
RH		 7194
7195 case OPTION_REGISTER_PREFIX_OPTIONAL:
7196 flag_reg_prefix_optional = 1;
7197 reg_prefix_optional_seen = 1;
7198 break;
7199
7200 /* -V: SVR4 argument to print version ID. */
7201 case 'V':
7202 print_version_id ();
7203 break;
7204
7205 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7206 should be emitted or not. FIXME: Not implemented. */
7207 case 'Q':
7208 break;
7209
7210 case OPTION_BITWISE_OR:
7211 {
7212 char *n, *t;
7213 const char *s;
7214
7215 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7216 t = n;
7217 for (s = m68k_comment_chars; *s != '\0'; s++)
7218 if (*s != '|')
7219 *t++ = *s;
7220 *t = '\0';
7221 m68k_comment_chars = n;
7222 }
7223 break;
7224
7225 case OPTION_BASE_SIZE_DEFAULT_16:
7226 m68k_index_width_default = SIZE_WORD;
7227 break;
7228
7229 case OPTION_BASE_SIZE_DEFAULT_32:
7230 m68k_index_width_default = SIZE_LONG;
7231 break;
7232
7233 case OPTION_DISP_SIZE_DEFAULT_16:
7234 m68k_rel32 = 0;
7235 m68k_rel32_from_cmdline = 1;
7236 break;
7237
7238 case OPTION_DISP_SIZE_DEFAULT_32:
7239 m68k_rel32 = 1;
7240 m68k_rel32_from_cmdline = 1;
7241 break;
7242
266abb8f
NS		 7243 case 'A':
7244#if WARN_DEPRECATED
7245 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7246 arg, arg));
7247#endif
7248 /* Intentional fall-through. */
7249 case 'm':
7250 if (!strncmp (arg, "arch=", 5))
7251 m68k_set_arch (arg + 5, 1, 0);
7252 else if (!strncmp (arg, "cpu=", 4))
7253 m68k_set_cpu (arg + 4, 1, 0);
7254 else if (m68k_set_extension (arg, 0, 1))
7255 ;
0b2e31dc
NS		 7256 else if (m68k_set_arch (arg, 0, 1))
7257 ;
266abb8f
NS		 7258 else if (m68k_set_cpu (arg, 0, 1))
7259 ;
7260 else
7261 return 0;
7262 break;
7263
252b5132
RH		 7264 default:
7265 return 0;
7266 }
7267
7268 return 1;
7269}
7270
266abb8f
NS		 7271/* Setup tables from the selected arch and/or cpu */
7272
7273static void
7274m68k_init_arch (void)
7275{
266abb8f
NS		 7276 if (not_current_architecture & current_architecture)
7277 {
7278 as_bad (_("architecture features both enabled and disabled"));
7279 not_current_architecture &= ~current_architecture;
7280 }
7281 if (selected_arch)
2da12c60
NS		 7282 {
7283 current_architecture |= selected_arch->arch;
7284 control_regs = selected_arch->control_regs;
7285 }
0b2e31dc
NS		 7286 else
7287 current_architecture |= selected_cpu->arch;
0b2e31dc 7288
2da12c60
NS		 7289 current_architecture &= ~not_current_architecture;
7290
0b2e31dc 7291 if (selected_cpu)
266abb8f 7292 {
2da12c60 7293 control_regs = selected_cpu->control_regs;
0b2e31dc 7294 if (current_architecture & ~selected_cpu->arch)
266abb8f 7295 {
0b2e31dc
NS		 7296 as_bad (_("selected processor does not have all features of selected architecture"));
7297 current_architecture
7298 = selected_cpu->arch & ~not_current_architecture;
266abb8f
NS		 7299 }
7300 }
266abb8f 7301
0b2e31dc
NS		 7302 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7303 {
7304 /* Determine which float is really meant. */
7305 if (current_architecture & (m68k_mask & ~m68881))
7306 current_architecture ^= cfloat;
7307 else
7308 current_architecture ^= m68881;
7309 }
7310
266abb8f
NS		 7311 if ((current_architecture & m68k_mask)
7312 && (current_architecture & ~m68k_mask))
7313 {
7314 as_bad (_ ("m68k and cf features both selected"));
0b2e31dc 7315 if (current_architecture & m68k_mask)
266abb8f
NS		 7316 current_architecture &= m68k_mask;
7317 else
7318 current_architecture &= ~m68k_mask;
7319 }
7320
7321 /* Permit m68881 specification with all cpus; those that can't work
7322 with a coprocessor could be doing emulation. */
7323 if (current_architecture & m68851)
7324 {
7325 if (current_architecture & m68040)
7326 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7327 }
7328 /* What other incompatibilities could we check for? */
7329
266abb8f
NS		 7330 if (cpu_of_arch (current_architecture) < m68020
7331 || arch_coldfire_p (current_architecture))
7332 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7333
7334 initialized = 1;
7335}
7336
252b5132 7337void
31302357 7338md_show_usage (FILE *stream)
252b5132 7339{
76f57f3a 7340 const char *default_cpu = TARGET_CPU;
f1f5ef86
AM		 7341 int i;
7342 unsigned int default_arch;
76f57f3a 7343
8a104df9 7344 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 7345 if (*default_cpu == 'm')
7346 default_cpu++;
266abb8f 7347 for (i = 0; m68k_cpus[i].name; i++)
76f57f3a 7348 {
266abb8f 7349 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
76f57f3a 7350 {
266abb8f 7351 default_arch = m68k_cpus[i].arch;
2da12c60
NS		 7352 while (m68k_cpus[i].alias > 0)
7353 i--;
7354 while (m68k_cpus[i].alias < 0)
7355 i++;
7356 default_cpu = m68k_cpus[i].name;
76f57f3a
JT		 7357 }
7358 }
7359
bc805888 7360 fprintf (stream, _("\
266abb8f
NS		 7361-march=<arch> set architecture\n\
7362-mcpu=<cpu> set cpu [default %s]\n\
7363"), default_cpu);
7364 for (i = 0; m68k_extensions[i].name; i++)
7365 fprintf (stream, _("\
0b2e31dc
NS		 7366-m[no-]%-16s enable/disable%s architecture extension\n\
7367"), m68k_extensions[i].name,
7368 m68k_extensions[i].alias > 0 ? " ColdFire"
7369 : m68k_extensions[i].alias < 0 ? " m68k" : "");
266abb8f 7370
bc805888 7371 fprintf (stream, _("\
266abb8f 7372-l use 1 word for refs to undefined symbols [default 2]\n\
252b5132
RH		 7373-pic, -k generate position independent code\n\
7374-S turn jbsr into jsr\n\
28e7409f 7375--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 7376--register-prefix-optional\n\
7377 recognize register names without prefix character\n\
266abb8f 7378--bitwise-or do not treat `|' as a comment character\n\
252b5132
RH		 7379--base-size-default-16 base reg without size is 16 bits\n\
7380--base-size-default-32 base reg without size is 32 bits (default)\n\
7381--disp-size-default-16 displacement with unknown size is 16 bits\n\
266abb8f
NS		 7382--disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7383"));
7384
7385 fprintf (stream, _("Architecture variants are: "));
7386 for (i = 0; m68k_archs[i].name; i++)
7387 {
7388 if (i)
7389 fprintf (stream, " | ");
7390 fprintf (stream, m68k_archs[i].name);
7391 }
7392 fprintf (stream, "\n");
7393
7394 fprintf (stream, _("Processor variants are: "));
7395 for (i = 0; m68k_cpus[i].name; i++)
7396 {
7397 if (i)
7398 fprintf (stream, " | ");
7399 fprintf (stream, m68k_cpus[i].name);
7400 }
7401 fprintf (stream, _("\n"));
252b5132
RH		 7402}
7403\f
7404#ifdef TEST2
7405
7406/* TEST2: Test md_assemble() */
36759679
NC		 7407/* Warning, this routine probably doesn't work anymore. */
7408int
31302357 7409main (void)
252b5132
RH		 7410{
7411 struct m68k_it the_ins;
7412 char buf[120];
7413 char *cp;
7414 int n;
7415
7416 m68k_ip_begin ();
7417 for (;;)
7418 {
7419 if (!gets (buf) || !*buf)
7420 break;
7421 if (buf[0] == '|' || buf[1] == '.')
7422 continue;
7423 for (cp = buf; *cp; cp++)
7424 if (*cp == '\t')
7425 *cp = ' ';
7426 if (is_label (buf))
7427 continue;
7428 memset (&the_ins, '\0', sizeof (the_ins));
7429 m68k_ip (&the_ins, buf);
7430 if (the_ins.error)
7431 {
7432 printf (_("Error %s in %s\n"), the_ins.error, buf);
7433 }
7434 else
7435 {
7436 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7437 for (n = 0; n < the_ins.numo; n++)
7438 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7439 printf (" ");
7440 print_the_insn (&the_ins.opcode[0], stdout);
7441 (void) putchar ('\n');
7442 }
7443 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7444 {
7445 if (the_ins.operands[n].error)
7446 {
7447 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7448 continue;
7449 }
31302357
AS		 7450 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7451 the_ins.operands[n].reg);
252b5132 7452 if (the_ins.operands[n].b_const)
31302357
AS		 7453 printf ("Constant: '%.*s', ",
7454 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7455 the_ins.operands[n].b_const);
7456 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7457 the_ins.operands[n].isiz, the_ins.operands[n].imul);
252b5132 7458 if (the_ins.operands[n].b_iadd)
31302357
AS		 7459 printf ("Iadd: '%.*s',",
7460 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7461 the_ins.operands[n].b_iadd);
7462 putchar ('\n');
252b5132
RH		 7463 }
7464 }
7465 m68k_ip_end ();
7466 return 0;
7467}
7468
31302357
AS		 7469int
7470is_label (char *str)
252b5132
RH		 7471{
7472 while (*str == ' ')
7473 str++;
7474 while (*str && *str != ' ')
7475 str++;
7476 if (str[-1] == ':' || str[1] == '=')
7477 return 1;
7478 return 0;
7479}
7480
7481#endif
7482
7483/* Possible states for relaxation:
7484
7485 0 0 branch offset byte (bra, etc)
7486 0 1 word
7487 0 2 long
7488
7489 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7490 1 1 word
7491 1 2 long
7492
7493 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7494 2 1 word-long
7495 2 2 long-word
7496 2 3 long-long
7497
7498 */
7499
7500/* We have no need to default values of symbols. */
7501
252b5132 7502symbolS *
31302357 7503md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 7504{
7505 return 0;
7506}
7507
7508/* Round up a section size to the appropriate boundary. */
7509valueT
31302357 7510md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132
RH		 7511{
7512#ifdef OBJ_AOUT
252b5132
RH		 7513 /* For a.out, force the section size to be aligned. If we don't do
7514 this, BFD will align it for us, but it will not write out the
7515 final bytes of the section. This may be a bug in BFD, but it is
7516 easier to fix it here since that is how the other a.out targets
7517 work. */
7518 int align;
7519
7520 align = bfd_get_section_alignment (stdoutput, segment);
7521 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
252b5132
RH		 7522#endif
7523
7524 return size;
7525}
7526
7527/* Exactly what point is a PC-relative offset relative TO?
7528 On the 68k, it is relative to the address of the first extension
7529 word. The difference between the addresses of the offset and the
92774660 7530 first extension word is stored in fx_pcrel_adjust. */
252b5132 7531long
31302357 7532md_pcrel_from (fixS *fixP)
252b5132
RH		 7533{
7534 int adjust;
7535
8390138c
AS		 7536 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7537 sign extend the value here. */
7538 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7539 if (adjust == 64)
7540 adjust = -1;
7541 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7542}
7543
0d96863f 7544#ifdef OBJ_ELF
8a104df9 7545void
31302357 7546m68k_elf_final_processing (void)
0d96863f 7547{
266abb8f
NS		 7548 unsigned flags = 0;
7549
238d258f 7550 if (arch_coldfire_fpu (current_architecture))
266abb8f
NS		 7551 flags |= EF_M68K_CFV4E;
7552 /* Set file-specific flags if this is a cpu32 processor. */
8a104df9 7553 if (cpu_of_arch (current_architecture) & cpu32)
266abb8f 7554 flags |= EF_M68K_CPU32;
8a104df9
KH		 7555 else if ((cpu_of_arch (current_architecture) & m68000up)
7556 && !(cpu_of_arch (current_architecture) & m68020up))
266abb8f
NS		 7557 flags |= EF_M68K_M68000;
7558
7559 if (current_architecture & mcfisa_a)
7560 {
0b2e31dc
NS		 7561 static const unsigned isa_features[][2] =
7562 {
7563 {EF_M68K_ISA_A_NODIV, mcfisa_a},
7564 {EF_M68K_ISA_A, mcfisa_a|mcfhwdiv},
7565 {EF_M68K_ISA_A_PLUS,mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7566 {EF_M68K_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7567 {EF_M68K_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7568 {0,0},
7569 };
7570 static const unsigned mac_features[][2] =
7571 {
7572 {EF_M68K_MAC, mcfmac},
7573 {EF_M68K_EMAC, mcfemac},
7574 {0,0},
7575 };
7576 unsigned ix;
7577 unsigned pattern;
266abb8f 7578
0b2e31dc
NS		 7579 pattern = (current_architecture
7580 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfhwdiv|mcfusp));
7581 for (ix = 0; isa_features[ix][1]; ix++)
7582 {
7583 if (pattern == isa_features[ix][1])
7584 {
7585 flags |= isa_features[ix][0];
7586 break;
7587 }
7588 }
7589 if (!isa_features[ix][1])
7590 {
7591 cf_bad:
7592 as_warn (_("Not a defined coldfire architecture"));
7593 }
7594 else
7595 {
7596 if (current_architecture & cfloat)
7597 flags |= EF_M68K_FLOAT | EF_M68K_CFV4E;
266abb8f 7598
0b2e31dc
NS		 7599 pattern = current_architecture & (mcfmac|mcfemac);
7600 if (pattern)
7601 {
7602 for (ix = 0; mac_features[ix][1]; ix++)
7603 {
7604 if (pattern == mac_features[ix][1])
7605 {
7606 flags |= mac_features[ix][0];
7607 break;
7608 }
7609 }
7610 if (!mac_features[ix][1])
7611 goto cf_bad;
7612 }
7613 }
266abb8f
NS		 7614 }
7615 elf_elfheader (stdoutput)->e_flags |= flags;
0d96863f
CM		 7616}
7617#endif
c04898f8
AS		 7618
7619int
7620tc_m68k_regname_to_dw2regnum (const char *regname)
7621{
7622 unsigned int regnum;
7623 static const char *const regnames[] =
7624 {
7625 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7626 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7627 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7628 "pc"
7629 };
7630
7631 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7632 if (strcmp (regname, regnames[regnum]) == 0)
7633 return regnum;
7634
7635 return -1;
7636}
7637
7638void
7639tc_m68k_frame_initial_instructions (void)
7640{
7641 static int sp_regno = -1;
7642
7643 if (sp_regno < 0)
7644 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7645
7646 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7647 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7648}
GDB Binutils - Deliverables
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