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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
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252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4
NC		 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001
252b5132
RH		 4 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
23#include <ctype.h>
24#include "as.h"
25#include "obstack.h"
26#include "subsegs.h"
27
28#include "opcode/m68k.h"
29#include "m68k-parse.h"
30
0d96863f
CM		 31#if defined (OBJ_ELF)
32#include "elf/m68k.h"
33#endif
34
252b5132
RH		 35/* This string holds the chars that always start a comment. If the
36 pre-processor is disabled, these aren't very useful. The macro
37 tc_comment_chars points to this. We use this, rather than the
38 usual comment_chars, so that the --bitwise-or option will work. */
39#if defined (TE_SVR4) || defined (TE_DELTA)
40const char *m68k_comment_chars = "|#";
41#else
42const char *m68k_comment_chars = "|";
43#endif
44
45/* This array holds the chars that only start a comment at the beginning of
46 a line. If the line seems to have the form '# 123 filename'
47 .line and .file directives will appear in the pre-processed output */
48/* Note that input_file.c hand checks for '#' at the beginning of the
49 first line of the input file. This is because the compiler outputs
92774660
KH		 50 #NO_APP at the beginning of its output. */
51/* Also note that comments like this one will always work. */
252b5132
RH		 52const char line_comment_chars[] = "#*";
53
63a0b638 54const char line_separator_chars[] = ";";
252b5132
RH		 55
56/* Chars that can be used to separate mant from exp in floating point nums */
57CONST char EXP_CHARS[] = "eE";
58
59/* Chars that mean this number is a floating point constant, as
60 in "0f12.456" or "0d1.2345e12". */
61
62CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
63
64/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
65 changed in read.c . Ideally it shouldn't have to know about it at all,
66 but nothing is ideal around here. */
67
68const int md_reloc_size = 8; /* Size of relocation record */
69
70/* Are we trying to generate PIC code? If so, absolute references
71 ought to be made into linkage table references or pc-relative
92774660 72 references. Not implemented. For ELF there are other means
252b5132
RH		 73 to denote pic relocations. */
74int flag_want_pic;
75
76static int flag_short_refs; /* -l option */
77static int flag_long_jumps; /* -S option */
28e7409f 78static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 79
80#ifdef REGISTER_PREFIX_OPTIONAL
81int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
82#else
83int flag_reg_prefix_optional;
84#endif
85
86/* Whether --register-prefix-optional was used on the command line. */
87static int reg_prefix_optional_seen;
88
89/* The floating point coprocessor to use by default. */
90static enum m68k_register m68k_float_copnum = COP1;
91
92/* If this is non-zero, then references to number(%pc) will be taken
93 to refer to number, rather than to %pc + number. */
94static int m68k_abspcadd;
95
96/* If this is non-zero, then the quick forms of the move, add, and sub
97 instructions are used when possible. */
98static int m68k_quick = 1;
99
100/* If this is non-zero, then if the size is not specified for a base
101 or outer displacement, the assembler assumes that the size should
102 be 32 bits. */
103static int m68k_rel32 = 1;
104
105/* This is non-zero if m68k_rel32 was set from the command line. */
106static int m68k_rel32_from_cmdline;
107
108/* The default width to use for an index register when using a base
109 displacement. */
110static enum m68k_size m68k_index_width_default = SIZE_LONG;
111
112/* We want to warn if any text labels are misaligned. In order to get
113 the right line number, we need to record the line number for each
114 label. */
115
116struct label_line
117{
118 struct label_line *next;
119 symbolS *label;
120 char *file;
121 unsigned int line;
122 int text;
123};
124
125/* The list of labels. */
126
127static struct label_line *labels;
128
129/* The current label. */
130
131static struct label_line *current_label;
132
133/* Its an arbitrary name: This means I don't approve of it */
134/* See flames below */
135static struct obstack robyn;
136
252b5132
RH		 137struct m68k_incant
138 {
139 const char *m_operands;
140 unsigned long m_opcode;
141 short m_opnum;
142 short m_codenum;
143 int m_arch;
144 struct m68k_incant *m_next;
145 };
146
147#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
148#define gettwo(x) (((x)->m_opcode)&0xffff)
149
150static const enum m68k_register m68000_control_regs[] = { 0 };
151static const enum m68k_register m68010_control_regs[] = {
152 SFC, DFC, USP, VBR,
153 0
154};
155static const enum m68k_register m68020_control_regs[] = {
156 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
157 0
158};
159static const enum m68k_register m68040_control_regs[] = {
160 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
161 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
162 0
163};
164static const enum m68k_register m68060_control_regs[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
166 USP, VBR, URP, SRP, PCR,
167 0
168};
6da466c7 169static const enum m68k_register mcf_control_regs[] = {
92774660 170 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
252b5132
RH		 171 RAMBAR0, RAMBAR1, MBAR,
172 0
173};
174#define cpu32_control_regs m68010_control_regs
175
176static const enum m68k_register *control_regs;
177
178/* internal form of a 68020 instruction */
179struct m68k_it
180{
181 const char *error;
182 const char *args; /* list of opcode info */
183 int numargs;
184
185 int numo; /* Number of shorts in opcode */
186 short opcode[11];
187
188 struct m68k_op operands[6];
189
190 int nexp; /* number of exprs in use */
191 struct m68k_exp exprs[4];
192
193 int nfrag; /* Number of frags we have to produce */
194 struct
195 {
196 int fragoff; /* Where in the current opcode the frag ends */
197 symbolS *fadd;
198 offsetT foff;
199 int fragty;
200 }
201 fragb[4];
202
203 int nrel; /* Num of reloc strucs in use */
204 struct
205 {
206 int n;
207 expressionS exp;
208 char wid;
209 char pcrel;
210 /* In a pc relative address the difference between the address
211 of the offset and the address that the offset is relative
212 to. This depends on the addressing mode. Basically this
213 is the value to put in the offset field to address the
214 first byte of the offset, without regarding the special
215 significance of some values (in the branch instruction, for
216 example). */
217 int pcrel_fix;
218#ifdef OBJ_ELF
219 /* Whether this expression needs special pic relocation, and if
220 so, which. */
221 enum pic_relocation pic_reloc;
222#endif
223 }
224 reloc[5]; /* Five is enough??? */
225};
226
6da466c7 227#define cpu_of_arch(x) ((x) & (m68000up|mcf))
252b5132
RH		 228#define float_of_arch(x) ((x) & mfloat)
229#define mmu_of_arch(x) ((x) & mmmu)
6da466c7 230#define arch_coldfire_p(x) (((x) & mcf) != 0)
252b5132
RH		 231
232/* Macros for determining if cpu supports a specific addressing mode */
dc84e067 233#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407))
252b5132
RH		 234
235static struct m68k_it the_ins; /* the instruction being assembled */
236
237#define op(ex) ((ex)->exp.X_op)
238#define adds(ex) ((ex)->exp.X_add_symbol)
239#define subs(ex) ((ex)->exp.X_op_symbol)
240#define offs(ex) ((ex)->exp.X_add_number)
241
242/* Macros for adding things to the m68k_it struct */
243
244#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
245
246/* Static functions. */
247
248static void insop PARAMS ((int, const struct m68k_incant *));
249static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
250static void add_frag PARAMS ((symbolS *, offsetT, int));
251
252/* Like addword, but goes BEFORE general operands */
253static void
254insop (w, opcode)
255 int w;
256 const struct m68k_incant *opcode;
257{
258 int z;
259 for(z=the_ins.numo;z>opcode->m_codenum;--z)
260 the_ins.opcode[z]=the_ins.opcode[z-1];
261 for(z=0;z<the_ins.nrel;z++)
262 the_ins.reloc[z].n+=2;
263 for (z = 0; z < the_ins.nfrag; z++)
264 the_ins.fragb[z].fragoff++;
265 the_ins.opcode[opcode->m_codenum]=w;
266 the_ins.numo++;
267}
268
269/* The numo+1 kludge is so we can hit the low order byte of the prev word.
270 Blecch. */
271static void
272add_fix (width, exp, pc_rel, pc_fix)
273 int width;
274 struct m68k_exp *exp;
275 int pc_rel;
276 int pc_fix;
277{
278 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
279 ? (the_ins.numo*2-1)
280 : (((width)=='b')
281 ? (the_ins.numo*2+1)
282 : (the_ins.numo*2)));
283 the_ins.reloc[the_ins.nrel].exp = exp->exp;
284 the_ins.reloc[the_ins.nrel].wid = width;
285 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
286#ifdef OBJ_ELF
287 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
288#endif
289 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
290}
291
292/* Cause an extra frag to be generated here, inserting up to 10 bytes
293 (that value is chosen in the frag_var call in md_assemble). TYPE
294 is the subtype of the frag to be generated; its primary type is
295 rs_machine_dependent.
296
297 The TYPE parameter is also used by md_convert_frag_1 and
298 md_estimate_size_before_relax. The appropriate type of fixup will
299 be emitted by md_convert_frag_1.
300
301 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
302static void
303add_frag (add, off, type)
304 symbolS *add;
305 offsetT off;
306 int type;
307{
308 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
309 the_ins.fragb[the_ins.nfrag].fadd=add;
310 the_ins.fragb[the_ins.nfrag].foff=off;
311 the_ins.fragb[the_ins.nfrag++].fragty=type;
312}
313
314#define isvar(ex) \
315 (op (ex) != O_constant && op (ex) != O_big)
316
317static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
318static int get_num PARAMS ((struct m68k_exp *exp, int ok));
319static void m68k_ip PARAMS ((char *));
320static void insert_reg PARAMS ((const char *, int));
321static void select_control_regs PARAMS ((void));
322static void init_regtable PARAMS ((void));
323static int reverse_16_bits PARAMS ((int in));
324static int reverse_8_bits PARAMS ((int in));
325static void install_gen_operand PARAMS ((int mode, int val));
326static void install_operand PARAMS ((int mode, int val));
327static void s_bss PARAMS ((int));
328static void s_data1 PARAMS ((int));
329static void s_data2 PARAMS ((int));
330static void s_even PARAMS ((int));
331static void s_proc PARAMS ((int));
332static void mri_chip PARAMS ((void));
333static void s_chip PARAMS ((int));
334static void s_fopt PARAMS ((int));
335static void s_opt PARAMS ((int));
336static void s_reg PARAMS ((int));
337static void s_restore PARAMS ((int));
338static void s_save PARAMS ((int));
339static void s_mri_if PARAMS ((int));
340static void s_mri_else PARAMS ((int));
341static void s_mri_endi PARAMS ((int));
342static void s_mri_break PARAMS ((int));
343static void s_mri_next PARAMS ((int));
344static void s_mri_for PARAMS ((int));
345static void s_mri_endf PARAMS ((int));
346static void s_mri_repeat PARAMS ((int));
347static void s_mri_until PARAMS ((int));
348static void s_mri_while PARAMS ((int));
349static void s_mri_endw PARAMS ((int));
350static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
351static void md_convert_frag_1 PARAMS ((fragS *));
352
353static int current_architecture;
354
dc84e067
NC		 355struct m68k_cpu
356 {
357 unsigned long arch;
358 const char *name;
359 int alias;
360 };
252b5132 361
dc84e067
NC		 362static const struct m68k_cpu archs[] =
363 {
364 { m68000, "68000", 0 },
365 { m68010, "68010", 0 },
366 { m68020, "68020", 0 },
367 { m68030, "68030", 0 },
368 { m68040, "68040", 0 },
369 { m68060, "68060", 0 },
370 { cpu32, "cpu32", 0 },
371 { m68881, "68881", 0 },
372 { m68851, "68851", 0 },
373 { mcf5200, "5200", 0 },
374 { mcf5206e, "5206e", 0 },
375 { mcf5307, "5307", 0},
376 { mcf5407, "5407", 0},
377 /* Aliases (effectively, so far as gas is concerned) for the above
378 cpus. */
379 { m68020, "68k", 1 },
380 { m68000, "68008", 1 },
381 { m68000, "68302", 1 },
382 { m68000, "68306", 1 },
383 { m68000, "68307", 1 },
384 { m68000, "68322", 1 },
385 { m68000, "68356", 1 },
386 { m68000, "68ec000", 1 },
387 { m68000, "68hc000", 1 },
388 { m68000, "68hc001", 1 },
389 { m68020, "68ec020", 1 },
390 { m68030, "68ec030", 1 },
391 { m68040, "68ec040", 1 },
392 { m68060, "68ec060", 1 },
393 { cpu32, "68330", 1 },
394 { cpu32, "68331", 1 },
395 { cpu32, "68332", 1 },
396 { cpu32, "68333", 1 },
397 { cpu32, "68334", 1 },
398 { cpu32, "68336", 1 },
399 { cpu32, "68340", 1 },
400 { cpu32, "68341", 1 },
401 { cpu32, "68349", 1 },
402 { cpu32, "68360", 1 },
403 { m68881, "68882", 1 },
404 { mcf5200, "5202", 1 },
405 { mcf5200, "5204", 1 },
406 { mcf5200, "5206", 1 },
407 };
252b5132
RH		 408
409static const int n_archs = sizeof (archs) / sizeof (archs[0]);
410
151337e8
NC		 411/* This is the assembler relaxation table for m68k. m68k is a rich CISC
412 architecture and we have a lot of relaxation modes. */
252b5132 413
151337e8
NC		 414/* Macros used in the relaxation code. */
415#define TAB(x,y) (((x) << 2) + (y))
416#define TABTYPE(x) ((x) >> 2)
417
418/* Relaxation states. */
419#define BYTE 0
420#define SHORT 1
421#define LONG 2
422#define SZ_UNDEF 3
423
424/* Here are all the relaxation modes we support. First we can relax ordinary
425 branches. On 68020 and higher and on CPU32 all branch instructions take
426 three forms, so on these CPUs all branches always remain as such. When we
427 have to expand to the LONG form on a 68000, though, we substitute an
428 absolute jump instead. This is a direct replacement for unconditional
429 branches and a branch over a jump for conditional branches. However, if the
430 user requires PIC and disables this with --pcrel, we can only relax between
431 BYTE and SHORT forms, punting if that isn't enough. This gives us four
432 different relaxation modes for branches: */
433
434#define BRANCHBWL 1 /* branch byte, word, or long */
435#define BRABSJUNC 2 /* absolute jump for LONG, unconditional */
436#define BRABSJCOND 3 /* absolute jump for LONG, conditional */
437#define BRANCHBW 4 /* branch byte or word */
438
439/* We also relax coprocessor branches and DBcc's. All CPUs that support
440 coprocessor branches support them in word and long forms, so we have only
441 one relaxation mode for them. DBcc's are word only on all CPUs. We can
442 relax them to the LONG form with a branch-around sequence. This sequence
443 can use a long branch (if available) or an absolute jump (if acceptable).
444 This gives us two relaxation modes. If long branches are not available and
445 absolute jumps are not acceptable, we don't relax DBcc's. */
446
447#define FBRANCH 5 /* coprocessor branch */
448#define DBCCLBR 6 /* DBcc relaxable with a long branch */
449#define DBCCABSJ 7 /* DBcc relaxable with an absolute jump */
450
451/* That's all for instruction relaxation. However, we also relax PC-relative
452 operands. Specifically, we have three operand relaxation modes. On the
453 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
454 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
455 two. Also PC+displacement+index operands in their simple form (with a non-
456 suppressed index without memory indirection) are supported on all CPUs, but
457 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
458 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
459 form of the PC+displacement+index operand. Finally, some absolute operands
460 can be relaxed down to 16-bit PC-relative. */
461
462#define PCREL1632 8 /* 16-bit or 32-bit PC-relative */
463#define PCINDEX 9 /* PC+displacement+index */
464#define ABSTOPCREL 10 /* absolute relax down to 16-bit PC-relative */
252b5132
RH		 465
466/* Note that calls to frag_var need to specify the maximum expansion
467 needed; this is currently 10 bytes for DBCC. */
468
469/* The fields are:
470 How far Forward this mode will reach:
471 How far Backward this mode will reach:
472 How many bytes this mode will add to the size of the frag
473 Which mode to go to if the offset won't fit in this one
474 */
475relax_typeS md_relax_table[] =
476{
477 {1, 1, 0, 0}, /* First entries aren't used */
478 {1, 1, 0, 0}, /* For no good reason except */
479 {1, 1, 0, 0}, /* that the VAX doesn't either */
480 {1, 1, 0, 0},
481
151337e8
NC		 482 {(127), (-128), 0, TAB (BRANCHBWL, SHORT)},
483 {(32767), (-32768), 2, TAB (BRANCHBWL, LONG)},
252b5132
RH		 484 {0, 0, 4, 0},
485 {1, 1, 0, 0},
486
151337e8
NC		 487 {(127), (-128), 0, TAB (BRABSJUNC, SHORT)},
488 {(32767), (-32768), 2, TAB (BRABSJUNC, LONG)},
252b5132
RH		 489 {0, 0, 4, 0},
490 {1, 1, 0, 0},
491
151337e8
NC		 492 {(127), (-128), 0, TAB (BRABSJCOND, SHORT)},
493 {(32767), (-32768), 2, TAB (BRABSJCOND, LONG)},
494 {0, 0, 6, 0},
495 {1, 1, 0, 0},
496
497 {(127), (-128), 0, TAB (BRANCHBW, SHORT)},
498 {0, 0, 2, 0},
499 {1, 1, 0, 0},
500 {1, 1, 0, 0},
501
502 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
503 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
252b5132
RH		 504 {0, 0, 4, 0},
505 {1, 1, 0, 0},
506
151337e8
NC		 507 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
508 {(32767), (-32768), 2, TAB (DBCCLBR, LONG)},
509 {0, 0, 10, 0},
252b5132
RH		 510 {1, 1, 0, 0},
511
512 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
151337e8
NC		 513 {(32767), (-32768), 2, TAB (DBCCABSJ, LONG)},
514 {0, 0, 10, 0},
252b5132
RH		 515 {1, 1, 0, 0},
516
151337e8
NC		 517 {1, 1, 0, 0}, /* PCREL1632 doesn't come BYTE */
518 {32767, -32768, 2, TAB (PCREL1632, LONG)},
252b5132
RH		 519 {0, 0, 6, 0},
520 {1, 1, 0, 0},
521
252b5132
RH		 522 {125, -130, 0, TAB (PCINDEX, SHORT)},
523 {32765, -32770, 2, TAB (PCINDEX, LONG)},
524 {0, 0, 4, 0},
525 {1, 1, 0, 0},
151337e8
NC		 526
527 {1, 1, 0, 0}, /* ABSTOPCREL doesn't come BYTE */
528 {(32767), (-32768), 2, TAB (ABSTOPCREL, LONG)},
529 {0, 0, 4, 0},
530 {1, 1, 0, 0},
252b5132
RH		 531};
532
533/* These are the machine dependent pseudo-ops. These are included so
534 the assembler can work on the output from the SUN C compiler, which
535 generates these.
536 */
537
538/* This table describes all the machine specific pseudo-ops the assembler
539 has to support. The fields are:
540 pseudo-op name without dot
541 function to call to execute this pseudo-op
542 Integer arg to pass to the function
543 */
544const pseudo_typeS md_pseudo_table[] =
545{
546 {"data1", s_data1, 0},
547 {"data2", s_data2, 0},
548 {"bss", s_bss, 0},
549 {"even", s_even, 0},
550 {"skip", s_space, 0},
551 {"proc", s_proc, 0},
552#if defined (TE_SUN3) || defined (OBJ_ELF)
553 {"align", s_align_bytes, 0},
554#endif
555#ifdef OBJ_ELF
556 {"swbeg", s_ignore, 0},
557#endif
558 {"extend", float_cons, 'x'},
559 {"ldouble", float_cons, 'x'},
560
561 /* The following pseudo-ops are supported for MRI compatibility. */
562 {"chip", s_chip, 0},
563 {"comline", s_space, 1},
564 {"fopt", s_fopt, 0},
565 {"mask2", s_ignore, 0},
566 {"opt", s_opt, 0},
567 {"reg", s_reg, 0},
568 {"restore", s_restore, 0},
569 {"save", s_save, 0},
570
571 {"if", s_mri_if, 0},
572 {"if.b", s_mri_if, 'b'},
573 {"if.w", s_mri_if, 'w'},
574 {"if.l", s_mri_if, 'l'},
575 {"else", s_mri_else, 0},
576 {"else.s", s_mri_else, 's'},
577 {"else.l", s_mri_else, 'l'},
578 {"endi", s_mri_endi, 0},
579 {"break", s_mri_break, 0},
580 {"break.s", s_mri_break, 's'},
581 {"break.l", s_mri_break, 'l'},
582 {"next", s_mri_next, 0},
583 {"next.s", s_mri_next, 's'},
584 {"next.l", s_mri_next, 'l'},
585 {"for", s_mri_for, 0},
586 {"for.b", s_mri_for, 'b'},
587 {"for.w", s_mri_for, 'w'},
588 {"for.l", s_mri_for, 'l'},
589 {"endf", s_mri_endf, 0},
590 {"repeat", s_mri_repeat, 0},
591 {"until", s_mri_until, 0},
592 {"until.b", s_mri_until, 'b'},
593 {"until.w", s_mri_until, 'w'},
594 {"until.l", s_mri_until, 'l'},
595 {"while", s_mri_while, 0},
596 {"while.b", s_mri_while, 'b'},
597 {"while.w", s_mri_while, 'w'},
598 {"while.l", s_mri_while, 'l'},
599 {"endw", s_mri_endw, 0},
600
601 {0, 0, 0}
602};
603
252b5132
RH		 604/* The mote pseudo ops are put into the opcode table, since they
605 don't start with a . they look like opcodes to gas.
606 */
607
608#ifdef M68KCOFF
609extern void obj_coff_section PARAMS ((int));
610#endif
611
612CONST pseudo_typeS mote_pseudo_table[] =
613{
614
615 {"dcl", cons, 4},
616 {"dc", cons, 2},
617 {"dcw", cons, 2},
618 {"dcb", cons, 1},
619
620 {"dsl", s_space, 4},
621 {"ds", s_space, 2},
622 {"dsw", s_space, 2},
623 {"dsb", s_space, 1},
624
625 {"xdef", s_globl, 0},
626#ifdef OBJ_ELF
627 {"align", s_align_bytes, 0},
628#else
629 {"align", s_align_ptwo, 0},
630#endif
631#ifdef M68KCOFF
632 {"sect", obj_coff_section, 0},
633 {"section", obj_coff_section, 0},
634#endif
635 {0, 0, 0}
636};
637
638#define issbyte(x) ((x)>=-128 && (x)<=127)
639#define isubyte(x) ((x)>=0 && (x)<=255)
640#define issword(x) ((x)>=-32768 && (x)<=32767)
641#define isuword(x) ((x)>=0 && (x)<=65535)
642
643#define isbyte(x) ((x)>= -255 && (x)<=255)
644#define isword(x) ((x)>=-65536 && (x)<=65535)
645#define islong(x) (1)
646
647extern char *input_line_pointer;
648
649static char mklower_table[256];
bc805888 650#define mklower(c) (mklower_table[(unsigned char) (c)])
252b5132
RH		 651static char notend_table[256];
652static char alt_notend_table[256];
653#define notend(s) \
654 (! (notend_table[(unsigned char) *s] \
655 || (*s == ':' \
656 && alt_notend_table[(unsigned char) s[1]])))
657
658#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
659
660#ifdef NO_PCREL_RELOCS
661
662int
663make_pcrel_absolute(fixP, add_number)
664 fixS *fixP;
665 long *add_number;
666{
667 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
668
669 /* rewrite the PC relative instructions to absolute address ones.
670 * these are rumoured to be faster, and the apollo linker refuses
671 * to deal with the PC relative relocations.
672 */
673 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
674 {
675 opcode[0] = 0x4e;
676 opcode[1] = 0xf9;
677 }
678 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
679 {
680 opcode[0] = 0x4e;
681 opcode[1] = 0xb9;
682 }
683 else
684 as_fatal (_("Unknown PC relative instruction"));
685 *add_number -= 4;
686 return 0;
687}
688
689#endif /* NO_PCREL_RELOCS */
690
691short
692tc_coff_fix2rtype (fixP)
693 fixS *fixP;
694{
695 if (fixP->fx_tcbit && fixP->fx_size == 4)
696 return R_RELLONG_NEG;
697#ifdef NO_PCREL_RELOCS
698 know (fixP->fx_pcrel == 0);
699 return (fixP->fx_size == 1 ? R_RELBYTE
700 : fixP->fx_size == 2 ? R_DIR16
701 : R_DIR32);
702#else
703 return (fixP->fx_pcrel ?
704 (fixP->fx_size == 1 ? R_PCRBYTE :
705 fixP->fx_size == 2 ? R_PCRWORD :
706 R_PCRLONG) :
707 (fixP->fx_size == 1 ? R_RELBYTE :
708 fixP->fx_size == 2 ? R_RELWORD :
709 R_RELLONG));
710#endif
711}
712
713#endif
714
715#ifdef OBJ_ELF
716
717/* Compute the relocation code for a fixup of SIZE bytes, using pc
718 relative relocation if PCREL is non-zero. PIC says whether a special
719 pic relocation was requested. */
720
721static bfd_reloc_code_real_type get_reloc_code
722 PARAMS ((int, int, enum pic_relocation));
723
724static bfd_reloc_code_real_type
725get_reloc_code (size, pcrel, pic)
726 int size;
727 int pcrel;
728 enum pic_relocation pic;
729{
730 switch (pic)
731 {
732 case pic_got_pcrel:
733 switch (size)
734 {
735 case 1:
736 return BFD_RELOC_8_GOT_PCREL;
737 case 2:
738 return BFD_RELOC_16_GOT_PCREL;
739 case 4:
740 return BFD_RELOC_32_GOT_PCREL;
741 }
742 break;
743
744 case pic_got_off:
745 switch (size)
746 {
747 case 1:
748 return BFD_RELOC_8_GOTOFF;
749 case 2:
750 return BFD_RELOC_16_GOTOFF;
751 case 4:
752 return BFD_RELOC_32_GOTOFF;
753 }
754 break;
755
756 case pic_plt_pcrel:
757 switch (size)
758 {
759 case 1:
760 return BFD_RELOC_8_PLT_PCREL;
761 case 2:
762 return BFD_RELOC_16_PLT_PCREL;
763 case 4:
764 return BFD_RELOC_32_PLT_PCREL;
765 }
766 break;
767
768 case pic_plt_off:
769 switch (size)
770 {
771 case 1:
772 return BFD_RELOC_8_PLTOFF;
773 case 2:
774 return BFD_RELOC_16_PLTOFF;
775 case 4:
776 return BFD_RELOC_32_PLTOFF;
777 }
778 break;
779
780 case pic_none:
781 if (pcrel)
782 {
783 switch (size)
784 {
785 case 1:
786 return BFD_RELOC_8_PCREL;
787 case 2:
788 return BFD_RELOC_16_PCREL;
789 case 4:
790 return BFD_RELOC_32_PCREL;
791 }
792 }
793 else
794 {
795 switch (size)
796 {
797 case 1:
798 return BFD_RELOC_8;
799 case 2:
800 return BFD_RELOC_16;
801 case 4:
802 return BFD_RELOC_32;
803 }
804 }
805 }
806
807 if (pcrel)
808 {
809 if (pic == pic_none)
810 as_bad (_("Can not do %d byte pc-relative relocation"), size);
811 else
812 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
813 }
814 else
815 {
816 if (pic == pic_none)
817 as_bad (_("Can not do %d byte relocation"), size);
818 else
819 as_bad (_("Can not do %d byte pic relocation"), size);
820 }
821
822 return BFD_RELOC_NONE;
823}
824
825/* Here we decide which fixups can be adjusted to make them relative
826 to the beginning of the section instead of the symbol. Basically
827 we need to make sure that the dynamic relocations are done
828 correctly, so in some cases we force the original symbol to be
829 used. */
830int
831tc_m68k_fix_adjustable (fixP)
832 fixS *fixP;
833{
92774660 834 /* Prevent all adjustments to global symbols. */
252b5132
RH		 835 if (S_IS_EXTERNAL (fixP->fx_addsy)
836 || S_IS_WEAK (fixP->fx_addsy))
837 return 0;
838
839 /* adjust_reloc_syms doesn't know about the GOT */
840 switch (fixP->fx_r_type)
841 {
842 case BFD_RELOC_8_GOT_PCREL:
843 case BFD_RELOC_16_GOT_PCREL:
844 case BFD_RELOC_32_GOT_PCREL:
845 case BFD_RELOC_8_GOTOFF:
846 case BFD_RELOC_16_GOTOFF:
847 case BFD_RELOC_32_GOTOFF:
848 case BFD_RELOC_8_PLT_PCREL:
849 case BFD_RELOC_16_PLT_PCREL:
850 case BFD_RELOC_32_PLT_PCREL:
851 case BFD_RELOC_8_PLTOFF:
852 case BFD_RELOC_16_PLTOFF:
853 case BFD_RELOC_32_PLTOFF:
854 return 0;
855
856 case BFD_RELOC_VTABLE_INHERIT:
857 case BFD_RELOC_VTABLE_ENTRY:
858 return 0;
859
860 default:
861 return 1;
862 }
863}
864
865#else /* !OBJ_ELF */
866
867#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
868
869#endif /* OBJ_ELF */
870
871#ifdef BFD_ASSEMBLER
872
873arelent *
874tc_gen_reloc (section, fixp)
875 asection *section;
876 fixS *fixp;
877{
878 arelent *reloc;
879 bfd_reloc_code_real_type code;
880
8ec6253e
NC		 881 /* If the tcbit is set, then this was a fixup of a negative value
882 that was never resolved. We do not have a reloc to handle this,
883 so just return. We assume that other code will have detected this
884 situation and produced a helpful error message, so we just tell the
885 user that the reloc cannot be produced. */
252b5132 886 if (fixp->fx_tcbit)
8ec6253e
NC		 887 {
888 if (fixp->fx_addsy)
889 as_bad (_("Unable to produce reloc against symbol '%s'"),
890 S_GET_NAME (fixp->fx_addsy));
891 return NULL;
892 }
252b5132
RH		 893
894 if (fixp->fx_r_type != BFD_RELOC_NONE)
895 {
896 code = fixp->fx_r_type;
897
898 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
899 that fixup_segment converted a non-PC relative reloc into a
900 PC relative reloc. In such a case, we need to convert the
901 reloc code. */
902 if (fixp->fx_pcrel)
903 {
904 switch (code)
905 {
906 case BFD_RELOC_8:
907 code = BFD_RELOC_8_PCREL;
908 break;
909 case BFD_RELOC_16:
910 code = BFD_RELOC_16_PCREL;
911 break;
912 case BFD_RELOC_32:
913 code = BFD_RELOC_32_PCREL;
914 break;
915 case BFD_RELOC_8_PCREL:
916 case BFD_RELOC_16_PCREL:
917 case BFD_RELOC_32_PCREL:
918 case BFD_RELOC_8_GOT_PCREL:
919 case BFD_RELOC_16_GOT_PCREL:
920 case BFD_RELOC_32_GOT_PCREL:
921 case BFD_RELOC_8_GOTOFF:
922 case BFD_RELOC_16_GOTOFF:
923 case BFD_RELOC_32_GOTOFF:
924 case BFD_RELOC_8_PLT_PCREL:
925 case BFD_RELOC_16_PLT_PCREL:
926 case BFD_RELOC_32_PLT_PCREL:
927 case BFD_RELOC_8_PLTOFF:
928 case BFD_RELOC_16_PLTOFF:
929 case BFD_RELOC_32_PLTOFF:
930 break;
931 default:
932 as_bad_where (fixp->fx_file, fixp->fx_line,
933 _("Cannot make %s relocation PC relative"),
934 bfd_get_reloc_code_name (code));
935 }
936 }
937 }
938 else
939 {
940#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
941 switch (F (fixp->fx_size, fixp->fx_pcrel))
942 {
943#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
944 MAP (1, 0, BFD_RELOC_8);
945 MAP (2, 0, BFD_RELOC_16);
946 MAP (4, 0, BFD_RELOC_32);
947 MAP (1, 1, BFD_RELOC_8_PCREL);
948 MAP (2, 1, BFD_RELOC_16_PCREL);
949 MAP (4, 1, BFD_RELOC_32_PCREL);
950 default:
951 abort ();
952 }
953 }
954#undef F
955#undef MAP
956
957 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 958 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
959 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 960 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
961#ifndef OBJ_ELF
962 if (fixp->fx_pcrel)
963 reloc->addend = fixp->fx_addnumber;
964 else
965 reloc->addend = 0;
966#else
967 if (!fixp->fx_pcrel)
968 reloc->addend = fixp->fx_addnumber;
969 else
970 reloc->addend = (section->vma
8390138c
AS		 971 /* Explicit sign extension in case char is
972 unsigned. */
973 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 974 + fixp->fx_addnumber
975 + md_pcrel_from (fixp));
976#endif
977
978 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
979 assert (reloc->howto != 0);
980
981 return reloc;
982}
983
984#endif /* BFD_ASSEMBLER */
985
986/* Return zero if the reference to SYMBOL from within the same segment may
987 be relaxed. */
988#ifdef OBJ_ELF
989
990/* On an ELF system, we can't relax an externally visible symbol,
991 because it may be overridden by a shared library. However, if
992 TARGET_OS is "elf", then we presume that we are assembling for an
993 embedded system, in which case we don't have to worry about shared
994 libraries, and we can relax anything. */
995
996#define relaxable_symbol(symbol) \
997 (strcmp (TARGET_OS, "elf") == 0 \
998 || (! S_IS_EXTERNAL (symbol) \
999 && ! S_IS_WEAK (symbol)))
1000
1001#else
1002
1003#define relaxable_symbol(symbol) 1
1004
1005#endif
92774660 1006
252b5132
RH		 1007/* Handle of the OPCODE hash table. NULL means any use before
1008 m68k_ip_begin() will crash. */
1009static struct hash_control *op_hash;
1010\f
1011/* Assemble an m68k instruction. */
1012
1013static void
1014m68k_ip (instring)
1015 char *instring;
1016{
1017 register char *p;
1018 register struct m68k_op *opP;
1019 register const struct m68k_incant *opcode;
1020 register const char *s;
1021 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1022 char *pdot, *pdotmove;
1023 enum m68k_size siz1, siz2;
1024 char c;
1025 int losing;
1026 int opsfound;
1027 LITTLENUM_TYPE words[6];
1028 LITTLENUM_TYPE *wordp;
1029 unsigned long ok_arch = 0;
1030
1031 if (*instring == ' ')
1032 instring++; /* skip leading whitespace */
1033
1034 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1035 or exactly 1 space. */
252b5132
RH		 1036 pdot = 0;
1037 for (p = instring; *p != '\0'; p++)
1038 {
1039 if (*p == ' ')
1040 break;
1041 if (*p == '.')
1042 pdot = p;
1043 }
1044
1045 if (p == instring)
1046 {
1047 the_ins.error = _("No operator");
1048 return;
1049 }
1050
1051 /* p now points to the end of the opcode name, probably whitespace.
1052 Make sure the name is null terminated by clobbering the
1053 whitespace, look it up in the hash table, then fix it back.
1054 Remove a dot, first, since the opcode tables have none. */
1055 if (pdot != NULL)
1056 {
1057 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1058 *pdotmove = pdotmove[1];
1059 p--;
1060 }
1061
1062 c = *p;
1063 *p = '\0';
1064 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1065 *p = c;
1066
1067 if (pdot != NULL)
1068 {
1069 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1070 *pdotmove = pdotmove[-1];
1071 *pdot = '.';
1072 ++p;
1073 }
1074
1075 if (opcode == NULL)
1076 {
1077 the_ins.error = _("Unknown operator");
1078 return;
1079 }
1080
1081 /* found a legitimate opcode, start matching operands */
1082 while (*p == ' ')
1083 ++p;
1084
1085 if (opcode->m_operands == 0)
1086 {
1087 char *old = input_line_pointer;
1088 *old = '\n';
1089 input_line_pointer = p;
1090 /* Ahh - it's a motorola style psuedo op */
1091 mote_pseudo_table[opcode->m_opnum].poc_handler
1092 (mote_pseudo_table[opcode->m_opnum].poc_val);
1093 input_line_pointer = old;
1094 *old = 0;
1095
1096 return;
1097 }
1098
1099 if (flag_mri && opcode->m_opnum == 0)
1100 {
1101 /* In MRI mode, random garbage is allowed after an instruction
1102 which accepts no operands. */
1103 the_ins.args = opcode->m_operands;
1104 the_ins.numargs = opcode->m_opnum;
1105 the_ins.numo = opcode->m_codenum;
1106 the_ins.opcode[0] = getone (opcode);
1107 the_ins.opcode[1] = gettwo (opcode);
1108 return;
1109 }
1110
1111 for (opP = &the_ins.operands[0]; *p; opP++)
1112 {
1113 p = crack_operand (p, opP);
1114
1115 if (opP->error)
1116 {
1117 the_ins.error = opP->error;
1118 return;
1119 }
1120 }
1121
1122 opsfound = opP - &the_ins.operands[0];
1123
1124 /* This ugly hack is to support the floating pt opcodes in their
1125 standard form. Essentially, we fake a first enty of type COP#1 */
1126 if (opcode->m_operands[0] == 'I')
1127 {
1128 int n;
1129
1130 for (n = opsfound; n > 0; --n)
1131 the_ins.operands[n] = the_ins.operands[n - 1];
1132
1133 memset ((char *) (&the_ins.operands[0]), '\0',
1134 sizeof (the_ins.operands[0]));
1135 the_ins.operands[0].mode = CONTROL;
1136 the_ins.operands[0].reg = m68k_float_copnum;
1137 opsfound++;
1138 }
1139
1140 /* We've got the operands. Find an opcode that'll accept them */
1141 for (losing = 0;;)
1142 {
1143 /* If we didn't get the right number of ops, or we have no
92774660 1144 common model with this pattern then reject this pattern. */
252b5132
RH		 1145
1146 ok_arch |= opcode->m_arch;
1147 if (opsfound != opcode->m_opnum
1148 || ((opcode->m_arch & current_architecture) == 0))
1149 ++losing;
1150 else
1151 {
1152 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1153 *s && !losing;
1154 s += 2, opP++)
1155 {
1156 /* Warning: this switch is huge! */
1157 /* I've tried to organize the cases into this order:
1158 non-alpha first, then alpha by letter. Lower-case
1159 goes directly before uppercase counterpart. */
1160 /* Code with multiple case ...: gets sorted by the lowest
1161 case ... it belongs to. I hope this makes sense. */
1162 switch (*s)
1163 {
1164 case '!':
1165 switch (opP->mode)
1166 {
1167 case IMMED:
1168 case DREG:
1169 case AREG:
1170 case FPREG:
1171 case CONTROL:
1172 case AINC:
1173 case ADEC:
1174 case REGLST:
1175 losing++;
1176 break;
1177 default:
1178 break;
1179 }
1180 break;
1181
1182 case '<':
1183 switch (opP->mode)
1184 {
1185 case DREG:
1186 case AREG:
1187 case FPREG:
1188 case CONTROL:
1189 case IMMED:
1190 case ADEC:
1191 case REGLST:
1192 losing++;
1193 break;
1194 default:
1195 break;
1196 }
1197 break;
1198
1199 case '>':
1200 switch (opP->mode)
1201 {
1202 case DREG:
1203 case AREG:
1204 case FPREG:
1205 case CONTROL:
1206 case IMMED:
1207 case AINC:
1208 case REGLST:
1209 losing++;
1210 break;
1211 case ABSL:
1212 break;
1213 default:
1214 if (opP->reg == PC
1215 || opP->reg == ZPC)
1216 losing++;
1217 break;
1218 }
1219 break;
1220
1221 case 'm':
1222 switch (opP->mode)
1223 {
1224 case DREG:
1225 case AREG:
1226 case AINDR:
1227 case AINC:
1228 case ADEC:
1229 break;
1230 default:
1231 losing++;
1232 }
1233 break;
1234
1235 case 'n':
1236 switch (opP->mode)
1237 {
1238 case DISP:
1239 break;
1240 default:
1241 losing++;
1242 }
1243 break;
1244
1245 case 'o':
1246 switch (opP->mode)
1247 {
1248 case BASE:
1249 case ABSL:
1250 case IMMED:
1251 break;
1252 default:
1253 losing++;
1254 }
1255 break;
1256
1257 case 'p':
1258 switch (opP->mode)
1259 {
1260 case DREG:
1261 case AREG:
1262 case AINDR:
1263 case AINC:
1264 case ADEC:
1265 break;
1266 case DISP:
1267 if (opP->reg == PC || opP->reg == ZPC)
1268 losing++;
1269 break;
1270 default:
1271 losing++;
1272 }
1273 break;
1274
1275 case 'q':
1276 switch (opP->mode)
1277 {
1278 case DREG:
1279 case AINDR:
1280 case AINC:
1281 case ADEC:
1282 break;
1283 case DISP:
1284 if (opP->reg == PC || opP->reg == ZPC)
1285 losing++;
1286 break;
1287 default:
1288 losing++;
1289 break;
1290 }
1291 break;
1292
1293 case 'v':
1294 switch (opP->mode)
1295 {
1296 case DREG:
1297 case AINDR:
1298 case AINC:
1299 case ADEC:
1300 case ABSL:
1301 break;
1302 case DISP:
1303 if (opP->reg == PC || opP->reg == ZPC)
1304 losing++;
1305 break;
1306 default:
1307 losing++;
1308 break;
1309 }
1310 break;
1311
1312 case '#':
1313 if (opP->mode != IMMED)
1314 losing++;
1315 else if (s[1] == 'b'
1316 && ! isvar (&opP->disp)
1317 && (opP->disp.exp.X_op != O_constant
1318 || ! isbyte (opP->disp.exp.X_add_number)))
1319 losing++;
1320 else if (s[1] == 'B'
1321 && ! isvar (&opP->disp)
1322 && (opP->disp.exp.X_op != O_constant
1323 || ! issbyte (opP->disp.exp.X_add_number)))
1324 losing++;
1325 else if (s[1] == 'w'
1326 && ! isvar (&opP->disp)
1327 && (opP->disp.exp.X_op != O_constant
1328 || ! isword (opP->disp.exp.X_add_number)))
1329 losing++;
1330 else if (s[1] == 'W'
1331 && ! isvar (&opP->disp)
1332 && (opP->disp.exp.X_op != O_constant
1333 || ! issword (opP->disp.exp.X_add_number)))
1334 losing++;
1335 break;
1336
1337 case '^':
1338 case 'T':
1339 if (opP->mode != IMMED)
1340 losing++;
1341 break;
1342
1343 case '$':
1344 if (opP->mode == AREG
1345 || opP->mode == CONTROL
1346 || opP->mode == FPREG
1347 || opP->mode == IMMED
1348 || opP->mode == REGLST
1349 || (opP->mode != ABSL
1350 && (opP->reg == PC
1351 || opP->reg == ZPC)))
1352 losing++;
1353 break;
1354
1355 case '%':
1356 if (opP->mode == CONTROL
1357 || opP->mode == FPREG
1358 || opP->mode == REGLST
1359 || opP->mode == IMMED
1360 || (opP->mode != ABSL
1361 && (opP->reg == PC
1362 || opP->reg == ZPC)))
1363 losing++;
1364 break;
1365
1366 case '&':
1367 switch (opP->mode)
1368 {
1369 case DREG:
1370 case AREG:
1371 case FPREG:
1372 case CONTROL:
1373 case IMMED:
1374 case AINC:
1375 case ADEC:
1376 case REGLST:
1377 losing++;
1378 break;
1379 case ABSL:
1380 break;
1381 default:
1382 if (opP->reg == PC
1383 || opP->reg == ZPC)
1384 losing++;
1385 break;
1386 }
1387 break;
1388
1389 case '*':
1390 if (opP->mode == CONTROL
1391 || opP->mode == FPREG
1392 || opP->mode == REGLST)
1393 losing++;
1394 break;
1395
1396 case '+':
1397 if (opP->mode != AINC)
1398 losing++;
1399 break;
1400
1401 case '-':
1402 if (opP->mode != ADEC)
1403 losing++;
1404 break;
1405
1406 case '/':
1407 switch (opP->mode)
1408 {
1409 case AREG:
1410 case CONTROL:
1411 case FPREG:
1412 case AINC:
1413 case ADEC:
1414 case IMMED:
1415 case REGLST:
1416 losing++;
1417 break;
1418 default:
1419 break;
1420 }
1421 break;
1422
1423 case ';':
1424 switch (opP->mode)
1425 {
1426 case AREG:
1427 case CONTROL:
1428 case FPREG:
1429 case REGLST:
1430 losing++;
1431 break;
1432 default:
1433 break;
1434 }
1435 break;
1436
1437 case '?':
1438 switch (opP->mode)
1439 {
1440 case AREG:
1441 case CONTROL:
1442 case FPREG:
1443 case AINC:
1444 case ADEC:
1445 case IMMED:
1446 case REGLST:
1447 losing++;
1448 break;
1449 case ABSL:
1450 break;
1451 default:
1452 if (opP->reg == PC || opP->reg == ZPC)
1453 losing++;
1454 break;
1455 }
1456 break;
1457
1458 case '@':
1459 switch (opP->mode)
1460 {
1461 case AREG:
1462 case CONTROL:
1463 case FPREG:
1464 case IMMED:
1465 case REGLST:
1466 losing++;
1467 break;
1468 default:
1469 break;
1470 }
1471 break;
1472
1473 case '~': /* For now! (JF FOO is this right?) */
1474 switch (opP->mode)
1475 {
1476 case DREG:
1477 case AREG:
1478 case CONTROL:
1479 case FPREG:
1480 case IMMED:
1481 case REGLST:
1482 losing++;
1483 break;
1484 case ABSL:
1485 break;
1486 default:
1487 if (opP->reg == PC
1488 || opP->reg == ZPC)
1489 losing++;
1490 break;
1491 }
1492 break;
1493
1494 case '3':
1495 if (opP->mode != CONTROL
1496 || (opP->reg != TT0 && opP->reg != TT1))
1497 losing++;
1498 break;
1499
1500 case 'A':
1501 if (opP->mode != AREG)
1502 losing++;
1503 break;
1504
1505 case 'a':
1506 if (opP->mode != AINDR)
1507 ++losing;
1508 break;
1509
1510 case 'B': /* FOO */
1511 if (opP->mode != ABSL
1512 || (flag_long_jumps
1513 && strncmp (instring, "jbsr", 4) == 0))
1514 losing++;
1515 break;
1516
1517 case 'C':
1518 if (opP->mode != CONTROL || opP->reg != CCR)
1519 losing++;
1520 break;
1521
1522 case 'd':
1523 if (opP->mode != DISP
1524 || opP->reg < ADDR0
1525 || opP->reg > ADDR7)
1526 losing++;
1527 break;
1528
1529 case 'D':
1530 if (opP->mode != DREG)
1531 losing++;
1532 break;
1533
6da466c7
ILT		 1534 case 'E':
1535 if (opP->reg != ACC)
1536 losing++;
1537 break;
1538
252b5132
RH		 1539 case 'F':
1540 if (opP->mode != FPREG)
1541 losing++;
1542 break;
1543
6da466c7
ILT		 1544 case 'G':
1545 if (opP->reg != MACSR)
1546 losing++;
1547 break;
1548
1549 case 'H':
1550 if (opP->reg != MASK)
1551 losing++;
1552 break;
1553
252b5132
RH		 1554 case 'I':
1555 if (opP->mode != CONTROL
1556 || opP->reg < COP0
1557 || opP->reg > COP7)
1558 losing++;
1559 break;
1560
1561 case 'J':
1562 if (opP->mode != CONTROL
1563 || opP->reg < USP
1564 || opP->reg > last_movec_reg)
1565 losing++;
1566 else
1567 {
1568 const enum m68k_register *rp;
1569 for (rp = control_regs; *rp; rp++)
1570 if (*rp == opP->reg)
1571 break;
1572 if (*rp == 0)
1573 losing++;
1574 }
1575 break;
1576
1577 case 'k':
1578 if (opP->mode != IMMED)
1579 losing++;
1580 break;
1581
1582 case 'l':
1583 case 'L':
1584 if (opP->mode == DREG
1585 || opP->mode == AREG
1586 || opP->mode == FPREG)
1587 {
1588 if (s[1] == '8')
1589 losing++;
1590 else
1591 {
1592 switch (opP->mode)
1593 {
1594 case DREG:
1595 opP->mask = 1 << (opP->reg - DATA0);
1596 break;
1597 case AREG:
1598 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1599 break;
1600 case FPREG:
1601 opP->mask = 1 << (opP->reg - FP0 + 16);
1602 break;
1603 default:
1604 abort ();
1605 }
1606 opP->mode = REGLST;
1607 }
1608 }
1609 else if (opP->mode == CONTROL)
1610 {
1611 if (s[1] != '8')
1612 losing++;
1613 else
1614 {
1615 switch (opP->reg)
1616 {
1617 case FPI:
1618 opP->mask = 1 << 24;
1619 break;
1620 case FPS:
1621 opP->mask = 1 << 25;
1622 break;
1623 case FPC:
1624 opP->mask = 1 << 26;
1625 break;
1626 default:
1627 losing++;
1628 break;
1629 }
1630 opP->mode = REGLST;
1631 }
1632 }
1633 else if (opP->mode != REGLST)
1634 losing++;
1635 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1636 losing++;
1637 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1638 losing++;
1639 break;
1640
1641 case 'M':
1642 if (opP->mode != IMMED)
1643 losing++;
1644 else if (opP->disp.exp.X_op != O_constant
1645 || ! issbyte (opP->disp.exp.X_add_number))
1646 losing++;
1647 else if (! m68k_quick
1648 && instring[3] != 'q'
1649 && instring[4] != 'q')
1650 losing++;
1651 break;
1652
1653 case 'O':
1654 if (opP->mode != DREG
1655 && opP->mode != IMMED
1656 && opP->mode != ABSL)
1657 losing++;
1658 break;
1659
1660 case 'Q':
1661 if (opP->mode != IMMED)
1662 losing++;
1663 else if (opP->disp.exp.X_op != O_constant
1664 || opP->disp.exp.X_add_number < 1
1665 || opP->disp.exp.X_add_number > 8)
1666 losing++;
1667 else if (! m68k_quick
1668 && (strncmp (instring, "add", 3) == 0
1669 || strncmp (instring, "sub", 3) == 0)
1670 && instring[3] != 'q')
1671 losing++;
1672 break;
1673
1674 case 'R':
1675 if (opP->mode != DREG && opP->mode != AREG)
1676 losing++;
1677 break;
1678
1679 case 'r':
1680 if (opP->mode != AINDR
1681 && (opP->mode != BASE
1682 || (opP->reg != 0
1683 && opP->reg != ZADDR0)
1684 || opP->disp.exp.X_op != O_absent
1685 || ((opP->index.reg < DATA0
1686 || opP->index.reg > DATA7)
1687 && (opP->index.reg < ADDR0
1688 || opP->index.reg > ADDR7))
1689 || opP->index.size != SIZE_UNSPEC
1690 || opP->index.scale != 1))
1691 losing++;
1692 break;
1693
1694 case 's':
1695 if (opP->mode != CONTROL
1696 || ! (opP->reg == FPI
1697 || opP->reg == FPS
1698 || opP->reg == FPC))
1699 losing++;
1700 break;
1701
1702 case 'S':
1703 if (opP->mode != CONTROL || opP->reg != SR)
1704 losing++;
1705 break;
1706
1707 case 't':
1708 if (opP->mode != IMMED)
1709 losing++;
1710 else if (opP->disp.exp.X_op != O_constant
1711 || opP->disp.exp.X_add_number < 0
1712 || opP->disp.exp.X_add_number > 7)
1713 losing++;
1714 break;
1715
1716 case 'U':
1717 if (opP->mode != CONTROL || opP->reg != USP)
1718 losing++;
1719 break;
1720
1721 /* JF these are out of order. We could put them
1722 in order if we were willing to put up with
1723 bunches of #ifdef m68851s in the code.
1724
1725 Don't forget that you need these operands
1726 to use 68030 MMU instructions. */
1727#ifndef NO_68851
1728 /* Memory addressing mode used by pflushr */
1729 case '|':
1730 if (opP->mode == CONTROL
1731 || opP->mode == FPREG
1732 || opP->mode == DREG
1733 || opP->mode == AREG
1734 || opP->mode == REGLST)
1735 losing++;
1736 /* We should accept immediate operands, but they
1737 supposedly have to be quad word, and we don't
1738 handle that. I would like to see what a Motorola
1739 assembler does before doing something here. */
1740 if (opP->mode == IMMED)
1741 losing++;
1742 break;
1743
1744 case 'f':
1745 if (opP->mode != CONTROL
1746 || (opP->reg != SFC && opP->reg != DFC))
1747 losing++;
1748 break;
1749
1750 case '0':
1751 if (opP->mode != CONTROL || opP->reg != TC)
1752 losing++;
1753 break;
1754
1755 case '1':
1756 if (opP->mode != CONTROL || opP->reg != AC)
1757 losing++;
1758 break;
1759
1760 case '2':
1761 if (opP->mode != CONTROL
1762 || (opP->reg != CAL
1763 && opP->reg != VAL
1764 && opP->reg != SCC))
1765 losing++;
1766 break;
1767
1768 case 'V':
1769 if (opP->mode != CONTROL
1770 || opP->reg != VAL)
1771 losing++;
1772 break;
1773
1774 case 'W':
1775 if (opP->mode != CONTROL
1776 || (opP->reg != DRP
1777 && opP->reg != SRP
1778 && opP->reg != CRP))
1779 losing++;
1780 break;
1781
1782 case 'X':
1783 if (opP->mode != CONTROL
1784 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1785 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1786 losing++;
1787 break;
1788
1789 case 'Y':
1790 if (opP->mode != CONTROL || opP->reg != PSR)
1791 losing++;
1792 break;
1793
1794 case 'Z':
1795 if (opP->mode != CONTROL || opP->reg != PCSR)
1796 losing++;
1797 break;
1798#endif
1799 case 'c':
1800 if (opP->mode != CONTROL
1801 || (opP->reg != NC
1802 && opP->reg != IC
1803 && opP->reg != DC
1804 && opP->reg != BC))
1805 {
1806 losing++;
92774660 1807 } /* not a cache specifier. */
252b5132
RH		 1808 break;
1809
1810 case '_':
1811 if (opP->mode != ABSL)
1812 ++losing;
1813 break;
1814
6da466c7
ILT		 1815 case 'u':
1816 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1817 losing++;
1818 /* FIXME: kludge instead of fixing parser:
1819 upper/lower registers are *not* CONTROL
92774660 1820 registers, but ordinary ones. */
6da466c7
ILT		 1821 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1822 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1823 opP->mode = DREG;
1824 else
1825 opP->mode = AREG;
1826 break;
1827
252b5132
RH		 1828 default:
1829 abort ();
1830 } /* switch on type of operand */
1831
1832 if (losing)
1833 break;
1834 } /* for each operand */
1835 } /* if immediately wrong */
1836
1837 if (!losing)
1838 {
1839 break;
92774660 1840 } /* got it. */
252b5132
RH		 1841
1842 opcode = opcode->m_next;
1843
1844 if (!opcode)
1845 {
1846 if (ok_arch
1847 && !(ok_arch & current_architecture))
1848 {
1849 char buf[200], *cp;
1850
1851 strcpy (buf,
1852 _("invalid instruction for this architecture; needs "));
1853 cp = buf + strlen (buf);
1854 switch (ok_arch)
1855 {
1856 case mfloat:
1857 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1858 break;
1859 case mmmu:
1860 strcpy (cp, _("mmu (68030 or 68851)"));
1861 break;
1862 case m68020up:
1863 strcpy (cp, _("68020 or higher"));
1864 break;
1865 case m68000up:
1866 strcpy (cp, _("68000 or higher"));
1867 break;
1868 case m68010up:
1869 strcpy (cp, _("68010 or higher"));
1870 break;
1871 default:
1872 {
1873 int got_one = 0, idx;
8fce3f5e
AM		 1874 for (idx = 0;
1875 idx < (int) (sizeof (archs) / sizeof (archs[0]));
252b5132
RH		 1876 idx++)
1877 {
1878 if ((archs[idx].arch & ok_arch)
1879 && ! archs[idx].alias)
1880 {
1881 if (got_one)
1882 {
1883 strcpy (cp, " or ");
1884 cp += strlen (cp);
1885 }
1886 got_one = 1;
1887 strcpy (cp, archs[idx].name);
1888 cp += strlen (cp);
1889 }
1890 }
1891 }
1892 }
1893 cp = xmalloc (strlen (buf) + 1);
1894 strcpy (cp, buf);
1895 the_ins.error = cp;
1896 }
1897 else
1898 the_ins.error = _("operands mismatch");
1899 return;
1900 } /* Fell off the end */
1901
1902 losing = 0;
1903 }
1904
1905 /* now assemble it */
1906
1907 the_ins.args = opcode->m_operands;
1908 the_ins.numargs = opcode->m_opnum;
1909 the_ins.numo = opcode->m_codenum;
1910 the_ins.opcode[0] = getone (opcode);
1911 the_ins.opcode[1] = gettwo (opcode);
1912
1913 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1914 {
1915 /* This switch is a doozy.
1916 Watch the first step; its a big one! */
1917 switch (s[0])
1918 {
1919
1920 case '*':
1921 case '~':
1922 case '%':
1923 case ';':
1924 case '@':
1925 case '!':
1926 case '&':
1927 case '$':
1928 case '?':
1929 case '/':
1930 case '<':
1931 case '>':
1932 case 'm':
1933 case 'n':
1934 case 'o':
1935 case 'p':
1936 case 'q':
1937 case 'v':
1938#ifndef NO_68851
1939 case '|':
1940#endif
1941 switch (opP->mode)
1942 {
1943 case IMMED:
1944 tmpreg = 0x3c; /* 7.4 */
1945 if (strchr ("bwl", s[1]))
1946 nextword = get_num (&opP->disp, 80);
1947 else
1948 nextword = get_num (&opP->disp, 0);
1949 if (isvar (&opP->disp))
1950 add_fix (s[1], &opP->disp, 0, 0);
1951 switch (s[1])
1952 {
1953 case 'b':
1954 if (!isbyte (nextword))
1955 opP->error = _("operand out of range");
1956 addword (nextword);
1957 baseo = 0;
1958 break;
1959 case 'w':
1960 if (!isword (nextword))
1961 opP->error = _("operand out of range");
1962 addword (nextword);
1963 baseo = 0;
1964 break;
1965 case 'W':
1966 if (!issword (nextword))
1967 opP->error = _("operand out of range");
1968 addword (nextword);
1969 baseo = 0;
1970 break;
1971 case 'l':
1972 addword (nextword >> 16);
1973 addword (nextword);
1974 baseo = 0;
1975 break;
1976
1977 case 'f':
1978 baseo = 2;
1979 outro = 8;
1980 break;
1981 case 'F':
1982 baseo = 4;
1983 outro = 11;
1984 break;
1985 case 'x':
1986 baseo = 6;
1987 outro = 15;
1988 break;
1989 case 'p':
1990 baseo = 6;
1991 outro = -1;
1992 break;
1993 default:
1994 abort ();
1995 }
1996 if (!baseo)
1997 break;
1998
1999 /* We gotta put out some float */
2000 if (op (&opP->disp) != O_big)
2001 {
2002 valueT val;
2003 int gencnt;
2004
2005 /* Can other cases happen here? */
2006 if (op (&opP->disp) != O_constant)
2007 abort ();
2008
2009 val = (valueT) offs (&opP->disp);
2010 gencnt = 0;
2011 do
2012 {
2013 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2014 val >>= LITTLENUM_NUMBER_OF_BITS;
2015 ++gencnt;
2016 }
2017 while (val != 0);
2018 offs (&opP->disp) = gencnt;
2019 }
2020 if (offs (&opP->disp) > 0)
2021 {
2022 if (offs (&opP->disp) > baseo)
2023 {
2024 as_warn (_("Bignum too big for %c format; truncated"),
2025 s[1]);
2026 offs (&opP->disp) = baseo;
2027 }
2028 baseo -= offs (&opP->disp);
2029 while (baseo--)
2030 addword (0);
2031 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2032 offs (&opP->disp)--;
2033 --wordp)
2034 addword (*wordp);
2035 break;
2036 }
2037 gen_to_words (words, baseo, (long) outro);
2038 for (wordp = words; baseo--; wordp++)
2039 addword (*wordp);
2040 break;
2041 case DREG:
2042 tmpreg = opP->reg - DATA; /* 0.dreg */
2043 break;
2044 case AREG:
2045 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2046 break;
2047 case AINDR:
2048 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2049 break;
2050 case ADEC:
2051 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2052 break;
2053 case AINC:
2054 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2055 break;
2056 case DISP:
2057
2058 nextword = get_num (&opP->disp, 80);
2059
2060 if (opP->reg == PC
2061 && ! isvar (&opP->disp)
2062 && m68k_abspcadd)
2063 {
2064 opP->disp.exp.X_op = O_symbol;
2065#ifndef BFD_ASSEMBLER
2066 opP->disp.exp.X_add_symbol = &abs_symbol;
2067#else
2068 opP->disp.exp.X_add_symbol =
2069 section_symbol (absolute_section);
2070#endif
2071 }
2072
2073 /* Force into index mode. Hope this works */
2074
2075 /* We do the first bit for 32-bit displacements, and the
2076 second bit for 16 bit ones. It is possible that we
2077 should make the default be WORD instead of LONG, but
2078 I think that'd break GCC, so we put up with a little
2079 inefficiency for the sake of working output. */
2080
2081 if (!issword (nextword)
2082 || (isvar (&opP->disp)
2083 && ((opP->disp.size == SIZE_UNSPEC
2084 && flag_short_refs == 0
2085 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2086 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2087 || opP->disp.size == SIZE_LONG)))
2088 {
2089 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2090 || arch_coldfire_p (current_architecture))
252b5132
RH		 2091 opP->error =
2092 _("displacement too large for this architecture; needs 68020 or higher");
2093 if (opP->reg == PC)
2094 tmpreg = 0x3B; /* 7.3 */
2095 else
2096 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2097 if (isvar (&opP->disp))
2098 {
2099 if (opP->reg == PC)
2100 {
2101 if (opP->disp.size == SIZE_LONG
2102#ifdef OBJ_ELF
2103 /* If the displacement needs pic
2104 relocation it cannot be relaxed. */
2105 || opP->disp.pic_reloc != pic_none
2106#endif
2107 )
2108 {
2109 addword (0x0170);
2110 add_fix ('l', &opP->disp, 1, 2);
2111 }
2112 else
2113 {
2114 add_frag (adds (&opP->disp),
2115 offs (&opP->disp),
151337e8 2116 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2117 break;
2118 }
2119 }
2120 else
2121 {
2122 addword (0x0170);
2123 add_fix ('l', &opP->disp, 0, 0);
2124 }
2125 }
2126 else
2127 addword (0x0170);
2128 addword (nextword >> 16);
2129 }
2130 else
2131 {
2132 if (opP->reg == PC)
2133 tmpreg = 0x3A; /* 7.2 */
2134 else
2135 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2136
2137 if (isvar (&opP->disp))
2138 {
2139 if (opP->reg == PC)
2140 {
2141 add_fix ('w', &opP->disp, 1, 0);
2142 }
2143 else
2144 add_fix ('w', &opP->disp, 0, 0);
2145 }
2146 }
2147 addword (nextword);
2148 break;
2149
2150 case POST:
2151 case PRE:
2152 case BASE:
2153 nextword = 0;
2154 baseo = get_num (&opP->disp, 80);
2155 if (opP->mode == POST || opP->mode == PRE)
2156 outro = get_num (&opP->odisp, 80);
2157 /* Figure out the `addressing mode'.
2158 Also turn on the BASE_DISABLE bit, if needed. */
2159 if (opP->reg == PC || opP->reg == ZPC)
2160 {
2161 tmpreg = 0x3b; /* 7.3 */
2162 if (opP->reg == ZPC)
2163 nextword |= 0x80;
2164 }
2165 else if (opP->reg == 0)
2166 {
2167 nextword |= 0x80;
2168 tmpreg = 0x30; /* 6.garbage */
2169 }
2170 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2171 {
2172 nextword |= 0x80;
2173 tmpreg = 0x30 + opP->reg - ZADDR0;
2174 }
2175 else
2176 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2177
2178 siz1 = opP->disp.size;
2179 if (opP->mode == POST || opP->mode == PRE)
2180 siz2 = opP->odisp.size;
2181 else
2182 siz2 = SIZE_UNSPEC;
2183
2184 /* Index register stuff */
2185 if (opP->index.reg != 0
2186 && opP->index.reg >= DATA
2187 && opP->index.reg <= ADDR7)
2188 {
2189 nextword |= (opP->index.reg - DATA) << 12;
2190
2191 if (opP->index.size == SIZE_LONG
2192 || (opP->index.size == SIZE_UNSPEC
2193 && m68k_index_width_default == SIZE_LONG))
2194 nextword |= 0x800;
2195
92774660 2196 if ((opP->index.scale != 1
252b5132 2197 && cpu_of_arch (current_architecture) < m68020)
92774660 2198 || (opP->index.scale == 8
6da466c7 2199 && arch_coldfire_p (current_architecture)))
252b5132
RH		 2200 {
2201 opP->error =
2202 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2203 }
2204
6da466c7
ILT		 2205 if (arch_coldfire_p (current_architecture)
2206 && opP->index.size == SIZE_WORD)
2207 opP->error = _("invalid index size for coldfire");
2208
252b5132
RH		 2209 switch (opP->index.scale)
2210 {
2211 case 1:
2212 break;
2213 case 2:
2214 nextword |= 0x200;
2215 break;
2216 case 4:
2217 nextword |= 0x400;
2218 break;
2219 case 8:
2220 nextword |= 0x600;
2221 break;
2222 default:
2223 abort ();
2224 }
2225 /* IF its simple,
2226 GET US OUT OF HERE! */
2227
2228 /* Must be INDEX, with an index register. Address
2229 register cannot be ZERO-PC, and either :b was
2230 forced, or we know it will fit. For a 68000 or
2231 68010, force this mode anyways, because the
2232 larger modes aren't supported. */
2233 if (opP->mode == BASE
2234 && ((opP->reg >= ADDR0
2235 && opP->reg <= ADDR7)
2236 || opP->reg == PC))
2237 {
2238 if (siz1 == SIZE_BYTE
2239 || cpu_of_arch (current_architecture) < m68020
6da466c7 2240 || arch_coldfire_p (current_architecture)
252b5132
RH		 2241 || (siz1 == SIZE_UNSPEC
2242 && ! isvar (&opP->disp)
2243 && issbyte (baseo)))
2244 {
2245 nextword += baseo & 0xff;
2246 addword (nextword);
2247 if (isvar (&opP->disp))
2248 {
2249 /* Do a byte relocation. If it doesn't
2250 fit (possible on m68000) let the
2251 fixup processing complain later. */
2252 if (opP->reg == PC)
2253 add_fix ('B', &opP->disp, 1, 1);
2254 else
2255 add_fix ('B', &opP->disp, 0, 0);
2256 }
2257 else if (siz1 != SIZE_BYTE)
2258 {
2259 if (siz1 != SIZE_UNSPEC)
2260 as_warn (_("Forcing byte displacement"));
2261 if (! issbyte (baseo))
2262 opP->error = _("byte displacement out of range");
2263 }
2264
2265 break;
2266 }
2267 else if (siz1 == SIZE_UNSPEC
2268 && opP->reg == PC
2269 && isvar (&opP->disp)
2270 && subs (&opP->disp) == NULL
2271#ifdef OBJ_ELF
2272 /* If the displacement needs pic
2273 relocation it cannot be relaxed. */
2274 && opP->disp.pic_reloc == pic_none
2275#endif
2276 )
2277 {
2278 /* The code in md_convert_frag_1 needs to be
2279 able to adjust nextword. Call frag_grow
2280 to ensure that we have enough space in
2281 the frag obstack to make all the bytes
2282 contiguous. */
2283 frag_grow (14);
2284 nextword += baseo & 0xff;
2285 addword (nextword);
2286 add_frag (adds (&opP->disp), offs (&opP->disp),
2287 TAB (PCINDEX, SZ_UNDEF));
2288
2289 break;
2290 }
2291 }
2292 }
2293 else
2294 {
2295 nextword |= 0x40; /* No index reg */
2296 if (opP->index.reg >= ZDATA0
2297 && opP->index.reg <= ZDATA7)
2298 nextword |= (opP->index.reg - ZDATA0) << 12;
2299 else if (opP->index.reg >= ZADDR0
2300 || opP->index.reg <= ZADDR7)
2301 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2302 }
2303
2304 /* It isn't simple. */
2305
2306 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2307 || arch_coldfire_p (current_architecture))
252b5132
RH		 2308 opP->error =
2309 _("invalid operand mode for this architecture; needs 68020 or higher");
2310
2311 nextword |= 0x100;
2312 /* If the guy specified a width, we assume that it is
2313 wide enough. Maybe it isn't. If so, we lose. */
2314 switch (siz1)
2315 {
2316 case SIZE_UNSPEC:
2317 if (isvar (&opP->disp)
2318 ? m68k_rel32
2319 : ! issword (baseo))
2320 {
2321 siz1 = SIZE_LONG;
2322 nextword |= 0x30;
2323 }
2324 else if (! isvar (&opP->disp) && baseo == 0)
2325 nextword |= 0x10;
2326 else
2327 {
2328 nextword |= 0x20;
2329 siz1 = SIZE_WORD;
2330 }
2331 break;
2332 case SIZE_BYTE:
2333 as_warn (_(":b not permitted; defaulting to :w"));
2334 /* Fall through. */
2335 case SIZE_WORD:
2336 nextword |= 0x20;
2337 break;
2338 case SIZE_LONG:
2339 nextword |= 0x30;
2340 break;
2341 }
2342
2343 /* Figure out innner displacement stuff */
2344 if (opP->mode == POST || opP->mode == PRE)
2345 {
2346 if (cpu_of_arch (current_architecture) & cpu32)
2347 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2348 switch (siz2)
2349 {
2350 case SIZE_UNSPEC:
2351 if (isvar (&opP->odisp)
2352 ? m68k_rel32
2353 : ! issword (outro))
2354 {
2355 siz2 = SIZE_LONG;
2356 nextword |= 0x3;
2357 }
2358 else if (! isvar (&opP->odisp) && outro == 0)
2359 nextword |= 0x1;
2360 else
2361 {
2362 nextword |= 0x2;
2363 siz2 = SIZE_WORD;
2364 }
2365 break;
2366 case 1:
2367 as_warn (_(":b not permitted; defaulting to :w"));
2368 /* Fall through. */
2369 case 2:
2370 nextword |= 0x2;
2371 break;
2372 case 3:
2373 nextword |= 0x3;
2374 break;
2375 }
2376 if (opP->mode == POST
2377 && (nextword & 0x40) == 0)
2378 nextword |= 0x04;
2379 }
2380 addword (nextword);
2381
2382 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2383 {
2384 if (opP->reg == PC || opP->reg == ZPC)
2385 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2386 else
2387 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2388 }
2389 if (siz1 == SIZE_LONG)
2390 addword (baseo >> 16);
2391 if (siz1 != SIZE_UNSPEC)
2392 addword (baseo);
2393
2394 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2395 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2396 if (siz2 == SIZE_LONG)
2397 addword (outro >> 16);
2398 if (siz2 != SIZE_UNSPEC)
2399 addword (outro);
2400
2401 break;
2402
2403 case ABSL:
2404 nextword = get_num (&opP->disp, 80);
2405 switch (opP->disp.size)
2406 {
2407 default:
2408 abort ();
2409 case SIZE_UNSPEC:
2410 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2411 {
2412 tmpreg = 0x38; /* 7.0 */
2413 addword (nextword);
2414 break;
2415 }
252b5132
RH		 2416 if (isvar (&opP->disp)
2417 && !subs (&opP->disp)
2418 && adds (&opP->disp)
2419#ifdef OBJ_ELF
2420 /* If the displacement needs pic relocation it
2421 cannot be relaxed. */
2422 && opP->disp.pic_reloc == pic_none
2423#endif
252b5132
RH		 2424 && !flag_long_jumps
2425 && !strchr ("~%&$?", s[0]))
2426 {
2427 tmpreg = 0x3A; /* 7.2 */
2428 add_frag (adds (&opP->disp),
2429 offs (&opP->disp),
151337e8 2430 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2431 break;
2432 }
2433 /* Fall through into long */
2434 case SIZE_LONG:
2435 if (isvar (&opP->disp))
2436 add_fix ('l', &opP->disp, 0, 0);
2437
2438 tmpreg = 0x39;/* 7.1 mode */
2439 addword (nextword >> 16);
2440 addword (nextword);
2441 break;
2442
2443 case SIZE_BYTE:
2444 as_bad (_("unsupported byte value; use a different suffix"));
2445 /* Fall through. */
2446 case SIZE_WORD: /* Word */
2447 if (isvar (&opP->disp))
2448 add_fix ('w', &opP->disp, 0, 0);
2449
2450 tmpreg = 0x38;/* 7.0 mode */
2451 addword (nextword);
2452 break;
2453 }
2454 break;
2455 case CONTROL:
2456 case FPREG:
2457 default:
2458 as_bad (_("unknown/incorrect operand"));
bc805888 2459 /* abort (); */
252b5132
RH		 2460 }
2461 install_gen_operand (s[1], tmpreg);
2462 break;
2463
2464 case '#':
2465 case '^':
2466 switch (s[1])
2467 { /* JF: I hate floating point! */
2468 case 'j':
2469 tmpreg = 70;
2470 break;
2471 case '8':
2472 tmpreg = 20;
2473 break;
2474 case 'C':
2475 tmpreg = 50;
2476 break;
2477 case '3':
2478 default:
2479 tmpreg = 80;
2480 break;
2481 }
2482 tmpreg = get_num (&opP->disp, tmpreg);
2483 if (isvar (&opP->disp))
2484 add_fix (s[1], &opP->disp, 0, 0);
2485 switch (s[1])
2486 {
2487 case 'b': /* Danger: These do no check for
2488 certain types of overflow.
2489 user beware! */
2490 if (!isbyte (tmpreg))
2491 opP->error = _("out of range");
2492 insop (tmpreg, opcode);
2493 if (isvar (&opP->disp))
2494 the_ins.reloc[the_ins.nrel - 1].n =
2495 (opcode->m_codenum) * 2 + 1;
2496 break;
2497 case 'B':
2498 if (!issbyte (tmpreg))
2499 opP->error = _("out of range");
2500 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2501 if (isvar (&opP->disp))
2502 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2503 break;
2504 case 'w':
2505 if (!isword (tmpreg))
2506 opP->error = _("out of range");
2507 insop (tmpreg, opcode);
2508 if (isvar (&opP->disp))
2509 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2510 break;
2511 case 'W':
2512 if (!issword (tmpreg))
2513 opP->error = _("out of range");
2514 insop (tmpreg, opcode);
2515 if (isvar (&opP->disp))
2516 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2517 break;
2518 case 'l':
2519 /* Because of the way insop works, we put these two out
2520 backwards. */
2521 insop (tmpreg, opcode);
2522 insop (tmpreg >> 16, opcode);
2523 if (isvar (&opP->disp))
2524 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2525 break;
2526 case '3':
2527 tmpreg &= 0xFF;
2528 case '8':
2529 case 'C':
2530 case 'j':
2531 install_operand (s[1], tmpreg);
2532 break;
2533 default:
2534 abort ();
2535 }
2536 break;
2537
2538 case '+':
2539 case '-':
2540 case 'A':
2541 case 'a':
2542 install_operand (s[1], opP->reg - ADDR);
2543 break;
2544
2545 case 'B':
2546 tmpreg = get_num (&opP->disp, 80);
2547 switch (s[1])
2548 {
2549 case 'B':
8390138c 2550 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 2551 break;
2552 case 'W':
2553 add_fix ('w', &opP->disp, 1, 0);
2554 addword (0);
2555 break;
2556 case 'L':
2557 long_branch:
151337e8 2558 if (! HAVE_LONG_BRANCH (current_architecture))
81d4177b 2559 as_warn (_("Can't use long branches on 68000/68010/5200"));
151337e8 2560 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2561 add_fix ('l', &opP->disp, 1, 0);
2562 addword (0);
2563 addword (0);
2564 break;
2565 case 'g':
2566 if (subs (&opP->disp)) /* We can't relax it */
2567 goto long_branch;
2568
2569#ifdef OBJ_ELF
2570 /* If the displacement needs pic relocation it cannot be
2571 relaxed. */
2572 if (opP->disp.pic_reloc != pic_none)
2573 goto long_branch;
2574#endif
252b5132 2575 /* This could either be a symbol, or an absolute
151337e8
NC		 2576 address. If it's an absolute address, turn it into
2577 an absolute jump right here and keep it out of the
2578 relaxer. */
2579 if (adds (&opP->disp) == 0)
2580 {
2581 if (the_ins.opcode[0] == 0x6000) /* jbra */
2582 the_ins.opcode[0] = 0x4EF1;
2583 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2584 the_ins.opcode[0] = 0x4EB1;
2585 else /* jCC */
2586 {
2587 the_ins.opcode[0] ^= 0x0100;
2588 the_ins.opcode[0] |= 0x0006;
2589 addword (0x4EF1);
2590 }
2591 add_fix ('l', &opP->disp, 0, 0);
2592 addword (0);
2593 addword (0);
2594 break;
2595 }
2596
2597 /* Now we know it's going into the relaxer. Now figure
2598 out which mode. We try in this order of preference:
2599 long branch, absolute jump, byte/word branches only. */
2600 if (HAVE_LONG_BRANCH (current_architecture))
252b5132 2601 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8
NC		 2602 TAB (BRANCHBWL, SZ_UNDEF));
2603 else if (! flag_keep_pcrel)
2604 {
2605 if ((the_ins.opcode[0] == 0x6000)
2606 || (the_ins.opcode[0] == 0x6100))
2607 add_frag (adds (&opP->disp), offs (&opP->disp),
2608 TAB (BRABSJUNC, SZ_UNDEF));
2609 else
2610 add_frag (adds (&opP->disp), offs (&opP->disp),
2611 TAB (BRABSJCOND, SZ_UNDEF));
2612 }
252b5132
RH		 2613 else
2614 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8 2615 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 2616 break;
2617 case 'w':
2618 if (isvar (&opP->disp))
2619 {
151337e8
NC		 2620 /* Check for DBcc instructions. We can relax them,
2621 but only if we have long branches and/or absolute
2622 jumps. */
2623 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2624 && (HAVE_LONG_BRANCH (current_architecture)
2625 || (! flag_keep_pcrel)))
252b5132 2626 {
151337e8
NC		 2627 if (HAVE_LONG_BRANCH (current_architecture))
2628 add_frag (adds (&opP->disp), offs (&opP->disp),
2629 TAB (DBCCLBR, SZ_UNDEF));
2630 else
2631 add_frag (adds (&opP->disp), offs (&opP->disp),
2632 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 2633 break;
2634 }
252b5132
RH		 2635 add_fix ('w', &opP->disp, 1, 0);
2636 }
2637 addword (0);
2638 break;
2639 case 'C': /* Fixed size LONG coproc branches */
2640 add_fix ('l', &opP->disp, 1, 0);
2641 addword (0);
2642 addword (0);
2643 break;
2644 case 'c': /* Var size Coprocesssor branches */
151337e8 2645 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 2646 {
252b5132
RH		 2647 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2648 add_fix ('l', &opP->disp, 1, 0);
2649 addword (0);
2650 addword (0);
2651 }
151337e8
NC		 2652 else
2653 add_frag (adds (&opP->disp), offs (&opP->disp),
2654 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 2655 break;
2656 default:
2657 abort ();
2658 }
2659 break;
2660
2661 case 'C': /* Ignore it */
2662 break;
2663
2664 case 'd': /* JF this is a kludge */
2665 install_operand ('s', opP->reg - ADDR);
2666 tmpreg = get_num (&opP->disp, 80);
2667 if (!issword (tmpreg))
2668 {
2669 as_warn (_("Expression out of range, using 0"));
2670 tmpreg = 0;
2671 }
2672 addword (tmpreg);
2673 break;
2674
2675 case 'D':
2676 install_operand (s[1], opP->reg - DATA);
2677 break;
2678
6da466c7
ILT		 2679 case 'E': /* Ignore it */
2680 break;
2681
252b5132
RH		 2682 case 'F':
2683 install_operand (s[1], opP->reg - FP0);
2684 break;
2685
6da466c7
ILT		 2686 case 'G': /* Ignore it */
2687 case 'H':
2688 break;
2689
252b5132
RH		 2690 case 'I':
2691 tmpreg = opP->reg - COP0;
2692 install_operand (s[1], tmpreg);
2693 break;
2694
2695 case 'J': /* JF foo */
2696 switch (opP->reg)
2697 {
2698 case SFC:
2699 tmpreg = 0x000;
2700 break;
2701 case DFC:
2702 tmpreg = 0x001;
2703 break;
2704 case CACR:
2705 tmpreg = 0x002;
2706 break;
2707 case TC:
2708 tmpreg = 0x003;
2709 break;
2710 case ITT0:
2711 tmpreg = 0x004;
2712 break;
2713 case ITT1:
2714 tmpreg = 0x005;
2715 break;
2716 case DTT0:
2717 tmpreg = 0x006;
2718 break;
2719 case DTT1:
2720 tmpreg = 0x007;
2721 break;
2722 case BUSCR:
2723 tmpreg = 0x008;
2724 break;
2725
2726 case USP:
2727 tmpreg = 0x800;
2728 break;
2729 case VBR:
2730 tmpreg = 0x801;
2731 break;
2732 case CAAR:
2733 tmpreg = 0x802;
2734 break;
2735 case MSP:
2736 tmpreg = 0x803;
2737 break;
2738 case ISP:
2739 tmpreg = 0x804;
2740 break;
2741 case MMUSR:
2742 tmpreg = 0x805;
2743 break;
2744 case URP:
2745 tmpreg = 0x806;
2746 break;
2747 case SRP:
2748 tmpreg = 0x807;
2749 break;
2750 case PCR:
2751 tmpreg = 0x808;
2752 break;
2753 case ROMBAR:
2754 tmpreg = 0xC00;
2755 break;
2756 case RAMBAR0:
2757 tmpreg = 0xC04;
2758 break;
2759 case RAMBAR1:
2760 tmpreg = 0xC05;
2761 break;
2762 case MBAR:
2763 tmpreg = 0xC0F;
2764 break;
2765 default:
2766 abort ();
2767 }
2768 install_operand (s[1], tmpreg);
2769 break;
2770
2771 case 'k':
2772 tmpreg = get_num (&opP->disp, 55);
2773 install_operand (s[1], tmpreg & 0x7f);
2774 break;
2775
2776 case 'l':
2777 tmpreg = opP->mask;
2778 if (s[1] == 'w')
2779 {
2780 if (tmpreg & 0x7FF0000)
2781 as_bad (_("Floating point register in register list"));
2782 insop (reverse_16_bits (tmpreg), opcode);
2783 }
2784 else
2785 {
2786 if (tmpreg & 0x700FFFF)
2787 as_bad (_("Wrong register in floating-point reglist"));
2788 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2789 }
2790 break;
2791
2792 case 'L':
2793 tmpreg = opP->mask;
2794 if (s[1] == 'w')
2795 {
2796 if (tmpreg & 0x7FF0000)
2797 as_bad (_("Floating point register in register list"));
2798 insop (tmpreg, opcode);
2799 }
2800 else if (s[1] == '8')
2801 {
2802 if (tmpreg & 0x0FFFFFF)
2803 as_bad (_("incorrect register in reglist"));
2804 install_operand (s[1], tmpreg >> 24);
2805 }
2806 else
2807 {
2808 if (tmpreg & 0x700FFFF)
2809 as_bad (_("wrong register in floating-point reglist"));
2810 else
2811 install_operand (s[1], tmpreg >> 16);
2812 }
2813 break;
2814
2815 case 'M':
2816 install_operand (s[1], get_num (&opP->disp, 60));
2817 break;
2818
2819 case 'O':
2820 tmpreg = ((opP->mode == DREG)
8fce3f5e 2821 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 2822 : (get_num (&opP->disp, 40) & 0x1F));
2823 install_operand (s[1], tmpreg);
2824 break;
2825
2826 case 'Q':
2827 tmpreg = get_num (&opP->disp, 10);
2828 if (tmpreg == 8)
2829 tmpreg = 0;
2830 install_operand (s[1], tmpreg);
2831 break;
2832
2833 case 'R':
2834 /* This depends on the fact that ADDR registers are eight
2835 more than their corresponding DATA regs, so the result
2836 will have the ADDR_REG bit set */
2837 install_operand (s[1], opP->reg - DATA);
2838 break;
2839
2840 case 'r':
2841 if (opP->mode == AINDR)
2842 install_operand (s[1], opP->reg - DATA);
2843 else
2844 install_operand (s[1], opP->index.reg - DATA);
2845 break;
2846
2847 case 's':
2848 if (opP->reg == FPI)
2849 tmpreg = 0x1;
2850 else if (opP->reg == FPS)
2851 tmpreg = 0x2;
2852 else if (opP->reg == FPC)
2853 tmpreg = 0x4;
2854 else
2855 abort ();
2856 install_operand (s[1], tmpreg);
2857 break;
2858
2859 case 'S': /* Ignore it */
2860 break;
2861
2862 case 'T':
2863 install_operand (s[1], get_num (&opP->disp, 30));
2864 break;
2865
2866 case 'U': /* Ignore it */
2867 break;
2868
2869 case 'c':
2870 switch (opP->reg)
2871 {
2872 case NC:
2873 tmpreg = 0;
2874 break;
2875 case DC:
2876 tmpreg = 1;
2877 break;
2878 case IC:
2879 tmpreg = 2;
2880 break;
2881 case BC:
2882 tmpreg = 3;
2883 break;
2884 default:
2885 as_fatal (_("failed sanity check"));
2886 } /* switch on cache token */
2887 install_operand (s[1], tmpreg);
2888 break;
2889#ifndef NO_68851
92774660 2890 /* JF: These are out of order, I fear. */
252b5132
RH		 2891 case 'f':
2892 switch (opP->reg)
2893 {
2894 case SFC:
2895 tmpreg = 0;
2896 break;
2897 case DFC:
2898 tmpreg = 1;
2899 break;
2900 default:
2901 abort ();
2902 }
2903 install_operand (s[1], tmpreg);
2904 break;
2905
2906 case '0':
2907 case '1':
2908 case '2':
2909 switch (opP->reg)
2910 {
2911 case TC:
2912 tmpreg = 0;
2913 break;
2914 case CAL:
2915 tmpreg = 4;
2916 break;
2917 case VAL:
2918 tmpreg = 5;
2919 break;
2920 case SCC:
2921 tmpreg = 6;
2922 break;
2923 case AC:
2924 tmpreg = 7;
2925 break;
2926 default:
2927 abort ();
2928 }
2929 install_operand (s[1], tmpreg);
2930 break;
2931
2932 case 'V':
2933 if (opP->reg == VAL)
2934 break;
2935 abort ();
2936
2937 case 'W':
2938 switch (opP->reg)
2939 {
2940 case DRP:
2941 tmpreg = 1;
2942 break;
2943 case SRP:
2944 tmpreg = 2;
2945 break;
2946 case CRP:
2947 tmpreg = 3;
2948 break;
2949 default:
2950 abort ();
2951 }
2952 install_operand (s[1], tmpreg);
2953 break;
2954
2955 case 'X':
2956 switch (opP->reg)
2957 {
2958 case BAD:
2959 case BAD + 1:
2960 case BAD + 2:
2961 case BAD + 3:
2962 case BAD + 4:
2963 case BAD + 5:
2964 case BAD + 6:
2965 case BAD + 7:
2966 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2967 break;
2968
2969 case BAC:
2970 case BAC + 1:
2971 case BAC + 2:
2972 case BAC + 3:
2973 case BAC + 4:
2974 case BAC + 5:
2975 case BAC + 6:
2976 case BAC + 7:
2977 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2978 break;
2979
2980 default:
2981 abort ();
2982 }
2983 install_operand (s[1], tmpreg);
2984 break;
2985 case 'Y':
2986 know (opP->reg == PSR);
2987 break;
2988 case 'Z':
2989 know (opP->reg == PCSR);
2990 break;
2991#endif /* m68851 */
2992 case '3':
2993 switch (opP->reg)
2994 {
2995 case TT0:
2996 tmpreg = 2;
2997 break;
2998 case TT1:
2999 tmpreg = 3;
3000 break;
3001 default:
3002 abort ();
3003 }
3004 install_operand (s[1], tmpreg);
3005 break;
3006 case 't':
3007 tmpreg = get_num (&opP->disp, 20);
3008 install_operand (s[1], tmpreg);
3009 break;
3010 case '_': /* used only for move16 absolute 32-bit address */
3011 if (isvar (&opP->disp))
3012 add_fix ('l', &opP->disp, 0, 0);
3013 tmpreg = get_num (&opP->disp, 80);
3014 addword (tmpreg >> 16);
3015 addword (tmpreg & 0xFFFF);
3016 break;
6da466c7
ILT		 3017 case 'u':
3018 install_operand (s[1], opP->reg - DATA0L);
3019 opP->reg -= (DATA0L);
3020 opP->reg &= 0x0F; /* remove upper/lower bit */
3021 break;
252b5132
RH		 3022 default:
3023 abort ();
3024 }
3025 }
3026
3027 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3028 instruction, ready to be emitted. . . */
252b5132
RH		 3029}
3030
3031static int
3032reverse_16_bits (in)
3033 int in;
3034{
3035 int out = 0;
3036 int n;
3037
3038 static int mask[16] =
3039 {
3040 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3041 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3042 };
3043 for (n = 0; n < 16; n++)
3044 {
3045 if (in & mask[n])
3046 out |= mask[15 - n];
3047 }
3048 return out;
3049} /* reverse_16_bits() */
3050
3051static int
3052reverse_8_bits (in)
3053 int in;
3054{
3055 int out = 0;
3056 int n;
3057
3058 static int mask[8] =
3059 {
3060 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3061 };
3062
3063 for (n = 0; n < 8; n++)
3064 {
3065 if (in & mask[n])
3066 out |= mask[7 - n];
3067 }
3068 return out;
3069} /* reverse_8_bits() */
3070
3071/* Cause an extra frag to be generated here, inserting up to 10 bytes
3072 (that value is chosen in the frag_var call in md_assemble). TYPE
3073 is the subtype of the frag to be generated; its primary type is
3074 rs_machine_dependent.
3075
3076 The TYPE parameter is also used by md_convert_frag_1 and
3077 md_estimate_size_before_relax. The appropriate type of fixup will
3078 be emitted by md_convert_frag_1.
3079
3080 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3081static void
3082install_operand (mode, val)
3083 int mode;
3084 int val;
3085{
3086 switch (mode)
3087 {
3088 case 's':
3089 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3090 break;
3091 case 'd':
3092 the_ins.opcode[0] |= val << 9;
3093 break;
3094 case '1':
3095 the_ins.opcode[1] |= val << 12;
3096 break;
3097 case '2':
3098 the_ins.opcode[1] |= val << 6;
3099 break;
3100 case '3':
3101 the_ins.opcode[1] |= val;
3102 break;
3103 case '4':
3104 the_ins.opcode[2] |= val << 12;
3105 break;
3106 case '5':
3107 the_ins.opcode[2] |= val << 6;
3108 break;
3109 case '6':
3110 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3111 three words long! */
3112 the_ins.numo++;
3113 the_ins.opcode[2] |= val;
3114 break;
3115 case '7':
3116 the_ins.opcode[1] |= val << 7;
3117 break;
3118 case '8':
3119 the_ins.opcode[1] |= val << 10;
3120 break;
3121#ifndef NO_68851
3122 case '9':
3123 the_ins.opcode[1] |= val << 5;
3124 break;
3125#endif
3126
3127 case 't':
3128 the_ins.opcode[1] |= (val << 10) | (val << 7);
3129 break;
3130 case 'D':
3131 the_ins.opcode[1] |= (val << 12) | val;
3132 break;
3133 case 'g':
3134 the_ins.opcode[0] |= val = 0xff;
3135 break;
3136 case 'i':
3137 the_ins.opcode[0] |= val << 9;
3138 break;
3139 case 'C':
3140 the_ins.opcode[1] |= val;
3141 break;
3142 case 'j':
3143 the_ins.opcode[1] |= val;
3144 the_ins.numo++; /* What a hack */
3145 break;
3146 case 'k':
3147 the_ins.opcode[1] |= val << 4;
3148 break;
3149 case 'b':
3150 case 'w':
3151 case 'W':
3152 case 'l':
3153 break;
3154 case 'e':
3155 the_ins.opcode[0] |= (val << 6);
3156 break;
3157 case 'L':
3158 the_ins.opcode[1] = (val >> 16);
3159 the_ins.opcode[2] = val & 0xffff;
3160 break;
6da466c7
ILT		 3161 case 'm':
3162 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3163 the_ins.opcode[0] |= ((val & 0x7) << 9);
3164 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3165 break;
3166 case 'n':
3167 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3168 the_ins.opcode[0] |= ((val & 0x7) << 9);
3169 break;
3170 case 'o':
3171 the_ins.opcode[1] |= val << 12;
3172 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3173 break;
3174 case 'M':
3175 the_ins.opcode[0] |= (val & 0xF);
3176 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3177 break;
3178 case 'N':
3179 the_ins.opcode[1] |= (val & 0xF);
3180 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3181 break;
3182 case 'h':
3183 the_ins.opcode[1] |= ((val != 1) << 10);
3184 break;
252b5132
RH		 3185 case 'c':
3186 default:
3187 as_fatal (_("failed sanity check."));
3188 }
3189} /* install_operand() */
3190
3191static void
3192install_gen_operand (mode, val)
3193 int mode;
3194 int val;
3195{
3196 switch (mode)
3197 {
3198 case 's':
3199 the_ins.opcode[0] |= val;
3200 break;
3201 case 'd':
3202 /* This is a kludge!!! */
3203 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3204 break;
3205 case 'b':
3206 case 'w':
3207 case 'l':
3208 case 'f':
3209 case 'F':
3210 case 'x':
3211 case 'p':
3212 the_ins.opcode[0] |= val;
3213 break;
3214 /* more stuff goes here */
3215 default:
3216 as_fatal (_("failed sanity check."));
3217 }
3218} /* install_gen_operand() */
3219
3220/*
3221 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3222 * then deal with the bitfield hack.
3223 */
3224
3225static char *
3226crack_operand (str, opP)
3227 register char *str;
3228 register struct m68k_op *opP;
3229{
3230 register int parens;
3231 register int c;
3232 register char *beg_str;
3233 int inquote = 0;
3234
3235 if (!str)
3236 {
3237 return str;
3238 }
3239 beg_str = str;
3240 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3241 {
3242 if (! inquote)
3243 {
3244 if (*str == '(')
3245 parens++;
3246 else if (*str == ')')
3247 {
3248 if (!parens)
3249 { /* ERROR */
3250 opP->error = _("Extra )");
3251 return str;
3252 }
3253 --parens;
3254 }
3255 }
3256 if (flag_mri && *str == '\'')
3257 inquote = ! inquote;
3258 }
3259 if (!*str && parens)
3260 { /* ERROR */
3261 opP->error = _("Missing )");
3262 return str;
3263 }
3264 c = *str;
3265 *str = '\0';
3266 if (m68k_ip_op (beg_str, opP) != 0)
3267 {
3268 *str = c;
3269 return str;
3270 }
3271 *str = c;
3272 if (c == '}')
3273 c = *++str; /* JF bitfield hack */
3274 if (c)
3275 {
3276 c = *++str;
3277 if (!c)
3278 as_bad (_("Missing operand"));
3279 }
3280
3281 /* Detect MRI REG symbols and convert them to REGLSTs. */
3282 if (opP->mode == CONTROL && (int)opP->reg < 0)
3283 {
3284 opP->mode = REGLST;
3285 opP->mask = ~(int)opP->reg;
3286 opP->reg = 0;
3287 }
3288
3289 return str;
3290}
3291
3292/* This is the guts of the machine-dependent assembler. STR points to a
3293 machine dependent instruction. This function is supposed to emit
3294 the frags/bytes it assembles to.
3295 */
3296
3297static void
3298insert_reg (regname, regnum)
3299 const char *regname;
3300 int regnum;
3301{
3302 char buf[100];
3303 int i;
3304
3305#ifdef REGISTER_PREFIX
3306 if (!flag_reg_prefix_optional)
3307 {
3308 buf[0] = REGISTER_PREFIX;
3309 strcpy (buf + 1, regname);
3310 regname = buf;
3311 }
3312#endif
3313
3314 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3315 &zero_address_frag));
3316
3317 for (i = 0; regname[i]; i++)
3318 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3319 buf[i] = '\0';
3320
3321 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3322 &zero_address_frag));
3323}
3324
3325struct init_entry
3326 {
3327 const char *name;
3328 int number;
3329 };
3330
3331static const struct init_entry init_table[] =
3332{
3333 { "d0", DATA0 },
3334 { "d1", DATA1 },
3335 { "d2", DATA2 },
3336 { "d3", DATA3 },
3337 { "d4", DATA4 },
3338 { "d5", DATA5 },
3339 { "d6", DATA6 },
3340 { "d7", DATA7 },
3341 { "a0", ADDR0 },
3342 { "a1", ADDR1 },
3343 { "a2", ADDR2 },
3344 { "a3", ADDR3 },
3345 { "a4", ADDR4 },
3346 { "a5", ADDR5 },
3347 { "a6", ADDR6 },
3348 { "fp", ADDR6 },
3349 { "a7", ADDR7 },
3350 { "sp", ADDR7 },
3351 { "ssp", ADDR7 },
3352 { "fp0", FP0 },
3353 { "fp1", FP1 },
3354 { "fp2", FP2 },
3355 { "fp3", FP3 },
3356 { "fp4", FP4 },
3357 { "fp5", FP5 },
3358 { "fp6", FP6 },
3359 { "fp7", FP7 },
3360 { "fpi", FPI },
3361 { "fpiar", FPI },
3362 { "fpc", FPI },
3363 { "fps", FPS },
3364 { "fpsr", FPS },
3365 { "fpc", FPC },
3366 { "fpcr", FPC },
3367 { "control", FPC },
3368 { "status", FPS },
3369 { "iaddr", FPI },
3370
3371 { "cop0", COP0 },
3372 { "cop1", COP1 },
3373 { "cop2", COP2 },
3374 { "cop3", COP3 },
3375 { "cop4", COP4 },
3376 { "cop5", COP5 },
3377 { "cop6", COP6 },
3378 { "cop7", COP7 },
3379 { "pc", PC },
3380 { "zpc", ZPC },
3381 { "sr", SR },
3382
3383 { "ccr", CCR },
3384 { "cc", CCR },
3385
6da466c7
ILT		 3386 { "acc", ACC },
3387 { "macsr", MACSR },
3388 { "mask", MASK },
3389
252b5132
RH		 3390 /* control registers */
3391 { "sfc", SFC }, /* Source Function Code */
3392 { "sfcr", SFC },
3393 { "dfc", DFC }, /* Destination Function Code */
3394 { "dfcr", DFC },
3395 { "cacr", CACR }, /* Cache Control Register */
3396 { "caar", CAAR }, /* Cache Address Register */
3397
3398 { "usp", USP }, /* User Stack Pointer */
3399 { "vbr", VBR }, /* Vector Base Register */
3400 { "msp", MSP }, /* Master Stack Pointer */
3401 { "isp", ISP }, /* Interrupt Stack Pointer */
3402
3403 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3404 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3405 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3406 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3407
3408 /* 68ec040 versions of same */
3409 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3410 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3411 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3412 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3413
3414 /* mcf5200 versions of same. The ColdFire programmer's reference
3415 manual indicated that the order is 2,3,0,1, but Ken Rose
3416 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3417 { "acr0", ITT0 }, /* Access Control Unit 0 */
3418 { "acr1", ITT1 }, /* Access Control Unit 1 */
3419 { "acr2", DTT0 }, /* Access Control Unit 2 */
3420 { "acr3", DTT1 }, /* Access Control Unit 3 */
3421
3422 { "tc", TC }, /* MMU Translation Control Register */
3423 { "tcr", TC },
3424
3425 { "mmusr", MMUSR }, /* MMU Status Register */
3426 { "srp", SRP }, /* User Root Pointer */
3427 { "urp", URP }, /* Supervisor Root Pointer */
3428
3429 { "buscr", BUSCR },
3430 { "pcr", PCR },
3431
3432 { "rombar", ROMBAR }, /* ROM Base Address Register */
3433 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3434 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3435 { "mbar", MBAR }, /* Module Base Address Register */
3436 /* end of control registers */
3437
3438 { "ac", AC },
3439 { "bc", BC },
3440 { "cal", CAL },
3441 { "crp", CRP },
3442 { "drp", DRP },
3443 { "pcsr", PCSR },
3444 { "psr", PSR },
3445 { "scc", SCC },
3446 { "val", VAL },
3447 { "bad0", BAD0 },
3448 { "bad1", BAD1 },
3449 { "bad2", BAD2 },
3450 { "bad3", BAD3 },
3451 { "bad4", BAD4 },
3452 { "bad5", BAD5 },
3453 { "bad6", BAD6 },
3454 { "bad7", BAD7 },
3455 { "bac0", BAC0 },
3456 { "bac1", BAC1 },
3457 { "bac2", BAC2 },
3458 { "bac3", BAC3 },
3459 { "bac4", BAC4 },
3460 { "bac5", BAC5 },
3461 { "bac6", BAC6 },
3462 { "bac7", BAC7 },
3463
3464 { "ic", IC },
3465 { "dc", DC },
3466 { "nc", NC },
3467
3468 { "tt0", TT0 },
3469 { "tt1", TT1 },
3470 /* 68ec030 versions of same */
3471 { "ac0", TT0 },
3472 { "ac1", TT1 },
3473 /* 68ec030 access control unit, identical to 030 MMU status reg */
3474 { "acusr", PSR },
3475
3476 /* Suppressed data and address registers. */
3477 { "zd0", ZDATA0 },
3478 { "zd1", ZDATA1 },
3479 { "zd2", ZDATA2 },
3480 { "zd3", ZDATA3 },
3481 { "zd4", ZDATA4 },
3482 { "zd5", ZDATA5 },
3483 { "zd6", ZDATA6 },
3484 { "zd7", ZDATA7 },
3485 { "za0", ZADDR0 },
3486 { "za1", ZADDR1 },
3487 { "za2", ZADDR2 },
3488 { "za3", ZADDR3 },
3489 { "za4", ZADDR4 },
3490 { "za5", ZADDR5 },
3491 { "za6", ZADDR6 },
3492 { "za7", ZADDR7 },
3493
92774660 3494 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 3495 { "d0l", DATA0L },
3496 { "d1l", DATA1L },
3497 { "d2l", DATA2L },
3498 { "d3l", DATA3L },
3499 { "d4l", DATA4L },
3500 { "d5l", DATA5L },
3501 { "d6l", DATA6L },
3502 { "d7l", DATA7L },
3503
3504 { "a0l", ADDR0L },
3505 { "a1l", ADDR1L },
3506 { "a2l", ADDR2L },
3507 { "a3l", ADDR3L },
3508 { "a4l", ADDR4L },
3509 { "a5l", ADDR5L },
3510 { "a6l", ADDR6L },
3511 { "a7l", ADDR7L },
3512
3513 { "d0u", DATA0U },
3514 { "d1u", DATA1U },
3515 { "d2u", DATA2U },
3516 { "d3u", DATA3U },
3517 { "d4u", DATA4U },
3518 { "d5u", DATA5U },
3519 { "d6u", DATA6U },
3520 { "d7u", DATA7U },
3521
3522 { "a0u", ADDR0U },
3523 { "a1u", ADDR1U },
3524 { "a2u", ADDR2U },
3525 { "a3u", ADDR3U },
3526 { "a4u", ADDR4U },
3527 { "a5u", ADDR5U },
3528 { "a6u", ADDR6U },
3529 { "a7u", ADDR7U },
3530
252b5132
RH		 3531 { 0, 0 }
3532};
3533
3534static void
3535init_regtable ()
3536{
3537 int i;
3538 for (i = 0; init_table[i].name; i++)
3539 insert_reg (init_table[i].name, init_table[i].number);
3540}
3541
3542static int no_68851, no_68881;
3543
3544#ifdef OBJ_AOUT
3545/* a.out machine type. Default to 68020. */
3546int m68k_aout_machtype = 2;
3547#endif
3548
3549void
3550md_assemble (str)
3551 char *str;
3552{
3553 const char *er;
3554 short *fromP;
3555 char *toP = NULL;
3556 int m, n = 0;
3557 char *to_beg_P;
3558 int shorts_this_frag;
3559 fixS *fixP;
3560
3561 /* In MRI mode, the instruction and operands are separated by a
3562 space. Anything following the operands is a comment. The label
3563 has already been removed. */
3564 if (flag_mri)
3565 {
3566 char *s;
3567 int fields = 0;
3568 int infield = 0;
3569 int inquote = 0;
3570
3571 for (s = str; *s != '\0'; s++)
3572 {
3573 if ((*s == ' ' || *s == '\t') && ! inquote)
3574 {
3575 if (infield)
3576 {
3577 ++fields;
3578 if (fields >= 2)
3579 {
3580 *s = '\0';
3581 break;
3582 }
3583 infield = 0;
3584 }
3585 }
3586 else
3587 {
3588 if (! infield)
3589 infield = 1;
3590 if (*s == '\'')
3591 inquote = ! inquote;
3592 }
3593 }
3594 }
3595
3596 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3597 m68k_ip (str);
3598 er = the_ins.error;
3599 if (!er)
3600 {
3601 for (n = 0; n < the_ins.numargs; n++)
3602 if (the_ins.operands[n].error)
3603 {
3604 er = the_ins.operands[n].error;
3605 break;
3606 }
3607 }
3608 if (er)
3609 {
3610 as_bad (_("%s -- statement `%s' ignored"), er, str);
3611 return;
3612 }
3613
3614 /* If there is a current label, record that it marks an instruction. */
3615 if (current_label != NULL)
3616 {
3617 current_label->text = 1;
3618 current_label = NULL;
3619 }
3620
3621 if (the_ins.nfrag == 0)
3622 {
3623 /* No frag hacking involved; just put it out */
3624 toP = frag_more (2 * the_ins.numo);
3625 fromP = &the_ins.opcode[0];
3626 for (m = the_ins.numo; m; --m)
3627 {
3628 md_number_to_chars (toP, (long) (*fromP), 2);
3629 toP += 2;
3630 fromP++;
3631 }
3632 /* put out symbol-dependent info */
3633 for (m = 0; m < the_ins.nrel; m++)
3634 {
3635 switch (the_ins.reloc[m].wid)
3636 {
3637 case 'B':
3638 n = 1;
3639 break;
3640 case 'b':
3641 n = 1;
3642 break;
3643 case '3':
3644 n = 1;
3645 break;
3646 case 'w':
3647 case 'W':
3648 n = 2;
3649 break;
3650 case 'l':
3651 n = 4;
3652 break;
3653 default:
3654 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3655 the_ins.reloc[m].wid);
3656 }
3657
3658 fixP = fix_new_exp (frag_now,
3659 ((toP - frag_now->fr_literal)
3660 - the_ins.numo * 2 + the_ins.reloc[m].n),
3661 n,
3662 &the_ins.reloc[m].exp,
3663 the_ins.reloc[m].pcrel,
3664 get_reloc_code (n, the_ins.reloc[m].pcrel,
3665 the_ins.reloc[m].pic_reloc));
3666 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3667 if (the_ins.reloc[m].wid == 'B')
3668 fixP->fx_signed = 1;
3669 }
3670 return;
3671 }
3672
3673 /* There's some frag hacking */
3674 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3675 {
3676 int wid;
3677
3678 if (n == 0)
3679 wid = 2 * the_ins.fragb[n].fragoff;
3680 else
3681 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3682 toP = frag_more (wid);
3683 to_beg_P = toP;
3684 shorts_this_frag = 0;
3685 for (m = wid / 2; m; --m)
3686 {
3687 md_number_to_chars (toP, (long) (*fromP), 2);
3688 toP += 2;
3689 fromP++;
3690 shorts_this_frag++;
3691 }
3692 for (m = 0; m < the_ins.nrel; m++)
3693 {
3694 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3695 {
3696 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3697 break;
3698 }
3699 wid = the_ins.reloc[m].wid;
3700 if (wid == 0)
3701 continue;
3702 the_ins.reloc[m].wid = 0;
3703 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3704
3705 fixP = fix_new_exp (frag_now,
3706 ((toP - frag_now->fr_literal)
3707 - the_ins.numo * 2 + the_ins.reloc[m].n),
3708 wid,
3709 &the_ins.reloc[m].exp,
3710 the_ins.reloc[m].pcrel,
3711 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3712 the_ins.reloc[m].pic_reloc));
3713 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3714 }
3715 (void) frag_var (rs_machine_dependent, 10, 0,
3716 (relax_substateT) (the_ins.fragb[n].fragty),
3717 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3718 }
3719 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3720 shorts_this_frag = 0;
3721 if (n)
3722 {
3723 toP = frag_more (n * sizeof (short));
3724 while (n--)
3725 {
3726 md_number_to_chars (toP, (long) (*fromP), 2);
3727 toP += 2;
3728 fromP++;
3729 shorts_this_frag++;
3730 }
3731 }
3732 for (m = 0; m < the_ins.nrel; m++)
3733 {
3734 int wid;
3735
3736 wid = the_ins.reloc[m].wid;
3737 if (wid == 0)
3738 continue;
3739 the_ins.reloc[m].wid = 0;
3740 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3741
3742 fixP = fix_new_exp (frag_now,
3743 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3744 - shorts_this_frag * 2),
3745 wid,
3746 &the_ins.reloc[m].exp,
3747 the_ins.reloc[m].pcrel,
3748 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3749 the_ins.reloc[m].pic_reloc));
3750 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3751 }
3752}
3753
3754void
3755md_begin ()
3756{
3757 /*
3758 * md_begin -- set up hash tables with 68000 instructions.
3759 * similar to what the vax assembler does. ---phr
3760 */
3761 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3762 a copy of it at runtime, adding in the information we want but isn't
3763 there. I think it'd be better to have an awk script hack the table
3764 at compile time. Or even just xstr the table and use it as-is. But
3765 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3766 names. */
3767
3768 register const struct m68k_opcode *ins;
3769 register struct m68k_incant *hack, *slak;
3770 register const char *retval = 0; /* empty string, or error msg text */
8fce3f5e 3771 register int i;
252b5132
RH		 3772 register char c;
3773
3774 if (flag_mri)
3775 {
3776 flag_reg_prefix_optional = 1;
3777 m68k_abspcadd = 1;
3778 if (! m68k_rel32_from_cmdline)
3779 m68k_rel32 = 0;
3780 }
3781
3782 op_hash = hash_new ();
3783
3784 obstack_begin (&robyn, 4000);
3785 for (i = 0; i < m68k_numopcodes; i++)
3786 {
3787 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3788 do
3789 {
3790 ins = &m68k_opcodes[i];
3791 /* We *could* ignore insns that don't match our arch here
92774660 3792 but just leaving them out of the hash. */
252b5132
RH		 3793 slak->m_operands = ins->args;
3794 slak->m_opnum = strlen (slak->m_operands) / 2;
3795 slak->m_arch = ins->arch;
3796 slak->m_opcode = ins->opcode;
3797 /* This is kludgey */
3798 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3799 if (i + 1 != m68k_numopcodes
3800 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3801 {
3802 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3803 i++;
3804 }
3805 else
3806 slak->m_next = 0;
3807 slak = slak->m_next;
3808 }
3809 while (slak);
3810
3811 retval = hash_insert (op_hash, ins->name, (char *) hack);
3812 if (retval)
3813 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3814 }
3815
3816 for (i = 0; i < m68k_numaliases; i++)
3817 {
3818 const char *name = m68k_opcode_aliases[i].primary;
3819 const char *alias = m68k_opcode_aliases[i].alias;
3820 PTR val = hash_find (op_hash, name);
3821 if (!val)
3822 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3823 retval = hash_insert (op_hash, alias, val);
3824 if (retval)
3825 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3826 }
3827
3828 /* In MRI mode, all unsized branches are variable sized. Normally,
3829 they are word sized. */
3830 if (flag_mri)
3831 {
3832 static struct m68k_opcode_alias mri_aliases[] =
3833 {
3834 { "bhi", "jhi", },
3835 { "bls", "jls", },
3836 { "bcc", "jcc", },
3837 { "bcs", "jcs", },
3838 { "bne", "jne", },
3839 { "beq", "jeq", },
3840 { "bvc", "jvc", },
3841 { "bvs", "jvs", },
3842 { "bpl", "jpl", },
3843 { "bmi", "jmi", },
3844 { "bge", "jge", },
3845 { "blt", "jlt", },
3846 { "bgt", "jgt", },
3847 { "ble", "jle", },
3848 { "bra", "jra", },
3849 { "bsr", "jbsr", },
3850 };
3851
8fce3f5e
AM		 3852 for (i = 0;
3853 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
3854 i++)
252b5132
RH		 3855 {
3856 const char *name = mri_aliases[i].primary;
3857 const char *alias = mri_aliases[i].alias;
3858 PTR val = hash_find (op_hash, name);
3859 if (!val)
3860 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3861 retval = hash_jam (op_hash, alias, val);
3862 if (retval)
3863 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3864 }
3865 }
3866
8fce3f5e 3867 for (i = 0; i < (int) sizeof (mklower_table); i++)
252b5132
RH		 3868 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3869
8fce3f5e 3870 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 3871 {
3872 notend_table[i] = 0;
3873 alt_notend_table[i] = 0;
3874 }
3875 notend_table[','] = 1;
3876 notend_table['{'] = 1;
3877 notend_table['}'] = 1;
3878 alt_notend_table['a'] = 1;
3879 alt_notend_table['A'] = 1;
3880 alt_notend_table['d'] = 1;
3881 alt_notend_table['D'] = 1;
3882 alt_notend_table['#'] = 1;
3883 alt_notend_table['&'] = 1;
3884 alt_notend_table['f'] = 1;
3885 alt_notend_table['F'] = 1;
3886#ifdef REGISTER_PREFIX
3887 alt_notend_table[REGISTER_PREFIX] = 1;
3888#endif
3889
3890 /* We need to put '(' in alt_notend_table to handle
3891 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3892 */
3893 alt_notend_table['('] = 1;
3894
3895 /* We need to put '@' in alt_notend_table to handle
3896 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3897 */
3898 alt_notend_table['@'] = 1;
3899
3900 /* We need to put digits in alt_notend_table to handle
3901 bfextu %d0{24:1},%d0
3902 */
3903 alt_notend_table['0'] = 1;
3904 alt_notend_table['1'] = 1;
3905 alt_notend_table['2'] = 1;
3906 alt_notend_table['3'] = 1;
3907 alt_notend_table['4'] = 1;
3908 alt_notend_table['5'] = 1;
3909 alt_notend_table['6'] = 1;
3910 alt_notend_table['7'] = 1;
3911 alt_notend_table['8'] = 1;
3912 alt_notend_table['9'] = 1;
3913
3914#ifndef MIT_SYNTAX_ONLY
3915 /* Insert pseudo ops, these have to go into the opcode table since
3916 gas expects pseudo ops to start with a dot */
3917 {
3918 int n = 0;
3919 while (mote_pseudo_table[n].poc_name)
3920 {
3921 hack = (struct m68k_incant *)
3922 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3923 hash_insert (op_hash,
3924 mote_pseudo_table[n].poc_name, (char *) hack);
3925 hack->m_operands = 0;
3926 hack->m_opnum = n;
3927 n++;
3928 }
3929 }
3930#endif
3931
3932 init_regtable ();
3933
3934#ifdef OBJ_ELF
3935 record_alignment (text_section, 2);
3936 record_alignment (data_section, 2);
3937 record_alignment (bss_section, 2);
3938#endif
3939}
3940
3941static void
3942select_control_regs ()
3943{
3944 /* Note which set of "movec" control registers is available. */
3945 switch (cpu_of_arch (current_architecture))
3946 {
3947 case m68000:
3948 control_regs = m68000_control_regs;
3949 break;
3950 case m68010:
3951 control_regs = m68010_control_regs;
3952 break;
3953 case m68020:
3954 case m68030:
3955 control_regs = m68020_control_regs;
3956 break;
3957 case m68040:
3958 control_regs = m68040_control_regs;
3959 break;
3960 case m68060:
3961 control_regs = m68060_control_regs;
3962 break;
3963 case cpu32:
3964 control_regs = cpu32_control_regs;
3965 break;
3966 case mcf5200:
6da466c7
ILT		 3967 case mcf5206e:
3968 case mcf5307:
dc84e067 3969 case mcf5407:
6da466c7 3970 control_regs = mcf_control_regs;
252b5132
RH		 3971 break;
3972 default:
3973 abort ();
3974 }
3975}
3976
3977void
3978m68k_init_after_args ()
3979{
3980 if (cpu_of_arch (current_architecture) == 0)
3981 {
3982 int i;
3983 const char *default_cpu = TARGET_CPU;
3984
3985 if (*default_cpu == 'm')
3986 default_cpu++;
3987 for (i = 0; i < n_archs; i++)
3988 if (strcasecmp (default_cpu, archs[i].name) == 0)
3989 break;
3990 if (i == n_archs)
3991 {
3992 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
3993 current_architecture |= m68020;
3994 }
3995 else
3996 current_architecture |= archs[i].arch;
3997 }
3998 /* Permit m68881 specification with all cpus; those that can't work
3999 with a coprocessor could be doing emulation. */
4000 if (current_architecture & m68851)
4001 {
4002 if (current_architecture & m68040)
4003 {
4004 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4005 }
4006 }
4007 /* What other incompatibilities could we check for? */
4008
4009 /* Toss in some default assumptions about coprocessors. */
4010 if (!no_68881
4011 && (cpu_of_arch (current_architecture)
4012 /* Can CPU32 have a 68881 coprocessor?? */
4013 & (m68020 | m68030 | cpu32)))
4014 {
4015 current_architecture |= m68881;
4016 }
4017 if (!no_68851
4018 && (cpu_of_arch (current_architecture) & m68020up) != 0
4019 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4020 {
4021 current_architecture |= m68851;
4022 }
4023 if (no_68881 && (current_architecture & m68881))
4024 as_bad (_("options for 68881 and no-68881 both given"));
4025 if (no_68851 && (current_architecture & m68851))
4026 as_bad (_("options for 68851 and no-68851 both given"));
4027
4028#ifdef OBJ_AOUT
4029 /* Work out the magic number. This isn't very general. */
4030 if (current_architecture & m68000)
4031 m68k_aout_machtype = 0;
4032 else if (current_architecture & m68010)
4033 m68k_aout_machtype = 1;
4034 else if (current_architecture & m68020)
4035 m68k_aout_machtype = 2;
4036 else
4037 m68k_aout_machtype = 2;
4038#endif
4039
4040 /* Note which set of "movec" control registers is available. */
4041 select_control_regs ();
4042
4043 if (cpu_of_arch (current_architecture) < m68020
6da466c7 4044 || arch_coldfire_p (current_architecture))
252b5132
RH		 4045 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4046}
4047\f
4048/* This is called when a label is defined. */
4049
4050void
4051m68k_frob_label (sym)
4052 symbolS *sym;
4053{
4054 struct label_line *n;
4055
4056 n = (struct label_line *) xmalloc (sizeof *n);
4057 n->next = labels;
4058 n->label = sym;
4059 as_where (&n->file, &n->line);
4060 n->text = 0;
4061 labels = n;
4062 current_label = n;
4063}
4064
4065/* This is called when a value that is not an instruction is emitted. */
4066
4067void
4068m68k_flush_pending_output ()
4069{
4070 current_label = NULL;
4071}
4072
4073/* This is called at the end of the assembly, when the final value of
4074 the label is known. We warn if this is a text symbol aligned at an
4075 odd location. */
4076
4077void
4078m68k_frob_symbol (sym)
4079 symbolS *sym;
4080{
4081 if (S_GET_SEGMENT (sym) == reg_section
4082 && (int) S_GET_VALUE (sym) < 0)
4083 {
4084 S_SET_SEGMENT (sym, absolute_section);
4085 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4086 }
4087 else if ((S_GET_VALUE (sym) & 1) != 0)
4088 {
4089 struct label_line *l;
4090
4091 for (l = labels; l != NULL; l = l->next)
4092 {
4093 if (l->label == sym)
4094 {
4095 if (l->text)
4096 as_warn_where (l->file, l->line,
4097 _("text label `%s' aligned to odd boundary"),
4098 S_GET_NAME (sym));
4099 break;
4100 }
4101 }
4102 }
4103}
4104\f
4105/* This is called if we go in or out of MRI mode because of the .mri
4106 pseudo-op. */
4107
4108void
4109m68k_mri_mode_change (on)
4110 int on;
4111{
4112 if (on)
4113 {
4114 if (! flag_reg_prefix_optional)
4115 {
4116 flag_reg_prefix_optional = 1;
4117#ifdef REGISTER_PREFIX
4118 init_regtable ();
4119#endif
4120 }
4121 m68k_abspcadd = 1;
4122 if (! m68k_rel32_from_cmdline)
4123 m68k_rel32 = 0;
4124 }
4125 else
4126 {
4127 if (! reg_prefix_optional_seen)
4128 {
4129#ifdef REGISTER_PREFIX_OPTIONAL
4130 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4131#else
4132 flag_reg_prefix_optional = 0;
4133#endif
4134#ifdef REGISTER_PREFIX
4135 init_regtable ();
4136#endif
4137 }
4138 m68k_abspcadd = 0;
4139 if (! m68k_rel32_from_cmdline)
4140 m68k_rel32 = 1;
4141 }
4142}
4143
4144/* Equal to MAX_PRECISION in atof-ieee.c */
4145#define MAX_LITTLENUMS 6
4146
4147/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4148 of type TYPE, and store the appropriate bytes in *LITP. The number
4149 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4150 returned, or NULL on OK. */
4151
4152char *
4153md_atof (type, litP, sizeP)
4154 char type;
4155 char *litP;
4156 int *sizeP;
4157{
4158 int prec;
4159 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4160 LITTLENUM_TYPE *wordP;
4161 char *t;
4162
4163 switch (type)
4164 {
4165 case 'f':
4166 case 'F':
4167 case 's':
4168 case 'S':
4169 prec = 2;
4170 break;
4171
4172 case 'd':
4173 case 'D':
4174 case 'r':
4175 case 'R':
4176 prec = 4;
4177 break;
4178
4179 case 'x':
4180 case 'X':
4181 prec = 6;
4182 break;
4183
4184 case 'p':
4185 case 'P':
4186 prec = 6;
4187 break;
4188
4189 default:
4190 *sizeP = 0;
4191 return _("Bad call to MD_ATOF()");
4192 }
4193 t = atof_ieee (input_line_pointer, type, words);
4194 if (t)
4195 input_line_pointer = t;
4196
4197 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4198 for (wordP = words; prec--;)
4199 {
4200 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4201 litP += sizeof (LITTLENUM_TYPE);
4202 }
4203 return 0;
4204}
4205
4206void
4207md_number_to_chars (buf, val, n)
4208 char *buf;
4209 valueT val;
4210 int n;
4211{
4212 number_to_chars_bigendian (buf, val, n);
4213}
4214
4215static void
4216md_apply_fix_2 (fixP, val)
4217 fixS *fixP;
4218 offsetT val;
4219{
4220 addressT upper_limit;
4221 offsetT lower_limit;
4222
4223 /* This is unnecessary but it convinces the native rs6000 compiler
4224 to generate the code we want. */
4225 char *buf = fixP->fx_frag->fr_literal;
4226 buf += fixP->fx_where;
4227 /* end ibm compiler workaround */
4228
4229 if (val & 0x80000000)
4230 val |= ~(addressT)0x7fffffff;
4231 else
4232 val &= 0x7fffffff;
4233
4234#ifdef OBJ_ELF
4235 if (fixP->fx_addsy)
4236 {
4237 memset (buf, 0, fixP->fx_size);
4238 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4239
4240 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4241 && !S_IS_DEFINED (fixP->fx_addsy)
4242 && !S_IS_WEAK (fixP->fx_addsy))
4243 S_SET_WEAK (fixP->fx_addsy);
4244 return;
4245 }
4246#endif
4247
4248#ifdef BFD_ASSEMBLER
4249 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4250 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4251 return;
4252#endif
4253
4254 switch (fixP->fx_size)
4255 {
4256 /* The cast to offsetT below are necessary to make code correct for
4257 machines where ints are smaller than offsetT */
4258 case 1:
4259 *buf++ = val;
4260 upper_limit = 0x7f;
4261 lower_limit = - (offsetT) 0x80;
4262 break;
4263 case 2:
4264 *buf++ = (val >> 8);
4265 *buf++ = val;
4266 upper_limit = 0x7fff;
4267 lower_limit = - (offsetT) 0x8000;
4268 break;
4269 case 4:
4270 *buf++ = (val >> 24);
4271 *buf++ = (val >> 16);
4272 *buf++ = (val >> 8);
4273 *buf++ = val;
4274 upper_limit = 0x7fffffff;
4275 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4276 break;
4277 default:
4278 BAD_CASE (fixP->fx_size);
4279 }
4280
4281 /* Fix up a negative reloc. */
4282 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4283 {
4284 fixP->fx_addsy = fixP->fx_subsy;
4285 fixP->fx_subsy = NULL;
4286 fixP->fx_tcbit = 1;
4287 }
4288
4289 /* For non-pc-relative values, it's conceivable we might get something
4290 like "0xff" for a byte field. So extend the upper part of the range
4291 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4292 so that we can do any range checking at all. */
4293 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4294 upper_limit = upper_limit * 2 + 1;
4295
4296 if ((addressT) val > upper_limit
4297 && (val > 0 || val < lower_limit))
4298 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4299
4300 /* A one byte PC-relative reloc means a short branch. We can't use
4301 a short branch with a value of 0 or -1, because those indicate
4302 different opcodes (branches with longer offsets). fixup_segment
4303 in write.c may have clobbered fx_pcrel, so we need to examine the
4304 reloc type. */
4305 if ((fixP->fx_pcrel
4306#ifdef BFD_ASSEMBLER
4307 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4308#endif
4309 )
4310 && fixP->fx_size == 1
4311 && (fixP->fx_addsy == NULL
4312 || S_IS_DEFINED (fixP->fx_addsy))
4313 && (val == 0 || val == -1))
4314 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4315}
4316
4317#ifdef BFD_ASSEMBLER
4318int
4319md_apply_fix (fixP, valp)
4320 fixS *fixP;
4321 valueT *valp;
4322{
4323 md_apply_fix_2 (fixP, (addressT) *valp);
4324 return 1;
4325}
4326#else
4327void md_apply_fix (fixP, val)
4328 fixS *fixP;
4329 long val;
4330{
4331 md_apply_fix_2 (fixP, (addressT) val);
4332}
4333#endif
4334
4335/* *fragP has been relaxed to its final size, and now needs to have
4336 the bytes inside it modified to conform to the new size There is UGLY
4337 MAGIC here. ..
4338 */
4339static void
4340md_convert_frag_1 (fragP)
4341 register fragS *fragP;
4342{
4343 long disp;
252b5132
RH		 4344 fixS *fixP;
4345
4346 /* Address in object code of the displacement. */
4347 register int object_address = fragP->fr_fix + fragP->fr_address;
4348
4349 /* Address in gas core of the place to store the displacement. */
4350 /* This convinces the native rs6000 compiler to generate the code we
92774660 4351 want. */
252b5132
RH		 4352 register char *buffer_address = fragP->fr_literal;
4353 buffer_address += fragP->fr_fix;
4354 /* end ibm compiler workaround */
4355
4356 /* The displacement of the address, from current location. */
4357 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4358 disp = (disp + fragP->fr_offset) - object_address;
4359
4360#ifdef BFD_ASSEMBLER
49309057 4361 disp += symbol_get_frag (fragP->fr_symbol)->fr_address;
252b5132
RH		 4362#endif
4363
4364 switch (fragP->fr_subtype)
4365 {
151337e8
NC		 4366 case TAB (BRANCHBWL, BYTE):
4367 case TAB (BRABSJUNC, BYTE):
4368 case TAB (BRABSJCOND, BYTE):
4369 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4370 know (issbyte (disp));
4371 if (disp == 0)
4372 as_bad (_("short branch with zero offset: use :w"));
151337e8 4373 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4374 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4375 fixP->fx_pcrel_adjust = -1;
252b5132 4376 break;
151337e8
NC		 4377 case TAB (BRANCHBWL, SHORT):
4378 case TAB (BRABSJUNC, SHORT):
4379 case TAB (BRABSJCOND, SHORT):
4380 case TAB (BRANCHBW, SHORT):
252b5132 4381 fragP->fr_opcode[1] = 0x00;
151337e8 4382 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4383 1, RELAX_RELOC_PC16);
151337e8
NC		 4384 fragP->fr_fix += 2;
4385 break;
4386 case TAB (BRANCHBWL, LONG):
4387 fragP->fr_opcode[1] = (char) 0xFF;
4388 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4389 1, RELAX_RELOC_PC32);
151337e8 4390 fragP->fr_fix += 4;
252b5132 4391 break;
151337e8
NC		 4392 case TAB (BRABSJUNC, LONG):
4393 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4394 {
151337e8
NC		 4395 fragP->fr_opcode[0] = 0x4E;
4396 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand */
4397 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3ae647a0 4398 0, RELAX_RELOC_ABS32);
151337e8
NC		 4399 fragP->fr_fix += 4;
4400 }
4401 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4402 {
4403 fragP->fr_opcode[0] = 0x4E;
4404 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand */
4405 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4406 0, RELAX_RELOC_ABS32);
151337e8 4407 fragP->fr_fix += 4;
252b5132
RH		 4408 }
4409 else
4410 {
151337e8
NC		 4411 /* This cannot happen, because jbsr and jbra are the only two
4412 unconditional branches. */
4413 abort ();
252b5132
RH		 4414 }
4415 break;
151337e8
NC		 4416 case TAB (BRABSJCOND, LONG):
4417 /* Only Bcc 68000 instructions can come here. */
4418 /* Change bcc into b!cc/jmp absl long. */
92774660 4419
252b5132
RH		 4420 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4421 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4422
4423 /* JF: these used to be fr_opcode[2,3], but they may be in a
4424 different frag, in which case refering to them is a no-no.
92774660 4425 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4426 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4427 *buffer_address++ = (char) 0xf9;
4428 fragP->fr_fix += 2; /* account for jmp instruction */
4429 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5cbdaa77 4430 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4431 fragP->fr_fix += 4;
4432 break;
4433 case TAB (FBRANCH, SHORT):
4434 know ((fragP->fr_opcode[1] & 0x40) == 0);
4435 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4436 1, RELAX_RELOC_PC16);
151337e8
NC		 4437 fragP->fr_fix += 2;
4438 break;
4439 case TAB (FBRANCH, LONG):
4440 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4441 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4442 1, RELAX_RELOC_PC32);
252b5132 4443 fragP->fr_fix += 4;
252b5132 4444 break;
151337e8
NC		 4445 case TAB (DBCCLBR, SHORT):
4446 case TAB (DBCCABSJ, SHORT):
4447 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4448 1, RELAX_RELOC_PC16);
151337e8
NC		 4449 fragP->fr_fix += 2;
4450 break;
4451 case TAB (DBCCLBR, LONG):
4452 /* only DBcc instructions can come here */
28e7409f 4453 /* Change dbcc into dbcc/bral. */
28e7409f 4454
252b5132
RH		 4455 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4456 *buffer_address++ = 0x00; /* branch offset = 4 */
4457 *buffer_address++ = 0x04;
4458 *buffer_address++ = 0x60; /* put in bra pc+6 */
4459 *buffer_address++ = 0x06;
151337e8
NC		 4460 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4461 *buffer_address++ = (char) 0xff;
252b5132
RH		 4462
4463 fragP->fr_fix += 6; /* account for bra/jmp instructions */
151337e8 4464 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
5cbdaa77 4465 RELAX_RELOC_PC32);
252b5132 4466 fragP->fr_fix += 4;
252b5132 4467 break;
151337e8
NC		 4468 case TAB (DBCCABSJ, LONG):
4469 /* only DBcc instructions can come here */
4470 /* Change dbcc into dbcc/jmp. */
4471
4472 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4473 *buffer_address++ = 0x00; /* branch offset = 4 */
4474 *buffer_address++ = 0x04;
4475 *buffer_address++ = 0x60; /* put in bra pc+6 */
4476 *buffer_address++ = 0x06;
4477 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4478 *buffer_address++ = (char) 0xf9;
4479
4480 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4481 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
5cbdaa77 4482 RELAX_RELOC_ABS32);
252b5132 4483 fragP->fr_fix += 4;
252b5132 4484 break;
151337e8 4485 case TAB (PCREL1632, SHORT):
252b5132
RH		 4486 fragP->fr_opcode[1] &= ~0x3F;
4487 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
151337e8 4488 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4489 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 4490 fragP->fr_fix += 2;
252b5132 4491 break;
151337e8 4492 case TAB (PCREL1632, LONG):
252b5132
RH		 4493 /* Already set to mode 7.3; this indicates: PC indirect with
4494 suppressed index, 32-bit displacement. */
4495 *buffer_address++ = 0x01;
4496 *buffer_address++ = 0x70;
4497 fragP->fr_fix += 2;
151337e8 4498 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4499 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4500 fixP->fx_pcrel_adjust = 2;
4501 fragP->fr_fix += 4;
252b5132 4502 break;
252b5132 4503 case TAB (PCINDEX, BYTE):
252b5132
RH		 4504 assert (fragP->fr_fix >= 2);
4505 buffer_address[-2] &= ~1;
151337e8 4506 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4507 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4508 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 4509 break;
4510 case TAB (PCINDEX, SHORT):
252b5132
RH		 4511 assert (fragP->fr_fix >= 2);
4512 buffer_address[-2] |= 0x1;
4513 buffer_address[-1] = 0x20;
4514 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4515 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 4516 fixP->fx_pcrel_adjust = 2;
151337e8 4517 fragP->fr_fix += 2;
252b5132
RH		 4518 break;
4519 case TAB (PCINDEX, LONG):
252b5132
RH		 4520 assert (fragP->fr_fix >= 2);
4521 buffer_address[-2] |= 0x1;
4522 buffer_address[-1] = 0x30;
151337e8 4523 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4524 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4525 fixP->fx_pcrel_adjust = 2;
4526 fragP->fr_fix += 4;
4527 break;
4528 case TAB (ABSTOPCREL, SHORT):
4529 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4530 1, RELAX_RELOC_PC16);
151337e8
NC		 4531 fragP->fr_fix += 2;
4532 break;
4533 case TAB (ABSTOPCREL, LONG):
4534 /* The thing to do here is force it to ABSOLUTE LONG, since
4535 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */
4536 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4537 abort ();
4538 fragP->fr_opcode[1] &= ~0x3F;
4539 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4540 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4541 0, RELAX_RELOC_ABS32);
151337e8 4542 fragP->fr_fix += 4;
252b5132 4543 break;
252b5132
RH		 4544 }
4545}
4546
4547#ifndef BFD_ASSEMBLER
4548
4549void
4550md_convert_frag (headers, sec, fragP)
8fce3f5e
AM		 4551 object_headers *headers ATTRIBUTE_UNUSED;
4552 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4553 fragS *fragP;
4554{
4555 md_convert_frag_1 (fragP);
4556}
4557
4558#else
4559
4560void
4561md_convert_frag (abfd, sec, fragP)
36823076
AS		 4562 bfd *abfd ATTRIBUTE_UNUSED;
4563 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4564 fragS *fragP;
4565{
4566 md_convert_frag_1 (fragP);
4567}
4568#endif
4569
4570/* Force truly undefined symbols to their maximum size, and generally set up
4571 the frag list to be relaxed
4572 */
4573int
4574md_estimate_size_before_relax (fragP, segment)
4575 register fragS *fragP;
4576 segT segment;
4577{
4578 int old_fix;
252b5132
RH		 4579
4580 old_fix = fragP->fr_fix;
4581
151337e8 4582 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 4583 switch (fragP->fr_subtype)
4584 {
151337e8
NC		 4585 case TAB (BRANCHBWL, SZ_UNDEF):
4586 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 4587 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 4588 {
151337e8
NC		 4589 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4590 && relaxable_symbol (fragP->fr_symbol))
252b5132 4591 {
151337e8
NC		 4592 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4593 }
4594 else if (flag_short_refs)
4595 {
4596 /* Symbol is undefined and we want short ref. */
4597 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4598 }
4599 else
4600 {
151337e8
NC		 4601 /* Symbol is still undefined. Make it LONG. */
4602 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4603 }
4604 break;
151337e8 4605 }
252b5132 4606
151337e8 4607 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 4608 {
151337e8
NC		 4609 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4610 && relaxable_symbol (fragP->fr_symbol))
252b5132 4611 {
151337e8 4612 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 4613 }
4614 else
4615 {
151337e8
NC		 4616 /* Symbol is undefined and we don't have long branches. */
4617 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4618 }
4619 break;
151337e8 4620 }
252b5132 4621
151337e8 4622 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 4623 case TAB (DBCCLBR, SZ_UNDEF):
4624 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 4625 case TAB (PCREL1632, SZ_UNDEF):
252b5132 4626 {
8ec6253e
NC		 4627 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4628 && relaxable_symbol (fragP->fr_symbol))
151337e8 4629 || flag_short_refs)
252b5132 4630 {
151337e8 4631 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4632 }
4633 else
4634 {
151337e8 4635 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4636 }
4637 break;
151337e8 4638 }
81d4177b 4639
252b5132
RH		 4640 case TAB (PCINDEX, SZ_UNDEF):
4641 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 4642 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 4643 {
4644 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4645 }
4646 else
4647 {
4648 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 4649 }
4650 break;
4651
151337e8
NC		 4652 case TAB (ABSTOPCREL, SZ_UNDEF):
4653 {
4654 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4655 && relaxable_symbol (fragP->fr_symbol)))
4656 {
4657 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 4658 }
4659 else
4660 {
4661 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 4662 }
4663 break;
4664 }
4665
252b5132
RH		 4666 default:
4667 break;
4668 }
4669
151337e8 4670 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 4671 switch (fragP->fr_subtype)
4672 {
151337e8
NC		 4673 case TAB (BRANCHBWL, BYTE):
4674 case TAB (BRABSJUNC, BYTE):
4675 case TAB (BRABSJCOND, BYTE):
4676 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4677 /* We can't do a short jump to the next instruction, so in that
4678 case we force word mode. At this point S_GET_VALUE should
4679 return the offset of the symbol within its frag. If the
4680 symbol is at the start of a frag, and it is the next frag
4681 with any data in it (usually this is just the next frag, but
4682 assembler listings may introduce empty frags), we must use
4683 word mode. */
4684 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4685 {
49309057 4686 fragS *stop;
252b5132
RH		 4687 fragS *l;
4688
49309057
ILT		 4689 stop = symbol_get_frag (fragP->fr_symbol);
4690 for (l = fragP->fr_next; l != stop; l = l->fr_next)
252b5132
RH		 4691 if (l->fr_fix + l->fr_var != 0)
4692 break;
49309057 4693 if (l == stop)
252b5132
RH		 4694 {
4695 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4696 }
4697 }
4698 break;
4699 default:
4700 break;
4701 }
5c65dbc1 4702 fragP->fr_var = md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 4703 return fragP->fr_var + fragP->fr_fix - old_fix;
4704}
4705
4706#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4707/* the bit-field entries in the relocation_info struct plays hell
4708 with the byte-order problems of cross-assembly. So as a hack,
4709 I added this mach. dependent ri twiddler. Ugly, but it gets
4710 you there. -KWK */
4711/* on m68k: first 4 bytes are normal unsigned long, next three bytes
4712 are symbolnum, most sig. byte first. Last byte is broken up with
4713 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4714 nibble as nuthin. (on Sun 3 at least) */
4715/* Translate the internal relocation information into target-specific
92774660 4716 format. */
252b5132
RH		 4717#ifdef comment
4718void
4719md_ri_to_chars (the_bytes, ri)
4720 char *the_bytes;
4721 struct reloc_info_generic *ri;
4722{
4723 /* this is easy */
4724 md_number_to_chars (the_bytes, ri->r_address, 4);
4725 /* now the fun stuff */
4726 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4727 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4728 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4729 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4730 ((ri->r_extern << 4) & 0x10));
4731}
4732
4733#endif /* comment */
4734
4735#ifndef BFD_ASSEMBLER
4736void
4737tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4738 char *where;
4739 fixS *fixP;
4740 relax_addressT segment_address_in_file;
4741{
4742 /*
4743 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4744 * Out: GNU LD relocation length code: 0, 1, or 2.
4745 */
4746
4747 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4748 long r_symbolnum;
4749
4750 know (fixP->fx_addsy != NULL);
4751
4752 md_number_to_chars (where,
4753 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4754 4);
4755
4756 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4757 ? S_GET_TYPE (fixP->fx_addsy)
4758 : fixP->fx_addsy->sy_number);
4759
4760 where[4] = (r_symbolnum >> 16) & 0x0ff;
4761 where[5] = (r_symbolnum >> 8) & 0x0ff;
4762 where[6] = r_symbolnum & 0x0ff;
4763 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4764 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4765}
4766#endif
4767
4768#endif /* OBJ_AOUT or OBJ_BOUT */
4769
4770#ifndef WORKING_DOT_WORD
4771CONST int md_short_jump_size = 4;
4772CONST int md_long_jump_size = 6;
4773
4774void
4775md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4776 char *ptr;
4777 addressT from_addr, to_addr;
36823076
AS		 4778 fragS *frag ATTRIBUTE_UNUSED;
4779 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132
RH		 4780{
4781 valueT offset;
4782
4783 offset = to_addr - (from_addr + 2);
4784
4785 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4786 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4787}
4788
4789void
4790md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4791 char *ptr;
4792 addressT from_addr, to_addr;
4793 fragS *frag;
4794 symbolS *to_symbol;
4795{
4796 valueT offset;
4797
4798 if (!HAVE_LONG_BRANCH(current_architecture))
4799 {
4800 offset = to_addr - S_GET_VALUE (to_symbol);
4801 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4802 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4803 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4804 0, NO_RELOC);
4805 }
4806 else
4807 {
4808 offset = to_addr - (from_addr + 2);
4809 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4810 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4811 }
4812}
4813
4814#endif
4815
4816/* Different values of OK tell what its OK to return. Things that
4817 aren't OK are an error (what a shock, no?)
4818
4819 0: Everything is OK
4820 10: Absolute 1:8 only
4821 20: Absolute 0:7 only
4822 30: absolute 0:15 only
4823 40: Absolute 0:31 only
4824 50: absolute 0:127 only
4825 55: absolute -64:63 only
4826 60: absolute -128:127 only
4827 70: absolute 0:4095 only
4828 80: No bignums
4829
4830 */
4831
4832static int
4833get_num (exp, ok)
4834 struct m68k_exp *exp;
4835 int ok;
4836{
4837 if (exp->exp.X_op == O_absent)
4838 {
4839 /* Do the same thing the VAX asm does */
4840 op (exp) = O_constant;
4841 adds (exp) = 0;
4842 subs (exp) = 0;
4843 offs (exp) = 0;
4844 if (ok == 10)
4845 {
4846 as_warn (_("expression out of range: defaulting to 1"));
4847 offs (exp) = 1;
4848 }
4849 }
4850 else if (exp->exp.X_op == O_constant)
4851 {
4852 switch (ok)
4853 {
4854 case 10:
4855 if (offs (exp) < 1 || offs (exp) > 8)
4856 {
4857 as_warn (_("expression out of range: defaulting to 1"));
4858 offs (exp) = 1;
4859 }
4860 break;
4861 case 20:
4862 if (offs (exp) < 0 || offs (exp) > 7)
4863 goto outrange;
4864 break;
4865 case 30:
4866 if (offs (exp) < 0 || offs (exp) > 15)
4867 goto outrange;
4868 break;
4869 case 40:
4870 if (offs (exp) < 0 || offs (exp) > 32)
4871 goto outrange;
4872 break;
4873 case 50:
4874 if (offs (exp) < 0 || offs (exp) > 127)
4875 goto outrange;
4876 break;
4877 case 55:
4878 if (offs (exp) < -64 || offs (exp) > 63)
4879 goto outrange;
4880 break;
4881 case 60:
4882 if (offs (exp) < -128 || offs (exp) > 127)
4883 goto outrange;
4884 break;
4885 case 70:
4886 if (offs (exp) < 0 || offs (exp) > 4095)
4887 {
4888 outrange:
4889 as_warn (_("expression out of range: defaulting to 0"));
4890 offs (exp) = 0;
4891 }
4892 break;
4893 default:
4894 break;
4895 }
4896 }
4897 else if (exp->exp.X_op == O_big)
4898 {
4899 if (offs (exp) <= 0 /* flonum */
4900 && (ok == 80 /* no bignums */
4901 || (ok > 10 /* small-int ranges including 0 ok */
4902 /* If we have a flonum zero, a zero integer should
4903 do as well (e.g., in moveq). */
4904 && generic_floating_point_number.exponent == 0
4905 && generic_floating_point_number.low[0] == 0)))
4906 {
4907 /* HACK! Turn it into a long */
4908 LITTLENUM_TYPE words[6];
4909
4910 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4911 op (exp) = O_constant;
4912 adds (exp) = 0;
4913 subs (exp) = 0;
4914 offs (exp) = words[1] | (words[0] << 16);
4915 }
4916 else if (ok != 0)
4917 {
4918 op (exp) = O_constant;
4919 adds (exp) = 0;
4920 subs (exp) = 0;
4921 offs (exp) = (ok == 10) ? 1 : 0;
4922 as_warn (_("Can't deal with expression; defaulting to %ld"),
4923 offs (exp));
4924 }
4925 }
4926 else
4927 {
4928 if (ok >= 10 && ok <= 70)
4929 {
4930 op (exp) = O_constant;
4931 adds (exp) = 0;
4932 subs (exp) = 0;
4933 offs (exp) = (ok == 10) ? 1 : 0;
4934 as_warn (_("Can't deal with expression; defaulting to %ld"),
4935 offs (exp));
4936 }
4937 }
4938
4939 if (exp->size != SIZE_UNSPEC)
4940 {
4941 switch (exp->size)
4942 {
4943 case SIZE_UNSPEC:
4944 case SIZE_LONG:
4945 break;
4946 case SIZE_BYTE:
4947 if (!isbyte (offs (exp)))
4948 as_warn (_("expression doesn't fit in BYTE"));
4949 break;
4950 case SIZE_WORD:
4951 if (!isword (offs (exp)))
4952 as_warn (_("expression doesn't fit in WORD"));
4953 break;
4954 }
4955 }
4956
4957 return offs (exp);
4958}
4959
4960/* These are the back-ends for the various machine dependent pseudo-ops. */
4961
4962static void
4963s_data1 (ignore)
36823076 4964 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4965{
4966 subseg_set (data_section, 1);
4967 demand_empty_rest_of_line ();
4968}
4969
4970static void
4971s_data2 (ignore)
36823076 4972 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4973{
4974 subseg_set (data_section, 2);
4975 demand_empty_rest_of_line ();
4976}
4977
4978static void
4979s_bss (ignore)
36823076 4980 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4981{
4982 /* We don't support putting frags in the BSS segment, we fake it
4983 by marking in_bss, then looking at s_skip for clues. */
4984
4985 subseg_set (bss_section, 0);
4986 demand_empty_rest_of_line ();
4987}
4988
4989static void
4990s_even (ignore)
36823076 4991 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4992{
4993 register int temp;
4994 register long temp_fill;
4995
4996 temp = 1; /* JF should be 2? */
4997 temp_fill = get_absolute_expression ();
92774660 4998 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 4999 frag_align (temp, (int) temp_fill, 0);
5000 demand_empty_rest_of_line ();
5001 record_alignment (now_seg, temp);
5002}
5003
5004static void
5005s_proc (ignore)
36823076 5006 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5007{
5008 demand_empty_rest_of_line ();
5009}
5010\f
5011/* Pseudo-ops handled for MRI compatibility. */
5012
5013/* This function returns non-zero if the argument is a conditional
5014 pseudo-op. This is called when checking whether a pending
5015 alignment is needed. */
5016
5017int
5018m68k_conditional_pseudoop (pop)
5019 pseudo_typeS *pop;
5020{
5021 return (pop->poc_handler == s_mri_if
5022 || pop->poc_handler == s_mri_else);
5023}
5024
5025/* Handle an MRI style chip specification. */
5026
5027static void
5028mri_chip ()
5029{
5030 char *s;
5031 char c;
5032 int i;
5033
5034 s = input_line_pointer;
5035 /* We can't use get_symbol_end since the processor names are not proper
5036 symbols. */
5037 while (is_part_of_name (c = *input_line_pointer++))
5038 ;
5039 *--input_line_pointer = 0;
5040 for (i = 0; i < n_archs; i++)
5041 if (strcasecmp (s, archs[i].name) == 0)
5042 break;
5043 if (i >= n_archs)
5044 {
5045 as_bad (_("%s: unrecognized processor name"), s);
5046 *input_line_pointer = c;
5047 ignore_rest_of_line ();
5048 return;
5049 }
5050 *input_line_pointer = c;
5051
5052 if (*input_line_pointer == '/')
5053 current_architecture = 0;
5054 else
5055 current_architecture &= m68881 | m68851;
5056 current_architecture |= archs[i].arch;
5057
5058 while (*input_line_pointer == '/')
5059 {
5060 ++input_line_pointer;
5061 s = input_line_pointer;
5062 /* We can't use get_symbol_end since the processor names are not
5063 proper symbols. */
5064 while (is_part_of_name (c = *input_line_pointer++))
5065 ;
5066 *--input_line_pointer = 0;
5067 if (strcmp (s, "68881") == 0)
5068 current_architecture |= m68881;
5069 else if (strcmp (s, "68851") == 0)
5070 current_architecture |= m68851;
5071 *input_line_pointer = c;
5072 }
5073
5074 /* Update info about available control registers. */
5075 select_control_regs ();
5076}
5077
5078/* The MRI CHIP pseudo-op. */
5079
5080static void
5081s_chip (ignore)
36823076 5082 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5083{
5084 char *stop = NULL;
5085 char stopc;
5086
5087 if (flag_mri)
5088 stop = mri_comment_field (&stopc);
5089 mri_chip ();
5090 if (flag_mri)
5091 mri_comment_end (stop, stopc);
5092 demand_empty_rest_of_line ();
5093}
5094
5095/* The MRI FOPT pseudo-op. */
5096
5097static void
5098s_fopt (ignore)
36823076 5099 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5100{
5101 SKIP_WHITESPACE ();
5102
5103 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5104 {
5105 int temp;
5106
5107 input_line_pointer += 3;
5108 temp = get_absolute_expression ();
5109 if (temp < 0 || temp > 7)
5110 as_bad (_("bad coprocessor id"));
5111 else
5112 m68k_float_copnum = COP0 + temp;
5113 }
5114 else
5115 {
5116 as_bad (_("unrecognized fopt option"));
5117 ignore_rest_of_line ();
5118 return;
5119 }
5120
5121 demand_empty_rest_of_line ();
5122}
5123
5124/* The structure used to handle the MRI OPT pseudo-op. */
5125
5126struct opt_action
5127{
5128 /* The name of the option. */
5129 const char *name;
5130
5131 /* If this is not NULL, just call this function. The first argument
5132 is the ARG field of this structure, the second argument is
5133 whether the option was negated. */
5134 void (*pfn) PARAMS ((int arg, int on));
5135
5136 /* If this is not NULL, and the PFN field is NULL, set the variable
5137 this points to. Set it to the ARG field if the option was not
5138 negated, and the NOTARG field otherwise. */
5139 int *pvar;
5140
5141 /* The value to pass to PFN or to assign to *PVAR. */
5142 int arg;
5143
5144 /* The value to assign to *PVAR if the option is negated. If PFN is
5145 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5146 the option may not be negated. */
5147 int notarg;
5148};
5149
5150/* The table used to handle the MRI OPT pseudo-op. */
5151
5152static void skip_to_comma PARAMS ((int, int));
5153static void opt_nest PARAMS ((int, int));
5154static void opt_chip PARAMS ((int, int));
5155static void opt_list PARAMS ((int, int));
5156static void opt_list_symbols PARAMS ((int, int));
5157
5158static const struct opt_action opt_table[] =
5159{
5160 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5161
5162 /* We do relaxing, so there is little use for these options. */
5163 { "b", 0, 0, 0, 0 },
5164 { "brs", 0, 0, 0, 0 },
5165 { "brb", 0, 0, 0, 0 },
5166 { "brl", 0, 0, 0, 0 },
5167 { "brw", 0, 0, 0, 0 },
5168
5169 { "c", 0, 0, 0, 0 },
5170 { "cex", 0, 0, 0, 0 },
5171 { "case", 0, &symbols_case_sensitive, 1, 0 },
5172 { "cl", 0, 0, 0, 0 },
5173 { "cre", 0, 0, 0, 0 },
5174 { "d", 0, &flag_keep_locals, 1, 0 },
5175 { "e", 0, 0, 0, 0 },
5176 { "f", 0, &flag_short_refs, 1, 0 },
5177 { "frs", 0, &flag_short_refs, 1, 0 },
5178 { "frl", 0, &flag_short_refs, 0, 1 },
5179 { "g", 0, 0, 0, 0 },
5180 { "i", 0, 0, 0, 0 },
5181 { "m", 0, 0, 0, 0 },
5182 { "mex", 0, 0, 0, 0 },
5183 { "mc", 0, 0, 0, 0 },
5184 { "md", 0, 0, 0, 0 },
5185 { "nest", opt_nest, 0, 0, 0 },
5186 { "next", skip_to_comma, 0, 0, 0 },
5187 { "o", 0, 0, 0, 0 },
5188 { "old", 0, 0, 0, 0 },
5189 { "op", skip_to_comma, 0, 0, 0 },
5190 { "pco", 0, 0, 0, 0 },
5191 { "p", opt_chip, 0, 0, 0 },
5192 { "pcr", 0, 0, 0, 0 },
5193 { "pcs", 0, 0, 0, 0 },
5194 { "r", 0, 0, 0, 0 },
5195 { "quick", 0, &m68k_quick, 1, 0 },
5196 { "rel32", 0, &m68k_rel32, 1, 0 },
5197 { "s", opt_list, 0, 0, 0 },
5198 { "t", opt_list_symbols, 0, 0, 0 },
5199 { "w", 0, &flag_no_warnings, 0, 1 },
5200 { "x", 0, 0, 0, 0 }
5201};
5202
8fce3f5e 5203#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5204
5205/* The MRI OPT pseudo-op. */
5206
5207static void
5208s_opt (ignore)
36823076 5209 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5210{
5211 do
5212 {
5213 int t;
5214 char *s;
5215 char c;
5216 int i;
5217 const struct opt_action *o;
5218
5219 SKIP_WHITESPACE ();
5220
5221 t = 1;
5222 if (*input_line_pointer == '-')
5223 {
5224 ++input_line_pointer;
5225 t = 0;
5226 }
5227 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5228 {
5229 input_line_pointer += 2;
5230 t = 0;
5231 }
5232
5233 s = input_line_pointer;
5234 c = get_symbol_end ();
5235
5236 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5237 {
5238 if (strcasecmp (s, o->name) == 0)
5239 {
5240 if (o->pfn)
5241 {
5242 /* Restore input_line_pointer now in case the option
5243 takes arguments. */
5244 *input_line_pointer = c;
5245 (*o->pfn) (o->arg, t);
5246 }
5247 else if (o->pvar != NULL)
5248 {
5249 if (! t && o->arg == o->notarg)
5250 as_bad (_("option `%s' may not be negated"), s);
5251 *input_line_pointer = c;
5252 *o->pvar = t ? o->arg : o->notarg;
5253 }
5254 else
5255 *input_line_pointer = c;
5256 break;
5257 }
5258 }
5259 if (i >= OPTCOUNT)
5260 {
5261 as_bad (_("option `%s' not recognized"), s);
5262 *input_line_pointer = c;
5263 }
5264 }
5265 while (*input_line_pointer++ == ',');
5266
5267 /* Move back to terminating character. */
5268 --input_line_pointer;
5269 demand_empty_rest_of_line ();
5270}
5271
5272/* Skip ahead to a comma. This is used for OPT options which we do
5273 not suppor tand which take arguments. */
5274
5275static void
5276skip_to_comma (arg, on)
36823076
AS		 5277 int arg ATTRIBUTE_UNUSED;
5278 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5279{
5280 while (*input_line_pointer != ','
5281 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5282 ++input_line_pointer;
5283}
5284
5285/* Handle the OPT NEST=depth option. */
5286
5287static void
5288opt_nest (arg, on)
36823076
AS		 5289 int arg ATTRIBUTE_UNUSED;
5290 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5291{
5292 if (*input_line_pointer != '=')
5293 {
5294 as_bad (_("bad format of OPT NEST=depth"));
5295 return;
5296 }
5297
5298 ++input_line_pointer;
5299 max_macro_nest = get_absolute_expression ();
5300}
5301
5302/* Handle the OPT P=chip option. */
5303
5304static void
5305opt_chip (arg, on)
36823076
AS		 5306 int arg ATTRIBUTE_UNUSED;
5307 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5308{
5309 if (*input_line_pointer != '=')
5310 {
5311 /* This is just OPT P, which we do not support. */
5312 return;
5313 }
5314
5315 ++input_line_pointer;
5316 mri_chip ();
5317}
5318
5319/* Handle the OPT S option. */
5320
5321static void
5322opt_list (arg, on)
36823076 5323 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5324 int on;
5325{
5326 listing_list (on);
5327}
5328
5329/* Handle the OPT T option. */
5330
5331static void
5332opt_list_symbols (arg, on)
36823076 5333 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5334 int on;
5335{
5336 if (on)
5337 listing |= LISTING_SYMBOLS;
5338 else
5339 listing &=~ LISTING_SYMBOLS;
5340}
5341
5342/* Handle the MRI REG pseudo-op. */
5343
5344static void
5345s_reg (ignore)
36823076 5346 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5347{
5348 char *s;
5349 int c;
5350 struct m68k_op rop;
5351 int mask;
5352 char *stop = NULL;
5353 char stopc;
5354
5355 if (line_label == NULL)
5356 {
5357 as_bad (_("missing label"));
5358 ignore_rest_of_line ();
5359 return;
5360 }
5361
5362 if (flag_mri)
5363 stop = mri_comment_field (&stopc);
5364
5365 SKIP_WHITESPACE ();
5366
5367 s = input_line_pointer;
5368 while (isalnum ((unsigned char) *input_line_pointer)
5369#ifdef REGISTER_PREFIX
5370 || *input_line_pointer == REGISTER_PREFIX
5371#endif
5372 || *input_line_pointer == '/'
5373 || *input_line_pointer == '-')
5374 ++input_line_pointer;
5375 c = *input_line_pointer;
5376 *input_line_pointer = '\0';
5377
5378 if (m68k_ip_op (s, &rop) != 0)
5379 {
5380 if (rop.error == NULL)
5381 as_bad (_("bad register list"));
5382 else
5383 as_bad (_("bad register list: %s"), rop.error);
5384 *input_line_pointer = c;
5385 ignore_rest_of_line ();
5386 return;
5387 }
5388
5389 *input_line_pointer = c;
5390
5391 if (rop.mode == REGLST)
5392 mask = rop.mask;
5393 else if (rop.mode == DREG)
5394 mask = 1 << (rop.reg - DATA0);
5395 else if (rop.mode == AREG)
5396 mask = 1 << (rop.reg - ADDR0 + 8);
5397 else if (rop.mode == FPREG)
5398 mask = 1 << (rop.reg - FP0 + 16);
5399 else if (rop.mode == CONTROL
5400 && rop.reg == FPI)
5401 mask = 1 << 24;
5402 else if (rop.mode == CONTROL
5403 && rop.reg == FPS)
5404 mask = 1 << 25;
5405 else if (rop.mode == CONTROL
5406 && rop.reg == FPC)
5407 mask = 1 << 26;
5408 else
5409 {
5410 as_bad (_("bad register list"));
5411 ignore_rest_of_line ();
5412 return;
5413 }
5414
5415 S_SET_SEGMENT (line_label, reg_section);
5416 S_SET_VALUE (line_label, ~mask);
49309057 5417 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5418
5419 if (flag_mri)
5420 mri_comment_end (stop, stopc);
5421
5422 demand_empty_rest_of_line ();
5423}
5424
5425/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5426
5427struct save_opts
5428{
5429 struct save_opts *next;
5430 int abspcadd;
5431 int symbols_case_sensitive;
5432 int keep_locals;
5433 int short_refs;
5434 int architecture;
5435 int quick;
5436 int rel32;
5437 int listing;
5438 int no_warnings;
5439 /* FIXME: We don't save OPT S. */
5440};
5441
5442/* This variable holds the stack of saved options. */
5443
5444static struct save_opts *save_stack;
5445
5446/* The MRI SAVE pseudo-op. */
5447
5448static void
5449s_save (ignore)
36823076 5450 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5451{
5452 struct save_opts *s;
5453
5454 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5455 s->abspcadd = m68k_abspcadd;
5456 s->symbols_case_sensitive = symbols_case_sensitive;
5457 s->keep_locals = flag_keep_locals;
5458 s->short_refs = flag_short_refs;
5459 s->architecture = current_architecture;
5460 s->quick = m68k_quick;
5461 s->rel32 = m68k_rel32;
5462 s->listing = listing;
5463 s->no_warnings = flag_no_warnings;
5464
5465 s->next = save_stack;
5466 save_stack = s;
5467
5468 demand_empty_rest_of_line ();
5469}
5470
5471/* The MRI RESTORE pseudo-op. */
5472
5473static void
5474s_restore (ignore)
36823076 5475 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5476{
5477 struct save_opts *s;
5478
5479 if (save_stack == NULL)
5480 {
5481 as_bad (_("restore without save"));
5482 ignore_rest_of_line ();
5483 return;
5484 }
5485
5486 s = save_stack;
5487 save_stack = s->next;
5488
5489 m68k_abspcadd = s->abspcadd;
5490 symbols_case_sensitive = s->symbols_case_sensitive;
5491 flag_keep_locals = s->keep_locals;
5492 flag_short_refs = s->short_refs;
5493 current_architecture = s->architecture;
5494 m68k_quick = s->quick;
5495 m68k_rel32 = s->rel32;
5496 listing = s->listing;
5497 flag_no_warnings = s->no_warnings;
5498
5499 free (s);
5500
5501 demand_empty_rest_of_line ();
5502}
5503
5504/* Types of MRI structured control directives. */
5505
5506enum mri_control_type
5507{
5508 mri_for,
5509 mri_if,
5510 mri_repeat,
5511 mri_while
5512};
5513
5514/* This structure is used to stack the MRI structured control
5515 directives. */
5516
5517struct mri_control_info
5518{
5519 /* The directive within which this one is enclosed. */
5520 struct mri_control_info *outer;
5521
5522 /* The type of directive. */
5523 enum mri_control_type type;
5524
5525 /* Whether an ELSE has been in an IF. */
5526 int else_seen;
5527
5528 /* The add or sub statement at the end of a FOR. */
5529 char *incr;
5530
5531 /* The label of the top of a FOR or REPEAT loop. */
5532 char *top;
5533
5534 /* The label to jump to for the next iteration, or the else
5535 expression of a conditional. */
5536 char *next;
5537
5538 /* The label to jump to to break out of the loop, or the label past
5539 the end of a conditional. */
5540 char *bottom;
5541};
5542
5543/* The stack of MRI structured control directives. */
5544
5545static struct mri_control_info *mri_control_stack;
5546
5547/* The current MRI structured control directive index number, used to
5548 generate label names. */
5549
5550static int mri_control_index;
5551
5552/* Some function prototypes. */
5553
5554static void mri_assemble PARAMS ((char *));
5555static char *mri_control_label PARAMS ((void));
5556static struct mri_control_info *push_mri_control
5557 PARAMS ((enum mri_control_type));
5558static void pop_mri_control PARAMS ((void));
5559static int parse_mri_condition PARAMS ((int *));
5560static int parse_mri_control_operand
5561 PARAMS ((int *, char **, char **, char **, char **));
5562static int swap_mri_condition PARAMS ((int));
5563static int reverse_mri_condition PARAMS ((int));
5564static void build_mri_control_operand
5565 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5566 const char *, int));
5567static void parse_mri_control_expression
5568 PARAMS ((char *, int, const char *, const char *, int));
5569
5570/* Assemble an instruction for an MRI structured control directive. */
5571
5572static void
5573mri_assemble (str)
5574 char *str;
5575{
5576 char *s;
5577
5578 /* md_assemble expects the opcode to be in lower case. */
5579 for (s = str; *s != ' ' && *s != '\0'; s++)
5580 {
5581 if (isupper ((unsigned char) *s))
5582 *s = tolower ((unsigned char) *s);
5583 }
5584
5585 md_assemble (str);
5586}
5587
5588/* Generate a new MRI label structured control directive label name. */
5589
5590static char *
5591mri_control_label ()
5592{
5593 char *n;
5594
5595 n = (char *) xmalloc (20);
5596 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5597 ++mri_control_index;
5598 return n;
5599}
5600
5601/* Create a new MRI structured control directive. */
5602
5603static struct mri_control_info *
5604push_mri_control (type)
5605 enum mri_control_type type;
5606{
5607 struct mri_control_info *n;
5608
5609 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5610
5611 n->type = type;
5612 n->else_seen = 0;
5613 if (type == mri_if || type == mri_while)
5614 n->top = NULL;
5615 else
5616 n->top = mri_control_label ();
5617 n->next = mri_control_label ();
5618 n->bottom = mri_control_label ();
5619
5620 n->outer = mri_control_stack;
5621 mri_control_stack = n;
5622
5623 return n;
5624}
5625
5626/* Pop off the stack of MRI structured control directives. */
5627
5628static void
5629pop_mri_control ()
5630{
5631 struct mri_control_info *n;
5632
5633 n = mri_control_stack;
5634 mri_control_stack = n->outer;
5635 if (n->top != NULL)
5636 free (n->top);
5637 free (n->next);
5638 free (n->bottom);
5639 free (n);
5640}
5641
5642/* Recognize a condition code in an MRI structured control expression. */
5643
5644static int
5645parse_mri_condition (pcc)
5646 int *pcc;
5647{
5648 char c1, c2;
5649
5650 know (*input_line_pointer == '<');
5651
5652 ++input_line_pointer;
5653 c1 = *input_line_pointer++;
5654 c2 = *input_line_pointer++;
5655
5656 if (*input_line_pointer != '>')
5657 {
5658 as_bad (_("syntax error in structured control directive"));
5659 return 0;
5660 }
5661
5662 ++input_line_pointer;
5663 SKIP_WHITESPACE ();
5664
5665 if (isupper (c1))
5666 c1 = tolower (c1);
5667 if (isupper (c2))
5668 c2 = tolower (c2);
5669
5670 *pcc = (c1 << 8) | c2;
5671
5672 return 1;
5673}
5674
5675/* Parse a single operand in an MRI structured control expression. */
5676
5677static int
5678parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5679 int *pcc;
5680 char **leftstart;
5681 char **leftstop;
5682 char **rightstart;
5683 char **rightstop;
5684{
5685 char *s;
5686
5687 SKIP_WHITESPACE ();
5688
5689 *pcc = -1;
5690 *leftstart = NULL;
5691 *leftstop = NULL;
5692 *rightstart = NULL;
5693 *rightstop = NULL;
5694
5695 if (*input_line_pointer == '<')
5696 {
5697 /* It's just a condition code. */
5698 return parse_mri_condition (pcc);
5699 }
5700
5701 /* Look ahead for the condition code. */
5702 for (s = input_line_pointer; *s != '\0'; ++s)
5703 {
5704 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5705 break;
5706 }
5707 if (*s == '\0')
5708 {
5709 as_bad (_("missing condition code in structured control directive"));
5710 return 0;
5711 }
5712
5713 *leftstart = input_line_pointer;
5714 *leftstop = s;
5715 if (*leftstop > *leftstart
5716 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5717 --*leftstop;
5718
5719 input_line_pointer = s;
5720 if (! parse_mri_condition (pcc))
5721 return 0;
5722
5723 /* Look ahead for AND or OR or end of line. */
5724 for (s = input_line_pointer; *s != '\0'; ++s)
5725 {
5726 if ((strncasecmp (s, "AND", 3) == 0
5727 && (s[3] == '.' || ! is_part_of_name (s[3])))
5728 || (strncasecmp (s, "OR", 2) == 0
5729 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5730 break;
5731 }
5732
5733 *rightstart = input_line_pointer;
5734 *rightstop = s;
5735 if (*rightstop > *rightstart
5736 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5737 --*rightstop;
5738
5739 input_line_pointer = s;
5740
5741 return 1;
5742}
5743
5744#define MCC(b1, b2) (((b1) << 8) | (b2))
5745
5746/* Swap the sense of a condition. This changes the condition so that
5747 it generates the same result when the operands are swapped. */
5748
5749static int
5750swap_mri_condition (cc)
5751 int cc;
5752{
5753 switch (cc)
5754 {
5755 case MCC ('h', 'i'): return MCC ('c', 's');
5756 case MCC ('l', 's'): return MCC ('c', 'c');
5757 case MCC ('c', 'c'): return MCC ('l', 's');
5758 case MCC ('c', 's'): return MCC ('h', 'i');
5759 case MCC ('p', 'l'): return MCC ('m', 'i');
5760 case MCC ('m', 'i'): return MCC ('p', 'l');
5761 case MCC ('g', 'e'): return MCC ('l', 'e');
5762 case MCC ('l', 't'): return MCC ('g', 't');
5763 case MCC ('g', 't'): return MCC ('l', 't');
5764 case MCC ('l', 'e'): return MCC ('g', 'e');
5765 }
5766 return cc;
5767}
5768
5769/* Reverse the sense of a condition. */
5770
5771static int
5772reverse_mri_condition (cc)
5773 int cc;
5774{
5775 switch (cc)
5776 {
5777 case MCC ('h', 'i'): return MCC ('l', 's');
5778 case MCC ('l', 's'): return MCC ('h', 'i');
5779 case MCC ('c', 'c'): return MCC ('c', 's');
5780 case MCC ('c', 's'): return MCC ('c', 'c');
5781 case MCC ('n', 'e'): return MCC ('e', 'q');
5782 case MCC ('e', 'q'): return MCC ('n', 'e');
5783 case MCC ('v', 'c'): return MCC ('v', 's');
5784 case MCC ('v', 's'): return MCC ('v', 'c');
5785 case MCC ('p', 'l'): return MCC ('m', 'i');
5786 case MCC ('m', 'i'): return MCC ('p', 'l');
5787 case MCC ('g', 'e'): return MCC ('l', 't');
5788 case MCC ('l', 't'): return MCC ('g', 'e');
5789 case MCC ('g', 't'): return MCC ('l', 'e');
5790 case MCC ('l', 'e'): return MCC ('g', 't');
5791 }
5792 return cc;
5793}
5794
5795/* Build an MRI structured control expression. This generates test
5796 and branch instructions. It goes to TRUELAB if the condition is
5797 true, and to FALSELAB if the condition is false. Exactly one of
5798 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5799 is the size qualifier for the expression. EXTENT is the size to
5800 use for the branch. */
5801
5802static void
5803build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5804 rightstop, truelab, falselab, extent)
5805 int qual;
5806 int cc;
5807 char *leftstart;
5808 char *leftstop;
5809 char *rightstart;
5810 char *rightstop;
5811 const char *truelab;
5812 const char *falselab;
5813 int extent;
5814{
5815 char *buf;
5816 char *s;
5817
5818 if (leftstart != NULL)
5819 {
5820 struct m68k_op leftop, rightop;
5821 char c;
5822
5823 /* Swap the compare operands, if necessary, to produce a legal
5824 m68k compare instruction. Comparing a register operand with
5825 a non-register operand requires the register to be on the
5826 right (cmp, cmpa). Comparing an immediate value with
5827 anything requires the immediate value to be on the left
5828 (cmpi). */
5829
5830 c = *leftstop;
5831 *leftstop = '\0';
5832 (void) m68k_ip_op (leftstart, &leftop);
5833 *leftstop = c;
5834
5835 c = *rightstop;
5836 *rightstop = '\0';
5837 (void) m68k_ip_op (rightstart, &rightop);
5838 *rightstop = c;
5839
5840 if (rightop.mode == IMMED
5841 || ((leftop.mode == DREG || leftop.mode == AREG)
5842 && (rightop.mode != DREG && rightop.mode != AREG)))
5843 {
5844 char *temp;
5845
5846 cc = swap_mri_condition (cc);
5847 temp = leftstart;
5848 leftstart = rightstart;
5849 rightstart = temp;
5850 temp = leftstop;
5851 leftstop = rightstop;
5852 rightstop = temp;
5853 }
5854 }
5855
5856 if (truelab == NULL)
5857 {
5858 cc = reverse_mri_condition (cc);
5859 truelab = falselab;
5860 }
92774660 5861
252b5132
RH		 5862 if (leftstart != NULL)
5863 {
5864 buf = (char *) xmalloc (20
5865 + (leftstop - leftstart)
5866 + (rightstop - rightstart));
5867 s = buf;
5868 *s++ = 'c';
5869 *s++ = 'm';
5870 *s++ = 'p';
5871 if (qual != '\0')
5872 *s++ = qual;
5873 *s++ = ' ';
5874 memcpy (s, leftstart, leftstop - leftstart);
5875 s += leftstop - leftstart;
5876 *s++ = ',';
5877 memcpy (s, rightstart, rightstop - rightstart);
5878 s += rightstop - rightstart;
5879 *s = '\0';
5880 mri_assemble (buf);
5881 free (buf);
5882 }
92774660 5883
252b5132
RH		 5884 buf = (char *) xmalloc (20 + strlen (truelab));
5885 s = buf;
5886 *s++ = 'b';
5887 *s++ = cc >> 8;
5888 *s++ = cc & 0xff;
5889 if (extent != '\0')
5890 *s++ = extent;
5891 *s++ = ' ';
5892 strcpy (s, truelab);
5893 mri_assemble (buf);
5894 free (buf);
5895}
5896
5897/* Parse an MRI structured control expression. This generates test
5898 and branch instructions. STOP is where the expression ends. It
5899 goes to TRUELAB if the condition is true, and to FALSELAB if the
5900 condition is false. Exactly one of TRUELAB and FALSELAB will be
5901 NULL, meaning to fall through. QUAL is the size qualifier for the
5902 expression. EXTENT is the size to use for the branch. */
5903
5904static void
5905parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5906 char *stop;
5907 int qual;
5908 const char *truelab;
5909 const char *falselab;
5910 int extent;
5911{
5912 int c;
5913 int cc;
5914 char *leftstart;
5915 char *leftstop;
5916 char *rightstart;
5917 char *rightstop;
5918
5919 c = *stop;
5920 *stop = '\0';
5921
5922 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5923 &rightstart, &rightstop))
5924 {
5925 *stop = c;
5926 return;
5927 }
5928
5929 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5930 {
5931 const char *flab;
5932
5933 if (falselab != NULL)
5934 flab = falselab;
5935 else
5936 flab = mri_control_label ();
5937
5938 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5939 rightstop, (const char *) NULL, flab, extent);
5940
5941 input_line_pointer += 3;
5942 if (*input_line_pointer != '.'
5943 || input_line_pointer[1] == '\0')
5944 qual = '\0';
5945 else
5946 {
5947 qual = input_line_pointer[1];
5948 input_line_pointer += 2;
5949 }
5950
5951 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5952 &rightstart, &rightstop))
5953 {
5954 *stop = c;
5955 return;
5956 }
5957
5958 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5959 rightstop, truelab, falselab, extent);
5960
5961 if (falselab == NULL)
5962 colon (flab);
5963 }
5964 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5965 {
5966 const char *tlab;
5967
5968 if (truelab != NULL)
5969 tlab = truelab;
5970 else
5971 tlab = mri_control_label ();
5972
5973 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5974 rightstop, tlab, (const char *) NULL, extent);
5975
5976 input_line_pointer += 2;
5977 if (*input_line_pointer != '.'
5978 || input_line_pointer[1] == '\0')
5979 qual = '\0';
5980 else
5981 {
5982 qual = input_line_pointer[1];
5983 input_line_pointer += 2;
5984 }
5985
5986 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5987 &rightstart, &rightstop))
5988 {
5989 *stop = c;
5990 return;
5991 }
5992
5993 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5994 rightstop, truelab, falselab, extent);
5995
5996 if (truelab == NULL)
5997 colon (tlab);
5998 }
5999 else
6000 {
6001 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6002 rightstop, truelab, falselab, extent);
6003 }
6004
6005 *stop = c;
6006 if (input_line_pointer != stop)
6007 as_bad (_("syntax error in structured control directive"));
6008}
6009
6010/* Handle the MRI IF pseudo-op. This may be a structured control
6011 directive, or it may be a regular assembler conditional, depending
6012 on its operands. */
6013
6014static void
6015s_mri_if (qual)
6016 int qual;
6017{
6018 char *s;
6019 int c;
6020 struct mri_control_info *n;
6021
6022 /* A structured control directive must end with THEN with an
6023 optional qualifier. */
6024 s = input_line_pointer;
6025 while (! is_end_of_line[(unsigned char) *s]
6026 && (! flag_mri || *s != '*'))
6027 ++s;
6028 --s;
6029 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6030 --s;
6031
6032 if (s - input_line_pointer > 1
6033 && s[-1] == '.')
6034 s -= 2;
6035
6036 if (s - input_line_pointer < 3
6037 || strncasecmp (s - 3, "THEN", 4) != 0)
6038 {
6039 if (qual != '\0')
6040 {
6041 as_bad (_("missing then"));
6042 ignore_rest_of_line ();
6043 return;
6044 }
6045
6046 /* It's a conditional. */
6047 s_if (O_ne);
6048 return;
6049 }
6050
6051 /* Since this might be a conditional if, this pseudo-op will be
6052 called even if we are supported to be ignoring input. Double
6053 check now. Clobber *input_line_pointer so that ignore_input
6054 thinks that this is not a special pseudo-op. */
6055 c = *input_line_pointer;
6056 *input_line_pointer = 0;
6057 if (ignore_input ())
6058 {
6059 *input_line_pointer = c;
6060 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6061 ++input_line_pointer;
6062 demand_empty_rest_of_line ();
6063 return;
6064 }
6065 *input_line_pointer = c;
6066
6067 n = push_mri_control (mri_if);
6068
6069 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6070 n->next, s[1] == '.' ? s[2] : '\0');
6071
6072 if (s[1] == '.')
6073 input_line_pointer = s + 3;
6074 else
6075 input_line_pointer = s + 1;
6076
6077 if (flag_mri)
6078 {
6079 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6080 ++input_line_pointer;
6081 }
6082
6083 demand_empty_rest_of_line ();
6084}
6085
6086/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6087 structured IF, associate the ELSE with the IF. Otherwise, assume
6088 it is a conditional else. */
6089
6090static void
6091s_mri_else (qual)
6092 int qual;
6093{
6094 int c;
6095 char *buf;
6096 char q[2];
6097
6098 if (qual == '\0'
6099 && (mri_control_stack == NULL
6100 || mri_control_stack->type != mri_if
6101 || mri_control_stack->else_seen))
6102 {
6103 s_else (0);
6104 return;
6105 }
6106
6107 c = *input_line_pointer;
6108 *input_line_pointer = 0;
6109 if (ignore_input ())
6110 {
6111 *input_line_pointer = c;
6112 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6113 ++input_line_pointer;
6114 demand_empty_rest_of_line ();
6115 return;
6116 }
6117 *input_line_pointer = c;
6118
6119 if (mri_control_stack == NULL
6120 || mri_control_stack->type != mri_if
6121 || mri_control_stack->else_seen)
6122 {
6123 as_bad (_("else without matching if"));
6124 ignore_rest_of_line ();
6125 return;
6126 }
6127
6128 mri_control_stack->else_seen = 1;
6129
6130 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6131 q[0] = qual;
6132 q[1] = '\0';
6133 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6134 mri_assemble (buf);
6135 free (buf);
6136
6137 colon (mri_control_stack->next);
6138
6139 if (flag_mri)
6140 {
6141 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6142 ++input_line_pointer;
6143 }
6144
6145 demand_empty_rest_of_line ();
6146}
6147
6148/* Handle the MRI ENDI pseudo-op. */
6149
6150static void
6151s_mri_endi (ignore)
36823076 6152 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6153{
6154 if (mri_control_stack == NULL
6155 || mri_control_stack->type != mri_if)
6156 {
6157 as_bad (_("endi without matching if"));
6158 ignore_rest_of_line ();
6159 return;
6160 }
6161
6162 /* ignore_input will not return true for ENDI, so we don't need to
6163 worry about checking it again here. */
6164
6165 if (! mri_control_stack->else_seen)
6166 colon (mri_control_stack->next);
6167 colon (mri_control_stack->bottom);
6168
6169 pop_mri_control ();
6170
6171 if (flag_mri)
6172 {
6173 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6174 ++input_line_pointer;
6175 }
6176
6177 demand_empty_rest_of_line ();
6178}
6179
6180/* Handle the MRI BREAK pseudo-op. */
6181
6182static void
6183s_mri_break (extent)
6184 int extent;
6185{
6186 struct mri_control_info *n;
6187 char *buf;
6188 char ex[2];
6189
6190 n = mri_control_stack;
6191 while (n != NULL
6192 && n->type != mri_for
6193 && n->type != mri_repeat
6194 && n->type != mri_while)
6195 n = n->outer;
6196 if (n == NULL)
6197 {
6198 as_bad (_("break outside of structured loop"));
6199 ignore_rest_of_line ();
6200 return;
6201 }
6202
6203 buf = (char *) xmalloc (20 + strlen (n->bottom));
6204 ex[0] = extent;
6205 ex[1] = '\0';
6206 sprintf (buf, "bra%s %s", ex, n->bottom);
6207 mri_assemble (buf);
6208 free (buf);
6209
6210 if (flag_mri)
6211 {
6212 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6213 ++input_line_pointer;
6214 }
6215
6216 demand_empty_rest_of_line ();
6217}
6218
6219/* Handle the MRI NEXT pseudo-op. */
6220
6221static void
6222s_mri_next (extent)
6223 int extent;
6224{
6225 struct mri_control_info *n;
6226 char *buf;
6227 char ex[2];
6228
6229 n = mri_control_stack;
6230 while (n != NULL
6231 && n->type != mri_for
6232 && n->type != mri_repeat
6233 && n->type != mri_while)
6234 n = n->outer;
6235 if (n == NULL)
6236 {
6237 as_bad (_("next outside of structured loop"));
6238 ignore_rest_of_line ();
6239 return;
6240 }
6241
6242 buf = (char *) xmalloc (20 + strlen (n->next));
6243 ex[0] = extent;
6244 ex[1] = '\0';
6245 sprintf (buf, "bra%s %s", ex, n->next);
6246 mri_assemble (buf);
6247 free (buf);
6248
6249 if (flag_mri)
6250 {
6251 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6252 ++input_line_pointer;
6253 }
6254
6255 demand_empty_rest_of_line ();
6256}
6257
6258/* Handle the MRI FOR pseudo-op. */
6259
6260static void
6261s_mri_for (qual)
6262 int qual;
6263{
6264 const char *varstart, *varstop;
6265 const char *initstart, *initstop;
6266 const char *endstart, *endstop;
6267 const char *bystart, *bystop;
6268 int up;
6269 int by;
6270 int extent;
6271 struct mri_control_info *n;
6272 char *buf;
6273 char *s;
6274 char ex[2];
6275
6276 /* The syntax is
6277 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6278 */
6279
6280 SKIP_WHITESPACE ();
6281 varstart = input_line_pointer;
6282
6283 /* Look for the '='. */
6284 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6285 && *input_line_pointer != '=')
6286 ++input_line_pointer;
6287 if (*input_line_pointer != '=')
6288 {
6289 as_bad (_("missing ="));
6290 ignore_rest_of_line ();
6291 return;
6292 }
6293
6294 varstop = input_line_pointer;
6295 if (varstop > varstart
6296 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6297 --varstop;
6298
6299 ++input_line_pointer;
6300
6301 initstart = input_line_pointer;
6302
6303 /* Look for TO or DOWNTO. */
6304 up = 1;
6305 initstop = NULL;
6306 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6307 {
6308 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6309 && ! is_part_of_name (input_line_pointer[2]))
6310 {
6311 initstop = input_line_pointer;
6312 input_line_pointer += 2;
6313 break;
6314 }
6315 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6316 && ! is_part_of_name (input_line_pointer[6]))
6317 {
6318 initstop = input_line_pointer;
6319 up = 0;
6320 input_line_pointer += 6;
6321 break;
6322 }
6323 ++input_line_pointer;
6324 }
6325 if (initstop == NULL)
6326 {
6327 as_bad (_("missing to or downto"));
6328 ignore_rest_of_line ();
6329 return;
6330 }
6331 if (initstop > initstart
6332 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6333 --initstop;
6334
6335 SKIP_WHITESPACE ();
6336 endstart = input_line_pointer;
6337
6338 /* Look for BY or DO. */
6339 by = 0;
6340 endstop = NULL;
6341 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6342 {
6343 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6344 && ! is_part_of_name (input_line_pointer[2]))
6345 {
6346 endstop = input_line_pointer;
6347 by = 1;
6348 input_line_pointer += 2;
6349 break;
6350 }
6351 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6352 && (input_line_pointer[2] == '.'
6353 || ! is_part_of_name (input_line_pointer[2])))
6354 {
6355 endstop = input_line_pointer;
6356 input_line_pointer += 2;
6357 break;
6358 }
6359 ++input_line_pointer;
6360 }
6361 if (endstop == NULL)
6362 {
6363 as_bad (_("missing do"));
6364 ignore_rest_of_line ();
6365 return;
6366 }
6367 if (endstop > endstart
6368 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6369 --endstop;
6370
6371 if (! by)
6372 {
6373 bystart = "#1";
6374 bystop = bystart + 2;
6375 }
6376 else
6377 {
6378 SKIP_WHITESPACE ();
6379 bystart = input_line_pointer;
6380
6381 /* Look for DO. */
6382 bystop = NULL;
6383 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6384 {
6385 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6386 && (input_line_pointer[2] == '.'
6387 || ! is_part_of_name (input_line_pointer[2])))
6388 {
6389 bystop = input_line_pointer;
6390 input_line_pointer += 2;
6391 break;
6392 }
6393 ++input_line_pointer;
6394 }
6395 if (bystop == NULL)
6396 {
6397 as_bad (_("missing do"));
6398 ignore_rest_of_line ();
6399 return;
6400 }
6401 if (bystop > bystart
6402 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6403 --bystop;
6404 }
6405
6406 if (*input_line_pointer != '.')
6407 extent = '\0';
6408 else
6409 {
6410 extent = input_line_pointer[1];
6411 input_line_pointer += 2;
6412 }
6413
6414 /* We have fully parsed the FOR operands. Now build the loop. */
6415
6416 n = push_mri_control (mri_for);
6417
6418 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6419
6420 /* move init,var */
6421 s = buf;
6422 *s++ = 'm';
6423 *s++ = 'o';
6424 *s++ = 'v';
6425 *s++ = 'e';
6426 if (qual != '\0')
6427 *s++ = qual;
6428 *s++ = ' ';
6429 memcpy (s, initstart, initstop - initstart);
6430 s += initstop - initstart;
6431 *s++ = ',';
6432 memcpy (s, varstart, varstop - varstart);
6433 s += varstop - varstart;
6434 *s = '\0';
6435 mri_assemble (buf);
6436
6437 colon (n->top);
6438
6439 /* cmp end,var */
6440 s = buf;
6441 *s++ = 'c';
6442 *s++ = 'm';
6443 *s++ = 'p';
6444 if (qual != '\0')
6445 *s++ = qual;
6446 *s++ = ' ';
6447 memcpy (s, endstart, endstop - endstart);
6448 s += endstop - endstart;
6449 *s++ = ',';
6450 memcpy (s, varstart, varstop - varstart);
6451 s += varstop - varstart;
6452 *s = '\0';
6453 mri_assemble (buf);
6454
6455 /* bcc bottom */
6456 ex[0] = extent;
6457 ex[1] = '\0';
6458 if (up)
6459 sprintf (buf, "blt%s %s", ex, n->bottom);
6460 else
6461 sprintf (buf, "bgt%s %s", ex, n->bottom);
6462 mri_assemble (buf);
6463
6464 /* Put together the add or sub instruction used by ENDF. */
6465 s = buf;
6466 if (up)
6467 strcpy (s, "add");
6468 else
6469 strcpy (s, "sub");
6470 s += 3;
6471 if (qual != '\0')
6472 *s++ = qual;
6473 *s++ = ' ';
6474 memcpy (s, bystart, bystop - bystart);
6475 s += bystop - bystart;
6476 *s++ = ',';
6477 memcpy (s, varstart, varstop - varstart);
6478 s += varstop - varstart;
6479 *s = '\0';
6480 n->incr = buf;
6481
6482 if (flag_mri)
6483 {
6484 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6485 ++input_line_pointer;
6486 }
6487
6488 demand_empty_rest_of_line ();
6489}
6490
6491/* Handle the MRI ENDF pseudo-op. */
6492
6493static void
6494s_mri_endf (ignore)
36823076 6495 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6496{
6497 if (mri_control_stack == NULL
6498 || mri_control_stack->type != mri_for)
6499 {
6500 as_bad (_("endf without for"));
6501 ignore_rest_of_line ();
6502 return;
6503 }
6504
6505 colon (mri_control_stack->next);
6506
6507 mri_assemble (mri_control_stack->incr);
6508
6509 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6510 mri_assemble (mri_control_stack->incr);
6511
6512 free (mri_control_stack->incr);
6513
6514 colon (mri_control_stack->bottom);
6515
6516 pop_mri_control ();
6517
6518 if (flag_mri)
6519 {
6520 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6521 ++input_line_pointer;
6522 }
6523
6524 demand_empty_rest_of_line ();
6525}
6526
6527/* Handle the MRI REPEAT pseudo-op. */
6528
6529static void
6530s_mri_repeat (ignore)
36823076 6531 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6532{
6533 struct mri_control_info *n;
6534
6535 n = push_mri_control (mri_repeat);
6536 colon (n->top);
6537 if (flag_mri)
6538 {
6539 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6540 ++input_line_pointer;
6541 }
6542 demand_empty_rest_of_line ();
6543}
6544
6545/* Handle the MRI UNTIL pseudo-op. */
6546
6547static void
6548s_mri_until (qual)
6549 int qual;
6550{
6551 char *s;
6552
6553 if (mri_control_stack == NULL
6554 || mri_control_stack->type != mri_repeat)
6555 {
6556 as_bad (_("until without repeat"));
6557 ignore_rest_of_line ();
6558 return;
6559 }
6560
6561 colon (mri_control_stack->next);
6562
6563 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6564 ;
6565
6566 parse_mri_control_expression (s, qual, (const char *) NULL,
6567 mri_control_stack->top, '\0');
6568
6569 colon (mri_control_stack->bottom);
6570
6571 input_line_pointer = s;
6572
6573 pop_mri_control ();
6574
6575 if (flag_mri)
6576 {
6577 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6578 ++input_line_pointer;
6579 }
6580
6581 demand_empty_rest_of_line ();
6582}
6583
6584/* Handle the MRI WHILE pseudo-op. */
6585
6586static void
6587s_mri_while (qual)
6588 int qual;
6589{
6590 char *s;
6591
6592 struct mri_control_info *n;
6593
6594 s = input_line_pointer;
6595 while (! is_end_of_line[(unsigned char) *s]
6596 && (! flag_mri || *s != '*'))
6597 s++;
6598 --s;
6599 while (*s == ' ' || *s == '\t')
6600 --s;
6601 if (s - input_line_pointer > 1
6602 && s[-1] == '.')
6603 s -= 2;
6604 if (s - input_line_pointer < 2
6605 || strncasecmp (s - 1, "DO", 2) != 0)
6606 {
6607 as_bad (_("missing do"));
6608 ignore_rest_of_line ();
6609 return;
6610 }
6611
6612 n = push_mri_control (mri_while);
6613
6614 colon (n->next);
6615
6616 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6617 s[1] == '.' ? s[2] : '\0');
6618
6619 input_line_pointer = s + 1;
6620 if (*input_line_pointer == '.')
6621 input_line_pointer += 2;
6622
6623 if (flag_mri)
6624 {
6625 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6626 ++input_line_pointer;
6627 }
6628
6629 demand_empty_rest_of_line ();
6630}
6631
6632/* Handle the MRI ENDW pseudo-op. */
6633
6634static void
6635s_mri_endw (ignore)
36823076 6636 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6637{
6638 char *buf;
6639
6640 if (mri_control_stack == NULL
6641 || mri_control_stack->type != mri_while)
6642 {
6643 as_bad (_("endw without while"));
6644 ignore_rest_of_line ();
6645 return;
6646 }
6647
6648 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6649 sprintf (buf, "bra %s", mri_control_stack->next);
6650 mri_assemble (buf);
6651 free (buf);
6652
6653 colon (mri_control_stack->bottom);
6654
6655 pop_mri_control ();
6656
6657 if (flag_mri)
6658 {
6659 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6660 ++input_line_pointer;
6661 }
6662
6663 demand_empty_rest_of_line ();
6664}
6665\f
6666/*
6667 * md_parse_option
6668 * Invocation line includes a switch not recognized by the base assembler.
6669 * See if it's a processor-specific option. These are:
6670 *
6671 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6672 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6673 * Select the architecture. Instructions or features not
6674 * supported by the selected architecture cause fatal
6675 * errors. More than one may be specified. The default is
6676 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6677 * for -m68000, and -m68882 is a synonym for -m68881.
6678 * -[A]m[c]no-68851, -[A]m[c]no-68881
6679 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6680 * so don't use or document it, but that's the way the parsing
6681 * works).
6682 *
6683 * -pic Indicates PIC.
6684 * -k Indicates PIC. (Sun 3 only.)
28e7409f 6685 * --pcrel Never turn PC-relative branches into absolute jumps.
252b5132
RH		 6686 *
6687 * --bitwise-or
6688 * Permit `|' to be used in expressions.
6689 *
6690 */
6691
6692#ifdef OBJ_ELF
6693CONST char *md_shortopts = "lSA:m:kQ:V";
6694#else
6695CONST char *md_shortopts = "lSA:m:k";
6696#endif
6697
6698struct option md_longopts[] = {
6699#define OPTION_PIC (OPTION_MD_BASE)
6700 {"pic", no_argument, NULL, OPTION_PIC},
6701#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6702 {"register-prefix-optional", no_argument, NULL,
6703 OPTION_REGISTER_PREFIX_OPTIONAL},
6704#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6705 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6706#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6707 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6708#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6709 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6710#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6711 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6712#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6713 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 6714#define OPTION_PCREL (OPTION_MD_BASE + 7)
6715 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 6716 {NULL, no_argument, NULL, 0}
6717};
bc805888 6718size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 6719
6720int
6721md_parse_option (c, arg)
6722 int c;
6723 char *arg;
6724{
6725 switch (c)
6726 {
6727 case 'l': /* -l means keep external to 2 bit offset
6728 rather than 16 bit one */
6729 flag_short_refs = 1;
6730 break;
6731
6732 case 'S': /* -S means that jbsr's always turn into
6733 jsr's. */
6734 flag_long_jumps = 1;
6735 break;
6736
28e7409f
NC		 6737 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6738 branches into absolute jumps. */
6739 flag_keep_pcrel = 1;
6740 break;
6741
252b5132
RH		 6742 case 'A':
6743 if (*arg == 'm')
6744 arg++;
6745 /* intentional fall-through */
6746 case 'm':
6747
6748 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6749 {
6750 int i;
6751 unsigned long arch;
6752 const char *oarg = arg;
6753
6754 arg += 3;
6755 if (*arg == 'm')
6756 {
6757 arg++;
6758 if (arg[0] == 'c' && arg[1] == '6')
6759 arg++;
6760 }
6761 for (i = 0; i < n_archs; i++)
6762 if (!strcmp (arg, archs[i].name))
6763 break;
6764 if (i == n_archs)
6765 {
6766 unknown:
6767 as_bad (_("unrecognized option `%s'"), oarg);
6768 return 0;
6769 }
6770 arch = archs[i].arch;
6771 if (arch == m68881)
6772 no_68881 = 1;
6773 else if (arch == m68851)
6774 no_68851 = 1;
6775 else
6776 goto unknown;
6777 }
6778 else
6779 {
6780 int i;
6781
6782 if (arg[0] == 'c' && arg[1] == '6')
6783 arg++;
6784
6785 for (i = 0; i < n_archs; i++)
6786 if (!strcmp (arg, archs[i].name))
6787 {
6788 unsigned long arch = archs[i].arch;
6789 if (cpu_of_arch (arch))
6790 /* It's a cpu spec. */
6791 {
6792 current_architecture &= ~m68000up;
6793 current_architecture |= arch;
6794 }
6795 else if (arch == m68881)
6796 {
6797 current_architecture |= m68881;
6798 no_68881 = 0;
6799 }
6800 else if (arch == m68851)
6801 {
6802 current_architecture |= m68851;
6803 no_68851 = 0;
6804 }
6805 else
6806 /* ??? */
6807 abort ();
6808 break;
6809 }
6810 if (i == n_archs)
6811 {
6812 as_bad (_("unrecognized architecture specification `%s'"), arg);
6813 return 0;
6814 }
6815 }
6816 break;
6817
6818 case OPTION_PIC:
6819 case 'k':
6820 flag_want_pic = 1;
6821 break; /* -pic, Position Independent Code */
6822
6823 case OPTION_REGISTER_PREFIX_OPTIONAL:
6824 flag_reg_prefix_optional = 1;
6825 reg_prefix_optional_seen = 1;
6826 break;
6827
6828 /* -V: SVR4 argument to print version ID. */
6829 case 'V':
6830 print_version_id ();
6831 break;
6832
6833 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6834 should be emitted or not. FIXME: Not implemented. */
6835 case 'Q':
6836 break;
6837
6838 case OPTION_BITWISE_OR:
6839 {
6840 char *n, *t;
6841 const char *s;
6842
6843 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6844 t = n;
6845 for (s = m68k_comment_chars; *s != '\0'; s++)
6846 if (*s != '|')
6847 *t++ = *s;
6848 *t = '\0';
6849 m68k_comment_chars = n;
6850 }
6851 break;
6852
6853 case OPTION_BASE_SIZE_DEFAULT_16:
6854 m68k_index_width_default = SIZE_WORD;
6855 break;
6856
6857 case OPTION_BASE_SIZE_DEFAULT_32:
6858 m68k_index_width_default = SIZE_LONG;
6859 break;
6860
6861 case OPTION_DISP_SIZE_DEFAULT_16:
6862 m68k_rel32 = 0;
6863 m68k_rel32_from_cmdline = 1;
6864 break;
6865
6866 case OPTION_DISP_SIZE_DEFAULT_32:
6867 m68k_rel32 = 1;
6868 m68k_rel32_from_cmdline = 1;
6869 break;
6870
6871 default:
6872 return 0;
6873 }
6874
6875 return 1;
6876}
6877
6878void
6879md_show_usage (stream)
6880 FILE *stream;
6881{
bc805888 6882 fprintf (stream, _("\
252b5132
RH		 6883680X0 options:\n\
6884-l use 1 word for refs to undefined symbols [default 2]\n\
6885-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6886 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6887 | -mcpu32 | -m5200\n\
6888 specify variant of 680X0 architecture [default 68020]\n\
6889-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6890 target has/lacks floating-point coprocessor\n\
6891 [default yes for 68020, 68030, and cpu32]\n"));
bc805888 6892 fprintf (stream, _("\
252b5132
RH		 6893-m68851 | -mno-68851\n\
6894 target has/lacks memory-management unit coprocessor\n\
6895 [default yes for 68020 and up]\n\
6896-pic, -k generate position independent code\n\
6897-S turn jbsr into jsr\n\
28e7409f 6898--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 6899--register-prefix-optional\n\
6900 recognize register names without prefix character\n\
6901--bitwise-or do not treat `|' as a comment character\n"));
6902 fprintf (stream, _("\
6903--base-size-default-16 base reg without size is 16 bits\n\
6904--base-size-default-32 base reg without size is 32 bits (default)\n\
6905--disp-size-default-16 displacement with unknown size is 16 bits\n\
6906--disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6907}
6908\f
6909#ifdef TEST2
6910
6911/* TEST2: Test md_assemble() */
6912/* Warning, this routine probably doesn't work anymore */
6913
6914main ()
6915{
6916 struct m68k_it the_ins;
6917 char buf[120];
6918 char *cp;
6919 int n;
6920
6921 m68k_ip_begin ();
6922 for (;;)
6923 {
6924 if (!gets (buf) || !*buf)
6925 break;
6926 if (buf[0] == '|' || buf[1] == '.')
6927 continue;
6928 for (cp = buf; *cp; cp++)
6929 if (*cp == '\t')
6930 *cp = ' ';
6931 if (is_label (buf))
6932 continue;
6933 memset (&the_ins, '\0', sizeof (the_ins));
6934 m68k_ip (&the_ins, buf);
6935 if (the_ins.error)
6936 {
6937 printf (_("Error %s in %s\n"), the_ins.error, buf);
6938 }
6939 else
6940 {
6941 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
6942 for (n = 0; n < the_ins.numo; n++)
6943 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6944 printf (" ");
6945 print_the_insn (&the_ins.opcode[0], stdout);
6946 (void) putchar ('\n');
6947 }
6948 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6949 {
6950 if (the_ins.operands[n].error)
6951 {
6952 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6953 continue;
6954 }
6955 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6956 if (the_ins.operands[n].b_const)
6957 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6958 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6959 if (the_ins.operands[n].b_iadd)
6960 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6961 (void) putchar ('\n');
6962 }
6963 }
6964 m68k_ip_end ();
6965 return 0;
6966}
6967
6968is_label (str)
6969 char *str;
6970{
6971 while (*str == ' ')
6972 str++;
6973 while (*str && *str != ' ')
6974 str++;
6975 if (str[-1] == ':' || str[1] == '=')
6976 return 1;
6977 return 0;
6978}
6979
6980#endif
6981
6982/* Possible states for relaxation:
6983
6984 0 0 branch offset byte (bra, etc)
6985 0 1 word
6986 0 2 long
6987
6988 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6989 1 1 word
6990 1 2 long
6991
6992 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6993 2 1 word-long
6994 2 2 long-word
6995 2 3 long-long
6996
6997 */
6998
6999/* We have no need to default values of symbols. */
7000
252b5132
RH		 7001symbolS *
7002md_undefined_symbol (name)
36823076 7003 char *name ATTRIBUTE_UNUSED;
252b5132
RH		 7004{
7005 return 0;
7006}
7007
7008/* Round up a section size to the appropriate boundary. */
7009valueT
7010md_section_align (segment, size)
36823076 7011 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7012 valueT size;
7013{
7014#ifdef OBJ_AOUT
7015#ifdef BFD_ASSEMBLER
7016 /* For a.out, force the section size to be aligned. If we don't do
7017 this, BFD will align it for us, but it will not write out the
7018 final bytes of the section. This may be a bug in BFD, but it is
7019 easier to fix it here since that is how the other a.out targets
7020 work. */
7021 int align;
7022
7023 align = bfd_get_section_alignment (stdoutput, segment);
7024 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7025#endif
7026#endif
7027
7028 return size;
7029}
7030
7031/* Exactly what point is a PC-relative offset relative TO?
7032 On the 68k, it is relative to the address of the first extension
7033 word. The difference between the addresses of the offset and the
92774660 7034 first extension word is stored in fx_pcrel_adjust. */
252b5132
RH		 7035long
7036md_pcrel_from (fixP)
7037 fixS *fixP;
7038{
7039 int adjust;
7040
8390138c
AS		 7041 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7042 sign extend the value here. */
7043 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7044 if (adjust == 64)
7045 adjust = -1;
7046 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7047}
7048
7049#ifndef BFD_ASSEMBLER
7050#ifdef OBJ_COFF
7051
252b5132
RH		 7052void
7053tc_coff_symbol_emit_hook (ignore)
8fce3f5e 7054 symbolS *ignore ATTRIBUTE_UNUSED;
252b5132
RH		 7055{
7056}
7057
7058int
7059tc_coff_sizemachdep (frag)
7060 fragS *frag;
7061{
7062 switch (frag->fr_subtype & 0x3)
7063 {
7064 case BYTE:
7065 return 1;
7066 case SHORT:
7067 return 2;
7068 case LONG:
7069 return 4;
7070 default:
7071 abort ();
7072 return 0;
7073 }
7074}
7075
7076#endif
7077#endif
0d96863f
CM		 7078#ifdef OBJ_ELF
7079void m68k_elf_final_processing()
7080{
7081 /* Set file-specific flags if this is a cpu32 processor */
7082 if (cpu_of_arch (current_architecture) & cpu32)
7083 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7084}
7085#endif
GDB Binutils - Deliverables
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