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Fix breakage from 2000-03-31 bfd/srec.c change.
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
CommitLineData
252b5132 1/* tc-m68k.c -- Assemble for the m68k family
6da466c7 2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 97, 98, 1999
252b5132
RH		 3 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22#include <ctype.h>
23#include "as.h"
24#include "obstack.h"
25#include "subsegs.h"
26
27#include "opcode/m68k.h"
28#include "m68k-parse.h"
29
0d96863f
CM		 30#if defined (OBJ_ELF)
31#include "elf/m68k.h"
32#endif
33
252b5132
RH		 34/* This string holds the chars that always start a comment. If the
35 pre-processor is disabled, these aren't very useful. The macro
36 tc_comment_chars points to this. We use this, rather than the
37 usual comment_chars, so that the --bitwise-or option will work. */
38#if defined (TE_SVR4) || defined (TE_DELTA)
39const char *m68k_comment_chars = "|#";
40#else
41const char *m68k_comment_chars = "|";
42#endif
43
44/* This array holds the chars that only start a comment at the beginning of
45 a line. If the line seems to have the form '# 123 filename'
46 .line and .file directives will appear in the pre-processed output */
47/* Note that input_file.c hand checks for '#' at the beginning of the
48 first line of the input file. This is because the compiler outputs
49 #NO_APP at the beginning of its output. */
50/* Also note that comments like this one will always work. */
51const char line_comment_chars[] = "#*";
52
53const char line_separator_chars[] = "";
54
55/* Chars that can be used to separate mant from exp in floating point nums */
56CONST char EXP_CHARS[] = "eE";
57
58/* Chars that mean this number is a floating point constant, as
59 in "0f12.456" or "0d1.2345e12". */
60
61CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
62
63/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
64 changed in read.c . Ideally it shouldn't have to know about it at all,
65 but nothing is ideal around here. */
66
67const int md_reloc_size = 8; /* Size of relocation record */
68
69/* Are we trying to generate PIC code? If so, absolute references
70 ought to be made into linkage table references or pc-relative
71 references. Not implemented. For ELF there are other means
72 to denote pic relocations. */
73int flag_want_pic;
74
75static int flag_short_refs; /* -l option */
76static int flag_long_jumps; /* -S option */
77
78#ifdef REGISTER_PREFIX_OPTIONAL
79int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
80#else
81int flag_reg_prefix_optional;
82#endif
83
84/* Whether --register-prefix-optional was used on the command line. */
85static int reg_prefix_optional_seen;
86
87/* The floating point coprocessor to use by default. */
88static enum m68k_register m68k_float_copnum = COP1;
89
90/* If this is non-zero, then references to number(%pc) will be taken
91 to refer to number, rather than to %pc + number. */
92static int m68k_abspcadd;
93
94/* If this is non-zero, then the quick forms of the move, add, and sub
95 instructions are used when possible. */
96static int m68k_quick = 1;
97
98/* If this is non-zero, then if the size is not specified for a base
99 or outer displacement, the assembler assumes that the size should
100 be 32 bits. */
101static int m68k_rel32 = 1;
102
103/* This is non-zero if m68k_rel32 was set from the command line. */
104static int m68k_rel32_from_cmdline;
105
106/* The default width to use for an index register when using a base
107 displacement. */
108static enum m68k_size m68k_index_width_default = SIZE_LONG;
109
110/* We want to warn if any text labels are misaligned. In order to get
111 the right line number, we need to record the line number for each
112 label. */
113
114struct label_line
115{
116 struct label_line *next;
117 symbolS *label;
118 char *file;
119 unsigned int line;
120 int text;
121};
122
123/* The list of labels. */
124
125static struct label_line *labels;
126
127/* The current label. */
128
129static struct label_line *current_label;
130
131/* Its an arbitrary name: This means I don't approve of it */
132/* See flames below */
133static struct obstack robyn;
134
135#define TAB(x,y) (((x)<<2)+(y))
136#define TABTYPE(xy) ((xy) >> 2)
137#define BYTE 0
138#define SHORT 1
139#define LONG 2
140#define SZ_UNDEF 3
141#undef BRANCH
142/* Case `g' except when BCC68000 is applicable. */
143#define ABRANCH 1
144/* Coprocessor branches. */
145#define FBRANCH 2
146/* Mode 7.2 -- program counter indirect with (16-bit) displacement,
147 supported on all cpus. Widens to 32-bit absolute. */
148#define PCREL 3
149/* For inserting an extra jmp instruction with long offset on 68000,
150 for expanding conditional branches. (Not bsr or bra.) Since the
151 68000 doesn't support 32-bit displacements for conditional
152 branches, we fake it by reversing the condition and branching
153 around a jmp with an absolute long operand. */
154#define BCC68000 4
155/* For the DBcc "instructions". If the displacement requires 32 bits,
156 the branch-around-a-jump game is played here too. */
157#define DBCC 5
158/* Not currently used? */
159#define PCLEA 6
160/* Mode AINDX (apc-relative) using PC, with variable target, might fit
161 in 16 or 8 bits. */
162#define PCINDEX 7
163
164struct m68k_incant
165 {
166 const char *m_operands;
167 unsigned long m_opcode;
168 short m_opnum;
169 short m_codenum;
170 int m_arch;
171 struct m68k_incant *m_next;
172 };
173
174#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
175#define gettwo(x) (((x)->m_opcode)&0xffff)
176
177static const enum m68k_register m68000_control_regs[] = { 0 };
178static const enum m68k_register m68010_control_regs[] = {
179 SFC, DFC, USP, VBR,
180 0
181};
182static const enum m68k_register m68020_control_regs[] = {
183 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
184 0
185};
186static const enum m68k_register m68040_control_regs[] = {
187 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
188 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
189 0
190};
191static const enum m68k_register m68060_control_regs[] = {
192 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
193 USP, VBR, URP, SRP, PCR,
194 0
195};
6da466c7 196static const enum m68k_register mcf_control_regs[] = {
252b5132
RH		 197 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
198 RAMBAR0, RAMBAR1, MBAR,
199 0
200};
201#define cpu32_control_regs m68010_control_regs
202
203static const enum m68k_register *control_regs;
204
205/* internal form of a 68020 instruction */
206struct m68k_it
207{
208 const char *error;
209 const char *args; /* list of opcode info */
210 int numargs;
211
212 int numo; /* Number of shorts in opcode */
213 short opcode[11];
214
215 struct m68k_op operands[6];
216
217 int nexp; /* number of exprs in use */
218 struct m68k_exp exprs[4];
219
220 int nfrag; /* Number of frags we have to produce */
221 struct
222 {
223 int fragoff; /* Where in the current opcode the frag ends */
224 symbolS *fadd;
225 offsetT foff;
226 int fragty;
227 }
228 fragb[4];
229
230 int nrel; /* Num of reloc strucs in use */
231 struct
232 {
233 int n;
234 expressionS exp;
235 char wid;
236 char pcrel;
237 /* In a pc relative address the difference between the address
238 of the offset and the address that the offset is relative
239 to. This depends on the addressing mode. Basically this
240 is the value to put in the offset field to address the
241 first byte of the offset, without regarding the special
242 significance of some values (in the branch instruction, for
243 example). */
244 int pcrel_fix;
245#ifdef OBJ_ELF
246 /* Whether this expression needs special pic relocation, and if
247 so, which. */
248 enum pic_relocation pic_reloc;
249#endif
250 }
251 reloc[5]; /* Five is enough??? */
252};
253
6da466c7 254#define cpu_of_arch(x) ((x) & (m68000up|mcf))
252b5132
RH		 255#define float_of_arch(x) ((x) & mfloat)
256#define mmu_of_arch(x) ((x) & mmmu)
6da466c7 257#define arch_coldfire_p(x) (((x) & mcf) != 0)
252b5132
RH		 258
259/* Macros for determining if cpu supports a specific addressing mode */
260#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
261
262static struct m68k_it the_ins; /* the instruction being assembled */
263
264#define op(ex) ((ex)->exp.X_op)
265#define adds(ex) ((ex)->exp.X_add_symbol)
266#define subs(ex) ((ex)->exp.X_op_symbol)
267#define offs(ex) ((ex)->exp.X_add_number)
268
269/* Macros for adding things to the m68k_it struct */
270
271#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
272
273/* Static functions. */
274
275static void insop PARAMS ((int, const struct m68k_incant *));
276static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
277static void add_frag PARAMS ((symbolS *, offsetT, int));
278
279/* Like addword, but goes BEFORE general operands */
280static void
281insop (w, opcode)
282 int w;
283 const struct m68k_incant *opcode;
284{
285 int z;
286 for(z=the_ins.numo;z>opcode->m_codenum;--z)
287 the_ins.opcode[z]=the_ins.opcode[z-1];
288 for(z=0;z<the_ins.nrel;z++)
289 the_ins.reloc[z].n+=2;
290 for (z = 0; z < the_ins.nfrag; z++)
291 the_ins.fragb[z].fragoff++;
292 the_ins.opcode[opcode->m_codenum]=w;
293 the_ins.numo++;
294}
295
296/* The numo+1 kludge is so we can hit the low order byte of the prev word.
297 Blecch. */
298static void
299add_fix (width, exp, pc_rel, pc_fix)
300 int width;
301 struct m68k_exp *exp;
302 int pc_rel;
303 int pc_fix;
304{
305 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
306 ? (the_ins.numo*2-1)
307 : (((width)=='b')
308 ? (the_ins.numo*2+1)
309 : (the_ins.numo*2)));
310 the_ins.reloc[the_ins.nrel].exp = exp->exp;
311 the_ins.reloc[the_ins.nrel].wid = width;
312 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
313#ifdef OBJ_ELF
314 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
315#endif
316 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
317}
318
319/* Cause an extra frag to be generated here, inserting up to 10 bytes
320 (that value is chosen in the frag_var call in md_assemble). TYPE
321 is the subtype of the frag to be generated; its primary type is
322 rs_machine_dependent.
323
324 The TYPE parameter is also used by md_convert_frag_1 and
325 md_estimate_size_before_relax. The appropriate type of fixup will
326 be emitted by md_convert_frag_1.
327
328 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
329static void
330add_frag (add, off, type)
331 symbolS *add;
332 offsetT off;
333 int type;
334{
335 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
336 the_ins.fragb[the_ins.nfrag].fadd=add;
337 the_ins.fragb[the_ins.nfrag].foff=off;
338 the_ins.fragb[the_ins.nfrag++].fragty=type;
339}
340
341#define isvar(ex) \
342 (op (ex) != O_constant && op (ex) != O_big)
343
344static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
345static int get_num PARAMS ((struct m68k_exp *exp, int ok));
346static void m68k_ip PARAMS ((char *));
347static void insert_reg PARAMS ((const char *, int));
348static void select_control_regs PARAMS ((void));
349static void init_regtable PARAMS ((void));
350static int reverse_16_bits PARAMS ((int in));
351static int reverse_8_bits PARAMS ((int in));
352static void install_gen_operand PARAMS ((int mode, int val));
353static void install_operand PARAMS ((int mode, int val));
354static void s_bss PARAMS ((int));
355static void s_data1 PARAMS ((int));
356static void s_data2 PARAMS ((int));
357static void s_even PARAMS ((int));
358static void s_proc PARAMS ((int));
359static void mri_chip PARAMS ((void));
360static void s_chip PARAMS ((int));
361static void s_fopt PARAMS ((int));
362static void s_opt PARAMS ((int));
363static void s_reg PARAMS ((int));
364static void s_restore PARAMS ((int));
365static void s_save PARAMS ((int));
366static void s_mri_if PARAMS ((int));
367static void s_mri_else PARAMS ((int));
368static void s_mri_endi PARAMS ((int));
369static void s_mri_break PARAMS ((int));
370static void s_mri_next PARAMS ((int));
371static void s_mri_for PARAMS ((int));
372static void s_mri_endf PARAMS ((int));
373static void s_mri_repeat PARAMS ((int));
374static void s_mri_until PARAMS ((int));
375static void s_mri_while PARAMS ((int));
376static void s_mri_endw PARAMS ((int));
377static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
378static void md_convert_frag_1 PARAMS ((fragS *));
379
380static int current_architecture;
381
382struct m68k_cpu {
383 unsigned long arch;
384 const char *name;
385 int alias;
386};
387
388static const struct m68k_cpu archs[] = {
389 { m68000, "68000", 0 },
390 { m68010, "68010", 0 },
391 { m68020, "68020", 0 },
392 { m68030, "68030", 0 },
393 { m68040, "68040", 0 },
394 { m68060, "68060", 0 },
395 { cpu32, "cpu32", 0 },
396 { m68881, "68881", 0 },
397 { m68851, "68851", 0 },
398 { mcf5200, "5200", 0 },
6da466c7
ILT		 399 { mcf5206e, "5206e", 0 },
400 { mcf5307, "5307", 0},
252b5132
RH		 401 /* Aliases (effectively, so far as gas is concerned) for the above
402 cpus. */
403 { m68020, "68k", 1 },
404 { m68000, "68008", 1 },
405 { m68000, "68302", 1 },
406 { m68000, "68306", 1 },
407 { m68000, "68307", 1 },
408 { m68000, "68322", 1 },
409 { m68000, "68356", 1 },
410 { m68000, "68ec000", 1 },
411 { m68000, "68hc000", 1 },
412 { m68000, "68hc001", 1 },
413 { m68020, "68ec020", 1 },
414 { m68030, "68ec030", 1 },
415 { m68040, "68ec040", 1 },
416 { m68060, "68ec060", 1 },
417 { cpu32, "68330", 1 },
418 { cpu32, "68331", 1 },
419 { cpu32, "68332", 1 },
420 { cpu32, "68333", 1 },
421 { cpu32, "68334", 1 },
422 { cpu32, "68336", 1 },
423 { cpu32, "68340", 1 },
424 { cpu32, "68341", 1 },
425 { cpu32, "68349", 1 },
426 { cpu32, "68360", 1 },
427 { m68881, "68882", 1 },
6da466c7
ILT		 428 { mcf5200, "5202", 1 },
429 { mcf5200, "5204", 1 },
430 { mcf5200, "5206", 1 },
252b5132
RH		 431};
432
433static const int n_archs = sizeof (archs) / sizeof (archs[0]);
434
435/* BCC68000 is for patching in an extra jmp instruction for long offsets
436 on the 68000. The 68000 doesn't support long branches with branchs */
437
438/* This table desribes how you change sizes for the various types of variable
439 size expressions. This version only supports two kinds. */
440
441/* Note that calls to frag_var need to specify the maximum expansion
442 needed; this is currently 10 bytes for DBCC. */
443
444/* The fields are:
445 How far Forward this mode will reach:
446 How far Backward this mode will reach:
447 How many bytes this mode will add to the size of the frag
448 Which mode to go to if the offset won't fit in this one
449 */
450relax_typeS md_relax_table[] =
451{
452 {1, 1, 0, 0}, /* First entries aren't used */
453 {1, 1, 0, 0}, /* For no good reason except */
454 {1, 1, 0, 0}, /* that the VAX doesn't either */
455 {1, 1, 0, 0},
456
457 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
458 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
459 {0, 0, 4, 0},
460 {1, 1, 0, 0},
461
462 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
463 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
464 {0, 0, 4, 0},
465 {1, 1, 0, 0},
466
467 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
468 {(32767), (-32768), 2, TAB (PCREL, LONG)},
469 {0, 0, 4, 0},
470 {1, 1, 0, 0},
471
472 {(127), (-128), 0, TAB (BCC68000, SHORT)},
473 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
474 {0, 0, 6, 0}, /* jmp long space */
475 {1, 1, 0, 0},
476
477 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
478 {(32767), (-32768), 2, TAB (DBCC, LONG)},
479 {0, 0, 10, 0}, /* bra/jmp long space */
480 {1, 1, 0, 0},
481
482 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
483 {32767, -32768, 2, TAB (PCLEA, LONG)},
484 {0, 0, 6, 0},
485 {1, 1, 0, 0},
486
487 /* For, e.g., jmp pcrel indexed. */
488 {125, -130, 0, TAB (PCINDEX, SHORT)},
489 {32765, -32770, 2, TAB (PCINDEX, LONG)},
490 {0, 0, 4, 0},
491 {1, 1, 0, 0},
492};
493
494/* These are the machine dependent pseudo-ops. These are included so
495 the assembler can work on the output from the SUN C compiler, which
496 generates these.
497 */
498
499/* This table describes all the machine specific pseudo-ops the assembler
500 has to support. The fields are:
501 pseudo-op name without dot
502 function to call to execute this pseudo-op
503 Integer arg to pass to the function
504 */
505const pseudo_typeS md_pseudo_table[] =
506{
507 {"data1", s_data1, 0},
508 {"data2", s_data2, 0},
509 {"bss", s_bss, 0},
510 {"even", s_even, 0},
511 {"skip", s_space, 0},
512 {"proc", s_proc, 0},
513#if defined (TE_SUN3) || defined (OBJ_ELF)
514 {"align", s_align_bytes, 0},
515#endif
516#ifdef OBJ_ELF
517 {"swbeg", s_ignore, 0},
518#endif
519 {"extend", float_cons, 'x'},
520 {"ldouble", float_cons, 'x'},
521
522 /* The following pseudo-ops are supported for MRI compatibility. */
523 {"chip", s_chip, 0},
524 {"comline", s_space, 1},
525 {"fopt", s_fopt, 0},
526 {"mask2", s_ignore, 0},
527 {"opt", s_opt, 0},
528 {"reg", s_reg, 0},
529 {"restore", s_restore, 0},
530 {"save", s_save, 0},
531
532 {"if", s_mri_if, 0},
533 {"if.b", s_mri_if, 'b'},
534 {"if.w", s_mri_if, 'w'},
535 {"if.l", s_mri_if, 'l'},
536 {"else", s_mri_else, 0},
537 {"else.s", s_mri_else, 's'},
538 {"else.l", s_mri_else, 'l'},
539 {"endi", s_mri_endi, 0},
540 {"break", s_mri_break, 0},
541 {"break.s", s_mri_break, 's'},
542 {"break.l", s_mri_break, 'l'},
543 {"next", s_mri_next, 0},
544 {"next.s", s_mri_next, 's'},
545 {"next.l", s_mri_next, 'l'},
546 {"for", s_mri_for, 0},
547 {"for.b", s_mri_for, 'b'},
548 {"for.w", s_mri_for, 'w'},
549 {"for.l", s_mri_for, 'l'},
550 {"endf", s_mri_endf, 0},
551 {"repeat", s_mri_repeat, 0},
552 {"until", s_mri_until, 0},
553 {"until.b", s_mri_until, 'b'},
554 {"until.w", s_mri_until, 'w'},
555 {"until.l", s_mri_until, 'l'},
556 {"while", s_mri_while, 0},
557 {"while.b", s_mri_while, 'b'},
558 {"while.w", s_mri_while, 'w'},
559 {"while.l", s_mri_while, 'l'},
560 {"endw", s_mri_endw, 0},
561
562 {0, 0, 0}
563};
564
565
566/* The mote pseudo ops are put into the opcode table, since they
567 don't start with a . they look like opcodes to gas.
568 */
569
570#ifdef M68KCOFF
571extern void obj_coff_section PARAMS ((int));
572#endif
573
574CONST pseudo_typeS mote_pseudo_table[] =
575{
576
577 {"dcl", cons, 4},
578 {"dc", cons, 2},
579 {"dcw", cons, 2},
580 {"dcb", cons, 1},
581
582 {"dsl", s_space, 4},
583 {"ds", s_space, 2},
584 {"dsw", s_space, 2},
585 {"dsb", s_space, 1},
586
587 {"xdef", s_globl, 0},
588#ifdef OBJ_ELF
589 {"align", s_align_bytes, 0},
590#else
591 {"align", s_align_ptwo, 0},
592#endif
593#ifdef M68KCOFF
594 {"sect", obj_coff_section, 0},
595 {"section", obj_coff_section, 0},
596#endif
597 {0, 0, 0}
598};
599
600#define issbyte(x) ((x)>=-128 && (x)<=127)
601#define isubyte(x) ((x)>=0 && (x)<=255)
602#define issword(x) ((x)>=-32768 && (x)<=32767)
603#define isuword(x) ((x)>=0 && (x)<=65535)
604
605#define isbyte(x) ((x)>= -255 && (x)<=255)
606#define isword(x) ((x)>=-65536 && (x)<=65535)
607#define islong(x) (1)
608
609extern char *input_line_pointer;
610
611static char mklower_table[256];
612#define mklower(c) (mklower_table[(unsigned char)(c)])
613static char notend_table[256];
614static char alt_notend_table[256];
615#define notend(s) \
616 (! (notend_table[(unsigned char) *s] \
617 || (*s == ':' \
618 && alt_notend_table[(unsigned char) s[1]])))
619
620#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
621
622#ifdef NO_PCREL_RELOCS
623
624int
625make_pcrel_absolute(fixP, add_number)
626 fixS *fixP;
627 long *add_number;
628{
629 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
630
631 /* rewrite the PC relative instructions to absolute address ones.
632 * these are rumoured to be faster, and the apollo linker refuses
633 * to deal with the PC relative relocations.
634 */
635 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
636 {
637 opcode[0] = 0x4e;
638 opcode[1] = 0xf9;
639 }
640 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
641 {
642 opcode[0] = 0x4e;
643 opcode[1] = 0xb9;
644 }
645 else
646 as_fatal (_("Unknown PC relative instruction"));
647 *add_number -= 4;
648 return 0;
649}
650
651#endif /* NO_PCREL_RELOCS */
652
653short
654tc_coff_fix2rtype (fixP)
655 fixS *fixP;
656{
657 if (fixP->fx_tcbit && fixP->fx_size == 4)
658 return R_RELLONG_NEG;
659#ifdef NO_PCREL_RELOCS
660 know (fixP->fx_pcrel == 0);
661 return (fixP->fx_size == 1 ? R_RELBYTE
662 : fixP->fx_size == 2 ? R_DIR16
663 : R_DIR32);
664#else
665 return (fixP->fx_pcrel ?
666 (fixP->fx_size == 1 ? R_PCRBYTE :
667 fixP->fx_size == 2 ? R_PCRWORD :
668 R_PCRLONG) :
669 (fixP->fx_size == 1 ? R_RELBYTE :
670 fixP->fx_size == 2 ? R_RELWORD :
671 R_RELLONG));
672#endif
673}
674
675#endif
676
677#ifdef OBJ_ELF
678
679/* Compute the relocation code for a fixup of SIZE bytes, using pc
680 relative relocation if PCREL is non-zero. PIC says whether a special
681 pic relocation was requested. */
682
683static bfd_reloc_code_real_type get_reloc_code
684 PARAMS ((int, int, enum pic_relocation));
685
686static bfd_reloc_code_real_type
687get_reloc_code (size, pcrel, pic)
688 int size;
689 int pcrel;
690 enum pic_relocation pic;
691{
692 switch (pic)
693 {
694 case pic_got_pcrel:
695 switch (size)
696 {
697 case 1:
698 return BFD_RELOC_8_GOT_PCREL;
699 case 2:
700 return BFD_RELOC_16_GOT_PCREL;
701 case 4:
702 return BFD_RELOC_32_GOT_PCREL;
703 }
704 break;
705
706 case pic_got_off:
707 switch (size)
708 {
709 case 1:
710 return BFD_RELOC_8_GOTOFF;
711 case 2:
712 return BFD_RELOC_16_GOTOFF;
713 case 4:
714 return BFD_RELOC_32_GOTOFF;
715 }
716 break;
717
718 case pic_plt_pcrel:
719 switch (size)
720 {
721 case 1:
722 return BFD_RELOC_8_PLT_PCREL;
723 case 2:
724 return BFD_RELOC_16_PLT_PCREL;
725 case 4:
726 return BFD_RELOC_32_PLT_PCREL;
727 }
728 break;
729
730 case pic_plt_off:
731 switch (size)
732 {
733 case 1:
734 return BFD_RELOC_8_PLTOFF;
735 case 2:
736 return BFD_RELOC_16_PLTOFF;
737 case 4:
738 return BFD_RELOC_32_PLTOFF;
739 }
740 break;
741
742 case pic_none:
743 if (pcrel)
744 {
745 switch (size)
746 {
747 case 1:
748 return BFD_RELOC_8_PCREL;
749 case 2:
750 return BFD_RELOC_16_PCREL;
751 case 4:
752 return BFD_RELOC_32_PCREL;
753 }
754 }
755 else
756 {
757 switch (size)
758 {
759 case 1:
760 return BFD_RELOC_8;
761 case 2:
762 return BFD_RELOC_16;
763 case 4:
764 return BFD_RELOC_32;
765 }
766 }
767 }
768
769 if (pcrel)
770 {
771 if (pic == pic_none)
772 as_bad (_("Can not do %d byte pc-relative relocation"), size);
773 else
774 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
775 }
776 else
777 {
778 if (pic == pic_none)
779 as_bad (_("Can not do %d byte relocation"), size);
780 else
781 as_bad (_("Can not do %d byte pic relocation"), size);
782 }
783
784 return BFD_RELOC_NONE;
785}
786
787/* Here we decide which fixups can be adjusted to make them relative
788 to the beginning of the section instead of the symbol. Basically
789 we need to make sure that the dynamic relocations are done
790 correctly, so in some cases we force the original symbol to be
791 used. */
792int
793tc_m68k_fix_adjustable (fixP)
794 fixS *fixP;
795{
796 /* Prevent all adjustments to global symbols. */
797 if (S_IS_EXTERNAL (fixP->fx_addsy)
798 || S_IS_WEAK (fixP->fx_addsy))
799 return 0;
800
801 /* adjust_reloc_syms doesn't know about the GOT */
802 switch (fixP->fx_r_type)
803 {
804 case BFD_RELOC_8_GOT_PCREL:
805 case BFD_RELOC_16_GOT_PCREL:
806 case BFD_RELOC_32_GOT_PCREL:
807 case BFD_RELOC_8_GOTOFF:
808 case BFD_RELOC_16_GOTOFF:
809 case BFD_RELOC_32_GOTOFF:
810 case BFD_RELOC_8_PLT_PCREL:
811 case BFD_RELOC_16_PLT_PCREL:
812 case BFD_RELOC_32_PLT_PCREL:
813 case BFD_RELOC_8_PLTOFF:
814 case BFD_RELOC_16_PLTOFF:
815 case BFD_RELOC_32_PLTOFF:
816 return 0;
817
818 case BFD_RELOC_VTABLE_INHERIT:
819 case BFD_RELOC_VTABLE_ENTRY:
820 return 0;
821
822 default:
823 return 1;
824 }
825}
826
827#else /* !OBJ_ELF */
828
829#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
830
831#endif /* OBJ_ELF */
832
833#ifdef BFD_ASSEMBLER
834
835arelent *
836tc_gen_reloc (section, fixp)
837 asection *section;
838 fixS *fixp;
839{
840 arelent *reloc;
841 bfd_reloc_code_real_type code;
842
843 if (fixp->fx_tcbit)
844 abort ();
845
846 if (fixp->fx_r_type != BFD_RELOC_NONE)
847 {
848 code = fixp->fx_r_type;
849
850 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
851 that fixup_segment converted a non-PC relative reloc into a
852 PC relative reloc. In such a case, we need to convert the
853 reloc code. */
854 if (fixp->fx_pcrel)
855 {
856 switch (code)
857 {
858 case BFD_RELOC_8:
859 code = BFD_RELOC_8_PCREL;
860 break;
861 case BFD_RELOC_16:
862 code = BFD_RELOC_16_PCREL;
863 break;
864 case BFD_RELOC_32:
865 code = BFD_RELOC_32_PCREL;
866 break;
867 case BFD_RELOC_8_PCREL:
868 case BFD_RELOC_16_PCREL:
869 case BFD_RELOC_32_PCREL:
870 case BFD_RELOC_8_GOT_PCREL:
871 case BFD_RELOC_16_GOT_PCREL:
872 case BFD_RELOC_32_GOT_PCREL:
873 case BFD_RELOC_8_GOTOFF:
874 case BFD_RELOC_16_GOTOFF:
875 case BFD_RELOC_32_GOTOFF:
876 case BFD_RELOC_8_PLT_PCREL:
877 case BFD_RELOC_16_PLT_PCREL:
878 case BFD_RELOC_32_PLT_PCREL:
879 case BFD_RELOC_8_PLTOFF:
880 case BFD_RELOC_16_PLTOFF:
881 case BFD_RELOC_32_PLTOFF:
882 break;
883 default:
884 as_bad_where (fixp->fx_file, fixp->fx_line,
885 _("Cannot make %s relocation PC relative"),
886 bfd_get_reloc_code_name (code));
887 }
888 }
889 }
890 else
891 {
892#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
893 switch (F (fixp->fx_size, fixp->fx_pcrel))
894 {
895#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
896 MAP (1, 0, BFD_RELOC_8);
897 MAP (2, 0, BFD_RELOC_16);
898 MAP (4, 0, BFD_RELOC_32);
899 MAP (1, 1, BFD_RELOC_8_PCREL);
900 MAP (2, 1, BFD_RELOC_16_PCREL);
901 MAP (4, 1, BFD_RELOC_32_PCREL);
902 default:
903 abort ();
904 }
905 }
906#undef F
907#undef MAP
908
909 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 910 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
911 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 912 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
913#ifndef OBJ_ELF
914 if (fixp->fx_pcrel)
915 reloc->addend = fixp->fx_addnumber;
916 else
917 reloc->addend = 0;
918#else
919 if (!fixp->fx_pcrel)
920 reloc->addend = fixp->fx_addnumber;
921 else
922 reloc->addend = (section->vma
923 + (fixp->fx_pcrel_adjust == 64
924 ? -1 : fixp->fx_pcrel_adjust)
925 + fixp->fx_addnumber
926 + md_pcrel_from (fixp));
927#endif
928
929 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
930 assert (reloc->howto != 0);
931
932 return reloc;
933}
934
935#endif /* BFD_ASSEMBLER */
936
937/* Return zero if the reference to SYMBOL from within the same segment may
938 be relaxed. */
939#ifdef OBJ_ELF
940
941/* On an ELF system, we can't relax an externally visible symbol,
942 because it may be overridden by a shared library. However, if
943 TARGET_OS is "elf", then we presume that we are assembling for an
944 embedded system, in which case we don't have to worry about shared
945 libraries, and we can relax anything. */
946
947#define relaxable_symbol(symbol) \
948 (strcmp (TARGET_OS, "elf") == 0 \
949 || (! S_IS_EXTERNAL (symbol) \
950 && ! S_IS_WEAK (symbol)))
951
952#else
953
954#define relaxable_symbol(symbol) 1
955
956#endif
957
958/* Handle of the OPCODE hash table. NULL means any use before
959 m68k_ip_begin() will crash. */
960static struct hash_control *op_hash;
961\f
962/* Assemble an m68k instruction. */
963
964static void
965m68k_ip (instring)
966 char *instring;
967{
968 register char *p;
969 register struct m68k_op *opP;
970 register const struct m68k_incant *opcode;
971 register const char *s;
972 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
973 char *pdot, *pdotmove;
974 enum m68k_size siz1, siz2;
975 char c;
976 int losing;
977 int opsfound;
978 LITTLENUM_TYPE words[6];
979 LITTLENUM_TYPE *wordp;
980 unsigned long ok_arch = 0;
981
982 if (*instring == ' ')
983 instring++; /* skip leading whitespace */
984
985 /* Scan up to end of operation-code, which MUST end in end-of-string
986 or exactly 1 space. */
987 pdot = 0;
988 for (p = instring; *p != '\0'; p++)
989 {
990 if (*p == ' ')
991 break;
992 if (*p == '.')
993 pdot = p;
994 }
995
996 if (p == instring)
997 {
998 the_ins.error = _("No operator");
999 return;
1000 }
1001
1002 /* p now points to the end of the opcode name, probably whitespace.
1003 Make sure the name is null terminated by clobbering the
1004 whitespace, look it up in the hash table, then fix it back.
1005 Remove a dot, first, since the opcode tables have none. */
1006 if (pdot != NULL)
1007 {
1008 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1009 *pdotmove = pdotmove[1];
1010 p--;
1011 }
1012
1013 c = *p;
1014 *p = '\0';
1015 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1016 *p = c;
1017
1018 if (pdot != NULL)
1019 {
1020 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1021 *pdotmove = pdotmove[-1];
1022 *pdot = '.';
1023 ++p;
1024 }
1025
1026 if (opcode == NULL)
1027 {
1028 the_ins.error = _("Unknown operator");
1029 return;
1030 }
1031
1032 /* found a legitimate opcode, start matching operands */
1033 while (*p == ' ')
1034 ++p;
1035
1036 if (opcode->m_operands == 0)
1037 {
1038 char *old = input_line_pointer;
1039 *old = '\n';
1040 input_line_pointer = p;
1041 /* Ahh - it's a motorola style psuedo op */
1042 mote_pseudo_table[opcode->m_opnum].poc_handler
1043 (mote_pseudo_table[opcode->m_opnum].poc_val);
1044 input_line_pointer = old;
1045 *old = 0;
1046
1047 return;
1048 }
1049
1050 if (flag_mri && opcode->m_opnum == 0)
1051 {
1052 /* In MRI mode, random garbage is allowed after an instruction
1053 which accepts no operands. */
1054 the_ins.args = opcode->m_operands;
1055 the_ins.numargs = opcode->m_opnum;
1056 the_ins.numo = opcode->m_codenum;
1057 the_ins.opcode[0] = getone (opcode);
1058 the_ins.opcode[1] = gettwo (opcode);
1059 return;
1060 }
1061
1062 for (opP = &the_ins.operands[0]; *p; opP++)
1063 {
1064 p = crack_operand (p, opP);
1065
1066 if (opP->error)
1067 {
1068 the_ins.error = opP->error;
1069 return;
1070 }
1071 }
1072
1073 opsfound = opP - &the_ins.operands[0];
1074
1075 /* This ugly hack is to support the floating pt opcodes in their
1076 standard form. Essentially, we fake a first enty of type COP#1 */
1077 if (opcode->m_operands[0] == 'I')
1078 {
1079 int n;
1080
1081 for (n = opsfound; n > 0; --n)
1082 the_ins.operands[n] = the_ins.operands[n - 1];
1083
1084 memset ((char *) (&the_ins.operands[0]), '\0',
1085 sizeof (the_ins.operands[0]));
1086 the_ins.operands[0].mode = CONTROL;
1087 the_ins.operands[0].reg = m68k_float_copnum;
1088 opsfound++;
1089 }
1090
1091 /* We've got the operands. Find an opcode that'll accept them */
1092 for (losing = 0;;)
1093 {
1094 /* If we didn't get the right number of ops, or we have no
1095 common model with this pattern then reject this pattern. */
1096
1097 ok_arch |= opcode->m_arch;
1098 if (opsfound != opcode->m_opnum
1099 || ((opcode->m_arch & current_architecture) == 0))
1100 ++losing;
1101 else
1102 {
1103 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1104 *s && !losing;
1105 s += 2, opP++)
1106 {
1107 /* Warning: this switch is huge! */
1108 /* I've tried to organize the cases into this order:
1109 non-alpha first, then alpha by letter. Lower-case
1110 goes directly before uppercase counterpart. */
1111 /* Code with multiple case ...: gets sorted by the lowest
1112 case ... it belongs to. I hope this makes sense. */
1113 switch (*s)
1114 {
1115 case '!':
1116 switch (opP->mode)
1117 {
1118 case IMMED:
1119 case DREG:
1120 case AREG:
1121 case FPREG:
1122 case CONTROL:
1123 case AINC:
1124 case ADEC:
1125 case REGLST:
1126 losing++;
1127 break;
1128 default:
1129 break;
1130 }
1131 break;
1132
1133 case '<':
1134 switch (opP->mode)
1135 {
1136 case DREG:
1137 case AREG:
1138 case FPREG:
1139 case CONTROL:
1140 case IMMED:
1141 case ADEC:
1142 case REGLST:
1143 losing++;
1144 break;
1145 default:
1146 break;
1147 }
1148 break;
1149
1150 case '>':
1151 switch (opP->mode)
1152 {
1153 case DREG:
1154 case AREG:
1155 case FPREG:
1156 case CONTROL:
1157 case IMMED:
1158 case AINC:
1159 case REGLST:
1160 losing++;
1161 break;
1162 case ABSL:
1163 break;
1164 default:
1165 if (opP->reg == PC
1166 || opP->reg == ZPC)
1167 losing++;
1168 break;
1169 }
1170 break;
1171
1172 case 'm':
1173 switch (opP->mode)
1174 {
1175 case DREG:
1176 case AREG:
1177 case AINDR:
1178 case AINC:
1179 case ADEC:
1180 break;
1181 default:
1182 losing++;
1183 }
1184 break;
1185
1186 case 'n':
1187 switch (opP->mode)
1188 {
1189 case DISP:
1190 break;
1191 default:
1192 losing++;
1193 }
1194 break;
1195
1196 case 'o':
1197 switch (opP->mode)
1198 {
1199 case BASE:
1200 case ABSL:
1201 case IMMED:
1202 break;
1203 default:
1204 losing++;
1205 }
1206 break;
1207
1208 case 'p':
1209 switch (opP->mode)
1210 {
1211 case DREG:
1212 case AREG:
1213 case AINDR:
1214 case AINC:
1215 case ADEC:
1216 break;
1217 case DISP:
1218 if (opP->reg == PC || opP->reg == ZPC)
1219 losing++;
1220 break;
1221 default:
1222 losing++;
1223 }
1224 break;
1225
1226 case 'q':
1227 switch (opP->mode)
1228 {
1229 case DREG:
1230 case AINDR:
1231 case AINC:
1232 case ADEC:
1233 break;
1234 case DISP:
1235 if (opP->reg == PC || opP->reg == ZPC)
1236 losing++;
1237 break;
1238 default:
1239 losing++;
1240 break;
1241 }
1242 break;
1243
1244 case 'v':
1245 switch (opP->mode)
1246 {
1247 case DREG:
1248 case AINDR:
1249 case AINC:
1250 case ADEC:
1251 case ABSL:
1252 break;
1253 case DISP:
1254 if (opP->reg == PC || opP->reg == ZPC)
1255 losing++;
1256 break;
1257 default:
1258 losing++;
1259 break;
1260 }
1261 break;
1262
1263 case '#':
1264 if (opP->mode != IMMED)
1265 losing++;
1266 else if (s[1] == 'b'
1267 && ! isvar (&opP->disp)
1268 && (opP->disp.exp.X_op != O_constant
1269 || ! isbyte (opP->disp.exp.X_add_number)))
1270 losing++;
1271 else if (s[1] == 'B'
1272 && ! isvar (&opP->disp)
1273 && (opP->disp.exp.X_op != O_constant
1274 || ! issbyte (opP->disp.exp.X_add_number)))
1275 losing++;
1276 else if (s[1] == 'w'
1277 && ! isvar (&opP->disp)
1278 && (opP->disp.exp.X_op != O_constant
1279 || ! isword (opP->disp.exp.X_add_number)))
1280 losing++;
1281 else if (s[1] == 'W'
1282 && ! isvar (&opP->disp)
1283 && (opP->disp.exp.X_op != O_constant
1284 || ! issword (opP->disp.exp.X_add_number)))
1285 losing++;
1286 break;
1287
1288 case '^':
1289 case 'T':
1290 if (opP->mode != IMMED)
1291 losing++;
1292 break;
1293
1294 case '$':
1295 if (opP->mode == AREG
1296 || opP->mode == CONTROL
1297 || opP->mode == FPREG
1298 || opP->mode == IMMED
1299 || opP->mode == REGLST
1300 || (opP->mode != ABSL
1301 && (opP->reg == PC
1302 || opP->reg == ZPC)))
1303 losing++;
1304 break;
1305
1306 case '%':
1307 if (opP->mode == CONTROL
1308 || opP->mode == FPREG
1309 || opP->mode == REGLST
1310 || opP->mode == IMMED
1311 || (opP->mode != ABSL
1312 && (opP->reg == PC
1313 || opP->reg == ZPC)))
1314 losing++;
1315 break;
1316
1317 case '&':
1318 switch (opP->mode)
1319 {
1320 case DREG:
1321 case AREG:
1322 case FPREG:
1323 case CONTROL:
1324 case IMMED:
1325 case AINC:
1326 case ADEC:
1327 case REGLST:
1328 losing++;
1329 break;
1330 case ABSL:
1331 break;
1332 default:
1333 if (opP->reg == PC
1334 || opP->reg == ZPC)
1335 losing++;
1336 break;
1337 }
1338 break;
1339
1340 case '*':
1341 if (opP->mode == CONTROL
1342 || opP->mode == FPREG
1343 || opP->mode == REGLST)
1344 losing++;
1345 break;
1346
1347 case '+':
1348 if (opP->mode != AINC)
1349 losing++;
1350 break;
1351
1352 case '-':
1353 if (opP->mode != ADEC)
1354 losing++;
1355 break;
1356
1357 case '/':
1358 switch (opP->mode)
1359 {
1360 case AREG:
1361 case CONTROL:
1362 case FPREG:
1363 case AINC:
1364 case ADEC:
1365 case IMMED:
1366 case REGLST:
1367 losing++;
1368 break;
1369 default:
1370 break;
1371 }
1372 break;
1373
1374 case ';':
1375 switch (opP->mode)
1376 {
1377 case AREG:
1378 case CONTROL:
1379 case FPREG:
1380 case REGLST:
1381 losing++;
1382 break;
1383 default:
1384 break;
1385 }
1386 break;
1387
1388 case '?':
1389 switch (opP->mode)
1390 {
1391 case AREG:
1392 case CONTROL:
1393 case FPREG:
1394 case AINC:
1395 case ADEC:
1396 case IMMED:
1397 case REGLST:
1398 losing++;
1399 break;
1400 case ABSL:
1401 break;
1402 default:
1403 if (opP->reg == PC || opP->reg == ZPC)
1404 losing++;
1405 break;
1406 }
1407 break;
1408
1409 case '@':
1410 switch (opP->mode)
1411 {
1412 case AREG:
1413 case CONTROL:
1414 case FPREG:
1415 case IMMED:
1416 case REGLST:
1417 losing++;
1418 break;
1419 default:
1420 break;
1421 }
1422 break;
1423
1424 case '~': /* For now! (JF FOO is this right?) */
1425 switch (opP->mode)
1426 {
1427 case DREG:
1428 case AREG:
1429 case CONTROL:
1430 case FPREG:
1431 case IMMED:
1432 case REGLST:
1433 losing++;
1434 break;
1435 case ABSL:
1436 break;
1437 default:
1438 if (opP->reg == PC
1439 || opP->reg == ZPC)
1440 losing++;
1441 break;
1442 }
1443 break;
1444
1445 case '3':
1446 if (opP->mode != CONTROL
1447 || (opP->reg != TT0 && opP->reg != TT1))
1448 losing++;
1449 break;
1450
1451 case 'A':
1452 if (opP->mode != AREG)
1453 losing++;
1454 break;
1455
1456 case 'a':
1457 if (opP->mode != AINDR)
1458 ++losing;
1459 break;
1460
1461 case 'B': /* FOO */
1462 if (opP->mode != ABSL
1463 || (flag_long_jumps
1464 && strncmp (instring, "jbsr", 4) == 0))
1465 losing++;
1466 break;
1467
1468 case 'C':
1469 if (opP->mode != CONTROL || opP->reg != CCR)
1470 losing++;
1471 break;
1472
1473 case 'd':
1474 if (opP->mode != DISP
1475 || opP->reg < ADDR0
1476 || opP->reg > ADDR7)
1477 losing++;
1478 break;
1479
1480 case 'D':
1481 if (opP->mode != DREG)
1482 losing++;
1483 break;
1484
6da466c7
ILT		 1485 case 'E':
1486 if (opP->reg != ACC)
1487 losing++;
1488 break;
1489
252b5132
RH		 1490 case 'F':
1491 if (opP->mode != FPREG)
1492 losing++;
1493 break;
1494
6da466c7
ILT		 1495 case 'G':
1496 if (opP->reg != MACSR)
1497 losing++;
1498 break;
1499
1500 case 'H':
1501 if (opP->reg != MASK)
1502 losing++;
1503 break;
1504
252b5132
RH		 1505 case 'I':
1506 if (opP->mode != CONTROL
1507 || opP->reg < COP0
1508 || opP->reg > COP7)
1509 losing++;
1510 break;
1511
1512 case 'J':
1513 if (opP->mode != CONTROL
1514 || opP->reg < USP
1515 || opP->reg > last_movec_reg)
1516 losing++;
1517 else
1518 {
1519 const enum m68k_register *rp;
1520 for (rp = control_regs; *rp; rp++)
1521 if (*rp == opP->reg)
1522 break;
1523 if (*rp == 0)
1524 losing++;
1525 }
1526 break;
1527
1528 case 'k':
1529 if (opP->mode != IMMED)
1530 losing++;
1531 break;
1532
1533 case 'l':
1534 case 'L':
1535 if (opP->mode == DREG
1536 || opP->mode == AREG
1537 || opP->mode == FPREG)
1538 {
1539 if (s[1] == '8')
1540 losing++;
1541 else
1542 {
1543 switch (opP->mode)
1544 {
1545 case DREG:
1546 opP->mask = 1 << (opP->reg - DATA0);
1547 break;
1548 case AREG:
1549 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1550 break;
1551 case FPREG:
1552 opP->mask = 1 << (opP->reg - FP0 + 16);
1553 break;
1554 default:
1555 abort ();
1556 }
1557 opP->mode = REGLST;
1558 }
1559 }
1560 else if (opP->mode == CONTROL)
1561 {
1562 if (s[1] != '8')
1563 losing++;
1564 else
1565 {
1566 switch (opP->reg)
1567 {
1568 case FPI:
1569 opP->mask = 1 << 24;
1570 break;
1571 case FPS:
1572 opP->mask = 1 << 25;
1573 break;
1574 case FPC:
1575 opP->mask = 1 << 26;
1576 break;
1577 default:
1578 losing++;
1579 break;
1580 }
1581 opP->mode = REGLST;
1582 }
1583 }
1584 else if (opP->mode != REGLST)
1585 losing++;
1586 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1587 losing++;
1588 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1589 losing++;
1590 break;
1591
1592 case 'M':
1593 if (opP->mode != IMMED)
1594 losing++;
1595 else if (opP->disp.exp.X_op != O_constant
1596 || ! issbyte (opP->disp.exp.X_add_number))
1597 losing++;
1598 else if (! m68k_quick
1599 && instring[3] != 'q'
1600 && instring[4] != 'q')
1601 losing++;
1602 break;
1603
1604 case 'O':
1605 if (opP->mode != DREG
1606 && opP->mode != IMMED
1607 && opP->mode != ABSL)
1608 losing++;
1609 break;
1610
1611 case 'Q':
1612 if (opP->mode != IMMED)
1613 losing++;
1614 else if (opP->disp.exp.X_op != O_constant
1615 || opP->disp.exp.X_add_number < 1
1616 || opP->disp.exp.X_add_number > 8)
1617 losing++;
1618 else if (! m68k_quick
1619 && (strncmp (instring, "add", 3) == 0
1620 || strncmp (instring, "sub", 3) == 0)
1621 && instring[3] != 'q')
1622 losing++;
1623 break;
1624
1625 case 'R':
1626 if (opP->mode != DREG && opP->mode != AREG)
1627 losing++;
1628 break;
1629
1630 case 'r':
1631 if (opP->mode != AINDR
1632 && (opP->mode != BASE
1633 || (opP->reg != 0
1634 && opP->reg != ZADDR0)
1635 || opP->disp.exp.X_op != O_absent
1636 || ((opP->index.reg < DATA0
1637 || opP->index.reg > DATA7)
1638 && (opP->index.reg < ADDR0
1639 || opP->index.reg > ADDR7))
1640 || opP->index.size != SIZE_UNSPEC
1641 || opP->index.scale != 1))
1642 losing++;
1643 break;
1644
1645 case 's':
1646 if (opP->mode != CONTROL
1647 || ! (opP->reg == FPI
1648 || opP->reg == FPS
1649 || opP->reg == FPC))
1650 losing++;
1651 break;
1652
1653 case 'S':
1654 if (opP->mode != CONTROL || opP->reg != SR)
1655 losing++;
1656 break;
1657
1658 case 't':
1659 if (opP->mode != IMMED)
1660 losing++;
1661 else if (opP->disp.exp.X_op != O_constant
1662 || opP->disp.exp.X_add_number < 0
1663 || opP->disp.exp.X_add_number > 7)
1664 losing++;
1665 break;
1666
1667 case 'U':
1668 if (opP->mode != CONTROL || opP->reg != USP)
1669 losing++;
1670 break;
1671
1672 /* JF these are out of order. We could put them
1673 in order if we were willing to put up with
1674 bunches of #ifdef m68851s in the code.
1675
1676 Don't forget that you need these operands
1677 to use 68030 MMU instructions. */
1678#ifndef NO_68851
1679 /* Memory addressing mode used by pflushr */
1680 case '|':
1681 if (opP->mode == CONTROL
1682 || opP->mode == FPREG
1683 || opP->mode == DREG
1684 || opP->mode == AREG
1685 || opP->mode == REGLST)
1686 losing++;
1687 /* We should accept immediate operands, but they
1688 supposedly have to be quad word, and we don't
1689 handle that. I would like to see what a Motorola
1690 assembler does before doing something here. */
1691 if (opP->mode == IMMED)
1692 losing++;
1693 break;
1694
1695 case 'f':
1696 if (opP->mode != CONTROL
1697 || (opP->reg != SFC && opP->reg != DFC))
1698 losing++;
1699 break;
1700
1701 case '0':
1702 if (opP->mode != CONTROL || opP->reg != TC)
1703 losing++;
1704 break;
1705
1706 case '1':
1707 if (opP->mode != CONTROL || opP->reg != AC)
1708 losing++;
1709 break;
1710
1711 case '2':
1712 if (opP->mode != CONTROL
1713 || (opP->reg != CAL
1714 && opP->reg != VAL
1715 && opP->reg != SCC))
1716 losing++;
1717 break;
1718
1719 case 'V':
1720 if (opP->mode != CONTROL
1721 || opP->reg != VAL)
1722 losing++;
1723 break;
1724
1725 case 'W':
1726 if (opP->mode != CONTROL
1727 || (opP->reg != DRP
1728 && opP->reg != SRP
1729 && opP->reg != CRP))
1730 losing++;
1731 break;
1732
1733 case 'X':
1734 if (opP->mode != CONTROL
1735 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1736 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1737 losing++;
1738 break;
1739
1740 case 'Y':
1741 if (opP->mode != CONTROL || opP->reg != PSR)
1742 losing++;
1743 break;
1744
1745 case 'Z':
1746 if (opP->mode != CONTROL || opP->reg != PCSR)
1747 losing++;
1748 break;
1749#endif
1750 case 'c':
1751 if (opP->mode != CONTROL
1752 || (opP->reg != NC
1753 && opP->reg != IC
1754 && opP->reg != DC
1755 && opP->reg != BC))
1756 {
1757 losing++;
1758 } /* not a cache specifier. */
1759 break;
1760
1761 case '_':
1762 if (opP->mode != ABSL)
1763 ++losing;
1764 break;
1765
6da466c7
ILT		 1766 case 'u':
1767 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1768 losing++;
1769 /* FIXME: kludge instead of fixing parser:
1770 upper/lower registers are *not* CONTROL
1771 registers, but ordinary ones. */
1772 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1773 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1774 opP->mode = DREG;
1775 else
1776 opP->mode = AREG;
1777 break;
1778
252b5132
RH		 1779 default:
1780 abort ();
1781 } /* switch on type of operand */
1782
1783 if (losing)
1784 break;
1785 } /* for each operand */
1786 } /* if immediately wrong */
1787
1788 if (!losing)
1789 {
1790 break;
1791 } /* got it. */
1792
1793 opcode = opcode->m_next;
1794
1795 if (!opcode)
1796 {
1797 if (ok_arch
1798 && !(ok_arch & current_architecture))
1799 {
1800 char buf[200], *cp;
1801
1802 strcpy (buf,
1803 _("invalid instruction for this architecture; needs "));
1804 cp = buf + strlen (buf);
1805 switch (ok_arch)
1806 {
1807 case mfloat:
1808 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1809 break;
1810 case mmmu:
1811 strcpy (cp, _("mmu (68030 or 68851)"));
1812 break;
1813 case m68020up:
1814 strcpy (cp, _("68020 or higher"));
1815 break;
1816 case m68000up:
1817 strcpy (cp, _("68000 or higher"));
1818 break;
1819 case m68010up:
1820 strcpy (cp, _("68010 or higher"));
1821 break;
1822 default:
1823 {
1824 int got_one = 0, idx;
1825 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1826 idx++)
1827 {
1828 if ((archs[idx].arch & ok_arch)
1829 && ! archs[idx].alias)
1830 {
1831 if (got_one)
1832 {
1833 strcpy (cp, " or ");
1834 cp += strlen (cp);
1835 }
1836 got_one = 1;
1837 strcpy (cp, archs[idx].name);
1838 cp += strlen (cp);
1839 }
1840 }
1841 }
1842 }
1843 cp = xmalloc (strlen (buf) + 1);
1844 strcpy (cp, buf);
1845 the_ins.error = cp;
1846 }
1847 else
1848 the_ins.error = _("operands mismatch");
1849 return;
1850 } /* Fell off the end */
1851
1852 losing = 0;
1853 }
1854
1855 /* now assemble it */
1856
1857 the_ins.args = opcode->m_operands;
1858 the_ins.numargs = opcode->m_opnum;
1859 the_ins.numo = opcode->m_codenum;
1860 the_ins.opcode[0] = getone (opcode);
1861 the_ins.opcode[1] = gettwo (opcode);
1862
1863 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1864 {
1865 /* This switch is a doozy.
1866 Watch the first step; its a big one! */
1867 switch (s[0])
1868 {
1869
1870 case '*':
1871 case '~':
1872 case '%':
1873 case ';':
1874 case '@':
1875 case '!':
1876 case '&':
1877 case '$':
1878 case '?':
1879 case '/':
1880 case '<':
1881 case '>':
1882 case 'm':
1883 case 'n':
1884 case 'o':
1885 case 'p':
1886 case 'q':
1887 case 'v':
1888#ifndef NO_68851
1889 case '|':
1890#endif
1891 switch (opP->mode)
1892 {
1893 case IMMED:
1894 tmpreg = 0x3c; /* 7.4 */
1895 if (strchr ("bwl", s[1]))
1896 nextword = get_num (&opP->disp, 80);
1897 else
1898 nextword = get_num (&opP->disp, 0);
1899 if (isvar (&opP->disp))
1900 add_fix (s[1], &opP->disp, 0, 0);
1901 switch (s[1])
1902 {
1903 case 'b':
1904 if (!isbyte (nextword))
1905 opP->error = _("operand out of range");
1906 addword (nextword);
1907 baseo = 0;
1908 break;
1909 case 'w':
1910 if (!isword (nextword))
1911 opP->error = _("operand out of range");
1912 addword (nextword);
1913 baseo = 0;
1914 break;
1915 case 'W':
1916 if (!issword (nextword))
1917 opP->error = _("operand out of range");
1918 addword (nextword);
1919 baseo = 0;
1920 break;
1921 case 'l':
1922 addword (nextword >> 16);
1923 addword (nextword);
1924 baseo = 0;
1925 break;
1926
1927 case 'f':
1928 baseo = 2;
1929 outro = 8;
1930 break;
1931 case 'F':
1932 baseo = 4;
1933 outro = 11;
1934 break;
1935 case 'x':
1936 baseo = 6;
1937 outro = 15;
1938 break;
1939 case 'p':
1940 baseo = 6;
1941 outro = -1;
1942 break;
1943 default:
1944 abort ();
1945 }
1946 if (!baseo)
1947 break;
1948
1949 /* We gotta put out some float */
1950 if (op (&opP->disp) != O_big)
1951 {
1952 valueT val;
1953 int gencnt;
1954
1955 /* Can other cases happen here? */
1956 if (op (&opP->disp) != O_constant)
1957 abort ();
1958
1959 val = (valueT) offs (&opP->disp);
1960 gencnt = 0;
1961 do
1962 {
1963 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1964 val >>= LITTLENUM_NUMBER_OF_BITS;
1965 ++gencnt;
1966 }
1967 while (val != 0);
1968 offs (&opP->disp) = gencnt;
1969 }
1970 if (offs (&opP->disp) > 0)
1971 {
1972 if (offs (&opP->disp) > baseo)
1973 {
1974 as_warn (_("Bignum too big for %c format; truncated"),
1975 s[1]);
1976 offs (&opP->disp) = baseo;
1977 }
1978 baseo -= offs (&opP->disp);
1979 while (baseo--)
1980 addword (0);
1981 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1982 offs (&opP->disp)--;
1983 --wordp)
1984 addword (*wordp);
1985 break;
1986 }
1987 gen_to_words (words, baseo, (long) outro);
1988 for (wordp = words; baseo--; wordp++)
1989 addword (*wordp);
1990 break;
1991 case DREG:
1992 tmpreg = opP->reg - DATA; /* 0.dreg */
1993 break;
1994 case AREG:
1995 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1996 break;
1997 case AINDR:
1998 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1999 break;
2000 case ADEC:
2001 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2002 break;
2003 case AINC:
2004 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2005 break;
2006 case DISP:
2007
2008 nextword = get_num (&opP->disp, 80);
2009
2010 if (opP->reg == PC
2011 && ! isvar (&opP->disp)
2012 && m68k_abspcadd)
2013 {
2014 opP->disp.exp.X_op = O_symbol;
2015#ifndef BFD_ASSEMBLER
2016 opP->disp.exp.X_add_symbol = &abs_symbol;
2017#else
2018 opP->disp.exp.X_add_symbol =
2019 section_symbol (absolute_section);
2020#endif
2021 }
2022
2023 /* Force into index mode. Hope this works */
2024
2025 /* We do the first bit for 32-bit displacements, and the
2026 second bit for 16 bit ones. It is possible that we
2027 should make the default be WORD instead of LONG, but
2028 I think that'd break GCC, so we put up with a little
2029 inefficiency for the sake of working output. */
2030
2031 if (!issword (nextword)
2032 || (isvar (&opP->disp)
2033 && ((opP->disp.size == SIZE_UNSPEC
2034 && flag_short_refs == 0
2035 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2036 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2037 || opP->disp.size == SIZE_LONG)))
2038 {
2039 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2040 || arch_coldfire_p (current_architecture))
252b5132
RH		 2041 opP->error =
2042 _("displacement too large for this architecture; needs 68020 or higher");
2043 if (opP->reg == PC)
2044 tmpreg = 0x3B; /* 7.3 */
2045 else
2046 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2047 if (isvar (&opP->disp))
2048 {
2049 if (opP->reg == PC)
2050 {
2051 if (opP->disp.size == SIZE_LONG
2052#ifdef OBJ_ELF
2053 /* If the displacement needs pic
2054 relocation it cannot be relaxed. */
2055 || opP->disp.pic_reloc != pic_none
2056#endif
2057 )
2058 {
2059 addword (0x0170);
2060 add_fix ('l', &opP->disp, 1, 2);
2061 }
2062 else
2063 {
2064 add_frag (adds (&opP->disp),
2065 offs (&opP->disp),
2066 TAB (PCLEA, SZ_UNDEF));
2067 break;
2068 }
2069 }
2070 else
2071 {
2072 addword (0x0170);
2073 add_fix ('l', &opP->disp, 0, 0);
2074 }
2075 }
2076 else
2077 addword (0x0170);
2078 addword (nextword >> 16);
2079 }
2080 else
2081 {
2082 if (opP->reg == PC)
2083 tmpreg = 0x3A; /* 7.2 */
2084 else
2085 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2086
2087 if (isvar (&opP->disp))
2088 {
2089 if (opP->reg == PC)
2090 {
2091 add_fix ('w', &opP->disp, 1, 0);
2092 }
2093 else
2094 add_fix ('w', &opP->disp, 0, 0);
2095 }
2096 }
2097 addword (nextword);
2098 break;
2099
2100 case POST:
2101 case PRE:
2102 case BASE:
2103 nextword = 0;
2104 baseo = get_num (&opP->disp, 80);
2105 if (opP->mode == POST || opP->mode == PRE)
2106 outro = get_num (&opP->odisp, 80);
2107 /* Figure out the `addressing mode'.
2108 Also turn on the BASE_DISABLE bit, if needed. */
2109 if (opP->reg == PC || opP->reg == ZPC)
2110 {
2111 tmpreg = 0x3b; /* 7.3 */
2112 if (opP->reg == ZPC)
2113 nextword |= 0x80;
2114 }
2115 else if (opP->reg == 0)
2116 {
2117 nextword |= 0x80;
2118 tmpreg = 0x30; /* 6.garbage */
2119 }
2120 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2121 {
2122 nextword |= 0x80;
2123 tmpreg = 0x30 + opP->reg - ZADDR0;
2124 }
2125 else
2126 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2127
2128 siz1 = opP->disp.size;
2129 if (opP->mode == POST || opP->mode == PRE)
2130 siz2 = opP->odisp.size;
2131 else
2132 siz2 = SIZE_UNSPEC;
2133
2134 /* Index register stuff */
2135 if (opP->index.reg != 0
2136 && opP->index.reg >= DATA
2137 && opP->index.reg <= ADDR7)
2138 {
2139 nextword |= (opP->index.reg - DATA) << 12;
2140
2141 if (opP->index.size == SIZE_LONG
2142 || (opP->index.size == SIZE_UNSPEC
2143 && m68k_index_width_default == SIZE_LONG))
2144 nextword |= 0x800;
2145
2146 if ((opP->index.scale != 1
2147 && cpu_of_arch (current_architecture) < m68020)
2148 || (opP->index.scale == 8
6da466c7 2149 && arch_coldfire_p (current_architecture)))
252b5132
RH		 2150 {
2151 opP->error =
2152 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2153 }
2154
6da466c7
ILT		 2155 if (arch_coldfire_p (current_architecture)
2156 && opP->index.size == SIZE_WORD)
2157 opP->error = _("invalid index size for coldfire");
2158
252b5132
RH		 2159 switch (opP->index.scale)
2160 {
2161 case 1:
2162 break;
2163 case 2:
2164 nextword |= 0x200;
2165 break;
2166 case 4:
2167 nextword |= 0x400;
2168 break;
2169 case 8:
2170 nextword |= 0x600;
2171 break;
2172 default:
2173 abort ();
2174 }
2175 /* IF its simple,
2176 GET US OUT OF HERE! */
2177
2178 /* Must be INDEX, with an index register. Address
2179 register cannot be ZERO-PC, and either :b was
2180 forced, or we know it will fit. For a 68000 or
2181 68010, force this mode anyways, because the
2182 larger modes aren't supported. */
2183 if (opP->mode == BASE
2184 && ((opP->reg >= ADDR0
2185 && opP->reg <= ADDR7)
2186 || opP->reg == PC))
2187 {
2188 if (siz1 == SIZE_BYTE
2189 || cpu_of_arch (current_architecture) < m68020
6da466c7 2190 || arch_coldfire_p (current_architecture)
252b5132
RH		 2191 || (siz1 == SIZE_UNSPEC
2192 && ! isvar (&opP->disp)
2193 && issbyte (baseo)))
2194 {
2195 nextword += baseo & 0xff;
2196 addword (nextword);
2197 if (isvar (&opP->disp))
2198 {
2199 /* Do a byte relocation. If it doesn't
2200 fit (possible on m68000) let the
2201 fixup processing complain later. */
2202 if (opP->reg == PC)
2203 add_fix ('B', &opP->disp, 1, 1);
2204 else
2205 add_fix ('B', &opP->disp, 0, 0);
2206 }
2207 else if (siz1 != SIZE_BYTE)
2208 {
2209 if (siz1 != SIZE_UNSPEC)
2210 as_warn (_("Forcing byte displacement"));
2211 if (! issbyte (baseo))
2212 opP->error = _("byte displacement out of range");
2213 }
2214
2215 break;
2216 }
2217 else if (siz1 == SIZE_UNSPEC
2218 && opP->reg == PC
2219 && isvar (&opP->disp)
2220 && subs (&opP->disp) == NULL
2221#ifdef OBJ_ELF
2222 /* If the displacement needs pic
2223 relocation it cannot be relaxed. */
2224 && opP->disp.pic_reloc == pic_none
2225#endif
2226 )
2227 {
2228 /* The code in md_convert_frag_1 needs to be
2229 able to adjust nextword. Call frag_grow
2230 to ensure that we have enough space in
2231 the frag obstack to make all the bytes
2232 contiguous. */
2233 frag_grow (14);
2234 nextword += baseo & 0xff;
2235 addword (nextword);
2236 add_frag (adds (&opP->disp), offs (&opP->disp),
2237 TAB (PCINDEX, SZ_UNDEF));
2238
2239 break;
2240 }
2241 }
2242 }
2243 else
2244 {
2245 nextword |= 0x40; /* No index reg */
2246 if (opP->index.reg >= ZDATA0
2247 && opP->index.reg <= ZDATA7)
2248 nextword |= (opP->index.reg - ZDATA0) << 12;
2249 else if (opP->index.reg >= ZADDR0
2250 || opP->index.reg <= ZADDR7)
2251 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2252 }
2253
2254 /* It isn't simple. */
2255
2256 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2257 || arch_coldfire_p (current_architecture))
252b5132
RH		 2258 opP->error =
2259 _("invalid operand mode for this architecture; needs 68020 or higher");
2260
2261 nextword |= 0x100;
2262 /* If the guy specified a width, we assume that it is
2263 wide enough. Maybe it isn't. If so, we lose. */
2264 switch (siz1)
2265 {
2266 case SIZE_UNSPEC:
2267 if (isvar (&opP->disp)
2268 ? m68k_rel32
2269 : ! issword (baseo))
2270 {
2271 siz1 = SIZE_LONG;
2272 nextword |= 0x30;
2273 }
2274 else if (! isvar (&opP->disp) && baseo == 0)
2275 nextword |= 0x10;
2276 else
2277 {
2278 nextword |= 0x20;
2279 siz1 = SIZE_WORD;
2280 }
2281 break;
2282 case SIZE_BYTE:
2283 as_warn (_(":b not permitted; defaulting to :w"));
2284 /* Fall through. */
2285 case SIZE_WORD:
2286 nextword |= 0x20;
2287 break;
2288 case SIZE_LONG:
2289 nextword |= 0x30;
2290 break;
2291 }
2292
2293 /* Figure out innner displacement stuff */
2294 if (opP->mode == POST || opP->mode == PRE)
2295 {
2296 if (cpu_of_arch (current_architecture) & cpu32)
2297 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2298 switch (siz2)
2299 {
2300 case SIZE_UNSPEC:
2301 if (isvar (&opP->odisp)
2302 ? m68k_rel32
2303 : ! issword (outro))
2304 {
2305 siz2 = SIZE_LONG;
2306 nextword |= 0x3;
2307 }
2308 else if (! isvar (&opP->odisp) && outro == 0)
2309 nextword |= 0x1;
2310 else
2311 {
2312 nextword |= 0x2;
2313 siz2 = SIZE_WORD;
2314 }
2315 break;
2316 case 1:
2317 as_warn (_(":b not permitted; defaulting to :w"));
2318 /* Fall through. */
2319 case 2:
2320 nextword |= 0x2;
2321 break;
2322 case 3:
2323 nextword |= 0x3;
2324 break;
2325 }
2326 if (opP->mode == POST
2327 && (nextword & 0x40) == 0)
2328 nextword |= 0x04;
2329 }
2330 addword (nextword);
2331
2332 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2333 {
2334 if (opP->reg == PC || opP->reg == ZPC)
2335 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2336 else
2337 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2338 }
2339 if (siz1 == SIZE_LONG)
2340 addword (baseo >> 16);
2341 if (siz1 != SIZE_UNSPEC)
2342 addword (baseo);
2343
2344 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2345 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2346 if (siz2 == SIZE_LONG)
2347 addword (outro >> 16);
2348 if (siz2 != SIZE_UNSPEC)
2349 addword (outro);
2350
2351 break;
2352
2353 case ABSL:
2354 nextword = get_num (&opP->disp, 80);
2355 switch (opP->disp.size)
2356 {
2357 default:
2358 abort ();
2359 case SIZE_UNSPEC:
2360 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2361 {
2362 tmpreg = 0x38; /* 7.0 */
2363 addword (nextword);
2364 break;
2365 }
2366 /* Don't generate pc relative code on 68010 and
2367 68000. */
2368 if (isvar (&opP->disp)
2369 && !subs (&opP->disp)
2370 && adds (&opP->disp)
2371#ifdef OBJ_ELF
2372 /* If the displacement needs pic relocation it
2373 cannot be relaxed. */
2374 && opP->disp.pic_reloc == pic_none
2375#endif
2376 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2377 && relaxable_symbol (adds (&opP->disp))
2378 && HAVE_LONG_BRANCH(current_architecture)
2379 && !flag_long_jumps
2380 && !strchr ("~%&$?", s[0]))
2381 {
2382 tmpreg = 0x3A; /* 7.2 */
2383 add_frag (adds (&opP->disp),
2384 offs (&opP->disp),
2385 TAB (PCREL, SZ_UNDEF));
2386 break;
2387 }
2388 /* Fall through into long */
2389 case SIZE_LONG:
2390 if (isvar (&opP->disp))
2391 add_fix ('l', &opP->disp, 0, 0);
2392
2393 tmpreg = 0x39;/* 7.1 mode */
2394 addword (nextword >> 16);
2395 addword (nextword);
2396 break;
2397
2398 case SIZE_BYTE:
2399 as_bad (_("unsupported byte value; use a different suffix"));
2400 /* Fall through. */
2401 case SIZE_WORD: /* Word */
2402 if (isvar (&opP->disp))
2403 add_fix ('w', &opP->disp, 0, 0);
2404
2405 tmpreg = 0x38;/* 7.0 mode */
2406 addword (nextword);
2407 break;
2408 }
2409 break;
2410 case CONTROL:
2411 case FPREG:
2412 default:
2413 as_bad (_("unknown/incorrect operand"));
2414 /* abort(); */
2415 }
2416 install_gen_operand (s[1], tmpreg);
2417 break;
2418
2419 case '#':
2420 case '^':
2421 switch (s[1])
2422 { /* JF: I hate floating point! */
2423 case 'j':
2424 tmpreg = 70;
2425 break;
2426 case '8':
2427 tmpreg = 20;
2428 break;
2429 case 'C':
2430 tmpreg = 50;
2431 break;
2432 case '3':
2433 default:
2434 tmpreg = 80;
2435 break;
2436 }
2437 tmpreg = get_num (&opP->disp, tmpreg);
2438 if (isvar (&opP->disp))
2439 add_fix (s[1], &opP->disp, 0, 0);
2440 switch (s[1])
2441 {
2442 case 'b': /* Danger: These do no check for
2443 certain types of overflow.
2444 user beware! */
2445 if (!isbyte (tmpreg))
2446 opP->error = _("out of range");
2447 insop (tmpreg, opcode);
2448 if (isvar (&opP->disp))
2449 the_ins.reloc[the_ins.nrel - 1].n =
2450 (opcode->m_codenum) * 2 + 1;
2451 break;
2452 case 'B':
2453 if (!issbyte (tmpreg))
2454 opP->error = _("out of range");
2455 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2456 if (isvar (&opP->disp))
2457 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2458 break;
2459 case 'w':
2460 if (!isword (tmpreg))
2461 opP->error = _("out of range");
2462 insop (tmpreg, opcode);
2463 if (isvar (&opP->disp))
2464 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2465 break;
2466 case 'W':
2467 if (!issword (tmpreg))
2468 opP->error = _("out of range");
2469 insop (tmpreg, opcode);
2470 if (isvar (&opP->disp))
2471 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2472 break;
2473 case 'l':
2474 /* Because of the way insop works, we put these two out
2475 backwards. */
2476 insop (tmpreg, opcode);
2477 insop (tmpreg >> 16, opcode);
2478 if (isvar (&opP->disp))
2479 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2480 break;
2481 case '3':
2482 tmpreg &= 0xFF;
2483 case '8':
2484 case 'C':
2485 case 'j':
2486 install_operand (s[1], tmpreg);
2487 break;
2488 default:
2489 abort ();
2490 }
2491 break;
2492
2493 case '+':
2494 case '-':
2495 case 'A':
2496 case 'a':
2497 install_operand (s[1], opP->reg - ADDR);
2498 break;
2499
2500 case 'B':
2501 tmpreg = get_num (&opP->disp, 80);
2502 switch (s[1])
2503 {
2504 case 'B':
2505 /* The pc_fix argument winds up in fx_pcrel_adjust,
2506 which is a char, and may therefore be unsigned. We
2507 want to pass -1, but we pass 64 instead, and convert
2508 back in md_pcrel_from. */
2509 add_fix ('B', &opP->disp, 1, 64);
2510 break;
2511 case 'W':
2512 add_fix ('w', &opP->disp, 1, 0);
2513 addword (0);
2514 break;
2515 case 'L':
2516 long_branch:
2517 if (!HAVE_LONG_BRANCH(current_architecture))
2518 as_warn (_("Can't use long branches on 68000/68010/5200"));
2519 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2520 add_fix ('l', &opP->disp, 1, 0);
2521 addword (0);
2522 addword (0);
2523 break;
2524 case 'g':
2525 if (subs (&opP->disp)) /* We can't relax it */
2526 goto long_branch;
2527
2528#ifdef OBJ_ELF
2529 /* If the displacement needs pic relocation it cannot be
2530 relaxed. */
2531 if (opP->disp.pic_reloc != pic_none)
2532 goto long_branch;
2533#endif
2534
2535 /* This could either be a symbol, or an absolute
2536 address. No matter, the frag hacking will finger it
2537 out. Not quite: it can't switch from BRANCH to
2538 BCC68000 for the case where opnd is absolute (it
2539 needs to use the 68000 hack since no conditional abs
2540 jumps). */
2541 if (( !HAVE_LONG_BRANCH(current_architecture)
2542 || (0 == adds (&opP->disp)))
2543 && (the_ins.opcode[0] >= 0x6200)
2544 && (the_ins.opcode[0] <= 0x6f00))
2545 add_frag (adds (&opP->disp), offs (&opP->disp),
2546 TAB (BCC68000, SZ_UNDEF));
2547 else
2548 add_frag (adds (&opP->disp), offs (&opP->disp),
2549 TAB (ABRANCH, SZ_UNDEF));
2550 break;
2551 case 'w':
2552 if (isvar (&opP->disp))
2553 {
2554#if 1
2555 /* check for DBcc instruction */
2556 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2557 {
2558 /* size varies if patch */
2559 /* needed for long form */
2560 add_frag (adds (&opP->disp), offs (&opP->disp),
2561 TAB (DBCC, SZ_UNDEF));
2562 break;
2563 }
2564#endif
2565 add_fix ('w', &opP->disp, 1, 0);
2566 }
2567 addword (0);
2568 break;
2569 case 'C': /* Fixed size LONG coproc branches */
2570 add_fix ('l', &opP->disp, 1, 0);
2571 addword (0);
2572 addword (0);
2573 break;
2574 case 'c': /* Var size Coprocesssor branches */
2575 if (subs (&opP->disp))
2576 {
2577 add_fix ('l', &opP->disp, 1, 0);
2578 add_frag ((symbolS *) 0, (offsetT) 0, TAB (FBRANCH, LONG));
2579 }
2580 else if (adds (&opP->disp))
2581 add_frag (adds (&opP->disp), offs (&opP->disp),
2582 TAB (FBRANCH, SZ_UNDEF));
2583 else
2584 {
2585 /* add_frag ((symbolS *) 0, offs (&opP->disp),
2586 TAB(FBRANCH,SHORT)); */
2587 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2588 add_fix ('l', &opP->disp, 1, 0);
2589 addword (0);
2590 addword (0);
2591 }
2592 break;
2593 default:
2594 abort ();
2595 }
2596 break;
2597
2598 case 'C': /* Ignore it */
2599 break;
2600
2601 case 'd': /* JF this is a kludge */
2602 install_operand ('s', opP->reg - ADDR);
2603 tmpreg = get_num (&opP->disp, 80);
2604 if (!issword (tmpreg))
2605 {
2606 as_warn (_("Expression out of range, using 0"));
2607 tmpreg = 0;
2608 }
2609 addword (tmpreg);
2610 break;
2611
2612 case 'D':
2613 install_operand (s[1], opP->reg - DATA);
2614 break;
2615
6da466c7
ILT		 2616 case 'E': /* Ignore it */
2617 break;
2618
252b5132
RH		 2619 case 'F':
2620 install_operand (s[1], opP->reg - FP0);
2621 break;
2622
6da466c7
ILT		 2623 case 'G': /* Ignore it */
2624 case 'H':
2625 break;
2626
252b5132
RH		 2627 case 'I':
2628 tmpreg = opP->reg - COP0;
2629 install_operand (s[1], tmpreg);
2630 break;
2631
2632 case 'J': /* JF foo */
2633 switch (opP->reg)
2634 {
2635 case SFC:
2636 tmpreg = 0x000;
2637 break;
2638 case DFC:
2639 tmpreg = 0x001;
2640 break;
2641 case CACR:
2642 tmpreg = 0x002;
2643 break;
2644 case TC:
2645 tmpreg = 0x003;
2646 break;
2647 case ITT0:
2648 tmpreg = 0x004;
2649 break;
2650 case ITT1:
2651 tmpreg = 0x005;
2652 break;
2653 case DTT0:
2654 tmpreg = 0x006;
2655 break;
2656 case DTT1:
2657 tmpreg = 0x007;
2658 break;
2659 case BUSCR:
2660 tmpreg = 0x008;
2661 break;
2662
2663 case USP:
2664 tmpreg = 0x800;
2665 break;
2666 case VBR:
2667 tmpreg = 0x801;
2668 break;
2669 case CAAR:
2670 tmpreg = 0x802;
2671 break;
2672 case MSP:
2673 tmpreg = 0x803;
2674 break;
2675 case ISP:
2676 tmpreg = 0x804;
2677 break;
2678 case MMUSR:
2679 tmpreg = 0x805;
2680 break;
2681 case URP:
2682 tmpreg = 0x806;
2683 break;
2684 case SRP:
2685 tmpreg = 0x807;
2686 break;
2687 case PCR:
2688 tmpreg = 0x808;
2689 break;
2690 case ROMBAR:
2691 tmpreg = 0xC00;
2692 break;
2693 case RAMBAR0:
2694 tmpreg = 0xC04;
2695 break;
2696 case RAMBAR1:
2697 tmpreg = 0xC05;
2698 break;
2699 case MBAR:
2700 tmpreg = 0xC0F;
2701 break;
2702 default:
2703 abort ();
2704 }
2705 install_operand (s[1], tmpreg);
2706 break;
2707
2708 case 'k':
2709 tmpreg = get_num (&opP->disp, 55);
2710 install_operand (s[1], tmpreg & 0x7f);
2711 break;
2712
2713 case 'l':
2714 tmpreg = opP->mask;
2715 if (s[1] == 'w')
2716 {
2717 if (tmpreg & 0x7FF0000)
2718 as_bad (_("Floating point register in register list"));
2719 insop (reverse_16_bits (tmpreg), opcode);
2720 }
2721 else
2722 {
2723 if (tmpreg & 0x700FFFF)
2724 as_bad (_("Wrong register in floating-point reglist"));
2725 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2726 }
2727 break;
2728
2729 case 'L':
2730 tmpreg = opP->mask;
2731 if (s[1] == 'w')
2732 {
2733 if (tmpreg & 0x7FF0000)
2734 as_bad (_("Floating point register in register list"));
2735 insop (tmpreg, opcode);
2736 }
2737 else if (s[1] == '8')
2738 {
2739 if (tmpreg & 0x0FFFFFF)
2740 as_bad (_("incorrect register in reglist"));
2741 install_operand (s[1], tmpreg >> 24);
2742 }
2743 else
2744 {
2745 if (tmpreg & 0x700FFFF)
2746 as_bad (_("wrong register in floating-point reglist"));
2747 else
2748 install_operand (s[1], tmpreg >> 16);
2749 }
2750 break;
2751
2752 case 'M':
2753 install_operand (s[1], get_num (&opP->disp, 60));
2754 break;
2755
2756 case 'O':
2757 tmpreg = ((opP->mode == DREG)
2758 ? 0x20 + opP->reg - DATA
2759 : (get_num (&opP->disp, 40) & 0x1F));
2760 install_operand (s[1], tmpreg);
2761 break;
2762
2763 case 'Q':
2764 tmpreg = get_num (&opP->disp, 10);
2765 if (tmpreg == 8)
2766 tmpreg = 0;
2767 install_operand (s[1], tmpreg);
2768 break;
2769
2770 case 'R':
2771 /* This depends on the fact that ADDR registers are eight
2772 more than their corresponding DATA regs, so the result
2773 will have the ADDR_REG bit set */
2774 install_operand (s[1], opP->reg - DATA);
2775 break;
2776
2777 case 'r':
2778 if (opP->mode == AINDR)
2779 install_operand (s[1], opP->reg - DATA);
2780 else
2781 install_operand (s[1], opP->index.reg - DATA);
2782 break;
2783
2784 case 's':
2785 if (opP->reg == FPI)
2786 tmpreg = 0x1;
2787 else if (opP->reg == FPS)
2788 tmpreg = 0x2;
2789 else if (opP->reg == FPC)
2790 tmpreg = 0x4;
2791 else
2792 abort ();
2793 install_operand (s[1], tmpreg);
2794 break;
2795
2796 case 'S': /* Ignore it */
2797 break;
2798
2799 case 'T':
2800 install_operand (s[1], get_num (&opP->disp, 30));
2801 break;
2802
2803 case 'U': /* Ignore it */
2804 break;
2805
2806 case 'c':
2807 switch (opP->reg)
2808 {
2809 case NC:
2810 tmpreg = 0;
2811 break;
2812 case DC:
2813 tmpreg = 1;
2814 break;
2815 case IC:
2816 tmpreg = 2;
2817 break;
2818 case BC:
2819 tmpreg = 3;
2820 break;
2821 default:
2822 as_fatal (_("failed sanity check"));
2823 } /* switch on cache token */
2824 install_operand (s[1], tmpreg);
2825 break;
2826#ifndef NO_68851
2827 /* JF: These are out of order, I fear. */
2828 case 'f':
2829 switch (opP->reg)
2830 {
2831 case SFC:
2832 tmpreg = 0;
2833 break;
2834 case DFC:
2835 tmpreg = 1;
2836 break;
2837 default:
2838 abort ();
2839 }
2840 install_operand (s[1], tmpreg);
2841 break;
2842
2843 case '0':
2844 case '1':
2845 case '2':
2846 switch (opP->reg)
2847 {
2848 case TC:
2849 tmpreg = 0;
2850 break;
2851 case CAL:
2852 tmpreg = 4;
2853 break;
2854 case VAL:
2855 tmpreg = 5;
2856 break;
2857 case SCC:
2858 tmpreg = 6;
2859 break;
2860 case AC:
2861 tmpreg = 7;
2862 break;
2863 default:
2864 abort ();
2865 }
2866 install_operand (s[1], tmpreg);
2867 break;
2868
2869 case 'V':
2870 if (opP->reg == VAL)
2871 break;
2872 abort ();
2873
2874 case 'W':
2875 switch (opP->reg)
2876 {
2877 case DRP:
2878 tmpreg = 1;
2879 break;
2880 case SRP:
2881 tmpreg = 2;
2882 break;
2883 case CRP:
2884 tmpreg = 3;
2885 break;
2886 default:
2887 abort ();
2888 }
2889 install_operand (s[1], tmpreg);
2890 break;
2891
2892 case 'X':
2893 switch (opP->reg)
2894 {
2895 case BAD:
2896 case BAD + 1:
2897 case BAD + 2:
2898 case BAD + 3:
2899 case BAD + 4:
2900 case BAD + 5:
2901 case BAD + 6:
2902 case BAD + 7:
2903 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2904 break;
2905
2906 case BAC:
2907 case BAC + 1:
2908 case BAC + 2:
2909 case BAC + 3:
2910 case BAC + 4:
2911 case BAC + 5:
2912 case BAC + 6:
2913 case BAC + 7:
2914 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2915 break;
2916
2917 default:
2918 abort ();
2919 }
2920 install_operand (s[1], tmpreg);
2921 break;
2922 case 'Y':
2923 know (opP->reg == PSR);
2924 break;
2925 case 'Z':
2926 know (opP->reg == PCSR);
2927 break;
2928#endif /* m68851 */
2929 case '3':
2930 switch (opP->reg)
2931 {
2932 case TT0:
2933 tmpreg = 2;
2934 break;
2935 case TT1:
2936 tmpreg = 3;
2937 break;
2938 default:
2939 abort ();
2940 }
2941 install_operand (s[1], tmpreg);
2942 break;
2943 case 't':
2944 tmpreg = get_num (&opP->disp, 20);
2945 install_operand (s[1], tmpreg);
2946 break;
2947 case '_': /* used only for move16 absolute 32-bit address */
2948 if (isvar (&opP->disp))
2949 add_fix ('l', &opP->disp, 0, 0);
2950 tmpreg = get_num (&opP->disp, 80);
2951 addword (tmpreg >> 16);
2952 addword (tmpreg & 0xFFFF);
2953 break;
6da466c7
ILT		 2954 case 'u':
2955 install_operand (s[1], opP->reg - DATA0L);
2956 opP->reg -= (DATA0L);
2957 opP->reg &= 0x0F; /* remove upper/lower bit */
2958 break;
252b5132
RH		 2959 default:
2960 abort ();
2961 }
2962 }
2963
2964 /* By the time whe get here (FINALLY) the_ins contains the complete
2965 instruction, ready to be emitted. . . */
2966}
2967
2968static int
2969reverse_16_bits (in)
2970 int in;
2971{
2972 int out = 0;
2973 int n;
2974
2975 static int mask[16] =
2976 {
2977 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2978 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2979 };
2980 for (n = 0; n < 16; n++)
2981 {
2982 if (in & mask[n])
2983 out |= mask[15 - n];
2984 }
2985 return out;
2986} /* reverse_16_bits() */
2987
2988static int
2989reverse_8_bits (in)
2990 int in;
2991{
2992 int out = 0;
2993 int n;
2994
2995 static int mask[8] =
2996 {
2997 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2998 };
2999
3000 for (n = 0; n < 8; n++)
3001 {
3002 if (in & mask[n])
3003 out |= mask[7 - n];
3004 }
3005 return out;
3006} /* reverse_8_bits() */
3007
3008/* Cause an extra frag to be generated here, inserting up to 10 bytes
3009 (that value is chosen in the frag_var call in md_assemble). TYPE
3010 is the subtype of the frag to be generated; its primary type is
3011 rs_machine_dependent.
3012
3013 The TYPE parameter is also used by md_convert_frag_1 and
3014 md_estimate_size_before_relax. The appropriate type of fixup will
3015 be emitted by md_convert_frag_1.
3016
3017 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3018static void
3019install_operand (mode, val)
3020 int mode;
3021 int val;
3022{
3023 switch (mode)
3024 {
3025 case 's':
3026 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3027 break;
3028 case 'd':
3029 the_ins.opcode[0] |= val << 9;
3030 break;
3031 case '1':
3032 the_ins.opcode[1] |= val << 12;
3033 break;
3034 case '2':
3035 the_ins.opcode[1] |= val << 6;
3036 break;
3037 case '3':
3038 the_ins.opcode[1] |= val;
3039 break;
3040 case '4':
3041 the_ins.opcode[2] |= val << 12;
3042 break;
3043 case '5':
3044 the_ins.opcode[2] |= val << 6;
3045 break;
3046 case '6':
3047 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3048 three words long! */
3049 the_ins.numo++;
3050 the_ins.opcode[2] |= val;
3051 break;
3052 case '7':
3053 the_ins.opcode[1] |= val << 7;
3054 break;
3055 case '8':
3056 the_ins.opcode[1] |= val << 10;
3057 break;
3058#ifndef NO_68851
3059 case '9':
3060 the_ins.opcode[1] |= val << 5;
3061 break;
3062#endif
3063
3064 case 't':
3065 the_ins.opcode[1] |= (val << 10) | (val << 7);
3066 break;
3067 case 'D':
3068 the_ins.opcode[1] |= (val << 12) | val;
3069 break;
3070 case 'g':
3071 the_ins.opcode[0] |= val = 0xff;
3072 break;
3073 case 'i':
3074 the_ins.opcode[0] |= val << 9;
3075 break;
3076 case 'C':
3077 the_ins.opcode[1] |= val;
3078 break;
3079 case 'j':
3080 the_ins.opcode[1] |= val;
3081 the_ins.numo++; /* What a hack */
3082 break;
3083 case 'k':
3084 the_ins.opcode[1] |= val << 4;
3085 break;
3086 case 'b':
3087 case 'w':
3088 case 'W':
3089 case 'l':
3090 break;
3091 case 'e':
3092 the_ins.opcode[0] |= (val << 6);
3093 break;
3094 case 'L':
3095 the_ins.opcode[1] = (val >> 16);
3096 the_ins.opcode[2] = val & 0xffff;
3097 break;
6da466c7
ILT		 3098 case 'm':
3099 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3100 the_ins.opcode[0] |= ((val & 0x7) << 9);
3101 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3102 break;
3103 case 'n':
3104 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3105 the_ins.opcode[0] |= ((val & 0x7) << 9);
3106 break;
3107 case 'o':
3108 the_ins.opcode[1] |= val << 12;
3109 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3110 break;
3111 case 'M':
3112 the_ins.opcode[0] |= (val & 0xF);
3113 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3114 break;
3115 case 'N':
3116 the_ins.opcode[1] |= (val & 0xF);
3117 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3118 break;
3119 case 'h':
3120 the_ins.opcode[1] |= ((val != 1) << 10);
3121 break;
252b5132
RH		 3122 case 'c':
3123 default:
3124 as_fatal (_("failed sanity check."));
3125 }
3126} /* install_operand() */
3127
3128static void
3129install_gen_operand (mode, val)
3130 int mode;
3131 int val;
3132{
3133 switch (mode)
3134 {
3135 case 's':
3136 the_ins.opcode[0] |= val;
3137 break;
3138 case 'd':
3139 /* This is a kludge!!! */
3140 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3141 break;
3142 case 'b':
3143 case 'w':
3144 case 'l':
3145 case 'f':
3146 case 'F':
3147 case 'x':
3148 case 'p':
3149 the_ins.opcode[0] |= val;
3150 break;
3151 /* more stuff goes here */
3152 default:
3153 as_fatal (_("failed sanity check."));
3154 }
3155} /* install_gen_operand() */
3156
3157/*
3158 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3159 * then deal with the bitfield hack.
3160 */
3161
3162static char *
3163crack_operand (str, opP)
3164 register char *str;
3165 register struct m68k_op *opP;
3166{
3167 register int parens;
3168 register int c;
3169 register char *beg_str;
3170 int inquote = 0;
3171
3172 if (!str)
3173 {
3174 return str;
3175 }
3176 beg_str = str;
3177 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3178 {
3179 if (! inquote)
3180 {
3181 if (*str == '(')
3182 parens++;
3183 else if (*str == ')')
3184 {
3185 if (!parens)
3186 { /* ERROR */
3187 opP->error = _("Extra )");
3188 return str;
3189 }
3190 --parens;
3191 }
3192 }
3193 if (flag_mri && *str == '\'')
3194 inquote = ! inquote;
3195 }
3196 if (!*str && parens)
3197 { /* ERROR */
3198 opP->error = _("Missing )");
3199 return str;
3200 }
3201 c = *str;
3202 *str = '\0';
3203 if (m68k_ip_op (beg_str, opP) != 0)
3204 {
3205 *str = c;
3206 return str;
3207 }
3208 *str = c;
3209 if (c == '}')
3210 c = *++str; /* JF bitfield hack */
3211 if (c)
3212 {
3213 c = *++str;
3214 if (!c)
3215 as_bad (_("Missing operand"));
3216 }
3217
3218 /* Detect MRI REG symbols and convert them to REGLSTs. */
3219 if (opP->mode == CONTROL && (int)opP->reg < 0)
3220 {
3221 opP->mode = REGLST;
3222 opP->mask = ~(int)opP->reg;
3223 opP->reg = 0;
3224 }
3225
3226 return str;
3227}
3228
3229/* This is the guts of the machine-dependent assembler. STR points to a
3230 machine dependent instruction. This function is supposed to emit
3231 the frags/bytes it assembles to.
3232 */
3233
3234static void
3235insert_reg (regname, regnum)
3236 const char *regname;
3237 int regnum;
3238{
3239 char buf[100];
3240 int i;
3241
3242#ifdef REGISTER_PREFIX
3243 if (!flag_reg_prefix_optional)
3244 {
3245 buf[0] = REGISTER_PREFIX;
3246 strcpy (buf + 1, regname);
3247 regname = buf;
3248 }
3249#endif
3250
3251 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3252 &zero_address_frag));
3253
3254 for (i = 0; regname[i]; i++)
3255 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3256 buf[i] = '\0';
3257
3258 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3259 &zero_address_frag));
3260}
3261
3262struct init_entry
3263 {
3264 const char *name;
3265 int number;
3266 };
3267
3268static const struct init_entry init_table[] =
3269{
3270 { "d0", DATA0 },
3271 { "d1", DATA1 },
3272 { "d2", DATA2 },
3273 { "d3", DATA3 },
3274 { "d4", DATA4 },
3275 { "d5", DATA5 },
3276 { "d6", DATA6 },
3277 { "d7", DATA7 },
3278 { "a0", ADDR0 },
3279 { "a1", ADDR1 },
3280 { "a2", ADDR2 },
3281 { "a3", ADDR3 },
3282 { "a4", ADDR4 },
3283 { "a5", ADDR5 },
3284 { "a6", ADDR6 },
3285 { "fp", ADDR6 },
3286 { "a7", ADDR7 },
3287 { "sp", ADDR7 },
3288 { "ssp", ADDR7 },
3289 { "fp0", FP0 },
3290 { "fp1", FP1 },
3291 { "fp2", FP2 },
3292 { "fp3", FP3 },
3293 { "fp4", FP4 },
3294 { "fp5", FP5 },
3295 { "fp6", FP6 },
3296 { "fp7", FP7 },
3297 { "fpi", FPI },
3298 { "fpiar", FPI },
3299 { "fpc", FPI },
3300 { "fps", FPS },
3301 { "fpsr", FPS },
3302 { "fpc", FPC },
3303 { "fpcr", FPC },
3304 { "control", FPC },
3305 { "status", FPS },
3306 { "iaddr", FPI },
3307
3308 { "cop0", COP0 },
3309 { "cop1", COP1 },
3310 { "cop2", COP2 },
3311 { "cop3", COP3 },
3312 { "cop4", COP4 },
3313 { "cop5", COP5 },
3314 { "cop6", COP6 },
3315 { "cop7", COP7 },
3316 { "pc", PC },
3317 { "zpc", ZPC },
3318 { "sr", SR },
3319
3320 { "ccr", CCR },
3321 { "cc", CCR },
3322
6da466c7
ILT		 3323 { "acc", ACC },
3324 { "macsr", MACSR },
3325 { "mask", MASK },
3326
252b5132
RH		 3327 /* control registers */
3328 { "sfc", SFC }, /* Source Function Code */
3329 { "sfcr", SFC },
3330 { "dfc", DFC }, /* Destination Function Code */
3331 { "dfcr", DFC },
3332 { "cacr", CACR }, /* Cache Control Register */
3333 { "caar", CAAR }, /* Cache Address Register */
3334
3335 { "usp", USP }, /* User Stack Pointer */
3336 { "vbr", VBR }, /* Vector Base Register */
3337 { "msp", MSP }, /* Master Stack Pointer */
3338 { "isp", ISP }, /* Interrupt Stack Pointer */
3339
3340 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3341 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3342 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3343 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3344
3345 /* 68ec040 versions of same */
3346 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3347 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3348 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3349 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3350
3351 /* mcf5200 versions of same. The ColdFire programmer's reference
3352 manual indicated that the order is 2,3,0,1, but Ken Rose
3353 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3354 { "acr0", ITT0 }, /* Access Control Unit 0 */
3355 { "acr1", ITT1 }, /* Access Control Unit 1 */
3356 { "acr2", DTT0 }, /* Access Control Unit 2 */
3357 { "acr3", DTT1 }, /* Access Control Unit 3 */
3358
3359 { "tc", TC }, /* MMU Translation Control Register */
3360 { "tcr", TC },
3361
3362 { "mmusr", MMUSR }, /* MMU Status Register */
3363 { "srp", SRP }, /* User Root Pointer */
3364 { "urp", URP }, /* Supervisor Root Pointer */
3365
3366 { "buscr", BUSCR },
3367 { "pcr", PCR },
3368
3369 { "rombar", ROMBAR }, /* ROM Base Address Register */
3370 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3371 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3372 { "mbar", MBAR }, /* Module Base Address Register */
3373 /* end of control registers */
3374
3375 { "ac", AC },
3376 { "bc", BC },
3377 { "cal", CAL },
3378 { "crp", CRP },
3379 { "drp", DRP },
3380 { "pcsr", PCSR },
3381 { "psr", PSR },
3382 { "scc", SCC },
3383 { "val", VAL },
3384 { "bad0", BAD0 },
3385 { "bad1", BAD1 },
3386 { "bad2", BAD2 },
3387 { "bad3", BAD3 },
3388 { "bad4", BAD4 },
3389 { "bad5", BAD5 },
3390 { "bad6", BAD6 },
3391 { "bad7", BAD7 },
3392 { "bac0", BAC0 },
3393 { "bac1", BAC1 },
3394 { "bac2", BAC2 },
3395 { "bac3", BAC3 },
3396 { "bac4", BAC4 },
3397 { "bac5", BAC5 },
3398 { "bac6", BAC6 },
3399 { "bac7", BAC7 },
3400
3401 { "ic", IC },
3402 { "dc", DC },
3403 { "nc", NC },
3404
3405 { "tt0", TT0 },
3406 { "tt1", TT1 },
3407 /* 68ec030 versions of same */
3408 { "ac0", TT0 },
3409 { "ac1", TT1 },
3410 /* 68ec030 access control unit, identical to 030 MMU status reg */
3411 { "acusr", PSR },
3412
3413 /* Suppressed data and address registers. */
3414 { "zd0", ZDATA0 },
3415 { "zd1", ZDATA1 },
3416 { "zd2", ZDATA2 },
3417 { "zd3", ZDATA3 },
3418 { "zd4", ZDATA4 },
3419 { "zd5", ZDATA5 },
3420 { "zd6", ZDATA6 },
3421 { "zd7", ZDATA7 },
3422 { "za0", ZADDR0 },
3423 { "za1", ZADDR1 },
3424 { "za2", ZADDR2 },
3425 { "za3", ZADDR3 },
3426 { "za4", ZADDR4 },
3427 { "za5", ZADDR5 },
3428 { "za6", ZADDR6 },
3429 { "za7", ZADDR7 },
3430
6da466c7
ILT		 3431 /* Upper and lower data and address registers, used by macw and msacw. */
3432 { "d0l", DATA0L },
3433 { "d1l", DATA1L },
3434 { "d2l", DATA2L },
3435 { "d3l", DATA3L },
3436 { "d4l", DATA4L },
3437 { "d5l", DATA5L },
3438 { "d6l", DATA6L },
3439 { "d7l", DATA7L },
3440
3441 { "a0l", ADDR0L },
3442 { "a1l", ADDR1L },
3443 { "a2l", ADDR2L },
3444 { "a3l", ADDR3L },
3445 { "a4l", ADDR4L },
3446 { "a5l", ADDR5L },
3447 { "a6l", ADDR6L },
3448 { "a7l", ADDR7L },
3449
3450 { "d0u", DATA0U },
3451 { "d1u", DATA1U },
3452 { "d2u", DATA2U },
3453 { "d3u", DATA3U },
3454 { "d4u", DATA4U },
3455 { "d5u", DATA5U },
3456 { "d6u", DATA6U },
3457 { "d7u", DATA7U },
3458
3459 { "a0u", ADDR0U },
3460 { "a1u", ADDR1U },
3461 { "a2u", ADDR2U },
3462 { "a3u", ADDR3U },
3463 { "a4u", ADDR4U },
3464 { "a5u", ADDR5U },
3465 { "a6u", ADDR6U },
3466 { "a7u", ADDR7U },
3467
252b5132
RH		 3468 { 0, 0 }
3469};
3470
3471static void
3472init_regtable ()
3473{
3474 int i;
3475 for (i = 0; init_table[i].name; i++)
3476 insert_reg (init_table[i].name, init_table[i].number);
3477}
3478
3479static int no_68851, no_68881;
3480
3481#ifdef OBJ_AOUT
3482/* a.out machine type. Default to 68020. */
3483int m68k_aout_machtype = 2;
3484#endif
3485
3486void
3487md_assemble (str)
3488 char *str;
3489{
3490 const char *er;
3491 short *fromP;
3492 char *toP = NULL;
3493 int m, n = 0;
3494 char *to_beg_P;
3495 int shorts_this_frag;
3496 fixS *fixP;
3497
3498 /* In MRI mode, the instruction and operands are separated by a
3499 space. Anything following the operands is a comment. The label
3500 has already been removed. */
3501 if (flag_mri)
3502 {
3503 char *s;
3504 int fields = 0;
3505 int infield = 0;
3506 int inquote = 0;
3507
3508 for (s = str; *s != '\0'; s++)
3509 {
3510 if ((*s == ' ' || *s == '\t') && ! inquote)
3511 {
3512 if (infield)
3513 {
3514 ++fields;
3515 if (fields >= 2)
3516 {
3517 *s = '\0';
3518 break;
3519 }
3520 infield = 0;
3521 }
3522 }
3523 else
3524 {
3525 if (! infield)
3526 infield = 1;
3527 if (*s == '\'')
3528 inquote = ! inquote;
3529 }
3530 }
3531 }
3532
3533 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3534 m68k_ip (str);
3535 er = the_ins.error;
3536 if (!er)
3537 {
3538 for (n = 0; n < the_ins.numargs; n++)
3539 if (the_ins.operands[n].error)
3540 {
3541 er = the_ins.operands[n].error;
3542 break;
3543 }
3544 }
3545 if (er)
3546 {
3547 as_bad (_("%s -- statement `%s' ignored"), er, str);
3548 return;
3549 }
3550
3551 /* If there is a current label, record that it marks an instruction. */
3552 if (current_label != NULL)
3553 {
3554 current_label->text = 1;
3555 current_label = NULL;
3556 }
3557
3558 if (the_ins.nfrag == 0)
3559 {
3560 /* No frag hacking involved; just put it out */
3561 toP = frag_more (2 * the_ins.numo);
3562 fromP = &the_ins.opcode[0];
3563 for (m = the_ins.numo; m; --m)
3564 {
3565 md_number_to_chars (toP, (long) (*fromP), 2);
3566 toP += 2;
3567 fromP++;
3568 }
3569 /* put out symbol-dependent info */
3570 for (m = 0; m < the_ins.nrel; m++)
3571 {
3572 switch (the_ins.reloc[m].wid)
3573 {
3574 case 'B':
3575 n = 1;
3576 break;
3577 case 'b':
3578 n = 1;
3579 break;
3580 case '3':
3581 n = 1;
3582 break;
3583 case 'w':
3584 case 'W':
3585 n = 2;
3586 break;
3587 case 'l':
3588 n = 4;
3589 break;
3590 default:
3591 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3592 the_ins.reloc[m].wid);
3593 }
3594
3595 fixP = fix_new_exp (frag_now,
3596 ((toP - frag_now->fr_literal)
3597 - the_ins.numo * 2 + the_ins.reloc[m].n),
3598 n,
3599 &the_ins.reloc[m].exp,
3600 the_ins.reloc[m].pcrel,
3601 get_reloc_code (n, the_ins.reloc[m].pcrel,
3602 the_ins.reloc[m].pic_reloc));
3603 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3604 if (the_ins.reloc[m].wid == 'B')
3605 fixP->fx_signed = 1;
3606 }
3607 return;
3608 }
3609
3610 /* There's some frag hacking */
3611 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3612 {
3613 int wid;
3614
3615 if (n == 0)
3616 wid = 2 * the_ins.fragb[n].fragoff;
3617 else
3618 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3619 toP = frag_more (wid);
3620 to_beg_P = toP;
3621 shorts_this_frag = 0;
3622 for (m = wid / 2; m; --m)
3623 {
3624 md_number_to_chars (toP, (long) (*fromP), 2);
3625 toP += 2;
3626 fromP++;
3627 shorts_this_frag++;
3628 }
3629 for (m = 0; m < the_ins.nrel; m++)
3630 {
3631 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3632 {
3633 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3634 break;
3635 }
3636 wid = the_ins.reloc[m].wid;
3637 if (wid == 0)
3638 continue;
3639 the_ins.reloc[m].wid = 0;
3640 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3641
3642 fixP = fix_new_exp (frag_now,
3643 ((toP - frag_now->fr_literal)
3644 - the_ins.numo * 2 + the_ins.reloc[m].n),
3645 wid,
3646 &the_ins.reloc[m].exp,
3647 the_ins.reloc[m].pcrel,
3648 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3649 the_ins.reloc[m].pic_reloc));
3650 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3651 }
3652 (void) frag_var (rs_machine_dependent, 10, 0,
3653 (relax_substateT) (the_ins.fragb[n].fragty),
3654 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3655 }
3656 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3657 shorts_this_frag = 0;
3658 if (n)
3659 {
3660 toP = frag_more (n * sizeof (short));
3661 while (n--)
3662 {
3663 md_number_to_chars (toP, (long) (*fromP), 2);
3664 toP += 2;
3665 fromP++;
3666 shorts_this_frag++;
3667 }
3668 }
3669 for (m = 0; m < the_ins.nrel; m++)
3670 {
3671 int wid;
3672
3673 wid = the_ins.reloc[m].wid;
3674 if (wid == 0)
3675 continue;
3676 the_ins.reloc[m].wid = 0;
3677 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3678
3679 fixP = fix_new_exp (frag_now,
3680 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3681 - shorts_this_frag * 2),
3682 wid,
3683 &the_ins.reloc[m].exp,
3684 the_ins.reloc[m].pcrel,
3685 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3686 the_ins.reloc[m].pic_reloc));
3687 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3688 }
3689}
3690
3691void
3692md_begin ()
3693{
3694 /*
3695 * md_begin -- set up hash tables with 68000 instructions.
3696 * similar to what the vax assembler does. ---phr
3697 */
3698 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3699 a copy of it at runtime, adding in the information we want but isn't
3700 there. I think it'd be better to have an awk script hack the table
3701 at compile time. Or even just xstr the table and use it as-is. But
3702 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3703 names. */
3704
3705 register const struct m68k_opcode *ins;
3706 register struct m68k_incant *hack, *slak;
3707 register const char *retval = 0; /* empty string, or error msg text */
3708 register unsigned int i;
3709 register char c;
3710
3711 if (flag_mri)
3712 {
3713 flag_reg_prefix_optional = 1;
3714 m68k_abspcadd = 1;
3715 if (! m68k_rel32_from_cmdline)
3716 m68k_rel32 = 0;
3717 }
3718
3719 op_hash = hash_new ();
3720
3721 obstack_begin (&robyn, 4000);
3722 for (i = 0; i < m68k_numopcodes; i++)
3723 {
3724 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3725 do
3726 {
3727 ins = &m68k_opcodes[i];
3728 /* We *could* ignore insns that don't match our arch here
3729 but just leaving them out of the hash. */
3730 slak->m_operands = ins->args;
3731 slak->m_opnum = strlen (slak->m_operands) / 2;
3732 slak->m_arch = ins->arch;
3733 slak->m_opcode = ins->opcode;
3734 /* This is kludgey */
3735 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3736 if (i + 1 != m68k_numopcodes
3737 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3738 {
3739 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3740 i++;
3741 }
3742 else
3743 slak->m_next = 0;
3744 slak = slak->m_next;
3745 }
3746 while (slak);
3747
3748 retval = hash_insert (op_hash, ins->name, (char *) hack);
3749 if (retval)
3750 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3751 }
3752
3753 for (i = 0; i < m68k_numaliases; i++)
3754 {
3755 const char *name = m68k_opcode_aliases[i].primary;
3756 const char *alias = m68k_opcode_aliases[i].alias;
3757 PTR val = hash_find (op_hash, name);
3758 if (!val)
3759 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3760 retval = hash_insert (op_hash, alias, val);
3761 if (retval)
3762 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3763 }
3764
3765 /* In MRI mode, all unsized branches are variable sized. Normally,
3766 they are word sized. */
3767 if (flag_mri)
3768 {
3769 static struct m68k_opcode_alias mri_aliases[] =
3770 {
3771 { "bhi", "jhi", },
3772 { "bls", "jls", },
3773 { "bcc", "jcc", },
3774 { "bcs", "jcs", },
3775 { "bne", "jne", },
3776 { "beq", "jeq", },
3777 { "bvc", "jvc", },
3778 { "bvs", "jvs", },
3779 { "bpl", "jpl", },
3780 { "bmi", "jmi", },
3781 { "bge", "jge", },
3782 { "blt", "jlt", },
3783 { "bgt", "jgt", },
3784 { "ble", "jle", },
3785 { "bra", "jra", },
3786 { "bsr", "jbsr", },
3787 };
3788
3789 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3790 {
3791 const char *name = mri_aliases[i].primary;
3792 const char *alias = mri_aliases[i].alias;
3793 PTR val = hash_find (op_hash, name);
3794 if (!val)
3795 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3796 retval = hash_jam (op_hash, alias, val);
3797 if (retval)
3798 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3799 }
3800 }
3801
3802 for (i = 0; i < sizeof (mklower_table); i++)
3803 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3804
3805 for (i = 0; i < sizeof (notend_table); i++)
3806 {
3807 notend_table[i] = 0;
3808 alt_notend_table[i] = 0;
3809 }
3810 notend_table[','] = 1;
3811 notend_table['{'] = 1;
3812 notend_table['}'] = 1;
3813 alt_notend_table['a'] = 1;
3814 alt_notend_table['A'] = 1;
3815 alt_notend_table['d'] = 1;
3816 alt_notend_table['D'] = 1;
3817 alt_notend_table['#'] = 1;
3818 alt_notend_table['&'] = 1;
3819 alt_notend_table['f'] = 1;
3820 alt_notend_table['F'] = 1;
3821#ifdef REGISTER_PREFIX
3822 alt_notend_table[REGISTER_PREFIX] = 1;
3823#endif
3824
3825 /* We need to put '(' in alt_notend_table to handle
3826 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3827 */
3828 alt_notend_table['('] = 1;
3829
3830 /* We need to put '@' in alt_notend_table to handle
3831 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3832 */
3833 alt_notend_table['@'] = 1;
3834
3835 /* We need to put digits in alt_notend_table to handle
3836 bfextu %d0{24:1},%d0
3837 */
3838 alt_notend_table['0'] = 1;
3839 alt_notend_table['1'] = 1;
3840 alt_notend_table['2'] = 1;
3841 alt_notend_table['3'] = 1;
3842 alt_notend_table['4'] = 1;
3843 alt_notend_table['5'] = 1;
3844 alt_notend_table['6'] = 1;
3845 alt_notend_table['7'] = 1;
3846 alt_notend_table['8'] = 1;
3847 alt_notend_table['9'] = 1;
3848
3849#ifndef MIT_SYNTAX_ONLY
3850 /* Insert pseudo ops, these have to go into the opcode table since
3851 gas expects pseudo ops to start with a dot */
3852 {
3853 int n = 0;
3854 while (mote_pseudo_table[n].poc_name)
3855 {
3856 hack = (struct m68k_incant *)
3857 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3858 hash_insert (op_hash,
3859 mote_pseudo_table[n].poc_name, (char *) hack);
3860 hack->m_operands = 0;
3861 hack->m_opnum = n;
3862 n++;
3863 }
3864 }
3865#endif
3866
3867 init_regtable ();
3868
3869#ifdef OBJ_ELF
3870 record_alignment (text_section, 2);
3871 record_alignment (data_section, 2);
3872 record_alignment (bss_section, 2);
3873#endif
3874}
3875
3876static void
3877select_control_regs ()
3878{
3879 /* Note which set of "movec" control registers is available. */
3880 switch (cpu_of_arch (current_architecture))
3881 {
3882 case m68000:
3883 control_regs = m68000_control_regs;
3884 break;
3885 case m68010:
3886 control_regs = m68010_control_regs;
3887 break;
3888 case m68020:
3889 case m68030:
3890 control_regs = m68020_control_regs;
3891 break;
3892 case m68040:
3893 control_regs = m68040_control_regs;
3894 break;
3895 case m68060:
3896 control_regs = m68060_control_regs;
3897 break;
3898 case cpu32:
3899 control_regs = cpu32_control_regs;
3900 break;
3901 case mcf5200:
6da466c7
ILT		 3902 case mcf5206e:
3903 case mcf5307:
3904 control_regs = mcf_control_regs;
252b5132
RH		 3905 break;
3906 default:
3907 abort ();
3908 }
3909}
3910
3911void
3912m68k_init_after_args ()
3913{
3914 if (cpu_of_arch (current_architecture) == 0)
3915 {
3916 int i;
3917 const char *default_cpu = TARGET_CPU;
3918
3919 if (*default_cpu == 'm')
3920 default_cpu++;
3921 for (i = 0; i < n_archs; i++)
3922 if (strcasecmp (default_cpu, archs[i].name) == 0)
3923 break;
3924 if (i == n_archs)
3925 {
3926 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
3927 current_architecture |= m68020;
3928 }
3929 else
3930 current_architecture |= archs[i].arch;
3931 }
3932 /* Permit m68881 specification with all cpus; those that can't work
3933 with a coprocessor could be doing emulation. */
3934 if (current_architecture & m68851)
3935 {
3936 if (current_architecture & m68040)
3937 {
3938 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
3939 }
3940 }
3941 /* What other incompatibilities could we check for? */
3942
3943 /* Toss in some default assumptions about coprocessors. */
3944 if (!no_68881
3945 && (cpu_of_arch (current_architecture)
3946 /* Can CPU32 have a 68881 coprocessor?? */
3947 & (m68020 | m68030 | cpu32)))
3948 {
3949 current_architecture |= m68881;
3950 }
3951 if (!no_68851
3952 && (cpu_of_arch (current_architecture) & m68020up) != 0
3953 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3954 {
3955 current_architecture |= m68851;
3956 }
3957 if (no_68881 && (current_architecture & m68881))
3958 as_bad (_("options for 68881 and no-68881 both given"));
3959 if (no_68851 && (current_architecture & m68851))
3960 as_bad (_("options for 68851 and no-68851 both given"));
3961
3962#ifdef OBJ_AOUT
3963 /* Work out the magic number. This isn't very general. */
3964 if (current_architecture & m68000)
3965 m68k_aout_machtype = 0;
3966 else if (current_architecture & m68010)
3967 m68k_aout_machtype = 1;
3968 else if (current_architecture & m68020)
3969 m68k_aout_machtype = 2;
3970 else
3971 m68k_aout_machtype = 2;
3972#endif
3973
3974 /* Note which set of "movec" control registers is available. */
3975 select_control_regs ();
3976
3977 if (cpu_of_arch (current_architecture) < m68020
6da466c7 3978 || arch_coldfire_p (current_architecture))
252b5132
RH		 3979 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3980}
3981\f
3982/* This is called when a label is defined. */
3983
3984void
3985m68k_frob_label (sym)
3986 symbolS *sym;
3987{
3988 struct label_line *n;
3989
3990 n = (struct label_line *) xmalloc (sizeof *n);
3991 n->next = labels;
3992 n->label = sym;
3993 as_where (&n->file, &n->line);
3994 n->text = 0;
3995 labels = n;
3996 current_label = n;
3997}
3998
3999/* This is called when a value that is not an instruction is emitted. */
4000
4001void
4002m68k_flush_pending_output ()
4003{
4004 current_label = NULL;
4005}
4006
4007/* This is called at the end of the assembly, when the final value of
4008 the label is known. We warn if this is a text symbol aligned at an
4009 odd location. */
4010
4011void
4012m68k_frob_symbol (sym)
4013 symbolS *sym;
4014{
4015 if (S_GET_SEGMENT (sym) == reg_section
4016 && (int) S_GET_VALUE (sym) < 0)
4017 {
4018 S_SET_SEGMENT (sym, absolute_section);
4019 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4020 }
4021 else if ((S_GET_VALUE (sym) & 1) != 0)
4022 {
4023 struct label_line *l;
4024
4025 for (l = labels; l != NULL; l = l->next)
4026 {
4027 if (l->label == sym)
4028 {
4029 if (l->text)
4030 as_warn_where (l->file, l->line,
4031 _("text label `%s' aligned to odd boundary"),
4032 S_GET_NAME (sym));
4033 break;
4034 }
4035 }
4036 }
4037}
4038\f
4039/* This is called if we go in or out of MRI mode because of the .mri
4040 pseudo-op. */
4041
4042void
4043m68k_mri_mode_change (on)
4044 int on;
4045{
4046 if (on)
4047 {
4048 if (! flag_reg_prefix_optional)
4049 {
4050 flag_reg_prefix_optional = 1;
4051#ifdef REGISTER_PREFIX
4052 init_regtable ();
4053#endif
4054 }
4055 m68k_abspcadd = 1;
4056 if (! m68k_rel32_from_cmdline)
4057 m68k_rel32 = 0;
4058 }
4059 else
4060 {
4061 if (! reg_prefix_optional_seen)
4062 {
4063#ifdef REGISTER_PREFIX_OPTIONAL
4064 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4065#else
4066 flag_reg_prefix_optional = 0;
4067#endif
4068#ifdef REGISTER_PREFIX
4069 init_regtable ();
4070#endif
4071 }
4072 m68k_abspcadd = 0;
4073 if (! m68k_rel32_from_cmdline)
4074 m68k_rel32 = 1;
4075 }
4076}
4077
4078/* Equal to MAX_PRECISION in atof-ieee.c */
4079#define MAX_LITTLENUMS 6
4080
4081/* Turn a string in input_line_pointer into a floating point constant
4082 of type type, and store the appropriate bytes in *litP. The number
4083 of LITTLENUMS emitted is stored in *sizeP . An error message is
4084 returned, or NULL on OK. */
4085
4086char *
4087md_atof (type, litP, sizeP)
4088 char type;
4089 char *litP;
4090 int *sizeP;
4091{
4092 int prec;
4093 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4094 LITTLENUM_TYPE *wordP;
4095 char *t;
4096
4097 switch (type)
4098 {
4099 case 'f':
4100 case 'F':
4101 case 's':
4102 case 'S':
4103 prec = 2;
4104 break;
4105
4106 case 'd':
4107 case 'D':
4108 case 'r':
4109 case 'R':
4110 prec = 4;
4111 break;
4112
4113 case 'x':
4114 case 'X':
4115 prec = 6;
4116 break;
4117
4118 case 'p':
4119 case 'P':
4120 prec = 6;
4121 break;
4122
4123 default:
4124 *sizeP = 0;
4125 return _("Bad call to MD_ATOF()");
4126 }
4127 t = atof_ieee (input_line_pointer, type, words);
4128 if (t)
4129 input_line_pointer = t;
4130
4131 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4132 for (wordP = words; prec--;)
4133 {
4134 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4135 litP += sizeof (LITTLENUM_TYPE);
4136 }
4137 return 0;
4138}
4139
4140void
4141md_number_to_chars (buf, val, n)
4142 char *buf;
4143 valueT val;
4144 int n;
4145{
4146 number_to_chars_bigendian (buf, val, n);
4147}
4148
4149static void
4150md_apply_fix_2 (fixP, val)
4151 fixS *fixP;
4152 offsetT val;
4153{
4154 addressT upper_limit;
4155 offsetT lower_limit;
4156
4157 /* This is unnecessary but it convinces the native rs6000 compiler
4158 to generate the code we want. */
4159 char *buf = fixP->fx_frag->fr_literal;
4160 buf += fixP->fx_where;
4161 /* end ibm compiler workaround */
4162
4163 if (val & 0x80000000)
4164 val |= ~(addressT)0x7fffffff;
4165 else
4166 val &= 0x7fffffff;
4167
4168#ifdef OBJ_ELF
4169 if (fixP->fx_addsy)
4170 {
4171 memset (buf, 0, fixP->fx_size);
4172 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4173
4174 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4175 && !S_IS_DEFINED (fixP->fx_addsy)
4176 && !S_IS_WEAK (fixP->fx_addsy))
4177 S_SET_WEAK (fixP->fx_addsy);
4178 return;
4179 }
4180#endif
4181
4182#ifdef BFD_ASSEMBLER
4183 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4184 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4185 return;
4186#endif
4187
4188 switch (fixP->fx_size)
4189 {
4190 /* The cast to offsetT below are necessary to make code correct for
4191 machines where ints are smaller than offsetT */
4192 case 1:
4193 *buf++ = val;
4194 upper_limit = 0x7f;
4195 lower_limit = - (offsetT) 0x80;
4196 break;
4197 case 2:
4198 *buf++ = (val >> 8);
4199 *buf++ = val;
4200 upper_limit = 0x7fff;
4201 lower_limit = - (offsetT) 0x8000;
4202 break;
4203 case 4:
4204 *buf++ = (val >> 24);
4205 *buf++ = (val >> 16);
4206 *buf++ = (val >> 8);
4207 *buf++ = val;
4208 upper_limit = 0x7fffffff;
4209 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4210 break;
4211 default:
4212 BAD_CASE (fixP->fx_size);
4213 }
4214
4215 /* Fix up a negative reloc. */
4216 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4217 {
4218 fixP->fx_addsy = fixP->fx_subsy;
4219 fixP->fx_subsy = NULL;
4220 fixP->fx_tcbit = 1;
4221 }
4222
4223 /* For non-pc-relative values, it's conceivable we might get something
4224 like "0xff" for a byte field. So extend the upper part of the range
4225 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4226 so that we can do any range checking at all. */
4227 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4228 upper_limit = upper_limit * 2 + 1;
4229
4230 if ((addressT) val > upper_limit
4231 && (val > 0 || val < lower_limit))
4232 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4233
4234 /* A one byte PC-relative reloc means a short branch. We can't use
4235 a short branch with a value of 0 or -1, because those indicate
4236 different opcodes (branches with longer offsets). fixup_segment
4237 in write.c may have clobbered fx_pcrel, so we need to examine the
4238 reloc type. */
4239 if ((fixP->fx_pcrel
4240#ifdef BFD_ASSEMBLER
4241 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4242#endif
4243 )
4244 && fixP->fx_size == 1
4245 && (fixP->fx_addsy == NULL
4246 || S_IS_DEFINED (fixP->fx_addsy))
4247 && (val == 0 || val == -1))
4248 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4249}
4250
4251#ifdef BFD_ASSEMBLER
4252int
4253md_apply_fix (fixP, valp)
4254 fixS *fixP;
4255 valueT *valp;
4256{
4257 md_apply_fix_2 (fixP, (addressT) *valp);
4258 return 1;
4259}
4260#else
4261void md_apply_fix (fixP, val)
4262 fixS *fixP;
4263 long val;
4264{
4265 md_apply_fix_2 (fixP, (addressT) val);
4266}
4267#endif
4268
4269/* *fragP has been relaxed to its final size, and now needs to have
4270 the bytes inside it modified to conform to the new size There is UGLY
4271 MAGIC here. ..
4272 */
4273static void
4274md_convert_frag_1 (fragP)
4275 register fragS *fragP;
4276{
4277 long disp;
4278 long ext = 0;
4279 fixS *fixP;
4280
4281 /* Address in object code of the displacement. */
4282 register int object_address = fragP->fr_fix + fragP->fr_address;
4283
4284 /* Address in gas core of the place to store the displacement. */
4285 /* This convinces the native rs6000 compiler to generate the code we
4286 want. */
4287 register char *buffer_address = fragP->fr_literal;
4288 buffer_address += fragP->fr_fix;
4289 /* end ibm compiler workaround */
4290
4291 /* The displacement of the address, from current location. */
4292 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4293 disp = (disp + fragP->fr_offset) - object_address;
4294
4295#ifdef BFD_ASSEMBLER
49309057 4296 disp += symbol_get_frag (fragP->fr_symbol)->fr_address;
252b5132
RH		 4297#endif
4298
4299 switch (fragP->fr_subtype)
4300 {
4301 case TAB (BCC68000, BYTE):
4302 case TAB (ABRANCH, BYTE):
4303 know (issbyte (disp));
4304 if (disp == 0)
4305 as_bad (_("short branch with zero offset: use :w"));
4306 fragP->fr_opcode[1] = disp;
4307 ext = 0;
4308 break;
4309 case TAB (DBCC, SHORT):
4310 know (issword (disp));
4311 ext = 2;
4312 break;
4313 case TAB (BCC68000, SHORT):
4314 case TAB (ABRANCH, SHORT):
4315 know (issword (disp));
4316 fragP->fr_opcode[1] = 0x00;
4317 ext = 2;
4318 break;
4319 case TAB (ABRANCH, LONG):
4320 if (!HAVE_LONG_BRANCH(current_architecture))
4321 {
4322 if (fragP->fr_opcode[0] == 0x61)
4323 /* BSR */
4324 {
4325 fragP->fr_opcode[0] = 0x4E;
4326 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4327
4328 fix_new (fragP,
4329 fragP->fr_fix,
4330 4,
4331 fragP->fr_symbol,
4332 fragP->fr_offset,
4333 0,
4334 NO_RELOC);
4335
4336 fragP->fr_fix += 4;
4337 ext = 0;
4338 }
4339 /* BRA */
4340 else if (fragP->fr_opcode[0] == 0x60)
4341 {
4342 fragP->fr_opcode[0] = 0x4E;
4343 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4344 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4345 fragP->fr_offset, 0, NO_RELOC);
4346 fragP->fr_fix += 4;
4347 ext = 0;
4348 }
4349 else
4350 {
4351 as_bad (_("Long branch offset not supported."));
4352 }
4353 }
4354 else
4355 {
4356 fragP->fr_opcode[1] = (char) 0xff;
4357 ext = 4;
4358 }
4359 break;
4360 case TAB (BCC68000, LONG):
4361 /* only Bcc 68000 instructions can come here */
4362 /* change bcc into b!cc/jmp absl long */
4363 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4364 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4365
4366 /* JF: these used to be fr_opcode[2,3], but they may be in a
4367 different frag, in which case refering to them is a no-no.
4368 Only fr_opcode[0,1] are guaranteed to work. */
4369 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4370 *buffer_address++ = (char) 0xf9;
4371 fragP->fr_fix += 2; /* account for jmp instruction */
4372 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4373 fragP->fr_offset, 0, NO_RELOC);
4374 fragP->fr_fix += 4;
4375 ext = 0;
4376 break;
4377 case TAB (DBCC, LONG):
4378 /* only DBcc 68000 instructions can come here */
4379 /* change dbcc into dbcc/jmp absl long */
4380 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4381 *buffer_address++ = 0x00; /* branch offset = 4 */
4382 *buffer_address++ = 0x04;
4383 *buffer_address++ = 0x60; /* put in bra pc+6 */
4384 *buffer_address++ = 0x06;
4385 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4386 *buffer_address++ = (char) 0xf9;
4387
4388 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4389 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4390 fragP->fr_offset, 0, NO_RELOC);
4391 fragP->fr_fix += 4;
4392 ext = 0;
4393 break;
4394 case TAB (FBRANCH, SHORT):
4395 know ((fragP->fr_opcode[1] & 0x40) == 0);
4396 ext = 2;
4397 break;
4398 case TAB (FBRANCH, LONG):
4399 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4400 ext = 4;
4401 break;
4402 case TAB (PCREL, SHORT):
4403 ext = 2;
4404 break;
4405 case TAB (PCREL, LONG):
4406 /* The thing to do here is force it to ABSOLUTE LONG, since
4407 PCREL is really trying to shorten an ABSOLUTE address anyway */
4408 /* JF FOO This code has not been tested */
4409 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4410 0, NO_RELOC);
4411 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4412 as_bad (_("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx"),
4413 (unsigned) fragP->fr_opcode[0],
4414 (unsigned long) fragP->fr_address);
4415 fragP->fr_opcode[1] &= ~0x3F;
4416 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4417 fragP->fr_fix += 4;
4418 ext = 0;
4419 break;
4420 case TAB (PCLEA, SHORT):
4421 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4422 fragP->fr_offset, 1, NO_RELOC);
4423 fragP->fr_opcode[1] &= ~0x3F;
4424 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4425 ext = 2;
4426 break;
4427 case TAB (PCLEA, LONG):
4428 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4429 fragP->fr_offset, 1, NO_RELOC);
4430 fixP->fx_pcrel_adjust = 2;
4431 /* Already set to mode 7.3; this indicates: PC indirect with
4432 suppressed index, 32-bit displacement. */
4433 *buffer_address++ = 0x01;
4434 *buffer_address++ = 0x70;
4435 fragP->fr_fix += 2;
4436 ext = 4;
4437 break;
4438
4439 case TAB (PCINDEX, BYTE):
4440 disp += 2;
4441 if (!issbyte (disp))
4442 {
4443 as_bad (_("displacement doesn't fit in one byte"));
4444 disp = 0;
4445 }
4446 assert (fragP->fr_fix >= 2);
4447 buffer_address[-2] &= ~1;
4448 buffer_address[-1] = disp;
4449 ext = 0;
4450 break;
4451 case TAB (PCINDEX, SHORT):
4452 disp += 2;
4453 assert (issword (disp));
4454 assert (fragP->fr_fix >= 2);
4455 buffer_address[-2] |= 0x1;
4456 buffer_address[-1] = 0x20;
4457 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4458 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4459 NO_RELOC);
4460 fixP->fx_pcrel_adjust = 2;
4461 ext = 2;
4462 break;
4463 case TAB (PCINDEX, LONG):
4464 disp += 2;
4465 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4466 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4467 NO_RELOC);
4468 fixP->fx_pcrel_adjust = 2;
4469 assert (fragP->fr_fix >= 2);
4470 buffer_address[-2] |= 0x1;
4471 buffer_address[-1] = 0x30;
4472 ext = 4;
4473 break;
4474 }
4475
4476 if (ext)
4477 {
4478 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4479 fragP->fr_fix += ext;
4480 }
4481}
4482
4483#ifndef BFD_ASSEMBLER
4484
4485void
4486md_convert_frag (headers, sec, fragP)
4487 object_headers *headers;
4488 segT sec;
4489 fragS *fragP;
4490{
4491 md_convert_frag_1 (fragP);
4492}
4493
4494#else
4495
4496void
4497md_convert_frag (abfd, sec, fragP)
36823076
AS		 4498 bfd *abfd ATTRIBUTE_UNUSED;
4499 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4500 fragS *fragP;
4501{
4502 md_convert_frag_1 (fragP);
4503}
4504#endif
4505
4506/* Force truly undefined symbols to their maximum size, and generally set up
4507 the frag list to be relaxed
4508 */
4509int
4510md_estimate_size_before_relax (fragP, segment)
4511 register fragS *fragP;
4512 segT segment;
4513{
4514 int old_fix;
4515 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4516
4517 old_fix = fragP->fr_fix;
4518
4519 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4520 switch (fragP->fr_subtype)
4521 {
4522
4523 case TAB (ABRANCH, SZ_UNDEF):
4524 {
4525 if ((fragP->fr_symbol != NULL) /* Not absolute */
4526 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4527 && relaxable_symbol (fragP->fr_symbol))
4528 {
4529 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4530 break;
4531 }
4532 else if ((fragP->fr_symbol == 0) || !HAVE_LONG_BRANCH(current_architecture))
4533 {
4534 /* On 68000, or for absolute value, switch to abs long */
4535 /* FIXME, we should check abs val, pick short or long */
4536 if (fragP->fr_opcode[0] == 0x61)
4537 {
4538 fragP->fr_opcode[0] = 0x4E;
4539 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4540 fix_new (fragP, fragP->fr_fix, 4,
4541 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4542 fragP->fr_fix += 4;
4543 frag_wane (fragP);
4544 }
4545 else if (fragP->fr_opcode[0] == 0x60)
4546 {
4547 fragP->fr_opcode[0] = 0x4E;
4548 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4549 fix_new (fragP, fragP->fr_fix, 4,
4550 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4551 fragP->fr_fix += 4;
4552 frag_wane (fragP);
4553 }
4554 else
4555 {
4556 as_warn (_("Long branch offset to extern symbol not supported."));
4557 }
4558 }
4559 else
4560 { /* Symbol is still undefined. Make it simple */
4561 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4562 fragP->fr_offset, 1, NO_RELOC);
4563 fragP->fr_fix += 4;
4564 fragP->fr_opcode[1] = (char) 0xff;
4565 frag_wane (fragP);
4566 break;
4567 }
4568
4569 break;
4570 } /* case TAB(ABRANCH,SZ_UNDEF) */
4571
4572 case TAB (FBRANCH, SZ_UNDEF):
4573 {
4574 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4575 && relaxable_symbol (fragP->fr_symbol))
4576 || flag_short_refs)
4577 {
4578 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4579 fragP->fr_var += 2;
4580 }
4581 else
4582 {
4583 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4584 fragP->fr_offset, 1, NO_RELOC);
4585 fragP->fr_fix += 4;
4586 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4587 frag_wane (fragP);
4588 }
4589 break;
4590 } /* TAB(FBRANCH,SZ_UNDEF) */
4591
4592 case TAB (PCREL, SZ_UNDEF):
4593 {
4594 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4595 && relaxable_symbol (fragP->fr_symbol))
4596 || flag_short_refs
4597 || cpu_of_arch (current_architecture) < m68020
4598 || cpu_of_arch (current_architecture) == mcf5200)
4599 {
4600 fragP->fr_subtype = TAB (PCREL, SHORT);
4601 fragP->fr_var += 2;
4602 }
4603 else
4604 {
4605 fragP->fr_subtype = TAB (PCREL, LONG);
4606 fragP->fr_var += 4;
4607 }
4608 break;
4609 } /* TAB(PCREL,SZ_UNDEF) */
4610
4611 case TAB (BCC68000, SZ_UNDEF):
4612 {
4613 if ((fragP->fr_symbol != NULL)
4614 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4615 && relaxable_symbol (fragP->fr_symbol))
4616 {
4617 fragP->fr_subtype = TAB (BCC68000, BYTE);
4618 break;
4619 }
4620 /* only Bcc 68000 instructions can come here */
4621 /* change bcc into b!cc/jmp absl long */
4622 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4623 if (flag_short_refs)
4624 {
4625 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4626 /* JF: these were fr_opcode[2,3] */
4627 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4628 buffer_address[1] = (char) 0xf8;
4629 fragP->fr_fix += 2; /* account for jmp instruction */
4630 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4631 fragP->fr_offset, 0, NO_RELOC);
4632 fragP->fr_fix += 2;
4633 }
4634 else
4635 {
4636 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4637 /* JF: these were fr_opcode[2,3] */
4638 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4639 buffer_address[1] = (char) 0xf9;
4640 fragP->fr_fix += 2; /* account for jmp instruction */
4641 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4642 fragP->fr_offset, 0, NO_RELOC);
4643 fragP->fr_fix += 4;
4644 }
4645 frag_wane (fragP);
4646 break;
4647 } /* case TAB(BCC68000,SZ_UNDEF) */
4648
4649 case TAB (DBCC, SZ_UNDEF):
4650 {
4651 if (fragP->fr_symbol != NULL
4652 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4653 && relaxable_symbol (fragP->fr_symbol))
4654 {
4655 fragP->fr_subtype = TAB (DBCC, SHORT);
4656 fragP->fr_var += 2;
4657 break;
4658 }
4659 /* only DBcc 68000 instructions can come here */
4660 /* change dbcc into dbcc/jmp absl long */
4661 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4662 buffer_address[0] = 0x00; /* branch offset = 4 */
4663 buffer_address[1] = 0x04;
4664 buffer_address[2] = 0x60; /* put in bra pc + ... */
4665
4666 if (flag_short_refs)
4667 {
4668 /* JF: these were fr_opcode[5-7] */
4669 buffer_address[3] = 0x04; /* plus 4 */
4670 buffer_address[4] = 0x4e; /* Put in Jump Word */
4671 buffer_address[5] = (char) 0xf8;
4672 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4673 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4674 fragP->fr_offset, 0, NO_RELOC);
4675 fragP->fr_fix += 2;
4676 }
4677 else
4678 {
4679 /* JF: these were fr_opcode[5-7] */
4680 buffer_address[3] = 0x06; /* Plus 6 */
4681 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4682 buffer_address[5] = (char) 0xf9;
4683 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4684 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4685 fragP->fr_offset, 0, NO_RELOC);
4686 fragP->fr_fix += 4;
4687 }
4688
4689 frag_wane (fragP);
4690 break;
4691 } /* case TAB(DBCC,SZ_UNDEF) */
4692
4693 case TAB (PCLEA, SZ_UNDEF):
4694 {
4695 if (((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4696 && relaxable_symbol (fragP->fr_symbol))
4697 || flag_short_refs
4698 || cpu_of_arch (current_architecture) < m68020
4699 || cpu_of_arch (current_architecture) == mcf5200)
4700 {
4701 fragP->fr_subtype = TAB (PCLEA, SHORT);
4702 fragP->fr_var += 2;
4703 }
4704 else
4705 {
4706 fragP->fr_subtype = TAB (PCLEA, LONG);
4707 fragP->fr_var += 6;
4708 }
4709 break;
4710 } /* TAB(PCLEA,SZ_UNDEF) */
4711
4712 case TAB (PCINDEX, SZ_UNDEF):
4713 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4714 && relaxable_symbol (fragP->fr_symbol))
4715 || cpu_of_arch (current_architecture) < m68020
4716 || cpu_of_arch (current_architecture) == mcf5200)
4717 {
4718 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4719 }
4720 else
4721 {
4722 fragP->fr_subtype = TAB (PCINDEX, LONG);
4723 fragP->fr_var += 4;
4724 }
4725 break;
4726
4727 default:
4728 break;
4729 }
4730
4731 /* now that SZ_UNDEF are taken care of, check others */
4732 switch (fragP->fr_subtype)
4733 {
4734 case TAB (BCC68000, BYTE):
4735 case TAB (ABRANCH, BYTE):
4736 /* We can't do a short jump to the next instruction, so in that
4737 case we force word mode. At this point S_GET_VALUE should
4738 return the offset of the symbol within its frag. If the
4739 symbol is at the start of a frag, and it is the next frag
4740 with any data in it (usually this is just the next frag, but
4741 assembler listings may introduce empty frags), we must use
4742 word mode. */
4743 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4744 {
49309057 4745 fragS *stop;
252b5132
RH		 4746 fragS *l;
4747
49309057
ILT		 4748 stop = symbol_get_frag (fragP->fr_symbol);
4749 for (l = fragP->fr_next; l != stop; l = l->fr_next)
252b5132
RH		 4750 if (l->fr_fix + l->fr_var != 0)
4751 break;
49309057 4752 if (l == stop)
252b5132
RH		 4753 {
4754 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4755 fragP->fr_var += 2;
4756 }
4757 }
4758 break;
4759 default:
4760 break;
4761 }
4762 return fragP->fr_var + fragP->fr_fix - old_fix;
4763}
4764
4765#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4766/* the bit-field entries in the relocation_info struct plays hell
4767 with the byte-order problems of cross-assembly. So as a hack,
4768 I added this mach. dependent ri twiddler. Ugly, but it gets
4769 you there. -KWK */
4770/* on m68k: first 4 bytes are normal unsigned long, next three bytes
4771 are symbolnum, most sig. byte first. Last byte is broken up with
4772 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4773 nibble as nuthin. (on Sun 3 at least) */
4774/* Translate the internal relocation information into target-specific
4775 format. */
4776#ifdef comment
4777void
4778md_ri_to_chars (the_bytes, ri)
4779 char *the_bytes;
4780 struct reloc_info_generic *ri;
4781{
4782 /* this is easy */
4783 md_number_to_chars (the_bytes, ri->r_address, 4);
4784 /* now the fun stuff */
4785 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4786 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4787 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4788 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4789 ((ri->r_extern << 4) & 0x10));
4790}
4791
4792#endif /* comment */
4793
4794#ifndef BFD_ASSEMBLER
4795void
4796tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4797 char *where;
4798 fixS *fixP;
4799 relax_addressT segment_address_in_file;
4800{
4801 /*
4802 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4803 * Out: GNU LD relocation length code: 0, 1, or 2.
4804 */
4805
4806 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4807 long r_symbolnum;
4808
4809 know (fixP->fx_addsy != NULL);
4810
4811 md_number_to_chars (where,
4812 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4813 4);
4814
4815 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4816 ? S_GET_TYPE (fixP->fx_addsy)
4817 : fixP->fx_addsy->sy_number);
4818
4819 where[4] = (r_symbolnum >> 16) & 0x0ff;
4820 where[5] = (r_symbolnum >> 8) & 0x0ff;
4821 where[6] = r_symbolnum & 0x0ff;
4822 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4823 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4824}
4825#endif
4826
4827#endif /* OBJ_AOUT or OBJ_BOUT */
4828
4829#ifndef WORKING_DOT_WORD
4830CONST int md_short_jump_size = 4;
4831CONST int md_long_jump_size = 6;
4832
4833void
4834md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4835 char *ptr;
4836 addressT from_addr, to_addr;
36823076
AS		 4837 fragS *frag ATTRIBUTE_UNUSED;
4838 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132
RH		 4839{
4840 valueT offset;
4841
4842 offset = to_addr - (from_addr + 2);
4843
4844 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4845 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4846}
4847
4848void
4849md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4850 char *ptr;
4851 addressT from_addr, to_addr;
4852 fragS *frag;
4853 symbolS *to_symbol;
4854{
4855 valueT offset;
4856
4857 if (!HAVE_LONG_BRANCH(current_architecture))
4858 {
4859 offset = to_addr - S_GET_VALUE (to_symbol);
4860 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4861 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4862 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4863 0, NO_RELOC);
4864 }
4865 else
4866 {
4867 offset = to_addr - (from_addr + 2);
4868 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4869 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4870 }
4871}
4872
4873#endif
4874
4875/* Different values of OK tell what its OK to return. Things that
4876 aren't OK are an error (what a shock, no?)
4877
4878 0: Everything is OK
4879 10: Absolute 1:8 only
4880 20: Absolute 0:7 only
4881 30: absolute 0:15 only
4882 40: Absolute 0:31 only
4883 50: absolute 0:127 only
4884 55: absolute -64:63 only
4885 60: absolute -128:127 only
4886 70: absolute 0:4095 only
4887 80: No bignums
4888
4889 */
4890
4891static int
4892get_num (exp, ok)
4893 struct m68k_exp *exp;
4894 int ok;
4895{
4896 if (exp->exp.X_op == O_absent)
4897 {
4898 /* Do the same thing the VAX asm does */
4899 op (exp) = O_constant;
4900 adds (exp) = 0;
4901 subs (exp) = 0;
4902 offs (exp) = 0;
4903 if (ok == 10)
4904 {
4905 as_warn (_("expression out of range: defaulting to 1"));
4906 offs (exp) = 1;
4907 }
4908 }
4909 else if (exp->exp.X_op == O_constant)
4910 {
4911 switch (ok)
4912 {
4913 case 10:
4914 if (offs (exp) < 1 || offs (exp) > 8)
4915 {
4916 as_warn (_("expression out of range: defaulting to 1"));
4917 offs (exp) = 1;
4918 }
4919 break;
4920 case 20:
4921 if (offs (exp) < 0 || offs (exp) > 7)
4922 goto outrange;
4923 break;
4924 case 30:
4925 if (offs (exp) < 0 || offs (exp) > 15)
4926 goto outrange;
4927 break;
4928 case 40:
4929 if (offs (exp) < 0 || offs (exp) > 32)
4930 goto outrange;
4931 break;
4932 case 50:
4933 if (offs (exp) < 0 || offs (exp) > 127)
4934 goto outrange;
4935 break;
4936 case 55:
4937 if (offs (exp) < -64 || offs (exp) > 63)
4938 goto outrange;
4939 break;
4940 case 60:
4941 if (offs (exp) < -128 || offs (exp) > 127)
4942 goto outrange;
4943 break;
4944 case 70:
4945 if (offs (exp) < 0 || offs (exp) > 4095)
4946 {
4947 outrange:
4948 as_warn (_("expression out of range: defaulting to 0"));
4949 offs (exp) = 0;
4950 }
4951 break;
4952 default:
4953 break;
4954 }
4955 }
4956 else if (exp->exp.X_op == O_big)
4957 {
4958 if (offs (exp) <= 0 /* flonum */
4959 && (ok == 80 /* no bignums */
4960 || (ok > 10 /* small-int ranges including 0 ok */
4961 /* If we have a flonum zero, a zero integer should
4962 do as well (e.g., in moveq). */
4963 && generic_floating_point_number.exponent == 0
4964 && generic_floating_point_number.low[0] == 0)))
4965 {
4966 /* HACK! Turn it into a long */
4967 LITTLENUM_TYPE words[6];
4968
4969 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4970 op (exp) = O_constant;
4971 adds (exp) = 0;
4972 subs (exp) = 0;
4973 offs (exp) = words[1] | (words[0] << 16);
4974 }
4975 else if (ok != 0)
4976 {
4977 op (exp) = O_constant;
4978 adds (exp) = 0;
4979 subs (exp) = 0;
4980 offs (exp) = (ok == 10) ? 1 : 0;
4981 as_warn (_("Can't deal with expression; defaulting to %ld"),
4982 offs (exp));
4983 }
4984 }
4985 else
4986 {
4987 if (ok >= 10 && ok <= 70)
4988 {
4989 op (exp) = O_constant;
4990 adds (exp) = 0;
4991 subs (exp) = 0;
4992 offs (exp) = (ok == 10) ? 1 : 0;
4993 as_warn (_("Can't deal with expression; defaulting to %ld"),
4994 offs (exp));
4995 }
4996 }
4997
4998 if (exp->size != SIZE_UNSPEC)
4999 {
5000 switch (exp->size)
5001 {
5002 case SIZE_UNSPEC:
5003 case SIZE_LONG:
5004 break;
5005 case SIZE_BYTE:
5006 if (!isbyte (offs (exp)))
5007 as_warn (_("expression doesn't fit in BYTE"));
5008 break;
5009 case SIZE_WORD:
5010 if (!isword (offs (exp)))
5011 as_warn (_("expression doesn't fit in WORD"));
5012 break;
5013 }
5014 }
5015
5016 return offs (exp);
5017}
5018
5019/* These are the back-ends for the various machine dependent pseudo-ops. */
5020
5021static void
5022s_data1 (ignore)
36823076 5023 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5024{
5025 subseg_set (data_section, 1);
5026 demand_empty_rest_of_line ();
5027}
5028
5029static void
5030s_data2 (ignore)
36823076 5031 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5032{
5033 subseg_set (data_section, 2);
5034 demand_empty_rest_of_line ();
5035}
5036
5037static void
5038s_bss (ignore)
36823076 5039 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5040{
5041 /* We don't support putting frags in the BSS segment, we fake it
5042 by marking in_bss, then looking at s_skip for clues. */
5043
5044 subseg_set (bss_section, 0);
5045 demand_empty_rest_of_line ();
5046}
5047
5048static void
5049s_even (ignore)
36823076 5050 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5051{
5052 register int temp;
5053 register long temp_fill;
5054
5055 temp = 1; /* JF should be 2? */
5056 temp_fill = get_absolute_expression ();
5057 if (!need_pass_2) /* Never make frag if expect extra pass. */
5058 frag_align (temp, (int) temp_fill, 0);
5059 demand_empty_rest_of_line ();
5060 record_alignment (now_seg, temp);
5061}
5062
5063static void
5064s_proc (ignore)
36823076 5065 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5066{
5067 demand_empty_rest_of_line ();
5068}
5069\f
5070/* Pseudo-ops handled for MRI compatibility. */
5071
5072/* This function returns non-zero if the argument is a conditional
5073 pseudo-op. This is called when checking whether a pending
5074 alignment is needed. */
5075
5076int
5077m68k_conditional_pseudoop (pop)
5078 pseudo_typeS *pop;
5079{
5080 return (pop->poc_handler == s_mri_if
5081 || pop->poc_handler == s_mri_else);
5082}
5083
5084/* Handle an MRI style chip specification. */
5085
5086static void
5087mri_chip ()
5088{
5089 char *s;
5090 char c;
5091 int i;
5092
5093 s = input_line_pointer;
5094 /* We can't use get_symbol_end since the processor names are not proper
5095 symbols. */
5096 while (is_part_of_name (c = *input_line_pointer++))
5097 ;
5098 *--input_line_pointer = 0;
5099 for (i = 0; i < n_archs; i++)
5100 if (strcasecmp (s, archs[i].name) == 0)
5101 break;
5102 if (i >= n_archs)
5103 {
5104 as_bad (_("%s: unrecognized processor name"), s);
5105 *input_line_pointer = c;
5106 ignore_rest_of_line ();
5107 return;
5108 }
5109 *input_line_pointer = c;
5110
5111 if (*input_line_pointer == '/')
5112 current_architecture = 0;
5113 else
5114 current_architecture &= m68881 | m68851;
5115 current_architecture |= archs[i].arch;
5116
5117 while (*input_line_pointer == '/')
5118 {
5119 ++input_line_pointer;
5120 s = input_line_pointer;
5121 /* We can't use get_symbol_end since the processor names are not
5122 proper symbols. */
5123 while (is_part_of_name (c = *input_line_pointer++))
5124 ;
5125 *--input_line_pointer = 0;
5126 if (strcmp (s, "68881") == 0)
5127 current_architecture |= m68881;
5128 else if (strcmp (s, "68851") == 0)
5129 current_architecture |= m68851;
5130 *input_line_pointer = c;
5131 }
5132
5133 /* Update info about available control registers. */
5134 select_control_regs ();
5135}
5136
5137/* The MRI CHIP pseudo-op. */
5138
5139static void
5140s_chip (ignore)
36823076 5141 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5142{
5143 char *stop = NULL;
5144 char stopc;
5145
5146 if (flag_mri)
5147 stop = mri_comment_field (&stopc);
5148 mri_chip ();
5149 if (flag_mri)
5150 mri_comment_end (stop, stopc);
5151 demand_empty_rest_of_line ();
5152}
5153
5154/* The MRI FOPT pseudo-op. */
5155
5156static void
5157s_fopt (ignore)
36823076 5158 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5159{
5160 SKIP_WHITESPACE ();
5161
5162 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5163 {
5164 int temp;
5165
5166 input_line_pointer += 3;
5167 temp = get_absolute_expression ();
5168 if (temp < 0 || temp > 7)
5169 as_bad (_("bad coprocessor id"));
5170 else
5171 m68k_float_copnum = COP0 + temp;
5172 }
5173 else
5174 {
5175 as_bad (_("unrecognized fopt option"));
5176 ignore_rest_of_line ();
5177 return;
5178 }
5179
5180 demand_empty_rest_of_line ();
5181}
5182
5183/* The structure used to handle the MRI OPT pseudo-op. */
5184
5185struct opt_action
5186{
5187 /* The name of the option. */
5188 const char *name;
5189
5190 /* If this is not NULL, just call this function. The first argument
5191 is the ARG field of this structure, the second argument is
5192 whether the option was negated. */
5193 void (*pfn) PARAMS ((int arg, int on));
5194
5195 /* If this is not NULL, and the PFN field is NULL, set the variable
5196 this points to. Set it to the ARG field if the option was not
5197 negated, and the NOTARG field otherwise. */
5198 int *pvar;
5199
5200 /* The value to pass to PFN or to assign to *PVAR. */
5201 int arg;
5202
5203 /* The value to assign to *PVAR if the option is negated. If PFN is
5204 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5205 the option may not be negated. */
5206 int notarg;
5207};
5208
5209/* The table used to handle the MRI OPT pseudo-op. */
5210
5211static void skip_to_comma PARAMS ((int, int));
5212static void opt_nest PARAMS ((int, int));
5213static void opt_chip PARAMS ((int, int));
5214static void opt_list PARAMS ((int, int));
5215static void opt_list_symbols PARAMS ((int, int));
5216
5217static const struct opt_action opt_table[] =
5218{
5219 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5220
5221 /* We do relaxing, so there is little use for these options. */
5222 { "b", 0, 0, 0, 0 },
5223 { "brs", 0, 0, 0, 0 },
5224 { "brb", 0, 0, 0, 0 },
5225 { "brl", 0, 0, 0, 0 },
5226 { "brw", 0, 0, 0, 0 },
5227
5228 { "c", 0, 0, 0, 0 },
5229 { "cex", 0, 0, 0, 0 },
5230 { "case", 0, &symbols_case_sensitive, 1, 0 },
5231 { "cl", 0, 0, 0, 0 },
5232 { "cre", 0, 0, 0, 0 },
5233 { "d", 0, &flag_keep_locals, 1, 0 },
5234 { "e", 0, 0, 0, 0 },
5235 { "f", 0, &flag_short_refs, 1, 0 },
5236 { "frs", 0, &flag_short_refs, 1, 0 },
5237 { "frl", 0, &flag_short_refs, 0, 1 },
5238 { "g", 0, 0, 0, 0 },
5239 { "i", 0, 0, 0, 0 },
5240 { "m", 0, 0, 0, 0 },
5241 { "mex", 0, 0, 0, 0 },
5242 { "mc", 0, 0, 0, 0 },
5243 { "md", 0, 0, 0, 0 },
5244 { "nest", opt_nest, 0, 0, 0 },
5245 { "next", skip_to_comma, 0, 0, 0 },
5246 { "o", 0, 0, 0, 0 },
5247 { "old", 0, 0, 0, 0 },
5248 { "op", skip_to_comma, 0, 0, 0 },
5249 { "pco", 0, 0, 0, 0 },
5250 { "p", opt_chip, 0, 0, 0 },
5251 { "pcr", 0, 0, 0, 0 },
5252 { "pcs", 0, 0, 0, 0 },
5253 { "r", 0, 0, 0, 0 },
5254 { "quick", 0, &m68k_quick, 1, 0 },
5255 { "rel32", 0, &m68k_rel32, 1, 0 },
5256 { "s", opt_list, 0, 0, 0 },
5257 { "t", opt_list_symbols, 0, 0, 0 },
5258 { "w", 0, &flag_no_warnings, 0, 1 },
5259 { "x", 0, 0, 0, 0 }
5260};
5261
5262#define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
5263
5264/* The MRI OPT pseudo-op. */
5265
5266static void
5267s_opt (ignore)
36823076 5268 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5269{
5270 do
5271 {
5272 int t;
5273 char *s;
5274 char c;
5275 int i;
5276 const struct opt_action *o;
5277
5278 SKIP_WHITESPACE ();
5279
5280 t = 1;
5281 if (*input_line_pointer == '-')
5282 {
5283 ++input_line_pointer;
5284 t = 0;
5285 }
5286 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5287 {
5288 input_line_pointer += 2;
5289 t = 0;
5290 }
5291
5292 s = input_line_pointer;
5293 c = get_symbol_end ();
5294
5295 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5296 {
5297 if (strcasecmp (s, o->name) == 0)
5298 {
5299 if (o->pfn)
5300 {
5301 /* Restore input_line_pointer now in case the option
5302 takes arguments. */
5303 *input_line_pointer = c;
5304 (*o->pfn) (o->arg, t);
5305 }
5306 else if (o->pvar != NULL)
5307 {
5308 if (! t && o->arg == o->notarg)
5309 as_bad (_("option `%s' may not be negated"), s);
5310 *input_line_pointer = c;
5311 *o->pvar = t ? o->arg : o->notarg;
5312 }
5313 else
5314 *input_line_pointer = c;
5315 break;
5316 }
5317 }
5318 if (i >= OPTCOUNT)
5319 {
5320 as_bad (_("option `%s' not recognized"), s);
5321 *input_line_pointer = c;
5322 }
5323 }
5324 while (*input_line_pointer++ == ',');
5325
5326 /* Move back to terminating character. */
5327 --input_line_pointer;
5328 demand_empty_rest_of_line ();
5329}
5330
5331/* Skip ahead to a comma. This is used for OPT options which we do
5332 not suppor tand which take arguments. */
5333
5334static void
5335skip_to_comma (arg, on)
36823076
AS		 5336 int arg ATTRIBUTE_UNUSED;
5337 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5338{
5339 while (*input_line_pointer != ','
5340 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5341 ++input_line_pointer;
5342}
5343
5344/* Handle the OPT NEST=depth option. */
5345
5346static void
5347opt_nest (arg, on)
36823076
AS		 5348 int arg ATTRIBUTE_UNUSED;
5349 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5350{
5351 if (*input_line_pointer != '=')
5352 {
5353 as_bad (_("bad format of OPT NEST=depth"));
5354 return;
5355 }
5356
5357 ++input_line_pointer;
5358 max_macro_nest = get_absolute_expression ();
5359}
5360
5361/* Handle the OPT P=chip option. */
5362
5363static void
5364opt_chip (arg, on)
36823076
AS		 5365 int arg ATTRIBUTE_UNUSED;
5366 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5367{
5368 if (*input_line_pointer != '=')
5369 {
5370 /* This is just OPT P, which we do not support. */
5371 return;
5372 }
5373
5374 ++input_line_pointer;
5375 mri_chip ();
5376}
5377
5378/* Handle the OPT S option. */
5379
5380static void
5381opt_list (arg, on)
36823076 5382 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5383 int on;
5384{
5385 listing_list (on);
5386}
5387
5388/* Handle the OPT T option. */
5389
5390static void
5391opt_list_symbols (arg, on)
36823076 5392 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5393 int on;
5394{
5395 if (on)
5396 listing |= LISTING_SYMBOLS;
5397 else
5398 listing &=~ LISTING_SYMBOLS;
5399}
5400
5401/* Handle the MRI REG pseudo-op. */
5402
5403static void
5404s_reg (ignore)
36823076 5405 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5406{
5407 char *s;
5408 int c;
5409 struct m68k_op rop;
5410 int mask;
5411 char *stop = NULL;
5412 char stopc;
5413
5414 if (line_label == NULL)
5415 {
5416 as_bad (_("missing label"));
5417 ignore_rest_of_line ();
5418 return;
5419 }
5420
5421 if (flag_mri)
5422 stop = mri_comment_field (&stopc);
5423
5424 SKIP_WHITESPACE ();
5425
5426 s = input_line_pointer;
5427 while (isalnum ((unsigned char) *input_line_pointer)
5428#ifdef REGISTER_PREFIX
5429 || *input_line_pointer == REGISTER_PREFIX
5430#endif
5431 || *input_line_pointer == '/'
5432 || *input_line_pointer == '-')
5433 ++input_line_pointer;
5434 c = *input_line_pointer;
5435 *input_line_pointer = '\0';
5436
5437 if (m68k_ip_op (s, &rop) != 0)
5438 {
5439 if (rop.error == NULL)
5440 as_bad (_("bad register list"));
5441 else
5442 as_bad (_("bad register list: %s"), rop.error);
5443 *input_line_pointer = c;
5444 ignore_rest_of_line ();
5445 return;
5446 }
5447
5448 *input_line_pointer = c;
5449
5450 if (rop.mode == REGLST)
5451 mask = rop.mask;
5452 else if (rop.mode == DREG)
5453 mask = 1 << (rop.reg - DATA0);
5454 else if (rop.mode == AREG)
5455 mask = 1 << (rop.reg - ADDR0 + 8);
5456 else if (rop.mode == FPREG)
5457 mask = 1 << (rop.reg - FP0 + 16);
5458 else if (rop.mode == CONTROL
5459 && rop.reg == FPI)
5460 mask = 1 << 24;
5461 else if (rop.mode == CONTROL
5462 && rop.reg == FPS)
5463 mask = 1 << 25;
5464 else if (rop.mode == CONTROL
5465 && rop.reg == FPC)
5466 mask = 1 << 26;
5467 else
5468 {
5469 as_bad (_("bad register list"));
5470 ignore_rest_of_line ();
5471 return;
5472 }
5473
5474 S_SET_SEGMENT (line_label, reg_section);
5475 S_SET_VALUE (line_label, ~mask);
49309057 5476 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5477
5478 if (flag_mri)
5479 mri_comment_end (stop, stopc);
5480
5481 demand_empty_rest_of_line ();
5482}
5483
5484/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5485
5486struct save_opts
5487{
5488 struct save_opts *next;
5489 int abspcadd;
5490 int symbols_case_sensitive;
5491 int keep_locals;
5492 int short_refs;
5493 int architecture;
5494 int quick;
5495 int rel32;
5496 int listing;
5497 int no_warnings;
5498 /* FIXME: We don't save OPT S. */
5499};
5500
5501/* This variable holds the stack of saved options. */
5502
5503static struct save_opts *save_stack;
5504
5505/* The MRI SAVE pseudo-op. */
5506
5507static void
5508s_save (ignore)
36823076 5509 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5510{
5511 struct save_opts *s;
5512
5513 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5514 s->abspcadd = m68k_abspcadd;
5515 s->symbols_case_sensitive = symbols_case_sensitive;
5516 s->keep_locals = flag_keep_locals;
5517 s->short_refs = flag_short_refs;
5518 s->architecture = current_architecture;
5519 s->quick = m68k_quick;
5520 s->rel32 = m68k_rel32;
5521 s->listing = listing;
5522 s->no_warnings = flag_no_warnings;
5523
5524 s->next = save_stack;
5525 save_stack = s;
5526
5527 demand_empty_rest_of_line ();
5528}
5529
5530/* The MRI RESTORE pseudo-op. */
5531
5532static void
5533s_restore (ignore)
36823076 5534 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5535{
5536 struct save_opts *s;
5537
5538 if (save_stack == NULL)
5539 {
5540 as_bad (_("restore without save"));
5541 ignore_rest_of_line ();
5542 return;
5543 }
5544
5545 s = save_stack;
5546 save_stack = s->next;
5547
5548 m68k_abspcadd = s->abspcadd;
5549 symbols_case_sensitive = s->symbols_case_sensitive;
5550 flag_keep_locals = s->keep_locals;
5551 flag_short_refs = s->short_refs;
5552 current_architecture = s->architecture;
5553 m68k_quick = s->quick;
5554 m68k_rel32 = s->rel32;
5555 listing = s->listing;
5556 flag_no_warnings = s->no_warnings;
5557
5558 free (s);
5559
5560 demand_empty_rest_of_line ();
5561}
5562
5563/* Types of MRI structured control directives. */
5564
5565enum mri_control_type
5566{
5567 mri_for,
5568 mri_if,
5569 mri_repeat,
5570 mri_while
5571};
5572
5573/* This structure is used to stack the MRI structured control
5574 directives. */
5575
5576struct mri_control_info
5577{
5578 /* The directive within which this one is enclosed. */
5579 struct mri_control_info *outer;
5580
5581 /* The type of directive. */
5582 enum mri_control_type type;
5583
5584 /* Whether an ELSE has been in an IF. */
5585 int else_seen;
5586
5587 /* The add or sub statement at the end of a FOR. */
5588 char *incr;
5589
5590 /* The label of the top of a FOR or REPEAT loop. */
5591 char *top;
5592
5593 /* The label to jump to for the next iteration, or the else
5594 expression of a conditional. */
5595 char *next;
5596
5597 /* The label to jump to to break out of the loop, or the label past
5598 the end of a conditional. */
5599 char *bottom;
5600};
5601
5602/* The stack of MRI structured control directives. */
5603
5604static struct mri_control_info *mri_control_stack;
5605
5606/* The current MRI structured control directive index number, used to
5607 generate label names. */
5608
5609static int mri_control_index;
5610
5611/* Some function prototypes. */
5612
5613static void mri_assemble PARAMS ((char *));
5614static char *mri_control_label PARAMS ((void));
5615static struct mri_control_info *push_mri_control
5616 PARAMS ((enum mri_control_type));
5617static void pop_mri_control PARAMS ((void));
5618static int parse_mri_condition PARAMS ((int *));
5619static int parse_mri_control_operand
5620 PARAMS ((int *, char **, char **, char **, char **));
5621static int swap_mri_condition PARAMS ((int));
5622static int reverse_mri_condition PARAMS ((int));
5623static void build_mri_control_operand
5624 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5625 const char *, int));
5626static void parse_mri_control_expression
5627 PARAMS ((char *, int, const char *, const char *, int));
5628
5629/* Assemble an instruction for an MRI structured control directive. */
5630
5631static void
5632mri_assemble (str)
5633 char *str;
5634{
5635 char *s;
5636
5637 /* md_assemble expects the opcode to be in lower case. */
5638 for (s = str; *s != ' ' && *s != '\0'; s++)
5639 {
5640 if (isupper ((unsigned char) *s))
5641 *s = tolower ((unsigned char) *s);
5642 }
5643
5644 md_assemble (str);
5645}
5646
5647/* Generate a new MRI label structured control directive label name. */
5648
5649static char *
5650mri_control_label ()
5651{
5652 char *n;
5653
5654 n = (char *) xmalloc (20);
5655 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5656 ++mri_control_index;
5657 return n;
5658}
5659
5660/* Create a new MRI structured control directive. */
5661
5662static struct mri_control_info *
5663push_mri_control (type)
5664 enum mri_control_type type;
5665{
5666 struct mri_control_info *n;
5667
5668 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5669
5670 n->type = type;
5671 n->else_seen = 0;
5672 if (type == mri_if || type == mri_while)
5673 n->top = NULL;
5674 else
5675 n->top = mri_control_label ();
5676 n->next = mri_control_label ();
5677 n->bottom = mri_control_label ();
5678
5679 n->outer = mri_control_stack;
5680 mri_control_stack = n;
5681
5682 return n;
5683}
5684
5685/* Pop off the stack of MRI structured control directives. */
5686
5687static void
5688pop_mri_control ()
5689{
5690 struct mri_control_info *n;
5691
5692 n = mri_control_stack;
5693 mri_control_stack = n->outer;
5694 if (n->top != NULL)
5695 free (n->top);
5696 free (n->next);
5697 free (n->bottom);
5698 free (n);
5699}
5700
5701/* Recognize a condition code in an MRI structured control expression. */
5702
5703static int
5704parse_mri_condition (pcc)
5705 int *pcc;
5706{
5707 char c1, c2;
5708
5709 know (*input_line_pointer == '<');
5710
5711 ++input_line_pointer;
5712 c1 = *input_line_pointer++;
5713 c2 = *input_line_pointer++;
5714
5715 if (*input_line_pointer != '>')
5716 {
5717 as_bad (_("syntax error in structured control directive"));
5718 return 0;
5719 }
5720
5721 ++input_line_pointer;
5722 SKIP_WHITESPACE ();
5723
5724 if (isupper (c1))
5725 c1 = tolower (c1);
5726 if (isupper (c2))
5727 c2 = tolower (c2);
5728
5729 *pcc = (c1 << 8) | c2;
5730
5731 return 1;
5732}
5733
5734/* Parse a single operand in an MRI structured control expression. */
5735
5736static int
5737parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5738 int *pcc;
5739 char **leftstart;
5740 char **leftstop;
5741 char **rightstart;
5742 char **rightstop;
5743{
5744 char *s;
5745
5746 SKIP_WHITESPACE ();
5747
5748 *pcc = -1;
5749 *leftstart = NULL;
5750 *leftstop = NULL;
5751 *rightstart = NULL;
5752 *rightstop = NULL;
5753
5754 if (*input_line_pointer == '<')
5755 {
5756 /* It's just a condition code. */
5757 return parse_mri_condition (pcc);
5758 }
5759
5760 /* Look ahead for the condition code. */
5761 for (s = input_line_pointer; *s != '\0'; ++s)
5762 {
5763 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5764 break;
5765 }
5766 if (*s == '\0')
5767 {
5768 as_bad (_("missing condition code in structured control directive"));
5769 return 0;
5770 }
5771
5772 *leftstart = input_line_pointer;
5773 *leftstop = s;
5774 if (*leftstop > *leftstart
5775 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5776 --*leftstop;
5777
5778 input_line_pointer = s;
5779 if (! parse_mri_condition (pcc))
5780 return 0;
5781
5782 /* Look ahead for AND or OR or end of line. */
5783 for (s = input_line_pointer; *s != '\0'; ++s)
5784 {
5785 if ((strncasecmp (s, "AND", 3) == 0
5786 && (s[3] == '.' || ! is_part_of_name (s[3])))
5787 || (strncasecmp (s, "OR", 2) == 0
5788 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5789 break;
5790 }
5791
5792 *rightstart = input_line_pointer;
5793 *rightstop = s;
5794 if (*rightstop > *rightstart
5795 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5796 --*rightstop;
5797
5798 input_line_pointer = s;
5799
5800 return 1;
5801}
5802
5803#define MCC(b1, b2) (((b1) << 8) | (b2))
5804
5805/* Swap the sense of a condition. This changes the condition so that
5806 it generates the same result when the operands are swapped. */
5807
5808static int
5809swap_mri_condition (cc)
5810 int cc;
5811{
5812 switch (cc)
5813 {
5814 case MCC ('h', 'i'): return MCC ('c', 's');
5815 case MCC ('l', 's'): return MCC ('c', 'c');
5816 case MCC ('c', 'c'): return MCC ('l', 's');
5817 case MCC ('c', 's'): return MCC ('h', 'i');
5818 case MCC ('p', 'l'): return MCC ('m', 'i');
5819 case MCC ('m', 'i'): return MCC ('p', 'l');
5820 case MCC ('g', 'e'): return MCC ('l', 'e');
5821 case MCC ('l', 't'): return MCC ('g', 't');
5822 case MCC ('g', 't'): return MCC ('l', 't');
5823 case MCC ('l', 'e'): return MCC ('g', 'e');
5824 }
5825 return cc;
5826}
5827
5828/* Reverse the sense of a condition. */
5829
5830static int
5831reverse_mri_condition (cc)
5832 int cc;
5833{
5834 switch (cc)
5835 {
5836 case MCC ('h', 'i'): return MCC ('l', 's');
5837 case MCC ('l', 's'): return MCC ('h', 'i');
5838 case MCC ('c', 'c'): return MCC ('c', 's');
5839 case MCC ('c', 's'): return MCC ('c', 'c');
5840 case MCC ('n', 'e'): return MCC ('e', 'q');
5841 case MCC ('e', 'q'): return MCC ('n', 'e');
5842 case MCC ('v', 'c'): return MCC ('v', 's');
5843 case MCC ('v', 's'): return MCC ('v', 'c');
5844 case MCC ('p', 'l'): return MCC ('m', 'i');
5845 case MCC ('m', 'i'): return MCC ('p', 'l');
5846 case MCC ('g', 'e'): return MCC ('l', 't');
5847 case MCC ('l', 't'): return MCC ('g', 'e');
5848 case MCC ('g', 't'): return MCC ('l', 'e');
5849 case MCC ('l', 'e'): return MCC ('g', 't');
5850 }
5851 return cc;
5852}
5853
5854/* Build an MRI structured control expression. This generates test
5855 and branch instructions. It goes to TRUELAB if the condition is
5856 true, and to FALSELAB if the condition is false. Exactly one of
5857 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5858 is the size qualifier for the expression. EXTENT is the size to
5859 use for the branch. */
5860
5861static void
5862build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5863 rightstop, truelab, falselab, extent)
5864 int qual;
5865 int cc;
5866 char *leftstart;
5867 char *leftstop;
5868 char *rightstart;
5869 char *rightstop;
5870 const char *truelab;
5871 const char *falselab;
5872 int extent;
5873{
5874 char *buf;
5875 char *s;
5876
5877 if (leftstart != NULL)
5878 {
5879 struct m68k_op leftop, rightop;
5880 char c;
5881
5882 /* Swap the compare operands, if necessary, to produce a legal
5883 m68k compare instruction. Comparing a register operand with
5884 a non-register operand requires the register to be on the
5885 right (cmp, cmpa). Comparing an immediate value with
5886 anything requires the immediate value to be on the left
5887 (cmpi). */
5888
5889 c = *leftstop;
5890 *leftstop = '\0';
5891 (void) m68k_ip_op (leftstart, &leftop);
5892 *leftstop = c;
5893
5894 c = *rightstop;
5895 *rightstop = '\0';
5896 (void) m68k_ip_op (rightstart, &rightop);
5897 *rightstop = c;
5898
5899 if (rightop.mode == IMMED
5900 || ((leftop.mode == DREG || leftop.mode == AREG)
5901 && (rightop.mode != DREG && rightop.mode != AREG)))
5902 {
5903 char *temp;
5904
5905 cc = swap_mri_condition (cc);
5906 temp = leftstart;
5907 leftstart = rightstart;
5908 rightstart = temp;
5909 temp = leftstop;
5910 leftstop = rightstop;
5911 rightstop = temp;
5912 }
5913 }
5914
5915 if (truelab == NULL)
5916 {
5917 cc = reverse_mri_condition (cc);
5918 truelab = falselab;
5919 }
5920
5921 if (leftstart != NULL)
5922 {
5923 buf = (char *) xmalloc (20
5924 + (leftstop - leftstart)
5925 + (rightstop - rightstart));
5926 s = buf;
5927 *s++ = 'c';
5928 *s++ = 'm';
5929 *s++ = 'p';
5930 if (qual != '\0')
5931 *s++ = qual;
5932 *s++ = ' ';
5933 memcpy (s, leftstart, leftstop - leftstart);
5934 s += leftstop - leftstart;
5935 *s++ = ',';
5936 memcpy (s, rightstart, rightstop - rightstart);
5937 s += rightstop - rightstart;
5938 *s = '\0';
5939 mri_assemble (buf);
5940 free (buf);
5941 }
5942
5943 buf = (char *) xmalloc (20 + strlen (truelab));
5944 s = buf;
5945 *s++ = 'b';
5946 *s++ = cc >> 8;
5947 *s++ = cc & 0xff;
5948 if (extent != '\0')
5949 *s++ = extent;
5950 *s++ = ' ';
5951 strcpy (s, truelab);
5952 mri_assemble (buf);
5953 free (buf);
5954}
5955
5956/* Parse an MRI structured control expression. This generates test
5957 and branch instructions. STOP is where the expression ends. It
5958 goes to TRUELAB if the condition is true, and to FALSELAB if the
5959 condition is false. Exactly one of TRUELAB and FALSELAB will be
5960 NULL, meaning to fall through. QUAL is the size qualifier for the
5961 expression. EXTENT is the size to use for the branch. */
5962
5963static void
5964parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5965 char *stop;
5966 int qual;
5967 const char *truelab;
5968 const char *falselab;
5969 int extent;
5970{
5971 int c;
5972 int cc;
5973 char *leftstart;
5974 char *leftstop;
5975 char *rightstart;
5976 char *rightstop;
5977
5978 c = *stop;
5979 *stop = '\0';
5980
5981 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5982 &rightstart, &rightstop))
5983 {
5984 *stop = c;
5985 return;
5986 }
5987
5988 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5989 {
5990 const char *flab;
5991
5992 if (falselab != NULL)
5993 flab = falselab;
5994 else
5995 flab = mri_control_label ();
5996
5997 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5998 rightstop, (const char *) NULL, flab, extent);
5999
6000 input_line_pointer += 3;
6001 if (*input_line_pointer != '.'
6002 || input_line_pointer[1] == '\0')
6003 qual = '\0';
6004 else
6005 {
6006 qual = input_line_pointer[1];
6007 input_line_pointer += 2;
6008 }
6009
6010 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6011 &rightstart, &rightstop))
6012 {
6013 *stop = c;
6014 return;
6015 }
6016
6017 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6018 rightstop, truelab, falselab, extent);
6019
6020 if (falselab == NULL)
6021 colon (flab);
6022 }
6023 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6024 {
6025 const char *tlab;
6026
6027 if (truelab != NULL)
6028 tlab = truelab;
6029 else
6030 tlab = mri_control_label ();
6031
6032 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6033 rightstop, tlab, (const char *) NULL, extent);
6034
6035 input_line_pointer += 2;
6036 if (*input_line_pointer != '.'
6037 || input_line_pointer[1] == '\0')
6038 qual = '\0';
6039 else
6040 {
6041 qual = input_line_pointer[1];
6042 input_line_pointer += 2;
6043 }
6044
6045 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6046 &rightstart, &rightstop))
6047 {
6048 *stop = c;
6049 return;
6050 }
6051
6052 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6053 rightstop, truelab, falselab, extent);
6054
6055 if (truelab == NULL)
6056 colon (tlab);
6057 }
6058 else
6059 {
6060 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6061 rightstop, truelab, falselab, extent);
6062 }
6063
6064 *stop = c;
6065 if (input_line_pointer != stop)
6066 as_bad (_("syntax error in structured control directive"));
6067}
6068
6069/* Handle the MRI IF pseudo-op. This may be a structured control
6070 directive, or it may be a regular assembler conditional, depending
6071 on its operands. */
6072
6073static void
6074s_mri_if (qual)
6075 int qual;
6076{
6077 char *s;
6078 int c;
6079 struct mri_control_info *n;
6080
6081 /* A structured control directive must end with THEN with an
6082 optional qualifier. */
6083 s = input_line_pointer;
6084 while (! is_end_of_line[(unsigned char) *s]
6085 && (! flag_mri || *s != '*'))
6086 ++s;
6087 --s;
6088 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6089 --s;
6090
6091 if (s - input_line_pointer > 1
6092 && s[-1] == '.')
6093 s -= 2;
6094
6095 if (s - input_line_pointer < 3
6096 || strncasecmp (s - 3, "THEN", 4) != 0)
6097 {
6098 if (qual != '\0')
6099 {
6100 as_bad (_("missing then"));
6101 ignore_rest_of_line ();
6102 return;
6103 }
6104
6105 /* It's a conditional. */
6106 s_if (O_ne);
6107 return;
6108 }
6109
6110 /* Since this might be a conditional if, this pseudo-op will be
6111 called even if we are supported to be ignoring input. Double
6112 check now. Clobber *input_line_pointer so that ignore_input
6113 thinks that this is not a special pseudo-op. */
6114 c = *input_line_pointer;
6115 *input_line_pointer = 0;
6116 if (ignore_input ())
6117 {
6118 *input_line_pointer = c;
6119 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6120 ++input_line_pointer;
6121 demand_empty_rest_of_line ();
6122 return;
6123 }
6124 *input_line_pointer = c;
6125
6126 n = push_mri_control (mri_if);
6127
6128 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6129 n->next, s[1] == '.' ? s[2] : '\0');
6130
6131 if (s[1] == '.')
6132 input_line_pointer = s + 3;
6133 else
6134 input_line_pointer = s + 1;
6135
6136 if (flag_mri)
6137 {
6138 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6139 ++input_line_pointer;
6140 }
6141
6142 demand_empty_rest_of_line ();
6143}
6144
6145/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6146 structured IF, associate the ELSE with the IF. Otherwise, assume
6147 it is a conditional else. */
6148
6149static void
6150s_mri_else (qual)
6151 int qual;
6152{
6153 int c;
6154 char *buf;
6155 char q[2];
6156
6157 if (qual == '\0'
6158 && (mri_control_stack == NULL
6159 || mri_control_stack->type != mri_if
6160 || mri_control_stack->else_seen))
6161 {
6162 s_else (0);
6163 return;
6164 }
6165
6166 c = *input_line_pointer;
6167 *input_line_pointer = 0;
6168 if (ignore_input ())
6169 {
6170 *input_line_pointer = c;
6171 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6172 ++input_line_pointer;
6173 demand_empty_rest_of_line ();
6174 return;
6175 }
6176 *input_line_pointer = c;
6177
6178 if (mri_control_stack == NULL
6179 || mri_control_stack->type != mri_if
6180 || mri_control_stack->else_seen)
6181 {
6182 as_bad (_("else without matching if"));
6183 ignore_rest_of_line ();
6184 return;
6185 }
6186
6187 mri_control_stack->else_seen = 1;
6188
6189 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6190 q[0] = qual;
6191 q[1] = '\0';
6192 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6193 mri_assemble (buf);
6194 free (buf);
6195
6196 colon (mri_control_stack->next);
6197
6198 if (flag_mri)
6199 {
6200 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6201 ++input_line_pointer;
6202 }
6203
6204 demand_empty_rest_of_line ();
6205}
6206
6207/* Handle the MRI ENDI pseudo-op. */
6208
6209static void
6210s_mri_endi (ignore)
36823076 6211 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6212{
6213 if (mri_control_stack == NULL
6214 || mri_control_stack->type != mri_if)
6215 {
6216 as_bad (_("endi without matching if"));
6217 ignore_rest_of_line ();
6218 return;
6219 }
6220
6221 /* ignore_input will not return true for ENDI, so we don't need to
6222 worry about checking it again here. */
6223
6224 if (! mri_control_stack->else_seen)
6225 colon (mri_control_stack->next);
6226 colon (mri_control_stack->bottom);
6227
6228 pop_mri_control ();
6229
6230 if (flag_mri)
6231 {
6232 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6233 ++input_line_pointer;
6234 }
6235
6236 demand_empty_rest_of_line ();
6237}
6238
6239/* Handle the MRI BREAK pseudo-op. */
6240
6241static void
6242s_mri_break (extent)
6243 int extent;
6244{
6245 struct mri_control_info *n;
6246 char *buf;
6247 char ex[2];
6248
6249 n = mri_control_stack;
6250 while (n != NULL
6251 && n->type != mri_for
6252 && n->type != mri_repeat
6253 && n->type != mri_while)
6254 n = n->outer;
6255 if (n == NULL)
6256 {
6257 as_bad (_("break outside of structured loop"));
6258 ignore_rest_of_line ();
6259 return;
6260 }
6261
6262 buf = (char *) xmalloc (20 + strlen (n->bottom));
6263 ex[0] = extent;
6264 ex[1] = '\0';
6265 sprintf (buf, "bra%s %s", ex, n->bottom);
6266 mri_assemble (buf);
6267 free (buf);
6268
6269 if (flag_mri)
6270 {
6271 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6272 ++input_line_pointer;
6273 }
6274
6275 demand_empty_rest_of_line ();
6276}
6277
6278/* Handle the MRI NEXT pseudo-op. */
6279
6280static void
6281s_mri_next (extent)
6282 int extent;
6283{
6284 struct mri_control_info *n;
6285 char *buf;
6286 char ex[2];
6287
6288 n = mri_control_stack;
6289 while (n != NULL
6290 && n->type != mri_for
6291 && n->type != mri_repeat
6292 && n->type != mri_while)
6293 n = n->outer;
6294 if (n == NULL)
6295 {
6296 as_bad (_("next outside of structured loop"));
6297 ignore_rest_of_line ();
6298 return;
6299 }
6300
6301 buf = (char *) xmalloc (20 + strlen (n->next));
6302 ex[0] = extent;
6303 ex[1] = '\0';
6304 sprintf (buf, "bra%s %s", ex, n->next);
6305 mri_assemble (buf);
6306 free (buf);
6307
6308 if (flag_mri)
6309 {
6310 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6311 ++input_line_pointer;
6312 }
6313
6314 demand_empty_rest_of_line ();
6315}
6316
6317/* Handle the MRI FOR pseudo-op. */
6318
6319static void
6320s_mri_for (qual)
6321 int qual;
6322{
6323 const char *varstart, *varstop;
6324 const char *initstart, *initstop;
6325 const char *endstart, *endstop;
6326 const char *bystart, *bystop;
6327 int up;
6328 int by;
6329 int extent;
6330 struct mri_control_info *n;
6331 char *buf;
6332 char *s;
6333 char ex[2];
6334
6335 /* The syntax is
6336 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6337 */
6338
6339 SKIP_WHITESPACE ();
6340 varstart = input_line_pointer;
6341
6342 /* Look for the '='. */
6343 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6344 && *input_line_pointer != '=')
6345 ++input_line_pointer;
6346 if (*input_line_pointer != '=')
6347 {
6348 as_bad (_("missing ="));
6349 ignore_rest_of_line ();
6350 return;
6351 }
6352
6353 varstop = input_line_pointer;
6354 if (varstop > varstart
6355 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6356 --varstop;
6357
6358 ++input_line_pointer;
6359
6360 initstart = input_line_pointer;
6361
6362 /* Look for TO or DOWNTO. */
6363 up = 1;
6364 initstop = NULL;
6365 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6366 {
6367 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6368 && ! is_part_of_name (input_line_pointer[2]))
6369 {
6370 initstop = input_line_pointer;
6371 input_line_pointer += 2;
6372 break;
6373 }
6374 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6375 && ! is_part_of_name (input_line_pointer[6]))
6376 {
6377 initstop = input_line_pointer;
6378 up = 0;
6379 input_line_pointer += 6;
6380 break;
6381 }
6382 ++input_line_pointer;
6383 }
6384 if (initstop == NULL)
6385 {
6386 as_bad (_("missing to or downto"));
6387 ignore_rest_of_line ();
6388 return;
6389 }
6390 if (initstop > initstart
6391 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6392 --initstop;
6393
6394 SKIP_WHITESPACE ();
6395 endstart = input_line_pointer;
6396
6397 /* Look for BY or DO. */
6398 by = 0;
6399 endstop = NULL;
6400 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6401 {
6402 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6403 && ! is_part_of_name (input_line_pointer[2]))
6404 {
6405 endstop = input_line_pointer;
6406 by = 1;
6407 input_line_pointer += 2;
6408 break;
6409 }
6410 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6411 && (input_line_pointer[2] == '.'
6412 || ! is_part_of_name (input_line_pointer[2])))
6413 {
6414 endstop = input_line_pointer;
6415 input_line_pointer += 2;
6416 break;
6417 }
6418 ++input_line_pointer;
6419 }
6420 if (endstop == NULL)
6421 {
6422 as_bad (_("missing do"));
6423 ignore_rest_of_line ();
6424 return;
6425 }
6426 if (endstop > endstart
6427 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6428 --endstop;
6429
6430 if (! by)
6431 {
6432 bystart = "#1";
6433 bystop = bystart + 2;
6434 }
6435 else
6436 {
6437 SKIP_WHITESPACE ();
6438 bystart = input_line_pointer;
6439
6440 /* Look for DO. */
6441 bystop = NULL;
6442 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6443 {
6444 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6445 && (input_line_pointer[2] == '.'
6446 || ! is_part_of_name (input_line_pointer[2])))
6447 {
6448 bystop = input_line_pointer;
6449 input_line_pointer += 2;
6450 break;
6451 }
6452 ++input_line_pointer;
6453 }
6454 if (bystop == NULL)
6455 {
6456 as_bad (_("missing do"));
6457 ignore_rest_of_line ();
6458 return;
6459 }
6460 if (bystop > bystart
6461 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6462 --bystop;
6463 }
6464
6465 if (*input_line_pointer != '.')
6466 extent = '\0';
6467 else
6468 {
6469 extent = input_line_pointer[1];
6470 input_line_pointer += 2;
6471 }
6472
6473 /* We have fully parsed the FOR operands. Now build the loop. */
6474
6475 n = push_mri_control (mri_for);
6476
6477 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6478
6479 /* move init,var */
6480 s = buf;
6481 *s++ = 'm';
6482 *s++ = 'o';
6483 *s++ = 'v';
6484 *s++ = 'e';
6485 if (qual != '\0')
6486 *s++ = qual;
6487 *s++ = ' ';
6488 memcpy (s, initstart, initstop - initstart);
6489 s += initstop - initstart;
6490 *s++ = ',';
6491 memcpy (s, varstart, varstop - varstart);
6492 s += varstop - varstart;
6493 *s = '\0';
6494 mri_assemble (buf);
6495
6496 colon (n->top);
6497
6498 /* cmp end,var */
6499 s = buf;
6500 *s++ = 'c';
6501 *s++ = 'm';
6502 *s++ = 'p';
6503 if (qual != '\0')
6504 *s++ = qual;
6505 *s++ = ' ';
6506 memcpy (s, endstart, endstop - endstart);
6507 s += endstop - endstart;
6508 *s++ = ',';
6509 memcpy (s, varstart, varstop - varstart);
6510 s += varstop - varstart;
6511 *s = '\0';
6512 mri_assemble (buf);
6513
6514 /* bcc bottom */
6515 ex[0] = extent;
6516 ex[1] = '\0';
6517 if (up)
6518 sprintf (buf, "blt%s %s", ex, n->bottom);
6519 else
6520 sprintf (buf, "bgt%s %s", ex, n->bottom);
6521 mri_assemble (buf);
6522
6523 /* Put together the add or sub instruction used by ENDF. */
6524 s = buf;
6525 if (up)
6526 strcpy (s, "add");
6527 else
6528 strcpy (s, "sub");
6529 s += 3;
6530 if (qual != '\0')
6531 *s++ = qual;
6532 *s++ = ' ';
6533 memcpy (s, bystart, bystop - bystart);
6534 s += bystop - bystart;
6535 *s++ = ',';
6536 memcpy (s, varstart, varstop - varstart);
6537 s += varstop - varstart;
6538 *s = '\0';
6539 n->incr = buf;
6540
6541 if (flag_mri)
6542 {
6543 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6544 ++input_line_pointer;
6545 }
6546
6547 demand_empty_rest_of_line ();
6548}
6549
6550/* Handle the MRI ENDF pseudo-op. */
6551
6552static void
6553s_mri_endf (ignore)
36823076 6554 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6555{
6556 if (mri_control_stack == NULL
6557 || mri_control_stack->type != mri_for)
6558 {
6559 as_bad (_("endf without for"));
6560 ignore_rest_of_line ();
6561 return;
6562 }
6563
6564 colon (mri_control_stack->next);
6565
6566 mri_assemble (mri_control_stack->incr);
6567
6568 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6569 mri_assemble (mri_control_stack->incr);
6570
6571 free (mri_control_stack->incr);
6572
6573 colon (mri_control_stack->bottom);
6574
6575 pop_mri_control ();
6576
6577 if (flag_mri)
6578 {
6579 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6580 ++input_line_pointer;
6581 }
6582
6583 demand_empty_rest_of_line ();
6584}
6585
6586/* Handle the MRI REPEAT pseudo-op. */
6587
6588static void
6589s_mri_repeat (ignore)
36823076 6590 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6591{
6592 struct mri_control_info *n;
6593
6594 n = push_mri_control (mri_repeat);
6595 colon (n->top);
6596 if (flag_mri)
6597 {
6598 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6599 ++input_line_pointer;
6600 }
6601 demand_empty_rest_of_line ();
6602}
6603
6604/* Handle the MRI UNTIL pseudo-op. */
6605
6606static void
6607s_mri_until (qual)
6608 int qual;
6609{
6610 char *s;
6611
6612 if (mri_control_stack == NULL
6613 || mri_control_stack->type != mri_repeat)
6614 {
6615 as_bad (_("until without repeat"));
6616 ignore_rest_of_line ();
6617 return;
6618 }
6619
6620 colon (mri_control_stack->next);
6621
6622 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6623 ;
6624
6625 parse_mri_control_expression (s, qual, (const char *) NULL,
6626 mri_control_stack->top, '\0');
6627
6628 colon (mri_control_stack->bottom);
6629
6630 input_line_pointer = s;
6631
6632 pop_mri_control ();
6633
6634 if (flag_mri)
6635 {
6636 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6637 ++input_line_pointer;
6638 }
6639
6640 demand_empty_rest_of_line ();
6641}
6642
6643/* Handle the MRI WHILE pseudo-op. */
6644
6645static void
6646s_mri_while (qual)
6647 int qual;
6648{
6649 char *s;
6650
6651 struct mri_control_info *n;
6652
6653 s = input_line_pointer;
6654 while (! is_end_of_line[(unsigned char) *s]
6655 && (! flag_mri || *s != '*'))
6656 s++;
6657 --s;
6658 while (*s == ' ' || *s == '\t')
6659 --s;
6660 if (s - input_line_pointer > 1
6661 && s[-1] == '.')
6662 s -= 2;
6663 if (s - input_line_pointer < 2
6664 || strncasecmp (s - 1, "DO", 2) != 0)
6665 {
6666 as_bad (_("missing do"));
6667 ignore_rest_of_line ();
6668 return;
6669 }
6670
6671 n = push_mri_control (mri_while);
6672
6673 colon (n->next);
6674
6675 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6676 s[1] == '.' ? s[2] : '\0');
6677
6678 input_line_pointer = s + 1;
6679 if (*input_line_pointer == '.')
6680 input_line_pointer += 2;
6681
6682 if (flag_mri)
6683 {
6684 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6685 ++input_line_pointer;
6686 }
6687
6688 demand_empty_rest_of_line ();
6689}
6690
6691/* Handle the MRI ENDW pseudo-op. */
6692
6693static void
6694s_mri_endw (ignore)
36823076 6695 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6696{
6697 char *buf;
6698
6699 if (mri_control_stack == NULL
6700 || mri_control_stack->type != mri_while)
6701 {
6702 as_bad (_("endw without while"));
6703 ignore_rest_of_line ();
6704 return;
6705 }
6706
6707 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6708 sprintf (buf, "bra %s", mri_control_stack->next);
6709 mri_assemble (buf);
6710 free (buf);
6711
6712 colon (mri_control_stack->bottom);
6713
6714 pop_mri_control ();
6715
6716 if (flag_mri)
6717 {
6718 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6719 ++input_line_pointer;
6720 }
6721
6722 demand_empty_rest_of_line ();
6723}
6724\f
6725/*
6726 * md_parse_option
6727 * Invocation line includes a switch not recognized by the base assembler.
6728 * See if it's a processor-specific option. These are:
6729 *
6730 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6731 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6732 * Select the architecture. Instructions or features not
6733 * supported by the selected architecture cause fatal
6734 * errors. More than one may be specified. The default is
6735 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6736 * for -m68000, and -m68882 is a synonym for -m68881.
6737 * -[A]m[c]no-68851, -[A]m[c]no-68881
6738 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6739 * so don't use or document it, but that's the way the parsing
6740 * works).
6741 *
6742 * -pic Indicates PIC.
6743 * -k Indicates PIC. (Sun 3 only.)
6744 *
6745 * --bitwise-or
6746 * Permit `|' to be used in expressions.
6747 *
6748 */
6749
6750#ifdef OBJ_ELF
6751CONST char *md_shortopts = "lSA:m:kQ:V";
6752#else
6753CONST char *md_shortopts = "lSA:m:k";
6754#endif
6755
6756struct option md_longopts[] = {
6757#define OPTION_PIC (OPTION_MD_BASE)
6758 {"pic", no_argument, NULL, OPTION_PIC},
6759#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6760 {"register-prefix-optional", no_argument, NULL,
6761 OPTION_REGISTER_PREFIX_OPTIONAL},
6762#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6763 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6764#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6765 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6766#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6767 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6768#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6769 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6770#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6771 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6772 {NULL, no_argument, NULL, 0}
6773};
6774size_t md_longopts_size = sizeof(md_longopts);
6775
6776int
6777md_parse_option (c, arg)
6778 int c;
6779 char *arg;
6780{
6781 switch (c)
6782 {
6783 case 'l': /* -l means keep external to 2 bit offset
6784 rather than 16 bit one */
6785 flag_short_refs = 1;
6786 break;
6787
6788 case 'S': /* -S means that jbsr's always turn into
6789 jsr's. */
6790 flag_long_jumps = 1;
6791 break;
6792
6793 case 'A':
6794 if (*arg == 'm')
6795 arg++;
6796 /* intentional fall-through */
6797 case 'm':
6798
6799 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6800 {
6801 int i;
6802 unsigned long arch;
6803 const char *oarg = arg;
6804
6805 arg += 3;
6806 if (*arg == 'm')
6807 {
6808 arg++;
6809 if (arg[0] == 'c' && arg[1] == '6')
6810 arg++;
6811 }
6812 for (i = 0; i < n_archs; i++)
6813 if (!strcmp (arg, archs[i].name))
6814 break;
6815 if (i == n_archs)
6816 {
6817 unknown:
6818 as_bad (_("unrecognized option `%s'"), oarg);
6819 return 0;
6820 }
6821 arch = archs[i].arch;
6822 if (arch == m68881)
6823 no_68881 = 1;
6824 else if (arch == m68851)
6825 no_68851 = 1;
6826 else
6827 goto unknown;
6828 }
6829 else
6830 {
6831 int i;
6832
6833 if (arg[0] == 'c' && arg[1] == '6')
6834 arg++;
6835
6836 for (i = 0; i < n_archs; i++)
6837 if (!strcmp (arg, archs[i].name))
6838 {
6839 unsigned long arch = archs[i].arch;
6840 if (cpu_of_arch (arch))
6841 /* It's a cpu spec. */
6842 {
6843 current_architecture &= ~m68000up;
6844 current_architecture |= arch;
6845 }
6846 else if (arch == m68881)
6847 {
6848 current_architecture |= m68881;
6849 no_68881 = 0;
6850 }
6851 else if (arch == m68851)
6852 {
6853 current_architecture |= m68851;
6854 no_68851 = 0;
6855 }
6856 else
6857 /* ??? */
6858 abort ();
6859 break;
6860 }
6861 if (i == n_archs)
6862 {
6863 as_bad (_("unrecognized architecture specification `%s'"), arg);
6864 return 0;
6865 }
6866 }
6867 break;
6868
6869 case OPTION_PIC:
6870 case 'k':
6871 flag_want_pic = 1;
6872 break; /* -pic, Position Independent Code */
6873
6874 case OPTION_REGISTER_PREFIX_OPTIONAL:
6875 flag_reg_prefix_optional = 1;
6876 reg_prefix_optional_seen = 1;
6877 break;
6878
6879 /* -V: SVR4 argument to print version ID. */
6880 case 'V':
6881 print_version_id ();
6882 break;
6883
6884 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6885 should be emitted or not. FIXME: Not implemented. */
6886 case 'Q':
6887 break;
6888
6889 case OPTION_BITWISE_OR:
6890 {
6891 char *n, *t;
6892 const char *s;
6893
6894 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6895 t = n;
6896 for (s = m68k_comment_chars; *s != '\0'; s++)
6897 if (*s != '|')
6898 *t++ = *s;
6899 *t = '\0';
6900 m68k_comment_chars = n;
6901 }
6902 break;
6903
6904 case OPTION_BASE_SIZE_DEFAULT_16:
6905 m68k_index_width_default = SIZE_WORD;
6906 break;
6907
6908 case OPTION_BASE_SIZE_DEFAULT_32:
6909 m68k_index_width_default = SIZE_LONG;
6910 break;
6911
6912 case OPTION_DISP_SIZE_DEFAULT_16:
6913 m68k_rel32 = 0;
6914 m68k_rel32_from_cmdline = 1;
6915 break;
6916
6917 case OPTION_DISP_SIZE_DEFAULT_32:
6918 m68k_rel32 = 1;
6919 m68k_rel32_from_cmdline = 1;
6920 break;
6921
6922 default:
6923 return 0;
6924 }
6925
6926 return 1;
6927}
6928
6929void
6930md_show_usage (stream)
6931 FILE *stream;
6932{
6933 fprintf(stream, _("\
6934680X0 options:\n\
6935-l use 1 word for refs to undefined symbols [default 2]\n\
6936-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6937 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6938 | -mcpu32 | -m5200\n\
6939 specify variant of 680X0 architecture [default 68020]\n\
6940-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6941 target has/lacks floating-point coprocessor\n\
6942 [default yes for 68020, 68030, and cpu32]\n"));
6943 fprintf(stream, _("\
6944-m68851 | -mno-68851\n\
6945 target has/lacks memory-management unit coprocessor\n\
6946 [default yes for 68020 and up]\n\
6947-pic, -k generate position independent code\n\
6948-S turn jbsr into jsr\n\
6949--register-prefix-optional\n\
6950 recognize register names without prefix character\n\
6951--bitwise-or do not treat `|' as a comment character\n"));
6952 fprintf (stream, _("\
6953--base-size-default-16 base reg without size is 16 bits\n\
6954--base-size-default-32 base reg without size is 32 bits (default)\n\
6955--disp-size-default-16 displacement with unknown size is 16 bits\n\
6956--disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6957}
6958\f
6959#ifdef TEST2
6960
6961/* TEST2: Test md_assemble() */
6962/* Warning, this routine probably doesn't work anymore */
6963
6964main ()
6965{
6966 struct m68k_it the_ins;
6967 char buf[120];
6968 char *cp;
6969 int n;
6970
6971 m68k_ip_begin ();
6972 for (;;)
6973 {
6974 if (!gets (buf) || !*buf)
6975 break;
6976 if (buf[0] == '|' || buf[1] == '.')
6977 continue;
6978 for (cp = buf; *cp; cp++)
6979 if (*cp == '\t')
6980 *cp = ' ';
6981 if (is_label (buf))
6982 continue;
6983 memset (&the_ins, '\0', sizeof (the_ins));
6984 m68k_ip (&the_ins, buf);
6985 if (the_ins.error)
6986 {
6987 printf (_("Error %s in %s\n"), the_ins.error, buf);
6988 }
6989 else
6990 {
6991 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
6992 for (n = 0; n < the_ins.numo; n++)
6993 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6994 printf (" ");
6995 print_the_insn (&the_ins.opcode[0], stdout);
6996 (void) putchar ('\n');
6997 }
6998 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6999 {
7000 if (the_ins.operands[n].error)
7001 {
7002 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7003 continue;
7004 }
7005 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7006 if (the_ins.operands[n].b_const)
7007 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7008 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7009 if (the_ins.operands[n].b_iadd)
7010 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7011 (void) putchar ('\n');
7012 }
7013 }
7014 m68k_ip_end ();
7015 return 0;
7016}
7017
7018is_label (str)
7019 char *str;
7020{
7021 while (*str == ' ')
7022 str++;
7023 while (*str && *str != ' ')
7024 str++;
7025 if (str[-1] == ':' || str[1] == '=')
7026 return 1;
7027 return 0;
7028}
7029
7030#endif
7031
7032/* Possible states for relaxation:
7033
7034 0 0 branch offset byte (bra, etc)
7035 0 1 word
7036 0 2 long
7037
7038 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7039 1 1 word
7040 1 2 long
7041
7042 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7043 2 1 word-long
7044 2 2 long-word
7045 2 3 long-long
7046
7047 */
7048
7049/* We have no need to default values of symbols. */
7050
7051/* ARGSUSED */
7052symbolS *
7053md_undefined_symbol (name)
36823076 7054 char *name ATTRIBUTE_UNUSED;
252b5132
RH		 7055{
7056 return 0;
7057}
7058
7059/* Round up a section size to the appropriate boundary. */
7060valueT
7061md_section_align (segment, size)
36823076 7062 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7063 valueT size;
7064{
7065#ifdef OBJ_AOUT
7066#ifdef BFD_ASSEMBLER
7067 /* For a.out, force the section size to be aligned. If we don't do
7068 this, BFD will align it for us, but it will not write out the
7069 final bytes of the section. This may be a bug in BFD, but it is
7070 easier to fix it here since that is how the other a.out targets
7071 work. */
7072 int align;
7073
7074 align = bfd_get_section_alignment (stdoutput, segment);
7075 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7076#endif
7077#endif
7078
7079 return size;
7080}
7081
7082/* Exactly what point is a PC-relative offset relative TO?
7083 On the 68k, it is relative to the address of the first extension
7084 word. The difference between the addresses of the offset and the
7085 first extension word is stored in fx_pcrel_adjust. */
7086long
7087md_pcrel_from (fixP)
7088 fixS *fixP;
7089{
7090 int adjust;
7091
7092 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
7093 -1 as 64. */
7094 adjust = fixP->fx_pcrel_adjust;
7095 if (adjust == 64)
7096 adjust = -1;
7097 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7098}
7099
7100#ifndef BFD_ASSEMBLER
7101#ifdef OBJ_COFF
7102
7103/*ARGSUSED*/
7104void
7105tc_coff_symbol_emit_hook (ignore)
7106 symbolS *ignore;
7107{
7108}
7109
7110int
7111tc_coff_sizemachdep (frag)
7112 fragS *frag;
7113{
7114 switch (frag->fr_subtype & 0x3)
7115 {
7116 case BYTE:
7117 return 1;
7118 case SHORT:
7119 return 2;
7120 case LONG:
7121 return 4;
7122 default:
7123 abort ();
7124 return 0;
7125 }
7126}
7127
7128#endif
7129#endif
0d96863f
CM		 7130#ifdef OBJ_ELF
7131void m68k_elf_final_processing()
7132{
7133 /* Set file-specific flags if this is a cpu32 processor */
7134 if (cpu_of_arch (current_architecture) & cpu32)
7135 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7136}
7137#endif
252b5132 7138/* end of tc-m68k.c */
GDB Binutils - Deliverables
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