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These changes clean things up a bit, and improve Solaris cross
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
CommitLineData
a87b3269 1/* tc-m68k.c All the m68020 specific stuff in one convenient, huge,
fecd2382 2 slow to compile, easy to find file.
6d27d3a2 3
a87b3269 4 Copyright (C) 1987, 1991, 1992 Free Software Foundation, Inc.
6d27d3a2 5
a39116f1 6 This file is part of GAS, the GNU Assembler.
6d27d3a2 7
a39116f1
RP		 8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
6d27d3a2 12
a39116f1
RP		 13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
6d27d3a2 17
a39116f1
RP		 18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
fecd2382
RP		 21
22#include <ctype.h>
f8701a3f 23#define NO_RELOC 0
fecd2382 24#include "as.h"
3ad9ec6a 25#include "read.h"
fecd2382
RP		 26
27#include "obstack.h"
28
a39116f1 29/* note that this file includes real declarations and thus can only be included by one source file per executable. */
e0982afe 30#include "opcode/m68k.h"
3ad9ec6a 31
f6e504fe
RP		 32#ifdef TE_SUN
33/* This variable contains the value to write out at the beginning of
34 the a.out file. The 2<<16 means that this is a 68020 file instead
35 of an old-style 68000 file */
36
37long omagic = 2<<16|OMAGIC; /* Magic byte for header file */
38#else
39long omagic = OMAGIC;
40#endif
fecd2382
RP		 41
42/* This array holds the chars that always start a comment. If the
43 pre-processor is disabled, these aren't very useful */
44const char comment_chars[] = "|";
45
46/* This array holds the chars that only start a comment at the beginning of
47 a line. If the line seems to have the form '# 123 filename'
48 .line and .file directives will appear in the pre-processed output */
49/* Note that input_file.c hand checks for '#' at the beginning of the
50 first line of the input file. This is because the compiler outputs
51 #NO_APP at the beginning of its output. */
52/* Also note that comments like this one will always work. */
53const char line_comment_chars[] = "#";
54
587c4264
ILT		 55const char line_separator_chars[] = "";
56
fecd2382
RP		 57/* Chars that can be used to separate mant from exp in floating point nums */
58const char EXP_CHARS[] = "eE";
59
60/* Chars that mean this number is a floating point constant */
61/* As in 0f12.456 */
62/* or 0d1.2345e12 */
63
64const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
65
66/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
67 changed in read.c . Ideally it shouldn't have to know about it at all,
68 but nothing is ideal around here.
a39116f1 69 */
fecd2382
RP		 70
71int md_reloc_size = 8; /* Size of relocation record */
72
73/* Its an arbitrary name: This means I don't approve of it */
74/* See flames below */
75static struct obstack robyn;
76
77#define TAB(x,y) (((x)<<2)+(y))
78#define TABTYPE(xy) ((xy) >> 2)
79#define BYTE 0
80#define SHORT 1
81#define LONG 2
82#define SZ_UNDEF 3
3ad9ec6a
ILT		 83#undef BRANCH
84#define ABRANCH 1
fecd2382
RP		 85#define FBRANCH 2
86#define PCREL 3
87#define BCC68000 4
88#define DBCC 5
89#define PCLEA 6
90
f6e504fe 91/* Operands we can parse: (And associated modes)
6d27d3a2 92
a39116f1
RP		 93 numb: 8 bit num
94 numw: 16 bit num
95 numl: 32 bit num
96 dreg: data reg 0-7
97 reg: address or data register
98 areg: address register
99 apc: address register, PC, ZPC or empty string
100 num: 16 or 32 bit num
101 num2: like num
102 sz: w or l if omitted, l assumed
103 scale: 1 2 4 or 8 if omitted, 1 assumed
6d27d3a2 104
a39116f1
RP		 105 7.4 IMMED #num --> NUM
106 0.? DREG dreg --> dreg
107 1.? AREG areg --> areg
108 2.? AINDR areg@ --> *(areg)
109 3.? AINC areg@+ --> *(areg++)
110 4.? ADEC areg@- --> *(--areg)
111 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
112 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
113 6.? AINDX apc@(reg:sz:scale) --> same, with num=0
114 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
115 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
116 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
117 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
118 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
119 7.0 ABSL num:sz --> *(num)
120 num --> *(num) (sz L assumed)
121 *** MSCR otherreg --> Magic
122 With -l option
123 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
c50140c8 124 ?.? DINDR dreg@ --> (dreg) -- cas2 only
6d27d3a2 125
a39116f1
RP		 126 examples:
127 #foo #0x35 #12
128 d2
129 a4
130 a3@
131 a5@+
132 a6@-
133 a2@(12) pc@(14)
134 a1@(5,d2:w:1) @(45,d6:l:4)
135 pc@(a2) @(d4)
136 etc . . .
6d27d3a2
KR		 137
138
a39116f1
RP		 139 #name@(numw) -->turn into PC rel mode
140 apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
6d27d3a2 141
a39116f1 142 */
f6e504fe
RP		 143
144enum operand_type {
f8701a3f
SC		 145 IMMED = 1,
146 DREG,
147 AREG,
148 AINDR,
149 ADEC,
150 AINC,
151 AOFF,
152 AINDX,
153 APODX,
154 AMIND,
155 APRDX,
156 ABSL,
157 MSCR,
158 REGLST,
c50140c8 159 DINDR
f6e504fe
RP		 160};
161
162
fecd2382 163struct m68k_exp {
f8701a3f
SC		 164 char *e_beg;
165 char *e_end;
166 expressionS e_exp;
167 short e_siz; /* 0== default 1==short/byte 2==word 3==long */
fecd2382
RP		 168};
169
7c15cbe8
RP		 170/* DATA and ADDR have to be contiguous, so that reg-DATA gives 0-7==data reg,
171 8-15==addr reg for operands that take both types */
172
173enum _register {
f8701a3f
SC		 174 DATA = 1, /* 1- 8 == data registers 0-7 */
175 DATA0 = DATA,
176 DATA1,
177 DATA2,
178 DATA3,
179 DATA4,
180 DATA5,
181 DATA6,
182 DATA7,
6d27d3a2 183
f8701a3f
SC		 184 ADDR,
185 ADDR0 = ADDR,
186 ADDR1,
187 ADDR2,
188 ADDR3,
189 ADDR4,
190 ADDR5,
191 ADDR6,
192 ADDR7,
6d27d3a2 193
f8701a3f
SC		 194 /* Note that COPNUM==processor #1 -- COPNUM+7==#8, which stores as 000 */
195 /* I think. . . */
6d27d3a2 196
f8701a3f 197 SP = ADDR7,
6d27d3a2 198
f8701a3f
SC		 199 FPREG, /* Eight FP registers */
200 FP0 = FPREG,
201 FP1,
202 FP2,
203 FP3,
204 FP4,
205 FP5,
206 FP6,
207 FP7,
208 COPNUM = (FPREG+8), /* Co-processor #1-#8 */
209 COP0 = COPNUM,
210 COP1,
211 COP2,
212 COP3,
213 COP4,
214 COP5,
215 COP6,
216 COP7,
217 PC, /* Program counter */
218 ZPC, /* Hack for Program space, but 0 addressing */
219 SR, /* Status Reg */
220 CCR, /* Condition code Reg */
6d27d3a2 221
f8701a3f
SC		 222 /* These have to be in order for the movec instruction to work. */
223 USP, /* User Stack Pointer */
224 ISP, /* Interrupt stack pointer */
225 SFC,
226 DFC,
227 CACR,
228 VBR,
229 CAAR,
230 MSP,
231 ITT0,
232 ITT1,
233 DTT0,
234 DTT1,
235 MMUSR,
236 TC,
237 SRP,
238 URP,
239 /* end of movec ordering constraints */
6d27d3a2 240
f8701a3f
SC		 241 FPI,
242 FPS,
243 FPC,
6d27d3a2 244
4134a793 245 DRP, /* 68851 or 68030 MMU regs */
f8701a3f
SC		 246 CRP,
247 CAL,
248 VAL,
249 SCC,
250 AC,
251 BAD,
252 BAD0 = BAD,
253 BAD1,
254 BAD2,
255 BAD3,
256 BAD4,
257 BAD5,
258 BAD6,
259 BAD7,
260 BAC,
261 BAC0 = BAC,
262 BAC1,
263 BAC2,
264 BAC3,
265 BAC4,
266 BAC5,
267 BAC6,
268 BAC7,
4134a793
KR		 269 PSR, /* aka MMUSR on 68030 (but not MMUSR on 68040)
270 and ACUSR on 68ec030 */
f8701a3f 271 PCSR,
6d27d3a2 272
f8701a3f
SC		 273 IC, /* instruction cache token */
274 DC, /* data cache token */
275 NC, /* no cache token */
276 BC, /* both caches token */
6d27d3a2 277
4134a793
KR		 278 TT0, /* 68030 access control unit regs */
279 TT1,
7c15cbe8
RP		 280};
281
fecd2382
RP		 282/* Internal form of an operand. */
283struct m68k_op {
f8701a3f
SC		 284 char *error; /* Couldn't parse it */
285 enum operand_type mode; /* What mode this instruction is in. */
286 enum _register reg; /* Base register */
287 struct m68k_exp *con1;
288 int ireg; /* Index register */
289 int isiz; /* 0==unspec 1==byte(?) 2==short 3==long */
290 int imul; /* Multipy ireg by this (1,2,4,or 8) */
291 struct m68k_exp *con2;
fecd2382
RP		 292};
293
294/* internal form of a 68020 instruction */
7c15cbe8 295struct m68k_it {
f8701a3f
SC		 296 char *error;
297 char *args; /* list of opcode info */
298 int numargs;
6d27d3a2 299
f8701a3f
SC		 300 int numo; /* Number of shorts in opcode */
301 short opcode[11];
6d27d3a2 302
f8701a3f 303 struct m68k_op operands[6];
6d27d3a2 304
f8701a3f
SC		 305 int nexp; /* number of exprs in use */
306 struct m68k_exp exprs[4];
6d27d3a2 307
f8701a3f
SC		 308 int nfrag; /* Number of frags we have to produce */
309 struct {
310 int fragoff; /* Where in the current opcode[] the frag ends */
311 symbolS *fadd;
312 long foff;
313 int fragty;
314 } fragb[4];
6d27d3a2 315
f8701a3f
SC		 316 int nrel; /* Num of reloc strucs in use */
317 struct {
318 int n;
319 symbolS *add,
320 *sub;
321 long off;
322 char wid;
323 char pcrel;
324 } reloc[5]; /* Five is enough??? */
fecd2382
RP		 325};
326
865a2edf
MT		 327#define cpu_of_arch(x) ((x) & m68000up)
328#define float_of_arch(x) ((x) & mfloat)
329#define mmu_of_arch(x) ((x) & mmmu)
330
7c15cbe8 331static struct m68k_it the_ins; /* the instruction being assembled */
fecd2382 332
7c15cbe8 333/* Macros for adding things to the m68k_it struct */
fecd2382
RP		 334
335#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
336
337/* Like addword, but goes BEFORE general operands */
338#define insop(w) {int z;\
a39116f1
RP		 339 for(z=the_ins.numo;z>opcode->m_codenum;--z)\
340 the_ins.opcode[z]=the_ins.opcode[z-1];\
341 for(z=0;z<the_ins.nrel;z++)\
342 the_ins.reloc[z].n+=2;\
343 the_ins.opcode[opcode->m_codenum]=w;\
344 the_ins.numo++;\
f8701a3f 345 }
fecd2382
RP		 346
347
348#define add_exp(beg,end) (\
a39116f1
RP		 349 the_ins.exprs[the_ins.nexp].e_beg=beg,\
350 the_ins.exprs[the_ins.nexp].e_end=end,\
351 &the_ins.exprs[the_ins.nexp++]\
352 )
fecd2382
RP		 353
354
355/* The numo+1 kludge is so we can hit the low order byte of the prev word. Blecch*/
356#define add_fix(width,exp,pc_rel) {\
a39116f1
RP		 357 the_ins.reloc[the_ins.nrel].n= ((width)=='B') ? (the_ins.numo*2-1) : \
358 (((width)=='b') ? ((the_ins.numo-1)*2) : (the_ins.numo*2));\
359 the_ins.reloc[the_ins.nrel].add=adds((exp));\
360 the_ins.reloc[the_ins.nrel].sub=subs((exp));\
361 the_ins.reloc[the_ins.nrel].off=offs((exp));\
362 the_ins.reloc[the_ins.nrel].wid=width;\
363 the_ins.reloc[the_ins.nrel++].pcrel=pc_rel;\
f8701a3f 364 }
fecd2382
RP		 365
366#define add_frag(add,off,type) {\
a39116f1
RP		 367 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;\
368 the_ins.fragb[the_ins.nfrag].fadd=add;\
369 the_ins.fragb[the_ins.nfrag].foff=off;\
370 the_ins.fragb[the_ins.nfrag++].fragty=type;\
f8701a3f 371 }
fecd2382
RP		 372
373#define isvar(exp) ((exp) && (adds(exp) || subs(exp)))
374
375#define seg(exp) ((exp)->e_exp.X_seg)
376#define adds(exp) ((exp)->e_exp.X_add_symbol)
377#define subs(exp) ((exp)->e_exp.X_subtract_symbol)
378#define offs(exp) ((exp)->e_exp.X_add_number)
379
380
7c15cbe8 381struct m68k_incant {
f8701a3f
SC		 382 char *m_operands;
383 unsigned long m_opcode;
384 short m_opnum;
385 short m_codenum;
df3768fb 386 int m_arch;
f8701a3f 387 struct m68k_incant *m_next;
fecd2382
RP		 388};
389
3ad9ec6a
ILT		 390
391
fecd2382
RP		 392#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
393#define gettwo(x) (((x)->m_opcode)&0xffff)
394
395
a87b3269 396#if __STDC__ == 1
fecd2382
RP		 397
398static char *crack_operand(char *str, struct m68k_op *opP);
399static int get_num(struct m68k_exp *exp, int ok);
400static int get_regs(int i, char *str, struct m68k_op *opP);
401static int reverse_16_bits(int in);
402static int reverse_8_bits(int in);
403static int try_index(char **s, struct m68k_op *opP);
404static void install_gen_operand(int mode, int val);
405static void install_operand(int mode, int val);
3ad9ec6a 406static void s_bss(void);
fecd2382
RP		 407static void s_data1(void);
408static void s_data2(void);
409static void s_even(void);
410static void s_proc(void);
411
a87b3269 412#else /* not __STDC__ */
fecd2382
RP		 413
414static char *crack_operand();
415static int get_num();
416static int get_regs();
417static int reverse_16_bits();
418static int reverse_8_bits();
419static int try_index();
420static void install_gen_operand();
421static void install_operand();
3ad9ec6a 422static void s_bss();
9e43698e 423void s_align_bytes();
fecd2382
RP		 424static void s_data1();
425static void s_data2();
426static void s_even();
427static void s_proc();
428
a87b3269 429#endif /* not __STDC__ */
fecd2382 430
df3768fb 431static int current_architecture = 0;
7c15cbe8 432
fecd2382
RP		 433/* BCC68000 is for patching in an extra jmp instruction for long offsets
434 on the 68000. The 68000 doesn't support long branches with branchs */
435
436/* This table desribes how you change sizes for the various types of variable
437 size expressions. This version only supports two kinds. */
438
439/* Note that calls to frag_var need to specify the maximum expansion needed */
440/* This is currently 10 bytes for DBCC */
441
442/* The fields are:
a39116f1
RP		 443 How far Forward this mode will reach:
444 How far Backward this mode will reach:
445 How many bytes this mode will add to the size of the frag
446 Which mode to go to if the offset won't fit in this one
447 */
fecd2382 448const relax_typeS
a39116f1 449 md_relax_table[] = {
f8701a3f
SC		 450 { 1, 1, 0, 0 }, /* First entries aren't used */
451 { 1, 1, 0, 0 }, /* For no good reason except */
452 { 1, 1, 0, 0 }, /* that the VAX doesn't either */
453 { 1, 1, 0, 0 },
6d27d3a2 454
3ad9ec6a
ILT		 455 { (127), (-128), 0, TAB(ABRANCH,SHORT)},
456 { (32767), (-32768), 2, TAB(ABRANCH,LONG) },
f8701a3f
SC		 457 { 0, 0, 4, 0 },
458 { 1, 1, 0, 0 },
6d27d3a2 459
f8701a3f
SC		 460 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */
461 { (32767), (-32768), 2, TAB(FBRANCH,LONG)},
462 { 0, 0, 4, 0 },
463 { 1, 1, 0, 0 },
6d27d3a2 464
f8701a3f
SC		 465 { 1, 1, 0, 0 }, /* PCREL doesn't come BYTE */
466 { (32767), (-32768), 2, TAB(PCREL,LONG)},
467 { 0, 0, 4, 0 },
468 { 1, 1, 0, 0 },
6d27d3a2 469
f8701a3f
SC		 470 { (127), (-128), 0, TAB(BCC68000,SHORT)},
471 { (32767), (-32768), 2, TAB(BCC68000,LONG) },
472 { 0, 0, 6, 0 }, /* jmp long space */
473 { 1, 1, 0, 0 },
6d27d3a2 474
f8701a3f
SC		 475 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
476 { (32767), (-32768), 2, TAB(DBCC,LONG) },
477 { 0, 0, 10, 0 }, /* bra/jmp long space */
478 { 1, 1, 0, 0 },
6d27d3a2 479
f8701a3f
SC		 480 { 1, 1, 0, 0 }, /* PCLEA doesn't come BYTE */
481 { 32767, -32768, 2, TAB(PCLEA,LONG) },
482 { 0, 0, 6, 0 },
483 { 1, 1, 0, 0 },
6d27d3a2 484
f8701a3f 485 };
fecd2382
RP		 486
487/* These are the machine dependent pseudo-ops. These are included so
488 the assembler can work on the output from the SUN C compiler, which
489 generates these.
a39116f1 490 */
fecd2382
RP		 491
492/* This table describes all the machine specific pseudo-ops the assembler
493 has to support. The fields are:
a39116f1
RP		 494 pseudo-op name without dot
495 function to call to execute this pseudo-op
496 Integer arg to pass to the function
497 */
fecd2382 498const pseudo_typeS md_pseudo_table[] = {
f8701a3f
SC		 499 { "data1", s_data1, 0 },
500 { "data2", s_data2, 0 },
501 { "bss", s_bss, 0 },
502 { "even", s_even, 0 },
503 { "skip", s_space, 0 },
504 { "proc", s_proc, 0 },
bec66218 505#ifdef TE_SUN3
9e43698e 506 { "align", s_align_bytes, 0 },
bec66218 507#endif
f8701a3f 508 { 0, 0, 0 }
fecd2382
RP		 509};
510
511
3ad9ec6a
ILT		 512/* The mote pseudo ops are put into the opcode table, since they
513 don't start with a . they look like opcodes to gas.
514 */
515extern void obj_coff_section();
516
517const pseudo_typeS mote_pseudo_table[] =
518{
519
520 { "dc.l", cons,4},
521 { "dc", cons,2},
522 { "dc.w", cons,2},
523 { "dc.b", cons,1},
524
525 { "ds.l", s_space,4},
526 { "ds", s_space,2},
527 { "ds.w", s_space,2},
528 { "ds.b", s_space,1},
529
530 { "xdef", s_globl, 0},
531 { "align", s_align_ptwo, 0},
532#ifdef M68KCOFF
533 { "sect", obj_coff_section,0},
534 { "section", obj_coff_section,0},
535#endif
536 0,
537};
538
fecd2382
RP		 539/* #define isbyte(x) ((x)>=-128 && (x)<=127) */
540/* #define isword(x) ((x)>=-32768 && (x)<=32767) */
541
542#define issbyte(x) ((x)>=-128 && (x)<=127)
543#define isubyte(x) ((x)>=0 && (x)<=255)
544#define issword(x) ((x)>=-32768 && (x)<=32767)
545#define isuword(x) ((x)>=0 && (x)<=65535)
f8701a3f 546
fecd2382
RP		 547#define isbyte(x) ((x)>=-128 && (x)<=255)
548#define isword(x) ((x)>=-32768 && (x)<=65535)
549#define islong(x) (1)
f8701a3f
SC		 550
551extern char *input_line_pointer;
fecd2382 552
7c15cbe8 553enum {
f8701a3f
SC		 554 FAIL = 0,
555 OK = 1,
7c15cbe8 556};
fecd2382
RP		 557
558/* JF these tables here are for speed at the expense of size */
559/* You can replace them with the #if 0 versions if you really
560 need space and don't mind it running a bit slower */
561
562static char mklower_table[256];
563#define mklower(c) (mklower_table[(unsigned char)(c)])
f8701a3f 564static char notend_table[256];
fecd2382
RP		 565static char alt_notend_table[256];
566#define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
a39116f1 567 alt_notend_table[(unsigned char)(s[1])])))
fecd2382
RP		 568
569#if 0
570#define mklower(c) (isupper(c) ? tolower(c) : c)
571#endif
f8701a3f
SC		 572
573
574/* JF modified this to handle cases where the first part of a symbol name
575 looks like a register */
576
577/*
578 * m68k_reg_parse() := if it looks like a register, return it's token &
579 * advance the pointer.
580 */
581
587c4264
ILT		 582enum _register
583m68k_reg_parse(ccp)
584 register char **ccp;
fecd2382 585{
f8701a3f
SC		 586 char *start = *ccp;
587
587c4264
ILT		 588#ifdef REGISTER_PREFIX
589 if (*start == REGISTER_PREFIX)
590 ++start;
591#endif
592
6d27d3a2 593 if (isalpha(*start) && is_name_beginner(*start))
f8701a3f
SC		 594 {
595 char c;
596 char *p = start;
597 symbolS *symbolP;
6d27d3a2 598
3ad9ec6a 599 c = *p++;
587c4264
ILT		 600 while (isalpha(c) || isdigit(c) || c == '_')
601 {
602 c = *p++;
603 }
3ad9ec6a 604
f8701a3f
SC		 605 * -- p = 0;
606 symbolP = symbol_find(start);
607 *p = c;
608
6d27d3a2 609 if (symbolP && S_GET_SEGMENT(symbolP) == SEG_REGISTER)
a39116f1 610 {
f8701a3f
SC		 611 *ccp = p;
612 return S_GET_VALUE(symbolP);
a39116f1 613 }
f8701a3f
SC		 614 }
615 return FAIL;
616
617
fecd2382
RP		 618}
619
620#define SKIP_WHITE() { str++; if(*str==' ') str++;}
3ad9ec6a
ILT		 621#define SKIP_W() { ss++; if(*ss==' ') ss++;}
622
623/* Parse an index specification using Motorola syntax. */
624
625static int
626try_moto_index(s,opP)
627char **s;
628struct m68k_op *opP;
629{
630 register int i;
631 char *ss;
632
633 ss= *s;
634 /* SKIP_W(); */
635 if(*ss==' ') ss++;
636 i=m68k_reg_parse(&ss);
637 if(!(i>=DATA+0 && i<=ADDR+7)) { /* if i is not DATA or ADDR reg */
638 opP->error="Invalid index register";
639 *s=ss;
640 return FAIL;
641 }
642 opP->ireg=i;
643 /* SKIP_W(); */
644 if(*ss==')') {
645 opP->isiz=0;
646 opP->imul=1;
647 SKIP_W();
648 *s=ss;
649 return OK;
650 }
651 if(*ss!='.') {
652 opP->error="Missing . in index register";
653 *s=ss;
654 return FAIL;
655 }
656 SKIP_W();
657 if(mklower(*ss)=='w') opP->isiz=2;
658 else if(mklower(*ss)=='l') opP->isiz=3;
659 else {
660 opP->error="Size spec not .W or .L";
661 *s=ss;
662 return FAIL;
663 }
664 SKIP_W();
665 if(*ss=='.' || *ss=='*') {
666 SKIP_W();
667 switch(*ss) {
668 case '1':
669 case '2':
670 case '4':
671 case '8':
672 opP->imul= *ss-'0';
673 break;
674 default:
675 opP->error="index multiplier not 1, 2, 4 or 8";
676 *s=ss;
677 return FAIL;
678 }
679 SKIP_W();
680 } else opP->imul=1;
681 if(*ss!=')') {
682 opP->error="Missing )";
683 *s=ss;
684 return FAIL;
685 }
686 SKIP_W();
687 *s=ss;
688 return OK;
689}
fecd2382 690
7c15cbe8 691/*
3ad9ec6a
ILT		 692 *
693 * try_index := data_or_address_register + ')' + SKIP_W
694 * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W
695 *
696 * multiplier := <empty>
697 * | ':' + multiplier_number
7c15cbe8 698 * ;
6d27d3a2 699 *
3ad9ec6a 700 * multiplier_number := '1' | '2' | '4' | '8' ;
7c15cbe8 701 *
3ad9ec6a
ILT		 702 * size_spec := 'l' | 'L' | 'w' | 'W' ;
703 *
704 * SKIP_W := <empty> | ' ' ;
7c15cbe8
RP		 705 *
706 */
707
3ad9ec6a
ILT		 708static int try_index(s,opP)
709char **s;
710struct m68k_op *opP;
711{
712 register int i;
713 char *ss;
714
715 ss= *s;
716 /* SKIP_W(); */
717 i=m68k_reg_parse(&ss);
718 if(!(i>=DATA+0 && i<=ADDR+7)) { /* if i is not DATA or ADDR reg */
719 *s=ss;
720 return FAIL;
721 }
722 opP->ireg=i;
723 /* SKIP_W(); */
724 if(*ss==')') {
725 opP->isiz=0;
726 opP->imul=1;
727 SKIP_W();
728 *s=ss;
729 return OK;
730 }
731 if(*ss!=':') {
732 opP->error="Missing : in index register";
733 *s=ss;
734 return FAIL;
735 }
736 SKIP_W();
737 switch(*ss) {
738 case 'w':
739 case 'W':
740 opP->isiz=2;
741 break;
742 case 'l':
743 case 'L':
744 opP->isiz=3;
745 break;
746 default:
747 opP->error="Index register size spec not :w or :l";
748 *s=ss;
749 return FAIL;
750 }
751 SKIP_W();
752 if(*ss==':') {
753 SKIP_W();
754 switch(*ss) {
755 case '1':
756 case '2':
757 case '4':
758 case '8':
759 if (cpu_of_arch(current_architecture) < m68020) {
760 opP->error="no index scaling in pre-68020's";
761 *s=ss;
762 return FAIL;
763 }
764 opP->imul= *ss-'0';
765 break;
766 default:
767 opP->error="index multiplier not 1, 2, 4 or 8";
768 *s=ss;
769 return FAIL;
770 }
771 SKIP_W();
772 } else opP->imul=1;
773 if(*ss!=')') {
774 opP->error="Missing )";
775 *s=ss;
776 return FAIL;
777 }
778 SKIP_W();
779 *s=ss;
780 return OK;
781} /* try_index() */
782
783/* Ian Taylor expanded this function to accept both MIT and Motorola
784 syntax. I removed the old comment, since it was wrong. The syntax
785 this accepted even before my changes was complex and undocumented.
786 I mainly added a large case when the operand string does not
787 contain an '@', since the Motorola syntax does not use the '@'
788 character. */
789
fecd2382 790int
a39116f1 791 m68k_ip_op(str,opP)
fecd2382
RP		 792char *str;
793register struct m68k_op *opP;
794{
f8701a3f
SC		 795 char *strend;
796 long i;
797 char *parse_index();
a933d598 798 int needp;
3ad9ec6a 799
f8701a3f
SC		 800 if (*str==' ') {
801 str++;
802 } /* Find the beginning of the string */
6d27d3a2 803
f8701a3f
SC		 804 if(!*str) {
805 opP->error="Missing operand";
fecd2382 806 return FAIL;
f8701a3f 807 } /* Out of gas */
6d27d3a2 808
3ad9ec6a
ILT		 809 for(strend = str; *strend; strend++)
810 ;
f8701a3f 811 --strend;
6d27d3a2 812
f8701a3f
SC		 813 if(*str=='#') {
814 str++;
815 opP->con1=add_exp(str,strend);
816 opP->mode=IMMED;
817 return OK;
818 } /* Guess what: A constant. Shar and enjoy */
6d27d3a2 819
f8701a3f 820 i = m68k_reg_parse(&str);
6d27d3a2 821
3ad9ec6a
ILT		 822 if (i!=FAIL) {
823 if(*str=='/' || *str=='-') {
824 /* "Rm-Rn/Ro-Rp" Register list for MOVEM instruction */
825 opP->mode=REGLST;
826 return get_regs(i,str,opP);
827 }
828 if(*str=='\0') {
829 opP->reg=i;
830 /* "Rn" Register Direct mode */
831 if(i>=DATA+0 && i<=DATA+7)
832 opP->mode=DREG;
833 else if(i>=ADDR+0 && i<=ADDR+7)
834 opP->mode=AREG;
835 else
836 opP->mode=MSCR;
837 return OK;
838 }
839 }
6d27d3a2 840
3ad9ec6a 841 if (*str!='@') {
f8701a3f 842 char *stmp;
6d27d3a2 843
3ad9ec6a 844 if ((stmp=strchr(str,'@')) != 0) {
f8701a3f
SC		 845 opP->con1=add_exp(str,stmp-1);
846 if(stmp==strend) {
847 opP->mode=AINDX;
848 return(OK);
849 }
6d27d3a2 850
f8701a3f
SC		 851 if ((current_architecture & m68020up) == 0) {
852 return(FAIL);
853 } /* if target is not a '20 or better */
6d27d3a2 854
f8701a3f
SC		 855 stmp++;
856 if(*stmp++!='(' || *strend--!=')') {
857 opP->error="Malformed operand";
858 return(FAIL);
859 }
860 i=try_index(&stmp,opP);
861 opP->con2=add_exp(stmp,strend);
6d27d3a2 862
f8701a3f
SC		 863 if (i == FAIL) {
864 opP->mode=AMIND;
865 } else {
866 opP->mode=APODX;
867 }
868 return(OK);
869 } /* if there's an '@' */
6d27d3a2 870
3ad9ec6a
ILT		 871#ifndef MIT_SYNTAX_ONLY
872 /* The operand has no '@'. Try to parse it using
873 Motorola syntax. */
874 /* Logic of the parsing switch(*str):
875 case opP->mode =
876 ---- -----------
877 #anything IMMED 1
878 REG AREG or DREG or MSCR 3 or 2 or 13
879 REG- or REG/ REGLST 14
880 (REG) AINDR 4
881 (REG)+ AINC 6
882 (REG,INDX) AINDX 8
883 (EXPR,REG) AOFF 7
884 (EXPR,REG,INDX) AINDX 8
885 -(REG) ADEC 5
886 EXP2(REG) AOFF 7
887 EXP2(REG,INDX) AINDX 8
888 EXP2 ABSL 12
889
890 REG means truth(m68k_reg_parse(&str))
891 INDX means truth(try_moto_index(&str,opP))
892 EXPR means not REG
893 EXP2 means not REG and not '(' and not '-('
894 */
895
896 if(*str=='(') {
897 str++;
898 i=m68k_reg_parse(&str);
899 if((i<ADDR+0 || i>ADDR+7)
900 && (i<DATA+0 || i>DATA+7
901 || *str != ')' || str[1] != '0')
902 && i!=PC && i!=ZPC && i!=FAIL) {
903 /* Can't indirect off non address regs */
904 opP->error="Invalid indirect register";
905 return FAIL;
906 }
907 if(i!=FAIL) {
908 opP->reg=i;
909 if(*str==')') {
910 str++;
911 if(*str=='\0') {
912 /* "(An)" Address Register Indirect mode
913 or "(Dn)" for cas2. */
914 if (i>=DATA+0 && i<=DATA+7)
915 opP->mode=DINDR;
916 else
917 opP->mode=AINDR;
918 return OK;
919 }
920 if(*str=='+') {
921 if(str[1]=='\0') {
922 /* "(An)+" Register Indirect w Postincrement */
923 opP->mode=AINC;
924 return OK;
925 }
926 }
927 opP->error="Junk after indirect";
928 return FAIL;
929 }
930 if(*str==',') {
931 str++;
932 i=try_moto_index(&str,opP);
933 if(i==FAIL) return FAIL;
934 /* "(An,Rn)" Register Indirect with Index mode*/
935 opP->mode=AINDX;
936 return OK;
937 }
938 else {
939 opP->error="Bad indirect syntax";
940 return FAIL;
941 }
942 }
943 else {
944 /* "(EXPR,..." , a displacement */
945 char *stmp;
946 char *index();
947
948 if(stmp=index(str,',')) {
949 opP->con1=add_exp(str,stmp-1);
950 str=stmp;
951 SKIP_WHITE();
952 i=m68k_reg_parse(&str);
953 if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC) {
954 /* Can't indirect off non address regs */
955 opP->error="Invalid indirect register";
956 return FAIL;
957 }
958 if(i!=FAIL) {
959 opP->reg=i;
960 if(*str==')') {
961 /* "(d,An)" Register Indirect w Displacement */
962 opP->mode=AOFF;
963 return OK;
964 }
965 if(*str==',') {
966 str++;
967 i=try_moto_index(&str,opP);
968 if(i==FAIL) return FAIL;
969 /* "(d,An,Rn)" Register Indirect with Index */
970 opP->mode=AINDX;
971 return OK;
972 }
973 else {
974 opP->error="Bad indirect syntax";
975 return FAIL;
976 }
977 }
978 else {
979 opP->error="Invalid register";
980 return FAIL;
981 }
982 }
983 else {
984 opP->mode = ABSL;
985 opP->con1 = add_exp(str-1,strend);
986 return OK;
987 }
988 }
989 }
6d27d3a2 990
3ad9ec6a
ILT		 991 if(*str=='-') {
992 if(str[1]=='(') {
993 str = str+2;
994 i=m68k_reg_parse(&str);
995 if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL) {
996 /* Can't indirect off non address regs */
997 opP->error="Invalid indirect register";
998 return FAIL;
999 }
1000 if(i!=FAIL) {
1001 opP->reg=i;
1002 if(*str==')') {
1003 str++;
1004 if(*str=='\0') {
1005 /* "-(An)" Register Indirect with Predecrement */
1006 opP->mode=ADEC;
1007 return OK;
1008 }
1009 opP->error="Junk after indirect";
1010 return FAIL;
1011 }
1012 opP->error="Bad indirect syntax";
1013 return FAIL;
1014 }
1015 opP->mode = ABSL;
1016 opP->con1 = add_exp(str-2,strend);
1017 return OK;
1018 }
1019 /* if '-' but not "-(', do nothing */
1020 }
1021
1022 /* whether *str=='-' or not */
1023 {
1024 /* "EXP2" or "EXP2(REG..." */
1025 char *stmp;
1026 char *index();
1027 if(stmp=index(str,'(')) {
1028 char *ostr=str;
1029
1030 opP->con1=add_exp(str,stmp-1);
1031 str=stmp+1;
1032 i=m68k_reg_parse(&str);
1033 if((i<ADDR+0 || i>ADDR+7) && i!=PC
1034 && i!=ZPC && i!=FAIL) {
1035 /* Can't indirect off non address regs */
1036 opP->error="Invalid indirect register";
1037 return FAIL;
1038 }
1039 if(i!=FAIL) {
1040 opP->reg=i;
1041 if(*str==')') {
1042 /* "d(An)" Register Indirect w Displacement */
1043 opP->mode=AOFF;
1044 return OK;
1045 }
1046 if(*str==',') {
1047 str++;
1048 i=try_moto_index(&str,opP);
1049 if(i==FAIL) return FAIL;
1050 /* "d(An,Rn)" Register Indirect with Index */
1051 opP->mode=AINDX;
1052 return OK;
1053 }
1054 else {
1055 opP->error="Bad indirect syntax";
1056 return FAIL;
1057 }
1058 }
1059 else {
1060 opP->mode = ABSL;
1061 opP->con1 = add_exp(ostr,strend);
1062 return OK;
1063 }
1064 }
1065 else {
1066 /* "EXP2" Absolute */
1067 opP->mode=ABSL;
1068 opP->isiz=0;
1069 if(strend[-1]=='.' || strend[-1]==':') {
1070 /* mode ==foo.[wl] */
1071 switch(*strend) {
1072 case 'w':
1073 case 'W':
1074 opP->isiz=2;
1075 strend-=2;
1076 break;
1077 case 'l':
1078 case 'L':
1079 opP->isiz=3;
1080 strend-=2;
1081 break;
1082 }
1083 }
1084 opP->con1=add_exp(str,strend);
1085 return OK;
1086 }
1087 }
1088 /*NOTREACHED*/
1089#else /* defined (MIT_SYNTAX_ONLY) */
1090 opP->mode=ABSL;
1091 opP->con1=add_exp(str,strend);
f8701a3f 1092 return OK;
3ad9ec6a
ILT		 1093#endif /* defined (MIT_SYNTAX_ONLY) */
1094 }
1095
1096 opP->reg=i;
6d27d3a2 1097
c50140c8
ILT		 1098 /* Can't indirect off non address regs, but Dx@ is OK for cas2 */
1099 if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL
1100 && (str[1] != '\0' || i<DATA+0 || i>DATA+7)) {
f8701a3f 1101 opP->error="Invalid indirect register";
a39116f1 1102 return FAIL;
fecd2382 1103 }
f8701a3f 1104 know(*str == '@');
6d27d3a2 1105
f8701a3f
SC		 1106 str++;
1107 switch(*str) {
1108 case '\0':
3ad9ec6a 1109 if (i<DATA+0 || i>DATA+7)
c50140c8
ILT		 1110 opP->mode=AINDR;
1111 else
1112 opP->mode=DINDR;
f8701a3f
SC		 1113 return OK;
1114 case '-':
1115 opP->mode=ADEC;
1116 return OK;
1117 case '+':
1118 opP->mode=AINC;
1119 return OK;
1120 case '(':
1121 str++;
1122 break;
1123 default:
1124 opP->error="Junk after indirect";
1125 return FAIL;
fecd2382 1126 }
f8701a3f
SC		 1127 /* Some kind of indexing involved. Lets find out how bad it is */
1128 i=try_index(&str,opP);
1129 /* Didn't start with an index reg, maybe its offset or offset,reg */
1130 if(i==FAIL) {
1131 char *beg_str;
6d27d3a2 1132
f8701a3f
SC		 1133 beg_str=str;
1134 for(i=1;i;) {
1135 switch(*str++) {
1136 case '\0':
1137 opP->error="Missing )";
1138 return FAIL;
1139 case ',': i=0; break;
1140 case '(': i++; break;
1141 case ')': --i; break;
1142 }
1143 }
1144 /* if(str[-3]==':') {
1145 int siz;
6d27d3a2 1146
f8701a3f
SC		 1147 switch(str[-2]) {
1148 case 'b':
1149 case 'B':
1150 siz=1;
1151 break;
1152 case 'w':
1153 case 'W':
1154 siz=2;
1155 break;
1156 case 'l':
1157 case 'L':
1158 siz=3;
1159 break;
1160 default:
1161 opP->error="Specified size isn't :w or :l";
1162 return FAIL;
1163 }
1164 opP->con1=add_exp(beg_str,str-4);
1165 opP->con1->e_siz=siz;
1166 } else */
1167 opP->con1=add_exp(beg_str,str-2);
1168 /* Should be offset,reg */
1169 if(str[-1]==',') {
1170 i=try_index(&str,opP);
1171 if(i==FAIL) {
1172 opP->error="Malformed index reg";
1173 return FAIL;
1174 }
1175 }
1176 }
1177 /* We've now got offset) offset,reg) or reg) */
6d27d3a2 1178
f8701a3f
SC		 1179 if (*str == '\0') {
1180 /* Th-the-thats all folks */
1181 if (opP->reg == FAIL) opP->mode = AINDX; /* Other form of indirect */
1182 else if(opP->ireg == FAIL) opP->mode = AOFF;
1183 else opP->mode = AINDX;
1184 return(OK);
1185 }
1186 /* Next thing had better be another @ */
a933d598
SC		 1187 if (*str == '@') {
1188 if (str[1] == '(') {
1189 needp = 1;
1190 str+=2;
1191 }
1192 else {
1193 needp = 0;
1194 str++;
1195 }
fecd2382 1196 }
6d27d3a2 1197
f8701a3f 1198 if ((current_architecture & m68020up) == 0) {
a39116f1 1199 return(FAIL);
f8701a3f 1200 } /* if target is not a '20 or better */
6d27d3a2
KR		 1201
1202
f8701a3f
SC		 1203 if(opP->ireg != FAIL) {
1204 opP->mode = APRDX;
6d27d3a2 1205
f8701a3f
SC		 1206 i = try_index(&str, opP);
1207 if (i != FAIL) {
1208 opP->error = "Two index registers! not allowed!";
1209 return(FAIL);
1210 }
865a2edf 1211 } else {
f8701a3f 1212 i = try_index(&str, opP);
865a2edf 1213 }
6d27d3a2 1214
f8701a3f
SC		 1215 if (i == FAIL) {
1216 char *beg_str;
6d27d3a2 1217
f8701a3f 1218 beg_str = str;
6d27d3a2 1219
f8701a3f
SC		 1220 for (i = 1; i; ) {
1221 switch(*str++) {
1222 case '\0':
a933d598 1223 if (needp)
f8701a3f
SC		 1224 opP->error="Missing )";
1225 return(FAIL);
a933d598 1226 break;
f8701a3f
SC		 1227 case ',': i=0; break;
1228 case '(': i++; break;
1229 case ')': --i; break;
1230 }
1231 }
6d27d3a2 1232
f8701a3f 1233 opP->con2=add_exp(beg_str,str-2);
6d27d3a2 1234
f8701a3f
SC		 1235 if (str[-1] == ',') {
1236 if (opP->ireg != FAIL) {
1237 opP->error = "Can't have two index regs";
1238 return(FAIL);
1239 }
6d27d3a2 1240
f8701a3f 1241 i = try_index(&str, opP);
6d27d3a2 1242
f8701a3f
SC		 1243 if (i == FAIL) {
1244 opP->error = "malformed index reg";
1245 return(FAIL);
1246 }
6d27d3a2 1247
f8701a3f
SC		 1248 opP->mode = APODX;
1249 } else if (opP->ireg != FAIL) {
1250 opP->mode = APRDX;
1251 } else {
1252 opP->mode = AMIND;
1253 }
1254 } else {
1255 opP->mode = APODX;
1256 }
6d27d3a2 1257
f8701a3f
SC		 1258 if(*str!='\0') {
1259 opP->error="Junk after indirect";
1260 return FAIL;
1261 }
1262 return(OK);
a39116f1 1263} /* m68k_ip_op() */
fecd2382 1264
7c15cbe8 1265
3ad9ec6a
ILT		 1266#ifdef M68KCOFF
1267
1268short tc_coff_fix2rtype(fixP)
1269fixS *fixP;
fecd2382 1270{
3ad9ec6a
ILT		 1271 return (fixP->fx_pcrel ?
1272 (fixP->fx_size == 1 ? R_PCRBYTE :
1273 fixP->fx_size == 2 ? R_PCRWORD :
1274 R_PCRLONG):
1275 (fixP->fx_size == 1 ? R_RELBYTE :
1276 fixP->fx_size == 2 ? R_RELWORD :
1277 R_RELLONG));
6d27d3a2 1278
3ad9ec6a
ILT		 1279
1280}
1281
1282#endif
fecd2382
RP		 1283
1284#ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
1285main()
1286{
f8701a3f
SC		 1287 char buf[128];
1288 struct m68k_op thark;
6d27d3a2 1289
f8701a3f
SC		 1290 for(;;) {
1291 if(!gets(buf))
1292 break;
1293 memset(&thark, '\0', sizeof(thark));
1294 if(!m68k_ip_op(buf,&thark)) printf("FAIL:");
1295 if(thark.error)
1296 printf("op1 error %s in %s\n",thark.error,buf);
1297 printf("mode %d, reg %d, ",thark.mode,thark.reg);
1298 if(thark.b_const)
1299 printf("Constant: '%.*s',",1+thark.e_const-thark.b_const,thark.b_const);
1300 printf("ireg %d, isiz %d, imul %d ",thark.ireg,thark.isiz,thark.imul);
1301 if(thark.b_iadd)
1302 printf("Iadd: '%.*s'",1+thark.e_iadd-thark.b_iadd,thark.b_iadd);
1303 printf("\n");
1304 }
1305 exit(0);
fecd2382
RP		 1306}
1307
1308#endif
1309
1310
1311static struct hash_control* op_hash = NULL; /* handle of the OPCODE hash table
a39116f1
RP		 1312 NULL means any use before m68k_ip_begin()
1313 will crash */
fecd2382
RP		 1314
1315\f
1316/*
7c15cbe8 1317 * m 6 8 k _ i p ( )
fecd2382
RP		 1318 *
1319 * This converts a string into a 68k instruction.
1320 * The string must be a bare single instruction in sun format
1321 * with RMS-style 68020 indirects
1322 * (example: )
1323 *
1324 * It provides some error messages: at most one fatal error message (which
1325 * stops the scan) and at most one warning message for each operand.
1326 * The 68k instruction is returned in exploded form, since we have no
1327 * knowledge of how you parse (or evaluate) your expressions.
1328 * We do however strip off and decode addressing modes and operation
1329 * mnemonic.
1330 *
1331 * This function's value is a string. If it is not "" then an internal
1332 * logic error was found: read this code to assign meaning to the string.
1333 * No argument string should generate such an error string:
1334 * it means a bug in our code, not in the user's text.
1335 *
7c15cbe8 1336 * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using
fecd2382
RP		 1337 * this function.
1338 */
1339
1340/* JF this function no longer returns a useful value. Sorry */
7c15cbe8 1341void m68k_ip (instring)
6d27d3a2 1342 char *instring;
fecd2382 1343{
6d27d3a2
KR		 1344 register char *p;
1345 register struct m68k_op *opP;
1346 register struct m68k_incant *opcode;
1347 register char *s;
1348 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
3ad9ec6a 1349 char *pdot, *pdotmove;
6d27d3a2
KR		 1350 int siz1, siz2;
1351 char c;
1352 int losing;
1353 int opsfound;
1354 char *crack_operand();
1355 LITTLENUM_TYPE words[6];
1356 LITTLENUM_TYPE *wordp;
8be74775 1357 unsigned long ok_arch = 0;
6d27d3a2
KR		 1358
1359 if (*instring == ' ')
1360 instring++; /* skip leading whitespace */
1361
1362 /* Scan up to end of operation-code, which MUST end in end-of-string
1363 or exactly 1 space. */
3ad9ec6a
ILT		 1364 pdot = 0;
1365 for (p = instring; *p != '\0'; p++) {
6d27d3a2
KR		 1366 if (*p == ' ')
1367 break;
3ad9ec6a
ILT		 1368 if (*p == '.')
1369 pdot = p;
1370 }
6d27d3a2
KR		 1371
1372 if (p == instring) {
1373 the_ins.error = "No operator";
1374 the_ins.opcode[0] = NULL;
1375 /* the_ins.numo=1; */
1376 return;
1377 }
1378
1379 /* p now points to the end of the opcode name, probably whitespace.
1380 make sure the name is null terminated by clobbering the whitespace,
3ad9ec6a
ILT		 1381 look it up in the hash table, then fix it back.
1382 Remove a dot, first, since the opcode tables have none. */
1383 if (pdot != NULL) {
1384 for (pdotmove=pdot; pdotmove<p; pdotmove++)
1385 *pdotmove=pdotmove[1];
1386 p--;
1387 }
1388
6d27d3a2
KR		 1389 c = *p;
1390 *p = '\0';
1391 opcode = (struct m68k_incant *)hash_find (op_hash, instring);
1392 *p = c;
1393
3ad9ec6a
ILT		 1394 if (pdot != NULL) {
1395 for (pdotmove=p; pdotmove>pdot; pdotmove--)
1396 *pdotmove=pdotmove[-1];
1397 *pdot='.';
1398 ++p;
1399 }
1400
6d27d3a2
KR		 1401 if (opcode == NULL) {
1402 the_ins.error = "Unknown operator";
1403 the_ins.opcode[0] = NULL;
1404 /* the_ins.numo=1; */
1405 return;
1406 }
1407
1408 /* found a legitimate opcode, start matching operands */
1409 while (*p == ' ') ++p;
1410
3ad9ec6a
ILT		 1411
1412 if (opcode->m_operands == 0) {
1413 char *old = input_line_pointer;
1414 *old = '\n';
1415 input_line_pointer = p;
1416 /* Ahh - it's a motorola style psuedo op */
1417 mote_pseudo_table[opcode->m_opnum].poc_handler
1418 ( mote_pseudo_table[opcode->m_opnum].poc_val);
1419 input_line_pointer = old;
1420 *old = 0;
1421
1422 return;
1423 }
1424
6d27d3a2
KR		 1425 for(opP = &the_ins.operands[0]; *p; opP++) {
1426
1427 p = crack_operand(p, opP);
1428
1429 if (opP->error) {
1430 the_ins.error=opP->error;
1431 return;
1432 }
1433 }
1434
1435 opsfound = opP - &the_ins.operands[0];
1436
1437 /* This ugly hack is to support the floating pt opcodes in their standard form */
1438 /* Essentially, we fake a first enty of type COP#1 */
1439 if (opcode->m_operands[0]=='I') {
1440 int n;
1441
1442 for(n=opsfound;n>0;--n)
1443 the_ins.operands[n]=the_ins.operands[n-1];
1444
6d27d3a2
KR		 1445 memset((char *)(&the_ins.operands[0]), '\0', sizeof(the_ins.operands[0]));
1446 the_ins.operands[0].mode=MSCR;
1447 the_ins.operands[0].reg=COPNUM; /* COP #1 */
1448 opsfound++;
1449 }
1450
1451 /* We've got the operands. Find an opcode that'll accept them */
1452 for (losing = 0; ; ) {
1453 /* if we didn't get the right number of ops,
1454 or we have no common model with this pattern
1455 then reject this pattern. */
1456
1457 if (opsfound != opcode->m_opnum
8be74775
KR		 1458 || ((opcode->m_arch & current_architecture) == 0))
1459 {
1460 ++losing;
1461 ok_arch |= opcode->m_arch;
1462 }
1463 else {
1464 for (s=opcode->m_operands, opP = &the_ins.operands[0]; *s && !losing; s += 2, opP++) {
1465 /* Warning: this switch is huge! */
1466 /* I've tried to organize the cases into this order:
1467 non-alpha first, then alpha by letter. lower-case goes directly
1468 before uppercase counterpart. */
1469 /* Code with multiple case ...: gets sorted by the lowest case ...
1470 it belongs to. I hope this makes sense. */
1471 switch(*s) {
1472 case '!':
1473 if (opP->mode == MSCR || opP->mode == IMMED
1474 || opP->mode == DREG || opP->mode == AREG
1475 || opP->mode == AINC || opP->mode == ADEC
1476 || opP->mode == REGLST)
1477 losing++;
1478 break;
1479
df3768fb
KR		 1480 case '`':
1481 switch (opP->mode) {
1482 case MSCR: case IMMED: case DREG: case AREG:
1483 case AINC: case REGLST: case AINDR:
1484 losing++;
1485 }
1486 break;
1487
8be74775
KR		 1488 case '#':
1489 if(opP->mode!=IMMED)
1490 losing++;
1491 else {
1492 long t;
6d27d3a2 1493
8be74775
KR		 1494 t=get_num(opP->con1,80);
1495 if(s[1]=='b' && !isbyte(t))
1496 losing++;
1497 else if(s[1]=='w' && !isword(t))
1498 losing++;
1499 }
1500 break;
1501
1502 case '^':
1503 case 'T':
1504 if(opP->mode!=IMMED)
1505 losing++;
1506 break;
1507
1508 case '$':
1509 if(opP->mode==MSCR || opP->mode==AREG ||
1510 opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST)
1511 losing++;
1512 break;
1513
1514 case '%':
1515 if(opP->mode==MSCR || opP->reg==PC ||
1516 opP->reg==ZPC || opP->mode==REGLST)
1517 losing++;
1518 break;
1519
1520
1521 case '&':
1522 if(opP->mode==MSCR || opP->mode==DREG ||
1523 opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC ||
1524 opP->mode==AINC || opP->mode==ADEC || opP->mode==REGLST)
1525 losing++;
1526 break;
1527
1528 case '*':
1529 if(opP->mode==MSCR || opP->mode==REGLST)
1530 losing++;
1531 break;
6d27d3a2 1532
8be74775
KR		 1533 case '+':
1534 if(opP->mode!=AINC)
1535 losing++;
1536 break;
6d27d3a2 1537
8be74775
KR		 1538 case '-':
1539 if(opP->mode!=ADEC)
1540 losing++;
1541 break;
1542
1543 case '/':
1544 if(opP->mode==MSCR || opP->mode==AREG ||
1545 opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->mode==REGLST)
1546 losing++;
1547 break;
1548
1549 case ';':
1550 if(opP->mode==MSCR || opP->mode==AREG || opP->mode==REGLST)
1551 losing++;
1552 break;
1553
1554 case '?':
1555 if(opP->mode==MSCR || opP->mode==AREG ||
1556 opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->reg==PC ||
1557 opP->reg==ZPC || opP->mode==REGLST)
1558 losing++;
1559 break;
1560
1561 case '@':
1562 if(opP->mode==MSCR || opP->mode==AREG ||
1563 opP->mode==IMMED || opP->mode==REGLST)
1564 losing++;
1565 break;
1566
1567 case '~': /* For now! (JF FOO is this right?) */
1568 if(opP->mode==MSCR || opP->mode==DREG ||
1569 opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST)
1570 losing++;
1571 break;
1572
4134a793
KR		 1573 case '3':
1574 if (opP->mode != MSCR || (opP->reg != TT0 && opP->reg != TT1))
1575 losing++;
1576 break;
1577
8be74775
KR		 1578 case 'A':
1579 if(opP->mode!=AREG)
1580 losing++;
1581 break;
1582 case 'a':
1583 if (opP->mode != AINDR) {
1584 ++losing;
1585 } /* if not address register indirect */
1586 break;
1587 case 'B': /* FOO */
1588 if(opP->mode!=ABSL || (flagseen['S'] && instring[0] == 'j'
1589 && instring[1] == 'b'
1590 && instring[2] == 's'
1591 && instring[3] == 'r'))
1592 losing++;
1593 break;
1594
1595 case 'C':
1596 if(opP->mode!=MSCR || opP->reg!=CCR)
1597 losing++;
1598 break;
1599
1600 case 'd': /* FOO This mode is a KLUDGE!! */
1601 if(opP->mode!=AOFF && (opP->mode!=ABSL ||
1602 opP->con1->e_beg[0]!='(' || opP->con1->e_end[0]!=')'))
1603 losing++;
1604 break;
1605
1606 case 'D':
1607 if(opP->mode!=DREG)
1608 losing++;
1609 break;
1610
1611 case 'F':
1612 if(opP->mode!=MSCR || opP->reg<(FPREG+0) || opP->reg>(FPREG+7))
1613 losing++;
1614 break;
1615
1616 case 'I':
1617 if(opP->mode!=MSCR || opP->reg<COPNUM ||
1618 opP->reg>=COPNUM+7)
1619 losing++;
1620 break;
1621
1622 case 'J':
1623 if (opP->mode != MSCR
1624 || opP->reg < USP
1625 || opP->reg > URP
1626 || cpu_of_arch(current_architecture) < m68010 /* before 68010 had none */
1627 || (cpu_of_arch(current_architecture) < m68020
1628 && opP->reg != SFC
1629 && opP->reg != DFC
1630 && opP->reg != USP
1631 && opP->reg != VBR) /* 68010's had only these */
1632 || (cpu_of_arch(current_architecture) < m68040
1633 && opP->reg != SFC
1634 && opP->reg != DFC
1635 && opP->reg != USP
1636 && opP->reg != VBR
1637 && opP->reg != CACR
1638 && opP->reg != CAAR
1639 && opP->reg != MSP
1640 && opP->reg != ISP) /* 680[23]0's have only these */
1641 || (cpu_of_arch(current_architecture) == m68040 /* 68040 has all but this */
1642 && opP->reg == CAAR)) {
1643 losing++;
1644 } /* doesn't cut it */
1645 break;
1646
1647 case 'k':
1648 if(opP->mode!=IMMED)
1649 losing++;
1650 break;
6d27d3a2 1651
8be74775
KR		 1652 case 'l':
1653 case 'L':
1654 if(opP->mode==DREG || opP->mode==AREG || opP->mode==FPREG) {
1655 if(s[1]=='8')
1656 losing++;
1657 else {
1658 opP->mode=REGLST;
1659 opP->reg=1<<(opP->reg-DATA);
1660 }
1661 } else if(opP->mode!=REGLST) {
1662 losing++;
1663 } else if(s[1]=='8' && opP->reg&0x0FFffFF)
1664 losing++;
1665 else if(s[1]=='3' && opP->reg&0x7000000)
1666 losing++;
1667 break;
1668
1669 case 'M':
1670 if(opP->mode!=IMMED)
1671 losing++;
1672 else {
1673 long t;
6d27d3a2 1674
8be74775
KR		 1675 t=get_num(opP->con1,80);
1676 if(!issbyte(t) || isvar(opP->con1))
1677 losing++;
1678 }
1679 break;
6d27d3a2 1680
8be74775
KR		 1681 case 'O':
1682 if(opP->mode!=DREG && opP->mode!=IMMED)
1683 losing++;
1684 break;
6d27d3a2 1685
8be74775
KR		 1686 case 'Q':
1687 if(opP->mode!=IMMED)
1688 losing++;
1689 else {
1690 long t;
6d27d3a2 1691
8be74775
KR		 1692 t=get_num(opP->con1,80);
1693 if(t<1 || t>8 || isvar(opP->con1))
1694 losing++;
1695 }
1696 break;
1697
1698 case 'R':
1699 if(opP->mode!=DREG && opP->mode!=AREG)
1700 losing++;
1701 break;
1702
c50140c8
ILT		 1703 case 'r':
1704 if (opP->mode!=AINDR && opP->mode!=DINDR)
1705 losing++;
1706 break;
1707
8be74775
KR		 1708 case 's':
1709 if(opP->mode!=MSCR || !(opP->reg==FPI || opP->reg==FPS || opP->reg==FPC))
1710 losing++;
1711 break;
1712
1713 case 'S':
1714 if(opP->mode!=MSCR || opP->reg!=SR)
1715 losing++;
1716 break;
1717
4134a793
KR		 1718 case 't':
1719 if (opP->mode != IMMED)
1720 losing++;
1721 else
1722 {
1723 long t = get_num (opP->con1, 80);
1724 if (t < 0 || t > 7 || isvar (opP->con1))
1725 losing++;
1726 }
1727 break;
1728
8be74775
KR		 1729 case 'U':
1730 if(opP->mode!=MSCR || opP->reg!=USP)
1731 losing++;
1732 break;
1733
1734 /* JF these are out of order. We could put them
1735 in order if we were willing to put up with
4134a793
KR		 1736 bunches of #ifdef m68851s in the code.
1737
1738 Don't forget that you need these operands
1739 to use 68030 MMU instructions. */
f8701a3f 1740#ifndef NO_68851
8be74775
KR		 1741 /* Memory addressing mode used by pflushr */
1742 case '|':
1743 if(opP->mode==MSCR || opP->mode==DREG ||
1744 opP->mode==AREG || opP->mode==REGLST)
1745 losing++;
1746 break;
1747
1748 case 'f':
1749 if (opP->mode != MSCR || (opP->reg != SFC && opP->reg != DFC))
1750 losing++;
1751 break;
1752
1753 case 'P':
4134a793
KR		 1754 if (opP->mode != MSCR
1755 || (opP->reg != TC && opP->reg != CAL
1756 && opP->reg != VAL && opP->reg != SCC && opP->reg != AC))
8be74775
KR		 1757 losing++;
1758 break;
1759
1760 case 'V':
1761 if (opP->reg != VAL)
1762 losing++;
1763 break;
6d27d3a2 1764
8be74775 1765 case 'W':
4134a793
KR		 1766 if (opP->mode != MSCR
1767 || (opP->reg != DRP && opP->reg != SRP
1768 && opP->reg != CRP))
8be74775
KR		 1769 losing++;
1770 break;
1771
1772 case 'X':
1773 if (opP->mode != MSCR ||
1774 (!(opP->reg >= BAD && opP->reg <= BAD+7) &&
1775 !(opP->reg >= BAC && opP->reg <= BAC+7)))
1776 losing++;
1777 break;
1778
1779 case 'Y':
1780 if (opP->reg != PSR)
1781 losing++;
1782 break;
1783
1784 case 'Z':
1785 if (opP->reg != PCSR)
1786 losing++;
1787 break;
f8701a3f 1788#endif
8be74775
KR		 1789 case 'c':
1790 if (opP->reg != NC
1791 && opP->reg != IC
1792 && opP->reg != DC
1793 && opP->reg != BC) {
1794 losing++;
1795 } /* not a cache specifier. */
1796 break;
1797
1798 case '_':
1799 if (opP->mode != ABSL) {
1800 ++losing;
1801 } /* not absolute */
1802 break;
6d27d3a2 1803
8be74775 1804 default:
4134a793 1805 as_fatal("Internal error: Operand mode %c unknown in line %d of file \"%s\"",
8be74775
KR		 1806 *s, __LINE__, __FILE__);
1807 } /* switch on type of operand */
6d27d3a2 1808
8be74775
KR		 1809 if (losing)
1810 break;
1811 } /* for each operand */
1812 } /* if immediately wrong */
6d27d3a2
KR		 1813
1814 if (!losing) {
1815 break;
1816 } /* got it. */
1817
1818 opcode = opcode->m_next;
1819
1820 if (!opcode) {
4134a793
KR		 1821 if (ok_arch
1822 && !(ok_arch & current_architecture))
8be74775
KR		 1823 {
1824 char buf[200], *cp;
1825 int len;
1826 strcpy (buf, "invalid instruction for this architecture; needs ");
1827 cp = buf + strlen (buf);
1828 switch (ok_arch)
1829 {
1830 case mfloat:
4134a793 1831 strcpy (cp, "fpu (68040 or 68881/68882)");
8be74775
KR		 1832 break;
1833 case mmmu:
4134a793 1834 strcpy (cp, "mmu (68030 or 68851)");
8be74775
KR		 1835 break;
1836 case m68020up:
1837 strcpy (cp, "68020 or higher");
1838 break;
1839 case m68000up:
1840 strcpy (cp, "68000 or higher");
1841 break;
1842 case m68010up:
1843 strcpy (cp, "68010 or higher");
1844 break;
1845 default:
1846 {
1847 int got_one = 0, idx;
1848 const static struct {
df3768fb 1849 int arch;
8be74775
KR		 1850 const char *name;
1851 } archs[] = {
1852 m68000, "68000",
1853 m68010, "68010",
1854 m68020, "68020",
1855 m68030, "68030",
1856 m68040, "68040",
df3768fb 1857 cpu32, "cpu32",
8be74775
KR		 1858 m68881, "68881",
1859 m68851, "68851",
1860 };
1861 for (idx = 0; idx < sizeof (archs)/sizeof (archs[0]); idx++)
1862 {
1863 if (archs[idx].arch & ok_arch)
1864 {
1865 if (got_one)
1866 {
1867 strcpy (cp, " or ");
1868 cp += strlen (cp);
1869 }
1870 got_one = 1;
1871 strcpy (cp, archs[idx].name);
1872 cp += strlen (cp);
1873 }
1874 }
1875 }
1876 }
1877 len = cp - buf + 1;
1878 cp = malloc (len);
1879 strcpy (cp, buf);
1880 the_ins.error = cp;
1881 }
1882 else
1883 the_ins.error = "operands mismatch";
6d27d3a2
KR		 1884 return;
1885 } /* Fell off the end */
1886
1887 losing = 0;
1888 }
1889
1890 /* now assemble it */
1891
1892 the_ins.args=opcode->m_operands;
1893 the_ins.numargs=opcode->m_opnum;
1894 the_ins.numo=opcode->m_codenum;
1895 the_ins.opcode[0]=getone(opcode);
1896 the_ins.opcode[1]=gettwo(opcode);
1897
1898 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++) {
1899 /* This switch is a doozy.
1900 Watch the first step; its a big one! */
1901 switch(s[0]) {
1902
1903 case '*':
1904 case '~':
1905 case '%':
1906 case ';':
1907 case '@':
1908 case '!':
1909 case '&':
1910 case '$':
1911 case '?':
1912 case '/':
df3768fb 1913 case '`':
f8701a3f 1914#ifndef NO_68851
6d27d3a2 1915 case '|':
f8701a3f 1916#endif
6d27d3a2
KR		 1917 switch(opP->mode) {
1918 case IMMED:
1919 tmpreg=0x3c; /* 7.4 */
1920 if (strchr("bwl",s[1])) nextword=get_num(opP->con1,80);
1921 else nextword=nextword=get_num(opP->con1,0);
1922 if(isvar(opP->con1))
1923 add_fix(s[1],opP->con1,0);
1924 switch(s[1]) {
1925 case 'b':
1926 if(!isbyte(nextword))
1927 opP->error="operand out of range";
1928 addword(nextword);
1929 baseo=0;
1930 break;
1931 case 'w':
1932 if(!isword(nextword))
1933 opP->error="operand out of range";
1934 addword(nextword);
1935 baseo=0;
1936 break;
1937 case 'l':
1938 addword(nextword>>16);
1939 addword(nextword);
1940 baseo=0;
1941 break;
1942
1943 case 'f':
1944 baseo=2;
1945 outro=8;
1946 break;
1947 case 'F':
1948 baseo=4;
1949 outro=11;
1950 break;
1951 case 'x':
1952 baseo=6;
1953 outro=15;
1954 break;
1955 case 'p':
1956 baseo=6;
1957 outro= -1;
1958 break;
1959 default:
1960 as_fatal("Internal error: Can't decode %c%c in line %s of file \"%s\"",
1961 *s, s[1], __LINE__, __FILE__);
1962 }
1963 if(!baseo)
1964 break;
1965
1966 /* We gotta put out some float */
1967 if(seg(opP->con1)!=SEG_BIG) {
1968 int_to_gen(nextword);
1969 gen_to_words(words,baseo,(long int)outro);
1970 for(wordp=words;baseo--;wordp++)
1971 addword(*wordp);
1972 break;
1973 } /* Its BIG */
1974 if(offs(opP->con1)>0) {
6d27d3a2
KR		 1975 if(offs(opP->con1)>baseo) {
1976 as_warn("Bignum too big for %c format; truncated",s[1]);
1977 offs(opP->con1)=baseo;
1978 }
1979 baseo-=offs(opP->con1);
1980 for(wordp=generic_bignum+offs(opP->con1)-1;offs(opP->con1)--;--wordp)
1981 addword(*wordp);
1982 while(baseo--)
1983 addword(0);
1984 break;
1985 }
1986 gen_to_words(words,baseo,(long)outro);
1987 for (wordp=words;baseo--;wordp++)
1988 addword(*wordp);
1989 break;
1990 case DREG:
1991 tmpreg=opP->reg-DATA; /* 0.dreg */
1992 break;
1993 case AREG:
1994 tmpreg=0x08+opP->reg-ADDR; /* 1.areg */
1995 break;
1996 case AINDR:
1997 tmpreg=0x10+opP->reg-ADDR; /* 2.areg */
1998 break;
1999 case ADEC:
2000 tmpreg=0x20+opP->reg-ADDR; /* 4.areg */
2001 break;
2002 case AINC:
2003 tmpreg=0x18+opP->reg-ADDR; /* 3.areg */
2004 break;
2005 case AOFF:
2006
2007 nextword=get_num(opP->con1,80);
2008 /* Force into index mode. Hope this works */
2009
2010 /* We do the first bit for 32-bit displacements,
2011 and the second bit for 16 bit ones. It is
2012 possible that we should make the default be
2013 WORD instead of LONG, but I think that'd
2014 break GCC, so we put up with a little
2015 inefficiency for the sake of working output.
2016 */
2017
2018 if( !issword(nextword)
2019 || ( isvar(opP->con1)
2020 && ( ( opP->con1->e_siz==0
2021 && flagseen['l']==0)
2022 || opP->con1->e_siz==3))) {
2023
2024 if(opP->reg==PC)
2025 tmpreg=0x3B; /* 7.3 */
2026 else
2027 tmpreg=0x30+opP->reg-ADDR; /* 6.areg */
2028 if(isvar(opP->con1)) {
2029 if(opP->reg==PC) {
2030 add_frag(adds(opP->con1),
2031 offs(opP->con1),
2032 TAB(PCLEA,SZ_UNDEF));
2033 break;
2034 } else {
2035 addword(0x0170);
04b07d16 2036 add_fix('l',opP->con1,0);
6d27d3a2
KR		 2037 }
2038 } else
2039 addword(0x0170);
2040 addword(nextword>>16);
2041 } else {
2042 if(opP->reg==PC)
2043 tmpreg=0x3A; /* 7.2 */
2044 else
2045 tmpreg=0x28+opP->reg-ADDR; /* 5.areg */
2046
2047 if(isvar(opP->con1)) {
2048 if(opP->reg==PC) {
2049 add_fix('w',opP->con1,1);
2050 } else
2051 add_fix('w',opP->con1,0);
2052 }
2053 }
2054 addword(nextword);
2055 break;
2056
2057 case APODX:
2058 case AMIND:
2059 case APRDX:
2060 know(current_architecture & m68020up);
2061 /* intentional fall-through */
2062 case AINDX:
2063 nextword=0;
2064 baseo=get_num(opP->con1,80);
2065 outro=get_num(opP->con2,80);
2066 /* Figure out the 'addressing mode' */
2067 /* Also turn on the BASE_DISABLE bit, if needed */
2068 if(opP->reg==PC || opP->reg==ZPC) {
2069 tmpreg=0x3b; /* 7.3 */
2070 if(opP->reg==ZPC)
2071 nextword|=0x80;
2072 } else if(opP->reg==FAIL) {
2073 nextword|=0x80;
2074 tmpreg=0x30; /* 6.garbage */
2075 } else tmpreg=0x30+opP->reg-ADDR; /* 6.areg */
2076
2077 siz1= (opP->con1) ? opP->con1->e_siz : 0;
2078 siz2= (opP->con2) ? opP->con2->e_siz : 0;
2079
2080 /* Index register stuff */
2081 if(opP->ireg>=DATA+0 && opP->ireg<=ADDR+7) {
2082 nextword|=(opP->ireg-DATA)<<12;
2083
2084 if(opP->isiz==0 || opP->isiz==3)
2085 nextword|=0x800;
2086 switch(opP->imul) {
2087 case 1: break;
2088 case 2: nextword|=0x200; break;
2089 case 4: nextword|=0x400; break;
2090 case 8: nextword|=0x600; break;
2091 default: as_fatal("failed sanity check.");
2092 }
2093 /* IF its simple,
2094 GET US OUT OF HERE! */
2095
2096 /* Must be INDEX, with an index
2097 register. Address register
2098 cannot be ZERO-PC, and either
2099 :b was forced, or we know
2100 it will fit */
2101 if( opP->mode==AINDX
2102 && opP->reg!=FAIL
2103 && opP->reg!=ZPC
2104 && ( siz1==1
2105 || ( issbyte(baseo)
2106 && !isvar(opP->con1)))) {
2107 nextword +=baseo&0xff;
2108 addword(nextword);
2109 if(isvar(opP->con1))
2110 add_fix('B',opP->con1,0);
2111 break;
2112 }
2113 } else
2114 nextword|=0x40; /* No index reg */
2115
2116 /* It aint simple */
2117 nextword|=0x100;
2118 /* If the guy specified a width, we assume that
2119 it is wide enough. Maybe it isn't. If so, we lose
2120 */
2121 switch(siz1) {
2122 case 0:
2123 if(isvar(opP->con1) || !issword(baseo)) {
2124 siz1=3;
2125 nextword|=0x30;
2126 } else if(baseo==0)
2127 nextword|=0x10;
2128 else {
2129 nextword|=0x20;
2130 siz1=2;
2131 }
2132 break;
2133 case 1:
2134 as_warn("Byte dispacement won't work. Defaulting to :w");
2135 case 2:
2136 nextword|=0x20;
2137 break;
2138 case 3:
2139 nextword|=0x30;
2140 break;
2141 }
2142
2143 /* Figure out innner displacement stuff */
2144 if(opP->mode!=AINDX) {
2145 switch(siz2) {
2146 case 0:
2147 if(isvar(opP->con2) || !issword(outro)) {
2148 siz2=3;
2149 nextword|=0x3;
2150 } else if(outro==0)
2151 nextword|=0x1;
2152 else {
2153 nextword|=0x2;
2154 siz2=2;
2155 }
2156 break;
2157 case 1:
2158 as_warn("Byte dispacement won't work. Defaulting to :w");
2159 case 2:
2160 nextword|=0x2;
2161 break;
2162 case 3:
2163 nextword|=0x3;
2164 break;
2165 }
2166 if(opP->mode==APODX) nextword|=0x04;
2167 else if(opP->mode==AMIND) nextword|=0x40;
2168 }
2169 addword(nextword);
2170
2171 if(isvar(opP->con1)) {
2172 if(opP->reg==PC || opP->reg==ZPC) {
2173 add_fix(siz1==3 ? 'l' : 'w',opP->con1,1);
2174 opP->con1->e_exp.X_add_number+=6;
2175 } else
2176 add_fix(siz1==3 ? 'l' : 'w',opP->con1,0);
2177 }
2178 if(siz1==3)
2179 addword(baseo>>16);
2180 if(siz1)
2181 addword(baseo);
2182
2183 if(isvar(opP->con2)) {
2184 if(opP->reg==PC || opP->reg==ZPC) {
2185 add_fix(siz2==3 ? 'l' : 'w',opP->con2,1);
2186 opP->con1->e_exp.X_add_number+=6;
2187 } else
2188 add_fix(siz2==3 ? 'l' : 'w',opP->con2,0);
2189 }
2190 if(siz2==3)
2191 addword(outro>>16);
2192 if(siz2)
2193 addword(outro);
2194
2195 break;
2196
2197 case ABSL:
2198 nextword=get_num(opP->con1,80);
2199 switch(opP->con1->e_siz) {
2200 default:
2201 as_warn("Unknown size for absolute reference");
2202 case 0:
2203 if(!isvar(opP->con1) && issword(offs(opP->con1))) {
2204 tmpreg=0x38; /* 7.0 */
2205 addword(nextword);
2206 break;
2207 }
2208 /* Don't generate pc relative code
2209 on 68010 and 68000 */
2210 if(isvar(opP->con1)
2211 && !subs(opP->con1)
2212 && seg(opP->con1) == SEG_TEXT
2213 && now_seg == SEG_TEXT
2214 && cpu_of_arch(current_architecture) >= m68020
2215 && !flagseen['S']
2216 && !strchr("~%&$?", s[0])) {
2217 tmpreg=0x3A; /* 7.2 */
2218 add_frag(adds(opP->con1),
2219 offs(opP->con1),
2220 TAB(PCREL,SZ_UNDEF));
2221 break;
2222 }
2223 case 3: /* Fall through into long */
2224 if(isvar(opP->con1))
2225 add_fix('l',opP->con1,0);
2226
2227 tmpreg=0x39; /* 7.1 mode */
2228 addword(nextword>>16);
2229 addword(nextword);
2230 break;
2231
2232 case 2: /* Word */
2233 if(isvar(opP->con1))
2234 add_fix('w',opP->con1,0);
2235
2236 tmpreg=0x38; /* 7.0 mode */
2237 addword(nextword);
2238 break;
2239 }
2240 break;
c50140c8
ILT		 2241 case DINDR:
2242 as_bad("invalid indirect register");
2243 break;
6d27d3a2
KR		 2244 case MSCR:
2245 default:
2246 as_bad("unknown/incorrect operand");
2247 /* abort(); */
2248 }
2249 install_gen_operand(s[1],tmpreg);
2250 break;
2251
2252 case '#':
2253 case '^':
2254 switch(s[1]) { /* JF: I hate floating point! */
2255 case 'j':
2256 tmpreg=70;
2257 break;
2258 case '8':
2259 tmpreg=20;
2260 break;
2261 case 'C':
2262 tmpreg=50;
2263 break;
2264 case '3':
2265 default:
2266 tmpreg=80;
2267 break;
2268 }
2269 tmpreg=get_num(opP->con1,tmpreg);
2270 if(isvar(opP->con1))
2271 add_fix(s[1],opP->con1,0);
2272 switch(s[1]) {
2273 case 'b': /* Danger: These do no check for
2274 certain types of overflow.
2275 user beware! */
2276 if(!isbyte(tmpreg))
2277 opP->error="out of range";
2278 insop(tmpreg);
2279 if(isvar(opP->con1))
2280 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
2281 break;
2282 case 'w':
2283 if(!isword(tmpreg))
2284 opP->error="out of range";
2285 insop(tmpreg);
2286 if(isvar(opP->con1))
2287 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
2288 break;
2289 case 'l':
2290 insop(tmpreg); /* Because of the way insop works, we put these two out backwards */
2291 insop(tmpreg>>16);
2292 if(isvar(opP->con1))
2293 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
2294 break;
2295 case '3':
2296 tmpreg&=0xFF;
2297 case '8':
2298 case 'C':
2299 install_operand(s[1],tmpreg);
2300 break;
2301 default:
2302 as_fatal("Internal error: Unknown mode #%c in line %s of file \"%s\"", s[1], __LINE__, __FILE__);
2303 }
2304 break;
2305
2306 case '+':
2307 case '-':
2308 case 'A':
2309 case 'a':
2310 install_operand(s[1],opP->reg-ADDR);
2311 break;
2312
2313 case 'B':
2314 tmpreg=get_num(opP->con1,80);
2315 switch(s[1]) {
2316 case 'B':
2317 /* Needs no offsetting */
2318 add_fix('B',opP->con1,1);
2319 break;
2320 case 'W':
2321 /* Offset the displacement to be relative to byte disp location */
2322 opP->con1->e_exp.X_add_number+=2;
2323 add_fix('w',opP->con1,1);
2324 addword(0);
2325 break;
2326 case 'L':
2327 long_branch:
2328 if (cpu_of_arch(current_architecture) < m68020) /* 68000 or 010 */
2329 as_warn("Can't use long branches on 68000/68010");
2330 the_ins.opcode[the_ins.numo-1]|=0xff;
2331 /* Offset the displacement to be relative to byte disp location */
2332 opP->con1->e_exp.X_add_number+=4;
2333 add_fix('l',opP->con1,1);
2334 addword(0);
2335 addword(0);
2336 break;
2337 case 'g':
2338 if(subs(opP->con1)) /* We can't relax it */
2339 goto long_branch;
2340
2341 /* This could either be a symbol, or an
2342 absolute address. No matter, the
2343 frag hacking will finger it out.
2344 Not quite: it can't switch from
2345 BRANCH to BCC68000 for the case
2346 where opnd is absolute (it needs
2347 to use the 68000 hack since no
2348 conditional abs jumps). */
2349 if (((cpu_of_arch(current_architecture) < m68020) || (0==adds(opP->con1)))
2350 && (the_ins.opcode[0] >= 0x6200)
2351 && (the_ins.opcode[0] <= 0x6f00)) {
2352 add_frag(adds(opP->con1),offs(opP->con1),TAB(BCC68000,SZ_UNDEF));
2353 } else {
3ad9ec6a 2354 add_frag(adds(opP->con1),offs(opP->con1),TAB(ABRANCH,SZ_UNDEF));
6d27d3a2
KR		 2355 }
2356 break;
2357 case 'w':
2358 if(isvar(opP->con1)) {
2359 /* check for DBcc instruction */
2360 if ((the_ins.opcode[0] & 0xf0f8) ==0x50c8) {
2361 /* size varies if patch */
2362 /* needed for long form */
2363 add_frag(adds(opP->con1),offs(opP->con1),TAB(DBCC,SZ_UNDEF));
2364 break;
2365 }
2366
2367 /* Don't ask! */
2368 opP->con1->e_exp.X_add_number+=2;
2369 add_fix('w',opP->con1,1);
2370 }
2371 addword(0);
2372 break;
2373 case 'C': /* Fixed size LONG coproc branches */
2374 the_ins.opcode[the_ins.numo-1]|=0x40;
2375 /* Offset the displacement to be relative to byte disp location */
2376 /* Coproc branches don't have a byte disp option, but they are
2377 compatible with the ordinary branches, which do... */
2378 opP->con1->e_exp.X_add_number+=4;
2379 add_fix('l',opP->con1,1);
2380 addword(0);
2381 addword(0);
2382 break;
2383 case 'c': /* Var size Coprocesssor branches */
2384 if(subs(opP->con1)) {
2385 add_fix('l',opP->con1,1);
2386 add_frag((symbolS *)0,(long)0,TAB(FBRANCH,LONG));
2387 } else if(adds(opP->con1)) {
2388 add_frag(adds(opP->con1),offs(opP->con1),TAB(FBRANCH,SZ_UNDEF));
2389 } else {
2390 /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
2391 the_ins.opcode[the_ins.numo-1]|=0x40;
2392 add_fix('l',opP->con1,1);
2393 addword(0);
2394 addword(4);
2395 }
2396 break;
2397 default:
2398 as_fatal("Internal error: operand type B%c unknown in line %s of file \"%s\"",
2399 s[1], __LINE__, __FILE__);
2400 }
2401 break;
2402
2403 case 'C': /* Ignore it */
2404 break;
2405
2406 case 'd': /* JF this is a kludge */
2407 if(opP->mode==AOFF) {
2408 install_operand('s',opP->reg-ADDR);
2409 } else {
2410 char *tmpP;
2411
2412 tmpP=opP->con1->e_end-2;
2413 opP->con1->e_beg++;
2414 opP->con1->e_end-=4; /* point to the , */
2415 baseo=m68k_reg_parse(&tmpP);
2416 if(baseo<ADDR+0 || baseo>ADDR+7) {
2417 as_bad("Unknown address reg, using A0");
2418 baseo=0;
2419 } else baseo-=ADDR;
2420 install_operand('s',baseo);
2421 }
2422 tmpreg=get_num(opP->con1,80);
2423 if(!issword(tmpreg)) {
2424 as_warn("Expression out of range, using 0");
2425 tmpreg=0;
2426 }
2427 addword(tmpreg);
2428 break;
2429
2430 case 'D':
2431 install_operand(s[1],opP->reg-DATA);
2432 break;
2433
2434 case 'F':
2435 install_operand(s[1],opP->reg-FPREG);
2436 break;
2437
2438 case 'I':
2439 tmpreg=1+opP->reg-COPNUM;
2440 if(tmpreg==8)
2441 tmpreg=0;
2442 install_operand(s[1],tmpreg);
2443 break;
2444
2445 case 'J': /* JF foo */
2446 switch(opP->reg) {
2447 case SFC: tmpreg=0x000; break;
2448 case DFC: tmpreg=0x001; break;
2449 case CACR: tmpreg=0x002; break;
2450 case TC: tmpreg=0x003; break;
2451 case ITT0: tmpreg=0x004; break;
2452 case ITT1: tmpreg=0x005; break;
2453 case DTT0: tmpreg=0x006; break;
2454 case DTT1: tmpreg=0x007; break;
2455
2456 case USP: tmpreg=0x800; break;
2457 case VBR: tmpreg=0x801; break;
2458 case CAAR: tmpreg=0x802; break;
2459 case MSP: tmpreg=0x803; break;
2460 case ISP: tmpreg=0x804; break;
2461 case MMUSR: tmpreg=0x805; break;
2462 case URP: tmpreg=0x806; break;
2463 case SRP: tmpreg=0x807; break;
2464 default:
2465 as_fatal("failed sanity check.");
2466 }
2467 install_operand(s[1],tmpreg);
2468 break;
2469
2470 case 'k':
2471 tmpreg=get_num(opP->con1,55);
2472 install_operand(s[1],tmpreg&0x7f);
2473 break;
2474
2475 case 'l':
2476 tmpreg=opP->reg;
2477 if(s[1]=='w') {
2478 if(tmpreg&0x7FF0000)
2479 as_bad("Floating point register in register list");
2480 insop(reverse_16_bits(tmpreg));
2481 } else {
2482 if(tmpreg&0x700FFFF)
2483 as_bad("Wrong register in floating-point reglist");
2484 install_operand(s[1],reverse_8_bits(tmpreg>>16));
2485 }
2486 break;
2487
2488 case 'L':
2489 tmpreg=opP->reg;
2490 if(s[1]=='w') {
2491 if(tmpreg&0x7FF0000)
2492 as_bad("Floating point register in register list");
2493 insop(tmpreg);
2494 } else if(s[1]=='8') {
2495 if(tmpreg&0x0FFFFFF)
2496 as_bad("incorrect register in reglist");
2497 install_operand(s[1],tmpreg>>24);
2498 } else {
2499 if(tmpreg&0x700FFFF)
2500 as_bad("wrong register in floating-point reglist");
2501 else
2502 install_operand(s[1],tmpreg>>16);
2503 }
2504 break;
2505
2506 case 'M':
2507 install_operand(s[1],get_num(opP->con1,60));
2508 break;
2509
2510 case 'O':
2511 tmpreg= (opP->mode==DREG)
2512 ? 0x20+opP->reg-DATA
2513 : (get_num(opP->con1,40)&0x1F);
2514 install_operand(s[1],tmpreg);
2515 break;
2516
2517 case 'Q':
2518 tmpreg=get_num(opP->con1,10);
2519 if(tmpreg==8)
2520 tmpreg=0;
2521 install_operand(s[1],tmpreg);
2522 break;
2523
2524 case 'R':
c50140c8 2525 case 'r':
6d27d3a2
KR		 2526 /* This depends on the fact that ADDR registers are
2527 eight more than their corresponding DATA regs, so
2528 the result will have the ADDR_REG bit set */
2529 install_operand(s[1],opP->reg-DATA);
2530 break;
2531
2532 case 's':
2533 if(opP->reg==FPI) tmpreg=0x1;
2534 else if(opP->reg==FPS) tmpreg=0x2;
2535 else if(opP->reg==FPC) tmpreg=0x4;
2536 else as_fatal("failed sanity check.");
2537 install_operand(s[1],tmpreg);
2538 break;
2539
2540 case 'S': /* Ignore it */
2541 break;
2542
2543 case 'T':
2544 install_operand(s[1],get_num(opP->con1,30));
2545 break;
2546
2547 case 'U': /* Ignore it */
2548 break;
2549
2550 case 'c':
2551 switch (opP->reg) {
2552 case NC: tmpreg = 0; break;
2553 case DC: tmpreg = 1; break;
2554 case IC: tmpreg = 2; break;
2555 case BC: tmpreg = 3; break;
2556 default:
2557 as_fatal("failed sanity check");
2558 } /* switch on cache token */
2559 install_operand(s[1], tmpreg);
2560 break;
a39116f1 2561#ifndef NO_68851
6d27d3a2
KR		 2562 /* JF: These are out of order, I fear. */
2563 case 'f':
2564 switch (opP->reg) {
2565 case SFC:
2566 tmpreg=0;
2567 break;
2568 case DFC:
2569 tmpreg=1;
2570 break;
2571 default:
2572 as_fatal("failed sanity check.");
2573 }
2574 install_operand(s[1],tmpreg);
2575 break;
2576
2577 case 'P':
2578 switch(opP->reg) {
2579 case TC:
2580 tmpreg=0;
2581 break;
2582 case CAL:
2583 tmpreg=4;
2584 break;
2585 case VAL:
2586 tmpreg=5;
2587 break;
2588 case SCC:
2589 tmpreg=6;
2590 break;
2591 case AC:
2592 tmpreg=7;
2593 break;
2594 default:
2595 as_fatal("failed sanity check.");
2596 }
2597 install_operand(s[1],tmpreg);
2598 break;
2599
2600 case 'V':
2601 if (opP->reg == VAL)
2602 break;
2603 as_fatal("failed sanity check.");
2604
2605 case 'W':
2606 switch(opP->reg) {
2607
2608 case DRP:
2609 tmpreg=1;
2610 break;
2611 case SRP:
2612 tmpreg=2;
2613 break;
2614 case CRP:
2615 tmpreg=3;
2616 break;
2617 default:
2618 as_fatal("failed sanity check.");
2619 }
2620 install_operand(s[1],tmpreg);
2621 break;
2622
2623 case 'X':
2624 switch (opP->reg) {
2625 case BAD: case BAD+1: case BAD+2: case BAD+3:
2626 case BAD+4: case BAD+5: case BAD+6: case BAD+7:
2627 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2628 break;
2629
2630 case BAC: case BAC+1: case BAC+2: case BAC+3:
2631 case BAC+4: case BAC+5: case BAC+6: case BAC+7:
2632 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2633 break;
2634
2635 default:
2636 as_fatal("failed sanity check.");
2637 }
2638 install_operand(s[1], tmpreg);
2639 break;
2640 case 'Y':
2641 know(opP->reg == PSR);
2642 break;
2643 case 'Z':
2644 know(opP->reg == PCSR);
2645 break;
f8701a3f 2646#endif /* m68851 */
4134a793
KR		 2647 case '3':
2648 switch (opP->reg)
2649 {
2650 case TT0:
2651 tmpreg = 2;
2652 break;
2653 case TT1:
2654 tmpreg = 3;
2655 break;
2656 default:
2657 as_fatal ("failed sanity check");
2658 }
2659 install_operand (s[1], tmpreg);
2660 break;
2661 case 't':
2662 tmpreg = get_num (opP->con1, 20);
2663 install_operand (s[1], tmpreg);
2664 break;
2665 case '_': /* used only for move16 absolute 32-bit address */
6d27d3a2 2666 tmpreg=get_num(opP->con1,80);
065b6303
ILT		 2667 addword (tmpreg >> 16);
2668 addword (tmpreg & 0xFFFF);
6d27d3a2
KR		 2669 break;
2670 default:
4134a793
KR		 2671 as_fatal("Internal error: Operand type %c unknown in line %d of file \"%s\"",
2672 s[0], __LINE__, __FILE__);
6d27d3a2
KR		 2673 }
2674 }
3ad9ec6a 2675
6d27d3a2
KR		 2676 /* By the time whe get here (FINALLY) the_ins contains the complete
2677 instruction, ready to be emitted. . . */
7c15cbe8
RP		 2678} /* m68k_ip() */
2679
2680/*
2681 * get_regs := '/' + ?
2682 * | '-' + <register>
2683 * | '-' + <register> + ?
2684 * | <empty>
2685 * ;
2686 *
6d27d3a2 2687
7c15cbe8
RP		 2688 * The idea here must be to scan in a set of registers but I don't
2689 * understand it. Looks awfully sloppy to me but I don't have any doc on
2690 * this format so...
6d27d3a2
KR		 2691
2692 *
7c15cbe8
RP		 2693 *
2694 */
fecd2382
RP		 2695
2696static int get_regs(i,str,opP)
f8701a3f
SC		 2697int i;
2698struct m68k_op *opP;
2699char *str;
fecd2382 2700{
f8701a3f
SC		 2701 /* 26, 25, 24, 23-16, 15-8, 0-7 */
2702 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
2703 unsigned long cur_regs = 0;
2704 int reg1,
2705 reg2;
6d27d3a2 2706
fecd2382 2707#define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
a39116f1
RP		 2708else if(x==FPS) cur_regs|=(1<<25);\
2709else if(x==FPC) cur_regs|=(1<<26);\
2710else cur_regs|=(1<<(x-1)); }
6d27d3a2 2711
f8701a3f
SC		 2712 reg1=i;
2713 for(;;) {
2714 if(*str=='/') {
2715 ADD_REG(reg1);
2716 str++;
2717 } else if(*str=='-') {
2718 str++;
2719 reg2=m68k_reg_parse(&str);
2720 if(reg2<DATA || reg2>=FPREG+8 || reg1==FPI || reg1==FPS || reg1==FPC) {
2721 opP->error="unknown register in register list";
2722 return FAIL;
2723 }
2724 while(reg1<=reg2) {
2725 ADD_REG(reg1);
2726 reg1++;
2727 }
2728 if(*str=='\0')
2729 break;
2730 } else if(*str=='\0') {
2731 ADD_REG(reg1);
2732 break;
2733 } else {
2734 opP->error="unknow character in register list";
2735 return FAIL;
2736 }
2737 /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
2738 if (*str=='/')
2739 str ++;
2740 reg1=m68k_reg_parse(&str);
2741 if((reg1<DATA || reg1>=FPREG+8) && !(reg1==FPI || reg1==FPS || reg1==FPC)) {
2742 opP->error="unknown register in register list";
2743 return FAIL;
2744 }
a39116f1 2745 }
f8701a3f
SC		 2746 opP->reg=cur_regs;
2747 return OK;
fecd2382
RP		 2748} /* get_regs() */
2749
2750static int reverse_16_bits(in)
f8701a3f 2751int in;
fecd2382 2752{
f8701a3f
SC		 2753 int out=0;
2754 int n;
6d27d3a2 2755
f8701a3f
SC		 2756 static int mask[16] = {
2757 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,
2758 0x0100,0x0200,0x0400,0x0800,0x1000,0x2000,0x4000,0x8000
2759 };
2760 for(n=0;n<16;n++) {
2761 if(in&mask[n])
2762 out|=mask[15-n];
2763 }
2764 return out;
fecd2382
RP		 2765} /* reverse_16_bits() */
2766
2767static int reverse_8_bits(in)
f8701a3f 2768int in;
fecd2382 2769{
f8701a3f
SC		 2770 int out=0;
2771 int n;
6d27d3a2 2772
f8701a3f
SC		 2773 static int mask[8] = {
2774 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,
2775 };
6d27d3a2 2776
f8701a3f
SC		 2777 for(n=0;n<8;n++) {
2778 if(in&mask[n])
2779 out|=mask[7-n];
2780 }
2781 return out;
fecd2382
RP		 2782} /* reverse_8_bits() */
2783
2784static void install_operand(mode,val)
f8701a3f
SC		 2785int mode;
2786int val;
fecd2382 2787{
f8701a3f
SC		 2788 switch(mode) {
2789 case 's':
2790 the_ins.opcode[0]|=val & 0xFF; /* JF FF is for M kludge */
2791 break;
2792 case 'd':
2793 the_ins.opcode[0]|=val<<9;
2794 break;
2795 case '1':
2796 the_ins.opcode[1]|=val<<12;
2797 break;
2798 case '2':
2799 the_ins.opcode[1]|=val<<6;
2800 break;
2801 case '3':
2802 the_ins.opcode[1]|=val;
2803 break;
2804 case '4':
2805 the_ins.opcode[2]|=val<<12;
2806 break;
2807 case '5':
2808 the_ins.opcode[2]|=val<<6;
2809 break;
2810 case '6':
2811 /* DANGER! This is a hack to force cas2l and cas2w cmds
2812 to be three words long! */
2813 the_ins.numo++;
2814 the_ins.opcode[2]|=val;
2815 break;
2816 case '7':
2817 the_ins.opcode[1]|=val<<7;
2818 break;
2819 case '8':
2820 the_ins.opcode[1]|=val<<10;
2821 break;
2822#ifndef NO_68851
2823 case '9':
2824 the_ins.opcode[1]|=val<<5;
2825 break;
2826#endif
6d27d3a2 2827
f8701a3f
SC		 2828 case 't':
2829 the_ins.opcode[1]|=(val<<10)|(val<<7);
2830 break;
2831 case 'D':
2832 the_ins.opcode[1]|=(val<<12)|val;
2833 break;
2834 case 'g':
2835 the_ins.opcode[0]|=val=0xff;
2836 break;
2837 case 'i':
2838 the_ins.opcode[0]|=val<<9;
2839 break;
2840 case 'C':
2841 the_ins.opcode[1]|=val;
2842 break;
2843 case 'j':
2844 the_ins.opcode[1]|=val;
2845 the_ins.numo++; /* What a hack */
2846 break;
2847 case 'k':
2848 the_ins.opcode[1]|=val<<4;
2849 break;
2850 case 'b':
2851 case 'w':
2852 case 'l':
2853 break;
2854 case 'e':
2855 the_ins.opcode[0] |= (val << 6);
2856 break;
2857 case 'L':
2858 the_ins.opcode[1] = (val >> 16);
2859 the_ins.opcode[2] = val & 0xffff;
2860 break;
2861 case 'c':
2862 default:
2863 as_fatal("failed sanity check.");
2864 }
fecd2382
RP		 2865} /* install_operand() */
2866
2867static void install_gen_operand(mode,val)
f8701a3f
SC		 2868int mode;
2869int val;
fecd2382 2870{
f8701a3f
SC		 2871 switch(mode) {
2872 case 's':
2873 the_ins.opcode[0]|=val;
2874 break;
2875 case 'd':
2876 /* This is a kludge!!! */
2877 the_ins.opcode[0]|=(val&0x07)<<9|(val&0x38)<<3;
2878 break;
2879 case 'b':
2880 case 'w':
2881 case 'l':
2882 case 'f':
2883 case 'F':
2884 case 'x':
2885 case 'p':
2886 the_ins.opcode[0]|=val;
2887 break;
2888 /* more stuff goes here */
2889 default:
2890 as_fatal("failed sanity check.");
2891 }
fecd2382
RP		 2892} /* install_gen_operand() */
2893
7c15cbe8
RP		 2894/*
2895 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2896 * then deal with the bitfield hack.
2897 */
2898
fecd2382 2899static char *crack_operand(str,opP)
f8701a3f
SC		 2900register char *str;
2901register struct m68k_op *opP;
fecd2382 2902{
f8701a3f
SC		 2903 register int parens;
2904 register int c;
2905 register char *beg_str;
6d27d3a2 2906
f8701a3f
SC		 2907 if(!str) {
2908 return str;
2909 }
2910 beg_str=str;
2911 for(parens=0;*str && (parens>0 || notend(str));str++) {
2912 if(*str=='(') parens++;
2913 else if(*str==')') {
2914 if(!parens) { /* ERROR */
2915 opP->error="Extra )";
2916 return str;
2917 }
2918 --parens;
2919 }
2920 }
2921 if(!*str && parens) { /* ERROR */
2922 opP->error="Missing )";
2923 return str;
2924 }
2925 c= *str;
2926 *str='\0';
2927 if(m68k_ip_op(beg_str,opP)==FAIL) {
2928 *str=c;
fecd2382
RP		 2929 return str;
2930 }
2931 *str=c;
f8701a3f
SC		 2932 if(c=='}')
2933 c= *++str; /* JF bitfield hack */
2934 if(c) {
2935 c= *++str;
2936 if(!c)
2937 as_bad("Missing operand");
2938 }
fecd2382
RP		 2939 return str;
2940}
2941
2942/* See the comment up above where the #define notend(... is */
2943#if 0
2944notend(s)
f8701a3f 2945char *s;
fecd2382 2946{
f8701a3f
SC		 2947 if(*s==',') return 0;
2948 if(*s=='{' || *s=='}')
2949 return 0;
2950 if(*s!=':') return 1;
2951 /* This kludge here is for the division cmd, which is a kludge */
2952 if(index("aAdD#",s[1])) return 0;
2953 return 1;
fecd2382
RP		 2954}
2955#endif
2956
2957/* This is the guts of the machine-dependent assembler. STR points to a
7c15cbe8 2958 machine dependent instruction. This function is supposed to emit
fecd2382 2959 the frags/bytes it assembles to.
a39116f1 2960 */
a933d598
SC		 2961
2962void
2963insert_reg(regname, regnum)
2964char *regname;
2965int regnum;
2966{
2967 char buf[100];
2968 int i;
2969 symbol_table_insert(symbol_new(regname, SEG_REGISTER, regnum, &zero_address_frag));
2970
2971 for (i = 0; regname[i]; i++)
2972 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2973 buf[i] = '\0';
6d27d3a2 2974
a933d598
SC		 2975 symbol_table_insert(symbol_new(buf, SEG_REGISTER, regnum, &zero_address_frag));
2976}
2977
4134a793 2978static const struct {
6d27d3a2 2979char *name;
a933d598 2980int number;
4134a793 2981} init_table[] = {
a933d598
SC		 2982 "d0", DATA0,
2983 "d1", DATA1,
2984 "d2", DATA2,
2985 "d3", DATA3,
2986 "d4", DATA4,
2987 "d5", DATA5,
2988 "d6", DATA6,
2989 "d7", DATA7,
2990 "a0", ADDR0,
2991 "a1", ADDR1,
2992 "a2", ADDR2,
2993 "a3", ADDR3,
2994 "a4", ADDR4,
2995 "a5", ADDR5,
2996 "a6", ADDR6,
2997 "fp", ADDR6,
2998 "a7", ADDR7,
2999 "sp", ADDR7,
3000 "fp0", FP0,
3001 "fp1", FP1,
3002 "fp2", FP2,
3003 "fp3", FP3,
3004 "fp4", FP4,
3005 "fp5", FP5,
3006 "fp6", FP6,
3007 "fp7", FP7,
3008 "fpi", FPI,
3009 "fpiar", FPI,
3010 "fpc", FPI,
3011 "fps", FPS,
3012 "fpsr", FPS,
3013 "fpc", FPC,
3014 "fpcr", FPC,
3015
3016 "cop0", COP0,
3017 "cop1", COP1,
3018 "cop2", COP2,
3019 "cop3", COP3,
3020 "cop4", COP4,
3021 "cop5", COP5,
3022 "cop6", COP6,
3023 "cop7", COP7,
6d27d3a2
KR		 3024 "pc", PC,
3025 "zpc", ZPC,
3026 "sr", SR,
a933d598 3027
6d27d3a2
KR		 3028 "ccr", CCR,
3029 "cc", CCR,
a933d598 3030
6d27d3a2
KR		 3031 "usp", USP,
3032 "isp", ISP,
a933d598
SC		 3033 "sfc", SFC,
3034 "dfc", DFC,
3035 "cacr", CACR,
3036 "caar", CAAR,
3037
3038 "vbr", VBR,
3039
3040 "msp", MSP,
3041 "itt0", ITT0,
3042 "itt1", ITT1,
3043 "dtt0", DTT0,
3044 "dtt1", DTT1,
3045 "mmusr", MMUSR,
3046 "tc", TC,
3047 "srp", SRP,
3048 "urp", URP,
3049
a933d598
SC		 3050 "ac", AC,
3051 "bc", BC,
3052 "cal", CAL,
3053 "crp", CRP,
3054 "drp", DRP,
3055 "pcsr", PCSR,
3056 "psr", PSR,
3057 "scc", SCC,
3058 "val", VAL,
3059 "bad0", BAD0,
3060 "bad1", BAD1,
3061 "bad2", BAD2,
3062 "bad3", BAD3,
3063 "bad4", BAD4,
3064 "bad5", BAD5,
3065 "bad6", BAD6,
3066 "bad7", BAD7,
3067 "bac0", BAC0,
3068 "bac1", BAC1,
3069 "bac2", BAC2,
3070 "bac3", BAC3,
3071 "bac4", BAC4,
3072 "bac5", BAC5,
3073 "bac6", BAC6,
3074 "bac7", BAC7,
a933d598
SC		 3075
3076 "ic", IC,
3077 "dc", DC,
3078 "nc", NC,
3079
4134a793
KR		 3080 "tt0", TT0,
3081 "tt1", TT1,
3082 /* 68ec030 versions of same */
3083 "ac0", TT0,
3084 "ac1", TT1,
3085 /* 68ec030 access control unit, identical to 030 MMU status reg */
3086 "acusr", PSR,
3087
a933d598
SC		 3088 0,
3089
3090};
3091
3092
3093void
3094init_regtable()
3095{
3096 int i;
6d27d3a2 3097 for (i = 0; init_table[i].name; i++)
a933d598 3098 insert_reg(init_table[i].name, init_table[i].number);
a933d598 3099}
6d27d3a2 3100
df3768fb 3101static int no_68851, no_68881;
a933d598 3102
fecd2382 3103void
6d27d3a2
KR		 3104md_assemble(str)
3105 char *str;
fecd2382 3106{
f8701a3f
SC		 3107 char *er;
3108 short *fromP;
3109 char *toP = NULL;
3110 int m,n = 0;
3111 char *to_beg_P;
3112 int shorts_this_frag;
4134a793 3113 static int done_first_time;
6d27d3a2 3114
4134a793 3115 if (!done_first_time)
148eb5dd 3116 {
4134a793
KR		 3117 done_first_time = 1;
3118
3119 if (cpu_of_arch (current_architecture) == 0)
3120 {
df3768fb 3121 int cpu_type;
148eb5dd
ILT		 3122
3123#ifndef TARGET_CPU
4134a793 3124 cpu_type = m68020;
148eb5dd 3125#else
4134a793
KR		 3126 if (strcmp (TARGET_CPU, "m68000") == 0)
3127 cpu_type = m68000;
3128 else if (strcmp (TARGET_CPU, "m68010") == 0)
3129 cpu_type = m68010;
3130 else if (strcmp (TARGET_CPU, "m68020") == 0
3131 || strcmp (TARGET_CPU, "m68k") == 0)
3132 cpu_type = m68020;
3133 else if (strcmp (TARGET_CPU, "m68030") == 0)
3134 cpu_type = m68030;
3135 else if (strcmp (TARGET_CPU, "m68040") == 0)
3136 cpu_type = m68040;
df3768fb
KR		 3137 else if (strcmp (TARGET_CPU, "cpu32") == 0)
3138 cpu_type = cpu32;
4134a793
KR		 3139 else
3140 cpu_type = m68020;
148eb5dd
ILT		 3141#endif
3142
df3768fb 3143 current_architecture |= cpu_type;
4134a793 3144 }
df3768fb
KR		 3145 if (current_architecture & m68881)
3146 {
3147 if (current_architecture & m68000)
3148 as_bad ("incompatible processors 68000 and 68881/2 specified");
3149 if (current_architecture & m68010)
3150 as_bad ("incompatible processors 68010 and 68881/2 specified");
3151 if (current_architecture & m68040)
3152 as_bad ("incompatible processors 68040 and 68881/2 specified");
3153 }
3154 /* What other incompatibilities ought we to check for? */
3155
3156 /* Toss in some default assumptions about coprocessors. */
3157 if (!no_68881
3158 && (cpu_of_arch (current_architecture)
3159 /* Can CPU32 have a 68881 coprocessor?? */
3160 & (m68020 | m68030 | cpu32)))
4134a793 3161 {
df3768fb 3162 current_architecture |= m68881;
148eb5dd 3163 }
df3768fb
KR		 3164 if (!no_68851
3165 && (cpu_of_arch (current_architecture) & m68020up) != 0)
3166 {
3167 current_architecture |= m68851;
3168 }
3169 if (no_68881 && (current_architecture & m68881))
3170 as_bad ("options for 68881 and no-68881 both given");
3171 if (no_68851 && (current_architecture & m68851))
3172 as_bad ("options for 68851 and no-68851 both given");
4134a793 3173 done_first_time = 1;
148eb5dd 3174 }
6d27d3a2 3175
f8701a3f
SC		 3176 memset((char *)(&the_ins), '\0', sizeof(the_ins)); /* JF for paranoia sake */
3177 m68k_ip(str);
3178 er=the_ins.error;
3179 if(!er) {
3180 for(n=the_ins.numargs;n;--n)
3181 if(the_ins.operands[n].error) {
3182 er=the_ins.operands[n].error;
3183 break;
3184 }
fecd2382 3185 }
f8701a3f 3186 if(er) {
6d27d3a2 3187 as_bad("%s -- statement `%s' ignored",er,str);
f8701a3f 3188 return;
fecd2382 3189 }
6d27d3a2 3190
f8701a3f
SC		 3191 if(the_ins.nfrag==0) { /* No frag hacking involved; just put it out */
3192 toP=frag_more(2*the_ins.numo);
3193 fromP= &the_ins.opcode[0];
3194 for(m=the_ins.numo;m;--m) {
3195 md_number_to_chars(toP,(long)(*fromP),2);
3196 toP+=2;
3197 fromP++;
3198 }
3199 /* put out symbol-dependent info */
3200 for(m=0;m<the_ins.nrel;m++) {
3201 switch(the_ins.reloc[m].wid) {
3202 case 'B':
3203 n=1;
3204 break;
3205 case 'b':
3206 n=1;
3207 break;
3208 case '3':
3209 n=2;
3210 break;
3211 case 'w':
3212 n=2;
3213 break;
3214 case 'l':
3215 n=4;
3216 break;
3217 default:
3218 as_fatal("Don't know how to figure width of %c in md_assemble()",the_ins.reloc[m].wid);
3219 }
6d27d3a2 3220
f8701a3f
SC		 3221 fix_new(frag_now,
3222 (toP-frag_now->fr_literal)-the_ins.numo*2+the_ins.reloc[m].n,
3223 n,
3224 the_ins.reloc[m].add,
3225 the_ins.reloc[m].sub,
3226 the_ins.reloc[m].off,
3227 the_ins.reloc[m].pcrel,
3228 NO_RELOC);
3229 }
3230 return;
3231 }
6d27d3a2 3232
f8701a3f
SC		 3233 /* There's some frag hacking */
3234 for(n=0,fromP= &the_ins.opcode[0];n<the_ins.nfrag;n++) {
3235 int wid;
6d27d3a2 3236
f8701a3f
SC		 3237 if(n==0) wid=2*the_ins.fragb[n].fragoff;
3238 else wid=2*(the_ins.numo-the_ins.fragb[n-1].fragoff);
3239 toP=frag_more(wid);
3240 to_beg_P=toP;
3241 shorts_this_frag=0;
3242 for(m=wid/2;m;--m) {
3243 md_number_to_chars(toP,(long)(*fromP),2);
3244 toP+=2;
3245 fromP++;
3246 shorts_this_frag++;
3247 }
3248 for(m=0;m<the_ins.nrel;m++) {
3249 if((the_ins.reloc[m].n)>= 2*shorts_this_frag /* 2*the_ins.fragb[n].fragoff */) {
3250 the_ins.reloc[m].n-= 2*shorts_this_frag /* 2*the_ins.fragb[n].fragoff */;
3251 break;
3252 }
3253 wid=the_ins.reloc[m].wid;
3254 if(wid==0)
3255 continue;
3256 the_ins.reloc[m].wid=0;
3257 wid = (wid=='b') ? 1 : (wid=='w') ? 2 : (wid=='l') ? 4 : 4000;
6d27d3a2 3258
f8701a3f
SC		 3259 fix_new(frag_now,
3260 (toP-frag_now->fr_literal)-the_ins.numo*2+the_ins.reloc[m].n,
3261 wid,
3262 the_ins.reloc[m].add,
3263 the_ins.reloc[m].sub,
3264 the_ins.reloc[m].off,
3265 the_ins.reloc[m].pcrel,
3266 NO_RELOC);
3267 }
3268 /* know(the_ins.fragb[n].fadd); */
3269 (void)frag_var(rs_machine_dependent,10,0,(relax_substateT)(the_ins.fragb[n].fragty),
3270 the_ins.fragb[n].fadd,the_ins.fragb[n].foff,to_beg_P);
3271 }
3272 n=(the_ins.numo-the_ins.fragb[n-1].fragoff);
fecd2382 3273 shorts_this_frag=0;
f8701a3f
SC		 3274 if(n) {
3275 toP=frag_more(n*sizeof(short));
3276 while(n--) {
3277 md_number_to_chars(toP,(long)(*fromP),2);
3278 toP+=2;
3279 fromP++;
3280 shorts_this_frag++;
3281 }
fecd2382
RP		 3282 }
3283 for(m=0;m<the_ins.nrel;m++) {
f8701a3f 3284 int wid;
6d27d3a2 3285
f8701a3f
SC		 3286 wid=the_ins.reloc[m].wid;
3287 if(wid==0)
3288 continue;
3289 the_ins.reloc[m].wid=0;
3290 wid = (wid=='b') ? 1 : (wid=='w') ? 2 : (wid=='l') ? 4 : 4000;
6d27d3a2 3291
f8701a3f
SC		 3292 fix_new(frag_now,
3293 (the_ins.reloc[m].n + toP-frag_now->fr_literal)-/* the_ins.numo */ shorts_this_frag*2,
3294 wid,
3295 the_ins.reloc[m].add,
3296 the_ins.reloc[m].sub,
3297 the_ins.reloc[m].off,
3298 the_ins.reloc[m].pcrel,
3299 NO_RELOC);
fecd2382
RP		 3300 }
3301}
3302
f8701a3f 3303
f8701a3f 3304
fecd2382 3305void
a39116f1 3306 md_begin()
fecd2382 3307{
f8701a3f
SC		 3308 /*
3309 * md_begin -- set up hash tables with 68000 instructions.
3310 * similar to what the vax assembler does. ---phr
3311 */
3312 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3313 a copy of it at runtime, adding in the information we want but isn't
3314 there. I think it'd be better to have an awk script hack the table
3315 at compile time. Or even just xstr the table and use it as-is. But
3316 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3317 names. */
6d27d3a2 3318
f8701a3f
SC		 3319 register const struct m68k_opcode *ins;
3320 register struct m68k_incant *hack,
3321 *slak;
3322 register char *retval = 0; /* empty string, or error msg text */
3323 register unsigned int i;
3324 register char c;
6d27d3a2 3325
f8701a3f
SC		 3326 if ((op_hash = hash_new()) == NULL)
3327 as_fatal("Virtual memory exhausted");
6d27d3a2 3328
f8701a3f
SC		 3329 obstack_begin(&robyn,4000);
3330 for (ins = m68k_opcodes; ins < endop; ins++) {
3331 hack=slak=(struct m68k_incant *)obstack_alloc(&robyn,sizeof(struct m68k_incant));
3332 do {
3333 /* we *could* ignore insns that don't match our
3334 arch here but just leaving them out of the
3335 hash. */
3336 slak->m_operands=ins->args;
3337 slak->m_opnum=strlen(slak->m_operands)/2;
3338 slak->m_arch = ins->arch;
3339 slak->m_opcode=ins->opcode;
3340 /* This is kludgey */
3341 slak->m_codenum=((ins->match)&0xffffL) ? 2 : 1;
3342 if((ins+1)!=endop && !strcmp(ins->name,(ins+1)->name)) {
3343 slak->m_next=(struct m68k_incant *) obstack_alloc(&robyn,sizeof(struct m68k_incant));
3344 ins++;
3345 } else
3346 slak->m_next=0;
3347 slak=slak->m_next;
3348 } while(slak);
6d27d3a2 3349
f8701a3f
SC		 3350 retval = hash_insert (op_hash, ins->name,(char *)hack);
3351 /* Didn't his mommy tell him about null pointers? */
3352 if(retval && *retval)
3ad9ec6a 3353 as_bad("Internal Error: Can't hash %s: %s",ins->name,retval);
f8701a3f 3354 }
6d27d3a2 3355
f8701a3f
SC		 3356 for (i = 0; i < sizeof(mklower_table) ; i++)
3357 mklower_table[i] = (isupper(c = (char) i)) ? tolower(c) : c;
6d27d3a2 3358
f8701a3f
SC		 3359 for (i = 0 ; i < sizeof(notend_table) ; i++) {
3360 notend_table[i] = 0;
3361 alt_notend_table[i] = 0;
3362 }
3363 notend_table[','] = 1;
3364 notend_table['{'] = 1;
3365 notend_table['}'] = 1;
3366 alt_notend_table['a'] = 1;
3367 alt_notend_table['A'] = 1;
3368 alt_notend_table['d'] = 1;
3369 alt_notend_table['D'] = 1;
3370 alt_notend_table['#'] = 1;
3371 alt_notend_table['f'] = 1;
3372 alt_notend_table['F'] = 1;
fecd2382 3373#ifdef REGISTER_PREFIX
f8701a3f 3374 alt_notend_table[REGISTER_PREFIX] = 1;
fecd2382 3375#endif
f8701a3f 3376
3ad9ec6a
ILT		 3377#ifndef MIT_SYNTAX_ONLY
3378 /* Insert pseudo ops, these have to go into the opcode table since
3379 gas expects pseudo ops to start with a dot */
3380 {
3381 int n = 0;
3382 while (mote_pseudo_table[n].poc_name)
3383 {
3384 hack=(struct m68k_incant *)
3385 obstack_alloc(&robyn,sizeof(struct m68k_incant));
3386 hash_insert(op_hash,
3387 mote_pseudo_table[n].poc_name, (char *)hack);
3388 hack->m_operands = 0;
3389 hack->m_opnum = n;
3390 n++;
3391 }
3392 }
3393#endif
3394
f8701a3f 3395 init_regtable();
fecd2382
RP		 3396}
3397
3398#if 0
3399#define notend(s) ((*s == ',' || *s == '}' || *s == '{' \
a39116f1
RP		 3400 || (*s == ':' && strchr("aAdD#", s[1]))) \
3401 ? 0 : 1)
fecd2382
RP		 3402#endif
3403
3404/* This funciton is called once, before the assembler exits. It is
3405 supposed to do any final cleanup for this part of the assembler.
a39116f1 3406 */
fecd2382 3407void
a39116f1 3408 md_end()
fecd2382
RP		 3409{
3410}
3411
3412/* Equal to MAX_PRECISION in atof-ieee.c */
3413#define MAX_LITTLENUMS 6
3414
3415/* Turn a string in input_line_pointer into a floating point constant of type
3416 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
3417 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
a39116f1 3418 */
fecd2382 3419char *
a39116f1 3420 md_atof(type,litP,sizeP)
fecd2382
RP		 3421char type;
3422char *litP;
3423int *sizeP;
3424{
f8701a3f
SC		 3425 int prec;
3426 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3427 LITTLENUM_TYPE *wordP;
3428 char *t;
3429 char *atof_ieee();
6d27d3a2 3430
f8701a3f
SC		 3431 switch(type) {
3432 case 'f':
3433 case 'F':
3434 case 's':
3435 case 'S':
3436 prec = 2;
3437 break;
6d27d3a2 3438
f8701a3f
SC		 3439 case 'd':
3440 case 'D':
3441 case 'r':
3442 case 'R':
3443 prec = 4;
3444 break;
6d27d3a2 3445
f8701a3f
SC		 3446 case 'x':
3447 case 'X':
3448 prec = 6;
3449 break;
6d27d3a2 3450
f8701a3f
SC		 3451 case 'p':
3452 case 'P':
3453 prec = 6;
3454 break;
6d27d3a2 3455
f8701a3f
SC		 3456 default:
3457 *sizeP=0;
3458 return "Bad call to MD_ATOF()";
3459 }
3460 t=atof_ieee(input_line_pointer,type,words);
3461 if(t)
3462 input_line_pointer=t;
6d27d3a2 3463
f8701a3f
SC		 3464 *sizeP=prec * sizeof(LITTLENUM_TYPE);
3465 for(wordP=words;prec--;) {
3466 md_number_to_chars(litP,(long)(*wordP++),sizeof(LITTLENUM_TYPE));
3467 litP+=sizeof(LITTLENUM_TYPE);
3468 }
3469 return ""; /* Someone should teach Dean about null pointers */
fecd2382
RP		 3470}
3471
3472/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
3473 for use in the a.out file, and stores them in the array pointed to by buf.
3474 This knows about the endian-ness of the target machine and does
3475 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
3476 2 (short) and 4 (long) Floating numbers are put out as a series of
3477 LITTLENUMS (shorts, here at least)
a39116f1 3478 */
fecd2382 3479void
a39116f1 3480 md_number_to_chars(buf,val,n)
fecd2382
RP		 3481char *buf;
3482long val;
3483int n;
3484{
f8701a3f
SC		 3485 switch(n) {
3486 case 1:
3487 *buf++=val;
3488 break;
3489 case 2:
3490 *buf++=(val>>8);
3491 *buf++=val;
3492 break;
3493 case 4:
3494 *buf++=(val>>24);
3495 *buf++=(val>>16);
3496 *buf++=(val>>8);
3497 *buf++=val;
3498 break;
3499 default:
3500 as_fatal("failed sanity check.");
3501 }
fecd2382
RP		 3502}
3503
3504void
a39116f1
RP		 3505 md_apply_fix(fixP, val)
3506fixS *fixP;
3507long val;
fecd2382 3508{
587c4264
ILT		 3509#ifdef IBM_COMPILER_SUX
3510 /* This is unnecessary but it convinces the native rs6000
3511 compiler to generate the code we want. */
3512 char *buf = fixP->fx_frag->fr_literal;
3513 buf += fixP->fx_where;
3514#else /* IBM_COMPILER_SUX */
f8701a3f 3515 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
587c4264 3516#endif /* IBM_COMPILER_SUX */
6d27d3a2 3517
f8701a3f
SC		 3518 switch(fixP->fx_size) {
3519 case 1:
3520 *buf++=val;
3521 break;
3522 case 2:
3523 *buf++=(val>>8);
3524 *buf++=val;
3525 break;
3526 case 4:
3527 *buf++=(val>>24);
3528 *buf++=(val>>16);
3529 *buf++=(val>>8);
3530 *buf++=val;
3531 break;
3532 default:
3533 BAD_CASE (fixP->fx_size);
3534 }
fecd2382
RP		 3535}
3536
3537
3538/* *fragP has been relaxed to its final size, and now needs to have
3539 the bytes inside it modified to conform to the new size There is UGLY
3540 MAGIC here. ..
a39116f1 3541 */
fecd2382 3542void
a39116f1 3543 md_convert_frag(headers, fragP)
f6e504fe 3544object_headers *headers;
fecd2382
RP		 3545register fragS *fragP;
3546{
f8701a3f
SC		 3547 long disp;
3548 long ext = 0;
6d27d3a2 3549
f8701a3f
SC		 3550 /* Address in object code of the displacement. */
3551 register int object_address = fragP -> fr_fix + fragP -> fr_address;
6d27d3a2 3552
f6e504fe 3553#ifdef IBM_COMPILER_SUX
f8701a3f
SC		 3554 /* This is wrong but it convinces the native rs6000 compiler to
3555 generate the code we want. */
3556 register char *buffer_address = fragP -> fr_literal;
3557 buffer_address += fragP -> fr_fix;
f6e504fe 3558#else /* IBM_COMPILER_SUX */
f8701a3f
SC		 3559 /* Address in gas core of the place to store the displacement. */
3560 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
f6e504fe 3561#endif /* IBM_COMPILER_SUX */
6d27d3a2 3562
f8701a3f 3563 /* No longer true: know(fragP->fr_symbol); */
6d27d3a2 3564
f8701a3f
SC		 3565 /* The displacement of the address, from current location. */
3566 disp = fragP->fr_symbol ? S_GET_VALUE(fragP->fr_symbol) : 0;
3567 disp = (disp + fragP->fr_offset) - object_address;
6d27d3a2 3568
f8701a3f
SC		 3569 switch(fragP->fr_subtype) {
3570 case TAB(BCC68000,BYTE):
3ad9ec6a 3571 case TAB(ABRANCH,BYTE):
a39116f1
RP		 3572 know(issbyte(disp));
3573 if(disp==0)
3574 as_bad("short branch with zero offset: use :w");
3575 fragP->fr_opcode[1]=disp;
fecd2382 3576 ext=0;
a39116f1 3577 break;
f8701a3f
SC		 3578 case TAB(DBCC,SHORT):
3579 know(issword(disp));
a39116f1
RP		 3580 ext=2;
3581 break;
f8701a3f 3582 case TAB(BCC68000,SHORT):
3ad9ec6a 3583 case TAB(ABRANCH,SHORT):
f8701a3f 3584 know(issword(disp));
a39116f1
RP		 3585 fragP->fr_opcode[1]=0x00;
3586 ext=2;
3587 break;
3ad9ec6a 3588 case TAB(ABRANCH,LONG):
f8701a3f
SC		 3589 if (cpu_of_arch(current_architecture) < m68020) {
3590 if (fragP->fr_opcode[0]==0x61) {
3591 fragP->fr_opcode[0]= 0x4E;
3592 fragP->fr_opcode[1]= 0xB9; /* JBSR with ABSL LONG offset */
3593 subseg_change(SEG_TEXT, 0);
6d27d3a2 3594
f8701a3f
SC		 3595 fix_new(fragP,
3596 fragP->fr_fix,
3597 4,
3598 fragP->fr_symbol,
3599 0,
3600 fragP->fr_offset,
3601 0,
3602 NO_RELOC);
6d27d3a2 3603
f8701a3f
SC		 3604 fragP->fr_fix+=4;
3605 ext=0;
3606 } else if (fragP->fr_opcode[0]==0x60) {
3607 fragP->fr_opcode[0]= 0x4E;
3608 fragP->fr_opcode[1]= 0xF9; /* JMP with ABSL LONG offset */
3609 subseg_change(SEG_TEXT, 0);
3610 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset,0,
3611 NO_RELOC);
3612 fragP->fr_fix+=4;
3613 ext=0;
3614 } else {
3615 as_bad("Long branch offset not supported.");
3616 }
3617 } else {
3618 fragP->fr_opcode[1]=0xff;
3619 ext=4;
3620 }
3621 break;
3622 case TAB(BCC68000,LONG):
3623 /* only Bcc 68000 instructions can come here */
3624 /* change bcc into b!cc/jmp absl long */
3625 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
fecd2382 3626 fragP->fr_opcode[1] = 0x6; /* branch offset = 6 */
6d27d3a2 3627
fecd2382
RP		 3628 /* JF: these used to be fr_opcode[2,3], but they may be in a
3629 different frag, in which case refering to them is a no-no.
3630 Only fr_opcode[0,1] are guaranteed to work. */
6d27d3a2
KR		 3631 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3632 *buffer_address++ = 0xf9;
fecd2382
RP		 3633 fragP->fr_fix += 2; /* account for jmp instruction */
3634 subseg_change(SEG_TEXT,0);
6d27d3a2 3635 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
a39116f1
RP		 3636 fragP->fr_offset,0,
3637 NO_RELOC);
fecd2382
RP		 3638 fragP->fr_fix += 4;
3639 ext=0;
3640 break;
f8701a3f
SC		 3641 case TAB(DBCC,LONG):
3642 /* only DBcc 68000 instructions can come here */
3643 /* change dbcc into dbcc/jmp absl long */
3644 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3645 *buffer_address++ = 0x00; /* branch offset = 4 */
6d27d3a2
KR		 3646 *buffer_address++ = 0x04;
3647 *buffer_address++ = 0x60; /* put in bra pc+6 */
3648 *buffer_address++ = 0x06;
3649 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3650 *buffer_address++ = 0xf9;
3651
fecd2382
RP		 3652 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3653 subseg_change(SEG_TEXT,0);
6d27d3a2 3654 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
a39116f1
RP		 3655 fragP->fr_offset,0,
3656 NO_RELOC);
fecd2382
RP		 3657 fragP->fr_fix += 4;
3658 ext=0;
a39116f1 3659 break;
f8701a3f
SC		 3660 case TAB(FBRANCH,SHORT):
3661 know((fragP->fr_opcode[1]&0x40)==0);
a39116f1
RP		 3662 ext=2;
3663 break;
f8701a3f
SC		 3664 case TAB(FBRANCH,LONG):
3665 fragP->fr_opcode[1]|=0x40; /* Turn on LONG bit */
a39116f1
RP		 3666 ext=4;
3667 break;
f8701a3f
SC		 3668 case TAB(PCREL,SHORT):
3669 ext=2;
a39116f1 3670 break;
f8701a3f
SC		 3671 case TAB(PCREL,LONG):
3672 /* The thing to do here is force it to ABSOLUTE LONG, since
3673 PCREL is really trying to shorten an ABSOLUTE address anyway */
3674 /* JF FOO This code has not been tested */
3675 subseg_change(SEG_TEXT,0);
a39116f1
RP		 3676 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3677 if((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3678 as_bad("Internal error (long PC-relative operand) for insn 0x%04lx at 0x%lx",
3679 fragP->fr_opcode[0],fragP->fr_address);
3680 fragP->fr_opcode[1]&= ~0x3F;
3681 fragP->fr_opcode[1]|=0x39; /* Mode 7.1 */
3682 fragP->fr_fix+=4;
3683 /* md_number_to_chars(buffer_address,
3684 (long)(fragP->fr_symbol->sy_value + fragP->fr_offset),
3685 4); */
3686 ext=0;
3687 break;
f8701a3f
SC		 3688 case TAB(PCLEA,SHORT):
3689 subseg_change(SEG_TEXT,0);
a39116f1
RP		 3690 fix_new(fragP,(int)(fragP->fr_fix),2,fragP->fr_symbol,(symbolS *)0,fragP->fr_offset,1,
3691 NO_RELOC);
3692 fragP->fr_opcode[1] &= ~0x3F;
3693 fragP->fr_opcode[1] |= 0x3A;
3694 ext=2;
3695 break;
f8701a3f
SC		 3696 case TAB(PCLEA,LONG):
3697 subseg_change(SEG_TEXT,0);
3698 fix_new(fragP,(int)(fragP->fr_fix)+2,4,fragP->fr_symbol,(symbolS *)0,fragP->fr_offset+2,1,
3699 NO_RELOC);
3700 *buffer_address++ = 0x01;
3701 *buffer_address++ = 0x70;
3702 fragP->fr_fix+=2;
3703 /* buffer_address+=2; */
3704 ext=4;
a39116f1 3705 break;
6d27d3a2 3706
f8701a3f 3707} /* switch on subtype */
6d27d3a2 3708
f8701a3f
SC		 3709 if (ext) {
3710 md_number_to_chars(buffer_address, (long) disp, (int) ext);
3711 fragP->fr_fix += ext;
3712 /* H_SET_TEXT_SIZE(headers, H_GET_TEXT_SIZE(headers) + ext); */
3713 } /* if extending */
6d27d3a2 3714
f8701a3f
SC		 3715 return;
3716} /* md_convert_frag() */
3717
3718/* Force truly undefined symbols to their maximum size, and generally set up
3719 the frag list to be relaxed
3720 */
3721int md_estimate_size_before_relax(fragP, segment)
3722register fragS *fragP;
3723segT segment;
3724{
3725 int old_fix;
3726 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
6d27d3a2 3727
f8701a3f 3728 old_fix = fragP->fr_fix;
6d27d3a2 3729
f8701a3f
SC		 3730 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3731 switch (fragP->fr_subtype) {
6d27d3a2 3732
3ad9ec6a 3733 case TAB(ABRANCH,SZ_UNDEF): {
f8701a3f
SC		 3734 if((fragP->fr_symbol != NULL) /* Not absolute */
3735 && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3736 fragP->fr_subtype=TAB(TABTYPE(fragP->fr_subtype),BYTE);
3737 break;
3738 } else if((fragP->fr_symbol == 0) || (cpu_of_arch(current_architecture) < m68020)) {
3739 /* On 68000, or for absolute value, switch to abs long */
3740 /* FIXME, we should check abs val, pick short or long */
3741 if(fragP->fr_opcode[0]==0x61) {
3742 fragP->fr_opcode[0]= 0x4E;
3743 fragP->fr_opcode[1]= 0xB9; /* JBSR with ABSL LONG offset */
3744 subseg_change(SEG_TEXT, 0);
6d27d3a2 3745 fix_new(fragP, fragP->fr_fix, 4,
f8701a3f
SC		 3746 fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3747 fragP->fr_fix+=4;
3748 frag_wane(fragP);
3749 } else if(fragP->fr_opcode[0]==0x60) {
3750 fragP->fr_opcode[0]= 0x4E;
3751 fragP->fr_opcode[1]= 0xF9; /* JMP with ABSL LONG offset */
3752 subseg_change(SEG_TEXT, 0);
6d27d3a2 3753 fix_new(fragP, fragP->fr_fix, 4,
f8701a3f
SC		 3754 fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3755 fragP->fr_fix+=4;
3756 frag_wane(fragP);
3757 } else {
3758 as_warn("Long branch offset to extern symbol not supported.");
3759 }
3760 } else { /* Symbol is still undefined. Make it simple */
3761 fix_new(fragP, (int)(fragP->fr_fix), 4, fragP->fr_symbol,
3762 (symbolS *)0, fragP->fr_offset+4, 1, NO_RELOC);
3763 fragP->fr_fix+=4;
3764 fragP->fr_opcode[1]=0xff;
3765 frag_wane(fragP);
3766 break;
3767 }
6d27d3a2 3768
f8701a3f 3769 break;
3ad9ec6a 3770 } /* case TAB(ABRANCH,SZ_UNDEF) */
6d27d3a2 3771
f8701a3f
SC		 3772 case TAB(FBRANCH,SZ_UNDEF): {
3773 if(S_GET_SEGMENT(fragP->fr_symbol) == segment || flagseen['l']) {
3774 fragP->fr_subtype = TAB(FBRANCH,SHORT);
3775 fragP->fr_var += 2;
3776 } else {
3777 fragP->fr_subtype = TAB(FBRANCH,LONG);
3778 fragP->fr_var += 4;
3779 }
3780 break;
3781 } /* TAB(FBRANCH,SZ_UNDEF) */
6d27d3a2 3782
f8701a3f
SC		 3783 case TAB(PCREL,SZ_UNDEF): {
3784 if(S_GET_SEGMENT(fragP->fr_symbol) == segment || flagseen['l']) {
3785 fragP->fr_subtype = TAB(PCREL,SHORT);
3786 fragP->fr_var += 2;
3787 } else {
3788 fragP->fr_subtype = TAB(PCREL,LONG);
3789 fragP->fr_var += 4;
3790 }
3791 break;
3792 } /* TAB(PCREL,SZ_UNDEF) */
6d27d3a2 3793
f8701a3f
SC		 3794 case TAB(BCC68000,SZ_UNDEF): {
3795 if((fragP->fr_symbol != NULL)
3796 && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3797 fragP->fr_subtype=TAB(BCC68000,BYTE);
3798 break;
3799 }
3800 /* only Bcc 68000 instructions can come here */
3801 /* change bcc into b!cc/jmp absl long */
3802 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3803 if(flagseen['l']) {
3804 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
3805 /* JF: these were fr_opcode[2,3] */
6d27d3a2 3806 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
f8701a3f
SC		 3807 buffer_address[1] = 0xf8;
3808 fragP->fr_fix += 2; /* account for jmp instruction */
3809 subseg_change(SEG_TEXT,0);
6d27d3a2 3810 fix_new(fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0,
f8701a3f
SC		 3811 fragP->fr_offset, 0, NO_RELOC);
3812 fragP->fr_fix += 2;
3813 } else {
3814 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
3815 /* JF: these were fr_opcode[2,3] */
6d27d3a2 3816 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
a1765cf0 3817 buffer_address[1] = 0xf9;
f8701a3f
SC		 3818 fragP->fr_fix += 2; /* account for jmp instruction */
3819 subseg_change(SEG_TEXT,0);
6d27d3a2 3820 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
f8701a3f
SC		 3821 fragP->fr_offset, 0, NO_RELOC);
3822 fragP->fr_fix += 4;
3823 }
3824 frag_wane(fragP);
3825 break;
3826 } /* case TAB(BCC68000,SZ_UNDEF) */
6d27d3a2 3827
f8701a3f
SC		 3828 case TAB(DBCC,SZ_UNDEF): {
3829 if (fragP->fr_symbol != NULL && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3830 fragP->fr_subtype=TAB(DBCC,SHORT);
3831 fragP->fr_var+=2;
3832 break;
3833 }
3834 /* only DBcc 68000 instructions can come here */
3835 /* change dbcc into dbcc/jmp absl long */
3836 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3837 buffer_address[0] = 0x00; /* branch offset = 4 */
6d27d3a2 3838 buffer_address[1] = 0x04;
f8701a3f 3839 buffer_address[2] = 0x60; /* put in bra pc + ... */
6d27d3a2 3840
f8701a3f
SC		 3841 if(flagseen['l']) {
3842 /* JF: these were fr_opcode[5-7] */
3843 buffer_address[3] = 0x04; /* plus 4 */
3844 buffer_address[4] = 0x4e;/* Put in Jump Word */
3845 buffer_address[5] = 0xf8;
3846 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3847 subseg_change(SEG_TEXT,0);
6d27d3a2 3848 fix_new(fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0,
a933d598
SC		 3849
3850
f8701a3f
SC		 3851 fragP->fr_offset, 0, NO_RELOC);
3852 fragP->fr_fix += 2;
3853 } else {
3854 /* JF: these were fr_opcode[5-7] */
3855 buffer_address[3] = 0x06; /* Plus 6 */
6d27d3a2
KR		 3856 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
3857 buffer_address[5] = 0xf9;
f8701a3f
SC		 3858 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3859 subseg_change(SEG_TEXT,0);
6d27d3a2 3860 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
f8701a3f
SC		 3861 fragP->fr_offset, 0, NO_RELOC);
3862 fragP->fr_fix += 4;
3863 }
6d27d3a2 3864
f8701a3f
SC		 3865 frag_wane(fragP);
3866 break;
3867 } /* case TAB(DBCC,SZ_UNDEF) */
6d27d3a2 3868
f8701a3f
SC		 3869 case TAB(PCLEA,SZ_UNDEF): {
3870 if ((S_GET_SEGMENT(fragP->fr_symbol))==segment || flagseen['l']) {
3871 fragP->fr_subtype=TAB(PCLEA,SHORT);
3872 fragP->fr_var+=2;
3873 } else {
3874 fragP->fr_subtype=TAB(PCLEA,LONG);
3875 fragP->fr_var+=6;
3876 }
3877 break;
3878 } /* TAB(PCLEA,SZ_UNDEF) */
6d27d3a2 3879
f8701a3f
SC		 3880 default:
3881 break;
6d27d3a2 3882
f8701a3f 3883 } /* switch on subtype looking for SZ_UNDEF's. */
6d27d3a2 3884
f8701a3f
SC		 3885 /* now that SZ_UNDEF are taken care of, check others */
3886 switch (fragP->fr_subtype) {
3887 case TAB(BCC68000,BYTE):
3ad9ec6a 3888 case TAB(ABRANCH,BYTE):
a39116f1
RP		 3889 /* We can't do a short jump to the next instruction,
3890 so we force word mode. */
3891 if (fragP->fr_symbol && S_GET_VALUE(fragP->fr_symbol)==0 &&
3892 fragP->fr_symbol->sy_frag==fragP->fr_next) {
f8701a3f
SC		 3893 fragP->fr_subtype=TAB(TABTYPE(fragP->fr_subtype),SHORT);
3894 fragP->fr_var+=2;
fecd2382 3895 }
a39116f1 3896 break;
f8701a3f 3897 default:
a39116f1 3898 break;
f8701a3f
SC		 3899}
3900 return fragP->fr_var + fragP->fr_fix - old_fix;
fecd2382
RP		 3901}
3902
3903#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
6d27d3a2 3904/* the bit-field entries in the relocation_info struct plays hell
fecd2382
RP		 3905 with the byte-order problems of cross-assembly. So as a hack,
3906 I added this mach. dependent ri twiddler. Ugly, but it gets
3907 you there. -KWK */
3908/* on m68k: first 4 bytes are normal unsigned long, next three bytes
a39116f1
RP		 3909 are symbolnum, most sig. byte first. Last byte is broken up with
3910 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3911 nibble as nuthin. (on Sun 3 at least) */
fecd2382
RP		 3912/* Translate the internal relocation information into target-specific
3913 format. */
a79c6033 3914#ifdef comment
fecd2382 3915void
a39116f1
RP		 3916 md_ri_to_chars(the_bytes, ri)
3917char *the_bytes;
3918struct reloc_info_generic *ri;
fecd2382 3919{
f8701a3f
SC		 3920 /* this is easy */
3921 md_number_to_chars(the_bytes, ri->r_address, 4);
3922 /* now the fun stuff */
3923 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
3924 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
3925 the_bytes[6] = ri->r_symbolnum & 0x0ff;
6d27d3a2
KR		 3926 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
3927 ((ri->r_extern << 4) & 0x10));
fecd2382 3928}
a79c6033
RP		 3929#endif /* comment */
3930
3931void tc_aout_fix_to_chars(where, fixP, segment_address_in_file)
f8701a3f
SC		 3932char *where;
3933fixS *fixP;
3934relax_addressT segment_address_in_file;
a79c6033 3935{
f8701a3f
SC		 3936 /*
3937 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3938 * Out: GNU LD relocation length code: 0, 1, or 2.
3939 */
6d27d3a2 3940
f8701a3f
SC		 3941 static unsigned char nbytes_r_length [] = { 42, 0, 1, 42, 2 };
3942 long r_symbolnum;
6d27d3a2 3943
f8701a3f 3944 know(fixP->fx_addsy != NULL);
6d27d3a2 3945
f8701a3f
SC		 3946 md_number_to_chars(where,
3947 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
3948 4);
6d27d3a2 3949
f8701a3f
SC		 3950 r_symbolnum = (S_IS_DEFINED(fixP->fx_addsy)
3951 ? S_GET_TYPE(fixP->fx_addsy)
3952 : fixP->fx_addsy->sy_number);
6d27d3a2 3953
f8701a3f
SC		 3954 where[4] = (r_symbolnum >> 16) & 0x0ff;
3955 where[5] = (r_symbolnum >> 8) & 0x0ff;
3956 where[6] = r_symbolnum & 0x0ff;
6d27d3a2 3957 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
f8701a3f 3958 (((!S_IS_DEFINED(fixP->fx_addsy)) << 4) & 0x10));
6d27d3a2 3959
f8701a3f 3960 return;
a79c6033
RP		 3961} /* tc_aout_fix_to_chars() */
3962
fecd2382
RP		 3963#endif /* OBJ_AOUT or OBJ_BOUT */
3964
3965#ifndef WORKING_DOT_WORD
3966const int md_short_jump_size = 4;
3967const int md_long_jump_size = 6;
3968
3969void
a39116f1 3970 md_create_short_jump(ptr,from_addr,to_addr,frag,to_symbol)
fecd2382
RP		 3971char *ptr;
3972long from_addr,
a39116f1 3973 to_addr;
fecd2382
RP		 3974fragS *frag;
3975symbolS *to_symbol;
3976{
f8701a3f 3977 long offset;
6d27d3a2 3978
f8701a3f 3979 offset = to_addr - (from_addr+2);
6d27d3a2 3980
f8701a3f
SC		 3981 md_number_to_chars(ptr ,(long)0x6000,2);
3982 md_number_to_chars(ptr+2,(long)offset,2);
fecd2382
RP		 3983}
3984
3985void
a39116f1 3986 md_create_long_jump(ptr,from_addr,to_addr,frag,to_symbol)
fecd2382
RP		 3987char *ptr;
3988long from_addr,
a39116f1 3989 to_addr;
fecd2382
RP		 3990fragS *frag;
3991symbolS *to_symbol;
3992{
f8701a3f 3993 long offset;
6d27d3a2 3994
f8701a3f
SC		 3995 if (cpu_of_arch(current_architecture) < m68020) {
3996 offset=to_addr-S_GET_VALUE(to_symbol);
3997 md_number_to_chars(ptr ,(long)0x4EF9,2);
3998 md_number_to_chars(ptr+2,(long)offset,4);
3999 fix_new(frag,(ptr+2)-frag->fr_literal,4,to_symbol,(symbolS *)0,(long)0,0,
4000 NO_RELOC);
4001 } else {
4002 offset=to_addr - (from_addr+2);
4003 md_number_to_chars(ptr ,(long)0x60ff,2);
4004 md_number_to_chars(ptr+2,(long)offset,4);
4005 }
fecd2382
RP		 4006}
4007
4008#endif
4009/* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
6d27d3a2 4010
a39116f1
RP		 4011 0: Everything is OK
4012 10: Absolute 1:8 only
4013 20: Absolute 0:7 only
4014 30: absolute 0:15 only
4015 40: Absolute 0:31 only
4016 50: absolute 0:127 only
4017 55: absolute -64:63 only
4018 60: absolute -128:127 only
4019 70: absolute 0:4095 only
4020 80: No bignums
6d27d3a2 4021
a39116f1 4022 */
fecd2382
RP		 4023
4024static int get_num(exp,ok)
f8701a3f
SC		 4025struct m68k_exp *exp;
4026int ok;
fecd2382
RP		 4027{
4028#ifdef TEST2
f8701a3f 4029 long l = 0;
6d27d3a2 4030
f8701a3f
SC		 4031 if(!exp->e_beg)
4032 return 0;
4033 if(*exp->e_beg=='0') {
4034 if(exp->e_beg[1]=='x')
4035 sscanf(exp->e_beg+2,"%x",&l);
4036 else
4037 sscanf(exp->e_beg+1,"%O",&l);
4038 return l;
4039 }
4040 return atol(exp->e_beg);
fecd2382 4041#else
f8701a3f
SC		 4042 char *save_in;
4043 char c_save;
6d27d3a2 4044
f8701a3f
SC		 4045 if(!exp) {
4046 /* Can't do anything */
4047 return 0;
4048 }
4049 if(!exp->e_beg || !exp->e_end) {
4050 seg(exp)=SEG_ABSOLUTE;
4051 adds(exp)=0;
4052 subs(exp)=0;
4053 offs(exp)= (ok==10) ? 1 : 0;
4054 as_warn("Null expression defaults to %ld",offs(exp));
4055 return 0;
fecd2382 4056 }
6d27d3a2 4057
f8701a3f 4058 exp->e_siz=0;
3ad9ec6a
ILT		 4059 if(/* ok!=80 && */ (exp->e_end[-1]==':' || exp->e_end[-1]=='.')
4060 && (exp->e_end-exp->e_beg)>=2) {
f8701a3f
SC		 4061 switch(exp->e_end[0]) {
4062 case 's':
4063 case 'S':
4064 case 'b':
4065 case 'B':
4066 exp->e_siz=1;
3ad9ec6a 4067 exp->e_end-=2;
f8701a3f
SC		 4068 break;
4069 case 'w':
4070 case 'W':
4071 exp->e_siz=2;
3ad9ec6a 4072 exp->e_end-=2;
f8701a3f
SC		 4073 break;
4074 case 'l':
4075 case 'L':
4076 exp->e_siz=3;
3ad9ec6a 4077 exp->e_end-=2;
f8701a3f
SC		 4078 break;
4079 default:
3ad9ec6a
ILT		 4080 if (exp->e_end[-1] == ':')
4081 as_bad("Unknown size for expression \"%c\"",exp->e_end[0]);
4082 break;
f8701a3f 4083 }
fecd2382 4084 }
f8701a3f
SC		 4085 c_save=exp->e_end[1];
4086 exp->e_end[1]='\0';
4087 save_in=input_line_pointer;
4088 input_line_pointer=exp->e_beg;
4089 switch(expression(&(exp->e_exp))) {
4090 case SEG_PASS1:
4091 seg(exp)=SEG_ABSOLUTE;
4092 adds(exp)=0;
4093 subs(exp)=0;
4094 offs(exp)= (ok==10) ? 1 : 0;
4095 as_warn("Unknown expression: '%s' defaulting to %d",exp->e_beg,offs(exp));
4096 break;
6d27d3a2 4097
f8701a3f
SC		 4098 case SEG_ABSENT:
4099 /* Do the same thing the VAX asm does */
4100 seg(exp)=SEG_ABSOLUTE;
4101 adds(exp)=0;
4102 subs(exp)=0;
fecd2382 4103 offs(exp)=0;
f8701a3f
SC		 4104 if(ok==10) {
4105 as_warn("expression out of range: defaulting to 1");
4106 offs(exp)=1;
4107 }
4108 break;
4109 case SEG_ABSOLUTE:
4110 switch(ok) {
4111 case 10:
4112 if(offs(exp)<1 || offs(exp)>8) {
4113 as_warn("expression out of range: defaulting to 1");
4114 offs(exp)=1;
4115 }
4116 break;
4117 case 20:
4118 if(offs(exp)<0 || offs(exp)>7)
4119 goto outrange;
4120 break;
4121 case 30:
4122 if(offs(exp)<0 || offs(exp)>15)
4123 goto outrange;
4124 break;
4125 case 40:
4126 if(offs(exp)<0 || offs(exp)>32)
4127 goto outrange;
4128 break;
4129 case 50:
4130 if(offs(exp)<0 || offs(exp)>127)
4131 goto outrange;
4132 break;
4133 case 55:
4134 if(offs(exp)<-64 || offs(exp)>63)
4135 goto outrange;
4136 break;
4137 case 60:
4138 if(offs(exp)<-128 || offs(exp)>127)
4139 goto outrange;
4140 break;
4141 case 70:
4142 if(offs(exp)<0 || offs(exp)>4095) {
4143 outrange:
4144 as_warn("expression out of range: defaulting to 0");
4145 offs(exp)=0;
4146 }
4147 break;
4148 default:
4149 break;
4150 }
4151 break;
f8701a3f 4152 case SEG_BIG:
e53ab768
KR		 4153 if (offs (exp) < 0 /* flonum */
4154 && (ok == 80 /* no bignums */
4155 || (ok > 10 /* small-int ranges including 0 ok */
4156 /* If we have a flonum zero, a zero integer should
4157 do as well (e.g., in moveq). */
4158 && generic_floating_point_number.exponent == 0
4159 && generic_floating_point_number.low[0] == 0)))
4160 {
4161 /* HACK! Turn it into a long */
4162 LITTLENUM_TYPE words[6];
4163
4164 gen_to_words(words,2,8L);/* These numbers are magic! */
4165 seg(exp)=SEG_ABSOLUTE;
4166 adds(exp)=0;
4167 subs(exp)=0;
4168 offs(exp)=words[1]|(words[0]<<16);
4169 }
4170 else if(ok!=0) {
f8701a3f
SC		 4171 seg(exp)=SEG_ABSOLUTE;
4172 adds(exp)=0;
4173 subs(exp)=0;
4174 offs(exp)= (ok==10) ? 1 : 0;
4175 as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp->e_beg,offs(exp));
4176 }
4177 break;
fecd2382 4178 default:
587c4264
ILT		 4179 case SEG_TEXT:
4180 case SEG_DATA:
4181 case SEG_BSS:
4182 case SEG_UNKNOWN:
4183 case SEG_DIFFERENCE:
4184 if(ok>=10 && ok<=70) {
4185 seg(exp)=SEG_ABSOLUTE;
4186 adds(exp)=0;
4187 subs(exp)=0;
4188 offs(exp)= (ok==10) ? 1 : 0;
4189 as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp->e_beg,offs(exp));
4190 }
4191 break;
4192
4193
a39116f1 4194 }
f8701a3f
SC		 4195 if(input_line_pointer!=exp->e_end+1)
4196 as_bad("Ignoring junk after expression");
4197 exp->e_end[1]=c_save;
4198 input_line_pointer=save_in;
4199 if(exp->e_siz) {
4200 switch(exp->e_siz) {
4201 case 1:
4202 if(!isbyte(offs(exp)))
4203 as_warn("expression doesn't fit in BYTE");
4204 break;
4205 case 2:
4206 if(!isword(offs(exp)))
4207 as_warn("expression doesn't fit in WORD");
4208 break;
4209 }
a39116f1 4210 }
f8701a3f 4211 return offs(exp);
fecd2382
RP		 4212#endif
4213} /* get_num() */
4214
4215/* These are the back-ends for the various machine dependent pseudo-ops. */
f6e504fe 4216void demand_empty_rest_of_line(); /* Hate those extra verbose names */
fecd2382
RP		 4217
4218static void s_data1() {
f8701a3f
SC		 4219 subseg_new(SEG_DATA,1);
4220 demand_empty_rest_of_line();
fecd2382
RP		 4221} /* s_data1() */
4222
4223static void s_data2() {
f8701a3f
SC		 4224 subseg_new(SEG_DATA,2);
4225 demand_empty_rest_of_line();
fecd2382
RP		 4226} /* s_data2() */
4227
6d27d3a2 4228static void s_bss()
a1765cf0 4229{
6d27d3a2 4230 /* We don't support putting frags in the BSS segment, we fake it
a1765cf0
SC		 4231 by marking in_bss, then looking at s_skip for clues */
4232
4233 subseg_new(SEG_BSS, 0);
f8701a3f 4234 demand_empty_rest_of_line();
fecd2382
RP		 4235} /* s_bss() */
4236
4237static void s_even() {
f8701a3f
SC		 4238 register int temp;
4239 register long temp_fill;
6d27d3a2 4240
f8701a3f
SC		 4241 temp = 1; /* JF should be 2? */
4242 temp_fill = get_absolute_expression ();
4243 if ( ! need_pass_2 ) /* Never make frag if expect extra pass. */
4244 frag_align (temp, (int)temp_fill);
4245 demand_empty_rest_of_line();
fecd2382
RP		 4246} /* s_even() */
4247
4248static void s_proc() {
f8701a3f 4249 demand_empty_rest_of_line();
fecd2382
RP		 4250} /* s_proc() */
4251
4252/* s_space is defined in read.c .skip is simply an alias to it. */
4253
7c15cbe8
RP		 4254/*
4255 * md_parse_option
4256 * Invocation line includes a switch not recognized by the base assembler.
4257 * See if it's a processor-specific option. These are:
4258 *
4259 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
4260 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
4261 * Select the architecture. Instructions or features not
4262 * supported by the selected architecture cause fatal
4263 * errors. More than one may be specified. The default is
4264 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
4265 * for -m68000, and -m68882 is a synonym for -m68881.
df3768fb
KR		 4266 * -[A]m[c]no-68851, -[A]m[c]no-68881
4267 * Don't accept 688?1 instructions. (The "c" is kind of silly,
4268 * so don't use or document it, but that's the way the parsing
4269 * works).
7c15cbe8 4270 *
a39116f1
RP		 4271 * MAYBE_FLOAT_TOO is defined below so that specifying a processor type
4272 * (e.g. m68020) also requests that float instructions be included. This
4273 * is the default setup, mostly to avoid hassling users. A better
4274 * rearrangement of this structure would be to add an option to DENY
4275 * floating point opcodes, for people who want to really know there's none
4276 * of that funny floaty stuff going on. FIXME-later.
7c15cbe8 4277 */
a39116f1 4278#ifndef MAYBE_FLOAT_TOO
df3768fb 4279#define MAYBE_FLOAT_TOO /* m68881 */ 0 /* this is handled later */
a39116f1 4280#endif
7c15cbe8
RP		 4281
4282int md_parse_option(argP,cntP,vecP)
f8701a3f
SC		 4283char **argP;
4284int *cntP;
4285char ***vecP;
fecd2382 4286{
f8701a3f
SC		 4287 switch(**argP) {
4288 case 'l': /* -l means keep external to 2 bit offset
4289 rather than 16 bit one */
4290 break;
6d27d3a2 4291
f8701a3f
SC		 4292 case 'S': /* -S means that jbsr's always turn into jsr's. */
4293 break;
6d27d3a2 4294
f8701a3f
SC		 4295 case 'A':
4296 (*argP)++;
4297 /* intentional fall-through */
4298 case 'm':
4299 (*argP)++;
6d27d3a2 4300
f8701a3f
SC		 4301 if (**argP=='c') {
4302 (*argP)++;
4303 } /* allow an optional "c" */
6d27d3a2 4304
f8701a3f
SC		 4305 if (!strcmp(*argP, "68000")
4306 || !strcmp(*argP, "68008")) {
4307 current_architecture |= m68000;
4308 } else if (!strcmp(*argP, "68010")) {
fecd2382 4309#ifdef TE_SUN
f8701a3f 4310 omagic= 1<<16|OMAGIC;
fecd2382 4311#endif
f8701a3f 4312 current_architecture |= m68010;
6d27d3a2
KR		 4313
4314 } else if (!strcmp(*argP, "68020")) {
f8701a3f 4315 current_architecture |= m68020 | MAYBE_FLOAT_TOO;
6d27d3a2
KR		 4316
4317 } else if (!strcmp(*argP, "68030")) {
f8701a3f 4318 current_architecture |= m68030 | MAYBE_FLOAT_TOO;
6d27d3a2
KR		 4319
4320 } else if (!strcmp(*argP, "68040")) {
f8701a3f 4321 current_architecture |= m68040 | MAYBE_FLOAT_TOO;
6d27d3a2 4322
7c15cbe8 4323#ifndef NO_68881
f8701a3f
SC		 4324 } else if (!strcmp(*argP, "68881")) {
4325 current_architecture |= m68881;
6d27d3a2 4326
f8701a3f
SC		 4327 } else if (!strcmp(*argP, "68882")) {
4328 current_architecture |= m68882;
7c15cbe8 4329#endif /* NO_68881 */
df3768fb
KR		 4330 /* Even if we aren't configured to support the processor,
4331 it should still be possible to assert that the user
4332 doesn't have it... */
4333 } else if (!strcmp (*argP, "no-68881")
4334 || !strcmp (*argP, "no-68882")) {
4335 no_68881 = 1;
7c15cbe8 4336#ifndef NO_68851
6d27d3a2 4337 } else if (!strcmp(*argP,"68851")) {
f8701a3f 4338 current_architecture |= m68851;
7c15cbe8 4339#endif /* NO_68851 */
df3768fb
KR		 4340 } else if (!strcmp (*argP, "no-68851")) {
4341 no_68851 = 1;
4342 } else if (!strcmp (*argP, "pu32")) { /* "-mcpu32" */
4343 current_architecture |= cpu32;
f8701a3f
SC		 4344 } else {
4345 as_warn("Unknown architecture, \"%s\". option ignored", *argP);
4346 } /* switch on architecture */
6d27d3a2 4347
f8701a3f 4348 while(**argP) (*argP)++;
6d27d3a2 4349
f8701a3f 4350 break;
6d27d3a2 4351
f8701a3f
SC		 4352 case 'p':
4353 if (!strcmp(*argP,"pic")) {
4354 (*argP) += 3;
4355 break; /* -pic, Position Independent Code */
4356 } else {
4357 return(0);
4358 } /* pic or not */
6d27d3a2 4359
f8701a3f
SC		 4360 default:
4361 return 0;
4362 }
4363 return 1;
fecd2382
RP		 4364}
4365
4366
4367#ifdef TEST2
4368
4369/* TEST2: Test md_assemble() */
4370/* Warning, this routine probably doesn't work anymore */
4371
4372main()
4373{
f8701a3f
SC		 4374 struct m68k_it the_ins;
4375 char buf[120];
4376 char *cp;
4377 int n;
6d27d3a2 4378
f8701a3f
SC		 4379 m68k_ip_begin();
4380 for(;;) {
4381 if(!gets(buf) || !*buf)
4382 break;
4383 if(buf[0]=='|' || buf[1]=='.')
4384 continue;
4385 for(cp=buf;*cp;cp++)
4386 if(*cp=='\t')
4387 *cp=' ';
4388 if(is_label(buf))
4389 continue;
4390 memset(&the_ins, '\0', sizeof(the_ins));
4391 m68k_ip(&the_ins,buf);
4392 if(the_ins.error) {
4393 printf("Error %s in %s\n",the_ins.error,buf);
4394 } else {
4395 printf("Opcode(%d.%s): ",the_ins.numo,the_ins.args);
4396 for(n=0;n<the_ins.numo;n++)
4397 printf(" 0x%x",the_ins.opcode[n]&0xffff);
4398 printf(" ");
4399 print_the_insn(&the_ins.opcode[0],stdout);
4400 (void)putchar('\n');
4401 }
4402 for(n=0;n<strlen(the_ins.args)/2;n++) {
4403 if(the_ins.operands[n].error) {
4404 printf("op%d Error %s in %s\n",n,the_ins.operands[n].error,buf);
4405 continue;
4406 }
4407 printf("mode %d, reg %d, ",the_ins.operands[n].mode,the_ins.operands[n].reg);
4408 if(the_ins.operands[n].b_const)
4409 printf("Constant: '%.*s', ",1+the_ins.operands[n].e_const-the_ins.operands[n].b_const,the_ins.operands[n].b_const);
4410 printf("ireg %d, isiz %d, imul %d, ",the_ins.operands[n].ireg,the_ins.operands[n].isiz,the_ins.operands[n].imul);
4411 if(the_ins.operands[n].b_iadd)
4412 printf("Iadd: '%.*s',",1+the_ins.operands[n].e_iadd-the_ins.operands[n].b_iadd,the_ins.operands[n].b_iadd);
4413 (void)putchar('\n');
4414 }
a39116f1 4415 }
f8701a3f
SC		 4416 m68k_ip_end();
4417 return 0;
fecd2382
RP		 4418}
4419
4420is_label(str)
f8701a3f 4421char *str;
fecd2382 4422{
f8701a3f
SC		 4423 while(*str==' ')
4424 str++;
4425 while(*str && *str!=' ')
4426 str++;
4427 if(str[-1]==':' || str[1]=='=')
4428 return 1;
4429 return 0;
fecd2382
RP		 4430}
4431
4432#endif
4433
4434/* Possible states for relaxation:
6d27d3a2 4435
a39116f1
RP		 4436 0 0 branch offset byte (bra, etc)
4437 0 1 word
4438 0 2 long
6d27d3a2 4439
a39116f1
RP		 4440 1 0 indexed offsets byte a0@(32,d4:w:1) etc
4441 1 1 word
4442 1 2 long
6d27d3a2 4443
a39116f1
RP		 4444 2 0 two-offset index word-word a0@(32,d4)@(45) etc
4445 2 1 word-long
4446 2 2 long-word
4447 2 3 long-long
6d27d3a2 4448
a39116f1 4449 */
fecd2382
RP		 4450
4451
4452
4453#ifdef DONTDEF
4454abort()
4455{
f8701a3f
SC		 4456 printf("ABORT!\n");
4457 exit(12);
fecd2382
RP		 4458}
4459
4460print_frags()
4461{
f8701a3f
SC		 4462 fragS *fragP;
4463 extern fragS *text_frag_root;
6d27d3a2 4464
f8701a3f
SC		 4465 for(fragP=text_frag_root;fragP;fragP=fragP->fr_next) {
4466 printf("addr %lu next 0x%x fix %ld var %ld symbol 0x%x offset %ld\n",
4467 fragP->fr_address,fragP->fr_next,fragP->fr_fix,fragP->fr_var,fragP->fr_symbol,fragP->fr_offset);
4468 printf("opcode 0x%x type %d subtype %d\n\n",fragP->fr_opcode,fragP->fr_type,fragP->fr_subtype);
4469 }
4470 fflush(stdout);
4471 return 0;
fecd2382
RP		 4472}
4473#endif
4474
4475#ifdef DONTDEF
4476/*VARARGS1*/
4477panic(format,args)
f8701a3f 4478char *format;
fecd2382 4479{
f8701a3f
SC		 4480 fputs("Internal error:",stderr);
4481 _doprnt(format,&args,stderr);
4482 (void)putc('\n',stderr);
4483 as_where();
4484 abort();
fecd2382
RP		 4485}
4486#endif
4487
4488/* We have no need to default values of symbols. */
4489
4490/* ARGSUSED */
4491symbolS *
a39116f1
RP		 4492 md_undefined_symbol (name)
4493char *name;
fecd2382 4494{
f8701a3f 4495 return 0;
fecd2382
RP		 4496}
4497
6d27d3a2 4498/* Parse an operand that is machine-specific.
fecd2382
RP		 4499 We just return without modifying the expression if we have nothing
4500 to do. */
4501
4502/* ARGSUSED */
4503void
a39116f1
RP		 4504 md_operand (expressionP)
4505expressionS *expressionP;
fecd2382
RP		 4506{
4507}
4508
4509/* Round up a section size to the appropriate boundary. */
4510long
a39116f1
RP		 4511 md_section_align (segment, size)
4512segT segment;
4513long size;
fecd2382 4514{
f8701a3f 4515 return size; /* Byte alignment is fine */
fecd2382
RP		 4516}
4517
4518/* Exactly what point is a PC-relative offset relative TO?
4519 On the 68k, they're relative to the address of the offset, plus
4520 its size. (??? Is this right? FIXME-SOON!) */
4521long
a39116f1
RP		 4522 md_pcrel_from (fixP)
4523fixS *fixP;
fecd2382 4524{
f8701a3f 4525 return(fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address);
fecd2382
RP		 4526}
4527
3ad9ec6a
ILT		 4528void
4529tc_coff_symbol_emit_hook ()
4530{
4531}
4532
4533int
4534tc_coff_sizemachdep(frag)
4535fragS *frag;
4536{
4537 switch (frag->fr_subtype & 0x3)
4538 {
4539 case BYTE: return 1;
4540 case SHORT: return 2;
4541 case LONG: return 4;
4542 default: abort();
4543 }
4544
4545}
fecd2382
RP		 4546/*
4547 * Local Variables:
4548 * comment-column: 0
4549 * fill-column: 131
4550 * End:
4551 */
4552
4553/* end of tc-m68k.c */
3ad9ec6a 4554
GDB Binutils - Deliverables
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