Commit | Line | Data |
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a87b3269 | 1 | /* tc-m68k.c All the m68020 specific stuff in one convenient, huge, |
fecd2382 | 2 | slow to compile, easy to find file. |
6d27d3a2 | 3 | |
a87b3269 | 4 | Copyright (C) 1987, 1991, 1992 Free Software Foundation, Inc. |
6d27d3a2 | 5 | |
a39116f1 | 6 | This file is part of GAS, the GNU Assembler. |
6d27d3a2 | 7 | |
a39116f1 RP |
8 | GAS is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
6d27d3a2 | 12 | |
a39116f1 RP |
13 | GAS is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
6d27d3a2 | 17 | |
a39116f1 RP |
18 | You should have received a copy of the GNU General Public License |
19 | along with GAS; see the file COPYING. If not, write to | |
20 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
fecd2382 RP |
21 | |
22 | #include <ctype.h> | |
f8701a3f | 23 | #define NO_RELOC 0 |
fecd2382 RP |
24 | #include "as.h" |
25 | ||
26 | #include "obstack.h" | |
27 | ||
a39116f1 | 28 | /* note that this file includes real declarations and thus can only be included by one source file per executable. */ |
e0982afe | 29 | #include "opcode/m68k.h" |
f6e504fe RP |
30 | #ifdef TE_SUN |
31 | /* This variable contains the value to write out at the beginning of | |
32 | the a.out file. The 2<<16 means that this is a 68020 file instead | |
33 | of an old-style 68000 file */ | |
34 | ||
35 | long omagic = 2<<16|OMAGIC; /* Magic byte for header file */ | |
36 | #else | |
37 | long omagic = OMAGIC; | |
38 | #endif | |
fecd2382 RP |
39 | |
40 | /* This array holds the chars that always start a comment. If the | |
41 | pre-processor is disabled, these aren't very useful */ | |
42 | const char comment_chars[] = "|"; | |
43 | ||
44 | /* This array holds the chars that only start a comment at the beginning of | |
45 | a line. If the line seems to have the form '# 123 filename' | |
46 | .line and .file directives will appear in the pre-processed output */ | |
47 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
48 | first line of the input file. This is because the compiler outputs | |
49 | #NO_APP at the beginning of its output. */ | |
50 | /* Also note that comments like this one will always work. */ | |
51 | const char line_comment_chars[] = "#"; | |
52 | ||
53 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
54 | const char EXP_CHARS[] = "eE"; | |
55 | ||
56 | /* Chars that mean this number is a floating point constant */ | |
57 | /* As in 0f12.456 */ | |
58 | /* or 0d1.2345e12 */ | |
59 | ||
60 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; | |
61 | ||
62 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
63 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
64 | but nothing is ideal around here. | |
a39116f1 | 65 | */ |
fecd2382 RP |
66 | |
67 | int md_reloc_size = 8; /* Size of relocation record */ | |
68 | ||
69 | /* Its an arbitrary name: This means I don't approve of it */ | |
70 | /* See flames below */ | |
71 | static struct obstack robyn; | |
72 | ||
73 | #define TAB(x,y) (((x)<<2)+(y)) | |
74 | #define TABTYPE(xy) ((xy) >> 2) | |
75 | #define BYTE 0 | |
76 | #define SHORT 1 | |
77 | #define LONG 2 | |
78 | #define SZ_UNDEF 3 | |
79 | ||
80 | #define BRANCH 1 | |
81 | #define FBRANCH 2 | |
82 | #define PCREL 3 | |
83 | #define BCC68000 4 | |
84 | #define DBCC 5 | |
85 | #define PCLEA 6 | |
86 | ||
f6e504fe | 87 | /* Operands we can parse: (And associated modes) |
6d27d3a2 | 88 | |
a39116f1 RP |
89 | numb: 8 bit num |
90 | numw: 16 bit num | |
91 | numl: 32 bit num | |
92 | dreg: data reg 0-7 | |
93 | reg: address or data register | |
94 | areg: address register | |
95 | apc: address register, PC, ZPC or empty string | |
96 | num: 16 or 32 bit num | |
97 | num2: like num | |
98 | sz: w or l if omitted, l assumed | |
99 | scale: 1 2 4 or 8 if omitted, 1 assumed | |
6d27d3a2 | 100 | |
a39116f1 RP |
101 | 7.4 IMMED #num --> NUM |
102 | 0.? DREG dreg --> dreg | |
103 | 1.? AREG areg --> areg | |
104 | 2.? AINDR areg@ --> *(areg) | |
105 | 3.? AINC areg@+ --> *(areg++) | |
106 | 4.? ADEC areg@- --> *(--areg) | |
107 | 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here | |
108 | 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale) | |
109 | 6.? AINDX apc@(reg:sz:scale) --> same, with num=0 | |
110 | 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale) | |
111 | 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0 | |
112 | 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg) | |
113 | 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2) | |
114 | 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0 | |
115 | 7.0 ABSL num:sz --> *(num) | |
116 | num --> *(num) (sz L assumed) | |
117 | *** MSCR otherreg --> Magic | |
118 | With -l option | |
119 | 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still | |
6d27d3a2 | 120 | |
a39116f1 RP |
121 | examples: |
122 | #foo #0x35 #12 | |
123 | d2 | |
124 | a4 | |
125 | a3@ | |
126 | a5@+ | |
127 | a6@- | |
128 | a2@(12) pc@(14) | |
129 | a1@(5,d2:w:1) @(45,d6:l:4) | |
130 | pc@(a2) @(d4) | |
131 | etc . . . | |
6d27d3a2 KR |
132 | |
133 | ||
a39116f1 RP |
134 | #name@(numw) -->turn into PC rel mode |
135 | apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale) | |
6d27d3a2 | 136 | |
a39116f1 | 137 | */ |
f6e504fe RP |
138 | |
139 | enum operand_type { | |
f8701a3f SC |
140 | IMMED = 1, |
141 | DREG, | |
142 | AREG, | |
143 | AINDR, | |
144 | ADEC, | |
145 | AINC, | |
146 | AOFF, | |
147 | AINDX, | |
148 | APODX, | |
149 | AMIND, | |
150 | APRDX, | |
151 | ABSL, | |
152 | MSCR, | |
153 | REGLST, | |
f6e504fe RP |
154 | }; |
155 | ||
156 | ||
fecd2382 | 157 | struct m68k_exp { |
f8701a3f SC |
158 | char *e_beg; |
159 | char *e_end; | |
160 | expressionS e_exp; | |
161 | short e_siz; /* 0== default 1==short/byte 2==word 3==long */ | |
fecd2382 RP |
162 | }; |
163 | ||
7c15cbe8 RP |
164 | /* DATA and ADDR have to be contiguous, so that reg-DATA gives 0-7==data reg, |
165 | 8-15==addr reg for operands that take both types */ | |
166 | ||
167 | enum _register { | |
f8701a3f SC |
168 | DATA = 1, /* 1- 8 == data registers 0-7 */ |
169 | DATA0 = DATA, | |
170 | DATA1, | |
171 | DATA2, | |
172 | DATA3, | |
173 | DATA4, | |
174 | DATA5, | |
175 | DATA6, | |
176 | DATA7, | |
6d27d3a2 | 177 | |
f8701a3f SC |
178 | ADDR, |
179 | ADDR0 = ADDR, | |
180 | ADDR1, | |
181 | ADDR2, | |
182 | ADDR3, | |
183 | ADDR4, | |
184 | ADDR5, | |
185 | ADDR6, | |
186 | ADDR7, | |
6d27d3a2 | 187 | |
f8701a3f SC |
188 | /* Note that COPNUM==processor #1 -- COPNUM+7==#8, which stores as 000 */ |
189 | /* I think. . . */ | |
6d27d3a2 | 190 | |
f8701a3f | 191 | SP = ADDR7, |
6d27d3a2 | 192 | |
f8701a3f SC |
193 | FPREG, /* Eight FP registers */ |
194 | FP0 = FPREG, | |
195 | FP1, | |
196 | FP2, | |
197 | FP3, | |
198 | FP4, | |
199 | FP5, | |
200 | FP6, | |
201 | FP7, | |
202 | COPNUM = (FPREG+8), /* Co-processor #1-#8 */ | |
203 | COP0 = COPNUM, | |
204 | COP1, | |
205 | COP2, | |
206 | COP3, | |
207 | COP4, | |
208 | COP5, | |
209 | COP6, | |
210 | COP7, | |
211 | PC, /* Program counter */ | |
212 | ZPC, /* Hack for Program space, but 0 addressing */ | |
213 | SR, /* Status Reg */ | |
214 | CCR, /* Condition code Reg */ | |
6d27d3a2 | 215 | |
f8701a3f SC |
216 | /* These have to be in order for the movec instruction to work. */ |
217 | USP, /* User Stack Pointer */ | |
218 | ISP, /* Interrupt stack pointer */ | |
219 | SFC, | |
220 | DFC, | |
221 | CACR, | |
222 | VBR, | |
223 | CAAR, | |
224 | MSP, | |
225 | ITT0, | |
226 | ITT1, | |
227 | DTT0, | |
228 | DTT1, | |
229 | MMUSR, | |
230 | TC, | |
231 | SRP, | |
232 | URP, | |
233 | /* end of movec ordering constraints */ | |
6d27d3a2 | 234 | |
f8701a3f SC |
235 | FPI, |
236 | FPS, | |
237 | FPC, | |
6d27d3a2 | 238 | |
f8701a3f SC |
239 | DRP, |
240 | CRP, | |
241 | CAL, | |
242 | VAL, | |
243 | SCC, | |
244 | AC, | |
245 | BAD, | |
246 | BAD0 = BAD, | |
247 | BAD1, | |
248 | BAD2, | |
249 | BAD3, | |
250 | BAD4, | |
251 | BAD5, | |
252 | BAD6, | |
253 | BAD7, | |
254 | BAC, | |
255 | BAC0 = BAC, | |
256 | BAC1, | |
257 | BAC2, | |
258 | BAC3, | |
259 | BAC4, | |
260 | BAC5, | |
261 | BAC6, | |
262 | BAC7, | |
263 | PSR, | |
264 | PCSR, | |
6d27d3a2 | 265 | |
f8701a3f SC |
266 | IC, /* instruction cache token */ |
267 | DC, /* data cache token */ | |
268 | NC, /* no cache token */ | |
269 | BC, /* both caches token */ | |
6d27d3a2 | 270 | |
7c15cbe8 RP |
271 | }; |
272 | ||
fecd2382 RP |
273 | /* Internal form of an operand. */ |
274 | struct m68k_op { | |
f8701a3f SC |
275 | char *error; /* Couldn't parse it */ |
276 | enum operand_type mode; /* What mode this instruction is in. */ | |
277 | enum _register reg; /* Base register */ | |
278 | struct m68k_exp *con1; | |
279 | int ireg; /* Index register */ | |
280 | int isiz; /* 0==unspec 1==byte(?) 2==short 3==long */ | |
281 | int imul; /* Multipy ireg by this (1,2,4,or 8) */ | |
282 | struct m68k_exp *con2; | |
fecd2382 RP |
283 | }; |
284 | ||
285 | /* internal form of a 68020 instruction */ | |
7c15cbe8 | 286 | struct m68k_it { |
f8701a3f SC |
287 | char *error; |
288 | char *args; /* list of opcode info */ | |
289 | int numargs; | |
6d27d3a2 | 290 | |
f8701a3f SC |
291 | int numo; /* Number of shorts in opcode */ |
292 | short opcode[11]; | |
6d27d3a2 | 293 | |
f8701a3f | 294 | struct m68k_op operands[6]; |
6d27d3a2 | 295 | |
f8701a3f SC |
296 | int nexp; /* number of exprs in use */ |
297 | struct m68k_exp exprs[4]; | |
6d27d3a2 | 298 | |
f8701a3f SC |
299 | int nfrag; /* Number of frags we have to produce */ |
300 | struct { | |
301 | int fragoff; /* Where in the current opcode[] the frag ends */ | |
302 | symbolS *fadd; | |
303 | long foff; | |
304 | int fragty; | |
305 | } fragb[4]; | |
6d27d3a2 | 306 | |
f8701a3f SC |
307 | int nrel; /* Num of reloc strucs in use */ |
308 | struct { | |
309 | int n; | |
310 | symbolS *add, | |
311 | *sub; | |
312 | long off; | |
313 | char wid; | |
314 | char pcrel; | |
315 | } reloc[5]; /* Five is enough??? */ | |
fecd2382 RP |
316 | }; |
317 | ||
865a2edf MT |
318 | #define cpu_of_arch(x) ((x) & m68000up) |
319 | #define float_of_arch(x) ((x) & mfloat) | |
320 | #define mmu_of_arch(x) ((x) & mmmu) | |
321 | ||
7c15cbe8 | 322 | static struct m68k_it the_ins; /* the instruction being assembled */ |
fecd2382 | 323 | |
7c15cbe8 | 324 | /* Macros for adding things to the m68k_it struct */ |
fecd2382 RP |
325 | |
326 | #define addword(w) the_ins.opcode[the_ins.numo++]=(w) | |
327 | ||
328 | /* Like addword, but goes BEFORE general operands */ | |
329 | #define insop(w) {int z;\ | |
a39116f1 RP |
330 | for(z=the_ins.numo;z>opcode->m_codenum;--z)\ |
331 | the_ins.opcode[z]=the_ins.opcode[z-1];\ | |
332 | for(z=0;z<the_ins.nrel;z++)\ | |
333 | the_ins.reloc[z].n+=2;\ | |
334 | the_ins.opcode[opcode->m_codenum]=w;\ | |
335 | the_ins.numo++;\ | |
f8701a3f | 336 | } |
fecd2382 RP |
337 | |
338 | ||
339 | #define add_exp(beg,end) (\ | |
a39116f1 RP |
340 | the_ins.exprs[the_ins.nexp].e_beg=beg,\ |
341 | the_ins.exprs[the_ins.nexp].e_end=end,\ | |
342 | &the_ins.exprs[the_ins.nexp++]\ | |
343 | ) | |
fecd2382 RP |
344 | |
345 | ||
346 | /* The numo+1 kludge is so we can hit the low order byte of the prev word. Blecch*/ | |
347 | #define add_fix(width,exp,pc_rel) {\ | |
a39116f1 RP |
348 | the_ins.reloc[the_ins.nrel].n= ((width)=='B') ? (the_ins.numo*2-1) : \ |
349 | (((width)=='b') ? ((the_ins.numo-1)*2) : (the_ins.numo*2));\ | |
350 | the_ins.reloc[the_ins.nrel].add=adds((exp));\ | |
351 | the_ins.reloc[the_ins.nrel].sub=subs((exp));\ | |
352 | the_ins.reloc[the_ins.nrel].off=offs((exp));\ | |
353 | the_ins.reloc[the_ins.nrel].wid=width;\ | |
354 | the_ins.reloc[the_ins.nrel++].pcrel=pc_rel;\ | |
f8701a3f | 355 | } |
fecd2382 RP |
356 | |
357 | #define add_frag(add,off,type) {\ | |
a39116f1 RP |
358 | the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;\ |
359 | the_ins.fragb[the_ins.nfrag].fadd=add;\ | |
360 | the_ins.fragb[the_ins.nfrag].foff=off;\ | |
361 | the_ins.fragb[the_ins.nfrag++].fragty=type;\ | |
f8701a3f | 362 | } |
fecd2382 RP |
363 | |
364 | #define isvar(exp) ((exp) && (adds(exp) || subs(exp))) | |
365 | ||
366 | #define seg(exp) ((exp)->e_exp.X_seg) | |
367 | #define adds(exp) ((exp)->e_exp.X_add_symbol) | |
368 | #define subs(exp) ((exp)->e_exp.X_subtract_symbol) | |
369 | #define offs(exp) ((exp)->e_exp.X_add_number) | |
370 | ||
371 | ||
7c15cbe8 | 372 | struct m68k_incant { |
f8701a3f SC |
373 | char *m_operands; |
374 | unsigned long m_opcode; | |
375 | short m_opnum; | |
376 | short m_codenum; | |
377 | enum m68k_architecture m_arch; | |
378 | struct m68k_incant *m_next; | |
fecd2382 RP |
379 | }; |
380 | ||
381 | #define getone(x) ((((x)->m_opcode)>>16)&0xffff) | |
382 | #define gettwo(x) (((x)->m_opcode)&0xffff) | |
383 | ||
384 | ||
a87b3269 | 385 | #if __STDC__ == 1 |
fecd2382 RP |
386 | |
387 | static char *crack_operand(char *str, struct m68k_op *opP); | |
388 | static int get_num(struct m68k_exp *exp, int ok); | |
389 | static int get_regs(int i, char *str, struct m68k_op *opP); | |
390 | static int reverse_16_bits(int in); | |
391 | static int reverse_8_bits(int in); | |
392 | static int try_index(char **s, struct m68k_op *opP); | |
393 | static void install_gen_operand(int mode, int val); | |
394 | static void install_operand(int mode, int val); | |
a933d598 | 395 | void s_bss(void); |
fecd2382 RP |
396 | static void s_data1(void); |
397 | static void s_data2(void); | |
398 | static void s_even(void); | |
399 | static void s_proc(void); | |
400 | ||
a87b3269 | 401 | #else /* not __STDC__ */ |
fecd2382 RP |
402 | |
403 | static char *crack_operand(); | |
404 | static int get_num(); | |
405 | static int get_regs(); | |
406 | static int reverse_16_bits(); | |
407 | static int reverse_8_bits(); | |
408 | static int try_index(); | |
409 | static void install_gen_operand(); | |
410 | static void install_operand(); | |
9e43698e SC |
411 | void s_bss(); |
412 | void s_align_bytes(); | |
fecd2382 RP |
413 | static void s_data1(); |
414 | static void s_data2(); | |
415 | static void s_even(); | |
416 | static void s_proc(); | |
417 | ||
a87b3269 | 418 | #endif /* not __STDC__ */ |
fecd2382 | 419 | |
865a2edf | 420 | static enum m68k_architecture current_architecture = 0; |
7c15cbe8 | 421 | |
fecd2382 RP |
422 | /* BCC68000 is for patching in an extra jmp instruction for long offsets |
423 | on the 68000. The 68000 doesn't support long branches with branchs */ | |
424 | ||
425 | /* This table desribes how you change sizes for the various types of variable | |
426 | size expressions. This version only supports two kinds. */ | |
427 | ||
428 | /* Note that calls to frag_var need to specify the maximum expansion needed */ | |
429 | /* This is currently 10 bytes for DBCC */ | |
430 | ||
431 | /* The fields are: | |
a39116f1 RP |
432 | How far Forward this mode will reach: |
433 | How far Backward this mode will reach: | |
434 | How many bytes this mode will add to the size of the frag | |
435 | Which mode to go to if the offset won't fit in this one | |
436 | */ | |
fecd2382 | 437 | const relax_typeS |
a39116f1 | 438 | md_relax_table[] = { |
f8701a3f SC |
439 | { 1, 1, 0, 0 }, /* First entries aren't used */ |
440 | { 1, 1, 0, 0 }, /* For no good reason except */ | |
441 | { 1, 1, 0, 0 }, /* that the VAX doesn't either */ | |
442 | { 1, 1, 0, 0 }, | |
6d27d3a2 | 443 | |
f8701a3f SC |
444 | { (127), (-128), 0, TAB(BRANCH,SHORT)}, |
445 | { (32767), (-32768), 2, TAB(BRANCH,LONG) }, | |
446 | { 0, 0, 4, 0 }, | |
447 | { 1, 1, 0, 0 }, | |
6d27d3a2 | 448 | |
f8701a3f SC |
449 | { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */ |
450 | { (32767), (-32768), 2, TAB(FBRANCH,LONG)}, | |
451 | { 0, 0, 4, 0 }, | |
452 | { 1, 1, 0, 0 }, | |
6d27d3a2 | 453 | |
f8701a3f SC |
454 | { 1, 1, 0, 0 }, /* PCREL doesn't come BYTE */ |
455 | { (32767), (-32768), 2, TAB(PCREL,LONG)}, | |
456 | { 0, 0, 4, 0 }, | |
457 | { 1, 1, 0, 0 }, | |
6d27d3a2 | 458 | |
f8701a3f SC |
459 | { (127), (-128), 0, TAB(BCC68000,SHORT)}, |
460 | { (32767), (-32768), 2, TAB(BCC68000,LONG) }, | |
461 | { 0, 0, 6, 0 }, /* jmp long space */ | |
462 | { 1, 1, 0, 0 }, | |
6d27d3a2 | 463 | |
f8701a3f SC |
464 | { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */ |
465 | { (32767), (-32768), 2, TAB(DBCC,LONG) }, | |
466 | { 0, 0, 10, 0 }, /* bra/jmp long space */ | |
467 | { 1, 1, 0, 0 }, | |
6d27d3a2 | 468 | |
f8701a3f SC |
469 | { 1, 1, 0, 0 }, /* PCLEA doesn't come BYTE */ |
470 | { 32767, -32768, 2, TAB(PCLEA,LONG) }, | |
471 | { 0, 0, 6, 0 }, | |
472 | { 1, 1, 0, 0 }, | |
6d27d3a2 | 473 | |
f8701a3f | 474 | }; |
fecd2382 RP |
475 | |
476 | /* These are the machine dependent pseudo-ops. These are included so | |
477 | the assembler can work on the output from the SUN C compiler, which | |
478 | generates these. | |
a39116f1 | 479 | */ |
fecd2382 RP |
480 | |
481 | /* This table describes all the machine specific pseudo-ops the assembler | |
482 | has to support. The fields are: | |
a39116f1 RP |
483 | pseudo-op name without dot |
484 | function to call to execute this pseudo-op | |
485 | Integer arg to pass to the function | |
486 | */ | |
fecd2382 | 487 | const pseudo_typeS md_pseudo_table[] = { |
f8701a3f SC |
488 | { "data1", s_data1, 0 }, |
489 | { "data2", s_data2, 0 }, | |
490 | { "bss", s_bss, 0 }, | |
491 | { "even", s_even, 0 }, | |
492 | { "skip", s_space, 0 }, | |
493 | { "proc", s_proc, 0 }, | |
9e43698e | 494 | { "align", s_align_bytes, 0 }, |
f8701a3f | 495 | { 0, 0, 0 } |
fecd2382 RP |
496 | }; |
497 | ||
498 | ||
499 | /* #define isbyte(x) ((x)>=-128 && (x)<=127) */ | |
500 | /* #define isword(x) ((x)>=-32768 && (x)<=32767) */ | |
501 | ||
502 | #define issbyte(x) ((x)>=-128 && (x)<=127) | |
503 | #define isubyte(x) ((x)>=0 && (x)<=255) | |
504 | #define issword(x) ((x)>=-32768 && (x)<=32767) | |
505 | #define isuword(x) ((x)>=0 && (x)<=65535) | |
f8701a3f | 506 | |
fecd2382 RP |
507 | #define isbyte(x) ((x)>=-128 && (x)<=255) |
508 | #define isword(x) ((x)>=-32768 && (x)<=65535) | |
509 | #define islong(x) (1) | |
f8701a3f SC |
510 | |
511 | extern char *input_line_pointer; | |
fecd2382 | 512 | |
7c15cbe8 | 513 | enum { |
f8701a3f SC |
514 | FAIL = 0, |
515 | OK = 1, | |
7c15cbe8 | 516 | }; |
fecd2382 RP |
517 | |
518 | /* JF these tables here are for speed at the expense of size */ | |
519 | /* You can replace them with the #if 0 versions if you really | |
520 | need space and don't mind it running a bit slower */ | |
521 | ||
522 | static char mklower_table[256]; | |
523 | #define mklower(c) (mklower_table[(unsigned char)(c)]) | |
f8701a3f | 524 | static char notend_table[256]; |
fecd2382 RP |
525 | static char alt_notend_table[256]; |
526 | #define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\ | |
a39116f1 | 527 | alt_notend_table[(unsigned char)(s[1])]))) |
fecd2382 RP |
528 | |
529 | #if 0 | |
530 | #define mklower(c) (isupper(c) ? tolower(c) : c) | |
531 | #endif | |
f8701a3f SC |
532 | |
533 | ||
534 | /* JF modified this to handle cases where the first part of a symbol name | |
535 | looks like a register */ | |
536 | ||
537 | /* | |
538 | * m68k_reg_parse() := if it looks like a register, return it's token & | |
539 | * advance the pointer. | |
540 | */ | |
541 | ||
542 | enum _register m68k_reg_parse(ccp) | |
fecd2382 RP |
543 | register char **ccp; |
544 | { | |
f8701a3f SC |
545 | char *start = *ccp; |
546 | ||
6d27d3a2 | 547 | if (isalpha(*start) && is_name_beginner(*start)) |
f8701a3f SC |
548 | { |
549 | char c; | |
550 | char *p = start; | |
551 | symbolS *symbolP; | |
6d27d3a2 | 552 | |
f8701a3f SC |
553 | while (is_part_of_name(c = *p++)) |
554 | ; | |
555 | * -- p = 0; | |
556 | symbolP = symbol_find(start); | |
557 | *p = c; | |
558 | ||
6d27d3a2 | 559 | if (symbolP && S_GET_SEGMENT(symbolP) == SEG_REGISTER) |
a39116f1 | 560 | { |
f8701a3f SC |
561 | *ccp = p; |
562 | return S_GET_VALUE(symbolP); | |
a39116f1 | 563 | } |
f8701a3f SC |
564 | } |
565 | return FAIL; | |
566 | ||
567 | ||
fecd2382 RP |
568 | } |
569 | ||
570 | #define SKIP_WHITE() { str++; if(*str==' ') str++;} | |
571 | ||
7c15cbe8 RP |
572 | /* |
573 | * m68k_ip_op := '#' + <anything> | |
574 | * | <register> + range_sep + get_regs | |
575 | * ; | |
6d27d3a2 | 576 | * |
7c15cbe8 RP |
577 | * range_sep := '/' | '-' ; |
578 | * | |
579 | * SKIP_WHITE := <empty> | ' ' ; | |
580 | * | |
581 | */ | |
582 | ||
fecd2382 | 583 | int |
a39116f1 | 584 | m68k_ip_op(str,opP) |
fecd2382 RP |
585 | char *str; |
586 | register struct m68k_op *opP; | |
587 | { | |
f8701a3f SC |
588 | char *strend; |
589 | long i; | |
590 | char *parse_index(); | |
a933d598 | 591 | int needp; |
f8701a3f SC |
592 | if (*str==' ') { |
593 | str++; | |
594 | } /* Find the beginning of the string */ | |
6d27d3a2 | 595 | |
f8701a3f SC |
596 | if(!*str) { |
597 | opP->error="Missing operand"; | |
fecd2382 | 598 | return FAIL; |
f8701a3f | 599 | } /* Out of gas */ |
6d27d3a2 | 600 | |
f8701a3f | 601 | for(strend = str; *strend; strend++) ;; |
6d27d3a2 | 602 | |
f8701a3f | 603 | --strend; |
6d27d3a2 | 604 | |
f8701a3f SC |
605 | if(*str=='#') { |
606 | str++; | |
607 | opP->con1=add_exp(str,strend); | |
608 | opP->mode=IMMED; | |
609 | return OK; | |
610 | } /* Guess what: A constant. Shar and enjoy */ | |
6d27d3a2 | 611 | |
f8701a3f | 612 | i = m68k_reg_parse(&str); |
6d27d3a2 | 613 | |
f8701a3f | 614 | /* is a register, is exactly a register, and is followed by '@' */ |
6d27d3a2 | 615 | |
f8701a3f SC |
616 | if((i==FAIL || *str!='\0') && *str!='@') { |
617 | char *stmp; | |
6d27d3a2 | 618 | |
f8701a3f SC |
619 | if(i!=FAIL && (*str=='/' || *str=='-')) { |
620 | opP->mode=REGLST; | |
621 | return(get_regs(i,str,opP)); | |
622 | } | |
623 | if ((stmp=strchr(str,'@')) != '\0') { | |
624 | opP->con1=add_exp(str,stmp-1); | |
625 | if(stmp==strend) { | |
626 | opP->mode=AINDX; | |
627 | return(OK); | |
628 | } | |
6d27d3a2 | 629 | |
f8701a3f SC |
630 | if ((current_architecture & m68020up) == 0) { |
631 | return(FAIL); | |
632 | } /* if target is not a '20 or better */ | |
6d27d3a2 | 633 | |
f8701a3f SC |
634 | stmp++; |
635 | if(*stmp++!='(' || *strend--!=')') { | |
636 | opP->error="Malformed operand"; | |
637 | return(FAIL); | |
638 | } | |
639 | i=try_index(&stmp,opP); | |
640 | opP->con2=add_exp(stmp,strend); | |
6d27d3a2 | 641 | |
f8701a3f SC |
642 | if (i == FAIL) { |
643 | opP->mode=AMIND; | |
644 | } else { | |
645 | opP->mode=APODX; | |
646 | } | |
647 | return(OK); | |
648 | } /* if there's an '@' */ | |
649 | opP->mode = ABSL; | |
650 | opP->con1 = add_exp(str,strend); | |
651 | return(OK); | |
652 | } /* not a register, not exactly a register, or no '@' */ | |
6d27d3a2 | 653 | |
f8701a3f | 654 | opP->reg=i; |
6d27d3a2 | 655 | |
f8701a3f SC |
656 | if (*str=='\0') { |
657 | if(i>=DATA+0 && i<=DATA+7) | |
658 | opP->mode=DREG; | |
659 | else if(i>=ADDR+0 && i<=ADDR+7) | |
660 | opP->mode=AREG; | |
661 | else | |
662 | opP->mode=MSCR; | |
663 | return OK; | |
fecd2382 | 664 | } |
6d27d3a2 | 665 | |
f8701a3f SC |
666 | if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL) { /* Can't indirect off non address regs */ |
667 | opP->error="Invalid indirect register"; | |
a39116f1 | 668 | return FAIL; |
fecd2382 | 669 | } |
f8701a3f | 670 | know(*str == '@'); |
6d27d3a2 | 671 | |
f8701a3f SC |
672 | str++; |
673 | switch(*str) { | |
674 | case '\0': | |
675 | opP->mode=AINDR; | |
676 | return OK; | |
677 | case '-': | |
678 | opP->mode=ADEC; | |
679 | return OK; | |
680 | case '+': | |
681 | opP->mode=AINC; | |
682 | return OK; | |
683 | case '(': | |
684 | str++; | |
685 | break; | |
686 | default: | |
687 | opP->error="Junk after indirect"; | |
688 | return FAIL; | |
fecd2382 | 689 | } |
f8701a3f SC |
690 | /* Some kind of indexing involved. Lets find out how bad it is */ |
691 | i=try_index(&str,opP); | |
692 | /* Didn't start with an index reg, maybe its offset or offset,reg */ | |
693 | if(i==FAIL) { | |
694 | char *beg_str; | |
6d27d3a2 | 695 | |
f8701a3f SC |
696 | beg_str=str; |
697 | for(i=1;i;) { | |
698 | switch(*str++) { | |
699 | case '\0': | |
700 | opP->error="Missing )"; | |
701 | return FAIL; | |
702 | case ',': i=0; break; | |
703 | case '(': i++; break; | |
704 | case ')': --i; break; | |
705 | } | |
706 | } | |
707 | /* if(str[-3]==':') { | |
708 | int siz; | |
6d27d3a2 | 709 | |
f8701a3f SC |
710 | switch(str[-2]) { |
711 | case 'b': | |
712 | case 'B': | |
713 | siz=1; | |
714 | break; | |
715 | case 'w': | |
716 | case 'W': | |
717 | siz=2; | |
718 | break; | |
719 | case 'l': | |
720 | case 'L': | |
721 | siz=3; | |
722 | break; | |
723 | default: | |
724 | opP->error="Specified size isn't :w or :l"; | |
725 | return FAIL; | |
726 | } | |
727 | opP->con1=add_exp(beg_str,str-4); | |
728 | opP->con1->e_siz=siz; | |
729 | } else */ | |
730 | opP->con1=add_exp(beg_str,str-2); | |
731 | /* Should be offset,reg */ | |
732 | if(str[-1]==',') { | |
733 | i=try_index(&str,opP); | |
734 | if(i==FAIL) { | |
735 | opP->error="Malformed index reg"; | |
736 | return FAIL; | |
737 | } | |
738 | } | |
739 | } | |
740 | /* We've now got offset) offset,reg) or reg) */ | |
6d27d3a2 | 741 | |
f8701a3f SC |
742 | if (*str == '\0') { |
743 | /* Th-the-thats all folks */ | |
744 | if (opP->reg == FAIL) opP->mode = AINDX; /* Other form of indirect */ | |
745 | else if(opP->ireg == FAIL) opP->mode = AOFF; | |
746 | else opP->mode = AINDX; | |
747 | return(OK); | |
748 | } | |
749 | /* Next thing had better be another @ */ | |
a933d598 SC |
750 | if (*str == '@') { |
751 | if (str[1] == '(') { | |
752 | needp = 1; | |
753 | str+=2; | |
754 | } | |
755 | else { | |
756 | needp = 0; | |
757 | str++; | |
758 | } | |
fecd2382 | 759 | } |
6d27d3a2 | 760 | |
f8701a3f | 761 | if ((current_architecture & m68020up) == 0) { |
a39116f1 | 762 | return(FAIL); |
f8701a3f | 763 | } /* if target is not a '20 or better */ |
6d27d3a2 KR |
764 | |
765 | ||
f8701a3f SC |
766 | if(opP->ireg != FAIL) { |
767 | opP->mode = APRDX; | |
6d27d3a2 | 768 | |
f8701a3f SC |
769 | i = try_index(&str, opP); |
770 | if (i != FAIL) { | |
771 | opP->error = "Two index registers! not allowed!"; | |
772 | return(FAIL); | |
773 | } | |
865a2edf | 774 | } else { |
f8701a3f | 775 | i = try_index(&str, opP); |
865a2edf | 776 | } |
6d27d3a2 | 777 | |
f8701a3f SC |
778 | if (i == FAIL) { |
779 | char *beg_str; | |
6d27d3a2 | 780 | |
f8701a3f | 781 | beg_str = str; |
6d27d3a2 | 782 | |
f8701a3f SC |
783 | for (i = 1; i; ) { |
784 | switch(*str++) { | |
785 | case '\0': | |
a933d598 | 786 | if (needp) |
f8701a3f SC |
787 | opP->error="Missing )"; |
788 | return(FAIL); | |
a933d598 | 789 | break; |
f8701a3f SC |
790 | case ',': i=0; break; |
791 | case '(': i++; break; | |
792 | case ')': --i; break; | |
793 | } | |
794 | } | |
6d27d3a2 | 795 | |
f8701a3f | 796 | opP->con2=add_exp(beg_str,str-2); |
6d27d3a2 | 797 | |
f8701a3f SC |
798 | if (str[-1] == ',') { |
799 | if (opP->ireg != FAIL) { | |
800 | opP->error = "Can't have two index regs"; | |
801 | return(FAIL); | |
802 | } | |
6d27d3a2 | 803 | |
f8701a3f | 804 | i = try_index(&str, opP); |
6d27d3a2 | 805 | |
f8701a3f SC |
806 | if (i == FAIL) { |
807 | opP->error = "malformed index reg"; | |
808 | return(FAIL); | |
809 | } | |
6d27d3a2 | 810 | |
f8701a3f SC |
811 | opP->mode = APODX; |
812 | } else if (opP->ireg != FAIL) { | |
813 | opP->mode = APRDX; | |
814 | } else { | |
815 | opP->mode = AMIND; | |
816 | } | |
817 | } else { | |
818 | opP->mode = APODX; | |
819 | } | |
6d27d3a2 | 820 | |
f8701a3f SC |
821 | if(*str!='\0') { |
822 | opP->error="Junk after indirect"; | |
823 | return FAIL; | |
824 | } | |
825 | return(OK); | |
a39116f1 | 826 | } /* m68k_ip_op() */ |
fecd2382 | 827 | |
7c15cbe8 | 828 | /* |
6d27d3a2 | 829 | * |
7c15cbe8 RP |
830 | * try_index := data_or_address_register + ')' + SKIP_W |
831 | * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W | |
832 | * | |
833 | * multiplier := <empty> | |
834 | * | ':' + multiplier_number | |
835 | * ; | |
836 | * | |
837 | * multiplier_number := '1' | '2' | '4' | '8' ; | |
838 | * | |
839 | * size_spec := 'l' | 'L' | 'w' | 'W' ; | |
840 | * | |
841 | * SKIP_W := <empty> | ' ' ; | |
842 | * | |
843 | */ | |
844 | ||
fecd2382 | 845 | static int try_index(s,opP) |
f8701a3f SC |
846 | char **s; |
847 | struct m68k_op *opP; | |
fecd2382 | 848 | { |
f8701a3f SC |
849 | register int i; |
850 | char *ss; | |
7c15cbe8 | 851 | #define SKIP_W() { ss++; if (*ss==' ') ss++;} |
6d27d3a2 | 852 | |
f8701a3f SC |
853 | ss= *s; |
854 | /* SKIP_W(); */ | |
855 | i=m68k_reg_parse(&ss); | |
856 | if(!(i>=DATA+0 && i<=ADDR+7)) { /* if i is not DATA or ADDR reg */ | |
857 | *s=ss; | |
858 | return FAIL; | |
859 | } | |
860 | opP->ireg=i; | |
861 | /* SKIP_W(); */ | |
862 | if(*ss==')') { | |
863 | opP->isiz=0; | |
864 | opP->imul=1; | |
865 | SKIP_W(); | |
866 | *s=ss; | |
867 | return OK; | |
868 | } | |
869 | if(*ss!=':') { | |
870 | opP->error="Missing : in index register"; | |
871 | *s=ss; | |
872 | return FAIL; | |
873 | } | |
fecd2382 RP |
874 | SKIP_W(); |
875 | switch(*ss) { | |
f8701a3f SC |
876 | case 'w': |
877 | case 'W': | |
878 | opP->isiz=2; | |
879 | break; | |
880 | case 'l': | |
881 | case 'L': | |
882 | opP->isiz=3; | |
883 | break; | |
fecd2382 | 884 | default: |
f8701a3f SC |
885 | opP->error="Index register size spec not :w or :l"; |
886 | *s=ss; | |
887 | return FAIL; | |
888 | } | |
889 | SKIP_W(); | |
890 | if(*ss==':') { | |
891 | SKIP_W(); | |
892 | switch(*ss) { | |
893 | case '1': | |
894 | case '2': | |
895 | case '4': | |
896 | case '8': | |
934afcd4 JG |
897 | if (cpu_of_arch(current_architecture) < m68020) { |
898 | opP->error="no index scaling in pre-68020's"; | |
899 | *s=ss; | |
900 | return FAIL; | |
901 | } | |
f8701a3f SC |
902 | opP->imul= *ss-'0'; |
903 | break; | |
904 | default: | |
905 | opP->error="index multiplier not 1, 2, 4 or 8"; | |
906 | *s=ss; | |
907 | return FAIL; | |
908 | } | |
909 | SKIP_W(); | |
910 | } else opP->imul=1; | |
911 | if(*ss!=')') { | |
912 | opP->error="Missing )"; | |
913 | *s=ss; | |
914 | return FAIL; | |
fecd2382 RP |
915 | } |
916 | SKIP_W(); | |
917 | *s=ss; | |
f8701a3f | 918 | return OK; |
fecd2382 RP |
919 | } /* try_index() */ |
920 | ||
921 | #ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */ | |
922 | main() | |
923 | { | |
f8701a3f SC |
924 | char buf[128]; |
925 | struct m68k_op thark; | |
6d27d3a2 | 926 | |
f8701a3f SC |
927 | for(;;) { |
928 | if(!gets(buf)) | |
929 | break; | |
930 | memset(&thark, '\0', sizeof(thark)); | |
931 | if(!m68k_ip_op(buf,&thark)) printf("FAIL:"); | |
932 | if(thark.error) | |
933 | printf("op1 error %s in %s\n",thark.error,buf); | |
934 | printf("mode %d, reg %d, ",thark.mode,thark.reg); | |
935 | if(thark.b_const) | |
936 | printf("Constant: '%.*s',",1+thark.e_const-thark.b_const,thark.b_const); | |
937 | printf("ireg %d, isiz %d, imul %d ",thark.ireg,thark.isiz,thark.imul); | |
938 | if(thark.b_iadd) | |
939 | printf("Iadd: '%.*s'",1+thark.e_iadd-thark.b_iadd,thark.b_iadd); | |
940 | printf("\n"); | |
941 | } | |
942 | exit(0); | |
fecd2382 RP |
943 | } |
944 | ||
945 | #endif | |
946 | ||
947 | ||
948 | static struct hash_control* op_hash = NULL; /* handle of the OPCODE hash table | |
a39116f1 RP |
949 | NULL means any use before m68k_ip_begin() |
950 | will crash */ | |
fecd2382 RP |
951 | |
952 | \f | |
953 | /* | |
7c15cbe8 | 954 | * m 6 8 k _ i p ( ) |
fecd2382 RP |
955 | * |
956 | * This converts a string into a 68k instruction. | |
957 | * The string must be a bare single instruction in sun format | |
958 | * with RMS-style 68020 indirects | |
959 | * (example: ) | |
960 | * | |
961 | * It provides some error messages: at most one fatal error message (which | |
962 | * stops the scan) and at most one warning message for each operand. | |
963 | * The 68k instruction is returned in exploded form, since we have no | |
964 | * knowledge of how you parse (or evaluate) your expressions. | |
965 | * We do however strip off and decode addressing modes and operation | |
966 | * mnemonic. | |
967 | * | |
968 | * This function's value is a string. If it is not "" then an internal | |
969 | * logic error was found: read this code to assign meaning to the string. | |
970 | * No argument string should generate such an error string: | |
971 | * it means a bug in our code, not in the user's text. | |
972 | * | |
7c15cbe8 | 973 | * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using |
fecd2382 RP |
974 | * this function. |
975 | */ | |
976 | ||
977 | /* JF this function no longer returns a useful value. Sorry */ | |
7c15cbe8 | 978 | void m68k_ip (instring) |
6d27d3a2 | 979 | char *instring; |
fecd2382 | 980 | { |
6d27d3a2 KR |
981 | register char *p; |
982 | register struct m68k_op *opP; | |
983 | register struct m68k_incant *opcode; | |
984 | register char *s; | |
985 | register int tmpreg = 0, baseo = 0, outro = 0, nextword; | |
986 | int siz1, siz2; | |
987 | char c; | |
988 | int losing; | |
989 | int opsfound; | |
990 | char *crack_operand(); | |
991 | LITTLENUM_TYPE words[6]; | |
992 | LITTLENUM_TYPE *wordp; | |
993 | ||
994 | if (*instring == ' ') | |
995 | instring++; /* skip leading whitespace */ | |
996 | ||
997 | /* Scan up to end of operation-code, which MUST end in end-of-string | |
998 | or exactly 1 space. */ | |
999 | for (p = instring; *p != '\0'; p++) | |
1000 | if (*p == ' ') | |
1001 | break; | |
1002 | ||
1003 | ||
1004 | if (p == instring) { | |
1005 | the_ins.error = "No operator"; | |
1006 | the_ins.opcode[0] = NULL; | |
1007 | /* the_ins.numo=1; */ | |
1008 | return; | |
1009 | } | |
1010 | ||
1011 | /* p now points to the end of the opcode name, probably whitespace. | |
1012 | make sure the name is null terminated by clobbering the whitespace, | |
1013 | look it up in the hash table, then fix it back. */ | |
1014 | c = *p; | |
1015 | *p = '\0'; | |
1016 | opcode = (struct m68k_incant *)hash_find (op_hash, instring); | |
1017 | *p = c; | |
1018 | ||
1019 | if (opcode == NULL) { | |
1020 | the_ins.error = "Unknown operator"; | |
1021 | the_ins.opcode[0] = NULL; | |
1022 | /* the_ins.numo=1; */ | |
1023 | return; | |
1024 | } | |
1025 | ||
1026 | /* found a legitimate opcode, start matching operands */ | |
1027 | while (*p == ' ') ++p; | |
1028 | ||
1029 | for(opP = &the_ins.operands[0]; *p; opP++) { | |
1030 | ||
1031 | p = crack_operand(p, opP); | |
1032 | ||
1033 | if (opP->error) { | |
1034 | the_ins.error=opP->error; | |
1035 | return; | |
1036 | } | |
1037 | } | |
1038 | ||
1039 | opsfound = opP - &the_ins.operands[0]; | |
1040 | ||
1041 | /* This ugly hack is to support the floating pt opcodes in their standard form */ | |
1042 | /* Essentially, we fake a first enty of type COP#1 */ | |
1043 | if (opcode->m_operands[0]=='I') { | |
1044 | int n; | |
1045 | ||
1046 | for(n=opsfound;n>0;--n) | |
1047 | the_ins.operands[n]=the_ins.operands[n-1]; | |
1048 | ||
1049 | /* memcpy((char *)(&the_ins.operands[1]), (char *)(&the_ins.operands[0]), opsfound*sizeof(the_ins.operands[0])); */ | |
1050 | memset((char *)(&the_ins.operands[0]), '\0', sizeof(the_ins.operands[0])); | |
1051 | the_ins.operands[0].mode=MSCR; | |
1052 | the_ins.operands[0].reg=COPNUM; /* COP #1 */ | |
1053 | opsfound++; | |
1054 | } | |
1055 | ||
1056 | /* We've got the operands. Find an opcode that'll accept them */ | |
1057 | for (losing = 0; ; ) { | |
1058 | /* if we didn't get the right number of ops, | |
1059 | or we have no common model with this pattern | |
1060 | then reject this pattern. */ | |
1061 | ||
1062 | if (opsfound != opcode->m_opnum | |
1063 | || ((opcode->m_arch & current_architecture) == 0)) { | |
1064 | ||
1065 | ++losing; | |
1066 | ||
1067 | } else { | |
1068 | for (s=opcode->m_operands, opP = &the_ins.operands[0]; *s && !losing; s += 2, opP++) { | |
1069 | /* Warning: this switch is huge! */ | |
1070 | /* I've tried to organize the cases into this order: | |
1071 | non-alpha first, then alpha by letter. lower-case goes directly | |
1072 | before uppercase counterpart. */ | |
1073 | /* Code with multiple case ...: gets sorted by the lowest case ... | |
1074 | it belongs to. I hope this makes sense. */ | |
1075 | switch(*s) { | |
1076 | case '!': | |
1077 | if (opP->mode == MSCR || opP->mode == IMMED | |
1078 | || opP->mode == DREG || opP->mode == AREG | |
1079 | || opP->mode == AINC || opP->mode == ADEC | |
1080 | || opP->mode == REGLST) | |
1081 | losing++; | |
1082 | break; | |
1083 | ||
1084 | case '#': | |
1085 | if(opP->mode!=IMMED) | |
1086 | losing++; | |
1087 | else { | |
1088 | long t; | |
1089 | ||
1090 | t=get_num(opP->con1,80); | |
1091 | if(s[1]=='b' && !isbyte(t)) | |
1092 | losing++; | |
1093 | else if(s[1]=='w' && !isword(t)) | |
1094 | losing++; | |
1095 | } | |
1096 | break; | |
1097 | ||
1098 | case '^': | |
1099 | case 'T': | |
1100 | if(opP->mode!=IMMED) | |
1101 | losing++; | |
1102 | break; | |
1103 | ||
1104 | case '$': | |
1105 | if(opP->mode==MSCR || opP->mode==AREG || | |
1106 | opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST) | |
1107 | losing++; | |
1108 | break; | |
1109 | ||
1110 | case '%': | |
1111 | if(opP->mode==MSCR || opP->reg==PC || | |
1112 | opP->reg==ZPC || opP->mode==REGLST) | |
1113 | losing++; | |
1114 | break; | |
1115 | ||
1116 | ||
1117 | case '&': | |
1118 | if(opP->mode==MSCR || opP->mode==DREG || | |
1119 | opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || | |
1120 | opP->mode==AINC || opP->mode==ADEC || opP->mode==REGLST) | |
1121 | losing++; | |
1122 | break; | |
1123 | ||
1124 | case '*': | |
1125 | if(opP->mode==MSCR || opP->mode==REGLST) | |
1126 | losing++; | |
1127 | break; | |
1128 | ||
1129 | case '+': | |
1130 | if(opP->mode!=AINC) | |
1131 | losing++; | |
1132 | break; | |
1133 | ||
1134 | case '-': | |
1135 | if(opP->mode!=ADEC) | |
1136 | losing++; | |
1137 | break; | |
1138 | ||
1139 | case '/': | |
1140 | if(opP->mode==MSCR || opP->mode==AREG || | |
1141 | opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->mode==REGLST) | |
1142 | losing++; | |
1143 | break; | |
1144 | ||
1145 | case ';': | |
1146 | if(opP->mode==MSCR || opP->mode==AREG || opP->mode==REGLST) | |
1147 | losing++; | |
1148 | break; | |
1149 | ||
1150 | case '?': | |
1151 | if(opP->mode==MSCR || opP->mode==AREG || | |
1152 | opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->reg==PC || | |
1153 | opP->reg==ZPC || opP->mode==REGLST) | |
1154 | losing++; | |
1155 | break; | |
1156 | ||
1157 | case '@': | |
1158 | if(opP->mode==MSCR || opP->mode==AREG || | |
1159 | opP->mode==IMMED || opP->mode==REGLST) | |
1160 | losing++; | |
1161 | break; | |
1162 | ||
1163 | case '~': /* For now! (JF FOO is this right?) */ | |
1164 | if(opP->mode==MSCR || opP->mode==DREG || | |
1165 | opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST) | |
1166 | losing++; | |
1167 | break; | |
1168 | ||
1169 | case 'A': | |
1170 | if(opP->mode!=AREG) | |
1171 | losing++; | |
1172 | break; | |
1173 | case 'a': | |
1174 | if (opP->mode != AINDR) { | |
1175 | ++losing; | |
1176 | } /* if not address register indirect */ | |
1177 | break; | |
1178 | case 'B': /* FOO */ | |
1179 | if(opP->mode!=ABSL || (flagseen['S'] && instring[0] == 'j' | |
1180 | && instring[1] == 'b' | |
1181 | && instring[2] == 's' | |
1182 | && instring[3] == 'r')) | |
1183 | losing++; | |
1184 | break; | |
1185 | ||
1186 | case 'C': | |
1187 | if(opP->mode!=MSCR || opP->reg!=CCR) | |
1188 | losing++; | |
1189 | break; | |
1190 | ||
1191 | case 'd': /* FOO This mode is a KLUDGE!! */ | |
1192 | if(opP->mode!=AOFF && (opP->mode!=ABSL || | |
1193 | opP->con1->e_beg[0]!='(' || opP->con1->e_end[0]!=')')) | |
1194 | losing++; | |
1195 | break; | |
1196 | ||
1197 | case 'D': | |
1198 | if(opP->mode!=DREG) | |
1199 | losing++; | |
1200 | break; | |
1201 | ||
1202 | case 'F': | |
1203 | if(opP->mode!=MSCR || opP->reg<(FPREG+0) || opP->reg>(FPREG+7)) | |
1204 | losing++; | |
1205 | break; | |
1206 | ||
1207 | case 'I': | |
1208 | if(opP->mode!=MSCR || opP->reg<COPNUM || | |
1209 | opP->reg>=COPNUM+7) | |
1210 | losing++; | |
1211 | break; | |
1212 | ||
1213 | case 'J': | |
1214 | if (opP->mode != MSCR | |
1215 | || opP->reg < USP | |
1216 | || opP->reg > URP | |
1217 | || cpu_of_arch(current_architecture) < m68010 /* before 68010 had none */ | |
1218 | || (cpu_of_arch(current_architecture) < m68020 | |
1219 | && opP->reg != SFC | |
1220 | && opP->reg != DFC | |
1221 | && opP->reg != USP | |
1222 | && opP->reg != VBR) /* 68010's had only these */ | |
1223 | || (cpu_of_arch(current_architecture) < m68040 | |
1224 | && opP->reg != SFC | |
1225 | && opP->reg != DFC | |
1226 | && opP->reg != USP | |
1227 | && opP->reg != VBR | |
1228 | && opP->reg != CACR | |
1229 | && opP->reg != CAAR | |
1230 | && opP->reg != MSP | |
1231 | && opP->reg != ISP) /* 680[23]0's have only these */ | |
1232 | || (cpu_of_arch(current_architecture) == m68040 /* 68040 has all but this */ | |
1233 | && opP->reg == CAAR)) { | |
1234 | losing++; | |
1235 | } /* doesn't cut it */ | |
1236 | break; | |
1237 | ||
1238 | case 'k': | |
1239 | if(opP->mode!=IMMED) | |
1240 | losing++; | |
1241 | break; | |
1242 | ||
1243 | case 'l': | |
1244 | case 'L': | |
1245 | if(opP->mode==DREG || opP->mode==AREG || opP->mode==FPREG) { | |
1246 | if(s[1]=='8') | |
1247 | losing++; | |
1248 | else { | |
1249 | opP->mode=REGLST; | |
1250 | opP->reg=1<<(opP->reg-DATA); | |
f8701a3f | 1251 | } |
6d27d3a2 KR |
1252 | } else if(opP->mode!=REGLST) { |
1253 | losing++; | |
1254 | } else if(s[1]=='8' && opP->reg&0x0FFffFF) | |
1255 | losing++; | |
1256 | else if(s[1]=='3' && opP->reg&0x7000000) | |
1257 | losing++; | |
1258 | break; | |
1259 | ||
1260 | case 'M': | |
1261 | if(opP->mode!=IMMED) | |
1262 | losing++; | |
1263 | else { | |
1264 | long t; | |
1265 | ||
1266 | t=get_num(opP->con1,80); | |
1267 | if(!issbyte(t) || isvar(opP->con1)) | |
1268 | losing++; | |
1269 | } | |
1270 | break; | |
1271 | ||
1272 | case 'O': | |
1273 | if(opP->mode!=DREG && opP->mode!=IMMED) | |
1274 | losing++; | |
1275 | break; | |
1276 | ||
1277 | case 'Q': | |
1278 | if(opP->mode!=IMMED) | |
1279 | losing++; | |
1280 | else { | |
1281 | long t; | |
1282 | ||
1283 | t=get_num(opP->con1,80); | |
1284 | if(t<1 || t>8 || isvar(opP->con1)) | |
1285 | losing++; | |
1286 | } | |
1287 | break; | |
1288 | ||
1289 | case 'R': | |
1290 | if(opP->mode!=DREG && opP->mode!=AREG) | |
1291 | losing++; | |
1292 | break; | |
1293 | ||
1294 | case 's': | |
1295 | if(opP->mode!=MSCR || !(opP->reg==FPI || opP->reg==FPS || opP->reg==FPC)) | |
1296 | losing++; | |
1297 | break; | |
1298 | ||
1299 | case 'S': | |
1300 | if(opP->mode!=MSCR || opP->reg!=SR) | |
1301 | losing++; | |
1302 | break; | |
1303 | ||
1304 | case 'U': | |
1305 | if(opP->mode!=MSCR || opP->reg!=USP) | |
1306 | losing++; | |
1307 | break; | |
1308 | ||
1309 | /* JF these are out of order. We could put them | |
1310 | in order if we were willing to put up with | |
1311 | bunches of #ifdef m68851s in the code */ | |
f8701a3f | 1312 | #ifndef NO_68851 |
6d27d3a2 KR |
1313 | /* Memory addressing mode used by pflushr */ |
1314 | case '|': | |
1315 | if(opP->mode==MSCR || opP->mode==DREG || | |
1316 | opP->mode==AREG || opP->mode==REGLST) | |
1317 | losing++; | |
1318 | break; | |
1319 | ||
1320 | case 'f': | |
1321 | if (opP->mode != MSCR || (opP->reg != SFC && opP->reg != DFC)) | |
1322 | losing++; | |
1323 | break; | |
1324 | ||
1325 | case 'P': | |
1326 | if (opP->mode != MSCR || (opP->reg != TC && opP->reg != CAL && | |
1327 | opP->reg != VAL && opP->reg != SCC && opP->reg != AC)) | |
1328 | losing++; | |
1329 | break; | |
1330 | ||
1331 | case 'V': | |
1332 | if (opP->reg != VAL) | |
1333 | losing++; | |
1334 | break; | |
1335 | ||
1336 | case 'W': | |
1337 | if (opP->mode != MSCR || (opP->reg != DRP && opP->reg != SRP && | |
1338 | opP->reg != CRP)) | |
1339 | losing++; | |
1340 | break; | |
1341 | ||
1342 | case 'X': | |
1343 | if (opP->mode != MSCR || | |
1344 | (!(opP->reg >= BAD && opP->reg <= BAD+7) && | |
1345 | !(opP->reg >= BAC && opP->reg <= BAC+7))) | |
1346 | losing++; | |
1347 | break; | |
1348 | ||
1349 | case 'Y': | |
1350 | if (opP->reg != PSR) | |
1351 | losing++; | |
1352 | break; | |
1353 | ||
1354 | case 'Z': | |
1355 | if (opP->reg != PCSR) | |
1356 | losing++; | |
1357 | break; | |
f8701a3f | 1358 | #endif |
6d27d3a2 KR |
1359 | case 'c': |
1360 | if (opP->reg != NC | |
1361 | && opP->reg != IC | |
1362 | && opP->reg != DC | |
1363 | && opP->reg != BC) { | |
1364 | losing++; | |
1365 | } /* not a cache specifier. */ | |
1366 | break; | |
1367 | ||
1368 | case '_': | |
1369 | if (opP->mode != ABSL) { | |
1370 | ++losing; | |
1371 | } /* not absolute */ | |
1372 | break; | |
1373 | ||
1374 | default: | |
1375 | as_fatal("Internal error: Operand mode %c unknown in line %s of file \"%s\"", | |
1376 | *s, __LINE__, __FILE__); | |
1377 | } /* switch on type of operand */ | |
1378 | ||
1379 | if (losing) break; | |
1380 | } /* for each operand */ | |
1381 | } /* if immediately wrong */ | |
1382 | ||
1383 | if (!losing) { | |
1384 | break; | |
1385 | } /* got it. */ | |
1386 | ||
1387 | opcode = opcode->m_next; | |
1388 | ||
1389 | if (!opcode) { | |
1390 | the_ins.error = "instruction/operands mismatch or invalid\n instruction for this architecture"; | |
1391 | return; | |
1392 | } /* Fell off the end */ | |
1393 | ||
1394 | losing = 0; | |
1395 | } | |
1396 | ||
1397 | /* now assemble it */ | |
1398 | ||
1399 | the_ins.args=opcode->m_operands; | |
1400 | the_ins.numargs=opcode->m_opnum; | |
1401 | the_ins.numo=opcode->m_codenum; | |
1402 | the_ins.opcode[0]=getone(opcode); | |
1403 | the_ins.opcode[1]=gettwo(opcode); | |
1404 | ||
1405 | for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++) { | |
1406 | /* This switch is a doozy. | |
1407 | Watch the first step; its a big one! */ | |
1408 | switch(s[0]) { | |
1409 | ||
1410 | case '*': | |
1411 | case '~': | |
1412 | case '%': | |
1413 | case ';': | |
1414 | case '@': | |
1415 | case '!': | |
1416 | case '&': | |
1417 | case '$': | |
1418 | case '?': | |
1419 | case '/': | |
f8701a3f | 1420 | #ifndef NO_68851 |
6d27d3a2 | 1421 | case '|': |
f8701a3f | 1422 | #endif |
6d27d3a2 KR |
1423 | switch(opP->mode) { |
1424 | case IMMED: | |
1425 | tmpreg=0x3c; /* 7.4 */ | |
1426 | if (strchr("bwl",s[1])) nextword=get_num(opP->con1,80); | |
1427 | else nextword=nextword=get_num(opP->con1,0); | |
1428 | if(isvar(opP->con1)) | |
1429 | add_fix(s[1],opP->con1,0); | |
1430 | switch(s[1]) { | |
1431 | case 'b': | |
1432 | if(!isbyte(nextword)) | |
1433 | opP->error="operand out of range"; | |
1434 | addword(nextword); | |
1435 | baseo=0; | |
1436 | break; | |
1437 | case 'w': | |
1438 | if(!isword(nextword)) | |
1439 | opP->error="operand out of range"; | |
1440 | addword(nextword); | |
1441 | baseo=0; | |
1442 | break; | |
1443 | case 'l': | |
1444 | addword(nextword>>16); | |
1445 | addword(nextword); | |
1446 | baseo=0; | |
1447 | break; | |
1448 | ||
1449 | case 'f': | |
1450 | baseo=2; | |
1451 | outro=8; | |
1452 | break; | |
1453 | case 'F': | |
1454 | baseo=4; | |
1455 | outro=11; | |
1456 | break; | |
1457 | case 'x': | |
1458 | baseo=6; | |
1459 | outro=15; | |
1460 | break; | |
1461 | case 'p': | |
1462 | baseo=6; | |
1463 | outro= -1; | |
1464 | break; | |
1465 | default: | |
1466 | as_fatal("Internal error: Can't decode %c%c in line %s of file \"%s\"", | |
1467 | *s, s[1], __LINE__, __FILE__); | |
1468 | } | |
1469 | if(!baseo) | |
1470 | break; | |
1471 | ||
1472 | /* We gotta put out some float */ | |
1473 | if(seg(opP->con1)!=SEG_BIG) { | |
1474 | int_to_gen(nextword); | |
1475 | gen_to_words(words,baseo,(long int)outro); | |
1476 | for(wordp=words;baseo--;wordp++) | |
1477 | addword(*wordp); | |
1478 | break; | |
1479 | } /* Its BIG */ | |
1480 | if(offs(opP->con1)>0) { | |
1481 | as_warn("Bignum assumed to be binary bit-pattern"); | |
1482 | if(offs(opP->con1)>baseo) { | |
1483 | as_warn("Bignum too big for %c format; truncated",s[1]); | |
1484 | offs(opP->con1)=baseo; | |
1485 | } | |
1486 | baseo-=offs(opP->con1); | |
1487 | for(wordp=generic_bignum+offs(opP->con1)-1;offs(opP->con1)--;--wordp) | |
1488 | addword(*wordp); | |
1489 | while(baseo--) | |
1490 | addword(0); | |
1491 | break; | |
1492 | } | |
1493 | gen_to_words(words,baseo,(long)outro); | |
1494 | for (wordp=words;baseo--;wordp++) | |
1495 | addword(*wordp); | |
1496 | break; | |
1497 | case DREG: | |
1498 | tmpreg=opP->reg-DATA; /* 0.dreg */ | |
1499 | break; | |
1500 | case AREG: | |
1501 | tmpreg=0x08+opP->reg-ADDR; /* 1.areg */ | |
1502 | break; | |
1503 | case AINDR: | |
1504 | tmpreg=0x10+opP->reg-ADDR; /* 2.areg */ | |
1505 | break; | |
1506 | case ADEC: | |
1507 | tmpreg=0x20+opP->reg-ADDR; /* 4.areg */ | |
1508 | break; | |
1509 | case AINC: | |
1510 | tmpreg=0x18+opP->reg-ADDR; /* 3.areg */ | |
1511 | break; | |
1512 | case AOFF: | |
1513 | ||
1514 | nextword=get_num(opP->con1,80); | |
1515 | /* Force into index mode. Hope this works */ | |
1516 | ||
1517 | /* We do the first bit for 32-bit displacements, | |
1518 | and the second bit for 16 bit ones. It is | |
1519 | possible that we should make the default be | |
1520 | WORD instead of LONG, but I think that'd | |
1521 | break GCC, so we put up with a little | |
1522 | inefficiency for the sake of working output. | |
1523 | */ | |
1524 | ||
1525 | if( !issword(nextword) | |
1526 | || ( isvar(opP->con1) | |
1527 | && ( ( opP->con1->e_siz==0 | |
1528 | && flagseen['l']==0) | |
1529 | || opP->con1->e_siz==3))) { | |
1530 | ||
1531 | if(opP->reg==PC) | |
1532 | tmpreg=0x3B; /* 7.3 */ | |
1533 | else | |
1534 | tmpreg=0x30+opP->reg-ADDR; /* 6.areg */ | |
1535 | if(isvar(opP->con1)) { | |
1536 | if(opP->reg==PC) { | |
1537 | add_frag(adds(opP->con1), | |
1538 | offs(opP->con1), | |
1539 | TAB(PCLEA,SZ_UNDEF)); | |
1540 | break; | |
1541 | } else { | |
1542 | addword(0x0170); | |
1543 | add_fix('l',opP->con1,1); | |
1544 | } | |
1545 | } else | |
1546 | addword(0x0170); | |
1547 | addword(nextword>>16); | |
1548 | } else { | |
1549 | if(opP->reg==PC) | |
1550 | tmpreg=0x3A; /* 7.2 */ | |
1551 | else | |
1552 | tmpreg=0x28+opP->reg-ADDR; /* 5.areg */ | |
1553 | ||
1554 | if(isvar(opP->con1)) { | |
1555 | if(opP->reg==PC) { | |
1556 | add_fix('w',opP->con1,1); | |
1557 | } else | |
1558 | add_fix('w',opP->con1,0); | |
1559 | } | |
1560 | } | |
1561 | addword(nextword); | |
1562 | break; | |
1563 | ||
1564 | case APODX: | |
1565 | case AMIND: | |
1566 | case APRDX: | |
1567 | know(current_architecture & m68020up); | |
1568 | /* intentional fall-through */ | |
1569 | case AINDX: | |
1570 | nextword=0; | |
1571 | baseo=get_num(opP->con1,80); | |
1572 | outro=get_num(opP->con2,80); | |
1573 | /* Figure out the 'addressing mode' */ | |
1574 | /* Also turn on the BASE_DISABLE bit, if needed */ | |
1575 | if(opP->reg==PC || opP->reg==ZPC) { | |
1576 | tmpreg=0x3b; /* 7.3 */ | |
1577 | if(opP->reg==ZPC) | |
1578 | nextword|=0x80; | |
1579 | } else if(opP->reg==FAIL) { | |
1580 | nextword|=0x80; | |
1581 | tmpreg=0x30; /* 6.garbage */ | |
1582 | } else tmpreg=0x30+opP->reg-ADDR; /* 6.areg */ | |
1583 | ||
1584 | siz1= (opP->con1) ? opP->con1->e_siz : 0; | |
1585 | siz2= (opP->con2) ? opP->con2->e_siz : 0; | |
1586 | ||
1587 | /* Index register stuff */ | |
1588 | if(opP->ireg>=DATA+0 && opP->ireg<=ADDR+7) { | |
1589 | nextword|=(opP->ireg-DATA)<<12; | |
1590 | ||
1591 | if(opP->isiz==0 || opP->isiz==3) | |
1592 | nextword|=0x800; | |
1593 | switch(opP->imul) { | |
1594 | case 1: break; | |
1595 | case 2: nextword|=0x200; break; | |
1596 | case 4: nextword|=0x400; break; | |
1597 | case 8: nextword|=0x600; break; | |
1598 | default: as_fatal("failed sanity check."); | |
1599 | } | |
1600 | /* IF its simple, | |
1601 | GET US OUT OF HERE! */ | |
1602 | ||
1603 | /* Must be INDEX, with an index | |
1604 | register. Address register | |
1605 | cannot be ZERO-PC, and either | |
1606 | :b was forced, or we know | |
1607 | it will fit */ | |
1608 | if( opP->mode==AINDX | |
1609 | && opP->reg!=FAIL | |
1610 | && opP->reg!=ZPC | |
1611 | && ( siz1==1 | |
1612 | || ( issbyte(baseo) | |
1613 | && !isvar(opP->con1)))) { | |
1614 | nextword +=baseo&0xff; | |
1615 | addword(nextword); | |
1616 | if(isvar(opP->con1)) | |
1617 | add_fix('B',opP->con1,0); | |
1618 | break; | |
1619 | } | |
1620 | } else | |
1621 | nextword|=0x40; /* No index reg */ | |
1622 | ||
1623 | /* It aint simple */ | |
1624 | nextword|=0x100; | |
1625 | /* If the guy specified a width, we assume that | |
1626 | it is wide enough. Maybe it isn't. If so, we lose | |
1627 | */ | |
1628 | switch(siz1) { | |
1629 | case 0: | |
1630 | if(isvar(opP->con1) || !issword(baseo)) { | |
1631 | siz1=3; | |
1632 | nextword|=0x30; | |
1633 | } else if(baseo==0) | |
1634 | nextword|=0x10; | |
1635 | else { | |
1636 | nextword|=0x20; | |
1637 | siz1=2; | |
1638 | } | |
1639 | break; | |
1640 | case 1: | |
1641 | as_warn("Byte dispacement won't work. Defaulting to :w"); | |
1642 | case 2: | |
1643 | nextword|=0x20; | |
1644 | break; | |
1645 | case 3: | |
1646 | nextword|=0x30; | |
1647 | break; | |
1648 | } | |
1649 | ||
1650 | /* Figure out innner displacement stuff */ | |
1651 | if(opP->mode!=AINDX) { | |
1652 | switch(siz2) { | |
1653 | case 0: | |
1654 | if(isvar(opP->con2) || !issword(outro)) { | |
1655 | siz2=3; | |
1656 | nextword|=0x3; | |
1657 | } else if(outro==0) | |
1658 | nextword|=0x1; | |
1659 | else { | |
1660 | nextword|=0x2; | |
1661 | siz2=2; | |
1662 | } | |
1663 | break; | |
1664 | case 1: | |
1665 | as_warn("Byte dispacement won't work. Defaulting to :w"); | |
1666 | case 2: | |
1667 | nextword|=0x2; | |
1668 | break; | |
1669 | case 3: | |
1670 | nextword|=0x3; | |
1671 | break; | |
1672 | } | |
1673 | if(opP->mode==APODX) nextword|=0x04; | |
1674 | else if(opP->mode==AMIND) nextword|=0x40; | |
1675 | } | |
1676 | addword(nextword); | |
1677 | ||
1678 | if(isvar(opP->con1)) { | |
1679 | if(opP->reg==PC || opP->reg==ZPC) { | |
1680 | add_fix(siz1==3 ? 'l' : 'w',opP->con1,1); | |
1681 | opP->con1->e_exp.X_add_number+=6; | |
1682 | } else | |
1683 | add_fix(siz1==3 ? 'l' : 'w',opP->con1,0); | |
1684 | } | |
1685 | if(siz1==3) | |
1686 | addword(baseo>>16); | |
1687 | if(siz1) | |
1688 | addword(baseo); | |
1689 | ||
1690 | if(isvar(opP->con2)) { | |
1691 | if(opP->reg==PC || opP->reg==ZPC) { | |
1692 | add_fix(siz2==3 ? 'l' : 'w',opP->con2,1); | |
1693 | opP->con1->e_exp.X_add_number+=6; | |
1694 | } else | |
1695 | add_fix(siz2==3 ? 'l' : 'w',opP->con2,0); | |
1696 | } | |
1697 | if(siz2==3) | |
1698 | addword(outro>>16); | |
1699 | if(siz2) | |
1700 | addword(outro); | |
1701 | ||
1702 | break; | |
1703 | ||
1704 | case ABSL: | |
1705 | nextword=get_num(opP->con1,80); | |
1706 | switch(opP->con1->e_siz) { | |
1707 | default: | |
1708 | as_warn("Unknown size for absolute reference"); | |
1709 | case 0: | |
1710 | if(!isvar(opP->con1) && issword(offs(opP->con1))) { | |
1711 | tmpreg=0x38; /* 7.0 */ | |
1712 | addword(nextword); | |
1713 | break; | |
1714 | } | |
1715 | /* Don't generate pc relative code | |
1716 | on 68010 and 68000 */ | |
1717 | if(isvar(opP->con1) | |
1718 | && !subs(opP->con1) | |
1719 | && seg(opP->con1) == SEG_TEXT | |
1720 | && now_seg == SEG_TEXT | |
1721 | && cpu_of_arch(current_architecture) >= m68020 | |
1722 | && !flagseen['S'] | |
1723 | && !strchr("~%&$?", s[0])) { | |
1724 | tmpreg=0x3A; /* 7.2 */ | |
1725 | add_frag(adds(opP->con1), | |
1726 | offs(opP->con1), | |
1727 | TAB(PCREL,SZ_UNDEF)); | |
1728 | break; | |
1729 | } | |
1730 | case 3: /* Fall through into long */ | |
1731 | if(isvar(opP->con1)) | |
1732 | add_fix('l',opP->con1,0); | |
1733 | ||
1734 | tmpreg=0x39; /* 7.1 mode */ | |
1735 | addword(nextword>>16); | |
1736 | addword(nextword); | |
1737 | break; | |
1738 | ||
1739 | case 2: /* Word */ | |
1740 | if(isvar(opP->con1)) | |
1741 | add_fix('w',opP->con1,0); | |
1742 | ||
1743 | tmpreg=0x38; /* 7.0 mode */ | |
1744 | addword(nextword); | |
1745 | break; | |
1746 | } | |
1747 | break; | |
1748 | case MSCR: | |
1749 | default: | |
1750 | as_bad("unknown/incorrect operand"); | |
1751 | /* abort(); */ | |
1752 | } | |
1753 | install_gen_operand(s[1],tmpreg); | |
1754 | break; | |
1755 | ||
1756 | case '#': | |
1757 | case '^': | |
1758 | switch(s[1]) { /* JF: I hate floating point! */ | |
1759 | case 'j': | |
1760 | tmpreg=70; | |
1761 | break; | |
1762 | case '8': | |
1763 | tmpreg=20; | |
1764 | break; | |
1765 | case 'C': | |
1766 | tmpreg=50; | |
1767 | break; | |
1768 | case '3': | |
1769 | default: | |
1770 | tmpreg=80; | |
1771 | break; | |
1772 | } | |
1773 | tmpreg=get_num(opP->con1,tmpreg); | |
1774 | if(isvar(opP->con1)) | |
1775 | add_fix(s[1],opP->con1,0); | |
1776 | switch(s[1]) { | |
1777 | case 'b': /* Danger: These do no check for | |
1778 | certain types of overflow. | |
1779 | user beware! */ | |
1780 | if(!isbyte(tmpreg)) | |
1781 | opP->error="out of range"; | |
1782 | insop(tmpreg); | |
1783 | if(isvar(opP->con1)) | |
1784 | the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2; | |
1785 | break; | |
1786 | case 'w': | |
1787 | if(!isword(tmpreg)) | |
1788 | opP->error="out of range"; | |
1789 | insop(tmpreg); | |
1790 | if(isvar(opP->con1)) | |
1791 | the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2; | |
1792 | break; | |
1793 | case 'l': | |
1794 | insop(tmpreg); /* Because of the way insop works, we put these two out backwards */ | |
1795 | insop(tmpreg>>16); | |
1796 | if(isvar(opP->con1)) | |
1797 | the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2; | |
1798 | break; | |
1799 | case '3': | |
1800 | tmpreg&=0xFF; | |
1801 | case '8': | |
1802 | case 'C': | |
1803 | install_operand(s[1],tmpreg); | |
1804 | break; | |
1805 | default: | |
1806 | as_fatal("Internal error: Unknown mode #%c in line %s of file \"%s\"", s[1], __LINE__, __FILE__); | |
1807 | } | |
1808 | break; | |
1809 | ||
1810 | case '+': | |
1811 | case '-': | |
1812 | case 'A': | |
1813 | case 'a': | |
1814 | install_operand(s[1],opP->reg-ADDR); | |
1815 | break; | |
1816 | ||
1817 | case 'B': | |
1818 | tmpreg=get_num(opP->con1,80); | |
1819 | switch(s[1]) { | |
1820 | case 'B': | |
1821 | /* Needs no offsetting */ | |
1822 | add_fix('B',opP->con1,1); | |
1823 | break; | |
1824 | case 'W': | |
1825 | /* Offset the displacement to be relative to byte disp location */ | |
1826 | opP->con1->e_exp.X_add_number+=2; | |
1827 | add_fix('w',opP->con1,1); | |
1828 | addword(0); | |
1829 | break; | |
1830 | case 'L': | |
1831 | long_branch: | |
1832 | if (cpu_of_arch(current_architecture) < m68020) /* 68000 or 010 */ | |
1833 | as_warn("Can't use long branches on 68000/68010"); | |
1834 | the_ins.opcode[the_ins.numo-1]|=0xff; | |
1835 | /* Offset the displacement to be relative to byte disp location */ | |
1836 | opP->con1->e_exp.X_add_number+=4; | |
1837 | add_fix('l',opP->con1,1); | |
1838 | addword(0); | |
1839 | addword(0); | |
1840 | break; | |
1841 | case 'g': | |
1842 | if(subs(opP->con1)) /* We can't relax it */ | |
1843 | goto long_branch; | |
1844 | ||
1845 | /* This could either be a symbol, or an | |
1846 | absolute address. No matter, the | |
1847 | frag hacking will finger it out. | |
1848 | Not quite: it can't switch from | |
1849 | BRANCH to BCC68000 for the case | |
1850 | where opnd is absolute (it needs | |
1851 | to use the 68000 hack since no | |
1852 | conditional abs jumps). */ | |
1853 | if (((cpu_of_arch(current_architecture) < m68020) || (0==adds(opP->con1))) | |
1854 | && (the_ins.opcode[0] >= 0x6200) | |
1855 | && (the_ins.opcode[0] <= 0x6f00)) { | |
1856 | add_frag(adds(opP->con1),offs(opP->con1),TAB(BCC68000,SZ_UNDEF)); | |
1857 | } else { | |
1858 | add_frag(adds(opP->con1),offs(opP->con1),TAB(BRANCH,SZ_UNDEF)); | |
1859 | } | |
1860 | break; | |
1861 | case 'w': | |
1862 | if(isvar(opP->con1)) { | |
1863 | /* check for DBcc instruction */ | |
1864 | if ((the_ins.opcode[0] & 0xf0f8) ==0x50c8) { | |
1865 | /* size varies if patch */ | |
1866 | /* needed for long form */ | |
1867 | add_frag(adds(opP->con1),offs(opP->con1),TAB(DBCC,SZ_UNDEF)); | |
1868 | break; | |
1869 | } | |
1870 | ||
1871 | /* Don't ask! */ | |
1872 | opP->con1->e_exp.X_add_number+=2; | |
1873 | add_fix('w',opP->con1,1); | |
1874 | } | |
1875 | addword(0); | |
1876 | break; | |
1877 | case 'C': /* Fixed size LONG coproc branches */ | |
1878 | the_ins.opcode[the_ins.numo-1]|=0x40; | |
1879 | /* Offset the displacement to be relative to byte disp location */ | |
1880 | /* Coproc branches don't have a byte disp option, but they are | |
1881 | compatible with the ordinary branches, which do... */ | |
1882 | opP->con1->e_exp.X_add_number+=4; | |
1883 | add_fix('l',opP->con1,1); | |
1884 | addword(0); | |
1885 | addword(0); | |
1886 | break; | |
1887 | case 'c': /* Var size Coprocesssor branches */ | |
1888 | if(subs(opP->con1)) { | |
1889 | add_fix('l',opP->con1,1); | |
1890 | add_frag((symbolS *)0,(long)0,TAB(FBRANCH,LONG)); | |
1891 | } else if(adds(opP->con1)) { | |
1892 | add_frag(adds(opP->con1),offs(opP->con1),TAB(FBRANCH,SZ_UNDEF)); | |
1893 | } else { | |
1894 | /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */ | |
1895 | the_ins.opcode[the_ins.numo-1]|=0x40; | |
1896 | add_fix('l',opP->con1,1); | |
1897 | addword(0); | |
1898 | addword(4); | |
1899 | } | |
1900 | break; | |
1901 | default: | |
1902 | as_fatal("Internal error: operand type B%c unknown in line %s of file \"%s\"", | |
1903 | s[1], __LINE__, __FILE__); | |
1904 | } | |
1905 | break; | |
1906 | ||
1907 | case 'C': /* Ignore it */ | |
1908 | break; | |
1909 | ||
1910 | case 'd': /* JF this is a kludge */ | |
1911 | if(opP->mode==AOFF) { | |
1912 | install_operand('s',opP->reg-ADDR); | |
1913 | } else { | |
1914 | char *tmpP; | |
1915 | ||
1916 | tmpP=opP->con1->e_end-2; | |
1917 | opP->con1->e_beg++; | |
1918 | opP->con1->e_end-=4; /* point to the , */ | |
1919 | baseo=m68k_reg_parse(&tmpP); | |
1920 | if(baseo<ADDR+0 || baseo>ADDR+7) { | |
1921 | as_bad("Unknown address reg, using A0"); | |
1922 | baseo=0; | |
1923 | } else baseo-=ADDR; | |
1924 | install_operand('s',baseo); | |
1925 | } | |
1926 | tmpreg=get_num(opP->con1,80); | |
1927 | if(!issword(tmpreg)) { | |
1928 | as_warn("Expression out of range, using 0"); | |
1929 | tmpreg=0; | |
1930 | } | |
1931 | addword(tmpreg); | |
1932 | break; | |
1933 | ||
1934 | case 'D': | |
1935 | install_operand(s[1],opP->reg-DATA); | |
1936 | break; | |
1937 | ||
1938 | case 'F': | |
1939 | install_operand(s[1],opP->reg-FPREG); | |
1940 | break; | |
1941 | ||
1942 | case 'I': | |
1943 | tmpreg=1+opP->reg-COPNUM; | |
1944 | if(tmpreg==8) | |
1945 | tmpreg=0; | |
1946 | install_operand(s[1],tmpreg); | |
1947 | break; | |
1948 | ||
1949 | case 'J': /* JF foo */ | |
1950 | switch(opP->reg) { | |
1951 | case SFC: tmpreg=0x000; break; | |
1952 | case DFC: tmpreg=0x001; break; | |
1953 | case CACR: tmpreg=0x002; break; | |
1954 | case TC: tmpreg=0x003; break; | |
1955 | case ITT0: tmpreg=0x004; break; | |
1956 | case ITT1: tmpreg=0x005; break; | |
1957 | case DTT0: tmpreg=0x006; break; | |
1958 | case DTT1: tmpreg=0x007; break; | |
1959 | ||
1960 | case USP: tmpreg=0x800; break; | |
1961 | case VBR: tmpreg=0x801; break; | |
1962 | case CAAR: tmpreg=0x802; break; | |
1963 | case MSP: tmpreg=0x803; break; | |
1964 | case ISP: tmpreg=0x804; break; | |
1965 | case MMUSR: tmpreg=0x805; break; | |
1966 | case URP: tmpreg=0x806; break; | |
1967 | case SRP: tmpreg=0x807; break; | |
1968 | default: | |
1969 | as_fatal("failed sanity check."); | |
1970 | } | |
1971 | install_operand(s[1],tmpreg); | |
1972 | break; | |
1973 | ||
1974 | case 'k': | |
1975 | tmpreg=get_num(opP->con1,55); | |
1976 | install_operand(s[1],tmpreg&0x7f); | |
1977 | break; | |
1978 | ||
1979 | case 'l': | |
1980 | tmpreg=opP->reg; | |
1981 | if(s[1]=='w') { | |
1982 | if(tmpreg&0x7FF0000) | |
1983 | as_bad("Floating point register in register list"); | |
1984 | insop(reverse_16_bits(tmpreg)); | |
1985 | } else { | |
1986 | if(tmpreg&0x700FFFF) | |
1987 | as_bad("Wrong register in floating-point reglist"); | |
1988 | install_operand(s[1],reverse_8_bits(tmpreg>>16)); | |
1989 | } | |
1990 | break; | |
1991 | ||
1992 | case 'L': | |
1993 | tmpreg=opP->reg; | |
1994 | if(s[1]=='w') { | |
1995 | if(tmpreg&0x7FF0000) | |
1996 | as_bad("Floating point register in register list"); | |
1997 | insop(tmpreg); | |
1998 | } else if(s[1]=='8') { | |
1999 | if(tmpreg&0x0FFFFFF) | |
2000 | as_bad("incorrect register in reglist"); | |
2001 | install_operand(s[1],tmpreg>>24); | |
2002 | } else { | |
2003 | if(tmpreg&0x700FFFF) | |
2004 | as_bad("wrong register in floating-point reglist"); | |
2005 | else | |
2006 | install_operand(s[1],tmpreg>>16); | |
2007 | } | |
2008 | break; | |
2009 | ||
2010 | case 'M': | |
2011 | install_operand(s[1],get_num(opP->con1,60)); | |
2012 | break; | |
2013 | ||
2014 | case 'O': | |
2015 | tmpreg= (opP->mode==DREG) | |
2016 | ? 0x20+opP->reg-DATA | |
2017 | : (get_num(opP->con1,40)&0x1F); | |
2018 | install_operand(s[1],tmpreg); | |
2019 | break; | |
2020 | ||
2021 | case 'Q': | |
2022 | tmpreg=get_num(opP->con1,10); | |
2023 | if(tmpreg==8) | |
2024 | tmpreg=0; | |
2025 | install_operand(s[1],tmpreg); | |
2026 | break; | |
2027 | ||
2028 | case 'R': | |
2029 | /* This depends on the fact that ADDR registers are | |
2030 | eight more than their corresponding DATA regs, so | |
2031 | the result will have the ADDR_REG bit set */ | |
2032 | install_operand(s[1],opP->reg-DATA); | |
2033 | break; | |
2034 | ||
2035 | case 's': | |
2036 | if(opP->reg==FPI) tmpreg=0x1; | |
2037 | else if(opP->reg==FPS) tmpreg=0x2; | |
2038 | else if(opP->reg==FPC) tmpreg=0x4; | |
2039 | else as_fatal("failed sanity check."); | |
2040 | install_operand(s[1],tmpreg); | |
2041 | break; | |
2042 | ||
2043 | case 'S': /* Ignore it */ | |
2044 | break; | |
2045 | ||
2046 | case 'T': | |
2047 | install_operand(s[1],get_num(opP->con1,30)); | |
2048 | break; | |
2049 | ||
2050 | case 'U': /* Ignore it */ | |
2051 | break; | |
2052 | ||
2053 | case 'c': | |
2054 | switch (opP->reg) { | |
2055 | case NC: tmpreg = 0; break; | |
2056 | case DC: tmpreg = 1; break; | |
2057 | case IC: tmpreg = 2; break; | |
2058 | case BC: tmpreg = 3; break; | |
2059 | default: | |
2060 | as_fatal("failed sanity check"); | |
2061 | } /* switch on cache token */ | |
2062 | install_operand(s[1], tmpreg); | |
2063 | break; | |
a39116f1 | 2064 | #ifndef NO_68851 |
6d27d3a2 KR |
2065 | /* JF: These are out of order, I fear. */ |
2066 | case 'f': | |
2067 | switch (opP->reg) { | |
2068 | case SFC: | |
2069 | tmpreg=0; | |
2070 | break; | |
2071 | case DFC: | |
2072 | tmpreg=1; | |
2073 | break; | |
2074 | default: | |
2075 | as_fatal("failed sanity check."); | |
2076 | } | |
2077 | install_operand(s[1],tmpreg); | |
2078 | break; | |
2079 | ||
2080 | case 'P': | |
2081 | switch(opP->reg) { | |
2082 | case TC: | |
2083 | tmpreg=0; | |
2084 | break; | |
2085 | case CAL: | |
2086 | tmpreg=4; | |
2087 | break; | |
2088 | case VAL: | |
2089 | tmpreg=5; | |
2090 | break; | |
2091 | case SCC: | |
2092 | tmpreg=6; | |
2093 | break; | |
2094 | case AC: | |
2095 | tmpreg=7; | |
2096 | break; | |
2097 | default: | |
2098 | as_fatal("failed sanity check."); | |
2099 | } | |
2100 | install_operand(s[1],tmpreg); | |
2101 | break; | |
2102 | ||
2103 | case 'V': | |
2104 | if (opP->reg == VAL) | |
2105 | break; | |
2106 | as_fatal("failed sanity check."); | |
2107 | ||
2108 | case 'W': | |
2109 | switch(opP->reg) { | |
2110 | ||
2111 | case DRP: | |
2112 | tmpreg=1; | |
2113 | break; | |
2114 | case SRP: | |
2115 | tmpreg=2; | |
2116 | break; | |
2117 | case CRP: | |
2118 | tmpreg=3; | |
2119 | break; | |
2120 | default: | |
2121 | as_fatal("failed sanity check."); | |
2122 | } | |
2123 | install_operand(s[1],tmpreg); | |
2124 | break; | |
2125 | ||
2126 | case 'X': | |
2127 | switch (opP->reg) { | |
2128 | case BAD: case BAD+1: case BAD+2: case BAD+3: | |
2129 | case BAD+4: case BAD+5: case BAD+6: case BAD+7: | |
2130 | tmpreg = (4 << 10) | ((opP->reg - BAD) << 2); | |
2131 | break; | |
2132 | ||
2133 | case BAC: case BAC+1: case BAC+2: case BAC+3: | |
2134 | case BAC+4: case BAC+5: case BAC+6: case BAC+7: | |
2135 | tmpreg = (5 << 10) | ((opP->reg - BAC) << 2); | |
2136 | break; | |
2137 | ||
2138 | default: | |
2139 | as_fatal("failed sanity check."); | |
2140 | } | |
2141 | install_operand(s[1], tmpreg); | |
2142 | break; | |
2143 | case 'Y': | |
2144 | know(opP->reg == PSR); | |
2145 | break; | |
2146 | case 'Z': | |
2147 | know(opP->reg == PCSR); | |
2148 | break; | |
f8701a3f | 2149 | #endif /* m68851 */ |
6d27d3a2 KR |
2150 | case '_': |
2151 | tmpreg=get_num(opP->con1,80); | |
2152 | install_operand(s[1], tmpreg); | |
2153 | break; | |
2154 | default: | |
2155 | as_fatal("Internal error: Operand type %c unknown in line %s of file \"%s\"", s[0], __LINE__, __FILE__); | |
2156 | } | |
2157 | } | |
2158 | /* By the time whe get here (FINALLY) the_ins contains the complete | |
2159 | instruction, ready to be emitted. . . */ | |
7c15cbe8 RP |
2160 | } /* m68k_ip() */ |
2161 | ||
2162 | /* | |
2163 | * get_regs := '/' + ? | |
2164 | * | '-' + <register> | |
2165 | * | '-' + <register> + ? | |
2166 | * | <empty> | |
2167 | * ; | |
2168 | * | |
6d27d3a2 | 2169 | |
7c15cbe8 RP |
2170 | * The idea here must be to scan in a set of registers but I don't |
2171 | * understand it. Looks awfully sloppy to me but I don't have any doc on | |
2172 | * this format so... | |
6d27d3a2 KR |
2173 | |
2174 | * | |
7c15cbe8 RP |
2175 | * |
2176 | */ | |
fecd2382 RP |
2177 | |
2178 | static int get_regs(i,str,opP) | |
f8701a3f SC |
2179 | int i; |
2180 | struct m68k_op *opP; | |
2181 | char *str; | |
fecd2382 | 2182 | { |
f8701a3f SC |
2183 | /* 26, 25, 24, 23-16, 15-8, 0-7 */ |
2184 | /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */ | |
2185 | unsigned long cur_regs = 0; | |
2186 | int reg1, | |
2187 | reg2; | |
6d27d3a2 | 2188 | |
fecd2382 | 2189 | #define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\ |
a39116f1 RP |
2190 | else if(x==FPS) cur_regs|=(1<<25);\ |
2191 | else if(x==FPC) cur_regs|=(1<<26);\ | |
2192 | else cur_regs|=(1<<(x-1)); } | |
6d27d3a2 | 2193 | |
f8701a3f SC |
2194 | reg1=i; |
2195 | for(;;) { | |
2196 | if(*str=='/') { | |
2197 | ADD_REG(reg1); | |
2198 | str++; | |
2199 | } else if(*str=='-') { | |
2200 | str++; | |
2201 | reg2=m68k_reg_parse(&str); | |
2202 | if(reg2<DATA || reg2>=FPREG+8 || reg1==FPI || reg1==FPS || reg1==FPC) { | |
2203 | opP->error="unknown register in register list"; | |
2204 | return FAIL; | |
2205 | } | |
2206 | while(reg1<=reg2) { | |
2207 | ADD_REG(reg1); | |
2208 | reg1++; | |
2209 | } | |
2210 | if(*str=='\0') | |
2211 | break; | |
2212 | } else if(*str=='\0') { | |
2213 | ADD_REG(reg1); | |
2214 | break; | |
2215 | } else { | |
2216 | opP->error="unknow character in register list"; | |
2217 | return FAIL; | |
2218 | } | |
2219 | /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */ | |
2220 | if (*str=='/') | |
2221 | str ++; | |
2222 | reg1=m68k_reg_parse(&str); | |
2223 | if((reg1<DATA || reg1>=FPREG+8) && !(reg1==FPI || reg1==FPS || reg1==FPC)) { | |
2224 | opP->error="unknown register in register list"; | |
2225 | return FAIL; | |
2226 | } | |
a39116f1 | 2227 | } |
f8701a3f SC |
2228 | opP->reg=cur_regs; |
2229 | return OK; | |
fecd2382 RP |
2230 | } /* get_regs() */ |
2231 | ||
2232 | static int reverse_16_bits(in) | |
f8701a3f | 2233 | int in; |
fecd2382 | 2234 | { |
f8701a3f SC |
2235 | int out=0; |
2236 | int n; | |
6d27d3a2 | 2237 | |
f8701a3f SC |
2238 | static int mask[16] = { |
2239 | 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080, | |
2240 | 0x0100,0x0200,0x0400,0x0800,0x1000,0x2000,0x4000,0x8000 | |
2241 | }; | |
2242 | for(n=0;n<16;n++) { | |
2243 | if(in&mask[n]) | |
2244 | out|=mask[15-n]; | |
2245 | } | |
2246 | return out; | |
fecd2382 RP |
2247 | } /* reverse_16_bits() */ |
2248 | ||
2249 | static int reverse_8_bits(in) | |
f8701a3f | 2250 | int in; |
fecd2382 | 2251 | { |
f8701a3f SC |
2252 | int out=0; |
2253 | int n; | |
6d27d3a2 | 2254 | |
f8701a3f SC |
2255 | static int mask[8] = { |
2256 | 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080, | |
2257 | }; | |
6d27d3a2 | 2258 | |
f8701a3f SC |
2259 | for(n=0;n<8;n++) { |
2260 | if(in&mask[n]) | |
2261 | out|=mask[7-n]; | |
2262 | } | |
2263 | return out; | |
fecd2382 RP |
2264 | } /* reverse_8_bits() */ |
2265 | ||
2266 | static void install_operand(mode,val) | |
f8701a3f SC |
2267 | int mode; |
2268 | int val; | |
fecd2382 | 2269 | { |
f8701a3f SC |
2270 | switch(mode) { |
2271 | case 's': | |
2272 | the_ins.opcode[0]|=val & 0xFF; /* JF FF is for M kludge */ | |
2273 | break; | |
2274 | case 'd': | |
2275 | the_ins.opcode[0]|=val<<9; | |
2276 | break; | |
2277 | case '1': | |
2278 | the_ins.opcode[1]|=val<<12; | |
2279 | break; | |
2280 | case '2': | |
2281 | the_ins.opcode[1]|=val<<6; | |
2282 | break; | |
2283 | case '3': | |
2284 | the_ins.opcode[1]|=val; | |
2285 | break; | |
2286 | case '4': | |
2287 | the_ins.opcode[2]|=val<<12; | |
2288 | break; | |
2289 | case '5': | |
2290 | the_ins.opcode[2]|=val<<6; | |
2291 | break; | |
2292 | case '6': | |
2293 | /* DANGER! This is a hack to force cas2l and cas2w cmds | |
2294 | to be three words long! */ | |
2295 | the_ins.numo++; | |
2296 | the_ins.opcode[2]|=val; | |
2297 | break; | |
2298 | case '7': | |
2299 | the_ins.opcode[1]|=val<<7; | |
2300 | break; | |
2301 | case '8': | |
2302 | the_ins.opcode[1]|=val<<10; | |
2303 | break; | |
2304 | #ifndef NO_68851 | |
2305 | case '9': | |
2306 | the_ins.opcode[1]|=val<<5; | |
2307 | break; | |
2308 | #endif | |
6d27d3a2 | 2309 | |
f8701a3f SC |
2310 | case 't': |
2311 | the_ins.opcode[1]|=(val<<10)|(val<<7); | |
2312 | break; | |
2313 | case 'D': | |
2314 | the_ins.opcode[1]|=(val<<12)|val; | |
2315 | break; | |
2316 | case 'g': | |
2317 | the_ins.opcode[0]|=val=0xff; | |
2318 | break; | |
2319 | case 'i': | |
2320 | the_ins.opcode[0]|=val<<9; | |
2321 | break; | |
2322 | case 'C': | |
2323 | the_ins.opcode[1]|=val; | |
2324 | break; | |
2325 | case 'j': | |
2326 | the_ins.opcode[1]|=val; | |
2327 | the_ins.numo++; /* What a hack */ | |
2328 | break; | |
2329 | case 'k': | |
2330 | the_ins.opcode[1]|=val<<4; | |
2331 | break; | |
2332 | case 'b': | |
2333 | case 'w': | |
2334 | case 'l': | |
2335 | break; | |
2336 | case 'e': | |
2337 | the_ins.opcode[0] |= (val << 6); | |
2338 | break; | |
2339 | case 'L': | |
2340 | the_ins.opcode[1] = (val >> 16); | |
2341 | the_ins.opcode[2] = val & 0xffff; | |
2342 | break; | |
2343 | case 'c': | |
2344 | default: | |
2345 | as_fatal("failed sanity check."); | |
2346 | } | |
fecd2382 RP |
2347 | } /* install_operand() */ |
2348 | ||
2349 | static void install_gen_operand(mode,val) | |
f8701a3f SC |
2350 | int mode; |
2351 | int val; | |
fecd2382 | 2352 | { |
f8701a3f SC |
2353 | switch(mode) { |
2354 | case 's': | |
2355 | the_ins.opcode[0]|=val; | |
2356 | break; | |
2357 | case 'd': | |
2358 | /* This is a kludge!!! */ | |
2359 | the_ins.opcode[0]|=(val&0x07)<<9|(val&0x38)<<3; | |
2360 | break; | |
2361 | case 'b': | |
2362 | case 'w': | |
2363 | case 'l': | |
2364 | case 'f': | |
2365 | case 'F': | |
2366 | case 'x': | |
2367 | case 'p': | |
2368 | the_ins.opcode[0]|=val; | |
2369 | break; | |
2370 | /* more stuff goes here */ | |
2371 | default: | |
2372 | as_fatal("failed sanity check."); | |
2373 | } | |
fecd2382 RP |
2374 | } /* install_gen_operand() */ |
2375 | ||
7c15cbe8 RP |
2376 | /* |
2377 | * verify that we have some number of paren pairs, do m68k_ip_op(), and | |
2378 | * then deal with the bitfield hack. | |
2379 | */ | |
2380 | ||
fecd2382 | 2381 | static char *crack_operand(str,opP) |
f8701a3f SC |
2382 | register char *str; |
2383 | register struct m68k_op *opP; | |
fecd2382 | 2384 | { |
f8701a3f SC |
2385 | register int parens; |
2386 | register int c; | |
2387 | register char *beg_str; | |
6d27d3a2 | 2388 | |
f8701a3f SC |
2389 | if(!str) { |
2390 | return str; | |
2391 | } | |
2392 | beg_str=str; | |
2393 | for(parens=0;*str && (parens>0 || notend(str));str++) { | |
2394 | if(*str=='(') parens++; | |
2395 | else if(*str==')') { | |
2396 | if(!parens) { /* ERROR */ | |
2397 | opP->error="Extra )"; | |
2398 | return str; | |
2399 | } | |
2400 | --parens; | |
2401 | } | |
2402 | } | |
2403 | if(!*str && parens) { /* ERROR */ | |
2404 | opP->error="Missing )"; | |
2405 | return str; | |
2406 | } | |
2407 | c= *str; | |
2408 | *str='\0'; | |
2409 | if(m68k_ip_op(beg_str,opP)==FAIL) { | |
2410 | *str=c; | |
fecd2382 RP |
2411 | return str; |
2412 | } | |
2413 | *str=c; | |
f8701a3f SC |
2414 | if(c=='}') |
2415 | c= *++str; /* JF bitfield hack */ | |
2416 | if(c) { | |
2417 | c= *++str; | |
2418 | if(!c) | |
2419 | as_bad("Missing operand"); | |
2420 | } | |
fecd2382 RP |
2421 | return str; |
2422 | } | |
2423 | ||
2424 | /* See the comment up above where the #define notend(... is */ | |
2425 | #if 0 | |
2426 | notend(s) | |
f8701a3f | 2427 | char *s; |
fecd2382 | 2428 | { |
f8701a3f SC |
2429 | if(*s==',') return 0; |
2430 | if(*s=='{' || *s=='}') | |
2431 | return 0; | |
2432 | if(*s!=':') return 1; | |
2433 | /* This kludge here is for the division cmd, which is a kludge */ | |
2434 | if(index("aAdD#",s[1])) return 0; | |
2435 | return 1; | |
fecd2382 RP |
2436 | } |
2437 | #endif | |
2438 | ||
2439 | /* This is the guts of the machine-dependent assembler. STR points to a | |
7c15cbe8 | 2440 | machine dependent instruction. This function is supposed to emit |
fecd2382 | 2441 | the frags/bytes it assembles to. |
a39116f1 | 2442 | */ |
a933d598 SC |
2443 | |
2444 | void | |
2445 | insert_reg(regname, regnum) | |
2446 | char *regname; | |
2447 | int regnum; | |
2448 | { | |
2449 | char buf[100]; | |
2450 | int i; | |
2451 | symbol_table_insert(symbol_new(regname, SEG_REGISTER, regnum, &zero_address_frag)); | |
2452 | ||
2453 | for (i = 0; regname[i]; i++) | |
2454 | buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i]; | |
2455 | buf[i] = '\0'; | |
6d27d3a2 | 2456 | |
a933d598 SC |
2457 | symbol_table_insert(symbol_new(buf, SEG_REGISTER, regnum, &zero_address_frag)); |
2458 | } | |
2459 | ||
2460 | static struct { | |
6d27d3a2 | 2461 | char *name; |
a933d598 | 2462 | int number; |
6d27d3a2 | 2463 | } init_table[] = |
a933d598 SC |
2464 | { |
2465 | "d0", DATA0, | |
2466 | "d1", DATA1, | |
2467 | "d2", DATA2, | |
2468 | "d3", DATA3, | |
2469 | "d4", DATA4, | |
2470 | "d5", DATA5, | |
2471 | "d6", DATA6, | |
2472 | "d7", DATA7, | |
2473 | "a0", ADDR0, | |
2474 | "a1", ADDR1, | |
2475 | "a2", ADDR2, | |
2476 | "a3", ADDR3, | |
2477 | "a4", ADDR4, | |
2478 | "a5", ADDR5, | |
2479 | "a6", ADDR6, | |
2480 | "fp", ADDR6, | |
2481 | "a7", ADDR7, | |
2482 | "sp", ADDR7, | |
2483 | "fp0", FP0, | |
2484 | "fp1", FP1, | |
2485 | "fp2", FP2, | |
2486 | "fp3", FP3, | |
2487 | "fp4", FP4, | |
2488 | "fp5", FP5, | |
2489 | "fp6", FP6, | |
2490 | "fp7", FP7, | |
2491 | "fpi", FPI, | |
2492 | "fpiar", FPI, | |
2493 | "fpc", FPI, | |
2494 | "fps", FPS, | |
2495 | "fpsr", FPS, | |
2496 | "fpc", FPC, | |
2497 | "fpcr", FPC, | |
2498 | ||
2499 | "cop0", COP0, | |
2500 | "cop1", COP1, | |
2501 | "cop2", COP2, | |
2502 | "cop3", COP3, | |
2503 | "cop4", COP4, | |
2504 | "cop5", COP5, | |
2505 | "cop6", COP6, | |
2506 | "cop7", COP7, | |
6d27d3a2 KR |
2507 | "pc", PC, |
2508 | "zpc", ZPC, | |
2509 | "sr", SR, | |
a933d598 | 2510 | |
6d27d3a2 KR |
2511 | "ccr", CCR, |
2512 | "cc", CCR, | |
a933d598 | 2513 | |
6d27d3a2 KR |
2514 | "usp", USP, |
2515 | "isp", ISP, | |
a933d598 SC |
2516 | "sfc", SFC, |
2517 | "dfc", DFC, | |
2518 | "cacr", CACR, | |
2519 | "caar", CAAR, | |
2520 | ||
2521 | "vbr", VBR, | |
2522 | ||
2523 | "msp", MSP, | |
2524 | "itt0", ITT0, | |
2525 | "itt1", ITT1, | |
2526 | "dtt0", DTT0, | |
2527 | "dtt1", DTT1, | |
2528 | "mmusr", MMUSR, | |
2529 | "tc", TC, | |
2530 | "srp", SRP, | |
2531 | "urp", URP, | |
2532 | ||
2533 | #ifndef NO_68851 | |
2534 | "ac", AC, | |
2535 | "bc", BC, | |
2536 | "cal", CAL, | |
2537 | "crp", CRP, | |
2538 | "drp", DRP, | |
2539 | "pcsr", PCSR, | |
2540 | "psr", PSR, | |
2541 | "scc", SCC, | |
2542 | "val", VAL, | |
2543 | "bad0", BAD0, | |
2544 | "bad1", BAD1, | |
2545 | "bad2", BAD2, | |
2546 | "bad3", BAD3, | |
2547 | "bad4", BAD4, | |
2548 | "bad5", BAD5, | |
2549 | "bad6", BAD6, | |
2550 | "bad7", BAD7, | |
2551 | "bac0", BAC0, | |
2552 | "bac1", BAC1, | |
2553 | "bac2", BAC2, | |
2554 | "bac3", BAC3, | |
2555 | "bac4", BAC4, | |
2556 | "bac5", BAC5, | |
2557 | "bac6", BAC6, | |
2558 | "bac7", BAC7, | |
2559 | #endif | |
2560 | ||
2561 | "ic", IC, | |
2562 | "dc", DC, | |
2563 | "nc", NC, | |
2564 | ||
2565 | 0, | |
2566 | ||
2567 | }; | |
2568 | ||
2569 | ||
2570 | void | |
2571 | init_regtable() | |
2572 | { | |
2573 | int i; | |
6d27d3a2 | 2574 | for (i = 0; init_table[i].name; i++) |
a933d598 SC |
2575 | { |
2576 | insert_reg(init_table[i].name, init_table[i].number); | |
2577 | } | |
2578 | } | |
6d27d3a2 | 2579 | |
a933d598 | 2580 | |
fecd2382 | 2581 | void |
6d27d3a2 KR |
2582 | md_assemble(str) |
2583 | char *str; | |
fecd2382 | 2584 | { |
f8701a3f SC |
2585 | char *er; |
2586 | short *fromP; | |
2587 | char *toP = NULL; | |
2588 | int m,n = 0; | |
2589 | char *to_beg_P; | |
2590 | int shorts_this_frag; | |
6d27d3a2 KR |
2591 | |
2592 | ||
2593 | if (current_architecture == 0) | |
2594 | current_architecture = (m68020 | |
865a2edf | 2595 | #ifndef NO_68881 |
6d27d3a2 | 2596 | | m68881 |
865a2edf MT |
2597 | #endif |
2598 | #ifndef NO_68851 | |
6d27d3a2 | 2599 | | m68851 |
865a2edf | 2600 | #endif |
6d27d3a2 KR |
2601 | ); |
2602 | /* If only float and mmu were specified, default cpu. */ | |
2603 | else if (cpu_of_arch (current_architecture) == 0) | |
2604 | current_architecture |= m68020; | |
2605 | ||
f8701a3f SC |
2606 | memset((char *)(&the_ins), '\0', sizeof(the_ins)); /* JF for paranoia sake */ |
2607 | m68k_ip(str); | |
2608 | er=the_ins.error; | |
2609 | if(!er) { | |
2610 | for(n=the_ins.numargs;n;--n) | |
2611 | if(the_ins.operands[n].error) { | |
2612 | er=the_ins.operands[n].error; | |
2613 | break; | |
2614 | } | |
fecd2382 | 2615 | } |
f8701a3f | 2616 | if(er) { |
6d27d3a2 | 2617 | as_bad("%s -- statement `%s' ignored",er,str); |
f8701a3f | 2618 | return; |
fecd2382 | 2619 | } |
6d27d3a2 | 2620 | |
f8701a3f SC |
2621 | if(the_ins.nfrag==0) { /* No frag hacking involved; just put it out */ |
2622 | toP=frag_more(2*the_ins.numo); | |
2623 | fromP= &the_ins.opcode[0]; | |
2624 | for(m=the_ins.numo;m;--m) { | |
2625 | md_number_to_chars(toP,(long)(*fromP),2); | |
2626 | toP+=2; | |
2627 | fromP++; | |
2628 | } | |
2629 | /* put out symbol-dependent info */ | |
2630 | for(m=0;m<the_ins.nrel;m++) { | |
2631 | switch(the_ins.reloc[m].wid) { | |
2632 | case 'B': | |
2633 | n=1; | |
2634 | break; | |
2635 | case 'b': | |
2636 | n=1; | |
2637 | break; | |
2638 | case '3': | |
2639 | n=2; | |
2640 | break; | |
2641 | case 'w': | |
2642 | n=2; | |
2643 | break; | |
2644 | case 'l': | |
2645 | n=4; | |
2646 | break; | |
2647 | default: | |
2648 | as_fatal("Don't know how to figure width of %c in md_assemble()",the_ins.reloc[m].wid); | |
2649 | } | |
6d27d3a2 | 2650 | |
f8701a3f SC |
2651 | fix_new(frag_now, |
2652 | (toP-frag_now->fr_literal)-the_ins.numo*2+the_ins.reloc[m].n, | |
2653 | n, | |
2654 | the_ins.reloc[m].add, | |
2655 | the_ins.reloc[m].sub, | |
2656 | the_ins.reloc[m].off, | |
2657 | the_ins.reloc[m].pcrel, | |
2658 | NO_RELOC); | |
2659 | } | |
2660 | return; | |
2661 | } | |
6d27d3a2 | 2662 | |
f8701a3f SC |
2663 | /* There's some frag hacking */ |
2664 | for(n=0,fromP= &the_ins.opcode[0];n<the_ins.nfrag;n++) { | |
2665 | int wid; | |
6d27d3a2 | 2666 | |
f8701a3f SC |
2667 | if(n==0) wid=2*the_ins.fragb[n].fragoff; |
2668 | else wid=2*(the_ins.numo-the_ins.fragb[n-1].fragoff); | |
2669 | toP=frag_more(wid); | |
2670 | to_beg_P=toP; | |
2671 | shorts_this_frag=0; | |
2672 | for(m=wid/2;m;--m) { | |
2673 | md_number_to_chars(toP,(long)(*fromP),2); | |
2674 | toP+=2; | |
2675 | fromP++; | |
2676 | shorts_this_frag++; | |
2677 | } | |
2678 | for(m=0;m<the_ins.nrel;m++) { | |
2679 | if((the_ins.reloc[m].n)>= 2*shorts_this_frag /* 2*the_ins.fragb[n].fragoff */) { | |
2680 | the_ins.reloc[m].n-= 2*shorts_this_frag /* 2*the_ins.fragb[n].fragoff */; | |
2681 | break; | |
2682 | } | |
2683 | wid=the_ins.reloc[m].wid; | |
2684 | if(wid==0) | |
2685 | continue; | |
2686 | the_ins.reloc[m].wid=0; | |
2687 | wid = (wid=='b') ? 1 : (wid=='w') ? 2 : (wid=='l') ? 4 : 4000; | |
6d27d3a2 | 2688 | |
f8701a3f SC |
2689 | fix_new(frag_now, |
2690 | (toP-frag_now->fr_literal)-the_ins.numo*2+the_ins.reloc[m].n, | |
2691 | wid, | |
2692 | the_ins.reloc[m].add, | |
2693 | the_ins.reloc[m].sub, | |
2694 | the_ins.reloc[m].off, | |
2695 | the_ins.reloc[m].pcrel, | |
2696 | NO_RELOC); | |
2697 | } | |
2698 | /* know(the_ins.fragb[n].fadd); */ | |
2699 | (void)frag_var(rs_machine_dependent,10,0,(relax_substateT)(the_ins.fragb[n].fragty), | |
2700 | the_ins.fragb[n].fadd,the_ins.fragb[n].foff,to_beg_P); | |
2701 | } | |
2702 | n=(the_ins.numo-the_ins.fragb[n-1].fragoff); | |
fecd2382 | 2703 | shorts_this_frag=0; |
f8701a3f SC |
2704 | if(n) { |
2705 | toP=frag_more(n*sizeof(short)); | |
2706 | while(n--) { | |
2707 | md_number_to_chars(toP,(long)(*fromP),2); | |
2708 | toP+=2; | |
2709 | fromP++; | |
2710 | shorts_this_frag++; | |
2711 | } | |
fecd2382 RP |
2712 | } |
2713 | for(m=0;m<the_ins.nrel;m++) { | |
f8701a3f | 2714 | int wid; |
6d27d3a2 | 2715 | |
f8701a3f SC |
2716 | wid=the_ins.reloc[m].wid; |
2717 | if(wid==0) | |
2718 | continue; | |
2719 | the_ins.reloc[m].wid=0; | |
2720 | wid = (wid=='b') ? 1 : (wid=='w') ? 2 : (wid=='l') ? 4 : 4000; | |
6d27d3a2 | 2721 | |
f8701a3f SC |
2722 | fix_new(frag_now, |
2723 | (the_ins.reloc[m].n + toP-frag_now->fr_literal)-/* the_ins.numo */ shorts_this_frag*2, | |
2724 | wid, | |
2725 | the_ins.reloc[m].add, | |
2726 | the_ins.reloc[m].sub, | |
2727 | the_ins.reloc[m].off, | |
2728 | the_ins.reloc[m].pcrel, | |
2729 | NO_RELOC); | |
fecd2382 RP |
2730 | } |
2731 | } | |
2732 | ||
f8701a3f | 2733 | |
f8701a3f | 2734 | |
f8701a3f SC |
2735 | |
2736 | ||
fecd2382 | 2737 | void |
a39116f1 | 2738 | md_begin() |
fecd2382 | 2739 | { |
f8701a3f SC |
2740 | /* |
2741 | * md_begin -- set up hash tables with 68000 instructions. | |
2742 | * similar to what the vax assembler does. ---phr | |
2743 | */ | |
2744 | /* RMS claims the thing to do is take the m68k-opcode.h table, and make | |
2745 | a copy of it at runtime, adding in the information we want but isn't | |
2746 | there. I think it'd be better to have an awk script hack the table | |
2747 | at compile time. Or even just xstr the table and use it as-is. But | |
2748 | my lord ghod hath spoken, so we do it this way. Excuse the ugly var | |
2749 | names. */ | |
6d27d3a2 | 2750 | |
f8701a3f SC |
2751 | register const struct m68k_opcode *ins; |
2752 | register struct m68k_incant *hack, | |
2753 | *slak; | |
2754 | register char *retval = 0; /* empty string, or error msg text */ | |
2755 | register unsigned int i; | |
2756 | register char c; | |
6d27d3a2 | 2757 | |
f8701a3f SC |
2758 | if ((op_hash = hash_new()) == NULL) |
2759 | as_fatal("Virtual memory exhausted"); | |
6d27d3a2 | 2760 | |
f8701a3f SC |
2761 | obstack_begin(&robyn,4000); |
2762 | for (ins = m68k_opcodes; ins < endop; ins++) { | |
2763 | hack=slak=(struct m68k_incant *)obstack_alloc(&robyn,sizeof(struct m68k_incant)); | |
2764 | do { | |
2765 | /* we *could* ignore insns that don't match our | |
2766 | arch here but just leaving them out of the | |
2767 | hash. */ | |
2768 | slak->m_operands=ins->args; | |
2769 | slak->m_opnum=strlen(slak->m_operands)/2; | |
2770 | slak->m_arch = ins->arch; | |
2771 | slak->m_opcode=ins->opcode; | |
2772 | /* This is kludgey */ | |
2773 | slak->m_codenum=((ins->match)&0xffffL) ? 2 : 1; | |
2774 | if((ins+1)!=endop && !strcmp(ins->name,(ins+1)->name)) { | |
2775 | slak->m_next=(struct m68k_incant *) obstack_alloc(&robyn,sizeof(struct m68k_incant)); | |
2776 | ins++; | |
2777 | } else | |
2778 | slak->m_next=0; | |
2779 | slak=slak->m_next; | |
2780 | } while(slak); | |
6d27d3a2 | 2781 | |
f8701a3f SC |
2782 | retval = hash_insert (op_hash, ins->name,(char *)hack); |
2783 | /* Didn't his mommy tell him about null pointers? */ | |
2784 | if(retval && *retval) | |
2785 | as_fatal("Internal Error: Can't hash %s: %s",ins->name,retval); | |
2786 | } | |
6d27d3a2 | 2787 | |
f8701a3f SC |
2788 | for (i = 0; i < sizeof(mklower_table) ; i++) |
2789 | mklower_table[i] = (isupper(c = (char) i)) ? tolower(c) : c; | |
6d27d3a2 | 2790 | |
f8701a3f SC |
2791 | for (i = 0 ; i < sizeof(notend_table) ; i++) { |
2792 | notend_table[i] = 0; | |
2793 | alt_notend_table[i] = 0; | |
2794 | } | |
2795 | notend_table[','] = 1; | |
2796 | notend_table['{'] = 1; | |
2797 | notend_table['}'] = 1; | |
2798 | alt_notend_table['a'] = 1; | |
2799 | alt_notend_table['A'] = 1; | |
2800 | alt_notend_table['d'] = 1; | |
2801 | alt_notend_table['D'] = 1; | |
2802 | alt_notend_table['#'] = 1; | |
2803 | alt_notend_table['f'] = 1; | |
2804 | alt_notend_table['F'] = 1; | |
fecd2382 | 2805 | #ifdef REGISTER_PREFIX |
f8701a3f | 2806 | alt_notend_table[REGISTER_PREFIX] = 1; |
fecd2382 | 2807 | #endif |
f8701a3f SC |
2808 | |
2809 | init_regtable(); | |
fecd2382 RP |
2810 | } |
2811 | ||
2812 | #if 0 | |
2813 | #define notend(s) ((*s == ',' || *s == '}' || *s == '{' \ | |
a39116f1 RP |
2814 | || (*s == ':' && strchr("aAdD#", s[1]))) \ |
2815 | ? 0 : 1) | |
fecd2382 RP |
2816 | #endif |
2817 | ||
2818 | /* This funciton is called once, before the assembler exits. It is | |
2819 | supposed to do any final cleanup for this part of the assembler. | |
a39116f1 | 2820 | */ |
fecd2382 | 2821 | void |
a39116f1 | 2822 | md_end() |
fecd2382 RP |
2823 | { |
2824 | } | |
2825 | ||
2826 | /* Equal to MAX_PRECISION in atof-ieee.c */ | |
2827 | #define MAX_LITTLENUMS 6 | |
2828 | ||
2829 | /* Turn a string in input_line_pointer into a floating point constant of type | |
2830 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
2831 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. | |
a39116f1 | 2832 | */ |
fecd2382 | 2833 | char * |
a39116f1 | 2834 | md_atof(type,litP,sizeP) |
fecd2382 RP |
2835 | char type; |
2836 | char *litP; | |
2837 | int *sizeP; | |
2838 | { | |
f8701a3f SC |
2839 | int prec; |
2840 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
2841 | LITTLENUM_TYPE *wordP; | |
2842 | char *t; | |
2843 | char *atof_ieee(); | |
6d27d3a2 | 2844 | |
f8701a3f SC |
2845 | switch(type) { |
2846 | case 'f': | |
2847 | case 'F': | |
2848 | case 's': | |
2849 | case 'S': | |
2850 | prec = 2; | |
2851 | break; | |
6d27d3a2 | 2852 | |
f8701a3f SC |
2853 | case 'd': |
2854 | case 'D': | |
2855 | case 'r': | |
2856 | case 'R': | |
2857 | prec = 4; | |
2858 | break; | |
6d27d3a2 | 2859 | |
f8701a3f SC |
2860 | case 'x': |
2861 | case 'X': | |
2862 | prec = 6; | |
2863 | break; | |
6d27d3a2 | 2864 | |
f8701a3f SC |
2865 | case 'p': |
2866 | case 'P': | |
2867 | prec = 6; | |
2868 | break; | |
6d27d3a2 | 2869 | |
f8701a3f SC |
2870 | default: |
2871 | *sizeP=0; | |
2872 | return "Bad call to MD_ATOF()"; | |
2873 | } | |
2874 | t=atof_ieee(input_line_pointer,type,words); | |
2875 | if(t) | |
2876 | input_line_pointer=t; | |
6d27d3a2 | 2877 | |
f8701a3f SC |
2878 | *sizeP=prec * sizeof(LITTLENUM_TYPE); |
2879 | for(wordP=words;prec--;) { | |
2880 | md_number_to_chars(litP,(long)(*wordP++),sizeof(LITTLENUM_TYPE)); | |
2881 | litP+=sizeof(LITTLENUM_TYPE); | |
2882 | } | |
2883 | return ""; /* Someone should teach Dean about null pointers */ | |
fecd2382 RP |
2884 | } |
2885 | ||
2886 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate | |
2887 | for use in the a.out file, and stores them in the array pointed to by buf. | |
2888 | This knows about the endian-ness of the target machine and does | |
2889 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
2890 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
2891 | LITTLENUMS (shorts, here at least) | |
a39116f1 | 2892 | */ |
fecd2382 | 2893 | void |
a39116f1 | 2894 | md_number_to_chars(buf,val,n) |
fecd2382 RP |
2895 | char *buf; |
2896 | long val; | |
2897 | int n; | |
2898 | { | |
f8701a3f SC |
2899 | switch(n) { |
2900 | case 1: | |
2901 | *buf++=val; | |
2902 | break; | |
2903 | case 2: | |
2904 | *buf++=(val>>8); | |
2905 | *buf++=val; | |
2906 | break; | |
2907 | case 4: | |
2908 | *buf++=(val>>24); | |
2909 | *buf++=(val>>16); | |
2910 | *buf++=(val>>8); | |
2911 | *buf++=val; | |
2912 | break; | |
2913 | default: | |
2914 | as_fatal("failed sanity check."); | |
2915 | } | |
fecd2382 RP |
2916 | } |
2917 | ||
2918 | void | |
a39116f1 RP |
2919 | md_apply_fix(fixP, val) |
2920 | fixS *fixP; | |
2921 | long val; | |
fecd2382 | 2922 | { |
f8701a3f | 2923 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; |
6d27d3a2 | 2924 | |
f8701a3f SC |
2925 | switch(fixP->fx_size) { |
2926 | case 1: | |
2927 | *buf++=val; | |
2928 | break; | |
2929 | case 2: | |
2930 | *buf++=(val>>8); | |
2931 | *buf++=val; | |
2932 | break; | |
2933 | case 4: | |
2934 | *buf++=(val>>24); | |
2935 | *buf++=(val>>16); | |
2936 | *buf++=(val>>8); | |
2937 | *buf++=val; | |
2938 | break; | |
2939 | default: | |
2940 | BAD_CASE (fixP->fx_size); | |
2941 | } | |
fecd2382 RP |
2942 | } |
2943 | ||
2944 | ||
2945 | /* *fragP has been relaxed to its final size, and now needs to have | |
2946 | the bytes inside it modified to conform to the new size There is UGLY | |
2947 | MAGIC here. .. | |
a39116f1 | 2948 | */ |
fecd2382 | 2949 | void |
a39116f1 | 2950 | md_convert_frag(headers, fragP) |
f6e504fe | 2951 | object_headers *headers; |
fecd2382 RP |
2952 | register fragS *fragP; |
2953 | { | |
f8701a3f SC |
2954 | long disp; |
2955 | long ext = 0; | |
6d27d3a2 | 2956 | |
f8701a3f SC |
2957 | /* Address in object code of the displacement. */ |
2958 | register int object_address = fragP -> fr_fix + fragP -> fr_address; | |
6d27d3a2 | 2959 | |
f6e504fe | 2960 | #ifdef IBM_COMPILER_SUX |
f8701a3f SC |
2961 | /* This is wrong but it convinces the native rs6000 compiler to |
2962 | generate the code we want. */ | |
2963 | register char *buffer_address = fragP -> fr_literal; | |
2964 | buffer_address += fragP -> fr_fix; | |
f6e504fe | 2965 | #else /* IBM_COMPILER_SUX */ |
f8701a3f SC |
2966 | /* Address in gas core of the place to store the displacement. */ |
2967 | register char *buffer_address = fragP->fr_fix + fragP->fr_literal; | |
f6e504fe | 2968 | #endif /* IBM_COMPILER_SUX */ |
6d27d3a2 | 2969 | |
f8701a3f | 2970 | /* No longer true: know(fragP->fr_symbol); */ |
6d27d3a2 | 2971 | |
f8701a3f SC |
2972 | /* The displacement of the address, from current location. */ |
2973 | disp = fragP->fr_symbol ? S_GET_VALUE(fragP->fr_symbol) : 0; | |
2974 | disp = (disp + fragP->fr_offset) - object_address; | |
6d27d3a2 | 2975 | |
f8701a3f SC |
2976 | switch(fragP->fr_subtype) { |
2977 | case TAB(BCC68000,BYTE): | |
a39116f1 RP |
2978 | case TAB(BRANCH,BYTE): |
2979 | know(issbyte(disp)); | |
2980 | if(disp==0) | |
2981 | as_bad("short branch with zero offset: use :w"); | |
2982 | fragP->fr_opcode[1]=disp; | |
fecd2382 | 2983 | ext=0; |
a39116f1 | 2984 | break; |
f8701a3f SC |
2985 | case TAB(DBCC,SHORT): |
2986 | know(issword(disp)); | |
a39116f1 RP |
2987 | ext=2; |
2988 | break; | |
f8701a3f SC |
2989 | case TAB(BCC68000,SHORT): |
2990 | case TAB(BRANCH,SHORT): | |
2991 | know(issword(disp)); | |
a39116f1 RP |
2992 | fragP->fr_opcode[1]=0x00; |
2993 | ext=2; | |
2994 | break; | |
f8701a3f SC |
2995 | case TAB(BRANCH,LONG): |
2996 | if (cpu_of_arch(current_architecture) < m68020) { | |
2997 | if (fragP->fr_opcode[0]==0x61) { | |
2998 | fragP->fr_opcode[0]= 0x4E; | |
2999 | fragP->fr_opcode[1]= 0xB9; /* JBSR with ABSL LONG offset */ | |
3000 | subseg_change(SEG_TEXT, 0); | |
6d27d3a2 | 3001 | |
f8701a3f SC |
3002 | fix_new(fragP, |
3003 | fragP->fr_fix, | |
3004 | 4, | |
3005 | fragP->fr_symbol, | |
3006 | 0, | |
3007 | fragP->fr_offset, | |
3008 | 0, | |
3009 | NO_RELOC); | |
6d27d3a2 | 3010 | |
f8701a3f SC |
3011 | fragP->fr_fix+=4; |
3012 | ext=0; | |
3013 | } else if (fragP->fr_opcode[0]==0x60) { | |
3014 | fragP->fr_opcode[0]= 0x4E; | |
3015 | fragP->fr_opcode[1]= 0xF9; /* JMP with ABSL LONG offset */ | |
3016 | subseg_change(SEG_TEXT, 0); | |
3017 | fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset,0, | |
3018 | NO_RELOC); | |
3019 | fragP->fr_fix+=4; | |
3020 | ext=0; | |
3021 | } else { | |
3022 | as_bad("Long branch offset not supported."); | |
3023 | } | |
3024 | } else { | |
3025 | fragP->fr_opcode[1]=0xff; | |
3026 | ext=4; | |
3027 | } | |
3028 | break; | |
3029 | case TAB(BCC68000,LONG): | |
3030 | /* only Bcc 68000 instructions can come here */ | |
3031 | /* change bcc into b!cc/jmp absl long */ | |
3032 | fragP->fr_opcode[0] ^= 0x01; /* invert bcc */ | |
fecd2382 | 3033 | fragP->fr_opcode[1] = 0x6; /* branch offset = 6 */ |
6d27d3a2 | 3034 | |
fecd2382 RP |
3035 | /* JF: these used to be fr_opcode[2,3], but they may be in a |
3036 | different frag, in which case refering to them is a no-no. | |
3037 | Only fr_opcode[0,1] are guaranteed to work. */ | |
6d27d3a2 KR |
3038 | *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */ |
3039 | *buffer_address++ = 0xf9; | |
fecd2382 RP |
3040 | fragP->fr_fix += 2; /* account for jmp instruction */ |
3041 | subseg_change(SEG_TEXT,0); | |
6d27d3a2 | 3042 | fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, |
a39116f1 RP |
3043 | fragP->fr_offset,0, |
3044 | NO_RELOC); | |
fecd2382 RP |
3045 | fragP->fr_fix += 4; |
3046 | ext=0; | |
3047 | break; | |
f8701a3f SC |
3048 | case TAB(DBCC,LONG): |
3049 | /* only DBcc 68000 instructions can come here */ | |
3050 | /* change dbcc into dbcc/jmp absl long */ | |
3051 | /* JF: these used to be fr_opcode[2-7], but that's wrong */ | |
3052 | *buffer_address++ = 0x00; /* branch offset = 4 */ | |
6d27d3a2 KR |
3053 | *buffer_address++ = 0x04; |
3054 | *buffer_address++ = 0x60; /* put in bra pc+6 */ | |
3055 | *buffer_address++ = 0x06; | |
3056 | *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */ | |
3057 | *buffer_address++ = 0xf9; | |
3058 | ||
fecd2382 RP |
3059 | fragP->fr_fix += 6; /* account for bra/jmp instructions */ |
3060 | subseg_change(SEG_TEXT,0); | |
6d27d3a2 | 3061 | fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, |
a39116f1 RP |
3062 | fragP->fr_offset,0, |
3063 | NO_RELOC); | |
fecd2382 RP |
3064 | fragP->fr_fix += 4; |
3065 | ext=0; | |
a39116f1 | 3066 | break; |
f8701a3f SC |
3067 | case TAB(FBRANCH,SHORT): |
3068 | know((fragP->fr_opcode[1]&0x40)==0); | |
a39116f1 RP |
3069 | ext=2; |
3070 | break; | |
f8701a3f SC |
3071 | case TAB(FBRANCH,LONG): |
3072 | fragP->fr_opcode[1]|=0x40; /* Turn on LONG bit */ | |
a39116f1 RP |
3073 | ext=4; |
3074 | break; | |
f8701a3f SC |
3075 | case TAB(PCREL,SHORT): |
3076 | ext=2; | |
a39116f1 | 3077 | break; |
f8701a3f SC |
3078 | case TAB(PCREL,LONG): |
3079 | /* The thing to do here is force it to ABSOLUTE LONG, since | |
3080 | PCREL is really trying to shorten an ABSOLUTE address anyway */ | |
3081 | /* JF FOO This code has not been tested */ | |
3082 | subseg_change(SEG_TEXT,0); | |
a39116f1 RP |
3083 | fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC); |
3084 | if((fragP->fr_opcode[1] & 0x3F) != 0x3A) | |
3085 | as_bad("Internal error (long PC-relative operand) for insn 0x%04lx at 0x%lx", | |
3086 | fragP->fr_opcode[0],fragP->fr_address); | |
3087 | fragP->fr_opcode[1]&= ~0x3F; | |
3088 | fragP->fr_opcode[1]|=0x39; /* Mode 7.1 */ | |
3089 | fragP->fr_fix+=4; | |
3090 | /* md_number_to_chars(buffer_address, | |
3091 | (long)(fragP->fr_symbol->sy_value + fragP->fr_offset), | |
3092 | 4); */ | |
3093 | ext=0; | |
3094 | break; | |
f8701a3f SC |
3095 | case TAB(PCLEA,SHORT): |
3096 | subseg_change(SEG_TEXT,0); | |
a39116f1 RP |
3097 | fix_new(fragP,(int)(fragP->fr_fix),2,fragP->fr_symbol,(symbolS *)0,fragP->fr_offset,1, |
3098 | NO_RELOC); | |
3099 | fragP->fr_opcode[1] &= ~0x3F; | |
3100 | fragP->fr_opcode[1] |= 0x3A; | |
3101 | ext=2; | |
3102 | break; | |
f8701a3f SC |
3103 | case TAB(PCLEA,LONG): |
3104 | subseg_change(SEG_TEXT,0); | |
3105 | fix_new(fragP,(int)(fragP->fr_fix)+2,4,fragP->fr_symbol,(symbolS *)0,fragP->fr_offset+2,1, | |
3106 | NO_RELOC); | |
3107 | *buffer_address++ = 0x01; | |
3108 | *buffer_address++ = 0x70; | |
3109 | fragP->fr_fix+=2; | |
3110 | /* buffer_address+=2; */ | |
3111 | ext=4; | |
a39116f1 | 3112 | break; |
6d27d3a2 | 3113 | |
f8701a3f | 3114 | } /* switch on subtype */ |
6d27d3a2 | 3115 | |
f8701a3f SC |
3116 | if (ext) { |
3117 | md_number_to_chars(buffer_address, (long) disp, (int) ext); | |
3118 | fragP->fr_fix += ext; | |
3119 | /* H_SET_TEXT_SIZE(headers, H_GET_TEXT_SIZE(headers) + ext); */ | |
3120 | } /* if extending */ | |
6d27d3a2 | 3121 | |
f8701a3f SC |
3122 | return; |
3123 | } /* md_convert_frag() */ | |
3124 | ||
3125 | /* Force truly undefined symbols to their maximum size, and generally set up | |
3126 | the frag list to be relaxed | |
3127 | */ | |
3128 | int md_estimate_size_before_relax(fragP, segment) | |
3129 | register fragS *fragP; | |
3130 | segT segment; | |
3131 | { | |
3132 | int old_fix; | |
3133 | register char *buffer_address = fragP->fr_fix + fragP->fr_literal; | |
6d27d3a2 | 3134 | |
f8701a3f | 3135 | old_fix = fragP->fr_fix; |
6d27d3a2 | 3136 | |
f8701a3f SC |
3137 | /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */ |
3138 | switch (fragP->fr_subtype) { | |
6d27d3a2 | 3139 | |
f8701a3f SC |
3140 | case TAB(BRANCH,SZ_UNDEF): { |
3141 | if((fragP->fr_symbol != NULL) /* Not absolute */ | |
3142 | && S_GET_SEGMENT(fragP->fr_symbol) == segment) { | |
3143 | fragP->fr_subtype=TAB(TABTYPE(fragP->fr_subtype),BYTE); | |
3144 | break; | |
3145 | } else if((fragP->fr_symbol == 0) || (cpu_of_arch(current_architecture) < m68020)) { | |
3146 | /* On 68000, or for absolute value, switch to abs long */ | |
3147 | /* FIXME, we should check abs val, pick short or long */ | |
3148 | if(fragP->fr_opcode[0]==0x61) { | |
3149 | fragP->fr_opcode[0]= 0x4E; | |
3150 | fragP->fr_opcode[1]= 0xB9; /* JBSR with ABSL LONG offset */ | |
3151 | subseg_change(SEG_TEXT, 0); | |
6d27d3a2 | 3152 | fix_new(fragP, fragP->fr_fix, 4, |
f8701a3f SC |
3153 | fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC); |
3154 | fragP->fr_fix+=4; | |
3155 | frag_wane(fragP); | |
3156 | } else if(fragP->fr_opcode[0]==0x60) { | |
3157 | fragP->fr_opcode[0]= 0x4E; | |
3158 | fragP->fr_opcode[1]= 0xF9; /* JMP with ABSL LONG offset */ | |
3159 | subseg_change(SEG_TEXT, 0); | |
6d27d3a2 | 3160 | fix_new(fragP, fragP->fr_fix, 4, |
f8701a3f SC |
3161 | fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC); |
3162 | fragP->fr_fix+=4; | |
3163 | frag_wane(fragP); | |
3164 | } else { | |
3165 | as_warn("Long branch offset to extern symbol not supported."); | |
3166 | } | |
3167 | } else { /* Symbol is still undefined. Make it simple */ | |
3168 | fix_new(fragP, (int)(fragP->fr_fix), 4, fragP->fr_symbol, | |
3169 | (symbolS *)0, fragP->fr_offset+4, 1, NO_RELOC); | |
3170 | fragP->fr_fix+=4; | |
3171 | fragP->fr_opcode[1]=0xff; | |
3172 | frag_wane(fragP); | |
3173 | break; | |
3174 | } | |
6d27d3a2 | 3175 | |
f8701a3f SC |
3176 | break; |
3177 | } /* case TAB(BRANCH,SZ_UNDEF) */ | |
6d27d3a2 | 3178 | |
f8701a3f SC |
3179 | case TAB(FBRANCH,SZ_UNDEF): { |
3180 | if(S_GET_SEGMENT(fragP->fr_symbol) == segment || flagseen['l']) { | |
3181 | fragP->fr_subtype = TAB(FBRANCH,SHORT); | |
3182 | fragP->fr_var += 2; | |
3183 | } else { | |
3184 | fragP->fr_subtype = TAB(FBRANCH,LONG); | |
3185 | fragP->fr_var += 4; | |
3186 | } | |
3187 | break; | |
3188 | } /* TAB(FBRANCH,SZ_UNDEF) */ | |
6d27d3a2 | 3189 | |
f8701a3f SC |
3190 | case TAB(PCREL,SZ_UNDEF): { |
3191 | if(S_GET_SEGMENT(fragP->fr_symbol) == segment || flagseen['l']) { | |
3192 | fragP->fr_subtype = TAB(PCREL,SHORT); | |
3193 | fragP->fr_var += 2; | |
3194 | } else { | |
3195 | fragP->fr_subtype = TAB(PCREL,LONG); | |
3196 | fragP->fr_var += 4; | |
3197 | } | |
3198 | break; | |
3199 | } /* TAB(PCREL,SZ_UNDEF) */ | |
6d27d3a2 | 3200 | |
f8701a3f SC |
3201 | case TAB(BCC68000,SZ_UNDEF): { |
3202 | if((fragP->fr_symbol != NULL) | |
3203 | && S_GET_SEGMENT(fragP->fr_symbol) == segment) { | |
3204 | fragP->fr_subtype=TAB(BCC68000,BYTE); | |
3205 | break; | |
3206 | } | |
3207 | /* only Bcc 68000 instructions can come here */ | |
3208 | /* change bcc into b!cc/jmp absl long */ | |
3209 | fragP->fr_opcode[0] ^= 0x01; /* invert bcc */ | |
3210 | if(flagseen['l']) { | |
3211 | fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */ | |
3212 | /* JF: these were fr_opcode[2,3] */ | |
6d27d3a2 | 3213 | buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */ |
f8701a3f SC |
3214 | buffer_address[1] = 0xf8; |
3215 | fragP->fr_fix += 2; /* account for jmp instruction */ | |
3216 | subseg_change(SEG_TEXT,0); | |
6d27d3a2 | 3217 | fix_new(fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0, |
f8701a3f SC |
3218 | fragP->fr_offset, 0, NO_RELOC); |
3219 | fragP->fr_fix += 2; | |
3220 | } else { | |
3221 | fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */ | |
3222 | /* JF: these were fr_opcode[2,3] */ | |
6d27d3a2 | 3223 | buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */ |
a1765cf0 | 3224 | buffer_address[1] = 0xf9; |
f8701a3f SC |
3225 | fragP->fr_fix += 2; /* account for jmp instruction */ |
3226 | subseg_change(SEG_TEXT,0); | |
6d27d3a2 | 3227 | fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, |
f8701a3f SC |
3228 | fragP->fr_offset, 0, NO_RELOC); |
3229 | fragP->fr_fix += 4; | |
3230 | } | |
3231 | frag_wane(fragP); | |
3232 | break; | |
3233 | } /* case TAB(BCC68000,SZ_UNDEF) */ | |
6d27d3a2 | 3234 | |
f8701a3f SC |
3235 | case TAB(DBCC,SZ_UNDEF): { |
3236 | if (fragP->fr_symbol != NULL && S_GET_SEGMENT(fragP->fr_symbol) == segment) { | |
3237 | fragP->fr_subtype=TAB(DBCC,SHORT); | |
3238 | fragP->fr_var+=2; | |
3239 | break; | |
3240 | } | |
3241 | /* only DBcc 68000 instructions can come here */ | |
3242 | /* change dbcc into dbcc/jmp absl long */ | |
3243 | /* JF: these used to be fr_opcode[2-4], which is wrong. */ | |
3244 | buffer_address[0] = 0x00; /* branch offset = 4 */ | |
6d27d3a2 | 3245 | buffer_address[1] = 0x04; |
f8701a3f | 3246 | buffer_address[2] = 0x60; /* put in bra pc + ... */ |
6d27d3a2 | 3247 | |
f8701a3f SC |
3248 | if(flagseen['l']) { |
3249 | /* JF: these were fr_opcode[5-7] */ | |
3250 | buffer_address[3] = 0x04; /* plus 4 */ | |
3251 | buffer_address[4] = 0x4e;/* Put in Jump Word */ | |
3252 | buffer_address[5] = 0xf8; | |
3253 | fragP->fr_fix += 6; /* account for bra/jmp instruction */ | |
3254 | subseg_change(SEG_TEXT,0); | |
6d27d3a2 | 3255 | fix_new(fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0, |
a933d598 SC |
3256 | |
3257 | ||
f8701a3f SC |
3258 | fragP->fr_offset, 0, NO_RELOC); |
3259 | fragP->fr_fix += 2; | |
3260 | } else { | |
3261 | /* JF: these were fr_opcode[5-7] */ | |
3262 | buffer_address[3] = 0x06; /* Plus 6 */ | |
6d27d3a2 KR |
3263 | buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */ |
3264 | buffer_address[5] = 0xf9; | |
f8701a3f SC |
3265 | fragP->fr_fix += 6; /* account for bra/jmp instruction */ |
3266 | subseg_change(SEG_TEXT,0); | |
6d27d3a2 | 3267 | fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, |
f8701a3f SC |
3268 | fragP->fr_offset, 0, NO_RELOC); |
3269 | fragP->fr_fix += 4; | |
3270 | } | |
6d27d3a2 | 3271 | |
f8701a3f SC |
3272 | frag_wane(fragP); |
3273 | break; | |
3274 | } /* case TAB(DBCC,SZ_UNDEF) */ | |
6d27d3a2 | 3275 | |
f8701a3f SC |
3276 | case TAB(PCLEA,SZ_UNDEF): { |
3277 | if ((S_GET_SEGMENT(fragP->fr_symbol))==segment || flagseen['l']) { | |
3278 | fragP->fr_subtype=TAB(PCLEA,SHORT); | |
3279 | fragP->fr_var+=2; | |
3280 | } else { | |
3281 | fragP->fr_subtype=TAB(PCLEA,LONG); | |
3282 | fragP->fr_var+=6; | |
3283 | } | |
3284 | break; | |
3285 | } /* TAB(PCLEA,SZ_UNDEF) */ | |
6d27d3a2 | 3286 | |
f8701a3f SC |
3287 | default: |
3288 | break; | |
6d27d3a2 | 3289 | |
f8701a3f | 3290 | } /* switch on subtype looking for SZ_UNDEF's. */ |
6d27d3a2 | 3291 | |
f8701a3f SC |
3292 | /* now that SZ_UNDEF are taken care of, check others */ |
3293 | switch (fragP->fr_subtype) { | |
3294 | case TAB(BCC68000,BYTE): | |
a39116f1 RP |
3295 | case TAB(BRANCH,BYTE): |
3296 | /* We can't do a short jump to the next instruction, | |
3297 | so we force word mode. */ | |
3298 | if (fragP->fr_symbol && S_GET_VALUE(fragP->fr_symbol)==0 && | |
3299 | fragP->fr_symbol->sy_frag==fragP->fr_next) { | |
f8701a3f SC |
3300 | fragP->fr_subtype=TAB(TABTYPE(fragP->fr_subtype),SHORT); |
3301 | fragP->fr_var+=2; | |
fecd2382 | 3302 | } |
a39116f1 | 3303 | break; |
f8701a3f | 3304 | default: |
a39116f1 | 3305 | break; |
f8701a3f SC |
3306 | } |
3307 | return fragP->fr_var + fragP->fr_fix - old_fix; | |
fecd2382 RP |
3308 | } |
3309 | ||
3310 | #if defined(OBJ_AOUT) | defined(OBJ_BOUT) | |
6d27d3a2 | 3311 | /* the bit-field entries in the relocation_info struct plays hell |
fecd2382 RP |
3312 | with the byte-order problems of cross-assembly. So as a hack, |
3313 | I added this mach. dependent ri twiddler. Ugly, but it gets | |
3314 | you there. -KWK */ | |
3315 | /* on m68k: first 4 bytes are normal unsigned long, next three bytes | |
a39116f1 RP |
3316 | are symbolnum, most sig. byte first. Last byte is broken up with |
3317 | bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower | |
3318 | nibble as nuthin. (on Sun 3 at least) */ | |
fecd2382 RP |
3319 | /* Translate the internal relocation information into target-specific |
3320 | format. */ | |
a79c6033 | 3321 | #ifdef comment |
fecd2382 | 3322 | void |
a39116f1 RP |
3323 | md_ri_to_chars(the_bytes, ri) |
3324 | char *the_bytes; | |
3325 | struct reloc_info_generic *ri; | |
fecd2382 | 3326 | { |
f8701a3f SC |
3327 | /* this is easy */ |
3328 | md_number_to_chars(the_bytes, ri->r_address, 4); | |
3329 | /* now the fun stuff */ | |
3330 | the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff; | |
3331 | the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff; | |
3332 | the_bytes[6] = ri->r_symbolnum & 0x0ff; | |
6d27d3a2 KR |
3333 | the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) | |
3334 | ((ri->r_extern << 4) & 0x10)); | |
fecd2382 | 3335 | } |
a79c6033 RP |
3336 | #endif /* comment */ |
3337 | ||
3338 | void tc_aout_fix_to_chars(where, fixP, segment_address_in_file) | |
f8701a3f SC |
3339 | char *where; |
3340 | fixS *fixP; | |
3341 | relax_addressT segment_address_in_file; | |
a79c6033 | 3342 | { |
f8701a3f SC |
3343 | /* |
3344 | * In: length of relocation (or of address) in chars: 1, 2 or 4. | |
3345 | * Out: GNU LD relocation length code: 0, 1, or 2. | |
3346 | */ | |
6d27d3a2 | 3347 | |
f8701a3f SC |
3348 | static unsigned char nbytes_r_length [] = { 42, 0, 1, 42, 2 }; |
3349 | long r_symbolnum; | |
6d27d3a2 | 3350 | |
f8701a3f | 3351 | know(fixP->fx_addsy != NULL); |
6d27d3a2 | 3352 | |
f8701a3f SC |
3353 | md_number_to_chars(where, |
3354 | fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file, | |
3355 | 4); | |
6d27d3a2 | 3356 | |
f8701a3f SC |
3357 | r_symbolnum = (S_IS_DEFINED(fixP->fx_addsy) |
3358 | ? S_GET_TYPE(fixP->fx_addsy) | |
3359 | : fixP->fx_addsy->sy_number); | |
6d27d3a2 | 3360 | |
f8701a3f SC |
3361 | where[4] = (r_symbolnum >> 16) & 0x0ff; |
3362 | where[5] = (r_symbolnum >> 8) & 0x0ff; | |
3363 | where[6] = r_symbolnum & 0x0ff; | |
6d27d3a2 | 3364 | where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) | |
f8701a3f | 3365 | (((!S_IS_DEFINED(fixP->fx_addsy)) << 4) & 0x10)); |
6d27d3a2 | 3366 | |
f8701a3f | 3367 | return; |
a79c6033 RP |
3368 | } /* tc_aout_fix_to_chars() */ |
3369 | ||
fecd2382 RP |
3370 | #endif /* OBJ_AOUT or OBJ_BOUT */ |
3371 | ||
3372 | #ifndef WORKING_DOT_WORD | |
3373 | const int md_short_jump_size = 4; | |
3374 | const int md_long_jump_size = 6; | |
3375 | ||
3376 | void | |
a39116f1 | 3377 | md_create_short_jump(ptr,from_addr,to_addr,frag,to_symbol) |
fecd2382 RP |
3378 | char *ptr; |
3379 | long from_addr, | |
a39116f1 | 3380 | to_addr; |
fecd2382 RP |
3381 | fragS *frag; |
3382 | symbolS *to_symbol; | |
3383 | { | |
f8701a3f | 3384 | long offset; |
6d27d3a2 | 3385 | |
f8701a3f | 3386 | offset = to_addr - (from_addr+2); |
6d27d3a2 | 3387 | |
f8701a3f SC |
3388 | md_number_to_chars(ptr ,(long)0x6000,2); |
3389 | md_number_to_chars(ptr+2,(long)offset,2); | |
fecd2382 RP |
3390 | } |
3391 | ||
3392 | void | |
a39116f1 | 3393 | md_create_long_jump(ptr,from_addr,to_addr,frag,to_symbol) |
fecd2382 RP |
3394 | char *ptr; |
3395 | long from_addr, | |
a39116f1 | 3396 | to_addr; |
fecd2382 RP |
3397 | fragS *frag; |
3398 | symbolS *to_symbol; | |
3399 | { | |
f8701a3f | 3400 | long offset; |
6d27d3a2 | 3401 | |
f8701a3f SC |
3402 | if (cpu_of_arch(current_architecture) < m68020) { |
3403 | offset=to_addr-S_GET_VALUE(to_symbol); | |
3404 | md_number_to_chars(ptr ,(long)0x4EF9,2); | |
3405 | md_number_to_chars(ptr+2,(long)offset,4); | |
3406 | fix_new(frag,(ptr+2)-frag->fr_literal,4,to_symbol,(symbolS *)0,(long)0,0, | |
3407 | NO_RELOC); | |
3408 | } else { | |
3409 | offset=to_addr - (from_addr+2); | |
3410 | md_number_to_chars(ptr ,(long)0x60ff,2); | |
3411 | md_number_to_chars(ptr+2,(long)offset,4); | |
3412 | } | |
fecd2382 RP |
3413 | } |
3414 | ||
3415 | #endif | |
3416 | /* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?) | |
6d27d3a2 | 3417 | |
a39116f1 RP |
3418 | 0: Everything is OK |
3419 | 10: Absolute 1:8 only | |
3420 | 20: Absolute 0:7 only | |
3421 | 30: absolute 0:15 only | |
3422 | 40: Absolute 0:31 only | |
3423 | 50: absolute 0:127 only | |
3424 | 55: absolute -64:63 only | |
3425 | 60: absolute -128:127 only | |
3426 | 70: absolute 0:4095 only | |
3427 | 80: No bignums | |
6d27d3a2 | 3428 | |
a39116f1 | 3429 | */ |
fecd2382 RP |
3430 | |
3431 | static int get_num(exp,ok) | |
f8701a3f SC |
3432 | struct m68k_exp *exp; |
3433 | int ok; | |
fecd2382 RP |
3434 | { |
3435 | #ifdef TEST2 | |
f8701a3f | 3436 | long l = 0; |
6d27d3a2 | 3437 | |
f8701a3f SC |
3438 | if(!exp->e_beg) |
3439 | return 0; | |
3440 | if(*exp->e_beg=='0') { | |
3441 | if(exp->e_beg[1]=='x') | |
3442 | sscanf(exp->e_beg+2,"%x",&l); | |
3443 | else | |
3444 | sscanf(exp->e_beg+1,"%O",&l); | |
3445 | return l; | |
3446 | } | |
3447 | return atol(exp->e_beg); | |
fecd2382 | 3448 | #else |
f8701a3f SC |
3449 | char *save_in; |
3450 | char c_save; | |
6d27d3a2 | 3451 | |
f8701a3f SC |
3452 | if(!exp) { |
3453 | /* Can't do anything */ | |
3454 | return 0; | |
3455 | } | |
3456 | if(!exp->e_beg || !exp->e_end) { | |
3457 | seg(exp)=SEG_ABSOLUTE; | |
3458 | adds(exp)=0; | |
3459 | subs(exp)=0; | |
3460 | offs(exp)= (ok==10) ? 1 : 0; | |
3461 | as_warn("Null expression defaults to %ld",offs(exp)); | |
3462 | return 0; | |
fecd2382 | 3463 | } |
6d27d3a2 | 3464 | |
f8701a3f SC |
3465 | exp->e_siz=0; |
3466 | if(/* ok!=80 && */exp->e_end[-1]==':' && (exp->e_end-exp->e_beg)>=2) { | |
3467 | switch(exp->e_end[0]) { | |
3468 | case 's': | |
3469 | case 'S': | |
3470 | case 'b': | |
3471 | case 'B': | |
3472 | exp->e_siz=1; | |
3473 | break; | |
3474 | case 'w': | |
3475 | case 'W': | |
3476 | exp->e_siz=2; | |
3477 | break; | |
3478 | case 'l': | |
3479 | case 'L': | |
3480 | exp->e_siz=3; | |
3481 | break; | |
3482 | default: | |
3483 | as_bad("Unknown size for expression \"%c\"",exp->e_end[0]); | |
3484 | } | |
3485 | exp->e_end-=2; | |
fecd2382 | 3486 | } |
f8701a3f SC |
3487 | c_save=exp->e_end[1]; |
3488 | exp->e_end[1]='\0'; | |
3489 | save_in=input_line_pointer; | |
3490 | input_line_pointer=exp->e_beg; | |
3491 | switch(expression(&(exp->e_exp))) { | |
3492 | case SEG_PASS1: | |
3493 | seg(exp)=SEG_ABSOLUTE; | |
3494 | adds(exp)=0; | |
3495 | subs(exp)=0; | |
3496 | offs(exp)= (ok==10) ? 1 : 0; | |
3497 | as_warn("Unknown expression: '%s' defaulting to %d",exp->e_beg,offs(exp)); | |
3498 | break; | |
6d27d3a2 | 3499 | |
f8701a3f SC |
3500 | case SEG_ABSENT: |
3501 | /* Do the same thing the VAX asm does */ | |
3502 | seg(exp)=SEG_ABSOLUTE; | |
3503 | adds(exp)=0; | |
3504 | subs(exp)=0; | |
fecd2382 | 3505 | offs(exp)=0; |
f8701a3f SC |
3506 | if(ok==10) { |
3507 | as_warn("expression out of range: defaulting to 1"); | |
3508 | offs(exp)=1; | |
3509 | } | |
3510 | break; | |
3511 | case SEG_ABSOLUTE: | |
3512 | switch(ok) { | |
3513 | case 10: | |
3514 | if(offs(exp)<1 || offs(exp)>8) { | |
3515 | as_warn("expression out of range: defaulting to 1"); | |
3516 | offs(exp)=1; | |
3517 | } | |
3518 | break; | |
3519 | case 20: | |
3520 | if(offs(exp)<0 || offs(exp)>7) | |
3521 | goto outrange; | |
3522 | break; | |
3523 | case 30: | |
3524 | if(offs(exp)<0 || offs(exp)>15) | |
3525 | goto outrange; | |
3526 | break; | |
3527 | case 40: | |
3528 | if(offs(exp)<0 || offs(exp)>32) | |
3529 | goto outrange; | |
3530 | break; | |
3531 | case 50: | |
3532 | if(offs(exp)<0 || offs(exp)>127) | |
3533 | goto outrange; | |
3534 | break; | |
3535 | case 55: | |
3536 | if(offs(exp)<-64 || offs(exp)>63) | |
3537 | goto outrange; | |
3538 | break; | |
3539 | case 60: | |
3540 | if(offs(exp)<-128 || offs(exp)>127) | |
3541 | goto outrange; | |
3542 | break; | |
3543 | case 70: | |
3544 | if(offs(exp)<0 || offs(exp)>4095) { | |
3545 | outrange: | |
3546 | as_warn("expression out of range: defaulting to 0"); | |
3547 | offs(exp)=0; | |
3548 | } | |
3549 | break; | |
3550 | default: | |
3551 | break; | |
3552 | } | |
3553 | break; | |
3554 | case SEG_TEXT: | |
3555 | case SEG_DATA: | |
3556 | case SEG_BSS: | |
3557 | case SEG_UNKNOWN: | |
3558 | case SEG_DIFFERENCE: | |
3559 | if(ok>=10 && ok<=70) { | |
3560 | seg(exp)=SEG_ABSOLUTE; | |
3561 | adds(exp)=0; | |
3562 | subs(exp)=0; | |
3563 | offs(exp)= (ok==10) ? 1 : 0; | |
3564 | as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp->e_beg,offs(exp)); | |
3565 | } | |
3566 | break; | |
3567 | case SEG_BIG: | |
3568 | if(ok==80 && offs(exp)<0) { /* HACK! Turn it into a long */ | |
3569 | LITTLENUM_TYPE words[6]; | |
6d27d3a2 | 3570 | |
f8701a3f SC |
3571 | gen_to_words(words,2,8L);/* These numbers are magic! */ |
3572 | seg(exp)=SEG_ABSOLUTE; | |
3573 | adds(exp)=0; | |
3574 | subs(exp)=0; | |
3575 | offs(exp)=words[1]|(words[0]<<16); | |
3576 | } else if(ok!=0) { | |
3577 | seg(exp)=SEG_ABSOLUTE; | |
3578 | adds(exp)=0; | |
3579 | subs(exp)=0; | |
3580 | offs(exp)= (ok==10) ? 1 : 0; | |
3581 | as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp->e_beg,offs(exp)); | |
3582 | } | |
3583 | break; | |
fecd2382 | 3584 | default: |
f8701a3f | 3585 | as_fatal("failed sanity check."); |
a39116f1 | 3586 | } |
f8701a3f SC |
3587 | if(input_line_pointer!=exp->e_end+1) |
3588 | as_bad("Ignoring junk after expression"); | |
3589 | exp->e_end[1]=c_save; | |
3590 | input_line_pointer=save_in; | |
3591 | if(exp->e_siz) { | |
3592 | switch(exp->e_siz) { | |
3593 | case 1: | |
3594 | if(!isbyte(offs(exp))) | |
3595 | as_warn("expression doesn't fit in BYTE"); | |
3596 | break; | |
3597 | case 2: | |
3598 | if(!isword(offs(exp))) | |
3599 | as_warn("expression doesn't fit in WORD"); | |
3600 | break; | |
3601 | } | |
a39116f1 | 3602 | } |
f8701a3f | 3603 | return offs(exp); |
fecd2382 RP |
3604 | #endif |
3605 | } /* get_num() */ | |
3606 | ||
3607 | /* These are the back-ends for the various machine dependent pseudo-ops. */ | |
f6e504fe | 3608 | void demand_empty_rest_of_line(); /* Hate those extra verbose names */ |
fecd2382 RP |
3609 | |
3610 | static void s_data1() { | |
f8701a3f SC |
3611 | subseg_new(SEG_DATA,1); |
3612 | demand_empty_rest_of_line(); | |
fecd2382 RP |
3613 | } /* s_data1() */ |
3614 | ||
3615 | static void s_data2() { | |
f8701a3f SC |
3616 | subseg_new(SEG_DATA,2); |
3617 | demand_empty_rest_of_line(); | |
fecd2382 RP |
3618 | } /* s_data2() */ |
3619 | ||
6d27d3a2 | 3620 | static void s_bss() |
a1765cf0 | 3621 | { |
6d27d3a2 | 3622 | /* We don't support putting frags in the BSS segment, we fake it |
a1765cf0 SC |
3623 | by marking in_bss, then looking at s_skip for clues */ |
3624 | ||
3625 | subseg_new(SEG_BSS, 0); | |
f8701a3f | 3626 | demand_empty_rest_of_line(); |
fecd2382 RP |
3627 | } /* s_bss() */ |
3628 | ||
3629 | static void s_even() { | |
f8701a3f SC |
3630 | register int temp; |
3631 | register long temp_fill; | |
6d27d3a2 | 3632 | |
f8701a3f SC |
3633 | temp = 1; /* JF should be 2? */ |
3634 | temp_fill = get_absolute_expression (); | |
3635 | if ( ! need_pass_2 ) /* Never make frag if expect extra pass. */ | |
3636 | frag_align (temp, (int)temp_fill); | |
3637 | demand_empty_rest_of_line(); | |
fecd2382 RP |
3638 | } /* s_even() */ |
3639 | ||
3640 | static void s_proc() { | |
f8701a3f | 3641 | demand_empty_rest_of_line(); |
fecd2382 RP |
3642 | } /* s_proc() */ |
3643 | ||
3644 | /* s_space is defined in read.c .skip is simply an alias to it. */ | |
3645 | ||
7c15cbe8 RP |
3646 | /* |
3647 | * md_parse_option | |
3648 | * Invocation line includes a switch not recognized by the base assembler. | |
3649 | * See if it's a processor-specific option. These are: | |
3650 | * | |
3651 | * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040 | |
3652 | * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851 | |
3653 | * Select the architecture. Instructions or features not | |
3654 | * supported by the selected architecture cause fatal | |
3655 | * errors. More than one may be specified. The default is | |
3656 | * -m68020 -m68851 -m68881. Note that -m68008 is a synonym | |
3657 | * for -m68000, and -m68882 is a synonym for -m68881. | |
3658 | * | |
a39116f1 RP |
3659 | * MAYBE_FLOAT_TOO is defined below so that specifying a processor type |
3660 | * (e.g. m68020) also requests that float instructions be included. This | |
3661 | * is the default setup, mostly to avoid hassling users. A better | |
3662 | * rearrangement of this structure would be to add an option to DENY | |
3663 | * floating point opcodes, for people who want to really know there's none | |
3664 | * of that funny floaty stuff going on. FIXME-later. | |
7c15cbe8 | 3665 | */ |
a39116f1 RP |
3666 | #ifndef MAYBE_FLOAT_TOO |
3667 | #define MAYBE_FLOAT_TOO m68881 | |
3668 | #endif | |
7c15cbe8 RP |
3669 | |
3670 | int md_parse_option(argP,cntP,vecP) | |
f8701a3f SC |
3671 | char **argP; |
3672 | int *cntP; | |
3673 | char ***vecP; | |
fecd2382 | 3674 | { |
f8701a3f SC |
3675 | switch(**argP) { |
3676 | case 'l': /* -l means keep external to 2 bit offset | |
3677 | rather than 16 bit one */ | |
3678 | break; | |
6d27d3a2 | 3679 | |
f8701a3f SC |
3680 | case 'S': /* -S means that jbsr's always turn into jsr's. */ |
3681 | break; | |
6d27d3a2 | 3682 | |
f8701a3f SC |
3683 | case 'A': |
3684 | (*argP)++; | |
3685 | /* intentional fall-through */ | |
3686 | case 'm': | |
3687 | (*argP)++; | |
6d27d3a2 | 3688 | |
f8701a3f SC |
3689 | if (**argP=='c') { |
3690 | (*argP)++; | |
3691 | } /* allow an optional "c" */ | |
6d27d3a2 | 3692 | |
f8701a3f SC |
3693 | if (!strcmp(*argP, "68000") |
3694 | || !strcmp(*argP, "68008")) { | |
3695 | current_architecture |= m68000; | |
3696 | } else if (!strcmp(*argP, "68010")) { | |
fecd2382 | 3697 | #ifdef TE_SUN |
f8701a3f | 3698 | omagic= 1<<16|OMAGIC; |
fecd2382 | 3699 | #endif |
f8701a3f | 3700 | current_architecture |= m68010; |
6d27d3a2 KR |
3701 | |
3702 | } else if (!strcmp(*argP, "68020")) { | |
f8701a3f | 3703 | current_architecture |= m68020 | MAYBE_FLOAT_TOO; |
6d27d3a2 KR |
3704 | |
3705 | } else if (!strcmp(*argP, "68030")) { | |
f8701a3f | 3706 | current_architecture |= m68030 | MAYBE_FLOAT_TOO; |
6d27d3a2 KR |
3707 | |
3708 | } else if (!strcmp(*argP, "68040")) { | |
f8701a3f | 3709 | current_architecture |= m68040 | MAYBE_FLOAT_TOO; |
6d27d3a2 | 3710 | |
7c15cbe8 | 3711 | #ifndef NO_68881 |
f8701a3f SC |
3712 | } else if (!strcmp(*argP, "68881")) { |
3713 | current_architecture |= m68881; | |
6d27d3a2 | 3714 | |
f8701a3f SC |
3715 | } else if (!strcmp(*argP, "68882")) { |
3716 | current_architecture |= m68882; | |
6d27d3a2 | 3717 | |
7c15cbe8 RP |
3718 | #endif /* NO_68881 */ |
3719 | #ifndef NO_68851 | |
6d27d3a2 | 3720 | } else if (!strcmp(*argP,"68851")) { |
f8701a3f | 3721 | current_architecture |= m68851; |
6d27d3a2 | 3722 | |
7c15cbe8 | 3723 | #endif /* NO_68851 */ |
f8701a3f SC |
3724 | } else { |
3725 | as_warn("Unknown architecture, \"%s\". option ignored", *argP); | |
3726 | } /* switch on architecture */ | |
6d27d3a2 | 3727 | |
f8701a3f | 3728 | while(**argP) (*argP)++; |
6d27d3a2 | 3729 | |
f8701a3f | 3730 | break; |
6d27d3a2 | 3731 | |
f8701a3f SC |
3732 | case 'p': |
3733 | if (!strcmp(*argP,"pic")) { | |
3734 | (*argP) += 3; | |
3735 | break; /* -pic, Position Independent Code */ | |
3736 | } else { | |
3737 | return(0); | |
3738 | } /* pic or not */ | |
6d27d3a2 | 3739 | |
f8701a3f SC |
3740 | default: |
3741 | return 0; | |
3742 | } | |
3743 | return 1; | |
fecd2382 RP |
3744 | } |
3745 | ||
3746 | ||
3747 | #ifdef TEST2 | |
3748 | ||
3749 | /* TEST2: Test md_assemble() */ | |
3750 | /* Warning, this routine probably doesn't work anymore */ | |
3751 | ||
3752 | main() | |
3753 | { | |
f8701a3f SC |
3754 | struct m68k_it the_ins; |
3755 | char buf[120]; | |
3756 | char *cp; | |
3757 | int n; | |
6d27d3a2 | 3758 | |
f8701a3f SC |
3759 | m68k_ip_begin(); |
3760 | for(;;) { | |
3761 | if(!gets(buf) || !*buf) | |
3762 | break; | |
3763 | if(buf[0]=='|' || buf[1]=='.') | |
3764 | continue; | |
3765 | for(cp=buf;*cp;cp++) | |
3766 | if(*cp=='\t') | |
3767 | *cp=' '; | |
3768 | if(is_label(buf)) | |
3769 | continue; | |
3770 | memset(&the_ins, '\0', sizeof(the_ins)); | |
3771 | m68k_ip(&the_ins,buf); | |
3772 | if(the_ins.error) { | |
3773 | printf("Error %s in %s\n",the_ins.error,buf); | |
3774 | } else { | |
3775 | printf("Opcode(%d.%s): ",the_ins.numo,the_ins.args); | |
3776 | for(n=0;n<the_ins.numo;n++) | |
3777 | printf(" 0x%x",the_ins.opcode[n]&0xffff); | |
3778 | printf(" "); | |
3779 | print_the_insn(&the_ins.opcode[0],stdout); | |
3780 | (void)putchar('\n'); | |
3781 | } | |
3782 | for(n=0;n<strlen(the_ins.args)/2;n++) { | |
3783 | if(the_ins.operands[n].error) { | |
3784 | printf("op%d Error %s in %s\n",n,the_ins.operands[n].error,buf); | |
3785 | continue; | |
3786 | } | |
3787 | printf("mode %d, reg %d, ",the_ins.operands[n].mode,the_ins.operands[n].reg); | |
3788 | if(the_ins.operands[n].b_const) | |
3789 | printf("Constant: '%.*s', ",1+the_ins.operands[n].e_const-the_ins.operands[n].b_const,the_ins.operands[n].b_const); | |
3790 | printf("ireg %d, isiz %d, imul %d, ",the_ins.operands[n].ireg,the_ins.operands[n].isiz,the_ins.operands[n].imul); | |
3791 | if(the_ins.operands[n].b_iadd) | |
3792 | printf("Iadd: '%.*s',",1+the_ins.operands[n].e_iadd-the_ins.operands[n].b_iadd,the_ins.operands[n].b_iadd); | |
3793 | (void)putchar('\n'); | |
3794 | } | |
a39116f1 | 3795 | } |
f8701a3f SC |
3796 | m68k_ip_end(); |
3797 | return 0; | |
fecd2382 RP |
3798 | } |
3799 | ||
3800 | is_label(str) | |
f8701a3f | 3801 | char *str; |
fecd2382 | 3802 | { |
f8701a3f SC |
3803 | while(*str==' ') |
3804 | str++; | |
3805 | while(*str && *str!=' ') | |
3806 | str++; | |
3807 | if(str[-1]==':' || str[1]=='=') | |
3808 | return 1; | |
3809 | return 0; | |
fecd2382 RP |
3810 | } |
3811 | ||
3812 | #endif | |
3813 | ||
3814 | /* Possible states for relaxation: | |
6d27d3a2 | 3815 | |
a39116f1 RP |
3816 | 0 0 branch offset byte (bra, etc) |
3817 | 0 1 word | |
3818 | 0 2 long | |
6d27d3a2 | 3819 | |
a39116f1 RP |
3820 | 1 0 indexed offsets byte a0@(32,d4:w:1) etc |
3821 | 1 1 word | |
3822 | 1 2 long | |
6d27d3a2 | 3823 | |
a39116f1 RP |
3824 | 2 0 two-offset index word-word a0@(32,d4)@(45) etc |
3825 | 2 1 word-long | |
3826 | 2 2 long-word | |
3827 | 2 3 long-long | |
6d27d3a2 | 3828 | |
a39116f1 | 3829 | */ |
fecd2382 RP |
3830 | |
3831 | ||
3832 | ||
3833 | #ifdef DONTDEF | |
3834 | abort() | |
3835 | { | |
f8701a3f SC |
3836 | printf("ABORT!\n"); |
3837 | exit(12); | |
fecd2382 RP |
3838 | } |
3839 | ||
3840 | print_frags() | |
3841 | { | |
f8701a3f SC |
3842 | fragS *fragP; |
3843 | extern fragS *text_frag_root; | |
6d27d3a2 | 3844 | |
f8701a3f SC |
3845 | for(fragP=text_frag_root;fragP;fragP=fragP->fr_next) { |
3846 | printf("addr %lu next 0x%x fix %ld var %ld symbol 0x%x offset %ld\n", | |
3847 | fragP->fr_address,fragP->fr_next,fragP->fr_fix,fragP->fr_var,fragP->fr_symbol,fragP->fr_offset); | |
3848 | printf("opcode 0x%x type %d subtype %d\n\n",fragP->fr_opcode,fragP->fr_type,fragP->fr_subtype); | |
3849 | } | |
3850 | fflush(stdout); | |
3851 | return 0; | |
fecd2382 RP |
3852 | } |
3853 | #endif | |
3854 | ||
3855 | #ifdef DONTDEF | |
3856 | /*VARARGS1*/ | |
3857 | panic(format,args) | |
f8701a3f | 3858 | char *format; |
fecd2382 | 3859 | { |
f8701a3f SC |
3860 | fputs("Internal error:",stderr); |
3861 | _doprnt(format,&args,stderr); | |
3862 | (void)putc('\n',stderr); | |
3863 | as_where(); | |
3864 | abort(); | |
fecd2382 RP |
3865 | } |
3866 | #endif | |
3867 | ||
3868 | /* We have no need to default values of symbols. */ | |
3869 | ||
3870 | /* ARGSUSED */ | |
3871 | symbolS * | |
a39116f1 RP |
3872 | md_undefined_symbol (name) |
3873 | char *name; | |
fecd2382 | 3874 | { |
f8701a3f | 3875 | return 0; |
fecd2382 RP |
3876 | } |
3877 | ||
6d27d3a2 | 3878 | /* Parse an operand that is machine-specific. |
fecd2382 RP |
3879 | We just return without modifying the expression if we have nothing |
3880 | to do. */ | |
3881 | ||
3882 | /* ARGSUSED */ | |
3883 | void | |
a39116f1 RP |
3884 | md_operand (expressionP) |
3885 | expressionS *expressionP; | |
fecd2382 RP |
3886 | { |
3887 | } | |
3888 | ||
3889 | /* Round up a section size to the appropriate boundary. */ | |
3890 | long | |
a39116f1 RP |
3891 | md_section_align (segment, size) |
3892 | segT segment; | |
3893 | long size; | |
fecd2382 | 3894 | { |
f8701a3f | 3895 | return size; /* Byte alignment is fine */ |
fecd2382 RP |
3896 | } |
3897 | ||
3898 | /* Exactly what point is a PC-relative offset relative TO? | |
3899 | On the 68k, they're relative to the address of the offset, plus | |
3900 | its size. (??? Is this right? FIXME-SOON!) */ | |
3901 | long | |
a39116f1 RP |
3902 | md_pcrel_from (fixP) |
3903 | fixS *fixP; | |
fecd2382 | 3904 | { |
f8701a3f | 3905 | return(fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address); |
fecd2382 RP |
3906 | } |
3907 | ||
fecd2382 RP |
3908 | /* |
3909 | * Local Variables: | |
3910 | * comment-column: 0 | |
3911 | * fill-column: 131 | |
3912 | * End: | |
3913 | */ | |
3914 | ||
3915 | /* end of tc-m68k.c */ |