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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
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252b5132 1/* tc-m68k.c -- Assemble for the m68k family
8fce3f5e 2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
252b5132
RH		 3 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22#include <ctype.h>
23#include "as.h"
24#include "obstack.h"
25#include "subsegs.h"
26
27#include "opcode/m68k.h"
28#include "m68k-parse.h"
29
0d96863f
CM		 30#if defined (OBJ_ELF)
31#include "elf/m68k.h"
32#endif
33
252b5132
RH		 34/* This string holds the chars that always start a comment. If the
35 pre-processor is disabled, these aren't very useful. The macro
36 tc_comment_chars points to this. We use this, rather than the
37 usual comment_chars, so that the --bitwise-or option will work. */
38#if defined (TE_SVR4) || defined (TE_DELTA)
39const char *m68k_comment_chars = "|#";
40#else
41const char *m68k_comment_chars = "|";
42#endif
43
44/* This array holds the chars that only start a comment at the beginning of
45 a line. If the line seems to have the form '# 123 filename'
46 .line and .file directives will appear in the pre-processed output */
47/* Note that input_file.c hand checks for '#' at the beginning of the
48 first line of the input file. This is because the compiler outputs
92774660
KH		 49 #NO_APP at the beginning of its output. */
50/* Also note that comments like this one will always work. */
252b5132
RH		 51const char line_comment_chars[] = "#*";
52
63a0b638 53const char line_separator_chars[] = ";";
252b5132
RH		 54
55/* Chars that can be used to separate mant from exp in floating point nums */
56CONST char EXP_CHARS[] = "eE";
57
58/* Chars that mean this number is a floating point constant, as
59 in "0f12.456" or "0d1.2345e12". */
60
61CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
62
63/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
64 changed in read.c . Ideally it shouldn't have to know about it at all,
65 but nothing is ideal around here. */
66
67const int md_reloc_size = 8; /* Size of relocation record */
68
69/* Are we trying to generate PIC code? If so, absolute references
70 ought to be made into linkage table references or pc-relative
92774660 71 references. Not implemented. For ELF there are other means
252b5132
RH		 72 to denote pic relocations. */
73int flag_want_pic;
74
75static int flag_short_refs; /* -l option */
76static int flag_long_jumps; /* -S option */
28e7409f 77static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 78
79#ifdef REGISTER_PREFIX_OPTIONAL
80int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
81#else
82int flag_reg_prefix_optional;
83#endif
84
85/* Whether --register-prefix-optional was used on the command line. */
86static int reg_prefix_optional_seen;
87
88/* The floating point coprocessor to use by default. */
89static enum m68k_register m68k_float_copnum = COP1;
90
91/* If this is non-zero, then references to number(%pc) will be taken
92 to refer to number, rather than to %pc + number. */
93static int m68k_abspcadd;
94
95/* If this is non-zero, then the quick forms of the move, add, and sub
96 instructions are used when possible. */
97static int m68k_quick = 1;
98
99/* If this is non-zero, then if the size is not specified for a base
100 or outer displacement, the assembler assumes that the size should
101 be 32 bits. */
102static int m68k_rel32 = 1;
103
104/* This is non-zero if m68k_rel32 was set from the command line. */
105static int m68k_rel32_from_cmdline;
106
107/* The default width to use for an index register when using a base
108 displacement. */
109static enum m68k_size m68k_index_width_default = SIZE_LONG;
110
111/* We want to warn if any text labels are misaligned. In order to get
112 the right line number, we need to record the line number for each
113 label. */
114
115struct label_line
116{
117 struct label_line *next;
118 symbolS *label;
119 char *file;
120 unsigned int line;
121 int text;
122};
123
124/* The list of labels. */
125
126static struct label_line *labels;
127
128/* The current label. */
129
130static struct label_line *current_label;
131
132/* Its an arbitrary name: This means I don't approve of it */
133/* See flames below */
134static struct obstack robyn;
135
252b5132
RH		 136struct m68k_incant
137 {
138 const char *m_operands;
139 unsigned long m_opcode;
140 short m_opnum;
141 short m_codenum;
142 int m_arch;
143 struct m68k_incant *m_next;
144 };
145
146#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
147#define gettwo(x) (((x)->m_opcode)&0xffff)
148
149static const enum m68k_register m68000_control_regs[] = { 0 };
150static const enum m68k_register m68010_control_regs[] = {
151 SFC, DFC, USP, VBR,
152 0
153};
154static const enum m68k_register m68020_control_regs[] = {
155 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
156 0
157};
158static const enum m68k_register m68040_control_regs[] = {
159 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
160 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
161 0
162};
163static const enum m68k_register m68060_control_regs[] = {
164 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
165 USP, VBR, URP, SRP, PCR,
166 0
167};
6da466c7 168static const enum m68k_register mcf_control_regs[] = {
92774660 169 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
252b5132
RH		 170 RAMBAR0, RAMBAR1, MBAR,
171 0
172};
173#define cpu32_control_regs m68010_control_regs
174
175static const enum m68k_register *control_regs;
176
177/* internal form of a 68020 instruction */
178struct m68k_it
179{
180 const char *error;
181 const char *args; /* list of opcode info */
182 int numargs;
183
184 int numo; /* Number of shorts in opcode */
185 short opcode[11];
186
187 struct m68k_op operands[6];
188
189 int nexp; /* number of exprs in use */
190 struct m68k_exp exprs[4];
191
192 int nfrag; /* Number of frags we have to produce */
193 struct
194 {
195 int fragoff; /* Where in the current opcode the frag ends */
196 symbolS *fadd;
197 offsetT foff;
198 int fragty;
199 }
200 fragb[4];
201
202 int nrel; /* Num of reloc strucs in use */
203 struct
204 {
205 int n;
206 expressionS exp;
207 char wid;
208 char pcrel;
209 /* In a pc relative address the difference between the address
210 of the offset and the address that the offset is relative
211 to. This depends on the addressing mode. Basically this
212 is the value to put in the offset field to address the
213 first byte of the offset, without regarding the special
214 significance of some values (in the branch instruction, for
215 example). */
216 int pcrel_fix;
217#ifdef OBJ_ELF
218 /* Whether this expression needs special pic relocation, and if
219 so, which. */
220 enum pic_relocation pic_reloc;
221#endif
222 }
223 reloc[5]; /* Five is enough??? */
224};
225
6da466c7 226#define cpu_of_arch(x) ((x) & (m68000up|mcf))
252b5132
RH		 227#define float_of_arch(x) ((x) & mfloat)
228#define mmu_of_arch(x) ((x) & mmmu)
6da466c7 229#define arch_coldfire_p(x) (((x) & mcf) != 0)
252b5132
RH		 230
231/* Macros for determining if cpu supports a specific addressing mode */
232#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
233
234static struct m68k_it the_ins; /* the instruction being assembled */
235
236#define op(ex) ((ex)->exp.X_op)
237#define adds(ex) ((ex)->exp.X_add_symbol)
238#define subs(ex) ((ex)->exp.X_op_symbol)
239#define offs(ex) ((ex)->exp.X_add_number)
240
241/* Macros for adding things to the m68k_it struct */
242
243#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
244
245/* Static functions. */
246
247static void insop PARAMS ((int, const struct m68k_incant *));
248static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
249static void add_frag PARAMS ((symbolS *, offsetT, int));
250
251/* Like addword, but goes BEFORE general operands */
252static void
253insop (w, opcode)
254 int w;
255 const struct m68k_incant *opcode;
256{
257 int z;
258 for(z=the_ins.numo;z>opcode->m_codenum;--z)
259 the_ins.opcode[z]=the_ins.opcode[z-1];
260 for(z=0;z<the_ins.nrel;z++)
261 the_ins.reloc[z].n+=2;
262 for (z = 0; z < the_ins.nfrag; z++)
263 the_ins.fragb[z].fragoff++;
264 the_ins.opcode[opcode->m_codenum]=w;
265 the_ins.numo++;
266}
267
268/* The numo+1 kludge is so we can hit the low order byte of the prev word.
269 Blecch. */
270static void
271add_fix (width, exp, pc_rel, pc_fix)
272 int width;
273 struct m68k_exp *exp;
274 int pc_rel;
275 int pc_fix;
276{
277 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
278 ? (the_ins.numo*2-1)
279 : (((width)=='b')
280 ? (the_ins.numo*2+1)
281 : (the_ins.numo*2)));
282 the_ins.reloc[the_ins.nrel].exp = exp->exp;
283 the_ins.reloc[the_ins.nrel].wid = width;
284 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
285#ifdef OBJ_ELF
286 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
287#endif
288 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
289}
290
291/* Cause an extra frag to be generated here, inserting up to 10 bytes
292 (that value is chosen in the frag_var call in md_assemble). TYPE
293 is the subtype of the frag to be generated; its primary type is
294 rs_machine_dependent.
295
296 The TYPE parameter is also used by md_convert_frag_1 and
297 md_estimate_size_before_relax. The appropriate type of fixup will
298 be emitted by md_convert_frag_1.
299
300 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
301static void
302add_frag (add, off, type)
303 symbolS *add;
304 offsetT off;
305 int type;
306{
307 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
308 the_ins.fragb[the_ins.nfrag].fadd=add;
309 the_ins.fragb[the_ins.nfrag].foff=off;
310 the_ins.fragb[the_ins.nfrag++].fragty=type;
311}
312
313#define isvar(ex) \
314 (op (ex) != O_constant && op (ex) != O_big)
315
316static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
317static int get_num PARAMS ((struct m68k_exp *exp, int ok));
318static void m68k_ip PARAMS ((char *));
319static void insert_reg PARAMS ((const char *, int));
320static void select_control_regs PARAMS ((void));
321static void init_regtable PARAMS ((void));
322static int reverse_16_bits PARAMS ((int in));
323static int reverse_8_bits PARAMS ((int in));
324static void install_gen_operand PARAMS ((int mode, int val));
325static void install_operand PARAMS ((int mode, int val));
326static void s_bss PARAMS ((int));
327static void s_data1 PARAMS ((int));
328static void s_data2 PARAMS ((int));
329static void s_even PARAMS ((int));
330static void s_proc PARAMS ((int));
331static void mri_chip PARAMS ((void));
332static void s_chip PARAMS ((int));
333static void s_fopt PARAMS ((int));
334static void s_opt PARAMS ((int));
335static void s_reg PARAMS ((int));
336static void s_restore PARAMS ((int));
337static void s_save PARAMS ((int));
338static void s_mri_if PARAMS ((int));
339static void s_mri_else PARAMS ((int));
340static void s_mri_endi PARAMS ((int));
341static void s_mri_break PARAMS ((int));
342static void s_mri_next PARAMS ((int));
343static void s_mri_for PARAMS ((int));
344static void s_mri_endf PARAMS ((int));
345static void s_mri_repeat PARAMS ((int));
346static void s_mri_until PARAMS ((int));
347static void s_mri_while PARAMS ((int));
348static void s_mri_endw PARAMS ((int));
349static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
350static void md_convert_frag_1 PARAMS ((fragS *));
351
352static int current_architecture;
353
354struct m68k_cpu {
355 unsigned long arch;
356 const char *name;
357 int alias;
358};
359
360static const struct m68k_cpu archs[] = {
361 { m68000, "68000", 0 },
362 { m68010, "68010", 0 },
363 { m68020, "68020", 0 },
364 { m68030, "68030", 0 },
365 { m68040, "68040", 0 },
366 { m68060, "68060", 0 },
367 { cpu32, "cpu32", 0 },
368 { m68881, "68881", 0 },
369 { m68851, "68851", 0 },
370 { mcf5200, "5200", 0 },
6da466c7
ILT		 371 { mcf5206e, "5206e", 0 },
372 { mcf5307, "5307", 0},
252b5132
RH		 373 /* Aliases (effectively, so far as gas is concerned) for the above
374 cpus. */
375 { m68020, "68k", 1 },
376 { m68000, "68008", 1 },
377 { m68000, "68302", 1 },
378 { m68000, "68306", 1 },
379 { m68000, "68307", 1 },
380 { m68000, "68322", 1 },
381 { m68000, "68356", 1 },
382 { m68000, "68ec000", 1 },
383 { m68000, "68hc000", 1 },
384 { m68000, "68hc001", 1 },
385 { m68020, "68ec020", 1 },
386 { m68030, "68ec030", 1 },
387 { m68040, "68ec040", 1 },
388 { m68060, "68ec060", 1 },
389 { cpu32, "68330", 1 },
390 { cpu32, "68331", 1 },
391 { cpu32, "68332", 1 },
392 { cpu32, "68333", 1 },
393 { cpu32, "68334", 1 },
394 { cpu32, "68336", 1 },
395 { cpu32, "68340", 1 },
396 { cpu32, "68341", 1 },
397 { cpu32, "68349", 1 },
398 { cpu32, "68360", 1 },
399 { m68881, "68882", 1 },
6da466c7
ILT		 400 { mcf5200, "5202", 1 },
401 { mcf5200, "5204", 1 },
402 { mcf5200, "5206", 1 },
252b5132
RH		 403};
404
405static const int n_archs = sizeof (archs) / sizeof (archs[0]);
406
151337e8
NC		 407/* This is the assembler relaxation table for m68k. m68k is a rich CISC
408 architecture and we have a lot of relaxation modes. */
252b5132 409
151337e8
NC		 410/* Macros used in the relaxation code. */
411#define TAB(x,y) (((x) << 2) + (y))
412#define TABTYPE(x) ((x) >> 2)
413
414/* Relaxation states. */
415#define BYTE 0
416#define SHORT 1
417#define LONG 2
418#define SZ_UNDEF 3
419
420/* Here are all the relaxation modes we support. First we can relax ordinary
421 branches. On 68020 and higher and on CPU32 all branch instructions take
422 three forms, so on these CPUs all branches always remain as such. When we
423 have to expand to the LONG form on a 68000, though, we substitute an
424 absolute jump instead. This is a direct replacement for unconditional
425 branches and a branch over a jump for conditional branches. However, if the
426 user requires PIC and disables this with --pcrel, we can only relax between
427 BYTE and SHORT forms, punting if that isn't enough. This gives us four
428 different relaxation modes for branches: */
429
430#define BRANCHBWL 1 /* branch byte, word, or long */
431#define BRABSJUNC 2 /* absolute jump for LONG, unconditional */
432#define BRABSJCOND 3 /* absolute jump for LONG, conditional */
433#define BRANCHBW 4 /* branch byte or word */
434
435/* We also relax coprocessor branches and DBcc's. All CPUs that support
436 coprocessor branches support them in word and long forms, so we have only
437 one relaxation mode for them. DBcc's are word only on all CPUs. We can
438 relax them to the LONG form with a branch-around sequence. This sequence
439 can use a long branch (if available) or an absolute jump (if acceptable).
440 This gives us two relaxation modes. If long branches are not available and
441 absolute jumps are not acceptable, we don't relax DBcc's. */
442
443#define FBRANCH 5 /* coprocessor branch */
444#define DBCCLBR 6 /* DBcc relaxable with a long branch */
445#define DBCCABSJ 7 /* DBcc relaxable with an absolute jump */
446
447/* That's all for instruction relaxation. However, we also relax PC-relative
448 operands. Specifically, we have three operand relaxation modes. On the
449 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
450 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
451 two. Also PC+displacement+index operands in their simple form (with a non-
452 suppressed index without memory indirection) are supported on all CPUs, but
453 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
454 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
455 form of the PC+displacement+index operand. Finally, some absolute operands
456 can be relaxed down to 16-bit PC-relative. */
457
458#define PCREL1632 8 /* 16-bit or 32-bit PC-relative */
459#define PCINDEX 9 /* PC+displacement+index */
460#define ABSTOPCREL 10 /* absolute relax down to 16-bit PC-relative */
252b5132
RH		 461
462/* Note that calls to frag_var need to specify the maximum expansion
463 needed; this is currently 10 bytes for DBCC. */
464
465/* The fields are:
466 How far Forward this mode will reach:
467 How far Backward this mode will reach:
468 How many bytes this mode will add to the size of the frag
469 Which mode to go to if the offset won't fit in this one
470 */
471relax_typeS md_relax_table[] =
472{
473 {1, 1, 0, 0}, /* First entries aren't used */
474 {1, 1, 0, 0}, /* For no good reason except */
475 {1, 1, 0, 0}, /* that the VAX doesn't either */
476 {1, 1, 0, 0},
477
151337e8
NC		 478 {(127), (-128), 0, TAB (BRANCHBWL, SHORT)},
479 {(32767), (-32768), 2, TAB (BRANCHBWL, LONG)},
252b5132
RH		 480 {0, 0, 4, 0},
481 {1, 1, 0, 0},
482
151337e8
NC		 483 {(127), (-128), 0, TAB (BRABSJUNC, SHORT)},
484 {(32767), (-32768), 2, TAB (BRABSJUNC, LONG)},
252b5132
RH		 485 {0, 0, 4, 0},
486 {1, 1, 0, 0},
487
151337e8
NC		 488 {(127), (-128), 0, TAB (BRABSJCOND, SHORT)},
489 {(32767), (-32768), 2, TAB (BRABSJCOND, LONG)},
490 {0, 0, 6, 0},
491 {1, 1, 0, 0},
492
493 {(127), (-128), 0, TAB (BRANCHBW, SHORT)},
494 {0, 0, 2, 0},
495 {1, 1, 0, 0},
496 {1, 1, 0, 0},
497
498 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
499 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
252b5132
RH		 500 {0, 0, 4, 0},
501 {1, 1, 0, 0},
502
151337e8
NC		 503 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
504 {(32767), (-32768), 2, TAB (DBCCLBR, LONG)},
505 {0, 0, 10, 0},
252b5132
RH		 506 {1, 1, 0, 0},
507
508 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
151337e8
NC		 509 {(32767), (-32768), 2, TAB (DBCCABSJ, LONG)},
510 {0, 0, 10, 0},
252b5132
RH		 511 {1, 1, 0, 0},
512
151337e8
NC		 513 {1, 1, 0, 0}, /* PCREL1632 doesn't come BYTE */
514 {32767, -32768, 2, TAB (PCREL1632, LONG)},
252b5132
RH		 515 {0, 0, 6, 0},
516 {1, 1, 0, 0},
517
252b5132
RH		 518 {125, -130, 0, TAB (PCINDEX, SHORT)},
519 {32765, -32770, 2, TAB (PCINDEX, LONG)},
520 {0, 0, 4, 0},
521 {1, 1, 0, 0},
151337e8
NC		 522
523 {1, 1, 0, 0}, /* ABSTOPCREL doesn't come BYTE */
524 {(32767), (-32768), 2, TAB (ABSTOPCREL, LONG)},
525 {0, 0, 4, 0},
526 {1, 1, 0, 0},
252b5132
RH		 527};
528
529/* These are the machine dependent pseudo-ops. These are included so
530 the assembler can work on the output from the SUN C compiler, which
531 generates these.
532 */
533
534/* This table describes all the machine specific pseudo-ops the assembler
535 has to support. The fields are:
536 pseudo-op name without dot
537 function to call to execute this pseudo-op
538 Integer arg to pass to the function
539 */
540const pseudo_typeS md_pseudo_table[] =
541{
542 {"data1", s_data1, 0},
543 {"data2", s_data2, 0},
544 {"bss", s_bss, 0},
545 {"even", s_even, 0},
546 {"skip", s_space, 0},
547 {"proc", s_proc, 0},
548#if defined (TE_SUN3) || defined (OBJ_ELF)
549 {"align", s_align_bytes, 0},
550#endif
551#ifdef OBJ_ELF
552 {"swbeg", s_ignore, 0},
553#endif
554 {"extend", float_cons, 'x'},
555 {"ldouble", float_cons, 'x'},
556
557 /* The following pseudo-ops are supported for MRI compatibility. */
558 {"chip", s_chip, 0},
559 {"comline", s_space, 1},
560 {"fopt", s_fopt, 0},
561 {"mask2", s_ignore, 0},
562 {"opt", s_opt, 0},
563 {"reg", s_reg, 0},
564 {"restore", s_restore, 0},
565 {"save", s_save, 0},
566
567 {"if", s_mri_if, 0},
568 {"if.b", s_mri_if, 'b'},
569 {"if.w", s_mri_if, 'w'},
570 {"if.l", s_mri_if, 'l'},
571 {"else", s_mri_else, 0},
572 {"else.s", s_mri_else, 's'},
573 {"else.l", s_mri_else, 'l'},
574 {"endi", s_mri_endi, 0},
575 {"break", s_mri_break, 0},
576 {"break.s", s_mri_break, 's'},
577 {"break.l", s_mri_break, 'l'},
578 {"next", s_mri_next, 0},
579 {"next.s", s_mri_next, 's'},
580 {"next.l", s_mri_next, 'l'},
581 {"for", s_mri_for, 0},
582 {"for.b", s_mri_for, 'b'},
583 {"for.w", s_mri_for, 'w'},
584 {"for.l", s_mri_for, 'l'},
585 {"endf", s_mri_endf, 0},
586 {"repeat", s_mri_repeat, 0},
587 {"until", s_mri_until, 0},
588 {"until.b", s_mri_until, 'b'},
589 {"until.w", s_mri_until, 'w'},
590 {"until.l", s_mri_until, 'l'},
591 {"while", s_mri_while, 0},
592 {"while.b", s_mri_while, 'b'},
593 {"while.w", s_mri_while, 'w'},
594 {"while.l", s_mri_while, 'l'},
595 {"endw", s_mri_endw, 0},
596
597 {0, 0, 0}
598};
599
252b5132
RH		 600/* The mote pseudo ops are put into the opcode table, since they
601 don't start with a . they look like opcodes to gas.
602 */
603
604#ifdef M68KCOFF
605extern void obj_coff_section PARAMS ((int));
606#endif
607
608CONST pseudo_typeS mote_pseudo_table[] =
609{
610
611 {"dcl", cons, 4},
612 {"dc", cons, 2},
613 {"dcw", cons, 2},
614 {"dcb", cons, 1},
615
616 {"dsl", s_space, 4},
617 {"ds", s_space, 2},
618 {"dsw", s_space, 2},
619 {"dsb", s_space, 1},
620
621 {"xdef", s_globl, 0},
622#ifdef OBJ_ELF
623 {"align", s_align_bytes, 0},
624#else
625 {"align", s_align_ptwo, 0},
626#endif
627#ifdef M68KCOFF
628 {"sect", obj_coff_section, 0},
629 {"section", obj_coff_section, 0},
630#endif
631 {0, 0, 0}
632};
633
634#define issbyte(x) ((x)>=-128 && (x)<=127)
635#define isubyte(x) ((x)>=0 && (x)<=255)
636#define issword(x) ((x)>=-32768 && (x)<=32767)
637#define isuword(x) ((x)>=0 && (x)<=65535)
638
639#define isbyte(x) ((x)>= -255 && (x)<=255)
640#define isword(x) ((x)>=-65536 && (x)<=65535)
641#define islong(x) (1)
642
643extern char *input_line_pointer;
644
645static char mklower_table[256];
646#define mklower(c) (mklower_table[(unsigned char)(c)])
647static char notend_table[256];
648static char alt_notend_table[256];
649#define notend(s) \
650 (! (notend_table[(unsigned char) *s] \
651 || (*s == ':' \
652 && alt_notend_table[(unsigned char) s[1]])))
653
654#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
655
656#ifdef NO_PCREL_RELOCS
657
658int
659make_pcrel_absolute(fixP, add_number)
660 fixS *fixP;
661 long *add_number;
662{
663 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
664
665 /* rewrite the PC relative instructions to absolute address ones.
666 * these are rumoured to be faster, and the apollo linker refuses
667 * to deal with the PC relative relocations.
668 */
669 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
670 {
671 opcode[0] = 0x4e;
672 opcode[1] = 0xf9;
673 }
674 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
675 {
676 opcode[0] = 0x4e;
677 opcode[1] = 0xb9;
678 }
679 else
680 as_fatal (_("Unknown PC relative instruction"));
681 *add_number -= 4;
682 return 0;
683}
684
685#endif /* NO_PCREL_RELOCS */
686
687short
688tc_coff_fix2rtype (fixP)
689 fixS *fixP;
690{
691 if (fixP->fx_tcbit && fixP->fx_size == 4)
692 return R_RELLONG_NEG;
693#ifdef NO_PCREL_RELOCS
694 know (fixP->fx_pcrel == 0);
695 return (fixP->fx_size == 1 ? R_RELBYTE
696 : fixP->fx_size == 2 ? R_DIR16
697 : R_DIR32);
698#else
699 return (fixP->fx_pcrel ?
700 (fixP->fx_size == 1 ? R_PCRBYTE :
701 fixP->fx_size == 2 ? R_PCRWORD :
702 R_PCRLONG) :
703 (fixP->fx_size == 1 ? R_RELBYTE :
704 fixP->fx_size == 2 ? R_RELWORD :
705 R_RELLONG));
706#endif
707}
708
709#endif
710
711#ifdef OBJ_ELF
712
713/* Compute the relocation code for a fixup of SIZE bytes, using pc
714 relative relocation if PCREL is non-zero. PIC says whether a special
715 pic relocation was requested. */
716
717static bfd_reloc_code_real_type get_reloc_code
718 PARAMS ((int, int, enum pic_relocation));
719
720static bfd_reloc_code_real_type
721get_reloc_code (size, pcrel, pic)
722 int size;
723 int pcrel;
724 enum pic_relocation pic;
725{
726 switch (pic)
727 {
728 case pic_got_pcrel:
729 switch (size)
730 {
731 case 1:
732 return BFD_RELOC_8_GOT_PCREL;
733 case 2:
734 return BFD_RELOC_16_GOT_PCREL;
735 case 4:
736 return BFD_RELOC_32_GOT_PCREL;
737 }
738 break;
739
740 case pic_got_off:
741 switch (size)
742 {
743 case 1:
744 return BFD_RELOC_8_GOTOFF;
745 case 2:
746 return BFD_RELOC_16_GOTOFF;
747 case 4:
748 return BFD_RELOC_32_GOTOFF;
749 }
750 break;
751
752 case pic_plt_pcrel:
753 switch (size)
754 {
755 case 1:
756 return BFD_RELOC_8_PLT_PCREL;
757 case 2:
758 return BFD_RELOC_16_PLT_PCREL;
759 case 4:
760 return BFD_RELOC_32_PLT_PCREL;
761 }
762 break;
763
764 case pic_plt_off:
765 switch (size)
766 {
767 case 1:
768 return BFD_RELOC_8_PLTOFF;
769 case 2:
770 return BFD_RELOC_16_PLTOFF;
771 case 4:
772 return BFD_RELOC_32_PLTOFF;
773 }
774 break;
775
776 case pic_none:
777 if (pcrel)
778 {
779 switch (size)
780 {
781 case 1:
782 return BFD_RELOC_8_PCREL;
783 case 2:
784 return BFD_RELOC_16_PCREL;
785 case 4:
786 return BFD_RELOC_32_PCREL;
787 }
788 }
789 else
790 {
791 switch (size)
792 {
793 case 1:
794 return BFD_RELOC_8;
795 case 2:
796 return BFD_RELOC_16;
797 case 4:
798 return BFD_RELOC_32;
799 }
800 }
801 }
802
803 if (pcrel)
804 {
805 if (pic == pic_none)
806 as_bad (_("Can not do %d byte pc-relative relocation"), size);
807 else
808 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
809 }
810 else
811 {
812 if (pic == pic_none)
813 as_bad (_("Can not do %d byte relocation"), size);
814 else
815 as_bad (_("Can not do %d byte pic relocation"), size);
816 }
817
818 return BFD_RELOC_NONE;
819}
820
821/* Here we decide which fixups can be adjusted to make them relative
822 to the beginning of the section instead of the symbol. Basically
823 we need to make sure that the dynamic relocations are done
824 correctly, so in some cases we force the original symbol to be
825 used. */
826int
827tc_m68k_fix_adjustable (fixP)
828 fixS *fixP;
829{
92774660 830 /* Prevent all adjustments to global symbols. */
252b5132
RH		 831 if (S_IS_EXTERNAL (fixP->fx_addsy)
832 || S_IS_WEAK (fixP->fx_addsy))
833 return 0;
834
835 /* adjust_reloc_syms doesn't know about the GOT */
836 switch (fixP->fx_r_type)
837 {
838 case BFD_RELOC_8_GOT_PCREL:
839 case BFD_RELOC_16_GOT_PCREL:
840 case BFD_RELOC_32_GOT_PCREL:
841 case BFD_RELOC_8_GOTOFF:
842 case BFD_RELOC_16_GOTOFF:
843 case BFD_RELOC_32_GOTOFF:
844 case BFD_RELOC_8_PLT_PCREL:
845 case BFD_RELOC_16_PLT_PCREL:
846 case BFD_RELOC_32_PLT_PCREL:
847 case BFD_RELOC_8_PLTOFF:
848 case BFD_RELOC_16_PLTOFF:
849 case BFD_RELOC_32_PLTOFF:
850 return 0;
851
852 case BFD_RELOC_VTABLE_INHERIT:
853 case BFD_RELOC_VTABLE_ENTRY:
854 return 0;
855
856 default:
857 return 1;
858 }
859}
860
861#else /* !OBJ_ELF */
862
863#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
864
865#endif /* OBJ_ELF */
866
867#ifdef BFD_ASSEMBLER
868
869arelent *
870tc_gen_reloc (section, fixp)
871 asection *section;
872 fixS *fixp;
873{
874 arelent *reloc;
875 bfd_reloc_code_real_type code;
876
877 if (fixp->fx_tcbit)
878 abort ();
879
880 if (fixp->fx_r_type != BFD_RELOC_NONE)
881 {
882 code = fixp->fx_r_type;
883
884 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
885 that fixup_segment converted a non-PC relative reloc into a
886 PC relative reloc. In such a case, we need to convert the
887 reloc code. */
888 if (fixp->fx_pcrel)
889 {
890 switch (code)
891 {
892 case BFD_RELOC_8:
893 code = BFD_RELOC_8_PCREL;
894 break;
895 case BFD_RELOC_16:
896 code = BFD_RELOC_16_PCREL;
897 break;
898 case BFD_RELOC_32:
899 code = BFD_RELOC_32_PCREL;
900 break;
901 case BFD_RELOC_8_PCREL:
902 case BFD_RELOC_16_PCREL:
903 case BFD_RELOC_32_PCREL:
904 case BFD_RELOC_8_GOT_PCREL:
905 case BFD_RELOC_16_GOT_PCREL:
906 case BFD_RELOC_32_GOT_PCREL:
907 case BFD_RELOC_8_GOTOFF:
908 case BFD_RELOC_16_GOTOFF:
909 case BFD_RELOC_32_GOTOFF:
910 case BFD_RELOC_8_PLT_PCREL:
911 case BFD_RELOC_16_PLT_PCREL:
912 case BFD_RELOC_32_PLT_PCREL:
913 case BFD_RELOC_8_PLTOFF:
914 case BFD_RELOC_16_PLTOFF:
915 case BFD_RELOC_32_PLTOFF:
916 break;
917 default:
918 as_bad_where (fixp->fx_file, fixp->fx_line,
919 _("Cannot make %s relocation PC relative"),
920 bfd_get_reloc_code_name (code));
921 }
922 }
923 }
924 else
925 {
926#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
927 switch (F (fixp->fx_size, fixp->fx_pcrel))
928 {
929#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
930 MAP (1, 0, BFD_RELOC_8);
931 MAP (2, 0, BFD_RELOC_16);
932 MAP (4, 0, BFD_RELOC_32);
933 MAP (1, 1, BFD_RELOC_8_PCREL);
934 MAP (2, 1, BFD_RELOC_16_PCREL);
935 MAP (4, 1, BFD_RELOC_32_PCREL);
936 default:
937 abort ();
938 }
939 }
940#undef F
941#undef MAP
942
943 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 944 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
945 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 946 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
947#ifndef OBJ_ELF
948 if (fixp->fx_pcrel)
949 reloc->addend = fixp->fx_addnumber;
950 else
951 reloc->addend = 0;
952#else
953 if (!fixp->fx_pcrel)
954 reloc->addend = fixp->fx_addnumber;
955 else
956 reloc->addend = (section->vma
957 + (fixp->fx_pcrel_adjust == 64
958 ? -1 : fixp->fx_pcrel_adjust)
959 + fixp->fx_addnumber
960 + md_pcrel_from (fixp));
961#endif
962
963 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
964 assert (reloc->howto != 0);
965
966 return reloc;
967}
968
969#endif /* BFD_ASSEMBLER */
970
971/* Return zero if the reference to SYMBOL from within the same segment may
972 be relaxed. */
973#ifdef OBJ_ELF
974
975/* On an ELF system, we can't relax an externally visible symbol,
976 because it may be overridden by a shared library. However, if
977 TARGET_OS is "elf", then we presume that we are assembling for an
978 embedded system, in which case we don't have to worry about shared
979 libraries, and we can relax anything. */
980
981#define relaxable_symbol(symbol) \
982 (strcmp (TARGET_OS, "elf") == 0 \
983 || (! S_IS_EXTERNAL (symbol) \
984 && ! S_IS_WEAK (symbol)))
985
986#else
987
988#define relaxable_symbol(symbol) 1
989
990#endif
92774660 991
252b5132
RH		 992/* Handle of the OPCODE hash table. NULL means any use before
993 m68k_ip_begin() will crash. */
994static struct hash_control *op_hash;
995\f
996/* Assemble an m68k instruction. */
997
998static void
999m68k_ip (instring)
1000 char *instring;
1001{
1002 register char *p;
1003 register struct m68k_op *opP;
1004 register const struct m68k_incant *opcode;
1005 register const char *s;
1006 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1007 char *pdot, *pdotmove;
1008 enum m68k_size siz1, siz2;
1009 char c;
1010 int losing;
1011 int opsfound;
1012 LITTLENUM_TYPE words[6];
1013 LITTLENUM_TYPE *wordp;
1014 unsigned long ok_arch = 0;
1015
1016 if (*instring == ' ')
1017 instring++; /* skip leading whitespace */
1018
1019 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1020 or exactly 1 space. */
252b5132
RH		 1021 pdot = 0;
1022 for (p = instring; *p != '\0'; p++)
1023 {
1024 if (*p == ' ')
1025 break;
1026 if (*p == '.')
1027 pdot = p;
1028 }
1029
1030 if (p == instring)
1031 {
1032 the_ins.error = _("No operator");
1033 return;
1034 }
1035
1036 /* p now points to the end of the opcode name, probably whitespace.
1037 Make sure the name is null terminated by clobbering the
1038 whitespace, look it up in the hash table, then fix it back.
1039 Remove a dot, first, since the opcode tables have none. */
1040 if (pdot != NULL)
1041 {
1042 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1043 *pdotmove = pdotmove[1];
1044 p--;
1045 }
1046
1047 c = *p;
1048 *p = '\0';
1049 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1050 *p = c;
1051
1052 if (pdot != NULL)
1053 {
1054 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1055 *pdotmove = pdotmove[-1];
1056 *pdot = '.';
1057 ++p;
1058 }
1059
1060 if (opcode == NULL)
1061 {
1062 the_ins.error = _("Unknown operator");
1063 return;
1064 }
1065
1066 /* found a legitimate opcode, start matching operands */
1067 while (*p == ' ')
1068 ++p;
1069
1070 if (opcode->m_operands == 0)
1071 {
1072 char *old = input_line_pointer;
1073 *old = '\n';
1074 input_line_pointer = p;
1075 /* Ahh - it's a motorola style psuedo op */
1076 mote_pseudo_table[opcode->m_opnum].poc_handler
1077 (mote_pseudo_table[opcode->m_opnum].poc_val);
1078 input_line_pointer = old;
1079 *old = 0;
1080
1081 return;
1082 }
1083
1084 if (flag_mri && opcode->m_opnum == 0)
1085 {
1086 /* In MRI mode, random garbage is allowed after an instruction
1087 which accepts no operands. */
1088 the_ins.args = opcode->m_operands;
1089 the_ins.numargs = opcode->m_opnum;
1090 the_ins.numo = opcode->m_codenum;
1091 the_ins.opcode[0] = getone (opcode);
1092 the_ins.opcode[1] = gettwo (opcode);
1093 return;
1094 }
1095
1096 for (opP = &the_ins.operands[0]; *p; opP++)
1097 {
1098 p = crack_operand (p, opP);
1099
1100 if (opP->error)
1101 {
1102 the_ins.error = opP->error;
1103 return;
1104 }
1105 }
1106
1107 opsfound = opP - &the_ins.operands[0];
1108
1109 /* This ugly hack is to support the floating pt opcodes in their
1110 standard form. Essentially, we fake a first enty of type COP#1 */
1111 if (opcode->m_operands[0] == 'I')
1112 {
1113 int n;
1114
1115 for (n = opsfound; n > 0; --n)
1116 the_ins.operands[n] = the_ins.operands[n - 1];
1117
1118 memset ((char *) (&the_ins.operands[0]), '\0',
1119 sizeof (the_ins.operands[0]));
1120 the_ins.operands[0].mode = CONTROL;
1121 the_ins.operands[0].reg = m68k_float_copnum;
1122 opsfound++;
1123 }
1124
1125 /* We've got the operands. Find an opcode that'll accept them */
1126 for (losing = 0;;)
1127 {
1128 /* If we didn't get the right number of ops, or we have no
92774660 1129 common model with this pattern then reject this pattern. */
252b5132
RH		 1130
1131 ok_arch |= opcode->m_arch;
1132 if (opsfound != opcode->m_opnum
1133 || ((opcode->m_arch & current_architecture) == 0))
1134 ++losing;
1135 else
1136 {
1137 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1138 *s && !losing;
1139 s += 2, opP++)
1140 {
1141 /* Warning: this switch is huge! */
1142 /* I've tried to organize the cases into this order:
1143 non-alpha first, then alpha by letter. Lower-case
1144 goes directly before uppercase counterpart. */
1145 /* Code with multiple case ...: gets sorted by the lowest
1146 case ... it belongs to. I hope this makes sense. */
1147 switch (*s)
1148 {
1149 case '!':
1150 switch (opP->mode)
1151 {
1152 case IMMED:
1153 case DREG:
1154 case AREG:
1155 case FPREG:
1156 case CONTROL:
1157 case AINC:
1158 case ADEC:
1159 case REGLST:
1160 losing++;
1161 break;
1162 default:
1163 break;
1164 }
1165 break;
1166
1167 case '<':
1168 switch (opP->mode)
1169 {
1170 case DREG:
1171 case AREG:
1172 case FPREG:
1173 case CONTROL:
1174 case IMMED:
1175 case ADEC:
1176 case REGLST:
1177 losing++;
1178 break;
1179 default:
1180 break;
1181 }
1182 break;
1183
1184 case '>':
1185 switch (opP->mode)
1186 {
1187 case DREG:
1188 case AREG:
1189 case FPREG:
1190 case CONTROL:
1191 case IMMED:
1192 case AINC:
1193 case REGLST:
1194 losing++;
1195 break;
1196 case ABSL:
1197 break;
1198 default:
1199 if (opP->reg == PC
1200 || opP->reg == ZPC)
1201 losing++;
1202 break;
1203 }
1204 break;
1205
1206 case 'm':
1207 switch (opP->mode)
1208 {
1209 case DREG:
1210 case AREG:
1211 case AINDR:
1212 case AINC:
1213 case ADEC:
1214 break;
1215 default:
1216 losing++;
1217 }
1218 break;
1219
1220 case 'n':
1221 switch (opP->mode)
1222 {
1223 case DISP:
1224 break;
1225 default:
1226 losing++;
1227 }
1228 break;
1229
1230 case 'o':
1231 switch (opP->mode)
1232 {
1233 case BASE:
1234 case ABSL:
1235 case IMMED:
1236 break;
1237 default:
1238 losing++;
1239 }
1240 break;
1241
1242 case 'p':
1243 switch (opP->mode)
1244 {
1245 case DREG:
1246 case AREG:
1247 case AINDR:
1248 case AINC:
1249 case ADEC:
1250 break;
1251 case DISP:
1252 if (opP->reg == PC || opP->reg == ZPC)
1253 losing++;
1254 break;
1255 default:
1256 losing++;
1257 }
1258 break;
1259
1260 case 'q':
1261 switch (opP->mode)
1262 {
1263 case DREG:
1264 case AINDR:
1265 case AINC:
1266 case ADEC:
1267 break;
1268 case DISP:
1269 if (opP->reg == PC || opP->reg == ZPC)
1270 losing++;
1271 break;
1272 default:
1273 losing++;
1274 break;
1275 }
1276 break;
1277
1278 case 'v':
1279 switch (opP->mode)
1280 {
1281 case DREG:
1282 case AINDR:
1283 case AINC:
1284 case ADEC:
1285 case ABSL:
1286 break;
1287 case DISP:
1288 if (opP->reg == PC || opP->reg == ZPC)
1289 losing++;
1290 break;
1291 default:
1292 losing++;
1293 break;
1294 }
1295 break;
1296
1297 case '#':
1298 if (opP->mode != IMMED)
1299 losing++;
1300 else if (s[1] == 'b'
1301 && ! isvar (&opP->disp)
1302 && (opP->disp.exp.X_op != O_constant
1303 || ! isbyte (opP->disp.exp.X_add_number)))
1304 losing++;
1305 else if (s[1] == 'B'
1306 && ! isvar (&opP->disp)
1307 && (opP->disp.exp.X_op != O_constant
1308 || ! issbyte (opP->disp.exp.X_add_number)))
1309 losing++;
1310 else if (s[1] == 'w'
1311 && ! isvar (&opP->disp)
1312 && (opP->disp.exp.X_op != O_constant
1313 || ! isword (opP->disp.exp.X_add_number)))
1314 losing++;
1315 else if (s[1] == 'W'
1316 && ! isvar (&opP->disp)
1317 && (opP->disp.exp.X_op != O_constant
1318 || ! issword (opP->disp.exp.X_add_number)))
1319 losing++;
1320 break;
1321
1322 case '^':
1323 case 'T':
1324 if (opP->mode != IMMED)
1325 losing++;
1326 break;
1327
1328 case '$':
1329 if (opP->mode == AREG
1330 || opP->mode == CONTROL
1331 || opP->mode == FPREG
1332 || opP->mode == IMMED
1333 || opP->mode == REGLST
1334 || (opP->mode != ABSL
1335 && (opP->reg == PC
1336 || opP->reg == ZPC)))
1337 losing++;
1338 break;
1339
1340 case '%':
1341 if (opP->mode == CONTROL
1342 || opP->mode == FPREG
1343 || opP->mode == REGLST
1344 || opP->mode == IMMED
1345 || (opP->mode != ABSL
1346 && (opP->reg == PC
1347 || opP->reg == ZPC)))
1348 losing++;
1349 break;
1350
1351 case '&':
1352 switch (opP->mode)
1353 {
1354 case DREG:
1355 case AREG:
1356 case FPREG:
1357 case CONTROL:
1358 case IMMED:
1359 case AINC:
1360 case ADEC:
1361 case REGLST:
1362 losing++;
1363 break;
1364 case ABSL:
1365 break;
1366 default:
1367 if (opP->reg == PC
1368 || opP->reg == ZPC)
1369 losing++;
1370 break;
1371 }
1372 break;
1373
1374 case '*':
1375 if (opP->mode == CONTROL
1376 || opP->mode == FPREG
1377 || opP->mode == REGLST)
1378 losing++;
1379 break;
1380
1381 case '+':
1382 if (opP->mode != AINC)
1383 losing++;
1384 break;
1385
1386 case '-':
1387 if (opP->mode != ADEC)
1388 losing++;
1389 break;
1390
1391 case '/':
1392 switch (opP->mode)
1393 {
1394 case AREG:
1395 case CONTROL:
1396 case FPREG:
1397 case AINC:
1398 case ADEC:
1399 case IMMED:
1400 case REGLST:
1401 losing++;
1402 break;
1403 default:
1404 break;
1405 }
1406 break;
1407
1408 case ';':
1409 switch (opP->mode)
1410 {
1411 case AREG:
1412 case CONTROL:
1413 case FPREG:
1414 case REGLST:
1415 losing++;
1416 break;
1417 default:
1418 break;
1419 }
1420 break;
1421
1422 case '?':
1423 switch (opP->mode)
1424 {
1425 case AREG:
1426 case CONTROL:
1427 case FPREG:
1428 case AINC:
1429 case ADEC:
1430 case IMMED:
1431 case REGLST:
1432 losing++;
1433 break;
1434 case ABSL:
1435 break;
1436 default:
1437 if (opP->reg == PC || opP->reg == ZPC)
1438 losing++;
1439 break;
1440 }
1441 break;
1442
1443 case '@':
1444 switch (opP->mode)
1445 {
1446 case AREG:
1447 case CONTROL:
1448 case FPREG:
1449 case IMMED:
1450 case REGLST:
1451 losing++;
1452 break;
1453 default:
1454 break;
1455 }
1456 break;
1457
1458 case '~': /* For now! (JF FOO is this right?) */
1459 switch (opP->mode)
1460 {
1461 case DREG:
1462 case AREG:
1463 case CONTROL:
1464 case FPREG:
1465 case IMMED:
1466 case REGLST:
1467 losing++;
1468 break;
1469 case ABSL:
1470 break;
1471 default:
1472 if (opP->reg == PC
1473 || opP->reg == ZPC)
1474 losing++;
1475 break;
1476 }
1477 break;
1478
1479 case '3':
1480 if (opP->mode != CONTROL
1481 || (opP->reg != TT0 && opP->reg != TT1))
1482 losing++;
1483 break;
1484
1485 case 'A':
1486 if (opP->mode != AREG)
1487 losing++;
1488 break;
1489
1490 case 'a':
1491 if (opP->mode != AINDR)
1492 ++losing;
1493 break;
1494
1495 case 'B': /* FOO */
1496 if (opP->mode != ABSL
1497 || (flag_long_jumps
1498 && strncmp (instring, "jbsr", 4) == 0))
1499 losing++;
1500 break;
1501
1502 case 'C':
1503 if (opP->mode != CONTROL || opP->reg != CCR)
1504 losing++;
1505 break;
1506
1507 case 'd':
1508 if (opP->mode != DISP
1509 || opP->reg < ADDR0
1510 || opP->reg > ADDR7)
1511 losing++;
1512 break;
1513
1514 case 'D':
1515 if (opP->mode != DREG)
1516 losing++;
1517 break;
1518
6da466c7
ILT		 1519 case 'E':
1520 if (opP->reg != ACC)
1521 losing++;
1522 break;
1523
252b5132
RH		 1524 case 'F':
1525 if (opP->mode != FPREG)
1526 losing++;
1527 break;
1528
6da466c7
ILT		 1529 case 'G':
1530 if (opP->reg != MACSR)
1531 losing++;
1532 break;
1533
1534 case 'H':
1535 if (opP->reg != MASK)
1536 losing++;
1537 break;
1538
252b5132
RH		 1539 case 'I':
1540 if (opP->mode != CONTROL
1541 || opP->reg < COP0
1542 || opP->reg > COP7)
1543 losing++;
1544 break;
1545
1546 case 'J':
1547 if (opP->mode != CONTROL
1548 || opP->reg < USP
1549 || opP->reg > last_movec_reg)
1550 losing++;
1551 else
1552 {
1553 const enum m68k_register *rp;
1554 for (rp = control_regs; *rp; rp++)
1555 if (*rp == opP->reg)
1556 break;
1557 if (*rp == 0)
1558 losing++;
1559 }
1560 break;
1561
1562 case 'k':
1563 if (opP->mode != IMMED)
1564 losing++;
1565 break;
1566
1567 case 'l':
1568 case 'L':
1569 if (opP->mode == DREG
1570 || opP->mode == AREG
1571 || opP->mode == FPREG)
1572 {
1573 if (s[1] == '8')
1574 losing++;
1575 else
1576 {
1577 switch (opP->mode)
1578 {
1579 case DREG:
1580 opP->mask = 1 << (opP->reg - DATA0);
1581 break;
1582 case AREG:
1583 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1584 break;
1585 case FPREG:
1586 opP->mask = 1 << (opP->reg - FP0 + 16);
1587 break;
1588 default:
1589 abort ();
1590 }
1591 opP->mode = REGLST;
1592 }
1593 }
1594 else if (opP->mode == CONTROL)
1595 {
1596 if (s[1] != '8')
1597 losing++;
1598 else
1599 {
1600 switch (opP->reg)
1601 {
1602 case FPI:
1603 opP->mask = 1 << 24;
1604 break;
1605 case FPS:
1606 opP->mask = 1 << 25;
1607 break;
1608 case FPC:
1609 opP->mask = 1 << 26;
1610 break;
1611 default:
1612 losing++;
1613 break;
1614 }
1615 opP->mode = REGLST;
1616 }
1617 }
1618 else if (opP->mode != REGLST)
1619 losing++;
1620 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1621 losing++;
1622 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1623 losing++;
1624 break;
1625
1626 case 'M':
1627 if (opP->mode != IMMED)
1628 losing++;
1629 else if (opP->disp.exp.X_op != O_constant
1630 || ! issbyte (opP->disp.exp.X_add_number))
1631 losing++;
1632 else if (! m68k_quick
1633 && instring[3] != 'q'
1634 && instring[4] != 'q')
1635 losing++;
1636 break;
1637
1638 case 'O':
1639 if (opP->mode != DREG
1640 && opP->mode != IMMED
1641 && opP->mode != ABSL)
1642 losing++;
1643 break;
1644
1645 case 'Q':
1646 if (opP->mode != IMMED)
1647 losing++;
1648 else if (opP->disp.exp.X_op != O_constant
1649 || opP->disp.exp.X_add_number < 1
1650 || opP->disp.exp.X_add_number > 8)
1651 losing++;
1652 else if (! m68k_quick
1653 && (strncmp (instring, "add", 3) == 0
1654 || strncmp (instring, "sub", 3) == 0)
1655 && instring[3] != 'q')
1656 losing++;
1657 break;
1658
1659 case 'R':
1660 if (opP->mode != DREG && opP->mode != AREG)
1661 losing++;
1662 break;
1663
1664 case 'r':
1665 if (opP->mode != AINDR
1666 && (opP->mode != BASE
1667 || (opP->reg != 0
1668 && opP->reg != ZADDR0)
1669 || opP->disp.exp.X_op != O_absent
1670 || ((opP->index.reg < DATA0
1671 || opP->index.reg > DATA7)
1672 && (opP->index.reg < ADDR0
1673 || opP->index.reg > ADDR7))
1674 || opP->index.size != SIZE_UNSPEC
1675 || opP->index.scale != 1))
1676 losing++;
1677 break;
1678
1679 case 's':
1680 if (opP->mode != CONTROL
1681 || ! (opP->reg == FPI
1682 || opP->reg == FPS
1683 || opP->reg == FPC))
1684 losing++;
1685 break;
1686
1687 case 'S':
1688 if (opP->mode != CONTROL || opP->reg != SR)
1689 losing++;
1690 break;
1691
1692 case 't':
1693 if (opP->mode != IMMED)
1694 losing++;
1695 else if (opP->disp.exp.X_op != O_constant
1696 || opP->disp.exp.X_add_number < 0
1697 || opP->disp.exp.X_add_number > 7)
1698 losing++;
1699 break;
1700
1701 case 'U':
1702 if (opP->mode != CONTROL || opP->reg != USP)
1703 losing++;
1704 break;
1705
1706 /* JF these are out of order. We could put them
1707 in order if we were willing to put up with
1708 bunches of #ifdef m68851s in the code.
1709
1710 Don't forget that you need these operands
1711 to use 68030 MMU instructions. */
1712#ifndef NO_68851
1713 /* Memory addressing mode used by pflushr */
1714 case '|':
1715 if (opP->mode == CONTROL
1716 || opP->mode == FPREG
1717 || opP->mode == DREG
1718 || opP->mode == AREG
1719 || opP->mode == REGLST)
1720 losing++;
1721 /* We should accept immediate operands, but they
1722 supposedly have to be quad word, and we don't
1723 handle that. I would like to see what a Motorola
1724 assembler does before doing something here. */
1725 if (opP->mode == IMMED)
1726 losing++;
1727 break;
1728
1729 case 'f':
1730 if (opP->mode != CONTROL
1731 || (opP->reg != SFC && opP->reg != DFC))
1732 losing++;
1733 break;
1734
1735 case '0':
1736 if (opP->mode != CONTROL || opP->reg != TC)
1737 losing++;
1738 break;
1739
1740 case '1':
1741 if (opP->mode != CONTROL || opP->reg != AC)
1742 losing++;
1743 break;
1744
1745 case '2':
1746 if (opP->mode != CONTROL
1747 || (opP->reg != CAL
1748 && opP->reg != VAL
1749 && opP->reg != SCC))
1750 losing++;
1751 break;
1752
1753 case 'V':
1754 if (opP->mode != CONTROL
1755 || opP->reg != VAL)
1756 losing++;
1757 break;
1758
1759 case 'W':
1760 if (opP->mode != CONTROL
1761 || (opP->reg != DRP
1762 && opP->reg != SRP
1763 && opP->reg != CRP))
1764 losing++;
1765 break;
1766
1767 case 'X':
1768 if (opP->mode != CONTROL
1769 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1770 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1771 losing++;
1772 break;
1773
1774 case 'Y':
1775 if (opP->mode != CONTROL || opP->reg != PSR)
1776 losing++;
1777 break;
1778
1779 case 'Z':
1780 if (opP->mode != CONTROL || opP->reg != PCSR)
1781 losing++;
1782 break;
1783#endif
1784 case 'c':
1785 if (opP->mode != CONTROL
1786 || (opP->reg != NC
1787 && opP->reg != IC
1788 && opP->reg != DC
1789 && opP->reg != BC))
1790 {
1791 losing++;
92774660 1792 } /* not a cache specifier. */
252b5132
RH		 1793 break;
1794
1795 case '_':
1796 if (opP->mode != ABSL)
1797 ++losing;
1798 break;
1799
6da466c7
ILT		 1800 case 'u':
1801 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1802 losing++;
1803 /* FIXME: kludge instead of fixing parser:
1804 upper/lower registers are *not* CONTROL
92774660 1805 registers, but ordinary ones. */
6da466c7
ILT		 1806 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1807 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1808 opP->mode = DREG;
1809 else
1810 opP->mode = AREG;
1811 break;
1812
252b5132
RH		 1813 default:
1814 abort ();
1815 } /* switch on type of operand */
1816
1817 if (losing)
1818 break;
1819 } /* for each operand */
1820 } /* if immediately wrong */
1821
1822 if (!losing)
1823 {
1824 break;
92774660 1825 } /* got it. */
252b5132
RH		 1826
1827 opcode = opcode->m_next;
1828
1829 if (!opcode)
1830 {
1831 if (ok_arch
1832 && !(ok_arch & current_architecture))
1833 {
1834 char buf[200], *cp;
1835
1836 strcpy (buf,
1837 _("invalid instruction for this architecture; needs "));
1838 cp = buf + strlen (buf);
1839 switch (ok_arch)
1840 {
1841 case mfloat:
1842 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1843 break;
1844 case mmmu:
1845 strcpy (cp, _("mmu (68030 or 68851)"));
1846 break;
1847 case m68020up:
1848 strcpy (cp, _("68020 or higher"));
1849 break;
1850 case m68000up:
1851 strcpy (cp, _("68000 or higher"));
1852 break;
1853 case m68010up:
1854 strcpy (cp, _("68010 or higher"));
1855 break;
1856 default:
1857 {
1858 int got_one = 0, idx;
8fce3f5e
AM		 1859 for (idx = 0;
1860 idx < (int) (sizeof (archs) / sizeof (archs[0]));
252b5132
RH		 1861 idx++)
1862 {
1863 if ((archs[idx].arch & ok_arch)
1864 && ! archs[idx].alias)
1865 {
1866 if (got_one)
1867 {
1868 strcpy (cp, " or ");
1869 cp += strlen (cp);
1870 }
1871 got_one = 1;
1872 strcpy (cp, archs[idx].name);
1873 cp += strlen (cp);
1874 }
1875 }
1876 }
1877 }
1878 cp = xmalloc (strlen (buf) + 1);
1879 strcpy (cp, buf);
1880 the_ins.error = cp;
1881 }
1882 else
1883 the_ins.error = _("operands mismatch");
1884 return;
1885 } /* Fell off the end */
1886
1887 losing = 0;
1888 }
1889
1890 /* now assemble it */
1891
1892 the_ins.args = opcode->m_operands;
1893 the_ins.numargs = opcode->m_opnum;
1894 the_ins.numo = opcode->m_codenum;
1895 the_ins.opcode[0] = getone (opcode);
1896 the_ins.opcode[1] = gettwo (opcode);
1897
1898 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1899 {
1900 /* This switch is a doozy.
1901 Watch the first step; its a big one! */
1902 switch (s[0])
1903 {
1904
1905 case '*':
1906 case '~':
1907 case '%':
1908 case ';':
1909 case '@':
1910 case '!':
1911 case '&':
1912 case '$':
1913 case '?':
1914 case '/':
1915 case '<':
1916 case '>':
1917 case 'm':
1918 case 'n':
1919 case 'o':
1920 case 'p':
1921 case 'q':
1922 case 'v':
1923#ifndef NO_68851
1924 case '|':
1925#endif
1926 switch (opP->mode)
1927 {
1928 case IMMED:
1929 tmpreg = 0x3c; /* 7.4 */
1930 if (strchr ("bwl", s[1]))
1931 nextword = get_num (&opP->disp, 80);
1932 else
1933 nextword = get_num (&opP->disp, 0);
1934 if (isvar (&opP->disp))
1935 add_fix (s[1], &opP->disp, 0, 0);
1936 switch (s[1])
1937 {
1938 case 'b':
1939 if (!isbyte (nextword))
1940 opP->error = _("operand out of range");
1941 addword (nextword);
1942 baseo = 0;
1943 break;
1944 case 'w':
1945 if (!isword (nextword))
1946 opP->error = _("operand out of range");
1947 addword (nextword);
1948 baseo = 0;
1949 break;
1950 case 'W':
1951 if (!issword (nextword))
1952 opP->error = _("operand out of range");
1953 addword (nextword);
1954 baseo = 0;
1955 break;
1956 case 'l':
1957 addword (nextword >> 16);
1958 addword (nextword);
1959 baseo = 0;
1960 break;
1961
1962 case 'f':
1963 baseo = 2;
1964 outro = 8;
1965 break;
1966 case 'F':
1967 baseo = 4;
1968 outro = 11;
1969 break;
1970 case 'x':
1971 baseo = 6;
1972 outro = 15;
1973 break;
1974 case 'p':
1975 baseo = 6;
1976 outro = -1;
1977 break;
1978 default:
1979 abort ();
1980 }
1981 if (!baseo)
1982 break;
1983
1984 /* We gotta put out some float */
1985 if (op (&opP->disp) != O_big)
1986 {
1987 valueT val;
1988 int gencnt;
1989
1990 /* Can other cases happen here? */
1991 if (op (&opP->disp) != O_constant)
1992 abort ();
1993
1994 val = (valueT) offs (&opP->disp);
1995 gencnt = 0;
1996 do
1997 {
1998 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1999 val >>= LITTLENUM_NUMBER_OF_BITS;
2000 ++gencnt;
2001 }
2002 while (val != 0);
2003 offs (&opP->disp) = gencnt;
2004 }
2005 if (offs (&opP->disp) > 0)
2006 {
2007 if (offs (&opP->disp) > baseo)
2008 {
2009 as_warn (_("Bignum too big for %c format; truncated"),
2010 s[1]);
2011 offs (&opP->disp) = baseo;
2012 }
2013 baseo -= offs (&opP->disp);
2014 while (baseo--)
2015 addword (0);
2016 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2017 offs (&opP->disp)--;
2018 --wordp)
2019 addword (*wordp);
2020 break;
2021 }
2022 gen_to_words (words, baseo, (long) outro);
2023 for (wordp = words; baseo--; wordp++)
2024 addword (*wordp);
2025 break;
2026 case DREG:
2027 tmpreg = opP->reg - DATA; /* 0.dreg */
2028 break;
2029 case AREG:
2030 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2031 break;
2032 case AINDR:
2033 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2034 break;
2035 case ADEC:
2036 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2037 break;
2038 case AINC:
2039 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2040 break;
2041 case DISP:
2042
2043 nextword = get_num (&opP->disp, 80);
2044
2045 if (opP->reg == PC
2046 && ! isvar (&opP->disp)
2047 && m68k_abspcadd)
2048 {
2049 opP->disp.exp.X_op = O_symbol;
2050#ifndef BFD_ASSEMBLER
2051 opP->disp.exp.X_add_symbol = &abs_symbol;
2052#else
2053 opP->disp.exp.X_add_symbol =
2054 section_symbol (absolute_section);
2055#endif
2056 }
2057
2058 /* Force into index mode. Hope this works */
2059
2060 /* We do the first bit for 32-bit displacements, and the
2061 second bit for 16 bit ones. It is possible that we
2062 should make the default be WORD instead of LONG, but
2063 I think that'd break GCC, so we put up with a little
2064 inefficiency for the sake of working output. */
2065
2066 if (!issword (nextword)
2067 || (isvar (&opP->disp)
2068 && ((opP->disp.size == SIZE_UNSPEC
2069 && flag_short_refs == 0
2070 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2071 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2072 || opP->disp.size == SIZE_LONG)))
2073 {
2074 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2075 || arch_coldfire_p (current_architecture))
252b5132
RH		 2076 opP->error =
2077 _("displacement too large for this architecture; needs 68020 or higher");
2078 if (opP->reg == PC)
2079 tmpreg = 0x3B; /* 7.3 */
2080 else
2081 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2082 if (isvar (&opP->disp))
2083 {
2084 if (opP->reg == PC)
2085 {
2086 if (opP->disp.size == SIZE_LONG
2087#ifdef OBJ_ELF
2088 /* If the displacement needs pic
2089 relocation it cannot be relaxed. */
2090 || opP->disp.pic_reloc != pic_none
2091#endif
2092 )
2093 {
2094 addword (0x0170);
2095 add_fix ('l', &opP->disp, 1, 2);
2096 }
2097 else
2098 {
2099 add_frag (adds (&opP->disp),
2100 offs (&opP->disp),
151337e8 2101 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2102 break;
2103 }
2104 }
2105 else
2106 {
2107 addword (0x0170);
2108 add_fix ('l', &opP->disp, 0, 0);
2109 }
2110 }
2111 else
2112 addword (0x0170);
2113 addword (nextword >> 16);
2114 }
2115 else
2116 {
2117 if (opP->reg == PC)
2118 tmpreg = 0x3A; /* 7.2 */
2119 else
2120 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2121
2122 if (isvar (&opP->disp))
2123 {
2124 if (opP->reg == PC)
2125 {
2126 add_fix ('w', &opP->disp, 1, 0);
2127 }
2128 else
2129 add_fix ('w', &opP->disp, 0, 0);
2130 }
2131 }
2132 addword (nextword);
2133 break;
2134
2135 case POST:
2136 case PRE:
2137 case BASE:
2138 nextword = 0;
2139 baseo = get_num (&opP->disp, 80);
2140 if (opP->mode == POST || opP->mode == PRE)
2141 outro = get_num (&opP->odisp, 80);
2142 /* Figure out the `addressing mode'.
2143 Also turn on the BASE_DISABLE bit, if needed. */
2144 if (opP->reg == PC || opP->reg == ZPC)
2145 {
2146 tmpreg = 0x3b; /* 7.3 */
2147 if (opP->reg == ZPC)
2148 nextword |= 0x80;
2149 }
2150 else if (opP->reg == 0)
2151 {
2152 nextword |= 0x80;
2153 tmpreg = 0x30; /* 6.garbage */
2154 }
2155 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2156 {
2157 nextword |= 0x80;
2158 tmpreg = 0x30 + opP->reg - ZADDR0;
2159 }
2160 else
2161 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2162
2163 siz1 = opP->disp.size;
2164 if (opP->mode == POST || opP->mode == PRE)
2165 siz2 = opP->odisp.size;
2166 else
2167 siz2 = SIZE_UNSPEC;
2168
2169 /* Index register stuff */
2170 if (opP->index.reg != 0
2171 && opP->index.reg >= DATA
2172 && opP->index.reg <= ADDR7)
2173 {
2174 nextword |= (opP->index.reg - DATA) << 12;
2175
2176 if (opP->index.size == SIZE_LONG
2177 || (opP->index.size == SIZE_UNSPEC
2178 && m68k_index_width_default == SIZE_LONG))
2179 nextword |= 0x800;
2180
92774660 2181 if ((opP->index.scale != 1
252b5132 2182 && cpu_of_arch (current_architecture) < m68020)
92774660 2183 || (opP->index.scale == 8
6da466c7 2184 && arch_coldfire_p (current_architecture)))
252b5132
RH		 2185 {
2186 opP->error =
2187 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2188 }
2189
6da466c7
ILT		 2190 if (arch_coldfire_p (current_architecture)
2191 && opP->index.size == SIZE_WORD)
2192 opP->error = _("invalid index size for coldfire");
2193
252b5132
RH		 2194 switch (opP->index.scale)
2195 {
2196 case 1:
2197 break;
2198 case 2:
2199 nextword |= 0x200;
2200 break;
2201 case 4:
2202 nextword |= 0x400;
2203 break;
2204 case 8:
2205 nextword |= 0x600;
2206 break;
2207 default:
2208 abort ();
2209 }
2210 /* IF its simple,
2211 GET US OUT OF HERE! */
2212
2213 /* Must be INDEX, with an index register. Address
2214 register cannot be ZERO-PC, and either :b was
2215 forced, or we know it will fit. For a 68000 or
2216 68010, force this mode anyways, because the
2217 larger modes aren't supported. */
2218 if (opP->mode == BASE
2219 && ((opP->reg >= ADDR0
2220 && opP->reg <= ADDR7)
2221 || opP->reg == PC))
2222 {
2223 if (siz1 == SIZE_BYTE
2224 || cpu_of_arch (current_architecture) < m68020
6da466c7 2225 || arch_coldfire_p (current_architecture)
252b5132
RH		 2226 || (siz1 == SIZE_UNSPEC
2227 && ! isvar (&opP->disp)
2228 && issbyte (baseo)))
2229 {
2230 nextword += baseo & 0xff;
2231 addword (nextword);
2232 if (isvar (&opP->disp))
2233 {
2234 /* Do a byte relocation. If it doesn't
2235 fit (possible on m68000) let the
2236 fixup processing complain later. */
2237 if (opP->reg == PC)
2238 add_fix ('B', &opP->disp, 1, 1);
2239 else
2240 add_fix ('B', &opP->disp, 0, 0);
2241 }
2242 else if (siz1 != SIZE_BYTE)
2243 {
2244 if (siz1 != SIZE_UNSPEC)
2245 as_warn (_("Forcing byte displacement"));
2246 if (! issbyte (baseo))
2247 opP->error = _("byte displacement out of range");
2248 }
2249
2250 break;
2251 }
2252 else if (siz1 == SIZE_UNSPEC
2253 && opP->reg == PC
2254 && isvar (&opP->disp)
2255 && subs (&opP->disp) == NULL
2256#ifdef OBJ_ELF
2257 /* If the displacement needs pic
2258 relocation it cannot be relaxed. */
2259 && opP->disp.pic_reloc == pic_none
2260#endif
2261 )
2262 {
2263 /* The code in md_convert_frag_1 needs to be
2264 able to adjust nextword. Call frag_grow
2265 to ensure that we have enough space in
2266 the frag obstack to make all the bytes
2267 contiguous. */
2268 frag_grow (14);
2269 nextword += baseo & 0xff;
2270 addword (nextword);
2271 add_frag (adds (&opP->disp), offs (&opP->disp),
2272 TAB (PCINDEX, SZ_UNDEF));
2273
2274 break;
2275 }
2276 }
2277 }
2278 else
2279 {
2280 nextword |= 0x40; /* No index reg */
2281 if (opP->index.reg >= ZDATA0
2282 && opP->index.reg <= ZDATA7)
2283 nextword |= (opP->index.reg - ZDATA0) << 12;
2284 else if (opP->index.reg >= ZADDR0
2285 || opP->index.reg <= ZADDR7)
2286 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2287 }
2288
2289 /* It isn't simple. */
2290
2291 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2292 || arch_coldfire_p (current_architecture))
252b5132
RH		 2293 opP->error =
2294 _("invalid operand mode for this architecture; needs 68020 or higher");
2295
2296 nextword |= 0x100;
2297 /* If the guy specified a width, we assume that it is
2298 wide enough. Maybe it isn't. If so, we lose. */
2299 switch (siz1)
2300 {
2301 case SIZE_UNSPEC:
2302 if (isvar (&opP->disp)
2303 ? m68k_rel32
2304 : ! issword (baseo))
2305 {
2306 siz1 = SIZE_LONG;
2307 nextword |= 0x30;
2308 }
2309 else if (! isvar (&opP->disp) && baseo == 0)
2310 nextword |= 0x10;
2311 else
2312 {
2313 nextword |= 0x20;
2314 siz1 = SIZE_WORD;
2315 }
2316 break;
2317 case SIZE_BYTE:
2318 as_warn (_(":b not permitted; defaulting to :w"));
2319 /* Fall through. */
2320 case SIZE_WORD:
2321 nextword |= 0x20;
2322 break;
2323 case SIZE_LONG:
2324 nextword |= 0x30;
2325 break;
2326 }
2327
2328 /* Figure out innner displacement stuff */
2329 if (opP->mode == POST || opP->mode == PRE)
2330 {
2331 if (cpu_of_arch (current_architecture) & cpu32)
2332 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2333 switch (siz2)
2334 {
2335 case SIZE_UNSPEC:
2336 if (isvar (&opP->odisp)
2337 ? m68k_rel32
2338 : ! issword (outro))
2339 {
2340 siz2 = SIZE_LONG;
2341 nextword |= 0x3;
2342 }
2343 else if (! isvar (&opP->odisp) && outro == 0)
2344 nextword |= 0x1;
2345 else
2346 {
2347 nextword |= 0x2;
2348 siz2 = SIZE_WORD;
2349 }
2350 break;
2351 case 1:
2352 as_warn (_(":b not permitted; defaulting to :w"));
2353 /* Fall through. */
2354 case 2:
2355 nextword |= 0x2;
2356 break;
2357 case 3:
2358 nextword |= 0x3;
2359 break;
2360 }
2361 if (opP->mode == POST
2362 && (nextword & 0x40) == 0)
2363 nextword |= 0x04;
2364 }
2365 addword (nextword);
2366
2367 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2368 {
2369 if (opP->reg == PC || opP->reg == ZPC)
2370 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2371 else
2372 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2373 }
2374 if (siz1 == SIZE_LONG)
2375 addword (baseo >> 16);
2376 if (siz1 != SIZE_UNSPEC)
2377 addword (baseo);
2378
2379 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2380 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2381 if (siz2 == SIZE_LONG)
2382 addword (outro >> 16);
2383 if (siz2 != SIZE_UNSPEC)
2384 addword (outro);
2385
2386 break;
2387
2388 case ABSL:
2389 nextword = get_num (&opP->disp, 80);
2390 switch (opP->disp.size)
2391 {
2392 default:
2393 abort ();
2394 case SIZE_UNSPEC:
2395 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2396 {
2397 tmpreg = 0x38; /* 7.0 */
2398 addword (nextword);
2399 break;
2400 }
252b5132
RH		 2401 if (isvar (&opP->disp)
2402 && !subs (&opP->disp)
2403 && adds (&opP->disp)
2404#ifdef OBJ_ELF
2405 /* If the displacement needs pic relocation it
2406 cannot be relaxed. */
2407 && opP->disp.pic_reloc == pic_none
2408#endif
252b5132
RH		 2409 && !flag_long_jumps
2410 && !strchr ("~%&$?", s[0]))
2411 {
2412 tmpreg = 0x3A; /* 7.2 */
2413 add_frag (adds (&opP->disp),
2414 offs (&opP->disp),
151337e8 2415 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2416 break;
2417 }
2418 /* Fall through into long */
2419 case SIZE_LONG:
2420 if (isvar (&opP->disp))
2421 add_fix ('l', &opP->disp, 0, 0);
2422
2423 tmpreg = 0x39;/* 7.1 mode */
2424 addword (nextword >> 16);
2425 addword (nextword);
2426 break;
2427
2428 case SIZE_BYTE:
2429 as_bad (_("unsupported byte value; use a different suffix"));
2430 /* Fall through. */
2431 case SIZE_WORD: /* Word */
2432 if (isvar (&opP->disp))
2433 add_fix ('w', &opP->disp, 0, 0);
2434
2435 tmpreg = 0x38;/* 7.0 mode */
2436 addword (nextword);
2437 break;
2438 }
2439 break;
2440 case CONTROL:
2441 case FPREG:
2442 default:
2443 as_bad (_("unknown/incorrect operand"));
2444 /* abort(); */
2445 }
2446 install_gen_operand (s[1], tmpreg);
2447 break;
2448
2449 case '#':
2450 case '^':
2451 switch (s[1])
2452 { /* JF: I hate floating point! */
2453 case 'j':
2454 tmpreg = 70;
2455 break;
2456 case '8':
2457 tmpreg = 20;
2458 break;
2459 case 'C':
2460 tmpreg = 50;
2461 break;
2462 case '3':
2463 default:
2464 tmpreg = 80;
2465 break;
2466 }
2467 tmpreg = get_num (&opP->disp, tmpreg);
2468 if (isvar (&opP->disp))
2469 add_fix (s[1], &opP->disp, 0, 0);
2470 switch (s[1])
2471 {
2472 case 'b': /* Danger: These do no check for
2473 certain types of overflow.
2474 user beware! */
2475 if (!isbyte (tmpreg))
2476 opP->error = _("out of range");
2477 insop (tmpreg, opcode);
2478 if (isvar (&opP->disp))
2479 the_ins.reloc[the_ins.nrel - 1].n =
2480 (opcode->m_codenum) * 2 + 1;
2481 break;
2482 case 'B':
2483 if (!issbyte (tmpreg))
2484 opP->error = _("out of range");
2485 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2486 if (isvar (&opP->disp))
2487 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2488 break;
2489 case 'w':
2490 if (!isword (tmpreg))
2491 opP->error = _("out of range");
2492 insop (tmpreg, opcode);
2493 if (isvar (&opP->disp))
2494 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2495 break;
2496 case 'W':
2497 if (!issword (tmpreg))
2498 opP->error = _("out of range");
2499 insop (tmpreg, opcode);
2500 if (isvar (&opP->disp))
2501 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2502 break;
2503 case 'l':
2504 /* Because of the way insop works, we put these two out
2505 backwards. */
2506 insop (tmpreg, opcode);
2507 insop (tmpreg >> 16, opcode);
2508 if (isvar (&opP->disp))
2509 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2510 break;
2511 case '3':
2512 tmpreg &= 0xFF;
2513 case '8':
2514 case 'C':
2515 case 'j':
2516 install_operand (s[1], tmpreg);
2517 break;
2518 default:
2519 abort ();
2520 }
2521 break;
2522
2523 case '+':
2524 case '-':
2525 case 'A':
2526 case 'a':
2527 install_operand (s[1], opP->reg - ADDR);
2528 break;
2529
2530 case 'B':
2531 tmpreg = get_num (&opP->disp, 80);
2532 switch (s[1])
2533 {
2534 case 'B':
2535 /* The pc_fix argument winds up in fx_pcrel_adjust,
2536 which is a char, and may therefore be unsigned. We
2537 want to pass -1, but we pass 64 instead, and convert
2538 back in md_pcrel_from. */
2539 add_fix ('B', &opP->disp, 1, 64);
2540 break;
2541 case 'W':
2542 add_fix ('w', &opP->disp, 1, 0);
2543 addword (0);
2544 break;
2545 case 'L':
2546 long_branch:
151337e8
NC		 2547 if (! HAVE_LONG_BRANCH (current_architecture))
2548 as_warn (_("Can't use long branches on 68000/68010/5200"));
2549 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2550 add_fix ('l', &opP->disp, 1, 0);
2551 addword (0);
2552 addword (0);
2553 break;
2554 case 'g':
2555 if (subs (&opP->disp)) /* We can't relax it */
2556 goto long_branch;
2557
2558#ifdef OBJ_ELF
2559 /* If the displacement needs pic relocation it cannot be
2560 relaxed. */
2561 if (opP->disp.pic_reloc != pic_none)
2562 goto long_branch;
2563#endif
252b5132 2564 /* This could either be a symbol, or an absolute
151337e8
NC		 2565 address. If it's an absolute address, turn it into
2566 an absolute jump right here and keep it out of the
2567 relaxer. */
2568 if (adds (&opP->disp) == 0)
2569 {
2570 if (the_ins.opcode[0] == 0x6000) /* jbra */
2571 the_ins.opcode[0] = 0x4EF1;
2572 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2573 the_ins.opcode[0] = 0x4EB1;
2574 else /* jCC */
2575 {
2576 the_ins.opcode[0] ^= 0x0100;
2577 the_ins.opcode[0] |= 0x0006;
2578 addword (0x4EF1);
2579 }
2580 add_fix ('l', &opP->disp, 0, 0);
2581 addword (0);
2582 addword (0);
2583 break;
2584 }
2585
2586 /* Now we know it's going into the relaxer. Now figure
2587 out which mode. We try in this order of preference:
2588 long branch, absolute jump, byte/word branches only. */
2589 if (HAVE_LONG_BRANCH (current_architecture))
252b5132 2590 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8
NC		 2591 TAB (BRANCHBWL, SZ_UNDEF));
2592 else if (! flag_keep_pcrel)
2593 {
2594 if ((the_ins.opcode[0] == 0x6000)
2595 || (the_ins.opcode[0] == 0x6100))
2596 add_frag (adds (&opP->disp), offs (&opP->disp),
2597 TAB (BRABSJUNC, SZ_UNDEF));
2598 else
2599 add_frag (adds (&opP->disp), offs (&opP->disp),
2600 TAB (BRABSJCOND, SZ_UNDEF));
2601 }
252b5132
RH		 2602 else
2603 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8 2604 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 2605 break;
2606 case 'w':
2607 if (isvar (&opP->disp))
2608 {
151337e8
NC		 2609 /* Check for DBcc instructions. We can relax them,
2610 but only if we have long branches and/or absolute
2611 jumps. */
2612 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2613 && (HAVE_LONG_BRANCH (current_architecture)
2614 || (! flag_keep_pcrel)))
252b5132 2615 {
151337e8
NC		 2616 if (HAVE_LONG_BRANCH (current_architecture))
2617 add_frag (adds (&opP->disp), offs (&opP->disp),
2618 TAB (DBCCLBR, SZ_UNDEF));
2619 else
2620 add_frag (adds (&opP->disp), offs (&opP->disp),
2621 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 2622 break;
2623 }
252b5132
RH		 2624 add_fix ('w', &opP->disp, 1, 0);
2625 }
2626 addword (0);
2627 break;
2628 case 'C': /* Fixed size LONG coproc branches */
2629 add_fix ('l', &opP->disp, 1, 0);
2630 addword (0);
2631 addword (0);
2632 break;
2633 case 'c': /* Var size Coprocesssor branches */
151337e8 2634 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 2635 {
252b5132
RH		 2636 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2637 add_fix ('l', &opP->disp, 1, 0);
2638 addword (0);
2639 addword (0);
2640 }
151337e8
NC		 2641 else
2642 add_frag (adds (&opP->disp), offs (&opP->disp),
2643 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 2644 break;
2645 default:
2646 abort ();
2647 }
2648 break;
2649
2650 case 'C': /* Ignore it */
2651 break;
2652
2653 case 'd': /* JF this is a kludge */
2654 install_operand ('s', opP->reg - ADDR);
2655 tmpreg = get_num (&opP->disp, 80);
2656 if (!issword (tmpreg))
2657 {
2658 as_warn (_("Expression out of range, using 0"));
2659 tmpreg = 0;
2660 }
2661 addword (tmpreg);
2662 break;
2663
2664 case 'D':
2665 install_operand (s[1], opP->reg - DATA);
2666 break;
2667
6da466c7
ILT		 2668 case 'E': /* Ignore it */
2669 break;
2670
252b5132
RH		 2671 case 'F':
2672 install_operand (s[1], opP->reg - FP0);
2673 break;
2674
6da466c7
ILT		 2675 case 'G': /* Ignore it */
2676 case 'H':
2677 break;
2678
252b5132
RH		 2679 case 'I':
2680 tmpreg = opP->reg - COP0;
2681 install_operand (s[1], tmpreg);
2682 break;
2683
2684 case 'J': /* JF foo */
2685 switch (opP->reg)
2686 {
2687 case SFC:
2688 tmpreg = 0x000;
2689 break;
2690 case DFC:
2691 tmpreg = 0x001;
2692 break;
2693 case CACR:
2694 tmpreg = 0x002;
2695 break;
2696 case TC:
2697 tmpreg = 0x003;
2698 break;
2699 case ITT0:
2700 tmpreg = 0x004;
2701 break;
2702 case ITT1:
2703 tmpreg = 0x005;
2704 break;
2705 case DTT0:
2706 tmpreg = 0x006;
2707 break;
2708 case DTT1:
2709 tmpreg = 0x007;
2710 break;
2711 case BUSCR:
2712 tmpreg = 0x008;
2713 break;
2714
2715 case USP:
2716 tmpreg = 0x800;
2717 break;
2718 case VBR:
2719 tmpreg = 0x801;
2720 break;
2721 case CAAR:
2722 tmpreg = 0x802;
2723 break;
2724 case MSP:
2725 tmpreg = 0x803;
2726 break;
2727 case ISP:
2728 tmpreg = 0x804;
2729 break;
2730 case MMUSR:
2731 tmpreg = 0x805;
2732 break;
2733 case URP:
2734 tmpreg = 0x806;
2735 break;
2736 case SRP:
2737 tmpreg = 0x807;
2738 break;
2739 case PCR:
2740 tmpreg = 0x808;
2741 break;
2742 case ROMBAR:
2743 tmpreg = 0xC00;
2744 break;
2745 case RAMBAR0:
2746 tmpreg = 0xC04;
2747 break;
2748 case RAMBAR1:
2749 tmpreg = 0xC05;
2750 break;
2751 case MBAR:
2752 tmpreg = 0xC0F;
2753 break;
2754 default:
2755 abort ();
2756 }
2757 install_operand (s[1], tmpreg);
2758 break;
2759
2760 case 'k':
2761 tmpreg = get_num (&opP->disp, 55);
2762 install_operand (s[1], tmpreg & 0x7f);
2763 break;
2764
2765 case 'l':
2766 tmpreg = opP->mask;
2767 if (s[1] == 'w')
2768 {
2769 if (tmpreg & 0x7FF0000)
2770 as_bad (_("Floating point register in register list"));
2771 insop (reverse_16_bits (tmpreg), opcode);
2772 }
2773 else
2774 {
2775 if (tmpreg & 0x700FFFF)
2776 as_bad (_("Wrong register in floating-point reglist"));
2777 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2778 }
2779 break;
2780
2781 case 'L':
2782 tmpreg = opP->mask;
2783 if (s[1] == 'w')
2784 {
2785 if (tmpreg & 0x7FF0000)
2786 as_bad (_("Floating point register in register list"));
2787 insop (tmpreg, opcode);
2788 }
2789 else if (s[1] == '8')
2790 {
2791 if (tmpreg & 0x0FFFFFF)
2792 as_bad (_("incorrect register in reglist"));
2793 install_operand (s[1], tmpreg >> 24);
2794 }
2795 else
2796 {
2797 if (tmpreg & 0x700FFFF)
2798 as_bad (_("wrong register in floating-point reglist"));
2799 else
2800 install_operand (s[1], tmpreg >> 16);
2801 }
2802 break;
2803
2804 case 'M':
2805 install_operand (s[1], get_num (&opP->disp, 60));
2806 break;
2807
2808 case 'O':
2809 tmpreg = ((opP->mode == DREG)
8fce3f5e 2810 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 2811 : (get_num (&opP->disp, 40) & 0x1F));
2812 install_operand (s[1], tmpreg);
2813 break;
2814
2815 case 'Q':
2816 tmpreg = get_num (&opP->disp, 10);
2817 if (tmpreg == 8)
2818 tmpreg = 0;
2819 install_operand (s[1], tmpreg);
2820 break;
2821
2822 case 'R':
2823 /* This depends on the fact that ADDR registers are eight
2824 more than their corresponding DATA regs, so the result
2825 will have the ADDR_REG bit set */
2826 install_operand (s[1], opP->reg - DATA);
2827 break;
2828
2829 case 'r':
2830 if (opP->mode == AINDR)
2831 install_operand (s[1], opP->reg - DATA);
2832 else
2833 install_operand (s[1], opP->index.reg - DATA);
2834 break;
2835
2836 case 's':
2837 if (opP->reg == FPI)
2838 tmpreg = 0x1;
2839 else if (opP->reg == FPS)
2840 tmpreg = 0x2;
2841 else if (opP->reg == FPC)
2842 tmpreg = 0x4;
2843 else
2844 abort ();
2845 install_operand (s[1], tmpreg);
2846 break;
2847
2848 case 'S': /* Ignore it */
2849 break;
2850
2851 case 'T':
2852 install_operand (s[1], get_num (&opP->disp, 30));
2853 break;
2854
2855 case 'U': /* Ignore it */
2856 break;
2857
2858 case 'c':
2859 switch (opP->reg)
2860 {
2861 case NC:
2862 tmpreg = 0;
2863 break;
2864 case DC:
2865 tmpreg = 1;
2866 break;
2867 case IC:
2868 tmpreg = 2;
2869 break;
2870 case BC:
2871 tmpreg = 3;
2872 break;
2873 default:
2874 as_fatal (_("failed sanity check"));
2875 } /* switch on cache token */
2876 install_operand (s[1], tmpreg);
2877 break;
2878#ifndef NO_68851
92774660 2879 /* JF: These are out of order, I fear. */
252b5132
RH		 2880 case 'f':
2881 switch (opP->reg)
2882 {
2883 case SFC:
2884 tmpreg = 0;
2885 break;
2886 case DFC:
2887 tmpreg = 1;
2888 break;
2889 default:
2890 abort ();
2891 }
2892 install_operand (s[1], tmpreg);
2893 break;
2894
2895 case '0':
2896 case '1':
2897 case '2':
2898 switch (opP->reg)
2899 {
2900 case TC:
2901 tmpreg = 0;
2902 break;
2903 case CAL:
2904 tmpreg = 4;
2905 break;
2906 case VAL:
2907 tmpreg = 5;
2908 break;
2909 case SCC:
2910 tmpreg = 6;
2911 break;
2912 case AC:
2913 tmpreg = 7;
2914 break;
2915 default:
2916 abort ();
2917 }
2918 install_operand (s[1], tmpreg);
2919 break;
2920
2921 case 'V':
2922 if (opP->reg == VAL)
2923 break;
2924 abort ();
2925
2926 case 'W':
2927 switch (opP->reg)
2928 {
2929 case DRP:
2930 tmpreg = 1;
2931 break;
2932 case SRP:
2933 tmpreg = 2;
2934 break;
2935 case CRP:
2936 tmpreg = 3;
2937 break;
2938 default:
2939 abort ();
2940 }
2941 install_operand (s[1], tmpreg);
2942 break;
2943
2944 case 'X':
2945 switch (opP->reg)
2946 {
2947 case BAD:
2948 case BAD + 1:
2949 case BAD + 2:
2950 case BAD + 3:
2951 case BAD + 4:
2952 case BAD + 5:
2953 case BAD + 6:
2954 case BAD + 7:
2955 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2956 break;
2957
2958 case BAC:
2959 case BAC + 1:
2960 case BAC + 2:
2961 case BAC + 3:
2962 case BAC + 4:
2963 case BAC + 5:
2964 case BAC + 6:
2965 case BAC + 7:
2966 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2967 break;
2968
2969 default:
2970 abort ();
2971 }
2972 install_operand (s[1], tmpreg);
2973 break;
2974 case 'Y':
2975 know (opP->reg == PSR);
2976 break;
2977 case 'Z':
2978 know (opP->reg == PCSR);
2979 break;
2980#endif /* m68851 */
2981 case '3':
2982 switch (opP->reg)
2983 {
2984 case TT0:
2985 tmpreg = 2;
2986 break;
2987 case TT1:
2988 tmpreg = 3;
2989 break;
2990 default:
2991 abort ();
2992 }
2993 install_operand (s[1], tmpreg);
2994 break;
2995 case 't':
2996 tmpreg = get_num (&opP->disp, 20);
2997 install_operand (s[1], tmpreg);
2998 break;
2999 case '_': /* used only for move16 absolute 32-bit address */
3000 if (isvar (&opP->disp))
3001 add_fix ('l', &opP->disp, 0, 0);
3002 tmpreg = get_num (&opP->disp, 80);
3003 addword (tmpreg >> 16);
3004 addword (tmpreg & 0xFFFF);
3005 break;
6da466c7
ILT		 3006 case 'u':
3007 install_operand (s[1], opP->reg - DATA0L);
3008 opP->reg -= (DATA0L);
3009 opP->reg &= 0x0F; /* remove upper/lower bit */
3010 break;
252b5132
RH		 3011 default:
3012 abort ();
3013 }
3014 }
3015
3016 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3017 instruction, ready to be emitted. . . */
252b5132
RH		 3018}
3019
3020static int
3021reverse_16_bits (in)
3022 int in;
3023{
3024 int out = 0;
3025 int n;
3026
3027 static int mask[16] =
3028 {
3029 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3030 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3031 };
3032 for (n = 0; n < 16; n++)
3033 {
3034 if (in & mask[n])
3035 out |= mask[15 - n];
3036 }
3037 return out;
3038} /* reverse_16_bits() */
3039
3040static int
3041reverse_8_bits (in)
3042 int in;
3043{
3044 int out = 0;
3045 int n;
3046
3047 static int mask[8] =
3048 {
3049 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3050 };
3051
3052 for (n = 0; n < 8; n++)
3053 {
3054 if (in & mask[n])
3055 out |= mask[7 - n];
3056 }
3057 return out;
3058} /* reverse_8_bits() */
3059
3060/* Cause an extra frag to be generated here, inserting up to 10 bytes
3061 (that value is chosen in the frag_var call in md_assemble). TYPE
3062 is the subtype of the frag to be generated; its primary type is
3063 rs_machine_dependent.
3064
3065 The TYPE parameter is also used by md_convert_frag_1 and
3066 md_estimate_size_before_relax. The appropriate type of fixup will
3067 be emitted by md_convert_frag_1.
3068
3069 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3070static void
3071install_operand (mode, val)
3072 int mode;
3073 int val;
3074{
3075 switch (mode)
3076 {
3077 case 's':
3078 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3079 break;
3080 case 'd':
3081 the_ins.opcode[0] |= val << 9;
3082 break;
3083 case '1':
3084 the_ins.opcode[1] |= val << 12;
3085 break;
3086 case '2':
3087 the_ins.opcode[1] |= val << 6;
3088 break;
3089 case '3':
3090 the_ins.opcode[1] |= val;
3091 break;
3092 case '4':
3093 the_ins.opcode[2] |= val << 12;
3094 break;
3095 case '5':
3096 the_ins.opcode[2] |= val << 6;
3097 break;
3098 case '6':
3099 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3100 three words long! */
3101 the_ins.numo++;
3102 the_ins.opcode[2] |= val;
3103 break;
3104 case '7':
3105 the_ins.opcode[1] |= val << 7;
3106 break;
3107 case '8':
3108 the_ins.opcode[1] |= val << 10;
3109 break;
3110#ifndef NO_68851
3111 case '9':
3112 the_ins.opcode[1] |= val << 5;
3113 break;
3114#endif
3115
3116 case 't':
3117 the_ins.opcode[1] |= (val << 10) | (val << 7);
3118 break;
3119 case 'D':
3120 the_ins.opcode[1] |= (val << 12) | val;
3121 break;
3122 case 'g':
3123 the_ins.opcode[0] |= val = 0xff;
3124 break;
3125 case 'i':
3126 the_ins.opcode[0] |= val << 9;
3127 break;
3128 case 'C':
3129 the_ins.opcode[1] |= val;
3130 break;
3131 case 'j':
3132 the_ins.opcode[1] |= val;
3133 the_ins.numo++; /* What a hack */
3134 break;
3135 case 'k':
3136 the_ins.opcode[1] |= val << 4;
3137 break;
3138 case 'b':
3139 case 'w':
3140 case 'W':
3141 case 'l':
3142 break;
3143 case 'e':
3144 the_ins.opcode[0] |= (val << 6);
3145 break;
3146 case 'L':
3147 the_ins.opcode[1] = (val >> 16);
3148 the_ins.opcode[2] = val & 0xffff;
3149 break;
6da466c7
ILT		 3150 case 'm':
3151 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3152 the_ins.opcode[0] |= ((val & 0x7) << 9);
3153 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3154 break;
3155 case 'n':
3156 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3157 the_ins.opcode[0] |= ((val & 0x7) << 9);
3158 break;
3159 case 'o':
3160 the_ins.opcode[1] |= val << 12;
3161 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3162 break;
3163 case 'M':
3164 the_ins.opcode[0] |= (val & 0xF);
3165 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3166 break;
3167 case 'N':
3168 the_ins.opcode[1] |= (val & 0xF);
3169 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3170 break;
3171 case 'h':
3172 the_ins.opcode[1] |= ((val != 1) << 10);
3173 break;
252b5132
RH		 3174 case 'c':
3175 default:
3176 as_fatal (_("failed sanity check."));
3177 }
3178} /* install_operand() */
3179
3180static void
3181install_gen_operand (mode, val)
3182 int mode;
3183 int val;
3184{
3185 switch (mode)
3186 {
3187 case 's':
3188 the_ins.opcode[0] |= val;
3189 break;
3190 case 'd':
3191 /* This is a kludge!!! */
3192 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3193 break;
3194 case 'b':
3195 case 'w':
3196 case 'l':
3197 case 'f':
3198 case 'F':
3199 case 'x':
3200 case 'p':
3201 the_ins.opcode[0] |= val;
3202 break;
3203 /* more stuff goes here */
3204 default:
3205 as_fatal (_("failed sanity check."));
3206 }
3207} /* install_gen_operand() */
3208
3209/*
3210 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3211 * then deal with the bitfield hack.
3212 */
3213
3214static char *
3215crack_operand (str, opP)
3216 register char *str;
3217 register struct m68k_op *opP;
3218{
3219 register int parens;
3220 register int c;
3221 register char *beg_str;
3222 int inquote = 0;
3223
3224 if (!str)
3225 {
3226 return str;
3227 }
3228 beg_str = str;
3229 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3230 {
3231 if (! inquote)
3232 {
3233 if (*str == '(')
3234 parens++;
3235 else if (*str == ')')
3236 {
3237 if (!parens)
3238 { /* ERROR */
3239 opP->error = _("Extra )");
3240 return str;
3241 }
3242 --parens;
3243 }
3244 }
3245 if (flag_mri && *str == '\'')
3246 inquote = ! inquote;
3247 }
3248 if (!*str && parens)
3249 { /* ERROR */
3250 opP->error = _("Missing )");
3251 return str;
3252 }
3253 c = *str;
3254 *str = '\0';
3255 if (m68k_ip_op (beg_str, opP) != 0)
3256 {
3257 *str = c;
3258 return str;
3259 }
3260 *str = c;
3261 if (c == '}')
3262 c = *++str; /* JF bitfield hack */
3263 if (c)
3264 {
3265 c = *++str;
3266 if (!c)
3267 as_bad (_("Missing operand"));
3268 }
3269
3270 /* Detect MRI REG symbols and convert them to REGLSTs. */
3271 if (opP->mode == CONTROL && (int)opP->reg < 0)
3272 {
3273 opP->mode = REGLST;
3274 opP->mask = ~(int)opP->reg;
3275 opP->reg = 0;
3276 }
3277
3278 return str;
3279}
3280
3281/* This is the guts of the machine-dependent assembler. STR points to a
3282 machine dependent instruction. This function is supposed to emit
3283 the frags/bytes it assembles to.
3284 */
3285
3286static void
3287insert_reg (regname, regnum)
3288 const char *regname;
3289 int regnum;
3290{
3291 char buf[100];
3292 int i;
3293
3294#ifdef REGISTER_PREFIX
3295 if (!flag_reg_prefix_optional)
3296 {
3297 buf[0] = REGISTER_PREFIX;
3298 strcpy (buf + 1, regname);
3299 regname = buf;
3300 }
3301#endif
3302
3303 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3304 &zero_address_frag));
3305
3306 for (i = 0; regname[i]; i++)
3307 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3308 buf[i] = '\0';
3309
3310 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3311 &zero_address_frag));
3312}
3313
3314struct init_entry
3315 {
3316 const char *name;
3317 int number;
3318 };
3319
3320static const struct init_entry init_table[] =
3321{
3322 { "d0", DATA0 },
3323 { "d1", DATA1 },
3324 { "d2", DATA2 },
3325 { "d3", DATA3 },
3326 { "d4", DATA4 },
3327 { "d5", DATA5 },
3328 { "d6", DATA6 },
3329 { "d7", DATA7 },
3330 { "a0", ADDR0 },
3331 { "a1", ADDR1 },
3332 { "a2", ADDR2 },
3333 { "a3", ADDR3 },
3334 { "a4", ADDR4 },
3335 { "a5", ADDR5 },
3336 { "a6", ADDR6 },
3337 { "fp", ADDR6 },
3338 { "a7", ADDR7 },
3339 { "sp", ADDR7 },
3340 { "ssp", ADDR7 },
3341 { "fp0", FP0 },
3342 { "fp1", FP1 },
3343 { "fp2", FP2 },
3344 { "fp3", FP3 },
3345 { "fp4", FP4 },
3346 { "fp5", FP5 },
3347 { "fp6", FP6 },
3348 { "fp7", FP7 },
3349 { "fpi", FPI },
3350 { "fpiar", FPI },
3351 { "fpc", FPI },
3352 { "fps", FPS },
3353 { "fpsr", FPS },
3354 { "fpc", FPC },
3355 { "fpcr", FPC },
3356 { "control", FPC },
3357 { "status", FPS },
3358 { "iaddr", FPI },
3359
3360 { "cop0", COP0 },
3361 { "cop1", COP1 },
3362 { "cop2", COP2 },
3363 { "cop3", COP3 },
3364 { "cop4", COP4 },
3365 { "cop5", COP5 },
3366 { "cop6", COP6 },
3367 { "cop7", COP7 },
3368 { "pc", PC },
3369 { "zpc", ZPC },
3370 { "sr", SR },
3371
3372 { "ccr", CCR },
3373 { "cc", CCR },
3374
6da466c7
ILT		 3375 { "acc", ACC },
3376 { "macsr", MACSR },
3377 { "mask", MASK },
3378
252b5132
RH		 3379 /* control registers */
3380 { "sfc", SFC }, /* Source Function Code */
3381 { "sfcr", SFC },
3382 { "dfc", DFC }, /* Destination Function Code */
3383 { "dfcr", DFC },
3384 { "cacr", CACR }, /* Cache Control Register */
3385 { "caar", CAAR }, /* Cache Address Register */
3386
3387 { "usp", USP }, /* User Stack Pointer */
3388 { "vbr", VBR }, /* Vector Base Register */
3389 { "msp", MSP }, /* Master Stack Pointer */
3390 { "isp", ISP }, /* Interrupt Stack Pointer */
3391
3392 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3393 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3394 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3395 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3396
3397 /* 68ec040 versions of same */
3398 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3399 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3400 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3401 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3402
3403 /* mcf5200 versions of same. The ColdFire programmer's reference
3404 manual indicated that the order is 2,3,0,1, but Ken Rose
3405 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3406 { "acr0", ITT0 }, /* Access Control Unit 0 */
3407 { "acr1", ITT1 }, /* Access Control Unit 1 */
3408 { "acr2", DTT0 }, /* Access Control Unit 2 */
3409 { "acr3", DTT1 }, /* Access Control Unit 3 */
3410
3411 { "tc", TC }, /* MMU Translation Control Register */
3412 { "tcr", TC },
3413
3414 { "mmusr", MMUSR }, /* MMU Status Register */
3415 { "srp", SRP }, /* User Root Pointer */
3416 { "urp", URP }, /* Supervisor Root Pointer */
3417
3418 { "buscr", BUSCR },
3419 { "pcr", PCR },
3420
3421 { "rombar", ROMBAR }, /* ROM Base Address Register */
3422 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3423 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3424 { "mbar", MBAR }, /* Module Base Address Register */
3425 /* end of control registers */
3426
3427 { "ac", AC },
3428 { "bc", BC },
3429 { "cal", CAL },
3430 { "crp", CRP },
3431 { "drp", DRP },
3432 { "pcsr", PCSR },
3433 { "psr", PSR },
3434 { "scc", SCC },
3435 { "val", VAL },
3436 { "bad0", BAD0 },
3437 { "bad1", BAD1 },
3438 { "bad2", BAD2 },
3439 { "bad3", BAD3 },
3440 { "bad4", BAD4 },
3441 { "bad5", BAD5 },
3442 { "bad6", BAD6 },
3443 { "bad7", BAD7 },
3444 { "bac0", BAC0 },
3445 { "bac1", BAC1 },
3446 { "bac2", BAC2 },
3447 { "bac3", BAC3 },
3448 { "bac4", BAC4 },
3449 { "bac5", BAC5 },
3450 { "bac6", BAC6 },
3451 { "bac7", BAC7 },
3452
3453 { "ic", IC },
3454 { "dc", DC },
3455 { "nc", NC },
3456
3457 { "tt0", TT0 },
3458 { "tt1", TT1 },
3459 /* 68ec030 versions of same */
3460 { "ac0", TT0 },
3461 { "ac1", TT1 },
3462 /* 68ec030 access control unit, identical to 030 MMU status reg */
3463 { "acusr", PSR },
3464
3465 /* Suppressed data and address registers. */
3466 { "zd0", ZDATA0 },
3467 { "zd1", ZDATA1 },
3468 { "zd2", ZDATA2 },
3469 { "zd3", ZDATA3 },
3470 { "zd4", ZDATA4 },
3471 { "zd5", ZDATA5 },
3472 { "zd6", ZDATA6 },
3473 { "zd7", ZDATA7 },
3474 { "za0", ZADDR0 },
3475 { "za1", ZADDR1 },
3476 { "za2", ZADDR2 },
3477 { "za3", ZADDR3 },
3478 { "za4", ZADDR4 },
3479 { "za5", ZADDR5 },
3480 { "za6", ZADDR6 },
3481 { "za7", ZADDR7 },
3482
92774660 3483 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 3484 { "d0l", DATA0L },
3485 { "d1l", DATA1L },
3486 { "d2l", DATA2L },
3487 { "d3l", DATA3L },
3488 { "d4l", DATA4L },
3489 { "d5l", DATA5L },
3490 { "d6l", DATA6L },
3491 { "d7l", DATA7L },
3492
3493 { "a0l", ADDR0L },
3494 { "a1l", ADDR1L },
3495 { "a2l", ADDR2L },
3496 { "a3l", ADDR3L },
3497 { "a4l", ADDR4L },
3498 { "a5l", ADDR5L },
3499 { "a6l", ADDR6L },
3500 { "a7l", ADDR7L },
3501
3502 { "d0u", DATA0U },
3503 { "d1u", DATA1U },
3504 { "d2u", DATA2U },
3505 { "d3u", DATA3U },
3506 { "d4u", DATA4U },
3507 { "d5u", DATA5U },
3508 { "d6u", DATA6U },
3509 { "d7u", DATA7U },
3510
3511 { "a0u", ADDR0U },
3512 { "a1u", ADDR1U },
3513 { "a2u", ADDR2U },
3514 { "a3u", ADDR3U },
3515 { "a4u", ADDR4U },
3516 { "a5u", ADDR5U },
3517 { "a6u", ADDR6U },
3518 { "a7u", ADDR7U },
3519
252b5132
RH		 3520 { 0, 0 }
3521};
3522
3523static void
3524init_regtable ()
3525{
3526 int i;
3527 for (i = 0; init_table[i].name; i++)
3528 insert_reg (init_table[i].name, init_table[i].number);
3529}
3530
3531static int no_68851, no_68881;
3532
3533#ifdef OBJ_AOUT
3534/* a.out machine type. Default to 68020. */
3535int m68k_aout_machtype = 2;
3536#endif
3537
3538void
3539md_assemble (str)
3540 char *str;
3541{
3542 const char *er;
3543 short *fromP;
3544 char *toP = NULL;
3545 int m, n = 0;
3546 char *to_beg_P;
3547 int shorts_this_frag;
3548 fixS *fixP;
3549
3550 /* In MRI mode, the instruction and operands are separated by a
3551 space. Anything following the operands is a comment. The label
3552 has already been removed. */
3553 if (flag_mri)
3554 {
3555 char *s;
3556 int fields = 0;
3557 int infield = 0;
3558 int inquote = 0;
3559
3560 for (s = str; *s != '\0'; s++)
3561 {
3562 if ((*s == ' ' || *s == '\t') && ! inquote)
3563 {
3564 if (infield)
3565 {
3566 ++fields;
3567 if (fields >= 2)
3568 {
3569 *s = '\0';
3570 break;
3571 }
3572 infield = 0;
3573 }
3574 }
3575 else
3576 {
3577 if (! infield)
3578 infield = 1;
3579 if (*s == '\'')
3580 inquote = ! inquote;
3581 }
3582 }
3583 }
3584
3585 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3586 m68k_ip (str);
3587 er = the_ins.error;
3588 if (!er)
3589 {
3590 for (n = 0; n < the_ins.numargs; n++)
3591 if (the_ins.operands[n].error)
3592 {
3593 er = the_ins.operands[n].error;
3594 break;
3595 }
3596 }
3597 if (er)
3598 {
3599 as_bad (_("%s -- statement `%s' ignored"), er, str);
3600 return;
3601 }
3602
3603 /* If there is a current label, record that it marks an instruction. */
3604 if (current_label != NULL)
3605 {
3606 current_label->text = 1;
3607 current_label = NULL;
3608 }
3609
3610 if (the_ins.nfrag == 0)
3611 {
3612 /* No frag hacking involved; just put it out */
3613 toP = frag_more (2 * the_ins.numo);
3614 fromP = &the_ins.opcode[0];
3615 for (m = the_ins.numo; m; --m)
3616 {
3617 md_number_to_chars (toP, (long) (*fromP), 2);
3618 toP += 2;
3619 fromP++;
3620 }
3621 /* put out symbol-dependent info */
3622 for (m = 0; m < the_ins.nrel; m++)
3623 {
3624 switch (the_ins.reloc[m].wid)
3625 {
3626 case 'B':
3627 n = 1;
3628 break;
3629 case 'b':
3630 n = 1;
3631 break;
3632 case '3':
3633 n = 1;
3634 break;
3635 case 'w':
3636 case 'W':
3637 n = 2;
3638 break;
3639 case 'l':
3640 n = 4;
3641 break;
3642 default:
3643 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3644 the_ins.reloc[m].wid);
3645 }
3646
3647 fixP = fix_new_exp (frag_now,
3648 ((toP - frag_now->fr_literal)
3649 - the_ins.numo * 2 + the_ins.reloc[m].n),
3650 n,
3651 &the_ins.reloc[m].exp,
3652 the_ins.reloc[m].pcrel,
3653 get_reloc_code (n, the_ins.reloc[m].pcrel,
3654 the_ins.reloc[m].pic_reloc));
3655 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3656 if (the_ins.reloc[m].wid == 'B')
3657 fixP->fx_signed = 1;
3658 }
3659 return;
3660 }
3661
3662 /* There's some frag hacking */
3663 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3664 {
3665 int wid;
3666
3667 if (n == 0)
3668 wid = 2 * the_ins.fragb[n].fragoff;
3669 else
3670 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3671 toP = frag_more (wid);
3672 to_beg_P = toP;
3673 shorts_this_frag = 0;
3674 for (m = wid / 2; m; --m)
3675 {
3676 md_number_to_chars (toP, (long) (*fromP), 2);
3677 toP += 2;
3678 fromP++;
3679 shorts_this_frag++;
3680 }
3681 for (m = 0; m < the_ins.nrel; m++)
3682 {
3683 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3684 {
3685 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3686 break;
3687 }
3688 wid = the_ins.reloc[m].wid;
3689 if (wid == 0)
3690 continue;
3691 the_ins.reloc[m].wid = 0;
3692 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3693
3694 fixP = fix_new_exp (frag_now,
3695 ((toP - frag_now->fr_literal)
3696 - the_ins.numo * 2 + the_ins.reloc[m].n),
3697 wid,
3698 &the_ins.reloc[m].exp,
3699 the_ins.reloc[m].pcrel,
3700 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3701 the_ins.reloc[m].pic_reloc));
3702 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3703 }
3704 (void) frag_var (rs_machine_dependent, 10, 0,
3705 (relax_substateT) (the_ins.fragb[n].fragty),
3706 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3707 }
3708 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3709 shorts_this_frag = 0;
3710 if (n)
3711 {
3712 toP = frag_more (n * sizeof (short));
3713 while (n--)
3714 {
3715 md_number_to_chars (toP, (long) (*fromP), 2);
3716 toP += 2;
3717 fromP++;
3718 shorts_this_frag++;
3719 }
3720 }
3721 for (m = 0; m < the_ins.nrel; m++)
3722 {
3723 int wid;
3724
3725 wid = the_ins.reloc[m].wid;
3726 if (wid == 0)
3727 continue;
3728 the_ins.reloc[m].wid = 0;
3729 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3730
3731 fixP = fix_new_exp (frag_now,
3732 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3733 - shorts_this_frag * 2),
3734 wid,
3735 &the_ins.reloc[m].exp,
3736 the_ins.reloc[m].pcrel,
3737 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3738 the_ins.reloc[m].pic_reloc));
3739 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3740 }
3741}
3742
3743void
3744md_begin ()
3745{
3746 /*
3747 * md_begin -- set up hash tables with 68000 instructions.
3748 * similar to what the vax assembler does. ---phr
3749 */
3750 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3751 a copy of it at runtime, adding in the information we want but isn't
3752 there. I think it'd be better to have an awk script hack the table
3753 at compile time. Or even just xstr the table and use it as-is. But
3754 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3755 names. */
3756
3757 register const struct m68k_opcode *ins;
3758 register struct m68k_incant *hack, *slak;
3759 register const char *retval = 0; /* empty string, or error msg text */
8fce3f5e 3760 register int i;
252b5132
RH		 3761 register char c;
3762
3763 if (flag_mri)
3764 {
3765 flag_reg_prefix_optional = 1;
3766 m68k_abspcadd = 1;
3767 if (! m68k_rel32_from_cmdline)
3768 m68k_rel32 = 0;
3769 }
3770
3771 op_hash = hash_new ();
3772
3773 obstack_begin (&robyn, 4000);
3774 for (i = 0; i < m68k_numopcodes; i++)
3775 {
3776 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3777 do
3778 {
3779 ins = &m68k_opcodes[i];
3780 /* We *could* ignore insns that don't match our arch here
92774660 3781 but just leaving them out of the hash. */
252b5132
RH		 3782 slak->m_operands = ins->args;
3783 slak->m_opnum = strlen (slak->m_operands) / 2;
3784 slak->m_arch = ins->arch;
3785 slak->m_opcode = ins->opcode;
3786 /* This is kludgey */
3787 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3788 if (i + 1 != m68k_numopcodes
3789 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3790 {
3791 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3792 i++;
3793 }
3794 else
3795 slak->m_next = 0;
3796 slak = slak->m_next;
3797 }
3798 while (slak);
3799
3800 retval = hash_insert (op_hash, ins->name, (char *) hack);
3801 if (retval)
3802 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3803 }
3804
3805 for (i = 0; i < m68k_numaliases; i++)
3806 {
3807 const char *name = m68k_opcode_aliases[i].primary;
3808 const char *alias = m68k_opcode_aliases[i].alias;
3809 PTR val = hash_find (op_hash, name);
3810 if (!val)
3811 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3812 retval = hash_insert (op_hash, alias, val);
3813 if (retval)
3814 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3815 }
3816
3817 /* In MRI mode, all unsized branches are variable sized. Normally,
3818 they are word sized. */
3819 if (flag_mri)
3820 {
3821 static struct m68k_opcode_alias mri_aliases[] =
3822 {
3823 { "bhi", "jhi", },
3824 { "bls", "jls", },
3825 { "bcc", "jcc", },
3826 { "bcs", "jcs", },
3827 { "bne", "jne", },
3828 { "beq", "jeq", },
3829 { "bvc", "jvc", },
3830 { "bvs", "jvs", },
3831 { "bpl", "jpl", },
3832 { "bmi", "jmi", },
3833 { "bge", "jge", },
3834 { "blt", "jlt", },
3835 { "bgt", "jgt", },
3836 { "ble", "jle", },
3837 { "bra", "jra", },
3838 { "bsr", "jbsr", },
3839 };
3840
8fce3f5e
AM		 3841 for (i = 0;
3842 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
3843 i++)
252b5132
RH		 3844 {
3845 const char *name = mri_aliases[i].primary;
3846 const char *alias = mri_aliases[i].alias;
3847 PTR val = hash_find (op_hash, name);
3848 if (!val)
3849 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3850 retval = hash_jam (op_hash, alias, val);
3851 if (retval)
3852 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3853 }
3854 }
3855
8fce3f5e 3856 for (i = 0; i < (int) sizeof (mklower_table); i++)
252b5132
RH		 3857 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3858
8fce3f5e 3859 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 3860 {
3861 notend_table[i] = 0;
3862 alt_notend_table[i] = 0;
3863 }
3864 notend_table[','] = 1;
3865 notend_table['{'] = 1;
3866 notend_table['}'] = 1;
3867 alt_notend_table['a'] = 1;
3868 alt_notend_table['A'] = 1;
3869 alt_notend_table['d'] = 1;
3870 alt_notend_table['D'] = 1;
3871 alt_notend_table['#'] = 1;
3872 alt_notend_table['&'] = 1;
3873 alt_notend_table['f'] = 1;
3874 alt_notend_table['F'] = 1;
3875#ifdef REGISTER_PREFIX
3876 alt_notend_table[REGISTER_PREFIX] = 1;
3877#endif
3878
3879 /* We need to put '(' in alt_notend_table to handle
3880 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3881 */
3882 alt_notend_table['('] = 1;
3883
3884 /* We need to put '@' in alt_notend_table to handle
3885 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3886 */
3887 alt_notend_table['@'] = 1;
3888
3889 /* We need to put digits in alt_notend_table to handle
3890 bfextu %d0{24:1},%d0
3891 */
3892 alt_notend_table['0'] = 1;
3893 alt_notend_table['1'] = 1;
3894 alt_notend_table['2'] = 1;
3895 alt_notend_table['3'] = 1;
3896 alt_notend_table['4'] = 1;
3897 alt_notend_table['5'] = 1;
3898 alt_notend_table['6'] = 1;
3899 alt_notend_table['7'] = 1;
3900 alt_notend_table['8'] = 1;
3901 alt_notend_table['9'] = 1;
3902
3903#ifndef MIT_SYNTAX_ONLY
3904 /* Insert pseudo ops, these have to go into the opcode table since
3905 gas expects pseudo ops to start with a dot */
3906 {
3907 int n = 0;
3908 while (mote_pseudo_table[n].poc_name)
3909 {
3910 hack = (struct m68k_incant *)
3911 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3912 hash_insert (op_hash,
3913 mote_pseudo_table[n].poc_name, (char *) hack);
3914 hack->m_operands = 0;
3915 hack->m_opnum = n;
3916 n++;
3917 }
3918 }
3919#endif
3920
3921 init_regtable ();
3922
3923#ifdef OBJ_ELF
3924 record_alignment (text_section, 2);
3925 record_alignment (data_section, 2);
3926 record_alignment (bss_section, 2);
3927#endif
3928}
3929
3930static void
3931select_control_regs ()
3932{
3933 /* Note which set of "movec" control registers is available. */
3934 switch (cpu_of_arch (current_architecture))
3935 {
3936 case m68000:
3937 control_regs = m68000_control_regs;
3938 break;
3939 case m68010:
3940 control_regs = m68010_control_regs;
3941 break;
3942 case m68020:
3943 case m68030:
3944 control_regs = m68020_control_regs;
3945 break;
3946 case m68040:
3947 control_regs = m68040_control_regs;
3948 break;
3949 case m68060:
3950 control_regs = m68060_control_regs;
3951 break;
3952 case cpu32:
3953 control_regs = cpu32_control_regs;
3954 break;
3955 case mcf5200:
6da466c7
ILT		 3956 case mcf5206e:
3957 case mcf5307:
3958 control_regs = mcf_control_regs;
252b5132
RH		 3959 break;
3960 default:
3961 abort ();
3962 }
3963}
3964
3965void
3966m68k_init_after_args ()
3967{
3968 if (cpu_of_arch (current_architecture) == 0)
3969 {
3970 int i;
3971 const char *default_cpu = TARGET_CPU;
3972
3973 if (*default_cpu == 'm')
3974 default_cpu++;
3975 for (i = 0; i < n_archs; i++)
3976 if (strcasecmp (default_cpu, archs[i].name) == 0)
3977 break;
3978 if (i == n_archs)
3979 {
3980 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
3981 current_architecture |= m68020;
3982 }
3983 else
3984 current_architecture |= archs[i].arch;
3985 }
3986 /* Permit m68881 specification with all cpus; those that can't work
3987 with a coprocessor could be doing emulation. */
3988 if (current_architecture & m68851)
3989 {
3990 if (current_architecture & m68040)
3991 {
3992 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
3993 }
3994 }
3995 /* What other incompatibilities could we check for? */
3996
3997 /* Toss in some default assumptions about coprocessors. */
3998 if (!no_68881
3999 && (cpu_of_arch (current_architecture)
4000 /* Can CPU32 have a 68881 coprocessor?? */
4001 & (m68020 | m68030 | cpu32)))
4002 {
4003 current_architecture |= m68881;
4004 }
4005 if (!no_68851
4006 && (cpu_of_arch (current_architecture) & m68020up) != 0
4007 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4008 {
4009 current_architecture |= m68851;
4010 }
4011 if (no_68881 && (current_architecture & m68881))
4012 as_bad (_("options for 68881 and no-68881 both given"));
4013 if (no_68851 && (current_architecture & m68851))
4014 as_bad (_("options for 68851 and no-68851 both given"));
4015
4016#ifdef OBJ_AOUT
4017 /* Work out the magic number. This isn't very general. */
4018 if (current_architecture & m68000)
4019 m68k_aout_machtype = 0;
4020 else if (current_architecture & m68010)
4021 m68k_aout_machtype = 1;
4022 else if (current_architecture & m68020)
4023 m68k_aout_machtype = 2;
4024 else
4025 m68k_aout_machtype = 2;
4026#endif
4027
4028 /* Note which set of "movec" control registers is available. */
4029 select_control_regs ();
4030
4031 if (cpu_of_arch (current_architecture) < m68020
6da466c7 4032 || arch_coldfire_p (current_architecture))
252b5132
RH		 4033 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4034}
4035\f
4036/* This is called when a label is defined. */
4037
4038void
4039m68k_frob_label (sym)
4040 symbolS *sym;
4041{
4042 struct label_line *n;
4043
4044 n = (struct label_line *) xmalloc (sizeof *n);
4045 n->next = labels;
4046 n->label = sym;
4047 as_where (&n->file, &n->line);
4048 n->text = 0;
4049 labels = n;
4050 current_label = n;
4051}
4052
4053/* This is called when a value that is not an instruction is emitted. */
4054
4055void
4056m68k_flush_pending_output ()
4057{
4058 current_label = NULL;
4059}
4060
4061/* This is called at the end of the assembly, when the final value of
4062 the label is known. We warn if this is a text symbol aligned at an
4063 odd location. */
4064
4065void
4066m68k_frob_symbol (sym)
4067 symbolS *sym;
4068{
4069 if (S_GET_SEGMENT (sym) == reg_section
4070 && (int) S_GET_VALUE (sym) < 0)
4071 {
4072 S_SET_SEGMENT (sym, absolute_section);
4073 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4074 }
4075 else if ((S_GET_VALUE (sym) & 1) != 0)
4076 {
4077 struct label_line *l;
4078
4079 for (l = labels; l != NULL; l = l->next)
4080 {
4081 if (l->label == sym)
4082 {
4083 if (l->text)
4084 as_warn_where (l->file, l->line,
4085 _("text label `%s' aligned to odd boundary"),
4086 S_GET_NAME (sym));
4087 break;
4088 }
4089 }
4090 }
4091}
4092\f
4093/* This is called if we go in or out of MRI mode because of the .mri
4094 pseudo-op. */
4095
4096void
4097m68k_mri_mode_change (on)
4098 int on;
4099{
4100 if (on)
4101 {
4102 if (! flag_reg_prefix_optional)
4103 {
4104 flag_reg_prefix_optional = 1;
4105#ifdef REGISTER_PREFIX
4106 init_regtable ();
4107#endif
4108 }
4109 m68k_abspcadd = 1;
4110 if (! m68k_rel32_from_cmdline)
4111 m68k_rel32 = 0;
4112 }
4113 else
4114 {
4115 if (! reg_prefix_optional_seen)
4116 {
4117#ifdef REGISTER_PREFIX_OPTIONAL
4118 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4119#else
4120 flag_reg_prefix_optional = 0;
4121#endif
4122#ifdef REGISTER_PREFIX
4123 init_regtable ();
4124#endif
4125 }
4126 m68k_abspcadd = 0;
4127 if (! m68k_rel32_from_cmdline)
4128 m68k_rel32 = 1;
4129 }
4130}
4131
4132/* Equal to MAX_PRECISION in atof-ieee.c */
4133#define MAX_LITTLENUMS 6
4134
4135/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4136 of type TYPE, and store the appropriate bytes in *LITP. The number
4137 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4138 returned, or NULL on OK. */
4139
4140char *
4141md_atof (type, litP, sizeP)
4142 char type;
4143 char *litP;
4144 int *sizeP;
4145{
4146 int prec;
4147 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4148 LITTLENUM_TYPE *wordP;
4149 char *t;
4150
4151 switch (type)
4152 {
4153 case 'f':
4154 case 'F':
4155 case 's':
4156 case 'S':
4157 prec = 2;
4158 break;
4159
4160 case 'd':
4161 case 'D':
4162 case 'r':
4163 case 'R':
4164 prec = 4;
4165 break;
4166
4167 case 'x':
4168 case 'X':
4169 prec = 6;
4170 break;
4171
4172 case 'p':
4173 case 'P':
4174 prec = 6;
4175 break;
4176
4177 default:
4178 *sizeP = 0;
4179 return _("Bad call to MD_ATOF()");
4180 }
4181 t = atof_ieee (input_line_pointer, type, words);
4182 if (t)
4183 input_line_pointer = t;
4184
4185 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4186 for (wordP = words; prec--;)
4187 {
4188 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4189 litP += sizeof (LITTLENUM_TYPE);
4190 }
4191 return 0;
4192}
4193
4194void
4195md_number_to_chars (buf, val, n)
4196 char *buf;
4197 valueT val;
4198 int n;
4199{
4200 number_to_chars_bigendian (buf, val, n);
4201}
4202
4203static void
4204md_apply_fix_2 (fixP, val)
4205 fixS *fixP;
4206 offsetT val;
4207{
4208 addressT upper_limit;
4209 offsetT lower_limit;
4210
4211 /* This is unnecessary but it convinces the native rs6000 compiler
4212 to generate the code we want. */
4213 char *buf = fixP->fx_frag->fr_literal;
4214 buf += fixP->fx_where;
4215 /* end ibm compiler workaround */
4216
4217 if (val & 0x80000000)
4218 val |= ~(addressT)0x7fffffff;
4219 else
4220 val &= 0x7fffffff;
4221
4222#ifdef OBJ_ELF
4223 if (fixP->fx_addsy)
4224 {
4225 memset (buf, 0, fixP->fx_size);
4226 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4227
4228 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4229 && !S_IS_DEFINED (fixP->fx_addsy)
4230 && !S_IS_WEAK (fixP->fx_addsy))
4231 S_SET_WEAK (fixP->fx_addsy);
4232 return;
4233 }
4234#endif
4235
4236#ifdef BFD_ASSEMBLER
4237 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4238 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4239 return;
4240#endif
4241
4242 switch (fixP->fx_size)
4243 {
4244 /* The cast to offsetT below are necessary to make code correct for
4245 machines where ints are smaller than offsetT */
4246 case 1:
4247 *buf++ = val;
4248 upper_limit = 0x7f;
4249 lower_limit = - (offsetT) 0x80;
4250 break;
4251 case 2:
4252 *buf++ = (val >> 8);
4253 *buf++ = val;
4254 upper_limit = 0x7fff;
4255 lower_limit = - (offsetT) 0x8000;
4256 break;
4257 case 4:
4258 *buf++ = (val >> 24);
4259 *buf++ = (val >> 16);
4260 *buf++ = (val >> 8);
4261 *buf++ = val;
4262 upper_limit = 0x7fffffff;
4263 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4264 break;
4265 default:
4266 BAD_CASE (fixP->fx_size);
4267 }
4268
4269 /* Fix up a negative reloc. */
4270 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4271 {
4272 fixP->fx_addsy = fixP->fx_subsy;
4273 fixP->fx_subsy = NULL;
4274 fixP->fx_tcbit = 1;
4275 }
4276
4277 /* For non-pc-relative values, it's conceivable we might get something
4278 like "0xff" for a byte field. So extend the upper part of the range
4279 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4280 so that we can do any range checking at all. */
4281 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4282 upper_limit = upper_limit * 2 + 1;
4283
4284 if ((addressT) val > upper_limit
4285 && (val > 0 || val < lower_limit))
4286 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4287
4288 /* A one byte PC-relative reloc means a short branch. We can't use
4289 a short branch with a value of 0 or -1, because those indicate
4290 different opcodes (branches with longer offsets). fixup_segment
4291 in write.c may have clobbered fx_pcrel, so we need to examine the
4292 reloc type. */
4293 if ((fixP->fx_pcrel
4294#ifdef BFD_ASSEMBLER
4295 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4296#endif
4297 )
4298 && fixP->fx_size == 1
4299 && (fixP->fx_addsy == NULL
4300 || S_IS_DEFINED (fixP->fx_addsy))
4301 && (val == 0 || val == -1))
4302 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4303}
4304
4305#ifdef BFD_ASSEMBLER
4306int
4307md_apply_fix (fixP, valp)
4308 fixS *fixP;
4309 valueT *valp;
4310{
4311 md_apply_fix_2 (fixP, (addressT) *valp);
4312 return 1;
4313}
4314#else
4315void md_apply_fix (fixP, val)
4316 fixS *fixP;
4317 long val;
4318{
4319 md_apply_fix_2 (fixP, (addressT) val);
4320}
4321#endif
4322
4323/* *fragP has been relaxed to its final size, and now needs to have
4324 the bytes inside it modified to conform to the new size There is UGLY
4325 MAGIC here. ..
4326 */
4327static void
4328md_convert_frag_1 (fragP)
4329 register fragS *fragP;
4330{
4331 long disp;
252b5132
RH		 4332 fixS *fixP;
4333
4334 /* Address in object code of the displacement. */
4335 register int object_address = fragP->fr_fix + fragP->fr_address;
4336
4337 /* Address in gas core of the place to store the displacement. */
4338 /* This convinces the native rs6000 compiler to generate the code we
92774660 4339 want. */
252b5132
RH		 4340 register char *buffer_address = fragP->fr_literal;
4341 buffer_address += fragP->fr_fix;
4342 /* end ibm compiler workaround */
4343
4344 /* The displacement of the address, from current location. */
4345 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4346 disp = (disp + fragP->fr_offset) - object_address;
4347
4348#ifdef BFD_ASSEMBLER
49309057 4349 disp += symbol_get_frag (fragP->fr_symbol)->fr_address;
252b5132
RH		 4350#endif
4351
4352 switch (fragP->fr_subtype)
4353 {
151337e8
NC		 4354 case TAB (BRANCHBWL, BYTE):
4355 case TAB (BRABSJUNC, BYTE):
4356 case TAB (BRABSJCOND, BYTE):
4357 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4358 know (issbyte (disp));
4359 if (disp == 0)
4360 as_bad (_("short branch with zero offset: use :w"));
151337e8
NC		 4361 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4362 fragP->fr_offset, 1, BFD_RELOC_8_PCREL);
4363 fixP->fx_pcrel_adjust = -1;
252b5132 4364 break;
151337e8
NC		 4365 case TAB (BRANCHBWL, SHORT):
4366 case TAB (BRABSJUNC, SHORT):
4367 case TAB (BRABSJCOND, SHORT):
4368 case TAB (BRANCHBW, SHORT):
252b5132 4369 fragP->fr_opcode[1] = 0x00;
151337e8
NC		 4370 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4371 1, BFD_RELOC_16_PCREL);
4372 fragP->fr_fix += 2;
4373 break;
4374 case TAB (BRANCHBWL, LONG):
4375 fragP->fr_opcode[1] = (char) 0xFF;
4376 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4377 1, BFD_RELOC_32_PCREL);
4378 fragP->fr_fix += 4;
252b5132 4379 break;
151337e8
NC		 4380 case TAB (BRABSJUNC, LONG):
4381 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4382 {
151337e8
NC		 4383 fragP->fr_opcode[0] = 0x4E;
4384 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand */
4385 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4386 0, BFD_RELOC_32);
4387 fragP->fr_fix += 4;
4388 }
4389 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4390 {
4391 fragP->fr_opcode[0] = 0x4E;
4392 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand */
4393 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4394 0, BFD_RELOC_32);
4395 fragP->fr_fix += 4;
252b5132
RH		 4396 }
4397 else
4398 {
151337e8
NC		 4399 /* This cannot happen, because jbsr and jbra are the only two
4400 unconditional branches. */
4401 abort ();
252b5132
RH		 4402 }
4403 break;
151337e8
NC		 4404 case TAB (BRABSJCOND, LONG):
4405 /* Only Bcc 68000 instructions can come here. */
4406 /* Change bcc into b!cc/jmp absl long. */
92774660 4407
252b5132
RH		 4408 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4409 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4410
4411 /* JF: these used to be fr_opcode[2,3], but they may be in a
4412 different frag, in which case refering to them is a no-no.
92774660 4413 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4414 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4415 *buffer_address++ = (char) 0xf9;
4416 fragP->fr_fix += 2; /* account for jmp instruction */
4417 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
151337e8
NC		 4418 fragP->fr_offset, 0, BFD_RELOC_32);
4419 fragP->fr_fix += 4;
4420 break;
4421 case TAB (FBRANCH, SHORT):
4422 know ((fragP->fr_opcode[1] & 0x40) == 0);
4423 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4424 1, BFD_RELOC_16_PCREL);
4425 fragP->fr_fix += 2;
4426 break;
4427 case TAB (FBRANCH, LONG):
4428 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4429 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4430 1, BFD_RELOC_32_PCREL);
252b5132 4431 fragP->fr_fix += 4;
252b5132 4432 break;
151337e8
NC		 4433 case TAB (DBCCLBR, SHORT):
4434 case TAB (DBCCABSJ, SHORT):
4435 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4436 1, BFD_RELOC_16_PCREL);
4437 fragP->fr_fix += 2;
4438 break;
4439 case TAB (DBCCLBR, LONG):
4440 /* only DBcc instructions can come here */
28e7409f 4441 /* Change dbcc into dbcc/bral. */
28e7409f 4442
252b5132
RH		 4443 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4444 *buffer_address++ = 0x00; /* branch offset = 4 */
4445 *buffer_address++ = 0x04;
4446 *buffer_address++ = 0x60; /* put in bra pc+6 */
4447 *buffer_address++ = 0x06;
151337e8
NC		 4448 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4449 *buffer_address++ = (char) 0xff;
252b5132
RH		 4450
4451 fragP->fr_fix += 6; /* account for bra/jmp instructions */
151337e8
NC		 4452 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4453 BFD_RELOC_32_PCREL);
252b5132 4454 fragP->fr_fix += 4;
252b5132 4455 break;
151337e8
NC		 4456 case TAB (DBCCABSJ, LONG):
4457 /* only DBcc instructions can come here */
4458 /* Change dbcc into dbcc/jmp. */
4459
4460 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4461 *buffer_address++ = 0x00; /* branch offset = 4 */
4462 *buffer_address++ = 0x04;
4463 *buffer_address++ = 0x60; /* put in bra pc+6 */
4464 *buffer_address++ = 0x06;
4465 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4466 *buffer_address++ = (char) 0xf9;
4467
4468 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4469 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4470 BFD_RELOC_32);
252b5132 4471 fragP->fr_fix += 4;
252b5132 4472 break;
151337e8 4473 case TAB (PCREL1632, SHORT):
252b5132
RH		 4474 fragP->fr_opcode[1] &= ~0x3F;
4475 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
151337e8
NC		 4476 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4477 fragP->fr_offset, 1, BFD_RELOC_16_PCREL);
4478 fragP->fr_fix += 2;
252b5132 4479 break;
151337e8 4480 case TAB (PCREL1632, LONG):
252b5132
RH		 4481 /* Already set to mode 7.3; this indicates: PC indirect with
4482 suppressed index, 32-bit displacement. */
4483 *buffer_address++ = 0x01;
4484 *buffer_address++ = 0x70;
4485 fragP->fr_fix += 2;
151337e8
NC		 4486 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4487 fragP->fr_offset, 1, BFD_RELOC_32_PCREL);
4488 fixP->fx_pcrel_adjust = 2;
4489 fragP->fr_fix += 4;
252b5132 4490 break;
252b5132 4491 case TAB (PCINDEX, BYTE):
252b5132
RH		 4492 assert (fragP->fr_fix >= 2);
4493 buffer_address[-2] &= ~1;
151337e8
NC		 4494 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4495 fragP->fr_offset, 1, BFD_RELOC_8_PCREL);
4496 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 4497 break;
4498 case TAB (PCINDEX, SHORT):
252b5132
RH		 4499 assert (fragP->fr_fix >= 2);
4500 buffer_address[-2] |= 0x1;
4501 buffer_address[-1] = 0x20;
4502 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
151337e8 4503 fragP->fr_offset, 1, BFD_RELOC_16_PCREL);
252b5132 4504 fixP->fx_pcrel_adjust = 2;
151337e8 4505 fragP->fr_fix += 2;
252b5132
RH		 4506 break;
4507 case TAB (PCINDEX, LONG):
252b5132
RH		 4508 assert (fragP->fr_fix >= 2);
4509 buffer_address[-2] |= 0x1;
4510 buffer_address[-1] = 0x30;
151337e8
NC		 4511 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4512 fragP->fr_offset, 1, BFD_RELOC_32_PCREL);
4513 fixP->fx_pcrel_adjust = 2;
4514 fragP->fr_fix += 4;
4515 break;
4516 case TAB (ABSTOPCREL, SHORT):
4517 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4518 1, BFD_RELOC_16_PCREL);
4519 fragP->fr_fix += 2;
4520 break;
4521 case TAB (ABSTOPCREL, LONG):
4522 /* The thing to do here is force it to ABSOLUTE LONG, since
4523 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */
4524 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4525 abort ();
4526 fragP->fr_opcode[1] &= ~0x3F;
4527 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4528 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4529 0, BFD_RELOC_32);
4530 fragP->fr_fix += 4;
252b5132 4531 break;
252b5132
RH		 4532 }
4533}
4534
4535#ifndef BFD_ASSEMBLER
4536
4537void
4538md_convert_frag (headers, sec, fragP)
8fce3f5e
AM		 4539 object_headers *headers ATTRIBUTE_UNUSED;
4540 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4541 fragS *fragP;
4542{
4543 md_convert_frag_1 (fragP);
4544}
4545
4546#else
4547
4548void
4549md_convert_frag (abfd, sec, fragP)
36823076
AS		 4550 bfd *abfd ATTRIBUTE_UNUSED;
4551 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4552 fragS *fragP;
4553{
4554 md_convert_frag_1 (fragP);
4555}
4556#endif
4557
4558/* Force truly undefined symbols to their maximum size, and generally set up
4559 the frag list to be relaxed
4560 */
4561int
4562md_estimate_size_before_relax (fragP, segment)
4563 register fragS *fragP;
4564 segT segment;
4565{
4566 int old_fix;
4567 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4568
4569 old_fix = fragP->fr_fix;
4570
151337e8 4571 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 4572 switch (fragP->fr_subtype)
4573 {
151337e8
NC		 4574 case TAB (BRANCHBWL, SZ_UNDEF):
4575 case TAB (BRABSJUNC, SZ_UNDEF):
252b5132 4576 {
151337e8 4577 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
252b5132
RH		 4578 && relaxable_symbol (fragP->fr_symbol))
4579 {
4580 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
8fce3f5e 4581 }
151337e8 4582 else if (flag_short_refs)
252b5132 4583 {
151337e8
NC		 4584 /* Symbol is undefined and we want short ref. */
4585 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4586 fragP->fr_var += 2;
252b5132
RH		 4587 }
4588 else
151337e8
NC		 4589 {
4590 /* Symbol is still undefined. Make it LONG. */
4591 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4592 fragP->fr_var += 4;
252b5132 4593 }
252b5132 4594 break;
151337e8 4595 }
252b5132 4596
151337e8 4597 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 4598 {
151337e8
NC		 4599 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4600 && relaxable_symbol (fragP->fr_symbol))
252b5132 4601 {
151337e8
NC		 4602 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4603 }
4604 else if (flag_short_refs)
4605 {
4606 /* Symbol is undefined and we want short ref. */
4607 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4608 fragP->fr_var += 2;
4609 }
4610 else
4611 {
151337e8
NC		 4612 /* Symbol is still undefined. Make it LONG. */
4613 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4614 fragP->fr_var += 6;
252b5132
RH		 4615 }
4616 break;
151337e8 4617 }
252b5132 4618
151337e8 4619 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 4620 {
151337e8
NC		 4621 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4622 && relaxable_symbol (fragP->fr_symbol))
252b5132 4623 {
151337e8 4624 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 4625 }
4626 else
4627 {
151337e8
NC		 4628 /* Symbol is undefined and we don't have long branches. */
4629 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4630 fragP->fr_var += 2;
252b5132
RH		 4631 }
4632 break;
151337e8 4633 }
252b5132 4634
151337e8 4635 case TAB (FBRANCH, SZ_UNDEF):
252b5132 4636 {
151337e8
NC		 4637 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4638 && relaxable_symbol (fragP->fr_symbol))
4639 || flag_short_refs)
252b5132 4640 {
151337e8
NC		 4641 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4642 fragP->fr_var += 2;
252b5132
RH		 4643 }
4644 else
4645 {
151337e8
NC		 4646 fragP->fr_subtype = TAB (FBRANCH, LONG);
4647 fragP->fr_var += 4;
252b5132 4648 }
252b5132 4649 break;
151337e8 4650 }
252b5132 4651
151337e8
NC		 4652 case TAB (DBCCLBR, SZ_UNDEF):
4653 case TAB (DBCCABSJ, SZ_UNDEF):
252b5132 4654 {
151337e8
NC		 4655 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4656 && relaxable_symbol (fragP->fr_symbol)
4657 || flag_short_refs)
252b5132 4658 {
151337e8 4659 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132 4660 fragP->fr_var += 2;
252b5132
RH		 4661 }
4662 else
4663 {
151337e8
NC		 4664 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4665 fragP->fr_var += 10;
252b5132 4666 }
252b5132 4667 break;
151337e8 4668 }
252b5132 4669
151337e8 4670 case TAB (PCREL1632, SZ_UNDEF):
252b5132
RH		 4671 {
4672 if (((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4673 && relaxable_symbol (fragP->fr_symbol))
151337e8 4674 || flag_short_refs)
252b5132 4675 {
151337e8 4676 fragP->fr_subtype = TAB (PCREL1632, SHORT);
252b5132
RH		 4677 fragP->fr_var += 2;
4678 }
4679 else
4680 {
151337e8 4681 fragP->fr_subtype = TAB (PCREL1632, LONG);
252b5132
RH		 4682 fragP->fr_var += 6;
4683 }
4684 break;
151337e8
NC		 4685 }
4686
252b5132
RH		 4687 case TAB (PCINDEX, SZ_UNDEF):
4688 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 4689 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 4690 {
4691 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4692 }
4693 else
4694 {
4695 fragP->fr_subtype = TAB (PCINDEX, LONG);
4696 fragP->fr_var += 4;
4697 }
4698 break;
4699
151337e8
NC		 4700 case TAB (ABSTOPCREL, SZ_UNDEF):
4701 {
4702 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4703 && relaxable_symbol (fragP->fr_symbol)))
4704 {
4705 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
4706 fragP->fr_var += 2;
4707 }
4708 else
4709 {
4710 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
4711 fragP->fr_var += 4;
4712 }
4713 break;
4714 }
4715
252b5132
RH		 4716 default:
4717 break;
4718 }
4719
151337e8 4720 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 4721 switch (fragP->fr_subtype)
4722 {
151337e8
NC		 4723 case TAB (BRANCHBWL, BYTE):
4724 case TAB (BRABSJUNC, BYTE):
4725 case TAB (BRABSJCOND, BYTE):
4726 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4727 /* We can't do a short jump to the next instruction, so in that
4728 case we force word mode. At this point S_GET_VALUE should
4729 return the offset of the symbol within its frag. If the
4730 symbol is at the start of a frag, and it is the next frag
4731 with any data in it (usually this is just the next frag, but
4732 assembler listings may introduce empty frags), we must use
4733 word mode. */
4734 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4735 {
49309057 4736 fragS *stop;
252b5132
RH		 4737 fragS *l;
4738
49309057
ILT		 4739 stop = symbol_get_frag (fragP->fr_symbol);
4740 for (l = fragP->fr_next; l != stop; l = l->fr_next)
252b5132
RH		 4741 if (l->fr_fix + l->fr_var != 0)
4742 break;
49309057 4743 if (l == stop)
252b5132
RH		 4744 {
4745 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4746 fragP->fr_var += 2;
4747 }
4748 }
4749 break;
4750 default:
4751 break;
4752 }
4753 return fragP->fr_var + fragP->fr_fix - old_fix;
4754}
4755
4756#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4757/* the bit-field entries in the relocation_info struct plays hell
4758 with the byte-order problems of cross-assembly. So as a hack,
4759 I added this mach. dependent ri twiddler. Ugly, but it gets
4760 you there. -KWK */
4761/* on m68k: first 4 bytes are normal unsigned long, next three bytes
4762 are symbolnum, most sig. byte first. Last byte is broken up with
4763 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4764 nibble as nuthin. (on Sun 3 at least) */
4765/* Translate the internal relocation information into target-specific
92774660 4766 format. */
252b5132
RH		 4767#ifdef comment
4768void
4769md_ri_to_chars (the_bytes, ri)
4770 char *the_bytes;
4771 struct reloc_info_generic *ri;
4772{
4773 /* this is easy */
4774 md_number_to_chars (the_bytes, ri->r_address, 4);
4775 /* now the fun stuff */
4776 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4777 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4778 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4779 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4780 ((ri->r_extern << 4) & 0x10));
4781}
4782
4783#endif /* comment */
4784
4785#ifndef BFD_ASSEMBLER
4786void
4787tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4788 char *where;
4789 fixS *fixP;
4790 relax_addressT segment_address_in_file;
4791{
4792 /*
4793 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4794 * Out: GNU LD relocation length code: 0, 1, or 2.
4795 */
4796
4797 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4798 long r_symbolnum;
4799
4800 know (fixP->fx_addsy != NULL);
4801
4802 md_number_to_chars (where,
4803 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4804 4);
4805
4806 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4807 ? S_GET_TYPE (fixP->fx_addsy)
4808 : fixP->fx_addsy->sy_number);
4809
4810 where[4] = (r_symbolnum >> 16) & 0x0ff;
4811 where[5] = (r_symbolnum >> 8) & 0x0ff;
4812 where[6] = r_symbolnum & 0x0ff;
4813 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4814 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4815}
4816#endif
4817
4818#endif /* OBJ_AOUT or OBJ_BOUT */
4819
4820#ifndef WORKING_DOT_WORD
4821CONST int md_short_jump_size = 4;
4822CONST int md_long_jump_size = 6;
4823
4824void
4825md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4826 char *ptr;
4827 addressT from_addr, to_addr;
36823076
AS		 4828 fragS *frag ATTRIBUTE_UNUSED;
4829 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132
RH		 4830{
4831 valueT offset;
4832
4833 offset = to_addr - (from_addr + 2);
4834
4835 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4836 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4837}
4838
4839void
4840md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4841 char *ptr;
4842 addressT from_addr, to_addr;
4843 fragS *frag;
4844 symbolS *to_symbol;
4845{
4846 valueT offset;
4847
4848 if (!HAVE_LONG_BRANCH(current_architecture))
4849 {
4850 offset = to_addr - S_GET_VALUE (to_symbol);
4851 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4852 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4853 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4854 0, NO_RELOC);
4855 }
4856 else
4857 {
4858 offset = to_addr - (from_addr + 2);
4859 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4860 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4861 }
4862}
4863
4864#endif
4865
4866/* Different values of OK tell what its OK to return. Things that
4867 aren't OK are an error (what a shock, no?)
4868
4869 0: Everything is OK
4870 10: Absolute 1:8 only
4871 20: Absolute 0:7 only
4872 30: absolute 0:15 only
4873 40: Absolute 0:31 only
4874 50: absolute 0:127 only
4875 55: absolute -64:63 only
4876 60: absolute -128:127 only
4877 70: absolute 0:4095 only
4878 80: No bignums
4879
4880 */
4881
4882static int
4883get_num (exp, ok)
4884 struct m68k_exp *exp;
4885 int ok;
4886{
4887 if (exp->exp.X_op == O_absent)
4888 {
4889 /* Do the same thing the VAX asm does */
4890 op (exp) = O_constant;
4891 adds (exp) = 0;
4892 subs (exp) = 0;
4893 offs (exp) = 0;
4894 if (ok == 10)
4895 {
4896 as_warn (_("expression out of range: defaulting to 1"));
4897 offs (exp) = 1;
4898 }
4899 }
4900 else if (exp->exp.X_op == O_constant)
4901 {
4902 switch (ok)
4903 {
4904 case 10:
4905 if (offs (exp) < 1 || offs (exp) > 8)
4906 {
4907 as_warn (_("expression out of range: defaulting to 1"));
4908 offs (exp) = 1;
4909 }
4910 break;
4911 case 20:
4912 if (offs (exp) < 0 || offs (exp) > 7)
4913 goto outrange;
4914 break;
4915 case 30:
4916 if (offs (exp) < 0 || offs (exp) > 15)
4917 goto outrange;
4918 break;
4919 case 40:
4920 if (offs (exp) < 0 || offs (exp) > 32)
4921 goto outrange;
4922 break;
4923 case 50:
4924 if (offs (exp) < 0 || offs (exp) > 127)
4925 goto outrange;
4926 break;
4927 case 55:
4928 if (offs (exp) < -64 || offs (exp) > 63)
4929 goto outrange;
4930 break;
4931 case 60:
4932 if (offs (exp) < -128 || offs (exp) > 127)
4933 goto outrange;
4934 break;
4935 case 70:
4936 if (offs (exp) < 0 || offs (exp) > 4095)
4937 {
4938 outrange:
4939 as_warn (_("expression out of range: defaulting to 0"));
4940 offs (exp) = 0;
4941 }
4942 break;
4943 default:
4944 break;
4945 }
4946 }
4947 else if (exp->exp.X_op == O_big)
4948 {
4949 if (offs (exp) <= 0 /* flonum */
4950 && (ok == 80 /* no bignums */
4951 || (ok > 10 /* small-int ranges including 0 ok */
4952 /* If we have a flonum zero, a zero integer should
4953 do as well (e.g., in moveq). */
4954 && generic_floating_point_number.exponent == 0
4955 && generic_floating_point_number.low[0] == 0)))
4956 {
4957 /* HACK! Turn it into a long */
4958 LITTLENUM_TYPE words[6];
4959
4960 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4961 op (exp) = O_constant;
4962 adds (exp) = 0;
4963 subs (exp) = 0;
4964 offs (exp) = words[1] | (words[0] << 16);
4965 }
4966 else if (ok != 0)
4967 {
4968 op (exp) = O_constant;
4969 adds (exp) = 0;
4970 subs (exp) = 0;
4971 offs (exp) = (ok == 10) ? 1 : 0;
4972 as_warn (_("Can't deal with expression; defaulting to %ld"),
4973 offs (exp));
4974 }
4975 }
4976 else
4977 {
4978 if (ok >= 10 && ok <= 70)
4979 {
4980 op (exp) = O_constant;
4981 adds (exp) = 0;
4982 subs (exp) = 0;
4983 offs (exp) = (ok == 10) ? 1 : 0;
4984 as_warn (_("Can't deal with expression; defaulting to %ld"),
4985 offs (exp));
4986 }
4987 }
4988
4989 if (exp->size != SIZE_UNSPEC)
4990 {
4991 switch (exp->size)
4992 {
4993 case SIZE_UNSPEC:
4994 case SIZE_LONG:
4995 break;
4996 case SIZE_BYTE:
4997 if (!isbyte (offs (exp)))
4998 as_warn (_("expression doesn't fit in BYTE"));
4999 break;
5000 case SIZE_WORD:
5001 if (!isword (offs (exp)))
5002 as_warn (_("expression doesn't fit in WORD"));
5003 break;
5004 }
5005 }
5006
5007 return offs (exp);
5008}
5009
5010/* These are the back-ends for the various machine dependent pseudo-ops. */
5011
5012static void
5013s_data1 (ignore)
36823076 5014 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5015{
5016 subseg_set (data_section, 1);
5017 demand_empty_rest_of_line ();
5018}
5019
5020static void
5021s_data2 (ignore)
36823076 5022 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5023{
5024 subseg_set (data_section, 2);
5025 demand_empty_rest_of_line ();
5026}
5027
5028static void
5029s_bss (ignore)
36823076 5030 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5031{
5032 /* We don't support putting frags in the BSS segment, we fake it
5033 by marking in_bss, then looking at s_skip for clues. */
5034
5035 subseg_set (bss_section, 0);
5036 demand_empty_rest_of_line ();
5037}
5038
5039static void
5040s_even (ignore)
36823076 5041 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5042{
5043 register int temp;
5044 register long temp_fill;
5045
5046 temp = 1; /* JF should be 2? */
5047 temp_fill = get_absolute_expression ();
92774660 5048 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5049 frag_align (temp, (int) temp_fill, 0);
5050 demand_empty_rest_of_line ();
5051 record_alignment (now_seg, temp);
5052}
5053
5054static void
5055s_proc (ignore)
36823076 5056 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5057{
5058 demand_empty_rest_of_line ();
5059}
5060\f
5061/* Pseudo-ops handled for MRI compatibility. */
5062
5063/* This function returns non-zero if the argument is a conditional
5064 pseudo-op. This is called when checking whether a pending
5065 alignment is needed. */
5066
5067int
5068m68k_conditional_pseudoop (pop)
5069 pseudo_typeS *pop;
5070{
5071 return (pop->poc_handler == s_mri_if
5072 || pop->poc_handler == s_mri_else);
5073}
5074
5075/* Handle an MRI style chip specification. */
5076
5077static void
5078mri_chip ()
5079{
5080 char *s;
5081 char c;
5082 int i;
5083
5084 s = input_line_pointer;
5085 /* We can't use get_symbol_end since the processor names are not proper
5086 symbols. */
5087 while (is_part_of_name (c = *input_line_pointer++))
5088 ;
5089 *--input_line_pointer = 0;
5090 for (i = 0; i < n_archs; i++)
5091 if (strcasecmp (s, archs[i].name) == 0)
5092 break;
5093 if (i >= n_archs)
5094 {
5095 as_bad (_("%s: unrecognized processor name"), s);
5096 *input_line_pointer = c;
5097 ignore_rest_of_line ();
5098 return;
5099 }
5100 *input_line_pointer = c;
5101
5102 if (*input_line_pointer == '/')
5103 current_architecture = 0;
5104 else
5105 current_architecture &= m68881 | m68851;
5106 current_architecture |= archs[i].arch;
5107
5108 while (*input_line_pointer == '/')
5109 {
5110 ++input_line_pointer;
5111 s = input_line_pointer;
5112 /* We can't use get_symbol_end since the processor names are not
5113 proper symbols. */
5114 while (is_part_of_name (c = *input_line_pointer++))
5115 ;
5116 *--input_line_pointer = 0;
5117 if (strcmp (s, "68881") == 0)
5118 current_architecture |= m68881;
5119 else if (strcmp (s, "68851") == 0)
5120 current_architecture |= m68851;
5121 *input_line_pointer = c;
5122 }
5123
5124 /* Update info about available control registers. */
5125 select_control_regs ();
5126}
5127
5128/* The MRI CHIP pseudo-op. */
5129
5130static void
5131s_chip (ignore)
36823076 5132 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5133{
5134 char *stop = NULL;
5135 char stopc;
5136
5137 if (flag_mri)
5138 stop = mri_comment_field (&stopc);
5139 mri_chip ();
5140 if (flag_mri)
5141 mri_comment_end (stop, stopc);
5142 demand_empty_rest_of_line ();
5143}
5144
5145/* The MRI FOPT pseudo-op. */
5146
5147static void
5148s_fopt (ignore)
36823076 5149 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5150{
5151 SKIP_WHITESPACE ();
5152
5153 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5154 {
5155 int temp;
5156
5157 input_line_pointer += 3;
5158 temp = get_absolute_expression ();
5159 if (temp < 0 || temp > 7)
5160 as_bad (_("bad coprocessor id"));
5161 else
5162 m68k_float_copnum = COP0 + temp;
5163 }
5164 else
5165 {
5166 as_bad (_("unrecognized fopt option"));
5167 ignore_rest_of_line ();
5168 return;
5169 }
5170
5171 demand_empty_rest_of_line ();
5172}
5173
5174/* The structure used to handle the MRI OPT pseudo-op. */
5175
5176struct opt_action
5177{
5178 /* The name of the option. */
5179 const char *name;
5180
5181 /* If this is not NULL, just call this function. The first argument
5182 is the ARG field of this structure, the second argument is
5183 whether the option was negated. */
5184 void (*pfn) PARAMS ((int arg, int on));
5185
5186 /* If this is not NULL, and the PFN field is NULL, set the variable
5187 this points to. Set it to the ARG field if the option was not
5188 negated, and the NOTARG field otherwise. */
5189 int *pvar;
5190
5191 /* The value to pass to PFN or to assign to *PVAR. */
5192 int arg;
5193
5194 /* The value to assign to *PVAR if the option is negated. If PFN is
5195 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5196 the option may not be negated. */
5197 int notarg;
5198};
5199
5200/* The table used to handle the MRI OPT pseudo-op. */
5201
5202static void skip_to_comma PARAMS ((int, int));
5203static void opt_nest PARAMS ((int, int));
5204static void opt_chip PARAMS ((int, int));
5205static void opt_list PARAMS ((int, int));
5206static void opt_list_symbols PARAMS ((int, int));
5207
5208static const struct opt_action opt_table[] =
5209{
5210 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5211
5212 /* We do relaxing, so there is little use for these options. */
5213 { "b", 0, 0, 0, 0 },
5214 { "brs", 0, 0, 0, 0 },
5215 { "brb", 0, 0, 0, 0 },
5216 { "brl", 0, 0, 0, 0 },
5217 { "brw", 0, 0, 0, 0 },
5218
5219 { "c", 0, 0, 0, 0 },
5220 { "cex", 0, 0, 0, 0 },
5221 { "case", 0, &symbols_case_sensitive, 1, 0 },
5222 { "cl", 0, 0, 0, 0 },
5223 { "cre", 0, 0, 0, 0 },
5224 { "d", 0, &flag_keep_locals, 1, 0 },
5225 { "e", 0, 0, 0, 0 },
5226 { "f", 0, &flag_short_refs, 1, 0 },
5227 { "frs", 0, &flag_short_refs, 1, 0 },
5228 { "frl", 0, &flag_short_refs, 0, 1 },
5229 { "g", 0, 0, 0, 0 },
5230 { "i", 0, 0, 0, 0 },
5231 { "m", 0, 0, 0, 0 },
5232 { "mex", 0, 0, 0, 0 },
5233 { "mc", 0, 0, 0, 0 },
5234 { "md", 0, 0, 0, 0 },
5235 { "nest", opt_nest, 0, 0, 0 },
5236 { "next", skip_to_comma, 0, 0, 0 },
5237 { "o", 0, 0, 0, 0 },
5238 { "old", 0, 0, 0, 0 },
5239 { "op", skip_to_comma, 0, 0, 0 },
5240 { "pco", 0, 0, 0, 0 },
5241 { "p", opt_chip, 0, 0, 0 },
5242 { "pcr", 0, 0, 0, 0 },
5243 { "pcs", 0, 0, 0, 0 },
5244 { "r", 0, 0, 0, 0 },
5245 { "quick", 0, &m68k_quick, 1, 0 },
5246 { "rel32", 0, &m68k_rel32, 1, 0 },
5247 { "s", opt_list, 0, 0, 0 },
5248 { "t", opt_list_symbols, 0, 0, 0 },
5249 { "w", 0, &flag_no_warnings, 0, 1 },
5250 { "x", 0, 0, 0, 0 }
5251};
5252
8fce3f5e 5253#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5254
5255/* The MRI OPT pseudo-op. */
5256
5257static void
5258s_opt (ignore)
36823076 5259 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5260{
5261 do
5262 {
5263 int t;
5264 char *s;
5265 char c;
5266 int i;
5267 const struct opt_action *o;
5268
5269 SKIP_WHITESPACE ();
5270
5271 t = 1;
5272 if (*input_line_pointer == '-')
5273 {
5274 ++input_line_pointer;
5275 t = 0;
5276 }
5277 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5278 {
5279 input_line_pointer += 2;
5280 t = 0;
5281 }
5282
5283 s = input_line_pointer;
5284 c = get_symbol_end ();
5285
5286 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5287 {
5288 if (strcasecmp (s, o->name) == 0)
5289 {
5290 if (o->pfn)
5291 {
5292 /* Restore input_line_pointer now in case the option
5293 takes arguments. */
5294 *input_line_pointer = c;
5295 (*o->pfn) (o->arg, t);
5296 }
5297 else if (o->pvar != NULL)
5298 {
5299 if (! t && o->arg == o->notarg)
5300 as_bad (_("option `%s' may not be negated"), s);
5301 *input_line_pointer = c;
5302 *o->pvar = t ? o->arg : o->notarg;
5303 }
5304 else
5305 *input_line_pointer = c;
5306 break;
5307 }
5308 }
5309 if (i >= OPTCOUNT)
5310 {
5311 as_bad (_("option `%s' not recognized"), s);
5312 *input_line_pointer = c;
5313 }
5314 }
5315 while (*input_line_pointer++ == ',');
5316
5317 /* Move back to terminating character. */
5318 --input_line_pointer;
5319 demand_empty_rest_of_line ();
5320}
5321
5322/* Skip ahead to a comma. This is used for OPT options which we do
5323 not suppor tand which take arguments. */
5324
5325static void
5326skip_to_comma (arg, on)
36823076
AS		 5327 int arg ATTRIBUTE_UNUSED;
5328 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5329{
5330 while (*input_line_pointer != ','
5331 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5332 ++input_line_pointer;
5333}
5334
5335/* Handle the OPT NEST=depth option. */
5336
5337static void
5338opt_nest (arg, on)
36823076
AS		 5339 int arg ATTRIBUTE_UNUSED;
5340 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5341{
5342 if (*input_line_pointer != '=')
5343 {
5344 as_bad (_("bad format of OPT NEST=depth"));
5345 return;
5346 }
5347
5348 ++input_line_pointer;
5349 max_macro_nest = get_absolute_expression ();
5350}
5351
5352/* Handle the OPT P=chip option. */
5353
5354static void
5355opt_chip (arg, on)
36823076
AS		 5356 int arg ATTRIBUTE_UNUSED;
5357 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5358{
5359 if (*input_line_pointer != '=')
5360 {
5361 /* This is just OPT P, which we do not support. */
5362 return;
5363 }
5364
5365 ++input_line_pointer;
5366 mri_chip ();
5367}
5368
5369/* Handle the OPT S option. */
5370
5371static void
5372opt_list (arg, on)
36823076 5373 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5374 int on;
5375{
5376 listing_list (on);
5377}
5378
5379/* Handle the OPT T option. */
5380
5381static void
5382opt_list_symbols (arg, on)
36823076 5383 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5384 int on;
5385{
5386 if (on)
5387 listing |= LISTING_SYMBOLS;
5388 else
5389 listing &=~ LISTING_SYMBOLS;
5390}
5391
5392/* Handle the MRI REG pseudo-op. */
5393
5394static void
5395s_reg (ignore)
36823076 5396 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5397{
5398 char *s;
5399 int c;
5400 struct m68k_op rop;
5401 int mask;
5402 char *stop = NULL;
5403 char stopc;
5404
5405 if (line_label == NULL)
5406 {
5407 as_bad (_("missing label"));
5408 ignore_rest_of_line ();
5409 return;
5410 }
5411
5412 if (flag_mri)
5413 stop = mri_comment_field (&stopc);
5414
5415 SKIP_WHITESPACE ();
5416
5417 s = input_line_pointer;
5418 while (isalnum ((unsigned char) *input_line_pointer)
5419#ifdef REGISTER_PREFIX
5420 || *input_line_pointer == REGISTER_PREFIX
5421#endif
5422 || *input_line_pointer == '/'
5423 || *input_line_pointer == '-')
5424 ++input_line_pointer;
5425 c = *input_line_pointer;
5426 *input_line_pointer = '\0';
5427
5428 if (m68k_ip_op (s, &rop) != 0)
5429 {
5430 if (rop.error == NULL)
5431 as_bad (_("bad register list"));
5432 else
5433 as_bad (_("bad register list: %s"), rop.error);
5434 *input_line_pointer = c;
5435 ignore_rest_of_line ();
5436 return;
5437 }
5438
5439 *input_line_pointer = c;
5440
5441 if (rop.mode == REGLST)
5442 mask = rop.mask;
5443 else if (rop.mode == DREG)
5444 mask = 1 << (rop.reg - DATA0);
5445 else if (rop.mode == AREG)
5446 mask = 1 << (rop.reg - ADDR0 + 8);
5447 else if (rop.mode == FPREG)
5448 mask = 1 << (rop.reg - FP0 + 16);
5449 else if (rop.mode == CONTROL
5450 && rop.reg == FPI)
5451 mask = 1 << 24;
5452 else if (rop.mode == CONTROL
5453 && rop.reg == FPS)
5454 mask = 1 << 25;
5455 else if (rop.mode == CONTROL
5456 && rop.reg == FPC)
5457 mask = 1 << 26;
5458 else
5459 {
5460 as_bad (_("bad register list"));
5461 ignore_rest_of_line ();
5462 return;
5463 }
5464
5465 S_SET_SEGMENT (line_label, reg_section);
5466 S_SET_VALUE (line_label, ~mask);
49309057 5467 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5468
5469 if (flag_mri)
5470 mri_comment_end (stop, stopc);
5471
5472 demand_empty_rest_of_line ();
5473}
5474
5475/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5476
5477struct save_opts
5478{
5479 struct save_opts *next;
5480 int abspcadd;
5481 int symbols_case_sensitive;
5482 int keep_locals;
5483 int short_refs;
5484 int architecture;
5485 int quick;
5486 int rel32;
5487 int listing;
5488 int no_warnings;
5489 /* FIXME: We don't save OPT S. */
5490};
5491
5492/* This variable holds the stack of saved options. */
5493
5494static struct save_opts *save_stack;
5495
5496/* The MRI SAVE pseudo-op. */
5497
5498static void
5499s_save (ignore)
36823076 5500 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5501{
5502 struct save_opts *s;
5503
5504 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5505 s->abspcadd = m68k_abspcadd;
5506 s->symbols_case_sensitive = symbols_case_sensitive;
5507 s->keep_locals = flag_keep_locals;
5508 s->short_refs = flag_short_refs;
5509 s->architecture = current_architecture;
5510 s->quick = m68k_quick;
5511 s->rel32 = m68k_rel32;
5512 s->listing = listing;
5513 s->no_warnings = flag_no_warnings;
5514
5515 s->next = save_stack;
5516 save_stack = s;
5517
5518 demand_empty_rest_of_line ();
5519}
5520
5521/* The MRI RESTORE pseudo-op. */
5522
5523static void
5524s_restore (ignore)
36823076 5525 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5526{
5527 struct save_opts *s;
5528
5529 if (save_stack == NULL)
5530 {
5531 as_bad (_("restore without save"));
5532 ignore_rest_of_line ();
5533 return;
5534 }
5535
5536 s = save_stack;
5537 save_stack = s->next;
5538
5539 m68k_abspcadd = s->abspcadd;
5540 symbols_case_sensitive = s->symbols_case_sensitive;
5541 flag_keep_locals = s->keep_locals;
5542 flag_short_refs = s->short_refs;
5543 current_architecture = s->architecture;
5544 m68k_quick = s->quick;
5545 m68k_rel32 = s->rel32;
5546 listing = s->listing;
5547 flag_no_warnings = s->no_warnings;
5548
5549 free (s);
5550
5551 demand_empty_rest_of_line ();
5552}
5553
5554/* Types of MRI structured control directives. */
5555
5556enum mri_control_type
5557{
5558 mri_for,
5559 mri_if,
5560 mri_repeat,
5561 mri_while
5562};
5563
5564/* This structure is used to stack the MRI structured control
5565 directives. */
5566
5567struct mri_control_info
5568{
5569 /* The directive within which this one is enclosed. */
5570 struct mri_control_info *outer;
5571
5572 /* The type of directive. */
5573 enum mri_control_type type;
5574
5575 /* Whether an ELSE has been in an IF. */
5576 int else_seen;
5577
5578 /* The add or sub statement at the end of a FOR. */
5579 char *incr;
5580
5581 /* The label of the top of a FOR or REPEAT loop. */
5582 char *top;
5583
5584 /* The label to jump to for the next iteration, or the else
5585 expression of a conditional. */
5586 char *next;
5587
5588 /* The label to jump to to break out of the loop, or the label past
5589 the end of a conditional. */
5590 char *bottom;
5591};
5592
5593/* The stack of MRI structured control directives. */
5594
5595static struct mri_control_info *mri_control_stack;
5596
5597/* The current MRI structured control directive index number, used to
5598 generate label names. */
5599
5600static int mri_control_index;
5601
5602/* Some function prototypes. */
5603
5604static void mri_assemble PARAMS ((char *));
5605static char *mri_control_label PARAMS ((void));
5606static struct mri_control_info *push_mri_control
5607 PARAMS ((enum mri_control_type));
5608static void pop_mri_control PARAMS ((void));
5609static int parse_mri_condition PARAMS ((int *));
5610static int parse_mri_control_operand
5611 PARAMS ((int *, char **, char **, char **, char **));
5612static int swap_mri_condition PARAMS ((int));
5613static int reverse_mri_condition PARAMS ((int));
5614static void build_mri_control_operand
5615 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5616 const char *, int));
5617static void parse_mri_control_expression
5618 PARAMS ((char *, int, const char *, const char *, int));
5619
5620/* Assemble an instruction for an MRI structured control directive. */
5621
5622static void
5623mri_assemble (str)
5624 char *str;
5625{
5626 char *s;
5627
5628 /* md_assemble expects the opcode to be in lower case. */
5629 for (s = str; *s != ' ' && *s != '\0'; s++)
5630 {
5631 if (isupper ((unsigned char) *s))
5632 *s = tolower ((unsigned char) *s);
5633 }
5634
5635 md_assemble (str);
5636}
5637
5638/* Generate a new MRI label structured control directive label name. */
5639
5640static char *
5641mri_control_label ()
5642{
5643 char *n;
5644
5645 n = (char *) xmalloc (20);
5646 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5647 ++mri_control_index;
5648 return n;
5649}
5650
5651/* Create a new MRI structured control directive. */
5652
5653static struct mri_control_info *
5654push_mri_control (type)
5655 enum mri_control_type type;
5656{
5657 struct mri_control_info *n;
5658
5659 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5660
5661 n->type = type;
5662 n->else_seen = 0;
5663 if (type == mri_if || type == mri_while)
5664 n->top = NULL;
5665 else
5666 n->top = mri_control_label ();
5667 n->next = mri_control_label ();
5668 n->bottom = mri_control_label ();
5669
5670 n->outer = mri_control_stack;
5671 mri_control_stack = n;
5672
5673 return n;
5674}
5675
5676/* Pop off the stack of MRI structured control directives. */
5677
5678static void
5679pop_mri_control ()
5680{
5681 struct mri_control_info *n;
5682
5683 n = mri_control_stack;
5684 mri_control_stack = n->outer;
5685 if (n->top != NULL)
5686 free (n->top);
5687 free (n->next);
5688 free (n->bottom);
5689 free (n);
5690}
5691
5692/* Recognize a condition code in an MRI structured control expression. */
5693
5694static int
5695parse_mri_condition (pcc)
5696 int *pcc;
5697{
5698 char c1, c2;
5699
5700 know (*input_line_pointer == '<');
5701
5702 ++input_line_pointer;
5703 c1 = *input_line_pointer++;
5704 c2 = *input_line_pointer++;
5705
5706 if (*input_line_pointer != '>')
5707 {
5708 as_bad (_("syntax error in structured control directive"));
5709 return 0;
5710 }
5711
5712 ++input_line_pointer;
5713 SKIP_WHITESPACE ();
5714
5715 if (isupper (c1))
5716 c1 = tolower (c1);
5717 if (isupper (c2))
5718 c2 = tolower (c2);
5719
5720 *pcc = (c1 << 8) | c2;
5721
5722 return 1;
5723}
5724
5725/* Parse a single operand in an MRI structured control expression. */
5726
5727static int
5728parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5729 int *pcc;
5730 char **leftstart;
5731 char **leftstop;
5732 char **rightstart;
5733 char **rightstop;
5734{
5735 char *s;
5736
5737 SKIP_WHITESPACE ();
5738
5739 *pcc = -1;
5740 *leftstart = NULL;
5741 *leftstop = NULL;
5742 *rightstart = NULL;
5743 *rightstop = NULL;
5744
5745 if (*input_line_pointer == '<')
5746 {
5747 /* It's just a condition code. */
5748 return parse_mri_condition (pcc);
5749 }
5750
5751 /* Look ahead for the condition code. */
5752 for (s = input_line_pointer; *s != '\0'; ++s)
5753 {
5754 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5755 break;
5756 }
5757 if (*s == '\0')
5758 {
5759 as_bad (_("missing condition code in structured control directive"));
5760 return 0;
5761 }
5762
5763 *leftstart = input_line_pointer;
5764 *leftstop = s;
5765 if (*leftstop > *leftstart
5766 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5767 --*leftstop;
5768
5769 input_line_pointer = s;
5770 if (! parse_mri_condition (pcc))
5771 return 0;
5772
5773 /* Look ahead for AND or OR or end of line. */
5774 for (s = input_line_pointer; *s != '\0'; ++s)
5775 {
5776 if ((strncasecmp (s, "AND", 3) == 0
5777 && (s[3] == '.' || ! is_part_of_name (s[3])))
5778 || (strncasecmp (s, "OR", 2) == 0
5779 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5780 break;
5781 }
5782
5783 *rightstart = input_line_pointer;
5784 *rightstop = s;
5785 if (*rightstop > *rightstart
5786 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5787 --*rightstop;
5788
5789 input_line_pointer = s;
5790
5791 return 1;
5792}
5793
5794#define MCC(b1, b2) (((b1) << 8) | (b2))
5795
5796/* Swap the sense of a condition. This changes the condition so that
5797 it generates the same result when the operands are swapped. */
5798
5799static int
5800swap_mri_condition (cc)
5801 int cc;
5802{
5803 switch (cc)
5804 {
5805 case MCC ('h', 'i'): return MCC ('c', 's');
5806 case MCC ('l', 's'): return MCC ('c', 'c');
5807 case MCC ('c', 'c'): return MCC ('l', 's');
5808 case MCC ('c', 's'): return MCC ('h', 'i');
5809 case MCC ('p', 'l'): return MCC ('m', 'i');
5810 case MCC ('m', 'i'): return MCC ('p', 'l');
5811 case MCC ('g', 'e'): return MCC ('l', 'e');
5812 case MCC ('l', 't'): return MCC ('g', 't');
5813 case MCC ('g', 't'): return MCC ('l', 't');
5814 case MCC ('l', 'e'): return MCC ('g', 'e');
5815 }
5816 return cc;
5817}
5818
5819/* Reverse the sense of a condition. */
5820
5821static int
5822reverse_mri_condition (cc)
5823 int cc;
5824{
5825 switch (cc)
5826 {
5827 case MCC ('h', 'i'): return MCC ('l', 's');
5828 case MCC ('l', 's'): return MCC ('h', 'i');
5829 case MCC ('c', 'c'): return MCC ('c', 's');
5830 case MCC ('c', 's'): return MCC ('c', 'c');
5831 case MCC ('n', 'e'): return MCC ('e', 'q');
5832 case MCC ('e', 'q'): return MCC ('n', 'e');
5833 case MCC ('v', 'c'): return MCC ('v', 's');
5834 case MCC ('v', 's'): return MCC ('v', 'c');
5835 case MCC ('p', 'l'): return MCC ('m', 'i');
5836 case MCC ('m', 'i'): return MCC ('p', 'l');
5837 case MCC ('g', 'e'): return MCC ('l', 't');
5838 case MCC ('l', 't'): return MCC ('g', 'e');
5839 case MCC ('g', 't'): return MCC ('l', 'e');
5840 case MCC ('l', 'e'): return MCC ('g', 't');
5841 }
5842 return cc;
5843}
5844
5845/* Build an MRI structured control expression. This generates test
5846 and branch instructions. It goes to TRUELAB if the condition is
5847 true, and to FALSELAB if the condition is false. Exactly one of
5848 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5849 is the size qualifier for the expression. EXTENT is the size to
5850 use for the branch. */
5851
5852static void
5853build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5854 rightstop, truelab, falselab, extent)
5855 int qual;
5856 int cc;
5857 char *leftstart;
5858 char *leftstop;
5859 char *rightstart;
5860 char *rightstop;
5861 const char *truelab;
5862 const char *falselab;
5863 int extent;
5864{
5865 char *buf;
5866 char *s;
5867
5868 if (leftstart != NULL)
5869 {
5870 struct m68k_op leftop, rightop;
5871 char c;
5872
5873 /* Swap the compare operands, if necessary, to produce a legal
5874 m68k compare instruction. Comparing a register operand with
5875 a non-register operand requires the register to be on the
5876 right (cmp, cmpa). Comparing an immediate value with
5877 anything requires the immediate value to be on the left
5878 (cmpi). */
5879
5880 c = *leftstop;
5881 *leftstop = '\0';
5882 (void) m68k_ip_op (leftstart, &leftop);
5883 *leftstop = c;
5884
5885 c = *rightstop;
5886 *rightstop = '\0';
5887 (void) m68k_ip_op (rightstart, &rightop);
5888 *rightstop = c;
5889
5890 if (rightop.mode == IMMED
5891 || ((leftop.mode == DREG || leftop.mode == AREG)
5892 && (rightop.mode != DREG && rightop.mode != AREG)))
5893 {
5894 char *temp;
5895
5896 cc = swap_mri_condition (cc);
5897 temp = leftstart;
5898 leftstart = rightstart;
5899 rightstart = temp;
5900 temp = leftstop;
5901 leftstop = rightstop;
5902 rightstop = temp;
5903 }
5904 }
5905
5906 if (truelab == NULL)
5907 {
5908 cc = reverse_mri_condition (cc);
5909 truelab = falselab;
5910 }
92774660 5911
252b5132
RH		 5912 if (leftstart != NULL)
5913 {
5914 buf = (char *) xmalloc (20
5915 + (leftstop - leftstart)
5916 + (rightstop - rightstart));
5917 s = buf;
5918 *s++ = 'c';
5919 *s++ = 'm';
5920 *s++ = 'p';
5921 if (qual != '\0')
5922 *s++ = qual;
5923 *s++ = ' ';
5924 memcpy (s, leftstart, leftstop - leftstart);
5925 s += leftstop - leftstart;
5926 *s++ = ',';
5927 memcpy (s, rightstart, rightstop - rightstart);
5928 s += rightstop - rightstart;
5929 *s = '\0';
5930 mri_assemble (buf);
5931 free (buf);
5932 }
92774660 5933
252b5132
RH		 5934 buf = (char *) xmalloc (20 + strlen (truelab));
5935 s = buf;
5936 *s++ = 'b';
5937 *s++ = cc >> 8;
5938 *s++ = cc & 0xff;
5939 if (extent != '\0')
5940 *s++ = extent;
5941 *s++ = ' ';
5942 strcpy (s, truelab);
5943 mri_assemble (buf);
5944 free (buf);
5945}
5946
5947/* Parse an MRI structured control expression. This generates test
5948 and branch instructions. STOP is where the expression ends. It
5949 goes to TRUELAB if the condition is true, and to FALSELAB if the
5950 condition is false. Exactly one of TRUELAB and FALSELAB will be
5951 NULL, meaning to fall through. QUAL is the size qualifier for the
5952 expression. EXTENT is the size to use for the branch. */
5953
5954static void
5955parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5956 char *stop;
5957 int qual;
5958 const char *truelab;
5959 const char *falselab;
5960 int extent;
5961{
5962 int c;
5963 int cc;
5964 char *leftstart;
5965 char *leftstop;
5966 char *rightstart;
5967 char *rightstop;
5968
5969 c = *stop;
5970 *stop = '\0';
5971
5972 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5973 &rightstart, &rightstop))
5974 {
5975 *stop = c;
5976 return;
5977 }
5978
5979 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5980 {
5981 const char *flab;
5982
5983 if (falselab != NULL)
5984 flab = falselab;
5985 else
5986 flab = mri_control_label ();
5987
5988 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5989 rightstop, (const char *) NULL, flab, extent);
5990
5991 input_line_pointer += 3;
5992 if (*input_line_pointer != '.'
5993 || input_line_pointer[1] == '\0')
5994 qual = '\0';
5995 else
5996 {
5997 qual = input_line_pointer[1];
5998 input_line_pointer += 2;
5999 }
6000
6001 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6002 &rightstart, &rightstop))
6003 {
6004 *stop = c;
6005 return;
6006 }
6007
6008 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6009 rightstop, truelab, falselab, extent);
6010
6011 if (falselab == NULL)
6012 colon (flab);
6013 }
6014 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6015 {
6016 const char *tlab;
6017
6018 if (truelab != NULL)
6019 tlab = truelab;
6020 else
6021 tlab = mri_control_label ();
6022
6023 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6024 rightstop, tlab, (const char *) NULL, extent);
6025
6026 input_line_pointer += 2;
6027 if (*input_line_pointer != '.'
6028 || input_line_pointer[1] == '\0')
6029 qual = '\0';
6030 else
6031 {
6032 qual = input_line_pointer[1];
6033 input_line_pointer += 2;
6034 }
6035
6036 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6037 &rightstart, &rightstop))
6038 {
6039 *stop = c;
6040 return;
6041 }
6042
6043 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6044 rightstop, truelab, falselab, extent);
6045
6046 if (truelab == NULL)
6047 colon (tlab);
6048 }
6049 else
6050 {
6051 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6052 rightstop, truelab, falselab, extent);
6053 }
6054
6055 *stop = c;
6056 if (input_line_pointer != stop)
6057 as_bad (_("syntax error in structured control directive"));
6058}
6059
6060/* Handle the MRI IF pseudo-op. This may be a structured control
6061 directive, or it may be a regular assembler conditional, depending
6062 on its operands. */
6063
6064static void
6065s_mri_if (qual)
6066 int qual;
6067{
6068 char *s;
6069 int c;
6070 struct mri_control_info *n;
6071
6072 /* A structured control directive must end with THEN with an
6073 optional qualifier. */
6074 s = input_line_pointer;
6075 while (! is_end_of_line[(unsigned char) *s]
6076 && (! flag_mri || *s != '*'))
6077 ++s;
6078 --s;
6079 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6080 --s;
6081
6082 if (s - input_line_pointer > 1
6083 && s[-1] == '.')
6084 s -= 2;
6085
6086 if (s - input_line_pointer < 3
6087 || strncasecmp (s - 3, "THEN", 4) != 0)
6088 {
6089 if (qual != '\0')
6090 {
6091 as_bad (_("missing then"));
6092 ignore_rest_of_line ();
6093 return;
6094 }
6095
6096 /* It's a conditional. */
6097 s_if (O_ne);
6098 return;
6099 }
6100
6101 /* Since this might be a conditional if, this pseudo-op will be
6102 called even if we are supported to be ignoring input. Double
6103 check now. Clobber *input_line_pointer so that ignore_input
6104 thinks that this is not a special pseudo-op. */
6105 c = *input_line_pointer;
6106 *input_line_pointer = 0;
6107 if (ignore_input ())
6108 {
6109 *input_line_pointer = c;
6110 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6111 ++input_line_pointer;
6112 demand_empty_rest_of_line ();
6113 return;
6114 }
6115 *input_line_pointer = c;
6116
6117 n = push_mri_control (mri_if);
6118
6119 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6120 n->next, s[1] == '.' ? s[2] : '\0');
6121
6122 if (s[1] == '.')
6123 input_line_pointer = s + 3;
6124 else
6125 input_line_pointer = s + 1;
6126
6127 if (flag_mri)
6128 {
6129 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6130 ++input_line_pointer;
6131 }
6132
6133 demand_empty_rest_of_line ();
6134}
6135
6136/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6137 structured IF, associate the ELSE with the IF. Otherwise, assume
6138 it is a conditional else. */
6139
6140static void
6141s_mri_else (qual)
6142 int qual;
6143{
6144 int c;
6145 char *buf;
6146 char q[2];
6147
6148 if (qual == '\0'
6149 && (mri_control_stack == NULL
6150 || mri_control_stack->type != mri_if
6151 || mri_control_stack->else_seen))
6152 {
6153 s_else (0);
6154 return;
6155 }
6156
6157 c = *input_line_pointer;
6158 *input_line_pointer = 0;
6159 if (ignore_input ())
6160 {
6161 *input_line_pointer = c;
6162 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6163 ++input_line_pointer;
6164 demand_empty_rest_of_line ();
6165 return;
6166 }
6167 *input_line_pointer = c;
6168
6169 if (mri_control_stack == NULL
6170 || mri_control_stack->type != mri_if
6171 || mri_control_stack->else_seen)
6172 {
6173 as_bad (_("else without matching if"));
6174 ignore_rest_of_line ();
6175 return;
6176 }
6177
6178 mri_control_stack->else_seen = 1;
6179
6180 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6181 q[0] = qual;
6182 q[1] = '\0';
6183 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6184 mri_assemble (buf);
6185 free (buf);
6186
6187 colon (mri_control_stack->next);
6188
6189 if (flag_mri)
6190 {
6191 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6192 ++input_line_pointer;
6193 }
6194
6195 demand_empty_rest_of_line ();
6196}
6197
6198/* Handle the MRI ENDI pseudo-op. */
6199
6200static void
6201s_mri_endi (ignore)
36823076 6202 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6203{
6204 if (mri_control_stack == NULL
6205 || mri_control_stack->type != mri_if)
6206 {
6207 as_bad (_("endi without matching if"));
6208 ignore_rest_of_line ();
6209 return;
6210 }
6211
6212 /* ignore_input will not return true for ENDI, so we don't need to
6213 worry about checking it again here. */
6214
6215 if (! mri_control_stack->else_seen)
6216 colon (mri_control_stack->next);
6217 colon (mri_control_stack->bottom);
6218
6219 pop_mri_control ();
6220
6221 if (flag_mri)
6222 {
6223 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6224 ++input_line_pointer;
6225 }
6226
6227 demand_empty_rest_of_line ();
6228}
6229
6230/* Handle the MRI BREAK pseudo-op. */
6231
6232static void
6233s_mri_break (extent)
6234 int extent;
6235{
6236 struct mri_control_info *n;
6237 char *buf;
6238 char ex[2];
6239
6240 n = mri_control_stack;
6241 while (n != NULL
6242 && n->type != mri_for
6243 && n->type != mri_repeat
6244 && n->type != mri_while)
6245 n = n->outer;
6246 if (n == NULL)
6247 {
6248 as_bad (_("break outside of structured loop"));
6249 ignore_rest_of_line ();
6250 return;
6251 }
6252
6253 buf = (char *) xmalloc (20 + strlen (n->bottom));
6254 ex[0] = extent;
6255 ex[1] = '\0';
6256 sprintf (buf, "bra%s %s", ex, n->bottom);
6257 mri_assemble (buf);
6258 free (buf);
6259
6260 if (flag_mri)
6261 {
6262 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6263 ++input_line_pointer;
6264 }
6265
6266 demand_empty_rest_of_line ();
6267}
6268
6269/* Handle the MRI NEXT pseudo-op. */
6270
6271static void
6272s_mri_next (extent)
6273 int extent;
6274{
6275 struct mri_control_info *n;
6276 char *buf;
6277 char ex[2];
6278
6279 n = mri_control_stack;
6280 while (n != NULL
6281 && n->type != mri_for
6282 && n->type != mri_repeat
6283 && n->type != mri_while)
6284 n = n->outer;
6285 if (n == NULL)
6286 {
6287 as_bad (_("next outside of structured loop"));
6288 ignore_rest_of_line ();
6289 return;
6290 }
6291
6292 buf = (char *) xmalloc (20 + strlen (n->next));
6293 ex[0] = extent;
6294 ex[1] = '\0';
6295 sprintf (buf, "bra%s %s", ex, n->next);
6296 mri_assemble (buf);
6297 free (buf);
6298
6299 if (flag_mri)
6300 {
6301 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6302 ++input_line_pointer;
6303 }
6304
6305 demand_empty_rest_of_line ();
6306}
6307
6308/* Handle the MRI FOR pseudo-op. */
6309
6310static void
6311s_mri_for (qual)
6312 int qual;
6313{
6314 const char *varstart, *varstop;
6315 const char *initstart, *initstop;
6316 const char *endstart, *endstop;
6317 const char *bystart, *bystop;
6318 int up;
6319 int by;
6320 int extent;
6321 struct mri_control_info *n;
6322 char *buf;
6323 char *s;
6324 char ex[2];
6325
6326 /* The syntax is
6327 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6328 */
6329
6330 SKIP_WHITESPACE ();
6331 varstart = input_line_pointer;
6332
6333 /* Look for the '='. */
6334 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6335 && *input_line_pointer != '=')
6336 ++input_line_pointer;
6337 if (*input_line_pointer != '=')
6338 {
6339 as_bad (_("missing ="));
6340 ignore_rest_of_line ();
6341 return;
6342 }
6343
6344 varstop = input_line_pointer;
6345 if (varstop > varstart
6346 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6347 --varstop;
6348
6349 ++input_line_pointer;
6350
6351 initstart = input_line_pointer;
6352
6353 /* Look for TO or DOWNTO. */
6354 up = 1;
6355 initstop = NULL;
6356 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6357 {
6358 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6359 && ! is_part_of_name (input_line_pointer[2]))
6360 {
6361 initstop = input_line_pointer;
6362 input_line_pointer += 2;
6363 break;
6364 }
6365 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6366 && ! is_part_of_name (input_line_pointer[6]))
6367 {
6368 initstop = input_line_pointer;
6369 up = 0;
6370 input_line_pointer += 6;
6371 break;
6372 }
6373 ++input_line_pointer;
6374 }
6375 if (initstop == NULL)
6376 {
6377 as_bad (_("missing to or downto"));
6378 ignore_rest_of_line ();
6379 return;
6380 }
6381 if (initstop > initstart
6382 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6383 --initstop;
6384
6385 SKIP_WHITESPACE ();
6386 endstart = input_line_pointer;
6387
6388 /* Look for BY or DO. */
6389 by = 0;
6390 endstop = NULL;
6391 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6392 {
6393 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6394 && ! is_part_of_name (input_line_pointer[2]))
6395 {
6396 endstop = input_line_pointer;
6397 by = 1;
6398 input_line_pointer += 2;
6399 break;
6400 }
6401 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6402 && (input_line_pointer[2] == '.'
6403 || ! is_part_of_name (input_line_pointer[2])))
6404 {
6405 endstop = input_line_pointer;
6406 input_line_pointer += 2;
6407 break;
6408 }
6409 ++input_line_pointer;
6410 }
6411 if (endstop == NULL)
6412 {
6413 as_bad (_("missing do"));
6414 ignore_rest_of_line ();
6415 return;
6416 }
6417 if (endstop > endstart
6418 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6419 --endstop;
6420
6421 if (! by)
6422 {
6423 bystart = "#1";
6424 bystop = bystart + 2;
6425 }
6426 else
6427 {
6428 SKIP_WHITESPACE ();
6429 bystart = input_line_pointer;
6430
6431 /* Look for DO. */
6432 bystop = NULL;
6433 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6434 {
6435 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6436 && (input_line_pointer[2] == '.'
6437 || ! is_part_of_name (input_line_pointer[2])))
6438 {
6439 bystop = input_line_pointer;
6440 input_line_pointer += 2;
6441 break;
6442 }
6443 ++input_line_pointer;
6444 }
6445 if (bystop == NULL)
6446 {
6447 as_bad (_("missing do"));
6448 ignore_rest_of_line ();
6449 return;
6450 }
6451 if (bystop > bystart
6452 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6453 --bystop;
6454 }
6455
6456 if (*input_line_pointer != '.')
6457 extent = '\0';
6458 else
6459 {
6460 extent = input_line_pointer[1];
6461 input_line_pointer += 2;
6462 }
6463
6464 /* We have fully parsed the FOR operands. Now build the loop. */
6465
6466 n = push_mri_control (mri_for);
6467
6468 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6469
6470 /* move init,var */
6471 s = buf;
6472 *s++ = 'm';
6473 *s++ = 'o';
6474 *s++ = 'v';
6475 *s++ = 'e';
6476 if (qual != '\0')
6477 *s++ = qual;
6478 *s++ = ' ';
6479 memcpy (s, initstart, initstop - initstart);
6480 s += initstop - initstart;
6481 *s++ = ',';
6482 memcpy (s, varstart, varstop - varstart);
6483 s += varstop - varstart;
6484 *s = '\0';
6485 mri_assemble (buf);
6486
6487 colon (n->top);
6488
6489 /* cmp end,var */
6490 s = buf;
6491 *s++ = 'c';
6492 *s++ = 'm';
6493 *s++ = 'p';
6494 if (qual != '\0')
6495 *s++ = qual;
6496 *s++ = ' ';
6497 memcpy (s, endstart, endstop - endstart);
6498 s += endstop - endstart;
6499 *s++ = ',';
6500 memcpy (s, varstart, varstop - varstart);
6501 s += varstop - varstart;
6502 *s = '\0';
6503 mri_assemble (buf);
6504
6505 /* bcc bottom */
6506 ex[0] = extent;
6507 ex[1] = '\0';
6508 if (up)
6509 sprintf (buf, "blt%s %s", ex, n->bottom);
6510 else
6511 sprintf (buf, "bgt%s %s", ex, n->bottom);
6512 mri_assemble (buf);
6513
6514 /* Put together the add or sub instruction used by ENDF. */
6515 s = buf;
6516 if (up)
6517 strcpy (s, "add");
6518 else
6519 strcpy (s, "sub");
6520 s += 3;
6521 if (qual != '\0')
6522 *s++ = qual;
6523 *s++ = ' ';
6524 memcpy (s, bystart, bystop - bystart);
6525 s += bystop - bystart;
6526 *s++ = ',';
6527 memcpy (s, varstart, varstop - varstart);
6528 s += varstop - varstart;
6529 *s = '\0';
6530 n->incr = buf;
6531
6532 if (flag_mri)
6533 {
6534 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6535 ++input_line_pointer;
6536 }
6537
6538 demand_empty_rest_of_line ();
6539}
6540
6541/* Handle the MRI ENDF pseudo-op. */
6542
6543static void
6544s_mri_endf (ignore)
36823076 6545 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6546{
6547 if (mri_control_stack == NULL
6548 || mri_control_stack->type != mri_for)
6549 {
6550 as_bad (_("endf without for"));
6551 ignore_rest_of_line ();
6552 return;
6553 }
6554
6555 colon (mri_control_stack->next);
6556
6557 mri_assemble (mri_control_stack->incr);
6558
6559 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6560 mri_assemble (mri_control_stack->incr);
6561
6562 free (mri_control_stack->incr);
6563
6564 colon (mri_control_stack->bottom);
6565
6566 pop_mri_control ();
6567
6568 if (flag_mri)
6569 {
6570 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6571 ++input_line_pointer;
6572 }
6573
6574 demand_empty_rest_of_line ();
6575}
6576
6577/* Handle the MRI REPEAT pseudo-op. */
6578
6579static void
6580s_mri_repeat (ignore)
36823076 6581 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6582{
6583 struct mri_control_info *n;
6584
6585 n = push_mri_control (mri_repeat);
6586 colon (n->top);
6587 if (flag_mri)
6588 {
6589 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6590 ++input_line_pointer;
6591 }
6592 demand_empty_rest_of_line ();
6593}
6594
6595/* Handle the MRI UNTIL pseudo-op. */
6596
6597static void
6598s_mri_until (qual)
6599 int qual;
6600{
6601 char *s;
6602
6603 if (mri_control_stack == NULL
6604 || mri_control_stack->type != mri_repeat)
6605 {
6606 as_bad (_("until without repeat"));
6607 ignore_rest_of_line ();
6608 return;
6609 }
6610
6611 colon (mri_control_stack->next);
6612
6613 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6614 ;
6615
6616 parse_mri_control_expression (s, qual, (const char *) NULL,
6617 mri_control_stack->top, '\0');
6618
6619 colon (mri_control_stack->bottom);
6620
6621 input_line_pointer = s;
6622
6623 pop_mri_control ();
6624
6625 if (flag_mri)
6626 {
6627 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6628 ++input_line_pointer;
6629 }
6630
6631 demand_empty_rest_of_line ();
6632}
6633
6634/* Handle the MRI WHILE pseudo-op. */
6635
6636static void
6637s_mri_while (qual)
6638 int qual;
6639{
6640 char *s;
6641
6642 struct mri_control_info *n;
6643
6644 s = input_line_pointer;
6645 while (! is_end_of_line[(unsigned char) *s]
6646 && (! flag_mri || *s != '*'))
6647 s++;
6648 --s;
6649 while (*s == ' ' || *s == '\t')
6650 --s;
6651 if (s - input_line_pointer > 1
6652 && s[-1] == '.')
6653 s -= 2;
6654 if (s - input_line_pointer < 2
6655 || strncasecmp (s - 1, "DO", 2) != 0)
6656 {
6657 as_bad (_("missing do"));
6658 ignore_rest_of_line ();
6659 return;
6660 }
6661
6662 n = push_mri_control (mri_while);
6663
6664 colon (n->next);
6665
6666 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6667 s[1] == '.' ? s[2] : '\0');
6668
6669 input_line_pointer = s + 1;
6670 if (*input_line_pointer == '.')
6671 input_line_pointer += 2;
6672
6673 if (flag_mri)
6674 {
6675 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6676 ++input_line_pointer;
6677 }
6678
6679 demand_empty_rest_of_line ();
6680}
6681
6682/* Handle the MRI ENDW pseudo-op. */
6683
6684static void
6685s_mri_endw (ignore)
36823076 6686 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6687{
6688 char *buf;
6689
6690 if (mri_control_stack == NULL
6691 || mri_control_stack->type != mri_while)
6692 {
6693 as_bad (_("endw without while"));
6694 ignore_rest_of_line ();
6695 return;
6696 }
6697
6698 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6699 sprintf (buf, "bra %s", mri_control_stack->next);
6700 mri_assemble (buf);
6701 free (buf);
6702
6703 colon (mri_control_stack->bottom);
6704
6705 pop_mri_control ();
6706
6707 if (flag_mri)
6708 {
6709 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6710 ++input_line_pointer;
6711 }
6712
6713 demand_empty_rest_of_line ();
6714}
6715\f
6716/*
6717 * md_parse_option
6718 * Invocation line includes a switch not recognized by the base assembler.
6719 * See if it's a processor-specific option. These are:
6720 *
6721 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6722 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6723 * Select the architecture. Instructions or features not
6724 * supported by the selected architecture cause fatal
6725 * errors. More than one may be specified. The default is
6726 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6727 * for -m68000, and -m68882 is a synonym for -m68881.
6728 * -[A]m[c]no-68851, -[A]m[c]no-68881
6729 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6730 * so don't use or document it, but that's the way the parsing
6731 * works).
6732 *
6733 * -pic Indicates PIC.
6734 * -k Indicates PIC. (Sun 3 only.)
28e7409f 6735 * --pcrel Never turn PC-relative branches into absolute jumps.
252b5132
RH		 6736 *
6737 * --bitwise-or
6738 * Permit `|' to be used in expressions.
6739 *
6740 */
6741
6742#ifdef OBJ_ELF
6743CONST char *md_shortopts = "lSA:m:kQ:V";
6744#else
6745CONST char *md_shortopts = "lSA:m:k";
6746#endif
6747
6748struct option md_longopts[] = {
6749#define OPTION_PIC (OPTION_MD_BASE)
6750 {"pic", no_argument, NULL, OPTION_PIC},
6751#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6752 {"register-prefix-optional", no_argument, NULL,
6753 OPTION_REGISTER_PREFIX_OPTIONAL},
6754#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6755 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6756#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6757 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6758#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6759 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6760#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6761 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6762#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6763 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 6764#define OPTION_PCREL (OPTION_MD_BASE + 7)
6765 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 6766 {NULL, no_argument, NULL, 0}
6767};
6768size_t md_longopts_size = sizeof(md_longopts);
6769
6770int
6771md_parse_option (c, arg)
6772 int c;
6773 char *arg;
6774{
6775 switch (c)
6776 {
6777 case 'l': /* -l means keep external to 2 bit offset
6778 rather than 16 bit one */
6779 flag_short_refs = 1;
6780 break;
6781
6782 case 'S': /* -S means that jbsr's always turn into
6783 jsr's. */
6784 flag_long_jumps = 1;
6785 break;
6786
28e7409f
NC		 6787 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6788 branches into absolute jumps. */
6789 flag_keep_pcrel = 1;
6790 break;
6791
252b5132
RH		 6792 case 'A':
6793 if (*arg == 'm')
6794 arg++;
6795 /* intentional fall-through */
6796 case 'm':
6797
6798 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6799 {
6800 int i;
6801 unsigned long arch;
6802 const char *oarg = arg;
6803
6804 arg += 3;
6805 if (*arg == 'm')
6806 {
6807 arg++;
6808 if (arg[0] == 'c' && arg[1] == '6')
6809 arg++;
6810 }
6811 for (i = 0; i < n_archs; i++)
6812 if (!strcmp (arg, archs[i].name))
6813 break;
6814 if (i == n_archs)
6815 {
6816 unknown:
6817 as_bad (_("unrecognized option `%s'"), oarg);
6818 return 0;
6819 }
6820 arch = archs[i].arch;
6821 if (arch == m68881)
6822 no_68881 = 1;
6823 else if (arch == m68851)
6824 no_68851 = 1;
6825 else
6826 goto unknown;
6827 }
6828 else
6829 {
6830 int i;
6831
6832 if (arg[0] == 'c' && arg[1] == '6')
6833 arg++;
6834
6835 for (i = 0; i < n_archs; i++)
6836 if (!strcmp (arg, archs[i].name))
6837 {
6838 unsigned long arch = archs[i].arch;
6839 if (cpu_of_arch (arch))
6840 /* It's a cpu spec. */
6841 {
6842 current_architecture &= ~m68000up;
6843 current_architecture |= arch;
6844 }
6845 else if (arch == m68881)
6846 {
6847 current_architecture |= m68881;
6848 no_68881 = 0;
6849 }
6850 else if (arch == m68851)
6851 {
6852 current_architecture |= m68851;
6853 no_68851 = 0;
6854 }
6855 else
6856 /* ??? */
6857 abort ();
6858 break;
6859 }
6860 if (i == n_archs)
6861 {
6862 as_bad (_("unrecognized architecture specification `%s'"), arg);
6863 return 0;
6864 }
6865 }
6866 break;
6867
6868 case OPTION_PIC:
6869 case 'k':
6870 flag_want_pic = 1;
6871 break; /* -pic, Position Independent Code */
6872
6873 case OPTION_REGISTER_PREFIX_OPTIONAL:
6874 flag_reg_prefix_optional = 1;
6875 reg_prefix_optional_seen = 1;
6876 break;
6877
6878 /* -V: SVR4 argument to print version ID. */
6879 case 'V':
6880 print_version_id ();
6881 break;
6882
6883 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6884 should be emitted or not. FIXME: Not implemented. */
6885 case 'Q':
6886 break;
6887
6888 case OPTION_BITWISE_OR:
6889 {
6890 char *n, *t;
6891 const char *s;
6892
6893 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6894 t = n;
6895 for (s = m68k_comment_chars; *s != '\0'; s++)
6896 if (*s != '|')
6897 *t++ = *s;
6898 *t = '\0';
6899 m68k_comment_chars = n;
6900 }
6901 break;
6902
6903 case OPTION_BASE_SIZE_DEFAULT_16:
6904 m68k_index_width_default = SIZE_WORD;
6905 break;
6906
6907 case OPTION_BASE_SIZE_DEFAULT_32:
6908 m68k_index_width_default = SIZE_LONG;
6909 break;
6910
6911 case OPTION_DISP_SIZE_DEFAULT_16:
6912 m68k_rel32 = 0;
6913 m68k_rel32_from_cmdline = 1;
6914 break;
6915
6916 case OPTION_DISP_SIZE_DEFAULT_32:
6917 m68k_rel32 = 1;
6918 m68k_rel32_from_cmdline = 1;
6919 break;
6920
6921 default:
6922 return 0;
6923 }
6924
6925 return 1;
6926}
6927
6928void
6929md_show_usage (stream)
6930 FILE *stream;
6931{
6932 fprintf(stream, _("\
6933680X0 options:\n\
6934-l use 1 word for refs to undefined symbols [default 2]\n\
6935-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6936 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6937 | -mcpu32 | -m5200\n\
6938 specify variant of 680X0 architecture [default 68020]\n\
6939-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6940 target has/lacks floating-point coprocessor\n\
6941 [default yes for 68020, 68030, and cpu32]\n"));
6942 fprintf(stream, _("\
6943-m68851 | -mno-68851\n\
6944 target has/lacks memory-management unit coprocessor\n\
6945 [default yes for 68020 and up]\n\
6946-pic, -k generate position independent code\n\
6947-S turn jbsr into jsr\n\
28e7409f 6948--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 6949--register-prefix-optional\n\
6950 recognize register names without prefix character\n\
6951--bitwise-or do not treat `|' as a comment character\n"));
6952 fprintf (stream, _("\
6953--base-size-default-16 base reg without size is 16 bits\n\
6954--base-size-default-32 base reg without size is 32 bits (default)\n\
6955--disp-size-default-16 displacement with unknown size is 16 bits\n\
6956--disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6957}
6958\f
6959#ifdef TEST2
6960
6961/* TEST2: Test md_assemble() */
6962/* Warning, this routine probably doesn't work anymore */
6963
6964main ()
6965{
6966 struct m68k_it the_ins;
6967 char buf[120];
6968 char *cp;
6969 int n;
6970
6971 m68k_ip_begin ();
6972 for (;;)
6973 {
6974 if (!gets (buf) || !*buf)
6975 break;
6976 if (buf[0] == '|' || buf[1] == '.')
6977 continue;
6978 for (cp = buf; *cp; cp++)
6979 if (*cp == '\t')
6980 *cp = ' ';
6981 if (is_label (buf))
6982 continue;
6983 memset (&the_ins, '\0', sizeof (the_ins));
6984 m68k_ip (&the_ins, buf);
6985 if (the_ins.error)
6986 {
6987 printf (_("Error %s in %s\n"), the_ins.error, buf);
6988 }
6989 else
6990 {
6991 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
6992 for (n = 0; n < the_ins.numo; n++)
6993 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6994 printf (" ");
6995 print_the_insn (&the_ins.opcode[0], stdout);
6996 (void) putchar ('\n');
6997 }
6998 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6999 {
7000 if (the_ins.operands[n].error)
7001 {
7002 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7003 continue;
7004 }
7005 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7006 if (the_ins.operands[n].b_const)
7007 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7008 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7009 if (the_ins.operands[n].b_iadd)
7010 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7011 (void) putchar ('\n');
7012 }
7013 }
7014 m68k_ip_end ();
7015 return 0;
7016}
7017
7018is_label (str)
7019 char *str;
7020{
7021 while (*str == ' ')
7022 str++;
7023 while (*str && *str != ' ')
7024 str++;
7025 if (str[-1] == ':' || str[1] == '=')
7026 return 1;
7027 return 0;
7028}
7029
7030#endif
7031
7032/* Possible states for relaxation:
7033
7034 0 0 branch offset byte (bra, etc)
7035 0 1 word
7036 0 2 long
7037
7038 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7039 1 1 word
7040 1 2 long
7041
7042 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7043 2 1 word-long
7044 2 2 long-word
7045 2 3 long-long
7046
7047 */
7048
7049/* We have no need to default values of symbols. */
7050
7051/* ARGSUSED */
7052symbolS *
7053md_undefined_symbol (name)
36823076 7054 char *name ATTRIBUTE_UNUSED;
252b5132
RH		 7055{
7056 return 0;
7057}
7058
7059/* Round up a section size to the appropriate boundary. */
7060valueT
7061md_section_align (segment, size)
36823076 7062 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7063 valueT size;
7064{
7065#ifdef OBJ_AOUT
7066#ifdef BFD_ASSEMBLER
7067 /* For a.out, force the section size to be aligned. If we don't do
7068 this, BFD will align it for us, but it will not write out the
7069 final bytes of the section. This may be a bug in BFD, but it is
7070 easier to fix it here since that is how the other a.out targets
7071 work. */
7072 int align;
7073
7074 align = bfd_get_section_alignment (stdoutput, segment);
7075 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7076#endif
7077#endif
7078
7079 return size;
7080}
7081
7082/* Exactly what point is a PC-relative offset relative TO?
7083 On the 68k, it is relative to the address of the first extension
7084 word. The difference between the addresses of the offset and the
92774660 7085 first extension word is stored in fx_pcrel_adjust. */
252b5132
RH		 7086long
7087md_pcrel_from (fixP)
7088 fixS *fixP;
7089{
7090 int adjust;
7091
7092 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
7093 -1 as 64. */
7094 adjust = fixP->fx_pcrel_adjust;
7095 if (adjust == 64)
7096 adjust = -1;
7097 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7098}
7099
7100#ifndef BFD_ASSEMBLER
7101#ifdef OBJ_COFF
7102
7103/*ARGSUSED*/
7104void
7105tc_coff_symbol_emit_hook (ignore)
8fce3f5e 7106 symbolS *ignore ATTRIBUTE_UNUSED;
252b5132
RH		 7107{
7108}
7109
7110int
7111tc_coff_sizemachdep (frag)
7112 fragS *frag;
7113{
7114 switch (frag->fr_subtype & 0x3)
7115 {
7116 case BYTE:
7117 return 1;
7118 case SHORT:
7119 return 2;
7120 case LONG:
7121 return 4;
7122 default:
7123 abort ();
7124 return 0;
7125 }
7126}
7127
7128#endif
7129#endif
0d96863f
CM		 7130#ifdef OBJ_ELF
7131void m68k_elf_final_processing()
7132{
7133 /* Set file-specific flags if this is a cpu32 processor */
7134 if (cpu_of_arch (current_architecture) & cpu32)
7135 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7136}
7137#endif
252b5132 7138/* end of tc-m68k.c */
GDB Binutils - Deliverables
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