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Add support for macros.
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
CommitLineData
a1c7c0f3
ILT		 1/* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 1995 Free Software Foundation, Inc.
6d27d3a2 3
a39116f1 4 This file is part of GAS, the GNU Assembler.
6d27d3a2 5
a39116f1
RP		 6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
6d27d3a2 10
a39116f1
RP		 11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
6d27d3a2 15
a39116f1 16 You should have received a copy of the GNU General Public License
a1c7c0f3
ILT		 17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
19 02111-1307, USA. */
fecd2382
RP		 20
21#include <ctype.h>
f8701a3f 22#define NO_RELOC 0
fecd2382 23#include "as.h"
fecd2382 24#include "obstack.h"
b4ec75e0 25#include "subsegs.h"
fecd2382 26
e0982afe 27#include "opcode/m68k.h"
a1c7c0f3 28#include "m68k-parse.h"
3ad9ec6a 29
fecd2382
RP		 30/* This array holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful */
5f8cb05e
ILT		 32#ifdef OBJ_ELF
33CONST char comment_chars[] = "|#";
34#else
49864cfa 35CONST char comment_chars[] = "|";
5f8cb05e 36#endif
fecd2382
RP		 37
38/* This array holds the chars that only start a comment at the beginning of
39 a line. If the line seems to have the form '# 123 filename'
40 .line and .file directives will appear in the pre-processed output */
41/* Note that input_file.c hand checks for '#' at the beginning of the
42 first line of the input file. This is because the compiler outputs
43 #NO_APP at the beginning of its output. */
44/* Also note that comments like this one will always work. */
49864cfa 45CONST char line_comment_chars[] = "#";
fecd2382 46
49864cfa 47CONST char line_separator_chars[] = "";
587c4264 48
fecd2382 49/* Chars that can be used to separate mant from exp in floating point nums */
49864cfa 50CONST char EXP_CHARS[] = "eE";
fecd2382 51
49864cfa
KR		 52/* Chars that mean this number is a floating point constant, as
53 in "0f12.456" or "0d1.2345e12". */
fecd2382 54
49864cfa 55CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
fecd2382
RP		 56
57/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
58 changed in read.c . Ideally it shouldn't have to know about it at all,
49864cfa 59 but nothing is ideal around here. */
fecd2382 60
49864cfa 61const int md_reloc_size = 8; /* Size of relocation record */
fecd2382 62
b80d39a0 63/* Are we trying to generate PIC code? If so, absolute references
dff60b7d
ILT		 64 ought to be made into linkage table references or pc-relative
65 references. */
b80d39a0
KR		 66int flag_want_pic;
67
9ad5755f
KR		 68static int flag_short_refs; /* -l option */
69static int flag_long_jumps; /* -S option */
70
82489ea0
KR		 71#ifdef REGISTER_PREFIX_OPTIONAL
72int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
73#else
74int flag_reg_prefix_optional;
75#endif
76
27a53b88
ILT		 77/* The floating point coprocessor to use by default. */
78static enum m68k_register m68k_float_copnum = COP1;
79
6700d36e
ILT		 80/* If this is non-zero, then references to number(%pc) will be taken
81 to refer to number, rather than to %pc + number. */
82static int m68k_abspcadd;
83
84/* If this is non-zero, then the quick forms of the move, add, and sub
85 instructions are used when possible. */
86static int m68k_quick = 1;
87
88/* If this is non-zero, then if the size is not specified for a base
89 or outer displacement, the assembler assumes that the size should
90 be 32 bits. */
91static int m68k_rel32 = 1;
92
fecd2382
RP		 93/* Its an arbitrary name: This means I don't approve of it */
94/* See flames below */
95static struct obstack robyn;
96
97#define TAB(x,y) (((x)<<2)+(y))
98#define TABTYPE(xy) ((xy) >> 2)
99#define BYTE 0
100#define SHORT 1
101#define LONG 2
102#define SZ_UNDEF 3
3ad9ec6a 103#undef BRANCH
04ef74bb 104/* Case `g' except when BCC68000 is applicable. */
3ad9ec6a 105#define ABRANCH 1
04ef74bb 106/* Coprocessor branches. */
fecd2382 107#define FBRANCH 2
04ef74bb
KR		 108/* Mode 7.2 -- program counter indirect with (16-bit) displacement,
109 supported on all cpus. Widens to 32-bit absolute. */
fecd2382 110#define PCREL 3
04ef74bb
KR		 111/* For inserting an extra jmp instruction with long offset on 68000,
112 for expanding conditional branches. (Not bsr or bra.) Since the
113 68000 doesn't support 32-bit displacements for conditional
114 branches, we fake it by reversing the condition and branching
115 around a jmp with an absolute long operand. */
fecd2382 116#define BCC68000 4
04ef74bb
KR		 117/* For the DBcc "instructions". If the displacement requires 32 bits,
118 the branch-around-a-jump game is played here too. */
fecd2382 119#define DBCC 5
04ef74bb 120/* Not currently used? */
fecd2382 121#define PCLEA 6
04ef74bb
KR		 122/* Mode AINDX (apc-relative) using PC, with variable target, might fit
123 in 16 or 8 bits. */
124#define PCINDEX 7
fecd2382 125
bcb8dff8
KR		 126struct m68k_incant
127 {
a1c7c0f3 128 const char *m_operands;
bcb8dff8
KR		 129 unsigned long m_opcode;
130 short m_opnum;
131 short m_codenum;
132 int m_arch;
133 struct m68k_incant *m_next;
134 };
135
136#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
137#define gettwo(x) (((x)->m_opcode)&0xffff)
138
a1c7c0f3
ILT		 139static const enum m68k_register m68000_control_regs[] = { 0 };
140static const enum m68k_register m68010_control_regs[] = {
82489ea0
KR		 141 SFC, DFC, USP, VBR,
142 0
143};
a1c7c0f3 144static const enum m68k_register m68020_control_regs[] = {
82489ea0
KR		 145 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
146 0
147};
a1c7c0f3 148static const enum m68k_register m68040_control_regs[] = {
82489ea0
KR		 149 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
150 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
151 0
152};
a1c7c0f3 153static const enum m68k_register m68060_control_regs[] = {
82489ea0
KR		 154 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
155 USP, VBR, URP, SRP, PCR,
156 0
157};
b79de3a1 158#define cpu32_control_regs m68010_control_regs
82489ea0 159
a1c7c0f3 160static const enum m68k_register *control_regs;
fecd2382
RP		 161
162/* internal form of a 68020 instruction */
355afbcd 163struct m68k_it
a1c7c0f3
ILT		 164{
165 const char *error;
166 const char *args; /* list of opcode info */
167 int numargs;
355afbcd 168
a1c7c0f3
ILT		 169 int numo; /* Number of shorts in opcode */
170 short opcode[11];
355afbcd 171
a1c7c0f3 172 struct m68k_op operands[6];
355afbcd 173
a1c7c0f3
ILT		 174 int nexp; /* number of exprs in use */
175 struct m68k_exp exprs[4];
355afbcd 176
a1c7c0f3
ILT		 177 int nfrag; /* Number of frags we have to produce */
178 struct
179 {
180 int fragoff; /* Where in the current opcode the frag ends */
181 symbolS *fadd;
182 long foff;
183 int fragty;
184 }
185 fragb[4];
355afbcd 186
a1c7c0f3
ILT		 187 int nrel; /* Num of reloc strucs in use */
188 struct
189 {
190 int n;
191 expressionS exp;
192 char wid;
193 char pcrel;
194 /* In a pc relative address the difference between the address
195 of the offset and the address that the offset is relative
196 to. This depends on the addressing mode. Basically this
197 is the value to put in the offset field to address the
198 first byte of the offset, without regarding the special
199 significance of some values (in the branch instruction, for
200 example). */
201 int pcrel_fix;
202 }
203 reloc[5]; /* Five is enough??? */
204};
fecd2382 205
865a2edf
MT		 206#define cpu_of_arch(x) ((x) & m68000up)
207#define float_of_arch(x) ((x) & mfloat)
208#define mmu_of_arch(x) ((x) & mmmu)
209
355afbcd 210static struct m68k_it the_ins; /* the instruction being assembled */
fecd2382 211
a1c7c0f3
ILT		 212#define op(ex) ((ex)->exp.X_op)
213#define adds(ex) ((ex)->exp.X_add_symbol)
214#define subs(ex) ((ex)->exp.X_op_symbol)
215#define offs(ex) ((ex)->exp.X_add_number)
49864cfa 216
7c15cbe8 217/* Macros for adding things to the m68k_it struct */
fecd2382
RP		 218
219#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
220
221/* Like addword, but goes BEFORE general operands */
bcb8dff8
KR		 222static void
223insop (w, opcode)
224 int w;
225 struct m68k_incant *opcode;
226{
227 int z;
228 for(z=the_ins.numo;z>opcode->m_codenum;--z)
229 the_ins.opcode[z]=the_ins.opcode[z-1];
230 for(z=0;z<the_ins.nrel;z++)
231 the_ins.reloc[z].n+=2;
5f8cb05e
ILT		 232 for (z = 0; z < the_ins.nfrag; z++)
233 the_ins.fragb[z].fragoff++;
bcb8dff8
KR		 234 the_ins.opcode[opcode->m_codenum]=w;
235 the_ins.numo++;
236}
fecd2382 237
1404ef23
KR		 238/* The numo+1 kludge is so we can hit the low order byte of the prev word.
239 Blecch. */
49864cfa 240static void
5f8cb05e 241add_fix (width, exp, pc_rel, pc_fix)
49864cfa
KR		 242 char width;
243 struct m68k_exp *exp;
244 int pc_rel;
5f8cb05e 245 int pc_fix;
49864cfa
KR		 246{
247 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
248 ? (the_ins.numo*2-1)
249 : (((width)=='b')
5f8cb05e 250 ? (the_ins.numo*2+1)
49864cfa 251 : (the_ins.numo*2)));
a1c7c0f3 252 the_ins.reloc[the_ins.nrel].exp = exp->exp;
49864cfa 253 the_ins.reloc[the_ins.nrel].wid = width;
5f8cb05e 254 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
49864cfa 255 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
1404ef23
KR		 256}
257
5f8cb05e
ILT		 258/* Cause an extra frag to be generated here, inserting up to 10 bytes
259 (that value is chosen in the frag_var call in md_assemble). TYPE
260 is the subtype of the frag to be generated; its primary type is
261 rs_machine_dependent.
262
263 The TYPE parameter is also used by md_convert_frag_1 and
264 md_estimate_size_before_relax. The appropriate type of fixup will
265 be emitted by md_convert_frag_1.
266
267 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
49864cfa
KR		 268static void
269add_frag(add,off,type)
270 symbolS *add;
271 long off;
272 int type;
273{
274 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
275 the_ins.fragb[the_ins.nfrag].fadd=add;
276 the_ins.fragb[the_ins.nfrag].foff=off;
277 the_ins.fragb[the_ins.nfrag++].fragty=type;
1404ef23 278}
fecd2382 279
a1c7c0f3
ILT		 280#define isvar(ex) \
281 (op (ex) != O_constant && op (ex) != O_big)
fecd2382 282
49864cfa
KR		 283static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
284static int get_num PARAMS ((struct m68k_exp *exp, int ok));
49864cfa
KR		 285static int reverse_16_bits PARAMS ((int in));
286static int reverse_8_bits PARAMS ((int in));
49864cfa
KR		 287static void install_gen_operand PARAMS ((int mode, int val));
288static void install_operand PARAMS ((int mode, int val));
bcb8dff8
KR		 289static void s_bss PARAMS ((int));
290static void s_data1 PARAMS ((int));
291static void s_data2 PARAMS ((int));
292static void s_even PARAMS ((int));
293static void s_proc PARAMS ((int));
e9bb39b4
ILT		 294static void mri_chip PARAMS ((void));
295static void s_chip PARAMS ((int));
27a53b88 296static void s_fopt PARAMS ((int));
6700d36e
ILT		 297static void s_opt PARAMS ((int));
298static void s_reg PARAMS ((int));
e14994d9
ILT		 299static void s_restore PARAMS ((int));
300static void s_save PARAMS ((int));
b4ec75e0
ILT		 301static void s_mri_if PARAMS ((int));
302static void s_mri_else PARAMS ((int));
303static void s_mri_endi PARAMS ((int));
304static void s_mri_break PARAMS ((int));
305static void s_mri_next PARAMS ((int));
306static void s_mri_for PARAMS ((int));
307static void s_mri_endf PARAMS ((int));
308static void s_mri_repeat PARAMS ((int));
309static void s_mri_until PARAMS ((int));
310static void s_mri_while PARAMS ((int));
311static void s_mri_endw PARAMS ((int));
49864cfa
KR		 312
313static int current_architecture;
7c15cbe8 314
b79de3a1
KR		 315struct m68k_cpu {
316 unsigned long arch;
317 const char *name;
318};
319
320static const struct m68k_cpu archs[] = {
321 { m68000, "68000" },
322 { m68010, "68010" },
323 { m68020, "68020" },
324 { m68030, "68030" },
325 { m68040, "68040" },
326 { m68060, "68060" },
327 { cpu32, "cpu32" },
328 { m68881, "68881" },
329 { m68851, "68851" },
330 /* Aliases (effectively, so far as gas is concerned) for the above
331 cpus. */
332 { m68020, "68k" },
333 { m68000, "68302" },
334 { m68000, "68008" },
e9bb39b4
ILT		 335 { m68000, "68ec000" },
336 { m68000, "68hc000" },
337 { m68000, "68hc001" },
338 { m68020, "68ec020" },
339 { m68030, "68ec030" },
340 { m68040, "68ec040" },
341 { cpu32, "68330" },
b79de3a1
KR		 342 { cpu32, "68331" },
343 { cpu32, "68332" },
344 { cpu32, "68333" },
345 { cpu32, "68340" },
5f8cb05e 346 { cpu32, "68360" },
b79de3a1
KR		 347 { m68881, "68882" },
348};
349
350static const int n_archs = sizeof (archs) / sizeof (archs[0]);
351
fecd2382
RP		 352/* BCC68000 is for patching in an extra jmp instruction for long offsets
353 on the 68000. The 68000 doesn't support long branches with branchs */
354
355/* This table desribes how you change sizes for the various types of variable
356 size expressions. This version only supports two kinds. */
357
49864cfa
KR		 358/* Note that calls to frag_var need to specify the maximum expansion
359 needed; this is currently 10 bytes for DBCC. */
fecd2382
RP		 360
361/* The fields are:
a39116f1
RP		 362 How far Forward this mode will reach:
363 How far Backward this mode will reach:
364 How many bytes this mode will add to the size of the frag
365 Which mode to go to if the offset won't fit in this one
366 */
04ef74bb 367relax_typeS md_relax_table[] =
355afbcd
KR		 368{
369 {1, 1, 0, 0}, /* First entries aren't used */
370 {1, 1, 0, 0}, /* For no good reason except */
371 {1, 1, 0, 0}, /* that the VAX doesn't either */
372 {1, 1, 0, 0},
373
374 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
375 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
376 {0, 0, 4, 0},
377 {1, 1, 0, 0},
378
379 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
380 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
381 {0, 0, 4, 0},
382 {1, 1, 0, 0},
383
384 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
385 {(32767), (-32768), 2, TAB (PCREL, LONG)},
386 {0, 0, 4, 0},
387 {1, 1, 0, 0},
388
389 {(127), (-128), 0, TAB (BCC68000, SHORT)},
390 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
391 {0, 0, 6, 0}, /* jmp long space */
392 {1, 1, 0, 0},
393
394 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
395 {(32767), (-32768), 2, TAB (DBCC, LONG)},
396 {0, 0, 10, 0}, /* bra/jmp long space */
397 {1, 1, 0, 0},
398
399 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
400 {32767, -32768, 2, TAB (PCLEA, LONG)},
401 {0, 0, 6, 0},
402 {1, 1, 0, 0},
403
04ef74bb
KR		 404 /* For, e.g., jmp pcrel indexed. */
405 {125, -130, 0, TAB (PCINDEX, SHORT)},
406 {32765, -32770, 2, TAB (PCINDEX, LONG)},
407 {0, 0, 4, 0},
408 {1, 1, 0, 0},
355afbcd 409};
fecd2382
RP		 410
411/* These are the machine dependent pseudo-ops. These are included so
412 the assembler can work on the output from the SUN C compiler, which
413 generates these.
a39116f1 414 */
fecd2382
RP		 415
416/* This table describes all the machine specific pseudo-ops the assembler
417 has to support. The fields are:
a39116f1
RP		 418 pseudo-op name without dot
419 function to call to execute this pseudo-op
420 Integer arg to pass to the function
421 */
49864cfa 422CONST pseudo_typeS md_pseudo_table[] =
355afbcd
KR		 423{
424 {"data1", s_data1, 0},
425 {"data2", s_data2, 0},
426 {"bss", s_bss, 0},
427 {"even", s_even, 0},
428 {"skip", s_space, 0},
429 {"proc", s_proc, 0},
bec66218 430#ifdef TE_SUN3
355afbcd 431 {"align", s_align_bytes, 0},
5f8cb05e
ILT		 432#endif
433#ifdef OBJ_ELF
434 {"swbeg", s_ignore, 0},
bec66218 435#endif
e9bb39b4
ILT		 436
437 /* The following pseudo-ops are supported for MRI compatibility. */
438 {"chip", s_chip, 0},
439 {"comline", s_space, 1},
27a53b88
ILT		 440 {"fopt", s_fopt, 0},
441 {"mask2", s_ignore, 0},
6700d36e
ILT		 442 {"opt", s_opt, 0},
443 {"reg", s_reg, 0},
e14994d9
ILT		 444 {"restore", s_restore, 0},
445 {"save", s_save, 0},
e9bb39b4 446
b4ec75e0
ILT		 447 {"if", s_mri_if, 0},
448 {"if.b", s_mri_if, 'b'},
449 {"if.w", s_mri_if, 'w'},
450 {"if.l", s_mri_if, 'l'},
451 {"else", s_mri_else, 0},
452 {"else.s", s_mri_else, 's'},
453 {"else.l", s_mri_else, 'l'},
454 {"endi", s_mri_endi, 0},
455 {"break", s_mri_break, 0},
456 {"break.s", s_mri_break, 's'},
457 {"break.l", s_mri_break, 'l'},
458 {"next", s_mri_next, 0},
459 {"next.s", s_mri_next, 's'},
460 {"next.l", s_mri_next, 'l'},
461 {"for", s_mri_for, 0},
462 {"for.b", s_mri_for, 'b'},
463 {"for.w", s_mri_for, 'w'},
464 {"for.l", s_mri_for, 'l'},
465 {"endf", s_mri_endf, 0},
466 {"repeat", s_mri_repeat, 0},
467 {"until", s_mri_until, 0},
468 {"until.b", s_mri_until, 'b'},
469 {"until.w", s_mri_until, 'w'},
470 {"until.l", s_mri_until, 'l'},
471 {"while", s_mri_while, 0},
472 {"while.b", s_mri_while, 'b'},
473 {"while.w", s_mri_while, 'w'},
474 {"while.l", s_mri_while, 'l'},
475 {"endw", s_mri_endw, 0},
476
355afbcd 477 {0, 0, 0}
fecd2382
RP		 478};
479
480
3ad9ec6a 481/* The mote pseudo ops are put into the opcode table, since they
355afbcd 482 don't start with a . they look like opcodes to gas.
3ad9ec6a 483 */
355afbcd 484extern void obj_coff_section ();
3ad9ec6a 485
49864cfa 486CONST pseudo_typeS mote_pseudo_table[] =
3ad9ec6a
ILT		 487{
488
b79de3a1 489 {"dcl", cons, 4},
355afbcd 490 {"dc", cons, 2},
b79de3a1
KR		 491 {"dcw", cons, 2},
492 {"dcb", cons, 1},
3ad9ec6a 493
b79de3a1 494 {"dsl", s_space, 4},
355afbcd 495 {"ds", s_space, 2},
b79de3a1
KR		 496 {"dsw", s_space, 2},
497 {"dsb", s_space, 1},
3ad9ec6a 498
355afbcd
KR		 499 {"xdef", s_globl, 0},
500 {"align", s_align_ptwo, 0},
3ad9ec6a 501#ifdef M68KCOFF
355afbcd
KR		 502 {"sect", obj_coff_section, 0},
503 {"section", obj_coff_section, 0},
3ad9ec6a 504#endif
bcb8dff8 505 {0, 0, 0}
3ad9ec6a
ILT		 506};
507
fecd2382
RP		 508#define issbyte(x) ((x)>=-128 && (x)<=127)
509#define isubyte(x) ((x)>=0 && (x)<=255)
510#define issword(x) ((x)>=-32768 && (x)<=32767)
511#define isuword(x) ((x)>=0 && (x)<=65535)
f8701a3f 512
e284846a 513#define isbyte(x) ((x)>= -255 && (x)<=255)
fecd2382
RP		 514#define isword(x) ((x)>=-32768 && (x)<=65535)
515#define islong(x) (1)
f8701a3f
SC		 516
517extern char *input_line_pointer;
fecd2382 518
fecd2382
RP		 519static char mklower_table[256];
520#define mklower(c) (mklower_table[(unsigned char)(c)])
f8701a3f 521static char notend_table[256];
fecd2382 522static char alt_notend_table[256];
a1c7c0f3
ILT		 523#define notend(s) \
524 (! (notend_table[(unsigned char) *s] \
525 || (*s == ':' \
526 && alt_notend_table[(unsigned char) s[1]])))
7c15cbe8 527
49864cfa 528#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
3ad9ec6a 529
82489ea0
KR		 530#ifdef NO_PCREL_RELOCS
531
532int
533make_pcrel_absolute(fixP, add_number)
534 fixS *fixP;
535 long *add_number;
536{
537 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
538
539 /* rewrite the PC relative instructions to absolute address ones.
540 * these are rumoured to be faster, and the apollo linker refuses
541 * to deal with the PC relative relocations.
542 */
543 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
544 {
545 opcode[0] = 0x4e;
546 opcode[1] = 0xf9;
547 }
548 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
549 {
550 opcode[0] = 0x4e;
551 opcode[1] = 0xb9;
552 }
553 else
554 as_fatal ("Unknown PC relative instruction");
555 *add_number -= 4;
556 return 0;
557}
558
559#endif /* NO_PCREL_RELOCS */
560
355afbcd
KR		 561short
562tc_coff_fix2rtype (fixP)
563 fixS *fixP;
fecd2382 564{
82489ea0
KR		 565#ifdef NO_PCREL_RELOCS
566 know (fixP->fx_pcrel == 0);
567 return (fixP->fx_size == 1 ? R_RELBYTE
568 : fixP->fx_size == 2 ? R_DIR16
569 : R_DIR32);
570#else
355afbcd
KR		 571 return (fixP->fx_pcrel ?
572 (fixP->fx_size == 1 ? R_PCRBYTE :
573 fixP->fx_size == 2 ? R_PCRWORD :
574 R_PCRLONG) :
575 (fixP->fx_size == 1 ? R_RELBYTE :
576 fixP->fx_size == 2 ? R_RELWORD :
577 R_RELLONG));
82489ea0 578#endif
3ad9ec6a
ILT		 579}
580
581#endif
fecd2382 582
49864cfa
KR		 583#ifdef BFD_ASSEMBLER
584
585arelent *
586tc_gen_reloc (section, fixp)
587 asection *section;
588 fixS *fixp;
589{
590 arelent *reloc;
591 bfd_reloc_code_real_type code;
592
593#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
594 switch (F (fixp->fx_size, fixp->fx_pcrel))
595 {
596#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
597 MAP (1, 0, BFD_RELOC_8);
598 MAP (2, 0, BFD_RELOC_16);
599 MAP (4, 0, BFD_RELOC_32);
600 MAP (1, 1, BFD_RELOC_8_PCREL);
601 MAP (2, 1, BFD_RELOC_16_PCREL);
602 MAP (4, 1, BFD_RELOC_32_PCREL);
603 default:
604 abort ();
605 }
606
607 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
608 assert (reloc != 0);
609 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
610 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
611 if (fixp->fx_pcrel)
612 reloc->addend = fixp->fx_addnumber;
613 else
614 reloc->addend = 0;
615
616 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
617 assert (reloc->howto != 0);
618
619 return reloc;
620}
621
622#endif /* BFD_ASSEMBLER */
623
49864cfa
KR		 624/* Handle of the OPCODE hash table. NULL means any use before
625 m68k_ip_begin() will crash. */
626static struct hash_control *op_hash;
fecd2382 627\f
a1c7c0f3 628/* Assemble an m68k instruction. */
355afbcd 629
355afbcd
KR		 630void
631m68k_ip (instring)
6d27d3a2 632 char *instring;
fecd2382 633{
6d27d3a2
KR		 634 register char *p;
635 register struct m68k_op *opP;
636 register struct m68k_incant *opcode;
a1c7c0f3 637 register const char *s;
6d27d3a2 638 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
3ad9ec6a 639 char *pdot, *pdotmove;
a1c7c0f3 640 enum m68k_size siz1, siz2;
355afbcd
KR		 641 char c;
642 int losing;
643 int opsfound;
644 char *crack_operand ();
6d27d3a2
KR		 645 LITTLENUM_TYPE words[6];
646 LITTLENUM_TYPE *wordp;
8be74775 647 unsigned long ok_arch = 0;
6d27d3a2
KR		 648
649 if (*instring == ' ')
650 instring++; /* skip leading whitespace */
651
652 /* Scan up to end of operation-code, which MUST end in end-of-string
653 or exactly 1 space. */
3ad9ec6a 654 pdot = 0;
355afbcd
KR		 655 for (p = instring; *p != '\0'; p++)
656 {
657 if (*p == ' ')
658 break;
659 if (*p == '.')
660 pdot = p;
661 }
6d27d3a2 662
355afbcd
KR		 663 if (p == instring)
664 {
665 the_ins.error = "No operator";
355afbcd
KR		 666 return;
667 }
6d27d3a2
KR		 668
669 /* p now points to the end of the opcode name, probably whitespace.
a1c7c0f3
ILT		 670 Make sure the name is null terminated by clobbering the
671 whitespace, look it up in the hash table, then fix it back.
3ad9ec6a 672 Remove a dot, first, since the opcode tables have none. */
355afbcd
KR		 673 if (pdot != NULL)
674 {
675 for (pdotmove = pdot; pdotmove < p; pdotmove++)
676 *pdotmove = pdotmove[1];
677 p--;
678 }
3ad9ec6a 679
6d27d3a2
KR		 680 c = *p;
681 *p = '\0';
355afbcd 682 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
6d27d3a2
KR		 683 *p = c;
684
355afbcd
KR		 685 if (pdot != NULL)
686 {
687 for (pdotmove = p; pdotmove > pdot; pdotmove--)
688 *pdotmove = pdotmove[-1];
689 *pdot = '.';
690 ++p;
691 }
3ad9ec6a 692
355afbcd
KR		 693 if (opcode == NULL)
694 {
695 the_ins.error = "Unknown operator";
355afbcd
KR		 696 return;
697 }
6d27d3a2
KR		 698
699 /* found a legitimate opcode, start matching operands */
355afbcd
KR		 700 while (*p == ' ')
701 ++p;
6d27d3a2 702
355afbcd
KR		 703 if (opcode->m_operands == 0)
704 {
705 char *old = input_line_pointer;
706 *old = '\n';
707 input_line_pointer = p;
708 /* Ahh - it's a motorola style psuedo op */
709 mote_pseudo_table[opcode->m_opnum].poc_handler
710 (mote_pseudo_table[opcode->m_opnum].poc_val);
711 input_line_pointer = old;
712 *old = 0;
3ad9ec6a 713
355afbcd
KR		 714 return;
715 }
3ad9ec6a 716
355afbcd
KR		 717 for (opP = &the_ins.operands[0]; *p; opP++)
718 {
355afbcd 719 p = crack_operand (p, opP);
6d27d3a2 720
355afbcd
KR		 721 if (opP->error)
722 {
723 the_ins.error = opP->error;
724 return;
725 }
6d27d3a2 726 }
6d27d3a2
KR		 727
728 opsfound = opP - &the_ins.operands[0];
729
a1c7c0f3
ILT		 730 /* This ugly hack is to support the floating pt opcodes in their
731 standard form. Essentially, we fake a first enty of type COP#1 */
355afbcd
KR		 732 if (opcode->m_operands[0] == 'I')
733 {
734 int n;
6d27d3a2 735
355afbcd
KR		 736 for (n = opsfound; n > 0; --n)
737 the_ins.operands[n] = the_ins.operands[n - 1];
6d27d3a2 738
a1c7c0f3
ILT		 739 memset ((char *) (&the_ins.operands[0]), '\0',
740 sizeof (the_ins.operands[0]));
741 the_ins.operands[0].mode = CONTROL;
27a53b88 742 the_ins.operands[0].reg = m68k_float_copnum;
355afbcd
KR		 743 opsfound++;
744 }
6d27d3a2
KR		 745
746 /* We've got the operands. Find an opcode that'll accept them */
355afbcd
KR		 747 for (losing = 0;;)
748 {
49864cfa
KR		 749 /* If we didn't get the right number of ops, or we have no
750 common model with this pattern then reject this pattern. */
6d27d3a2 751
355afbcd
KR		 752 if (opsfound != opcode->m_opnum
753 || ((opcode->m_arch & current_architecture) == 0))
754 {
755 ++losing;
756 ok_arch |= opcode->m_arch;
757 }
758 else
759 {
a1c7c0f3
ILT		 760 for (s = opcode->m_operands, opP = &the_ins.operands[0];
761 *s && !losing;
762 s += 2, opP++)
355afbcd
KR		 763 {
764 /* Warning: this switch is huge! */
49864cfa
KR		 765 /* I've tried to organize the cases into this order:
766 non-alpha first, then alpha by letter. Lower-case
767 goes directly before uppercase counterpart. */
768 /* Code with multiple case ...: gets sorted by the lowest
769 case ... it belongs to. I hope this makes sense. */
355afbcd
KR		 770 switch (*s)
771 {
a1c7c0f3
ILT		 772 case '!':
773 switch (opP->mode)
774 {
775 case IMMED:
776 case DREG:
777 case AREG:
778 case FPREG:
779 case CONTROL:
780 case AINC:
781 case ADEC:
782 case REGLST:
783 losing++;
784 break;
785 default:
786 break;
787 }
355afbcd
KR		 788 break;
789
790 case '`':
791 switch (opP->mode)
792 {
355afbcd
KR		 793 case IMMED:
794 case DREG:
795 case AREG:
a1c7c0f3
ILT		 796 case FPREG:
797 case CONTROL:
355afbcd
KR		 798 case AINC:
799 case REGLST:
800 case AINDR:
801 losing++;
bcb8dff8
KR		 802 break;
803 default:
804 break;
355afbcd
KR		 805 }
806 break;
8be74775 807
355afbcd
KR		 808 case '#':
809 if (opP->mode != IMMED)
810 losing++;
a1c7c0f3
ILT		 811 else if (s[1] == 'b'
812 && ! isvar (&opP->disp)
336435bc
ILT		 813 && (opP->disp.exp.X_op != O_constant
814 || ! isbyte (opP->disp.exp.X_add_number)))
a1c7c0f3
ILT		 815 losing++;
816 else if (s[1] == 'w'
817 && ! isvar (&opP->disp)
336435bc
ILT		 818 && (opP->disp.exp.X_op != O_constant
819 || ! isword (opP->disp.exp.X_add_number)))
a1c7c0f3 820 losing++;
355afbcd
KR		 821 break;
822
823 case '^':
824 case 'T':
825 if (opP->mode != IMMED)
826 losing++;
827 break;
828
829 case '$':
a1c7c0f3
ILT		 830 if (opP->mode == AREG
831 || opP->mode == CONTROL
832 || opP->mode == FPREG
833 || opP->mode == IMMED
834 || opP->mode == REGLST
835 || (opP->mode != ABSL
836 && (opP->reg == PC
837 || opP->reg == ZPC)))
355afbcd
KR		 838 losing++;
839 break;
840
841 case '%':
a1c7c0f3
ILT		 842 if (opP->mode == CONTROL
843 || opP->mode == FPREG
844 || opP->mode == REGLST
845 || (opP->mode != ABSL
846 && opP->mode != IMMED
847 && (opP->reg == PC
848 || opP->reg == ZPC)))
355afbcd
KR		 849 losing++;
850 break;
851
355afbcd 852 case '&':
a1c7c0f3
ILT		 853 switch (opP->mode)
854 {
855 case DREG:
856 case AREG:
857 case FPREG:
858 case CONTROL:
859 case IMMED:
860 case AINC:
861 case ADEC:
862 case REGLST:
863 losing++;
864 break;
865 case ABSL:
866 break;
867 default:
868 if (opP->reg == PC
869 || opP->reg == ZPC)
870 losing++;
871 break;
872 }
355afbcd
KR		 873 break;
874
875 case '*':
a1c7c0f3
ILT		 876 if (opP->mode == CONTROL
877 || opP->mode == FPREG
878 || opP->mode == REGLST)
355afbcd
KR		 879 losing++;
880 break;
881
882 case '+':
883 if (opP->mode != AINC)
884 losing++;
885 break;
886
887 case '-':
888 if (opP->mode != ADEC)
889 losing++;
890 break;
891
892 case '/':
a1c7c0f3
ILT		 893 switch (opP->mode)
894 {
895 case AREG:
896 case CONTROL:
897 case FPREG:
898 case AINC:
899 case ADEC:
900 case IMMED:
901 case REGLST:
902 losing++;
903 break;
904 default:
905 break;
906 }
355afbcd
KR		 907 break;
908
909 case ';':
a1c7c0f3
ILT		 910 switch (opP->mode)
911 {
912 case AREG:
913 case CONTROL:
914 case FPREG:
915 case REGLST:
916 losing++;
917 break;
918 default:
919 break;
920 }
355afbcd
KR		 921 break;
922
923 case '?':
a1c7c0f3
ILT		 924 switch (opP->mode)
925 {
926 case AREG:
927 case CONTROL:
928 case FPREG:
929 case AINC:
930 case ADEC:
931 case IMMED:
932 case REGLST:
933 losing++;
934 break;
935 case ABSL:
936 break;
937 default:
938 if (opP->reg == PC || opP->reg == ZPC)
939 losing++;
940 break;
941 }
355afbcd
KR		 942 break;
943
944 case '@':
a1c7c0f3
ILT		 945 switch (opP->mode)
946 {
947 case AREG:
948 case CONTROL:
949 case FPREG:
950 case IMMED:
951 case REGLST:
952 losing++;
953 break;
954 default:
955 break;
956 }
355afbcd
KR		 957 break;
958
959 case '~': /* For now! (JF FOO is this right?) */
a1c7c0f3
ILT		 960 switch (opP->mode)
961 {
962 case DREG:
963 case AREG:
964 case CONTROL:
965 case FPREG:
966 case IMMED:
967 case REGLST:
968 losing++;
969 break;
970 case ABSL:
971 break;
972 default:
973 if (opP->reg == PC
974 || opP->reg == ZPC)
975 losing++;
976 break;
977 }
355afbcd
KR		 978 break;
979
980 case '3':
a1c7c0f3
ILT		 981 if (opP->mode != CONTROL
982 || (opP->reg != TT0 && opP->reg != TT1))
355afbcd
KR		 983 losing++;
984 break;
985
986 case 'A':
987 if (opP->mode != AREG)
988 losing++;
989 break;
a1c7c0f3 990
355afbcd
KR		 991 case 'a':
992 if (opP->mode != AINDR)
a1c7c0f3 993 ++losing;
355afbcd 994 break;
a1c7c0f3 995
355afbcd 996 case 'B': /* FOO */
a1c7c0f3
ILT		 997 if (opP->mode != ABSL
998 || (flag_long_jumps
999 && strncmp (instring, "jbsr", 4) == 0))
355afbcd
KR		 1000 losing++;
1001 break;
1002
1003 case 'C':
a1c7c0f3 1004 if (opP->mode != CONTROL || opP->reg != CCR)
355afbcd
KR		 1005 losing++;
1006 break;
1007
a1c7c0f3
ILT		 1008 case 'd':
1009 if (opP->mode != DISP
1010 || opP->reg < ADDR0
1011 || opP->reg > ADDR7)
355afbcd
KR		 1012 losing++;
1013 break;
1014
1015 case 'D':
1016 if (opP->mode != DREG)
1017 losing++;
1018 break;
1019
1020 case 'F':
a1c7c0f3 1021 if (opP->mode != FPREG)
355afbcd
KR		 1022 losing++;
1023 break;
1024
1025 case 'I':
a1c7c0f3 1026 if (opP->mode != CONTROL
27a53b88
ILT		 1027 || opP->reg < COP0
1028 || opP->reg > COP7)
355afbcd
KR		 1029 losing++;
1030 break;
1031
1032 case 'J':
a1c7c0f3 1033 if (opP->mode != CONTROL
355afbcd 1034 || opP->reg < USP
82489ea0
KR		 1035 || opP->reg > last_movec_reg)
1036 losing++;
1037 else
355afbcd 1038 {
a1c7c0f3 1039 const enum m68k_register *rp;
82489ea0
KR		 1040 for (rp = control_regs; *rp; rp++)
1041 if (*rp == opP->reg)
1042 break;
1043 if (*rp == 0)
1044 losing++;
1045 }
355afbcd
KR		 1046 break;
1047
1048 case 'k':
1049 if (opP->mode != IMMED)
1050 losing++;
1051 break;
8be74775 1052
355afbcd
KR		 1053 case 'l':
1054 case 'L':
a1c7c0f3
ILT		 1055 if (opP->mode == DREG
1056 || opP->mode == AREG
1057 || opP->mode == FPREG)
355afbcd
KR		 1058 {
1059 if (s[1] == '8')
1060 losing++;
1061 else
1062 {
a1c7c0f3
ILT		 1063 switch (opP->mode)
1064 {
1065 case DREG:
1066 opP->mask = 1 << (opP->reg - DATA0);
1067 break;
1068 case AREG:
1069 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1070 break;
1071 case FPREG:
1072 opP->mask = 1 << (opP->reg - FP0 + 16);
1073 break;
1074 default:
1075 abort ();
1076 }
355afbcd 1077 opP->mode = REGLST;
355afbcd
KR		 1078 }
1079 }
a1c7c0f3 1080 else if (opP->mode == CONTROL)
355afbcd 1081 {
a1c7c0f3
ILT		 1082 if (s[1] != '8')
1083 losing++;
1084 else
1085 {
1086 switch (opP->reg)
1087 {
1088 case FPI:
1089 opP->mask = 1 << 24;
1090 break;
1091 case FPS:
1092 opP->mask = 1 << 25;
1093 break;
1094 case FPC:
1095 opP->mask = 1 << 26;
1096 break;
1097 default:
1098 losing++;
1099 break;
1100 }
1101 opP->mode = REGLST;
1102 }
355afbcd 1103 }
6700d36e
ILT		 1104 else if (opP->mode == ABSL
1105 && opP->disp.size == SIZE_UNSPEC
1106 && opP->disp.exp.X_op == O_constant)
1107 {
1108 /* This is what the MRI REG pseudo-op generates. */
1109 opP->mode = REGLST;
1110 opP->mask = opP->disp.exp.X_add_number;
1111 }
a1c7c0f3 1112 else if (opP->mode != REGLST)
355afbcd 1113 losing++;
a1c7c0f3
ILT		 1114 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1115 losing++;
1116 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
355afbcd
KR		 1117 losing++;
1118 break;
1119
1120 case 'M':
1121 if (opP->mode != IMMED)
1122 losing++;
336435bc
ILT		 1123 else if (opP->disp.exp.X_op != O_constant
1124 || ! issbyte (opP->disp.exp.X_add_number))
a1c7c0f3 1125 losing++;
6700d36e
ILT		 1126 else if (! m68k_quick
1127 && instring[3] != 'q'
1128 && instring[4] != 'q')
1129 losing++;
355afbcd 1130 break;
8be74775 1131
355afbcd
KR		 1132 case 'O':
1133 if (opP->mode != DREG && opP->mode != IMMED)
1134 losing++;
1135 break;
6d27d3a2 1136
355afbcd
KR		 1137 case 'Q':
1138 if (opP->mode != IMMED)
1139 losing++;
336435bc 1140 else if (opP->disp.exp.X_op != O_constant
a1c7c0f3
ILT		 1141 || opP->disp.exp.X_add_number < 1
1142 || opP->disp.exp.X_add_number > 8)
1143 losing++;
6700d36e
ILT		 1144 else if (! m68k_quick
1145 && (strncmp (instring, "add", 3) == 0
1146 || strncmp (instring, "sub", 3) == 0)
1147 && instring[3] != 'q')
1148 losing++;
355afbcd 1149 break;
8be74775 1150
355afbcd
KR		 1151 case 'R':
1152 if (opP->mode != DREG && opP->mode != AREG)
1153 losing++;
1154 break;
8be74775 1155
355afbcd 1156 case 'r':
a1c7c0f3
ILT		 1157 if (opP->mode != AINDR
1158 && (opP->mode != BASE
1159 || (opP->reg != 0
1160 && opP->reg != ZADDR0)
1161 || opP->disp.exp.X_op != O_absent
1162 || ((opP->index.reg < DATA0
1163 || opP->index.reg > DATA7)
1164 && (opP->index.reg < ADDR0
1165 || opP->index.reg > ADDR7))
1166 || opP->index.size != SIZE_UNSPEC
1167 || opP->index.scale != 1))
355afbcd
KR		 1168 losing++;
1169 break;
c50140c8 1170
355afbcd 1171 case 's':
a1c7c0f3
ILT		 1172 if (opP->mode != CONTROL
1173 || ! (opP->reg == FPI
1174 || opP->reg == FPS
1175 || opP->reg == FPC))
355afbcd
KR		 1176 losing++;
1177 break;
8be74775 1178
355afbcd 1179 case 'S':
a1c7c0f3 1180 if (opP->mode != CONTROL || opP->reg != SR)
355afbcd
KR		 1181 losing++;
1182 break;
8be74775 1183
355afbcd
KR		 1184 case 't':
1185 if (opP->mode != IMMED)
1186 losing++;
336435bc 1187 else if (opP->disp.exp.X_op != O_constant
a1c7c0f3
ILT		 1188 || opP->disp.exp.X_add_number < 0
1189 || opP->disp.exp.X_add_number > 7)
1190 losing++;
355afbcd 1191 break;
4134a793 1192
355afbcd 1193 case 'U':
a1c7c0f3 1194 if (opP->mode != CONTROL || opP->reg != USP)
355afbcd
KR		 1195 losing++;
1196 break;
8be74775 1197
355afbcd 1198 /* JF these are out of order. We could put them
1404ef23
KR		 1199 in order if we were willing to put up with
1200 bunches of #ifdef m68851s in the code.
4134a793 1201
1404ef23
KR		 1202 Don't forget that you need these operands
1203 to use 68030 MMU instructions. */
f8701a3f 1204#ifndef NO_68851
355afbcd
KR		 1205 /* Memory addressing mode used by pflushr */
1206 case '|':
a1c7c0f3
ILT		 1207 if (opP->mode == CONTROL
1208 || opP->mode == FPREG
1209 || opP->mode == DREG
1210 || opP->mode == AREG
1211 || opP->mode == REGLST)
355afbcd
KR		 1212 losing++;
1213 break;
1214
1215 case 'f':
a1c7c0f3
ILT		 1216 if (opP->mode != CONTROL
1217 || (opP->reg != SFC && opP->reg != DFC))
355afbcd
KR		 1218 losing++;
1219 break;
1220
1221 case 'P':
a1c7c0f3
ILT		 1222 if (opP->mode != CONTROL
1223 || (opP->reg != TC
1224 && opP->reg != CAL
1225 && opP->reg != VAL
1226 && opP->reg != SCC
1227 && opP->reg != AC))
355afbcd
KR		 1228 losing++;
1229 break;
1230
1231 case 'V':
a1c7c0f3
ILT		 1232 if (opP->mode != CONTROL
1233 || opP->reg != VAL)
355afbcd
KR		 1234 losing++;
1235 break;
8be74775 1236
355afbcd 1237 case 'W':
a1c7c0f3
ILT		 1238 if (opP->mode != CONTROL
1239 || (opP->reg != DRP
1240 && opP->reg != SRP
355afbcd
KR		 1241 && opP->reg != CRP))
1242 losing++;
1243 break;
1244
1245 case 'X':
a1c7c0f3
ILT		 1246 if (opP->mode != CONTROL
1247 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1248 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
355afbcd
KR		 1249 losing++;
1250 break;
1251
1252 case 'Y':
a1c7c0f3 1253 if (opP->mode != CONTROL || opP->reg != PSR)
355afbcd
KR		 1254 losing++;
1255 break;
1256
1257 case 'Z':
a1c7c0f3 1258 if (opP->mode != CONTROL || opP->reg != PCSR)
355afbcd
KR		 1259 losing++;
1260 break;
f8701a3f 1261#endif
355afbcd 1262 case 'c':
a1c7c0f3
ILT		 1263 if (opP->mode != CONTROL
1264 || (opP->reg != NC
1265 && opP->reg != IC
1266 && opP->reg != DC
1267 && opP->reg != BC))
355afbcd
KR		 1268 {
1269 losing++;
1270 } /* not a cache specifier. */
1271 break;
1272
1273 case '_':
1274 if (opP->mode != ABSL)
a1c7c0f3 1275 ++losing;
355afbcd 1276 break;
8be74775 1277
355afbcd 1278 default:
a1c7c0f3 1279 abort ();
355afbcd 1280 } /* switch on type of operand */
6d27d3a2 1281
355afbcd
KR		 1282 if (losing)
1283 break;
1284 } /* for each operand */
1285 } /* if immediately wrong */
6d27d3a2 1286
355afbcd
KR		 1287 if (!losing)
1288 {
8be74775 1289 break;
355afbcd 1290 } /* got it. */
6d27d3a2 1291
355afbcd 1292 opcode = opcode->m_next;
6d27d3a2 1293
355afbcd 1294 if (!opcode)
8be74775 1295 {
355afbcd
KR		 1296 if (ok_arch
1297 && !(ok_arch & current_architecture))
8be74775 1298 {
355afbcd
KR		 1299 char buf[200], *cp;
1300 int len;
a1c7c0f3
ILT		 1301 strcpy (buf,
1302 "invalid instruction for this architecture; needs ");
355afbcd
KR		 1303 cp = buf + strlen (buf);
1304 switch (ok_arch)
1305 {
1306 case mfloat:
82489ea0 1307 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
355afbcd
KR		 1308 break;
1309 case mmmu:
1310 strcpy (cp, "mmu (68030 or 68851)");
1311 break;
1312 case m68020up:
1313 strcpy (cp, "68020 or higher");
1314 break;
1315 case m68000up:
1316 strcpy (cp, "68000 or higher");
1317 break;
1318 case m68010up:
1319 strcpy (cp, "68010 or higher");
1320 break;
1321 default:
8be74775 1322 {
355afbcd 1323 int got_one = 0, idx;
a1c7c0f3
ILT		 1324 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1325 idx++)
8be74775 1326 {
355afbcd 1327 if (archs[idx].arch & ok_arch)
8be74775 1328 {
355afbcd
KR		 1329 if (got_one)
1330 {
1331 strcpy (cp, " or ");
1332 cp += strlen (cp);
1333 }
1334 got_one = 1;
1335 strcpy (cp, archs[idx].name);
8be74775
KR		 1336 cp += strlen (cp);
1337 }
8be74775
KR		 1338 }
1339 }
355afbcd
KR		 1340 }
1341 len = cp - buf + 1;
1342 cp = malloc (len);
1343 strcpy (cp, buf);
1344 the_ins.error = cp;
8be74775 1345 }
355afbcd
KR		 1346 else
1347 the_ins.error = "operands mismatch";
1348 return;
1349 } /* Fell off the end */
6d27d3a2 1350
355afbcd
KR		 1351 losing = 0;
1352 }
6d27d3a2
KR		 1353
1354 /* now assemble it */
1355
355afbcd
KR		 1356 the_ins.args = opcode->m_operands;
1357 the_ins.numargs = opcode->m_opnum;
1358 the_ins.numo = opcode->m_codenum;
1359 the_ins.opcode[0] = getone (opcode);
1360 the_ins.opcode[1] = gettwo (opcode);
6d27d3a2 1361
355afbcd
KR		 1362 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1363 {
1364 /* This switch is a doozy.
6d27d3a2 1365 Watch the first step; its a big one! */
355afbcd
KR		 1366 switch (s[0])
1367 {
6d27d3a2 1368
355afbcd
KR		 1369 case '*':
1370 case '~':
1371 case '%':
1372 case ';':
1373 case '@':
1374 case '!':
1375 case '&':
1376 case '$':
1377 case '?':
1378 case '/':
1379 case '`':
1380#ifndef NO_68851
1381 case '|':
1382#endif
1383 switch (opP->mode)
1384 {
1385 case IMMED:
1386 tmpreg = 0x3c; /* 7.4 */
1387 if (strchr ("bwl", s[1]))
a1c7c0f3 1388 nextword = get_num (&opP->disp, 80);
355afbcd 1389 else
a1c7c0f3
ILT		 1390 nextword = get_num (&opP->disp, 0);
1391 if (isvar (&opP->disp))
1392 add_fix (s[1], &opP->disp, 0, 0);
355afbcd
KR		 1393 switch (s[1])
1394 {
1395 case 'b':
1396 if (!isbyte (nextword))
1397 opP->error = "operand out of range";
1398 addword (nextword);
1399 baseo = 0;
1400 break;
1401 case 'w':
1402 if (!isword (nextword))
1403 opP->error = "operand out of range";
1404 addword (nextword);
1405 baseo = 0;
1406 break;
1407 case 'l':
1408 addword (nextword >> 16);
1409 addword (nextword);
1410 baseo = 0;
1411 break;
1412
1413 case 'f':
1414 baseo = 2;
1415 outro = 8;
1416 break;
1417 case 'F':
1418 baseo = 4;
1419 outro = 11;
1420 break;
1421 case 'x':
1422 baseo = 6;
1423 outro = 15;
1424 break;
1425 case 'p':
1426 baseo = 6;
1427 outro = -1;
1428 break;
1429 default:
a1c7c0f3 1430 abort ();
355afbcd
KR		 1431 }
1432 if (!baseo)
1433 break;
6d27d3a2 1434
355afbcd 1435 /* We gotta put out some float */
a1c7c0f3 1436 if (op (&opP->disp) != O_big)
355afbcd 1437 {
bcb8dff8
KR		 1438 valueT val;
1439 int gencnt;
1440
1441 /* Can other cases happen here? */
a1c7c0f3 1442 if (op (&opP->disp) != O_constant)
bcb8dff8 1443 abort ();
82489ea0 1444
a1c7c0f3 1445 val = (valueT) offs (&opP->disp);
bcb8dff8
KR		 1446 gencnt = 0;
1447 do
1448 {
1449 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1450 val >>= LITTLENUM_NUMBER_OF_BITS;
1451 ++gencnt;
1452 }
1453 while (val != 0);
a1c7c0f3 1454 offs (&opP->disp) = gencnt;
355afbcd 1455 }
a1c7c0f3 1456 if (offs (&opP->disp) > 0)
355afbcd 1457 {
a1c7c0f3 1458 if (offs (&opP->disp) > baseo)
355afbcd 1459 {
a1c7c0f3
ILT		 1460 as_warn ("Bignum too big for %c format; truncated",
1461 s[1]);
1462 offs (&opP->disp) = baseo;
355afbcd 1463 }
a1c7c0f3 1464 baseo -= offs (&opP->disp);
355afbcd
KR		 1465 while (baseo--)
1466 addword (0);
a1c7c0f3
ILT		 1467 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1468 offs (&opP->disp)--;
1469 --wordp)
bcb8dff8 1470 addword (*wordp);
355afbcd
KR		 1471 break;
1472 }
1473 gen_to_words (words, baseo, (long) outro);
1474 for (wordp = words; baseo--; wordp++)
1475 addword (*wordp);
1476 break;
1477 case DREG:
1478 tmpreg = opP->reg - DATA; /* 0.dreg */
1479 break;
1480 case AREG:
1481 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1482 break;
1483 case AINDR:
1484 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1485 break;
1486 case ADEC:
1487 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1488 break;
1489 case AINC:
1490 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1491 break;
a1c7c0f3 1492 case DISP:
6d27d3a2 1493
a1c7c0f3 1494 nextword = get_num (&opP->disp, 80);
6700d36e
ILT		 1495
1496 if (opP->reg == PC
1497 && ! isvar (&opP->disp)
1498 && m68k_abspcadd)
1499 {
1500 opP->disp.exp.X_op = O_symbol;
1501#ifndef BFD_ASSEMBLER
1502 opP->disp.exp.X_add_symbol = &abs_symbol;
1503#else
1504 opP->disp.exp.X_add_symbol =
1505 section_symbol (absolute_section);
1506#endif
1507 }
1508
355afbcd 1509 /* Force into index mode. Hope this works */
6d27d3a2 1510
1404ef23
KR		 1511 /* We do the first bit for 32-bit displacements, and the
1512 second bit for 16 bit ones. It is possible that we
1513 should make the default be WORD instead of LONG, but
1514 I think that'd break GCC, so we put up with a little
1515 inefficiency for the sake of working output. */
6d27d3a2 1516
355afbcd 1517 if (!issword (nextword)
a1c7c0f3
ILT		 1518 || (isvar (&opP->disp)
1519 && ((opP->disp.size == SIZE_UNSPEC
b79de3a1
KR		 1520 && flag_short_refs == 0
1521 && cpu_of_arch (current_architecture) >= m68020)
a1c7c0f3 1522 || opP->disp.size == SIZE_LONG)))
355afbcd 1523 {
355afbcd
KR		 1524 if (opP->reg == PC)
1525 tmpreg = 0x3B; /* 7.3 */
1526 else
1527 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
a1c7c0f3 1528 if (isvar (&opP->disp))
355afbcd
KR		 1529 {
1530 if (opP->reg == PC)
1531 {
04ef74bb 1532#if 0
b80d39a0 1533 addword (0x0170);
a1c7c0f3 1534 add_fix ('l', &opP->disp, 1, 2);
b80d39a0 1535 addword (0), addword (0);
04ef74bb 1536#else
a1c7c0f3
ILT		 1537 add_frag (adds (&opP->disp),
1538 offs (&opP->disp),
04ef74bb
KR		 1539 TAB (PCLEA, SZ_UNDEF));
1540#endif
355afbcd
KR		 1541 break;
1542 }
1543 else
1544 {
1545 addword (0x0170);
a1c7c0f3 1546 add_fix ('l', &opP->disp, 0, 0);
355afbcd
KR		 1547 }
1548 }
1549 else
1550 addword (0x0170);
1551 addword (nextword >> 16);
1552 }
1553 else
1554 {
1555 if (opP->reg == PC)
1556 tmpreg = 0x3A; /* 7.2 */
1557 else
1558 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1559
a1c7c0f3 1560 if (isvar (&opP->disp))
355afbcd
KR		 1561 {
1562 if (opP->reg == PC)
1563 {
a1c7c0f3 1564 add_fix ('w', &opP->disp, 1, 0);
355afbcd
KR		 1565 }
1566 else
a1c7c0f3 1567 add_fix ('w', &opP->disp, 0, 0);
355afbcd
KR		 1568 }
1569 }
1570 addword (nextword);
6d27d3a2 1571 break;
6d27d3a2 1572
a1c7c0f3
ILT		 1573 case POST:
1574 case PRE:
1575 case BASE:
355afbcd 1576 nextword = 0;
a1c7c0f3
ILT		 1577 baseo = get_num (&opP->disp, 80);
1578 if (opP->mode == POST || opP->mode == PRE)
1579 outro = get_num (&opP->odisp, 80);
49864cfa
KR		 1580 /* Figure out the `addressing mode'.
1581 Also turn on the BASE_DISABLE bit, if needed. */
355afbcd
KR		 1582 if (opP->reg == PC || opP->reg == ZPC)
1583 {
a1c7c0f3 1584 tmpreg = 0x3b; /* 7.3 */
355afbcd
KR		 1585 if (opP->reg == ZPC)
1586 nextword |= 0x80;
1587 }
a1c7c0f3
ILT		 1588 else if (opP->reg == 0)
1589 {
1590 nextword |= 0x80;
1591 tmpreg = 0x30; /* 6.garbage */
1592 }
1593 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
355afbcd
KR		 1594 {
1595 nextword |= 0x80;
a1c7c0f3 1596 tmpreg = 0x30 + opP->reg - ZADDR0;
355afbcd
KR		 1597 }
1598 else
1599 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1600
a1c7c0f3
ILT		 1601 siz1 = opP->disp.size;
1602 if (opP->mode == POST || opP->mode == PRE)
1603 siz2 = opP->odisp.size;
1604 else
1605 siz2 = SIZE_UNSPEC;
355afbcd
KR		 1606
1607 /* Index register stuff */
a1c7c0f3
ILT		 1608 if (opP->index.reg != 0
1609 && opP->index.reg >= DATA
1610 && opP->index.reg <= ADDR7)
355afbcd 1611 {
a1c7c0f3 1612 nextword |= (opP->index.reg - DATA) << 12;
355afbcd 1613
a1c7c0f3
ILT		 1614 if (opP->index.size == SIZE_UNSPEC
1615 || opP->index.size == SIZE_LONG)
355afbcd 1616 nextword |= 0x800;
a1c7c0f3
ILT		 1617
1618 if (cpu_of_arch (current_architecture) < m68020)
1619 {
1620 if (opP->index.scale != 1)
1621 {
1622 opP->error =
1623 "scale factor invalid on this architecture; needs 68020 or higher";
1624 }
1625 }
1626
1627 switch (opP->index.scale)
355afbcd
KR		 1628 {
1629 case 1:
1630 break;
1631 case 2:
1632 nextword |= 0x200;
1633 break;
1634 case 4:
1635 nextword |= 0x400;
1636 break;
1637 case 8:
1638 nextword |= 0x600;
1639 break;
1640 default:
a1c7c0f3 1641 abort ();
355afbcd
KR		 1642 }
1643 /* IF its simple,
49864cfa 1644 GET US OUT OF HERE! */
6d27d3a2 1645
04ef74bb
KR		 1646 /* Must be INDEX, with an index register. Address
1647 register cannot be ZERO-PC, and either :b was
1648 forced, or we know it will fit. For a 68000 or
1649 68010, force this mode anyways, because the
1650 larger modes aren't supported. */
a1c7c0f3
ILT		 1651 if (opP->mode == BASE
1652 && ((opP->reg >= ADDR0
1653 && opP->reg <= ADDR7)
1654 || opP->reg == PC))
355afbcd 1655 {
a1c7c0f3
ILT		 1656 if (siz1 == SIZE_BYTE
1657 || cpu_of_arch (current_architecture) < m68020
1658 || (siz1 == SIZE_UNSPEC
1659 && ! isvar (&opP->disp)
1660 && issbyte (baseo)))
1661 {
5f8cb05e
ILT		 1662 nextword += baseo & 0xff;
1663 addword (nextword);
a1c7c0f3 1664 if (isvar (&opP->disp))
04ef74bb 1665 {
a1c7c0f3
ILT		 1666 /* Do a byte relocation. If it doesn't
1667 fit (possible on m68000) let the
1668 fixup processing complain later. */
5f8cb05e 1669 if (opP->reg == PC)
a1c7c0f3 1670 add_fix ('B', &opP->disp, 1, 1);
5f8cb05e 1671 else
a1c7c0f3 1672 add_fix ('B', &opP->disp, 0, 0);
04ef74bb 1673 }
a1c7c0f3
ILT		 1674 else if (siz1 != SIZE_BYTE)
1675 {
1676 if (siz1 != SIZE_UNSPEC)
1677 as_warn ("Forcing byte displacement");
1678 if (! issbyte (baseo))
1679 opP->error = "byte displacement out of range";
1680 }
1681
1682 break;
1683 }
1684 else if (siz1 == SIZE_UNSPEC
1685 && opP->reg == PC
1686 && isvar (&opP->disp)
1687 && subs (&opP->disp) == NULL)
1688 {
5f8cb05e
ILT		 1689 nextword += baseo & 0xff;
1690 addword (nextword);
a1c7c0f3 1691 add_frag (adds (&opP->disp), offs (&opP->disp),
5f8cb05e 1692 TAB (PCINDEX, SZ_UNDEF));
a1c7c0f3
ILT		 1693
1694 break;
5f8cb05e 1695 }
355afbcd
KR		 1696 }
1697 }
1698 else
a1c7c0f3
ILT		 1699 {
1700 nextword |= 0x40; /* No index reg */
1701 if (opP->index.reg >= ZDATA0
1702 && opP->index.reg <= ZDATA7)
1703 nextword |= (opP->index.reg - ZDATA0) << 12;
1704 else if (opP->index.reg >= ZADDR0
1705 || opP->index.reg <= ZADDR7)
1706 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
1707 }
6d27d3a2 1708
49864cfa 1709 /* It isn't simple. */
a1c7c0f3
ILT		 1710
1711 if (cpu_of_arch (current_architecture) < m68020)
1712 opP->error =
1713 "invalid operand mode for this architecture; needs 68020 or higher";
1714
355afbcd 1715 nextword |= 0x100;
49864cfa
KR		 1716 /* If the guy specified a width, we assume that it is
1717 wide enough. Maybe it isn't. If so, we lose. */
355afbcd
KR		 1718 switch (siz1)
1719 {
a1c7c0f3 1720 case SIZE_UNSPEC:
6700d36e
ILT		 1721 if (isvar (&opP->disp)
1722 ? m68k_rel32
1723 : ! issword (baseo))
355afbcd 1724 {
a1c7c0f3 1725 siz1 = SIZE_LONG;
355afbcd
KR		 1726 nextword |= 0x30;
1727 }
6700d36e 1728 else if (! isvar (&opP->disp) && baseo == 0)
355afbcd
KR		 1729 nextword |= 0x10;
1730 else
1731 {
1732 nextword |= 0x20;
a1c7c0f3 1733 siz1 = SIZE_WORD;
355afbcd
KR		 1734 }
1735 break;
a1c7c0f3
ILT		 1736 case SIZE_BYTE:
1737 as_warn (":b not permitted; defaulting to :w");
1738 /* Fall through. */
1739 case SIZE_WORD:
355afbcd
KR		 1740 nextword |= 0x20;
1741 break;
a1c7c0f3 1742 case SIZE_LONG:
355afbcd
KR		 1743 nextword |= 0x30;
1744 break;
1745 }
6d27d3a2 1746
355afbcd 1747 /* Figure out innner displacement stuff */
a1c7c0f3 1748 if (opP->mode == POST || opP->mode == PRE)
355afbcd
KR		 1749 {
1750 switch (siz2)
1751 {
a1c7c0f3 1752 case SIZE_UNSPEC:
6700d36e
ILT		 1753 if (isvar (&opP->odisp)
1754 ? m68k_rel32
1755 : ! issword (outro))
355afbcd 1756 {
a1c7c0f3 1757 siz2 = SIZE_LONG;
355afbcd
KR		 1758 nextword |= 0x3;
1759 }
6700d36e 1760 else if (! isvar (&opP->disp) && outro == 0)
355afbcd
KR		 1761 nextword |= 0x1;
1762 else
1763 {
1764 nextword |= 0x2;
a1c7c0f3 1765 siz2 = SIZE_WORD;
355afbcd
KR		 1766 }
1767 break;
1768 case 1:
a1c7c0f3
ILT		 1769 as_warn (":b not permitted; defaulting to :w");
1770 /* Fall through. */
355afbcd
KR		 1771 case 2:
1772 nextword |= 0x2;
1773 break;
1774 case 3:
1775 nextword |= 0x3;
1776 break;
1777 }
a1c7c0f3 1778 if (opP->mode == POST)
355afbcd 1779 nextword |= 0x04;
355afbcd
KR		 1780 }
1781 addword (nextword);
1782
a1c7c0f3 1783 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
355afbcd
KR		 1784 {
1785 if (opP->reg == PC || opP->reg == ZPC)
a1c7c0f3 1786 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
355afbcd 1787 else
a1c7c0f3 1788 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
355afbcd 1789 }
a1c7c0f3 1790 if (siz1 == SIZE_LONG)
355afbcd 1791 addword (baseo >> 16);
a1c7c0f3 1792 if (siz1 != SIZE_UNSPEC)
355afbcd
KR		 1793 addword (baseo);
1794
a1c7c0f3
ILT		 1795 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
1796 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
1797 if (siz2 == SIZE_LONG)
355afbcd 1798 addword (outro >> 16);
a1c7c0f3 1799 if (siz2 != SIZE_UNSPEC)
355afbcd 1800 addword (outro);
6d27d3a2 1801
355afbcd 1802 break;
6d27d3a2 1803
355afbcd 1804 case ABSL:
a1c7c0f3
ILT		 1805 nextword = get_num (&opP->disp, 80);
1806 switch (opP->disp.size)
355afbcd
KR		 1807 {
1808 default:
a1c7c0f3
ILT		 1809 abort ();
1810 case SIZE_UNSPEC:
1811 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
355afbcd
KR		 1812 {
1813 tmpreg = 0x38; /* 7.0 */
1814 addword (nextword);
1815 break;
1816 }
bcb8dff8
KR		 1817 /* Don't generate pc relative code on 68010 and
1818 68000. */
a1c7c0f3
ILT		 1819 if (isvar (&opP->disp)
1820 && !subs (&opP->disp)
1821 && adds (&opP->disp)
1822 && (S_GET_SEGMENT (adds (&opP->disp)) == text_section)
49864cfa 1823 && now_seg == text_section
355afbcd 1824 && cpu_of_arch (current_architecture) >= m68020
9ad5755f 1825 && !flag_long_jumps
355afbcd
KR		 1826 && !strchr ("~%&$?", s[0]))
1827 {
1828 tmpreg = 0x3A; /* 7.2 */
a1c7c0f3
ILT		 1829 add_frag (adds (&opP->disp),
1830 offs (&opP->disp),
355afbcd
KR		 1831 TAB (PCREL, SZ_UNDEF));
1832 break;
1833 }
04ef74bb 1834 /* Fall through into long */
a1c7c0f3
ILT		 1835 case SIZE_LONG:
1836 if (isvar (&opP->disp))
1837 add_fix ('l', &opP->disp, 0, 0);
355afbcd
KR		 1838
1839 tmpreg = 0x39;/* 7.1 mode */
1840 addword (nextword >> 16);
1841 addword (nextword);
1842 break;
1843
a1c7c0f3
ILT		 1844 case SIZE_WORD: /* Word */
1845 if (isvar (&opP->disp))
1846 add_fix ('w', &opP->disp, 0, 0);
355afbcd
KR		 1847
1848 tmpreg = 0x38;/* 7.0 mode */
1849 addword (nextword);
1850 break;
1851 }
1852 break;
a1c7c0f3
ILT		 1853 case CONTROL:
1854 case FPREG:
355afbcd
KR		 1855 default:
1856 as_bad ("unknown/incorrect operand");
1857 /* abort(); */
1858 }
1859 install_gen_operand (s[1], tmpreg);
6d27d3a2 1860 break;
6d27d3a2 1861
355afbcd
KR		 1862 case '#':
1863 case '^':
1864 switch (s[1])
1865 { /* JF: I hate floating point! */
1866 case 'j':
1867 tmpreg = 70;
1868 break;
1869 case '8':
1870 tmpreg = 20;
1871 break;
1872 case 'C':
1873 tmpreg = 50;
1874 break;
1875 case '3':
1876 default:
1877 tmpreg = 80;
1878 break;
1879 }
a1c7c0f3
ILT		 1880 tmpreg = get_num (&opP->disp, tmpreg);
1881 if (isvar (&opP->disp))
1882 add_fix (s[1], &opP->disp, 0, 0);
355afbcd
KR		 1883 switch (s[1])
1884 {
1885 case 'b': /* Danger: These do no check for
6d27d3a2
KR		 1886 certain types of overflow.
1887 user beware! */
355afbcd
KR		 1888 if (!isbyte (tmpreg))
1889 opP->error = "out of range";
bcb8dff8 1890 insop (tmpreg, opcode);
a1c7c0f3 1891 if (isvar (&opP->disp))
355afbcd
KR		 1892 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1893 break;
1894 case 'w':
1895 if (!isword (tmpreg))
1896 opP->error = "out of range";
bcb8dff8 1897 insop (tmpreg, opcode);
a1c7c0f3 1898 if (isvar (&opP->disp))
355afbcd
KR		 1899 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1900 break;
1901 case 'l':
bcb8dff8
KR		 1902 /* Because of the way insop works, we put these two out
1903 backwards. */
1904 insop (tmpreg, opcode);
1905 insop (tmpreg >> 16, opcode);
a1c7c0f3 1906 if (isvar (&opP->disp))
355afbcd
KR		 1907 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1908 break;
1909 case '3':
1910 tmpreg &= 0xFF;
1911 case '8':
1912 case 'C':
1913 install_operand (s[1], tmpreg);
1914 break;
1915 default:
a1c7c0f3 1916 abort ();
355afbcd
KR		 1917 }
1918 break;
6d27d3a2 1919
355afbcd
KR		 1920 case '+':
1921 case '-':
1922 case 'A':
1923 case 'a':
1924 install_operand (s[1], opP->reg - ADDR);
1925 break;
6d27d3a2 1926
355afbcd 1927 case 'B':
a1c7c0f3 1928 tmpreg = get_num (&opP->disp, 80);
355afbcd
KR		 1929 switch (s[1])
1930 {
1931 case 'B':
b4ec75e0
ILT		 1932 /* The pc_fix argument winds up in fx_pcrel_adjust,
1933 which is a char, and may therefore be unsigned. We
1934 want to pass -1, but we pass 64 instead, and convert
1935 back in md_pcrel_from. */
1936 add_fix ('B', &opP->disp, 1, 64);
355afbcd
KR		 1937 break;
1938 case 'W':
a1c7c0f3 1939 add_fix ('w', &opP->disp, 1, 0);
355afbcd
KR		 1940 addword (0);
1941 break;
1942 case 'L':
1943 long_branch:
a1c7c0f3 1944 if (cpu_of_arch (current_architecture) < m68020)
355afbcd
KR		 1945 as_warn ("Can't use long branches on 68000/68010");
1946 the_ins.opcode[the_ins.numo - 1] |= 0xff;
a1c7c0f3 1947 add_fix ('l', &opP->disp, 1, 0);
355afbcd
KR		 1948 addword (0);
1949 addword (0);
1950 break;
1951 case 'g':
a1c7c0f3 1952 if (subs (&opP->disp)) /* We can't relax it */
355afbcd 1953 goto long_branch;
6d27d3a2 1954
a1c7c0f3
ILT		 1955 /* This could either be a symbol, or an absolute
1956 address. No matter, the frag hacking will finger it
1957 out. Not quite: it can't switch from BRANCH to
1958 BCC68000 for the case where opnd is absolute (it
1959 needs to use the 68000 hack since no conditional abs
1960 jumps). */
b79de3a1 1961 if (((cpu_of_arch (current_architecture) < m68020)
a1c7c0f3 1962 || (0 == adds (&opP->disp)))
355afbcd
KR		 1963 && (the_ins.opcode[0] >= 0x6200)
1964 && (the_ins.opcode[0] <= 0x6f00))
a1c7c0f3
ILT		 1965 add_frag (adds (&opP->disp), offs (&opP->disp),
1966 TAB (BCC68000, SZ_UNDEF));
355afbcd 1967 else
a1c7c0f3
ILT		 1968 add_frag (adds (&opP->disp), offs (&opP->disp),
1969 TAB (ABRANCH, SZ_UNDEF));
355afbcd
KR		 1970 break;
1971 case 'w':
a1c7c0f3 1972 if (isvar (&opP->disp))
355afbcd 1973 {
49864cfa 1974#if 1
355afbcd
KR		 1975 /* check for DBcc instruction */
1976 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
1977 {
1978 /* size varies if patch */
1979 /* needed for long form */
a1c7c0f3 1980 add_frag (adds (&opP->disp), offs (&opP->disp),
b79de3a1 1981 TAB (DBCC, SZ_UNDEF));
355afbcd
KR		 1982 break;
1983 }
49864cfa 1984#endif
a1c7c0f3 1985 add_fix ('w', &opP->disp, 1, 0);
355afbcd
KR		 1986 }
1987 addword (0);
1988 break;
1989 case 'C': /* Fixed size LONG coproc branches */
a1c7c0f3 1990 add_fix ('l', &opP->disp, 1, 0);
355afbcd
KR		 1991 addword (0);
1992 addword (0);
1993 break;
1994 case 'c': /* Var size Coprocesssor branches */
a1c7c0f3 1995 if (subs (&opP->disp))
355afbcd 1996 {
a1c7c0f3 1997 add_fix ('l', &opP->disp, 1, 0);
355afbcd
KR		 1998 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
1999 }
a1c7c0f3
ILT		 2000 else if (adds (&opP->disp))
2001 add_frag (adds (&opP->disp), offs (&opP->disp),
2002 TAB (FBRANCH, SZ_UNDEF));
355afbcd
KR		 2003 else
2004 {
a1c7c0f3
ILT		 2005 /* add_frag((symbolS *) 0, offs(&opP->disp),
2006 TAB(FBRANCH,SHORT)); */
355afbcd 2007 the_ins.opcode[the_ins.numo - 1] |= 0x40;
a1c7c0f3 2008 add_fix ('l', &opP->disp, 1, 0);
5f8cb05e 2009 addword (0);
355afbcd 2010 addword (0);
355afbcd
KR		 2011 }
2012 break;
2013 default:
a1c7c0f3 2014 abort ();
355afbcd
KR		 2015 }
2016 break;
6d27d3a2 2017
355afbcd
KR		 2018 case 'C': /* Ignore it */
2019 break;
6d27d3a2 2020
355afbcd 2021 case 'd': /* JF this is a kludge */
a1c7c0f3
ILT		 2022 install_operand ('s', opP->reg - ADDR);
2023 tmpreg = get_num (&opP->disp, 80);
355afbcd
KR		 2024 if (!issword (tmpreg))
2025 {
2026 as_warn ("Expression out of range, using 0");
2027 tmpreg = 0;
2028 }
2029 addword (tmpreg);
2030 break;
6d27d3a2 2031
355afbcd
KR		 2032 case 'D':
2033 install_operand (s[1], opP->reg - DATA);
2034 break;
6d27d3a2 2035
355afbcd 2036 case 'F':
a1c7c0f3 2037 install_operand (s[1], opP->reg - FP0);
355afbcd 2038 break;
6d27d3a2 2039
355afbcd 2040 case 'I':
27a53b88 2041 tmpreg = opP->reg - COP0;
355afbcd
KR		 2042 install_operand (s[1], tmpreg);
2043 break;
6d27d3a2 2044
355afbcd
KR		 2045 case 'J': /* JF foo */
2046 switch (opP->reg)
2047 {
2048 case SFC:
2049 tmpreg = 0x000;
2050 break;
2051 case DFC:
2052 tmpreg = 0x001;
2053 break;
2054 case CACR:
2055 tmpreg = 0x002;
2056 break;
2057 case TC:
2058 tmpreg = 0x003;
2059 break;
2060 case ITT0:
2061 tmpreg = 0x004;
2062 break;
2063 case ITT1:
2064 tmpreg = 0x005;
2065 break;
2066 case DTT0:
2067 tmpreg = 0x006;
2068 break;
2069 case DTT1:
2070 tmpreg = 0x007;
2071 break;
9ad5755f
KR		 2072 case BUSCR:
2073 tmpreg = 0x008;
2074 break;
6d27d3a2 2075
355afbcd
KR		 2076 case USP:
2077 tmpreg = 0x800;
2078 break;
2079 case VBR:
2080 tmpreg = 0x801;
2081 break;
2082 case CAAR:
2083 tmpreg = 0x802;
2084 break;
2085 case MSP:
2086 tmpreg = 0x803;
2087 break;
2088 case ISP:
2089 tmpreg = 0x804;
2090 break;
2091 case MMUSR:
2092 tmpreg = 0x805;
2093 break;
2094 case URP:
2095 tmpreg = 0x806;
2096 break;
2097 case SRP:
2098 tmpreg = 0x807;
2099 break;
9ad5755f
KR		 2100 case PCR:
2101 tmpreg = 0x808;
2102 break;
355afbcd 2103 default:
a1c7c0f3 2104 abort ();
355afbcd
KR		 2105 }
2106 install_operand (s[1], tmpreg);
2107 break;
6d27d3a2 2108
355afbcd 2109 case 'k':
a1c7c0f3 2110 tmpreg = get_num (&opP->disp, 55);
355afbcd
KR		 2111 install_operand (s[1], tmpreg & 0x7f);
2112 break;
6d27d3a2 2113
355afbcd 2114 case 'l':
a1c7c0f3 2115 tmpreg = opP->mask;
355afbcd
KR		 2116 if (s[1] == 'w')
2117 {
2118 if (tmpreg & 0x7FF0000)
2119 as_bad ("Floating point register in register list");
bcb8dff8 2120 insop (reverse_16_bits (tmpreg), opcode);
355afbcd
KR		 2121 }
2122 else
2123 {
2124 if (tmpreg & 0x700FFFF)
2125 as_bad ("Wrong register in floating-point reglist");
2126 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2127 }
2128 break;
6d27d3a2 2129
355afbcd 2130 case 'L':
a1c7c0f3 2131 tmpreg = opP->mask;
355afbcd
KR		 2132 if (s[1] == 'w')
2133 {
2134 if (tmpreg & 0x7FF0000)
2135 as_bad ("Floating point register in register list");
bcb8dff8 2136 insop (tmpreg, opcode);
355afbcd
KR		 2137 }
2138 else if (s[1] == '8')
2139 {
2140 if (tmpreg & 0x0FFFFFF)
2141 as_bad ("incorrect register in reglist");
2142 install_operand (s[1], tmpreg >> 24);
2143 }
2144 else
2145 {
2146 if (tmpreg & 0x700FFFF)
2147 as_bad ("wrong register in floating-point reglist");
2148 else
2149 install_operand (s[1], tmpreg >> 16);
2150 }
2151 break;
6d27d3a2 2152
355afbcd 2153 case 'M':
a1c7c0f3 2154 install_operand (s[1], get_num (&opP->disp, 60));
355afbcd 2155 break;
6d27d3a2 2156
355afbcd 2157 case 'O':
a1c7c0f3
ILT		 2158 tmpreg = ((opP->mode == DREG)
2159 ? 0x20 + opP->reg - DATA
2160 : (get_num (&opP->disp, 40) & 0x1F));
355afbcd
KR		 2161 install_operand (s[1], tmpreg);
2162 break;
6d27d3a2 2163
355afbcd 2164 case 'Q':
a1c7c0f3 2165 tmpreg = get_num (&opP->disp, 10);
355afbcd
KR		 2166 if (tmpreg == 8)
2167 tmpreg = 0;
2168 install_operand (s[1], tmpreg);
2169 break;
2170
2171 case 'R':
a1c7c0f3
ILT		 2172 /* This depends on the fact that ADDR registers are eight
2173 more than their corresponding DATA regs, so the result
2174 will have the ADDR_REG bit set */
355afbcd
KR		 2175 install_operand (s[1], opP->reg - DATA);
2176 break;
6d27d3a2 2177
a1c7c0f3
ILT		 2178 case 'r':
2179 if (opP->mode == AINDR)
2180 install_operand (s[1], opP->reg - DATA);
2181 else
2182 install_operand (s[1], opP->index.reg - DATA);
2183 break;
2184
355afbcd
KR		 2185 case 's':
2186 if (opP->reg == FPI)
2187 tmpreg = 0x1;
2188 else if (opP->reg == FPS)
2189 tmpreg = 0x2;
2190 else if (opP->reg == FPC)
2191 tmpreg = 0x4;
2192 else
a1c7c0f3 2193 abort ();
355afbcd
KR		 2194 install_operand (s[1], tmpreg);
2195 break;
6d27d3a2 2196
355afbcd
KR		 2197 case 'S': /* Ignore it */
2198 break;
6d27d3a2 2199
355afbcd 2200 case 'T':
a1c7c0f3 2201 install_operand (s[1], get_num (&opP->disp, 30));
355afbcd 2202 break;
6d27d3a2 2203
355afbcd
KR		 2204 case 'U': /* Ignore it */
2205 break;
6d27d3a2 2206
355afbcd
KR		 2207 case 'c':
2208 switch (opP->reg)
2209 {
2210 case NC:
2211 tmpreg = 0;
2212 break;
2213 case DC:
2214 tmpreg = 1;
2215 break;
2216 case IC:
2217 tmpreg = 2;
2218 break;
2219 case BC:
2220 tmpreg = 3;
2221 break;
2222 default:
2223 as_fatal ("failed sanity check");
2224 } /* switch on cache token */
2225 install_operand (s[1], tmpreg);
2226 break;
a39116f1 2227#ifndef NO_68851
355afbcd
KR		 2228 /* JF: These are out of order, I fear. */
2229 case 'f':
2230 switch (opP->reg)
2231 {
2232 case SFC:
2233 tmpreg = 0;
2234 break;
2235 case DFC:
2236 tmpreg = 1;
2237 break;
2238 default:
a1c7c0f3 2239 abort ();
355afbcd
KR		 2240 }
2241 install_operand (s[1], tmpreg);
2242 break;
6d27d3a2 2243
355afbcd
KR		 2244 case 'P':
2245 switch (opP->reg)
2246 {
2247 case TC:
2248 tmpreg = 0;
2249 break;
2250 case CAL:
2251 tmpreg = 4;
2252 break;
2253 case VAL:
2254 tmpreg = 5;
2255 break;
2256 case SCC:
2257 tmpreg = 6;
2258 break;
2259 case AC:
2260 tmpreg = 7;
2261 break;
2262 default:
a1c7c0f3 2263 abort ();
355afbcd
KR		 2264 }
2265 install_operand (s[1], tmpreg);
2266 break;
6d27d3a2 2267
355afbcd
KR		 2268 case 'V':
2269 if (opP->reg == VAL)
2270 break;
a1c7c0f3 2271 abort ();
6d27d3a2 2272
355afbcd
KR		 2273 case 'W':
2274 switch (opP->reg)
2275 {
355afbcd
KR		 2276 case DRP:
2277 tmpreg = 1;
2278 break;
2279 case SRP:
2280 tmpreg = 2;
2281 break;
2282 case CRP:
2283 tmpreg = 3;
2284 break;
2285 default:
a1c7c0f3 2286 abort ();
355afbcd
KR		 2287 }
2288 install_operand (s[1], tmpreg);
2289 break;
6d27d3a2 2290
355afbcd
KR		 2291 case 'X':
2292 switch (opP->reg)
2293 {
2294 case BAD:
2295 case BAD + 1:
2296 case BAD + 2:
2297 case BAD + 3:
2298 case BAD + 4:
2299 case BAD + 5:
2300 case BAD + 6:
2301 case BAD + 7:
2302 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2303 break;
6d27d3a2 2304
355afbcd
KR		 2305 case BAC:
2306 case BAC + 1:
2307 case BAC + 2:
2308 case BAC + 3:
2309 case BAC + 4:
2310 case BAC + 5:
2311 case BAC + 6:
2312 case BAC + 7:
2313 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2314 break;
6d27d3a2 2315
355afbcd 2316 default:
a1c7c0f3 2317 abort ();
355afbcd
KR		 2318 }
2319 install_operand (s[1], tmpreg);
2320 break;
2321 case 'Y':
2322 know (opP->reg == PSR);
2323 break;
2324 case 'Z':
2325 know (opP->reg == PCSR);
2326 break;
f8701a3f 2327#endif /* m68851 */
355afbcd
KR		 2328 case '3':
2329 switch (opP->reg)
2330 {
2331 case TT0:
2332 tmpreg = 2;
2333 break;
2334 case TT1:
2335 tmpreg = 3;
2336 break;
2337 default:
a1c7c0f3 2338 abort ();
355afbcd
KR		 2339 }
2340 install_operand (s[1], tmpreg);
2341 break;
2342 case 't':
a1c7c0f3 2343 tmpreg = get_num (&opP->disp, 20);
355afbcd 2344 install_operand (s[1], tmpreg);
4134a793 2345 break;
a1c7c0f3
ILT		 2346 case '_': /* used only for move16 absolute 32-bit address */
2347 tmpreg = get_num (&opP->disp, 80);
355afbcd
KR		 2348 addword (tmpreg >> 16);
2349 addword (tmpreg & 0xFFFF);
4134a793
KR		 2350 break;
2351 default:
a1c7c0f3 2352 abort ();
4134a793 2353 }
6d27d3a2 2354 }
3ad9ec6a 2355
6d27d3a2
KR		 2356 /* By the time whe get here (FINALLY) the_ins contains the complete
2357 instruction, ready to be emitted. . . */
a1c7c0f3 2358}
fecd2382 2359
355afbcd
KR		 2360static int
2361reverse_16_bits (in)
2362 int in;
fecd2382 2363{
355afbcd
KR		 2364 int out = 0;
2365 int n;
6d27d3a2 2366
355afbcd
KR		 2367 static int mask[16] =
2368 {
2369 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2370 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2371 };
2372 for (n = 0; n < 16; n++)
2373 {
2374 if (in & mask[n])
2375 out |= mask[15 - n];
2376 }
2377 return out;
2378} /* reverse_16_bits() */
fecd2382 2379
355afbcd
KR		 2380static int
2381reverse_8_bits (in)
2382 int in;
fecd2382 2383{
355afbcd
KR		 2384 int out = 0;
2385 int n;
6d27d3a2 2386
355afbcd
KR		 2387 static int mask[8] =
2388 {
2389 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2390 };
6d27d3a2 2391
355afbcd
KR		 2392 for (n = 0; n < 8; n++)
2393 {
2394 if (in & mask[n])
2395 out |= mask[7 - n];
2396 }
2397 return out;
2398} /* reverse_8_bits() */
fecd2382 2399
04ef74bb
KR		 2400/* Cause an extra frag to be generated here, inserting up to 10 bytes
2401 (that value is chosen in the frag_var call in md_assemble). TYPE
2402 is the subtype of the frag to be generated; its primary type is
2403 rs_machine_dependent.
2404
2405 The TYPE parameter is also used by md_convert_frag_1 and
2406 md_estimate_size_before_relax. The appropriate type of fixup will
2407 be emitted by md_convert_frag_1.
2408
2409 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
355afbcd
KR		 2410static void
2411install_operand (mode, val)
2412 int mode;
2413 int val;
fecd2382 2414{
355afbcd
KR		 2415 switch (mode)
2416 {
2417 case 's':
2418 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2419 break;
2420 case 'd':
2421 the_ins.opcode[0] |= val << 9;
2422 break;
2423 case '1':
2424 the_ins.opcode[1] |= val << 12;
2425 break;
2426 case '2':
2427 the_ins.opcode[1] |= val << 6;
2428 break;
2429 case '3':
2430 the_ins.opcode[1] |= val;
2431 break;
2432 case '4':
2433 the_ins.opcode[2] |= val << 12;
2434 break;
2435 case '5':
2436 the_ins.opcode[2] |= val << 6;
2437 break;
2438 case '6':
bcb8dff8
KR		 2439 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2440 three words long! */
355afbcd
KR		 2441 the_ins.numo++;
2442 the_ins.opcode[2] |= val;
2443 break;
2444 case '7':
2445 the_ins.opcode[1] |= val << 7;
2446 break;
2447 case '8':
2448 the_ins.opcode[1] |= val << 10;
2449 break;
f8701a3f 2450#ifndef NO_68851
355afbcd
KR		 2451 case '9':
2452 the_ins.opcode[1] |= val << 5;
2453 break;
f8701a3f 2454#endif
6d27d3a2 2455
355afbcd
KR		 2456 case 't':
2457 the_ins.opcode[1] |= (val << 10) | (val << 7);
2458 break;
2459 case 'D':
2460 the_ins.opcode[1] |= (val << 12) | val;
2461 break;
2462 case 'g':
2463 the_ins.opcode[0] |= val = 0xff;
2464 break;
2465 case 'i':
2466 the_ins.opcode[0] |= val << 9;
2467 break;
2468 case 'C':
2469 the_ins.opcode[1] |= val;
2470 break;
2471 case 'j':
2472 the_ins.opcode[1] |= val;
2473 the_ins.numo++; /* What a hack */
2474 break;
2475 case 'k':
2476 the_ins.opcode[1] |= val << 4;
2477 break;
2478 case 'b':
2479 case 'w':
2480 case 'l':
2481 break;
2482 case 'e':
2483 the_ins.opcode[0] |= (val << 6);
2484 break;
2485 case 'L':
2486 the_ins.opcode[1] = (val >> 16);
2487 the_ins.opcode[2] = val & 0xffff;
2488 break;
2489 case 'c':
2490 default:
2491 as_fatal ("failed sanity check.");
2492 }
2493} /* install_operand() */
fecd2382 2494
355afbcd
KR		 2495static void
2496install_gen_operand (mode, val)
2497 int mode;
2498 int val;
fecd2382 2499{
355afbcd
KR		 2500 switch (mode)
2501 {
2502 case 's':
2503 the_ins.opcode[0] |= val;
2504 break;
2505 case 'd':
2506 /* This is a kludge!!! */
2507 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2508 break;
2509 case 'b':
2510 case 'w':
2511 case 'l':
2512 case 'f':
2513 case 'F':
2514 case 'x':
2515 case 'p':
2516 the_ins.opcode[0] |= val;
2517 break;
2518 /* more stuff goes here */
2519 default:
2520 as_fatal ("failed sanity check.");
2521 }
2522} /* install_gen_operand() */
fecd2382 2523
7c15cbe8
RP		 2524/*
2525 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2526 * then deal with the bitfield hack.
2527 */
2528
355afbcd
KR		 2529static char *
2530crack_operand (str, opP)
2531 register char *str;
2532 register struct m68k_op *opP;
fecd2382 2533{
355afbcd
KR		 2534 register int parens;
2535 register int c;
2536 register char *beg_str;
6d27d3a2 2537
355afbcd
KR		 2538 if (!str)
2539 {
2540 return str;
2541 }
2542 beg_str = str;
2543 for (parens = 0; *str && (parens > 0 || notend (str)); str++)
2544 {
2545 if (*str == '(')
2546 parens++;
2547 else if (*str == ')')
2548 {
2549 if (!parens)
2550 { /* ERROR */
2551 opP->error = "Extra )";
2552 return str;
2553 }
2554 --parens;
f8701a3f 2555 }
355afbcd
KR		 2556 }
2557 if (!*str && parens)
2558 { /* ERROR */
2559 opP->error = "Missing )";
2560 return str;
2561 }
2562 c = *str;
2563 *str = '\0';
a1c7c0f3 2564 if (m68k_ip_op (beg_str, opP) != 0)
355afbcd
KR		 2565 {
2566 *str = c;
2567 return str;
2568 }
2569 *str = c;
2570 if (c == '}')
2571 c = *++str; /* JF bitfield hack */
2572 if (c)
2573 {
2574 c = *++str;
2575 if (!c)
2576 as_bad ("Missing operand");
2577 }
2578 return str;
fecd2382
RP		 2579}
2580
fecd2382 2581/* This is the guts of the machine-dependent assembler. STR points to a
7c15cbe8 2582 machine dependent instruction. This function is supposed to emit
fecd2382 2583 the frags/bytes it assembles to.
a39116f1 2584 */
a933d598
SC		 2585
2586void
355afbcd
KR		 2587insert_reg (regname, regnum)
2588 char *regname;
2589 int regnum;
a933d598
SC		 2590{
2591 char buf[100];
2592 int i;
355afbcd
KR		 2593
2594#ifdef REGISTER_PREFIX
82489ea0
KR		 2595 if (!flag_reg_prefix_optional)
2596 {
2597 buf[0] = REGISTER_PREFIX;
2598 strcpy (buf + 1, regname);
2599 regname = buf;
2600 }
355afbcd
KR		 2601#endif
2602
82489ea0
KR		 2603 symbol_table_insert (symbol_new (regname, reg_section, regnum,
2604 &zero_address_frag));
a933d598
SC		 2605
2606 for (i = 0; regname[i]; i++)
355afbcd 2607 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
a933d598 2608 buf[i] = '\0';
6d27d3a2 2609
82489ea0
KR		 2610 symbol_table_insert (symbol_new (buf, reg_section, regnum,
2611 &zero_address_frag));
a933d598
SC		 2612}
2613
49864cfa 2614struct init_entry
355afbcd 2615 {
bcb8dff8 2616 const char *name;
355afbcd 2617 int number;
49864cfa 2618 };
355afbcd 2619
bcb8dff8 2620static const struct init_entry init_table[] =
355afbcd 2621{
bcb8dff8
KR		 2622 { "d0", DATA0 },
2623 { "d1", DATA1 },
2624 { "d2", DATA2 },
2625 { "d3", DATA3 },
2626 { "d4", DATA4 },
2627 { "d5", DATA5 },
2628 { "d6", DATA6 },
2629 { "d7", DATA7 },
2630 { "a0", ADDR0 },
2631 { "a1", ADDR1 },
2632 { "a2", ADDR2 },
2633 { "a3", ADDR3 },
2634 { "a4", ADDR4 },
2635 { "a5", ADDR5 },
2636 { "a6", ADDR6 },
2637 { "fp", ADDR6 },
2638 { "a7", ADDR7 },
2639 { "sp", ADDR7 },
a1c7c0f3 2640 { "ssp", ADDR7 },
bcb8dff8
KR		 2641 { "fp0", FP0 },
2642 { "fp1", FP1 },
2643 { "fp2", FP2 },
2644 { "fp3", FP3 },
2645 { "fp4", FP4 },
2646 { "fp5", FP5 },
2647 { "fp6", FP6 },
2648 { "fp7", FP7 },
2649 { "fpi", FPI },
2650 { "fpiar", FPI },
2651 { "fpc", FPI },
2652 { "fps", FPS },
2653 { "fpsr", FPS },
2654 { "fpc", FPC },
2655 { "fpcr", FPC },
064ba683
ILT		 2656 { "control", FPC },
2657 { "status", FPS },
2658 { "iaddr", FPI },
bcb8dff8
KR		 2659
2660 { "cop0", COP0 },
2661 { "cop1", COP1 },
2662 { "cop2", COP2 },
2663 { "cop3", COP3 },
2664 { "cop4", COP4 },
2665 { "cop5", COP5 },
2666 { "cop6", COP6 },
2667 { "cop7", COP7 },
2668 { "pc", PC },
2669 { "zpc", ZPC },
2670 { "sr", SR },
2671
2672 { "ccr", CCR },
2673 { "cc", CCR },
2674
2675 { "usp", USP },
2676 { "isp", ISP },
2677 { "sfc", SFC },
064ba683 2678 { "sfcr", SFC },
bcb8dff8 2679 { "dfc", DFC },
064ba683 2680 { "dfcr", DFC },
bcb8dff8
KR		 2681 { "cacr", CACR },
2682 { "caar", CAAR },
2683
2684 { "vbr", VBR },
2685
2686 { "msp", MSP },
2687 { "itt0", ITT0 },
2688 { "itt1", ITT1 },
2689 { "dtt0", DTT0 },
2690 { "dtt1", DTT1 },
2691 { "mmusr", MMUSR },
2692 { "tc", TC },
2693 { "srp", SRP },
2694 { "urp", URP },
9ad5755f
KR		 2695 { "buscr", BUSCR },
2696 { "pcr", PCR },
bcb8dff8
KR		 2697
2698 { "ac", AC },
2699 { "bc", BC },
2700 { "cal", CAL },
2701 { "crp", CRP },
2702 { "drp", DRP },
2703 { "pcsr", PCSR },
2704 { "psr", PSR },
2705 { "scc", SCC },
2706 { "val", VAL },
2707 { "bad0", BAD0 },
2708 { "bad1", BAD1 },
2709 { "bad2", BAD2 },
2710 { "bad3", BAD3 },
2711 { "bad4", BAD4 },
2712 { "bad5", BAD5 },
2713 { "bad6", BAD6 },
2714 { "bad7", BAD7 },
2715 { "bac0", BAC0 },
2716 { "bac1", BAC1 },
2717 { "bac2", BAC2 },
2718 { "bac3", BAC3 },
2719 { "bac4", BAC4 },
2720 { "bac5", BAC5 },
2721 { "bac6", BAC6 },
2722 { "bac7", BAC7 },
2723
2724 { "ic", IC },
2725 { "dc", DC },
2726 { "nc", NC },
2727
2728 { "tt0", TT0 },
2729 { "tt1", TT1 },
4134a793 2730 /* 68ec030 versions of same */
bcb8dff8
KR		 2731 { "ac0", TT0 },
2732 { "ac1", TT1 },
4134a793 2733 /* 68ec030 access control unit, identical to 030 MMU status reg */
bcb8dff8 2734 { "acusr", PSR },
a933d598 2735
a1c7c0f3
ILT		 2736 /* Suppressed data and address registers. */
2737 { "zd0", ZDATA0 },
2738 { "zd1", ZDATA1 },
2739 { "zd2", ZDATA2 },
2740 { "zd3", ZDATA3 },
2741 { "zd4", ZDATA4 },
2742 { "zd5", ZDATA5 },
2743 { "zd6", ZDATA6 },
2744 { "zd7", ZDATA7 },
2745 { "za0", ZADDR0 },
2746 { "za1", ZADDR1 },
2747 { "za2", ZADDR2 },
2748 { "za3", ZADDR3 },
2749 { "za4", ZADDR4 },
2750 { "za5", ZADDR5 },
2751 { "za6", ZADDR6 },
2752 { "za7", ZADDR7 },
2753
bcb8dff8 2754 { 0, 0 }
a933d598
SC		 2755};
2756
a933d598 2757void
355afbcd 2758init_regtable ()
a933d598
SC		 2759{
2760 int i;
6d27d3a2 2761 for (i = 0; init_table[i].name; i++)
355afbcd 2762 insert_reg (init_table[i].name, init_table[i].number);
a933d598 2763}
6d27d3a2 2764
df3768fb 2765static int no_68851, no_68881;
a933d598 2766
dff60b7d
ILT		 2767#ifdef OBJ_AOUT
2768/* a.out machine type. Default to 68020. */
2769int m68k_aout_machtype = 2;
2770#endif
2771
fecd2382 2772void
355afbcd 2773md_assemble (str)
6d27d3a2 2774 char *str;
fecd2382 2775{
a1c7c0f3 2776 const char *er;
355afbcd
KR		 2777 short *fromP;
2778 char *toP = NULL;
2779 int m, n = 0;
2780 char *to_beg_P;
2781 int shorts_this_frag;
5f8cb05e 2782 fixS *fixP;
6d27d3a2 2783
e284846a 2784 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
355afbcd
KR		 2785 m68k_ip (str);
2786 er = the_ins.error;
2787 if (!er)
2788 {
a1c7c0f3 2789 for (n = 0; n < the_ins.numargs; n++)
355afbcd
KR		 2790 if (the_ins.operands[n].error)
2791 {
2792 er = the_ins.operands[n].error;
2793 break;
2794 }
2795 }
2796 if (er)
2797 {
2798 as_bad ("%s -- statement `%s' ignored", er, str);
2799 return;
2800 }
6d27d3a2 2801
355afbcd 2802 if (the_ins.nfrag == 0)
49864cfa
KR		 2803 {
2804 /* No frag hacking involved; just put it out */
355afbcd
KR		 2805 toP = frag_more (2 * the_ins.numo);
2806 fromP = &the_ins.opcode[0];
2807 for (m = the_ins.numo; m; --m)
2808 {
2809 md_number_to_chars (toP, (long) (*fromP), 2);
2810 toP += 2;
2811 fromP++;
f8701a3f 2812 }
355afbcd
KR		 2813 /* put out symbol-dependent info */
2814 for (m = 0; m < the_ins.nrel; m++)
2815 {
2816 switch (the_ins.reloc[m].wid)
2817 {
2818 case 'B':
2819 n = 1;
2820 break;
2821 case 'b':
2822 n = 1;
2823 break;
2824 case '3':
2825 n = 2;
2826 break;
2827 case 'w':
2828 n = 2;
2829 break;
2830 case 'l':
2831 n = 4;
2832 break;
2833 default:
49864cfa
KR		 2834 as_fatal ("Don't know how to figure width of %c in md_assemble()",
2835 the_ins.reloc[m].wid);
355afbcd 2836 }
6d27d3a2 2837
5f8cb05e
ILT		 2838 fixP = fix_new_exp (frag_now,
2839 ((toP - frag_now->fr_literal)
2840 - the_ins.numo * 2 + the_ins.reloc[m].n),
2841 n,
2842 &the_ins.reloc[m].exp,
2843 the_ins.reloc[m].pcrel,
2844 NO_RELOC);
2845 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
f8701a3f 2846 }
355afbcd
KR		 2847 return;
2848 }
2849
2850 /* There's some frag hacking */
2851 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
2852 {
2853 int wid;
2854
2855 if (n == 0)
2856 wid = 2 * the_ins.fragb[n].fragoff;
2857 else
2858 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2859 toP = frag_more (wid);
2860 to_beg_P = toP;
2861 shorts_this_frag = 0;
2862 for (m = wid / 2; m; --m)
2863 {
2864 md_number_to_chars (toP, (long) (*fromP), 2);
2865 toP += 2;
2866 fromP++;
2867 shorts_this_frag++;
2868 }
2869 for (m = 0; m < the_ins.nrel; m++)
2870 {
49864cfa 2871 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
355afbcd 2872 {
49864cfa 2873 the_ins.reloc[m].n -= 2 * shorts_this_frag;
355afbcd
KR		 2874 break;
2875 }
2876 wid = the_ins.reloc[m].wid;
2877 if (wid == 0)
2878 continue;
2879 the_ins.reloc[m].wid = 0;
2880 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
2881
5f8cb05e
ILT		 2882 fixP = fix_new_exp (frag_now,
2883 ((toP - frag_now->fr_literal)
2884 - the_ins.numo * 2 + the_ins.reloc[m].n),
2885 wid,
2886 &the_ins.reloc[m].exp,
2887 the_ins.reloc[m].pcrel,
2888 NO_RELOC);
2889 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
fecd2382 2890 }
49864cfa
KR		 2891 (void) frag_var (rs_machine_dependent, 10, 0,
2892 (relax_substateT) (the_ins.fragb[n].fragty),
2893 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
355afbcd
KR		 2894 }
2895 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2896 shorts_this_frag = 0;
2897 if (n)
2898 {
2899 toP = frag_more (n * sizeof (short));
2900 while (n--)
2901 {
2902 md_number_to_chars (toP, (long) (*fromP), 2);
2903 toP += 2;
2904 fromP++;
2905 shorts_this_frag++;
fecd2382 2906 }
355afbcd
KR		 2907 }
2908 for (m = 0; m < the_ins.nrel; m++)
2909 {
2910 int wid;
2911
2912 wid = the_ins.reloc[m].wid;
2913 if (wid == 0)
2914 continue;
2915 the_ins.reloc[m].wid = 0;
2916 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
2917
5f8cb05e
ILT		 2918 fixP = fix_new_exp (frag_now,
2919 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
2920 - shorts_this_frag * 2),
2921 wid,
2922 &the_ins.reloc[m].exp,
2923 the_ins.reloc[m].pcrel,
2924 NO_RELOC);
2925 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
355afbcd 2926 }
fecd2382
RP		 2927}
2928
fecd2382 2929void
355afbcd 2930md_begin ()
fecd2382 2931{
355afbcd 2932 /*
e284846a
KR		 2933 * md_begin -- set up hash tables with 68000 instructions.
2934 * similar to what the vax assembler does. ---phr
2935 */
355afbcd 2936 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
e284846a
KR		 2937 a copy of it at runtime, adding in the information we want but isn't
2938 there. I think it'd be better to have an awk script hack the table
2939 at compile time. Or even just xstr the table and use it as-is. But
2940 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
2941 names. */
6d27d3a2 2942
b79de3a1 2943 register const struct m68k_opcode *ins;
355afbcd 2944 register struct m68k_incant *hack, *slak;
bcb8dff8 2945 register const char *retval = 0; /* empty string, or error msg text */
355afbcd
KR		 2946 register unsigned int i;
2947 register char c;
2948
064ba683 2949 if (flag_mri)
6700d36e
ILT		 2950 {
2951 flag_reg_prefix_optional = 1;
2952 m68k_abspcadd = 1;
2953 m68k_rel32 = 0;
2954 }
064ba683 2955
82489ea0 2956 op_hash = hash_new ();
355afbcd
KR		 2957
2958 obstack_begin (&robyn, 4000);
a1c7c0f3 2959 for (i = 0; i < m68k_numopcodes; i++)
355afbcd
KR		 2960 {
2961 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
2962 do
2963 {
a1c7c0f3 2964 ins = &m68k_opcodes[i];
e284846a
KR		 2965 /* We *could* ignore insns that don't match our arch here
2966 but just leaving them out of the hash. */
355afbcd
KR		 2967 slak->m_operands = ins->args;
2968 slak->m_opnum = strlen (slak->m_operands) / 2;
2969 slak->m_arch = ins->arch;
2970 slak->m_opcode = ins->opcode;
2971 /* This is kludgey */
2972 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
a1c7c0f3
ILT		 2973 if (i + 1 != m68k_numopcodes
2974 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
355afbcd
KR		 2975 {
2976 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
e284846a 2977 i++;
355afbcd
KR		 2978 }
2979 else
2980 slak->m_next = 0;
2981 slak = slak->m_next;
f8701a3f 2982 }
355afbcd
KR		 2983 while (slak);
2984
2985 retval = hash_insert (op_hash, ins->name, (char *) hack);
dff60b7d 2986 if (retval)
b79de3a1
KR		 2987 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
2988 }
2989
a1c7c0f3 2990 for (i = 0; i < m68k_numaliases; i++)
b79de3a1
KR		 2991 {
2992 const char *name = m68k_opcode_aliases[i].primary;
2993 const char *alias = m68k_opcode_aliases[i].alias;
2994 PTR val = hash_find (op_hash, name);
2995 if (!val)
2996 as_fatal ("Internal Error: Can't find %s in hash table", name);
2997 retval = hash_insert (op_hash, alias, val);
2998 if (retval)
2999 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
355afbcd 3000 }
6d27d3a2 3001
6700d36e
ILT		 3002 /* In MRI mode, all unsized branches are variable sized. Normally,
3003 they are word sized. */
3004 if (flag_mri)
3005 {
3006 static struct m68k_opcode_alias mri_aliases[] =
3007 {
3008 { "bhi", "jhi", },
3009 { "bls", "jls", },
3010 { "bcc", "jcc", },
3011 { "bcs", "jcs", },
3012 { "bne", "jne", },
3013 { "beq", "jeq", },
3014 { "bvc", "jvc", },
3015 { "bvs", "jvs", },
3016 { "bpl", "jpl", },
3017 { "bmi", "jmi", },
3018 { "bge", "jge", },
3019 { "blt", "jlt", },
3020 { "bgt", "jgt", },
3021 { "ble", "jle", },
3022 { "bra", "jra", },
3023 { "bsr", "jbsr", },
3024 };
3025
3026 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3027 {
3028 const char *name = mri_aliases[i].primary;
3029 const char *alias = mri_aliases[i].alias;
3030 PTR val = hash_find (op_hash, name);
3031 if (!val)
3032 as_fatal ("Internal Error: Can't find %s in hash table", name);
3033 retval = hash_jam (op_hash, alias, val);
3034 if (retval)
3035 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3036 }
3037 }
3038
355afbcd
KR		 3039 for (i = 0; i < sizeof (mklower_table); i++)
3040 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
6d27d3a2 3041
355afbcd
KR		 3042 for (i = 0; i < sizeof (notend_table); i++)
3043 {
3044 notend_table[i] = 0;
3045 alt_notend_table[i] = 0;
3046 }
3047 notend_table[','] = 1;
3048 notend_table['{'] = 1;
3049 notend_table['}'] = 1;
3050 alt_notend_table['a'] = 1;
3051 alt_notend_table['A'] = 1;
3052 alt_notend_table['d'] = 1;
3053 alt_notend_table['D'] = 1;
3054 alt_notend_table['#'] = 1;
5f8cb05e 3055 alt_notend_table['&'] = 1;
355afbcd
KR		 3056 alt_notend_table['f'] = 1;
3057 alt_notend_table['F'] = 1;
fecd2382 3058#ifdef REGISTER_PREFIX
355afbcd 3059 alt_notend_table[REGISTER_PREFIX] = 1;
fecd2382 3060#endif
f8701a3f 3061
a1c7c0f3
ILT		 3062 /* We need to put '(' in alt_notend_table to handle
3063 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3064 */
3065 alt_notend_table['('] = 1;
3066
3067 /* We need to put '@' in alt_notend_table to handle
3068 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3069 */
3070 alt_notend_table['@'] = 1;
3071
3ad9ec6a 3072#ifndef MIT_SYNTAX_ONLY
355afbcd 3073 /* Insert pseudo ops, these have to go into the opcode table since
bcb8dff8 3074 gas expects pseudo ops to start with a dot */
355afbcd
KR		 3075 {
3076 int n = 0;
3077 while (mote_pseudo_table[n].poc_name)
3078 {
3079 hack = (struct m68k_incant *)
3080 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3081 hash_insert (op_hash,
3082 mote_pseudo_table[n].poc_name, (char *) hack);
3083 hack->m_operands = 0;
3084 hack->m_opnum = n;
3085 n++;
3086 }
3087 }
3ad9ec6a
ILT		 3088#endif
3089
355afbcd 3090 init_regtable ();
fecd2382
RP		 3091}
3092
82489ea0
KR		 3093void
3094m68k_init_after_args ()
3095{
3096 if (cpu_of_arch (current_architecture) == 0)
3097 {
064ba683 3098 int i;
b79de3a1 3099 const char *default_cpu = TARGET_CPU;
82489ea0 3100
b79de3a1
KR		 3101 if (*default_cpu == 'm')
3102 default_cpu++;
3103 for (i = 0; i < n_archs; i++)
e9bb39b4 3104 if (strcasecmp (default_cpu, archs[i].name) == 0)
b79de3a1
KR		 3105 break;
3106 if (i == n_archs)
3107 {
3108 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3109 current_architecture |= m68020;
3110 }
3111 else
3112 current_architecture |= archs[i].arch;
82489ea0 3113 }
b79de3a1
KR		 3114 /* Permit m68881 specification with all cpus; those that can't work
3115 with a coprocessor could be doing emulation. */
82489ea0
KR		 3116 if (current_architecture & m68851)
3117 {
3118 if (current_architecture & m68040)
3119 {
3120 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3121 }
3122 }
3123 /* What other incompatibilities could we check for? */
3124
3125 /* Toss in some default assumptions about coprocessors. */
3126 if (!no_68881
3127 && (cpu_of_arch (current_architecture)
3128 /* Can CPU32 have a 68881 coprocessor?? */
3129 & (m68020 | m68030 | cpu32)))
3130 {
3131 current_architecture |= m68881;
3132 }
3133 if (!no_68851
3134 && (cpu_of_arch (current_architecture) & m68020up) != 0
3135 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3136 {
3137 current_architecture |= m68851;
3138 }
3139 if (no_68881 && (current_architecture & m68881))
3140 as_bad ("options for 68881 and no-68881 both given");
3141 if (no_68851 && (current_architecture & m68851))
3142 as_bad ("options for 68851 and no-68851 both given");
3143
3144#ifdef OBJ_AOUT
3145 /* Work out the magic number. This isn't very general. */
3146 if (current_architecture & m68000)
3147 m68k_aout_machtype = 0;
3148 else if (current_architecture & m68010)
3149 m68k_aout_machtype = 1;
3150 else if (current_architecture & m68020)
3151 m68k_aout_machtype = 2;
3152 else
3153 m68k_aout_machtype = 2;
3154#endif
3155
3156 /* Note which set of "movec" control registers is available. */
3157 switch (cpu_of_arch (current_architecture))
3158 {
3159 case m68000:
3160 control_regs = m68000_control_regs;
3161 break;
3162 case m68010:
3163 control_regs = m68010_control_regs;
3164 break;
3165 case m68020:
3166 case m68030:
3167 control_regs = m68020_control_regs;
3168 break;
3169 case m68040:
3170 control_regs = m68040_control_regs;
3171 break;
3172 case m68060:
3173 control_regs = m68060_control_regs;
3174 break;
b79de3a1
KR		 3175 case cpu32:
3176 control_regs = cpu32_control_regs;
3177 break;
82489ea0
KR		 3178 default:
3179 abort ();
3180 }
04ef74bb
KR		 3181
3182 if (cpu_of_arch (current_architecture) < m68020)
3183 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
82489ea0
KR		 3184}
3185
fecd2382
RP		 3186/* Equal to MAX_PRECISION in atof-ieee.c */
3187#define MAX_LITTLENUMS 6
3188
a1c7c0f3
ILT		 3189/* Turn a string in input_line_pointer into a floating point constant
3190 of type type, and store the appropriate bytes in *litP. The number
3191 of LITTLENUMS emitted is stored in *sizeP . An error message is
3192 returned, or NULL on OK. */
3193
fecd2382 3194char *
355afbcd
KR		 3195md_atof (type, litP, sizeP)
3196 char type;
3197 char *litP;
3198 int *sizeP;
fecd2382 3199{
355afbcd
KR		 3200 int prec;
3201 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3202 LITTLENUM_TYPE *wordP;
3203 char *t;
3204 char *atof_ieee ();
6d27d3a2 3205
355afbcd
KR		 3206 switch (type)
3207 {
3208 case 'f':
3209 case 'F':
3210 case 's':
3211 case 'S':
3212 prec = 2;
3213 break;
6d27d3a2 3214
355afbcd
KR		 3215 case 'd':
3216 case 'D':
3217 case 'r':
3218 case 'R':
3219 prec = 4;
3220 break;
6d27d3a2 3221
355afbcd
KR		 3222 case 'x':
3223 case 'X':
3224 prec = 6;
3225 break;
6d27d3a2 3226
355afbcd
KR		 3227 case 'p':
3228 case 'P':
3229 prec = 6;
3230 break;
6d27d3a2 3231
355afbcd
KR		 3232 default:
3233 *sizeP = 0;
3234 return "Bad call to MD_ATOF()";
3235 }
3236 t = atof_ieee (input_line_pointer, type, words);
3237 if (t)
3238 input_line_pointer = t;
3239
3240 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3241 for (wordP = words; prec--;)
3242 {
3243 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3244 litP += sizeof (LITTLENUM_TYPE);
3245 }
49864cfa 3246 return 0;
fecd2382
RP		 3247}
3248
fecd2382 3249void
355afbcd
KR		 3250md_number_to_chars (buf, val, n)
3251 char *buf;
025b0302 3252 valueT val;
355afbcd 3253 int n;
fecd2382 3254{
82489ea0 3255 number_to_chars_bigendian (buf, val, n);
fecd2382
RP		 3256}
3257
49864cfa
KR		 3258static void
3259md_apply_fix_2 (fixP, val)
355afbcd 3260 fixS *fixP;
9ad5755f 3261 offsetT val;
fecd2382 3262{
9ad5755f
KR		 3263 addressT upper_limit;
3264 offsetT lower_limit;
49864cfa 3265
9ad5755f
KR		 3266 /* This is unnecessary but it convinces the native rs6000 compiler
3267 to generate the code we want. */
355afbcd
KR		 3268 char *buf = fixP->fx_frag->fr_literal;
3269 buf += fixP->fx_where;
9ad5755f
KR		 3270 /* end ibm compiler workaround */
3271
3272 if (val & 0x80000000)
3273 val |= ~(addressT)0x7fffffff;
3274 else
3275 val &= 0x7fffffff;
6d27d3a2 3276
355afbcd
KR		 3277 switch (fixP->fx_size)
3278 {
b79de3a1
KR		 3279 /* The cast to offsetT below are necessary to make code correct for
3280 machines where ints are smaller than offsetT */
355afbcd
KR		 3281 case 1:
3282 *buf++ = val;
49864cfa 3283 upper_limit = 0x7f;
b79de3a1 3284 lower_limit = - (offsetT) 0x80;
355afbcd
KR		 3285 break;
3286 case 2:
3287 *buf++ = (val >> 8);
3288 *buf++ = val;
49864cfa 3289 upper_limit = 0x7fff;
b79de3a1 3290 lower_limit = - (offsetT) 0x8000;
355afbcd
KR		 3291 break;
3292 case 4:
3293 *buf++ = (val >> 24);
3294 *buf++ = (val >> 16);
3295 *buf++ = (val >> 8);
3296 *buf++ = val;
49864cfa 3297 upper_limit = 0x7fffffff;
b79de3a1 3298 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
355afbcd
KR		 3299 break;
3300 default:
3301 BAD_CASE (fixP->fx_size);
3302 }
49864cfa
KR		 3303
3304 /* For non-pc-relative values, it's conceivable we might get something
3305 like "0xff" for a byte field. So extend the upper part of the range
3306 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3307 so that we can do any range checking at all. */
3308 if (!fixP->fx_pcrel)
3309 upper_limit = upper_limit * 2 + 1;
3310
9ad5755f
KR		 3311 if ((addressT) val > upper_limit
3312 && (val > 0 || val < lower_limit))
f3751617
ILT		 3313 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3314
3315 /* A one byte PC-relative reloc means a short branch. We can't use
3316 a short branch with a value of 0 or -1, because those indicate
3317 different opcodes (branches with longer offsets). */
3318 if (fixP->fx_pcrel
3319 && fixP->fx_size == 1
3320 && (fixP->fx_addsy == NULL
3321 || S_IS_DEFINED (fixP->fx_addsy))
3322 && (val == 0 || val == -1))
3323 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
fecd2382
RP		 3324}
3325
49864cfa
KR		 3326#ifdef BFD_ASSEMBLER
3327int
3328md_apply_fix (fixP, valp)
3329 fixS *fixP;
5f8cb05e 3330 valueT *valp;
49864cfa 3331{
9ad5755f 3332 md_apply_fix_2 (fixP, (addressT) *valp);
49864cfa
KR		 3333 return 1;
3334}
3335#else
3336void md_apply_fix (fixP, val)
3337 fixS *fixP;
3338 long val;
3339{
9ad5755f 3340 md_apply_fix_2 (fixP, (addressT) val);
49864cfa
KR		 3341}
3342#endif
fecd2382
RP		 3343
3344/* *fragP has been relaxed to its final size, and now needs to have
3345 the bytes inside it modified to conform to the new size There is UGLY
3346 MAGIC here. ..
a39116f1 3347 */
fecd2382 3348void
49864cfa 3349md_convert_frag_1 (fragP)
355afbcd 3350 register fragS *fragP;
fecd2382 3351{
355afbcd
KR		 3352 long disp;
3353 long ext = 0;
5f8cb05e 3354 fixS *fixP;
6d27d3a2 3355
355afbcd
KR		 3356 /* Address in object code of the displacement. */
3357 register int object_address = fragP->fr_fix + fragP->fr_address;
6d27d3a2 3358
9ad5755f
KR		 3359 /* Address in gas core of the place to store the displacement. */
3360 /* This convinces the native rs6000 compiler to generate the code we
3361 want. */
355afbcd
KR		 3362 register char *buffer_address = fragP->fr_literal;
3363 buffer_address += fragP->fr_fix;
9ad5755f 3364 /* end ibm compiler workaround */
6d27d3a2 3365
355afbcd
KR		 3366 /* The displacement of the address, from current location. */
3367 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3368 disp = (disp + fragP->fr_offset) - object_address;
6d27d3a2 3369
5f8cb05e
ILT		 3370#ifdef BFD_ASSEMBLER
3371 disp += fragP->fr_symbol->sy_frag->fr_address;
3372#endif
3373
355afbcd
KR		 3374 switch (fragP->fr_subtype)
3375 {
3376 case TAB (BCC68000, BYTE):
3377 case TAB (ABRANCH, BYTE):
3378 know (issbyte (disp));
3379 if (disp == 0)
3380 as_bad ("short branch with zero offset: use :w");
3381 fragP->fr_opcode[1] = disp;
3382 ext = 0;
3383 break;
3384 case TAB (DBCC, SHORT):
3385 know (issword (disp));
3386 ext = 2;
3387 break;
3388 case TAB (BCC68000, SHORT):
3389 case TAB (ABRANCH, SHORT):
3390 know (issword (disp));
3391 fragP->fr_opcode[1] = 0x00;
3392 ext = 2;
3393 break;
3394 case TAB (ABRANCH, LONG):
3395 if (cpu_of_arch (current_architecture) < m68020)
3396 {
3397 if (fragP->fr_opcode[0] == 0x61)
04ef74bb 3398 /* BSR */
355afbcd
KR		 3399 {
3400 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 3401 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
49864cfa 3402 subseg_change (text_section, 0); /* @@ */
355afbcd
KR		 3403
3404 fix_new (fragP,
3405 fragP->fr_fix,
3406 4,
3407 fragP->fr_symbol,
355afbcd
KR		 3408 fragP->fr_offset,
3409 0,
3410 NO_RELOC);
3411
3412 fragP->fr_fix += 4;
3413 ext = 0;
3414 }
04ef74bb 3415 /* BRA */
355afbcd
KR		 3416 else if (fragP->fr_opcode[0] == 0x60)
3417 {
3418 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 3419 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
49864cfa 3420 subseg_change (text_section, 0); /* @@ */
bcb8dff8
KR		 3421 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3422 fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 3423 fragP->fr_fix += 4;
3424 ext = 0;
3425 }
3426 else
3427 {
3428 as_bad ("Long branch offset not supported.");
3429 }
3430 }
3431 else
3432 {
bcb8dff8 3433 fragP->fr_opcode[1] = (char) 0xff;
355afbcd
KR		 3434 ext = 4;
3435 }
3436 break;
3437 case TAB (BCC68000, LONG):
3438 /* only Bcc 68000 instructions can come here */
3439 /* change bcc into b!cc/jmp absl long */
3440 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3441 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
6d27d3a2 3442
355afbcd 3443 /* JF: these used to be fr_opcode[2,3], but they may be in a
fecd2382
RP		 3444 different frag, in which case refering to them is a no-no.
3445 Only fr_opcode[0,1] are guaranteed to work. */
355afbcd 3446 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 3447 *buffer_address++ = (char) 0xf9;
355afbcd 3448 fragP->fr_fix += 2; /* account for jmp instruction */
49864cfa 3449 subseg_change (text_section, 0);
bcb8dff8
KR		 3450 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3451 fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 3452 fragP->fr_fix += 4;
3453 ext = 0;
3454 break;
3455 case TAB (DBCC, LONG):
3456 /* only DBcc 68000 instructions can come here */
3457 /* change dbcc into dbcc/jmp absl long */
3458 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3459 *buffer_address++ = 0x00; /* branch offset = 4 */
3460 *buffer_address++ = 0x04;
3461 *buffer_address++ = 0x60; /* put in bra pc+6 */
3462 *buffer_address++ = 0x06;
3463 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 3464 *buffer_address++ = (char) 0xf9;
355afbcd
KR		 3465
3466 fragP->fr_fix += 6; /* account for bra/jmp instructions */
49864cfa 3467 subseg_change (text_section, 0);
bcb8dff8 3468 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
49864cfa 3469 fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 3470 fragP->fr_fix += 4;
3471 ext = 0;
3472 break;
3473 case TAB (FBRANCH, SHORT):
3474 know ((fragP->fr_opcode[1] & 0x40) == 0);
3475 ext = 2;
3476 break;
3477 case TAB (FBRANCH, LONG):
3478 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3479 ext = 4;
3480 break;
3481 case TAB (PCREL, SHORT):
3482 ext = 2;
3483 break;
3484 case TAB (PCREL, LONG):
3485 /* The thing to do here is force it to ABSOLUTE LONG, since
f8701a3f 3486 PCREL is really trying to shorten an ABSOLUTE address anyway */
355afbcd 3487 /* JF FOO This code has not been tested */
49864cfa 3488 subseg_change (text_section, 0);
bcb8dff8 3489 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
49864cfa 3490 0, NO_RELOC);
355afbcd 3491 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
bcb8dff8
KR		 3492 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
3493 (unsigned) fragP->fr_opcode[0],
3494 (unsigned long) fragP->fr_address);
355afbcd
KR		 3495 fragP->fr_opcode[1] &= ~0x3F;
3496 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
3497 fragP->fr_fix += 4;
355afbcd
KR		 3498 ext = 0;
3499 break;
3500 case TAB (PCLEA, SHORT):
49864cfa
KR		 3501 subseg_change (text_section, 0);
3502 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
bcb8dff8 3503 fragP->fr_offset, 1, NO_RELOC);
355afbcd 3504 fragP->fr_opcode[1] &= ~0x3F;
04ef74bb 3505 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
355afbcd
KR		 3506 ext = 2;
3507 break;
3508 case TAB (PCLEA, LONG):
49864cfa 3509 subseg_change (text_section, 0);
5f8cb05e
ILT		 3510 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
3511 fragP->fr_offset, 1, NO_RELOC);
3512 fixP->fx_pcrel_adjust = 2;
04ef74bb
KR		 3513 /* Already set to mode 7.3; this indicates: PC indirect with
3514 suppressed index, 32-bit displacement. */
355afbcd
KR		 3515 *buffer_address++ = 0x01;
3516 *buffer_address++ = 0x70;
3517 fragP->fr_fix += 2;
355afbcd
KR		 3518 ext = 4;
3519 break;
04ef74bb
KR		 3520
3521 case TAB (PCINDEX, BYTE):
3522 disp += 2;
3523 if (!issbyte (disp))
3524 {
3525 as_bad ("displacement doesn't fit in one byte");
3526 disp = 0;
3527 }
5f8cb05e
ILT		 3528 assert (fragP->fr_fix >= 2);
3529 buffer_address[-2] &= ~1;
3530 buffer_address[-1] = disp;
04ef74bb
KR		 3531 ext = 0;
3532 break;
3533 case TAB (PCINDEX, SHORT):
3534 subseg_change (text_section, 0);
3535 disp += 2;
3536 assert (issword (disp));
5f8cb05e
ILT		 3537 assert (fragP->fr_fix >= 2);
3538 buffer_address[-2] |= 0x1;
3539 buffer_address[-1] = 0x20;
3540 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3541 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3542 NO_RELOC);
3543 fixP->fx_pcrel_adjust = 2;
04ef74bb
KR		 3544 ext = 2;
3545 break;
3546 case TAB (PCINDEX, LONG):
3547 subseg_change (text_section, 0);
3548 disp += 2;
5f8cb05e
ILT		 3549 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3550 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3551 NO_RELOC);
3552 fixP->fx_pcrel_adjust = 2;
3553 assert (fragP->fr_fix >= 2);
3554 buffer_address[-2] |= 0x1;
3555 buffer_address[-1] = 0x30;
04ef74bb
KR		 3556 ext = 4;
3557 break;
49864cfa 3558 }
355afbcd
KR		 3559
3560 if (ext)
3561 {
3562 md_number_to_chars (buffer_address, (long) disp, (int) ext);
3563 fragP->fr_fix += ext;
49864cfa
KR		 3564 }
3565}
355afbcd 3566
49864cfa
KR		 3567#ifndef BFD_ASSEMBLER
3568
3569void
064ba683 3570md_convert_frag (headers, sec, fragP)
49864cfa 3571 object_headers *headers;
064ba683 3572 segT sec;
49864cfa
KR		 3573 fragS *fragP;
3574{
3575 md_convert_frag_1 (fragP);
3576}
3577
3578#else
3579
3580void
3581md_convert_frag (abfd, sec, fragP)
3582 bfd *abfd;
5f8cb05e 3583 segT sec;
49864cfa
KR		 3584 fragS *fragP;
3585{
3586 md_convert_frag_1 (fragP);
3587}
3588#endif
355afbcd
KR		 3589
3590/* Force truly undefined symbols to their maximum size, and generally set up
3591 the frag list to be relaxed
3592 */
3593int
3594md_estimate_size_before_relax (fragP, segment)
3595 register fragS *fragP;
3596 segT segment;
3597{
3598 int old_fix;
3599 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3600
3601 old_fix = fragP->fr_fix;
3602
3603 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3604 switch (fragP->fr_subtype)
3605 {
3606
3607 case TAB (ABRANCH, SZ_UNDEF):
3608 {
3609 if ((fragP->fr_symbol != NULL) /* Not absolute */
3610 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3611 {
3612 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
3613 break;
3614 }
3615 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
3616 {
3617 /* On 68000, or for absolute value, switch to abs long */
3618 /* FIXME, we should check abs val, pick short or long */
3619 if (fragP->fr_opcode[0] == 0x61)
3620 {
3621 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 3622 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
49864cfa 3623 subseg_change (text_section, 0);
355afbcd 3624 fix_new (fragP, fragP->fr_fix, 4,
bcb8dff8 3625 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 3626 fragP->fr_fix += 4;
3627 frag_wane (fragP);
3628 }
3629 else if (fragP->fr_opcode[0] == 0x60)
3630 {
3631 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 3632 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
49864cfa 3633 subseg_change (text_section, 0);
355afbcd 3634 fix_new (fragP, fragP->fr_fix, 4,
bcb8dff8 3635 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 3636 fragP->fr_fix += 4;
3637 frag_wane (fragP);
3638 }
3639 else
3640 {
3641 as_warn ("Long branch offset to extern symbol not supported.");
3642 }
3643 }
3644 else
3645 { /* Symbol is still undefined. Make it simple */
3646 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5f8cb05e 3647 fragP->fr_offset, 1, NO_RELOC);
355afbcd 3648 fragP->fr_fix += 4;
bcb8dff8 3649 fragP->fr_opcode[1] = (char) 0xff;
355afbcd
KR		 3650 frag_wane (fragP);
3651 break;
3652 }
3653
a39116f1 3654 break;
355afbcd 3655 } /* case TAB(ABRANCH,SZ_UNDEF) */
6d27d3a2 3656
355afbcd
KR		 3657 case TAB (FBRANCH, SZ_UNDEF):
3658 {
9ad5755f 3659 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
355afbcd
KR		 3660 {
3661 fragP->fr_subtype = TAB (FBRANCH, SHORT);
3662 fragP->fr_var += 2;
3663 }
3664 else
3665 {
5f8cb05e
ILT		 3666 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
3667 fragP->fr_offset, 1, NO_RELOC);
3668 fragP->fr_fix += 4;
3669 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3670 frag_wane (fragP);
355afbcd
KR		 3671 }
3672 break;
3673 } /* TAB(FBRANCH,SZ_UNDEF) */
6d27d3a2 3674
355afbcd
KR		 3675 case TAB (PCREL, SZ_UNDEF):
3676 {
b79de3a1
KR		 3677 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3678 || flag_short_refs
3679 || cpu_of_arch (current_architecture) < m68020)
355afbcd
KR		 3680 {
3681 fragP->fr_subtype = TAB (PCREL, SHORT);
3682 fragP->fr_var += 2;
3683 }
3684 else
3685 {
3686 fragP->fr_subtype = TAB (PCREL, LONG);
3687 fragP->fr_var += 4;
3688 }
3689 break;
3690 } /* TAB(PCREL,SZ_UNDEF) */
6d27d3a2 3691
355afbcd
KR		 3692 case TAB (BCC68000, SZ_UNDEF):
3693 {
3694 if ((fragP->fr_symbol != NULL)
3695 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3696 {
3697 fragP->fr_subtype = TAB (BCC68000, BYTE);
3698 break;
3699 }
3700 /* only Bcc 68000 instructions can come here */
3701 /* change bcc into b!cc/jmp absl long */
3702 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
9ad5755f 3703 if (flag_short_refs)
355afbcd
KR		 3704 {
3705 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
3706 /* JF: these were fr_opcode[2,3] */
3707 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 3708 buffer_address[1] = (char) 0xf8;
355afbcd 3709 fragP->fr_fix += 2; /* account for jmp instruction */
49864cfa 3710 subseg_change (text_section, 0);
bcb8dff8 3711 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
355afbcd
KR		 3712 fragP->fr_offset, 0, NO_RELOC);
3713 fragP->fr_fix += 2;
3714 }
3715 else
3716 {
3717 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
3718 /* JF: these were fr_opcode[2,3] */
3719 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 3720 buffer_address[1] = (char) 0xf9;
355afbcd 3721 fragP->fr_fix += 2; /* account for jmp instruction */
49864cfa 3722 subseg_change (text_section, 0);
bcb8dff8 3723 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
355afbcd
KR		 3724 fragP->fr_offset, 0, NO_RELOC);
3725 fragP->fr_fix += 4;
3726 }
3727 frag_wane (fragP);
3728 break;
3729 } /* case TAB(BCC68000,SZ_UNDEF) */
f8701a3f 3730
355afbcd
KR		 3731 case TAB (DBCC, SZ_UNDEF):
3732 {
3733 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3734 {
3735 fragP->fr_subtype = TAB (DBCC, SHORT);
3736 fragP->fr_var += 2;
3737 break;
3738 }
3739 /* only DBcc 68000 instructions can come here */
3740 /* change dbcc into dbcc/jmp absl long */
3741 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3742 buffer_address[0] = 0x00; /* branch offset = 4 */
3743 buffer_address[1] = 0x04;
3744 buffer_address[2] = 0x60; /* put in bra pc + ... */
3745
9ad5755f 3746 if (flag_short_refs)
355afbcd
KR		 3747 {
3748 /* JF: these were fr_opcode[5-7] */
3749 buffer_address[3] = 0x04; /* plus 4 */
3750 buffer_address[4] = 0x4e; /* Put in Jump Word */
bcb8dff8 3751 buffer_address[5] = (char) 0xf8;
355afbcd 3752 fragP->fr_fix += 6; /* account for bra/jmp instruction */
49864cfa 3753 subseg_change (text_section, 0);
bcb8dff8 3754 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
355afbcd
KR		 3755 fragP->fr_offset, 0, NO_RELOC);
3756 fragP->fr_fix += 2;
3757 }
3758 else
3759 {
3760 /* JF: these were fr_opcode[5-7] */
3761 buffer_address[3] = 0x06; /* Plus 6 */
3762 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 3763 buffer_address[5] = (char) 0xf9;
355afbcd 3764 fragP->fr_fix += 6; /* account for bra/jmp instruction */
49864cfa 3765 subseg_change (text_section, 0);
bcb8dff8 3766 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
355afbcd
KR		 3767 fragP->fr_offset, 0, NO_RELOC);
3768 fragP->fr_fix += 4;
3769 }
6d27d3a2 3770
355afbcd
KR		 3771 frag_wane (fragP);
3772 break;
3773 } /* case TAB(DBCC,SZ_UNDEF) */
6d27d3a2 3774
355afbcd
KR		 3775 case TAB (PCLEA, SZ_UNDEF):
3776 {
b79de3a1
KR		 3777 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
3778 || flag_short_refs
3779 || cpu_of_arch (current_architecture) < m68020)
355afbcd
KR		 3780 {
3781 fragP->fr_subtype = TAB (PCLEA, SHORT);
3782 fragP->fr_var += 2;
3783 }
3784 else
3785 {
3786 fragP->fr_subtype = TAB (PCLEA, LONG);
3787 fragP->fr_var += 6;
3788 }
3789 break;
3790 } /* TAB(PCLEA,SZ_UNDEF) */
6d27d3a2 3791
04ef74bb
KR		 3792 case TAB (PCINDEX, SZ_UNDEF):
3793 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3794 || cpu_of_arch (current_architecture) < m68020)
3795 {
3796 fragP->fr_subtype = TAB (PCINDEX, BYTE);
3797 }
3798 else
3799 {
3800 fragP->fr_subtype = TAB (PCINDEX, LONG);
5f8cb05e 3801 fragP->fr_var += 4;
04ef74bb 3802 }
355afbcd 3803 break;
6d27d3a2 3804
04ef74bb
KR		 3805 default:
3806 break;
3807 }
6d27d3a2 3808
355afbcd
KR		 3809 /* now that SZ_UNDEF are taken care of, check others */
3810 switch (fragP->fr_subtype)
3811 {
3812 case TAB (BCC68000, BYTE):
3813 case TAB (ABRANCH, BYTE):
3814 /* We can't do a short jump to the next instruction,
a39116f1 3815 so we force word mode. */
355afbcd
KR		 3816 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 &&
3817 fragP->fr_symbol->sy_frag == fragP->fr_next)
3818 {
3819 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
3820 fragP->fr_var += 2;
fecd2382 3821 }
355afbcd
KR		 3822 break;
3823 default:
3824 break;
3825 }
3826 return fragP->fr_var + fragP->fr_fix - old_fix;
fecd2382
RP		 3827}
3828
3829#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
6d27d3a2 3830/* the bit-field entries in the relocation_info struct plays hell
fecd2382
RP		 3831 with the byte-order problems of cross-assembly. So as a hack,
3832 I added this mach. dependent ri twiddler. Ugly, but it gets
3833 you there. -KWK */
3834/* on m68k: first 4 bytes are normal unsigned long, next three bytes
a39116f1
RP		 3835 are symbolnum, most sig. byte first. Last byte is broken up with
3836 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3837 nibble as nuthin. (on Sun 3 at least) */
fecd2382
RP		 3838/* Translate the internal relocation information into target-specific
3839 format. */
a79c6033 3840#ifdef comment
fecd2382 3841void
355afbcd
KR		 3842md_ri_to_chars (the_bytes, ri)
3843 char *the_bytes;
3844 struct reloc_info_generic *ri;
fecd2382 3845{
355afbcd
KR		 3846 /* this is easy */
3847 md_number_to_chars (the_bytes, ri->r_address, 4);
3848 /* now the fun stuff */
3849 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
3850 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
3851 the_bytes[6] = ri->r_symbolnum & 0x0ff;
3852 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
3853 ((ri->r_extern << 4) & 0x10));
fecd2382 3854}
355afbcd 3855
a79c6033
RP		 3856#endif /* comment */
3857
49864cfa 3858#ifndef BFD_ASSEMBLER
355afbcd
KR		 3859void
3860tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
3861 char *where;
3862 fixS *fixP;
3863 relax_addressT segment_address_in_file;
a79c6033 3864{
355afbcd 3865 /*
1404ef23
KR		 3866 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3867 * Out: GNU LD relocation length code: 0, 1, or 2.
3868 */
6d27d3a2 3869
82489ea0 3870 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
355afbcd 3871 long r_symbolnum;
6d27d3a2 3872
355afbcd 3873 know (fixP->fx_addsy != NULL);
6d27d3a2 3874
355afbcd
KR		 3875 md_number_to_chars (where,
3876 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
3877 4);
6d27d3a2 3878
355afbcd
KR		 3879 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
3880 ? S_GET_TYPE (fixP->fx_addsy)
3881 : fixP->fx_addsy->sy_number);
6d27d3a2 3882
355afbcd
KR		 3883 where[4] = (r_symbolnum >> 16) & 0x0ff;
3884 where[5] = (r_symbolnum >> 8) & 0x0ff;
3885 where[6] = r_symbolnum & 0x0ff;
3886 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
3887 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
49864cfa
KR		 3888}
3889#endif
a79c6033 3890
fecd2382
RP		 3891#endif /* OBJ_AOUT or OBJ_BOUT */
3892
3893#ifndef WORKING_DOT_WORD
49864cfa
KR		 3894CONST int md_short_jump_size = 4;
3895CONST int md_long_jump_size = 6;
fecd2382
RP		 3896
3897void
355afbcd
KR		 3898md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
3899 char *ptr;
025b0302 3900 addressT from_addr, to_addr;
355afbcd
KR		 3901 fragS *frag;
3902 symbolS *to_symbol;
fecd2382 3903{
025b0302 3904 valueT offset;
6d27d3a2 3905
355afbcd 3906 offset = to_addr - (from_addr + 2);
6d27d3a2 3907
025b0302
ME		 3908 md_number_to_chars (ptr, (valueT) 0x6000, 2);
3909 md_number_to_chars (ptr + 2, (valueT) offset, 2);
fecd2382
RP		 3910}
3911
3912void
355afbcd
KR		 3913md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
3914 char *ptr;
025b0302 3915 addressT from_addr, to_addr;
355afbcd
KR		 3916 fragS *frag;
3917 symbolS *to_symbol;
fecd2382 3918{
025b0302 3919 valueT offset;
355afbcd
KR		 3920
3921 if (cpu_of_arch (current_architecture) < m68020)
3922 {
3923 offset = to_addr - S_GET_VALUE (to_symbol);
025b0302
ME		 3924 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
3925 md_number_to_chars (ptr + 2, (valueT) offset, 4);
bcb8dff8
KR		 3926 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
3927 0, NO_RELOC);
355afbcd
KR		 3928 }
3929 else
3930 {
3931 offset = to_addr - (from_addr + 2);
025b0302
ME		 3932 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
3933 md_number_to_chars (ptr + 2, (valueT) offset, 4);
355afbcd 3934 }
fecd2382
RP		 3935}
3936
3937#endif
a1c7c0f3
ILT		 3938
3939/* Different values of OK tell what its OK to return. Things that
3940 aren't OK are an error (what a shock, no?)
6d27d3a2 3941
a39116f1
RP		 3942 0: Everything is OK
3943 10: Absolute 1:8 only
3944 20: Absolute 0:7 only
3945 30: absolute 0:15 only
3946 40: Absolute 0:31 only
3947 50: absolute 0:127 only
3948 55: absolute -64:63 only
3949 60: absolute -128:127 only
3950 70: absolute 0:4095 only
3951 80: No bignums
6d27d3a2 3952
a39116f1 3953 */
fecd2382 3954
355afbcd
KR		 3955static int
3956get_num (exp, ok)
3957 struct m68k_exp *exp;
3958 int ok;
fecd2382 3959{
a1c7c0f3 3960 if (exp->exp.X_op == O_absent)
49864cfa 3961 {
355afbcd 3962 /* Do the same thing the VAX asm does */
bcb8dff8 3963 op (exp) = O_constant;
355afbcd
KR		 3964 adds (exp) = 0;
3965 subs (exp) = 0;
3966 offs (exp) = 0;
3967 if (ok == 10)
3968 {
3969 as_warn ("expression out of range: defaulting to 1");
3970 offs (exp) = 1;
3971 }
49864cfa 3972 }
a1c7c0f3 3973 else if (exp->exp.X_op == O_constant)
49864cfa 3974 {
355afbcd
KR		 3975 switch (ok)
3976 {
3977 case 10:
3978 if (offs (exp) < 1 || offs (exp) > 8)
3979 {
3980 as_warn ("expression out of range: defaulting to 1");
3981 offs (exp) = 1;
3982 }
3983 break;
3984 case 20:
3985 if (offs (exp) < 0 || offs (exp) > 7)
3986 goto outrange;
3987 break;
3988 case 30:
3989 if (offs (exp) < 0 || offs (exp) > 15)
3990 goto outrange;
3991 break;
3992 case 40:
3993 if (offs (exp) < 0 || offs (exp) > 32)
3994 goto outrange;
3995 break;
3996 case 50:
3997 if (offs (exp) < 0 || offs (exp) > 127)
3998 goto outrange;
3999 break;
4000 case 55:
4001 if (offs (exp) < -64 || offs (exp) > 63)
4002 goto outrange;
4003 break;
4004 case 60:
4005 if (offs (exp) < -128 || offs (exp) > 127)
4006 goto outrange;
4007 break;
4008 case 70:
4009 if (offs (exp) < 0 || offs (exp) > 4095)
4010 {
4011 outrange:
4012 as_warn ("expression out of range: defaulting to 0");
4013 offs (exp) = 0;
4014 }
4015 break;
fecd2382 4016 default:
355afbcd
KR		 4017 break;
4018 }
49864cfa 4019 }
a1c7c0f3 4020 else if (exp->exp.X_op == O_big)
49864cfa 4021 {
bcb8dff8 4022 if (offs (exp) <= 0 /* flonum */
355afbcd
KR		 4023 && (ok == 80 /* no bignums */
4024 || (ok > 10 /* small-int ranges including 0 ok */
1404ef23
KR		 4025 /* If we have a flonum zero, a zero integer should
4026 do as well (e.g., in moveq). */
355afbcd
KR		 4027 && generic_floating_point_number.exponent == 0
4028 && generic_floating_point_number.low[0] == 0)))
4029 {
4030 /* HACK! Turn it into a long */
4031 LITTLENUM_TYPE words[6];
4032
4033 gen_to_words (words, 2, 8L); /* These numbers are magic! */
bcb8dff8 4034 op (exp) = O_constant;
355afbcd
KR		 4035 adds (exp) = 0;
4036 subs (exp) = 0;
4037 offs (exp) = words[1] | (words[0] << 16);
4038 }
4039 else if (ok != 0)
4040 {
bcb8dff8 4041 op (exp) = O_constant;
355afbcd
KR		 4042 adds (exp) = 0;
4043 subs (exp) = 0;
4044 offs (exp) = (ok == 10) ? 1 : 0;
a1c7c0f3
ILT		 4045 as_warn ("Can't deal with expression; defaulting to %ld",
4046 offs (exp));
355afbcd 4047 }
49864cfa
KR		 4048 }
4049 else
4050 {
355afbcd
KR		 4051 if (ok >= 10 && ok <= 70)
4052 {
bcb8dff8 4053 op (exp) = O_constant;
355afbcd
KR		 4054 adds (exp) = 0;
4055 subs (exp) = 0;
4056 offs (exp) = (ok == 10) ? 1 : 0;
a1c7c0f3
ILT		 4057 as_warn ("Can't deal with expression; defaulting to %ld",
4058 offs (exp));
355afbcd 4059 }
355afbcd 4060 }
49864cfa 4061
a1c7c0f3 4062 if (exp->size != SIZE_UNSPEC)
355afbcd 4063 {
a1c7c0f3 4064 switch (exp->size)
355afbcd 4065 {
a1c7c0f3
ILT		 4066 case SIZE_UNSPEC:
4067 case SIZE_LONG:
4068 break;
4069 case SIZE_BYTE:
355afbcd
KR		 4070 if (!isbyte (offs (exp)))
4071 as_warn ("expression doesn't fit in BYTE");
4072 break;
a1c7c0f3 4073 case SIZE_WORD:
355afbcd
KR		 4074 if (!isword (offs (exp)))
4075 as_warn ("expression doesn't fit in WORD");
4076 break;
a39116f1 4077 }
355afbcd 4078 }
a1c7c0f3 4079
355afbcd 4080 return offs (exp);
49864cfa 4081}
fecd2382
RP		 4082
4083/* These are the back-ends for the various machine dependent pseudo-ops. */
355afbcd 4084void demand_empty_rest_of_line (); /* Hate those extra verbose names */
fecd2382 4085
355afbcd 4086static void
bcb8dff8
KR		 4087s_data1 (ignore)
4088 int ignore;
355afbcd 4089{
bcb8dff8 4090 subseg_set (data_section, 1);
355afbcd 4091 demand_empty_rest_of_line ();
49864cfa 4092}
fecd2382 4093
355afbcd 4094static void
bcb8dff8
KR		 4095s_data2 (ignore)
4096 int ignore;
355afbcd 4097{
bcb8dff8 4098 subseg_set (data_section, 2);
355afbcd 4099 demand_empty_rest_of_line ();
49864cfa 4100}
fecd2382 4101
355afbcd 4102static void
bcb8dff8
KR		 4103s_bss (ignore)
4104 int ignore;
a1765cf0 4105{
355afbcd 4106 /* We don't support putting frags in the BSS segment, we fake it
49864cfa 4107 by marking in_bss, then looking at s_skip for clues. */
a1765cf0 4108
bcb8dff8 4109 subseg_set (bss_section, 0);
355afbcd 4110 demand_empty_rest_of_line ();
49864cfa 4111}
6d27d3a2 4112
355afbcd 4113static void
bcb8dff8
KR		 4114s_even (ignore)
4115 int ignore;
355afbcd
KR		 4116{
4117 register int temp;
4118 register long temp_fill;
4119
4120 temp = 1; /* JF should be 2? */
4121 temp_fill = get_absolute_expression ();
4122 if (!need_pass_2) /* Never make frag if expect extra pass. */
4123 frag_align (temp, (int) temp_fill);
4124 demand_empty_rest_of_line ();
49864cfa 4125}
355afbcd
KR		 4126
4127static void
bcb8dff8
KR		 4128s_proc (ignore)
4129 int ignore;
355afbcd
KR		 4130{
4131 demand_empty_rest_of_line ();
49864cfa 4132}
e9bb39b4
ILT		 4133\f
4134/* Pseudo-ops handled for MRI compatibility. */
4135
4136/* Handle an MRI style chip specification. */
fecd2382 4137
e9bb39b4
ILT		 4138static void
4139mri_chip ()
4140{
4141 char *s;
4142 char c;
4143 int i;
4144
4145 s = input_line_pointer;
4146 c = get_symbol_end ();
4147 for (i = 0; i < n_archs; i++)
4148 if (strcasecmp (s, archs[i].name) == 0)
4149 break;
4150 if (i >= n_archs)
4151 {
4152 as_bad ("%s: unrecognized processor name", s);
4153 *input_line_pointer = c;
4154 ignore_rest_of_line ();
4155 return;
4156 }
4157 *input_line_pointer = c;
fecd2382 4158
e9bb39b4
ILT		 4159 if (*input_line_pointer == '/')
4160 current_architecture = 0;
4161 else
4162 current_architecture &= m68881 | m68851;
4163 current_architecture |= archs[i].arch;
4164
4165 while (*input_line_pointer == '/')
4166 {
4167 ++input_line_pointer;
4168 s = input_line_pointer;
4169 c = get_symbol_end ();
4170 if (strcmp (s, "68881") == 0)
4171 current_architecture |= m68881;
4172 else if (strcmp (s, "68851") == 0)
4173 current_architecture |= m68851;
4174 *input_line_pointer = c;
4175 }
4176}
4177
4178/* The MRI CHIP pseudo-op. */
4179
4180static void
4181s_chip (ignore)
4182 int ignore;
4183{
4184 mri_chip ();
4185 demand_empty_rest_of_line ();
4186}
27a53b88
ILT		 4187
4188/* The MRI FOPT pseudo-op. */
4189
4190static void
4191s_fopt (ignore)
4192 int ignore;
4193{
4194 SKIP_WHITESPACE ();
4195
4196 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4197 {
4198 int temp;
4199
4200 input_line_pointer += 3;
4201 temp = get_absolute_expression ();
4202 if (temp < 0 || temp > 7)
4203 as_bad ("bad coprocessor id");
4204 else
4205 m68k_float_copnum = COP0 + temp;
4206 }
4207 else
4208 {
4209 as_bad ("unrecognized fopt option");
4210 ignore_rest_of_line ();
4211 return;
4212 }
4213
4214 demand_empty_rest_of_line ();
4215}
6700d36e
ILT		 4216
4217/* The structure used to handle the MRI OPT pseudo-op. */
4218
4219struct opt_action
4220{
4221 /* The name of the option. */
4222 const char *name;
4223
4224 /* If this is not NULL, just call this function. The first argument
4225 is the ARG field of this structure, the second argument is
4226 whether the option was negated. */
4227 void (*pfn) PARAMS ((int arg, int on));
4228
4229 /* If this is not NULL, and the PFN field is NULL, set the variable
4230 this points to. Set it to the ARG field if the option was not
4231 negated, and the NOTARG field otherwise. */
4232 int *pvar;
4233
4234 /* The value to pass to PFN or to assign to *PVAR. */
4235 int arg;
4236
4237 /* The value to assign to *PVAR if the option is negated. If PFN is
4238 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4239 the option may not be negated. */
4240 int notarg;
4241};
4242
4243/* The table used to handle the MRI OPT pseudo-op. */
4244
4245static void skip_to_comma PARAMS ((int, int));
7e047ac2 4246static void opt_nest PARAMS ((int, int));
6700d36e
ILT		 4247static void opt_chip PARAMS ((int, int));
4248static void opt_list PARAMS ((int, int));
4249static void opt_list_symbols PARAMS ((int, int));
4250
4251static const struct opt_action opt_table[] =
4252{
4253 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4254
4255 /* We do relaxing, so there is little use for these options. */
4256 { "b", 0, 0, 0, 0 },
4257 { "brs", 0, 0, 0, 0 },
4258 { "brb", 0, 0, 0, 0 },
4259 { "brl", 0, 0, 0, 0 },
4260 { "brw", 0, 0, 0, 0 },
4261
4262 { "c", 0, 0, 0, 0 },
4263 { "cex", 0, 0, 0, 0 },
4264 { "case", 0, &symbols_case_sensitive, 1, 0 },
4265 { "cl", 0, 0, 0, 0 },
4266 { "cre", 0, 0, 0, 0 },
4267 { "d", 0, &flag_keep_locals, 1, 0 },
4268 { "e", 0, 0, 0, 0 },
4269 { "f", 0, &flag_short_refs, 1, 0 },
4270 { "frs", 0, &flag_short_refs, 1, 0 },
4271 { "frl", 0, &flag_short_refs, 0, 1 },
4272 { "g", 0, 0, 0, 0 },
4273 { "i", 0, 0, 0, 0 },
4274 { "m", 0, 0, 0, 0 },
4275 { "mex", 0, 0, 0, 0 },
4276 { "mc", 0, 0, 0, 0 },
4277 { "md", 0, 0, 0, 0 },
7e047ac2 4278 { "nest", opt_nest, 0, 0, 0 },
6700d36e
ILT		 4279 { "next", skip_to_comma, 0, 0, 0 },
4280 { "o", 0, 0, 0, 0 },
4281 { "old", 0, 0, 0, 0 },
4282 { "op", skip_to_comma, 0, 0, 0 },
4283 { "pco", 0, 0, 0, 0 },
4284 { "p", opt_chip, 0, 0, 0 },
4285 { "pcr", 0, 0, 0, 0 },
4286 { "pcs", 0, 0, 0, 0 },
4287 { "r", 0, 0, 0, 0 },
4288 { "quick", 0, &m68k_quick, 1, 0 },
4289 { "rel32", 0, &m68k_rel32, 1, 0 },
4290 { "s", opt_list, 0, 0, 0 },
4291 { "t", opt_list_symbols, 0, 0, 0 },
4292 { "w", 0, &flag_no_warnings, 0, 1 },
4293 { "x", 0, 0, 0, 0 }
4294};
4295
4296#define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
4297
4298/* The MRI OPT pseudo-op. */
4299
4300static void
4301s_opt (ignore)
4302 int ignore;
4303{
4304 do
4305 {
4306 int t;
4307 char *s;
4308 char c;
4309 int i;
4310 const struct opt_action *o;
4311
4312 SKIP_WHITESPACE ();
4313
4314 t = 1;
4315 if (*input_line_pointer == '-')
4316 {
4317 ++input_line_pointer;
4318 t = 0;
4319 }
4320 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
4321 {
4322 input_line_pointer += 2;
4323 t = 0;
4324 }
4325
4326 s = input_line_pointer;
4327 c = get_symbol_end ();
4328
4329 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
4330 {
4331 if (strcasecmp (s, o->name) == 0)
4332 {
4333 if (o->pfn)
4334 {
4335 /* Restore input_line_pointer now in case the option
4336 takes arguments. */
4337 *input_line_pointer = c;
4338 (*o->pfn) (o->arg, t);
4339 }
4340 else if (o->pvar != NULL)
4341 {
4342 if (! t && o->arg == o->notarg)
4343 as_bad ("option `%s' may not be negated", s);
4344 *input_line_pointer = c;
4345 *o->pvar = t ? o->arg : o->notarg;
4346 }
9bef2324
ILT		 4347 else
4348 *input_line_pointer = c;
6700d36e
ILT		 4349 break;
4350 }
4351 }
4352 if (i >= OPTCOUNT)
4353 {
4354 as_bad ("option `%s' not recognized", s);
4355 *input_line_pointer = c;
4356 }
4357 }
4358 while (*input_line_pointer++ == ',');
4359
4360 /* Move back to terminating character. */
4361 --input_line_pointer;
4362 demand_empty_rest_of_line ();
4363}
4364
4365/* Skip ahead to a comma. This is used for OPT options which we do
4366 not suppor tand which take arguments. */
4367
4368static void
4369skip_to_comma (arg, on)
4370 int arg;
4371 int on;
4372{
4373 while (*input_line_pointer != ','
4374 && ! is_end_of_line[(unsigned char) *input_line_pointer])
4375 ++input_line_pointer;
4376}
4377
7e047ac2
ILT		 4378/* Handle the OPT NEST=depth option. */
4379
4380static void
4381opt_nest (arg, on)
4382 int arg;
4383 int on;
4384{
4385 if (*input_line_pointer != '=')
4386 {
4387 as_bad ("bad format of OPT NEST=depth");
4388 return;
4389 }
4390
4391 ++input_line_pointer;
4392 max_macro_nest = get_absolute_expression ();
4393}
4394
6700d36e
ILT		 4395/* Handle the OPT P=chip option. */
4396
4397static void
4398opt_chip (arg, on)
4399 int arg;
4400 int on;
4401{
4402 if (*input_line_pointer != '=')
4403 {
4404 /* This is just OPT P, which we do not support. */
4405 return;
4406 }
4407
4408 ++input_line_pointer;
4409 mri_chip ();
4410}
4411
4412/* Handle the OPT S option. */
4413
4414static void
4415opt_list (arg, on)
4416 int arg;
4417 int on;
4418{
4419 listing_list (on);
4420}
4421
4422/* Handle the OPT T option. */
4423
4424static void
4425opt_list_symbols (arg, on)
4426 int arg;
4427 int on;
4428{
4429 if (on)
4430 listing |= LISTING_SYMBOLS;
4431 else
4432 listing &=~ LISTING_SYMBOLS;
4433}
4434
4435/* Handle the MRI REG pseudo-op. */
4436
4437static void
4438s_reg (ignore)
4439 int ignore;
4440{
4441 char *s;
4442 int c;
8e11ad0a 4443 struct m68k_op rop;
6700d36e
ILT		 4444 unsigned long mask;
4445
7e047ac2 4446 if (line_label == NULL)
6700d36e
ILT		 4447 {
4448 as_bad ("missing label");
4449 ignore_rest_of_line ();
4450 return;
4451 }
4452
4453 SKIP_WHITESPACE ();
4454
4455 s = input_line_pointer;
4456 while (isalnum ((unsigned char) *input_line_pointer)
4457#ifdef REGISTER_PREFIX
4458 || *input_line_pointer == REGISTER_PREFIX
4459#endif
4460 || *input_line_pointer == '/'
4461 || *input_line_pointer == '-')
4462 ++input_line_pointer;
4463 c = *input_line_pointer;
4464 *input_line_pointer = '\0';
4465
8e11ad0a 4466 if (m68k_ip_op (s, &rop) != 0)
6700d36e 4467 {
8e11ad0a 4468 if (rop.error == NULL)
6700d36e
ILT		 4469 as_bad ("bad register list");
4470 else
8e11ad0a 4471 as_bad ("bad register list: %s", rop.error);
6700d36e
ILT		 4472 *input_line_pointer = c;
4473 ignore_rest_of_line ();
4474 return;
4475 }
4476
4477 *input_line_pointer = c;
4478
8e11ad0a
ILT		 4479 if (rop.mode == REGLST)
4480 mask = rop.mask;
4481 else if (rop.mode == DREG)
4482 mask = 1 << (rop.reg - DATA0);
4483 else if (rop.mode == AREG)
4484 mask = 1 << (rop.reg - ADDR0 + 8);
4485 else if (rop.mode == FPREG)
4486 mask = 1 << (rop.reg - FP0 + 16);
4487 else if (rop.mode == CONTROL
4488 && rop.reg == FPI)
6700d36e 4489 mask = 1 << 24;
8e11ad0a
ILT		 4490 else if (rop.mode == CONTROL
4491 && rop.reg == FPS)
6700d36e 4492 mask = 1 << 25;
8e11ad0a
ILT		 4493 else if (rop.mode == CONTROL
4494 && rop.reg == FPC)
6700d36e
ILT		 4495 mask = 1 << 26;
4496 else
4497 {
4498 as_bad ("bad register list");
4499 ignore_rest_of_line ();
4500 return;
4501 }
4502
7e047ac2
ILT		 4503 S_SET_SEGMENT (line_label, absolute_section);
4504 S_SET_VALUE (line_label, mask);
4505 line_label->sy_frag = &zero_address_frag;
6700d36e
ILT		 4506
4507 demand_empty_rest_of_line ();
4508}
e14994d9
ILT		 4509
4510/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
4511
4512struct save_opts
4513{
4514 struct save_opts *next;
4515 int abspcadd;
4516 int symbols_case_sensitive;
4517 int keep_locals;
4518 int short_refs;
4519 int architecture;
4520 int quick;
4521 int rel32;
4522 int listing;
4523 int no_warnings;
4524 /* FIXME: We don't save OPT S. */
4525};
4526
4527/* This variable holds the stack of saved options. */
4528
4529static struct save_opts *save_stack;
4530
4531/* The MRI SAVE pseudo-op. */
4532
4533static void
4534s_save (ignore)
4535 int ignore;
4536{
4537 struct save_opts *s;
4538
4539 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
4540 s->abspcadd = m68k_abspcadd;
4541 s->symbols_case_sensitive = symbols_case_sensitive;
4542 s->keep_locals = flag_keep_locals;
4543 s->short_refs = flag_short_refs;
4544 s->architecture = current_architecture;
4545 s->quick = m68k_quick;
4546 s->rel32 = m68k_rel32;
4547 s->listing = listing;
4548 s->no_warnings = flag_no_warnings;
4549
4550 s->next = save_stack;
4551 save_stack = s;
4552
4553 demand_empty_rest_of_line ();
4554}
4555
4556/* The MRI RESTORE pseudo-op. */
4557
4558static void
4559s_restore (ignore)
4560 int ignore;
4561{
4562 struct save_opts *s;
4563
4564 if (save_stack == NULL)
4565 {
4566 as_bad ("restore without save");
4567 ignore_rest_of_line ();
4568 return;
4569 }
4570
4571 s = save_stack;
4572 save_stack = s->next;
4573
4574 m68k_abspcadd = s->abspcadd;
4575 symbols_case_sensitive = s->symbols_case_sensitive;
4576 flag_keep_locals = s->keep_locals;
4577 flag_short_refs = s->short_refs;
4578 current_architecture = s->architecture;
4579 m68k_quick = s->quick;
4580 m68k_rel32 = s->rel32;
4581 listing = s->listing;
4582 flag_no_warnings = s->no_warnings;
4583
4584 free (s);
4585
4586 demand_empty_rest_of_line ();
4587}
b4ec75e0
ILT		 4588
4589/* Types of MRI structured control directives. */
4590
4591enum mri_control_type
4592{
4593 mri_for,
4594 mri_if,
4595 mri_repeat,
4596 mri_while
4597};
4598
4599/* This structure is used to stack the MRI structured control
4600 directives. */
4601
4602struct mri_control_info
4603{
4604 /* The directive within which this one is enclosed. */
4605 struct mri_control_info *outer;
4606
4607 /* The type of directive. */
4608 enum mri_control_type type;
4609
4610 /* Whether an ELSE has been in an IF. */
4611 int else_seen;
4612
4613 /* The add or sub statement at the end of a FOR. */
4614 char *incr;
4615
4616 /* The label of the top of a FOR or REPEAT loop. */
4617 char *top;
4618
4619 /* The label to jump to for the next iteration, or the else
4620 expression of a conditional. */
4621 char *next;
4622
4623 /* The label to jump to to break out of the loop, or the label past
4624 the end of a conditional. */
4625 char *bottom;
4626};
4627
4628/* The stack of MRI structured control directives. */
4629
4630static struct mri_control_info *mri_control_stack;
4631
4632/* The current MRI structured control directive index number, used to
4633 generate label names. */
4634
4635static int mri_control_index;
4636
4637/* Some function prototypes. */
4638
4639static char *mri_control_label PARAMS ((void));
4640static struct mri_control_info *push_mri_control
4641 PARAMS ((enum mri_control_type));
4642static void pop_mri_control PARAMS ((void));
4643static int parse_mri_condition PARAMS ((int *));
4644static int parse_mri_control_operand
4645 PARAMS ((int *, const char **, const char **, const char **, const char **));
4646static int swap_mri_condition PARAMS ((int));
4647static int reverse_mri_condition PARAMS ((int));
4648static void build_mri_control_operand
4649 PARAMS ((int, int, const char *, const char *, const char *, const char *,
4650 const char *, const char *, int));
4651static void parse_mri_control_expression
4652 PARAMS ((char *, int, const char *, const char *, int));
4653
4654/* Generate a new MRI label structured control directive label name. */
4655
4656static char *
4657mri_control_label ()
4658{
4659 char *n;
4660
4661 n = (char *) xmalloc (20);
4662 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
4663 ++mri_control_index;
4664 return n;
4665}
4666
4667/* Create a new MRI structured control directive. */
4668
4669static struct mri_control_info *
4670push_mri_control (type)
4671 enum mri_control_type type;
4672{
4673 struct mri_control_info *n;
4674
4675 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
4676
4677 n->type = type;
4678 n->else_seen = 0;
4679 if (type == mri_if || type == mri_while)
4680 n->top = NULL;
4681 else
4682 n->top = mri_control_label ();
4683 n->next = mri_control_label ();
4684 n->bottom = mri_control_label ();
4685
4686 n->outer = mri_control_stack;
4687 mri_control_stack = n;
4688
4689 return n;
4690}
4691
4692/* Pop off the stack of MRI structured control directives. */
4693
4694static void
4695pop_mri_control ()
4696{
4697 struct mri_control_info *n;
4698
4699 n = mri_control_stack;
4700 mri_control_stack = n->outer;
4701 if (n->top != NULL)
4702 free (n->top);
4703 free (n->next);
4704 free (n->bottom);
4705 free (n);
4706}
4707
4708/* Recognize a condition code in an MRI structured control expression. */
4709
4710static int
4711parse_mri_condition (pcc)
4712 int *pcc;
4713{
4714 char c1, c2;
4715
4716 know (*input_line_pointer == '<');
4717
4718 ++input_line_pointer;
4719 c1 = *input_line_pointer++;
4720 c2 = *input_line_pointer++;
4721
4722 if (*input_line_pointer != '>')
4723 {
4724 as_bad ("syntax error in structured control directive");
4725 return 0;
4726 }
4727
4728 ++input_line_pointer;
4729 SKIP_WHITESPACE ();
4730
4731 if (isupper (c1))
4732 c1 = tolower (c1);
4733 if (isupper (c2))
4734 c2 = tolower (c2);
4735
4736 *pcc = (c1 << 8) | c2;
4737
4738 return 1;
4739}
4740
4741/* Parse a single operand in an MRI structured control expression. */
4742
4743static int
4744parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
4745 int *pcc;
4746 const char **leftstart;
4747 const char **leftstop;
4748 const char **rightstart;
4749 const char **rightstop;
4750{
4751 char *s;
4752
4753 SKIP_WHITESPACE ();
4754
4755 *pcc = -1;
4756 *leftstart = NULL;
4757 *leftstop = NULL;
4758 *rightstart = NULL;
4759 *rightstop = NULL;
4760
4761 if (*input_line_pointer == '<')
4762 {
4763 /* It's just a condition code. */
4764 return parse_mri_condition (pcc);
4765 }
4766
4767 /* Look ahead for the condition code. */
4768 for (s = input_line_pointer; *s != '\0'; ++s)
4769 {
4770 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
4771 break;
4772 }
4773 if (*s == '\0')
4774 {
4775 as_bad ("missing condition code in structured control directive");
4776 return 0;
4777 }
4778
4779 *leftstart = input_line_pointer;
4780 *leftstop = s;
4781
4782 input_line_pointer = s;
4783 if (! parse_mri_condition (pcc))
4784 return 0;
4785
4786 /* Look ahead for AND or OR or end of line. */
4787 for (s = input_line_pointer; *s != '\0'; ++s)
4788 {
4789 if ((strncasecmp (s, "AND", 3) == 0
4790 && (s[3] == '.' || ! is_part_of_name (s[3])))
4791 || (strncasecmp (s, "OR", 2) == 0
4792 && (s[2] == '.' || ! is_part_of_name (s[2]))))
4793 break;
4794 }
4795
4796 *rightstart = input_line_pointer;
4797 *rightstop = s;
4798
4799 input_line_pointer = s;
4800
4801 return 1;
4802}
4803
4804#define MCC(b1, b2) (((b1) << 8) | (b2))
4805
4806/* Swap the sense of a condition. This changes the condition so that
4807 it generates the same result when the operands are swapped. */
4808
4809static int
4810swap_mri_condition (cc)
4811 int cc;
4812{
4813 switch (cc)
4814 {
4815 case MCC ('h', 'i'): return MCC ('c', 's');
4816 case MCC ('l', 's'): return MCC ('c', 'c');
4817 case MCC ('c', 'c'): return MCC ('l', 's');
4818 case MCC ('c', 's'): return MCC ('h', 'i');
4819 case MCC ('p', 'l'): return MCC ('m', 'i');
4820 case MCC ('m', 'i'): return MCC ('p', 'l');
4821 case MCC ('g', 'e'): return MCC ('l', 'e');
4822 case MCC ('l', 't'): return MCC ('g', 't');
4823 case MCC ('g', 't'): return MCC ('l', 't');
4824 case MCC ('l', 'e'): return MCC ('g', 'e');
4825 }
4826 return cc;
4827}
4828
4829/* Reverse the sense of a condition. */
4830
4831static int
4832reverse_mri_condition (cc)
4833 int cc;
4834{
4835 switch (cc)
4836 {
4837 case MCC ('h', 'i'): return MCC ('l', 's');
4838 case MCC ('l', 's'): return MCC ('h', 'i');
4839 case MCC ('c', 'c'): return MCC ('c', 's');
4840 case MCC ('c', 's'): return MCC ('c', 'c');
4841 case MCC ('n', 'e'): return MCC ('e', 'q');
4842 case MCC ('e', 'q'): return MCC ('n', 'e');
4843 case MCC ('v', 'c'): return MCC ('v', 's');
4844 case MCC ('v', 's'): return MCC ('v', 'c');
4845 case MCC ('p', 'l'): return MCC ('m', 'i');
4846 case MCC ('m', 'i'): return MCC ('p', 'l');
4847 case MCC ('g', 'e'): return MCC ('l', 't');
4848 case MCC ('l', 't'): return MCC ('g', 'e');
4849 case MCC ('g', 't'): return MCC ('l', 'e');
4850 case MCC ('l', 'e'): return MCC ('g', 't');
4851 }
4852 return cc;
4853}
4854
4855/* Build an MRI structured control expression. This generates test
4856 and branch instructions. It goes to TRUELAB if the condition is
4857 true, and to FALSELAB if the condition is false. Exactly one of
4858 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
4859 is the size qualifier for the expression. EXTENT is the size to
4860 use for the branch. */
4861
4862static void
4863build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
4864 rightstop, truelab, falselab, extent)
4865 int qual;
4866 int cc;
4867 const char *leftstart;
4868 const char *leftstop;
4869 const char *rightstart;
4870 const char *rightstop;
4871 const char *truelab;
4872 const char *falselab;
4873 int extent;
4874{
4875 char *buf;
4876 char *s;
4877
4878 /* The 68k can't do a general comparision with an immediate operand
4879 on the right hand side. */
4880 if (rightstart != NULL && *rightstart == '#')
4881 {
4882 const char *temp;
4883
4884 cc = swap_mri_condition (cc);
4885 temp = leftstart;
4886 leftstart = rightstart;
4887 rightstart = temp;
4888 temp = leftstop;
4889 leftstop = rightstop;
4890 rightstop = temp;
4891 }
4892
4893 if (truelab == NULL)
4894 {
4895 cc = reverse_mri_condition (cc);
4896 truelab = falselab;
4897 }
4898
4899 if (leftstart != NULL)
4900 {
4901 buf = (char *) xmalloc (20
4902 + (leftstop - leftstart)
4903 + (rightstop - rightstart));
4904 s = buf;
4905 *s++ = 'c';
4906 *s++ = 'm';
4907 *s++ = 'p';
4908 if (qual != '\0')
4909 *s++ = qual;
4910 *s++ = ' ';
4911 memcpy (s, leftstart, leftstop - leftstart);
4912 s += leftstop - leftstart;
4913 *s++ = ',';
4914 memcpy (s, rightstart, rightstop - rightstart);
4915 s += rightstop - rightstart;
4916 *s = '\0';
4917 md_assemble (buf);
4918 free (buf);
4919 }
4920
4921 buf = (char *) xmalloc (20 + strlen (truelab));
4922 s = buf;
4923 *s++ = 'b';
4924 *s++ = cc >> 8;
4925 *s++ = cc & 0xff;
4926 if (extent != '\0')
4927 *s++ = extent;
4928 *s++ = ' ';
4929 strcpy (s, truelab);
4930 md_assemble (buf);
4931 free (buf);
4932}
4933
4934/* Parse an MRI structured control expression. This generates test
4935 and branch instructions. STOP is where the expression ends. It
4936 goes to TRUELAB if the condition is true, and to FALSELAB if the
4937 condition is false. Exactly one of TRUELAB and FALSELAB will be
4938 NULL, meaning to fall through. QUAL is the size qualifier for the
4939 expression. EXTENT is the size to use for the branch. */
4940
4941static void
4942parse_mri_control_expression (stop, qual, truelab, falselab, extent)
4943 char *stop;
4944 int qual;
4945 const char *truelab;
4946 const char *falselab;
4947 int extent;
4948{
4949 int c;
4950 int cc;
4951 const char *leftstart;
4952 const char *leftstop;
4953 const char *rightstart;
4954 const char *rightstop;
4955
4956 c = *stop;
4957 *stop = '\0';
4958
4959 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
4960 &rightstart, &rightstop))
4961 {
4962 *stop = c;
4963 return;
4964 }
4965
4966 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
4967 {
4968 const char *flab;
4969
4970 if (falselab != NULL)
4971 flab = falselab;
4972 else
4973 flab = mri_control_label ();
4974
4975 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
4976 rightstop, (const char *) NULL, flab, extent);
4977
4978 input_line_pointer += 3;
4979 if (*input_line_pointer != '.'
4980 || input_line_pointer[1] == '\0')
4981 qual = '\0';
4982 else
4983 {
4984 qual = input_line_pointer[1];
4985 input_line_pointer += 2;
4986 }
4987
4988 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
4989 &rightstart, &rightstop))
4990 {
4991 *stop = c;
4992 return;
4993 }
4994
4995 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
4996 rightstop, truelab, falselab, extent);
4997
4998 if (falselab == NULL)
4999 colon (flab);
5000 }
5001 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5002 {
5003 const char *tlab;
5004
5005 if (truelab != NULL)
5006 tlab = truelab;
5007 else
5008 tlab = mri_control_label ();
5009
5010 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5011 rightstop, tlab, (const char *) NULL, extent);
5012
5013 input_line_pointer += 2;
5014 if (*input_line_pointer != '.'
5015 || input_line_pointer[1] == '\0')
5016 qual = '\0';
5017 else
5018 {
5019 qual = input_line_pointer[1];
5020 input_line_pointer += 2;
5021 }
5022
5023 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5024 &rightstart, &rightstop))
5025 {
5026 *stop = c;
5027 return;
5028 }
5029
5030 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5031 rightstop, truelab, falselab, extent);
5032
5033 if (truelab == NULL)
5034 colon (tlab);
5035 }
5036 else
5037 {
5038 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5039 rightstop, truelab, falselab, extent);
5040 }
5041
5042 *stop = c;
5043 if (input_line_pointer != stop)
5044 as_bad ("syntax error in structured control directive");
5045}
5046
5047/* Handle the MRI IF pseudo-op. This may be a structured control
5048 directive, or it may be a regular assembler conditional, depending
5049 on its operands. */
5050
5051static void
5052s_mri_if (qual)
5053 int qual;
5054{
5055 char *s;
5056 int c;
5057 struct mri_control_info *n;
5058
5059 /* A structured control directive must end with THEN with an
5060 optional qualifier. */
5061 s = input_line_pointer;
5062 while (! is_end_of_line[(unsigned char) *s])
5063 ++s;
5064 --s;
5065 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5066 --s;
5067
5068 if (s - input_line_pointer > 1
5069 && s[-1] == '.')
5070 s -= 2;
5071
5072 if (s - input_line_pointer < 3
5073 || strncasecmp (s - 3, "THEN", 4) != 0)
5074 {
5075 if (qual != '\0')
5076 {
5077 as_bad ("missing then");
5078 ignore_rest_of_line ();
5079 return;
5080 }
5081
5082 /* It's a conditional. */
5083 s_if (O_ne);
5084 return;
5085 }
5086
5087 /* Since this might be a conditional if, this pseudo-op will be
5088 called even if we are supported to be ignoring input. Double
5089 check now. Clobber *input_line_pointer so that ignore_input
5090 thinks that this is not a special pseudo-op. */
5091 c = *input_line_pointer;
5092 *input_line_pointer = 0;
5093 if (ignore_input ())
5094 {
5095 *input_line_pointer = c;
5096 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5097 ++input_line_pointer;
5098 demand_empty_rest_of_line ();
5099 return;
5100 }
5101 *input_line_pointer = c;
5102
5103 n = push_mri_control (mri_if);
5104
5105 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5106 n->next, s[1] == '.' ? s[2] : '\0');
5107
5108 if (s[1] == '.')
5109 input_line_pointer = s + 3;
5110 else
5111 input_line_pointer = s + 1;
5112
5113 demand_empty_rest_of_line ();
5114}
5115
5116/* Handle the MRI else pseudo-op. If we are currently doing an MRI
5117 structured IF, associate the ELSE with the IF. Otherwise, assume
5118 it is a conditional else. */
5119
5120static void
5121s_mri_else (qual)
5122 int qual;
5123{
5124 int c;
5125 char *buf;
5126 char q[2];
5127
5128 if (qual == '\0'
5129 && (mri_control_stack == NULL
5130 || mri_control_stack->type != mri_if
5131 || mri_control_stack->else_seen))
5132 {
5133 s_else (0);
5134 return;
5135 }
5136
5137 c = *input_line_pointer;
5138 *input_line_pointer = 0;
5139 if (ignore_input ())
5140 {
5141 *input_line_pointer = c;
5142 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5143 ++input_line_pointer;
5144 demand_empty_rest_of_line ();
5145 return;
5146 }
5147 *input_line_pointer = c;
5148
5149 if (mri_control_stack == NULL
5150 || mri_control_stack->type != mri_if
5151 || mri_control_stack->else_seen)
5152 {
5153 as_bad ("else without matching if");
5154 ignore_rest_of_line ();
5155 return;
5156 }
5157
5158 mri_control_stack->else_seen = 1;
5159
5160 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5161 q[0] = qual;
5162 q[1] = '\0';
5163 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5164 md_assemble (buf);
5165 free (buf);
5166
5167 colon (mri_control_stack->next);
5168
5169 demand_empty_rest_of_line ();
5170}
5171
5172/* Handle the MRI ENDI pseudo-op. */
5173
5174static void
5175s_mri_endi (ignore)
5176 int ignore;
5177{
5178 if (mri_control_stack == NULL
5179 || mri_control_stack->type != mri_if)
5180 {
5181 as_bad ("endi without matching if");
5182 ignore_rest_of_line ();
5183 return;
5184 }
5185
5186 /* ignore_input will not return true for ENDI, so we don't need to
5187 worry about checking it again here. */
5188
5189 if (! mri_control_stack->else_seen)
5190 colon (mri_control_stack->next);
5191 colon (mri_control_stack->bottom);
5192
5193 pop_mri_control ();
5194
5195 demand_empty_rest_of_line ();
5196}
5197
5198/* Handle the MRI BREAK pseudo-op. */
5199
5200static void
5201s_mri_break (extent)
5202 int extent;
5203{
5204 struct mri_control_info *n;
5205 char *buf;
5206 char ex[2];
5207
5208 n = mri_control_stack;
5209 while (n != NULL
5210 && n->type != mri_for
5211 && n->type != mri_repeat
5212 && n->type != mri_while)
5213 n = n->outer;
5214 if (n == NULL)
5215 {
5216 as_bad ("break outside of structured loop");
5217 ignore_rest_of_line ();
5218 return;
5219 }
5220
5221 buf = (char *) xmalloc (20 + strlen (n->bottom));
5222 ex[0] = extent;
5223 ex[1] = '\0';
5224 sprintf (buf, "bra%s %s", ex, n->bottom);
5225 md_assemble (buf);
5226 free (buf);
5227
5228 demand_empty_rest_of_line ();
5229}
5230
5231/* Handle the MRI NEXT pseudo-op. */
5232
5233static void
5234s_mri_next (extent)
5235 int extent;
5236{
5237 struct mri_control_info *n;
5238 char *buf;
5239 char ex[2];
5240
5241 n = mri_control_stack;
5242 while (n != NULL
5243 && n->type != mri_for
5244 && n->type != mri_repeat
5245 && n->type != mri_while)
5246 n = n->outer;
5247 if (n == NULL)
5248 {
5249 as_bad ("next outside of structured loop");
5250 ignore_rest_of_line ();
5251 return;
5252 }
5253
5254 buf = (char *) xmalloc (20 + strlen (n->next));
5255 ex[0] = extent;
5256 ex[1] = '\0';
5257 sprintf (buf, "bra%s %s", ex, n->next);
5258 md_assemble (buf);
5259 free (buf);
5260
5261 demand_empty_rest_of_line ();
5262}
5263
5264/* Handle the MRI FOR pseudo-op. */
5265
5266static void
5267s_mri_for (qual)
5268 int qual;
5269{
5270 const char *varstart, *varstop;
5271 const char *initstart, *initstop;
5272 const char *endstart, *endstop;
5273 const char *bystart, *bystop;
5274 int up;
5275 int by;
5276 int extent;
5277 struct mri_control_info *n;
5278 char *buf;
5279 char *s;
5280 char ex[2];
5281
5282 /* The syntax is
5283 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
5284 */
5285
5286 varstart = input_line_pointer;
5287
5288 /* Look for the '='. */
5289 while (! is_end_of_line[(unsigned char) *input_line_pointer]
5290 && *input_line_pointer != '=')
5291 ++input_line_pointer;
5292 if (*input_line_pointer != '=')
5293 {
5294 as_bad ("missing =");
5295 ignore_rest_of_line ();
5296 return;
5297 }
5298
5299 varstop = input_line_pointer;
5300
5301 ++input_line_pointer;
5302
5303 initstart = input_line_pointer;
5304
5305 /* Look for TO or DOWNTO. */
5306 up = 1;
5307 initstop = NULL;
5308 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5309 {
5310 if (strncasecmp (input_line_pointer, "TO", 2) == 0
5311 && ! is_part_of_name (input_line_pointer[2]))
5312 {
5313 initstop = input_line_pointer;
5314 input_line_pointer += 2;
5315 break;
5316 }
5317 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
5318 && ! is_part_of_name (input_line_pointer[6]))
5319 {
5320 initstop = input_line_pointer;
5321 up = 0;
5322 input_line_pointer += 6;
5323 break;
5324 }
5325 ++input_line_pointer;
5326 }
5327 if (initstop == NULL)
5328 {
5329 as_bad ("missing to or downto");
5330 ignore_rest_of_line ();
5331 return;
5332 }
5333
5334 endstart = input_line_pointer;
5335
5336 /* Look for BY or DO. */
5337 by = 0;
5338 endstop = NULL;
5339 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5340 {
5341 if (strncasecmp (input_line_pointer, "BY", 2) == 0
5342 && ! is_part_of_name (input_line_pointer[2]))
5343 {
5344 endstop = input_line_pointer;
5345 by = 1;
5346 input_line_pointer += 2;
5347 break;
5348 }
5349 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5350 && (input_line_pointer[2] == '.'
5351 || ! is_part_of_name (input_line_pointer[2])))
5352 {
5353 endstop = input_line_pointer;
5354 input_line_pointer += 2;
5355 break;
5356 }
5357 ++input_line_pointer;
5358 }
5359 if (endstop == NULL)
5360 {
5361 as_bad ("missing do");
5362 ignore_rest_of_line ();
5363 return;
5364 }
5365
5366 if (! by)
5367 {
5368 bystart = "#1";
5369 bystop = bystart + 2;
5370 }
5371 else
5372 {
5373 bystart = input_line_pointer;
5374
5375 /* Look for DO. */
5376 bystop = NULL;
5377 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5378 {
5379 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5380 && (input_line_pointer[2] == '.'
5381 || ! is_part_of_name (input_line_pointer[2])))
5382 {
5383 bystop = input_line_pointer;
5384 input_line_pointer += 2;
5385 break;
5386 }
5387 ++input_line_pointer;
5388 }
5389 if (bystop == NULL)
5390 {
5391 as_bad ("missing do");
5392 ignore_rest_of_line ();
5393 return;
5394 }
5395 }
5396
5397 if (*input_line_pointer != '.')
5398 extent = '\0';
5399 else
5400 {
5401 extent = input_line_pointer[1];
5402 input_line_pointer += 2;
5403 }
5404
5405 /* We have fully parsed the FOR operands. Now build the loop. */
5406
5407 n = push_mri_control (mri_for);
5408
5409 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
5410
5411 /* move init,var */
5412 s = buf;
5413 *s++ = 'm';
5414 *s++ = 'o';
5415 *s++ = 'v';
5416 *s++ = 'e';
5417 if (qual != '\0')
5418 *s++ = qual;
5419 *s++ = ' ';
5420 memcpy (s, initstart, initstop - initstart);
5421 s += initstop - initstart;
5422 *s++ = ',';
5423 memcpy (s, varstart, varstop - varstart);
5424 s += varstop - varstart;
5425 *s = '\0';
5426 md_assemble (buf);
5427
5428 colon (n->top);
5429
5430 /* cmp end,var */
5431 s = buf;
5432 *s++ = 'c';
5433 *s++ = 'm';
5434 *s++ = 'p';
5435 if (qual != '\0')
5436 *s++ = qual;
5437 *s++ = ' ';
5438 memcpy (s, endstart, endstop - endstart);
5439 s += endstop - endstart;
5440 *s++ = ',';
5441 memcpy (s, varstart, varstop - varstart);
5442 s += varstop - varstart;
5443 *s = '\0';
5444 md_assemble (buf);
5445
5446 /* bcc bottom */
5447 ex[0] = extent;
5448 ex[1] = '\0';
5449 if (up)
5450 sprintf (buf, "blt%s %s", ex, n->bottom);
5451 else
5452 sprintf (buf, "bgt%s %s", ex, n->bottom);
5453 md_assemble (buf);
5454
5455 /* Put together the add or sub instruction used by ENDF. */
5456 s = buf;
5457 if (up)
5458 strcpy (s, "add");
5459 else
5460 strcpy (s, "sub");
5461 s += 3;
5462 if (qual != '\0')
5463 *s++ = qual;
5464 *s++ = ' ';
5465 memcpy (s, bystart, bystop - bystart);
5466 s += bystop - bystart;
5467 *s++ = ',';
5468 memcpy (s, varstart, varstop - varstart);
5469 s += varstop - varstart;
5470 *s = '\0';
5471 n->incr = buf;
5472
5473 demand_empty_rest_of_line ();
5474}
5475
5476/* Handle the MRI ENDF pseudo-op. */
5477
5478static void
5479s_mri_endf (ignore)
5480 int ignore;
5481{
5482 if (mri_control_stack == NULL
5483 || mri_control_stack->type != mri_for)
5484 {
5485 as_bad ("endf without for");
5486 ignore_rest_of_line ();
5487 return;
5488 }
5489
5490 colon (mri_control_stack->next);
5491
5492 md_assemble (mri_control_stack->incr);
5493
5494 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
5495 md_assemble (mri_control_stack->incr);
5496
5497 free (mri_control_stack->incr);
5498
5499 colon (mri_control_stack->bottom);
5500
5501 pop_mri_control ();
5502
5503 demand_empty_rest_of_line ();
5504}
5505
5506/* Handle the MRI REPEAT pseudo-op. */
5507
5508static void
5509s_mri_repeat (ignore)
5510 int ignore;
5511{
5512 struct mri_control_info *n;
5513
5514 n = push_mri_control (mri_repeat);
5515 colon (n->top);
5516 demand_empty_rest_of_line ();
5517}
5518
5519/* Handle the MRI UNTIL pseudo-op. */
5520
5521static void
5522s_mri_until (qual)
5523 int qual;
5524{
5525 char *s;
5526
5527 if (mri_control_stack == NULL
5528 || mri_control_stack->type != mri_repeat)
5529 {
5530 as_bad ("until without repeat");
5531 ignore_rest_of_line ();
5532 return;
5533 }
5534
5535 colon (mri_control_stack->next);
5536
5537 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
5538 ;
5539
5540 parse_mri_control_expression (s, qual, (const char *) NULL,
5541 mri_control_stack->top, '\0');
5542
5543 colon (mri_control_stack->bottom);
5544
5545 input_line_pointer = s;
5546
5547 demand_empty_rest_of_line ();
5548}
5549
5550/* Handle the MRI WHILE pseudo-op. */
5551
5552static void
5553s_mri_while (qual)
5554 int qual;
5555{
5556 char *s;
5557
5558 struct mri_control_info *n;
5559
5560 s = input_line_pointer;
5561 while (! is_end_of_line[(unsigned char) *s])
5562 s++;
5563 --s;
5564 while (*s == ' ' || *s == '\t')
5565 --s;
5566 if (s - input_line_pointer > 1
5567 && s[-1] == '.')
5568 s -= 2;
5569 if (s - input_line_pointer < 2
5570 || strncasecmp (s - 1, "DO", 2) != 0)
5571 {
5572 as_bad ("missing do");
5573 ignore_rest_of_line ();
5574 return;
5575 }
5576
5577 n = push_mri_control (mri_while);
5578
5579 colon (n->next);
5580
5581 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
5582 s[1] == '.' ? s[2] : '\0');
5583
5584 input_line_pointer = s + 1;
5585 if (*input_line_pointer == '.')
5586 input_line_pointer += 2;
5587
5588 demand_empty_rest_of_line ();
5589}
5590
5591/* Handle the MRI ENDW pseudo-op. */
5592
5593static void
5594s_mri_endw (ignore)
5595 int ignore;
5596{
5597 char *buf;
5598
5599 if (mri_control_stack == NULL
5600 || mri_control_stack->type != mri_while)
5601 {
5602 as_bad ("endw without while");
5603 ignore_rest_of_line ();
5604 return;
5605 }
5606
5607 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
5608 sprintf (buf, "bra %s", mri_control_stack->next);
5609 md_assemble (buf);
5610 free (buf);
5611
5612 colon (mri_control_stack->bottom);
5613
5614 pop_mri_control ();
5615
5616 demand_empty_rest_of_line ();
5617}
f3d817d8 5618\f
7c15cbe8
RP		 5619/*
5620 * md_parse_option
5621 * Invocation line includes a switch not recognized by the base assembler.
5622 * See if it's a processor-specific option. These are:
5623 *
5624 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
5625 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
5626 * Select the architecture. Instructions or features not
5627 * supported by the selected architecture cause fatal
5628 * errors. More than one may be specified. The default is
5629 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
5630 * for -m68000, and -m68882 is a synonym for -m68881.
df3768fb
KR		 5631 * -[A]m[c]no-68851, -[A]m[c]no-68881
5632 * Don't accept 688?1 instructions. (The "c" is kind of silly,
5633 * so don't use or document it, but that's the way the parsing
5634 * works).
7c15cbe8 5635 *
dff60b7d
ILT		 5636 * -pic Indicates PIC.
5637 * -k Indicates PIC. (Sun 3 only.)
b80d39a0 5638 *
7c15cbe8
RP		 5639 */
5640
5f8cb05e
ILT		 5641#ifdef OBJ_ELF
5642CONST char *md_shortopts = "lSA:m:kQ:V";
5643#else
f3d817d8 5644CONST char *md_shortopts = "lSA:m:k";
5f8cb05e
ILT		 5645#endif
5646
f3d817d8
DM		 5647struct option md_longopts[] = {
5648#define OPTION_PIC (OPTION_MD_BASE)
5649 {"pic", no_argument, NULL, OPTION_PIC},
5650#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
5651 {"register-prefix-optional", no_argument, NULL,
5652 OPTION_REGISTER_PREFIX_OPTIONAL},
5653 {NULL, no_argument, NULL, 0}
5654};
5655size_t md_longopts_size = sizeof(md_longopts);
82489ea0 5656
355afbcd 5657int
f3d817d8
DM		 5658md_parse_option (c, arg)
5659 int c;
5660 char *arg;
fecd2382 5661{
f3d817d8 5662 switch (c)
355afbcd
KR		 5663 {
5664 case 'l': /* -l means keep external to 2 bit offset
e284846a 5665 rather than 16 bit one */
9ad5755f 5666 flag_short_refs = 1;
355afbcd 5667 break;
6d27d3a2 5668
e284846a
KR		 5669 case 'S': /* -S means that jbsr's always turn into
5670 jsr's. */
9ad5755f 5671 flag_long_jumps = 1;
355afbcd 5672 break;
6d27d3a2 5673
355afbcd 5674 case 'A':
f3d817d8
DM		 5675 if (*arg == 'm')
5676 arg++;
355afbcd
KR		 5677 /* intentional fall-through */
5678 case 'm':
355afbcd 5679
b79de3a1 5680 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
e284846a 5681 {
064ba683
ILT		 5682 int i;
5683 unsigned long arch;
b79de3a1
KR		 5684 const char *oarg = arg;
5685
5686 arg += 3;
5687 if (*arg == 'm')
5688 {
5689 arg++;
5690 if (arg[0] == 'c' && arg[1] == '6')
5691 arg++;
5692 }
5693 for (i = 0; i < n_archs; i++)
5694 if (!strcmp (arg, archs[i].name))
5695 break;
5696 if (i == n_archs)
5697 {
5698 unknown:
5699 as_bad ("unrecognized option `%s'", oarg);
5700 return 0;
5701 }
5702 arch = archs[i].arch;
5703 if (arch == m68881)
5704 no_68881 = 1;
5705 else if (arch == m68851)
5706 no_68851 = 1;
5707 else
5708 goto unknown;
355afbcd
KR		 5709 }
5710 else
5711 {
b79de3a1
KR		 5712 int i;
5713
5714 if (arg[0] == 'c' && arg[1] == '6')
5715 arg++;
5716
5717 for (i = 0; i < n_archs; i++)
5718 if (!strcmp (arg, archs[i].name))
5719 {
5720 unsigned long arch = archs[i].arch;
5721 if (cpu_of_arch (arch))
5722 /* It's a cpu spec. */
5723 {
5724 current_architecture &= ~m68000up;
5725 current_architecture |= arch;
5726 }
5727 else if (arch == m68881)
5728 {
5729 current_architecture |= m68881;
5730 no_68881 = 0;
5731 }
5732 else if (arch == m68851)
5733 {
5734 current_architecture |= m68851;
5735 no_68851 = 0;
5736 }
5737 else
5738 /* ??? */
5739 abort ();
5740 break;
5741 }
5742 if (i == n_archs)
5743 {
5744 as_bad ("unrecognized architecture specification `%s'", arg);
5745 return 0;
5746 }
f8701a3f 5747 }
f3d817d8 5748 break;
dff60b7d 5749
f3d817d8 5750 case OPTION_PIC:
dff60b7d
ILT		 5751 case 'k':
5752 flag_want_pic = 1;
f3d817d8
DM		 5753 break; /* -pic, Position Independent Code */
5754
5755 case OPTION_REGISTER_PREFIX_OPTIONAL:
5756 flag_reg_prefix_optional = 1;
dff60b7d 5757 break;
355afbcd 5758
5f8cb05e
ILT		 5759 case 'Q':
5760 case 'V':
5761 break;
5762
355afbcd
KR		 5763 default:
5764 return 0;
5765 }
f3d817d8 5766
355afbcd 5767 return 1;
fecd2382
RP		 5768}
5769
f3d817d8
DM		 5770void
5771md_show_usage (stream)
5772 FILE *stream;
5773{
5774 fprintf(stream, "\
5775680X0 options:\n\
5776-l use 1 word for refs to undefined symbols [default 2]\n\
5f8cb05e
ILT		 5777-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
5778 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
5779 | -mcpu32\n\
f3d817d8
DM		 5780 specify variant of 680X0 architecture [default 68020]\n\
5781-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
5782 target has/lacks floating-point coprocessor\n\
5783 [default yes for 68020, 68030, and cpu32]\n\
5784-m68851 | -mno-68851\n\
5785 target has/lacks memory-management unit coprocessor\n\
5786 [default yes for 68020 and up]\n\
5787-pic, -k generate position independent code\n\
5788-S turn jbsr into jsr\n\
5789--register-prefix-optional\n\
5790 recognize register names without prefix character\n");
5791}
5792\f
fecd2382
RP		 5793#ifdef TEST2
5794
5795/* TEST2: Test md_assemble() */
5796/* Warning, this routine probably doesn't work anymore */
5797
355afbcd 5798main ()
fecd2382 5799{
355afbcd
KR		 5800 struct m68k_it the_ins;
5801 char buf[120];
5802 char *cp;
5803 int n;
5804
5805 m68k_ip_begin ();
5806 for (;;)
5807 {
5808 if (!gets (buf) || !*buf)
5809 break;
5810 if (buf[0] == '|' || buf[1] == '.')
5811 continue;
5812 for (cp = buf; *cp; cp++)
5813 if (*cp == '\t')
5814 *cp = ' ';
5815 if (is_label (buf))
5816 continue;
5817 memset (&the_ins, '\0', sizeof (the_ins));
5818 m68k_ip (&the_ins, buf);
5819 if (the_ins.error)
5820 {
5821 printf ("Error %s in %s\n", the_ins.error, buf);
5822 }
5823 else
5824 {
5825 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
5826 for (n = 0; n < the_ins.numo; n++)
5827 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
5828 printf (" ");
5829 print_the_insn (&the_ins.opcode[0], stdout);
5830 (void) putchar ('\n');
5831 }
5832 for (n = 0; n < strlen (the_ins.args) / 2; n++)
5833 {
5834 if (the_ins.operands[n].error)
5835 {
5836 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
5837 continue;
5838 }
5839 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
5840 if (the_ins.operands[n].b_const)
5841 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
5842 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
5843 if (the_ins.operands[n].b_iadd)
5844 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
5845 (void) putchar ('\n');
a39116f1 5846 }
355afbcd
KR		 5847 }
5848 m68k_ip_end ();
5849 return 0;
fecd2382
RP		 5850}
5851
355afbcd
KR		 5852is_label (str)
5853 char *str;
fecd2382 5854{
355afbcd
KR		 5855 while (*str == ' ')
5856 str++;
5857 while (*str && *str != ' ')
5858 str++;
5859 if (str[-1] == ':' || str[1] == '=')
5860 return 1;
5861 return 0;
fecd2382
RP		 5862}
5863
5864#endif
5865
5866/* Possible states for relaxation:
6d27d3a2 5867
a39116f1
RP		 5868 0 0 branch offset byte (bra, etc)
5869 0 1 word
5870 0 2 long
6d27d3a2 5871
a39116f1
RP		 5872 1 0 indexed offsets byte a0@(32,d4:w:1) etc
5873 1 1 word
5874 1 2 long
6d27d3a2 5875
a39116f1
RP		 5876 2 0 two-offset index word-word a0@(32,d4)@(45) etc
5877 2 1 word-long
5878 2 2 long-word
5879 2 3 long-long
6d27d3a2 5880
a39116f1 5881 */
fecd2382 5882
fecd2382
RP		 5883/* We have no need to default values of symbols. */
5884
5885/* ARGSUSED */
5886symbolS *
355afbcd
KR		 5887md_undefined_symbol (name)
5888 char *name;
fecd2382 5889{
355afbcd 5890 return 0;
fecd2382
RP		 5891}
5892
fecd2382 5893/* Round up a section size to the appropriate boundary. */
025b0302 5894valueT
355afbcd
KR		 5895md_section_align (segment, size)
5896 segT segment;
025b0302 5897 valueT size;
fecd2382 5898{
355afbcd 5899 return size; /* Byte alignment is fine */
fecd2382
RP		 5900}
5901
5902/* Exactly what point is a PC-relative offset relative TO?
5f8cb05e
ILT		 5903 On the 68k, it is relative to the address of the first extension
5904 word. The difference between the addresses of the offset and the
5905 first extension word is stored in fx_pcrel_adjust. */
fecd2382 5906long
355afbcd
KR		 5907md_pcrel_from (fixP)
5908 fixS *fixP;
fecd2382 5909{
b4ec75e0
ILT		 5910 int adjust;
5911
5912 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
5913 -1 as 64. */
5914 adjust = fixP->fx_pcrel_adjust;
5915 if (adjust == 64)
5916 adjust = -1;
5917 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
fecd2382
RP		 5918}
5919
49864cfa 5920#ifndef BFD_ASSEMBLER
9ad5755f 5921/*ARGSUSED*/
355afbcd 5922void
9ad5755f
KR		 5923tc_coff_symbol_emit_hook (ignore)
5924 symbolS *ignore;
3ad9ec6a
ILT		 5925{
5926}
5927
355afbcd
KR		 5928int
5929tc_coff_sizemachdep (frag)
5930 fragS *frag;
3ad9ec6a 5931{
355afbcd
KR		 5932 switch (frag->fr_subtype & 0x3)
5933 {
5934 case BYTE:
5935 return 1;
5936 case SHORT:
5937 return 2;
5938 case LONG:
5939 return 4;
5940 default:
5941 abort ();
064ba683 5942 return 0;
355afbcd 5943 }
3ad9ec6a 5944}
49864cfa 5945#endif
355afbcd 5946
fecd2382 5947/* end of tc-m68k.c */
GDB Binutils - Deliverables
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