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2003-08-08 Elena Zannoni <ezannoni@redhat.com>
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
CommitLineData
252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
8a104df9 3 2000, 2001, 2002
252b5132
RH		 4 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
252b5132 23#include "as.h"
3882b010 24#include "safe-ctype.h"
252b5132
RH		 25#include "obstack.h"
26#include "subsegs.h"
f27a3839 27#include "dwarf2dbg.h"
252b5132
RH		 28
29#include "opcode/m68k.h"
30#include "m68k-parse.h"
31
0d96863f
CM		 32#if defined (OBJ_ELF)
33#include "elf/m68k.h"
34#endif
35
252b5132
RH		 36/* This string holds the chars that always start a comment. If the
37 pre-processor is disabled, these aren't very useful. The macro
38 tc_comment_chars points to this. We use this, rather than the
39 usual comment_chars, so that the --bitwise-or option will work. */
40#if defined (TE_SVR4) || defined (TE_DELTA)
41const char *m68k_comment_chars = "|#";
42#else
43const char *m68k_comment_chars = "|";
44#endif
45
46/* This array holds the chars that only start a comment at the beginning of
47 a line. If the line seems to have the form '# 123 filename'
48 .line and .file directives will appear in the pre-processed output */
49/* Note that input_file.c hand checks for '#' at the beginning of the
50 first line of the input file. This is because the compiler outputs
92774660
KH		 51 #NO_APP at the beginning of its output. */
52/* Also note that comments like this one will always work. */
252b5132
RH		 53const char line_comment_chars[] = "#*";
54
63a0b638 55const char line_separator_chars[] = ";";
252b5132
RH		 56
57/* Chars that can be used to separate mant from exp in floating point nums */
5a38dc70 58const char EXP_CHARS[] = "eE";
252b5132
RH		 59
60/* Chars that mean this number is a floating point constant, as
61 in "0f12.456" or "0d1.2345e12". */
62
5a38dc70 63const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 64
65/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
66 changed in read.c . Ideally it shouldn't have to know about it at all,
67 but nothing is ideal around here. */
68
69const int md_reloc_size = 8; /* Size of relocation record */
70
71/* Are we trying to generate PIC code? If so, absolute references
72 ought to be made into linkage table references or pc-relative
92774660 73 references. Not implemented. For ELF there are other means
252b5132
RH		 74 to denote pic relocations. */
75int flag_want_pic;
76
77static int flag_short_refs; /* -l option */
78static int flag_long_jumps; /* -S option */
28e7409f 79static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 80
81#ifdef REGISTER_PREFIX_OPTIONAL
82int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
83#else
84int flag_reg_prefix_optional;
85#endif
86
87/* Whether --register-prefix-optional was used on the command line. */
88static int reg_prefix_optional_seen;
89
90/* The floating point coprocessor to use by default. */
91static enum m68k_register m68k_float_copnum = COP1;
92
93/* If this is non-zero, then references to number(%pc) will be taken
94 to refer to number, rather than to %pc + number. */
95static int m68k_abspcadd;
96
97/* If this is non-zero, then the quick forms of the move, add, and sub
98 instructions are used when possible. */
99static int m68k_quick = 1;
100
101/* If this is non-zero, then if the size is not specified for a base
102 or outer displacement, the assembler assumes that the size should
103 be 32 bits. */
104static int m68k_rel32 = 1;
105
106/* This is non-zero if m68k_rel32 was set from the command line. */
107static int m68k_rel32_from_cmdline;
108
109/* The default width to use for an index register when using a base
110 displacement. */
111static enum m68k_size m68k_index_width_default = SIZE_LONG;
112
113/* We want to warn if any text labels are misaligned. In order to get
114 the right line number, we need to record the line number for each
115 label. */
116
117struct label_line
118{
119 struct label_line *next;
120 symbolS *label;
121 char *file;
122 unsigned int line;
123 int text;
124};
125
126/* The list of labels. */
127
128static struct label_line *labels;
129
130/* The current label. */
131
132static struct label_line *current_label;
133
134/* Its an arbitrary name: This means I don't approve of it */
135/* See flames below */
136static struct obstack robyn;
137
252b5132
RH		 138struct m68k_incant
139 {
140 const char *m_operands;
141 unsigned long m_opcode;
142 short m_opnum;
143 short m_codenum;
144 int m_arch;
145 struct m68k_incant *m_next;
146 };
147
148#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
149#define gettwo(x) (((x)->m_opcode)&0xffff)
150
151static const enum m68k_register m68000_control_regs[] = { 0 };
152static const enum m68k_register m68010_control_regs[] = {
153 SFC, DFC, USP, VBR,
154 0
155};
156static const enum m68k_register m68020_control_regs[] = {
157 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
158 0
159};
160static const enum m68k_register m68040_control_regs[] = {
161 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
162 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
163 0
164};
165static const enum m68k_register m68060_control_regs[] = {
166 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
167 USP, VBR, URP, SRP, PCR,
168 0
169};
6da466c7 170static const enum m68k_register mcf_control_regs[] = {
92774660 171 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
252b5132
RH		 172 RAMBAR0, RAMBAR1, MBAR,
173 0
174};
175#define cpu32_control_regs m68010_control_regs
176
177static const enum m68k_register *control_regs;
178
179/* internal form of a 68020 instruction */
180struct m68k_it
181{
182 const char *error;
183 const char *args; /* list of opcode info */
184 int numargs;
185
186 int numo; /* Number of shorts in opcode */
187 short opcode[11];
188
189 struct m68k_op operands[6];
190
191 int nexp; /* number of exprs in use */
192 struct m68k_exp exprs[4];
193
194 int nfrag; /* Number of frags we have to produce */
195 struct
196 {
197 int fragoff; /* Where in the current opcode the frag ends */
198 symbolS *fadd;
199 offsetT foff;
200 int fragty;
201 }
202 fragb[4];
203
204 int nrel; /* Num of reloc strucs in use */
205 struct
206 {
207 int n;
208 expressionS exp;
209 char wid;
210 char pcrel;
211 /* In a pc relative address the difference between the address
212 of the offset and the address that the offset is relative
213 to. This depends on the addressing mode. Basically this
214 is the value to put in the offset field to address the
215 first byte of the offset, without regarding the special
216 significance of some values (in the branch instruction, for
217 example). */
218 int pcrel_fix;
219#ifdef OBJ_ELF
220 /* Whether this expression needs special pic relocation, and if
221 so, which. */
222 enum pic_relocation pic_reloc;
223#endif
224 }
225 reloc[5]; /* Five is enough??? */
226};
227
6da466c7 228#define cpu_of_arch(x) ((x) & (m68000up|mcf))
252b5132
RH		 229#define float_of_arch(x) ((x) & mfloat)
230#define mmu_of_arch(x) ((x) & mmmu)
6da466c7 231#define arch_coldfire_p(x) (((x) & mcf) != 0)
252b5132
RH		 232
233/* Macros for determining if cpu supports a specific addressing mode */
dc84e067 234#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407))
252b5132
RH		 235
236static struct m68k_it the_ins; /* the instruction being assembled */
237
238#define op(ex) ((ex)->exp.X_op)
239#define adds(ex) ((ex)->exp.X_add_symbol)
240#define subs(ex) ((ex)->exp.X_op_symbol)
241#define offs(ex) ((ex)->exp.X_add_number)
242
243/* Macros for adding things to the m68k_it struct */
244
245#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
246
247/* Static functions. */
248
249static void insop PARAMS ((int, const struct m68k_incant *));
250static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
251static void add_frag PARAMS ((symbolS *, offsetT, int));
252
253/* Like addword, but goes BEFORE general operands */
254static void
255insop (w, opcode)
256 int w;
257 const struct m68k_incant *opcode;
258{
259 int z;
07726851 260 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 261 the_ins.opcode[z] = the_ins.opcode[z - 1];
262 for (z = 0; z < the_ins.nrel; z++)
263 the_ins.reloc[z].n += 2;
252b5132
RH		 264 for (z = 0; z < the_ins.nfrag; z++)
265 the_ins.fragb[z].fragoff++;
8a104df9 266 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 267 the_ins.numo++;
268}
269
270/* The numo+1 kludge is so we can hit the low order byte of the prev word.
271 Blecch. */
272static void
273add_fix (width, exp, pc_rel, pc_fix)
274 int width;
275 struct m68k_exp *exp;
276 int pc_rel;
277 int pc_fix;
278{
279 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
280 ? (the_ins.numo*2-1)
281 : (((width)=='b')
282 ? (the_ins.numo*2+1)
283 : (the_ins.numo*2)));
284 the_ins.reloc[the_ins.nrel].exp = exp->exp;
285 the_ins.reloc[the_ins.nrel].wid = width;
286 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
287#ifdef OBJ_ELF
288 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
289#endif
290 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
291}
292
293/* Cause an extra frag to be generated here, inserting up to 10 bytes
294 (that value is chosen in the frag_var call in md_assemble). TYPE
295 is the subtype of the frag to be generated; its primary type is
296 rs_machine_dependent.
297
298 The TYPE parameter is also used by md_convert_frag_1 and
299 md_estimate_size_before_relax. The appropriate type of fixup will
300 be emitted by md_convert_frag_1.
301
302 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
303static void
304add_frag (add, off, type)
305 symbolS *add;
306 offsetT off;
307 int type;
308{
8a104df9
KH		 309 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
310 the_ins.fragb[the_ins.nfrag].fadd = add;
311 the_ins.fragb[the_ins.nfrag].foff = off;
312 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 313}
314
315#define isvar(ex) \
316 (op (ex) != O_constant && op (ex) != O_big)
317
318static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
319static int get_num PARAMS ((struct m68k_exp *exp, int ok));
320static void m68k_ip PARAMS ((char *));
321static void insert_reg PARAMS ((const char *, int));
322static void select_control_regs PARAMS ((void));
323static void init_regtable PARAMS ((void));
324static int reverse_16_bits PARAMS ((int in));
325static int reverse_8_bits PARAMS ((int in));
326static void install_gen_operand PARAMS ((int mode, int val));
327static void install_operand PARAMS ((int mode, int val));
328static void s_bss PARAMS ((int));
329static void s_data1 PARAMS ((int));
330static void s_data2 PARAMS ((int));
331static void s_even PARAMS ((int));
332static void s_proc PARAMS ((int));
333static void mri_chip PARAMS ((void));
334static void s_chip PARAMS ((int));
335static void s_fopt PARAMS ((int));
336static void s_opt PARAMS ((int));
337static void s_reg PARAMS ((int));
338static void s_restore PARAMS ((int));
339static void s_save PARAMS ((int));
340static void s_mri_if PARAMS ((int));
341static void s_mri_else PARAMS ((int));
342static void s_mri_endi PARAMS ((int));
343static void s_mri_break PARAMS ((int));
344static void s_mri_next PARAMS ((int));
345static void s_mri_for PARAMS ((int));
346static void s_mri_endf PARAMS ((int));
347static void s_mri_repeat PARAMS ((int));
348static void s_mri_until PARAMS ((int));
349static void s_mri_while PARAMS ((int));
350static void s_mri_endw PARAMS ((int));
252b5132
RH		 351static void md_convert_frag_1 PARAMS ((fragS *));
352
353static int current_architecture;
354
dc84e067
NC		 355struct m68k_cpu
356 {
357 unsigned long arch;
358 const char *name;
359 int alias;
360 };
252b5132 361
dc84e067
NC		 362static const struct m68k_cpu archs[] =
363 {
364 { m68000, "68000", 0 },
365 { m68010, "68010", 0 },
366 { m68020, "68020", 0 },
367 { m68030, "68030", 0 },
368 { m68040, "68040", 0 },
369 { m68060, "68060", 0 },
370 { cpu32, "cpu32", 0 },
371 { m68881, "68881", 0 },
372 { m68851, "68851", 0 },
373 { mcf5200, "5200", 0 },
374 { mcf5206e, "5206e", 0 },
375 { mcf5307, "5307", 0},
376 { mcf5407, "5407", 0},
377 /* Aliases (effectively, so far as gas is concerned) for the above
378 cpus. */
379 { m68020, "68k", 1 },
380 { m68000, "68008", 1 },
381 { m68000, "68302", 1 },
382 { m68000, "68306", 1 },
383 { m68000, "68307", 1 },
384 { m68000, "68322", 1 },
385 { m68000, "68356", 1 },
386 { m68000, "68ec000", 1 },
387 { m68000, "68hc000", 1 },
388 { m68000, "68hc001", 1 },
389 { m68020, "68ec020", 1 },
390 { m68030, "68ec030", 1 },
391 { m68040, "68ec040", 1 },
392 { m68060, "68ec060", 1 },
393 { cpu32, "68330", 1 },
394 { cpu32, "68331", 1 },
395 { cpu32, "68332", 1 },
396 { cpu32, "68333", 1 },
397 { cpu32, "68334", 1 },
398 { cpu32, "68336", 1 },
399 { cpu32, "68340", 1 },
400 { cpu32, "68341", 1 },
401 { cpu32, "68349", 1 },
402 { cpu32, "68360", 1 },
403 { m68881, "68882", 1 },
404 { mcf5200, "5202", 1 },
405 { mcf5200, "5204", 1 },
406 { mcf5200, "5206", 1 },
407 };
252b5132
RH		 408
409static const int n_archs = sizeof (archs) / sizeof (archs[0]);
410
151337e8
NC		 411/* This is the assembler relaxation table for m68k. m68k is a rich CISC
412 architecture and we have a lot of relaxation modes. */
252b5132 413
151337e8
NC		 414/* Macros used in the relaxation code. */
415#define TAB(x,y) (((x) << 2) + (y))
416#define TABTYPE(x) ((x) >> 2)
417
418/* Relaxation states. */
419#define BYTE 0
420#define SHORT 1
421#define LONG 2
422#define SZ_UNDEF 3
423
424/* Here are all the relaxation modes we support. First we can relax ordinary
425 branches. On 68020 and higher and on CPU32 all branch instructions take
426 three forms, so on these CPUs all branches always remain as such. When we
427 have to expand to the LONG form on a 68000, though, we substitute an
428 absolute jump instead. This is a direct replacement for unconditional
429 branches and a branch over a jump for conditional branches. However, if the
430 user requires PIC and disables this with --pcrel, we can only relax between
431 BYTE and SHORT forms, punting if that isn't enough. This gives us four
432 different relaxation modes for branches: */
433
ac62c346
AM		 434#define BRANCHBWL 0 /* branch byte, word, or long */
435#define BRABSJUNC 1 /* absolute jump for LONG, unconditional */
436#define BRABSJCOND 2 /* absolute jump for LONG, conditional */
437#define BRANCHBW 3 /* branch byte or word */
151337e8
NC		 438
439/* We also relax coprocessor branches and DBcc's. All CPUs that support
440 coprocessor branches support them in word and long forms, so we have only
441 one relaxation mode for them. DBcc's are word only on all CPUs. We can
442 relax them to the LONG form with a branch-around sequence. This sequence
443 can use a long branch (if available) or an absolute jump (if acceptable).
444 This gives us two relaxation modes. If long branches are not available and
445 absolute jumps are not acceptable, we don't relax DBcc's. */
446
ac62c346
AM		 447#define FBRANCH 4 /* coprocessor branch */
448#define DBCCLBR 5 /* DBcc relaxable with a long branch */
449#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump */
151337e8
NC		 450
451/* That's all for instruction relaxation. However, we also relax PC-relative
452 operands. Specifically, we have three operand relaxation modes. On the
453 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
454 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
455 two. Also PC+displacement+index operands in their simple form (with a non-
456 suppressed index without memory indirection) are supported on all CPUs, but
457 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
458 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
459 form of the PC+displacement+index operand. Finally, some absolute operands
460 can be relaxed down to 16-bit PC-relative. */
461
ac62c346
AM		 462#define PCREL1632 7 /* 16-bit or 32-bit PC-relative */
463#define PCINDEX 8 /* PC+displacement+index */
464#define ABSTOPCREL 9 /* absolute relax down to 16-bit PC-relative */
252b5132
RH		 465
466/* Note that calls to frag_var need to specify the maximum expansion
467 needed; this is currently 10 bytes for DBCC. */
468
469/* The fields are:
470 How far Forward this mode will reach:
471 How far Backward this mode will reach:
472 How many bytes this mode will add to the size of the frag
473 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 474
475 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 476relax_typeS md_relax_table[] =
477{
ac62c346
AM		 478 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
479 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
480 { 0, 0, 4, 0 },
481 { 1, 1, 0, 0 },
482
483 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
484 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
485 { 0, 0, 4, 0 },
486 { 1, 1, 0, 0 },
487
488 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
489 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
490 { 0, 0, 6, 0 },
491 { 1, 1, 0, 0 },
492
493 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
494 { 0, 0, 2, 0 },
495 { 1, 1, 0, 0 },
496 { 1, 1, 0, 0 },
497
498 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */
499 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
500 { 0, 0, 4, 0 },
501 { 1, 1, 0, 0 },
502
503 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
504 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
505 { 0, 0, 10, 0 },
506 { 1, 1, 0, 0 },
507
508 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
509 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
510 { 0, 0, 10, 0 },
511 { 1, 1, 0, 0 },
512
513 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE */
514 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
515 { 0, 0, 6, 0 },
516 { 1, 1, 0, 0 },
517
518 { 125, -130, 0, TAB (PCINDEX, SHORT) },
519 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
520 { 0, 0, 4, 0 },
521 { 1, 1, 0, 0 },
522
523 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE */
524 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
525 { 0, 0, 4, 0 },
526 { 1, 1, 0, 0 },
252b5132
RH		 527};
528
529/* These are the machine dependent pseudo-ops. These are included so
530 the assembler can work on the output from the SUN C compiler, which
531 generates these.
532 */
533
534/* This table describes all the machine specific pseudo-ops the assembler
535 has to support. The fields are:
536 pseudo-op name without dot
537 function to call to execute this pseudo-op
538 Integer arg to pass to the function
539 */
540const pseudo_typeS md_pseudo_table[] =
541{
542 {"data1", s_data1, 0},
543 {"data2", s_data2, 0},
544 {"bss", s_bss, 0},
545 {"even", s_even, 0},
546 {"skip", s_space, 0},
547 {"proc", s_proc, 0},
548#if defined (TE_SUN3) || defined (OBJ_ELF)
549 {"align", s_align_bytes, 0},
550#endif
551#ifdef OBJ_ELF
552 {"swbeg", s_ignore, 0},
553#endif
554 {"extend", float_cons, 'x'},
555 {"ldouble", float_cons, 'x'},
556
557 /* The following pseudo-ops are supported for MRI compatibility. */
558 {"chip", s_chip, 0},
559 {"comline", s_space, 1},
560 {"fopt", s_fopt, 0},
561 {"mask2", s_ignore, 0},
562 {"opt", s_opt, 0},
563 {"reg", s_reg, 0},
564 {"restore", s_restore, 0},
565 {"save", s_save, 0},
566
567 {"if", s_mri_if, 0},
568 {"if.b", s_mri_if, 'b'},
569 {"if.w", s_mri_if, 'w'},
570 {"if.l", s_mri_if, 'l'},
571 {"else", s_mri_else, 0},
572 {"else.s", s_mri_else, 's'},
573 {"else.l", s_mri_else, 'l'},
574 {"endi", s_mri_endi, 0},
575 {"break", s_mri_break, 0},
576 {"break.s", s_mri_break, 's'},
577 {"break.l", s_mri_break, 'l'},
578 {"next", s_mri_next, 0},
579 {"next.s", s_mri_next, 's'},
580 {"next.l", s_mri_next, 'l'},
581 {"for", s_mri_for, 0},
582 {"for.b", s_mri_for, 'b'},
583 {"for.w", s_mri_for, 'w'},
584 {"for.l", s_mri_for, 'l'},
585 {"endf", s_mri_endf, 0},
586 {"repeat", s_mri_repeat, 0},
587 {"until", s_mri_until, 0},
588 {"until.b", s_mri_until, 'b'},
589 {"until.w", s_mri_until, 'w'},
590 {"until.l", s_mri_until, 'l'},
591 {"while", s_mri_while, 0},
592 {"while.b", s_mri_while, 'b'},
593 {"while.w", s_mri_while, 'w'},
594 {"while.l", s_mri_while, 'l'},
595 {"endw", s_mri_endw, 0},
596
597 {0, 0, 0}
598};
599
252b5132
RH		 600/* The mote pseudo ops are put into the opcode table, since they
601 don't start with a . they look like opcodes to gas.
602 */
603
604#ifdef M68KCOFF
605extern void obj_coff_section PARAMS ((int));
606#endif
607
5a38dc70 608const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 609{
610
611 {"dcl", cons, 4},
612 {"dc", cons, 2},
613 {"dcw", cons, 2},
614 {"dcb", cons, 1},
615
616 {"dsl", s_space, 4},
617 {"ds", s_space, 2},
618 {"dsw", s_space, 2},
619 {"dsb", s_space, 1},
620
621 {"xdef", s_globl, 0},
622#ifdef OBJ_ELF
623 {"align", s_align_bytes, 0},
624#else
625 {"align", s_align_ptwo, 0},
626#endif
627#ifdef M68KCOFF
628 {"sect", obj_coff_section, 0},
629 {"section", obj_coff_section, 0},
630#endif
631 {0, 0, 0}
632};
633
634#define issbyte(x) ((x)>=-128 && (x)<=127)
635#define isubyte(x) ((x)>=0 && (x)<=255)
636#define issword(x) ((x)>=-32768 && (x)<=32767)
637#define isuword(x) ((x)>=0 && (x)<=65535)
638
639#define isbyte(x) ((x)>= -255 && (x)<=255)
640#define isword(x) ((x)>=-65536 && (x)<=65535)
641#define islong(x) (1)
642
643extern char *input_line_pointer;
644
252b5132
RH		 645static char notend_table[256];
646static char alt_notend_table[256];
647#define notend(s) \
648 (! (notend_table[(unsigned char) *s] \
649 || (*s == ':' \
650 && alt_notend_table[(unsigned char) s[1]])))
651
652#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
653
654#ifdef NO_PCREL_RELOCS
655
656int
657make_pcrel_absolute(fixP, add_number)
658 fixS *fixP;
659 long *add_number;
660{
661 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
662
663 /* rewrite the PC relative instructions to absolute address ones.
664 * these are rumoured to be faster, and the apollo linker refuses
665 * to deal with the PC relative relocations.
666 */
667 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
668 {
669 opcode[0] = 0x4e;
670 opcode[1] = 0xf9;
671 }
672 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
673 {
674 opcode[0] = 0x4e;
675 opcode[1] = 0xb9;
676 }
677 else
678 as_fatal (_("Unknown PC relative instruction"));
679 *add_number -= 4;
680 return 0;
681}
682
683#endif /* NO_PCREL_RELOCS */
684
685short
686tc_coff_fix2rtype (fixP)
687 fixS *fixP;
688{
689 if (fixP->fx_tcbit && fixP->fx_size == 4)
690 return R_RELLONG_NEG;
691#ifdef NO_PCREL_RELOCS
692 know (fixP->fx_pcrel == 0);
693 return (fixP->fx_size == 1 ? R_RELBYTE
694 : fixP->fx_size == 2 ? R_DIR16
695 : R_DIR32);
696#else
697 return (fixP->fx_pcrel ?
698 (fixP->fx_size == 1 ? R_PCRBYTE :
699 fixP->fx_size == 2 ? R_PCRWORD :
700 R_PCRLONG) :
701 (fixP->fx_size == 1 ? R_RELBYTE :
702 fixP->fx_size == 2 ? R_RELWORD :
703 R_RELLONG));
704#endif
705}
706
707#endif
708
709#ifdef OBJ_ELF
710
c801568a
AM		 711/* Return zero if the reference to SYMBOL from within the same segment may
712 be relaxed. */
713
714/* On an ELF system, we can't relax an externally visible symbol,
715 because it may be overridden by a shared library. However, if
716 TARGET_OS is "elf", then we presume that we are assembling for an
717 embedded system, in which case we don't have to worry about shared
718 libraries, and we can relax any external sym. */
719
720#define relaxable_symbol(symbol) \
721 (!((S_IS_EXTERNAL (symbol) && strcmp (TARGET_OS, "elf") != 0) \
722 || S_IS_WEAK (symbol)))
723
252b5132
RH		 724/* Compute the relocation code for a fixup of SIZE bytes, using pc
725 relative relocation if PCREL is non-zero. PIC says whether a special
726 pic relocation was requested. */
727
728static bfd_reloc_code_real_type get_reloc_code
729 PARAMS ((int, int, enum pic_relocation));
730
731static bfd_reloc_code_real_type
732get_reloc_code (size, pcrel, pic)
733 int size;
734 int pcrel;
735 enum pic_relocation pic;
736{
737 switch (pic)
738 {
739 case pic_got_pcrel:
740 switch (size)
741 {
742 case 1:
743 return BFD_RELOC_8_GOT_PCREL;
744 case 2:
745 return BFD_RELOC_16_GOT_PCREL;
746 case 4:
747 return BFD_RELOC_32_GOT_PCREL;
748 }
749 break;
750
751 case pic_got_off:
752 switch (size)
753 {
754 case 1:
755 return BFD_RELOC_8_GOTOFF;
756 case 2:
757 return BFD_RELOC_16_GOTOFF;
758 case 4:
759 return BFD_RELOC_32_GOTOFF;
760 }
761 break;
762
763 case pic_plt_pcrel:
764 switch (size)
765 {
766 case 1:
767 return BFD_RELOC_8_PLT_PCREL;
768 case 2:
769 return BFD_RELOC_16_PLT_PCREL;
770 case 4:
771 return BFD_RELOC_32_PLT_PCREL;
772 }
773 break;
774
775 case pic_plt_off:
776 switch (size)
777 {
778 case 1:
779 return BFD_RELOC_8_PLTOFF;
780 case 2:
781 return BFD_RELOC_16_PLTOFF;
782 case 4:
783 return BFD_RELOC_32_PLTOFF;
784 }
785 break;
786
787 case pic_none:
788 if (pcrel)
789 {
790 switch (size)
791 {
792 case 1:
793 return BFD_RELOC_8_PCREL;
794 case 2:
795 return BFD_RELOC_16_PCREL;
796 case 4:
797 return BFD_RELOC_32_PCREL;
798 }
799 }
800 else
801 {
802 switch (size)
803 {
804 case 1:
805 return BFD_RELOC_8;
806 case 2:
807 return BFD_RELOC_16;
808 case 4:
809 return BFD_RELOC_32;
810 }
811 }
812 }
813
814 if (pcrel)
815 {
816 if (pic == pic_none)
817 as_bad (_("Can not do %d byte pc-relative relocation"), size);
818 else
819 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
820 }
821 else
822 {
823 if (pic == pic_none)
824 as_bad (_("Can not do %d byte relocation"), size);
825 else
826 as_bad (_("Can not do %d byte pic relocation"), size);
827 }
828
829 return BFD_RELOC_NONE;
830}
831
832/* Here we decide which fixups can be adjusted to make them relative
833 to the beginning of the section instead of the symbol. Basically
834 we need to make sure that the dynamic relocations are done
835 correctly, so in some cases we force the original symbol to be
836 used. */
837int
838tc_m68k_fix_adjustable (fixP)
839 fixS *fixP;
840{
252b5132
RH		 841 /* adjust_reloc_syms doesn't know about the GOT */
842 switch (fixP->fx_r_type)
843 {
844 case BFD_RELOC_8_GOT_PCREL:
845 case BFD_RELOC_16_GOT_PCREL:
846 case BFD_RELOC_32_GOT_PCREL:
847 case BFD_RELOC_8_GOTOFF:
848 case BFD_RELOC_16_GOTOFF:
849 case BFD_RELOC_32_GOTOFF:
850 case BFD_RELOC_8_PLT_PCREL:
851 case BFD_RELOC_16_PLT_PCREL:
852 case BFD_RELOC_32_PLT_PCREL:
853 case BFD_RELOC_8_PLTOFF:
854 case BFD_RELOC_16_PLTOFF:
855 case BFD_RELOC_32_PLTOFF:
856 return 0;
857
858 case BFD_RELOC_VTABLE_INHERIT:
859 case BFD_RELOC_VTABLE_ENTRY:
860 return 0;
861
862 default:
863 return 1;
864 }
865}
866
867#else /* !OBJ_ELF */
868
869#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
870
c801568a
AM		 871#define relaxable_symbol(symbol) 1
872
252b5132
RH		 873#endif /* OBJ_ELF */
874
875#ifdef BFD_ASSEMBLER
876
877arelent *
878tc_gen_reloc (section, fixp)
f1f5ef86 879 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 880 fixS *fixp;
881{
882 arelent *reloc;
883 bfd_reloc_code_real_type code;
884
8ec6253e
NC		 885 /* If the tcbit is set, then this was a fixup of a negative value
886 that was never resolved. We do not have a reloc to handle this,
887 so just return. We assume that other code will have detected this
888 situation and produced a helpful error message, so we just tell the
889 user that the reloc cannot be produced. */
252b5132 890 if (fixp->fx_tcbit)
8ec6253e
NC		 891 {
892 if (fixp->fx_addsy)
b091f402
AM		 893 as_bad_where (fixp->fx_file, fixp->fx_line,
894 _("Unable to produce reloc against symbol '%s'"),
895 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 896 return NULL;
897 }
252b5132
RH		 898
899 if (fixp->fx_r_type != BFD_RELOC_NONE)
900 {
901 code = fixp->fx_r_type;
902
903 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
904 that fixup_segment converted a non-PC relative reloc into a
905 PC relative reloc. In such a case, we need to convert the
906 reloc code. */
907 if (fixp->fx_pcrel)
908 {
909 switch (code)
910 {
911 case BFD_RELOC_8:
912 code = BFD_RELOC_8_PCREL;
913 break;
914 case BFD_RELOC_16:
915 code = BFD_RELOC_16_PCREL;
916 break;
917 case BFD_RELOC_32:
918 code = BFD_RELOC_32_PCREL;
919 break;
920 case BFD_RELOC_8_PCREL:
921 case BFD_RELOC_16_PCREL:
922 case BFD_RELOC_32_PCREL:
923 case BFD_RELOC_8_GOT_PCREL:
924 case BFD_RELOC_16_GOT_PCREL:
925 case BFD_RELOC_32_GOT_PCREL:
926 case BFD_RELOC_8_GOTOFF:
927 case BFD_RELOC_16_GOTOFF:
928 case BFD_RELOC_32_GOTOFF:
929 case BFD_RELOC_8_PLT_PCREL:
930 case BFD_RELOC_16_PLT_PCREL:
931 case BFD_RELOC_32_PLT_PCREL:
932 case BFD_RELOC_8_PLTOFF:
933 case BFD_RELOC_16_PLTOFF:
934 case BFD_RELOC_32_PLTOFF:
935 break;
936 default:
937 as_bad_where (fixp->fx_file, fixp->fx_line,
938 _("Cannot make %s relocation PC relative"),
939 bfd_get_reloc_code_name (code));
940 }
941 }
942 }
943 else
944 {
945#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
946 switch (F (fixp->fx_size, fixp->fx_pcrel))
947 {
948#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
949 MAP (1, 0, BFD_RELOC_8);
950 MAP (2, 0, BFD_RELOC_16);
951 MAP (4, 0, BFD_RELOC_32);
952 MAP (1, 1, BFD_RELOC_8_PCREL);
953 MAP (2, 1, BFD_RELOC_16_PCREL);
954 MAP (4, 1, BFD_RELOC_32_PCREL);
955 default:
956 abort ();
957 }
958 }
959#undef F
960#undef MAP
961
962 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 963 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
964 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 965 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
966#ifndef OBJ_ELF
967 if (fixp->fx_pcrel)
968 reloc->addend = fixp->fx_addnumber;
969 else
970 reloc->addend = 0;
971#else
972 if (!fixp->fx_pcrel)
973 reloc->addend = fixp->fx_addnumber;
974 else
975 reloc->addend = (section->vma
8390138c
AS		 976 /* Explicit sign extension in case char is
977 unsigned. */
978 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 979 + fixp->fx_addnumber
980 + md_pcrel_from (fixp));
981#endif
982
983 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
984 assert (reloc->howto != 0);
985
986 return reloc;
987}
988
989#endif /* BFD_ASSEMBLER */
990
252b5132
RH		 991/* Handle of the OPCODE hash table. NULL means any use before
992 m68k_ip_begin() will crash. */
993static struct hash_control *op_hash;
994\f
995/* Assemble an m68k instruction. */
996
997static void
998m68k_ip (instring)
999 char *instring;
1000{
1001 register char *p;
1002 register struct m68k_op *opP;
1003 register const struct m68k_incant *opcode;
1004 register const char *s;
1005 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1006 char *pdot, *pdotmove;
1007 enum m68k_size siz1, siz2;
1008 char c;
1009 int losing;
1010 int opsfound;
1011 LITTLENUM_TYPE words[6];
1012 LITTLENUM_TYPE *wordp;
1013 unsigned long ok_arch = 0;
1014
1015 if (*instring == ' ')
1016 instring++; /* skip leading whitespace */
1017
1018 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1019 or exactly 1 space. */
252b5132
RH		 1020 pdot = 0;
1021 for (p = instring; *p != '\0'; p++)
1022 {
1023 if (*p == ' ')
1024 break;
1025 if (*p == '.')
1026 pdot = p;
1027 }
1028
1029 if (p == instring)
1030 {
1031 the_ins.error = _("No operator");
1032 return;
1033 }
1034
1035 /* p now points to the end of the opcode name, probably whitespace.
1036 Make sure the name is null terminated by clobbering the
1037 whitespace, look it up in the hash table, then fix it back.
1038 Remove a dot, first, since the opcode tables have none. */
1039 if (pdot != NULL)
1040 {
1041 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1042 *pdotmove = pdotmove[1];
1043 p--;
1044 }
1045
1046 c = *p;
1047 *p = '\0';
1048 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1049 *p = c;
1050
1051 if (pdot != NULL)
1052 {
1053 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1054 *pdotmove = pdotmove[-1];
1055 *pdot = '.';
1056 ++p;
1057 }
1058
1059 if (opcode == NULL)
1060 {
1061 the_ins.error = _("Unknown operator");
1062 return;
1063 }
1064
1065 /* found a legitimate opcode, start matching operands */
1066 while (*p == ' ')
1067 ++p;
1068
1069 if (opcode->m_operands == 0)
1070 {
1071 char *old = input_line_pointer;
1072 *old = '\n';
1073 input_line_pointer = p;
1074 /* Ahh - it's a motorola style psuedo op */
1075 mote_pseudo_table[opcode->m_opnum].poc_handler
1076 (mote_pseudo_table[opcode->m_opnum].poc_val);
1077 input_line_pointer = old;
1078 *old = 0;
1079
1080 return;
1081 }
1082
1083 if (flag_mri && opcode->m_opnum == 0)
1084 {
1085 /* In MRI mode, random garbage is allowed after an instruction
1086 which accepts no operands. */
1087 the_ins.args = opcode->m_operands;
1088 the_ins.numargs = opcode->m_opnum;
1089 the_ins.numo = opcode->m_codenum;
1090 the_ins.opcode[0] = getone (opcode);
1091 the_ins.opcode[1] = gettwo (opcode);
1092 return;
1093 }
1094
1095 for (opP = &the_ins.operands[0]; *p; opP++)
1096 {
1097 p = crack_operand (p, opP);
1098
1099 if (opP->error)
1100 {
1101 the_ins.error = opP->error;
1102 return;
1103 }
1104 }
1105
1106 opsfound = opP - &the_ins.operands[0];
1107
1108 /* This ugly hack is to support the floating pt opcodes in their
1109 standard form. Essentially, we fake a first enty of type COP#1 */
1110 if (opcode->m_operands[0] == 'I')
1111 {
1112 int n;
1113
1114 for (n = opsfound; n > 0; --n)
1115 the_ins.operands[n] = the_ins.operands[n - 1];
1116
1117 memset ((char *) (&the_ins.operands[0]), '\0',
1118 sizeof (the_ins.operands[0]));
1119 the_ins.operands[0].mode = CONTROL;
1120 the_ins.operands[0].reg = m68k_float_copnum;
1121 opsfound++;
1122 }
1123
1124 /* We've got the operands. Find an opcode that'll accept them */
1125 for (losing = 0;;)
1126 {
1127 /* If we didn't get the right number of ops, or we have no
92774660 1128 common model with this pattern then reject this pattern. */
252b5132
RH		 1129
1130 ok_arch |= opcode->m_arch;
1131 if (opsfound != opcode->m_opnum
1132 || ((opcode->m_arch & current_architecture) == 0))
1133 ++losing;
1134 else
1135 {
1136 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1137 *s && !losing;
1138 s += 2, opP++)
1139 {
1140 /* Warning: this switch is huge! */
1141 /* I've tried to organize the cases into this order:
1142 non-alpha first, then alpha by letter. Lower-case
1143 goes directly before uppercase counterpart. */
1144 /* Code with multiple case ...: gets sorted by the lowest
1145 case ... it belongs to. I hope this makes sense. */
1146 switch (*s)
1147 {
1148 case '!':
1149 switch (opP->mode)
1150 {
1151 case IMMED:
1152 case DREG:
1153 case AREG:
1154 case FPREG:
1155 case CONTROL:
1156 case AINC:
1157 case ADEC:
1158 case REGLST:
1159 losing++;
1160 break;
1161 default:
1162 break;
1163 }
1164 break;
1165
1166 case '<':
1167 switch (opP->mode)
1168 {
1169 case DREG:
1170 case AREG:
1171 case FPREG:
1172 case CONTROL:
1173 case IMMED:
1174 case ADEC:
1175 case REGLST:
1176 losing++;
1177 break;
1178 default:
1179 break;
1180 }
1181 break;
1182
1183 case '>':
1184 switch (opP->mode)
1185 {
1186 case DREG:
1187 case AREG:
1188 case FPREG:
1189 case CONTROL:
1190 case IMMED:
1191 case AINC:
1192 case REGLST:
1193 losing++;
1194 break;
1195 case ABSL:
1196 break;
1197 default:
1198 if (opP->reg == PC
1199 || opP->reg == ZPC)
1200 losing++;
1201 break;
1202 }
1203 break;
1204
1205 case 'm':
1206 switch (opP->mode)
1207 {
1208 case DREG:
1209 case AREG:
1210 case AINDR:
1211 case AINC:
1212 case ADEC:
1213 break;
1214 default:
1215 losing++;
1216 }
8a104df9 1217 break;
252b5132
RH		 1218
1219 case 'n':
1220 switch (opP->mode)
1221 {
1222 case DISP:
1223 break;
1224 default:
1225 losing++;
1226 }
8a104df9 1227 break;
252b5132
RH		 1228
1229 case 'o':
1230 switch (opP->mode)
1231 {
1232 case BASE:
1233 case ABSL:
1234 case IMMED:
1235 break;
1236 default:
1237 losing++;
1238 }
8a104df9 1239 break;
252b5132
RH		 1240
1241 case 'p':
1242 switch (opP->mode)
1243 {
1244 case DREG:
1245 case AREG:
1246 case AINDR:
1247 case AINC:
1248 case ADEC:
1249 break;
1250 case DISP:
1251 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1252 losing++;
252b5132
RH		 1253 break;
1254 default:
1255 losing++;
1256 }
8a104df9 1257 break;
252b5132
RH		 1258
1259 case 'q':
1260 switch (opP->mode)
1261 {
1262 case DREG:
1263 case AINDR:
1264 case AINC:
1265 case ADEC:
1266 break;
1267 case DISP:
1268 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1269 losing++;
252b5132
RH		 1270 break;
1271 default:
1272 losing++;
1273 break;
1274 }
8a104df9 1275 break;
252b5132
RH		 1276
1277 case 'v':
1278 switch (opP->mode)
1279 {
1280 case DREG:
1281 case AINDR:
1282 case AINC:
1283 case ADEC:
1284 case ABSL:
1285 break;
1286 case DISP:
1287 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1288 losing++;
252b5132
RH		 1289 break;
1290 default:
1291 losing++;
1292 break;
1293 }
1294 break;
1295
1296 case '#':
1297 if (opP->mode != IMMED)
1298 losing++;
1299 else if (s[1] == 'b'
1300 && ! isvar (&opP->disp)
1301 && (opP->disp.exp.X_op != O_constant
1302 || ! isbyte (opP->disp.exp.X_add_number)))
1303 losing++;
1304 else if (s[1] == 'B'
1305 && ! isvar (&opP->disp)
1306 && (opP->disp.exp.X_op != O_constant
1307 || ! issbyte (opP->disp.exp.X_add_number)))
1308 losing++;
1309 else if (s[1] == 'w'
1310 && ! isvar (&opP->disp)
1311 && (opP->disp.exp.X_op != O_constant
1312 || ! isword (opP->disp.exp.X_add_number)))
1313 losing++;
1314 else if (s[1] == 'W'
1315 && ! isvar (&opP->disp)
1316 && (opP->disp.exp.X_op != O_constant
1317 || ! issword (opP->disp.exp.X_add_number)))
1318 losing++;
1319 break;
1320
1321 case '^':
1322 case 'T':
1323 if (opP->mode != IMMED)
1324 losing++;
1325 break;
1326
1327 case '$':
1328 if (opP->mode == AREG
1329 || opP->mode == CONTROL
1330 || opP->mode == FPREG
1331 || opP->mode == IMMED
1332 || opP->mode == REGLST
1333 || (opP->mode != ABSL
1334 && (opP->reg == PC
1335 || opP->reg == ZPC)))
1336 losing++;
1337 break;
1338
1339 case '%':
1340 if (opP->mode == CONTROL
1341 || opP->mode == FPREG
1342 || opP->mode == REGLST
1343 || opP->mode == IMMED
1344 || (opP->mode != ABSL
1345 && (opP->reg == PC
1346 || opP->reg == ZPC)))
1347 losing++;
1348 break;
1349
1350 case '&':
1351 switch (opP->mode)
1352 {
1353 case DREG:
1354 case AREG:
1355 case FPREG:
1356 case CONTROL:
1357 case IMMED:
1358 case AINC:
1359 case ADEC:
1360 case REGLST:
1361 losing++;
1362 break;
1363 case ABSL:
1364 break;
1365 default:
1366 if (opP->reg == PC
1367 || opP->reg == ZPC)
1368 losing++;
1369 break;
1370 }
1371 break;
1372
1373 case '*':
1374 if (opP->mode == CONTROL
1375 || opP->mode == FPREG
1376 || opP->mode == REGLST)
1377 losing++;
1378 break;
1379
1380 case '+':
1381 if (opP->mode != AINC)
1382 losing++;
1383 break;
1384
1385 case '-':
1386 if (opP->mode != ADEC)
1387 losing++;
1388 break;
1389
1390 case '/':
1391 switch (opP->mode)
1392 {
1393 case AREG:
1394 case CONTROL:
1395 case FPREG:
1396 case AINC:
1397 case ADEC:
1398 case IMMED:
1399 case REGLST:
1400 losing++;
1401 break;
1402 default:
1403 break;
1404 }
1405 break;
1406
1407 case ';':
1408 switch (opP->mode)
1409 {
1410 case AREG:
1411 case CONTROL:
1412 case FPREG:
1413 case REGLST:
1414 losing++;
1415 break;
1416 default:
1417 break;
1418 }
1419 break;
1420
1421 case '?':
1422 switch (opP->mode)
1423 {
1424 case AREG:
1425 case CONTROL:
1426 case FPREG:
1427 case AINC:
1428 case ADEC:
1429 case IMMED:
1430 case REGLST:
1431 losing++;
1432 break;
1433 case ABSL:
1434 break;
1435 default:
1436 if (opP->reg == PC || opP->reg == ZPC)
1437 losing++;
1438 break;
1439 }
1440 break;
1441
1442 case '@':
1443 switch (opP->mode)
1444 {
1445 case AREG:
1446 case CONTROL:
1447 case FPREG:
1448 case IMMED:
1449 case REGLST:
1450 losing++;
1451 break;
1452 default:
1453 break;
1454 }
1455 break;
1456
1457 case '~': /* For now! (JF FOO is this right?) */
1458 switch (opP->mode)
1459 {
1460 case DREG:
1461 case AREG:
1462 case CONTROL:
1463 case FPREG:
1464 case IMMED:
1465 case REGLST:
1466 losing++;
1467 break;
1468 case ABSL:
1469 break;
1470 default:
1471 if (opP->reg == PC
1472 || opP->reg == ZPC)
1473 losing++;
1474 break;
1475 }
1476 break;
1477
1478 case '3':
1479 if (opP->mode != CONTROL
1480 || (opP->reg != TT0 && opP->reg != TT1))
1481 losing++;
1482 break;
1483
1484 case 'A':
1485 if (opP->mode != AREG)
1486 losing++;
1487 break;
1488
1489 case 'a':
1490 if (opP->mode != AINDR)
1491 ++losing;
1492 break;
1493
1494 case 'B': /* FOO */
1495 if (opP->mode != ABSL
1496 || (flag_long_jumps
1497 && strncmp (instring, "jbsr", 4) == 0))
1498 losing++;
1499 break;
1500
1501 case 'C':
1502 if (opP->mode != CONTROL || opP->reg != CCR)
1503 losing++;
1504 break;
1505
1506 case 'd':
1507 if (opP->mode != DISP
1508 || opP->reg < ADDR0
1509 || opP->reg > ADDR7)
1510 losing++;
1511 break;
1512
1513 case 'D':
1514 if (opP->mode != DREG)
1515 losing++;
1516 break;
1517
6da466c7
ILT		 1518 case 'E':
1519 if (opP->reg != ACC)
1520 losing++;
1521 break;
1522
252b5132
RH		 1523 case 'F':
1524 if (opP->mode != FPREG)
1525 losing++;
1526 break;
1527
6da466c7
ILT		 1528 case 'G':
1529 if (opP->reg != MACSR)
1530 losing++;
1531 break;
1532
1533 case 'H':
1534 if (opP->reg != MASK)
1535 losing++;
1536 break;
1537
252b5132
RH		 1538 case 'I':
1539 if (opP->mode != CONTROL
1540 || opP->reg < COP0
1541 || opP->reg > COP7)
1542 losing++;
1543 break;
1544
1545 case 'J':
1546 if (opP->mode != CONTROL
1547 || opP->reg < USP
1548 || opP->reg > last_movec_reg)
1549 losing++;
1550 else
1551 {
1552 const enum m68k_register *rp;
1553 for (rp = control_regs; *rp; rp++)
1554 if (*rp == opP->reg)
1555 break;
1556 if (*rp == 0)
1557 losing++;
1558 }
1559 break;
1560
1561 case 'k':
1562 if (opP->mode != IMMED)
1563 losing++;
1564 break;
1565
1566 case 'l':
1567 case 'L':
1568 if (opP->mode == DREG
1569 || opP->mode == AREG
1570 || opP->mode == FPREG)
1571 {
1572 if (s[1] == '8')
1573 losing++;
1574 else
1575 {
1576 switch (opP->mode)
1577 {
1578 case DREG:
1579 opP->mask = 1 << (opP->reg - DATA0);
1580 break;
1581 case AREG:
1582 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1583 break;
1584 case FPREG:
1585 opP->mask = 1 << (opP->reg - FP0 + 16);
1586 break;
1587 default:
1588 abort ();
1589 }
1590 opP->mode = REGLST;
1591 }
1592 }
1593 else if (opP->mode == CONTROL)
1594 {
1595 if (s[1] != '8')
1596 losing++;
1597 else
1598 {
1599 switch (opP->reg)
1600 {
1601 case FPI:
1602 opP->mask = 1 << 24;
1603 break;
1604 case FPS:
1605 opP->mask = 1 << 25;
1606 break;
1607 case FPC:
1608 opP->mask = 1 << 26;
1609 break;
1610 default:
1611 losing++;
1612 break;
1613 }
1614 opP->mode = REGLST;
1615 }
1616 }
1617 else if (opP->mode != REGLST)
1618 losing++;
1619 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1620 losing++;
1621 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1622 losing++;
1623 break;
1624
1625 case 'M':
1626 if (opP->mode != IMMED)
1627 losing++;
1628 else if (opP->disp.exp.X_op != O_constant
1629 || ! issbyte (opP->disp.exp.X_add_number))
1630 losing++;
1631 else if (! m68k_quick
1632 && instring[3] != 'q'
1633 && instring[4] != 'q')
1634 losing++;
1635 break;
1636
1637 case 'O':
1638 if (opP->mode != DREG
1639 && opP->mode != IMMED
1640 && opP->mode != ABSL)
1641 losing++;
1642 break;
1643
1644 case 'Q':
1645 if (opP->mode != IMMED)
1646 losing++;
1647 else if (opP->disp.exp.X_op != O_constant
1648 || opP->disp.exp.X_add_number < 1
1649 || opP->disp.exp.X_add_number > 8)
1650 losing++;
1651 else if (! m68k_quick
1652 && (strncmp (instring, "add", 3) == 0
1653 || strncmp (instring, "sub", 3) == 0)
1654 && instring[3] != 'q')
1655 losing++;
1656 break;
1657
1658 case 'R':
1659 if (opP->mode != DREG && opP->mode != AREG)
1660 losing++;
1661 break;
1662
1663 case 'r':
1664 if (opP->mode != AINDR
1665 && (opP->mode != BASE
1666 || (opP->reg != 0
1667 && opP->reg != ZADDR0)
1668 || opP->disp.exp.X_op != O_absent
1669 || ((opP->index.reg < DATA0
1670 || opP->index.reg > DATA7)
1671 && (opP->index.reg < ADDR0
1672 || opP->index.reg > ADDR7))
1673 || opP->index.size != SIZE_UNSPEC
1674 || opP->index.scale != 1))
1675 losing++;
1676 break;
1677
1678 case 's':
1679 if (opP->mode != CONTROL
1680 || ! (opP->reg == FPI
1681 || opP->reg == FPS
1682 || opP->reg == FPC))
1683 losing++;
1684 break;
1685
1686 case 'S':
1687 if (opP->mode != CONTROL || opP->reg != SR)
1688 losing++;
1689 break;
1690
1691 case 't':
1692 if (opP->mode != IMMED)
1693 losing++;
1694 else if (opP->disp.exp.X_op != O_constant
1695 || opP->disp.exp.X_add_number < 0
1696 || opP->disp.exp.X_add_number > 7)
1697 losing++;
1698 break;
1699
1700 case 'U':
1701 if (opP->mode != CONTROL || opP->reg != USP)
1702 losing++;
1703 break;
1704
1705 /* JF these are out of order. We could put them
1706 in order if we were willing to put up with
1707 bunches of #ifdef m68851s in the code.
1708
1709 Don't forget that you need these operands
1710 to use 68030 MMU instructions. */
1711#ifndef NO_68851
1712 /* Memory addressing mode used by pflushr */
1713 case '|':
1714 if (opP->mode == CONTROL
1715 || opP->mode == FPREG
1716 || opP->mode == DREG
1717 || opP->mode == AREG
1718 || opP->mode == REGLST)
1719 losing++;
1720 /* We should accept immediate operands, but they
1721 supposedly have to be quad word, and we don't
1722 handle that. I would like to see what a Motorola
1723 assembler does before doing something here. */
1724 if (opP->mode == IMMED)
1725 losing++;
1726 break;
1727
1728 case 'f':
1729 if (opP->mode != CONTROL
1730 || (opP->reg != SFC && opP->reg != DFC))
1731 losing++;
1732 break;
1733
1734 case '0':
1735 if (opP->mode != CONTROL || opP->reg != TC)
1736 losing++;
1737 break;
1738
1739 case '1':
1740 if (opP->mode != CONTROL || opP->reg != AC)
1741 losing++;
1742 break;
1743
1744 case '2':
1745 if (opP->mode != CONTROL
1746 || (opP->reg != CAL
1747 && opP->reg != VAL
1748 && opP->reg != SCC))
1749 losing++;
1750 break;
1751
1752 case 'V':
1753 if (opP->mode != CONTROL
1754 || opP->reg != VAL)
1755 losing++;
1756 break;
1757
1758 case 'W':
1759 if (opP->mode != CONTROL
1760 || (opP->reg != DRP
1761 && opP->reg != SRP
1762 && opP->reg != CRP))
1763 losing++;
1764 break;
1765
1766 case 'X':
1767 if (opP->mode != CONTROL
1768 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1769 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1770 losing++;
1771 break;
1772
1773 case 'Y':
1774 if (opP->mode != CONTROL || opP->reg != PSR)
1775 losing++;
1776 break;
1777
1778 case 'Z':
1779 if (opP->mode != CONTROL || opP->reg != PCSR)
1780 losing++;
1781 break;
1782#endif
1783 case 'c':
1784 if (opP->mode != CONTROL
1785 || (opP->reg != NC
1786 && opP->reg != IC
1787 && opP->reg != DC
1788 && opP->reg != BC))
1789 {
1790 losing++;
92774660 1791 } /* not a cache specifier. */
252b5132
RH		 1792 break;
1793
1794 case '_':
1795 if (opP->mode != ABSL)
1796 ++losing;
1797 break;
1798
6da466c7
ILT		 1799 case 'u':
1800 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1801 losing++;
1802 /* FIXME: kludge instead of fixing parser:
1803 upper/lower registers are *not* CONTROL
92774660 1804 registers, but ordinary ones. */
6da466c7
ILT		 1805 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1806 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1807 opP->mode = DREG;
1808 else
1809 opP->mode = AREG;
1810 break;
1811
252b5132
RH		 1812 default:
1813 abort ();
1814 } /* switch on type of operand */
1815
1816 if (losing)
1817 break;
1818 } /* for each operand */
1819 } /* if immediately wrong */
1820
1821 if (!losing)
1822 {
1823 break;
92774660 1824 } /* got it. */
252b5132
RH		 1825
1826 opcode = opcode->m_next;
1827
1828 if (!opcode)
1829 {
1830 if (ok_arch
1831 && !(ok_arch & current_architecture))
1832 {
1833 char buf[200], *cp;
1834
1835 strcpy (buf,
1836 _("invalid instruction for this architecture; needs "));
1837 cp = buf + strlen (buf);
1838 switch (ok_arch)
1839 {
1840 case mfloat:
1841 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1842 break;
1843 case mmmu:
1844 strcpy (cp, _("mmu (68030 or 68851)"));
1845 break;
1846 case m68020up:
1847 strcpy (cp, _("68020 or higher"));
1848 break;
1849 case m68000up:
1850 strcpy (cp, _("68000 or higher"));
1851 break;
1852 case m68010up:
1853 strcpy (cp, _("68010 or higher"));
1854 break;
1855 default:
1856 {
1857 int got_one = 0, idx;
8fce3f5e
AM		 1858 for (idx = 0;
1859 idx < (int) (sizeof (archs) / sizeof (archs[0]));
252b5132
RH		 1860 idx++)
1861 {
1862 if ((archs[idx].arch & ok_arch)
1863 && ! archs[idx].alias)
1864 {
1865 if (got_one)
1866 {
1867 strcpy (cp, " or ");
1868 cp += strlen (cp);
1869 }
1870 got_one = 1;
1871 strcpy (cp, archs[idx].name);
1872 cp += strlen (cp);
1873 }
1874 }
1875 }
1876 }
1877 cp = xmalloc (strlen (buf) + 1);
1878 strcpy (cp, buf);
1879 the_ins.error = cp;
1880 }
1881 else
1882 the_ins.error = _("operands mismatch");
1883 return;
1884 } /* Fell off the end */
1885
1886 losing = 0;
1887 }
1888
1889 /* now assemble it */
1890
1891 the_ins.args = opcode->m_operands;
1892 the_ins.numargs = opcode->m_opnum;
1893 the_ins.numo = opcode->m_codenum;
1894 the_ins.opcode[0] = getone (opcode);
1895 the_ins.opcode[1] = gettwo (opcode);
1896
1897 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1898 {
1899 /* This switch is a doozy.
1900 Watch the first step; its a big one! */
1901 switch (s[0])
1902 {
1903
1904 case '*':
1905 case '~':
1906 case '%':
1907 case ';':
1908 case '@':
1909 case '!':
1910 case '&':
1911 case '$':
1912 case '?':
1913 case '/':
1914 case '<':
1915 case '>':
1916 case 'm':
1917 case 'n':
1918 case 'o':
1919 case 'p':
1920 case 'q':
1921 case 'v':
1922#ifndef NO_68851
1923 case '|':
1924#endif
1925 switch (opP->mode)
1926 {
1927 case IMMED:
1928 tmpreg = 0x3c; /* 7.4 */
1929 if (strchr ("bwl", s[1]))
1930 nextword = get_num (&opP->disp, 80);
1931 else
1932 nextword = get_num (&opP->disp, 0);
1933 if (isvar (&opP->disp))
1934 add_fix (s[1], &opP->disp, 0, 0);
1935 switch (s[1])
1936 {
1937 case 'b':
1938 if (!isbyte (nextword))
1939 opP->error = _("operand out of range");
1940 addword (nextword);
1941 baseo = 0;
1942 break;
1943 case 'w':
1944 if (!isword (nextword))
1945 opP->error = _("operand out of range");
1946 addword (nextword);
1947 baseo = 0;
1948 break;
1949 case 'W':
1950 if (!issword (nextword))
1951 opP->error = _("operand out of range");
1952 addword (nextword);
1953 baseo = 0;
1954 break;
1955 case 'l':
1956 addword (nextword >> 16);
1957 addword (nextword);
1958 baseo = 0;
1959 break;
1960
1961 case 'f':
1962 baseo = 2;
1963 outro = 8;
1964 break;
1965 case 'F':
1966 baseo = 4;
1967 outro = 11;
1968 break;
1969 case 'x':
1970 baseo = 6;
1971 outro = 15;
1972 break;
1973 case 'p':
1974 baseo = 6;
1975 outro = -1;
1976 break;
1977 default:
1978 abort ();
1979 }
1980 if (!baseo)
1981 break;
1982
1983 /* We gotta put out some float */
1984 if (op (&opP->disp) != O_big)
1985 {
1986 valueT val;
1987 int gencnt;
1988
1989 /* Can other cases happen here? */
1990 if (op (&opP->disp) != O_constant)
1991 abort ();
1992
1993 val = (valueT) offs (&opP->disp);
1994 gencnt = 0;
1995 do
1996 {
1997 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1998 val >>= LITTLENUM_NUMBER_OF_BITS;
1999 ++gencnt;
2000 }
2001 while (val != 0);
2002 offs (&opP->disp) = gencnt;
2003 }
2004 if (offs (&opP->disp) > 0)
2005 {
2006 if (offs (&opP->disp) > baseo)
2007 {
2008 as_warn (_("Bignum too big for %c format; truncated"),
2009 s[1]);
2010 offs (&opP->disp) = baseo;
2011 }
2012 baseo -= offs (&opP->disp);
2013 while (baseo--)
2014 addword (0);
2015 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2016 offs (&opP->disp)--;
2017 --wordp)
2018 addword (*wordp);
2019 break;
2020 }
2021 gen_to_words (words, baseo, (long) outro);
2022 for (wordp = words; baseo--; wordp++)
2023 addword (*wordp);
2024 break;
2025 case DREG:
2026 tmpreg = opP->reg - DATA; /* 0.dreg */
2027 break;
2028 case AREG:
2029 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2030 break;
2031 case AINDR:
2032 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2033 break;
2034 case ADEC:
2035 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2036 break;
2037 case AINC:
2038 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2039 break;
2040 case DISP:
2041
2042 nextword = get_num (&opP->disp, 80);
2043
2044 if (opP->reg == PC
2045 && ! isvar (&opP->disp)
2046 && m68k_abspcadd)
2047 {
2048 opP->disp.exp.X_op = O_symbol;
2049#ifndef BFD_ASSEMBLER
2050 opP->disp.exp.X_add_symbol = &abs_symbol;
2051#else
2052 opP->disp.exp.X_add_symbol =
2053 section_symbol (absolute_section);
2054#endif
2055 }
2056
2057 /* Force into index mode. Hope this works */
2058
2059 /* We do the first bit for 32-bit displacements, and the
2060 second bit for 16 bit ones. It is possible that we
2061 should make the default be WORD instead of LONG, but
2062 I think that'd break GCC, so we put up with a little
2063 inefficiency for the sake of working output. */
2064
2065 if (!issword (nextword)
2066 || (isvar (&opP->disp)
2067 && ((opP->disp.size == SIZE_UNSPEC
2068 && flag_short_refs == 0
2069 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2070 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2071 || opP->disp.size == SIZE_LONG)))
2072 {
2073 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2074 || arch_coldfire_p (current_architecture))
252b5132
RH		 2075 opP->error =
2076 _("displacement too large for this architecture; needs 68020 or higher");
2077 if (opP->reg == PC)
2078 tmpreg = 0x3B; /* 7.3 */
2079 else
2080 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2081 if (isvar (&opP->disp))
2082 {
2083 if (opP->reg == PC)
2084 {
2085 if (opP->disp.size == SIZE_LONG
2086#ifdef OBJ_ELF
2087 /* If the displacement needs pic
2088 relocation it cannot be relaxed. */
2089 || opP->disp.pic_reloc != pic_none
2090#endif
2091 )
2092 {
2093 addword (0x0170);
2094 add_fix ('l', &opP->disp, 1, 2);
2095 }
2096 else
2097 {
2098 add_frag (adds (&opP->disp),
2099 offs (&opP->disp),
151337e8 2100 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2101 break;
2102 }
2103 }
2104 else
2105 {
2106 addword (0x0170);
2107 add_fix ('l', &opP->disp, 0, 0);
2108 }
2109 }
2110 else
2111 addword (0x0170);
2112 addword (nextword >> 16);
2113 }
2114 else
2115 {
2116 if (opP->reg == PC)
2117 tmpreg = 0x3A; /* 7.2 */
2118 else
2119 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2120
2121 if (isvar (&opP->disp))
2122 {
2123 if (opP->reg == PC)
2124 {
2125 add_fix ('w', &opP->disp, 1, 0);
2126 }
2127 else
2128 add_fix ('w', &opP->disp, 0, 0);
2129 }
2130 }
2131 addword (nextword);
2132 break;
2133
2134 case POST:
2135 case PRE:
2136 case BASE:
2137 nextword = 0;
2138 baseo = get_num (&opP->disp, 80);
2139 if (opP->mode == POST || opP->mode == PRE)
2140 outro = get_num (&opP->odisp, 80);
2141 /* Figure out the `addressing mode'.
2142 Also turn on the BASE_DISABLE bit, if needed. */
2143 if (opP->reg == PC || opP->reg == ZPC)
2144 {
2145 tmpreg = 0x3b; /* 7.3 */
2146 if (opP->reg == ZPC)
2147 nextword |= 0x80;
2148 }
2149 else if (opP->reg == 0)
2150 {
2151 nextword |= 0x80;
2152 tmpreg = 0x30; /* 6.garbage */
2153 }
2154 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2155 {
2156 nextword |= 0x80;
2157 tmpreg = 0x30 + opP->reg - ZADDR0;
2158 }
2159 else
2160 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2161
2162 siz1 = opP->disp.size;
2163 if (opP->mode == POST || opP->mode == PRE)
2164 siz2 = opP->odisp.size;
2165 else
2166 siz2 = SIZE_UNSPEC;
2167
2168 /* Index register stuff */
2169 if (opP->index.reg != 0
2170 && opP->index.reg >= DATA
2171 && opP->index.reg <= ADDR7)
2172 {
2173 nextword |= (opP->index.reg - DATA) << 12;
2174
2175 if (opP->index.size == SIZE_LONG
2176 || (opP->index.size == SIZE_UNSPEC
2177 && m68k_index_width_default == SIZE_LONG))
2178 nextword |= 0x800;
2179
92774660 2180 if ((opP->index.scale != 1
252b5132 2181 && cpu_of_arch (current_architecture) < m68020)
92774660 2182 || (opP->index.scale == 8
6da466c7 2183 && arch_coldfire_p (current_architecture)))
252b5132
RH		 2184 {
2185 opP->error =
2186 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2187 }
2188
6da466c7
ILT		 2189 if (arch_coldfire_p (current_architecture)
2190 && opP->index.size == SIZE_WORD)
2191 opP->error = _("invalid index size for coldfire");
2192
252b5132
RH		 2193 switch (opP->index.scale)
2194 {
2195 case 1:
2196 break;
2197 case 2:
2198 nextword |= 0x200;
2199 break;
2200 case 4:
2201 nextword |= 0x400;
2202 break;
2203 case 8:
2204 nextword |= 0x600;
2205 break;
2206 default:
2207 abort ();
2208 }
2209 /* IF its simple,
2210 GET US OUT OF HERE! */
2211
2212 /* Must be INDEX, with an index register. Address
2213 register cannot be ZERO-PC, and either :b was
2214 forced, or we know it will fit. For a 68000 or
2215 68010, force this mode anyways, because the
2216 larger modes aren't supported. */
2217 if (opP->mode == BASE
2218 && ((opP->reg >= ADDR0
2219 && opP->reg <= ADDR7)
2220 || opP->reg == PC))
2221 {
2222 if (siz1 == SIZE_BYTE
2223 || cpu_of_arch (current_architecture) < m68020
6da466c7 2224 || arch_coldfire_p (current_architecture)
252b5132
RH		 2225 || (siz1 == SIZE_UNSPEC
2226 && ! isvar (&opP->disp)
2227 && issbyte (baseo)))
2228 {
2229 nextword += baseo & 0xff;
2230 addword (nextword);
2231 if (isvar (&opP->disp))
2232 {
2233 /* Do a byte relocation. If it doesn't
2234 fit (possible on m68000) let the
2235 fixup processing complain later. */
2236 if (opP->reg == PC)
2237 add_fix ('B', &opP->disp, 1, 1);
2238 else
2239 add_fix ('B', &opP->disp, 0, 0);
2240 }
2241 else if (siz1 != SIZE_BYTE)
2242 {
2243 if (siz1 != SIZE_UNSPEC)
2244 as_warn (_("Forcing byte displacement"));
2245 if (! issbyte (baseo))
2246 opP->error = _("byte displacement out of range");
2247 }
2248
2249 break;
2250 }
2251 else if (siz1 == SIZE_UNSPEC
2252 && opP->reg == PC
2253 && isvar (&opP->disp)
2254 && subs (&opP->disp) == NULL
2255#ifdef OBJ_ELF
2256 /* If the displacement needs pic
2257 relocation it cannot be relaxed. */
2258 && opP->disp.pic_reloc == pic_none
2259#endif
2260 )
2261 {
2262 /* The code in md_convert_frag_1 needs to be
2263 able to adjust nextword. Call frag_grow
2264 to ensure that we have enough space in
2265 the frag obstack to make all the bytes
2266 contiguous. */
2267 frag_grow (14);
8a104df9
KH		 2268 nextword += baseo & 0xff;
2269 addword (nextword);
2270 add_frag (adds (&opP->disp), offs (&opP->disp),
2271 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2272
2273 break;
8a104df9 2274 }
252b5132
RH		 2275 }
2276 }
2277 else
2278 {
2279 nextword |= 0x40; /* No index reg */
2280 if (opP->index.reg >= ZDATA0
2281 && opP->index.reg <= ZDATA7)
2282 nextword |= (opP->index.reg - ZDATA0) << 12;
2283 else if (opP->index.reg >= ZADDR0
2284 || opP->index.reg <= ZADDR7)
2285 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2286 }
2287
2288 /* It isn't simple. */
2289
2290 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2291 || arch_coldfire_p (current_architecture))
252b5132
RH		 2292 opP->error =
2293 _("invalid operand mode for this architecture; needs 68020 or higher");
2294
2295 nextword |= 0x100;
2296 /* If the guy specified a width, we assume that it is
2297 wide enough. Maybe it isn't. If so, we lose. */
2298 switch (siz1)
2299 {
2300 case SIZE_UNSPEC:
2301 if (isvar (&opP->disp)
2302 ? m68k_rel32
2303 : ! issword (baseo))
2304 {
2305 siz1 = SIZE_LONG;
2306 nextword |= 0x30;
2307 }
2308 else if (! isvar (&opP->disp) && baseo == 0)
2309 nextword |= 0x10;
2310 else
2311 {
2312 nextword |= 0x20;
2313 siz1 = SIZE_WORD;
2314 }
2315 break;
2316 case SIZE_BYTE:
2317 as_warn (_(":b not permitted; defaulting to :w"));
2318 /* Fall through. */
2319 case SIZE_WORD:
2320 nextword |= 0x20;
2321 break;
2322 case SIZE_LONG:
2323 nextword |= 0x30;
2324 break;
2325 }
2326
2327 /* Figure out innner displacement stuff */
2328 if (opP->mode == POST || opP->mode == PRE)
2329 {
2330 if (cpu_of_arch (current_architecture) & cpu32)
2331 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2332 switch (siz2)
2333 {
2334 case SIZE_UNSPEC:
2335 if (isvar (&opP->odisp)
2336 ? m68k_rel32
2337 : ! issword (outro))
2338 {
2339 siz2 = SIZE_LONG;
2340 nextword |= 0x3;
2341 }
2342 else if (! isvar (&opP->odisp) && outro == 0)
2343 nextword |= 0x1;
2344 else
2345 {
2346 nextword |= 0x2;
2347 siz2 = SIZE_WORD;
2348 }
2349 break;
2350 case 1:
2351 as_warn (_(":b not permitted; defaulting to :w"));
2352 /* Fall through. */
2353 case 2:
2354 nextword |= 0x2;
2355 break;
2356 case 3:
2357 nextword |= 0x3;
2358 break;
2359 }
2360 if (opP->mode == POST
2361 && (nextword & 0x40) == 0)
2362 nextword |= 0x04;
2363 }
2364 addword (nextword);
2365
2366 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2367 {
2368 if (opP->reg == PC || opP->reg == ZPC)
2369 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2370 else
2371 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2372 }
2373 if (siz1 == SIZE_LONG)
2374 addword (baseo >> 16);
2375 if (siz1 != SIZE_UNSPEC)
2376 addword (baseo);
2377
2378 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2379 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2380 if (siz2 == SIZE_LONG)
2381 addword (outro >> 16);
2382 if (siz2 != SIZE_UNSPEC)
2383 addword (outro);
2384
2385 break;
2386
2387 case ABSL:
2388 nextword = get_num (&opP->disp, 80);
2389 switch (opP->disp.size)
2390 {
2391 default:
2392 abort ();
2393 case SIZE_UNSPEC:
2394 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2395 {
2396 tmpreg = 0x38; /* 7.0 */
2397 addword (nextword);
2398 break;
2399 }
252b5132
RH		 2400 if (isvar (&opP->disp)
2401 && !subs (&opP->disp)
2402 && adds (&opP->disp)
2403#ifdef OBJ_ELF
2404 /* If the displacement needs pic relocation it
2405 cannot be relaxed. */
2406 && opP->disp.pic_reloc == pic_none
2407#endif
252b5132
RH		 2408 && !flag_long_jumps
2409 && !strchr ("~%&$?", s[0]))
2410 {
2411 tmpreg = 0x3A; /* 7.2 */
2412 add_frag (adds (&opP->disp),
2413 offs (&opP->disp),
151337e8 2414 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2415 break;
2416 }
2417 /* Fall through into long */
2418 case SIZE_LONG:
2419 if (isvar (&opP->disp))
2420 add_fix ('l', &opP->disp, 0, 0);
2421
2422 tmpreg = 0x39;/* 7.1 mode */
2423 addword (nextword >> 16);
2424 addword (nextword);
2425 break;
2426
2427 case SIZE_BYTE:
2428 as_bad (_("unsupported byte value; use a different suffix"));
2429 /* Fall through. */
2430 case SIZE_WORD: /* Word */
2431 if (isvar (&opP->disp))
2432 add_fix ('w', &opP->disp, 0, 0);
2433
2434 tmpreg = 0x38;/* 7.0 mode */
2435 addword (nextword);
2436 break;
2437 }
2438 break;
2439 case CONTROL:
2440 case FPREG:
2441 default:
2442 as_bad (_("unknown/incorrect operand"));
bc805888 2443 /* abort (); */
252b5132
RH		 2444 }
2445 install_gen_operand (s[1], tmpreg);
2446 break;
2447
2448 case '#':
2449 case '^':
2450 switch (s[1])
2451 { /* JF: I hate floating point! */
2452 case 'j':
2453 tmpreg = 70;
2454 break;
2455 case '8':
2456 tmpreg = 20;
2457 break;
2458 case 'C':
2459 tmpreg = 50;
2460 break;
2461 case '3':
2462 default:
2463 tmpreg = 80;
2464 break;
2465 }
2466 tmpreg = get_num (&opP->disp, tmpreg);
2467 if (isvar (&opP->disp))
2468 add_fix (s[1], &opP->disp, 0, 0);
2469 switch (s[1])
2470 {
2471 case 'b': /* Danger: These do no check for
2472 certain types of overflow.
2473 user beware! */
2474 if (!isbyte (tmpreg))
2475 opP->error = _("out of range");
2476 insop (tmpreg, opcode);
2477 if (isvar (&opP->disp))
2478 the_ins.reloc[the_ins.nrel - 1].n =
2479 (opcode->m_codenum) * 2 + 1;
2480 break;
2481 case 'B':
2482 if (!issbyte (tmpreg))
2483 opP->error = _("out of range");
2484 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2485 if (isvar (&opP->disp))
2486 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2487 break;
2488 case 'w':
2489 if (!isword (tmpreg))
2490 opP->error = _("out of range");
2491 insop (tmpreg, opcode);
2492 if (isvar (&opP->disp))
2493 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2494 break;
2495 case 'W':
2496 if (!issword (tmpreg))
2497 opP->error = _("out of range");
2498 insop (tmpreg, opcode);
2499 if (isvar (&opP->disp))
2500 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2501 break;
2502 case 'l':
2503 /* Because of the way insop works, we put these two out
2504 backwards. */
2505 insop (tmpreg, opcode);
2506 insop (tmpreg >> 16, opcode);
2507 if (isvar (&opP->disp))
2508 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2509 break;
2510 case '3':
2511 tmpreg &= 0xFF;
2512 case '8':
2513 case 'C':
2514 case 'j':
2515 install_operand (s[1], tmpreg);
2516 break;
2517 default:
2518 abort ();
2519 }
2520 break;
2521
2522 case '+':
2523 case '-':
2524 case 'A':
2525 case 'a':
2526 install_operand (s[1], opP->reg - ADDR);
2527 break;
2528
2529 case 'B':
2530 tmpreg = get_num (&opP->disp, 80);
2531 switch (s[1])
2532 {
2533 case 'B':
8390138c 2534 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 2535 break;
2536 case 'W':
2537 add_fix ('w', &opP->disp, 1, 0);
2538 addword (0);
2539 break;
2540 case 'L':
2541 long_branch:
151337e8 2542 if (! HAVE_LONG_BRANCH (current_architecture))
81d4177b 2543 as_warn (_("Can't use long branches on 68000/68010/5200"));
151337e8 2544 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2545 add_fix ('l', &opP->disp, 1, 0);
2546 addword (0);
2547 addword (0);
2548 break;
2549 case 'g':
2550 if (subs (&opP->disp)) /* We can't relax it */
2551 goto long_branch;
2552
2553#ifdef OBJ_ELF
2554 /* If the displacement needs pic relocation it cannot be
2555 relaxed. */
2556 if (opP->disp.pic_reloc != pic_none)
2557 goto long_branch;
2558#endif
252b5132 2559 /* This could either be a symbol, or an absolute
151337e8
NC		 2560 address. If it's an absolute address, turn it into
2561 an absolute jump right here and keep it out of the
2562 relaxer. */
2563 if (adds (&opP->disp) == 0)
2564 {
2565 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 2566 the_ins.opcode[0] = 0x4EF9;
151337e8 2567 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 2568 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 2569 else /* jCC */
2570 {
2571 the_ins.opcode[0] ^= 0x0100;
2572 the_ins.opcode[0] |= 0x0006;
18566f55 2573 addword (0x4EF9);
151337e8
NC		 2574 }
2575 add_fix ('l', &opP->disp, 0, 0);
2576 addword (0);
2577 addword (0);
2578 break;
2579 }
2580
2581 /* Now we know it's going into the relaxer. Now figure
2582 out which mode. We try in this order of preference:
2583 long branch, absolute jump, byte/word branches only. */
2584 if (HAVE_LONG_BRANCH (current_architecture))
252b5132 2585 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8
NC		 2586 TAB (BRANCHBWL, SZ_UNDEF));
2587 else if (! flag_keep_pcrel)
2588 {
2589 if ((the_ins.opcode[0] == 0x6000)
2590 || (the_ins.opcode[0] == 0x6100))
2591 add_frag (adds (&opP->disp), offs (&opP->disp),
2592 TAB (BRABSJUNC, SZ_UNDEF));
2593 else
2594 add_frag (adds (&opP->disp), offs (&opP->disp),
2595 TAB (BRABSJCOND, SZ_UNDEF));
2596 }
252b5132
RH		 2597 else
2598 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8 2599 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 2600 break;
2601 case 'w':
2602 if (isvar (&opP->disp))
2603 {
151337e8
NC		 2604 /* Check for DBcc instructions. We can relax them,
2605 but only if we have long branches and/or absolute
2606 jumps. */
2607 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2608 && (HAVE_LONG_BRANCH (current_architecture)
2609 || (! flag_keep_pcrel)))
252b5132 2610 {
151337e8
NC		 2611 if (HAVE_LONG_BRANCH (current_architecture))
2612 add_frag (adds (&opP->disp), offs (&opP->disp),
2613 TAB (DBCCLBR, SZ_UNDEF));
2614 else
2615 add_frag (adds (&opP->disp), offs (&opP->disp),
2616 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 2617 break;
2618 }
252b5132
RH		 2619 add_fix ('w', &opP->disp, 1, 0);
2620 }
2621 addword (0);
2622 break;
2623 case 'C': /* Fixed size LONG coproc branches */
2624 add_fix ('l', &opP->disp, 1, 0);
2625 addword (0);
2626 addword (0);
2627 break;
2628 case 'c': /* Var size Coprocesssor branches */
151337e8 2629 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 2630 {
252b5132
RH		 2631 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2632 add_fix ('l', &opP->disp, 1, 0);
2633 addword (0);
2634 addword (0);
2635 }
151337e8
NC		 2636 else
2637 add_frag (adds (&opP->disp), offs (&opP->disp),
2638 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 2639 break;
2640 default:
2641 abort ();
2642 }
2643 break;
2644
2645 case 'C': /* Ignore it */
2646 break;
2647
2648 case 'd': /* JF this is a kludge */
2649 install_operand ('s', opP->reg - ADDR);
2650 tmpreg = get_num (&opP->disp, 80);
2651 if (!issword (tmpreg))
2652 {
2653 as_warn (_("Expression out of range, using 0"));
2654 tmpreg = 0;
2655 }
2656 addword (tmpreg);
2657 break;
2658
2659 case 'D':
2660 install_operand (s[1], opP->reg - DATA);
2661 break;
2662
6da466c7
ILT		 2663 case 'E': /* Ignore it */
2664 break;
2665
252b5132
RH		 2666 case 'F':
2667 install_operand (s[1], opP->reg - FP0);
2668 break;
2669
6da466c7
ILT		 2670 case 'G': /* Ignore it */
2671 case 'H':
2672 break;
2673
252b5132
RH		 2674 case 'I':
2675 tmpreg = opP->reg - COP0;
2676 install_operand (s[1], tmpreg);
2677 break;
2678
2679 case 'J': /* JF foo */
2680 switch (opP->reg)
2681 {
2682 case SFC:
2683 tmpreg = 0x000;
2684 break;
2685 case DFC:
2686 tmpreg = 0x001;
2687 break;
2688 case CACR:
2689 tmpreg = 0x002;
2690 break;
2691 case TC:
2692 tmpreg = 0x003;
2693 break;
2694 case ITT0:
2695 tmpreg = 0x004;
2696 break;
2697 case ITT1:
2698 tmpreg = 0x005;
2699 break;
2700 case DTT0:
2701 tmpreg = 0x006;
2702 break;
2703 case DTT1:
2704 tmpreg = 0x007;
2705 break;
2706 case BUSCR:
2707 tmpreg = 0x008;
2708 break;
2709
2710 case USP:
2711 tmpreg = 0x800;
2712 break;
2713 case VBR:
2714 tmpreg = 0x801;
2715 break;
2716 case CAAR:
2717 tmpreg = 0x802;
2718 break;
2719 case MSP:
2720 tmpreg = 0x803;
2721 break;
2722 case ISP:
2723 tmpreg = 0x804;
2724 break;
2725 case MMUSR:
2726 tmpreg = 0x805;
2727 break;
2728 case URP:
2729 tmpreg = 0x806;
2730 break;
2731 case SRP:
2732 tmpreg = 0x807;
2733 break;
2734 case PCR:
2735 tmpreg = 0x808;
2736 break;
2737 case ROMBAR:
2738 tmpreg = 0xC00;
2739 break;
2740 case RAMBAR0:
2741 tmpreg = 0xC04;
2742 break;
2743 case RAMBAR1:
2744 tmpreg = 0xC05;
2745 break;
2746 case MBAR:
2747 tmpreg = 0xC0F;
2748 break;
2749 default:
2750 abort ();
2751 }
2752 install_operand (s[1], tmpreg);
2753 break;
2754
2755 case 'k':
2756 tmpreg = get_num (&opP->disp, 55);
2757 install_operand (s[1], tmpreg & 0x7f);
2758 break;
2759
2760 case 'l':
2761 tmpreg = opP->mask;
2762 if (s[1] == 'w')
2763 {
2764 if (tmpreg & 0x7FF0000)
2765 as_bad (_("Floating point register in register list"));
2766 insop (reverse_16_bits (tmpreg), opcode);
2767 }
2768 else
2769 {
2770 if (tmpreg & 0x700FFFF)
2771 as_bad (_("Wrong register in floating-point reglist"));
2772 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2773 }
2774 break;
2775
2776 case 'L':
2777 tmpreg = opP->mask;
2778 if (s[1] == 'w')
2779 {
2780 if (tmpreg & 0x7FF0000)
2781 as_bad (_("Floating point register in register list"));
2782 insop (tmpreg, opcode);
2783 }
2784 else if (s[1] == '8')
2785 {
2786 if (tmpreg & 0x0FFFFFF)
2787 as_bad (_("incorrect register in reglist"));
2788 install_operand (s[1], tmpreg >> 24);
2789 }
2790 else
2791 {
2792 if (tmpreg & 0x700FFFF)
2793 as_bad (_("wrong register in floating-point reglist"));
2794 else
2795 install_operand (s[1], tmpreg >> 16);
2796 }
2797 break;
2798
2799 case 'M':
2800 install_operand (s[1], get_num (&opP->disp, 60));
2801 break;
2802
2803 case 'O':
2804 tmpreg = ((opP->mode == DREG)
8fce3f5e 2805 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 2806 : (get_num (&opP->disp, 40) & 0x1F));
2807 install_operand (s[1], tmpreg);
2808 break;
2809
2810 case 'Q':
2811 tmpreg = get_num (&opP->disp, 10);
2812 if (tmpreg == 8)
2813 tmpreg = 0;
2814 install_operand (s[1], tmpreg);
2815 break;
2816
2817 case 'R':
2818 /* This depends on the fact that ADDR registers are eight
2819 more than their corresponding DATA regs, so the result
2820 will have the ADDR_REG bit set */
2821 install_operand (s[1], opP->reg - DATA);
2822 break;
2823
2824 case 'r':
2825 if (opP->mode == AINDR)
2826 install_operand (s[1], opP->reg - DATA);
2827 else
2828 install_operand (s[1], opP->index.reg - DATA);
2829 break;
2830
2831 case 's':
2832 if (opP->reg == FPI)
2833 tmpreg = 0x1;
2834 else if (opP->reg == FPS)
2835 tmpreg = 0x2;
2836 else if (opP->reg == FPC)
2837 tmpreg = 0x4;
2838 else
2839 abort ();
2840 install_operand (s[1], tmpreg);
2841 break;
2842
2843 case 'S': /* Ignore it */
2844 break;
2845
2846 case 'T':
2847 install_operand (s[1], get_num (&opP->disp, 30));
2848 break;
2849
2850 case 'U': /* Ignore it */
2851 break;
2852
2853 case 'c':
2854 switch (opP->reg)
2855 {
2856 case NC:
2857 tmpreg = 0;
2858 break;
2859 case DC:
2860 tmpreg = 1;
2861 break;
2862 case IC:
2863 tmpreg = 2;
2864 break;
2865 case BC:
2866 tmpreg = 3;
2867 break;
2868 default:
2869 as_fatal (_("failed sanity check"));
2870 } /* switch on cache token */
2871 install_operand (s[1], tmpreg);
2872 break;
2873#ifndef NO_68851
92774660 2874 /* JF: These are out of order, I fear. */
252b5132
RH		 2875 case 'f':
2876 switch (opP->reg)
2877 {
2878 case SFC:
2879 tmpreg = 0;
2880 break;
2881 case DFC:
2882 tmpreg = 1;
2883 break;
2884 default:
2885 abort ();
2886 }
2887 install_operand (s[1], tmpreg);
2888 break;
2889
2890 case '0':
2891 case '1':
2892 case '2':
2893 switch (opP->reg)
2894 {
2895 case TC:
2896 tmpreg = 0;
2897 break;
2898 case CAL:
2899 tmpreg = 4;
2900 break;
2901 case VAL:
2902 tmpreg = 5;
2903 break;
2904 case SCC:
2905 tmpreg = 6;
2906 break;
2907 case AC:
2908 tmpreg = 7;
2909 break;
2910 default:
2911 abort ();
2912 }
2913 install_operand (s[1], tmpreg);
2914 break;
2915
2916 case 'V':
2917 if (opP->reg == VAL)
2918 break;
2919 abort ();
2920
2921 case 'W':
2922 switch (opP->reg)
2923 {
2924 case DRP:
2925 tmpreg = 1;
2926 break;
2927 case SRP:
2928 tmpreg = 2;
2929 break;
2930 case CRP:
2931 tmpreg = 3;
2932 break;
2933 default:
2934 abort ();
2935 }
2936 install_operand (s[1], tmpreg);
2937 break;
2938
2939 case 'X':
2940 switch (opP->reg)
2941 {
2942 case BAD:
2943 case BAD + 1:
2944 case BAD + 2:
2945 case BAD + 3:
2946 case BAD + 4:
2947 case BAD + 5:
2948 case BAD + 6:
2949 case BAD + 7:
2950 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2951 break;
2952
2953 case BAC:
2954 case BAC + 1:
2955 case BAC + 2:
2956 case BAC + 3:
2957 case BAC + 4:
2958 case BAC + 5:
2959 case BAC + 6:
2960 case BAC + 7:
2961 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2962 break;
2963
2964 default:
2965 abort ();
2966 }
2967 install_operand (s[1], tmpreg);
2968 break;
2969 case 'Y':
2970 know (opP->reg == PSR);
2971 break;
2972 case 'Z':
2973 know (opP->reg == PCSR);
2974 break;
2975#endif /* m68851 */
2976 case '3':
2977 switch (opP->reg)
2978 {
2979 case TT0:
2980 tmpreg = 2;
2981 break;
2982 case TT1:
2983 tmpreg = 3;
2984 break;
2985 default:
2986 abort ();
2987 }
2988 install_operand (s[1], tmpreg);
2989 break;
2990 case 't':
2991 tmpreg = get_num (&opP->disp, 20);
2992 install_operand (s[1], tmpreg);
2993 break;
2994 case '_': /* used only for move16 absolute 32-bit address */
2995 if (isvar (&opP->disp))
2996 add_fix ('l', &opP->disp, 0, 0);
2997 tmpreg = get_num (&opP->disp, 80);
2998 addword (tmpreg >> 16);
2999 addword (tmpreg & 0xFFFF);
3000 break;
6da466c7
ILT		 3001 case 'u':
3002 install_operand (s[1], opP->reg - DATA0L);
3003 opP->reg -= (DATA0L);
3004 opP->reg &= 0x0F; /* remove upper/lower bit */
3005 break;
252b5132
RH		 3006 default:
3007 abort ();
3008 }
3009 }
3010
3011 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3012 instruction, ready to be emitted. . . */
252b5132
RH		 3013}
3014
3015static int
3016reverse_16_bits (in)
3017 int in;
3018{
3019 int out = 0;
3020 int n;
3021
3022 static int mask[16] =
3023 {
3024 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3025 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3026 };
3027 for (n = 0; n < 16; n++)
3028 {
3029 if (in & mask[n])
3030 out |= mask[15 - n];
3031 }
3032 return out;
3033} /* reverse_16_bits() */
3034
3035static int
3036reverse_8_bits (in)
3037 int in;
3038{
3039 int out = 0;
3040 int n;
3041
3042 static int mask[8] =
3043 {
3044 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3045 };
3046
3047 for (n = 0; n < 8; n++)
3048 {
3049 if (in & mask[n])
3050 out |= mask[7 - n];
3051 }
3052 return out;
3053} /* reverse_8_bits() */
3054
3055/* Cause an extra frag to be generated here, inserting up to 10 bytes
3056 (that value is chosen in the frag_var call in md_assemble). TYPE
3057 is the subtype of the frag to be generated; its primary type is
3058 rs_machine_dependent.
3059
3060 The TYPE parameter is also used by md_convert_frag_1 and
3061 md_estimate_size_before_relax. The appropriate type of fixup will
3062 be emitted by md_convert_frag_1.
3063
3064 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3065static void
3066install_operand (mode, val)
3067 int mode;
3068 int val;
3069{
3070 switch (mode)
3071 {
3072 case 's':
3073 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3074 break;
3075 case 'd':
3076 the_ins.opcode[0] |= val << 9;
3077 break;
3078 case '1':
3079 the_ins.opcode[1] |= val << 12;
3080 break;
3081 case '2':
3082 the_ins.opcode[1] |= val << 6;
3083 break;
3084 case '3':
3085 the_ins.opcode[1] |= val;
3086 break;
3087 case '4':
3088 the_ins.opcode[2] |= val << 12;
3089 break;
3090 case '5':
3091 the_ins.opcode[2] |= val << 6;
3092 break;
3093 case '6':
3094 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3095 three words long! */
3096 the_ins.numo++;
3097 the_ins.opcode[2] |= val;
3098 break;
3099 case '7':
3100 the_ins.opcode[1] |= val << 7;
3101 break;
3102 case '8':
3103 the_ins.opcode[1] |= val << 10;
3104 break;
3105#ifndef NO_68851
3106 case '9':
3107 the_ins.opcode[1] |= val << 5;
3108 break;
3109#endif
3110
3111 case 't':
3112 the_ins.opcode[1] |= (val << 10) | (val << 7);
3113 break;
3114 case 'D':
3115 the_ins.opcode[1] |= (val << 12) | val;
3116 break;
3117 case 'g':
3118 the_ins.opcode[0] |= val = 0xff;
3119 break;
3120 case 'i':
3121 the_ins.opcode[0] |= val << 9;
3122 break;
3123 case 'C':
3124 the_ins.opcode[1] |= val;
3125 break;
3126 case 'j':
3127 the_ins.opcode[1] |= val;
3128 the_ins.numo++; /* What a hack */
3129 break;
3130 case 'k':
3131 the_ins.opcode[1] |= val << 4;
3132 break;
3133 case 'b':
3134 case 'w':
3135 case 'W':
3136 case 'l':
3137 break;
3138 case 'e':
3139 the_ins.opcode[0] |= (val << 6);
3140 break;
3141 case 'L':
3142 the_ins.opcode[1] = (val >> 16);
3143 the_ins.opcode[2] = val & 0xffff;
3144 break;
6da466c7
ILT		 3145 case 'm':
3146 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3147 the_ins.opcode[0] |= ((val & 0x7) << 9);
3148 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3149 break;
3150 case 'n':
3151 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3152 the_ins.opcode[0] |= ((val & 0x7) << 9);
3153 break;
3154 case 'o':
3155 the_ins.opcode[1] |= val << 12;
3156 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3157 break;
3158 case 'M':
3159 the_ins.opcode[0] |= (val & 0xF);
3160 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3161 break;
3162 case 'N':
3163 the_ins.opcode[1] |= (val & 0xF);
3164 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3165 break;
3166 case 'h':
3167 the_ins.opcode[1] |= ((val != 1) << 10);
3168 break;
252b5132
RH		 3169 case 'c':
3170 default:
3171 as_fatal (_("failed sanity check."));
3172 }
3173} /* install_operand() */
3174
3175static void
3176install_gen_operand (mode, val)
3177 int mode;
3178 int val;
3179{
3180 switch (mode)
3181 {
3182 case 's':
3183 the_ins.opcode[0] |= val;
3184 break;
3185 case 'd':
3186 /* This is a kludge!!! */
3187 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3188 break;
3189 case 'b':
3190 case 'w':
3191 case 'l':
3192 case 'f':
3193 case 'F':
3194 case 'x':
3195 case 'p':
3196 the_ins.opcode[0] |= val;
3197 break;
3198 /* more stuff goes here */
3199 default:
3200 as_fatal (_("failed sanity check."));
3201 }
3202} /* install_gen_operand() */
3203
3204/*
3205 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3206 * then deal with the bitfield hack.
3207 */
3208
3209static char *
3210crack_operand (str, opP)
3211 register char *str;
3212 register struct m68k_op *opP;
3213{
3214 register int parens;
3215 register int c;
3216 register char *beg_str;
3217 int inquote = 0;
3218
3219 if (!str)
3220 {
3221 return str;
3222 }
3223 beg_str = str;
3224 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3225 {
3226 if (! inquote)
3227 {
3228 if (*str == '(')
3229 parens++;
3230 else if (*str == ')')
3231 {
3232 if (!parens)
3233 { /* ERROR */
3234 opP->error = _("Extra )");
3235 return str;
3236 }
3237 --parens;
3238 }
3239 }
3240 if (flag_mri && *str == '\'')
3241 inquote = ! inquote;
3242 }
3243 if (!*str && parens)
3244 { /* ERROR */
3245 opP->error = _("Missing )");
3246 return str;
3247 }
3248 c = *str;
3249 *str = '\0';
3250 if (m68k_ip_op (beg_str, opP) != 0)
3251 {
3252 *str = c;
3253 return str;
3254 }
3255 *str = c;
3256 if (c == '}')
3257 c = *++str; /* JF bitfield hack */
3258 if (c)
3259 {
3260 c = *++str;
3261 if (!c)
3262 as_bad (_("Missing operand"));
3263 }
3264
3265 /* Detect MRI REG symbols and convert them to REGLSTs. */
3266 if (opP->mode == CONTROL && (int)opP->reg < 0)
3267 {
3268 opP->mode = REGLST;
3269 opP->mask = ~(int)opP->reg;
3270 opP->reg = 0;
3271 }
3272
3273 return str;
3274}
3275
3276/* This is the guts of the machine-dependent assembler. STR points to a
3277 machine dependent instruction. This function is supposed to emit
3278 the frags/bytes it assembles to.
3279 */
3280
3281static void
3282insert_reg (regname, regnum)
3283 const char *regname;
3284 int regnum;
3285{
3286 char buf[100];
3287 int i;
3288
3289#ifdef REGISTER_PREFIX
3290 if (!flag_reg_prefix_optional)
3291 {
3292 buf[0] = REGISTER_PREFIX;
3293 strcpy (buf + 1, regname);
3294 regname = buf;
3295 }
3296#endif
3297
3298 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3299 &zero_address_frag));
3300
3301 for (i = 0; regname[i]; i++)
3882b010 3302 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 3303 buf[i] = '\0';
3304
3305 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3306 &zero_address_frag));
3307}
3308
3309struct init_entry
3310 {
3311 const char *name;
3312 int number;
3313 };
3314
3315static const struct init_entry init_table[] =
3316{
3317 { "d0", DATA0 },
3318 { "d1", DATA1 },
3319 { "d2", DATA2 },
3320 { "d3", DATA3 },
3321 { "d4", DATA4 },
3322 { "d5", DATA5 },
3323 { "d6", DATA6 },
3324 { "d7", DATA7 },
3325 { "a0", ADDR0 },
3326 { "a1", ADDR1 },
3327 { "a2", ADDR2 },
3328 { "a3", ADDR3 },
3329 { "a4", ADDR4 },
3330 { "a5", ADDR5 },
3331 { "a6", ADDR6 },
3332 { "fp", ADDR6 },
3333 { "a7", ADDR7 },
3334 { "sp", ADDR7 },
3335 { "ssp", ADDR7 },
3336 { "fp0", FP0 },
3337 { "fp1", FP1 },
3338 { "fp2", FP2 },
3339 { "fp3", FP3 },
3340 { "fp4", FP4 },
3341 { "fp5", FP5 },
3342 { "fp6", FP6 },
3343 { "fp7", FP7 },
3344 { "fpi", FPI },
3345 { "fpiar", FPI },
3346 { "fpc", FPI },
3347 { "fps", FPS },
3348 { "fpsr", FPS },
3349 { "fpc", FPC },
3350 { "fpcr", FPC },
3351 { "control", FPC },
3352 { "status", FPS },
3353 { "iaddr", FPI },
3354
3355 { "cop0", COP0 },
3356 { "cop1", COP1 },
3357 { "cop2", COP2 },
3358 { "cop3", COP3 },
3359 { "cop4", COP4 },
3360 { "cop5", COP5 },
3361 { "cop6", COP6 },
3362 { "cop7", COP7 },
3363 { "pc", PC },
3364 { "zpc", ZPC },
3365 { "sr", SR },
3366
3367 { "ccr", CCR },
3368 { "cc", CCR },
3369
6da466c7
ILT		 3370 { "acc", ACC },
3371 { "macsr", MACSR },
3372 { "mask", MASK },
3373
252b5132
RH		 3374 /* control registers */
3375 { "sfc", SFC }, /* Source Function Code */
3376 { "sfcr", SFC },
3377 { "dfc", DFC }, /* Destination Function Code */
3378 { "dfcr", DFC },
3379 { "cacr", CACR }, /* Cache Control Register */
3380 { "caar", CAAR }, /* Cache Address Register */
3381
3382 { "usp", USP }, /* User Stack Pointer */
3383 { "vbr", VBR }, /* Vector Base Register */
3384 { "msp", MSP }, /* Master Stack Pointer */
3385 { "isp", ISP }, /* Interrupt Stack Pointer */
3386
3387 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3388 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3389 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3390 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3391
3392 /* 68ec040 versions of same */
3393 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3394 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3395 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3396 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3397
3398 /* mcf5200 versions of same. The ColdFire programmer's reference
3399 manual indicated that the order is 2,3,0,1, but Ken Rose
3400 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3401 { "acr0", ITT0 }, /* Access Control Unit 0 */
3402 { "acr1", ITT1 }, /* Access Control Unit 1 */
3403 { "acr2", DTT0 }, /* Access Control Unit 2 */
3404 { "acr3", DTT1 }, /* Access Control Unit 3 */
3405
3406 { "tc", TC }, /* MMU Translation Control Register */
3407 { "tcr", TC },
3408
3409 { "mmusr", MMUSR }, /* MMU Status Register */
3410 { "srp", SRP }, /* User Root Pointer */
3411 { "urp", URP }, /* Supervisor Root Pointer */
3412
3413 { "buscr", BUSCR },
3414 { "pcr", PCR },
3415
3416 { "rombar", ROMBAR }, /* ROM Base Address Register */
3417 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3418 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3419 { "mbar", MBAR }, /* Module Base Address Register */
3420 /* end of control registers */
3421
3422 { "ac", AC },
3423 { "bc", BC },
3424 { "cal", CAL },
3425 { "crp", CRP },
3426 { "drp", DRP },
3427 { "pcsr", PCSR },
3428 { "psr", PSR },
3429 { "scc", SCC },
3430 { "val", VAL },
3431 { "bad0", BAD0 },
3432 { "bad1", BAD1 },
3433 { "bad2", BAD2 },
3434 { "bad3", BAD3 },
3435 { "bad4", BAD4 },
3436 { "bad5", BAD5 },
3437 { "bad6", BAD6 },
3438 { "bad7", BAD7 },
3439 { "bac0", BAC0 },
3440 { "bac1", BAC1 },
3441 { "bac2", BAC2 },
3442 { "bac3", BAC3 },
3443 { "bac4", BAC4 },
3444 { "bac5", BAC5 },
3445 { "bac6", BAC6 },
3446 { "bac7", BAC7 },
3447
3448 { "ic", IC },
3449 { "dc", DC },
3450 { "nc", NC },
3451
3452 { "tt0", TT0 },
3453 { "tt1", TT1 },
3454 /* 68ec030 versions of same */
3455 { "ac0", TT0 },
3456 { "ac1", TT1 },
3457 /* 68ec030 access control unit, identical to 030 MMU status reg */
3458 { "acusr", PSR },
3459
3460 /* Suppressed data and address registers. */
3461 { "zd0", ZDATA0 },
3462 { "zd1", ZDATA1 },
3463 { "zd2", ZDATA2 },
3464 { "zd3", ZDATA3 },
3465 { "zd4", ZDATA4 },
3466 { "zd5", ZDATA5 },
3467 { "zd6", ZDATA6 },
3468 { "zd7", ZDATA7 },
3469 { "za0", ZADDR0 },
3470 { "za1", ZADDR1 },
3471 { "za2", ZADDR2 },
3472 { "za3", ZADDR3 },
3473 { "za4", ZADDR4 },
3474 { "za5", ZADDR5 },
3475 { "za6", ZADDR6 },
3476 { "za7", ZADDR7 },
3477
92774660 3478 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 3479 { "d0l", DATA0L },
3480 { "d1l", DATA1L },
3481 { "d2l", DATA2L },
3482 { "d3l", DATA3L },
3483 { "d4l", DATA4L },
3484 { "d5l", DATA5L },
3485 { "d6l", DATA6L },
3486 { "d7l", DATA7L },
3487
3488 { "a0l", ADDR0L },
3489 { "a1l", ADDR1L },
3490 { "a2l", ADDR2L },
3491 { "a3l", ADDR3L },
3492 { "a4l", ADDR4L },
3493 { "a5l", ADDR5L },
3494 { "a6l", ADDR6L },
3495 { "a7l", ADDR7L },
3496
3497 { "d0u", DATA0U },
3498 { "d1u", DATA1U },
3499 { "d2u", DATA2U },
3500 { "d3u", DATA3U },
3501 { "d4u", DATA4U },
3502 { "d5u", DATA5U },
3503 { "d6u", DATA6U },
3504 { "d7u", DATA7U },
3505
3506 { "a0u", ADDR0U },
3507 { "a1u", ADDR1U },
3508 { "a2u", ADDR2U },
3509 { "a3u", ADDR3U },
3510 { "a4u", ADDR4U },
3511 { "a5u", ADDR5U },
3512 { "a6u", ADDR6U },
3513 { "a7u", ADDR7U },
3514
252b5132
RH		 3515 { 0, 0 }
3516};
3517
3518static void
3519init_regtable ()
3520{
3521 int i;
3522 for (i = 0; init_table[i].name; i++)
3523 insert_reg (init_table[i].name, init_table[i].number);
3524}
3525
3526static int no_68851, no_68881;
3527
3528#ifdef OBJ_AOUT
3529/* a.out machine type. Default to 68020. */
3530int m68k_aout_machtype = 2;
3531#endif
3532
3533void
3534md_assemble (str)
3535 char *str;
3536{
3537 const char *er;
3538 short *fromP;
3539 char *toP = NULL;
3540 int m, n = 0;
3541 char *to_beg_P;
3542 int shorts_this_frag;
3543 fixS *fixP;
3544
3545 /* In MRI mode, the instruction and operands are separated by a
3546 space. Anything following the operands is a comment. The label
3547 has already been removed. */
3548 if (flag_mri)
3549 {
3550 char *s;
3551 int fields = 0;
3552 int infield = 0;
3553 int inquote = 0;
3554
3555 for (s = str; *s != '\0'; s++)
3556 {
3557 if ((*s == ' ' || *s == '\t') && ! inquote)
3558 {
3559 if (infield)
3560 {
3561 ++fields;
3562 if (fields >= 2)
3563 {
3564 *s = '\0';
3565 break;
3566 }
3567 infield = 0;
3568 }
3569 }
3570 else
3571 {
3572 if (! infield)
3573 infield = 1;
3574 if (*s == '\'')
3575 inquote = ! inquote;
3576 }
3577 }
3578 }
3579
3580 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3581 m68k_ip (str);
3582 er = the_ins.error;
3583 if (!er)
3584 {
3585 for (n = 0; n < the_ins.numargs; n++)
3586 if (the_ins.operands[n].error)
3587 {
3588 er = the_ins.operands[n].error;
3589 break;
3590 }
3591 }
3592 if (er)
3593 {
3594 as_bad (_("%s -- statement `%s' ignored"), er, str);
3595 return;
3596 }
3597
3598 /* If there is a current label, record that it marks an instruction. */
3599 if (current_label != NULL)
3600 {
3601 current_label->text = 1;
3602 current_label = NULL;
3603 }
3604
f27a3839
AS		 3605#ifdef OBJ_ELF
3606 /* Tie dwarf2 debug info to the address at the start of the insn. */
3607 dwarf2_emit_insn (0);
3608#endif
3609
252b5132
RH		 3610 if (the_ins.nfrag == 0)
3611 {
3612 /* No frag hacking involved; just put it out */
3613 toP = frag_more (2 * the_ins.numo);
3614 fromP = &the_ins.opcode[0];
3615 for (m = the_ins.numo; m; --m)
3616 {
3617 md_number_to_chars (toP, (long) (*fromP), 2);
3618 toP += 2;
3619 fromP++;
3620 }
3621 /* put out symbol-dependent info */
3622 for (m = 0; m < the_ins.nrel; m++)
3623 {
3624 switch (the_ins.reloc[m].wid)
3625 {
3626 case 'B':
3627 n = 1;
3628 break;
3629 case 'b':
3630 n = 1;
3631 break;
3632 case '3':
3633 n = 1;
3634 break;
3635 case 'w':
3636 case 'W':
3637 n = 2;
3638 break;
3639 case 'l':
3640 n = 4;
3641 break;
3642 default:
3643 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3644 the_ins.reloc[m].wid);
3645 }
3646
3647 fixP = fix_new_exp (frag_now,
3648 ((toP - frag_now->fr_literal)
3649 - the_ins.numo * 2 + the_ins.reloc[m].n),
3650 n,
3651 &the_ins.reloc[m].exp,
3652 the_ins.reloc[m].pcrel,
3653 get_reloc_code (n, the_ins.reloc[m].pcrel,
3654 the_ins.reloc[m].pic_reloc));
3655 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3656 if (the_ins.reloc[m].wid == 'B')
3657 fixP->fx_signed = 1;
3658 }
3659 return;
3660 }
3661
3662 /* There's some frag hacking */
fbe572f9
AM		 3663 {
3664 /* Calculate the max frag size. */
3665 int wid;
3666
3667 wid = 2 * the_ins.fragb[0].fragoff;
3668 for (n = 1; n < the_ins.nfrag; n++)
3669 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3670 /* frag_var part. */
3671 wid += 10;
3672 /* Make sure the whole insn fits in one chunk, in particular that
3673 the var part is attached, as we access one byte before the
3674 variable frag for byte branches. */
3675 frag_grow (wid);
3676 }
3677
252b5132
RH		 3678 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3679 {
3680 int wid;
3681
3682 if (n == 0)
3683 wid = 2 * the_ins.fragb[n].fragoff;
3684 else
3685 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3686 toP = frag_more (wid);
3687 to_beg_P = toP;
3688 shorts_this_frag = 0;
3689 for (m = wid / 2; m; --m)
3690 {
3691 md_number_to_chars (toP, (long) (*fromP), 2);
3692 toP += 2;
3693 fromP++;
3694 shorts_this_frag++;
3695 }
3696 for (m = 0; m < the_ins.nrel; m++)
3697 {
3698 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3699 {
3700 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3701 break;
3702 }
3703 wid = the_ins.reloc[m].wid;
3704 if (wid == 0)
3705 continue;
3706 the_ins.reloc[m].wid = 0;
3707 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3708
3709 fixP = fix_new_exp (frag_now,
3710 ((toP - frag_now->fr_literal)
3711 - the_ins.numo * 2 + the_ins.reloc[m].n),
3712 wid,
3713 &the_ins.reloc[m].exp,
3714 the_ins.reloc[m].pcrel,
3715 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3716 the_ins.reloc[m].pic_reloc));
3717 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3718 }
3719 (void) frag_var (rs_machine_dependent, 10, 0,
3720 (relax_substateT) (the_ins.fragb[n].fragty),
3721 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3722 }
3723 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3724 shorts_this_frag = 0;
3725 if (n)
3726 {
3727 toP = frag_more (n * sizeof (short));
3728 while (n--)
3729 {
3730 md_number_to_chars (toP, (long) (*fromP), 2);
3731 toP += 2;
3732 fromP++;
3733 shorts_this_frag++;
3734 }
3735 }
3736 for (m = 0; m < the_ins.nrel; m++)
3737 {
3738 int wid;
3739
3740 wid = the_ins.reloc[m].wid;
3741 if (wid == 0)
3742 continue;
3743 the_ins.reloc[m].wid = 0;
3744 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3745
3746 fixP = fix_new_exp (frag_now,
3747 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3748 - shorts_this_frag * 2),
3749 wid,
3750 &the_ins.reloc[m].exp,
3751 the_ins.reloc[m].pcrel,
3752 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3753 the_ins.reloc[m].pic_reloc));
3754 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3755 }
3756}
3757
3758void
3759md_begin ()
3760{
3761 /*
3762 * md_begin -- set up hash tables with 68000 instructions.
3763 * similar to what the vax assembler does. ---phr
3764 */
3765 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3766 a copy of it at runtime, adding in the information we want but isn't
3767 there. I think it'd be better to have an awk script hack the table
3768 at compile time. Or even just xstr the table and use it as-is. But
3769 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3770 names. */
3771
94f592af
NC		 3772 const struct m68k_opcode *ins;
3773 struct m68k_incant *hack, *slak;
3774 const char *retval = 0; /* empty string, or error msg text */
3775 int i;
252b5132
RH		 3776
3777 if (flag_mri)
3778 {
3779 flag_reg_prefix_optional = 1;
3780 m68k_abspcadd = 1;
3781 if (! m68k_rel32_from_cmdline)
3782 m68k_rel32 = 0;
3783 }
3784
3785 op_hash = hash_new ();
3786
3787 obstack_begin (&robyn, 4000);
3788 for (i = 0; i < m68k_numopcodes; i++)
3789 {
3790 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3791 do
3792 {
3793 ins = &m68k_opcodes[i];
3794 /* We *could* ignore insns that don't match our arch here
92774660 3795 but just leaving them out of the hash. */
252b5132
RH		 3796 slak->m_operands = ins->args;
3797 slak->m_opnum = strlen (slak->m_operands) / 2;
3798 slak->m_arch = ins->arch;
3799 slak->m_opcode = ins->opcode;
3800 /* This is kludgey */
3801 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3802 if (i + 1 != m68k_numopcodes
3803 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3804 {
3805 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3806 i++;
3807 }
3808 else
3809 slak->m_next = 0;
3810 slak = slak->m_next;
3811 }
3812 while (slak);
3813
3814 retval = hash_insert (op_hash, ins->name, (char *) hack);
3815 if (retval)
3816 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3817 }
3818
3819 for (i = 0; i < m68k_numaliases; i++)
3820 {
3821 const char *name = m68k_opcode_aliases[i].primary;
3822 const char *alias = m68k_opcode_aliases[i].alias;
3823 PTR val = hash_find (op_hash, name);
3824 if (!val)
3825 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3826 retval = hash_insert (op_hash, alias, val);
3827 if (retval)
3828 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3829 }
3830
3831 /* In MRI mode, all unsized branches are variable sized. Normally,
3832 they are word sized. */
3833 if (flag_mri)
3834 {
3835 static struct m68k_opcode_alias mri_aliases[] =
3836 {
3837 { "bhi", "jhi", },
3838 { "bls", "jls", },
3839 { "bcc", "jcc", },
3840 { "bcs", "jcs", },
3841 { "bne", "jne", },
3842 { "beq", "jeq", },
3843 { "bvc", "jvc", },
3844 { "bvs", "jvs", },
3845 { "bpl", "jpl", },
3846 { "bmi", "jmi", },
3847 { "bge", "jge", },
3848 { "blt", "jlt", },
3849 { "bgt", "jgt", },
3850 { "ble", "jle", },
3851 { "bra", "jra", },
3852 { "bsr", "jbsr", },
3853 };
3854
8fce3f5e
AM		 3855 for (i = 0;
3856 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
3857 i++)
252b5132
RH		 3858 {
3859 const char *name = mri_aliases[i].primary;
3860 const char *alias = mri_aliases[i].alias;
3861 PTR val = hash_find (op_hash, name);
3862 if (!val)
3863 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3864 retval = hash_jam (op_hash, alias, val);
3865 if (retval)
3866 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3867 }
3868 }
3869
8fce3f5e 3870 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 3871 {
3872 notend_table[i] = 0;
3873 alt_notend_table[i] = 0;
3874 }
3875 notend_table[','] = 1;
3876 notend_table['{'] = 1;
3877 notend_table['}'] = 1;
3878 alt_notend_table['a'] = 1;
3879 alt_notend_table['A'] = 1;
3880 alt_notend_table['d'] = 1;
3881 alt_notend_table['D'] = 1;
3882 alt_notend_table['#'] = 1;
3883 alt_notend_table['&'] = 1;
3884 alt_notend_table['f'] = 1;
3885 alt_notend_table['F'] = 1;
3886#ifdef REGISTER_PREFIX
3887 alt_notend_table[REGISTER_PREFIX] = 1;
3888#endif
3889
3890 /* We need to put '(' in alt_notend_table to handle
3891 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3892 */
3893 alt_notend_table['('] = 1;
3894
3895 /* We need to put '@' in alt_notend_table to handle
3896 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3897 */
3898 alt_notend_table['@'] = 1;
3899
3900 /* We need to put digits in alt_notend_table to handle
3901 bfextu %d0{24:1},%d0
3902 */
3903 alt_notend_table['0'] = 1;
3904 alt_notend_table['1'] = 1;
3905 alt_notend_table['2'] = 1;
3906 alt_notend_table['3'] = 1;
3907 alt_notend_table['4'] = 1;
3908 alt_notend_table['5'] = 1;
3909 alt_notend_table['6'] = 1;
3910 alt_notend_table['7'] = 1;
3911 alt_notend_table['8'] = 1;
3912 alt_notend_table['9'] = 1;
3913
3914#ifndef MIT_SYNTAX_ONLY
3915 /* Insert pseudo ops, these have to go into the opcode table since
3916 gas expects pseudo ops to start with a dot */
3917 {
3918 int n = 0;
3919 while (mote_pseudo_table[n].poc_name)
3920 {
3921 hack = (struct m68k_incant *)
3922 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3923 hash_insert (op_hash,
3924 mote_pseudo_table[n].poc_name, (char *) hack);
3925 hack->m_operands = 0;
3926 hack->m_opnum = n;
3927 n++;
3928 }
3929 }
3930#endif
3931
3932 init_regtable ();
3933
3934#ifdef OBJ_ELF
3935 record_alignment (text_section, 2);
3936 record_alignment (data_section, 2);
3937 record_alignment (bss_section, 2);
3938#endif
3939}
3940
3941static void
3942select_control_regs ()
3943{
3944 /* Note which set of "movec" control registers is available. */
3945 switch (cpu_of_arch (current_architecture))
3946 {
4f2a7c9e
NC		 3947 case 0:
3948 as_warn (_("architecture not yet selected: defaulting to 68020"));
3949 control_regs = m68020_control_regs;
3950 break;
3951
252b5132
RH		 3952 case m68000:
3953 control_regs = m68000_control_regs;
3954 break;
3955 case m68010:
3956 control_regs = m68010_control_regs;
3957 break;
3958 case m68020:
3959 case m68030:
3960 control_regs = m68020_control_regs;
3961 break;
3962 case m68040:
3963 control_regs = m68040_control_regs;
3964 break;
3965 case m68060:
3966 control_regs = m68060_control_regs;
3967 break;
3968 case cpu32:
3969 control_regs = cpu32_control_regs;
3970 break;
3971 case mcf5200:
6da466c7
ILT		 3972 case mcf5206e:
3973 case mcf5307:
dc84e067 3974 case mcf5407:
6da466c7 3975 control_regs = mcf_control_regs;
252b5132
RH		 3976 break;
3977 default:
3978 abort ();
3979 }
3980}
3981
3982void
3983m68k_init_after_args ()
3984{
3985 if (cpu_of_arch (current_architecture) == 0)
3986 {
3987 int i;
3988 const char *default_cpu = TARGET_CPU;
3989
3990 if (*default_cpu == 'm')
3991 default_cpu++;
3992 for (i = 0; i < n_archs; i++)
3993 if (strcasecmp (default_cpu, archs[i].name) == 0)
3994 break;
3995 if (i == n_archs)
3996 {
3997 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
3998 current_architecture |= m68020;
3999 }
4000 else
4001 current_architecture |= archs[i].arch;
4002 }
4003 /* Permit m68881 specification with all cpus; those that can't work
4004 with a coprocessor could be doing emulation. */
4005 if (current_architecture & m68851)
4006 {
4007 if (current_architecture & m68040)
4008 {
4009 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4010 }
4011 }
4012 /* What other incompatibilities could we check for? */
4013
4014 /* Toss in some default assumptions about coprocessors. */
4015 if (!no_68881
4016 && (cpu_of_arch (current_architecture)
4017 /* Can CPU32 have a 68881 coprocessor?? */
4018 & (m68020 | m68030 | cpu32)))
4019 {
4020 current_architecture |= m68881;
4021 }
4022 if (!no_68851
4023 && (cpu_of_arch (current_architecture) & m68020up) != 0
4024 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4025 {
4026 current_architecture |= m68851;
4027 }
4028 if (no_68881 && (current_architecture & m68881))
4029 as_bad (_("options for 68881 and no-68881 both given"));
4030 if (no_68851 && (current_architecture & m68851))
4031 as_bad (_("options for 68851 and no-68851 both given"));
4032
4033#ifdef OBJ_AOUT
4034 /* Work out the magic number. This isn't very general. */
4035 if (current_architecture & m68000)
4036 m68k_aout_machtype = 0;
4037 else if (current_architecture & m68010)
4038 m68k_aout_machtype = 1;
4039 else if (current_architecture & m68020)
4040 m68k_aout_machtype = 2;
4041 else
4042 m68k_aout_machtype = 2;
4043#endif
4044
4045 /* Note which set of "movec" control registers is available. */
4046 select_control_regs ();
4047
4048 if (cpu_of_arch (current_architecture) < m68020
6da466c7 4049 || arch_coldfire_p (current_architecture))
252b5132
RH		 4050 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4051}
4052\f
4053/* This is called when a label is defined. */
4054
4055void
4056m68k_frob_label (sym)
4057 symbolS *sym;
4058{
4059 struct label_line *n;
4060
4061 n = (struct label_line *) xmalloc (sizeof *n);
4062 n->next = labels;
4063 n->label = sym;
4064 as_where (&n->file, &n->line);
4065 n->text = 0;
4066 labels = n;
4067 current_label = n;
4068}
4069
4070/* This is called when a value that is not an instruction is emitted. */
4071
4072void
4073m68k_flush_pending_output ()
4074{
4075 current_label = NULL;
4076}
4077
4078/* This is called at the end of the assembly, when the final value of
4079 the label is known. We warn if this is a text symbol aligned at an
4080 odd location. */
4081
4082void
4083m68k_frob_symbol (sym)
4084 symbolS *sym;
4085{
4086 if (S_GET_SEGMENT (sym) == reg_section
4087 && (int) S_GET_VALUE (sym) < 0)
4088 {
4089 S_SET_SEGMENT (sym, absolute_section);
4090 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4091 }
4092 else if ((S_GET_VALUE (sym) & 1) != 0)
4093 {
4094 struct label_line *l;
4095
4096 for (l = labels; l != NULL; l = l->next)
4097 {
4098 if (l->label == sym)
4099 {
4100 if (l->text)
4101 as_warn_where (l->file, l->line,
4102 _("text label `%s' aligned to odd boundary"),
4103 S_GET_NAME (sym));
4104 break;
4105 }
4106 }
4107 }
4108}
4109\f
4110/* This is called if we go in or out of MRI mode because of the .mri
4111 pseudo-op. */
4112
4113void
4114m68k_mri_mode_change (on)
4115 int on;
4116{
4117 if (on)
4118 {
4119 if (! flag_reg_prefix_optional)
4120 {
4121 flag_reg_prefix_optional = 1;
4122#ifdef REGISTER_PREFIX
4123 init_regtable ();
4124#endif
4125 }
4126 m68k_abspcadd = 1;
4127 if (! m68k_rel32_from_cmdline)
4128 m68k_rel32 = 0;
4129 }
4130 else
4131 {
4132 if (! reg_prefix_optional_seen)
4133 {
4134#ifdef REGISTER_PREFIX_OPTIONAL
4135 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4136#else
4137 flag_reg_prefix_optional = 0;
4138#endif
4139#ifdef REGISTER_PREFIX
4140 init_regtable ();
4141#endif
4142 }
4143 m68k_abspcadd = 0;
4144 if (! m68k_rel32_from_cmdline)
4145 m68k_rel32 = 1;
4146 }
4147}
4148
4149/* Equal to MAX_PRECISION in atof-ieee.c */
4150#define MAX_LITTLENUMS 6
4151
4152/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4153 of type TYPE, and store the appropriate bytes in *LITP. The number
4154 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4155 returned, or NULL on OK. */
4156
4157char *
4158md_atof (type, litP, sizeP)
4159 char type;
4160 char *litP;
4161 int *sizeP;
4162{
4163 int prec;
4164 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4165 LITTLENUM_TYPE *wordP;
4166 char *t;
4167
4168 switch (type)
4169 {
4170 case 'f':
4171 case 'F':
4172 case 's':
4173 case 'S':
4174 prec = 2;
4175 break;
4176
4177 case 'd':
4178 case 'D':
4179 case 'r':
4180 case 'R':
4181 prec = 4;
4182 break;
4183
4184 case 'x':
4185 case 'X':
4186 prec = 6;
4187 break;
4188
4189 case 'p':
4190 case 'P':
4191 prec = 6;
4192 break;
4193
4194 default:
4195 *sizeP = 0;
4196 return _("Bad call to MD_ATOF()");
4197 }
4198 t = atof_ieee (input_line_pointer, type, words);
4199 if (t)
4200 input_line_pointer = t;
4201
4202 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4203 for (wordP = words; prec--;)
4204 {
4205 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4206 litP += sizeof (LITTLENUM_TYPE);
4207 }
4208 return 0;
4209}
4210
4211void
4212md_number_to_chars (buf, val, n)
4213 char *buf;
4214 valueT val;
4215 int n;
4216{
4217 number_to_chars_bigendian (buf, val, n);
4218}
4219
94f592af
NC		 4220void
4221md_apply_fix3 (fixP, valP, seg)
252b5132 4222 fixS *fixP;
bbe8ef22 4223 valueT *valP;
94f592af 4224 segT seg ATTRIBUTE_UNUSED;
252b5132 4225{
bbe8ef22 4226 offsetT val = *valP;
252b5132
RH		 4227 addressT upper_limit;
4228 offsetT lower_limit;
4229
4230 /* This is unnecessary but it convinces the native rs6000 compiler
4231 to generate the code we want. */
4232 char *buf = fixP->fx_frag->fr_literal;
4233 buf += fixP->fx_where;
4234 /* end ibm compiler workaround */
4235
c801568a 4236 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
252b5132 4237
94f592af
NC		 4238 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4239 fixP->fx_done = 1;
4240
252b5132
RH		 4241#ifdef OBJ_ELF
4242 if (fixP->fx_addsy)
4243 {
4244 memset (buf, 0, fixP->fx_size);
4245 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4246
4247 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4248 && !S_IS_DEFINED (fixP->fx_addsy)
4249 && !S_IS_WEAK (fixP->fx_addsy))
4250 S_SET_WEAK (fixP->fx_addsy);
4251 return;
4252 }
4253#endif
4254
4255#ifdef BFD_ASSEMBLER
4256 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4257 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4258 return;
4259#endif
4260
4261 switch (fixP->fx_size)
4262 {
94f592af
NC		 4263 /* The cast to offsetT below are necessary to make code
4264 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4265 case 1:
4266 *buf++ = val;
4267 upper_limit = 0x7f;
4268 lower_limit = - (offsetT) 0x80;
4269 break;
4270 case 2:
4271 *buf++ = (val >> 8);
4272 *buf++ = val;
4273 upper_limit = 0x7fff;
4274 lower_limit = - (offsetT) 0x8000;
4275 break;
4276 case 4:
4277 *buf++ = (val >> 24);
4278 *buf++ = (val >> 16);
4279 *buf++ = (val >> 8);
4280 *buf++ = val;
4281 upper_limit = 0x7fffffff;
4282 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4283 break;
4284 default:
4285 BAD_CASE (fixP->fx_size);
4286 }
4287
4288 /* Fix up a negative reloc. */
4289 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4290 {
4291 fixP->fx_addsy = fixP->fx_subsy;
4292 fixP->fx_subsy = NULL;
4293 fixP->fx_tcbit = 1;
4294 }
4295
4296 /* For non-pc-relative values, it's conceivable we might get something
4297 like "0xff" for a byte field. So extend the upper part of the range
4298 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4299 so that we can do any range checking at all. */
4300 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4301 upper_limit = upper_limit * 2 + 1;
4302
4303 if ((addressT) val > upper_limit
4304 && (val > 0 || val < lower_limit))
4305 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4306
4307 /* A one byte PC-relative reloc means a short branch. We can't use
4308 a short branch with a value of 0 or -1, because those indicate
4309 different opcodes (branches with longer offsets). fixup_segment
4310 in write.c may have clobbered fx_pcrel, so we need to examine the
4311 reloc type. */
4312 if ((fixP->fx_pcrel
4313#ifdef BFD_ASSEMBLER
4314 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4315#endif
4316 )
4317 && fixP->fx_size == 1
4318 && (fixP->fx_addsy == NULL
4319 || S_IS_DEFINED (fixP->fx_addsy))
4320 && (val == 0 || val == -1))
4321 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4322}
4323
252b5132
RH		 4324/* *fragP has been relaxed to its final size, and now needs to have
4325 the bytes inside it modified to conform to the new size There is UGLY
4326 MAGIC here. ..
4327 */
4328static void
4329md_convert_frag_1 (fragP)
4330 register fragS *fragP;
4331{
4332 long disp;
252b5132
RH		 4333 fixS *fixP;
4334
4335 /* Address in object code of the displacement. */
4336 register int object_address = fragP->fr_fix + fragP->fr_address;
4337
4338 /* Address in gas core of the place to store the displacement. */
4339 /* This convinces the native rs6000 compiler to generate the code we
92774660 4340 want. */
252b5132
RH		 4341 register char *buffer_address = fragP->fr_literal;
4342 buffer_address += fragP->fr_fix;
4343 /* end ibm compiler workaround */
4344
4345 /* The displacement of the address, from current location. */
4346 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4347 disp = (disp + fragP->fr_offset) - object_address;
4348
252b5132
RH		 4349 switch (fragP->fr_subtype)
4350 {
151337e8
NC		 4351 case TAB (BRANCHBWL, BYTE):
4352 case TAB (BRABSJUNC, BYTE):
4353 case TAB (BRABSJCOND, BYTE):
4354 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4355 know (issbyte (disp));
4356 if (disp == 0)
b091f402
AM		 4357 as_bad_where (fragP->fr_file, fragP->fr_line,
4358 _("short branch with zero offset: use :w"));
151337e8 4359 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4360 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4361 fixP->fx_pcrel_adjust = -1;
252b5132 4362 break;
151337e8
NC		 4363 case TAB (BRANCHBWL, SHORT):
4364 case TAB (BRABSJUNC, SHORT):
4365 case TAB (BRABSJCOND, SHORT):
4366 case TAB (BRANCHBW, SHORT):
252b5132 4367 fragP->fr_opcode[1] = 0x00;
151337e8 4368 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4369 1, RELAX_RELOC_PC16);
151337e8
NC		 4370 fragP->fr_fix += 2;
4371 break;
4372 case TAB (BRANCHBWL, LONG):
4373 fragP->fr_opcode[1] = (char) 0xFF;
4374 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4375 1, RELAX_RELOC_PC32);
151337e8 4376 fragP->fr_fix += 4;
252b5132 4377 break;
151337e8
NC		 4378 case TAB (BRABSJUNC, LONG):
4379 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4380 {
151337e8
NC		 4381 fragP->fr_opcode[0] = 0x4E;
4382 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand */
4383 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3ae647a0 4384 0, RELAX_RELOC_ABS32);
151337e8
NC		 4385 fragP->fr_fix += 4;
4386 }
4387 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4388 {
4389 fragP->fr_opcode[0] = 0x4E;
4390 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand */
4391 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4392 0, RELAX_RELOC_ABS32);
151337e8 4393 fragP->fr_fix += 4;
252b5132
RH		 4394 }
4395 else
4396 {
151337e8
NC		 4397 /* This cannot happen, because jbsr and jbra are the only two
4398 unconditional branches. */
4399 abort ();
252b5132
RH		 4400 }
4401 break;
151337e8
NC		 4402 case TAB (BRABSJCOND, LONG):
4403 /* Only Bcc 68000 instructions can come here. */
4404 /* Change bcc into b!cc/jmp absl long. */
92774660 4405
252b5132
RH		 4406 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4407 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4408
4409 /* JF: these used to be fr_opcode[2,3], but they may be in a
4410 different frag, in which case refering to them is a no-no.
92774660 4411 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4412 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4413 *buffer_address++ = (char) 0xf9;
4414 fragP->fr_fix += 2; /* account for jmp instruction */
4415 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5cbdaa77 4416 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4417 fragP->fr_fix += 4;
4418 break;
4419 case TAB (FBRANCH, SHORT):
4420 know ((fragP->fr_opcode[1] & 0x40) == 0);
4421 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4422 1, RELAX_RELOC_PC16);
151337e8
NC		 4423 fragP->fr_fix += 2;
4424 break;
4425 case TAB (FBRANCH, LONG):
4426 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4427 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4428 1, RELAX_RELOC_PC32);
252b5132 4429 fragP->fr_fix += 4;
252b5132 4430 break;
151337e8
NC		 4431 case TAB (DBCCLBR, SHORT):
4432 case TAB (DBCCABSJ, SHORT):
4433 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4434 1, RELAX_RELOC_PC16);
151337e8
NC		 4435 fragP->fr_fix += 2;
4436 break;
4437 case TAB (DBCCLBR, LONG):
4438 /* only DBcc instructions can come here */
28e7409f 4439 /* Change dbcc into dbcc/bral. */
28e7409f 4440
252b5132
RH		 4441 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4442 *buffer_address++ = 0x00; /* branch offset = 4 */
4443 *buffer_address++ = 0x04;
4444 *buffer_address++ = 0x60; /* put in bra pc+6 */
4445 *buffer_address++ = 0x06;
151337e8
NC		 4446 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4447 *buffer_address++ = (char) 0xff;
252b5132
RH		 4448
4449 fragP->fr_fix += 6; /* account for bra/jmp instructions */
151337e8 4450 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
5cbdaa77 4451 RELAX_RELOC_PC32);
252b5132 4452 fragP->fr_fix += 4;
252b5132 4453 break;
151337e8
NC		 4454 case TAB (DBCCABSJ, LONG):
4455 /* only DBcc instructions can come here */
4456 /* Change dbcc into dbcc/jmp. */
4457
4458 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4459 *buffer_address++ = 0x00; /* branch offset = 4 */
4460 *buffer_address++ = 0x04;
4461 *buffer_address++ = 0x60; /* put in bra pc+6 */
4462 *buffer_address++ = 0x06;
4463 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4464 *buffer_address++ = (char) 0xf9;
4465
4466 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4467 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
5cbdaa77 4468 RELAX_RELOC_ABS32);
252b5132 4469 fragP->fr_fix += 4;
252b5132 4470 break;
151337e8 4471 case TAB (PCREL1632, SHORT):
252b5132
RH		 4472 fragP->fr_opcode[1] &= ~0x3F;
4473 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
151337e8 4474 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4475 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 4476 fragP->fr_fix += 2;
252b5132 4477 break;
151337e8 4478 case TAB (PCREL1632, LONG):
252b5132
RH		 4479 /* Already set to mode 7.3; this indicates: PC indirect with
4480 suppressed index, 32-bit displacement. */
4481 *buffer_address++ = 0x01;
4482 *buffer_address++ = 0x70;
4483 fragP->fr_fix += 2;
151337e8 4484 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4485 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4486 fixP->fx_pcrel_adjust = 2;
4487 fragP->fr_fix += 4;
252b5132 4488 break;
252b5132 4489 case TAB (PCINDEX, BYTE):
252b5132
RH		 4490 assert (fragP->fr_fix >= 2);
4491 buffer_address[-2] &= ~1;
151337e8 4492 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4493 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4494 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 4495 break;
4496 case TAB (PCINDEX, SHORT):
252b5132
RH		 4497 assert (fragP->fr_fix >= 2);
4498 buffer_address[-2] |= 0x1;
4499 buffer_address[-1] = 0x20;
4500 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4501 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 4502 fixP->fx_pcrel_adjust = 2;
151337e8 4503 fragP->fr_fix += 2;
252b5132
RH		 4504 break;
4505 case TAB (PCINDEX, LONG):
252b5132
RH		 4506 assert (fragP->fr_fix >= 2);
4507 buffer_address[-2] |= 0x1;
4508 buffer_address[-1] = 0x30;
151337e8 4509 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4510 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4511 fixP->fx_pcrel_adjust = 2;
4512 fragP->fr_fix += 4;
4513 break;
4514 case TAB (ABSTOPCREL, SHORT):
4515 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4516 1, RELAX_RELOC_PC16);
151337e8
NC		 4517 fragP->fr_fix += 2;
4518 break;
4519 case TAB (ABSTOPCREL, LONG):
4520 /* The thing to do here is force it to ABSOLUTE LONG, since
4521 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */
4522 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4523 abort ();
4524 fragP->fr_opcode[1] &= ~0x3F;
4525 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4526 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4527 0, RELAX_RELOC_ABS32);
151337e8 4528 fragP->fr_fix += 4;
252b5132 4529 break;
252b5132
RH		 4530 }
4531}
4532
4533#ifndef BFD_ASSEMBLER
4534
4535void
4536md_convert_frag (headers, sec, fragP)
8fce3f5e
AM		 4537 object_headers *headers ATTRIBUTE_UNUSED;
4538 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4539 fragS *fragP;
4540{
4541 md_convert_frag_1 (fragP);
4542}
4543
4544#else
4545
4546void
4547md_convert_frag (abfd, sec, fragP)
36823076
AS		 4548 bfd *abfd ATTRIBUTE_UNUSED;
4549 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4550 fragS *fragP;
4551{
4552 md_convert_frag_1 (fragP);
4553}
4554#endif
4555
4556/* Force truly undefined symbols to their maximum size, and generally set up
4557 the frag list to be relaxed
4558 */
4559int
4560md_estimate_size_before_relax (fragP, segment)
4561 register fragS *fragP;
4562 segT segment;
4563{
151337e8 4564 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 4565 switch (fragP->fr_subtype)
4566 {
151337e8
NC		 4567 case TAB (BRANCHBWL, SZ_UNDEF):
4568 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 4569 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 4570 {
151337e8
NC		 4571 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4572 && relaxable_symbol (fragP->fr_symbol))
252b5132 4573 {
151337e8
NC		 4574 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4575 }
4576 else if (flag_short_refs)
4577 {
4578 /* Symbol is undefined and we want short ref. */
4579 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4580 }
4581 else
4582 {
151337e8
NC		 4583 /* Symbol is still undefined. Make it LONG. */
4584 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4585 }
4586 break;
151337e8 4587 }
252b5132 4588
151337e8 4589 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 4590 {
151337e8
NC		 4591 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4592 && relaxable_symbol (fragP->fr_symbol))
252b5132 4593 {
151337e8 4594 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 4595 }
4596 else
4597 {
151337e8
NC		 4598 /* Symbol is undefined and we don't have long branches. */
4599 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4600 }
4601 break;
151337e8 4602 }
252b5132 4603
151337e8 4604 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 4605 case TAB (DBCCLBR, SZ_UNDEF):
4606 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 4607 case TAB (PCREL1632, SZ_UNDEF):
252b5132 4608 {
8ec6253e
NC		 4609 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4610 && relaxable_symbol (fragP->fr_symbol))
151337e8 4611 || flag_short_refs)
252b5132 4612 {
151337e8 4613 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4614 }
4615 else
4616 {
151337e8 4617 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4618 }
4619 break;
151337e8 4620 }
81d4177b 4621
252b5132
RH		 4622 case TAB (PCINDEX, SZ_UNDEF):
4623 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 4624 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 4625 {
4626 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4627 }
4628 else
4629 {
4630 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 4631 }
4632 break;
4633
151337e8
NC		 4634 case TAB (ABSTOPCREL, SZ_UNDEF):
4635 {
4636 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4637 && relaxable_symbol (fragP->fr_symbol)))
4638 {
4639 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 4640 }
4641 else
4642 {
4643 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 4644 }
4645 break;
4646 }
4647
252b5132
RH		 4648 default:
4649 break;
4650 }
4651
151337e8 4652 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 4653 switch (fragP->fr_subtype)
4654 {
151337e8
NC		 4655 case TAB (BRANCHBWL, BYTE):
4656 case TAB (BRABSJUNC, BYTE):
4657 case TAB (BRABSJCOND, BYTE):
4658 case TAB (BRANCHBW, BYTE):
252b5132 4659 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 4660 case we force word mode. If the symbol is at the start of a
4661 frag, and it is the next frag with any data in it (usually
4662 this is just the next frag, but assembler listings may
4663 introduce empty frags), we must use word mode. */
4664 if (fragP->fr_symbol)
252b5132 4665 {
ac62c346 4666 fragS *sym_frag;
252b5132 4667
ac62c346
AM		 4668 sym_frag = symbol_get_frag (fragP->fr_symbol);
4669 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 4670 {
ac62c346
AM		 4671 fragS *l;
4672
23b7f870 4673 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 4674 if (l->fr_fix != 0)
4675 break;
4676 if (l == sym_frag)
4677 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4678 }
4679 }
4680 break;
4681 default:
4682 break;
4683 }
ac62c346 4684 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 4685}
4686
4687#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4688/* the bit-field entries in the relocation_info struct plays hell
4689 with the byte-order problems of cross-assembly. So as a hack,
4690 I added this mach. dependent ri twiddler. Ugly, but it gets
4691 you there. -KWK */
4692/* on m68k: first 4 bytes are normal unsigned long, next three bytes
4693 are symbolnum, most sig. byte first. Last byte is broken up with
4694 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4695 nibble as nuthin. (on Sun 3 at least) */
4696/* Translate the internal relocation information into target-specific
92774660 4697 format. */
252b5132
RH		 4698#ifdef comment
4699void
4700md_ri_to_chars (the_bytes, ri)
4701 char *the_bytes;
4702 struct reloc_info_generic *ri;
4703{
4704 /* this is easy */
4705 md_number_to_chars (the_bytes, ri->r_address, 4);
4706 /* now the fun stuff */
4707 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4708 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4709 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4710 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4711 ((ri->r_extern << 4) & 0x10));
4712}
4713
4714#endif /* comment */
4715
4716#ifndef BFD_ASSEMBLER
4717void
4718tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4719 char *where;
4720 fixS *fixP;
4721 relax_addressT segment_address_in_file;
4722{
4723 /*
4724 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4725 * Out: GNU LD relocation length code: 0, 1, or 2.
4726 */
4727
5a38dc70 4728 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
252b5132
RH		 4729 long r_symbolnum;
4730
4731 know (fixP->fx_addsy != NULL);
4732
4733 md_number_to_chars (where,
4734 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4735 4);
4736
4737 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4738 ? S_GET_TYPE (fixP->fx_addsy)
4739 : fixP->fx_addsy->sy_number);
4740
4741 where[4] = (r_symbolnum >> 16) & 0x0ff;
4742 where[5] = (r_symbolnum >> 8) & 0x0ff;
4743 where[6] = r_symbolnum & 0x0ff;
4744 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4745 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4746}
4747#endif
4748
4749#endif /* OBJ_AOUT or OBJ_BOUT */
4750
4751#ifndef WORKING_DOT_WORD
5a38dc70
AM		 4752const int md_short_jump_size = 4;
4753const int md_long_jump_size = 6;
252b5132
RH		 4754
4755void
4756md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4757 char *ptr;
4758 addressT from_addr, to_addr;
36823076
AS		 4759 fragS *frag ATTRIBUTE_UNUSED;
4760 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132
RH		 4761{
4762 valueT offset;
4763
4764 offset = to_addr - (from_addr + 2);
4765
4766 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4767 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4768}
4769
4770void
4771md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4772 char *ptr;
4773 addressT from_addr, to_addr;
4774 fragS *frag;
4775 symbolS *to_symbol;
4776{
4777 valueT offset;
4778
4779 if (!HAVE_LONG_BRANCH(current_architecture))
4780 {
4781 offset = to_addr - S_GET_VALUE (to_symbol);
4782 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4783 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4784 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4785 0, NO_RELOC);
4786 }
4787 else
4788 {
4789 offset = to_addr - (from_addr + 2);
4790 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4791 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4792 }
4793}
4794
4795#endif
4796
4797/* Different values of OK tell what its OK to return. Things that
4798 aren't OK are an error (what a shock, no?)
4799
4800 0: Everything is OK
4801 10: Absolute 1:8 only
4802 20: Absolute 0:7 only
4803 30: absolute 0:15 only
4804 40: Absolute 0:31 only
4805 50: absolute 0:127 only
4806 55: absolute -64:63 only
4807 60: absolute -128:127 only
4808 70: absolute 0:4095 only
4809 80: No bignums
4810
4811 */
4812
4813static int
4814get_num (exp, ok)
4815 struct m68k_exp *exp;
4816 int ok;
4817{
4818 if (exp->exp.X_op == O_absent)
4819 {
4820 /* Do the same thing the VAX asm does */
4821 op (exp) = O_constant;
4822 adds (exp) = 0;
4823 subs (exp) = 0;
4824 offs (exp) = 0;
4825 if (ok == 10)
4826 {
4827 as_warn (_("expression out of range: defaulting to 1"));
4828 offs (exp) = 1;
4829 }
4830 }
4831 else if (exp->exp.X_op == O_constant)
4832 {
4833 switch (ok)
4834 {
4835 case 10:
4836 if (offs (exp) < 1 || offs (exp) > 8)
4837 {
4838 as_warn (_("expression out of range: defaulting to 1"));
4839 offs (exp) = 1;
4840 }
4841 break;
4842 case 20:
4843 if (offs (exp) < 0 || offs (exp) > 7)
4844 goto outrange;
4845 break;
4846 case 30:
4847 if (offs (exp) < 0 || offs (exp) > 15)
4848 goto outrange;
4849 break;
4850 case 40:
4851 if (offs (exp) < 0 || offs (exp) > 32)
4852 goto outrange;
4853 break;
4854 case 50:
4855 if (offs (exp) < 0 || offs (exp) > 127)
4856 goto outrange;
4857 break;
4858 case 55:
4859 if (offs (exp) < -64 || offs (exp) > 63)
4860 goto outrange;
4861 break;
4862 case 60:
4863 if (offs (exp) < -128 || offs (exp) > 127)
4864 goto outrange;
4865 break;
4866 case 70:
4867 if (offs (exp) < 0 || offs (exp) > 4095)
4868 {
4869 outrange:
4870 as_warn (_("expression out of range: defaulting to 0"));
4871 offs (exp) = 0;
4872 }
4873 break;
4874 default:
4875 break;
4876 }
4877 }
4878 else if (exp->exp.X_op == O_big)
4879 {
4880 if (offs (exp) <= 0 /* flonum */
4881 && (ok == 80 /* no bignums */
4882 || (ok > 10 /* small-int ranges including 0 ok */
4883 /* If we have a flonum zero, a zero integer should
4884 do as well (e.g., in moveq). */
4885 && generic_floating_point_number.exponent == 0
4886 && generic_floating_point_number.low[0] == 0)))
4887 {
4888 /* HACK! Turn it into a long */
4889 LITTLENUM_TYPE words[6];
4890
4891 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4892 op (exp) = O_constant;
4893 adds (exp) = 0;
4894 subs (exp) = 0;
4895 offs (exp) = words[1] | (words[0] << 16);
4896 }
4897 else if (ok != 0)
4898 {
4899 op (exp) = O_constant;
4900 adds (exp) = 0;
4901 subs (exp) = 0;
4902 offs (exp) = (ok == 10) ? 1 : 0;
4903 as_warn (_("Can't deal with expression; defaulting to %ld"),
4904 offs (exp));
4905 }
4906 }
4907 else
4908 {
4909 if (ok >= 10 && ok <= 70)
4910 {
4911 op (exp) = O_constant;
4912 adds (exp) = 0;
4913 subs (exp) = 0;
4914 offs (exp) = (ok == 10) ? 1 : 0;
4915 as_warn (_("Can't deal with expression; defaulting to %ld"),
4916 offs (exp));
4917 }
4918 }
4919
4920 if (exp->size != SIZE_UNSPEC)
4921 {
4922 switch (exp->size)
4923 {
4924 case SIZE_UNSPEC:
4925 case SIZE_LONG:
4926 break;
4927 case SIZE_BYTE:
4928 if (!isbyte (offs (exp)))
4929 as_warn (_("expression doesn't fit in BYTE"));
4930 break;
4931 case SIZE_WORD:
4932 if (!isword (offs (exp)))
4933 as_warn (_("expression doesn't fit in WORD"));
4934 break;
4935 }
4936 }
4937
4938 return offs (exp);
4939}
4940
4941/* These are the back-ends for the various machine dependent pseudo-ops. */
4942
4943static void
4944s_data1 (ignore)
36823076 4945 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4946{
4947 subseg_set (data_section, 1);
4948 demand_empty_rest_of_line ();
4949}
4950
4951static void
4952s_data2 (ignore)
36823076 4953 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4954{
4955 subseg_set (data_section, 2);
4956 demand_empty_rest_of_line ();
4957}
4958
4959static void
4960s_bss (ignore)
36823076 4961 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4962{
4963 /* We don't support putting frags in the BSS segment, we fake it
4964 by marking in_bss, then looking at s_skip for clues. */
4965
4966 subseg_set (bss_section, 0);
4967 demand_empty_rest_of_line ();
4968}
4969
4970static void
4971s_even (ignore)
36823076 4972 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4973{
4974 register int temp;
4975 register long temp_fill;
4976
4977 temp = 1; /* JF should be 2? */
4978 temp_fill = get_absolute_expression ();
92774660 4979 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 4980 frag_align (temp, (int) temp_fill, 0);
4981 demand_empty_rest_of_line ();
4982 record_alignment (now_seg, temp);
4983}
4984
4985static void
4986s_proc (ignore)
36823076 4987 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4988{
4989 demand_empty_rest_of_line ();
4990}
4991\f
4992/* Pseudo-ops handled for MRI compatibility. */
4993
4994/* This function returns non-zero if the argument is a conditional
4995 pseudo-op. This is called when checking whether a pending
4996 alignment is needed. */
4997
4998int
4999m68k_conditional_pseudoop (pop)
5000 pseudo_typeS *pop;
5001{
5002 return (pop->poc_handler == s_mri_if
5003 || pop->poc_handler == s_mri_else);
5004}
5005
5006/* Handle an MRI style chip specification. */
5007
5008static void
5009mri_chip ()
5010{
5011 char *s;
5012 char c;
5013 int i;
5014
5015 s = input_line_pointer;
5016 /* We can't use get_symbol_end since the processor names are not proper
5017 symbols. */
5018 while (is_part_of_name (c = *input_line_pointer++))
5019 ;
5020 *--input_line_pointer = 0;
5021 for (i = 0; i < n_archs; i++)
5022 if (strcasecmp (s, archs[i].name) == 0)
5023 break;
5024 if (i >= n_archs)
5025 {
5026 as_bad (_("%s: unrecognized processor name"), s);
5027 *input_line_pointer = c;
5028 ignore_rest_of_line ();
5029 return;
5030 }
5031 *input_line_pointer = c;
5032
5033 if (*input_line_pointer == '/')
5034 current_architecture = 0;
5035 else
5036 current_architecture &= m68881 | m68851;
5037 current_architecture |= archs[i].arch;
5038
5039 while (*input_line_pointer == '/')
5040 {
5041 ++input_line_pointer;
5042 s = input_line_pointer;
5043 /* We can't use get_symbol_end since the processor names are not
5044 proper symbols. */
5045 while (is_part_of_name (c = *input_line_pointer++))
5046 ;
5047 *--input_line_pointer = 0;
5048 if (strcmp (s, "68881") == 0)
5049 current_architecture |= m68881;
5050 else if (strcmp (s, "68851") == 0)
5051 current_architecture |= m68851;
5052 *input_line_pointer = c;
5053 }
5054
5055 /* Update info about available control registers. */
5056 select_control_regs ();
5057}
5058
5059/* The MRI CHIP pseudo-op. */
5060
5061static void
5062s_chip (ignore)
36823076 5063 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5064{
5065 char *stop = NULL;
5066 char stopc;
5067
5068 if (flag_mri)
5069 stop = mri_comment_field (&stopc);
5070 mri_chip ();
5071 if (flag_mri)
5072 mri_comment_end (stop, stopc);
5073 demand_empty_rest_of_line ();
5074}
5075
5076/* The MRI FOPT pseudo-op. */
5077
5078static void
5079s_fopt (ignore)
36823076 5080 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5081{
5082 SKIP_WHITESPACE ();
5083
5084 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5085 {
5086 int temp;
5087
5088 input_line_pointer += 3;
5089 temp = get_absolute_expression ();
5090 if (temp < 0 || temp > 7)
5091 as_bad (_("bad coprocessor id"));
5092 else
5093 m68k_float_copnum = COP0 + temp;
5094 }
5095 else
5096 {
5097 as_bad (_("unrecognized fopt option"));
5098 ignore_rest_of_line ();
5099 return;
5100 }
5101
5102 demand_empty_rest_of_line ();
5103}
5104
5105/* The structure used to handle the MRI OPT pseudo-op. */
5106
5107struct opt_action
5108{
5109 /* The name of the option. */
5110 const char *name;
5111
5112 /* If this is not NULL, just call this function. The first argument
5113 is the ARG field of this structure, the second argument is
5114 whether the option was negated. */
5115 void (*pfn) PARAMS ((int arg, int on));
5116
5117 /* If this is not NULL, and the PFN field is NULL, set the variable
5118 this points to. Set it to the ARG field if the option was not
5119 negated, and the NOTARG field otherwise. */
5120 int *pvar;
5121
5122 /* The value to pass to PFN or to assign to *PVAR. */
5123 int arg;
5124
5125 /* The value to assign to *PVAR if the option is negated. If PFN is
5126 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5127 the option may not be negated. */
5128 int notarg;
5129};
5130
5131/* The table used to handle the MRI OPT pseudo-op. */
5132
5133static void skip_to_comma PARAMS ((int, int));
5134static void opt_nest PARAMS ((int, int));
5135static void opt_chip PARAMS ((int, int));
5136static void opt_list PARAMS ((int, int));
5137static void opt_list_symbols PARAMS ((int, int));
5138
5139static const struct opt_action opt_table[] =
5140{
5141 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5142
5143 /* We do relaxing, so there is little use for these options. */
5144 { "b", 0, 0, 0, 0 },
5145 { "brs", 0, 0, 0, 0 },
5146 { "brb", 0, 0, 0, 0 },
5147 { "brl", 0, 0, 0, 0 },
5148 { "brw", 0, 0, 0, 0 },
5149
5150 { "c", 0, 0, 0, 0 },
5151 { "cex", 0, 0, 0, 0 },
5152 { "case", 0, &symbols_case_sensitive, 1, 0 },
5153 { "cl", 0, 0, 0, 0 },
5154 { "cre", 0, 0, 0, 0 },
5155 { "d", 0, &flag_keep_locals, 1, 0 },
5156 { "e", 0, 0, 0, 0 },
5157 { "f", 0, &flag_short_refs, 1, 0 },
5158 { "frs", 0, &flag_short_refs, 1, 0 },
5159 { "frl", 0, &flag_short_refs, 0, 1 },
5160 { "g", 0, 0, 0, 0 },
5161 { "i", 0, 0, 0, 0 },
5162 { "m", 0, 0, 0, 0 },
5163 { "mex", 0, 0, 0, 0 },
5164 { "mc", 0, 0, 0, 0 },
5165 { "md", 0, 0, 0, 0 },
5166 { "nest", opt_nest, 0, 0, 0 },
5167 { "next", skip_to_comma, 0, 0, 0 },
5168 { "o", 0, 0, 0, 0 },
5169 { "old", 0, 0, 0, 0 },
5170 { "op", skip_to_comma, 0, 0, 0 },
5171 { "pco", 0, 0, 0, 0 },
5172 { "p", opt_chip, 0, 0, 0 },
5173 { "pcr", 0, 0, 0, 0 },
5174 { "pcs", 0, 0, 0, 0 },
5175 { "r", 0, 0, 0, 0 },
5176 { "quick", 0, &m68k_quick, 1, 0 },
5177 { "rel32", 0, &m68k_rel32, 1, 0 },
5178 { "s", opt_list, 0, 0, 0 },
5179 { "t", opt_list_symbols, 0, 0, 0 },
5180 { "w", 0, &flag_no_warnings, 0, 1 },
5181 { "x", 0, 0, 0, 0 }
5182};
5183
8fce3f5e 5184#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5185
5186/* The MRI OPT pseudo-op. */
5187
5188static void
5189s_opt (ignore)
36823076 5190 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5191{
5192 do
5193 {
5194 int t;
5195 char *s;
5196 char c;
5197 int i;
5198 const struct opt_action *o;
5199
5200 SKIP_WHITESPACE ();
5201
5202 t = 1;
5203 if (*input_line_pointer == '-')
5204 {
5205 ++input_line_pointer;
5206 t = 0;
5207 }
5208 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5209 {
5210 input_line_pointer += 2;
5211 t = 0;
5212 }
5213
5214 s = input_line_pointer;
5215 c = get_symbol_end ();
5216
5217 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5218 {
5219 if (strcasecmp (s, o->name) == 0)
5220 {
5221 if (o->pfn)
5222 {
5223 /* Restore input_line_pointer now in case the option
5224 takes arguments. */
5225 *input_line_pointer = c;
5226 (*o->pfn) (o->arg, t);
5227 }
5228 else if (o->pvar != NULL)
5229 {
5230 if (! t && o->arg == o->notarg)
5231 as_bad (_("option `%s' may not be negated"), s);
5232 *input_line_pointer = c;
5233 *o->pvar = t ? o->arg : o->notarg;
5234 }
5235 else
5236 *input_line_pointer = c;
5237 break;
5238 }
5239 }
5240 if (i >= OPTCOUNT)
5241 {
5242 as_bad (_("option `%s' not recognized"), s);
5243 *input_line_pointer = c;
5244 }
5245 }
5246 while (*input_line_pointer++ == ',');
5247
5248 /* Move back to terminating character. */
5249 --input_line_pointer;
5250 demand_empty_rest_of_line ();
5251}
5252
5253/* Skip ahead to a comma. This is used for OPT options which we do
5254 not suppor tand which take arguments. */
5255
5256static void
5257skip_to_comma (arg, on)
36823076
AS		 5258 int arg ATTRIBUTE_UNUSED;
5259 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5260{
5261 while (*input_line_pointer != ','
5262 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5263 ++input_line_pointer;
5264}
5265
5266/* Handle the OPT NEST=depth option. */
5267
5268static void
5269opt_nest (arg, on)
36823076
AS		 5270 int arg ATTRIBUTE_UNUSED;
5271 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5272{
5273 if (*input_line_pointer != '=')
5274 {
5275 as_bad (_("bad format of OPT NEST=depth"));
5276 return;
5277 }
5278
5279 ++input_line_pointer;
5280 max_macro_nest = get_absolute_expression ();
5281}
5282
5283/* Handle the OPT P=chip option. */
5284
5285static void
5286opt_chip (arg, on)
36823076
AS		 5287 int arg ATTRIBUTE_UNUSED;
5288 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5289{
5290 if (*input_line_pointer != '=')
5291 {
5292 /* This is just OPT P, which we do not support. */
5293 return;
5294 }
5295
5296 ++input_line_pointer;
5297 mri_chip ();
5298}
5299
5300/* Handle the OPT S option. */
5301
5302static void
5303opt_list (arg, on)
36823076 5304 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5305 int on;
5306{
5307 listing_list (on);
5308}
5309
5310/* Handle the OPT T option. */
5311
5312static void
5313opt_list_symbols (arg, on)
36823076 5314 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5315 int on;
5316{
5317 if (on)
5318 listing |= LISTING_SYMBOLS;
5319 else
8a104df9 5320 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5321}
5322
5323/* Handle the MRI REG pseudo-op. */
5324
5325static void
5326s_reg (ignore)
36823076 5327 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5328{
5329 char *s;
5330 int c;
5331 struct m68k_op rop;
5332 int mask;
5333 char *stop = NULL;
5334 char stopc;
5335
5336 if (line_label == NULL)
5337 {
5338 as_bad (_("missing label"));
5339 ignore_rest_of_line ();
5340 return;
5341 }
5342
5343 if (flag_mri)
5344 stop = mri_comment_field (&stopc);
5345
5346 SKIP_WHITESPACE ();
5347
5348 s = input_line_pointer;
3882b010 5349 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5350#ifdef REGISTER_PREFIX
5351 || *input_line_pointer == REGISTER_PREFIX
5352#endif
5353 || *input_line_pointer == '/'
5354 || *input_line_pointer == '-')
5355 ++input_line_pointer;
5356 c = *input_line_pointer;
5357 *input_line_pointer = '\0';
5358
5359 if (m68k_ip_op (s, &rop) != 0)
5360 {
5361 if (rop.error == NULL)
5362 as_bad (_("bad register list"));
5363 else
5364 as_bad (_("bad register list: %s"), rop.error);
5365 *input_line_pointer = c;
5366 ignore_rest_of_line ();
5367 return;
5368 }
5369
5370 *input_line_pointer = c;
5371
5372 if (rop.mode == REGLST)
5373 mask = rop.mask;
5374 else if (rop.mode == DREG)
5375 mask = 1 << (rop.reg - DATA0);
5376 else if (rop.mode == AREG)
5377 mask = 1 << (rop.reg - ADDR0 + 8);
5378 else if (rop.mode == FPREG)
5379 mask = 1 << (rop.reg - FP0 + 16);
5380 else if (rop.mode == CONTROL
5381 && rop.reg == FPI)
5382 mask = 1 << 24;
5383 else if (rop.mode == CONTROL
5384 && rop.reg == FPS)
5385 mask = 1 << 25;
5386 else if (rop.mode == CONTROL
5387 && rop.reg == FPC)
5388 mask = 1 << 26;
5389 else
5390 {
5391 as_bad (_("bad register list"));
5392 ignore_rest_of_line ();
5393 return;
5394 }
5395
5396 S_SET_SEGMENT (line_label, reg_section);
5397 S_SET_VALUE (line_label, ~mask);
49309057 5398 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5399
5400 if (flag_mri)
5401 mri_comment_end (stop, stopc);
5402
5403 demand_empty_rest_of_line ();
5404}
5405
5406/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5407
5408struct save_opts
5409{
5410 struct save_opts *next;
5411 int abspcadd;
5412 int symbols_case_sensitive;
5413 int keep_locals;
5414 int short_refs;
5415 int architecture;
5416 int quick;
5417 int rel32;
5418 int listing;
5419 int no_warnings;
5420 /* FIXME: We don't save OPT S. */
5421};
5422
5423/* This variable holds the stack of saved options. */
5424
5425static struct save_opts *save_stack;
5426
5427/* The MRI SAVE pseudo-op. */
5428
5429static void
5430s_save (ignore)
36823076 5431 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5432{
5433 struct save_opts *s;
5434
5435 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5436 s->abspcadd = m68k_abspcadd;
5437 s->symbols_case_sensitive = symbols_case_sensitive;
5438 s->keep_locals = flag_keep_locals;
5439 s->short_refs = flag_short_refs;
5440 s->architecture = current_architecture;
5441 s->quick = m68k_quick;
5442 s->rel32 = m68k_rel32;
5443 s->listing = listing;
5444 s->no_warnings = flag_no_warnings;
5445
5446 s->next = save_stack;
5447 save_stack = s;
5448
5449 demand_empty_rest_of_line ();
5450}
5451
5452/* The MRI RESTORE pseudo-op. */
5453
5454static void
5455s_restore (ignore)
36823076 5456 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5457{
5458 struct save_opts *s;
5459
5460 if (save_stack == NULL)
5461 {
5462 as_bad (_("restore without save"));
5463 ignore_rest_of_line ();
5464 return;
5465 }
5466
5467 s = save_stack;
5468 save_stack = s->next;
5469
5470 m68k_abspcadd = s->abspcadd;
5471 symbols_case_sensitive = s->symbols_case_sensitive;
5472 flag_keep_locals = s->keep_locals;
5473 flag_short_refs = s->short_refs;
5474 current_architecture = s->architecture;
5475 m68k_quick = s->quick;
5476 m68k_rel32 = s->rel32;
5477 listing = s->listing;
5478 flag_no_warnings = s->no_warnings;
5479
5480 free (s);
5481
5482 demand_empty_rest_of_line ();
5483}
5484
5485/* Types of MRI structured control directives. */
5486
5487enum mri_control_type
5488{
5489 mri_for,
5490 mri_if,
5491 mri_repeat,
5492 mri_while
5493};
5494
5495/* This structure is used to stack the MRI structured control
5496 directives. */
5497
5498struct mri_control_info
5499{
5500 /* The directive within which this one is enclosed. */
5501 struct mri_control_info *outer;
5502
5503 /* The type of directive. */
5504 enum mri_control_type type;
5505
5506 /* Whether an ELSE has been in an IF. */
5507 int else_seen;
5508
5509 /* The add or sub statement at the end of a FOR. */
5510 char *incr;
5511
5512 /* The label of the top of a FOR or REPEAT loop. */
5513 char *top;
5514
5515 /* The label to jump to for the next iteration, or the else
5516 expression of a conditional. */
5517 char *next;
5518
5519 /* The label to jump to to break out of the loop, or the label past
5520 the end of a conditional. */
5521 char *bottom;
5522};
5523
5524/* The stack of MRI structured control directives. */
5525
5526static struct mri_control_info *mri_control_stack;
5527
5528/* The current MRI structured control directive index number, used to
5529 generate label names. */
5530
5531static int mri_control_index;
5532
5533/* Some function prototypes. */
5534
5535static void mri_assemble PARAMS ((char *));
5536static char *mri_control_label PARAMS ((void));
5537static struct mri_control_info *push_mri_control
5538 PARAMS ((enum mri_control_type));
5539static void pop_mri_control PARAMS ((void));
5540static int parse_mri_condition PARAMS ((int *));
5541static int parse_mri_control_operand
5542 PARAMS ((int *, char **, char **, char **, char **));
5543static int swap_mri_condition PARAMS ((int));
5544static int reverse_mri_condition PARAMS ((int));
5545static void build_mri_control_operand
5546 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5547 const char *, int));
5548static void parse_mri_control_expression
5549 PARAMS ((char *, int, const char *, const char *, int));
5550
5551/* Assemble an instruction for an MRI structured control directive. */
5552
5553static void
5554mri_assemble (str)
5555 char *str;
5556{
5557 char *s;
5558
5559 /* md_assemble expects the opcode to be in lower case. */
5560 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 5561 *s = TOLOWER (*s);
252b5132
RH		 5562
5563 md_assemble (str);
5564}
5565
5566/* Generate a new MRI label structured control directive label name. */
5567
5568static char *
5569mri_control_label ()
5570{
5571 char *n;
5572
5573 n = (char *) xmalloc (20);
5574 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5575 ++mri_control_index;
5576 return n;
5577}
5578
5579/* Create a new MRI structured control directive. */
5580
5581static struct mri_control_info *
5582push_mri_control (type)
5583 enum mri_control_type type;
5584{
5585 struct mri_control_info *n;
5586
5587 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5588
5589 n->type = type;
5590 n->else_seen = 0;
5591 if (type == mri_if || type == mri_while)
5592 n->top = NULL;
5593 else
5594 n->top = mri_control_label ();
5595 n->next = mri_control_label ();
5596 n->bottom = mri_control_label ();
5597
5598 n->outer = mri_control_stack;
5599 mri_control_stack = n;
5600
5601 return n;
5602}
5603
5604/* Pop off the stack of MRI structured control directives. */
5605
5606static void
5607pop_mri_control ()
5608{
5609 struct mri_control_info *n;
5610
5611 n = mri_control_stack;
5612 mri_control_stack = n->outer;
5613 if (n->top != NULL)
5614 free (n->top);
5615 free (n->next);
5616 free (n->bottom);
5617 free (n);
5618}
5619
5620/* Recognize a condition code in an MRI structured control expression. */
5621
5622static int
5623parse_mri_condition (pcc)
5624 int *pcc;
5625{
5626 char c1, c2;
5627
5628 know (*input_line_pointer == '<');
5629
5630 ++input_line_pointer;
5631 c1 = *input_line_pointer++;
5632 c2 = *input_line_pointer++;
5633
5634 if (*input_line_pointer != '>')
5635 {
5636 as_bad (_("syntax error in structured control directive"));
5637 return 0;
5638 }
5639
5640 ++input_line_pointer;
5641 SKIP_WHITESPACE ();
5642
3882b010
L		 5643 c1 = TOLOWER (c1);
5644 c2 = TOLOWER (c2);
252b5132
RH		 5645
5646 *pcc = (c1 << 8) | c2;
5647
5648 return 1;
5649}
5650
5651/* Parse a single operand in an MRI structured control expression. */
5652
5653static int
5654parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5655 int *pcc;
5656 char **leftstart;
5657 char **leftstop;
5658 char **rightstart;
5659 char **rightstop;
5660{
5661 char *s;
5662
5663 SKIP_WHITESPACE ();
5664
5665 *pcc = -1;
5666 *leftstart = NULL;
5667 *leftstop = NULL;
5668 *rightstart = NULL;
5669 *rightstop = NULL;
5670
5671 if (*input_line_pointer == '<')
5672 {
5673 /* It's just a condition code. */
5674 return parse_mri_condition (pcc);
5675 }
5676
5677 /* Look ahead for the condition code. */
5678 for (s = input_line_pointer; *s != '\0'; ++s)
5679 {
5680 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5681 break;
5682 }
5683 if (*s == '\0')
5684 {
5685 as_bad (_("missing condition code in structured control directive"));
5686 return 0;
5687 }
5688
5689 *leftstart = input_line_pointer;
5690 *leftstop = s;
5691 if (*leftstop > *leftstart
5692 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5693 --*leftstop;
5694
5695 input_line_pointer = s;
5696 if (! parse_mri_condition (pcc))
5697 return 0;
5698
5699 /* Look ahead for AND or OR or end of line. */
5700 for (s = input_line_pointer; *s != '\0'; ++s)
5701 {
e1f44d10
NC		 5702 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5703 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5704 ^^^ ^^ */
8a104df9
KH		 5705 if ((s == input_line_pointer
5706 || *(s-1) == ' '
5707 || *(s-1) == '\t')
5708 && ((strncasecmp (s, "AND", 3) == 0
5709 && (s[3] == '.' || ! is_part_of_name (s[3])))
5710 || (strncasecmp (s, "OR", 2) == 0
5711 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5712 break;
252b5132
RH		 5713 }
5714
5715 *rightstart = input_line_pointer;
5716 *rightstop = s;
5717 if (*rightstop > *rightstart
5718 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5719 --*rightstop;
5720
5721 input_line_pointer = s;
5722
5723 return 1;
5724}
5725
5726#define MCC(b1, b2) (((b1) << 8) | (b2))
5727
5728/* Swap the sense of a condition. This changes the condition so that
5729 it generates the same result when the operands are swapped. */
5730
5731static int
5732swap_mri_condition (cc)
5733 int cc;
5734{
5735 switch (cc)
5736 {
5737 case MCC ('h', 'i'): return MCC ('c', 's');
5738 case MCC ('l', 's'): return MCC ('c', 'c');
e1f44d10
NC		 5739 /* <HS> is an alias for <CC> */
5740 case MCC ('h', 's'):
252b5132 5741 case MCC ('c', 'c'): return MCC ('l', 's');
e1f44d10
NC		 5742 /* <LO> is an alias for <CS> */
5743 case MCC ('l', 'o'):
252b5132
RH		 5744 case MCC ('c', 's'): return MCC ('h', 'i');
5745 case MCC ('p', 'l'): return MCC ('m', 'i');
5746 case MCC ('m', 'i'): return MCC ('p', 'l');
5747 case MCC ('g', 'e'): return MCC ('l', 'e');
5748 case MCC ('l', 't'): return MCC ('g', 't');
5749 case MCC ('g', 't'): return MCC ('l', 't');
5750 case MCC ('l', 'e'): return MCC ('g', 'e');
e1f44d10
NC		 5751 /* issue a warning for conditions we can not swap */
5752 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
5753 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
5754 case MCC ('v', 'c'):
5755 case MCC ('v', 's'):
5756 default :
5757 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
5758 (char) (cc >> 8), (char) (cc));
5759 break;
252b5132
RH		 5760 }
5761 return cc;
5762}
5763
5764/* Reverse the sense of a condition. */
5765
5766static int
5767reverse_mri_condition (cc)
5768 int cc;
5769{
5770 switch (cc)
5771 {
5772 case MCC ('h', 'i'): return MCC ('l', 's');
5773 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 5774 /* <HS> is an alias for <CC> */
5775 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 5776 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 5777 /* <LO> is an alias for <CS> */
5778 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 5779 case MCC ('c', 's'): return MCC ('c', 'c');
5780 case MCC ('n', 'e'): return MCC ('e', 'q');
5781 case MCC ('e', 'q'): return MCC ('n', 'e');
5782 case MCC ('v', 'c'): return MCC ('v', 's');
5783 case MCC ('v', 's'): return MCC ('v', 'c');
5784 case MCC ('p', 'l'): return MCC ('m', 'i');
5785 case MCC ('m', 'i'): return MCC ('p', 'l');
5786 case MCC ('g', 'e'): return MCC ('l', 't');
5787 case MCC ('l', 't'): return MCC ('g', 'e');
5788 case MCC ('g', 't'): return MCC ('l', 'e');
5789 case MCC ('l', 'e'): return MCC ('g', 't');
5790 }
5791 return cc;
5792}
5793
5794/* Build an MRI structured control expression. This generates test
5795 and branch instructions. It goes to TRUELAB if the condition is
5796 true, and to FALSELAB if the condition is false. Exactly one of
5797 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5798 is the size qualifier for the expression. EXTENT is the size to
5799 use for the branch. */
5800
5801static void
5802build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5803 rightstop, truelab, falselab, extent)
5804 int qual;
5805 int cc;
5806 char *leftstart;
5807 char *leftstop;
5808 char *rightstart;
5809 char *rightstop;
5810 const char *truelab;
5811 const char *falselab;
5812 int extent;
5813{
5814 char *buf;
5815 char *s;
5816
5817 if (leftstart != NULL)
5818 {
5819 struct m68k_op leftop, rightop;
5820 char c;
5821
5822 /* Swap the compare operands, if necessary, to produce a legal
5823 m68k compare instruction. Comparing a register operand with
5824 a non-register operand requires the register to be on the
5825 right (cmp, cmpa). Comparing an immediate value with
5826 anything requires the immediate value to be on the left
5827 (cmpi). */
5828
5829 c = *leftstop;
5830 *leftstop = '\0';
5831 (void) m68k_ip_op (leftstart, &leftop);
5832 *leftstop = c;
5833
5834 c = *rightstop;
5835 *rightstop = '\0';
5836 (void) m68k_ip_op (rightstart, &rightop);
5837 *rightstop = c;
5838
5839 if (rightop.mode == IMMED
5840 || ((leftop.mode == DREG || leftop.mode == AREG)
5841 && (rightop.mode != DREG && rightop.mode != AREG)))
5842 {
5843 char *temp;
5844
e1f44d10
NC		 5845 /* Correct conditional handling:
5846 if #1 <lt> d0 then ;means if (1 < d0)
5847 ...
5848 endi
5849
5850 should assemble to:
5851
5852 cmp #1,d0 if we do *not* swap the operands
5853 bgt true we need the swapped condition!
5854 ble false
5855 true:
5856 ...
5857 false:
5858 */
252b5132
RH		 5859 temp = leftstart;
5860 leftstart = rightstart;
5861 rightstart = temp;
5862 temp = leftstop;
5863 leftstop = rightstop;
5864 rightstop = temp;
8a104df9
KH		 5865 }
5866 else
5867 {
e1f44d10 5868 cc = swap_mri_condition (cc);
252b5132
RH		 5869 }
5870 }
5871
5872 if (truelab == NULL)
5873 {
5874 cc = reverse_mri_condition (cc);
5875 truelab = falselab;
5876 }
92774660 5877
252b5132
RH		 5878 if (leftstart != NULL)
5879 {
5880 buf = (char *) xmalloc (20
5881 + (leftstop - leftstart)
5882 + (rightstop - rightstart));
5883 s = buf;
5884 *s++ = 'c';
5885 *s++ = 'm';
5886 *s++ = 'p';
5887 if (qual != '\0')
3882b010 5888 *s++ = TOLOWER (qual);
252b5132
RH		 5889 *s++ = ' ';
5890 memcpy (s, leftstart, leftstop - leftstart);
5891 s += leftstop - leftstart;
5892 *s++ = ',';
5893 memcpy (s, rightstart, rightstop - rightstart);
5894 s += rightstop - rightstart;
5895 *s = '\0';
5896 mri_assemble (buf);
5897 free (buf);
5898 }
92774660 5899
252b5132
RH		 5900 buf = (char *) xmalloc (20 + strlen (truelab));
5901 s = buf;
5902 *s++ = 'b';
5903 *s++ = cc >> 8;
5904 *s++ = cc & 0xff;
5905 if (extent != '\0')
3882b010 5906 *s++ = TOLOWER (extent);
252b5132
RH		 5907 *s++ = ' ';
5908 strcpy (s, truelab);
5909 mri_assemble (buf);
5910 free (buf);
5911}
5912
5913/* Parse an MRI structured control expression. This generates test
5914 and branch instructions. STOP is where the expression ends. It
5915 goes to TRUELAB if the condition is true, and to FALSELAB if the
5916 condition is false. Exactly one of TRUELAB and FALSELAB will be
5917 NULL, meaning to fall through. QUAL is the size qualifier for the
5918 expression. EXTENT is the size to use for the branch. */
5919
5920static void
5921parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5922 char *stop;
5923 int qual;
5924 const char *truelab;
5925 const char *falselab;
5926 int extent;
5927{
5928 int c;
5929 int cc;
5930 char *leftstart;
5931 char *leftstop;
5932 char *rightstart;
5933 char *rightstop;
5934
5935 c = *stop;
5936 *stop = '\0';
5937
5938 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5939 &rightstart, &rightstop))
5940 {
5941 *stop = c;
5942 return;
5943 }
5944
5945 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5946 {
5947 const char *flab;
5948
5949 if (falselab != NULL)
5950 flab = falselab;
5951 else
5952 flab = mri_control_label ();
5953
5954 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5955 rightstop, (const char *) NULL, flab, extent);
5956
5957 input_line_pointer += 3;
5958 if (*input_line_pointer != '.'
5959 || input_line_pointer[1] == '\0')
5960 qual = '\0';
5961 else
5962 {
5963 qual = input_line_pointer[1];
5964 input_line_pointer += 2;
5965 }
5966
5967 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5968 &rightstart, &rightstop))
5969 {
5970 *stop = c;
5971 return;
5972 }
5973
5974 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5975 rightstop, truelab, falselab, extent);
5976
5977 if (falselab == NULL)
5978 colon (flab);
5979 }
5980 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5981 {
5982 const char *tlab;
5983
5984 if (truelab != NULL)
5985 tlab = truelab;
5986 else
5987 tlab = mri_control_label ();
5988
5989 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5990 rightstop, tlab, (const char *) NULL, extent);
5991
5992 input_line_pointer += 2;
5993 if (*input_line_pointer != '.'
5994 || input_line_pointer[1] == '\0')
5995 qual = '\0';
5996 else
5997 {
5998 qual = input_line_pointer[1];
5999 input_line_pointer += 2;
6000 }
6001
6002 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6003 &rightstart, &rightstop))
6004 {
6005 *stop = c;
6006 return;
6007 }
6008
6009 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6010 rightstop, truelab, falselab, extent);
6011
6012 if (truelab == NULL)
6013 colon (tlab);
6014 }
6015 else
6016 {
6017 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6018 rightstop, truelab, falselab, extent);
6019 }
6020
6021 *stop = c;
6022 if (input_line_pointer != stop)
6023 as_bad (_("syntax error in structured control directive"));
6024}
6025
6026/* Handle the MRI IF pseudo-op. This may be a structured control
6027 directive, or it may be a regular assembler conditional, depending
6028 on its operands. */
6029
6030static void
6031s_mri_if (qual)
6032 int qual;
6033{
6034 char *s;
6035 int c;
6036 struct mri_control_info *n;
6037
6038 /* A structured control directive must end with THEN with an
6039 optional qualifier. */
6040 s = input_line_pointer;
e1f44d10
NC		 6041 /* We only accept '*' as introduction of comments if preceded by white space
6042 or at first column of a line (I think this can't actually happen here?)
6043 This is important when assembling:
6044 if d0 <ne> 12(a0,d0*2) then
6045 if d0 <ne> #CONST*20 then */
6046 while ( ! ( is_end_of_line[(unsigned char) *s]
6047 || ( flag_mri
6048 && *s == '*'
6049 && ( s == input_line_pointer
6050 || *(s-1) == ' '
6051 || *(s-1) == '\t'))))
252b5132
RH		 6052 ++s;
6053 --s;
6054 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6055 --s;
6056
6057 if (s - input_line_pointer > 1
6058 && s[-1] == '.')
6059 s -= 2;
6060
6061 if (s - input_line_pointer < 3
6062 || strncasecmp (s - 3, "THEN", 4) != 0)
6063 {
6064 if (qual != '\0')
6065 {
6066 as_bad (_("missing then"));
6067 ignore_rest_of_line ();
6068 return;
6069 }
6070
6071 /* It's a conditional. */
6072 s_if (O_ne);
6073 return;
6074 }
6075
6076 /* Since this might be a conditional if, this pseudo-op will be
6077 called even if we are supported to be ignoring input. Double
6078 check now. Clobber *input_line_pointer so that ignore_input
6079 thinks that this is not a special pseudo-op. */
6080 c = *input_line_pointer;
6081 *input_line_pointer = 0;
6082 if (ignore_input ())
6083 {
6084 *input_line_pointer = c;
6085 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6086 ++input_line_pointer;
6087 demand_empty_rest_of_line ();
6088 return;
6089 }
6090 *input_line_pointer = c;
6091
6092 n = push_mri_control (mri_if);
6093
6094 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6095 n->next, s[1] == '.' ? s[2] : '\0');
6096
6097 if (s[1] == '.')
6098 input_line_pointer = s + 3;
6099 else
6100 input_line_pointer = s + 1;
6101
6102 if (flag_mri)
6103 {
6104 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6105 ++input_line_pointer;
6106 }
6107
6108 demand_empty_rest_of_line ();
6109}
6110
6111/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6112 structured IF, associate the ELSE with the IF. Otherwise, assume
6113 it is a conditional else. */
6114
6115static void
6116s_mri_else (qual)
6117 int qual;
6118{
6119 int c;
6120 char *buf;
6121 char q[2];
6122
6123 if (qual == '\0'
6124 && (mri_control_stack == NULL
6125 || mri_control_stack->type != mri_if
6126 || mri_control_stack->else_seen))
6127 {
6128 s_else (0);
6129 return;
6130 }
6131
6132 c = *input_line_pointer;
6133 *input_line_pointer = 0;
6134 if (ignore_input ())
6135 {
6136 *input_line_pointer = c;
6137 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6138 ++input_line_pointer;
6139 demand_empty_rest_of_line ();
6140 return;
6141 }
6142 *input_line_pointer = c;
6143
6144 if (mri_control_stack == NULL
6145 || mri_control_stack->type != mri_if
6146 || mri_control_stack->else_seen)
6147 {
6148 as_bad (_("else without matching if"));
6149 ignore_rest_of_line ();
6150 return;
6151 }
6152
6153 mri_control_stack->else_seen = 1;
6154
6155 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6156 q[0] = TOLOWER (qual);
252b5132
RH		 6157 q[1] = '\0';
6158 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6159 mri_assemble (buf);
6160 free (buf);
6161
6162 colon (mri_control_stack->next);
6163
6164 if (flag_mri)
6165 {
6166 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6167 ++input_line_pointer;
6168 }
6169
6170 demand_empty_rest_of_line ();
6171}
6172
6173/* Handle the MRI ENDI pseudo-op. */
6174
6175static void
6176s_mri_endi (ignore)
36823076 6177 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6178{
6179 if (mri_control_stack == NULL
6180 || mri_control_stack->type != mri_if)
6181 {
6182 as_bad (_("endi without matching if"));
6183 ignore_rest_of_line ();
6184 return;
6185 }
6186
6187 /* ignore_input will not return true for ENDI, so we don't need to
6188 worry about checking it again here. */
6189
6190 if (! mri_control_stack->else_seen)
6191 colon (mri_control_stack->next);
6192 colon (mri_control_stack->bottom);
6193
6194 pop_mri_control ();
6195
6196 if (flag_mri)
6197 {
6198 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6199 ++input_line_pointer;
6200 }
6201
6202 demand_empty_rest_of_line ();
6203}
6204
6205/* Handle the MRI BREAK pseudo-op. */
6206
6207static void
6208s_mri_break (extent)
6209 int extent;
6210{
6211 struct mri_control_info *n;
6212 char *buf;
6213 char ex[2];
6214
6215 n = mri_control_stack;
6216 while (n != NULL
6217 && n->type != mri_for
6218 && n->type != mri_repeat
6219 && n->type != mri_while)
6220 n = n->outer;
6221 if (n == NULL)
6222 {
6223 as_bad (_("break outside of structured loop"));
6224 ignore_rest_of_line ();
6225 return;
6226 }
6227
6228 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6229 ex[0] = TOLOWER (extent);
252b5132
RH		 6230 ex[1] = '\0';
6231 sprintf (buf, "bra%s %s", ex, n->bottom);
6232 mri_assemble (buf);
6233 free (buf);
6234
6235 if (flag_mri)
6236 {
6237 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6238 ++input_line_pointer;
6239 }
6240
6241 demand_empty_rest_of_line ();
6242}
6243
6244/* Handle the MRI NEXT pseudo-op. */
6245
6246static void
6247s_mri_next (extent)
6248 int extent;
6249{
6250 struct mri_control_info *n;
6251 char *buf;
6252 char ex[2];
6253
6254 n = mri_control_stack;
6255 while (n != NULL
6256 && n->type != mri_for
6257 && n->type != mri_repeat
6258 && n->type != mri_while)
6259 n = n->outer;
6260 if (n == NULL)
6261 {
6262 as_bad (_("next outside of structured loop"));
6263 ignore_rest_of_line ();
6264 return;
6265 }
6266
6267 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6268 ex[0] = TOLOWER (extent);
252b5132
RH		 6269 ex[1] = '\0';
6270 sprintf (buf, "bra%s %s", ex, n->next);
6271 mri_assemble (buf);
6272 free (buf);
6273
6274 if (flag_mri)
6275 {
6276 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6277 ++input_line_pointer;
6278 }
6279
6280 demand_empty_rest_of_line ();
6281}
6282
6283/* Handle the MRI FOR pseudo-op. */
6284
6285static void
6286s_mri_for (qual)
6287 int qual;
6288{
6289 const char *varstart, *varstop;
6290 const char *initstart, *initstop;
6291 const char *endstart, *endstop;
6292 const char *bystart, *bystop;
6293 int up;
6294 int by;
6295 int extent;
6296 struct mri_control_info *n;
6297 char *buf;
6298 char *s;
6299 char ex[2];
6300
6301 /* The syntax is
6302 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6303 */
6304
6305 SKIP_WHITESPACE ();
6306 varstart = input_line_pointer;
6307
6308 /* Look for the '='. */
6309 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6310 && *input_line_pointer != '=')
6311 ++input_line_pointer;
6312 if (*input_line_pointer != '=')
6313 {
6314 as_bad (_("missing ="));
6315 ignore_rest_of_line ();
6316 return;
6317 }
6318
6319 varstop = input_line_pointer;
6320 if (varstop > varstart
6321 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6322 --varstop;
6323
6324 ++input_line_pointer;
6325
6326 initstart = input_line_pointer;
6327
6328 /* Look for TO or DOWNTO. */
6329 up = 1;
6330 initstop = NULL;
6331 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6332 {
6333 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6334 && ! is_part_of_name (input_line_pointer[2]))
6335 {
6336 initstop = input_line_pointer;
6337 input_line_pointer += 2;
6338 break;
6339 }
6340 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6341 && ! is_part_of_name (input_line_pointer[6]))
6342 {
6343 initstop = input_line_pointer;
6344 up = 0;
6345 input_line_pointer += 6;
6346 break;
6347 }
6348 ++input_line_pointer;
6349 }
6350 if (initstop == NULL)
6351 {
6352 as_bad (_("missing to or downto"));
6353 ignore_rest_of_line ();
6354 return;
6355 }
6356 if (initstop > initstart
6357 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6358 --initstop;
6359
6360 SKIP_WHITESPACE ();
6361 endstart = input_line_pointer;
6362
6363 /* Look for BY or DO. */
6364 by = 0;
6365 endstop = NULL;
6366 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6367 {
6368 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6369 && ! is_part_of_name (input_line_pointer[2]))
6370 {
6371 endstop = input_line_pointer;
6372 by = 1;
6373 input_line_pointer += 2;
6374 break;
6375 }
6376 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6377 && (input_line_pointer[2] == '.'
6378 || ! is_part_of_name (input_line_pointer[2])))
6379 {
6380 endstop = input_line_pointer;
6381 input_line_pointer += 2;
6382 break;
6383 }
6384 ++input_line_pointer;
6385 }
6386 if (endstop == NULL)
6387 {
6388 as_bad (_("missing do"));
6389 ignore_rest_of_line ();
6390 return;
6391 }
6392 if (endstop > endstart
6393 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6394 --endstop;
6395
6396 if (! by)
6397 {
6398 bystart = "#1";
6399 bystop = bystart + 2;
6400 }
6401 else
6402 {
6403 SKIP_WHITESPACE ();
6404 bystart = input_line_pointer;
6405
6406 /* Look for DO. */
6407 bystop = NULL;
6408 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6409 {
6410 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6411 && (input_line_pointer[2] == '.'
6412 || ! is_part_of_name (input_line_pointer[2])))
6413 {
6414 bystop = input_line_pointer;
6415 input_line_pointer += 2;
6416 break;
6417 }
6418 ++input_line_pointer;
6419 }
6420 if (bystop == NULL)
6421 {
6422 as_bad (_("missing do"));
6423 ignore_rest_of_line ();
6424 return;
6425 }
6426 if (bystop > bystart
6427 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6428 --bystop;
6429 }
6430
6431 if (*input_line_pointer != '.')
6432 extent = '\0';
6433 else
6434 {
6435 extent = input_line_pointer[1];
6436 input_line_pointer += 2;
6437 }
6438
6439 /* We have fully parsed the FOR operands. Now build the loop. */
6440
6441 n = push_mri_control (mri_for);
6442
6443 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6444
6445 /* move init,var */
6446 s = buf;
6447 *s++ = 'm';
6448 *s++ = 'o';
6449 *s++ = 'v';
6450 *s++ = 'e';
6451 if (qual != '\0')
3882b010 6452 *s++ = TOLOWER (qual);
252b5132
RH		 6453 *s++ = ' ';
6454 memcpy (s, initstart, initstop - initstart);
6455 s += initstop - initstart;
6456 *s++ = ',';
6457 memcpy (s, varstart, varstop - varstart);
6458 s += varstop - varstart;
6459 *s = '\0';
6460 mri_assemble (buf);
6461
6462 colon (n->top);
6463
6464 /* cmp end,var */
6465 s = buf;
6466 *s++ = 'c';
6467 *s++ = 'm';
6468 *s++ = 'p';
6469 if (qual != '\0')
3882b010 6470 *s++ = TOLOWER (qual);
252b5132
RH		 6471 *s++ = ' ';
6472 memcpy (s, endstart, endstop - endstart);
6473 s += endstop - endstart;
6474 *s++ = ',';
6475 memcpy (s, varstart, varstop - varstart);
6476 s += varstop - varstart;
6477 *s = '\0';
6478 mri_assemble (buf);
6479
6480 /* bcc bottom */
3882b010 6481 ex[0] = TOLOWER (extent);
252b5132
RH		 6482 ex[1] = '\0';
6483 if (up)
6484 sprintf (buf, "blt%s %s", ex, n->bottom);
6485 else
6486 sprintf (buf, "bgt%s %s", ex, n->bottom);
6487 mri_assemble (buf);
6488
6489 /* Put together the add or sub instruction used by ENDF. */
6490 s = buf;
6491 if (up)
6492 strcpy (s, "add");
6493 else
6494 strcpy (s, "sub");
6495 s += 3;
6496 if (qual != '\0')
3882b010 6497 *s++ = TOLOWER (qual);
252b5132
RH		 6498 *s++ = ' ';
6499 memcpy (s, bystart, bystop - bystart);
6500 s += bystop - bystart;
6501 *s++ = ',';
6502 memcpy (s, varstart, varstop - varstart);
6503 s += varstop - varstart;
6504 *s = '\0';
6505 n->incr = buf;
6506
6507 if (flag_mri)
6508 {
6509 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6510 ++input_line_pointer;
6511 }
6512
6513 demand_empty_rest_of_line ();
6514}
6515
6516/* Handle the MRI ENDF pseudo-op. */
6517
6518static void
6519s_mri_endf (ignore)
36823076 6520 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6521{
6522 if (mri_control_stack == NULL
6523 || mri_control_stack->type != mri_for)
6524 {
6525 as_bad (_("endf without for"));
6526 ignore_rest_of_line ();
6527 return;
6528 }
6529
6530 colon (mri_control_stack->next);
6531
6532 mri_assemble (mri_control_stack->incr);
6533
6534 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6535 mri_assemble (mri_control_stack->incr);
6536
6537 free (mri_control_stack->incr);
6538
6539 colon (mri_control_stack->bottom);
6540
6541 pop_mri_control ();
6542
6543 if (flag_mri)
6544 {
6545 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6546 ++input_line_pointer;
6547 }
6548
6549 demand_empty_rest_of_line ();
6550}
6551
6552/* Handle the MRI REPEAT pseudo-op. */
6553
6554static void
6555s_mri_repeat (ignore)
36823076 6556 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6557{
6558 struct mri_control_info *n;
6559
6560 n = push_mri_control (mri_repeat);
6561 colon (n->top);
6562 if (flag_mri)
6563 {
6564 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6565 ++input_line_pointer;
6566 }
6567 demand_empty_rest_of_line ();
6568}
6569
6570/* Handle the MRI UNTIL pseudo-op. */
6571
6572static void
6573s_mri_until (qual)
6574 int qual;
6575{
6576 char *s;
6577
6578 if (mri_control_stack == NULL
6579 || mri_control_stack->type != mri_repeat)
6580 {
6581 as_bad (_("until without repeat"));
6582 ignore_rest_of_line ();
6583 return;
6584 }
6585
6586 colon (mri_control_stack->next);
6587
6588 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6589 ;
6590
6591 parse_mri_control_expression (s, qual, (const char *) NULL,
6592 mri_control_stack->top, '\0');
6593
6594 colon (mri_control_stack->bottom);
6595
6596 input_line_pointer = s;
6597
6598 pop_mri_control ();
6599
6600 if (flag_mri)
6601 {
6602 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6603 ++input_line_pointer;
6604 }
6605
6606 demand_empty_rest_of_line ();
6607}
6608
6609/* Handle the MRI WHILE pseudo-op. */
6610
6611static void
6612s_mri_while (qual)
6613 int qual;
6614{
6615 char *s;
6616
6617 struct mri_control_info *n;
6618
6619 s = input_line_pointer;
e1f44d10
NC		 6620 /* We only accept '*' as introduction of comments if preceded by white space
6621 or at first column of a line (I think this can't actually happen here?)
6622 This is important when assembling:
6623 while d0 <ne> 12(a0,d0*2) do
6624 while d0 <ne> #CONST*20 do */
8a104df9
KH		 6625 while (! (is_end_of_line[(unsigned char) *s]
6626 || (flag_mri
6627 && *s == '*'
6628 && (s == input_line_pointer
6629 || *(s-1) == ' '
6630 || *(s-1) == '\t'))))
252b5132
RH		 6631 s++;
6632 --s;
6633 while (*s == ' ' || *s == '\t')
6634 --s;
6635 if (s - input_line_pointer > 1
6636 && s[-1] == '.')
6637 s -= 2;
6638 if (s - input_line_pointer < 2
6639 || strncasecmp (s - 1, "DO", 2) != 0)
6640 {
6641 as_bad (_("missing do"));
6642 ignore_rest_of_line ();
6643 return;
6644 }
6645
6646 n = push_mri_control (mri_while);
6647
6648 colon (n->next);
6649
6650 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6651 s[1] == '.' ? s[2] : '\0');
6652
6653 input_line_pointer = s + 1;
6654 if (*input_line_pointer == '.')
6655 input_line_pointer += 2;
6656
6657 if (flag_mri)
6658 {
6659 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6660 ++input_line_pointer;
6661 }
6662
6663 demand_empty_rest_of_line ();
6664}
6665
6666/* Handle the MRI ENDW pseudo-op. */
6667
6668static void
6669s_mri_endw (ignore)
36823076 6670 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6671{
6672 char *buf;
6673
6674 if (mri_control_stack == NULL
6675 || mri_control_stack->type != mri_while)
6676 {
6677 as_bad (_("endw without while"));
6678 ignore_rest_of_line ();
6679 return;
6680 }
6681
6682 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6683 sprintf (buf, "bra %s", mri_control_stack->next);
6684 mri_assemble (buf);
6685 free (buf);
6686
6687 colon (mri_control_stack->bottom);
6688
6689 pop_mri_control ();
6690
6691 if (flag_mri)
6692 {
6693 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6694 ++input_line_pointer;
6695 }
6696
6697 demand_empty_rest_of_line ();
6698}
6699\f
6700/*
6701 * md_parse_option
6702 * Invocation line includes a switch not recognized by the base assembler.
6703 * See if it's a processor-specific option. These are:
6704 *
6705 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6706 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6707 * Select the architecture. Instructions or features not
6708 * supported by the selected architecture cause fatal
6709 * errors. More than one may be specified. The default is
6710 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6711 * for -m68000, and -m68882 is a synonym for -m68881.
6712 * -[A]m[c]no-68851, -[A]m[c]no-68881
6713 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6714 * so don't use or document it, but that's the way the parsing
6715 * works).
6716 *
6717 * -pic Indicates PIC.
6718 * -k Indicates PIC. (Sun 3 only.)
28e7409f 6719 * --pcrel Never turn PC-relative branches into absolute jumps.
252b5132
RH		 6720 *
6721 * --bitwise-or
6722 * Permit `|' to be used in expressions.
6723 *
6724 */
6725
6726#ifdef OBJ_ELF
5a38dc70 6727const char *md_shortopts = "lSA:m:kQ:V";
252b5132 6728#else
5a38dc70 6729const char *md_shortopts = "lSA:m:k";
252b5132
RH		 6730#endif
6731
6732struct option md_longopts[] = {
6733#define OPTION_PIC (OPTION_MD_BASE)
6734 {"pic", no_argument, NULL, OPTION_PIC},
6735#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6736 {"register-prefix-optional", no_argument, NULL,
6737 OPTION_REGISTER_PREFIX_OPTIONAL},
6738#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6739 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6740#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6741 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6742#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6743 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6744#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6745 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6746#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6747 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 6748#define OPTION_PCREL (OPTION_MD_BASE + 7)
6749 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 6750 {NULL, no_argument, NULL, 0}
6751};
bc805888 6752size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 6753
6754int
6755md_parse_option (c, arg)
6756 int c;
6757 char *arg;
6758{
6759 switch (c)
6760 {
6761 case 'l': /* -l means keep external to 2 bit offset
6762 rather than 16 bit one */
6763 flag_short_refs = 1;
6764 break;
6765
6766 case 'S': /* -S means that jbsr's always turn into
6767 jsr's. */
6768 flag_long_jumps = 1;
6769 break;
6770
28e7409f
NC		 6771 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6772 branches into absolute jumps. */
6773 flag_keep_pcrel = 1;
6774 break;
6775
252b5132
RH		 6776 case 'A':
6777 if (*arg == 'm')
8a104df9 6778 arg++;
252b5132
RH		 6779 /* intentional fall-through */
6780 case 'm':
6781
6782 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6783 {
6784 int i;
6785 unsigned long arch;
6786 const char *oarg = arg;
6787
6788 arg += 3;
6789 if (*arg == 'm')
6790 {
6791 arg++;
6792 if (arg[0] == 'c' && arg[1] == '6')
6793 arg++;
6794 }
6795 for (i = 0; i < n_archs; i++)
6796 if (!strcmp (arg, archs[i].name))
6797 break;
6798 if (i == n_archs)
6799 {
6800 unknown:
6801 as_bad (_("unrecognized option `%s'"), oarg);
6802 return 0;
6803 }
6804 arch = archs[i].arch;
6805 if (arch == m68881)
6806 no_68881 = 1;
6807 else if (arch == m68851)
6808 no_68851 = 1;
6809 else
6810 goto unknown;
6811 }
6812 else
6813 {
6814 int i;
6815
6816 if (arg[0] == 'c' && arg[1] == '6')
6817 arg++;
6818
6819 for (i = 0; i < n_archs; i++)
6820 if (!strcmp (arg, archs[i].name))
6821 {
6822 unsigned long arch = archs[i].arch;
6823 if (cpu_of_arch (arch))
6824 /* It's a cpu spec. */
6825 {
6826 current_architecture &= ~m68000up;
6827 current_architecture |= arch;
6828 }
6829 else if (arch == m68881)
6830 {
6831 current_architecture |= m68881;
6832 no_68881 = 0;
6833 }
6834 else if (arch == m68851)
6835 {
6836 current_architecture |= m68851;
6837 no_68851 = 0;
6838 }
6839 else
6840 /* ??? */
6841 abort ();
6842 break;
6843 }
6844 if (i == n_archs)
6845 {
6846 as_bad (_("unrecognized architecture specification `%s'"), arg);
6847 return 0;
6848 }
6849 }
6850 break;
6851
6852 case OPTION_PIC:
6853 case 'k':
6854 flag_want_pic = 1;
6855 break; /* -pic, Position Independent Code */
6856
6857 case OPTION_REGISTER_PREFIX_OPTIONAL:
6858 flag_reg_prefix_optional = 1;
6859 reg_prefix_optional_seen = 1;
6860 break;
6861
6862 /* -V: SVR4 argument to print version ID. */
6863 case 'V':
6864 print_version_id ();
6865 break;
6866
6867 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6868 should be emitted or not. FIXME: Not implemented. */
6869 case 'Q':
6870 break;
6871
6872 case OPTION_BITWISE_OR:
6873 {
6874 char *n, *t;
6875 const char *s;
6876
6877 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6878 t = n;
6879 for (s = m68k_comment_chars; *s != '\0'; s++)
6880 if (*s != '|')
6881 *t++ = *s;
6882 *t = '\0';
6883 m68k_comment_chars = n;
6884 }
6885 break;
6886
6887 case OPTION_BASE_SIZE_DEFAULT_16:
6888 m68k_index_width_default = SIZE_WORD;
6889 break;
6890
6891 case OPTION_BASE_SIZE_DEFAULT_32:
6892 m68k_index_width_default = SIZE_LONG;
6893 break;
6894
6895 case OPTION_DISP_SIZE_DEFAULT_16:
6896 m68k_rel32 = 0;
6897 m68k_rel32_from_cmdline = 1;
6898 break;
6899
6900 case OPTION_DISP_SIZE_DEFAULT_32:
6901 m68k_rel32 = 1;
6902 m68k_rel32_from_cmdline = 1;
6903 break;
6904
6905 default:
6906 return 0;
6907 }
6908
6909 return 1;
6910}
6911
6912void
6913md_show_usage (stream)
6914 FILE *stream;
6915{
76f57f3a 6916 const char *default_cpu = TARGET_CPU;
f1f5ef86
AM		 6917 int i;
6918 unsigned int default_arch;
76f57f3a 6919
8a104df9 6920 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 6921 if (*default_cpu == 'm')
6922 default_cpu++;
6923 for (i = 0; i < n_archs; i++)
6924 {
6925 if (strcasecmp (default_cpu, archs[i].name) == 0)
6926 {
6927 default_arch = archs[i].arch;
6928 for (i = 0; i < n_archs; i++)
6929 {
6930 if (archs[i].arch == default_arch
6931 && !archs[i].alias)
6932 {
6933 default_cpu = archs[i].name;
6934 break;
6935 }
6936 }
6937 }
6938 }
6939
bc805888 6940 fprintf (stream, _("\
252b5132
RH		 6941680X0 options:\n\
6942-l use 1 word for refs to undefined symbols [default 2]\n\
98b32482
NC		 6943-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
6944-m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
6945-m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m5307 | -m5407\n\
76f57f3a 6946 specify variant of 680X0 architecture [default %s]\n\
252b5132
RH		 6947-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6948 target has/lacks floating-point coprocessor\n\
76f57f3a
JT		 6949 [default yes for 68020, 68030, and cpu32]\n"),
6950 default_cpu);
bc805888 6951 fprintf (stream, _("\
252b5132
RH		 6952-m68851 | -mno-68851\n\
6953 target has/lacks memory-management unit coprocessor\n\
6954 [default yes for 68020 and up]\n\
6955-pic, -k generate position independent code\n\
6956-S turn jbsr into jsr\n\
28e7409f 6957--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 6958--register-prefix-optional\n\
6959 recognize register names without prefix character\n\
6960--bitwise-or do not treat `|' as a comment character\n"));
6961 fprintf (stream, _("\
6962--base-size-default-16 base reg without size is 16 bits\n\
6963--base-size-default-32 base reg without size is 32 bits (default)\n\
6964--disp-size-default-16 displacement with unknown size is 16 bits\n\
6965--disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6966}
6967\f
6968#ifdef TEST2
6969
6970/* TEST2: Test md_assemble() */
6971/* Warning, this routine probably doesn't work anymore */
6972
6973main ()
6974{
6975 struct m68k_it the_ins;
6976 char buf[120];
6977 char *cp;
6978 int n;
6979
6980 m68k_ip_begin ();
6981 for (;;)
6982 {
6983 if (!gets (buf) || !*buf)
6984 break;
6985 if (buf[0] == '|' || buf[1] == '.')
6986 continue;
6987 for (cp = buf; *cp; cp++)
6988 if (*cp == '\t')
6989 *cp = ' ';
6990 if (is_label (buf))
6991 continue;
6992 memset (&the_ins, '\0', sizeof (the_ins));
6993 m68k_ip (&the_ins, buf);
6994 if (the_ins.error)
6995 {
6996 printf (_("Error %s in %s\n"), the_ins.error, buf);
6997 }
6998 else
6999 {
7000 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7001 for (n = 0; n < the_ins.numo; n++)
7002 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7003 printf (" ");
7004 print_the_insn (&the_ins.opcode[0], stdout);
7005 (void) putchar ('\n');
7006 }
7007 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7008 {
7009 if (the_ins.operands[n].error)
7010 {
7011 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7012 continue;
7013 }
7014 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7015 if (the_ins.operands[n].b_const)
7016 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7017 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7018 if (the_ins.operands[n].b_iadd)
7019 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7020 (void) putchar ('\n');
7021 }
7022 }
7023 m68k_ip_end ();
7024 return 0;
7025}
7026
7027is_label (str)
7028 char *str;
7029{
7030 while (*str == ' ')
7031 str++;
7032 while (*str && *str != ' ')
7033 str++;
7034 if (str[-1] == ':' || str[1] == '=')
7035 return 1;
7036 return 0;
7037}
7038
7039#endif
7040
7041/* Possible states for relaxation:
7042
7043 0 0 branch offset byte (bra, etc)
7044 0 1 word
7045 0 2 long
7046
7047 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7048 1 1 word
7049 1 2 long
7050
7051 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7052 2 1 word-long
7053 2 2 long-word
7054 2 3 long-long
7055
7056 */
7057
7058/* We have no need to default values of symbols. */
7059
252b5132
RH		 7060symbolS *
7061md_undefined_symbol (name)
36823076 7062 char *name ATTRIBUTE_UNUSED;
252b5132
RH		 7063{
7064 return 0;
7065}
7066
7067/* Round up a section size to the appropriate boundary. */
7068valueT
7069md_section_align (segment, size)
36823076 7070 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7071 valueT size;
7072{
7073#ifdef OBJ_AOUT
7074#ifdef BFD_ASSEMBLER
7075 /* For a.out, force the section size to be aligned. If we don't do
7076 this, BFD will align it for us, but it will not write out the
7077 final bytes of the section. This may be a bug in BFD, but it is
7078 easier to fix it here since that is how the other a.out targets
7079 work. */
7080 int align;
7081
7082 align = bfd_get_section_alignment (stdoutput, segment);
7083 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7084#endif
7085#endif
7086
7087 return size;
7088}
7089
7090/* Exactly what point is a PC-relative offset relative TO?
7091 On the 68k, it is relative to the address of the first extension
7092 word. The difference between the addresses of the offset and the
92774660 7093 first extension word is stored in fx_pcrel_adjust. */
252b5132
RH		 7094long
7095md_pcrel_from (fixP)
7096 fixS *fixP;
7097{
7098 int adjust;
7099
8390138c
AS		 7100 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7101 sign extend the value here. */
7102 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7103 if (adjust == 64)
7104 adjust = -1;
7105 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7106}
7107
7108#ifndef BFD_ASSEMBLER
7109#ifdef OBJ_COFF
7110
252b5132
RH		 7111void
7112tc_coff_symbol_emit_hook (ignore)
8fce3f5e 7113 symbolS *ignore ATTRIBUTE_UNUSED;
252b5132
RH		 7114{
7115}
7116
7117int
7118tc_coff_sizemachdep (frag)
7119 fragS *frag;
7120{
7121 switch (frag->fr_subtype & 0x3)
7122 {
7123 case BYTE:
7124 return 1;
7125 case SHORT:
7126 return 2;
7127 case LONG:
7128 return 4;
7129 default:
7130 abort ();
7131 return 0;
7132 }
7133}
7134
7135#endif
7136#endif
0d96863f 7137#ifdef OBJ_ELF
8a104df9
KH		 7138void
7139m68k_elf_final_processing ()
0d96863f 7140{
8a104df9
KH		 7141 /* Set file-specific flags if this is a cpu32 processor */
7142 if (cpu_of_arch (current_architecture) & cpu32)
7143 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7144 else if ((cpu_of_arch (current_architecture) & m68000up)
7145 && !(cpu_of_arch (current_architecture) & m68020up))
7146 elf_elfheader (stdoutput)->e_flags |= EF_M68000;
0d96863f
CM		 7147}
7148#endif
GDB Binutils - Deliverables
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