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* config/m68k-parse.y: New file: bison grammar for m68k operands,
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
CommitLineData
a1c7c0f3
ILT		 1/* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 1995 Free Software Foundation, Inc.
6d27d3a2 3
a39116f1 4 This file is part of GAS, the GNU Assembler.
6d27d3a2 5
a39116f1
RP		 6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
6d27d3a2 10
a39116f1
RP		 11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
6d27d3a2 15
a39116f1 16 You should have received a copy of the GNU General Public License
a1c7c0f3
ILT		 17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
19 02111-1307, USA. */
fecd2382
RP		 20
21#include <ctype.h>
f8701a3f 22#define NO_RELOC 0
fecd2382 23#include "as.h"
fecd2382
RP		 24#include "obstack.h"
25
e0982afe 26#include "opcode/m68k.h"
a1c7c0f3 27#include "m68k-parse.h"
3ad9ec6a 28
fecd2382
RP		 29/* This array holds the chars that always start a comment. If the
30 pre-processor is disabled, these aren't very useful */
5f8cb05e
ILT		 31#ifdef OBJ_ELF
32CONST char comment_chars[] = "|#";
33#else
49864cfa 34CONST char comment_chars[] = "|";
5f8cb05e 35#endif
fecd2382
RP		 36
37/* This array holds the chars that only start a comment at the beginning of
38 a line. If the line seems to have the form '# 123 filename'
39 .line and .file directives will appear in the pre-processed output */
40/* Note that input_file.c hand checks for '#' at the beginning of the
41 first line of the input file. This is because the compiler outputs
42 #NO_APP at the beginning of its output. */
43/* Also note that comments like this one will always work. */
49864cfa 44CONST char line_comment_chars[] = "#";
fecd2382 45
49864cfa 46CONST char line_separator_chars[] = "";
587c4264 47
fecd2382 48/* Chars that can be used to separate mant from exp in floating point nums */
49864cfa 49CONST char EXP_CHARS[] = "eE";
fecd2382 50
49864cfa
KR		 51/* Chars that mean this number is a floating point constant, as
52 in "0f12.456" or "0d1.2345e12". */
fecd2382 53
49864cfa 54CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
fecd2382
RP		 55
56/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
57 changed in read.c . Ideally it shouldn't have to know about it at all,
49864cfa 58 but nothing is ideal around here. */
fecd2382 59
49864cfa 60const int md_reloc_size = 8; /* Size of relocation record */
fecd2382 61
b80d39a0 62/* Are we trying to generate PIC code? If so, absolute references
dff60b7d
ILT		 63 ought to be made into linkage table references or pc-relative
64 references. */
b80d39a0
KR		 65int flag_want_pic;
66
9ad5755f
KR		 67static int flag_short_refs; /* -l option */
68static int flag_long_jumps; /* -S option */
69
82489ea0
KR		 70#ifdef REGISTER_PREFIX_OPTIONAL
71int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
72#else
73int flag_reg_prefix_optional;
74#endif
75
fecd2382
RP		 76/* Its an arbitrary name: This means I don't approve of it */
77/* See flames below */
78static struct obstack robyn;
79
80#define TAB(x,y) (((x)<<2)+(y))
81#define TABTYPE(xy) ((xy) >> 2)
82#define BYTE 0
83#define SHORT 1
84#define LONG 2
85#define SZ_UNDEF 3
3ad9ec6a 86#undef BRANCH
04ef74bb 87/* Case `g' except when BCC68000 is applicable. */
3ad9ec6a 88#define ABRANCH 1
04ef74bb 89/* Coprocessor branches. */
fecd2382 90#define FBRANCH 2
04ef74bb
KR		 91/* Mode 7.2 -- program counter indirect with (16-bit) displacement,
92 supported on all cpus. Widens to 32-bit absolute. */
fecd2382 93#define PCREL 3
04ef74bb
KR		 94/* For inserting an extra jmp instruction with long offset on 68000,
95 for expanding conditional branches. (Not bsr or bra.) Since the
96 68000 doesn't support 32-bit displacements for conditional
97 branches, we fake it by reversing the condition and branching
98 around a jmp with an absolute long operand. */
fecd2382 99#define BCC68000 4
04ef74bb
KR		 100/* For the DBcc "instructions". If the displacement requires 32 bits,
101 the branch-around-a-jump game is played here too. */
fecd2382 102#define DBCC 5
04ef74bb 103/* Not currently used? */
fecd2382 104#define PCLEA 6
04ef74bb
KR		 105/* Mode AINDX (apc-relative) using PC, with variable target, might fit
106 in 16 or 8 bits. */
107#define PCINDEX 7
fecd2382 108
bcb8dff8
KR		 109struct m68k_incant
110 {
a1c7c0f3 111 const char *m_operands;
bcb8dff8
KR		 112 unsigned long m_opcode;
113 short m_opnum;
114 short m_codenum;
115 int m_arch;
116 struct m68k_incant *m_next;
117 };
118
119#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
120#define gettwo(x) (((x)->m_opcode)&0xffff)
121
a1c7c0f3
ILT		 122static const enum m68k_register m68000_control_regs[] = { 0 };
123static const enum m68k_register m68010_control_regs[] = {
82489ea0
KR		 124 SFC, DFC, USP, VBR,
125 0
126};
a1c7c0f3 127static const enum m68k_register m68020_control_regs[] = {
82489ea0
KR		 128 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
129 0
130};
a1c7c0f3 131static const enum m68k_register m68040_control_regs[] = {
82489ea0
KR		 132 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
133 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
134 0
135};
a1c7c0f3 136static const enum m68k_register m68060_control_regs[] = {
82489ea0
KR		 137 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
138 USP, VBR, URP, SRP, PCR,
139 0
140};
b79de3a1 141#define cpu32_control_regs m68010_control_regs
82489ea0 142
a1c7c0f3 143static const enum m68k_register *control_regs;
fecd2382
RP		 144
145/* internal form of a 68020 instruction */
355afbcd 146struct m68k_it
a1c7c0f3
ILT		 147{
148 const char *error;
149 const char *args; /* list of opcode info */
150 int numargs;
355afbcd 151
a1c7c0f3
ILT		 152 int numo; /* Number of shorts in opcode */
153 short opcode[11];
355afbcd 154
a1c7c0f3 155 struct m68k_op operands[6];
355afbcd 156
a1c7c0f3
ILT		 157 int nexp; /* number of exprs in use */
158 struct m68k_exp exprs[4];
355afbcd 159
a1c7c0f3
ILT		 160 int nfrag; /* Number of frags we have to produce */
161 struct
162 {
163 int fragoff; /* Where in the current opcode the frag ends */
164 symbolS *fadd;
165 long foff;
166 int fragty;
167 }
168 fragb[4];
355afbcd 169
a1c7c0f3
ILT		 170 int nrel; /* Num of reloc strucs in use */
171 struct
172 {
173 int n;
174 expressionS exp;
175 char wid;
176 char pcrel;
177 /* In a pc relative address the difference between the address
178 of the offset and the address that the offset is relative
179 to. This depends on the addressing mode. Basically this
180 is the value to put in the offset field to address the
181 first byte of the offset, without regarding the special
182 significance of some values (in the branch instruction, for
183 example). */
184 int pcrel_fix;
185 }
186 reloc[5]; /* Five is enough??? */
187};
fecd2382 188
865a2edf
MT		 189#define cpu_of_arch(x) ((x) & m68000up)
190#define float_of_arch(x) ((x) & mfloat)
191#define mmu_of_arch(x) ((x) & mmmu)
192
355afbcd 193static struct m68k_it the_ins; /* the instruction being assembled */
fecd2382 194
a1c7c0f3
ILT		 195#define op(ex) ((ex)->exp.X_op)
196#define adds(ex) ((ex)->exp.X_add_symbol)
197#define subs(ex) ((ex)->exp.X_op_symbol)
198#define offs(ex) ((ex)->exp.X_add_number)
49864cfa 199
7c15cbe8 200/* Macros for adding things to the m68k_it struct */
fecd2382
RP		 201
202#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
203
204/* Like addword, but goes BEFORE general operands */
bcb8dff8
KR		 205static void
206insop (w, opcode)
207 int w;
208 struct m68k_incant *opcode;
209{
210 int z;
211 for(z=the_ins.numo;z>opcode->m_codenum;--z)
212 the_ins.opcode[z]=the_ins.opcode[z-1];
213 for(z=0;z<the_ins.nrel;z++)
214 the_ins.reloc[z].n+=2;
5f8cb05e
ILT		 215 for (z = 0; z < the_ins.nfrag; z++)
216 the_ins.fragb[z].fragoff++;
bcb8dff8
KR		 217 the_ins.opcode[opcode->m_codenum]=w;
218 the_ins.numo++;
219}
fecd2382 220
1404ef23
KR		 221/* The numo+1 kludge is so we can hit the low order byte of the prev word.
222 Blecch. */
49864cfa 223static void
5f8cb05e 224add_fix (width, exp, pc_rel, pc_fix)
49864cfa
KR		 225 char width;
226 struct m68k_exp *exp;
227 int pc_rel;
5f8cb05e 228 int pc_fix;
49864cfa
KR		 229{
230 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
231 ? (the_ins.numo*2-1)
232 : (((width)=='b')
5f8cb05e 233 ? (the_ins.numo*2+1)
49864cfa 234 : (the_ins.numo*2)));
a1c7c0f3 235 the_ins.reloc[the_ins.nrel].exp = exp->exp;
49864cfa 236 the_ins.reloc[the_ins.nrel].wid = width;
5f8cb05e 237 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
49864cfa 238 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
1404ef23
KR		 239}
240
5f8cb05e
ILT		 241/* Cause an extra frag to be generated here, inserting up to 10 bytes
242 (that value is chosen in the frag_var call in md_assemble). TYPE
243 is the subtype of the frag to be generated; its primary type is
244 rs_machine_dependent.
245
246 The TYPE parameter is also used by md_convert_frag_1 and
247 md_estimate_size_before_relax. The appropriate type of fixup will
248 be emitted by md_convert_frag_1.
249
250 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
49864cfa
KR		 251static void
252add_frag(add,off,type)
253 symbolS *add;
254 long off;
255 int type;
256{
257 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
258 the_ins.fragb[the_ins.nfrag].fadd=add;
259 the_ins.fragb[the_ins.nfrag].foff=off;
260 the_ins.fragb[the_ins.nfrag++].fragty=type;
1404ef23 261}
fecd2382 262
a1c7c0f3
ILT		 263#define isvar(ex) \
264 (op (ex) != O_constant && op (ex) != O_big)
fecd2382 265
49864cfa
KR		 266static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
267static int get_num PARAMS ((struct m68k_exp *exp, int ok));
49864cfa
KR		 268static int reverse_16_bits PARAMS ((int in));
269static int reverse_8_bits PARAMS ((int in));
49864cfa
KR		 270static void install_gen_operand PARAMS ((int mode, int val));
271static void install_operand PARAMS ((int mode, int val));
bcb8dff8
KR		 272static void s_bss PARAMS ((int));
273static void s_data1 PARAMS ((int));
274static void s_data2 PARAMS ((int));
275static void s_even PARAMS ((int));
276static void s_proc PARAMS ((int));
49864cfa
KR		 277
278static int current_architecture;
7c15cbe8 279
b79de3a1
KR		 280struct m68k_cpu {
281 unsigned long arch;
282 const char *name;
283};
284
285static const struct m68k_cpu archs[] = {
286 { m68000, "68000" },
287 { m68010, "68010" },
288 { m68020, "68020" },
289 { m68030, "68030" },
290 { m68040, "68040" },
291 { m68060, "68060" },
292 { cpu32, "cpu32" },
293 { m68881, "68881" },
294 { m68851, "68851" },
295 /* Aliases (effectively, so far as gas is concerned) for the above
296 cpus. */
297 { m68020, "68k" },
298 { m68000, "68302" },
299 { m68000, "68008" },
300 { cpu32, "68331" },
301 { cpu32, "68332" },
302 { cpu32, "68333" },
303 { cpu32, "68340" },
5f8cb05e 304 { cpu32, "68360" },
b79de3a1
KR		 305 { m68881, "68882" },
306};
307
308static const int n_archs = sizeof (archs) / sizeof (archs[0]);
309
fecd2382
RP		 310/* BCC68000 is for patching in an extra jmp instruction for long offsets
311 on the 68000. The 68000 doesn't support long branches with branchs */
312
313/* This table desribes how you change sizes for the various types of variable
314 size expressions. This version only supports two kinds. */
315
49864cfa
KR		 316/* Note that calls to frag_var need to specify the maximum expansion
317 needed; this is currently 10 bytes for DBCC. */
fecd2382
RP		 318
319/* The fields are:
a39116f1
RP		 320 How far Forward this mode will reach:
321 How far Backward this mode will reach:
322 How many bytes this mode will add to the size of the frag
323 Which mode to go to if the offset won't fit in this one
324 */
04ef74bb 325relax_typeS md_relax_table[] =
355afbcd
KR		 326{
327 {1, 1, 0, 0}, /* First entries aren't used */
328 {1, 1, 0, 0}, /* For no good reason except */
329 {1, 1, 0, 0}, /* that the VAX doesn't either */
330 {1, 1, 0, 0},
331
332 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
333 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
334 {0, 0, 4, 0},
335 {1, 1, 0, 0},
336
337 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
338 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
339 {0, 0, 4, 0},
340 {1, 1, 0, 0},
341
342 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
343 {(32767), (-32768), 2, TAB (PCREL, LONG)},
344 {0, 0, 4, 0},
345 {1, 1, 0, 0},
346
347 {(127), (-128), 0, TAB (BCC68000, SHORT)},
348 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
349 {0, 0, 6, 0}, /* jmp long space */
350 {1, 1, 0, 0},
351
352 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
353 {(32767), (-32768), 2, TAB (DBCC, LONG)},
354 {0, 0, 10, 0}, /* bra/jmp long space */
355 {1, 1, 0, 0},
356
357 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
358 {32767, -32768, 2, TAB (PCLEA, LONG)},
359 {0, 0, 6, 0},
360 {1, 1, 0, 0},
361
04ef74bb
KR		 362 /* For, e.g., jmp pcrel indexed. */
363 {125, -130, 0, TAB (PCINDEX, SHORT)},
364 {32765, -32770, 2, TAB (PCINDEX, LONG)},
365 {0, 0, 4, 0},
366 {1, 1, 0, 0},
355afbcd 367};
fecd2382
RP		 368
369/* These are the machine dependent pseudo-ops. These are included so
370 the assembler can work on the output from the SUN C compiler, which
371 generates these.
a39116f1 372 */
fecd2382
RP		 373
374/* This table describes all the machine specific pseudo-ops the assembler
375 has to support. The fields are:
a39116f1
RP		 376 pseudo-op name without dot
377 function to call to execute this pseudo-op
378 Integer arg to pass to the function
379 */
49864cfa 380CONST pseudo_typeS md_pseudo_table[] =
355afbcd
KR		 381{
382 {"data1", s_data1, 0},
383 {"data2", s_data2, 0},
384 {"bss", s_bss, 0},
385 {"even", s_even, 0},
386 {"skip", s_space, 0},
387 {"proc", s_proc, 0},
bec66218 388#ifdef TE_SUN3
355afbcd 389 {"align", s_align_bytes, 0},
5f8cb05e
ILT		 390#endif
391#ifdef OBJ_ELF
392 {"swbeg", s_ignore, 0},
bec66218 393#endif
355afbcd 394 {0, 0, 0}
fecd2382
RP		 395};
396
397
3ad9ec6a 398/* The mote pseudo ops are put into the opcode table, since they
355afbcd 399 don't start with a . they look like opcodes to gas.
3ad9ec6a 400 */
355afbcd 401extern void obj_coff_section ();
3ad9ec6a 402
49864cfa 403CONST pseudo_typeS mote_pseudo_table[] =
3ad9ec6a
ILT		 404{
405
b79de3a1 406 {"dcl", cons, 4},
355afbcd 407 {"dc", cons, 2},
b79de3a1
KR		 408 {"dcw", cons, 2},
409 {"dcb", cons, 1},
3ad9ec6a 410
b79de3a1 411 {"dsl", s_space, 4},
355afbcd 412 {"ds", s_space, 2},
b79de3a1
KR		 413 {"dsw", s_space, 2},
414 {"dsb", s_space, 1},
3ad9ec6a 415
355afbcd
KR		 416 {"xdef", s_globl, 0},
417 {"align", s_align_ptwo, 0},
3ad9ec6a 418#ifdef M68KCOFF
355afbcd
KR		 419 {"sect", obj_coff_section, 0},
420 {"section", obj_coff_section, 0},
3ad9ec6a 421#endif
bcb8dff8 422 {0, 0, 0}
3ad9ec6a
ILT		 423};
424
fecd2382
RP		 425#define issbyte(x) ((x)>=-128 && (x)<=127)
426#define isubyte(x) ((x)>=0 && (x)<=255)
427#define issword(x) ((x)>=-32768 && (x)<=32767)
428#define isuword(x) ((x)>=0 && (x)<=65535)
f8701a3f 429
e284846a 430#define isbyte(x) ((x)>= -255 && (x)<=255)
fecd2382
RP		 431#define isword(x) ((x)>=-32768 && (x)<=65535)
432#define islong(x) (1)
f8701a3f
SC		 433
434extern char *input_line_pointer;
fecd2382 435
fecd2382
RP		 436static char mklower_table[256];
437#define mklower(c) (mklower_table[(unsigned char)(c)])
f8701a3f 438static char notend_table[256];
fecd2382 439static char alt_notend_table[256];
a1c7c0f3
ILT		 440#define notend(s) \
441 (! (notend_table[(unsigned char) *s] \
442 || (*s == ':' \
443 && alt_notend_table[(unsigned char) s[1]])))
7c15cbe8 444
49864cfa 445#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
3ad9ec6a 446
82489ea0
KR		 447#ifdef NO_PCREL_RELOCS
448
449int
450make_pcrel_absolute(fixP, add_number)
451 fixS *fixP;
452 long *add_number;
453{
454 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
455
456 /* rewrite the PC relative instructions to absolute address ones.
457 * these are rumoured to be faster, and the apollo linker refuses
458 * to deal with the PC relative relocations.
459 */
460 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
461 {
462 opcode[0] = 0x4e;
463 opcode[1] = 0xf9;
464 }
465 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
466 {
467 opcode[0] = 0x4e;
468 opcode[1] = 0xb9;
469 }
470 else
471 as_fatal ("Unknown PC relative instruction");
472 *add_number -= 4;
473 return 0;
474}
475
476#endif /* NO_PCREL_RELOCS */
477
355afbcd
KR		 478short
479tc_coff_fix2rtype (fixP)
480 fixS *fixP;
fecd2382 481{
82489ea0
KR		 482#ifdef NO_PCREL_RELOCS
483 know (fixP->fx_pcrel == 0);
484 return (fixP->fx_size == 1 ? R_RELBYTE
485 : fixP->fx_size == 2 ? R_DIR16
486 : R_DIR32);
487#else
355afbcd
KR		 488 return (fixP->fx_pcrel ?
489 (fixP->fx_size == 1 ? R_PCRBYTE :
490 fixP->fx_size == 2 ? R_PCRWORD :
491 R_PCRLONG) :
492 (fixP->fx_size == 1 ? R_RELBYTE :
493 fixP->fx_size == 2 ? R_RELWORD :
494 R_RELLONG));
82489ea0 495#endif
3ad9ec6a
ILT		 496}
497
498#endif
fecd2382 499
49864cfa
KR		 500#ifdef BFD_ASSEMBLER
501
502arelent *
503tc_gen_reloc (section, fixp)
504 asection *section;
505 fixS *fixp;
506{
507 arelent *reloc;
508 bfd_reloc_code_real_type code;
509
510#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
511 switch (F (fixp->fx_size, fixp->fx_pcrel))
512 {
513#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
514 MAP (1, 0, BFD_RELOC_8);
515 MAP (2, 0, BFD_RELOC_16);
516 MAP (4, 0, BFD_RELOC_32);
517 MAP (1, 1, BFD_RELOC_8_PCREL);
518 MAP (2, 1, BFD_RELOC_16_PCREL);
519 MAP (4, 1, BFD_RELOC_32_PCREL);
520 default:
521 abort ();
522 }
523
524 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
525 assert (reloc != 0);
526 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
527 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
528 if (fixp->fx_pcrel)
529 reloc->addend = fixp->fx_addnumber;
530 else
531 reloc->addend = 0;
532
533 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
534 assert (reloc->howto != 0);
535
536 return reloc;
537}
538
539#endif /* BFD_ASSEMBLER */
540
49864cfa
KR		 541/* Handle of the OPCODE hash table. NULL means any use before
542 m68k_ip_begin() will crash. */
543static struct hash_control *op_hash;
fecd2382 544\f
a1c7c0f3 545/* Assemble an m68k instruction. */
355afbcd 546
355afbcd
KR		 547void
548m68k_ip (instring)
6d27d3a2 549 char *instring;
fecd2382 550{
6d27d3a2
KR		 551 register char *p;
552 register struct m68k_op *opP;
553 register struct m68k_incant *opcode;
a1c7c0f3 554 register const char *s;
6d27d3a2 555 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
3ad9ec6a 556 char *pdot, *pdotmove;
a1c7c0f3 557 enum m68k_size siz1, siz2;
355afbcd
KR		 558 char c;
559 int losing;
560 int opsfound;
561 char *crack_operand ();
6d27d3a2
KR		 562 LITTLENUM_TYPE words[6];
563 LITTLENUM_TYPE *wordp;
8be74775 564 unsigned long ok_arch = 0;
6d27d3a2
KR		 565
566 if (*instring == ' ')
567 instring++; /* skip leading whitespace */
568
569 /* Scan up to end of operation-code, which MUST end in end-of-string
570 or exactly 1 space. */
3ad9ec6a 571 pdot = 0;
355afbcd
KR		 572 for (p = instring; *p != '\0'; p++)
573 {
574 if (*p == ' ')
575 break;
576 if (*p == '.')
577 pdot = p;
578 }
6d27d3a2 579
355afbcd
KR		 580 if (p == instring)
581 {
582 the_ins.error = "No operator";
355afbcd
KR		 583 return;
584 }
6d27d3a2
KR		 585
586 /* p now points to the end of the opcode name, probably whitespace.
a1c7c0f3
ILT		 587 Make sure the name is null terminated by clobbering the
588 whitespace, look it up in the hash table, then fix it back.
3ad9ec6a 589 Remove a dot, first, since the opcode tables have none. */
355afbcd
KR		 590 if (pdot != NULL)
591 {
592 for (pdotmove = pdot; pdotmove < p; pdotmove++)
593 *pdotmove = pdotmove[1];
594 p--;
595 }
3ad9ec6a 596
6d27d3a2
KR		 597 c = *p;
598 *p = '\0';
355afbcd 599 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
6d27d3a2
KR		 600 *p = c;
601
355afbcd
KR		 602 if (pdot != NULL)
603 {
604 for (pdotmove = p; pdotmove > pdot; pdotmove--)
605 *pdotmove = pdotmove[-1];
606 *pdot = '.';
607 ++p;
608 }
3ad9ec6a 609
355afbcd
KR		 610 if (opcode == NULL)
611 {
612 the_ins.error = "Unknown operator";
355afbcd
KR		 613 return;
614 }
6d27d3a2
KR		 615
616 /* found a legitimate opcode, start matching operands */
355afbcd
KR		 617 while (*p == ' ')
618 ++p;
6d27d3a2 619
355afbcd
KR		 620 if (opcode->m_operands == 0)
621 {
622 char *old = input_line_pointer;
623 *old = '\n';
624 input_line_pointer = p;
625 /* Ahh - it's a motorola style psuedo op */
626 mote_pseudo_table[opcode->m_opnum].poc_handler
627 (mote_pseudo_table[opcode->m_opnum].poc_val);
628 input_line_pointer = old;
629 *old = 0;
3ad9ec6a 630
355afbcd
KR		 631 return;
632 }
3ad9ec6a 633
355afbcd
KR		 634 for (opP = &the_ins.operands[0]; *p; opP++)
635 {
355afbcd 636 p = crack_operand (p, opP);
6d27d3a2 637
355afbcd
KR		 638 if (opP->error)
639 {
640 the_ins.error = opP->error;
641 return;
642 }
6d27d3a2 643 }
6d27d3a2
KR		 644
645 opsfound = opP - &the_ins.operands[0];
646
a1c7c0f3
ILT		 647 /* This ugly hack is to support the floating pt opcodes in their
648 standard form. Essentially, we fake a first enty of type COP#1 */
355afbcd
KR		 649 if (opcode->m_operands[0] == 'I')
650 {
651 int n;
6d27d3a2 652
355afbcd
KR		 653 for (n = opsfound; n > 0; --n)
654 the_ins.operands[n] = the_ins.operands[n - 1];
6d27d3a2 655
a1c7c0f3
ILT		 656 memset ((char *) (&the_ins.operands[0]), '\0',
657 sizeof (the_ins.operands[0]));
658 the_ins.operands[0].mode = CONTROL;
355afbcd
KR		 659 the_ins.operands[0].reg = COPNUM; /* COP #1 */
660 opsfound++;
661 }
6d27d3a2
KR		 662
663 /* We've got the operands. Find an opcode that'll accept them */
355afbcd
KR		 664 for (losing = 0;;)
665 {
49864cfa
KR		 666 /* If we didn't get the right number of ops, or we have no
667 common model with this pattern then reject this pattern. */
6d27d3a2 668
355afbcd
KR		 669 if (opsfound != opcode->m_opnum
670 || ((opcode->m_arch & current_architecture) == 0))
671 {
672 ++losing;
673 ok_arch |= opcode->m_arch;
674 }
675 else
676 {
a1c7c0f3
ILT		 677 for (s = opcode->m_operands, opP = &the_ins.operands[0];
678 *s && !losing;
679 s += 2, opP++)
355afbcd
KR		 680 {
681 /* Warning: this switch is huge! */
49864cfa
KR		 682 /* I've tried to organize the cases into this order:
683 non-alpha first, then alpha by letter. Lower-case
684 goes directly before uppercase counterpart. */
685 /* Code with multiple case ...: gets sorted by the lowest
686 case ... it belongs to. I hope this makes sense. */
355afbcd
KR		 687 switch (*s)
688 {
a1c7c0f3
ILT		 689 case '!':
690 switch (opP->mode)
691 {
692 case IMMED:
693 case DREG:
694 case AREG:
695 case FPREG:
696 case CONTROL:
697 case AINC:
698 case ADEC:
699 case REGLST:
700 losing++;
701 break;
702 default:
703 break;
704 }
355afbcd
KR		 705 break;
706
707 case '`':
708 switch (opP->mode)
709 {
355afbcd
KR		 710 case IMMED:
711 case DREG:
712 case AREG:
a1c7c0f3
ILT		 713 case FPREG:
714 case CONTROL:
355afbcd
KR		 715 case AINC:
716 case REGLST:
717 case AINDR:
718 losing++;
bcb8dff8
KR		 719 break;
720 default:
721 break;
355afbcd
KR		 722 }
723 break;
8be74775 724
355afbcd
KR		 725 case '#':
726 if (opP->mode != IMMED)
727 losing++;
a1c7c0f3
ILT		 728 else if (s[1] == 'b'
729 && ! isvar (&opP->disp)
730 && ! expr8 (&opP->disp))
731 losing++;
732 else if (s[1] == 'w'
733 && ! isvar (&opP->disp)
734 && ! expr16 (&opP->disp))
735 losing++;
355afbcd
KR		 736 break;
737
738 case '^':
739 case 'T':
740 if (opP->mode != IMMED)
741 losing++;
742 break;
743
744 case '$':
a1c7c0f3
ILT		 745 if (opP->mode == AREG
746 || opP->mode == CONTROL
747 || opP->mode == FPREG
748 || opP->mode == IMMED
749 || opP->mode == REGLST
750 || (opP->mode != ABSL
751 && (opP->reg == PC
752 || opP->reg == ZPC)))
355afbcd
KR		 753 losing++;
754 break;
755
756 case '%':
a1c7c0f3
ILT		 757 if (opP->mode == CONTROL
758 || opP->mode == FPREG
759 || opP->mode == REGLST
760 || (opP->mode != ABSL
761 && opP->mode != IMMED
762 && (opP->reg == PC
763 || opP->reg == ZPC)))
355afbcd
KR		 764 losing++;
765 break;
766
355afbcd 767 case '&':
a1c7c0f3
ILT		 768 switch (opP->mode)
769 {
770 case DREG:
771 case AREG:
772 case FPREG:
773 case CONTROL:
774 case IMMED:
775 case AINC:
776 case ADEC:
777 case REGLST:
778 losing++;
779 break;
780 case ABSL:
781 break;
782 default:
783 if (opP->reg == PC
784 || opP->reg == ZPC)
785 losing++;
786 break;
787 }
355afbcd
KR		 788 break;
789
790 case '*':
a1c7c0f3
ILT		 791 if (opP->mode == CONTROL
792 || opP->mode == FPREG
793 || opP->mode == REGLST)
355afbcd
KR		 794 losing++;
795 break;
796
797 case '+':
798 if (opP->mode != AINC)
799 losing++;
800 break;
801
802 case '-':
803 if (opP->mode != ADEC)
804 losing++;
805 break;
806
807 case '/':
a1c7c0f3
ILT		 808 switch (opP->mode)
809 {
810 case AREG:
811 case CONTROL:
812 case FPREG:
813 case AINC:
814 case ADEC:
815 case IMMED:
816 case REGLST:
817 losing++;
818 break;
819 default:
820 break;
821 }
355afbcd
KR		 822 break;
823
824 case ';':
a1c7c0f3
ILT		 825 switch (opP->mode)
826 {
827 case AREG:
828 case CONTROL:
829 case FPREG:
830 case REGLST:
831 losing++;
832 break;
833 default:
834 break;
835 }
355afbcd
KR		 836 break;
837
838 case '?':
a1c7c0f3
ILT		 839 switch (opP->mode)
840 {
841 case AREG:
842 case CONTROL:
843 case FPREG:
844 case AINC:
845 case ADEC:
846 case IMMED:
847 case REGLST:
848 losing++;
849 break;
850 case ABSL:
851 break;
852 default:
853 if (opP->reg == PC || opP->reg == ZPC)
854 losing++;
855 break;
856 }
355afbcd
KR		 857 break;
858
859 case '@':
a1c7c0f3
ILT		 860 switch (opP->mode)
861 {
862 case AREG:
863 case CONTROL:
864 case FPREG:
865 case IMMED:
866 case REGLST:
867 losing++;
868 break;
869 default:
870 break;
871 }
355afbcd
KR		 872 break;
873
874 case '~': /* For now! (JF FOO is this right?) */
a1c7c0f3
ILT		 875 switch (opP->mode)
876 {
877 case DREG:
878 case AREG:
879 case CONTROL:
880 case FPREG:
881 case IMMED:
882 case REGLST:
883 losing++;
884 break;
885 case ABSL:
886 break;
887 default:
888 if (opP->reg == PC
889 || opP->reg == ZPC)
890 losing++;
891 break;
892 }
355afbcd
KR		 893 break;
894
895 case '3':
a1c7c0f3
ILT		 896 if (opP->mode != CONTROL
897 || (opP->reg != TT0 && opP->reg != TT1))
355afbcd
KR		 898 losing++;
899 break;
900
901 case 'A':
902 if (opP->mode != AREG)
903 losing++;
904 break;
a1c7c0f3 905
355afbcd
KR		 906 case 'a':
907 if (opP->mode != AINDR)
a1c7c0f3 908 ++losing;
355afbcd 909 break;
a1c7c0f3 910
355afbcd 911 case 'B': /* FOO */
a1c7c0f3
ILT		 912 if (opP->mode != ABSL
913 || (flag_long_jumps
914 && strncmp (instring, "jbsr", 4) == 0))
355afbcd
KR		 915 losing++;
916 break;
917
918 case 'C':
a1c7c0f3 919 if (opP->mode != CONTROL || opP->reg != CCR)
355afbcd
KR		 920 losing++;
921 break;
922
a1c7c0f3
ILT		 923 case 'd':
924 if (opP->mode != DISP
925 || opP->reg < ADDR0
926 || opP->reg > ADDR7)
355afbcd
KR		 927 losing++;
928 break;
929
930 case 'D':
931 if (opP->mode != DREG)
932 losing++;
933 break;
934
935 case 'F':
a1c7c0f3 936 if (opP->mode != FPREG)
355afbcd
KR		 937 losing++;
938 break;
939
940 case 'I':
a1c7c0f3
ILT		 941 if (opP->mode != CONTROL
942 || opP->reg < COPNUM
943 || opP->reg >= COPNUM + 7)
355afbcd
KR		 944 losing++;
945 break;
946
947 case 'J':
a1c7c0f3 948 if (opP->mode != CONTROL
355afbcd 949 || opP->reg < USP
82489ea0
KR		 950 || opP->reg > last_movec_reg)
951 losing++;
952 else
355afbcd 953 {
a1c7c0f3 954 const enum m68k_register *rp;
82489ea0
KR		 955 for (rp = control_regs; *rp; rp++)
956 if (*rp == opP->reg)
957 break;
958 if (*rp == 0)
959 losing++;
960 }
355afbcd
KR		 961 break;
962
963 case 'k':
964 if (opP->mode != IMMED)
965 losing++;
966 break;
8be74775 967
355afbcd
KR		 968 case 'l':
969 case 'L':
a1c7c0f3
ILT		 970 if (opP->mode == DREG
971 || opP->mode == AREG
972 || opP->mode == FPREG)
355afbcd
KR		 973 {
974 if (s[1] == '8')
975 losing++;
976 else
977 {
a1c7c0f3
ILT		 978 switch (opP->mode)
979 {
980 case DREG:
981 opP->mask = 1 << (opP->reg - DATA0);
982 break;
983 case AREG:
984 opP->mask = 1 << (opP->reg - ADDR0 + 8);
985 break;
986 case FPREG:
987 opP->mask = 1 << (opP->reg - FP0 + 16);
988 break;
989 default:
990 abort ();
991 }
355afbcd 992 opP->mode = REGLST;
355afbcd
KR		 993 }
994 }
a1c7c0f3 995 else if (opP->mode == CONTROL)
355afbcd 996 {
a1c7c0f3
ILT		 997 if (s[1] != '8')
998 losing++;
999 else
1000 {
1001 switch (opP->reg)
1002 {
1003 case FPI:
1004 opP->mask = 1 << 24;
1005 break;
1006 case FPS:
1007 opP->mask = 1 << 25;
1008 break;
1009 case FPC:
1010 opP->mask = 1 << 26;
1011 break;
1012 default:
1013 losing++;
1014 break;
1015 }
1016 opP->mode = REGLST;
1017 }
355afbcd 1018 }
a1c7c0f3 1019 else if (opP->mode != REGLST)
355afbcd 1020 losing++;
a1c7c0f3
ILT		 1021 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1022 losing++;
1023 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
355afbcd
KR		 1024 losing++;
1025 break;
1026
1027 case 'M':
1028 if (opP->mode != IMMED)
1029 losing++;
a1c7c0f3
ILT		 1030 else if (! expr8 (&opP->disp))
1031 losing++;
355afbcd 1032 break;
8be74775 1033
355afbcd
KR		 1034 case 'O':
1035 if (opP->mode != DREG && opP->mode != IMMED)
1036 losing++;
1037 break;
6d27d3a2 1038
355afbcd
KR		 1039 case 'Q':
1040 if (opP->mode != IMMED)
1041 losing++;
a1c7c0f3
ILT		 1042 else if (! expr8 (&opP->disp)
1043 || opP->disp.exp.X_add_number < 1
1044 || opP->disp.exp.X_add_number > 8)
1045 losing++;
355afbcd 1046 break;
8be74775 1047
355afbcd
KR		 1048 case 'R':
1049 if (opP->mode != DREG && opP->mode != AREG)
1050 losing++;
1051 break;
8be74775 1052
355afbcd 1053 case 'r':
a1c7c0f3
ILT		 1054 if (opP->mode != AINDR
1055 && (opP->mode != BASE
1056 || (opP->reg != 0
1057 && opP->reg != ZADDR0)
1058 || opP->disp.exp.X_op != O_absent
1059 || ((opP->index.reg < DATA0
1060 || opP->index.reg > DATA7)
1061 && (opP->index.reg < ADDR0
1062 || opP->index.reg > ADDR7))
1063 || opP->index.size != SIZE_UNSPEC
1064 || opP->index.scale != 1))
355afbcd
KR		 1065 losing++;
1066 break;
c50140c8 1067
355afbcd 1068 case 's':
a1c7c0f3
ILT		 1069 if (opP->mode != CONTROL
1070 || ! (opP->reg == FPI
1071 || opP->reg == FPS
1072 || opP->reg == FPC))
355afbcd
KR		 1073 losing++;
1074 break;
8be74775 1075
355afbcd 1076 case 'S':
a1c7c0f3 1077 if (opP->mode != CONTROL || opP->reg != SR)
355afbcd
KR		 1078 losing++;
1079 break;
8be74775 1080
355afbcd
KR		 1081 case 't':
1082 if (opP->mode != IMMED)
1083 losing++;
a1c7c0f3
ILT		 1084 else if (! expr8 (&opP->disp)
1085 || opP->disp.exp.X_add_number < 0
1086 || opP->disp.exp.X_add_number > 7)
1087 losing++;
355afbcd 1088 break;
4134a793 1089
355afbcd 1090 case 'U':
a1c7c0f3 1091 if (opP->mode != CONTROL || opP->reg != USP)
355afbcd
KR		 1092 losing++;
1093 break;
8be74775 1094
355afbcd 1095 /* JF these are out of order. We could put them
1404ef23
KR		 1096 in order if we were willing to put up with
1097 bunches of #ifdef m68851s in the code.
4134a793 1098
1404ef23
KR		 1099 Don't forget that you need these operands
1100 to use 68030 MMU instructions. */
f8701a3f 1101#ifndef NO_68851
355afbcd
KR		 1102 /* Memory addressing mode used by pflushr */
1103 case '|':
a1c7c0f3
ILT		 1104 if (opP->mode == CONTROL
1105 || opP->mode == FPREG
1106 || opP->mode == DREG
1107 || opP->mode == AREG
1108 || opP->mode == REGLST)
355afbcd
KR		 1109 losing++;
1110 break;
1111
1112 case 'f':
a1c7c0f3
ILT		 1113 if (opP->mode != CONTROL
1114 || (opP->reg != SFC && opP->reg != DFC))
355afbcd
KR		 1115 losing++;
1116 break;
1117
1118 case 'P':
a1c7c0f3
ILT		 1119 if (opP->mode != CONTROL
1120 || (opP->reg != TC
1121 && opP->reg != CAL
1122 && opP->reg != VAL
1123 && opP->reg != SCC
1124 && opP->reg != AC))
355afbcd
KR		 1125 losing++;
1126 break;
1127
1128 case 'V':
a1c7c0f3
ILT		 1129 if (opP->mode != CONTROL
1130 || opP->reg != VAL)
355afbcd
KR		 1131 losing++;
1132 break;
8be74775 1133
355afbcd 1134 case 'W':
a1c7c0f3
ILT		 1135 if (opP->mode != CONTROL
1136 || (opP->reg != DRP
1137 && opP->reg != SRP
355afbcd
KR		 1138 && opP->reg != CRP))
1139 losing++;
1140 break;
1141
1142 case 'X':
a1c7c0f3
ILT		 1143 if (opP->mode != CONTROL
1144 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1145 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
355afbcd
KR		 1146 losing++;
1147 break;
1148
1149 case 'Y':
a1c7c0f3 1150 if (opP->mode != CONTROL || opP->reg != PSR)
355afbcd
KR		 1151 losing++;
1152 break;
1153
1154 case 'Z':
a1c7c0f3 1155 if (opP->mode != CONTROL || opP->reg != PCSR)
355afbcd
KR		 1156 losing++;
1157 break;
f8701a3f 1158#endif
355afbcd 1159 case 'c':
a1c7c0f3
ILT		 1160 if (opP->mode != CONTROL
1161 || (opP->reg != NC
1162 && opP->reg != IC
1163 && opP->reg != DC
1164 && opP->reg != BC))
355afbcd
KR		 1165 {
1166 losing++;
1167 } /* not a cache specifier. */
1168 break;
1169
1170 case '_':
1171 if (opP->mode != ABSL)
a1c7c0f3 1172 ++losing;
355afbcd 1173 break;
8be74775 1174
355afbcd 1175 default:
a1c7c0f3 1176 abort ();
355afbcd 1177 } /* switch on type of operand */
6d27d3a2 1178
355afbcd
KR		 1179 if (losing)
1180 break;
1181 } /* for each operand */
1182 } /* if immediately wrong */
6d27d3a2 1183
355afbcd
KR		 1184 if (!losing)
1185 {
8be74775 1186 break;
355afbcd 1187 } /* got it. */
6d27d3a2 1188
355afbcd 1189 opcode = opcode->m_next;
6d27d3a2 1190
355afbcd 1191 if (!opcode)
8be74775 1192 {
355afbcd
KR		 1193 if (ok_arch
1194 && !(ok_arch & current_architecture))
8be74775 1195 {
355afbcd
KR		 1196 char buf[200], *cp;
1197 int len;
a1c7c0f3
ILT		 1198 strcpy (buf,
1199 "invalid instruction for this architecture; needs ");
355afbcd
KR		 1200 cp = buf + strlen (buf);
1201 switch (ok_arch)
1202 {
1203 case mfloat:
82489ea0 1204 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
355afbcd
KR		 1205 break;
1206 case mmmu:
1207 strcpy (cp, "mmu (68030 or 68851)");
1208 break;
1209 case m68020up:
1210 strcpy (cp, "68020 or higher");
1211 break;
1212 case m68000up:
1213 strcpy (cp, "68000 or higher");
1214 break;
1215 case m68010up:
1216 strcpy (cp, "68010 or higher");
1217 break;
1218 default:
8be74775 1219 {
355afbcd 1220 int got_one = 0, idx;
a1c7c0f3
ILT		 1221 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1222 idx++)
8be74775 1223 {
355afbcd 1224 if (archs[idx].arch & ok_arch)
8be74775 1225 {
355afbcd
KR		 1226 if (got_one)
1227 {
1228 strcpy (cp, " or ");
1229 cp += strlen (cp);
1230 }
1231 got_one = 1;
1232 strcpy (cp, archs[idx].name);
8be74775
KR		 1233 cp += strlen (cp);
1234 }
8be74775
KR		 1235 }
1236 }
355afbcd
KR		 1237 }
1238 len = cp - buf + 1;
1239 cp = malloc (len);
1240 strcpy (cp, buf);
1241 the_ins.error = cp;
8be74775 1242 }
355afbcd
KR		 1243 else
1244 the_ins.error = "operands mismatch";
1245 return;
1246 } /* Fell off the end */
6d27d3a2 1247
355afbcd
KR		 1248 losing = 0;
1249 }
6d27d3a2
KR		 1250
1251 /* now assemble it */
1252
355afbcd
KR		 1253 the_ins.args = opcode->m_operands;
1254 the_ins.numargs = opcode->m_opnum;
1255 the_ins.numo = opcode->m_codenum;
1256 the_ins.opcode[0] = getone (opcode);
1257 the_ins.opcode[1] = gettwo (opcode);
6d27d3a2 1258
355afbcd
KR		 1259 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1260 {
1261 /* This switch is a doozy.
6d27d3a2 1262 Watch the first step; its a big one! */
355afbcd
KR		 1263 switch (s[0])
1264 {
6d27d3a2 1265
355afbcd
KR		 1266 case '*':
1267 case '~':
1268 case '%':
1269 case ';':
1270 case '@':
1271 case '!':
1272 case '&':
1273 case '$':
1274 case '?':
1275 case '/':
1276 case '`':
1277#ifndef NO_68851
1278 case '|':
1279#endif
1280 switch (opP->mode)
1281 {
1282 case IMMED:
1283 tmpreg = 0x3c; /* 7.4 */
1284 if (strchr ("bwl", s[1]))
a1c7c0f3 1285 nextword = get_num (&opP->disp, 80);
355afbcd 1286 else
a1c7c0f3
ILT		 1287 nextword = get_num (&opP->disp, 0);
1288 if (isvar (&opP->disp))
1289 add_fix (s[1], &opP->disp, 0, 0);
355afbcd
KR		 1290 switch (s[1])
1291 {
1292 case 'b':
1293 if (!isbyte (nextword))
1294 opP->error = "operand out of range";
1295 addword (nextword);
1296 baseo = 0;
1297 break;
1298 case 'w':
1299 if (!isword (nextword))
1300 opP->error = "operand out of range";
1301 addword (nextword);
1302 baseo = 0;
1303 break;
1304 case 'l':
1305 addword (nextword >> 16);
1306 addword (nextword);
1307 baseo = 0;
1308 break;
1309
1310 case 'f':
1311 baseo = 2;
1312 outro = 8;
1313 break;
1314 case 'F':
1315 baseo = 4;
1316 outro = 11;
1317 break;
1318 case 'x':
1319 baseo = 6;
1320 outro = 15;
1321 break;
1322 case 'p':
1323 baseo = 6;
1324 outro = -1;
1325 break;
1326 default:
a1c7c0f3 1327 abort ();
355afbcd
KR		 1328 }
1329 if (!baseo)
1330 break;
6d27d3a2 1331
355afbcd 1332 /* We gotta put out some float */
a1c7c0f3 1333 if (op (&opP->disp) != O_big)
355afbcd 1334 {
bcb8dff8
KR		 1335 valueT val;
1336 int gencnt;
1337
1338 /* Can other cases happen here? */
a1c7c0f3 1339 if (op (&opP->disp) != O_constant)
bcb8dff8 1340 abort ();
82489ea0 1341
a1c7c0f3 1342 val = (valueT) offs (&opP->disp);
bcb8dff8
KR		 1343 gencnt = 0;
1344 do
1345 {
1346 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1347 val >>= LITTLENUM_NUMBER_OF_BITS;
1348 ++gencnt;
1349 }
1350 while (val != 0);
a1c7c0f3 1351 offs (&opP->disp) = gencnt;
355afbcd 1352 }
a1c7c0f3 1353 if (offs (&opP->disp) > 0)
355afbcd 1354 {
a1c7c0f3 1355 if (offs (&opP->disp) > baseo)
355afbcd 1356 {
a1c7c0f3
ILT		 1357 as_warn ("Bignum too big for %c format; truncated",
1358 s[1]);
1359 offs (&opP->disp) = baseo;
355afbcd 1360 }
a1c7c0f3 1361 baseo -= offs (&opP->disp);
355afbcd
KR		 1362 while (baseo--)
1363 addword (0);
a1c7c0f3
ILT		 1364 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1365 offs (&opP->disp)--;
1366 --wordp)
bcb8dff8 1367 addword (*wordp);
355afbcd
KR		 1368 break;
1369 }
1370 gen_to_words (words, baseo, (long) outro);
1371 for (wordp = words; baseo--; wordp++)
1372 addword (*wordp);
1373 break;
1374 case DREG:
1375 tmpreg = opP->reg - DATA; /* 0.dreg */
1376 break;
1377 case AREG:
1378 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1379 break;
1380 case AINDR:
1381 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1382 break;
1383 case ADEC:
1384 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1385 break;
1386 case AINC:
1387 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1388 break;
a1c7c0f3 1389 case DISP:
6d27d3a2 1390
a1c7c0f3 1391 nextword = get_num (&opP->disp, 80);
355afbcd 1392 /* Force into index mode. Hope this works */
6d27d3a2 1393
1404ef23
KR		 1394 /* We do the first bit for 32-bit displacements, and the
1395 second bit for 16 bit ones. It is possible that we
1396 should make the default be WORD instead of LONG, but
1397 I think that'd break GCC, so we put up with a little
1398 inefficiency for the sake of working output. */
6d27d3a2 1399
355afbcd 1400 if (!issword (nextword)
a1c7c0f3
ILT		 1401 || (isvar (&opP->disp)
1402 && ((opP->disp.size == SIZE_UNSPEC
b79de3a1
KR		 1403 && flag_short_refs == 0
1404 && cpu_of_arch (current_architecture) >= m68020)
a1c7c0f3 1405 || opP->disp.size == SIZE_LONG)))
355afbcd 1406 {
355afbcd
KR		 1407 if (opP->reg == PC)
1408 tmpreg = 0x3B; /* 7.3 */
1409 else
1410 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
a1c7c0f3 1411 if (isvar (&opP->disp))
355afbcd
KR		 1412 {
1413 if (opP->reg == PC)
1414 {
04ef74bb 1415#if 0
b80d39a0 1416 addword (0x0170);
a1c7c0f3 1417 add_fix ('l', &opP->disp, 1, 2);
b80d39a0 1418 addword (0), addword (0);
04ef74bb 1419#else
a1c7c0f3
ILT		 1420 add_frag (adds (&opP->disp),
1421 offs (&opP->disp),
04ef74bb
KR		 1422 TAB (PCLEA, SZ_UNDEF));
1423#endif
355afbcd
KR		 1424 break;
1425 }
1426 else
1427 {
1428 addword (0x0170);
a1c7c0f3 1429 add_fix ('l', &opP->disp, 0, 0);
355afbcd
KR		 1430 }
1431 }
1432 else
1433 addword (0x0170);
1434 addword (nextword >> 16);
1435 }
1436 else
1437 {
1438 if (opP->reg == PC)
1439 tmpreg = 0x3A; /* 7.2 */
1440 else
1441 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1442
a1c7c0f3 1443 if (isvar (&opP->disp))
355afbcd
KR		 1444 {
1445 if (opP->reg == PC)
1446 {
a1c7c0f3 1447 add_fix ('w', &opP->disp, 1, 0);
355afbcd
KR		 1448 }
1449 else
a1c7c0f3 1450 add_fix ('w', &opP->disp, 0, 0);
355afbcd
KR		 1451 }
1452 }
1453 addword (nextword);
6d27d3a2 1454 break;
6d27d3a2 1455
a1c7c0f3
ILT		 1456 case POST:
1457 case PRE:
1458 case BASE:
355afbcd 1459 nextword = 0;
a1c7c0f3
ILT		 1460 baseo = get_num (&opP->disp, 80);
1461 if (opP->mode == POST || opP->mode == PRE)
1462 outro = get_num (&opP->odisp, 80);
49864cfa
KR		 1463 /* Figure out the `addressing mode'.
1464 Also turn on the BASE_DISABLE bit, if needed. */
355afbcd
KR		 1465 if (opP->reg == PC || opP->reg == ZPC)
1466 {
a1c7c0f3 1467 tmpreg = 0x3b; /* 7.3 */
355afbcd
KR		 1468 if (opP->reg == ZPC)
1469 nextword |= 0x80;
1470 }
a1c7c0f3
ILT		 1471 else if (opP->reg == 0)
1472 {
1473 nextword |= 0x80;
1474 tmpreg = 0x30; /* 6.garbage */
1475 }
1476 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
355afbcd
KR		 1477 {
1478 nextword |= 0x80;
a1c7c0f3 1479 tmpreg = 0x30 + opP->reg - ZADDR0;
355afbcd
KR		 1480 }
1481 else
1482 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1483
a1c7c0f3
ILT		 1484 siz1 = opP->disp.size;
1485 if (opP->mode == POST || opP->mode == PRE)
1486 siz2 = opP->odisp.size;
1487 else
1488 siz2 = SIZE_UNSPEC;
355afbcd
KR		 1489
1490 /* Index register stuff */
a1c7c0f3
ILT		 1491 if (opP->index.reg != 0
1492 && opP->index.reg >= DATA
1493 && opP->index.reg <= ADDR7)
355afbcd 1494 {
a1c7c0f3 1495 nextword |= (opP->index.reg - DATA) << 12;
355afbcd 1496
a1c7c0f3
ILT		 1497 if (opP->index.size == SIZE_UNSPEC
1498 || opP->index.size == SIZE_LONG)
355afbcd 1499 nextword |= 0x800;
a1c7c0f3
ILT		 1500
1501 if (cpu_of_arch (current_architecture) < m68020)
1502 {
1503 if (opP->index.scale != 1)
1504 {
1505 opP->error =
1506 "scale factor invalid on this architecture; needs 68020 or higher";
1507 }
1508 }
1509
1510 switch (opP->index.scale)
355afbcd
KR		 1511 {
1512 case 1:
1513 break;
1514 case 2:
1515 nextword |= 0x200;
1516 break;
1517 case 4:
1518 nextword |= 0x400;
1519 break;
1520 case 8:
1521 nextword |= 0x600;
1522 break;
1523 default:
a1c7c0f3 1524 abort ();
355afbcd
KR		 1525 }
1526 /* IF its simple,
49864cfa 1527 GET US OUT OF HERE! */
6d27d3a2 1528
04ef74bb
KR		 1529 /* Must be INDEX, with an index register. Address
1530 register cannot be ZERO-PC, and either :b was
1531 forced, or we know it will fit. For a 68000 or
1532 68010, force this mode anyways, because the
1533 larger modes aren't supported. */
a1c7c0f3
ILT		 1534 if (opP->mode == BASE
1535 && ((opP->reg >= ADDR0
1536 && opP->reg <= ADDR7)
1537 || opP->reg == PC))
355afbcd 1538 {
a1c7c0f3
ILT		 1539 if (siz1 == SIZE_BYTE
1540 || cpu_of_arch (current_architecture) < m68020
1541 || (siz1 == SIZE_UNSPEC
1542 && ! isvar (&opP->disp)
1543 && issbyte (baseo)))
1544 {
5f8cb05e
ILT		 1545 nextword += baseo & 0xff;
1546 addword (nextword);
a1c7c0f3 1547 if (isvar (&opP->disp))
04ef74bb 1548 {
a1c7c0f3
ILT		 1549 /* Do a byte relocation. If it doesn't
1550 fit (possible on m68000) let the
1551 fixup processing complain later. */
5f8cb05e 1552 if (opP->reg == PC)
a1c7c0f3 1553 add_fix ('B', &opP->disp, 1, 1);
5f8cb05e 1554 else
a1c7c0f3 1555 add_fix ('B', &opP->disp, 0, 0);
04ef74bb 1556 }
a1c7c0f3
ILT		 1557 else if (siz1 != SIZE_BYTE)
1558 {
1559 if (siz1 != SIZE_UNSPEC)
1560 as_warn ("Forcing byte displacement");
1561 if (! issbyte (baseo))
1562 opP->error = "byte displacement out of range";
1563 }
1564
1565 break;
1566 }
1567 else if (siz1 == SIZE_UNSPEC
1568 && opP->reg == PC
1569 && isvar (&opP->disp)
1570 && subs (&opP->disp) == NULL)
1571 {
5f8cb05e
ILT		 1572 nextword += baseo & 0xff;
1573 addword (nextword);
a1c7c0f3 1574 add_frag (adds (&opP->disp), offs (&opP->disp),
5f8cb05e 1575 TAB (PCINDEX, SZ_UNDEF));
a1c7c0f3
ILT		 1576
1577 break;
5f8cb05e 1578 }
355afbcd
KR		 1579 }
1580 }
1581 else
a1c7c0f3
ILT		 1582 {
1583 nextword |= 0x40; /* No index reg */
1584 if (opP->index.reg >= ZDATA0
1585 && opP->index.reg <= ZDATA7)
1586 nextword |= (opP->index.reg - ZDATA0) << 12;
1587 else if (opP->index.reg >= ZADDR0
1588 || opP->index.reg <= ZADDR7)
1589 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
1590 }
6d27d3a2 1591
49864cfa 1592 /* It isn't simple. */
a1c7c0f3
ILT		 1593
1594 if (cpu_of_arch (current_architecture) < m68020)
1595 opP->error =
1596 "invalid operand mode for this architecture; needs 68020 or higher";
1597
355afbcd 1598 nextword |= 0x100;
49864cfa
KR		 1599 /* If the guy specified a width, we assume that it is
1600 wide enough. Maybe it isn't. If so, we lose. */
355afbcd
KR		 1601 switch (siz1)
1602 {
a1c7c0f3
ILT		 1603 case SIZE_UNSPEC:
1604 if (isvar (&opP->disp) || !issword (baseo))
355afbcd 1605 {
a1c7c0f3 1606 siz1 = SIZE_LONG;
355afbcd
KR		 1607 nextword |= 0x30;
1608 }
1609 else if (baseo == 0)
1610 nextword |= 0x10;
1611 else
1612 {
1613 nextword |= 0x20;
a1c7c0f3 1614 siz1 = SIZE_WORD;
355afbcd
KR		 1615 }
1616 break;
a1c7c0f3
ILT		 1617 case SIZE_BYTE:
1618 as_warn (":b not permitted; defaulting to :w");
1619 /* Fall through. */
1620 case SIZE_WORD:
355afbcd
KR		 1621 nextword |= 0x20;
1622 break;
a1c7c0f3 1623 case SIZE_LONG:
355afbcd
KR		 1624 nextword |= 0x30;
1625 break;
1626 }
6d27d3a2 1627
355afbcd 1628 /* Figure out innner displacement stuff */
a1c7c0f3 1629 if (opP->mode == POST || opP->mode == PRE)
355afbcd
KR		 1630 {
1631 switch (siz2)
1632 {
a1c7c0f3
ILT		 1633 case SIZE_UNSPEC:
1634 if (isvar (&opP->odisp) || !issword (outro))
355afbcd 1635 {
a1c7c0f3 1636 siz2 = SIZE_LONG;
355afbcd
KR		 1637 nextword |= 0x3;
1638 }
1639 else if (outro == 0)
1640 nextword |= 0x1;
1641 else
1642 {
1643 nextword |= 0x2;
a1c7c0f3 1644 siz2 = SIZE_WORD;
355afbcd
KR		 1645 }
1646 break;
1647 case 1:
a1c7c0f3
ILT		 1648 as_warn (":b not permitted; defaulting to :w");
1649 /* Fall through. */
355afbcd
KR		 1650 case 2:
1651 nextword |= 0x2;
1652 break;
1653 case 3:
1654 nextword |= 0x3;
1655 break;
1656 }
a1c7c0f3 1657 if (opP->mode == POST)
355afbcd 1658 nextword |= 0x04;
355afbcd
KR		 1659 }
1660 addword (nextword);
1661
a1c7c0f3 1662 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
355afbcd
KR		 1663 {
1664 if (opP->reg == PC || opP->reg == ZPC)
a1c7c0f3 1665 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
355afbcd 1666 else
a1c7c0f3 1667 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
355afbcd 1668 }
a1c7c0f3 1669 if (siz1 == SIZE_LONG)
355afbcd 1670 addword (baseo >> 16);
a1c7c0f3 1671 if (siz1 != SIZE_UNSPEC)
355afbcd
KR		 1672 addword (baseo);
1673
a1c7c0f3
ILT		 1674 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
1675 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
1676 if (siz2 == SIZE_LONG)
355afbcd 1677 addword (outro >> 16);
a1c7c0f3 1678 if (siz2 != SIZE_UNSPEC)
355afbcd 1679 addword (outro);
6d27d3a2 1680
355afbcd 1681 break;
6d27d3a2 1682
355afbcd 1683 case ABSL:
a1c7c0f3
ILT		 1684 nextword = get_num (&opP->disp, 80);
1685 switch (opP->disp.size)
355afbcd
KR		 1686 {
1687 default:
a1c7c0f3
ILT		 1688 abort ();
1689 case SIZE_UNSPEC:
1690 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
355afbcd
KR		 1691 {
1692 tmpreg = 0x38; /* 7.0 */
1693 addword (nextword);
1694 break;
1695 }
bcb8dff8
KR		 1696 /* Don't generate pc relative code on 68010 and
1697 68000. */
a1c7c0f3
ILT		 1698 if (isvar (&opP->disp)
1699 && !subs (&opP->disp)
1700 && adds (&opP->disp)
1701 && (S_GET_SEGMENT (adds (&opP->disp)) == text_section)
49864cfa 1702 && now_seg == text_section
355afbcd 1703 && cpu_of_arch (current_architecture) >= m68020
9ad5755f 1704 && !flag_long_jumps
355afbcd
KR		 1705 && !strchr ("~%&$?", s[0]))
1706 {
1707 tmpreg = 0x3A; /* 7.2 */
a1c7c0f3
ILT		 1708 add_frag (adds (&opP->disp),
1709 offs (&opP->disp),
355afbcd
KR		 1710 TAB (PCREL, SZ_UNDEF));
1711 break;
1712 }
04ef74bb 1713 /* Fall through into long */
a1c7c0f3
ILT		 1714 case SIZE_LONG:
1715 if (isvar (&opP->disp))
1716 add_fix ('l', &opP->disp, 0, 0);
355afbcd
KR		 1717
1718 tmpreg = 0x39;/* 7.1 mode */
1719 addword (nextword >> 16);
1720 addword (nextword);
1721 break;
1722
a1c7c0f3
ILT		 1723 case SIZE_WORD: /* Word */
1724 if (isvar (&opP->disp))
1725 add_fix ('w', &opP->disp, 0, 0);
355afbcd
KR		 1726
1727 tmpreg = 0x38;/* 7.0 mode */
1728 addword (nextword);
1729 break;
1730 }
1731 break;
a1c7c0f3
ILT		 1732 case CONTROL:
1733 case FPREG:
355afbcd
KR		 1734 default:
1735 as_bad ("unknown/incorrect operand");
1736 /* abort(); */
1737 }
1738 install_gen_operand (s[1], tmpreg);
6d27d3a2 1739 break;
6d27d3a2 1740
355afbcd
KR		 1741 case '#':
1742 case '^':
1743 switch (s[1])
1744 { /* JF: I hate floating point! */
1745 case 'j':
1746 tmpreg = 70;
1747 break;
1748 case '8':
1749 tmpreg = 20;
1750 break;
1751 case 'C':
1752 tmpreg = 50;
1753 break;
1754 case '3':
1755 default:
1756 tmpreg = 80;
1757 break;
1758 }
a1c7c0f3
ILT		 1759 tmpreg = get_num (&opP->disp, tmpreg);
1760 if (isvar (&opP->disp))
1761 add_fix (s[1], &opP->disp, 0, 0);
355afbcd
KR		 1762 switch (s[1])
1763 {
1764 case 'b': /* Danger: These do no check for
6d27d3a2
KR		 1765 certain types of overflow.
1766 user beware! */
355afbcd
KR		 1767 if (!isbyte (tmpreg))
1768 opP->error = "out of range";
bcb8dff8 1769 insop (tmpreg, opcode);
a1c7c0f3 1770 if (isvar (&opP->disp))
355afbcd
KR		 1771 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1772 break;
1773 case 'w':
1774 if (!isword (tmpreg))
1775 opP->error = "out of range";
bcb8dff8 1776 insop (tmpreg, opcode);
a1c7c0f3 1777 if (isvar (&opP->disp))
355afbcd
KR		 1778 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1779 break;
1780 case 'l':
bcb8dff8
KR		 1781 /* Because of the way insop works, we put these two out
1782 backwards. */
1783 insop (tmpreg, opcode);
1784 insop (tmpreg >> 16, opcode);
a1c7c0f3 1785 if (isvar (&opP->disp))
355afbcd
KR		 1786 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1787 break;
1788 case '3':
1789 tmpreg &= 0xFF;
1790 case '8':
1791 case 'C':
1792 install_operand (s[1], tmpreg);
1793 break;
1794 default:
a1c7c0f3 1795 abort ();
355afbcd
KR		 1796 }
1797 break;
6d27d3a2 1798
355afbcd
KR		 1799 case '+':
1800 case '-':
1801 case 'A':
1802 case 'a':
1803 install_operand (s[1], opP->reg - ADDR);
1804 break;
6d27d3a2 1805
355afbcd 1806 case 'B':
a1c7c0f3 1807 tmpreg = get_num (&opP->disp, 80);
355afbcd
KR		 1808 switch (s[1])
1809 {
1810 case 'B':
a1c7c0f3 1811 add_fix ('B', &opP->disp, 1, -1);
355afbcd
KR		 1812 break;
1813 case 'W':
a1c7c0f3 1814 add_fix ('w', &opP->disp, 1, 0);
355afbcd
KR		 1815 addword (0);
1816 break;
1817 case 'L':
1818 long_branch:
a1c7c0f3 1819 if (cpu_of_arch (current_architecture) < m68020)
355afbcd
KR		 1820 as_warn ("Can't use long branches on 68000/68010");
1821 the_ins.opcode[the_ins.numo - 1] |= 0xff;
a1c7c0f3 1822 add_fix ('l', &opP->disp, 1, 0);
355afbcd
KR		 1823 addword (0);
1824 addword (0);
1825 break;
1826 case 'g':
a1c7c0f3 1827 if (subs (&opP->disp)) /* We can't relax it */
355afbcd 1828 goto long_branch;
6d27d3a2 1829
a1c7c0f3
ILT		 1830 /* This could either be a symbol, or an absolute
1831 address. No matter, the frag hacking will finger it
1832 out. Not quite: it can't switch from BRANCH to
1833 BCC68000 for the case where opnd is absolute (it
1834 needs to use the 68000 hack since no conditional abs
1835 jumps). */
b79de3a1 1836 if (((cpu_of_arch (current_architecture) < m68020)
a1c7c0f3 1837 || (0 == adds (&opP->disp)))
355afbcd
KR		 1838 && (the_ins.opcode[0] >= 0x6200)
1839 && (the_ins.opcode[0] <= 0x6f00))
a1c7c0f3
ILT		 1840 add_frag (adds (&opP->disp), offs (&opP->disp),
1841 TAB (BCC68000, SZ_UNDEF));
355afbcd 1842 else
a1c7c0f3
ILT		 1843 add_frag (adds (&opP->disp), offs (&opP->disp),
1844 TAB (ABRANCH, SZ_UNDEF));
355afbcd
KR		 1845 break;
1846 case 'w':
a1c7c0f3 1847 if (isvar (&opP->disp))
355afbcd 1848 {
49864cfa 1849#if 1
355afbcd
KR		 1850 /* check for DBcc instruction */
1851 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
1852 {
1853 /* size varies if patch */
1854 /* needed for long form */
a1c7c0f3 1855 add_frag (adds (&opP->disp), offs (&opP->disp),
b79de3a1 1856 TAB (DBCC, SZ_UNDEF));
355afbcd
KR		 1857 break;
1858 }
49864cfa 1859#endif
a1c7c0f3 1860 add_fix ('w', &opP->disp, 1, 0);
355afbcd
KR		 1861 }
1862 addword (0);
1863 break;
1864 case 'C': /* Fixed size LONG coproc branches */
a1c7c0f3 1865 add_fix ('l', &opP->disp, 1, 0);
355afbcd
KR		 1866 addword (0);
1867 addword (0);
1868 break;
1869 case 'c': /* Var size Coprocesssor branches */
a1c7c0f3 1870 if (subs (&opP->disp))
355afbcd 1871 {
a1c7c0f3 1872 add_fix ('l', &opP->disp, 1, 0);
355afbcd
KR		 1873 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
1874 }
a1c7c0f3
ILT		 1875 else if (adds (&opP->disp))
1876 add_frag (adds (&opP->disp), offs (&opP->disp),
1877 TAB (FBRANCH, SZ_UNDEF));
355afbcd
KR		 1878 else
1879 {
a1c7c0f3
ILT		 1880 /* add_frag((symbolS *) 0, offs(&opP->disp),
1881 TAB(FBRANCH,SHORT)); */
355afbcd 1882 the_ins.opcode[the_ins.numo - 1] |= 0x40;
a1c7c0f3 1883 add_fix ('l', &opP->disp, 1, 0);
5f8cb05e 1884 addword (0);
355afbcd 1885 addword (0);
355afbcd
KR		 1886 }
1887 break;
1888 default:
a1c7c0f3 1889 abort ();
355afbcd
KR		 1890 }
1891 break;
6d27d3a2 1892
355afbcd
KR		 1893 case 'C': /* Ignore it */
1894 break;
6d27d3a2 1895
355afbcd 1896 case 'd': /* JF this is a kludge */
a1c7c0f3
ILT		 1897 install_operand ('s', opP->reg - ADDR);
1898 tmpreg = get_num (&opP->disp, 80);
355afbcd
KR		 1899 if (!issword (tmpreg))
1900 {
1901 as_warn ("Expression out of range, using 0");
1902 tmpreg = 0;
1903 }
1904 addword (tmpreg);
1905 break;
6d27d3a2 1906
355afbcd
KR		 1907 case 'D':
1908 install_operand (s[1], opP->reg - DATA);
1909 break;
6d27d3a2 1910
355afbcd 1911 case 'F':
a1c7c0f3 1912 install_operand (s[1], opP->reg - FP0);
355afbcd 1913 break;
6d27d3a2 1914
355afbcd
KR		 1915 case 'I':
1916 tmpreg = 1 + opP->reg - COPNUM;
1917 if (tmpreg == 8)
1918 tmpreg = 0;
1919 install_operand (s[1], tmpreg);
1920 break;
6d27d3a2 1921
355afbcd
KR		 1922 case 'J': /* JF foo */
1923 switch (opP->reg)
1924 {
1925 case SFC:
1926 tmpreg = 0x000;
1927 break;
1928 case DFC:
1929 tmpreg = 0x001;
1930 break;
1931 case CACR:
1932 tmpreg = 0x002;
1933 break;
1934 case TC:
1935 tmpreg = 0x003;
1936 break;
1937 case ITT0:
1938 tmpreg = 0x004;
1939 break;
1940 case ITT1:
1941 tmpreg = 0x005;
1942 break;
1943 case DTT0:
1944 tmpreg = 0x006;
1945 break;
1946 case DTT1:
1947 tmpreg = 0x007;
1948 break;
9ad5755f
KR		 1949 case BUSCR:
1950 tmpreg = 0x008;
1951 break;
6d27d3a2 1952
355afbcd
KR		 1953 case USP:
1954 tmpreg = 0x800;
1955 break;
1956 case VBR:
1957 tmpreg = 0x801;
1958 break;
1959 case CAAR:
1960 tmpreg = 0x802;
1961 break;
1962 case MSP:
1963 tmpreg = 0x803;
1964 break;
1965 case ISP:
1966 tmpreg = 0x804;
1967 break;
1968 case MMUSR:
1969 tmpreg = 0x805;
1970 break;
1971 case URP:
1972 tmpreg = 0x806;
1973 break;
1974 case SRP:
1975 tmpreg = 0x807;
1976 break;
9ad5755f
KR		 1977 case PCR:
1978 tmpreg = 0x808;
1979 break;
355afbcd 1980 default:
a1c7c0f3 1981 abort ();
355afbcd
KR		 1982 }
1983 install_operand (s[1], tmpreg);
1984 break;
6d27d3a2 1985
355afbcd 1986 case 'k':
a1c7c0f3 1987 tmpreg = get_num (&opP->disp, 55);
355afbcd
KR		 1988 install_operand (s[1], tmpreg & 0x7f);
1989 break;
6d27d3a2 1990
355afbcd 1991 case 'l':
a1c7c0f3 1992 tmpreg = opP->mask;
355afbcd
KR		 1993 if (s[1] == 'w')
1994 {
1995 if (tmpreg & 0x7FF0000)
1996 as_bad ("Floating point register in register list");
bcb8dff8 1997 insop (reverse_16_bits (tmpreg), opcode);
355afbcd
KR		 1998 }
1999 else
2000 {
2001 if (tmpreg & 0x700FFFF)
2002 as_bad ("Wrong register in floating-point reglist");
2003 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2004 }
2005 break;
6d27d3a2 2006
355afbcd 2007 case 'L':
a1c7c0f3 2008 tmpreg = opP->mask;
355afbcd
KR		 2009 if (s[1] == 'w')
2010 {
2011 if (tmpreg & 0x7FF0000)
2012 as_bad ("Floating point register in register list");
bcb8dff8 2013 insop (tmpreg, opcode);
355afbcd
KR		 2014 }
2015 else if (s[1] == '8')
2016 {
2017 if (tmpreg & 0x0FFFFFF)
2018 as_bad ("incorrect register in reglist");
2019 install_operand (s[1], tmpreg >> 24);
2020 }
2021 else
2022 {
2023 if (tmpreg & 0x700FFFF)
2024 as_bad ("wrong register in floating-point reglist");
2025 else
2026 install_operand (s[1], tmpreg >> 16);
2027 }
2028 break;
6d27d3a2 2029
355afbcd 2030 case 'M':
a1c7c0f3 2031 install_operand (s[1], get_num (&opP->disp, 60));
355afbcd 2032 break;
6d27d3a2 2033
355afbcd 2034 case 'O':
a1c7c0f3
ILT		 2035 tmpreg = ((opP->mode == DREG)
2036 ? 0x20 + opP->reg - DATA
2037 : (get_num (&opP->disp, 40) & 0x1F));
355afbcd
KR		 2038 install_operand (s[1], tmpreg);
2039 break;
6d27d3a2 2040
355afbcd 2041 case 'Q':
a1c7c0f3 2042 tmpreg = get_num (&opP->disp, 10);
355afbcd
KR		 2043 if (tmpreg == 8)
2044 tmpreg = 0;
2045 install_operand (s[1], tmpreg);
2046 break;
2047
2048 case 'R':
a1c7c0f3
ILT		 2049 /* This depends on the fact that ADDR registers are eight
2050 more than their corresponding DATA regs, so the result
2051 will have the ADDR_REG bit set */
355afbcd
KR		 2052 install_operand (s[1], opP->reg - DATA);
2053 break;
6d27d3a2 2054
a1c7c0f3
ILT		 2055 case 'r':
2056 if (opP->mode == AINDR)
2057 install_operand (s[1], opP->reg - DATA);
2058 else
2059 install_operand (s[1], opP->index.reg - DATA);
2060 break;
2061
355afbcd
KR		 2062 case 's':
2063 if (opP->reg == FPI)
2064 tmpreg = 0x1;
2065 else if (opP->reg == FPS)
2066 tmpreg = 0x2;
2067 else if (opP->reg == FPC)
2068 tmpreg = 0x4;
2069 else
a1c7c0f3 2070 abort ();
355afbcd
KR		 2071 install_operand (s[1], tmpreg);
2072 break;
6d27d3a2 2073
355afbcd
KR		 2074 case 'S': /* Ignore it */
2075 break;
6d27d3a2 2076
355afbcd 2077 case 'T':
a1c7c0f3 2078 install_operand (s[1], get_num (&opP->disp, 30));
355afbcd 2079 break;
6d27d3a2 2080
355afbcd
KR		 2081 case 'U': /* Ignore it */
2082 break;
6d27d3a2 2083
355afbcd
KR		 2084 case 'c':
2085 switch (opP->reg)
2086 {
2087 case NC:
2088 tmpreg = 0;
2089 break;
2090 case DC:
2091 tmpreg = 1;
2092 break;
2093 case IC:
2094 tmpreg = 2;
2095 break;
2096 case BC:
2097 tmpreg = 3;
2098 break;
2099 default:
2100 as_fatal ("failed sanity check");
2101 } /* switch on cache token */
2102 install_operand (s[1], tmpreg);
2103 break;
a39116f1 2104#ifndef NO_68851
355afbcd
KR		 2105 /* JF: These are out of order, I fear. */
2106 case 'f':
2107 switch (opP->reg)
2108 {
2109 case SFC:
2110 tmpreg = 0;
2111 break;
2112 case DFC:
2113 tmpreg = 1;
2114 break;
2115 default:
a1c7c0f3 2116 abort ();
355afbcd
KR		 2117 }
2118 install_operand (s[1], tmpreg);
2119 break;
6d27d3a2 2120
355afbcd
KR		 2121 case 'P':
2122 switch (opP->reg)
2123 {
2124 case TC:
2125 tmpreg = 0;
2126 break;
2127 case CAL:
2128 tmpreg = 4;
2129 break;
2130 case VAL:
2131 tmpreg = 5;
2132 break;
2133 case SCC:
2134 tmpreg = 6;
2135 break;
2136 case AC:
2137 tmpreg = 7;
2138 break;
2139 default:
a1c7c0f3 2140 abort ();
355afbcd
KR		 2141 }
2142 install_operand (s[1], tmpreg);
2143 break;
6d27d3a2 2144
355afbcd
KR		 2145 case 'V':
2146 if (opP->reg == VAL)
2147 break;
a1c7c0f3 2148 abort ();
6d27d3a2 2149
355afbcd
KR		 2150 case 'W':
2151 switch (opP->reg)
2152 {
355afbcd
KR		 2153 case DRP:
2154 tmpreg = 1;
2155 break;
2156 case SRP:
2157 tmpreg = 2;
2158 break;
2159 case CRP:
2160 tmpreg = 3;
2161 break;
2162 default:
a1c7c0f3 2163 abort ();
355afbcd
KR		 2164 }
2165 install_operand (s[1], tmpreg);
2166 break;
6d27d3a2 2167
355afbcd
KR		 2168 case 'X':
2169 switch (opP->reg)
2170 {
2171 case BAD:
2172 case BAD + 1:
2173 case BAD + 2:
2174 case BAD + 3:
2175 case BAD + 4:
2176 case BAD + 5:
2177 case BAD + 6:
2178 case BAD + 7:
2179 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2180 break;
6d27d3a2 2181
355afbcd
KR		 2182 case BAC:
2183 case BAC + 1:
2184 case BAC + 2:
2185 case BAC + 3:
2186 case BAC + 4:
2187 case BAC + 5:
2188 case BAC + 6:
2189 case BAC + 7:
2190 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2191 break;
6d27d3a2 2192
355afbcd 2193 default:
a1c7c0f3 2194 abort ();
355afbcd
KR		 2195 }
2196 install_operand (s[1], tmpreg);
2197 break;
2198 case 'Y':
2199 know (opP->reg == PSR);
2200 break;
2201 case 'Z':
2202 know (opP->reg == PCSR);
2203 break;
f8701a3f 2204#endif /* m68851 */
355afbcd
KR		 2205 case '3':
2206 switch (opP->reg)
2207 {
2208 case TT0:
2209 tmpreg = 2;
2210 break;
2211 case TT1:
2212 tmpreg = 3;
2213 break;
2214 default:
a1c7c0f3 2215 abort ();
355afbcd
KR		 2216 }
2217 install_operand (s[1], tmpreg);
2218 break;
2219 case 't':
a1c7c0f3 2220 tmpreg = get_num (&opP->disp, 20);
355afbcd 2221 install_operand (s[1], tmpreg);
4134a793 2222 break;
a1c7c0f3
ILT		 2223 case '_': /* used only for move16 absolute 32-bit address */
2224 tmpreg = get_num (&opP->disp, 80);
355afbcd
KR		 2225 addword (tmpreg >> 16);
2226 addword (tmpreg & 0xFFFF);
4134a793
KR		 2227 break;
2228 default:
a1c7c0f3 2229 abort ();
4134a793 2230 }
6d27d3a2 2231 }
3ad9ec6a 2232
6d27d3a2
KR		 2233 /* By the time whe get here (FINALLY) the_ins contains the complete
2234 instruction, ready to be emitted. . . */
a1c7c0f3 2235}
fecd2382 2236
355afbcd
KR		 2237static int
2238reverse_16_bits (in)
2239 int in;
fecd2382 2240{
355afbcd
KR		 2241 int out = 0;
2242 int n;
6d27d3a2 2243
355afbcd
KR		 2244 static int mask[16] =
2245 {
2246 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2247 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2248 };
2249 for (n = 0; n < 16; n++)
2250 {
2251 if (in & mask[n])
2252 out |= mask[15 - n];
2253 }
2254 return out;
2255} /* reverse_16_bits() */
fecd2382 2256
355afbcd
KR		 2257static int
2258reverse_8_bits (in)
2259 int in;
fecd2382 2260{
355afbcd
KR		 2261 int out = 0;
2262 int n;
6d27d3a2 2263
355afbcd
KR		 2264 static int mask[8] =
2265 {
2266 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2267 };
6d27d3a2 2268
355afbcd
KR		 2269 for (n = 0; n < 8; n++)
2270 {
2271 if (in & mask[n])
2272 out |= mask[7 - n];
2273 }
2274 return out;
2275} /* reverse_8_bits() */
fecd2382 2276
04ef74bb
KR		 2277/* Cause an extra frag to be generated here, inserting up to 10 bytes
2278 (that value is chosen in the frag_var call in md_assemble). TYPE
2279 is the subtype of the frag to be generated; its primary type is
2280 rs_machine_dependent.
2281
2282 The TYPE parameter is also used by md_convert_frag_1 and
2283 md_estimate_size_before_relax. The appropriate type of fixup will
2284 be emitted by md_convert_frag_1.
2285
2286 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
355afbcd
KR		 2287static void
2288install_operand (mode, val)
2289 int mode;
2290 int val;
fecd2382 2291{
355afbcd
KR		 2292 switch (mode)
2293 {
2294 case 's':
2295 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2296 break;
2297 case 'd':
2298 the_ins.opcode[0] |= val << 9;
2299 break;
2300 case '1':
2301 the_ins.opcode[1] |= val << 12;
2302 break;
2303 case '2':
2304 the_ins.opcode[1] |= val << 6;
2305 break;
2306 case '3':
2307 the_ins.opcode[1] |= val;
2308 break;
2309 case '4':
2310 the_ins.opcode[2] |= val << 12;
2311 break;
2312 case '5':
2313 the_ins.opcode[2] |= val << 6;
2314 break;
2315 case '6':
bcb8dff8
KR		 2316 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2317 three words long! */
355afbcd
KR		 2318 the_ins.numo++;
2319 the_ins.opcode[2] |= val;
2320 break;
2321 case '7':
2322 the_ins.opcode[1] |= val << 7;
2323 break;
2324 case '8':
2325 the_ins.opcode[1] |= val << 10;
2326 break;
f8701a3f 2327#ifndef NO_68851
355afbcd
KR		 2328 case '9':
2329 the_ins.opcode[1] |= val << 5;
2330 break;
f8701a3f 2331#endif
6d27d3a2 2332
355afbcd
KR		 2333 case 't':
2334 the_ins.opcode[1] |= (val << 10) | (val << 7);
2335 break;
2336 case 'D':
2337 the_ins.opcode[1] |= (val << 12) | val;
2338 break;
2339 case 'g':
2340 the_ins.opcode[0] |= val = 0xff;
2341 break;
2342 case 'i':
2343 the_ins.opcode[0] |= val << 9;
2344 break;
2345 case 'C':
2346 the_ins.opcode[1] |= val;
2347 break;
2348 case 'j':
2349 the_ins.opcode[1] |= val;
2350 the_ins.numo++; /* What a hack */
2351 break;
2352 case 'k':
2353 the_ins.opcode[1] |= val << 4;
2354 break;
2355 case 'b':
2356 case 'w':
2357 case 'l':
2358 break;
2359 case 'e':
2360 the_ins.opcode[0] |= (val << 6);
2361 break;
2362 case 'L':
2363 the_ins.opcode[1] = (val >> 16);
2364 the_ins.opcode[2] = val & 0xffff;
2365 break;
2366 case 'c':
2367 default:
2368 as_fatal ("failed sanity check.");
2369 }
2370} /* install_operand() */
fecd2382 2371
355afbcd
KR		 2372static void
2373install_gen_operand (mode, val)
2374 int mode;
2375 int val;
fecd2382 2376{
355afbcd
KR		 2377 switch (mode)
2378 {
2379 case 's':
2380 the_ins.opcode[0] |= val;
2381 break;
2382 case 'd':
2383 /* This is a kludge!!! */
2384 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2385 break;
2386 case 'b':
2387 case 'w':
2388 case 'l':
2389 case 'f':
2390 case 'F':
2391 case 'x':
2392 case 'p':
2393 the_ins.opcode[0] |= val;
2394 break;
2395 /* more stuff goes here */
2396 default:
2397 as_fatal ("failed sanity check.");
2398 }
2399} /* install_gen_operand() */
fecd2382 2400
7c15cbe8
RP		 2401/*
2402 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2403 * then deal with the bitfield hack.
2404 */
2405
355afbcd
KR		 2406static char *
2407crack_operand (str, opP)
2408 register char *str;
2409 register struct m68k_op *opP;
fecd2382 2410{
355afbcd
KR		 2411 register int parens;
2412 register int c;
2413 register char *beg_str;
6d27d3a2 2414
355afbcd
KR		 2415 if (!str)
2416 {
2417 return str;
2418 }
2419 beg_str = str;
2420 for (parens = 0; *str && (parens > 0 || notend (str)); str++)
2421 {
2422 if (*str == '(')
2423 parens++;
2424 else if (*str == ')')
2425 {
2426 if (!parens)
2427 { /* ERROR */
2428 opP->error = "Extra )";
2429 return str;
2430 }
2431 --parens;
f8701a3f 2432 }
355afbcd
KR		 2433 }
2434 if (!*str && parens)
2435 { /* ERROR */
2436 opP->error = "Missing )";
2437 return str;
2438 }
2439 c = *str;
2440 *str = '\0';
a1c7c0f3 2441 if (m68k_ip_op (beg_str, opP) != 0)
355afbcd
KR		 2442 {
2443 *str = c;
2444 return str;
2445 }
2446 *str = c;
2447 if (c == '}')
2448 c = *++str; /* JF bitfield hack */
2449 if (c)
2450 {
2451 c = *++str;
2452 if (!c)
2453 as_bad ("Missing operand");
2454 }
2455 return str;
fecd2382
RP		 2456}
2457
fecd2382 2458/* This is the guts of the machine-dependent assembler. STR points to a
7c15cbe8 2459 machine dependent instruction. This function is supposed to emit
fecd2382 2460 the frags/bytes it assembles to.
a39116f1 2461 */
a933d598
SC		 2462
2463void
355afbcd
KR		 2464insert_reg (regname, regnum)
2465 char *regname;
2466 int regnum;
a933d598
SC		 2467{
2468 char buf[100];
2469 int i;
355afbcd
KR		 2470
2471#ifdef REGISTER_PREFIX
82489ea0
KR		 2472 if (!flag_reg_prefix_optional)
2473 {
2474 buf[0] = REGISTER_PREFIX;
2475 strcpy (buf + 1, regname);
2476 regname = buf;
2477 }
355afbcd
KR		 2478#endif
2479
82489ea0
KR		 2480 symbol_table_insert (symbol_new (regname, reg_section, regnum,
2481 &zero_address_frag));
a933d598
SC		 2482
2483 for (i = 0; regname[i]; i++)
355afbcd 2484 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
a933d598 2485 buf[i] = '\0';
6d27d3a2 2486
82489ea0
KR		 2487 symbol_table_insert (symbol_new (buf, reg_section, regnum,
2488 &zero_address_frag));
a933d598
SC		 2489}
2490
49864cfa 2491struct init_entry
355afbcd 2492 {
bcb8dff8 2493 const char *name;
355afbcd 2494 int number;
49864cfa 2495 };
355afbcd 2496
bcb8dff8 2497static const struct init_entry init_table[] =
355afbcd 2498{
bcb8dff8
KR		 2499 { "d0", DATA0 },
2500 { "d1", DATA1 },
2501 { "d2", DATA2 },
2502 { "d3", DATA3 },
2503 { "d4", DATA4 },
2504 { "d5", DATA5 },
2505 { "d6", DATA6 },
2506 { "d7", DATA7 },
2507 { "a0", ADDR0 },
2508 { "a1", ADDR1 },
2509 { "a2", ADDR2 },
2510 { "a3", ADDR3 },
2511 { "a4", ADDR4 },
2512 { "a5", ADDR5 },
2513 { "a6", ADDR6 },
2514 { "fp", ADDR6 },
2515 { "a7", ADDR7 },
2516 { "sp", ADDR7 },
a1c7c0f3 2517 { "ssp", ADDR7 },
bcb8dff8
KR		 2518 { "fp0", FP0 },
2519 { "fp1", FP1 },
2520 { "fp2", FP2 },
2521 { "fp3", FP3 },
2522 { "fp4", FP4 },
2523 { "fp5", FP5 },
2524 { "fp6", FP6 },
2525 { "fp7", FP7 },
2526 { "fpi", FPI },
2527 { "fpiar", FPI },
2528 { "fpc", FPI },
2529 { "fps", FPS },
2530 { "fpsr", FPS },
2531 { "fpc", FPC },
2532 { "fpcr", FPC },
064ba683
ILT		 2533 { "control", FPC },
2534 { "status", FPS },
2535 { "iaddr", FPI },
bcb8dff8
KR		 2536
2537 { "cop0", COP0 },
2538 { "cop1", COP1 },
2539 { "cop2", COP2 },
2540 { "cop3", COP3 },
2541 { "cop4", COP4 },
2542 { "cop5", COP5 },
2543 { "cop6", COP6 },
2544 { "cop7", COP7 },
2545 { "pc", PC },
2546 { "zpc", ZPC },
2547 { "sr", SR },
2548
2549 { "ccr", CCR },
2550 { "cc", CCR },
2551
2552 { "usp", USP },
2553 { "isp", ISP },
2554 { "sfc", SFC },
064ba683 2555 { "sfcr", SFC },
bcb8dff8 2556 { "dfc", DFC },
064ba683 2557 { "dfcr", DFC },
bcb8dff8
KR		 2558 { "cacr", CACR },
2559 { "caar", CAAR },
2560
2561 { "vbr", VBR },
2562
2563 { "msp", MSP },
2564 { "itt0", ITT0 },
2565 { "itt1", ITT1 },
2566 { "dtt0", DTT0 },
2567 { "dtt1", DTT1 },
2568 { "mmusr", MMUSR },
2569 { "tc", TC },
2570 { "srp", SRP },
2571 { "urp", URP },
9ad5755f
KR		 2572 { "buscr", BUSCR },
2573 { "pcr", PCR },
bcb8dff8
KR		 2574
2575 { "ac", AC },
2576 { "bc", BC },
2577 { "cal", CAL },
2578 { "crp", CRP },
2579 { "drp", DRP },
2580 { "pcsr", PCSR },
2581 { "psr", PSR },
2582 { "scc", SCC },
2583 { "val", VAL },
2584 { "bad0", BAD0 },
2585 { "bad1", BAD1 },
2586 { "bad2", BAD2 },
2587 { "bad3", BAD3 },
2588 { "bad4", BAD4 },
2589 { "bad5", BAD5 },
2590 { "bad6", BAD6 },
2591 { "bad7", BAD7 },
2592 { "bac0", BAC0 },
2593 { "bac1", BAC1 },
2594 { "bac2", BAC2 },
2595 { "bac3", BAC3 },
2596 { "bac4", BAC4 },
2597 { "bac5", BAC5 },
2598 { "bac6", BAC6 },
2599 { "bac7", BAC7 },
2600
2601 { "ic", IC },
2602 { "dc", DC },
2603 { "nc", NC },
2604
2605 { "tt0", TT0 },
2606 { "tt1", TT1 },
4134a793 2607 /* 68ec030 versions of same */
bcb8dff8
KR		 2608 { "ac0", TT0 },
2609 { "ac1", TT1 },
4134a793 2610 /* 68ec030 access control unit, identical to 030 MMU status reg */
bcb8dff8 2611 { "acusr", PSR },
a933d598 2612
a1c7c0f3
ILT		 2613 /* Suppressed data and address registers. */
2614 { "zd0", ZDATA0 },
2615 { "zd1", ZDATA1 },
2616 { "zd2", ZDATA2 },
2617 { "zd3", ZDATA3 },
2618 { "zd4", ZDATA4 },
2619 { "zd5", ZDATA5 },
2620 { "zd6", ZDATA6 },
2621 { "zd7", ZDATA7 },
2622 { "za0", ZADDR0 },
2623 { "za1", ZADDR1 },
2624 { "za2", ZADDR2 },
2625 { "za3", ZADDR3 },
2626 { "za4", ZADDR4 },
2627 { "za5", ZADDR5 },
2628 { "za6", ZADDR6 },
2629 { "za7", ZADDR7 },
2630
bcb8dff8 2631 { 0, 0 }
a933d598
SC		 2632};
2633
a933d598 2634void
355afbcd 2635init_regtable ()
a933d598
SC		 2636{
2637 int i;
6d27d3a2 2638 for (i = 0; init_table[i].name; i++)
355afbcd 2639 insert_reg (init_table[i].name, init_table[i].number);
a933d598 2640}
6d27d3a2 2641
df3768fb 2642static int no_68851, no_68881;
a933d598 2643
dff60b7d
ILT		 2644#ifdef OBJ_AOUT
2645/* a.out machine type. Default to 68020. */
2646int m68k_aout_machtype = 2;
2647#endif
2648
fecd2382 2649void
355afbcd 2650md_assemble (str)
6d27d3a2 2651 char *str;
fecd2382 2652{
a1c7c0f3 2653 const char *er;
355afbcd
KR		 2654 short *fromP;
2655 char *toP = NULL;
2656 int m, n = 0;
2657 char *to_beg_P;
2658 int shorts_this_frag;
5f8cb05e 2659 fixS *fixP;
6d27d3a2 2660
e284846a 2661 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
355afbcd
KR		 2662 m68k_ip (str);
2663 er = the_ins.error;
2664 if (!er)
2665 {
a1c7c0f3 2666 for (n = 0; n < the_ins.numargs; n++)
355afbcd
KR		 2667 if (the_ins.operands[n].error)
2668 {
2669 er = the_ins.operands[n].error;
2670 break;
2671 }
2672 }
2673 if (er)
2674 {
2675 as_bad ("%s -- statement `%s' ignored", er, str);
2676 return;
2677 }
6d27d3a2 2678
355afbcd 2679 if (the_ins.nfrag == 0)
49864cfa
KR		 2680 {
2681 /* No frag hacking involved; just put it out */
355afbcd
KR		 2682 toP = frag_more (2 * the_ins.numo);
2683 fromP = &the_ins.opcode[0];
2684 for (m = the_ins.numo; m; --m)
2685 {
2686 md_number_to_chars (toP, (long) (*fromP), 2);
2687 toP += 2;
2688 fromP++;
f8701a3f 2689 }
355afbcd
KR		 2690 /* put out symbol-dependent info */
2691 for (m = 0; m < the_ins.nrel; m++)
2692 {
2693 switch (the_ins.reloc[m].wid)
2694 {
2695 case 'B':
2696 n = 1;
2697 break;
2698 case 'b':
2699 n = 1;
2700 break;
2701 case '3':
2702 n = 2;
2703 break;
2704 case 'w':
2705 n = 2;
2706 break;
2707 case 'l':
2708 n = 4;
2709 break;
2710 default:
49864cfa
KR		 2711 as_fatal ("Don't know how to figure width of %c in md_assemble()",
2712 the_ins.reloc[m].wid);
355afbcd 2713 }
6d27d3a2 2714
5f8cb05e
ILT		 2715 fixP = fix_new_exp (frag_now,
2716 ((toP - frag_now->fr_literal)
2717 - the_ins.numo * 2 + the_ins.reloc[m].n),
2718 n,
2719 &the_ins.reloc[m].exp,
2720 the_ins.reloc[m].pcrel,
2721 NO_RELOC);
2722 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
f8701a3f 2723 }
355afbcd
KR		 2724 return;
2725 }
2726
2727 /* There's some frag hacking */
2728 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
2729 {
2730 int wid;
2731
2732 if (n == 0)
2733 wid = 2 * the_ins.fragb[n].fragoff;
2734 else
2735 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2736 toP = frag_more (wid);
2737 to_beg_P = toP;
2738 shorts_this_frag = 0;
2739 for (m = wid / 2; m; --m)
2740 {
2741 md_number_to_chars (toP, (long) (*fromP), 2);
2742 toP += 2;
2743 fromP++;
2744 shorts_this_frag++;
2745 }
2746 for (m = 0; m < the_ins.nrel; m++)
2747 {
49864cfa 2748 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
355afbcd 2749 {
49864cfa 2750 the_ins.reloc[m].n -= 2 * shorts_this_frag;
355afbcd
KR		 2751 break;
2752 }
2753 wid = the_ins.reloc[m].wid;
2754 if (wid == 0)
2755 continue;
2756 the_ins.reloc[m].wid = 0;
2757 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
2758
5f8cb05e
ILT		 2759 fixP = fix_new_exp (frag_now,
2760 ((toP - frag_now->fr_literal)
2761 - the_ins.numo * 2 + the_ins.reloc[m].n),
2762 wid,
2763 &the_ins.reloc[m].exp,
2764 the_ins.reloc[m].pcrel,
2765 NO_RELOC);
2766 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
fecd2382 2767 }
49864cfa
KR		 2768 (void) frag_var (rs_machine_dependent, 10, 0,
2769 (relax_substateT) (the_ins.fragb[n].fragty),
2770 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
355afbcd
KR		 2771 }
2772 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2773 shorts_this_frag = 0;
2774 if (n)
2775 {
2776 toP = frag_more (n * sizeof (short));
2777 while (n--)
2778 {
2779 md_number_to_chars (toP, (long) (*fromP), 2);
2780 toP += 2;
2781 fromP++;
2782 shorts_this_frag++;
fecd2382 2783 }
355afbcd
KR		 2784 }
2785 for (m = 0; m < the_ins.nrel; m++)
2786 {
2787 int wid;
2788
2789 wid = the_ins.reloc[m].wid;
2790 if (wid == 0)
2791 continue;
2792 the_ins.reloc[m].wid = 0;
2793 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
2794
5f8cb05e
ILT		 2795 fixP = fix_new_exp (frag_now,
2796 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
2797 - shorts_this_frag * 2),
2798 wid,
2799 &the_ins.reloc[m].exp,
2800 the_ins.reloc[m].pcrel,
2801 NO_RELOC);
2802 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
355afbcd 2803 }
fecd2382
RP		 2804}
2805
fecd2382 2806void
355afbcd 2807md_begin ()
fecd2382 2808{
355afbcd 2809 /*
e284846a
KR		 2810 * md_begin -- set up hash tables with 68000 instructions.
2811 * similar to what the vax assembler does. ---phr
2812 */
355afbcd 2813 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
e284846a
KR		 2814 a copy of it at runtime, adding in the information we want but isn't
2815 there. I think it'd be better to have an awk script hack the table
2816 at compile time. Or even just xstr the table and use it as-is. But
2817 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
2818 names. */
6d27d3a2 2819
b79de3a1 2820 register const struct m68k_opcode *ins;
355afbcd 2821 register struct m68k_incant *hack, *slak;
bcb8dff8 2822 register const char *retval = 0; /* empty string, or error msg text */
355afbcd
KR		 2823 register unsigned int i;
2824 register char c;
2825
064ba683
ILT		 2826 if (flag_mri)
2827 flag_reg_prefix_optional = 1;
2828
82489ea0 2829 op_hash = hash_new ();
355afbcd
KR		 2830
2831 obstack_begin (&robyn, 4000);
a1c7c0f3 2832 for (i = 0; i < m68k_numopcodes; i++)
355afbcd
KR		 2833 {
2834 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
2835 do
2836 {
a1c7c0f3 2837 ins = &m68k_opcodes[i];
e284846a
KR		 2838 /* We *could* ignore insns that don't match our arch here
2839 but just leaving them out of the hash. */
355afbcd
KR		 2840 slak->m_operands = ins->args;
2841 slak->m_opnum = strlen (slak->m_operands) / 2;
2842 slak->m_arch = ins->arch;
2843 slak->m_opcode = ins->opcode;
2844 /* This is kludgey */
2845 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
a1c7c0f3
ILT		 2846 if (i + 1 != m68k_numopcodes
2847 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
355afbcd
KR		 2848 {
2849 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
e284846a 2850 i++;
355afbcd
KR		 2851 }
2852 else
2853 slak->m_next = 0;
2854 slak = slak->m_next;
f8701a3f 2855 }
355afbcd
KR		 2856 while (slak);
2857
2858 retval = hash_insert (op_hash, ins->name, (char *) hack);
dff60b7d 2859 if (retval)
b79de3a1
KR		 2860 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
2861 }
2862
a1c7c0f3 2863 for (i = 0; i < m68k_numaliases; i++)
b79de3a1
KR		 2864 {
2865 const char *name = m68k_opcode_aliases[i].primary;
2866 const char *alias = m68k_opcode_aliases[i].alias;
2867 PTR val = hash_find (op_hash, name);
2868 if (!val)
2869 as_fatal ("Internal Error: Can't find %s in hash table", name);
2870 retval = hash_insert (op_hash, alias, val);
2871 if (retval)
2872 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
355afbcd 2873 }
6d27d3a2 2874
355afbcd
KR		 2875 for (i = 0; i < sizeof (mklower_table); i++)
2876 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
6d27d3a2 2877
355afbcd
KR		 2878 for (i = 0; i < sizeof (notend_table); i++)
2879 {
2880 notend_table[i] = 0;
2881 alt_notend_table[i] = 0;
2882 }
2883 notend_table[','] = 1;
2884 notend_table['{'] = 1;
2885 notend_table['}'] = 1;
2886 alt_notend_table['a'] = 1;
2887 alt_notend_table['A'] = 1;
2888 alt_notend_table['d'] = 1;
2889 alt_notend_table['D'] = 1;
2890 alt_notend_table['#'] = 1;
5f8cb05e 2891 alt_notend_table['&'] = 1;
355afbcd
KR		 2892 alt_notend_table['f'] = 1;
2893 alt_notend_table['F'] = 1;
fecd2382 2894#ifdef REGISTER_PREFIX
355afbcd 2895 alt_notend_table[REGISTER_PREFIX] = 1;
fecd2382 2896#endif
f8701a3f 2897
a1c7c0f3
ILT		 2898 /* We need to put '(' in alt_notend_table to handle
2899 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
2900 */
2901 alt_notend_table['('] = 1;
2902
2903 /* We need to put '@' in alt_notend_table to handle
2904 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
2905 */
2906 alt_notend_table['@'] = 1;
2907
3ad9ec6a 2908#ifndef MIT_SYNTAX_ONLY
355afbcd 2909 /* Insert pseudo ops, these have to go into the opcode table since
bcb8dff8 2910 gas expects pseudo ops to start with a dot */
355afbcd
KR		 2911 {
2912 int n = 0;
2913 while (mote_pseudo_table[n].poc_name)
2914 {
2915 hack = (struct m68k_incant *)
2916 obstack_alloc (&robyn, sizeof (struct m68k_incant));
2917 hash_insert (op_hash,
2918 mote_pseudo_table[n].poc_name, (char *) hack);
2919 hack->m_operands = 0;
2920 hack->m_opnum = n;
2921 n++;
2922 }
2923 }
3ad9ec6a
ILT		 2924#endif
2925
355afbcd 2926 init_regtable ();
fecd2382
RP		 2927}
2928
82489ea0
KR		 2929void
2930m68k_init_after_args ()
2931{
2932 if (cpu_of_arch (current_architecture) == 0)
2933 {
064ba683 2934 int i;
b79de3a1 2935 const char *default_cpu = TARGET_CPU;
82489ea0 2936
b79de3a1
KR		 2937 if (*default_cpu == 'm')
2938 default_cpu++;
2939 for (i = 0; i < n_archs; i++)
2940 if (!strcmp (default_cpu, archs[i].name))
2941 break;
2942 if (i == n_archs)
2943 {
2944 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
2945 current_architecture |= m68020;
2946 }
2947 else
2948 current_architecture |= archs[i].arch;
82489ea0 2949 }
b79de3a1
KR		 2950 /* Permit m68881 specification with all cpus; those that can't work
2951 with a coprocessor could be doing emulation. */
82489ea0
KR		 2952 if (current_architecture & m68851)
2953 {
2954 if (current_architecture & m68040)
2955 {
2956 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
2957 }
2958 }
2959 /* What other incompatibilities could we check for? */
2960
2961 /* Toss in some default assumptions about coprocessors. */
2962 if (!no_68881
2963 && (cpu_of_arch (current_architecture)
2964 /* Can CPU32 have a 68881 coprocessor?? */
2965 & (m68020 | m68030 | cpu32)))
2966 {
2967 current_architecture |= m68881;
2968 }
2969 if (!no_68851
2970 && (cpu_of_arch (current_architecture) & m68020up) != 0
2971 && (cpu_of_arch (current_architecture) & m68040up) == 0)
2972 {
2973 current_architecture |= m68851;
2974 }
2975 if (no_68881 && (current_architecture & m68881))
2976 as_bad ("options for 68881 and no-68881 both given");
2977 if (no_68851 && (current_architecture & m68851))
2978 as_bad ("options for 68851 and no-68851 both given");
2979
2980#ifdef OBJ_AOUT
2981 /* Work out the magic number. This isn't very general. */
2982 if (current_architecture & m68000)
2983 m68k_aout_machtype = 0;
2984 else if (current_architecture & m68010)
2985 m68k_aout_machtype = 1;
2986 else if (current_architecture & m68020)
2987 m68k_aout_machtype = 2;
2988 else
2989 m68k_aout_machtype = 2;
2990#endif
2991
2992 /* Note which set of "movec" control registers is available. */
2993 switch (cpu_of_arch (current_architecture))
2994 {
2995 case m68000:
2996 control_regs = m68000_control_regs;
2997 break;
2998 case m68010:
2999 control_regs = m68010_control_regs;
3000 break;
3001 case m68020:
3002 case m68030:
3003 control_regs = m68020_control_regs;
3004 break;
3005 case m68040:
3006 control_regs = m68040_control_regs;
3007 break;
3008 case m68060:
3009 control_regs = m68060_control_regs;
3010 break;
b79de3a1
KR		 3011 case cpu32:
3012 control_regs = cpu32_control_regs;
3013 break;
82489ea0
KR		 3014 default:
3015 abort ();
3016 }
04ef74bb
KR		 3017
3018 if (cpu_of_arch (current_architecture) < m68020)
3019 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
82489ea0
KR		 3020}
3021
fecd2382
RP		 3022/* Equal to MAX_PRECISION in atof-ieee.c */
3023#define MAX_LITTLENUMS 6
3024
a1c7c0f3
ILT		 3025/* Turn a string in input_line_pointer into a floating point constant
3026 of type type, and store the appropriate bytes in *litP. The number
3027 of LITTLENUMS emitted is stored in *sizeP . An error message is
3028 returned, or NULL on OK. */
3029
fecd2382 3030char *
355afbcd
KR		 3031md_atof (type, litP, sizeP)
3032 char type;
3033 char *litP;
3034 int *sizeP;
fecd2382 3035{
355afbcd
KR		 3036 int prec;
3037 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3038 LITTLENUM_TYPE *wordP;
3039 char *t;
3040 char *atof_ieee ();
6d27d3a2 3041
355afbcd
KR		 3042 switch (type)
3043 {
3044 case 'f':
3045 case 'F':
3046 case 's':
3047 case 'S':
3048 prec = 2;
3049 break;
6d27d3a2 3050
355afbcd
KR		 3051 case 'd':
3052 case 'D':
3053 case 'r':
3054 case 'R':
3055 prec = 4;
3056 break;
6d27d3a2 3057
355afbcd
KR		 3058 case 'x':
3059 case 'X':
3060 prec = 6;
3061 break;
6d27d3a2 3062
355afbcd
KR		 3063 case 'p':
3064 case 'P':
3065 prec = 6;
3066 break;
6d27d3a2 3067
355afbcd
KR		 3068 default:
3069 *sizeP = 0;
3070 return "Bad call to MD_ATOF()";
3071 }
3072 t = atof_ieee (input_line_pointer, type, words);
3073 if (t)
3074 input_line_pointer = t;
3075
3076 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3077 for (wordP = words; prec--;)
3078 {
3079 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3080 litP += sizeof (LITTLENUM_TYPE);
3081 }
49864cfa 3082 return 0;
fecd2382
RP		 3083}
3084
fecd2382 3085void
355afbcd
KR		 3086md_number_to_chars (buf, val, n)
3087 char *buf;
025b0302 3088 valueT val;
355afbcd 3089 int n;
fecd2382 3090{
82489ea0 3091 number_to_chars_bigendian (buf, val, n);
fecd2382
RP		 3092}
3093
49864cfa
KR		 3094static void
3095md_apply_fix_2 (fixP, val)
355afbcd 3096 fixS *fixP;
9ad5755f 3097 offsetT val;
fecd2382 3098{
9ad5755f
KR		 3099 addressT upper_limit;
3100 offsetT lower_limit;
49864cfa 3101
9ad5755f
KR		 3102 /* This is unnecessary but it convinces the native rs6000 compiler
3103 to generate the code we want. */
355afbcd
KR		 3104 char *buf = fixP->fx_frag->fr_literal;
3105 buf += fixP->fx_where;
9ad5755f
KR		 3106 /* end ibm compiler workaround */
3107
3108 if (val & 0x80000000)
3109 val |= ~(addressT)0x7fffffff;
3110 else
3111 val &= 0x7fffffff;
6d27d3a2 3112
355afbcd
KR		 3113 switch (fixP->fx_size)
3114 {
b79de3a1
KR		 3115 /* The cast to offsetT below are necessary to make code correct for
3116 machines where ints are smaller than offsetT */
355afbcd
KR		 3117 case 1:
3118 *buf++ = val;
49864cfa 3119 upper_limit = 0x7f;
b79de3a1 3120 lower_limit = - (offsetT) 0x80;
355afbcd
KR		 3121 break;
3122 case 2:
3123 *buf++ = (val >> 8);
3124 *buf++ = val;
49864cfa 3125 upper_limit = 0x7fff;
b79de3a1 3126 lower_limit = - (offsetT) 0x8000;
355afbcd
KR		 3127 break;
3128 case 4:
3129 *buf++ = (val >> 24);
3130 *buf++ = (val >> 16);
3131 *buf++ = (val >> 8);
3132 *buf++ = val;
49864cfa 3133 upper_limit = 0x7fffffff;
b79de3a1 3134 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
355afbcd
KR		 3135 break;
3136 default:
3137 BAD_CASE (fixP->fx_size);
3138 }
49864cfa
KR		 3139
3140 /* For non-pc-relative values, it's conceivable we might get something
3141 like "0xff" for a byte field. So extend the upper part of the range
3142 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3143 so that we can do any range checking at all. */
3144 if (!fixP->fx_pcrel)
3145 upper_limit = upper_limit * 2 + 1;
3146
9ad5755f
KR		 3147 if ((addressT) val > upper_limit
3148 && (val > 0 || val < lower_limit))
f3751617
ILT		 3149 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3150
3151 /* A one byte PC-relative reloc means a short branch. We can't use
3152 a short branch with a value of 0 or -1, because those indicate
3153 different opcodes (branches with longer offsets). */
3154 if (fixP->fx_pcrel
3155 && fixP->fx_size == 1
3156 && (fixP->fx_addsy == NULL
3157 || S_IS_DEFINED (fixP->fx_addsy))
3158 && (val == 0 || val == -1))
3159 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
fecd2382
RP		 3160}
3161
49864cfa
KR		 3162#ifdef BFD_ASSEMBLER
3163int
3164md_apply_fix (fixP, valp)
3165 fixS *fixP;
5f8cb05e 3166 valueT *valp;
49864cfa 3167{
9ad5755f 3168 md_apply_fix_2 (fixP, (addressT) *valp);
49864cfa
KR		 3169 return 1;
3170}
3171#else
3172void md_apply_fix (fixP, val)
3173 fixS *fixP;
3174 long val;
3175{
9ad5755f 3176 md_apply_fix_2 (fixP, (addressT) val);
49864cfa
KR		 3177}
3178#endif
fecd2382
RP		 3179
3180/* *fragP has been relaxed to its final size, and now needs to have
3181 the bytes inside it modified to conform to the new size There is UGLY
3182 MAGIC here. ..
a39116f1 3183 */
fecd2382 3184void
49864cfa 3185md_convert_frag_1 (fragP)
355afbcd 3186 register fragS *fragP;
fecd2382 3187{
355afbcd
KR		 3188 long disp;
3189 long ext = 0;
5f8cb05e 3190 fixS *fixP;
6d27d3a2 3191
355afbcd
KR		 3192 /* Address in object code of the displacement. */
3193 register int object_address = fragP->fr_fix + fragP->fr_address;
6d27d3a2 3194
9ad5755f
KR		 3195 /* Address in gas core of the place to store the displacement. */
3196 /* This convinces the native rs6000 compiler to generate the code we
3197 want. */
355afbcd
KR		 3198 register char *buffer_address = fragP->fr_literal;
3199 buffer_address += fragP->fr_fix;
9ad5755f 3200 /* end ibm compiler workaround */
6d27d3a2 3201
355afbcd
KR		 3202 /* The displacement of the address, from current location. */
3203 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3204 disp = (disp + fragP->fr_offset) - object_address;
6d27d3a2 3205
5f8cb05e
ILT		 3206#ifdef BFD_ASSEMBLER
3207 disp += fragP->fr_symbol->sy_frag->fr_address;
3208#endif
3209
355afbcd
KR		 3210 switch (fragP->fr_subtype)
3211 {
3212 case TAB (BCC68000, BYTE):
3213 case TAB (ABRANCH, BYTE):
3214 know (issbyte (disp));
3215 if (disp == 0)
3216 as_bad ("short branch with zero offset: use :w");
3217 fragP->fr_opcode[1] = disp;
3218 ext = 0;
3219 break;
3220 case TAB (DBCC, SHORT):
3221 know (issword (disp));
3222 ext = 2;
3223 break;
3224 case TAB (BCC68000, SHORT):
3225 case TAB (ABRANCH, SHORT):
3226 know (issword (disp));
3227 fragP->fr_opcode[1] = 0x00;
3228 ext = 2;
3229 break;
3230 case TAB (ABRANCH, LONG):
3231 if (cpu_of_arch (current_architecture) < m68020)
3232 {
3233 if (fragP->fr_opcode[0] == 0x61)
04ef74bb 3234 /* BSR */
355afbcd
KR		 3235 {
3236 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 3237 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
49864cfa 3238 subseg_change (text_section, 0); /* @@ */
355afbcd
KR		 3239
3240 fix_new (fragP,
3241 fragP->fr_fix,
3242 4,
3243 fragP->fr_symbol,
355afbcd
KR		 3244 fragP->fr_offset,
3245 0,
3246 NO_RELOC);
3247
3248 fragP->fr_fix += 4;
3249 ext = 0;
3250 }
04ef74bb 3251 /* BRA */
355afbcd
KR		 3252 else if (fragP->fr_opcode[0] == 0x60)
3253 {
3254 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 3255 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
49864cfa 3256 subseg_change (text_section, 0); /* @@ */
bcb8dff8
KR		 3257 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3258 fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 3259 fragP->fr_fix += 4;
3260 ext = 0;
3261 }
3262 else
3263 {
3264 as_bad ("Long branch offset not supported.");
3265 }
3266 }
3267 else
3268 {
bcb8dff8 3269 fragP->fr_opcode[1] = (char) 0xff;
355afbcd
KR		 3270 ext = 4;
3271 }
3272 break;
3273 case TAB (BCC68000, LONG):
3274 /* only Bcc 68000 instructions can come here */
3275 /* change bcc into b!cc/jmp absl long */
3276 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3277 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
6d27d3a2 3278
355afbcd 3279 /* JF: these used to be fr_opcode[2,3], but they may be in a
fecd2382
RP		 3280 different frag, in which case refering to them is a no-no.
3281 Only fr_opcode[0,1] are guaranteed to work. */
355afbcd 3282 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 3283 *buffer_address++ = (char) 0xf9;
355afbcd 3284 fragP->fr_fix += 2; /* account for jmp instruction */
49864cfa 3285 subseg_change (text_section, 0);
bcb8dff8
KR		 3286 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3287 fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 3288 fragP->fr_fix += 4;
3289 ext = 0;
3290 break;
3291 case TAB (DBCC, LONG):
3292 /* only DBcc 68000 instructions can come here */
3293 /* change dbcc into dbcc/jmp absl long */
3294 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3295 *buffer_address++ = 0x00; /* branch offset = 4 */
3296 *buffer_address++ = 0x04;
3297 *buffer_address++ = 0x60; /* put in bra pc+6 */
3298 *buffer_address++ = 0x06;
3299 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 3300 *buffer_address++ = (char) 0xf9;
355afbcd
KR		 3301
3302 fragP->fr_fix += 6; /* account for bra/jmp instructions */
49864cfa 3303 subseg_change (text_section, 0);
bcb8dff8 3304 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
49864cfa 3305 fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 3306 fragP->fr_fix += 4;
3307 ext = 0;
3308 break;
3309 case TAB (FBRANCH, SHORT):
3310 know ((fragP->fr_opcode[1] & 0x40) == 0);
3311 ext = 2;
3312 break;
3313 case TAB (FBRANCH, LONG):
3314 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3315 ext = 4;
3316 break;
3317 case TAB (PCREL, SHORT):
3318 ext = 2;
3319 break;
3320 case TAB (PCREL, LONG):
3321 /* The thing to do here is force it to ABSOLUTE LONG, since
f8701a3f 3322 PCREL is really trying to shorten an ABSOLUTE address anyway */
355afbcd 3323 /* JF FOO This code has not been tested */
49864cfa 3324 subseg_change (text_section, 0);
bcb8dff8 3325 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
49864cfa 3326 0, NO_RELOC);
355afbcd 3327 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
bcb8dff8
KR		 3328 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
3329 (unsigned) fragP->fr_opcode[0],
3330 (unsigned long) fragP->fr_address);
355afbcd
KR		 3331 fragP->fr_opcode[1] &= ~0x3F;
3332 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
3333 fragP->fr_fix += 4;
355afbcd
KR		 3334 ext = 0;
3335 break;
3336 case TAB (PCLEA, SHORT):
49864cfa
KR		 3337 subseg_change (text_section, 0);
3338 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
bcb8dff8 3339 fragP->fr_offset, 1, NO_RELOC);
355afbcd 3340 fragP->fr_opcode[1] &= ~0x3F;
04ef74bb 3341 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
355afbcd
KR		 3342 ext = 2;
3343 break;
3344 case TAB (PCLEA, LONG):
49864cfa 3345 subseg_change (text_section, 0);
5f8cb05e
ILT		 3346 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
3347 fragP->fr_offset, 1, NO_RELOC);
3348 fixP->fx_pcrel_adjust = 2;
04ef74bb
KR		 3349 /* Already set to mode 7.3; this indicates: PC indirect with
3350 suppressed index, 32-bit displacement. */
355afbcd
KR		 3351 *buffer_address++ = 0x01;
3352 *buffer_address++ = 0x70;
3353 fragP->fr_fix += 2;
355afbcd
KR		 3354 ext = 4;
3355 break;
04ef74bb
KR		 3356
3357 case TAB (PCINDEX, BYTE):
3358 disp += 2;
3359 if (!issbyte (disp))
3360 {
3361 as_bad ("displacement doesn't fit in one byte");
3362 disp = 0;
3363 }
5f8cb05e
ILT		 3364 assert (fragP->fr_fix >= 2);
3365 buffer_address[-2] &= ~1;
3366 buffer_address[-1] = disp;
04ef74bb
KR		 3367 ext = 0;
3368 break;
3369 case TAB (PCINDEX, SHORT):
3370 subseg_change (text_section, 0);
3371 disp += 2;
3372 assert (issword (disp));
5f8cb05e
ILT		 3373 assert (fragP->fr_fix >= 2);
3374 buffer_address[-2] |= 0x1;
3375 buffer_address[-1] = 0x20;
3376 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3377 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3378 NO_RELOC);
3379 fixP->fx_pcrel_adjust = 2;
04ef74bb
KR		 3380 ext = 2;
3381 break;
3382 case TAB (PCINDEX, LONG):
3383 subseg_change (text_section, 0);
3384 disp += 2;
5f8cb05e
ILT		 3385 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3386 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3387 NO_RELOC);
3388 fixP->fx_pcrel_adjust = 2;
3389 assert (fragP->fr_fix >= 2);
3390 buffer_address[-2] |= 0x1;
3391 buffer_address[-1] = 0x30;
04ef74bb
KR		 3392 ext = 4;
3393 break;
49864cfa 3394 }
355afbcd
KR		 3395
3396 if (ext)
3397 {
3398 md_number_to_chars (buffer_address, (long) disp, (int) ext);
3399 fragP->fr_fix += ext;
49864cfa
KR		 3400 }
3401}
355afbcd 3402
49864cfa
KR		 3403#ifndef BFD_ASSEMBLER
3404
3405void
064ba683 3406md_convert_frag (headers, sec, fragP)
49864cfa 3407 object_headers *headers;
064ba683 3408 segT sec;
49864cfa
KR		 3409 fragS *fragP;
3410{
3411 md_convert_frag_1 (fragP);
3412}
3413
3414#else
3415
3416void
3417md_convert_frag (abfd, sec, fragP)
3418 bfd *abfd;
5f8cb05e 3419 segT sec;
49864cfa
KR		 3420 fragS *fragP;
3421{
3422 md_convert_frag_1 (fragP);
3423}
3424#endif
355afbcd
KR		 3425
3426/* Force truly undefined symbols to their maximum size, and generally set up
3427 the frag list to be relaxed
3428 */
3429int
3430md_estimate_size_before_relax (fragP, segment)
3431 register fragS *fragP;
3432 segT segment;
3433{
3434 int old_fix;
3435 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3436
3437 old_fix = fragP->fr_fix;
3438
3439 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3440 switch (fragP->fr_subtype)
3441 {
3442
3443 case TAB (ABRANCH, SZ_UNDEF):
3444 {
3445 if ((fragP->fr_symbol != NULL) /* Not absolute */
3446 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3447 {
3448 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
3449 break;
3450 }
3451 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
3452 {
3453 /* On 68000, or for absolute value, switch to abs long */
3454 /* FIXME, we should check abs val, pick short or long */
3455 if (fragP->fr_opcode[0] == 0x61)
3456 {
3457 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 3458 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
49864cfa 3459 subseg_change (text_section, 0);
355afbcd 3460 fix_new (fragP, fragP->fr_fix, 4,
bcb8dff8 3461 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 3462 fragP->fr_fix += 4;
3463 frag_wane (fragP);
3464 }
3465 else if (fragP->fr_opcode[0] == 0x60)
3466 {
3467 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 3468 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
49864cfa 3469 subseg_change (text_section, 0);
355afbcd 3470 fix_new (fragP, fragP->fr_fix, 4,
bcb8dff8 3471 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 3472 fragP->fr_fix += 4;
3473 frag_wane (fragP);
3474 }
3475 else
3476 {
3477 as_warn ("Long branch offset to extern symbol not supported.");
3478 }
3479 }
3480 else
3481 { /* Symbol is still undefined. Make it simple */
3482 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5f8cb05e 3483 fragP->fr_offset, 1, NO_RELOC);
355afbcd 3484 fragP->fr_fix += 4;
bcb8dff8 3485 fragP->fr_opcode[1] = (char) 0xff;
355afbcd
KR		 3486 frag_wane (fragP);
3487 break;
3488 }
3489
a39116f1 3490 break;
355afbcd 3491 } /* case TAB(ABRANCH,SZ_UNDEF) */
6d27d3a2 3492
355afbcd
KR		 3493 case TAB (FBRANCH, SZ_UNDEF):
3494 {
9ad5755f 3495 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
355afbcd
KR		 3496 {
3497 fragP->fr_subtype = TAB (FBRANCH, SHORT);
3498 fragP->fr_var += 2;
3499 }
3500 else
3501 {
5f8cb05e
ILT		 3502 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
3503 fragP->fr_offset, 1, NO_RELOC);
3504 fragP->fr_fix += 4;
3505 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3506 frag_wane (fragP);
355afbcd
KR		 3507 }
3508 break;
3509 } /* TAB(FBRANCH,SZ_UNDEF) */
6d27d3a2 3510
355afbcd
KR		 3511 case TAB (PCREL, SZ_UNDEF):
3512 {
b79de3a1
KR		 3513 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3514 || flag_short_refs
3515 || cpu_of_arch (current_architecture) < m68020)
355afbcd
KR		 3516 {
3517 fragP->fr_subtype = TAB (PCREL, SHORT);
3518 fragP->fr_var += 2;
3519 }
3520 else
3521 {
3522 fragP->fr_subtype = TAB (PCREL, LONG);
3523 fragP->fr_var += 4;
3524 }
3525 break;
3526 } /* TAB(PCREL,SZ_UNDEF) */
6d27d3a2 3527
355afbcd
KR		 3528 case TAB (BCC68000, SZ_UNDEF):
3529 {
3530 if ((fragP->fr_symbol != NULL)
3531 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3532 {
3533 fragP->fr_subtype = TAB (BCC68000, BYTE);
3534 break;
3535 }
3536 /* only Bcc 68000 instructions can come here */
3537 /* change bcc into b!cc/jmp absl long */
3538 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
9ad5755f 3539 if (flag_short_refs)
355afbcd
KR		 3540 {
3541 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
3542 /* JF: these were fr_opcode[2,3] */
3543 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 3544 buffer_address[1] = (char) 0xf8;
355afbcd 3545 fragP->fr_fix += 2; /* account for jmp instruction */
49864cfa 3546 subseg_change (text_section, 0);
bcb8dff8 3547 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
355afbcd
KR		 3548 fragP->fr_offset, 0, NO_RELOC);
3549 fragP->fr_fix += 2;
3550 }
3551 else
3552 {
3553 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
3554 /* JF: these were fr_opcode[2,3] */
3555 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 3556 buffer_address[1] = (char) 0xf9;
355afbcd 3557 fragP->fr_fix += 2; /* account for jmp instruction */
49864cfa 3558 subseg_change (text_section, 0);
bcb8dff8 3559 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
355afbcd
KR		 3560 fragP->fr_offset, 0, NO_RELOC);
3561 fragP->fr_fix += 4;
3562 }
3563 frag_wane (fragP);
3564 break;
3565 } /* case TAB(BCC68000,SZ_UNDEF) */
f8701a3f 3566
355afbcd
KR		 3567 case TAB (DBCC, SZ_UNDEF):
3568 {
3569 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3570 {
3571 fragP->fr_subtype = TAB (DBCC, SHORT);
3572 fragP->fr_var += 2;
3573 break;
3574 }
3575 /* only DBcc 68000 instructions can come here */
3576 /* change dbcc into dbcc/jmp absl long */
3577 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3578 buffer_address[0] = 0x00; /* branch offset = 4 */
3579 buffer_address[1] = 0x04;
3580 buffer_address[2] = 0x60; /* put in bra pc + ... */
3581
9ad5755f 3582 if (flag_short_refs)
355afbcd
KR		 3583 {
3584 /* JF: these were fr_opcode[5-7] */
3585 buffer_address[3] = 0x04; /* plus 4 */
3586 buffer_address[4] = 0x4e; /* Put in Jump Word */
bcb8dff8 3587 buffer_address[5] = (char) 0xf8;
355afbcd 3588 fragP->fr_fix += 6; /* account for bra/jmp instruction */
49864cfa 3589 subseg_change (text_section, 0);
bcb8dff8 3590 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
355afbcd
KR		 3591 fragP->fr_offset, 0, NO_RELOC);
3592 fragP->fr_fix += 2;
3593 }
3594 else
3595 {
3596 /* JF: these were fr_opcode[5-7] */
3597 buffer_address[3] = 0x06; /* Plus 6 */
3598 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 3599 buffer_address[5] = (char) 0xf9;
355afbcd 3600 fragP->fr_fix += 6; /* account for bra/jmp instruction */
49864cfa 3601 subseg_change (text_section, 0);
bcb8dff8 3602 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
355afbcd
KR		 3603 fragP->fr_offset, 0, NO_RELOC);
3604 fragP->fr_fix += 4;
3605 }
6d27d3a2 3606
355afbcd
KR		 3607 frag_wane (fragP);
3608 break;
3609 } /* case TAB(DBCC,SZ_UNDEF) */
6d27d3a2 3610
355afbcd
KR		 3611 case TAB (PCLEA, SZ_UNDEF):
3612 {
b79de3a1
KR		 3613 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
3614 || flag_short_refs
3615 || cpu_of_arch (current_architecture) < m68020)
355afbcd
KR		 3616 {
3617 fragP->fr_subtype = TAB (PCLEA, SHORT);
3618 fragP->fr_var += 2;
3619 }
3620 else
3621 {
3622 fragP->fr_subtype = TAB (PCLEA, LONG);
3623 fragP->fr_var += 6;
3624 }
3625 break;
3626 } /* TAB(PCLEA,SZ_UNDEF) */
6d27d3a2 3627
04ef74bb
KR		 3628 case TAB (PCINDEX, SZ_UNDEF):
3629 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3630 || cpu_of_arch (current_architecture) < m68020)
3631 {
3632 fragP->fr_subtype = TAB (PCINDEX, BYTE);
3633 }
3634 else
3635 {
3636 fragP->fr_subtype = TAB (PCINDEX, LONG);
5f8cb05e 3637 fragP->fr_var += 4;
04ef74bb 3638 }
355afbcd 3639 break;
6d27d3a2 3640
04ef74bb
KR		 3641 default:
3642 break;
3643 }
6d27d3a2 3644
355afbcd
KR		 3645 /* now that SZ_UNDEF are taken care of, check others */
3646 switch (fragP->fr_subtype)
3647 {
3648 case TAB (BCC68000, BYTE):
3649 case TAB (ABRANCH, BYTE):
3650 /* We can't do a short jump to the next instruction,
a39116f1 3651 so we force word mode. */
355afbcd
KR		 3652 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 &&
3653 fragP->fr_symbol->sy_frag == fragP->fr_next)
3654 {
3655 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
3656 fragP->fr_var += 2;
fecd2382 3657 }
355afbcd
KR		 3658 break;
3659 default:
3660 break;
3661 }
3662 return fragP->fr_var + fragP->fr_fix - old_fix;
fecd2382
RP		 3663}
3664
3665#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
6d27d3a2 3666/* the bit-field entries in the relocation_info struct plays hell
fecd2382
RP		 3667 with the byte-order problems of cross-assembly. So as a hack,
3668 I added this mach. dependent ri twiddler. Ugly, but it gets
3669 you there. -KWK */
3670/* on m68k: first 4 bytes are normal unsigned long, next three bytes
a39116f1
RP		 3671 are symbolnum, most sig. byte first. Last byte is broken up with
3672 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3673 nibble as nuthin. (on Sun 3 at least) */
fecd2382
RP		 3674/* Translate the internal relocation information into target-specific
3675 format. */
a79c6033 3676#ifdef comment
fecd2382 3677void
355afbcd
KR		 3678md_ri_to_chars (the_bytes, ri)
3679 char *the_bytes;
3680 struct reloc_info_generic *ri;
fecd2382 3681{
355afbcd
KR		 3682 /* this is easy */
3683 md_number_to_chars (the_bytes, ri->r_address, 4);
3684 /* now the fun stuff */
3685 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
3686 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
3687 the_bytes[6] = ri->r_symbolnum & 0x0ff;
3688 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
3689 ((ri->r_extern << 4) & 0x10));
fecd2382 3690}
355afbcd 3691
a79c6033
RP		 3692#endif /* comment */
3693
49864cfa 3694#ifndef BFD_ASSEMBLER
355afbcd
KR		 3695void
3696tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
3697 char *where;
3698 fixS *fixP;
3699 relax_addressT segment_address_in_file;
a79c6033 3700{
355afbcd 3701 /*
1404ef23
KR		 3702 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3703 * Out: GNU LD relocation length code: 0, 1, or 2.
3704 */
6d27d3a2 3705
82489ea0 3706 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
355afbcd 3707 long r_symbolnum;
6d27d3a2 3708
355afbcd 3709 know (fixP->fx_addsy != NULL);
6d27d3a2 3710
355afbcd
KR		 3711 md_number_to_chars (where,
3712 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
3713 4);
6d27d3a2 3714
355afbcd
KR		 3715 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
3716 ? S_GET_TYPE (fixP->fx_addsy)
3717 : fixP->fx_addsy->sy_number);
6d27d3a2 3718
355afbcd
KR		 3719 where[4] = (r_symbolnum >> 16) & 0x0ff;
3720 where[5] = (r_symbolnum >> 8) & 0x0ff;
3721 where[6] = r_symbolnum & 0x0ff;
3722 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
3723 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
49864cfa
KR		 3724}
3725#endif
a79c6033 3726
fecd2382
RP		 3727#endif /* OBJ_AOUT or OBJ_BOUT */
3728
3729#ifndef WORKING_DOT_WORD
49864cfa
KR		 3730CONST int md_short_jump_size = 4;
3731CONST int md_long_jump_size = 6;
fecd2382
RP		 3732
3733void
355afbcd
KR		 3734md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
3735 char *ptr;
025b0302 3736 addressT from_addr, to_addr;
355afbcd
KR		 3737 fragS *frag;
3738 symbolS *to_symbol;
fecd2382 3739{
025b0302 3740 valueT offset;
6d27d3a2 3741
355afbcd 3742 offset = to_addr - (from_addr + 2);
6d27d3a2 3743
025b0302
ME		 3744 md_number_to_chars (ptr, (valueT) 0x6000, 2);
3745 md_number_to_chars (ptr + 2, (valueT) offset, 2);
fecd2382
RP		 3746}
3747
3748void
355afbcd
KR		 3749md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
3750 char *ptr;
025b0302 3751 addressT from_addr, to_addr;
355afbcd
KR		 3752 fragS *frag;
3753 symbolS *to_symbol;
fecd2382 3754{
025b0302 3755 valueT offset;
355afbcd
KR		 3756
3757 if (cpu_of_arch (current_architecture) < m68020)
3758 {
3759 offset = to_addr - S_GET_VALUE (to_symbol);
025b0302
ME		 3760 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
3761 md_number_to_chars (ptr + 2, (valueT) offset, 4);
bcb8dff8
KR		 3762 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
3763 0, NO_RELOC);
355afbcd
KR		 3764 }
3765 else
3766 {
3767 offset = to_addr - (from_addr + 2);
025b0302
ME		 3768 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
3769 md_number_to_chars (ptr + 2, (valueT) offset, 4);
355afbcd 3770 }
fecd2382
RP		 3771}
3772
3773#endif
a1c7c0f3
ILT		 3774
3775/* Different values of OK tell what its OK to return. Things that
3776 aren't OK are an error (what a shock, no?)
6d27d3a2 3777
a39116f1
RP		 3778 0: Everything is OK
3779 10: Absolute 1:8 only
3780 20: Absolute 0:7 only
3781 30: absolute 0:15 only
3782 40: Absolute 0:31 only
3783 50: absolute 0:127 only
3784 55: absolute -64:63 only
3785 60: absolute -128:127 only
3786 70: absolute 0:4095 only
3787 80: No bignums
6d27d3a2 3788
a39116f1 3789 */
fecd2382 3790
355afbcd
KR		 3791static int
3792get_num (exp, ok)
3793 struct m68k_exp *exp;
3794 int ok;
fecd2382 3795{
a1c7c0f3 3796 if (exp->exp.X_op == O_absent)
49864cfa 3797 {
355afbcd 3798 /* Do the same thing the VAX asm does */
bcb8dff8 3799 op (exp) = O_constant;
355afbcd
KR		 3800 adds (exp) = 0;
3801 subs (exp) = 0;
3802 offs (exp) = 0;
3803 if (ok == 10)
3804 {
3805 as_warn ("expression out of range: defaulting to 1");
3806 offs (exp) = 1;
3807 }
49864cfa 3808 }
a1c7c0f3 3809 else if (exp->exp.X_op == O_constant)
49864cfa 3810 {
355afbcd
KR		 3811 switch (ok)
3812 {
3813 case 10:
3814 if (offs (exp) < 1 || offs (exp) > 8)
3815 {
3816 as_warn ("expression out of range: defaulting to 1");
3817 offs (exp) = 1;
3818 }
3819 break;
3820 case 20:
3821 if (offs (exp) < 0 || offs (exp) > 7)
3822 goto outrange;
3823 break;
3824 case 30:
3825 if (offs (exp) < 0 || offs (exp) > 15)
3826 goto outrange;
3827 break;
3828 case 40:
3829 if (offs (exp) < 0 || offs (exp) > 32)
3830 goto outrange;
3831 break;
3832 case 50:
3833 if (offs (exp) < 0 || offs (exp) > 127)
3834 goto outrange;
3835 break;
3836 case 55:
3837 if (offs (exp) < -64 || offs (exp) > 63)
3838 goto outrange;
3839 break;
3840 case 60:
3841 if (offs (exp) < -128 || offs (exp) > 127)
3842 goto outrange;
3843 break;
3844 case 70:
3845 if (offs (exp) < 0 || offs (exp) > 4095)
3846 {
3847 outrange:
3848 as_warn ("expression out of range: defaulting to 0");
3849 offs (exp) = 0;
3850 }
3851 break;
fecd2382 3852 default:
355afbcd
KR		 3853 break;
3854 }
49864cfa 3855 }
a1c7c0f3 3856 else if (exp->exp.X_op == O_big)
49864cfa 3857 {
bcb8dff8 3858 if (offs (exp) <= 0 /* flonum */
355afbcd
KR		 3859 && (ok == 80 /* no bignums */
3860 || (ok > 10 /* small-int ranges including 0 ok */
1404ef23
KR		 3861 /* If we have a flonum zero, a zero integer should
3862 do as well (e.g., in moveq). */
355afbcd
KR		 3863 && generic_floating_point_number.exponent == 0
3864 && generic_floating_point_number.low[0] == 0)))
3865 {
3866 /* HACK! Turn it into a long */
3867 LITTLENUM_TYPE words[6];
3868
3869 gen_to_words (words, 2, 8L); /* These numbers are magic! */
bcb8dff8 3870 op (exp) = O_constant;
355afbcd
KR		 3871 adds (exp) = 0;
3872 subs (exp) = 0;
3873 offs (exp) = words[1] | (words[0] << 16);
3874 }
3875 else if (ok != 0)
3876 {
bcb8dff8 3877 op (exp) = O_constant;
355afbcd
KR		 3878 adds (exp) = 0;
3879 subs (exp) = 0;
3880 offs (exp) = (ok == 10) ? 1 : 0;
a1c7c0f3
ILT		 3881 as_warn ("Can't deal with expression; defaulting to %ld",
3882 offs (exp));
355afbcd 3883 }
49864cfa
KR		 3884 }
3885 else
3886 {
355afbcd
KR		 3887 if (ok >= 10 && ok <= 70)
3888 {
bcb8dff8 3889 op (exp) = O_constant;
355afbcd
KR		 3890 adds (exp) = 0;
3891 subs (exp) = 0;
3892 offs (exp) = (ok == 10) ? 1 : 0;
a1c7c0f3
ILT		 3893 as_warn ("Can't deal with expression; defaulting to %ld",
3894 offs (exp));
355afbcd 3895 }
355afbcd 3896 }
49864cfa 3897
a1c7c0f3 3898 if (exp->size != SIZE_UNSPEC)
355afbcd 3899 {
a1c7c0f3 3900 switch (exp->size)
355afbcd 3901 {
a1c7c0f3
ILT		 3902 case SIZE_UNSPEC:
3903 case SIZE_LONG:
3904 break;
3905 case SIZE_BYTE:
355afbcd
KR		 3906 if (!isbyte (offs (exp)))
3907 as_warn ("expression doesn't fit in BYTE");
3908 break;
a1c7c0f3 3909 case SIZE_WORD:
355afbcd
KR		 3910 if (!isword (offs (exp)))
3911 as_warn ("expression doesn't fit in WORD");
3912 break;
a39116f1 3913 }
355afbcd 3914 }
a1c7c0f3 3915
355afbcd 3916 return offs (exp);
49864cfa 3917}
fecd2382
RP		 3918
3919/* These are the back-ends for the various machine dependent pseudo-ops. */
355afbcd 3920void demand_empty_rest_of_line (); /* Hate those extra verbose names */
fecd2382 3921
355afbcd 3922static void
bcb8dff8
KR		 3923s_data1 (ignore)
3924 int ignore;
355afbcd 3925{
bcb8dff8 3926 subseg_set (data_section, 1);
355afbcd 3927 demand_empty_rest_of_line ();
49864cfa 3928}
fecd2382 3929
355afbcd 3930static void
bcb8dff8
KR		 3931s_data2 (ignore)
3932 int ignore;
355afbcd 3933{
bcb8dff8 3934 subseg_set (data_section, 2);
355afbcd 3935 demand_empty_rest_of_line ();
49864cfa 3936}
fecd2382 3937
355afbcd 3938static void
bcb8dff8
KR		 3939s_bss (ignore)
3940 int ignore;
a1765cf0 3941{
355afbcd 3942 /* We don't support putting frags in the BSS segment, we fake it
49864cfa 3943 by marking in_bss, then looking at s_skip for clues. */
a1765cf0 3944
bcb8dff8 3945 subseg_set (bss_section, 0);
355afbcd 3946 demand_empty_rest_of_line ();
49864cfa 3947}
6d27d3a2 3948
355afbcd 3949static void
bcb8dff8
KR		 3950s_even (ignore)
3951 int ignore;
355afbcd
KR		 3952{
3953 register int temp;
3954 register long temp_fill;
3955
3956 temp = 1; /* JF should be 2? */
3957 temp_fill = get_absolute_expression ();
3958 if (!need_pass_2) /* Never make frag if expect extra pass. */
3959 frag_align (temp, (int) temp_fill);
3960 demand_empty_rest_of_line ();
49864cfa 3961}
355afbcd
KR		 3962
3963static void
bcb8dff8
KR		 3964s_proc (ignore)
3965 int ignore;
355afbcd
KR		 3966{
3967 demand_empty_rest_of_line ();
49864cfa 3968}
fecd2382
RP		 3969
3970/* s_space is defined in read.c .skip is simply an alias to it. */
3971
f3d817d8 3972\f
7c15cbe8
RP		 3973/*
3974 * md_parse_option
3975 * Invocation line includes a switch not recognized by the base assembler.
3976 * See if it's a processor-specific option. These are:
3977 *
3978 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
3979 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
3980 * Select the architecture. Instructions or features not
3981 * supported by the selected architecture cause fatal
3982 * errors. More than one may be specified. The default is
3983 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
3984 * for -m68000, and -m68882 is a synonym for -m68881.
df3768fb
KR		 3985 * -[A]m[c]no-68851, -[A]m[c]no-68881
3986 * Don't accept 688?1 instructions. (The "c" is kind of silly,
3987 * so don't use or document it, but that's the way the parsing
3988 * works).
7c15cbe8 3989 *
dff60b7d
ILT		 3990 * -pic Indicates PIC.
3991 * -k Indicates PIC. (Sun 3 only.)
b80d39a0 3992 *
7c15cbe8
RP		 3993 */
3994
5f8cb05e
ILT		 3995#ifdef OBJ_ELF
3996CONST char *md_shortopts = "lSA:m:kQ:V";
3997#else
f3d817d8 3998CONST char *md_shortopts = "lSA:m:k";
5f8cb05e
ILT		 3999#endif
4000
f3d817d8
DM		 4001struct option md_longopts[] = {
4002#define OPTION_PIC (OPTION_MD_BASE)
4003 {"pic", no_argument, NULL, OPTION_PIC},
4004#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
4005 {"register-prefix-optional", no_argument, NULL,
4006 OPTION_REGISTER_PREFIX_OPTIONAL},
4007 {NULL, no_argument, NULL, 0}
4008};
4009size_t md_longopts_size = sizeof(md_longopts);
82489ea0 4010
355afbcd 4011int
f3d817d8
DM		 4012md_parse_option (c, arg)
4013 int c;
4014 char *arg;
fecd2382 4015{
f3d817d8 4016 switch (c)
355afbcd
KR		 4017 {
4018 case 'l': /* -l means keep external to 2 bit offset
e284846a 4019 rather than 16 bit one */
9ad5755f 4020 flag_short_refs = 1;
355afbcd 4021 break;
6d27d3a2 4022
e284846a
KR		 4023 case 'S': /* -S means that jbsr's always turn into
4024 jsr's. */
9ad5755f 4025 flag_long_jumps = 1;
355afbcd 4026 break;
6d27d3a2 4027
355afbcd 4028 case 'A':
f3d817d8
DM		 4029 if (*arg == 'm')
4030 arg++;
355afbcd
KR		 4031 /* intentional fall-through */
4032 case 'm':
355afbcd 4033
b79de3a1 4034 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
e284846a 4035 {
064ba683
ILT		 4036 int i;
4037 unsigned long arch;
b79de3a1
KR		 4038 const char *oarg = arg;
4039
4040 arg += 3;
4041 if (*arg == 'm')
4042 {
4043 arg++;
4044 if (arg[0] == 'c' && arg[1] == '6')
4045 arg++;
4046 }
4047 for (i = 0; i < n_archs; i++)
4048 if (!strcmp (arg, archs[i].name))
4049 break;
4050 if (i == n_archs)
4051 {
4052 unknown:
4053 as_bad ("unrecognized option `%s'", oarg);
4054 return 0;
4055 }
4056 arch = archs[i].arch;
4057 if (arch == m68881)
4058 no_68881 = 1;
4059 else if (arch == m68851)
4060 no_68851 = 1;
4061 else
4062 goto unknown;
355afbcd
KR		 4063 }
4064 else
4065 {
b79de3a1
KR		 4066 int i;
4067
4068 if (arg[0] == 'c' && arg[1] == '6')
4069 arg++;
4070
4071 for (i = 0; i < n_archs; i++)
4072 if (!strcmp (arg, archs[i].name))
4073 {
4074 unsigned long arch = archs[i].arch;
4075 if (cpu_of_arch (arch))
4076 /* It's a cpu spec. */
4077 {
4078 current_architecture &= ~m68000up;
4079 current_architecture |= arch;
4080 }
4081 else if (arch == m68881)
4082 {
4083 current_architecture |= m68881;
4084 no_68881 = 0;
4085 }
4086 else if (arch == m68851)
4087 {
4088 current_architecture |= m68851;
4089 no_68851 = 0;
4090 }
4091 else
4092 /* ??? */
4093 abort ();
4094 break;
4095 }
4096 if (i == n_archs)
4097 {
4098 as_bad ("unrecognized architecture specification `%s'", arg);
4099 return 0;
4100 }
f8701a3f 4101 }
f3d817d8 4102 break;
dff60b7d 4103
f3d817d8 4104 case OPTION_PIC:
dff60b7d
ILT		 4105 case 'k':
4106 flag_want_pic = 1;
f3d817d8
DM		 4107 break; /* -pic, Position Independent Code */
4108
4109 case OPTION_REGISTER_PREFIX_OPTIONAL:
4110 flag_reg_prefix_optional = 1;
dff60b7d 4111 break;
355afbcd 4112
5f8cb05e
ILT		 4113 case 'Q':
4114 case 'V':
4115 break;
4116
355afbcd
KR		 4117 default:
4118 return 0;
4119 }
f3d817d8 4120
355afbcd 4121 return 1;
fecd2382
RP		 4122}
4123
f3d817d8
DM		 4124void
4125md_show_usage (stream)
4126 FILE *stream;
4127{
4128 fprintf(stream, "\
4129680X0 options:\n\
4130-l use 1 word for refs to undefined symbols [default 2]\n\
5f8cb05e
ILT		 4131-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
4132 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
4133 | -mcpu32\n\
f3d817d8
DM		 4134 specify variant of 680X0 architecture [default 68020]\n\
4135-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
4136 target has/lacks floating-point coprocessor\n\
4137 [default yes for 68020, 68030, and cpu32]\n\
4138-m68851 | -mno-68851\n\
4139 target has/lacks memory-management unit coprocessor\n\
4140 [default yes for 68020 and up]\n\
4141-pic, -k generate position independent code\n\
4142-S turn jbsr into jsr\n\
4143--register-prefix-optional\n\
4144 recognize register names without prefix character\n");
4145}
4146\f
fecd2382
RP		 4147#ifdef TEST2
4148
4149/* TEST2: Test md_assemble() */
4150/* Warning, this routine probably doesn't work anymore */
4151
355afbcd 4152main ()
fecd2382 4153{
355afbcd
KR		 4154 struct m68k_it the_ins;
4155 char buf[120];
4156 char *cp;
4157 int n;
4158
4159 m68k_ip_begin ();
4160 for (;;)
4161 {
4162 if (!gets (buf) || !*buf)
4163 break;
4164 if (buf[0] == '|' || buf[1] == '.')
4165 continue;
4166 for (cp = buf; *cp; cp++)
4167 if (*cp == '\t')
4168 *cp = ' ';
4169 if (is_label (buf))
4170 continue;
4171 memset (&the_ins, '\0', sizeof (the_ins));
4172 m68k_ip (&the_ins, buf);
4173 if (the_ins.error)
4174 {
4175 printf ("Error %s in %s\n", the_ins.error, buf);
4176 }
4177 else
4178 {
4179 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
4180 for (n = 0; n < the_ins.numo; n++)
4181 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
4182 printf (" ");
4183 print_the_insn (&the_ins.opcode[0], stdout);
4184 (void) putchar ('\n');
4185 }
4186 for (n = 0; n < strlen (the_ins.args) / 2; n++)
4187 {
4188 if (the_ins.operands[n].error)
4189 {
4190 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
4191 continue;
4192 }
4193 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
4194 if (the_ins.operands[n].b_const)
4195 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
4196 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
4197 if (the_ins.operands[n].b_iadd)
4198 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
4199 (void) putchar ('\n');
a39116f1 4200 }
355afbcd
KR		 4201 }
4202 m68k_ip_end ();
4203 return 0;
fecd2382
RP		 4204}
4205
355afbcd
KR		 4206is_label (str)
4207 char *str;
fecd2382 4208{
355afbcd
KR		 4209 while (*str == ' ')
4210 str++;
4211 while (*str && *str != ' ')
4212 str++;
4213 if (str[-1] == ':' || str[1] == '=')
4214 return 1;
4215 return 0;
fecd2382
RP		 4216}
4217
4218#endif
4219
4220/* Possible states for relaxation:
6d27d3a2 4221
a39116f1
RP		 4222 0 0 branch offset byte (bra, etc)
4223 0 1 word
4224 0 2 long
6d27d3a2 4225
a39116f1
RP		 4226 1 0 indexed offsets byte a0@(32,d4:w:1) etc
4227 1 1 word
4228 1 2 long
6d27d3a2 4229
a39116f1
RP		 4230 2 0 two-offset index word-word a0@(32,d4)@(45) etc
4231 2 1 word-long
4232 2 2 long-word
4233 2 3 long-long
6d27d3a2 4234
a39116f1 4235 */
fecd2382 4236
fecd2382
RP		 4237/* We have no need to default values of symbols. */
4238
4239/* ARGSUSED */
4240symbolS *
355afbcd
KR		 4241md_undefined_symbol (name)
4242 char *name;
fecd2382 4243{
355afbcd 4244 return 0;
fecd2382
RP		 4245}
4246
fecd2382 4247/* Round up a section size to the appropriate boundary. */
025b0302 4248valueT
355afbcd
KR		 4249md_section_align (segment, size)
4250 segT segment;
025b0302 4251 valueT size;
fecd2382 4252{
355afbcd 4253 return size; /* Byte alignment is fine */
fecd2382
RP		 4254}
4255
4256/* Exactly what point is a PC-relative offset relative TO?
5f8cb05e
ILT		 4257 On the 68k, it is relative to the address of the first extension
4258 word. The difference between the addresses of the offset and the
4259 first extension word is stored in fx_pcrel_adjust. */
fecd2382 4260long
355afbcd
KR		 4261md_pcrel_from (fixP)
4262 fixS *fixP;
fecd2382 4263{
5f8cb05e 4264 return (fixP->fx_where + fixP->fx_frag->fr_address - fixP->fx_pcrel_adjust);
fecd2382
RP		 4265}
4266
49864cfa 4267#ifndef BFD_ASSEMBLER
9ad5755f 4268/*ARGSUSED*/
355afbcd 4269void
9ad5755f
KR		 4270tc_coff_symbol_emit_hook (ignore)
4271 symbolS *ignore;
3ad9ec6a
ILT		 4272{
4273}
4274
355afbcd
KR		 4275int
4276tc_coff_sizemachdep (frag)
4277 fragS *frag;
3ad9ec6a 4278{
355afbcd
KR		 4279 switch (frag->fr_subtype & 0x3)
4280 {
4281 case BYTE:
4282 return 1;
4283 case SHORT:
4284 return 2;
4285 case LONG:
4286 return 4;
4287 default:
4288 abort ();
064ba683 4289 return 0;
355afbcd 4290 }
3ad9ec6a 4291}
49864cfa 4292#endif
355afbcd 4293
fecd2382 4294/* end of tc-m68k.c */
GDB Binutils - Deliverables
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