Commit | Line | Data |
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a87b3269 | 1 | /* tc-m68k.c All the m68020 specific stuff in one convenient, huge, |
fecd2382 | 2 | slow to compile, easy to find file. |
6d27d3a2 | 3 | |
a87b3269 | 4 | Copyright (C) 1987, 1991, 1992 Free Software Foundation, Inc. |
6d27d3a2 | 5 | |
a39116f1 | 6 | This file is part of GAS, the GNU Assembler. |
6d27d3a2 | 7 | |
a39116f1 RP |
8 | GAS is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
6d27d3a2 | 12 | |
a39116f1 RP |
13 | GAS is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
6d27d3a2 | 17 | |
a39116f1 RP |
18 | You should have received a copy of the GNU General Public License |
19 | along with GAS; see the file COPYING. If not, write to | |
20 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
fecd2382 RP |
21 | |
22 | #include <ctype.h> | |
f8701a3f | 23 | #define NO_RELOC 0 |
fecd2382 RP |
24 | #include "as.h" |
25 | ||
26 | #include "obstack.h" | |
27 | ||
a39116f1 | 28 | /* note that this file includes real declarations and thus can only be included by one source file per executable. */ |
e0982afe | 29 | #include "opcode/m68k.h" |
f6e504fe RP |
30 | #ifdef TE_SUN |
31 | /* This variable contains the value to write out at the beginning of | |
32 | the a.out file. The 2<<16 means that this is a 68020 file instead | |
33 | of an old-style 68000 file */ | |
34 | ||
35 | long omagic = 2<<16|OMAGIC; /* Magic byte for header file */ | |
36 | #else | |
37 | long omagic = OMAGIC; | |
38 | #endif | |
fecd2382 RP |
39 | |
40 | /* This array holds the chars that always start a comment. If the | |
41 | pre-processor is disabled, these aren't very useful */ | |
42 | const char comment_chars[] = "|"; | |
43 | ||
44 | /* This array holds the chars that only start a comment at the beginning of | |
45 | a line. If the line seems to have the form '# 123 filename' | |
46 | .line and .file directives will appear in the pre-processed output */ | |
47 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
48 | first line of the input file. This is because the compiler outputs | |
49 | #NO_APP at the beginning of its output. */ | |
50 | /* Also note that comments like this one will always work. */ | |
51 | const char line_comment_chars[] = "#"; | |
52 | ||
53 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
54 | const char EXP_CHARS[] = "eE"; | |
55 | ||
56 | /* Chars that mean this number is a floating point constant */ | |
57 | /* As in 0f12.456 */ | |
58 | /* or 0d1.2345e12 */ | |
59 | ||
60 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; | |
61 | ||
62 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
63 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
64 | but nothing is ideal around here. | |
a39116f1 | 65 | */ |
fecd2382 RP |
66 | |
67 | int md_reloc_size = 8; /* Size of relocation record */ | |
68 | ||
69 | /* Its an arbitrary name: This means I don't approve of it */ | |
70 | /* See flames below */ | |
71 | static struct obstack robyn; | |
72 | ||
73 | #define TAB(x,y) (((x)<<2)+(y)) | |
74 | #define TABTYPE(xy) ((xy) >> 2) | |
75 | #define BYTE 0 | |
76 | #define SHORT 1 | |
77 | #define LONG 2 | |
78 | #define SZ_UNDEF 3 | |
79 | ||
80 | #define BRANCH 1 | |
81 | #define FBRANCH 2 | |
82 | #define PCREL 3 | |
83 | #define BCC68000 4 | |
84 | #define DBCC 5 | |
85 | #define PCLEA 6 | |
86 | ||
f6e504fe | 87 | /* Operands we can parse: (And associated modes) |
6d27d3a2 | 88 | |
a39116f1 RP |
89 | numb: 8 bit num |
90 | numw: 16 bit num | |
91 | numl: 32 bit num | |
92 | dreg: data reg 0-7 | |
93 | reg: address or data register | |
94 | areg: address register | |
95 | apc: address register, PC, ZPC or empty string | |
96 | num: 16 or 32 bit num | |
97 | num2: like num | |
98 | sz: w or l if omitted, l assumed | |
99 | scale: 1 2 4 or 8 if omitted, 1 assumed | |
6d27d3a2 | 100 | |
a39116f1 RP |
101 | 7.4 IMMED #num --> NUM |
102 | 0.? DREG dreg --> dreg | |
103 | 1.? AREG areg --> areg | |
104 | 2.? AINDR areg@ --> *(areg) | |
105 | 3.? AINC areg@+ --> *(areg++) | |
106 | 4.? ADEC areg@- --> *(--areg) | |
107 | 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here | |
108 | 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale) | |
109 | 6.? AINDX apc@(reg:sz:scale) --> same, with num=0 | |
110 | 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale) | |
111 | 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0 | |
112 | 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg) | |
113 | 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2) | |
114 | 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0 | |
115 | 7.0 ABSL num:sz --> *(num) | |
116 | num --> *(num) (sz L assumed) | |
117 | *** MSCR otherreg --> Magic | |
118 | With -l option | |
119 | 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still | |
c50140c8 | 120 | ?.? DINDR dreg@ --> (dreg) -- cas2 only |
6d27d3a2 | 121 | |
a39116f1 RP |
122 | examples: |
123 | #foo #0x35 #12 | |
124 | d2 | |
125 | a4 | |
126 | a3@ | |
127 | a5@+ | |
128 | a6@- | |
129 | a2@(12) pc@(14) | |
130 | a1@(5,d2:w:1) @(45,d6:l:4) | |
131 | pc@(a2) @(d4) | |
132 | etc . . . | |
6d27d3a2 KR |
133 | |
134 | ||
a39116f1 RP |
135 | #name@(numw) -->turn into PC rel mode |
136 | apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale) | |
6d27d3a2 | 137 | |
a39116f1 | 138 | */ |
f6e504fe RP |
139 | |
140 | enum operand_type { | |
f8701a3f SC |
141 | IMMED = 1, |
142 | DREG, | |
143 | AREG, | |
144 | AINDR, | |
145 | ADEC, | |
146 | AINC, | |
147 | AOFF, | |
148 | AINDX, | |
149 | APODX, | |
150 | AMIND, | |
151 | APRDX, | |
152 | ABSL, | |
153 | MSCR, | |
154 | REGLST, | |
c50140c8 | 155 | DINDR |
f6e504fe RP |
156 | }; |
157 | ||
158 | ||
fecd2382 | 159 | struct m68k_exp { |
f8701a3f SC |
160 | char *e_beg; |
161 | char *e_end; | |
162 | expressionS e_exp; | |
163 | short e_siz; /* 0== default 1==short/byte 2==word 3==long */ | |
fecd2382 RP |
164 | }; |
165 | ||
7c15cbe8 RP |
166 | /* DATA and ADDR have to be contiguous, so that reg-DATA gives 0-7==data reg, |
167 | 8-15==addr reg for operands that take both types */ | |
168 | ||
169 | enum _register { | |
f8701a3f SC |
170 | DATA = 1, /* 1- 8 == data registers 0-7 */ |
171 | DATA0 = DATA, | |
172 | DATA1, | |
173 | DATA2, | |
174 | DATA3, | |
175 | DATA4, | |
176 | DATA5, | |
177 | DATA6, | |
178 | DATA7, | |
6d27d3a2 | 179 | |
f8701a3f SC |
180 | ADDR, |
181 | ADDR0 = ADDR, | |
182 | ADDR1, | |
183 | ADDR2, | |
184 | ADDR3, | |
185 | ADDR4, | |
186 | ADDR5, | |
187 | ADDR6, | |
188 | ADDR7, | |
6d27d3a2 | 189 | |
f8701a3f SC |
190 | /* Note that COPNUM==processor #1 -- COPNUM+7==#8, which stores as 000 */ |
191 | /* I think. . . */ | |
6d27d3a2 | 192 | |
f8701a3f | 193 | SP = ADDR7, |
6d27d3a2 | 194 | |
f8701a3f SC |
195 | FPREG, /* Eight FP registers */ |
196 | FP0 = FPREG, | |
197 | FP1, | |
198 | FP2, | |
199 | FP3, | |
200 | FP4, | |
201 | FP5, | |
202 | FP6, | |
203 | FP7, | |
204 | COPNUM = (FPREG+8), /* Co-processor #1-#8 */ | |
205 | COP0 = COPNUM, | |
206 | COP1, | |
207 | COP2, | |
208 | COP3, | |
209 | COP4, | |
210 | COP5, | |
211 | COP6, | |
212 | COP7, | |
213 | PC, /* Program counter */ | |
214 | ZPC, /* Hack for Program space, but 0 addressing */ | |
215 | SR, /* Status Reg */ | |
216 | CCR, /* Condition code Reg */ | |
6d27d3a2 | 217 | |
f8701a3f SC |
218 | /* These have to be in order for the movec instruction to work. */ |
219 | USP, /* User Stack Pointer */ | |
220 | ISP, /* Interrupt stack pointer */ | |
221 | SFC, | |
222 | DFC, | |
223 | CACR, | |
224 | VBR, | |
225 | CAAR, | |
226 | MSP, | |
227 | ITT0, | |
228 | ITT1, | |
229 | DTT0, | |
230 | DTT1, | |
231 | MMUSR, | |
232 | TC, | |
233 | SRP, | |
234 | URP, | |
235 | /* end of movec ordering constraints */ | |
6d27d3a2 | 236 | |
f8701a3f SC |
237 | FPI, |
238 | FPS, | |
239 | FPC, | |
6d27d3a2 | 240 | |
4134a793 | 241 | DRP, /* 68851 or 68030 MMU regs */ |
f8701a3f SC |
242 | CRP, |
243 | CAL, | |
244 | VAL, | |
245 | SCC, | |
246 | AC, | |
247 | BAD, | |
248 | BAD0 = BAD, | |
249 | BAD1, | |
250 | BAD2, | |
251 | BAD3, | |
252 | BAD4, | |
253 | BAD5, | |
254 | BAD6, | |
255 | BAD7, | |
256 | BAC, | |
257 | BAC0 = BAC, | |
258 | BAC1, | |
259 | BAC2, | |
260 | BAC3, | |
261 | BAC4, | |
262 | BAC5, | |
263 | BAC6, | |
264 | BAC7, | |
4134a793 KR |
265 | PSR, /* aka MMUSR on 68030 (but not MMUSR on 68040) |
266 | and ACUSR on 68ec030 */ | |
f8701a3f | 267 | PCSR, |
6d27d3a2 | 268 | |
f8701a3f SC |
269 | IC, /* instruction cache token */ |
270 | DC, /* data cache token */ | |
271 | NC, /* no cache token */ | |
272 | BC, /* both caches token */ | |
6d27d3a2 | 273 | |
4134a793 KR |
274 | TT0, /* 68030 access control unit regs */ |
275 | TT1, | |
7c15cbe8 RP |
276 | }; |
277 | ||
fecd2382 RP |
278 | /* Internal form of an operand. */ |
279 | struct m68k_op { | |
f8701a3f SC |
280 | char *error; /* Couldn't parse it */ |
281 | enum operand_type mode; /* What mode this instruction is in. */ | |
282 | enum _register reg; /* Base register */ | |
283 | struct m68k_exp *con1; | |
284 | int ireg; /* Index register */ | |
285 | int isiz; /* 0==unspec 1==byte(?) 2==short 3==long */ | |
286 | int imul; /* Multipy ireg by this (1,2,4,or 8) */ | |
287 | struct m68k_exp *con2; | |
fecd2382 RP |
288 | }; |
289 | ||
290 | /* internal form of a 68020 instruction */ | |
7c15cbe8 | 291 | struct m68k_it { |
f8701a3f SC |
292 | char *error; |
293 | char *args; /* list of opcode info */ | |
294 | int numargs; | |
6d27d3a2 | 295 | |
f8701a3f SC |
296 | int numo; /* Number of shorts in opcode */ |
297 | short opcode[11]; | |
6d27d3a2 | 298 | |
f8701a3f | 299 | struct m68k_op operands[6]; |
6d27d3a2 | 300 | |
f8701a3f SC |
301 | int nexp; /* number of exprs in use */ |
302 | struct m68k_exp exprs[4]; | |
6d27d3a2 | 303 | |
f8701a3f SC |
304 | int nfrag; /* Number of frags we have to produce */ |
305 | struct { | |
306 | int fragoff; /* Where in the current opcode[] the frag ends */ | |
307 | symbolS *fadd; | |
308 | long foff; | |
309 | int fragty; | |
310 | } fragb[4]; | |
6d27d3a2 | 311 | |
f8701a3f SC |
312 | int nrel; /* Num of reloc strucs in use */ |
313 | struct { | |
314 | int n; | |
315 | symbolS *add, | |
316 | *sub; | |
317 | long off; | |
318 | char wid; | |
319 | char pcrel; | |
320 | } reloc[5]; /* Five is enough??? */ | |
fecd2382 RP |
321 | }; |
322 | ||
865a2edf MT |
323 | #define cpu_of_arch(x) ((x) & m68000up) |
324 | #define float_of_arch(x) ((x) & mfloat) | |
325 | #define mmu_of_arch(x) ((x) & mmmu) | |
326 | ||
7c15cbe8 | 327 | static struct m68k_it the_ins; /* the instruction being assembled */ |
fecd2382 | 328 | |
7c15cbe8 | 329 | /* Macros for adding things to the m68k_it struct */ |
fecd2382 RP |
330 | |
331 | #define addword(w) the_ins.opcode[the_ins.numo++]=(w) | |
332 | ||
333 | /* Like addword, but goes BEFORE general operands */ | |
334 | #define insop(w) {int z;\ | |
a39116f1 RP |
335 | for(z=the_ins.numo;z>opcode->m_codenum;--z)\ |
336 | the_ins.opcode[z]=the_ins.opcode[z-1];\ | |
337 | for(z=0;z<the_ins.nrel;z++)\ | |
338 | the_ins.reloc[z].n+=2;\ | |
339 | the_ins.opcode[opcode->m_codenum]=w;\ | |
340 | the_ins.numo++;\ | |
f8701a3f | 341 | } |
fecd2382 RP |
342 | |
343 | ||
344 | #define add_exp(beg,end) (\ | |
a39116f1 RP |
345 | the_ins.exprs[the_ins.nexp].e_beg=beg,\ |
346 | the_ins.exprs[the_ins.nexp].e_end=end,\ | |
347 | &the_ins.exprs[the_ins.nexp++]\ | |
348 | ) | |
fecd2382 RP |
349 | |
350 | ||
351 | /* The numo+1 kludge is so we can hit the low order byte of the prev word. Blecch*/ | |
352 | #define add_fix(width,exp,pc_rel) {\ | |
a39116f1 RP |
353 | the_ins.reloc[the_ins.nrel].n= ((width)=='B') ? (the_ins.numo*2-1) : \ |
354 | (((width)=='b') ? ((the_ins.numo-1)*2) : (the_ins.numo*2));\ | |
355 | the_ins.reloc[the_ins.nrel].add=adds((exp));\ | |
356 | the_ins.reloc[the_ins.nrel].sub=subs((exp));\ | |
357 | the_ins.reloc[the_ins.nrel].off=offs((exp));\ | |
358 | the_ins.reloc[the_ins.nrel].wid=width;\ | |
359 | the_ins.reloc[the_ins.nrel++].pcrel=pc_rel;\ | |
f8701a3f | 360 | } |
fecd2382 RP |
361 | |
362 | #define add_frag(add,off,type) {\ | |
a39116f1 RP |
363 | the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;\ |
364 | the_ins.fragb[the_ins.nfrag].fadd=add;\ | |
365 | the_ins.fragb[the_ins.nfrag].foff=off;\ | |
366 | the_ins.fragb[the_ins.nfrag++].fragty=type;\ | |
f8701a3f | 367 | } |
fecd2382 RP |
368 | |
369 | #define isvar(exp) ((exp) && (adds(exp) || subs(exp))) | |
370 | ||
371 | #define seg(exp) ((exp)->e_exp.X_seg) | |
372 | #define adds(exp) ((exp)->e_exp.X_add_symbol) | |
373 | #define subs(exp) ((exp)->e_exp.X_subtract_symbol) | |
374 | #define offs(exp) ((exp)->e_exp.X_add_number) | |
375 | ||
376 | ||
7c15cbe8 | 377 | struct m68k_incant { |
f8701a3f SC |
378 | char *m_operands; |
379 | unsigned long m_opcode; | |
380 | short m_opnum; | |
381 | short m_codenum; | |
382 | enum m68k_architecture m_arch; | |
383 | struct m68k_incant *m_next; | |
fecd2382 RP |
384 | }; |
385 | ||
386 | #define getone(x) ((((x)->m_opcode)>>16)&0xffff) | |
387 | #define gettwo(x) (((x)->m_opcode)&0xffff) | |
388 | ||
389 | ||
a87b3269 | 390 | #if __STDC__ == 1 |
fecd2382 RP |
391 | |
392 | static char *crack_operand(char *str, struct m68k_op *opP); | |
393 | static int get_num(struct m68k_exp *exp, int ok); | |
394 | static int get_regs(int i, char *str, struct m68k_op *opP); | |
395 | static int reverse_16_bits(int in); | |
396 | static int reverse_8_bits(int in); | |
397 | static int try_index(char **s, struct m68k_op *opP); | |
398 | static void install_gen_operand(int mode, int val); | |
399 | static void install_operand(int mode, int val); | |
a933d598 | 400 | void s_bss(void); |
fecd2382 RP |
401 | static void s_data1(void); |
402 | static void s_data2(void); | |
403 | static void s_even(void); | |
404 | static void s_proc(void); | |
405 | ||
a87b3269 | 406 | #else /* not __STDC__ */ |
fecd2382 RP |
407 | |
408 | static char *crack_operand(); | |
409 | static int get_num(); | |
410 | static int get_regs(); | |
411 | static int reverse_16_bits(); | |
412 | static int reverse_8_bits(); | |
413 | static int try_index(); | |
414 | static void install_gen_operand(); | |
415 | static void install_operand(); | |
9e43698e SC |
416 | void s_bss(); |
417 | void s_align_bytes(); | |
fecd2382 RP |
418 | static void s_data1(); |
419 | static void s_data2(); | |
420 | static void s_even(); | |
421 | static void s_proc(); | |
422 | ||
a87b3269 | 423 | #endif /* not __STDC__ */ |
fecd2382 | 424 | |
865a2edf | 425 | static enum m68k_architecture current_architecture = 0; |
7c15cbe8 | 426 | |
fecd2382 RP |
427 | /* BCC68000 is for patching in an extra jmp instruction for long offsets |
428 | on the 68000. The 68000 doesn't support long branches with branchs */ | |
429 | ||
430 | /* This table desribes how you change sizes for the various types of variable | |
431 | size expressions. This version only supports two kinds. */ | |
432 | ||
433 | /* Note that calls to frag_var need to specify the maximum expansion needed */ | |
434 | /* This is currently 10 bytes for DBCC */ | |
435 | ||
436 | /* The fields are: | |
a39116f1 RP |
437 | How far Forward this mode will reach: |
438 | How far Backward this mode will reach: | |
439 | How many bytes this mode will add to the size of the frag | |
440 | Which mode to go to if the offset won't fit in this one | |
441 | */ | |
fecd2382 | 442 | const relax_typeS |
a39116f1 | 443 | md_relax_table[] = { |
f8701a3f SC |
444 | { 1, 1, 0, 0 }, /* First entries aren't used */ |
445 | { 1, 1, 0, 0 }, /* For no good reason except */ | |
446 | { 1, 1, 0, 0 }, /* that the VAX doesn't either */ | |
447 | { 1, 1, 0, 0 }, | |
6d27d3a2 | 448 | |
f8701a3f SC |
449 | { (127), (-128), 0, TAB(BRANCH,SHORT)}, |
450 | { (32767), (-32768), 2, TAB(BRANCH,LONG) }, | |
451 | { 0, 0, 4, 0 }, | |
452 | { 1, 1, 0, 0 }, | |
6d27d3a2 | 453 | |
f8701a3f SC |
454 | { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */ |
455 | { (32767), (-32768), 2, TAB(FBRANCH,LONG)}, | |
456 | { 0, 0, 4, 0 }, | |
457 | { 1, 1, 0, 0 }, | |
6d27d3a2 | 458 | |
f8701a3f SC |
459 | { 1, 1, 0, 0 }, /* PCREL doesn't come BYTE */ |
460 | { (32767), (-32768), 2, TAB(PCREL,LONG)}, | |
461 | { 0, 0, 4, 0 }, | |
462 | { 1, 1, 0, 0 }, | |
6d27d3a2 | 463 | |
f8701a3f SC |
464 | { (127), (-128), 0, TAB(BCC68000,SHORT)}, |
465 | { (32767), (-32768), 2, TAB(BCC68000,LONG) }, | |
466 | { 0, 0, 6, 0 }, /* jmp long space */ | |
467 | { 1, 1, 0, 0 }, | |
6d27d3a2 | 468 | |
f8701a3f SC |
469 | { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */ |
470 | { (32767), (-32768), 2, TAB(DBCC,LONG) }, | |
471 | { 0, 0, 10, 0 }, /* bra/jmp long space */ | |
472 | { 1, 1, 0, 0 }, | |
6d27d3a2 | 473 | |
f8701a3f SC |
474 | { 1, 1, 0, 0 }, /* PCLEA doesn't come BYTE */ |
475 | { 32767, -32768, 2, TAB(PCLEA,LONG) }, | |
476 | { 0, 0, 6, 0 }, | |
477 | { 1, 1, 0, 0 }, | |
6d27d3a2 | 478 | |
f8701a3f | 479 | }; |
fecd2382 RP |
480 | |
481 | /* These are the machine dependent pseudo-ops. These are included so | |
482 | the assembler can work on the output from the SUN C compiler, which | |
483 | generates these. | |
a39116f1 | 484 | */ |
fecd2382 RP |
485 | |
486 | /* This table describes all the machine specific pseudo-ops the assembler | |
487 | has to support. The fields are: | |
a39116f1 RP |
488 | pseudo-op name without dot |
489 | function to call to execute this pseudo-op | |
490 | Integer arg to pass to the function | |
491 | */ | |
fecd2382 | 492 | const pseudo_typeS md_pseudo_table[] = { |
f8701a3f SC |
493 | { "data1", s_data1, 0 }, |
494 | { "data2", s_data2, 0 }, | |
495 | { "bss", s_bss, 0 }, | |
496 | { "even", s_even, 0 }, | |
497 | { "skip", s_space, 0 }, | |
498 | { "proc", s_proc, 0 }, | |
bec66218 | 499 | #ifdef TE_SUN3 |
9e43698e | 500 | { "align", s_align_bytes, 0 }, |
bec66218 | 501 | #endif |
f8701a3f | 502 | { 0, 0, 0 } |
fecd2382 RP |
503 | }; |
504 | ||
505 | ||
506 | /* #define isbyte(x) ((x)>=-128 && (x)<=127) */ | |
507 | /* #define isword(x) ((x)>=-32768 && (x)<=32767) */ | |
508 | ||
509 | #define issbyte(x) ((x)>=-128 && (x)<=127) | |
510 | #define isubyte(x) ((x)>=0 && (x)<=255) | |
511 | #define issword(x) ((x)>=-32768 && (x)<=32767) | |
512 | #define isuword(x) ((x)>=0 && (x)<=65535) | |
f8701a3f | 513 | |
fecd2382 RP |
514 | #define isbyte(x) ((x)>=-128 && (x)<=255) |
515 | #define isword(x) ((x)>=-32768 && (x)<=65535) | |
516 | #define islong(x) (1) | |
f8701a3f SC |
517 | |
518 | extern char *input_line_pointer; | |
fecd2382 | 519 | |
7c15cbe8 | 520 | enum { |
f8701a3f SC |
521 | FAIL = 0, |
522 | OK = 1, | |
7c15cbe8 | 523 | }; |
fecd2382 RP |
524 | |
525 | /* JF these tables here are for speed at the expense of size */ | |
526 | /* You can replace them with the #if 0 versions if you really | |
527 | need space and don't mind it running a bit slower */ | |
528 | ||
529 | static char mklower_table[256]; | |
530 | #define mklower(c) (mklower_table[(unsigned char)(c)]) | |
f8701a3f | 531 | static char notend_table[256]; |
fecd2382 RP |
532 | static char alt_notend_table[256]; |
533 | #define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\ | |
a39116f1 | 534 | alt_notend_table[(unsigned char)(s[1])]))) |
fecd2382 RP |
535 | |
536 | #if 0 | |
537 | #define mklower(c) (isupper(c) ? tolower(c) : c) | |
538 | #endif | |
f8701a3f SC |
539 | |
540 | ||
541 | /* JF modified this to handle cases where the first part of a symbol name | |
542 | looks like a register */ | |
543 | ||
544 | /* | |
545 | * m68k_reg_parse() := if it looks like a register, return it's token & | |
546 | * advance the pointer. | |
547 | */ | |
548 | ||
549 | enum _register m68k_reg_parse(ccp) | |
fecd2382 RP |
550 | register char **ccp; |
551 | { | |
f8701a3f SC |
552 | char *start = *ccp; |
553 | ||
6d27d3a2 | 554 | if (isalpha(*start) && is_name_beginner(*start)) |
f8701a3f SC |
555 | { |
556 | char c; | |
557 | char *p = start; | |
558 | symbolS *symbolP; | |
6d27d3a2 | 559 | |
f8701a3f SC |
560 | while (is_part_of_name(c = *p++)) |
561 | ; | |
562 | * -- p = 0; | |
563 | symbolP = symbol_find(start); | |
564 | *p = c; | |
565 | ||
6d27d3a2 | 566 | if (symbolP && S_GET_SEGMENT(symbolP) == SEG_REGISTER) |
a39116f1 | 567 | { |
f8701a3f SC |
568 | *ccp = p; |
569 | return S_GET_VALUE(symbolP); | |
a39116f1 | 570 | } |
f8701a3f SC |
571 | } |
572 | return FAIL; | |
573 | ||
574 | ||
fecd2382 RP |
575 | } |
576 | ||
577 | #define SKIP_WHITE() { str++; if(*str==' ') str++;} | |
578 | ||
7c15cbe8 RP |
579 | /* |
580 | * m68k_ip_op := '#' + <anything> | |
581 | * | <register> + range_sep + get_regs | |
582 | * ; | |
6d27d3a2 | 583 | * |
7c15cbe8 RP |
584 | * range_sep := '/' | '-' ; |
585 | * | |
586 | * SKIP_WHITE := <empty> | ' ' ; | |
587 | * | |
588 | */ | |
589 | ||
fecd2382 | 590 | int |
a39116f1 | 591 | m68k_ip_op(str,opP) |
fecd2382 RP |
592 | char *str; |
593 | register struct m68k_op *opP; | |
594 | { | |
f8701a3f SC |
595 | char *strend; |
596 | long i; | |
597 | char *parse_index(); | |
a933d598 | 598 | int needp; |
f8701a3f SC |
599 | if (*str==' ') { |
600 | str++; | |
601 | } /* Find the beginning of the string */ | |
6d27d3a2 | 602 | |
f8701a3f SC |
603 | if(!*str) { |
604 | opP->error="Missing operand"; | |
fecd2382 | 605 | return FAIL; |
f8701a3f | 606 | } /* Out of gas */ |
6d27d3a2 | 607 | |
f8701a3f | 608 | for(strend = str; *strend; strend++) ;; |
6d27d3a2 | 609 | |
f8701a3f | 610 | --strend; |
6d27d3a2 | 611 | |
f8701a3f SC |
612 | if(*str=='#') { |
613 | str++; | |
614 | opP->con1=add_exp(str,strend); | |
615 | opP->mode=IMMED; | |
616 | return OK; | |
617 | } /* Guess what: A constant. Shar and enjoy */ | |
6d27d3a2 | 618 | |
f8701a3f | 619 | i = m68k_reg_parse(&str); |
6d27d3a2 | 620 | |
f8701a3f | 621 | /* is a register, is exactly a register, and is followed by '@' */ |
6d27d3a2 | 622 | |
f8701a3f SC |
623 | if((i==FAIL || *str!='\0') && *str!='@') { |
624 | char *stmp; | |
6d27d3a2 | 625 | |
f8701a3f SC |
626 | if(i!=FAIL && (*str=='/' || *str=='-')) { |
627 | opP->mode=REGLST; | |
628 | return(get_regs(i,str,opP)); | |
629 | } | |
630 | if ((stmp=strchr(str,'@')) != '\0') { | |
631 | opP->con1=add_exp(str,stmp-1); | |
632 | if(stmp==strend) { | |
633 | opP->mode=AINDX; | |
634 | return(OK); | |
635 | } | |
6d27d3a2 | 636 | |
f8701a3f SC |
637 | if ((current_architecture & m68020up) == 0) { |
638 | return(FAIL); | |
639 | } /* if target is not a '20 or better */ | |
6d27d3a2 | 640 | |
f8701a3f SC |
641 | stmp++; |
642 | if(*stmp++!='(' || *strend--!=')') { | |
643 | opP->error="Malformed operand"; | |
644 | return(FAIL); | |
645 | } | |
646 | i=try_index(&stmp,opP); | |
647 | opP->con2=add_exp(stmp,strend); | |
6d27d3a2 | 648 | |
f8701a3f SC |
649 | if (i == FAIL) { |
650 | opP->mode=AMIND; | |
651 | } else { | |
652 | opP->mode=APODX; | |
653 | } | |
654 | return(OK); | |
655 | } /* if there's an '@' */ | |
656 | opP->mode = ABSL; | |
657 | opP->con1 = add_exp(str,strend); | |
658 | return(OK); | |
659 | } /* not a register, not exactly a register, or no '@' */ | |
6d27d3a2 | 660 | |
f8701a3f | 661 | opP->reg=i; |
6d27d3a2 | 662 | |
f8701a3f SC |
663 | if (*str=='\0') { |
664 | if(i>=DATA+0 && i<=DATA+7) | |
665 | opP->mode=DREG; | |
666 | else if(i>=ADDR+0 && i<=ADDR+7) | |
667 | opP->mode=AREG; | |
668 | else | |
669 | opP->mode=MSCR; | |
670 | return OK; | |
fecd2382 | 671 | } |
6d27d3a2 | 672 | |
c50140c8 ILT |
673 | /* Can't indirect off non address regs, but Dx@ is OK for cas2 */ |
674 | if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL | |
675 | && (str[1] != '\0' || i<DATA+0 || i>DATA+7)) { | |
f8701a3f | 676 | opP->error="Invalid indirect register"; |
a39116f1 | 677 | return FAIL; |
fecd2382 | 678 | } |
f8701a3f | 679 | know(*str == '@'); |
6d27d3a2 | 680 | |
f8701a3f SC |
681 | str++; |
682 | switch(*str) { | |
683 | case '\0': | |
c50140c8 ILT |
684 | if (i < DATA + 0 || i > DATA + 7) |
685 | opP->mode=AINDR; | |
686 | else | |
687 | opP->mode=DINDR; | |
f8701a3f SC |
688 | return OK; |
689 | case '-': | |
690 | opP->mode=ADEC; | |
691 | return OK; | |
692 | case '+': | |
693 | opP->mode=AINC; | |
694 | return OK; | |
695 | case '(': | |
696 | str++; | |
697 | break; | |
698 | default: | |
699 | opP->error="Junk after indirect"; | |
700 | return FAIL; | |
fecd2382 | 701 | } |
f8701a3f SC |
702 | /* Some kind of indexing involved. Lets find out how bad it is */ |
703 | i=try_index(&str,opP); | |
704 | /* Didn't start with an index reg, maybe its offset or offset,reg */ | |
705 | if(i==FAIL) { | |
706 | char *beg_str; | |
6d27d3a2 | 707 | |
f8701a3f SC |
708 | beg_str=str; |
709 | for(i=1;i;) { | |
710 | switch(*str++) { | |
711 | case '\0': | |
712 | opP->error="Missing )"; | |
713 | return FAIL; | |
714 | case ',': i=0; break; | |
715 | case '(': i++; break; | |
716 | case ')': --i; break; | |
717 | } | |
718 | } | |
719 | /* if(str[-3]==':') { | |
720 | int siz; | |
6d27d3a2 | 721 | |
f8701a3f SC |
722 | switch(str[-2]) { |
723 | case 'b': | |
724 | case 'B': | |
725 | siz=1; | |
726 | break; | |
727 | case 'w': | |
728 | case 'W': | |
729 | siz=2; | |
730 | break; | |
731 | case 'l': | |
732 | case 'L': | |
733 | siz=3; | |
734 | break; | |
735 | default: | |
736 | opP->error="Specified size isn't :w or :l"; | |
737 | return FAIL; | |
738 | } | |
739 | opP->con1=add_exp(beg_str,str-4); | |
740 | opP->con1->e_siz=siz; | |
741 | } else */ | |
742 | opP->con1=add_exp(beg_str,str-2); | |
743 | /* Should be offset,reg */ | |
744 | if(str[-1]==',') { | |
745 | i=try_index(&str,opP); | |
746 | if(i==FAIL) { | |
747 | opP->error="Malformed index reg"; | |
748 | return FAIL; | |
749 | } | |
750 | } | |
751 | } | |
752 | /* We've now got offset) offset,reg) or reg) */ | |
6d27d3a2 | 753 | |
f8701a3f SC |
754 | if (*str == '\0') { |
755 | /* Th-the-thats all folks */ | |
756 | if (opP->reg == FAIL) opP->mode = AINDX; /* Other form of indirect */ | |
757 | else if(opP->ireg == FAIL) opP->mode = AOFF; | |
758 | else opP->mode = AINDX; | |
759 | return(OK); | |
760 | } | |
761 | /* Next thing had better be another @ */ | |
a933d598 SC |
762 | if (*str == '@') { |
763 | if (str[1] == '(') { | |
764 | needp = 1; | |
765 | str+=2; | |
766 | } | |
767 | else { | |
768 | needp = 0; | |
769 | str++; | |
770 | } | |
fecd2382 | 771 | } |
6d27d3a2 | 772 | |
f8701a3f | 773 | if ((current_architecture & m68020up) == 0) { |
a39116f1 | 774 | return(FAIL); |
f8701a3f | 775 | } /* if target is not a '20 or better */ |
6d27d3a2 KR |
776 | |
777 | ||
f8701a3f SC |
778 | if(opP->ireg != FAIL) { |
779 | opP->mode = APRDX; | |
6d27d3a2 | 780 | |
f8701a3f SC |
781 | i = try_index(&str, opP); |
782 | if (i != FAIL) { | |
783 | opP->error = "Two index registers! not allowed!"; | |
784 | return(FAIL); | |
785 | } | |
865a2edf | 786 | } else { |
f8701a3f | 787 | i = try_index(&str, opP); |
865a2edf | 788 | } |
6d27d3a2 | 789 | |
f8701a3f SC |
790 | if (i == FAIL) { |
791 | char *beg_str; | |
6d27d3a2 | 792 | |
f8701a3f | 793 | beg_str = str; |
6d27d3a2 | 794 | |
f8701a3f SC |
795 | for (i = 1; i; ) { |
796 | switch(*str++) { | |
797 | case '\0': | |
a933d598 | 798 | if (needp) |
f8701a3f SC |
799 | opP->error="Missing )"; |
800 | return(FAIL); | |
a933d598 | 801 | break; |
f8701a3f SC |
802 | case ',': i=0; break; |
803 | case '(': i++; break; | |
804 | case ')': --i; break; | |
805 | } | |
806 | } | |
6d27d3a2 | 807 | |
f8701a3f | 808 | opP->con2=add_exp(beg_str,str-2); |
6d27d3a2 | 809 | |
f8701a3f SC |
810 | if (str[-1] == ',') { |
811 | if (opP->ireg != FAIL) { | |
812 | opP->error = "Can't have two index regs"; | |
813 | return(FAIL); | |
814 | } | |
6d27d3a2 | 815 | |
f8701a3f | 816 | i = try_index(&str, opP); |
6d27d3a2 | 817 | |
f8701a3f SC |
818 | if (i == FAIL) { |
819 | opP->error = "malformed index reg"; | |
820 | return(FAIL); | |
821 | } | |
6d27d3a2 | 822 | |
f8701a3f SC |
823 | opP->mode = APODX; |
824 | } else if (opP->ireg != FAIL) { | |
825 | opP->mode = APRDX; | |
826 | } else { | |
827 | opP->mode = AMIND; | |
828 | } | |
829 | } else { | |
830 | opP->mode = APODX; | |
831 | } | |
6d27d3a2 | 832 | |
f8701a3f SC |
833 | if(*str!='\0') { |
834 | opP->error="Junk after indirect"; | |
835 | return FAIL; | |
836 | } | |
837 | return(OK); | |
a39116f1 | 838 | } /* m68k_ip_op() */ |
fecd2382 | 839 | |
7c15cbe8 | 840 | /* |
6d27d3a2 | 841 | * |
7c15cbe8 RP |
842 | * try_index := data_or_address_register + ')' + SKIP_W |
843 | * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W | |
844 | * | |
845 | * multiplier := <empty> | |
846 | * | ':' + multiplier_number | |
847 | * ; | |
848 | * | |
849 | * multiplier_number := '1' | '2' | '4' | '8' ; | |
850 | * | |
851 | * size_spec := 'l' | 'L' | 'w' | 'W' ; | |
852 | * | |
853 | * SKIP_W := <empty> | ' ' ; | |
854 | * | |
855 | */ | |
856 | ||
fecd2382 | 857 | static int try_index(s,opP) |
f8701a3f SC |
858 | char **s; |
859 | struct m68k_op *opP; | |
fecd2382 | 860 | { |
f8701a3f SC |
861 | register int i; |
862 | char *ss; | |
7c15cbe8 | 863 | #define SKIP_W() { ss++; if (*ss==' ') ss++;} |
6d27d3a2 | 864 | |
f8701a3f SC |
865 | ss= *s; |
866 | /* SKIP_W(); */ | |
867 | i=m68k_reg_parse(&ss); | |
868 | if(!(i>=DATA+0 && i<=ADDR+7)) { /* if i is not DATA or ADDR reg */ | |
869 | *s=ss; | |
870 | return FAIL; | |
871 | } | |
872 | opP->ireg=i; | |
873 | /* SKIP_W(); */ | |
874 | if(*ss==')') { | |
875 | opP->isiz=0; | |
876 | opP->imul=1; | |
877 | SKIP_W(); | |
878 | *s=ss; | |
879 | return OK; | |
880 | } | |
881 | if(*ss!=':') { | |
882 | opP->error="Missing : in index register"; | |
883 | *s=ss; | |
884 | return FAIL; | |
885 | } | |
fecd2382 RP |
886 | SKIP_W(); |
887 | switch(*ss) { | |
f8701a3f SC |
888 | case 'w': |
889 | case 'W': | |
890 | opP->isiz=2; | |
891 | break; | |
892 | case 'l': | |
893 | case 'L': | |
894 | opP->isiz=3; | |
895 | break; | |
fecd2382 | 896 | default: |
f8701a3f SC |
897 | opP->error="Index register size spec not :w or :l"; |
898 | *s=ss; | |
899 | return FAIL; | |
900 | } | |
901 | SKIP_W(); | |
902 | if(*ss==':') { | |
903 | SKIP_W(); | |
904 | switch(*ss) { | |
905 | case '1': | |
906 | case '2': | |
907 | case '4': | |
908 | case '8': | |
934afcd4 JG |
909 | if (cpu_of_arch(current_architecture) < m68020) { |
910 | opP->error="no index scaling in pre-68020's"; | |
911 | *s=ss; | |
912 | return FAIL; | |
913 | } | |
f8701a3f SC |
914 | opP->imul= *ss-'0'; |
915 | break; | |
916 | default: | |
917 | opP->error="index multiplier not 1, 2, 4 or 8"; | |
918 | *s=ss; | |
919 | return FAIL; | |
920 | } | |
921 | SKIP_W(); | |
922 | } else opP->imul=1; | |
923 | if(*ss!=')') { | |
924 | opP->error="Missing )"; | |
925 | *s=ss; | |
926 | return FAIL; | |
fecd2382 RP |
927 | } |
928 | SKIP_W(); | |
929 | *s=ss; | |
f8701a3f | 930 | return OK; |
fecd2382 RP |
931 | } /* try_index() */ |
932 | ||
933 | #ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */ | |
934 | main() | |
935 | { | |
f8701a3f SC |
936 | char buf[128]; |
937 | struct m68k_op thark; | |
6d27d3a2 | 938 | |
f8701a3f SC |
939 | for(;;) { |
940 | if(!gets(buf)) | |
941 | break; | |
942 | memset(&thark, '\0', sizeof(thark)); | |
943 | if(!m68k_ip_op(buf,&thark)) printf("FAIL:"); | |
944 | if(thark.error) | |
945 | printf("op1 error %s in %s\n",thark.error,buf); | |
946 | printf("mode %d, reg %d, ",thark.mode,thark.reg); | |
947 | if(thark.b_const) | |
948 | printf("Constant: '%.*s',",1+thark.e_const-thark.b_const,thark.b_const); | |
949 | printf("ireg %d, isiz %d, imul %d ",thark.ireg,thark.isiz,thark.imul); | |
950 | if(thark.b_iadd) | |
951 | printf("Iadd: '%.*s'",1+thark.e_iadd-thark.b_iadd,thark.b_iadd); | |
952 | printf("\n"); | |
953 | } | |
954 | exit(0); | |
fecd2382 RP |
955 | } |
956 | ||
957 | #endif | |
958 | ||
959 | ||
960 | static struct hash_control* op_hash = NULL; /* handle of the OPCODE hash table | |
a39116f1 RP |
961 | NULL means any use before m68k_ip_begin() |
962 | will crash */ | |
fecd2382 RP |
963 | |
964 | \f | |
965 | /* | |
7c15cbe8 | 966 | * m 6 8 k _ i p ( ) |
fecd2382 RP |
967 | * |
968 | * This converts a string into a 68k instruction. | |
969 | * The string must be a bare single instruction in sun format | |
970 | * with RMS-style 68020 indirects | |
971 | * (example: ) | |
972 | * | |
973 | * It provides some error messages: at most one fatal error message (which | |
974 | * stops the scan) and at most one warning message for each operand. | |
975 | * The 68k instruction is returned in exploded form, since we have no | |
976 | * knowledge of how you parse (or evaluate) your expressions. | |
977 | * We do however strip off and decode addressing modes and operation | |
978 | * mnemonic. | |
979 | * | |
980 | * This function's value is a string. If it is not "" then an internal | |
981 | * logic error was found: read this code to assign meaning to the string. | |
982 | * No argument string should generate such an error string: | |
983 | * it means a bug in our code, not in the user's text. | |
984 | * | |
7c15cbe8 | 985 | * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using |
fecd2382 RP |
986 | * this function. |
987 | */ | |
988 | ||
989 | /* JF this function no longer returns a useful value. Sorry */ | |
7c15cbe8 | 990 | void m68k_ip (instring) |
6d27d3a2 | 991 | char *instring; |
fecd2382 | 992 | { |
6d27d3a2 KR |
993 | register char *p; |
994 | register struct m68k_op *opP; | |
995 | register struct m68k_incant *opcode; | |
996 | register char *s; | |
997 | register int tmpreg = 0, baseo = 0, outro = 0, nextword; | |
998 | int siz1, siz2; | |
999 | char c; | |
1000 | int losing; | |
1001 | int opsfound; | |
1002 | char *crack_operand(); | |
1003 | LITTLENUM_TYPE words[6]; | |
1004 | LITTLENUM_TYPE *wordp; | |
8be74775 | 1005 | unsigned long ok_arch = 0; |
6d27d3a2 KR |
1006 | |
1007 | if (*instring == ' ') | |
1008 | instring++; /* skip leading whitespace */ | |
1009 | ||
1010 | /* Scan up to end of operation-code, which MUST end in end-of-string | |
1011 | or exactly 1 space. */ | |
1012 | for (p = instring; *p != '\0'; p++) | |
1013 | if (*p == ' ') | |
1014 | break; | |
1015 | ||
1016 | ||
1017 | if (p == instring) { | |
1018 | the_ins.error = "No operator"; | |
1019 | the_ins.opcode[0] = NULL; | |
1020 | /* the_ins.numo=1; */ | |
1021 | return; | |
1022 | } | |
1023 | ||
1024 | /* p now points to the end of the opcode name, probably whitespace. | |
1025 | make sure the name is null terminated by clobbering the whitespace, | |
1026 | look it up in the hash table, then fix it back. */ | |
1027 | c = *p; | |
1028 | *p = '\0'; | |
1029 | opcode = (struct m68k_incant *)hash_find (op_hash, instring); | |
1030 | *p = c; | |
1031 | ||
1032 | if (opcode == NULL) { | |
1033 | the_ins.error = "Unknown operator"; | |
1034 | the_ins.opcode[0] = NULL; | |
1035 | /* the_ins.numo=1; */ | |
1036 | return; | |
1037 | } | |
1038 | ||
1039 | /* found a legitimate opcode, start matching operands */ | |
1040 | while (*p == ' ') ++p; | |
1041 | ||
1042 | for(opP = &the_ins.operands[0]; *p; opP++) { | |
1043 | ||
1044 | p = crack_operand(p, opP); | |
1045 | ||
1046 | if (opP->error) { | |
1047 | the_ins.error=opP->error; | |
1048 | return; | |
1049 | } | |
1050 | } | |
1051 | ||
1052 | opsfound = opP - &the_ins.operands[0]; | |
1053 | ||
1054 | /* This ugly hack is to support the floating pt opcodes in their standard form */ | |
1055 | /* Essentially, we fake a first enty of type COP#1 */ | |
1056 | if (opcode->m_operands[0]=='I') { | |
1057 | int n; | |
1058 | ||
1059 | for(n=opsfound;n>0;--n) | |
1060 | the_ins.operands[n]=the_ins.operands[n-1]; | |
1061 | ||
6d27d3a2 KR |
1062 | memset((char *)(&the_ins.operands[0]), '\0', sizeof(the_ins.operands[0])); |
1063 | the_ins.operands[0].mode=MSCR; | |
1064 | the_ins.operands[0].reg=COPNUM; /* COP #1 */ | |
1065 | opsfound++; | |
1066 | } | |
1067 | ||
1068 | /* We've got the operands. Find an opcode that'll accept them */ | |
1069 | for (losing = 0; ; ) { | |
1070 | /* if we didn't get the right number of ops, | |
1071 | or we have no common model with this pattern | |
1072 | then reject this pattern. */ | |
1073 | ||
1074 | if (opsfound != opcode->m_opnum | |
8be74775 KR |
1075 | || ((opcode->m_arch & current_architecture) == 0)) |
1076 | { | |
1077 | ++losing; | |
1078 | ok_arch |= opcode->m_arch; | |
1079 | } | |
1080 | else { | |
1081 | for (s=opcode->m_operands, opP = &the_ins.operands[0]; *s && !losing; s += 2, opP++) { | |
1082 | /* Warning: this switch is huge! */ | |
1083 | /* I've tried to organize the cases into this order: | |
1084 | non-alpha first, then alpha by letter. lower-case goes directly | |
1085 | before uppercase counterpart. */ | |
1086 | /* Code with multiple case ...: gets sorted by the lowest case ... | |
1087 | it belongs to. I hope this makes sense. */ | |
1088 | switch(*s) { | |
1089 | case '!': | |
1090 | if (opP->mode == MSCR || opP->mode == IMMED | |
1091 | || opP->mode == DREG || opP->mode == AREG | |
1092 | || opP->mode == AINC || opP->mode == ADEC | |
1093 | || opP->mode == REGLST) | |
1094 | losing++; | |
1095 | break; | |
1096 | ||
1097 | case '#': | |
1098 | if(opP->mode!=IMMED) | |
1099 | losing++; | |
1100 | else { | |
1101 | long t; | |
6d27d3a2 | 1102 | |
8be74775 KR |
1103 | t=get_num(opP->con1,80); |
1104 | if(s[1]=='b' && !isbyte(t)) | |
1105 | losing++; | |
1106 | else if(s[1]=='w' && !isword(t)) | |
1107 | losing++; | |
1108 | } | |
1109 | break; | |
1110 | ||
1111 | case '^': | |
1112 | case 'T': | |
1113 | if(opP->mode!=IMMED) | |
1114 | losing++; | |
1115 | break; | |
1116 | ||
1117 | case '$': | |
1118 | if(opP->mode==MSCR || opP->mode==AREG || | |
1119 | opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST) | |
1120 | losing++; | |
1121 | break; | |
1122 | ||
1123 | case '%': | |
1124 | if(opP->mode==MSCR || opP->reg==PC || | |
1125 | opP->reg==ZPC || opP->mode==REGLST) | |
1126 | losing++; | |
1127 | break; | |
1128 | ||
1129 | ||
1130 | case '&': | |
1131 | if(opP->mode==MSCR || opP->mode==DREG || | |
1132 | opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || | |
1133 | opP->mode==AINC || opP->mode==ADEC || opP->mode==REGLST) | |
1134 | losing++; | |
1135 | break; | |
1136 | ||
1137 | case '*': | |
1138 | if(opP->mode==MSCR || opP->mode==REGLST) | |
1139 | losing++; | |
1140 | break; | |
6d27d3a2 | 1141 | |
8be74775 KR |
1142 | case '+': |
1143 | if(opP->mode!=AINC) | |
1144 | losing++; | |
1145 | break; | |
6d27d3a2 | 1146 | |
8be74775 KR |
1147 | case '-': |
1148 | if(opP->mode!=ADEC) | |
1149 | losing++; | |
1150 | break; | |
1151 | ||
1152 | case '/': | |
1153 | if(opP->mode==MSCR || opP->mode==AREG || | |
1154 | opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->mode==REGLST) | |
1155 | losing++; | |
1156 | break; | |
1157 | ||
1158 | case ';': | |
1159 | if(opP->mode==MSCR || opP->mode==AREG || opP->mode==REGLST) | |
1160 | losing++; | |
1161 | break; | |
1162 | ||
1163 | case '?': | |
1164 | if(opP->mode==MSCR || opP->mode==AREG || | |
1165 | opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->reg==PC || | |
1166 | opP->reg==ZPC || opP->mode==REGLST) | |
1167 | losing++; | |
1168 | break; | |
1169 | ||
1170 | case '@': | |
1171 | if(opP->mode==MSCR || opP->mode==AREG || | |
1172 | opP->mode==IMMED || opP->mode==REGLST) | |
1173 | losing++; | |
1174 | break; | |
1175 | ||
1176 | case '~': /* For now! (JF FOO is this right?) */ | |
1177 | if(opP->mode==MSCR || opP->mode==DREG || | |
1178 | opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST) | |
1179 | losing++; | |
1180 | break; | |
1181 | ||
4134a793 KR |
1182 | case '3': |
1183 | if (opP->mode != MSCR || (opP->reg != TT0 && opP->reg != TT1)) | |
1184 | losing++; | |
1185 | break; | |
1186 | ||
8be74775 KR |
1187 | case 'A': |
1188 | if(opP->mode!=AREG) | |
1189 | losing++; | |
1190 | break; | |
1191 | case 'a': | |
1192 | if (opP->mode != AINDR) { | |
1193 | ++losing; | |
1194 | } /* if not address register indirect */ | |
1195 | break; | |
1196 | case 'B': /* FOO */ | |
1197 | if(opP->mode!=ABSL || (flagseen['S'] && instring[0] == 'j' | |
1198 | && instring[1] == 'b' | |
1199 | && instring[2] == 's' | |
1200 | && instring[3] == 'r')) | |
1201 | losing++; | |
1202 | break; | |
1203 | ||
1204 | case 'C': | |
1205 | if(opP->mode!=MSCR || opP->reg!=CCR) | |
1206 | losing++; | |
1207 | break; | |
1208 | ||
1209 | case 'd': /* FOO This mode is a KLUDGE!! */ | |
1210 | if(opP->mode!=AOFF && (opP->mode!=ABSL || | |
1211 | opP->con1->e_beg[0]!='(' || opP->con1->e_end[0]!=')')) | |
1212 | losing++; | |
1213 | break; | |
1214 | ||
1215 | case 'D': | |
1216 | if(opP->mode!=DREG) | |
1217 | losing++; | |
1218 | break; | |
1219 | ||
1220 | case 'F': | |
1221 | if(opP->mode!=MSCR || opP->reg<(FPREG+0) || opP->reg>(FPREG+7)) | |
1222 | losing++; | |
1223 | break; | |
1224 | ||
1225 | case 'I': | |
1226 | if(opP->mode!=MSCR || opP->reg<COPNUM || | |
1227 | opP->reg>=COPNUM+7) | |
1228 | losing++; | |
1229 | break; | |
1230 | ||
1231 | case 'J': | |
1232 | if (opP->mode != MSCR | |
1233 | || opP->reg < USP | |
1234 | || opP->reg > URP | |
1235 | || cpu_of_arch(current_architecture) < m68010 /* before 68010 had none */ | |
1236 | || (cpu_of_arch(current_architecture) < m68020 | |
1237 | && opP->reg != SFC | |
1238 | && opP->reg != DFC | |
1239 | && opP->reg != USP | |
1240 | && opP->reg != VBR) /* 68010's had only these */ | |
1241 | || (cpu_of_arch(current_architecture) < m68040 | |
1242 | && opP->reg != SFC | |
1243 | && opP->reg != DFC | |
1244 | && opP->reg != USP | |
1245 | && opP->reg != VBR | |
1246 | && opP->reg != CACR | |
1247 | && opP->reg != CAAR | |
1248 | && opP->reg != MSP | |
1249 | && opP->reg != ISP) /* 680[23]0's have only these */ | |
1250 | || (cpu_of_arch(current_architecture) == m68040 /* 68040 has all but this */ | |
1251 | && opP->reg == CAAR)) { | |
1252 | losing++; | |
1253 | } /* doesn't cut it */ | |
1254 | break; | |
1255 | ||
1256 | case 'k': | |
1257 | if(opP->mode!=IMMED) | |
1258 | losing++; | |
1259 | break; | |
6d27d3a2 | 1260 | |
8be74775 KR |
1261 | case 'l': |
1262 | case 'L': | |
1263 | if(opP->mode==DREG || opP->mode==AREG || opP->mode==FPREG) { | |
1264 | if(s[1]=='8') | |
1265 | losing++; | |
1266 | else { | |
1267 | opP->mode=REGLST; | |
1268 | opP->reg=1<<(opP->reg-DATA); | |
1269 | } | |
1270 | } else if(opP->mode!=REGLST) { | |
1271 | losing++; | |
1272 | } else if(s[1]=='8' && opP->reg&0x0FFffFF) | |
1273 | losing++; | |
1274 | else if(s[1]=='3' && opP->reg&0x7000000) | |
1275 | losing++; | |
1276 | break; | |
1277 | ||
1278 | case 'M': | |
1279 | if(opP->mode!=IMMED) | |
1280 | losing++; | |
1281 | else { | |
1282 | long t; | |
6d27d3a2 | 1283 | |
8be74775 KR |
1284 | t=get_num(opP->con1,80); |
1285 | if(!issbyte(t) || isvar(opP->con1)) | |
1286 | losing++; | |
1287 | } | |
1288 | break; | |
6d27d3a2 | 1289 | |
8be74775 KR |
1290 | case 'O': |
1291 | if(opP->mode!=DREG && opP->mode!=IMMED) | |
1292 | losing++; | |
1293 | break; | |
6d27d3a2 | 1294 | |
8be74775 KR |
1295 | case 'Q': |
1296 | if(opP->mode!=IMMED) | |
1297 | losing++; | |
1298 | else { | |
1299 | long t; | |
6d27d3a2 | 1300 | |
8be74775 KR |
1301 | t=get_num(opP->con1,80); |
1302 | if(t<1 || t>8 || isvar(opP->con1)) | |
1303 | losing++; | |
1304 | } | |
1305 | break; | |
1306 | ||
1307 | case 'R': | |
1308 | if(opP->mode!=DREG && opP->mode!=AREG) | |
1309 | losing++; | |
1310 | break; | |
1311 | ||
c50140c8 ILT |
1312 | case 'r': |
1313 | if (opP->mode!=AINDR && opP->mode!=DINDR) | |
1314 | losing++; | |
1315 | break; | |
1316 | ||
8be74775 KR |
1317 | case 's': |
1318 | if(opP->mode!=MSCR || !(opP->reg==FPI || opP->reg==FPS || opP->reg==FPC)) | |
1319 | losing++; | |
1320 | break; | |
1321 | ||
1322 | case 'S': | |
1323 | if(opP->mode!=MSCR || opP->reg!=SR) | |
1324 | losing++; | |
1325 | break; | |
1326 | ||
4134a793 KR |
1327 | case 't': |
1328 | if (opP->mode != IMMED) | |
1329 | losing++; | |
1330 | else | |
1331 | { | |
1332 | long t = get_num (opP->con1, 80); | |
1333 | if (t < 0 || t > 7 || isvar (opP->con1)) | |
1334 | losing++; | |
1335 | } | |
1336 | break; | |
1337 | ||
8be74775 KR |
1338 | case 'U': |
1339 | if(opP->mode!=MSCR || opP->reg!=USP) | |
1340 | losing++; | |
1341 | break; | |
1342 | ||
1343 | /* JF these are out of order. We could put them | |
1344 | in order if we were willing to put up with | |
4134a793 KR |
1345 | bunches of #ifdef m68851s in the code. |
1346 | ||
1347 | Don't forget that you need these operands | |
1348 | to use 68030 MMU instructions. */ | |
f8701a3f | 1349 | #ifndef NO_68851 |
8be74775 KR |
1350 | /* Memory addressing mode used by pflushr */ |
1351 | case '|': | |
1352 | if(opP->mode==MSCR || opP->mode==DREG || | |
1353 | opP->mode==AREG || opP->mode==REGLST) | |
1354 | losing++; | |
1355 | break; | |
1356 | ||
1357 | case 'f': | |
1358 | if (opP->mode != MSCR || (opP->reg != SFC && opP->reg != DFC)) | |
1359 | losing++; | |
1360 | break; | |
1361 | ||
1362 | case 'P': | |
4134a793 KR |
1363 | if (opP->mode != MSCR |
1364 | || (opP->reg != TC && opP->reg != CAL | |
1365 | && opP->reg != VAL && opP->reg != SCC && opP->reg != AC)) | |
8be74775 KR |
1366 | losing++; |
1367 | break; | |
1368 | ||
1369 | case 'V': | |
1370 | if (opP->reg != VAL) | |
1371 | losing++; | |
1372 | break; | |
6d27d3a2 | 1373 | |
8be74775 | 1374 | case 'W': |
4134a793 KR |
1375 | if (opP->mode != MSCR |
1376 | || (opP->reg != DRP && opP->reg != SRP | |
1377 | && opP->reg != CRP)) | |
8be74775 KR |
1378 | losing++; |
1379 | break; | |
1380 | ||
1381 | case 'X': | |
1382 | if (opP->mode != MSCR || | |
1383 | (!(opP->reg >= BAD && opP->reg <= BAD+7) && | |
1384 | !(opP->reg >= BAC && opP->reg <= BAC+7))) | |
1385 | losing++; | |
1386 | break; | |
1387 | ||
1388 | case 'Y': | |
1389 | if (opP->reg != PSR) | |
1390 | losing++; | |
1391 | break; | |
1392 | ||
1393 | case 'Z': | |
1394 | if (opP->reg != PCSR) | |
1395 | losing++; | |
1396 | break; | |
f8701a3f | 1397 | #endif |
8be74775 KR |
1398 | case 'c': |
1399 | if (opP->reg != NC | |
1400 | && opP->reg != IC | |
1401 | && opP->reg != DC | |
1402 | && opP->reg != BC) { | |
1403 | losing++; | |
1404 | } /* not a cache specifier. */ | |
1405 | break; | |
1406 | ||
1407 | case '_': | |
1408 | if (opP->mode != ABSL) { | |
1409 | ++losing; | |
1410 | } /* not absolute */ | |
1411 | break; | |
6d27d3a2 | 1412 | |
8be74775 | 1413 | default: |
4134a793 | 1414 | as_fatal("Internal error: Operand mode %c unknown in line %d of file \"%s\"", |
8be74775 KR |
1415 | *s, __LINE__, __FILE__); |
1416 | } /* switch on type of operand */ | |
6d27d3a2 | 1417 | |
8be74775 KR |
1418 | if (losing) |
1419 | break; | |
1420 | } /* for each operand */ | |
1421 | } /* if immediately wrong */ | |
6d27d3a2 KR |
1422 | |
1423 | if (!losing) { | |
1424 | break; | |
1425 | } /* got it. */ | |
1426 | ||
1427 | opcode = opcode->m_next; | |
1428 | ||
1429 | if (!opcode) { | |
4134a793 KR |
1430 | if (ok_arch |
1431 | && !(ok_arch & current_architecture)) | |
8be74775 KR |
1432 | { |
1433 | char buf[200], *cp; | |
1434 | int len; | |
1435 | strcpy (buf, "invalid instruction for this architecture; needs "); | |
1436 | cp = buf + strlen (buf); | |
1437 | switch (ok_arch) | |
1438 | { | |
1439 | case mfloat: | |
4134a793 | 1440 | strcpy (cp, "fpu (68040 or 68881/68882)"); |
8be74775 KR |
1441 | break; |
1442 | case mmmu: | |
4134a793 | 1443 | strcpy (cp, "mmu (68030 or 68851)"); |
8be74775 KR |
1444 | break; |
1445 | case m68020up: | |
1446 | strcpy (cp, "68020 or higher"); | |
1447 | break; | |
1448 | case m68000up: | |
1449 | strcpy (cp, "68000 or higher"); | |
1450 | break; | |
1451 | case m68010up: | |
1452 | strcpy (cp, "68010 or higher"); | |
1453 | break; | |
1454 | default: | |
1455 | { | |
1456 | int got_one = 0, idx; | |
1457 | const static struct { | |
1458 | enum m68k_architecture arch; | |
1459 | const char *name; | |
1460 | } archs[] = { | |
1461 | m68000, "68000", | |
1462 | m68010, "68010", | |
1463 | m68020, "68020", | |
1464 | m68030, "68030", | |
1465 | m68040, "68040", | |
1466 | m68881, "68881", | |
1467 | m68851, "68851", | |
1468 | }; | |
1469 | for (idx = 0; idx < sizeof (archs)/sizeof (archs[0]); idx++) | |
1470 | { | |
1471 | if (archs[idx].arch & ok_arch) | |
1472 | { | |
1473 | if (got_one) | |
1474 | { | |
1475 | strcpy (cp, " or "); | |
1476 | cp += strlen (cp); | |
1477 | } | |
1478 | got_one = 1; | |
1479 | strcpy (cp, archs[idx].name); | |
1480 | cp += strlen (cp); | |
1481 | } | |
1482 | } | |
1483 | } | |
1484 | } | |
1485 | len = cp - buf + 1; | |
1486 | cp = malloc (len); | |
1487 | strcpy (cp, buf); | |
1488 | the_ins.error = cp; | |
1489 | } | |
1490 | else | |
1491 | the_ins.error = "operands mismatch"; | |
6d27d3a2 KR |
1492 | return; |
1493 | } /* Fell off the end */ | |
1494 | ||
1495 | losing = 0; | |
1496 | } | |
1497 | ||
1498 | /* now assemble it */ | |
1499 | ||
1500 | the_ins.args=opcode->m_operands; | |
1501 | the_ins.numargs=opcode->m_opnum; | |
1502 | the_ins.numo=opcode->m_codenum; | |
1503 | the_ins.opcode[0]=getone(opcode); | |
1504 | the_ins.opcode[1]=gettwo(opcode); | |
1505 | ||
1506 | for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++) { | |
1507 | /* This switch is a doozy. | |
1508 | Watch the first step; its a big one! */ | |
1509 | switch(s[0]) { | |
1510 | ||
1511 | case '*': | |
1512 | case '~': | |
1513 | case '%': | |
1514 | case ';': | |
1515 | case '@': | |
1516 | case '!': | |
1517 | case '&': | |
1518 | case '$': | |
1519 | case '?': | |
1520 | case '/': | |
f8701a3f | 1521 | #ifndef NO_68851 |
6d27d3a2 | 1522 | case '|': |
f8701a3f | 1523 | #endif |
6d27d3a2 KR |
1524 | switch(opP->mode) { |
1525 | case IMMED: | |
1526 | tmpreg=0x3c; /* 7.4 */ | |
1527 | if (strchr("bwl",s[1])) nextword=get_num(opP->con1,80); | |
1528 | else nextword=nextword=get_num(opP->con1,0); | |
1529 | if(isvar(opP->con1)) | |
1530 | add_fix(s[1],opP->con1,0); | |
1531 | switch(s[1]) { | |
1532 | case 'b': | |
1533 | if(!isbyte(nextword)) | |
1534 | opP->error="operand out of range"; | |
1535 | addword(nextword); | |
1536 | baseo=0; | |
1537 | break; | |
1538 | case 'w': | |
1539 | if(!isword(nextword)) | |
1540 | opP->error="operand out of range"; | |
1541 | addword(nextword); | |
1542 | baseo=0; | |
1543 | break; | |
1544 | case 'l': | |
1545 | addword(nextword>>16); | |
1546 | addword(nextword); | |
1547 | baseo=0; | |
1548 | break; | |
1549 | ||
1550 | case 'f': | |
1551 | baseo=2; | |
1552 | outro=8; | |
1553 | break; | |
1554 | case 'F': | |
1555 | baseo=4; | |
1556 | outro=11; | |
1557 | break; | |
1558 | case 'x': | |
1559 | baseo=6; | |
1560 | outro=15; | |
1561 | break; | |
1562 | case 'p': | |
1563 | baseo=6; | |
1564 | outro= -1; | |
1565 | break; | |
1566 | default: | |
1567 | as_fatal("Internal error: Can't decode %c%c in line %s of file \"%s\"", | |
1568 | *s, s[1], __LINE__, __FILE__); | |
1569 | } | |
1570 | if(!baseo) | |
1571 | break; | |
1572 | ||
1573 | /* We gotta put out some float */ | |
1574 | if(seg(opP->con1)!=SEG_BIG) { | |
1575 | int_to_gen(nextword); | |
1576 | gen_to_words(words,baseo,(long int)outro); | |
1577 | for(wordp=words;baseo--;wordp++) | |
1578 | addword(*wordp); | |
1579 | break; | |
1580 | } /* Its BIG */ | |
1581 | if(offs(opP->con1)>0) { | |
1582 | as_warn("Bignum assumed to be binary bit-pattern"); | |
1583 | if(offs(opP->con1)>baseo) { | |
1584 | as_warn("Bignum too big for %c format; truncated",s[1]); | |
1585 | offs(opP->con1)=baseo; | |
1586 | } | |
1587 | baseo-=offs(opP->con1); | |
1588 | for(wordp=generic_bignum+offs(opP->con1)-1;offs(opP->con1)--;--wordp) | |
1589 | addword(*wordp); | |
1590 | while(baseo--) | |
1591 | addword(0); | |
1592 | break; | |
1593 | } | |
1594 | gen_to_words(words,baseo,(long)outro); | |
1595 | for (wordp=words;baseo--;wordp++) | |
1596 | addword(*wordp); | |
1597 | break; | |
1598 | case DREG: | |
1599 | tmpreg=opP->reg-DATA; /* 0.dreg */ | |
1600 | break; | |
1601 | case AREG: | |
1602 | tmpreg=0x08+opP->reg-ADDR; /* 1.areg */ | |
1603 | break; | |
1604 | case AINDR: | |
1605 | tmpreg=0x10+opP->reg-ADDR; /* 2.areg */ | |
1606 | break; | |
1607 | case ADEC: | |
1608 | tmpreg=0x20+opP->reg-ADDR; /* 4.areg */ | |
1609 | break; | |
1610 | case AINC: | |
1611 | tmpreg=0x18+opP->reg-ADDR; /* 3.areg */ | |
1612 | break; | |
1613 | case AOFF: | |
1614 | ||
1615 | nextword=get_num(opP->con1,80); | |
1616 | /* Force into index mode. Hope this works */ | |
1617 | ||
1618 | /* We do the first bit for 32-bit displacements, | |
1619 | and the second bit for 16 bit ones. It is | |
1620 | possible that we should make the default be | |
1621 | WORD instead of LONG, but I think that'd | |
1622 | break GCC, so we put up with a little | |
1623 | inefficiency for the sake of working output. | |
1624 | */ | |
1625 | ||
1626 | if( !issword(nextword) | |
1627 | || ( isvar(opP->con1) | |
1628 | && ( ( opP->con1->e_siz==0 | |
1629 | && flagseen['l']==0) | |
1630 | || opP->con1->e_siz==3))) { | |
1631 | ||
1632 | if(opP->reg==PC) | |
1633 | tmpreg=0x3B; /* 7.3 */ | |
1634 | else | |
1635 | tmpreg=0x30+opP->reg-ADDR; /* 6.areg */ | |
1636 | if(isvar(opP->con1)) { | |
1637 | if(opP->reg==PC) { | |
1638 | add_frag(adds(opP->con1), | |
1639 | offs(opP->con1), | |
1640 | TAB(PCLEA,SZ_UNDEF)); | |
1641 | break; | |
1642 | } else { | |
1643 | addword(0x0170); | |
1644 | add_fix('l',opP->con1,1); | |
1645 | } | |
1646 | } else | |
1647 | addword(0x0170); | |
1648 | addword(nextword>>16); | |
1649 | } else { | |
1650 | if(opP->reg==PC) | |
1651 | tmpreg=0x3A; /* 7.2 */ | |
1652 | else | |
1653 | tmpreg=0x28+opP->reg-ADDR; /* 5.areg */ | |
1654 | ||
1655 | if(isvar(opP->con1)) { | |
1656 | if(opP->reg==PC) { | |
1657 | add_fix('w',opP->con1,1); | |
1658 | } else | |
1659 | add_fix('w',opP->con1,0); | |
1660 | } | |
1661 | } | |
1662 | addword(nextword); | |
1663 | break; | |
1664 | ||
1665 | case APODX: | |
1666 | case AMIND: | |
1667 | case APRDX: | |
1668 | know(current_architecture & m68020up); | |
1669 | /* intentional fall-through */ | |
1670 | case AINDX: | |
1671 | nextword=0; | |
1672 | baseo=get_num(opP->con1,80); | |
1673 | outro=get_num(opP->con2,80); | |
1674 | /* Figure out the 'addressing mode' */ | |
1675 | /* Also turn on the BASE_DISABLE bit, if needed */ | |
1676 | if(opP->reg==PC || opP->reg==ZPC) { | |
1677 | tmpreg=0x3b; /* 7.3 */ | |
1678 | if(opP->reg==ZPC) | |
1679 | nextword|=0x80; | |
1680 | } else if(opP->reg==FAIL) { | |
1681 | nextword|=0x80; | |
1682 | tmpreg=0x30; /* 6.garbage */ | |
1683 | } else tmpreg=0x30+opP->reg-ADDR; /* 6.areg */ | |
1684 | ||
1685 | siz1= (opP->con1) ? opP->con1->e_siz : 0; | |
1686 | siz2= (opP->con2) ? opP->con2->e_siz : 0; | |
1687 | ||
1688 | /* Index register stuff */ | |
1689 | if(opP->ireg>=DATA+0 && opP->ireg<=ADDR+7) { | |
1690 | nextword|=(opP->ireg-DATA)<<12; | |
1691 | ||
1692 | if(opP->isiz==0 || opP->isiz==3) | |
1693 | nextword|=0x800; | |
1694 | switch(opP->imul) { | |
1695 | case 1: break; | |
1696 | case 2: nextword|=0x200; break; | |
1697 | case 4: nextword|=0x400; break; | |
1698 | case 8: nextword|=0x600; break; | |
1699 | default: as_fatal("failed sanity check."); | |
1700 | } | |
1701 | /* IF its simple, | |
1702 | GET US OUT OF HERE! */ | |
1703 | ||
1704 | /* Must be INDEX, with an index | |
1705 | register. Address register | |
1706 | cannot be ZERO-PC, and either | |
1707 | :b was forced, or we know | |
1708 | it will fit */ | |
1709 | if( opP->mode==AINDX | |
1710 | && opP->reg!=FAIL | |
1711 | && opP->reg!=ZPC | |
1712 | && ( siz1==1 | |
1713 | || ( issbyte(baseo) | |
1714 | && !isvar(opP->con1)))) { | |
1715 | nextword +=baseo&0xff; | |
1716 | addword(nextword); | |
1717 | if(isvar(opP->con1)) | |
1718 | add_fix('B',opP->con1,0); | |
1719 | break; | |
1720 | } | |
1721 | } else | |
1722 | nextword|=0x40; /* No index reg */ | |
1723 | ||
1724 | /* It aint simple */ | |
1725 | nextword|=0x100; | |
1726 | /* If the guy specified a width, we assume that | |
1727 | it is wide enough. Maybe it isn't. If so, we lose | |
1728 | */ | |
1729 | switch(siz1) { | |
1730 | case 0: | |
1731 | if(isvar(opP->con1) || !issword(baseo)) { | |
1732 | siz1=3; | |
1733 | nextword|=0x30; | |
1734 | } else if(baseo==0) | |
1735 | nextword|=0x10; | |
1736 | else { | |
1737 | nextword|=0x20; | |
1738 | siz1=2; | |
1739 | } | |
1740 | break; | |
1741 | case 1: | |
1742 | as_warn("Byte dispacement won't work. Defaulting to :w"); | |
1743 | case 2: | |
1744 | nextword|=0x20; | |
1745 | break; | |
1746 | case 3: | |
1747 | nextword|=0x30; | |
1748 | break; | |
1749 | } | |
1750 | ||
1751 | /* Figure out innner displacement stuff */ | |
1752 | if(opP->mode!=AINDX) { | |
1753 | switch(siz2) { | |
1754 | case 0: | |
1755 | if(isvar(opP->con2) || !issword(outro)) { | |
1756 | siz2=3; | |
1757 | nextword|=0x3; | |
1758 | } else if(outro==0) | |
1759 | nextword|=0x1; | |
1760 | else { | |
1761 | nextword|=0x2; | |
1762 | siz2=2; | |
1763 | } | |
1764 | break; | |
1765 | case 1: | |
1766 | as_warn("Byte dispacement won't work. Defaulting to :w"); | |
1767 | case 2: | |
1768 | nextword|=0x2; | |
1769 | break; | |
1770 | case 3: | |
1771 | nextword|=0x3; | |
1772 | break; | |
1773 | } | |
1774 | if(opP->mode==APODX) nextword|=0x04; | |
1775 | else if(opP->mode==AMIND) nextword|=0x40; | |
1776 | } | |
1777 | addword(nextword); | |
1778 | ||
1779 | if(isvar(opP->con1)) { | |
1780 | if(opP->reg==PC || opP->reg==ZPC) { | |
1781 | add_fix(siz1==3 ? 'l' : 'w',opP->con1,1); | |
1782 | opP->con1->e_exp.X_add_number+=6; | |
1783 | } else | |
1784 | add_fix(siz1==3 ? 'l' : 'w',opP->con1,0); | |
1785 | } | |
1786 | if(siz1==3) | |
1787 | addword(baseo>>16); | |
1788 | if(siz1) | |
1789 | addword(baseo); | |
1790 | ||
1791 | if(isvar(opP->con2)) { | |
1792 | if(opP->reg==PC || opP->reg==ZPC) { | |
1793 | add_fix(siz2==3 ? 'l' : 'w',opP->con2,1); | |
1794 | opP->con1->e_exp.X_add_number+=6; | |
1795 | } else | |
1796 | add_fix(siz2==3 ? 'l' : 'w',opP->con2,0); | |
1797 | } | |
1798 | if(siz2==3) | |
1799 | addword(outro>>16); | |
1800 | if(siz2) | |
1801 | addword(outro); | |
1802 | ||
1803 | break; | |
1804 | ||
1805 | case ABSL: | |
1806 | nextword=get_num(opP->con1,80); | |
1807 | switch(opP->con1->e_siz) { | |
1808 | default: | |
1809 | as_warn("Unknown size for absolute reference"); | |
1810 | case 0: | |
1811 | if(!isvar(opP->con1) && issword(offs(opP->con1))) { | |
1812 | tmpreg=0x38; /* 7.0 */ | |
1813 | addword(nextword); | |
1814 | break; | |
1815 | } | |
1816 | /* Don't generate pc relative code | |
1817 | on 68010 and 68000 */ | |
1818 | if(isvar(opP->con1) | |
1819 | && !subs(opP->con1) | |
1820 | && seg(opP->con1) == SEG_TEXT | |
1821 | && now_seg == SEG_TEXT | |
1822 | && cpu_of_arch(current_architecture) >= m68020 | |
1823 | && !flagseen['S'] | |
1824 | && !strchr("~%&$?", s[0])) { | |
1825 | tmpreg=0x3A; /* 7.2 */ | |
1826 | add_frag(adds(opP->con1), | |
1827 | offs(opP->con1), | |
1828 | TAB(PCREL,SZ_UNDEF)); | |
1829 | break; | |
1830 | } | |
1831 | case 3: /* Fall through into long */ | |
1832 | if(isvar(opP->con1)) | |
1833 | add_fix('l',opP->con1,0); | |
1834 | ||
1835 | tmpreg=0x39; /* 7.1 mode */ | |
1836 | addword(nextword>>16); | |
1837 | addword(nextword); | |
1838 | break; | |
1839 | ||
1840 | case 2: /* Word */ | |
1841 | if(isvar(opP->con1)) | |
1842 | add_fix('w',opP->con1,0); | |
1843 | ||
1844 | tmpreg=0x38; /* 7.0 mode */ | |
1845 | addword(nextword); | |
1846 | break; | |
1847 | } | |
1848 | break; | |
c50140c8 ILT |
1849 | case DINDR: |
1850 | as_bad("invalid indirect register"); | |
1851 | break; | |
6d27d3a2 KR |
1852 | case MSCR: |
1853 | default: | |
1854 | as_bad("unknown/incorrect operand"); | |
1855 | /* abort(); */ | |
1856 | } | |
1857 | install_gen_operand(s[1],tmpreg); | |
1858 | break; | |
1859 | ||
1860 | case '#': | |
1861 | case '^': | |
1862 | switch(s[1]) { /* JF: I hate floating point! */ | |
1863 | case 'j': | |
1864 | tmpreg=70; | |
1865 | break; | |
1866 | case '8': | |
1867 | tmpreg=20; | |
1868 | break; | |
1869 | case 'C': | |
1870 | tmpreg=50; | |
1871 | break; | |
1872 | case '3': | |
1873 | default: | |
1874 | tmpreg=80; | |
1875 | break; | |
1876 | } | |
1877 | tmpreg=get_num(opP->con1,tmpreg); | |
1878 | if(isvar(opP->con1)) | |
1879 | add_fix(s[1],opP->con1,0); | |
1880 | switch(s[1]) { | |
1881 | case 'b': /* Danger: These do no check for | |
1882 | certain types of overflow. | |
1883 | user beware! */ | |
1884 | if(!isbyte(tmpreg)) | |
1885 | opP->error="out of range"; | |
1886 | insop(tmpreg); | |
1887 | if(isvar(opP->con1)) | |
1888 | the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2; | |
1889 | break; | |
1890 | case 'w': | |
1891 | if(!isword(tmpreg)) | |
1892 | opP->error="out of range"; | |
1893 | insop(tmpreg); | |
1894 | if(isvar(opP->con1)) | |
1895 | the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2; | |
1896 | break; | |
1897 | case 'l': | |
1898 | insop(tmpreg); /* Because of the way insop works, we put these two out backwards */ | |
1899 | insop(tmpreg>>16); | |
1900 | if(isvar(opP->con1)) | |
1901 | the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2; | |
1902 | break; | |
1903 | case '3': | |
1904 | tmpreg&=0xFF; | |
1905 | case '8': | |
1906 | case 'C': | |
1907 | install_operand(s[1],tmpreg); | |
1908 | break; | |
1909 | default: | |
1910 | as_fatal("Internal error: Unknown mode #%c in line %s of file \"%s\"", s[1], __LINE__, __FILE__); | |
1911 | } | |
1912 | break; | |
1913 | ||
1914 | case '+': | |
1915 | case '-': | |
1916 | case 'A': | |
1917 | case 'a': | |
1918 | install_operand(s[1],opP->reg-ADDR); | |
1919 | break; | |
1920 | ||
1921 | case 'B': | |
1922 | tmpreg=get_num(opP->con1,80); | |
1923 | switch(s[1]) { | |
1924 | case 'B': | |
1925 | /* Needs no offsetting */ | |
1926 | add_fix('B',opP->con1,1); | |
1927 | break; | |
1928 | case 'W': | |
1929 | /* Offset the displacement to be relative to byte disp location */ | |
1930 | opP->con1->e_exp.X_add_number+=2; | |
1931 | add_fix('w',opP->con1,1); | |
1932 | addword(0); | |
1933 | break; | |
1934 | case 'L': | |
1935 | long_branch: | |
1936 | if (cpu_of_arch(current_architecture) < m68020) /* 68000 or 010 */ | |
1937 | as_warn("Can't use long branches on 68000/68010"); | |
1938 | the_ins.opcode[the_ins.numo-1]|=0xff; | |
1939 | /* Offset the displacement to be relative to byte disp location */ | |
1940 | opP->con1->e_exp.X_add_number+=4; | |
1941 | add_fix('l',opP->con1,1); | |
1942 | addword(0); | |
1943 | addword(0); | |
1944 | break; | |
1945 | case 'g': | |
1946 | if(subs(opP->con1)) /* We can't relax it */ | |
1947 | goto long_branch; | |
1948 | ||
1949 | /* This could either be a symbol, or an | |
1950 | absolute address. No matter, the | |
1951 | frag hacking will finger it out. | |
1952 | Not quite: it can't switch from | |
1953 | BRANCH to BCC68000 for the case | |
1954 | where opnd is absolute (it needs | |
1955 | to use the 68000 hack since no | |
1956 | conditional abs jumps). */ | |
1957 | if (((cpu_of_arch(current_architecture) < m68020) || (0==adds(opP->con1))) | |
1958 | && (the_ins.opcode[0] >= 0x6200) | |
1959 | && (the_ins.opcode[0] <= 0x6f00)) { | |
1960 | add_frag(adds(opP->con1),offs(opP->con1),TAB(BCC68000,SZ_UNDEF)); | |
1961 | } else { | |
1962 | add_frag(adds(opP->con1),offs(opP->con1),TAB(BRANCH,SZ_UNDEF)); | |
1963 | } | |
1964 | break; | |
1965 | case 'w': | |
1966 | if(isvar(opP->con1)) { | |
1967 | /* check for DBcc instruction */ | |
1968 | if ((the_ins.opcode[0] & 0xf0f8) ==0x50c8) { | |
1969 | /* size varies if patch */ | |
1970 | /* needed for long form */ | |
1971 | add_frag(adds(opP->con1),offs(opP->con1),TAB(DBCC,SZ_UNDEF)); | |
1972 | break; | |
1973 | } | |
1974 | ||
1975 | /* Don't ask! */ | |
1976 | opP->con1->e_exp.X_add_number+=2; | |
1977 | add_fix('w',opP->con1,1); | |
1978 | } | |
1979 | addword(0); | |
1980 | break; | |
1981 | case 'C': /* Fixed size LONG coproc branches */ | |
1982 | the_ins.opcode[the_ins.numo-1]|=0x40; | |
1983 | /* Offset the displacement to be relative to byte disp location */ | |
1984 | /* Coproc branches don't have a byte disp option, but they are | |
1985 | compatible with the ordinary branches, which do... */ | |
1986 | opP->con1->e_exp.X_add_number+=4; | |
1987 | add_fix('l',opP->con1,1); | |
1988 | addword(0); | |
1989 | addword(0); | |
1990 | break; | |
1991 | case 'c': /* Var size Coprocesssor branches */ | |
1992 | if(subs(opP->con1)) { | |
1993 | add_fix('l',opP->con1,1); | |
1994 | add_frag((symbolS *)0,(long)0,TAB(FBRANCH,LONG)); | |
1995 | } else if(adds(opP->con1)) { | |
1996 | add_frag(adds(opP->con1),offs(opP->con1),TAB(FBRANCH,SZ_UNDEF)); | |
1997 | } else { | |
1998 | /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */ | |
1999 | the_ins.opcode[the_ins.numo-1]|=0x40; | |
2000 | add_fix('l',opP->con1,1); | |
2001 | addword(0); | |
2002 | addword(4); | |
2003 | } | |
2004 | break; | |
2005 | default: | |
2006 | as_fatal("Internal error: operand type B%c unknown in line %s of file \"%s\"", | |
2007 | s[1], __LINE__, __FILE__); | |
2008 | } | |
2009 | break; | |
2010 | ||
2011 | case 'C': /* Ignore it */ | |
2012 | break; | |
2013 | ||
2014 | case 'd': /* JF this is a kludge */ | |
2015 | if(opP->mode==AOFF) { | |
2016 | install_operand('s',opP->reg-ADDR); | |
2017 | } else { | |
2018 | char *tmpP; | |
2019 | ||
2020 | tmpP=opP->con1->e_end-2; | |
2021 | opP->con1->e_beg++; | |
2022 | opP->con1->e_end-=4; /* point to the , */ | |
2023 | baseo=m68k_reg_parse(&tmpP); | |
2024 | if(baseo<ADDR+0 || baseo>ADDR+7) { | |
2025 | as_bad("Unknown address reg, using A0"); | |
2026 | baseo=0; | |
2027 | } else baseo-=ADDR; | |
2028 | install_operand('s',baseo); | |
2029 | } | |
2030 | tmpreg=get_num(opP->con1,80); | |
2031 | if(!issword(tmpreg)) { | |
2032 | as_warn("Expression out of range, using 0"); | |
2033 | tmpreg=0; | |
2034 | } | |
2035 | addword(tmpreg); | |
2036 | break; | |
2037 | ||
2038 | case 'D': | |
2039 | install_operand(s[1],opP->reg-DATA); | |
2040 | break; | |
2041 | ||
2042 | case 'F': | |
2043 | install_operand(s[1],opP->reg-FPREG); | |
2044 | break; | |
2045 | ||
2046 | case 'I': | |
2047 | tmpreg=1+opP->reg-COPNUM; | |
2048 | if(tmpreg==8) | |
2049 | tmpreg=0; | |
2050 | install_operand(s[1],tmpreg); | |
2051 | break; | |
2052 | ||
2053 | case 'J': /* JF foo */ | |
2054 | switch(opP->reg) { | |
2055 | case SFC: tmpreg=0x000; break; | |
2056 | case DFC: tmpreg=0x001; break; | |
2057 | case CACR: tmpreg=0x002; break; | |
2058 | case TC: tmpreg=0x003; break; | |
2059 | case ITT0: tmpreg=0x004; break; | |
2060 | case ITT1: tmpreg=0x005; break; | |
2061 | case DTT0: tmpreg=0x006; break; | |
2062 | case DTT1: tmpreg=0x007; break; | |
2063 | ||
2064 | case USP: tmpreg=0x800; break; | |
2065 | case VBR: tmpreg=0x801; break; | |
2066 | case CAAR: tmpreg=0x802; break; | |
2067 | case MSP: tmpreg=0x803; break; | |
2068 | case ISP: tmpreg=0x804; break; | |
2069 | case MMUSR: tmpreg=0x805; break; | |
2070 | case URP: tmpreg=0x806; break; | |
2071 | case SRP: tmpreg=0x807; break; | |
2072 | default: | |
2073 | as_fatal("failed sanity check."); | |
2074 | } | |
2075 | install_operand(s[1],tmpreg); | |
2076 | break; | |
2077 | ||
2078 | case 'k': | |
2079 | tmpreg=get_num(opP->con1,55); | |
2080 | install_operand(s[1],tmpreg&0x7f); | |
2081 | break; | |
2082 | ||
2083 | case 'l': | |
2084 | tmpreg=opP->reg; | |
2085 | if(s[1]=='w') { | |
2086 | if(tmpreg&0x7FF0000) | |
2087 | as_bad("Floating point register in register list"); | |
2088 | insop(reverse_16_bits(tmpreg)); | |
2089 | } else { | |
2090 | if(tmpreg&0x700FFFF) | |
2091 | as_bad("Wrong register in floating-point reglist"); | |
2092 | install_operand(s[1],reverse_8_bits(tmpreg>>16)); | |
2093 | } | |
2094 | break; | |
2095 | ||
2096 | case 'L': | |
2097 | tmpreg=opP->reg; | |
2098 | if(s[1]=='w') { | |
2099 | if(tmpreg&0x7FF0000) | |
2100 | as_bad("Floating point register in register list"); | |
2101 | insop(tmpreg); | |
2102 | } else if(s[1]=='8') { | |
2103 | if(tmpreg&0x0FFFFFF) | |
2104 | as_bad("incorrect register in reglist"); | |
2105 | install_operand(s[1],tmpreg>>24); | |
2106 | } else { | |
2107 | if(tmpreg&0x700FFFF) | |
2108 | as_bad("wrong register in floating-point reglist"); | |
2109 | else | |
2110 | install_operand(s[1],tmpreg>>16); | |
2111 | } | |
2112 | break; | |
2113 | ||
2114 | case 'M': | |
2115 | install_operand(s[1],get_num(opP->con1,60)); | |
2116 | break; | |
2117 | ||
2118 | case 'O': | |
2119 | tmpreg= (opP->mode==DREG) | |
2120 | ? 0x20+opP->reg-DATA | |
2121 | : (get_num(opP->con1,40)&0x1F); | |
2122 | install_operand(s[1],tmpreg); | |
2123 | break; | |
2124 | ||
2125 | case 'Q': | |
2126 | tmpreg=get_num(opP->con1,10); | |
2127 | if(tmpreg==8) | |
2128 | tmpreg=0; | |
2129 | install_operand(s[1],tmpreg); | |
2130 | break; | |
2131 | ||
2132 | case 'R': | |
c50140c8 | 2133 | case 'r': |
6d27d3a2 KR |
2134 | /* This depends on the fact that ADDR registers are |
2135 | eight more than their corresponding DATA regs, so | |
2136 | the result will have the ADDR_REG bit set */ | |
2137 | install_operand(s[1],opP->reg-DATA); | |
2138 | break; | |
2139 | ||
2140 | case 's': | |
2141 | if(opP->reg==FPI) tmpreg=0x1; | |
2142 | else if(opP->reg==FPS) tmpreg=0x2; | |
2143 | else if(opP->reg==FPC) tmpreg=0x4; | |
2144 | else as_fatal("failed sanity check."); | |
2145 | install_operand(s[1],tmpreg); | |
2146 | break; | |
2147 | ||
2148 | case 'S': /* Ignore it */ | |
2149 | break; | |
2150 | ||
2151 | case 'T': | |
2152 | install_operand(s[1],get_num(opP->con1,30)); | |
2153 | break; | |
2154 | ||
2155 | case 'U': /* Ignore it */ | |
2156 | break; | |
2157 | ||
2158 | case 'c': | |
2159 | switch (opP->reg) { | |
2160 | case NC: tmpreg = 0; break; | |
2161 | case DC: tmpreg = 1; break; | |
2162 | case IC: tmpreg = 2; break; | |
2163 | case BC: tmpreg = 3; break; | |
2164 | default: | |
2165 | as_fatal("failed sanity check"); | |
2166 | } /* switch on cache token */ | |
2167 | install_operand(s[1], tmpreg); | |
2168 | break; | |
a39116f1 | 2169 | #ifndef NO_68851 |
6d27d3a2 KR |
2170 | /* JF: These are out of order, I fear. */ |
2171 | case 'f': | |
2172 | switch (opP->reg) { | |
2173 | case SFC: | |
2174 | tmpreg=0; | |
2175 | break; | |
2176 | case DFC: | |
2177 | tmpreg=1; | |
2178 | break; | |
2179 | default: | |
2180 | as_fatal("failed sanity check."); | |
2181 | } | |
2182 | install_operand(s[1],tmpreg); | |
2183 | break; | |
2184 | ||
2185 | case 'P': | |
2186 | switch(opP->reg) { | |
2187 | case TC: | |
2188 | tmpreg=0; | |
2189 | break; | |
2190 | case CAL: | |
2191 | tmpreg=4; | |
2192 | break; | |
2193 | case VAL: | |
2194 | tmpreg=5; | |
2195 | break; | |
2196 | case SCC: | |
2197 | tmpreg=6; | |
2198 | break; | |
2199 | case AC: | |
2200 | tmpreg=7; | |
2201 | break; | |
2202 | default: | |
2203 | as_fatal("failed sanity check."); | |
2204 | } | |
2205 | install_operand(s[1],tmpreg); | |
2206 | break; | |
2207 | ||
2208 | case 'V': | |
2209 | if (opP->reg == VAL) | |
2210 | break; | |
2211 | as_fatal("failed sanity check."); | |
2212 | ||
2213 | case 'W': | |
2214 | switch(opP->reg) { | |
2215 | ||
2216 | case DRP: | |
2217 | tmpreg=1; | |
2218 | break; | |
2219 | case SRP: | |
2220 | tmpreg=2; | |
2221 | break; | |
2222 | case CRP: | |
2223 | tmpreg=3; | |
2224 | break; | |
2225 | default: | |
2226 | as_fatal("failed sanity check."); | |
2227 | } | |
2228 | install_operand(s[1],tmpreg); | |
2229 | break; | |
2230 | ||
2231 | case 'X': | |
2232 | switch (opP->reg) { | |
2233 | case BAD: case BAD+1: case BAD+2: case BAD+3: | |
2234 | case BAD+4: case BAD+5: case BAD+6: case BAD+7: | |
2235 | tmpreg = (4 << 10) | ((opP->reg - BAD) << 2); | |
2236 | break; | |
2237 | ||
2238 | case BAC: case BAC+1: case BAC+2: case BAC+3: | |
2239 | case BAC+4: case BAC+5: case BAC+6: case BAC+7: | |
2240 | tmpreg = (5 << 10) | ((opP->reg - BAC) << 2); | |
2241 | break; | |
2242 | ||
2243 | default: | |
2244 | as_fatal("failed sanity check."); | |
2245 | } | |
2246 | install_operand(s[1], tmpreg); | |
2247 | break; | |
2248 | case 'Y': | |
2249 | know(opP->reg == PSR); | |
2250 | break; | |
2251 | case 'Z': | |
2252 | know(opP->reg == PCSR); | |
2253 | break; | |
f8701a3f | 2254 | #endif /* m68851 */ |
4134a793 KR |
2255 | case '3': |
2256 | switch (opP->reg) | |
2257 | { | |
2258 | case TT0: | |
2259 | tmpreg = 2; | |
2260 | break; | |
2261 | case TT1: | |
2262 | tmpreg = 3; | |
2263 | break; | |
2264 | default: | |
2265 | as_fatal ("failed sanity check"); | |
2266 | } | |
2267 | install_operand (s[1], tmpreg); | |
2268 | break; | |
2269 | case 't': | |
2270 | tmpreg = get_num (opP->con1, 20); | |
2271 | install_operand (s[1], tmpreg); | |
2272 | break; | |
2273 | case '_': /* used only for move16 absolute 32-bit address */ | |
6d27d3a2 | 2274 | tmpreg=get_num(opP->con1,80); |
4134a793 KR |
2275 | addword (tmpreg >> 16); |
2276 | addword (tmpreg & 0xFFFF); | |
6d27d3a2 KR |
2277 | break; |
2278 | default: | |
4134a793 KR |
2279 | as_fatal("Internal error: Operand type %c unknown in line %d of file \"%s\"", |
2280 | s[0], __LINE__, __FILE__); | |
6d27d3a2 KR |
2281 | } |
2282 | } | |
2283 | /* By the time whe get here (FINALLY) the_ins contains the complete | |
2284 | instruction, ready to be emitted. . . */ | |
7c15cbe8 RP |
2285 | } /* m68k_ip() */ |
2286 | ||
2287 | /* | |
2288 | * get_regs := '/' + ? | |
2289 | * | '-' + <register> | |
2290 | * | '-' + <register> + ? | |
2291 | * | <empty> | |
2292 | * ; | |
2293 | * | |
6d27d3a2 | 2294 | |
7c15cbe8 RP |
2295 | * The idea here must be to scan in a set of registers but I don't |
2296 | * understand it. Looks awfully sloppy to me but I don't have any doc on | |
2297 | * this format so... | |
6d27d3a2 KR |
2298 | |
2299 | * | |
7c15cbe8 RP |
2300 | * |
2301 | */ | |
fecd2382 RP |
2302 | |
2303 | static int get_regs(i,str,opP) | |
f8701a3f SC |
2304 | int i; |
2305 | struct m68k_op *opP; | |
2306 | char *str; | |
fecd2382 | 2307 | { |
f8701a3f SC |
2308 | /* 26, 25, 24, 23-16, 15-8, 0-7 */ |
2309 | /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */ | |
2310 | unsigned long cur_regs = 0; | |
2311 | int reg1, | |
2312 | reg2; | |
6d27d3a2 | 2313 | |
fecd2382 | 2314 | #define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\ |
a39116f1 RP |
2315 | else if(x==FPS) cur_regs|=(1<<25);\ |
2316 | else if(x==FPC) cur_regs|=(1<<26);\ | |
2317 | else cur_regs|=(1<<(x-1)); } | |
6d27d3a2 | 2318 | |
f8701a3f SC |
2319 | reg1=i; |
2320 | for(;;) { | |
2321 | if(*str=='/') { | |
2322 | ADD_REG(reg1); | |
2323 | str++; | |
2324 | } else if(*str=='-') { | |
2325 | str++; | |
2326 | reg2=m68k_reg_parse(&str); | |
2327 | if(reg2<DATA || reg2>=FPREG+8 || reg1==FPI || reg1==FPS || reg1==FPC) { | |
2328 | opP->error="unknown register in register list"; | |
2329 | return FAIL; | |
2330 | } | |
2331 | while(reg1<=reg2) { | |
2332 | ADD_REG(reg1); | |
2333 | reg1++; | |
2334 | } | |
2335 | if(*str=='\0') | |
2336 | break; | |
2337 | } else if(*str=='\0') { | |
2338 | ADD_REG(reg1); | |
2339 | break; | |
2340 | } else { | |
2341 | opP->error="unknow character in register list"; | |
2342 | return FAIL; | |
2343 | } | |
2344 | /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */ | |
2345 | if (*str=='/') | |
2346 | str ++; | |
2347 | reg1=m68k_reg_parse(&str); | |
2348 | if((reg1<DATA || reg1>=FPREG+8) && !(reg1==FPI || reg1==FPS || reg1==FPC)) { | |
2349 | opP->error="unknown register in register list"; | |
2350 | return FAIL; | |
2351 | } | |
a39116f1 | 2352 | } |
f8701a3f SC |
2353 | opP->reg=cur_regs; |
2354 | return OK; | |
fecd2382 RP |
2355 | } /* get_regs() */ |
2356 | ||
2357 | static int reverse_16_bits(in) | |
f8701a3f | 2358 | int in; |
fecd2382 | 2359 | { |
f8701a3f SC |
2360 | int out=0; |
2361 | int n; | |
6d27d3a2 | 2362 | |
f8701a3f SC |
2363 | static int mask[16] = { |
2364 | 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080, | |
2365 | 0x0100,0x0200,0x0400,0x0800,0x1000,0x2000,0x4000,0x8000 | |
2366 | }; | |
2367 | for(n=0;n<16;n++) { | |
2368 | if(in&mask[n]) | |
2369 | out|=mask[15-n]; | |
2370 | } | |
2371 | return out; | |
fecd2382 RP |
2372 | } /* reverse_16_bits() */ |
2373 | ||
2374 | static int reverse_8_bits(in) | |
f8701a3f | 2375 | int in; |
fecd2382 | 2376 | { |
f8701a3f SC |
2377 | int out=0; |
2378 | int n; | |
6d27d3a2 | 2379 | |
f8701a3f SC |
2380 | static int mask[8] = { |
2381 | 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080, | |
2382 | }; | |
6d27d3a2 | 2383 | |
f8701a3f SC |
2384 | for(n=0;n<8;n++) { |
2385 | if(in&mask[n]) | |
2386 | out|=mask[7-n]; | |
2387 | } | |
2388 | return out; | |
fecd2382 RP |
2389 | } /* reverse_8_bits() */ |
2390 | ||
2391 | static void install_operand(mode,val) | |
f8701a3f SC |
2392 | int mode; |
2393 | int val; | |
fecd2382 | 2394 | { |
f8701a3f SC |
2395 | switch(mode) { |
2396 | case 's': | |
2397 | the_ins.opcode[0]|=val & 0xFF; /* JF FF is for M kludge */ | |
2398 | break; | |
2399 | case 'd': | |
2400 | the_ins.opcode[0]|=val<<9; | |
2401 | break; | |
2402 | case '1': | |
2403 | the_ins.opcode[1]|=val<<12; | |
2404 | break; | |
2405 | case '2': | |
2406 | the_ins.opcode[1]|=val<<6; | |
2407 | break; | |
2408 | case '3': | |
2409 | the_ins.opcode[1]|=val; | |
2410 | break; | |
2411 | case '4': | |
2412 | the_ins.opcode[2]|=val<<12; | |
2413 | break; | |
2414 | case '5': | |
2415 | the_ins.opcode[2]|=val<<6; | |
2416 | break; | |
2417 | case '6': | |
2418 | /* DANGER! This is a hack to force cas2l and cas2w cmds | |
2419 | to be three words long! */ | |
2420 | the_ins.numo++; | |
2421 | the_ins.opcode[2]|=val; | |
2422 | break; | |
2423 | case '7': | |
2424 | the_ins.opcode[1]|=val<<7; | |
2425 | break; | |
2426 | case '8': | |
2427 | the_ins.opcode[1]|=val<<10; | |
2428 | break; | |
2429 | #ifndef NO_68851 | |
2430 | case '9': | |
2431 | the_ins.opcode[1]|=val<<5; | |
2432 | break; | |
2433 | #endif | |
6d27d3a2 | 2434 | |
f8701a3f SC |
2435 | case 't': |
2436 | the_ins.opcode[1]|=(val<<10)|(val<<7); | |
2437 | break; | |
2438 | case 'D': | |
2439 | the_ins.opcode[1]|=(val<<12)|val; | |
2440 | break; | |
2441 | case 'g': | |
2442 | the_ins.opcode[0]|=val=0xff; | |
2443 | break; | |
2444 | case 'i': | |
2445 | the_ins.opcode[0]|=val<<9; | |
2446 | break; | |
2447 | case 'C': | |
2448 | the_ins.opcode[1]|=val; | |
2449 | break; | |
2450 | case 'j': | |
2451 | the_ins.opcode[1]|=val; | |
2452 | the_ins.numo++; /* What a hack */ | |
2453 | break; | |
2454 | case 'k': | |
2455 | the_ins.opcode[1]|=val<<4; | |
2456 | break; | |
2457 | case 'b': | |
2458 | case 'w': | |
2459 | case 'l': | |
2460 | break; | |
2461 | case 'e': | |
2462 | the_ins.opcode[0] |= (val << 6); | |
2463 | break; | |
2464 | case 'L': | |
2465 | the_ins.opcode[1] = (val >> 16); | |
2466 | the_ins.opcode[2] = val & 0xffff; | |
2467 | break; | |
2468 | case 'c': | |
2469 | default: | |
2470 | as_fatal("failed sanity check."); | |
2471 | } | |
fecd2382 RP |
2472 | } /* install_operand() */ |
2473 | ||
2474 | static void install_gen_operand(mode,val) | |
f8701a3f SC |
2475 | int mode; |
2476 | int val; | |
fecd2382 | 2477 | { |
f8701a3f SC |
2478 | switch(mode) { |
2479 | case 's': | |
2480 | the_ins.opcode[0]|=val; | |
2481 | break; | |
2482 | case 'd': | |
2483 | /* This is a kludge!!! */ | |
2484 | the_ins.opcode[0]|=(val&0x07)<<9|(val&0x38)<<3; | |
2485 | break; | |
2486 | case 'b': | |
2487 | case 'w': | |
2488 | case 'l': | |
2489 | case 'f': | |
2490 | case 'F': | |
2491 | case 'x': | |
2492 | case 'p': | |
2493 | the_ins.opcode[0]|=val; | |
2494 | break; | |
2495 | /* more stuff goes here */ | |
2496 | default: | |
2497 | as_fatal("failed sanity check."); | |
2498 | } | |
fecd2382 RP |
2499 | } /* install_gen_operand() */ |
2500 | ||
7c15cbe8 RP |
2501 | /* |
2502 | * verify that we have some number of paren pairs, do m68k_ip_op(), and | |
2503 | * then deal with the bitfield hack. | |
2504 | */ | |
2505 | ||
fecd2382 | 2506 | static char *crack_operand(str,opP) |
f8701a3f SC |
2507 | register char *str; |
2508 | register struct m68k_op *opP; | |
fecd2382 | 2509 | { |
f8701a3f SC |
2510 | register int parens; |
2511 | register int c; | |
2512 | register char *beg_str; | |
6d27d3a2 | 2513 | |
f8701a3f SC |
2514 | if(!str) { |
2515 | return str; | |
2516 | } | |
2517 | beg_str=str; | |
2518 | for(parens=0;*str && (parens>0 || notend(str));str++) { | |
2519 | if(*str=='(') parens++; | |
2520 | else if(*str==')') { | |
2521 | if(!parens) { /* ERROR */ | |
2522 | opP->error="Extra )"; | |
2523 | return str; | |
2524 | } | |
2525 | --parens; | |
2526 | } | |
2527 | } | |
2528 | if(!*str && parens) { /* ERROR */ | |
2529 | opP->error="Missing )"; | |
2530 | return str; | |
2531 | } | |
2532 | c= *str; | |
2533 | *str='\0'; | |
2534 | if(m68k_ip_op(beg_str,opP)==FAIL) { | |
2535 | *str=c; | |
fecd2382 RP |
2536 | return str; |
2537 | } | |
2538 | *str=c; | |
f8701a3f SC |
2539 | if(c=='}') |
2540 | c= *++str; /* JF bitfield hack */ | |
2541 | if(c) { | |
2542 | c= *++str; | |
2543 | if(!c) | |
2544 | as_bad("Missing operand"); | |
2545 | } | |
fecd2382 RP |
2546 | return str; |
2547 | } | |
2548 | ||
2549 | /* See the comment up above where the #define notend(... is */ | |
2550 | #if 0 | |
2551 | notend(s) | |
f8701a3f | 2552 | char *s; |
fecd2382 | 2553 | { |
f8701a3f SC |
2554 | if(*s==',') return 0; |
2555 | if(*s=='{' || *s=='}') | |
2556 | return 0; | |
2557 | if(*s!=':') return 1; | |
2558 | /* This kludge here is for the division cmd, which is a kludge */ | |
2559 | if(index("aAdD#",s[1])) return 0; | |
2560 | return 1; | |
fecd2382 RP |
2561 | } |
2562 | #endif | |
2563 | ||
2564 | /* This is the guts of the machine-dependent assembler. STR points to a | |
7c15cbe8 | 2565 | machine dependent instruction. This function is supposed to emit |
fecd2382 | 2566 | the frags/bytes it assembles to. |
a39116f1 | 2567 | */ |
a933d598 SC |
2568 | |
2569 | void | |
2570 | insert_reg(regname, regnum) | |
2571 | char *regname; | |
2572 | int regnum; | |
2573 | { | |
2574 | char buf[100]; | |
2575 | int i; | |
2576 | symbol_table_insert(symbol_new(regname, SEG_REGISTER, regnum, &zero_address_frag)); | |
2577 | ||
2578 | for (i = 0; regname[i]; i++) | |
2579 | buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i]; | |
2580 | buf[i] = '\0'; | |
6d27d3a2 | 2581 | |
a933d598 SC |
2582 | symbol_table_insert(symbol_new(buf, SEG_REGISTER, regnum, &zero_address_frag)); |
2583 | } | |
2584 | ||
4134a793 | 2585 | static const struct { |
6d27d3a2 | 2586 | char *name; |
a933d598 | 2587 | int number; |
4134a793 | 2588 | } init_table[] = { |
a933d598 SC |
2589 | "d0", DATA0, |
2590 | "d1", DATA1, | |
2591 | "d2", DATA2, | |
2592 | "d3", DATA3, | |
2593 | "d4", DATA4, | |
2594 | "d5", DATA5, | |
2595 | "d6", DATA6, | |
2596 | "d7", DATA7, | |
2597 | "a0", ADDR0, | |
2598 | "a1", ADDR1, | |
2599 | "a2", ADDR2, | |
2600 | "a3", ADDR3, | |
2601 | "a4", ADDR4, | |
2602 | "a5", ADDR5, | |
2603 | "a6", ADDR6, | |
2604 | "fp", ADDR6, | |
2605 | "a7", ADDR7, | |
2606 | "sp", ADDR7, | |
2607 | "fp0", FP0, | |
2608 | "fp1", FP1, | |
2609 | "fp2", FP2, | |
2610 | "fp3", FP3, | |
2611 | "fp4", FP4, | |
2612 | "fp5", FP5, | |
2613 | "fp6", FP6, | |
2614 | "fp7", FP7, | |
2615 | "fpi", FPI, | |
2616 | "fpiar", FPI, | |
2617 | "fpc", FPI, | |
2618 | "fps", FPS, | |
2619 | "fpsr", FPS, | |
2620 | "fpc", FPC, | |
2621 | "fpcr", FPC, | |
2622 | ||
2623 | "cop0", COP0, | |
2624 | "cop1", COP1, | |
2625 | "cop2", COP2, | |
2626 | "cop3", COP3, | |
2627 | "cop4", COP4, | |
2628 | "cop5", COP5, | |
2629 | "cop6", COP6, | |
2630 | "cop7", COP7, | |
6d27d3a2 KR |
2631 | "pc", PC, |
2632 | "zpc", ZPC, | |
2633 | "sr", SR, | |
a933d598 | 2634 | |
6d27d3a2 KR |
2635 | "ccr", CCR, |
2636 | "cc", CCR, | |
a933d598 | 2637 | |
6d27d3a2 KR |
2638 | "usp", USP, |
2639 | "isp", ISP, | |
a933d598 SC |
2640 | "sfc", SFC, |
2641 | "dfc", DFC, | |
2642 | "cacr", CACR, | |
2643 | "caar", CAAR, | |
2644 | ||
2645 | "vbr", VBR, | |
2646 | ||
2647 | "msp", MSP, | |
2648 | "itt0", ITT0, | |
2649 | "itt1", ITT1, | |
2650 | "dtt0", DTT0, | |
2651 | "dtt1", DTT1, | |
2652 | "mmusr", MMUSR, | |
2653 | "tc", TC, | |
2654 | "srp", SRP, | |
2655 | "urp", URP, | |
2656 | ||
a933d598 SC |
2657 | "ac", AC, |
2658 | "bc", BC, | |
2659 | "cal", CAL, | |
2660 | "crp", CRP, | |
2661 | "drp", DRP, | |
2662 | "pcsr", PCSR, | |
2663 | "psr", PSR, | |
2664 | "scc", SCC, | |
2665 | "val", VAL, | |
2666 | "bad0", BAD0, | |
2667 | "bad1", BAD1, | |
2668 | "bad2", BAD2, | |
2669 | "bad3", BAD3, | |
2670 | "bad4", BAD4, | |
2671 | "bad5", BAD5, | |
2672 | "bad6", BAD6, | |
2673 | "bad7", BAD7, | |
2674 | "bac0", BAC0, | |
2675 | "bac1", BAC1, | |
2676 | "bac2", BAC2, | |
2677 | "bac3", BAC3, | |
2678 | "bac4", BAC4, | |
2679 | "bac5", BAC5, | |
2680 | "bac6", BAC6, | |
2681 | "bac7", BAC7, | |
a933d598 SC |
2682 | |
2683 | "ic", IC, | |
2684 | "dc", DC, | |
2685 | "nc", NC, | |
2686 | ||
4134a793 KR |
2687 | "tt0", TT0, |
2688 | "tt1", TT1, | |
2689 | /* 68ec030 versions of same */ | |
2690 | "ac0", TT0, | |
2691 | "ac1", TT1, | |
2692 | /* 68ec030 access control unit, identical to 030 MMU status reg */ | |
2693 | "acusr", PSR, | |
2694 | ||
a933d598 SC |
2695 | 0, |
2696 | ||
2697 | }; | |
2698 | ||
2699 | ||
2700 | void | |
2701 | init_regtable() | |
2702 | { | |
2703 | int i; | |
6d27d3a2 | 2704 | for (i = 0; init_table[i].name; i++) |
a933d598 | 2705 | insert_reg(init_table[i].name, init_table[i].number); |
a933d598 | 2706 | } |
6d27d3a2 | 2707 | |
a933d598 | 2708 | |
fecd2382 | 2709 | void |
6d27d3a2 KR |
2710 | md_assemble(str) |
2711 | char *str; | |
fecd2382 | 2712 | { |
f8701a3f SC |
2713 | char *er; |
2714 | short *fromP; | |
2715 | char *toP = NULL; | |
2716 | int m,n = 0; | |
2717 | char *to_beg_P; | |
2718 | int shorts_this_frag; | |
4134a793 | 2719 | static int done_first_time; |
6d27d3a2 | 2720 | |
4134a793 | 2721 | if (!done_first_time) |
148eb5dd | 2722 | { |
4134a793 KR |
2723 | done_first_time = 1; |
2724 | ||
2725 | if (cpu_of_arch (current_architecture) == 0) | |
2726 | { | |
2727 | enum m68k_architecture cpu_type; | |
148eb5dd ILT |
2728 | |
2729 | #ifndef TARGET_CPU | |
4134a793 | 2730 | cpu_type = m68020; |
148eb5dd | 2731 | #else |
4134a793 KR |
2732 | if (strcmp (TARGET_CPU, "m68000") == 0) |
2733 | cpu_type = m68000; | |
2734 | else if (strcmp (TARGET_CPU, "m68010") == 0) | |
2735 | cpu_type = m68010; | |
2736 | else if (strcmp (TARGET_CPU, "m68020") == 0 | |
2737 | || strcmp (TARGET_CPU, "m68k") == 0) | |
2738 | cpu_type = m68020; | |
2739 | else if (strcmp (TARGET_CPU, "m68030") == 0) | |
2740 | cpu_type = m68030; | |
2741 | else if (strcmp (TARGET_CPU, "m68040") == 0) | |
2742 | cpu_type = m68040; | |
2743 | else | |
2744 | cpu_type = m68020; | |
148eb5dd ILT |
2745 | #endif |
2746 | ||
4134a793 KR |
2747 | /* If float or mmu were specified, just default cpu. */ |
2748 | if (current_architecture != 0) | |
2749 | current_architecture |= cpu_type; | |
2750 | else | |
2751 | { | |
2752 | if ((cpu_type & m68020up) != 0) | |
2753 | current_architecture = (cpu_type | |
865a2edf | 2754 | #ifndef NO_68881 |
4134a793 | 2755 | | m68881 |
865a2edf MT |
2756 | #endif |
2757 | #ifndef NO_68851 | |
4134a793 | 2758 | | m68851 |
865a2edf | 2759 | #endif |
4134a793 KR |
2760 | ); |
2761 | else | |
2762 | current_architecture = cpu_type; | |
2763 | } | |
2764 | } | |
2765 | if (cpu_of_arch (current_architecture) == m68000 | |
2766 | && (current_architecture & m68881) != 0) | |
2767 | { | |
2768 | as_bad ("incompatible processors 68000 and 68881 specified"); | |
148eb5dd | 2769 | } |
4134a793 | 2770 | done_first_time = 1; |
148eb5dd | 2771 | } |
6d27d3a2 | 2772 | |
f8701a3f SC |
2773 | memset((char *)(&the_ins), '\0', sizeof(the_ins)); /* JF for paranoia sake */ |
2774 | m68k_ip(str); | |
2775 | er=the_ins.error; | |
2776 | if(!er) { | |
2777 | for(n=the_ins.numargs;n;--n) | |
2778 | if(the_ins.operands[n].error) { | |
2779 | er=the_ins.operands[n].error; | |
2780 | break; | |
2781 | } | |
fecd2382 | 2782 | } |
f8701a3f | 2783 | if(er) { |
6d27d3a2 | 2784 | as_bad("%s -- statement `%s' ignored",er,str); |
f8701a3f | 2785 | return; |
fecd2382 | 2786 | } |
6d27d3a2 | 2787 | |
f8701a3f SC |
2788 | if(the_ins.nfrag==0) { /* No frag hacking involved; just put it out */ |
2789 | toP=frag_more(2*the_ins.numo); | |
2790 | fromP= &the_ins.opcode[0]; | |
2791 | for(m=the_ins.numo;m;--m) { | |
2792 | md_number_to_chars(toP,(long)(*fromP),2); | |
2793 | toP+=2; | |
2794 | fromP++; | |
2795 | } | |
2796 | /* put out symbol-dependent info */ | |
2797 | for(m=0;m<the_ins.nrel;m++) { | |
2798 | switch(the_ins.reloc[m].wid) { | |
2799 | case 'B': | |
2800 | n=1; | |
2801 | break; | |
2802 | case 'b': | |
2803 | n=1; | |
2804 | break; | |
2805 | case '3': | |
2806 | n=2; | |
2807 | break; | |
2808 | case 'w': | |
2809 | n=2; | |
2810 | break; | |
2811 | case 'l': | |
2812 | n=4; | |
2813 | break; | |
2814 | default: | |
2815 | as_fatal("Don't know how to figure width of %c in md_assemble()",the_ins.reloc[m].wid); | |
2816 | } | |
6d27d3a2 | 2817 | |
f8701a3f SC |
2818 | fix_new(frag_now, |
2819 | (toP-frag_now->fr_literal)-the_ins.numo*2+the_ins.reloc[m].n, | |
2820 | n, | |
2821 | the_ins.reloc[m].add, | |
2822 | the_ins.reloc[m].sub, | |
2823 | the_ins.reloc[m].off, | |
2824 | the_ins.reloc[m].pcrel, | |
2825 | NO_RELOC); | |
2826 | } | |
2827 | return; | |
2828 | } | |
6d27d3a2 | 2829 | |
f8701a3f SC |
2830 | /* There's some frag hacking */ |
2831 | for(n=0,fromP= &the_ins.opcode[0];n<the_ins.nfrag;n++) { | |
2832 | int wid; | |
6d27d3a2 | 2833 | |
f8701a3f SC |
2834 | if(n==0) wid=2*the_ins.fragb[n].fragoff; |
2835 | else wid=2*(the_ins.numo-the_ins.fragb[n-1].fragoff); | |
2836 | toP=frag_more(wid); | |
2837 | to_beg_P=toP; | |
2838 | shorts_this_frag=0; | |
2839 | for(m=wid/2;m;--m) { | |
2840 | md_number_to_chars(toP,(long)(*fromP),2); | |
2841 | toP+=2; | |
2842 | fromP++; | |
2843 | shorts_this_frag++; | |
2844 | } | |
2845 | for(m=0;m<the_ins.nrel;m++) { | |
2846 | if((the_ins.reloc[m].n)>= 2*shorts_this_frag /* 2*the_ins.fragb[n].fragoff */) { | |
2847 | the_ins.reloc[m].n-= 2*shorts_this_frag /* 2*the_ins.fragb[n].fragoff */; | |
2848 | break; | |
2849 | } | |
2850 | wid=the_ins.reloc[m].wid; | |
2851 | if(wid==0) | |
2852 | continue; | |
2853 | the_ins.reloc[m].wid=0; | |
2854 | wid = (wid=='b') ? 1 : (wid=='w') ? 2 : (wid=='l') ? 4 : 4000; | |
6d27d3a2 | 2855 | |
f8701a3f SC |
2856 | fix_new(frag_now, |
2857 | (toP-frag_now->fr_literal)-the_ins.numo*2+the_ins.reloc[m].n, | |
2858 | wid, | |
2859 | the_ins.reloc[m].add, | |
2860 | the_ins.reloc[m].sub, | |
2861 | the_ins.reloc[m].off, | |
2862 | the_ins.reloc[m].pcrel, | |
2863 | NO_RELOC); | |
2864 | } | |
2865 | /* know(the_ins.fragb[n].fadd); */ | |
2866 | (void)frag_var(rs_machine_dependent,10,0,(relax_substateT)(the_ins.fragb[n].fragty), | |
2867 | the_ins.fragb[n].fadd,the_ins.fragb[n].foff,to_beg_P); | |
2868 | } | |
2869 | n=(the_ins.numo-the_ins.fragb[n-1].fragoff); | |
fecd2382 | 2870 | shorts_this_frag=0; |
f8701a3f SC |
2871 | if(n) { |
2872 | toP=frag_more(n*sizeof(short)); | |
2873 | while(n--) { | |
2874 | md_number_to_chars(toP,(long)(*fromP),2); | |
2875 | toP+=2; | |
2876 | fromP++; | |
2877 | shorts_this_frag++; | |
2878 | } | |
fecd2382 RP |
2879 | } |
2880 | for(m=0;m<the_ins.nrel;m++) { | |
f8701a3f | 2881 | int wid; |
6d27d3a2 | 2882 | |
f8701a3f SC |
2883 | wid=the_ins.reloc[m].wid; |
2884 | if(wid==0) | |
2885 | continue; | |
2886 | the_ins.reloc[m].wid=0; | |
2887 | wid = (wid=='b') ? 1 : (wid=='w') ? 2 : (wid=='l') ? 4 : 4000; | |
6d27d3a2 | 2888 | |
f8701a3f SC |
2889 | fix_new(frag_now, |
2890 | (the_ins.reloc[m].n + toP-frag_now->fr_literal)-/* the_ins.numo */ shorts_this_frag*2, | |
2891 | wid, | |
2892 | the_ins.reloc[m].add, | |
2893 | the_ins.reloc[m].sub, | |
2894 | the_ins.reloc[m].off, | |
2895 | the_ins.reloc[m].pcrel, | |
2896 | NO_RELOC); | |
fecd2382 RP |
2897 | } |
2898 | } | |
2899 | ||
f8701a3f | 2900 | |
f8701a3f | 2901 | |
f8701a3f SC |
2902 | |
2903 | ||
fecd2382 | 2904 | void |
a39116f1 | 2905 | md_begin() |
fecd2382 | 2906 | { |
f8701a3f SC |
2907 | /* |
2908 | * md_begin -- set up hash tables with 68000 instructions. | |
2909 | * similar to what the vax assembler does. ---phr | |
2910 | */ | |
2911 | /* RMS claims the thing to do is take the m68k-opcode.h table, and make | |
2912 | a copy of it at runtime, adding in the information we want but isn't | |
2913 | there. I think it'd be better to have an awk script hack the table | |
2914 | at compile time. Or even just xstr the table and use it as-is. But | |
2915 | my lord ghod hath spoken, so we do it this way. Excuse the ugly var | |
2916 | names. */ | |
6d27d3a2 | 2917 | |
f8701a3f SC |
2918 | register const struct m68k_opcode *ins; |
2919 | register struct m68k_incant *hack, | |
2920 | *slak; | |
2921 | register char *retval = 0; /* empty string, or error msg text */ | |
2922 | register unsigned int i; | |
2923 | register char c; | |
6d27d3a2 | 2924 | |
f8701a3f SC |
2925 | if ((op_hash = hash_new()) == NULL) |
2926 | as_fatal("Virtual memory exhausted"); | |
6d27d3a2 | 2927 | |
f8701a3f SC |
2928 | obstack_begin(&robyn,4000); |
2929 | for (ins = m68k_opcodes; ins < endop; ins++) { | |
2930 | hack=slak=(struct m68k_incant *)obstack_alloc(&robyn,sizeof(struct m68k_incant)); | |
2931 | do { | |
2932 | /* we *could* ignore insns that don't match our | |
2933 | arch here but just leaving them out of the | |
2934 | hash. */ | |
2935 | slak->m_operands=ins->args; | |
2936 | slak->m_opnum=strlen(slak->m_operands)/2; | |
2937 | slak->m_arch = ins->arch; | |
2938 | slak->m_opcode=ins->opcode; | |
2939 | /* This is kludgey */ | |
2940 | slak->m_codenum=((ins->match)&0xffffL) ? 2 : 1; | |
2941 | if((ins+1)!=endop && !strcmp(ins->name,(ins+1)->name)) { | |
2942 | slak->m_next=(struct m68k_incant *) obstack_alloc(&robyn,sizeof(struct m68k_incant)); | |
2943 | ins++; | |
2944 | } else | |
2945 | slak->m_next=0; | |
2946 | slak=slak->m_next; | |
2947 | } while(slak); | |
6d27d3a2 | 2948 | |
f8701a3f SC |
2949 | retval = hash_insert (op_hash, ins->name,(char *)hack); |
2950 | /* Didn't his mommy tell him about null pointers? */ | |
2951 | if(retval && *retval) | |
2952 | as_fatal("Internal Error: Can't hash %s: %s",ins->name,retval); | |
2953 | } | |
6d27d3a2 | 2954 | |
f8701a3f SC |
2955 | for (i = 0; i < sizeof(mklower_table) ; i++) |
2956 | mklower_table[i] = (isupper(c = (char) i)) ? tolower(c) : c; | |
6d27d3a2 | 2957 | |
f8701a3f SC |
2958 | for (i = 0 ; i < sizeof(notend_table) ; i++) { |
2959 | notend_table[i] = 0; | |
2960 | alt_notend_table[i] = 0; | |
2961 | } | |
2962 | notend_table[','] = 1; | |
2963 | notend_table['{'] = 1; | |
2964 | notend_table['}'] = 1; | |
2965 | alt_notend_table['a'] = 1; | |
2966 | alt_notend_table['A'] = 1; | |
2967 | alt_notend_table['d'] = 1; | |
2968 | alt_notend_table['D'] = 1; | |
2969 | alt_notend_table['#'] = 1; | |
2970 | alt_notend_table['f'] = 1; | |
2971 | alt_notend_table['F'] = 1; | |
fecd2382 | 2972 | #ifdef REGISTER_PREFIX |
f8701a3f | 2973 | alt_notend_table[REGISTER_PREFIX] = 1; |
fecd2382 | 2974 | #endif |
f8701a3f SC |
2975 | |
2976 | init_regtable(); | |
fecd2382 RP |
2977 | } |
2978 | ||
2979 | #if 0 | |
2980 | #define notend(s) ((*s == ',' || *s == '}' || *s == '{' \ | |
a39116f1 RP |
2981 | || (*s == ':' && strchr("aAdD#", s[1]))) \ |
2982 | ? 0 : 1) | |
fecd2382 RP |
2983 | #endif |
2984 | ||
2985 | /* This funciton is called once, before the assembler exits. It is | |
2986 | supposed to do any final cleanup for this part of the assembler. | |
a39116f1 | 2987 | */ |
fecd2382 | 2988 | void |
a39116f1 | 2989 | md_end() |
fecd2382 RP |
2990 | { |
2991 | } | |
2992 | ||
2993 | /* Equal to MAX_PRECISION in atof-ieee.c */ | |
2994 | #define MAX_LITTLENUMS 6 | |
2995 | ||
2996 | /* Turn a string in input_line_pointer into a floating point constant of type | |
2997 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
2998 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. | |
a39116f1 | 2999 | */ |
fecd2382 | 3000 | char * |
a39116f1 | 3001 | md_atof(type,litP,sizeP) |
fecd2382 RP |
3002 | char type; |
3003 | char *litP; | |
3004 | int *sizeP; | |
3005 | { | |
f8701a3f SC |
3006 | int prec; |
3007 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
3008 | LITTLENUM_TYPE *wordP; | |
3009 | char *t; | |
3010 | char *atof_ieee(); | |
6d27d3a2 | 3011 | |
f8701a3f SC |
3012 | switch(type) { |
3013 | case 'f': | |
3014 | case 'F': | |
3015 | case 's': | |
3016 | case 'S': | |
3017 | prec = 2; | |
3018 | break; | |
6d27d3a2 | 3019 | |
f8701a3f SC |
3020 | case 'd': |
3021 | case 'D': | |
3022 | case 'r': | |
3023 | case 'R': | |
3024 | prec = 4; | |
3025 | break; | |
6d27d3a2 | 3026 | |
f8701a3f SC |
3027 | case 'x': |
3028 | case 'X': | |
3029 | prec = 6; | |
3030 | break; | |
6d27d3a2 | 3031 | |
f8701a3f SC |
3032 | case 'p': |
3033 | case 'P': | |
3034 | prec = 6; | |
3035 | break; | |
6d27d3a2 | 3036 | |
f8701a3f SC |
3037 | default: |
3038 | *sizeP=0; | |
3039 | return "Bad call to MD_ATOF()"; | |
3040 | } | |
3041 | t=atof_ieee(input_line_pointer,type,words); | |
3042 | if(t) | |
3043 | input_line_pointer=t; | |
6d27d3a2 | 3044 | |
f8701a3f SC |
3045 | *sizeP=prec * sizeof(LITTLENUM_TYPE); |
3046 | for(wordP=words;prec--;) { | |
3047 | md_number_to_chars(litP,(long)(*wordP++),sizeof(LITTLENUM_TYPE)); | |
3048 | litP+=sizeof(LITTLENUM_TYPE); | |
3049 | } | |
3050 | return ""; /* Someone should teach Dean about null pointers */ | |
fecd2382 RP |
3051 | } |
3052 | ||
3053 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate | |
3054 | for use in the a.out file, and stores them in the array pointed to by buf. | |
3055 | This knows about the endian-ness of the target machine and does | |
3056 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
3057 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
3058 | LITTLENUMS (shorts, here at least) | |
a39116f1 | 3059 | */ |
fecd2382 | 3060 | void |
a39116f1 | 3061 | md_number_to_chars(buf,val,n) |
fecd2382 RP |
3062 | char *buf; |
3063 | long val; | |
3064 | int n; | |
3065 | { | |
f8701a3f SC |
3066 | switch(n) { |
3067 | case 1: | |
3068 | *buf++=val; | |
3069 | break; | |
3070 | case 2: | |
3071 | *buf++=(val>>8); | |
3072 | *buf++=val; | |
3073 | break; | |
3074 | case 4: | |
3075 | *buf++=(val>>24); | |
3076 | *buf++=(val>>16); | |
3077 | *buf++=(val>>8); | |
3078 | *buf++=val; | |
3079 | break; | |
3080 | default: | |
3081 | as_fatal("failed sanity check."); | |
3082 | } | |
fecd2382 RP |
3083 | } |
3084 | ||
3085 | void | |
a39116f1 RP |
3086 | md_apply_fix(fixP, val) |
3087 | fixS *fixP; | |
3088 | long val; | |
fecd2382 | 3089 | { |
f8701a3f | 3090 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; |
6d27d3a2 | 3091 | |
f8701a3f SC |
3092 | switch(fixP->fx_size) { |
3093 | case 1: | |
3094 | *buf++=val; | |
3095 | break; | |
3096 | case 2: | |
3097 | *buf++=(val>>8); | |
3098 | *buf++=val; | |
3099 | break; | |
3100 | case 4: | |
3101 | *buf++=(val>>24); | |
3102 | *buf++=(val>>16); | |
3103 | *buf++=(val>>8); | |
3104 | *buf++=val; | |
3105 | break; | |
3106 | default: | |
3107 | BAD_CASE (fixP->fx_size); | |
3108 | } | |
fecd2382 RP |
3109 | } |
3110 | ||
3111 | ||
3112 | /* *fragP has been relaxed to its final size, and now needs to have | |
3113 | the bytes inside it modified to conform to the new size There is UGLY | |
3114 | MAGIC here. .. | |
a39116f1 | 3115 | */ |
fecd2382 | 3116 | void |
a39116f1 | 3117 | md_convert_frag(headers, fragP) |
f6e504fe | 3118 | object_headers *headers; |
fecd2382 RP |
3119 | register fragS *fragP; |
3120 | { | |
f8701a3f SC |
3121 | long disp; |
3122 | long ext = 0; | |
6d27d3a2 | 3123 | |
f8701a3f SC |
3124 | /* Address in object code of the displacement. */ |
3125 | register int object_address = fragP -> fr_fix + fragP -> fr_address; | |
6d27d3a2 | 3126 | |
f6e504fe | 3127 | #ifdef IBM_COMPILER_SUX |
f8701a3f SC |
3128 | /* This is wrong but it convinces the native rs6000 compiler to |
3129 | generate the code we want. */ | |
3130 | register char *buffer_address = fragP -> fr_literal; | |
3131 | buffer_address += fragP -> fr_fix; | |
f6e504fe | 3132 | #else /* IBM_COMPILER_SUX */ |
f8701a3f SC |
3133 | /* Address in gas core of the place to store the displacement. */ |
3134 | register char *buffer_address = fragP->fr_fix + fragP->fr_literal; | |
f6e504fe | 3135 | #endif /* IBM_COMPILER_SUX */ |
6d27d3a2 | 3136 | |
f8701a3f | 3137 | /* No longer true: know(fragP->fr_symbol); */ |
6d27d3a2 | 3138 | |
f8701a3f SC |
3139 | /* The displacement of the address, from current location. */ |
3140 | disp = fragP->fr_symbol ? S_GET_VALUE(fragP->fr_symbol) : 0; | |
3141 | disp = (disp + fragP->fr_offset) - object_address; | |
6d27d3a2 | 3142 | |
f8701a3f SC |
3143 | switch(fragP->fr_subtype) { |
3144 | case TAB(BCC68000,BYTE): | |
a39116f1 RP |
3145 | case TAB(BRANCH,BYTE): |
3146 | know(issbyte(disp)); | |
3147 | if(disp==0) | |
3148 | as_bad("short branch with zero offset: use :w"); | |
3149 | fragP->fr_opcode[1]=disp; | |
fecd2382 | 3150 | ext=0; |
a39116f1 | 3151 | break; |
f8701a3f SC |
3152 | case TAB(DBCC,SHORT): |
3153 | know(issword(disp)); | |
a39116f1 RP |
3154 | ext=2; |
3155 | break; | |
f8701a3f SC |
3156 | case TAB(BCC68000,SHORT): |
3157 | case TAB(BRANCH,SHORT): | |
3158 | know(issword(disp)); | |
a39116f1 RP |
3159 | fragP->fr_opcode[1]=0x00; |
3160 | ext=2; | |
3161 | break; | |
f8701a3f SC |
3162 | case TAB(BRANCH,LONG): |
3163 | if (cpu_of_arch(current_architecture) < m68020) { | |
3164 | if (fragP->fr_opcode[0]==0x61) { | |
3165 | fragP->fr_opcode[0]= 0x4E; | |
3166 | fragP->fr_opcode[1]= 0xB9; /* JBSR with ABSL LONG offset */ | |
3167 | subseg_change(SEG_TEXT, 0); | |
6d27d3a2 | 3168 | |
f8701a3f SC |
3169 | fix_new(fragP, |
3170 | fragP->fr_fix, | |
3171 | 4, | |
3172 | fragP->fr_symbol, | |
3173 | 0, | |
3174 | fragP->fr_offset, | |
3175 | 0, | |
3176 | NO_RELOC); | |
6d27d3a2 | 3177 | |
f8701a3f SC |
3178 | fragP->fr_fix+=4; |
3179 | ext=0; | |
3180 | } else if (fragP->fr_opcode[0]==0x60) { | |
3181 | fragP->fr_opcode[0]= 0x4E; | |
3182 | fragP->fr_opcode[1]= 0xF9; /* JMP with ABSL LONG offset */ | |
3183 | subseg_change(SEG_TEXT, 0); | |
3184 | fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset,0, | |
3185 | NO_RELOC); | |
3186 | fragP->fr_fix+=4; | |
3187 | ext=0; | |
3188 | } else { | |
3189 | as_bad("Long branch offset not supported."); | |
3190 | } | |
3191 | } else { | |
3192 | fragP->fr_opcode[1]=0xff; | |
3193 | ext=4; | |
3194 | } | |
3195 | break; | |
3196 | case TAB(BCC68000,LONG): | |
3197 | /* only Bcc 68000 instructions can come here */ | |
3198 | /* change bcc into b!cc/jmp absl long */ | |
3199 | fragP->fr_opcode[0] ^= 0x01; /* invert bcc */ | |
fecd2382 | 3200 | fragP->fr_opcode[1] = 0x6; /* branch offset = 6 */ |
6d27d3a2 | 3201 | |
fecd2382 RP |
3202 | /* JF: these used to be fr_opcode[2,3], but they may be in a |
3203 | different frag, in which case refering to them is a no-no. | |
3204 | Only fr_opcode[0,1] are guaranteed to work. */ | |
6d27d3a2 KR |
3205 | *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */ |
3206 | *buffer_address++ = 0xf9; | |
fecd2382 RP |
3207 | fragP->fr_fix += 2; /* account for jmp instruction */ |
3208 | subseg_change(SEG_TEXT,0); | |
6d27d3a2 | 3209 | fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, |
a39116f1 RP |
3210 | fragP->fr_offset,0, |
3211 | NO_RELOC); | |
fecd2382 RP |
3212 | fragP->fr_fix += 4; |
3213 | ext=0; | |
3214 | break; | |
f8701a3f SC |
3215 | case TAB(DBCC,LONG): |
3216 | /* only DBcc 68000 instructions can come here */ | |
3217 | /* change dbcc into dbcc/jmp absl long */ | |
3218 | /* JF: these used to be fr_opcode[2-7], but that's wrong */ | |
3219 | *buffer_address++ = 0x00; /* branch offset = 4 */ | |
6d27d3a2 KR |
3220 | *buffer_address++ = 0x04; |
3221 | *buffer_address++ = 0x60; /* put in bra pc+6 */ | |
3222 | *buffer_address++ = 0x06; | |
3223 | *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */ | |
3224 | *buffer_address++ = 0xf9; | |
3225 | ||
fecd2382 RP |
3226 | fragP->fr_fix += 6; /* account for bra/jmp instructions */ |
3227 | subseg_change(SEG_TEXT,0); | |
6d27d3a2 | 3228 | fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, |
a39116f1 RP |
3229 | fragP->fr_offset,0, |
3230 | NO_RELOC); | |
fecd2382 RP |
3231 | fragP->fr_fix += 4; |
3232 | ext=0; | |
a39116f1 | 3233 | break; |
f8701a3f SC |
3234 | case TAB(FBRANCH,SHORT): |
3235 | know((fragP->fr_opcode[1]&0x40)==0); | |
a39116f1 RP |
3236 | ext=2; |
3237 | break; | |
f8701a3f SC |
3238 | case TAB(FBRANCH,LONG): |
3239 | fragP->fr_opcode[1]|=0x40; /* Turn on LONG bit */ | |
a39116f1 RP |
3240 | ext=4; |
3241 | break; | |
f8701a3f SC |
3242 | case TAB(PCREL,SHORT): |
3243 | ext=2; | |
a39116f1 | 3244 | break; |
f8701a3f SC |
3245 | case TAB(PCREL,LONG): |
3246 | /* The thing to do here is force it to ABSOLUTE LONG, since | |
3247 | PCREL is really trying to shorten an ABSOLUTE address anyway */ | |
3248 | /* JF FOO This code has not been tested */ | |
3249 | subseg_change(SEG_TEXT,0); | |
a39116f1 RP |
3250 | fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC); |
3251 | if((fragP->fr_opcode[1] & 0x3F) != 0x3A) | |
3252 | as_bad("Internal error (long PC-relative operand) for insn 0x%04lx at 0x%lx", | |
3253 | fragP->fr_opcode[0],fragP->fr_address); | |
3254 | fragP->fr_opcode[1]&= ~0x3F; | |
3255 | fragP->fr_opcode[1]|=0x39; /* Mode 7.1 */ | |
3256 | fragP->fr_fix+=4; | |
3257 | /* md_number_to_chars(buffer_address, | |
3258 | (long)(fragP->fr_symbol->sy_value + fragP->fr_offset), | |
3259 | 4); */ | |
3260 | ext=0; | |
3261 | break; | |
f8701a3f SC |
3262 | case TAB(PCLEA,SHORT): |
3263 | subseg_change(SEG_TEXT,0); | |
a39116f1 RP |
3264 | fix_new(fragP,(int)(fragP->fr_fix),2,fragP->fr_symbol,(symbolS *)0,fragP->fr_offset,1, |
3265 | NO_RELOC); | |
3266 | fragP->fr_opcode[1] &= ~0x3F; | |
3267 | fragP->fr_opcode[1] |= 0x3A; | |
3268 | ext=2; | |
3269 | break; | |
f8701a3f SC |
3270 | case TAB(PCLEA,LONG): |
3271 | subseg_change(SEG_TEXT,0); | |
3272 | fix_new(fragP,(int)(fragP->fr_fix)+2,4,fragP->fr_symbol,(symbolS *)0,fragP->fr_offset+2,1, | |
3273 | NO_RELOC); | |
3274 | *buffer_address++ = 0x01; | |
3275 | *buffer_address++ = 0x70; | |
3276 | fragP->fr_fix+=2; | |
3277 | /* buffer_address+=2; */ | |
3278 | ext=4; | |
a39116f1 | 3279 | break; |
6d27d3a2 | 3280 | |
f8701a3f | 3281 | } /* switch on subtype */ |
6d27d3a2 | 3282 | |
f8701a3f SC |
3283 | if (ext) { |
3284 | md_number_to_chars(buffer_address, (long) disp, (int) ext); | |
3285 | fragP->fr_fix += ext; | |
3286 | /* H_SET_TEXT_SIZE(headers, H_GET_TEXT_SIZE(headers) + ext); */ | |
3287 | } /* if extending */ | |
6d27d3a2 | 3288 | |
f8701a3f SC |
3289 | return; |
3290 | } /* md_convert_frag() */ | |
3291 | ||
3292 | /* Force truly undefined symbols to their maximum size, and generally set up | |
3293 | the frag list to be relaxed | |
3294 | */ | |
3295 | int md_estimate_size_before_relax(fragP, segment) | |
3296 | register fragS *fragP; | |
3297 | segT segment; | |
3298 | { | |
3299 | int old_fix; | |
3300 | register char *buffer_address = fragP->fr_fix + fragP->fr_literal; | |
6d27d3a2 | 3301 | |
f8701a3f | 3302 | old_fix = fragP->fr_fix; |
6d27d3a2 | 3303 | |
f8701a3f SC |
3304 | /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */ |
3305 | switch (fragP->fr_subtype) { | |
6d27d3a2 | 3306 | |
f8701a3f SC |
3307 | case TAB(BRANCH,SZ_UNDEF): { |
3308 | if((fragP->fr_symbol != NULL) /* Not absolute */ | |
3309 | && S_GET_SEGMENT(fragP->fr_symbol) == segment) { | |
3310 | fragP->fr_subtype=TAB(TABTYPE(fragP->fr_subtype),BYTE); | |
3311 | break; | |
3312 | } else if((fragP->fr_symbol == 0) || (cpu_of_arch(current_architecture) < m68020)) { | |
3313 | /* On 68000, or for absolute value, switch to abs long */ | |
3314 | /* FIXME, we should check abs val, pick short or long */ | |
3315 | if(fragP->fr_opcode[0]==0x61) { | |
3316 | fragP->fr_opcode[0]= 0x4E; | |
3317 | fragP->fr_opcode[1]= 0xB9; /* JBSR with ABSL LONG offset */ | |
3318 | subseg_change(SEG_TEXT, 0); | |
6d27d3a2 | 3319 | fix_new(fragP, fragP->fr_fix, 4, |
f8701a3f SC |
3320 | fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC); |
3321 | fragP->fr_fix+=4; | |
3322 | frag_wane(fragP); | |
3323 | } else if(fragP->fr_opcode[0]==0x60) { | |
3324 | fragP->fr_opcode[0]= 0x4E; | |
3325 | fragP->fr_opcode[1]= 0xF9; /* JMP with ABSL LONG offset */ | |
3326 | subseg_change(SEG_TEXT, 0); | |
6d27d3a2 | 3327 | fix_new(fragP, fragP->fr_fix, 4, |
f8701a3f SC |
3328 | fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC); |
3329 | fragP->fr_fix+=4; | |
3330 | frag_wane(fragP); | |
3331 | } else { | |
3332 | as_warn("Long branch offset to extern symbol not supported."); | |
3333 | } | |
3334 | } else { /* Symbol is still undefined. Make it simple */ | |
3335 | fix_new(fragP, (int)(fragP->fr_fix), 4, fragP->fr_symbol, | |
3336 | (symbolS *)0, fragP->fr_offset+4, 1, NO_RELOC); | |
3337 | fragP->fr_fix+=4; | |
3338 | fragP->fr_opcode[1]=0xff; | |
3339 | frag_wane(fragP); | |
3340 | break; | |
3341 | } | |
6d27d3a2 | 3342 | |
f8701a3f SC |
3343 | break; |
3344 | } /* case TAB(BRANCH,SZ_UNDEF) */ | |
6d27d3a2 | 3345 | |
f8701a3f SC |
3346 | case TAB(FBRANCH,SZ_UNDEF): { |
3347 | if(S_GET_SEGMENT(fragP->fr_symbol) == segment || flagseen['l']) { | |
3348 | fragP->fr_subtype = TAB(FBRANCH,SHORT); | |
3349 | fragP->fr_var += 2; | |
3350 | } else { | |
3351 | fragP->fr_subtype = TAB(FBRANCH,LONG); | |
3352 | fragP->fr_var += 4; | |
3353 | } | |
3354 | break; | |
3355 | } /* TAB(FBRANCH,SZ_UNDEF) */ | |
6d27d3a2 | 3356 | |
f8701a3f SC |
3357 | case TAB(PCREL,SZ_UNDEF): { |
3358 | if(S_GET_SEGMENT(fragP->fr_symbol) == segment || flagseen['l']) { | |
3359 | fragP->fr_subtype = TAB(PCREL,SHORT); | |
3360 | fragP->fr_var += 2; | |
3361 | } else { | |
3362 | fragP->fr_subtype = TAB(PCREL,LONG); | |
3363 | fragP->fr_var += 4; | |
3364 | } | |
3365 | break; | |
3366 | } /* TAB(PCREL,SZ_UNDEF) */ | |
6d27d3a2 | 3367 | |
f8701a3f SC |
3368 | case TAB(BCC68000,SZ_UNDEF): { |
3369 | if((fragP->fr_symbol != NULL) | |
3370 | && S_GET_SEGMENT(fragP->fr_symbol) == segment) { | |
3371 | fragP->fr_subtype=TAB(BCC68000,BYTE); | |
3372 | break; | |
3373 | } | |
3374 | /* only Bcc 68000 instructions can come here */ | |
3375 | /* change bcc into b!cc/jmp absl long */ | |
3376 | fragP->fr_opcode[0] ^= 0x01; /* invert bcc */ | |
3377 | if(flagseen['l']) { | |
3378 | fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */ | |
3379 | /* JF: these were fr_opcode[2,3] */ | |
6d27d3a2 | 3380 | buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */ |
f8701a3f SC |
3381 | buffer_address[1] = 0xf8; |
3382 | fragP->fr_fix += 2; /* account for jmp instruction */ | |
3383 | subseg_change(SEG_TEXT,0); | |
6d27d3a2 | 3384 | fix_new(fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0, |
f8701a3f SC |
3385 | fragP->fr_offset, 0, NO_RELOC); |
3386 | fragP->fr_fix += 2; | |
3387 | } else { | |
3388 | fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */ | |
3389 | /* JF: these were fr_opcode[2,3] */ | |
6d27d3a2 | 3390 | buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */ |
a1765cf0 | 3391 | buffer_address[1] = 0xf9; |
f8701a3f SC |
3392 | fragP->fr_fix += 2; /* account for jmp instruction */ |
3393 | subseg_change(SEG_TEXT,0); | |
6d27d3a2 | 3394 | fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, |
f8701a3f SC |
3395 | fragP->fr_offset, 0, NO_RELOC); |
3396 | fragP->fr_fix += 4; | |
3397 | } | |
3398 | frag_wane(fragP); | |
3399 | break; | |
3400 | } /* case TAB(BCC68000,SZ_UNDEF) */ | |
6d27d3a2 | 3401 | |
f8701a3f SC |
3402 | case TAB(DBCC,SZ_UNDEF): { |
3403 | if (fragP->fr_symbol != NULL && S_GET_SEGMENT(fragP->fr_symbol) == segment) { | |
3404 | fragP->fr_subtype=TAB(DBCC,SHORT); | |
3405 | fragP->fr_var+=2; | |
3406 | break; | |
3407 | } | |
3408 | /* only DBcc 68000 instructions can come here */ | |
3409 | /* change dbcc into dbcc/jmp absl long */ | |
3410 | /* JF: these used to be fr_opcode[2-4], which is wrong. */ | |
3411 | buffer_address[0] = 0x00; /* branch offset = 4 */ | |
6d27d3a2 | 3412 | buffer_address[1] = 0x04; |
f8701a3f | 3413 | buffer_address[2] = 0x60; /* put in bra pc + ... */ |
6d27d3a2 | 3414 | |
f8701a3f SC |
3415 | if(flagseen['l']) { |
3416 | /* JF: these were fr_opcode[5-7] */ | |
3417 | buffer_address[3] = 0x04; /* plus 4 */ | |
3418 | buffer_address[4] = 0x4e;/* Put in Jump Word */ | |
3419 | buffer_address[5] = 0xf8; | |
3420 | fragP->fr_fix += 6; /* account for bra/jmp instruction */ | |
3421 | subseg_change(SEG_TEXT,0); | |
6d27d3a2 | 3422 | fix_new(fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0, |
a933d598 SC |
3423 | |
3424 | ||
f8701a3f SC |
3425 | fragP->fr_offset, 0, NO_RELOC); |
3426 | fragP->fr_fix += 2; | |
3427 | } else { | |
3428 | /* JF: these were fr_opcode[5-7] */ | |
3429 | buffer_address[3] = 0x06; /* Plus 6 */ | |
6d27d3a2 KR |
3430 | buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */ |
3431 | buffer_address[5] = 0xf9; | |
f8701a3f SC |
3432 | fragP->fr_fix += 6; /* account for bra/jmp instruction */ |
3433 | subseg_change(SEG_TEXT,0); | |
6d27d3a2 | 3434 | fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, |
f8701a3f SC |
3435 | fragP->fr_offset, 0, NO_RELOC); |
3436 | fragP->fr_fix += 4; | |
3437 | } | |
6d27d3a2 | 3438 | |
f8701a3f SC |
3439 | frag_wane(fragP); |
3440 | break; | |
3441 | } /* case TAB(DBCC,SZ_UNDEF) */ | |
6d27d3a2 | 3442 | |
f8701a3f SC |
3443 | case TAB(PCLEA,SZ_UNDEF): { |
3444 | if ((S_GET_SEGMENT(fragP->fr_symbol))==segment || flagseen['l']) { | |
3445 | fragP->fr_subtype=TAB(PCLEA,SHORT); | |
3446 | fragP->fr_var+=2; | |
3447 | } else { | |
3448 | fragP->fr_subtype=TAB(PCLEA,LONG); | |
3449 | fragP->fr_var+=6; | |
3450 | } | |
3451 | break; | |
3452 | } /* TAB(PCLEA,SZ_UNDEF) */ | |
6d27d3a2 | 3453 | |
f8701a3f SC |
3454 | default: |
3455 | break; | |
6d27d3a2 | 3456 | |
f8701a3f | 3457 | } /* switch on subtype looking for SZ_UNDEF's. */ |
6d27d3a2 | 3458 | |
f8701a3f SC |
3459 | /* now that SZ_UNDEF are taken care of, check others */ |
3460 | switch (fragP->fr_subtype) { | |
3461 | case TAB(BCC68000,BYTE): | |
a39116f1 RP |
3462 | case TAB(BRANCH,BYTE): |
3463 | /* We can't do a short jump to the next instruction, | |
3464 | so we force word mode. */ | |
3465 | if (fragP->fr_symbol && S_GET_VALUE(fragP->fr_symbol)==0 && | |
3466 | fragP->fr_symbol->sy_frag==fragP->fr_next) { | |
f8701a3f SC |
3467 | fragP->fr_subtype=TAB(TABTYPE(fragP->fr_subtype),SHORT); |
3468 | fragP->fr_var+=2; | |
fecd2382 | 3469 | } |
a39116f1 | 3470 | break; |
f8701a3f | 3471 | default: |
a39116f1 | 3472 | break; |
f8701a3f SC |
3473 | } |
3474 | return fragP->fr_var + fragP->fr_fix - old_fix; | |
fecd2382 RP |
3475 | } |
3476 | ||
3477 | #if defined(OBJ_AOUT) | defined(OBJ_BOUT) | |
6d27d3a2 | 3478 | /* the bit-field entries in the relocation_info struct plays hell |
fecd2382 RP |
3479 | with the byte-order problems of cross-assembly. So as a hack, |
3480 | I added this mach. dependent ri twiddler. Ugly, but it gets | |
3481 | you there. -KWK */ | |
3482 | /* on m68k: first 4 bytes are normal unsigned long, next three bytes | |
a39116f1 RP |
3483 | are symbolnum, most sig. byte first. Last byte is broken up with |
3484 | bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower | |
3485 | nibble as nuthin. (on Sun 3 at least) */ | |
fecd2382 RP |
3486 | /* Translate the internal relocation information into target-specific |
3487 | format. */ | |
a79c6033 | 3488 | #ifdef comment |
fecd2382 | 3489 | void |
a39116f1 RP |
3490 | md_ri_to_chars(the_bytes, ri) |
3491 | char *the_bytes; | |
3492 | struct reloc_info_generic *ri; | |
fecd2382 | 3493 | { |
f8701a3f SC |
3494 | /* this is easy */ |
3495 | md_number_to_chars(the_bytes, ri->r_address, 4); | |
3496 | /* now the fun stuff */ | |
3497 | the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff; | |
3498 | the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff; | |
3499 | the_bytes[6] = ri->r_symbolnum & 0x0ff; | |
6d27d3a2 KR |
3500 | the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) | |
3501 | ((ri->r_extern << 4) & 0x10)); | |
fecd2382 | 3502 | } |
a79c6033 RP |
3503 | #endif /* comment */ |
3504 | ||
3505 | void tc_aout_fix_to_chars(where, fixP, segment_address_in_file) | |
f8701a3f SC |
3506 | char *where; |
3507 | fixS *fixP; | |
3508 | relax_addressT segment_address_in_file; | |
a79c6033 | 3509 | { |
f8701a3f SC |
3510 | /* |
3511 | * In: length of relocation (or of address) in chars: 1, 2 or 4. | |
3512 | * Out: GNU LD relocation length code: 0, 1, or 2. | |
3513 | */ | |
6d27d3a2 | 3514 | |
f8701a3f SC |
3515 | static unsigned char nbytes_r_length [] = { 42, 0, 1, 42, 2 }; |
3516 | long r_symbolnum; | |
6d27d3a2 | 3517 | |
f8701a3f | 3518 | know(fixP->fx_addsy != NULL); |
6d27d3a2 | 3519 | |
f8701a3f SC |
3520 | md_number_to_chars(where, |
3521 | fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file, | |
3522 | 4); | |
6d27d3a2 | 3523 | |
f8701a3f SC |
3524 | r_symbolnum = (S_IS_DEFINED(fixP->fx_addsy) |
3525 | ? S_GET_TYPE(fixP->fx_addsy) | |
3526 | : fixP->fx_addsy->sy_number); | |
6d27d3a2 | 3527 | |
f8701a3f SC |
3528 | where[4] = (r_symbolnum >> 16) & 0x0ff; |
3529 | where[5] = (r_symbolnum >> 8) & 0x0ff; | |
3530 | where[6] = r_symbolnum & 0x0ff; | |
6d27d3a2 | 3531 | where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) | |
f8701a3f | 3532 | (((!S_IS_DEFINED(fixP->fx_addsy)) << 4) & 0x10)); |
6d27d3a2 | 3533 | |
f8701a3f | 3534 | return; |
a79c6033 RP |
3535 | } /* tc_aout_fix_to_chars() */ |
3536 | ||
fecd2382 RP |
3537 | #endif /* OBJ_AOUT or OBJ_BOUT */ |
3538 | ||
3539 | #ifndef WORKING_DOT_WORD | |
3540 | const int md_short_jump_size = 4; | |
3541 | const int md_long_jump_size = 6; | |
3542 | ||
3543 | void | |
a39116f1 | 3544 | md_create_short_jump(ptr,from_addr,to_addr,frag,to_symbol) |
fecd2382 RP |
3545 | char *ptr; |
3546 | long from_addr, | |
a39116f1 | 3547 | to_addr; |
fecd2382 RP |
3548 | fragS *frag; |
3549 | symbolS *to_symbol; | |
3550 | { | |
f8701a3f | 3551 | long offset; |
6d27d3a2 | 3552 | |
f8701a3f | 3553 | offset = to_addr - (from_addr+2); |
6d27d3a2 | 3554 | |
f8701a3f SC |
3555 | md_number_to_chars(ptr ,(long)0x6000,2); |
3556 | md_number_to_chars(ptr+2,(long)offset,2); | |
fecd2382 RP |
3557 | } |
3558 | ||
3559 | void | |
a39116f1 | 3560 | md_create_long_jump(ptr,from_addr,to_addr,frag,to_symbol) |
fecd2382 RP |
3561 | char *ptr; |
3562 | long from_addr, | |
a39116f1 | 3563 | to_addr; |
fecd2382 RP |
3564 | fragS *frag; |
3565 | symbolS *to_symbol; | |
3566 | { | |
f8701a3f | 3567 | long offset; |
6d27d3a2 | 3568 | |
f8701a3f SC |
3569 | if (cpu_of_arch(current_architecture) < m68020) { |
3570 | offset=to_addr-S_GET_VALUE(to_symbol); | |
3571 | md_number_to_chars(ptr ,(long)0x4EF9,2); | |
3572 | md_number_to_chars(ptr+2,(long)offset,4); | |
3573 | fix_new(frag,(ptr+2)-frag->fr_literal,4,to_symbol,(symbolS *)0,(long)0,0, | |
3574 | NO_RELOC); | |
3575 | } else { | |
3576 | offset=to_addr - (from_addr+2); | |
3577 | md_number_to_chars(ptr ,(long)0x60ff,2); | |
3578 | md_number_to_chars(ptr+2,(long)offset,4); | |
3579 | } | |
fecd2382 RP |
3580 | } |
3581 | ||
3582 | #endif | |
3583 | /* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?) | |
6d27d3a2 | 3584 | |
a39116f1 RP |
3585 | 0: Everything is OK |
3586 | 10: Absolute 1:8 only | |
3587 | 20: Absolute 0:7 only | |
3588 | 30: absolute 0:15 only | |
3589 | 40: Absolute 0:31 only | |
3590 | 50: absolute 0:127 only | |
3591 | 55: absolute -64:63 only | |
3592 | 60: absolute -128:127 only | |
3593 | 70: absolute 0:4095 only | |
3594 | 80: No bignums | |
6d27d3a2 | 3595 | |
a39116f1 | 3596 | */ |
fecd2382 RP |
3597 | |
3598 | static int get_num(exp,ok) | |
f8701a3f SC |
3599 | struct m68k_exp *exp; |
3600 | int ok; | |
fecd2382 RP |
3601 | { |
3602 | #ifdef TEST2 | |
f8701a3f | 3603 | long l = 0; |
6d27d3a2 | 3604 | |
f8701a3f SC |
3605 | if(!exp->e_beg) |
3606 | return 0; | |
3607 | if(*exp->e_beg=='0') { | |
3608 | if(exp->e_beg[1]=='x') | |
3609 | sscanf(exp->e_beg+2,"%x",&l); | |
3610 | else | |
3611 | sscanf(exp->e_beg+1,"%O",&l); | |
3612 | return l; | |
3613 | } | |
3614 | return atol(exp->e_beg); | |
fecd2382 | 3615 | #else |
f8701a3f SC |
3616 | char *save_in; |
3617 | char c_save; | |
6d27d3a2 | 3618 | |
f8701a3f SC |
3619 | if(!exp) { |
3620 | /* Can't do anything */ | |
3621 | return 0; | |
3622 | } | |
3623 | if(!exp->e_beg || !exp->e_end) { | |
3624 | seg(exp)=SEG_ABSOLUTE; | |
3625 | adds(exp)=0; | |
3626 | subs(exp)=0; | |
3627 | offs(exp)= (ok==10) ? 1 : 0; | |
3628 | as_warn("Null expression defaults to %ld",offs(exp)); | |
3629 | return 0; | |
fecd2382 | 3630 | } |
6d27d3a2 | 3631 | |
f8701a3f SC |
3632 | exp->e_siz=0; |
3633 | if(/* ok!=80 && */exp->e_end[-1]==':' && (exp->e_end-exp->e_beg)>=2) { | |
3634 | switch(exp->e_end[0]) { | |
3635 | case 's': | |
3636 | case 'S': | |
3637 | case 'b': | |
3638 | case 'B': | |
3639 | exp->e_siz=1; | |
3640 | break; | |
3641 | case 'w': | |
3642 | case 'W': | |
3643 | exp->e_siz=2; | |
3644 | break; | |
3645 | case 'l': | |
3646 | case 'L': | |
3647 | exp->e_siz=3; | |
3648 | break; | |
3649 | default: | |
3650 | as_bad("Unknown size for expression \"%c\"",exp->e_end[0]); | |
3651 | } | |
3652 | exp->e_end-=2; | |
fecd2382 | 3653 | } |
f8701a3f SC |
3654 | c_save=exp->e_end[1]; |
3655 | exp->e_end[1]='\0'; | |
3656 | save_in=input_line_pointer; | |
3657 | input_line_pointer=exp->e_beg; | |
3658 | switch(expression(&(exp->e_exp))) { | |
3659 | case SEG_PASS1: | |
3660 | seg(exp)=SEG_ABSOLUTE; | |
3661 | adds(exp)=0; | |
3662 | subs(exp)=0; | |
3663 | offs(exp)= (ok==10) ? 1 : 0; | |
3664 | as_warn("Unknown expression: '%s' defaulting to %d",exp->e_beg,offs(exp)); | |
3665 | break; | |
6d27d3a2 | 3666 | |
f8701a3f SC |
3667 | case SEG_ABSENT: |
3668 | /* Do the same thing the VAX asm does */ | |
3669 | seg(exp)=SEG_ABSOLUTE; | |
3670 | adds(exp)=0; | |
3671 | subs(exp)=0; | |
fecd2382 | 3672 | offs(exp)=0; |
f8701a3f SC |
3673 | if(ok==10) { |
3674 | as_warn("expression out of range: defaulting to 1"); | |
3675 | offs(exp)=1; | |
3676 | } | |
3677 | break; | |
3678 | case SEG_ABSOLUTE: | |
3679 | switch(ok) { | |
3680 | case 10: | |
3681 | if(offs(exp)<1 || offs(exp)>8) { | |
3682 | as_warn("expression out of range: defaulting to 1"); | |
3683 | offs(exp)=1; | |
3684 | } | |
3685 | break; | |
3686 | case 20: | |
3687 | if(offs(exp)<0 || offs(exp)>7) | |
3688 | goto outrange; | |
3689 | break; | |
3690 | case 30: | |
3691 | if(offs(exp)<0 || offs(exp)>15) | |
3692 | goto outrange; | |
3693 | break; | |
3694 | case 40: | |
3695 | if(offs(exp)<0 || offs(exp)>32) | |
3696 | goto outrange; | |
3697 | break; | |
3698 | case 50: | |
3699 | if(offs(exp)<0 || offs(exp)>127) | |
3700 | goto outrange; | |
3701 | break; | |
3702 | case 55: | |
3703 | if(offs(exp)<-64 || offs(exp)>63) | |
3704 | goto outrange; | |
3705 | break; | |
3706 | case 60: | |
3707 | if(offs(exp)<-128 || offs(exp)>127) | |
3708 | goto outrange; | |
3709 | break; | |
3710 | case 70: | |
3711 | if(offs(exp)<0 || offs(exp)>4095) { | |
3712 | outrange: | |
3713 | as_warn("expression out of range: defaulting to 0"); | |
3714 | offs(exp)=0; | |
3715 | } | |
3716 | break; | |
3717 | default: | |
3718 | break; | |
3719 | } | |
3720 | break; | |
3721 | case SEG_TEXT: | |
3722 | case SEG_DATA: | |
3723 | case SEG_BSS: | |
3724 | case SEG_UNKNOWN: | |
3725 | case SEG_DIFFERENCE: | |
3726 | if(ok>=10 && ok<=70) { | |
3727 | seg(exp)=SEG_ABSOLUTE; | |
3728 | adds(exp)=0; | |
3729 | subs(exp)=0; | |
3730 | offs(exp)= (ok==10) ? 1 : 0; | |
3731 | as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp->e_beg,offs(exp)); | |
3732 | } | |
3733 | break; | |
3734 | case SEG_BIG: | |
e53ab768 KR |
3735 | if (offs (exp) < 0 /* flonum */ |
3736 | && (ok == 80 /* no bignums */ | |
3737 | || (ok > 10 /* small-int ranges including 0 ok */ | |
3738 | /* If we have a flonum zero, a zero integer should | |
3739 | do as well (e.g., in moveq). */ | |
3740 | && generic_floating_point_number.exponent == 0 | |
3741 | && generic_floating_point_number.low[0] == 0))) | |
3742 | { | |
3743 | /* HACK! Turn it into a long */ | |
3744 | LITTLENUM_TYPE words[6]; | |
3745 | ||
3746 | gen_to_words(words,2,8L);/* These numbers are magic! */ | |
3747 | seg(exp)=SEG_ABSOLUTE; | |
3748 | adds(exp)=0; | |
3749 | subs(exp)=0; | |
3750 | offs(exp)=words[1]|(words[0]<<16); | |
3751 | } | |
3752 | else if(ok!=0) { | |
f8701a3f SC |
3753 | seg(exp)=SEG_ABSOLUTE; |
3754 | adds(exp)=0; | |
3755 | subs(exp)=0; | |
3756 | offs(exp)= (ok==10) ? 1 : 0; | |
3757 | as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp->e_beg,offs(exp)); | |
3758 | } | |
3759 | break; | |
fecd2382 | 3760 | default: |
f8701a3f | 3761 | as_fatal("failed sanity check."); |
a39116f1 | 3762 | } |
f8701a3f SC |
3763 | if(input_line_pointer!=exp->e_end+1) |
3764 | as_bad("Ignoring junk after expression"); | |
3765 | exp->e_end[1]=c_save; | |
3766 | input_line_pointer=save_in; | |
3767 | if(exp->e_siz) { | |
3768 | switch(exp->e_siz) { | |
3769 | case 1: | |
3770 | if(!isbyte(offs(exp))) | |
3771 | as_warn("expression doesn't fit in BYTE"); | |
3772 | break; | |
3773 | case 2: | |
3774 | if(!isword(offs(exp))) | |
3775 | as_warn("expression doesn't fit in WORD"); | |
3776 | break; | |
3777 | } | |
a39116f1 | 3778 | } |
f8701a3f | 3779 | return offs(exp); |
fecd2382 RP |
3780 | #endif |
3781 | } /* get_num() */ | |
3782 | ||
3783 | /* These are the back-ends for the various machine dependent pseudo-ops. */ | |
f6e504fe | 3784 | void demand_empty_rest_of_line(); /* Hate those extra verbose names */ |
fecd2382 RP |
3785 | |
3786 | static void s_data1() { | |
f8701a3f SC |
3787 | subseg_new(SEG_DATA,1); |
3788 | demand_empty_rest_of_line(); | |
fecd2382 RP |
3789 | } /* s_data1() */ |
3790 | ||
3791 | static void s_data2() { | |
f8701a3f SC |
3792 | subseg_new(SEG_DATA,2); |
3793 | demand_empty_rest_of_line(); | |
fecd2382 RP |
3794 | } /* s_data2() */ |
3795 | ||
6d27d3a2 | 3796 | static void s_bss() |
a1765cf0 | 3797 | { |
6d27d3a2 | 3798 | /* We don't support putting frags in the BSS segment, we fake it |
a1765cf0 SC |
3799 | by marking in_bss, then looking at s_skip for clues */ |
3800 | ||
3801 | subseg_new(SEG_BSS, 0); | |
f8701a3f | 3802 | demand_empty_rest_of_line(); |
fecd2382 RP |
3803 | } /* s_bss() */ |
3804 | ||
3805 | static void s_even() { | |
f8701a3f SC |
3806 | register int temp; |
3807 | register long temp_fill; | |
6d27d3a2 | 3808 | |
f8701a3f SC |
3809 | temp = 1; /* JF should be 2? */ |
3810 | temp_fill = get_absolute_expression (); | |
3811 | if ( ! need_pass_2 ) /* Never make frag if expect extra pass. */ | |
3812 | frag_align (temp, (int)temp_fill); | |
3813 | demand_empty_rest_of_line(); | |
fecd2382 RP |
3814 | } /* s_even() */ |
3815 | ||
3816 | static void s_proc() { | |
f8701a3f | 3817 | demand_empty_rest_of_line(); |
fecd2382 RP |
3818 | } /* s_proc() */ |
3819 | ||
3820 | /* s_space is defined in read.c .skip is simply an alias to it. */ | |
3821 | ||
7c15cbe8 RP |
3822 | /* |
3823 | * md_parse_option | |
3824 | * Invocation line includes a switch not recognized by the base assembler. | |
3825 | * See if it's a processor-specific option. These are: | |
3826 | * | |
3827 | * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040 | |
3828 | * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851 | |
3829 | * Select the architecture. Instructions or features not | |
3830 | * supported by the selected architecture cause fatal | |
3831 | * errors. More than one may be specified. The default is | |
3832 | * -m68020 -m68851 -m68881. Note that -m68008 is a synonym | |
3833 | * for -m68000, and -m68882 is a synonym for -m68881. | |
3834 | * | |
a39116f1 RP |
3835 | * MAYBE_FLOAT_TOO is defined below so that specifying a processor type |
3836 | * (e.g. m68020) also requests that float instructions be included. This | |
3837 | * is the default setup, mostly to avoid hassling users. A better | |
3838 | * rearrangement of this structure would be to add an option to DENY | |
3839 | * floating point opcodes, for people who want to really know there's none | |
3840 | * of that funny floaty stuff going on. FIXME-later. | |
7c15cbe8 | 3841 | */ |
a39116f1 RP |
3842 | #ifndef MAYBE_FLOAT_TOO |
3843 | #define MAYBE_FLOAT_TOO m68881 | |
3844 | #endif | |
7c15cbe8 RP |
3845 | |
3846 | int md_parse_option(argP,cntP,vecP) | |
f8701a3f SC |
3847 | char **argP; |
3848 | int *cntP; | |
3849 | char ***vecP; | |
fecd2382 | 3850 | { |
f8701a3f SC |
3851 | switch(**argP) { |
3852 | case 'l': /* -l means keep external to 2 bit offset | |
3853 | rather than 16 bit one */ | |
3854 | break; | |
6d27d3a2 | 3855 | |
f8701a3f SC |
3856 | case 'S': /* -S means that jbsr's always turn into jsr's. */ |
3857 | break; | |
6d27d3a2 | 3858 | |
f8701a3f SC |
3859 | case 'A': |
3860 | (*argP)++; | |
3861 | /* intentional fall-through */ | |
3862 | case 'm': | |
3863 | (*argP)++; | |
6d27d3a2 | 3864 | |
f8701a3f SC |
3865 | if (**argP=='c') { |
3866 | (*argP)++; | |
3867 | } /* allow an optional "c" */ | |
6d27d3a2 | 3868 | |
f8701a3f SC |
3869 | if (!strcmp(*argP, "68000") |
3870 | || !strcmp(*argP, "68008")) { | |
3871 | current_architecture |= m68000; | |
3872 | } else if (!strcmp(*argP, "68010")) { | |
fecd2382 | 3873 | #ifdef TE_SUN |
f8701a3f | 3874 | omagic= 1<<16|OMAGIC; |
fecd2382 | 3875 | #endif |
f8701a3f | 3876 | current_architecture |= m68010; |
6d27d3a2 KR |
3877 | |
3878 | } else if (!strcmp(*argP, "68020")) { | |
f8701a3f | 3879 | current_architecture |= m68020 | MAYBE_FLOAT_TOO; |
6d27d3a2 KR |
3880 | |
3881 | } else if (!strcmp(*argP, "68030")) { | |
f8701a3f | 3882 | current_architecture |= m68030 | MAYBE_FLOAT_TOO; |
6d27d3a2 KR |
3883 | |
3884 | } else if (!strcmp(*argP, "68040")) { | |
f8701a3f | 3885 | current_architecture |= m68040 | MAYBE_FLOAT_TOO; |
6d27d3a2 | 3886 | |
7c15cbe8 | 3887 | #ifndef NO_68881 |
f8701a3f SC |
3888 | } else if (!strcmp(*argP, "68881")) { |
3889 | current_architecture |= m68881; | |
6d27d3a2 | 3890 | |
f8701a3f SC |
3891 | } else if (!strcmp(*argP, "68882")) { |
3892 | current_architecture |= m68882; | |
6d27d3a2 | 3893 | |
7c15cbe8 RP |
3894 | #endif /* NO_68881 */ |
3895 | #ifndef NO_68851 | |
6d27d3a2 | 3896 | } else if (!strcmp(*argP,"68851")) { |
f8701a3f | 3897 | current_architecture |= m68851; |
6d27d3a2 | 3898 | |
7c15cbe8 | 3899 | #endif /* NO_68851 */ |
f8701a3f SC |
3900 | } else { |
3901 | as_warn("Unknown architecture, \"%s\". option ignored", *argP); | |
3902 | } /* switch on architecture */ | |
6d27d3a2 | 3903 | |
f8701a3f | 3904 | while(**argP) (*argP)++; |
6d27d3a2 | 3905 | |
f8701a3f | 3906 | break; |
6d27d3a2 | 3907 | |
f8701a3f SC |
3908 | case 'p': |
3909 | if (!strcmp(*argP,"pic")) { | |
3910 | (*argP) += 3; | |
3911 | break; /* -pic, Position Independent Code */ | |
3912 | } else { | |
3913 | return(0); | |
3914 | } /* pic or not */ | |
6d27d3a2 | 3915 | |
f8701a3f SC |
3916 | default: |
3917 | return 0; | |
3918 | } | |
3919 | return 1; | |
fecd2382 RP |
3920 | } |
3921 | ||
3922 | ||
3923 | #ifdef TEST2 | |
3924 | ||
3925 | /* TEST2: Test md_assemble() */ | |
3926 | /* Warning, this routine probably doesn't work anymore */ | |
3927 | ||
3928 | main() | |
3929 | { | |
f8701a3f SC |
3930 | struct m68k_it the_ins; |
3931 | char buf[120]; | |
3932 | char *cp; | |
3933 | int n; | |
6d27d3a2 | 3934 | |
f8701a3f SC |
3935 | m68k_ip_begin(); |
3936 | for(;;) { | |
3937 | if(!gets(buf) || !*buf) | |
3938 | break; | |
3939 | if(buf[0]=='|' || buf[1]=='.') | |
3940 | continue; | |
3941 | for(cp=buf;*cp;cp++) | |
3942 | if(*cp=='\t') | |
3943 | *cp=' '; | |
3944 | if(is_label(buf)) | |
3945 | continue; | |
3946 | memset(&the_ins, '\0', sizeof(the_ins)); | |
3947 | m68k_ip(&the_ins,buf); | |
3948 | if(the_ins.error) { | |
3949 | printf("Error %s in %s\n",the_ins.error,buf); | |
3950 | } else { | |
3951 | printf("Opcode(%d.%s): ",the_ins.numo,the_ins.args); | |
3952 | for(n=0;n<the_ins.numo;n++) | |
3953 | printf(" 0x%x",the_ins.opcode[n]&0xffff); | |
3954 | printf(" "); | |
3955 | print_the_insn(&the_ins.opcode[0],stdout); | |
3956 | (void)putchar('\n'); | |
3957 | } | |
3958 | for(n=0;n<strlen(the_ins.args)/2;n++) { | |
3959 | if(the_ins.operands[n].error) { | |
3960 | printf("op%d Error %s in %s\n",n,the_ins.operands[n].error,buf); | |
3961 | continue; | |
3962 | } | |
3963 | printf("mode %d, reg %d, ",the_ins.operands[n].mode,the_ins.operands[n].reg); | |
3964 | if(the_ins.operands[n].b_const) | |
3965 | printf("Constant: '%.*s', ",1+the_ins.operands[n].e_const-the_ins.operands[n].b_const,the_ins.operands[n].b_const); | |
3966 | printf("ireg %d, isiz %d, imul %d, ",the_ins.operands[n].ireg,the_ins.operands[n].isiz,the_ins.operands[n].imul); | |
3967 | if(the_ins.operands[n].b_iadd) | |
3968 | printf("Iadd: '%.*s',",1+the_ins.operands[n].e_iadd-the_ins.operands[n].b_iadd,the_ins.operands[n].b_iadd); | |
3969 | (void)putchar('\n'); | |
3970 | } | |
a39116f1 | 3971 | } |
f8701a3f SC |
3972 | m68k_ip_end(); |
3973 | return 0; | |
fecd2382 RP |
3974 | } |
3975 | ||
3976 | is_label(str) | |
f8701a3f | 3977 | char *str; |
fecd2382 | 3978 | { |
f8701a3f SC |
3979 | while(*str==' ') |
3980 | str++; | |
3981 | while(*str && *str!=' ') | |
3982 | str++; | |
3983 | if(str[-1]==':' || str[1]=='=') | |
3984 | return 1; | |
3985 | return 0; | |
fecd2382 RP |
3986 | } |
3987 | ||
3988 | #endif | |
3989 | ||
3990 | /* Possible states for relaxation: | |
6d27d3a2 | 3991 | |
a39116f1 RP |
3992 | 0 0 branch offset byte (bra, etc) |
3993 | 0 1 word | |
3994 | 0 2 long | |
6d27d3a2 | 3995 | |
a39116f1 RP |
3996 | 1 0 indexed offsets byte a0@(32,d4:w:1) etc |
3997 | 1 1 word | |
3998 | 1 2 long | |
6d27d3a2 | 3999 | |
a39116f1 RP |
4000 | 2 0 two-offset index word-word a0@(32,d4)@(45) etc |
4001 | 2 1 word-long | |
4002 | 2 2 long-word | |
4003 | 2 3 long-long | |
6d27d3a2 | 4004 | |
a39116f1 | 4005 | */ |
fecd2382 RP |
4006 | |
4007 | ||
4008 | ||
4009 | #ifdef DONTDEF | |
4010 | abort() | |
4011 | { | |
f8701a3f SC |
4012 | printf("ABORT!\n"); |
4013 | exit(12); | |
fecd2382 RP |
4014 | } |
4015 | ||
4016 | print_frags() | |
4017 | { | |
f8701a3f SC |
4018 | fragS *fragP; |
4019 | extern fragS *text_frag_root; | |
6d27d3a2 | 4020 | |
f8701a3f SC |
4021 | for(fragP=text_frag_root;fragP;fragP=fragP->fr_next) { |
4022 | printf("addr %lu next 0x%x fix %ld var %ld symbol 0x%x offset %ld\n", | |
4023 | fragP->fr_address,fragP->fr_next,fragP->fr_fix,fragP->fr_var,fragP->fr_symbol,fragP->fr_offset); | |
4024 | printf("opcode 0x%x type %d subtype %d\n\n",fragP->fr_opcode,fragP->fr_type,fragP->fr_subtype); | |
4025 | } | |
4026 | fflush(stdout); | |
4027 | return 0; | |
fecd2382 RP |
4028 | } |
4029 | #endif | |
4030 | ||
4031 | #ifdef DONTDEF | |
4032 | /*VARARGS1*/ | |
4033 | panic(format,args) | |
f8701a3f | 4034 | char *format; |
fecd2382 | 4035 | { |
f8701a3f SC |
4036 | fputs("Internal error:",stderr); |
4037 | _doprnt(format,&args,stderr); | |
4038 | (void)putc('\n',stderr); | |
4039 | as_where(); | |
4040 | abort(); | |
fecd2382 RP |
4041 | } |
4042 | #endif | |
4043 | ||
4044 | /* We have no need to default values of symbols. */ | |
4045 | ||
4046 | /* ARGSUSED */ | |
4047 | symbolS * | |
a39116f1 RP |
4048 | md_undefined_symbol (name) |
4049 | char *name; | |
fecd2382 | 4050 | { |
f8701a3f | 4051 | return 0; |
fecd2382 RP |
4052 | } |
4053 | ||
6d27d3a2 | 4054 | /* Parse an operand that is machine-specific. |
fecd2382 RP |
4055 | We just return without modifying the expression if we have nothing |
4056 | to do. */ | |
4057 | ||
4058 | /* ARGSUSED */ | |
4059 | void | |
a39116f1 RP |
4060 | md_operand (expressionP) |
4061 | expressionS *expressionP; | |
fecd2382 RP |
4062 | { |
4063 | } | |
4064 | ||
4065 | /* Round up a section size to the appropriate boundary. */ | |
4066 | long | |
a39116f1 RP |
4067 | md_section_align (segment, size) |
4068 | segT segment; | |
4069 | long size; | |
fecd2382 | 4070 | { |
f8701a3f | 4071 | return size; /* Byte alignment is fine */ |
fecd2382 RP |
4072 | } |
4073 | ||
4074 | /* Exactly what point is a PC-relative offset relative TO? | |
4075 | On the 68k, they're relative to the address of the offset, plus | |
4076 | its size. (??? Is this right? FIXME-SOON!) */ | |
4077 | long | |
a39116f1 RP |
4078 | md_pcrel_from (fixP) |
4079 | fixS *fixP; | |
fecd2382 | 4080 | { |
f8701a3f | 4081 | return(fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address); |
fecd2382 RP |
4082 | } |
4083 | ||
fecd2382 RP |
4084 | /* |
4085 | * Local Variables: | |
4086 | * comment-column: 0 | |
4087 | * fill-column: 131 | |
4088 | * End: | |
4089 | */ | |
4090 | ||
4091 | /* end of tc-m68k.c */ |