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* config/tc-m68k.c (md_pseudo_table) [OBJ_ELF]: Add .file and
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
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252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4
NC		 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001
252b5132
RH		 4 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
23#include <ctype.h>
24#include "as.h"
25#include "obstack.h"
26#include "subsegs.h"
f27a3839 27#include "dwarf2dbg.h"
252b5132
RH		 28
29#include "opcode/m68k.h"
30#include "m68k-parse.h"
31
0d96863f
CM		 32#if defined (OBJ_ELF)
33#include "elf/m68k.h"
34#endif
35
252b5132
RH		 36/* This string holds the chars that always start a comment. If the
37 pre-processor is disabled, these aren't very useful. The macro
38 tc_comment_chars points to this. We use this, rather than the
39 usual comment_chars, so that the --bitwise-or option will work. */
40#if defined (TE_SVR4) || defined (TE_DELTA)
41const char *m68k_comment_chars = "|#";
42#else
43const char *m68k_comment_chars = "|";
44#endif
45
46/* This array holds the chars that only start a comment at the beginning of
47 a line. If the line seems to have the form '# 123 filename'
48 .line and .file directives will appear in the pre-processed output */
49/* Note that input_file.c hand checks for '#' at the beginning of the
50 first line of the input file. This is because the compiler outputs
92774660
KH		 51 #NO_APP at the beginning of its output. */
52/* Also note that comments like this one will always work. */
252b5132
RH		 53const char line_comment_chars[] = "#*";
54
63a0b638 55const char line_separator_chars[] = ";";
252b5132
RH		 56
57/* Chars that can be used to separate mant from exp in floating point nums */
58CONST char EXP_CHARS[] = "eE";
59
60/* Chars that mean this number is a floating point constant, as
61 in "0f12.456" or "0d1.2345e12". */
62
63CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
64
65/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
66 changed in read.c . Ideally it shouldn't have to know about it at all,
67 but nothing is ideal around here. */
68
69const int md_reloc_size = 8; /* Size of relocation record */
70
71/* Are we trying to generate PIC code? If so, absolute references
72 ought to be made into linkage table references or pc-relative
92774660 73 references. Not implemented. For ELF there are other means
252b5132
RH		 74 to denote pic relocations. */
75int flag_want_pic;
76
77static int flag_short_refs; /* -l option */
78static int flag_long_jumps; /* -S option */
28e7409f 79static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 80
81#ifdef REGISTER_PREFIX_OPTIONAL
82int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
83#else
84int flag_reg_prefix_optional;
85#endif
86
87/* Whether --register-prefix-optional was used on the command line. */
88static int reg_prefix_optional_seen;
89
90/* The floating point coprocessor to use by default. */
91static enum m68k_register m68k_float_copnum = COP1;
92
93/* If this is non-zero, then references to number(%pc) will be taken
94 to refer to number, rather than to %pc + number. */
95static int m68k_abspcadd;
96
97/* If this is non-zero, then the quick forms of the move, add, and sub
98 instructions are used when possible. */
99static int m68k_quick = 1;
100
101/* If this is non-zero, then if the size is not specified for a base
102 or outer displacement, the assembler assumes that the size should
103 be 32 bits. */
104static int m68k_rel32 = 1;
105
106/* This is non-zero if m68k_rel32 was set from the command line. */
107static int m68k_rel32_from_cmdline;
108
109/* The default width to use for an index register when using a base
110 displacement. */
111static enum m68k_size m68k_index_width_default = SIZE_LONG;
112
113/* We want to warn if any text labels are misaligned. In order to get
114 the right line number, we need to record the line number for each
115 label. */
116
117struct label_line
118{
119 struct label_line *next;
120 symbolS *label;
121 char *file;
122 unsigned int line;
123 int text;
124};
125
126/* The list of labels. */
127
128static struct label_line *labels;
129
130/* The current label. */
131
132static struct label_line *current_label;
133
134/* Its an arbitrary name: This means I don't approve of it */
135/* See flames below */
136static struct obstack robyn;
137
252b5132
RH		 138struct m68k_incant
139 {
140 const char *m_operands;
141 unsigned long m_opcode;
142 short m_opnum;
143 short m_codenum;
144 int m_arch;
145 struct m68k_incant *m_next;
146 };
147
148#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
149#define gettwo(x) (((x)->m_opcode)&0xffff)
150
151static const enum m68k_register m68000_control_regs[] = { 0 };
152static const enum m68k_register m68010_control_regs[] = {
153 SFC, DFC, USP, VBR,
154 0
155};
156static const enum m68k_register m68020_control_regs[] = {
157 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
158 0
159};
160static const enum m68k_register m68040_control_regs[] = {
161 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
162 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
163 0
164};
165static const enum m68k_register m68060_control_regs[] = {
166 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
167 USP, VBR, URP, SRP, PCR,
168 0
169};
6da466c7 170static const enum m68k_register mcf_control_regs[] = {
92774660 171 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
252b5132
RH		 172 RAMBAR0, RAMBAR1, MBAR,
173 0
174};
175#define cpu32_control_regs m68010_control_regs
176
177static const enum m68k_register *control_regs;
178
179/* internal form of a 68020 instruction */
180struct m68k_it
181{
182 const char *error;
183 const char *args; /* list of opcode info */
184 int numargs;
185
186 int numo; /* Number of shorts in opcode */
187 short opcode[11];
188
189 struct m68k_op operands[6];
190
191 int nexp; /* number of exprs in use */
192 struct m68k_exp exprs[4];
193
194 int nfrag; /* Number of frags we have to produce */
195 struct
196 {
197 int fragoff; /* Where in the current opcode the frag ends */
198 symbolS *fadd;
199 offsetT foff;
200 int fragty;
201 }
202 fragb[4];
203
204 int nrel; /* Num of reloc strucs in use */
205 struct
206 {
207 int n;
208 expressionS exp;
209 char wid;
210 char pcrel;
211 /* In a pc relative address the difference between the address
212 of the offset and the address that the offset is relative
213 to. This depends on the addressing mode. Basically this
214 is the value to put in the offset field to address the
215 first byte of the offset, without regarding the special
216 significance of some values (in the branch instruction, for
217 example). */
218 int pcrel_fix;
219#ifdef OBJ_ELF
220 /* Whether this expression needs special pic relocation, and if
221 so, which. */
222 enum pic_relocation pic_reloc;
223#endif
224 }
225 reloc[5]; /* Five is enough??? */
226};
227
6da466c7 228#define cpu_of_arch(x) ((x) & (m68000up|mcf))
252b5132
RH		 229#define float_of_arch(x) ((x) & mfloat)
230#define mmu_of_arch(x) ((x) & mmmu)
6da466c7 231#define arch_coldfire_p(x) (((x) & mcf) != 0)
252b5132
RH		 232
233/* Macros for determining if cpu supports a specific addressing mode */
dc84e067 234#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407))
252b5132
RH		 235
236static struct m68k_it the_ins; /* the instruction being assembled */
237
238#define op(ex) ((ex)->exp.X_op)
239#define adds(ex) ((ex)->exp.X_add_symbol)
240#define subs(ex) ((ex)->exp.X_op_symbol)
241#define offs(ex) ((ex)->exp.X_add_number)
242
243/* Macros for adding things to the m68k_it struct */
244
245#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
246
247/* Static functions. */
248
249static void insop PARAMS ((int, const struct m68k_incant *));
250static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
251static void add_frag PARAMS ((symbolS *, offsetT, int));
252
253/* Like addword, but goes BEFORE general operands */
254static void
255insop (w, opcode)
256 int w;
257 const struct m68k_incant *opcode;
258{
259 int z;
260 for(z=the_ins.numo;z>opcode->m_codenum;--z)
261 the_ins.opcode[z]=the_ins.opcode[z-1];
262 for(z=0;z<the_ins.nrel;z++)
263 the_ins.reloc[z].n+=2;
264 for (z = 0; z < the_ins.nfrag; z++)
265 the_ins.fragb[z].fragoff++;
266 the_ins.opcode[opcode->m_codenum]=w;
267 the_ins.numo++;
268}
269
270/* The numo+1 kludge is so we can hit the low order byte of the prev word.
271 Blecch. */
272static void
273add_fix (width, exp, pc_rel, pc_fix)
274 int width;
275 struct m68k_exp *exp;
276 int pc_rel;
277 int pc_fix;
278{
279 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
280 ? (the_ins.numo*2-1)
281 : (((width)=='b')
282 ? (the_ins.numo*2+1)
283 : (the_ins.numo*2)));
284 the_ins.reloc[the_ins.nrel].exp = exp->exp;
285 the_ins.reloc[the_ins.nrel].wid = width;
286 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
287#ifdef OBJ_ELF
288 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
289#endif
290 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
291}
292
293/* Cause an extra frag to be generated here, inserting up to 10 bytes
294 (that value is chosen in the frag_var call in md_assemble). TYPE
295 is the subtype of the frag to be generated; its primary type is
296 rs_machine_dependent.
297
298 The TYPE parameter is also used by md_convert_frag_1 and
299 md_estimate_size_before_relax. The appropriate type of fixup will
300 be emitted by md_convert_frag_1.
301
302 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
303static void
304add_frag (add, off, type)
305 symbolS *add;
306 offsetT off;
307 int type;
308{
309 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
310 the_ins.fragb[the_ins.nfrag].fadd=add;
311 the_ins.fragb[the_ins.nfrag].foff=off;
312 the_ins.fragb[the_ins.nfrag++].fragty=type;
313}
314
315#define isvar(ex) \
316 (op (ex) != O_constant && op (ex) != O_big)
317
318static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
319static int get_num PARAMS ((struct m68k_exp *exp, int ok));
320static void m68k_ip PARAMS ((char *));
321static void insert_reg PARAMS ((const char *, int));
322static void select_control_regs PARAMS ((void));
323static void init_regtable PARAMS ((void));
324static int reverse_16_bits PARAMS ((int in));
325static int reverse_8_bits PARAMS ((int in));
326static void install_gen_operand PARAMS ((int mode, int val));
327static void install_operand PARAMS ((int mode, int val));
328static void s_bss PARAMS ((int));
329static void s_data1 PARAMS ((int));
330static void s_data2 PARAMS ((int));
331static void s_even PARAMS ((int));
332static void s_proc PARAMS ((int));
333static void mri_chip PARAMS ((void));
334static void s_chip PARAMS ((int));
335static void s_fopt PARAMS ((int));
336static void s_opt PARAMS ((int));
337static void s_reg PARAMS ((int));
338static void s_restore PARAMS ((int));
339static void s_save PARAMS ((int));
340static void s_mri_if PARAMS ((int));
341static void s_mri_else PARAMS ((int));
342static void s_mri_endi PARAMS ((int));
343static void s_mri_break PARAMS ((int));
344static void s_mri_next PARAMS ((int));
345static void s_mri_for PARAMS ((int));
346static void s_mri_endf PARAMS ((int));
347static void s_mri_repeat PARAMS ((int));
348static void s_mri_until PARAMS ((int));
349static void s_mri_while PARAMS ((int));
350static void s_mri_endw PARAMS ((int));
351static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
352static void md_convert_frag_1 PARAMS ((fragS *));
353
354static int current_architecture;
355
dc84e067
NC		 356struct m68k_cpu
357 {
358 unsigned long arch;
359 const char *name;
360 int alias;
361 };
252b5132 362
dc84e067
NC		 363static const struct m68k_cpu archs[] =
364 {
365 { m68000, "68000", 0 },
366 { m68010, "68010", 0 },
367 { m68020, "68020", 0 },
368 { m68030, "68030", 0 },
369 { m68040, "68040", 0 },
370 { m68060, "68060", 0 },
371 { cpu32, "cpu32", 0 },
372 { m68881, "68881", 0 },
373 { m68851, "68851", 0 },
374 { mcf5200, "5200", 0 },
375 { mcf5206e, "5206e", 0 },
376 { mcf5307, "5307", 0},
377 { mcf5407, "5407", 0},
378 /* Aliases (effectively, so far as gas is concerned) for the above
379 cpus. */
380 { m68020, "68k", 1 },
381 { m68000, "68008", 1 },
382 { m68000, "68302", 1 },
383 { m68000, "68306", 1 },
384 { m68000, "68307", 1 },
385 { m68000, "68322", 1 },
386 { m68000, "68356", 1 },
387 { m68000, "68ec000", 1 },
388 { m68000, "68hc000", 1 },
389 { m68000, "68hc001", 1 },
390 { m68020, "68ec020", 1 },
391 { m68030, "68ec030", 1 },
392 { m68040, "68ec040", 1 },
393 { m68060, "68ec060", 1 },
394 { cpu32, "68330", 1 },
395 { cpu32, "68331", 1 },
396 { cpu32, "68332", 1 },
397 { cpu32, "68333", 1 },
398 { cpu32, "68334", 1 },
399 { cpu32, "68336", 1 },
400 { cpu32, "68340", 1 },
401 { cpu32, "68341", 1 },
402 { cpu32, "68349", 1 },
403 { cpu32, "68360", 1 },
404 { m68881, "68882", 1 },
405 { mcf5200, "5202", 1 },
406 { mcf5200, "5204", 1 },
407 { mcf5200, "5206", 1 },
408 };
252b5132
RH		 409
410static const int n_archs = sizeof (archs) / sizeof (archs[0]);
411
151337e8
NC		 412/* This is the assembler relaxation table for m68k. m68k is a rich CISC
413 architecture and we have a lot of relaxation modes. */
252b5132 414
151337e8
NC		 415/* Macros used in the relaxation code. */
416#define TAB(x,y) (((x) << 2) + (y))
417#define TABTYPE(x) ((x) >> 2)
418
419/* Relaxation states. */
420#define BYTE 0
421#define SHORT 1
422#define LONG 2
423#define SZ_UNDEF 3
424
425/* Here are all the relaxation modes we support. First we can relax ordinary
426 branches. On 68020 and higher and on CPU32 all branch instructions take
427 three forms, so on these CPUs all branches always remain as such. When we
428 have to expand to the LONG form on a 68000, though, we substitute an
429 absolute jump instead. This is a direct replacement for unconditional
430 branches and a branch over a jump for conditional branches. However, if the
431 user requires PIC and disables this with --pcrel, we can only relax between
432 BYTE and SHORT forms, punting if that isn't enough. This gives us four
433 different relaxation modes for branches: */
434
435#define BRANCHBWL 1 /* branch byte, word, or long */
436#define BRABSJUNC 2 /* absolute jump for LONG, unconditional */
437#define BRABSJCOND 3 /* absolute jump for LONG, conditional */
438#define BRANCHBW 4 /* branch byte or word */
439
440/* We also relax coprocessor branches and DBcc's. All CPUs that support
441 coprocessor branches support them in word and long forms, so we have only
442 one relaxation mode for them. DBcc's are word only on all CPUs. We can
443 relax them to the LONG form with a branch-around sequence. This sequence
444 can use a long branch (if available) or an absolute jump (if acceptable).
445 This gives us two relaxation modes. If long branches are not available and
446 absolute jumps are not acceptable, we don't relax DBcc's. */
447
448#define FBRANCH 5 /* coprocessor branch */
449#define DBCCLBR 6 /* DBcc relaxable with a long branch */
450#define DBCCABSJ 7 /* DBcc relaxable with an absolute jump */
451
452/* That's all for instruction relaxation. However, we also relax PC-relative
453 operands. Specifically, we have three operand relaxation modes. On the
454 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
455 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
456 two. Also PC+displacement+index operands in their simple form (with a non-
457 suppressed index without memory indirection) are supported on all CPUs, but
458 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
459 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
460 form of the PC+displacement+index operand. Finally, some absolute operands
461 can be relaxed down to 16-bit PC-relative. */
462
463#define PCREL1632 8 /* 16-bit or 32-bit PC-relative */
464#define PCINDEX 9 /* PC+displacement+index */
465#define ABSTOPCREL 10 /* absolute relax down to 16-bit PC-relative */
252b5132
RH		 466
467/* Note that calls to frag_var need to specify the maximum expansion
468 needed; this is currently 10 bytes for DBCC. */
469
470/* The fields are:
471 How far Forward this mode will reach:
472 How far Backward this mode will reach:
473 How many bytes this mode will add to the size of the frag
474 Which mode to go to if the offset won't fit in this one
475 */
476relax_typeS md_relax_table[] =
477{
478 {1, 1, 0, 0}, /* First entries aren't used */
479 {1, 1, 0, 0}, /* For no good reason except */
480 {1, 1, 0, 0}, /* that the VAX doesn't either */
481 {1, 1, 0, 0},
482
151337e8
NC		 483 {(127), (-128), 0, TAB (BRANCHBWL, SHORT)},
484 {(32767), (-32768), 2, TAB (BRANCHBWL, LONG)},
252b5132
RH		 485 {0, 0, 4, 0},
486 {1, 1, 0, 0},
487
151337e8
NC		 488 {(127), (-128), 0, TAB (BRABSJUNC, SHORT)},
489 {(32767), (-32768), 2, TAB (BRABSJUNC, LONG)},
252b5132
RH		 490 {0, 0, 4, 0},
491 {1, 1, 0, 0},
492
151337e8
NC		 493 {(127), (-128), 0, TAB (BRABSJCOND, SHORT)},
494 {(32767), (-32768), 2, TAB (BRABSJCOND, LONG)},
495 {0, 0, 6, 0},
496 {1, 1, 0, 0},
497
498 {(127), (-128), 0, TAB (BRANCHBW, SHORT)},
499 {0, 0, 2, 0},
500 {1, 1, 0, 0},
501 {1, 1, 0, 0},
502
503 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
504 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
252b5132
RH		 505 {0, 0, 4, 0},
506 {1, 1, 0, 0},
507
151337e8
NC		 508 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
509 {(32767), (-32768), 2, TAB (DBCCLBR, LONG)},
510 {0, 0, 10, 0},
252b5132
RH		 511 {1, 1, 0, 0},
512
513 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
151337e8
NC		 514 {(32767), (-32768), 2, TAB (DBCCABSJ, LONG)},
515 {0, 0, 10, 0},
252b5132
RH		 516 {1, 1, 0, 0},
517
151337e8
NC		 518 {1, 1, 0, 0}, /* PCREL1632 doesn't come BYTE */
519 {32767, -32768, 2, TAB (PCREL1632, LONG)},
252b5132
RH		 520 {0, 0, 6, 0},
521 {1, 1, 0, 0},
522
252b5132
RH		 523 {125, -130, 0, TAB (PCINDEX, SHORT)},
524 {32765, -32770, 2, TAB (PCINDEX, LONG)},
525 {0, 0, 4, 0},
526 {1, 1, 0, 0},
151337e8
NC		 527
528 {1, 1, 0, 0}, /* ABSTOPCREL doesn't come BYTE */
529 {(32767), (-32768), 2, TAB (ABSTOPCREL, LONG)},
530 {0, 0, 4, 0},
531 {1, 1, 0, 0},
252b5132
RH		 532};
533
534/* These are the machine dependent pseudo-ops. These are included so
535 the assembler can work on the output from the SUN C compiler, which
536 generates these.
537 */
538
539/* This table describes all the machine specific pseudo-ops the assembler
540 has to support. The fields are:
541 pseudo-op name without dot
542 function to call to execute this pseudo-op
543 Integer arg to pass to the function
544 */
545const pseudo_typeS md_pseudo_table[] =
546{
547 {"data1", s_data1, 0},
548 {"data2", s_data2, 0},
549 {"bss", s_bss, 0},
550 {"even", s_even, 0},
551 {"skip", s_space, 0},
552 {"proc", s_proc, 0},
553#if defined (TE_SUN3) || defined (OBJ_ELF)
554 {"align", s_align_bytes, 0},
555#endif
556#ifdef OBJ_ELF
557 {"swbeg", s_ignore, 0},
558#endif
559 {"extend", float_cons, 'x'},
560 {"ldouble", float_cons, 'x'},
561
f27a3839
AS		 562#ifdef OBJ_ELF
563 /* Dwarf2 support for Gcc. */
564 {"file", dwarf2_directive_file, 0},
565 {"loc", dwarf2_directive_loc, 0},
566#endif
567
252b5132
RH		 568 /* The following pseudo-ops are supported for MRI compatibility. */
569 {"chip", s_chip, 0},
570 {"comline", s_space, 1},
571 {"fopt", s_fopt, 0},
572 {"mask2", s_ignore, 0},
573 {"opt", s_opt, 0},
574 {"reg", s_reg, 0},
575 {"restore", s_restore, 0},
576 {"save", s_save, 0},
577
578 {"if", s_mri_if, 0},
579 {"if.b", s_mri_if, 'b'},
580 {"if.w", s_mri_if, 'w'},
581 {"if.l", s_mri_if, 'l'},
582 {"else", s_mri_else, 0},
583 {"else.s", s_mri_else, 's'},
584 {"else.l", s_mri_else, 'l'},
585 {"endi", s_mri_endi, 0},
586 {"break", s_mri_break, 0},
587 {"break.s", s_mri_break, 's'},
588 {"break.l", s_mri_break, 'l'},
589 {"next", s_mri_next, 0},
590 {"next.s", s_mri_next, 's'},
591 {"next.l", s_mri_next, 'l'},
592 {"for", s_mri_for, 0},
593 {"for.b", s_mri_for, 'b'},
594 {"for.w", s_mri_for, 'w'},
595 {"for.l", s_mri_for, 'l'},
596 {"endf", s_mri_endf, 0},
597 {"repeat", s_mri_repeat, 0},
598 {"until", s_mri_until, 0},
599 {"until.b", s_mri_until, 'b'},
600 {"until.w", s_mri_until, 'w'},
601 {"until.l", s_mri_until, 'l'},
602 {"while", s_mri_while, 0},
603 {"while.b", s_mri_while, 'b'},
604 {"while.w", s_mri_while, 'w'},
605 {"while.l", s_mri_while, 'l'},
606 {"endw", s_mri_endw, 0},
607
608 {0, 0, 0}
609};
610
252b5132
RH		 611/* The mote pseudo ops are put into the opcode table, since they
612 don't start with a . they look like opcodes to gas.
613 */
614
615#ifdef M68KCOFF
616extern void obj_coff_section PARAMS ((int));
617#endif
618
619CONST pseudo_typeS mote_pseudo_table[] =
620{
621
622 {"dcl", cons, 4},
623 {"dc", cons, 2},
624 {"dcw", cons, 2},
625 {"dcb", cons, 1},
626
627 {"dsl", s_space, 4},
628 {"ds", s_space, 2},
629 {"dsw", s_space, 2},
630 {"dsb", s_space, 1},
631
632 {"xdef", s_globl, 0},
633#ifdef OBJ_ELF
634 {"align", s_align_bytes, 0},
635#else
636 {"align", s_align_ptwo, 0},
637#endif
638#ifdef M68KCOFF
639 {"sect", obj_coff_section, 0},
640 {"section", obj_coff_section, 0},
641#endif
642 {0, 0, 0}
643};
644
645#define issbyte(x) ((x)>=-128 && (x)<=127)
646#define isubyte(x) ((x)>=0 && (x)<=255)
647#define issword(x) ((x)>=-32768 && (x)<=32767)
648#define isuword(x) ((x)>=0 && (x)<=65535)
649
650#define isbyte(x) ((x)>= -255 && (x)<=255)
651#define isword(x) ((x)>=-65536 && (x)<=65535)
652#define islong(x) (1)
653
654extern char *input_line_pointer;
655
656static char mklower_table[256];
bc805888 657#define mklower(c) (mklower_table[(unsigned char) (c)])
252b5132
RH		 658static char notend_table[256];
659static char alt_notend_table[256];
660#define notend(s) \
661 (! (notend_table[(unsigned char) *s] \
662 || (*s == ':' \
663 && alt_notend_table[(unsigned char) s[1]])))
664
665#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
666
667#ifdef NO_PCREL_RELOCS
668
669int
670make_pcrel_absolute(fixP, add_number)
671 fixS *fixP;
672 long *add_number;
673{
674 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
675
676 /* rewrite the PC relative instructions to absolute address ones.
677 * these are rumoured to be faster, and the apollo linker refuses
678 * to deal with the PC relative relocations.
679 */
680 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
681 {
682 opcode[0] = 0x4e;
683 opcode[1] = 0xf9;
684 }
685 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
686 {
687 opcode[0] = 0x4e;
688 opcode[1] = 0xb9;
689 }
690 else
691 as_fatal (_("Unknown PC relative instruction"));
692 *add_number -= 4;
693 return 0;
694}
695
696#endif /* NO_PCREL_RELOCS */
697
698short
699tc_coff_fix2rtype (fixP)
700 fixS *fixP;
701{
702 if (fixP->fx_tcbit && fixP->fx_size == 4)
703 return R_RELLONG_NEG;
704#ifdef NO_PCREL_RELOCS
705 know (fixP->fx_pcrel == 0);
706 return (fixP->fx_size == 1 ? R_RELBYTE
707 : fixP->fx_size == 2 ? R_DIR16
708 : R_DIR32);
709#else
710 return (fixP->fx_pcrel ?
711 (fixP->fx_size == 1 ? R_PCRBYTE :
712 fixP->fx_size == 2 ? R_PCRWORD :
713 R_PCRLONG) :
714 (fixP->fx_size == 1 ? R_RELBYTE :
715 fixP->fx_size == 2 ? R_RELWORD :
716 R_RELLONG));
717#endif
718}
719
720#endif
721
722#ifdef OBJ_ELF
723
c801568a
AM		 724/* Return zero if the reference to SYMBOL from within the same segment may
725 be relaxed. */
726
727/* On an ELF system, we can't relax an externally visible symbol,
728 because it may be overridden by a shared library. However, if
729 TARGET_OS is "elf", then we presume that we are assembling for an
730 embedded system, in which case we don't have to worry about shared
731 libraries, and we can relax any external sym. */
732
733#define relaxable_symbol(symbol) \
734 (!((S_IS_EXTERNAL (symbol) && strcmp (TARGET_OS, "elf") != 0) \
735 || S_IS_WEAK (symbol)))
736
252b5132
RH		 737/* Compute the relocation code for a fixup of SIZE bytes, using pc
738 relative relocation if PCREL is non-zero. PIC says whether a special
739 pic relocation was requested. */
740
741static bfd_reloc_code_real_type get_reloc_code
742 PARAMS ((int, int, enum pic_relocation));
743
744static bfd_reloc_code_real_type
745get_reloc_code (size, pcrel, pic)
746 int size;
747 int pcrel;
748 enum pic_relocation pic;
749{
750 switch (pic)
751 {
752 case pic_got_pcrel:
753 switch (size)
754 {
755 case 1:
756 return BFD_RELOC_8_GOT_PCREL;
757 case 2:
758 return BFD_RELOC_16_GOT_PCREL;
759 case 4:
760 return BFD_RELOC_32_GOT_PCREL;
761 }
762 break;
763
764 case pic_got_off:
765 switch (size)
766 {
767 case 1:
768 return BFD_RELOC_8_GOTOFF;
769 case 2:
770 return BFD_RELOC_16_GOTOFF;
771 case 4:
772 return BFD_RELOC_32_GOTOFF;
773 }
774 break;
775
776 case pic_plt_pcrel:
777 switch (size)
778 {
779 case 1:
780 return BFD_RELOC_8_PLT_PCREL;
781 case 2:
782 return BFD_RELOC_16_PLT_PCREL;
783 case 4:
784 return BFD_RELOC_32_PLT_PCREL;
785 }
786 break;
787
788 case pic_plt_off:
789 switch (size)
790 {
791 case 1:
792 return BFD_RELOC_8_PLTOFF;
793 case 2:
794 return BFD_RELOC_16_PLTOFF;
795 case 4:
796 return BFD_RELOC_32_PLTOFF;
797 }
798 break;
799
800 case pic_none:
801 if (pcrel)
802 {
803 switch (size)
804 {
805 case 1:
806 return BFD_RELOC_8_PCREL;
807 case 2:
808 return BFD_RELOC_16_PCREL;
809 case 4:
810 return BFD_RELOC_32_PCREL;
811 }
812 }
813 else
814 {
815 switch (size)
816 {
817 case 1:
818 return BFD_RELOC_8;
819 case 2:
820 return BFD_RELOC_16;
821 case 4:
822 return BFD_RELOC_32;
823 }
824 }
825 }
826
827 if (pcrel)
828 {
829 if (pic == pic_none)
830 as_bad (_("Can not do %d byte pc-relative relocation"), size);
831 else
832 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
833 }
834 else
835 {
836 if (pic == pic_none)
837 as_bad (_("Can not do %d byte relocation"), size);
838 else
839 as_bad (_("Can not do %d byte pic relocation"), size);
840 }
841
842 return BFD_RELOC_NONE;
843}
844
845/* Here we decide which fixups can be adjusted to make them relative
846 to the beginning of the section instead of the symbol. Basically
847 we need to make sure that the dynamic relocations are done
848 correctly, so in some cases we force the original symbol to be
849 used. */
850int
851tc_m68k_fix_adjustable (fixP)
852 fixS *fixP;
853{
92774660 854 /* Prevent all adjustments to global symbols. */
c801568a 855 if (! relaxable_symbol (fixP->fx_addsy))
252b5132
RH		 856 return 0;
857
858 /* adjust_reloc_syms doesn't know about the GOT */
859 switch (fixP->fx_r_type)
860 {
861 case BFD_RELOC_8_GOT_PCREL:
862 case BFD_RELOC_16_GOT_PCREL:
863 case BFD_RELOC_32_GOT_PCREL:
864 case BFD_RELOC_8_GOTOFF:
865 case BFD_RELOC_16_GOTOFF:
866 case BFD_RELOC_32_GOTOFF:
867 case BFD_RELOC_8_PLT_PCREL:
868 case BFD_RELOC_16_PLT_PCREL:
869 case BFD_RELOC_32_PLT_PCREL:
870 case BFD_RELOC_8_PLTOFF:
871 case BFD_RELOC_16_PLTOFF:
872 case BFD_RELOC_32_PLTOFF:
873 return 0;
874
875 case BFD_RELOC_VTABLE_INHERIT:
876 case BFD_RELOC_VTABLE_ENTRY:
877 return 0;
878
879 default:
880 return 1;
881 }
882}
883
884#else /* !OBJ_ELF */
885
886#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
887
c801568a
AM		 888#define relaxable_symbol(symbol) 1
889
252b5132
RH		 890#endif /* OBJ_ELF */
891
892#ifdef BFD_ASSEMBLER
893
894arelent *
895tc_gen_reloc (section, fixp)
896 asection *section;
897 fixS *fixp;
898{
899 arelent *reloc;
900 bfd_reloc_code_real_type code;
901
8ec6253e
NC		 902 /* If the tcbit is set, then this was a fixup of a negative value
903 that was never resolved. We do not have a reloc to handle this,
904 so just return. We assume that other code will have detected this
905 situation and produced a helpful error message, so we just tell the
906 user that the reloc cannot be produced. */
252b5132 907 if (fixp->fx_tcbit)
8ec6253e
NC		 908 {
909 if (fixp->fx_addsy)
b091f402
AM		 910 as_bad_where (fixp->fx_file, fixp->fx_line,
911 _("Unable to produce reloc against symbol '%s'"),
912 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 913 return NULL;
914 }
252b5132
RH		 915
916 if (fixp->fx_r_type != BFD_RELOC_NONE)
917 {
918 code = fixp->fx_r_type;
919
920 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
921 that fixup_segment converted a non-PC relative reloc into a
922 PC relative reloc. In such a case, we need to convert the
923 reloc code. */
924 if (fixp->fx_pcrel)
925 {
926 switch (code)
927 {
928 case BFD_RELOC_8:
929 code = BFD_RELOC_8_PCREL;
930 break;
931 case BFD_RELOC_16:
932 code = BFD_RELOC_16_PCREL;
933 break;
934 case BFD_RELOC_32:
935 code = BFD_RELOC_32_PCREL;
936 break;
937 case BFD_RELOC_8_PCREL:
938 case BFD_RELOC_16_PCREL:
939 case BFD_RELOC_32_PCREL:
940 case BFD_RELOC_8_GOT_PCREL:
941 case BFD_RELOC_16_GOT_PCREL:
942 case BFD_RELOC_32_GOT_PCREL:
943 case BFD_RELOC_8_GOTOFF:
944 case BFD_RELOC_16_GOTOFF:
945 case BFD_RELOC_32_GOTOFF:
946 case BFD_RELOC_8_PLT_PCREL:
947 case BFD_RELOC_16_PLT_PCREL:
948 case BFD_RELOC_32_PLT_PCREL:
949 case BFD_RELOC_8_PLTOFF:
950 case BFD_RELOC_16_PLTOFF:
951 case BFD_RELOC_32_PLTOFF:
952 break;
953 default:
954 as_bad_where (fixp->fx_file, fixp->fx_line,
955 _("Cannot make %s relocation PC relative"),
956 bfd_get_reloc_code_name (code));
957 }
958 }
959 }
960 else
961 {
962#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
963 switch (F (fixp->fx_size, fixp->fx_pcrel))
964 {
965#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
966 MAP (1, 0, BFD_RELOC_8);
967 MAP (2, 0, BFD_RELOC_16);
968 MAP (4, 0, BFD_RELOC_32);
969 MAP (1, 1, BFD_RELOC_8_PCREL);
970 MAP (2, 1, BFD_RELOC_16_PCREL);
971 MAP (4, 1, BFD_RELOC_32_PCREL);
972 default:
973 abort ();
974 }
975 }
976#undef F
977#undef MAP
978
979 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 980 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
981 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 982 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
983#ifndef OBJ_ELF
984 if (fixp->fx_pcrel)
985 reloc->addend = fixp->fx_addnumber;
986 else
987 reloc->addend = 0;
988#else
989 if (!fixp->fx_pcrel)
990 reloc->addend = fixp->fx_addnumber;
991 else
992 reloc->addend = (section->vma
8390138c
AS		 993 /* Explicit sign extension in case char is
994 unsigned. */
995 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 996 + fixp->fx_addnumber
997 + md_pcrel_from (fixp));
998#endif
999
1000 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1001 assert (reloc->howto != 0);
1002
1003 return reloc;
1004}
1005
1006#endif /* BFD_ASSEMBLER */
1007
252b5132
RH		 1008/* Handle of the OPCODE hash table. NULL means any use before
1009 m68k_ip_begin() will crash. */
1010static struct hash_control *op_hash;
1011\f
1012/* Assemble an m68k instruction. */
1013
1014static void
1015m68k_ip (instring)
1016 char *instring;
1017{
1018 register char *p;
1019 register struct m68k_op *opP;
1020 register const struct m68k_incant *opcode;
1021 register const char *s;
1022 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1023 char *pdot, *pdotmove;
1024 enum m68k_size siz1, siz2;
1025 char c;
1026 int losing;
1027 int opsfound;
1028 LITTLENUM_TYPE words[6];
1029 LITTLENUM_TYPE *wordp;
1030 unsigned long ok_arch = 0;
1031
1032 if (*instring == ' ')
1033 instring++; /* skip leading whitespace */
1034
1035 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1036 or exactly 1 space. */
252b5132
RH		 1037 pdot = 0;
1038 for (p = instring; *p != '\0'; p++)
1039 {
1040 if (*p == ' ')
1041 break;
1042 if (*p == '.')
1043 pdot = p;
1044 }
1045
1046 if (p == instring)
1047 {
1048 the_ins.error = _("No operator");
1049 return;
1050 }
1051
1052 /* p now points to the end of the opcode name, probably whitespace.
1053 Make sure the name is null terminated by clobbering the
1054 whitespace, look it up in the hash table, then fix it back.
1055 Remove a dot, first, since the opcode tables have none. */
1056 if (pdot != NULL)
1057 {
1058 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1059 *pdotmove = pdotmove[1];
1060 p--;
1061 }
1062
1063 c = *p;
1064 *p = '\0';
1065 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1066 *p = c;
1067
1068 if (pdot != NULL)
1069 {
1070 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1071 *pdotmove = pdotmove[-1];
1072 *pdot = '.';
1073 ++p;
1074 }
1075
1076 if (opcode == NULL)
1077 {
1078 the_ins.error = _("Unknown operator");
1079 return;
1080 }
1081
1082 /* found a legitimate opcode, start matching operands */
1083 while (*p == ' ')
1084 ++p;
1085
1086 if (opcode->m_operands == 0)
1087 {
1088 char *old = input_line_pointer;
1089 *old = '\n';
1090 input_line_pointer = p;
1091 /* Ahh - it's a motorola style psuedo op */
1092 mote_pseudo_table[opcode->m_opnum].poc_handler
1093 (mote_pseudo_table[opcode->m_opnum].poc_val);
1094 input_line_pointer = old;
1095 *old = 0;
1096
1097 return;
1098 }
1099
1100 if (flag_mri && opcode->m_opnum == 0)
1101 {
1102 /* In MRI mode, random garbage is allowed after an instruction
1103 which accepts no operands. */
1104 the_ins.args = opcode->m_operands;
1105 the_ins.numargs = opcode->m_opnum;
1106 the_ins.numo = opcode->m_codenum;
1107 the_ins.opcode[0] = getone (opcode);
1108 the_ins.opcode[1] = gettwo (opcode);
1109 return;
1110 }
1111
1112 for (opP = &the_ins.operands[0]; *p; opP++)
1113 {
1114 p = crack_operand (p, opP);
1115
1116 if (opP->error)
1117 {
1118 the_ins.error = opP->error;
1119 return;
1120 }
1121 }
1122
1123 opsfound = opP - &the_ins.operands[0];
1124
1125 /* This ugly hack is to support the floating pt opcodes in their
1126 standard form. Essentially, we fake a first enty of type COP#1 */
1127 if (opcode->m_operands[0] == 'I')
1128 {
1129 int n;
1130
1131 for (n = opsfound; n > 0; --n)
1132 the_ins.operands[n] = the_ins.operands[n - 1];
1133
1134 memset ((char *) (&the_ins.operands[0]), '\0',
1135 sizeof (the_ins.operands[0]));
1136 the_ins.operands[0].mode = CONTROL;
1137 the_ins.operands[0].reg = m68k_float_copnum;
1138 opsfound++;
1139 }
1140
1141 /* We've got the operands. Find an opcode that'll accept them */
1142 for (losing = 0;;)
1143 {
1144 /* If we didn't get the right number of ops, or we have no
92774660 1145 common model with this pattern then reject this pattern. */
252b5132
RH		 1146
1147 ok_arch |= opcode->m_arch;
1148 if (opsfound != opcode->m_opnum
1149 || ((opcode->m_arch & current_architecture) == 0))
1150 ++losing;
1151 else
1152 {
1153 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1154 *s && !losing;
1155 s += 2, opP++)
1156 {
1157 /* Warning: this switch is huge! */
1158 /* I've tried to organize the cases into this order:
1159 non-alpha first, then alpha by letter. Lower-case
1160 goes directly before uppercase counterpart. */
1161 /* Code with multiple case ...: gets sorted by the lowest
1162 case ... it belongs to. I hope this makes sense. */
1163 switch (*s)
1164 {
1165 case '!':
1166 switch (opP->mode)
1167 {
1168 case IMMED:
1169 case DREG:
1170 case AREG:
1171 case FPREG:
1172 case CONTROL:
1173 case AINC:
1174 case ADEC:
1175 case REGLST:
1176 losing++;
1177 break;
1178 default:
1179 break;
1180 }
1181 break;
1182
1183 case '<':
1184 switch (opP->mode)
1185 {
1186 case DREG:
1187 case AREG:
1188 case FPREG:
1189 case CONTROL:
1190 case IMMED:
1191 case ADEC:
1192 case REGLST:
1193 losing++;
1194 break;
1195 default:
1196 break;
1197 }
1198 break;
1199
1200 case '>':
1201 switch (opP->mode)
1202 {
1203 case DREG:
1204 case AREG:
1205 case FPREG:
1206 case CONTROL:
1207 case IMMED:
1208 case AINC:
1209 case REGLST:
1210 losing++;
1211 break;
1212 case ABSL:
1213 break;
1214 default:
1215 if (opP->reg == PC
1216 || opP->reg == ZPC)
1217 losing++;
1218 break;
1219 }
1220 break;
1221
1222 case 'm':
1223 switch (opP->mode)
1224 {
1225 case DREG:
1226 case AREG:
1227 case AINDR:
1228 case AINC:
1229 case ADEC:
1230 break;
1231 default:
1232 losing++;
1233 }
1234 break;
1235
1236 case 'n':
1237 switch (opP->mode)
1238 {
1239 case DISP:
1240 break;
1241 default:
1242 losing++;
1243 }
1244 break;
1245
1246 case 'o':
1247 switch (opP->mode)
1248 {
1249 case BASE:
1250 case ABSL:
1251 case IMMED:
1252 break;
1253 default:
1254 losing++;
1255 }
1256 break;
1257
1258 case 'p':
1259 switch (opP->mode)
1260 {
1261 case DREG:
1262 case AREG:
1263 case AINDR:
1264 case AINC:
1265 case ADEC:
1266 break;
1267 case DISP:
1268 if (opP->reg == PC || opP->reg == ZPC)
1269 losing++;
1270 break;
1271 default:
1272 losing++;
1273 }
1274 break;
1275
1276 case 'q':
1277 switch (opP->mode)
1278 {
1279 case DREG:
1280 case AINDR:
1281 case AINC:
1282 case ADEC:
1283 break;
1284 case DISP:
1285 if (opP->reg == PC || opP->reg == ZPC)
1286 losing++;
1287 break;
1288 default:
1289 losing++;
1290 break;
1291 }
1292 break;
1293
1294 case 'v':
1295 switch (opP->mode)
1296 {
1297 case DREG:
1298 case AINDR:
1299 case AINC:
1300 case ADEC:
1301 case ABSL:
1302 break;
1303 case DISP:
1304 if (opP->reg == PC || opP->reg == ZPC)
1305 losing++;
1306 break;
1307 default:
1308 losing++;
1309 break;
1310 }
1311 break;
1312
1313 case '#':
1314 if (opP->mode != IMMED)
1315 losing++;
1316 else if (s[1] == 'b'
1317 && ! isvar (&opP->disp)
1318 && (opP->disp.exp.X_op != O_constant
1319 || ! isbyte (opP->disp.exp.X_add_number)))
1320 losing++;
1321 else if (s[1] == 'B'
1322 && ! isvar (&opP->disp)
1323 && (opP->disp.exp.X_op != O_constant
1324 || ! issbyte (opP->disp.exp.X_add_number)))
1325 losing++;
1326 else if (s[1] == 'w'
1327 && ! isvar (&opP->disp)
1328 && (opP->disp.exp.X_op != O_constant
1329 || ! isword (opP->disp.exp.X_add_number)))
1330 losing++;
1331 else if (s[1] == 'W'
1332 && ! isvar (&opP->disp)
1333 && (opP->disp.exp.X_op != O_constant
1334 || ! issword (opP->disp.exp.X_add_number)))
1335 losing++;
1336 break;
1337
1338 case '^':
1339 case 'T':
1340 if (opP->mode != IMMED)
1341 losing++;
1342 break;
1343
1344 case '$':
1345 if (opP->mode == AREG
1346 || opP->mode == CONTROL
1347 || opP->mode == FPREG
1348 || opP->mode == IMMED
1349 || opP->mode == REGLST
1350 || (opP->mode != ABSL
1351 && (opP->reg == PC
1352 || opP->reg == ZPC)))
1353 losing++;
1354 break;
1355
1356 case '%':
1357 if (opP->mode == CONTROL
1358 || opP->mode == FPREG
1359 || opP->mode == REGLST
1360 || opP->mode == IMMED
1361 || (opP->mode != ABSL
1362 && (opP->reg == PC
1363 || opP->reg == ZPC)))
1364 losing++;
1365 break;
1366
1367 case '&':
1368 switch (opP->mode)
1369 {
1370 case DREG:
1371 case AREG:
1372 case FPREG:
1373 case CONTROL:
1374 case IMMED:
1375 case AINC:
1376 case ADEC:
1377 case REGLST:
1378 losing++;
1379 break;
1380 case ABSL:
1381 break;
1382 default:
1383 if (opP->reg == PC
1384 || opP->reg == ZPC)
1385 losing++;
1386 break;
1387 }
1388 break;
1389
1390 case '*':
1391 if (opP->mode == CONTROL
1392 || opP->mode == FPREG
1393 || opP->mode == REGLST)
1394 losing++;
1395 break;
1396
1397 case '+':
1398 if (opP->mode != AINC)
1399 losing++;
1400 break;
1401
1402 case '-':
1403 if (opP->mode != ADEC)
1404 losing++;
1405 break;
1406
1407 case '/':
1408 switch (opP->mode)
1409 {
1410 case AREG:
1411 case CONTROL:
1412 case FPREG:
1413 case AINC:
1414 case ADEC:
1415 case IMMED:
1416 case REGLST:
1417 losing++;
1418 break;
1419 default:
1420 break;
1421 }
1422 break;
1423
1424 case ';':
1425 switch (opP->mode)
1426 {
1427 case AREG:
1428 case CONTROL:
1429 case FPREG:
1430 case REGLST:
1431 losing++;
1432 break;
1433 default:
1434 break;
1435 }
1436 break;
1437
1438 case '?':
1439 switch (opP->mode)
1440 {
1441 case AREG:
1442 case CONTROL:
1443 case FPREG:
1444 case AINC:
1445 case ADEC:
1446 case IMMED:
1447 case REGLST:
1448 losing++;
1449 break;
1450 case ABSL:
1451 break;
1452 default:
1453 if (opP->reg == PC || opP->reg == ZPC)
1454 losing++;
1455 break;
1456 }
1457 break;
1458
1459 case '@':
1460 switch (opP->mode)
1461 {
1462 case AREG:
1463 case CONTROL:
1464 case FPREG:
1465 case IMMED:
1466 case REGLST:
1467 losing++;
1468 break;
1469 default:
1470 break;
1471 }
1472 break;
1473
1474 case '~': /* For now! (JF FOO is this right?) */
1475 switch (opP->mode)
1476 {
1477 case DREG:
1478 case AREG:
1479 case CONTROL:
1480 case FPREG:
1481 case IMMED:
1482 case REGLST:
1483 losing++;
1484 break;
1485 case ABSL:
1486 break;
1487 default:
1488 if (opP->reg == PC
1489 || opP->reg == ZPC)
1490 losing++;
1491 break;
1492 }
1493 break;
1494
1495 case '3':
1496 if (opP->mode != CONTROL
1497 || (opP->reg != TT0 && opP->reg != TT1))
1498 losing++;
1499 break;
1500
1501 case 'A':
1502 if (opP->mode != AREG)
1503 losing++;
1504 break;
1505
1506 case 'a':
1507 if (opP->mode != AINDR)
1508 ++losing;
1509 break;
1510
1511 case 'B': /* FOO */
1512 if (opP->mode != ABSL
1513 || (flag_long_jumps
1514 && strncmp (instring, "jbsr", 4) == 0))
1515 losing++;
1516 break;
1517
1518 case 'C':
1519 if (opP->mode != CONTROL || opP->reg != CCR)
1520 losing++;
1521 break;
1522
1523 case 'd':
1524 if (opP->mode != DISP
1525 || opP->reg < ADDR0
1526 || opP->reg > ADDR7)
1527 losing++;
1528 break;
1529
1530 case 'D':
1531 if (opP->mode != DREG)
1532 losing++;
1533 break;
1534
6da466c7
ILT		 1535 case 'E':
1536 if (opP->reg != ACC)
1537 losing++;
1538 break;
1539
252b5132
RH		 1540 case 'F':
1541 if (opP->mode != FPREG)
1542 losing++;
1543 break;
1544
6da466c7
ILT		 1545 case 'G':
1546 if (opP->reg != MACSR)
1547 losing++;
1548 break;
1549
1550 case 'H':
1551 if (opP->reg != MASK)
1552 losing++;
1553 break;
1554
252b5132
RH		 1555 case 'I':
1556 if (opP->mode != CONTROL
1557 || opP->reg < COP0
1558 || opP->reg > COP7)
1559 losing++;
1560 break;
1561
1562 case 'J':
1563 if (opP->mode != CONTROL
1564 || opP->reg < USP
1565 || opP->reg > last_movec_reg)
1566 losing++;
1567 else
1568 {
1569 const enum m68k_register *rp;
1570 for (rp = control_regs; *rp; rp++)
1571 if (*rp == opP->reg)
1572 break;
1573 if (*rp == 0)
1574 losing++;
1575 }
1576 break;
1577
1578 case 'k':
1579 if (opP->mode != IMMED)
1580 losing++;
1581 break;
1582
1583 case 'l':
1584 case 'L':
1585 if (opP->mode == DREG
1586 || opP->mode == AREG
1587 || opP->mode == FPREG)
1588 {
1589 if (s[1] == '8')
1590 losing++;
1591 else
1592 {
1593 switch (opP->mode)
1594 {
1595 case DREG:
1596 opP->mask = 1 << (opP->reg - DATA0);
1597 break;
1598 case AREG:
1599 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1600 break;
1601 case FPREG:
1602 opP->mask = 1 << (opP->reg - FP0 + 16);
1603 break;
1604 default:
1605 abort ();
1606 }
1607 opP->mode = REGLST;
1608 }
1609 }
1610 else if (opP->mode == CONTROL)
1611 {
1612 if (s[1] != '8')
1613 losing++;
1614 else
1615 {
1616 switch (opP->reg)
1617 {
1618 case FPI:
1619 opP->mask = 1 << 24;
1620 break;
1621 case FPS:
1622 opP->mask = 1 << 25;
1623 break;
1624 case FPC:
1625 opP->mask = 1 << 26;
1626 break;
1627 default:
1628 losing++;
1629 break;
1630 }
1631 opP->mode = REGLST;
1632 }
1633 }
1634 else if (opP->mode != REGLST)
1635 losing++;
1636 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1637 losing++;
1638 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1639 losing++;
1640 break;
1641
1642 case 'M':
1643 if (opP->mode != IMMED)
1644 losing++;
1645 else if (opP->disp.exp.X_op != O_constant
1646 || ! issbyte (opP->disp.exp.X_add_number))
1647 losing++;
1648 else if (! m68k_quick
1649 && instring[3] != 'q'
1650 && instring[4] != 'q')
1651 losing++;
1652 break;
1653
1654 case 'O':
1655 if (opP->mode != DREG
1656 && opP->mode != IMMED
1657 && opP->mode != ABSL)
1658 losing++;
1659 break;
1660
1661 case 'Q':
1662 if (opP->mode != IMMED)
1663 losing++;
1664 else if (opP->disp.exp.X_op != O_constant
1665 || opP->disp.exp.X_add_number < 1
1666 || opP->disp.exp.X_add_number > 8)
1667 losing++;
1668 else if (! m68k_quick
1669 && (strncmp (instring, "add", 3) == 0
1670 || strncmp (instring, "sub", 3) == 0)
1671 && instring[3] != 'q')
1672 losing++;
1673 break;
1674
1675 case 'R':
1676 if (opP->mode != DREG && opP->mode != AREG)
1677 losing++;
1678 break;
1679
1680 case 'r':
1681 if (opP->mode != AINDR
1682 && (opP->mode != BASE
1683 || (opP->reg != 0
1684 && opP->reg != ZADDR0)
1685 || opP->disp.exp.X_op != O_absent
1686 || ((opP->index.reg < DATA0
1687 || opP->index.reg > DATA7)
1688 && (opP->index.reg < ADDR0
1689 || opP->index.reg > ADDR7))
1690 || opP->index.size != SIZE_UNSPEC
1691 || opP->index.scale != 1))
1692 losing++;
1693 break;
1694
1695 case 's':
1696 if (opP->mode != CONTROL
1697 || ! (opP->reg == FPI
1698 || opP->reg == FPS
1699 || opP->reg == FPC))
1700 losing++;
1701 break;
1702
1703 case 'S':
1704 if (opP->mode != CONTROL || opP->reg != SR)
1705 losing++;
1706 break;
1707
1708 case 't':
1709 if (opP->mode != IMMED)
1710 losing++;
1711 else if (opP->disp.exp.X_op != O_constant
1712 || opP->disp.exp.X_add_number < 0
1713 || opP->disp.exp.X_add_number > 7)
1714 losing++;
1715 break;
1716
1717 case 'U':
1718 if (opP->mode != CONTROL || opP->reg != USP)
1719 losing++;
1720 break;
1721
1722 /* JF these are out of order. We could put them
1723 in order if we were willing to put up with
1724 bunches of #ifdef m68851s in the code.
1725
1726 Don't forget that you need these operands
1727 to use 68030 MMU instructions. */
1728#ifndef NO_68851
1729 /* Memory addressing mode used by pflushr */
1730 case '|':
1731 if (opP->mode == CONTROL
1732 || opP->mode == FPREG
1733 || opP->mode == DREG
1734 || opP->mode == AREG
1735 || opP->mode == REGLST)
1736 losing++;
1737 /* We should accept immediate operands, but they
1738 supposedly have to be quad word, and we don't
1739 handle that. I would like to see what a Motorola
1740 assembler does before doing something here. */
1741 if (opP->mode == IMMED)
1742 losing++;
1743 break;
1744
1745 case 'f':
1746 if (opP->mode != CONTROL
1747 || (opP->reg != SFC && opP->reg != DFC))
1748 losing++;
1749 break;
1750
1751 case '0':
1752 if (opP->mode != CONTROL || opP->reg != TC)
1753 losing++;
1754 break;
1755
1756 case '1':
1757 if (opP->mode != CONTROL || opP->reg != AC)
1758 losing++;
1759 break;
1760
1761 case '2':
1762 if (opP->mode != CONTROL
1763 || (opP->reg != CAL
1764 && opP->reg != VAL
1765 && opP->reg != SCC))
1766 losing++;
1767 break;
1768
1769 case 'V':
1770 if (opP->mode != CONTROL
1771 || opP->reg != VAL)
1772 losing++;
1773 break;
1774
1775 case 'W':
1776 if (opP->mode != CONTROL
1777 || (opP->reg != DRP
1778 && opP->reg != SRP
1779 && opP->reg != CRP))
1780 losing++;
1781 break;
1782
1783 case 'X':
1784 if (opP->mode != CONTROL
1785 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1786 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1787 losing++;
1788 break;
1789
1790 case 'Y':
1791 if (opP->mode != CONTROL || opP->reg != PSR)
1792 losing++;
1793 break;
1794
1795 case 'Z':
1796 if (opP->mode != CONTROL || opP->reg != PCSR)
1797 losing++;
1798 break;
1799#endif
1800 case 'c':
1801 if (opP->mode != CONTROL
1802 || (opP->reg != NC
1803 && opP->reg != IC
1804 && opP->reg != DC
1805 && opP->reg != BC))
1806 {
1807 losing++;
92774660 1808 } /* not a cache specifier. */
252b5132
RH		 1809 break;
1810
1811 case '_':
1812 if (opP->mode != ABSL)
1813 ++losing;
1814 break;
1815
6da466c7
ILT		 1816 case 'u':
1817 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1818 losing++;
1819 /* FIXME: kludge instead of fixing parser:
1820 upper/lower registers are *not* CONTROL
92774660 1821 registers, but ordinary ones. */
6da466c7
ILT		 1822 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1823 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1824 opP->mode = DREG;
1825 else
1826 opP->mode = AREG;
1827 break;
1828
252b5132
RH		 1829 default:
1830 abort ();
1831 } /* switch on type of operand */
1832
1833 if (losing)
1834 break;
1835 } /* for each operand */
1836 } /* if immediately wrong */
1837
1838 if (!losing)
1839 {
1840 break;
92774660 1841 } /* got it. */
252b5132
RH		 1842
1843 opcode = opcode->m_next;
1844
1845 if (!opcode)
1846 {
1847 if (ok_arch
1848 && !(ok_arch & current_architecture))
1849 {
1850 char buf[200], *cp;
1851
1852 strcpy (buf,
1853 _("invalid instruction for this architecture; needs "));
1854 cp = buf + strlen (buf);
1855 switch (ok_arch)
1856 {
1857 case mfloat:
1858 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1859 break;
1860 case mmmu:
1861 strcpy (cp, _("mmu (68030 or 68851)"));
1862 break;
1863 case m68020up:
1864 strcpy (cp, _("68020 or higher"));
1865 break;
1866 case m68000up:
1867 strcpy (cp, _("68000 or higher"));
1868 break;
1869 case m68010up:
1870 strcpy (cp, _("68010 or higher"));
1871 break;
1872 default:
1873 {
1874 int got_one = 0, idx;
8fce3f5e
AM		 1875 for (idx = 0;
1876 idx < (int) (sizeof (archs) / sizeof (archs[0]));
252b5132
RH		 1877 idx++)
1878 {
1879 if ((archs[idx].arch & ok_arch)
1880 && ! archs[idx].alias)
1881 {
1882 if (got_one)
1883 {
1884 strcpy (cp, " or ");
1885 cp += strlen (cp);
1886 }
1887 got_one = 1;
1888 strcpy (cp, archs[idx].name);
1889 cp += strlen (cp);
1890 }
1891 }
1892 }
1893 }
1894 cp = xmalloc (strlen (buf) + 1);
1895 strcpy (cp, buf);
1896 the_ins.error = cp;
1897 }
1898 else
1899 the_ins.error = _("operands mismatch");
1900 return;
1901 } /* Fell off the end */
1902
1903 losing = 0;
1904 }
1905
1906 /* now assemble it */
1907
1908 the_ins.args = opcode->m_operands;
1909 the_ins.numargs = opcode->m_opnum;
1910 the_ins.numo = opcode->m_codenum;
1911 the_ins.opcode[0] = getone (opcode);
1912 the_ins.opcode[1] = gettwo (opcode);
1913
1914 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1915 {
1916 /* This switch is a doozy.
1917 Watch the first step; its a big one! */
1918 switch (s[0])
1919 {
1920
1921 case '*':
1922 case '~':
1923 case '%':
1924 case ';':
1925 case '@':
1926 case '!':
1927 case '&':
1928 case '$':
1929 case '?':
1930 case '/':
1931 case '<':
1932 case '>':
1933 case 'm':
1934 case 'n':
1935 case 'o':
1936 case 'p':
1937 case 'q':
1938 case 'v':
1939#ifndef NO_68851
1940 case '|':
1941#endif
1942 switch (opP->mode)
1943 {
1944 case IMMED:
1945 tmpreg = 0x3c; /* 7.4 */
1946 if (strchr ("bwl", s[1]))
1947 nextword = get_num (&opP->disp, 80);
1948 else
1949 nextword = get_num (&opP->disp, 0);
1950 if (isvar (&opP->disp))
1951 add_fix (s[1], &opP->disp, 0, 0);
1952 switch (s[1])
1953 {
1954 case 'b':
1955 if (!isbyte (nextword))
1956 opP->error = _("operand out of range");
1957 addword (nextword);
1958 baseo = 0;
1959 break;
1960 case 'w':
1961 if (!isword (nextword))
1962 opP->error = _("operand out of range");
1963 addword (nextword);
1964 baseo = 0;
1965 break;
1966 case 'W':
1967 if (!issword (nextword))
1968 opP->error = _("operand out of range");
1969 addword (nextword);
1970 baseo = 0;
1971 break;
1972 case 'l':
1973 addword (nextword >> 16);
1974 addword (nextword);
1975 baseo = 0;
1976 break;
1977
1978 case 'f':
1979 baseo = 2;
1980 outro = 8;
1981 break;
1982 case 'F':
1983 baseo = 4;
1984 outro = 11;
1985 break;
1986 case 'x':
1987 baseo = 6;
1988 outro = 15;
1989 break;
1990 case 'p':
1991 baseo = 6;
1992 outro = -1;
1993 break;
1994 default:
1995 abort ();
1996 }
1997 if (!baseo)
1998 break;
1999
2000 /* We gotta put out some float */
2001 if (op (&opP->disp) != O_big)
2002 {
2003 valueT val;
2004 int gencnt;
2005
2006 /* Can other cases happen here? */
2007 if (op (&opP->disp) != O_constant)
2008 abort ();
2009
2010 val = (valueT) offs (&opP->disp);
2011 gencnt = 0;
2012 do
2013 {
2014 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2015 val >>= LITTLENUM_NUMBER_OF_BITS;
2016 ++gencnt;
2017 }
2018 while (val != 0);
2019 offs (&opP->disp) = gencnt;
2020 }
2021 if (offs (&opP->disp) > 0)
2022 {
2023 if (offs (&opP->disp) > baseo)
2024 {
2025 as_warn (_("Bignum too big for %c format; truncated"),
2026 s[1]);
2027 offs (&opP->disp) = baseo;
2028 }
2029 baseo -= offs (&opP->disp);
2030 while (baseo--)
2031 addword (0);
2032 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2033 offs (&opP->disp)--;
2034 --wordp)
2035 addword (*wordp);
2036 break;
2037 }
2038 gen_to_words (words, baseo, (long) outro);
2039 for (wordp = words; baseo--; wordp++)
2040 addword (*wordp);
2041 break;
2042 case DREG:
2043 tmpreg = opP->reg - DATA; /* 0.dreg */
2044 break;
2045 case AREG:
2046 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2047 break;
2048 case AINDR:
2049 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2050 break;
2051 case ADEC:
2052 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2053 break;
2054 case AINC:
2055 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2056 break;
2057 case DISP:
2058
2059 nextword = get_num (&opP->disp, 80);
2060
2061 if (opP->reg == PC
2062 && ! isvar (&opP->disp)
2063 && m68k_abspcadd)
2064 {
2065 opP->disp.exp.X_op = O_symbol;
2066#ifndef BFD_ASSEMBLER
2067 opP->disp.exp.X_add_symbol = &abs_symbol;
2068#else
2069 opP->disp.exp.X_add_symbol =
2070 section_symbol (absolute_section);
2071#endif
2072 }
2073
2074 /* Force into index mode. Hope this works */
2075
2076 /* We do the first bit for 32-bit displacements, and the
2077 second bit for 16 bit ones. It is possible that we
2078 should make the default be WORD instead of LONG, but
2079 I think that'd break GCC, so we put up with a little
2080 inefficiency for the sake of working output. */
2081
2082 if (!issword (nextword)
2083 || (isvar (&opP->disp)
2084 && ((opP->disp.size == SIZE_UNSPEC
2085 && flag_short_refs == 0
2086 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2087 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2088 || opP->disp.size == SIZE_LONG)))
2089 {
2090 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2091 || arch_coldfire_p (current_architecture))
252b5132
RH		 2092 opP->error =
2093 _("displacement too large for this architecture; needs 68020 or higher");
2094 if (opP->reg == PC)
2095 tmpreg = 0x3B; /* 7.3 */
2096 else
2097 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2098 if (isvar (&opP->disp))
2099 {
2100 if (opP->reg == PC)
2101 {
2102 if (opP->disp.size == SIZE_LONG
2103#ifdef OBJ_ELF
2104 /* If the displacement needs pic
2105 relocation it cannot be relaxed. */
2106 || opP->disp.pic_reloc != pic_none
2107#endif
2108 )
2109 {
2110 addword (0x0170);
2111 add_fix ('l', &opP->disp, 1, 2);
2112 }
2113 else
2114 {
2115 add_frag (adds (&opP->disp),
2116 offs (&opP->disp),
151337e8 2117 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2118 break;
2119 }
2120 }
2121 else
2122 {
2123 addword (0x0170);
2124 add_fix ('l', &opP->disp, 0, 0);
2125 }
2126 }
2127 else
2128 addword (0x0170);
2129 addword (nextword >> 16);
2130 }
2131 else
2132 {
2133 if (opP->reg == PC)
2134 tmpreg = 0x3A; /* 7.2 */
2135 else
2136 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2137
2138 if (isvar (&opP->disp))
2139 {
2140 if (opP->reg == PC)
2141 {
2142 add_fix ('w', &opP->disp, 1, 0);
2143 }
2144 else
2145 add_fix ('w', &opP->disp, 0, 0);
2146 }
2147 }
2148 addword (nextword);
2149 break;
2150
2151 case POST:
2152 case PRE:
2153 case BASE:
2154 nextword = 0;
2155 baseo = get_num (&opP->disp, 80);
2156 if (opP->mode == POST || opP->mode == PRE)
2157 outro = get_num (&opP->odisp, 80);
2158 /* Figure out the `addressing mode'.
2159 Also turn on the BASE_DISABLE bit, if needed. */
2160 if (opP->reg == PC || opP->reg == ZPC)
2161 {
2162 tmpreg = 0x3b; /* 7.3 */
2163 if (opP->reg == ZPC)
2164 nextword |= 0x80;
2165 }
2166 else if (opP->reg == 0)
2167 {
2168 nextword |= 0x80;
2169 tmpreg = 0x30; /* 6.garbage */
2170 }
2171 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2172 {
2173 nextword |= 0x80;
2174 tmpreg = 0x30 + opP->reg - ZADDR0;
2175 }
2176 else
2177 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2178
2179 siz1 = opP->disp.size;
2180 if (opP->mode == POST || opP->mode == PRE)
2181 siz2 = opP->odisp.size;
2182 else
2183 siz2 = SIZE_UNSPEC;
2184
2185 /* Index register stuff */
2186 if (opP->index.reg != 0
2187 && opP->index.reg >= DATA
2188 && opP->index.reg <= ADDR7)
2189 {
2190 nextword |= (opP->index.reg - DATA) << 12;
2191
2192 if (opP->index.size == SIZE_LONG
2193 || (opP->index.size == SIZE_UNSPEC
2194 && m68k_index_width_default == SIZE_LONG))
2195 nextword |= 0x800;
2196
92774660 2197 if ((opP->index.scale != 1
252b5132 2198 && cpu_of_arch (current_architecture) < m68020)
92774660 2199 || (opP->index.scale == 8
6da466c7 2200 && arch_coldfire_p (current_architecture)))
252b5132
RH		 2201 {
2202 opP->error =
2203 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2204 }
2205
6da466c7
ILT		 2206 if (arch_coldfire_p (current_architecture)
2207 && opP->index.size == SIZE_WORD)
2208 opP->error = _("invalid index size for coldfire");
2209
252b5132
RH		 2210 switch (opP->index.scale)
2211 {
2212 case 1:
2213 break;
2214 case 2:
2215 nextword |= 0x200;
2216 break;
2217 case 4:
2218 nextword |= 0x400;
2219 break;
2220 case 8:
2221 nextword |= 0x600;
2222 break;
2223 default:
2224 abort ();
2225 }
2226 /* IF its simple,
2227 GET US OUT OF HERE! */
2228
2229 /* Must be INDEX, with an index register. Address
2230 register cannot be ZERO-PC, and either :b was
2231 forced, or we know it will fit. For a 68000 or
2232 68010, force this mode anyways, because the
2233 larger modes aren't supported. */
2234 if (opP->mode == BASE
2235 && ((opP->reg >= ADDR0
2236 && opP->reg <= ADDR7)
2237 || opP->reg == PC))
2238 {
2239 if (siz1 == SIZE_BYTE
2240 || cpu_of_arch (current_architecture) < m68020
6da466c7 2241 || arch_coldfire_p (current_architecture)
252b5132
RH		 2242 || (siz1 == SIZE_UNSPEC
2243 && ! isvar (&opP->disp)
2244 && issbyte (baseo)))
2245 {
2246 nextword += baseo & 0xff;
2247 addword (nextword);
2248 if (isvar (&opP->disp))
2249 {
2250 /* Do a byte relocation. If it doesn't
2251 fit (possible on m68000) let the
2252 fixup processing complain later. */
2253 if (opP->reg == PC)
2254 add_fix ('B', &opP->disp, 1, 1);
2255 else
2256 add_fix ('B', &opP->disp, 0, 0);
2257 }
2258 else if (siz1 != SIZE_BYTE)
2259 {
2260 if (siz1 != SIZE_UNSPEC)
2261 as_warn (_("Forcing byte displacement"));
2262 if (! issbyte (baseo))
2263 opP->error = _("byte displacement out of range");
2264 }
2265
2266 break;
2267 }
2268 else if (siz1 == SIZE_UNSPEC
2269 && opP->reg == PC
2270 && isvar (&opP->disp)
2271 && subs (&opP->disp) == NULL
2272#ifdef OBJ_ELF
2273 /* If the displacement needs pic
2274 relocation it cannot be relaxed. */
2275 && opP->disp.pic_reloc == pic_none
2276#endif
2277 )
2278 {
2279 /* The code in md_convert_frag_1 needs to be
2280 able to adjust nextword. Call frag_grow
2281 to ensure that we have enough space in
2282 the frag obstack to make all the bytes
2283 contiguous. */
2284 frag_grow (14);
2285 nextword += baseo & 0xff;
2286 addword (nextword);
2287 add_frag (adds (&opP->disp), offs (&opP->disp),
2288 TAB (PCINDEX, SZ_UNDEF));
2289
2290 break;
2291 }
2292 }
2293 }
2294 else
2295 {
2296 nextword |= 0x40; /* No index reg */
2297 if (opP->index.reg >= ZDATA0
2298 && opP->index.reg <= ZDATA7)
2299 nextword |= (opP->index.reg - ZDATA0) << 12;
2300 else if (opP->index.reg >= ZADDR0
2301 || opP->index.reg <= ZADDR7)
2302 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2303 }
2304
2305 /* It isn't simple. */
2306
2307 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2308 || arch_coldfire_p (current_architecture))
252b5132
RH		 2309 opP->error =
2310 _("invalid operand mode for this architecture; needs 68020 or higher");
2311
2312 nextword |= 0x100;
2313 /* If the guy specified a width, we assume that it is
2314 wide enough. Maybe it isn't. If so, we lose. */
2315 switch (siz1)
2316 {
2317 case SIZE_UNSPEC:
2318 if (isvar (&opP->disp)
2319 ? m68k_rel32
2320 : ! issword (baseo))
2321 {
2322 siz1 = SIZE_LONG;
2323 nextword |= 0x30;
2324 }
2325 else if (! isvar (&opP->disp) && baseo == 0)
2326 nextword |= 0x10;
2327 else
2328 {
2329 nextword |= 0x20;
2330 siz1 = SIZE_WORD;
2331 }
2332 break;
2333 case SIZE_BYTE:
2334 as_warn (_(":b not permitted; defaulting to :w"));
2335 /* Fall through. */
2336 case SIZE_WORD:
2337 nextword |= 0x20;
2338 break;
2339 case SIZE_LONG:
2340 nextword |= 0x30;
2341 break;
2342 }
2343
2344 /* Figure out innner displacement stuff */
2345 if (opP->mode == POST || opP->mode == PRE)
2346 {
2347 if (cpu_of_arch (current_architecture) & cpu32)
2348 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2349 switch (siz2)
2350 {
2351 case SIZE_UNSPEC:
2352 if (isvar (&opP->odisp)
2353 ? m68k_rel32
2354 : ! issword (outro))
2355 {
2356 siz2 = SIZE_LONG;
2357 nextword |= 0x3;
2358 }
2359 else if (! isvar (&opP->odisp) && outro == 0)
2360 nextword |= 0x1;
2361 else
2362 {
2363 nextword |= 0x2;
2364 siz2 = SIZE_WORD;
2365 }
2366 break;
2367 case 1:
2368 as_warn (_(":b not permitted; defaulting to :w"));
2369 /* Fall through. */
2370 case 2:
2371 nextword |= 0x2;
2372 break;
2373 case 3:
2374 nextword |= 0x3;
2375 break;
2376 }
2377 if (opP->mode == POST
2378 && (nextword & 0x40) == 0)
2379 nextword |= 0x04;
2380 }
2381 addword (nextword);
2382
2383 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2384 {
2385 if (opP->reg == PC || opP->reg == ZPC)
2386 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2387 else
2388 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2389 }
2390 if (siz1 == SIZE_LONG)
2391 addword (baseo >> 16);
2392 if (siz1 != SIZE_UNSPEC)
2393 addword (baseo);
2394
2395 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2396 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2397 if (siz2 == SIZE_LONG)
2398 addword (outro >> 16);
2399 if (siz2 != SIZE_UNSPEC)
2400 addword (outro);
2401
2402 break;
2403
2404 case ABSL:
2405 nextword = get_num (&opP->disp, 80);
2406 switch (opP->disp.size)
2407 {
2408 default:
2409 abort ();
2410 case SIZE_UNSPEC:
2411 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2412 {
2413 tmpreg = 0x38; /* 7.0 */
2414 addword (nextword);
2415 break;
2416 }
252b5132
RH		 2417 if (isvar (&opP->disp)
2418 && !subs (&opP->disp)
2419 && adds (&opP->disp)
2420#ifdef OBJ_ELF
2421 /* If the displacement needs pic relocation it
2422 cannot be relaxed. */
2423 && opP->disp.pic_reloc == pic_none
2424#endif
252b5132
RH		 2425 && !flag_long_jumps
2426 && !strchr ("~%&$?", s[0]))
2427 {
2428 tmpreg = 0x3A; /* 7.2 */
2429 add_frag (adds (&opP->disp),
2430 offs (&opP->disp),
151337e8 2431 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2432 break;
2433 }
2434 /* Fall through into long */
2435 case SIZE_LONG:
2436 if (isvar (&opP->disp))
2437 add_fix ('l', &opP->disp, 0, 0);
2438
2439 tmpreg = 0x39;/* 7.1 mode */
2440 addword (nextword >> 16);
2441 addword (nextword);
2442 break;
2443
2444 case SIZE_BYTE:
2445 as_bad (_("unsupported byte value; use a different suffix"));
2446 /* Fall through. */
2447 case SIZE_WORD: /* Word */
2448 if (isvar (&opP->disp))
2449 add_fix ('w', &opP->disp, 0, 0);
2450
2451 tmpreg = 0x38;/* 7.0 mode */
2452 addword (nextword);
2453 break;
2454 }
2455 break;
2456 case CONTROL:
2457 case FPREG:
2458 default:
2459 as_bad (_("unknown/incorrect operand"));
bc805888 2460 /* abort (); */
252b5132
RH		 2461 }
2462 install_gen_operand (s[1], tmpreg);
2463 break;
2464
2465 case '#':
2466 case '^':
2467 switch (s[1])
2468 { /* JF: I hate floating point! */
2469 case 'j':
2470 tmpreg = 70;
2471 break;
2472 case '8':
2473 tmpreg = 20;
2474 break;
2475 case 'C':
2476 tmpreg = 50;
2477 break;
2478 case '3':
2479 default:
2480 tmpreg = 80;
2481 break;
2482 }
2483 tmpreg = get_num (&opP->disp, tmpreg);
2484 if (isvar (&opP->disp))
2485 add_fix (s[1], &opP->disp, 0, 0);
2486 switch (s[1])
2487 {
2488 case 'b': /* Danger: These do no check for
2489 certain types of overflow.
2490 user beware! */
2491 if (!isbyte (tmpreg))
2492 opP->error = _("out of range");
2493 insop (tmpreg, opcode);
2494 if (isvar (&opP->disp))
2495 the_ins.reloc[the_ins.nrel - 1].n =
2496 (opcode->m_codenum) * 2 + 1;
2497 break;
2498 case 'B':
2499 if (!issbyte (tmpreg))
2500 opP->error = _("out of range");
2501 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2502 if (isvar (&opP->disp))
2503 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2504 break;
2505 case 'w':
2506 if (!isword (tmpreg))
2507 opP->error = _("out of range");
2508 insop (tmpreg, opcode);
2509 if (isvar (&opP->disp))
2510 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2511 break;
2512 case 'W':
2513 if (!issword (tmpreg))
2514 opP->error = _("out of range");
2515 insop (tmpreg, opcode);
2516 if (isvar (&opP->disp))
2517 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2518 break;
2519 case 'l':
2520 /* Because of the way insop works, we put these two out
2521 backwards. */
2522 insop (tmpreg, opcode);
2523 insop (tmpreg >> 16, opcode);
2524 if (isvar (&opP->disp))
2525 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2526 break;
2527 case '3':
2528 tmpreg &= 0xFF;
2529 case '8':
2530 case 'C':
2531 case 'j':
2532 install_operand (s[1], tmpreg);
2533 break;
2534 default:
2535 abort ();
2536 }
2537 break;
2538
2539 case '+':
2540 case '-':
2541 case 'A':
2542 case 'a':
2543 install_operand (s[1], opP->reg - ADDR);
2544 break;
2545
2546 case 'B':
2547 tmpreg = get_num (&opP->disp, 80);
2548 switch (s[1])
2549 {
2550 case 'B':
8390138c 2551 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 2552 break;
2553 case 'W':
2554 add_fix ('w', &opP->disp, 1, 0);
2555 addword (0);
2556 break;
2557 case 'L':
2558 long_branch:
151337e8 2559 if (! HAVE_LONG_BRANCH (current_architecture))
81d4177b 2560 as_warn (_("Can't use long branches on 68000/68010/5200"));
151337e8 2561 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2562 add_fix ('l', &opP->disp, 1, 0);
2563 addword (0);
2564 addword (0);
2565 break;
2566 case 'g':
2567 if (subs (&opP->disp)) /* We can't relax it */
2568 goto long_branch;
2569
2570#ifdef OBJ_ELF
2571 /* If the displacement needs pic relocation it cannot be
2572 relaxed. */
2573 if (opP->disp.pic_reloc != pic_none)
2574 goto long_branch;
2575#endif
252b5132 2576 /* This could either be a symbol, or an absolute
151337e8
NC		 2577 address. If it's an absolute address, turn it into
2578 an absolute jump right here and keep it out of the
2579 relaxer. */
2580 if (adds (&opP->disp) == 0)
2581 {
2582 if (the_ins.opcode[0] == 0x6000) /* jbra */
2583 the_ins.opcode[0] = 0x4EF1;
2584 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2585 the_ins.opcode[0] = 0x4EB1;
2586 else /* jCC */
2587 {
2588 the_ins.opcode[0] ^= 0x0100;
2589 the_ins.opcode[0] |= 0x0006;
2590 addword (0x4EF1);
2591 }
2592 add_fix ('l', &opP->disp, 0, 0);
2593 addword (0);
2594 addword (0);
2595 break;
2596 }
2597
2598 /* Now we know it's going into the relaxer. Now figure
2599 out which mode. We try in this order of preference:
2600 long branch, absolute jump, byte/word branches only. */
2601 if (HAVE_LONG_BRANCH (current_architecture))
252b5132 2602 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8
NC		 2603 TAB (BRANCHBWL, SZ_UNDEF));
2604 else if (! flag_keep_pcrel)
2605 {
2606 if ((the_ins.opcode[0] == 0x6000)
2607 || (the_ins.opcode[0] == 0x6100))
2608 add_frag (adds (&opP->disp), offs (&opP->disp),
2609 TAB (BRABSJUNC, SZ_UNDEF));
2610 else
2611 add_frag (adds (&opP->disp), offs (&opP->disp),
2612 TAB (BRABSJCOND, SZ_UNDEF));
2613 }
252b5132
RH		 2614 else
2615 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8 2616 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 2617 break;
2618 case 'w':
2619 if (isvar (&opP->disp))
2620 {
151337e8
NC		 2621 /* Check for DBcc instructions. We can relax them,
2622 but only if we have long branches and/or absolute
2623 jumps. */
2624 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2625 && (HAVE_LONG_BRANCH (current_architecture)
2626 || (! flag_keep_pcrel)))
252b5132 2627 {
151337e8
NC		 2628 if (HAVE_LONG_BRANCH (current_architecture))
2629 add_frag (adds (&opP->disp), offs (&opP->disp),
2630 TAB (DBCCLBR, SZ_UNDEF));
2631 else
2632 add_frag (adds (&opP->disp), offs (&opP->disp),
2633 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 2634 break;
2635 }
252b5132
RH		 2636 add_fix ('w', &opP->disp, 1, 0);
2637 }
2638 addword (0);
2639 break;
2640 case 'C': /* Fixed size LONG coproc branches */
2641 add_fix ('l', &opP->disp, 1, 0);
2642 addword (0);
2643 addword (0);
2644 break;
2645 case 'c': /* Var size Coprocesssor branches */
151337e8 2646 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 2647 {
252b5132
RH		 2648 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2649 add_fix ('l', &opP->disp, 1, 0);
2650 addword (0);
2651 addword (0);
2652 }
151337e8
NC		 2653 else
2654 add_frag (adds (&opP->disp), offs (&opP->disp),
2655 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 2656 break;
2657 default:
2658 abort ();
2659 }
2660 break;
2661
2662 case 'C': /* Ignore it */
2663 break;
2664
2665 case 'd': /* JF this is a kludge */
2666 install_operand ('s', opP->reg - ADDR);
2667 tmpreg = get_num (&opP->disp, 80);
2668 if (!issword (tmpreg))
2669 {
2670 as_warn (_("Expression out of range, using 0"));
2671 tmpreg = 0;
2672 }
2673 addword (tmpreg);
2674 break;
2675
2676 case 'D':
2677 install_operand (s[1], opP->reg - DATA);
2678 break;
2679
6da466c7
ILT		 2680 case 'E': /* Ignore it */
2681 break;
2682
252b5132
RH		 2683 case 'F':
2684 install_operand (s[1], opP->reg - FP0);
2685 break;
2686
6da466c7
ILT		 2687 case 'G': /* Ignore it */
2688 case 'H':
2689 break;
2690
252b5132
RH		 2691 case 'I':
2692 tmpreg = opP->reg - COP0;
2693 install_operand (s[1], tmpreg);
2694 break;
2695
2696 case 'J': /* JF foo */
2697 switch (opP->reg)
2698 {
2699 case SFC:
2700 tmpreg = 0x000;
2701 break;
2702 case DFC:
2703 tmpreg = 0x001;
2704 break;
2705 case CACR:
2706 tmpreg = 0x002;
2707 break;
2708 case TC:
2709 tmpreg = 0x003;
2710 break;
2711 case ITT0:
2712 tmpreg = 0x004;
2713 break;
2714 case ITT1:
2715 tmpreg = 0x005;
2716 break;
2717 case DTT0:
2718 tmpreg = 0x006;
2719 break;
2720 case DTT1:
2721 tmpreg = 0x007;
2722 break;
2723 case BUSCR:
2724 tmpreg = 0x008;
2725 break;
2726
2727 case USP:
2728 tmpreg = 0x800;
2729 break;
2730 case VBR:
2731 tmpreg = 0x801;
2732 break;
2733 case CAAR:
2734 tmpreg = 0x802;
2735 break;
2736 case MSP:
2737 tmpreg = 0x803;
2738 break;
2739 case ISP:
2740 tmpreg = 0x804;
2741 break;
2742 case MMUSR:
2743 tmpreg = 0x805;
2744 break;
2745 case URP:
2746 tmpreg = 0x806;
2747 break;
2748 case SRP:
2749 tmpreg = 0x807;
2750 break;
2751 case PCR:
2752 tmpreg = 0x808;
2753 break;
2754 case ROMBAR:
2755 tmpreg = 0xC00;
2756 break;
2757 case RAMBAR0:
2758 tmpreg = 0xC04;
2759 break;
2760 case RAMBAR1:
2761 tmpreg = 0xC05;
2762 break;
2763 case MBAR:
2764 tmpreg = 0xC0F;
2765 break;
2766 default:
2767 abort ();
2768 }
2769 install_operand (s[1], tmpreg);
2770 break;
2771
2772 case 'k':
2773 tmpreg = get_num (&opP->disp, 55);
2774 install_operand (s[1], tmpreg & 0x7f);
2775 break;
2776
2777 case 'l':
2778 tmpreg = opP->mask;
2779 if (s[1] == 'w')
2780 {
2781 if (tmpreg & 0x7FF0000)
2782 as_bad (_("Floating point register in register list"));
2783 insop (reverse_16_bits (tmpreg), opcode);
2784 }
2785 else
2786 {
2787 if (tmpreg & 0x700FFFF)
2788 as_bad (_("Wrong register in floating-point reglist"));
2789 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2790 }
2791 break;
2792
2793 case 'L':
2794 tmpreg = opP->mask;
2795 if (s[1] == 'w')
2796 {
2797 if (tmpreg & 0x7FF0000)
2798 as_bad (_("Floating point register in register list"));
2799 insop (tmpreg, opcode);
2800 }
2801 else if (s[1] == '8')
2802 {
2803 if (tmpreg & 0x0FFFFFF)
2804 as_bad (_("incorrect register in reglist"));
2805 install_operand (s[1], tmpreg >> 24);
2806 }
2807 else
2808 {
2809 if (tmpreg & 0x700FFFF)
2810 as_bad (_("wrong register in floating-point reglist"));
2811 else
2812 install_operand (s[1], tmpreg >> 16);
2813 }
2814 break;
2815
2816 case 'M':
2817 install_operand (s[1], get_num (&opP->disp, 60));
2818 break;
2819
2820 case 'O':
2821 tmpreg = ((opP->mode == DREG)
8fce3f5e 2822 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 2823 : (get_num (&opP->disp, 40) & 0x1F));
2824 install_operand (s[1], tmpreg);
2825 break;
2826
2827 case 'Q':
2828 tmpreg = get_num (&opP->disp, 10);
2829 if (tmpreg == 8)
2830 tmpreg = 0;
2831 install_operand (s[1], tmpreg);
2832 break;
2833
2834 case 'R':
2835 /* This depends on the fact that ADDR registers are eight
2836 more than their corresponding DATA regs, so the result
2837 will have the ADDR_REG bit set */
2838 install_operand (s[1], opP->reg - DATA);
2839 break;
2840
2841 case 'r':
2842 if (opP->mode == AINDR)
2843 install_operand (s[1], opP->reg - DATA);
2844 else
2845 install_operand (s[1], opP->index.reg - DATA);
2846 break;
2847
2848 case 's':
2849 if (opP->reg == FPI)
2850 tmpreg = 0x1;
2851 else if (opP->reg == FPS)
2852 tmpreg = 0x2;
2853 else if (opP->reg == FPC)
2854 tmpreg = 0x4;
2855 else
2856 abort ();
2857 install_operand (s[1], tmpreg);
2858 break;
2859
2860 case 'S': /* Ignore it */
2861 break;
2862
2863 case 'T':
2864 install_operand (s[1], get_num (&opP->disp, 30));
2865 break;
2866
2867 case 'U': /* Ignore it */
2868 break;
2869
2870 case 'c':
2871 switch (opP->reg)
2872 {
2873 case NC:
2874 tmpreg = 0;
2875 break;
2876 case DC:
2877 tmpreg = 1;
2878 break;
2879 case IC:
2880 tmpreg = 2;
2881 break;
2882 case BC:
2883 tmpreg = 3;
2884 break;
2885 default:
2886 as_fatal (_("failed sanity check"));
2887 } /* switch on cache token */
2888 install_operand (s[1], tmpreg);
2889 break;
2890#ifndef NO_68851
92774660 2891 /* JF: These are out of order, I fear. */
252b5132
RH		 2892 case 'f':
2893 switch (opP->reg)
2894 {
2895 case SFC:
2896 tmpreg = 0;
2897 break;
2898 case DFC:
2899 tmpreg = 1;
2900 break;
2901 default:
2902 abort ();
2903 }
2904 install_operand (s[1], tmpreg);
2905 break;
2906
2907 case '0':
2908 case '1':
2909 case '2':
2910 switch (opP->reg)
2911 {
2912 case TC:
2913 tmpreg = 0;
2914 break;
2915 case CAL:
2916 tmpreg = 4;
2917 break;
2918 case VAL:
2919 tmpreg = 5;
2920 break;
2921 case SCC:
2922 tmpreg = 6;
2923 break;
2924 case AC:
2925 tmpreg = 7;
2926 break;
2927 default:
2928 abort ();
2929 }
2930 install_operand (s[1], tmpreg);
2931 break;
2932
2933 case 'V':
2934 if (opP->reg == VAL)
2935 break;
2936 abort ();
2937
2938 case 'W':
2939 switch (opP->reg)
2940 {
2941 case DRP:
2942 tmpreg = 1;
2943 break;
2944 case SRP:
2945 tmpreg = 2;
2946 break;
2947 case CRP:
2948 tmpreg = 3;
2949 break;
2950 default:
2951 abort ();
2952 }
2953 install_operand (s[1], tmpreg);
2954 break;
2955
2956 case 'X':
2957 switch (opP->reg)
2958 {
2959 case BAD:
2960 case BAD + 1:
2961 case BAD + 2:
2962 case BAD + 3:
2963 case BAD + 4:
2964 case BAD + 5:
2965 case BAD + 6:
2966 case BAD + 7:
2967 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2968 break;
2969
2970 case BAC:
2971 case BAC + 1:
2972 case BAC + 2:
2973 case BAC + 3:
2974 case BAC + 4:
2975 case BAC + 5:
2976 case BAC + 6:
2977 case BAC + 7:
2978 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2979 break;
2980
2981 default:
2982 abort ();
2983 }
2984 install_operand (s[1], tmpreg);
2985 break;
2986 case 'Y':
2987 know (opP->reg == PSR);
2988 break;
2989 case 'Z':
2990 know (opP->reg == PCSR);
2991 break;
2992#endif /* m68851 */
2993 case '3':
2994 switch (opP->reg)
2995 {
2996 case TT0:
2997 tmpreg = 2;
2998 break;
2999 case TT1:
3000 tmpreg = 3;
3001 break;
3002 default:
3003 abort ();
3004 }
3005 install_operand (s[1], tmpreg);
3006 break;
3007 case 't':
3008 tmpreg = get_num (&opP->disp, 20);
3009 install_operand (s[1], tmpreg);
3010 break;
3011 case '_': /* used only for move16 absolute 32-bit address */
3012 if (isvar (&opP->disp))
3013 add_fix ('l', &opP->disp, 0, 0);
3014 tmpreg = get_num (&opP->disp, 80);
3015 addword (tmpreg >> 16);
3016 addword (tmpreg & 0xFFFF);
3017 break;
6da466c7
ILT		 3018 case 'u':
3019 install_operand (s[1], opP->reg - DATA0L);
3020 opP->reg -= (DATA0L);
3021 opP->reg &= 0x0F; /* remove upper/lower bit */
3022 break;
252b5132
RH		 3023 default:
3024 abort ();
3025 }
3026 }
3027
3028 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3029 instruction, ready to be emitted. . . */
252b5132
RH		 3030}
3031
3032static int
3033reverse_16_bits (in)
3034 int in;
3035{
3036 int out = 0;
3037 int n;
3038
3039 static int mask[16] =
3040 {
3041 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3042 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3043 };
3044 for (n = 0; n < 16; n++)
3045 {
3046 if (in & mask[n])
3047 out |= mask[15 - n];
3048 }
3049 return out;
3050} /* reverse_16_bits() */
3051
3052static int
3053reverse_8_bits (in)
3054 int in;
3055{
3056 int out = 0;
3057 int n;
3058
3059 static int mask[8] =
3060 {
3061 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3062 };
3063
3064 for (n = 0; n < 8; n++)
3065 {
3066 if (in & mask[n])
3067 out |= mask[7 - n];
3068 }
3069 return out;
3070} /* reverse_8_bits() */
3071
3072/* Cause an extra frag to be generated here, inserting up to 10 bytes
3073 (that value is chosen in the frag_var call in md_assemble). TYPE
3074 is the subtype of the frag to be generated; its primary type is
3075 rs_machine_dependent.
3076
3077 The TYPE parameter is also used by md_convert_frag_1 and
3078 md_estimate_size_before_relax. The appropriate type of fixup will
3079 be emitted by md_convert_frag_1.
3080
3081 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3082static void
3083install_operand (mode, val)
3084 int mode;
3085 int val;
3086{
3087 switch (mode)
3088 {
3089 case 's':
3090 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3091 break;
3092 case 'd':
3093 the_ins.opcode[0] |= val << 9;
3094 break;
3095 case '1':
3096 the_ins.opcode[1] |= val << 12;
3097 break;
3098 case '2':
3099 the_ins.opcode[1] |= val << 6;
3100 break;
3101 case '3':
3102 the_ins.opcode[1] |= val;
3103 break;
3104 case '4':
3105 the_ins.opcode[2] |= val << 12;
3106 break;
3107 case '5':
3108 the_ins.opcode[2] |= val << 6;
3109 break;
3110 case '6':
3111 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3112 three words long! */
3113 the_ins.numo++;
3114 the_ins.opcode[2] |= val;
3115 break;
3116 case '7':
3117 the_ins.opcode[1] |= val << 7;
3118 break;
3119 case '8':
3120 the_ins.opcode[1] |= val << 10;
3121 break;
3122#ifndef NO_68851
3123 case '9':
3124 the_ins.opcode[1] |= val << 5;
3125 break;
3126#endif
3127
3128 case 't':
3129 the_ins.opcode[1] |= (val << 10) | (val << 7);
3130 break;
3131 case 'D':
3132 the_ins.opcode[1] |= (val << 12) | val;
3133 break;
3134 case 'g':
3135 the_ins.opcode[0] |= val = 0xff;
3136 break;
3137 case 'i':
3138 the_ins.opcode[0] |= val << 9;
3139 break;
3140 case 'C':
3141 the_ins.opcode[1] |= val;
3142 break;
3143 case 'j':
3144 the_ins.opcode[1] |= val;
3145 the_ins.numo++; /* What a hack */
3146 break;
3147 case 'k':
3148 the_ins.opcode[1] |= val << 4;
3149 break;
3150 case 'b':
3151 case 'w':
3152 case 'W':
3153 case 'l':
3154 break;
3155 case 'e':
3156 the_ins.opcode[0] |= (val << 6);
3157 break;
3158 case 'L':
3159 the_ins.opcode[1] = (val >> 16);
3160 the_ins.opcode[2] = val & 0xffff;
3161 break;
6da466c7
ILT		 3162 case 'm':
3163 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3164 the_ins.opcode[0] |= ((val & 0x7) << 9);
3165 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3166 break;
3167 case 'n':
3168 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3169 the_ins.opcode[0] |= ((val & 0x7) << 9);
3170 break;
3171 case 'o':
3172 the_ins.opcode[1] |= val << 12;
3173 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3174 break;
3175 case 'M':
3176 the_ins.opcode[0] |= (val & 0xF);
3177 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3178 break;
3179 case 'N':
3180 the_ins.opcode[1] |= (val & 0xF);
3181 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3182 break;
3183 case 'h':
3184 the_ins.opcode[1] |= ((val != 1) << 10);
3185 break;
252b5132
RH		 3186 case 'c':
3187 default:
3188 as_fatal (_("failed sanity check."));
3189 }
3190} /* install_operand() */
3191
3192static void
3193install_gen_operand (mode, val)
3194 int mode;
3195 int val;
3196{
3197 switch (mode)
3198 {
3199 case 's':
3200 the_ins.opcode[0] |= val;
3201 break;
3202 case 'd':
3203 /* This is a kludge!!! */
3204 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3205 break;
3206 case 'b':
3207 case 'w':
3208 case 'l':
3209 case 'f':
3210 case 'F':
3211 case 'x':
3212 case 'p':
3213 the_ins.opcode[0] |= val;
3214 break;
3215 /* more stuff goes here */
3216 default:
3217 as_fatal (_("failed sanity check."));
3218 }
3219} /* install_gen_operand() */
3220
3221/*
3222 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3223 * then deal with the bitfield hack.
3224 */
3225
3226static char *
3227crack_operand (str, opP)
3228 register char *str;
3229 register struct m68k_op *opP;
3230{
3231 register int parens;
3232 register int c;
3233 register char *beg_str;
3234 int inquote = 0;
3235
3236 if (!str)
3237 {
3238 return str;
3239 }
3240 beg_str = str;
3241 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3242 {
3243 if (! inquote)
3244 {
3245 if (*str == '(')
3246 parens++;
3247 else if (*str == ')')
3248 {
3249 if (!parens)
3250 { /* ERROR */
3251 opP->error = _("Extra )");
3252 return str;
3253 }
3254 --parens;
3255 }
3256 }
3257 if (flag_mri && *str == '\'')
3258 inquote = ! inquote;
3259 }
3260 if (!*str && parens)
3261 { /* ERROR */
3262 opP->error = _("Missing )");
3263 return str;
3264 }
3265 c = *str;
3266 *str = '\0';
3267 if (m68k_ip_op (beg_str, opP) != 0)
3268 {
3269 *str = c;
3270 return str;
3271 }
3272 *str = c;
3273 if (c == '}')
3274 c = *++str; /* JF bitfield hack */
3275 if (c)
3276 {
3277 c = *++str;
3278 if (!c)
3279 as_bad (_("Missing operand"));
3280 }
3281
3282 /* Detect MRI REG symbols and convert them to REGLSTs. */
3283 if (opP->mode == CONTROL && (int)opP->reg < 0)
3284 {
3285 opP->mode = REGLST;
3286 opP->mask = ~(int)opP->reg;
3287 opP->reg = 0;
3288 }
3289
3290 return str;
3291}
3292
3293/* This is the guts of the machine-dependent assembler. STR points to a
3294 machine dependent instruction. This function is supposed to emit
3295 the frags/bytes it assembles to.
3296 */
3297
3298static void
3299insert_reg (regname, regnum)
3300 const char *regname;
3301 int regnum;
3302{
3303 char buf[100];
3304 int i;
3305
3306#ifdef REGISTER_PREFIX
3307 if (!flag_reg_prefix_optional)
3308 {
3309 buf[0] = REGISTER_PREFIX;
3310 strcpy (buf + 1, regname);
3311 regname = buf;
3312 }
3313#endif
3314
3315 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3316 &zero_address_frag));
3317
3318 for (i = 0; regname[i]; i++)
3319 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3320 buf[i] = '\0';
3321
3322 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3323 &zero_address_frag));
3324}
3325
3326struct init_entry
3327 {
3328 const char *name;
3329 int number;
3330 };
3331
3332static const struct init_entry init_table[] =
3333{
3334 { "d0", DATA0 },
3335 { "d1", DATA1 },
3336 { "d2", DATA2 },
3337 { "d3", DATA3 },
3338 { "d4", DATA4 },
3339 { "d5", DATA5 },
3340 { "d6", DATA6 },
3341 { "d7", DATA7 },
3342 { "a0", ADDR0 },
3343 { "a1", ADDR1 },
3344 { "a2", ADDR2 },
3345 { "a3", ADDR3 },
3346 { "a4", ADDR4 },
3347 { "a5", ADDR5 },
3348 { "a6", ADDR6 },
3349 { "fp", ADDR6 },
3350 { "a7", ADDR7 },
3351 { "sp", ADDR7 },
3352 { "ssp", ADDR7 },
3353 { "fp0", FP0 },
3354 { "fp1", FP1 },
3355 { "fp2", FP2 },
3356 { "fp3", FP3 },
3357 { "fp4", FP4 },
3358 { "fp5", FP5 },
3359 { "fp6", FP6 },
3360 { "fp7", FP7 },
3361 { "fpi", FPI },
3362 { "fpiar", FPI },
3363 { "fpc", FPI },
3364 { "fps", FPS },
3365 { "fpsr", FPS },
3366 { "fpc", FPC },
3367 { "fpcr", FPC },
3368 { "control", FPC },
3369 { "status", FPS },
3370 { "iaddr", FPI },
3371
3372 { "cop0", COP0 },
3373 { "cop1", COP1 },
3374 { "cop2", COP2 },
3375 { "cop3", COP3 },
3376 { "cop4", COP4 },
3377 { "cop5", COP5 },
3378 { "cop6", COP6 },
3379 { "cop7", COP7 },
3380 { "pc", PC },
3381 { "zpc", ZPC },
3382 { "sr", SR },
3383
3384 { "ccr", CCR },
3385 { "cc", CCR },
3386
6da466c7
ILT		 3387 { "acc", ACC },
3388 { "macsr", MACSR },
3389 { "mask", MASK },
3390
252b5132
RH		 3391 /* control registers */
3392 { "sfc", SFC }, /* Source Function Code */
3393 { "sfcr", SFC },
3394 { "dfc", DFC }, /* Destination Function Code */
3395 { "dfcr", DFC },
3396 { "cacr", CACR }, /* Cache Control Register */
3397 { "caar", CAAR }, /* Cache Address Register */
3398
3399 { "usp", USP }, /* User Stack Pointer */
3400 { "vbr", VBR }, /* Vector Base Register */
3401 { "msp", MSP }, /* Master Stack Pointer */
3402 { "isp", ISP }, /* Interrupt Stack Pointer */
3403
3404 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3405 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3406 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3407 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3408
3409 /* 68ec040 versions of same */
3410 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3411 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3412 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3413 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3414
3415 /* mcf5200 versions of same. The ColdFire programmer's reference
3416 manual indicated that the order is 2,3,0,1, but Ken Rose
3417 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3418 { "acr0", ITT0 }, /* Access Control Unit 0 */
3419 { "acr1", ITT1 }, /* Access Control Unit 1 */
3420 { "acr2", DTT0 }, /* Access Control Unit 2 */
3421 { "acr3", DTT1 }, /* Access Control Unit 3 */
3422
3423 { "tc", TC }, /* MMU Translation Control Register */
3424 { "tcr", TC },
3425
3426 { "mmusr", MMUSR }, /* MMU Status Register */
3427 { "srp", SRP }, /* User Root Pointer */
3428 { "urp", URP }, /* Supervisor Root Pointer */
3429
3430 { "buscr", BUSCR },
3431 { "pcr", PCR },
3432
3433 { "rombar", ROMBAR }, /* ROM Base Address Register */
3434 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3435 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3436 { "mbar", MBAR }, /* Module Base Address Register */
3437 /* end of control registers */
3438
3439 { "ac", AC },
3440 { "bc", BC },
3441 { "cal", CAL },
3442 { "crp", CRP },
3443 { "drp", DRP },
3444 { "pcsr", PCSR },
3445 { "psr", PSR },
3446 { "scc", SCC },
3447 { "val", VAL },
3448 { "bad0", BAD0 },
3449 { "bad1", BAD1 },
3450 { "bad2", BAD2 },
3451 { "bad3", BAD3 },
3452 { "bad4", BAD4 },
3453 { "bad5", BAD5 },
3454 { "bad6", BAD6 },
3455 { "bad7", BAD7 },
3456 { "bac0", BAC0 },
3457 { "bac1", BAC1 },
3458 { "bac2", BAC2 },
3459 { "bac3", BAC3 },
3460 { "bac4", BAC4 },
3461 { "bac5", BAC5 },
3462 { "bac6", BAC6 },
3463 { "bac7", BAC7 },
3464
3465 { "ic", IC },
3466 { "dc", DC },
3467 { "nc", NC },
3468
3469 { "tt0", TT0 },
3470 { "tt1", TT1 },
3471 /* 68ec030 versions of same */
3472 { "ac0", TT0 },
3473 { "ac1", TT1 },
3474 /* 68ec030 access control unit, identical to 030 MMU status reg */
3475 { "acusr", PSR },
3476
3477 /* Suppressed data and address registers. */
3478 { "zd0", ZDATA0 },
3479 { "zd1", ZDATA1 },
3480 { "zd2", ZDATA2 },
3481 { "zd3", ZDATA3 },
3482 { "zd4", ZDATA4 },
3483 { "zd5", ZDATA5 },
3484 { "zd6", ZDATA6 },
3485 { "zd7", ZDATA7 },
3486 { "za0", ZADDR0 },
3487 { "za1", ZADDR1 },
3488 { "za2", ZADDR2 },
3489 { "za3", ZADDR3 },
3490 { "za4", ZADDR4 },
3491 { "za5", ZADDR5 },
3492 { "za6", ZADDR6 },
3493 { "za7", ZADDR7 },
3494
92774660 3495 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 3496 { "d0l", DATA0L },
3497 { "d1l", DATA1L },
3498 { "d2l", DATA2L },
3499 { "d3l", DATA3L },
3500 { "d4l", DATA4L },
3501 { "d5l", DATA5L },
3502 { "d6l", DATA6L },
3503 { "d7l", DATA7L },
3504
3505 { "a0l", ADDR0L },
3506 { "a1l", ADDR1L },
3507 { "a2l", ADDR2L },
3508 { "a3l", ADDR3L },
3509 { "a4l", ADDR4L },
3510 { "a5l", ADDR5L },
3511 { "a6l", ADDR6L },
3512 { "a7l", ADDR7L },
3513
3514 { "d0u", DATA0U },
3515 { "d1u", DATA1U },
3516 { "d2u", DATA2U },
3517 { "d3u", DATA3U },
3518 { "d4u", DATA4U },
3519 { "d5u", DATA5U },
3520 { "d6u", DATA6U },
3521 { "d7u", DATA7U },
3522
3523 { "a0u", ADDR0U },
3524 { "a1u", ADDR1U },
3525 { "a2u", ADDR2U },
3526 { "a3u", ADDR3U },
3527 { "a4u", ADDR4U },
3528 { "a5u", ADDR5U },
3529 { "a6u", ADDR6U },
3530 { "a7u", ADDR7U },
3531
252b5132
RH		 3532 { 0, 0 }
3533};
3534
3535static void
3536init_regtable ()
3537{
3538 int i;
3539 for (i = 0; init_table[i].name; i++)
3540 insert_reg (init_table[i].name, init_table[i].number);
3541}
3542
3543static int no_68851, no_68881;
3544
3545#ifdef OBJ_AOUT
3546/* a.out machine type. Default to 68020. */
3547int m68k_aout_machtype = 2;
3548#endif
3549
3550void
3551md_assemble (str)
3552 char *str;
3553{
3554 const char *er;
3555 short *fromP;
3556 char *toP = NULL;
3557 int m, n = 0;
3558 char *to_beg_P;
3559 int shorts_this_frag;
3560 fixS *fixP;
3561
3562 /* In MRI mode, the instruction and operands are separated by a
3563 space. Anything following the operands is a comment. The label
3564 has already been removed. */
3565 if (flag_mri)
3566 {
3567 char *s;
3568 int fields = 0;
3569 int infield = 0;
3570 int inquote = 0;
3571
3572 for (s = str; *s != '\0'; s++)
3573 {
3574 if ((*s == ' ' || *s == '\t') && ! inquote)
3575 {
3576 if (infield)
3577 {
3578 ++fields;
3579 if (fields >= 2)
3580 {
3581 *s = '\0';
3582 break;
3583 }
3584 infield = 0;
3585 }
3586 }
3587 else
3588 {
3589 if (! infield)
3590 infield = 1;
3591 if (*s == '\'')
3592 inquote = ! inquote;
3593 }
3594 }
3595 }
3596
3597 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3598 m68k_ip (str);
3599 er = the_ins.error;
3600 if (!er)
3601 {
3602 for (n = 0; n < the_ins.numargs; n++)
3603 if (the_ins.operands[n].error)
3604 {
3605 er = the_ins.operands[n].error;
3606 break;
3607 }
3608 }
3609 if (er)
3610 {
3611 as_bad (_("%s -- statement `%s' ignored"), er, str);
3612 return;
3613 }
3614
3615 /* If there is a current label, record that it marks an instruction. */
3616 if (current_label != NULL)
3617 {
3618 current_label->text = 1;
3619 current_label = NULL;
3620 }
3621
f27a3839
AS		 3622#ifdef OBJ_ELF
3623 /* Tie dwarf2 debug info to the address at the start of the insn. */
3624 dwarf2_emit_insn (0);
3625#endif
3626
252b5132
RH		 3627 if (the_ins.nfrag == 0)
3628 {
3629 /* No frag hacking involved; just put it out */
3630 toP = frag_more (2 * the_ins.numo);
3631 fromP = &the_ins.opcode[0];
3632 for (m = the_ins.numo; m; --m)
3633 {
3634 md_number_to_chars (toP, (long) (*fromP), 2);
3635 toP += 2;
3636 fromP++;
3637 }
3638 /* put out symbol-dependent info */
3639 for (m = 0; m < the_ins.nrel; m++)
3640 {
3641 switch (the_ins.reloc[m].wid)
3642 {
3643 case 'B':
3644 n = 1;
3645 break;
3646 case 'b':
3647 n = 1;
3648 break;
3649 case '3':
3650 n = 1;
3651 break;
3652 case 'w':
3653 case 'W':
3654 n = 2;
3655 break;
3656 case 'l':
3657 n = 4;
3658 break;
3659 default:
3660 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3661 the_ins.reloc[m].wid);
3662 }
3663
3664 fixP = fix_new_exp (frag_now,
3665 ((toP - frag_now->fr_literal)
3666 - the_ins.numo * 2 + the_ins.reloc[m].n),
3667 n,
3668 &the_ins.reloc[m].exp,
3669 the_ins.reloc[m].pcrel,
3670 get_reloc_code (n, the_ins.reloc[m].pcrel,
3671 the_ins.reloc[m].pic_reloc));
3672 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3673 if (the_ins.reloc[m].wid == 'B')
3674 fixP->fx_signed = 1;
3675 }
3676 return;
3677 }
3678
3679 /* There's some frag hacking */
fbe572f9
AM		 3680 {
3681 /* Calculate the max frag size. */
3682 int wid;
3683
3684 wid = 2 * the_ins.fragb[0].fragoff;
3685 for (n = 1; n < the_ins.nfrag; n++)
3686 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3687 /* frag_var part. */
3688 wid += 10;
3689 /* Make sure the whole insn fits in one chunk, in particular that
3690 the var part is attached, as we access one byte before the
3691 variable frag for byte branches. */
3692 frag_grow (wid);
3693 }
3694
252b5132
RH		 3695 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3696 {
3697 int wid;
3698
3699 if (n == 0)
3700 wid = 2 * the_ins.fragb[n].fragoff;
3701 else
3702 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3703 toP = frag_more (wid);
3704 to_beg_P = toP;
3705 shorts_this_frag = 0;
3706 for (m = wid / 2; m; --m)
3707 {
3708 md_number_to_chars (toP, (long) (*fromP), 2);
3709 toP += 2;
3710 fromP++;
3711 shorts_this_frag++;
3712 }
3713 for (m = 0; m < the_ins.nrel; m++)
3714 {
3715 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3716 {
3717 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3718 break;
3719 }
3720 wid = the_ins.reloc[m].wid;
3721 if (wid == 0)
3722 continue;
3723 the_ins.reloc[m].wid = 0;
3724 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3725
3726 fixP = fix_new_exp (frag_now,
3727 ((toP - frag_now->fr_literal)
3728 - the_ins.numo * 2 + the_ins.reloc[m].n),
3729 wid,
3730 &the_ins.reloc[m].exp,
3731 the_ins.reloc[m].pcrel,
3732 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3733 the_ins.reloc[m].pic_reloc));
3734 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3735 }
3736 (void) frag_var (rs_machine_dependent, 10, 0,
3737 (relax_substateT) (the_ins.fragb[n].fragty),
3738 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3739 }
3740 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3741 shorts_this_frag = 0;
3742 if (n)
3743 {
3744 toP = frag_more (n * sizeof (short));
3745 while (n--)
3746 {
3747 md_number_to_chars (toP, (long) (*fromP), 2);
3748 toP += 2;
3749 fromP++;
3750 shorts_this_frag++;
3751 }
3752 }
3753 for (m = 0; m < the_ins.nrel; m++)
3754 {
3755 int wid;
3756
3757 wid = the_ins.reloc[m].wid;
3758 if (wid == 0)
3759 continue;
3760 the_ins.reloc[m].wid = 0;
3761 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3762
3763 fixP = fix_new_exp (frag_now,
3764 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3765 - shorts_this_frag * 2),
3766 wid,
3767 &the_ins.reloc[m].exp,
3768 the_ins.reloc[m].pcrel,
3769 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3770 the_ins.reloc[m].pic_reloc));
3771 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3772 }
3773}
3774
3775void
3776md_begin ()
3777{
3778 /*
3779 * md_begin -- set up hash tables with 68000 instructions.
3780 * similar to what the vax assembler does. ---phr
3781 */
3782 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3783 a copy of it at runtime, adding in the information we want but isn't
3784 there. I think it'd be better to have an awk script hack the table
3785 at compile time. Or even just xstr the table and use it as-is. But
3786 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3787 names. */
3788
3789 register const struct m68k_opcode *ins;
3790 register struct m68k_incant *hack, *slak;
3791 register const char *retval = 0; /* empty string, or error msg text */
8fce3f5e 3792 register int i;
252b5132
RH		 3793 register char c;
3794
3795 if (flag_mri)
3796 {
3797 flag_reg_prefix_optional = 1;
3798 m68k_abspcadd = 1;
3799 if (! m68k_rel32_from_cmdline)
3800 m68k_rel32 = 0;
3801 }
3802
3803 op_hash = hash_new ();
3804
3805 obstack_begin (&robyn, 4000);
3806 for (i = 0; i < m68k_numopcodes; i++)
3807 {
3808 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3809 do
3810 {
3811 ins = &m68k_opcodes[i];
3812 /* We *could* ignore insns that don't match our arch here
92774660 3813 but just leaving them out of the hash. */
252b5132
RH		 3814 slak->m_operands = ins->args;
3815 slak->m_opnum = strlen (slak->m_operands) / 2;
3816 slak->m_arch = ins->arch;
3817 slak->m_opcode = ins->opcode;
3818 /* This is kludgey */
3819 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3820 if (i + 1 != m68k_numopcodes
3821 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3822 {
3823 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3824 i++;
3825 }
3826 else
3827 slak->m_next = 0;
3828 slak = slak->m_next;
3829 }
3830 while (slak);
3831
3832 retval = hash_insert (op_hash, ins->name, (char *) hack);
3833 if (retval)
3834 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3835 }
3836
3837 for (i = 0; i < m68k_numaliases; i++)
3838 {
3839 const char *name = m68k_opcode_aliases[i].primary;
3840 const char *alias = m68k_opcode_aliases[i].alias;
3841 PTR val = hash_find (op_hash, name);
3842 if (!val)
3843 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3844 retval = hash_insert (op_hash, alias, val);
3845 if (retval)
3846 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3847 }
3848
3849 /* In MRI mode, all unsized branches are variable sized. Normally,
3850 they are word sized. */
3851 if (flag_mri)
3852 {
3853 static struct m68k_opcode_alias mri_aliases[] =
3854 {
3855 { "bhi", "jhi", },
3856 { "bls", "jls", },
3857 { "bcc", "jcc", },
3858 { "bcs", "jcs", },
3859 { "bne", "jne", },
3860 { "beq", "jeq", },
3861 { "bvc", "jvc", },
3862 { "bvs", "jvs", },
3863 { "bpl", "jpl", },
3864 { "bmi", "jmi", },
3865 { "bge", "jge", },
3866 { "blt", "jlt", },
3867 { "bgt", "jgt", },
3868 { "ble", "jle", },
3869 { "bra", "jra", },
3870 { "bsr", "jbsr", },
3871 };
3872
8fce3f5e
AM		 3873 for (i = 0;
3874 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
3875 i++)
252b5132
RH		 3876 {
3877 const char *name = mri_aliases[i].primary;
3878 const char *alias = mri_aliases[i].alias;
3879 PTR val = hash_find (op_hash, name);
3880 if (!val)
3881 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3882 retval = hash_jam (op_hash, alias, val);
3883 if (retval)
3884 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3885 }
3886 }
3887
8fce3f5e 3888 for (i = 0; i < (int) sizeof (mklower_table); i++)
252b5132
RH		 3889 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3890
8fce3f5e 3891 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 3892 {
3893 notend_table[i] = 0;
3894 alt_notend_table[i] = 0;
3895 }
3896 notend_table[','] = 1;
3897 notend_table['{'] = 1;
3898 notend_table['}'] = 1;
3899 alt_notend_table['a'] = 1;
3900 alt_notend_table['A'] = 1;
3901 alt_notend_table['d'] = 1;
3902 alt_notend_table['D'] = 1;
3903 alt_notend_table['#'] = 1;
3904 alt_notend_table['&'] = 1;
3905 alt_notend_table['f'] = 1;
3906 alt_notend_table['F'] = 1;
3907#ifdef REGISTER_PREFIX
3908 alt_notend_table[REGISTER_PREFIX] = 1;
3909#endif
3910
3911 /* We need to put '(' in alt_notend_table to handle
3912 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3913 */
3914 alt_notend_table['('] = 1;
3915
3916 /* We need to put '@' in alt_notend_table to handle
3917 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3918 */
3919 alt_notend_table['@'] = 1;
3920
3921 /* We need to put digits in alt_notend_table to handle
3922 bfextu %d0{24:1},%d0
3923 */
3924 alt_notend_table['0'] = 1;
3925 alt_notend_table['1'] = 1;
3926 alt_notend_table['2'] = 1;
3927 alt_notend_table['3'] = 1;
3928 alt_notend_table['4'] = 1;
3929 alt_notend_table['5'] = 1;
3930 alt_notend_table['6'] = 1;
3931 alt_notend_table['7'] = 1;
3932 alt_notend_table['8'] = 1;
3933 alt_notend_table['9'] = 1;
3934
3935#ifndef MIT_SYNTAX_ONLY
3936 /* Insert pseudo ops, these have to go into the opcode table since
3937 gas expects pseudo ops to start with a dot */
3938 {
3939 int n = 0;
3940 while (mote_pseudo_table[n].poc_name)
3941 {
3942 hack = (struct m68k_incant *)
3943 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3944 hash_insert (op_hash,
3945 mote_pseudo_table[n].poc_name, (char *) hack);
3946 hack->m_operands = 0;
3947 hack->m_opnum = n;
3948 n++;
3949 }
3950 }
3951#endif
3952
3953 init_regtable ();
3954
3955#ifdef OBJ_ELF
3956 record_alignment (text_section, 2);
3957 record_alignment (data_section, 2);
3958 record_alignment (bss_section, 2);
3959#endif
3960}
3961
3962static void
3963select_control_regs ()
3964{
3965 /* Note which set of "movec" control registers is available. */
3966 switch (cpu_of_arch (current_architecture))
3967 {
3968 case m68000:
3969 control_regs = m68000_control_regs;
3970 break;
3971 case m68010:
3972 control_regs = m68010_control_regs;
3973 break;
3974 case m68020:
3975 case m68030:
3976 control_regs = m68020_control_regs;
3977 break;
3978 case m68040:
3979 control_regs = m68040_control_regs;
3980 break;
3981 case m68060:
3982 control_regs = m68060_control_regs;
3983 break;
3984 case cpu32:
3985 control_regs = cpu32_control_regs;
3986 break;
3987 case mcf5200:
6da466c7
ILT		 3988 case mcf5206e:
3989 case mcf5307:
dc84e067 3990 case mcf5407:
6da466c7 3991 control_regs = mcf_control_regs;
252b5132
RH		 3992 break;
3993 default:
3994 abort ();
3995 }
3996}
3997
3998void
3999m68k_init_after_args ()
4000{
4001 if (cpu_of_arch (current_architecture) == 0)
4002 {
4003 int i;
4004 const char *default_cpu = TARGET_CPU;
4005
4006 if (*default_cpu == 'm')
4007 default_cpu++;
4008 for (i = 0; i < n_archs; i++)
4009 if (strcasecmp (default_cpu, archs[i].name) == 0)
4010 break;
4011 if (i == n_archs)
4012 {
4013 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
4014 current_architecture |= m68020;
4015 }
4016 else
4017 current_architecture |= archs[i].arch;
4018 }
4019 /* Permit m68881 specification with all cpus; those that can't work
4020 with a coprocessor could be doing emulation. */
4021 if (current_architecture & m68851)
4022 {
4023 if (current_architecture & m68040)
4024 {
4025 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4026 }
4027 }
4028 /* What other incompatibilities could we check for? */
4029
4030 /* Toss in some default assumptions about coprocessors. */
4031 if (!no_68881
4032 && (cpu_of_arch (current_architecture)
4033 /* Can CPU32 have a 68881 coprocessor?? */
4034 & (m68020 | m68030 | cpu32)))
4035 {
4036 current_architecture |= m68881;
4037 }
4038 if (!no_68851
4039 && (cpu_of_arch (current_architecture) & m68020up) != 0
4040 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4041 {
4042 current_architecture |= m68851;
4043 }
4044 if (no_68881 && (current_architecture & m68881))
4045 as_bad (_("options for 68881 and no-68881 both given"));
4046 if (no_68851 && (current_architecture & m68851))
4047 as_bad (_("options for 68851 and no-68851 both given"));
4048
4049#ifdef OBJ_AOUT
4050 /* Work out the magic number. This isn't very general. */
4051 if (current_architecture & m68000)
4052 m68k_aout_machtype = 0;
4053 else if (current_architecture & m68010)
4054 m68k_aout_machtype = 1;
4055 else if (current_architecture & m68020)
4056 m68k_aout_machtype = 2;
4057 else
4058 m68k_aout_machtype = 2;
4059#endif
4060
4061 /* Note which set of "movec" control registers is available. */
4062 select_control_regs ();
4063
4064 if (cpu_of_arch (current_architecture) < m68020
6da466c7 4065 || arch_coldfire_p (current_architecture))
252b5132
RH		 4066 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4067}
4068\f
4069/* This is called when a label is defined. */
4070
4071void
4072m68k_frob_label (sym)
4073 symbolS *sym;
4074{
4075 struct label_line *n;
4076
4077 n = (struct label_line *) xmalloc (sizeof *n);
4078 n->next = labels;
4079 n->label = sym;
4080 as_where (&n->file, &n->line);
4081 n->text = 0;
4082 labels = n;
4083 current_label = n;
4084}
4085
4086/* This is called when a value that is not an instruction is emitted. */
4087
4088void
4089m68k_flush_pending_output ()
4090{
4091 current_label = NULL;
4092}
4093
4094/* This is called at the end of the assembly, when the final value of
4095 the label is known. We warn if this is a text symbol aligned at an
4096 odd location. */
4097
4098void
4099m68k_frob_symbol (sym)
4100 symbolS *sym;
4101{
4102 if (S_GET_SEGMENT (sym) == reg_section
4103 && (int) S_GET_VALUE (sym) < 0)
4104 {
4105 S_SET_SEGMENT (sym, absolute_section);
4106 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4107 }
4108 else if ((S_GET_VALUE (sym) & 1) != 0)
4109 {
4110 struct label_line *l;
4111
4112 for (l = labels; l != NULL; l = l->next)
4113 {
4114 if (l->label == sym)
4115 {
4116 if (l->text)
4117 as_warn_where (l->file, l->line,
4118 _("text label `%s' aligned to odd boundary"),
4119 S_GET_NAME (sym));
4120 break;
4121 }
4122 }
4123 }
4124}
4125\f
4126/* This is called if we go in or out of MRI mode because of the .mri
4127 pseudo-op. */
4128
4129void
4130m68k_mri_mode_change (on)
4131 int on;
4132{
4133 if (on)
4134 {
4135 if (! flag_reg_prefix_optional)
4136 {
4137 flag_reg_prefix_optional = 1;
4138#ifdef REGISTER_PREFIX
4139 init_regtable ();
4140#endif
4141 }
4142 m68k_abspcadd = 1;
4143 if (! m68k_rel32_from_cmdline)
4144 m68k_rel32 = 0;
4145 }
4146 else
4147 {
4148 if (! reg_prefix_optional_seen)
4149 {
4150#ifdef REGISTER_PREFIX_OPTIONAL
4151 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4152#else
4153 flag_reg_prefix_optional = 0;
4154#endif
4155#ifdef REGISTER_PREFIX
4156 init_regtable ();
4157#endif
4158 }
4159 m68k_abspcadd = 0;
4160 if (! m68k_rel32_from_cmdline)
4161 m68k_rel32 = 1;
4162 }
4163}
4164
4165/* Equal to MAX_PRECISION in atof-ieee.c */
4166#define MAX_LITTLENUMS 6
4167
4168/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4169 of type TYPE, and store the appropriate bytes in *LITP. The number
4170 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4171 returned, or NULL on OK. */
4172
4173char *
4174md_atof (type, litP, sizeP)
4175 char type;
4176 char *litP;
4177 int *sizeP;
4178{
4179 int prec;
4180 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4181 LITTLENUM_TYPE *wordP;
4182 char *t;
4183
4184 switch (type)
4185 {
4186 case 'f':
4187 case 'F':
4188 case 's':
4189 case 'S':
4190 prec = 2;
4191 break;
4192
4193 case 'd':
4194 case 'D':
4195 case 'r':
4196 case 'R':
4197 prec = 4;
4198 break;
4199
4200 case 'x':
4201 case 'X':
4202 prec = 6;
4203 break;
4204
4205 case 'p':
4206 case 'P':
4207 prec = 6;
4208 break;
4209
4210 default:
4211 *sizeP = 0;
4212 return _("Bad call to MD_ATOF()");
4213 }
4214 t = atof_ieee (input_line_pointer, type, words);
4215 if (t)
4216 input_line_pointer = t;
4217
4218 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4219 for (wordP = words; prec--;)
4220 {
4221 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4222 litP += sizeof (LITTLENUM_TYPE);
4223 }
4224 return 0;
4225}
4226
4227void
4228md_number_to_chars (buf, val, n)
4229 char *buf;
4230 valueT val;
4231 int n;
4232{
4233 number_to_chars_bigendian (buf, val, n);
4234}
4235
4236static void
4237md_apply_fix_2 (fixP, val)
4238 fixS *fixP;
4239 offsetT val;
4240{
4241 addressT upper_limit;
4242 offsetT lower_limit;
4243
4244 /* This is unnecessary but it convinces the native rs6000 compiler
4245 to generate the code we want. */
4246 char *buf = fixP->fx_frag->fr_literal;
4247 buf += fixP->fx_where;
4248 /* end ibm compiler workaround */
4249
c801568a 4250 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
252b5132
RH		 4251
4252#ifdef OBJ_ELF
4253 if (fixP->fx_addsy)
4254 {
4255 memset (buf, 0, fixP->fx_size);
4256 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4257
4258 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4259 && !S_IS_DEFINED (fixP->fx_addsy)
4260 && !S_IS_WEAK (fixP->fx_addsy))
4261 S_SET_WEAK (fixP->fx_addsy);
4262 return;
4263 }
4264#endif
4265
4266#ifdef BFD_ASSEMBLER
4267 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4268 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4269 return;
4270#endif
4271
4272 switch (fixP->fx_size)
4273 {
4274 /* The cast to offsetT below are necessary to make code correct for
4275 machines where ints are smaller than offsetT */
4276 case 1:
4277 *buf++ = val;
4278 upper_limit = 0x7f;
4279 lower_limit = - (offsetT) 0x80;
4280 break;
4281 case 2:
4282 *buf++ = (val >> 8);
4283 *buf++ = val;
4284 upper_limit = 0x7fff;
4285 lower_limit = - (offsetT) 0x8000;
4286 break;
4287 case 4:
4288 *buf++ = (val >> 24);
4289 *buf++ = (val >> 16);
4290 *buf++ = (val >> 8);
4291 *buf++ = val;
4292 upper_limit = 0x7fffffff;
4293 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4294 break;
4295 default:
4296 BAD_CASE (fixP->fx_size);
4297 }
4298
4299 /* Fix up a negative reloc. */
4300 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4301 {
4302 fixP->fx_addsy = fixP->fx_subsy;
4303 fixP->fx_subsy = NULL;
4304 fixP->fx_tcbit = 1;
4305 }
4306
4307 /* For non-pc-relative values, it's conceivable we might get something
4308 like "0xff" for a byte field. So extend the upper part of the range
4309 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4310 so that we can do any range checking at all. */
4311 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4312 upper_limit = upper_limit * 2 + 1;
4313
4314 if ((addressT) val > upper_limit
4315 && (val > 0 || val < lower_limit))
4316 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4317
4318 /* A one byte PC-relative reloc means a short branch. We can't use
4319 a short branch with a value of 0 or -1, because those indicate
4320 different opcodes (branches with longer offsets). fixup_segment
4321 in write.c may have clobbered fx_pcrel, so we need to examine the
4322 reloc type. */
4323 if ((fixP->fx_pcrel
4324#ifdef BFD_ASSEMBLER
4325 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4326#endif
4327 )
4328 && fixP->fx_size == 1
4329 && (fixP->fx_addsy == NULL
4330 || S_IS_DEFINED (fixP->fx_addsy))
4331 && (val == 0 || val == -1))
4332 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4333}
4334
4335#ifdef BFD_ASSEMBLER
4336int
4337md_apply_fix (fixP, valp)
4338 fixS *fixP;
4339 valueT *valp;
4340{
4341 md_apply_fix_2 (fixP, (addressT) *valp);
4342 return 1;
4343}
4344#else
4345void md_apply_fix (fixP, val)
4346 fixS *fixP;
4347 long val;
4348{
4349 md_apply_fix_2 (fixP, (addressT) val);
4350}
4351#endif
4352
4353/* *fragP has been relaxed to its final size, and now needs to have
4354 the bytes inside it modified to conform to the new size There is UGLY
4355 MAGIC here. ..
4356 */
4357static void
4358md_convert_frag_1 (fragP)
4359 register fragS *fragP;
4360{
4361 long disp;
252b5132
RH		 4362 fixS *fixP;
4363
4364 /* Address in object code of the displacement. */
4365 register int object_address = fragP->fr_fix + fragP->fr_address;
4366
4367 /* Address in gas core of the place to store the displacement. */
4368 /* This convinces the native rs6000 compiler to generate the code we
92774660 4369 want. */
252b5132
RH		 4370 register char *buffer_address = fragP->fr_literal;
4371 buffer_address += fragP->fr_fix;
4372 /* end ibm compiler workaround */
4373
4374 /* The displacement of the address, from current location. */
4375 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4376 disp = (disp + fragP->fr_offset) - object_address;
4377
4378#ifdef BFD_ASSEMBLER
49309057 4379 disp += symbol_get_frag (fragP->fr_symbol)->fr_address;
252b5132
RH		 4380#endif
4381
4382 switch (fragP->fr_subtype)
4383 {
151337e8
NC		 4384 case TAB (BRANCHBWL, BYTE):
4385 case TAB (BRABSJUNC, BYTE):
4386 case TAB (BRABSJCOND, BYTE):
4387 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4388 know (issbyte (disp));
4389 if (disp == 0)
b091f402
AM		 4390 as_bad_where (fragP->fr_file, fragP->fr_line,
4391 _("short branch with zero offset: use :w"));
151337e8 4392 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4393 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4394 fixP->fx_pcrel_adjust = -1;
252b5132 4395 break;
151337e8
NC		 4396 case TAB (BRANCHBWL, SHORT):
4397 case TAB (BRABSJUNC, SHORT):
4398 case TAB (BRABSJCOND, SHORT):
4399 case TAB (BRANCHBW, SHORT):
252b5132 4400 fragP->fr_opcode[1] = 0x00;
151337e8 4401 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4402 1, RELAX_RELOC_PC16);
151337e8
NC		 4403 fragP->fr_fix += 2;
4404 break;
4405 case TAB (BRANCHBWL, LONG):
4406 fragP->fr_opcode[1] = (char) 0xFF;
4407 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4408 1, RELAX_RELOC_PC32);
151337e8 4409 fragP->fr_fix += 4;
252b5132 4410 break;
151337e8
NC		 4411 case TAB (BRABSJUNC, LONG):
4412 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4413 {
151337e8
NC		 4414 fragP->fr_opcode[0] = 0x4E;
4415 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand */
4416 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3ae647a0 4417 0, RELAX_RELOC_ABS32);
151337e8
NC		 4418 fragP->fr_fix += 4;
4419 }
4420 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4421 {
4422 fragP->fr_opcode[0] = 0x4E;
4423 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand */
4424 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4425 0, RELAX_RELOC_ABS32);
151337e8 4426 fragP->fr_fix += 4;
252b5132
RH		 4427 }
4428 else
4429 {
151337e8
NC		 4430 /* This cannot happen, because jbsr and jbra are the only two
4431 unconditional branches. */
4432 abort ();
252b5132
RH		 4433 }
4434 break;
151337e8
NC		 4435 case TAB (BRABSJCOND, LONG):
4436 /* Only Bcc 68000 instructions can come here. */
4437 /* Change bcc into b!cc/jmp absl long. */
92774660 4438
252b5132
RH		 4439 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4440 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4441
4442 /* JF: these used to be fr_opcode[2,3], but they may be in a
4443 different frag, in which case refering to them is a no-no.
92774660 4444 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4445 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4446 *buffer_address++ = (char) 0xf9;
4447 fragP->fr_fix += 2; /* account for jmp instruction */
4448 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5cbdaa77 4449 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4450 fragP->fr_fix += 4;
4451 break;
4452 case TAB (FBRANCH, SHORT):
4453 know ((fragP->fr_opcode[1] & 0x40) == 0);
4454 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4455 1, RELAX_RELOC_PC16);
151337e8
NC		 4456 fragP->fr_fix += 2;
4457 break;
4458 case TAB (FBRANCH, LONG):
4459 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4460 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4461 1, RELAX_RELOC_PC32);
252b5132 4462 fragP->fr_fix += 4;
252b5132 4463 break;
151337e8
NC		 4464 case TAB (DBCCLBR, SHORT):
4465 case TAB (DBCCABSJ, SHORT):
4466 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4467 1, RELAX_RELOC_PC16);
151337e8
NC		 4468 fragP->fr_fix += 2;
4469 break;
4470 case TAB (DBCCLBR, LONG):
4471 /* only DBcc instructions can come here */
28e7409f 4472 /* Change dbcc into dbcc/bral. */
28e7409f 4473
252b5132
RH		 4474 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4475 *buffer_address++ = 0x00; /* branch offset = 4 */
4476 *buffer_address++ = 0x04;
4477 *buffer_address++ = 0x60; /* put in bra pc+6 */
4478 *buffer_address++ = 0x06;
151337e8
NC		 4479 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4480 *buffer_address++ = (char) 0xff;
252b5132
RH		 4481
4482 fragP->fr_fix += 6; /* account for bra/jmp instructions */
151337e8 4483 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
5cbdaa77 4484 RELAX_RELOC_PC32);
252b5132 4485 fragP->fr_fix += 4;
252b5132 4486 break;
151337e8
NC		 4487 case TAB (DBCCABSJ, LONG):
4488 /* only DBcc instructions can come here */
4489 /* Change dbcc into dbcc/jmp. */
4490
4491 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4492 *buffer_address++ = 0x00; /* branch offset = 4 */
4493 *buffer_address++ = 0x04;
4494 *buffer_address++ = 0x60; /* put in bra pc+6 */
4495 *buffer_address++ = 0x06;
4496 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4497 *buffer_address++ = (char) 0xf9;
4498
4499 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4500 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
5cbdaa77 4501 RELAX_RELOC_ABS32);
252b5132 4502 fragP->fr_fix += 4;
252b5132 4503 break;
151337e8 4504 case TAB (PCREL1632, SHORT):
252b5132
RH		 4505 fragP->fr_opcode[1] &= ~0x3F;
4506 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
151337e8 4507 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4508 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 4509 fragP->fr_fix += 2;
252b5132 4510 break;
151337e8 4511 case TAB (PCREL1632, LONG):
252b5132
RH		 4512 /* Already set to mode 7.3; this indicates: PC indirect with
4513 suppressed index, 32-bit displacement. */
4514 *buffer_address++ = 0x01;
4515 *buffer_address++ = 0x70;
4516 fragP->fr_fix += 2;
151337e8 4517 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4518 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4519 fixP->fx_pcrel_adjust = 2;
4520 fragP->fr_fix += 4;
252b5132 4521 break;
252b5132 4522 case TAB (PCINDEX, BYTE):
252b5132
RH		 4523 assert (fragP->fr_fix >= 2);
4524 buffer_address[-2] &= ~1;
151337e8 4525 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4526 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4527 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 4528 break;
4529 case TAB (PCINDEX, SHORT):
252b5132
RH		 4530 assert (fragP->fr_fix >= 2);
4531 buffer_address[-2] |= 0x1;
4532 buffer_address[-1] = 0x20;
4533 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4534 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 4535 fixP->fx_pcrel_adjust = 2;
151337e8 4536 fragP->fr_fix += 2;
252b5132
RH		 4537 break;
4538 case TAB (PCINDEX, LONG):
252b5132
RH		 4539 assert (fragP->fr_fix >= 2);
4540 buffer_address[-2] |= 0x1;
4541 buffer_address[-1] = 0x30;
151337e8 4542 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4543 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4544 fixP->fx_pcrel_adjust = 2;
4545 fragP->fr_fix += 4;
4546 break;
4547 case TAB (ABSTOPCREL, SHORT):
4548 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4549 1, RELAX_RELOC_PC16);
151337e8
NC		 4550 fragP->fr_fix += 2;
4551 break;
4552 case TAB (ABSTOPCREL, LONG):
4553 /* The thing to do here is force it to ABSOLUTE LONG, since
4554 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */
4555 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4556 abort ();
4557 fragP->fr_opcode[1] &= ~0x3F;
4558 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4559 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4560 0, RELAX_RELOC_ABS32);
151337e8 4561 fragP->fr_fix += 4;
252b5132 4562 break;
252b5132
RH		 4563 }
4564}
4565
4566#ifndef BFD_ASSEMBLER
4567
4568void
4569md_convert_frag (headers, sec, fragP)
8fce3f5e
AM		 4570 object_headers *headers ATTRIBUTE_UNUSED;
4571 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4572 fragS *fragP;
4573{
4574 md_convert_frag_1 (fragP);
4575}
4576
4577#else
4578
4579void
4580md_convert_frag (abfd, sec, fragP)
36823076
AS		 4581 bfd *abfd ATTRIBUTE_UNUSED;
4582 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4583 fragS *fragP;
4584{
4585 md_convert_frag_1 (fragP);
4586}
4587#endif
4588
4589/* Force truly undefined symbols to their maximum size, and generally set up
4590 the frag list to be relaxed
4591 */
4592int
4593md_estimate_size_before_relax (fragP, segment)
4594 register fragS *fragP;
4595 segT segment;
4596{
4597 int old_fix;
252b5132
RH		 4598
4599 old_fix = fragP->fr_fix;
4600
151337e8 4601 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 4602 switch (fragP->fr_subtype)
4603 {
151337e8
NC		 4604 case TAB (BRANCHBWL, SZ_UNDEF):
4605 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 4606 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 4607 {
151337e8
NC		 4608 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4609 && relaxable_symbol (fragP->fr_symbol))
252b5132 4610 {
151337e8
NC		 4611 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4612 }
4613 else if (flag_short_refs)
4614 {
4615 /* Symbol is undefined and we want short ref. */
4616 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4617 }
4618 else
4619 {
151337e8
NC		 4620 /* Symbol is still undefined. Make it LONG. */
4621 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4622 }
4623 break;
151337e8 4624 }
252b5132 4625
151337e8 4626 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 4627 {
151337e8
NC		 4628 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4629 && relaxable_symbol (fragP->fr_symbol))
252b5132 4630 {
151337e8 4631 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 4632 }
4633 else
4634 {
151337e8
NC		 4635 /* Symbol is undefined and we don't have long branches. */
4636 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4637 }
4638 break;
151337e8 4639 }
252b5132 4640
151337e8 4641 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 4642 case TAB (DBCCLBR, SZ_UNDEF):
4643 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 4644 case TAB (PCREL1632, SZ_UNDEF):
252b5132 4645 {
8ec6253e
NC		 4646 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4647 && relaxable_symbol (fragP->fr_symbol))
151337e8 4648 || flag_short_refs)
252b5132 4649 {
151337e8 4650 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4651 }
4652 else
4653 {
151337e8 4654 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4655 }
4656 break;
151337e8 4657 }
81d4177b 4658
252b5132
RH		 4659 case TAB (PCINDEX, SZ_UNDEF):
4660 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 4661 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 4662 {
4663 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4664 }
4665 else
4666 {
4667 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 4668 }
4669 break;
4670
151337e8
NC		 4671 case TAB (ABSTOPCREL, SZ_UNDEF):
4672 {
4673 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4674 && relaxable_symbol (fragP->fr_symbol)))
4675 {
4676 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 4677 }
4678 else
4679 {
4680 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 4681 }
4682 break;
4683 }
4684
252b5132
RH		 4685 default:
4686 break;
4687 }
4688
151337e8 4689 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 4690 switch (fragP->fr_subtype)
4691 {
151337e8
NC		 4692 case TAB (BRANCHBWL, BYTE):
4693 case TAB (BRABSJUNC, BYTE):
4694 case TAB (BRABSJCOND, BYTE):
4695 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4696 /* We can't do a short jump to the next instruction, so in that
4697 case we force word mode. At this point S_GET_VALUE should
4698 return the offset of the symbol within its frag. If the
4699 symbol is at the start of a frag, and it is the next frag
4700 with any data in it (usually this is just the next frag, but
4701 assembler listings may introduce empty frags), we must use
4702 word mode. */
4703 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4704 {
49309057 4705 fragS *stop;
252b5132
RH		 4706 fragS *l;
4707
49309057 4708 stop = symbol_get_frag (fragP->fr_symbol);
7099f9f9 4709
49309057 4710 for (l = fragP->fr_next; l != stop; l = l->fr_next)
252b5132 4711 {
7099f9f9
NC		 4712 /* Catch empty alignment frags whoes fr_offset field
4713 is an alignment requirement of 2 bytes. The check
4714 below will misinterpret this as evidence that real
4715 code exists between the symbol and the instruction
4716 and so will not convert the short jump into a word
4717 jump. */
4718 if (l->fr_fix == 0
4719 && l->fr_var == 1
4720 && (l->fr_type == rs_align || l->fr_type == rs_align_code))
4721 continue;
4722
4723 if (l->fr_fix + l->fr_var != 0)
4724 break;
252b5132 4725 }
7099f9f9
NC		 4726 if (l == stop)
4727 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4728 }
4729 break;
4730 default:
4731 break;
4732 }
5c65dbc1 4733 fragP->fr_var = md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 4734 return fragP->fr_var + fragP->fr_fix - old_fix;
4735}
4736
4737#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4738/* the bit-field entries in the relocation_info struct plays hell
4739 with the byte-order problems of cross-assembly. So as a hack,
4740 I added this mach. dependent ri twiddler. Ugly, but it gets
4741 you there. -KWK */
4742/* on m68k: first 4 bytes are normal unsigned long, next three bytes
4743 are symbolnum, most sig. byte first. Last byte is broken up with
4744 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4745 nibble as nuthin. (on Sun 3 at least) */
4746/* Translate the internal relocation information into target-specific
92774660 4747 format. */
252b5132
RH		 4748#ifdef comment
4749void
4750md_ri_to_chars (the_bytes, ri)
4751 char *the_bytes;
4752 struct reloc_info_generic *ri;
4753{
4754 /* this is easy */
4755 md_number_to_chars (the_bytes, ri->r_address, 4);
4756 /* now the fun stuff */
4757 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4758 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4759 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4760 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4761 ((ri->r_extern << 4) & 0x10));
4762}
4763
4764#endif /* comment */
4765
4766#ifndef BFD_ASSEMBLER
4767void
4768tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4769 char *where;
4770 fixS *fixP;
4771 relax_addressT segment_address_in_file;
4772{
4773 /*
4774 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4775 * Out: GNU LD relocation length code: 0, 1, or 2.
4776 */
4777
4778 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4779 long r_symbolnum;
4780
4781 know (fixP->fx_addsy != NULL);
4782
4783 md_number_to_chars (where,
4784 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4785 4);
4786
4787 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4788 ? S_GET_TYPE (fixP->fx_addsy)
4789 : fixP->fx_addsy->sy_number);
4790
4791 where[4] = (r_symbolnum >> 16) & 0x0ff;
4792 where[5] = (r_symbolnum >> 8) & 0x0ff;
4793 where[6] = r_symbolnum & 0x0ff;
4794 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4795 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4796}
4797#endif
4798
4799#endif /* OBJ_AOUT or OBJ_BOUT */
4800
4801#ifndef WORKING_DOT_WORD
4802CONST int md_short_jump_size = 4;
4803CONST int md_long_jump_size = 6;
4804
4805void
4806md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4807 char *ptr;
4808 addressT from_addr, to_addr;
36823076
AS		 4809 fragS *frag ATTRIBUTE_UNUSED;
4810 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132
RH		 4811{
4812 valueT offset;
4813
4814 offset = to_addr - (from_addr + 2);
4815
4816 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4817 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4818}
4819
4820void
4821md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4822 char *ptr;
4823 addressT from_addr, to_addr;
4824 fragS *frag;
4825 symbolS *to_symbol;
4826{
4827 valueT offset;
4828
4829 if (!HAVE_LONG_BRANCH(current_architecture))
4830 {
4831 offset = to_addr - S_GET_VALUE (to_symbol);
4832 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4833 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4834 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4835 0, NO_RELOC);
4836 }
4837 else
4838 {
4839 offset = to_addr - (from_addr + 2);
4840 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4841 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4842 }
4843}
4844
4845#endif
4846
4847/* Different values of OK tell what its OK to return. Things that
4848 aren't OK are an error (what a shock, no?)
4849
4850 0: Everything is OK
4851 10: Absolute 1:8 only
4852 20: Absolute 0:7 only
4853 30: absolute 0:15 only
4854 40: Absolute 0:31 only
4855 50: absolute 0:127 only
4856 55: absolute -64:63 only
4857 60: absolute -128:127 only
4858 70: absolute 0:4095 only
4859 80: No bignums
4860
4861 */
4862
4863static int
4864get_num (exp, ok)
4865 struct m68k_exp *exp;
4866 int ok;
4867{
4868 if (exp->exp.X_op == O_absent)
4869 {
4870 /* Do the same thing the VAX asm does */
4871 op (exp) = O_constant;
4872 adds (exp) = 0;
4873 subs (exp) = 0;
4874 offs (exp) = 0;
4875 if (ok == 10)
4876 {
4877 as_warn (_("expression out of range: defaulting to 1"));
4878 offs (exp) = 1;
4879 }
4880 }
4881 else if (exp->exp.X_op == O_constant)
4882 {
4883 switch (ok)
4884 {
4885 case 10:
4886 if (offs (exp) < 1 || offs (exp) > 8)
4887 {
4888 as_warn (_("expression out of range: defaulting to 1"));
4889 offs (exp) = 1;
4890 }
4891 break;
4892 case 20:
4893 if (offs (exp) < 0 || offs (exp) > 7)
4894 goto outrange;
4895 break;
4896 case 30:
4897 if (offs (exp) < 0 || offs (exp) > 15)
4898 goto outrange;
4899 break;
4900 case 40:
4901 if (offs (exp) < 0 || offs (exp) > 32)
4902 goto outrange;
4903 break;
4904 case 50:
4905 if (offs (exp) < 0 || offs (exp) > 127)
4906 goto outrange;
4907 break;
4908 case 55:
4909 if (offs (exp) < -64 || offs (exp) > 63)
4910 goto outrange;
4911 break;
4912 case 60:
4913 if (offs (exp) < -128 || offs (exp) > 127)
4914 goto outrange;
4915 break;
4916 case 70:
4917 if (offs (exp) < 0 || offs (exp) > 4095)
4918 {
4919 outrange:
4920 as_warn (_("expression out of range: defaulting to 0"));
4921 offs (exp) = 0;
4922 }
4923 break;
4924 default:
4925 break;
4926 }
4927 }
4928 else if (exp->exp.X_op == O_big)
4929 {
4930 if (offs (exp) <= 0 /* flonum */
4931 && (ok == 80 /* no bignums */
4932 || (ok > 10 /* small-int ranges including 0 ok */
4933 /* If we have a flonum zero, a zero integer should
4934 do as well (e.g., in moveq). */
4935 && generic_floating_point_number.exponent == 0
4936 && generic_floating_point_number.low[0] == 0)))
4937 {
4938 /* HACK! Turn it into a long */
4939 LITTLENUM_TYPE words[6];
4940
4941 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4942 op (exp) = O_constant;
4943 adds (exp) = 0;
4944 subs (exp) = 0;
4945 offs (exp) = words[1] | (words[0] << 16);
4946 }
4947 else if (ok != 0)
4948 {
4949 op (exp) = O_constant;
4950 adds (exp) = 0;
4951 subs (exp) = 0;
4952 offs (exp) = (ok == 10) ? 1 : 0;
4953 as_warn (_("Can't deal with expression; defaulting to %ld"),
4954 offs (exp));
4955 }
4956 }
4957 else
4958 {
4959 if (ok >= 10 && ok <= 70)
4960 {
4961 op (exp) = O_constant;
4962 adds (exp) = 0;
4963 subs (exp) = 0;
4964 offs (exp) = (ok == 10) ? 1 : 0;
4965 as_warn (_("Can't deal with expression; defaulting to %ld"),
4966 offs (exp));
4967 }
4968 }
4969
4970 if (exp->size != SIZE_UNSPEC)
4971 {
4972 switch (exp->size)
4973 {
4974 case SIZE_UNSPEC:
4975 case SIZE_LONG:
4976 break;
4977 case SIZE_BYTE:
4978 if (!isbyte (offs (exp)))
4979 as_warn (_("expression doesn't fit in BYTE"));
4980 break;
4981 case SIZE_WORD:
4982 if (!isword (offs (exp)))
4983 as_warn (_("expression doesn't fit in WORD"));
4984 break;
4985 }
4986 }
4987
4988 return offs (exp);
4989}
4990
4991/* These are the back-ends for the various machine dependent pseudo-ops. */
4992
4993static void
4994s_data1 (ignore)
36823076 4995 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4996{
4997 subseg_set (data_section, 1);
4998 demand_empty_rest_of_line ();
4999}
5000
5001static void
5002s_data2 (ignore)
36823076 5003 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5004{
5005 subseg_set (data_section, 2);
5006 demand_empty_rest_of_line ();
5007}
5008
5009static void
5010s_bss (ignore)
36823076 5011 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5012{
5013 /* We don't support putting frags in the BSS segment, we fake it
5014 by marking in_bss, then looking at s_skip for clues. */
5015
5016 subseg_set (bss_section, 0);
5017 demand_empty_rest_of_line ();
5018}
5019
5020static void
5021s_even (ignore)
36823076 5022 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5023{
5024 register int temp;
5025 register long temp_fill;
5026
5027 temp = 1; /* JF should be 2? */
5028 temp_fill = get_absolute_expression ();
92774660 5029 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5030 frag_align (temp, (int) temp_fill, 0);
5031 demand_empty_rest_of_line ();
5032 record_alignment (now_seg, temp);
5033}
5034
5035static void
5036s_proc (ignore)
36823076 5037 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5038{
5039 demand_empty_rest_of_line ();
5040}
5041\f
5042/* Pseudo-ops handled for MRI compatibility. */
5043
5044/* This function returns non-zero if the argument is a conditional
5045 pseudo-op. This is called when checking whether a pending
5046 alignment is needed. */
5047
5048int
5049m68k_conditional_pseudoop (pop)
5050 pseudo_typeS *pop;
5051{
5052 return (pop->poc_handler == s_mri_if
5053 || pop->poc_handler == s_mri_else);
5054}
5055
5056/* Handle an MRI style chip specification. */
5057
5058static void
5059mri_chip ()
5060{
5061 char *s;
5062 char c;
5063 int i;
5064
5065 s = input_line_pointer;
5066 /* We can't use get_symbol_end since the processor names are not proper
5067 symbols. */
5068 while (is_part_of_name (c = *input_line_pointer++))
5069 ;
5070 *--input_line_pointer = 0;
5071 for (i = 0; i < n_archs; i++)
5072 if (strcasecmp (s, archs[i].name) == 0)
5073 break;
5074 if (i >= n_archs)
5075 {
5076 as_bad (_("%s: unrecognized processor name"), s);
5077 *input_line_pointer = c;
5078 ignore_rest_of_line ();
5079 return;
5080 }
5081 *input_line_pointer = c;
5082
5083 if (*input_line_pointer == '/')
5084 current_architecture = 0;
5085 else
5086 current_architecture &= m68881 | m68851;
5087 current_architecture |= archs[i].arch;
5088
5089 while (*input_line_pointer == '/')
5090 {
5091 ++input_line_pointer;
5092 s = input_line_pointer;
5093 /* We can't use get_symbol_end since the processor names are not
5094 proper symbols. */
5095 while (is_part_of_name (c = *input_line_pointer++))
5096 ;
5097 *--input_line_pointer = 0;
5098 if (strcmp (s, "68881") == 0)
5099 current_architecture |= m68881;
5100 else if (strcmp (s, "68851") == 0)
5101 current_architecture |= m68851;
5102 *input_line_pointer = c;
5103 }
5104
5105 /* Update info about available control registers. */
5106 select_control_regs ();
5107}
5108
5109/* The MRI CHIP pseudo-op. */
5110
5111static void
5112s_chip (ignore)
36823076 5113 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5114{
5115 char *stop = NULL;
5116 char stopc;
5117
5118 if (flag_mri)
5119 stop = mri_comment_field (&stopc);
5120 mri_chip ();
5121 if (flag_mri)
5122 mri_comment_end (stop, stopc);
5123 demand_empty_rest_of_line ();
5124}
5125
5126/* The MRI FOPT pseudo-op. */
5127
5128static void
5129s_fopt (ignore)
36823076 5130 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5131{
5132 SKIP_WHITESPACE ();
5133
5134 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5135 {
5136 int temp;
5137
5138 input_line_pointer += 3;
5139 temp = get_absolute_expression ();
5140 if (temp < 0 || temp > 7)
5141 as_bad (_("bad coprocessor id"));
5142 else
5143 m68k_float_copnum = COP0 + temp;
5144 }
5145 else
5146 {
5147 as_bad (_("unrecognized fopt option"));
5148 ignore_rest_of_line ();
5149 return;
5150 }
5151
5152 demand_empty_rest_of_line ();
5153}
5154
5155/* The structure used to handle the MRI OPT pseudo-op. */
5156
5157struct opt_action
5158{
5159 /* The name of the option. */
5160 const char *name;
5161
5162 /* If this is not NULL, just call this function. The first argument
5163 is the ARG field of this structure, the second argument is
5164 whether the option was negated. */
5165 void (*pfn) PARAMS ((int arg, int on));
5166
5167 /* If this is not NULL, and the PFN field is NULL, set the variable
5168 this points to. Set it to the ARG field if the option was not
5169 negated, and the NOTARG field otherwise. */
5170 int *pvar;
5171
5172 /* The value to pass to PFN or to assign to *PVAR. */
5173 int arg;
5174
5175 /* The value to assign to *PVAR if the option is negated. If PFN is
5176 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5177 the option may not be negated. */
5178 int notarg;
5179};
5180
5181/* The table used to handle the MRI OPT pseudo-op. */
5182
5183static void skip_to_comma PARAMS ((int, int));
5184static void opt_nest PARAMS ((int, int));
5185static void opt_chip PARAMS ((int, int));
5186static void opt_list PARAMS ((int, int));
5187static void opt_list_symbols PARAMS ((int, int));
5188
5189static const struct opt_action opt_table[] =
5190{
5191 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5192
5193 /* We do relaxing, so there is little use for these options. */
5194 { "b", 0, 0, 0, 0 },
5195 { "brs", 0, 0, 0, 0 },
5196 { "brb", 0, 0, 0, 0 },
5197 { "brl", 0, 0, 0, 0 },
5198 { "brw", 0, 0, 0, 0 },
5199
5200 { "c", 0, 0, 0, 0 },
5201 { "cex", 0, 0, 0, 0 },
5202 { "case", 0, &symbols_case_sensitive, 1, 0 },
5203 { "cl", 0, 0, 0, 0 },
5204 { "cre", 0, 0, 0, 0 },
5205 { "d", 0, &flag_keep_locals, 1, 0 },
5206 { "e", 0, 0, 0, 0 },
5207 { "f", 0, &flag_short_refs, 1, 0 },
5208 { "frs", 0, &flag_short_refs, 1, 0 },
5209 { "frl", 0, &flag_short_refs, 0, 1 },
5210 { "g", 0, 0, 0, 0 },
5211 { "i", 0, 0, 0, 0 },
5212 { "m", 0, 0, 0, 0 },
5213 { "mex", 0, 0, 0, 0 },
5214 { "mc", 0, 0, 0, 0 },
5215 { "md", 0, 0, 0, 0 },
5216 { "nest", opt_nest, 0, 0, 0 },
5217 { "next", skip_to_comma, 0, 0, 0 },
5218 { "o", 0, 0, 0, 0 },
5219 { "old", 0, 0, 0, 0 },
5220 { "op", skip_to_comma, 0, 0, 0 },
5221 { "pco", 0, 0, 0, 0 },
5222 { "p", opt_chip, 0, 0, 0 },
5223 { "pcr", 0, 0, 0, 0 },
5224 { "pcs", 0, 0, 0, 0 },
5225 { "r", 0, 0, 0, 0 },
5226 { "quick", 0, &m68k_quick, 1, 0 },
5227 { "rel32", 0, &m68k_rel32, 1, 0 },
5228 { "s", opt_list, 0, 0, 0 },
5229 { "t", opt_list_symbols, 0, 0, 0 },
5230 { "w", 0, &flag_no_warnings, 0, 1 },
5231 { "x", 0, 0, 0, 0 }
5232};
5233
8fce3f5e 5234#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5235
5236/* The MRI OPT pseudo-op. */
5237
5238static void
5239s_opt (ignore)
36823076 5240 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5241{
5242 do
5243 {
5244 int t;
5245 char *s;
5246 char c;
5247 int i;
5248 const struct opt_action *o;
5249
5250 SKIP_WHITESPACE ();
5251
5252 t = 1;
5253 if (*input_line_pointer == '-')
5254 {
5255 ++input_line_pointer;
5256 t = 0;
5257 }
5258 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5259 {
5260 input_line_pointer += 2;
5261 t = 0;
5262 }
5263
5264 s = input_line_pointer;
5265 c = get_symbol_end ();
5266
5267 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5268 {
5269 if (strcasecmp (s, o->name) == 0)
5270 {
5271 if (o->pfn)
5272 {
5273 /* Restore input_line_pointer now in case the option
5274 takes arguments. */
5275 *input_line_pointer = c;
5276 (*o->pfn) (o->arg, t);
5277 }
5278 else if (o->pvar != NULL)
5279 {
5280 if (! t && o->arg == o->notarg)
5281 as_bad (_("option `%s' may not be negated"), s);
5282 *input_line_pointer = c;
5283 *o->pvar = t ? o->arg : o->notarg;
5284 }
5285 else
5286 *input_line_pointer = c;
5287 break;
5288 }
5289 }
5290 if (i >= OPTCOUNT)
5291 {
5292 as_bad (_("option `%s' not recognized"), s);
5293 *input_line_pointer = c;
5294 }
5295 }
5296 while (*input_line_pointer++ == ',');
5297
5298 /* Move back to terminating character. */
5299 --input_line_pointer;
5300 demand_empty_rest_of_line ();
5301}
5302
5303/* Skip ahead to a comma. This is used for OPT options which we do
5304 not suppor tand which take arguments. */
5305
5306static void
5307skip_to_comma (arg, on)
36823076
AS		 5308 int arg ATTRIBUTE_UNUSED;
5309 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5310{
5311 while (*input_line_pointer != ','
5312 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5313 ++input_line_pointer;
5314}
5315
5316/* Handle the OPT NEST=depth option. */
5317
5318static void
5319opt_nest (arg, on)
36823076
AS		 5320 int arg ATTRIBUTE_UNUSED;
5321 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5322{
5323 if (*input_line_pointer != '=')
5324 {
5325 as_bad (_("bad format of OPT NEST=depth"));
5326 return;
5327 }
5328
5329 ++input_line_pointer;
5330 max_macro_nest = get_absolute_expression ();
5331}
5332
5333/* Handle the OPT P=chip option. */
5334
5335static void
5336opt_chip (arg, on)
36823076
AS		 5337 int arg ATTRIBUTE_UNUSED;
5338 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5339{
5340 if (*input_line_pointer != '=')
5341 {
5342 /* This is just OPT P, which we do not support. */
5343 return;
5344 }
5345
5346 ++input_line_pointer;
5347 mri_chip ();
5348}
5349
5350/* Handle the OPT S option. */
5351
5352static void
5353opt_list (arg, on)
36823076 5354 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5355 int on;
5356{
5357 listing_list (on);
5358}
5359
5360/* Handle the OPT T option. */
5361
5362static void
5363opt_list_symbols (arg, on)
36823076 5364 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5365 int on;
5366{
5367 if (on)
5368 listing |= LISTING_SYMBOLS;
5369 else
5370 listing &=~ LISTING_SYMBOLS;
5371}
5372
5373/* Handle the MRI REG pseudo-op. */
5374
5375static void
5376s_reg (ignore)
36823076 5377 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5378{
5379 char *s;
5380 int c;
5381 struct m68k_op rop;
5382 int mask;
5383 char *stop = NULL;
5384 char stopc;
5385
5386 if (line_label == NULL)
5387 {
5388 as_bad (_("missing label"));
5389 ignore_rest_of_line ();
5390 return;
5391 }
5392
5393 if (flag_mri)
5394 stop = mri_comment_field (&stopc);
5395
5396 SKIP_WHITESPACE ();
5397
5398 s = input_line_pointer;
5399 while (isalnum ((unsigned char) *input_line_pointer)
5400#ifdef REGISTER_PREFIX
5401 || *input_line_pointer == REGISTER_PREFIX
5402#endif
5403 || *input_line_pointer == '/'
5404 || *input_line_pointer == '-')
5405 ++input_line_pointer;
5406 c = *input_line_pointer;
5407 *input_line_pointer = '\0';
5408
5409 if (m68k_ip_op (s, &rop) != 0)
5410 {
5411 if (rop.error == NULL)
5412 as_bad (_("bad register list"));
5413 else
5414 as_bad (_("bad register list: %s"), rop.error);
5415 *input_line_pointer = c;
5416 ignore_rest_of_line ();
5417 return;
5418 }
5419
5420 *input_line_pointer = c;
5421
5422 if (rop.mode == REGLST)
5423 mask = rop.mask;
5424 else if (rop.mode == DREG)
5425 mask = 1 << (rop.reg - DATA0);
5426 else if (rop.mode == AREG)
5427 mask = 1 << (rop.reg - ADDR0 + 8);
5428 else if (rop.mode == FPREG)
5429 mask = 1 << (rop.reg - FP0 + 16);
5430 else if (rop.mode == CONTROL
5431 && rop.reg == FPI)
5432 mask = 1 << 24;
5433 else if (rop.mode == CONTROL
5434 && rop.reg == FPS)
5435 mask = 1 << 25;
5436 else if (rop.mode == CONTROL
5437 && rop.reg == FPC)
5438 mask = 1 << 26;
5439 else
5440 {
5441 as_bad (_("bad register list"));
5442 ignore_rest_of_line ();
5443 return;
5444 }
5445
5446 S_SET_SEGMENT (line_label, reg_section);
5447 S_SET_VALUE (line_label, ~mask);
49309057 5448 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5449
5450 if (flag_mri)
5451 mri_comment_end (stop, stopc);
5452
5453 demand_empty_rest_of_line ();
5454}
5455
5456/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5457
5458struct save_opts
5459{
5460 struct save_opts *next;
5461 int abspcadd;
5462 int symbols_case_sensitive;
5463 int keep_locals;
5464 int short_refs;
5465 int architecture;
5466 int quick;
5467 int rel32;
5468 int listing;
5469 int no_warnings;
5470 /* FIXME: We don't save OPT S. */
5471};
5472
5473/* This variable holds the stack of saved options. */
5474
5475static struct save_opts *save_stack;
5476
5477/* The MRI SAVE pseudo-op. */
5478
5479static void
5480s_save (ignore)
36823076 5481 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5482{
5483 struct save_opts *s;
5484
5485 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5486 s->abspcadd = m68k_abspcadd;
5487 s->symbols_case_sensitive = symbols_case_sensitive;
5488 s->keep_locals = flag_keep_locals;
5489 s->short_refs = flag_short_refs;
5490 s->architecture = current_architecture;
5491 s->quick = m68k_quick;
5492 s->rel32 = m68k_rel32;
5493 s->listing = listing;
5494 s->no_warnings = flag_no_warnings;
5495
5496 s->next = save_stack;
5497 save_stack = s;
5498
5499 demand_empty_rest_of_line ();
5500}
5501
5502/* The MRI RESTORE pseudo-op. */
5503
5504static void
5505s_restore (ignore)
36823076 5506 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5507{
5508 struct save_opts *s;
5509
5510 if (save_stack == NULL)
5511 {
5512 as_bad (_("restore without save"));
5513 ignore_rest_of_line ();
5514 return;
5515 }
5516
5517 s = save_stack;
5518 save_stack = s->next;
5519
5520 m68k_abspcadd = s->abspcadd;
5521 symbols_case_sensitive = s->symbols_case_sensitive;
5522 flag_keep_locals = s->keep_locals;
5523 flag_short_refs = s->short_refs;
5524 current_architecture = s->architecture;
5525 m68k_quick = s->quick;
5526 m68k_rel32 = s->rel32;
5527 listing = s->listing;
5528 flag_no_warnings = s->no_warnings;
5529
5530 free (s);
5531
5532 demand_empty_rest_of_line ();
5533}
5534
5535/* Types of MRI structured control directives. */
5536
5537enum mri_control_type
5538{
5539 mri_for,
5540 mri_if,
5541 mri_repeat,
5542 mri_while
5543};
5544
5545/* This structure is used to stack the MRI structured control
5546 directives. */
5547
5548struct mri_control_info
5549{
5550 /* The directive within which this one is enclosed. */
5551 struct mri_control_info *outer;
5552
5553 /* The type of directive. */
5554 enum mri_control_type type;
5555
5556 /* Whether an ELSE has been in an IF. */
5557 int else_seen;
5558
5559 /* The add or sub statement at the end of a FOR. */
5560 char *incr;
5561
5562 /* The label of the top of a FOR or REPEAT loop. */
5563 char *top;
5564
5565 /* The label to jump to for the next iteration, or the else
5566 expression of a conditional. */
5567 char *next;
5568
5569 /* The label to jump to to break out of the loop, or the label past
5570 the end of a conditional. */
5571 char *bottom;
5572};
5573
5574/* The stack of MRI structured control directives. */
5575
5576static struct mri_control_info *mri_control_stack;
5577
5578/* The current MRI structured control directive index number, used to
5579 generate label names. */
5580
5581static int mri_control_index;
5582
5583/* Some function prototypes. */
5584
5585static void mri_assemble PARAMS ((char *));
5586static char *mri_control_label PARAMS ((void));
5587static struct mri_control_info *push_mri_control
5588 PARAMS ((enum mri_control_type));
5589static void pop_mri_control PARAMS ((void));
5590static int parse_mri_condition PARAMS ((int *));
5591static int parse_mri_control_operand
5592 PARAMS ((int *, char **, char **, char **, char **));
5593static int swap_mri_condition PARAMS ((int));
5594static int reverse_mri_condition PARAMS ((int));
5595static void build_mri_control_operand
5596 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5597 const char *, int));
5598static void parse_mri_control_expression
5599 PARAMS ((char *, int, const char *, const char *, int));
5600
5601/* Assemble an instruction for an MRI structured control directive. */
5602
5603static void
5604mri_assemble (str)
5605 char *str;
5606{
5607 char *s;
5608
5609 /* md_assemble expects the opcode to be in lower case. */
5610 for (s = str; *s != ' ' && *s != '\0'; s++)
5611 {
5612 if (isupper ((unsigned char) *s))
5613 *s = tolower ((unsigned char) *s);
5614 }
5615
5616 md_assemble (str);
5617}
5618
5619/* Generate a new MRI label structured control directive label name. */
5620
5621static char *
5622mri_control_label ()
5623{
5624 char *n;
5625
5626 n = (char *) xmalloc (20);
5627 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5628 ++mri_control_index;
5629 return n;
5630}
5631
5632/* Create a new MRI structured control directive. */
5633
5634static struct mri_control_info *
5635push_mri_control (type)
5636 enum mri_control_type type;
5637{
5638 struct mri_control_info *n;
5639
5640 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5641
5642 n->type = type;
5643 n->else_seen = 0;
5644 if (type == mri_if || type == mri_while)
5645 n->top = NULL;
5646 else
5647 n->top = mri_control_label ();
5648 n->next = mri_control_label ();
5649 n->bottom = mri_control_label ();
5650
5651 n->outer = mri_control_stack;
5652 mri_control_stack = n;
5653
5654 return n;
5655}
5656
5657/* Pop off the stack of MRI structured control directives. */
5658
5659static void
5660pop_mri_control ()
5661{
5662 struct mri_control_info *n;
5663
5664 n = mri_control_stack;
5665 mri_control_stack = n->outer;
5666 if (n->top != NULL)
5667 free (n->top);
5668 free (n->next);
5669 free (n->bottom);
5670 free (n);
5671}
5672
5673/* Recognize a condition code in an MRI structured control expression. */
5674
5675static int
5676parse_mri_condition (pcc)
5677 int *pcc;
5678{
5679 char c1, c2;
5680
5681 know (*input_line_pointer == '<');
5682
5683 ++input_line_pointer;
5684 c1 = *input_line_pointer++;
5685 c2 = *input_line_pointer++;
5686
5687 if (*input_line_pointer != '>')
5688 {
5689 as_bad (_("syntax error in structured control directive"));
5690 return 0;
5691 }
5692
5693 ++input_line_pointer;
5694 SKIP_WHITESPACE ();
5695
5696 if (isupper (c1))
5697 c1 = tolower (c1);
5698 if (isupper (c2))
5699 c2 = tolower (c2);
5700
5701 *pcc = (c1 << 8) | c2;
5702
5703 return 1;
5704}
5705
5706/* Parse a single operand in an MRI structured control expression. */
5707
5708static int
5709parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5710 int *pcc;
5711 char **leftstart;
5712 char **leftstop;
5713 char **rightstart;
5714 char **rightstop;
5715{
5716 char *s;
5717
5718 SKIP_WHITESPACE ();
5719
5720 *pcc = -1;
5721 *leftstart = NULL;
5722 *leftstop = NULL;
5723 *rightstart = NULL;
5724 *rightstop = NULL;
5725
5726 if (*input_line_pointer == '<')
5727 {
5728 /* It's just a condition code. */
5729 return parse_mri_condition (pcc);
5730 }
5731
5732 /* Look ahead for the condition code. */
5733 for (s = input_line_pointer; *s != '\0'; ++s)
5734 {
5735 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5736 break;
5737 }
5738 if (*s == '\0')
5739 {
5740 as_bad (_("missing condition code in structured control directive"));
5741 return 0;
5742 }
5743
5744 *leftstart = input_line_pointer;
5745 *leftstop = s;
5746 if (*leftstop > *leftstart
5747 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5748 --*leftstop;
5749
5750 input_line_pointer = s;
5751 if (! parse_mri_condition (pcc))
5752 return 0;
5753
5754 /* Look ahead for AND or OR or end of line. */
5755 for (s = input_line_pointer; *s != '\0'; ++s)
5756 {
e1f44d10
NC		 5757 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5758 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5759 ^^^ ^^ */
5760 if ( ( s == input_line_pointer
5761 || *(s-1) == ' '
5762 || *(s-1) == '\t')
5763 && ( ( strncasecmp (s, "AND", 3) == 0
5764 && (s[3] == '.' || ! is_part_of_name (s[3])))
5765 || ( strncasecmp (s, "OR", 2) == 0
5766 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5767 break;
252b5132
RH		 5768 }
5769
5770 *rightstart = input_line_pointer;
5771 *rightstop = s;
5772 if (*rightstop > *rightstart
5773 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5774 --*rightstop;
5775
5776 input_line_pointer = s;
5777
5778 return 1;
5779}
5780
5781#define MCC(b1, b2) (((b1) << 8) | (b2))
5782
5783/* Swap the sense of a condition. This changes the condition so that
5784 it generates the same result when the operands are swapped. */
5785
5786static int
5787swap_mri_condition (cc)
5788 int cc;
5789{
5790 switch (cc)
5791 {
5792 case MCC ('h', 'i'): return MCC ('c', 's');
5793 case MCC ('l', 's'): return MCC ('c', 'c');
e1f44d10
NC		 5794 /* <HS> is an alias for <CC> */
5795 case MCC ('h', 's'):
252b5132 5796 case MCC ('c', 'c'): return MCC ('l', 's');
e1f44d10
NC		 5797 /* <LO> is an alias for <CS> */
5798 case MCC ('l', 'o'):
252b5132
RH		 5799 case MCC ('c', 's'): return MCC ('h', 'i');
5800 case MCC ('p', 'l'): return MCC ('m', 'i');
5801 case MCC ('m', 'i'): return MCC ('p', 'l');
5802 case MCC ('g', 'e'): return MCC ('l', 'e');
5803 case MCC ('l', 't'): return MCC ('g', 't');
5804 case MCC ('g', 't'): return MCC ('l', 't');
5805 case MCC ('l', 'e'): return MCC ('g', 'e');
e1f44d10
NC		 5806 /* issue a warning for conditions we can not swap */
5807 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
5808 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
5809 case MCC ('v', 'c'):
5810 case MCC ('v', 's'):
5811 default :
5812 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
5813 (char) (cc >> 8), (char) (cc));
5814 break;
252b5132
RH		 5815 }
5816 return cc;
5817}
5818
5819/* Reverse the sense of a condition. */
5820
5821static int
5822reverse_mri_condition (cc)
5823 int cc;
5824{
5825 switch (cc)
5826 {
5827 case MCC ('h', 'i'): return MCC ('l', 's');
5828 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 5829 /* <HS> is an alias for <CC> */
5830 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 5831 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 5832 /* <LO> is an alias for <CS> */
5833 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 5834 case MCC ('c', 's'): return MCC ('c', 'c');
5835 case MCC ('n', 'e'): return MCC ('e', 'q');
5836 case MCC ('e', 'q'): return MCC ('n', 'e');
5837 case MCC ('v', 'c'): return MCC ('v', 's');
5838 case MCC ('v', 's'): return MCC ('v', 'c');
5839 case MCC ('p', 'l'): return MCC ('m', 'i');
5840 case MCC ('m', 'i'): return MCC ('p', 'l');
5841 case MCC ('g', 'e'): return MCC ('l', 't');
5842 case MCC ('l', 't'): return MCC ('g', 'e');
5843 case MCC ('g', 't'): return MCC ('l', 'e');
5844 case MCC ('l', 'e'): return MCC ('g', 't');
5845 }
5846 return cc;
5847}
5848
5849/* Build an MRI structured control expression. This generates test
5850 and branch instructions. It goes to TRUELAB if the condition is
5851 true, and to FALSELAB if the condition is false. Exactly one of
5852 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5853 is the size qualifier for the expression. EXTENT is the size to
5854 use for the branch. */
5855
5856static void
5857build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5858 rightstop, truelab, falselab, extent)
5859 int qual;
5860 int cc;
5861 char *leftstart;
5862 char *leftstop;
5863 char *rightstart;
5864 char *rightstop;
5865 const char *truelab;
5866 const char *falselab;
5867 int extent;
5868{
5869 char *buf;
5870 char *s;
5871
5872 if (leftstart != NULL)
5873 {
5874 struct m68k_op leftop, rightop;
5875 char c;
5876
5877 /* Swap the compare operands, if necessary, to produce a legal
5878 m68k compare instruction. Comparing a register operand with
5879 a non-register operand requires the register to be on the
5880 right (cmp, cmpa). Comparing an immediate value with
5881 anything requires the immediate value to be on the left
5882 (cmpi). */
5883
5884 c = *leftstop;
5885 *leftstop = '\0';
5886 (void) m68k_ip_op (leftstart, &leftop);
5887 *leftstop = c;
5888
5889 c = *rightstop;
5890 *rightstop = '\0';
5891 (void) m68k_ip_op (rightstart, &rightop);
5892 *rightstop = c;
5893
5894 if (rightop.mode == IMMED
5895 || ((leftop.mode == DREG || leftop.mode == AREG)
5896 && (rightop.mode != DREG && rightop.mode != AREG)))
5897 {
5898 char *temp;
5899
e1f44d10
NC		 5900 /* Correct conditional handling:
5901 if #1 <lt> d0 then ;means if (1 < d0)
5902 ...
5903 endi
5904
5905 should assemble to:
5906
5907 cmp #1,d0 if we do *not* swap the operands
5908 bgt true we need the swapped condition!
5909 ble false
5910 true:
5911 ...
5912 false:
5913 */
252b5132
RH		 5914 temp = leftstart;
5915 leftstart = rightstart;
5916 rightstart = temp;
5917 temp = leftstop;
5918 leftstop = rightstop;
5919 rightstop = temp;
e1f44d10
NC		 5920 } else {
5921 cc = swap_mri_condition (cc);
252b5132
RH		 5922 }
5923 }
5924
5925 if (truelab == NULL)
5926 {
5927 cc = reverse_mri_condition (cc);
5928 truelab = falselab;
5929 }
92774660 5930
252b5132
RH		 5931 if (leftstart != NULL)
5932 {
5933 buf = (char *) xmalloc (20
5934 + (leftstop - leftstart)
5935 + (rightstop - rightstart));
5936 s = buf;
5937 *s++ = 'c';
5938 *s++ = 'm';
5939 *s++ = 'p';
5940 if (qual != '\0')
e1f44d10 5941 *s++ = tolower(qual);
252b5132
RH		 5942 *s++ = ' ';
5943 memcpy (s, leftstart, leftstop - leftstart);
5944 s += leftstop - leftstart;
5945 *s++ = ',';
5946 memcpy (s, rightstart, rightstop - rightstart);
5947 s += rightstop - rightstart;
5948 *s = '\0';
5949 mri_assemble (buf);
5950 free (buf);
5951 }
92774660 5952
252b5132
RH		 5953 buf = (char *) xmalloc (20 + strlen (truelab));
5954 s = buf;
5955 *s++ = 'b';
5956 *s++ = cc >> 8;
5957 *s++ = cc & 0xff;
5958 if (extent != '\0')
e1f44d10 5959 *s++ = tolower(extent);
252b5132
RH		 5960 *s++ = ' ';
5961 strcpy (s, truelab);
5962 mri_assemble (buf);
5963 free (buf);
5964}
5965
5966/* Parse an MRI structured control expression. This generates test
5967 and branch instructions. STOP is where the expression ends. It
5968 goes to TRUELAB if the condition is true, and to FALSELAB if the
5969 condition is false. Exactly one of TRUELAB and FALSELAB will be
5970 NULL, meaning to fall through. QUAL is the size qualifier for the
5971 expression. EXTENT is the size to use for the branch. */
5972
5973static void
5974parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5975 char *stop;
5976 int qual;
5977 const char *truelab;
5978 const char *falselab;
5979 int extent;
5980{
5981 int c;
5982 int cc;
5983 char *leftstart;
5984 char *leftstop;
5985 char *rightstart;
5986 char *rightstop;
5987
5988 c = *stop;
5989 *stop = '\0';
5990
5991 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5992 &rightstart, &rightstop))
5993 {
5994 *stop = c;
5995 return;
5996 }
5997
5998 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5999 {
6000 const char *flab;
6001
6002 if (falselab != NULL)
6003 flab = falselab;
6004 else
6005 flab = mri_control_label ();
6006
6007 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6008 rightstop, (const char *) NULL, flab, extent);
6009
6010 input_line_pointer += 3;
6011 if (*input_line_pointer != '.'
6012 || input_line_pointer[1] == '\0')
6013 qual = '\0';
6014 else
6015 {
6016 qual = input_line_pointer[1];
6017 input_line_pointer += 2;
6018 }
6019
6020 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6021 &rightstart, &rightstop))
6022 {
6023 *stop = c;
6024 return;
6025 }
6026
6027 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6028 rightstop, truelab, falselab, extent);
6029
6030 if (falselab == NULL)
6031 colon (flab);
6032 }
6033 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6034 {
6035 const char *tlab;
6036
6037 if (truelab != NULL)
6038 tlab = truelab;
6039 else
6040 tlab = mri_control_label ();
6041
6042 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6043 rightstop, tlab, (const char *) NULL, extent);
6044
6045 input_line_pointer += 2;
6046 if (*input_line_pointer != '.'
6047 || input_line_pointer[1] == '\0')
6048 qual = '\0';
6049 else
6050 {
6051 qual = input_line_pointer[1];
6052 input_line_pointer += 2;
6053 }
6054
6055 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6056 &rightstart, &rightstop))
6057 {
6058 *stop = c;
6059 return;
6060 }
6061
6062 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6063 rightstop, truelab, falselab, extent);
6064
6065 if (truelab == NULL)
6066 colon (tlab);
6067 }
6068 else
6069 {
6070 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6071 rightstop, truelab, falselab, extent);
6072 }
6073
6074 *stop = c;
6075 if (input_line_pointer != stop)
6076 as_bad (_("syntax error in structured control directive"));
6077}
6078
6079/* Handle the MRI IF pseudo-op. This may be a structured control
6080 directive, or it may be a regular assembler conditional, depending
6081 on its operands. */
6082
6083static void
6084s_mri_if (qual)
6085 int qual;
6086{
6087 char *s;
6088 int c;
6089 struct mri_control_info *n;
6090
6091 /* A structured control directive must end with THEN with an
6092 optional qualifier. */
6093 s = input_line_pointer;
e1f44d10
NC		 6094 /* We only accept '*' as introduction of comments if preceded by white space
6095 or at first column of a line (I think this can't actually happen here?)
6096 This is important when assembling:
6097 if d0 <ne> 12(a0,d0*2) then
6098 if d0 <ne> #CONST*20 then */
6099 while ( ! ( is_end_of_line[(unsigned char) *s]
6100 || ( flag_mri
6101 && *s == '*'
6102 && ( s == input_line_pointer
6103 || *(s-1) == ' '
6104 || *(s-1) == '\t'))))
252b5132
RH		 6105 ++s;
6106 --s;
6107 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6108 --s;
6109
6110 if (s - input_line_pointer > 1
6111 && s[-1] == '.')
6112 s -= 2;
6113
6114 if (s - input_line_pointer < 3
6115 || strncasecmp (s - 3, "THEN", 4) != 0)
6116 {
6117 if (qual != '\0')
6118 {
6119 as_bad (_("missing then"));
6120 ignore_rest_of_line ();
6121 return;
6122 }
6123
6124 /* It's a conditional. */
6125 s_if (O_ne);
6126 return;
6127 }
6128
6129 /* Since this might be a conditional if, this pseudo-op will be
6130 called even if we are supported to be ignoring input. Double
6131 check now. Clobber *input_line_pointer so that ignore_input
6132 thinks that this is not a special pseudo-op. */
6133 c = *input_line_pointer;
6134 *input_line_pointer = 0;
6135 if (ignore_input ())
6136 {
6137 *input_line_pointer = c;
6138 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6139 ++input_line_pointer;
6140 demand_empty_rest_of_line ();
6141 return;
6142 }
6143 *input_line_pointer = c;
6144
6145 n = push_mri_control (mri_if);
6146
6147 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6148 n->next, s[1] == '.' ? s[2] : '\0');
6149
6150 if (s[1] == '.')
6151 input_line_pointer = s + 3;
6152 else
6153 input_line_pointer = s + 1;
6154
6155 if (flag_mri)
6156 {
6157 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6158 ++input_line_pointer;
6159 }
6160
6161 demand_empty_rest_of_line ();
6162}
6163
6164/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6165 structured IF, associate the ELSE with the IF. Otherwise, assume
6166 it is a conditional else. */
6167
6168static void
6169s_mri_else (qual)
6170 int qual;
6171{
6172 int c;
6173 char *buf;
6174 char q[2];
6175
6176 if (qual == '\0'
6177 && (mri_control_stack == NULL
6178 || mri_control_stack->type != mri_if
6179 || mri_control_stack->else_seen))
6180 {
6181 s_else (0);
6182 return;
6183 }
6184
6185 c = *input_line_pointer;
6186 *input_line_pointer = 0;
6187 if (ignore_input ())
6188 {
6189 *input_line_pointer = c;
6190 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6191 ++input_line_pointer;
6192 demand_empty_rest_of_line ();
6193 return;
6194 }
6195 *input_line_pointer = c;
6196
6197 if (mri_control_stack == NULL
6198 || mri_control_stack->type != mri_if
6199 || mri_control_stack->else_seen)
6200 {
6201 as_bad (_("else without matching if"));
6202 ignore_rest_of_line ();
6203 return;
6204 }
6205
6206 mri_control_stack->else_seen = 1;
6207
6208 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
e1f44d10 6209 q[0] = tolower(qual);
252b5132
RH		 6210 q[1] = '\0';
6211 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6212 mri_assemble (buf);
6213 free (buf);
6214
6215 colon (mri_control_stack->next);
6216
6217 if (flag_mri)
6218 {
6219 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6220 ++input_line_pointer;
6221 }
6222
6223 demand_empty_rest_of_line ();
6224}
6225
6226/* Handle the MRI ENDI pseudo-op. */
6227
6228static void
6229s_mri_endi (ignore)
36823076 6230 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6231{
6232 if (mri_control_stack == NULL
6233 || mri_control_stack->type != mri_if)
6234 {
6235 as_bad (_("endi without matching if"));
6236 ignore_rest_of_line ();
6237 return;
6238 }
6239
6240 /* ignore_input will not return true for ENDI, so we don't need to
6241 worry about checking it again here. */
6242
6243 if (! mri_control_stack->else_seen)
6244 colon (mri_control_stack->next);
6245 colon (mri_control_stack->bottom);
6246
6247 pop_mri_control ();
6248
6249 if (flag_mri)
6250 {
6251 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6252 ++input_line_pointer;
6253 }
6254
6255 demand_empty_rest_of_line ();
6256}
6257
6258/* Handle the MRI BREAK pseudo-op. */
6259
6260static void
6261s_mri_break (extent)
6262 int extent;
6263{
6264 struct mri_control_info *n;
6265 char *buf;
6266 char ex[2];
6267
6268 n = mri_control_stack;
6269 while (n != NULL
6270 && n->type != mri_for
6271 && n->type != mri_repeat
6272 && n->type != mri_while)
6273 n = n->outer;
6274 if (n == NULL)
6275 {
6276 as_bad (_("break outside of structured loop"));
6277 ignore_rest_of_line ();
6278 return;
6279 }
6280
6281 buf = (char *) xmalloc (20 + strlen (n->bottom));
e1f44d10 6282 ex[0] = tolower(extent);
252b5132
RH		 6283 ex[1] = '\0';
6284 sprintf (buf, "bra%s %s", ex, n->bottom);
6285 mri_assemble (buf);
6286 free (buf);
6287
6288 if (flag_mri)
6289 {
6290 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6291 ++input_line_pointer;
6292 }
6293
6294 demand_empty_rest_of_line ();
6295}
6296
6297/* Handle the MRI NEXT pseudo-op. */
6298
6299static void
6300s_mri_next (extent)
6301 int extent;
6302{
6303 struct mri_control_info *n;
6304 char *buf;
6305 char ex[2];
6306
6307 n = mri_control_stack;
6308 while (n != NULL
6309 && n->type != mri_for
6310 && n->type != mri_repeat
6311 && n->type != mri_while)
6312 n = n->outer;
6313 if (n == NULL)
6314 {
6315 as_bad (_("next outside of structured loop"));
6316 ignore_rest_of_line ();
6317 return;
6318 }
6319
6320 buf = (char *) xmalloc (20 + strlen (n->next));
e1f44d10 6321 ex[0] = tolower(extent);
252b5132
RH		 6322 ex[1] = '\0';
6323 sprintf (buf, "bra%s %s", ex, n->next);
6324 mri_assemble (buf);
6325 free (buf);
6326
6327 if (flag_mri)
6328 {
6329 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6330 ++input_line_pointer;
6331 }
6332
6333 demand_empty_rest_of_line ();
6334}
6335
6336/* Handle the MRI FOR pseudo-op. */
6337
6338static void
6339s_mri_for (qual)
6340 int qual;
6341{
6342 const char *varstart, *varstop;
6343 const char *initstart, *initstop;
6344 const char *endstart, *endstop;
6345 const char *bystart, *bystop;
6346 int up;
6347 int by;
6348 int extent;
6349 struct mri_control_info *n;
6350 char *buf;
6351 char *s;
6352 char ex[2];
6353
6354 /* The syntax is
6355 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6356 */
6357
6358 SKIP_WHITESPACE ();
6359 varstart = input_line_pointer;
6360
6361 /* Look for the '='. */
6362 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6363 && *input_line_pointer != '=')
6364 ++input_line_pointer;
6365 if (*input_line_pointer != '=')
6366 {
6367 as_bad (_("missing ="));
6368 ignore_rest_of_line ();
6369 return;
6370 }
6371
6372 varstop = input_line_pointer;
6373 if (varstop > varstart
6374 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6375 --varstop;
6376
6377 ++input_line_pointer;
6378
6379 initstart = input_line_pointer;
6380
6381 /* Look for TO or DOWNTO. */
6382 up = 1;
6383 initstop = NULL;
6384 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6385 {
6386 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6387 && ! is_part_of_name (input_line_pointer[2]))
6388 {
6389 initstop = input_line_pointer;
6390 input_line_pointer += 2;
6391 break;
6392 }
6393 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6394 && ! is_part_of_name (input_line_pointer[6]))
6395 {
6396 initstop = input_line_pointer;
6397 up = 0;
6398 input_line_pointer += 6;
6399 break;
6400 }
6401 ++input_line_pointer;
6402 }
6403 if (initstop == NULL)
6404 {
6405 as_bad (_("missing to or downto"));
6406 ignore_rest_of_line ();
6407 return;
6408 }
6409 if (initstop > initstart
6410 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6411 --initstop;
6412
6413 SKIP_WHITESPACE ();
6414 endstart = input_line_pointer;
6415
6416 /* Look for BY or DO. */
6417 by = 0;
6418 endstop = NULL;
6419 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6420 {
6421 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6422 && ! is_part_of_name (input_line_pointer[2]))
6423 {
6424 endstop = input_line_pointer;
6425 by = 1;
6426 input_line_pointer += 2;
6427 break;
6428 }
6429 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6430 && (input_line_pointer[2] == '.'
6431 || ! is_part_of_name (input_line_pointer[2])))
6432 {
6433 endstop = input_line_pointer;
6434 input_line_pointer += 2;
6435 break;
6436 }
6437 ++input_line_pointer;
6438 }
6439 if (endstop == NULL)
6440 {
6441 as_bad (_("missing do"));
6442 ignore_rest_of_line ();
6443 return;
6444 }
6445 if (endstop > endstart
6446 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6447 --endstop;
6448
6449 if (! by)
6450 {
6451 bystart = "#1";
6452 bystop = bystart + 2;
6453 }
6454 else
6455 {
6456 SKIP_WHITESPACE ();
6457 bystart = input_line_pointer;
6458
6459 /* Look for DO. */
6460 bystop = NULL;
6461 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6462 {
6463 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6464 && (input_line_pointer[2] == '.'
6465 || ! is_part_of_name (input_line_pointer[2])))
6466 {
6467 bystop = input_line_pointer;
6468 input_line_pointer += 2;
6469 break;
6470 }
6471 ++input_line_pointer;
6472 }
6473 if (bystop == NULL)
6474 {
6475 as_bad (_("missing do"));
6476 ignore_rest_of_line ();
6477 return;
6478 }
6479 if (bystop > bystart
6480 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6481 --bystop;
6482 }
6483
6484 if (*input_line_pointer != '.')
6485 extent = '\0';
6486 else
6487 {
6488 extent = input_line_pointer[1];
6489 input_line_pointer += 2;
6490 }
6491
6492 /* We have fully parsed the FOR operands. Now build the loop. */
6493
6494 n = push_mri_control (mri_for);
6495
6496 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6497
6498 /* move init,var */
6499 s = buf;
6500 *s++ = 'm';
6501 *s++ = 'o';
6502 *s++ = 'v';
6503 *s++ = 'e';
6504 if (qual != '\0')
e1f44d10 6505 *s++ = tolower(qual);
252b5132
RH		 6506 *s++ = ' ';
6507 memcpy (s, initstart, initstop - initstart);
6508 s += initstop - initstart;
6509 *s++ = ',';
6510 memcpy (s, varstart, varstop - varstart);
6511 s += varstop - varstart;
6512 *s = '\0';
6513 mri_assemble (buf);
6514
6515 colon (n->top);
6516
6517 /* cmp end,var */
6518 s = buf;
6519 *s++ = 'c';
6520 *s++ = 'm';
6521 *s++ = 'p';
6522 if (qual != '\0')
e1f44d10 6523 *s++ = tolower(qual);
252b5132
RH		 6524 *s++ = ' ';
6525 memcpy (s, endstart, endstop - endstart);
6526 s += endstop - endstart;
6527 *s++ = ',';
6528 memcpy (s, varstart, varstop - varstart);
6529 s += varstop - varstart;
6530 *s = '\0';
6531 mri_assemble (buf);
6532
6533 /* bcc bottom */
e1f44d10 6534 ex[0] = tolower(extent);
252b5132
RH		 6535 ex[1] = '\0';
6536 if (up)
6537 sprintf (buf, "blt%s %s", ex, n->bottom);
6538 else
6539 sprintf (buf, "bgt%s %s", ex, n->bottom);
6540 mri_assemble (buf);
6541
6542 /* Put together the add or sub instruction used by ENDF. */
6543 s = buf;
6544 if (up)
6545 strcpy (s, "add");
6546 else
6547 strcpy (s, "sub");
6548 s += 3;
6549 if (qual != '\0')
e1f44d10 6550 *s++ = tolower(qual);
252b5132
RH		 6551 *s++ = ' ';
6552 memcpy (s, bystart, bystop - bystart);
6553 s += bystop - bystart;
6554 *s++ = ',';
6555 memcpy (s, varstart, varstop - varstart);
6556 s += varstop - varstart;
6557 *s = '\0';
6558 n->incr = buf;
6559
6560 if (flag_mri)
6561 {
6562 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6563 ++input_line_pointer;
6564 }
6565
6566 demand_empty_rest_of_line ();
6567}
6568
6569/* Handle the MRI ENDF pseudo-op. */
6570
6571static void
6572s_mri_endf (ignore)
36823076 6573 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6574{
6575 if (mri_control_stack == NULL
6576 || mri_control_stack->type != mri_for)
6577 {
6578 as_bad (_("endf without for"));
6579 ignore_rest_of_line ();
6580 return;
6581 }
6582
6583 colon (mri_control_stack->next);
6584
6585 mri_assemble (mri_control_stack->incr);
6586
6587 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6588 mri_assemble (mri_control_stack->incr);
6589
6590 free (mri_control_stack->incr);
6591
6592 colon (mri_control_stack->bottom);
6593
6594 pop_mri_control ();
6595
6596 if (flag_mri)
6597 {
6598 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6599 ++input_line_pointer;
6600 }
6601
6602 demand_empty_rest_of_line ();
6603}
6604
6605/* Handle the MRI REPEAT pseudo-op. */
6606
6607static void
6608s_mri_repeat (ignore)
36823076 6609 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6610{
6611 struct mri_control_info *n;
6612
6613 n = push_mri_control (mri_repeat);
6614 colon (n->top);
6615 if (flag_mri)
6616 {
6617 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6618 ++input_line_pointer;
6619 }
6620 demand_empty_rest_of_line ();
6621}
6622
6623/* Handle the MRI UNTIL pseudo-op. */
6624
6625static void
6626s_mri_until (qual)
6627 int qual;
6628{
6629 char *s;
6630
6631 if (mri_control_stack == NULL
6632 || mri_control_stack->type != mri_repeat)
6633 {
6634 as_bad (_("until without repeat"));
6635 ignore_rest_of_line ();
6636 return;
6637 }
6638
6639 colon (mri_control_stack->next);
6640
6641 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6642 ;
6643
6644 parse_mri_control_expression (s, qual, (const char *) NULL,
6645 mri_control_stack->top, '\0');
6646
6647 colon (mri_control_stack->bottom);
6648
6649 input_line_pointer = s;
6650
6651 pop_mri_control ();
6652
6653 if (flag_mri)
6654 {
6655 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6656 ++input_line_pointer;
6657 }
6658
6659 demand_empty_rest_of_line ();
6660}
6661
6662/* Handle the MRI WHILE pseudo-op. */
6663
6664static void
6665s_mri_while (qual)
6666 int qual;
6667{
6668 char *s;
6669
6670 struct mri_control_info *n;
6671
6672 s = input_line_pointer;
e1f44d10
NC		 6673 /* We only accept '*' as introduction of comments if preceded by white space
6674 or at first column of a line (I think this can't actually happen here?)
6675 This is important when assembling:
6676 while d0 <ne> 12(a0,d0*2) do
6677 while d0 <ne> #CONST*20 do */
6678 while ( ! ( is_end_of_line[(unsigned char) *s]
6679 || ( flag_mri
6680 && *s == '*'
6681 && ( s == input_line_pointer
6682 || *(s-1) == ' '
6683 || *(s-1) == '\t'))))
252b5132
RH		 6684 s++;
6685 --s;
6686 while (*s == ' ' || *s == '\t')
6687 --s;
6688 if (s - input_line_pointer > 1
6689 && s[-1] == '.')
6690 s -= 2;
6691 if (s - input_line_pointer < 2
6692 || strncasecmp (s - 1, "DO", 2) != 0)
6693 {
6694 as_bad (_("missing do"));
6695 ignore_rest_of_line ();
6696 return;
6697 }
6698
6699 n = push_mri_control (mri_while);
6700
6701 colon (n->next);
6702
6703 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6704 s[1] == '.' ? s[2] : '\0');
6705
6706 input_line_pointer = s + 1;
6707 if (*input_line_pointer == '.')
6708 input_line_pointer += 2;
6709
6710 if (flag_mri)
6711 {
6712 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6713 ++input_line_pointer;
6714 }
6715
6716 demand_empty_rest_of_line ();
6717}
6718
6719/* Handle the MRI ENDW pseudo-op. */
6720
6721static void
6722s_mri_endw (ignore)
36823076 6723 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6724{
6725 char *buf;
6726
6727 if (mri_control_stack == NULL
6728 || mri_control_stack->type != mri_while)
6729 {
6730 as_bad (_("endw without while"));
6731 ignore_rest_of_line ();
6732 return;
6733 }
6734
6735 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6736 sprintf (buf, "bra %s", mri_control_stack->next);
6737 mri_assemble (buf);
6738 free (buf);
6739
6740 colon (mri_control_stack->bottom);
6741
6742 pop_mri_control ();
6743
6744 if (flag_mri)
6745 {
6746 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6747 ++input_line_pointer;
6748 }
6749
6750 demand_empty_rest_of_line ();
6751}
6752\f
6753/*
6754 * md_parse_option
6755 * Invocation line includes a switch not recognized by the base assembler.
6756 * See if it's a processor-specific option. These are:
6757 *
6758 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6759 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6760 * Select the architecture. Instructions or features not
6761 * supported by the selected architecture cause fatal
6762 * errors. More than one may be specified. The default is
6763 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6764 * for -m68000, and -m68882 is a synonym for -m68881.
6765 * -[A]m[c]no-68851, -[A]m[c]no-68881
6766 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6767 * so don't use or document it, but that's the way the parsing
6768 * works).
6769 *
6770 * -pic Indicates PIC.
6771 * -k Indicates PIC. (Sun 3 only.)
28e7409f 6772 * --pcrel Never turn PC-relative branches into absolute jumps.
252b5132
RH		 6773 *
6774 * --bitwise-or
6775 * Permit `|' to be used in expressions.
6776 *
6777 */
6778
6779#ifdef OBJ_ELF
6780CONST char *md_shortopts = "lSA:m:kQ:V";
6781#else
6782CONST char *md_shortopts = "lSA:m:k";
6783#endif
6784
6785struct option md_longopts[] = {
6786#define OPTION_PIC (OPTION_MD_BASE)
6787 {"pic", no_argument, NULL, OPTION_PIC},
6788#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6789 {"register-prefix-optional", no_argument, NULL,
6790 OPTION_REGISTER_PREFIX_OPTIONAL},
6791#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6792 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6793#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6794 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6795#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6796 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6797#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6798 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6799#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6800 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 6801#define OPTION_PCREL (OPTION_MD_BASE + 7)
6802 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 6803 {NULL, no_argument, NULL, 0}
6804};
bc805888 6805size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 6806
6807int
6808md_parse_option (c, arg)
6809 int c;
6810 char *arg;
6811{
6812 switch (c)
6813 {
6814 case 'l': /* -l means keep external to 2 bit offset
6815 rather than 16 bit one */
6816 flag_short_refs = 1;
6817 break;
6818
6819 case 'S': /* -S means that jbsr's always turn into
6820 jsr's. */
6821 flag_long_jumps = 1;
6822 break;
6823
28e7409f
NC		 6824 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6825 branches into absolute jumps. */
6826 flag_keep_pcrel = 1;
6827 break;
6828
252b5132
RH		 6829 case 'A':
6830 if (*arg == 'm')
6831 arg++;
6832 /* intentional fall-through */
6833 case 'm':
6834
6835 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6836 {
6837 int i;
6838 unsigned long arch;
6839 const char *oarg = arg;
6840
6841 arg += 3;
6842 if (*arg == 'm')
6843 {
6844 arg++;
6845 if (arg[0] == 'c' && arg[1] == '6')
6846 arg++;
6847 }
6848 for (i = 0; i < n_archs; i++)
6849 if (!strcmp (arg, archs[i].name))
6850 break;
6851 if (i == n_archs)
6852 {
6853 unknown:
6854 as_bad (_("unrecognized option `%s'"), oarg);
6855 return 0;
6856 }
6857 arch = archs[i].arch;
6858 if (arch == m68881)
6859 no_68881 = 1;
6860 else if (arch == m68851)
6861 no_68851 = 1;
6862 else
6863 goto unknown;
6864 }
6865 else
6866 {
6867 int i;
6868
6869 if (arg[0] == 'c' && arg[1] == '6')
6870 arg++;
6871
6872 for (i = 0; i < n_archs; i++)
6873 if (!strcmp (arg, archs[i].name))
6874 {
6875 unsigned long arch = archs[i].arch;
6876 if (cpu_of_arch (arch))
6877 /* It's a cpu spec. */
6878 {
6879 current_architecture &= ~m68000up;
6880 current_architecture |= arch;
6881 }
6882 else if (arch == m68881)
6883 {
6884 current_architecture |= m68881;
6885 no_68881 = 0;
6886 }
6887 else if (arch == m68851)
6888 {
6889 current_architecture |= m68851;
6890 no_68851 = 0;
6891 }
6892 else
6893 /* ??? */
6894 abort ();
6895 break;
6896 }
6897 if (i == n_archs)
6898 {
6899 as_bad (_("unrecognized architecture specification `%s'"), arg);
6900 return 0;
6901 }
6902 }
6903 break;
6904
6905 case OPTION_PIC:
6906 case 'k':
6907 flag_want_pic = 1;
6908 break; /* -pic, Position Independent Code */
6909
6910 case OPTION_REGISTER_PREFIX_OPTIONAL:
6911 flag_reg_prefix_optional = 1;
6912 reg_prefix_optional_seen = 1;
6913 break;
6914
6915 /* -V: SVR4 argument to print version ID. */
6916 case 'V':
6917 print_version_id ();
6918 break;
6919
6920 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6921 should be emitted or not. FIXME: Not implemented. */
6922 case 'Q':
6923 break;
6924
6925 case OPTION_BITWISE_OR:
6926 {
6927 char *n, *t;
6928 const char *s;
6929
6930 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6931 t = n;
6932 for (s = m68k_comment_chars; *s != '\0'; s++)
6933 if (*s != '|')
6934 *t++ = *s;
6935 *t = '\0';
6936 m68k_comment_chars = n;
6937 }
6938 break;
6939
6940 case OPTION_BASE_SIZE_DEFAULT_16:
6941 m68k_index_width_default = SIZE_WORD;
6942 break;
6943
6944 case OPTION_BASE_SIZE_DEFAULT_32:
6945 m68k_index_width_default = SIZE_LONG;
6946 break;
6947
6948 case OPTION_DISP_SIZE_DEFAULT_16:
6949 m68k_rel32 = 0;
6950 m68k_rel32_from_cmdline = 1;
6951 break;
6952
6953 case OPTION_DISP_SIZE_DEFAULT_32:
6954 m68k_rel32 = 1;
6955 m68k_rel32_from_cmdline = 1;
6956 break;
6957
6958 default:
6959 return 0;
6960 }
6961
6962 return 1;
6963}
6964
6965void
6966md_show_usage (stream)
6967 FILE *stream;
6968{
bc805888 6969 fprintf (stream, _("\
252b5132
RH		 6970680X0 options:\n\
6971-l use 1 word for refs to undefined symbols [default 2]\n\
98b32482
NC		 6972-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
6973-m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
6974-m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m5307 | -m5407\n\
252b5132
RH		 6975 specify variant of 680X0 architecture [default 68020]\n\
6976-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6977 target has/lacks floating-point coprocessor\n\
6978 [default yes for 68020, 68030, and cpu32]\n"));
bc805888 6979 fprintf (stream, _("\
252b5132
RH		 6980-m68851 | -mno-68851\n\
6981 target has/lacks memory-management unit coprocessor\n\
6982 [default yes for 68020 and up]\n\
6983-pic, -k generate position independent code\n\
6984-S turn jbsr into jsr\n\
28e7409f 6985--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 6986--register-prefix-optional\n\
6987 recognize register names without prefix character\n\
6988--bitwise-or do not treat `|' as a comment character\n"));
6989 fprintf (stream, _("\
6990--base-size-default-16 base reg without size is 16 bits\n\
6991--base-size-default-32 base reg without size is 32 bits (default)\n\
6992--disp-size-default-16 displacement with unknown size is 16 bits\n\
6993--disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6994}
6995\f
6996#ifdef TEST2
6997
6998/* TEST2: Test md_assemble() */
6999/* Warning, this routine probably doesn't work anymore */
7000
7001main ()
7002{
7003 struct m68k_it the_ins;
7004 char buf[120];
7005 char *cp;
7006 int n;
7007
7008 m68k_ip_begin ();
7009 for (;;)
7010 {
7011 if (!gets (buf) || !*buf)
7012 break;
7013 if (buf[0] == '|' || buf[1] == '.')
7014 continue;
7015 for (cp = buf; *cp; cp++)
7016 if (*cp == '\t')
7017 *cp = ' ';
7018 if (is_label (buf))
7019 continue;
7020 memset (&the_ins, '\0', sizeof (the_ins));
7021 m68k_ip (&the_ins, buf);
7022 if (the_ins.error)
7023 {
7024 printf (_("Error %s in %s\n"), the_ins.error, buf);
7025 }
7026 else
7027 {
7028 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7029 for (n = 0; n < the_ins.numo; n++)
7030 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7031 printf (" ");
7032 print_the_insn (&the_ins.opcode[0], stdout);
7033 (void) putchar ('\n');
7034 }
7035 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7036 {
7037 if (the_ins.operands[n].error)
7038 {
7039 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7040 continue;
7041 }
7042 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7043 if (the_ins.operands[n].b_const)
7044 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7045 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7046 if (the_ins.operands[n].b_iadd)
7047 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7048 (void) putchar ('\n');
7049 }
7050 }
7051 m68k_ip_end ();
7052 return 0;
7053}
7054
7055is_label (str)
7056 char *str;
7057{
7058 while (*str == ' ')
7059 str++;
7060 while (*str && *str != ' ')
7061 str++;
7062 if (str[-1] == ':' || str[1] == '=')
7063 return 1;
7064 return 0;
7065}
7066
7067#endif
7068
7069/* Possible states for relaxation:
7070
7071 0 0 branch offset byte (bra, etc)
7072 0 1 word
7073 0 2 long
7074
7075 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7076 1 1 word
7077 1 2 long
7078
7079 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7080 2 1 word-long
7081 2 2 long-word
7082 2 3 long-long
7083
7084 */
7085
7086/* We have no need to default values of symbols. */
7087
252b5132
RH		 7088symbolS *
7089md_undefined_symbol (name)
36823076 7090 char *name ATTRIBUTE_UNUSED;
252b5132
RH		 7091{
7092 return 0;
7093}
7094
7095/* Round up a section size to the appropriate boundary. */
7096valueT
7097md_section_align (segment, size)
36823076 7098 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7099 valueT size;
7100{
7101#ifdef OBJ_AOUT
7102#ifdef BFD_ASSEMBLER
7103 /* For a.out, force the section size to be aligned. If we don't do
7104 this, BFD will align it for us, but it will not write out the
7105 final bytes of the section. This may be a bug in BFD, but it is
7106 easier to fix it here since that is how the other a.out targets
7107 work. */
7108 int align;
7109
7110 align = bfd_get_section_alignment (stdoutput, segment);
7111 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7112#endif
7113#endif
7114
7115 return size;
7116}
7117
7118/* Exactly what point is a PC-relative offset relative TO?
7119 On the 68k, it is relative to the address of the first extension
7120 word. The difference between the addresses of the offset and the
92774660 7121 first extension word is stored in fx_pcrel_adjust. */
252b5132
RH		 7122long
7123md_pcrel_from (fixP)
7124 fixS *fixP;
7125{
7126 int adjust;
7127
8390138c
AS		 7128 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7129 sign extend the value here. */
7130 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7131 if (adjust == 64)
7132 adjust = -1;
7133 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7134}
7135
7136#ifndef BFD_ASSEMBLER
7137#ifdef OBJ_COFF
7138
252b5132
RH		 7139void
7140tc_coff_symbol_emit_hook (ignore)
8fce3f5e 7141 symbolS *ignore ATTRIBUTE_UNUSED;
252b5132
RH		 7142{
7143}
7144
7145int
7146tc_coff_sizemachdep (frag)
7147 fragS *frag;
7148{
7149 switch (frag->fr_subtype & 0x3)
7150 {
7151 case BYTE:
7152 return 1;
7153 case SHORT:
7154 return 2;
7155 case LONG:
7156 return 4;
7157 default:
7158 abort ();
7159 return 0;
7160 }
7161}
7162
7163#endif
7164#endif
0d96863f
CM		 7165#ifdef OBJ_ELF
7166void m68k_elf_final_processing()
7167{
7168 /* Set file-specific flags if this is a cpu32 processor */
7169 if (cpu_of_arch (current_architecture) & cpu32)
7170 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7171}
7172#endif
GDB Binutils - Deliverables
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