Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mcore.c -- Assemble code for M*Core |
6f2750fe | 2 | Copyright (C) 1999-2016 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
d7f1f2b0 | 17 | along with GAS; see the file COPYING. If not, write to the Free |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
252b5132 | 21 | #include "as.h" |
252b5132 RH |
22 | #include "subsegs.h" |
23 | #define DEFINE_TABLE | |
24 | #include "../opcodes/mcore-opc.h" | |
3882b010 | 25 | #include "safe-ctype.h" |
252b5132 RH |
26 | |
27 | #ifdef OBJ_ELF | |
28 | #include "elf/mcore.h" | |
29 | #endif | |
30 | ||
31 | #ifndef streq | |
32 | #define streq(a,b) (strcmp (a, b) == 0) | |
33 | #endif | |
34 | ||
35 | /* Forward declarations for dumb compilers. */ | |
252b5132 RH |
36 | |
37 | /* Several places in this file insert raw instructions into the | |
38 | object. They should use MCORE_INST_XXX macros to get the opcodes | |
39 | and then use these two macros to crack the MCORE_INST value into | |
40 | the appropriate byte values. */ | |
bec50466 NC |
41 | #define INST_BYTE0(x) (target_big_endian ? (((x) >> 8) & 0xFF) : ((x) & 0xFF)) |
42 | #define INST_BYTE1(x) (target_big_endian ? ((x) & 0xFF) : (((x) >> 8) & 0xFF)) | |
252b5132 RH |
43 | |
44 | const char comment_chars[] = "#/"; | |
45 | const char line_separator_chars[] = ";"; | |
46 | const char line_comment_chars[] = "#/"; | |
47 | ||
eaa15ab8 | 48 | static int do_jsri2bsr = 0; /* Change here from 1 by Cruess 19 August 97. */ |
252b5132 RH |
49 | static int sifilter_mode = 0; |
50 | ||
51 | const char EXP_CHARS[] = "eE"; | |
52 | ||
eaa15ab8 NC |
53 | /* Chars that mean this number is a floating point constant |
54 | As in 0f12.456 | |
55 | or 0d1.2345e12 */ | |
252b5132 RH |
56 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
57 | ||
58 | #define C(what,length) (((what) << 2) + (length)) | |
59 | #define GET_WHAT(x) ((x >> 2)) | |
60 | ||
ea1562b3 | 61 | /* These are the two types of relaxable instruction. */ |
252b5132 RH |
62 | #define COND_JUMP 1 |
63 | #define UNCD_JUMP 2 | |
64 | ||
65 | #define UNDEF_DISP 0 | |
93c2a809 AM |
66 | #define DISP12 1 |
67 | #define DISP32 2 | |
68 | #define UNDEF_WORD_DISP 3 | |
252b5132 RH |
69 | |
70 | #define C12_LEN 2 | |
ea1562b3 | 71 | #define C32_LEN 10 /* Allow for align. */ |
252b5132 | 72 | #define U12_LEN 2 |
ea1562b3 | 73 | #define U32_LEN 8 /* Allow for align. */ |
252b5132 | 74 | |
bec50466 NC |
75 | typedef enum |
76 | { | |
77 | M210, | |
78 | M340 | |
79 | } | |
80 | cpu_type; | |
81 | ||
82 | cpu_type cpu = M340; | |
252b5132 | 83 | |
eaa15ab8 | 84 | /* Initialize the relax table. */ |
ea1562b3 NC |
85 | const relax_typeS md_relax_table[] = |
86 | { | |
e66457fb AM |
87 | { 0, 0, 0, 0 }, |
88 | { 0, 0, 0, 0 }, | |
89 | { 0, 0, 0, 0 }, | |
90 | { 0, 0, 0, 0 }, | |
91 | ||
92 | /* COND_JUMP */ | |
93 | { 0, 0, 0, 0 }, /* UNDEF_DISP */ | |
94 | { 2048, -2046, C12_LEN, C(COND_JUMP, DISP32) }, /* DISP12 */ | |
95 | { 0, 0, C32_LEN, 0 }, /* DISP32 */ | |
96 | { 0, 0, C32_LEN, 0 }, /* UNDEF_WORD_DISP */ | |
97 | ||
98 | /* UNCD_JUMP */ | |
5d6255fe KH |
99 | { 0, 0, 0, 0 }, /* UNDEF_DISP */ |
100 | { 2048, -2046, U12_LEN, C(UNCD_JUMP, DISP32) }, /* DISP12 */ | |
101 | { 0, 0, U32_LEN, 0 }, /* DISP32 */ | |
e66457fb AM |
102 | { 0, 0, U32_LEN, 0 } /* UNDEF_WORD_DISP */ |
103 | ||
252b5132 RH |
104 | }; |
105 | ||
eaa15ab8 | 106 | /* Literal pool data structures. */ |
252b5132 RH |
107 | struct literal |
108 | { | |
109 | unsigned short refcnt; | |
110 | unsigned char ispcrel; | |
111 | unsigned char unused; | |
112 | expressionS e; | |
113 | }; | |
114 | ||
115 | #define MAX_POOL_SIZE (1024/4) | |
116 | static struct literal litpool [MAX_POOL_SIZE]; | |
117 | static unsigned poolsize; | |
118 | static unsigned poolnumber; | |
119 | static unsigned long poolspan; | |
120 | ||
121 | /* SPANPANIC: the point at which we get too scared and force a dump | |
122 | of the literal pool, and perhaps put a branch in place. | |
123 | Calculated as: | |
124 | 1024 span of lrw/jmpi/jsri insn (actually span+1) | |
125 | -2 possible alignment at the insn. | |
126 | -2 possible alignment to get the table aligned. | |
127 | -2 an inserted branch around the table. | |
128 | == 1018 | |
129 | at 1018, we might be in trouble. | |
130 | -- so we have to be smaller than 1018 and since we deal with 2-byte | |
131 | instructions, the next good choice is 1016. | |
132 | -- Note we have a test case that fails when we've got 1018 here. */ | |
eaa15ab8 | 133 | #define SPANPANIC (1016) /* 1024 - 1 entry - 2 byte rounding. */ |
252b5132 RH |
134 | #define SPANCLOSE (900) |
135 | #define SPANEXIT (600) | |
ea1562b3 | 136 | static symbolS * poolsym; /* Label for current pool. */ |
252b5132 | 137 | static char poolname[8]; |
eaa15ab8 | 138 | static struct hash_control * opcode_hash_control; /* Opcode mnemonics. */ |
252b5132 | 139 | |
ea1562b3 NC |
140 | #define POOL_END_LABEL ".LE" |
141 | #define POOL_START_LABEL ".LS" | |
142 | ||
143 | static void | |
e0471c16 | 144 | make_name (char * s, const char * p, int n) |
252b5132 | 145 | { |
ea1562b3 | 146 | static const char hex[] = "0123456789ABCDEF"; |
252b5132 | 147 | |
ea1562b3 NC |
148 | s[0] = p[0]; |
149 | s[1] = p[1]; | |
150 | s[2] = p[2]; | |
151 | s[3] = hex[(n >> 12) & 0xF]; | |
152 | s[4] = hex[(n >> 8) & 0xF]; | |
153 | s[5] = hex[(n >> 4) & 0xF]; | |
154 | s[6] = hex[(n) & 0xF]; | |
155 | s[7] = 0; | |
156 | } | |
252b5132 | 157 | |
ea1562b3 NC |
158 | static void |
159 | dump_literals (int isforce) | |
160 | { | |
161 | unsigned int i; | |
162 | struct literal * p; | |
163 | symbolS * brarsym = NULL; | |
a75214e5 | 164 | |
ea1562b3 NC |
165 | if (poolsize == 0) |
166 | return; | |
167 | ||
168 | /* Must we branch around the literal table? */ | |
169 | if (isforce) | |
170 | { | |
171 | char * output; | |
172 | char brarname[8]; | |
173 | ||
174 | make_name (brarname, POOL_END_LABEL, poolnumber); | |
175 | ||
176 | brarsym = symbol_make (brarname); | |
177 | ||
178 | symbol_table_insert (brarsym); | |
179 | ||
180 | output = frag_var (rs_machine_dependent, | |
181 | md_relax_table[C (UNCD_JUMP, DISP32)].rlx_length, | |
182 | md_relax_table[C (UNCD_JUMP, DISP12)].rlx_length, | |
183 | C (UNCD_JUMP, 0), brarsym, 0, 0); | |
184 | output[0] = INST_BYTE0 (MCORE_INST_BR); /* br .+xxx */ | |
185 | output[1] = INST_BYTE1 (MCORE_INST_BR); | |
186 | } | |
187 | ||
188 | /* Make sure that the section is sufficiently aligned and that | |
189 | the literal table is aligned within it. */ | |
190 | record_alignment (now_seg, 2); | |
191 | frag_align (2, 0, 0); | |
192 | ||
193 | colon (S_GET_NAME (poolsym)); | |
194 | ||
195 | for (i = 0, p = litpool; i < poolsize; i++, p++) | |
196 | emit_expr (& p->e, 4); | |
197 | ||
198 | if (brarsym != NULL) | |
199 | colon (S_GET_NAME (brarsym)); | |
200 | ||
201 | poolsize = 0; | |
202 | } | |
252b5132 RH |
203 | |
204 | static void | |
ea1562b3 | 205 | mcore_s_literals (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
206 | { |
207 | dump_literals (0); | |
208 | demand_empty_rest_of_line (); | |
209 | } | |
210 | ||
5f8075fa AM |
211 | /* Perform FUNC (ARG), and track number of bytes added to frag. */ |
212 | ||
252b5132 | 213 | static void |
ea1562b3 | 214 | mcore_pool_count (void (*func) (int), int arg) |
252b5132 | 215 | { |
5f8075fa AM |
216 | const fragS *curr_frag = frag_now; |
217 | offsetT added = -frag_now_fix_octets (); | |
a75214e5 | 218 | |
5f8075fa | 219 | (*func) (arg); |
a75214e5 | 220 | |
5f8075fa AM |
221 | while (curr_frag != frag_now) |
222 | { | |
223 | added += curr_frag->fr_fix; | |
224 | curr_frag = curr_frag->fr_next; | |
252b5132 | 225 | } |
a75214e5 | 226 | |
5f8075fa AM |
227 | added += frag_now_fix_octets (); |
228 | poolspan += added; | |
229 | } | |
230 | ||
231 | static void | |
ea1562b3 NC |
232 | check_literals (int kind, int offset) |
233 | { | |
234 | poolspan += offset; | |
235 | ||
236 | /* SPANCLOSE and SPANEXIT are smaller numbers than SPANPANIC. | |
237 | SPANPANIC means that we must dump now. | |
238 | kind == 0 is any old instruction. | |
239 | kind > 0 means we just had a control transfer instruction. | |
240 | kind == 1 means within a function | |
241 | kind == 2 means we just left a function | |
242 | ||
243 | The dump_literals (1) call inserts a branch around the table, so | |
244 | we first look to see if its a situation where we won't have to | |
245 | insert a branch (e.g., the previous instruction was an unconditional | |
246 | branch). | |
247 | ||
248 | SPANPANIC is the point where we must dump a single-entry pool. | |
249 | it accounts for alignments and an inserted branch. | |
250 | the 'poolsize*2' accounts for the scenario where we do: | |
251 | lrw r1,lit1; lrw r2,lit2; lrw r3,lit3 | |
252 | Note that the 'lit2' reference is 2 bytes further along | |
253 | but the literal it references will be 4 bytes further along, | |
254 | so we must consider the poolsize into this equation. | |
255 | This is slightly over-cautious, but guarantees that we won't | |
256 | panic because a relocation is too distant. */ | |
257 | ||
258 | if (poolspan > SPANCLOSE && kind > 0) | |
259 | dump_literals (0); | |
260 | else if (poolspan > SPANEXIT && kind > 1) | |
261 | dump_literals (0); | |
262 | else if (poolspan >= (SPANPANIC - poolsize * 2)) | |
263 | dump_literals (1); | |
264 | } | |
265 | ||
266 | static void | |
267 | mcore_cons (int nbytes) | |
5f8075fa AM |
268 | { |
269 | if (now_seg == text_section) | |
270 | mcore_pool_count (cons, nbytes); | |
271 | else | |
272 | cons (nbytes); | |
252b5132 RH |
273 | |
274 | /* In theory we ought to call check_literals (2,0) here in case | |
275 | we need to dump the literal table. We cannot do this however, | |
276 | as the directives that we are intercepting may be being used | |
277 | to build a switch table, and we must not interfere with its | |
a75214e5 | 278 | contents. Instead we cross our fingers and pray... */ |
252b5132 RH |
279 | } |
280 | ||
281 | static void | |
ea1562b3 | 282 | mcore_float_cons (int float_type) |
252b5132 RH |
283 | { |
284 | if (now_seg == text_section) | |
5f8075fa AM |
285 | mcore_pool_count (float_cons, float_type); |
286 | else | |
287 | float_cons (float_type); | |
a75214e5 | 288 | |
252b5132 RH |
289 | /* See the comment in mcore_cons () about calling check_literals. |
290 | It is unlikely that a switch table will be constructed using | |
291 | floating point values, but it is still likely that an indexed | |
292 | table of floating point constants is being created by these | |
293 | directives, so again we must not interfere with their placement. */ | |
294 | } | |
295 | ||
296 | static void | |
ea1562b3 | 297 | mcore_stringer (int append_zero) |
252b5132 RH |
298 | { |
299 | if (now_seg == text_section) | |
5f8075fa AM |
300 | mcore_pool_count (stringer, append_zero); |
301 | else | |
302 | stringer (append_zero); | |
252b5132 RH |
303 | |
304 | /* We call check_literals here in case a large number of strings are | |
305 | being placed into the text section with a sequence of stringer | |
306 | directives. In theory we could be upsetting something if these | |
307 | strings are actually in an indexed table instead of referenced by | |
308 | individual labels. Let us hope that that never happens. */ | |
309 | check_literals (2, 0); | |
310 | } | |
311 | ||
bcef92fa | 312 | static void |
ea1562b3 | 313 | mcore_fill (int unused) |
bcef92fa NC |
314 | { |
315 | if (now_seg == text_section) | |
5f8075fa AM |
316 | mcore_pool_count (s_fill, unused); |
317 | else | |
318 | s_fill (unused); | |
bcef92fa | 319 | |
4c1102fd | 320 | check_literals (2, 0); |
bcef92fa NC |
321 | } |
322 | ||
16b93d88 NC |
323 | /* Handle the section changing pseudo-ops. These call through to the |
324 | normal implementations, but they dump the literal pool first. */ | |
ea1562b3 | 325 | |
252b5132 | 326 | static void |
ea1562b3 | 327 | mcore_s_text (int ignore) |
252b5132 RH |
328 | { |
329 | dump_literals (0); | |
a75214e5 | 330 | |
16b93d88 NC |
331 | #ifdef OBJ_ELF |
332 | obj_elf_text (ignore); | |
333 | #else | |
252b5132 | 334 | s_text (ignore); |
16b93d88 | 335 | #endif |
252b5132 RH |
336 | } |
337 | ||
338 | static void | |
ea1562b3 | 339 | mcore_s_data (int ignore) |
252b5132 RH |
340 | { |
341 | dump_literals (0); | |
a75214e5 | 342 | |
16b93d88 NC |
343 | #ifdef OBJ_ELF |
344 | obj_elf_data (ignore); | |
345 | #else | |
252b5132 | 346 | s_data (ignore); |
16b93d88 NC |
347 | #endif |
348 | } | |
349 | ||
350 | static void | |
ea1562b3 | 351 | mcore_s_section (int ignore) |
16b93d88 | 352 | { |
bcef92fa NC |
353 | /* Scan forwards to find the name of the section. If the section |
354 | being switched to is ".line" then this is a DWARF1 debug section | |
67c1ffbe | 355 | which is arbitrarily placed inside generated code. In this case |
bcef92fa NC |
356 | do not dump the literal pool because it is a) inefficient and |
357 | b) would require the generation of extra code to jump around the | |
358 | pool. */ | |
359 | char * ilp = input_line_pointer; | |
360 | ||
3882b010 | 361 | while (*ilp != 0 && ISSPACE (*ilp)) |
bcef92fa NC |
362 | ++ ilp; |
363 | ||
364 | if (strncmp (ilp, ".line", 5) == 0 | |
3882b010 | 365 | && (ISSPACE (ilp[5]) || *ilp == '\n' || *ilp == '\r')) |
bcef92fa NC |
366 | ; |
367 | else | |
368 | dump_literals (0); | |
16b93d88 NC |
369 | |
370 | #ifdef OBJ_ELF | |
371 | obj_elf_section (ignore); | |
372 | #endif | |
373 | #ifdef OBJ_COFF | |
374 | obj_coff_section (ignore); | |
375 | #endif | |
252b5132 RH |
376 | } |
377 | ||
16b93d88 | 378 | static void |
ea1562b3 | 379 | mcore_s_bss (int needs_align) |
16b93d88 NC |
380 | { |
381 | dump_literals (0); | |
a75214e5 | 382 | |
16b93d88 NC |
383 | s_lcomm_bytes (needs_align); |
384 | } | |
385 | ||
386 | #ifdef OBJ_ELF | |
387 | static void | |
ea1562b3 | 388 | mcore_s_comm (int needs_align) |
16b93d88 NC |
389 | { |
390 | dump_literals (0); | |
a75214e5 | 391 | |
16b93d88 NC |
392 | obj_elf_common (needs_align); |
393 | } | |
394 | #endif | |
395 | ||
ea1562b3 NC |
396 | /* This table describes all the machine specific pseudo-ops the assembler |
397 | has to support. The fields are: | |
398 | Pseudo-op name without dot | |
399 | Function to call to execute this pseudo-op | |
400 | Integer arg to pass to the function. */ | |
401 | const pseudo_typeS md_pseudo_table[] = | |
402 | { | |
403 | { "export", s_globl, 0 }, | |
404 | { "import", s_ignore, 0 }, | |
405 | { "literals", mcore_s_literals, 0 }, | |
406 | { "page", listing_eject, 0 }, | |
407 | ||
408 | /* The following are to intercept the placement of data into the text | |
409 | section (eg addresses for a switch table), so that the space they | |
410 | occupy can be taken into account when deciding whether or not to | |
411 | dump the current literal pool. | |
412 | XXX - currently we do not cope with the .space and .dcb.d directives. */ | |
38a57ae7 NC |
413 | { "ascii", mcore_stringer, 8 + 0 }, |
414 | { "asciz", mcore_stringer, 8 + 1 }, | |
ea1562b3 NC |
415 | { "byte", mcore_cons, 1 }, |
416 | { "dc", mcore_cons, 2 }, | |
417 | { "dc.b", mcore_cons, 1 }, | |
418 | { "dc.d", mcore_float_cons, 'd'}, | |
419 | { "dc.l", mcore_cons, 4 }, | |
420 | { "dc.s", mcore_float_cons, 'f'}, | |
421 | { "dc.w", mcore_cons, 2 }, | |
422 | { "dc.x", mcore_float_cons, 'x'}, | |
423 | { "double", mcore_float_cons, 'd'}, | |
424 | { "float", mcore_float_cons, 'f'}, | |
425 | { "hword", mcore_cons, 2 }, | |
426 | { "int", mcore_cons, 4 }, | |
427 | { "long", mcore_cons, 4 }, | |
428 | { "octa", mcore_cons, 16 }, | |
429 | { "quad", mcore_cons, 8 }, | |
430 | { "short", mcore_cons, 2 }, | |
431 | { "single", mcore_float_cons, 'f'}, | |
38a57ae7 | 432 | { "string", mcore_stringer, 8 + 1 }, |
ea1562b3 NC |
433 | { "word", mcore_cons, 2 }, |
434 | { "fill", mcore_fill, 0 }, | |
435 | ||
436 | /* Allow for the effect of section changes. */ | |
437 | { "text", mcore_s_text, 0 }, | |
438 | { "data", mcore_s_data, 0 }, | |
439 | { "bss", mcore_s_bss, 1 }, | |
440 | #ifdef OBJ_ELF | |
441 | { "comm", mcore_s_comm, 0 }, | |
442 | #endif | |
443 | { "section", mcore_s_section, 0 }, | |
444 | { "section.s", mcore_s_section, 0 }, | |
445 | { "sect", mcore_s_section, 0 }, | |
446 | { "sect.s", mcore_s_section, 0 }, | |
447 | ||
448 | { 0, 0, 0 } | |
449 | }; | |
450 | ||
252b5132 | 451 | /* This function is called once, at assembler startup time. This should |
bcef92fa | 452 | set up all the tables, etc that the MD part of the assembler needs. */ |
ea1562b3 | 453 | |
252b5132 | 454 | void |
ea1562b3 | 455 | md_begin (void) |
252b5132 | 456 | { |
5ff37431 | 457 | const mcore_opcode_info * opcode; |
e0471c16 | 458 | const char * prev_name = ""; |
252b5132 RH |
459 | |
460 | opcode_hash_control = hash_new (); | |
461 | ||
ea1562b3 | 462 | /* Insert unique names into hash table. */ |
252b5132 RH |
463 | for (opcode = mcore_table; opcode->name; opcode ++) |
464 | { | |
5ff37431 | 465 | if (! streq (prev_name, opcode->name)) |
252b5132 RH |
466 | { |
467 | prev_name = opcode->name; | |
468 | hash_insert (opcode_hash_control, opcode->name, (char *) opcode); | |
469 | } | |
470 | } | |
471 | } | |
472 | ||
252b5132 | 473 | /* Get a log2(val). */ |
ea1562b3 | 474 | |
252b5132 | 475 | static int |
ea1562b3 | 476 | mylog2 (unsigned int val) |
252b5132 | 477 | { |
ea1562b3 NC |
478 | int log = -1; |
479 | ||
480 | while (val != 0) | |
252b5132 | 481 | { |
5f8075fa AM |
482 | log ++; |
483 | val >>= 1; | |
252b5132 | 484 | } |
a75214e5 | 485 | |
ea1562b3 | 486 | return log; |
252b5132 RH |
487 | } |
488 | ||
489 | /* Try to parse a reg name. */ | |
ea1562b3 | 490 | |
252b5132 | 491 | static char * |
ea1562b3 | 492 | parse_reg (char * s, unsigned * reg) |
252b5132 RH |
493 | { |
494 | /* Strip leading whitespace. */ | |
3882b010 | 495 | while (ISSPACE (* s)) |
252b5132 | 496 | ++ s; |
a75214e5 | 497 | |
3882b010 | 498 | if (TOLOWER (s[0]) == 'r') |
252b5132 RH |
499 | { |
500 | if (s[1] == '1' && s[2] >= '0' && s[2] <= '5') | |
501 | { | |
502 | *reg = 10 + s[2] - '0'; | |
503 | return s + 3; | |
504 | } | |
a75214e5 | 505 | |
252b5132 RH |
506 | if (s[1] >= '0' && s[1] <= '9') |
507 | { | |
508 | *reg = s[1] - '0'; | |
509 | return s + 2; | |
510 | } | |
511 | } | |
3882b010 L |
512 | else if ( TOLOWER (s[0]) == 's' |
513 | && TOLOWER (s[1]) == 'p' | |
514 | && ! ISALNUM (s[2])) | |
252b5132 RH |
515 | { |
516 | * reg = 0; | |
517 | return s + 2; | |
518 | } | |
a75214e5 | 519 | |
252b5132 RH |
520 | as_bad (_("register expected, but saw '%.6s'"), s); |
521 | return s; | |
522 | } | |
523 | ||
524 | static struct Cregs | |
525 | { | |
e0471c16 | 526 | const char * name; |
252b5132 RH |
527 | unsigned int crnum; |
528 | } | |
529 | cregs[] = | |
530 | { | |
531 | { "psr", 0}, | |
532 | { "vbr", 1}, | |
533 | { "epsr", 2}, | |
534 | { "fpsr", 3}, | |
535 | { "epc", 4}, | |
536 | { "fpc", 5}, | |
537 | { "ss0", 6}, | |
538 | { "ss1", 7}, | |
539 | { "ss2", 8}, | |
540 | { "ss3", 9}, | |
541 | { "ss4", 10}, | |
542 | { "gcr", 11}, | |
543 | { "gsr", 12}, | |
544 | { "", 0} | |
545 | }; | |
546 | ||
547 | static char * | |
ea1562b3 | 548 | parse_creg (char * s, unsigned * reg) |
252b5132 RH |
549 | { |
550 | int i; | |
551 | ||
552 | /* Strip leading whitespace. */ | |
3882b010 | 553 | while (ISSPACE (* s)) |
252b5132 | 554 | ++s; |
a75214e5 | 555 | |
3882b010 | 556 | if ((TOLOWER (s[0]) == 'c' && TOLOWER (s[1]) == 'r')) |
252b5132 RH |
557 | { |
558 | if (s[2] == '3' && s[3] >= '0' && s[3] <= '1') | |
559 | { | |
560 | *reg = 30 + s[3] - '0'; | |
561 | return s + 4; | |
562 | } | |
a75214e5 | 563 | |
252b5132 RH |
564 | if (s[2] == '2' && s[3] >= '0' && s[3] <= '9') |
565 | { | |
566 | *reg = 20 + s[3] - '0'; | |
567 | return s + 4; | |
568 | } | |
a75214e5 | 569 | |
252b5132 RH |
570 | if (s[2] == '1' && s[3] >= '0' && s[3] <= '9') |
571 | { | |
572 | *reg = 10 + s[3] - '0'; | |
573 | return s + 4; | |
574 | } | |
a75214e5 | 575 | |
252b5132 RH |
576 | if (s[2] >= '0' && s[2] <= '9') |
577 | { | |
578 | *reg = s[2] - '0'; | |
579 | return s + 3; | |
580 | } | |
581 | } | |
a75214e5 | 582 | |
252b5132 RH |
583 | /* Look at alternate creg names before giving error. */ |
584 | for (i = 0; cregs[i].name[0] != '\0'; i++) | |
585 | { | |
586 | char buf [10]; | |
587 | int length; | |
588 | int j; | |
a75214e5 | 589 | |
252b5132 | 590 | length = strlen (cregs[i].name); |
a75214e5 | 591 | |
252b5132 | 592 | for (j = 0; j < length; j++) |
3882b010 | 593 | buf[j] = TOLOWER (s[j]); |
a75214e5 | 594 | |
252b5132 RH |
595 | if (strncmp (cregs[i].name, buf, length) == 0) |
596 | { | |
597 | *reg = cregs[i].crnum; | |
598 | return s + length; | |
599 | } | |
600 | } | |
a75214e5 | 601 | |
252b5132 | 602 | as_bad (_("control register expected, but saw '%.6s'"), s); |
a75214e5 | 603 | |
252b5132 RH |
604 | return s; |
605 | } | |
606 | ||
bec50466 | 607 | static char * |
ea1562b3 | 608 | parse_psrmod (char * s, unsigned * reg) |
bec50466 NC |
609 | { |
610 | int i; | |
611 | char buf[10]; | |
612 | static struct psrmods | |
613 | { | |
e0471c16 | 614 | const char * name; |
bec50466 NC |
615 | unsigned int value; |
616 | } | |
617 | psrmods[] = | |
618 | { | |
619 | { "ie", 1 }, | |
620 | { "fe", 2 }, | |
621 | { "ee", 4 }, | |
622 | { "af", 8 } /* Really 0 and non-combinable. */ | |
623 | }; | |
a75214e5 | 624 | |
bec50466 | 625 | for (i = 0; i < 2; i++) |
3882b010 | 626 | buf[i] = TOLOWER (s[i]); |
a75214e5 | 627 | |
bec50466 NC |
628 | for (i = sizeof (psrmods) / sizeof (psrmods[0]); i--;) |
629 | { | |
630 | if (! strncmp (psrmods[i].name, buf, 2)) | |
631 | { | |
5f8075fa | 632 | * reg = psrmods[i].value; |
a75214e5 | 633 | |
5f8075fa | 634 | return s + 2; |
bec50466 NC |
635 | } |
636 | } | |
a75214e5 | 637 | |
bec50466 | 638 | as_bad (_("bad/missing psr specifier")); |
a75214e5 | 639 | |
bec50466 | 640 | * reg = 0; |
a75214e5 | 641 | |
bec50466 NC |
642 | return s; |
643 | } | |
644 | ||
252b5132 | 645 | static char * |
ea1562b3 | 646 | parse_exp (char * s, expressionS * e) |
252b5132 RH |
647 | { |
648 | char * save; | |
d3ce72d0 | 649 | char * new_pointer; |
252b5132 RH |
650 | |
651 | /* Skip whitespace. */ | |
3882b010 | 652 | while (ISSPACE (* s)) |
252b5132 | 653 | ++ s; |
a75214e5 | 654 | |
252b5132 RH |
655 | save = input_line_pointer; |
656 | input_line_pointer = s; | |
657 | ||
658 | expression (e); | |
a75214e5 | 659 | |
252b5132 RH |
660 | if (e->X_op == O_absent) |
661 | as_bad (_("missing operand")); | |
a75214e5 | 662 | |
d3ce72d0 | 663 | new_pointer = input_line_pointer; |
252b5132 | 664 | input_line_pointer = save; |
a75214e5 | 665 | |
d3ce72d0 | 666 | return new_pointer; |
252b5132 RH |
667 | } |
668 | ||
252b5132 | 669 | static int |
ea1562b3 | 670 | enter_literal (expressionS * e, int ispcrel) |
252b5132 | 671 | { |
aa699a2c | 672 | unsigned int i; |
252b5132 RH |
673 | struct literal * p; |
674 | ||
675 | if (poolsize >= MAX_POOL_SIZE - 2) | |
ea1562b3 NC |
676 | /* The literal pool is as full as we can handle. We have |
677 | to be 2 entries shy of the 1024/4=256 entries because we | |
678 | have to allow for the branch (2 bytes) and the alignment | |
679 | (2 bytes before the first insn referencing the pool and | |
680 | 2 bytes before the pool itself) == 6 bytes, rounds up | |
681 | to 2 entries. */ | |
682 | dump_literals (1); | |
252b5132 RH |
683 | |
684 | if (poolsize == 0) | |
685 | { | |
686 | /* Create new literal pool. */ | |
687 | if (++ poolnumber > 0xFFFF) | |
688 | as_fatal (_("more than 65K literal pools")); | |
a75214e5 | 689 | |
b8a40f53 | 690 | make_name (poolname, POOL_START_LABEL, poolnumber); |
252b5132 RH |
691 | poolsym = symbol_make (poolname); |
692 | symbol_table_insert (poolsym); | |
693 | poolspan = 0; | |
694 | } | |
a75214e5 | 695 | |
252b5132 RH |
696 | /* Search pool for value so we don't have duplicates. */ |
697 | for (p = litpool, i = 0; i < poolsize; i++, p++) | |
698 | { | |
699 | if (e->X_op == p->e.X_op | |
700 | && e->X_add_symbol == p->e.X_add_symbol | |
701 | && e->X_add_number == p->e.X_add_number | |
702 | && ispcrel == p->ispcrel) | |
703 | { | |
704 | p->refcnt ++; | |
705 | return i; | |
706 | } | |
707 | } | |
708 | ||
709 | p->refcnt = 1; | |
710 | p->ispcrel = ispcrel; | |
711 | p->e = * e; | |
a75214e5 | 712 | |
252b5132 RH |
713 | poolsize ++; |
714 | ||
a75214e5 | 715 | return i; |
252b5132 RH |
716 | } |
717 | ||
718 | /* Parse a literal specification. -- either new or old syntax. | |
719 | old syntax: the user supplies the label and places the literal. | |
720 | new syntax: we put it into the literal pool. */ | |
ea1562b3 | 721 | |
252b5132 | 722 | static char * |
ea1562b3 NC |
723 | parse_rt (char * s, |
724 | char ** outputp, | |
725 | int ispcrel, | |
726 | expressionS * ep) | |
252b5132 RH |
727 | { |
728 | expressionS e; | |
729 | int n; | |
a75214e5 | 730 | |
252b5132 RH |
731 | if (ep) |
732 | /* Indicate nothing there. */ | |
733 | ep->X_op = O_absent; | |
a75214e5 | 734 | |
252b5132 RH |
735 | if (*s == '[') |
736 | { | |
737 | s = parse_exp (s + 1, & e); | |
a75214e5 | 738 | |
252b5132 RH |
739 | if (*s == ']') |
740 | s++; | |
741 | else | |
742 | as_bad (_("missing ']'")); | |
743 | } | |
744 | else | |
745 | { | |
746 | s = parse_exp (s, & e); | |
a75214e5 | 747 | |
252b5132 | 748 | n = enter_literal (& e, ispcrel); |
a75214e5 | 749 | |
252b5132 RH |
750 | if (ep) |
751 | *ep = e; | |
752 | ||
753 | /* Create a reference to pool entry. */ | |
754 | e.X_op = O_symbol; | |
755 | e.X_add_symbol = poolsym; | |
756 | e.X_add_number = n << 2; | |
757 | } | |
a75214e5 | 758 | |
252b5132 RH |
759 | * outputp = frag_more (2); |
760 | ||
761 | fix_new_exp (frag_now, (*outputp) - frag_now->fr_literal, 2, & e, 1, | |
762 | BFD_RELOC_MCORE_PCREL_IMM8BY4); | |
763 | ||
764 | return s; | |
765 | } | |
766 | ||
767 | static char * | |
ea1562b3 NC |
768 | parse_imm (char * s, |
769 | unsigned * val, | |
770 | unsigned min, | |
771 | unsigned max) | |
252b5132 | 772 | { |
d3ce72d0 | 773 | char * new_pointer; |
252b5132 | 774 | expressionS e; |
a75214e5 | 775 | |
d3ce72d0 | 776 | new_pointer = parse_exp (s, & e); |
a75214e5 | 777 | |
252b5132 RH |
778 | if (e.X_op == O_absent) |
779 | ; /* An error message has already been emitted. */ | |
780 | else if (e.X_op != O_constant) | |
781 | as_bad (_("operand must be a constant")); | |
aa699a2c AM |
782 | else if ((addressT) e.X_add_number < min || (addressT) e.X_add_number > max) |
783 | as_bad (_("operand must be absolute in range %u..%u, not %ld"), | |
784 | min, max, (long) e.X_add_number); | |
252b5132 RH |
785 | |
786 | * val = e.X_add_number; | |
a75214e5 | 787 | |
d3ce72d0 | 788 | return new_pointer; |
252b5132 RH |
789 | } |
790 | ||
791 | static char * | |
ea1562b3 NC |
792 | parse_mem (char * s, |
793 | unsigned * reg, | |
794 | unsigned * off, | |
795 | unsigned siz) | |
252b5132 | 796 | { |
252b5132 | 797 | * off = 0; |
a75214e5 | 798 | |
3882b010 | 799 | while (ISSPACE (* s)) |
252b5132 | 800 | ++ s; |
a75214e5 | 801 | |
252b5132 RH |
802 | if (* s == '(') |
803 | { | |
804 | s = parse_reg (s + 1, reg); | |
805 | ||
3882b010 | 806 | while (ISSPACE (* s)) |
252b5132 | 807 | ++ s; |
a75214e5 | 808 | |
252b5132 RH |
809 | if (* s == ',') |
810 | { | |
811 | s = parse_imm (s + 1, off, 0, 63); | |
a75214e5 | 812 | |
252b5132 RH |
813 | if (siz > 1) |
814 | { | |
815 | if (siz > 2) | |
816 | { | |
817 | if (* off & 0x3) | |
818 | as_bad (_("operand must be a multiple of 4")); | |
a75214e5 | 819 | |
252b5132 RH |
820 | * off >>= 2; |
821 | } | |
822 | else | |
823 | { | |
824 | if (* off & 0x1) | |
825 | as_bad (_("operand must be a multiple of 2")); | |
a75214e5 | 826 | |
252b5132 RH |
827 | * off >>= 1; |
828 | } | |
829 | } | |
830 | } | |
a75214e5 | 831 | |
3882b010 | 832 | while (ISSPACE (* s)) |
252b5132 | 833 | ++ s; |
a75214e5 | 834 | |
252b5132 RH |
835 | if (* s == ')') |
836 | s ++; | |
837 | } | |
838 | else | |
839 | as_bad (_("base register expected")); | |
a75214e5 | 840 | |
252b5132 RH |
841 | return s; |
842 | } | |
843 | ||
844 | /* This is the guts of the machine-dependent assembler. STR points to a | |
845 | machine dependent instruction. This function is supposed to emit | |
846 | the frags/bytes it assembles to. */ | |
847 | ||
848 | void | |
ea1562b3 | 849 | md_assemble (char * str) |
252b5132 RH |
850 | { |
851 | char * op_start; | |
852 | char * op_end; | |
853 | mcore_opcode_info * opcode; | |
854 | char * output; | |
855 | int nlen = 0; | |
856 | unsigned short inst; | |
857 | unsigned reg; | |
858 | unsigned off; | |
859 | unsigned isize; | |
860 | expressionS e; | |
34857dd6 | 861 | char name[21]; |
252b5132 RH |
862 | |
863 | /* Drop leading whitespace. */ | |
3882b010 | 864 | while (ISSPACE (* str)) |
252b5132 RH |
865 | str ++; |
866 | ||
867 | /* Find the op code end. */ | |
868 | for (op_start = op_end = str; | |
b75c0c92 | 869 | nlen < 20 && !is_end_of_line [(unsigned char) *op_end] && *op_end != ' '; |
252b5132 RH |
870 | op_end++) |
871 | { | |
872 | name[nlen] = op_start[nlen]; | |
873 | nlen++; | |
874 | } | |
a75214e5 | 875 | |
252b5132 | 876 | name [nlen] = 0; |
a75214e5 | 877 | |
252b5132 RH |
878 | if (nlen == 0) |
879 | { | |
880 | as_bad (_("can't find opcode ")); | |
881 | return; | |
882 | } | |
883 | ||
884 | opcode = (mcore_opcode_info *) hash_find (opcode_hash_control, name); | |
885 | if (opcode == NULL) | |
886 | { | |
887 | as_bad (_("unknown opcode \"%s\""), name); | |
888 | return; | |
889 | } | |
a75214e5 | 890 | |
252b5132 RH |
891 | inst = opcode->inst; |
892 | isize = 2; | |
a75214e5 | 893 | |
252b5132 RH |
894 | switch (opcode->opclass) |
895 | { | |
896 | case O0: | |
897 | output = frag_more (2); | |
898 | break; | |
a75214e5 | 899 | |
252b5132 RH |
900 | case OT: |
901 | op_end = parse_imm (op_end + 1, & reg, 0, 3); | |
902 | inst |= reg; | |
903 | output = frag_more (2); | |
904 | break; | |
a75214e5 | 905 | |
252b5132 RH |
906 | case O1: |
907 | op_end = parse_reg (op_end + 1, & reg); | |
908 | inst |= reg; | |
909 | output = frag_more (2); | |
910 | break; | |
a75214e5 | 911 | |
252b5132 RH |
912 | case JMP: |
913 | op_end = parse_reg (op_end + 1, & reg); | |
914 | inst |= reg; | |
915 | output = frag_more (2); | |
916 | /* In a sifilter mode, we emit this insn 2 times, | |
5f8075fa | 917 | fixes problem of an interrupt during a jmp.. */ |
252b5132 RH |
918 | if (sifilter_mode) |
919 | { | |
b8a40f53 NC |
920 | output[0] = INST_BYTE0 (inst); |
921 | output[1] = INST_BYTE1 (inst); | |
252b5132 RH |
922 | output = frag_more (2); |
923 | } | |
924 | break; | |
a75214e5 | 925 | |
252b5132 RH |
926 | case JSR: |
927 | op_end = parse_reg (op_end + 1, & reg); | |
a75214e5 | 928 | |
252b5132 RH |
929 | if (reg == 15) |
930 | as_bad (_("invalid register: r15 illegal")); | |
a75214e5 | 931 | |
252b5132 RH |
932 | inst |= reg; |
933 | output = frag_more (2); | |
a75214e5 | 934 | |
252b5132 RH |
935 | if (sifilter_mode) |
936 | { | |
ea1562b3 NC |
937 | /* Replace with: bsr .+2 ; addi r15,6; jmp rx ; jmp rx. */ |
938 | inst = MCORE_INST_BSR; /* With 0 displacement. */ | |
b8a40f53 NC |
939 | output[0] = INST_BYTE0 (inst); |
940 | output[1] = INST_BYTE1 (inst); | |
252b5132 RH |
941 | |
942 | output = frag_more (2); | |
943 | inst = MCORE_INST_ADDI; | |
ea1562b3 NC |
944 | inst |= 15; /* addi r15,6 */ |
945 | inst |= (6 - 1) << 4; /* Over the jmp's. */ | |
b8a40f53 NC |
946 | output[0] = INST_BYTE0 (inst); |
947 | output[1] = INST_BYTE1 (inst); | |
252b5132 RH |
948 | |
949 | output = frag_more (2); | |
950 | inst = MCORE_INST_JMP | reg; | |
b8a40f53 NC |
951 | output[0] = INST_BYTE0 (inst); |
952 | output[1] = INST_BYTE1 (inst); | |
252b5132 | 953 | |
ea1562b3 NC |
954 | /* 2nd emitted in fallthrough. */ |
955 | output = frag_more (2); | |
252b5132 RH |
956 | } |
957 | break; | |
a75214e5 | 958 | |
252b5132 RH |
959 | case OC: |
960 | op_end = parse_reg (op_end + 1, & reg); | |
961 | inst |= reg; | |
a75214e5 | 962 | |
252b5132 | 963 | /* Skip whitespace. */ |
3882b010 | 964 | while (ISSPACE (* op_end)) |
252b5132 | 965 | ++ op_end; |
a75214e5 | 966 | |
252b5132 RH |
967 | if (*op_end == ',') |
968 | { | |
969 | op_end = parse_creg (op_end + 1, & reg); | |
970 | inst |= reg << 4; | |
971 | } | |
a75214e5 | 972 | |
252b5132 RH |
973 | output = frag_more (2); |
974 | break; | |
975 | ||
bec50466 NC |
976 | case MULSH: |
977 | if (cpu == M210) | |
978 | { | |
979 | as_bad (_("M340 specific opcode used when assembling for M210")); | |
980 | break; | |
981 | } | |
a75214e5 | 982 | /* drop through... */ |
252b5132 RH |
983 | case O2: |
984 | op_end = parse_reg (op_end + 1, & reg); | |
985 | inst |= reg; | |
a75214e5 | 986 | |
252b5132 | 987 | /* Skip whitespace. */ |
3882b010 | 988 | while (ISSPACE (* op_end)) |
252b5132 | 989 | ++ op_end; |
a75214e5 | 990 | |
252b5132 RH |
991 | if (* op_end == ',') |
992 | { | |
993 | op_end = parse_reg (op_end + 1, & reg); | |
994 | inst |= reg << 4; | |
995 | } | |
996 | else | |
997 | as_bad (_("second operand missing")); | |
a75214e5 | 998 | |
252b5132 RH |
999 | output = frag_more (2); |
1000 | break; | |
a75214e5 | 1001 | |
ea1562b3 NC |
1002 | case X1: |
1003 | /* Handle both syntax-> xtrb- r1,rx OR xtrb- rx. */ | |
252b5132 | 1004 | op_end = parse_reg (op_end + 1, & reg); |
a75214e5 | 1005 | |
252b5132 | 1006 | /* Skip whitespace. */ |
3882b010 | 1007 | while (ISSPACE (* op_end)) |
252b5132 | 1008 | ++ op_end; |
a75214e5 | 1009 | |
ea1562b3 | 1010 | if (* op_end == ',') /* xtrb- r1,rx. */ |
252b5132 RH |
1011 | { |
1012 | if (reg != 1) | |
1013 | as_bad (_("destination register must be r1")); | |
a75214e5 | 1014 | |
252b5132 RH |
1015 | op_end = parse_reg (op_end + 1, & reg); |
1016 | } | |
a75214e5 | 1017 | |
252b5132 RH |
1018 | inst |= reg; |
1019 | output = frag_more (2); | |
1020 | break; | |
a75214e5 | 1021 | |
ea1562b3 | 1022 | case O1R1: /* div- rx,r1. */ |
252b5132 RH |
1023 | op_end = parse_reg (op_end + 1, & reg); |
1024 | inst |= reg; | |
a75214e5 | 1025 | |
252b5132 | 1026 | /* Skip whitespace. */ |
3882b010 | 1027 | while (ISSPACE (* op_end)) |
252b5132 | 1028 | ++ op_end; |
a75214e5 | 1029 | |
252b5132 RH |
1030 | if (* op_end == ',') |
1031 | { | |
1032 | op_end = parse_reg (op_end + 1, & reg); | |
1033 | if (reg != 1) | |
1034 | as_bad (_("source register must be r1")); | |
1035 | } | |
1036 | else | |
1037 | as_bad (_("second operand missing")); | |
a75214e5 | 1038 | |
252b5132 RH |
1039 | output = frag_more (2); |
1040 | break; | |
a75214e5 | 1041 | |
252b5132 RH |
1042 | case OI: |
1043 | op_end = parse_reg (op_end + 1, & reg); | |
1044 | inst |= reg; | |
a75214e5 | 1045 | |
252b5132 | 1046 | /* Skip whitespace. */ |
3882b010 | 1047 | while (ISSPACE (* op_end)) |
252b5132 | 1048 | ++ op_end; |
a75214e5 | 1049 | |
252b5132 RH |
1050 | if (* op_end == ',') |
1051 | { | |
1052 | op_end = parse_imm (op_end + 1, & reg, 1, 32); | |
1053 | inst |= (reg - 1) << 4; | |
1054 | } | |
1055 | else | |
1056 | as_bad (_("second operand missing")); | |
a75214e5 | 1057 | |
252b5132 RH |
1058 | output = frag_more (2); |
1059 | break; | |
a75214e5 | 1060 | |
252b5132 RH |
1061 | case OB: |
1062 | op_end = parse_reg (op_end + 1, & reg); | |
1063 | inst |= reg; | |
a75214e5 | 1064 | |
252b5132 | 1065 | /* Skip whitespace. */ |
3882b010 | 1066 | while (ISSPACE (* op_end)) |
252b5132 | 1067 | ++ op_end; |
a75214e5 | 1068 | |
252b5132 RH |
1069 | if (* op_end == ',') |
1070 | { | |
1071 | op_end = parse_imm (op_end + 1, & reg, 0, 31); | |
1072 | inst |= reg << 4; | |
1073 | } | |
1074 | else | |
1075 | as_bad (_("second operand missing")); | |
a75214e5 | 1076 | |
252b5132 RH |
1077 | output = frag_more (2); |
1078 | break; | |
a75214e5 | 1079 | |
ea1562b3 NC |
1080 | case OB2: |
1081 | /* Like OB, but arg is 2^n instead of n. */ | |
252b5132 RH |
1082 | op_end = parse_reg (op_end + 1, & reg); |
1083 | inst |= reg; | |
a75214e5 | 1084 | |
252b5132 | 1085 | /* Skip whitespace. */ |
3882b010 | 1086 | while (ISSPACE (* op_end)) |
252b5132 | 1087 | ++ op_end; |
a75214e5 | 1088 | |
252b5132 RH |
1089 | if (* op_end == ',') |
1090 | { | |
1091 | op_end = parse_imm (op_end + 1, & reg, 1, 1 << 31); | |
a75214e5 | 1092 | /* Further restrict the immediate to a power of two. */ |
252b5132 | 1093 | if ((reg & (reg - 1)) == 0) |
f17c130b | 1094 | reg = mylog2 (reg); |
252b5132 RH |
1095 | else |
1096 | { | |
1097 | reg = 0; | |
1098 | as_bad (_("immediate is not a power of two")); | |
1099 | } | |
1100 | inst |= (reg) << 4; | |
1101 | } | |
1102 | else | |
1103 | as_bad (_("second operand missing")); | |
a75214e5 | 1104 | |
252b5132 RH |
1105 | output = frag_more (2); |
1106 | break; | |
a75214e5 KH |
1107 | |
1108 | case OBRa: /* Specific for bgeni: imm of 0->6 translate to movi. */ | |
252b5132 RH |
1109 | case OBRb: |
1110 | case OBRc: | |
1111 | op_end = parse_reg (op_end + 1, & reg); | |
1112 | inst |= reg; | |
a75214e5 | 1113 | |
252b5132 | 1114 | /* Skip whitespace. */ |
3882b010 | 1115 | while (ISSPACE (* op_end)) |
252b5132 | 1116 | ++ op_end; |
a75214e5 | 1117 | |
252b5132 RH |
1118 | if (* op_end == ',') |
1119 | { | |
1120 | op_end = parse_imm (op_end + 1, & reg, 0, 31); | |
ea1562b3 | 1121 | /* Immediate values of 0 -> 6 translate to movi. */ |
252b5132 RH |
1122 | if (reg <= 6) |
1123 | { | |
1124 | inst = (inst & 0xF) | MCORE_INST_BGENI_ALT; | |
1125 | reg = 0x1 << reg; | |
1126 | as_warn (_("translating bgeni to movi")); | |
1127 | } | |
1128 | inst &= ~ 0x01f0; | |
1129 | inst |= reg << 4; | |
1130 | } | |
1131 | else | |
1132 | as_bad (_("second operand missing")); | |
a75214e5 | 1133 | |
252b5132 RH |
1134 | output = frag_more (2); |
1135 | break; | |
a75214e5 | 1136 | |
ea1562b3 | 1137 | case OBR2: /* Like OBR, but arg is 2^n instead of n. */ |
252b5132 RH |
1138 | op_end = parse_reg (op_end + 1, & reg); |
1139 | inst |= reg; | |
a75214e5 | 1140 | |
252b5132 | 1141 | /* Skip whitespace. */ |
3882b010 | 1142 | while (ISSPACE (* op_end)) |
252b5132 | 1143 | ++ op_end; |
a75214e5 | 1144 | |
252b5132 RH |
1145 | if (* op_end == ',') |
1146 | { | |
1147 | op_end = parse_imm (op_end + 1, & reg, 1, 1 << 31); | |
a75214e5 | 1148 | |
252b5132 RH |
1149 | /* Further restrict the immediate to a power of two. */ |
1150 | if ((reg & (reg - 1)) == 0) | |
f17c130b | 1151 | reg = mylog2 (reg); |
252b5132 RH |
1152 | else |
1153 | { | |
1154 | reg = 0; | |
1155 | as_bad (_("immediate is not a power of two")); | |
1156 | } | |
a75214e5 KH |
1157 | |
1158 | /* Immediate values of 0 -> 6 translate to movi. */ | |
252b5132 RH |
1159 | if (reg <= 6) |
1160 | { | |
1161 | inst = (inst & 0xF) | MCORE_INST_BGENI_ALT; | |
1162 | reg = 0x1 << reg; | |
1163 | as_warn (_("translating mgeni to movi")); | |
1164 | } | |
a75214e5 | 1165 | |
252b5132 RH |
1166 | inst |= reg << 4; |
1167 | } | |
1168 | else | |
1169 | as_bad (_("second operand missing")); | |
a75214e5 | 1170 | |
252b5132 RH |
1171 | output = frag_more (2); |
1172 | break; | |
a75214e5 | 1173 | |
252b5132 RH |
1174 | case OMa: /* Specific for bmaski: imm 1->7 translate to movi. */ |
1175 | case OMb: | |
1176 | case OMc: | |
1177 | op_end = parse_reg (op_end + 1, & reg); | |
1178 | inst |= reg; | |
a75214e5 | 1179 | |
252b5132 | 1180 | /* Skip whitespace. */ |
3882b010 | 1181 | while (ISSPACE (* op_end)) |
252b5132 | 1182 | ++ op_end; |
a75214e5 | 1183 | |
252b5132 RH |
1184 | if (* op_end == ',') |
1185 | { | |
1186 | op_end = parse_imm (op_end + 1, & reg, 1, 32); | |
a75214e5 KH |
1187 | |
1188 | /* Immediate values of 1 -> 7 translate to movi. */ | |
252b5132 RH |
1189 | if (reg <= 7) |
1190 | { | |
1191 | inst = (inst & 0xF) | MCORE_INST_BMASKI_ALT; | |
1192 | reg = (0x1 << reg) - 1; | |
1193 | inst |= reg << 4; | |
a75214e5 | 1194 | |
252b5132 RH |
1195 | as_warn (_("translating bmaski to movi")); |
1196 | } | |
1197 | else | |
1198 | { | |
1199 | inst &= ~ 0x01F0; | |
1200 | inst |= (reg & 0x1F) << 4; | |
1201 | } | |
1202 | } | |
1203 | else | |
1204 | as_bad (_("second operand missing")); | |
a75214e5 | 1205 | |
252b5132 RH |
1206 | output = frag_more (2); |
1207 | break; | |
a75214e5 | 1208 | |
252b5132 RH |
1209 | case SI: |
1210 | op_end = parse_reg (op_end + 1, & reg); | |
1211 | inst |= reg; | |
a75214e5 | 1212 | |
252b5132 | 1213 | /* Skip whitespace. */ |
3882b010 | 1214 | while (ISSPACE (* op_end)) |
252b5132 | 1215 | ++ op_end; |
a75214e5 | 1216 | |
252b5132 RH |
1217 | if (* op_end == ',') |
1218 | { | |
1219 | op_end = parse_imm (op_end + 1, & reg, 1, 31); | |
1220 | inst |= reg << 4; | |
1221 | } | |
1222 | else | |
1223 | as_bad (_("second operand missing")); | |
a75214e5 | 1224 | |
252b5132 RH |
1225 | output = frag_more (2); |
1226 | break; | |
1227 | ||
1228 | case I7: | |
1229 | op_end = parse_reg (op_end + 1, & reg); | |
1230 | inst |= reg; | |
a75214e5 | 1231 | |
252b5132 | 1232 | /* Skip whitespace. */ |
3882b010 | 1233 | while (ISSPACE (* op_end)) |
252b5132 | 1234 | ++ op_end; |
a75214e5 | 1235 | |
252b5132 RH |
1236 | if (* op_end == ',') |
1237 | { | |
1238 | op_end = parse_imm (op_end + 1, & reg, 0, 0x7F); | |
1239 | inst |= reg << 4; | |
1240 | } | |
1241 | else | |
1242 | as_bad (_("second operand missing")); | |
a75214e5 | 1243 | |
252b5132 RH |
1244 | output = frag_more (2); |
1245 | break; | |
a75214e5 | 1246 | |
252b5132 RH |
1247 | case LS: |
1248 | op_end = parse_reg (op_end + 1, & reg); | |
1249 | inst |= reg << 8; | |
a75214e5 | 1250 | |
252b5132 | 1251 | /* Skip whitespace. */ |
3882b010 | 1252 | while (ISSPACE (* op_end)) |
252b5132 | 1253 | ++ op_end; |
a75214e5 | 1254 | |
252b5132 RH |
1255 | if (* op_end == ',') |
1256 | { | |
1257 | int size; | |
a75214e5 | 1258 | |
252b5132 RH |
1259 | if ((inst & 0x6000) == 0) |
1260 | size = 4; | |
1261 | else if ((inst & 0x6000) == 0x4000) | |
1262 | size = 2; | |
1263 | else if ((inst & 0x6000) == 0x2000) | |
1264 | size = 1; | |
aa699a2c AM |
1265 | else |
1266 | abort (); | |
a75214e5 | 1267 | |
252b5132 | 1268 | op_end = parse_mem (op_end + 1, & reg, & off, size); |
a75214e5 | 1269 | |
252b5132 RH |
1270 | if (off > 16) |
1271 | as_bad (_("displacement too large (%d)"), off); | |
1272 | else | |
1273 | inst |= (reg) | (off << 4); | |
1274 | } | |
1275 | else | |
1276 | as_bad (_("second operand missing")); | |
a75214e5 | 1277 | |
252b5132 RH |
1278 | output = frag_more (2); |
1279 | break; | |
a75214e5 | 1280 | |
252b5132 RH |
1281 | case LR: |
1282 | op_end = parse_reg (op_end + 1, & reg); | |
a75214e5 | 1283 | |
252b5132 RH |
1284 | if (reg == 0 || reg == 15) |
1285 | as_bad (_("Invalid register: r0 and r15 illegal")); | |
a75214e5 | 1286 | |
252b5132 | 1287 | inst |= (reg << 8); |
a75214e5 | 1288 | |
252b5132 | 1289 | /* Skip whitespace. */ |
3882b010 | 1290 | while (ISSPACE (* op_end)) |
252b5132 | 1291 | ++ op_end; |
a75214e5 | 1292 | |
252b5132 | 1293 | if (* op_end == ',') |
2d473ce9 NC |
1294 | { |
1295 | /* parse_rt calls frag_more() for us. */ | |
1296 | input_line_pointer = parse_rt (op_end + 1, & output, 0, 0); | |
5f8075fa | 1297 | op_end = input_line_pointer; |
2d473ce9 | 1298 | } |
252b5132 RH |
1299 | else |
1300 | { | |
1301 | as_bad (_("second operand missing")); | |
1302 | output = frag_more (2); /* save its space */ | |
1303 | } | |
1304 | break; | |
a75214e5 | 1305 | |
252b5132 RH |
1306 | case LJ: |
1307 | input_line_pointer = parse_rt (op_end + 1, & output, 1, 0); | |
1308 | /* parse_rt() calls frag_more() for us. */ | |
2d473ce9 | 1309 | op_end = input_line_pointer; |
252b5132 | 1310 | break; |
a75214e5 | 1311 | |
252b5132 RH |
1312 | case RM: |
1313 | op_end = parse_reg (op_end + 1, & reg); | |
a75214e5 | 1314 | |
252b5132 RH |
1315 | if (reg == 0 || reg == 15) |
1316 | as_bad (_("bad starting register: r0 and r15 invalid")); | |
a75214e5 | 1317 | |
252b5132 | 1318 | inst |= reg; |
a75214e5 | 1319 | |
252b5132 | 1320 | /* Skip whitespace. */ |
3882b010 | 1321 | while (ISSPACE (* op_end)) |
252b5132 | 1322 | ++ op_end; |
a75214e5 | 1323 | |
252b5132 RH |
1324 | if (* op_end == '-') |
1325 | { | |
1326 | op_end = parse_reg (op_end + 1, & reg); | |
a75214e5 | 1327 | |
252b5132 RH |
1328 | if (reg != 15) |
1329 | as_bad (_("ending register must be r15")); | |
a75214e5 | 1330 | |
252b5132 | 1331 | /* Skip whitespace. */ |
3882b010 | 1332 | while (ISSPACE (* op_end)) |
252b5132 RH |
1333 | ++ op_end; |
1334 | } | |
a75214e5 | 1335 | |
252b5132 RH |
1336 | if (* op_end == ',') |
1337 | { | |
1338 | op_end ++; | |
a75214e5 | 1339 | |
252b5132 | 1340 | /* Skip whitespace. */ |
3882b010 | 1341 | while (ISSPACE (* op_end)) |
252b5132 | 1342 | ++ op_end; |
a75214e5 | 1343 | |
252b5132 RH |
1344 | if (* op_end == '(') |
1345 | { | |
1346 | op_end = parse_reg (op_end + 1, & reg); | |
a75214e5 | 1347 | |
252b5132 RH |
1348 | if (reg != 0) |
1349 | as_bad (_("bad base register: must be r0")); | |
a75214e5 | 1350 | |
252b5132 RH |
1351 | if (* op_end == ')') |
1352 | op_end ++; | |
1353 | } | |
1354 | else | |
1355 | as_bad (_("base register expected")); | |
1356 | } | |
1357 | else | |
1358 | as_bad (_("second operand missing")); | |
a75214e5 | 1359 | |
252b5132 RH |
1360 | output = frag_more (2); |
1361 | break; | |
a75214e5 | 1362 | |
252b5132 RH |
1363 | case RQ: |
1364 | op_end = parse_reg (op_end + 1, & reg); | |
a75214e5 | 1365 | |
252b5132 RH |
1366 | if (reg != 4) |
1367 | as_fatal (_("first register must be r4")); | |
a75214e5 | 1368 | |
252b5132 | 1369 | /* Skip whitespace. */ |
3882b010 | 1370 | while (ISSPACE (* op_end)) |
252b5132 | 1371 | ++ op_end; |
a75214e5 | 1372 | |
252b5132 RH |
1373 | if (* op_end == '-') |
1374 | { | |
1375 | op_end = parse_reg (op_end + 1, & reg); | |
a75214e5 | 1376 | |
252b5132 RH |
1377 | if (reg != 7) |
1378 | as_fatal (_("last register must be r7")); | |
a75214e5 | 1379 | |
252b5132 | 1380 | /* Skip whitespace. */ |
3882b010 | 1381 | while (ISSPACE (* op_end)) |
252b5132 | 1382 | ++ op_end; |
a75214e5 | 1383 | |
252b5132 RH |
1384 | if (* op_end == ',') |
1385 | { | |
1386 | op_end ++; | |
a75214e5 | 1387 | |
252b5132 | 1388 | /* Skip whitespace. */ |
3882b010 | 1389 | while (ISSPACE (* op_end)) |
252b5132 | 1390 | ++ op_end; |
a75214e5 | 1391 | |
252b5132 RH |
1392 | if (* op_end == '(') |
1393 | { | |
1394 | op_end = parse_reg (op_end + 1, & reg); | |
a75214e5 | 1395 | |
252b5132 RH |
1396 | if (reg >= 4 && reg <= 7) |
1397 | as_fatal ("base register cannot be r4, r5, r6, or r7"); | |
a75214e5 | 1398 | |
252b5132 | 1399 | inst |= reg; |
a75214e5 | 1400 | |
252b5132 | 1401 | /* Skip whitespace. */ |
3882b010 | 1402 | while (ISSPACE (* op_end)) |
252b5132 | 1403 | ++ op_end; |
a75214e5 | 1404 | |
252b5132 RH |
1405 | if (* op_end == ')') |
1406 | op_end ++; | |
1407 | } | |
1408 | else | |
1409 | as_bad (_("base register expected")); | |
1410 | } | |
1411 | else | |
1412 | as_bad (_("second operand missing")); | |
1413 | } | |
1414 | else | |
1415 | as_bad (_("reg-reg expected")); | |
a75214e5 | 1416 | |
252b5132 RH |
1417 | output = frag_more (2); |
1418 | break; | |
a75214e5 | 1419 | |
252b5132 RH |
1420 | case BR: |
1421 | input_line_pointer = parse_exp (op_end + 1, & e); | |
2d473ce9 | 1422 | op_end = input_line_pointer; |
a75214e5 | 1423 | |
252b5132 | 1424 | output = frag_more (2); |
a75214e5 KH |
1425 | |
1426 | fix_new_exp (frag_now, output-frag_now->fr_literal, | |
252b5132 RH |
1427 | 2, & e, 1, BFD_RELOC_MCORE_PCREL_IMM11BY2); |
1428 | break; | |
a75214e5 | 1429 | |
252b5132 RH |
1430 | case BL: |
1431 | op_end = parse_reg (op_end + 1, & reg); | |
1432 | inst |= reg << 4; | |
a75214e5 | 1433 | |
252b5132 | 1434 | /* Skip whitespace. */ |
3882b010 | 1435 | while (ISSPACE (* op_end)) |
252b5132 | 1436 | ++ op_end; |
a75214e5 | 1437 | |
252b5132 RH |
1438 | if (* op_end == ',') |
1439 | { | |
1440 | op_end = parse_exp (op_end + 1, & e); | |
1441 | output = frag_more (2); | |
a75214e5 KH |
1442 | |
1443 | fix_new_exp (frag_now, output-frag_now->fr_literal, | |
252b5132 RH |
1444 | 2, & e, 1, BFD_RELOC_MCORE_PCREL_IMM4BY2); |
1445 | } | |
1446 | else | |
1447 | { | |
1448 | as_bad (_("second operand missing")); | |
1449 | output = frag_more (2); | |
1450 | } | |
1451 | break; | |
a75214e5 | 1452 | |
252b5132 RH |
1453 | case JC: |
1454 | input_line_pointer = parse_exp (op_end + 1, & e); | |
2d473ce9 | 1455 | op_end = input_line_pointer; |
a75214e5 | 1456 | |
252b5132 | 1457 | output = frag_var (rs_machine_dependent, |
93c2a809 AM |
1458 | md_relax_table[C (COND_JUMP, DISP32)].rlx_length, |
1459 | md_relax_table[C (COND_JUMP, DISP12)].rlx_length, | |
252b5132 RH |
1460 | C (COND_JUMP, 0), e.X_add_symbol, e.X_add_number, 0); |
1461 | isize = C32_LEN; | |
1462 | break; | |
a75214e5 | 1463 | |
252b5132 RH |
1464 | case JU: |
1465 | input_line_pointer = parse_exp (op_end + 1, & e); | |
2d473ce9 NC |
1466 | op_end = input_line_pointer; |
1467 | ||
252b5132 | 1468 | output = frag_var (rs_machine_dependent, |
93c2a809 AM |
1469 | md_relax_table[C (UNCD_JUMP, DISP32)].rlx_length, |
1470 | md_relax_table[C (UNCD_JUMP, DISP12)].rlx_length, | |
252b5132 RH |
1471 | C (UNCD_JUMP, 0), e.X_add_symbol, e.X_add_number, 0); |
1472 | isize = U32_LEN; | |
1473 | break; | |
a75214e5 | 1474 | |
252b5132 RH |
1475 | case JL: |
1476 | inst = MCORE_INST_JSRI; /* jsri */ | |
1477 | input_line_pointer = parse_rt (op_end + 1, & output, 1, & e); | |
bcef92fa | 1478 | /* parse_rt() calls frag_more for us. */ |
2d473ce9 | 1479 | op_end = input_line_pointer; |
a75214e5 KH |
1480 | |
1481 | /* Only do this if we know how to do it ... */ | |
252b5132 RH |
1482 | if (e.X_op != O_absent && do_jsri2bsr) |
1483 | { | |
1484 | /* Look at adding the R_PCREL_JSRIMM11BY2. */ | |
a75214e5 | 1485 | fix_new_exp (frag_now, output-frag_now->fr_literal, |
252b5132 RH |
1486 | 2, & e, 1, BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2); |
1487 | } | |
1488 | break; | |
1489 | ||
ea1562b3 NC |
1490 | case RSI: |
1491 | /* SI, but imm becomes 32-imm. */ | |
252b5132 RH |
1492 | op_end = parse_reg (op_end + 1, & reg); |
1493 | inst |= reg; | |
a75214e5 | 1494 | |
252b5132 | 1495 | /* Skip whitespace. */ |
3882b010 | 1496 | while (ISSPACE (* op_end)) |
252b5132 | 1497 | ++ op_end; |
a75214e5 | 1498 | |
252b5132 RH |
1499 | if (* op_end == ',') |
1500 | { | |
1501 | op_end = parse_imm (op_end + 1, & reg, 1, 31); | |
a75214e5 | 1502 | |
252b5132 RH |
1503 | reg = 32 - reg; |
1504 | inst |= reg << 4; | |
1505 | } | |
1506 | else | |
1507 | as_bad (_("second operand missing")); | |
a75214e5 | 1508 | |
252b5132 RH |
1509 | output = frag_more (2); |
1510 | break; | |
a75214e5 | 1511 | |
252b5132 RH |
1512 | case DO21: /* O2, dup rd, lit must be 1 */ |
1513 | op_end = parse_reg (op_end + 1, & reg); | |
1514 | inst |= reg; | |
1515 | inst |= reg << 4; | |
a75214e5 | 1516 | |
252b5132 | 1517 | /* Skip whitespace. */ |
3882b010 | 1518 | while (ISSPACE (* op_end)) |
252b5132 | 1519 | ++ op_end; |
a75214e5 | 1520 | |
252b5132 RH |
1521 | if (* op_end == ',') |
1522 | { | |
1523 | op_end = parse_imm (op_end + 1, & reg, 1, 31); | |
a75214e5 | 1524 | |
252b5132 RH |
1525 | if (reg != 1) |
1526 | as_bad (_("second operand must be 1")); | |
1527 | } | |
1528 | else | |
1529 | as_bad (_("second operand missing")); | |
a75214e5 | 1530 | |
252b5132 RH |
1531 | output = frag_more (2); |
1532 | break; | |
a75214e5 | 1533 | |
252b5132 RH |
1534 | case SIa: |
1535 | op_end = parse_reg (op_end + 1, & reg); | |
1536 | inst |= reg; | |
a75214e5 | 1537 | |
252b5132 | 1538 | /* Skip whitespace. */ |
3882b010 | 1539 | while (ISSPACE (* op_end)) |
252b5132 | 1540 | ++ op_end; |
a75214e5 | 1541 | |
252b5132 RH |
1542 | if (* op_end == ',') |
1543 | { | |
1544 | op_end = parse_imm (op_end + 1, & reg, 1, 31); | |
1545 | ||
1546 | if (reg == 0) | |
1547 | as_bad (_("zero used as immediate value")); | |
a75214e5 | 1548 | |
252b5132 RH |
1549 | inst |= reg << 4; |
1550 | } | |
1551 | else | |
1552 | as_bad (_("second operand missing")); | |
a75214e5 | 1553 | |
252b5132 RH |
1554 | output = frag_more (2); |
1555 | break; | |
1556 | ||
bec50466 NC |
1557 | case OPSR: |
1558 | if (cpu == M210) | |
1559 | { | |
1560 | as_bad (_("M340 specific opcode used when assembling for M210")); | |
1561 | break; | |
1562 | } | |
a75214e5 | 1563 | |
bec50466 | 1564 | op_end = parse_psrmod (op_end + 1, & reg); |
a75214e5 | 1565 | |
bec50466 NC |
1566 | /* Look for further selectors. */ |
1567 | while (* op_end == ',') | |
1568 | { | |
1569 | unsigned value; | |
a75214e5 | 1570 | |
bec50466 | 1571 | op_end = parse_psrmod (op_end + 1, & value); |
a75214e5 | 1572 | |
bec50466 NC |
1573 | if (value & reg) |
1574 | as_bad (_("duplicated psr bit specifier")); | |
a75214e5 | 1575 | |
bec50466 NC |
1576 | reg |= value; |
1577 | } | |
a75214e5 | 1578 | |
bec50466 NC |
1579 | if (reg > 8) |
1580 | as_bad (_("`af' must appear alone")); | |
a75214e5 | 1581 | |
bec50466 NC |
1582 | inst |= (reg & 0x7); |
1583 | output = frag_more (2); | |
1584 | break; | |
a75214e5 | 1585 | |
252b5132 RH |
1586 | default: |
1587 | as_bad (_("unimplemented opcode \"%s\""), name); | |
1588 | } | |
2d473ce9 NC |
1589 | |
1590 | /* Drop whitespace after all the operands have been parsed. */ | |
3882b010 | 1591 | while (ISSPACE (* op_end)) |
2d473ce9 NC |
1592 | op_end ++; |
1593 | ||
a75214e5 | 1594 | /* Give warning message if the insn has more operands than required. */ |
2d473ce9 NC |
1595 | if (strcmp (op_end, opcode->name) && strcmp (op_end, "")) |
1596 | as_warn (_("ignoring operands: %s "), op_end); | |
a75214e5 | 1597 | |
b8a40f53 NC |
1598 | output[0] = INST_BYTE0 (inst); |
1599 | output[1] = INST_BYTE1 (inst); | |
a75214e5 | 1600 | |
252b5132 RH |
1601 | check_literals (opcode->transfer, isize); |
1602 | } | |
1603 | ||
1604 | symbolS * | |
ea1562b3 | 1605 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
1606 | { |
1607 | return 0; | |
1608 | } | |
1609 | ||
1610 | void | |
ea1562b3 | 1611 | md_mcore_end (void) |
252b5132 RH |
1612 | { |
1613 | dump_literals (0); | |
1614 | subseg_set (text_section, 0); | |
1615 | } | |
1616 | ||
1617 | /* Various routines to kill one day. */ | |
ea1562b3 | 1618 | |
6d4af3c2 | 1619 | const char * |
499ac353 | 1620 | md_atof (int type, char * litP, int * sizeP) |
252b5132 | 1621 | { |
499ac353 | 1622 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
1623 | } |
1624 | \f | |
5a38dc70 | 1625 | const char * md_shortopts = ""; |
252b5132 | 1626 | |
ea1562b3 NC |
1627 | enum options |
1628 | { | |
1629 | OPTION_JSRI2BSR_ON = OPTION_MD_BASE, | |
1630 | OPTION_JSRI2BSR_OFF, | |
1631 | OPTION_SIFILTER_ON, | |
1632 | OPTION_SIFILTER_OFF, | |
1633 | OPTION_CPU, | |
1634 | OPTION_EB, | |
1635 | OPTION_EL, | |
1636 | }; | |
252b5132 RH |
1637 | |
1638 | struct option md_longopts[] = | |
1639 | { | |
252b5132 RH |
1640 | { "no-jsri2bsr", no_argument, NULL, OPTION_JSRI2BSR_OFF}, |
1641 | { "jsri2bsr", no_argument, NULL, OPTION_JSRI2BSR_ON}, | |
1642 | { "sifilter", no_argument, NULL, OPTION_SIFILTER_ON}, | |
1643 | { "no-sifilter", no_argument, NULL, OPTION_SIFILTER_OFF}, | |
bec50466 NC |
1644 | { "cpu", required_argument, NULL, OPTION_CPU}, |
1645 | { "EB", no_argument, NULL, OPTION_EB}, | |
1646 | { "EL", no_argument, NULL, OPTION_EL}, | |
252b5132 RH |
1647 | { NULL, no_argument, NULL, 0} |
1648 | }; | |
1649 | ||
1650 | size_t md_longopts_size = sizeof (md_longopts); | |
1651 | ||
1652 | int | |
17b9d67d | 1653 | md_parse_option (int c, const char * arg) |
252b5132 | 1654 | { |
252b5132 RH |
1655 | switch (c) |
1656 | { | |
bec50466 NC |
1657 | case OPTION_CPU: |
1658 | if (streq (arg, "210")) | |
1659 | { | |
1660 | cpu = M210; | |
1661 | target_big_endian = 1; | |
1662 | } | |
1663 | else if (streq (arg, "340")) | |
1664 | cpu = M340; | |
1665 | else | |
5f8075fa | 1666 | as_warn (_("unrecognised cpu type '%s'"), arg); |
bec50466 | 1667 | break; |
a75214e5 | 1668 | |
bec50466 NC |
1669 | case OPTION_EB: target_big_endian = 1; break; |
1670 | case OPTION_EL: target_big_endian = 0; cpu = M340; break; | |
252b5132 RH |
1671 | case OPTION_JSRI2BSR_ON: do_jsri2bsr = 1; break; |
1672 | case OPTION_JSRI2BSR_OFF: do_jsri2bsr = 0; break; | |
1673 | case OPTION_SIFILTER_ON: sifilter_mode = 1; break; | |
1674 | case OPTION_SIFILTER_OFF: sifilter_mode = 0; break; | |
1675 | default: return 0; | |
1676 | } | |
1677 | ||
1678 | return 1; | |
1679 | } | |
1680 | ||
1681 | void | |
ea1562b3 | 1682 | md_show_usage (FILE * stream) |
252b5132 RH |
1683 | { |
1684 | fprintf (stream, _("\ | |
1685 | MCORE specific options:\n\ | |
b8a40f53 | 1686 | -{no-}jsri2bsr {dis}able jsri to bsr transformation (def: dis)\n\ |
bec50466 NC |
1687 | -{no-}sifilter {dis}able silicon filter behavior (def: dis)\n\ |
1688 | -cpu=[210|340] select CPU type\n\ | |
1689 | -EB assemble for a big endian system (default)\n\ | |
1690 | -EL assemble for a little endian system\n")); | |
252b5132 RH |
1691 | } |
1692 | \f | |
1693 | int md_short_jump_size; | |
1694 | ||
1695 | void | |
ea1562b3 NC |
1696 | md_create_short_jump (char * ptr ATTRIBUTE_UNUSED, |
1697 | addressT from_Nddr ATTRIBUTE_UNUSED, | |
1698 | addressT to_Nddr ATTRIBUTE_UNUSED, | |
1699 | fragS * frag ATTRIBUTE_UNUSED, | |
1700 | symbolS * to_symbol ATTRIBUTE_UNUSED) | |
252b5132 RH |
1701 | { |
1702 | as_fatal (_("failed sanity check: short_jump")); | |
1703 | } | |
1704 | ||
1705 | void | |
ea1562b3 NC |
1706 | md_create_long_jump (char * ptr ATTRIBUTE_UNUSED, |
1707 | addressT from_Nddr ATTRIBUTE_UNUSED, | |
1708 | addressT to_Nddr ATTRIBUTE_UNUSED, | |
1709 | fragS * frag ATTRIBUTE_UNUSED, | |
1710 | symbolS * to_symbol ATTRIBUTE_UNUSED) | |
252b5132 RH |
1711 | { |
1712 | as_fatal (_("failed sanity check: long_jump")); | |
1713 | } | |
1714 | ||
1715 | /* Called after relaxing, change the frags so they know how big they are. */ | |
ea1562b3 | 1716 | |
252b5132 | 1717 | void |
ea1562b3 NC |
1718 | md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, |
1719 | segT sec ATTRIBUTE_UNUSED, | |
1720 | fragS * fragP) | |
252b5132 | 1721 | { |
2132e3a3 | 1722 | char *buffer; |
252b5132 | 1723 | int targ_addr = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
a75214e5 | 1724 | |
2132e3a3 | 1725 | buffer = fragP->fr_fix + fragP->fr_literal; |
252b5132 RH |
1726 | |
1727 | switch (fragP->fr_subtype) | |
1728 | { | |
93c2a809 AM |
1729 | case C (COND_JUMP, DISP12): |
1730 | case C (UNCD_JUMP, DISP12): | |
252b5132 | 1731 | { |
bcef92fa | 1732 | /* Get the address of the end of the instruction. */ |
252b5132 RH |
1733 | int next_inst = fragP->fr_fix + fragP->fr_address + 2; |
1734 | unsigned char t0; | |
1735 | int disp = targ_addr - next_inst; | |
a75214e5 | 1736 | |
252b5132 | 1737 | if (disp & 1) |
b8a40f53 | 1738 | as_bad (_("odd displacement at %x"), next_inst - 2); |
a75214e5 | 1739 | |
252b5132 | 1740 | disp >>= 1; |
a75214e5 | 1741 | |
bec50466 NC |
1742 | if (! target_big_endian) |
1743 | { | |
1744 | t0 = buffer[1] & 0xF8; | |
a75214e5 | 1745 | |
bec50466 | 1746 | md_number_to_chars (buffer, disp, 2); |
a75214e5 | 1747 | |
bec50466 NC |
1748 | buffer[1] = (buffer[1] & 0x07) | t0; |
1749 | } | |
1750 | else | |
b8a40f53 NC |
1751 | { |
1752 | t0 = buffer[0] & 0xF8; | |
a75214e5 | 1753 | |
b8a40f53 | 1754 | md_number_to_chars (buffer, disp, 2); |
a75214e5 | 1755 | |
b8a40f53 NC |
1756 | buffer[0] = (buffer[0] & 0x07) | t0; |
1757 | } | |
a75214e5 | 1758 | |
252b5132 | 1759 | fragP->fr_fix += 2; |
252b5132 RH |
1760 | } |
1761 | break; | |
1762 | ||
93c2a809 | 1763 | case C (COND_JUMP, DISP32): |
252b5132 RH |
1764 | case C (COND_JUMP, UNDEF_WORD_DISP): |
1765 | { | |
1766 | /* A conditional branch wont fit into 12 bits so: | |
ea1562b3 NC |
1767 | b!cond 1f |
1768 | jmpi 0f | |
1769 | .align 2 | |
1770 | 0: .long disp | |
1771 | 1: | |
3739860c | 1772 | |
ea1562b3 NC |
1773 | If the b!cond is 4 byte aligned, the literal which would |
1774 | go at x+4 will also be aligned. */ | |
252b5132 RH |
1775 | int first_inst = fragP->fr_fix + fragP->fr_address; |
1776 | int needpad = (first_inst & 3); | |
1777 | ||
bec50466 NC |
1778 | if (! target_big_endian) |
1779 | buffer[1] ^= 0x08; | |
1780 | else | |
ea1562b3 | 1781 | buffer[0] ^= 0x08; /* Toggle T/F bit. */ |
252b5132 | 1782 | |
ea1562b3 | 1783 | buffer[2] = INST_BYTE0 (MCORE_INST_JMPI); /* Build jmpi. */ |
252b5132 | 1784 | buffer[3] = INST_BYTE1 (MCORE_INST_JMPI); |
a75214e5 | 1785 | |
252b5132 RH |
1786 | if (needpad) |
1787 | { | |
bec50466 NC |
1788 | if (! target_big_endian) |
1789 | { | |
ea1562b3 NC |
1790 | buffer[0] = 4; /* Branch over jmpi, pad, and ptr. */ |
1791 | buffer[2] = 1; /* Jmpi offset of 1 gets the pointer. */ | |
bec50466 NC |
1792 | } |
1793 | else | |
b8a40f53 | 1794 | { |
ea1562b3 NC |
1795 | buffer[1] = 4; /* Branch over jmpi, pad, and ptr. */ |
1796 | buffer[3] = 1; /* Jmpi offset of 1 gets the pointer. */ | |
b8a40f53 | 1797 | } |
a75214e5 | 1798 | |
ea1562b3 | 1799 | buffer[4] = 0; /* Alignment/pad. */ |
252b5132 | 1800 | buffer[5] = 0; |
ea1562b3 | 1801 | buffer[6] = 0; /* Space for 32 bit address. */ |
252b5132 RH |
1802 | buffer[7] = 0; |
1803 | buffer[8] = 0; | |
1804 | buffer[9] = 0; | |
a75214e5 | 1805 | |
ea1562b3 | 1806 | /* Make reloc for the long disp. */ |
252b5132 RH |
1807 | fix_new (fragP, fragP->fr_fix + 6, 4, |
1808 | fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_32); | |
a75214e5 | 1809 | |
252b5132 RH |
1810 | fragP->fr_fix += C32_LEN; |
1811 | } | |
1812 | else | |
1813 | { | |
1814 | /* See comment below about this given gas' limitations for | |
1815 | shrinking the fragment. '3' is the amount of code that | |
1816 | we inserted here, but '4' is right for the space we reserved | |
a75214e5 | 1817 | for this fragment. */ |
bec50466 NC |
1818 | if (! target_big_endian) |
1819 | { | |
ea1562b3 NC |
1820 | buffer[0] = 3; /* Branch over jmpi, and ptr. */ |
1821 | buffer[2] = 0; /* Jmpi offset of 0 gets the pointer. */ | |
bec50466 NC |
1822 | } |
1823 | else | |
b8a40f53 | 1824 | { |
ea1562b3 NC |
1825 | buffer[1] = 3; /* Branch over jmpi, and ptr. */ |
1826 | buffer[3] = 0; /* Jmpi offset of 0 gets the pointer. */ | |
b8a40f53 | 1827 | } |
a75214e5 | 1828 | |
ea1562b3 | 1829 | buffer[4] = 0; /* Space for 32 bit address. */ |
252b5132 RH |
1830 | buffer[5] = 0; |
1831 | buffer[6] = 0; | |
1832 | buffer[7] = 0; | |
a75214e5 | 1833 | |
252b5132 RH |
1834 | /* Make reloc for the long disp. */ |
1835 | fix_new (fragP, fragP->fr_fix + 4, 4, | |
1836 | fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_32); | |
1837 | fragP->fr_fix += C32_LEN; | |
1838 | ||
b8a40f53 NC |
1839 | /* Frag is actually shorter (see the other side of this ifdef) |
1840 | but gas isn't prepared for that. We have to re-adjust | |
a75214e5 | 1841 | the branch displacement so that it goes beyond the |
252b5132 RH |
1842 | full length of the fragment, not just what we actually |
1843 | filled in. */ | |
bec50466 | 1844 | if (! target_big_endian) |
ea1562b3 | 1845 | buffer[0] = 4; /* Jmpi, ptr, and the 'tail pad'. */ |
bec50466 | 1846 | else |
ea1562b3 | 1847 | buffer[1] = 4; /* Jmpi, ptr, and the 'tail pad'. */ |
252b5132 | 1848 | } |
252b5132 RH |
1849 | } |
1850 | break; | |
1851 | ||
93c2a809 | 1852 | case C (UNCD_JUMP, DISP32): |
252b5132 RH |
1853 | case C (UNCD_JUMP, UNDEF_WORD_DISP): |
1854 | { | |
1855 | /* An unconditional branch will not fit in 12 bits, make code which | |
1856 | looks like: | |
1857 | jmpi 0f | |
1858 | .align 2 | |
1859 | 0: .long disp | |
1860 | we need a pad if "first_inst" is 4 byte aligned. | |
ea1562b3 | 1861 | [because the natural literal place is x + 2]. */ |
252b5132 RH |
1862 | int first_inst = fragP->fr_fix + fragP->fr_address; |
1863 | int needpad = !(first_inst & 3); | |
1864 | ||
ea1562b3 | 1865 | buffer[0] = INST_BYTE0 (MCORE_INST_JMPI); /* Build jmpi. */ |
252b5132 RH |
1866 | buffer[1] = INST_BYTE1 (MCORE_INST_JMPI); |
1867 | ||
1868 | if (needpad) | |
1869 | { | |
bec50466 | 1870 | if (! target_big_endian) |
ea1562b3 | 1871 | buffer[0] = 1; /* Jmpi offset of 1 since padded. */ |
bec50466 | 1872 | else |
ea1562b3 NC |
1873 | buffer[1] = 1; /* Jmpi offset of 1 since padded. */ |
1874 | buffer[2] = 0; /* Alignment. */ | |
252b5132 | 1875 | buffer[3] = 0; |
ea1562b3 | 1876 | buffer[4] = 0; /* Space for 32 bit address. */ |
252b5132 RH |
1877 | buffer[5] = 0; |
1878 | buffer[6] = 0; | |
1879 | buffer[7] = 0; | |
a75214e5 | 1880 | |
bcef92fa | 1881 | /* Make reloc for the long disp. */ |
252b5132 RH |
1882 | fix_new (fragP, fragP->fr_fix + 4, 4, |
1883 | fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_32); | |
a75214e5 | 1884 | |
252b5132 RH |
1885 | fragP->fr_fix += U32_LEN; |
1886 | } | |
1887 | else | |
1888 | { | |
bec50466 | 1889 | if (! target_big_endian) |
ea1562b3 | 1890 | buffer[0] = 0; /* Jmpi offset of 0 if no pad. */ |
bec50466 | 1891 | else |
ea1562b3 NC |
1892 | buffer[1] = 0; /* Jmpi offset of 0 if no pad. */ |
1893 | buffer[2] = 0; /* Space for 32 bit address. */ | |
252b5132 RH |
1894 | buffer[3] = 0; |
1895 | buffer[4] = 0; | |
1896 | buffer[5] = 0; | |
a75214e5 | 1897 | |
bcef92fa | 1898 | /* Make reloc for the long disp. */ |
252b5132 RH |
1899 | fix_new (fragP, fragP->fr_fix + 2, 4, |
1900 | fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_32); | |
1901 | fragP->fr_fix += U32_LEN; | |
1902 | } | |
252b5132 RH |
1903 | } |
1904 | break; | |
1905 | ||
1906 | default: | |
1907 | abort (); | |
1908 | } | |
1909 | } | |
1910 | ||
1911 | /* Applies the desired value to the specified location. | |
1912 | Also sets up addends for 'rela' type relocations. */ | |
94f592af NC |
1913 | |
1914 | void | |
55cf6793 | 1915 | md_apply_fix (fixS * fixP, |
ea1562b3 NC |
1916 | valueT * valP, |
1917 | segT segment ATTRIBUTE_UNUSED) | |
252b5132 RH |
1918 | { |
1919 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
3b4dbbbf | 1920 | const char * file = fixP->fx_file ? fixP->fx_file : _("unknown"); |
252b5132 RH |
1921 | const char * symname; |
1922 | /* Note: use offsetT because it is signed, valueT is unsigned. */ | |
a161fe53 | 1923 | offsetT val = *valP; |
a75214e5 | 1924 | |
252b5132 RH |
1925 | symname = fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : _("<unknown>"); |
1926 | /* Save this for the addend in the relocation record. */ | |
1927 | fixP->fx_addnumber = val; | |
1928 | ||
a161fe53 | 1929 | if (fixP->fx_addsy != NULL) |
252b5132 | 1930 | { |
252b5132 RH |
1931 | #ifdef OBJ_ELF |
1932 | /* For ELF we can just return and let the reloc that will be generated | |
1933 | take care of everything. For COFF we still have to insert 'val' | |
1934 | into the insn since the addend field will be ignored. */ | |
94f592af | 1935 | return; |
252b5132 RH |
1936 | #endif |
1937 | } | |
1938 | else | |
1939 | fixP->fx_done = 1; | |
a75214e5 | 1940 | |
252b5132 RH |
1941 | switch (fixP->fx_r_type) |
1942 | { | |
ea1562b3 NC |
1943 | /* Second byte of 2 byte opcode. */ |
1944 | case BFD_RELOC_MCORE_PCREL_IMM11BY2: | |
252b5132 RH |
1945 | if ((val & 1) != 0) |
1946 | as_bad_where (file, fixP->fx_line, | |
aa699a2c | 1947 | _("odd distance branch (0x%lx bytes)"), (long) val); |
252b5132 RH |
1948 | val /= 2; |
1949 | if (((val & ~0x3ff) != 0) && ((val | 0x3ff) != -1)) | |
1950 | as_bad_where (file, fixP->fx_line, | |
aa699a2c AM |
1951 | _("pcrel for branch to %s too far (0x%lx)"), |
1952 | symname, (long) val); | |
bec50466 NC |
1953 | if (target_big_endian) |
1954 | { | |
1955 | buf[0] |= ((val >> 8) & 0x7); | |
1956 | buf[1] |= (val & 0xff); | |
1957 | } | |
1958 | else | |
1959 | { | |
eaa15ab8 NC |
1960 | buf[1] |= ((val >> 8) & 0x7); |
1961 | buf[0] |= (val & 0xff); | |
bec50466 | 1962 | } |
b8a40f53 | 1963 | break; |
252b5132 | 1964 | |
ea1562b3 NC |
1965 | /* Lower 8 bits of 2 byte opcode. */ |
1966 | case BFD_RELOC_MCORE_PCREL_IMM8BY4: | |
252b5132 RH |
1967 | val += 3; |
1968 | val /= 4; | |
1969 | if (val & ~0xff) | |
1970 | as_bad_where (file, fixP->fx_line, | |
aa699a2c AM |
1971 | _("pcrel for lrw/jmpi/jsri to %s too far (0x%lx)"), |
1972 | symname, (long) val); | |
bec50466 NC |
1973 | else if (! target_big_endian) |
1974 | buf[0] |= (val & 0xff); | |
252b5132 RH |
1975 | else |
1976 | buf[1] |= (val & 0xff); | |
b8a40f53 | 1977 | break; |
252b5132 | 1978 | |
ea1562b3 NC |
1979 | /* Loopt instruction. */ |
1980 | case BFD_RELOC_MCORE_PCREL_IMM4BY2: | |
252b5132 RH |
1981 | if ((val < -32) || (val > -2)) |
1982 | as_bad_where (file, fixP->fx_line, | |
aa699a2c | 1983 | _("pcrel for loopt too far (0x%lx)"), (long) val); |
252b5132 | 1984 | val /= 2; |
bec50466 NC |
1985 | if (! target_big_endian) |
1986 | buf[0] |= (val & 0xf); | |
1987 | else | |
2d473ce9 | 1988 | buf[1] |= (val & 0xf); |
252b5132 RH |
1989 | break; |
1990 | ||
1991 | case BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2: | |
1992 | /* Conditional linker map jsri to bsr. */ | |
a75214e5 | 1993 | /* If its a local target and close enough, fix it. |
5f8075fa | 1994 | NB: >= -2k for backwards bsr; < 2k for forwards... */ |
252b5132 RH |
1995 | if (fixP->fx_addsy == 0 && val >= -2048 && val < 2048) |
1996 | { | |
1997 | long nval = (val / 2) & 0x7ff; | |
1998 | nval |= MCORE_INST_BSR; | |
a75214e5 | 1999 | |
252b5132 | 2000 | /* REPLACE the instruction, don't just modify it. */ |
b8a40f53 NC |
2001 | buf[0] = INST_BYTE0 (nval); |
2002 | buf[1] = INST_BYTE1 (nval); | |
252b5132 RH |
2003 | } |
2004 | else | |
2005 | fixP->fx_done = 0; | |
2006 | break; | |
2007 | ||
2008 | case BFD_RELOC_MCORE_PCREL_32: | |
2009 | case BFD_RELOC_VTABLE_INHERIT: | |
2010 | case BFD_RELOC_VTABLE_ENTRY: | |
2011 | fixP->fx_done = 0; | |
2012 | break; | |
a75214e5 | 2013 | |
252b5132 RH |
2014 | default: |
2015 | if (fixP->fx_addsy != NULL) | |
2016 | { | |
2017 | /* If the fix is an absolute reloc based on a symbol's | |
2018 | address, then it cannot be resolved until the final link. */ | |
2019 | fixP->fx_done = 0; | |
2020 | } | |
a75214e5 | 2021 | #ifdef OBJ_ELF |
252b5132 RH |
2022 | else |
2023 | #endif | |
2024 | { | |
2025 | if (fixP->fx_size == 4) | |
b8a40f53 | 2026 | ; |
252b5132 | 2027 | else if (fixP->fx_size == 2 && val >= -32768 && val <= 32767) |
b8a40f53 | 2028 | ; |
252b5132 | 2029 | else if (fixP->fx_size == 1 && val >= -256 && val <= 255) |
b8a40f53 | 2030 | ; |
252b5132 RH |
2031 | else |
2032 | abort (); | |
b8a40f53 | 2033 | md_number_to_chars (buf, val, fixP->fx_size); |
252b5132 RH |
2034 | } |
2035 | break; | |
2036 | } | |
252b5132 RH |
2037 | } |
2038 | ||
2039 | void | |
ea1562b3 | 2040 | md_operand (expressionS * expressionP) |
252b5132 RH |
2041 | { |
2042 | /* Ignore leading hash symbol, if poresent. */ | |
2043 | if (* input_line_pointer == '#') | |
2044 | { | |
2045 | input_line_pointer ++; | |
2046 | expression (expressionP); | |
2047 | } | |
2048 | } | |
2049 | ||
2050 | int md_long_jump_size; | |
2051 | ||
2052 | /* Called just before address relaxation, return the length | |
2053 | by which a fragment must grow to reach it's destination. */ | |
2054 | int | |
ea1562b3 | 2055 | md_estimate_size_before_relax (fragS * fragP, segT segment_type) |
252b5132 RH |
2056 | { |
2057 | switch (fragP->fr_subtype) | |
2058 | { | |
93c2a809 AM |
2059 | default: |
2060 | abort (); | |
2061 | ||
252b5132 RH |
2062 | case C (UNCD_JUMP, UNDEF_DISP): |
2063 | /* Used to be a branch to somewhere which was unknown. */ | |
2064 | if (!fragP->fr_symbol) | |
ea1562b3 | 2065 | fragP->fr_subtype = C (UNCD_JUMP, DISP12); |
252b5132 | 2066 | else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type) |
ea1562b3 | 2067 | fragP->fr_subtype = C (UNCD_JUMP, DISP12); |
252b5132 | 2068 | else |
ea1562b3 | 2069 | fragP->fr_subtype = C (UNCD_JUMP, UNDEF_WORD_DISP); |
252b5132 RH |
2070 | break; |
2071 | ||
252b5132 | 2072 | case C (COND_JUMP, UNDEF_DISP): |
a75214e5 | 2073 | /* Used to be a branch to somewhere which was unknown. */ |
252b5132 RH |
2074 | if (fragP->fr_symbol |
2075 | && S_GET_SEGMENT (fragP->fr_symbol) == segment_type) | |
ea1562b3 NC |
2076 | /* Got a symbol and it's defined in this segment, become byte |
2077 | sized - maybe it will fix up */ | |
2078 | fragP->fr_subtype = C (COND_JUMP, DISP12); | |
252b5132 | 2079 | else if (fragP->fr_symbol) |
ea1562b3 NC |
2080 | /* Its got a segment, but its not ours, so it will always be long. */ |
2081 | fragP->fr_subtype = C (COND_JUMP, UNDEF_WORD_DISP); | |
252b5132 | 2082 | else |
ea1562b3 NC |
2083 | /* We know the abs value. */ |
2084 | fragP->fr_subtype = C (COND_JUMP, DISP12); | |
93c2a809 | 2085 | break; |
252b5132 | 2086 | |
93c2a809 | 2087 | case C (UNCD_JUMP, DISP12): |
e66457fb | 2088 | case C (UNCD_JUMP, DISP32): |
93c2a809 AM |
2089 | case C (UNCD_JUMP, UNDEF_WORD_DISP): |
2090 | case C (COND_JUMP, DISP12): | |
e66457fb | 2091 | case C (COND_JUMP, DISP32): |
93c2a809 AM |
2092 | case C (COND_JUMP, UNDEF_WORD_DISP): |
2093 | /* When relaxing a section for the second time, we don't need to | |
e66457fb | 2094 | do anything besides return the current size. */ |
252b5132 RH |
2095 | break; |
2096 | } | |
a75214e5 | 2097 | |
606ab118 | 2098 | return md_relax_table[fragP->fr_subtype].rlx_length; |
252b5132 RH |
2099 | } |
2100 | ||
bcef92fa | 2101 | /* Put number into target byte order. */ |
ea1562b3 | 2102 | |
252b5132 | 2103 | void |
ea1562b3 | 2104 | md_number_to_chars (char * ptr, valueT use, int nbytes) |
252b5132 | 2105 | { |
04f8d83b NC |
2106 | if (target_big_endian) |
2107 | number_to_chars_bigendian (ptr, use, nbytes); | |
bec50466 | 2108 | else |
04f8d83b | 2109 | number_to_chars_littleendian (ptr, use, nbytes); |
252b5132 RH |
2110 | } |
2111 | ||
2112 | /* Round up a section size to the appropriate boundary. */ | |
ea1562b3 | 2113 | |
252b5132 | 2114 | valueT |
ea1562b3 NC |
2115 | md_section_align (segT segment ATTRIBUTE_UNUSED, |
2116 | valueT size) | |
252b5132 | 2117 | { |
ea1562b3 NC |
2118 | /* Byte alignment is fine. */ |
2119 | return size; | |
252b5132 RH |
2120 | } |
2121 | ||
252b5132 RH |
2122 | /* The location from which a PC relative jump should be calculated, |
2123 | given a PC relative reloc. */ | |
ea1562b3 | 2124 | |
252b5132 | 2125 | long |
ea1562b3 | 2126 | md_pcrel_from_section (fixS * fixp, segT sec ATTRIBUTE_UNUSED) |
252b5132 RH |
2127 | { |
2128 | #ifdef OBJ_ELF | |
2129 | /* If the symbol is undefined or defined in another section | |
2130 | we leave the add number alone for the linker to fix it later. | |
a75214e5 | 2131 | Only account for the PC pre-bump (which is 2 bytes on the MCore). */ |
252b5132 RH |
2132 | if (fixp->fx_addsy != (symbolS *) NULL |
2133 | && (! S_IS_DEFINED (fixp->fx_addsy) | |
2134 | || (S_GET_SEGMENT (fixp->fx_addsy) != sec))) | |
a75214e5 | 2135 | |
252b5132 | 2136 | { |
9c2799c2 | 2137 | gas_assert (fixp->fx_size == 2); /* must be an insn */ |
252b5132 RH |
2138 | return fixp->fx_size; |
2139 | } | |
2140 | #endif | |
2141 | ||
a75214e5 | 2142 | /* The case where we are going to resolve things... */ |
252b5132 RH |
2143 | return fixp->fx_size + fixp->fx_where + fixp->fx_frag->fr_address; |
2144 | } | |
2145 | ||
2146 | #define F(SZ,PCREL) (((SZ) << 1) + (PCREL)) | |
2147 | #define MAP(SZ,PCREL,TYPE) case F (SZ, PCREL): code = (TYPE); break | |
2148 | ||
2149 | arelent * | |
ea1562b3 | 2150 | tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp) |
252b5132 RH |
2151 | { |
2152 | arelent * rel; | |
2153 | bfd_reloc_code_real_type code; | |
252b5132 RH |
2154 | |
2155 | switch (fixp->fx_r_type) | |
2156 | { | |
a75214e5 | 2157 | /* These confuse the size/pcrel macro approach. */ |
252b5132 RH |
2158 | case BFD_RELOC_VTABLE_INHERIT: |
2159 | case BFD_RELOC_VTABLE_ENTRY: | |
2160 | case BFD_RELOC_MCORE_PCREL_IMM4BY2: | |
2161 | case BFD_RELOC_MCORE_PCREL_IMM8BY4: | |
2162 | case BFD_RELOC_MCORE_PCREL_IMM11BY2: | |
2163 | case BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2: | |
a75214e5 | 2164 | case BFD_RELOC_RVA: |
252b5132 RH |
2165 | code = fixp->fx_r_type; |
2166 | break; | |
a75214e5 | 2167 | |
252b5132 RH |
2168 | default: |
2169 | switch (F (fixp->fx_size, fixp->fx_pcrel)) | |
5f8075fa AM |
2170 | { |
2171 | MAP (1, 0, BFD_RELOC_8); | |
2172 | MAP (2, 0, BFD_RELOC_16); | |
2173 | MAP (4, 0, BFD_RELOC_32); | |
2174 | MAP (1, 1, BFD_RELOC_8_PCREL); | |
2175 | MAP (2, 1, BFD_RELOC_16_PCREL); | |
2176 | MAP (4, 1, BFD_RELOC_32_PCREL); | |
2177 | default: | |
252b5132 | 2178 | code = fixp->fx_r_type; |
5f8075fa | 2179 | as_bad (_("Can not do %d byte %srelocation"), |
252b5132 | 2180 | fixp->fx_size, |
5f8075fa AM |
2181 | fixp->fx_pcrel ? _("pc-relative") : ""); |
2182 | } | |
252b5132 RH |
2183 | break; |
2184 | } | |
2185 | ||
ea1562b3 NC |
2186 | rel = xmalloc (sizeof (arelent)); |
2187 | rel->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); | |
310b5aa2 | 2188 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
2189 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; |
2190 | /* Always pass the addend along! */ | |
2191 | rel->addend = fixp->fx_addnumber; | |
2192 | ||
2193 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); | |
a75214e5 | 2194 | |
252b5132 RH |
2195 | if (rel->howto == NULL) |
2196 | { | |
2197 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
5f8075fa AM |
2198 | _("Cannot represent relocation type %s"), |
2199 | bfd_get_reloc_code_name (code)); | |
a75214e5 | 2200 | |
252b5132 RH |
2201 | /* Set howto to a garbage value so that we can keep going. */ |
2202 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 2203 | gas_assert (rel->howto != NULL); |
252b5132 RH |
2204 | } |
2205 | ||
2206 | return rel; | |
2207 | } | |
2208 | ||
2209 | #ifdef OBJ_ELF | |
2210 | /* See whether we need to force a relocation into the output file. | |
2211 | This is used to force out switch and PC relative relocations when | |
2212 | relaxing. */ | |
2213 | int | |
ea1562b3 | 2214 | mcore_force_relocation (fixS * fix) |
252b5132 | 2215 | { |
ae6063d4 | 2216 | if (fix->fx_r_type == BFD_RELOC_RVA) |
252b5132 RH |
2217 | return 1; |
2218 | ||
ae6063d4 | 2219 | return generic_force_reloc (fix); |
252b5132 RH |
2220 | } |
2221 | ||
2222 | /* Return true if the fix can be handled by GAS, false if it must | |
2223 | be passed through to the linker. */ | |
ea1562b3 | 2224 | |
b34976b6 | 2225 | bfd_boolean |
ea1562b3 | 2226 | mcore_fix_adjustable (fixS * fixP) |
252b5132 | 2227 | { |
252b5132 RH |
2228 | /* We need the symbol name for the VTABLE entries. */ |
2229 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
2230 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
2231 | return 0; | |
2232 | ||
2233 | return 1; | |
2234 | } | |
252b5132 | 2235 | #endif /* OBJ_ELF */ |