Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
45dfa85a | 3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 |
c67a084a | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
741fe287 | 93 | #define ATREG 1 |
df58fc94 RS |
94 | #define S0 16 |
95 | #define S7 23 | |
252b5132 RH |
96 | #define TREG 24 |
97 | #define PIC_CALL_REG 25 | |
98 | #define KT0 26 | |
99 | #define KT1 27 | |
100 | #define GP 28 | |
101 | #define SP 29 | |
102 | #define FP 30 | |
103 | #define RA 31 | |
104 | ||
105 | #define ILLEGAL_REG (32) | |
106 | ||
741fe287 MR |
107 | #define AT mips_opts.at |
108 | ||
252b5132 RH |
109 | /* Allow override of standard little-endian ECOFF format. */ |
110 | ||
111 | #ifndef ECOFF_LITTLE_FORMAT | |
112 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
113 | #endif | |
114 | ||
115 | extern int target_big_endian; | |
116 | ||
252b5132 | 117 | /* The name of the readonly data section. */ |
4d0d148d | 118 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 119 | ? ".rdata" \ |
056350c6 NC |
120 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
121 | ? ".rdata" \ | |
252b5132 RH |
122 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
123 | ? ".rodata" \ | |
124 | : (abort (), "")) | |
125 | ||
a4e06468 RS |
126 | /* Ways in which an instruction can be "appended" to the output. */ |
127 | enum append_method { | |
128 | /* Just add it normally. */ | |
129 | APPEND_ADD, | |
130 | ||
131 | /* Add it normally and then add a nop. */ | |
132 | APPEND_ADD_WITH_NOP, | |
133 | ||
134 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
135 | APPEND_ADD_COMPACT, | |
136 | ||
137 | /* Insert the instruction before the last one. */ | |
138 | APPEND_SWAP | |
139 | }; | |
140 | ||
47e39b9d RS |
141 | /* Information about an instruction, including its format, operands |
142 | and fixups. */ | |
143 | struct mips_cl_insn | |
144 | { | |
145 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
146 | const struct mips_opcode *insn_mo; | |
147 | ||
47e39b9d | 148 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
149 | a copy of INSN_MO->match with the operands filled in. If we have |
150 | decided to use an extended MIPS16 instruction, this includes the | |
151 | extension. */ | |
47e39b9d RS |
152 | unsigned long insn_opcode; |
153 | ||
154 | /* The frag that contains the instruction. */ | |
155 | struct frag *frag; | |
156 | ||
157 | /* The offset into FRAG of the first instruction byte. */ | |
158 | long where; | |
159 | ||
160 | /* The relocs associated with the instruction, if any. */ | |
161 | fixS *fixp[3]; | |
162 | ||
a38419a5 RS |
163 | /* True if this entry cannot be moved from its current position. */ |
164 | unsigned int fixed_p : 1; | |
47e39b9d | 165 | |
708587a4 | 166 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
167 | unsigned int noreorder_p : 1; |
168 | ||
2fa15973 RS |
169 | /* True for mips16 instructions that jump to an absolute address. */ |
170 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
171 | |
172 | /* True if this instruction is complete. */ | |
173 | unsigned int complete_p : 1; | |
47e39b9d RS |
174 | }; |
175 | ||
a325df1d TS |
176 | /* The ABI to use. */ |
177 | enum mips_abi_level | |
178 | { | |
179 | NO_ABI = 0, | |
180 | O32_ABI, | |
181 | O64_ABI, | |
182 | N32_ABI, | |
183 | N64_ABI, | |
184 | EABI_ABI | |
185 | }; | |
186 | ||
187 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 188 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 189 | |
143d77c5 EC |
190 | /* Whether or not we have code that can call pic code. */ |
191 | int mips_abicalls = FALSE; | |
192 | ||
aa6975fb ILT |
193 | /* Whether or not we have code which can be put into a shared |
194 | library. */ | |
195 | static bfd_boolean mips_in_shared = TRUE; | |
196 | ||
252b5132 RH |
197 | /* This is the set of options which may be modified by the .set |
198 | pseudo-op. We use a struct so that .set push and .set pop are more | |
199 | reliable. */ | |
200 | ||
e972090a NC |
201 | struct mips_set_options |
202 | { | |
252b5132 RH |
203 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
204 | if it has not been initialized. Changed by `.set mipsN', and the | |
205 | -mipsN command line option, and the default CPU. */ | |
206 | int isa; | |
1f25f5d3 CD |
207 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
208 | if they have not been initialized. Changed by `.set <asename>', by | |
209 | command line options, and based on the default architecture. */ | |
210 | int ase_mips3d; | |
deec1734 | 211 | int ase_mdmx; |
e16bfa71 | 212 | int ase_smartmips; |
74cd071d | 213 | int ase_dsp; |
8b082fb1 | 214 | int ase_dspr2; |
ef2e4d86 | 215 | int ase_mt; |
dec0624d | 216 | int ase_mcu; |
252b5132 RH |
217 | /* Whether we are assembling for the mips16 processor. 0 if we are |
218 | not, 1 if we are, and -1 if the value has not been initialized. | |
219 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
220 | -nomips16 command line options, and the default CPU. */ | |
221 | int mips16; | |
df58fc94 RS |
222 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
223 | 1 if we are, and -1 if the value has not been initialized. Changed | |
224 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
225 | and -mno-micromips command line options, and the default CPU. */ | |
226 | int micromips; | |
252b5132 RH |
227 | /* Non-zero if we should not reorder instructions. Changed by `.set |
228 | reorder' and `.set noreorder'. */ | |
229 | int noreorder; | |
741fe287 MR |
230 | /* Non-zero if we should not permit the register designated "assembler |
231 | temporary" to be used in instructions. The value is the register | |
232 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
233 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
234 | unsigned int at; | |
252b5132 RH |
235 | /* Non-zero if we should warn when a macro instruction expands into |
236 | more than one machine instruction. Changed by `.set nomacro' and | |
237 | `.set macro'. */ | |
238 | int warn_about_macros; | |
239 | /* Non-zero if we should not move instructions. Changed by `.set | |
240 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
241 | int nomove; | |
242 | /* Non-zero if we should not optimize branches by moving the target | |
243 | of the branch into the delay slot. Actually, we don't perform | |
244 | this optimization anyhow. Changed by `.set bopt' and `.set | |
245 | nobopt'. */ | |
246 | int nobopt; | |
247 | /* Non-zero if we should not autoextend mips16 instructions. | |
248 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
249 | int noautoextend; | |
a325df1d TS |
250 | /* Restrict general purpose registers and floating point registers |
251 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
252 | is passed but can changed if the assembler code uses .set mipsN. */ | |
253 | int gp32; | |
254 | int fp32; | |
fef14a42 TS |
255 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
256 | command line option, and the default CPU. */ | |
257 | int arch; | |
aed1a261 RS |
258 | /* True if ".set sym32" is in effect. */ |
259 | bfd_boolean sym32; | |
037b32b9 AN |
260 | /* True if floating-point operations are not allowed. Changed by .set |
261 | softfloat or .set hardfloat, by command line options -msoft-float or | |
262 | -mhard-float. The default is false. */ | |
263 | bfd_boolean soft_float; | |
264 | ||
265 | /* True if only single-precision floating-point operations are allowed. | |
266 | Changed by .set singlefloat or .set doublefloat, command-line options | |
267 | -msingle-float or -mdouble-float. The default is false. */ | |
268 | bfd_boolean single_float; | |
252b5132 RH |
269 | }; |
270 | ||
037b32b9 AN |
271 | /* This is the struct we use to hold the current set of options. Note |
272 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
273 | -1 to indicate that they have not been initialized. */ | |
274 | ||
a325df1d | 275 | /* True if -mgp32 was passed. */ |
a8e8e863 | 276 | static int file_mips_gp32 = -1; |
a325df1d TS |
277 | |
278 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 279 | static int file_mips_fp32 = -1; |
a325df1d | 280 | |
037b32b9 AN |
281 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
282 | static int file_mips_soft_float = 0; | |
283 | ||
284 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
285 | static int file_mips_single_float = 0; | |
252b5132 | 286 | |
e972090a NC |
287 | static struct mips_set_options mips_opts = |
288 | { | |
037b32b9 AN |
289 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
290 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
dec0624d MR |
291 | /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0, |
292 | /* at */ ATREG, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, | |
037b32b9 AN |
293 | /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, |
294 | /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 295 | }; |
252b5132 RH |
296 | |
297 | /* These variables are filled in with the masks of registers used. | |
298 | The object format code reads them and puts them in the appropriate | |
299 | place. */ | |
300 | unsigned long mips_gprmask; | |
301 | unsigned long mips_cprmask[4]; | |
302 | ||
303 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 304 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 305 | |
738f4d98 | 306 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
307 | static int file_ase_mips16; |
308 | ||
3994f87e TS |
309 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
310 | || mips_opts.isa == ISA_MIPS32R2 \ | |
311 | || mips_opts.isa == ISA_MIPS64 \ | |
312 | || mips_opts.isa == ISA_MIPS64R2) | |
313 | ||
df58fc94 RS |
314 | /* True if any microMIPS code was produced. */ |
315 | static int file_ase_micromips; | |
316 | ||
b12dd2e4 CF |
317 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
318 | #ifdef TE_IRIX | |
1180b5a4 | 319 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 320 | #else |
1180b5a4 RS |
321 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
322 | because there's no place for any addend, the only acceptable | |
323 | expression is a bare symbol. */ | |
324 | #define MIPS_JALR_HINT_P(EXPR) \ | |
325 | (!HAVE_IN_PLACE_ADDENDS \ | |
326 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
327 | #endif |
328 | ||
1f25f5d3 CD |
329 | /* True if -mips3d was passed or implied by arguments passed on the |
330 | command line (e.g., by -march). */ | |
331 | static int file_ase_mips3d; | |
332 | ||
deec1734 CD |
333 | /* True if -mdmx was passed or implied by arguments passed on the |
334 | command line (e.g., by -march). */ | |
335 | static int file_ase_mdmx; | |
336 | ||
e16bfa71 TS |
337 | /* True if -msmartmips was passed or implied by arguments passed on the |
338 | command line (e.g., by -march). */ | |
339 | static int file_ase_smartmips; | |
340 | ||
ad3fea08 TS |
341 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
342 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 343 | |
74cd071d CF |
344 | /* True if -mdsp was passed or implied by arguments passed on the |
345 | command line (e.g., by -march). */ | |
346 | static int file_ase_dsp; | |
347 | ||
ad3fea08 | 348 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
03f66e8a MR |
349 | || mips_opts.isa == ISA_MIPS64R2 \ |
350 | || mips_opts.micromips) | |
ad3fea08 | 351 | |
65263ce3 TS |
352 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
353 | ||
8b082fb1 TS |
354 | /* True if -mdspr2 was passed or implied by arguments passed on the |
355 | command line (e.g., by -march). */ | |
356 | static int file_ase_dspr2; | |
357 | ||
358 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
03f66e8a MR |
359 | || mips_opts.isa == ISA_MIPS64R2 \ |
360 | || mips_opts.micromips) | |
8b082fb1 | 361 | |
ef2e4d86 CF |
362 | /* True if -mmt was passed or implied by arguments passed on the |
363 | command line (e.g., by -march). */ | |
364 | static int file_ase_mt; | |
365 | ||
ad3fea08 TS |
366 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
367 | || mips_opts.isa == ISA_MIPS64R2) | |
368 | ||
dec0624d | 369 | #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
9ddc84cc MR |
370 | || mips_opts.isa == ISA_MIPS64R2 \ |
371 | || mips_opts.micromips) | |
dec0624d | 372 | |
ec68c924 | 373 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 374 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 375 | static const char *mips_arch_string; |
ec68c924 EC |
376 | |
377 | /* The argument of the -mtune= flag. The architecture for which we | |
378 | are optimizing. */ | |
379 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 380 | static const char *mips_tune_string; |
ec68c924 | 381 | |
316f5878 | 382 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
383 | static int mips_32bitmode = 0; |
384 | ||
316f5878 RS |
385 | /* True if the given ABI requires 32-bit registers. */ |
386 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
387 | ||
388 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
389 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
390 | ((ABI) == N32_ABI \ | |
391 | || (ABI) == N64_ABI \ | |
316f5878 RS |
392 | || (ABI) == O64_ABI) |
393 | ||
ad3fea08 | 394 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
395 | #define ISA_HAS_64BIT_REGS(ISA) \ |
396 | ((ISA) == ISA_MIPS3 \ | |
397 | || (ISA) == ISA_MIPS4 \ | |
398 | || (ISA) == ISA_MIPS5 \ | |
399 | || (ISA) == ISA_MIPS64 \ | |
400 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 401 | |
ad3fea08 TS |
402 | /* Return true if ISA supports 64 bit wide float registers. */ |
403 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
404 | ((ISA) == ISA_MIPS3 \ | |
405 | || (ISA) == ISA_MIPS4 \ | |
406 | || (ISA) == ISA_MIPS5 \ | |
407 | || (ISA) == ISA_MIPS32R2 \ | |
408 | || (ISA) == ISA_MIPS64 \ | |
409 | || (ISA) == ISA_MIPS64R2) | |
410 | ||
af7ee8bf CD |
411 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
412 | instructions. */ | |
707bfff6 | 413 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 RS |
414 | ((ISA) == ISA_MIPS64R2 \ |
415 | || (mips_opts.micromips \ | |
416 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
417 | ) | |
af7ee8bf CD |
418 | |
419 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
420 | instructions. */ | |
707bfff6 TS |
421 | #define ISA_HAS_ROR(ISA) \ |
422 | ((ISA) == ISA_MIPS32R2 \ | |
423 | || (ISA) == ISA_MIPS64R2 \ | |
df58fc94 RS |
424 | || mips_opts.ase_smartmips \ |
425 | || mips_opts.micromips \ | |
426 | ) | |
707bfff6 | 427 | |
7455baf8 TS |
428 | /* Return true if ISA supports single-precision floats in odd registers. */ |
429 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
430 | ((ISA) == ISA_MIPS32 \ | |
431 | || (ISA) == ISA_MIPS32R2 \ | |
432 | || (ISA) == ISA_MIPS64 \ | |
433 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 434 | |
ad3fea08 TS |
435 | /* Return true if ISA supports move to/from high part of a 64-bit |
436 | floating-point register. */ | |
437 | #define ISA_HAS_MXHC1(ISA) \ | |
438 | ((ISA) == ISA_MIPS32R2 \ | |
439 | || (ISA) == ISA_MIPS64R2) | |
440 | ||
e013f690 | 441 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 442 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 443 | |
e013f690 | 444 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 445 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 446 | |
ad3fea08 TS |
447 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
448 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 449 | |
316f5878 | 450 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 451 | |
316f5878 | 452 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 453 | |
3b91255e RS |
454 | /* True if relocations are stored in-place. */ |
455 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
456 | ||
aed1a261 RS |
457 | /* The ABI-derived address size. */ |
458 | #define HAVE_64BIT_ADDRESSES \ | |
459 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
460 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 461 | |
aed1a261 RS |
462 | /* The size of symbolic constants (i.e., expressions of the form |
463 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
464 | #define HAVE_32BIT_SYMBOLS \ | |
465 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
466 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 467 | |
b7c7d6c1 TS |
468 | /* Addresses are loaded in different ways, depending on the address size |
469 | in use. The n32 ABI Documentation also mandates the use of additions | |
470 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 471 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 472 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
473 | |
474 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 475 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
476 | |
477 | #define ADDRESS_LOAD_INSN \ | |
478 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
479 | ||
480 | #define ADDRESS_STORE_INSN \ | |
481 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
482 | ||
a4672219 | 483 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
484 | #define CPU_HAS_MIPS16(cpu) \ |
485 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
486 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 487 | |
2309ddf2 | 488 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
489 | #define CPU_HAS_MICROMIPS(cpu) 0 |
490 | ||
60b63b72 RS |
491 | /* True if CPU has a dror instruction. */ |
492 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
493 | ||
494 | /* True if CPU has a ror instruction. */ | |
495 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
496 | ||
dd6a37e7 | 497 | /* True if CPU is in the Octeon family */ |
432233b3 | 498 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2) |
dd6a37e7 | 499 | |
dd3cbb7e | 500 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 501 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 502 | |
c8978940 CD |
503 | /* True if mflo and mfhi can be immediately followed by instructions |
504 | which write to the HI and LO registers. | |
505 | ||
506 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
507 | (at least) two instructions between the reads of HI/LO and | |
508 | instructions which write them, and later ISAs do not. Contradicting | |
509 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
510 | the UM for the NEC Vr5000) document needing the instructions between | |
511 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
512 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
513 | earlier-ISA CPUs for which CPU documentation declares that the | |
514 | instructions are really interlocked. */ | |
515 | #define hilo_interlocks \ | |
516 | (mips_opts.isa == ISA_MIPS32 \ | |
517 | || mips_opts.isa == ISA_MIPS32R2 \ | |
518 | || mips_opts.isa == ISA_MIPS64 \ | |
519 | || mips_opts.isa == ISA_MIPS64R2 \ | |
520 | || mips_opts.arch == CPU_R4010 \ | |
521 | || mips_opts.arch == CPU_R10000 \ | |
522 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
523 | || mips_opts.arch == CPU_R14000 \ |
524 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 525 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 526 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 527 | || mips_opts.micromips \ |
c8978940 | 528 | ) |
252b5132 RH |
529 | |
530 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
531 | from the GPRs after they are loaded from memory, and thus does not |
532 | require nops to be inserted. This applies to instructions marked | |
533 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
df58fc94 RS |
534 | level I and microMIPS mode instructions are always interlocked. */ |
535 | #define gpr_interlocks \ | |
536 | (mips_opts.isa != ISA_MIPS1 \ | |
537 | || mips_opts.arch == CPU_R3900 \ | |
538 | || mips_opts.micromips \ | |
539 | ) | |
252b5132 | 540 | |
81912461 ILT |
541 | /* Whether the processor uses hardware interlocks to avoid delays |
542 | required by coprocessor instructions, and thus does not require | |
543 | nops to be inserted. This applies to instructions marked | |
544 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
545 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
546 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
df58fc94 RS |
547 | levels I, II, and III and microMIPS mode instructions are always |
548 | interlocked. */ | |
bdaaa2e1 | 549 | /* Itbl support may require additional care here. */ |
81912461 ILT |
550 | #define cop_interlocks \ |
551 | ((mips_opts.isa != ISA_MIPS1 \ | |
552 | && mips_opts.isa != ISA_MIPS2 \ | |
553 | && mips_opts.isa != ISA_MIPS3) \ | |
554 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 555 | || mips_opts.micromips \ |
81912461 ILT |
556 | ) |
557 | ||
558 | /* Whether the processor uses hardware interlocks to protect reads | |
559 | from coprocessor registers after they are loaded from memory, and | |
560 | thus does not require nops to be inserted. This applies to | |
561 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
562 | requires at MIPS ISA level I and microMIPS mode instructions are |
563 | always interlocked. */ | |
564 | #define cop_mem_interlocks \ | |
565 | (mips_opts.isa != ISA_MIPS1 \ | |
566 | || mips_opts.micromips \ | |
567 | ) | |
252b5132 | 568 | |
6b76fefe CM |
569 | /* Is this a mfhi or mflo instruction? */ |
570 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
571 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
572 | ||
df58fc94 RS |
573 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
574 | has been selected. This implies, in particular, that addresses of text | |
575 | labels have their LSB set. */ | |
576 | #define HAVE_CODE_COMPRESSION \ | |
577 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
578 | ||
252b5132 RH |
579 | /* MIPS PIC level. */ |
580 | ||
a161fe53 | 581 | enum mips_pic_level mips_pic; |
252b5132 | 582 | |
c9914766 | 583 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 584 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 585 | static int mips_big_got = 0; |
252b5132 RH |
586 | |
587 | /* 1 if trap instructions should used for overflow rather than break | |
588 | instructions. */ | |
c9914766 | 589 | static int mips_trap = 0; |
252b5132 | 590 | |
119d663a | 591 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 592 | by assembling two single width halves into two single width floating |
119d663a NC |
593 | point registers which just happen to alias the double width destination |
594 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 595 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
596 | automatically at assemble time. */ |
597 | static int mips_disable_float_construction; | |
598 | ||
252b5132 RH |
599 | /* Non-zero if any .set noreorder directives were used. */ |
600 | ||
601 | static int mips_any_noreorder; | |
602 | ||
6b76fefe CM |
603 | /* Non-zero if nops should be inserted when the register referenced in |
604 | an mfhi/mflo instruction is read in the next two instructions. */ | |
605 | static int mips_7000_hilo_fix; | |
606 | ||
02ffd3e4 | 607 | /* The size of objects in the small data section. */ |
156c2f8b | 608 | static unsigned int g_switch_value = 8; |
252b5132 RH |
609 | /* Whether the -G option was used. */ |
610 | static int g_switch_seen = 0; | |
611 | ||
612 | #define N_RMASK 0xc4 | |
613 | #define N_VFP 0xd4 | |
614 | ||
615 | /* If we can determine in advance that GP optimization won't be | |
616 | possible, we can skip the relaxation stuff that tries to produce | |
617 | GP-relative references. This makes delay slot optimization work | |
618 | better. | |
619 | ||
620 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
621 | gcc output. It needs to guess right for gcc, otherwise gcc |
622 | will put what it thinks is a GP-relative instruction in a branch | |
623 | delay slot. | |
252b5132 RH |
624 | |
625 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
626 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 627 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
628 | |
629 | /* handle of the OPCODE hash table */ | |
630 | static struct hash_control *op_hash = NULL; | |
631 | ||
632 | /* The opcode hash table we use for the mips16. */ | |
633 | static struct hash_control *mips16_op_hash = NULL; | |
634 | ||
df58fc94 RS |
635 | /* The opcode hash table we use for the microMIPS ASE. */ |
636 | static struct hash_control *micromips_op_hash = NULL; | |
637 | ||
252b5132 RH |
638 | /* This array holds the chars that always start a comment. If the |
639 | pre-processor is disabled, these aren't very useful */ | |
640 | const char comment_chars[] = "#"; | |
641 | ||
642 | /* This array holds the chars that only start a comment at the beginning of | |
643 | a line. If the line seems to have the form '# 123 filename' | |
644 | .line and .file directives will appear in the pre-processed output */ | |
645 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
646 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 647 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
648 | /* Also note that C style comments are always supported. */ |
649 | const char line_comment_chars[] = "#"; | |
650 | ||
bdaaa2e1 | 651 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 652 | const char line_separator_chars[] = ";"; |
252b5132 RH |
653 | |
654 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
655 | const char EXP_CHARS[] = "eE"; | |
656 | ||
657 | /* Chars that mean this number is a floating point constant */ | |
658 | /* As in 0f12.456 */ | |
659 | /* or 0d1.2345e12 */ | |
660 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
661 | ||
662 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
663 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
664 | but nothing is ideal around here. | |
665 | */ | |
666 | ||
667 | static char *insn_error; | |
668 | ||
669 | static int auto_align = 1; | |
670 | ||
671 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
672 | offset in the stack frame from which to restore the $gp register. | |
673 | This is set by the .cprestore pseudo-op, and saved in this | |
674 | variable. */ | |
675 | static offsetT mips_cprestore_offset = -1; | |
676 | ||
67c1ffbe | 677 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 678 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 679 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
680 | static offsetT mips_cpreturn_offset = -1; |
681 | static int mips_cpreturn_register = -1; | |
682 | static int mips_gp_register = GP; | |
def2e0dd | 683 | static int mips_gprel_offset = 0; |
6478892d | 684 | |
7a621144 DJ |
685 | /* Whether mips_cprestore_offset has been set in the current function |
686 | (or whether it has already been warned about, if not). */ | |
687 | static int mips_cprestore_valid = 0; | |
688 | ||
252b5132 RH |
689 | /* This is the register which holds the stack frame, as set by the |
690 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
691 | static int mips_frame_reg = SP; | |
692 | ||
7a621144 DJ |
693 | /* Whether mips_frame_reg has been set in the current function |
694 | (or whether it has already been warned about, if not). */ | |
695 | static int mips_frame_reg_valid = 0; | |
696 | ||
252b5132 RH |
697 | /* To output NOP instructions correctly, we need to keep information |
698 | about the previous two instructions. */ | |
699 | ||
700 | /* Whether we are optimizing. The default value of 2 means to remove | |
701 | unneeded NOPs and swap branch instructions when possible. A value | |
702 | of 1 means to not swap branches. A value of 0 means to always | |
703 | insert NOPs. */ | |
704 | static int mips_optimize = 2; | |
705 | ||
706 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
707 | equivalent to seeing no -g option at all. */ | |
708 | static int mips_debug = 0; | |
709 | ||
7d8e00cf RS |
710 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
711 | #define MAX_VR4130_NOPS 4 | |
712 | ||
713 | /* The maximum number of NOPs needed to fill delay slots. */ | |
714 | #define MAX_DELAY_NOPS 2 | |
715 | ||
716 | /* The maximum number of NOPs needed for any purpose. */ | |
717 | #define MAX_NOPS 4 | |
71400594 RS |
718 | |
719 | /* A list of previous instructions, with index 0 being the most recent. | |
720 | We need to look back MAX_NOPS instructions when filling delay slots | |
721 | or working around processor errata. We need to look back one | |
722 | instruction further if we're thinking about using history[0] to | |
723 | fill a branch delay slot. */ | |
724 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 725 | |
1e915849 | 726 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
727 | static struct mips_cl_insn nop_insn; |
728 | static struct mips_cl_insn mips16_nop_insn; | |
729 | static struct mips_cl_insn micromips_nop16_insn; | |
730 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
731 | |
732 | /* The appropriate nop for the current mode. */ | |
df58fc94 RS |
733 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \ |
734 | : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn)) | |
735 | ||
736 | /* The size of NOP_INSN in bytes. */ | |
737 | #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4) | |
252b5132 | 738 | |
252b5132 RH |
739 | /* If this is set, it points to a frag holding nop instructions which |
740 | were inserted before the start of a noreorder section. If those | |
741 | nops turn out to be unnecessary, the size of the frag can be | |
742 | decreased. */ | |
743 | static fragS *prev_nop_frag; | |
744 | ||
745 | /* The number of nop instructions we created in prev_nop_frag. */ | |
746 | static int prev_nop_frag_holds; | |
747 | ||
748 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 749 | prev_nop_frag. */ |
252b5132 RH |
750 | static int prev_nop_frag_required; |
751 | ||
752 | /* The number of instructions we've seen since prev_nop_frag. */ | |
753 | static int prev_nop_frag_since; | |
754 | ||
755 | /* For ECOFF and ELF, relocations against symbols are done in two | |
756 | parts, with a HI relocation and a LO relocation. Each relocation | |
757 | has only 16 bits of space to store an addend. This means that in | |
758 | order for the linker to handle carries correctly, it must be able | |
759 | to locate both the HI and the LO relocation. This means that the | |
760 | relocations must appear in order in the relocation table. | |
761 | ||
762 | In order to implement this, we keep track of each unmatched HI | |
763 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 764 | corresponding LO relocation. */ |
252b5132 | 765 | |
e972090a NC |
766 | struct mips_hi_fixup |
767 | { | |
252b5132 RH |
768 | /* Next HI fixup. */ |
769 | struct mips_hi_fixup *next; | |
770 | /* This fixup. */ | |
771 | fixS *fixp; | |
772 | /* The section this fixup is in. */ | |
773 | segT seg; | |
774 | }; | |
775 | ||
776 | /* The list of unmatched HI relocs. */ | |
777 | ||
778 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
779 | ||
64bdfcaf RS |
780 | /* The frag containing the last explicit relocation operator. |
781 | Null if explicit relocations have not been used. */ | |
782 | ||
783 | static fragS *prev_reloc_op_frag; | |
784 | ||
252b5132 RH |
785 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
786 | ||
787 | #define X ILLEGAL_REG | |
e972090a NC |
788 | static const int mips32_to_16_reg_map[] = |
789 | { | |
252b5132 RH |
790 | X, X, 2, 3, 4, 5, 6, 7, |
791 | X, X, X, X, X, X, X, X, | |
792 | 0, 1, X, X, X, X, X, X, | |
793 | X, X, X, X, X, X, X, X | |
794 | }; | |
795 | #undef X | |
796 | ||
797 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
798 | ||
e972090a NC |
799 | static const unsigned int mips16_to_32_reg_map[] = |
800 | { | |
252b5132 RH |
801 | 16, 17, 2, 3, 4, 5, 6, 7 |
802 | }; | |
60b63b72 | 803 | |
df58fc94 RS |
804 | /* Map normal MIPS register numbers to microMIPS register numbers. */ |
805 | ||
806 | #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map | |
807 | #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map | |
808 | #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map | |
809 | #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map | |
810 | #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map | |
811 | #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map | |
812 | #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map | |
813 | ||
814 | #define X ILLEGAL_REG | |
815 | /* reg type h: 4, 5, 6. */ | |
816 | static const int mips32_to_micromips_reg_h_map[] = | |
817 | { | |
818 | X, X, X, X, 4, 5, 6, X, | |
819 | X, X, X, X, X, X, X, X, | |
820 | X, X, X, X, X, X, X, X, | |
821 | X, X, X, X, X, X, X, X | |
822 | }; | |
823 | ||
824 | /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */ | |
825 | static const int mips32_to_micromips_reg_m_map[] = | |
826 | { | |
827 | 0, X, 2, 3, X, X, X, X, | |
828 | X, X, X, X, X, X, X, X, | |
829 | 4, 1, 5, 6, 7, X, X, X, | |
830 | X, X, X, X, X, X, X, X | |
831 | }; | |
832 | ||
833 | /* reg type q: 0, 2-7. 17. */ | |
834 | static const int mips32_to_micromips_reg_q_map[] = | |
835 | { | |
836 | 0, X, 2, 3, 4, 5, 6, 7, | |
837 | X, X, X, X, X, X, X, X, | |
838 | X, 1, X, X, X, X, X, X, | |
839 | X, X, X, X, X, X, X, X | |
840 | }; | |
841 | ||
842 | #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map | |
843 | #undef X | |
844 | ||
845 | /* Map microMIPS register numbers to normal MIPS register numbers. */ | |
846 | ||
847 | #define micromips_to_32_reg_b_map mips16_to_32_reg_map | |
848 | #define micromips_to_32_reg_c_map mips16_to_32_reg_map | |
849 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map | |
850 | #define micromips_to_32_reg_e_map mips16_to_32_reg_map | |
851 | #define micromips_to_32_reg_f_map mips16_to_32_reg_map | |
852 | #define micromips_to_32_reg_g_map mips16_to_32_reg_map | |
853 | ||
854 | /* The microMIPS registers with type h. */ | |
855 | static const unsigned int micromips_to_32_reg_h_map[] = | |
856 | { | |
857 | 5, 5, 6, 4, 4, 4, 4, 4 | |
858 | }; | |
859 | ||
860 | /* The microMIPS registers with type i. */ | |
861 | static const unsigned int micromips_to_32_reg_i_map[] = | |
862 | { | |
863 | 6, 7, 7, 21, 22, 5, 6, 7 | |
864 | }; | |
865 | ||
866 | #define micromips_to_32_reg_l_map mips16_to_32_reg_map | |
867 | ||
868 | /* The microMIPS registers with type m. */ | |
869 | static const unsigned int micromips_to_32_reg_m_map[] = | |
870 | { | |
871 | 0, 17, 2, 3, 16, 18, 19, 20 | |
872 | }; | |
873 | ||
874 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
875 | ||
876 | /* The microMIPS registers with type q. */ | |
877 | static const unsigned int micromips_to_32_reg_q_map[] = | |
878 | { | |
879 | 0, 17, 2, 3, 4, 5, 6, 7 | |
880 | }; | |
881 | ||
882 | /* microMIPS imm type B. */ | |
883 | static const int micromips_imm_b_map[] = | |
884 | { | |
885 | 1, 4, 8, 12, 16, 20, 24, -1 | |
886 | }; | |
887 | ||
888 | /* microMIPS imm type C. */ | |
889 | static const int micromips_imm_c_map[] = | |
890 | { | |
891 | 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535 | |
892 | }; | |
893 | ||
71400594 RS |
894 | /* Classifies the kind of instructions we're interested in when |
895 | implementing -mfix-vr4120. */ | |
c67a084a NC |
896 | enum fix_vr4120_class |
897 | { | |
71400594 RS |
898 | FIX_VR4120_MACC, |
899 | FIX_VR4120_DMACC, | |
900 | FIX_VR4120_MULT, | |
901 | FIX_VR4120_DMULT, | |
902 | FIX_VR4120_DIV, | |
903 | FIX_VR4120_MTHILO, | |
904 | NUM_FIX_VR4120_CLASSES | |
905 | }; | |
906 | ||
c67a084a NC |
907 | /* ...likewise -mfix-loongson2f-jump. */ |
908 | static bfd_boolean mips_fix_loongson2f_jump; | |
909 | ||
910 | /* ...likewise -mfix-loongson2f-nop. */ | |
911 | static bfd_boolean mips_fix_loongson2f_nop; | |
912 | ||
913 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
914 | static bfd_boolean mips_fix_loongson2f; | |
915 | ||
71400594 RS |
916 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
917 | there must be at least one other instruction between an instruction | |
918 | of type X and an instruction of type Y. */ | |
919 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
920 | ||
921 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 922 | static int mips_fix_vr4120; |
4a6a3df4 | 923 | |
7d8e00cf RS |
924 | /* ...likewise -mfix-vr4130. */ |
925 | static int mips_fix_vr4130; | |
926 | ||
6a32d874 CM |
927 | /* ...likewise -mfix-24k. */ |
928 | static int mips_fix_24k; | |
929 | ||
d954098f DD |
930 | /* ...likewise -mfix-cn63xxp1 */ |
931 | static bfd_boolean mips_fix_cn63xxp1; | |
932 | ||
4a6a3df4 AO |
933 | /* We don't relax branches by default, since this causes us to expand |
934 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
935 | fail to compute the offset before expanding the macro to the most | |
936 | efficient expansion. */ | |
937 | ||
938 | static int mips_relax_branch; | |
252b5132 | 939 | \f |
4d7206a2 RS |
940 | /* The expansion of many macros depends on the type of symbol that |
941 | they refer to. For example, when generating position-dependent code, | |
942 | a macro that refers to a symbol may have two different expansions, | |
943 | one which uses GP-relative addresses and one which uses absolute | |
944 | addresses. When generating SVR4-style PIC, a macro may have | |
945 | different expansions for local and global symbols. | |
946 | ||
947 | We handle these situations by generating both sequences and putting | |
948 | them in variant frags. In position-dependent code, the first sequence | |
949 | will be the GP-relative one and the second sequence will be the | |
950 | absolute one. In SVR4 PIC, the first sequence will be for global | |
951 | symbols and the second will be for local symbols. | |
952 | ||
584892a6 RS |
953 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
954 | SECOND are the lengths of the two sequences in bytes. These fields | |
955 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
956 | the subtype has the following flags: | |
4d7206a2 | 957 | |
584892a6 RS |
958 | RELAX_USE_SECOND |
959 | Set if it has been decided that we should use the second | |
960 | sequence instead of the first. | |
961 | ||
962 | RELAX_SECOND_LONGER | |
963 | Set in the first variant frag if the macro's second implementation | |
964 | is longer than its first. This refers to the macro as a whole, | |
965 | not an individual relaxation. | |
966 | ||
967 | RELAX_NOMACRO | |
968 | Set in the first variant frag if the macro appeared in a .set nomacro | |
969 | block and if one alternative requires a warning but the other does not. | |
970 | ||
971 | RELAX_DELAY_SLOT | |
972 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
973 | delay slot. | |
4d7206a2 | 974 | |
df58fc94 RS |
975 | RELAX_DELAY_SLOT_16BIT |
976 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
977 | 16-bit instruction. | |
978 | ||
979 | RELAX_DELAY_SLOT_SIZE_FIRST | |
980 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
981 | the macro is of the wrong size for the branch delay slot. | |
982 | ||
983 | RELAX_DELAY_SLOT_SIZE_SECOND | |
984 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
985 | the macro is of the wrong size for the branch delay slot. | |
986 | ||
4d7206a2 RS |
987 | The frag's "opcode" points to the first fixup for relaxable code. |
988 | ||
989 | Relaxable macros are generated using a sequence such as: | |
990 | ||
991 | relax_start (SYMBOL); | |
992 | ... generate first expansion ... | |
993 | relax_switch (); | |
994 | ... generate second expansion ... | |
995 | relax_end (); | |
996 | ||
997 | The code and fixups for the unwanted alternative are discarded | |
998 | by md_convert_frag. */ | |
584892a6 | 999 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 1000 | |
584892a6 RS |
1001 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1002 | #define RELAX_SECOND(X) ((X) & 0xff) | |
1003 | #define RELAX_USE_SECOND 0x10000 | |
1004 | #define RELAX_SECOND_LONGER 0x20000 | |
1005 | #define RELAX_NOMACRO 0x40000 | |
1006 | #define RELAX_DELAY_SLOT 0x80000 | |
df58fc94 RS |
1007 | #define RELAX_DELAY_SLOT_16BIT 0x100000 |
1008 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 | |
1009 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 | |
252b5132 | 1010 | |
4a6a3df4 AO |
1011 | /* Branch without likely bit. If label is out of range, we turn: |
1012 | ||
1013 | beq reg1, reg2, label | |
1014 | delay slot | |
1015 | ||
1016 | into | |
1017 | ||
1018 | bne reg1, reg2, 0f | |
1019 | nop | |
1020 | j label | |
1021 | 0: delay slot | |
1022 | ||
1023 | with the following opcode replacements: | |
1024 | ||
1025 | beq <-> bne | |
1026 | blez <-> bgtz | |
1027 | bltz <-> bgez | |
1028 | bc1f <-> bc1t | |
1029 | ||
1030 | bltzal <-> bgezal (with jal label instead of j label) | |
1031 | ||
1032 | Even though keeping the delay slot instruction in the delay slot of | |
1033 | the branch would be more efficient, it would be very tricky to do | |
1034 | correctly, because we'd have to introduce a variable frag *after* | |
1035 | the delay slot instruction, and expand that instead. Let's do it | |
1036 | the easy way for now, even if the branch-not-taken case now costs | |
1037 | one additional instruction. Out-of-range branches are not supposed | |
1038 | to be common, anyway. | |
1039 | ||
1040 | Branch likely. If label is out of range, we turn: | |
1041 | ||
1042 | beql reg1, reg2, label | |
1043 | delay slot (annulled if branch not taken) | |
1044 | ||
1045 | into | |
1046 | ||
1047 | beql reg1, reg2, 1f | |
1048 | nop | |
1049 | beql $0, $0, 2f | |
1050 | nop | |
1051 | 1: j[al] label | |
1052 | delay slot (executed only if branch taken) | |
1053 | 2: | |
1054 | ||
1055 | It would be possible to generate a shorter sequence by losing the | |
1056 | likely bit, generating something like: | |
b34976b6 | 1057 | |
4a6a3df4 AO |
1058 | bne reg1, reg2, 0f |
1059 | nop | |
1060 | j[al] label | |
1061 | delay slot (executed only if branch taken) | |
1062 | 0: | |
1063 | ||
1064 | beql -> bne | |
1065 | bnel -> beq | |
1066 | blezl -> bgtz | |
1067 | bgtzl -> blez | |
1068 | bltzl -> bgez | |
1069 | bgezl -> bltz | |
1070 | bc1fl -> bc1t | |
1071 | bc1tl -> bc1f | |
1072 | ||
1073 | bltzall -> bgezal (with jal label instead of j label) | |
1074 | bgezall -> bltzal (ditto) | |
1075 | ||
1076 | ||
1077 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
1078 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
1079 | ((relax_substateT) \ | |
1080 | (0xc0000000 \ | |
1081 | | ((at) & 0x1f) \ | |
1082 | | ((toofar) ? 0x20 : 0) \ | |
1083 | | ((link) ? 0x40 : 0) \ | |
1084 | | ((likely) ? 0x80 : 0) \ | |
1085 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 1086 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
1087 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
1088 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
1089 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
1090 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
1091 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 1092 | |
252b5132 RH |
1093 | /* For mips16 code, we use an entirely different form of relaxation. |
1094 | mips16 supports two versions of most instructions which take | |
1095 | immediate values: a small one which takes some small value, and a | |
1096 | larger one which takes a 16 bit value. Since branches also follow | |
1097 | this pattern, relaxing these values is required. | |
1098 | ||
1099 | We can assemble both mips16 and normal MIPS code in a single | |
1100 | object. Therefore, we need to support this type of relaxation at | |
1101 | the same time that we support the relaxation described above. We | |
1102 | use the high bit of the subtype field to distinguish these cases. | |
1103 | ||
1104 | The information we store for this type of relaxation is the | |
1105 | argument code found in the opcode file for this relocation, whether | |
1106 | the user explicitly requested a small or extended form, and whether | |
1107 | the relocation is in a jump or jal delay slot. That tells us the | |
1108 | size of the value, and how it should be stored. We also store | |
1109 | whether the fragment is considered to be extended or not. We also | |
1110 | store whether this is known to be a branch to a different section, | |
1111 | whether we have tried to relax this frag yet, and whether we have | |
1112 | ever extended a PC relative fragment because of a shift count. */ | |
1113 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
1114 | (0x80000000 \ | |
1115 | | ((type) & 0xff) \ | |
1116 | | ((small) ? 0x100 : 0) \ | |
1117 | | ((ext) ? 0x200 : 0) \ | |
1118 | | ((dslot) ? 0x400 : 0) \ | |
1119 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 1120 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
1121 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
1122 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
1123 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
1124 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
1125 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
1126 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
1127 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
1128 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
1129 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
1130 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
1131 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 | 1132 | |
df58fc94 RS |
1133 | /* For microMIPS code, we use relaxation similar to one we use for |
1134 | MIPS16 code. Some instructions that take immediate values support | |
1135 | two encodings: a small one which takes some small value, and a | |
1136 | larger one which takes a 16 bit value. As some branches also follow | |
1137 | this pattern, relaxing these values is required. | |
1138 | ||
1139 | We can assemble both microMIPS and normal MIPS code in a single | |
1140 | object. Therefore, we need to support this type of relaxation at | |
1141 | the same time that we support the relaxation described above. We | |
1142 | use one of the high bits of the subtype field to distinguish these | |
1143 | cases. | |
1144 | ||
1145 | The information we store for this type of relaxation is the argument | |
1146 | code found in the opcode file for this relocation, the register | |
40209cad MR |
1147 | selected as the assembler temporary, whether the branch is |
1148 | unconditional, whether it is compact, whether it stores the link | |
1149 | address implicitly in $ra, whether relaxation of out-of-range 32-bit | |
1150 | branches to a sequence of instructions is enabled, and whether the | |
1151 | displacement of a branch is too large to fit as an immediate argument | |
1152 | of a 16-bit and a 32-bit branch, respectively. */ | |
1153 | #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \ | |
1154 | relax32, toofar16, toofar32) \ | |
1155 | (0x40000000 \ | |
1156 | | ((type) & 0xff) \ | |
1157 | | (((at) & 0x1f) << 8) \ | |
1158 | | ((uncond) ? 0x2000 : 0) \ | |
1159 | | ((compact) ? 0x4000 : 0) \ | |
1160 | | ((link) ? 0x8000 : 0) \ | |
1161 | | ((relax32) ? 0x10000 : 0) \ | |
1162 | | ((toofar16) ? 0x20000 : 0) \ | |
1163 | | ((toofar32) ? 0x40000 : 0)) | |
df58fc94 RS |
1164 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1165 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1166 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
40209cad MR |
1167 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0) |
1168 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0) | |
1169 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0) | |
1170 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0) | |
1171 | ||
1172 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0) | |
1173 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000) | |
1174 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000) | |
1175 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0) | |
1176 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000) | |
1177 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000) | |
df58fc94 | 1178 | |
43c0598f RS |
1179 | /* Sign-extend 16-bit value X. */ |
1180 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1181 | ||
885add95 CD |
1182 | /* Is the given value a sign-extended 32-bit value? */ |
1183 | #define IS_SEXT_32BIT_NUM(x) \ | |
1184 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1185 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1186 | ||
1187 | /* Is the given value a sign-extended 16-bit value? */ | |
1188 | #define IS_SEXT_16BIT_NUM(x) \ | |
1189 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1190 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1191 | ||
df58fc94 RS |
1192 | /* Is the given value a sign-extended 12-bit value? */ |
1193 | #define IS_SEXT_12BIT_NUM(x) \ | |
1194 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1195 | ||
2051e8c4 MR |
1196 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1197 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1198 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1199 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1200 | ||
bf12938e RS |
1201 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
1202 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
1203 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
1204 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
1205 | | (((VALUE) & (MASK)) << (SHIFT))) | |
1206 | ||
1207 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
1208 | SHIFT places. */ | |
1209 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1210 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1211 | ||
1212 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1213 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1214 | ||
1215 | include/opcode/mips.h specifies operand fields using the macros | |
1216 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1217 | with "MIPS16OP" instead of "OP". */ | |
df58fc94 RS |
1218 | #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \ |
1219 | do \ | |
1220 | if (!(MICROMIPS)) \ | |
1221 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1222 | OP_MASK_##FIELD, OP_SH_##FIELD); \ | |
1223 | else \ | |
1224 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1225 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \ | |
1226 | while (0) | |
bf12938e RS |
1227 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ |
1228 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1229 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1230 | ||
1231 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
df58fc94 RS |
1232 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1233 | (!(MICROMIPS) \ | |
1234 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1235 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1236 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1237 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1238 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1239 | MIPS16OP_MASK_##FIELD, \ | |
1240 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1241 | |
1242 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1243 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1244 | \f |
df58fc94 RS |
1245 | /* Whether or not we are emitting a branch-likely macro. */ |
1246 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1247 | ||
4d7206a2 RS |
1248 | /* Global variables used when generating relaxable macros. See the |
1249 | comment above RELAX_ENCODE for more details about how relaxation | |
1250 | is used. */ | |
1251 | static struct { | |
1252 | /* 0 if we're not emitting a relaxable macro. | |
1253 | 1 if we're emitting the first of the two relaxation alternatives. | |
1254 | 2 if we're emitting the second alternative. */ | |
1255 | int sequence; | |
1256 | ||
1257 | /* The first relaxable fixup in the current frag. (In other words, | |
1258 | the first fixup that refers to relaxable code.) */ | |
1259 | fixS *first_fixup; | |
1260 | ||
1261 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1262 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1263 | unsigned int sizes[2]; | |
1264 | ||
1265 | /* The symbol on which the choice of sequence depends. */ | |
1266 | symbolS *symbol; | |
1267 | } mips_relax; | |
252b5132 | 1268 | \f |
584892a6 RS |
1269 | /* Global variables used to decide whether a macro needs a warning. */ |
1270 | static struct { | |
1271 | /* True if the macro is in a branch delay slot. */ | |
1272 | bfd_boolean delay_slot_p; | |
1273 | ||
df58fc94 RS |
1274 | /* Set to the length in bytes required if the macro is in a delay slot |
1275 | that requires a specific length of instruction, otherwise zero. */ | |
1276 | unsigned int delay_slot_length; | |
1277 | ||
584892a6 RS |
1278 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1279 | in bytes and sizes[1] is the length of the second alternative. | |
1280 | For non-relaxable macros, both elements give the length of the | |
1281 | macro in bytes. */ | |
1282 | unsigned int sizes[2]; | |
1283 | ||
df58fc94 RS |
1284 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1285 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1286 | is the length of the first instruction of the second alternative. | |
1287 | For non-relaxable macros, both elements give the length of the first | |
1288 | instruction in bytes. | |
1289 | ||
1290 | Set to zero if we haven't yet seen the first instruction. */ | |
1291 | unsigned int first_insn_sizes[2]; | |
1292 | ||
1293 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1294 | first alternative and insns[1] is the number of instructions for the | |
1295 | second alternative. | |
1296 | ||
1297 | For non-relaxable macros, both elements give the number of | |
1298 | instructions for the macro. */ | |
1299 | unsigned int insns[2]; | |
1300 | ||
584892a6 RS |
1301 | /* The first variant frag for this macro. */ |
1302 | fragS *first_frag; | |
1303 | } mips_macro_warning; | |
1304 | \f | |
252b5132 RH |
1305 | /* Prototypes for static functions. */ |
1306 | ||
17a2f251 | 1307 | #define internalError() \ |
252b5132 | 1308 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
1309 | |
1310 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
1311 | ||
b34976b6 | 1312 | static void append_insn |
df58fc94 RS |
1313 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1314 | bfd_boolean expansionp); | |
7d10b47d | 1315 | static void mips_no_prev_insn (void); |
c67a084a | 1316 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1317 | static void mips16_macro_build |
03ea81db | 1318 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1319 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1320 | static void macro_start (void); |
1321 | static void macro_end (void); | |
17a2f251 TS |
1322 | static void macro (struct mips_cl_insn * ip); |
1323 | static void mips16_macro (struct mips_cl_insn * ip); | |
17a2f251 TS |
1324 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1325 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1326 | static void mips16_immed |
43c0598f RS |
1327 | (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
1328 | unsigned int, unsigned long *); | |
5e0116d5 | 1329 | static size_t my_getSmallExpression |
17a2f251 TS |
1330 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1331 | static void my_getExpression (expressionS *, char *); | |
1332 | static void s_align (int); | |
1333 | static void s_change_sec (int); | |
1334 | static void s_change_section (int); | |
1335 | static void s_cons (int); | |
1336 | static void s_float_cons (int); | |
1337 | static void s_mips_globl (int); | |
1338 | static void s_option (int); | |
1339 | static void s_mipsset (int); | |
1340 | static void s_abicalls (int); | |
1341 | static void s_cpload (int); | |
1342 | static void s_cpsetup (int); | |
1343 | static void s_cplocal (int); | |
1344 | static void s_cprestore (int); | |
1345 | static void s_cpreturn (int); | |
741d6ea8 JM |
1346 | static void s_dtprelword (int); |
1347 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1348 | static void s_tprelword (int); |
1349 | static void s_tpreldword (int); | |
17a2f251 TS |
1350 | static void s_gpvalue (int); |
1351 | static void s_gpword (int); | |
1352 | static void s_gpdword (int); | |
1353 | static void s_cpadd (int); | |
1354 | static void s_insn (int); | |
1355 | static void md_obj_begin (void); | |
1356 | static void md_obj_end (void); | |
1357 | static void s_mips_ent (int); | |
1358 | static void s_mips_end (int); | |
1359 | static void s_mips_frame (int); | |
1360 | static void s_mips_mask (int reg_type); | |
1361 | static void s_mips_stab (int); | |
1362 | static void s_mips_weakext (int); | |
1363 | static void s_mips_file (int); | |
1364 | static void s_mips_loc (int); | |
1365 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1366 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1367 | static int validate_mips_insn (const struct mips_opcode *); |
df58fc94 RS |
1368 | static int validate_micromips_insn (const struct mips_opcode *); |
1369 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); | |
1370 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
e7af610e NC |
1371 | |
1372 | /* Table and functions used to map between CPU/ISA names, and | |
1373 | ISA levels, and CPU numbers. */ | |
1374 | ||
e972090a NC |
1375 | struct mips_cpu_info |
1376 | { | |
e7af610e | 1377 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1378 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1379 | int isa; /* ISA level. */ |
1380 | int cpu; /* CPU number (default CPU if ISA). */ | |
1381 | }; | |
1382 | ||
ad3fea08 TS |
1383 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1384 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1385 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1386 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1387 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1388 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1389 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
dec0624d | 1390 | #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */ |
ad3fea08 | 1391 | |
17a2f251 TS |
1392 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1393 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1394 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1395 | \f |
1396 | /* Pseudo-op table. | |
1397 | ||
1398 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1399 | should be defined here, but are currently unsupported: .alias, | |
1400 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1401 | ||
1402 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1403 | specific to the type of debugging information being generated, and | |
1404 | should be defined by the object format: .aent, .begin, .bend, | |
1405 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1406 | .vreg. | |
1407 | ||
1408 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1409 | not MIPS CPU specific, but are also not specific to the object file | |
1410 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1411 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1412 | |
e972090a NC |
1413 | static const pseudo_typeS mips_pseudo_table[] = |
1414 | { | |
beae10d5 | 1415 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1416 | {"option", s_option, 0}, |
1417 | {"set", s_mipsset, 0}, | |
1418 | {"rdata", s_change_sec, 'r'}, | |
1419 | {"sdata", s_change_sec, 's'}, | |
1420 | {"livereg", s_ignore, 0}, | |
1421 | {"abicalls", s_abicalls, 0}, | |
1422 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1423 | {"cpsetup", s_cpsetup, 0}, |
1424 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1425 | {"cprestore", s_cprestore, 0}, |
6478892d | 1426 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1427 | {"dtprelword", s_dtprelword, 0}, |
1428 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1429 | {"tprelword", s_tprelword, 0}, |
1430 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1431 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1432 | {"gpword", s_gpword, 0}, |
10181a0d | 1433 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1434 | {"cpadd", s_cpadd, 0}, |
1435 | {"insn", s_insn, 0}, | |
1436 | ||
beae10d5 | 1437 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1438 | chips. */ |
38a57ae7 | 1439 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1440 | {"bss", s_change_sec, 'b'}, |
1441 | {"err", s_err, 0}, | |
1442 | {"half", s_cons, 1}, | |
1443 | {"dword", s_cons, 3}, | |
1444 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1445 | {"origin", s_org, 0}, |
1446 | {"repeat", s_rept, 0}, | |
252b5132 | 1447 | |
998b3c36 MR |
1448 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1449 | {"sbss", s_change_sec, 'B'}, | |
1450 | ||
beae10d5 | 1451 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1452 | here for one reason or another. */ |
1453 | {"align", s_align, 0}, | |
1454 | {"byte", s_cons, 0}, | |
1455 | {"data", s_change_sec, 'd'}, | |
1456 | {"double", s_float_cons, 'd'}, | |
1457 | {"float", s_float_cons, 'f'}, | |
1458 | {"globl", s_mips_globl, 0}, | |
1459 | {"global", s_mips_globl, 0}, | |
1460 | {"hword", s_cons, 1}, | |
1461 | {"int", s_cons, 2}, | |
1462 | {"long", s_cons, 2}, | |
1463 | {"octa", s_cons, 4}, | |
1464 | {"quad", s_cons, 3}, | |
cca86cc8 | 1465 | {"section", s_change_section, 0}, |
252b5132 RH |
1466 | {"short", s_cons, 1}, |
1467 | {"single", s_float_cons, 'f'}, | |
1468 | {"stabn", s_mips_stab, 'n'}, | |
1469 | {"text", s_change_sec, 't'}, | |
1470 | {"word", s_cons, 2}, | |
add56521 | 1471 | |
add56521 | 1472 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1473 | |
43841e91 | 1474 | { NULL, NULL, 0 }, |
252b5132 RH |
1475 | }; |
1476 | ||
e972090a NC |
1477 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1478 | { | |
beae10d5 KH |
1479 | /* These pseudo-ops should be defined by the object file format. |
1480 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1481 | {"aent", s_mips_ent, 1}, |
1482 | {"bgnb", s_ignore, 0}, | |
1483 | {"end", s_mips_end, 0}, | |
1484 | {"endb", s_ignore, 0}, | |
1485 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1486 | {"file", s_mips_file, 0}, |
252b5132 RH |
1487 | {"fmask", s_mips_mask, 'F'}, |
1488 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1489 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1490 | {"mask", s_mips_mask, 'R'}, |
1491 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1492 | { NULL, NULL, 0 }, |
252b5132 RH |
1493 | }; |
1494 | ||
3ae8dd8d MR |
1495 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1496 | purpose of the `.dc.a' internal pseudo-op. */ | |
1497 | ||
1498 | int | |
1499 | mips_address_bytes (void) | |
1500 | { | |
1501 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1502 | } | |
1503 | ||
17a2f251 | 1504 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1505 | |
1506 | void | |
17a2f251 | 1507 | mips_pop_insert (void) |
252b5132 RH |
1508 | { |
1509 | pop_insert (mips_pseudo_table); | |
1510 | if (! ECOFF_DEBUGGING) | |
1511 | pop_insert (mips_nonecoff_pseudo_table); | |
1512 | } | |
1513 | \f | |
1514 | /* Symbols labelling the current insn. */ | |
1515 | ||
e972090a NC |
1516 | struct insn_label_list |
1517 | { | |
252b5132 RH |
1518 | struct insn_label_list *next; |
1519 | symbolS *label; | |
1520 | }; | |
1521 | ||
252b5132 | 1522 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1523 | #define label_list tc_segment_info_data.labels |
252b5132 | 1524 | |
17a2f251 | 1525 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1526 | static void mips_mark_labels (void); |
1527 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1528 | |
1529 | static inline void | |
17a2f251 | 1530 | mips_clear_insn_labels (void) |
252b5132 RH |
1531 | { |
1532 | register struct insn_label_list **pl; | |
a8dbcb85 | 1533 | segment_info_type *si; |
252b5132 | 1534 | |
a8dbcb85 TS |
1535 | if (now_seg) |
1536 | { | |
1537 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1538 | ; | |
1539 | ||
1540 | si = seg_info (now_seg); | |
1541 | *pl = si->label_list; | |
1542 | si->label_list = NULL; | |
1543 | } | |
252b5132 | 1544 | } |
a8dbcb85 | 1545 | |
df58fc94 RS |
1546 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1547 | ||
1548 | static inline void | |
1549 | mips_mark_labels (void) | |
1550 | { | |
1551 | if (HAVE_CODE_COMPRESSION) | |
1552 | mips_compressed_mark_labels (); | |
1553 | } | |
252b5132 RH |
1554 | \f |
1555 | static char *expr_end; | |
1556 | ||
1557 | /* Expressions which appear in instructions. These are set by | |
1558 | mips_ip. */ | |
1559 | ||
1560 | static expressionS imm_expr; | |
5f74bc13 | 1561 | static expressionS imm2_expr; |
252b5132 RH |
1562 | static expressionS offset_expr; |
1563 | ||
1564 | /* Relocs associated with imm_expr and offset_expr. */ | |
1565 | ||
f6688943 TS |
1566 | static bfd_reloc_code_real_type imm_reloc[3] |
1567 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1568 | static bfd_reloc_code_real_type offset_reloc[3] | |
1569 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1570 | |
df58fc94 RS |
1571 | /* This is set to the resulting size of the instruction to be produced |
1572 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1573 | explicit size is supplied. */ | |
252b5132 | 1574 | |
df58fc94 | 1575 | static unsigned int forced_insn_length; |
252b5132 | 1576 | |
e1b47bd5 RS |
1577 | /* True if we are assembling an instruction. All dot symbols defined during |
1578 | this time should be treated as code labels. */ | |
1579 | ||
1580 | static bfd_boolean mips_assembling_insn; | |
1581 | ||
7ed4a06a | 1582 | #ifdef OBJ_ELF |
ecb4347a DJ |
1583 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1584 | ECOFF debugging. */ | |
252b5132 RH |
1585 | |
1586 | static segT pdr_seg; | |
7ed4a06a | 1587 | #endif |
252b5132 | 1588 | |
e013f690 TS |
1589 | /* The default target format to use. */ |
1590 | ||
aeffff67 RS |
1591 | #if defined (TE_FreeBSD) |
1592 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1593 | #elif defined (TE_TMIPS) | |
1594 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1595 | #else | |
1596 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1597 | #endif | |
1598 | ||
e013f690 | 1599 | const char * |
17a2f251 | 1600 | mips_target_format (void) |
e013f690 TS |
1601 | { |
1602 | switch (OUTPUT_FLAVOR) | |
1603 | { | |
e013f690 TS |
1604 | case bfd_target_ecoff_flavour: |
1605 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1606 | case bfd_target_coff_flavour: | |
1607 | return "pe-mips"; | |
1608 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1609 | #ifdef TE_VXWORKS |
1610 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1611 | return (target_big_endian | |
1612 | ? "elf32-bigmips-vxworks" | |
1613 | : "elf32-littlemips-vxworks"); | |
1614 | #endif | |
e013f690 | 1615 | return (target_big_endian |
cfe86eaa | 1616 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1617 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1618 | : (HAVE_NEWABI |
aeffff67 RS |
1619 | ? ELF_TARGET ("elf32-n", "big") |
1620 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1621 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1622 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1623 | : (HAVE_NEWABI |
aeffff67 RS |
1624 | ? ELF_TARGET ("elf32-n", "little") |
1625 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1626 | default: |
1627 | abort (); | |
1628 | return NULL; | |
1629 | } | |
1630 | } | |
1631 | ||
df58fc94 RS |
1632 | /* Return the length of a microMIPS instruction in bytes. If bits of |
1633 | the mask beyond the low 16 are 0, then it is a 16-bit instruction. | |
1634 | Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f | |
1635 | major opcode) will require further modifications to the opcode | |
1636 | table. */ | |
1637 | ||
1638 | static inline unsigned int | |
1639 | micromips_insn_length (const struct mips_opcode *mo) | |
1640 | { | |
1641 | return (mo->mask >> 16) == 0 ? 2 : 4; | |
1642 | } | |
1643 | ||
5c04167a RS |
1644 | /* Return the length of MIPS16 instruction OPCODE. */ |
1645 | ||
1646 | static inline unsigned int | |
1647 | mips16_opcode_length (unsigned long opcode) | |
1648 | { | |
1649 | return (opcode >> 16) == 0 ? 2 : 4; | |
1650 | } | |
1651 | ||
1e915849 RS |
1652 | /* Return the length of instruction INSN. */ |
1653 | ||
1654 | static inline unsigned int | |
1655 | insn_length (const struct mips_cl_insn *insn) | |
1656 | { | |
df58fc94 RS |
1657 | if (mips_opts.micromips) |
1658 | return micromips_insn_length (insn->insn_mo); | |
1659 | else if (mips_opts.mips16) | |
5c04167a | 1660 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 1661 | else |
1e915849 | 1662 | return 4; |
1e915849 RS |
1663 | } |
1664 | ||
1665 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1666 | ||
1667 | static void | |
1668 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1669 | { | |
1670 | size_t i; | |
1671 | ||
1672 | insn->insn_mo = mo; | |
1e915849 RS |
1673 | insn->insn_opcode = mo->match; |
1674 | insn->frag = NULL; | |
1675 | insn->where = 0; | |
1676 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1677 | insn->fixp[i] = NULL; | |
1678 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1679 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1680 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 1681 | insn->complete_p = 0; |
1e915849 RS |
1682 | } |
1683 | ||
df58fc94 | 1684 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
1685 | |
1686 | static void | |
df58fc94 | 1687 | mips_record_compressed_mode (void) |
742a56fe RS |
1688 | { |
1689 | segment_info_type *si; | |
1690 | ||
1691 | si = seg_info (now_seg); | |
1692 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1693 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
1694 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
1695 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
1696 | } |
1697 | ||
4d68580a RS |
1698 | /* Read a standard MIPS instruction from BUF. */ |
1699 | ||
1700 | static unsigned long | |
1701 | read_insn (char *buf) | |
1702 | { | |
1703 | if (target_big_endian) | |
1704 | return bfd_getb32 ((bfd_byte *) buf); | |
1705 | else | |
1706 | return bfd_getl32 ((bfd_byte *) buf); | |
1707 | } | |
1708 | ||
1709 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
1710 | the next byte. */ | |
1711 | ||
1712 | static char * | |
1713 | write_insn (char *buf, unsigned int insn) | |
1714 | { | |
1715 | md_number_to_chars (buf, insn, 4); | |
1716 | return buf + 4; | |
1717 | } | |
1718 | ||
1719 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
1720 | has length LENGTH. */ | |
1721 | ||
1722 | static unsigned long | |
1723 | read_compressed_insn (char *buf, unsigned int length) | |
1724 | { | |
1725 | unsigned long insn; | |
1726 | unsigned int i; | |
1727 | ||
1728 | insn = 0; | |
1729 | for (i = 0; i < length; i += 2) | |
1730 | { | |
1731 | insn <<= 16; | |
1732 | if (target_big_endian) | |
1733 | insn |= bfd_getb16 ((char *) buf); | |
1734 | else | |
1735 | insn |= bfd_getl16 ((char *) buf); | |
1736 | buf += 2; | |
1737 | } | |
1738 | return insn; | |
1739 | } | |
1740 | ||
5c04167a RS |
1741 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
1742 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
1743 | ||
1744 | static char * | |
1745 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
1746 | { | |
1747 | unsigned int i; | |
1748 | ||
1749 | for (i = 0; i < length; i += 2) | |
1750 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
1751 | return buf + length; | |
1752 | } | |
1753 | ||
1e915849 RS |
1754 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1755 | ||
1756 | static void | |
1757 | install_insn (const struct mips_cl_insn *insn) | |
1758 | { | |
1759 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
1760 | if (HAVE_CODE_COMPRESSION) |
1761 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 1762 | else |
4d68580a | 1763 | write_insn (f, insn->insn_opcode); |
df58fc94 | 1764 | mips_record_compressed_mode (); |
1e915849 RS |
1765 | } |
1766 | ||
1767 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1768 | and install the opcode in the new location. */ | |
1769 | ||
1770 | static void | |
1771 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1772 | { | |
1773 | size_t i; | |
1774 | ||
1775 | insn->frag = frag; | |
1776 | insn->where = where; | |
1777 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1778 | if (insn->fixp[i] != NULL) | |
1779 | { | |
1780 | insn->fixp[i]->fx_frag = frag; | |
1781 | insn->fixp[i]->fx_where = where; | |
1782 | } | |
1783 | install_insn (insn); | |
1784 | } | |
1785 | ||
1786 | /* Add INSN to the end of the output. */ | |
1787 | ||
1788 | static void | |
1789 | add_fixed_insn (struct mips_cl_insn *insn) | |
1790 | { | |
1791 | char *f = frag_more (insn_length (insn)); | |
1792 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1793 | } | |
1794 | ||
1795 | /* Start a variant frag and move INSN to the start of the variant part, | |
1796 | marking it as fixed. The other arguments are as for frag_var. */ | |
1797 | ||
1798 | static void | |
1799 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1800 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1801 | { | |
1802 | frag_grow (max_chars); | |
1803 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1804 | insn->fixed_p = 1; | |
1805 | frag_var (rs_machine_dependent, max_chars, var, | |
1806 | subtype, symbol, offset, NULL); | |
1807 | } | |
1808 | ||
1809 | /* Insert N copies of INSN into the history buffer, starting at | |
1810 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1811 | ||
1812 | static void | |
1813 | insert_into_history (unsigned int first, unsigned int n, | |
1814 | const struct mips_cl_insn *insn) | |
1815 | { | |
1816 | if (mips_relax.sequence != 2) | |
1817 | { | |
1818 | unsigned int i; | |
1819 | ||
1820 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1821 | if (i >= first + n) | |
1822 | history[i] = history[i - n]; | |
1823 | else | |
1824 | history[i] = *insn; | |
1825 | } | |
1826 | } | |
1827 | ||
71400594 RS |
1828 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1829 | the idea is to make it obvious at a glance that each errata is | |
1830 | included. */ | |
1831 | ||
1832 | static void | |
1833 | init_vr4120_conflicts (void) | |
1834 | { | |
1835 | #define CONFLICT(FIRST, SECOND) \ | |
1836 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1837 | ||
1838 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1839 | CONFLICT (MACC, DIV); | |
1840 | CONFLICT (DMACC, DIV); | |
1841 | ||
1842 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1843 | CONFLICT (DMULT, DMULT); | |
1844 | CONFLICT (DMULT, DMACC); | |
1845 | CONFLICT (DMACC, DMULT); | |
1846 | CONFLICT (DMACC, DMACC); | |
1847 | ||
1848 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1849 | CONFLICT (MACC, MTHILO); | |
1850 | CONFLICT (DMACC, MTHILO); | |
1851 | ||
1852 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1853 | instruction is executed immediately after a MACC or DMACC | |
1854 | instruction, the result of [either instruction] is incorrect." */ | |
1855 | CONFLICT (MACC, MULT); | |
1856 | CONFLICT (MACC, DMULT); | |
1857 | CONFLICT (DMACC, MULT); | |
1858 | CONFLICT (DMACC, DMULT); | |
1859 | ||
1860 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1861 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1862 | DDIV or DDIVU instruction, the result of the MACC or | |
1863 | DMACC instruction is incorrect.". */ | |
1864 | CONFLICT (DMULT, MACC); | |
1865 | CONFLICT (DMULT, DMACC); | |
1866 | CONFLICT (DIV, MACC); | |
1867 | CONFLICT (DIV, DMACC); | |
1868 | ||
1869 | #undef CONFLICT | |
1870 | } | |
1871 | ||
707bfff6 TS |
1872 | struct regname { |
1873 | const char *name; | |
1874 | unsigned int num; | |
1875 | }; | |
1876 | ||
1877 | #define RTYPE_MASK 0x1ff00 | |
1878 | #define RTYPE_NUM 0x00100 | |
1879 | #define RTYPE_FPU 0x00200 | |
1880 | #define RTYPE_FCC 0x00400 | |
1881 | #define RTYPE_VEC 0x00800 | |
1882 | #define RTYPE_GP 0x01000 | |
1883 | #define RTYPE_CP0 0x02000 | |
1884 | #define RTYPE_PC 0x04000 | |
1885 | #define RTYPE_ACC 0x08000 | |
1886 | #define RTYPE_CCC 0x10000 | |
1887 | #define RNUM_MASK 0x000ff | |
1888 | #define RWARN 0x80000 | |
1889 | ||
1890 | #define GENERIC_REGISTER_NUMBERS \ | |
1891 | {"$0", RTYPE_NUM | 0}, \ | |
1892 | {"$1", RTYPE_NUM | 1}, \ | |
1893 | {"$2", RTYPE_NUM | 2}, \ | |
1894 | {"$3", RTYPE_NUM | 3}, \ | |
1895 | {"$4", RTYPE_NUM | 4}, \ | |
1896 | {"$5", RTYPE_NUM | 5}, \ | |
1897 | {"$6", RTYPE_NUM | 6}, \ | |
1898 | {"$7", RTYPE_NUM | 7}, \ | |
1899 | {"$8", RTYPE_NUM | 8}, \ | |
1900 | {"$9", RTYPE_NUM | 9}, \ | |
1901 | {"$10", RTYPE_NUM | 10}, \ | |
1902 | {"$11", RTYPE_NUM | 11}, \ | |
1903 | {"$12", RTYPE_NUM | 12}, \ | |
1904 | {"$13", RTYPE_NUM | 13}, \ | |
1905 | {"$14", RTYPE_NUM | 14}, \ | |
1906 | {"$15", RTYPE_NUM | 15}, \ | |
1907 | {"$16", RTYPE_NUM | 16}, \ | |
1908 | {"$17", RTYPE_NUM | 17}, \ | |
1909 | {"$18", RTYPE_NUM | 18}, \ | |
1910 | {"$19", RTYPE_NUM | 19}, \ | |
1911 | {"$20", RTYPE_NUM | 20}, \ | |
1912 | {"$21", RTYPE_NUM | 21}, \ | |
1913 | {"$22", RTYPE_NUM | 22}, \ | |
1914 | {"$23", RTYPE_NUM | 23}, \ | |
1915 | {"$24", RTYPE_NUM | 24}, \ | |
1916 | {"$25", RTYPE_NUM | 25}, \ | |
1917 | {"$26", RTYPE_NUM | 26}, \ | |
1918 | {"$27", RTYPE_NUM | 27}, \ | |
1919 | {"$28", RTYPE_NUM | 28}, \ | |
1920 | {"$29", RTYPE_NUM | 29}, \ | |
1921 | {"$30", RTYPE_NUM | 30}, \ | |
1922 | {"$31", RTYPE_NUM | 31} | |
1923 | ||
1924 | #define FPU_REGISTER_NAMES \ | |
1925 | {"$f0", RTYPE_FPU | 0}, \ | |
1926 | {"$f1", RTYPE_FPU | 1}, \ | |
1927 | {"$f2", RTYPE_FPU | 2}, \ | |
1928 | {"$f3", RTYPE_FPU | 3}, \ | |
1929 | {"$f4", RTYPE_FPU | 4}, \ | |
1930 | {"$f5", RTYPE_FPU | 5}, \ | |
1931 | {"$f6", RTYPE_FPU | 6}, \ | |
1932 | {"$f7", RTYPE_FPU | 7}, \ | |
1933 | {"$f8", RTYPE_FPU | 8}, \ | |
1934 | {"$f9", RTYPE_FPU | 9}, \ | |
1935 | {"$f10", RTYPE_FPU | 10}, \ | |
1936 | {"$f11", RTYPE_FPU | 11}, \ | |
1937 | {"$f12", RTYPE_FPU | 12}, \ | |
1938 | {"$f13", RTYPE_FPU | 13}, \ | |
1939 | {"$f14", RTYPE_FPU | 14}, \ | |
1940 | {"$f15", RTYPE_FPU | 15}, \ | |
1941 | {"$f16", RTYPE_FPU | 16}, \ | |
1942 | {"$f17", RTYPE_FPU | 17}, \ | |
1943 | {"$f18", RTYPE_FPU | 18}, \ | |
1944 | {"$f19", RTYPE_FPU | 19}, \ | |
1945 | {"$f20", RTYPE_FPU | 20}, \ | |
1946 | {"$f21", RTYPE_FPU | 21}, \ | |
1947 | {"$f22", RTYPE_FPU | 22}, \ | |
1948 | {"$f23", RTYPE_FPU | 23}, \ | |
1949 | {"$f24", RTYPE_FPU | 24}, \ | |
1950 | {"$f25", RTYPE_FPU | 25}, \ | |
1951 | {"$f26", RTYPE_FPU | 26}, \ | |
1952 | {"$f27", RTYPE_FPU | 27}, \ | |
1953 | {"$f28", RTYPE_FPU | 28}, \ | |
1954 | {"$f29", RTYPE_FPU | 29}, \ | |
1955 | {"$f30", RTYPE_FPU | 30}, \ | |
1956 | {"$f31", RTYPE_FPU | 31} | |
1957 | ||
1958 | #define FPU_CONDITION_CODE_NAMES \ | |
1959 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1960 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1961 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1962 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1963 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1964 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1965 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1966 | {"$fcc7", RTYPE_FCC | 7} | |
1967 | ||
1968 | #define COPROC_CONDITION_CODE_NAMES \ | |
1969 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1970 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1971 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1972 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1973 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1974 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1975 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1976 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1977 | ||
1978 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1979 | {"$a4", RTYPE_GP | 8}, \ | |
1980 | {"$a5", RTYPE_GP | 9}, \ | |
1981 | {"$a6", RTYPE_GP | 10}, \ | |
1982 | {"$a7", RTYPE_GP | 11}, \ | |
1983 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1984 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1985 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1986 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1987 | {"$t0", RTYPE_GP | 12}, \ | |
1988 | {"$t1", RTYPE_GP | 13}, \ | |
1989 | {"$t2", RTYPE_GP | 14}, \ | |
1990 | {"$t3", RTYPE_GP | 15} | |
1991 | ||
1992 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1993 | {"$t0", RTYPE_GP | 8}, \ | |
1994 | {"$t1", RTYPE_GP | 9}, \ | |
1995 | {"$t2", RTYPE_GP | 10}, \ | |
1996 | {"$t3", RTYPE_GP | 11}, \ | |
1997 | {"$t4", RTYPE_GP | 12}, \ | |
1998 | {"$t5", RTYPE_GP | 13}, \ | |
1999 | {"$t6", RTYPE_GP | 14}, \ | |
2000 | {"$t7", RTYPE_GP | 15}, \ | |
2001 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2002 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2003 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
2004 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
2005 | ||
2006 | /* Remaining symbolic register names */ | |
2007 | #define SYMBOLIC_REGISTER_NAMES \ | |
2008 | {"$zero", RTYPE_GP | 0}, \ | |
2009 | {"$at", RTYPE_GP | 1}, \ | |
2010 | {"$AT", RTYPE_GP | 1}, \ | |
2011 | {"$v0", RTYPE_GP | 2}, \ | |
2012 | {"$v1", RTYPE_GP | 3}, \ | |
2013 | {"$a0", RTYPE_GP | 4}, \ | |
2014 | {"$a1", RTYPE_GP | 5}, \ | |
2015 | {"$a2", RTYPE_GP | 6}, \ | |
2016 | {"$a3", RTYPE_GP | 7}, \ | |
2017 | {"$s0", RTYPE_GP | 16}, \ | |
2018 | {"$s1", RTYPE_GP | 17}, \ | |
2019 | {"$s2", RTYPE_GP | 18}, \ | |
2020 | {"$s3", RTYPE_GP | 19}, \ | |
2021 | {"$s4", RTYPE_GP | 20}, \ | |
2022 | {"$s5", RTYPE_GP | 21}, \ | |
2023 | {"$s6", RTYPE_GP | 22}, \ | |
2024 | {"$s7", RTYPE_GP | 23}, \ | |
2025 | {"$t8", RTYPE_GP | 24}, \ | |
2026 | {"$t9", RTYPE_GP | 25}, \ | |
2027 | {"$k0", RTYPE_GP | 26}, \ | |
2028 | {"$kt0", RTYPE_GP | 26}, \ | |
2029 | {"$k1", RTYPE_GP | 27}, \ | |
2030 | {"$kt1", RTYPE_GP | 27}, \ | |
2031 | {"$gp", RTYPE_GP | 28}, \ | |
2032 | {"$sp", RTYPE_GP | 29}, \ | |
2033 | {"$s8", RTYPE_GP | 30}, \ | |
2034 | {"$fp", RTYPE_GP | 30}, \ | |
2035 | {"$ra", RTYPE_GP | 31} | |
2036 | ||
2037 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2038 | {"$pc", RTYPE_PC | 0} | |
2039 | ||
2040 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2041 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2042 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2043 | {"$v2", RTYPE_VEC | 2}, \ | |
2044 | {"$v3", RTYPE_VEC | 3}, \ | |
2045 | {"$v4", RTYPE_VEC | 4}, \ | |
2046 | {"$v5", RTYPE_VEC | 5}, \ | |
2047 | {"$v6", RTYPE_VEC | 6}, \ | |
2048 | {"$v7", RTYPE_VEC | 7}, \ | |
2049 | {"$v8", RTYPE_VEC | 8}, \ | |
2050 | {"$v9", RTYPE_VEC | 9}, \ | |
2051 | {"$v10", RTYPE_VEC | 10}, \ | |
2052 | {"$v11", RTYPE_VEC | 11}, \ | |
2053 | {"$v12", RTYPE_VEC | 12}, \ | |
2054 | {"$v13", RTYPE_VEC | 13}, \ | |
2055 | {"$v14", RTYPE_VEC | 14}, \ | |
2056 | {"$v15", RTYPE_VEC | 15}, \ | |
2057 | {"$v16", RTYPE_VEC | 16}, \ | |
2058 | {"$v17", RTYPE_VEC | 17}, \ | |
2059 | {"$v18", RTYPE_VEC | 18}, \ | |
2060 | {"$v19", RTYPE_VEC | 19}, \ | |
2061 | {"$v20", RTYPE_VEC | 20}, \ | |
2062 | {"$v21", RTYPE_VEC | 21}, \ | |
2063 | {"$v22", RTYPE_VEC | 22}, \ | |
2064 | {"$v23", RTYPE_VEC | 23}, \ | |
2065 | {"$v24", RTYPE_VEC | 24}, \ | |
2066 | {"$v25", RTYPE_VEC | 25}, \ | |
2067 | {"$v26", RTYPE_VEC | 26}, \ | |
2068 | {"$v27", RTYPE_VEC | 27}, \ | |
2069 | {"$v28", RTYPE_VEC | 28}, \ | |
2070 | {"$v29", RTYPE_VEC | 29}, \ | |
2071 | {"$v30", RTYPE_VEC | 30}, \ | |
2072 | {"$v31", RTYPE_VEC | 31} | |
2073 | ||
2074 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
2075 | {"$ac0", RTYPE_ACC | 0}, \ | |
2076 | {"$ac1", RTYPE_ACC | 1}, \ | |
2077 | {"$ac2", RTYPE_ACC | 2}, \ | |
2078 | {"$ac3", RTYPE_ACC | 3} | |
2079 | ||
2080 | static const struct regname reg_names[] = { | |
2081 | GENERIC_REGISTER_NUMBERS, | |
2082 | FPU_REGISTER_NAMES, | |
2083 | FPU_CONDITION_CODE_NAMES, | |
2084 | COPROC_CONDITION_CODE_NAMES, | |
2085 | ||
2086 | /* The $txx registers depends on the abi, | |
2087 | these will be added later into the symbol table from | |
2088 | one of the tables below once mips_abi is set after | |
2089 | parsing of arguments from the command line. */ | |
2090 | SYMBOLIC_REGISTER_NAMES, | |
2091 | ||
2092 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2093 | MDMX_VECTOR_REGISTER_NAMES, | |
2094 | MIPS_DSP_ACCUMULATOR_NAMES, | |
2095 | {0, 0} | |
2096 | }; | |
2097 | ||
2098 | static const struct regname reg_names_o32[] = { | |
2099 | O32_SYMBOLIC_REGISTER_NAMES, | |
2100 | {0, 0} | |
2101 | }; | |
2102 | ||
2103 | static const struct regname reg_names_n32n64[] = { | |
2104 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2105 | {0, 0} | |
2106 | }; | |
2107 | ||
df58fc94 RS |
2108 | /* Check if S points at a valid register specifier according to TYPES. |
2109 | If so, then return 1, advance S to consume the specifier and store | |
2110 | the register's number in REGNOP, otherwise return 0. */ | |
2111 | ||
707bfff6 TS |
2112 | static int |
2113 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2114 | { | |
2115 | symbolS *symbolP; | |
2116 | char *e; | |
2117 | char save_c; | |
2118 | int reg = -1; | |
2119 | ||
2120 | /* Find end of name. */ | |
2121 | e = *s; | |
2122 | if (is_name_beginner (*e)) | |
2123 | ++e; | |
2124 | while (is_part_of_name (*e)) | |
2125 | ++e; | |
2126 | ||
2127 | /* Terminate name. */ | |
2128 | save_c = *e; | |
2129 | *e = '\0'; | |
2130 | ||
2131 | /* Look for a register symbol. */ | |
2132 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
2133 | { | |
2134 | int r = S_GET_VALUE (symbolP); | |
2135 | if (r & types) | |
2136 | reg = r & RNUM_MASK; | |
2137 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
2138 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
2139 | reg = (r & RNUM_MASK) - 2; | |
2140 | } | |
2141 | /* Else see if this is a register defined in an itbl entry. */ | |
2142 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
2143 | { | |
2144 | char *n = *s; | |
2145 | unsigned long r; | |
2146 | ||
2147 | if (*n == '$') | |
2148 | ++n; | |
2149 | if (itbl_get_reg_val (n, &r)) | |
2150 | reg = r & RNUM_MASK; | |
2151 | } | |
2152 | ||
2153 | /* Advance to next token if a register was recognised. */ | |
2154 | if (reg >= 0) | |
2155 | *s = e; | |
2156 | else if (types & RWARN) | |
20203fb9 | 2157 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
2158 | |
2159 | *e = save_c; | |
2160 | if (regnop) | |
2161 | *regnop = reg; | |
2162 | return reg >= 0; | |
2163 | } | |
2164 | ||
df58fc94 RS |
2165 | /* Check if S points at a valid register list according to TYPES. |
2166 | If so, then return 1, advance S to consume the list and store | |
2167 | the registers present on the list as a bitmask of ones in REGLISTP, | |
2168 | otherwise return 0. A valid list comprises a comma-separated | |
2169 | enumeration of valid single registers and/or dash-separated | |
2170 | contiguous register ranges as determined by their numbers. | |
2171 | ||
2172 | As a special exception if one of s0-s7 registers is specified as | |
2173 | the range's lower delimiter and s8 (fp) is its upper one, then no | |
2174 | registers whose numbers place them between s7 and s8 (i.e. $24-$29) | |
2309ddf2 | 2175 | are selected; they have to be listed separately if needed. */ |
df58fc94 RS |
2176 | |
2177 | static int | |
2178 | reglist_lookup (char **s, unsigned int types, unsigned int *reglistp) | |
2179 | { | |
2180 | unsigned int reglist = 0; | |
2181 | unsigned int lastregno; | |
2182 | bfd_boolean ok = TRUE; | |
2183 | unsigned int regmask; | |
2309ddf2 | 2184 | char *s_endlist = *s; |
df58fc94 | 2185 | char *s_reset = *s; |
2309ddf2 | 2186 | unsigned int regno; |
df58fc94 RS |
2187 | |
2188 | while (reg_lookup (s, types, ®no)) | |
2189 | { | |
2190 | lastregno = regno; | |
2191 | if (**s == '-') | |
2192 | { | |
2193 | (*s)++; | |
2194 | ok = reg_lookup (s, types, &lastregno); | |
2195 | if (ok && lastregno < regno) | |
2196 | ok = FALSE; | |
2197 | if (!ok) | |
2198 | break; | |
2199 | } | |
2200 | ||
2201 | if (lastregno == FP && regno >= S0 && regno <= S7) | |
2202 | { | |
2203 | lastregno = S7; | |
2204 | reglist |= 1 << FP; | |
2205 | } | |
2206 | regmask = 1 << lastregno; | |
2207 | regmask = (regmask << 1) - 1; | |
2208 | regmask ^= (1 << regno) - 1; | |
2209 | reglist |= regmask; | |
2210 | ||
2309ddf2 | 2211 | s_endlist = *s; |
df58fc94 RS |
2212 | if (**s != ',') |
2213 | break; | |
2214 | (*s)++; | |
2215 | } | |
2216 | ||
2217 | if (ok) | |
2309ddf2 | 2218 | *s = s_endlist; |
df58fc94 RS |
2219 | else |
2220 | *s = s_reset; | |
2221 | if (reglistp) | |
2222 | *reglistp = reglist; | |
2223 | return ok && reglist != 0; | |
2224 | } | |
2225 | ||
037b32b9 | 2226 | /* Return TRUE if opcode MO is valid on the currently selected ISA and |
f79e2745 | 2227 | architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ |
037b32b9 AN |
2228 | |
2229 | static bfd_boolean | |
f79e2745 | 2230 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
2231 | { |
2232 | int isa = mips_opts.isa; | |
2233 | int fp_s, fp_d; | |
2234 | ||
2235 | if (mips_opts.ase_mdmx) | |
2236 | isa |= INSN_MDMX; | |
2237 | if (mips_opts.ase_dsp) | |
2238 | isa |= INSN_DSP; | |
2239 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
2240 | isa |= INSN_DSP64; | |
2241 | if (mips_opts.ase_dspr2) | |
2242 | isa |= INSN_DSPR2; | |
2243 | if (mips_opts.ase_mt) | |
2244 | isa |= INSN_MT; | |
2245 | if (mips_opts.ase_mips3d) | |
2246 | isa |= INSN_MIPS3D; | |
2247 | if (mips_opts.ase_smartmips) | |
2248 | isa |= INSN_SMARTMIPS; | |
dec0624d MR |
2249 | if (mips_opts.ase_mcu) |
2250 | isa |= INSN_MCU; | |
037b32b9 | 2251 | |
35d0a169 | 2252 | if (!opcode_is_member (mo, isa, mips_opts.arch)) |
037b32b9 AN |
2253 | return FALSE; |
2254 | ||
2255 | /* Check whether the instruction or macro requires single-precision or | |
2256 | double-precision floating-point support. Note that this information is | |
2257 | stored differently in the opcode table for insns and macros. */ | |
2258 | if (mo->pinfo == INSN_MACRO) | |
2259 | { | |
2260 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
2261 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
2262 | } | |
2263 | else | |
2264 | { | |
2265 | fp_s = mo->pinfo & FP_S; | |
2266 | fp_d = mo->pinfo & FP_D; | |
2267 | } | |
2268 | ||
2269 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
2270 | return FALSE; | |
2271 | ||
2272 | if (fp_s && mips_opts.soft_float) | |
2273 | return FALSE; | |
2274 | ||
2275 | return TRUE; | |
2276 | } | |
2277 | ||
2278 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
2279 | selected ISA and architecture. */ | |
2280 | ||
2281 | static bfd_boolean | |
2282 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
2283 | { | |
35d0a169 | 2284 | return opcode_is_member (mo, mips_opts.isa, mips_opts.arch); |
037b32b9 AN |
2285 | } |
2286 | ||
df58fc94 RS |
2287 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
2288 | explicitly requested. Always TRUE in the standard MIPS mode. */ | |
2289 | ||
2290 | static bfd_boolean | |
2291 | is_size_valid (const struct mips_opcode *mo) | |
2292 | { | |
2293 | if (!mips_opts.micromips) | |
2294 | return TRUE; | |
2295 | ||
2296 | if (!forced_insn_length) | |
2297 | return TRUE; | |
2298 | if (mo->pinfo == INSN_MACRO) | |
2299 | return FALSE; | |
2300 | return forced_insn_length == micromips_insn_length (mo); | |
2301 | } | |
2302 | ||
2303 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot | |
e64af278 MR |
2304 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
2305 | ||
2306 | We don't accept macros in 16-bit delay slots to avoid a case where | |
2307 | a macro expansion fails because it relies on a preceding 32-bit real | |
2308 | instruction to have matched and does not handle the operands correctly. | |
2309 | The only macros that may expand to 16-bit instructions are JAL that | |
2310 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
2311 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
2312 | a NOP. In all these cases the macros precede any corresponding real | |
2313 | instruction definitions in the opcode table, so they will match in the | |
2314 | second pass where the size of the delay slot is ignored and therefore | |
2315 | produce correct code. */ | |
df58fc94 RS |
2316 | |
2317 | static bfd_boolean | |
2318 | is_delay_slot_valid (const struct mips_opcode *mo) | |
2319 | { | |
2320 | if (!mips_opts.micromips) | |
2321 | return TRUE; | |
2322 | ||
2323 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 2324 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
2325 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
2326 | && micromips_insn_length (mo) != 4) | |
2327 | return FALSE; | |
2328 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
2329 | && micromips_insn_length (mo) != 2) | |
2330 | return FALSE; | |
2331 | ||
2332 | return TRUE; | |
2333 | } | |
2334 | ||
707bfff6 TS |
2335 | /* This function is called once, at assembler startup time. It should set up |
2336 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 2337 | |
252b5132 | 2338 | void |
17a2f251 | 2339 | md_begin (void) |
252b5132 | 2340 | { |
3994f87e | 2341 | const char *retval = NULL; |
156c2f8b | 2342 | int i = 0; |
252b5132 | 2343 | int broken = 0; |
1f25f5d3 | 2344 | |
0a44bf69 RS |
2345 | if (mips_pic != NO_PIC) |
2346 | { | |
2347 | if (g_switch_seen && g_switch_value != 0) | |
2348 | as_bad (_("-G may not be used in position-independent code")); | |
2349 | g_switch_value = 0; | |
2350 | } | |
2351 | ||
fef14a42 | 2352 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
2353 | as_warn (_("Could not set architecture and machine")); |
2354 | ||
252b5132 RH |
2355 | op_hash = hash_new (); |
2356 | ||
2357 | for (i = 0; i < NUMOPCODES;) | |
2358 | { | |
2359 | const char *name = mips_opcodes[i].name; | |
2360 | ||
17a2f251 | 2361 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
2362 | if (retval != NULL) |
2363 | { | |
2364 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
2365 | mips_opcodes[i].name, retval); | |
2366 | /* Probably a memory allocation problem? Give up now. */ | |
2367 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2368 | } | |
2369 | do | |
2370 | { | |
2371 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
2372 | { | |
2373 | if (!validate_mips_insn (&mips_opcodes[i])) | |
2374 | broken = 1; | |
1e915849 RS |
2375 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2376 | { | |
2377 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
2378 | if (mips_fix_loongson2f_nop) |
2379 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
2380 | nop_insn.fixed_p = 1; |
2381 | } | |
252b5132 RH |
2382 | } |
2383 | ++i; | |
2384 | } | |
2385 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
2386 | } | |
2387 | ||
2388 | mips16_op_hash = hash_new (); | |
2389 | ||
2390 | i = 0; | |
2391 | while (i < bfd_mips16_num_opcodes) | |
2392 | { | |
2393 | const char *name = mips16_opcodes[i].name; | |
2394 | ||
17a2f251 | 2395 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
2396 | if (retval != NULL) |
2397 | as_fatal (_("internal: can't hash `%s': %s"), | |
2398 | mips16_opcodes[i].name, retval); | |
2399 | do | |
2400 | { | |
2401 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
2402 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
2403 | != mips16_opcodes[i].match)) | |
2404 | { | |
2405 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
2406 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
2407 | broken = 1; | |
2408 | } | |
1e915849 RS |
2409 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2410 | { | |
2411 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
2412 | mips16_nop_insn.fixed_p = 1; | |
2413 | } | |
252b5132 RH |
2414 | ++i; |
2415 | } | |
2416 | while (i < bfd_mips16_num_opcodes | |
2417 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
2418 | } | |
2419 | ||
df58fc94 RS |
2420 | micromips_op_hash = hash_new (); |
2421 | ||
2422 | i = 0; | |
2423 | while (i < bfd_micromips_num_opcodes) | |
2424 | { | |
2425 | const char *name = micromips_opcodes[i].name; | |
2426 | ||
2427 | retval = hash_insert (micromips_op_hash, name, | |
2428 | (void *) µmips_opcodes[i]); | |
2429 | if (retval != NULL) | |
2430 | as_fatal (_("internal: can't hash `%s': %s"), | |
2431 | micromips_opcodes[i].name, retval); | |
2432 | do | |
2433 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
2434 | { | |
2435 | struct mips_cl_insn *micromips_nop_insn; | |
2436 | ||
2437 | if (!validate_micromips_insn (µmips_opcodes[i])) | |
2438 | broken = 1; | |
2439 | ||
2440 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
2441 | micromips_nop_insn = µmips_nop16_insn; | |
2442 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
2443 | micromips_nop_insn = µmips_nop32_insn; | |
2444 | else | |
2445 | continue; | |
2446 | ||
2447 | if (micromips_nop_insn->insn_mo == NULL | |
2448 | && strcmp (name, "nop") == 0) | |
2449 | { | |
2450 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
2451 | micromips_nop_insn->fixed_p = 1; | |
2452 | } | |
2453 | } | |
2454 | while (++i < bfd_micromips_num_opcodes | |
2455 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
2456 | } | |
2457 | ||
252b5132 RH |
2458 | if (broken) |
2459 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2460 | ||
2461 | /* We add all the general register names to the symbol table. This | |
2462 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
2463 | for (i = 0; reg_names[i].name; i++) |
2464 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 2465 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
2466 | &zero_address_frag)); |
2467 | if (HAVE_NEWABI) | |
2468 | for (i = 0; reg_names_n32n64[i].name; i++) | |
2469 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 2470 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 2471 | &zero_address_frag)); |
707bfff6 TS |
2472 | else |
2473 | for (i = 0; reg_names_o32[i].name; i++) | |
2474 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 2475 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 2476 | &zero_address_frag)); |
6047c971 | 2477 | |
7d10b47d | 2478 | mips_no_prev_insn (); |
252b5132 RH |
2479 | |
2480 | mips_gprmask = 0; | |
2481 | mips_cprmask[0] = 0; | |
2482 | mips_cprmask[1] = 0; | |
2483 | mips_cprmask[2] = 0; | |
2484 | mips_cprmask[3] = 0; | |
2485 | ||
2486 | /* set the default alignment for the text section (2**2) */ | |
2487 | record_alignment (text_section, 2); | |
2488 | ||
4d0d148d | 2489 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2490 | |
707bfff6 | 2491 | #ifdef OBJ_ELF |
f43abd2b | 2492 | if (IS_ELF) |
252b5132 | 2493 | { |
0a44bf69 RS |
2494 | /* On a native system other than VxWorks, sections must be aligned |
2495 | to 16 byte boundaries. When configured for an embedded ELF | |
2496 | target, we don't bother. */ | |
c41e87e3 CF |
2497 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
2498 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
2499 | { |
2500 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2501 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2502 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2503 | } | |
2504 | ||
2505 | /* Create a .reginfo section for register masks and a .mdebug | |
2506 | section for debugging information. */ | |
2507 | { | |
2508 | segT seg; | |
2509 | subsegT subseg; | |
2510 | flagword flags; | |
2511 | segT sec; | |
2512 | ||
2513 | seg = now_seg; | |
2514 | subseg = now_subseg; | |
2515 | ||
2516 | /* The ABI says this section should be loaded so that the | |
2517 | running program can access it. However, we don't load it | |
2518 | if we are configured for an embedded target */ | |
2519 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2520 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2521 | flags |= SEC_ALLOC | SEC_LOAD; |
2522 | ||
316f5878 | 2523 | if (mips_abi != N64_ABI) |
252b5132 RH |
2524 | { |
2525 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2526 | ||
195325d2 TS |
2527 | bfd_set_section_flags (stdoutput, sec, flags); |
2528 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2529 | |
252b5132 | 2530 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2531 | } |
2532 | else | |
2533 | { | |
2534 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2535 | .reginfo section. */ | |
2536 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2537 | bfd_set_section_flags (stdoutput, sec, flags); |
2538 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2539 | |
252b5132 RH |
2540 | /* Set up the option header. */ |
2541 | { | |
2542 | Elf_Internal_Options opthdr; | |
2543 | char *f; | |
2544 | ||
2545 | opthdr.kind = ODK_REGINFO; | |
2546 | opthdr.size = (sizeof (Elf_External_Options) | |
2547 | + sizeof (Elf64_External_RegInfo)); | |
2548 | opthdr.section = 0; | |
2549 | opthdr.info = 0; | |
2550 | f = frag_more (sizeof (Elf_External_Options)); | |
2551 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2552 | (Elf_External_Options *) f); | |
2553 | ||
2554 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2555 | } | |
252b5132 RH |
2556 | } |
2557 | ||
2558 | if (ECOFF_DEBUGGING) | |
2559 | { | |
2560 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2561 | (void) bfd_set_section_flags (stdoutput, sec, | |
2562 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2563 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2564 | } | |
f43abd2b | 2565 | else if (mips_flag_pdr) |
ecb4347a DJ |
2566 | { |
2567 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2568 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2569 | SEC_READONLY | SEC_RELOC | |
2570 | | SEC_DEBUGGING); | |
2571 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2572 | } | |
252b5132 RH |
2573 | |
2574 | subseg_set (seg, subseg); | |
2575 | } | |
2576 | } | |
707bfff6 | 2577 | #endif /* OBJ_ELF */ |
252b5132 RH |
2578 | |
2579 | if (! ECOFF_DEBUGGING) | |
2580 | md_obj_begin (); | |
71400594 RS |
2581 | |
2582 | if (mips_fix_vr4120) | |
2583 | init_vr4120_conflicts (); | |
252b5132 RH |
2584 | } |
2585 | ||
2586 | void | |
17a2f251 | 2587 | md_mips_end (void) |
252b5132 | 2588 | { |
02b1ab82 | 2589 | mips_emit_delays (); |
252b5132 RH |
2590 | if (! ECOFF_DEBUGGING) |
2591 | md_obj_end (); | |
2592 | } | |
2593 | ||
2594 | void | |
17a2f251 | 2595 | md_assemble (char *str) |
252b5132 RH |
2596 | { |
2597 | struct mips_cl_insn insn; | |
f6688943 TS |
2598 | bfd_reloc_code_real_type unused_reloc[3] |
2599 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2600 | |
2601 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2602 | imm2_expr.X_op = O_absent; |
252b5132 | 2603 | offset_expr.X_op = O_absent; |
f6688943 TS |
2604 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2605 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2606 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2607 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2608 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2609 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 2610 | |
e1b47bd5 RS |
2611 | mips_mark_labels (); |
2612 | mips_assembling_insn = TRUE; | |
2613 | ||
252b5132 RH |
2614 | if (mips_opts.mips16) |
2615 | mips16_ip (str, &insn); | |
2616 | else | |
2617 | { | |
2618 | mips_ip (str, &insn); | |
beae10d5 KH |
2619 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2620 | str, insn.insn_opcode)); | |
252b5132 RH |
2621 | } |
2622 | ||
2623 | if (insn_error) | |
e1b47bd5 RS |
2624 | as_bad ("%s `%s'", insn_error, str); |
2625 | else if (insn.insn_mo->pinfo == INSN_MACRO) | |
252b5132 | 2626 | { |
584892a6 | 2627 | macro_start (); |
252b5132 RH |
2628 | if (mips_opts.mips16) |
2629 | mips16_macro (&insn); | |
2630 | else | |
2631 | macro (&insn); | |
584892a6 | 2632 | macro_end (); |
252b5132 RH |
2633 | } |
2634 | else | |
2635 | { | |
2636 | if (imm_expr.X_op != O_absent) | |
df58fc94 | 2637 | append_insn (&insn, &imm_expr, imm_reloc, FALSE); |
252b5132 | 2638 | else if (offset_expr.X_op != O_absent) |
df58fc94 | 2639 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 2640 | else |
df58fc94 | 2641 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 2642 | } |
e1b47bd5 RS |
2643 | |
2644 | mips_assembling_insn = FALSE; | |
252b5132 RH |
2645 | } |
2646 | ||
738e5348 RS |
2647 | /* Convenience functions for abstracting away the differences between |
2648 | MIPS16 and non-MIPS16 relocations. */ | |
2649 | ||
2650 | static inline bfd_boolean | |
2651 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2652 | { | |
2653 | switch (reloc) | |
2654 | { | |
2655 | case BFD_RELOC_MIPS16_JMP: | |
2656 | case BFD_RELOC_MIPS16_GPREL: | |
2657 | case BFD_RELOC_MIPS16_GOT16: | |
2658 | case BFD_RELOC_MIPS16_CALL16: | |
2659 | case BFD_RELOC_MIPS16_HI16_S: | |
2660 | case BFD_RELOC_MIPS16_HI16: | |
2661 | case BFD_RELOC_MIPS16_LO16: | |
2662 | return TRUE; | |
2663 | ||
2664 | default: | |
2665 | return FALSE; | |
2666 | } | |
2667 | } | |
2668 | ||
df58fc94 RS |
2669 | static inline bfd_boolean |
2670 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
2671 | { | |
2672 | switch (reloc) | |
2673 | { | |
2674 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
2675 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
2676 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
2677 | case BFD_RELOC_MICROMIPS_GPREL16: | |
2678 | case BFD_RELOC_MICROMIPS_JMP: | |
2679 | case BFD_RELOC_MICROMIPS_HI16: | |
2680 | case BFD_RELOC_MICROMIPS_HI16_S: | |
2681 | case BFD_RELOC_MICROMIPS_LO16: | |
2682 | case BFD_RELOC_MICROMIPS_LITERAL: | |
2683 | case BFD_RELOC_MICROMIPS_GOT16: | |
2684 | case BFD_RELOC_MICROMIPS_CALL16: | |
2685 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
2686 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
2687 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
2688 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
2689 | case BFD_RELOC_MICROMIPS_SUB: | |
2690 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
2691 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
2692 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
2693 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
2694 | case BFD_RELOC_MICROMIPS_HIGHER: | |
2695 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
2696 | case BFD_RELOC_MICROMIPS_JALR: | |
2697 | return TRUE; | |
2698 | ||
2699 | default: | |
2700 | return FALSE; | |
2701 | } | |
2702 | } | |
2703 | ||
2309ddf2 MR |
2704 | static inline bfd_boolean |
2705 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
2706 | { | |
2707 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
2708 | } | |
2709 | ||
738e5348 RS |
2710 | static inline bfd_boolean |
2711 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2712 | { | |
2309ddf2 | 2713 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 2714 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
2715 | } |
2716 | ||
2717 | static inline bfd_boolean | |
2718 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2719 | { | |
2309ddf2 | 2720 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 2721 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
2722 | } |
2723 | ||
2724 | static inline bfd_boolean | |
2725 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2726 | { | |
2309ddf2 | 2727 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
2728 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
2729 | } | |
2730 | ||
df58fc94 RS |
2731 | static inline bfd_boolean |
2732 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
2733 | { | |
2309ddf2 | 2734 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
2735 | } |
2736 | ||
5919d012 | 2737 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2738 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2739 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2740 | |
2741 | static inline bfd_boolean | |
17a2f251 | 2742 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2743 | { |
3b91255e | 2744 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2745 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2746 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2747 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2748 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2749 | } | |
2750 | ||
2751 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2752 | reloc_needs_lo_p. */ | |
2753 | ||
2754 | static inline bfd_reloc_code_real_type | |
2755 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2756 | { | |
df58fc94 RS |
2757 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
2758 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
2759 | : BFD_RELOC_LO16)); | |
5919d012 RS |
2760 | } |
2761 | ||
2762 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2763 | relocation. */ | |
2764 | ||
2765 | static inline bfd_boolean | |
17a2f251 | 2766 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2767 | { |
2768 | return (fixp->fx_next != NULL | |
738e5348 | 2769 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2770 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2771 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2772 | } | |
2773 | ||
252b5132 RH |
2774 | /* This function returns true if modifying a register requires a |
2775 | delay. */ | |
2776 | ||
2777 | static int | |
17a2f251 | 2778 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2779 | { |
2780 | unsigned long prev_pinfo; | |
2781 | ||
47e39b9d | 2782 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2783 | if (! mips_opts.noreorder |
81912461 ILT |
2784 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2785 | && ! gpr_interlocks) | |
2786 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2787 | && ! cop_interlocks))) | |
252b5132 | 2788 | { |
81912461 ILT |
2789 | /* A load from a coprocessor or from memory. All load delays |
2790 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2791 | /* Itbl support may require additional care here. */ |
252b5132 | 2792 | know (prev_pinfo & INSN_WRITE_GPR_T); |
df58fc94 | 2793 | if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0])) |
252b5132 RH |
2794 | return 1; |
2795 | } | |
2796 | ||
2797 | return 0; | |
2798 | } | |
2799 | ||
462427c4 RS |
2800 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
2801 | says whether the labels refer to text or data. */ | |
404a8071 RS |
2802 | |
2803 | static void | |
462427c4 | 2804 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
2805 | { |
2806 | struct insn_label_list *l; | |
2807 | valueT val; | |
2808 | ||
462427c4 | 2809 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 2810 | { |
9c2799c2 | 2811 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
2812 | symbol_set_frag (l->label, frag_now); |
2813 | val = (valueT) frag_now_fix (); | |
df58fc94 | 2814 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 2815 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
2816 | ++val; |
2817 | S_SET_VALUE (l->label, val); | |
2818 | } | |
2819 | } | |
2820 | ||
462427c4 RS |
2821 | /* Move all labels in insn_labels to the current insertion point |
2822 | and treat them as text labels. */ | |
2823 | ||
2824 | static void | |
2825 | mips_move_text_labels (void) | |
2826 | { | |
2827 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
2828 | } | |
2829 | ||
5f0fe04b TS |
2830 | static bfd_boolean |
2831 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2832 | { | |
2833 | bfd_boolean linkonce = FALSE; | |
2834 | segT symseg = S_GET_SEGMENT (sym); | |
2835 | ||
2836 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2837 | { | |
2838 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2839 | linkonce = TRUE; | |
2840 | #ifdef OBJ_ELF | |
2841 | /* The GNU toolchain uses an extension for ELF: a section | |
2842 | beginning with the magic string .gnu.linkonce is a | |
2843 | linkonce section. */ | |
2844 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2845 | sizeof ".gnu.linkonce" - 1) == 0) | |
2846 | linkonce = TRUE; | |
2847 | #endif | |
2848 | } | |
2849 | return linkonce; | |
2850 | } | |
2851 | ||
e1b47bd5 | 2852 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
2853 | linker to handle them specially, such as generating jalx instructions |
2854 | when needed. We also make them odd for the duration of the assembly, | |
2855 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
2856 | in the adjust_symtab routine, while leaving them marked. This is |
2857 | convenient for the debugger and the disassembler. The linker knows | |
2858 | to make them odd again. */ | |
2859 | ||
2860 | static void | |
e1b47bd5 | 2861 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 2862 | { |
df58fc94 | 2863 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 2864 | |
a8dbcb85 | 2865 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) |
e1b47bd5 RS |
2866 | if (IS_ELF) |
2867 | { | |
2868 | if (mips_opts.mips16) | |
2869 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
2870 | else | |
2871 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
252b5132 | 2872 | } |
e1b47bd5 RS |
2873 | #endif |
2874 | if ((S_GET_VALUE (label) & 1) == 0 | |
2875 | /* Don't adjust the address if the label is global or weak, or | |
2876 | in a link-once section, since we'll be emitting symbol reloc | |
2877 | references to it which will be patched up by the linker, and | |
2878 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
2879 | && !S_IS_WEAK (label) | |
2880 | && !S_IS_EXTERNAL (label) | |
2881 | && !s_is_linkonce (label, now_seg)) | |
2882 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
2883 | } | |
2884 | ||
2885 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
2886 | ||
2887 | static void | |
2888 | mips_compressed_mark_labels (void) | |
2889 | { | |
2890 | struct insn_label_list *l; | |
2891 | ||
2892 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
2893 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
2894 | } |
2895 | ||
4d7206a2 RS |
2896 | /* End the current frag. Make it a variant frag and record the |
2897 | relaxation info. */ | |
2898 | ||
2899 | static void | |
2900 | relax_close_frag (void) | |
2901 | { | |
584892a6 | 2902 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2903 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2904 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2905 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2906 | ||
2907 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2908 | mips_relax.first_fixup = 0; | |
2909 | } | |
2910 | ||
2911 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2912 | See the comment above RELAX_ENCODE for more details. */ | |
2913 | ||
2914 | static void | |
2915 | relax_start (symbolS *symbol) | |
2916 | { | |
9c2799c2 | 2917 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
2918 | mips_relax.sequence = 1; |
2919 | mips_relax.symbol = symbol; | |
2920 | } | |
2921 | ||
2922 | /* Start generating the second version of a relaxable sequence. | |
2923 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2924 | |
2925 | static void | |
4d7206a2 RS |
2926 | relax_switch (void) |
2927 | { | |
9c2799c2 | 2928 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
2929 | mips_relax.sequence = 2; |
2930 | } | |
2931 | ||
2932 | /* End the current relaxable sequence. */ | |
2933 | ||
2934 | static void | |
2935 | relax_end (void) | |
2936 | { | |
9c2799c2 | 2937 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
2938 | relax_close_frag (); |
2939 | mips_relax.sequence = 0; | |
2940 | } | |
2941 | ||
11625dd8 RS |
2942 | /* Return true if IP is a delayed branch or jump. */ |
2943 | ||
2944 | static inline bfd_boolean | |
2945 | delayed_branch_p (const struct mips_cl_insn *ip) | |
2946 | { | |
2947 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2948 | | INSN_COND_BRANCH_DELAY | |
2949 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
2950 | } | |
2951 | ||
2952 | /* Return true if IP is a compact branch or jump. */ | |
2953 | ||
2954 | static inline bfd_boolean | |
2955 | compact_branch_p (const struct mips_cl_insn *ip) | |
2956 | { | |
2957 | if (mips_opts.mips16) | |
2958 | return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
2959 | | MIPS16_INSN_COND_BRANCH)) != 0; | |
2960 | else | |
2961 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH | |
2962 | | INSN2_COND_BRANCH)) != 0; | |
2963 | } | |
2964 | ||
2965 | /* Return true if IP is an unconditional branch or jump. */ | |
2966 | ||
2967 | static inline bfd_boolean | |
2968 | uncond_branch_p (const struct mips_cl_insn *ip) | |
2969 | { | |
2970 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
2971 | || (mips_opts.mips16 | |
2972 | ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0 | |
2973 | : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0)); | |
2974 | } | |
2975 | ||
2976 | /* Return true if IP is a branch-likely instruction. */ | |
2977 | ||
2978 | static inline bfd_boolean | |
2979 | branch_likely_p (const struct mips_cl_insn *ip) | |
2980 | { | |
2981 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
2982 | } | |
2983 | ||
14fe068b RS |
2984 | /* Return the type of nop that should be used to fill the delay slot |
2985 | of delayed branch IP. */ | |
2986 | ||
2987 | static struct mips_cl_insn * | |
2988 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
2989 | { | |
2990 | if (mips_opts.micromips | |
2991 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
2992 | return µmips_nop32_insn; | |
2993 | return NOP_INSN; | |
2994 | } | |
2995 | ||
2309ddf2 | 2996 | /* Return the mask of core registers that IP reads or writes. */ |
df58fc94 RS |
2997 | |
2998 | static unsigned int | |
2999 | gpr_mod_mask (const struct mips_cl_insn *ip) | |
3000 | { | |
2309ddf2 | 3001 | unsigned long pinfo2; |
df58fc94 RS |
3002 | unsigned int mask; |
3003 | ||
3004 | mask = 0; | |
df58fc94 RS |
3005 | pinfo2 = ip->insn_mo->pinfo2; |
3006 | if (mips_opts.micromips) | |
3007 | { | |
df58fc94 RS |
3008 | if (pinfo2 & INSN2_MOD_GPR_MD) |
3009 | mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)]; | |
df58fc94 RS |
3010 | if (pinfo2 & INSN2_MOD_GPR_MF) |
3011 | mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)]; | |
df58fc94 RS |
3012 | if (pinfo2 & INSN2_MOD_SP) |
3013 | mask |= 1 << SP; | |
3014 | } | |
3015 | return mask; | |
3016 | } | |
3017 | ||
4c260379 RS |
3018 | /* Return the mask of core registers that IP reads. */ |
3019 | ||
3020 | static unsigned int | |
3021 | gpr_read_mask (const struct mips_cl_insn *ip) | |
3022 | { | |
3023 | unsigned long pinfo, pinfo2; | |
3024 | unsigned int mask; | |
3025 | ||
df58fc94 | 3026 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3027 | pinfo = ip->insn_mo->pinfo; |
3028 | pinfo2 = ip->insn_mo->pinfo2; | |
3029 | if (mips_opts.mips16) | |
3030 | { | |
3031 | if (pinfo & MIPS16_INSN_READ_X) | |
3032 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3033 | if (pinfo & MIPS16_INSN_READ_Y) | |
3034 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3035 | if (pinfo & MIPS16_INSN_READ_T) | |
3036 | mask |= 1 << TREG; | |
3037 | if (pinfo & MIPS16_INSN_READ_SP) | |
3038 | mask |= 1 << SP; | |
3039 | if (pinfo & MIPS16_INSN_READ_31) | |
3040 | mask |= 1 << RA; | |
3041 | if (pinfo & MIPS16_INSN_READ_Z) | |
3042 | mask |= 1 << (mips16_to_32_reg_map | |
3043 | [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]); | |
3044 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
3045 | mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); | |
3046 | } | |
3047 | else | |
3048 | { | |
3049 | if (pinfo2 & INSN2_READ_GPR_D) | |
2309ddf2 | 3050 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3051 | if (pinfo & INSN_READ_GPR_T) |
2309ddf2 | 3052 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
4c260379 | 3053 | if (pinfo & INSN_READ_GPR_S) |
2309ddf2 MR |
3054 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
3055 | if (pinfo2 & INSN2_READ_GP) | |
3056 | mask |= 1 << GP; | |
3057 | if (pinfo2 & INSN2_READ_GPR_31) | |
3058 | mask |= 1 << RA; | |
4c260379 | 3059 | if (pinfo2 & INSN2_READ_GPR_Z) |
2309ddf2 | 3060 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3061 | } |
2b0c8b40 MR |
3062 | if (mips_opts.micromips) |
3063 | { | |
3064 | if (pinfo2 & INSN2_READ_GPR_MC) | |
3065 | mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)]; | |
3066 | if (pinfo2 & INSN2_READ_GPR_ME) | |
3067 | mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)]; | |
3068 | if (pinfo2 & INSN2_READ_GPR_MG) | |
3069 | mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)]; | |
3070 | if (pinfo2 & INSN2_READ_GPR_MJ) | |
3071 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3072 | if (pinfo2 & INSN2_READ_GPR_MMN) | |
3073 | { | |
3074 | mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)]; | |
3075 | mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)]; | |
3076 | } | |
3077 | if (pinfo2 & INSN2_READ_GPR_MP) | |
3078 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3079 | if (pinfo2 & INSN2_READ_GPR_MQ) | |
3080 | mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)]; | |
3081 | } | |
fe35f09f RS |
3082 | /* Don't include register 0. */ |
3083 | return mask & ~1; | |
4c260379 RS |
3084 | } |
3085 | ||
3086 | /* Return the mask of core registers that IP writes. */ | |
3087 | ||
3088 | static unsigned int | |
3089 | gpr_write_mask (const struct mips_cl_insn *ip) | |
3090 | { | |
3091 | unsigned long pinfo, pinfo2; | |
3092 | unsigned int mask; | |
3093 | ||
df58fc94 | 3094 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3095 | pinfo = ip->insn_mo->pinfo; |
3096 | pinfo2 = ip->insn_mo->pinfo2; | |
3097 | if (mips_opts.mips16) | |
3098 | { | |
3099 | if (pinfo & MIPS16_INSN_WRITE_X) | |
3100 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3101 | if (pinfo & MIPS16_INSN_WRITE_Y) | |
3102 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3103 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
3104 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)]; | |
3105 | if (pinfo & MIPS16_INSN_WRITE_T) | |
3106 | mask |= 1 << TREG; | |
3107 | if (pinfo & MIPS16_INSN_WRITE_SP) | |
3108 | mask |= 1 << SP; | |
3109 | if (pinfo & MIPS16_INSN_WRITE_31) | |
3110 | mask |= 1 << RA; | |
3111 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3112 | mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3113 | } | |
3114 | else | |
3115 | { | |
3116 | if (pinfo & INSN_WRITE_GPR_D) | |
df58fc94 | 3117 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3118 | if (pinfo & INSN_WRITE_GPR_T) |
df58fc94 | 3119 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
2b0c8b40 | 3120 | if (pinfo & INSN_WRITE_GPR_S) |
2309ddf2 | 3121 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
4c260379 RS |
3122 | if (pinfo & INSN_WRITE_GPR_31) |
3123 | mask |= 1 << RA; | |
3124 | if (pinfo2 & INSN2_WRITE_GPR_Z) | |
df58fc94 | 3125 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3126 | } |
2b0c8b40 MR |
3127 | if (mips_opts.micromips) |
3128 | { | |
3129 | if (pinfo2 & INSN2_WRITE_GPR_MB) | |
3130 | mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)]; | |
3131 | if (pinfo2 & INSN2_WRITE_GPR_MHI) | |
3132 | { | |
3133 | mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)]; | |
3134 | mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)]; | |
3135 | } | |
3136 | if (pinfo2 & INSN2_WRITE_GPR_MJ) | |
3137 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3138 | if (pinfo2 & INSN2_WRITE_GPR_MP) | |
3139 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3140 | } | |
fe35f09f RS |
3141 | /* Don't include register 0. */ |
3142 | return mask & ~1; | |
4c260379 RS |
3143 | } |
3144 | ||
3145 | /* Return the mask of floating-point registers that IP reads. */ | |
3146 | ||
3147 | static unsigned int | |
3148 | fpr_read_mask (const struct mips_cl_insn *ip) | |
3149 | { | |
3150 | unsigned long pinfo, pinfo2; | |
3151 | unsigned int mask; | |
3152 | ||
3153 | mask = 0; | |
3154 | pinfo = ip->insn_mo->pinfo; | |
3155 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3156 | if (!mips_opts.mips16) |
df58fc94 RS |
3157 | { |
3158 | if (pinfo2 & INSN2_READ_FPR_D) | |
2309ddf2 | 3159 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3160 | if (pinfo & INSN_READ_FPR_S) |
df58fc94 | 3161 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3162 | if (pinfo & INSN_READ_FPR_T) |
df58fc94 | 3163 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3164 | if (pinfo & INSN_READ_FPR_R) |
df58fc94 | 3165 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip); |
4c260379 | 3166 | if (pinfo2 & INSN2_READ_FPR_Z) |
df58fc94 | 3167 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3168 | } |
3169 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3170 | (This is overly pessimistic for things like cvt.d.s.) */ | |
3171 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3172 | mask |= mask << 1; | |
3173 | return mask; | |
3174 | } | |
3175 | ||
3176 | /* Return the mask of floating-point registers that IP writes. */ | |
3177 | ||
3178 | static unsigned int | |
3179 | fpr_write_mask (const struct mips_cl_insn *ip) | |
3180 | { | |
3181 | unsigned long pinfo, pinfo2; | |
3182 | unsigned int mask; | |
3183 | ||
3184 | mask = 0; | |
3185 | pinfo = ip->insn_mo->pinfo; | |
3186 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3187 | if (!mips_opts.mips16) |
4c260379 RS |
3188 | { |
3189 | if (pinfo & INSN_WRITE_FPR_D) | |
df58fc94 | 3190 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3191 | if (pinfo & INSN_WRITE_FPR_S) |
df58fc94 | 3192 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3193 | if (pinfo & INSN_WRITE_FPR_T) |
df58fc94 | 3194 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3195 | if (pinfo2 & INSN2_WRITE_FPR_Z) |
df58fc94 | 3196 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3197 | } |
3198 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3199 | (This is overly pessimistic for things like cvt.s.d.) */ | |
3200 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3201 | mask |= mask << 1; | |
3202 | return mask; | |
3203 | } | |
3204 | ||
71400594 RS |
3205 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
3206 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
3207 | by VR4120 errata. */ | |
4d7206a2 | 3208 | |
71400594 RS |
3209 | static unsigned int |
3210 | classify_vr4120_insn (const char *name) | |
252b5132 | 3211 | { |
71400594 RS |
3212 | if (strncmp (name, "macc", 4) == 0) |
3213 | return FIX_VR4120_MACC; | |
3214 | if (strncmp (name, "dmacc", 5) == 0) | |
3215 | return FIX_VR4120_DMACC; | |
3216 | if (strncmp (name, "mult", 4) == 0) | |
3217 | return FIX_VR4120_MULT; | |
3218 | if (strncmp (name, "dmult", 5) == 0) | |
3219 | return FIX_VR4120_DMULT; | |
3220 | if (strstr (name, "div")) | |
3221 | return FIX_VR4120_DIV; | |
3222 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
3223 | return FIX_VR4120_MTHILO; | |
3224 | return NUM_FIX_VR4120_CLASSES; | |
3225 | } | |
252b5132 | 3226 | |
ff239038 CM |
3227 | #define INSN_ERET 0x42000018 |
3228 | #define INSN_DERET 0x4200001f | |
3229 | ||
71400594 RS |
3230 | /* Return the number of instructions that must separate INSN1 and INSN2, |
3231 | where INSN1 is the earlier instruction. Return the worst-case value | |
3232 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 3233 | |
71400594 RS |
3234 | static unsigned int |
3235 | insns_between (const struct mips_cl_insn *insn1, | |
3236 | const struct mips_cl_insn *insn2) | |
3237 | { | |
3238 | unsigned long pinfo1, pinfo2; | |
4c260379 | 3239 | unsigned int mask; |
71400594 RS |
3240 | |
3241 | /* This function needs to know which pinfo flags are set for INSN2 | |
3242 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
4c260379 RS |
3243 | the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2 |
3244 | will have every flag set and INSN2_USES_GPR will always return true. */ | |
71400594 RS |
3245 | pinfo1 = insn1->insn_mo->pinfo; |
3246 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 3247 | |
4c260379 RS |
3248 | #define INSN2_USES_GPR(REG) \ |
3249 | (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0) | |
71400594 RS |
3250 | |
3251 | /* For most targets, write-after-read dependencies on the HI and LO | |
3252 | registers must be separated by at least two instructions. */ | |
3253 | if (!hilo_interlocks) | |
252b5132 | 3254 | { |
71400594 RS |
3255 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
3256 | return 2; | |
3257 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
3258 | return 2; | |
3259 | } | |
3260 | ||
3261 | /* If we're working around r7000 errata, there must be two instructions | |
3262 | between an mfhi or mflo and any instruction that uses the result. */ | |
3263 | if (mips_7000_hilo_fix | |
df58fc94 | 3264 | && !mips_opts.micromips |
71400594 | 3265 | && MF_HILO_INSN (pinfo1) |
df58fc94 | 3266 | && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1))) |
71400594 RS |
3267 | return 2; |
3268 | ||
ff239038 CM |
3269 | /* If we're working around 24K errata, one instruction is required |
3270 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 3271 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
3272 | { |
3273 | if (insn1->insn_opcode == INSN_ERET | |
3274 | || insn1->insn_opcode == INSN_DERET) | |
3275 | { | |
3276 | if (insn2 == NULL | |
3277 | || insn2->insn_opcode == INSN_ERET | |
3278 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 3279 | || delayed_branch_p (insn2)) |
ff239038 CM |
3280 | return 1; |
3281 | } | |
3282 | } | |
3283 | ||
71400594 RS |
3284 | /* If working around VR4120 errata, check for combinations that need |
3285 | a single intervening instruction. */ | |
df58fc94 | 3286 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
3287 | { |
3288 | unsigned int class1, class2; | |
252b5132 | 3289 | |
71400594 RS |
3290 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
3291 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 3292 | { |
71400594 RS |
3293 | if (insn2 == NULL) |
3294 | return 1; | |
3295 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
3296 | if (vr4120_conflicts[class1] & (1 << class2)) | |
3297 | return 1; | |
252b5132 | 3298 | } |
71400594 RS |
3299 | } |
3300 | ||
df58fc94 | 3301 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
3302 | { |
3303 | /* Check for GPR or coprocessor load delays. All such delays | |
3304 | are on the RT register. */ | |
3305 | /* Itbl support may require additional care here. */ | |
3306 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
3307 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 3308 | { |
71400594 | 3309 | know (pinfo1 & INSN_WRITE_GPR_T); |
df58fc94 | 3310 | if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1))) |
71400594 RS |
3311 | return 1; |
3312 | } | |
3313 | ||
3314 | /* Check for generic coprocessor hazards. | |
3315 | ||
3316 | This case is not handled very well. There is no special | |
3317 | knowledge of CP0 handling, and the coprocessors other than | |
3318 | the floating point unit are not distinguished at all. */ | |
3319 | /* Itbl support may require additional care here. FIXME! | |
3320 | Need to modify this to include knowledge about | |
3321 | user specified delays! */ | |
3322 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
3323 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
3324 | { | |
3325 | /* Handle cases where INSN1 writes to a known general coprocessor | |
3326 | register. There must be a one instruction delay before INSN2 | |
3327 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
3328 | mask = fpr_write_mask (insn1); |
3329 | if (mask != 0) | |
252b5132 | 3330 | { |
4c260379 | 3331 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 3332 | return 1; |
252b5132 RH |
3333 | } |
3334 | else | |
3335 | { | |
71400594 RS |
3336 | /* Read-after-write dependencies on the control registers |
3337 | require a two-instruction gap. */ | |
3338 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
3339 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3340 | return 2; | |
3341 | ||
3342 | /* We don't know exactly what INSN1 does. If INSN2 is | |
3343 | also a coprocessor instruction, assume there must be | |
3344 | a one instruction gap. */ | |
3345 | if (pinfo2 & INSN_COP) | |
3346 | return 1; | |
252b5132 RH |
3347 | } |
3348 | } | |
6b76fefe | 3349 | |
71400594 RS |
3350 | /* Check for read-after-write dependencies on the coprocessor |
3351 | control registers in cases where INSN1 does not need a general | |
3352 | coprocessor delay. This means that INSN1 is a floating point | |
3353 | comparison instruction. */ | |
3354 | /* Itbl support may require additional care here. */ | |
3355 | else if (!cop_interlocks | |
3356 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
3357 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3358 | return 1; | |
3359 | } | |
6b76fefe | 3360 | |
4c260379 | 3361 | #undef INSN2_USES_GPR |
6b76fefe | 3362 | |
71400594 RS |
3363 | return 0; |
3364 | } | |
6b76fefe | 3365 | |
7d8e00cf RS |
3366 | /* Return the number of nops that would be needed to work around the |
3367 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
3368 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
3369 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
3370 | |
3371 | static int | |
932d1a1b | 3372 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
3373 | const struct mips_cl_insn *insn) |
3374 | { | |
4c260379 RS |
3375 | int i, j; |
3376 | unsigned int mask; | |
7d8e00cf RS |
3377 | |
3378 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
3379 | are not affected by the errata. */ | |
3380 | if (insn != 0 | |
3381 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
3382 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
3383 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
3384 | return 0; | |
3385 | ||
3386 | /* Search for the first MFLO or MFHI. */ | |
3387 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 3388 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
3389 | { |
3390 | /* Extract the destination register. */ | |
4c260379 | 3391 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
3392 | |
3393 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 3394 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
3395 | return 0; |
3396 | ||
3397 | /* ...or if any of the intervening instructions do. */ | |
3398 | for (j = 0; j < i; j++) | |
4c260379 | 3399 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
3400 | return 0; |
3401 | ||
932d1a1b RS |
3402 | if (i >= ignore) |
3403 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
3404 | } |
3405 | return 0; | |
3406 | } | |
3407 | ||
15be625d CM |
3408 | #define BASE_REG_EQ(INSN1, INSN2) \ |
3409 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
3410 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
3411 | ||
3412 | /* Return the minimum alignment for this store instruction. */ | |
3413 | ||
3414 | static int | |
3415 | fix_24k_align_to (const struct mips_opcode *mo) | |
3416 | { | |
3417 | if (strcmp (mo->name, "sh") == 0) | |
3418 | return 2; | |
3419 | ||
3420 | if (strcmp (mo->name, "swc1") == 0 | |
3421 | || strcmp (mo->name, "swc2") == 0 | |
3422 | || strcmp (mo->name, "sw") == 0 | |
3423 | || strcmp (mo->name, "sc") == 0 | |
3424 | || strcmp (mo->name, "s.s") == 0) | |
3425 | return 4; | |
3426 | ||
3427 | if (strcmp (mo->name, "sdc1") == 0 | |
3428 | || strcmp (mo->name, "sdc2") == 0 | |
3429 | || strcmp (mo->name, "s.d") == 0) | |
3430 | return 8; | |
3431 | ||
3432 | /* sb, swl, swr */ | |
3433 | return 1; | |
3434 | } | |
3435 | ||
3436 | struct fix_24k_store_info | |
3437 | { | |
3438 | /* Immediate offset, if any, for this store instruction. */ | |
3439 | short off; | |
3440 | /* Alignment required by this store instruction. */ | |
3441 | int align_to; | |
3442 | /* True for register offsets. */ | |
3443 | int register_offset; | |
3444 | }; | |
3445 | ||
3446 | /* Comparison function used by qsort. */ | |
3447 | ||
3448 | static int | |
3449 | fix_24k_sort (const void *a, const void *b) | |
3450 | { | |
3451 | const struct fix_24k_store_info *pos1 = a; | |
3452 | const struct fix_24k_store_info *pos2 = b; | |
3453 | ||
3454 | return (pos1->off - pos2->off); | |
3455 | } | |
3456 | ||
3457 | /* INSN is a store instruction. Try to record the store information | |
3458 | in STINFO. Return false if the information isn't known. */ | |
3459 | ||
3460 | static bfd_boolean | |
3461 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 3462 | const struct mips_cl_insn *insn) |
15be625d CM |
3463 | { |
3464 | /* The instruction must have a known offset. */ | |
3465 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
3466 | return FALSE; | |
3467 | ||
3468 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
3469 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
3470 | return TRUE; | |
3471 | } | |
3472 | ||
932d1a1b RS |
3473 | /* Return the number of nops that would be needed to work around the 24k |
3474 | "lost data on stores during refill" errata if instruction INSN | |
3475 | immediately followed the 2 instructions described by HIST. | |
3476 | Ignore hazards that are contained within the first IGNORE | |
3477 | instructions of HIST. | |
3478 | ||
3479 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
3480 | for the data cache refills and store data. The following describes | |
3481 | the scenario where the store data could be lost. | |
3482 | ||
3483 | * A data cache miss, due to either a load or a store, causing fill | |
3484 | data to be supplied by the memory subsystem | |
3485 | * The first three doublewords of fill data are returned and written | |
3486 | into the cache | |
3487 | * A sequence of four stores occurs in consecutive cycles around the | |
3488 | final doubleword of the fill: | |
3489 | * Store A | |
3490 | * Store B | |
3491 | * Store C | |
3492 | * Zero, One or more instructions | |
3493 | * Store D | |
3494 | ||
3495 | The four stores A-D must be to different doublewords of the line that | |
3496 | is being filled. The fourth instruction in the sequence above permits | |
3497 | the fill of the final doubleword to be transferred from the FSB into | |
3498 | the cache. In the sequence above, the stores may be either integer | |
3499 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
3500 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
3501 | different doublewords on the line. If the floating point unit is | |
3502 | running in 1:2 mode, it is not possible to create the sequence above | |
3503 | using only floating point store instructions. | |
15be625d CM |
3504 | |
3505 | In this case, the cache line being filled is incorrectly marked | |
3506 | invalid, thereby losing the data from any store to the line that | |
3507 | occurs between the original miss and the completion of the five | |
3508 | cycle sequence shown above. | |
3509 | ||
932d1a1b | 3510 | The workarounds are: |
15be625d | 3511 | |
932d1a1b RS |
3512 | * Run the data cache in write-through mode. |
3513 | * Insert a non-store instruction between | |
3514 | Store A and Store B or Store B and Store C. */ | |
15be625d CM |
3515 | |
3516 | static int | |
932d1a1b | 3517 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
3518 | const struct mips_cl_insn *insn) |
3519 | { | |
3520 | struct fix_24k_store_info pos[3]; | |
3521 | int align, i, base_offset; | |
3522 | ||
932d1a1b RS |
3523 | if (ignore >= 2) |
3524 | return 0; | |
3525 | ||
ab9794cf RS |
3526 | /* If the previous instruction wasn't a store, there's nothing to |
3527 | worry about. */ | |
15be625d CM |
3528 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
3529 | return 0; | |
3530 | ||
ab9794cf RS |
3531 | /* If the instructions after the previous one are unknown, we have |
3532 | to assume the worst. */ | |
3533 | if (!insn) | |
15be625d CM |
3534 | return 1; |
3535 | ||
ab9794cf RS |
3536 | /* Check whether we are dealing with three consecutive stores. */ |
3537 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
3538 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
3539 | return 0; |
3540 | ||
3541 | /* If we don't know the relationship between the store addresses, | |
3542 | assume the worst. */ | |
ab9794cf | 3543 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
3544 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
3545 | return 1; | |
3546 | ||
3547 | if (!fix_24k_record_store_info (&pos[0], insn) | |
3548 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
3549 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
3550 | return 1; | |
3551 | ||
3552 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
3553 | ||
3554 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
3555 | X bytes and such that the base register + X is known to be aligned | |
3556 | to align bytes. */ | |
3557 | ||
3558 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
3559 | align = 8; | |
3560 | else | |
3561 | { | |
3562 | align = pos[0].align_to; | |
3563 | base_offset = pos[0].off; | |
3564 | for (i = 1; i < 3; i++) | |
3565 | if (align < pos[i].align_to) | |
3566 | { | |
3567 | align = pos[i].align_to; | |
3568 | base_offset = pos[i].off; | |
3569 | } | |
3570 | for (i = 0; i < 3; i++) | |
3571 | pos[i].off -= base_offset; | |
3572 | } | |
3573 | ||
3574 | pos[0].off &= ~align + 1; | |
3575 | pos[1].off &= ~align + 1; | |
3576 | pos[2].off &= ~align + 1; | |
3577 | ||
3578 | /* If any two stores write to the same chunk, they also write to the | |
3579 | same doubleword. The offsets are still sorted at this point. */ | |
3580 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
3581 | return 0; | |
3582 | ||
3583 | /* A range of at least 9 bytes is needed for the stores to be in | |
3584 | non-overlapping doublewords. */ | |
3585 | if (pos[2].off - pos[0].off <= 8) | |
3586 | return 0; | |
3587 | ||
3588 | if (pos[2].off - pos[1].off >= 24 | |
3589 | || pos[1].off - pos[0].off >= 24 | |
3590 | || pos[2].off - pos[0].off >= 32) | |
3591 | return 0; | |
3592 | ||
3593 | return 1; | |
3594 | } | |
3595 | ||
71400594 | 3596 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 3597 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
3598 | where HIST[0] is the most recent instruction. Ignore hazards |
3599 | between INSN and the first IGNORE instructions in HIST. | |
3600 | ||
3601 | If INSN is null, return the worse-case number of nops for any | |
3602 | instruction. */ | |
bdaaa2e1 | 3603 | |
71400594 | 3604 | static int |
932d1a1b | 3605 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3606 | const struct mips_cl_insn *insn) |
3607 | { | |
3608 | int i, nops, tmp_nops; | |
bdaaa2e1 | 3609 | |
71400594 | 3610 | nops = 0; |
932d1a1b | 3611 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 3612 | { |
91d6fa6a | 3613 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
3614 | if (tmp_nops > nops) |
3615 | nops = tmp_nops; | |
3616 | } | |
7d8e00cf | 3617 | |
df58fc94 | 3618 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 3619 | { |
932d1a1b | 3620 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
3621 | if (tmp_nops > nops) |
3622 | nops = tmp_nops; | |
3623 | } | |
3624 | ||
df58fc94 | 3625 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 3626 | { |
932d1a1b | 3627 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
3628 | if (tmp_nops > nops) |
3629 | nops = tmp_nops; | |
3630 | } | |
3631 | ||
71400594 RS |
3632 | return nops; |
3633 | } | |
252b5132 | 3634 | |
71400594 | 3635 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 3636 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
3637 | would be needed after the extended sequence, ignoring hazards |
3638 | in the first IGNORE instructions. */ | |
252b5132 | 3639 | |
71400594 | 3640 | static int |
932d1a1b RS |
3641 | nops_for_sequence (int num_insns, int ignore, |
3642 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
3643 | { |
3644 | va_list args; | |
3645 | struct mips_cl_insn buffer[MAX_NOPS]; | |
3646 | struct mips_cl_insn *cursor; | |
3647 | int nops; | |
3648 | ||
91d6fa6a | 3649 | va_start (args, hist); |
71400594 | 3650 | cursor = buffer + num_insns; |
91d6fa6a | 3651 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
3652 | while (cursor > buffer) |
3653 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
3654 | ||
932d1a1b | 3655 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
3656 | va_end (args); |
3657 | return nops; | |
3658 | } | |
252b5132 | 3659 | |
71400594 RS |
3660 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
3661 | worst-case delay for the branch target. */ | |
252b5132 | 3662 | |
71400594 | 3663 | static int |
932d1a1b | 3664 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3665 | const struct mips_cl_insn *insn) |
3666 | { | |
3667 | int nops, tmp_nops; | |
60b63b72 | 3668 | |
932d1a1b | 3669 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 3670 | if (delayed_branch_p (insn)) |
71400594 | 3671 | { |
932d1a1b | 3672 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 3673 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
3674 | if (tmp_nops > nops) |
3675 | nops = tmp_nops; | |
3676 | } | |
11625dd8 | 3677 | else if (compact_branch_p (insn)) |
71400594 | 3678 | { |
932d1a1b | 3679 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
3680 | if (tmp_nops > nops) |
3681 | nops = tmp_nops; | |
3682 | } | |
3683 | return nops; | |
3684 | } | |
3685 | ||
c67a084a NC |
3686 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
3687 | ||
3688 | static void | |
3689 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
3690 | { | |
df58fc94 | 3691 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3692 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
3693 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
3694 | } | |
3695 | ||
3696 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
3697 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
3698 | ||
3699 | static void | |
3700 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
3701 | { | |
df58fc94 | 3702 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3703 | if (strcmp (ip->insn_mo->name, "j") == 0 |
3704 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
3705 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
3706 | { | |
3707 | int sreg; | |
3708 | expressionS ep; | |
3709 | ||
3710 | if (! mips_opts.at) | |
3711 | return; | |
3712 | ||
df58fc94 | 3713 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
3714 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
3715 | return; | |
3716 | ||
3717 | ep.X_op = O_constant; | |
3718 | ep.X_add_number = 0xcfff0000; | |
3719 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
3720 | ep.X_add_number = 0xffff; | |
3721 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
3722 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
3723 | } | |
3724 | } | |
3725 | ||
3726 | static void | |
3727 | fix_loongson2f (struct mips_cl_insn * ip) | |
3728 | { | |
3729 | if (mips_fix_loongson2f_nop) | |
3730 | fix_loongson2f_nop (ip); | |
3731 | ||
3732 | if (mips_fix_loongson2f_jump) | |
3733 | fix_loongson2f_jump (ip); | |
3734 | } | |
3735 | ||
a4e06468 RS |
3736 | /* IP is a branch that has a delay slot, and we need to fill it |
3737 | automatically. Return true if we can do that by swapping IP | |
3738 | with the previous instruction. */ | |
3739 | ||
3740 | static bfd_boolean | |
3741 | can_swap_branch_p (struct mips_cl_insn *ip) | |
3742 | { | |
2b0c8b40 | 3743 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 RS |
3744 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
3745 | ||
3746 | /* -O2 and above is required for this optimization. */ | |
3747 | if (mips_optimize < 2) | |
3748 | return FALSE; | |
3749 | ||
3750 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
3751 | if (mips_opts.nomove) | |
3752 | return FALSE; | |
3753 | ||
3754 | /* We can't swap if the previous instruction's position is fixed. */ | |
3755 | if (history[0].fixed_p) | |
3756 | return FALSE; | |
3757 | ||
3758 | /* If the previous previous insn was in a .set noreorder, we can't | |
3759 | swap. Actually, the MIPS assembler will swap in this situation. | |
3760 | However, gcc configured -with-gnu-as will generate code like | |
3761 | ||
3762 | .set noreorder | |
3763 | lw $4,XXX | |
3764 | .set reorder | |
3765 | INSN | |
3766 | bne $4,$0,foo | |
3767 | ||
3768 | in which we can not swap the bne and INSN. If gcc is not configured | |
3769 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
3770 | if (history[1].noreorder_p) | |
3771 | return FALSE; | |
3772 | ||
87333bb7 MR |
3773 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
3774 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
3775 | if (mips_opts.mips16 && history[0].fixp[0]) |
3776 | return FALSE; | |
3777 | ||
3778 | /* If the branch is itself the target of a branch, we can not swap. | |
3779 | We cheat on this; all we check for is whether there is a label on | |
3780 | this instruction. If there are any branches to anything other than | |
3781 | a label, users must use .set noreorder. */ | |
3782 | if (seg_info (now_seg)->label_list) | |
3783 | return FALSE; | |
3784 | ||
3785 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 3786 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
3787 | MIPS16 code, which uses variant frags for different purposes. */ |
3788 | if (!mips_opts.mips16 | |
a4e06468 RS |
3789 | && history[0].frag |
3790 | && history[0].frag->fr_type == rs_machine_dependent) | |
3791 | return FALSE; | |
3792 | ||
bcd530a7 RS |
3793 | /* We do not swap with instructions that cannot architecturally |
3794 | be placed in a branch delay slot, such as SYNC or ERET. We | |
3795 | also refrain from swapping with a trap instruction, since it | |
3796 | complicates trap handlers to have the trap instruction be in | |
3797 | a delay slot. */ | |
a4e06468 | 3798 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 3799 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
3800 | return FALSE; |
3801 | ||
3802 | /* Check for conflicts between the branch and the instructions | |
3803 | before the candidate delay slot. */ | |
3804 | if (nops_for_insn (0, history + 1, ip) > 0) | |
3805 | return FALSE; | |
3806 | ||
3807 | /* Check for conflicts between the swapped sequence and the | |
3808 | target of the branch. */ | |
3809 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
3810 | return FALSE; | |
3811 | ||
3812 | /* If the branch reads a register that the previous | |
3813 | instruction sets, we can not swap. */ | |
3814 | gpr_read = gpr_read_mask (ip); | |
3815 | prev_gpr_write = gpr_write_mask (&history[0]); | |
3816 | if (gpr_read & prev_gpr_write) | |
3817 | return FALSE; | |
3818 | ||
3819 | /* If the branch writes a register that the previous | |
3820 | instruction sets, we can not swap. */ | |
3821 | gpr_write = gpr_write_mask (ip); | |
3822 | if (gpr_write & prev_gpr_write) | |
3823 | return FALSE; | |
3824 | ||
3825 | /* If the branch writes a register that the previous | |
3826 | instruction reads, we can not swap. */ | |
3827 | prev_gpr_read = gpr_read_mask (&history[0]); | |
3828 | if (gpr_write & prev_gpr_read) | |
3829 | return FALSE; | |
3830 | ||
3831 | /* If one instruction sets a condition code and the | |
3832 | other one uses a condition code, we can not swap. */ | |
3833 | pinfo = ip->insn_mo->pinfo; | |
3834 | if ((pinfo & INSN_READ_COND_CODE) | |
3835 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3836 | return FALSE; | |
3837 | if ((pinfo & INSN_WRITE_COND_CODE) | |
3838 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3839 | return FALSE; | |
3840 | ||
3841 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 3842 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
a4e06468 RS |
3843 | if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC)) |
3844 | return FALSE; | |
2b0c8b40 MR |
3845 | if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC)) |
3846 | return FALSE; | |
a4e06468 | 3847 | |
df58fc94 RS |
3848 | /* If the previous instruction has an incorrect size for a fixed |
3849 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
3850 | pinfo2 = ip->insn_mo->pinfo2; |
3851 | if (mips_opts.micromips | |
3852 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
3853 | && insn_length (history) != 2) | |
3854 | return FALSE; | |
3855 | if (mips_opts.micromips | |
3856 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
3857 | && insn_length (history) != 4) | |
3858 | return FALSE; | |
3859 | ||
a4e06468 RS |
3860 | return TRUE; |
3861 | } | |
3862 | ||
3863 | /* Decide how we should add IP to the instruction stream. */ | |
3864 | ||
3865 | static enum append_method | |
3866 | get_append_method (struct mips_cl_insn *ip) | |
3867 | { | |
3868 | unsigned long pinfo; | |
3869 | ||
3870 | /* The relaxed version of a macro sequence must be inherently | |
3871 | hazard-free. */ | |
3872 | if (mips_relax.sequence == 2) | |
3873 | return APPEND_ADD; | |
3874 | ||
3875 | /* We must not dabble with instructions in a ".set norerorder" block. */ | |
3876 | if (mips_opts.noreorder) | |
3877 | return APPEND_ADD; | |
3878 | ||
3879 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 3880 | if (delayed_branch_p (ip)) |
a4e06468 | 3881 | { |
11625dd8 | 3882 | if (!branch_likely_p (ip) && can_swap_branch_p (ip)) |
a4e06468 RS |
3883 | return APPEND_SWAP; |
3884 | ||
11625dd8 | 3885 | pinfo = ip->insn_mo->pinfo; |
a4e06468 RS |
3886 | if (mips_opts.mips16 |
3887 | && ISA_SUPPORTS_MIPS16E | |
a4e06468 RS |
3888 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))) |
3889 | return APPEND_ADD_COMPACT; | |
3890 | ||
3891 | return APPEND_ADD_WITH_NOP; | |
3892 | } | |
3893 | ||
a4e06468 RS |
3894 | return APPEND_ADD; |
3895 | } | |
3896 | ||
ceb94aa5 RS |
3897 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
3898 | Point IP->insn_mo to the new opcode's definition. */ | |
3899 | ||
3900 | static void | |
3901 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
3902 | { | |
3903 | const struct mips_opcode *mo, *end; | |
3904 | ||
3905 | end = &mips16_opcodes[bfd_mips16_num_opcodes]; | |
3906 | for (mo = ip->insn_mo; mo < end; mo++) | |
3907 | if ((ip->insn_opcode & mo->mask) == mo->match) | |
3908 | { | |
3909 | ip->insn_mo = mo; | |
3910 | return; | |
3911 | } | |
3912 | abort (); | |
3913 | } | |
3914 | ||
df58fc94 RS |
3915 | /* For microMIPS macros, we need to generate a local number label |
3916 | as the target of branches. */ | |
3917 | #define MICROMIPS_LABEL_CHAR '\037' | |
3918 | static unsigned long micromips_target_label; | |
3919 | static char micromips_target_name[32]; | |
3920 | ||
3921 | static char * | |
3922 | micromips_label_name (void) | |
3923 | { | |
3924 | char *p = micromips_target_name; | |
3925 | char symbol_name_temporary[24]; | |
3926 | unsigned long l; | |
3927 | int i; | |
3928 | ||
3929 | if (*p) | |
3930 | return p; | |
3931 | ||
3932 | i = 0; | |
3933 | l = micromips_target_label; | |
3934 | #ifdef LOCAL_LABEL_PREFIX | |
3935 | *p++ = LOCAL_LABEL_PREFIX; | |
3936 | #endif | |
3937 | *p++ = 'L'; | |
3938 | *p++ = MICROMIPS_LABEL_CHAR; | |
3939 | do | |
3940 | { | |
3941 | symbol_name_temporary[i++] = l % 10 + '0'; | |
3942 | l /= 10; | |
3943 | } | |
3944 | while (l != 0); | |
3945 | while (i > 0) | |
3946 | *p++ = symbol_name_temporary[--i]; | |
3947 | *p = '\0'; | |
3948 | ||
3949 | return micromips_target_name; | |
3950 | } | |
3951 | ||
3952 | static void | |
3953 | micromips_label_expr (expressionS *label_expr) | |
3954 | { | |
3955 | label_expr->X_op = O_symbol; | |
3956 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
3957 | label_expr->X_add_number = 0; | |
3958 | } | |
3959 | ||
3960 | static void | |
3961 | micromips_label_inc (void) | |
3962 | { | |
3963 | micromips_target_label++; | |
3964 | *micromips_target_name = '\0'; | |
3965 | } | |
3966 | ||
3967 | static void | |
3968 | micromips_add_label (void) | |
3969 | { | |
3970 | symbolS *s; | |
3971 | ||
3972 | s = colon (micromips_label_name ()); | |
3973 | micromips_label_inc (); | |
3974 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
3975 | if (IS_ELF) | |
3976 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); | |
db9b2be4 AM |
3977 | #else |
3978 | (void) s; | |
df58fc94 RS |
3979 | #endif |
3980 | } | |
3981 | ||
3982 | /* If assembling microMIPS code, then return the microMIPS reloc | |
3983 | corresponding to the requested one if any. Otherwise return | |
3984 | the reloc unchanged. */ | |
3985 | ||
3986 | static bfd_reloc_code_real_type | |
3987 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
3988 | { | |
3989 | static const bfd_reloc_code_real_type relocs[][2] = | |
3990 | { | |
3991 | /* Keep sorted incrementally by the left-hand key. */ | |
3992 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
3993 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
3994 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
3995 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
3996 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
3997 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
3998 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
3999 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
4000 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
4001 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
4002 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
4003 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
4004 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
4005 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
4006 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
4007 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
4008 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
4009 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
4010 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
4011 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
4012 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
4013 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
4014 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
4015 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
4016 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
4017 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
4018 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
4019 | }; | |
4020 | bfd_reloc_code_real_type r; | |
4021 | size_t i; | |
4022 | ||
4023 | if (!mips_opts.micromips) | |
4024 | return reloc; | |
4025 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
4026 | { | |
4027 | r = relocs[i][0]; | |
4028 | if (r > reloc) | |
4029 | return reloc; | |
4030 | if (r == reloc) | |
4031 | return relocs[i][1]; | |
4032 | } | |
4033 | return reloc; | |
4034 | } | |
4035 | ||
b886a2ab RS |
4036 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
4037 | Return true on success, storing the resolved value in RESULT. */ | |
4038 | ||
4039 | static bfd_boolean | |
4040 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
4041 | offsetT *result) | |
4042 | { | |
4043 | switch (reloc) | |
4044 | { | |
4045 | case BFD_RELOC_MIPS_HIGHEST: | |
4046 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4047 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
4048 | return TRUE; | |
4049 | ||
4050 | case BFD_RELOC_MIPS_HIGHER: | |
4051 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4052 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
4053 | return TRUE; | |
4054 | ||
4055 | case BFD_RELOC_HI16_S: | |
4056 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4057 | case BFD_RELOC_MIPS16_HI16_S: | |
4058 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
4059 | return TRUE; | |
4060 | ||
4061 | case BFD_RELOC_HI16: | |
4062 | case BFD_RELOC_MICROMIPS_HI16: | |
4063 | case BFD_RELOC_MIPS16_HI16: | |
4064 | *result = (operand >> 16) & 0xffff; | |
4065 | return TRUE; | |
4066 | ||
4067 | case BFD_RELOC_LO16: | |
4068 | case BFD_RELOC_MICROMIPS_LO16: | |
4069 | case BFD_RELOC_MIPS16_LO16: | |
4070 | *result = operand & 0xffff; | |
4071 | return TRUE; | |
4072 | ||
4073 | case BFD_RELOC_UNUSED: | |
4074 | *result = operand; | |
4075 | return TRUE; | |
4076 | ||
4077 | default: | |
4078 | return FALSE; | |
4079 | } | |
4080 | } | |
4081 | ||
71400594 RS |
4082 | /* Output an instruction. IP is the instruction information. |
4083 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
4084 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
4085 | a macro expansion. */ | |
71400594 RS |
4086 | |
4087 | static void | |
4088 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 4089 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 4090 | { |
14fe068b | 4091 | unsigned long prev_pinfo2, pinfo; |
71400594 | 4092 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 4093 | enum append_method method; |
2309ddf2 | 4094 | bfd_boolean relax32; |
2b0c8b40 | 4095 | int branch_disp; |
71400594 | 4096 | |
2309ddf2 | 4097 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
4098 | fix_loongson2f (ip); |
4099 | ||
738f4d98 | 4100 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 4101 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 4102 | |
df58fc94 | 4103 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 4104 | pinfo = ip->insn_mo->pinfo; |
df58fc94 RS |
4105 | |
4106 | if (mips_opts.micromips | |
4107 | && !expansionp | |
4108 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
4109 | && micromips_insn_length (ip->insn_mo) != 2) | |
4110 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
4111 | && micromips_insn_length (ip->insn_mo) != 4))) | |
4112 | as_warn (_("Wrong size instruction in a %u-bit branch delay slot"), | |
4113 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); | |
71400594 | 4114 | |
15be625d CM |
4115 | if (address_expr == NULL) |
4116 | ip->complete_p = 1; | |
b886a2ab RS |
4117 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
4118 | && reloc_type[1] == BFD_RELOC_UNUSED | |
4119 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
4120 | && address_expr->X_op == O_constant) |
4121 | { | |
15be625d CM |
4122 | switch (*reloc_type) |
4123 | { | |
15be625d | 4124 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
4125 | { |
4126 | int shift; | |
4127 | ||
4128 | shift = mips_opts.micromips ? 1 : 2; | |
4129 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4130 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4131 | (unsigned long) address_expr->X_add_number); | |
4132 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4133 | & 0x3ffffff); | |
335574df | 4134 | ip->complete_p = 1; |
df58fc94 | 4135 | } |
15be625d CM |
4136 | break; |
4137 | ||
4138 | case BFD_RELOC_MIPS16_JMP: | |
4139 | if ((address_expr->X_add_number & 3) != 0) | |
4140 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4141 | (unsigned long) address_expr->X_add_number); | |
4142 | ip->insn_opcode |= | |
4143 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
4144 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
4145 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 4146 | ip->complete_p = 1; |
15be625d CM |
4147 | break; |
4148 | ||
4149 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
4150 | { |
4151 | int shift; | |
4152 | ||
4153 | shift = mips_opts.micromips ? 1 : 2; | |
4154 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4155 | as_bad (_("branch to misaligned address (0x%lx)"), | |
4156 | (unsigned long) address_expr->X_add_number); | |
4157 | if (!mips_relax_branch) | |
4158 | { | |
4159 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
4160 | & ~((1 << (shift + 16)) - 1)) | |
4161 | as_bad (_("branch address range overflow (0x%lx)"), | |
4162 | (unsigned long) address_expr->X_add_number); | |
4163 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4164 | & 0xffff); | |
4165 | } | |
df58fc94 | 4166 | } |
15be625d CM |
4167 | break; |
4168 | ||
4169 | default: | |
b886a2ab RS |
4170 | { |
4171 | offsetT value; | |
4172 | ||
4173 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
4174 | &value)) | |
4175 | { | |
4176 | ip->insn_opcode |= value & 0xffff; | |
4177 | ip->complete_p = 1; | |
4178 | } | |
4179 | } | |
4180 | break; | |
4181 | } | |
15be625d CM |
4182 | } |
4183 | ||
71400594 RS |
4184 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
4185 | { | |
4186 | /* There are a lot of optimizations we could do that we don't. | |
4187 | In particular, we do not, in general, reorder instructions. | |
4188 | If you use gcc with optimization, it will reorder | |
4189 | instructions and generally do much more optimization then we | |
4190 | do here; repeating all that work in the assembler would only | |
4191 | benefit hand written assembly code, and does not seem worth | |
4192 | it. */ | |
4193 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
4194 | ? nops_for_insn (0, history, NULL) |
4195 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 4196 | if (nops > 0) |
252b5132 RH |
4197 | { |
4198 | fragS *old_frag; | |
4199 | unsigned long old_frag_offset; | |
4200 | int i; | |
252b5132 RH |
4201 | |
4202 | old_frag = frag_now; | |
4203 | old_frag_offset = frag_now_fix (); | |
4204 | ||
4205 | for (i = 0; i < nops; i++) | |
14fe068b RS |
4206 | add_fixed_insn (NOP_INSN); |
4207 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
4208 | |
4209 | if (listing) | |
4210 | { | |
4211 | listing_prev_line (); | |
4212 | /* We may be at the start of a variant frag. In case we | |
4213 | are, make sure there is enough space for the frag | |
4214 | after the frags created by listing_prev_line. The | |
4215 | argument to frag_grow here must be at least as large | |
4216 | as the argument to all other calls to frag_grow in | |
4217 | this file. We don't have to worry about being in the | |
4218 | middle of a variant frag, because the variants insert | |
4219 | all needed nop instructions themselves. */ | |
4220 | frag_grow (40); | |
4221 | } | |
4222 | ||
462427c4 | 4223 | mips_move_text_labels (); |
252b5132 RH |
4224 | |
4225 | #ifndef NO_ECOFF_DEBUGGING | |
4226 | if (ECOFF_DEBUGGING) | |
4227 | ecoff_fix_loc (old_frag, old_frag_offset); | |
4228 | #endif | |
4229 | } | |
71400594 RS |
4230 | } |
4231 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
4232 | { | |
932d1a1b RS |
4233 | int nops; |
4234 | ||
4235 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
4236 | ignoring hazards generated by the first prev_nop_frag_since | |
4237 | instructions. */ | |
4238 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 4239 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 4240 | |
71400594 RS |
4241 | /* Enforce NOPS as a minimum. */ |
4242 | if (nops > prev_nop_frag_required) | |
4243 | prev_nop_frag_required = nops; | |
252b5132 | 4244 | |
71400594 RS |
4245 | if (prev_nop_frag_holds == prev_nop_frag_required) |
4246 | { | |
4247 | /* Settle for the current number of nops. Update the history | |
4248 | accordingly (for the benefit of any future .set reorder code). */ | |
4249 | prev_nop_frag = NULL; | |
4250 | insert_into_history (prev_nop_frag_since, | |
4251 | prev_nop_frag_holds, NOP_INSN); | |
4252 | } | |
4253 | else | |
4254 | { | |
4255 | /* Allow this instruction to replace one of the nops that was | |
4256 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 4257 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
4258 | prev_nop_frag_holds--; |
4259 | prev_nop_frag_since++; | |
252b5132 RH |
4260 | } |
4261 | } | |
4262 | ||
a4e06468 | 4263 | method = get_append_method (ip); |
2b0c8b40 | 4264 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 4265 | |
58e2ea4d MR |
4266 | #ifdef OBJ_ELF |
4267 | /* The value passed to dwarf2_emit_insn is the distance between | |
4268 | the beginning of the current instruction and the address that | |
e3a82c8e MR |
4269 | should be recorded in the debug tables. This is normally the |
4270 | current address. | |
4271 | ||
df58fc94 RS |
4272 | For MIPS16/microMIPS debug info we want to use ISA-encoded |
4273 | addresses, so we use -1 for an address higher by one than the | |
4274 | current one. | |
e3a82c8e MR |
4275 | |
4276 | If the instruction produced is a branch that we will swap with | |
4277 | the preceding instruction, then we add the displacement by which | |
4278 | the branch will be moved backwards. This is more appropriate | |
2309ddf2 MR |
4279 | and for MIPS16/microMIPS code also prevents a debugger from |
4280 | placing a breakpoint in the middle of the branch (and corrupting | |
4281 | code if software breakpoints are used). */ | |
2b0c8b40 | 4282 | dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) + branch_disp); |
58e2ea4d MR |
4283 | #endif |
4284 | ||
df58fc94 RS |
4285 | relax32 = (mips_relax_branch |
4286 | /* Don't try branch relaxation within .set nomacro, or within | |
4287 | .set noat if we use $at for PIC computations. If it turns | |
4288 | out that the branch was out-of-range, we'll get an error. */ | |
4289 | && !mips_opts.warn_about_macros | |
4290 | && (mips_opts.at || mips_pic == NO_PIC) | |
4291 | /* Don't relax BPOSGE32/64 as they have no complementing | |
4292 | branches. */ | |
40209cad | 4293 | && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))); |
df58fc94 RS |
4294 | |
4295 | if (!HAVE_CODE_COMPRESSION | |
4296 | && address_expr | |
4297 | && relax32 | |
0b25d3e6 | 4298 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 4299 | && delayed_branch_p (ip)) |
4a6a3df4 | 4300 | { |
895921c9 | 4301 | relaxed_branch = TRUE; |
1e915849 RS |
4302 | add_relaxed_insn (ip, (relaxed_branch_length |
4303 | (NULL, NULL, | |
11625dd8 RS |
4304 | uncond_branch_p (ip) ? -1 |
4305 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
4306 | : 0)), 4, |
4307 | RELAX_BRANCH_ENCODE | |
66b3e8da | 4308 | (AT, |
11625dd8 RS |
4309 | uncond_branch_p (ip), |
4310 | branch_likely_p (ip), | |
1e915849 RS |
4311 | pinfo & INSN_WRITE_GPR_31, |
4312 | 0), | |
4313 | address_expr->X_add_symbol, | |
4314 | address_expr->X_add_number); | |
4a6a3df4 AO |
4315 | *reloc_type = BFD_RELOC_UNUSED; |
4316 | } | |
df58fc94 RS |
4317 | else if (mips_opts.micromips |
4318 | && address_expr | |
4319 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
4320 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
4321 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
4322 | /* Don't try branch relaxation when users specify | |
4323 | 16-bit/32-bit instructions. */ | |
4324 | && !forced_insn_length) | |
df58fc94 RS |
4325 | { |
4326 | bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED; | |
4327 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; | |
11625dd8 RS |
4328 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
4329 | int compact = compact_branch_p (ip); | |
df58fc94 RS |
4330 | int al = pinfo & INSN_WRITE_GPR_31; |
4331 | int length32; | |
4332 | ||
4333 | gas_assert (address_expr != NULL); | |
4334 | gas_assert (!mips_relax.sequence); | |
4335 | ||
2b0c8b40 | 4336 | relaxed_branch = TRUE; |
df58fc94 RS |
4337 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); |
4338 | add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4, | |
40209cad MR |
4339 | RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al, |
4340 | relax32, 0, 0), | |
df58fc94 RS |
4341 | address_expr->X_add_symbol, |
4342 | address_expr->X_add_number); | |
4343 | *reloc_type = BFD_RELOC_UNUSED; | |
4344 | } | |
4345 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
4346 | { |
4347 | /* We need to set up a variant frag. */ | |
df58fc94 | 4348 | gas_assert (address_expr != NULL); |
1e915849 RS |
4349 | add_relaxed_insn (ip, 4, 0, |
4350 | RELAX_MIPS16_ENCODE | |
4351 | (*reloc_type - BFD_RELOC_UNUSED, | |
df58fc94 | 4352 | forced_insn_length == 2, forced_insn_length == 4, |
11625dd8 | 4353 | delayed_branch_p (&history[0]), |
1e915849 RS |
4354 | history[0].mips16_absolute_jump_p), |
4355 | make_expr_symbol (address_expr), 0); | |
252b5132 | 4356 | } |
5c04167a | 4357 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 4358 | { |
11625dd8 | 4359 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
4360 | /* Make sure there is enough room to swap this instruction with |
4361 | a following jump instruction. */ | |
4362 | frag_grow (6); | |
1e915849 | 4363 | add_fixed_insn (ip); |
252b5132 RH |
4364 | } |
4365 | else | |
4366 | { | |
4367 | if (mips_opts.mips16 | |
4368 | && mips_opts.noreorder | |
11625dd8 | 4369 | && delayed_branch_p (&history[0])) |
252b5132 RH |
4370 | as_warn (_("extended instruction in delay slot")); |
4371 | ||
4d7206a2 RS |
4372 | if (mips_relax.sequence) |
4373 | { | |
4374 | /* If we've reached the end of this frag, turn it into a variant | |
4375 | frag and record the information for the instructions we've | |
4376 | written so far. */ | |
4377 | if (frag_room () < 4) | |
4378 | relax_close_frag (); | |
df58fc94 | 4379 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
4380 | } |
4381 | ||
584892a6 | 4382 | if (mips_relax.sequence != 2) |
df58fc94 RS |
4383 | { |
4384 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
4385 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
4386 | mips_macro_warning.sizes[0] += insn_length (ip); | |
4387 | mips_macro_warning.insns[0]++; | |
4388 | } | |
584892a6 | 4389 | if (mips_relax.sequence != 1) |
df58fc94 RS |
4390 | { |
4391 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
4392 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
4393 | mips_macro_warning.sizes[1] += insn_length (ip); | |
4394 | mips_macro_warning.insns[1]++; | |
4395 | } | |
584892a6 | 4396 | |
1e915849 RS |
4397 | if (mips_opts.mips16) |
4398 | { | |
4399 | ip->fixed_p = 1; | |
4400 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
4401 | } | |
4402 | add_fixed_insn (ip); | |
252b5132 RH |
4403 | } |
4404 | ||
9fe77896 | 4405 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 4406 | { |
df58fc94 | 4407 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 4408 | reloc_howto_type *howto0; |
9fe77896 RS |
4409 | reloc_howto_type *howto; |
4410 | int i; | |
34ce925e | 4411 | |
df58fc94 RS |
4412 | /* Perform any necessary conversion to microMIPS relocations |
4413 | and find out how many relocations there actually are. */ | |
4414 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
4415 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
4416 | ||
9fe77896 RS |
4417 | /* In a compound relocation, it is the final (outermost) |
4418 | operator that determines the relocated field. */ | |
2309ddf2 MR |
4419 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
4420 | ||
9fe77896 RS |
4421 | if (howto == NULL) |
4422 | { | |
4423 | /* To reproduce this failure try assembling gas/testsuites/ | |
4424 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
4425 | assembler. */ | |
df58fc94 RS |
4426 | as_bad (_("Unsupported MIPS relocation number %d"), |
4427 | final_type[i - 1]); | |
9fe77896 RS |
4428 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); |
4429 | } | |
2309ddf2 MR |
4430 | |
4431 | if (i > 1) | |
4432 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
4433 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
4434 | bfd_get_reloc_size (howto), | |
4435 | address_expr, | |
2309ddf2 MR |
4436 | howto0 && howto0->pc_relative, |
4437 | final_type[0]); | |
9fe77896 RS |
4438 | |
4439 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 4440 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
4441 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
4442 | ||
4443 | /* These relocations can have an addend that won't fit in | |
4444 | 4 octets for 64bit assembly. */ | |
4445 | if (HAVE_64BIT_GPRS | |
4446 | && ! howto->partial_inplace | |
4447 | && (reloc_type[0] == BFD_RELOC_16 | |
4448 | || reloc_type[0] == BFD_RELOC_32 | |
4449 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4450 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
4451 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
4452 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
4453 | || reloc_type[0] == BFD_RELOC_64 | |
4454 | || reloc_type[0] == BFD_RELOC_CTOR | |
4455 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
4456 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
4457 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
4458 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
4459 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
4460 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
4461 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
4462 | || hi16_reloc_p (reloc_type[0]) | |
4463 | || lo16_reloc_p (reloc_type[0]))) | |
4464 | ip->fixp[0]->fx_no_overflow = 1; | |
4465 | ||
ddaf2c41 MR |
4466 | /* These relocations can have an addend that won't fit in 2 octets. */ |
4467 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
4468 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
4469 | ip->fixp[0]->fx_no_overflow = 1; | |
4470 | ||
9fe77896 RS |
4471 | if (mips_relax.sequence) |
4472 | { | |
4473 | if (mips_relax.first_fixup == 0) | |
4474 | mips_relax.first_fixup = ip->fixp[0]; | |
4475 | } | |
4476 | else if (reloc_needs_lo_p (*reloc_type)) | |
4477 | { | |
4478 | struct mips_hi_fixup *hi_fixup; | |
4479 | ||
4480 | /* Reuse the last entry if it already has a matching %lo. */ | |
4481 | hi_fixup = mips_hi_fixup_list; | |
4482 | if (hi_fixup == 0 | |
4483 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 4484 | { |
9fe77896 RS |
4485 | hi_fixup = ((struct mips_hi_fixup *) |
4486 | xmalloc (sizeof (struct mips_hi_fixup))); | |
4487 | hi_fixup->next = mips_hi_fixup_list; | |
4488 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 4489 | } |
9fe77896 RS |
4490 | hi_fixup->fixp = ip->fixp[0]; |
4491 | hi_fixup->seg = now_seg; | |
4492 | } | |
252b5132 | 4493 | |
9fe77896 RS |
4494 | /* Add fixups for the second and third relocations, if given. |
4495 | Note that the ABI allows the second relocation to be | |
4496 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
4497 | moment we only use RSS_UNDEF, but we could add support | |
4498 | for the others if it ever becomes necessary. */ | |
4499 | for (i = 1; i < 3; i++) | |
4500 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
4501 | { | |
4502 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
4503 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 4504 | FALSE, final_type[i]); |
f6688943 | 4505 | |
9fe77896 RS |
4506 | /* Use fx_tcbit to mark compound relocs. */ |
4507 | ip->fixp[0]->fx_tcbit = 1; | |
4508 | ip->fixp[i]->fx_tcbit = 1; | |
4509 | } | |
252b5132 | 4510 | } |
1e915849 | 4511 | install_insn (ip); |
252b5132 RH |
4512 | |
4513 | /* Update the register mask information. */ | |
4c260379 RS |
4514 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
4515 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 4516 | |
a4e06468 | 4517 | switch (method) |
252b5132 | 4518 | { |
a4e06468 RS |
4519 | case APPEND_ADD: |
4520 | insert_into_history (0, 1, ip); | |
4521 | break; | |
4522 | ||
4523 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
4524 | { |
4525 | struct mips_cl_insn *nop; | |
4526 | ||
4527 | insert_into_history (0, 1, ip); | |
4528 | nop = get_delay_slot_nop (ip); | |
4529 | add_fixed_insn (nop); | |
4530 | insert_into_history (0, 1, nop); | |
4531 | if (mips_relax.sequence) | |
4532 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
4533 | } | |
a4e06468 RS |
4534 | break; |
4535 | ||
4536 | case APPEND_ADD_COMPACT: | |
4537 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
4538 | gas_assert (mips_opts.mips16); | |
4539 | ip->insn_opcode |= 0x0080; | |
4540 | find_altered_mips16_opcode (ip); | |
4541 | install_insn (ip); | |
4542 | insert_into_history (0, 1, ip); | |
4543 | break; | |
4544 | ||
4545 | case APPEND_SWAP: | |
4546 | { | |
4547 | struct mips_cl_insn delay = history[0]; | |
4548 | if (mips_opts.mips16) | |
4549 | { | |
4550 | know (delay.frag == ip->frag); | |
4551 | move_insn (ip, delay.frag, delay.where); | |
4552 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
4553 | } | |
464ab0e5 | 4554 | else if (relaxed_branch || delay.frag != ip->frag) |
a4e06468 RS |
4555 | { |
4556 | /* Add the delay slot instruction to the end of the | |
4557 | current frag and shrink the fixed part of the | |
4558 | original frag. If the branch occupies the tail of | |
4559 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 4560 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 4561 | if (delay.frag == ip->frag) |
2b0c8b40 | 4562 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
4563 | add_fixed_insn (&delay); |
4564 | } | |
4565 | else | |
4566 | { | |
2b0c8b40 MR |
4567 | move_insn (&delay, ip->frag, |
4568 | ip->where - branch_disp + insn_length (ip)); | |
a4e06468 RS |
4569 | move_insn (ip, history[0].frag, history[0].where); |
4570 | } | |
4571 | history[0] = *ip; | |
4572 | delay.fixed_p = 1; | |
4573 | insert_into_history (0, 1, &delay); | |
4574 | } | |
4575 | break; | |
252b5132 RH |
4576 | } |
4577 | ||
13408f1e | 4578 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
4579 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
4580 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
13408f1e RS |
4581 | mips_no_prev_insn (); |
4582 | ||
df58fc94 RS |
4583 | /* We need to emit a label at the end of branch-likely macros. */ |
4584 | if (emit_branch_likely_macro) | |
4585 | { | |
4586 | emit_branch_likely_macro = FALSE; | |
4587 | micromips_add_label (); | |
4588 | } | |
4589 | ||
252b5132 RH |
4590 | /* We just output an insn, so the next one doesn't have a label. */ |
4591 | mips_clear_insn_labels (); | |
252b5132 RH |
4592 | } |
4593 | ||
7d10b47d | 4594 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
4595 | |
4596 | static void | |
7d10b47d | 4597 | mips_no_prev_insn (void) |
252b5132 | 4598 | { |
7d10b47d RS |
4599 | prev_nop_frag = NULL; |
4600 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
4601 | mips_clear_insn_labels (); |
4602 | } | |
4603 | ||
7d10b47d RS |
4604 | /* This function must be called before we emit something other than |
4605 | instructions. It is like mips_no_prev_insn except that it inserts | |
4606 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 4607 | |
7d10b47d RS |
4608 | void |
4609 | mips_emit_delays (void) | |
252b5132 RH |
4610 | { |
4611 | if (! mips_opts.noreorder) | |
4612 | { | |
932d1a1b | 4613 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
4614 | if (nops > 0) |
4615 | { | |
7d10b47d RS |
4616 | while (nops-- > 0) |
4617 | add_fixed_insn (NOP_INSN); | |
462427c4 | 4618 | mips_move_text_labels (); |
7d10b47d RS |
4619 | } |
4620 | } | |
4621 | mips_no_prev_insn (); | |
4622 | } | |
4623 | ||
4624 | /* Start a (possibly nested) noreorder block. */ | |
4625 | ||
4626 | static void | |
4627 | start_noreorder (void) | |
4628 | { | |
4629 | if (mips_opts.noreorder == 0) | |
4630 | { | |
4631 | unsigned int i; | |
4632 | int nops; | |
4633 | ||
4634 | /* None of the instructions before the .set noreorder can be moved. */ | |
4635 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
4636 | history[i].fixed_p = 1; | |
4637 | ||
4638 | /* Insert any nops that might be needed between the .set noreorder | |
4639 | block and the previous instructions. We will later remove any | |
4640 | nops that turn out not to be needed. */ | |
932d1a1b | 4641 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
4642 | if (nops > 0) |
4643 | { | |
4644 | if (mips_optimize != 0) | |
252b5132 RH |
4645 | { |
4646 | /* Record the frag which holds the nop instructions, so | |
4647 | that we can remove them if we don't need them. */ | |
df58fc94 | 4648 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
4649 | prev_nop_frag = frag_now; |
4650 | prev_nop_frag_holds = nops; | |
4651 | prev_nop_frag_required = 0; | |
4652 | prev_nop_frag_since = 0; | |
4653 | } | |
4654 | ||
4655 | for (; nops > 0; --nops) | |
1e915849 | 4656 | add_fixed_insn (NOP_INSN); |
252b5132 | 4657 | |
7d10b47d RS |
4658 | /* Move on to a new frag, so that it is safe to simply |
4659 | decrease the size of prev_nop_frag. */ | |
4660 | frag_wane (frag_now); | |
4661 | frag_new (0); | |
462427c4 | 4662 | mips_move_text_labels (); |
252b5132 | 4663 | } |
df58fc94 | 4664 | mips_mark_labels (); |
7d10b47d | 4665 | mips_clear_insn_labels (); |
252b5132 | 4666 | } |
7d10b47d RS |
4667 | mips_opts.noreorder++; |
4668 | mips_any_noreorder = 1; | |
4669 | } | |
252b5132 | 4670 | |
7d10b47d | 4671 | /* End a nested noreorder block. */ |
252b5132 | 4672 | |
7d10b47d RS |
4673 | static void |
4674 | end_noreorder (void) | |
4675 | { | |
4676 | mips_opts.noreorder--; | |
4677 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
4678 | { | |
4679 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
4680 | handling nop insertion the .set reorder way. */ | |
4681 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 4682 | * NOP_INSN_SIZE); |
7d10b47d RS |
4683 | insert_into_history (prev_nop_frag_since, |
4684 | prev_nop_frag_required, NOP_INSN); | |
4685 | prev_nop_frag = NULL; | |
4686 | } | |
252b5132 RH |
4687 | } |
4688 | ||
584892a6 RS |
4689 | /* Set up global variables for the start of a new macro. */ |
4690 | ||
4691 | static void | |
4692 | macro_start (void) | |
4693 | { | |
4694 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
4695 | memset (&mips_macro_warning.first_insn_sizes, 0, |
4696 | sizeof (mips_macro_warning.first_insn_sizes)); | |
4697 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 4698 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 4699 | && delayed_branch_p (&history[0])); |
df58fc94 RS |
4700 | switch (history[0].insn_mo->pinfo2 |
4701 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
4702 | { | |
4703 | case INSN2_BRANCH_DELAY_32BIT: | |
4704 | mips_macro_warning.delay_slot_length = 4; | |
4705 | break; | |
4706 | case INSN2_BRANCH_DELAY_16BIT: | |
4707 | mips_macro_warning.delay_slot_length = 2; | |
4708 | break; | |
4709 | default: | |
4710 | mips_macro_warning.delay_slot_length = 0; | |
4711 | break; | |
4712 | } | |
4713 | mips_macro_warning.first_frag = NULL; | |
584892a6 RS |
4714 | } |
4715 | ||
df58fc94 RS |
4716 | /* Given that a macro is longer than one instruction or of the wrong size, |
4717 | return the appropriate warning for it. Return null if no warning is | |
4718 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
4719 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
4720 | and RELAX_NOMACRO. */ | |
584892a6 RS |
4721 | |
4722 | static const char * | |
4723 | macro_warning (relax_substateT subtype) | |
4724 | { | |
4725 | if (subtype & RELAX_DELAY_SLOT) | |
4726 | return _("Macro instruction expanded into multiple instructions" | |
4727 | " in a branch delay slot"); | |
4728 | else if (subtype & RELAX_NOMACRO) | |
4729 | return _("Macro instruction expanded into multiple instructions"); | |
df58fc94 RS |
4730 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
4731 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
4732 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
4733 | ? _("Macro instruction expanded into a wrong size instruction" | |
4734 | " in a 16-bit branch delay slot") | |
4735 | : _("Macro instruction expanded into a wrong size instruction" | |
4736 | " in a 32-bit branch delay slot")); | |
584892a6 RS |
4737 | else |
4738 | return 0; | |
4739 | } | |
4740 | ||
4741 | /* Finish up a macro. Emit warnings as appropriate. */ | |
4742 | ||
4743 | static void | |
4744 | macro_end (void) | |
4745 | { | |
df58fc94 RS |
4746 | /* Relaxation warning flags. */ |
4747 | relax_substateT subtype = 0; | |
4748 | ||
4749 | /* Check delay slot size requirements. */ | |
4750 | if (mips_macro_warning.delay_slot_length == 2) | |
4751 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
4752 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 4753 | { |
df58fc94 RS |
4754 | if (mips_macro_warning.delay_slot_length |
4755 | != mips_macro_warning.first_insn_sizes[0]) | |
4756 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
4757 | if (mips_macro_warning.delay_slot_length | |
4758 | != mips_macro_warning.first_insn_sizes[1]) | |
4759 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
4760 | } | |
584892a6 | 4761 | |
df58fc94 RS |
4762 | /* Check instruction count requirements. */ |
4763 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
4764 | { | |
4765 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
4766 | subtype |= RELAX_SECOND_LONGER; |
4767 | if (mips_opts.warn_about_macros) | |
4768 | subtype |= RELAX_NOMACRO; | |
4769 | if (mips_macro_warning.delay_slot_p) | |
4770 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 4771 | } |
584892a6 | 4772 | |
df58fc94 RS |
4773 | /* If both alternatives fail to fill a delay slot correctly, |
4774 | emit the warning now. */ | |
4775 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
4776 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
4777 | { | |
4778 | relax_substateT s; | |
4779 | const char *msg; | |
4780 | ||
4781 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
4782 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
4783 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
4784 | msg = macro_warning (s); | |
4785 | if (msg != NULL) | |
4786 | as_warn ("%s", msg); | |
4787 | subtype &= ~s; | |
4788 | } | |
4789 | ||
4790 | /* If both implementations are longer than 1 instruction, then emit the | |
4791 | warning now. */ | |
4792 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
4793 | { | |
4794 | relax_substateT s; | |
4795 | const char *msg; | |
4796 | ||
4797 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
4798 | msg = macro_warning (s); | |
4799 | if (msg != NULL) | |
4800 | as_warn ("%s", msg); | |
4801 | subtype &= ~s; | |
584892a6 | 4802 | } |
df58fc94 RS |
4803 | |
4804 | /* If any flags still set, then one implementation might need a warning | |
4805 | and the other either will need one of a different kind or none at all. | |
4806 | Pass any remaining flags over to relaxation. */ | |
4807 | if (mips_macro_warning.first_frag != NULL) | |
4808 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
4809 | } |
4810 | ||
df58fc94 RS |
4811 | /* Instruction operand formats used in macros that vary between |
4812 | standard MIPS and microMIPS code. */ | |
4813 | ||
4814 | static const char * const brk_fmt[2] = { "c", "mF" }; | |
4815 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; | |
4816 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
4817 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
4818 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
4819 | static const char * const mfhl_fmt[2] = { "d", "mj" }; | |
4820 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; | |
4821 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
4822 | ||
4823 | #define BRK_FMT (brk_fmt[mips_opts.micromips]) | |
4824 | #define COP12_FMT (cop12_fmt[mips_opts.micromips]) | |
4825 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) | |
4826 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
4827 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
4828 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips]) | |
4829 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) | |
4830 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
4831 | ||
6e1304d8 RS |
4832 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
4833 | The first argument in *ARGS will be either the code for a single | |
4834 | relocation or -1 followed by the three codes that make up a | |
4835 | composite relocation. */ | |
4836 | ||
4837 | static void | |
4838 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
4839 | { | |
4840 | int i, next; | |
4841 | ||
4842 | next = va_arg (*args, int); | |
4843 | if (next >= 0) | |
4844 | r[0] = (bfd_reloc_code_real_type) next; | |
4845 | else | |
4846 | for (i = 0; i < 3; i++) | |
4847 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
4848 | } | |
4849 | ||
252b5132 RH |
4850 | /* Build an instruction created by a macro expansion. This is passed |
4851 | a pointer to the count of instructions created so far, an | |
4852 | expression, the name of the instruction to build, an operand format | |
4853 | string, and corresponding arguments. */ | |
4854 | ||
252b5132 | 4855 | static void |
67c0d1eb | 4856 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 4857 | { |
df58fc94 | 4858 | const struct mips_opcode *mo = NULL; |
f6688943 | 4859 | bfd_reloc_code_real_type r[3]; |
df58fc94 RS |
4860 | const struct mips_opcode *amo; |
4861 | struct hash_control *hash; | |
4862 | struct mips_cl_insn insn; | |
252b5132 | 4863 | va_list args; |
252b5132 | 4864 | |
252b5132 | 4865 | va_start (args, fmt); |
252b5132 | 4866 | |
252b5132 RH |
4867 | if (mips_opts.mips16) |
4868 | { | |
03ea81db | 4869 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
4870 | va_end (args); |
4871 | return; | |
4872 | } | |
4873 | ||
f6688943 TS |
4874 | r[0] = BFD_RELOC_UNUSED; |
4875 | r[1] = BFD_RELOC_UNUSED; | |
4876 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
4877 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
4878 | amo = (struct mips_opcode *) hash_find (hash, name); | |
4879 | gas_assert (amo); | |
4880 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 4881 | |
df58fc94 | 4882 | do |
8b082fb1 TS |
4883 | { |
4884 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 RS |
4885 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
4886 | We try to match an instruction that fulfils the branch delay | |
4887 | slot instruction length requirement (if any) of the previous | |
4888 | instruction. While doing this we record the first instruction | |
4889 | seen that matches all the other conditions and use it anyway | |
4890 | if the requirement cannot be met; we will issue an appropriate | |
4891 | warning later on. */ | |
4892 | if (strcmp (fmt, amo->args) == 0 | |
4893 | && amo->pinfo != INSN_MACRO | |
4894 | && is_opcode_valid (amo) | |
4895 | && is_size_valid (amo)) | |
4896 | { | |
4897 | if (is_delay_slot_valid (amo)) | |
4898 | { | |
4899 | mo = amo; | |
4900 | break; | |
4901 | } | |
4902 | else if (!mo) | |
4903 | mo = amo; | |
4904 | } | |
8b082fb1 | 4905 | |
df58fc94 RS |
4906 | ++amo; |
4907 | gas_assert (amo->name); | |
252b5132 | 4908 | } |
df58fc94 | 4909 | while (strcmp (name, amo->name) == 0); |
252b5132 | 4910 | |
df58fc94 | 4911 | gas_assert (mo); |
1e915849 | 4912 | create_insn (&insn, mo); |
252b5132 RH |
4913 | for (;;) |
4914 | { | |
4915 | switch (*fmt++) | |
4916 | { | |
4917 | case '\0': | |
4918 | break; | |
4919 | ||
4920 | case ',': | |
4921 | case '(': | |
4922 | case ')': | |
4923 | continue; | |
4924 | ||
5f74bc13 CD |
4925 | case '+': |
4926 | switch (*fmt++) | |
4927 | { | |
4928 | case 'A': | |
4929 | case 'E': | |
df58fc94 RS |
4930 | INSERT_OPERAND (mips_opts.micromips, |
4931 | EXTLSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
4932 | continue; |
4933 | ||
4934 | case 'B': | |
4935 | case 'F': | |
4936 | /* Note that in the macro case, these arguments are already | |
4937 | in MSB form. (When handling the instruction in the | |
4938 | non-macro case, these arguments are sizes from which | |
4939 | MSB values must be calculated.) */ | |
df58fc94 RS |
4940 | INSERT_OPERAND (mips_opts.micromips, |
4941 | INSMSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
4942 | continue; |
4943 | ||
4944 | case 'C': | |
4945 | case 'G': | |
4946 | case 'H': | |
4947 | /* Note that in the macro case, these arguments are already | |
4948 | in MSBD form. (When handling the instruction in the | |
4949 | non-macro case, these arguments are sizes from which | |
4950 | MSBD values must be calculated.) */ | |
df58fc94 RS |
4951 | INSERT_OPERAND (mips_opts.micromips, |
4952 | EXTMSBD, insn, va_arg (args, int)); | |
5f74bc13 CD |
4953 | continue; |
4954 | ||
dd3cbb7e | 4955 | case 'Q': |
df58fc94 RS |
4956 | gas_assert (!mips_opts.micromips); |
4957 | INSERT_OPERAND (0, SEQI, insn, va_arg (args, int)); | |
dd3cbb7e NC |
4958 | continue; |
4959 | ||
5f74bc13 CD |
4960 | default: |
4961 | internalError (); | |
4962 | } | |
4963 | continue; | |
4964 | ||
8b082fb1 | 4965 | case '2': |
03f66e8a | 4966 | INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int)); |
8b082fb1 TS |
4967 | continue; |
4968 | ||
df58fc94 RS |
4969 | case 'n': |
4970 | gas_assert (mips_opts.micromips); | |
252b5132 RH |
4971 | case 't': |
4972 | case 'w': | |
4973 | case 'E': | |
df58fc94 | 4974 | INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int)); |
252b5132 RH |
4975 | continue; |
4976 | ||
4977 | case 'c': | |
df58fc94 RS |
4978 | gas_assert (!mips_opts.micromips); |
4979 | INSERT_OPERAND (0, CODE, insn, va_arg (args, int)); | |
38487616 TS |
4980 | continue; |
4981 | ||
252b5132 | 4982 | case 'W': |
df58fc94 RS |
4983 | gas_assert (!mips_opts.micromips); |
4984 | case 'T': | |
4985 | INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int)); | |
252b5132 RH |
4986 | continue; |
4987 | ||
252b5132 | 4988 | case 'G': |
df58fc94 RS |
4989 | if (mips_opts.micromips) |
4990 | INSERT_OPERAND (1, RS, insn, va_arg (args, int)); | |
4991 | else | |
4992 | INSERT_OPERAND (0, RD, insn, va_arg (args, int)); | |
4993 | continue; | |
4994 | ||
af7ee8bf | 4995 | case 'K': |
df58fc94 RS |
4996 | gas_assert (!mips_opts.micromips); |
4997 | case 'd': | |
4998 | INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int)); | |
252b5132 RH |
4999 | continue; |
5000 | ||
4372b673 | 5001 | case 'U': |
df58fc94 | 5002 | gas_assert (!mips_opts.micromips); |
4372b673 NC |
5003 | { |
5004 | int tmp = va_arg (args, int); | |
5005 | ||
df58fc94 RS |
5006 | INSERT_OPERAND (0, RT, insn, tmp); |
5007 | INSERT_OPERAND (0, RD, insn, tmp); | |
4372b673 | 5008 | } |
df58fc94 | 5009 | continue; |
4372b673 | 5010 | |
252b5132 RH |
5011 | case 'V': |
5012 | case 'S': | |
df58fc94 RS |
5013 | gas_assert (!mips_opts.micromips); |
5014 | INSERT_OPERAND (0, FS, insn, va_arg (args, int)); | |
252b5132 RH |
5015 | continue; |
5016 | ||
5017 | case 'z': | |
5018 | continue; | |
5019 | ||
5020 | case '<': | |
df58fc94 RS |
5021 | INSERT_OPERAND (mips_opts.micromips, |
5022 | SHAMT, insn, va_arg (args, int)); | |
252b5132 RH |
5023 | continue; |
5024 | ||
5025 | case 'D': | |
df58fc94 RS |
5026 | gas_assert (!mips_opts.micromips); |
5027 | INSERT_OPERAND (0, FD, insn, va_arg (args, int)); | |
252b5132 RH |
5028 | continue; |
5029 | ||
5030 | case 'B': | |
df58fc94 RS |
5031 | gas_assert (!mips_opts.micromips); |
5032 | INSERT_OPERAND (0, CODE20, insn, va_arg (args, int)); | |
252b5132 RH |
5033 | continue; |
5034 | ||
4372b673 | 5035 | case 'J': |
df58fc94 RS |
5036 | gas_assert (!mips_opts.micromips); |
5037 | INSERT_OPERAND (0, CODE19, insn, va_arg (args, int)); | |
4372b673 NC |
5038 | continue; |
5039 | ||
252b5132 | 5040 | case 'q': |
df58fc94 RS |
5041 | gas_assert (!mips_opts.micromips); |
5042 | INSERT_OPERAND (0, CODE2, insn, va_arg (args, int)); | |
252b5132 RH |
5043 | continue; |
5044 | ||
5045 | case 'b': | |
5046 | case 's': | |
5047 | case 'r': | |
5048 | case 'v': | |
df58fc94 | 5049 | INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int)); |
252b5132 RH |
5050 | continue; |
5051 | ||
5052 | case 'i': | |
5053 | case 'j': | |
6e1304d8 | 5054 | macro_read_relocs (&args, r); |
9c2799c2 | 5055 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
5056 | || *r == BFD_RELOC_MIPS_HIGHER |
5057 | || *r == BFD_RELOC_HI16_S | |
5058 | || *r == BFD_RELOC_LO16 | |
5059 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
5060 | continue; | |
5061 | ||
5062 | case 'o': | |
5063 | macro_read_relocs (&args, r); | |
252b5132 RH |
5064 | continue; |
5065 | ||
5066 | case 'u': | |
6e1304d8 | 5067 | macro_read_relocs (&args, r); |
9c2799c2 | 5068 | gas_assert (ep != NULL |
90ecf173 MR |
5069 | && (ep->X_op == O_constant |
5070 | || (ep->X_op == O_symbol | |
5071 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
5072 | || *r == BFD_RELOC_HI16_S | |
5073 | || *r == BFD_RELOC_HI16 | |
5074 | || *r == BFD_RELOC_GPREL16 | |
5075 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
5076 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
5077 | continue; |
5078 | ||
5079 | case 'p': | |
9c2799c2 | 5080 | gas_assert (ep != NULL); |
bad36eac | 5081 | |
252b5132 RH |
5082 | /* |
5083 | * This allows macro() to pass an immediate expression for | |
5084 | * creating short branches without creating a symbol. | |
bad36eac DJ |
5085 | * |
5086 | * We don't allow branch relaxation for these branches, as | |
5087 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
5088 | */ |
5089 | if (ep->X_op == O_constant) | |
5090 | { | |
df58fc94 RS |
5091 | /* For microMIPS we always use relocations for branches. |
5092 | So we should not resolve immediate values. */ | |
5093 | gas_assert (!mips_opts.micromips); | |
5094 | ||
bad36eac DJ |
5095 | if ((ep->X_add_number & 3) != 0) |
5096 | as_bad (_("branch to misaligned address (0x%lx)"), | |
5097 | (unsigned long) ep->X_add_number); | |
5098 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
5099 | as_bad (_("branch address range overflow (0x%lx)"), | |
5100 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
5101 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
5102 | ep = NULL; | |
5103 | } | |
5104 | else | |
0b25d3e6 | 5105 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
5106 | continue; |
5107 | ||
5108 | case 'a': | |
9c2799c2 | 5109 | gas_assert (ep != NULL); |
f6688943 | 5110 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
5111 | continue; |
5112 | ||
5113 | case 'C': | |
df58fc94 RS |
5114 | gas_assert (!mips_opts.micromips); |
5115 | INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long)); | |
252b5132 RH |
5116 | continue; |
5117 | ||
d43b4baf | 5118 | case 'k': |
df58fc94 RS |
5119 | INSERT_OPERAND (mips_opts.micromips, |
5120 | CACHE, insn, va_arg (args, unsigned long)); | |
5121 | continue; | |
5122 | ||
5123 | case '|': | |
5124 | gas_assert (mips_opts.micromips); | |
5125 | INSERT_OPERAND (1, TRAP, insn, va_arg (args, int)); | |
5126 | continue; | |
5127 | ||
5128 | case '.': | |
5129 | gas_assert (mips_opts.micromips); | |
5130 | INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int)); | |
5131 | continue; | |
5132 | ||
dec0624d MR |
5133 | case '\\': |
5134 | INSERT_OPERAND (mips_opts.micromips, | |
5135 | 3BITPOS, insn, va_arg (args, unsigned int)); | |
5136 | continue; | |
5137 | ||
df58fc94 | 5138 | case '~': |
dec0624d MR |
5139 | INSERT_OPERAND (mips_opts.micromips, |
5140 | OFFSET12, insn, va_arg (args, unsigned long)); | |
df58fc94 RS |
5141 | continue; |
5142 | ||
5143 | case 'N': | |
5144 | gas_assert (mips_opts.micromips); | |
5145 | INSERT_OPERAND (1, BCC, insn, va_arg (args, int)); | |
5146 | continue; | |
5147 | ||
5148 | case 'm': /* Opcode extension character. */ | |
5149 | gas_assert (mips_opts.micromips); | |
5150 | switch (*fmt++) | |
5151 | { | |
5152 | case 'j': | |
5153 | INSERT_OPERAND (1, MJ, insn, va_arg (args, int)); | |
5154 | break; | |
5155 | ||
5156 | case 'p': | |
5157 | INSERT_OPERAND (1, MP, insn, va_arg (args, int)); | |
5158 | break; | |
5159 | ||
5160 | case 'F': | |
5161 | INSERT_OPERAND (1, IMMF, insn, va_arg (args, int)); | |
5162 | break; | |
5163 | ||
5164 | default: | |
5165 | internalError (); | |
5166 | } | |
d43b4baf TS |
5167 | continue; |
5168 | ||
252b5132 RH |
5169 | default: |
5170 | internalError (); | |
5171 | } | |
5172 | break; | |
5173 | } | |
5174 | va_end (args); | |
9c2799c2 | 5175 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5176 | |
df58fc94 | 5177 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5178 | } |
5179 | ||
5180 | static void | |
67c0d1eb | 5181 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 5182 | va_list *args) |
252b5132 | 5183 | { |
1e915849 | 5184 | struct mips_opcode *mo; |
252b5132 | 5185 | struct mips_cl_insn insn; |
f6688943 TS |
5186 | bfd_reloc_code_real_type r[3] |
5187 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 5188 | |
1e915849 | 5189 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
5190 | gas_assert (mo); |
5191 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 5192 | |
1e915849 | 5193 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 5194 | { |
1e915849 | 5195 | ++mo; |
9c2799c2 NC |
5196 | gas_assert (mo->name); |
5197 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
5198 | } |
5199 | ||
1e915849 | 5200 | create_insn (&insn, mo); |
252b5132 RH |
5201 | for (;;) |
5202 | { | |
5203 | int c; | |
5204 | ||
5205 | c = *fmt++; | |
5206 | switch (c) | |
5207 | { | |
5208 | case '\0': | |
5209 | break; | |
5210 | ||
5211 | case ',': | |
5212 | case '(': | |
5213 | case ')': | |
5214 | continue; | |
5215 | ||
5216 | case 'y': | |
5217 | case 'w': | |
03ea81db | 5218 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
5219 | continue; |
5220 | ||
5221 | case 'x': | |
5222 | case 'v': | |
03ea81db | 5223 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
5224 | continue; |
5225 | ||
5226 | case 'z': | |
03ea81db | 5227 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
5228 | continue; |
5229 | ||
5230 | case 'Z': | |
03ea81db | 5231 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
5232 | continue; |
5233 | ||
5234 | case '0': | |
5235 | case 'S': | |
5236 | case 'P': | |
5237 | case 'R': | |
5238 | continue; | |
5239 | ||
5240 | case 'X': | |
03ea81db | 5241 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
5242 | continue; |
5243 | ||
5244 | case 'Y': | |
5245 | { | |
5246 | int regno; | |
5247 | ||
03ea81db | 5248 | regno = va_arg (*args, int); |
252b5132 | 5249 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 5250 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
5251 | } |
5252 | continue; | |
5253 | ||
5254 | case '<': | |
5255 | case '>': | |
5256 | case '4': | |
5257 | case '5': | |
5258 | case 'H': | |
5259 | case 'W': | |
5260 | case 'D': | |
5261 | case 'j': | |
5262 | case '8': | |
5263 | case 'V': | |
5264 | case 'C': | |
5265 | case 'U': | |
5266 | case 'k': | |
5267 | case 'K': | |
5268 | case 'p': | |
5269 | case 'q': | |
5270 | { | |
b886a2ab RS |
5271 | offsetT value; |
5272 | ||
9c2799c2 | 5273 | gas_assert (ep != NULL); |
252b5132 RH |
5274 | |
5275 | if (ep->X_op != O_constant) | |
874e8986 | 5276 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 5277 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 5278 | { |
b886a2ab | 5279 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 5280 | ep = NULL; |
f6688943 | 5281 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
5282 | } |
5283 | } | |
5284 | continue; | |
5285 | ||
5286 | case '6': | |
03ea81db | 5287 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
5288 | continue; |
5289 | } | |
5290 | ||
5291 | break; | |
5292 | } | |
5293 | ||
9c2799c2 | 5294 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5295 | |
df58fc94 | 5296 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5297 | } |
5298 | ||
2051e8c4 MR |
5299 | /* |
5300 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
5301 | * higher bits unset. | |
5302 | */ | |
9f872bbe | 5303 | static void |
2051e8c4 MR |
5304 | normalize_constant_expr (expressionS *ex) |
5305 | { | |
9ee2a2d4 | 5306 | if (ex->X_op == O_constant |
2051e8c4 MR |
5307 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
5308 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5309 | - 0x80000000); | |
5310 | } | |
5311 | ||
5312 | /* | |
5313 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
5314 | * all higher bits unset. | |
5315 | */ | |
5316 | static void | |
5317 | normalize_address_expr (expressionS *ex) | |
5318 | { | |
5319 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
5320 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
5321 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
5322 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5323 | - 0x80000000); | |
5324 | } | |
5325 | ||
438c16b8 TS |
5326 | /* |
5327 | * Generate a "jalr" instruction with a relocation hint to the called | |
5328 | * function. This occurs in NewABI PIC code. | |
5329 | */ | |
5330 | static void | |
df58fc94 | 5331 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 5332 | { |
df58fc94 RS |
5333 | static const bfd_reloc_code_real_type jalr_relocs[2] |
5334 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
5335 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
5336 | const char *jalr; | |
685736be | 5337 | char *f = NULL; |
b34976b6 | 5338 | |
1180b5a4 | 5339 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 5340 | { |
cc3d92a5 | 5341 | frag_grow (8); |
f21f8242 AO |
5342 | f = frag_more (0); |
5343 | } | |
2906b037 | 5344 | if (mips_opts.micromips) |
df58fc94 RS |
5345 | { |
5346 | jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs"; | |
e64af278 MR |
5347 | if (MIPS_JALR_HINT_P (ep) |
5348 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
5349 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
5350 | else | |
5351 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
5352 | } | |
2906b037 MR |
5353 | else |
5354 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 5355 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 5356 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
5357 | } |
5358 | ||
252b5132 RH |
5359 | /* |
5360 | * Generate a "lui" instruction. | |
5361 | */ | |
5362 | static void | |
67c0d1eb | 5363 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 5364 | { |
9c2799c2 | 5365 | gas_assert (! mips_opts.mips16); |
252b5132 | 5366 | |
df58fc94 | 5367 | if (ep->X_op != O_constant) |
252b5132 | 5368 | { |
9c2799c2 | 5369 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
5370 | /* _gp_disp is a special case, used from s_cpload. |
5371 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 5372 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 5373 | || (! HAVE_NEWABI |
aa6975fb ILT |
5374 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
5375 | || (! mips_in_shared | |
bbe506e8 TS |
5376 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
5377 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
5378 | } |
5379 | ||
df58fc94 | 5380 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
5381 | } |
5382 | ||
885add95 CD |
5383 | /* Generate a sequence of instructions to do a load or store from a constant |
5384 | offset off of a base register (breg) into/from a target register (treg), | |
5385 | using AT if necessary. */ | |
5386 | static void | |
67c0d1eb RS |
5387 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
5388 | int treg, int breg, int dbl) | |
885add95 | 5389 | { |
9c2799c2 | 5390 | gas_assert (ep->X_op == O_constant); |
885add95 | 5391 | |
256ab948 | 5392 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
5393 | if (!dbl) |
5394 | normalize_constant_expr (ep); | |
256ab948 | 5395 | |
67c1ffbe | 5396 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 5397 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
5398 | as_warn (_("operand overflow")); |
5399 | ||
5400 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
5401 | { | |
5402 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 5403 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
5404 | } |
5405 | else | |
5406 | { | |
5407 | /* 32-bit offset, need multiple instructions and AT, like: | |
5408 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
5409 | addu $tempreg,$tempreg,$breg | |
5410 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
5411 | to handle the complete offset. */ | |
67c0d1eb RS |
5412 | macro_build_lui (ep, AT); |
5413 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
5414 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 5415 | |
741fe287 | 5416 | if (!mips_opts.at) |
8fc2e39e | 5417 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
5418 | } |
5419 | } | |
5420 | ||
252b5132 RH |
5421 | /* set_at() |
5422 | * Generates code to set the $at register to true (one) | |
5423 | * if reg is less than the immediate expression. | |
5424 | */ | |
5425 | static void | |
67c0d1eb | 5426 | set_at (int reg, int unsignedp) |
252b5132 RH |
5427 | { |
5428 | if (imm_expr.X_op == O_constant | |
5429 | && imm_expr.X_add_number >= -0x8000 | |
5430 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
5431 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
5432 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
5433 | else |
5434 | { | |
67c0d1eb RS |
5435 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5436 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
5437 | } |
5438 | } | |
5439 | ||
5440 | /* Warn if an expression is not a constant. */ | |
5441 | ||
5442 | static void | |
17a2f251 | 5443 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
5444 | { |
5445 | if (ex->X_op == O_big) | |
5446 | as_bad (_("unsupported large constant")); | |
5447 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
5448 | as_bad (_("Instruction %s requires absolute expression"), |
5449 | ip->insn_mo->name); | |
13757d0c | 5450 | |
9ee2a2d4 MR |
5451 | if (HAVE_32BIT_GPRS) |
5452 | normalize_constant_expr (ex); | |
252b5132 RH |
5453 | } |
5454 | ||
5455 | /* Count the leading zeroes by performing a binary chop. This is a | |
5456 | bulky bit of source, but performance is a LOT better for the | |
5457 | majority of values than a simple loop to count the bits: | |
5458 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
5459 | if ((v) & (1 << (31 - lcnt))) | |
5460 | break; | |
5461 | However it is not code size friendly, and the gain will drop a bit | |
5462 | on certain cached systems. | |
5463 | */ | |
5464 | #define COUNT_TOP_ZEROES(v) \ | |
5465 | (((v) & ~0xffff) == 0 \ | |
5466 | ? ((v) & ~0xff) == 0 \ | |
5467 | ? ((v) & ~0xf) == 0 \ | |
5468 | ? ((v) & ~0x3) == 0 \ | |
5469 | ? ((v) & ~0x1) == 0 \ | |
5470 | ? !(v) \ | |
5471 | ? 32 \ | |
5472 | : 31 \ | |
5473 | : 30 \ | |
5474 | : ((v) & ~0x7) == 0 \ | |
5475 | ? 29 \ | |
5476 | : 28 \ | |
5477 | : ((v) & ~0x3f) == 0 \ | |
5478 | ? ((v) & ~0x1f) == 0 \ | |
5479 | ? 27 \ | |
5480 | : 26 \ | |
5481 | : ((v) & ~0x7f) == 0 \ | |
5482 | ? 25 \ | |
5483 | : 24 \ | |
5484 | : ((v) & ~0xfff) == 0 \ | |
5485 | ? ((v) & ~0x3ff) == 0 \ | |
5486 | ? ((v) & ~0x1ff) == 0 \ | |
5487 | ? 23 \ | |
5488 | : 22 \ | |
5489 | : ((v) & ~0x7ff) == 0 \ | |
5490 | ? 21 \ | |
5491 | : 20 \ | |
5492 | : ((v) & ~0x3fff) == 0 \ | |
5493 | ? ((v) & ~0x1fff) == 0 \ | |
5494 | ? 19 \ | |
5495 | : 18 \ | |
5496 | : ((v) & ~0x7fff) == 0 \ | |
5497 | ? 17 \ | |
5498 | : 16 \ | |
5499 | : ((v) & ~0xffffff) == 0 \ | |
5500 | ? ((v) & ~0xfffff) == 0 \ | |
5501 | ? ((v) & ~0x3ffff) == 0 \ | |
5502 | ? ((v) & ~0x1ffff) == 0 \ | |
5503 | ? 15 \ | |
5504 | : 14 \ | |
5505 | : ((v) & ~0x7ffff) == 0 \ | |
5506 | ? 13 \ | |
5507 | : 12 \ | |
5508 | : ((v) & ~0x3fffff) == 0 \ | |
5509 | ? ((v) & ~0x1fffff) == 0 \ | |
5510 | ? 11 \ | |
5511 | : 10 \ | |
5512 | : ((v) & ~0x7fffff) == 0 \ | |
5513 | ? 9 \ | |
5514 | : 8 \ | |
5515 | : ((v) & ~0xfffffff) == 0 \ | |
5516 | ? ((v) & ~0x3ffffff) == 0 \ | |
5517 | ? ((v) & ~0x1ffffff) == 0 \ | |
5518 | ? 7 \ | |
5519 | : 6 \ | |
5520 | : ((v) & ~0x7ffffff) == 0 \ | |
5521 | ? 5 \ | |
5522 | : 4 \ | |
5523 | : ((v) & ~0x3fffffff) == 0 \ | |
5524 | ? ((v) & ~0x1fffffff) == 0 \ | |
5525 | ? 3 \ | |
5526 | : 2 \ | |
5527 | : ((v) & ~0x7fffffff) == 0 \ | |
5528 | ? 1 \ | |
5529 | : 0) | |
5530 | ||
5531 | /* load_register() | |
67c1ffbe | 5532 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
5533 | * an absolute expression value into a register. |
5534 | */ | |
5535 | static void | |
67c0d1eb | 5536 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
5537 | { |
5538 | int freg; | |
5539 | expressionS hi32, lo32; | |
5540 | ||
5541 | if (ep->X_op != O_big) | |
5542 | { | |
9c2799c2 | 5543 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
5544 | |
5545 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
5546 | if (!dbl) |
5547 | normalize_constant_expr (ep); | |
256ab948 TS |
5548 | |
5549 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
5550 | { |
5551 | /* We can handle 16 bit signed values with an addiu to | |
5552 | $zero. No need to ever use daddiu here, since $zero and | |
5553 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 5554 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5555 | return; |
5556 | } | |
5557 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
5558 | { | |
5559 | /* We can handle 16 bit unsigned values with an ori to | |
5560 | $zero. */ | |
67c0d1eb | 5561 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5562 | return; |
5563 | } | |
256ab948 | 5564 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
5565 | { |
5566 | /* 32 bit values require an lui. */ | |
df58fc94 | 5567 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5568 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 5569 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
5570 | return; |
5571 | } | |
5572 | } | |
5573 | ||
5574 | /* The value is larger than 32 bits. */ | |
5575 | ||
2051e8c4 | 5576 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 5577 | { |
55e08f71 NC |
5578 | char value[32]; |
5579 | ||
5580 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 5581 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 5582 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5583 | return; |
5584 | } | |
5585 | ||
5586 | if (ep->X_op != O_big) | |
5587 | { | |
5588 | hi32 = *ep; | |
5589 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5590 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5591 | hi32.X_add_number &= 0xffffffff; | |
5592 | lo32 = *ep; | |
5593 | lo32.X_add_number &= 0xffffffff; | |
5594 | } | |
5595 | else | |
5596 | { | |
9c2799c2 | 5597 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
5598 | if (ep->X_add_number == 3) |
5599 | generic_bignum[3] = 0; | |
5600 | else if (ep->X_add_number > 4) | |
5601 | as_bad (_("Number larger than 64 bits")); | |
5602 | lo32.X_op = O_constant; | |
5603 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
5604 | hi32.X_op = O_constant; | |
5605 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
5606 | } | |
5607 | ||
5608 | if (hi32.X_add_number == 0) | |
5609 | freg = 0; | |
5610 | else | |
5611 | { | |
5612 | int shift, bit; | |
5613 | unsigned long hi, lo; | |
5614 | ||
956cd1d6 | 5615 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
5616 | { |
5617 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
5618 | { | |
67c0d1eb | 5619 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5620 | return; |
5621 | } | |
5622 | if (lo32.X_add_number & 0x80000000) | |
5623 | { | |
df58fc94 | 5624 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5625 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 5626 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
5627 | return; |
5628 | } | |
5629 | } | |
252b5132 RH |
5630 | |
5631 | /* Check for 16bit shifted constant. We know that hi32 is | |
5632 | non-zero, so start the mask on the first bit of the hi32 | |
5633 | value. */ | |
5634 | shift = 17; | |
5635 | do | |
beae10d5 KH |
5636 | { |
5637 | unsigned long himask, lomask; | |
5638 | ||
5639 | if (shift < 32) | |
5640 | { | |
5641 | himask = 0xffff >> (32 - shift); | |
5642 | lomask = (0xffff << shift) & 0xffffffff; | |
5643 | } | |
5644 | else | |
5645 | { | |
5646 | himask = 0xffff << (shift - 32); | |
5647 | lomask = 0; | |
5648 | } | |
5649 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
5650 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
5651 | { | |
5652 | expressionS tmp; | |
5653 | ||
5654 | tmp.X_op = O_constant; | |
5655 | if (shift < 32) | |
5656 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
5657 | | (lo32.X_add_number >> shift)); | |
5658 | else | |
5659 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 5660 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 5661 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5662 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5663 | return; |
5664 | } | |
f9419b05 | 5665 | ++shift; |
beae10d5 KH |
5666 | } |
5667 | while (shift <= (64 - 16)); | |
252b5132 RH |
5668 | |
5669 | /* Find the bit number of the lowest one bit, and store the | |
5670 | shifted value in hi/lo. */ | |
5671 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
5672 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
5673 | if (lo != 0) | |
5674 | { | |
5675 | bit = 0; | |
5676 | while ((lo & 1) == 0) | |
5677 | { | |
5678 | lo >>= 1; | |
5679 | ++bit; | |
5680 | } | |
5681 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
5682 | hi >>= bit; | |
5683 | } | |
5684 | else | |
5685 | { | |
5686 | bit = 32; | |
5687 | while ((hi & 1) == 0) | |
5688 | { | |
5689 | hi >>= 1; | |
5690 | ++bit; | |
5691 | } | |
5692 | lo = hi; | |
5693 | hi = 0; | |
5694 | } | |
5695 | ||
5696 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
5697 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
5698 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
5699 | { |
5700 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 5701 | if (shift != 0) |
beae10d5 | 5702 | { |
252b5132 RH |
5703 | expressionS tmp; |
5704 | ||
5705 | /* This instruction will set the register to be all | |
5706 | ones. */ | |
beae10d5 KH |
5707 | tmp.X_op = O_constant; |
5708 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 5709 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5710 | if (bit != 0) |
5711 | { | |
5712 | bit += shift; | |
df58fc94 | 5713 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5714 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 5715 | } |
df58fc94 | 5716 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 5717 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5718 | return; |
5719 | } | |
5720 | } | |
252b5132 RH |
5721 | |
5722 | /* Sign extend hi32 before calling load_register, because we can | |
5723 | generally get better code when we load a sign extended value. */ | |
5724 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 5725 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 5726 | load_register (reg, &hi32, 0); |
252b5132 RH |
5727 | freg = reg; |
5728 | } | |
5729 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
5730 | { | |
5731 | if (freg != 0) | |
5732 | { | |
df58fc94 | 5733 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
5734 | freg = reg; |
5735 | } | |
5736 | } | |
5737 | else | |
5738 | { | |
5739 | expressionS mid16; | |
5740 | ||
956cd1d6 | 5741 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 5742 | { |
df58fc94 RS |
5743 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
5744 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
5745 | return; |
5746 | } | |
252b5132 RH |
5747 | |
5748 | if (freg != 0) | |
5749 | { | |
df58fc94 | 5750 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
5751 | freg = reg; |
5752 | } | |
5753 | mid16 = lo32; | |
5754 | mid16.X_add_number >>= 16; | |
67c0d1eb | 5755 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 5756 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
5757 | freg = reg; |
5758 | } | |
5759 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 5760 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
5761 | } |
5762 | ||
269137b2 TS |
5763 | static inline void |
5764 | load_delay_nop (void) | |
5765 | { | |
5766 | if (!gpr_interlocks) | |
5767 | macro_build (NULL, "nop", ""); | |
5768 | } | |
5769 | ||
252b5132 RH |
5770 | /* Load an address into a register. */ |
5771 | ||
5772 | static void | |
67c0d1eb | 5773 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 5774 | { |
252b5132 RH |
5775 | if (ep->X_op != O_constant |
5776 | && ep->X_op != O_symbol) | |
5777 | { | |
5778 | as_bad (_("expression too complex")); | |
5779 | ep->X_op = O_constant; | |
5780 | } | |
5781 | ||
5782 | if (ep->X_op == O_constant) | |
5783 | { | |
67c0d1eb | 5784 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5785 | return; |
5786 | } | |
5787 | ||
5788 | if (mips_pic == NO_PIC) | |
5789 | { | |
5790 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 5791 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5792 | Otherwise we want |
5793 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
5794 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 5795 | If we have an addend, we always use the latter form. |
76b3015f | 5796 | |
d6bc6245 TS |
5797 | With 64bit address space and a usable $at we want |
5798 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5799 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5800 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5801 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5802 | dsll32 $reg,0 | |
3a482fd5 | 5803 | daddu $reg,$reg,$at |
76b3015f | 5804 | |
c03099e6 | 5805 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
5806 | on superscalar processors. |
5807 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5808 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5809 | dsll $reg,16 | |
5810 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
5811 | dsll $reg,16 | |
5812 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
5813 | |
5814 | For GP relative symbols in 64bit address space we can use | |
5815 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5816 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 5817 | { |
6caf9ef4 TS |
5818 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
5819 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
5820 | { | |
5821 | relax_start (ep->X_add_symbol); | |
5822 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
5823 | mips_gp_register, BFD_RELOC_GPREL16); | |
5824 | relax_switch (); | |
5825 | } | |
d6bc6245 | 5826 | |
741fe287 | 5827 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 5828 | { |
df58fc94 RS |
5829 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
5830 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
5831 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5832 | BFD_RELOC_MIPS_HIGHER); | |
5833 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 5834 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 5835 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
5836 | *used_at = 1; |
5837 | } | |
5838 | else | |
5839 | { | |
df58fc94 | 5840 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
5841 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5842 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 5843 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5844 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 5845 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5846 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 5847 | } |
6caf9ef4 TS |
5848 | |
5849 | if (mips_relax.sequence) | |
5850 | relax_end (); | |
d6bc6245 | 5851 | } |
252b5132 RH |
5852 | else |
5853 | { | |
d6bc6245 | 5854 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5855 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 5856 | { |
4d7206a2 | 5857 | relax_start (ep->X_add_symbol); |
67c0d1eb | 5858 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 5859 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 5860 | relax_switch (); |
d6bc6245 | 5861 | } |
67c0d1eb RS |
5862 | macro_build_lui (ep, reg); |
5863 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
5864 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5865 | if (mips_relax.sequence) |
5866 | relax_end (); | |
d6bc6245 | 5867 | } |
252b5132 | 5868 | } |
0a44bf69 | 5869 | else if (!mips_big_got) |
252b5132 RH |
5870 | { |
5871 | expressionS ex; | |
5872 | ||
5873 | /* If this is a reference to an external symbol, we want | |
5874 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5875 | Otherwise we want | |
5876 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5877 | nop | |
5878 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
5879 | If there is a constant, it must be added in after. |
5880 | ||
ed6fb7bd | 5881 | If we have NewABI, we want |
f5040a92 AO |
5882 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
5883 | unless we're referencing a global symbol with a non-zero | |
5884 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
5885 | if (HAVE_NEWABI) |
5886 | { | |
f5040a92 AO |
5887 | if (ep->X_add_number) |
5888 | { | |
4d7206a2 | 5889 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 5890 | ep->X_add_number = 0; |
4d7206a2 | 5891 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
5892 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
5893 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5894 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
5895 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5896 | ex.X_op = O_constant; | |
67c0d1eb | 5897 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5898 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 5899 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 5900 | relax_switch (); |
f5040a92 | 5901 | } |
67c0d1eb | 5902 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5903 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
5904 | if (mips_relax.sequence) |
5905 | relax_end (); | |
ed6fb7bd SC |
5906 | } |
5907 | else | |
5908 | { | |
f5040a92 AO |
5909 | ex.X_add_number = ep->X_add_number; |
5910 | ep->X_add_number = 0; | |
67c0d1eb RS |
5911 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
5912 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5913 | load_delay_nop (); |
4d7206a2 RS |
5914 | relax_start (ep->X_add_symbol); |
5915 | relax_switch (); | |
67c0d1eb | 5916 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 5917 | BFD_RELOC_LO16); |
4d7206a2 | 5918 | relax_end (); |
ed6fb7bd | 5919 | |
f5040a92 AO |
5920 | if (ex.X_add_number != 0) |
5921 | { | |
5922 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
5923 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5924 | ex.X_op = O_constant; | |
67c0d1eb | 5925 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5926 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 5927 | } |
252b5132 RH |
5928 | } |
5929 | } | |
0a44bf69 | 5930 | else if (mips_big_got) |
252b5132 RH |
5931 | { |
5932 | expressionS ex; | |
252b5132 RH |
5933 | |
5934 | /* This is the large GOT case. If this is a reference to an | |
5935 | external symbol, we want | |
5936 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5937 | addu $reg,$reg,$gp | |
5938 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
5939 | |
5940 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
5941 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
5942 | nop | |
5943 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 5944 | If there is a constant, it must be added in after. |
f5040a92 AO |
5945 | |
5946 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
5947 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
5948 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 5949 | */ |
438c16b8 TS |
5950 | if (HAVE_NEWABI) |
5951 | { | |
4d7206a2 | 5952 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 5953 | ep->X_add_number = 0; |
4d7206a2 | 5954 | relax_start (ep->X_add_symbol); |
df58fc94 | 5955 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
5956 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5957 | reg, reg, mips_gp_register); | |
5958 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
5959 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
5960 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
5961 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5962 | else if (ex.X_add_number) | |
5963 | { | |
5964 | ex.X_op = O_constant; | |
67c0d1eb RS |
5965 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
5966 | BFD_RELOC_LO16); | |
f5040a92 AO |
5967 | } |
5968 | ||
5969 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 5970 | relax_switch (); |
67c0d1eb | 5971 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5972 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
5973 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
5974 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 5975 | relax_end (); |
438c16b8 | 5976 | } |
252b5132 | 5977 | else |
438c16b8 | 5978 | { |
f5040a92 AO |
5979 | ex.X_add_number = ep->X_add_number; |
5980 | ep->X_add_number = 0; | |
4d7206a2 | 5981 | relax_start (ep->X_add_symbol); |
df58fc94 | 5982 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
5983 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5984 | reg, reg, mips_gp_register); | |
5985 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
5986 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
5987 | relax_switch (); |
5988 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
5989 | { |
5990 | /* We need a nop before loading from $gp. This special | |
5991 | check is required because the lui which starts the main | |
5992 | instruction stream does not refer to $gp, and so will not | |
5993 | insert the nop which may be required. */ | |
67c0d1eb | 5994 | macro_build (NULL, "nop", ""); |
438c16b8 | 5995 | } |
67c0d1eb | 5996 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5997 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 5998 | load_delay_nop (); |
67c0d1eb | 5999 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 6000 | BFD_RELOC_LO16); |
4d7206a2 | 6001 | relax_end (); |
438c16b8 | 6002 | |
f5040a92 AO |
6003 | if (ex.X_add_number != 0) |
6004 | { | |
6005 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
6006 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6007 | ex.X_op = O_constant; | |
67c0d1eb RS |
6008 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6009 | BFD_RELOC_LO16); | |
f5040a92 | 6010 | } |
252b5132 RH |
6011 | } |
6012 | } | |
252b5132 RH |
6013 | else |
6014 | abort (); | |
8fc2e39e | 6015 | |
741fe287 | 6016 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 6017 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
6018 | } |
6019 | ||
ea1fb5dc RS |
6020 | /* Move the contents of register SOURCE into register DEST. */ |
6021 | ||
6022 | static void | |
67c0d1eb | 6023 | move_register (int dest, int source) |
ea1fb5dc | 6024 | { |
df58fc94 RS |
6025 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
6026 | instruction specifically requires a 32-bit one. */ | |
6027 | if (mips_opts.micromips | |
6028 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
7951ca42 | 6029 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 RS |
6030 | else |
6031 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", | |
6032 | dest, source, 0); | |
ea1fb5dc RS |
6033 | } |
6034 | ||
4d7206a2 | 6035 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
6036 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
6037 | The two alternatives are: | |
4d7206a2 RS |
6038 | |
6039 | Global symbol Local sybmol | |
6040 | ------------- ------------ | |
6041 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
6042 | ... ... | |
6043 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
6044 | ||
6045 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
6046 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
6047 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
6048 | |
6049 | static void | |
67c0d1eb | 6050 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6051 | { |
6052 | expressionS global; | |
6053 | ||
6054 | global = *local; | |
6055 | global.X_add_number = 0; | |
6056 | ||
6057 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
6058 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6059 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 6060 | relax_switch (); |
67c0d1eb RS |
6061 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6062 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
6063 | relax_end (); |
6064 | } | |
6065 | ||
6066 | static void | |
67c0d1eb | 6067 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6068 | { |
6069 | expressionS global; | |
6070 | ||
6071 | global.X_op = O_constant; | |
6072 | global.X_op_symbol = NULL; | |
6073 | global.X_add_symbol = NULL; | |
6074 | global.X_add_number = local->X_add_number; | |
6075 | ||
6076 | relax_start (local->X_add_symbol); | |
67c0d1eb | 6077 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
6078 | dest, dest, BFD_RELOC_LO16); |
6079 | relax_switch (); | |
67c0d1eb | 6080 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
6081 | relax_end (); |
6082 | } | |
6083 | ||
f6a22291 MR |
6084 | static void |
6085 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
6086 | { | |
6087 | expressionS global; | |
6088 | int hold_mips_optimize; | |
6089 | ||
6090 | global.X_op = O_constant; | |
6091 | global.X_op_symbol = NULL; | |
6092 | global.X_add_symbol = NULL; | |
6093 | global.X_add_number = local->X_add_number; | |
6094 | ||
6095 | relax_start (local->X_add_symbol); | |
6096 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
6097 | relax_switch (); | |
6098 | /* Set mips_optimize around the lui instruction to avoid | |
6099 | inserting an unnecessary nop after the lw. */ | |
6100 | hold_mips_optimize = mips_optimize; | |
6101 | mips_optimize = 2; | |
6102 | macro_build_lui (&global, tmp); | |
6103 | mips_optimize = hold_mips_optimize; | |
6104 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
6105 | relax_end (); | |
6106 | ||
6107 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
6108 | } | |
6109 | ||
df58fc94 RS |
6110 | /* Emit a sequence of instructions to emulate a branch likely operation. |
6111 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
6112 | is its complementing branch with the original condition negated. | |
6113 | CALL is set if the original branch specified the link operation. | |
6114 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
6115 | ||
6116 | Code like this is produced in the noreorder mode: | |
6117 | ||
6118 | BRNEG <args>, 1f | |
6119 | nop | |
6120 | b <sym> | |
6121 | delay slot (executed only if branch taken) | |
6122 | 1: | |
6123 | ||
6124 | or, if CALL is set: | |
6125 | ||
6126 | BRNEG <args>, 1f | |
6127 | nop | |
6128 | bal <sym> | |
6129 | delay slot (executed only if branch taken) | |
6130 | 1: | |
6131 | ||
6132 | In the reorder mode the delay slot would be filled with a nop anyway, | |
6133 | so code produced is simply: | |
6134 | ||
6135 | BR <args>, <sym> | |
6136 | nop | |
6137 | ||
6138 | This function is used when producing code for the microMIPS ASE that | |
6139 | does not implement branch likely instructions in hardware. */ | |
6140 | ||
6141 | static void | |
6142 | macro_build_branch_likely (const char *br, const char *brneg, | |
6143 | int call, expressionS *ep, const char *fmt, | |
6144 | unsigned int sreg, unsigned int treg) | |
6145 | { | |
6146 | int noreorder = mips_opts.noreorder; | |
6147 | expressionS expr1; | |
6148 | ||
6149 | gas_assert (mips_opts.micromips); | |
6150 | start_noreorder (); | |
6151 | if (noreorder) | |
6152 | { | |
6153 | micromips_label_expr (&expr1); | |
6154 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
6155 | macro_build (NULL, "nop", ""); | |
6156 | macro_build (ep, call ? "bal" : "b", "p"); | |
6157 | ||
6158 | /* Set to true so that append_insn adds a label. */ | |
6159 | emit_branch_likely_macro = TRUE; | |
6160 | } | |
6161 | else | |
6162 | { | |
6163 | macro_build (ep, br, fmt, sreg, treg); | |
6164 | macro_build (NULL, "nop", ""); | |
6165 | } | |
6166 | end_noreorder (); | |
6167 | } | |
6168 | ||
6169 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
6170 | the condition code tested. EP specifies the branch target. */ | |
6171 | ||
6172 | static void | |
6173 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
6174 | { | |
6175 | const int call = 0; | |
6176 | const char *brneg; | |
6177 | const char *br; | |
6178 | ||
6179 | switch (type) | |
6180 | { | |
6181 | case M_BC1FL: | |
6182 | br = "bc1f"; | |
6183 | brneg = "bc1t"; | |
6184 | break; | |
6185 | case M_BC1TL: | |
6186 | br = "bc1t"; | |
6187 | brneg = "bc1f"; | |
6188 | break; | |
6189 | case M_BC2FL: | |
6190 | br = "bc2f"; | |
6191 | brneg = "bc2t"; | |
6192 | break; | |
6193 | case M_BC2TL: | |
6194 | br = "bc2t"; | |
6195 | brneg = "bc2f"; | |
6196 | break; | |
6197 | default: | |
6198 | abort (); | |
6199 | } | |
6200 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
6201 | } | |
6202 | ||
6203 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
6204 | the register tested. EP specifies the branch target. */ | |
6205 | ||
6206 | static void | |
6207 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
6208 | { | |
6209 | const char *brneg = NULL; | |
6210 | const char *br; | |
6211 | int call = 0; | |
6212 | ||
6213 | switch (type) | |
6214 | { | |
6215 | case M_BGEZ: | |
6216 | br = "bgez"; | |
6217 | break; | |
6218 | case M_BGEZL: | |
6219 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
6220 | brneg = "bltz"; | |
6221 | break; | |
6222 | case M_BGEZALL: | |
6223 | gas_assert (mips_opts.micromips); | |
6224 | br = "bgezals"; | |
6225 | brneg = "bltz"; | |
6226 | call = 1; | |
6227 | break; | |
6228 | case M_BGTZ: | |
6229 | br = "bgtz"; | |
6230 | break; | |
6231 | case M_BGTZL: | |
6232 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
6233 | brneg = "blez"; | |
6234 | break; | |
6235 | case M_BLEZ: | |
6236 | br = "blez"; | |
6237 | break; | |
6238 | case M_BLEZL: | |
6239 | br = mips_opts.micromips ? "blez" : "blezl"; | |
6240 | brneg = "bgtz"; | |
6241 | break; | |
6242 | case M_BLTZ: | |
6243 | br = "bltz"; | |
6244 | break; | |
6245 | case M_BLTZL: | |
6246 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
6247 | brneg = "bgez"; | |
6248 | break; | |
6249 | case M_BLTZALL: | |
6250 | gas_assert (mips_opts.micromips); | |
6251 | br = "bltzals"; | |
6252 | brneg = "bgez"; | |
6253 | call = 1; | |
6254 | break; | |
6255 | default: | |
6256 | abort (); | |
6257 | } | |
6258 | if (mips_opts.micromips && brneg) | |
6259 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
6260 | else | |
6261 | macro_build (ep, br, "s,p", sreg); | |
6262 | } | |
6263 | ||
6264 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
6265 | TREG as the registers tested. EP specifies the branch target. */ | |
6266 | ||
6267 | static void | |
6268 | macro_build_branch_rsrt (int type, expressionS *ep, | |
6269 | unsigned int sreg, unsigned int treg) | |
6270 | { | |
6271 | const char *brneg = NULL; | |
6272 | const int call = 0; | |
6273 | const char *br; | |
6274 | ||
6275 | switch (type) | |
6276 | { | |
6277 | case M_BEQ: | |
6278 | case M_BEQ_I: | |
6279 | br = "beq"; | |
6280 | break; | |
6281 | case M_BEQL: | |
6282 | case M_BEQL_I: | |
6283 | br = mips_opts.micromips ? "beq" : "beql"; | |
6284 | brneg = "bne"; | |
6285 | break; | |
6286 | case M_BNE: | |
6287 | case M_BNE_I: | |
6288 | br = "bne"; | |
6289 | break; | |
6290 | case M_BNEL: | |
6291 | case M_BNEL_I: | |
6292 | br = mips_opts.micromips ? "bne" : "bnel"; | |
6293 | brneg = "beq"; | |
6294 | break; | |
6295 | default: | |
6296 | abort (); | |
6297 | } | |
6298 | if (mips_opts.micromips && brneg) | |
6299 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
6300 | else | |
6301 | macro_build (ep, br, "s,t,p", sreg, treg); | |
6302 | } | |
6303 | ||
252b5132 RH |
6304 | /* |
6305 | * Build macros | |
6306 | * This routine implements the seemingly endless macro or synthesized | |
6307 | * instructions and addressing modes in the mips assembly language. Many | |
6308 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 6309 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
6310 | * this verbose method. Others are not simple macros but are more like |
6311 | * optimizing code generation. | |
6312 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 6313 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
6314 | * The ensuing load upper instructions are ommited. This implies some kind |
6315 | * of global optimization. We currently only optimize within a single macro. | |
6316 | * For many of the load and store macros if the address is specified as a | |
6317 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
6318 | * first load register 'at' with zero and use it as the base register. The | |
6319 | * mips assembler simply uses register $zero. Just one tiny optimization | |
6320 | * we're missing. | |
6321 | */ | |
6322 | static void | |
17a2f251 | 6323 | macro (struct mips_cl_insn *ip) |
252b5132 | 6324 | { |
741fe287 MR |
6325 | unsigned int treg, sreg, dreg, breg; |
6326 | unsigned int tempreg; | |
252b5132 | 6327 | int mask; |
43841e91 | 6328 | int used_at = 0; |
df58fc94 | 6329 | expressionS label_expr; |
252b5132 | 6330 | expressionS expr1; |
df58fc94 | 6331 | expressionS *ep; |
252b5132 RH |
6332 | const char *s; |
6333 | const char *s2; | |
6334 | const char *fmt; | |
6335 | int likely = 0; | |
252b5132 | 6336 | int coproc = 0; |
df58fc94 | 6337 | int off12 = 0; |
1abe91b1 | 6338 | int call = 0; |
df58fc94 RS |
6339 | int jals = 0; |
6340 | int dbl = 0; | |
6341 | int imm = 0; | |
6342 | int ust = 0; | |
6343 | int lp = 0; | |
6344 | int ab = 0; | |
dd6a37e7 | 6345 | int off0 = 0; |
252b5132 | 6346 | int off; |
67c0d1eb | 6347 | offsetT maxnum; |
252b5132 | 6348 | bfd_reloc_code_real_type r; |
252b5132 RH |
6349 | int hold_mips_optimize; |
6350 | ||
9c2799c2 | 6351 | gas_assert (! mips_opts.mips16); |
252b5132 | 6352 | |
df58fc94 RS |
6353 | treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
6354 | dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
6355 | sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
252b5132 RH |
6356 | mask = ip->insn_mo->mask; |
6357 | ||
df58fc94 RS |
6358 | label_expr.X_op = O_constant; |
6359 | label_expr.X_op_symbol = NULL; | |
6360 | label_expr.X_add_symbol = NULL; | |
6361 | label_expr.X_add_number = 0; | |
6362 | ||
252b5132 RH |
6363 | expr1.X_op = O_constant; |
6364 | expr1.X_op_symbol = NULL; | |
6365 | expr1.X_add_symbol = NULL; | |
6366 | expr1.X_add_number = 1; | |
6367 | ||
6368 | switch (mask) | |
6369 | { | |
6370 | case M_DABS: | |
6371 | dbl = 1; | |
6372 | case M_ABS: | |
df58fc94 RS |
6373 | /* bgez $a0,1f |
6374 | move v0,$a0 | |
6375 | sub v0,$zero,$a0 | |
6376 | 1: | |
6377 | */ | |
252b5132 | 6378 | |
7d10b47d | 6379 | start_noreorder (); |
252b5132 | 6380 | |
df58fc94 RS |
6381 | if (mips_opts.micromips) |
6382 | micromips_label_expr (&label_expr); | |
6383 | else | |
6384 | label_expr.X_add_number = 8; | |
6385 | macro_build (&label_expr, "bgez", "s,p", sreg); | |
252b5132 | 6386 | if (dreg == sreg) |
a605d2b3 | 6387 | macro_build (NULL, "nop", ""); |
252b5132 | 6388 | else |
67c0d1eb RS |
6389 | move_register (dreg, sreg); |
6390 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
df58fc94 RS |
6391 | if (mips_opts.micromips) |
6392 | micromips_add_label (); | |
252b5132 | 6393 | |
7d10b47d | 6394 | end_noreorder (); |
8fc2e39e | 6395 | break; |
252b5132 RH |
6396 | |
6397 | case M_ADD_I: | |
6398 | s = "addi"; | |
6399 | s2 = "add"; | |
6400 | goto do_addi; | |
6401 | case M_ADDU_I: | |
6402 | s = "addiu"; | |
6403 | s2 = "addu"; | |
6404 | goto do_addi; | |
6405 | case M_DADD_I: | |
6406 | dbl = 1; | |
6407 | s = "daddi"; | |
6408 | s2 = "dadd"; | |
df58fc94 RS |
6409 | if (!mips_opts.micromips) |
6410 | goto do_addi; | |
6411 | if (imm_expr.X_op == O_constant | |
6412 | && imm_expr.X_add_number >= -0x200 | |
6413 | && imm_expr.X_add_number < 0x200) | |
6414 | { | |
6415 | macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number); | |
6416 | break; | |
6417 | } | |
6418 | goto do_addi_i; | |
252b5132 RH |
6419 | case M_DADDU_I: |
6420 | dbl = 1; | |
6421 | s = "daddiu"; | |
6422 | s2 = "daddu"; | |
6423 | do_addi: | |
6424 | if (imm_expr.X_op == O_constant | |
6425 | && imm_expr.X_add_number >= -0x8000 | |
6426 | && imm_expr.X_add_number < 0x8000) | |
6427 | { | |
67c0d1eb | 6428 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 6429 | break; |
252b5132 | 6430 | } |
df58fc94 | 6431 | do_addi_i: |
8fc2e39e | 6432 | used_at = 1; |
67c0d1eb RS |
6433 | load_register (AT, &imm_expr, dbl); |
6434 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6435 | break; |
6436 | ||
6437 | case M_AND_I: | |
6438 | s = "andi"; | |
6439 | s2 = "and"; | |
6440 | goto do_bit; | |
6441 | case M_OR_I: | |
6442 | s = "ori"; | |
6443 | s2 = "or"; | |
6444 | goto do_bit; | |
6445 | case M_NOR_I: | |
6446 | s = ""; | |
6447 | s2 = "nor"; | |
6448 | goto do_bit; | |
6449 | case M_XOR_I: | |
6450 | s = "xori"; | |
6451 | s2 = "xor"; | |
6452 | do_bit: | |
6453 | if (imm_expr.X_op == O_constant | |
6454 | && imm_expr.X_add_number >= 0 | |
6455 | && imm_expr.X_add_number < 0x10000) | |
6456 | { | |
6457 | if (mask != M_NOR_I) | |
67c0d1eb | 6458 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
6459 | else |
6460 | { | |
67c0d1eb RS |
6461 | macro_build (&imm_expr, "ori", "t,r,i", |
6462 | treg, sreg, BFD_RELOC_LO16); | |
6463 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 6464 | } |
8fc2e39e | 6465 | break; |
252b5132 RH |
6466 | } |
6467 | ||
8fc2e39e | 6468 | used_at = 1; |
67c0d1eb RS |
6469 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
6470 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6471 | break; |
6472 | ||
8b082fb1 TS |
6473 | case M_BALIGN: |
6474 | switch (imm_expr.X_add_number) | |
6475 | { | |
6476 | case 0: | |
6477 | macro_build (NULL, "nop", ""); | |
6478 | break; | |
6479 | case 2: | |
6480 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
6481 | break; | |
03f66e8a MR |
6482 | case 1: |
6483 | case 3: | |
8b082fb1 | 6484 | macro_build (NULL, "balign", "t,s,2", treg, sreg, |
90ecf173 | 6485 | (int) imm_expr.X_add_number); |
8b082fb1 | 6486 | break; |
03f66e8a MR |
6487 | default: |
6488 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
6489 | (unsigned long) imm_expr.X_add_number); | |
6490 | break; | |
8b082fb1 TS |
6491 | } |
6492 | break; | |
6493 | ||
df58fc94 RS |
6494 | case M_BC1FL: |
6495 | case M_BC1TL: | |
6496 | case M_BC2FL: | |
6497 | case M_BC2TL: | |
6498 | gas_assert (mips_opts.micromips); | |
6499 | macro_build_branch_ccl (mask, &offset_expr, | |
6500 | EXTRACT_OPERAND (1, BCC, *ip)); | |
6501 | break; | |
6502 | ||
252b5132 | 6503 | case M_BEQ_I: |
252b5132 | 6504 | case M_BEQL_I: |
252b5132 | 6505 | case M_BNE_I: |
252b5132 | 6506 | case M_BNEL_I: |
252b5132 | 6507 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
df58fc94 RS |
6508 | treg = 0; |
6509 | else | |
252b5132 | 6510 | { |
df58fc94 RS |
6511 | treg = AT; |
6512 | used_at = 1; | |
6513 | load_register (treg, &imm_expr, HAVE_64BIT_GPRS); | |
252b5132 | 6514 | } |
df58fc94 RS |
6515 | /* Fall through. */ |
6516 | case M_BEQL: | |
6517 | case M_BNEL: | |
6518 | macro_build_branch_rsrt (mask, &offset_expr, sreg, treg); | |
252b5132 RH |
6519 | break; |
6520 | ||
6521 | case M_BGEL: | |
6522 | likely = 1; | |
6523 | case M_BGE: | |
6524 | if (treg == 0) | |
df58fc94 RS |
6525 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg); |
6526 | else if (sreg == 0) | |
6527 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg); | |
6528 | else | |
252b5132 | 6529 | { |
df58fc94 RS |
6530 | used_at = 1; |
6531 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6532 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6533 | &offset_expr, AT, ZERO); | |
252b5132 | 6534 | } |
df58fc94 RS |
6535 | break; |
6536 | ||
6537 | case M_BGEZL: | |
6538 | case M_BGEZALL: | |
6539 | case M_BGTZL: | |
6540 | case M_BLEZL: | |
6541 | case M_BLTZL: | |
6542 | case M_BLTZALL: | |
6543 | macro_build_branch_rs (mask, &offset_expr, sreg); | |
252b5132 RH |
6544 | break; |
6545 | ||
6546 | case M_BGTL_I: | |
6547 | likely = 1; | |
6548 | case M_BGT_I: | |
90ecf173 | 6549 | /* Check for > max integer. */ |
252b5132 | 6550 | maxnum = 0x7fffffff; |
ca4e0257 | 6551 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6552 | { |
6553 | maxnum <<= 16; | |
6554 | maxnum |= 0xffff; | |
6555 | maxnum <<= 16; | |
6556 | maxnum |= 0xffff; | |
6557 | } | |
6558 | if (imm_expr.X_op == O_constant | |
6559 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6560 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6561 | { |
6562 | do_false: | |
90ecf173 | 6563 | /* Result is always false. */ |
252b5132 | 6564 | if (! likely) |
a605d2b3 | 6565 | macro_build (NULL, "nop", ""); |
252b5132 | 6566 | else |
df58fc94 | 6567 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 6568 | break; |
252b5132 RH |
6569 | } |
6570 | if (imm_expr.X_op != O_constant) | |
6571 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6572 | ++imm_expr.X_add_number; |
252b5132 RH |
6573 | /* FALLTHROUGH */ |
6574 | case M_BGE_I: | |
6575 | case M_BGEL_I: | |
6576 | if (mask == M_BGEL_I) | |
6577 | likely = 1; | |
6578 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6579 | { | |
df58fc94 RS |
6580 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
6581 | &offset_expr, sreg); | |
8fc2e39e | 6582 | break; |
252b5132 RH |
6583 | } |
6584 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6585 | { | |
df58fc94 RS |
6586 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
6587 | &offset_expr, sreg); | |
8fc2e39e | 6588 | break; |
252b5132 RH |
6589 | } |
6590 | maxnum = 0x7fffffff; | |
ca4e0257 | 6591 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6592 | { |
6593 | maxnum <<= 16; | |
6594 | maxnum |= 0xffff; | |
6595 | maxnum <<= 16; | |
6596 | maxnum |= 0xffff; | |
6597 | } | |
6598 | maxnum = - maxnum - 1; | |
6599 | if (imm_expr.X_op == O_constant | |
6600 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 6601 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6602 | { |
6603 | do_true: | |
6604 | /* result is always true */ | |
6605 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 6606 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6607 | break; |
252b5132 | 6608 | } |
8fc2e39e | 6609 | used_at = 1; |
67c0d1eb | 6610 | set_at (sreg, 0); |
df58fc94 RS |
6611 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6612 | &offset_expr, AT, ZERO); | |
252b5132 RH |
6613 | break; |
6614 | ||
6615 | case M_BGEUL: | |
6616 | likely = 1; | |
6617 | case M_BGEU: | |
6618 | if (treg == 0) | |
6619 | goto do_true; | |
df58fc94 RS |
6620 | else if (sreg == 0) |
6621 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6622 | &offset_expr, ZERO, treg); | |
6623 | else | |
252b5132 | 6624 | { |
df58fc94 RS |
6625 | used_at = 1; |
6626 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6627 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6628 | &offset_expr, AT, ZERO); | |
252b5132 | 6629 | } |
252b5132 RH |
6630 | break; |
6631 | ||
6632 | case M_BGTUL_I: | |
6633 | likely = 1; | |
6634 | case M_BGTU_I: | |
6635 | if (sreg == 0 | |
ca4e0257 | 6636 | || (HAVE_32BIT_GPRS |
252b5132 | 6637 | && imm_expr.X_op == O_constant |
f01dc953 | 6638 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6639 | goto do_false; |
6640 | if (imm_expr.X_op != O_constant) | |
6641 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6642 | ++imm_expr.X_add_number; |
252b5132 RH |
6643 | /* FALLTHROUGH */ |
6644 | case M_BGEU_I: | |
6645 | case M_BGEUL_I: | |
6646 | if (mask == M_BGEUL_I) | |
6647 | likely = 1; | |
6648 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6649 | goto do_true; | |
df58fc94 RS |
6650 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6651 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6652 | &offset_expr, sreg, ZERO); | |
6653 | else | |
252b5132 | 6654 | { |
df58fc94 RS |
6655 | used_at = 1; |
6656 | set_at (sreg, 1); | |
6657 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6658 | &offset_expr, AT, ZERO); | |
252b5132 | 6659 | } |
252b5132 RH |
6660 | break; |
6661 | ||
6662 | case M_BGTL: | |
6663 | likely = 1; | |
6664 | case M_BGT: | |
6665 | if (treg == 0) | |
df58fc94 RS |
6666 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg); |
6667 | else if (sreg == 0) | |
6668 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg); | |
6669 | else | |
252b5132 | 6670 | { |
df58fc94 RS |
6671 | used_at = 1; |
6672 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6673 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6674 | &offset_expr, AT, ZERO); | |
252b5132 | 6675 | } |
252b5132 RH |
6676 | break; |
6677 | ||
6678 | case M_BGTUL: | |
6679 | likely = 1; | |
6680 | case M_BGTU: | |
6681 | if (treg == 0) | |
df58fc94 RS |
6682 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
6683 | &offset_expr, sreg, ZERO); | |
6684 | else if (sreg == 0) | |
6685 | goto do_false; | |
6686 | else | |
252b5132 | 6687 | { |
df58fc94 RS |
6688 | used_at = 1; |
6689 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6690 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6691 | &offset_expr, AT, ZERO); | |
252b5132 | 6692 | } |
252b5132 RH |
6693 | break; |
6694 | ||
6695 | case M_BLEL: | |
6696 | likely = 1; | |
6697 | case M_BLE: | |
6698 | if (treg == 0) | |
df58fc94 RS |
6699 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); |
6700 | else if (sreg == 0) | |
6701 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg); | |
6702 | else | |
252b5132 | 6703 | { |
df58fc94 RS |
6704 | used_at = 1; |
6705 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6706 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6707 | &offset_expr, AT, ZERO); | |
252b5132 | 6708 | } |
252b5132 RH |
6709 | break; |
6710 | ||
6711 | case M_BLEL_I: | |
6712 | likely = 1; | |
6713 | case M_BLE_I: | |
6714 | maxnum = 0x7fffffff; | |
ca4e0257 | 6715 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6716 | { |
6717 | maxnum <<= 16; | |
6718 | maxnum |= 0xffff; | |
6719 | maxnum <<= 16; | |
6720 | maxnum |= 0xffff; | |
6721 | } | |
6722 | if (imm_expr.X_op == O_constant | |
6723 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6724 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6725 | goto do_true; |
6726 | if (imm_expr.X_op != O_constant) | |
6727 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6728 | ++imm_expr.X_add_number; |
252b5132 RH |
6729 | /* FALLTHROUGH */ |
6730 | case M_BLT_I: | |
6731 | case M_BLTL_I: | |
6732 | if (mask == M_BLTL_I) | |
6733 | likely = 1; | |
6734 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
df58fc94 RS |
6735 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6736 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6737 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); | |
6738 | else | |
252b5132 | 6739 | { |
df58fc94 RS |
6740 | used_at = 1; |
6741 | set_at (sreg, 0); | |
6742 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6743 | &offset_expr, AT, ZERO); | |
252b5132 | 6744 | } |
252b5132 RH |
6745 | break; |
6746 | ||
6747 | case M_BLEUL: | |
6748 | likely = 1; | |
6749 | case M_BLEU: | |
6750 | if (treg == 0) | |
df58fc94 RS |
6751 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6752 | &offset_expr, sreg, ZERO); | |
6753 | else if (sreg == 0) | |
6754 | goto do_true; | |
6755 | else | |
252b5132 | 6756 | { |
df58fc94 RS |
6757 | used_at = 1; |
6758 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6759 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6760 | &offset_expr, AT, ZERO); | |
252b5132 | 6761 | } |
252b5132 RH |
6762 | break; |
6763 | ||
6764 | case M_BLEUL_I: | |
6765 | likely = 1; | |
6766 | case M_BLEU_I: | |
6767 | if (sreg == 0 | |
ca4e0257 | 6768 | || (HAVE_32BIT_GPRS |
252b5132 | 6769 | && imm_expr.X_op == O_constant |
f01dc953 | 6770 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6771 | goto do_true; |
6772 | if (imm_expr.X_op != O_constant) | |
6773 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6774 | ++imm_expr.X_add_number; |
252b5132 RH |
6775 | /* FALLTHROUGH */ |
6776 | case M_BLTU_I: | |
6777 | case M_BLTUL_I: | |
6778 | if (mask == M_BLTUL_I) | |
6779 | likely = 1; | |
6780 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6781 | goto do_false; | |
df58fc94 RS |
6782 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6783 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6784 | &offset_expr, sreg, ZERO); | |
6785 | else | |
252b5132 | 6786 | { |
df58fc94 RS |
6787 | used_at = 1; |
6788 | set_at (sreg, 1); | |
6789 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6790 | &offset_expr, AT, ZERO); | |
252b5132 | 6791 | } |
252b5132 RH |
6792 | break; |
6793 | ||
6794 | case M_BLTL: | |
6795 | likely = 1; | |
6796 | case M_BLT: | |
6797 | if (treg == 0) | |
df58fc94 RS |
6798 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6799 | else if (sreg == 0) | |
6800 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg); | |
6801 | else | |
252b5132 | 6802 | { |
df58fc94 RS |
6803 | used_at = 1; |
6804 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6805 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6806 | &offset_expr, AT, ZERO); | |
252b5132 | 6807 | } |
252b5132 RH |
6808 | break; |
6809 | ||
6810 | case M_BLTUL: | |
6811 | likely = 1; | |
6812 | case M_BLTU: | |
6813 | if (treg == 0) | |
6814 | goto do_false; | |
df58fc94 RS |
6815 | else if (sreg == 0) |
6816 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6817 | &offset_expr, ZERO, treg); | |
6818 | else | |
252b5132 | 6819 | { |
df58fc94 RS |
6820 | used_at = 1; |
6821 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6822 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6823 | &offset_expr, AT, ZERO); | |
252b5132 | 6824 | } |
252b5132 RH |
6825 | break; |
6826 | ||
5f74bc13 CD |
6827 | case M_DEXT: |
6828 | { | |
d5818fca MR |
6829 | /* Use unsigned arithmetic. */ |
6830 | addressT pos; | |
6831 | addressT size; | |
5f74bc13 | 6832 | |
90ecf173 | 6833 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6834 | { |
6835 | as_bad (_("Unsupported large constant")); | |
6836 | pos = size = 1; | |
6837 | } | |
6838 | else | |
6839 | { | |
d5818fca MR |
6840 | pos = imm_expr.X_add_number; |
6841 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
6842 | } |
6843 | ||
6844 | if (pos > 63) | |
6845 | { | |
d5818fca | 6846 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
6847 | pos = 1; |
6848 | } | |
90ecf173 | 6849 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
6850 | { |
6851 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 6852 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
6853 | size = 1; |
6854 | } | |
6855 | ||
6856 | if (size <= 32 && pos < 32) | |
6857 | { | |
6858 | s = "dext"; | |
6859 | fmt = "t,r,+A,+C"; | |
6860 | } | |
6861 | else if (size <= 32) | |
6862 | { | |
6863 | s = "dextu"; | |
6864 | fmt = "t,r,+E,+H"; | |
6865 | } | |
6866 | else | |
6867 | { | |
6868 | s = "dextm"; | |
6869 | fmt = "t,r,+A,+G"; | |
6870 | } | |
d5818fca MR |
6871 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
6872 | (int) (size - 1)); | |
5f74bc13 | 6873 | } |
8fc2e39e | 6874 | break; |
5f74bc13 CD |
6875 | |
6876 | case M_DINS: | |
6877 | { | |
d5818fca MR |
6878 | /* Use unsigned arithmetic. */ |
6879 | addressT pos; | |
6880 | addressT size; | |
5f74bc13 | 6881 | |
90ecf173 | 6882 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6883 | { |
6884 | as_bad (_("Unsupported large constant")); | |
6885 | pos = size = 1; | |
6886 | } | |
6887 | else | |
6888 | { | |
d5818fca MR |
6889 | pos = imm_expr.X_add_number; |
6890 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
6891 | } |
6892 | ||
6893 | if (pos > 63) | |
6894 | { | |
d5818fca | 6895 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
6896 | pos = 1; |
6897 | } | |
90ecf173 | 6898 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
6899 | { |
6900 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 6901 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
6902 | size = 1; |
6903 | } | |
6904 | ||
6905 | if (pos < 32 && (pos + size - 1) < 32) | |
6906 | { | |
6907 | s = "dins"; | |
6908 | fmt = "t,r,+A,+B"; | |
6909 | } | |
6910 | else if (pos >= 32) | |
6911 | { | |
6912 | s = "dinsu"; | |
6913 | fmt = "t,r,+E,+F"; | |
6914 | } | |
6915 | else | |
6916 | { | |
6917 | s = "dinsm"; | |
6918 | fmt = "t,r,+A,+F"; | |
6919 | } | |
750bdd57 AS |
6920 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
6921 | (int) (pos + size - 1)); | |
5f74bc13 | 6922 | } |
8fc2e39e | 6923 | break; |
5f74bc13 | 6924 | |
252b5132 RH |
6925 | case M_DDIV_3: |
6926 | dbl = 1; | |
6927 | case M_DIV_3: | |
6928 | s = "mflo"; | |
6929 | goto do_div3; | |
6930 | case M_DREM_3: | |
6931 | dbl = 1; | |
6932 | case M_REM_3: | |
6933 | s = "mfhi"; | |
6934 | do_div3: | |
6935 | if (treg == 0) | |
6936 | { | |
6937 | as_warn (_("Divide by zero.")); | |
6938 | if (mips_trap) | |
df58fc94 | 6939 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 6940 | else |
df58fc94 | 6941 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 6942 | break; |
252b5132 RH |
6943 | } |
6944 | ||
7d10b47d | 6945 | start_noreorder (); |
252b5132 RH |
6946 | if (mips_trap) |
6947 | { | |
df58fc94 | 6948 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 6949 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
6950 | } |
6951 | else | |
6952 | { | |
df58fc94 RS |
6953 | if (mips_opts.micromips) |
6954 | micromips_label_expr (&label_expr); | |
6955 | else | |
6956 | label_expr.X_add_number = 8; | |
6957 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 6958 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
df58fc94 RS |
6959 | macro_build (NULL, "break", BRK_FMT, 7); |
6960 | if (mips_opts.micromips) | |
6961 | micromips_add_label (); | |
252b5132 RH |
6962 | } |
6963 | expr1.X_add_number = -1; | |
8fc2e39e | 6964 | used_at = 1; |
f6a22291 | 6965 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
6966 | if (mips_opts.micromips) |
6967 | micromips_label_expr (&label_expr); | |
6968 | else | |
6969 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
6970 | macro_build (&label_expr, "bne", "s,t,p", treg, AT); | |
252b5132 RH |
6971 | if (dbl) |
6972 | { | |
6973 | expr1.X_add_number = 1; | |
f6a22291 | 6974 | load_register (AT, &expr1, dbl); |
df58fc94 | 6975 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
6976 | } |
6977 | else | |
6978 | { | |
6979 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 6980 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
6981 | } |
6982 | if (mips_trap) | |
6983 | { | |
df58fc94 | 6984 | macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6); |
252b5132 RH |
6985 | /* We want to close the noreorder block as soon as possible, so |
6986 | that later insns are available for delay slot filling. */ | |
7d10b47d | 6987 | end_noreorder (); |
252b5132 RH |
6988 | } |
6989 | else | |
6990 | { | |
df58fc94 RS |
6991 | if (mips_opts.micromips) |
6992 | micromips_label_expr (&label_expr); | |
6993 | else | |
6994 | label_expr.X_add_number = 8; | |
6995 | macro_build (&label_expr, "bne", "s,t,p", sreg, AT); | |
a605d2b3 | 6996 | macro_build (NULL, "nop", ""); |
252b5132 RH |
6997 | |
6998 | /* We want to close the noreorder block as soon as possible, so | |
6999 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7000 | end_noreorder (); |
252b5132 | 7001 | |
df58fc94 | 7002 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 7003 | } |
df58fc94 RS |
7004 | if (mips_opts.micromips) |
7005 | micromips_add_label (); | |
7006 | macro_build (NULL, s, MFHL_FMT, dreg); | |
252b5132 RH |
7007 | break; |
7008 | ||
7009 | case M_DIV_3I: | |
7010 | s = "div"; | |
7011 | s2 = "mflo"; | |
7012 | goto do_divi; | |
7013 | case M_DIVU_3I: | |
7014 | s = "divu"; | |
7015 | s2 = "mflo"; | |
7016 | goto do_divi; | |
7017 | case M_REM_3I: | |
7018 | s = "div"; | |
7019 | s2 = "mfhi"; | |
7020 | goto do_divi; | |
7021 | case M_REMU_3I: | |
7022 | s = "divu"; | |
7023 | s2 = "mfhi"; | |
7024 | goto do_divi; | |
7025 | case M_DDIV_3I: | |
7026 | dbl = 1; | |
7027 | s = "ddiv"; | |
7028 | s2 = "mflo"; | |
7029 | goto do_divi; | |
7030 | case M_DDIVU_3I: | |
7031 | dbl = 1; | |
7032 | s = "ddivu"; | |
7033 | s2 = "mflo"; | |
7034 | goto do_divi; | |
7035 | case M_DREM_3I: | |
7036 | dbl = 1; | |
7037 | s = "ddiv"; | |
7038 | s2 = "mfhi"; | |
7039 | goto do_divi; | |
7040 | case M_DREMU_3I: | |
7041 | dbl = 1; | |
7042 | s = "ddivu"; | |
7043 | s2 = "mfhi"; | |
7044 | do_divi: | |
7045 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7046 | { | |
7047 | as_warn (_("Divide by zero.")); | |
7048 | if (mips_trap) | |
df58fc94 | 7049 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7050 | else |
df58fc94 | 7051 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7052 | break; |
252b5132 RH |
7053 | } |
7054 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
7055 | { | |
7056 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 7057 | move_register (dreg, sreg); |
252b5132 | 7058 | else |
c80c840e | 7059 | move_register (dreg, ZERO); |
8fc2e39e | 7060 | break; |
252b5132 RH |
7061 | } |
7062 | if (imm_expr.X_op == O_constant | |
7063 | && imm_expr.X_add_number == -1 | |
7064 | && s[strlen (s) - 1] != 'u') | |
7065 | { | |
7066 | if (strcmp (s2, "mflo") == 0) | |
7067 | { | |
67c0d1eb | 7068 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
7069 | } |
7070 | else | |
c80c840e | 7071 | move_register (dreg, ZERO); |
8fc2e39e | 7072 | break; |
252b5132 RH |
7073 | } |
7074 | ||
8fc2e39e | 7075 | used_at = 1; |
67c0d1eb RS |
7076 | load_register (AT, &imm_expr, dbl); |
7077 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
df58fc94 | 7078 | macro_build (NULL, s2, MFHL_FMT, dreg); |
252b5132 RH |
7079 | break; |
7080 | ||
7081 | case M_DIVU_3: | |
7082 | s = "divu"; | |
7083 | s2 = "mflo"; | |
7084 | goto do_divu3; | |
7085 | case M_REMU_3: | |
7086 | s = "divu"; | |
7087 | s2 = "mfhi"; | |
7088 | goto do_divu3; | |
7089 | case M_DDIVU_3: | |
7090 | s = "ddivu"; | |
7091 | s2 = "mflo"; | |
7092 | goto do_divu3; | |
7093 | case M_DREMU_3: | |
7094 | s = "ddivu"; | |
7095 | s2 = "mfhi"; | |
7096 | do_divu3: | |
7d10b47d | 7097 | start_noreorder (); |
252b5132 RH |
7098 | if (mips_trap) |
7099 | { | |
df58fc94 | 7100 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7101 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7102 | /* We want to close the noreorder block as soon as possible, so |
7103 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7104 | end_noreorder (); |
252b5132 RH |
7105 | } |
7106 | else | |
7107 | { | |
df58fc94 RS |
7108 | if (mips_opts.micromips) |
7109 | micromips_label_expr (&label_expr); | |
7110 | else | |
7111 | label_expr.X_add_number = 8; | |
7112 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7113 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7114 | |
7115 | /* We want to close the noreorder block as soon as possible, so | |
7116 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7117 | end_noreorder (); |
df58fc94 RS |
7118 | macro_build (NULL, "break", BRK_FMT, 7); |
7119 | if (mips_opts.micromips) | |
7120 | micromips_add_label (); | |
252b5132 | 7121 | } |
df58fc94 | 7122 | macro_build (NULL, s2, MFHL_FMT, dreg); |
8fc2e39e | 7123 | break; |
252b5132 | 7124 | |
1abe91b1 MR |
7125 | case M_DLCA_AB: |
7126 | dbl = 1; | |
7127 | case M_LCA_AB: | |
7128 | call = 1; | |
7129 | goto do_la; | |
252b5132 RH |
7130 | case M_DLA_AB: |
7131 | dbl = 1; | |
7132 | case M_LA_AB: | |
1abe91b1 | 7133 | do_la: |
252b5132 RH |
7134 | /* Load the address of a symbol into a register. If breg is not |
7135 | zero, we then add a base register to it. */ | |
7136 | ||
3bec30a8 TS |
7137 | if (dbl && HAVE_32BIT_GPRS) |
7138 | as_warn (_("dla used to load 32-bit register")); | |
7139 | ||
90ecf173 | 7140 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
7141 | as_warn (_("la used to load 64-bit address")); |
7142 | ||
0c11417f MR |
7143 | if (offset_expr.X_op == O_constant |
7144 | && offset_expr.X_add_number >= -0x8000 | |
7145 | && offset_expr.X_add_number < 0x8000) | |
7146 | { | |
aed1a261 | 7147 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 7148 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7149 | break; |
0c11417f MR |
7150 | } |
7151 | ||
741fe287 | 7152 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
7153 | { |
7154 | tempreg = AT; | |
7155 | used_at = 1; | |
7156 | } | |
7157 | else | |
7158 | { | |
7159 | tempreg = treg; | |
afdbd6d0 CD |
7160 | } |
7161 | ||
252b5132 RH |
7162 | if (offset_expr.X_op != O_symbol |
7163 | && offset_expr.X_op != O_constant) | |
7164 | { | |
f71d0d44 | 7165 | as_bad (_("Expression too complex")); |
252b5132 RH |
7166 | offset_expr.X_op = O_constant; |
7167 | } | |
7168 | ||
252b5132 | 7169 | if (offset_expr.X_op == O_constant) |
aed1a261 | 7170 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
7171 | else if (mips_pic == NO_PIC) |
7172 | { | |
d6bc6245 | 7173 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 7174 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
7175 | Otherwise we want |
7176 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7177 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7178 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 7179 | so we may as well always use the latter form. |
76b3015f | 7180 | |
6caf9ef4 TS |
7181 | With 64bit address space and a usable $at we want |
7182 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7183 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7184 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7185 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
7186 | dsll32 $tempreg,0 | |
7187 | daddu $tempreg,$tempreg,$at | |
7188 | ||
7189 | If $at is already in use, we use a path which is suboptimal | |
7190 | on superscalar processors. | |
7191 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7192 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7193 | dsll $tempreg,16 | |
7194 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7195 | dsll $tempreg,16 | |
7196 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
7197 | ||
7198 | For GP relative symbols in 64bit address space we can use | |
7199 | the same sequence as in 32bit address space. */ | |
aed1a261 | 7200 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 7201 | { |
6caf9ef4 TS |
7202 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
7203 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
7204 | { | |
7205 | relax_start (offset_expr.X_add_symbol); | |
7206 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7207 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
7208 | relax_switch (); | |
7209 | } | |
d6bc6245 | 7210 | |
741fe287 | 7211 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 7212 | { |
df58fc94 | 7213 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7214 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 7215 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7216 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 7217 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7218 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 7219 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7220 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 7221 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 7222 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
7223 | used_at = 1; |
7224 | } | |
7225 | else | |
7226 | { | |
df58fc94 | 7227 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7228 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 7229 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7230 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 7231 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7232 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7233 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 7234 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7235 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7236 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 7237 | } |
6caf9ef4 TS |
7238 | |
7239 | if (mips_relax.sequence) | |
7240 | relax_end (); | |
98d3f06f KH |
7241 | } |
7242 | else | |
7243 | { | |
7244 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7245 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 7246 | { |
4d7206a2 | 7247 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7248 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7249 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 7250 | relax_switch (); |
98d3f06f | 7251 | } |
6943caf0 | 7252 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 7253 | as_bad (_("Offset too large")); |
67c0d1eb RS |
7254 | macro_build_lui (&offset_expr, tempreg); |
7255 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7256 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
7257 | if (mips_relax.sequence) |
7258 | relax_end (); | |
98d3f06f | 7259 | } |
252b5132 | 7260 | } |
0a44bf69 | 7261 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 7262 | { |
9117d219 NC |
7263 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
7264 | ||
252b5132 RH |
7265 | /* If this is a reference to an external symbol, and there |
7266 | is no constant, we want | |
7267 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 7268 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 7269 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
7270 | For a local symbol, we want |
7271 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7272 | nop | |
7273 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7274 | ||
7275 | If we have a small constant, and this is a reference to | |
7276 | an external symbol, we want | |
7277 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7278 | nop | |
7279 | addiu $tempreg,$tempreg,<constant> | |
7280 | For a local symbol, we want the same instruction | |
7281 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
7282 | addiu instruction. | |
7283 | ||
7284 | If we have a large constant, and this is a reference to | |
7285 | an external symbol, we want | |
7286 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7287 | lui $at,<hiconstant> | |
7288 | addiu $at,$at,<loconstant> | |
7289 | addu $tempreg,$tempreg,$at | |
7290 | For a local symbol, we want the same instruction | |
7291 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 7292 | addiu instruction. |
ed6fb7bd SC |
7293 | */ |
7294 | ||
4d7206a2 | 7295 | if (offset_expr.X_add_number == 0) |
252b5132 | 7296 | { |
0a44bf69 RS |
7297 | if (mips_pic == SVR4_PIC |
7298 | && breg == 0 | |
7299 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
7300 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
7301 | ||
7302 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
7303 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7304 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 7305 | if (breg != 0) |
252b5132 RH |
7306 | { |
7307 | /* We're going to put in an addu instruction using | |
7308 | tempreg, so we may as well insert the nop right | |
7309 | now. */ | |
269137b2 | 7310 | load_delay_nop (); |
252b5132 | 7311 | } |
4d7206a2 | 7312 | relax_switch (); |
67c0d1eb RS |
7313 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7314 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7315 | load_delay_nop (); |
67c0d1eb RS |
7316 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7317 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 7318 | relax_end (); |
252b5132 RH |
7319 | /* FIXME: If breg == 0, and the next instruction uses |
7320 | $tempreg, then if this variant case is used an extra | |
7321 | nop will be generated. */ | |
7322 | } | |
4d7206a2 RS |
7323 | else if (offset_expr.X_add_number >= -0x8000 |
7324 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 7325 | { |
67c0d1eb | 7326 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 7327 | load_delay_nop (); |
67c0d1eb | 7328 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
7329 | } |
7330 | else | |
7331 | { | |
4d7206a2 RS |
7332 | expr1.X_add_number = offset_expr.X_add_number; |
7333 | offset_expr.X_add_number = | |
43c0598f | 7334 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 7335 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 7336 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
7337 | /* If we are going to add in a base register, and the |
7338 | target register and the base register are the same, | |
7339 | then we are using AT as a temporary register. Since | |
7340 | we want to load the constant into AT, we add our | |
7341 | current AT (from the global offset table) and the | |
7342 | register into the register now, and pretend we were | |
7343 | not using a base register. */ | |
67c0d1eb | 7344 | if (breg == treg) |
252b5132 | 7345 | { |
269137b2 | 7346 | load_delay_nop (); |
67c0d1eb | 7347 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7348 | treg, AT, breg); |
252b5132 RH |
7349 | breg = 0; |
7350 | tempreg = treg; | |
252b5132 | 7351 | } |
f6a22291 | 7352 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
7353 | used_at = 1; |
7354 | } | |
7355 | } | |
0a44bf69 | 7356 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 7357 | { |
67c0d1eb | 7358 | int add_breg_early = 0; |
f5040a92 AO |
7359 | |
7360 | /* If this is a reference to an external, and there is no | |
7361 | constant, or local symbol (*), with or without a | |
7362 | constant, we want | |
7363 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 7364 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7365 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
7366 | ||
7367 | If we have a small constant, and this is a reference to | |
7368 | an external symbol, we want | |
7369 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7370 | addiu $tempreg,$tempreg,<constant> | |
7371 | ||
7372 | If we have a large constant, and this is a reference to | |
7373 | an external symbol, we want | |
7374 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7375 | lui $at,<hiconstant> | |
7376 | addiu $at,$at,<loconstant> | |
7377 | addu $tempreg,$tempreg,$at | |
7378 | ||
7379 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
7380 | local symbols, even though it introduces an additional | |
7381 | instruction. */ | |
7382 | ||
f5040a92 AO |
7383 | if (offset_expr.X_add_number) |
7384 | { | |
4d7206a2 | 7385 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7386 | offset_expr.X_add_number = 0; |
7387 | ||
4d7206a2 | 7388 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7389 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7390 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7391 | |
7392 | if (expr1.X_add_number >= -0x8000 | |
7393 | && expr1.X_add_number < 0x8000) | |
7394 | { | |
67c0d1eb RS |
7395 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
7396 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 7397 | } |
ecd13cd3 | 7398 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7399 | { |
f5040a92 AO |
7400 | /* If we are going to add in a base register, and the |
7401 | target register and the base register are the same, | |
7402 | then we are using AT as a temporary register. Since | |
7403 | we want to load the constant into AT, we add our | |
7404 | current AT (from the global offset table) and the | |
7405 | register into the register now, and pretend we were | |
7406 | not using a base register. */ | |
7407 | if (breg != treg) | |
7408 | dreg = tempreg; | |
7409 | else | |
7410 | { | |
9c2799c2 | 7411 | gas_assert (tempreg == AT); |
67c0d1eb RS |
7412 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
7413 | treg, AT, breg); | |
f5040a92 | 7414 | dreg = treg; |
67c0d1eb | 7415 | add_breg_early = 1; |
f5040a92 AO |
7416 | } |
7417 | ||
f6a22291 | 7418 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7419 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7420 | dreg, dreg, AT); |
f5040a92 | 7421 | |
f5040a92 AO |
7422 | used_at = 1; |
7423 | } | |
7424 | else | |
7425 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7426 | ||
4d7206a2 | 7427 | relax_switch (); |
f5040a92 AO |
7428 | offset_expr.X_add_number = expr1.X_add_number; |
7429 | ||
67c0d1eb RS |
7430 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7431 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
7432 | if (add_breg_early) | |
f5040a92 | 7433 | { |
67c0d1eb | 7434 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 7435 | treg, tempreg, breg); |
f5040a92 AO |
7436 | breg = 0; |
7437 | tempreg = treg; | |
7438 | } | |
4d7206a2 | 7439 | relax_end (); |
f5040a92 | 7440 | } |
4d7206a2 | 7441 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 7442 | { |
4d7206a2 | 7443 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7444 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7445 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 7446 | relax_switch (); |
67c0d1eb RS |
7447 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7448 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 7449 | relax_end (); |
f5040a92 | 7450 | } |
4d7206a2 | 7451 | else |
f5040a92 | 7452 | { |
67c0d1eb RS |
7453 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7454 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7455 | } |
7456 | } | |
0a44bf69 | 7457 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 7458 | { |
67c0d1eb | 7459 | int gpdelay; |
9117d219 NC |
7460 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7461 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 7462 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
7463 | |
7464 | /* This is the large GOT case. If this is a reference to an | |
7465 | external symbol, and there is no constant, we want | |
7466 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7467 | addu $tempreg,$tempreg,$gp | |
7468 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7469 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
7470 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7471 | addu $tempreg,$tempreg,$gp | |
7472 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
7473 | For a local symbol, we want |
7474 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7475 | nop | |
7476 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7477 | ||
7478 | If we have a small constant, and this is a reference to | |
7479 | an external symbol, we want | |
7480 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7481 | addu $tempreg,$tempreg,$gp | |
7482 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7483 | nop | |
7484 | addiu $tempreg,$tempreg,<constant> | |
7485 | For a local symbol, we want | |
7486 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7487 | nop | |
7488 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
7489 | ||
7490 | If we have a large constant, and this is a reference to | |
7491 | an external symbol, we want | |
7492 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7493 | addu $tempreg,$tempreg,$gp | |
7494 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7495 | lui $at,<hiconstant> | |
7496 | addiu $at,$at,<loconstant> | |
7497 | addu $tempreg,$tempreg,$at | |
7498 | For a local symbol, we want | |
7499 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7500 | lui $at,<hiconstant> | |
7501 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
7502 | addu $tempreg,$tempreg,$at | |
f5040a92 | 7503 | */ |
438c16b8 | 7504 | |
252b5132 RH |
7505 | expr1.X_add_number = offset_expr.X_add_number; |
7506 | offset_expr.X_add_number = 0; | |
4d7206a2 | 7507 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7508 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
7509 | if (expr1.X_add_number == 0 && breg == 0 |
7510 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
7511 | { |
7512 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7513 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7514 | } | |
df58fc94 | 7515 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7516 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7517 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 7518 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7519 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
7520 | if (expr1.X_add_number == 0) |
7521 | { | |
67c0d1eb | 7522 | if (breg != 0) |
252b5132 RH |
7523 | { |
7524 | /* We're going to put in an addu instruction using | |
7525 | tempreg, so we may as well insert the nop right | |
7526 | now. */ | |
269137b2 | 7527 | load_delay_nop (); |
252b5132 | 7528 | } |
252b5132 RH |
7529 | } |
7530 | else if (expr1.X_add_number >= -0x8000 | |
7531 | && expr1.X_add_number < 0x8000) | |
7532 | { | |
269137b2 | 7533 | load_delay_nop (); |
67c0d1eb | 7534 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7535 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
7536 | } |
7537 | else | |
7538 | { | |
252b5132 RH |
7539 | /* If we are going to add in a base register, and the |
7540 | target register and the base register are the same, | |
7541 | then we are using AT as a temporary register. Since | |
7542 | we want to load the constant into AT, we add our | |
7543 | current AT (from the global offset table) and the | |
7544 | register into the register now, and pretend we were | |
7545 | not using a base register. */ | |
7546 | if (breg != treg) | |
67c0d1eb | 7547 | dreg = tempreg; |
252b5132 RH |
7548 | else |
7549 | { | |
9c2799c2 | 7550 | gas_assert (tempreg == AT); |
269137b2 | 7551 | load_delay_nop (); |
67c0d1eb | 7552 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7553 | treg, AT, breg); |
252b5132 | 7554 | dreg = treg; |
252b5132 RH |
7555 | } |
7556 | ||
f6a22291 | 7557 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7558 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 7559 | |
252b5132 RH |
7560 | used_at = 1; |
7561 | } | |
43c0598f | 7562 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 7563 | relax_switch (); |
252b5132 | 7564 | |
67c0d1eb | 7565 | if (gpdelay) |
252b5132 RH |
7566 | { |
7567 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 7568 | the first instruction on the main stream does not. */ |
67c0d1eb | 7569 | macro_build (NULL, "nop", ""); |
252b5132 | 7570 | } |
ed6fb7bd | 7571 | |
67c0d1eb RS |
7572 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7573 | local_reloc_type, mips_gp_register); | |
f5040a92 | 7574 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
7575 | && expr1.X_add_number < 0x8000) |
7576 | { | |
269137b2 | 7577 | load_delay_nop (); |
67c0d1eb RS |
7578 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7579 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 7580 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
7581 | register, the external symbol case ended with a load, |
7582 | so if the symbol turns out to not be external, and | |
7583 | the next instruction uses tempreg, an unnecessary nop | |
7584 | will be inserted. */ | |
252b5132 RH |
7585 | } |
7586 | else | |
7587 | { | |
7588 | if (breg == treg) | |
7589 | { | |
7590 | /* We must add in the base register now, as in the | |
f5040a92 | 7591 | external symbol case. */ |
9c2799c2 | 7592 | gas_assert (tempreg == AT); |
269137b2 | 7593 | load_delay_nop (); |
67c0d1eb | 7594 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7595 | treg, AT, breg); |
252b5132 RH |
7596 | tempreg = treg; |
7597 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 7598 | it in in both cases. */ |
252b5132 RH |
7599 | breg = 0; |
7600 | } | |
7601 | ||
67c0d1eb RS |
7602 | macro_build_lui (&expr1, AT); |
7603 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 7604 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 7605 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7606 | tempreg, tempreg, AT); |
8fc2e39e | 7607 | used_at = 1; |
252b5132 | 7608 | } |
4d7206a2 | 7609 | relax_end (); |
252b5132 | 7610 | } |
0a44bf69 | 7611 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 7612 | { |
f5040a92 AO |
7613 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7614 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 7615 | int add_breg_early = 0; |
f5040a92 AO |
7616 | |
7617 | /* This is the large GOT case. If this is a reference to an | |
7618 | external symbol, and there is no constant, we want | |
7619 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7620 | add $tempreg,$tempreg,$gp | |
7621 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7622 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7623 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7624 | add $tempreg,$tempreg,$gp | |
7625 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
7626 | ||
7627 | If we have a small constant, and this is a reference to | |
7628 | an external symbol, we want | |
7629 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7630 | add $tempreg,$tempreg,$gp | |
7631 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7632 | addi $tempreg,$tempreg,<constant> | |
7633 | ||
7634 | If we have a large constant, and this is a reference to | |
7635 | an external symbol, we want | |
7636 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7637 | addu $tempreg,$tempreg,$gp | |
7638 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7639 | lui $at,<hiconstant> | |
7640 | addi $at,$at,<loconstant> | |
7641 | add $tempreg,$tempreg,$at | |
7642 | ||
7643 | If we have NewABI, and we know it's a local symbol, we want | |
7644 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
7645 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
7646 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
7647 | ||
4d7206a2 | 7648 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 7649 | |
4d7206a2 | 7650 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7651 | offset_expr.X_add_number = 0; |
7652 | ||
1abe91b1 MR |
7653 | if (expr1.X_add_number == 0 && breg == 0 |
7654 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
7655 | { |
7656 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7657 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7658 | } | |
df58fc94 | 7659 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7660 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7661 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
7662 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7663 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
7664 | |
7665 | if (expr1.X_add_number == 0) | |
4d7206a2 | 7666 | ; |
f5040a92 AO |
7667 | else if (expr1.X_add_number >= -0x8000 |
7668 | && expr1.X_add_number < 0x8000) | |
7669 | { | |
67c0d1eb | 7670 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7671 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 7672 | } |
ecd13cd3 | 7673 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7674 | { |
f5040a92 AO |
7675 | /* If we are going to add in a base register, and the |
7676 | target register and the base register are the same, | |
7677 | then we are using AT as a temporary register. Since | |
7678 | we want to load the constant into AT, we add our | |
7679 | current AT (from the global offset table) and the | |
7680 | register into the register now, and pretend we were | |
7681 | not using a base register. */ | |
7682 | if (breg != treg) | |
7683 | dreg = tempreg; | |
7684 | else | |
7685 | { | |
9c2799c2 | 7686 | gas_assert (tempreg == AT); |
67c0d1eb | 7687 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7688 | treg, AT, breg); |
f5040a92 | 7689 | dreg = treg; |
67c0d1eb | 7690 | add_breg_early = 1; |
f5040a92 AO |
7691 | } |
7692 | ||
f6a22291 | 7693 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7694 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 7695 | |
f5040a92 AO |
7696 | used_at = 1; |
7697 | } | |
7698 | else | |
7699 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7700 | ||
4d7206a2 | 7701 | relax_switch (); |
f5040a92 | 7702 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
7703 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7704 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
7705 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
7706 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
7707 | if (add_breg_early) | |
f5040a92 | 7708 | { |
67c0d1eb | 7709 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7710 | treg, tempreg, breg); |
f5040a92 AO |
7711 | breg = 0; |
7712 | tempreg = treg; | |
7713 | } | |
4d7206a2 | 7714 | relax_end (); |
f5040a92 | 7715 | } |
252b5132 RH |
7716 | else |
7717 | abort (); | |
7718 | ||
7719 | if (breg != 0) | |
aed1a261 | 7720 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
7721 | break; |
7722 | ||
52b6b6b9 | 7723 | case M_MSGSND: |
df58fc94 | 7724 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7725 | { |
7726 | unsigned long temp = (treg << 16) | (0x01); | |
7727 | macro_build (NULL, "c2", "C", temp); | |
7728 | } | |
c7af4273 | 7729 | break; |
52b6b6b9 JM |
7730 | |
7731 | case M_MSGLD: | |
df58fc94 | 7732 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7733 | { |
7734 | unsigned long temp = (0x02); | |
7735 | macro_build (NULL, "c2", "C", temp); | |
7736 | } | |
c7af4273 | 7737 | break; |
52b6b6b9 JM |
7738 | |
7739 | case M_MSGLD_T: | |
df58fc94 | 7740 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7741 | { |
7742 | unsigned long temp = (treg << 16) | (0x02); | |
7743 | macro_build (NULL, "c2", "C", temp); | |
7744 | } | |
c7af4273 | 7745 | break; |
52b6b6b9 JM |
7746 | |
7747 | case M_MSGWAIT: | |
df58fc94 | 7748 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 7749 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 7750 | break; |
52b6b6b9 JM |
7751 | |
7752 | case M_MSGWAIT_T: | |
df58fc94 | 7753 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7754 | { |
7755 | unsigned long temp = (treg << 16) | 0x03; | |
7756 | macro_build (NULL, "c2", "C", temp); | |
7757 | } | |
c7af4273 | 7758 | break; |
52b6b6b9 | 7759 | |
252b5132 RH |
7760 | case M_J_A: |
7761 | /* The j instruction may not be used in PIC code, since it | |
7762 | requires an absolute address. We convert it to a b | |
7763 | instruction. */ | |
7764 | if (mips_pic == NO_PIC) | |
67c0d1eb | 7765 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 7766 | else |
67c0d1eb | 7767 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 7768 | break; |
252b5132 RH |
7769 | |
7770 | /* The jal instructions must be handled as macros because when | |
7771 | generating PIC code they expand to multi-instruction | |
7772 | sequences. Normally they are simple instructions. */ | |
df58fc94 RS |
7773 | case M_JALS_1: |
7774 | dreg = RA; | |
7775 | /* Fall through. */ | |
7776 | case M_JALS_2: | |
7777 | gas_assert (mips_opts.micromips); | |
7778 | jals = 1; | |
7779 | goto jal; | |
252b5132 RH |
7780 | case M_JAL_1: |
7781 | dreg = RA; | |
7782 | /* Fall through. */ | |
7783 | case M_JAL_2: | |
df58fc94 | 7784 | jal: |
3e722fb5 | 7785 | if (mips_pic == NO_PIC) |
df58fc94 RS |
7786 | { |
7787 | s = jals ? "jalrs" : "jalr"; | |
e64af278 MR |
7788 | if (mips_opts.micromips |
7789 | && dreg == RA | |
7790 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
7791 | macro_build (NULL, s, "mj", sreg); |
7792 | else | |
7793 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
7794 | } | |
0a44bf69 | 7795 | else |
252b5132 | 7796 | { |
df58fc94 RS |
7797 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
7798 | && mips_cprestore_offset >= 0); | |
7799 | ||
252b5132 RH |
7800 | if (sreg != PIC_CALL_REG) |
7801 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 7802 | |
df58fc94 RS |
7803 | s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore) |
7804 | ? "jalrs" : "jalr"); | |
e64af278 MR |
7805 | if (mips_opts.micromips |
7806 | && dreg == RA | |
7807 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
7808 | macro_build (NULL, s, "mj", sreg); |
7809 | else | |
7810 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
0a44bf69 | 7811 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 7812 | { |
6478892d TS |
7813 | if (mips_cprestore_offset < 0) |
7814 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7815 | else | |
7816 | { | |
90ecf173 | 7817 | if (!mips_frame_reg_valid) |
7a621144 DJ |
7818 | { |
7819 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
7820 | /* Quiet this warning. */ | |
7821 | mips_frame_reg_valid = 1; | |
7822 | } | |
90ecf173 | 7823 | if (!mips_cprestore_valid) |
7a621144 DJ |
7824 | { |
7825 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7826 | /* Quiet this warning. */ | |
7827 | mips_cprestore_valid = 1; | |
7828 | } | |
d3fca0b5 MR |
7829 | if (mips_opts.noreorder) |
7830 | macro_build (NULL, "nop", ""); | |
6478892d | 7831 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 7832 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 7833 | mips_gp_register, |
256ab948 TS |
7834 | mips_frame_reg, |
7835 | HAVE_64BIT_ADDRESSES); | |
6478892d | 7836 | } |
252b5132 RH |
7837 | } |
7838 | } | |
252b5132 | 7839 | |
8fc2e39e | 7840 | break; |
252b5132 | 7841 | |
df58fc94 RS |
7842 | case M_JALS_A: |
7843 | gas_assert (mips_opts.micromips); | |
7844 | jals = 1; | |
7845 | /* Fall through. */ | |
252b5132 RH |
7846 | case M_JAL_A: |
7847 | if (mips_pic == NO_PIC) | |
df58fc94 | 7848 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
7849 | else if (mips_pic == SVR4_PIC) |
7850 | { | |
7851 | /* If this is a reference to an external symbol, and we are | |
7852 | using a small GOT, we want | |
7853 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
7854 | nop | |
f9419b05 | 7855 | jalr $ra,$25 |
252b5132 RH |
7856 | nop |
7857 | lw $gp,cprestore($sp) | |
7858 | The cprestore value is set using the .cprestore | |
7859 | pseudo-op. If we are using a big GOT, we want | |
7860 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
7861 | addu $25,$25,$gp | |
7862 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
7863 | nop | |
f9419b05 | 7864 | jalr $ra,$25 |
252b5132 RH |
7865 | nop |
7866 | lw $gp,cprestore($sp) | |
7867 | If the symbol is not external, we want | |
7868 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7869 | nop | |
7870 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 7871 | jalr $ra,$25 |
252b5132 | 7872 | nop |
438c16b8 | 7873 | lw $gp,cprestore($sp) |
f5040a92 AO |
7874 | |
7875 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
7876 | sequences above, minus nops, unless the symbol is local, | |
7877 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
7878 | GOT_DISP. */ | |
438c16b8 | 7879 | if (HAVE_NEWABI) |
252b5132 | 7880 | { |
90ecf173 | 7881 | if (!mips_big_got) |
f5040a92 | 7882 | { |
4d7206a2 | 7883 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7884 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7885 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 7886 | mips_gp_register); |
4d7206a2 | 7887 | relax_switch (); |
67c0d1eb RS |
7888 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7889 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
7890 | mips_gp_register); |
7891 | relax_end (); | |
f5040a92 AO |
7892 | } |
7893 | else | |
7894 | { | |
4d7206a2 | 7895 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 7896 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
7897 | BFD_RELOC_MIPS_CALL_HI16); |
7898 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
7899 | PIC_CALL_REG, mips_gp_register); | |
7900 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
7901 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
7902 | PIC_CALL_REG); | |
4d7206a2 | 7903 | relax_switch (); |
67c0d1eb RS |
7904 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7905 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
7906 | mips_gp_register); | |
7907 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7908 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 7909 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 7910 | relax_end (); |
f5040a92 | 7911 | } |
684022ea | 7912 | |
df58fc94 | 7913 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
7914 | } |
7915 | else | |
7916 | { | |
4d7206a2 | 7917 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 7918 | if (!mips_big_got) |
438c16b8 | 7919 | { |
67c0d1eb RS |
7920 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7921 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 7922 | mips_gp_register); |
269137b2 | 7923 | load_delay_nop (); |
4d7206a2 | 7924 | relax_switch (); |
438c16b8 | 7925 | } |
252b5132 | 7926 | else |
252b5132 | 7927 | { |
67c0d1eb RS |
7928 | int gpdelay; |
7929 | ||
7930 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 7931 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
7932 | BFD_RELOC_MIPS_CALL_HI16); |
7933 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
7934 | PIC_CALL_REG, mips_gp_register); | |
7935 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
7936 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
7937 | PIC_CALL_REG); | |
269137b2 | 7938 | load_delay_nop (); |
4d7206a2 | 7939 | relax_switch (); |
67c0d1eb RS |
7940 | if (gpdelay) |
7941 | macro_build (NULL, "nop", ""); | |
252b5132 | 7942 | } |
67c0d1eb RS |
7943 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7944 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 7945 | mips_gp_register); |
269137b2 | 7946 | load_delay_nop (); |
67c0d1eb RS |
7947 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7948 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 7949 | relax_end (); |
df58fc94 | 7950 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 7951 | |
6478892d TS |
7952 | if (mips_cprestore_offset < 0) |
7953 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7954 | else | |
7955 | { | |
90ecf173 | 7956 | if (!mips_frame_reg_valid) |
7a621144 DJ |
7957 | { |
7958 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
7959 | /* Quiet this warning. */ | |
7960 | mips_frame_reg_valid = 1; | |
7961 | } | |
90ecf173 | 7962 | if (!mips_cprestore_valid) |
7a621144 DJ |
7963 | { |
7964 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7965 | /* Quiet this warning. */ | |
7966 | mips_cprestore_valid = 1; | |
7967 | } | |
6478892d | 7968 | if (mips_opts.noreorder) |
67c0d1eb | 7969 | macro_build (NULL, "nop", ""); |
6478892d | 7970 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 7971 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 7972 | mips_gp_register, |
256ab948 TS |
7973 | mips_frame_reg, |
7974 | HAVE_64BIT_ADDRESSES); | |
6478892d | 7975 | } |
252b5132 RH |
7976 | } |
7977 | } | |
0a44bf69 RS |
7978 | else if (mips_pic == VXWORKS_PIC) |
7979 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
7980 | else |
7981 | abort (); | |
7982 | ||
8fc2e39e | 7983 | break; |
252b5132 | 7984 | |
dec0624d MR |
7985 | case M_ACLR_AB: |
7986 | ab = 1; | |
7987 | case M_ACLR_OB: | |
7988 | s = "aclr"; | |
7989 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
7990 | fmt = "\\,~(b)"; | |
7991 | off12 = 1; | |
7992 | goto ld_st; | |
7993 | case M_ASET_AB: | |
7994 | ab = 1; | |
7995 | case M_ASET_OB: | |
7996 | s = "aset"; | |
7997 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
7998 | fmt = "\\,~(b)"; | |
7999 | off12 = 1; | |
8000 | goto ld_st; | |
252b5132 | 8001 | case M_LB_AB: |
df58fc94 | 8002 | ab = 1; |
252b5132 | 8003 | s = "lb"; |
df58fc94 | 8004 | fmt = "t,o(b)"; |
252b5132 RH |
8005 | goto ld; |
8006 | case M_LBU_AB: | |
df58fc94 | 8007 | ab = 1; |
252b5132 | 8008 | s = "lbu"; |
df58fc94 | 8009 | fmt = "t,o(b)"; |
252b5132 RH |
8010 | goto ld; |
8011 | case M_LH_AB: | |
df58fc94 | 8012 | ab = 1; |
252b5132 | 8013 | s = "lh"; |
df58fc94 | 8014 | fmt = "t,o(b)"; |
252b5132 RH |
8015 | goto ld; |
8016 | case M_LHU_AB: | |
df58fc94 | 8017 | ab = 1; |
252b5132 | 8018 | s = "lhu"; |
df58fc94 | 8019 | fmt = "t,o(b)"; |
252b5132 RH |
8020 | goto ld; |
8021 | case M_LW_AB: | |
df58fc94 | 8022 | ab = 1; |
252b5132 | 8023 | s = "lw"; |
df58fc94 | 8024 | fmt = "t,o(b)"; |
252b5132 RH |
8025 | goto ld; |
8026 | case M_LWC0_AB: | |
df58fc94 RS |
8027 | ab = 1; |
8028 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8029 | s = "lwc0"; |
df58fc94 | 8030 | fmt = "E,o(b)"; |
bdaaa2e1 | 8031 | /* Itbl support may require additional care here. */ |
252b5132 | 8032 | coproc = 1; |
df58fc94 | 8033 | goto ld_st; |
252b5132 | 8034 | case M_LWC1_AB: |
df58fc94 | 8035 | ab = 1; |
252b5132 | 8036 | s = "lwc1"; |
df58fc94 | 8037 | fmt = "T,o(b)"; |
bdaaa2e1 | 8038 | /* Itbl support may require additional care here. */ |
252b5132 | 8039 | coproc = 1; |
df58fc94 | 8040 | goto ld_st; |
252b5132 | 8041 | case M_LWC2_AB: |
df58fc94 RS |
8042 | ab = 1; |
8043 | case M_LWC2_OB: | |
252b5132 | 8044 | s = "lwc2"; |
df58fc94 RS |
8045 | fmt = COP12_FMT; |
8046 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8047 | /* Itbl support may require additional care here. */ |
252b5132 | 8048 | coproc = 1; |
df58fc94 | 8049 | goto ld_st; |
252b5132 | 8050 | case M_LWC3_AB: |
df58fc94 RS |
8051 | ab = 1; |
8052 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8053 | s = "lwc3"; |
df58fc94 | 8054 | fmt = "E,o(b)"; |
bdaaa2e1 | 8055 | /* Itbl support may require additional care here. */ |
252b5132 | 8056 | coproc = 1; |
df58fc94 | 8057 | goto ld_st; |
252b5132 | 8058 | case M_LWL_AB: |
df58fc94 RS |
8059 | ab = 1; |
8060 | case M_LWL_OB: | |
252b5132 | 8061 | s = "lwl"; |
df58fc94 RS |
8062 | fmt = MEM12_FMT; |
8063 | off12 = mips_opts.micromips; | |
8064 | goto ld_st; | |
252b5132 | 8065 | case M_LWR_AB: |
df58fc94 RS |
8066 | ab = 1; |
8067 | case M_LWR_OB: | |
252b5132 | 8068 | s = "lwr"; |
df58fc94 RS |
8069 | fmt = MEM12_FMT; |
8070 | off12 = mips_opts.micromips; | |
8071 | goto ld_st; | |
252b5132 | 8072 | case M_LDC1_AB: |
df58fc94 | 8073 | ab = 1; |
252b5132 | 8074 | s = "ldc1"; |
df58fc94 | 8075 | fmt = "T,o(b)"; |
bdaaa2e1 | 8076 | /* Itbl support may require additional care here. */ |
252b5132 | 8077 | coproc = 1; |
df58fc94 | 8078 | goto ld_st; |
252b5132 | 8079 | case M_LDC2_AB: |
df58fc94 RS |
8080 | ab = 1; |
8081 | case M_LDC2_OB: | |
252b5132 | 8082 | s = "ldc2"; |
df58fc94 RS |
8083 | fmt = COP12_FMT; |
8084 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8085 | /* Itbl support may require additional care here. */ |
252b5132 | 8086 | coproc = 1; |
df58fc94 | 8087 | goto ld_st; |
252b5132 | 8088 | case M_LDC3_AB: |
df58fc94 | 8089 | ab = 1; |
252b5132 | 8090 | s = "ldc3"; |
df58fc94 | 8091 | fmt = "E,o(b)"; |
bdaaa2e1 | 8092 | /* Itbl support may require additional care here. */ |
252b5132 | 8093 | coproc = 1; |
df58fc94 | 8094 | goto ld_st; |
252b5132 | 8095 | case M_LDL_AB: |
df58fc94 RS |
8096 | ab = 1; |
8097 | case M_LDL_OB: | |
252b5132 | 8098 | s = "ldl"; |
df58fc94 RS |
8099 | fmt = MEM12_FMT; |
8100 | off12 = mips_opts.micromips; | |
8101 | goto ld_st; | |
252b5132 | 8102 | case M_LDR_AB: |
df58fc94 RS |
8103 | ab = 1; |
8104 | case M_LDR_OB: | |
252b5132 | 8105 | s = "ldr"; |
df58fc94 RS |
8106 | fmt = MEM12_FMT; |
8107 | off12 = mips_opts.micromips; | |
8108 | goto ld_st; | |
252b5132 | 8109 | case M_LL_AB: |
df58fc94 RS |
8110 | ab = 1; |
8111 | case M_LL_OB: | |
252b5132 | 8112 | s = "ll"; |
df58fc94 RS |
8113 | fmt = MEM12_FMT; |
8114 | off12 = mips_opts.micromips; | |
252b5132 RH |
8115 | goto ld; |
8116 | case M_LLD_AB: | |
df58fc94 RS |
8117 | ab = 1; |
8118 | case M_LLD_OB: | |
252b5132 | 8119 | s = "lld"; |
df58fc94 RS |
8120 | fmt = MEM12_FMT; |
8121 | off12 = mips_opts.micromips; | |
252b5132 RH |
8122 | goto ld; |
8123 | case M_LWU_AB: | |
df58fc94 RS |
8124 | ab = 1; |
8125 | case M_LWU_OB: | |
252b5132 | 8126 | s = "lwu"; |
df58fc94 RS |
8127 | fmt = MEM12_FMT; |
8128 | off12 = mips_opts.micromips; | |
8129 | goto ld; | |
8130 | case M_LWP_AB: | |
8131 | ab = 1; | |
8132 | case M_LWP_OB: | |
8133 | gas_assert (mips_opts.micromips); | |
8134 | s = "lwp"; | |
8135 | fmt = "t,~(b)"; | |
8136 | off12 = 1; | |
8137 | lp = 1; | |
8138 | goto ld; | |
8139 | case M_LDP_AB: | |
8140 | ab = 1; | |
8141 | case M_LDP_OB: | |
8142 | gas_assert (mips_opts.micromips); | |
8143 | s = "ldp"; | |
8144 | fmt = "t,~(b)"; | |
8145 | off12 = 1; | |
8146 | lp = 1; | |
8147 | goto ld; | |
8148 | case M_LWM_AB: | |
8149 | ab = 1; | |
8150 | case M_LWM_OB: | |
8151 | gas_assert (mips_opts.micromips); | |
8152 | s = "lwm"; | |
8153 | fmt = "n,~(b)"; | |
8154 | off12 = 1; | |
8155 | goto ld_st; | |
8156 | case M_LDM_AB: | |
8157 | ab = 1; | |
8158 | case M_LDM_OB: | |
8159 | gas_assert (mips_opts.micromips); | |
8160 | s = "ldm"; | |
8161 | fmt = "n,~(b)"; | |
8162 | off12 = 1; | |
8163 | goto ld_st; | |
8164 | ||
252b5132 | 8165 | ld: |
df58fc94 RS |
8166 | if (breg == treg + lp) |
8167 | goto ld_st; | |
252b5132 | 8168 | else |
df58fc94 RS |
8169 | tempreg = treg + lp; |
8170 | goto ld_noat; | |
8171 | ||
252b5132 | 8172 | case M_SB_AB: |
df58fc94 | 8173 | ab = 1; |
252b5132 | 8174 | s = "sb"; |
df58fc94 RS |
8175 | fmt = "t,o(b)"; |
8176 | goto ld_st; | |
252b5132 | 8177 | case M_SH_AB: |
df58fc94 | 8178 | ab = 1; |
252b5132 | 8179 | s = "sh"; |
df58fc94 RS |
8180 | fmt = "t,o(b)"; |
8181 | goto ld_st; | |
252b5132 | 8182 | case M_SW_AB: |
df58fc94 | 8183 | ab = 1; |
252b5132 | 8184 | s = "sw"; |
df58fc94 RS |
8185 | fmt = "t,o(b)"; |
8186 | goto ld_st; | |
252b5132 | 8187 | case M_SWC0_AB: |
df58fc94 RS |
8188 | ab = 1; |
8189 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8190 | s = "swc0"; |
df58fc94 | 8191 | fmt = "E,o(b)"; |
bdaaa2e1 | 8192 | /* Itbl support may require additional care here. */ |
252b5132 | 8193 | coproc = 1; |
df58fc94 | 8194 | goto ld_st; |
252b5132 | 8195 | case M_SWC1_AB: |
df58fc94 | 8196 | ab = 1; |
252b5132 | 8197 | s = "swc1"; |
df58fc94 | 8198 | fmt = "T,o(b)"; |
bdaaa2e1 | 8199 | /* Itbl support may require additional care here. */ |
252b5132 | 8200 | coproc = 1; |
df58fc94 | 8201 | goto ld_st; |
252b5132 | 8202 | case M_SWC2_AB: |
df58fc94 RS |
8203 | ab = 1; |
8204 | case M_SWC2_OB: | |
252b5132 | 8205 | s = "swc2"; |
df58fc94 RS |
8206 | fmt = COP12_FMT; |
8207 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8208 | /* Itbl support may require additional care here. */ |
252b5132 | 8209 | coproc = 1; |
df58fc94 | 8210 | goto ld_st; |
252b5132 | 8211 | case M_SWC3_AB: |
df58fc94 RS |
8212 | ab = 1; |
8213 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8214 | s = "swc3"; |
df58fc94 | 8215 | fmt = "E,o(b)"; |
bdaaa2e1 | 8216 | /* Itbl support may require additional care here. */ |
252b5132 | 8217 | coproc = 1; |
df58fc94 | 8218 | goto ld_st; |
252b5132 | 8219 | case M_SWL_AB: |
df58fc94 RS |
8220 | ab = 1; |
8221 | case M_SWL_OB: | |
252b5132 | 8222 | s = "swl"; |
df58fc94 RS |
8223 | fmt = MEM12_FMT; |
8224 | off12 = mips_opts.micromips; | |
8225 | goto ld_st; | |
252b5132 | 8226 | case M_SWR_AB: |
df58fc94 RS |
8227 | ab = 1; |
8228 | case M_SWR_OB: | |
252b5132 | 8229 | s = "swr"; |
df58fc94 RS |
8230 | fmt = MEM12_FMT; |
8231 | off12 = mips_opts.micromips; | |
8232 | goto ld_st; | |
252b5132 | 8233 | case M_SC_AB: |
df58fc94 RS |
8234 | ab = 1; |
8235 | case M_SC_OB: | |
252b5132 | 8236 | s = "sc"; |
df58fc94 RS |
8237 | fmt = MEM12_FMT; |
8238 | off12 = mips_opts.micromips; | |
8239 | goto ld_st; | |
252b5132 | 8240 | case M_SCD_AB: |
df58fc94 RS |
8241 | ab = 1; |
8242 | case M_SCD_OB: | |
252b5132 | 8243 | s = "scd"; |
df58fc94 RS |
8244 | fmt = MEM12_FMT; |
8245 | off12 = mips_opts.micromips; | |
8246 | goto ld_st; | |
d43b4baf | 8247 | case M_CACHE_AB: |
df58fc94 RS |
8248 | ab = 1; |
8249 | case M_CACHE_OB: | |
d43b4baf | 8250 | s = "cache"; |
df58fc94 RS |
8251 | fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)"; |
8252 | off12 = mips_opts.micromips; | |
8253 | goto ld_st; | |
3eebd5eb | 8254 | case M_PREF_AB: |
df58fc94 RS |
8255 | ab = 1; |
8256 | case M_PREF_OB: | |
3eebd5eb | 8257 | s = "pref"; |
df58fc94 RS |
8258 | fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)"; |
8259 | off12 = mips_opts.micromips; | |
8260 | goto ld_st; | |
252b5132 | 8261 | case M_SDC1_AB: |
df58fc94 | 8262 | ab = 1; |
252b5132 | 8263 | s = "sdc1"; |
df58fc94 | 8264 | fmt = "T,o(b)"; |
252b5132 | 8265 | coproc = 1; |
bdaaa2e1 | 8266 | /* Itbl support may require additional care here. */ |
df58fc94 | 8267 | goto ld_st; |
252b5132 | 8268 | case M_SDC2_AB: |
df58fc94 RS |
8269 | ab = 1; |
8270 | case M_SDC2_OB: | |
252b5132 | 8271 | s = "sdc2"; |
df58fc94 RS |
8272 | fmt = COP12_FMT; |
8273 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8274 | /* Itbl support may require additional care here. */ |
252b5132 | 8275 | coproc = 1; |
df58fc94 | 8276 | goto ld_st; |
252b5132 | 8277 | case M_SDC3_AB: |
df58fc94 RS |
8278 | ab = 1; |
8279 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8280 | s = "sdc3"; |
df58fc94 | 8281 | fmt = "E,o(b)"; |
bdaaa2e1 | 8282 | /* Itbl support may require additional care here. */ |
252b5132 | 8283 | coproc = 1; |
df58fc94 | 8284 | goto ld_st; |
252b5132 | 8285 | case M_SDL_AB: |
df58fc94 RS |
8286 | ab = 1; |
8287 | case M_SDL_OB: | |
252b5132 | 8288 | s = "sdl"; |
df58fc94 RS |
8289 | fmt = MEM12_FMT; |
8290 | off12 = mips_opts.micromips; | |
8291 | goto ld_st; | |
252b5132 | 8292 | case M_SDR_AB: |
df58fc94 RS |
8293 | ab = 1; |
8294 | case M_SDR_OB: | |
252b5132 | 8295 | s = "sdr"; |
df58fc94 RS |
8296 | fmt = MEM12_FMT; |
8297 | off12 = mips_opts.micromips; | |
8298 | goto ld_st; | |
8299 | case M_SWP_AB: | |
8300 | ab = 1; | |
8301 | case M_SWP_OB: | |
8302 | gas_assert (mips_opts.micromips); | |
8303 | s = "swp"; | |
8304 | fmt = "t,~(b)"; | |
8305 | off12 = 1; | |
8306 | goto ld_st; | |
8307 | case M_SDP_AB: | |
8308 | ab = 1; | |
8309 | case M_SDP_OB: | |
8310 | gas_assert (mips_opts.micromips); | |
8311 | s = "sdp"; | |
8312 | fmt = "t,~(b)"; | |
8313 | off12 = 1; | |
8314 | goto ld_st; | |
8315 | case M_SWM_AB: | |
8316 | ab = 1; | |
8317 | case M_SWM_OB: | |
8318 | gas_assert (mips_opts.micromips); | |
8319 | s = "swm"; | |
8320 | fmt = "n,~(b)"; | |
8321 | off12 = 1; | |
8322 | goto ld_st; | |
8323 | case M_SDM_AB: | |
8324 | ab = 1; | |
8325 | case M_SDM_OB: | |
8326 | gas_assert (mips_opts.micromips); | |
8327 | s = "sdm"; | |
8328 | fmt = "n,~(b)"; | |
8329 | off12 = 1; | |
8330 | ||
8331 | ld_st: | |
8fc2e39e TS |
8332 | tempreg = AT; |
8333 | used_at = 1; | |
df58fc94 | 8334 | ld_noat: |
252b5132 RH |
8335 | if (offset_expr.X_op != O_constant |
8336 | && offset_expr.X_op != O_symbol) | |
8337 | { | |
f71d0d44 | 8338 | as_bad (_("Expression too complex")); |
252b5132 RH |
8339 | offset_expr.X_op = O_constant; |
8340 | } | |
8341 | ||
2051e8c4 MR |
8342 | if (HAVE_32BIT_ADDRESSES |
8343 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8344 | { |
8345 | char value [32]; | |
8346 | ||
8347 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8348 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8349 | } |
2051e8c4 | 8350 | |
252b5132 RH |
8351 | /* A constant expression in PIC code can be handled just as it |
8352 | is in non PIC code. */ | |
aed1a261 RS |
8353 | if (offset_expr.X_op == O_constant) |
8354 | { | |
df58fc94 RS |
8355 | int hipart = 0; |
8356 | ||
842f8b2a | 8357 | expr1.X_add_number = offset_expr.X_add_number; |
2051e8c4 | 8358 | normalize_address_expr (&expr1); |
df58fc94 | 8359 | if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number)) |
842f8b2a MR |
8360 | { |
8361 | expr1.X_add_number = ((expr1.X_add_number + 0x8000) | |
8362 | & ~(bfd_vma) 0xffff); | |
df58fc94 RS |
8363 | hipart = 1; |
8364 | } | |
8365 | else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number)) | |
8366 | { | |
8367 | expr1.X_add_number = ((expr1.X_add_number + 0x800) | |
8368 | & ~(bfd_vma) 0xfff); | |
8369 | hipart = 1; | |
8370 | } | |
8371 | if (hipart) | |
8372 | { | |
842f8b2a MR |
8373 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
8374 | if (breg != 0) | |
8375 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8376 | tempreg, tempreg, breg); | |
8377 | breg = tempreg; | |
8378 | } | |
dd6a37e7 AP |
8379 | if (off0) |
8380 | { | |
8381 | if (offset_expr.X_add_number == 0) | |
8382 | tempreg = breg; | |
8383 | else | |
8384 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, | |
8385 | "t,r,j", tempreg, breg, BFD_RELOC_LO16); | |
8386 | macro_build (NULL, s, fmt, treg, tempreg); | |
8387 | } | |
8388 | else if (!off12) | |
df58fc94 RS |
8389 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg); |
8390 | else | |
8391 | macro_build (NULL, s, fmt, | |
8392 | treg, (unsigned long) offset_expr.X_add_number, breg); | |
8393 | } | |
dd6a37e7 | 8394 | else if (off12 || off0) |
df58fc94 | 8395 | { |
dd6a37e7 AP |
8396 | /* A 12-bit or 0-bit offset field is too narrow to be used |
8397 | for a low-part relocation, so load the whole address into | |
8398 | the auxillary register. In the case of "A(b)" addresses, | |
8399 | we first load absolute address "A" into the register and | |
8400 | then add base register "b". In the case of "o(b)" addresses, | |
8401 | we simply need to add 16-bit offset "o" to base register "b", and | |
df58fc94 RS |
8402 | offset_reloc already contains the relocations associated |
8403 | with "o". */ | |
8404 | if (ab) | |
8405 | { | |
8406 | load_address (tempreg, &offset_expr, &used_at); | |
8407 | if (breg != 0) | |
8408 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8409 | tempreg, tempreg, breg); | |
8410 | } | |
8411 | else | |
8412 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8413 | tempreg, breg, -1, | |
8414 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
8415 | expr1.X_add_number = 0; | |
dd6a37e7 AP |
8416 | if (off0) |
8417 | macro_build (NULL, s, fmt, treg, tempreg); | |
8418 | else | |
8419 | macro_build (NULL, s, fmt, | |
8420 | treg, (unsigned long) expr1.X_add_number, tempreg); | |
aed1a261 RS |
8421 | } |
8422 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
8423 | { |
8424 | /* If this is a reference to a GP relative symbol, and there | |
8425 | is no base register, we want | |
cdf6fd85 | 8426 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
8427 | Otherwise, if there is no base register, we want |
8428 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8429 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8430 | If we have a constant, we need two instructions anyhow, | |
8431 | so we always use the latter form. | |
8432 | ||
8433 | If we have a base register, and this is a reference to a | |
8434 | GP relative symbol, we want | |
8435 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 8436 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
8437 | Otherwise we want |
8438 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8439 | addu $tempreg,$tempreg,$breg | |
8440 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 8441 | With a constant we always use the latter case. |
76b3015f | 8442 | |
d6bc6245 TS |
8443 | With 64bit address space and no base register and $at usable, |
8444 | we want | |
8445 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8446 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8447 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8448 | dsll32 $tempreg,0 | |
8449 | daddu $tempreg,$at | |
8450 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8451 | If we have a base register, we want | |
8452 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8453 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8454 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8455 | daddu $at,$breg | |
8456 | dsll32 $tempreg,0 | |
8457 | daddu $tempreg,$at | |
8458 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8459 | ||
8460 | Without $at we can't generate the optimal path for superscalar | |
8461 | processors here since this would require two temporary registers. | |
8462 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8463 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8464 | dsll $tempreg,16 | |
8465 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8466 | dsll $tempreg,16 | |
8467 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8468 | If we have a base register, we want | |
8469 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8470 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8471 | dsll $tempreg,16 | |
8472 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8473 | dsll $tempreg,16 | |
8474 | daddu $tempreg,$tempreg,$breg | |
8475 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 8476 | |
6caf9ef4 | 8477 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
8478 | the same sequence as in 32bit address space. */ |
8479 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 8480 | { |
aed1a261 | 8481 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
8482 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
8483 | { | |
8484 | relax_start (offset_expr.X_add_symbol); | |
8485 | if (breg == 0) | |
8486 | { | |
8487 | macro_build (&offset_expr, s, fmt, treg, | |
8488 | BFD_RELOC_GPREL16, mips_gp_register); | |
8489 | } | |
8490 | else | |
8491 | { | |
8492 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8493 | tempreg, breg, mips_gp_register); | |
8494 | macro_build (&offset_expr, s, fmt, treg, | |
8495 | BFD_RELOC_GPREL16, tempreg); | |
8496 | } | |
8497 | relax_switch (); | |
8498 | } | |
d6bc6245 | 8499 | |
741fe287 | 8500 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 8501 | { |
df58fc94 | 8502 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 8503 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 8504 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
8505 | BFD_RELOC_HI16_S); |
8506 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8507 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 8508 | if (breg != 0) |
67c0d1eb | 8509 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 8510 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb RS |
8511 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
8512 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
8513 | tempreg); | |
d6bc6245 TS |
8514 | used_at = 1; |
8515 | } | |
8516 | else | |
8517 | { | |
df58fc94 | 8518 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
8519 | BFD_RELOC_MIPS_HIGHEST); |
8520 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8521 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 8522 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
8523 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
8524 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 8525 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 8526 | if (breg != 0) |
67c0d1eb | 8527 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 8528 | tempreg, tempreg, breg); |
67c0d1eb | 8529 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8530 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 8531 | } |
6caf9ef4 TS |
8532 | |
8533 | if (mips_relax.sequence) | |
8534 | relax_end (); | |
8fc2e39e | 8535 | break; |
d6bc6245 | 8536 | } |
256ab948 | 8537 | |
252b5132 RH |
8538 | if (breg == 0) |
8539 | { | |
67c0d1eb | 8540 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8541 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8542 | { |
4d7206a2 | 8543 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8544 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
8545 | mips_gp_register); | |
4d7206a2 | 8546 | relax_switch (); |
252b5132 | 8547 | } |
67c0d1eb RS |
8548 | macro_build_lui (&offset_expr, tempreg); |
8549 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 8550 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8551 | if (mips_relax.sequence) |
8552 | relax_end (); | |
252b5132 RH |
8553 | } |
8554 | else | |
8555 | { | |
67c0d1eb | 8556 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8557 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8558 | { |
4d7206a2 | 8559 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 8560 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8561 | tempreg, breg, mips_gp_register); |
67c0d1eb | 8562 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8563 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 8564 | relax_switch (); |
252b5132 | 8565 | } |
67c0d1eb RS |
8566 | macro_build_lui (&offset_expr, tempreg); |
8567 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 8568 | tempreg, tempreg, breg); |
67c0d1eb | 8569 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8570 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8571 | if (mips_relax.sequence) |
8572 | relax_end (); | |
252b5132 RH |
8573 | } |
8574 | } | |
0a44bf69 | 8575 | else if (!mips_big_got) |
252b5132 | 8576 | { |
ed6fb7bd | 8577 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 8578 | |
252b5132 RH |
8579 | /* If this is a reference to an external symbol, we want |
8580 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8581 | nop | |
8582 | <op> $treg,0($tempreg) | |
8583 | Otherwise we want | |
8584 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8585 | nop | |
8586 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8587 | <op> $treg,0($tempreg) | |
f5040a92 AO |
8588 | |
8589 | For NewABI, we want | |
8590 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8591 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
8592 | ||
252b5132 RH |
8593 | If there is a base register, we add it to $tempreg before |
8594 | the <op>. If there is a constant, we stick it in the | |
8595 | <op> instruction. We don't handle constants larger than | |
8596 | 16 bits, because we have no way to load the upper 16 bits | |
8597 | (actually, we could handle them for the subset of cases | |
8598 | in which we are not using $at). */ | |
9c2799c2 | 8599 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
8600 | if (HAVE_NEWABI) |
8601 | { | |
67c0d1eb RS |
8602 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8603 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8604 | if (breg != 0) |
67c0d1eb | 8605 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8606 | tempreg, tempreg, breg); |
67c0d1eb | 8607 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8608 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
8609 | break; |
8610 | } | |
252b5132 RH |
8611 | expr1.X_add_number = offset_expr.X_add_number; |
8612 | offset_expr.X_add_number = 0; | |
8613 | if (expr1.X_add_number < -0x8000 | |
8614 | || expr1.X_add_number >= 0x8000) | |
8615 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
8616 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8617 | lw_reloc_type, mips_gp_register); | |
269137b2 | 8618 | load_delay_nop (); |
4d7206a2 RS |
8619 | relax_start (offset_expr.X_add_symbol); |
8620 | relax_switch (); | |
67c0d1eb RS |
8621 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8622 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 8623 | relax_end (); |
252b5132 | 8624 | if (breg != 0) |
67c0d1eb | 8625 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8626 | tempreg, tempreg, breg); |
67c0d1eb | 8627 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8628 | } |
0a44bf69 | 8629 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 8630 | { |
67c0d1eb | 8631 | int gpdelay; |
252b5132 RH |
8632 | |
8633 | /* If this is a reference to an external symbol, we want | |
8634 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8635 | addu $tempreg,$tempreg,$gp | |
8636 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8637 | <op> $treg,0($tempreg) | |
8638 | Otherwise we want | |
8639 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8640 | nop | |
8641 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8642 | <op> $treg,0($tempreg) | |
8643 | If there is a base register, we add it to $tempreg before | |
8644 | the <op>. If there is a constant, we stick it in the | |
8645 | <op> instruction. We don't handle constants larger than | |
8646 | 16 bits, because we have no way to load the upper 16 bits | |
8647 | (actually, we could handle them for the subset of cases | |
f5040a92 | 8648 | in which we are not using $at). */ |
9c2799c2 | 8649 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
8650 | expr1.X_add_number = offset_expr.X_add_number; |
8651 | offset_expr.X_add_number = 0; | |
8652 | if (expr1.X_add_number < -0x8000 | |
8653 | || expr1.X_add_number >= 0x8000) | |
8654 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 8655 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 8656 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8657 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8658 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8659 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8660 | mips_gp_register); | |
8661 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8662 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 8663 | relax_switch (); |
67c0d1eb RS |
8664 | if (gpdelay) |
8665 | macro_build (NULL, "nop", ""); | |
8666 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8667 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 8668 | load_delay_nop (); |
67c0d1eb RS |
8669 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8670 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
8671 | relax_end (); |
8672 | ||
252b5132 | 8673 | if (breg != 0) |
67c0d1eb | 8674 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8675 | tempreg, tempreg, breg); |
67c0d1eb | 8676 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8677 | } |
0a44bf69 | 8678 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 8679 | { |
f5040a92 AO |
8680 | /* If this is a reference to an external symbol, we want |
8681 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8682 | add $tempreg,$tempreg,$gp | |
8683 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8684 | <op> $treg,<ofst>($tempreg) | |
8685 | Otherwise, for local symbols, we want: | |
8686 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8687 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 8688 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 8689 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
8690 | offset_expr.X_add_number = 0; |
8691 | if (expr1.X_add_number < -0x8000 | |
8692 | || expr1.X_add_number >= 0x8000) | |
8693 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 8694 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8695 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8696 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8697 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8698 | mips_gp_register); | |
8699 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8700 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 8701 | if (breg != 0) |
67c0d1eb | 8702 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8703 | tempreg, tempreg, breg); |
67c0d1eb | 8704 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 8705 | |
4d7206a2 | 8706 | relax_switch (); |
f5040a92 | 8707 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
8708 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8709 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8710 | if (breg != 0) |
67c0d1eb | 8711 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8712 | tempreg, tempreg, breg); |
67c0d1eb | 8713 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8714 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 8715 | relax_end (); |
f5040a92 | 8716 | } |
252b5132 RH |
8717 | else |
8718 | abort (); | |
8719 | ||
252b5132 RH |
8720 | break; |
8721 | ||
8722 | case M_LI: | |
8723 | case M_LI_S: | |
67c0d1eb | 8724 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 8725 | break; |
252b5132 RH |
8726 | |
8727 | case M_DLI: | |
67c0d1eb | 8728 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 8729 | break; |
252b5132 RH |
8730 | |
8731 | case M_LI_SS: | |
8732 | if (imm_expr.X_op == O_constant) | |
8733 | { | |
8fc2e39e | 8734 | used_at = 1; |
67c0d1eb RS |
8735 | load_register (AT, &imm_expr, 0); |
8736 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8737 | break; |
8738 | } | |
8739 | else | |
8740 | { | |
9c2799c2 | 8741 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
8742 | && strcmp (segment_name (S_GET_SEGMENT |
8743 | (offset_expr.X_add_symbol)), | |
8744 | ".lit4") == 0 | |
8745 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 8746 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 8747 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8748 | break; |
252b5132 RH |
8749 | } |
8750 | ||
8751 | case M_LI_D: | |
ca4e0257 RS |
8752 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
8753 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
8754 | order 32 bits of the value and the low order 32 bits are either | |
8755 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
8756 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8757 | { | |
ca4e0257 | 8758 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 8759 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
8760 | else |
8761 | { | |
8762 | int hreg, lreg; | |
8763 | ||
8764 | if (target_big_endian) | |
8765 | { | |
8766 | hreg = treg; | |
8767 | lreg = treg + 1; | |
8768 | } | |
8769 | else | |
8770 | { | |
8771 | hreg = treg + 1; | |
8772 | lreg = treg; | |
8773 | } | |
8774 | ||
8775 | if (hreg <= 31) | |
67c0d1eb | 8776 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
8777 | if (lreg <= 31) |
8778 | { | |
8779 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 8780 | move_register (lreg, 0); |
252b5132 RH |
8781 | else |
8782 | { | |
9c2799c2 | 8783 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 8784 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
8785 | } |
8786 | } | |
8787 | } | |
8fc2e39e | 8788 | break; |
252b5132 RH |
8789 | } |
8790 | ||
8791 | /* We know that sym is in the .rdata section. First we get the | |
8792 | upper 16 bits of the address. */ | |
8793 | if (mips_pic == NO_PIC) | |
8794 | { | |
67c0d1eb | 8795 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 8796 | used_at = 1; |
252b5132 | 8797 | } |
0a44bf69 | 8798 | else |
252b5132 | 8799 | { |
67c0d1eb RS |
8800 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
8801 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 8802 | used_at = 1; |
252b5132 | 8803 | } |
bdaaa2e1 | 8804 | |
252b5132 | 8805 | /* Now we load the register(s). */ |
ca4e0257 | 8806 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
8807 | { |
8808 | used_at = 1; | |
8809 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
8810 | } | |
252b5132 RH |
8811 | else |
8812 | { | |
8fc2e39e | 8813 | used_at = 1; |
67c0d1eb | 8814 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 8815 | if (treg != RA) |
252b5132 RH |
8816 | { |
8817 | /* FIXME: How in the world do we deal with the possible | |
8818 | overflow here? */ | |
8819 | offset_expr.X_add_number += 4; | |
67c0d1eb | 8820 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 8821 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
8822 | } |
8823 | } | |
252b5132 RH |
8824 | break; |
8825 | ||
8826 | case M_LI_DD: | |
ca4e0257 RS |
8827 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
8828 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
8829 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
8830 | the value and the low order 32 bits are either zero or in | |
8831 | OFFSET_EXPR. */ | |
252b5132 RH |
8832 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8833 | { | |
8fc2e39e | 8834 | used_at = 1; |
67c0d1eb | 8835 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
8836 | if (HAVE_64BIT_FPRS) |
8837 | { | |
9c2799c2 | 8838 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 8839 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 8840 | } |
252b5132 RH |
8841 | else |
8842 | { | |
67c0d1eb | 8843 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 8844 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 8845 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
8846 | else |
8847 | { | |
9c2799c2 | 8848 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
8849 | load_register (AT, &offset_expr, 0); |
8850 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8851 | } |
8852 | } | |
8853 | break; | |
8854 | } | |
8855 | ||
9c2799c2 | 8856 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 8857 | && offset_expr.X_add_number == 0); |
252b5132 RH |
8858 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
8859 | if (strcmp (s, ".lit8") == 0) | |
8860 | { | |
df58fc94 | 8861 | if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips) |
252b5132 | 8862 | { |
67c0d1eb | 8863 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 8864 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8865 | break; |
252b5132 | 8866 | } |
c9914766 | 8867 | breg = mips_gp_register; |
252b5132 RH |
8868 | r = BFD_RELOC_MIPS_LITERAL; |
8869 | goto dob; | |
8870 | } | |
8871 | else | |
8872 | { | |
9c2799c2 | 8873 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 8874 | used_at = 1; |
0a44bf69 | 8875 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
8876 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
8877 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
8878 | else |
8879 | { | |
8880 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 8881 | macro_build_lui (&offset_expr, AT); |
252b5132 | 8882 | } |
bdaaa2e1 | 8883 | |
df58fc94 | 8884 | if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips) |
252b5132 | 8885 | { |
67c0d1eb RS |
8886 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
8887 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
8888 | break; |
8889 | } | |
8890 | breg = AT; | |
8891 | r = BFD_RELOC_LO16; | |
8892 | goto dob; | |
8893 | } | |
8894 | ||
8895 | case M_L_DOB: | |
252b5132 RH |
8896 | /* Even on a big endian machine $fn comes before $fn+1. We have |
8897 | to adjust when loading from memory. */ | |
8898 | r = BFD_RELOC_LO16; | |
8899 | dob: | |
df58fc94 | 8900 | gas_assert (!mips_opts.micromips); |
9c2799c2 | 8901 | gas_assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 8902 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 8903 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
8904 | /* FIXME: A possible overflow which I don't know how to deal |
8905 | with. */ | |
8906 | offset_expr.X_add_number += 4; | |
67c0d1eb | 8907 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 8908 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
8909 | break; |
8910 | ||
c4a68bea | 8911 | case M_S_DOB: |
df58fc94 | 8912 | gas_assert (!mips_opts.micromips); |
c4a68bea MR |
8913 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8914 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
8915 | to adjust when storing to memory. */ | |
8916 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
8917 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
8918 | offset_expr.X_add_number += 4; | |
8919 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
8920 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8921 | break; | |
8922 | ||
252b5132 | 8923 | case M_L_DAB: |
df58fc94 | 8924 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
8925 | /* |
8926 | * The MIPS assembler seems to check for X_add_number not | |
8927 | * being double aligned and generating: | |
8928 | * lui at,%hi(foo+1) | |
8929 | * addu at,at,v1 | |
8930 | * addiu at,at,%lo(foo+1) | |
8931 | * lwc1 f2,0(at) | |
8932 | * lwc1 f3,4(at) | |
8933 | * But, the resulting address is the same after relocation so why | |
8934 | * generate the extra instruction? | |
8935 | */ | |
bdaaa2e1 | 8936 | /* Itbl support may require additional care here. */ |
252b5132 | 8937 | coproc = 1; |
df58fc94 | 8938 | fmt = "T,o(b)"; |
e7af610e | 8939 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
8940 | { |
8941 | s = "ldc1"; | |
df58fc94 | 8942 | goto ld_st; |
252b5132 | 8943 | } |
252b5132 | 8944 | s = "lwc1"; |
252b5132 RH |
8945 | goto ldd_std; |
8946 | ||
8947 | case M_S_DAB: | |
df58fc94 RS |
8948 | gas_assert (!mips_opts.micromips); |
8949 | /* Itbl support may require additional care here. */ | |
8950 | coproc = 1; | |
8951 | fmt = "T,o(b)"; | |
e7af610e | 8952 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
8953 | { |
8954 | s = "sdc1"; | |
df58fc94 | 8955 | goto ld_st; |
252b5132 | 8956 | } |
252b5132 | 8957 | s = "swc1"; |
252b5132 RH |
8958 | goto ldd_std; |
8959 | ||
8960 | case M_LD_AB: | |
df58fc94 | 8961 | fmt = "t,o(b)"; |
ca4e0257 | 8962 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
8963 | { |
8964 | s = "ld"; | |
8965 | goto ld; | |
8966 | } | |
252b5132 | 8967 | s = "lw"; |
252b5132 RH |
8968 | goto ldd_std; |
8969 | ||
8970 | case M_SD_AB: | |
df58fc94 | 8971 | fmt = "t,o(b)"; |
ca4e0257 | 8972 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
8973 | { |
8974 | s = "sd"; | |
df58fc94 | 8975 | goto ld_st; |
252b5132 | 8976 | } |
252b5132 | 8977 | s = "sw"; |
252b5132 RH |
8978 | |
8979 | ldd_std: | |
8980 | if (offset_expr.X_op != O_symbol | |
8981 | && offset_expr.X_op != O_constant) | |
8982 | { | |
f71d0d44 | 8983 | as_bad (_("Expression too complex")); |
252b5132 RH |
8984 | offset_expr.X_op = O_constant; |
8985 | } | |
8986 | ||
2051e8c4 MR |
8987 | if (HAVE_32BIT_ADDRESSES |
8988 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8989 | { |
8990 | char value [32]; | |
8991 | ||
8992 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8993 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8994 | } |
2051e8c4 | 8995 | |
252b5132 RH |
8996 | /* Even on a big endian machine $fn comes before $fn+1. We have |
8997 | to adjust when loading from memory. We set coproc if we must | |
8998 | load $fn+1 first. */ | |
bdaaa2e1 | 8999 | /* Itbl support may require additional care here. */ |
90ecf173 | 9000 | if (!target_big_endian) |
252b5132 RH |
9001 | coproc = 0; |
9002 | ||
90ecf173 | 9003 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
9004 | { |
9005 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
9006 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
9007 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9008 | If we have a base register, we use this |
9009 | addu $at,$breg,$gp | |
cdf6fd85 TS |
9010 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
9011 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9012 | If this is not a GP relative symbol, we want |
9013 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9014 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9015 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9016 | If there is a base register, we add it to $at after the | |
9017 | lui instruction. If there is a constant, we always use | |
9018 | the last case. */ | |
39a59cf8 MR |
9019 | if (offset_expr.X_op == O_symbol |
9020 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 9021 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 9022 | { |
4d7206a2 | 9023 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
9024 | if (breg == 0) |
9025 | { | |
c9914766 | 9026 | tempreg = mips_gp_register; |
252b5132 RH |
9027 | } |
9028 | else | |
9029 | { | |
67c0d1eb | 9030 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9031 | AT, breg, mips_gp_register); |
252b5132 | 9032 | tempreg = AT; |
252b5132 RH |
9033 | used_at = 1; |
9034 | } | |
9035 | ||
beae10d5 | 9036 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9037 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9038 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9039 | offset_expr.X_add_number += 4; |
9040 | ||
9041 | /* Set mips_optimize to 2 to avoid inserting an | |
9042 | undesired nop. */ | |
9043 | hold_mips_optimize = mips_optimize; | |
9044 | mips_optimize = 2; | |
beae10d5 | 9045 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9046 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9047 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9048 | mips_optimize = hold_mips_optimize; |
9049 | ||
4d7206a2 | 9050 | relax_switch (); |
252b5132 | 9051 | |
0970e49e | 9052 | offset_expr.X_add_number -= 4; |
252b5132 | 9053 | } |
8fc2e39e | 9054 | used_at = 1; |
67c0d1eb | 9055 | macro_build_lui (&offset_expr, AT); |
252b5132 | 9056 | if (breg != 0) |
67c0d1eb | 9057 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9058 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9059 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9060 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9061 | /* FIXME: How do we handle overflow here? */ |
9062 | offset_expr.X_add_number += 4; | |
beae10d5 | 9063 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9064 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9065 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
9066 | if (mips_relax.sequence) |
9067 | relax_end (); | |
bdaaa2e1 | 9068 | } |
0a44bf69 | 9069 | else if (!mips_big_got) |
252b5132 | 9070 | { |
252b5132 RH |
9071 | /* If this is a reference to an external symbol, we want |
9072 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9073 | nop | |
9074 | <op> $treg,0($at) | |
9075 | <op> $treg+1,4($at) | |
9076 | Otherwise we want | |
9077 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9078 | nop | |
9079 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9080 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9081 | If there is a base register we add it to $at before the | |
9082 | lwc1 instructions. If there is a constant we include it | |
9083 | in the lwc1 instructions. */ | |
9084 | used_at = 1; | |
9085 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
9086 | if (expr1.X_add_number < -0x8000 |
9087 | || expr1.X_add_number >= 0x8000 - 4) | |
9088 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9089 | load_got_offset (AT, &offset_expr); |
269137b2 | 9090 | load_delay_nop (); |
252b5132 | 9091 | if (breg != 0) |
67c0d1eb | 9092 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
9093 | |
9094 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9095 | nop. */ | |
9096 | hold_mips_optimize = mips_optimize; | |
9097 | mips_optimize = 2; | |
4d7206a2 | 9098 | |
beae10d5 | 9099 | /* Itbl support may require additional care here. */ |
4d7206a2 | 9100 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
9101 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
9102 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9103 | expr1.X_add_number += 4; |
67c0d1eb RS |
9104 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
9105 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9106 | relax_switch (); |
67c0d1eb RS |
9107 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9108 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9109 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
9110 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9111 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9112 | relax_end (); |
252b5132 | 9113 | |
4d7206a2 | 9114 | mips_optimize = hold_mips_optimize; |
252b5132 | 9115 | } |
0a44bf69 | 9116 | else if (mips_big_got) |
252b5132 | 9117 | { |
67c0d1eb | 9118 | int gpdelay; |
252b5132 RH |
9119 | |
9120 | /* If this is a reference to an external symbol, we want | |
9121 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9122 | addu $at,$at,$gp | |
9123 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
9124 | nop | |
9125 | <op> $treg,0($at) | |
9126 | <op> $treg+1,4($at) | |
9127 | Otherwise we want | |
9128 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9129 | nop | |
9130 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9131 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9132 | If there is a base register we add it to $at before the | |
9133 | lwc1 instructions. If there is a constant we include it | |
9134 | in the lwc1 instructions. */ | |
9135 | used_at = 1; | |
9136 | expr1.X_add_number = offset_expr.X_add_number; | |
9137 | offset_expr.X_add_number = 0; | |
9138 | if (expr1.X_add_number < -0x8000 | |
9139 | || expr1.X_add_number >= 0x8000 - 4) | |
9140 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9141 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9142 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9143 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
9144 | AT, BFD_RELOC_MIPS_GOT_HI16); |
9145 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 9146 | AT, AT, mips_gp_register); |
67c0d1eb | 9147 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 9148 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 9149 | load_delay_nop (); |
252b5132 | 9150 | if (breg != 0) |
67c0d1eb | 9151 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9152 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9153 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9154 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9155 | expr1.X_add_number += 4; |
9156 | ||
9157 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9158 | nop. */ | |
9159 | hold_mips_optimize = mips_optimize; | |
9160 | mips_optimize = 2; | |
beae10d5 | 9161 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9162 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9163 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9164 | mips_optimize = hold_mips_optimize; |
9165 | expr1.X_add_number -= 4; | |
9166 | ||
4d7206a2 RS |
9167 | relax_switch (); |
9168 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
9169 | if (gpdelay) |
9170 | macro_build (NULL, "nop", ""); | |
9171 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
9172 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9173 | load_delay_nop (); |
252b5132 | 9174 | if (breg != 0) |
67c0d1eb | 9175 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9176 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9177 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9178 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9179 | offset_expr.X_add_number += 4; |
252b5132 RH |
9180 | |
9181 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9182 | nop. */ | |
9183 | hold_mips_optimize = mips_optimize; | |
9184 | mips_optimize = 2; | |
beae10d5 | 9185 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9186 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9187 | BFD_RELOC_LO16, AT); | |
252b5132 | 9188 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 9189 | relax_end (); |
252b5132 | 9190 | } |
252b5132 RH |
9191 | else |
9192 | abort (); | |
9193 | ||
252b5132 RH |
9194 | break; |
9195 | ||
9196 | case M_LD_OB: | |
704897fb | 9197 | s = HAVE_64BIT_GPRS ? "ld" : "lw"; |
252b5132 RH |
9198 | goto sd_ob; |
9199 | case M_SD_OB: | |
704897fb | 9200 | s = HAVE_64BIT_GPRS ? "sd" : "sw"; |
252b5132 | 9201 | sd_ob: |
4614d845 MR |
9202 | macro_build (&offset_expr, s, "t,o(b)", treg, |
9203 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
9204 | breg); | |
704897fb MR |
9205 | if (!HAVE_64BIT_GPRS) |
9206 | { | |
9207 | offset_expr.X_add_number += 4; | |
9208 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, | |
4614d845 MR |
9209 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], |
9210 | breg); | |
704897fb | 9211 | } |
8fc2e39e | 9212 | break; |
252b5132 | 9213 | |
dd6a37e7 AP |
9214 | |
9215 | case M_SAA_AB: | |
9216 | ab = 1; | |
9217 | case M_SAA_OB: | |
9218 | s = "saa"; | |
9219 | off0 = 1; | |
9220 | fmt = "t,(b)"; | |
9221 | goto ld_st; | |
9222 | case M_SAAD_AB: | |
9223 | ab = 1; | |
9224 | case M_SAAD_OB: | |
9225 | s = "saad"; | |
9226 | off0 = 1; | |
9227 | fmt = "t,(b)"; | |
9228 | goto ld_st; | |
9229 | ||
252b5132 RH |
9230 | /* New code added to support COPZ instructions. |
9231 | This code builds table entries out of the macros in mip_opcodes. | |
9232 | R4000 uses interlocks to handle coproc delays. | |
9233 | Other chips (like the R3000) require nops to be inserted for delays. | |
9234 | ||
f72c8c98 | 9235 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
9236 | In order to fill delay slots for non-interlocked chips, |
9237 | we must have a way to specify delays based on the coprocessor. | |
9238 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
9239 | What are the side-effects of the cop instruction? | |
9240 | What cache support might we have and what are its effects? | |
9241 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 9242 | What registers are read/set/modified? |
252b5132 RH |
9243 | |
9244 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 9245 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
9246 | |
9247 | case M_COP0: | |
9248 | s = "c0"; | |
9249 | goto copz; | |
9250 | case M_COP1: | |
9251 | s = "c1"; | |
9252 | goto copz; | |
9253 | case M_COP2: | |
9254 | s = "c2"; | |
9255 | goto copz; | |
9256 | case M_COP3: | |
9257 | s = "c3"; | |
9258 | copz: | |
df58fc94 | 9259 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
9260 | /* For now we just do C (same as Cz). The parameter will be |
9261 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 9262 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 9263 | break; |
252b5132 | 9264 | |
ea1fb5dc | 9265 | case M_MOVE: |
67c0d1eb | 9266 | move_register (dreg, sreg); |
8fc2e39e | 9267 | break; |
ea1fb5dc | 9268 | |
252b5132 RH |
9269 | case M_DMUL: |
9270 | dbl = 1; | |
9271 | case M_MUL: | |
67c0d1eb | 9272 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
df58fc94 | 9273 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
8fc2e39e | 9274 | break; |
252b5132 RH |
9275 | |
9276 | case M_DMUL_I: | |
9277 | dbl = 1; | |
9278 | case M_MUL_I: | |
9279 | /* The MIPS assembler some times generates shifts and adds. I'm | |
9280 | not trying to be that fancy. GCC should do this for us | |
9281 | anyway. */ | |
8fc2e39e | 9282 | used_at = 1; |
67c0d1eb RS |
9283 | load_register (AT, &imm_expr, dbl); |
9284 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
df58fc94 | 9285 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9286 | break; |
9287 | ||
9288 | case M_DMULO_I: | |
9289 | dbl = 1; | |
9290 | case M_MULO_I: | |
9291 | imm = 1; | |
9292 | goto do_mulo; | |
9293 | ||
9294 | case M_DMULO: | |
9295 | dbl = 1; | |
9296 | case M_MULO: | |
9297 | do_mulo: | |
7d10b47d | 9298 | start_noreorder (); |
8fc2e39e | 9299 | used_at = 1; |
252b5132 | 9300 | if (imm) |
67c0d1eb RS |
9301 | load_register (AT, &imm_expr, dbl); |
9302 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
df58fc94 RS |
9303 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
9304 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA); | |
9305 | macro_build (NULL, "mfhi", MFHL_FMT, AT); | |
252b5132 | 9306 | if (mips_trap) |
df58fc94 | 9307 | macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6); |
252b5132 RH |
9308 | else |
9309 | { | |
df58fc94 RS |
9310 | if (mips_opts.micromips) |
9311 | micromips_label_expr (&label_expr); | |
9312 | else | |
9313 | label_expr.X_add_number = 8; | |
9314 | macro_build (&label_expr, "beq", "s,t,p", dreg, AT); | |
a605d2b3 | 9315 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9316 | macro_build (NULL, "break", BRK_FMT, 6); |
9317 | if (mips_opts.micromips) | |
9318 | micromips_add_label (); | |
252b5132 | 9319 | } |
7d10b47d | 9320 | end_noreorder (); |
df58fc94 | 9321 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9322 | break; |
9323 | ||
9324 | case M_DMULOU_I: | |
9325 | dbl = 1; | |
9326 | case M_MULOU_I: | |
9327 | imm = 1; | |
9328 | goto do_mulou; | |
9329 | ||
9330 | case M_DMULOU: | |
9331 | dbl = 1; | |
9332 | case M_MULOU: | |
9333 | do_mulou: | |
7d10b47d | 9334 | start_noreorder (); |
8fc2e39e | 9335 | used_at = 1; |
252b5132 | 9336 | if (imm) |
67c0d1eb RS |
9337 | load_register (AT, &imm_expr, dbl); |
9338 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 9339 | sreg, imm ? AT : treg); |
df58fc94 RS |
9340 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
9341 | macro_build (NULL, "mflo", MFHL_FMT, dreg); | |
252b5132 | 9342 | if (mips_trap) |
df58fc94 | 9343 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
9344 | else |
9345 | { | |
df58fc94 RS |
9346 | if (mips_opts.micromips) |
9347 | micromips_label_expr (&label_expr); | |
9348 | else | |
9349 | label_expr.X_add_number = 8; | |
9350 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 9351 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9352 | macro_build (NULL, "break", BRK_FMT, 6); |
9353 | if (mips_opts.micromips) | |
9354 | micromips_add_label (); | |
252b5132 | 9355 | } |
7d10b47d | 9356 | end_noreorder (); |
252b5132 RH |
9357 | break; |
9358 | ||
771c7ce4 | 9359 | case M_DROL: |
fef14a42 | 9360 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9361 | { |
9362 | if (dreg == sreg) | |
9363 | { | |
9364 | tempreg = AT; | |
9365 | used_at = 1; | |
9366 | } | |
9367 | else | |
9368 | { | |
9369 | tempreg = dreg; | |
82dd0097 | 9370 | } |
67c0d1eb RS |
9371 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
9372 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9373 | break; |
82dd0097 | 9374 | } |
8fc2e39e | 9375 | used_at = 1; |
c80c840e | 9376 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9377 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
9378 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
9379 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
9380 | break; |
9381 | ||
252b5132 | 9382 | case M_ROL: |
fef14a42 | 9383 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
9384 | { |
9385 | if (dreg == sreg) | |
9386 | { | |
9387 | tempreg = AT; | |
9388 | used_at = 1; | |
9389 | } | |
9390 | else | |
9391 | { | |
9392 | tempreg = dreg; | |
82dd0097 | 9393 | } |
67c0d1eb RS |
9394 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
9395 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9396 | break; |
82dd0097 | 9397 | } |
8fc2e39e | 9398 | used_at = 1; |
c80c840e | 9399 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9400 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
9401 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
9402 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9403 | break; |
9404 | ||
771c7ce4 TS |
9405 | case M_DROL_I: |
9406 | { | |
9407 | unsigned int rot; | |
91d6fa6a NC |
9408 | char *l; |
9409 | char *rr; | |
771c7ce4 TS |
9410 | |
9411 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9412 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9413 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9414 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
9415 | { |
9416 | rot = (64 - rot) & 0x3f; | |
9417 | if (rot >= 32) | |
df58fc94 | 9418 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
60b63b72 | 9419 | else |
df58fc94 | 9420 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9421 | break; |
60b63b72 | 9422 | } |
483fc7cd | 9423 | if (rot == 0) |
483fc7cd | 9424 | { |
df58fc94 | 9425 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9426 | break; |
483fc7cd | 9427 | } |
82dd0097 | 9428 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 9429 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 9430 | rot &= 0x1f; |
8fc2e39e | 9431 | used_at = 1; |
df58fc94 RS |
9432 | macro_build (NULL, l, SHFT_FMT, AT, sreg, rot); |
9433 | macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9434 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9435 | } |
9436 | break; | |
9437 | ||
252b5132 | 9438 | case M_ROL_I: |
771c7ce4 TS |
9439 | { |
9440 | unsigned int rot; | |
9441 | ||
9442 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9443 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9444 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9445 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 9446 | { |
df58fc94 | 9447 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 9448 | break; |
60b63b72 | 9449 | } |
483fc7cd | 9450 | if (rot == 0) |
483fc7cd | 9451 | { |
df58fc94 | 9452 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9453 | break; |
483fc7cd | 9454 | } |
8fc2e39e | 9455 | used_at = 1; |
df58fc94 RS |
9456 | macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot); |
9457 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9458 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9459 | } |
9460 | break; | |
9461 | ||
9462 | case M_DROR: | |
fef14a42 | 9463 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 9464 | { |
67c0d1eb | 9465 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9466 | break; |
82dd0097 | 9467 | } |
8fc2e39e | 9468 | used_at = 1; |
c80c840e | 9469 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9470 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
9471 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
9472 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9473 | break; |
9474 | ||
9475 | case M_ROR: | |
fef14a42 | 9476 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9477 | { |
67c0d1eb | 9478 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9479 | break; |
82dd0097 | 9480 | } |
8fc2e39e | 9481 | used_at = 1; |
c80c840e | 9482 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9483 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
9484 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
9485 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9486 | break; |
9487 | ||
771c7ce4 TS |
9488 | case M_DROR_I: |
9489 | { | |
9490 | unsigned int rot; | |
91d6fa6a NC |
9491 | char *l; |
9492 | char *rr; | |
771c7ce4 TS |
9493 | |
9494 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9495 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9496 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9497 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9498 | { |
9499 | if (rot >= 32) | |
df58fc94 | 9500 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
82dd0097 | 9501 | else |
df58fc94 | 9502 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9503 | break; |
82dd0097 | 9504 | } |
483fc7cd | 9505 | if (rot == 0) |
483fc7cd | 9506 | { |
df58fc94 | 9507 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9508 | break; |
483fc7cd | 9509 | } |
91d6fa6a | 9510 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
9511 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
9512 | rot &= 0x1f; | |
8fc2e39e | 9513 | used_at = 1; |
df58fc94 RS |
9514 | macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot); |
9515 | macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9516 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9517 | } |
9518 | break; | |
9519 | ||
252b5132 | 9520 | case M_ROR_I: |
771c7ce4 TS |
9521 | { |
9522 | unsigned int rot; | |
9523 | ||
9524 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9525 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9526 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9527 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9528 | { |
df58fc94 | 9529 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9530 | break; |
82dd0097 | 9531 | } |
483fc7cd | 9532 | if (rot == 0) |
483fc7cd | 9533 | { |
df58fc94 | 9534 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9535 | break; |
483fc7cd | 9536 | } |
8fc2e39e | 9537 | used_at = 1; |
df58fc94 RS |
9538 | macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot); |
9539 | macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9540 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 | 9541 | } |
252b5132 RH |
9542 | break; |
9543 | ||
252b5132 RH |
9544 | case M_SEQ: |
9545 | if (sreg == 0) | |
67c0d1eb | 9546 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 9547 | else if (treg == 0) |
67c0d1eb | 9548 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9549 | else |
9550 | { | |
67c0d1eb RS |
9551 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9552 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 9553 | } |
8fc2e39e | 9554 | break; |
252b5132 RH |
9555 | |
9556 | case M_SEQ_I: | |
9557 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9558 | { | |
67c0d1eb | 9559 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9560 | break; |
252b5132 RH |
9561 | } |
9562 | if (sreg == 0) | |
9563 | { | |
9564 | as_warn (_("Instruction %s: result is always false"), | |
9565 | ip->insn_mo->name); | |
67c0d1eb | 9566 | move_register (dreg, 0); |
8fc2e39e | 9567 | break; |
252b5132 | 9568 | } |
dd3cbb7e NC |
9569 | if (CPU_HAS_SEQ (mips_opts.arch) |
9570 | && -512 <= imm_expr.X_add_number | |
9571 | && imm_expr.X_add_number < 512) | |
9572 | { | |
9573 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9574 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9575 | break; |
9576 | } | |
252b5132 RH |
9577 | if (imm_expr.X_op == O_constant |
9578 | && imm_expr.X_add_number >= 0 | |
9579 | && imm_expr.X_add_number < 0x10000) | |
9580 | { | |
67c0d1eb | 9581 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9582 | } |
9583 | else if (imm_expr.X_op == O_constant | |
9584 | && imm_expr.X_add_number > -0x8000 | |
9585 | && imm_expr.X_add_number < 0) | |
9586 | { | |
9587 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9588 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9589 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9590 | } |
dd3cbb7e NC |
9591 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9592 | { | |
9593 | used_at = 1; | |
9594 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9595 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
9596 | break; | |
9597 | } | |
252b5132 RH |
9598 | else |
9599 | { | |
67c0d1eb RS |
9600 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9601 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9602 | used_at = 1; |
9603 | } | |
67c0d1eb | 9604 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9605 | break; |
252b5132 RH |
9606 | |
9607 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
9608 | s = "slt"; | |
9609 | goto sge; | |
9610 | case M_SGEU: | |
9611 | s = "sltu"; | |
9612 | sge: | |
67c0d1eb RS |
9613 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
9614 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9615 | break; |
252b5132 RH |
9616 | |
9617 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
9618 | case M_SGEU_I: | |
9619 | if (imm_expr.X_op == O_constant | |
9620 | && imm_expr.X_add_number >= -0x8000 | |
9621 | && imm_expr.X_add_number < 0x8000) | |
9622 | { | |
67c0d1eb RS |
9623 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
9624 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
9625 | } |
9626 | else | |
9627 | { | |
67c0d1eb RS |
9628 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9629 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
9630 | dreg, sreg, AT); | |
252b5132 RH |
9631 | used_at = 1; |
9632 | } | |
67c0d1eb | 9633 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9634 | break; |
252b5132 RH |
9635 | |
9636 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
9637 | s = "slt"; | |
9638 | goto sgt; | |
9639 | case M_SGTU: | |
9640 | s = "sltu"; | |
9641 | sgt: | |
67c0d1eb | 9642 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 9643 | break; |
252b5132 RH |
9644 | |
9645 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
9646 | s = "slt"; | |
9647 | goto sgti; | |
9648 | case M_SGTU_I: | |
9649 | s = "sltu"; | |
9650 | sgti: | |
8fc2e39e | 9651 | used_at = 1; |
67c0d1eb RS |
9652 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9653 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
9654 | break; |
9655 | ||
2396cfb9 | 9656 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
9657 | s = "slt"; |
9658 | goto sle; | |
9659 | case M_SLEU: | |
9660 | s = "sltu"; | |
9661 | sle: | |
67c0d1eb RS |
9662 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
9663 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9664 | break; |
252b5132 | 9665 | |
2396cfb9 | 9666 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
9667 | s = "slt"; |
9668 | goto slei; | |
9669 | case M_SLEU_I: | |
9670 | s = "sltu"; | |
9671 | slei: | |
8fc2e39e | 9672 | used_at = 1; |
67c0d1eb RS |
9673 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9674 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
9675 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
9676 | break; |
9677 | ||
9678 | case M_SLT_I: | |
9679 | if (imm_expr.X_op == O_constant | |
9680 | && imm_expr.X_add_number >= -0x8000 | |
9681 | && imm_expr.X_add_number < 0x8000) | |
9682 | { | |
67c0d1eb | 9683 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9684 | break; |
252b5132 | 9685 | } |
8fc2e39e | 9686 | used_at = 1; |
67c0d1eb RS |
9687 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9688 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9689 | break; |
9690 | ||
9691 | case M_SLTU_I: | |
9692 | if (imm_expr.X_op == O_constant | |
9693 | && imm_expr.X_add_number >= -0x8000 | |
9694 | && imm_expr.X_add_number < 0x8000) | |
9695 | { | |
67c0d1eb | 9696 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 9697 | BFD_RELOC_LO16); |
8fc2e39e | 9698 | break; |
252b5132 | 9699 | } |
8fc2e39e | 9700 | used_at = 1; |
67c0d1eb RS |
9701 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9702 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9703 | break; |
9704 | ||
9705 | case M_SNE: | |
9706 | if (sreg == 0) | |
67c0d1eb | 9707 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 9708 | else if (treg == 0) |
67c0d1eb | 9709 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
9710 | else |
9711 | { | |
67c0d1eb RS |
9712 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9713 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 9714 | } |
8fc2e39e | 9715 | break; |
252b5132 RH |
9716 | |
9717 | case M_SNE_I: | |
9718 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9719 | { | |
67c0d1eb | 9720 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 9721 | break; |
252b5132 RH |
9722 | } |
9723 | if (sreg == 0) | |
9724 | { | |
9725 | as_warn (_("Instruction %s: result is always true"), | |
9726 | ip->insn_mo->name); | |
67c0d1eb RS |
9727 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
9728 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 9729 | break; |
252b5132 | 9730 | } |
dd3cbb7e NC |
9731 | if (CPU_HAS_SEQ (mips_opts.arch) |
9732 | && -512 <= imm_expr.X_add_number | |
9733 | && imm_expr.X_add_number < 512) | |
9734 | { | |
9735 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9736 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9737 | break; |
9738 | } | |
252b5132 RH |
9739 | if (imm_expr.X_op == O_constant |
9740 | && imm_expr.X_add_number >= 0 | |
9741 | && imm_expr.X_add_number < 0x10000) | |
9742 | { | |
67c0d1eb | 9743 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9744 | } |
9745 | else if (imm_expr.X_op == O_constant | |
9746 | && imm_expr.X_add_number > -0x8000 | |
9747 | && imm_expr.X_add_number < 0) | |
9748 | { | |
9749 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9750 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9751 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9752 | } |
dd3cbb7e NC |
9753 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9754 | { | |
9755 | used_at = 1; | |
9756 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9757 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
9758 | break; | |
9759 | } | |
252b5132 RH |
9760 | else |
9761 | { | |
67c0d1eb RS |
9762 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9763 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9764 | used_at = 1; |
9765 | } | |
67c0d1eb | 9766 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 9767 | break; |
252b5132 | 9768 | |
df58fc94 RS |
9769 | case M_SUB_I: |
9770 | s = "addi"; | |
9771 | s2 = "sub"; | |
9772 | goto do_subi; | |
9773 | case M_SUBU_I: | |
9774 | s = "addiu"; | |
9775 | s2 = "subu"; | |
9776 | goto do_subi; | |
252b5132 RH |
9777 | case M_DSUB_I: |
9778 | dbl = 1; | |
df58fc94 RS |
9779 | s = "daddi"; |
9780 | s2 = "dsub"; | |
9781 | if (!mips_opts.micromips) | |
9782 | goto do_subi; | |
252b5132 | 9783 | if (imm_expr.X_op == O_constant |
df58fc94 RS |
9784 | && imm_expr.X_add_number > -0x200 |
9785 | && imm_expr.X_add_number <= 0x200) | |
252b5132 | 9786 | { |
df58fc94 | 9787 | macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number); |
8fc2e39e | 9788 | break; |
252b5132 | 9789 | } |
df58fc94 | 9790 | goto do_subi_i; |
252b5132 RH |
9791 | case M_DSUBU_I: |
9792 | dbl = 1; | |
df58fc94 RS |
9793 | s = "daddiu"; |
9794 | s2 = "dsubu"; | |
9795 | do_subi: | |
252b5132 RH |
9796 | if (imm_expr.X_op == O_constant |
9797 | && imm_expr.X_add_number > -0x8000 | |
9798 | && imm_expr.X_add_number <= 0x8000) | |
9799 | { | |
9800 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
df58fc94 | 9801 | macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9802 | break; |
252b5132 | 9803 | } |
df58fc94 | 9804 | do_subi_i: |
8fc2e39e | 9805 | used_at = 1; |
67c0d1eb | 9806 | load_register (AT, &imm_expr, dbl); |
df58fc94 | 9807 | macro_build (NULL, s2, "d,v,t", dreg, sreg, AT); |
252b5132 RH |
9808 | break; |
9809 | ||
9810 | case M_TEQ_I: | |
9811 | s = "teq"; | |
9812 | goto trap; | |
9813 | case M_TGE_I: | |
9814 | s = "tge"; | |
9815 | goto trap; | |
9816 | case M_TGEU_I: | |
9817 | s = "tgeu"; | |
9818 | goto trap; | |
9819 | case M_TLT_I: | |
9820 | s = "tlt"; | |
9821 | goto trap; | |
9822 | case M_TLTU_I: | |
9823 | s = "tltu"; | |
9824 | goto trap; | |
9825 | case M_TNE_I: | |
9826 | s = "tne"; | |
9827 | trap: | |
8fc2e39e | 9828 | used_at = 1; |
67c0d1eb RS |
9829 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9830 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
9831 | break; |
9832 | ||
252b5132 | 9833 | case M_TRUNCWS: |
43841e91 | 9834 | case M_TRUNCWD: |
df58fc94 | 9835 | gas_assert (!mips_opts.micromips); |
9c2799c2 | 9836 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 9837 | used_at = 1; |
252b5132 RH |
9838 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
9839 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
9840 | ||
9841 | /* | |
9842 | * Is the double cfc1 instruction a bug in the mips assembler; | |
9843 | * or is there a reason for it? | |
9844 | */ | |
7d10b47d | 9845 | start_noreorder (); |
67c0d1eb RS |
9846 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
9847 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
9848 | macro_build (NULL, "nop", ""); | |
252b5132 | 9849 | expr1.X_add_number = 3; |
67c0d1eb | 9850 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 9851 | expr1.X_add_number = 2; |
67c0d1eb RS |
9852 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
9853 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
9854 | macro_build (NULL, "nop", ""); | |
9855 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
9856 | dreg, sreg); | |
9857 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
9858 | macro_build (NULL, "nop", ""); | |
7d10b47d | 9859 | end_noreorder (); |
252b5132 RH |
9860 | break; |
9861 | ||
df58fc94 RS |
9862 | case M_ULH_A: |
9863 | ab = 1; | |
252b5132 RH |
9864 | case M_ULH: |
9865 | s = "lb"; | |
df58fc94 RS |
9866 | s2 = "lbu"; |
9867 | off = 1; | |
9868 | goto uld_st; | |
9869 | case M_ULHU_A: | |
9870 | ab = 1; | |
252b5132 RH |
9871 | case M_ULHU: |
9872 | s = "lbu"; | |
df58fc94 RS |
9873 | s2 = "lbu"; |
9874 | off = 1; | |
9875 | goto uld_st; | |
9876 | case M_ULW_A: | |
9877 | ab = 1; | |
9878 | case M_ULW: | |
9879 | s = "lwl"; | |
9880 | s2 = "lwr"; | |
9881 | off12 = mips_opts.micromips; | |
9882 | off = 3; | |
9883 | goto uld_st; | |
9884 | case M_ULD_A: | |
9885 | ab = 1; | |
252b5132 RH |
9886 | case M_ULD: |
9887 | s = "ldl"; | |
9888 | s2 = "ldr"; | |
df58fc94 | 9889 | off12 = mips_opts.micromips; |
252b5132 | 9890 | off = 7; |
df58fc94 RS |
9891 | goto uld_st; |
9892 | case M_USH_A: | |
9893 | ab = 1; | |
9894 | case M_USH: | |
9895 | s = "sb"; | |
9896 | s2 = "sb"; | |
9897 | off = 1; | |
9898 | ust = 1; | |
9899 | goto uld_st; | |
9900 | case M_USW_A: | |
9901 | ab = 1; | |
9902 | case M_USW: | |
9903 | s = "swl"; | |
9904 | s2 = "swr"; | |
9905 | off12 = mips_opts.micromips; | |
252b5132 | 9906 | off = 3; |
df58fc94 RS |
9907 | ust = 1; |
9908 | goto uld_st; | |
9909 | case M_USD_A: | |
9910 | ab = 1; | |
9911 | case M_USD: | |
9912 | s = "sdl"; | |
9913 | s2 = "sdr"; | |
9914 | off12 = mips_opts.micromips; | |
9915 | off = 7; | |
9916 | ust = 1; | |
9917 | ||
9918 | uld_st: | |
9919 | if (!ab && offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 9920 | as_bad (_("Operand overflow")); |
df58fc94 RS |
9921 | |
9922 | ep = &offset_expr; | |
9923 | expr1.X_add_number = 0; | |
9924 | if (ab) | |
9925 | { | |
9926 | used_at = 1; | |
9927 | tempreg = AT; | |
9928 | load_address (tempreg, ep, &used_at); | |
9929 | if (breg != 0) | |
9930 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
9931 | tempreg, tempreg, breg); | |
9932 | breg = tempreg; | |
9933 | tempreg = treg; | |
9934 | ep = &expr1; | |
9935 | } | |
9936 | else if (off12 | |
9937 | && (offset_expr.X_op != O_constant | |
9938 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number) | |
9939 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off))) | |
9940 | { | |
9941 | used_at = 1; | |
9942 | tempreg = AT; | |
9943 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, | |
9944 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
9945 | breg = tempreg; | |
9946 | tempreg = treg; | |
9947 | ep = &expr1; | |
9948 | } | |
9949 | else if (!ust && treg == breg) | |
8fc2e39e TS |
9950 | { |
9951 | used_at = 1; | |
9952 | tempreg = AT; | |
9953 | } | |
252b5132 | 9954 | else |
df58fc94 | 9955 | tempreg = treg; |
af22f5b2 | 9956 | |
df58fc94 RS |
9957 | if (off == 1) |
9958 | goto ulh_sh; | |
252b5132 | 9959 | |
90ecf173 | 9960 | if (!target_big_endian) |
df58fc94 RS |
9961 | ep->X_add_number += off; |
9962 | if (!off12) | |
9963 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 9964 | else |
df58fc94 RS |
9965 | macro_build (NULL, s, "t,~(b)", |
9966 | tempreg, (unsigned long) ep->X_add_number, breg); | |
9967 | ||
90ecf173 | 9968 | if (!target_big_endian) |
df58fc94 | 9969 | ep->X_add_number -= off; |
252b5132 | 9970 | else |
df58fc94 RS |
9971 | ep->X_add_number += off; |
9972 | if (!off12) | |
9973 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
9974 | else | |
9975 | macro_build (NULL, s2, "t,~(b)", | |
9976 | tempreg, (unsigned long) ep->X_add_number, breg); | |
252b5132 | 9977 | |
df58fc94 RS |
9978 | /* If necessary, move the result in tempreg to the final destination. */ |
9979 | if (!ust && treg != tempreg) | |
9980 | { | |
9981 | /* Protect second load's delay slot. */ | |
9982 | load_delay_nop (); | |
9983 | move_register (treg, tempreg); | |
9984 | } | |
8fc2e39e | 9985 | break; |
252b5132 | 9986 | |
df58fc94 | 9987 | ulh_sh: |
d6bc6245 | 9988 | used_at = 1; |
df58fc94 RS |
9989 | if (target_big_endian == ust) |
9990 | ep->X_add_number += off; | |
9991 | tempreg = ust || ab ? treg : AT; | |
9992 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
9993 | ||
9994 | /* For halfword transfers we need a temporary register to shuffle | |
9995 | bytes. Unfortunately for M_USH_A we have none available before | |
9996 | the next store as AT holds the base address. We deal with this | |
9997 | case by clobbering TREG and then restoring it as with ULH. */ | |
9998 | tempreg = ust == ab ? treg : AT; | |
9999 | if (ust) | |
10000 | macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8); | |
10001 | ||
10002 | if (target_big_endian == ust) | |
10003 | ep->X_add_number -= off; | |
252b5132 | 10004 | else |
df58fc94 RS |
10005 | ep->X_add_number += off; |
10006 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 10007 | |
df58fc94 RS |
10008 | /* For M_USH_A re-retrieve the LSB. */ |
10009 | if (ust && ab) | |
10010 | { | |
10011 | if (target_big_endian) | |
10012 | ep->X_add_number += off; | |
10013 | else | |
10014 | ep->X_add_number -= off; | |
10015 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); | |
10016 | } | |
10017 | /* For ULH and M_USH_A OR the LSB in. */ | |
10018 | if (!ust || ab) | |
10019 | { | |
10020 | tempreg = !ab ? AT : treg; | |
10021 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); | |
10022 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
10023 | } | |
252b5132 RH |
10024 | break; |
10025 | ||
10026 | default: | |
10027 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 10028 | are added dynamically. */ |
252b5132 RH |
10029 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
10030 | break; | |
10031 | } | |
741fe287 | 10032 | if (!mips_opts.at && used_at) |
8fc2e39e | 10033 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
10034 | } |
10035 | ||
10036 | /* Implement macros in mips16 mode. */ | |
10037 | ||
10038 | static void | |
17a2f251 | 10039 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
10040 | { |
10041 | int mask; | |
10042 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
10043 | expressionS expr1; |
10044 | int dbl; | |
10045 | const char *s, *s2, *s3; | |
10046 | ||
10047 | mask = ip->insn_mo->mask; | |
10048 | ||
bf12938e RS |
10049 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
10050 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
10051 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 10052 | |
252b5132 RH |
10053 | expr1.X_op = O_constant; |
10054 | expr1.X_op_symbol = NULL; | |
10055 | expr1.X_add_symbol = NULL; | |
10056 | expr1.X_add_number = 1; | |
10057 | ||
10058 | dbl = 0; | |
10059 | ||
10060 | switch (mask) | |
10061 | { | |
10062 | default: | |
10063 | internalError (); | |
10064 | ||
10065 | case M_DDIV_3: | |
10066 | dbl = 1; | |
10067 | case M_DIV_3: | |
10068 | s = "mflo"; | |
10069 | goto do_div3; | |
10070 | case M_DREM_3: | |
10071 | dbl = 1; | |
10072 | case M_REM_3: | |
10073 | s = "mfhi"; | |
10074 | do_div3: | |
7d10b47d | 10075 | start_noreorder (); |
67c0d1eb | 10076 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 10077 | expr1.X_add_number = 2; |
67c0d1eb RS |
10078 | macro_build (&expr1, "bnez", "x,p", yreg); |
10079 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 10080 | |
252b5132 RH |
10081 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
10082 | since that causes an overflow. We should do that as well, | |
10083 | but I don't see how to do the comparisons without a temporary | |
10084 | register. */ | |
7d10b47d | 10085 | end_noreorder (); |
67c0d1eb | 10086 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
10087 | break; |
10088 | ||
10089 | case M_DIVU_3: | |
10090 | s = "divu"; | |
10091 | s2 = "mflo"; | |
10092 | goto do_divu3; | |
10093 | case M_REMU_3: | |
10094 | s = "divu"; | |
10095 | s2 = "mfhi"; | |
10096 | goto do_divu3; | |
10097 | case M_DDIVU_3: | |
10098 | s = "ddivu"; | |
10099 | s2 = "mflo"; | |
10100 | goto do_divu3; | |
10101 | case M_DREMU_3: | |
10102 | s = "ddivu"; | |
10103 | s2 = "mfhi"; | |
10104 | do_divu3: | |
7d10b47d | 10105 | start_noreorder (); |
67c0d1eb | 10106 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 10107 | expr1.X_add_number = 2; |
67c0d1eb RS |
10108 | macro_build (&expr1, "bnez", "x,p", yreg); |
10109 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 10110 | end_noreorder (); |
67c0d1eb | 10111 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
10112 | break; |
10113 | ||
10114 | case M_DMUL: | |
10115 | dbl = 1; | |
10116 | case M_MUL: | |
67c0d1eb RS |
10117 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
10118 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 10119 | break; |
252b5132 RH |
10120 | |
10121 | case M_DSUBU_I: | |
10122 | dbl = 1; | |
10123 | goto do_subu; | |
10124 | case M_SUBU_I: | |
10125 | do_subu: | |
10126 | if (imm_expr.X_op != O_constant) | |
10127 | as_bad (_("Unsupported large constant")); | |
10128 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10129 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
10130 | break; |
10131 | ||
10132 | case M_SUBU_I_2: | |
10133 | if (imm_expr.X_op != O_constant) | |
10134 | as_bad (_("Unsupported large constant")); | |
10135 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10136 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
10137 | break; |
10138 | ||
10139 | case M_DSUBU_I_2: | |
10140 | if (imm_expr.X_op != O_constant) | |
10141 | as_bad (_("Unsupported large constant")); | |
10142 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10143 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
10144 | break; |
10145 | ||
10146 | case M_BEQ: | |
10147 | s = "cmp"; | |
10148 | s2 = "bteqz"; | |
10149 | goto do_branch; | |
10150 | case M_BNE: | |
10151 | s = "cmp"; | |
10152 | s2 = "btnez"; | |
10153 | goto do_branch; | |
10154 | case M_BLT: | |
10155 | s = "slt"; | |
10156 | s2 = "btnez"; | |
10157 | goto do_branch; | |
10158 | case M_BLTU: | |
10159 | s = "sltu"; | |
10160 | s2 = "btnez"; | |
10161 | goto do_branch; | |
10162 | case M_BLE: | |
10163 | s = "slt"; | |
10164 | s2 = "bteqz"; | |
10165 | goto do_reverse_branch; | |
10166 | case M_BLEU: | |
10167 | s = "sltu"; | |
10168 | s2 = "bteqz"; | |
10169 | goto do_reverse_branch; | |
10170 | case M_BGE: | |
10171 | s = "slt"; | |
10172 | s2 = "bteqz"; | |
10173 | goto do_branch; | |
10174 | case M_BGEU: | |
10175 | s = "sltu"; | |
10176 | s2 = "bteqz"; | |
10177 | goto do_branch; | |
10178 | case M_BGT: | |
10179 | s = "slt"; | |
10180 | s2 = "btnez"; | |
10181 | goto do_reverse_branch; | |
10182 | case M_BGTU: | |
10183 | s = "sltu"; | |
10184 | s2 = "btnez"; | |
10185 | ||
10186 | do_reverse_branch: | |
10187 | tmp = xreg; | |
10188 | xreg = yreg; | |
10189 | yreg = tmp; | |
10190 | ||
10191 | do_branch: | |
67c0d1eb RS |
10192 | macro_build (NULL, s, "x,y", xreg, yreg); |
10193 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10194 | break; |
10195 | ||
10196 | case M_BEQ_I: | |
10197 | s = "cmpi"; | |
10198 | s2 = "bteqz"; | |
10199 | s3 = "x,U"; | |
10200 | goto do_branch_i; | |
10201 | case M_BNE_I: | |
10202 | s = "cmpi"; | |
10203 | s2 = "btnez"; | |
10204 | s3 = "x,U"; | |
10205 | goto do_branch_i; | |
10206 | case M_BLT_I: | |
10207 | s = "slti"; | |
10208 | s2 = "btnez"; | |
10209 | s3 = "x,8"; | |
10210 | goto do_branch_i; | |
10211 | case M_BLTU_I: | |
10212 | s = "sltiu"; | |
10213 | s2 = "btnez"; | |
10214 | s3 = "x,8"; | |
10215 | goto do_branch_i; | |
10216 | case M_BLE_I: | |
10217 | s = "slti"; | |
10218 | s2 = "btnez"; | |
10219 | s3 = "x,8"; | |
10220 | goto do_addone_branch_i; | |
10221 | case M_BLEU_I: | |
10222 | s = "sltiu"; | |
10223 | s2 = "btnez"; | |
10224 | s3 = "x,8"; | |
10225 | goto do_addone_branch_i; | |
10226 | case M_BGE_I: | |
10227 | s = "slti"; | |
10228 | s2 = "bteqz"; | |
10229 | s3 = "x,8"; | |
10230 | goto do_branch_i; | |
10231 | case M_BGEU_I: | |
10232 | s = "sltiu"; | |
10233 | s2 = "bteqz"; | |
10234 | s3 = "x,8"; | |
10235 | goto do_branch_i; | |
10236 | case M_BGT_I: | |
10237 | s = "slti"; | |
10238 | s2 = "bteqz"; | |
10239 | s3 = "x,8"; | |
10240 | goto do_addone_branch_i; | |
10241 | case M_BGTU_I: | |
10242 | s = "sltiu"; | |
10243 | s2 = "bteqz"; | |
10244 | s3 = "x,8"; | |
10245 | ||
10246 | do_addone_branch_i: | |
10247 | if (imm_expr.X_op != O_constant) | |
10248 | as_bad (_("Unsupported large constant")); | |
10249 | ++imm_expr.X_add_number; | |
10250 | ||
10251 | do_branch_i: | |
67c0d1eb RS |
10252 | macro_build (&imm_expr, s, s3, xreg); |
10253 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10254 | break; |
10255 | ||
10256 | case M_ABS: | |
10257 | expr1.X_add_number = 0; | |
67c0d1eb | 10258 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 10259 | if (xreg != yreg) |
67c0d1eb | 10260 | move_register (xreg, yreg); |
252b5132 | 10261 | expr1.X_add_number = 2; |
67c0d1eb RS |
10262 | macro_build (&expr1, "bteqz", "p"); |
10263 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
10264 | } |
10265 | } | |
10266 | ||
10267 | /* For consistency checking, verify that all bits are specified either | |
10268 | by the match/mask part of the instruction definition, or by the | |
10269 | operand list. */ | |
10270 | static int | |
17a2f251 | 10271 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
10272 | { |
10273 | const char *p = opc->args; | |
10274 | char c; | |
10275 | unsigned long used_bits = opc->mask; | |
10276 | ||
10277 | if ((used_bits & opc->match) != opc->match) | |
10278 | { | |
10279 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
10280 | opc->name, opc->args); | |
10281 | return 0; | |
10282 | } | |
10283 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
10284 | while (*p) | |
10285 | switch (c = *p++) | |
10286 | { | |
10287 | case ',': break; | |
10288 | case '(': break; | |
10289 | case ')': break; | |
af7ee8bf CD |
10290 | case '+': |
10291 | switch (c = *p++) | |
10292 | { | |
9bcd4f99 TS |
10293 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
10294 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
10295 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
10296 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
10297 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10298 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10299 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
10300 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10301 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
10302 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10303 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10304 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10305 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10306 | case 'I': break; | |
ef2e4d86 CF |
10307 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
10308 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
10309 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
10310 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
10311 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
10312 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
10313 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 10314 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
10315 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
10316 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
10317 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
10318 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
10319 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
10320 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
10321 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
bb35fb24 | 10322 | |
af7ee8bf CD |
10323 | default: |
10324 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
10325 | c, opc->name, opc->args); | |
10326 | return 0; | |
10327 | } | |
10328 | break; | |
252b5132 RH |
10329 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10330 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
10331 | case 'A': break; | |
4372b673 | 10332 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
10333 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
10334 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
10335 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10336 | case 'F': break; | |
10337 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 10338 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 10339 | case 'I': break; |
e972090a | 10340 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 10341 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10342 | case 'L': break; |
10343 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
10344 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
10345 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
10346 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
10347 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10348 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
10349 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10350 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
10351 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10352 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
10353 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
10354 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10355 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10356 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
10357 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10358 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
10359 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
10360 | case 'f': break; | |
10361 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
10362 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10363 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10364 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
10365 | case 'l': break; | |
10366 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10367 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10368 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
10369 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10370 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10371 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10372 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10373 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10374 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10375 | case 'x': break; | |
10376 | case 'z': break; | |
10377 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
10378 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10379 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
10380 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
10381 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
10382 | case '[': break; | |
10383 | case ']': break; | |
620edafd | 10384 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 10385 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
10386 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
10387 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
10388 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
10389 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10390 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
10391 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
10392 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
10393 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
10394 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
10395 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
10396 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
10397 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
10398 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
10399 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
10400 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
dec0624d MR |
10401 | case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break; |
10402 | case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break; | |
ef2e4d86 | 10403 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10404 | default: |
10405 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
10406 | c, opc->name, opc->args); | |
10407 | return 0; | |
10408 | } | |
10409 | #undef USE_BITS | |
10410 | if (used_bits != 0xffffffff) | |
10411 | { | |
10412 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
10413 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
10414 | return 0; | |
10415 | } | |
10416 | return 1; | |
10417 | } | |
10418 | ||
df58fc94 RS |
10419 | /* For consistency checking, verify that the length implied matches the |
10420 | major opcode and that all bits are specified either by the match/mask | |
10421 | part of the instruction definition, or by the operand list. */ | |
10422 | ||
10423 | static int | |
10424 | validate_micromips_insn (const struct mips_opcode *opc) | |
10425 | { | |
10426 | unsigned long match = opc->match; | |
10427 | unsigned long mask = opc->mask; | |
10428 | const char *p = opc->args; | |
10429 | unsigned long insn_bits; | |
10430 | unsigned long used_bits; | |
10431 | unsigned long major; | |
10432 | unsigned int length; | |
10433 | char e; | |
10434 | char c; | |
10435 | ||
10436 | if ((mask & match) != match) | |
10437 | { | |
10438 | as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"), | |
10439 | opc->name, opc->args); | |
10440 | return 0; | |
10441 | } | |
10442 | length = micromips_insn_length (opc); | |
10443 | if (length != 2 && length != 4) | |
10444 | { | |
10445 | as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): " | |
10446 | "%s %s"), length, opc->name, opc->args); | |
10447 | return 0; | |
10448 | } | |
10449 | major = match >> (10 + 8 * (length - 2)); | |
10450 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
10451 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
10452 | { | |
10453 | as_bad (_("Internal error: bad microMIPS opcode " | |
10454 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); | |
10455 | return 0; | |
10456 | } | |
10457 | ||
10458 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
10459 | insn_bits = 1 << 4 * length; | |
10460 | insn_bits <<= 4 * length; | |
10461 | insn_bits -= 1; | |
10462 | used_bits = mask; | |
10463 | #define USE_BITS(field) \ | |
10464 | (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field) | |
10465 | while (*p) | |
10466 | switch (c = *p++) | |
10467 | { | |
10468 | case ',': break; | |
10469 | case '(': break; | |
10470 | case ')': break; | |
10471 | case '+': | |
10472 | e = c; | |
10473 | switch (c = *p++) | |
10474 | { | |
10475 | case 'A': USE_BITS (EXTLSB); break; | |
10476 | case 'B': USE_BITS (INSMSB); break; | |
10477 | case 'C': USE_BITS (EXTMSBD); break; | |
10478 | case 'D': USE_BITS (RS); USE_BITS (SEL); break; | |
10479 | case 'E': USE_BITS (EXTLSB); break; | |
10480 | case 'F': USE_BITS (INSMSB); break; | |
10481 | case 'G': USE_BITS (EXTMSBD); break; | |
10482 | case 'H': USE_BITS (EXTMSBD); break; | |
10483 | default: | |
10484 | as_bad (_("Internal error: bad mips opcode " | |
10485 | "(unknown extension operand type `%c%c'): %s %s"), | |
10486 | e, c, opc->name, opc->args); | |
10487 | return 0; | |
10488 | } | |
10489 | break; | |
10490 | case 'm': | |
10491 | e = c; | |
10492 | switch (c = *p++) | |
10493 | { | |
10494 | case 'A': USE_BITS (IMMA); break; | |
10495 | case 'B': USE_BITS (IMMB); break; | |
10496 | case 'C': USE_BITS (IMMC); break; | |
10497 | case 'D': USE_BITS (IMMD); break; | |
10498 | case 'E': USE_BITS (IMME); break; | |
10499 | case 'F': USE_BITS (IMMF); break; | |
10500 | case 'G': USE_BITS (IMMG); break; | |
10501 | case 'H': USE_BITS (IMMH); break; | |
10502 | case 'I': USE_BITS (IMMI); break; | |
10503 | case 'J': USE_BITS (IMMJ); break; | |
10504 | case 'L': USE_BITS (IMML); break; | |
10505 | case 'M': USE_BITS (IMMM); break; | |
10506 | case 'N': USE_BITS (IMMN); break; | |
10507 | case 'O': USE_BITS (IMMO); break; | |
10508 | case 'P': USE_BITS (IMMP); break; | |
10509 | case 'Q': USE_BITS (IMMQ); break; | |
10510 | case 'U': USE_BITS (IMMU); break; | |
10511 | case 'W': USE_BITS (IMMW); break; | |
10512 | case 'X': USE_BITS (IMMX); break; | |
10513 | case 'Y': USE_BITS (IMMY); break; | |
10514 | case 'Z': break; | |
10515 | case 'a': break; | |
10516 | case 'b': USE_BITS (MB); break; | |
10517 | case 'c': USE_BITS (MC); break; | |
10518 | case 'd': USE_BITS (MD); break; | |
10519 | case 'e': USE_BITS (ME); break; | |
10520 | case 'f': USE_BITS (MF); break; | |
10521 | case 'g': USE_BITS (MG); break; | |
10522 | case 'h': USE_BITS (MH); break; | |
10523 | case 'i': USE_BITS (MI); break; | |
10524 | case 'j': USE_BITS (MJ); break; | |
10525 | case 'l': USE_BITS (ML); break; | |
10526 | case 'm': USE_BITS (MM); break; | |
10527 | case 'n': USE_BITS (MN); break; | |
10528 | case 'p': USE_BITS (MP); break; | |
10529 | case 'q': USE_BITS (MQ); break; | |
10530 | case 'r': break; | |
10531 | case 's': break; | |
10532 | case 't': break; | |
10533 | case 'x': break; | |
10534 | case 'y': break; | |
10535 | case 'z': break; | |
10536 | default: | |
10537 | as_bad (_("Internal error: bad mips opcode " | |
10538 | "(unknown extension operand type `%c%c'): %s %s"), | |
10539 | e, c, opc->name, opc->args); | |
10540 | return 0; | |
10541 | } | |
10542 | break; | |
10543 | case '.': USE_BITS (OFFSET10); break; | |
10544 | case '1': USE_BITS (STYPE); break; | |
03f66e8a MR |
10545 | case '2': USE_BITS (BP); break; |
10546 | case '3': USE_BITS (SA3); break; | |
10547 | case '4': USE_BITS (SA4); break; | |
10548 | case '5': USE_BITS (IMM8); break; | |
10549 | case '6': USE_BITS (RS); break; | |
10550 | case '7': USE_BITS (DSPACC); break; | |
10551 | case '8': USE_BITS (WRDSP); break; | |
10552 | case '0': USE_BITS (DSPSFT); break; | |
df58fc94 RS |
10553 | case '<': USE_BITS (SHAMT); break; |
10554 | case '>': USE_BITS (SHAMT); break; | |
03f66e8a | 10555 | case '@': USE_BITS (IMM10); break; |
df58fc94 RS |
10556 | case 'B': USE_BITS (CODE10); break; |
10557 | case 'C': USE_BITS (COPZ); break; | |
10558 | case 'D': USE_BITS (FD); break; | |
10559 | case 'E': USE_BITS (RT); break; | |
10560 | case 'G': USE_BITS (RS); break; | |
444d75be | 10561 | case 'H': USE_BITS (SEL); break; |
df58fc94 RS |
10562 | case 'K': USE_BITS (RS); break; |
10563 | case 'M': USE_BITS (CCC); break; | |
10564 | case 'N': USE_BITS (BCC); break; | |
10565 | case 'R': USE_BITS (FR); break; | |
10566 | case 'S': USE_BITS (FS); break; | |
10567 | case 'T': USE_BITS (FT); break; | |
10568 | case 'V': USE_BITS (FS); break; | |
dec0624d | 10569 | case '\\': USE_BITS (3BITPOS); break; |
03f66e8a | 10570 | case '^': USE_BITS (RD); break; |
df58fc94 RS |
10571 | case 'a': USE_BITS (TARGET); break; |
10572 | case 'b': USE_BITS (RS); break; | |
10573 | case 'c': USE_BITS (CODE); break; | |
10574 | case 'd': USE_BITS (RD); break; | |
10575 | case 'h': USE_BITS (PREFX); break; | |
10576 | case 'i': USE_BITS (IMMEDIATE); break; | |
10577 | case 'j': USE_BITS (DELTA); break; | |
10578 | case 'k': USE_BITS (CACHE); break; | |
10579 | case 'n': USE_BITS (RT); break; | |
10580 | case 'o': USE_BITS (DELTA); break; | |
10581 | case 'p': USE_BITS (DELTA); break; | |
10582 | case 'q': USE_BITS (CODE2); break; | |
10583 | case 'r': USE_BITS (RS); break; | |
10584 | case 's': USE_BITS (RS); break; | |
10585 | case 't': USE_BITS (RT); break; | |
10586 | case 'u': USE_BITS (IMMEDIATE); break; | |
10587 | case 'v': USE_BITS (RS); break; | |
10588 | case 'w': USE_BITS (RT); break; | |
10589 | case 'y': USE_BITS (RS3); break; | |
10590 | case 'z': break; | |
10591 | case '|': USE_BITS (TRAP); break; | |
10592 | case '~': USE_BITS (OFFSET12); break; | |
10593 | default: | |
10594 | as_bad (_("Internal error: bad microMIPS opcode " | |
10595 | "(unknown operand type `%c'): %s %s"), | |
10596 | c, opc->name, opc->args); | |
10597 | return 0; | |
10598 | } | |
10599 | #undef USE_BITS | |
10600 | if (used_bits != insn_bits) | |
10601 | { | |
10602 | if (~used_bits & insn_bits) | |
10603 | as_bad (_("Internal error: bad microMIPS opcode " | |
10604 | "(bits 0x%lx undefined): %s %s"), | |
10605 | ~used_bits & insn_bits, opc->name, opc->args); | |
10606 | if (used_bits & ~insn_bits) | |
10607 | as_bad (_("Internal error: bad microMIPS opcode " | |
10608 | "(bits 0x%lx defined): %s %s"), | |
10609 | used_bits & ~insn_bits, opc->name, opc->args); | |
10610 | return 0; | |
10611 | } | |
10612 | return 1; | |
10613 | } | |
10614 | ||
9bcd4f99 TS |
10615 | /* UDI immediates. */ |
10616 | struct mips_immed { | |
10617 | char type; | |
10618 | unsigned int shift; | |
10619 | unsigned long mask; | |
10620 | const char * desc; | |
10621 | }; | |
10622 | ||
10623 | static const struct mips_immed mips_immed[] = { | |
10624 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
10625 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
10626 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
10627 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
10628 | { 0,0,0,0 } | |
10629 | }; | |
10630 | ||
7455baf8 TS |
10631 | /* Check whether an odd floating-point register is allowed. */ |
10632 | static int | |
10633 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
10634 | { | |
10635 | const char *s = insn->name; | |
10636 | ||
10637 | if (insn->pinfo == INSN_MACRO) | |
10638 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
10639 | return 1; | |
10640 | ||
10641 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
10642 | { | |
10643 | /* Allow odd registers for single-precision ops. */ | |
10644 | switch (insn->pinfo & (FP_S | FP_D)) | |
10645 | { | |
10646 | case FP_S: | |
10647 | case 0: | |
10648 | return 1; /* both single precision - ok */ | |
10649 | case FP_D: | |
10650 | return 0; /* both double precision - fail */ | |
10651 | default: | |
10652 | break; | |
10653 | } | |
10654 | ||
10655 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
10656 | s = strchr (insn->name, '.'); | |
10657 | if (argnum == 2) | |
10658 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
10659 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
10660 | } | |
10661 | ||
10662 | /* Single-precision coprocessor loads and moves are OK too. */ | |
10663 | if ((insn->pinfo & FP_S) | |
10664 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
10665 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
10666 | return 1; | |
10667 | ||
10668 | return 0; | |
10669 | } | |
10670 | ||
df58fc94 RS |
10671 | /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive) |
10672 | taking bits from BIT up. */ | |
10673 | static int | |
10674 | expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit) | |
10675 | { | |
10676 | return (ep->X_op == O_constant | |
10677 | && (ep->X_add_number & ((1 << bit) - 1)) == 0 | |
10678 | && ep->X_add_number >= min << bit | |
10679 | && ep->X_add_number < max << bit); | |
10680 | } | |
10681 | ||
252b5132 RH |
10682 | /* This routine assembles an instruction into its binary format. As a |
10683 | side effect, it sets one of the global variables imm_reloc or | |
10684 | offset_reloc to the type of relocation to do if one of the operands | |
10685 | is an address expression. */ | |
10686 | ||
10687 | static void | |
17a2f251 | 10688 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 | 10689 | { |
df58fc94 RS |
10690 | bfd_boolean wrong_delay_slot_insns = FALSE; |
10691 | bfd_boolean need_delay_slot_ok = TRUE; | |
10692 | struct mips_opcode *firstinsn = NULL; | |
10693 | const struct mips_opcode *past; | |
10694 | struct hash_control *hash; | |
252b5132 RH |
10695 | char *s; |
10696 | const char *args; | |
43841e91 | 10697 | char c = 0; |
252b5132 RH |
10698 | struct mips_opcode *insn; |
10699 | char *argsStart; | |
10700 | unsigned int regno; | |
34224acf | 10701 | unsigned int lastregno; |
df58fc94 | 10702 | unsigned int destregno = 0; |
af7ee8bf | 10703 | unsigned int lastpos = 0; |
071742cf | 10704 | unsigned int limlo, limhi; |
252b5132 | 10705 | char *s_reset; |
74cd071d | 10706 | offsetT min_range, max_range; |
df58fc94 | 10707 | long opend; |
a40bc9dd | 10708 | char *name; |
707bfff6 TS |
10709 | int argnum; |
10710 | unsigned int rtype; | |
df58fc94 | 10711 | char *dot; |
a40bc9dd | 10712 | long end; |
252b5132 RH |
10713 | |
10714 | insn_error = NULL; | |
10715 | ||
df58fc94 RS |
10716 | if (mips_opts.micromips) |
10717 | { | |
10718 | hash = micromips_op_hash; | |
10719 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
10720 | } | |
10721 | else | |
10722 | { | |
10723 | hash = op_hash; | |
10724 | past = &mips_opcodes[NUMOPCODES]; | |
10725 | } | |
10726 | forced_insn_length = 0; | |
252b5132 | 10727 | insn = NULL; |
252b5132 | 10728 | |
df58fc94 | 10729 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
10730 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
10731 | continue; | |
bdaaa2e1 | 10732 | |
a40bc9dd RS |
10733 | /* Make a copy of the instruction so that we can fiddle with it. */ |
10734 | name = alloca (end + 1); | |
10735 | memcpy (name, str, end); | |
10736 | name[end] = '\0'; | |
252b5132 | 10737 | |
df58fc94 RS |
10738 | for (;;) |
10739 | { | |
10740 | insn = (struct mips_opcode *) hash_find (hash, name); | |
10741 | ||
10742 | if (insn != NULL || !mips_opts.micromips) | |
10743 | break; | |
10744 | if (forced_insn_length) | |
10745 | break; | |
10746 | ||
10747 | /* See if there's an instruction size override suffix, | |
10748 | either `16' or `32', at the end of the mnemonic proper, | |
10749 | that defines the operation, i.e. before the first `.' | |
10750 | character if any. Strip it and retry. */ | |
10751 | dot = strchr (name, '.'); | |
10752 | opend = dot != NULL ? dot - name : end; | |
10753 | if (opend < 3) | |
10754 | break; | |
10755 | if (name[opend - 2] == '1' && name[opend - 1] == '6') | |
10756 | forced_insn_length = 2; | |
10757 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
10758 | forced_insn_length = 4; | |
10759 | else | |
10760 | break; | |
10761 | memcpy (name + opend - 2, name + opend, end - opend + 1); | |
10762 | } | |
252b5132 RH |
10763 | if (insn == NULL) |
10764 | { | |
a40bc9dd RS |
10765 | insn_error = _("Unrecognized opcode"); |
10766 | return; | |
252b5132 RH |
10767 | } |
10768 | ||
df58fc94 RS |
10769 | /* For microMIPS instructions placed in a fixed-length branch delay slot |
10770 | we make up to two passes over the relevant fragment of the opcode | |
10771 | table. First we try instructions that meet the delay slot's length | |
10772 | requirement. If none matched, then we retry with the remaining ones | |
10773 | and if one matches, then we use it and then issue an appropriate | |
10774 | warning later on. */ | |
a40bc9dd | 10775 | argsStart = s = str + end; |
252b5132 RH |
10776 | for (;;) |
10777 | { | |
df58fc94 RS |
10778 | bfd_boolean delay_slot_ok; |
10779 | bfd_boolean size_ok; | |
b34976b6 | 10780 | bfd_boolean ok; |
252b5132 | 10781 | |
a40bc9dd | 10782 | gas_assert (strcmp (insn->name, name) == 0); |
252b5132 | 10783 | |
f79e2745 | 10784 | ok = is_opcode_valid (insn); |
df58fc94 RS |
10785 | size_ok = is_size_valid (insn); |
10786 | delay_slot_ok = is_delay_slot_valid (insn); | |
10787 | if (!delay_slot_ok && !wrong_delay_slot_insns) | |
252b5132 | 10788 | { |
df58fc94 RS |
10789 | firstinsn = insn; |
10790 | wrong_delay_slot_insns = TRUE; | |
10791 | } | |
10792 | if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok) | |
10793 | { | |
10794 | static char buf[256]; | |
10795 | ||
10796 | if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0) | |
252b5132 RH |
10797 | { |
10798 | ++insn; | |
10799 | continue; | |
10800 | } | |
df58fc94 | 10801 | if (wrong_delay_slot_insns && need_delay_slot_ok) |
beae10d5 | 10802 | { |
df58fc94 RS |
10803 | gas_assert (firstinsn); |
10804 | need_delay_slot_ok = FALSE; | |
10805 | past = insn + 1; | |
10806 | insn = firstinsn; | |
10807 | continue; | |
252b5132 | 10808 | } |
df58fc94 RS |
10809 | |
10810 | if (insn_error) | |
10811 | return; | |
10812 | ||
10813 | if (!ok) | |
7bd942df | 10814 | sprintf (buf, _("Opcode not supported on this processor: %s (%s)"), |
df58fc94 RS |
10815 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
10816 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
10817 | else | |
10818 | sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"), | |
10819 | 8 * forced_insn_length); | |
10820 | insn_error = buf; | |
10821 | ||
10822 | return; | |
252b5132 RH |
10823 | } |
10824 | ||
1e915849 | 10825 | create_insn (ip, insn); |
268f6bed | 10826 | insn_error = NULL; |
707bfff6 | 10827 | argnum = 1; |
24864476 | 10828 | lastregno = 0xffffffff; |
252b5132 RH |
10829 | for (args = insn->args;; ++args) |
10830 | { | |
deec1734 CD |
10831 | int is_mdmx; |
10832 | ||
ad8d3bb3 | 10833 | s += strspn (s, " \t"); |
deec1734 | 10834 | is_mdmx = 0; |
252b5132 RH |
10835 | switch (*args) |
10836 | { | |
10837 | case '\0': /* end of args */ | |
10838 | if (*s == '\0') | |
10839 | return; | |
10840 | break; | |
10841 | ||
03f66e8a MR |
10842 | case '2': |
10843 | /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS | |
10844 | code) or 14 (for microMIPS code). */ | |
8b082fb1 TS |
10845 | my_getExpression (&imm_expr, s); |
10846 | check_absolute_expr (ip, &imm_expr); | |
10847 | if ((unsigned long) imm_expr.X_add_number != 1 | |
10848 | && (unsigned long) imm_expr.X_add_number != 3) | |
10849 | { | |
10850 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
10851 | (unsigned long) imm_expr.X_add_number); | |
10852 | } | |
03f66e8a MR |
10853 | INSERT_OPERAND (mips_opts.micromips, |
10854 | BP, *ip, imm_expr.X_add_number); | |
8b082fb1 TS |
10855 | imm_expr.X_op = O_absent; |
10856 | s = expr_end; | |
10857 | continue; | |
10858 | ||
03f66e8a MR |
10859 | case '3': |
10860 | /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS | |
10861 | code) or 21 (for microMIPS code). */ | |
10862 | { | |
10863 | unsigned long mask = (mips_opts.micromips | |
10864 | ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3); | |
10865 | ||
10866 | my_getExpression (&imm_expr, s); | |
10867 | check_absolute_expr (ip, &imm_expr); | |
10868 | if ((unsigned long) imm_expr.X_add_number > mask) | |
10869 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
10870 | mask, (unsigned long) imm_expr.X_add_number); | |
10871 | INSERT_OPERAND (mips_opts.micromips, | |
10872 | SA3, *ip, imm_expr.X_add_number); | |
10873 | imm_expr.X_op = O_absent; | |
10874 | s = expr_end; | |
10875 | } | |
74cd071d CF |
10876 | continue; |
10877 | ||
03f66e8a MR |
10878 | case '4': |
10879 | /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS | |
10880 | code) or 21 (for microMIPS code). */ | |
10881 | { | |
10882 | unsigned long mask = (mips_opts.micromips | |
10883 | ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4); | |
10884 | ||
10885 | my_getExpression (&imm_expr, s); | |
10886 | check_absolute_expr (ip, &imm_expr); | |
10887 | if ((unsigned long) imm_expr.X_add_number > mask) | |
10888 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
10889 | mask, (unsigned long) imm_expr.X_add_number); | |
10890 | INSERT_OPERAND (mips_opts.micromips, | |
10891 | SA4, *ip, imm_expr.X_add_number); | |
10892 | imm_expr.X_op = O_absent; | |
10893 | s = expr_end; | |
10894 | } | |
74cd071d CF |
10895 | continue; |
10896 | ||
03f66e8a MR |
10897 | case '5': |
10898 | /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS | |
10899 | code) or 16 (for microMIPS code). */ | |
10900 | { | |
10901 | unsigned long mask = (mips_opts.micromips | |
10902 | ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8); | |
10903 | ||
10904 | my_getExpression (&imm_expr, s); | |
10905 | check_absolute_expr (ip, &imm_expr); | |
10906 | if ((unsigned long) imm_expr.X_add_number > mask) | |
10907 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
10908 | mask, (unsigned long) imm_expr.X_add_number); | |
10909 | INSERT_OPERAND (mips_opts.micromips, | |
10910 | IMM8, *ip, imm_expr.X_add_number); | |
10911 | imm_expr.X_op = O_absent; | |
10912 | s = expr_end; | |
10913 | } | |
74cd071d CF |
10914 | continue; |
10915 | ||
03f66e8a MR |
10916 | case '6': |
10917 | /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS | |
10918 | code) or 21 (for microMIPS code). */ | |
10919 | { | |
10920 | unsigned long mask = (mips_opts.micromips | |
10921 | ? MICROMIPSOP_MASK_RS : OP_MASK_RS); | |
10922 | ||
10923 | my_getExpression (&imm_expr, s); | |
10924 | check_absolute_expr (ip, &imm_expr); | |
10925 | if ((unsigned long) imm_expr.X_add_number > mask) | |
10926 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
10927 | mask, (unsigned long) imm_expr.X_add_number); | |
10928 | INSERT_OPERAND (mips_opts.micromips, | |
10929 | RS, *ip, imm_expr.X_add_number); | |
10930 | imm_expr.X_op = O_absent; | |
10931 | s = expr_end; | |
10932 | } | |
74cd071d CF |
10933 | continue; |
10934 | ||
90ecf173 | 10935 | case '7': /* Four DSP accumulators in bits 11,12. */ |
03f66e8a MR |
10936 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
10937 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
10938 | { |
10939 | regno = s[3] - '0'; | |
10940 | s += 4; | |
03f66e8a | 10941 | INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno); |
74cd071d CF |
10942 | continue; |
10943 | } | |
10944 | else | |
10945 | as_bad (_("Invalid dsp acc register")); | |
10946 | break; | |
10947 | ||
03f66e8a MR |
10948 | case '8': |
10949 | /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS | |
10950 | code) or 14 (for microMIPS code). */ | |
10951 | { | |
10952 | unsigned long mask = (mips_opts.micromips | |
10953 | ? MICROMIPSOP_MASK_WRDSP | |
10954 | : OP_MASK_WRDSP); | |
10955 | ||
10956 | my_getExpression (&imm_expr, s); | |
10957 | check_absolute_expr (ip, &imm_expr); | |
10958 | if ((unsigned long) imm_expr.X_add_number > mask) | |
10959 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
10960 | mask, (unsigned long) imm_expr.X_add_number); | |
10961 | INSERT_OPERAND (mips_opts.micromips, | |
10962 | WRDSP, *ip, imm_expr.X_add_number); | |
10963 | imm_expr.X_op = O_absent; | |
10964 | s = expr_end; | |
10965 | } | |
74cd071d CF |
10966 | continue; |
10967 | ||
90ecf173 | 10968 | case '9': /* Four DSP accumulators in bits 21,22. */ |
df58fc94 | 10969 | gas_assert (!mips_opts.micromips); |
03f66e8a MR |
10970 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
10971 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
10972 | { |
10973 | regno = s[3] - '0'; | |
10974 | s += 4; | |
df58fc94 | 10975 | INSERT_OPERAND (0, DSPACC_S, *ip, regno); |
74cd071d CF |
10976 | continue; |
10977 | } | |
10978 | else | |
10979 | as_bad (_("Invalid dsp acc register")); | |
10980 | break; | |
10981 | ||
03f66e8a MR |
10982 | case '0': |
10983 | /* DSP 6-bit signed immediate in bit 16 (for standard MIPS | |
10984 | code) or 20 (for microMIPS code). */ | |
10985 | { | |
10986 | long mask = (mips_opts.micromips | |
10987 | ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT); | |
10988 | ||
10989 | my_getExpression (&imm_expr, s); | |
10990 | check_absolute_expr (ip, &imm_expr); | |
10991 | min_range = -((mask + 1) >> 1); | |
10992 | max_range = ((mask + 1) >> 1) - 1; | |
10993 | if (imm_expr.X_add_number < min_range | |
10994 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
10995 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
10996 | (long) min_range, (long) max_range, | |
10997 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
10998 | INSERT_OPERAND (mips_opts.micromips, |
10999 | DSPSFT, *ip, imm_expr.X_add_number); | |
11000 | imm_expr.X_op = O_absent; | |
11001 | s = expr_end; | |
11002 | } | |
74cd071d CF |
11003 | continue; |
11004 | ||
90ecf173 | 11005 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
df58fc94 | 11006 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11007 | my_getExpression (&imm_expr, s); |
11008 | check_absolute_expr (ip, &imm_expr); | |
11009 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
11010 | { | |
a9e24354 TS |
11011 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
11012 | OP_MASK_RDDSP, | |
11013 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 11014 | } |
df58fc94 | 11015 | INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
11016 | imm_expr.X_op = O_absent; |
11017 | s = expr_end; | |
11018 | continue; | |
11019 | ||
90ecf173 | 11020 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
df58fc94 | 11021 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11022 | my_getExpression (&imm_expr, s); |
11023 | check_absolute_expr (ip, &imm_expr); | |
11024 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
11025 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
11026 | if (imm_expr.X_add_number < min_range || | |
11027 | imm_expr.X_add_number > max_range) | |
11028 | { | |
a9e24354 TS |
11029 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11030 | (long) min_range, (long) max_range, | |
11031 | (long) imm_expr.X_add_number); | |
74cd071d | 11032 | } |
df58fc94 | 11033 | INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
11034 | imm_expr.X_op = O_absent; |
11035 | s = expr_end; | |
11036 | continue; | |
11037 | ||
90ecf173 | 11038 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
03f66e8a MR |
11039 | { |
11040 | long mask = (mips_opts.micromips | |
11041 | ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10); | |
11042 | ||
11043 | my_getExpression (&imm_expr, s); | |
11044 | check_absolute_expr (ip, &imm_expr); | |
11045 | min_range = -((mask + 1) >> 1); | |
11046 | max_range = ((mask + 1) >> 1) - 1; | |
11047 | if (imm_expr.X_add_number < min_range | |
11048 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11049 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11050 | (long) min_range, (long) max_range, | |
11051 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11052 | INSERT_OPERAND (mips_opts.micromips, |
11053 | IMM10, *ip, imm_expr.X_add_number); | |
11054 | imm_expr.X_op = O_absent; | |
11055 | s = expr_end; | |
11056 | } | |
11057 | continue; | |
11058 | ||
11059 | case '^': /* DSP 5-bit unsigned immediate in bit 11. */ | |
11060 | gas_assert (mips_opts.micromips); | |
11061 | my_getExpression (&imm_expr, s); | |
11062 | check_absolute_expr (ip, &imm_expr); | |
11063 | if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD) | |
11064 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), | |
11065 | MICROMIPSOP_MASK_RD, | |
11066 | (unsigned long) imm_expr.X_add_number); | |
11067 | INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number); | |
74cd071d CF |
11068 | imm_expr.X_op = O_absent; |
11069 | s = expr_end; | |
11070 | continue; | |
11071 | ||
a9e24354 | 11072 | case '!': /* MT usermode flag bit. */ |
df58fc94 | 11073 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11074 | my_getExpression (&imm_expr, s); |
11075 | check_absolute_expr (ip, &imm_expr); | |
11076 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
11077 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
11078 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11079 | INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11080 | imm_expr.X_op = O_absent; |
11081 | s = expr_end; | |
11082 | continue; | |
11083 | ||
a9e24354 | 11084 | case '$': /* MT load high flag bit. */ |
df58fc94 | 11085 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11086 | my_getExpression (&imm_expr, s); |
11087 | check_absolute_expr (ip, &imm_expr); | |
11088 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
11089 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
11090 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11091 | INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11092 | imm_expr.X_op = O_absent; |
11093 | s = expr_end; | |
11094 | continue; | |
11095 | ||
90ecf173 | 11096 | case '*': /* Four DSP accumulators in bits 18,19. */ |
df58fc94 | 11097 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11098 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11099 | s[3] >= '0' && s[3] <= '3') | |
11100 | { | |
11101 | regno = s[3] - '0'; | |
11102 | s += 4; | |
df58fc94 | 11103 | INSERT_OPERAND (0, MTACC_T, *ip, regno); |
ef2e4d86 CF |
11104 | continue; |
11105 | } | |
11106 | else | |
11107 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11108 | break; | |
11109 | ||
90ecf173 | 11110 | case '&': /* Four DSP accumulators in bits 13,14. */ |
df58fc94 | 11111 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11112 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11113 | s[3] >= '0' && s[3] <= '3') | |
11114 | { | |
11115 | regno = s[3] - '0'; | |
11116 | s += 4; | |
df58fc94 | 11117 | INSERT_OPERAND (0, MTACC_D, *ip, regno); |
ef2e4d86 CF |
11118 | continue; |
11119 | } | |
11120 | else | |
11121 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11122 | break; | |
11123 | ||
dec0624d MR |
11124 | case '\\': /* 3-bit bit position. */ |
11125 | { | |
2906b037 MR |
11126 | unsigned long mask = (mips_opts.micromips |
11127 | ? MICROMIPSOP_MASK_3BITPOS | |
11128 | : OP_MASK_3BITPOS); | |
dec0624d MR |
11129 | |
11130 | my_getExpression (&imm_expr, s); | |
11131 | check_absolute_expr (ip, &imm_expr); | |
11132 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11133 | as_warn (_("Bit position for %s not in range 0..%lu (%lu)"), | |
11134 | ip->insn_mo->name, | |
11135 | mask, (unsigned long) imm_expr.X_add_number); | |
11136 | INSERT_OPERAND (mips_opts.micromips, | |
11137 | 3BITPOS, *ip, imm_expr.X_add_number); | |
11138 | imm_expr.X_op = O_absent; | |
11139 | s = expr_end; | |
11140 | } | |
11141 | continue; | |
11142 | ||
252b5132 | 11143 | case ',': |
a339155f | 11144 | ++argnum; |
252b5132 RH |
11145 | if (*s++ == *args) |
11146 | continue; | |
11147 | s--; | |
11148 | switch (*++args) | |
11149 | { | |
11150 | case 'r': | |
11151 | case 'v': | |
df58fc94 | 11152 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 RH |
11153 | continue; |
11154 | ||
11155 | case 'w': | |
df58fc94 | 11156 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
38487616 TS |
11157 | continue; |
11158 | ||
252b5132 | 11159 | case 'W': |
df58fc94 RS |
11160 | gas_assert (!mips_opts.micromips); |
11161 | INSERT_OPERAND (0, FT, *ip, lastregno); | |
252b5132 RH |
11162 | continue; |
11163 | ||
11164 | case 'V': | |
df58fc94 | 11165 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 RH |
11166 | continue; |
11167 | } | |
11168 | break; | |
11169 | ||
11170 | case '(': | |
11171 | /* Handle optional base register. | |
11172 | Either the base register is omitted or | |
bdaaa2e1 | 11173 | we must have a left paren. */ |
252b5132 RH |
11174 | /* This is dependent on the next operand specifier |
11175 | is a base register specification. */ | |
df58fc94 RS |
11176 | gas_assert (args[1] == 'b' |
11177 | || (mips_opts.micromips | |
11178 | && args[1] == 'm' | |
11179 | && (args[2] == 'l' || args[2] == 'n' | |
11180 | || args[2] == 's' || args[2] == 'a'))); | |
11181 | if (*s == '\0' && args[1] == 'b') | |
252b5132 | 11182 | return; |
df58fc94 | 11183 | /* Fall through. */ |
252b5132 | 11184 | |
90ecf173 | 11185 | case ')': /* These must match exactly. */ |
df58fc94 RS |
11186 | if (*s++ == *args) |
11187 | continue; | |
11188 | break; | |
11189 | ||
11190 | case '[': /* These must match exactly. */ | |
60b63b72 | 11191 | case ']': |
df58fc94 | 11192 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
11193 | if (*s++ == *args) |
11194 | continue; | |
11195 | break; | |
11196 | ||
af7ee8bf CD |
11197 | case '+': /* Opcode extension character. */ |
11198 | switch (*++args) | |
11199 | { | |
9bcd4f99 TS |
11200 | case '1': /* UDI immediates. */ |
11201 | case '2': | |
11202 | case '3': | |
11203 | case '4': | |
df58fc94 | 11204 | gas_assert (!mips_opts.micromips); |
9bcd4f99 TS |
11205 | { |
11206 | const struct mips_immed *imm = mips_immed; | |
11207 | ||
11208 | while (imm->type && imm->type != *args) | |
11209 | ++imm; | |
11210 | if (! imm->type) | |
11211 | internalError (); | |
11212 | my_getExpression (&imm_expr, s); | |
11213 | check_absolute_expr (ip, &imm_expr); | |
11214 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
11215 | { | |
11216 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
11217 | imm->desc ? imm->desc : ip->insn_mo->name, | |
11218 | (unsigned long) imm_expr.X_add_number, | |
11219 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 11220 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
11221 | } |
11222 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
11223 | << imm->shift); | |
11224 | imm_expr.X_op = O_absent; | |
11225 | s = expr_end; | |
11226 | } | |
11227 | continue; | |
90ecf173 | 11228 | |
071742cf CD |
11229 | case 'A': /* ins/ext position, becomes LSB. */ |
11230 | limlo = 0; | |
11231 | limhi = 31; | |
5f74bc13 CD |
11232 | goto do_lsb; |
11233 | case 'E': | |
11234 | limlo = 32; | |
11235 | limhi = 63; | |
11236 | goto do_lsb; | |
90ecf173 | 11237 | do_lsb: |
071742cf CD |
11238 | my_getExpression (&imm_expr, s); |
11239 | check_absolute_expr (ip, &imm_expr); | |
11240 | if ((unsigned long) imm_expr.X_add_number < limlo | |
11241 | || (unsigned long) imm_expr.X_add_number > limhi) | |
11242 | { | |
11243 | as_bad (_("Improper position (%lu)"), | |
11244 | (unsigned long) imm_expr.X_add_number); | |
11245 | imm_expr.X_add_number = limlo; | |
11246 | } | |
11247 | lastpos = imm_expr.X_add_number; | |
df58fc94 RS |
11248 | INSERT_OPERAND (mips_opts.micromips, |
11249 | EXTLSB, *ip, imm_expr.X_add_number); | |
071742cf CD |
11250 | imm_expr.X_op = O_absent; |
11251 | s = expr_end; | |
11252 | continue; | |
11253 | ||
11254 | case 'B': /* ins size, becomes MSB. */ | |
11255 | limlo = 1; | |
11256 | limhi = 32; | |
5f74bc13 CD |
11257 | goto do_msb; |
11258 | case 'F': | |
11259 | limlo = 33; | |
11260 | limhi = 64; | |
11261 | goto do_msb; | |
90ecf173 | 11262 | do_msb: |
071742cf CD |
11263 | my_getExpression (&imm_expr, s); |
11264 | check_absolute_expr (ip, &imm_expr); | |
11265 | /* Check for negative input so that small negative numbers | |
11266 | will not succeed incorrectly. The checks against | |
11267 | (pos+size) transitively check "size" itself, | |
11268 | assuming that "pos" is reasonable. */ | |
11269 | if ((long) imm_expr.X_add_number < 0 | |
11270 | || ((unsigned long) imm_expr.X_add_number | |
11271 | + lastpos) < limlo | |
11272 | || ((unsigned long) imm_expr.X_add_number | |
11273 | + lastpos) > limhi) | |
11274 | { | |
11275 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
11276 | (unsigned long) imm_expr.X_add_number, | |
11277 | (unsigned long) lastpos); | |
11278 | imm_expr.X_add_number = limlo - lastpos; | |
11279 | } | |
df58fc94 RS |
11280 | INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip, |
11281 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
11282 | imm_expr.X_op = O_absent; |
11283 | s = expr_end; | |
11284 | continue; | |
11285 | ||
11286 | case 'C': /* ext size, becomes MSBD. */ | |
11287 | limlo = 1; | |
11288 | limhi = 32; | |
5f74bc13 CD |
11289 | goto do_msbd; |
11290 | case 'G': | |
11291 | limlo = 33; | |
11292 | limhi = 64; | |
11293 | goto do_msbd; | |
11294 | case 'H': | |
11295 | limlo = 33; | |
11296 | limhi = 64; | |
11297 | goto do_msbd; | |
90ecf173 | 11298 | do_msbd: |
071742cf CD |
11299 | my_getExpression (&imm_expr, s); |
11300 | check_absolute_expr (ip, &imm_expr); | |
11301 | /* Check for negative input so that small negative numbers | |
11302 | will not succeed incorrectly. The checks against | |
11303 | (pos+size) transitively check "size" itself, | |
11304 | assuming that "pos" is reasonable. */ | |
11305 | if ((long) imm_expr.X_add_number < 0 | |
11306 | || ((unsigned long) imm_expr.X_add_number | |
11307 | + lastpos) < limlo | |
11308 | || ((unsigned long) imm_expr.X_add_number | |
11309 | + lastpos) > limhi) | |
11310 | { | |
11311 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
11312 | (unsigned long) imm_expr.X_add_number, | |
11313 | (unsigned long) lastpos); | |
11314 | imm_expr.X_add_number = limlo - lastpos; | |
11315 | } | |
df58fc94 RS |
11316 | INSERT_OPERAND (mips_opts.micromips, |
11317 | EXTMSBD, *ip, imm_expr.X_add_number - 1); | |
071742cf CD |
11318 | imm_expr.X_op = O_absent; |
11319 | s = expr_end; | |
11320 | continue; | |
af7ee8bf | 11321 | |
bbcc0807 CD |
11322 | case 'D': |
11323 | /* +D is for disassembly only; never match. */ | |
11324 | break; | |
11325 | ||
5f74bc13 CD |
11326 | case 'I': |
11327 | /* "+I" is like "I", except that imm2_expr is used. */ | |
11328 | my_getExpression (&imm2_expr, s); | |
11329 | if (imm2_expr.X_op != O_big | |
11330 | && imm2_expr.X_op != O_constant) | |
11331 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
11332 | if (HAVE_32BIT_GPRS) |
11333 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
11334 | s = expr_end; |
11335 | continue; | |
11336 | ||
707bfff6 | 11337 | case 'T': /* Coprocessor register. */ |
df58fc94 | 11338 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11339 | /* +T is for disassembly only; never match. */ |
11340 | break; | |
11341 | ||
707bfff6 | 11342 | case 't': /* Coprocessor register number. */ |
df58fc94 | 11343 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11344 | if (s[0] == '$' && ISDIGIT (s[1])) |
11345 | { | |
11346 | ++s; | |
11347 | regno = 0; | |
11348 | do | |
11349 | { | |
11350 | regno *= 10; | |
11351 | regno += *s - '0'; | |
11352 | ++s; | |
11353 | } | |
11354 | while (ISDIGIT (*s)); | |
11355 | if (regno > 31) | |
11356 | as_bad (_("Invalid register number (%d)"), regno); | |
11357 | else | |
11358 | { | |
df58fc94 | 11359 | INSERT_OPERAND (0, RT, *ip, regno); |
ef2e4d86 CF |
11360 | continue; |
11361 | } | |
11362 | } | |
11363 | else | |
11364 | as_bad (_("Invalid coprocessor 0 register number")); | |
11365 | break; | |
11366 | ||
bb35fb24 NC |
11367 | case 'x': |
11368 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
11369 | is not in the valid range. */ | |
df58fc94 | 11370 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11371 | my_getExpression (&imm_expr, s); |
11372 | check_absolute_expr (ip, &imm_expr); | |
11373 | if ((unsigned) imm_expr.X_add_number > 31) | |
11374 | { | |
11375 | as_bad (_("Improper bit index (%lu)"), | |
11376 | (unsigned long) imm_expr.X_add_number); | |
11377 | imm_expr.X_add_number = 0; | |
11378 | } | |
df58fc94 | 11379 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11380 | imm_expr.X_op = O_absent; |
11381 | s = expr_end; | |
11382 | continue; | |
11383 | ||
11384 | case 'X': | |
11385 | /* bbit[01] bit index when bbit is used but we generate | |
11386 | bbit[01]32 because the index is over 32. Move to the | |
11387 | next candidate if index is not in the valid range. */ | |
df58fc94 | 11388 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11389 | my_getExpression (&imm_expr, s); |
11390 | check_absolute_expr (ip, &imm_expr); | |
11391 | if ((unsigned) imm_expr.X_add_number < 32 | |
11392 | || (unsigned) imm_expr.X_add_number > 63) | |
11393 | break; | |
df58fc94 | 11394 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11395 | imm_expr.X_op = O_absent; |
11396 | s = expr_end; | |
11397 | continue; | |
11398 | ||
11399 | case 'p': | |
11400 | /* cins, cins32, exts and exts32 position field. Give error | |
11401 | if it's not in the valid range. */ | |
df58fc94 | 11402 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11403 | my_getExpression (&imm_expr, s); |
11404 | check_absolute_expr (ip, &imm_expr); | |
11405 | if ((unsigned) imm_expr.X_add_number > 31) | |
11406 | { | |
11407 | as_bad (_("Improper position (%lu)"), | |
11408 | (unsigned long) imm_expr.X_add_number); | |
11409 | imm_expr.X_add_number = 0; | |
11410 | } | |
11411 | /* Make the pos explicit to simplify +S. */ | |
11412 | lastpos = imm_expr.X_add_number + 32; | |
df58fc94 | 11413 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11414 | imm_expr.X_op = O_absent; |
11415 | s = expr_end; | |
11416 | continue; | |
11417 | ||
11418 | case 'P': | |
11419 | /* cins, cins32, exts and exts32 position field. Move to | |
11420 | the next candidate if it's not in the valid range. */ | |
df58fc94 | 11421 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11422 | my_getExpression (&imm_expr, s); |
11423 | check_absolute_expr (ip, &imm_expr); | |
11424 | if ((unsigned) imm_expr.X_add_number < 32 | |
11425 | || (unsigned) imm_expr.X_add_number > 63) | |
11426 | break; | |
11427 | lastpos = imm_expr.X_add_number; | |
df58fc94 | 11428 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11429 | imm_expr.X_op = O_absent; |
11430 | s = expr_end; | |
11431 | continue; | |
11432 | ||
11433 | case 's': | |
11434 | /* cins and exts length-minus-one field. */ | |
df58fc94 | 11435 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11436 | my_getExpression (&imm_expr, s); |
11437 | check_absolute_expr (ip, &imm_expr); | |
11438 | if ((unsigned long) imm_expr.X_add_number > 31) | |
11439 | { | |
11440 | as_bad (_("Improper size (%lu)"), | |
11441 | (unsigned long) imm_expr.X_add_number); | |
11442 | imm_expr.X_add_number = 0; | |
11443 | } | |
df58fc94 | 11444 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11445 | imm_expr.X_op = O_absent; |
11446 | s = expr_end; | |
11447 | continue; | |
11448 | ||
11449 | case 'S': | |
11450 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
11451 | length-minus-one field. */ | |
df58fc94 | 11452 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11453 | my_getExpression (&imm_expr, s); |
11454 | check_absolute_expr (ip, &imm_expr); | |
11455 | if ((long) imm_expr.X_add_number < 0 | |
11456 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
11457 | { | |
11458 | as_bad (_("Improper size (%lu)"), | |
11459 | (unsigned long) imm_expr.X_add_number); | |
11460 | imm_expr.X_add_number = 0; | |
11461 | } | |
df58fc94 | 11462 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11463 | imm_expr.X_op = O_absent; |
11464 | s = expr_end; | |
11465 | continue; | |
11466 | ||
dd3cbb7e NC |
11467 | case 'Q': |
11468 | /* seqi/snei immediate field. */ | |
df58fc94 | 11469 | gas_assert (!mips_opts.micromips); |
dd3cbb7e NC |
11470 | my_getExpression (&imm_expr, s); |
11471 | check_absolute_expr (ip, &imm_expr); | |
11472 | if ((long) imm_expr.X_add_number < -512 | |
11473 | || (long) imm_expr.X_add_number >= 512) | |
11474 | { | |
11475 | as_bad (_("Improper immediate (%ld)"), | |
11476 | (long) imm_expr.X_add_number); | |
11477 | imm_expr.X_add_number = 0; | |
11478 | } | |
df58fc94 | 11479 | INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number); |
dd3cbb7e NC |
11480 | imm_expr.X_op = O_absent; |
11481 | s = expr_end; | |
11482 | continue; | |
11483 | ||
98675402 | 11484 | case 'a': /* 8-bit signed offset in bit 6 */ |
df58fc94 | 11485 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11486 | my_getExpression (&imm_expr, s); |
11487 | check_absolute_expr (ip, &imm_expr); | |
11488 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
11489 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
11490 | if (imm_expr.X_add_number < min_range | |
11491 | || imm_expr.X_add_number > max_range) | |
11492 | { | |
c95354ed | 11493 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11494 | (long) min_range, (long) max_range, |
11495 | (long) imm_expr.X_add_number); | |
11496 | } | |
df58fc94 | 11497 | INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number); |
98675402 RS |
11498 | imm_expr.X_op = O_absent; |
11499 | s = expr_end; | |
11500 | continue; | |
11501 | ||
11502 | case 'b': /* 8-bit signed offset in bit 3 */ | |
df58fc94 | 11503 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11504 | my_getExpression (&imm_expr, s); |
11505 | check_absolute_expr (ip, &imm_expr); | |
11506 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
11507 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
11508 | if (imm_expr.X_add_number < min_range | |
11509 | || imm_expr.X_add_number > max_range) | |
11510 | { | |
c95354ed | 11511 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11512 | (long) min_range, (long) max_range, |
11513 | (long) imm_expr.X_add_number); | |
11514 | } | |
df58fc94 | 11515 | INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number); |
98675402 RS |
11516 | imm_expr.X_op = O_absent; |
11517 | s = expr_end; | |
11518 | continue; | |
11519 | ||
11520 | case 'c': /* 9-bit signed offset in bit 6 */ | |
df58fc94 | 11521 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11522 | my_getExpression (&imm_expr, s); |
11523 | check_absolute_expr (ip, &imm_expr); | |
11524 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
11525 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
11526 | /* We check the offset range before adjusted. */ |
11527 | min_range <<= 4; | |
11528 | max_range <<= 4; | |
98675402 RS |
11529 | if (imm_expr.X_add_number < min_range |
11530 | || imm_expr.X_add_number > max_range) | |
11531 | { | |
c95354ed | 11532 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11533 | (long) min_range, (long) max_range, |
11534 | (long) imm_expr.X_add_number); | |
11535 | } | |
c95354ed MX |
11536 | if (imm_expr.X_add_number & 0xf) |
11537 | { | |
11538 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
11539 | (long) imm_expr.X_add_number); | |
11540 | } | |
11541 | /* Right shift 4 bits to adjust the offset operand. */ | |
df58fc94 RS |
11542 | INSERT_OPERAND (0, OFFSET_C, *ip, |
11543 | imm_expr.X_add_number >> 4); | |
98675402 RS |
11544 | imm_expr.X_op = O_absent; |
11545 | s = expr_end; | |
11546 | continue; | |
11547 | ||
11548 | case 'z': | |
df58fc94 | 11549 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11550 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) |
11551 | break; | |
11552 | if (regno == AT && mips_opts.at) | |
11553 | { | |
11554 | if (mips_opts.at == ATREG) | |
11555 | as_warn (_("used $at without \".set noat\"")); | |
11556 | else | |
11557 | as_warn (_("used $%u with \".set at=$%u\""), | |
11558 | regno, mips_opts.at); | |
11559 | } | |
df58fc94 | 11560 | INSERT_OPERAND (0, RZ, *ip, regno); |
98675402 RS |
11561 | continue; |
11562 | ||
11563 | case 'Z': | |
df58fc94 | 11564 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11565 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) |
11566 | break; | |
df58fc94 | 11567 | INSERT_OPERAND (0, FZ, *ip, regno); |
98675402 RS |
11568 | continue; |
11569 | ||
af7ee8bf | 11570 | default: |
df58fc94 | 11571 | as_bad (_("Internal error: bad %s opcode " |
90ecf173 | 11572 | "(unknown extension operand type `+%c'): %s %s"), |
df58fc94 | 11573 | mips_opts.micromips ? "microMIPS" : "MIPS", |
90ecf173 | 11574 | *args, insn->name, insn->args); |
af7ee8bf CD |
11575 | /* Further processing is fruitless. */ |
11576 | return; | |
11577 | } | |
11578 | break; | |
11579 | ||
df58fc94 | 11580 | case '.': /* 10-bit offset. */ |
df58fc94 | 11581 | gas_assert (mips_opts.micromips); |
dec0624d | 11582 | case '~': /* 12-bit offset. */ |
df58fc94 RS |
11583 | { |
11584 | int shift = *args == '.' ? 9 : 11; | |
11585 | size_t i; | |
11586 | ||
11587 | /* Check whether there is only a single bracketed expression | |
11588 | left. If so, it must be the base register and the | |
11589 | constant must be zero. */ | |
11590 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
11591 | continue; | |
11592 | ||
11593 | /* If this value won't fit into the offset, then go find | |
11594 | a macro that will generate a 16- or 32-bit offset code | |
11595 | pattern. */ | |
11596 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); | |
11597 | if ((i == 0 && (imm_expr.X_op != O_constant | |
11598 | || imm_expr.X_add_number >= 1 << shift | |
11599 | || imm_expr.X_add_number < -1 << shift)) | |
11600 | || i > 0) | |
11601 | { | |
11602 | imm_expr.X_op = O_absent; | |
11603 | break; | |
11604 | } | |
11605 | if (shift == 9) | |
11606 | INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number); | |
11607 | else | |
dec0624d MR |
11608 | INSERT_OPERAND (mips_opts.micromips, |
11609 | OFFSET12, *ip, imm_expr.X_add_number); | |
df58fc94 RS |
11610 | imm_expr.X_op = O_absent; |
11611 | s = expr_end; | |
11612 | } | |
11613 | continue; | |
11614 | ||
252b5132 RH |
11615 | case '<': /* must be at least one digit */ |
11616 | /* | |
11617 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
11618 | * than 31 or less than 0, then the shift amount should be |
11619 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
11620 | * We issue a warning and mask out all but the low 5 bits. |
11621 | */ | |
11622 | my_getExpression (&imm_expr, s); | |
11623 | check_absolute_expr (ip, &imm_expr); | |
11624 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11625 | as_warn (_("Improper shift amount (%lu)"), |
11626 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 RS |
11627 | INSERT_OPERAND (mips_opts.micromips, |
11628 | SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
11629 | imm_expr.X_op = O_absent; |
11630 | s = expr_end; | |
11631 | continue; | |
11632 | ||
11633 | case '>': /* shift amount minus 32 */ | |
11634 | my_getExpression (&imm_expr, s); | |
11635 | check_absolute_expr (ip, &imm_expr); | |
11636 | if ((unsigned long) imm_expr.X_add_number < 32 | |
11637 | || (unsigned long) imm_expr.X_add_number > 63) | |
11638 | break; | |
df58fc94 RS |
11639 | INSERT_OPERAND (mips_opts.micromips, |
11640 | SHAMT, *ip, imm_expr.X_add_number - 32); | |
252b5132 RH |
11641 | imm_expr.X_op = O_absent; |
11642 | s = expr_end; | |
11643 | continue; | |
11644 | ||
90ecf173 MR |
11645 | case 'k': /* CACHE code. */ |
11646 | case 'h': /* PREFX code. */ | |
11647 | case '1': /* SYNC type. */ | |
252b5132 RH |
11648 | my_getExpression (&imm_expr, s); |
11649 | check_absolute_expr (ip, &imm_expr); | |
11650 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11651 | as_warn (_("Invalid value for `%s' (%lu)"), |
11652 | ip->insn_mo->name, | |
11653 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11654 | switch (*args) |
d954098f | 11655 | { |
df58fc94 RS |
11656 | case 'k': |
11657 | if (mips_fix_cn63xxp1 | |
11658 | && !mips_opts.micromips | |
11659 | && strcmp ("pref", insn->name) == 0) | |
d954098f DD |
11660 | switch (imm_expr.X_add_number) |
11661 | { | |
11662 | case 5: | |
11663 | case 25: | |
11664 | case 26: | |
11665 | case 27: | |
11666 | case 28: | |
11667 | case 29: | |
11668 | case 30: | |
11669 | case 31: /* These are ok. */ | |
11670 | break; | |
11671 | ||
11672 | default: /* The rest must be changed to 28. */ | |
11673 | imm_expr.X_add_number = 28; | |
11674 | break; | |
11675 | } | |
df58fc94 RS |
11676 | INSERT_OPERAND (mips_opts.micromips, |
11677 | CACHE, *ip, imm_expr.X_add_number); | |
11678 | break; | |
11679 | case 'h': | |
11680 | INSERT_OPERAND (mips_opts.micromips, | |
11681 | PREFX, *ip, imm_expr.X_add_number); | |
11682 | break; | |
11683 | case '1': | |
11684 | INSERT_OPERAND (mips_opts.micromips, | |
11685 | STYPE, *ip, imm_expr.X_add_number); | |
11686 | break; | |
d954098f | 11687 | } |
252b5132 RH |
11688 | imm_expr.X_op = O_absent; |
11689 | s = expr_end; | |
11690 | continue; | |
11691 | ||
90ecf173 | 11692 | case 'c': /* BREAK code. */ |
df58fc94 RS |
11693 | { |
11694 | unsigned long mask = (mips_opts.micromips | |
11695 | ? MICROMIPSOP_MASK_CODE | |
11696 | : OP_MASK_CODE); | |
11697 | ||
11698 | my_getExpression (&imm_expr, s); | |
11699 | check_absolute_expr (ip, &imm_expr); | |
11700 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11701 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11702 | ip->insn_mo->name, | |
11703 | mask, (unsigned long) imm_expr.X_add_number); | |
11704 | INSERT_OPERAND (mips_opts.micromips, | |
11705 | CODE, *ip, imm_expr.X_add_number); | |
11706 | imm_expr.X_op = O_absent; | |
11707 | s = expr_end; | |
11708 | } | |
252b5132 RH |
11709 | continue; |
11710 | ||
90ecf173 | 11711 | case 'q': /* Lower BREAK code. */ |
df58fc94 RS |
11712 | { |
11713 | unsigned long mask = (mips_opts.micromips | |
11714 | ? MICROMIPSOP_MASK_CODE2 | |
11715 | : OP_MASK_CODE2); | |
11716 | ||
11717 | my_getExpression (&imm_expr, s); | |
11718 | check_absolute_expr (ip, &imm_expr); | |
11719 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11720 | as_warn (_("Lower code for %s not in range 0..%lu (%lu)"), | |
11721 | ip->insn_mo->name, | |
11722 | mask, (unsigned long) imm_expr.X_add_number); | |
11723 | INSERT_OPERAND (mips_opts.micromips, | |
11724 | CODE2, *ip, imm_expr.X_add_number); | |
11725 | imm_expr.X_op = O_absent; | |
11726 | s = expr_end; | |
11727 | } | |
252b5132 RH |
11728 | continue; |
11729 | ||
df58fc94 RS |
11730 | case 'B': /* 20- or 10-bit syscall/break/wait code. */ |
11731 | { | |
11732 | unsigned long mask = (mips_opts.micromips | |
11733 | ? MICROMIPSOP_MASK_CODE10 | |
11734 | : OP_MASK_CODE20); | |
11735 | ||
11736 | my_getExpression (&imm_expr, s); | |
11737 | check_absolute_expr (ip, &imm_expr); | |
11738 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11739 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11740 | ip->insn_mo->name, | |
11741 | mask, (unsigned long) imm_expr.X_add_number); | |
11742 | if (mips_opts.micromips) | |
11743 | INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number); | |
11744 | else | |
11745 | INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number); | |
11746 | imm_expr.X_op = O_absent; | |
11747 | s = expr_end; | |
11748 | } | |
252b5132 RH |
11749 | continue; |
11750 | ||
df58fc94 RS |
11751 | case 'C': /* 25- or 23-bit coprocessor code. */ |
11752 | { | |
11753 | unsigned long mask = (mips_opts.micromips | |
11754 | ? MICROMIPSOP_MASK_COPZ | |
11755 | : OP_MASK_COPZ); | |
11756 | ||
11757 | my_getExpression (&imm_expr, s); | |
11758 | check_absolute_expr (ip, &imm_expr); | |
11759 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11760 | as_warn (_("Coproccesor code > %u bits (%lu)"), | |
11761 | mips_opts.micromips ? 23U : 25U, | |
793b27f4 | 11762 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11763 | INSERT_OPERAND (mips_opts.micromips, |
11764 | COPZ, *ip, imm_expr.X_add_number); | |
11765 | imm_expr.X_op = O_absent; | |
11766 | s = expr_end; | |
11767 | } | |
beae10d5 | 11768 | continue; |
252b5132 | 11769 | |
df58fc94 RS |
11770 | case 'J': /* 19-bit WAIT code. */ |
11771 | gas_assert (!mips_opts.micromips); | |
4372b673 NC |
11772 | my_getExpression (&imm_expr, s); |
11773 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 11774 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
df58fc94 RS |
11775 | { |
11776 | as_warn (_("Illegal 19-bit code (%lu)"), | |
a9e24354 | 11777 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11778 | imm_expr.X_add_number &= OP_MASK_CODE19; |
11779 | } | |
11780 | INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number); | |
4372b673 NC |
11781 | imm_expr.X_op = O_absent; |
11782 | s = expr_end; | |
11783 | continue; | |
11784 | ||
707bfff6 | 11785 | case 'P': /* Performance register. */ |
df58fc94 | 11786 | gas_assert (!mips_opts.micromips); |
beae10d5 | 11787 | my_getExpression (&imm_expr, s); |
252b5132 | 11788 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 11789 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
11790 | as_warn (_("Invalid performance register (%lu)"), |
11791 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11792 | INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number); |
beae10d5 KH |
11793 | imm_expr.X_op = O_absent; |
11794 | s = expr_end; | |
11795 | continue; | |
252b5132 | 11796 | |
707bfff6 | 11797 | case 'G': /* Coprocessor destination register. */ |
df58fc94 RS |
11798 | { |
11799 | unsigned long opcode = ip->insn_opcode; | |
11800 | unsigned long mask; | |
11801 | unsigned int types; | |
11802 | int cop0; | |
11803 | ||
11804 | if (mips_opts.micromips) | |
11805 | { | |
11806 | mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT) | |
11807 | | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS) | |
11808 | | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL)); | |
11809 | opcode &= mask; | |
11810 | switch (opcode) | |
11811 | { | |
11812 | case 0x000000fc: /* mfc0 */ | |
11813 | case 0x000002fc: /* mtc0 */ | |
11814 | case 0x580000fc: /* dmfc0 */ | |
11815 | case 0x580002fc: /* dmtc0 */ | |
11816 | cop0 = 1; | |
11817 | break; | |
11818 | default: | |
11819 | cop0 = 0; | |
11820 | break; | |
11821 | } | |
11822 | } | |
11823 | else | |
11824 | { | |
11825 | opcode = (opcode >> OP_SH_OP) & OP_MASK_OP; | |
11826 | cop0 = opcode == OP_OP_COP0; | |
11827 | } | |
11828 | types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP); | |
11829 | ok = reg_lookup (&s, types, ®no); | |
11830 | if (mips_opts.micromips) | |
11831 | INSERT_OPERAND (1, RS, *ip, regno); | |
11832 | else | |
11833 | INSERT_OPERAND (0, RD, *ip, regno); | |
11834 | if (ok) | |
11835 | { | |
11836 | lastregno = regno; | |
11837 | continue; | |
11838 | } | |
11839 | } | |
11840 | break; | |
707bfff6 | 11841 | |
df58fc94 RS |
11842 | case 'y': /* ALNV.PS source register. */ |
11843 | gas_assert (mips_opts.micromips); | |
11844 | goto do_reg; | |
11845 | case 'x': /* Ignore register name. */ | |
11846 | case 'U': /* Destination register (CLO/CLZ). */ | |
11847 | case 'g': /* Coprocessor destination register. */ | |
11848 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
11849 | case 'b': /* Base register. */ |
11850 | case 'd': /* Destination register. */ | |
11851 | case 's': /* Source register. */ | |
11852 | case 't': /* Target register. */ | |
11853 | case 'r': /* Both target and source. */ | |
11854 | case 'v': /* Both dest and source. */ | |
11855 | case 'w': /* Both dest and target. */ | |
11856 | case 'E': /* Coprocessor target register. */ | |
11857 | case 'K': /* RDHWR destination register. */ | |
90ecf173 | 11858 | case 'z': /* Must be zero register. */ |
df58fc94 | 11859 | do_reg: |
90ecf173 | 11860 | s_reset = s; |
707bfff6 TS |
11861 | if (*args == 'E' || *args == 'K') |
11862 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
11863 | else | |
11864 | { | |
11865 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
11866 | if (regno == AT && mips_opts.at) |
11867 | { | |
11868 | if (mips_opts.at == ATREG) | |
f71d0d44 | 11869 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 11870 | else |
f71d0d44 | 11871 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
11872 | regno, mips_opts.at); |
11873 | } | |
707bfff6 TS |
11874 | } |
11875 | if (ok) | |
252b5132 | 11876 | { |
252b5132 RH |
11877 | c = *args; |
11878 | if (*s == ' ') | |
f9419b05 | 11879 | ++s; |
252b5132 RH |
11880 | if (args[1] != *s) |
11881 | { | |
11882 | if (c == 'r' || c == 'v' || c == 'w') | |
11883 | { | |
11884 | regno = lastregno; | |
11885 | s = s_reset; | |
f9419b05 | 11886 | ++args; |
252b5132 RH |
11887 | } |
11888 | } | |
11889 | /* 'z' only matches $0. */ | |
11890 | if (c == 'z' && regno != 0) | |
11891 | break; | |
11892 | ||
24864476 | 11893 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
11894 | { |
11895 | if (regno == lastregno) | |
90ecf173 MR |
11896 | { |
11897 | insn_error | |
f71d0d44 | 11898 | = _("Source and destination must be different"); |
e7c604dd | 11899 | continue; |
90ecf173 | 11900 | } |
24864476 | 11901 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
11902 | { |
11903 | insn_error | |
f71d0d44 | 11904 | = _("A destination register must be supplied"); |
e7c604dd | 11905 | continue; |
90ecf173 | 11906 | } |
e7c604dd | 11907 | } |
90ecf173 MR |
11908 | /* Now that we have assembled one operand, we use the args |
11909 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
11910 | switch (c) |
11911 | { | |
11912 | case 'r': | |
11913 | case 's': | |
11914 | case 'v': | |
11915 | case 'b': | |
df58fc94 | 11916 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno); |
252b5132 | 11917 | break; |
df58fc94 | 11918 | |
af7ee8bf | 11919 | case 'K': |
df58fc94 RS |
11920 | if (mips_opts.micromips) |
11921 | INSERT_OPERAND (1, RS, *ip, regno); | |
11922 | else | |
11923 | INSERT_OPERAND (0, RD, *ip, regno); | |
11924 | break; | |
11925 | ||
11926 | case 'd': | |
ef2e4d86 | 11927 | case 'g': |
df58fc94 | 11928 | INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno); |
252b5132 | 11929 | break; |
df58fc94 | 11930 | |
4372b673 | 11931 | case 'U': |
df58fc94 RS |
11932 | gas_assert (!mips_opts.micromips); |
11933 | INSERT_OPERAND (0, RD, *ip, regno); | |
11934 | INSERT_OPERAND (0, RT, *ip, regno); | |
4372b673 | 11935 | break; |
df58fc94 | 11936 | |
252b5132 RH |
11937 | case 'w': |
11938 | case 't': | |
11939 | case 'E': | |
df58fc94 RS |
11940 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno); |
11941 | break; | |
11942 | ||
11943 | case 'y': | |
11944 | gas_assert (mips_opts.micromips); | |
11945 | INSERT_OPERAND (1, RS3, *ip, regno); | |
252b5132 | 11946 | break; |
df58fc94 | 11947 | |
252b5132 RH |
11948 | case 'x': |
11949 | /* This case exists because on the r3000 trunc | |
11950 | expands into a macro which requires a gp | |
11951 | register. On the r6000 or r4000 it is | |
11952 | assembled into a single instruction which | |
11953 | ignores the register. Thus the insn version | |
11954 | is MIPS_ISA2 and uses 'x', and the macro | |
11955 | version is MIPS_ISA1 and uses 't'. */ | |
11956 | break; | |
df58fc94 | 11957 | |
252b5132 RH |
11958 | case 'z': |
11959 | /* This case is for the div instruction, which | |
11960 | acts differently if the destination argument | |
11961 | is $0. This only matches $0, and is checked | |
11962 | outside the switch. */ | |
11963 | break; | |
252b5132 RH |
11964 | } |
11965 | lastregno = regno; | |
11966 | continue; | |
11967 | } | |
252b5132 RH |
11968 | switch (*args++) |
11969 | { | |
11970 | case 'r': | |
11971 | case 'v': | |
df58fc94 | 11972 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 | 11973 | continue; |
df58fc94 | 11974 | |
252b5132 | 11975 | case 'w': |
df58fc94 | 11976 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
252b5132 RH |
11977 | continue; |
11978 | } | |
11979 | break; | |
11980 | ||
deec1734 | 11981 | case 'O': /* MDMX alignment immediate constant. */ |
df58fc94 | 11982 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
11983 | my_getExpression (&imm_expr, s); |
11984 | check_absolute_expr (ip, &imm_expr); | |
11985 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 11986 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e | 11987 | (long) imm_expr.X_add_number); |
df58fc94 | 11988 | INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number); |
deec1734 CD |
11989 | imm_expr.X_op = O_absent; |
11990 | s = expr_end; | |
11991 | continue; | |
11992 | ||
11993 | case 'Q': /* MDMX vector, element sel, or const. */ | |
11994 | if (s[0] != '$') | |
11995 | { | |
11996 | /* MDMX Immediate. */ | |
df58fc94 | 11997 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
11998 | my_getExpression (&imm_expr, s); |
11999 | check_absolute_expr (ip, &imm_expr); | |
12000 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
12001 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
12002 | (long) imm_expr.X_add_number); | |
df58fc94 | 12003 | INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number); |
deec1734 CD |
12004 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
12005 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
12006 | else | |
12007 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
12008 | imm_expr.X_op = O_absent; |
12009 | s = expr_end; | |
12010 | continue; | |
12011 | } | |
12012 | /* Not MDMX Immediate. Fall through. */ | |
12013 | case 'X': /* MDMX destination register. */ | |
12014 | case 'Y': /* MDMX source register. */ | |
12015 | case 'Z': /* MDMX target register. */ | |
12016 | is_mdmx = 1; | |
df58fc94 RS |
12017 | case 'W': |
12018 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
12019 | case 'D': /* Floating point destination register. */ |
12020 | case 'S': /* Floating point source register. */ | |
12021 | case 'T': /* Floating point target register. */ | |
12022 | case 'R': /* Floating point source register. */ | |
252b5132 | 12023 | case 'V': |
707bfff6 TS |
12024 | rtype = RTYPE_FPU; |
12025 | if (is_mdmx | |
12026 | || (mips_opts.ase_mdmx | |
12027 | && (ip->insn_mo->pinfo & FP_D) | |
12028 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
12029 | | INSN_COPROC_MEMORY_DELAY | |
12030 | | INSN_LOAD_COPROC_DELAY | |
12031 | | INSN_LOAD_MEMORY_DELAY | |
12032 | | INSN_STORE_MEMORY)))) | |
12033 | rtype |= RTYPE_VEC; | |
252b5132 | 12034 | s_reset = s; |
707bfff6 | 12035 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 12036 | { |
252b5132 | 12037 | if ((regno & 1) != 0 |
ca4e0257 | 12038 | && HAVE_32BIT_FPRS |
90ecf173 | 12039 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
12040 | as_warn (_("Float register should be even, was %d"), |
12041 | regno); | |
12042 | ||
12043 | c = *args; | |
12044 | if (*s == ' ') | |
f9419b05 | 12045 | ++s; |
252b5132 RH |
12046 | if (args[1] != *s) |
12047 | { | |
12048 | if (c == 'V' || c == 'W') | |
12049 | { | |
12050 | regno = lastregno; | |
12051 | s = s_reset; | |
f9419b05 | 12052 | ++args; |
252b5132 RH |
12053 | } |
12054 | } | |
12055 | switch (c) | |
12056 | { | |
12057 | case 'D': | |
deec1734 | 12058 | case 'X': |
df58fc94 | 12059 | INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno); |
252b5132 | 12060 | break; |
df58fc94 | 12061 | |
252b5132 RH |
12062 | case 'V': |
12063 | case 'S': | |
deec1734 | 12064 | case 'Y': |
df58fc94 | 12065 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno); |
252b5132 | 12066 | break; |
df58fc94 | 12067 | |
deec1734 CD |
12068 | case 'Q': |
12069 | /* This is like 'Z', but also needs to fix the MDMX | |
12070 | vector/scalar select bits. Note that the | |
12071 | scalar immediate case is handled above. */ | |
12072 | if (*s == '[') | |
12073 | { | |
12074 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
12075 | int max_el = (is_qh ? 3 : 7); | |
12076 | s++; | |
12077 | my_getExpression(&imm_expr, s); | |
12078 | check_absolute_expr (ip, &imm_expr); | |
12079 | s = expr_end; | |
12080 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
12081 | as_bad (_("Bad element selector %ld"), |
12082 | (long) imm_expr.X_add_number); | |
deec1734 CD |
12083 | imm_expr.X_add_number &= max_el; |
12084 | ip->insn_opcode |= (imm_expr.X_add_number | |
12085 | << (OP_SH_VSEL + | |
12086 | (is_qh ? 2 : 1))); | |
01a3f561 | 12087 | imm_expr.X_op = O_absent; |
deec1734 | 12088 | if (*s != ']') |
20203fb9 | 12089 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
12090 | else |
12091 | s++; | |
12092 | } | |
12093 | else | |
12094 | { | |
12095 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
12096 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
12097 | << OP_SH_VSEL); | |
12098 | else | |
12099 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
12100 | OP_SH_VSEL); | |
12101 | } | |
90ecf173 | 12102 | /* Fall through. */ |
252b5132 RH |
12103 | case 'W': |
12104 | case 'T': | |
deec1734 | 12105 | case 'Z': |
df58fc94 | 12106 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno); |
252b5132 | 12107 | break; |
df58fc94 | 12108 | |
252b5132 | 12109 | case 'R': |
df58fc94 | 12110 | INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno); |
252b5132 RH |
12111 | break; |
12112 | } | |
12113 | lastregno = regno; | |
12114 | continue; | |
12115 | } | |
12116 | ||
252b5132 RH |
12117 | switch (*args++) |
12118 | { | |
12119 | case 'V': | |
df58fc94 | 12120 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 | 12121 | continue; |
df58fc94 | 12122 | |
252b5132 | 12123 | case 'W': |
df58fc94 | 12124 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno); |
252b5132 RH |
12125 | continue; |
12126 | } | |
12127 | break; | |
12128 | ||
12129 | case 'I': | |
12130 | my_getExpression (&imm_expr, s); | |
12131 | if (imm_expr.X_op != O_big | |
12132 | && imm_expr.X_op != O_constant) | |
12133 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
12134 | if (HAVE_32BIT_GPRS) |
12135 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
12136 | s = expr_end; |
12137 | continue; | |
12138 | ||
12139 | case 'A': | |
12140 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 12141 | normalize_address_expr (&offset_expr); |
f6688943 | 12142 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
12143 | s = expr_end; |
12144 | continue; | |
12145 | ||
12146 | case 'F': | |
12147 | case 'L': | |
12148 | case 'f': | |
12149 | case 'l': | |
12150 | { | |
12151 | int f64; | |
ca4e0257 | 12152 | int using_gprs; |
252b5132 RH |
12153 | char *save_in; |
12154 | char *err; | |
12155 | unsigned char temp[8]; | |
12156 | int len; | |
12157 | unsigned int length; | |
12158 | segT seg; | |
12159 | subsegT subseg; | |
12160 | char *p; | |
12161 | ||
12162 | /* These only appear as the last operand in an | |
12163 | instruction, and every instruction that accepts | |
12164 | them in any variant accepts them in all variants. | |
12165 | This means we don't have to worry about backing out | |
12166 | any changes if the instruction does not match. | |
12167 | ||
12168 | The difference between them is the size of the | |
12169 | floating point constant and where it goes. For 'F' | |
12170 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
12171 | is 32 bits. Where the constant is placed is based | |
12172 | on how the MIPS assembler does things: | |
12173 | F -- .rdata | |
12174 | L -- .lit8 | |
12175 | f -- immediate value | |
12176 | l -- .lit4 | |
12177 | ||
12178 | The .lit4 and .lit8 sections are only used if | |
12179 | permitted by the -G argument. | |
12180 | ||
ca4e0257 RS |
12181 | The code below needs to know whether the target register |
12182 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
12183 | 'F' are used with GPR-based instructions and 'l' and | |
12184 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
12185 | |
12186 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 12187 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
12188 | |
12189 | save_in = input_line_pointer; | |
12190 | input_line_pointer = s; | |
12191 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
12192 | length = len; | |
12193 | s = input_line_pointer; | |
12194 | input_line_pointer = save_in; | |
12195 | if (err != NULL && *err != '\0') | |
12196 | { | |
12197 | as_bad (_("Bad floating point constant: %s"), err); | |
12198 | memset (temp, '\0', sizeof temp); | |
12199 | length = f64 ? 8 : 4; | |
12200 | } | |
12201 | ||
9c2799c2 | 12202 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
12203 | |
12204 | if (*args == 'f' | |
12205 | || (*args == 'l' | |
3e722fb5 | 12206 | && (g_switch_value < 4 |
252b5132 RH |
12207 | || (temp[0] == 0 && temp[1] == 0) |
12208 | || (temp[2] == 0 && temp[3] == 0)))) | |
12209 | { | |
12210 | imm_expr.X_op = O_constant; | |
90ecf173 | 12211 | if (!target_big_endian) |
252b5132 RH |
12212 | imm_expr.X_add_number = bfd_getl32 (temp); |
12213 | else | |
12214 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12215 | } | |
12216 | else if (length > 4 | |
90ecf173 | 12217 | && !mips_disable_float_construction |
ca4e0257 RS |
12218 | /* Constants can only be constructed in GPRs and |
12219 | copied to FPRs if the GPRs are at least as wide | |
12220 | as the FPRs. Force the constant into memory if | |
12221 | we are using 64-bit FPRs but the GPRs are only | |
12222 | 32 bits wide. */ | |
12223 | && (using_gprs | |
90ecf173 | 12224 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
12225 | && ((temp[0] == 0 && temp[1] == 0) |
12226 | || (temp[2] == 0 && temp[3] == 0)) | |
12227 | && ((temp[4] == 0 && temp[5] == 0) | |
12228 | || (temp[6] == 0 && temp[7] == 0))) | |
12229 | { | |
ca4e0257 | 12230 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
12231 | instructions. If using 32-bit registers, set |
12232 | imm_expr to the high order 32 bits and offset_expr to | |
12233 | the low order 32 bits. Otherwise, set imm_expr to | |
12234 | the entire 64 bit constant. */ | |
ca4e0257 | 12235 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
12236 | { |
12237 | imm_expr.X_op = O_constant; | |
12238 | offset_expr.X_op = O_constant; | |
90ecf173 | 12239 | if (!target_big_endian) |
252b5132 RH |
12240 | { |
12241 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
12242 | offset_expr.X_add_number = bfd_getl32 (temp); | |
12243 | } | |
12244 | else | |
12245 | { | |
12246 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12247 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
12248 | } | |
12249 | if (offset_expr.X_add_number == 0) | |
12250 | offset_expr.X_op = O_absent; | |
12251 | } | |
12252 | else if (sizeof (imm_expr.X_add_number) > 4) | |
12253 | { | |
12254 | imm_expr.X_op = O_constant; | |
90ecf173 | 12255 | if (!target_big_endian) |
252b5132 RH |
12256 | imm_expr.X_add_number = bfd_getl64 (temp); |
12257 | else | |
12258 | imm_expr.X_add_number = bfd_getb64 (temp); | |
12259 | } | |
12260 | else | |
12261 | { | |
12262 | imm_expr.X_op = O_big; | |
12263 | imm_expr.X_add_number = 4; | |
90ecf173 | 12264 | if (!target_big_endian) |
252b5132 RH |
12265 | { |
12266 | generic_bignum[0] = bfd_getl16 (temp); | |
12267 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
12268 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
12269 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
12270 | } | |
12271 | else | |
12272 | { | |
12273 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
12274 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
12275 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
12276 | generic_bignum[3] = bfd_getb16 (temp); | |
12277 | } | |
12278 | } | |
12279 | } | |
12280 | else | |
12281 | { | |
12282 | const char *newname; | |
12283 | segT new_seg; | |
12284 | ||
12285 | /* Switch to the right section. */ | |
12286 | seg = now_seg; | |
12287 | subseg = now_subseg; | |
12288 | switch (*args) | |
12289 | { | |
12290 | default: /* unused default case avoids warnings. */ | |
12291 | case 'L': | |
12292 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 12293 | if (g_switch_value >= 8) |
252b5132 RH |
12294 | newname = ".lit8"; |
12295 | break; | |
12296 | case 'F': | |
3e722fb5 | 12297 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
12298 | break; |
12299 | case 'l': | |
9c2799c2 | 12300 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
12301 | newname = ".lit4"; |
12302 | break; | |
12303 | } | |
12304 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 12305 | if (IS_ELF) |
252b5132 RH |
12306 | bfd_set_section_flags (stdoutput, new_seg, |
12307 | (SEC_ALLOC | |
12308 | | SEC_LOAD | |
12309 | | SEC_READONLY | |
12310 | | SEC_DATA)); | |
12311 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 12312 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
12313 | record_alignment (new_seg, 4); |
12314 | else | |
12315 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
12316 | if (seg == now_seg) | |
12317 | as_bad (_("Can't use floating point insn in this section")); | |
12318 | ||
df58fc94 RS |
12319 | /* Set the argument to the current address in the |
12320 | section. */ | |
12321 | offset_expr.X_op = O_symbol; | |
12322 | offset_expr.X_add_symbol = symbol_temp_new_now (); | |
12323 | offset_expr.X_add_number = 0; | |
12324 | ||
12325 | /* Put the floating point number into the section. */ | |
12326 | p = frag_more ((int) length); | |
12327 | memcpy (p, temp, length); | |
12328 | ||
12329 | /* Switch back to the original section. */ | |
12330 | subseg_set (seg, subseg); | |
12331 | } | |
12332 | } | |
12333 | continue; | |
12334 | ||
12335 | case 'i': /* 16-bit unsigned immediate. */ | |
12336 | case 'j': /* 16-bit signed immediate. */ | |
12337 | *imm_reloc = BFD_RELOC_LO16; | |
12338 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) | |
12339 | { | |
12340 | int more; | |
12341 | offsetT minval, maxval; | |
12342 | ||
12343 | more = (insn + 1 < past | |
12344 | && strcmp (insn->name, insn[1].name) == 0); | |
12345 | ||
12346 | /* If the expression was written as an unsigned number, | |
12347 | only treat it as signed if there are no more | |
12348 | alternatives. */ | |
12349 | if (more | |
12350 | && *args == 'j' | |
12351 | && sizeof (imm_expr.X_add_number) <= 4 | |
12352 | && imm_expr.X_op == O_constant | |
12353 | && imm_expr.X_add_number < 0 | |
12354 | && imm_expr.X_unsigned | |
12355 | && HAVE_64BIT_GPRS) | |
12356 | break; | |
12357 | ||
12358 | /* For compatibility with older assemblers, we accept | |
12359 | 0x8000-0xffff as signed 16-bit numbers when only | |
12360 | signed numbers are allowed. */ | |
12361 | if (*args == 'i') | |
12362 | minval = 0, maxval = 0xffff; | |
12363 | else if (more) | |
12364 | minval = -0x8000, maxval = 0x7fff; | |
12365 | else | |
12366 | minval = -0x8000, maxval = 0xffff; | |
12367 | ||
12368 | if (imm_expr.X_op != O_constant | |
12369 | || imm_expr.X_add_number < minval | |
12370 | || imm_expr.X_add_number > maxval) | |
12371 | { | |
12372 | if (more) | |
12373 | break; | |
12374 | if (imm_expr.X_op == O_constant | |
12375 | || imm_expr.X_op == O_big) | |
12376 | as_bad (_("Expression out of range")); | |
12377 | } | |
12378 | } | |
12379 | s = expr_end; | |
12380 | continue; | |
12381 | ||
12382 | case 'o': /* 16-bit offset. */ | |
12383 | offset_reloc[0] = BFD_RELOC_LO16; | |
12384 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12385 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12386 | ||
12387 | /* Check whether there is only a single bracketed expression | |
12388 | left. If so, it must be the base register and the | |
12389 | constant must be zero. */ | |
12390 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12391 | { | |
12392 | offset_expr.X_op = O_constant; | |
12393 | offset_expr.X_add_number = 0; | |
12394 | continue; | |
12395 | } | |
12396 | ||
12397 | /* If this value won't fit into a 16 bit offset, then go | |
12398 | find a macro that will generate the 32 bit offset | |
12399 | code pattern. */ | |
12400 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 | |
12401 | && (offset_expr.X_op != O_constant | |
12402 | || offset_expr.X_add_number >= 0x8000 | |
12403 | || offset_expr.X_add_number < -0x8000)) | |
12404 | break; | |
12405 | ||
12406 | s = expr_end; | |
12407 | continue; | |
12408 | ||
12409 | case 'p': /* PC-relative offset. */ | |
12410 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
12411 | my_getExpression (&offset_expr, s); | |
12412 | s = expr_end; | |
12413 | continue; | |
12414 | ||
12415 | case 'u': /* Upper 16 bits. */ | |
12416 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 | |
12417 | && imm_expr.X_op == O_constant | |
12418 | && (imm_expr.X_add_number < 0 | |
12419 | || imm_expr.X_add_number >= 0x10000)) | |
12420 | as_bad (_("lui expression (%lu) not in range 0..65535"), | |
12421 | (unsigned long) imm_expr.X_add_number); | |
12422 | s = expr_end; | |
12423 | continue; | |
12424 | ||
12425 | case 'a': /* 26-bit address. */ | |
12426 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
12427 | my_getExpression (&offset_expr, s); | |
12428 | s = expr_end; | |
12429 | continue; | |
12430 | ||
12431 | case 'N': /* 3-bit branch condition code. */ | |
12432 | case 'M': /* 3-bit compare condition code. */ | |
12433 | rtype = RTYPE_CCC; | |
12434 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) | |
12435 | rtype |= RTYPE_FCC; | |
12436 | if (!reg_lookup (&s, rtype, ®no)) | |
12437 | break; | |
12438 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 | |
12439 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
12440 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
12441 | && (regno & 1) != 0) | |
12442 | as_warn (_("Condition code register should be even for %s, " | |
12443 | "was %d"), | |
12444 | str, regno); | |
12445 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 | |
12446 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
12447 | && (regno & 3) != 0) | |
12448 | as_warn (_("Condition code register should be 0 or 4 for %s, " | |
12449 | "was %d"), | |
12450 | str, regno); | |
12451 | if (*args == 'N') | |
12452 | INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno); | |
12453 | else | |
12454 | INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno); | |
12455 | continue; | |
12456 | ||
12457 | case 'H': | |
12458 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
12459 | s += 2; | |
12460 | if (ISDIGIT (*s)) | |
12461 | { | |
12462 | c = 0; | |
12463 | do | |
12464 | { | |
12465 | c *= 10; | |
12466 | c += *s - '0'; | |
12467 | ++s; | |
12468 | } | |
12469 | while (ISDIGIT (*s)); | |
12470 | } | |
12471 | else | |
12472 | c = 8; /* Invalid sel value. */ | |
12473 | ||
12474 | if (c > 7) | |
12475 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); | |
12476 | INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c); | |
12477 | continue; | |
12478 | ||
12479 | case 'e': | |
12480 | gas_assert (!mips_opts.micromips); | |
12481 | /* Must be at least one digit. */ | |
12482 | my_getExpression (&imm_expr, s); | |
12483 | check_absolute_expr (ip, &imm_expr); | |
12484 | ||
12485 | if ((unsigned long) imm_expr.X_add_number | |
12486 | > (unsigned long) OP_MASK_VECBYTE) | |
12487 | { | |
12488 | as_bad (_("bad byte vector index (%ld)"), | |
12489 | (long) imm_expr.X_add_number); | |
12490 | imm_expr.X_add_number = 0; | |
12491 | } | |
12492 | ||
12493 | INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number); | |
12494 | imm_expr.X_op = O_absent; | |
12495 | s = expr_end; | |
12496 | continue; | |
12497 | ||
12498 | case '%': | |
12499 | gas_assert (!mips_opts.micromips); | |
12500 | my_getExpression (&imm_expr, s); | |
12501 | check_absolute_expr (ip, &imm_expr); | |
12502 | ||
12503 | if ((unsigned long) imm_expr.X_add_number | |
12504 | > (unsigned long) OP_MASK_VECALIGN) | |
12505 | { | |
12506 | as_bad (_("bad byte vector index (%ld)"), | |
12507 | (long) imm_expr.X_add_number); | |
12508 | imm_expr.X_add_number = 0; | |
12509 | } | |
12510 | ||
12511 | INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number); | |
12512 | imm_expr.X_op = O_absent; | |
12513 | s = expr_end; | |
12514 | continue; | |
12515 | ||
12516 | case 'm': /* Opcode extension character. */ | |
12517 | gas_assert (mips_opts.micromips); | |
12518 | c = *++args; | |
12519 | switch (c) | |
12520 | { | |
12521 | case 'r': | |
12522 | if (strncmp (s, "$pc", 3) == 0) | |
12523 | { | |
12524 | s += 3; | |
12525 | continue; | |
12526 | } | |
12527 | break; | |
12528 | ||
12529 | case 'a': | |
12530 | case 'b': | |
12531 | case 'c': | |
12532 | case 'd': | |
12533 | case 'e': | |
12534 | case 'f': | |
12535 | case 'g': | |
12536 | case 'h': | |
12537 | case 'i': | |
12538 | case 'j': | |
12539 | case 'l': | |
12540 | case 'm': | |
12541 | case 'n': | |
12542 | case 'p': | |
12543 | case 'q': | |
12544 | case 's': | |
12545 | case 't': | |
12546 | case 'x': | |
12547 | case 'y': | |
12548 | case 'z': | |
12549 | s_reset = s; | |
12550 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
12551 | if (regno == AT && mips_opts.at) | |
12552 | { | |
12553 | if (mips_opts.at == ATREG) | |
12554 | as_warn (_("Used $at without \".set noat\"")); | |
12555 | else | |
12556 | as_warn (_("Used $%u with \".set at=$%u\""), | |
12557 | regno, mips_opts.at); | |
12558 | } | |
12559 | if (!ok) | |
12560 | { | |
12561 | if (c == 'c') | |
12562 | { | |
12563 | gas_assert (args[1] == ','); | |
12564 | regno = lastregno; | |
12565 | ++args; | |
12566 | } | |
12567 | else if (c == 't') | |
12568 | { | |
12569 | gas_assert (args[1] == ','); | |
12570 | ++args; | |
12571 | continue; /* Nothing to do. */ | |
12572 | } | |
12573 | else | |
12574 | break; | |
12575 | } | |
12576 | ||
12577 | if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4)) | |
12578 | { | |
12579 | if (regno == lastregno) | |
12580 | { | |
12581 | insn_error | |
12582 | = _("Source and destination must be different"); | |
12583 | continue; | |
12584 | } | |
12585 | if (regno == 31 && lastregno == 0xffffffff) | |
12586 | { | |
12587 | insn_error | |
12588 | = _("A destination register must be supplied"); | |
12589 | continue; | |
12590 | } | |
12591 | } | |
12592 | ||
12593 | if (*s == ' ') | |
12594 | ++s; | |
12595 | if (args[1] != *s) | |
12596 | { | |
12597 | if (c == 'e') | |
12598 | { | |
12599 | gas_assert (args[1] == ','); | |
12600 | regno = lastregno; | |
12601 | s = s_reset; | |
12602 | ++args; | |
12603 | } | |
12604 | else if (c == 't') | |
12605 | { | |
12606 | gas_assert (args[1] == ','); | |
12607 | s = s_reset; | |
12608 | ++args; | |
12609 | continue; /* Nothing to do. */ | |
12610 | } | |
12611 | } | |
12612 | ||
12613 | /* Make sure regno is the same as lastregno. */ | |
12614 | if (c == 't' && regno != lastregno) | |
12615 | break; | |
12616 | ||
12617 | /* Make sure regno is the same as destregno. */ | |
12618 | if (c == 'x' && regno != destregno) | |
12619 | break; | |
12620 | ||
12621 | /* We need to save regno, before regno maps to the | |
12622 | microMIPS register encoding. */ | |
12623 | lastregno = regno; | |
12624 | ||
12625 | if (c == 'f') | |
12626 | destregno = regno; | |
12627 | ||
12628 | switch (c) | |
12629 | { | |
12630 | case 'a': | |
12631 | if (regno != GP) | |
12632 | regno = ILLEGAL_REG; | |
12633 | break; | |
12634 | ||
12635 | case 'b': | |
12636 | regno = mips32_to_micromips_reg_b_map[regno]; | |
12637 | break; | |
12638 | ||
12639 | case 'c': | |
12640 | regno = mips32_to_micromips_reg_c_map[regno]; | |
12641 | break; | |
12642 | ||
12643 | case 'd': | |
12644 | regno = mips32_to_micromips_reg_d_map[regno]; | |
12645 | break; | |
12646 | ||
12647 | case 'e': | |
12648 | regno = mips32_to_micromips_reg_e_map[regno]; | |
12649 | break; | |
12650 | ||
12651 | case 'f': | |
12652 | regno = mips32_to_micromips_reg_f_map[regno]; | |
12653 | break; | |
12654 | ||
12655 | case 'g': | |
12656 | regno = mips32_to_micromips_reg_g_map[regno]; | |
12657 | break; | |
12658 | ||
12659 | case 'h': | |
12660 | regno = mips32_to_micromips_reg_h_map[regno]; | |
12661 | break; | |
12662 | ||
12663 | case 'i': | |
12664 | switch (EXTRACT_OPERAND (1, MI, *ip)) | |
12665 | { | |
12666 | case 4: | |
12667 | if (regno == 21) | |
12668 | regno = 3; | |
12669 | else if (regno == 22) | |
12670 | regno = 4; | |
12671 | else if (regno == 5) | |
12672 | regno = 5; | |
12673 | else if (regno == 6) | |
12674 | regno = 6; | |
12675 | else if (regno == 7) | |
12676 | regno = 7; | |
12677 | else | |
12678 | regno = ILLEGAL_REG; | |
12679 | break; | |
12680 | ||
12681 | case 5: | |
12682 | if (regno == 6) | |
12683 | regno = 0; | |
12684 | else if (regno == 7) | |
12685 | regno = 1; | |
12686 | else | |
12687 | regno = ILLEGAL_REG; | |
12688 | break; | |
12689 | ||
12690 | case 6: | |
12691 | if (regno == 7) | |
12692 | regno = 2; | |
12693 | else | |
12694 | regno = ILLEGAL_REG; | |
12695 | break; | |
12696 | ||
12697 | default: | |
12698 | regno = ILLEGAL_REG; | |
12699 | break; | |
12700 | } | |
12701 | break; | |
12702 | ||
12703 | case 'l': | |
12704 | regno = mips32_to_micromips_reg_l_map[regno]; | |
12705 | break; | |
12706 | ||
12707 | case 'm': | |
12708 | regno = mips32_to_micromips_reg_m_map[regno]; | |
12709 | break; | |
12710 | ||
12711 | case 'n': | |
12712 | regno = mips32_to_micromips_reg_n_map[regno]; | |
12713 | break; | |
12714 | ||
12715 | case 'q': | |
12716 | regno = mips32_to_micromips_reg_q_map[regno]; | |
12717 | break; | |
12718 | ||
12719 | case 's': | |
12720 | if (regno != SP) | |
12721 | regno = ILLEGAL_REG; | |
12722 | break; | |
12723 | ||
12724 | case 'y': | |
12725 | if (regno != 31) | |
12726 | regno = ILLEGAL_REG; | |
12727 | break; | |
12728 | ||
12729 | case 'z': | |
12730 | if (regno != ZERO) | |
12731 | regno = ILLEGAL_REG; | |
12732 | break; | |
12733 | ||
12734 | case 'j': /* Do nothing. */ | |
12735 | case 'p': | |
12736 | case 't': | |
12737 | case 'x': | |
12738 | break; | |
12739 | ||
12740 | default: | |
12741 | internalError (); | |
12742 | } | |
12743 | ||
12744 | if (regno == ILLEGAL_REG) | |
12745 | break; | |
12746 | ||
12747 | switch (c) | |
12748 | { | |
12749 | case 'b': | |
12750 | INSERT_OPERAND (1, MB, *ip, regno); | |
12751 | break; | |
12752 | ||
12753 | case 'c': | |
12754 | INSERT_OPERAND (1, MC, *ip, regno); | |
12755 | break; | |
12756 | ||
12757 | case 'd': | |
12758 | INSERT_OPERAND (1, MD, *ip, regno); | |
12759 | break; | |
12760 | ||
12761 | case 'e': | |
12762 | INSERT_OPERAND (1, ME, *ip, regno); | |
12763 | break; | |
12764 | ||
12765 | case 'f': | |
12766 | INSERT_OPERAND (1, MF, *ip, regno); | |
12767 | break; | |
12768 | ||
12769 | case 'g': | |
12770 | INSERT_OPERAND (1, MG, *ip, regno); | |
12771 | break; | |
12772 | ||
12773 | case 'h': | |
12774 | INSERT_OPERAND (1, MH, *ip, regno); | |
12775 | break; | |
12776 | ||
12777 | case 'i': | |
12778 | INSERT_OPERAND (1, MI, *ip, regno); | |
12779 | break; | |
12780 | ||
12781 | case 'j': | |
12782 | INSERT_OPERAND (1, MJ, *ip, regno); | |
12783 | break; | |
12784 | ||
12785 | case 'l': | |
12786 | INSERT_OPERAND (1, ML, *ip, regno); | |
12787 | break; | |
12788 | ||
12789 | case 'm': | |
12790 | INSERT_OPERAND (1, MM, *ip, regno); | |
12791 | break; | |
12792 | ||
12793 | case 'n': | |
12794 | INSERT_OPERAND (1, MN, *ip, regno); | |
12795 | break; | |
12796 | ||
12797 | case 'p': | |
12798 | INSERT_OPERAND (1, MP, *ip, regno); | |
12799 | break; | |
12800 | ||
12801 | case 'q': | |
12802 | INSERT_OPERAND (1, MQ, *ip, regno); | |
12803 | break; | |
12804 | ||
12805 | case 'a': /* Do nothing. */ | |
12806 | case 's': /* Do nothing. */ | |
12807 | case 't': /* Do nothing. */ | |
12808 | case 'x': /* Do nothing. */ | |
12809 | case 'y': /* Do nothing. */ | |
12810 | case 'z': /* Do nothing. */ | |
12811 | break; | |
12812 | ||
12813 | default: | |
12814 | internalError (); | |
12815 | } | |
12816 | continue; | |
12817 | ||
12818 | case 'A': | |
12819 | { | |
12820 | bfd_reloc_code_real_type r[3]; | |
12821 | expressionS ep; | |
12822 | int imm; | |
12823 | ||
12824 | /* Check whether there is only a single bracketed | |
12825 | expression left. If so, it must be the base register | |
12826 | and the constant must be zero. */ | |
12827 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12828 | { | |
12829 | INSERT_OPERAND (1, IMMA, *ip, 0); | |
12830 | continue; | |
12831 | } | |
12832 | ||
12833 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12834 | || !expr_const_in_range (&ep, -64, 64, 2)) | |
12835 | break; | |
12836 | ||
12837 | imm = ep.X_add_number >> 2; | |
12838 | INSERT_OPERAND (1, IMMA, *ip, imm); | |
12839 | } | |
12840 | s = expr_end; | |
12841 | continue; | |
12842 | ||
12843 | case 'B': | |
12844 | { | |
12845 | bfd_reloc_code_real_type r[3]; | |
12846 | expressionS ep; | |
12847 | int imm; | |
12848 | ||
12849 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12850 | || ep.X_op != O_constant) | |
12851 | break; | |
12852 | ||
12853 | for (imm = 0; imm < 8; imm++) | |
12854 | if (micromips_imm_b_map[imm] == ep.X_add_number) | |
12855 | break; | |
12856 | if (imm >= 8) | |
12857 | break; | |
12858 | ||
12859 | INSERT_OPERAND (1, IMMB, *ip, imm); | |
12860 | } | |
12861 | s = expr_end; | |
12862 | continue; | |
12863 | ||
12864 | case 'C': | |
12865 | { | |
12866 | bfd_reloc_code_real_type r[3]; | |
12867 | expressionS ep; | |
12868 | int imm; | |
12869 | ||
12870 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12871 | || ep.X_op != O_constant) | |
12872 | break; | |
12873 | ||
12874 | for (imm = 0; imm < 16; imm++) | |
12875 | if (micromips_imm_c_map[imm] == ep.X_add_number) | |
12876 | break; | |
12877 | if (imm >= 16) | |
12878 | break; | |
12879 | ||
12880 | INSERT_OPERAND (1, IMMC, *ip, imm); | |
12881 | } | |
12882 | s = expr_end; | |
12883 | continue; | |
12884 | ||
12885 | case 'D': /* pc relative offset */ | |
12886 | case 'E': /* pc relative offset */ | |
12887 | my_getExpression (&offset_expr, s); | |
12888 | if (offset_expr.X_op == O_register) | |
12889 | break; | |
12890 | ||
40209cad MR |
12891 | if (!forced_insn_length) |
12892 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
12893 | else if (c == 'D') | |
12894 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
12895 | else | |
12896 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
df58fc94 RS |
12897 | s = expr_end; |
12898 | continue; | |
12899 | ||
12900 | case 'F': | |
12901 | { | |
12902 | bfd_reloc_code_real_type r[3]; | |
12903 | expressionS ep; | |
12904 | int imm; | |
12905 | ||
12906 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12907 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
12908 | break; | |
12909 | ||
12910 | imm = ep.X_add_number; | |
12911 | INSERT_OPERAND (1, IMMF, *ip, imm); | |
12912 | } | |
12913 | s = expr_end; | |
12914 | continue; | |
12915 | ||
12916 | case 'G': | |
12917 | { | |
12918 | bfd_reloc_code_real_type r[3]; | |
12919 | expressionS ep; | |
12920 | int imm; | |
12921 | ||
12922 | /* Check whether there is only a single bracketed | |
12923 | expression left. If so, it must be the base register | |
12924 | and the constant must be zero. */ | |
12925 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12926 | { | |
12927 | INSERT_OPERAND (1, IMMG, *ip, 0); | |
12928 | continue; | |
12929 | } | |
12930 | ||
12931 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12932 | || !expr_const_in_range (&ep, -1, 15, 0)) | |
12933 | break; | |
12934 | ||
12935 | imm = ep.X_add_number & 15; | |
12936 | INSERT_OPERAND (1, IMMG, *ip, imm); | |
12937 | } | |
12938 | s = expr_end; | |
12939 | continue; | |
12940 | ||
12941 | case 'H': | |
12942 | { | |
12943 | bfd_reloc_code_real_type r[3]; | |
12944 | expressionS ep; | |
12945 | int imm; | |
12946 | ||
12947 | /* Check whether there is only a single bracketed | |
12948 | expression left. If so, it must be the base register | |
12949 | and the constant must be zero. */ | |
12950 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12951 | { | |
12952 | INSERT_OPERAND (1, IMMH, *ip, 0); | |
12953 | continue; | |
12954 | } | |
12955 | ||
12956 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12957 | || !expr_const_in_range (&ep, 0, 16, 1)) | |
12958 | break; | |
12959 | ||
12960 | imm = ep.X_add_number >> 1; | |
12961 | INSERT_OPERAND (1, IMMH, *ip, imm); | |
12962 | } | |
12963 | s = expr_end; | |
12964 | continue; | |
12965 | ||
12966 | case 'I': | |
12967 | { | |
12968 | bfd_reloc_code_real_type r[3]; | |
12969 | expressionS ep; | |
12970 | int imm; | |
12971 | ||
12972 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12973 | || !expr_const_in_range (&ep, -1, 127, 0)) | |
12974 | break; | |
12975 | ||
12976 | imm = ep.X_add_number & 127; | |
12977 | INSERT_OPERAND (1, IMMI, *ip, imm); | |
12978 | } | |
12979 | s = expr_end; | |
12980 | continue; | |
12981 | ||
12982 | case 'J': | |
12983 | { | |
12984 | bfd_reloc_code_real_type r[3]; | |
12985 | expressionS ep; | |
12986 | int imm; | |
12987 | ||
12988 | /* Check whether there is only a single bracketed | |
12989 | expression left. If so, it must be the base register | |
12990 | and the constant must be zero. */ | |
12991 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12992 | { | |
12993 | INSERT_OPERAND (1, IMMJ, *ip, 0); | |
12994 | continue; | |
12995 | } | |
12996 | ||
12997 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12998 | || !expr_const_in_range (&ep, 0, 16, 2)) | |
12999 | break; | |
13000 | ||
13001 | imm = ep.X_add_number >> 2; | |
13002 | INSERT_OPERAND (1, IMMJ, *ip, imm); | |
13003 | } | |
13004 | s = expr_end; | |
13005 | continue; | |
13006 | ||
13007 | case 'L': | |
13008 | { | |
13009 | bfd_reloc_code_real_type r[3]; | |
13010 | expressionS ep; | |
13011 | int imm; | |
13012 | ||
13013 | /* Check whether there is only a single bracketed | |
13014 | expression left. If so, it must be the base register | |
13015 | and the constant must be zero. */ | |
13016 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13017 | { | |
13018 | INSERT_OPERAND (1, IMML, *ip, 0); | |
13019 | continue; | |
13020 | } | |
13021 | ||
13022 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13023 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13024 | break; | |
13025 | ||
13026 | imm = ep.X_add_number; | |
13027 | INSERT_OPERAND (1, IMML, *ip, imm); | |
13028 | } | |
13029 | s = expr_end; | |
13030 | continue; | |
13031 | ||
13032 | case 'M': | |
13033 | { | |
13034 | bfd_reloc_code_real_type r[3]; | |
13035 | expressionS ep; | |
13036 | int imm; | |
13037 | ||
13038 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13039 | || !expr_const_in_range (&ep, 1, 9, 0)) | |
13040 | break; | |
13041 | ||
13042 | imm = ep.X_add_number & 7; | |
13043 | INSERT_OPERAND (1, IMMM, *ip, imm); | |
13044 | } | |
13045 | s = expr_end; | |
13046 | continue; | |
13047 | ||
13048 | case 'N': /* Register list for lwm and swm. */ | |
13049 | { | |
13050 | /* A comma-separated list of registers and/or | |
13051 | dash-separated contiguous ranges including | |
13052 | both ra and a set of one or more registers | |
13053 | starting at s0 up to s3 which have to be | |
13054 | consecutive, e.g.: | |
13055 | ||
13056 | s0, ra | |
13057 | s0, s1, ra, s2, s3 | |
13058 | s0-s2, ra | |
13059 | ||
13060 | and any permutations of these. */ | |
13061 | unsigned int reglist; | |
13062 | int imm; | |
13063 | ||
13064 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13065 | break; | |
13066 | ||
13067 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
13068 | break; | |
13069 | ||
13070 | reglist = (reglist >> 17) & 7; | |
13071 | reglist += 1; | |
13072 | if ((reglist & -reglist) != reglist) | |
13073 | break; | |
252b5132 | 13074 | |
df58fc94 RS |
13075 | imm = ffs (reglist) - 1; |
13076 | INSERT_OPERAND (1, IMMN, *ip, imm); | |
13077 | } | |
13078 | continue; | |
252b5132 | 13079 | |
df58fc94 RS |
13080 | case 'O': /* sdbbp 4-bit code. */ |
13081 | { | |
13082 | bfd_reloc_code_real_type r[3]; | |
13083 | expressionS ep; | |
13084 | int imm; | |
13085 | ||
13086 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13087 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13088 | break; | |
13089 | ||
13090 | imm = ep.X_add_number; | |
13091 | INSERT_OPERAND (1, IMMO, *ip, imm); | |
252b5132 | 13092 | } |
df58fc94 RS |
13093 | s = expr_end; |
13094 | continue; | |
252b5132 | 13095 | |
df58fc94 RS |
13096 | case 'P': |
13097 | { | |
13098 | bfd_reloc_code_real_type r[3]; | |
13099 | expressionS ep; | |
13100 | int imm; | |
5e0116d5 | 13101 | |
df58fc94 RS |
13102 | if (my_getSmallExpression (&ep, r, s) > 0 |
13103 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13104 | break; | |
5e0116d5 | 13105 | |
df58fc94 RS |
13106 | imm = ep.X_add_number >> 2; |
13107 | INSERT_OPERAND (1, IMMP, *ip, imm); | |
13108 | } | |
13109 | s = expr_end; | |
13110 | continue; | |
5e0116d5 | 13111 | |
df58fc94 RS |
13112 | case 'Q': |
13113 | { | |
13114 | bfd_reloc_code_real_type r[3]; | |
13115 | expressionS ep; | |
13116 | int imm; | |
5e0116d5 | 13117 | |
df58fc94 RS |
13118 | if (my_getSmallExpression (&ep, r, s) > 0 |
13119 | || !expr_const_in_range (&ep, -0x400000, 0x400000, 2)) | |
13120 | break; | |
252b5132 | 13121 | |
df58fc94 RS |
13122 | imm = ep.X_add_number >> 2; |
13123 | INSERT_OPERAND (1, IMMQ, *ip, imm); | |
13124 | } | |
13125 | s = expr_end; | |
13126 | continue; | |
4614d845 | 13127 | |
df58fc94 RS |
13128 | case 'U': |
13129 | { | |
13130 | bfd_reloc_code_real_type r[3]; | |
13131 | expressionS ep; | |
13132 | int imm; | |
13133 | ||
13134 | /* Check whether there is only a single bracketed | |
13135 | expression left. If so, it must be the base register | |
13136 | and the constant must be zero. */ | |
13137 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13138 | { | |
13139 | INSERT_OPERAND (1, IMMU, *ip, 0); | |
13140 | continue; | |
13141 | } | |
13142 | ||
13143 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13144 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13145 | break; | |
13146 | ||
13147 | imm = ep.X_add_number >> 2; | |
13148 | INSERT_OPERAND (1, IMMU, *ip, imm); | |
13149 | } | |
13150 | s = expr_end; | |
5e0116d5 | 13151 | continue; |
252b5132 | 13152 | |
df58fc94 RS |
13153 | case 'W': |
13154 | { | |
13155 | bfd_reloc_code_real_type r[3]; | |
13156 | expressionS ep; | |
13157 | int imm; | |
252b5132 | 13158 | |
df58fc94 RS |
13159 | if (my_getSmallExpression (&ep, r, s) > 0 |
13160 | || !expr_const_in_range (&ep, 0, 64, 2)) | |
13161 | break; | |
252b5132 | 13162 | |
df58fc94 RS |
13163 | imm = ep.X_add_number >> 2; |
13164 | INSERT_OPERAND (1, IMMW, *ip, imm); | |
13165 | } | |
13166 | s = expr_end; | |
13167 | continue; | |
252b5132 | 13168 | |
df58fc94 RS |
13169 | case 'X': |
13170 | { | |
13171 | bfd_reloc_code_real_type r[3]; | |
13172 | expressionS ep; | |
13173 | int imm; | |
252b5132 | 13174 | |
df58fc94 RS |
13175 | if (my_getSmallExpression (&ep, r, s) > 0 |
13176 | || !expr_const_in_range (&ep, -8, 8, 0)) | |
13177 | break; | |
252b5132 | 13178 | |
df58fc94 RS |
13179 | imm = ep.X_add_number; |
13180 | INSERT_OPERAND (1, IMMX, *ip, imm); | |
13181 | } | |
13182 | s = expr_end; | |
13183 | continue; | |
252b5132 | 13184 | |
df58fc94 RS |
13185 | case 'Y': |
13186 | { | |
13187 | bfd_reloc_code_real_type r[3]; | |
13188 | expressionS ep; | |
13189 | int imm; | |
156c2f8b | 13190 | |
df58fc94 RS |
13191 | if (my_getSmallExpression (&ep, r, s) > 0 |
13192 | || expr_const_in_range (&ep, -2, 2, 2) | |
13193 | || !expr_const_in_range (&ep, -258, 258, 2)) | |
13194 | break; | |
156c2f8b | 13195 | |
df58fc94 RS |
13196 | imm = ep.X_add_number >> 2; |
13197 | imm = ((imm >> 1) & ~0xff) | (imm & 0xff); | |
13198 | INSERT_OPERAND (1, IMMY, *ip, imm); | |
13199 | } | |
13200 | s = expr_end; | |
13201 | continue; | |
60b63b72 | 13202 | |
df58fc94 RS |
13203 | case 'Z': |
13204 | { | |
13205 | bfd_reloc_code_real_type r[3]; | |
13206 | expressionS ep; | |
13207 | ||
13208 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13209 | || !expr_const_in_range (&ep, 0, 1, 0)) | |
13210 | break; | |
13211 | } | |
13212 | s = expr_end; | |
13213 | continue; | |
13214 | ||
13215 | default: | |
13216 | as_bad (_("Internal error: bad microMIPS opcode " | |
13217 | "(unknown extension operand type `m%c'): %s %s"), | |
13218 | *args, insn->name, insn->args); | |
13219 | /* Further processing is fruitless. */ | |
13220 | return; | |
60b63b72 | 13221 | } |
df58fc94 | 13222 | break; |
60b63b72 | 13223 | |
df58fc94 RS |
13224 | case 'n': /* Register list for 32-bit lwm and swm. */ |
13225 | gas_assert (mips_opts.micromips); | |
13226 | { | |
13227 | /* A comma-separated list of registers and/or | |
13228 | dash-separated contiguous ranges including | |
13229 | at least one of ra and a set of one or more | |
13230 | registers starting at s0 up to s7 and then | |
13231 | s8 which have to be consecutive, e.g.: | |
13232 | ||
13233 | ra | |
13234 | s0 | |
13235 | ra, s0, s1, s2 | |
13236 | s0-s8 | |
13237 | s0-s5, ra | |
13238 | ||
13239 | and any permutations of these. */ | |
13240 | unsigned int reglist; | |
13241 | int imm; | |
13242 | int ra; | |
13243 | ||
13244 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13245 | break; | |
13246 | ||
13247 | if ((reglist & 0x3f00ffff) != 0) | |
13248 | break; | |
13249 | ||
13250 | ra = (reglist >> 27) & 0x10; | |
13251 | reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
13252 | reglist += 1; | |
13253 | if ((reglist & -reglist) != reglist) | |
13254 | break; | |
13255 | ||
13256 | imm = (ffs (reglist) - 1) | ra; | |
13257 | INSERT_OPERAND (1, RT, *ip, imm); | |
13258 | imm_expr.X_op = O_absent; | |
13259 | } | |
60b63b72 RS |
13260 | continue; |
13261 | ||
df58fc94 RS |
13262 | case '|': /* 4-bit trap code. */ |
13263 | gas_assert (mips_opts.micromips); | |
60b63b72 RS |
13264 | my_getExpression (&imm_expr, s); |
13265 | check_absolute_expr (ip, &imm_expr); | |
60b63b72 | 13266 | if ((unsigned long) imm_expr.X_add_number |
df58fc94 RS |
13267 | > MICROMIPSOP_MASK_TRAP) |
13268 | as_bad (_("Trap code (%lu) for %s not in 0..15 range"), | |
13269 | (unsigned long) imm_expr.X_add_number, | |
13270 | ip->insn_mo->name); | |
13271 | INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number); | |
60b63b72 RS |
13272 | imm_expr.X_op = O_absent; |
13273 | s = expr_end; | |
13274 | continue; | |
13275 | ||
252b5132 | 13276 | default: |
f71d0d44 | 13277 | as_bad (_("Bad char = '%c'\n"), *args); |
252b5132 RH |
13278 | internalError (); |
13279 | } | |
13280 | break; | |
13281 | } | |
13282 | /* Args don't match. */ | |
df58fc94 RS |
13283 | s = argsStart; |
13284 | insn_error = _("Illegal operands"); | |
13285 | if (insn + 1 < past && !strcmp (insn->name, insn[1].name)) | |
252b5132 RH |
13286 | { |
13287 | ++insn; | |
252b5132 RH |
13288 | continue; |
13289 | } | |
df58fc94 RS |
13290 | else if (wrong_delay_slot_insns && need_delay_slot_ok) |
13291 | { | |
13292 | gas_assert (firstinsn); | |
13293 | need_delay_slot_ok = FALSE; | |
13294 | past = insn + 1; | |
13295 | insn = firstinsn; | |
13296 | continue; | |
13297 | } | |
252b5132 RH |
13298 | return; |
13299 | } | |
13300 | } | |
13301 | ||
0499d65b TS |
13302 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
13303 | ||
252b5132 RH |
13304 | /* This routine assembles an instruction into its binary format when |
13305 | assembling for the mips16. As a side effect, it sets one of the | |
df58fc94 RS |
13306 | global variables imm_reloc or offset_reloc to the type of relocation |
13307 | to do if one of the operands is an address expression. It also sets | |
13308 | forced_insn_length to the resulting instruction size in bytes if the | |
13309 | user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
13310 | |
13311 | static void | |
17a2f251 | 13312 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
13313 | { |
13314 | char *s; | |
13315 | const char *args; | |
13316 | struct mips_opcode *insn; | |
13317 | char *argsstart; | |
13318 | unsigned int regno; | |
13319 | unsigned int lastregno = 0; | |
13320 | char *s_reset; | |
d6f16593 | 13321 | size_t i; |
252b5132 RH |
13322 | |
13323 | insn_error = NULL; | |
13324 | ||
df58fc94 | 13325 | forced_insn_length = 0; |
252b5132 | 13326 | |
3882b010 | 13327 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
13328 | ; |
13329 | switch (*s) | |
13330 | { | |
13331 | case '\0': | |
13332 | break; | |
13333 | ||
13334 | case ' ': | |
13335 | *s++ = '\0'; | |
13336 | break; | |
13337 | ||
13338 | case '.': | |
13339 | if (s[1] == 't' && s[2] == ' ') | |
13340 | { | |
13341 | *s = '\0'; | |
df58fc94 | 13342 | forced_insn_length = 2; |
252b5132 RH |
13343 | s += 3; |
13344 | break; | |
13345 | } | |
13346 | else if (s[1] == 'e' && s[2] == ' ') | |
13347 | { | |
13348 | *s = '\0'; | |
df58fc94 | 13349 | forced_insn_length = 4; |
252b5132 RH |
13350 | s += 3; |
13351 | break; | |
13352 | } | |
13353 | /* Fall through. */ | |
13354 | default: | |
13355 | insn_error = _("unknown opcode"); | |
13356 | return; | |
13357 | } | |
13358 | ||
df58fc94 RS |
13359 | if (mips_opts.noautoextend && !forced_insn_length) |
13360 | forced_insn_length = 2; | |
252b5132 RH |
13361 | |
13362 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
13363 | { | |
13364 | insn_error = _("unrecognized opcode"); | |
13365 | return; | |
13366 | } | |
13367 | ||
13368 | argsstart = s; | |
13369 | for (;;) | |
13370 | { | |
9b3f89ee TS |
13371 | bfd_boolean ok; |
13372 | ||
9c2799c2 | 13373 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 13374 | |
037b32b9 | 13375 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
13376 | if (! ok) |
13377 | { | |
13378 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
13379 | && strcmp (insn->name, insn[1].name) == 0) | |
13380 | { | |
13381 | ++insn; | |
13382 | continue; | |
13383 | } | |
13384 | else | |
13385 | { | |
13386 | if (!insn_error) | |
13387 | { | |
13388 | static char buf[100]; | |
13389 | sprintf (buf, | |
7bd942df | 13390 | _("Opcode not supported on this processor: %s (%s)"), |
9b3f89ee TS |
13391 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
13392 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
13393 | insn_error = buf; | |
13394 | } | |
13395 | return; | |
13396 | } | |
13397 | } | |
13398 | ||
1e915849 | 13399 | create_insn (ip, insn); |
252b5132 | 13400 | imm_expr.X_op = O_absent; |
f6688943 TS |
13401 | imm_reloc[0] = BFD_RELOC_UNUSED; |
13402 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
13403 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 13404 | imm2_expr.X_op = O_absent; |
252b5132 | 13405 | offset_expr.X_op = O_absent; |
f6688943 TS |
13406 | offset_reloc[0] = BFD_RELOC_UNUSED; |
13407 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13408 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
13409 | for (args = insn->args; 1; ++args) |
13410 | { | |
13411 | int c; | |
13412 | ||
13413 | if (*s == ' ') | |
13414 | ++s; | |
13415 | ||
13416 | /* In this switch statement we call break if we did not find | |
13417 | a match, continue if we did find a match, or return if we | |
13418 | are done. */ | |
13419 | ||
13420 | c = *args; | |
13421 | switch (c) | |
13422 | { | |
13423 | case '\0': | |
13424 | if (*s == '\0') | |
13425 | { | |
b886a2ab RS |
13426 | offsetT value; |
13427 | ||
252b5132 RH |
13428 | /* Stuff the immediate value in now, if we can. */ |
13429 | if (imm_expr.X_op == O_constant | |
f6688943 | 13430 | && *imm_reloc > BFD_RELOC_UNUSED |
b886a2ab RS |
13431 | && insn->pinfo != INSN_MACRO |
13432 | && calculate_reloc (*offset_reloc, | |
13433 | imm_expr.X_add_number, &value)) | |
252b5132 | 13434 | { |
c4e7957c | 13435 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
b886a2ab | 13436 | *offset_reloc, value, forced_insn_length, |
43c0598f | 13437 | &ip->insn_opcode); |
252b5132 | 13438 | imm_expr.X_op = O_absent; |
f6688943 | 13439 | *imm_reloc = BFD_RELOC_UNUSED; |
43c0598f | 13440 | *offset_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
13441 | } |
13442 | ||
13443 | return; | |
13444 | } | |
13445 | break; | |
13446 | ||
13447 | case ',': | |
13448 | if (*s++ == c) | |
13449 | continue; | |
13450 | s--; | |
13451 | switch (*++args) | |
13452 | { | |
13453 | case 'v': | |
bf12938e | 13454 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
13455 | continue; |
13456 | case 'w': | |
bf12938e | 13457 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13458 | continue; |
13459 | } | |
13460 | break; | |
13461 | ||
13462 | case '(': | |
13463 | case ')': | |
13464 | if (*s++ == c) | |
13465 | continue; | |
13466 | break; | |
13467 | ||
13468 | case 'v': | |
13469 | case 'w': | |
13470 | if (s[0] != '$') | |
13471 | { | |
13472 | if (c == 'v') | |
bf12938e | 13473 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 13474 | else |
bf12938e | 13475 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13476 | ++args; |
13477 | continue; | |
13478 | } | |
13479 | /* Fall through. */ | |
13480 | case 'x': | |
13481 | case 'y': | |
13482 | case 'z': | |
13483 | case 'Z': | |
13484 | case '0': | |
13485 | case 'S': | |
13486 | case 'R': | |
13487 | case 'X': | |
13488 | case 'Y': | |
707bfff6 TS |
13489 | s_reset = s; |
13490 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 13491 | { |
707bfff6 | 13492 | if (c == 'v' || c == 'w') |
85b51719 | 13493 | { |
707bfff6 | 13494 | if (c == 'v') |
a9e24354 | 13495 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 13496 | else |
a9e24354 | 13497 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
13498 | ++args; |
13499 | continue; | |
85b51719 | 13500 | } |
707bfff6 | 13501 | break; |
252b5132 RH |
13502 | } |
13503 | ||
13504 | if (*s == ' ') | |
13505 | ++s; | |
13506 | if (args[1] != *s) | |
13507 | { | |
13508 | if (c == 'v' || c == 'w') | |
13509 | { | |
13510 | regno = mips16_to_32_reg_map[lastregno]; | |
13511 | s = s_reset; | |
f9419b05 | 13512 | ++args; |
252b5132 RH |
13513 | } |
13514 | } | |
13515 | ||
13516 | switch (c) | |
13517 | { | |
13518 | case 'x': | |
13519 | case 'y': | |
13520 | case 'z': | |
13521 | case 'v': | |
13522 | case 'w': | |
13523 | case 'Z': | |
13524 | regno = mips32_to_16_reg_map[regno]; | |
13525 | break; | |
13526 | ||
13527 | case '0': | |
13528 | if (regno != 0) | |
13529 | regno = ILLEGAL_REG; | |
13530 | break; | |
13531 | ||
13532 | case 'S': | |
13533 | if (regno != SP) | |
13534 | regno = ILLEGAL_REG; | |
13535 | break; | |
13536 | ||
13537 | case 'R': | |
13538 | if (regno != RA) | |
13539 | regno = ILLEGAL_REG; | |
13540 | break; | |
13541 | ||
13542 | case 'X': | |
13543 | case 'Y': | |
741fe287 MR |
13544 | if (regno == AT && mips_opts.at) |
13545 | { | |
13546 | if (mips_opts.at == ATREG) | |
13547 | as_warn (_("used $at without \".set noat\"")); | |
13548 | else | |
13549 | as_warn (_("used $%u with \".set at=$%u\""), | |
13550 | regno, mips_opts.at); | |
13551 | } | |
252b5132 RH |
13552 | break; |
13553 | ||
13554 | default: | |
13555 | internalError (); | |
13556 | } | |
13557 | ||
13558 | if (regno == ILLEGAL_REG) | |
13559 | break; | |
13560 | ||
13561 | switch (c) | |
13562 | { | |
13563 | case 'x': | |
13564 | case 'v': | |
bf12938e | 13565 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
13566 | break; |
13567 | case 'y': | |
13568 | case 'w': | |
bf12938e | 13569 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
13570 | break; |
13571 | case 'z': | |
bf12938e | 13572 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
13573 | break; |
13574 | case 'Z': | |
bf12938e | 13575 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
13576 | case '0': |
13577 | case 'S': | |
13578 | case 'R': | |
13579 | break; | |
13580 | case 'X': | |
bf12938e | 13581 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
13582 | break; |
13583 | case 'Y': | |
13584 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 13585 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
13586 | break; |
13587 | default: | |
13588 | internalError (); | |
13589 | } | |
13590 | ||
13591 | lastregno = regno; | |
13592 | continue; | |
13593 | ||
13594 | case 'P': | |
13595 | if (strncmp (s, "$pc", 3) == 0) | |
13596 | { | |
13597 | s += 3; | |
13598 | continue; | |
13599 | } | |
13600 | break; | |
13601 | ||
252b5132 RH |
13602 | case '5': |
13603 | case 'H': | |
13604 | case 'W': | |
13605 | case 'D': | |
13606 | case 'j': | |
252b5132 RH |
13607 | case 'V': |
13608 | case 'C': | |
13609 | case 'U': | |
13610 | case 'k': | |
13611 | case 'K': | |
d6f16593 MR |
13612 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
13613 | if (i > 0) | |
252b5132 | 13614 | { |
d6f16593 | 13615 | if (imm_expr.X_op != O_constant) |
252b5132 | 13616 | { |
df58fc94 | 13617 | forced_insn_length = 4; |
5c04167a | 13618 | ip->insn_opcode |= MIPS16_EXTEND; |
252b5132 | 13619 | } |
d6f16593 MR |
13620 | else |
13621 | { | |
13622 | /* We need to relax this instruction. */ | |
13623 | *offset_reloc = *imm_reloc; | |
13624 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
13625 | } | |
13626 | s = expr_end; | |
13627 | continue; | |
252b5132 | 13628 | } |
d6f16593 MR |
13629 | *imm_reloc = BFD_RELOC_UNUSED; |
13630 | /* Fall through. */ | |
13631 | case '<': | |
13632 | case '>': | |
13633 | case '[': | |
13634 | case ']': | |
13635 | case '4': | |
13636 | case '8': | |
13637 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
13638 | if (imm_expr.X_op == O_register) |
13639 | { | |
13640 | /* What we thought was an expression turned out to | |
13641 | be a register. */ | |
13642 | ||
13643 | if (s[0] == '(' && args[1] == '(') | |
13644 | { | |
13645 | /* It looks like the expression was omitted | |
13646 | before a register indirection, which means | |
13647 | that the expression is implicitly zero. We | |
13648 | still set up imm_expr, so that we handle | |
13649 | explicit extensions correctly. */ | |
13650 | imm_expr.X_op = O_constant; | |
13651 | imm_expr.X_add_number = 0; | |
f6688943 | 13652 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13653 | continue; |
13654 | } | |
13655 | ||
13656 | break; | |
13657 | } | |
13658 | ||
13659 | /* We need to relax this instruction. */ | |
f6688943 | 13660 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13661 | s = expr_end; |
13662 | continue; | |
13663 | ||
13664 | case 'p': | |
13665 | case 'q': | |
13666 | case 'A': | |
13667 | case 'B': | |
13668 | case 'E': | |
13669 | /* We use offset_reloc rather than imm_reloc for the PC | |
13670 | relative operands. This lets macros with both | |
13671 | immediate and address operands work correctly. */ | |
13672 | my_getExpression (&offset_expr, s); | |
13673 | ||
13674 | if (offset_expr.X_op == O_register) | |
13675 | break; | |
13676 | ||
13677 | /* We need to relax this instruction. */ | |
f6688943 | 13678 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13679 | s = expr_end; |
13680 | continue; | |
13681 | ||
13682 | case '6': /* break code */ | |
13683 | my_getExpression (&imm_expr, s); | |
13684 | check_absolute_expr (ip, &imm_expr); | |
13685 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
13686 | as_warn (_("Invalid value for `%s' (%lu)"), |
13687 | ip->insn_mo->name, | |
13688 | (unsigned long) imm_expr.X_add_number); | |
13689 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
13690 | imm_expr.X_op = O_absent; |
13691 | s = expr_end; | |
13692 | continue; | |
13693 | ||
13694 | case 'a': /* 26 bit address */ | |
13695 | my_getExpression (&offset_expr, s); | |
13696 | s = expr_end; | |
f6688943 | 13697 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
13698 | ip->insn_opcode <<= 16; |
13699 | continue; | |
13700 | ||
13701 | case 'l': /* register list for entry macro */ | |
13702 | case 'L': /* register list for exit macro */ | |
13703 | { | |
13704 | int mask; | |
13705 | ||
13706 | if (c == 'l') | |
13707 | mask = 0; | |
13708 | else | |
13709 | mask = 7 << 3; | |
13710 | while (*s != '\0') | |
13711 | { | |
707bfff6 | 13712 | unsigned int freg, reg1, reg2; |
252b5132 RH |
13713 | |
13714 | while (*s == ' ' || *s == ',') | |
13715 | ++s; | |
707bfff6 | 13716 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 13717 | freg = 0; |
707bfff6 TS |
13718 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
13719 | freg = 1; | |
252b5132 RH |
13720 | else |
13721 | { | |
707bfff6 TS |
13722 | as_bad (_("can't parse register list")); |
13723 | break; | |
252b5132 RH |
13724 | } |
13725 | if (*s == ' ') | |
13726 | ++s; | |
13727 | if (*s != '-') | |
13728 | reg2 = reg1; | |
13729 | else | |
13730 | { | |
13731 | ++s; | |
707bfff6 TS |
13732 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
13733 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 13734 | { |
707bfff6 TS |
13735 | as_bad (_("invalid register list")); |
13736 | break; | |
252b5132 RH |
13737 | } |
13738 | } | |
13739 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
13740 | { | |
13741 | mask &= ~ (7 << 3); | |
13742 | mask |= 5 << 3; | |
13743 | } | |
13744 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
13745 | { | |
13746 | mask &= ~ (7 << 3); | |
13747 | mask |= 6 << 3; | |
13748 | } | |
13749 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
13750 | mask |= (reg2 - 3) << 3; | |
13751 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
13752 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 13753 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
13754 | mask |= 1; |
13755 | else | |
13756 | { | |
13757 | as_bad (_("invalid register list")); | |
13758 | break; | |
13759 | } | |
13760 | } | |
13761 | /* The mask is filled in in the opcode table for the | |
13762 | benefit of the disassembler. We remove it before | |
13763 | applying the actual mask. */ | |
13764 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
13765 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
13766 | } | |
13767 | continue; | |
13768 | ||
0499d65b TS |
13769 | case 'm': /* Register list for save insn. */ |
13770 | case 'M': /* Register list for restore insn. */ | |
13771 | { | |
5c04167a | 13772 | int opcode = ip->insn_opcode; |
0499d65b | 13773 | int framesz = 0, seen_framesz = 0; |
91d6fa6a | 13774 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
13775 | |
13776 | while (*s != '\0') | |
13777 | { | |
13778 | unsigned int reg1, reg2; | |
13779 | ||
13780 | SKIP_SPACE_TABS (s); | |
13781 | while (*s == ',') | |
13782 | ++s; | |
13783 | SKIP_SPACE_TABS (s); | |
13784 | ||
13785 | my_getExpression (&imm_expr, s); | |
13786 | if (imm_expr.X_op == O_constant) | |
13787 | { | |
13788 | /* Handle the frame size. */ | |
13789 | if (seen_framesz) | |
13790 | { | |
13791 | as_bad (_("more than one frame size in list")); | |
13792 | break; | |
13793 | } | |
13794 | seen_framesz = 1; | |
13795 | framesz = imm_expr.X_add_number; | |
13796 | imm_expr.X_op = O_absent; | |
13797 | s = expr_end; | |
13798 | continue; | |
13799 | } | |
13800 | ||
707bfff6 | 13801 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
13802 | { |
13803 | as_bad (_("can't parse register list")); | |
13804 | break; | |
13805 | } | |
0499d65b | 13806 | |
707bfff6 TS |
13807 | while (*s == ' ') |
13808 | ++s; | |
13809 | ||
0499d65b TS |
13810 | if (*s != '-') |
13811 | reg2 = reg1; | |
13812 | else | |
13813 | { | |
13814 | ++s; | |
707bfff6 TS |
13815 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
13816 | || reg2 < reg1) | |
0499d65b TS |
13817 | { |
13818 | as_bad (_("can't parse register list")); | |
13819 | break; | |
13820 | } | |
0499d65b TS |
13821 | } |
13822 | ||
13823 | while (reg1 <= reg2) | |
13824 | { | |
13825 | if (reg1 >= 4 && reg1 <= 7) | |
13826 | { | |
3a93f742 | 13827 | if (!seen_framesz) |
0499d65b | 13828 | /* args $a0-$a3 */ |
91d6fa6a | 13829 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
13830 | else |
13831 | /* statics $a0-$a3 */ | |
13832 | statics |= 1 << (reg1 - 4); | |
13833 | } | |
13834 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
13835 | { | |
13836 | /* $s0-$s8 */ | |
13837 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
13838 | } | |
13839 | else if (reg1 == 31) | |
13840 | { | |
13841 | /* Add $ra to insn. */ | |
13842 | opcode |= 0x40; | |
13843 | } | |
13844 | else | |
13845 | { | |
13846 | as_bad (_("unexpected register in list")); | |
13847 | break; | |
13848 | } | |
13849 | if (++reg1 == 24) | |
13850 | reg1 = 30; | |
13851 | } | |
13852 | } | |
13853 | ||
13854 | /* Encode args/statics combination. */ | |
91d6fa6a | 13855 | if (nargs & statics) |
0499d65b | 13856 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 13857 | else if (nargs == 0xf) |
0499d65b TS |
13858 | /* All $a0-$a3 are args. */ |
13859 | opcode |= MIPS16_ALL_ARGS << 16; | |
13860 | else if (statics == 0xf) | |
13861 | /* All $a0-$a3 are statics. */ | |
13862 | opcode |= MIPS16_ALL_STATICS << 16; | |
13863 | else | |
13864 | { | |
13865 | int narg = 0, nstat = 0; | |
13866 | ||
13867 | /* Count arg registers. */ | |
91d6fa6a | 13868 | while (nargs & 0x1) |
0499d65b | 13869 | { |
91d6fa6a | 13870 | nargs >>= 1; |
0499d65b TS |
13871 | narg++; |
13872 | } | |
91d6fa6a | 13873 | if (nargs != 0) |
0499d65b TS |
13874 | as_bad (_("invalid arg register list")); |
13875 | ||
13876 | /* Count static registers. */ | |
13877 | while (statics & 0x8) | |
13878 | { | |
13879 | statics = (statics << 1) & 0xf; | |
13880 | nstat++; | |
13881 | } | |
13882 | if (statics != 0) | |
13883 | as_bad (_("invalid static register list")); | |
13884 | ||
13885 | /* Encode args/statics. */ | |
13886 | opcode |= ((narg << 2) | nstat) << 16; | |
13887 | } | |
13888 | ||
13889 | /* Encode $s0/$s1. */ | |
13890 | if (sregs & (1 << 0)) /* $s0 */ | |
13891 | opcode |= 0x20; | |
13892 | if (sregs & (1 << 1)) /* $s1 */ | |
13893 | opcode |= 0x10; | |
13894 | sregs >>= 2; | |
13895 | ||
13896 | if (sregs != 0) | |
13897 | { | |
13898 | /* Count regs $s2-$s8. */ | |
13899 | int nsreg = 0; | |
13900 | while (sregs & 1) | |
13901 | { | |
13902 | sregs >>= 1; | |
13903 | nsreg++; | |
13904 | } | |
13905 | if (sregs != 0) | |
13906 | as_bad (_("invalid static register list")); | |
13907 | /* Encode $s2-$s8. */ | |
13908 | opcode |= nsreg << 24; | |
13909 | } | |
13910 | ||
13911 | /* Encode frame size. */ | |
13912 | if (!seen_framesz) | |
13913 | as_bad (_("missing frame size")); | |
13914 | else if ((framesz & 7) != 0 || framesz < 0 | |
13915 | || framesz > 0xff * 8) | |
13916 | as_bad (_("invalid frame size")); | |
13917 | else if (framesz != 128 || (opcode >> 16) != 0) | |
13918 | { | |
13919 | framesz /= 8; | |
13920 | opcode |= (((framesz & 0xf0) << 16) | |
13921 | | (framesz & 0x0f)); | |
13922 | } | |
13923 | ||
13924 | /* Finally build the instruction. */ | |
13925 | if ((opcode >> 16) != 0 || framesz == 0) | |
5c04167a RS |
13926 | opcode |= MIPS16_EXTEND; |
13927 | ip->insn_opcode = opcode; | |
0499d65b TS |
13928 | } |
13929 | continue; | |
13930 | ||
252b5132 RH |
13931 | case 'e': /* extend code */ |
13932 | my_getExpression (&imm_expr, s); | |
13933 | check_absolute_expr (ip, &imm_expr); | |
13934 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
13935 | { | |
13936 | as_warn (_("Invalid value for `%s' (%lu)"), | |
13937 | ip->insn_mo->name, | |
13938 | (unsigned long) imm_expr.X_add_number); | |
13939 | imm_expr.X_add_number &= 0x7ff; | |
13940 | } | |
13941 | ip->insn_opcode |= imm_expr.X_add_number; | |
13942 | imm_expr.X_op = O_absent; | |
13943 | s = expr_end; | |
13944 | continue; | |
13945 | ||
13946 | default: | |
13947 | internalError (); | |
13948 | } | |
13949 | break; | |
13950 | } | |
13951 | ||
13952 | /* Args don't match. */ | |
13953 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
13954 | strcmp (insn->name, insn[1].name) == 0) | |
13955 | { | |
13956 | ++insn; | |
13957 | s = argsstart; | |
13958 | continue; | |
13959 | } | |
13960 | ||
13961 | insn_error = _("illegal operands"); | |
13962 | ||
13963 | return; | |
13964 | } | |
13965 | } | |
13966 | ||
13967 | /* This structure holds information we know about a mips16 immediate | |
13968 | argument type. */ | |
13969 | ||
e972090a NC |
13970 | struct mips16_immed_operand |
13971 | { | |
252b5132 RH |
13972 | /* The type code used in the argument string in the opcode table. */ |
13973 | int type; | |
13974 | /* The number of bits in the short form of the opcode. */ | |
13975 | int nbits; | |
13976 | /* The number of bits in the extended form of the opcode. */ | |
13977 | int extbits; | |
13978 | /* The amount by which the short form is shifted when it is used; | |
13979 | for example, the sw instruction has a shift count of 2. */ | |
13980 | int shift; | |
13981 | /* The amount by which the short form is shifted when it is stored | |
13982 | into the instruction code. */ | |
13983 | int op_shift; | |
13984 | /* Non-zero if the short form is unsigned. */ | |
13985 | int unsp; | |
13986 | /* Non-zero if the extended form is unsigned. */ | |
13987 | int extu; | |
13988 | /* Non-zero if the value is PC relative. */ | |
13989 | int pcrel; | |
13990 | }; | |
13991 | ||
13992 | /* The mips16 immediate operand types. */ | |
13993 | ||
13994 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
13995 | { | |
13996 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
13997 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
13998 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
13999 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14000 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
14001 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14002 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14003 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14004 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14005 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
14006 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14007 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14008 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14009 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
14010 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14011 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14012 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14013 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14014 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
14015 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
14016 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
14017 | }; | |
14018 | ||
14019 | #define MIPS16_NUM_IMMED \ | |
14020 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
14021 | ||
b886a2ab RS |
14022 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
14023 | NBITS is the number of significant bits in VAL. */ | |
14024 | ||
14025 | static unsigned long | |
14026 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
14027 | { | |
14028 | int extval; | |
14029 | if (nbits == 16) | |
14030 | { | |
14031 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
14032 | val &= 0x1f; | |
14033 | } | |
14034 | else if (nbits == 15) | |
14035 | { | |
14036 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
14037 | val &= 0xf; | |
14038 | } | |
14039 | else | |
14040 | { | |
14041 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14042 | val = 0; | |
14043 | } | |
14044 | return (extval << 16) | val; | |
14045 | } | |
14046 | ||
5c04167a RS |
14047 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
14048 | extending it if necessary. The instruction in *INSN may | |
14049 | already be extended. | |
14050 | ||
43c0598f RS |
14051 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
14052 | if none. In the former case, VAL is a 16-bit number with no | |
14053 | defined signedness. | |
14054 | ||
14055 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14056 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14057 | |
14058 | static void | |
43c0598f RS |
14059 | mips16_immed (char *file, unsigned int line, int type, |
14060 | bfd_reloc_code_real_type reloc, offsetT val, | |
5c04167a | 14061 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14062 | { |
3994f87e | 14063 | const struct mips16_immed_operand *op; |
252b5132 | 14064 | int mintiny, maxtiny; |
252b5132 RH |
14065 | |
14066 | op = mips16_immed_operands; | |
14067 | while (op->type != type) | |
14068 | { | |
14069 | ++op; | |
9c2799c2 | 14070 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
14071 | } |
14072 | ||
14073 | if (op->unsp) | |
14074 | { | |
14075 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
14076 | { | |
14077 | mintiny = 1; | |
14078 | maxtiny = 1 << op->nbits; | |
14079 | } | |
14080 | else | |
14081 | { | |
14082 | mintiny = 0; | |
14083 | maxtiny = (1 << op->nbits) - 1; | |
14084 | } | |
43c0598f RS |
14085 | if (reloc != BFD_RELOC_UNUSED) |
14086 | val &= 0xffff; | |
252b5132 RH |
14087 | } |
14088 | else | |
14089 | { | |
14090 | mintiny = - (1 << (op->nbits - 1)); | |
14091 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
43c0598f RS |
14092 | if (reloc != BFD_RELOC_UNUSED) |
14093 | val = SEXT_16BIT (val); | |
252b5132 RH |
14094 | } |
14095 | ||
14096 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
14097 | if (type == 'p' || type == 'q') | |
14098 | val /= 2; | |
14099 | ||
14100 | if ((val & ((1 << op->shift) - 1)) != 0 | |
14101 | || val < (mintiny << op->shift) | |
14102 | || val > (maxtiny << op->shift)) | |
5c04167a RS |
14103 | { |
14104 | /* We need an extended instruction. */ | |
14105 | if (user_insn_length == 2) | |
14106 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14107 | else | |
14108 | *insn |= MIPS16_EXTEND; | |
14109 | } | |
14110 | else if (user_insn_length == 4) | |
14111 | { | |
14112 | /* The operand doesn't force an unextended instruction to be extended. | |
14113 | Warn if the user wanted an extended instruction anyway. */ | |
14114 | *insn |= MIPS16_EXTEND; | |
14115 | as_warn_where (file, line, | |
14116 | _("extended operand requested but not required")); | |
14117 | } | |
252b5132 | 14118 | |
5c04167a | 14119 | if (mips16_opcode_length (*insn) == 2) |
252b5132 RH |
14120 | { |
14121 | int insnval; | |
14122 | ||
252b5132 RH |
14123 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
14124 | insnval <<= op->op_shift; | |
14125 | *insn |= insnval; | |
14126 | } | |
14127 | else | |
14128 | { | |
14129 | long minext, maxext; | |
252b5132 | 14130 | |
43c0598f | 14131 | if (reloc == BFD_RELOC_UNUSED) |
252b5132 | 14132 | { |
43c0598f RS |
14133 | if (op->extu) |
14134 | { | |
14135 | minext = 0; | |
14136 | maxext = (1 << op->extbits) - 1; | |
14137 | } | |
14138 | else | |
14139 | { | |
14140 | minext = - (1 << (op->extbits - 1)); | |
14141 | maxext = (1 << (op->extbits - 1)) - 1; | |
14142 | } | |
14143 | if (val < minext || val > maxext) | |
14144 | as_bad_where (file, line, | |
14145 | _("operand value out of range for instruction")); | |
252b5132 | 14146 | } |
252b5132 | 14147 | |
b886a2ab | 14148 | *insn |= mips16_immed_extend (val, op->extbits); |
252b5132 RH |
14149 | } |
14150 | } | |
14151 | \f | |
d6f16593 | 14152 | struct percent_op_match |
ad8d3bb3 | 14153 | { |
5e0116d5 RS |
14154 | const char *str; |
14155 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14156 | }; |
14157 | ||
14158 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14159 | { |
5e0116d5 | 14160 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 14161 | #ifdef OBJ_ELF |
5e0116d5 RS |
14162 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14163 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14164 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14165 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14166 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14167 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14168 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14169 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14170 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14171 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
14172 | {"%half", BFD_RELOC_16}, | |
14173 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14174 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14175 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14176 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14177 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14178 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14179 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14180 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14181 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14182 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 14183 | #endif |
5e0116d5 | 14184 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
14185 | }; |
14186 | ||
d6f16593 MR |
14187 | static const struct percent_op_match mips16_percent_op[] = |
14188 | { | |
14189 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
14190 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
14191 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14192 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14193 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14194 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14195 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14196 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14197 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14198 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14199 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14200 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14201 | }; |
14202 | ||
252b5132 | 14203 | |
5e0116d5 RS |
14204 | /* Return true if *STR points to a relocation operator. When returning true, |
14205 | move *STR over the operator and store its relocation code in *RELOC. | |
14206 | Leave both *STR and *RELOC alone when returning false. */ | |
14207 | ||
14208 | static bfd_boolean | |
17a2f251 | 14209 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14210 | { |
d6f16593 MR |
14211 | const struct percent_op_match *percent_op; |
14212 | size_t limit, i; | |
14213 | ||
14214 | if (mips_opts.mips16) | |
14215 | { | |
14216 | percent_op = mips16_percent_op; | |
14217 | limit = ARRAY_SIZE (mips16_percent_op); | |
14218 | } | |
14219 | else | |
14220 | { | |
14221 | percent_op = mips_percent_op; | |
14222 | limit = ARRAY_SIZE (mips_percent_op); | |
14223 | } | |
76b3015f | 14224 | |
d6f16593 | 14225 | for (i = 0; i < limit; i++) |
5e0116d5 | 14226 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14227 | { |
3f98094e DJ |
14228 | int len = strlen (percent_op[i].str); |
14229 | ||
14230 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14231 | continue; | |
14232 | ||
5e0116d5 RS |
14233 | *str += strlen (percent_op[i].str); |
14234 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14235 | |
5e0116d5 RS |
14236 | /* Check whether the output BFD supports this relocation. |
14237 | If not, issue an error and fall back on something safe. */ | |
14238 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14239 | { |
20203fb9 | 14240 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14241 | percent_op[i].str); |
01a3f561 | 14242 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14243 | } |
5e0116d5 | 14244 | return TRUE; |
394f9b3a | 14245 | } |
5e0116d5 | 14246 | return FALSE; |
394f9b3a | 14247 | } |
ad8d3bb3 | 14248 | |
ad8d3bb3 | 14249 | |
5e0116d5 RS |
14250 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14251 | expression in *EP and the relocations in the array starting | |
14252 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14253 | |
01a3f561 | 14254 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14255 | |
5e0116d5 | 14256 | static size_t |
17a2f251 TS |
14257 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14258 | char *str) | |
ad8d3bb3 | 14259 | { |
5e0116d5 RS |
14260 | bfd_reloc_code_real_type reversed_reloc[3]; |
14261 | size_t reloc_index, i; | |
09b8f35a RS |
14262 | int crux_depth, str_depth; |
14263 | char *crux; | |
5e0116d5 RS |
14264 | |
14265 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14266 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14267 | of the main expression and with CRUX_DEPTH containing the number | |
14268 | of open brackets at that point. */ | |
14269 | reloc_index = -1; | |
14270 | str_depth = 0; | |
14271 | do | |
fb1b3232 | 14272 | { |
09b8f35a RS |
14273 | reloc_index++; |
14274 | crux = str; | |
14275 | crux_depth = str_depth; | |
14276 | ||
14277 | /* Skip over whitespace and brackets, keeping count of the number | |
14278 | of brackets. */ | |
14279 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14280 | if (*str++ == '(') | |
14281 | str_depth++; | |
5e0116d5 | 14282 | } |
09b8f35a RS |
14283 | while (*str == '%' |
14284 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14285 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14286 | |
09b8f35a | 14287 | my_getExpression (ep, crux); |
5e0116d5 | 14288 | str = expr_end; |
394f9b3a | 14289 | |
5e0116d5 | 14290 | /* Match every open bracket. */ |
09b8f35a | 14291 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14292 | if (*str++ == ')') |
09b8f35a | 14293 | crux_depth--; |
394f9b3a | 14294 | |
09b8f35a | 14295 | if (crux_depth > 0) |
20203fb9 | 14296 | as_bad (_("unclosed '('")); |
394f9b3a | 14297 | |
5e0116d5 | 14298 | expr_end = str; |
252b5132 | 14299 | |
01a3f561 | 14300 | if (reloc_index != 0) |
64bdfcaf RS |
14301 | { |
14302 | prev_reloc_op_frag = frag_now; | |
14303 | for (i = 0; i < reloc_index; i++) | |
14304 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14305 | } | |
fb1b3232 | 14306 | |
5e0116d5 | 14307 | return reloc_index; |
252b5132 RH |
14308 | } |
14309 | ||
14310 | static void | |
17a2f251 | 14311 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14312 | { |
14313 | char *save_in; | |
14314 | ||
14315 | save_in = input_line_pointer; | |
14316 | input_line_pointer = str; | |
14317 | expression (ep); | |
14318 | expr_end = input_line_pointer; | |
14319 | input_line_pointer = save_in; | |
252b5132 RH |
14320 | } |
14321 | ||
252b5132 | 14322 | char * |
17a2f251 | 14323 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14324 | { |
499ac353 | 14325 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14326 | } |
14327 | ||
14328 | void | |
17a2f251 | 14329 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14330 | { |
14331 | if (target_big_endian) | |
14332 | number_to_chars_bigendian (buf, val, n); | |
14333 | else | |
14334 | number_to_chars_littleendian (buf, val, n); | |
14335 | } | |
14336 | \f | |
ae948b86 | 14337 | #ifdef OBJ_ELF |
e013f690 TS |
14338 | static int support_64bit_objects(void) |
14339 | { | |
14340 | const char **list, **l; | |
aa3d8fdf | 14341 | int yes; |
e013f690 TS |
14342 | |
14343 | list = bfd_target_list (); | |
14344 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14345 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14346 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14347 | break; |
aa3d8fdf | 14348 | yes = (*l != NULL); |
e013f690 | 14349 | free (list); |
aa3d8fdf | 14350 | return yes; |
e013f690 | 14351 | } |
ae948b86 | 14352 | #endif /* OBJ_ELF */ |
e013f690 | 14353 | |
78849248 | 14354 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 14355 | |
23fce1e3 NC |
14356 | enum options |
14357 | { | |
14358 | OPTION_MARCH = OPTION_MD_BASE, | |
14359 | OPTION_MTUNE, | |
14360 | OPTION_MIPS1, | |
14361 | OPTION_MIPS2, | |
14362 | OPTION_MIPS3, | |
14363 | OPTION_MIPS4, | |
14364 | OPTION_MIPS5, | |
14365 | OPTION_MIPS32, | |
14366 | OPTION_MIPS64, | |
14367 | OPTION_MIPS32R2, | |
14368 | OPTION_MIPS64R2, | |
14369 | OPTION_MIPS16, | |
14370 | OPTION_NO_MIPS16, | |
14371 | OPTION_MIPS3D, | |
14372 | OPTION_NO_MIPS3D, | |
14373 | OPTION_MDMX, | |
14374 | OPTION_NO_MDMX, | |
14375 | OPTION_DSP, | |
14376 | OPTION_NO_DSP, | |
14377 | OPTION_MT, | |
14378 | OPTION_NO_MT, | |
14379 | OPTION_SMARTMIPS, | |
14380 | OPTION_NO_SMARTMIPS, | |
14381 | OPTION_DSPR2, | |
14382 | OPTION_NO_DSPR2, | |
df58fc94 RS |
14383 | OPTION_MICROMIPS, |
14384 | OPTION_NO_MICROMIPS, | |
dec0624d MR |
14385 | OPTION_MCU, |
14386 | OPTION_NO_MCU, | |
23fce1e3 NC |
14387 | OPTION_COMPAT_ARCH_BASE, |
14388 | OPTION_M4650, | |
14389 | OPTION_NO_M4650, | |
14390 | OPTION_M4010, | |
14391 | OPTION_NO_M4010, | |
14392 | OPTION_M4100, | |
14393 | OPTION_NO_M4100, | |
14394 | OPTION_M3900, | |
14395 | OPTION_NO_M3900, | |
14396 | OPTION_M7000_HILO_FIX, | |
6a32d874 CM |
14397 | OPTION_MNO_7000_HILO_FIX, |
14398 | OPTION_FIX_24K, | |
14399 | OPTION_NO_FIX_24K, | |
c67a084a NC |
14400 | OPTION_FIX_LOONGSON2F_JUMP, |
14401 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
14402 | OPTION_FIX_LOONGSON2F_NOP, | |
14403 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
23fce1e3 NC |
14404 | OPTION_FIX_VR4120, |
14405 | OPTION_NO_FIX_VR4120, | |
14406 | OPTION_FIX_VR4130, | |
14407 | OPTION_NO_FIX_VR4130, | |
d954098f DD |
14408 | OPTION_FIX_CN63XXP1, |
14409 | OPTION_NO_FIX_CN63XXP1, | |
23fce1e3 NC |
14410 | OPTION_TRAP, |
14411 | OPTION_BREAK, | |
14412 | OPTION_EB, | |
14413 | OPTION_EL, | |
14414 | OPTION_FP32, | |
14415 | OPTION_GP32, | |
14416 | OPTION_CONSTRUCT_FLOATS, | |
14417 | OPTION_NO_CONSTRUCT_FLOATS, | |
14418 | OPTION_FP64, | |
14419 | OPTION_GP64, | |
14420 | OPTION_RELAX_BRANCH, | |
14421 | OPTION_NO_RELAX_BRANCH, | |
14422 | OPTION_MSHARED, | |
14423 | OPTION_MNO_SHARED, | |
14424 | OPTION_MSYM32, | |
14425 | OPTION_MNO_SYM32, | |
14426 | OPTION_SOFT_FLOAT, | |
14427 | OPTION_HARD_FLOAT, | |
14428 | OPTION_SINGLE_FLOAT, | |
14429 | OPTION_DOUBLE_FLOAT, | |
14430 | OPTION_32, | |
14431 | #ifdef OBJ_ELF | |
14432 | OPTION_CALL_SHARED, | |
14433 | OPTION_CALL_NONPIC, | |
14434 | OPTION_NON_SHARED, | |
14435 | OPTION_XGOT, | |
14436 | OPTION_MABI, | |
14437 | OPTION_N32, | |
14438 | OPTION_64, | |
14439 | OPTION_MDEBUG, | |
14440 | OPTION_NO_MDEBUG, | |
14441 | OPTION_PDR, | |
14442 | OPTION_NO_PDR, | |
14443 | OPTION_MVXWORKS_PIC, | |
14444 | #endif /* OBJ_ELF */ | |
14445 | OPTION_END_OF_ENUM | |
14446 | }; | |
14447 | ||
e972090a NC |
14448 | struct option md_longopts[] = |
14449 | { | |
f9b4148d | 14450 | /* Options which specify architecture. */ |
f9b4148d | 14451 | {"march", required_argument, NULL, OPTION_MARCH}, |
f9b4148d | 14452 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
252b5132 RH |
14453 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
14454 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
252b5132 | 14455 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
252b5132 | 14456 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
252b5132 | 14457 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
ae948b86 | 14458 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
ae948b86 | 14459 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
ae948b86 | 14460 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d | 14461 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
5f74bc13 | 14462 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
f9b4148d CD |
14463 | |
14464 | /* Options which specify Application Specific Extensions (ASEs). */ | |
f9b4148d | 14465 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
f9b4148d | 14466 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f9b4148d | 14467 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
f9b4148d | 14468 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
f9b4148d | 14469 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
f9b4148d | 14470 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
74cd071d | 14471 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
74cd071d | 14472 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
ef2e4d86 | 14473 | {"mmt", no_argument, NULL, OPTION_MT}, |
ef2e4d86 | 14474 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
e16bfa71 | 14475 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
e16bfa71 | 14476 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
8b082fb1 | 14477 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
8b082fb1 | 14478 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
df58fc94 RS |
14479 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, |
14480 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
dec0624d MR |
14481 | {"mmcu", no_argument, NULL, OPTION_MCU}, |
14482 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
f9b4148d CD |
14483 | |
14484 | /* Old-style architecture options. Don't add more of these. */ | |
f9b4148d | 14485 | {"m4650", no_argument, NULL, OPTION_M4650}, |
f9b4148d | 14486 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
f9b4148d | 14487 | {"m4010", no_argument, NULL, OPTION_M4010}, |
f9b4148d | 14488 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
f9b4148d | 14489 | {"m4100", no_argument, NULL, OPTION_M4100}, |
f9b4148d | 14490 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
f9b4148d | 14491 | {"m3900", no_argument, NULL, OPTION_M3900}, |
f9b4148d CD |
14492 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
14493 | ||
14494 | /* Options which enable bug fixes. */ | |
f9b4148d | 14495 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
f9b4148d CD |
14496 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
14497 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
c67a084a NC |
14498 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
14499 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
14500 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
14501 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
d766e8ec RS |
14502 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
14503 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
14504 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
14505 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
6a32d874 CM |
14506 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
14507 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
d954098f DD |
14508 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
14509 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
f9b4148d CD |
14510 | |
14511 | /* Miscellaneous options. */ | |
252b5132 RH |
14512 | {"trap", no_argument, NULL, OPTION_TRAP}, |
14513 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
252b5132 RH |
14514 | {"break", no_argument, NULL, OPTION_BREAK}, |
14515 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
252b5132 | 14516 | {"EB", no_argument, NULL, OPTION_EB}, |
252b5132 | 14517 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 14518 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
c97ef257 | 14519 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
119d663a | 14520 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
119d663a | 14521 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
316f5878 | 14522 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
ae948b86 | 14523 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
4a6a3df4 AO |
14524 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
14525 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
14526 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
14527 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
14528 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
14529 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
14530 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
14531 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
037b32b9 AN |
14532 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
14533 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
23fce1e3 NC |
14534 | |
14535 | /* Strictly speaking this next option is ELF specific, | |
14536 | but we allow it for other ports as well in order to | |
14537 | make testing easier. */ | |
14538 | {"32", no_argument, NULL, OPTION_32}, | |
037b32b9 | 14539 | |
f9b4148d | 14540 | /* ELF-specific options. */ |
156c2f8b | 14541 | #ifdef OBJ_ELF |
156c2f8b NC |
14542 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
14543 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
861fb55a | 14544 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
156c2f8b NC |
14545 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
14546 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
ae948b86 | 14547 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e013f690 | 14548 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b | 14549 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a | 14550 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
ecb4347a | 14551 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
dcd410fe | 14552 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
dcd410fe | 14553 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
0a44bf69 | 14554 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
ae948b86 | 14555 | #endif /* OBJ_ELF */ |
f9b4148d | 14556 | |
252b5132 RH |
14557 | {NULL, no_argument, NULL, 0} |
14558 | }; | |
156c2f8b | 14559 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 14560 | |
316f5878 RS |
14561 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14562 | NEW_VALUE. Warn if another value was already specified. Note: | |
14563 | we have to defer parsing the -march and -mtune arguments in order | |
14564 | to handle 'from-abi' correctly, since the ABI might be specified | |
14565 | in a later argument. */ | |
14566 | ||
14567 | static void | |
17a2f251 | 14568 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14569 | { |
14570 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
14571 | as_warn (_("A different %s was already specified, is now %s"), | |
14572 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
14573 | new_value); | |
14574 | ||
14575 | *string_ptr = new_value; | |
14576 | } | |
14577 | ||
252b5132 | 14578 | int |
17a2f251 | 14579 | md_parse_option (int c, char *arg) |
252b5132 RH |
14580 | { |
14581 | switch (c) | |
14582 | { | |
119d663a NC |
14583 | case OPTION_CONSTRUCT_FLOATS: |
14584 | mips_disable_float_construction = 0; | |
14585 | break; | |
bdaaa2e1 | 14586 | |
119d663a NC |
14587 | case OPTION_NO_CONSTRUCT_FLOATS: |
14588 | mips_disable_float_construction = 1; | |
14589 | break; | |
bdaaa2e1 | 14590 | |
252b5132 RH |
14591 | case OPTION_TRAP: |
14592 | mips_trap = 1; | |
14593 | break; | |
14594 | ||
14595 | case OPTION_BREAK: | |
14596 | mips_trap = 0; | |
14597 | break; | |
14598 | ||
14599 | case OPTION_EB: | |
14600 | target_big_endian = 1; | |
14601 | break; | |
14602 | ||
14603 | case OPTION_EL: | |
14604 | target_big_endian = 0; | |
14605 | break; | |
14606 | ||
14607 | case 'O': | |
4ffff32f TS |
14608 | if (arg == NULL) |
14609 | mips_optimize = 1; | |
14610 | else if (arg[0] == '0') | |
14611 | mips_optimize = 0; | |
14612 | else if (arg[0] == '1') | |
252b5132 RH |
14613 | mips_optimize = 1; |
14614 | else | |
14615 | mips_optimize = 2; | |
14616 | break; | |
14617 | ||
14618 | case 'g': | |
14619 | if (arg == NULL) | |
14620 | mips_debug = 2; | |
14621 | else | |
14622 | mips_debug = atoi (arg); | |
252b5132 RH |
14623 | break; |
14624 | ||
14625 | case OPTION_MIPS1: | |
316f5878 | 14626 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
14627 | break; |
14628 | ||
14629 | case OPTION_MIPS2: | |
316f5878 | 14630 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
14631 | break; |
14632 | ||
14633 | case OPTION_MIPS3: | |
316f5878 | 14634 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
14635 | break; |
14636 | ||
14637 | case OPTION_MIPS4: | |
316f5878 | 14638 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
14639 | break; |
14640 | ||
84ea6cf2 | 14641 | case OPTION_MIPS5: |
316f5878 | 14642 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
14643 | break; |
14644 | ||
e7af610e | 14645 | case OPTION_MIPS32: |
316f5878 | 14646 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
14647 | break; |
14648 | ||
af7ee8bf CD |
14649 | case OPTION_MIPS32R2: |
14650 | file_mips_isa = ISA_MIPS32R2; | |
14651 | break; | |
14652 | ||
5f74bc13 CD |
14653 | case OPTION_MIPS64R2: |
14654 | file_mips_isa = ISA_MIPS64R2; | |
14655 | break; | |
14656 | ||
84ea6cf2 | 14657 | case OPTION_MIPS64: |
316f5878 | 14658 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
14659 | break; |
14660 | ||
ec68c924 | 14661 | case OPTION_MTUNE: |
316f5878 RS |
14662 | mips_set_option_string (&mips_tune_string, arg); |
14663 | break; | |
ec68c924 | 14664 | |
316f5878 RS |
14665 | case OPTION_MARCH: |
14666 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14667 | break; |
14668 | ||
14669 | case OPTION_M4650: | |
316f5878 RS |
14670 | mips_set_option_string (&mips_arch_string, "4650"); |
14671 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14672 | break; |
14673 | ||
14674 | case OPTION_NO_M4650: | |
14675 | break; | |
14676 | ||
14677 | case OPTION_M4010: | |
316f5878 RS |
14678 | mips_set_option_string (&mips_arch_string, "4010"); |
14679 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14680 | break; |
14681 | ||
14682 | case OPTION_NO_M4010: | |
14683 | break; | |
14684 | ||
14685 | case OPTION_M4100: | |
316f5878 RS |
14686 | mips_set_option_string (&mips_arch_string, "4100"); |
14687 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14688 | break; |
14689 | ||
14690 | case OPTION_NO_M4100: | |
14691 | break; | |
14692 | ||
252b5132 | 14693 | case OPTION_M3900: |
316f5878 RS |
14694 | mips_set_option_string (&mips_arch_string, "3900"); |
14695 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14696 | break; |
bdaaa2e1 | 14697 | |
252b5132 RH |
14698 | case OPTION_NO_M3900: |
14699 | break; | |
14700 | ||
deec1734 CD |
14701 | case OPTION_MDMX: |
14702 | mips_opts.ase_mdmx = 1; | |
14703 | break; | |
14704 | ||
14705 | case OPTION_NO_MDMX: | |
14706 | mips_opts.ase_mdmx = 0; | |
14707 | break; | |
14708 | ||
74cd071d CF |
14709 | case OPTION_DSP: |
14710 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 14711 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
14712 | break; |
14713 | ||
14714 | case OPTION_NO_DSP: | |
8b082fb1 TS |
14715 | mips_opts.ase_dsp = 0; |
14716 | mips_opts.ase_dspr2 = 0; | |
14717 | break; | |
14718 | ||
14719 | case OPTION_DSPR2: | |
14720 | mips_opts.ase_dspr2 = 1; | |
14721 | mips_opts.ase_dsp = 1; | |
14722 | break; | |
14723 | ||
14724 | case OPTION_NO_DSPR2: | |
14725 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
14726 | mips_opts.ase_dsp = 0; |
14727 | break; | |
14728 | ||
ef2e4d86 CF |
14729 | case OPTION_MT: |
14730 | mips_opts.ase_mt = 1; | |
14731 | break; | |
14732 | ||
14733 | case OPTION_NO_MT: | |
14734 | mips_opts.ase_mt = 0; | |
14735 | break; | |
14736 | ||
dec0624d MR |
14737 | case OPTION_MCU: |
14738 | mips_opts.ase_mcu = 1; | |
14739 | break; | |
14740 | ||
14741 | case OPTION_NO_MCU: | |
14742 | mips_opts.ase_mcu = 0; | |
14743 | break; | |
14744 | ||
df58fc94 RS |
14745 | case OPTION_MICROMIPS: |
14746 | if (mips_opts.mips16 == 1) | |
14747 | { | |
14748 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14749 | return 0; | |
14750 | } | |
14751 | mips_opts.micromips = 1; | |
14752 | mips_no_prev_insn (); | |
14753 | break; | |
14754 | ||
14755 | case OPTION_NO_MICROMIPS: | |
14756 | mips_opts.micromips = 0; | |
14757 | mips_no_prev_insn (); | |
14758 | break; | |
14759 | ||
252b5132 | 14760 | case OPTION_MIPS16: |
df58fc94 RS |
14761 | if (mips_opts.micromips == 1) |
14762 | { | |
14763 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14764 | return 0; | |
14765 | } | |
252b5132 | 14766 | mips_opts.mips16 = 1; |
7d10b47d | 14767 | mips_no_prev_insn (); |
252b5132 RH |
14768 | break; |
14769 | ||
14770 | case OPTION_NO_MIPS16: | |
14771 | mips_opts.mips16 = 0; | |
7d10b47d | 14772 | mips_no_prev_insn (); |
252b5132 RH |
14773 | break; |
14774 | ||
1f25f5d3 CD |
14775 | case OPTION_MIPS3D: |
14776 | mips_opts.ase_mips3d = 1; | |
14777 | break; | |
14778 | ||
14779 | case OPTION_NO_MIPS3D: | |
14780 | mips_opts.ase_mips3d = 0; | |
14781 | break; | |
14782 | ||
e16bfa71 TS |
14783 | case OPTION_SMARTMIPS: |
14784 | mips_opts.ase_smartmips = 1; | |
14785 | break; | |
14786 | ||
14787 | case OPTION_NO_SMARTMIPS: | |
14788 | mips_opts.ase_smartmips = 0; | |
14789 | break; | |
14790 | ||
6a32d874 CM |
14791 | case OPTION_FIX_24K: |
14792 | mips_fix_24k = 1; | |
14793 | break; | |
14794 | ||
14795 | case OPTION_NO_FIX_24K: | |
14796 | mips_fix_24k = 0; | |
14797 | break; | |
14798 | ||
c67a084a NC |
14799 | case OPTION_FIX_LOONGSON2F_JUMP: |
14800 | mips_fix_loongson2f_jump = TRUE; | |
14801 | break; | |
14802 | ||
14803 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14804 | mips_fix_loongson2f_jump = FALSE; | |
14805 | break; | |
14806 | ||
14807 | case OPTION_FIX_LOONGSON2F_NOP: | |
14808 | mips_fix_loongson2f_nop = TRUE; | |
14809 | break; | |
14810 | ||
14811 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
14812 | mips_fix_loongson2f_nop = FALSE; | |
14813 | break; | |
14814 | ||
d766e8ec RS |
14815 | case OPTION_FIX_VR4120: |
14816 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
14817 | break; |
14818 | ||
d766e8ec RS |
14819 | case OPTION_NO_FIX_VR4120: |
14820 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
14821 | break; |
14822 | ||
7d8e00cf RS |
14823 | case OPTION_FIX_VR4130: |
14824 | mips_fix_vr4130 = 1; | |
14825 | break; | |
14826 | ||
14827 | case OPTION_NO_FIX_VR4130: | |
14828 | mips_fix_vr4130 = 0; | |
14829 | break; | |
14830 | ||
d954098f DD |
14831 | case OPTION_FIX_CN63XXP1: |
14832 | mips_fix_cn63xxp1 = TRUE; | |
14833 | break; | |
14834 | ||
14835 | case OPTION_NO_FIX_CN63XXP1: | |
14836 | mips_fix_cn63xxp1 = FALSE; | |
14837 | break; | |
14838 | ||
4a6a3df4 AO |
14839 | case OPTION_RELAX_BRANCH: |
14840 | mips_relax_branch = 1; | |
14841 | break; | |
14842 | ||
14843 | case OPTION_NO_RELAX_BRANCH: | |
14844 | mips_relax_branch = 0; | |
14845 | break; | |
14846 | ||
aa6975fb ILT |
14847 | case OPTION_MSHARED: |
14848 | mips_in_shared = TRUE; | |
14849 | break; | |
14850 | ||
14851 | case OPTION_MNO_SHARED: | |
14852 | mips_in_shared = FALSE; | |
14853 | break; | |
14854 | ||
aed1a261 RS |
14855 | case OPTION_MSYM32: |
14856 | mips_opts.sym32 = TRUE; | |
14857 | break; | |
14858 | ||
14859 | case OPTION_MNO_SYM32: | |
14860 | mips_opts.sym32 = FALSE; | |
14861 | break; | |
14862 | ||
0f074f60 | 14863 | #ifdef OBJ_ELF |
252b5132 RH |
14864 | /* When generating ELF code, we permit -KPIC and -call_shared to |
14865 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
14866 | intended to be compatible with Irix 5. */ | |
14867 | case OPTION_CALL_SHARED: | |
f43abd2b | 14868 | if (!IS_ELF) |
252b5132 RH |
14869 | { |
14870 | as_bad (_("-call_shared is supported only for ELF format")); | |
14871 | return 0; | |
14872 | } | |
14873 | mips_pic = SVR4_PIC; | |
143d77c5 | 14874 | mips_abicalls = TRUE; |
252b5132 RH |
14875 | break; |
14876 | ||
861fb55a DJ |
14877 | case OPTION_CALL_NONPIC: |
14878 | if (!IS_ELF) | |
14879 | { | |
14880 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
14881 | return 0; | |
14882 | } | |
14883 | mips_pic = NO_PIC; | |
14884 | mips_abicalls = TRUE; | |
14885 | break; | |
14886 | ||
252b5132 | 14887 | case OPTION_NON_SHARED: |
f43abd2b | 14888 | if (!IS_ELF) |
252b5132 RH |
14889 | { |
14890 | as_bad (_("-non_shared is supported only for ELF format")); | |
14891 | return 0; | |
14892 | } | |
14893 | mips_pic = NO_PIC; | |
143d77c5 | 14894 | mips_abicalls = FALSE; |
252b5132 RH |
14895 | break; |
14896 | ||
44075ae2 TS |
14897 | /* The -xgot option tells the assembler to use 32 bit offsets |
14898 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
14899 | compatibility. */ |
14900 | case OPTION_XGOT: | |
14901 | mips_big_got = 1; | |
14902 | break; | |
0f074f60 | 14903 | #endif /* OBJ_ELF */ |
252b5132 RH |
14904 | |
14905 | case 'G': | |
6caf9ef4 TS |
14906 | g_switch_value = atoi (arg); |
14907 | g_switch_seen = 1; | |
252b5132 RH |
14908 | break; |
14909 | ||
34ba82a8 TS |
14910 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
14911 | and -mabi=64. */ | |
252b5132 | 14912 | case OPTION_32: |
23fce1e3 NC |
14913 | if (IS_ELF) |
14914 | mips_abi = O32_ABI; | |
14915 | /* We silently ignore -32 for non-ELF targets. This greatly | |
14916 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
14917 | break; |
14918 | ||
23fce1e3 | 14919 | #ifdef OBJ_ELF |
e013f690 | 14920 | case OPTION_N32: |
f43abd2b | 14921 | if (!IS_ELF) |
34ba82a8 TS |
14922 | { |
14923 | as_bad (_("-n32 is supported for ELF format only")); | |
14924 | return 0; | |
14925 | } | |
316f5878 | 14926 | mips_abi = N32_ABI; |
e013f690 | 14927 | break; |
252b5132 | 14928 | |
e013f690 | 14929 | case OPTION_64: |
f43abd2b | 14930 | if (!IS_ELF) |
34ba82a8 TS |
14931 | { |
14932 | as_bad (_("-64 is supported for ELF format only")); | |
14933 | return 0; | |
14934 | } | |
316f5878 | 14935 | mips_abi = N64_ABI; |
f43abd2b | 14936 | if (!support_64bit_objects()) |
e013f690 | 14937 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 14938 | break; |
ae948b86 | 14939 | #endif /* OBJ_ELF */ |
252b5132 | 14940 | |
c97ef257 | 14941 | case OPTION_GP32: |
a325df1d | 14942 | file_mips_gp32 = 1; |
c97ef257 AH |
14943 | break; |
14944 | ||
14945 | case OPTION_GP64: | |
a325df1d | 14946 | file_mips_gp32 = 0; |
c97ef257 | 14947 | break; |
252b5132 | 14948 | |
ca4e0257 | 14949 | case OPTION_FP32: |
a325df1d | 14950 | file_mips_fp32 = 1; |
316f5878 RS |
14951 | break; |
14952 | ||
14953 | case OPTION_FP64: | |
14954 | file_mips_fp32 = 0; | |
ca4e0257 RS |
14955 | break; |
14956 | ||
037b32b9 AN |
14957 | case OPTION_SINGLE_FLOAT: |
14958 | file_mips_single_float = 1; | |
14959 | break; | |
14960 | ||
14961 | case OPTION_DOUBLE_FLOAT: | |
14962 | file_mips_single_float = 0; | |
14963 | break; | |
14964 | ||
14965 | case OPTION_SOFT_FLOAT: | |
14966 | file_mips_soft_float = 1; | |
14967 | break; | |
14968 | ||
14969 | case OPTION_HARD_FLOAT: | |
14970 | file_mips_soft_float = 0; | |
14971 | break; | |
14972 | ||
ae948b86 | 14973 | #ifdef OBJ_ELF |
252b5132 | 14974 | case OPTION_MABI: |
f43abd2b | 14975 | if (!IS_ELF) |
34ba82a8 TS |
14976 | { |
14977 | as_bad (_("-mabi is supported for ELF format only")); | |
14978 | return 0; | |
14979 | } | |
e013f690 | 14980 | if (strcmp (arg, "32") == 0) |
316f5878 | 14981 | mips_abi = O32_ABI; |
e013f690 | 14982 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 14983 | mips_abi = O64_ABI; |
e013f690 | 14984 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 14985 | mips_abi = N32_ABI; |
e013f690 TS |
14986 | else if (strcmp (arg, "64") == 0) |
14987 | { | |
316f5878 | 14988 | mips_abi = N64_ABI; |
e013f690 TS |
14989 | if (! support_64bit_objects()) |
14990 | as_fatal (_("No compiled in support for 64 bit object file " | |
14991 | "format")); | |
14992 | } | |
14993 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 14994 | mips_abi = EABI_ABI; |
e013f690 | 14995 | else |
da0e507f TS |
14996 | { |
14997 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
14998 | return 0; | |
14999 | } | |
252b5132 | 15000 | break; |
e013f690 | 15001 | #endif /* OBJ_ELF */ |
252b5132 | 15002 | |
6b76fefe | 15003 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 15004 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
15005 | break; |
15006 | ||
9ee72ff1 | 15007 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 15008 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
15009 | break; |
15010 | ||
ecb4347a DJ |
15011 | #ifdef OBJ_ELF |
15012 | case OPTION_MDEBUG: | |
b34976b6 | 15013 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
15014 | break; |
15015 | ||
15016 | case OPTION_NO_MDEBUG: | |
b34976b6 | 15017 | mips_flag_mdebug = FALSE; |
ecb4347a | 15018 | break; |
dcd410fe RO |
15019 | |
15020 | case OPTION_PDR: | |
15021 | mips_flag_pdr = TRUE; | |
15022 | break; | |
15023 | ||
15024 | case OPTION_NO_PDR: | |
15025 | mips_flag_pdr = FALSE; | |
15026 | break; | |
0a44bf69 RS |
15027 | |
15028 | case OPTION_MVXWORKS_PIC: | |
15029 | mips_pic = VXWORKS_PIC; | |
15030 | break; | |
ecb4347a DJ |
15031 | #endif /* OBJ_ELF */ |
15032 | ||
252b5132 RH |
15033 | default: |
15034 | return 0; | |
15035 | } | |
15036 | ||
c67a084a NC |
15037 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
15038 | ||
252b5132 RH |
15039 | return 1; |
15040 | } | |
316f5878 RS |
15041 | \f |
15042 | /* Set up globals to generate code for the ISA or processor | |
15043 | described by INFO. */ | |
252b5132 | 15044 | |
252b5132 | 15045 | static void |
17a2f251 | 15046 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 15047 | { |
316f5878 | 15048 | if (info != 0) |
252b5132 | 15049 | { |
fef14a42 TS |
15050 | file_mips_arch = info->cpu; |
15051 | mips_opts.arch = info->cpu; | |
316f5878 | 15052 | mips_opts.isa = info->isa; |
252b5132 | 15053 | } |
252b5132 RH |
15054 | } |
15055 | ||
252b5132 | 15056 | |
316f5878 | 15057 | /* Likewise for tuning. */ |
252b5132 | 15058 | |
316f5878 | 15059 | static void |
17a2f251 | 15060 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
15061 | { |
15062 | if (info != 0) | |
fef14a42 | 15063 | mips_tune = info->cpu; |
316f5878 | 15064 | } |
80cc45a5 | 15065 | |
34ba82a8 | 15066 | |
252b5132 | 15067 | void |
17a2f251 | 15068 | mips_after_parse_args (void) |
e9670677 | 15069 | { |
fef14a42 TS |
15070 | const struct mips_cpu_info *arch_info = 0; |
15071 | const struct mips_cpu_info *tune_info = 0; | |
15072 | ||
e9670677 | 15073 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 15074 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 15075 | { |
6caf9ef4 | 15076 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
15077 | as_bad (_("-G not supported in this configuration.")); |
15078 | g_switch_value = 0; | |
15079 | } | |
15080 | ||
cac012d6 AO |
15081 | if (mips_abi == NO_ABI) |
15082 | mips_abi = MIPS_DEFAULT_ABI; | |
15083 | ||
22923709 RS |
15084 | /* The following code determines the architecture and register size. |
15085 | Similar code was added to GCC 3.3 (see override_options() in | |
15086 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
15087 | as much as possible. */ | |
e9670677 | 15088 | |
316f5878 | 15089 | if (mips_arch_string != 0) |
fef14a42 | 15090 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 15091 | |
316f5878 | 15092 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 15093 | { |
316f5878 | 15094 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 15095 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 15096 | the -march selection (if any). */ |
fef14a42 | 15097 | if (arch_info != 0) |
e9670677 | 15098 | { |
316f5878 RS |
15099 | /* -march takes precedence over -mipsN, since it is more descriptive. |
15100 | There's no harm in specifying both as long as the ISA levels | |
15101 | are the same. */ | |
fef14a42 | 15102 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
15103 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
15104 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 15105 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 15106 | } |
316f5878 | 15107 | else |
fef14a42 | 15108 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
15109 | } |
15110 | ||
fef14a42 | 15111 | if (arch_info == 0) |
95bfe26e MF |
15112 | { |
15113 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
15114 | gas_assert (arch_info); | |
15115 | } | |
e9670677 | 15116 | |
fef14a42 | 15117 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 15118 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
15119 | arch_info->name); |
15120 | ||
15121 | mips_set_architecture (arch_info); | |
15122 | ||
15123 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
15124 | if (mips_tune_string != 0) | |
15125 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 15126 | |
fef14a42 TS |
15127 | if (tune_info == 0) |
15128 | mips_set_tune (arch_info); | |
15129 | else | |
15130 | mips_set_tune (tune_info); | |
e9670677 | 15131 | |
316f5878 | 15132 | if (file_mips_gp32 >= 0) |
e9670677 | 15133 | { |
316f5878 RS |
15134 | /* The user specified the size of the integer registers. Make sure |
15135 | it agrees with the ABI and ISA. */ | |
15136 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
15137 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
15138 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15139 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
15140 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15141 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
15142 | } |
15143 | else | |
15144 | { | |
316f5878 RS |
15145 | /* Infer the integer register size from the ABI and processor. |
15146 | Restrict ourselves to 32-bit registers if that's all the | |
15147 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
15148 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15149 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
15150 | } |
15151 | ||
ad3fea08 TS |
15152 | switch (file_mips_fp32) |
15153 | { | |
15154 | default: | |
15155 | case -1: | |
15156 | /* No user specified float register size. | |
15157 | ??? GAS treats single-float processors as though they had 64-bit | |
15158 | float registers (although it complains when double-precision | |
15159 | instructions are used). As things stand, saying they have 32-bit | |
15160 | registers would lead to spurious "register must be even" messages. | |
15161 | So here we assume float registers are never smaller than the | |
15162 | integer ones. */ | |
15163 | if (file_mips_gp32 == 0) | |
15164 | /* 64-bit integer registers implies 64-bit float registers. */ | |
15165 | file_mips_fp32 = 0; | |
15166 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
15167 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15168 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
15169 | file_mips_fp32 = 0; | |
15170 | else | |
15171 | /* 32-bit float registers. */ | |
15172 | file_mips_fp32 = 1; | |
15173 | break; | |
15174 | ||
15175 | /* The user specified the size of the float registers. Check if it | |
15176 | agrees with the ABI and ISA. */ | |
15177 | case 0: | |
15178 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15179 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
15180 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15181 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
15182 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
15183 | break; | |
15184 | case 1: | |
15185 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15186 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
15187 | break; | |
15188 | } | |
e9670677 | 15189 | |
316f5878 | 15190 | /* End of GCC-shared inference code. */ |
e9670677 | 15191 | |
17a2f251 TS |
15192 | /* This flag is set when we have a 64-bit capable CPU but use only |
15193 | 32-bit wide registers. Note that EABI does not use it. */ | |
15194 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
15195 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
15196 | || mips_abi == O32_ABI)) | |
316f5878 | 15197 | mips_32bitmode = 1; |
e9670677 MR |
15198 | |
15199 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
15200 | as_bad (_("trap exception not supported at ISA 1")); | |
15201 | ||
e9670677 MR |
15202 | /* If the selected architecture includes support for ASEs, enable |
15203 | generation of code for them. */ | |
a4672219 | 15204 | if (mips_opts.mips16 == -1) |
fef14a42 | 15205 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
df58fc94 RS |
15206 | if (mips_opts.micromips == -1) |
15207 | mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0; | |
ffdefa66 | 15208 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 15209 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
15210 | && file_mips_fp32 == 0) ? 1 : 0; |
15211 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
15212 | as_bad (_("-mfp32 used with -mips3d")); | |
15213 | ||
ffdefa66 | 15214 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 15215 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
15216 | && file_mips_fp32 == 0) ? 1 : 0; |
15217 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
15218 | as_bad (_("-mfp32 used with -mdmx")); | |
15219 | ||
15220 | if (mips_opts.ase_smartmips == -1) | |
15221 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
15222 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
20203fb9 NC |
15223 | as_warn (_("%s ISA does not support SmartMIPS"), |
15224 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15225 | |
74cd071d | 15226 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
15227 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
15228 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
20203fb9 NC |
15229 | as_warn (_("%s ISA does not support DSP ASE"), |
15230 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15231 | |
8b082fb1 TS |
15232 | if (mips_opts.ase_dspr2 == -1) |
15233 | { | |
15234 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
15235 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
15236 | } | |
15237 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 NC |
15238 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
15239 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 15240 | |
ef2e4d86 | 15241 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
15242 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
15243 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
20203fb9 NC |
15244 | as_warn (_("%s ISA does not support MT ASE"), |
15245 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 15246 | |
dec0624d MR |
15247 | if (mips_opts.ase_mcu == -1) |
15248 | mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0; | |
15249 | if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE) | |
15250 | as_warn (_("%s ISA does not support MCU ASE"), | |
15251 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
15252 | ||
e9670677 | 15253 | file_mips_isa = mips_opts.isa; |
e9670677 MR |
15254 | file_ase_mips3d = mips_opts.ase_mips3d; |
15255 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 15256 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 15257 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 15258 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 15259 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
15260 | mips_opts.gp32 = file_mips_gp32; |
15261 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
15262 | mips_opts.soft_float = file_mips_soft_float; |
15263 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 15264 | |
ecb4347a DJ |
15265 | if (mips_flag_mdebug < 0) |
15266 | { | |
15267 | #ifdef OBJ_MAYBE_ECOFF | |
15268 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
15269 | mips_flag_mdebug = 1; | |
15270 | else | |
15271 | #endif /* OBJ_MAYBE_ECOFF */ | |
15272 | mips_flag_mdebug = 0; | |
15273 | } | |
e9670677 MR |
15274 | } |
15275 | \f | |
15276 | void | |
17a2f251 | 15277 | mips_init_after_args (void) |
252b5132 RH |
15278 | { |
15279 | /* initialize opcodes */ | |
15280 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 15281 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15282 | } |
15283 | ||
15284 | long | |
17a2f251 | 15285 | md_pcrel_from (fixS *fixP) |
252b5132 | 15286 | { |
a7ebbfdf TS |
15287 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
15288 | switch (fixP->fx_r_type) | |
15289 | { | |
df58fc94 RS |
15290 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15291 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15292 | /* Return the address of the delay slot. */ | |
15293 | return addr + 2; | |
15294 | ||
15295 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15296 | case BFD_RELOC_MICROMIPS_JMP: | |
a7ebbfdf TS |
15297 | case BFD_RELOC_16_PCREL_S2: |
15298 | case BFD_RELOC_MIPS_JMP: | |
15299 | /* Return the address of the delay slot. */ | |
15300 | return addr + 4; | |
df58fc94 | 15301 | |
a7ebbfdf | 15302 | default: |
58ea3d6a | 15303 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
15304 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
15305 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15306 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
15307 | return addr; |
15308 | } | |
252b5132 RH |
15309 | } |
15310 | ||
252b5132 RH |
15311 | /* This is called before the symbol table is processed. In order to |
15312 | work with gcc when using mips-tfile, we must keep all local labels. | |
15313 | However, in other cases, we want to discard them. If we were | |
15314 | called with -g, but we didn't see any debugging information, it may | |
15315 | mean that gcc is smuggling debugging information through to | |
15316 | mips-tfile, in which case we must generate all local labels. */ | |
15317 | ||
15318 | void | |
17a2f251 | 15319 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15320 | { |
15321 | #ifndef NO_ECOFF_DEBUGGING | |
15322 | if (ECOFF_DEBUGGING | |
15323 | && mips_debug != 0 | |
15324 | && ! ecoff_debugging_seen) | |
15325 | flag_keep_locals = 1; | |
15326 | #endif | |
15327 | } | |
15328 | ||
3b91255e | 15329 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15330 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15331 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15332 | relocation operators. | |
15333 | ||
15334 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15335 | expression if: | |
15336 | ||
15337 | (a) it refers to the same symbol; and | |
15338 | (b) the offset applied in the %lo() expression is no lower than | |
15339 | the offset applied in the %got() or %hi(). | |
15340 | ||
15341 | (b) allows us to cope with code like: | |
15342 | ||
15343 | lui $4,%hi(foo) | |
15344 | lh $4,%lo(foo+2)($4) | |
15345 | ||
15346 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15347 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15348 | the high 16 bits. | |
15349 | ||
15350 | When several %lo()s match a particular %got() or %hi(), we use the | |
15351 | following rules to distinguish them: | |
15352 | ||
15353 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15354 | higher offsets. | |
15355 | ||
15356 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15357 | that already have a matching %got() or %hi(). | |
15358 | ||
15359 | (3) later %lo()s are better than earlier %lo()s. | |
15360 | ||
15361 | These rules are applied in order. | |
15362 | ||
15363 | (1) means, among other things, that %lo()s with identical offsets are | |
15364 | chosen if they exist. | |
15365 | ||
15366 | (2) means that we won't associate several high-part relocations with | |
15367 | the same low-part relocation unless there's no alternative. Having | |
15368 | several high parts for the same low part is a GNU extension; this rule | |
15369 | allows careful users to avoid it. | |
15370 | ||
15371 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15372 | with the last high-part relocation being at the front of the list. | |
15373 | It therefore makes sense to choose the last matching low-part | |
15374 | relocation, all other things being equal. It's also easier | |
15375 | to code that way. */ | |
252b5132 RH |
15376 | |
15377 | void | |
17a2f251 | 15378 | mips_frob_file (void) |
252b5132 RH |
15379 | { |
15380 | struct mips_hi_fixup *l; | |
35903be0 | 15381 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15382 | |
15383 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15384 | { | |
15385 | segment_info_type *seginfo; | |
3b91255e RS |
15386 | bfd_boolean matched_lo_p; |
15387 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15388 | |
9c2799c2 | 15389 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15390 | |
5919d012 | 15391 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
15392 | there isn't supposed to be a matching LO. Ignore %gots against |
15393 | constants; we'll report an error for those later. */ | |
738e5348 | 15394 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab RS |
15395 | && !(l->fixp->fx_addsy |
15396 | && pic_need_relax (l->fixp->fx_addsy, l->seg))) | |
5919d012 RS |
15397 | continue; |
15398 | ||
15399 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15400 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15401 | continue; |
15402 | ||
252b5132 | 15403 | seginfo = seg_info (l->seg); |
252b5132 | 15404 | |
3b91255e RS |
15405 | /* Set HI_POS to the position of this relocation in the chain. |
15406 | Set LO_POS to the position of the chosen low-part relocation. | |
15407 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15408 | relocation that matches an immediately-preceding high-part | |
15409 | relocation. */ | |
15410 | hi_pos = NULL; | |
15411 | lo_pos = NULL; | |
15412 | matched_lo_p = FALSE; | |
738e5348 | 15413 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15414 | |
3b91255e RS |
15415 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15416 | { | |
15417 | if (*pos == l->fixp) | |
15418 | hi_pos = pos; | |
15419 | ||
35903be0 | 15420 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15421 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15422 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15423 | && (lo_pos == NULL | |
15424 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15425 | || (!matched_lo_p | |
15426 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15427 | lo_pos = pos; | |
15428 | ||
15429 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15430 | && fixup_has_matching_lo_p (*pos)); | |
15431 | } | |
15432 | ||
15433 | /* If we found a match, remove the high-part relocation from its | |
15434 | current position and insert it before the low-part relocation. | |
15435 | Make the offsets match so that fixup_has_matching_lo_p() | |
15436 | will return true. | |
15437 | ||
15438 | We don't warn about unmatched high-part relocations since some | |
15439 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15440 | instructions. */ | |
15441 | if (lo_pos != NULL) | |
15442 | { | |
15443 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15444 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15445 | { |
3b91255e RS |
15446 | *hi_pos = l->fixp->fx_next; |
15447 | l->fixp->fx_next = *lo_pos; | |
15448 | *lo_pos = l->fixp; | |
252b5132 | 15449 | } |
252b5132 RH |
15450 | } |
15451 | } | |
15452 | } | |
15453 | ||
252b5132 | 15454 | int |
17a2f251 | 15455 | mips_force_relocation (fixS *fixp) |
252b5132 | 15456 | { |
ae6063d4 | 15457 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15458 | return 1; |
15459 | ||
df58fc94 RS |
15460 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15461 | so that the linker relaxation can update targets. */ | |
15462 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15463 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15464 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15465 | return 1; | |
15466 | ||
3e722fb5 | 15467 | return 0; |
252b5132 RH |
15468 | } |
15469 | ||
b886a2ab RS |
15470 | /* Read the instruction associated with RELOC from BUF. */ |
15471 | ||
15472 | static unsigned int | |
15473 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
15474 | { | |
15475 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15476 | return read_compressed_insn (buf, 4); | |
15477 | else | |
15478 | return read_insn (buf); | |
15479 | } | |
15480 | ||
15481 | /* Write instruction INSN to BUF, given that it has been relocated | |
15482 | by RELOC. */ | |
15483 | ||
15484 | static void | |
15485 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
15486 | unsigned long insn) | |
15487 | { | |
15488 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15489 | write_compressed_insn (buf, insn, 4); | |
15490 | else | |
15491 | write_insn (buf, insn); | |
15492 | } | |
15493 | ||
252b5132 RH |
15494 | /* Apply a fixup to the object file. */ |
15495 | ||
94f592af | 15496 | void |
55cf6793 | 15497 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15498 | { |
4d68580a | 15499 | char *buf; |
b886a2ab | 15500 | unsigned long insn; |
a7ebbfdf | 15501 | reloc_howto_type *howto; |
252b5132 | 15502 | |
a7ebbfdf TS |
15503 | /* We ignore generic BFD relocations we don't know about. */ |
15504 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15505 | if (! howto) | |
15506 | return; | |
65551fa4 | 15507 | |
df58fc94 RS |
15508 | gas_assert (fixP->fx_size == 2 |
15509 | || fixP->fx_size == 4 | |
90ecf173 MR |
15510 | || fixP->fx_r_type == BFD_RELOC_16 |
15511 | || fixP->fx_r_type == BFD_RELOC_64 | |
15512 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15513 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15514 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15515 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15516 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
15517 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 15518 | |
4d68580a | 15519 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15520 | |
df58fc94 RS |
15521 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15522 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15523 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15524 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
b1dca8ee RS |
15525 | |
15526 | /* Don't treat parts of a composite relocation as done. There are two | |
15527 | reasons for this: | |
15528 | ||
15529 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15530 | should nevertheless be emitted if the first part is. | |
15531 | ||
15532 | (2) In normal usage, composite relocations are never assembly-time | |
15533 | constants. The easiest way of dealing with the pathological | |
15534 | exceptions is to generate a relocation against STN_UNDEF and | |
15535 | leave everything up to the linker. */ | |
3994f87e | 15536 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15537 | fixP->fx_done = 1; |
15538 | ||
15539 | switch (fixP->fx_r_type) | |
15540 | { | |
3f98094e DJ |
15541 | case BFD_RELOC_MIPS_TLS_GD: |
15542 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15543 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15544 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15545 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15546 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15547 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15548 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15549 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15550 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15551 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15552 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15553 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15554 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15555 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15556 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15557 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15558 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15559 | case BFD_RELOC_MIPS16_TLS_GD: |
15560 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15561 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15562 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15563 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15564 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15565 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
b886a2ab RS |
15566 | if (!fixP->fx_addsy) |
15567 | { | |
15568 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15569 | _("TLS relocation against a constant")); | |
15570 | break; | |
15571 | } | |
3f98094e DJ |
15572 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
15573 | /* fall through */ | |
15574 | ||
252b5132 | 15575 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
15576 | case BFD_RELOC_MIPS_SHIFT5: |
15577 | case BFD_RELOC_MIPS_SHIFT6: | |
15578 | case BFD_RELOC_MIPS_GOT_DISP: | |
15579 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15580 | case BFD_RELOC_MIPS_GOT_OFST: | |
15581 | case BFD_RELOC_MIPS_SUB: | |
15582 | case BFD_RELOC_MIPS_INSERT_A: | |
15583 | case BFD_RELOC_MIPS_INSERT_B: | |
15584 | case BFD_RELOC_MIPS_DELETE: | |
15585 | case BFD_RELOC_MIPS_HIGHEST: | |
15586 | case BFD_RELOC_MIPS_HIGHER: | |
15587 | case BFD_RELOC_MIPS_SCN_DISP: | |
15588 | case BFD_RELOC_MIPS_REL16: | |
15589 | case BFD_RELOC_MIPS_RELGOT: | |
15590 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15591 | case BFD_RELOC_HI16: |
15592 | case BFD_RELOC_HI16_S: | |
b886a2ab | 15593 | case BFD_RELOC_LO16: |
cdf6fd85 | 15594 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15595 | case BFD_RELOC_MIPS_LITERAL: |
15596 | case BFD_RELOC_MIPS_CALL16: | |
15597 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15598 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15599 | case BFD_RELOC_MIPS_GOT_HI16: |
15600 | case BFD_RELOC_MIPS_GOT_LO16: | |
15601 | case BFD_RELOC_MIPS_CALL_HI16: | |
15602 | case BFD_RELOC_MIPS_CALL_LO16: | |
15603 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
15604 | case BFD_RELOC_MIPS16_GOT16: |
15605 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15606 | case BFD_RELOC_MIPS16_HI16: |
15607 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 15608 | case BFD_RELOC_MIPS16_LO16: |
252b5132 | 15609 | case BFD_RELOC_MIPS16_JMP: |
df58fc94 RS |
15610 | case BFD_RELOC_MICROMIPS_JMP: |
15611 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
15612 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15613 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15614 | case BFD_RELOC_MICROMIPS_SUB: | |
15615 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15616 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15617 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15618 | case BFD_RELOC_MICROMIPS_JALR: | |
15619 | case BFD_RELOC_MICROMIPS_HI16: | |
15620 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 15621 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
15622 | case BFD_RELOC_MICROMIPS_GPREL16: |
15623 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15624 | case BFD_RELOC_MICROMIPS_CALL16: | |
15625 | case BFD_RELOC_MICROMIPS_GOT16: | |
15626 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15627 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15628 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15629 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
b886a2ab RS |
15630 | if (fixP->fx_done) |
15631 | { | |
15632 | offsetT value; | |
15633 | ||
15634 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
15635 | { | |
15636 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
15637 | if (mips16_reloc_p (fixP->fx_r_type)) | |
15638 | insn |= mips16_immed_extend (value, 16); | |
15639 | else | |
15640 | insn |= (value & 0xffff); | |
15641 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
15642 | } | |
15643 | else | |
15644 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15645 | _("Unsupported constant in relocation")); | |
15646 | } | |
252b5132 RH |
15647 | break; |
15648 | ||
252b5132 RH |
15649 | case BFD_RELOC_64: |
15650 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15651 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15652 | if (fixP->fx_done) |
252b5132 RH |
15653 | { |
15654 | if (8 <= sizeof (valueT)) | |
4d68580a | 15655 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
15656 | else |
15657 | { | |
a7ebbfdf | 15658 | valueT hiv; |
252b5132 | 15659 | |
a7ebbfdf | 15660 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15661 | hiv = 0xffffffff; |
15662 | else | |
15663 | hiv = 0; | |
4d68580a RS |
15664 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
15665 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
15666 | } |
15667 | } | |
15668 | break; | |
15669 | ||
056350c6 | 15670 | case BFD_RELOC_RVA: |
252b5132 | 15671 | case BFD_RELOC_32: |
252b5132 RH |
15672 | case BFD_RELOC_16: |
15673 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
15674 | value now. This can happen if we have a .word which is not |
15675 | resolved when it appears but is later defined. */ | |
252b5132 | 15676 | if (fixP->fx_done) |
4d68580a | 15677 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
15678 | break; |
15679 | ||
252b5132 | 15680 | case BFD_RELOC_16_PCREL_S2: |
a7ebbfdf | 15681 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 15682 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 15683 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 15684 | |
54f4ddb3 TS |
15685 | /* We need to save the bits in the instruction since fixup_segment() |
15686 | might be deleting the relocation entry (i.e., a branch within | |
15687 | the current segment). */ | |
a7ebbfdf | 15688 | if (! fixP->fx_done) |
bb2d6cd7 | 15689 | break; |
252b5132 | 15690 | |
54f4ddb3 | 15691 | /* Update old instruction data. */ |
4d68580a | 15692 | insn = read_insn (buf); |
252b5132 | 15693 | |
a7ebbfdf TS |
15694 | if (*valP + 0x20000 <= 0x3ffff) |
15695 | { | |
15696 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 15697 | write_insn (buf, insn); |
a7ebbfdf TS |
15698 | } |
15699 | else if (mips_pic == NO_PIC | |
15700 | && fixP->fx_done | |
15701 | && fixP->fx_frag->fr_address >= text_section->vma | |
15702 | && (fixP->fx_frag->fr_address | |
587aac4e | 15703 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15704 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15705 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15706 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15707 | { |
15708 | /* The branch offset is too large. If this is an | |
15709 | unconditional branch, and we are not generating PIC code, | |
15710 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15711 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15712 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15713 | else |
a7ebbfdf TS |
15714 | insn = 0x08000000; /* j */ |
15715 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15716 | fixP->fx_done = 0; | |
15717 | fixP->fx_addsy = section_symbol (text_section); | |
15718 | *valP += md_pcrel_from (fixP); | |
4d68580a | 15719 | write_insn (buf, insn); |
a7ebbfdf TS |
15720 | } |
15721 | else | |
15722 | { | |
15723 | /* If we got here, we have branch-relaxation disabled, | |
15724 | and there's nothing we can do to fix this instruction | |
15725 | without turning it into a longer sequence. */ | |
15726 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15727 | _("Branch out of range")); | |
252b5132 | 15728 | } |
252b5132 RH |
15729 | break; |
15730 | ||
df58fc94 RS |
15731 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15732 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15733 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15734 | /* We adjust the offset back to even. */ | |
15735 | if ((*valP & 0x1) != 0) | |
15736 | --(*valP); | |
15737 | ||
15738 | if (! fixP->fx_done) | |
15739 | break; | |
15740 | ||
15741 | /* Should never visit here, because we keep the relocation. */ | |
15742 | abort (); | |
15743 | break; | |
15744 | ||
252b5132 RH |
15745 | case BFD_RELOC_VTABLE_INHERIT: |
15746 | fixP->fx_done = 0; | |
15747 | if (fixP->fx_addsy | |
15748 | && !S_IS_DEFINED (fixP->fx_addsy) | |
15749 | && !S_IS_WEAK (fixP->fx_addsy)) | |
15750 | S_SET_WEAK (fixP->fx_addsy); | |
15751 | break; | |
15752 | ||
15753 | case BFD_RELOC_VTABLE_ENTRY: | |
15754 | fixP->fx_done = 0; | |
15755 | break; | |
15756 | ||
15757 | default: | |
15758 | internalError (); | |
15759 | } | |
a7ebbfdf TS |
15760 | |
15761 | /* Remember value for tc_gen_reloc. */ | |
15762 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
15763 | } |
15764 | ||
252b5132 | 15765 | static symbolS * |
17a2f251 | 15766 | get_symbol (void) |
252b5132 RH |
15767 | { |
15768 | int c; | |
15769 | char *name; | |
15770 | symbolS *p; | |
15771 | ||
15772 | name = input_line_pointer; | |
15773 | c = get_symbol_end (); | |
15774 | p = (symbolS *) symbol_find_or_make (name); | |
15775 | *input_line_pointer = c; | |
15776 | return p; | |
15777 | } | |
15778 | ||
742a56fe RS |
15779 | /* Align the current frag to a given power of two. If a particular |
15780 | fill byte should be used, FILL points to an integer that contains | |
15781 | that byte, otherwise FILL is null. | |
15782 | ||
462427c4 RS |
15783 | This function used to have the comment: |
15784 | ||
15785 | The MIPS assembler also automatically adjusts any preceding label. | |
15786 | ||
15787 | The implementation therefore applied the adjustment to a maximum of | |
15788 | one label. However, other label adjustments are applied to batches | |
15789 | of labels, and adjusting just one caused problems when new labels | |
15790 | were added for the sake of debugging or unwind information. | |
15791 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
15792 | |
15793 | static void | |
462427c4 | 15794 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 15795 | { |
7d10b47d | 15796 | mips_emit_delays (); |
df58fc94 | 15797 | mips_record_compressed_mode (); |
742a56fe RS |
15798 | if (fill == NULL && subseg_text_p (now_seg)) |
15799 | frag_align_code (to, 0); | |
15800 | else | |
15801 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 15802 | record_alignment (now_seg, to); |
462427c4 | 15803 | mips_move_labels (labels, FALSE); |
252b5132 RH |
15804 | } |
15805 | ||
15806 | /* Align to a given power of two. .align 0 turns off the automatic | |
15807 | alignment used by the data creating pseudo-ops. */ | |
15808 | ||
15809 | static void | |
17a2f251 | 15810 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 15811 | { |
742a56fe | 15812 | int temp, fill_value, *fill_ptr; |
49954fb4 | 15813 | long max_alignment = 28; |
252b5132 | 15814 | |
54f4ddb3 | 15815 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 15816 | to the aligned address. |
54f4ddb3 | 15817 | o It's not documented but auto alignment is reinstated by |
252b5132 | 15818 | a .align pseudo instruction. |
54f4ddb3 | 15819 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 15820 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 15821 | We don't. */ |
252b5132 RH |
15822 | |
15823 | temp = get_absolute_expression (); | |
15824 | if (temp > max_alignment) | |
15825 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
15826 | else if (temp < 0) | |
15827 | { | |
15828 | as_warn (_("Alignment negative: 0 assumed.")); | |
15829 | temp = 0; | |
15830 | } | |
15831 | if (*input_line_pointer == ',') | |
15832 | { | |
f9419b05 | 15833 | ++input_line_pointer; |
742a56fe RS |
15834 | fill_value = get_absolute_expression (); |
15835 | fill_ptr = &fill_value; | |
252b5132 RH |
15836 | } |
15837 | else | |
742a56fe | 15838 | fill_ptr = 0; |
252b5132 RH |
15839 | if (temp) |
15840 | { | |
a8dbcb85 TS |
15841 | segment_info_type *si = seg_info (now_seg); |
15842 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 15843 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 15844 | auto_align = 1; |
462427c4 | 15845 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
15846 | } |
15847 | else | |
15848 | { | |
15849 | auto_align = 0; | |
15850 | } | |
15851 | ||
15852 | demand_empty_rest_of_line (); | |
15853 | } | |
15854 | ||
252b5132 | 15855 | static void |
17a2f251 | 15856 | s_change_sec (int sec) |
252b5132 RH |
15857 | { |
15858 | segT seg; | |
15859 | ||
252b5132 RH |
15860 | #ifdef OBJ_ELF |
15861 | /* The ELF backend needs to know that we are changing sections, so | |
15862 | that .previous works correctly. We could do something like check | |
b6ff326e | 15863 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
15864 | as it would not be appropriate to use it in the section changing |
15865 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
15866 | This should be cleaner, somehow. */ | |
f43abd2b TS |
15867 | if (IS_ELF) |
15868 | obj_elf_section_change_hook (); | |
252b5132 RH |
15869 | #endif |
15870 | ||
7d10b47d | 15871 | mips_emit_delays (); |
6a32d874 | 15872 | |
252b5132 RH |
15873 | switch (sec) |
15874 | { | |
15875 | case 't': | |
15876 | s_text (0); | |
15877 | break; | |
15878 | case 'd': | |
15879 | s_data (0); | |
15880 | break; | |
15881 | case 'b': | |
15882 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
15883 | demand_empty_rest_of_line (); | |
15884 | break; | |
15885 | ||
15886 | case 'r': | |
4d0d148d TS |
15887 | seg = subseg_new (RDATA_SECTION_NAME, |
15888 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 15889 | if (IS_ELF) |
252b5132 | 15890 | { |
4d0d148d TS |
15891 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
15892 | | SEC_READONLY | SEC_RELOC | |
15893 | | SEC_DATA)); | |
c41e87e3 | 15894 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 15895 | record_alignment (seg, 4); |
252b5132 | 15896 | } |
4d0d148d | 15897 | demand_empty_rest_of_line (); |
252b5132 RH |
15898 | break; |
15899 | ||
15900 | case 's': | |
4d0d148d | 15901 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 15902 | if (IS_ELF) |
252b5132 | 15903 | { |
4d0d148d TS |
15904 | bfd_set_section_flags (stdoutput, seg, |
15905 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 15906 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 15907 | record_alignment (seg, 4); |
252b5132 | 15908 | } |
4d0d148d TS |
15909 | demand_empty_rest_of_line (); |
15910 | break; | |
998b3c36 MR |
15911 | |
15912 | case 'B': | |
15913 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
15914 | if (IS_ELF) | |
15915 | { | |
15916 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); | |
15917 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
15918 | record_alignment (seg, 4); | |
15919 | } | |
15920 | demand_empty_rest_of_line (); | |
15921 | break; | |
252b5132 RH |
15922 | } |
15923 | ||
15924 | auto_align = 1; | |
15925 | } | |
b34976b6 | 15926 | |
cca86cc8 | 15927 | void |
17a2f251 | 15928 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 15929 | { |
7ed4a06a | 15930 | #ifdef OBJ_ELF |
cca86cc8 SC |
15931 | char *section_name; |
15932 | char c; | |
684022ea | 15933 | char next_c = 0; |
cca86cc8 SC |
15934 | int section_type; |
15935 | int section_flag; | |
15936 | int section_entry_size; | |
15937 | int section_alignment; | |
b34976b6 | 15938 | |
f43abd2b | 15939 | if (!IS_ELF) |
7ed4a06a TS |
15940 | return; |
15941 | ||
cca86cc8 SC |
15942 | section_name = input_line_pointer; |
15943 | c = get_symbol_end (); | |
a816d1ed AO |
15944 | if (c) |
15945 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 15946 | |
4cf0dd0d TS |
15947 | /* Do we have .section Name<,"flags">? */ |
15948 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 15949 | { |
4cf0dd0d TS |
15950 | /* just after name is now '\0'. */ |
15951 | *input_line_pointer = c; | |
cca86cc8 SC |
15952 | input_line_pointer = section_name; |
15953 | obj_elf_section (ignore); | |
15954 | return; | |
15955 | } | |
15956 | input_line_pointer++; | |
15957 | ||
15958 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
15959 | if (c == ',') | |
15960 | section_type = get_absolute_expression (); | |
15961 | else | |
15962 | section_type = 0; | |
15963 | if (*input_line_pointer++ == ',') | |
15964 | section_flag = get_absolute_expression (); | |
15965 | else | |
15966 | section_flag = 0; | |
15967 | if (*input_line_pointer++ == ',') | |
15968 | section_entry_size = get_absolute_expression (); | |
15969 | else | |
15970 | section_entry_size = 0; | |
15971 | if (*input_line_pointer++ == ',') | |
15972 | section_alignment = get_absolute_expression (); | |
15973 | else | |
15974 | section_alignment = 0; | |
87975d2a AM |
15975 | /* FIXME: really ignore? */ |
15976 | (void) section_alignment; | |
cca86cc8 | 15977 | |
a816d1ed AO |
15978 | section_name = xstrdup (section_name); |
15979 | ||
8ab8a5c8 RS |
15980 | /* When using the generic form of .section (as implemented by obj-elf.c), |
15981 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
15982 | traditionally had to fall back on the more common @progbits instead. | |
15983 | ||
15984 | There's nothing really harmful in this, since bfd will correct | |
15985 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 15986 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
15987 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
15988 | ||
15989 | Even so, we shouldn't force users of the MIPS .section syntax to | |
15990 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
15991 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
15992 | generic type-checking code. */ | |
15993 | if (section_type == SHT_MIPS_DWARF) | |
15994 | section_type = SHT_PROGBITS; | |
15995 | ||
cca86cc8 SC |
15996 | obj_elf_change_section (section_name, section_type, section_flag, |
15997 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
15998 | |
15999 | if (now_seg->name != section_name) | |
16000 | free (section_name); | |
7ed4a06a | 16001 | #endif /* OBJ_ELF */ |
cca86cc8 | 16002 | } |
252b5132 RH |
16003 | |
16004 | void | |
17a2f251 | 16005 | mips_enable_auto_align (void) |
252b5132 RH |
16006 | { |
16007 | auto_align = 1; | |
16008 | } | |
16009 | ||
16010 | static void | |
17a2f251 | 16011 | s_cons (int log_size) |
252b5132 | 16012 | { |
a8dbcb85 TS |
16013 | segment_info_type *si = seg_info (now_seg); |
16014 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16015 | |
7d10b47d | 16016 | mips_emit_delays (); |
252b5132 | 16017 | if (log_size > 0 && auto_align) |
462427c4 | 16018 | mips_align (log_size, 0, l); |
252b5132 | 16019 | cons (1 << log_size); |
a1facbec | 16020 | mips_clear_insn_labels (); |
252b5132 RH |
16021 | } |
16022 | ||
16023 | static void | |
17a2f251 | 16024 | s_float_cons (int type) |
252b5132 | 16025 | { |
a8dbcb85 TS |
16026 | segment_info_type *si = seg_info (now_seg); |
16027 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16028 | |
7d10b47d | 16029 | mips_emit_delays (); |
252b5132 RH |
16030 | |
16031 | if (auto_align) | |
49309057 ILT |
16032 | { |
16033 | if (type == 'd') | |
462427c4 | 16034 | mips_align (3, 0, l); |
49309057 | 16035 | else |
462427c4 | 16036 | mips_align (2, 0, l); |
49309057 | 16037 | } |
252b5132 | 16038 | |
252b5132 | 16039 | float_cons (type); |
a1facbec | 16040 | mips_clear_insn_labels (); |
252b5132 RH |
16041 | } |
16042 | ||
16043 | /* Handle .globl. We need to override it because on Irix 5 you are | |
16044 | permitted to say | |
16045 | .globl foo .text | |
16046 | where foo is an undefined symbol, to mean that foo should be | |
16047 | considered to be the address of a function. */ | |
16048 | ||
16049 | static void | |
17a2f251 | 16050 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16051 | { |
16052 | char *name; | |
16053 | int c; | |
16054 | symbolS *symbolP; | |
16055 | flagword flag; | |
16056 | ||
8a06b769 | 16057 | do |
252b5132 | 16058 | { |
8a06b769 | 16059 | name = input_line_pointer; |
252b5132 | 16060 | c = get_symbol_end (); |
8a06b769 TS |
16061 | symbolP = symbol_find_or_make (name); |
16062 | S_SET_EXTERNAL (symbolP); | |
16063 | ||
252b5132 | 16064 | *input_line_pointer = c; |
8a06b769 | 16065 | SKIP_WHITESPACE (); |
252b5132 | 16066 | |
8a06b769 TS |
16067 | /* On Irix 5, every global symbol that is not explicitly labelled as |
16068 | being a function is apparently labelled as being an object. */ | |
16069 | flag = BSF_OBJECT; | |
252b5132 | 16070 | |
8a06b769 TS |
16071 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
16072 | && (*input_line_pointer != ',')) | |
16073 | { | |
16074 | char *secname; | |
16075 | asection *sec; | |
16076 | ||
16077 | secname = input_line_pointer; | |
16078 | c = get_symbol_end (); | |
16079 | sec = bfd_get_section_by_name (stdoutput, secname); | |
16080 | if (sec == NULL) | |
16081 | as_bad (_("%s: no such section"), secname); | |
16082 | *input_line_pointer = c; | |
16083 | ||
16084 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
16085 | flag = BSF_FUNCTION; | |
16086 | } | |
16087 | ||
16088 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
16089 | ||
16090 | c = *input_line_pointer; | |
16091 | if (c == ',') | |
16092 | { | |
16093 | input_line_pointer++; | |
16094 | SKIP_WHITESPACE (); | |
16095 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16096 | c = '\n'; | |
16097 | } | |
16098 | } | |
16099 | while (c == ','); | |
252b5132 | 16100 | |
252b5132 RH |
16101 | demand_empty_rest_of_line (); |
16102 | } | |
16103 | ||
16104 | static void | |
17a2f251 | 16105 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16106 | { |
16107 | char *opt; | |
16108 | char c; | |
16109 | ||
16110 | opt = input_line_pointer; | |
16111 | c = get_symbol_end (); | |
16112 | ||
16113 | if (*opt == 'O') | |
16114 | { | |
16115 | /* FIXME: What does this mean? */ | |
16116 | } | |
16117 | else if (strncmp (opt, "pic", 3) == 0) | |
16118 | { | |
16119 | int i; | |
16120 | ||
16121 | i = atoi (opt + 3); | |
16122 | if (i == 0) | |
16123 | mips_pic = NO_PIC; | |
16124 | else if (i == 2) | |
143d77c5 | 16125 | { |
8b828383 | 16126 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16127 | mips_abicalls = TRUE; |
16128 | } | |
252b5132 RH |
16129 | else |
16130 | as_bad (_(".option pic%d not supported"), i); | |
16131 | ||
4d0d148d | 16132 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16133 | { |
16134 | if (g_switch_seen && g_switch_value != 0) | |
16135 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16136 | g_switch_value = 0; | |
16137 | bfd_set_gp_size (stdoutput, 0); | |
16138 | } | |
16139 | } | |
16140 | else | |
16141 | as_warn (_("Unrecognized option \"%s\""), opt); | |
16142 | ||
16143 | *input_line_pointer = c; | |
16144 | demand_empty_rest_of_line (); | |
16145 | } | |
16146 | ||
16147 | /* This structure is used to hold a stack of .set values. */ | |
16148 | ||
e972090a NC |
16149 | struct mips_option_stack |
16150 | { | |
252b5132 RH |
16151 | struct mips_option_stack *next; |
16152 | struct mips_set_options options; | |
16153 | }; | |
16154 | ||
16155 | static struct mips_option_stack *mips_opts_stack; | |
16156 | ||
16157 | /* Handle the .set pseudo-op. */ | |
16158 | ||
16159 | static void | |
17a2f251 | 16160 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16161 | { |
16162 | char *name = input_line_pointer, ch; | |
16163 | ||
16164 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 16165 | ++input_line_pointer; |
252b5132 RH |
16166 | ch = *input_line_pointer; |
16167 | *input_line_pointer = '\0'; | |
16168 | ||
16169 | if (strcmp (name, "reorder") == 0) | |
16170 | { | |
7d10b47d RS |
16171 | if (mips_opts.noreorder) |
16172 | end_noreorder (); | |
252b5132 RH |
16173 | } |
16174 | else if (strcmp (name, "noreorder") == 0) | |
16175 | { | |
7d10b47d RS |
16176 | if (!mips_opts.noreorder) |
16177 | start_noreorder (); | |
252b5132 | 16178 | } |
741fe287 MR |
16179 | else if (strncmp (name, "at=", 3) == 0) |
16180 | { | |
16181 | char *s = name + 3; | |
16182 | ||
16183 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
16184 | as_bad (_("Unrecognized register name `%s'"), s); | |
16185 | } | |
252b5132 RH |
16186 | else if (strcmp (name, "at") == 0) |
16187 | { | |
741fe287 | 16188 | mips_opts.at = ATREG; |
252b5132 RH |
16189 | } |
16190 | else if (strcmp (name, "noat") == 0) | |
16191 | { | |
741fe287 | 16192 | mips_opts.at = ZERO; |
252b5132 RH |
16193 | } |
16194 | else if (strcmp (name, "macro") == 0) | |
16195 | { | |
16196 | mips_opts.warn_about_macros = 0; | |
16197 | } | |
16198 | else if (strcmp (name, "nomacro") == 0) | |
16199 | { | |
16200 | if (mips_opts.noreorder == 0) | |
16201 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16202 | mips_opts.warn_about_macros = 1; | |
16203 | } | |
16204 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
16205 | { | |
16206 | mips_opts.nomove = 0; | |
16207 | } | |
16208 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
16209 | { | |
16210 | mips_opts.nomove = 1; | |
16211 | } | |
16212 | else if (strcmp (name, "bopt") == 0) | |
16213 | { | |
16214 | mips_opts.nobopt = 0; | |
16215 | } | |
16216 | else if (strcmp (name, "nobopt") == 0) | |
16217 | { | |
16218 | mips_opts.nobopt = 1; | |
16219 | } | |
ad3fea08 TS |
16220 | else if (strcmp (name, "gp=default") == 0) |
16221 | mips_opts.gp32 = file_mips_gp32; | |
16222 | else if (strcmp (name, "gp=32") == 0) | |
16223 | mips_opts.gp32 = 1; | |
16224 | else if (strcmp (name, "gp=64") == 0) | |
16225 | { | |
16226 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 16227 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
16228 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16229 | mips_opts.gp32 = 0; | |
16230 | } | |
16231 | else if (strcmp (name, "fp=default") == 0) | |
16232 | mips_opts.fp32 = file_mips_fp32; | |
16233 | else if (strcmp (name, "fp=32") == 0) | |
16234 | mips_opts.fp32 = 1; | |
16235 | else if (strcmp (name, "fp=64") == 0) | |
16236 | { | |
16237 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 16238 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
16239 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16240 | mips_opts.fp32 = 0; | |
16241 | } | |
037b32b9 AN |
16242 | else if (strcmp (name, "softfloat") == 0) |
16243 | mips_opts.soft_float = 1; | |
16244 | else if (strcmp (name, "hardfloat") == 0) | |
16245 | mips_opts.soft_float = 0; | |
16246 | else if (strcmp (name, "singlefloat") == 0) | |
16247 | mips_opts.single_float = 1; | |
16248 | else if (strcmp (name, "doublefloat") == 0) | |
16249 | mips_opts.single_float = 0; | |
252b5132 RH |
16250 | else if (strcmp (name, "mips16") == 0 |
16251 | || strcmp (name, "MIPS-16") == 0) | |
df58fc94 RS |
16252 | { |
16253 | if (mips_opts.micromips == 1) | |
16254 | as_fatal (_("`mips16' cannot be used with `micromips'")); | |
16255 | mips_opts.mips16 = 1; | |
16256 | } | |
252b5132 RH |
16257 | else if (strcmp (name, "nomips16") == 0 |
16258 | || strcmp (name, "noMIPS-16") == 0) | |
16259 | mips_opts.mips16 = 0; | |
df58fc94 RS |
16260 | else if (strcmp (name, "micromips") == 0) |
16261 | { | |
16262 | if (mips_opts.mips16 == 1) | |
16263 | as_fatal (_("`micromips' cannot be used with `mips16'")); | |
16264 | mips_opts.micromips = 1; | |
16265 | } | |
16266 | else if (strcmp (name, "nomicromips") == 0) | |
16267 | mips_opts.micromips = 0; | |
e16bfa71 TS |
16268 | else if (strcmp (name, "smartmips") == 0) |
16269 | { | |
ad3fea08 | 16270 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 16271 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 TS |
16272 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16273 | mips_opts.ase_smartmips = 1; | |
16274 | } | |
16275 | else if (strcmp (name, "nosmartmips") == 0) | |
16276 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
16277 | else if (strcmp (name, "mips3d") == 0) |
16278 | mips_opts.ase_mips3d = 1; | |
16279 | else if (strcmp (name, "nomips3d") == 0) | |
16280 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
16281 | else if (strcmp (name, "mdmx") == 0) |
16282 | mips_opts.ase_mdmx = 1; | |
16283 | else if (strcmp (name, "nomdmx") == 0) | |
16284 | mips_opts.ase_mdmx = 0; | |
74cd071d | 16285 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
16286 | { |
16287 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 16288 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 TS |
16289 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16290 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 16291 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 16292 | } |
74cd071d | 16293 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
16294 | { |
16295 | mips_opts.ase_dsp = 0; | |
16296 | mips_opts.ase_dspr2 = 0; | |
16297 | } | |
16298 | else if (strcmp (name, "dspr2") == 0) | |
16299 | { | |
16300 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 16301 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 TS |
16302 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16303 | mips_opts.ase_dspr2 = 1; | |
16304 | mips_opts.ase_dsp = 1; | |
16305 | } | |
16306 | else if (strcmp (name, "nodspr2") == 0) | |
16307 | { | |
16308 | mips_opts.ase_dspr2 = 0; | |
16309 | mips_opts.ase_dsp = 0; | |
16310 | } | |
ef2e4d86 | 16311 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
16312 | { |
16313 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 16314 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 TS |
16315 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16316 | mips_opts.ase_mt = 1; | |
16317 | } | |
ef2e4d86 CF |
16318 | else if (strcmp (name, "nomt") == 0) |
16319 | mips_opts.ase_mt = 0; | |
dec0624d MR |
16320 | else if (strcmp (name, "mcu") == 0) |
16321 | mips_opts.ase_mcu = 1; | |
16322 | else if (strcmp (name, "nomcu") == 0) | |
16323 | mips_opts.ase_mcu = 0; | |
1a2c1fad | 16324 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16325 | { |
af7ee8bf | 16326 | int reset = 0; |
252b5132 | 16327 | |
1a2c1fad CD |
16328 | /* Permit the user to change the ISA and architecture on the fly. |
16329 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 16330 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
16331 | { |
16332 | reset = 1; | |
16333 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 16334 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
16335 | } |
16336 | else if (strncmp (name, "arch=", 5) == 0) | |
16337 | { | |
16338 | const struct mips_cpu_info *p; | |
16339 | ||
16340 | p = mips_parse_cpu("internal use", name + 5); | |
16341 | if (!p) | |
16342 | as_bad (_("unknown architecture %s"), name + 5); | |
16343 | else | |
16344 | { | |
16345 | mips_opts.arch = p->cpu; | |
16346 | mips_opts.isa = p->isa; | |
16347 | } | |
16348 | } | |
81a21e38 TS |
16349 | else if (strncmp (name, "mips", 4) == 0) |
16350 | { | |
16351 | const struct mips_cpu_info *p; | |
16352 | ||
16353 | p = mips_parse_cpu("internal use", name); | |
16354 | if (!p) | |
16355 | as_bad (_("unknown ISA level %s"), name + 4); | |
16356 | else | |
16357 | { | |
16358 | mips_opts.arch = p->cpu; | |
16359 | mips_opts.isa = p->isa; | |
16360 | } | |
16361 | } | |
af7ee8bf | 16362 | else |
81a21e38 | 16363 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
16364 | |
16365 | switch (mips_opts.isa) | |
98d3f06f KH |
16366 | { |
16367 | case 0: | |
98d3f06f | 16368 | break; |
af7ee8bf CD |
16369 | case ISA_MIPS1: |
16370 | case ISA_MIPS2: | |
16371 | case ISA_MIPS32: | |
16372 | case ISA_MIPS32R2: | |
98d3f06f KH |
16373 | mips_opts.gp32 = 1; |
16374 | mips_opts.fp32 = 1; | |
16375 | break; | |
af7ee8bf CD |
16376 | case ISA_MIPS3: |
16377 | case ISA_MIPS4: | |
16378 | case ISA_MIPS5: | |
16379 | case ISA_MIPS64: | |
5f74bc13 | 16380 | case ISA_MIPS64R2: |
98d3f06f KH |
16381 | mips_opts.gp32 = 0; |
16382 | mips_opts.fp32 = 0; | |
16383 | break; | |
16384 | default: | |
16385 | as_bad (_("unknown ISA level %s"), name + 4); | |
16386 | break; | |
16387 | } | |
af7ee8bf | 16388 | if (reset) |
98d3f06f | 16389 | { |
af7ee8bf CD |
16390 | mips_opts.gp32 = file_mips_gp32; |
16391 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 16392 | } |
252b5132 RH |
16393 | } |
16394 | else if (strcmp (name, "autoextend") == 0) | |
16395 | mips_opts.noautoextend = 0; | |
16396 | else if (strcmp (name, "noautoextend") == 0) | |
16397 | mips_opts.noautoextend = 1; | |
16398 | else if (strcmp (name, "push") == 0) | |
16399 | { | |
16400 | struct mips_option_stack *s; | |
16401 | ||
16402 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
16403 | s->next = mips_opts_stack; | |
16404 | s->options = mips_opts; | |
16405 | mips_opts_stack = s; | |
16406 | } | |
16407 | else if (strcmp (name, "pop") == 0) | |
16408 | { | |
16409 | struct mips_option_stack *s; | |
16410 | ||
16411 | s = mips_opts_stack; | |
16412 | if (s == NULL) | |
16413 | as_bad (_(".set pop with no .set push")); | |
16414 | else | |
16415 | { | |
16416 | /* If we're changing the reorder mode we need to handle | |
16417 | delay slots correctly. */ | |
16418 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16419 | start_noreorder (); |
252b5132 | 16420 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16421 | end_noreorder (); |
252b5132 RH |
16422 | |
16423 | mips_opts = s->options; | |
16424 | mips_opts_stack = s->next; | |
16425 | free (s); | |
16426 | } | |
16427 | } | |
aed1a261 RS |
16428 | else if (strcmp (name, "sym32") == 0) |
16429 | mips_opts.sym32 = TRUE; | |
16430 | else if (strcmp (name, "nosym32") == 0) | |
16431 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
16432 | else if (strchr (name, ',')) |
16433 | { | |
16434 | /* Generic ".set" directive; use the generic handler. */ | |
16435 | *input_line_pointer = ch; | |
16436 | input_line_pointer = name; | |
16437 | s_set (0); | |
16438 | return; | |
16439 | } | |
252b5132 RH |
16440 | else |
16441 | { | |
16442 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
16443 | } | |
16444 | *input_line_pointer = ch; | |
16445 | demand_empty_rest_of_line (); | |
16446 | } | |
16447 | ||
16448 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16449 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16450 | ||
16451 | static void | |
17a2f251 | 16452 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16453 | { |
16454 | mips_pic = SVR4_PIC; | |
143d77c5 | 16455 | mips_abicalls = TRUE; |
4d0d148d TS |
16456 | |
16457 | if (g_switch_seen && g_switch_value != 0) | |
16458 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16459 | g_switch_value = 0; | |
16460 | ||
252b5132 RH |
16461 | bfd_set_gp_size (stdoutput, 0); |
16462 | demand_empty_rest_of_line (); | |
16463 | } | |
16464 | ||
16465 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16466 | PIC code. It sets the $gp register for the function based on the | |
16467 | function address, which is in the register named in the argument. | |
16468 | This uses a relocation against _gp_disp, which is handled specially | |
16469 | by the linker. The result is: | |
16470 | lui $gp,%hi(_gp_disp) | |
16471 | addiu $gp,$gp,%lo(_gp_disp) | |
16472 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16473 | The .cpload argument is normally $25 == $t9. |
16474 | ||
16475 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16476 | lui $gp,%hi(__gnu_local_gp) |
16477 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16478 | and the argument is ignored. This saves an instruction, but the |
16479 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16480 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16481 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16482 | |
16483 | static void | |
17a2f251 | 16484 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16485 | { |
16486 | expressionS ex; | |
aa6975fb ILT |
16487 | int reg; |
16488 | int in_shared; | |
252b5132 | 16489 | |
6478892d TS |
16490 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16491 | .cpload is ignored. */ | |
16492 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16493 | { |
16494 | s_ignore (0); | |
16495 | return; | |
16496 | } | |
16497 | ||
a276b80c MR |
16498 | if (mips_opts.mips16) |
16499 | { | |
16500 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16501 | ignore_rest_of_line (); | |
16502 | return; | |
16503 | } | |
16504 | ||
d3ecfc59 | 16505 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16506 | if (mips_opts.noreorder == 0) |
16507 | as_warn (_(".cpload not in noreorder section")); | |
16508 | ||
aa6975fb ILT |
16509 | reg = tc_get_register (0); |
16510 | ||
16511 | /* If we need to produce a 64-bit address, we are better off using | |
16512 | the default instruction sequence. */ | |
aed1a261 | 16513 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16514 | |
252b5132 | 16515 | ex.X_op = O_symbol; |
bbe506e8 TS |
16516 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16517 | "__gnu_local_gp"); | |
252b5132 RH |
16518 | ex.X_op_symbol = NULL; |
16519 | ex.X_add_number = 0; | |
16520 | ||
16521 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16522 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16523 | |
584892a6 | 16524 | macro_start (); |
67c0d1eb RS |
16525 | macro_build_lui (&ex, mips_gp_register); |
16526 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16527 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16528 | if (in_shared) |
16529 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16530 | mips_gp_register, reg); | |
584892a6 | 16531 | macro_end (); |
252b5132 RH |
16532 | |
16533 | demand_empty_rest_of_line (); | |
16534 | } | |
16535 | ||
6478892d TS |
16536 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16537 | .cpsetup $reg1, offset|$reg2, label | |
16538 | ||
16539 | If offset is given, this results in: | |
16540 | sd $gp, offset($sp) | |
956cd1d6 | 16541 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16542 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16543 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16544 | |
16545 | If $reg2 is given, this results in: | |
16546 | daddu $reg2, $gp, $0 | |
956cd1d6 | 16547 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16548 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16549 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16550 | $reg1 is normally $25 == $t9. |
16551 | ||
16552 | The -mno-shared option replaces the last three instructions with | |
16553 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16554 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16555 | |
6478892d | 16556 | static void |
17a2f251 | 16557 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16558 | { |
16559 | expressionS ex_off; | |
16560 | expressionS ex_sym; | |
16561 | int reg1; | |
6478892d | 16562 | |
8586fc66 | 16563 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16564 | We also need NewABI support. */ |
16565 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16566 | { | |
16567 | s_ignore (0); | |
16568 | return; | |
16569 | } | |
16570 | ||
a276b80c MR |
16571 | if (mips_opts.mips16) |
16572 | { | |
16573 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
16574 | ignore_rest_of_line (); | |
16575 | return; | |
16576 | } | |
16577 | ||
6478892d TS |
16578 | reg1 = tc_get_register (0); |
16579 | SKIP_WHITESPACE (); | |
16580 | if (*input_line_pointer != ',') | |
16581 | { | |
16582 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16583 | return; | |
16584 | } | |
16585 | else | |
80245285 | 16586 | ++input_line_pointer; |
6478892d TS |
16587 | SKIP_WHITESPACE (); |
16588 | if (*input_line_pointer == '$') | |
80245285 TS |
16589 | { |
16590 | mips_cpreturn_register = tc_get_register (0); | |
16591 | mips_cpreturn_offset = -1; | |
16592 | } | |
6478892d | 16593 | else |
80245285 TS |
16594 | { |
16595 | mips_cpreturn_offset = get_absolute_expression (); | |
16596 | mips_cpreturn_register = -1; | |
16597 | } | |
6478892d TS |
16598 | SKIP_WHITESPACE (); |
16599 | if (*input_line_pointer != ',') | |
16600 | { | |
16601 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16602 | return; | |
16603 | } | |
16604 | else | |
f9419b05 | 16605 | ++input_line_pointer; |
6478892d | 16606 | SKIP_WHITESPACE (); |
f21f8242 | 16607 | expression (&ex_sym); |
6478892d | 16608 | |
584892a6 | 16609 | macro_start (); |
6478892d TS |
16610 | if (mips_cpreturn_register == -1) |
16611 | { | |
16612 | ex_off.X_op = O_constant; | |
16613 | ex_off.X_add_symbol = NULL; | |
16614 | ex_off.X_op_symbol = NULL; | |
16615 | ex_off.X_add_number = mips_cpreturn_offset; | |
16616 | ||
67c0d1eb | 16617 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16618 | BFD_RELOC_LO16, SP); |
6478892d TS |
16619 | } |
16620 | else | |
67c0d1eb | 16621 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 16622 | mips_gp_register, 0); |
6478892d | 16623 | |
aed1a261 | 16624 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16625 | { |
df58fc94 | 16626 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16627 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16628 | BFD_RELOC_HI16_S); | |
16629 | ||
16630 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16631 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16632 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16633 | ||
16634 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16635 | mips_gp_register, reg1); | |
16636 | } | |
16637 | else | |
16638 | { | |
16639 | expressionS ex; | |
16640 | ||
16641 | ex.X_op = O_symbol; | |
4184909a | 16642 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16643 | ex.X_op_symbol = NULL; |
16644 | ex.X_add_number = 0; | |
6e1304d8 | 16645 | |
aa6975fb ILT |
16646 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16647 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16648 | ||
16649 | macro_build_lui (&ex, mips_gp_register); | |
16650 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16651 | mips_gp_register, BFD_RELOC_LO16); | |
16652 | } | |
f21f8242 | 16653 | |
584892a6 | 16654 | macro_end (); |
6478892d TS |
16655 | |
16656 | demand_empty_rest_of_line (); | |
16657 | } | |
16658 | ||
16659 | static void | |
17a2f251 | 16660 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16661 | { |
16662 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 16663 | .cplocal is ignored. */ |
6478892d TS |
16664 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16665 | { | |
16666 | s_ignore (0); | |
16667 | return; | |
16668 | } | |
16669 | ||
a276b80c MR |
16670 | if (mips_opts.mips16) |
16671 | { | |
16672 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
16673 | ignore_rest_of_line (); | |
16674 | return; | |
16675 | } | |
16676 | ||
6478892d | 16677 | mips_gp_register = tc_get_register (0); |
85b51719 | 16678 | demand_empty_rest_of_line (); |
6478892d TS |
16679 | } |
16680 | ||
252b5132 RH |
16681 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16682 | offset from $sp. The offset is remembered, and after making a PIC | |
16683 | call $gp is restored from that location. */ | |
16684 | ||
16685 | static void | |
17a2f251 | 16686 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16687 | { |
16688 | expressionS ex; | |
252b5132 | 16689 | |
6478892d | 16690 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16691 | .cprestore is ignored. */ |
6478892d | 16692 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16693 | { |
16694 | s_ignore (0); | |
16695 | return; | |
16696 | } | |
16697 | ||
a276b80c MR |
16698 | if (mips_opts.mips16) |
16699 | { | |
16700 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
16701 | ignore_rest_of_line (); | |
16702 | return; | |
16703 | } | |
16704 | ||
252b5132 | 16705 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 16706 | mips_cprestore_valid = 1; |
252b5132 RH |
16707 | |
16708 | ex.X_op = O_constant; | |
16709 | ex.X_add_symbol = NULL; | |
16710 | ex.X_op_symbol = NULL; | |
16711 | ex.X_add_number = mips_cprestore_offset; | |
16712 | ||
584892a6 | 16713 | macro_start (); |
67c0d1eb RS |
16714 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16715 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16716 | macro_end (); |
252b5132 RH |
16717 | |
16718 | demand_empty_rest_of_line (); | |
16719 | } | |
16720 | ||
6478892d | 16721 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16722 | was given in the preceding .cpsetup, it results in: |
6478892d | 16723 | ld $gp, offset($sp) |
76b3015f | 16724 | |
6478892d | 16725 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
16726 | daddu $gp, $reg2, $0 */ |
16727 | ||
6478892d | 16728 | static void |
17a2f251 | 16729 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16730 | { |
16731 | expressionS ex; | |
6478892d TS |
16732 | |
16733 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
16734 | We also need NewABI support. */ | |
16735 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16736 | { | |
16737 | s_ignore (0); | |
16738 | return; | |
16739 | } | |
16740 | ||
a276b80c MR |
16741 | if (mips_opts.mips16) |
16742 | { | |
16743 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
16744 | ignore_rest_of_line (); | |
16745 | return; | |
16746 | } | |
16747 | ||
584892a6 | 16748 | macro_start (); |
6478892d TS |
16749 | if (mips_cpreturn_register == -1) |
16750 | { | |
16751 | ex.X_op = O_constant; | |
16752 | ex.X_add_symbol = NULL; | |
16753 | ex.X_op_symbol = NULL; | |
16754 | ex.X_add_number = mips_cpreturn_offset; | |
16755 | ||
67c0d1eb | 16756 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16757 | } |
16758 | else | |
67c0d1eb | 16759 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 16760 | mips_cpreturn_register, 0); |
584892a6 | 16761 | macro_end (); |
6478892d TS |
16762 | |
16763 | demand_empty_rest_of_line (); | |
16764 | } | |
16765 | ||
d0f13682 CLT |
16766 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
16767 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
16768 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
16769 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
16770 | |
16771 | static void | |
d0f13682 CLT |
16772 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
16773 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
16774 | { |
16775 | expressionS ex; | |
16776 | char *p; | |
16777 | ||
16778 | expression (&ex); | |
16779 | ||
16780 | if (ex.X_op != O_symbol) | |
16781 | { | |
d0f13682 | 16782 | as_bad (_("Unsupported use of %s"), dirstr); |
741d6ea8 JM |
16783 | ignore_rest_of_line (); |
16784 | } | |
16785 | ||
16786 | p = frag_more (bytes); | |
16787 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 16788 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 16789 | demand_empty_rest_of_line (); |
de64cffd | 16790 | mips_clear_insn_labels (); |
741d6ea8 JM |
16791 | } |
16792 | ||
16793 | /* Handle .dtprelword. */ | |
16794 | ||
16795 | static void | |
16796 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
16797 | { | |
d0f13682 | 16798 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
16799 | } |
16800 | ||
16801 | /* Handle .dtpreldword. */ | |
16802 | ||
16803 | static void | |
16804 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
16805 | { | |
d0f13682 CLT |
16806 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
16807 | } | |
16808 | ||
16809 | /* Handle .tprelword. */ | |
16810 | ||
16811 | static void | |
16812 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
16813 | { | |
16814 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
16815 | } | |
16816 | ||
16817 | /* Handle .tpreldword. */ | |
16818 | ||
16819 | static void | |
16820 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
16821 | { | |
16822 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
16823 | } |
16824 | ||
6478892d TS |
16825 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
16826 | code. It sets the offset to use in gp_rel relocations. */ | |
16827 | ||
16828 | static void | |
17a2f251 | 16829 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16830 | { |
16831 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
16832 | We also need NewABI support. */ | |
16833 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16834 | { | |
16835 | s_ignore (0); | |
16836 | return; | |
16837 | } | |
16838 | ||
def2e0dd | 16839 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
16840 | |
16841 | demand_empty_rest_of_line (); | |
16842 | } | |
16843 | ||
252b5132 RH |
16844 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
16845 | code. It generates a 32 bit GP relative reloc. */ | |
16846 | ||
16847 | static void | |
17a2f251 | 16848 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16849 | { |
a8dbcb85 TS |
16850 | segment_info_type *si; |
16851 | struct insn_label_list *l; | |
252b5132 RH |
16852 | expressionS ex; |
16853 | char *p; | |
16854 | ||
16855 | /* When not generating PIC code, this is treated as .word. */ | |
16856 | if (mips_pic != SVR4_PIC) | |
16857 | { | |
16858 | s_cons (2); | |
16859 | return; | |
16860 | } | |
16861 | ||
a8dbcb85 TS |
16862 | si = seg_info (now_seg); |
16863 | l = si->label_list; | |
7d10b47d | 16864 | mips_emit_delays (); |
252b5132 | 16865 | if (auto_align) |
462427c4 | 16866 | mips_align (2, 0, l); |
252b5132 RH |
16867 | |
16868 | expression (&ex); | |
a1facbec | 16869 | mips_clear_insn_labels (); |
252b5132 RH |
16870 | |
16871 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16872 | { | |
16873 | as_bad (_("Unsupported use of .gpword")); | |
16874 | ignore_rest_of_line (); | |
16875 | } | |
16876 | ||
16877 | p = frag_more (4); | |
17a2f251 | 16878 | md_number_to_chars (p, 0, 4); |
b34976b6 | 16879 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 16880 | BFD_RELOC_GPREL32); |
252b5132 RH |
16881 | |
16882 | demand_empty_rest_of_line (); | |
16883 | } | |
16884 | ||
10181a0d | 16885 | static void |
17a2f251 | 16886 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 16887 | { |
a8dbcb85 TS |
16888 | segment_info_type *si; |
16889 | struct insn_label_list *l; | |
10181a0d AO |
16890 | expressionS ex; |
16891 | char *p; | |
16892 | ||
16893 | /* When not generating PIC code, this is treated as .dword. */ | |
16894 | if (mips_pic != SVR4_PIC) | |
16895 | { | |
16896 | s_cons (3); | |
16897 | return; | |
16898 | } | |
16899 | ||
a8dbcb85 TS |
16900 | si = seg_info (now_seg); |
16901 | l = si->label_list; | |
7d10b47d | 16902 | mips_emit_delays (); |
10181a0d | 16903 | if (auto_align) |
462427c4 | 16904 | mips_align (3, 0, l); |
10181a0d AO |
16905 | |
16906 | expression (&ex); | |
a1facbec | 16907 | mips_clear_insn_labels (); |
10181a0d AO |
16908 | |
16909 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16910 | { | |
16911 | as_bad (_("Unsupported use of .gpdword")); | |
16912 | ignore_rest_of_line (); | |
16913 | } | |
16914 | ||
16915 | p = frag_more (8); | |
17a2f251 | 16916 | md_number_to_chars (p, 0, 8); |
a105a300 | 16917 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 16918 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
16919 | |
16920 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
16921 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
16922 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
16923 | |
16924 | demand_empty_rest_of_line (); | |
16925 | } | |
16926 | ||
252b5132 RH |
16927 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
16928 | tables in SVR4 PIC code. */ | |
16929 | ||
16930 | static void | |
17a2f251 | 16931 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16932 | { |
252b5132 RH |
16933 | int reg; |
16934 | ||
10181a0d AO |
16935 | /* This is ignored when not generating SVR4 PIC code. */ |
16936 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
16937 | { |
16938 | s_ignore (0); | |
16939 | return; | |
16940 | } | |
16941 | ||
16942 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 16943 | macro_start (); |
252b5132 | 16944 | reg = tc_get_register (0); |
67c0d1eb | 16945 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 16946 | macro_end (); |
252b5132 | 16947 | |
bdaaa2e1 | 16948 | demand_empty_rest_of_line (); |
252b5132 RH |
16949 | } |
16950 | ||
16951 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 16952 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
16953 | such as generating jalx instructions when needed. We also make |
16954 | them odd for the duration of the assembly, in order to generate the | |
16955 | right sort of code. We will make them even in the adjust_symtab | |
16956 | routine, while leaving them marked. This is convenient for the | |
16957 | debugger and the disassembler. The linker knows to make them odd | |
16958 | again. */ | |
16959 | ||
16960 | static void | |
17a2f251 | 16961 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16962 | { |
df58fc94 | 16963 | mips_mark_labels (); |
252b5132 RH |
16964 | |
16965 | demand_empty_rest_of_line (); | |
16966 | } | |
16967 | ||
16968 | /* Handle a .stabn directive. We need these in order to mark a label | |
16969 | as being a mips16 text label correctly. Sometimes the compiler | |
16970 | will emit a label, followed by a .stabn, and then switch sections. | |
16971 | If the label and .stabn are in mips16 mode, then the label is | |
16972 | really a mips16 text label. */ | |
16973 | ||
16974 | static void | |
17a2f251 | 16975 | s_mips_stab (int type) |
252b5132 | 16976 | { |
f9419b05 | 16977 | if (type == 'n') |
df58fc94 | 16978 | mips_mark_labels (); |
252b5132 RH |
16979 | |
16980 | s_stab (type); | |
16981 | } | |
16982 | ||
54f4ddb3 | 16983 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
16984 | |
16985 | static void | |
17a2f251 | 16986 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16987 | { |
16988 | char *name; | |
16989 | int c; | |
16990 | symbolS *symbolP; | |
16991 | expressionS exp; | |
16992 | ||
16993 | name = input_line_pointer; | |
16994 | c = get_symbol_end (); | |
16995 | symbolP = symbol_find_or_make (name); | |
16996 | S_SET_WEAK (symbolP); | |
16997 | *input_line_pointer = c; | |
16998 | ||
16999 | SKIP_WHITESPACE (); | |
17000 | ||
17001 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
17002 | { | |
17003 | if (S_IS_DEFINED (symbolP)) | |
17004 | { | |
20203fb9 | 17005 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
17006 | S_GET_NAME (symbolP)); |
17007 | ignore_rest_of_line (); | |
17008 | return; | |
17009 | } | |
bdaaa2e1 | 17010 | |
252b5132 RH |
17011 | if (*input_line_pointer == ',') |
17012 | { | |
17013 | ++input_line_pointer; | |
17014 | SKIP_WHITESPACE (); | |
17015 | } | |
bdaaa2e1 | 17016 | |
252b5132 RH |
17017 | expression (&exp); |
17018 | if (exp.X_op != O_symbol) | |
17019 | { | |
20203fb9 | 17020 | as_bad (_("bad .weakext directive")); |
98d3f06f | 17021 | ignore_rest_of_line (); |
252b5132 RH |
17022 | return; |
17023 | } | |
49309057 | 17024 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
17025 | } |
17026 | ||
17027 | demand_empty_rest_of_line (); | |
17028 | } | |
17029 | ||
17030 | /* Parse a register string into a number. Called from the ECOFF code | |
17031 | to parse .frame. The argument is non-zero if this is the frame | |
17032 | register, so that we can record it in mips_frame_reg. */ | |
17033 | ||
17034 | int | |
17a2f251 | 17035 | tc_get_register (int frame) |
252b5132 | 17036 | { |
707bfff6 | 17037 | unsigned int reg; |
252b5132 RH |
17038 | |
17039 | SKIP_WHITESPACE (); | |
707bfff6 TS |
17040 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
17041 | reg = 0; | |
252b5132 | 17042 | if (frame) |
7a621144 DJ |
17043 | { |
17044 | mips_frame_reg = reg != 0 ? reg : SP; | |
17045 | mips_frame_reg_valid = 1; | |
17046 | mips_cprestore_valid = 0; | |
17047 | } | |
252b5132 RH |
17048 | return reg; |
17049 | } | |
17050 | ||
17051 | valueT | |
17a2f251 | 17052 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
17053 | { |
17054 | int align = bfd_get_section_alignment (stdoutput, seg); | |
17055 | ||
b4c71f56 TS |
17056 | if (IS_ELF) |
17057 | { | |
17058 | /* We don't need to align ELF sections to the full alignment. | |
17059 | However, Irix 5 may prefer that we align them at least to a 16 | |
17060 | byte boundary. We don't bother to align the sections if we | |
17061 | are targeted for an embedded system. */ | |
c41e87e3 | 17062 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
17063 | return addr; |
17064 | if (align > 4) | |
17065 | align = 4; | |
17066 | } | |
252b5132 RH |
17067 | |
17068 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
17069 | } | |
17070 | ||
17071 | /* Utility routine, called from above as well. If called while the | |
17072 | input file is still being read, it's only an approximation. (For | |
17073 | example, a symbol may later become defined which appeared to be | |
17074 | undefined earlier.) */ | |
17075 | ||
17076 | static int | |
17a2f251 | 17077 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17078 | { |
17079 | if (sym == 0) | |
17080 | return 0; | |
17081 | ||
4d0d148d | 17082 | if (g_switch_value > 0) |
252b5132 RH |
17083 | { |
17084 | const char *symname; | |
17085 | int change; | |
17086 | ||
c9914766 | 17087 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17088 | register. It can be if it is smaller than the -G size or if |
17089 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17090 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17091 | they can. */ |
17092 | symname = S_GET_NAME (sym); | |
17093 | if (symname != (const char *) NULL | |
17094 | && (strcmp (symname, "eprol") == 0 | |
17095 | || strcmp (symname, "etext") == 0 | |
17096 | || strcmp (symname, "_gp") == 0 | |
17097 | || strcmp (symname, "edata") == 0 | |
17098 | || strcmp (symname, "_fbss") == 0 | |
17099 | || strcmp (symname, "_fdata") == 0 | |
17100 | || strcmp (symname, "_ftext") == 0 | |
17101 | || strcmp (symname, "end") == 0 | |
17102 | || strcmp (symname, "_gp_disp") == 0)) | |
17103 | change = 1; | |
17104 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17105 | && (0 | |
17106 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17107 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17108 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17109 | <= g_switch_value)) | |
252b5132 RH |
17110 | #endif |
17111 | /* We must defer this decision until after the whole | |
17112 | file has been read, since there might be a .extern | |
17113 | after the first use of this symbol. */ | |
17114 | || (before_relaxing | |
17115 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17116 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17117 | #endif |
17118 | && S_GET_VALUE (sym) == 0) | |
17119 | || (S_GET_VALUE (sym) != 0 | |
17120 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17121 | change = 0; | |
17122 | else | |
17123 | { | |
17124 | const char *segname; | |
17125 | ||
17126 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17127 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17128 | && strcmp (segname, ".lit4") != 0); |
17129 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17130 | && strcmp (segname, ".sbss") != 0 |
17131 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17132 | && strncmp (segname, ".sbss.", 6) != 0 |
17133 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17134 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17135 | } |
17136 | return change; | |
17137 | } | |
17138 | else | |
c9914766 | 17139 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17140 | return 1; |
17141 | } | |
17142 | ||
5919d012 RS |
17143 | |
17144 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17145 | ||
17146 | static bfd_boolean | |
17a2f251 | 17147 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
17148 | { |
17149 | asection *symsec; | |
5919d012 RS |
17150 | |
17151 | /* Handle the case of a symbol equated to another symbol. */ | |
17152 | while (symbol_equated_reloc_p (sym)) | |
17153 | { | |
17154 | symbolS *n; | |
17155 | ||
5f0fe04b | 17156 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17157 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17158 | if (n == sym) | |
17159 | break; | |
17160 | sym = n; | |
17161 | } | |
17162 | ||
df1f3cda DD |
17163 | if (symbol_section_p (sym)) |
17164 | return TRUE; | |
17165 | ||
5919d012 RS |
17166 | symsec = S_GET_SEGMENT (sym); |
17167 | ||
5919d012 | 17168 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17169 | return (!bfd_is_und_section (symsec) |
17170 | && !bfd_is_abs_section (symsec) | |
5f0fe04b TS |
17171 | && !bfd_is_com_section (symsec) |
17172 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
17173 | #ifdef OBJ_ELF |
17174 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 17175 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
17176 | #endif |
17177 | ); | |
17178 | } | |
17179 | ||
17180 | ||
252b5132 RH |
17181 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17182 | extended opcode. SEC is the section the frag is in. */ | |
17183 | ||
17184 | static int | |
17a2f251 | 17185 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
17186 | { |
17187 | int type; | |
3994f87e | 17188 | const struct mips16_immed_operand *op; |
252b5132 RH |
17189 | offsetT val; |
17190 | int mintiny, maxtiny; | |
17191 | segT symsec; | |
98aa84af | 17192 | fragS *sym_frag; |
252b5132 RH |
17193 | |
17194 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17195 | return 0; | |
17196 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17197 | return 1; | |
17198 | ||
17199 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17200 | op = mips16_immed_operands; | |
17201 | while (op->type != type) | |
17202 | { | |
17203 | ++op; | |
9c2799c2 | 17204 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
17205 | } |
17206 | ||
17207 | if (op->unsp) | |
17208 | { | |
17209 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
17210 | { | |
17211 | mintiny = 1; | |
17212 | maxtiny = 1 << op->nbits; | |
17213 | } | |
17214 | else | |
17215 | { | |
17216 | mintiny = 0; | |
17217 | maxtiny = (1 << op->nbits) - 1; | |
17218 | } | |
17219 | } | |
17220 | else | |
17221 | { | |
17222 | mintiny = - (1 << (op->nbits - 1)); | |
17223 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
17224 | } | |
17225 | ||
98aa84af | 17226 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 17227 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 17228 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
17229 | |
17230 | if (op->pcrel) | |
17231 | { | |
17232 | addressT addr; | |
17233 | ||
17234 | /* We won't have the section when we are called from | |
17235 | mips_relax_frag. However, we will always have been called | |
17236 | from md_estimate_size_before_relax first. If this is a | |
17237 | branch to a different section, we mark it as such. If SEC is | |
17238 | NULL, and the frag is not marked, then it must be a branch to | |
17239 | the same section. */ | |
17240 | if (sec == NULL) | |
17241 | { | |
17242 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
17243 | return 1; | |
17244 | } | |
17245 | else | |
17246 | { | |
98aa84af | 17247 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
17248 | if (symsec != sec) |
17249 | { | |
17250 | fragp->fr_subtype = | |
17251 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17252 | ||
17253 | /* FIXME: We should support this, and let the linker | |
17254 | catch branches and loads that are out of range. */ | |
17255 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
17256 | _("unsupported PC relative reference to different section")); | |
17257 | ||
17258 | return 1; | |
17259 | } | |
98aa84af AM |
17260 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
17261 | /* Assume non-extended on the first relaxation pass. | |
17262 | The address we have calculated will be bogus if this is | |
17263 | a forward branch to another frag, as the forward frag | |
17264 | will have fr_address == 0. */ | |
17265 | return 0; | |
252b5132 RH |
17266 | } |
17267 | ||
17268 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
17269 | the same section. If the relax_marker of the symbol fragment |
17270 | differs from the relax_marker of this fragment, we have not | |
17271 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
17272 | in STRETCH in order to get a better estimate of the address. |
17273 | This particularly matters because of the shift bits. */ | |
17274 | if (stretch != 0 | |
98aa84af | 17275 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
17276 | { |
17277 | fragS *f; | |
17278 | ||
17279 | /* Adjust stretch for any alignment frag. Note that if have | |
17280 | been expanding the earlier code, the symbol may be | |
17281 | defined in what appears to be an earlier frag. FIXME: | |
17282 | This doesn't handle the fr_subtype field, which specifies | |
17283 | a maximum number of bytes to skip when doing an | |
17284 | alignment. */ | |
98aa84af | 17285 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
17286 | { |
17287 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17288 | { | |
17289 | if (stretch < 0) | |
17290 | stretch = - ((- stretch) | |
17291 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
17292 | else | |
17293 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
17294 | if (stretch == 0) | |
17295 | break; | |
17296 | } | |
17297 | } | |
17298 | if (f != NULL) | |
17299 | val += stretch; | |
17300 | } | |
17301 | ||
17302 | addr = fragp->fr_address + fragp->fr_fix; | |
17303 | ||
17304 | /* The base address rules are complicated. The base address of | |
17305 | a branch is the following instruction. The base address of a | |
17306 | PC relative load or add is the instruction itself, but if it | |
17307 | is in a delay slot (in which case it can not be extended) use | |
17308 | the address of the instruction whose delay slot it is in. */ | |
17309 | if (type == 'p' || type == 'q') | |
17310 | { | |
17311 | addr += 2; | |
17312 | ||
17313 | /* If we are currently assuming that this frag should be | |
17314 | extended, then, the current address is two bytes | |
bdaaa2e1 | 17315 | higher. */ |
252b5132 RH |
17316 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
17317 | addr += 2; | |
17318 | ||
17319 | /* Ignore the low bit in the target, since it will be set | |
17320 | for a text label. */ | |
17321 | if ((val & 1) != 0) | |
17322 | --val; | |
17323 | } | |
17324 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17325 | addr -= 4; | |
17326 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17327 | addr -= 2; | |
17328 | ||
17329 | val -= addr & ~ ((1 << op->shift) - 1); | |
17330 | ||
17331 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
17332 | if (type == 'p' || type == 'q') | |
17333 | val /= 2; | |
17334 | ||
17335 | /* If any of the shifted bits are set, we must use an extended | |
17336 | opcode. If the address depends on the size of this | |
17337 | instruction, this can lead to a loop, so we arrange to always | |
17338 | use an extended opcode. We only check this when we are in | |
17339 | the main relaxation loop, when SEC is NULL. */ | |
17340 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
17341 | { | |
17342 | fragp->fr_subtype = | |
17343 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17344 | return 1; | |
17345 | } | |
17346 | ||
17347 | /* If we are about to mark a frag as extended because the value | |
17348 | is precisely maxtiny + 1, then there is a chance of an | |
17349 | infinite loop as in the following code: | |
17350 | la $4,foo | |
17351 | .skip 1020 | |
17352 | .align 2 | |
17353 | foo: | |
17354 | In this case when the la is extended, foo is 0x3fc bytes | |
17355 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17356 | the la must be extended. To avoid this loop, we mark the | |
17357 | frag as extended if it was small, and is about to become | |
17358 | extended with a value of maxtiny + 1. */ | |
17359 | if (val == ((maxtiny + 1) << op->shift) | |
17360 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
17361 | && sec == NULL) | |
17362 | { | |
17363 | fragp->fr_subtype = | |
17364 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17365 | return 1; | |
17366 | } | |
17367 | } | |
17368 | else if (symsec != absolute_section && sec != NULL) | |
17369 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
17370 | ||
17371 | if ((val & ((1 << op->shift) - 1)) != 0 | |
17372 | || val < (mintiny << op->shift) | |
17373 | || val > (maxtiny << op->shift)) | |
17374 | return 1; | |
17375 | else | |
17376 | return 0; | |
17377 | } | |
17378 | ||
4a6a3df4 AO |
17379 | /* Compute the length of a branch sequence, and adjust the |
17380 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17381 | worst-case length is computed, with UPDATE being used to indicate | |
17382 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17383 | branch is to be computed. */ | |
17384 | static int | |
17a2f251 | 17385 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17386 | { |
b34976b6 | 17387 | bfd_boolean toofar; |
4a6a3df4 AO |
17388 | int length; |
17389 | ||
17390 | if (fragp | |
17391 | && S_IS_DEFINED (fragp->fr_symbol) | |
17392 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17393 | { | |
17394 | addressT addr; | |
17395 | offsetT val; | |
17396 | ||
17397 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17398 | ||
17399 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17400 | ||
17401 | val -= addr; | |
17402 | ||
17403 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17404 | } | |
17405 | else if (fragp) | |
17406 | /* If the symbol is not defined or it's in a different segment, | |
17407 | assume the user knows what's going on and emit a short | |
17408 | branch. */ | |
b34976b6 | 17409 | toofar = FALSE; |
4a6a3df4 | 17410 | else |
b34976b6 | 17411 | toofar = TRUE; |
4a6a3df4 AO |
17412 | |
17413 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17414 | fragp->fr_subtype | |
66b3e8da MR |
17415 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
17416 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
17417 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17418 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17419 | toofar); | |
17420 | ||
17421 | length = 4; | |
17422 | if (toofar) | |
17423 | { | |
17424 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17425 | length += 8; | |
17426 | ||
17427 | if (mips_pic != NO_PIC) | |
17428 | { | |
17429 | /* Additional space for PIC loading of target address. */ | |
17430 | length += 8; | |
17431 | if (mips_opts.isa == ISA_MIPS1) | |
17432 | /* Additional space for $at-stabilizing nop. */ | |
17433 | length += 4; | |
17434 | } | |
17435 | ||
17436 | /* If branch is conditional. */ | |
17437 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17438 | length += 8; | |
17439 | } | |
b34976b6 | 17440 | |
4a6a3df4 AO |
17441 | return length; |
17442 | } | |
17443 | ||
df58fc94 RS |
17444 | /* Compute the length of a branch sequence, and adjust the |
17445 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17446 | worst-case length is computed, with UPDATE being used to indicate | |
17447 | whether an unconditional (-1), or regular (0) branch is to be | |
17448 | computed. */ | |
17449 | ||
17450 | static int | |
17451 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17452 | { | |
17453 | bfd_boolean toofar; | |
17454 | int length; | |
17455 | ||
17456 | if (fragp | |
17457 | && S_IS_DEFINED (fragp->fr_symbol) | |
17458 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17459 | { | |
17460 | addressT addr; | |
17461 | offsetT val; | |
17462 | ||
17463 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17464 | /* Ignore the low bit in the target, since it will be set | |
17465 | for a text label. */ | |
17466 | if ((val & 1) != 0) | |
17467 | --val; | |
17468 | ||
17469 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17470 | ||
17471 | val -= addr; | |
17472 | ||
17473 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17474 | } | |
17475 | else if (fragp) | |
17476 | /* If the symbol is not defined or it's in a different segment, | |
17477 | assume the user knows what's going on and emit a short | |
17478 | branch. */ | |
17479 | toofar = FALSE; | |
17480 | else | |
17481 | toofar = TRUE; | |
17482 | ||
17483 | if (fragp && update | |
17484 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17485 | fragp->fr_subtype = (toofar | |
17486 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17487 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17488 | ||
17489 | length = 4; | |
17490 | if (toofar) | |
17491 | { | |
17492 | bfd_boolean compact_known = fragp != NULL; | |
17493 | bfd_boolean compact = FALSE; | |
17494 | bfd_boolean uncond; | |
17495 | ||
17496 | if (compact_known) | |
17497 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17498 | if (fragp) | |
17499 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
17500 | else | |
17501 | uncond = update < 0; | |
17502 | ||
17503 | /* If label is out of range, we turn branch <br>: | |
17504 | ||
17505 | <br> label # 4 bytes | |
17506 | 0: | |
17507 | ||
17508 | into: | |
17509 | ||
17510 | j label # 4 bytes | |
17511 | nop # 2 bytes if compact && !PIC | |
17512 | 0: | |
17513 | */ | |
17514 | if (mips_pic == NO_PIC && (!compact_known || compact)) | |
17515 | length += 2; | |
17516 | ||
17517 | /* If assembling PIC code, we further turn: | |
17518 | ||
17519 | j label # 4 bytes | |
17520 | ||
17521 | into: | |
17522 | ||
17523 | lw/ld at, %got(label)(gp) # 4 bytes | |
17524 | d/addiu at, %lo(label) # 4 bytes | |
17525 | jr/c at # 2 bytes | |
17526 | */ | |
17527 | if (mips_pic != NO_PIC) | |
17528 | length += 6; | |
17529 | ||
17530 | /* If branch <br> is conditional, we prepend negated branch <brneg>: | |
17531 | ||
17532 | <brneg> 0f # 4 bytes | |
17533 | nop # 2 bytes if !compact | |
17534 | */ | |
17535 | if (!uncond) | |
17536 | length += (compact_known && compact) ? 4 : 6; | |
17537 | } | |
17538 | ||
17539 | return length; | |
17540 | } | |
17541 | ||
17542 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17543 | bit accordingly. */ | |
17544 | ||
17545 | static int | |
17546 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17547 | { | |
17548 | bfd_boolean toofar; | |
17549 | ||
df58fc94 RS |
17550 | if (fragp |
17551 | && S_IS_DEFINED (fragp->fr_symbol) | |
17552 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17553 | { | |
17554 | addressT addr; | |
17555 | offsetT val; | |
17556 | int type; | |
17557 | ||
17558 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17559 | /* Ignore the low bit in the target, since it will be set | |
17560 | for a text label. */ | |
17561 | if ((val & 1) != 0) | |
17562 | --val; | |
17563 | ||
17564 | /* Assume this is a 2-byte branch. */ | |
17565 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17566 | ||
17567 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17568 | long branches. */ | |
17569 | ||
17570 | val -= addr; | |
17571 | ||
17572 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17573 | if (type == 'D') | |
17574 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17575 | else if (type == 'E') | |
17576 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17577 | else | |
17578 | abort (); | |
17579 | } | |
17580 | else | |
17581 | /* If the symbol is not defined or it's in a different segment, | |
17582 | we emit a normal 32-bit branch. */ | |
17583 | toofar = TRUE; | |
17584 | ||
17585 | if (fragp && update | |
17586 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17587 | fragp->fr_subtype | |
17588 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17589 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17590 | ||
17591 | if (toofar) | |
17592 | return 4; | |
17593 | ||
17594 | return 2; | |
17595 | } | |
17596 | ||
252b5132 RH |
17597 | /* Estimate the size of a frag before relaxing. Unless this is the |
17598 | mips16, we are not really relaxing here, and the final size is | |
17599 | encoded in the subtype information. For the mips16, we have to | |
17600 | decide whether we are using an extended opcode or not. */ | |
17601 | ||
252b5132 | 17602 | int |
17a2f251 | 17603 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17604 | { |
5919d012 | 17605 | int change; |
252b5132 | 17606 | |
4a6a3df4 AO |
17607 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17608 | { | |
17609 | ||
b34976b6 AM |
17610 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17611 | ||
4a6a3df4 AO |
17612 | return fragp->fr_var; |
17613 | } | |
17614 | ||
252b5132 | 17615 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
17616 | /* We don't want to modify the EXTENDED bit here; it might get us |
17617 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17618 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 | 17619 | |
df58fc94 RS |
17620 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17621 | { | |
17622 | int length = 4; | |
17623 | ||
17624 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17625 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17626 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17627 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17628 | fragp->fr_var = length; | |
17629 | ||
17630 | return length; | |
17631 | } | |
17632 | ||
252b5132 | 17633 | if (mips_pic == NO_PIC) |
5919d012 | 17634 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 17635 | else if (mips_pic == SVR4_PIC) |
5919d012 | 17636 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
17637 | else if (mips_pic == VXWORKS_PIC) |
17638 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
17639 | change = 0; | |
252b5132 RH |
17640 | else |
17641 | abort (); | |
17642 | ||
17643 | if (change) | |
17644 | { | |
4d7206a2 | 17645 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17646 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17647 | } |
4d7206a2 RS |
17648 | else |
17649 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17650 | } |
17651 | ||
17652 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17653 | should be converted into a reloc against a section. */ |
252b5132 RH |
17654 | |
17655 | int | |
17a2f251 | 17656 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17657 | { |
252b5132 RH |
17658 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17659 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17660 | return 0; | |
a161fe53 | 17661 | |
252b5132 RH |
17662 | if (fixp->fx_addsy == NULL) |
17663 | return 1; | |
a161fe53 | 17664 | |
de7e6852 RS |
17665 | /* If symbol SYM is in a mergeable section, relocations of the form |
17666 | SYM + 0 can usually be made section-relative. The mergeable data | |
17667 | is then identified by the section offset rather than by the symbol. | |
17668 | ||
17669 | However, if we're generating REL LO16 relocations, the offset is split | |
17670 | between the LO16 and parterning high part relocation. The linker will | |
17671 | need to recalculate the complete offset in order to correctly identify | |
17672 | the merge data. | |
17673 | ||
17674 | The linker has traditionally not looked for the parterning high part | |
17675 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
17676 | placed anywhere. Rather than break backwards compatibility by changing | |
17677 | this, it seems better not to force the issue, and instead keep the | |
17678 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 17679 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 17680 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
17681 | && HAVE_IN_PLACE_ADDENDS |
17682 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
17683 | return 0; | |
17684 | ||
ce70d90a MR |
17685 | /* There is no place to store an in-place offset for JALR relocations. |
17686 | Likewise an in-range offset of PC-relative relocations may overflow | |
17687 | the in-place relocatable field if recalculated against the start | |
17688 | address of the symbol's containing section. */ | |
17689 | if (HAVE_IN_PLACE_ADDENDS | |
df58fc94 | 17690 | && (fixp->fx_pcrel || jalr_reloc_p (fixp->fx_r_type))) |
1180b5a4 RS |
17691 | return 0; |
17692 | ||
252b5132 | 17693 | #ifdef OBJ_ELF |
b314ec0e RS |
17694 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
17695 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
17696 | relocations against MIPS16 functions; in this case, the stub becomes | |
17697 | the function's canonical address. | |
17698 | ||
17699 | Floating-point stubs are stored in unique .mips16.call.* or | |
17700 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
17701 | the first relocation in section S must be against F; this is how the | |
17702 | linker determines the target function. All relocations that might | |
17703 | resolve to T must also be against F. We therefore have the following | |
17704 | restrictions, which are given in an intentionally-redundant way: | |
17705 | ||
17706 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
17707 | symbols. | |
17708 | ||
17709 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
17710 | if that stub might be used. | |
17711 | ||
17712 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
17713 | symbols. | |
17714 | ||
17715 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
17716 | that stub might be used. | |
17717 | ||
17718 | There is a further restriction: | |
17719 | ||
df58fc94 RS |
17720 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
17721 | R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on | |
17722 | targets with in-place addends; the relocation field cannot | |
b314ec0e RS |
17723 | encode the low bit. |
17724 | ||
df58fc94 RS |
17725 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
17726 | against a MIPS16 symbol. We deal with (5) by by not reducing any | |
17727 | such relocations on REL targets. | |
b314ec0e RS |
17728 | |
17729 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
17730 | relocation against some symbol R, no relocation against R may be | |
17731 | reduced. (Note that this deals with (2) as well as (1) because | |
17732 | relocations against global symbols will never be reduced on ELF | |
17733 | targets.) This approach is a little simpler than trying to detect | |
17734 | stub sections, and gives the "all or nothing" per-symbol consistency | |
17735 | that we have for MIPS16 symbols. */ | |
f43abd2b | 17736 | if (IS_ELF |
b314ec0e | 17737 | && fixp->fx_subsy == NULL |
30c09090 | 17738 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
df58fc94 RS |
17739 | || *symbol_get_tc (fixp->fx_addsy) |
17740 | || (HAVE_IN_PLACE_ADDENDS | |
17741 | && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) | |
17742 | && jmp_reloc_p (fixp->fx_r_type)))) | |
252b5132 RH |
17743 | return 0; |
17744 | #endif | |
a161fe53 | 17745 | |
252b5132 RH |
17746 | return 1; |
17747 | } | |
17748 | ||
17749 | /* Translate internal representation of relocation info to BFD target | |
17750 | format. */ | |
17751 | ||
17752 | arelent ** | |
17a2f251 | 17753 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
17754 | { |
17755 | static arelent *retval[4]; | |
17756 | arelent *reloc; | |
17757 | bfd_reloc_code_real_type code; | |
17758 | ||
4b0cff4e TS |
17759 | memset (retval, 0, sizeof(retval)); |
17760 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
17761 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
17762 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
17763 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
17764 | ||
bad36eac DJ |
17765 | if (fixp->fx_pcrel) |
17766 | { | |
df58fc94 RS |
17767 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
17768 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
17769 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
17770 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
bad36eac DJ |
17771 | |
17772 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
17773 | Relocations want only the symbol offset. */ | |
17774 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 17775 | if (!IS_ELF) |
bad36eac DJ |
17776 | { |
17777 | /* A gruesome hack which is a result of the gruesome gas | |
17778 | reloc handling. What's worse, for COFF (as opposed to | |
17779 | ECOFF), we might need yet another copy of reloc->address. | |
17780 | See bfd_install_relocation. */ | |
17781 | reloc->addend += reloc->address; | |
17782 | } | |
17783 | } | |
17784 | else | |
17785 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 17786 | |
438c16b8 TS |
17787 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
17788 | entry to be used in the relocation's section offset. */ | |
17789 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
17790 | { |
17791 | reloc->address = reloc->addend; | |
17792 | reloc->addend = 0; | |
17793 | } | |
17794 | ||
252b5132 | 17795 | code = fixp->fx_r_type; |
252b5132 | 17796 | |
bad36eac | 17797 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
17798 | if (reloc->howto == NULL) |
17799 | { | |
17800 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
17801 | _("Can not represent %s relocation in this object file format"), | |
17802 | bfd_get_reloc_code_name (code)); | |
17803 | retval[0] = NULL; | |
17804 | } | |
17805 | ||
17806 | return retval; | |
17807 | } | |
17808 | ||
17809 | /* Relax a machine dependent frag. This returns the amount by which | |
17810 | the current size of the frag should change. */ | |
17811 | ||
17812 | int | |
17a2f251 | 17813 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 17814 | { |
4a6a3df4 AO |
17815 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17816 | { | |
17817 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
17818 | |
17819 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
17820 | |
17821 | return fragp->fr_var - old_var; | |
17822 | } | |
17823 | ||
df58fc94 RS |
17824 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17825 | { | |
17826 | offsetT old_var = fragp->fr_var; | |
17827 | offsetT new_var = 4; | |
17828 | ||
17829 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17830 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
17831 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17832 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
17833 | fragp->fr_var = new_var; | |
17834 | ||
17835 | return new_var - old_var; | |
17836 | } | |
17837 | ||
252b5132 RH |
17838 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
17839 | return 0; | |
17840 | ||
c4e7957c | 17841 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
17842 | { |
17843 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17844 | return 0; | |
17845 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
17846 | return 2; | |
17847 | } | |
17848 | else | |
17849 | { | |
17850 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17851 | return 0; | |
17852 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
17853 | return -2; | |
17854 | } | |
17855 | ||
17856 | return 0; | |
17857 | } | |
17858 | ||
17859 | /* Convert a machine dependent frag. */ | |
17860 | ||
17861 | void | |
17a2f251 | 17862 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 17863 | { |
4a6a3df4 AO |
17864 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17865 | { | |
4d68580a | 17866 | char *buf; |
4a6a3df4 AO |
17867 | unsigned long insn; |
17868 | expressionS exp; | |
17869 | fixS *fixp; | |
b34976b6 | 17870 | |
4d68580a RS |
17871 | buf = fragp->fr_literal + fragp->fr_fix; |
17872 | insn = read_insn (buf); | |
b34976b6 | 17873 | |
4a6a3df4 AO |
17874 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
17875 | { | |
17876 | /* We generate a fixup instead of applying it right now | |
17877 | because, if there are linker relaxations, we're going to | |
17878 | need the relocations. */ | |
17879 | exp.X_op = O_symbol; | |
17880 | exp.X_add_symbol = fragp->fr_symbol; | |
17881 | exp.X_add_number = fragp->fr_offset; | |
17882 | ||
4d68580a RS |
17883 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
17884 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
17885 | fixp->fx_file = fragp->fr_file; |
17886 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 17887 | |
4d68580a | 17888 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
17889 | } |
17890 | else | |
17891 | { | |
17892 | int i; | |
17893 | ||
17894 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 17895 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
17896 | |
17897 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
17898 | goto uncond; | |
17899 | ||
17900 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17901 | { | |
17902 | /* Reverse the branch. */ | |
17903 | switch ((insn >> 28) & 0xf) | |
17904 | { | |
17905 | case 4: | |
17906 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
17907 | have the condition reversed by tweaking a single | |
17908 | bit, and their opcodes all have 0x4???????. */ | |
9c2799c2 | 17909 | gas_assert ((insn & 0xf1000000) == 0x41000000); |
4a6a3df4 AO |
17910 | insn ^= 0x00010000; |
17911 | break; | |
17912 | ||
17913 | case 0: | |
17914 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 17915 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 17916 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
17917 | insn ^= 0x00010000; |
17918 | break; | |
b34976b6 | 17919 | |
4a6a3df4 AO |
17920 | case 1: |
17921 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 17922 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
17923 | insn ^= 0x04000000; |
17924 | break; | |
17925 | ||
17926 | default: | |
17927 | abort (); | |
17928 | } | |
17929 | } | |
17930 | ||
17931 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
17932 | { | |
17933 | /* Clear the and-link bit. */ | |
9c2799c2 | 17934 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 17935 | |
54f4ddb3 TS |
17936 | /* bltzal 0x04100000 bgezal 0x04110000 |
17937 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
17938 | insn &= ~0x00100000; |
17939 | } | |
17940 | ||
17941 | /* Branch over the branch (if the branch was likely) or the | |
17942 | full jump (not likely case). Compute the offset from the | |
17943 | current instruction to branch to. */ | |
17944 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17945 | i = 16; | |
17946 | else | |
17947 | { | |
17948 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 17949 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
17950 | /* How many bytes in instructions from here to the end? */ |
17951 | i = fragp->fr_var - i; | |
17952 | } | |
17953 | /* Convert to instruction count. */ | |
17954 | i >>= 2; | |
17955 | /* Branch counts from the next instruction. */ | |
b34976b6 | 17956 | i--; |
4a6a3df4 AO |
17957 | insn |= i; |
17958 | /* Branch over the jump. */ | |
4d68580a | 17959 | buf = write_insn (buf, insn); |
4a6a3df4 | 17960 | |
54f4ddb3 | 17961 | /* nop */ |
4d68580a | 17962 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
17963 | |
17964 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17965 | { | |
17966 | /* beql $0, $0, 2f */ | |
17967 | insn = 0x50000000; | |
17968 | /* Compute the PC offset from the current instruction to | |
17969 | the end of the variable frag. */ | |
17970 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 17971 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
17972 | /* How many bytes in instructions from here to the end? */ |
17973 | i = fragp->fr_var - i; | |
17974 | /* Convert to instruction count. */ | |
17975 | i >>= 2; | |
17976 | /* Don't decrement i, because we want to branch over the | |
17977 | delay slot. */ | |
4a6a3df4 | 17978 | insn |= i; |
4a6a3df4 | 17979 | |
4d68580a RS |
17980 | buf = write_insn (buf, insn); |
17981 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
17982 | } |
17983 | ||
17984 | uncond: | |
17985 | if (mips_pic == NO_PIC) | |
17986 | { | |
17987 | /* j or jal. */ | |
17988 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
17989 | ? 0x0c000000 : 0x08000000); | |
17990 | exp.X_op = O_symbol; | |
17991 | exp.X_add_symbol = fragp->fr_symbol; | |
17992 | exp.X_add_number = fragp->fr_offset; | |
17993 | ||
4d68580a RS |
17994 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
17995 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
17996 | fixp->fx_file = fragp->fr_file; |
17997 | fixp->fx_line = fragp->fr_line; | |
17998 | ||
4d68580a | 17999 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18000 | } |
18001 | else | |
18002 | { | |
66b3e8da MR |
18003 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
18004 | ||
4a6a3df4 | 18005 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
18006 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
18007 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
18008 | exp.X_op = O_symbol; |
18009 | exp.X_add_symbol = fragp->fr_symbol; | |
18010 | exp.X_add_number = fragp->fr_offset; | |
18011 | ||
18012 | if (fragp->fr_offset) | |
18013 | { | |
18014 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18015 | exp.X_add_number = 0; | |
18016 | } | |
18017 | ||
4d68580a RS |
18018 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18019 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
18020 | fixp->fx_file = fragp->fr_file; |
18021 | fixp->fx_line = fragp->fr_line; | |
18022 | ||
4d68580a | 18023 | buf = write_insn (buf, insn); |
b34976b6 | 18024 | |
4a6a3df4 | 18025 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
18026 | /* nop */ |
18027 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18028 | |
18029 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
18030 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
18031 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 18032 | |
4d68580a RS |
18033 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18034 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
18035 | fixp->fx_file = fragp->fr_file; |
18036 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18037 | |
4d68580a | 18038 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18039 | |
18040 | /* j(al)r $at. */ | |
18041 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 18042 | insn = 0x0000f809; |
4a6a3df4 | 18043 | else |
66b3e8da MR |
18044 | insn = 0x00000008; |
18045 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 18046 | |
4d68580a | 18047 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18048 | } |
18049 | } | |
18050 | ||
4a6a3df4 | 18051 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 18052 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
18053 | return; |
18054 | } | |
18055 | ||
df58fc94 RS |
18056 | /* Relax microMIPS branches. */ |
18057 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
18058 | { | |
4d68580a | 18059 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18060 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
18061 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); | |
18062 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18063 | bfd_boolean short_ds; |
df58fc94 RS |
18064 | unsigned long insn; |
18065 | expressionS exp; | |
18066 | fixS *fixp; | |
18067 | ||
18068 | exp.X_op = O_symbol; | |
18069 | exp.X_add_symbol = fragp->fr_symbol; | |
18070 | exp.X_add_number = fragp->fr_offset; | |
18071 | ||
18072 | fragp->fr_fix += fragp->fr_var; | |
18073 | ||
18074 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18075 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18076 | { | |
18077 | /* We generate a fixup instead of applying it right now, | |
18078 | because if there is linker relaxation, we're going to | |
18079 | need the relocations. */ | |
18080 | if (type == 'D') | |
4d68580a | 18081 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18082 | BFD_RELOC_MICROMIPS_10_PCREL_S1); |
18083 | else if (type == 'E') | |
4d68580a | 18084 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18085 | BFD_RELOC_MICROMIPS_7_PCREL_S1); |
18086 | else | |
18087 | abort (); | |
18088 | ||
18089 | fixp->fx_file = fragp->fr_file; | |
18090 | fixp->fx_line = fragp->fr_line; | |
18091 | ||
18092 | /* These relocations can have an addend that won't fit in | |
18093 | 2 octets. */ | |
18094 | fixp->fx_no_overflow = 1; | |
18095 | ||
18096 | return; | |
18097 | } | |
18098 | ||
2309ddf2 | 18099 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18100 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18101 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18102 | { | |
18103 | /* We generate a fixup instead of applying it right now, | |
18104 | because if there is linker relaxation, we're going to | |
18105 | need the relocations. */ | |
4d68580a RS |
18106 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18107 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18108 | fixp->fx_file = fragp->fr_file; |
18109 | fixp->fx_line = fragp->fr_line; | |
18110 | ||
18111 | if (type == 0) | |
18112 | return; | |
18113 | } | |
18114 | ||
18115 | /* Relax 16-bit branches to 32-bit branches. */ | |
18116 | if (type != 0) | |
18117 | { | |
4d68580a | 18118 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18119 | |
18120 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18121 | insn = 0x94000000; /* beq */ | |
18122 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18123 | { | |
18124 | unsigned long regno; | |
18125 | ||
18126 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18127 | regno = micromips_to_32_reg_d_map [regno]; | |
18128 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18129 | insn |= regno << MICROMIPSOP_SH_RS; | |
18130 | } | |
18131 | else | |
18132 | abort (); | |
18133 | ||
18134 | /* Nothing else to do, just write it out. */ | |
18135 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18136 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18137 | { | |
4d68580a RS |
18138 | buf = write_compressed_insn (buf, insn, 4); |
18139 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
df58fc94 RS |
18140 | return; |
18141 | } | |
18142 | } | |
18143 | else | |
4d68580a | 18144 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18145 | |
18146 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18147 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18148 | _("Relaxed out-of-range branch into a jump")); | |
18149 | ||
2309ddf2 MR |
18150 | /* Set the short-delay-slot bit. */ |
18151 | short_ds = al && (insn & 0x02000000) != 0; | |
df58fc94 RS |
18152 | |
18153 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18154 | { | |
18155 | symbolS *l; | |
18156 | ||
18157 | /* Reverse the branch. */ | |
18158 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18159 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18160 | insn ^= 0x20000000; | |
18161 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18162 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18163 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18164 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18165 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18166 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18167 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18168 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18169 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18170 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18171 | insn ^= 0x00400000; | |
18172 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18173 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18174 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18175 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18176 | insn ^= 0x00200000; | |
18177 | else | |
18178 | abort (); | |
18179 | ||
18180 | if (al) | |
18181 | { | |
18182 | /* Clear the and-link and short-delay-slot bits. */ | |
18183 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18184 | ||
18185 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18186 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18187 | insn &= ~0x02200000; | |
18188 | } | |
18189 | ||
18190 | /* Make a label at the end for use with the branch. */ | |
18191 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18192 | micromips_label_inc (); | |
18193 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
18194 | if (IS_ELF) | |
18195 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); | |
18196 | #endif | |
18197 | ||
18198 | /* Refer to it. */ | |
4d68580a RS |
18199 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18200 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18201 | fixp->fx_file = fragp->fr_file; |
18202 | fixp->fx_line = fragp->fr_line; | |
18203 | ||
18204 | /* Branch over the jump. */ | |
4d68580a | 18205 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18206 | if (!compact) |
4d68580a RS |
18207 | /* nop */ |
18208 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18209 | } |
18210 | ||
18211 | if (mips_pic == NO_PIC) | |
18212 | { | |
2309ddf2 MR |
18213 | unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */ |
18214 | ||
df58fc94 RS |
18215 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18216 | insn = al ? jal : 0xd4000000; | |
18217 | ||
4d68580a RS |
18218 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18219 | BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18220 | fixp->fx_file = fragp->fr_file; |
18221 | fixp->fx_line = fragp->fr_line; | |
18222 | ||
4d68580a | 18223 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18224 | if (compact) |
4d68580a RS |
18225 | /* nop */ |
18226 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18227 | } |
18228 | else | |
18229 | { | |
18230 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
2309ddf2 MR |
18231 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ |
18232 | unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */ | |
df58fc94 RS |
18233 | |
18234 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18235 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18236 | insn |= at << MICROMIPSOP_SH_RT; | |
18237 | ||
18238 | if (exp.X_add_number) | |
18239 | { | |
18240 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18241 | exp.X_add_number = 0; | |
18242 | } | |
18243 | ||
4d68580a RS |
18244 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18245 | BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18246 | fixp->fx_file = fragp->fr_file; |
18247 | fixp->fx_line = fragp->fr_line; | |
18248 | ||
4d68580a | 18249 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18250 | |
18251 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18252 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18253 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18254 | ||
4d68580a RS |
18255 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18256 | BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18257 | fixp->fx_file = fragp->fr_file; |
18258 | fixp->fx_line = fragp->fr_line; | |
18259 | ||
4d68580a | 18260 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18261 | |
18262 | /* jr/jrc/jalr/jalrs $at */ | |
18263 | insn = al ? jalr : jr; | |
18264 | insn |= at << MICROMIPSOP_SH_MJ; | |
18265 | ||
4d68580a | 18266 | buf = write_compressed_insn (buf, insn, 2); |
df58fc94 RS |
18267 | } |
18268 | ||
4d68580a | 18269 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18270 | return; |
18271 | } | |
18272 | ||
252b5132 RH |
18273 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18274 | { | |
18275 | int type; | |
3994f87e | 18276 | const struct mips16_immed_operand *op; |
252b5132 | 18277 | offsetT val; |
5c04167a RS |
18278 | char *buf; |
18279 | unsigned int user_length, length; | |
252b5132 | 18280 | unsigned long insn; |
5c04167a | 18281 | bfd_boolean ext; |
252b5132 RH |
18282 | |
18283 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
18284 | op = mips16_immed_operands; | |
18285 | while (op->type != type) | |
18286 | ++op; | |
18287 | ||
5c04167a | 18288 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
5f5f22c0 | 18289 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
18290 | if (op->pcrel) |
18291 | { | |
18292 | addressT addr; | |
18293 | ||
18294 | addr = fragp->fr_address + fragp->fr_fix; | |
18295 | ||
18296 | /* The rules for the base address of a PC relative reloc are | |
18297 | complicated; see mips16_extended_frag. */ | |
18298 | if (type == 'p' || type == 'q') | |
18299 | { | |
18300 | addr += 2; | |
18301 | if (ext) | |
18302 | addr += 2; | |
18303 | /* Ignore the low bit in the target, since it will be | |
18304 | set for a text label. */ | |
18305 | if ((val & 1) != 0) | |
18306 | --val; | |
18307 | } | |
18308 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
18309 | addr -= 4; | |
18310 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18311 | addr -= 2; | |
18312 | ||
18313 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
18314 | val -= addr; | |
18315 | ||
18316 | /* Make sure the section winds up with the alignment we have | |
18317 | assumed. */ | |
18318 | if (op->shift > 0) | |
18319 | record_alignment (asec, op->shift); | |
18320 | } | |
18321 | ||
18322 | if (ext | |
18323 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
18324 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
18325 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18326 | _("extended instruction in delay slot")); | |
18327 | ||
5c04167a | 18328 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 18329 | |
4d68580a | 18330 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
18331 | if (ext) |
18332 | insn |= MIPS16_EXTEND; | |
252b5132 | 18333 | |
5c04167a RS |
18334 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
18335 | user_length = 4; | |
18336 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
18337 | user_length = 2; | |
18338 | else | |
18339 | user_length = 0; | |
18340 | ||
43c0598f | 18341 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
c150d1d2 | 18342 | BFD_RELOC_UNUSED, val, user_length, &insn); |
252b5132 | 18343 | |
5c04167a RS |
18344 | length = (ext ? 4 : 2); |
18345 | gas_assert (mips16_opcode_length (insn) == length); | |
18346 | write_compressed_insn (buf, insn, length); | |
18347 | fragp->fr_fix += length; | |
252b5132 RH |
18348 | } |
18349 | else | |
18350 | { | |
df58fc94 RS |
18351 | relax_substateT subtype = fragp->fr_subtype; |
18352 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18353 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18354 | int first, second; |
18355 | fixS *fixp; | |
252b5132 | 18356 | |
df58fc94 RS |
18357 | first = RELAX_FIRST (subtype); |
18358 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18359 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18360 | |
df58fc94 RS |
18361 | /* If the delay slot chosen does not match the size of the instruction, |
18362 | then emit a warning. */ | |
18363 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18364 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18365 | { | |
18366 | relax_substateT s; | |
18367 | const char *msg; | |
18368 | ||
18369 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18370 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18371 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18372 | msg = macro_warning (s); | |
18373 | if (msg != NULL) | |
db9b2be4 | 18374 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
18375 | subtype &= ~s; |
18376 | } | |
18377 | ||
584892a6 | 18378 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18379 | if (use_second == second_longer) |
584892a6 | 18380 | { |
df58fc94 RS |
18381 | relax_substateT s; |
18382 | const char *msg; | |
18383 | ||
18384 | s = (subtype | |
18385 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18386 | msg = macro_warning (s); | |
18387 | if (msg != NULL) | |
db9b2be4 | 18388 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 18389 | subtype &= ~s; |
584892a6 RS |
18390 | } |
18391 | ||
4d7206a2 RS |
18392 | /* Go through all the fixups for the first sequence. Disable them |
18393 | (by marking them as done) if we're going to use the second | |
18394 | sequence instead. */ | |
18395 | while (fixp | |
18396 | && fixp->fx_frag == fragp | |
18397 | && fixp->fx_where < fragp->fr_fix - second) | |
18398 | { | |
df58fc94 | 18399 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18400 | fixp->fx_done = 1; |
18401 | fixp = fixp->fx_next; | |
18402 | } | |
252b5132 | 18403 | |
4d7206a2 RS |
18404 | /* Go through the fixups for the second sequence. Disable them if |
18405 | we're going to use the first sequence, otherwise adjust their | |
18406 | addresses to account for the relaxation. */ | |
18407 | while (fixp && fixp->fx_frag == fragp) | |
18408 | { | |
df58fc94 | 18409 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18410 | fixp->fx_where -= first; |
18411 | else | |
18412 | fixp->fx_done = 1; | |
18413 | fixp = fixp->fx_next; | |
18414 | } | |
18415 | ||
18416 | /* Now modify the frag contents. */ | |
df58fc94 | 18417 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18418 | { |
18419 | char *start; | |
18420 | ||
18421 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18422 | memmove (start, start + first, second); | |
18423 | fragp->fr_fix -= first; | |
18424 | } | |
18425 | else | |
18426 | fragp->fr_fix -= second; | |
252b5132 RH |
18427 | } |
18428 | } | |
18429 | ||
18430 | #ifdef OBJ_ELF | |
18431 | ||
18432 | /* This function is called after the relocs have been generated. | |
18433 | We've been storing mips16 text labels as odd. Here we convert them | |
18434 | back to even for the convenience of the debugger. */ | |
18435 | ||
18436 | void | |
17a2f251 | 18437 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18438 | { |
18439 | asymbol **syms; | |
18440 | unsigned int count, i; | |
18441 | ||
f43abd2b | 18442 | if (!IS_ELF) |
252b5132 RH |
18443 | return; |
18444 | ||
18445 | syms = bfd_get_outsymbols (stdoutput); | |
18446 | count = bfd_get_symcount (stdoutput); | |
18447 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18448 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18449 | && ((*syms)->value & 1) != 0) | |
18450 | { | |
18451 | (*syms)->value &= ~1; | |
18452 | /* If the symbol has an odd size, it was probably computed | |
18453 | incorrectly, so adjust that as well. */ | |
18454 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18455 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18456 | } | |
252b5132 RH |
18457 | } |
18458 | ||
18459 | #endif | |
18460 | ||
a1facbec MR |
18461 | /* This function is called whenever a label is defined, including fake |
18462 | labels instantiated off the dot special symbol. It is used when | |
18463 | handling branch delays; if a branch has a label, we assume we cannot | |
18464 | move it. This also bumps the value of the symbol by 1 in compressed | |
18465 | code. */ | |
252b5132 | 18466 | |
e1b47bd5 | 18467 | static void |
a1facbec | 18468 | mips_record_label (symbolS *sym) |
252b5132 | 18469 | { |
a8dbcb85 | 18470 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18471 | struct insn_label_list *l; |
18472 | ||
18473 | if (free_insn_labels == NULL) | |
18474 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
18475 | else | |
18476 | { | |
18477 | l = free_insn_labels; | |
18478 | free_insn_labels = l->next; | |
18479 | } | |
18480 | ||
18481 | l->label = sym; | |
a8dbcb85 TS |
18482 | l->next = si->label_list; |
18483 | si->label_list = l; | |
a1facbec | 18484 | } |
07a53e5c | 18485 | |
a1facbec MR |
18486 | /* This function is called as tc_frob_label() whenever a label is defined |
18487 | and adds a DWARF-2 record we only want for true labels. */ | |
18488 | ||
18489 | void | |
18490 | mips_define_label (symbolS *sym) | |
18491 | { | |
18492 | mips_record_label (sym); | |
07a53e5c RH |
18493 | #ifdef OBJ_ELF |
18494 | dwarf2_emit_label (sym); | |
18495 | #endif | |
252b5132 | 18496 | } |
e1b47bd5 RS |
18497 | |
18498 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
18499 | is defined. */ | |
18500 | ||
18501 | void | |
18502 | mips_add_dot_label (symbolS *sym) | |
18503 | { | |
18504 | mips_record_label (sym); | |
18505 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
18506 | mips_compressed_mark_label (sym); | |
18507 | } | |
252b5132 RH |
18508 | \f |
18509 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
18510 | ||
18511 | /* Some special processing for a MIPS ELF file. */ | |
18512 | ||
18513 | void | |
17a2f251 | 18514 | mips_elf_final_processing (void) |
252b5132 RH |
18515 | { |
18516 | /* Write out the register information. */ | |
316f5878 | 18517 | if (mips_abi != N64_ABI) |
252b5132 RH |
18518 | { |
18519 | Elf32_RegInfo s; | |
18520 | ||
18521 | s.ri_gprmask = mips_gprmask; | |
18522 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18523 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18524 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18525 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18526 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18527 | ||
18528 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
18529 | ((Elf32_External_RegInfo *) | |
18530 | mips_regmask_frag)); | |
18531 | } | |
18532 | else | |
18533 | { | |
18534 | Elf64_Internal_RegInfo s; | |
18535 | ||
18536 | s.ri_gprmask = mips_gprmask; | |
18537 | s.ri_pad = 0; | |
18538 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18539 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18540 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18541 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18542 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18543 | ||
18544 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
18545 | ((Elf64_External_RegInfo *) | |
18546 | mips_regmask_frag)); | |
18547 | } | |
18548 | ||
18549 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
18550 | sort of BFD interface for this. */ | |
18551 | if (mips_any_noreorder) | |
18552 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
18553 | if (mips_pic != NO_PIC) | |
143d77c5 | 18554 | { |
8b828383 | 18555 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
18556 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
18557 | } | |
18558 | if (mips_abicalls) | |
18559 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 18560 | |
98d3f06f | 18561 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
18562 | /* We may need to define a new flag for DSP ASE, and set this flag when |
18563 | file_ase_dsp is true. */ | |
8b082fb1 | 18564 | /* Same for DSP R2. */ |
ef2e4d86 CF |
18565 | /* We may need to define a new flag for MT ASE, and set this flag when |
18566 | file_ase_mt is true. */ | |
a4672219 TS |
18567 | if (file_ase_mips16) |
18568 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
18569 | if (file_ase_micromips) |
18570 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
1f25f5d3 CD |
18571 | #if 0 /* XXX FIXME */ |
18572 | if (file_ase_mips3d) | |
18573 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18574 | #endif | |
deec1734 CD |
18575 | if (file_ase_mdmx) |
18576 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 18577 | |
bdaaa2e1 | 18578 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 18579 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 18580 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 18581 | else if (mips_abi == O64_ABI) |
252b5132 | 18582 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 18583 | else if (mips_abi == EABI_ABI) |
252b5132 | 18584 | { |
316f5878 | 18585 | if (!file_mips_gp32) |
252b5132 RH |
18586 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
18587 | else | |
18588 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
18589 | } | |
316f5878 | 18590 | else if (mips_abi == N32_ABI) |
be00bddd TS |
18591 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
18592 | ||
c9914766 | 18593 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
18594 | |
18595 | if (mips_32bitmode) | |
18596 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
18597 | |
18598 | #if 0 /* XXX FIXME */ | |
18599 | /* 32 bit code with 64 bit FP registers. */ | |
18600 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
18601 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18602 | #endif | |
252b5132 RH |
18603 | } |
18604 | ||
18605 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
18606 | \f | |
beae10d5 | 18607 | typedef struct proc { |
9b2f1d35 EC |
18608 | symbolS *func_sym; |
18609 | symbolS *func_end_sym; | |
beae10d5 KH |
18610 | unsigned long reg_mask; |
18611 | unsigned long reg_offset; | |
18612 | unsigned long fpreg_mask; | |
18613 | unsigned long fpreg_offset; | |
18614 | unsigned long frame_offset; | |
18615 | unsigned long frame_reg; | |
18616 | unsigned long pc_reg; | |
18617 | } procS; | |
252b5132 RH |
18618 | |
18619 | static procS cur_proc; | |
18620 | static procS *cur_proc_ptr; | |
18621 | static int numprocs; | |
18622 | ||
df58fc94 RS |
18623 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
18624 | as "2", and a normal nop as "0". */ | |
18625 | ||
18626 | #define NOP_OPCODE_MIPS 0 | |
18627 | #define NOP_OPCODE_MIPS16 1 | |
18628 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
18629 | |
18630 | char | |
18631 | mips_nop_opcode (void) | |
18632 | { | |
df58fc94 RS |
18633 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
18634 | return NOP_OPCODE_MICROMIPS; | |
18635 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
18636 | return NOP_OPCODE_MIPS16; | |
18637 | else | |
18638 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
18639 | } |
18640 | ||
df58fc94 RS |
18641 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
18642 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 18643 | |
0a9ef439 | 18644 | void |
17a2f251 | 18645 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 18646 | { |
df58fc94 | 18647 | char nop_opcode; |
742a56fe | 18648 | char *p; |
c67a084a NC |
18649 | int bytes, size, excess; |
18650 | valueT opcode; | |
742a56fe | 18651 | |
0a9ef439 RH |
18652 | if (fragp->fr_type != rs_align_code) |
18653 | return; | |
18654 | ||
742a56fe | 18655 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18656 | nop_opcode = *p; |
18657 | switch (nop_opcode) | |
a19d8eb0 | 18658 | { |
df58fc94 RS |
18659 | case NOP_OPCODE_MICROMIPS: |
18660 | opcode = micromips_nop32_insn.insn_opcode; | |
18661 | size = 4; | |
18662 | break; | |
18663 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
18664 | opcode = mips16_nop_insn.insn_opcode; |
18665 | size = 2; | |
df58fc94 RS |
18666 | break; |
18667 | case NOP_OPCODE_MIPS: | |
18668 | default: | |
c67a084a NC |
18669 | opcode = nop_insn.insn_opcode; |
18670 | size = 4; | |
df58fc94 | 18671 | break; |
c67a084a | 18672 | } |
a19d8eb0 | 18673 | |
c67a084a NC |
18674 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
18675 | excess = bytes % size; | |
df58fc94 RS |
18676 | |
18677 | /* Handle the leading part if we're not inserting a whole number of | |
18678 | instructions, and make it the end of the fixed part of the frag. | |
18679 | Try to fit in a short microMIPS NOP if applicable and possible, | |
18680 | and use zeroes otherwise. */ | |
18681 | gas_assert (excess < 4); | |
18682 | fragp->fr_fix += excess; | |
18683 | switch (excess) | |
c67a084a | 18684 | { |
df58fc94 RS |
18685 | case 3: |
18686 | *p++ = '\0'; | |
18687 | /* Fall through. */ | |
18688 | case 2: | |
18689 | if (nop_opcode == NOP_OPCODE_MICROMIPS) | |
18690 | { | |
4d68580a | 18691 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
18692 | break; |
18693 | } | |
18694 | *p++ = '\0'; | |
18695 | /* Fall through. */ | |
18696 | case 1: | |
18697 | *p++ = '\0'; | |
18698 | /* Fall through. */ | |
18699 | case 0: | |
18700 | break; | |
a19d8eb0 | 18701 | } |
c67a084a NC |
18702 | |
18703 | md_number_to_chars (p, opcode, size); | |
18704 | fragp->fr_var = size; | |
a19d8eb0 CP |
18705 | } |
18706 | ||
252b5132 | 18707 | static void |
17a2f251 | 18708 | md_obj_begin (void) |
252b5132 RH |
18709 | { |
18710 | } | |
18711 | ||
18712 | static void | |
17a2f251 | 18713 | md_obj_end (void) |
252b5132 | 18714 | { |
54f4ddb3 | 18715 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 18716 | if (cur_proc_ptr) |
9a41af64 | 18717 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
18718 | } |
18719 | ||
18720 | static long | |
17a2f251 | 18721 | get_number (void) |
252b5132 RH |
18722 | { |
18723 | int negative = 0; | |
18724 | long val = 0; | |
18725 | ||
18726 | if (*input_line_pointer == '-') | |
18727 | { | |
18728 | ++input_line_pointer; | |
18729 | negative = 1; | |
18730 | } | |
3882b010 | 18731 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 18732 | as_bad (_("expected simple number")); |
252b5132 RH |
18733 | if (input_line_pointer[0] == '0') |
18734 | { | |
18735 | if (input_line_pointer[1] == 'x') | |
18736 | { | |
18737 | input_line_pointer += 2; | |
3882b010 | 18738 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
18739 | { |
18740 | val <<= 4; | |
18741 | val |= hex_value (*input_line_pointer++); | |
18742 | } | |
18743 | return negative ? -val : val; | |
18744 | } | |
18745 | else | |
18746 | { | |
18747 | ++input_line_pointer; | |
3882b010 | 18748 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18749 | { |
18750 | val <<= 3; | |
18751 | val |= *input_line_pointer++ - '0'; | |
18752 | } | |
18753 | return negative ? -val : val; | |
18754 | } | |
18755 | } | |
3882b010 | 18756 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18757 | { |
18758 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
18759 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 18760 | as_warn (_("invalid number")); |
252b5132 RH |
18761 | return -1; |
18762 | } | |
3882b010 | 18763 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18764 | { |
18765 | val *= 10; | |
18766 | val += *input_line_pointer++ - '0'; | |
18767 | } | |
18768 | return negative ? -val : val; | |
18769 | } | |
18770 | ||
18771 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
18772 | is an initial number which is the ECOFF file index. In the non-ECOFF |
18773 | case .file implies DWARF-2. */ | |
18774 | ||
18775 | static void | |
17a2f251 | 18776 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 18777 | { |
ecb4347a DJ |
18778 | static int first_file_directive = 0; |
18779 | ||
c5dd6aab DJ |
18780 | if (ECOFF_DEBUGGING) |
18781 | { | |
18782 | get_number (); | |
18783 | s_app_file (0); | |
18784 | } | |
18785 | else | |
ecb4347a DJ |
18786 | { |
18787 | char *filename; | |
18788 | ||
18789 | filename = dwarf2_directive_file (0); | |
18790 | ||
18791 | /* Versions of GCC up to 3.1 start files with a ".file" | |
18792 | directive even for stabs output. Make sure that this | |
18793 | ".file" is handled. Note that you need a version of GCC | |
18794 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
18795 | if (filename != NULL && ! first_file_directive) | |
18796 | { | |
18797 | (void) new_logical_line (filename, -1); | |
c04f5787 | 18798 | s_app_file_string (filename, 0); |
ecb4347a DJ |
18799 | } |
18800 | first_file_directive = 1; | |
18801 | } | |
c5dd6aab DJ |
18802 | } |
18803 | ||
18804 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
18805 | |
18806 | static void | |
17a2f251 | 18807 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 18808 | { |
c5dd6aab DJ |
18809 | if (!ECOFF_DEBUGGING) |
18810 | dwarf2_directive_loc (0); | |
252b5132 RH |
18811 | } |
18812 | ||
252b5132 RH |
18813 | /* The .end directive. */ |
18814 | ||
18815 | static void | |
17a2f251 | 18816 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
18817 | { |
18818 | symbolS *p; | |
252b5132 | 18819 | |
7a621144 DJ |
18820 | /* Following functions need their own .frame and .cprestore directives. */ |
18821 | mips_frame_reg_valid = 0; | |
18822 | mips_cprestore_valid = 0; | |
18823 | ||
252b5132 RH |
18824 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
18825 | { | |
18826 | p = get_symbol (); | |
18827 | demand_empty_rest_of_line (); | |
18828 | } | |
18829 | else | |
18830 | p = NULL; | |
18831 | ||
14949570 | 18832 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
18833 | as_warn (_(".end not in text section")); |
18834 | ||
18835 | if (!cur_proc_ptr) | |
18836 | { | |
18837 | as_warn (_(".end directive without a preceding .ent directive.")); | |
18838 | demand_empty_rest_of_line (); | |
18839 | return; | |
18840 | } | |
18841 | ||
18842 | if (p != NULL) | |
18843 | { | |
9c2799c2 | 18844 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 18845 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 18846 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
18847 | |
18848 | if (debug_type == DEBUG_STABS) | |
18849 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
18850 | S_GET_NAME (p)); | |
252b5132 RH |
18851 | } |
18852 | else | |
18853 | as_warn (_(".end directive missing or unknown symbol")); | |
18854 | ||
2132e3a3 | 18855 | #ifdef OBJ_ELF |
9b2f1d35 EC |
18856 | /* Create an expression to calculate the size of the function. */ |
18857 | if (p && cur_proc_ptr) | |
18858 | { | |
18859 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
18860 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
18861 | ||
18862 | obj->size = exp; | |
18863 | exp->X_op = O_subtract; | |
18864 | exp->X_add_symbol = symbol_temp_new_now (); | |
18865 | exp->X_op_symbol = p; | |
18866 | exp->X_add_number = 0; | |
18867 | ||
18868 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
18869 | } | |
18870 | ||
ecb4347a | 18871 | /* Generate a .pdr section. */ |
f43abd2b | 18872 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
18873 | { |
18874 | segT saved_seg = now_seg; | |
18875 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
18876 | expressionS exp; |
18877 | char *fragp; | |
252b5132 | 18878 | |
252b5132 | 18879 | #ifdef md_flush_pending_output |
ecb4347a | 18880 | md_flush_pending_output (); |
252b5132 RH |
18881 | #endif |
18882 | ||
9c2799c2 | 18883 | gas_assert (pdr_seg); |
ecb4347a | 18884 | subseg_set (pdr_seg, 0); |
252b5132 | 18885 | |
ecb4347a DJ |
18886 | /* Write the symbol. */ |
18887 | exp.X_op = O_symbol; | |
18888 | exp.X_add_symbol = p; | |
18889 | exp.X_add_number = 0; | |
18890 | emit_expr (&exp, 4); | |
252b5132 | 18891 | |
ecb4347a | 18892 | fragp = frag_more (7 * 4); |
252b5132 | 18893 | |
17a2f251 TS |
18894 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
18895 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
18896 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
18897 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
18898 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
18899 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
18900 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 18901 | |
ecb4347a DJ |
18902 | subseg_set (saved_seg, saved_subseg); |
18903 | } | |
18904 | #endif /* OBJ_ELF */ | |
252b5132 RH |
18905 | |
18906 | cur_proc_ptr = NULL; | |
18907 | } | |
18908 | ||
18909 | /* The .aent and .ent directives. */ | |
18910 | ||
18911 | static void | |
17a2f251 | 18912 | s_mips_ent (int aent) |
252b5132 | 18913 | { |
252b5132 | 18914 | symbolS *symbolP; |
252b5132 RH |
18915 | |
18916 | symbolP = get_symbol (); | |
18917 | if (*input_line_pointer == ',') | |
f9419b05 | 18918 | ++input_line_pointer; |
252b5132 | 18919 | SKIP_WHITESPACE (); |
3882b010 | 18920 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 18921 | || *input_line_pointer == '-') |
874e8986 | 18922 | get_number (); |
252b5132 | 18923 | |
14949570 | 18924 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
18925 | as_warn (_(".ent or .aent not in text section.")); |
18926 | ||
18927 | if (!aent && cur_proc_ptr) | |
9a41af64 | 18928 | as_warn (_("missing .end")); |
252b5132 RH |
18929 | |
18930 | if (!aent) | |
18931 | { | |
7a621144 DJ |
18932 | /* This function needs its own .frame and .cprestore directives. */ |
18933 | mips_frame_reg_valid = 0; | |
18934 | mips_cprestore_valid = 0; | |
18935 | ||
252b5132 RH |
18936 | cur_proc_ptr = &cur_proc; |
18937 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
18938 | ||
9b2f1d35 | 18939 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 18940 | |
f9419b05 | 18941 | ++numprocs; |
ecb4347a DJ |
18942 | |
18943 | if (debug_type == DEBUG_STABS) | |
18944 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
18945 | S_GET_NAME (symbolP)); | |
252b5132 RH |
18946 | } |
18947 | ||
7c0fc524 MR |
18948 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
18949 | ||
252b5132 RH |
18950 | demand_empty_rest_of_line (); |
18951 | } | |
18952 | ||
18953 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 18954 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 18955 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 18956 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
18957 | symbol table (in the mdebug section). */ |
18958 | ||
18959 | static void | |
17a2f251 | 18960 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 18961 | { |
ecb4347a | 18962 | #ifdef OBJ_ELF |
f43abd2b | 18963 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
18964 | { |
18965 | long val; | |
252b5132 | 18966 | |
ecb4347a DJ |
18967 | if (cur_proc_ptr == (procS *) NULL) |
18968 | { | |
18969 | as_warn (_(".frame outside of .ent")); | |
18970 | demand_empty_rest_of_line (); | |
18971 | return; | |
18972 | } | |
252b5132 | 18973 | |
ecb4347a DJ |
18974 | cur_proc_ptr->frame_reg = tc_get_register (1); |
18975 | ||
18976 | SKIP_WHITESPACE (); | |
18977 | if (*input_line_pointer++ != ',' | |
18978 | || get_absolute_expression_and_terminator (&val) != ',') | |
18979 | { | |
18980 | as_warn (_("Bad .frame directive")); | |
18981 | --input_line_pointer; | |
18982 | demand_empty_rest_of_line (); | |
18983 | return; | |
18984 | } | |
252b5132 | 18985 | |
ecb4347a DJ |
18986 | cur_proc_ptr->frame_offset = val; |
18987 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 18988 | |
252b5132 | 18989 | demand_empty_rest_of_line (); |
252b5132 | 18990 | } |
ecb4347a DJ |
18991 | else |
18992 | #endif /* OBJ_ELF */ | |
18993 | s_ignore (ignore); | |
252b5132 RH |
18994 | } |
18995 | ||
bdaaa2e1 KH |
18996 | /* The .fmask and .mask directives. If the mdebug section is present |
18997 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 18998 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 18999 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
19000 | make reference to the ecoff symbol table (in the mdebug section). */ |
19001 | ||
19002 | static void | |
17a2f251 | 19003 | s_mips_mask (int reg_type) |
252b5132 | 19004 | { |
ecb4347a | 19005 | #ifdef OBJ_ELF |
f43abd2b | 19006 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 19007 | { |
ecb4347a | 19008 | long mask, off; |
252b5132 | 19009 | |
ecb4347a DJ |
19010 | if (cur_proc_ptr == (procS *) NULL) |
19011 | { | |
19012 | as_warn (_(".mask/.fmask outside of .ent")); | |
19013 | demand_empty_rest_of_line (); | |
19014 | return; | |
19015 | } | |
252b5132 | 19016 | |
ecb4347a DJ |
19017 | if (get_absolute_expression_and_terminator (&mask) != ',') |
19018 | { | |
19019 | as_warn (_("Bad .mask/.fmask directive")); | |
19020 | --input_line_pointer; | |
19021 | demand_empty_rest_of_line (); | |
19022 | return; | |
19023 | } | |
252b5132 | 19024 | |
ecb4347a DJ |
19025 | off = get_absolute_expression (); |
19026 | ||
19027 | if (reg_type == 'F') | |
19028 | { | |
19029 | cur_proc_ptr->fpreg_mask = mask; | |
19030 | cur_proc_ptr->fpreg_offset = off; | |
19031 | } | |
19032 | else | |
19033 | { | |
19034 | cur_proc_ptr->reg_mask = mask; | |
19035 | cur_proc_ptr->reg_offset = off; | |
19036 | } | |
19037 | ||
19038 | demand_empty_rest_of_line (); | |
252b5132 RH |
19039 | } |
19040 | else | |
ecb4347a DJ |
19041 | #endif /* OBJ_ELF */ |
19042 | s_ignore (reg_type); | |
252b5132 RH |
19043 | } |
19044 | ||
316f5878 RS |
19045 | /* A table describing all the processors gas knows about. Names are |
19046 | matched in the order listed. | |
e7af610e | 19047 | |
316f5878 RS |
19048 | To ease comparison, please keep this table in the same order as |
19049 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
19050 | static const struct mips_cpu_info mips_cpu_info_table[] = |
19051 | { | |
316f5878 | 19052 | /* Entries for generic ISAs */ |
ad3fea08 TS |
19053 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
19054 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
19055 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
19056 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
19057 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
19058 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
19059 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19060 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
19061 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
19062 | |
19063 | /* MIPS I */ | |
ad3fea08 TS |
19064 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
19065 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
19066 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
19067 | |
19068 | /* MIPS II */ | |
ad3fea08 | 19069 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
19070 | |
19071 | /* MIPS III */ | |
ad3fea08 TS |
19072 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
19073 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
19074 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
19075 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
19076 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
19077 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
19078 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
19079 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
19080 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
19081 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
19082 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
19083 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
b15591bb AN |
19084 | /* ST Microelectronics Loongson 2E and 2F cores */ |
19085 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
19086 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
19087 | |
19088 | /* MIPS IV */ | |
ad3fea08 TS |
19089 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
19090 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
19091 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
3aa3176b TS |
19092 | { "r14000", 0, ISA_MIPS4, CPU_R14000 }, |
19093 | { "r16000", 0, ISA_MIPS4, CPU_R16000 }, | |
ad3fea08 TS |
19094 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
19095 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
19096 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
19097 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
19098 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
19099 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
19100 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
19101 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
19102 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
19103 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
19104 | |
19105 | /* MIPS 32 */ | |
ad3fea08 TS |
19106 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
19107 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
19108 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
19109 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
19110 | ||
19111 | /* MIPS 32 Release 2 */ | |
19112 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19113 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19114 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19115 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19116 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19117 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
b5503c7b MR |
19118 | { "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19119 | { "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
7a795ef4 MR |
19120 | { "m14ke", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU, |
19121 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19122 | { "m14kec", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU, | |
19123 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 19124 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 19125 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 19126 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
19127 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19128 | /* Deprecated forms of the above. */ | |
19129 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 19130 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19131 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 19132 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 19133 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 19134 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
19135 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19136 | /* Deprecated forms of the above. */ | |
19137 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 19138 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19139 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
19140 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19141 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19142 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19143 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
19144 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19145 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19146 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19147 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19148 | /* Deprecated forms of the above. */ | |
19149 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19150 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
19151 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19152 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 SL |
19153 | /* 34Kn is a 34kc without DSP. */ |
19154 | { "34kn", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19155 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
19156 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19157 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19158 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19159 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19160 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19161 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19162 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19163 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19164 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19165 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19166 | /* Deprecated forms of the above. */ | |
19167 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19168 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19169 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19170 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a SL |
19171 | /* 1004K cores are multiprocessor versions of the 34K. */ |
19172 | { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19173 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19174 | { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19175 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19176 | { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19177 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19178 | { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19179 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 19180 | |
316f5878 | 19181 | /* MIPS 64 */ |
ad3fea08 TS |
19182 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
19183 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
19184 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 19185 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 | 19186 | |
c7a23324 | 19187 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
19188 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
19189 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
19190 | /* Broadcom SB-1A CPU core */ |
19191 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
19192 | ISA_MIPS64, CPU_SB1 }, | |
d051516a NC |
19193 | |
19194 | { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A }, | |
e7af610e | 19195 | |
ed163775 MR |
19196 | /* MIPS 64 Release 2 */ |
19197 | ||
967344c6 AN |
19198 | /* Cavium Networks Octeon CPU core */ |
19199 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
dd6a37e7 | 19200 | { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP }, |
432233b3 | 19201 | { "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 }, |
967344c6 | 19202 | |
52b6b6b9 JM |
19203 | /* RMI Xlr */ |
19204 | { "xlr", 0, ISA_MIPS64, CPU_XLR }, | |
19205 | ||
55a36193 MK |
19206 | /* Broadcom XLP. |
19207 | XLP is mostly like XLR, with the prominent exception that it is | |
19208 | MIPS64R2 rather than MIPS64. */ | |
19209 | { "xlp", 0, ISA_MIPS64R2, CPU_XLR }, | |
19210 | ||
316f5878 RS |
19211 | /* End marker */ |
19212 | { NULL, 0, 0, 0 } | |
19213 | }; | |
e7af610e | 19214 | |
84ea6cf2 | 19215 | |
316f5878 RS |
19216 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
19217 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 19218 | |
316f5878 | 19219 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 19220 | |
b34976b6 | 19221 | static bfd_boolean |
17a2f251 | 19222 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19223 | { |
19224 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
19225 | given++, canonical++; | |
19226 | ||
19227 | return ((*given == 0 && *canonical == 0) | |
19228 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
19229 | } | |
19230 | ||
19231 | ||
19232 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
19233 | CPU name. We've traditionally allowed a lot of variation here. | |
19234 | ||
19235 | Note: this function is shared between GCC and GAS. */ | |
19236 | ||
b34976b6 | 19237 | static bfd_boolean |
17a2f251 | 19238 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19239 | { |
19240 | /* First see if the name matches exactly, or with a final "000" | |
19241 | turned into "k". */ | |
19242 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 19243 | return TRUE; |
316f5878 RS |
19244 | |
19245 | /* If not, try comparing based on numerical designation alone. | |
19246 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
19247 | if (TOLOWER (*given) == 'r') | |
19248 | given++; | |
19249 | if (!ISDIGIT (*given)) | |
b34976b6 | 19250 | return FALSE; |
316f5878 RS |
19251 | |
19252 | /* Skip over some well-known prefixes in the canonical name, | |
19253 | hoping to find a number there too. */ | |
19254 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19255 | canonical += 2; | |
19256 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19257 | canonical += 2; | |
19258 | else if (TOLOWER (canonical[0]) == 'r') | |
19259 | canonical += 1; | |
19260 | ||
19261 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19262 | } | |
19263 | ||
19264 | ||
19265 | /* Parse an option that takes the name of a processor as its argument. | |
19266 | OPTION is the name of the option and CPU_STRING is the argument. | |
19267 | Return the corresponding processor enumeration if the CPU_STRING is | |
19268 | recognized, otherwise report an error and return null. | |
19269 | ||
19270 | A similar function exists in GCC. */ | |
e7af610e NC |
19271 | |
19272 | static const struct mips_cpu_info * | |
17a2f251 | 19273 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19274 | { |
316f5878 | 19275 | const struct mips_cpu_info *p; |
e7af610e | 19276 | |
316f5878 RS |
19277 | /* 'from-abi' selects the most compatible architecture for the given |
19278 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19279 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19280 | version. Look first at the -mgp options, if given, otherwise base | |
19281 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19282 | |
316f5878 RS |
19283 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19284 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19285 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19286 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19287 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19288 | { | |
19289 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19290 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19291 | ||
19292 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19293 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19294 | ||
19295 | if (file_mips_gp32 >= 0) | |
19296 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
19297 | ||
19298 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19299 | ? ISA_MIPS3 | |
19300 | : ISA_MIPS1); | |
19301 | } | |
19302 | ||
19303 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19304 | if (strcasecmp (cpu_string, "default") == 0) | |
19305 | return 0; | |
19306 | ||
19307 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19308 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19309 | return p; | |
19310 | ||
20203fb9 | 19311 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19312 | return 0; |
e7af610e NC |
19313 | } |
19314 | ||
316f5878 RS |
19315 | /* Return the canonical processor information for ISA (a member of the |
19316 | ISA_MIPS* enumeration). */ | |
19317 | ||
e7af610e | 19318 | static const struct mips_cpu_info * |
17a2f251 | 19319 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19320 | { |
19321 | int i; | |
19322 | ||
19323 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19324 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19325 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19326 | return (&mips_cpu_info_table[i]); |
19327 | ||
e972090a | 19328 | return NULL; |
e7af610e | 19329 | } |
fef14a42 TS |
19330 | |
19331 | static const struct mips_cpu_info * | |
17a2f251 | 19332 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19333 | { |
19334 | int i; | |
19335 | ||
19336 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19337 | if (arch == mips_cpu_info_table[i].cpu) | |
19338 | return (&mips_cpu_info_table[i]); | |
19339 | ||
19340 | return NULL; | |
19341 | } | |
316f5878 RS |
19342 | \f |
19343 | static void | |
17a2f251 | 19344 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19345 | { |
19346 | if (*first_p) | |
19347 | { | |
19348 | fprintf (stream, "%24s", ""); | |
19349 | *col_p = 24; | |
19350 | } | |
19351 | else | |
19352 | { | |
19353 | fprintf (stream, ", "); | |
19354 | *col_p += 2; | |
19355 | } | |
e7af610e | 19356 | |
316f5878 RS |
19357 | if (*col_p + strlen (string) > 72) |
19358 | { | |
19359 | fprintf (stream, "\n%24s", ""); | |
19360 | *col_p = 24; | |
19361 | } | |
19362 | ||
19363 | fprintf (stream, "%s", string); | |
19364 | *col_p += strlen (string); | |
19365 | ||
19366 | *first_p = 0; | |
19367 | } | |
19368 | ||
19369 | void | |
17a2f251 | 19370 | md_show_usage (FILE *stream) |
e7af610e | 19371 | { |
316f5878 RS |
19372 | int column, first; |
19373 | size_t i; | |
19374 | ||
19375 | fprintf (stream, _("\ | |
19376 | MIPS options:\n\ | |
316f5878 RS |
19377 | -EB generate big endian output\n\ |
19378 | -EL generate little endian output\n\ | |
19379 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19380 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19381 | implicitly with the gp register [default 8]\n")); | |
19382 | fprintf (stream, _("\ | |
19383 | -mips1 generate MIPS ISA I instructions\n\ | |
19384 | -mips2 generate MIPS ISA II instructions\n\ | |
19385 | -mips3 generate MIPS ISA III instructions\n\ | |
19386 | -mips4 generate MIPS ISA IV instructions\n\ | |
19387 | -mips5 generate MIPS ISA V instructions\n\ | |
19388 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19389 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 19390 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19391 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
19392 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19393 | ||
19394 | first = 1; | |
e7af610e NC |
19395 | |
19396 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
19397 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
19398 | show (stream, "from-abi", &column, &first); | |
19399 | fputc ('\n', stream); | |
e7af610e | 19400 | |
316f5878 RS |
19401 | fprintf (stream, _("\ |
19402 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
19403 | -no-mCPU don't generate code specific to CPU.\n\ | |
19404 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
19405 | ||
19406 | first = 1; | |
19407 | ||
19408 | show (stream, "3900", &column, &first); | |
19409 | show (stream, "4010", &column, &first); | |
19410 | show (stream, "4100", &column, &first); | |
19411 | show (stream, "4650", &column, &first); | |
19412 | fputc ('\n', stream); | |
19413 | ||
19414 | fprintf (stream, _("\ | |
19415 | -mips16 generate mips16 instructions\n\ | |
19416 | -no-mips16 do not generate mips16 instructions\n")); | |
19417 | fprintf (stream, _("\ | |
df58fc94 RS |
19418 | -mmicromips generate microMIPS instructions\n\ |
19419 | -mno-micromips do not generate microMIPS instructions\n")); | |
19420 | fprintf (stream, _("\ | |
e16bfa71 TS |
19421 | -msmartmips generate smartmips instructions\n\ |
19422 | -mno-smartmips do not generate smartmips instructions\n")); | |
19423 | fprintf (stream, _("\ | |
74cd071d CF |
19424 | -mdsp generate DSP instructions\n\ |
19425 | -mno-dsp do not generate DSP instructions\n")); | |
19426 | fprintf (stream, _("\ | |
8b082fb1 TS |
19427 | -mdspr2 generate DSP R2 instructions\n\ |
19428 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
19429 | fprintf (stream, _("\ | |
ef2e4d86 CF |
19430 | -mmt generate MT instructions\n\ |
19431 | -mno-mt do not generate MT instructions\n")); | |
19432 | fprintf (stream, _("\ | |
dec0624d MR |
19433 | -mmcu generate MCU instructions\n\ |
19434 | -mno-mcu do not generate MCU instructions\n")); | |
19435 | fprintf (stream, _("\ | |
c67a084a NC |
19436 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
19437 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 19438 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 19439 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 19440 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 19441 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
19442 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
19443 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 19444 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
19445 | -O0 remove unneeded NOPs, do not swap branches\n\ |
19446 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
19447 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
19448 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
19449 | fprintf (stream, _("\ |
19450 | -mhard-float allow floating-point instructions\n\ | |
19451 | -msoft-float do not allow floating-point instructions\n\ | |
19452 | -msingle-float only allow 32-bit floating-point operations\n\ | |
19453 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
19454 | --[no-]construct-floats [dis]allow floating point values to be constructed\n" | |
19455 | )); | |
316f5878 RS |
19456 | #ifdef OBJ_ELF |
19457 | fprintf (stream, _("\ | |
19458 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 19459 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 19460 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 19461 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 19462 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 19463 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 19464 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 19465 | position dependent (non shared) code\n\ |
316f5878 RS |
19466 | -mabi=ABI create ABI conformant object file for:\n")); |
19467 | ||
19468 | first = 1; | |
19469 | ||
19470 | show (stream, "32", &column, &first); | |
19471 | show (stream, "o64", &column, &first); | |
19472 | show (stream, "n32", &column, &first); | |
19473 | show (stream, "64", &column, &first); | |
19474 | show (stream, "eabi", &column, &first); | |
19475 | ||
19476 | fputc ('\n', stream); | |
19477 | ||
19478 | fprintf (stream, _("\ | |
19479 | -32 create o32 ABI object file (default)\n\ | |
19480 | -n32 create n32 ABI object file\n\ | |
19481 | -64 create 64 ABI object file\n")); | |
19482 | #endif | |
e7af610e | 19483 | } |
14e777e0 | 19484 | |
1575952e | 19485 | #ifdef TE_IRIX |
14e777e0 | 19486 | enum dwarf2_format |
413a266c | 19487 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 19488 | { |
369943fe | 19489 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 19490 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
19491 | else |
19492 | return dwarf2_format_32bit; | |
19493 | } | |
1575952e | 19494 | #endif |
73369e65 EC |
19495 | |
19496 | int | |
19497 | mips_dwarf2_addr_size (void) | |
19498 | { | |
6b6b3450 | 19499 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 19500 | return 8; |
73369e65 EC |
19501 | else |
19502 | return 4; | |
19503 | } | |
5862107c EC |
19504 | |
19505 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
19506 | void | |
19507 | mips_cfi_frame_initial_instructions (void) | |
19508 | { | |
19509 | cfi_add_CFA_def_cfa_register (SP); | |
19510 | } | |
19511 | ||
707bfff6 TS |
19512 | int |
19513 | tc_mips_regname_to_dw2regnum (char *regname) | |
19514 | { | |
19515 | unsigned int regnum = -1; | |
19516 | unsigned int reg; | |
19517 | ||
19518 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
19519 | regnum = reg; | |
19520 | ||
19521 | return regnum; | |
19522 | } |