Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
98d3f06f | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 |
82efde3a | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 RH |
30 | |
31 | #ifdef USE_STDARG | |
32 | #include <stdarg.h> | |
33 | #endif | |
34 | #ifdef USE_VARARGS | |
35 | #include <varargs.h> | |
36 | #endif | |
37 | ||
38 | #include "opcode/mips.h" | |
39 | #include "itbl-ops.h" | |
c5dd6aab | 40 | #include "dwarf2dbg.h" |
252b5132 RH |
41 | |
42 | #ifdef DEBUG | |
43 | #define DBG(x) printf x | |
44 | #else | |
45 | #define DBG(x) | |
46 | #endif | |
47 | ||
48 | #ifdef OBJ_MAYBE_ELF | |
49 | /* Clean up namespace so we can include obj-elf.h too. */ | |
50 | static int mips_output_flavor PARAMS ((void)); | |
51 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
52 | #undef OBJ_PROCESS_STAB | |
53 | #undef OUTPUT_FLAVOR | |
54 | #undef S_GET_ALIGN | |
55 | #undef S_GET_SIZE | |
56 | #undef S_SET_ALIGN | |
57 | #undef S_SET_SIZE | |
252b5132 RH |
58 | #undef obj_frob_file |
59 | #undef obj_frob_file_after_relocs | |
60 | #undef obj_frob_symbol | |
61 | #undef obj_pop_insert | |
62 | #undef obj_sec_sym_ok_for_reloc | |
63 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
64 | ||
65 | #include "obj-elf.h" | |
66 | /* Fix any of them that we actually care about. */ | |
67 | #undef OUTPUT_FLAVOR | |
68 | #define OUTPUT_FLAVOR mips_output_flavor() | |
69 | #endif | |
70 | ||
71 | #if defined (OBJ_ELF) | |
72 | #include "elf/mips.h" | |
73 | #endif | |
74 | ||
75 | #ifndef ECOFF_DEBUGGING | |
76 | #define NO_ECOFF_DEBUGGING | |
77 | #define ECOFF_DEBUGGING 0 | |
78 | #endif | |
79 | ||
ecb4347a DJ |
80 | int mips_flag_mdebug = -1; |
81 | ||
252b5132 RH |
82 | #include "ecoff.h" |
83 | ||
84 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
85 | static char *mips_regmask_frag; | |
86 | #endif | |
87 | ||
85b51719 | 88 | #define ZERO 0 |
252b5132 RH |
89 | #define AT 1 |
90 | #define TREG 24 | |
91 | #define PIC_CALL_REG 25 | |
92 | #define KT0 26 | |
93 | #define KT1 27 | |
94 | #define GP 28 | |
95 | #define SP 29 | |
96 | #define FP 30 | |
97 | #define RA 31 | |
98 | ||
99 | #define ILLEGAL_REG (32) | |
100 | ||
101 | /* Allow override of standard little-endian ECOFF format. */ | |
102 | ||
103 | #ifndef ECOFF_LITTLE_FORMAT | |
104 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
105 | #endif | |
106 | ||
107 | extern int target_big_endian; | |
108 | ||
252b5132 RH |
109 | /* The name of the readonly data section. */ |
110 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ | |
111 | ? ".data" \ | |
112 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
113 | ? ".rdata" \ | |
056350c6 NC |
114 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
115 | ? ".rdata" \ | |
252b5132 RH |
116 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
117 | ? ".rodata" \ | |
118 | : (abort (), "")) | |
119 | ||
a325df1d TS |
120 | /* The ABI to use. */ |
121 | enum mips_abi_level | |
122 | { | |
123 | NO_ABI = 0, | |
124 | O32_ABI, | |
125 | O64_ABI, | |
126 | N32_ABI, | |
127 | N64_ABI, | |
128 | EABI_ABI | |
129 | }; | |
130 | ||
131 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 132 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 133 | |
252b5132 RH |
134 | /* This is the set of options which may be modified by the .set |
135 | pseudo-op. We use a struct so that .set push and .set pop are more | |
136 | reliable. */ | |
137 | ||
e972090a NC |
138 | struct mips_set_options |
139 | { | |
252b5132 RH |
140 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
141 | if it has not been initialized. Changed by `.set mipsN', and the | |
142 | -mipsN command line option, and the default CPU. */ | |
143 | int isa; | |
1f25f5d3 CD |
144 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
145 | if they have not been initialized. Changed by `.set <asename>', by | |
146 | command line options, and based on the default architecture. */ | |
147 | int ase_mips3d; | |
deec1734 | 148 | int ase_mdmx; |
252b5132 RH |
149 | /* Whether we are assembling for the mips16 processor. 0 if we are |
150 | not, 1 if we are, and -1 if the value has not been initialized. | |
151 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
152 | -nomips16 command line options, and the default CPU. */ | |
153 | int mips16; | |
154 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
155 | reorder' and `.set noreorder'. */ | |
156 | int noreorder; | |
157 | /* Non-zero if we should not permit the $at ($1) register to be used | |
158 | in instructions. Changed by `.set at' and `.set noat'. */ | |
159 | int noat; | |
160 | /* Non-zero if we should warn when a macro instruction expands into | |
161 | more than one machine instruction. Changed by `.set nomacro' and | |
162 | `.set macro'. */ | |
163 | int warn_about_macros; | |
164 | /* Non-zero if we should not move instructions. Changed by `.set | |
165 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
166 | int nomove; | |
167 | /* Non-zero if we should not optimize branches by moving the target | |
168 | of the branch into the delay slot. Actually, we don't perform | |
169 | this optimization anyhow. Changed by `.set bopt' and `.set | |
170 | nobopt'. */ | |
171 | int nobopt; | |
172 | /* Non-zero if we should not autoextend mips16 instructions. | |
173 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
174 | int noautoextend; | |
a325df1d TS |
175 | /* Restrict general purpose registers and floating point registers |
176 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
177 | is passed but can changed if the assembler code uses .set mipsN. */ | |
178 | int gp32; | |
179 | int fp32; | |
252b5132 RH |
180 | }; |
181 | ||
a325df1d | 182 | /* True if -mgp32 was passed. */ |
a8e8e863 | 183 | static int file_mips_gp32 = -1; |
a325df1d TS |
184 | |
185 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 186 | static int file_mips_fp32 = -1; |
a325df1d | 187 | |
252b5132 | 188 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 189 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 190 | -1 to indicate that they have not been initialized. */ |
252b5132 | 191 | |
e972090a NC |
192 | static struct mips_set_options mips_opts = |
193 | { | |
316f5878 | 194 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0 |
e7af610e | 195 | }; |
252b5132 RH |
196 | |
197 | /* These variables are filled in with the masks of registers used. | |
198 | The object format code reads them and puts them in the appropriate | |
199 | place. */ | |
200 | unsigned long mips_gprmask; | |
201 | unsigned long mips_cprmask[4]; | |
202 | ||
203 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 204 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 205 | |
a4672219 TS |
206 | /* True if -mips16 was passed or implied by arguments passed on the |
207 | command line (e.g., by -march). */ | |
208 | static int file_ase_mips16; | |
209 | ||
1f25f5d3 CD |
210 | /* True if -mips3d was passed or implied by arguments passed on the |
211 | command line (e.g., by -march). */ | |
212 | static int file_ase_mips3d; | |
213 | ||
deec1734 CD |
214 | /* True if -mdmx was passed or implied by arguments passed on the |
215 | command line (e.g., by -march). */ | |
216 | static int file_ase_mdmx; | |
217 | ||
ec68c924 EC |
218 | /* The argument of the -march= flag. The architecture we are assembling. */ |
219 | static int mips_arch = CPU_UNKNOWN; | |
316f5878 RS |
220 | static const char *mips_arch_string; |
221 | static const struct mips_cpu_info *mips_arch_info; | |
ec68c924 EC |
222 | |
223 | /* The argument of the -mtune= flag. The architecture for which we | |
224 | are optimizing. */ | |
225 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 RS |
226 | static const char *mips_tune_string; |
227 | static const struct mips_cpu_info *mips_tune_info; | |
ec68c924 | 228 | |
316f5878 | 229 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
230 | static int mips_32bitmode = 0; |
231 | ||
9ce8a5dd GRK |
232 | /* Some ISA's have delay slots for instructions which read or write |
233 | from a coprocessor (eg. mips1-mips3); some don't (eg mips4). | |
bdaaa2e1 | 234 | Return true if instructions marked INSN_LOAD_COPROC_DELAY, |
9ce8a5dd GRK |
235 | INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a |
236 | delay slot in this ISA. The uses of this macro assume that any | |
237 | ISA that has delay slots for one of these, has them for all. They | |
238 | also assume that ISAs which don't have delays for these insns, don't | |
bdaaa2e1 | 239 | have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */ |
9ce8a5dd | 240 | #define ISA_HAS_COPROC_DELAYS(ISA) ( \ |
e7af610e NC |
241 | (ISA) == ISA_MIPS1 \ |
242 | || (ISA) == ISA_MIPS2 \ | |
243 | || (ISA) == ISA_MIPS3 \ | |
9ce8a5dd GRK |
244 | ) |
245 | ||
316f5878 RS |
246 | /* True if the given ABI requires 32-bit registers. */ |
247 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
248 | ||
249 | /* Likewise 64-bit registers. */ | |
250 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
251 | ((ABI) == N32_ABI \ | |
252 | || (ABI) == N64_ABI \ | |
253 | || (ABI) == O64_ABI) | |
254 | ||
bdaaa2e1 | 255 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 256 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
257 | (ISA) == ISA_MIPS3 \ |
258 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 259 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 260 | || (ISA) == ISA_MIPS64 \ |
9ce8a5dd GRK |
261 | ) |
262 | ||
e013f690 | 263 | #define HAVE_32BIT_GPRS \ |
316f5878 | 264 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 265 | |
e013f690 | 266 | #define HAVE_32BIT_FPRS \ |
316f5878 | 267 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
268 | |
269 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
270 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
271 | ||
316f5878 | 272 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 273 | |
316f5878 | 274 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 TS |
275 | |
276 | /* We can only have 64bit addresses if the object file format | |
277 | supports it. */ | |
afdbd6d0 CD |
278 | #define HAVE_32BIT_ADDRESSES \ |
279 | (HAVE_32BIT_GPRS \ | |
280 | || ((bfd_arch_bits_per_address (stdoutput) == 32 \ | |
281 | || ! HAVE_64BIT_OBJECTS) \ | |
282 | && mips_pic != EMBEDDED_PIC)) | |
e013f690 TS |
283 | |
284 | #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) | |
ca4e0257 | 285 | |
a4672219 | 286 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
287 | #define CPU_HAS_MIPS16(cpu) \ |
288 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
289 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 290 | |
1f25f5d3 CD |
291 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
292 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
293 | ) | |
294 | ||
deec1734 | 295 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 296 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
297 | ) |
298 | ||
60b63b72 RS |
299 | /* True if CPU has a dror instruction. */ |
300 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
301 | ||
302 | /* True if CPU has a ror instruction. */ | |
303 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
304 | ||
bdaaa2e1 | 305 | /* Whether the processor uses hardware interlocks to protect |
252b5132 | 306 | reads from the HI and LO registers, and thus does not |
ec68c924 | 307 | require nops to be inserted. */ |
252b5132 | 308 | |
ec68c924 | 309 | #define hilo_interlocks (mips_arch == CPU_R4010 \ |
60b63b72 | 310 | || mips_arch == CPU_VR5500 \ |
0a758a12 | 311 | || mips_arch == CPU_SB1 \ |
252b5132 RH |
312 | ) |
313 | ||
314 | /* Whether the processor uses hardware interlocks to protect reads | |
315 | from the GPRs, and thus does not require nops to be inserted. */ | |
316 | #define gpr_interlocks \ | |
e7af610e | 317 | (mips_opts.isa != ISA_MIPS1 \ |
60b63b72 RS |
318 | || mips_arch == CPU_VR5400 \ |
319 | || mips_arch == CPU_VR5500 \ | |
ec68c924 | 320 | || mips_arch == CPU_R3900) |
252b5132 RH |
321 | |
322 | /* As with other "interlocks" this is used by hardware that has FP | |
323 | (co-processor) interlocks. */ | |
bdaaa2e1 | 324 | /* Itbl support may require additional care here. */ |
ec68c924 | 325 | #define cop_interlocks (mips_arch == CPU_R4300 \ |
60b63b72 RS |
326 | || mips_arch == CPU_VR5400 \ |
327 | || mips_arch == CPU_VR5500 \ | |
0a758a12 | 328 | || mips_arch == CPU_SB1 \ |
252b5132 RH |
329 | ) |
330 | ||
6b76fefe CM |
331 | /* Is this a mfhi or mflo instruction? */ |
332 | #define MF_HILO_INSN(PINFO) \ | |
333 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
334 | ||
252b5132 RH |
335 | /* MIPS PIC level. */ |
336 | ||
a161fe53 | 337 | enum mips_pic_level mips_pic; |
252b5132 | 338 | |
39c0a331 L |
339 | /* Warn about all NOPS that the assembler generates. */ |
340 | static int warn_nops = 0; | |
341 | ||
c9914766 | 342 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 343 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 344 | static int mips_big_got = 0; |
252b5132 RH |
345 | |
346 | /* 1 if trap instructions should used for overflow rather than break | |
347 | instructions. */ | |
c9914766 | 348 | static int mips_trap = 0; |
252b5132 | 349 | |
119d663a | 350 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 351 | by assembling two single width halves into two single width floating |
119d663a NC |
352 | point registers which just happen to alias the double width destination |
353 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 354 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
355 | automatically at assemble time. */ |
356 | static int mips_disable_float_construction; | |
357 | ||
252b5132 RH |
358 | /* Non-zero if any .set noreorder directives were used. */ |
359 | ||
360 | static int mips_any_noreorder; | |
361 | ||
6b76fefe CM |
362 | /* Non-zero if nops should be inserted when the register referenced in |
363 | an mfhi/mflo instruction is read in the next two instructions. */ | |
364 | static int mips_7000_hilo_fix; | |
365 | ||
252b5132 | 366 | /* The size of the small data section. */ |
156c2f8b | 367 | static unsigned int g_switch_value = 8; |
252b5132 RH |
368 | /* Whether the -G option was used. */ |
369 | static int g_switch_seen = 0; | |
370 | ||
371 | #define N_RMASK 0xc4 | |
372 | #define N_VFP 0xd4 | |
373 | ||
374 | /* If we can determine in advance that GP optimization won't be | |
375 | possible, we can skip the relaxation stuff that tries to produce | |
376 | GP-relative references. This makes delay slot optimization work | |
377 | better. | |
378 | ||
379 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
380 | gcc output. It needs to guess right for gcc, otherwise gcc |
381 | will put what it thinks is a GP-relative instruction in a branch | |
382 | delay slot. | |
252b5132 RH |
383 | |
384 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
385 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
386 | static int nopic_need_relax PARAMS ((symbolS *, int)); | |
387 | ||
388 | /* handle of the OPCODE hash table */ | |
389 | static struct hash_control *op_hash = NULL; | |
390 | ||
391 | /* The opcode hash table we use for the mips16. */ | |
392 | static struct hash_control *mips16_op_hash = NULL; | |
393 | ||
394 | /* This array holds the chars that always start a comment. If the | |
395 | pre-processor is disabled, these aren't very useful */ | |
396 | const char comment_chars[] = "#"; | |
397 | ||
398 | /* This array holds the chars that only start a comment at the beginning of | |
399 | a line. If the line seems to have the form '# 123 filename' | |
400 | .line and .file directives will appear in the pre-processed output */ | |
401 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
402 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 403 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
404 | /* Also note that C style comments are always supported. */ |
405 | const char line_comment_chars[] = "#"; | |
406 | ||
bdaaa2e1 | 407 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 408 | const char line_separator_chars[] = ";"; |
252b5132 RH |
409 | |
410 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
411 | const char EXP_CHARS[] = "eE"; | |
412 | ||
413 | /* Chars that mean this number is a floating point constant */ | |
414 | /* As in 0f12.456 */ | |
415 | /* or 0d1.2345e12 */ | |
416 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
417 | ||
418 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
419 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
420 | but nothing is ideal around here. | |
421 | */ | |
422 | ||
423 | static char *insn_error; | |
424 | ||
425 | static int auto_align = 1; | |
426 | ||
427 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
428 | offset in the stack frame from which to restore the $gp register. | |
429 | This is set by the .cprestore pseudo-op, and saved in this | |
430 | variable. */ | |
431 | static offsetT mips_cprestore_offset = -1; | |
432 | ||
6478892d TS |
433 | /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
434 | more optimizations, it can use a register value instead of a memory-saved | |
956cd1d6 | 435 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
436 | static offsetT mips_cpreturn_offset = -1; |
437 | static int mips_cpreturn_register = -1; | |
438 | static int mips_gp_register = GP; | |
def2e0dd | 439 | static int mips_gprel_offset = 0; |
6478892d | 440 | |
7a621144 DJ |
441 | /* Whether mips_cprestore_offset has been set in the current function |
442 | (or whether it has already been warned about, if not). */ | |
443 | static int mips_cprestore_valid = 0; | |
444 | ||
252b5132 RH |
445 | /* This is the register which holds the stack frame, as set by the |
446 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
447 | static int mips_frame_reg = SP; | |
448 | ||
7a621144 DJ |
449 | /* Whether mips_frame_reg has been set in the current function |
450 | (or whether it has already been warned about, if not). */ | |
451 | static int mips_frame_reg_valid = 0; | |
452 | ||
252b5132 RH |
453 | /* To output NOP instructions correctly, we need to keep information |
454 | about the previous two instructions. */ | |
455 | ||
456 | /* Whether we are optimizing. The default value of 2 means to remove | |
457 | unneeded NOPs and swap branch instructions when possible. A value | |
458 | of 1 means to not swap branches. A value of 0 means to always | |
459 | insert NOPs. */ | |
460 | static int mips_optimize = 2; | |
461 | ||
462 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
463 | equivalent to seeing no -g option at all. */ | |
464 | static int mips_debug = 0; | |
465 | ||
466 | /* The previous instruction. */ | |
467 | static struct mips_cl_insn prev_insn; | |
468 | ||
469 | /* The instruction before prev_insn. */ | |
470 | static struct mips_cl_insn prev_prev_insn; | |
471 | ||
472 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
473 | point the insn_mo field at this dummy integer. */ | |
43841e91 | 474 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
252b5132 RH |
475 | |
476 | /* Non-zero if prev_insn is valid. */ | |
477 | static int prev_insn_valid; | |
478 | ||
479 | /* The frag for the previous instruction. */ | |
480 | static struct frag *prev_insn_frag; | |
481 | ||
482 | /* The offset into prev_insn_frag for the previous instruction. */ | |
483 | static long prev_insn_where; | |
484 | ||
485 | /* The reloc type for the previous instruction, if any. */ | |
f6688943 | 486 | static bfd_reloc_code_real_type prev_insn_reloc_type[3]; |
252b5132 RH |
487 | |
488 | /* The reloc for the previous instruction, if any. */ | |
f6688943 | 489 | static fixS *prev_insn_fixp[3]; |
252b5132 RH |
490 | |
491 | /* Non-zero if the previous instruction was in a delay slot. */ | |
492 | static int prev_insn_is_delay_slot; | |
493 | ||
494 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
495 | static int prev_insn_unreordered; | |
496 | ||
497 | /* Non-zero if the previous instruction uses an extend opcode (if | |
498 | mips16). */ | |
499 | static int prev_insn_extended; | |
500 | ||
501 | /* Non-zero if the previous previous instruction was in a .set | |
502 | noreorder. */ | |
503 | static int prev_prev_insn_unreordered; | |
504 | ||
505 | /* If this is set, it points to a frag holding nop instructions which | |
506 | were inserted before the start of a noreorder section. If those | |
507 | nops turn out to be unnecessary, the size of the frag can be | |
508 | decreased. */ | |
509 | static fragS *prev_nop_frag; | |
510 | ||
511 | /* The number of nop instructions we created in prev_nop_frag. */ | |
512 | static int prev_nop_frag_holds; | |
513 | ||
514 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 515 | prev_nop_frag. */ |
252b5132 RH |
516 | static int prev_nop_frag_required; |
517 | ||
518 | /* The number of instructions we've seen since prev_nop_frag. */ | |
519 | static int prev_nop_frag_since; | |
520 | ||
521 | /* For ECOFF and ELF, relocations against symbols are done in two | |
522 | parts, with a HI relocation and a LO relocation. Each relocation | |
523 | has only 16 bits of space to store an addend. This means that in | |
524 | order for the linker to handle carries correctly, it must be able | |
525 | to locate both the HI and the LO relocation. This means that the | |
526 | relocations must appear in order in the relocation table. | |
527 | ||
528 | In order to implement this, we keep track of each unmatched HI | |
529 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 530 | corresponding LO relocation. */ |
252b5132 | 531 | |
e972090a NC |
532 | struct mips_hi_fixup |
533 | { | |
252b5132 RH |
534 | /* Next HI fixup. */ |
535 | struct mips_hi_fixup *next; | |
536 | /* This fixup. */ | |
537 | fixS *fixp; | |
538 | /* The section this fixup is in. */ | |
539 | segT seg; | |
540 | }; | |
541 | ||
542 | /* The list of unmatched HI relocs. */ | |
543 | ||
544 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
545 | ||
546 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
547 | ||
548 | #define X ILLEGAL_REG | |
e972090a NC |
549 | static const int mips32_to_16_reg_map[] = |
550 | { | |
252b5132 RH |
551 | X, X, 2, 3, 4, 5, 6, 7, |
552 | X, X, X, X, X, X, X, X, | |
553 | 0, 1, X, X, X, X, X, X, | |
554 | X, X, X, X, X, X, X, X | |
555 | }; | |
556 | #undef X | |
557 | ||
558 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
559 | ||
e972090a NC |
560 | static const unsigned int mips16_to_32_reg_map[] = |
561 | { | |
252b5132 RH |
562 | 16, 17, 2, 3, 4, 5, 6, 7 |
563 | }; | |
60b63b72 RS |
564 | |
565 | static int mips_fix_4122_bugs; | |
4a6a3df4 AO |
566 | |
567 | /* We don't relax branches by default, since this causes us to expand | |
568 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
569 | fail to compute the offset before expanding the macro to the most | |
570 | efficient expansion. */ | |
571 | ||
572 | static int mips_relax_branch; | |
252b5132 RH |
573 | \f |
574 | /* Since the MIPS does not have multiple forms of PC relative | |
575 | instructions, we do not have to do relaxing as is done on other | |
576 | platforms. However, we do have to handle GP relative addressing | |
577 | correctly, which turns out to be a similar problem. | |
578 | ||
579 | Every macro that refers to a symbol can occur in (at least) two | |
580 | forms, one with GP relative addressing and one without. For | |
581 | example, loading a global variable into a register generally uses | |
582 | a macro instruction like this: | |
583 | lw $4,i | |
584 | If i can be addressed off the GP register (this is true if it is in | |
585 | the .sbss or .sdata section, or if it is known to be smaller than | |
586 | the -G argument) this will generate the following instruction: | |
587 | lw $4,i($gp) | |
588 | This instruction will use a GPREL reloc. If i can not be addressed | |
589 | off the GP register, the following instruction sequence will be used: | |
590 | lui $at,i | |
591 | lw $4,i($at) | |
592 | In this case the first instruction will have a HI16 reloc, and the | |
593 | second reloc will have a LO16 reloc. Both relocs will be against | |
594 | the symbol i. | |
595 | ||
596 | The issue here is that we may not know whether i is GP addressable | |
597 | until after we see the instruction that uses it. Therefore, we | |
598 | want to be able to choose the final instruction sequence only at | |
599 | the end of the assembly. This is similar to the way other | |
600 | platforms choose the size of a PC relative instruction only at the | |
601 | end of assembly. | |
602 | ||
603 | When generating position independent code we do not use GP | |
604 | addressing in quite the same way, but the issue still arises as | |
605 | external symbols and local symbols must be handled differently. | |
606 | ||
607 | We handle these issues by actually generating both possible | |
608 | instruction sequences. The longer one is put in a frag_var with | |
609 | type rs_machine_dependent. We encode what to do with the frag in | |
610 | the subtype field. We encode (1) the number of existing bytes to | |
611 | replace, (2) the number of new bytes to use, (3) the offset from | |
612 | the start of the existing bytes to the first reloc we must generate | |
613 | (that is, the offset is applied from the start of the existing | |
614 | bytes after they are replaced by the new bytes, if any), (4) the | |
615 | offset from the start of the existing bytes to the second reloc, | |
616 | (5) whether a third reloc is needed (the third reloc is always four | |
617 | bytes after the second reloc), and (6) whether to warn if this | |
618 | variant is used (this is sometimes needed if .set nomacro or .set | |
619 | noat is in effect). All these numbers are reasonably small. | |
620 | ||
621 | Generating two instruction sequences must be handled carefully to | |
622 | ensure that delay slots are handled correctly. Fortunately, there | |
623 | are a limited number of cases. When the second instruction | |
624 | sequence is generated, append_insn is directed to maintain the | |
625 | existing delay slot information, so it continues to apply to any | |
626 | code after the second instruction sequence. This means that the | |
627 | second instruction sequence must not impose any requirements not | |
628 | required by the first instruction sequence. | |
629 | ||
630 | These variant frags are then handled in functions called by the | |
631 | machine independent code. md_estimate_size_before_relax returns | |
632 | the final size of the frag. md_convert_frag sets up the final form | |
633 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
634 | one if needed. */ | |
635 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
636 | ((relax_substateT) \ | |
637 | (((old) << 23) \ | |
638 | | ((new) << 16) \ | |
639 | | (((reloc1) + 64) << 9) \ | |
640 | | (((reloc2) + 64) << 2) \ | |
641 | | ((reloc3) ? (1 << 1) : 0) \ | |
642 | | ((warn) ? 1 : 0))) | |
643 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) | |
644 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
9a41af64 TS |
645 | #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64) |
646 | #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64) | |
252b5132 RH |
647 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
648 | #define RELAX_WARN(i) ((i) & 1) | |
649 | ||
4a6a3df4 AO |
650 | /* Branch without likely bit. If label is out of range, we turn: |
651 | ||
652 | beq reg1, reg2, label | |
653 | delay slot | |
654 | ||
655 | into | |
656 | ||
657 | bne reg1, reg2, 0f | |
658 | nop | |
659 | j label | |
660 | 0: delay slot | |
661 | ||
662 | with the following opcode replacements: | |
663 | ||
664 | beq <-> bne | |
665 | blez <-> bgtz | |
666 | bltz <-> bgez | |
667 | bc1f <-> bc1t | |
668 | ||
669 | bltzal <-> bgezal (with jal label instead of j label) | |
670 | ||
671 | Even though keeping the delay slot instruction in the delay slot of | |
672 | the branch would be more efficient, it would be very tricky to do | |
673 | correctly, because we'd have to introduce a variable frag *after* | |
674 | the delay slot instruction, and expand that instead. Let's do it | |
675 | the easy way for now, even if the branch-not-taken case now costs | |
676 | one additional instruction. Out-of-range branches are not supposed | |
677 | to be common, anyway. | |
678 | ||
679 | Branch likely. If label is out of range, we turn: | |
680 | ||
681 | beql reg1, reg2, label | |
682 | delay slot (annulled if branch not taken) | |
683 | ||
684 | into | |
685 | ||
686 | beql reg1, reg2, 1f | |
687 | nop | |
688 | beql $0, $0, 2f | |
689 | nop | |
690 | 1: j[al] label | |
691 | delay slot (executed only if branch taken) | |
692 | 2: | |
693 | ||
694 | It would be possible to generate a shorter sequence by losing the | |
695 | likely bit, generating something like: | |
b34976b6 | 696 | |
4a6a3df4 AO |
697 | bne reg1, reg2, 0f |
698 | nop | |
699 | j[al] label | |
700 | delay slot (executed only if branch taken) | |
701 | 0: | |
702 | ||
703 | beql -> bne | |
704 | bnel -> beq | |
705 | blezl -> bgtz | |
706 | bgtzl -> blez | |
707 | bltzl -> bgez | |
708 | bgezl -> bltz | |
709 | bc1fl -> bc1t | |
710 | bc1tl -> bc1f | |
711 | ||
712 | bltzall -> bgezal (with jal label instead of j label) | |
713 | bgezall -> bltzal (ditto) | |
714 | ||
715 | ||
716 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 717 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
718 | ((relax_substateT) \ |
719 | (0xc0000000 \ | |
720 | | ((toofar) ? 1 : 0) \ | |
721 | | ((link) ? 2 : 0) \ | |
722 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 723 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 724 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
725 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
726 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
727 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
728 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1)) | |
729 | ||
252b5132 RH |
730 | /* For mips16 code, we use an entirely different form of relaxation. |
731 | mips16 supports two versions of most instructions which take | |
732 | immediate values: a small one which takes some small value, and a | |
733 | larger one which takes a 16 bit value. Since branches also follow | |
734 | this pattern, relaxing these values is required. | |
735 | ||
736 | We can assemble both mips16 and normal MIPS code in a single | |
737 | object. Therefore, we need to support this type of relaxation at | |
738 | the same time that we support the relaxation described above. We | |
739 | use the high bit of the subtype field to distinguish these cases. | |
740 | ||
741 | The information we store for this type of relaxation is the | |
742 | argument code found in the opcode file for this relocation, whether | |
743 | the user explicitly requested a small or extended form, and whether | |
744 | the relocation is in a jump or jal delay slot. That tells us the | |
745 | size of the value, and how it should be stored. We also store | |
746 | whether the fragment is considered to be extended or not. We also | |
747 | store whether this is known to be a branch to a different section, | |
748 | whether we have tried to relax this frag yet, and whether we have | |
749 | ever extended a PC relative fragment because of a shift count. */ | |
750 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
751 | (0x80000000 \ | |
752 | | ((type) & 0xff) \ | |
753 | | ((small) ? 0x100 : 0) \ | |
754 | | ((ext) ? 0x200 : 0) \ | |
755 | | ((dslot) ? 0x400 : 0) \ | |
756 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 757 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
758 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
759 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
760 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
761 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
762 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
763 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
764 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
765 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
766 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
767 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
768 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
769 | |
770 | /* Is the given value a sign-extended 32-bit value? */ | |
771 | #define IS_SEXT_32BIT_NUM(x) \ | |
772 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
773 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
774 | ||
775 | /* Is the given value a sign-extended 16-bit value? */ | |
776 | #define IS_SEXT_16BIT_NUM(x) \ | |
777 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
778 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
779 | ||
252b5132 RH |
780 | \f |
781 | /* Prototypes for static functions. */ | |
782 | ||
783 | #ifdef __STDC__ | |
784 | #define internalError() \ | |
785 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) | |
786 | #else | |
787 | #define internalError() as_fatal (_("MIPS internal Error")); | |
788 | #endif | |
789 | ||
790 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
791 | ||
b34976b6 AM |
792 | static int insn_uses_reg |
793 | PARAMS ((struct mips_cl_insn *ip, unsigned int reg, | |
794 | enum mips_regclass class)); | |
795 | static int reg_needs_delay | |
796 | PARAMS ((unsigned int)); | |
797 | static void mips16_mark_labels | |
798 | PARAMS ((void)); | |
799 | static void append_insn | |
800 | PARAMS ((char *place, struct mips_cl_insn * ip, expressionS * p, | |
801 | bfd_reloc_code_real_type *r, bfd_boolean)); | |
802 | static void mips_no_prev_insn | |
803 | PARAMS ((int)); | |
804 | static void mips_emit_delays | |
805 | PARAMS ((bfd_boolean)); | |
252b5132 | 806 | #ifdef USE_STDARG |
b34976b6 AM |
807 | static void macro_build |
808 | PARAMS ((char *place, int *counter, expressionS * ep, const char *name, | |
809 | const char *fmt, ...)); | |
252b5132 RH |
810 | #else |
811 | static void macro_build (); | |
812 | #endif | |
b34976b6 AM |
813 | static void mips16_macro_build |
814 | PARAMS ((char *, int *, expressionS *, const char *, const char *, va_list)); | |
815 | static void macro_build_jalr | |
816 | PARAMS ((int, expressionS *)); | |
817 | static void macro_build_lui | |
818 | PARAMS ((char *place, int *counter, expressionS * ep, int regnum)); | |
819 | static void macro_build_ldst_constoffset | |
820 | PARAMS ((char *place, int *counter, expressionS * ep, const char *op, | |
821 | int valreg, int breg)); | |
822 | static void set_at | |
823 | PARAMS ((int *counter, int reg, int unsignedp)); | |
824 | static void check_absolute_expr | |
825 | PARAMS ((struct mips_cl_insn * ip, expressionS *)); | |
826 | static void load_register | |
827 | PARAMS ((int *, int, expressionS *, int)); | |
828 | static void load_address | |
829 | PARAMS ((int *, int, expressionS *, int *)); | |
830 | static void move_register | |
831 | PARAMS ((int *, int, int)); | |
832 | static void macro | |
833 | PARAMS ((struct mips_cl_insn * ip)); | |
834 | static void mips16_macro | |
835 | PARAMS ((struct mips_cl_insn * ip)); | |
252b5132 | 836 | #ifdef LOSING_COMPILER |
b34976b6 AM |
837 | static void macro2 |
838 | PARAMS ((struct mips_cl_insn * ip)); | |
252b5132 | 839 | #endif |
b34976b6 AM |
840 | static void mips_ip |
841 | PARAMS ((char *str, struct mips_cl_insn * ip)); | |
842 | static void mips16_ip | |
843 | PARAMS ((char *str, struct mips_cl_insn * ip)); | |
844 | static void mips16_immed | |
845 | PARAMS ((char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, | |
846 | bfd_boolean, unsigned long *, bfd_boolean *, unsigned short *)); | |
847 | static int my_getPercentOp | |
848 | PARAMS ((char **, unsigned int *, int *)); | |
849 | static int my_getSmallParser | |
850 | PARAMS ((char **, unsigned int *, int *)); | |
851 | static int my_getSmallExpression | |
852 | PARAMS ((expressionS *, char *)); | |
853 | static void my_getExpression | |
854 | PARAMS ((expressionS *, char *)); | |
ae948b86 | 855 | #ifdef OBJ_ELF |
b34976b6 AM |
856 | static int support_64bit_objects |
857 | PARAMS((void)); | |
ae948b86 | 858 | #endif |
b34976b6 AM |
859 | static void mips_set_option_string |
860 | PARAMS ((const char **, const char *)); | |
861 | static symbolS *get_symbol | |
862 | PARAMS ((void)); | |
863 | static void mips_align | |
864 | PARAMS ((int to, int fill, symbolS *label)); | |
865 | static void s_align | |
866 | PARAMS ((int)); | |
867 | static void s_change_sec | |
868 | PARAMS ((int)); | |
869 | static void s_change_section | |
870 | PARAMS ((int)); | |
871 | static void s_cons | |
872 | PARAMS ((int)); | |
873 | static void s_float_cons | |
874 | PARAMS ((int)); | |
875 | static void s_mips_globl | |
876 | PARAMS ((int)); | |
877 | static void s_option | |
878 | PARAMS ((int)); | |
879 | static void s_mipsset | |
880 | PARAMS ((int)); | |
881 | static void s_abicalls | |
882 | PARAMS ((int)); | |
883 | static void s_cpload | |
884 | PARAMS ((int)); | |
885 | static void s_cpsetup | |
886 | PARAMS ((int)); | |
887 | static void s_cplocal | |
888 | PARAMS ((int)); | |
889 | static void s_cprestore | |
890 | PARAMS ((int)); | |
891 | static void s_cpreturn | |
892 | PARAMS ((int)); | |
893 | static void s_gpvalue | |
894 | PARAMS ((int)); | |
895 | static void s_gpword | |
896 | PARAMS ((int)); | |
897 | static void s_gpdword | |
898 | PARAMS ((int)); | |
899 | static void s_cpadd | |
900 | PARAMS ((int)); | |
901 | static void s_insn | |
902 | PARAMS ((int)); | |
903 | static void md_obj_begin | |
904 | PARAMS ((void)); | |
905 | static void md_obj_end | |
906 | PARAMS ((void)); | |
907 | static long get_number | |
908 | PARAMS ((void)); | |
909 | static void s_mips_ent | |
910 | PARAMS ((int)); | |
911 | static void s_mips_end | |
912 | PARAMS ((int)); | |
913 | static void s_mips_frame | |
914 | PARAMS ((int)); | |
915 | static void s_mips_mask | |
916 | PARAMS ((int)); | |
917 | static void s_mips_stab | |
918 | PARAMS ((int)); | |
919 | static void s_mips_weakext | |
920 | PARAMS ((int)); | |
921 | static void s_mips_file | |
922 | PARAMS ((int)); | |
923 | static void s_mips_loc | |
924 | PARAMS ((int)); | |
925 | static int mips16_extended_frag | |
926 | PARAMS ((fragS *, asection *, long)); | |
4a6a3df4 | 927 | static int relaxed_branch_length (fragS *, asection *, int); |
b34976b6 AM |
928 | static int validate_mips_insn |
929 | PARAMS ((const struct mips_opcode *)); | |
930 | static void show | |
931 | PARAMS ((FILE *, const char *, int *, int *)); | |
add55e1f | 932 | #ifdef OBJ_ELF |
b34976b6 AM |
933 | static int mips_need_elf_addend_fixup |
934 | PARAMS ((fixS *)); | |
add55e1f | 935 | #endif |
e7af610e | 936 | |
ad8d3bb3 | 937 | /* Return values of my_getSmallExpression(). */ |
fb1b3232 | 938 | |
ad8d3bb3 | 939 | enum small_ex_type |
fb1b3232 TS |
940 | { |
941 | S_EX_NONE = 0, | |
ad8d3bb3 TS |
942 | S_EX_REGISTER, |
943 | ||
944 | /* Direct relocation creation by %percent_op(). */ | |
945 | S_EX_HALF, | |
fb1b3232 | 946 | S_EX_HI, |
ad8d3bb3 TS |
947 | S_EX_LO, |
948 | S_EX_GP_REL, | |
949 | S_EX_GOT, | |
950 | S_EX_CALL16, | |
951 | S_EX_GOT_DISP, | |
952 | S_EX_GOT_PAGE, | |
953 | S_EX_GOT_OFST, | |
954 | S_EX_GOT_HI, | |
955 | S_EX_GOT_LO, | |
956 | S_EX_NEG, | |
fb1b3232 TS |
957 | S_EX_HIGHER, |
958 | S_EX_HIGHEST, | |
ad8d3bb3 TS |
959 | S_EX_CALL_HI, |
960 | S_EX_CALL_LO | |
fb1b3232 TS |
961 | }; |
962 | ||
e7af610e NC |
963 | /* Table and functions used to map between CPU/ISA names, and |
964 | ISA levels, and CPU numbers. */ | |
965 | ||
e972090a NC |
966 | struct mips_cpu_info |
967 | { | |
e7af610e NC |
968 | const char *name; /* CPU or ISA name. */ |
969 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
970 | int isa; /* ISA level. */ | |
971 | int cpu; /* CPU number (default CPU if ISA). */ | |
972 | }; | |
973 | ||
b34976b6 AM |
974 | static void mips_set_architecture |
975 | PARAMS ((const struct mips_cpu_info *)); | |
976 | static void mips_set_tune | |
977 | PARAMS ((const struct mips_cpu_info *)); | |
978 | static bfd_boolean mips_strict_matching_cpu_name_p | |
979 | PARAMS ((const char *, const char *)); | |
980 | static bfd_boolean mips_matching_cpu_name_p | |
981 | PARAMS ((const char *, const char *)); | |
982 | static const struct mips_cpu_info *mips_parse_cpu | |
983 | PARAMS ((const char *, const char *)); | |
984 | static const struct mips_cpu_info *mips_cpu_info_from_isa | |
985 | PARAMS ((int)); | |
252b5132 RH |
986 | \f |
987 | /* Pseudo-op table. | |
988 | ||
989 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
990 | should be defined here, but are currently unsupported: .alias, | |
991 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
992 | ||
993 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
994 | specific to the type of debugging information being generated, and | |
995 | should be defined by the object format: .aent, .begin, .bend, | |
996 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
997 | .vreg. | |
998 | ||
999 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1000 | not MIPS CPU specific, but are also not specific to the object file | |
1001 | format. This file is probably the best place to define them, but | |
1002 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
1003 | .struct. */ | |
1004 | ||
e972090a NC |
1005 | static const pseudo_typeS mips_pseudo_table[] = |
1006 | { | |
beae10d5 | 1007 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1008 | {"option", s_option, 0}, |
1009 | {"set", s_mipsset, 0}, | |
1010 | {"rdata", s_change_sec, 'r'}, | |
1011 | {"sdata", s_change_sec, 's'}, | |
1012 | {"livereg", s_ignore, 0}, | |
1013 | {"abicalls", s_abicalls, 0}, | |
1014 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1015 | {"cpsetup", s_cpsetup, 0}, |
1016 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1017 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
1018 | {"cpreturn", s_cpreturn, 0}, |
1019 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 1020 | {"gpword", s_gpword, 0}, |
10181a0d | 1021 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1022 | {"cpadd", s_cpadd, 0}, |
1023 | {"insn", s_insn, 0}, | |
1024 | ||
beae10d5 | 1025 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
1026 | chips. */ |
1027 | {"asciiz", stringer, 1}, | |
1028 | {"bss", s_change_sec, 'b'}, | |
1029 | {"err", s_err, 0}, | |
1030 | {"half", s_cons, 1}, | |
1031 | {"dword", s_cons, 3}, | |
1032 | {"weakext", s_mips_weakext, 0}, | |
1033 | ||
beae10d5 | 1034 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1035 | here for one reason or another. */ |
1036 | {"align", s_align, 0}, | |
1037 | {"byte", s_cons, 0}, | |
1038 | {"data", s_change_sec, 'd'}, | |
1039 | {"double", s_float_cons, 'd'}, | |
1040 | {"float", s_float_cons, 'f'}, | |
1041 | {"globl", s_mips_globl, 0}, | |
1042 | {"global", s_mips_globl, 0}, | |
1043 | {"hword", s_cons, 1}, | |
1044 | {"int", s_cons, 2}, | |
1045 | {"long", s_cons, 2}, | |
1046 | {"octa", s_cons, 4}, | |
1047 | {"quad", s_cons, 3}, | |
cca86cc8 | 1048 | {"section", s_change_section, 0}, |
252b5132 RH |
1049 | {"short", s_cons, 1}, |
1050 | {"single", s_float_cons, 'f'}, | |
1051 | {"stabn", s_mips_stab, 'n'}, | |
1052 | {"text", s_change_sec, 't'}, | |
1053 | {"word", s_cons, 2}, | |
add56521 | 1054 | |
add56521 | 1055 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1056 | |
43841e91 | 1057 | { NULL, NULL, 0 }, |
252b5132 RH |
1058 | }; |
1059 | ||
e972090a NC |
1060 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1061 | { | |
beae10d5 KH |
1062 | /* These pseudo-ops should be defined by the object file format. |
1063 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1064 | {"aent", s_mips_ent, 1}, |
1065 | {"bgnb", s_ignore, 0}, | |
1066 | {"end", s_mips_end, 0}, | |
1067 | {"endb", s_ignore, 0}, | |
1068 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1069 | {"file", s_mips_file, 0}, |
252b5132 RH |
1070 | {"fmask", s_mips_mask, 'F'}, |
1071 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1072 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1073 | {"mask", s_mips_mask, 'R'}, |
1074 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1075 | { NULL, NULL, 0 }, |
252b5132 RH |
1076 | }; |
1077 | ||
1078 | extern void pop_insert PARAMS ((const pseudo_typeS *)); | |
1079 | ||
1080 | void | |
1081 | mips_pop_insert () | |
1082 | { | |
1083 | pop_insert (mips_pseudo_table); | |
1084 | if (! ECOFF_DEBUGGING) | |
1085 | pop_insert (mips_nonecoff_pseudo_table); | |
1086 | } | |
1087 | \f | |
1088 | /* Symbols labelling the current insn. */ | |
1089 | ||
e972090a NC |
1090 | struct insn_label_list |
1091 | { | |
252b5132 RH |
1092 | struct insn_label_list *next; |
1093 | symbolS *label; | |
1094 | }; | |
1095 | ||
1096 | static struct insn_label_list *insn_labels; | |
1097 | static struct insn_label_list *free_insn_labels; | |
1098 | ||
1099 | static void mips_clear_insn_labels PARAMS ((void)); | |
1100 | ||
1101 | static inline void | |
1102 | mips_clear_insn_labels () | |
1103 | { | |
1104 | register struct insn_label_list **pl; | |
1105 | ||
1106 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1107 | ; | |
1108 | *pl = insn_labels; | |
1109 | insn_labels = NULL; | |
1110 | } | |
1111 | \f | |
1112 | static char *expr_end; | |
1113 | ||
1114 | /* Expressions which appear in instructions. These are set by | |
1115 | mips_ip. */ | |
1116 | ||
1117 | static expressionS imm_expr; | |
1118 | static expressionS offset_expr; | |
1119 | ||
1120 | /* Relocs associated with imm_expr and offset_expr. */ | |
1121 | ||
f6688943 TS |
1122 | static bfd_reloc_code_real_type imm_reloc[3] |
1123 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1124 | static bfd_reloc_code_real_type offset_reloc[3] | |
1125 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1126 | |
1127 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ | |
1128 | ||
b34976b6 | 1129 | static bfd_boolean imm_unmatched_hi; |
252b5132 RH |
1130 | |
1131 | /* These are set by mips16_ip if an explicit extension is used. */ | |
1132 | ||
b34976b6 | 1133 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1134 | |
7ed4a06a | 1135 | #ifdef OBJ_ELF |
ecb4347a DJ |
1136 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1137 | ECOFF debugging. */ | |
252b5132 RH |
1138 | |
1139 | static segT pdr_seg; | |
7ed4a06a | 1140 | #endif |
252b5132 | 1141 | |
e013f690 TS |
1142 | /* The default target format to use. */ |
1143 | ||
1144 | const char * | |
1145 | mips_target_format () | |
1146 | { | |
1147 | switch (OUTPUT_FLAVOR) | |
1148 | { | |
1149 | case bfd_target_aout_flavour: | |
1150 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
1151 | case bfd_target_ecoff_flavour: | |
1152 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1153 | case bfd_target_coff_flavour: | |
1154 | return "pe-mips"; | |
1155 | case bfd_target_elf_flavour: | |
1156 | #ifdef TE_TMIPS | |
cfe86eaa | 1157 | /* This is traditional mips. */ |
e013f690 | 1158 | return (target_big_endian |
cfe86eaa TS |
1159 | ? (HAVE_64BIT_OBJECTS |
1160 | ? "elf64-tradbigmips" | |
1161 | : (HAVE_NEWABI | |
1162 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1163 | : (HAVE_64BIT_OBJECTS | |
1164 | ? "elf64-tradlittlemips" | |
1165 | : (HAVE_NEWABI | |
1166 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1167 | #else |
1168 | return (target_big_endian | |
cfe86eaa TS |
1169 | ? (HAVE_64BIT_OBJECTS |
1170 | ? "elf64-bigmips" | |
1171 | : (HAVE_NEWABI | |
1172 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1173 | : (HAVE_64BIT_OBJECTS | |
1174 | ? "elf64-littlemips" | |
1175 | : (HAVE_NEWABI | |
1176 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1177 | #endif |
1178 | default: | |
1179 | abort (); | |
1180 | return NULL; | |
1181 | } | |
1182 | } | |
1183 | ||
156c2f8b NC |
1184 | /* This function is called once, at assembler startup time. It should |
1185 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1186 | ||
252b5132 RH |
1187 | void |
1188 | md_begin () | |
1189 | { | |
252b5132 | 1190 | register const char *retval = NULL; |
156c2f8b | 1191 | int i = 0; |
252b5132 | 1192 | int broken = 0; |
1f25f5d3 | 1193 | |
ec68c924 | 1194 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch)) |
252b5132 RH |
1195 | as_warn (_("Could not set architecture and machine")); |
1196 | ||
252b5132 RH |
1197 | op_hash = hash_new (); |
1198 | ||
1199 | for (i = 0; i < NUMOPCODES;) | |
1200 | { | |
1201 | const char *name = mips_opcodes[i].name; | |
1202 | ||
1203 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); | |
1204 | if (retval != NULL) | |
1205 | { | |
1206 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1207 | mips_opcodes[i].name, retval); | |
1208 | /* Probably a memory allocation problem? Give up now. */ | |
1209 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1210 | } | |
1211 | do | |
1212 | { | |
1213 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1214 | { | |
1215 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1216 | broken = 1; | |
1217 | } | |
1218 | ++i; | |
1219 | } | |
1220 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1221 | } | |
1222 | ||
1223 | mips16_op_hash = hash_new (); | |
1224 | ||
1225 | i = 0; | |
1226 | while (i < bfd_mips16_num_opcodes) | |
1227 | { | |
1228 | const char *name = mips16_opcodes[i].name; | |
1229 | ||
1230 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1231 | if (retval != NULL) | |
1232 | as_fatal (_("internal: can't hash `%s': %s"), | |
1233 | mips16_opcodes[i].name, retval); | |
1234 | do | |
1235 | { | |
1236 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1237 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1238 | != mips16_opcodes[i].match)) | |
1239 | { | |
1240 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1241 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1242 | broken = 1; | |
1243 | } | |
1244 | ++i; | |
1245 | } | |
1246 | while (i < bfd_mips16_num_opcodes | |
1247 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1248 | } | |
1249 | ||
1250 | if (broken) | |
1251 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1252 | ||
1253 | /* We add all the general register names to the symbol table. This | |
1254 | helps us detect invalid uses of them. */ | |
1255 | for (i = 0; i < 32; i++) | |
1256 | { | |
1257 | char buf[5]; | |
1258 | ||
1259 | sprintf (buf, "$%d", i); | |
1260 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1261 | &zero_address_frag)); | |
1262 | } | |
76db943d TS |
1263 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1264 | &zero_address_frag)); | |
252b5132 RH |
1265 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1266 | &zero_address_frag)); | |
1267 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1268 | &zero_address_frag)); | |
1269 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1270 | &zero_address_frag)); | |
1271 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1272 | &zero_address_frag)); | |
1273 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1274 | &zero_address_frag)); | |
1275 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1276 | &zero_address_frag)); | |
85b51719 TS |
1277 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1278 | &zero_address_frag)); | |
252b5132 RH |
1279 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1280 | &zero_address_frag)); | |
1281 | ||
6047c971 AO |
1282 | /* If we don't add these register names to the symbol table, they |
1283 | may end up being added as regular symbols by operand(), and then | |
1284 | make it to the object file as undefined in case they're not | |
1285 | regarded as local symbols. They're local in o32, since `$' is a | |
1286 | local symbol prefix, but not in n32 or n64. */ | |
1287 | for (i = 0; i < 8; i++) | |
1288 | { | |
1289 | char buf[6]; | |
1290 | ||
1291 | sprintf (buf, "$fcc%i", i); | |
1292 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1293 | &zero_address_frag)); | |
1294 | } | |
1295 | ||
b34976b6 | 1296 | mips_no_prev_insn (FALSE); |
252b5132 RH |
1297 | |
1298 | mips_gprmask = 0; | |
1299 | mips_cprmask[0] = 0; | |
1300 | mips_cprmask[1] = 0; | |
1301 | mips_cprmask[2] = 0; | |
1302 | mips_cprmask[3] = 0; | |
1303 | ||
1304 | /* set the default alignment for the text section (2**2) */ | |
1305 | record_alignment (text_section, 2); | |
1306 | ||
1307 | if (USE_GLOBAL_POINTER_OPT) | |
1308 | bfd_set_gp_size (stdoutput, g_switch_value); | |
1309 | ||
1310 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1311 | { | |
1312 | /* On a native system, sections must be aligned to 16 byte | |
1313 | boundaries. When configured for an embedded ELF target, we | |
1314 | don't bother. */ | |
1315 | if (strcmp (TARGET_OS, "elf") != 0) | |
1316 | { | |
1317 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1318 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1319 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1320 | } | |
1321 | ||
1322 | /* Create a .reginfo section for register masks and a .mdebug | |
1323 | section for debugging information. */ | |
1324 | { | |
1325 | segT seg; | |
1326 | subsegT subseg; | |
1327 | flagword flags; | |
1328 | segT sec; | |
1329 | ||
1330 | seg = now_seg; | |
1331 | subseg = now_subseg; | |
1332 | ||
1333 | /* The ABI says this section should be loaded so that the | |
1334 | running program can access it. However, we don't load it | |
1335 | if we are configured for an embedded target */ | |
1336 | flags = SEC_READONLY | SEC_DATA; | |
1337 | if (strcmp (TARGET_OS, "elf") != 0) | |
1338 | flags |= SEC_ALLOC | SEC_LOAD; | |
1339 | ||
316f5878 | 1340 | if (mips_abi != N64_ABI) |
252b5132 RH |
1341 | { |
1342 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1343 | ||
195325d2 TS |
1344 | bfd_set_section_flags (stdoutput, sec, flags); |
1345 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1346 | |
252b5132 RH |
1347 | #ifdef OBJ_ELF |
1348 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1349 | #endif | |
1350 | } | |
1351 | else | |
1352 | { | |
1353 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1354 | .reginfo section. */ | |
1355 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1356 | bfd_set_section_flags (stdoutput, sec, flags); |
1357 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1358 | |
1359 | #ifdef OBJ_ELF | |
1360 | /* Set up the option header. */ | |
1361 | { | |
1362 | Elf_Internal_Options opthdr; | |
1363 | char *f; | |
1364 | ||
1365 | opthdr.kind = ODK_REGINFO; | |
1366 | opthdr.size = (sizeof (Elf_External_Options) | |
1367 | + sizeof (Elf64_External_RegInfo)); | |
1368 | opthdr.section = 0; | |
1369 | opthdr.info = 0; | |
1370 | f = frag_more (sizeof (Elf_External_Options)); | |
1371 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1372 | (Elf_External_Options *) f); | |
1373 | ||
1374 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1375 | } | |
1376 | #endif | |
1377 | } | |
1378 | ||
1379 | if (ECOFF_DEBUGGING) | |
1380 | { | |
1381 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1382 | (void) bfd_set_section_flags (stdoutput, sec, | |
1383 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1384 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1385 | } | |
ecb4347a DJ |
1386 | #ifdef OBJ_ELF |
1387 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1388 | { | |
1389 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1390 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1391 | SEC_READONLY | SEC_RELOC | |
1392 | | SEC_DEBUGGING); | |
1393 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1394 | } | |
252b5132 RH |
1395 | #endif |
1396 | ||
1397 | subseg_set (seg, subseg); | |
1398 | } | |
1399 | } | |
1400 | ||
1401 | if (! ECOFF_DEBUGGING) | |
1402 | md_obj_begin (); | |
1403 | } | |
1404 | ||
1405 | void | |
1406 | md_mips_end () | |
1407 | { | |
1408 | if (! ECOFF_DEBUGGING) | |
1409 | md_obj_end (); | |
1410 | } | |
1411 | ||
1412 | void | |
1413 | md_assemble (str) | |
1414 | char *str; | |
1415 | { | |
1416 | struct mips_cl_insn insn; | |
f6688943 TS |
1417 | bfd_reloc_code_real_type unused_reloc[3] |
1418 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1419 | |
1420 | imm_expr.X_op = O_absent; | |
b34976b6 | 1421 | imm_unmatched_hi = FALSE; |
252b5132 | 1422 | offset_expr.X_op = O_absent; |
f6688943 TS |
1423 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1424 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1425 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1426 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1427 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1428 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1429 | |
1430 | if (mips_opts.mips16) | |
1431 | mips16_ip (str, &insn); | |
1432 | else | |
1433 | { | |
1434 | mips_ip (str, &insn); | |
beae10d5 KH |
1435 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1436 | str, insn.insn_opcode)); | |
252b5132 RH |
1437 | } |
1438 | ||
1439 | if (insn_error) | |
1440 | { | |
1441 | as_bad ("%s `%s'", insn_error, str); | |
1442 | return; | |
1443 | } | |
1444 | ||
1445 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1446 | { | |
1447 | if (mips_opts.mips16) | |
1448 | mips16_macro (&insn); | |
1449 | else | |
1450 | macro (&insn); | |
1451 | } | |
1452 | else | |
1453 | { | |
1454 | if (imm_expr.X_op != O_absent) | |
c4e7957c | 1455 | append_insn (NULL, &insn, &imm_expr, imm_reloc, imm_unmatched_hi); |
252b5132 | 1456 | else if (offset_expr.X_op != O_absent) |
b34976b6 | 1457 | append_insn (NULL, &insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 1458 | else |
b34976b6 | 1459 | append_insn (NULL, &insn, NULL, unused_reloc, FALSE); |
252b5132 RH |
1460 | } |
1461 | } | |
1462 | ||
1463 | /* See whether instruction IP reads register REG. CLASS is the type | |
1464 | of register. */ | |
1465 | ||
1466 | static int | |
1467 | insn_uses_reg (ip, reg, class) | |
1468 | struct mips_cl_insn *ip; | |
1469 | unsigned int reg; | |
1470 | enum mips_regclass class; | |
1471 | { | |
1472 | if (class == MIPS16_REG) | |
1473 | { | |
1474 | assert (mips_opts.mips16); | |
1475 | reg = mips16_to_32_reg_map[reg]; | |
1476 | class = MIPS_GR_REG; | |
1477 | } | |
1478 | ||
85b51719 TS |
1479 | /* Don't report on general register ZERO, since it never changes. */ |
1480 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1481 | return 0; |
1482 | ||
1483 | if (class == MIPS_FP_REG) | |
1484 | { | |
1485 | assert (! mips_opts.mips16); | |
1486 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1487 | This is not optimal, because it will introduce an unnecessary | |
1488 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1489 | need to distinguish reading both $f0 and $f1 or just one of | |
1490 | them. Note that we don't have to check the other way, | |
1491 | because there is no instruction that sets both $f0 and $f1 | |
1492 | and requires a delay. */ | |
1493 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1494 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1495 | == (reg &~ (unsigned) 1))) | |
1496 | return 1; | |
1497 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1498 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1499 | == (reg &~ (unsigned) 1))) | |
1500 | return 1; | |
1501 | } | |
1502 | else if (! mips_opts.mips16) | |
1503 | { | |
1504 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1505 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1506 | return 1; | |
1507 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1508 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1509 | return 1; | |
1510 | } | |
1511 | else | |
1512 | { | |
1513 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1514 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1515 | & MIPS16OP_MASK_RX)] | |
1516 | == reg)) | |
1517 | return 1; | |
1518 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1519 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1520 | & MIPS16OP_MASK_RY)] | |
1521 | == reg)) | |
1522 | return 1; | |
1523 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1524 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1525 | & MIPS16OP_MASK_MOVE32Z)] | |
1526 | == reg)) | |
1527 | return 1; | |
1528 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1529 | return 1; | |
1530 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1531 | return 1; | |
1532 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1533 | return 1; | |
1534 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1535 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1536 | & MIPS16OP_MASK_REGR32) == reg) | |
1537 | return 1; | |
1538 | } | |
1539 | ||
1540 | return 0; | |
1541 | } | |
1542 | ||
1543 | /* This function returns true if modifying a register requires a | |
1544 | delay. */ | |
1545 | ||
1546 | static int | |
1547 | reg_needs_delay (reg) | |
156c2f8b | 1548 | unsigned int reg; |
252b5132 RH |
1549 | { |
1550 | unsigned long prev_pinfo; | |
1551 | ||
1552 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1553 | if (! mips_opts.noreorder | |
9ce8a5dd | 1554 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1555 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1556 | || (! gpr_interlocks | |
1557 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1558 | { | |
1559 | /* A load from a coprocessor or from memory. All load | |
1560 | delays delay the use of general register rt for one | |
1561 | instruction on the r3000. The r6000 and r4000 use | |
1562 | interlocks. */ | |
bdaaa2e1 | 1563 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1564 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1565 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1566 | return 1; | |
1567 | } | |
1568 | ||
1569 | return 0; | |
1570 | } | |
1571 | ||
1572 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1573 | handle them specially, such as generating jalx instructions when | |
1574 | needed. We also make them odd for the duration of the assembly, in | |
1575 | order to generate the right sort of code. We will make them even | |
1576 | in the adjust_symtab routine, while leaving them marked. This is | |
1577 | convenient for the debugger and the disassembler. The linker knows | |
1578 | to make them odd again. */ | |
1579 | ||
1580 | static void | |
1581 | mips16_mark_labels () | |
1582 | { | |
1583 | if (mips_opts.mips16) | |
1584 | { | |
1585 | struct insn_label_list *l; | |
98aa84af | 1586 | valueT val; |
252b5132 RH |
1587 | |
1588 | for (l = insn_labels; l != NULL; l = l->next) | |
1589 | { | |
1590 | #ifdef OBJ_ELF | |
1591 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1592 | S_SET_OTHER (l->label, STO_MIPS16); | |
1593 | #endif | |
98aa84af AM |
1594 | val = S_GET_VALUE (l->label); |
1595 | if ((val & 1) == 0) | |
1596 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1597 | } |
1598 | } | |
1599 | } | |
1600 | ||
1601 | /* Output an instruction. PLACE is where to put the instruction; if | |
1602 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1603 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1604 | used with RELOC_TYPE. */ | |
1605 | ||
1606 | static void | |
1607 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) | |
1608 | char *place; | |
1609 | struct mips_cl_insn *ip; | |
1610 | expressionS *address_expr; | |
f6688943 | 1611 | bfd_reloc_code_real_type *reloc_type; |
b34976b6 | 1612 | bfd_boolean unmatched_hi; |
252b5132 RH |
1613 | { |
1614 | register unsigned long prev_pinfo, pinfo; | |
1615 | char *f; | |
f6688943 | 1616 | fixS *fixp[3]; |
252b5132 RH |
1617 | int nops = 0; |
1618 | ||
1619 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 1620 | mips16_mark_labels (); |
252b5132 RH |
1621 | |
1622 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1623 | pinfo = ip->insn_mo->pinfo; | |
1624 | ||
1625 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) | |
1626 | { | |
1627 | int prev_prev_nop; | |
1628 | ||
1629 | /* If the previous insn required any delay slots, see if we need | |
1630 | to insert a NOP or two. There are eight kinds of possible | |
1631 | hazards, of which an instruction can have at most one type. | |
1632 | (1) a load from memory delay | |
1633 | (2) a load from a coprocessor delay | |
1634 | (3) an unconditional branch delay | |
1635 | (4) a conditional branch delay | |
1636 | (5) a move to coprocessor register delay | |
1637 | (6) a load coprocessor register from memory delay | |
1638 | (7) a coprocessor condition code delay | |
1639 | (8) a HI/LO special register delay | |
1640 | ||
1641 | There are a lot of optimizations we could do that we don't. | |
1642 | In particular, we do not, in general, reorder instructions. | |
1643 | If you use gcc with optimization, it will reorder | |
1644 | instructions and generally do much more optimization then we | |
1645 | do here; repeating all that work in the assembler would only | |
1646 | benefit hand written assembly code, and does not seem worth | |
1647 | it. */ | |
1648 | ||
1649 | /* This is how a NOP is emitted. */ | |
1650 | #define emit_nop() \ | |
1651 | (mips_opts.mips16 \ | |
1652 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1653 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1654 | ||
1655 | /* The previous insn might require a delay slot, depending upon | |
1656 | the contents of the current insn. */ | |
1657 | if (! mips_opts.mips16 | |
9ce8a5dd | 1658 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1659 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1660 | && ! cop_interlocks) | |
1661 | || (! gpr_interlocks | |
1662 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1663 | { | |
1664 | /* A load from a coprocessor or from memory. All load | |
1665 | delays delay the use of general register rt for one | |
1666 | instruction on the r3000. The r6000 and r4000 use | |
1667 | interlocks. */ | |
beae10d5 | 1668 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1669 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1670 | if (mips_optimize == 0 | |
1671 | || insn_uses_reg (ip, | |
1672 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1673 | & OP_MASK_RT), | |
1674 | MIPS_GR_REG)) | |
1675 | ++nops; | |
1676 | } | |
1677 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1678 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 1679 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1680 | && ! cop_interlocks) |
e7af610e | 1681 | || (mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
1682 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
1683 | { | |
1684 | /* A generic coprocessor delay. The previous instruction | |
1685 | modified a coprocessor general or control register. If | |
1686 | it modified a control register, we need to avoid any | |
1687 | coprocessor instruction (this is probably not always | |
1688 | required, but it sometimes is). If it modified a general | |
1689 | register, we avoid using that register. | |
1690 | ||
1691 | On the r6000 and r4000 loading a coprocessor register | |
1692 | from memory is interlocked, and does not require a delay. | |
1693 | ||
1694 | This case is not handled very well. There is no special | |
1695 | knowledge of CP0 handling, and the coprocessors other | |
1696 | than the floating point unit are not distinguished at | |
1697 | all. */ | |
1698 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1699 | Need to modify this to include knowledge about |
252b5132 RH |
1700 | user specified delays! */ |
1701 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1702 | { | |
1703 | if (mips_optimize == 0 | |
1704 | || insn_uses_reg (ip, | |
1705 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1706 | & OP_MASK_FT), | |
1707 | MIPS_FP_REG)) | |
1708 | ++nops; | |
1709 | } | |
1710 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1711 | { | |
1712 | if (mips_optimize == 0 | |
1713 | || insn_uses_reg (ip, | |
1714 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1715 | & OP_MASK_FS), | |
1716 | MIPS_FP_REG)) | |
1717 | ++nops; | |
1718 | } | |
1719 | else | |
1720 | { | |
1721 | /* We don't know exactly what the previous instruction | |
1722 | does. If the current instruction uses a coprocessor | |
1723 | register, we must insert a NOP. If previous | |
1724 | instruction may set the condition codes, and the | |
1725 | current instruction uses them, we must insert two | |
1726 | NOPS. */ | |
bdaaa2e1 | 1727 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1728 | if (mips_optimize == 0 |
1729 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1730 | && (pinfo & INSN_READ_COND_CODE))) | |
1731 | nops += 2; | |
1732 | else if (pinfo & INSN_COP) | |
1733 | ++nops; | |
1734 | } | |
1735 | } | |
1736 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1737 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1738 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1739 | && ! cop_interlocks) | |
1740 | { | |
1741 | /* The previous instruction sets the coprocessor condition | |
1742 | codes, but does not require a general coprocessor delay | |
1743 | (this means it is a floating point comparison | |
1744 | instruction). If this instruction uses the condition | |
1745 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1746 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1747 | if (mips_optimize == 0 |
1748 | || (pinfo & INSN_READ_COND_CODE)) | |
1749 | ++nops; | |
1750 | } | |
6b76fefe CM |
1751 | |
1752 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1753 | previous insn was an mfhi/mflo and the current insn | |
1754 | reads the register that the mfhi/mflo wrote to, then | |
1755 | insert two nops. */ | |
1756 | ||
1757 | else if (mips_7000_hilo_fix | |
1758 | && MF_HILO_INSN (prev_pinfo) | |
1759 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1760 | & OP_MASK_RD), |
1761 | MIPS_GR_REG)) | |
6b76fefe CM |
1762 | { |
1763 | nops += 2; | |
1764 | } | |
1765 | ||
1766 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1767 | 2nd previous insn was an mfhi/mflo and the current insn | |
1768 | reads the register that the mfhi/mflo wrote to, then | |
1769 | insert one nop. */ | |
1770 | ||
1771 | else if (mips_7000_hilo_fix | |
1772 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1773 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1774 | & OP_MASK_RD), | |
1775 | MIPS_GR_REG)) | |
bdaaa2e1 | 1776 | |
6b76fefe | 1777 | { |
f9419b05 | 1778 | ++nops; |
6b76fefe | 1779 | } |
bdaaa2e1 | 1780 | |
252b5132 RH |
1781 | else if (prev_pinfo & INSN_READ_LO) |
1782 | { | |
1783 | /* The previous instruction reads the LO register; if the | |
1784 | current instruction writes to the LO register, we must | |
bdaaa2e1 KH |
1785 | insert two NOPS. Some newer processors have interlocks. |
1786 | Also the tx39's multiply instructions can be exectuted | |
252b5132 | 1787 | immediatly after a read from HI/LO (without the delay), |
bdaaa2e1 KH |
1788 | though the tx39's divide insns still do require the |
1789 | delay. */ | |
252b5132 | 1790 | if (! (hilo_interlocks |
ec68c924 | 1791 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1792 | && (mips_optimize == 0 |
1793 | || (pinfo & INSN_WRITE_LO))) | |
1794 | nops += 2; | |
1795 | /* Most mips16 branch insns don't have a delay slot. | |
1796 | If a read from LO is immediately followed by a branch | |
1797 | to a write to LO we have a read followed by a write | |
1798 | less than 2 insns away. We assume the target of | |
1799 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1800 | between a read and an immediately following branch. */ |
252b5132 RH |
1801 | else if (mips_opts.mips16 |
1802 | && (mips_optimize == 0 | |
1803 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1804 | ++nops; |
252b5132 RH |
1805 | } |
1806 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1807 | { | |
1808 | /* The previous instruction reads the HI register; if the | |
1809 | current instruction writes to the HI register, we must | |
1810 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1811 | Also the note tx39's multiply above. */ |
252b5132 | 1812 | if (! (hilo_interlocks |
ec68c924 | 1813 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1814 | && (mips_optimize == 0 |
1815 | || (pinfo & INSN_WRITE_HI))) | |
1816 | nops += 2; | |
1817 | /* Most mips16 branch insns don't have a delay slot. | |
1818 | If a read from HI is immediately followed by a branch | |
1819 | to a write to HI we have a read followed by a write | |
1820 | less than 2 insns away. We assume the target of | |
1821 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1822 | between a read and an immediately following branch. */ |
252b5132 RH |
1823 | else if (mips_opts.mips16 |
1824 | && (mips_optimize == 0 | |
1825 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1826 | ++nops; |
252b5132 RH |
1827 | } |
1828 | ||
1829 | /* If the previous instruction was in a noreorder section, then | |
1830 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1831 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1832 | if (prev_insn_unreordered) |
1833 | nops = 0; | |
1834 | ||
1835 | /* There are two cases which require two intervening | |
1836 | instructions: 1) setting the condition codes using a move to | |
1837 | coprocessor instruction which requires a general coprocessor | |
1838 | delay and then reading the condition codes 2) reading the HI | |
1839 | or LO register and then writing to it (except on processors | |
1840 | which have interlocks). If we are not already emitting a NOP | |
1841 | instruction, we must check for these cases compared to the | |
1842 | instruction previous to the previous instruction. */ | |
1843 | if ((! mips_opts.mips16 | |
9ce8a5dd | 1844 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1845 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1846 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1847 | && (pinfo & INSN_READ_COND_CODE) | |
1848 | && ! cop_interlocks) | |
1849 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1850 | && (pinfo & INSN_WRITE_LO) | |
1851 | && ! (hilo_interlocks | |
ec68c924 | 1852 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1853 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1854 | && (pinfo & INSN_WRITE_HI) | |
1855 | && ! (hilo_interlocks | |
ec68c924 | 1856 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1857 | prev_prev_nop = 1; |
1858 | else | |
1859 | prev_prev_nop = 0; | |
1860 | ||
1861 | if (prev_prev_insn_unreordered) | |
1862 | prev_prev_nop = 0; | |
1863 | ||
1864 | if (prev_prev_nop && nops == 0) | |
1865 | ++nops; | |
1866 | ||
60b63b72 RS |
1867 | if (mips_fix_4122_bugs && prev_insn.insn_mo->name) |
1868 | { | |
1869 | /* We're out of bits in pinfo, so we must resort to string | |
1870 | ops here. Shortcuts are selected based on opcodes being | |
1871 | limited to the VR4122 instruction set. */ | |
1872 | int min_nops = 0; | |
1873 | const char *pn = prev_insn.insn_mo->name; | |
1874 | const char *tn = ip->insn_mo->name; | |
1875 | if (strncmp(pn, "macc", 4) == 0 | |
1876 | || strncmp(pn, "dmacc", 5) == 0) | |
1877 | { | |
1878 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1879 | if (strstr (tn, "div")) | |
1880 | { | |
1881 | min_nops = 1; | |
1882 | } | |
1883 | ||
1884 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions */ | |
1885 | if (pn[0] == 'd' /* dmacc */ | |
1886 | && (strncmp(tn, "dmult", 5) == 0 | |
1887 | || strncmp(tn, "dmacc", 5) == 0)) | |
1888 | { | |
1889 | min_nops = 1; | |
1890 | } | |
1891 | ||
1892 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1893 | if (strcmp (tn, "mtlo") == 0 | |
1894 | || strcmp (tn, "mthi") == 0) | |
1895 | { | |
1896 | min_nops = 1; | |
1897 | } | |
1898 | ||
1899 | } | |
1900 | else if (strncmp(pn, "dmult", 5) == 0 | |
1901 | && (strncmp(tn, "dmult", 5) == 0 | |
1902 | || strncmp(tn, "dmacc", 5) == 0)) | |
1903 | { | |
1904 | /* Here is the rest of errata 23. */ | |
1905 | min_nops = 1; | |
1906 | } | |
1907 | if (nops < min_nops) | |
1908 | nops = min_nops; | |
1909 | } | |
1910 | ||
252b5132 RH |
1911 | /* If we are being given a nop instruction, don't bother with |
1912 | one of the nops we would otherwise output. This will only | |
1913 | happen when a nop instruction is used with mips_optimize set | |
1914 | to 0. */ | |
1915 | if (nops > 0 | |
1916 | && ! mips_opts.noreorder | |
156c2f8b | 1917 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1918 | --nops; |
1919 | ||
1920 | /* Now emit the right number of NOP instructions. */ | |
1921 | if (nops > 0 && ! mips_opts.noreorder) | |
1922 | { | |
1923 | fragS *old_frag; | |
1924 | unsigned long old_frag_offset; | |
1925 | int i; | |
1926 | struct insn_label_list *l; | |
1927 | ||
1928 | old_frag = frag_now; | |
1929 | old_frag_offset = frag_now_fix (); | |
1930 | ||
1931 | for (i = 0; i < nops; i++) | |
1932 | emit_nop (); | |
1933 | ||
1934 | if (listing) | |
1935 | { | |
1936 | listing_prev_line (); | |
1937 | /* We may be at the start of a variant frag. In case we | |
1938 | are, make sure there is enough space for the frag | |
1939 | after the frags created by listing_prev_line. The | |
1940 | argument to frag_grow here must be at least as large | |
1941 | as the argument to all other calls to frag_grow in | |
1942 | this file. We don't have to worry about being in the | |
1943 | middle of a variant frag, because the variants insert | |
1944 | all needed nop instructions themselves. */ | |
1945 | frag_grow (40); | |
1946 | } | |
1947 | ||
1948 | for (l = insn_labels; l != NULL; l = l->next) | |
1949 | { | |
98aa84af AM |
1950 | valueT val; |
1951 | ||
252b5132 | 1952 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1953 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1954 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1955 | /* mips16 text labels are stored as odd. */ |
1956 | if (mips_opts.mips16) | |
f9419b05 | 1957 | ++val; |
98aa84af | 1958 | S_SET_VALUE (l->label, val); |
252b5132 RH |
1959 | } |
1960 | ||
1961 | #ifndef NO_ECOFF_DEBUGGING | |
1962 | if (ECOFF_DEBUGGING) | |
1963 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1964 | #endif | |
1965 | } | |
1966 | else if (prev_nop_frag != NULL) | |
1967 | { | |
1968 | /* We have a frag holding nops we may be able to remove. If | |
1969 | we don't need any nops, we can decrease the size of | |
1970 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 1971 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
1972 | if (prev_nop_frag_since == 0) |
1973 | { | |
1974 | if (nops == 0) | |
1975 | { | |
1976 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1977 | --prev_nop_frag_holds; | |
1978 | } | |
1979 | else | |
1980 | prev_nop_frag_required += nops; | |
1981 | } | |
1982 | else | |
1983 | { | |
1984 | if (prev_prev_nop == 0) | |
1985 | { | |
1986 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1987 | --prev_nop_frag_holds; | |
1988 | } | |
1989 | else | |
1990 | ++prev_nop_frag_required; | |
1991 | } | |
1992 | ||
1993 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1994 | prev_nop_frag = NULL; | |
1995 | ||
1996 | ++prev_nop_frag_since; | |
1997 | ||
1998 | /* Sanity check: by the time we reach the second instruction | |
1999 | after prev_nop_frag, we should have used up all the nops | |
2000 | one way or another. */ | |
2001 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
2002 | } | |
2003 | } | |
2004 | ||
4a6a3df4 AO |
2005 | if (place == NULL |
2006 | && address_expr | |
af6ae2ad | 2007 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2008 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2009 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2010 | && mips_relax_branch | |
2011 | /* Don't try branch relaxation within .set nomacro, or within | |
2012 | .set noat if we use $at for PIC computations. If it turns | |
2013 | out that the branch was out-of-range, we'll get an error. */ | |
2014 | && !mips_opts.warn_about_macros | |
2015 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2016 | && !mips_opts.mips16) | |
2017 | { | |
2018 | f = frag_var (rs_machine_dependent, | |
2019 | relaxed_branch_length | |
2020 | (NULL, NULL, | |
2021 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2022 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4, | |
2023 | RELAX_BRANCH_ENCODE | |
af6ae2ad | 2024 | (pinfo & INSN_UNCOND_BRANCH_DELAY, |
4a6a3df4 AO |
2025 | pinfo & INSN_COND_BRANCH_LIKELY, |
2026 | pinfo & INSN_WRITE_GPR_31, | |
2027 | 0), | |
2028 | address_expr->X_add_symbol, | |
2029 | address_expr->X_add_number, | |
2030 | 0); | |
2031 | *reloc_type = BFD_RELOC_UNUSED; | |
2032 | } | |
2033 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2034 | { |
2035 | /* We need to set up a variant frag. */ | |
2036 | assert (mips_opts.mips16 && address_expr != NULL); | |
2037 | f = frag_var (rs_machine_dependent, 4, 0, | |
f6688943 | 2038 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
252b5132 RH |
2039 | mips16_small, mips16_ext, |
2040 | (prev_pinfo | |
2041 | & INSN_UNCOND_BRANCH_DELAY), | |
f6688943 | 2042 | (*prev_insn_reloc_type |
252b5132 | 2043 | == BFD_RELOC_MIPS16_JMP)), |
c4e7957c | 2044 | make_expr_symbol (address_expr), 0, NULL); |
252b5132 RH |
2045 | } |
2046 | else if (place != NULL) | |
2047 | f = place; | |
2048 | else if (mips_opts.mips16 | |
2049 | && ! ip->use_extend | |
f6688943 | 2050 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2051 | { |
2052 | /* Make sure there is enough room to swap this instruction with | |
2053 | a following jump instruction. */ | |
2054 | frag_grow (6); | |
2055 | f = frag_more (2); | |
2056 | } | |
2057 | else | |
2058 | { | |
2059 | if (mips_opts.mips16 | |
2060 | && mips_opts.noreorder | |
2061 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2062 | as_warn (_("extended instruction in delay slot")); | |
2063 | ||
2064 | f = frag_more (4); | |
2065 | } | |
2066 | ||
f6688943 TS |
2067 | fixp[0] = fixp[1] = fixp[2] = NULL; |
2068 | if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED) | |
252b5132 RH |
2069 | { |
2070 | if (address_expr->X_op == O_constant) | |
2071 | { | |
4db1a35d | 2072 | valueT tmp; |
f6688943 TS |
2073 | |
2074 | switch (*reloc_type) | |
252b5132 RH |
2075 | { |
2076 | case BFD_RELOC_32: | |
2077 | ip->insn_opcode |= address_expr->X_add_number; | |
2078 | break; | |
2079 | ||
f6688943 TS |
2080 | case BFD_RELOC_MIPS_HIGHEST: |
2081 | tmp = (address_expr->X_add_number + 0x800080008000) >> 16; | |
2082 | tmp >>= 16; | |
2083 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2084 | break; | |
2085 | ||
2086 | case BFD_RELOC_MIPS_HIGHER: | |
2087 | tmp = (address_expr->X_add_number + 0x80008000) >> 16; | |
2088 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2089 | break; | |
2090 | ||
2091 | case BFD_RELOC_HI16_S: | |
2092 | ip->insn_opcode |= ((address_expr->X_add_number + 0x8000) | |
2093 | >> 16) & 0xffff; | |
2094 | break; | |
2095 | ||
2096 | case BFD_RELOC_HI16: | |
2097 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2098 | break; | |
2099 | ||
252b5132 | 2100 | case BFD_RELOC_LO16: |
ed6fb7bd | 2101 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2102 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2103 | break; | |
2104 | ||
2105 | case BFD_RELOC_MIPS_JMP: | |
2106 | if ((address_expr->X_add_number & 3) != 0) | |
2107 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2108 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2109 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2110 | as_bad (_("jump address range overflow (0x%lx)"), |
2111 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2112 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2113 | break; | |
2114 | ||
2115 | case BFD_RELOC_MIPS16_JMP: | |
2116 | if ((address_expr->X_add_number & 3) != 0) | |
2117 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2118 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2119 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2120 | as_bad (_("jump address range overflow (0x%lx)"), |
2121 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2122 | ip->insn_opcode |= |
2123 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2124 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2125 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2126 | break; | |
2127 | ||
252b5132 RH |
2128 | case BFD_RELOC_16_PCREL_S2: |
2129 | goto need_reloc; | |
2130 | ||
2131 | default: | |
2132 | internalError (); | |
2133 | } | |
2134 | } | |
2135 | else | |
2136 | { | |
2137 | need_reloc: | |
f6688943 | 2138 | /* Don't generate a reloc if we are writing into a variant frag. */ |
252b5132 RH |
2139 | if (place == NULL) |
2140 | { | |
f6688943 TS |
2141 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, |
2142 | address_expr, | |
af6ae2ad | 2143 | *reloc_type == BFD_RELOC_16_PCREL_S2, |
f6688943 TS |
2144 | reloc_type[0]); |
2145 | ||
b6ff326e | 2146 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
2147 | 4 octets for 64bit assembly. */ |
2148 | if (HAVE_64BIT_GPRS && | |
2149 | (*reloc_type == BFD_RELOC_16 | |
98d3f06f KH |
2150 | || *reloc_type == BFD_RELOC_32 |
2151 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
2152 | || *reloc_type == BFD_RELOC_HI16_S | |
2153 | || *reloc_type == BFD_RELOC_LO16 | |
2154 | || *reloc_type == BFD_RELOC_GPREL16 | |
2155 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
2156 | || *reloc_type == BFD_RELOC_GPREL32 | |
2157 | || *reloc_type == BFD_RELOC_64 | |
2158 | || *reloc_type == BFD_RELOC_CTOR | |
2159 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
2160 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
2161 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
2162 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
2163 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
2164 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
f6688943 TS |
2165 | fixp[0]->fx_no_overflow = 1; |
2166 | ||
252b5132 RH |
2167 | if (unmatched_hi) |
2168 | { | |
2169 | struct mips_hi_fixup *hi_fixup; | |
2170 | ||
f6688943 | 2171 | assert (*reloc_type == BFD_RELOC_HI16_S); |
252b5132 RH |
2172 | hi_fixup = ((struct mips_hi_fixup *) |
2173 | xmalloc (sizeof (struct mips_hi_fixup))); | |
f6688943 | 2174 | hi_fixup->fixp = fixp[0]; |
252b5132 RH |
2175 | hi_fixup->seg = now_seg; |
2176 | hi_fixup->next = mips_hi_fixup_list; | |
2177 | mips_hi_fixup_list = hi_fixup; | |
2178 | } | |
f6688943 TS |
2179 | |
2180 | if (reloc_type[1] != BFD_RELOC_UNUSED) | |
2181 | { | |
2182 | /* FIXME: This symbol can be one of | |
2183 | RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */ | |
2184 | address_expr->X_op = O_absent; | |
2185 | address_expr->X_add_symbol = 0; | |
2186 | address_expr->X_add_number = 0; | |
2187 | ||
2188 | fixp[1] = fix_new_exp (frag_now, f - frag_now->fr_literal, | |
b34976b6 | 2189 | 4, address_expr, FALSE, |
f6688943 TS |
2190 | reloc_type[1]); |
2191 | ||
b6ff326e | 2192 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
2193 | 4 octets for 64bit assembly. */ |
2194 | if (HAVE_64BIT_GPRS && | |
2195 | (*reloc_type == BFD_RELOC_16 | |
2196 | || *reloc_type == BFD_RELOC_32 | |
2197 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
2198 | || *reloc_type == BFD_RELOC_HI16_S | |
2199 | || *reloc_type == BFD_RELOC_LO16 | |
2200 | || *reloc_type == BFD_RELOC_GPREL16 | |
2201 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
2202 | || *reloc_type == BFD_RELOC_GPREL32 | |
2203 | || *reloc_type == BFD_RELOC_64 | |
2204 | || *reloc_type == BFD_RELOC_CTOR | |
2205 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
2206 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
2207 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
2208 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
2209 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
2210 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
98d3f06f | 2211 | fixp[1]->fx_no_overflow = 1; |
f6688943 TS |
2212 | |
2213 | if (reloc_type[2] != BFD_RELOC_UNUSED) | |
2214 | { | |
2215 | address_expr->X_op = O_absent; | |
2216 | address_expr->X_add_symbol = 0; | |
2217 | address_expr->X_add_number = 0; | |
2218 | ||
2219 | fixp[2] = fix_new_exp (frag_now, | |
2220 | f - frag_now->fr_literal, 4, | |
b34976b6 | 2221 | address_expr, FALSE, |
f6688943 TS |
2222 | reloc_type[2]); |
2223 | ||
b6ff326e | 2224 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
2225 | 4 octets for 64bit assembly. */ |
2226 | if (HAVE_64BIT_GPRS && | |
2227 | (*reloc_type == BFD_RELOC_16 | |
2228 | || *reloc_type == BFD_RELOC_32 | |
2229 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
2230 | || *reloc_type == BFD_RELOC_HI16_S | |
2231 | || *reloc_type == BFD_RELOC_LO16 | |
2232 | || *reloc_type == BFD_RELOC_GPREL16 | |
2233 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
2234 | || *reloc_type == BFD_RELOC_GPREL32 | |
2235 | || *reloc_type == BFD_RELOC_64 | |
2236 | || *reloc_type == BFD_RELOC_CTOR | |
2237 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
2238 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
2239 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
2240 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
2241 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
2242 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
98d3f06f | 2243 | fixp[2]->fx_no_overflow = 1; |
f6688943 TS |
2244 | } |
2245 | } | |
252b5132 RH |
2246 | } |
2247 | } | |
2248 | } | |
2249 | ||
2250 | if (! mips_opts.mips16) | |
c5dd6aab DJ |
2251 | { |
2252 | md_number_to_chars (f, ip->insn_opcode, 4); | |
2253 | #ifdef OBJ_ELF | |
2254 | dwarf2_emit_insn (4); | |
2255 | #endif | |
2256 | } | |
f6688943 | 2257 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2258 | { |
2259 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
2260 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
c5dd6aab DJ |
2261 | #ifdef OBJ_ELF |
2262 | dwarf2_emit_insn (4); | |
2263 | #endif | |
252b5132 RH |
2264 | } |
2265 | else | |
2266 | { | |
2267 | if (ip->use_extend) | |
2268 | { | |
2269 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
2270 | f += 2; | |
2271 | } | |
2272 | md_number_to_chars (f, ip->insn_opcode, 2); | |
c5dd6aab DJ |
2273 | #ifdef OBJ_ELF |
2274 | dwarf2_emit_insn (ip->use_extend ? 4 : 2); | |
2275 | #endif | |
252b5132 RH |
2276 | } |
2277 | ||
2278 | /* Update the register mask information. */ | |
2279 | if (! mips_opts.mips16) | |
2280 | { | |
2281 | if (pinfo & INSN_WRITE_GPR_D) | |
2282 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
2283 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
2284 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
2285 | if (pinfo & INSN_READ_GPR_S) | |
2286 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
2287 | if (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2288 | mips_gprmask |= 1 << RA; |
252b5132 RH |
2289 | if (pinfo & INSN_WRITE_FPR_D) |
2290 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
2291 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
2292 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
2293 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
2294 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
2295 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
2296 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
2297 | if (pinfo & INSN_COP) | |
2298 | { | |
bdaaa2e1 KH |
2299 | /* We don't keep enough information to sort these cases out. |
2300 | The itbl support does keep this information however, although | |
2301 | we currently don't support itbl fprmats as part of the cop | |
2302 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2303 | } |
2304 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2305 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2306 | } |
2307 | else | |
2308 | { | |
2309 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
2310 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
2311 | & MIPS16OP_MASK_RX); | |
2312 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
2313 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
2314 | & MIPS16OP_MASK_RY); | |
2315 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2316 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
2317 | & MIPS16OP_MASK_RZ); | |
2318 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
2319 | mips_gprmask |= 1 << TREG; | |
2320 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2321 | mips_gprmask |= 1 << SP; | |
2322 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2323 | mips_gprmask |= 1 << RA; | |
2324 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2325 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2326 | if (pinfo & MIPS16_INSN_READ_Z) | |
2327 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
2328 | & MIPS16OP_MASK_MOVE32Z); | |
2329 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2330 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
2331 | & MIPS16OP_MASK_REGR32); | |
2332 | } | |
2333 | ||
2334 | if (place == NULL && ! mips_opts.noreorder) | |
2335 | { | |
2336 | /* Filling the branch delay slot is more complex. We try to | |
2337 | switch the branch with the previous instruction, which we can | |
2338 | do if the previous instruction does not set up a condition | |
2339 | that the branch tests and if the branch is not itself the | |
2340 | target of any branch. */ | |
2341 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2342 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2343 | { | |
2344 | if (mips_optimize < 2 | |
2345 | /* If we have seen .set volatile or .set nomove, don't | |
2346 | optimize. */ | |
2347 | || mips_opts.nomove != 0 | |
2348 | /* If we had to emit any NOP instructions, then we | |
2349 | already know we can not swap. */ | |
2350 | || nops != 0 | |
2351 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 2352 | swap. */ |
252b5132 RH |
2353 | || ! prev_insn_valid |
2354 | /* If the previous insn is already in a branch delay | |
2355 | slot, then we can not swap. */ | |
2356 | || prev_insn_is_delay_slot | |
2357 | /* If the previous previous insn was in a .set | |
2358 | noreorder, we can't swap. Actually, the MIPS | |
2359 | assembler will swap in this situation. However, gcc | |
2360 | configured -with-gnu-as will generate code like | |
2361 | .set noreorder | |
2362 | lw $4,XXX | |
2363 | .set reorder | |
2364 | INSN | |
2365 | bne $4,$0,foo | |
2366 | in which we can not swap the bne and INSN. If gcc is | |
2367 | not configured -with-gnu-as, it does not output the | |
2368 | .set pseudo-ops. We don't have to check | |
2369 | prev_insn_unreordered, because prev_insn_valid will | |
2370 | be 0 in that case. We don't want to use | |
2371 | prev_prev_insn_valid, because we do want to be able | |
2372 | to swap at the start of a function. */ | |
2373 | || prev_prev_insn_unreordered | |
2374 | /* If the branch is itself the target of a branch, we | |
2375 | can not swap. We cheat on this; all we check for is | |
2376 | whether there is a label on this instruction. If | |
2377 | there are any branches to anything other than a | |
2378 | label, users must use .set noreorder. */ | |
2379 | || insn_labels != NULL | |
2380 | /* If the previous instruction is in a variant frag, we | |
2381 | can not do the swap. This does not apply to the | |
2382 | mips16, which uses variant frags for different | |
2383 | purposes. */ | |
2384 | || (! mips_opts.mips16 | |
2385 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
2386 | /* If the branch reads the condition codes, we don't | |
2387 | even try to swap, because in the sequence | |
2388 | ctc1 $X,$31 | |
2389 | INSN | |
2390 | INSN | |
2391 | bc1t LABEL | |
2392 | we can not swap, and I don't feel like handling that | |
2393 | case. */ | |
2394 | || (! mips_opts.mips16 | |
9ce8a5dd | 2395 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2396 | && (pinfo & INSN_READ_COND_CODE)) |
2397 | /* We can not swap with an instruction that requires a | |
2398 | delay slot, becase the target of the branch might | |
2399 | interfere with that instruction. */ | |
2400 | || (! mips_opts.mips16 | |
9ce8a5dd | 2401 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 2402 | && (prev_pinfo |
bdaaa2e1 | 2403 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2404 | & (INSN_LOAD_COPROC_DELAY |
2405 | | INSN_COPROC_MOVE_DELAY | |
2406 | | INSN_WRITE_COND_CODE))) | |
2407 | || (! (hilo_interlocks | |
ec68c924 | 2408 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2409 | && (prev_pinfo |
2410 | & (INSN_READ_LO | |
2411 | | INSN_READ_HI))) | |
2412 | || (! mips_opts.mips16 | |
2413 | && ! gpr_interlocks | |
2414 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
2415 | || (! mips_opts.mips16 | |
e7af610e | 2416 | && mips_opts.isa == ISA_MIPS1 |
bdaaa2e1 | 2417 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2418 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) |
2419 | /* We can not swap with a branch instruction. */ | |
2420 | || (prev_pinfo | |
2421 | & (INSN_UNCOND_BRANCH_DELAY | |
2422 | | INSN_COND_BRANCH_DELAY | |
2423 | | INSN_COND_BRANCH_LIKELY)) | |
2424 | /* We do not swap with a trap instruction, since it | |
2425 | complicates trap handlers to have the trap | |
2426 | instruction be in a delay slot. */ | |
2427 | || (prev_pinfo & INSN_TRAP) | |
2428 | /* If the branch reads a register that the previous | |
2429 | instruction sets, we can not swap. */ | |
2430 | || (! mips_opts.mips16 | |
2431 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2432 | && insn_uses_reg (ip, | |
2433 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2434 | & OP_MASK_RT), | |
2435 | MIPS_GR_REG)) | |
2436 | || (! mips_opts.mips16 | |
2437 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2438 | && insn_uses_reg (ip, | |
2439 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2440 | & OP_MASK_RD), | |
2441 | MIPS_GR_REG)) | |
2442 | || (mips_opts.mips16 | |
2443 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2444 | && insn_uses_reg (ip, | |
2445 | ((prev_insn.insn_opcode | |
2446 | >> MIPS16OP_SH_RX) | |
2447 | & MIPS16OP_MASK_RX), | |
2448 | MIPS16_REG)) | |
2449 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2450 | && insn_uses_reg (ip, | |
2451 | ((prev_insn.insn_opcode | |
2452 | >> MIPS16OP_SH_RY) | |
2453 | & MIPS16OP_MASK_RY), | |
2454 | MIPS16_REG)) | |
2455 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2456 | && insn_uses_reg (ip, | |
2457 | ((prev_insn.insn_opcode | |
2458 | >> MIPS16OP_SH_RZ) | |
2459 | & MIPS16OP_MASK_RZ), | |
2460 | MIPS16_REG)) | |
2461 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2462 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2463 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2464 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2465 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2466 | && insn_uses_reg (ip, | |
2467 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2468 | insn_opcode), | |
2469 | MIPS_GR_REG)))) | |
2470 | /* If the branch writes a register that the previous | |
2471 | instruction sets, we can not swap (we know that | |
2472 | branches write only to RD or to $31). */ | |
2473 | || (! mips_opts.mips16 | |
2474 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2475 | && (((pinfo & INSN_WRITE_GPR_D) | |
2476 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2477 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2478 | || ((pinfo & INSN_WRITE_GPR_31) | |
2479 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2480 | & OP_MASK_RT) | |
f9419b05 | 2481 | == RA)))) |
252b5132 RH |
2482 | || (! mips_opts.mips16 |
2483 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2484 | && (((pinfo & INSN_WRITE_GPR_D) | |
2485 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2486 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2487 | || ((pinfo & INSN_WRITE_GPR_31) | |
2488 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2489 | & OP_MASK_RD) | |
f9419b05 | 2490 | == RA)))) |
252b5132 RH |
2491 | || (mips_opts.mips16 |
2492 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2493 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2494 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2495 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2496 | == RA)))) | |
2497 | /* If the branch writes a register that the previous | |
2498 | instruction reads, we can not swap (we know that | |
2499 | branches only write to RD or to $31). */ | |
2500 | || (! mips_opts.mips16 | |
2501 | && (pinfo & INSN_WRITE_GPR_D) | |
2502 | && insn_uses_reg (&prev_insn, | |
2503 | ((ip->insn_opcode >> OP_SH_RD) | |
2504 | & OP_MASK_RD), | |
2505 | MIPS_GR_REG)) | |
2506 | || (! mips_opts.mips16 | |
2507 | && (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2508 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) |
252b5132 RH |
2509 | || (mips_opts.mips16 |
2510 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2511 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
2512 | /* If we are generating embedded PIC code, the branch | |
2513 | might be expanded into a sequence which uses $at, so | |
2514 | we can't swap with an instruction which reads it. */ | |
2515 | || (mips_pic == EMBEDDED_PIC | |
2516 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) | |
2517 | /* If the previous previous instruction has a load | |
2518 | delay, and sets a register that the branch reads, we | |
2519 | can not swap. */ | |
2520 | || (! mips_opts.mips16 | |
9ce8a5dd | 2521 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
bdaaa2e1 | 2522 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2523 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2524 | || (! gpr_interlocks | |
2525 | && (prev_prev_insn.insn_mo->pinfo | |
2526 | & INSN_LOAD_MEMORY_DELAY))) | |
2527 | && insn_uses_reg (ip, | |
2528 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2529 | & OP_MASK_RT), | |
2530 | MIPS_GR_REG)) | |
2531 | /* If one instruction sets a condition code and the | |
2532 | other one uses a condition code, we can not swap. */ | |
2533 | || ((pinfo & INSN_READ_COND_CODE) | |
2534 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2535 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2536 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2537 | /* If the previous instruction uses the PC, we can not | |
2538 | swap. */ | |
2539 | || (mips_opts.mips16 | |
2540 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2541 | /* If the previous instruction was extended, we can not | |
2542 | swap. */ | |
2543 | || (mips_opts.mips16 && prev_insn_extended) | |
2544 | /* If the previous instruction had a fixup in mips16 | |
2545 | mode, we can not swap. This normally means that the | |
2546 | previous instruction was a 4 byte branch anyhow. */ | |
f6688943 | 2547 | || (mips_opts.mips16 && prev_insn_fixp[0]) |
bdaaa2e1 KH |
2548 | /* If the previous instruction is a sync, sync.l, or |
2549 | sync.p, we can not swap. */ | |
f173e82e | 2550 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2551 | { |
2552 | /* We could do even better for unconditional branches to | |
2553 | portions of this object file; we could pick up the | |
2554 | instruction at the destination, put it in the delay | |
2555 | slot, and bump the destination address. */ | |
2556 | emit_nop (); | |
2557 | /* Update the previous insn information. */ | |
2558 | prev_prev_insn = *ip; | |
2559 | prev_insn.insn_mo = &dummy_opcode; | |
2560 | } | |
2561 | else | |
2562 | { | |
2563 | /* It looks like we can actually do the swap. */ | |
2564 | if (! mips_opts.mips16) | |
2565 | { | |
2566 | char *prev_f; | |
2567 | char temp[4]; | |
2568 | ||
2569 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2570 | memcpy (temp, prev_f, 4); | |
2571 | memcpy (prev_f, f, 4); | |
2572 | memcpy (f, temp, 4); | |
f6688943 TS |
2573 | if (prev_insn_fixp[0]) |
2574 | { | |
2575 | prev_insn_fixp[0]->fx_frag = frag_now; | |
2576 | prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; | |
2577 | } | |
2578 | if (prev_insn_fixp[1]) | |
2579 | { | |
2580 | prev_insn_fixp[1]->fx_frag = frag_now; | |
2581 | prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; | |
2582 | } | |
2583 | if (prev_insn_fixp[2]) | |
252b5132 | 2584 | { |
f6688943 TS |
2585 | prev_insn_fixp[2]->fx_frag = frag_now; |
2586 | prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; | |
252b5132 | 2587 | } |
f6688943 | 2588 | if (fixp[0]) |
252b5132 | 2589 | { |
f6688943 TS |
2590 | fixp[0]->fx_frag = prev_insn_frag; |
2591 | fixp[0]->fx_where = prev_insn_where; | |
2592 | } | |
2593 | if (fixp[1]) | |
2594 | { | |
2595 | fixp[1]->fx_frag = prev_insn_frag; | |
2596 | fixp[1]->fx_where = prev_insn_where; | |
2597 | } | |
2598 | if (fixp[2]) | |
2599 | { | |
2600 | fixp[2]->fx_frag = prev_insn_frag; | |
2601 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2602 | } |
2603 | } | |
2604 | else | |
2605 | { | |
2606 | char *prev_f; | |
2607 | char temp[2]; | |
2608 | ||
f6688943 TS |
2609 | assert (prev_insn_fixp[0] == NULL); |
2610 | assert (prev_insn_fixp[1] == NULL); | |
2611 | assert (prev_insn_fixp[2] == NULL); | |
252b5132 RH |
2612 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
2613 | memcpy (temp, prev_f, 2); | |
2614 | memcpy (prev_f, f, 2); | |
f6688943 | 2615 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 | 2616 | { |
f6688943 | 2617 | assert (*reloc_type == BFD_RELOC_UNUSED); |
252b5132 RH |
2618 | memcpy (f, temp, 2); |
2619 | } | |
2620 | else | |
2621 | { | |
2622 | memcpy (f, f + 2, 2); | |
2623 | memcpy (f + 2, temp, 2); | |
2624 | } | |
f6688943 TS |
2625 | if (fixp[0]) |
2626 | { | |
2627 | fixp[0]->fx_frag = prev_insn_frag; | |
2628 | fixp[0]->fx_where = prev_insn_where; | |
2629 | } | |
2630 | if (fixp[1]) | |
2631 | { | |
2632 | fixp[1]->fx_frag = prev_insn_frag; | |
2633 | fixp[1]->fx_where = prev_insn_where; | |
2634 | } | |
2635 | if (fixp[2]) | |
252b5132 | 2636 | { |
f6688943 TS |
2637 | fixp[2]->fx_frag = prev_insn_frag; |
2638 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2639 | } |
2640 | } | |
2641 | ||
2642 | /* Update the previous insn information; leave prev_insn | |
2643 | unchanged. */ | |
2644 | prev_prev_insn = *ip; | |
2645 | } | |
2646 | prev_insn_is_delay_slot = 1; | |
2647 | ||
2648 | /* If that was an unconditional branch, forget the previous | |
2649 | insn information. */ | |
2650 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2651 | { | |
2652 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2653 | prev_insn.insn_mo = &dummy_opcode; | |
2654 | } | |
2655 | ||
f6688943 TS |
2656 | prev_insn_fixp[0] = NULL; |
2657 | prev_insn_fixp[1] = NULL; | |
2658 | prev_insn_fixp[2] = NULL; | |
2659 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2660 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2661 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2662 | prev_insn_extended = 0; |
2663 | } | |
2664 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2665 | { | |
2666 | /* We don't yet optimize a branch likely. What we should do | |
2667 | is look at the target, copy the instruction found there | |
2668 | into the delay slot, and increment the branch to jump to | |
2669 | the next instruction. */ | |
2670 | emit_nop (); | |
2671 | /* Update the previous insn information. */ | |
2672 | prev_prev_insn = *ip; | |
2673 | prev_insn.insn_mo = &dummy_opcode; | |
f6688943 TS |
2674 | prev_insn_fixp[0] = NULL; |
2675 | prev_insn_fixp[1] = NULL; | |
2676 | prev_insn_fixp[2] = NULL; | |
2677 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2678 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2679 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2680 | prev_insn_extended = 0; |
2681 | } | |
2682 | else | |
2683 | { | |
2684 | /* Update the previous insn information. */ | |
2685 | if (nops > 0) | |
2686 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2687 | else | |
2688 | prev_prev_insn = prev_insn; | |
2689 | prev_insn = *ip; | |
2690 | ||
2691 | /* Any time we see a branch, we always fill the delay slot | |
2692 | immediately; since this insn is not a branch, we know it | |
2693 | is not in a delay slot. */ | |
2694 | prev_insn_is_delay_slot = 0; | |
2695 | ||
f6688943 TS |
2696 | prev_insn_fixp[0] = fixp[0]; |
2697 | prev_insn_fixp[1] = fixp[1]; | |
2698 | prev_insn_fixp[2] = fixp[2]; | |
2699 | prev_insn_reloc_type[0] = reloc_type[0]; | |
2700 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2701 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2702 | if (mips_opts.mips16) |
2703 | prev_insn_extended = (ip->use_extend | |
f6688943 | 2704 | || *reloc_type > BFD_RELOC_UNUSED); |
252b5132 RH |
2705 | } |
2706 | ||
2707 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2708 | prev_insn_unreordered = 0; | |
2709 | prev_insn_frag = frag_now; | |
2710 | prev_insn_where = f - frag_now->fr_literal; | |
2711 | prev_insn_valid = 1; | |
2712 | } | |
2713 | else if (place == NULL) | |
2714 | { | |
2715 | /* We need to record a bit of information even when we are not | |
2716 | reordering, in order to determine the base address for mips16 | |
2717 | PC relative relocs. */ | |
2718 | prev_prev_insn = prev_insn; | |
2719 | prev_insn = *ip; | |
f6688943 TS |
2720 | prev_insn_reloc_type[0] = reloc_type[0]; |
2721 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2722 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2723 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2724 | prev_insn_unreordered = 1; | |
2725 | } | |
2726 | ||
2727 | /* We just output an insn, so the next one doesn't have a label. */ | |
2728 | mips_clear_insn_labels (); | |
2729 | ||
2730 | /* We must ensure that a fixup associated with an unmatched %hi | |
2731 | reloc does not become a variant frag. Otherwise, the | |
2732 | rearrangement of %hi relocs in frob_file may confuse | |
2733 | tc_gen_reloc. */ | |
2734 | if (unmatched_hi) | |
2735 | { | |
2736 | frag_wane (frag_now); | |
2737 | frag_new (0); | |
2738 | } | |
2739 | } | |
2740 | ||
2741 | /* This function forgets that there was any previous instruction or | |
2742 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2743 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2744 | |
2745 | static void | |
2746 | mips_no_prev_insn (preserve) | |
2747 | int preserve; | |
2748 | { | |
2749 | if (! preserve) | |
2750 | { | |
2751 | prev_insn.insn_mo = &dummy_opcode; | |
2752 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2753 | prev_nop_frag = NULL; | |
2754 | prev_nop_frag_holds = 0; | |
2755 | prev_nop_frag_required = 0; | |
2756 | prev_nop_frag_since = 0; | |
2757 | } | |
2758 | prev_insn_valid = 0; | |
2759 | prev_insn_is_delay_slot = 0; | |
2760 | prev_insn_unreordered = 0; | |
2761 | prev_insn_extended = 0; | |
f6688943 TS |
2762 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
2763 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2764 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2765 | prev_prev_insn_unreordered = 0; |
2766 | mips_clear_insn_labels (); | |
2767 | } | |
2768 | ||
2769 | /* This function must be called whenever we turn on noreorder or emit | |
2770 | something other than instructions. It inserts any NOPS which might | |
2771 | be needed by the previous instruction, and clears the information | |
2772 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2773 | instructions are to follow. */ |
252b5132 RH |
2774 | |
2775 | static void | |
2776 | mips_emit_delays (insns) | |
b34976b6 | 2777 | bfd_boolean insns; |
252b5132 RH |
2778 | { |
2779 | if (! mips_opts.noreorder) | |
2780 | { | |
2781 | int nops; | |
2782 | ||
2783 | nops = 0; | |
2784 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2785 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2786 | && (! cop_interlocks |
2787 | && (prev_insn.insn_mo->pinfo | |
2788 | & (INSN_LOAD_COPROC_DELAY | |
2789 | | INSN_COPROC_MOVE_DELAY | |
2790 | | INSN_WRITE_COND_CODE)))) | |
2791 | || (! hilo_interlocks | |
2792 | && (prev_insn.insn_mo->pinfo | |
2793 | & (INSN_READ_LO | |
2794 | | INSN_READ_HI))) | |
2795 | || (! mips_opts.mips16 | |
2796 | && ! gpr_interlocks | |
bdaaa2e1 | 2797 | && (prev_insn.insn_mo->pinfo |
252b5132 RH |
2798 | & INSN_LOAD_MEMORY_DELAY)) |
2799 | || (! mips_opts.mips16 | |
e7af610e | 2800 | && mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
2801 | && (prev_insn.insn_mo->pinfo |
2802 | & INSN_COPROC_MEMORY_DELAY))) | |
2803 | { | |
beae10d5 | 2804 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2805 | ++nops; |
2806 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2807 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2808 | && (! cop_interlocks |
2809 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2810 | || (! hilo_interlocks | |
2811 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2812 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2813 | ++nops; | |
2814 | ||
2815 | if (prev_insn_unreordered) | |
2816 | nops = 0; | |
2817 | } | |
2818 | else if ((! mips_opts.mips16 | |
9ce8a5dd | 2819 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2820 | && (! cop_interlocks |
2821 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2822 | || (! hilo_interlocks | |
2823 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2824 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2825 | { | |
beae10d5 | 2826 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2827 | if (! prev_prev_insn_unreordered) |
2828 | ++nops; | |
2829 | } | |
2830 | ||
60b63b72 RS |
2831 | if (mips_fix_4122_bugs && prev_insn.insn_mo->name) |
2832 | { | |
2833 | int min_nops = 0; | |
2834 | const char *pn = prev_insn.insn_mo->name; | |
2835 | if (strncmp(pn, "macc", 4) == 0 | |
2836 | || strncmp(pn, "dmacc", 5) == 0 | |
2837 | || strncmp(pn, "dmult", 5) == 0) | |
2838 | { | |
2839 | min_nops = 1; | |
2840 | } | |
2841 | if (nops < min_nops) | |
2842 | nops = min_nops; | |
2843 | } | |
2844 | ||
252b5132 RH |
2845 | if (nops > 0) |
2846 | { | |
2847 | struct insn_label_list *l; | |
2848 | ||
2849 | if (insns) | |
2850 | { | |
2851 | /* Record the frag which holds the nop instructions, so | |
2852 | that we can remove them if we don't need them. */ | |
2853 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2854 | prev_nop_frag = frag_now; | |
2855 | prev_nop_frag_holds = nops; | |
2856 | prev_nop_frag_required = 0; | |
2857 | prev_nop_frag_since = 0; | |
2858 | } | |
2859 | ||
2860 | for (; nops > 0; --nops) | |
2861 | emit_nop (); | |
2862 | ||
2863 | if (insns) | |
2864 | { | |
2865 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2866 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2867 | frag_wane (frag_now); |
2868 | frag_new (0); | |
2869 | } | |
2870 | ||
2871 | for (l = insn_labels; l != NULL; l = l->next) | |
2872 | { | |
98aa84af AM |
2873 | valueT val; |
2874 | ||
252b5132 | 2875 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2876 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2877 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2878 | /* mips16 text labels are stored as odd. */ |
2879 | if (mips_opts.mips16) | |
f9419b05 | 2880 | ++val; |
98aa84af | 2881 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2882 | } |
2883 | } | |
2884 | } | |
2885 | ||
2886 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 2887 | if (insns) |
252b5132 RH |
2888 | mips16_mark_labels (); |
2889 | ||
2890 | mips_no_prev_insn (insns); | |
2891 | } | |
2892 | ||
2893 | /* Build an instruction created by a macro expansion. This is passed | |
2894 | a pointer to the count of instructions created so far, an | |
2895 | expression, the name of the instruction to build, an operand format | |
2896 | string, and corresponding arguments. */ | |
2897 | ||
2898 | #ifdef USE_STDARG | |
2899 | static void | |
2900 | macro_build (char *place, | |
2901 | int *counter, | |
2902 | expressionS * ep, | |
2903 | const char *name, | |
2904 | const char *fmt, | |
2905 | ...) | |
2906 | #else | |
2907 | static void | |
2908 | macro_build (place, counter, ep, name, fmt, va_alist) | |
2909 | char *place; | |
2910 | int *counter; | |
2911 | expressionS *ep; | |
2912 | const char *name; | |
2913 | const char *fmt; | |
2914 | va_dcl | |
2915 | #endif | |
2916 | { | |
2917 | struct mips_cl_insn insn; | |
f6688943 | 2918 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2919 | va_list args; |
252b5132 RH |
2920 | |
2921 | #ifdef USE_STDARG | |
2922 | va_start (args, fmt); | |
2923 | #else | |
2924 | va_start (args); | |
2925 | #endif | |
2926 | ||
2927 | /* | |
2928 | * If the macro is about to expand into a second instruction, | |
2929 | * print a warning if needed. We need to pass ip as a parameter | |
2930 | * to generate a better warning message here... | |
2931 | */ | |
2932 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2933 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2934 | ||
80cc45a5 EC |
2935 | /* |
2936 | * If the macro is about to expand into a second instruction, | |
2937 | * and it is in a delay slot, print a warning. | |
2938 | */ | |
2939 | if (place == NULL | |
2940 | && *counter == 1 | |
2941 | && mips_opts.noreorder | |
2942 | && (prev_prev_insn.insn_mo->pinfo | |
2943 | & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY | |
2b2e39bf | 2944 | | INSN_COND_BRANCH_LIKELY)) != 0) |
80cc45a5 EC |
2945 | as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot")); |
2946 | ||
252b5132 | 2947 | if (place == NULL) |
f9419b05 | 2948 | ++*counter; /* bump instruction counter */ |
252b5132 RH |
2949 | |
2950 | if (mips_opts.mips16) | |
2951 | { | |
2952 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2953 | va_end (args); | |
2954 | return; | |
2955 | } | |
2956 | ||
f6688943 TS |
2957 | r[0] = BFD_RELOC_UNUSED; |
2958 | r[1] = BFD_RELOC_UNUSED; | |
2959 | r[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2960 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
2961 | assert (insn.insn_mo); | |
2962 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2963 | ||
2964 | /* Search until we get a match for NAME. */ | |
2965 | while (1) | |
2966 | { | |
b34976b6 | 2967 | /* It is assumed here that macros will never generate |
deec1734 | 2968 | MDMX or MIPS-3D instructions. */ |
252b5132 RH |
2969 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2970 | && insn.insn_mo->pinfo != INSN_MACRO | |
aec421e0 TS |
2971 | && OPCODE_IS_MEMBER (insn.insn_mo, |
2972 | (mips_opts.isa | |
3396de36 | 2973 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), |
aec421e0 | 2974 | mips_arch) |
ec68c924 | 2975 | && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) |
252b5132 RH |
2976 | break; |
2977 | ||
2978 | ++insn.insn_mo; | |
2979 | assert (insn.insn_mo->name); | |
2980 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2981 | } | |
2982 | ||
2983 | insn.insn_opcode = insn.insn_mo->match; | |
2984 | for (;;) | |
2985 | { | |
2986 | switch (*fmt++) | |
2987 | { | |
2988 | case '\0': | |
2989 | break; | |
2990 | ||
2991 | case ',': | |
2992 | case '(': | |
2993 | case ')': | |
2994 | continue; | |
2995 | ||
2996 | case 't': | |
2997 | case 'w': | |
2998 | case 'E': | |
38487616 | 2999 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
252b5132 RH |
3000 | continue; |
3001 | ||
3002 | case 'c': | |
38487616 TS |
3003 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
3004 | continue; | |
3005 | ||
252b5132 RH |
3006 | case 'T': |
3007 | case 'W': | |
38487616 | 3008 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
252b5132 RH |
3009 | continue; |
3010 | ||
3011 | case 'd': | |
3012 | case 'G': | |
38487616 | 3013 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
252b5132 RH |
3014 | continue; |
3015 | ||
4372b673 NC |
3016 | case 'U': |
3017 | { | |
3018 | int tmp = va_arg (args, int); | |
3019 | ||
38487616 TS |
3020 | insn.insn_opcode |= tmp << OP_SH_RT; |
3021 | insn.insn_opcode |= tmp << OP_SH_RD; | |
beae10d5 | 3022 | continue; |
4372b673 NC |
3023 | } |
3024 | ||
252b5132 RH |
3025 | case 'V': |
3026 | case 'S': | |
38487616 | 3027 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
252b5132 RH |
3028 | continue; |
3029 | ||
3030 | case 'z': | |
3031 | continue; | |
3032 | ||
3033 | case '<': | |
38487616 | 3034 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
252b5132 RH |
3035 | continue; |
3036 | ||
3037 | case 'D': | |
38487616 | 3038 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
252b5132 RH |
3039 | continue; |
3040 | ||
3041 | case 'B': | |
38487616 | 3042 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
252b5132 RH |
3043 | continue; |
3044 | ||
4372b673 | 3045 | case 'J': |
38487616 | 3046 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
4372b673 NC |
3047 | continue; |
3048 | ||
252b5132 | 3049 | case 'q': |
38487616 | 3050 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
252b5132 RH |
3051 | continue; |
3052 | ||
3053 | case 'b': | |
3054 | case 's': | |
3055 | case 'r': | |
3056 | case 'v': | |
38487616 | 3057 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
252b5132 RH |
3058 | continue; |
3059 | ||
3060 | case 'i': | |
3061 | case 'j': | |
3062 | case 'o': | |
f6688943 | 3063 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
cdf6fd85 | 3064 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3065 | || *r == BFD_RELOC_MIPS_LITERAL |
3066 | || *r == BFD_RELOC_MIPS_HIGHER | |
3067 | || *r == BFD_RELOC_HI16_S | |
3068 | || *r == BFD_RELOC_LO16 | |
3069 | || *r == BFD_RELOC_MIPS_GOT16 | |
3070 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3071 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3072 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3073 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 TS |
3074 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3075 | || *r == BFD_RELOC_MIPS_CALL_LO16 | |
252b5132 | 3076 | || (ep->X_op == O_subtract |
f6688943 | 3077 | && *r == BFD_RELOC_PCREL_LO16)); |
252b5132 RH |
3078 | continue; |
3079 | ||
3080 | case 'u': | |
f6688943 | 3081 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
252b5132 RH |
3082 | assert (ep != NULL |
3083 | && (ep->X_op == O_constant | |
3084 | || (ep->X_op == O_symbol | |
f6688943 TS |
3085 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3086 | || *r == BFD_RELOC_HI16_S | |
3087 | || *r == BFD_RELOC_HI16 | |
3088 | || *r == BFD_RELOC_GPREL16 | |
3089 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3090 | || *r == BFD_RELOC_MIPS_CALL_HI16)) | |
252b5132 | 3091 | || (ep->X_op == O_subtract |
f6688943 | 3092 | && *r == BFD_RELOC_PCREL_HI16_S))); |
252b5132 RH |
3093 | continue; |
3094 | ||
3095 | case 'p': | |
3096 | assert (ep != NULL); | |
3097 | /* | |
3098 | * This allows macro() to pass an immediate expression for | |
3099 | * creating short branches without creating a symbol. | |
3100 | * Note that the expression still might come from the assembly | |
3101 | * input, in which case the value is not checked for range nor | |
3102 | * is a relocation entry generated (yuck). | |
3103 | */ | |
3104 | if (ep->X_op == O_constant) | |
3105 | { | |
3106 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3107 | ep = NULL; | |
3108 | } | |
3109 | else | |
af6ae2ad | 3110 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3111 | continue; |
3112 | ||
3113 | case 'a': | |
3114 | assert (ep != NULL); | |
f6688943 | 3115 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3116 | continue; |
3117 | ||
3118 | case 'C': | |
3119 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3120 | continue; | |
3121 | ||
3122 | default: | |
3123 | internalError (); | |
3124 | } | |
3125 | break; | |
3126 | } | |
3127 | va_end (args); | |
f6688943 | 3128 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3129 | |
b34976b6 | 3130 | append_insn (place, &insn, ep, r, FALSE); |
252b5132 RH |
3131 | } |
3132 | ||
3133 | static void | |
3134 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
3135 | char *place; | |
43841e91 | 3136 | int *counter ATTRIBUTE_UNUSED; |
252b5132 RH |
3137 | expressionS *ep; |
3138 | const char *name; | |
3139 | const char *fmt; | |
3140 | va_list args; | |
3141 | { | |
3142 | struct mips_cl_insn insn; | |
f6688943 TS |
3143 | bfd_reloc_code_real_type r[3] |
3144 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3145 | |
252b5132 RH |
3146 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3147 | assert (insn.insn_mo); | |
3148 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3149 | ||
3150 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
3151 | || insn.insn_mo->pinfo == INSN_MACRO) | |
3152 | { | |
3153 | ++insn.insn_mo; | |
3154 | assert (insn.insn_mo->name); | |
3155 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3156 | } | |
3157 | ||
3158 | insn.insn_opcode = insn.insn_mo->match; | |
b34976b6 | 3159 | insn.use_extend = FALSE; |
252b5132 RH |
3160 | |
3161 | for (;;) | |
3162 | { | |
3163 | int c; | |
3164 | ||
3165 | c = *fmt++; | |
3166 | switch (c) | |
3167 | { | |
3168 | case '\0': | |
3169 | break; | |
3170 | ||
3171 | case ',': | |
3172 | case '(': | |
3173 | case ')': | |
3174 | continue; | |
3175 | ||
3176 | case 'y': | |
3177 | case 'w': | |
3178 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
3179 | continue; | |
3180 | ||
3181 | case 'x': | |
3182 | case 'v': | |
3183 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
3184 | continue; | |
3185 | ||
3186 | case 'z': | |
3187 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
3188 | continue; | |
3189 | ||
3190 | case 'Z': | |
3191 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
3192 | continue; | |
3193 | ||
3194 | case '0': | |
3195 | case 'S': | |
3196 | case 'P': | |
3197 | case 'R': | |
3198 | continue; | |
3199 | ||
3200 | case 'X': | |
3201 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
3202 | continue; | |
3203 | ||
3204 | case 'Y': | |
3205 | { | |
3206 | int regno; | |
3207 | ||
3208 | regno = va_arg (args, int); | |
3209 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3210 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3211 | } | |
3212 | continue; | |
3213 | ||
3214 | case '<': | |
3215 | case '>': | |
3216 | case '4': | |
3217 | case '5': | |
3218 | case 'H': | |
3219 | case 'W': | |
3220 | case 'D': | |
3221 | case 'j': | |
3222 | case '8': | |
3223 | case 'V': | |
3224 | case 'C': | |
3225 | case 'U': | |
3226 | case 'k': | |
3227 | case 'K': | |
3228 | case 'p': | |
3229 | case 'q': | |
3230 | { | |
3231 | assert (ep != NULL); | |
3232 | ||
3233 | if (ep->X_op != O_constant) | |
874e8986 | 3234 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3235 | else |
3236 | { | |
b34976b6 AM |
3237 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3238 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3239 | &insn.extend); |
252b5132 | 3240 | ep = NULL; |
f6688943 | 3241 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3242 | } |
3243 | } | |
3244 | continue; | |
3245 | ||
3246 | case '6': | |
3247 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
3248 | continue; | |
3249 | } | |
3250 | ||
3251 | break; | |
3252 | } | |
3253 | ||
f6688943 | 3254 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3255 | |
b34976b6 | 3256 | append_insn (place, &insn, ep, r, FALSE); |
252b5132 RH |
3257 | } |
3258 | ||
438c16b8 TS |
3259 | /* |
3260 | * Generate a "jalr" instruction with a relocation hint to the called | |
3261 | * function. This occurs in NewABI PIC code. | |
3262 | */ | |
3263 | static void | |
3264 | macro_build_jalr (icnt, ep) | |
3265 | int icnt; | |
3266 | expressionS *ep; | |
3267 | { | |
f21f8242 | 3268 | char *f; |
b34976b6 | 3269 | |
438c16b8 | 3270 | if (HAVE_NEWABI) |
f21f8242 AO |
3271 | { |
3272 | frag_grow (4); | |
3273 | f = frag_more (0); | |
3274 | } | |
438c16b8 TS |
3275 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", "d,s", |
3276 | RA, PIC_CALL_REG); | |
3277 | if (HAVE_NEWABI) | |
f21f8242 | 3278 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
b34976b6 | 3279 | 0, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3280 | } |
3281 | ||
252b5132 RH |
3282 | /* |
3283 | * Generate a "lui" instruction. | |
3284 | */ | |
3285 | static void | |
3286 | macro_build_lui (place, counter, ep, regnum) | |
3287 | char *place; | |
3288 | int *counter; | |
3289 | expressionS *ep; | |
3290 | int regnum; | |
3291 | { | |
3292 | expressionS high_expr; | |
3293 | struct mips_cl_insn insn; | |
f6688943 TS |
3294 | bfd_reloc_code_real_type r[3] |
3295 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3296 | const char *name = "lui"; |
3297 | const char *fmt = "t,u"; | |
252b5132 RH |
3298 | |
3299 | assert (! mips_opts.mips16); | |
3300 | ||
3301 | if (place == NULL) | |
3302 | high_expr = *ep; | |
3303 | else | |
3304 | { | |
3305 | high_expr.X_op = O_constant; | |
3306 | high_expr.X_add_number = ep->X_add_number; | |
3307 | } | |
3308 | ||
3309 | if (high_expr.X_op == O_constant) | |
3310 | { | |
3311 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3312 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3313 | >> 16) & 0xffff; | |
f6688943 | 3314 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3315 | } |
78e1bb40 | 3316 | else |
252b5132 RH |
3317 | { |
3318 | assert (ep->X_op == O_symbol); | |
3319 | /* _gp_disp is a special case, used from s_cpload. */ | |
3320 | assert (mips_pic == NO_PIC | |
78e1bb40 AO |
3321 | || (! HAVE_NEWABI |
3322 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)); | |
f6688943 | 3323 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3324 | } |
3325 | ||
3326 | /* | |
3327 | * If the macro is about to expand into a second instruction, | |
3328 | * print a warning if needed. We need to pass ip as a parameter | |
3329 | * to generate a better warning message here... | |
3330 | */ | |
3331 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
3332 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
3333 | ||
3334 | if (place == NULL) | |
f9419b05 | 3335 | ++*counter; /* bump instruction counter */ |
252b5132 RH |
3336 | |
3337 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
3338 | assert (insn.insn_mo); | |
3339 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3340 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
3341 | ||
3342 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
f6688943 | 3343 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3344 | { |
3345 | insn.insn_opcode |= high_expr.X_add_number; | |
b34976b6 | 3346 | append_insn (place, &insn, NULL, r, FALSE); |
252b5132 RH |
3347 | } |
3348 | else | |
b34976b6 | 3349 | append_insn (place, &insn, &high_expr, r, FALSE); |
252b5132 RH |
3350 | } |
3351 | ||
885add95 CD |
3352 | /* Generate a sequence of instructions to do a load or store from a constant |
3353 | offset off of a base register (breg) into/from a target register (treg), | |
3354 | using AT if necessary. */ | |
3355 | static void | |
3356 | macro_build_ldst_constoffset (place, counter, ep, op, treg, breg) | |
3357 | char *place; | |
3358 | int *counter; | |
3359 | expressionS *ep; | |
3360 | const char *op; | |
3361 | int treg, breg; | |
3362 | { | |
3363 | assert (ep->X_op == O_constant); | |
3364 | ||
3365 | /* Right now, this routine can only handle signed 32-bit contants. */ | |
3366 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number)) | |
3367 | as_warn (_("operand overflow")); | |
3368 | ||
3369 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3370 | { | |
3371 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
3372 | macro_build (place, counter, ep, op, "t,o(b)", treg, | |
3373 | (int) BFD_RELOC_LO16, breg); | |
3374 | } | |
3375 | else | |
3376 | { | |
3377 | /* 32-bit offset, need multiple instructions and AT, like: | |
3378 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3379 | addu $tempreg,$tempreg,$breg | |
3380 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3381 | to handle the complete offset. */ | |
3382 | macro_build_lui (place, counter, ep, AT); | |
3383 | if (place != NULL) | |
3384 | place += 4; | |
3385 | macro_build (place, counter, (expressionS *) NULL, | |
3386 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", | |
3387 | "d,v,t", AT, AT, breg); | |
3388 | if (place != NULL) | |
3389 | place += 4; | |
3390 | macro_build (place, counter, ep, op, "t,o(b)", treg, | |
3391 | (int) BFD_RELOC_LO16, AT); | |
3392 | ||
3393 | if (mips_opts.noat) | |
3394 | as_warn (_("Macro used $at after \".set noat\"")); | |
3395 | } | |
3396 | } | |
3397 | ||
252b5132 RH |
3398 | /* set_at() |
3399 | * Generates code to set the $at register to true (one) | |
3400 | * if reg is less than the immediate expression. | |
3401 | */ | |
3402 | static void | |
3403 | set_at (counter, reg, unsignedp) | |
3404 | int *counter; | |
3405 | int reg; | |
3406 | int unsignedp; | |
3407 | { | |
3408 | if (imm_expr.X_op == O_constant | |
3409 | && imm_expr.X_add_number >= -0x8000 | |
3410 | && imm_expr.X_add_number < 0x8000) | |
3411 | macro_build ((char *) NULL, counter, &imm_expr, | |
3412 | unsignedp ? "sltiu" : "slti", | |
3413 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); | |
3414 | else | |
3415 | { | |
4d34fb5f | 3416 | load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 | 3417 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
252b5132 RH |
3418 | unsignedp ? "sltu" : "slt", |
3419 | "d,v,t", AT, reg, AT); | |
3420 | } | |
3421 | } | |
3422 | ||
3423 | /* Warn if an expression is not a constant. */ | |
3424 | ||
3425 | static void | |
3426 | check_absolute_expr (ip, ex) | |
3427 | struct mips_cl_insn *ip; | |
3428 | expressionS *ex; | |
3429 | { | |
3430 | if (ex->X_op == O_big) | |
3431 | as_bad (_("unsupported large constant")); | |
3432 | else if (ex->X_op != O_constant) | |
3433 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
3434 | } | |
3435 | ||
3436 | /* Count the leading zeroes by performing a binary chop. This is a | |
3437 | bulky bit of source, but performance is a LOT better for the | |
3438 | majority of values than a simple loop to count the bits: | |
3439 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3440 | if ((v) & (1 << (31 - lcnt))) | |
3441 | break; | |
3442 | However it is not code size friendly, and the gain will drop a bit | |
3443 | on certain cached systems. | |
3444 | */ | |
3445 | #define COUNT_TOP_ZEROES(v) \ | |
3446 | (((v) & ~0xffff) == 0 \ | |
3447 | ? ((v) & ~0xff) == 0 \ | |
3448 | ? ((v) & ~0xf) == 0 \ | |
3449 | ? ((v) & ~0x3) == 0 \ | |
3450 | ? ((v) & ~0x1) == 0 \ | |
3451 | ? !(v) \ | |
3452 | ? 32 \ | |
3453 | : 31 \ | |
3454 | : 30 \ | |
3455 | : ((v) & ~0x7) == 0 \ | |
3456 | ? 29 \ | |
3457 | : 28 \ | |
3458 | : ((v) & ~0x3f) == 0 \ | |
3459 | ? ((v) & ~0x1f) == 0 \ | |
3460 | ? 27 \ | |
3461 | : 26 \ | |
3462 | : ((v) & ~0x7f) == 0 \ | |
3463 | ? 25 \ | |
3464 | : 24 \ | |
3465 | : ((v) & ~0xfff) == 0 \ | |
3466 | ? ((v) & ~0x3ff) == 0 \ | |
3467 | ? ((v) & ~0x1ff) == 0 \ | |
3468 | ? 23 \ | |
3469 | : 22 \ | |
3470 | : ((v) & ~0x7ff) == 0 \ | |
3471 | ? 21 \ | |
3472 | : 20 \ | |
3473 | : ((v) & ~0x3fff) == 0 \ | |
3474 | ? ((v) & ~0x1fff) == 0 \ | |
3475 | ? 19 \ | |
3476 | : 18 \ | |
3477 | : ((v) & ~0x7fff) == 0 \ | |
3478 | ? 17 \ | |
3479 | : 16 \ | |
3480 | : ((v) & ~0xffffff) == 0 \ | |
3481 | ? ((v) & ~0xfffff) == 0 \ | |
3482 | ? ((v) & ~0x3ffff) == 0 \ | |
3483 | ? ((v) & ~0x1ffff) == 0 \ | |
3484 | ? 15 \ | |
3485 | : 14 \ | |
3486 | : ((v) & ~0x7ffff) == 0 \ | |
3487 | ? 13 \ | |
3488 | : 12 \ | |
3489 | : ((v) & ~0x3fffff) == 0 \ | |
3490 | ? ((v) & ~0x1fffff) == 0 \ | |
3491 | ? 11 \ | |
3492 | : 10 \ | |
3493 | : ((v) & ~0x7fffff) == 0 \ | |
3494 | ? 9 \ | |
3495 | : 8 \ | |
3496 | : ((v) & ~0xfffffff) == 0 \ | |
3497 | ? ((v) & ~0x3ffffff) == 0 \ | |
3498 | ? ((v) & ~0x1ffffff) == 0 \ | |
3499 | ? 7 \ | |
3500 | : 6 \ | |
3501 | : ((v) & ~0x7ffffff) == 0 \ | |
3502 | ? 5 \ | |
3503 | : 4 \ | |
3504 | : ((v) & ~0x3fffffff) == 0 \ | |
3505 | ? ((v) & ~0x1fffffff) == 0 \ | |
3506 | ? 3 \ | |
3507 | : 2 \ | |
3508 | : ((v) & ~0x7fffffff) == 0 \ | |
3509 | ? 1 \ | |
3510 | : 0) | |
3511 | ||
3512 | /* load_register() | |
3513 | * This routine generates the least number of instructions neccessary to load | |
3514 | * an absolute expression value into a register. | |
3515 | */ | |
3516 | static void | |
3517 | load_register (counter, reg, ep, dbl) | |
3518 | int *counter; | |
3519 | int reg; | |
3520 | expressionS *ep; | |
3521 | int dbl; | |
3522 | { | |
3523 | int freg; | |
3524 | expressionS hi32, lo32; | |
3525 | ||
3526 | if (ep->X_op != O_big) | |
3527 | { | |
3528 | assert (ep->X_op == O_constant); | |
3529 | if (ep->X_add_number < 0x8000 | |
3530 | && (ep->X_add_number >= 0 | |
3531 | || (ep->X_add_number >= -0x8000 | |
3532 | && (! dbl | |
3533 | || ! ep->X_unsigned | |
3534 | || sizeof (ep->X_add_number) > 4)))) | |
3535 | { | |
3536 | /* We can handle 16 bit signed values with an addiu to | |
3537 | $zero. No need to ever use daddiu here, since $zero and | |
3538 | the result are always correct in 32 bit mode. */ | |
3539 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
3540 | (int) BFD_RELOC_LO16); | |
3541 | return; | |
3542 | } | |
3543 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3544 | { | |
3545 | /* We can handle 16 bit unsigned values with an ori to | |
3546 | $zero. */ | |
3547 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
3548 | (int) BFD_RELOC_LO16); | |
3549 | return; | |
3550 | } | |
6373ee54 | 3551 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number) |
252b5132 RH |
3552 | && (! dbl |
3553 | || ! ep->X_unsigned | |
3554 | || sizeof (ep->X_add_number) > 4 | |
3555 | || (ep->X_add_number & 0x80000000) == 0)) | |
ca4e0257 | 3556 | || ((HAVE_32BIT_GPRS || ! dbl) |
252b5132 | 3557 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
ca4e0257 | 3558 | || (HAVE_32BIT_GPRS |
252b5132 RH |
3559 | && ! dbl |
3560 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
3561 | == ~ (offsetT) 0xffffffff))) | |
3562 | { | |
3563 | /* 32 bit values require an lui. */ | |
3564 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3565 | (int) BFD_RELOC_HI16); | |
3566 | if ((ep->X_add_number & 0xffff) != 0) | |
3567 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
3568 | (int) BFD_RELOC_LO16); | |
3569 | return; | |
3570 | } | |
3571 | } | |
3572 | ||
3573 | /* The value is larger than 32 bits. */ | |
3574 | ||
ca4e0257 | 3575 | if (HAVE_32BIT_GPRS) |
252b5132 | 3576 | { |
956cd1d6 TS |
3577 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3578 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3579 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
3580 | (int) BFD_RELOC_LO16); | |
3581 | return; | |
3582 | } | |
3583 | ||
3584 | if (ep->X_op != O_big) | |
3585 | { | |
3586 | hi32 = *ep; | |
3587 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3588 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3589 | hi32.X_add_number &= 0xffffffff; | |
3590 | lo32 = *ep; | |
3591 | lo32.X_add_number &= 0xffffffff; | |
3592 | } | |
3593 | else | |
3594 | { | |
3595 | assert (ep->X_add_number > 2); | |
3596 | if (ep->X_add_number == 3) | |
3597 | generic_bignum[3] = 0; | |
3598 | else if (ep->X_add_number > 4) | |
3599 | as_bad (_("Number larger than 64 bits")); | |
3600 | lo32.X_op = O_constant; | |
3601 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3602 | hi32.X_op = O_constant; | |
3603 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3604 | } | |
3605 | ||
3606 | if (hi32.X_add_number == 0) | |
3607 | freg = 0; | |
3608 | else | |
3609 | { | |
3610 | int shift, bit; | |
3611 | unsigned long hi, lo; | |
3612 | ||
956cd1d6 | 3613 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3614 | { |
3615 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3616 | { | |
3617 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", | |
252b5132 | 3618 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3619 | return; |
3620 | } | |
3621 | if (lo32.X_add_number & 0x80000000) | |
3622 | { | |
3623 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3624 | (int) BFD_RELOC_HI16); | |
252b5132 RH |
3625 | if (lo32.X_add_number & 0xffff) |
3626 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
3627 | reg, reg, (int) BFD_RELOC_LO16); | |
beae10d5 KH |
3628 | return; |
3629 | } | |
3630 | } | |
252b5132 RH |
3631 | |
3632 | /* Check for 16bit shifted constant. We know that hi32 is | |
3633 | non-zero, so start the mask on the first bit of the hi32 | |
3634 | value. */ | |
3635 | shift = 17; | |
3636 | do | |
beae10d5 KH |
3637 | { |
3638 | unsigned long himask, lomask; | |
3639 | ||
3640 | if (shift < 32) | |
3641 | { | |
3642 | himask = 0xffff >> (32 - shift); | |
3643 | lomask = (0xffff << shift) & 0xffffffff; | |
3644 | } | |
3645 | else | |
3646 | { | |
3647 | himask = 0xffff << (shift - 32); | |
3648 | lomask = 0; | |
3649 | } | |
3650 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3651 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3652 | { | |
3653 | expressionS tmp; | |
3654 | ||
3655 | tmp.X_op = O_constant; | |
3656 | if (shift < 32) | |
3657 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3658 | | (lo32.X_add_number >> shift)); | |
3659 | else | |
3660 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
3661 | macro_build ((char *) NULL, counter, &tmp, | |
3662 | "ori", "t,r,i", reg, 0, | |
3663 | (int) BFD_RELOC_LO16); | |
2396cfb9 | 3664 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
beae10d5 KH |
3665 | (shift >= 32) ? "dsll32" : "dsll", |
3666 | "d,w,<", reg, reg, | |
3667 | (shift >= 32) ? shift - 32 : shift); | |
3668 | return; | |
3669 | } | |
f9419b05 | 3670 | ++shift; |
beae10d5 KH |
3671 | } |
3672 | while (shift <= (64 - 16)); | |
252b5132 RH |
3673 | |
3674 | /* Find the bit number of the lowest one bit, and store the | |
3675 | shifted value in hi/lo. */ | |
3676 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3677 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3678 | if (lo != 0) | |
3679 | { | |
3680 | bit = 0; | |
3681 | while ((lo & 1) == 0) | |
3682 | { | |
3683 | lo >>= 1; | |
3684 | ++bit; | |
3685 | } | |
3686 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3687 | hi >>= bit; | |
3688 | } | |
3689 | else | |
3690 | { | |
3691 | bit = 32; | |
3692 | while ((hi & 1) == 0) | |
3693 | { | |
3694 | hi >>= 1; | |
3695 | ++bit; | |
3696 | } | |
3697 | lo = hi; | |
3698 | hi = 0; | |
3699 | } | |
3700 | ||
3701 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3702 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3703 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3704 | { |
3705 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3706 | if (shift != 0) |
beae10d5 | 3707 | { |
252b5132 RH |
3708 | expressionS tmp; |
3709 | ||
3710 | /* This instruction will set the register to be all | |
3711 | ones. */ | |
beae10d5 KH |
3712 | tmp.X_op = O_constant; |
3713 | tmp.X_add_number = (offsetT) -1; | |
3714 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
252b5132 | 3715 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3716 | if (bit != 0) |
3717 | { | |
3718 | bit += shift; | |
2396cfb9 | 3719 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
beae10d5 KH |
3720 | (bit >= 32) ? "dsll32" : "dsll", |
3721 | "d,w,<", reg, reg, | |
3722 | (bit >= 32) ? bit - 32 : bit); | |
3723 | } | |
2396cfb9 | 3724 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
252b5132 | 3725 | (shift >= 32) ? "dsrl32" : "dsrl", |
beae10d5 | 3726 | "d,w,<", reg, reg, |
252b5132 | 3727 | (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
3728 | return; |
3729 | } | |
3730 | } | |
252b5132 RH |
3731 | |
3732 | /* Sign extend hi32 before calling load_register, because we can | |
3733 | generally get better code when we load a sign extended value. */ | |
3734 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3735 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
252b5132 RH |
3736 | load_register (counter, reg, &hi32, 0); |
3737 | freg = reg; | |
3738 | } | |
3739 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3740 | { | |
3741 | if (freg != 0) | |
3742 | { | |
2396cfb9 TS |
3743 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
3744 | "dsll32", "d,w,<", reg, freg, 0); | |
252b5132 RH |
3745 | freg = reg; |
3746 | } | |
3747 | } | |
3748 | else | |
3749 | { | |
3750 | expressionS mid16; | |
3751 | ||
956cd1d6 | 3752 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3753 | { |
252b5132 RH |
3754 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, |
3755 | (int) BFD_RELOC_HI16); | |
956cd1d6 TS |
3756 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
3757 | "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3758 | return; |
3759 | } | |
252b5132 RH |
3760 | |
3761 | if (freg != 0) | |
3762 | { | |
956cd1d6 TS |
3763 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll", |
3764 | "d,w,<", reg, freg, 16); | |
252b5132 RH |
3765 | freg = reg; |
3766 | } | |
3767 | mid16 = lo32; | |
3768 | mid16.X_add_number >>= 16; | |
3769 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
3770 | freg, (int) BFD_RELOC_LO16); | |
956cd1d6 TS |
3771 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll", |
3772 | "d,w,<", reg, reg, 16); | |
252b5132 RH |
3773 | freg = reg; |
3774 | } | |
3775 | if ((lo32.X_add_number & 0xffff) != 0) | |
3776 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, | |
3777 | (int) BFD_RELOC_LO16); | |
3778 | } | |
3779 | ||
3780 | /* Load an address into a register. */ | |
3781 | ||
3782 | static void | |
c9914766 | 3783 | load_address (counter, reg, ep, used_at) |
252b5132 RH |
3784 | int *counter; |
3785 | int reg; | |
3786 | expressionS *ep; | |
d6bc6245 | 3787 | int *used_at; |
252b5132 | 3788 | { |
f9419b05 | 3789 | char *p = NULL; |
252b5132 RH |
3790 | |
3791 | if (ep->X_op != O_constant | |
3792 | && ep->X_op != O_symbol) | |
3793 | { | |
3794 | as_bad (_("expression too complex")); | |
3795 | ep->X_op = O_constant; | |
3796 | } | |
3797 | ||
3798 | if (ep->X_op == O_constant) | |
3799 | { | |
c9914766 | 3800 | load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3801 | return; |
3802 | } | |
3803 | ||
3804 | if (mips_pic == NO_PIC) | |
3805 | { | |
3806 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3807 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3808 | Otherwise we want |
3809 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3810 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3811 | If we have an addend, we always use the latter form. |
76b3015f | 3812 | |
d6bc6245 TS |
3813 | With 64bit address space and a usable $at we want |
3814 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3815 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3816 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3817 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3818 | dsll32 $reg,0 | |
3a482fd5 | 3819 | daddu $reg,$reg,$at |
76b3015f | 3820 | |
c03099e6 | 3821 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3822 | on superscalar processors. |
3823 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3824 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3825 | dsll $reg,16 | |
3826 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3827 | dsll $reg,16 | |
3828 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
3829 | */ | |
c9914766 | 3830 | if (HAVE_64BIT_ADDRESSES) |
d6bc6245 | 3831 | { |
d6bc6245 TS |
3832 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
3833 | hold the data for such large chunks. */ | |
3834 | ||
460597ba | 3835 | if (*used_at == 0 && ! mips_opts.noat) |
d6bc6245 TS |
3836 | { |
3837 | macro_build (p, counter, ep, "lui", "t,u", | |
3838 | reg, (int) BFD_RELOC_MIPS_HIGHEST); | |
3839 | macro_build (p, counter, ep, "lui", "t,u", | |
3840 | AT, (int) BFD_RELOC_HI16_S); | |
3841 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3842 | reg, reg, (int) BFD_RELOC_MIPS_HIGHER); | |
3843 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3844 | AT, AT, (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
3845 | macro_build (p, counter, (expressionS *) NULL, "dsll32", |
3846 | "d,w,<", reg, reg, 0); | |
3a482fd5 | 3847 | macro_build (p, counter, (expressionS *) NULL, "daddu", |
2396cfb9 | 3848 | "d,v,t", reg, reg, AT); |
d6bc6245 TS |
3849 | *used_at = 1; |
3850 | } | |
3851 | else | |
3852 | { | |
3853 | macro_build (p, counter, ep, "lui", "t,u", | |
3854 | reg, (int) BFD_RELOC_MIPS_HIGHEST); | |
3855 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3856 | reg, reg, (int) BFD_RELOC_MIPS_HIGHER); | |
2396cfb9 TS |
3857 | macro_build (p, counter, (expressionS *) NULL, "dsll", |
3858 | "d,w,<", reg, reg, 16); | |
d6bc6245 TS |
3859 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
3860 | reg, reg, (int) BFD_RELOC_HI16_S); | |
2396cfb9 TS |
3861 | macro_build (p, counter, (expressionS *) NULL, "dsll", |
3862 | "d,w,<", reg, reg, 16); | |
d6bc6245 TS |
3863 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
3864 | reg, reg, (int) BFD_RELOC_LO16); | |
3865 | } | |
3866 | } | |
252b5132 RH |
3867 | else |
3868 | { | |
d6bc6245 TS |
3869 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3870 | && ! nopic_need_relax (ep->X_add_symbol, 1)) | |
3871 | { | |
3872 | frag_grow (20); | |
3873 | macro_build ((char *) NULL, counter, ep, | |
c9914766 TS |
3874 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", |
3875 | reg, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
d6bc6245 TS |
3876 | p = frag_var (rs_machine_dependent, 8, 0, |
3877 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3878 | mips_opts.warn_about_macros), | |
956cd1d6 | 3879 | ep->X_add_symbol, 0, NULL); |
d6bc6245 TS |
3880 | } |
3881 | macro_build_lui (p, counter, ep, reg); | |
3882 | if (p != NULL) | |
3883 | p += 4; | |
c9914766 TS |
3884 | macro_build (p, counter, ep, |
3885 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
d6bc6245 TS |
3886 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3887 | } | |
252b5132 RH |
3888 | } |
3889 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3890 | { | |
3891 | expressionS ex; | |
3892 | ||
3893 | /* If this is a reference to an external symbol, we want | |
3894 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3895 | Otherwise we want | |
3896 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3897 | nop | |
3898 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
ed6fb7bd SC |
3899 | If we have NewABI, we want |
3900 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
252b5132 RH |
3901 | If there is a constant, it must be added in after. */ |
3902 | ex.X_add_number = ep->X_add_number; | |
3903 | ep->X_add_number = 0; | |
3904 | frag_grow (20); | |
ed6fb7bd SC |
3905 | if (HAVE_NEWABI) |
3906 | { | |
3907 | macro_build ((char *) NULL, counter, ep, | |
3908 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg, | |
3909 | (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
3910 | } | |
3911 | else | |
3912 | { | |
3913 | macro_build ((char *) NULL, counter, ep, | |
3914 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", | |
3915 | reg, (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
3916 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3917 | p = frag_var (rs_machine_dependent, 4, 0, | |
3918 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), | |
3919 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3920 | macro_build (p, counter, ep, | |
3921 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
3922 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3923 | } | |
3924 | ||
252b5132 RH |
3925 | if (ex.X_add_number != 0) |
3926 | { | |
3927 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3928 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3929 | ex.X_op = O_constant; | |
3930 | macro_build ((char *) NULL, counter, &ex, | |
ca4e0257 | 3931 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3932 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3933 | } | |
3934 | } | |
3935 | else if (mips_pic == SVR4_PIC) | |
3936 | { | |
3937 | expressionS ex; | |
3938 | int off; | |
3939 | ||
3940 | /* This is the large GOT case. If this is a reference to an | |
3941 | external symbol, we want | |
3942 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3943 | addu $reg,$reg,$gp | |
3944 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3945 | Otherwise, for a reference to a local symbol, we want | |
3946 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3947 | nop | |
3948 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
438c16b8 TS |
3949 | If we have NewABI, we want |
3950 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
3951 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
252b5132 RH |
3952 | If there is a constant, it must be added in after. */ |
3953 | ex.X_add_number = ep->X_add_number; | |
3954 | ep->X_add_number = 0; | |
438c16b8 TS |
3955 | if (HAVE_NEWABI) |
3956 | { | |
3957 | macro_build ((char *) NULL, counter, ep, | |
3958 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg, | |
3959 | (int) BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
3960 | macro_build (p, counter, ep, | |
3961 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", | |
3962 | reg, reg, (int) BFD_RELOC_MIPS_GOT_OFST); | |
3963 | } | |
252b5132 | 3964 | else |
438c16b8 TS |
3965 | { |
3966 | if (reg_needs_delay (mips_gp_register)) | |
3967 | off = 4; | |
3968 | else | |
3969 | off = 0; | |
3970 | frag_grow (32); | |
3971 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3972 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3973 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
3974 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", "d,v,t", reg, | |
3975 | reg, mips_gp_register); | |
3976 | macro_build ((char *) NULL, counter, ep, | |
3977 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
3978 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); | |
3979 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3980 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3981 | mips_opts.warn_about_macros), | |
3982 | ep->X_add_symbol, 0, NULL); | |
3983 | if (off > 0) | |
3984 | { | |
3985 | /* We need a nop before loading from $gp. This special | |
3986 | check is required because the lui which starts the main | |
3987 | instruction stream does not refer to $gp, and so will not | |
3988 | insert the nop which may be required. */ | |
3989 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3990 | p += 4; | |
3991 | } | |
3992 | macro_build (p, counter, ep, | |
3993 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg, | |
3994 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
3995 | p += 4; | |
252b5132 RH |
3996 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); |
3997 | p += 4; | |
438c16b8 TS |
3998 | macro_build (p, counter, ep, |
3999 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
4000 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
252b5132 | 4001 | } |
438c16b8 | 4002 | |
252b5132 RH |
4003 | if (ex.X_add_number != 0) |
4004 | { | |
4005 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4006 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4007 | ex.X_op = O_constant; | |
f7ea7ef2 TS |
4008 | macro_build ((char *) NULL, counter, &ex, |
4009 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
252b5132 RH |
4010 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
4011 | } | |
4012 | } | |
4013 | else if (mips_pic == EMBEDDED_PIC) | |
4014 | { | |
4015 | /* We always do | |
cdf6fd85 | 4016 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
c9914766 TS |
4017 | */ |
4018 | macro_build ((char *) NULL, counter, ep, | |
4019 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
4020 | "t,r,j", reg, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
252b5132 RH |
4021 | } |
4022 | else | |
4023 | abort (); | |
4024 | } | |
4025 | ||
ea1fb5dc RS |
4026 | /* Move the contents of register SOURCE into register DEST. */ |
4027 | ||
4028 | static void | |
4029 | move_register (counter, dest, source) | |
4030 | int *counter; | |
4031 | int dest; | |
4032 | int source; | |
4033 | { | |
4034 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
4035 | HAVE_32BIT_GPRS ? "addu" : "daddu", | |
4036 | "d,v,t", dest, source, 0); | |
4037 | } | |
4038 | ||
252b5132 RH |
4039 | /* |
4040 | * Build macros | |
4041 | * This routine implements the seemingly endless macro or synthesized | |
4042 | * instructions and addressing modes in the mips assembly language. Many | |
4043 | * of these macros are simple and are similar to each other. These could | |
4044 | * probably be handled by some kind of table or grammer aproach instead of | |
4045 | * this verbose method. Others are not simple macros but are more like | |
4046 | * optimizing code generation. | |
4047 | * One interesting optimization is when several store macros appear | |
4048 | * consecutivly that would load AT with the upper half of the same address. | |
4049 | * The ensuing load upper instructions are ommited. This implies some kind | |
4050 | * of global optimization. We currently only optimize within a single macro. | |
4051 | * For many of the load and store macros if the address is specified as a | |
4052 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4053 | * first load register 'at' with zero and use it as the base register. The | |
4054 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4055 | * we're missing. | |
4056 | */ | |
4057 | static void | |
4058 | macro (ip) | |
4059 | struct mips_cl_insn *ip; | |
4060 | { | |
4061 | register int treg, sreg, dreg, breg; | |
4062 | int tempreg; | |
4063 | int mask; | |
4064 | int icnt = 0; | |
43841e91 | 4065 | int used_at = 0; |
252b5132 RH |
4066 | expressionS expr1; |
4067 | const char *s; | |
4068 | const char *s2; | |
4069 | const char *fmt; | |
4070 | int likely = 0; | |
4071 | int dbl = 0; | |
4072 | int coproc = 0; | |
4073 | int lr = 0; | |
4074 | int imm = 0; | |
4075 | offsetT maxnum; | |
4076 | int off; | |
4077 | bfd_reloc_code_real_type r; | |
252b5132 RH |
4078 | int hold_mips_optimize; |
4079 | ||
4080 | assert (! mips_opts.mips16); | |
4081 | ||
4082 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4083 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4084 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4085 | mask = ip->insn_mo->mask; | |
4086 | ||
4087 | expr1.X_op = O_constant; | |
4088 | expr1.X_op_symbol = NULL; | |
4089 | expr1.X_add_symbol = NULL; | |
4090 | expr1.X_add_number = 1; | |
4091 | ||
4092 | switch (mask) | |
4093 | { | |
4094 | case M_DABS: | |
4095 | dbl = 1; | |
4096 | case M_ABS: | |
4097 | /* bgez $a0,.+12 | |
4098 | move v0,$a0 | |
4099 | sub v0,$zero,$a0 | |
4100 | */ | |
4101 | ||
b34976b6 | 4102 | mips_emit_delays (TRUE); |
252b5132 RH |
4103 | ++mips_opts.noreorder; |
4104 | mips_any_noreorder = 1; | |
4105 | ||
4106 | expr1.X_add_number = 8; | |
4107 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); | |
4108 | if (dreg == sreg) | |
2396cfb9 TS |
4109 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
4110 | 0); | |
252b5132 | 4111 | else |
ea1fb5dc | 4112 | move_register (&icnt, dreg, sreg); |
2396cfb9 | 4113 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 4114 | dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
4115 | |
4116 | --mips_opts.noreorder; | |
4117 | return; | |
4118 | ||
4119 | case M_ADD_I: | |
4120 | s = "addi"; | |
4121 | s2 = "add"; | |
4122 | goto do_addi; | |
4123 | case M_ADDU_I: | |
4124 | s = "addiu"; | |
4125 | s2 = "addu"; | |
4126 | goto do_addi; | |
4127 | case M_DADD_I: | |
4128 | dbl = 1; | |
4129 | s = "daddi"; | |
4130 | s2 = "dadd"; | |
4131 | goto do_addi; | |
4132 | case M_DADDU_I: | |
4133 | dbl = 1; | |
4134 | s = "daddiu"; | |
4135 | s2 = "daddu"; | |
4136 | do_addi: | |
4137 | if (imm_expr.X_op == O_constant | |
4138 | && imm_expr.X_add_number >= -0x8000 | |
4139 | && imm_expr.X_add_number < 0x8000) | |
4140 | { | |
4141 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, | |
4142 | (int) BFD_RELOC_LO16); | |
4143 | return; | |
4144 | } | |
4145 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 TS |
4146 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t", |
4147 | treg, sreg, AT); | |
252b5132 RH |
4148 | break; |
4149 | ||
4150 | case M_AND_I: | |
4151 | s = "andi"; | |
4152 | s2 = "and"; | |
4153 | goto do_bit; | |
4154 | case M_OR_I: | |
4155 | s = "ori"; | |
4156 | s2 = "or"; | |
4157 | goto do_bit; | |
4158 | case M_NOR_I: | |
4159 | s = ""; | |
4160 | s2 = "nor"; | |
4161 | goto do_bit; | |
4162 | case M_XOR_I: | |
4163 | s = "xori"; | |
4164 | s2 = "xor"; | |
4165 | do_bit: | |
4166 | if (imm_expr.X_op == O_constant | |
4167 | && imm_expr.X_add_number >= 0 | |
4168 | && imm_expr.X_add_number < 0x10000) | |
4169 | { | |
4170 | if (mask != M_NOR_I) | |
4171 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, | |
4172 | sreg, (int) BFD_RELOC_LO16); | |
4173 | else | |
4174 | { | |
4175 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", | |
4176 | treg, sreg, (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
4177 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor", |
4178 | "d,v,t", treg, treg, 0); | |
252b5132 RH |
4179 | } |
4180 | return; | |
4181 | } | |
4182 | ||
d6bc6245 | 4183 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
4184 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t", |
4185 | treg, sreg, AT); | |
252b5132 RH |
4186 | break; |
4187 | ||
4188 | case M_BEQ_I: | |
4189 | s = "beq"; | |
4190 | goto beq_i; | |
4191 | case M_BEQL_I: | |
4192 | s = "beql"; | |
4193 | likely = 1; | |
4194 | goto beq_i; | |
4195 | case M_BNE_I: | |
4196 | s = "bne"; | |
4197 | goto beq_i; | |
4198 | case M_BNEL_I: | |
4199 | s = "bnel"; | |
4200 | likely = 1; | |
4201 | beq_i: | |
4202 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4203 | { | |
4204 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, | |
4205 | 0); | |
4206 | return; | |
4207 | } | |
4d34fb5f | 4208 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
252b5132 RH |
4209 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
4210 | break; | |
4211 | ||
4212 | case M_BGEL: | |
4213 | likely = 1; | |
4214 | case M_BGE: | |
4215 | if (treg == 0) | |
4216 | { | |
4217 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2396cfb9 | 4218 | likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4219 | return; |
4220 | } | |
4221 | if (sreg == 0) | |
4222 | { | |
4223 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2396cfb9 | 4224 | likely ? "blezl" : "blez", "s,p", treg); |
252b5132 RH |
4225 | return; |
4226 | } | |
2396cfb9 TS |
4227 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4228 | AT, sreg, treg); | |
252b5132 | 4229 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4230 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4231 | break; |
4232 | ||
4233 | case M_BGTL_I: | |
4234 | likely = 1; | |
4235 | case M_BGT_I: | |
4236 | /* check for > max integer */ | |
4237 | maxnum = 0x7fffffff; | |
ca4e0257 | 4238 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4239 | { |
4240 | maxnum <<= 16; | |
4241 | maxnum |= 0xffff; | |
4242 | maxnum <<= 16; | |
4243 | maxnum |= 0xffff; | |
4244 | } | |
4245 | if (imm_expr.X_op == O_constant | |
4246 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4247 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4248 | { |
4249 | do_false: | |
4250 | /* result is always false */ | |
4251 | if (! likely) | |
4252 | { | |
39c0a331 L |
4253 | if (warn_nops) |
4254 | as_warn (_("Branch %s is always false (nop)"), | |
4255 | ip->insn_mo->name); | |
2396cfb9 TS |
4256 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", |
4257 | "", 0); | |
252b5132 RH |
4258 | } |
4259 | else | |
4260 | { | |
39c0a331 L |
4261 | if (warn_nops) |
4262 | as_warn (_("Branch likely %s is always false"), | |
4263 | ip->insn_mo->name); | |
252b5132 RH |
4264 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
4265 | "s,t,p", 0, 0); | |
4266 | } | |
4267 | return; | |
4268 | } | |
4269 | if (imm_expr.X_op != O_constant) | |
4270 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4271 | ++imm_expr.X_add_number; |
252b5132 RH |
4272 | /* FALLTHROUGH */ |
4273 | case M_BGE_I: | |
4274 | case M_BGEL_I: | |
4275 | if (mask == M_BGEL_I) | |
4276 | likely = 1; | |
4277 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4278 | { | |
4279 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4280 | likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4281 | return; |
4282 | } | |
4283 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4284 | { | |
4285 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4286 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4287 | return; |
4288 | } | |
4289 | maxnum = 0x7fffffff; | |
ca4e0257 | 4290 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4291 | { |
4292 | maxnum <<= 16; | |
4293 | maxnum |= 0xffff; | |
4294 | maxnum <<= 16; | |
4295 | maxnum |= 0xffff; | |
4296 | } | |
4297 | maxnum = - maxnum - 1; | |
4298 | if (imm_expr.X_op == O_constant | |
4299 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4300 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4301 | { |
4302 | do_true: | |
4303 | /* result is always true */ | |
4304 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
4305 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
4306 | return; | |
4307 | } | |
4308 | set_at (&icnt, sreg, 0); | |
4309 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4310 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4311 | break; |
4312 | ||
4313 | case M_BGEUL: | |
4314 | likely = 1; | |
4315 | case M_BGEU: | |
4316 | if (treg == 0) | |
4317 | goto do_true; | |
4318 | if (sreg == 0) | |
4319 | { | |
4320 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4321 | likely ? "beql" : "beq", "s,t,p", 0, treg); |
252b5132 RH |
4322 | return; |
4323 | } | |
2396cfb9 TS |
4324 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4325 | "d,v,t", AT, sreg, treg); | |
252b5132 | 4326 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4327 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4328 | break; |
4329 | ||
4330 | case M_BGTUL_I: | |
4331 | likely = 1; | |
4332 | case M_BGTU_I: | |
4333 | if (sreg == 0 | |
ca4e0257 | 4334 | || (HAVE_32BIT_GPRS |
252b5132 | 4335 | && imm_expr.X_op == O_constant |
956cd1d6 | 4336 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4337 | goto do_false; |
4338 | if (imm_expr.X_op != O_constant) | |
4339 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4340 | ++imm_expr.X_add_number; |
252b5132 RH |
4341 | /* FALLTHROUGH */ |
4342 | case M_BGEU_I: | |
4343 | case M_BGEUL_I: | |
4344 | if (mask == M_BGEUL_I) | |
4345 | likely = 1; | |
4346 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4347 | goto do_true; | |
4348 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4349 | { | |
4350 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4351 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
252b5132 RH |
4352 | return; |
4353 | } | |
4354 | set_at (&icnt, sreg, 1); | |
4355 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4356 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4357 | break; |
4358 | ||
4359 | case M_BGTL: | |
4360 | likely = 1; | |
4361 | case M_BGT: | |
4362 | if (treg == 0) | |
4363 | { | |
4364 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4365 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4366 | return; |
4367 | } | |
4368 | if (sreg == 0) | |
4369 | { | |
4370 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4371 | likely ? "bltzl" : "bltz", "s,p", treg); |
252b5132 RH |
4372 | return; |
4373 | } | |
2396cfb9 TS |
4374 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4375 | AT, treg, sreg); | |
252b5132 | 4376 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4377 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4378 | break; |
4379 | ||
4380 | case M_BGTUL: | |
4381 | likely = 1; | |
4382 | case M_BGTU: | |
4383 | if (treg == 0) | |
4384 | { | |
4385 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4386 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
252b5132 RH |
4387 | return; |
4388 | } | |
4389 | if (sreg == 0) | |
4390 | goto do_false; | |
2396cfb9 TS |
4391 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4392 | "d,v,t", AT, treg, sreg); | |
252b5132 | 4393 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4394 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4395 | break; |
4396 | ||
4397 | case M_BLEL: | |
4398 | likely = 1; | |
4399 | case M_BLE: | |
4400 | if (treg == 0) | |
4401 | { | |
4402 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4403 | likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4404 | return; |
4405 | } | |
4406 | if (sreg == 0) | |
4407 | { | |
4408 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4409 | likely ? "bgezl" : "bgez", "s,p", treg); |
252b5132 RH |
4410 | return; |
4411 | } | |
2396cfb9 TS |
4412 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4413 | AT, treg, sreg); | |
252b5132 | 4414 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4415 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4416 | break; |
4417 | ||
4418 | case M_BLEL_I: | |
4419 | likely = 1; | |
4420 | case M_BLE_I: | |
4421 | maxnum = 0x7fffffff; | |
ca4e0257 | 4422 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4423 | { |
4424 | maxnum <<= 16; | |
4425 | maxnum |= 0xffff; | |
4426 | maxnum <<= 16; | |
4427 | maxnum |= 0xffff; | |
4428 | } | |
4429 | if (imm_expr.X_op == O_constant | |
4430 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4431 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4432 | goto do_true; |
4433 | if (imm_expr.X_op != O_constant) | |
4434 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4435 | ++imm_expr.X_add_number; |
252b5132 RH |
4436 | /* FALLTHROUGH */ |
4437 | case M_BLT_I: | |
4438 | case M_BLTL_I: | |
4439 | if (mask == M_BLTL_I) | |
4440 | likely = 1; | |
4441 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4442 | { | |
4443 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4444 | likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4445 | return; |
4446 | } | |
4447 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4448 | { | |
4449 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4450 | likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4451 | return; |
4452 | } | |
4453 | set_at (&icnt, sreg, 0); | |
4454 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4455 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4456 | break; |
4457 | ||
4458 | case M_BLEUL: | |
4459 | likely = 1; | |
4460 | case M_BLEU: | |
4461 | if (treg == 0) | |
4462 | { | |
4463 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4464 | likely ? "beql" : "beq", "s,t,p", sreg, 0); |
252b5132 RH |
4465 | return; |
4466 | } | |
4467 | if (sreg == 0) | |
4468 | goto do_true; | |
2396cfb9 TS |
4469 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4470 | "d,v,t", AT, treg, sreg); | |
252b5132 | 4471 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4472 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4473 | break; |
4474 | ||
4475 | case M_BLEUL_I: | |
4476 | likely = 1; | |
4477 | case M_BLEU_I: | |
4478 | if (sreg == 0 | |
ca4e0257 | 4479 | || (HAVE_32BIT_GPRS |
252b5132 | 4480 | && imm_expr.X_op == O_constant |
956cd1d6 | 4481 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4482 | goto do_true; |
4483 | if (imm_expr.X_op != O_constant) | |
4484 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4485 | ++imm_expr.X_add_number; |
252b5132 RH |
4486 | /* FALLTHROUGH */ |
4487 | case M_BLTU_I: | |
4488 | case M_BLTUL_I: | |
4489 | if (mask == M_BLTUL_I) | |
4490 | likely = 1; | |
4491 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4492 | goto do_false; | |
4493 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4494 | { | |
4495 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4496 | likely ? "beql" : "beq", | |
4497 | "s,t,p", sreg, 0); | |
4498 | return; | |
4499 | } | |
4500 | set_at (&icnt, sreg, 1); | |
4501 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4502 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4503 | break; |
4504 | ||
4505 | case M_BLTL: | |
4506 | likely = 1; | |
4507 | case M_BLT: | |
4508 | if (treg == 0) | |
4509 | { | |
4510 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4511 | likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4512 | return; |
4513 | } | |
4514 | if (sreg == 0) | |
4515 | { | |
4516 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4517 | likely ? "bgtzl" : "bgtz", "s,p", treg); |
252b5132 RH |
4518 | return; |
4519 | } | |
2396cfb9 TS |
4520 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4521 | AT, sreg, treg); | |
252b5132 | 4522 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4523 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4524 | break; |
4525 | ||
4526 | case M_BLTUL: | |
4527 | likely = 1; | |
4528 | case M_BLTU: | |
4529 | if (treg == 0) | |
4530 | goto do_false; | |
4531 | if (sreg == 0) | |
4532 | { | |
4533 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4534 | likely ? "bnel" : "bne", "s,t,p", 0, treg); |
252b5132 RH |
4535 | return; |
4536 | } | |
2396cfb9 TS |
4537 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4538 | "d,v,t", AT, sreg, | |
252b5132 RH |
4539 | treg); |
4540 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4541 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4542 | break; |
4543 | ||
4544 | case M_DDIV_3: | |
4545 | dbl = 1; | |
4546 | case M_DIV_3: | |
4547 | s = "mflo"; | |
4548 | goto do_div3; | |
4549 | case M_DREM_3: | |
4550 | dbl = 1; | |
4551 | case M_REM_3: | |
4552 | s = "mfhi"; | |
4553 | do_div3: | |
4554 | if (treg == 0) | |
4555 | { | |
4556 | as_warn (_("Divide by zero.")); | |
4557 | if (mips_trap) | |
2396cfb9 | 4558 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4559 | "s,t,q", 0, 0, 7); |
252b5132 | 4560 | else |
2396cfb9 TS |
4561 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4562 | "c", 7); | |
252b5132 RH |
4563 | return; |
4564 | } | |
4565 | ||
b34976b6 | 4566 | mips_emit_delays (TRUE); |
252b5132 RH |
4567 | ++mips_opts.noreorder; |
4568 | mips_any_noreorder = 1; | |
4569 | if (mips_trap) | |
4570 | { | |
2396cfb9 | 4571 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4572 | "s,t,q", treg, 0, 7); |
2396cfb9 | 4573 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 4574 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
4575 | } |
4576 | else | |
4577 | { | |
4578 | expr1.X_add_number = 8; | |
4579 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2396cfb9 | 4580 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 4581 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
2396cfb9 TS |
4582 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4583 | "c", 7); | |
252b5132 RH |
4584 | } |
4585 | expr1.X_add_number = -1; | |
4586 | macro_build ((char *) NULL, &icnt, &expr1, | |
4587 | dbl ? "daddiu" : "addiu", | |
4588 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); | |
4589 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
4590 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); | |
4591 | if (dbl) | |
4592 | { | |
4593 | expr1.X_add_number = 1; | |
4594 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, | |
4595 | (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
4596 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32", |
4597 | "d,w,<", AT, AT, 31); | |
252b5132 RH |
4598 | } |
4599 | else | |
4600 | { | |
4601 | expr1.X_add_number = 0x80000000; | |
4602 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, | |
4603 | (int) BFD_RELOC_HI16); | |
4604 | } | |
4605 | if (mips_trap) | |
4606 | { | |
2396cfb9 | 4607 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4608 | "s,t,q", sreg, AT, 6); |
252b5132 RH |
4609 | /* We want to close the noreorder block as soon as possible, so |
4610 | that later insns are available for delay slot filling. */ | |
4611 | --mips_opts.noreorder; | |
4612 | } | |
4613 | else | |
4614 | { | |
4615 | expr1.X_add_number = 8; | |
4616 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
2396cfb9 TS |
4617 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
4618 | 0); | |
252b5132 RH |
4619 | |
4620 | /* We want to close the noreorder block as soon as possible, so | |
4621 | that later insns are available for delay slot filling. */ | |
4622 | --mips_opts.noreorder; | |
4623 | ||
2396cfb9 TS |
4624 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4625 | "c", 6); | |
252b5132 | 4626 | } |
2396cfb9 | 4627 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg); |
252b5132 RH |
4628 | break; |
4629 | ||
4630 | case M_DIV_3I: | |
4631 | s = "div"; | |
4632 | s2 = "mflo"; | |
4633 | goto do_divi; | |
4634 | case M_DIVU_3I: | |
4635 | s = "divu"; | |
4636 | s2 = "mflo"; | |
4637 | goto do_divi; | |
4638 | case M_REM_3I: | |
4639 | s = "div"; | |
4640 | s2 = "mfhi"; | |
4641 | goto do_divi; | |
4642 | case M_REMU_3I: | |
4643 | s = "divu"; | |
4644 | s2 = "mfhi"; | |
4645 | goto do_divi; | |
4646 | case M_DDIV_3I: | |
4647 | dbl = 1; | |
4648 | s = "ddiv"; | |
4649 | s2 = "mflo"; | |
4650 | goto do_divi; | |
4651 | case M_DDIVU_3I: | |
4652 | dbl = 1; | |
4653 | s = "ddivu"; | |
4654 | s2 = "mflo"; | |
4655 | goto do_divi; | |
4656 | case M_DREM_3I: | |
4657 | dbl = 1; | |
4658 | s = "ddiv"; | |
4659 | s2 = "mfhi"; | |
4660 | goto do_divi; | |
4661 | case M_DREMU_3I: | |
4662 | dbl = 1; | |
4663 | s = "ddivu"; | |
4664 | s2 = "mfhi"; | |
4665 | do_divi: | |
4666 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4667 | { | |
4668 | as_warn (_("Divide by zero.")); | |
4669 | if (mips_trap) | |
2396cfb9 | 4670 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4671 | "s,t,q", 0, 0, 7); |
252b5132 | 4672 | else |
2396cfb9 TS |
4673 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4674 | "c", 7); | |
252b5132 RH |
4675 | return; |
4676 | } | |
4677 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4678 | { | |
4679 | if (strcmp (s2, "mflo") == 0) | |
ea1fb5dc | 4680 | move_register (&icnt, dreg, sreg); |
252b5132 | 4681 | else |
ea1fb5dc | 4682 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4683 | return; |
4684 | } | |
4685 | if (imm_expr.X_op == O_constant | |
4686 | && imm_expr.X_add_number == -1 | |
4687 | && s[strlen (s) - 1] != 'u') | |
4688 | { | |
4689 | if (strcmp (s2, "mflo") == 0) | |
4690 | { | |
2396cfb9 TS |
4691 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4692 | dbl ? "dneg" : "neg", "d,w", dreg, sreg); | |
252b5132 RH |
4693 | } |
4694 | else | |
ea1fb5dc | 4695 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4696 | return; |
4697 | } | |
4698 | ||
4699 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 TS |
4700 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4701 | sreg, AT); | |
4702 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg); | |
252b5132 RH |
4703 | break; |
4704 | ||
4705 | case M_DIVU_3: | |
4706 | s = "divu"; | |
4707 | s2 = "mflo"; | |
4708 | goto do_divu3; | |
4709 | case M_REMU_3: | |
4710 | s = "divu"; | |
4711 | s2 = "mfhi"; | |
4712 | goto do_divu3; | |
4713 | case M_DDIVU_3: | |
4714 | s = "ddivu"; | |
4715 | s2 = "mflo"; | |
4716 | goto do_divu3; | |
4717 | case M_DREMU_3: | |
4718 | s = "ddivu"; | |
4719 | s2 = "mfhi"; | |
4720 | do_divu3: | |
b34976b6 | 4721 | mips_emit_delays (TRUE); |
252b5132 RH |
4722 | ++mips_opts.noreorder; |
4723 | mips_any_noreorder = 1; | |
4724 | if (mips_trap) | |
4725 | { | |
2396cfb9 | 4726 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4727 | "s,t,q", treg, 0, 7); |
2396cfb9 TS |
4728 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4729 | sreg, treg); | |
252b5132 RH |
4730 | /* We want to close the noreorder block as soon as possible, so |
4731 | that later insns are available for delay slot filling. */ | |
4732 | --mips_opts.noreorder; | |
4733 | } | |
4734 | else | |
4735 | { | |
4736 | expr1.X_add_number = 8; | |
4737 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2396cfb9 TS |
4738 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4739 | sreg, treg); | |
252b5132 RH |
4740 | |
4741 | /* We want to close the noreorder block as soon as possible, so | |
4742 | that later insns are available for delay slot filling. */ | |
4743 | --mips_opts.noreorder; | |
2396cfb9 TS |
4744 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4745 | "c", 7); | |
252b5132 | 4746 | } |
2396cfb9 | 4747 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg); |
252b5132 RH |
4748 | return; |
4749 | ||
4750 | case M_DLA_AB: | |
4751 | dbl = 1; | |
4752 | case M_LA_AB: | |
4753 | /* Load the address of a symbol into a register. If breg is not | |
4754 | zero, we then add a base register to it. */ | |
4755 | ||
3bec30a8 TS |
4756 | if (dbl && HAVE_32BIT_GPRS) |
4757 | as_warn (_("dla used to load 32-bit register")); | |
4758 | ||
c90bbe5b | 4759 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4760 | as_warn (_("la used to load 64-bit address")); |
4761 | ||
0c11417f MR |
4762 | if (offset_expr.X_op == O_constant |
4763 | && offset_expr.X_add_number >= -0x8000 | |
4764 | && offset_expr.X_add_number < 0x8000) | |
4765 | { | |
4766 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4767 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", | |
4768 | "t,r,j", treg, sreg, (int) BFD_RELOC_LO16); | |
4769 | return; | |
4770 | } | |
4771 | ||
afdbd6d0 CD |
4772 | if (treg == breg) |
4773 | { | |
4774 | tempreg = AT; | |
4775 | used_at = 1; | |
4776 | } | |
4777 | else | |
4778 | { | |
4779 | tempreg = treg; | |
4780 | used_at = 0; | |
4781 | } | |
4782 | ||
252b5132 RH |
4783 | /* When generating embedded PIC code, we permit expressions of |
4784 | the form | |
afdbd6d0 CD |
4785 | la $treg,foo-bar |
4786 | la $treg,foo-bar($breg) | |
bb2d6cd7 | 4787 | where bar is an address in the current section. These are used |
252b5132 RH |
4788 | when getting the addresses of functions. We don't permit |
4789 | X_add_number to be non-zero, because if the symbol is | |
4790 | external the relaxing code needs to know that any addend is | |
4791 | purely the offset to X_op_symbol. */ | |
4792 | if (mips_pic == EMBEDDED_PIC | |
4793 | && offset_expr.X_op == O_subtract | |
49309057 | 4794 | && (symbol_constant_p (offset_expr.X_op_symbol) |
bb2d6cd7 | 4795 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg |
49309057 ILT |
4796 | : (symbol_equated_p (offset_expr.X_op_symbol) |
4797 | && (S_GET_SEGMENT | |
4798 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
4799 | ->X_add_symbol) | |
bb2d6cd7 | 4800 | == now_seg))) |
bb2d6cd7 GK |
4801 | && (offset_expr.X_add_number == 0 |
4802 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
252b5132 | 4803 | { |
afdbd6d0 CD |
4804 | if (breg == 0) |
4805 | { | |
4806 | tempreg = treg; | |
4807 | used_at = 0; | |
4808 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4809 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
4810 | } | |
4811 | else | |
4812 | { | |
4813 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4814 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
4815 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4d34fb5f | 4816 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu", |
afdbd6d0 CD |
4817 | "d,v,t", tempreg, tempreg, breg); |
4818 | } | |
252b5132 | 4819 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4d34fb5f | 4820 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
afdbd6d0 CD |
4821 | "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16); |
4822 | if (! used_at) | |
4823 | return; | |
4824 | break; | |
252b5132 RH |
4825 | } |
4826 | ||
4827 | if (offset_expr.X_op != O_symbol | |
4828 | && offset_expr.X_op != O_constant) | |
4829 | { | |
4830 | as_bad (_("expression too complex")); | |
4831 | offset_expr.X_op = O_constant; | |
4832 | } | |
4833 | ||
252b5132 | 4834 | if (offset_expr.X_op == O_constant) |
4d34fb5f TS |
4835 | load_register (&icnt, tempreg, &offset_expr, |
4836 | ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
4837 | ? (dbl || HAVE_64BIT_ADDRESSES) | |
4838 | : HAVE_64BIT_ADDRESSES)); | |
252b5132 RH |
4839 | else if (mips_pic == NO_PIC) |
4840 | { | |
d6bc6245 | 4841 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4842 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4843 | Otherwise we want |
4844 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4845 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4846 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4847 | so we may as well always use the latter form. |
76b3015f | 4848 | |
d6bc6245 TS |
4849 | With 64bit address space and a usable $at we want |
4850 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4851 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4852 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4853 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4854 | dsll32 $tempreg,0 | |
3a482fd5 | 4855 | daddu $tempreg,$tempreg,$at |
76b3015f | 4856 | |
c03099e6 | 4857 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4858 | on superscalar processors. |
4859 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4860 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4861 | dsll $tempreg,16 | |
4862 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4863 | dsll $tempreg,16 | |
4864 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4865 | */ | |
f9419b05 | 4866 | char *p = NULL; |
d6bc6245 | 4867 | if (HAVE_64BIT_ADDRESSES) |
252b5132 | 4868 | { |
d6bc6245 TS |
4869 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
4870 | hold the data for such large chunks. */ | |
4871 | ||
460597ba | 4872 | if (used_at == 0 && ! mips_opts.noat) |
98d3f06f KH |
4873 | { |
4874 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4875 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
4876 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4877 | AT, (int) BFD_RELOC_HI16_S); | |
4878 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4879 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
4880 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4881 | AT, AT, (int) BFD_RELOC_LO16); | |
4882 | macro_build (p, &icnt, (expressionS *) NULL, "dsll32", | |
4883 | "d,w,<", tempreg, tempreg, 0); | |
3a482fd5 MR |
4884 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
4885 | "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
4886 | used_at = 1; |
4887 | } | |
4888 | else | |
4889 | { | |
4890 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4891 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
4892 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4893 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
4894 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<", | |
4895 | tempreg, tempreg, 16); | |
4896 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4897 | tempreg, tempreg, (int) BFD_RELOC_HI16_S); | |
4898 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<", | |
4899 | tempreg, tempreg, 16); | |
4900 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4901 | tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4902 | } | |
4903 | } | |
4904 | else | |
4905 | { | |
4906 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
4907 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4908 | { | |
4909 | frag_grow (20); | |
4910 | macro_build ((char *) NULL, &icnt, &offset_expr, "addiu", | |
c9914766 TS |
4911 | "t,r,j", tempreg, mips_gp_register, |
4912 | (int) BFD_RELOC_GPREL16); | |
98d3f06f KH |
4913 | p = frag_var (rs_machine_dependent, 8, 0, |
4914 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
4915 | mips_opts.warn_about_macros), | |
4916 | offset_expr.X_add_symbol, 0, NULL); | |
4917 | } | |
4918 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4919 | if (p != NULL) | |
4920 | p += 4; | |
4921 | macro_build (p, &icnt, &offset_expr, "addiu", | |
4922 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4923 | } | |
252b5132 RH |
4924 | } |
4925 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
4926 | { | |
9117d219 NC |
4927 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4928 | ||
252b5132 RH |
4929 | /* If this is a reference to an external symbol, and there |
4930 | is no constant, we want | |
4931 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9117d219 NC |
4932 | or if tempreg is PIC_CALL_REG |
4933 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
252b5132 RH |
4934 | For a local symbol, we want |
4935 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4936 | nop | |
4937 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4938 | ||
4939 | If we have a small constant, and this is a reference to | |
4940 | an external symbol, we want | |
4941 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4942 | nop | |
4943 | addiu $tempreg,$tempreg,<constant> | |
4944 | For a local symbol, we want the same instruction | |
4945 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4946 | addiu instruction. | |
4947 | ||
4948 | If we have a large constant, and this is a reference to | |
4949 | an external symbol, we want | |
4950 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4951 | lui $at,<hiconstant> | |
4952 | addiu $at,$at,<loconstant> | |
4953 | addu $tempreg,$tempreg,$at | |
4954 | For a local symbol, we want the same instruction | |
4955 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd SC |
4956 | addiu instruction. |
4957 | ||
4958 | For NewABI, we want for local or external data addresses | |
4959 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
4960 | For a local function symbol, we want | |
4961 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
4962 | nop | |
4963 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
4964 | */ | |
4965 | ||
252b5132 RH |
4966 | expr1.X_add_number = offset_expr.X_add_number; |
4967 | offset_expr.X_add_number = 0; | |
4968 | frag_grow (32); | |
9117d219 NC |
4969 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
4970 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
ed6fb7bd SC |
4971 | else if (HAVE_NEWABI) |
4972 | lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP; | |
4d34fb5f TS |
4973 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4974 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
c9914766 | 4975 | "t,o(b)", tempreg, lw_reloc_type, mips_gp_register); |
252b5132 RH |
4976 | if (expr1.X_add_number == 0) |
4977 | { | |
4978 | int off; | |
f9419b05 | 4979 | char *p; |
252b5132 RH |
4980 | |
4981 | if (breg == 0) | |
4982 | off = 0; | |
4983 | else | |
4984 | { | |
4985 | /* We're going to put in an addu instruction using | |
4986 | tempreg, so we may as well insert the nop right | |
4987 | now. */ | |
4988 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4989 | "nop", ""); | |
4990 | off = 4; | |
4991 | } | |
4992 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4993 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4994 | (breg == 0 | |
4995 | ? mips_opts.warn_about_macros | |
4996 | : 0)), | |
c4e7957c | 4997 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
4998 | if (breg == 0) |
4999 | { | |
5000 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5001 | p += 4; | |
5002 | } | |
5003 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 5004 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5005 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5006 | /* FIXME: If breg == 0, and the next instruction uses | |
5007 | $tempreg, then if this variant case is used an extra | |
5008 | nop will be generated. */ | |
5009 | } | |
5010 | else if (expr1.X_add_number >= -0x8000 | |
5011 | && expr1.X_add_number < 0x8000) | |
5012 | { | |
5013 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5014 | "nop", ""); | |
5015 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 5016 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 | 5017 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
c4e7957c TS |
5018 | frag_var (rs_machine_dependent, 0, 0, |
5019 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
5020 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
5021 | } |
5022 | else | |
5023 | { | |
5024 | int off1; | |
5025 | ||
5026 | /* If we are going to add in a base register, and the | |
5027 | target register and the base register are the same, | |
5028 | then we are using AT as a temporary register. Since | |
5029 | we want to load the constant into AT, we add our | |
5030 | current AT (from the global offset table) and the | |
5031 | register into the register now, and pretend we were | |
5032 | not using a base register. */ | |
5033 | if (breg != treg) | |
5034 | off1 = 0; | |
5035 | else | |
5036 | { | |
5037 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5038 | "nop", ""); | |
5039 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5040 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5041 | "d,v,t", treg, AT, breg); |
5042 | breg = 0; | |
5043 | tempreg = treg; | |
5044 | off1 = -8; | |
5045 | } | |
5046 | ||
5047 | /* Set mips_optimize around the lui instruction to avoid | |
5048 | inserting an unnecessary nop after the lw. */ | |
5049 | hold_mips_optimize = mips_optimize; | |
5050 | mips_optimize = 2; | |
c4e7957c | 5051 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
5052 | mips_optimize = hold_mips_optimize; |
5053 | ||
5054 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 5055 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5056 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
5057 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5058 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 5059 | "d,v,t", tempreg, tempreg, AT); |
c4e7957c TS |
5060 | frag_var (rs_machine_dependent, 0, 0, |
5061 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
5062 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
5063 | used_at = 1; |
5064 | } | |
5065 | } | |
5066 | else if (mips_pic == SVR4_PIC) | |
5067 | { | |
5068 | int gpdel; | |
f9419b05 | 5069 | char *p; |
9117d219 NC |
5070 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5071 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5072 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5073 | |
5074 | /* This is the large GOT case. If this is a reference to an | |
5075 | external symbol, and there is no constant, we want | |
5076 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5077 | addu $tempreg,$tempreg,$gp | |
5078 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9117d219 NC |
5079 | or if tempreg is PIC_CALL_REG |
5080 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5081 | addu $tempreg,$tempreg,$gp | |
5082 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5083 | For a local symbol, we want |
5084 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5085 | nop | |
5086 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5087 | ||
5088 | If we have a small constant, and this is a reference to | |
5089 | an external symbol, we want | |
5090 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5091 | addu $tempreg,$tempreg,$gp | |
5092 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5093 | nop | |
5094 | addiu $tempreg,$tempreg,<constant> | |
5095 | For a local symbol, we want | |
5096 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5097 | nop | |
5098 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5099 | ||
5100 | If we have a large constant, and this is a reference to | |
5101 | an external symbol, we want | |
5102 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5103 | addu $tempreg,$tempreg,$gp | |
5104 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5105 | lui $at,<hiconstant> | |
5106 | addiu $at,$at,<loconstant> | |
5107 | addu $tempreg,$tempreg,$at | |
5108 | For a local symbol, we want | |
5109 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5110 | lui $at,<hiconstant> | |
5111 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5112 | addu $tempreg,$tempreg,$at | |
438c16b8 | 5113 | |
ed6fb7bd SC |
5114 | For NewABI, we want for local data addresses |
5115 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
438c16b8 | 5116 | */ |
438c16b8 | 5117 | |
252b5132 RH |
5118 | expr1.X_add_number = offset_expr.X_add_number; |
5119 | offset_expr.X_add_number = 0; | |
5120 | frag_grow (52); | |
f7ea7ef2 | 5121 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
5122 | gpdel = 4; |
5123 | else | |
5124 | gpdel = 0; | |
9117d219 NC |
5125 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
5126 | { | |
5127 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5128 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5129 | } | |
252b5132 | 5130 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
9117d219 | 5131 | tempreg, lui_reloc_type); |
252b5132 | 5132 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
ca4e0257 | 5133 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 5134 | "d,v,t", tempreg, tempreg, mips_gp_register); |
252b5132 | 5135 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4d34fb5f | 5136 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
9117d219 | 5137 | "t,o(b)", tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5138 | if (expr1.X_add_number == 0) |
5139 | { | |
5140 | int off; | |
5141 | ||
5142 | if (breg == 0) | |
5143 | off = 0; | |
5144 | else | |
5145 | { | |
5146 | /* We're going to put in an addu instruction using | |
5147 | tempreg, so we may as well insert the nop right | |
5148 | now. */ | |
5149 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5150 | "nop", ""); | |
5151 | off = 4; | |
5152 | } | |
5153 | ||
5154 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5155 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
5156 | 8 + gpdel, 0, | |
5157 | (breg == 0 | |
5158 | ? mips_opts.warn_about_macros | |
5159 | : 0)), | |
c4e7957c | 5160 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5161 | } |
5162 | else if (expr1.X_add_number >= -0x8000 | |
5163 | && expr1.X_add_number < 0x8000) | |
5164 | { | |
5165 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5166 | "nop", ""); | |
5167 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 5168 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5169 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5170 | ||
5171 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5172 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
5173 | (breg == 0 | |
5174 | ? mips_opts.warn_about_macros | |
5175 | : 0)), | |
c4e7957c | 5176 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5177 | } |
5178 | else | |
5179 | { | |
5180 | int adj, dreg; | |
5181 | ||
5182 | /* If we are going to add in a base register, and the | |
5183 | target register and the base register are the same, | |
5184 | then we are using AT as a temporary register. Since | |
5185 | we want to load the constant into AT, we add our | |
5186 | current AT (from the global offset table) and the | |
5187 | register into the register now, and pretend we were | |
5188 | not using a base register. */ | |
5189 | if (breg != treg) | |
5190 | { | |
5191 | adj = 0; | |
5192 | dreg = tempreg; | |
5193 | } | |
5194 | else | |
5195 | { | |
5196 | assert (tempreg == AT); | |
5197 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5198 | "nop", ""); | |
5199 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5200 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5201 | "d,v,t", treg, AT, breg); |
5202 | dreg = treg; | |
5203 | adj = 8; | |
5204 | } | |
5205 | ||
5206 | /* Set mips_optimize around the lui instruction to avoid | |
5207 | inserting an unnecessary nop after the lw. */ | |
5208 | hold_mips_optimize = mips_optimize; | |
5209 | mips_optimize = 2; | |
c4e7957c | 5210 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
5211 | mips_optimize = hold_mips_optimize; |
5212 | ||
5213 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 5214 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5215 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
5216 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5217 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5218 | "d,v,t", dreg, dreg, AT); |
5219 | ||
5220 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
5221 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
5222 | 8 + gpdel, 0, | |
5223 | (breg == 0 | |
5224 | ? mips_opts.warn_about_macros | |
5225 | : 0)), | |
c4e7957c | 5226 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5227 | |
5228 | used_at = 1; | |
5229 | } | |
5230 | ||
5231 | if (gpdel > 0) | |
5232 | { | |
5233 | /* This is needed because this instruction uses $gp, but | |
5234 | the first instruction on the main stream does not. */ | |
5235 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5236 | p += 4; | |
5237 | } | |
ed6fb7bd SC |
5238 | |
5239 | if (HAVE_NEWABI) | |
5240 | local_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP; | |
252b5132 | 5241 | macro_build (p, &icnt, &offset_expr, |
4d34fb5f | 5242 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
ed6fb7bd SC |
5243 | "t,o(b)", tempreg, |
5244 | local_reloc_type, | |
c9914766 | 5245 | mips_gp_register); |
252b5132 | 5246 | p += 4; |
ed6fb7bd SC |
5247 | if (expr1.X_add_number == 0 && HAVE_NEWABI) |
5248 | { | |
5249 | /* BFD_RELOC_MIPS_GOT_DISP is sufficient for newabi */ | |
5250 | } | |
5251 | else | |
5252 | if (expr1.X_add_number >= -0x8000 | |
252b5132 RH |
5253 | && expr1.X_add_number < 0x8000) |
5254 | { | |
5255 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5256 | p += 4; | |
5257 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 5258 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5259 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5260 | /* FIXME: If add_number is 0, and there was no base | |
5261 | register, the external symbol case ended with a load, | |
5262 | so if the symbol turns out to not be external, and | |
5263 | the next instruction uses tempreg, an unnecessary nop | |
5264 | will be inserted. */ | |
5265 | } | |
5266 | else | |
5267 | { | |
5268 | if (breg == treg) | |
5269 | { | |
5270 | /* We must add in the base register now, as in the | |
5271 | external symbol case. */ | |
5272 | assert (tempreg == AT); | |
5273 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5274 | p += 4; | |
5275 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5276 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5277 | "d,v,t", treg, AT, breg); |
5278 | p += 4; | |
5279 | tempreg = treg; | |
5280 | /* We set breg to 0 because we have arranged to add | |
5281 | it in in both cases. */ | |
5282 | breg = 0; | |
5283 | } | |
5284 | ||
5285 | macro_build_lui (p, &icnt, &expr1, AT); | |
5286 | p += 4; | |
5287 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 5288 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5289 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
5290 | p += 4; | |
5291 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5292 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5293 | "d,v,t", tempreg, tempreg, AT); |
5294 | p += 4; | |
5295 | } | |
5296 | } | |
5297 | else if (mips_pic == EMBEDDED_PIC) | |
5298 | { | |
5299 | /* We use | |
cdf6fd85 | 5300 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5301 | */ |
5302 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
c9914766 TS |
5303 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", |
5304 | tempreg, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
252b5132 RH |
5305 | } |
5306 | else | |
5307 | abort (); | |
5308 | ||
5309 | if (breg != 0) | |
4d34fb5f TS |
5310 | { |
5311 | char *s; | |
5312 | ||
5313 | if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
5314 | s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu"; | |
5315 | else | |
5316 | s = HAVE_64BIT_ADDRESSES ? "daddu" : "addu"; | |
5317 | ||
5318 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, | |
5319 | "d,v,t", treg, tempreg, breg); | |
5320 | } | |
252b5132 RH |
5321 | |
5322 | if (! used_at) | |
5323 | return; | |
5324 | ||
5325 | break; | |
5326 | ||
5327 | case M_J_A: | |
5328 | /* The j instruction may not be used in PIC code, since it | |
5329 | requires an absolute address. We convert it to a b | |
5330 | instruction. */ | |
5331 | if (mips_pic == NO_PIC) | |
5332 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); | |
5333 | else | |
5334 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
5335 | return; | |
5336 | ||
5337 | /* The jal instructions must be handled as macros because when | |
5338 | generating PIC code they expand to multi-instruction | |
5339 | sequences. Normally they are simple instructions. */ | |
5340 | case M_JAL_1: | |
5341 | dreg = RA; | |
5342 | /* Fall through. */ | |
5343 | case M_JAL_2: | |
5344 | if (mips_pic == NO_PIC | |
5345 | || mips_pic == EMBEDDED_PIC) | |
5346 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
5347 | "d,s", dreg, sreg); | |
5348 | else if (mips_pic == SVR4_PIC) | |
5349 | { | |
5350 | if (sreg != PIC_CALL_REG) | |
5351 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5352 | |
252b5132 RH |
5353 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
5354 | "d,s", dreg, sreg); | |
6478892d | 5355 | if (! HAVE_NEWABI) |
252b5132 | 5356 | { |
6478892d TS |
5357 | if (mips_cprestore_offset < 0) |
5358 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5359 | else | |
5360 | { | |
7a621144 DJ |
5361 | if (! mips_frame_reg_valid) |
5362 | { | |
5363 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5364 | /* Quiet this warning. */ | |
5365 | mips_frame_reg_valid = 1; | |
5366 | } | |
5367 | if (! mips_cprestore_valid) | |
5368 | { | |
5369 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5370 | /* Quiet this warning. */ | |
5371 | mips_cprestore_valid = 1; | |
5372 | } | |
6478892d | 5373 | expr1.X_add_number = mips_cprestore_offset; |
885add95 CD |
5374 | macro_build_ldst_constoffset ((char *) NULL, &icnt, &expr1, |
5375 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5376 | mips_gp_register, mips_frame_reg); | |
6478892d | 5377 | } |
252b5132 RH |
5378 | } |
5379 | } | |
5380 | else | |
5381 | abort (); | |
5382 | ||
5383 | return; | |
5384 | ||
5385 | case M_JAL_A: | |
5386 | if (mips_pic == NO_PIC) | |
5387 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
5388 | else if (mips_pic == SVR4_PIC) | |
5389 | { | |
f9419b05 TS |
5390 | char *p; |
5391 | ||
252b5132 RH |
5392 | /* If this is a reference to an external symbol, and we are |
5393 | using a small GOT, we want | |
5394 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5395 | nop | |
f9419b05 | 5396 | jalr $ra,$25 |
252b5132 RH |
5397 | nop |
5398 | lw $gp,cprestore($sp) | |
5399 | The cprestore value is set using the .cprestore | |
5400 | pseudo-op. If we are using a big GOT, we want | |
5401 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5402 | addu $25,$25,$gp | |
5403 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5404 | nop | |
f9419b05 | 5405 | jalr $ra,$25 |
252b5132 RH |
5406 | nop |
5407 | lw $gp,cprestore($sp) | |
5408 | If the symbol is not external, we want | |
5409 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5410 | nop | |
5411 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5412 | jalr $ra,$25 |
252b5132 | 5413 | nop |
438c16b8 TS |
5414 | lw $gp,cprestore($sp) |
5415 | For NewABI, we want | |
5416 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5417 | jalr $ra,$25 (BFD_RELOC_MIPS_JALR) | |
5418 | */ | |
5419 | if (HAVE_NEWABI) | |
252b5132 RH |
5420 | { |
5421 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5422 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 | 5423 | "t,o(b)", PIC_CALL_REG, |
438c16b8 TS |
5424 | (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
5425 | macro_build_jalr (icnt, &offset_expr); | |
252b5132 RH |
5426 | } |
5427 | else | |
5428 | { | |
438c16b8 TS |
5429 | frag_grow (40); |
5430 | if (! mips_big_got) | |
5431 | { | |
5432 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5433 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5434 | "t,o(b)", PIC_CALL_REG, | |
5435 | (int) BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
5436 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5437 | "nop", ""); | |
5438 | p = frag_var (rs_machine_dependent, 4, 0, | |
5439 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
5440 | offset_expr.X_add_symbol, 0, NULL); | |
5441 | } | |
252b5132 | 5442 | else |
252b5132 | 5443 | { |
438c16b8 TS |
5444 | int gpdel; |
5445 | ||
5446 | if (reg_needs_delay (mips_gp_register)) | |
5447 | gpdel = 4; | |
5448 | else | |
5449 | gpdel = 0; | |
5450 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", | |
5451 | "t,u", PIC_CALL_REG, | |
5452 | (int) BFD_RELOC_MIPS_CALL_HI16); | |
5453 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5454 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", | |
5455 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, | |
5456 | mips_gp_register); | |
5457 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5458 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5459 | "t,o(b)", PIC_CALL_REG, | |
5460 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
5461 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5462 | "nop", ""); | |
5463 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5464 | RELAX_ENCODE (16, 12 + gpdel, gpdel, | |
5465 | 8 + gpdel, 0, 0), | |
5466 | offset_expr.X_add_symbol, 0, NULL); | |
5467 | if (gpdel > 0) | |
5468 | { | |
5469 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5470 | p += 4; | |
5471 | } | |
5472 | macro_build (p, &icnt, &offset_expr, | |
5473 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5474 | "t,o(b)", PIC_CALL_REG, | |
5475 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
5476 | p += 4; | |
252b5132 RH |
5477 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
5478 | p += 4; | |
5479 | } | |
5480 | macro_build (p, &icnt, &offset_expr, | |
438c16b8 TS |
5481 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
5482 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
5483 | (int) BFD_RELOC_LO16); | |
5484 | macro_build_jalr (icnt, &offset_expr); | |
5485 | ||
6478892d TS |
5486 | if (mips_cprestore_offset < 0) |
5487 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5488 | else | |
5489 | { | |
7a621144 DJ |
5490 | if (! mips_frame_reg_valid) |
5491 | { | |
5492 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5493 | /* Quiet this warning. */ | |
5494 | mips_frame_reg_valid = 1; | |
5495 | } | |
5496 | if (! mips_cprestore_valid) | |
5497 | { | |
5498 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5499 | /* Quiet this warning. */ | |
5500 | mips_cprestore_valid = 1; | |
5501 | } | |
6478892d TS |
5502 | if (mips_opts.noreorder) |
5503 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
98d3f06f | 5504 | "nop", ""); |
6478892d | 5505 | expr1.X_add_number = mips_cprestore_offset; |
885add95 CD |
5506 | macro_build_ldst_constoffset ((char *) NULL, &icnt, &expr1, |
5507 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5508 | mips_gp_register, mips_frame_reg); | |
6478892d | 5509 | } |
252b5132 RH |
5510 | } |
5511 | } | |
5512 | else if (mips_pic == EMBEDDED_PIC) | |
5513 | { | |
5514 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
5515 | /* The linker may expand the call to a longer sequence which | |
5516 | uses $at, so we must break rather than return. */ | |
5517 | break; | |
5518 | } | |
5519 | else | |
5520 | abort (); | |
5521 | ||
5522 | return; | |
5523 | ||
5524 | case M_LB_AB: | |
5525 | s = "lb"; | |
5526 | goto ld; | |
5527 | case M_LBU_AB: | |
5528 | s = "lbu"; | |
5529 | goto ld; | |
5530 | case M_LH_AB: | |
5531 | s = "lh"; | |
5532 | goto ld; | |
5533 | case M_LHU_AB: | |
5534 | s = "lhu"; | |
5535 | goto ld; | |
5536 | case M_LW_AB: | |
5537 | s = "lw"; | |
5538 | goto ld; | |
5539 | case M_LWC0_AB: | |
5540 | s = "lwc0"; | |
bdaaa2e1 | 5541 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5542 | coproc = 1; |
5543 | goto ld; | |
5544 | case M_LWC1_AB: | |
5545 | s = "lwc1"; | |
bdaaa2e1 | 5546 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5547 | coproc = 1; |
5548 | goto ld; | |
5549 | case M_LWC2_AB: | |
5550 | s = "lwc2"; | |
bdaaa2e1 | 5551 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5552 | coproc = 1; |
5553 | goto ld; | |
5554 | case M_LWC3_AB: | |
5555 | s = "lwc3"; | |
bdaaa2e1 | 5556 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5557 | coproc = 1; |
5558 | goto ld; | |
5559 | case M_LWL_AB: | |
5560 | s = "lwl"; | |
5561 | lr = 1; | |
5562 | goto ld; | |
5563 | case M_LWR_AB: | |
5564 | s = "lwr"; | |
5565 | lr = 1; | |
5566 | goto ld; | |
5567 | case M_LDC1_AB: | |
ec68c924 | 5568 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5569 | { |
5570 | as_bad (_("opcode not supported on this processor")); | |
5571 | return; | |
5572 | } | |
5573 | s = "ldc1"; | |
bdaaa2e1 | 5574 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5575 | coproc = 1; |
5576 | goto ld; | |
5577 | case M_LDC2_AB: | |
5578 | s = "ldc2"; | |
bdaaa2e1 | 5579 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5580 | coproc = 1; |
5581 | goto ld; | |
5582 | case M_LDC3_AB: | |
5583 | s = "ldc3"; | |
bdaaa2e1 | 5584 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5585 | coproc = 1; |
5586 | goto ld; | |
5587 | case M_LDL_AB: | |
5588 | s = "ldl"; | |
5589 | lr = 1; | |
5590 | goto ld; | |
5591 | case M_LDR_AB: | |
5592 | s = "ldr"; | |
5593 | lr = 1; | |
5594 | goto ld; | |
5595 | case M_LL_AB: | |
5596 | s = "ll"; | |
5597 | goto ld; | |
5598 | case M_LLD_AB: | |
5599 | s = "lld"; | |
5600 | goto ld; | |
5601 | case M_LWU_AB: | |
5602 | s = "lwu"; | |
5603 | ld: | |
5604 | if (breg == treg || coproc || lr) | |
5605 | { | |
5606 | tempreg = AT; | |
5607 | used_at = 1; | |
5608 | } | |
5609 | else | |
5610 | { | |
5611 | tempreg = treg; | |
5612 | used_at = 0; | |
5613 | } | |
5614 | goto ld_st; | |
5615 | case M_SB_AB: | |
5616 | s = "sb"; | |
5617 | goto st; | |
5618 | case M_SH_AB: | |
5619 | s = "sh"; | |
5620 | goto st; | |
5621 | case M_SW_AB: | |
5622 | s = "sw"; | |
5623 | goto st; | |
5624 | case M_SWC0_AB: | |
5625 | s = "swc0"; | |
bdaaa2e1 | 5626 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5627 | coproc = 1; |
5628 | goto st; | |
5629 | case M_SWC1_AB: | |
5630 | s = "swc1"; | |
bdaaa2e1 | 5631 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5632 | coproc = 1; |
5633 | goto st; | |
5634 | case M_SWC2_AB: | |
5635 | s = "swc2"; | |
bdaaa2e1 | 5636 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5637 | coproc = 1; |
5638 | goto st; | |
5639 | case M_SWC3_AB: | |
5640 | s = "swc3"; | |
bdaaa2e1 | 5641 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5642 | coproc = 1; |
5643 | goto st; | |
5644 | case M_SWL_AB: | |
5645 | s = "swl"; | |
5646 | goto st; | |
5647 | case M_SWR_AB: | |
5648 | s = "swr"; | |
5649 | goto st; | |
5650 | case M_SC_AB: | |
5651 | s = "sc"; | |
5652 | goto st; | |
5653 | case M_SCD_AB: | |
5654 | s = "scd"; | |
5655 | goto st; | |
5656 | case M_SDC1_AB: | |
ec68c924 | 5657 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5658 | { |
5659 | as_bad (_("opcode not supported on this processor")); | |
5660 | return; | |
5661 | } | |
5662 | s = "sdc1"; | |
5663 | coproc = 1; | |
bdaaa2e1 | 5664 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5665 | goto st; |
5666 | case M_SDC2_AB: | |
5667 | s = "sdc2"; | |
bdaaa2e1 | 5668 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5669 | coproc = 1; |
5670 | goto st; | |
5671 | case M_SDC3_AB: | |
5672 | s = "sdc3"; | |
bdaaa2e1 | 5673 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5674 | coproc = 1; |
5675 | goto st; | |
5676 | case M_SDL_AB: | |
5677 | s = "sdl"; | |
5678 | goto st; | |
5679 | case M_SDR_AB: | |
5680 | s = "sdr"; | |
5681 | st: | |
5682 | tempreg = AT; | |
5683 | used_at = 1; | |
5684 | ld_st: | |
bdaaa2e1 | 5685 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5686 | if (mask == M_LWC1_AB |
5687 | || mask == M_SWC1_AB | |
5688 | || mask == M_LDC1_AB | |
5689 | || mask == M_SDC1_AB | |
5690 | || mask == M_L_DAB | |
5691 | || mask == M_S_DAB) | |
5692 | fmt = "T,o(b)"; | |
5693 | else if (coproc) | |
5694 | fmt = "E,o(b)"; | |
5695 | else | |
5696 | fmt = "t,o(b)"; | |
5697 | ||
afdbd6d0 CD |
5698 | /* For embedded PIC, we allow loads where the offset is calculated |
5699 | by subtracting a symbol in the current segment from an unknown | |
5700 | symbol, relative to a base register, e.g.: | |
5701 | <op> $treg, <sym>-<localsym>($breg) | |
5702 | This is used by the compiler for switch statements. */ | |
76b3015f | 5703 | if (mips_pic == EMBEDDED_PIC |
afdbd6d0 CD |
5704 | && offset_expr.X_op == O_subtract |
5705 | && (symbol_constant_p (offset_expr.X_op_symbol) | |
5706 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg | |
5707 | : (symbol_equated_p (offset_expr.X_op_symbol) | |
5708 | && (S_GET_SEGMENT | |
5709 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
5710 | ->X_add_symbol) | |
5711 | == now_seg))) | |
5712 | && breg != 0 | |
5713 | && (offset_expr.X_add_number == 0 | |
5714 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
5715 | { | |
5716 | /* For this case, we output the instructions: | |
5717 | lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S) | |
5718 | addiu $tempreg,$tempreg,$breg | |
5719 | <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16) | |
5720 | If the relocation would fit entirely in 16 bits, it would be | |
5721 | nice to emit: | |
5722 | <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16) | |
5723 | instead, but that seems quite difficult. */ | |
5724 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5725 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
5726 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5727 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
5728 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
5729 | ? "addu" : "daddu"), | |
5730 | "d,v,t", tempreg, tempreg, breg); | |
5731 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg, | |
5732 | (int) BFD_RELOC_PCREL_LO16, tempreg); | |
5733 | if (! used_at) | |
5734 | return; | |
5735 | break; | |
5736 | } | |
5737 | ||
252b5132 RH |
5738 | if (offset_expr.X_op != O_constant |
5739 | && offset_expr.X_op != O_symbol) | |
5740 | { | |
5741 | as_bad (_("expression too complex")); | |
5742 | offset_expr.X_op = O_constant; | |
5743 | } | |
5744 | ||
5745 | /* A constant expression in PIC code can be handled just as it | |
5746 | is in non PIC code. */ | |
5747 | if (mips_pic == NO_PIC | |
5748 | || offset_expr.X_op == O_constant) | |
5749 | { | |
f9419b05 TS |
5750 | char *p; |
5751 | ||
252b5132 RH |
5752 | /* If this is a reference to a GP relative symbol, and there |
5753 | is no base register, we want | |
cdf6fd85 | 5754 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5755 | Otherwise, if there is no base register, we want |
5756 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5757 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5758 | If we have a constant, we need two instructions anyhow, | |
5759 | so we always use the latter form. | |
5760 | ||
5761 | If we have a base register, and this is a reference to a | |
5762 | GP relative symbol, we want | |
5763 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5764 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5765 | Otherwise we want |
5766 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5767 | addu $tempreg,$tempreg,$breg | |
5768 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5769 | With a constant we always use the latter case. |
76b3015f | 5770 | |
d6bc6245 TS |
5771 | With 64bit address space and no base register and $at usable, |
5772 | we want | |
5773 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5774 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5775 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5776 | dsll32 $tempreg,0 | |
5777 | daddu $tempreg,$at | |
5778 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5779 | If we have a base register, we want | |
5780 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5781 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5782 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5783 | daddu $at,$breg | |
5784 | dsll32 $tempreg,0 | |
5785 | daddu $tempreg,$at | |
5786 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5787 | ||
5788 | Without $at we can't generate the optimal path for superscalar | |
5789 | processors here since this would require two temporary registers. | |
5790 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5791 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5792 | dsll $tempreg,16 | |
5793 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5794 | dsll $tempreg,16 | |
5795 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5796 | If we have a base register, we want | |
5797 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5798 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5799 | dsll $tempreg,16 | |
5800 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5801 | dsll $tempreg,16 | |
5802 | daddu $tempreg,$tempreg,$breg | |
5803 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 CD |
5804 | |
5805 | If we have 64-bit addresses, as an optimization, for | |
5806 | addresses which are 32-bit constants (e.g. kseg0/kseg1 | |
5807 | addresses) we fall back to the 32-bit address generation | |
78d32a17 MR |
5808 | mechanism since it is more efficient. Note that due to |
5809 | the signed offset used by memory operations, the 32-bit | |
5810 | range is shifted down by 32768 here. This code should | |
6373ee54 CD |
5811 | probably attempt to generate 64-bit constants more |
5812 | efficiently in general. | |
d6bc6245 | 5813 | */ |
6373ee54 CD |
5814 | if (HAVE_64BIT_ADDRESSES |
5815 | && !(offset_expr.X_op == O_constant | |
78d32a17 | 5816 | && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) |
d6bc6245 TS |
5817 | { |
5818 | p = NULL; | |
5819 | ||
5820 | /* We don't do GP optimization for now because RELAX_ENCODE can't | |
5821 | hold the data for such large chunks. */ | |
5822 | ||
460597ba | 5823 | if (used_at == 0 && ! mips_opts.noat) |
d6bc6245 TS |
5824 | { |
5825 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5826 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
5827 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5828 | AT, (int) BFD_RELOC_HI16_S); | |
5829 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
5830 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
5831 | if (breg != 0) | |
2396cfb9 TS |
5832 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
5833 | "d,v,t", AT, AT, breg); | |
5834 | macro_build (p, &icnt, (expressionS *) NULL, "dsll32", | |
5835 | "d,w,<", tempreg, tempreg, 0); | |
5836 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", | |
5837 | "d,v,t", tempreg, tempreg, AT); | |
d6bc6245 TS |
5838 | macro_build (p, &icnt, &offset_expr, s, |
5839 | fmt, treg, (int) BFD_RELOC_LO16, tempreg); | |
5840 | used_at = 1; | |
5841 | } | |
5842 | else | |
5843 | { | |
5844 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5845 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
5846 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
5847 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
2396cfb9 TS |
5848 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", |
5849 | "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 TS |
5850 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
5851 | tempreg, tempreg, (int) BFD_RELOC_HI16_S); | |
2396cfb9 TS |
5852 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", |
5853 | "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 5854 | if (breg != 0) |
2396cfb9 TS |
5855 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
5856 | "d,v,t", tempreg, tempreg, breg); | |
d6bc6245 TS |
5857 | macro_build (p, &icnt, &offset_expr, s, |
5858 | fmt, treg, (int) BFD_RELOC_LO16, tempreg); | |
5859 | } | |
5860 | ||
5861 | return; | |
5862 | } | |
76b3015f | 5863 | |
252b5132 RH |
5864 | if (breg == 0) |
5865 | { | |
e7d556df | 5866 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
5867 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5868 | p = NULL; | |
5869 | else | |
5870 | { | |
5871 | frag_grow (20); | |
5872 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
c9914766 TS |
5873 | treg, (int) BFD_RELOC_GPREL16, |
5874 | mips_gp_register); | |
252b5132 RH |
5875 | p = frag_var (rs_machine_dependent, 8, 0, |
5876 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
5877 | (mips_opts.warn_about_macros | |
5878 | || (used_at | |
5879 | && mips_opts.noat))), | |
956cd1d6 | 5880 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5881 | used_at = 0; |
5882 | } | |
5883 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5884 | if (p != NULL) | |
5885 | p += 4; | |
5886 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5887 | (int) BFD_RELOC_LO16, tempreg); | |
5888 | } | |
5889 | else | |
5890 | { | |
e7d556df | 5891 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
5892 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5893 | p = NULL; | |
5894 | else | |
5895 | { | |
5896 | frag_grow (28); | |
5897 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5898 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 5899 | "d,v,t", tempreg, breg, mips_gp_register); |
252b5132 | 5900 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
cdf6fd85 | 5901 | treg, (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
5902 | p = frag_var (rs_machine_dependent, 12, 0, |
5903 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
956cd1d6 | 5904 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5905 | } |
5906 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5907 | if (p != NULL) | |
5908 | p += 4; | |
5909 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5910 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5911 | "d,v,t", tempreg, tempreg, breg); |
5912 | if (p != NULL) | |
5913 | p += 4; | |
5914 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5915 | (int) BFD_RELOC_LO16, tempreg); | |
5916 | } | |
5917 | } | |
5918 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
5919 | { | |
f9419b05 | 5920 | char *p; |
ed6fb7bd | 5921 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 5922 | |
252b5132 RH |
5923 | /* If this is a reference to an external symbol, we want |
5924 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5925 | nop | |
5926 | <op> $treg,0($tempreg) | |
5927 | Otherwise we want | |
5928 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5929 | nop | |
5930 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5931 | <op> $treg,0($tempreg) | |
ed6fb7bd SC |
5932 | If we have NewABI, we want |
5933 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
252b5132 RH |
5934 | If there is a base register, we add it to $tempreg before |
5935 | the <op>. If there is a constant, we stick it in the | |
5936 | <op> instruction. We don't handle constants larger than | |
5937 | 16 bits, because we have no way to load the upper 16 bits | |
5938 | (actually, we could handle them for the subset of cases | |
5939 | in which we are not using $at). */ | |
5940 | assert (offset_expr.X_op == O_symbol); | |
5941 | expr1.X_add_number = offset_expr.X_add_number; | |
5942 | offset_expr.X_add_number = 0; | |
ed6fb7bd SC |
5943 | if (HAVE_NEWABI) |
5944 | lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP; | |
252b5132 RH |
5945 | if (expr1.X_add_number < -0x8000 |
5946 | || expr1.X_add_number >= 0x8000) | |
5947 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5948 | frag_grow (20); | |
5949 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
c9914766 | 5950 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", tempreg, |
ed6fb7bd | 5951 | (int) lw_reloc_type, mips_gp_register); |
252b5132 | 5952 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
bdaaa2e1 | 5953 | p = frag_var (rs_machine_dependent, 4, 0, |
252b5132 | 5954 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), |
c4e7957c | 5955 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 | 5956 | macro_build (p, &icnt, &offset_expr, |
ca4e0257 | 5957 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5958 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5959 | if (breg != 0) | |
5960 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5961 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5962 | "d,v,t", tempreg, tempreg, breg); |
5963 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5964 | (int) BFD_RELOC_LO16, tempreg); | |
5965 | } | |
5966 | else if (mips_pic == SVR4_PIC) | |
5967 | { | |
5968 | int gpdel; | |
f9419b05 | 5969 | char *p; |
252b5132 RH |
5970 | |
5971 | /* If this is a reference to an external symbol, we want | |
5972 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5973 | addu $tempreg,$tempreg,$gp | |
5974 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5975 | <op> $treg,0($tempreg) | |
5976 | Otherwise we want | |
5977 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5978 | nop | |
5979 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5980 | <op> $treg,0($tempreg) | |
5981 | If there is a base register, we add it to $tempreg before | |
5982 | the <op>. If there is a constant, we stick it in the | |
5983 | <op> instruction. We don't handle constants larger than | |
5984 | 16 bits, because we have no way to load the upper 16 bits | |
5985 | (actually, we could handle them for the subset of cases | |
438c16b8 TS |
5986 | in which we are not using $at). |
5987 | ||
5988 | For NewABI, we want | |
5989 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5990 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5991 | <op> $treg,0($tempreg) | |
5992 | */ | |
252b5132 RH |
5993 | assert (offset_expr.X_op == O_symbol); |
5994 | expr1.X_add_number = offset_expr.X_add_number; | |
5995 | offset_expr.X_add_number = 0; | |
5996 | if (expr1.X_add_number < -0x8000 | |
5997 | || expr1.X_add_number >= 0x8000) | |
5998 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
438c16b8 TS |
5999 | if (HAVE_NEWABI) |
6000 | { | |
6001 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
6002 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
6003 | "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE, | |
6004 | mips_gp_register); | |
6005 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
6006 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
6007 | "t,r,j", tempreg, tempreg, | |
6008 | BFD_RELOC_MIPS_GOT_OFST); | |
6009 | if (breg != 0) | |
6010 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6011 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", | |
6012 | "d,v,t", tempreg, tempreg, breg); | |
6013 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
6014 | (int) BFD_RELOC_LO16, tempreg); | |
6015 | ||
6016 | if (! used_at) | |
6017 | return; | |
6018 | ||
6019 | break; | |
6020 | } | |
f7ea7ef2 | 6021 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
6022 | gpdel = 4; |
6023 | else | |
6024 | gpdel = 0; | |
6025 | frag_grow (36); | |
6026 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
6027 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
6028 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6029 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 6030 | "d,v,t", tempreg, tempreg, mips_gp_register); |
252b5132 | 6031 | macro_build ((char *) NULL, &icnt, &offset_expr, |
ca4e0257 | 6032 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
6033 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
6034 | tempreg); | |
6035 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
6036 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
c4e7957c | 6037 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6038 | if (gpdel > 0) |
6039 | { | |
6040 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6041 | p += 4; | |
6042 | } | |
6043 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 6044 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
c9914766 TS |
6045 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, |
6046 | mips_gp_register); | |
252b5132 RH |
6047 | p += 4; |
6048 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6049 | p += 4; | |
6050 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 6051 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
6052 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
6053 | if (breg != 0) | |
6054 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6055 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6056 | "d,v,t", tempreg, tempreg, breg); |
6057 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
6058 | (int) BFD_RELOC_LO16, tempreg); | |
6059 | } | |
6060 | else if (mips_pic == EMBEDDED_PIC) | |
6061 | { | |
6062 | /* If there is no base register, we want | |
cdf6fd85 | 6063 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6064 | If there is a base register, we want |
6065 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6066 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6067 | */ |
6068 | assert (offset_expr.X_op == O_symbol); | |
6069 | if (breg == 0) | |
6070 | { | |
6071 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
c9914766 | 6072 | treg, (int) BFD_RELOC_GPREL16, mips_gp_register); |
252b5132 RH |
6073 | used_at = 0; |
6074 | } | |
6075 | else | |
6076 | { | |
6077 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6078 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 6079 | "d,v,t", tempreg, breg, mips_gp_register); |
252b5132 | 6080 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
cdf6fd85 | 6081 | treg, (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6082 | } |
6083 | } | |
6084 | else | |
6085 | abort (); | |
6086 | ||
6087 | if (! used_at) | |
6088 | return; | |
6089 | ||
6090 | break; | |
6091 | ||
6092 | case M_LI: | |
6093 | case M_LI_S: | |
6094 | load_register (&icnt, treg, &imm_expr, 0); | |
6095 | return; | |
6096 | ||
6097 | case M_DLI: | |
6098 | load_register (&icnt, treg, &imm_expr, 1); | |
6099 | return; | |
6100 | ||
6101 | case M_LI_SS: | |
6102 | if (imm_expr.X_op == O_constant) | |
6103 | { | |
6104 | load_register (&icnt, AT, &imm_expr, 0); | |
6105 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6106 | "mtc1", "t,G", AT, treg); | |
6107 | break; | |
6108 | } | |
6109 | else | |
6110 | { | |
6111 | assert (offset_expr.X_op == O_symbol | |
6112 | && strcmp (segment_name (S_GET_SEGMENT | |
6113 | (offset_expr.X_add_symbol)), | |
6114 | ".lit4") == 0 | |
6115 | && offset_expr.X_add_number == 0); | |
6116 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
c9914766 | 6117 | treg, (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
252b5132 RH |
6118 | return; |
6119 | } | |
6120 | ||
6121 | case M_LI_D: | |
ca4e0257 RS |
6122 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6123 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6124 | order 32 bits of the value and the low order 32 bits are either | |
6125 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6126 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6127 | { | |
ca4e0257 | 6128 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6129 | load_register (&icnt, treg, &imm_expr, 1); |
6130 | else | |
6131 | { | |
6132 | int hreg, lreg; | |
6133 | ||
6134 | if (target_big_endian) | |
6135 | { | |
6136 | hreg = treg; | |
6137 | lreg = treg + 1; | |
6138 | } | |
6139 | else | |
6140 | { | |
6141 | hreg = treg + 1; | |
6142 | lreg = treg; | |
6143 | } | |
6144 | ||
6145 | if (hreg <= 31) | |
6146 | load_register (&icnt, hreg, &imm_expr, 0); | |
6147 | if (lreg <= 31) | |
6148 | { | |
6149 | if (offset_expr.X_op == O_absent) | |
ea1fb5dc | 6150 | move_register (&icnt, lreg, 0); |
252b5132 RH |
6151 | else |
6152 | { | |
6153 | assert (offset_expr.X_op == O_constant); | |
6154 | load_register (&icnt, lreg, &offset_expr, 0); | |
6155 | } | |
6156 | } | |
6157 | } | |
6158 | return; | |
6159 | } | |
6160 | ||
6161 | /* We know that sym is in the .rdata section. First we get the | |
6162 | upper 16 bits of the address. */ | |
6163 | if (mips_pic == NO_PIC) | |
6164 | { | |
956cd1d6 | 6165 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 RH |
6166 | } |
6167 | else if (mips_pic == SVR4_PIC) | |
6168 | { | |
6169 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 6170 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
c9914766 TS |
6171 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, |
6172 | mips_gp_register); | |
252b5132 RH |
6173 | } |
6174 | else if (mips_pic == EMBEDDED_PIC) | |
6175 | { | |
6176 | /* For embedded PIC we pick up the entire address off $gp in | |
6177 | a single instruction. */ | |
6178 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
c9914766 TS |
6179 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", AT, |
6180 | mips_gp_register, (int) BFD_RELOC_GPREL16); | |
252b5132 RH |
6181 | offset_expr.X_op = O_constant; |
6182 | offset_expr.X_add_number = 0; | |
6183 | } | |
6184 | else | |
6185 | abort (); | |
bdaaa2e1 | 6186 | |
252b5132 | 6187 | /* Now we load the register(s). */ |
ca4e0257 | 6188 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6189 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
6190 | treg, (int) BFD_RELOC_LO16, AT); | |
6191 | else | |
6192 | { | |
6193 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
6194 | treg, (int) BFD_RELOC_LO16, AT); | |
f9419b05 | 6195 | if (treg != RA) |
252b5132 RH |
6196 | { |
6197 | /* FIXME: How in the world do we deal with the possible | |
6198 | overflow here? */ | |
6199 | offset_expr.X_add_number += 4; | |
6200 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
6201 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
6202 | } | |
6203 | } | |
6204 | ||
6205 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
6206 | does not become a variant frag. */ | |
6207 | frag_wane (frag_now); | |
6208 | frag_new (0); | |
6209 | ||
6210 | break; | |
6211 | ||
6212 | case M_LI_DD: | |
ca4e0257 RS |
6213 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6214 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6215 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6216 | the value and the low order 32 bits are either zero or in | |
6217 | OFFSET_EXPR. */ | |
252b5132 RH |
6218 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6219 | { | |
ca4e0257 RS |
6220 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS); |
6221 | if (HAVE_64BIT_FPRS) | |
6222 | { | |
6223 | assert (HAVE_64BIT_GPRS); | |
6224 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6225 | "dmtc1", "t,S", AT, treg); | |
6226 | } | |
252b5132 RH |
6227 | else |
6228 | { | |
6229 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6230 | "mtc1", "t,G", AT, treg + 1); | |
6231 | if (offset_expr.X_op == O_absent) | |
6232 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6233 | "mtc1", "t,G", 0, treg); | |
6234 | else | |
6235 | { | |
6236 | assert (offset_expr.X_op == O_constant); | |
6237 | load_register (&icnt, AT, &offset_expr, 0); | |
6238 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6239 | "mtc1", "t,G", AT, treg); | |
6240 | } | |
6241 | } | |
6242 | break; | |
6243 | } | |
6244 | ||
6245 | assert (offset_expr.X_op == O_symbol | |
6246 | && offset_expr.X_add_number == 0); | |
6247 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6248 | if (strcmp (s, ".lit8") == 0) | |
6249 | { | |
e7af610e | 6250 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6251 | { |
6252 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
c9914766 TS |
6253 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, |
6254 | mips_gp_register); | |
252b5132 RH |
6255 | return; |
6256 | } | |
c9914766 | 6257 | breg = mips_gp_register; |
252b5132 RH |
6258 | r = BFD_RELOC_MIPS_LITERAL; |
6259 | goto dob; | |
6260 | } | |
6261 | else | |
6262 | { | |
6263 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
6264 | if (mips_pic == SVR4_PIC) | |
6265 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 6266 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
c9914766 TS |
6267 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, |
6268 | mips_gp_register); | |
252b5132 RH |
6269 | else |
6270 | { | |
6271 | /* FIXME: This won't work for a 64 bit address. */ | |
956cd1d6 | 6272 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 | 6273 | } |
bdaaa2e1 | 6274 | |
e7af610e | 6275 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6276 | { |
6277 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
6278 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); | |
6279 | ||
6280 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
6281 | that this does not become a variant frag. */ | |
6282 | frag_wane (frag_now); | |
6283 | frag_new (0); | |
6284 | ||
6285 | break; | |
6286 | } | |
6287 | breg = AT; | |
6288 | r = BFD_RELOC_LO16; | |
6289 | goto dob; | |
6290 | } | |
6291 | ||
6292 | case M_L_DOB: | |
ec68c924 | 6293 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6294 | { |
6295 | as_bad (_("opcode not supported on this processor")); | |
6296 | return; | |
6297 | } | |
6298 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6299 | to adjust when loading from memory. */ | |
6300 | r = BFD_RELOC_LO16; | |
6301 | dob: | |
e7af610e | 6302 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6303 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
6304 | target_big_endian ? treg + 1 : treg, | |
6305 | (int) r, breg); | |
6306 | /* FIXME: A possible overflow which I don't know how to deal | |
6307 | with. */ | |
6308 | offset_expr.X_add_number += 4; | |
6309 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
6310 | target_big_endian ? treg : treg + 1, | |
6311 | (int) r, breg); | |
6312 | ||
6313 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
6314 | does not become a variant frag. */ | |
6315 | frag_wane (frag_now); | |
6316 | frag_new (0); | |
6317 | ||
6318 | if (breg != AT) | |
6319 | return; | |
6320 | break; | |
6321 | ||
6322 | case M_L_DAB: | |
6323 | /* | |
6324 | * The MIPS assembler seems to check for X_add_number not | |
6325 | * being double aligned and generating: | |
6326 | * lui at,%hi(foo+1) | |
6327 | * addu at,at,v1 | |
6328 | * addiu at,at,%lo(foo+1) | |
6329 | * lwc1 f2,0(at) | |
6330 | * lwc1 f3,4(at) | |
6331 | * But, the resulting address is the same after relocation so why | |
6332 | * generate the extra instruction? | |
6333 | */ | |
ec68c924 | 6334 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6335 | { |
6336 | as_bad (_("opcode not supported on this processor")); | |
6337 | return; | |
6338 | } | |
bdaaa2e1 | 6339 | /* Itbl support may require additional care here. */ |
252b5132 | 6340 | coproc = 1; |
e7af610e | 6341 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6342 | { |
6343 | s = "ldc1"; | |
6344 | goto ld; | |
6345 | } | |
6346 | ||
6347 | s = "lwc1"; | |
6348 | fmt = "T,o(b)"; | |
6349 | goto ldd_std; | |
6350 | ||
6351 | case M_S_DAB: | |
ec68c924 | 6352 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6353 | { |
6354 | as_bad (_("opcode not supported on this processor")); | |
6355 | return; | |
6356 | } | |
6357 | ||
e7af610e | 6358 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6359 | { |
6360 | s = "sdc1"; | |
6361 | goto st; | |
6362 | } | |
6363 | ||
6364 | s = "swc1"; | |
6365 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6366 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6367 | coproc = 1; |
6368 | goto ldd_std; | |
6369 | ||
6370 | case M_LD_AB: | |
ca4e0257 | 6371 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6372 | { |
6373 | s = "ld"; | |
6374 | goto ld; | |
6375 | } | |
6376 | ||
6377 | s = "lw"; | |
6378 | fmt = "t,o(b)"; | |
6379 | goto ldd_std; | |
6380 | ||
6381 | case M_SD_AB: | |
ca4e0257 | 6382 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6383 | { |
6384 | s = "sd"; | |
6385 | goto st; | |
6386 | } | |
6387 | ||
6388 | s = "sw"; | |
6389 | fmt = "t,o(b)"; | |
6390 | ||
6391 | ldd_std: | |
afdbd6d0 CD |
6392 | /* We do _not_ bother to allow embedded PIC (symbol-local_symbol) |
6393 | loads for the case of doing a pair of loads to simulate an 'ld'. | |
6394 | This is not currently done by the compiler, and assembly coders | |
6395 | writing embedded-pic code can cope. */ | |
6396 | ||
252b5132 RH |
6397 | if (offset_expr.X_op != O_symbol |
6398 | && offset_expr.X_op != O_constant) | |
6399 | { | |
6400 | as_bad (_("expression too complex")); | |
6401 | offset_expr.X_op = O_constant; | |
6402 | } | |
6403 | ||
6404 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6405 | to adjust when loading from memory. We set coproc if we must | |
6406 | load $fn+1 first. */ | |
bdaaa2e1 | 6407 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6408 | if (! target_big_endian) |
6409 | coproc = 0; | |
6410 | ||
6411 | if (mips_pic == NO_PIC | |
6412 | || offset_expr.X_op == O_constant) | |
6413 | { | |
f9419b05 TS |
6414 | char *p; |
6415 | ||
252b5132 | 6416 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 TS |
6417 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6418 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6419 | If we have a base register, we use this |
6420 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6421 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6422 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6423 | If this is not a GP relative symbol, we want |
6424 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6425 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6426 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6427 | If there is a base register, we add it to $at after the | |
6428 | lui instruction. If there is a constant, we always use | |
6429 | the last case. */ | |
e7d556df | 6430 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
6431 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6432 | { | |
6433 | p = NULL; | |
6434 | used_at = 1; | |
6435 | } | |
6436 | else | |
6437 | { | |
6438 | int off; | |
6439 | ||
6440 | if (breg == 0) | |
6441 | { | |
6442 | frag_grow (28); | |
c9914766 | 6443 | tempreg = mips_gp_register; |
252b5132 RH |
6444 | off = 0; |
6445 | used_at = 0; | |
6446 | } | |
6447 | else | |
6448 | { | |
6449 | frag_grow (36); | |
6450 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6451 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 6452 | "d,v,t", AT, breg, mips_gp_register); |
252b5132 RH |
6453 | tempreg = AT; |
6454 | off = 4; | |
6455 | used_at = 1; | |
6456 | } | |
6457 | ||
beae10d5 | 6458 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6459 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6460 | coproc ? treg + 1 : treg, | |
cdf6fd85 | 6461 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6462 | offset_expr.X_add_number += 4; |
6463 | ||
6464 | /* Set mips_optimize to 2 to avoid inserting an | |
6465 | undesired nop. */ | |
6466 | hold_mips_optimize = mips_optimize; | |
6467 | mips_optimize = 2; | |
beae10d5 | 6468 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6469 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6470 | coproc ? treg : treg + 1, | |
cdf6fd85 | 6471 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6472 | mips_optimize = hold_mips_optimize; |
6473 | ||
6474 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
6475 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
6476 | used_at && mips_opts.noat), | |
956cd1d6 | 6477 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6478 | |
6479 | /* We just generated two relocs. When tc_gen_reloc | |
6480 | handles this case, it will skip the first reloc and | |
6481 | handle the second. The second reloc already has an | |
6482 | extra addend of 4, which we added above. We must | |
6483 | subtract it out, and then subtract another 4 to make | |
6484 | the first reloc come out right. The second reloc | |
6485 | will come out right because we are going to add 4 to | |
6486 | offset_expr when we build its instruction below. | |
6487 | ||
6488 | If we have a symbol, then we don't want to include | |
6489 | the offset, because it will wind up being included | |
6490 | when we generate the reloc. */ | |
6491 | ||
6492 | if (offset_expr.X_op == O_constant) | |
6493 | offset_expr.X_add_number -= 8; | |
6494 | else | |
6495 | { | |
6496 | offset_expr.X_add_number = -4; | |
6497 | offset_expr.X_op = O_constant; | |
6498 | } | |
6499 | } | |
6500 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
6501 | if (p != NULL) | |
6502 | p += 4; | |
6503 | if (breg != 0) | |
6504 | { | |
6505 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6506 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6507 | "d,v,t", AT, breg, AT); |
6508 | if (p != NULL) | |
6509 | p += 4; | |
6510 | } | |
beae10d5 | 6511 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6512 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6513 | coproc ? treg + 1 : treg, | |
6514 | (int) BFD_RELOC_LO16, AT); | |
6515 | if (p != NULL) | |
6516 | p += 4; | |
6517 | /* FIXME: How do we handle overflow here? */ | |
6518 | offset_expr.X_add_number += 4; | |
beae10d5 | 6519 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6520 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6521 | coproc ? treg : treg + 1, | |
6522 | (int) BFD_RELOC_LO16, AT); | |
bdaaa2e1 | 6523 | } |
252b5132 RH |
6524 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6525 | { | |
6526 | int off; | |
6527 | ||
6528 | /* If this is a reference to an external symbol, we want | |
6529 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6530 | nop | |
6531 | <op> $treg,0($at) | |
6532 | <op> $treg+1,4($at) | |
6533 | Otherwise we want | |
6534 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6535 | nop | |
6536 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6537 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6538 | If there is a base register we add it to $at before the | |
6539 | lwc1 instructions. If there is a constant we include it | |
6540 | in the lwc1 instructions. */ | |
6541 | used_at = 1; | |
6542 | expr1.X_add_number = offset_expr.X_add_number; | |
6543 | offset_expr.X_add_number = 0; | |
6544 | if (expr1.X_add_number < -0x8000 | |
6545 | || expr1.X_add_number >= 0x8000 - 4) | |
6546 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6547 | if (breg == 0) | |
6548 | off = 0; | |
6549 | else | |
6550 | off = 4; | |
6551 | frag_grow (24 + off); | |
6552 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
c9914766 TS |
6553 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", AT, |
6554 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6555 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
6556 | if (breg != 0) | |
6557 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6558 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 6559 | "d,v,t", AT, breg, AT); |
beae10d5 | 6560 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6561 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6562 | coproc ? treg + 1 : treg, | |
6563 | (int) BFD_RELOC_LO16, AT); | |
6564 | expr1.X_add_number += 4; | |
6565 | ||
6566 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6567 | nop. */ | |
6568 | hold_mips_optimize = mips_optimize; | |
6569 | mips_optimize = 2; | |
beae10d5 | 6570 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6571 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6572 | coproc ? treg : treg + 1, | |
6573 | (int) BFD_RELOC_LO16, AT); | |
6574 | mips_optimize = hold_mips_optimize; | |
6575 | ||
6576 | (void) frag_var (rs_machine_dependent, 0, 0, | |
6577 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
c4e7957c | 6578 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6579 | } |
6580 | else if (mips_pic == SVR4_PIC) | |
6581 | { | |
6582 | int gpdel, off; | |
f9419b05 | 6583 | char *p; |
252b5132 RH |
6584 | |
6585 | /* If this is a reference to an external symbol, we want | |
6586 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6587 | addu $at,$at,$gp | |
6588 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6589 | nop | |
6590 | <op> $treg,0($at) | |
6591 | <op> $treg+1,4($at) | |
6592 | Otherwise we want | |
6593 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6594 | nop | |
6595 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6596 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6597 | If there is a base register we add it to $at before the | |
6598 | lwc1 instructions. If there is a constant we include it | |
6599 | in the lwc1 instructions. */ | |
6600 | used_at = 1; | |
6601 | expr1.X_add_number = offset_expr.X_add_number; | |
6602 | offset_expr.X_add_number = 0; | |
6603 | if (expr1.X_add_number < -0x8000 | |
6604 | || expr1.X_add_number >= 0x8000 - 4) | |
6605 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
c9914766 | 6606 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
6607 | gpdel = 4; |
6608 | else | |
6609 | gpdel = 0; | |
6610 | if (breg == 0) | |
6611 | off = 0; | |
6612 | else | |
6613 | off = 4; | |
6614 | frag_grow (56); | |
6615 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
6616 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
6617 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6618 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 6619 | "d,v,t", AT, AT, mips_gp_register); |
252b5132 | 6620 | macro_build ((char *) NULL, &icnt, &offset_expr, |
ca4e0257 | 6621 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
6622 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); |
6623 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
6624 | if (breg != 0) | |
6625 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6626 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 6627 | "d,v,t", AT, breg, AT); |
beae10d5 | 6628 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6629 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6630 | coproc ? treg + 1 : treg, | |
6631 | (int) BFD_RELOC_LO16, AT); | |
6632 | expr1.X_add_number += 4; | |
6633 | ||
6634 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6635 | nop. */ | |
6636 | hold_mips_optimize = mips_optimize; | |
6637 | mips_optimize = 2; | |
beae10d5 | 6638 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6639 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6640 | coproc ? treg : treg + 1, | |
6641 | (int) BFD_RELOC_LO16, AT); | |
6642 | mips_optimize = hold_mips_optimize; | |
6643 | expr1.X_add_number -= 4; | |
6644 | ||
6645 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
6646 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
6647 | 8 + gpdel + off, 1, 0), | |
c4e7957c | 6648 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6649 | if (gpdel > 0) |
6650 | { | |
6651 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6652 | p += 4; | |
6653 | } | |
6654 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 6655 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
c9914766 TS |
6656 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, |
6657 | mips_gp_register); | |
252b5132 RH |
6658 | p += 4; |
6659 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6660 | p += 4; | |
6661 | if (breg != 0) | |
6662 | { | |
6663 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6664 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6665 | "d,v,t", AT, breg, AT); |
6666 | p += 4; | |
6667 | } | |
beae10d5 | 6668 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6669 | macro_build (p, &icnt, &expr1, s, fmt, |
6670 | coproc ? treg + 1 : treg, | |
6671 | (int) BFD_RELOC_LO16, AT); | |
6672 | p += 4; | |
6673 | expr1.X_add_number += 4; | |
6674 | ||
6675 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6676 | nop. */ | |
6677 | hold_mips_optimize = mips_optimize; | |
6678 | mips_optimize = 2; | |
beae10d5 | 6679 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6680 | macro_build (p, &icnt, &expr1, s, fmt, |
6681 | coproc ? treg : treg + 1, | |
6682 | (int) BFD_RELOC_LO16, AT); | |
6683 | mips_optimize = hold_mips_optimize; | |
6684 | } | |
6685 | else if (mips_pic == EMBEDDED_PIC) | |
6686 | { | |
6687 | /* If there is no base register, we use | |
cdf6fd85 TS |
6688 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6689 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6690 | If we have a base register, we use |
6691 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6692 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6693 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6694 | */ |
6695 | if (breg == 0) | |
6696 | { | |
c9914766 | 6697 | tempreg = mips_gp_register; |
252b5132 RH |
6698 | used_at = 0; |
6699 | } | |
6700 | else | |
6701 | { | |
6702 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6703 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 6704 | "d,v,t", AT, breg, mips_gp_register); |
252b5132 RH |
6705 | tempreg = AT; |
6706 | used_at = 1; | |
6707 | } | |
6708 | ||
beae10d5 | 6709 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6710 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6711 | coproc ? treg + 1 : treg, | |
cdf6fd85 | 6712 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 | 6713 | offset_expr.X_add_number += 4; |
beae10d5 | 6714 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6715 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6716 | coproc ? treg : treg + 1, | |
cdf6fd85 | 6717 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6718 | } |
6719 | else | |
6720 | abort (); | |
6721 | ||
6722 | if (! used_at) | |
6723 | return; | |
6724 | ||
6725 | break; | |
6726 | ||
6727 | case M_LD_OB: | |
6728 | s = "lw"; | |
6729 | goto sd_ob; | |
6730 | case M_SD_OB: | |
6731 | s = "sw"; | |
6732 | sd_ob: | |
ca4e0257 | 6733 | assert (HAVE_32BIT_ADDRESSES); |
252b5132 RH |
6734 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
6735 | (int) BFD_RELOC_LO16, breg); | |
6736 | offset_expr.X_add_number += 4; | |
6737 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
6738 | (int) BFD_RELOC_LO16, breg); | |
6739 | return; | |
6740 | ||
6741 | /* New code added to support COPZ instructions. | |
6742 | This code builds table entries out of the macros in mip_opcodes. | |
6743 | R4000 uses interlocks to handle coproc delays. | |
6744 | Other chips (like the R3000) require nops to be inserted for delays. | |
6745 | ||
f72c8c98 | 6746 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6747 | In order to fill delay slots for non-interlocked chips, |
6748 | we must have a way to specify delays based on the coprocessor. | |
6749 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6750 | What are the side-effects of the cop instruction? | |
6751 | What cache support might we have and what are its effects? | |
6752 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6753 | What registers are read/set/modified? |
252b5132 RH |
6754 | |
6755 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6756 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6757 | |
6758 | case M_COP0: | |
6759 | s = "c0"; | |
6760 | goto copz; | |
6761 | case M_COP1: | |
6762 | s = "c1"; | |
6763 | goto copz; | |
6764 | case M_COP2: | |
6765 | s = "c2"; | |
6766 | goto copz; | |
6767 | case M_COP3: | |
6768 | s = "c3"; | |
6769 | copz: | |
6770 | /* For now we just do C (same as Cz). The parameter will be | |
6771 | stored in insn_opcode by mips_ip. */ | |
6772 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", | |
6773 | ip->insn_opcode); | |
6774 | return; | |
6775 | ||
ea1fb5dc RS |
6776 | case M_MOVE: |
6777 | move_register (&icnt, dreg, sreg); | |
6778 | return; | |
6779 | ||
252b5132 RH |
6780 | #ifdef LOSING_COMPILER |
6781 | default: | |
6782 | /* Try and see if this is a new itbl instruction. | |
6783 | This code builds table entries out of the macros in mip_opcodes. | |
6784 | FIXME: For now we just assemble the expression and pass it's | |
6785 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6786 | We may want to have the assembler assemble this value, |
252b5132 RH |
6787 | so that we gain the assembler's knowledge of delay slots, |
6788 | symbols, etc. | |
6789 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6790 | if (itbl_have_entries |
252b5132 | 6791 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6792 | { |
252b5132 RH |
6793 | s = ip->insn_mo->name; |
6794 | s2 = "cop3"; | |
6795 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
6796 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); | |
6797 | return; | |
beae10d5 | 6798 | } |
252b5132 RH |
6799 | macro2 (ip); |
6800 | return; | |
6801 | } | |
6802 | if (mips_opts.noat) | |
6803 | as_warn (_("Macro used $at after \".set noat\"")); | |
6804 | } | |
bdaaa2e1 | 6805 | |
252b5132 RH |
6806 | static void |
6807 | macro2 (ip) | |
6808 | struct mips_cl_insn *ip; | |
6809 | { | |
6810 | register int treg, sreg, dreg, breg; | |
6811 | int tempreg; | |
6812 | int mask; | |
6813 | int icnt = 0; | |
6814 | int used_at; | |
6815 | expressionS expr1; | |
6816 | const char *s; | |
6817 | const char *s2; | |
6818 | const char *fmt; | |
6819 | int likely = 0; | |
6820 | int dbl = 0; | |
6821 | int coproc = 0; | |
6822 | int lr = 0; | |
6823 | int imm = 0; | |
6824 | int off; | |
6825 | offsetT maxnum; | |
6826 | bfd_reloc_code_real_type r; | |
6827 | char *p; | |
bdaaa2e1 | 6828 | |
252b5132 RH |
6829 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6830 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6831 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6832 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6833 | |
252b5132 RH |
6834 | expr1.X_op = O_constant; |
6835 | expr1.X_op_symbol = NULL; | |
6836 | expr1.X_add_symbol = NULL; | |
6837 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6838 | |
252b5132 RH |
6839 | switch (mask) |
6840 | { | |
6841 | #endif /* LOSING_COMPILER */ | |
6842 | ||
6843 | case M_DMUL: | |
6844 | dbl = 1; | |
6845 | case M_MUL: | |
2396cfb9 TS |
6846 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6847 | dbl ? "dmultu" : "multu", "s,t", sreg, treg); | |
6848 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", | |
6849 | dreg); | |
252b5132 RH |
6850 | return; |
6851 | ||
6852 | case M_DMUL_I: | |
6853 | dbl = 1; | |
6854 | case M_MUL_I: | |
6855 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6856 | not trying to be that fancy. GCC should do this for us | |
6857 | anyway. */ | |
6858 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6859 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 6860 | dbl ? "dmult" : "mult", "s,t", sreg, AT); |
2396cfb9 TS |
6861 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", |
6862 | dreg); | |
252b5132 RH |
6863 | break; |
6864 | ||
6865 | case M_DMULO_I: | |
6866 | dbl = 1; | |
6867 | case M_MULO_I: | |
6868 | imm = 1; | |
6869 | goto do_mulo; | |
6870 | ||
6871 | case M_DMULO: | |
6872 | dbl = 1; | |
6873 | case M_MULO: | |
6874 | do_mulo: | |
b34976b6 | 6875 | mips_emit_delays (TRUE); |
252b5132 RH |
6876 | ++mips_opts.noreorder; |
6877 | mips_any_noreorder = 1; | |
6878 | if (imm) | |
6879 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6880 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 6881 | dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); |
2396cfb9 TS |
6882 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", |
6883 | dreg); | |
6884 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f9419b05 | 6885 | dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); |
2396cfb9 TS |
6886 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d", |
6887 | AT); | |
252b5132 | 6888 | if (mips_trap) |
9bd7d936 MR |
6889 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", |
6890 | "s,t,q", dreg, AT, 6); | |
252b5132 RH |
6891 | else |
6892 | { | |
6893 | expr1.X_add_number = 8; | |
2396cfb9 TS |
6894 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, |
6895 | AT); | |
6896 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", | |
6897 | 0); | |
6898 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", | |
6899 | "c", 6); | |
252b5132 RH |
6900 | } |
6901 | --mips_opts.noreorder; | |
2396cfb9 | 6902 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg); |
252b5132 RH |
6903 | break; |
6904 | ||
6905 | case M_DMULOU_I: | |
6906 | dbl = 1; | |
6907 | case M_MULOU_I: | |
6908 | imm = 1; | |
6909 | goto do_mulou; | |
6910 | ||
6911 | case M_DMULOU: | |
6912 | dbl = 1; | |
6913 | case M_MULOU: | |
6914 | do_mulou: | |
b34976b6 | 6915 | mips_emit_delays (TRUE); |
252b5132 RH |
6916 | ++mips_opts.noreorder; |
6917 | mips_any_noreorder = 1; | |
6918 | if (imm) | |
6919 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6920 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
252b5132 RH |
6921 | dbl ? "dmultu" : "multu", |
6922 | "s,t", sreg, imm ? AT : treg); | |
2396cfb9 TS |
6923 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d", |
6924 | AT); | |
6925 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", | |
6926 | dreg); | |
252b5132 | 6927 | if (mips_trap) |
9bd7d936 MR |
6928 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", |
6929 | "s,t,q", AT, 0, 6); | |
252b5132 RH |
6930 | else |
6931 | { | |
6932 | expr1.X_add_number = 8; | |
6933 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
2396cfb9 TS |
6934 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
6935 | 0); | |
6936 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", | |
6937 | "c", 6); | |
252b5132 RH |
6938 | } |
6939 | --mips_opts.noreorder; | |
6940 | break; | |
6941 | ||
771c7ce4 | 6942 | case M_DROL: |
82dd0097 CD |
6943 | if (CPU_HAS_DROR (mips_arch)) |
6944 | { | |
6945 | if (dreg == sreg) | |
6946 | { | |
6947 | tempreg = AT; | |
6948 | used_at = 1; | |
6949 | } | |
6950 | else | |
6951 | { | |
6952 | tempreg = dreg; | |
6953 | used_at = 0; | |
6954 | } | |
6955 | macro_build ((char *) NULL, &icnt, NULL, "dnegu", | |
6956 | "d,w", tempreg, treg); | |
6957 | macro_build ((char *) NULL, &icnt, NULL, "drorv", | |
6958 | "d,t,s", dreg, sreg, tempreg); | |
6959 | if (used_at) | |
6960 | break; | |
6961 | return; | |
6962 | } | |
771c7ce4 TS |
6963 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu", |
6964 | "d,v,t", AT, 0, treg); | |
6965 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv", | |
6966 | "d,t,s", AT, sreg, AT); | |
6967 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv", | |
6968 | "d,t,s", dreg, sreg, treg); | |
6969 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6970 | "d,v,t", dreg, dreg, AT); | |
6971 | break; | |
6972 | ||
252b5132 | 6973 | case M_ROL: |
82dd0097 CD |
6974 | if (CPU_HAS_ROR (mips_arch)) |
6975 | { | |
6976 | if (dreg == sreg) | |
6977 | { | |
6978 | tempreg = AT; | |
6979 | used_at = 1; | |
6980 | } | |
6981 | else | |
6982 | { | |
6983 | tempreg = dreg; | |
6984 | used_at = 0; | |
6985 | } | |
6986 | macro_build ((char *) NULL, &icnt, NULL, "negu", | |
6987 | "d,w", tempreg, treg); | |
6988 | macro_build ((char *) NULL, &icnt, NULL, "rorv", | |
6989 | "d,t,s", dreg, sreg, tempreg); | |
6990 | if (used_at) | |
6991 | break; | |
6992 | return; | |
6993 | } | |
2396cfb9 TS |
6994 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu", |
6995 | "d,v,t", AT, 0, treg); | |
6996 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv", | |
6997 | "d,t,s", AT, sreg, AT); | |
6998 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv", | |
6999 | "d,t,s", dreg, sreg, treg); | |
7000 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7001 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7002 | break; |
7003 | ||
771c7ce4 TS |
7004 | case M_DROL_I: |
7005 | { | |
7006 | unsigned int rot; | |
82dd0097 | 7007 | char *l, *r; |
771c7ce4 TS |
7008 | |
7009 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7010 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7011 | rot = imm_expr.X_add_number & 0x3f; |
60b63b72 RS |
7012 | if (CPU_HAS_DROR (mips_arch)) |
7013 | { | |
7014 | rot = (64 - rot) & 0x3f; | |
7015 | if (rot >= 32) | |
7016 | macro_build ((char *) NULL, &icnt, NULL, "dror32", | |
7017 | "d,w,<", dreg, sreg, rot - 32); | |
7018 | else | |
7019 | macro_build ((char *) NULL, &icnt, NULL, "dror", | |
7020 | "d,w,<", dreg, sreg, rot); | |
82dd0097 | 7021 | return; |
60b63b72 | 7022 | } |
483fc7cd | 7023 | if (rot == 0) |
483fc7cd | 7024 | { |
82dd0097 CD |
7025 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl", |
7026 | "d,w,<", dreg, sreg, 0); | |
7027 | return; | |
483fc7cd | 7028 | } |
82dd0097 CD |
7029 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
7030 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
7031 | rot &= 0x1f; | |
7032 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l, | |
7033 | "d,w,<", AT, sreg, rot); | |
7034 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r, | |
7035 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7036 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7037 | "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7038 | } |
7039 | break; | |
7040 | ||
252b5132 | 7041 | case M_ROL_I: |
771c7ce4 TS |
7042 | { |
7043 | unsigned int rot; | |
7044 | ||
7045 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7046 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7047 | rot = imm_expr.X_add_number & 0x1f; |
60b63b72 RS |
7048 | if (CPU_HAS_ROR (mips_arch)) |
7049 | { | |
7050 | macro_build ((char *) NULL, &icnt, NULL, "ror", | |
7051 | "d,w,<", dreg, sreg, (32 - rot) & 0x1f); | |
82dd0097 | 7052 | return; |
60b63b72 | 7053 | } |
483fc7cd | 7054 | if (rot == 0) |
483fc7cd | 7055 | { |
483fc7cd | 7056 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", |
82dd0097 CD |
7057 | "d,w,<", dreg, sreg, 0); |
7058 | return; | |
483fc7cd | 7059 | } |
82dd0097 CD |
7060 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", |
7061 | "d,w,<", AT, sreg, rot); | |
7062 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", | |
7063 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7064 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7065 | "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7066 | } |
7067 | break; | |
7068 | ||
7069 | case M_DROR: | |
82dd0097 CD |
7070 | if (CPU_HAS_DROR (mips_arch)) |
7071 | { | |
7072 | macro_build ((char *) NULL, &icnt, NULL, "drorv", | |
7073 | "d,t,s", dreg, sreg, treg); | |
7074 | return; | |
7075 | } | |
771c7ce4 TS |
7076 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu", |
7077 | "d,v,t", AT, 0, treg); | |
7078 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv", | |
7079 | "d,t,s", AT, sreg, AT); | |
7080 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv", | |
7081 | "d,t,s", dreg, sreg, treg); | |
7082 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7083 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7084 | break; |
7085 | ||
7086 | case M_ROR: | |
82dd0097 CD |
7087 | if (CPU_HAS_ROR (mips_arch)) |
7088 | { | |
7089 | macro_build ((char *) NULL, &icnt, NULL, "rorv", | |
7090 | "d,t,s", dreg, sreg, treg); | |
7091 | return; | |
7092 | } | |
2396cfb9 TS |
7093 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu", |
7094 | "d,v,t", AT, 0, treg); | |
7095 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv", | |
7096 | "d,t,s", AT, sreg, AT); | |
7097 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv", | |
7098 | "d,t,s", dreg, sreg, treg); | |
7099 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7100 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7101 | break; |
7102 | ||
771c7ce4 TS |
7103 | case M_DROR_I: |
7104 | { | |
7105 | unsigned int rot; | |
82dd0097 | 7106 | char *l, *r; |
771c7ce4 TS |
7107 | |
7108 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7109 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7110 | rot = imm_expr.X_add_number & 0x3f; |
82dd0097 CD |
7111 | if (CPU_HAS_DROR (mips_arch)) |
7112 | { | |
7113 | if (rot >= 32) | |
7114 | macro_build ((char *) NULL, &icnt, NULL, "dror32", | |
7115 | "d,w,<", dreg, sreg, rot - 32); | |
7116 | else | |
7117 | macro_build ((char *) NULL, &icnt, NULL, "dror", | |
7118 | "d,w,<", dreg, sreg, rot); | |
7119 | return; | |
7120 | } | |
483fc7cd | 7121 | if (rot == 0) |
483fc7cd | 7122 | { |
82dd0097 CD |
7123 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl", |
7124 | "d,w,<", dreg, sreg, 0); | |
7125 | return; | |
483fc7cd | 7126 | } |
82dd0097 CD |
7127 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7128 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7129 | rot &= 0x1f; | |
7130 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r, | |
7131 | "d,w,<", AT, sreg, rot); | |
7132 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l, | |
7133 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7134 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7135 | "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7136 | } |
7137 | break; | |
7138 | ||
252b5132 | 7139 | case M_ROR_I: |
771c7ce4 TS |
7140 | { |
7141 | unsigned int rot; | |
7142 | ||
7143 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7144 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7145 | rot = imm_expr.X_add_number & 0x1f; |
82dd0097 CD |
7146 | if (CPU_HAS_ROR (mips_arch)) |
7147 | { | |
7148 | macro_build ((char *) NULL, &icnt, NULL, "ror", | |
7149 | "d,w,<", dreg, sreg, rot); | |
7150 | return; | |
7151 | } | |
483fc7cd | 7152 | if (rot == 0) |
483fc7cd RS |
7153 | { |
7154 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", | |
82dd0097 CD |
7155 | "d,w,<", dreg, sreg, 0); |
7156 | return; | |
483fc7cd | 7157 | } |
82dd0097 CD |
7158 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", |
7159 | "d,w,<", AT, sreg, rot); | |
7160 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", | |
7161 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7162 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7163 | "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7164 | } |
252b5132 RH |
7165 | break; |
7166 | ||
7167 | case M_S_DOB: | |
ec68c924 | 7168 | if (mips_arch == CPU_R4650) |
252b5132 RH |
7169 | { |
7170 | as_bad (_("opcode not supported on this processor")); | |
7171 | return; | |
7172 | } | |
e7af610e | 7173 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7174 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7175 | to adjust when storing to memory. */ | |
7176 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
7177 | target_big_endian ? treg + 1 : treg, | |
7178 | (int) BFD_RELOC_LO16, breg); | |
7179 | offset_expr.X_add_number += 4; | |
7180 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
7181 | target_big_endian ? treg : treg + 1, | |
7182 | (int) BFD_RELOC_LO16, breg); | |
7183 | return; | |
7184 | ||
7185 | case M_SEQ: | |
7186 | if (sreg == 0) | |
7187 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
7188 | treg, (int) BFD_RELOC_LO16); | |
7189 | else if (treg == 0) | |
7190 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
7191 | sreg, (int) BFD_RELOC_LO16); | |
7192 | else | |
7193 | { | |
2396cfb9 TS |
7194 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7195 | "d,v,t", dreg, sreg, treg); | |
252b5132 RH |
7196 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
7197 | dreg, (int) BFD_RELOC_LO16); | |
7198 | } | |
7199 | return; | |
7200 | ||
7201 | case M_SEQ_I: | |
7202 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7203 | { | |
7204 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
7205 | sreg, (int) BFD_RELOC_LO16); | |
7206 | return; | |
7207 | } | |
7208 | if (sreg == 0) | |
7209 | { | |
7210 | as_warn (_("Instruction %s: result is always false"), | |
7211 | ip->insn_mo->name); | |
ea1fb5dc | 7212 | move_register (&icnt, dreg, 0); |
252b5132 RH |
7213 | return; |
7214 | } | |
7215 | if (imm_expr.X_op == O_constant | |
7216 | && imm_expr.X_add_number >= 0 | |
7217 | && imm_expr.X_add_number < 0x10000) | |
7218 | { | |
7219 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, | |
7220 | sreg, (int) BFD_RELOC_LO16); | |
7221 | used_at = 0; | |
7222 | } | |
7223 | else if (imm_expr.X_op == O_constant | |
7224 | && imm_expr.X_add_number > -0x8000 | |
7225 | && imm_expr.X_add_number < 0) | |
7226 | { | |
7227 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7228 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
ca4e0257 | 7229 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
7230 | "t,r,j", dreg, sreg, |
7231 | (int) BFD_RELOC_LO16); | |
7232 | used_at = 0; | |
7233 | } | |
7234 | else | |
7235 | { | |
4d34fb5f | 7236 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7237 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7238 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7239 | used_at = 1; |
7240 | } | |
7241 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, | |
7242 | (int) BFD_RELOC_LO16); | |
7243 | if (used_at) | |
7244 | break; | |
7245 | return; | |
7246 | ||
7247 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7248 | s = "slt"; | |
7249 | goto sge; | |
7250 | case M_SGEU: | |
7251 | s = "sltu"; | |
7252 | sge: | |
2396cfb9 TS |
7253 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7254 | dreg, sreg, treg); | |
252b5132 RH |
7255 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
7256 | (int) BFD_RELOC_LO16); | |
7257 | return; | |
7258 | ||
7259 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7260 | case M_SGEU_I: | |
7261 | if (imm_expr.X_op == O_constant | |
7262 | && imm_expr.X_add_number >= -0x8000 | |
7263 | && imm_expr.X_add_number < 0x8000) | |
7264 | { | |
7265 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
7266 | mask == M_SGE_I ? "slti" : "sltiu", | |
7267 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
7268 | used_at = 0; | |
7269 | } | |
7270 | else | |
7271 | { | |
4d34fb5f | 7272 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7273 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
7274 | mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg, | |
7275 | AT); | |
252b5132 RH |
7276 | used_at = 1; |
7277 | } | |
7278 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
7279 | (int) BFD_RELOC_LO16); | |
7280 | if (used_at) | |
7281 | break; | |
7282 | return; | |
7283 | ||
7284 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7285 | s = "slt"; | |
7286 | goto sgt; | |
7287 | case M_SGTU: | |
7288 | s = "sltu"; | |
7289 | sgt: | |
2396cfb9 TS |
7290 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7291 | dreg, treg, sreg); | |
252b5132 RH |
7292 | return; |
7293 | ||
7294 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7295 | s = "slt"; | |
7296 | goto sgti; | |
7297 | case M_SGTU_I: | |
7298 | s = "sltu"; | |
7299 | sgti: | |
4d34fb5f | 7300 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7301 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7302 | dreg, AT, sreg); | |
252b5132 RH |
7303 | break; |
7304 | ||
2396cfb9 | 7305 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7306 | s = "slt"; |
7307 | goto sle; | |
7308 | case M_SLEU: | |
7309 | s = "sltu"; | |
7310 | sle: | |
2396cfb9 TS |
7311 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7312 | dreg, treg, sreg); | |
252b5132 RH |
7313 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
7314 | (int) BFD_RELOC_LO16); | |
7315 | return; | |
7316 | ||
2396cfb9 | 7317 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7318 | s = "slt"; |
7319 | goto slei; | |
7320 | case M_SLEU_I: | |
7321 | s = "sltu"; | |
7322 | slei: | |
4d34fb5f | 7323 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7324 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7325 | dreg, AT, sreg); | |
252b5132 RH |
7326 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
7327 | (int) BFD_RELOC_LO16); | |
7328 | break; | |
7329 | ||
7330 | case M_SLT_I: | |
7331 | if (imm_expr.X_op == O_constant | |
7332 | && imm_expr.X_add_number >= -0x8000 | |
7333 | && imm_expr.X_add_number < 0x8000) | |
7334 | { | |
7335 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", | |
7336 | dreg, sreg, (int) BFD_RELOC_LO16); | |
7337 | return; | |
7338 | } | |
4d34fb5f | 7339 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7340 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
7341 | dreg, sreg, AT); | |
252b5132 RH |
7342 | break; |
7343 | ||
7344 | case M_SLTU_I: | |
7345 | if (imm_expr.X_op == O_constant | |
7346 | && imm_expr.X_add_number >= -0x8000 | |
7347 | && imm_expr.X_add_number < 0x8000) | |
7348 | { | |
7349 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", | |
7350 | dreg, sreg, (int) BFD_RELOC_LO16); | |
7351 | return; | |
7352 | } | |
4d34fb5f | 7353 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7354 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7355 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7356 | break; |
7357 | ||
7358 | case M_SNE: | |
7359 | if (sreg == 0) | |
2396cfb9 TS |
7360 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7361 | "d,v,t", dreg, 0, treg); | |
252b5132 | 7362 | else if (treg == 0) |
2396cfb9 TS |
7363 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7364 | "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
7365 | else |
7366 | { | |
2396cfb9 TS |
7367 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7368 | "d,v,t", dreg, sreg, treg); | |
7369 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", | |
7370 | "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7371 | } |
7372 | return; | |
7373 | ||
7374 | case M_SNE_I: | |
7375 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7376 | { | |
2396cfb9 TS |
7377 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7378 | "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
7379 | return; |
7380 | } | |
7381 | if (sreg == 0) | |
7382 | { | |
7383 | as_warn (_("Instruction %s: result is always true"), | |
7384 | ip->insn_mo->name); | |
7385 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 7386 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
7387 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
7388 | return; | |
7389 | } | |
7390 | if (imm_expr.X_op == O_constant | |
7391 | && imm_expr.X_add_number >= 0 | |
7392 | && imm_expr.X_add_number < 0x10000) | |
7393 | { | |
7394 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", | |
7395 | dreg, sreg, (int) BFD_RELOC_LO16); | |
7396 | used_at = 0; | |
7397 | } | |
7398 | else if (imm_expr.X_op == O_constant | |
7399 | && imm_expr.X_add_number > -0x8000 | |
7400 | && imm_expr.X_add_number < 0) | |
7401 | { | |
7402 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7403 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
ca4e0257 | 7404 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
7405 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
7406 | used_at = 0; | |
7407 | } | |
7408 | else | |
7409 | { | |
4d34fb5f | 7410 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7411 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7412 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7413 | used_at = 1; |
7414 | } | |
2396cfb9 TS |
7415 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7416 | "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7417 | if (used_at) |
7418 | break; | |
7419 | return; | |
7420 | ||
7421 | case M_DSUB_I: | |
7422 | dbl = 1; | |
7423 | case M_SUB_I: | |
7424 | if (imm_expr.X_op == O_constant | |
7425 | && imm_expr.X_add_number > -0x8000 | |
7426 | && imm_expr.X_add_number <= 0x8000) | |
7427 | { | |
7428 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7429 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
7430 | dbl ? "daddi" : "addi", | |
7431 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
7432 | return; | |
7433 | } | |
7434 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 7435 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7436 | dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7437 | break; |
7438 | ||
7439 | case M_DSUBU_I: | |
7440 | dbl = 1; | |
7441 | case M_SUBU_I: | |
7442 | if (imm_expr.X_op == O_constant | |
7443 | && imm_expr.X_add_number > -0x8000 | |
7444 | && imm_expr.X_add_number <= 0x8000) | |
7445 | { | |
7446 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7447 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
7448 | dbl ? "daddiu" : "addiu", | |
7449 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
7450 | return; | |
7451 | } | |
7452 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 7453 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7454 | dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7455 | break; |
7456 | ||
7457 | case M_TEQ_I: | |
7458 | s = "teq"; | |
7459 | goto trap; | |
7460 | case M_TGE_I: | |
7461 | s = "tge"; | |
7462 | goto trap; | |
7463 | case M_TGEU_I: | |
7464 | s = "tgeu"; | |
7465 | goto trap; | |
7466 | case M_TLT_I: | |
7467 | s = "tlt"; | |
7468 | goto trap; | |
7469 | case M_TLTU_I: | |
7470 | s = "tltu"; | |
7471 | goto trap; | |
7472 | case M_TNE_I: | |
7473 | s = "tne"; | |
7474 | trap: | |
4d34fb5f | 7475 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7476 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg, |
7477 | AT); | |
252b5132 RH |
7478 | break; |
7479 | ||
252b5132 | 7480 | case M_TRUNCWS: |
43841e91 | 7481 | case M_TRUNCWD: |
e7af610e | 7482 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7483 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7484 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7485 | ||
7486 | /* | |
7487 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7488 | * or is there a reason for it? | |
7489 | */ | |
b34976b6 | 7490 | mips_emit_delays (TRUE); |
252b5132 RH |
7491 | ++mips_opts.noreorder; |
7492 | mips_any_noreorder = 1; | |
2396cfb9 | 7493 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G", |
f9419b05 | 7494 | treg, RA); |
2396cfb9 | 7495 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G", |
f9419b05 | 7496 | treg, RA); |
2396cfb9 | 7497 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
252b5132 RH |
7498 | expr1.X_add_number = 3; |
7499 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, | |
7500 | (int) BFD_RELOC_LO16); | |
7501 | expr1.X_add_number = 2; | |
7502 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, | |
7503 | (int) BFD_RELOC_LO16); | |
2396cfb9 | 7504 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G", |
f9419b05 | 7505 | AT, RA); |
2396cfb9 TS |
7506 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
7507 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
252b5132 | 7508 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
2396cfb9 | 7509 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G", |
f9419b05 | 7510 | treg, RA); |
2396cfb9 | 7511 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
252b5132 RH |
7512 | --mips_opts.noreorder; |
7513 | break; | |
7514 | ||
7515 | case M_ULH: | |
7516 | s = "lb"; | |
7517 | goto ulh; | |
7518 | case M_ULHU: | |
7519 | s = "lbu"; | |
7520 | ulh: | |
7521 | if (offset_expr.X_add_number >= 0x7fff) | |
7522 | as_bad (_("operand overflow")); | |
7523 | /* avoid load delay */ | |
7524 | if (! target_big_endian) | |
f9419b05 | 7525 | ++offset_expr.X_add_number; |
252b5132 RH |
7526 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
7527 | (int) BFD_RELOC_LO16, breg); | |
7528 | if (! target_big_endian) | |
f9419b05 | 7529 | --offset_expr.X_add_number; |
252b5132 | 7530 | else |
f9419b05 | 7531 | ++offset_expr.X_add_number; |
252b5132 RH |
7532 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
7533 | (int) BFD_RELOC_LO16, breg); | |
2396cfb9 TS |
7534 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
7535 | treg, treg, 8); | |
7536 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
7537 | treg, treg, AT); | |
252b5132 RH |
7538 | break; |
7539 | ||
7540 | case M_ULD: | |
7541 | s = "ldl"; | |
7542 | s2 = "ldr"; | |
7543 | off = 7; | |
7544 | goto ulw; | |
7545 | case M_ULW: | |
7546 | s = "lwl"; | |
7547 | s2 = "lwr"; | |
7548 | off = 3; | |
7549 | ulw: | |
7550 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7551 | as_bad (_("operand overflow")); | |
7552 | if (! target_big_endian) | |
7553 | offset_expr.X_add_number += off; | |
7554 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
7555 | (int) BFD_RELOC_LO16, breg); | |
7556 | if (! target_big_endian) | |
7557 | offset_expr.X_add_number -= off; | |
7558 | else | |
7559 | offset_expr.X_add_number += off; | |
7560 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
7561 | (int) BFD_RELOC_LO16, breg); | |
7562 | return; | |
7563 | ||
7564 | case M_ULD_A: | |
7565 | s = "ldl"; | |
7566 | s2 = "ldr"; | |
7567 | off = 7; | |
7568 | goto ulwa; | |
7569 | case M_ULW_A: | |
7570 | s = "lwl"; | |
7571 | s2 = "lwr"; | |
7572 | off = 3; | |
7573 | ulwa: | |
d6bc6245 | 7574 | used_at = 1; |
c9914766 | 7575 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7576 | if (breg != 0) |
7577 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7578 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7579 | "d,v,t", AT, AT, breg); |
7580 | if (! target_big_endian) | |
7581 | expr1.X_add_number = off; | |
7582 | else | |
7583 | expr1.X_add_number = 0; | |
7584 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
7585 | (int) BFD_RELOC_LO16, AT); | |
7586 | if (! target_big_endian) | |
7587 | expr1.X_add_number = 0; | |
7588 | else | |
7589 | expr1.X_add_number = off; | |
7590 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
7591 | (int) BFD_RELOC_LO16, AT); | |
7592 | break; | |
7593 | ||
7594 | case M_ULH_A: | |
7595 | case M_ULHU_A: | |
d6bc6245 | 7596 | used_at = 1; |
c9914766 | 7597 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7598 | if (breg != 0) |
7599 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7600 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7601 | "d,v,t", AT, AT, breg); |
7602 | if (target_big_endian) | |
7603 | expr1.X_add_number = 0; | |
7604 | macro_build ((char *) NULL, &icnt, &expr1, | |
7605 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
7606 | (int) BFD_RELOC_LO16, AT); | |
7607 | if (target_big_endian) | |
7608 | expr1.X_add_number = 1; | |
7609 | else | |
7610 | expr1.X_add_number = 0; | |
7611 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
7612 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
7613 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
7614 | treg, treg, 8); | |
7615 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
7616 | treg, treg, AT); | |
252b5132 RH |
7617 | break; |
7618 | ||
7619 | case M_USH: | |
7620 | if (offset_expr.X_add_number >= 0x7fff) | |
7621 | as_bad (_("operand overflow")); | |
7622 | if (target_big_endian) | |
f9419b05 | 7623 | ++offset_expr.X_add_number; |
252b5132 RH |
7624 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
7625 | (int) BFD_RELOC_LO16, breg); | |
2396cfb9 TS |
7626 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", |
7627 | AT, treg, 8); | |
252b5132 | 7628 | if (target_big_endian) |
f9419b05 | 7629 | --offset_expr.X_add_number; |
252b5132 | 7630 | else |
f9419b05 | 7631 | ++offset_expr.X_add_number; |
252b5132 RH |
7632 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
7633 | (int) BFD_RELOC_LO16, breg); | |
7634 | break; | |
7635 | ||
7636 | case M_USD: | |
7637 | s = "sdl"; | |
7638 | s2 = "sdr"; | |
7639 | off = 7; | |
7640 | goto usw; | |
7641 | case M_USW: | |
7642 | s = "swl"; | |
7643 | s2 = "swr"; | |
7644 | off = 3; | |
7645 | usw: | |
7646 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7647 | as_bad (_("operand overflow")); | |
7648 | if (! target_big_endian) | |
7649 | offset_expr.X_add_number += off; | |
7650 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
7651 | (int) BFD_RELOC_LO16, breg); | |
7652 | if (! target_big_endian) | |
7653 | offset_expr.X_add_number -= off; | |
7654 | else | |
7655 | offset_expr.X_add_number += off; | |
7656 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
7657 | (int) BFD_RELOC_LO16, breg); | |
7658 | return; | |
7659 | ||
7660 | case M_USD_A: | |
7661 | s = "sdl"; | |
7662 | s2 = "sdr"; | |
7663 | off = 7; | |
7664 | goto uswa; | |
7665 | case M_USW_A: | |
7666 | s = "swl"; | |
7667 | s2 = "swr"; | |
7668 | off = 3; | |
7669 | uswa: | |
d6bc6245 | 7670 | used_at = 1; |
c9914766 | 7671 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7672 | if (breg != 0) |
7673 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7674 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7675 | "d,v,t", AT, AT, breg); |
7676 | if (! target_big_endian) | |
7677 | expr1.X_add_number = off; | |
7678 | else | |
7679 | expr1.X_add_number = 0; | |
7680 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
7681 | (int) BFD_RELOC_LO16, AT); | |
7682 | if (! target_big_endian) | |
7683 | expr1.X_add_number = 0; | |
7684 | else | |
7685 | expr1.X_add_number = off; | |
7686 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
7687 | (int) BFD_RELOC_LO16, AT); | |
7688 | break; | |
7689 | ||
7690 | case M_USH_A: | |
d6bc6245 | 7691 | used_at = 1; |
c9914766 | 7692 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7693 | if (breg != 0) |
7694 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7695 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7696 | "d,v,t", AT, AT, breg); |
7697 | if (! target_big_endian) | |
7698 | expr1.X_add_number = 0; | |
7699 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
7700 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
7701 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", |
7702 | treg, treg, 8); | |
252b5132 RH |
7703 | if (! target_big_endian) |
7704 | expr1.X_add_number = 1; | |
7705 | else | |
7706 | expr1.X_add_number = 0; | |
7707 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
7708 | (int) BFD_RELOC_LO16, AT); | |
7709 | if (! target_big_endian) | |
7710 | expr1.X_add_number = 0; | |
7711 | else | |
7712 | expr1.X_add_number = 1; | |
7713 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
7714 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
7715 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
7716 | treg, treg, 8); | |
7717 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
7718 | treg, treg, AT); | |
252b5132 RH |
7719 | break; |
7720 | ||
7721 | default: | |
7722 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7723 | are added dynamically. */ |
252b5132 RH |
7724 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7725 | break; | |
7726 | } | |
7727 | if (mips_opts.noat) | |
7728 | as_warn (_("Macro used $at after \".set noat\"")); | |
7729 | } | |
7730 | ||
7731 | /* Implement macros in mips16 mode. */ | |
7732 | ||
7733 | static void | |
7734 | mips16_macro (ip) | |
7735 | struct mips_cl_insn *ip; | |
7736 | { | |
7737 | int mask; | |
7738 | int xreg, yreg, zreg, tmp; | |
7739 | int icnt; | |
7740 | expressionS expr1; | |
7741 | int dbl; | |
7742 | const char *s, *s2, *s3; | |
7743 | ||
7744 | mask = ip->insn_mo->mask; | |
7745 | ||
7746 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
7747 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
7748 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
7749 | ||
7750 | icnt = 0; | |
7751 | ||
7752 | expr1.X_op = O_constant; | |
7753 | expr1.X_op_symbol = NULL; | |
7754 | expr1.X_add_symbol = NULL; | |
7755 | expr1.X_add_number = 1; | |
7756 | ||
7757 | dbl = 0; | |
7758 | ||
7759 | switch (mask) | |
7760 | { | |
7761 | default: | |
7762 | internalError (); | |
7763 | ||
7764 | case M_DDIV_3: | |
7765 | dbl = 1; | |
7766 | case M_DIV_3: | |
7767 | s = "mflo"; | |
7768 | goto do_div3; | |
7769 | case M_DREM_3: | |
7770 | dbl = 1; | |
7771 | case M_REM_3: | |
7772 | s = "mfhi"; | |
7773 | do_div3: | |
b34976b6 | 7774 | mips_emit_delays (TRUE); |
252b5132 RH |
7775 | ++mips_opts.noreorder; |
7776 | mips_any_noreorder = 1; | |
2396cfb9 | 7777 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
252b5132 RH |
7778 | dbl ? "ddiv" : "div", |
7779 | "0,x,y", xreg, yreg); | |
7780 | expr1.X_add_number = 2; | |
7781 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
2396cfb9 TS |
7782 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6", |
7783 | 7); | |
bdaaa2e1 | 7784 | |
252b5132 RH |
7785 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7786 | since that causes an overflow. We should do that as well, | |
7787 | but I don't see how to do the comparisons without a temporary | |
7788 | register. */ | |
7789 | --mips_opts.noreorder; | |
2396cfb9 | 7790 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg); |
252b5132 RH |
7791 | break; |
7792 | ||
7793 | case M_DIVU_3: | |
7794 | s = "divu"; | |
7795 | s2 = "mflo"; | |
7796 | goto do_divu3; | |
7797 | case M_REMU_3: | |
7798 | s = "divu"; | |
7799 | s2 = "mfhi"; | |
7800 | goto do_divu3; | |
7801 | case M_DDIVU_3: | |
7802 | s = "ddivu"; | |
7803 | s2 = "mflo"; | |
7804 | goto do_divu3; | |
7805 | case M_DREMU_3: | |
7806 | s = "ddivu"; | |
7807 | s2 = "mfhi"; | |
7808 | do_divu3: | |
b34976b6 | 7809 | mips_emit_delays (TRUE); |
252b5132 RH |
7810 | ++mips_opts.noreorder; |
7811 | mips_any_noreorder = 1; | |
2396cfb9 TS |
7812 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y", |
7813 | xreg, yreg); | |
252b5132 RH |
7814 | expr1.X_add_number = 2; |
7815 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
98d3f06f KH |
7816 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
7817 | "6", 7); | |
252b5132 | 7818 | --mips_opts.noreorder; |
2396cfb9 | 7819 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg); |
252b5132 RH |
7820 | break; |
7821 | ||
7822 | case M_DMUL: | |
7823 | dbl = 1; | |
7824 | case M_MUL: | |
2396cfb9 | 7825 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7826 | dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
2396cfb9 TS |
7827 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x", |
7828 | zreg); | |
252b5132 RH |
7829 | return; |
7830 | ||
7831 | case M_DSUBU_I: | |
7832 | dbl = 1; | |
7833 | goto do_subu; | |
7834 | case M_SUBU_I: | |
7835 | do_subu: | |
7836 | if (imm_expr.X_op != O_constant) | |
7837 | as_bad (_("Unsupported large constant")); | |
7838 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7839 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
9a41af64 | 7840 | dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7841 | break; |
7842 | ||
7843 | case M_SUBU_I_2: | |
7844 | if (imm_expr.X_op != O_constant) | |
7845 | as_bad (_("Unsupported large constant")); | |
7846 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7847 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
7848 | "x,k", xreg); | |
7849 | break; | |
7850 | ||
7851 | case M_DSUBU_I_2: | |
7852 | if (imm_expr.X_op != O_constant) | |
7853 | as_bad (_("Unsupported large constant")); | |
7854 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7855 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
7856 | "y,j", yreg); | |
7857 | break; | |
7858 | ||
7859 | case M_BEQ: | |
7860 | s = "cmp"; | |
7861 | s2 = "bteqz"; | |
7862 | goto do_branch; | |
7863 | case M_BNE: | |
7864 | s = "cmp"; | |
7865 | s2 = "btnez"; | |
7866 | goto do_branch; | |
7867 | case M_BLT: | |
7868 | s = "slt"; | |
7869 | s2 = "btnez"; | |
7870 | goto do_branch; | |
7871 | case M_BLTU: | |
7872 | s = "sltu"; | |
7873 | s2 = "btnez"; | |
7874 | goto do_branch; | |
7875 | case M_BLE: | |
7876 | s = "slt"; | |
7877 | s2 = "bteqz"; | |
7878 | goto do_reverse_branch; | |
7879 | case M_BLEU: | |
7880 | s = "sltu"; | |
7881 | s2 = "bteqz"; | |
7882 | goto do_reverse_branch; | |
7883 | case M_BGE: | |
7884 | s = "slt"; | |
7885 | s2 = "bteqz"; | |
7886 | goto do_branch; | |
7887 | case M_BGEU: | |
7888 | s = "sltu"; | |
7889 | s2 = "bteqz"; | |
7890 | goto do_branch; | |
7891 | case M_BGT: | |
7892 | s = "slt"; | |
7893 | s2 = "btnez"; | |
7894 | goto do_reverse_branch; | |
7895 | case M_BGTU: | |
7896 | s = "sltu"; | |
7897 | s2 = "btnez"; | |
7898 | ||
7899 | do_reverse_branch: | |
7900 | tmp = xreg; | |
7901 | xreg = yreg; | |
7902 | yreg = tmp; | |
7903 | ||
7904 | do_branch: | |
7905 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
7906 | xreg, yreg); | |
7907 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
7908 | break; | |
7909 | ||
7910 | case M_BEQ_I: | |
7911 | s = "cmpi"; | |
7912 | s2 = "bteqz"; | |
7913 | s3 = "x,U"; | |
7914 | goto do_branch_i; | |
7915 | case M_BNE_I: | |
7916 | s = "cmpi"; | |
7917 | s2 = "btnez"; | |
7918 | s3 = "x,U"; | |
7919 | goto do_branch_i; | |
7920 | case M_BLT_I: | |
7921 | s = "slti"; | |
7922 | s2 = "btnez"; | |
7923 | s3 = "x,8"; | |
7924 | goto do_branch_i; | |
7925 | case M_BLTU_I: | |
7926 | s = "sltiu"; | |
7927 | s2 = "btnez"; | |
7928 | s3 = "x,8"; | |
7929 | goto do_branch_i; | |
7930 | case M_BLE_I: | |
7931 | s = "slti"; | |
7932 | s2 = "btnez"; | |
7933 | s3 = "x,8"; | |
7934 | goto do_addone_branch_i; | |
7935 | case M_BLEU_I: | |
7936 | s = "sltiu"; | |
7937 | s2 = "btnez"; | |
7938 | s3 = "x,8"; | |
7939 | goto do_addone_branch_i; | |
7940 | case M_BGE_I: | |
7941 | s = "slti"; | |
7942 | s2 = "bteqz"; | |
7943 | s3 = "x,8"; | |
7944 | goto do_branch_i; | |
7945 | case M_BGEU_I: | |
7946 | s = "sltiu"; | |
7947 | s2 = "bteqz"; | |
7948 | s3 = "x,8"; | |
7949 | goto do_branch_i; | |
7950 | case M_BGT_I: | |
7951 | s = "slti"; | |
7952 | s2 = "bteqz"; | |
7953 | s3 = "x,8"; | |
7954 | goto do_addone_branch_i; | |
7955 | case M_BGTU_I: | |
7956 | s = "sltiu"; | |
7957 | s2 = "bteqz"; | |
7958 | s3 = "x,8"; | |
7959 | ||
7960 | do_addone_branch_i: | |
7961 | if (imm_expr.X_op != O_constant) | |
7962 | as_bad (_("Unsupported large constant")); | |
7963 | ++imm_expr.X_add_number; | |
7964 | ||
7965 | do_branch_i: | |
7966 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
7967 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
7968 | break; | |
7969 | ||
7970 | case M_ABS: | |
7971 | expr1.X_add_number = 0; | |
98d3f06f | 7972 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); |
252b5132 | 7973 | if (xreg != yreg) |
ea1fb5dc | 7974 | move_register (&icnt, xreg, yreg); |
252b5132 RH |
7975 | expr1.X_add_number = 2; |
7976 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
7977 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
7978 | "neg", "x,w", xreg, xreg); | |
7979 | } | |
7980 | } | |
7981 | ||
7982 | /* For consistency checking, verify that all bits are specified either | |
7983 | by the match/mask part of the instruction definition, or by the | |
7984 | operand list. */ | |
7985 | static int | |
7986 | validate_mips_insn (opc) | |
7987 | const struct mips_opcode *opc; | |
7988 | { | |
7989 | const char *p = opc->args; | |
7990 | char c; | |
7991 | unsigned long used_bits = opc->mask; | |
7992 | ||
7993 | if ((used_bits & opc->match) != opc->match) | |
7994 | { | |
7995 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7996 | opc->name, opc->args); | |
7997 | return 0; | |
7998 | } | |
7999 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8000 | while (*p) | |
8001 | switch (c = *p++) | |
8002 | { | |
8003 | case ',': break; | |
8004 | case '(': break; | |
8005 | case ')': break; | |
8006 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8007 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8008 | case 'A': break; | |
4372b673 | 8009 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8010 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8011 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8012 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8013 | case 'F': break; | |
8014 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8015 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8016 | case 'I': break; |
e972090a | 8017 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
252b5132 RH |
8018 | case 'L': break; |
8019 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8020 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8021 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8022 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8023 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8024 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8025 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8026 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8027 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8028 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8029 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8030 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8031 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8032 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8033 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8034 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8035 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8036 | case 'f': break; | |
8037 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8038 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8039 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8040 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8041 | case 'l': break; | |
8042 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8043 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8044 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8045 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8046 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8047 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8048 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8049 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8050 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8051 | case 'x': break; | |
8052 | case 'z': break; | |
8053 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8054 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8055 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8056 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8057 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8058 | case '[': break; | |
8059 | case ']': break; | |
252b5132 RH |
8060 | default: |
8061 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8062 | c, opc->name, opc->args); | |
8063 | return 0; | |
8064 | } | |
8065 | #undef USE_BITS | |
8066 | if (used_bits != 0xffffffff) | |
8067 | { | |
8068 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8069 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8070 | return 0; | |
8071 | } | |
8072 | return 1; | |
8073 | } | |
8074 | ||
8075 | /* This routine assembles an instruction into its binary format. As a | |
8076 | side effect, it sets one of the global variables imm_reloc or | |
8077 | offset_reloc to the type of relocation to do if one of the operands | |
8078 | is an address expression. */ | |
8079 | ||
8080 | static void | |
8081 | mips_ip (str, ip) | |
8082 | char *str; | |
8083 | struct mips_cl_insn *ip; | |
8084 | { | |
8085 | char *s; | |
8086 | const char *args; | |
43841e91 | 8087 | char c = 0; |
252b5132 RH |
8088 | struct mips_opcode *insn; |
8089 | char *argsStart; | |
8090 | unsigned int regno; | |
8091 | unsigned int lastregno = 0; | |
8092 | char *s_reset; | |
8093 | char save_c = 0; | |
252b5132 RH |
8094 | |
8095 | insn_error = NULL; | |
8096 | ||
8097 | /* If the instruction contains a '.', we first try to match an instruction | |
8098 | including the '.'. Then we try again without the '.'. */ | |
8099 | insn = NULL; | |
3882b010 | 8100 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8101 | continue; |
8102 | ||
8103 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8104 | the call to hash_find. Save the character we replaced just in case we | |
8105 | have to re-parse the instruction. */ | |
3882b010 | 8106 | if (ISSPACE (*s)) |
252b5132 RH |
8107 | { |
8108 | save_c = *s; | |
8109 | *s++ = '\0'; | |
8110 | } | |
bdaaa2e1 | 8111 | |
252b5132 RH |
8112 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8113 | ||
8114 | /* If we didn't find the instruction in the opcode table, try again, but | |
8115 | this time with just the instruction up to, but not including the | |
8116 | first '.'. */ | |
8117 | if (insn == NULL) | |
8118 | { | |
bdaaa2e1 | 8119 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8120 | if (save_c) |
8121 | *(--s) = save_c; | |
8122 | ||
8123 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8124 | for (s = str; |
8125 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8126 | ++s) | |
252b5132 RH |
8127 | continue; |
8128 | ||
8129 | /* If we did not find a '.', then we can quit now. */ | |
8130 | if (*s != '.') | |
8131 | { | |
8132 | insn_error = "unrecognized opcode"; | |
8133 | return; | |
8134 | } | |
8135 | ||
8136 | /* Lookup the instruction in the hash table. */ | |
8137 | *s++ = '\0'; | |
8138 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8139 | { | |
8140 | insn_error = "unrecognized opcode"; | |
8141 | return; | |
8142 | } | |
252b5132 RH |
8143 | } |
8144 | ||
8145 | argsStart = s; | |
8146 | for (;;) | |
8147 | { | |
b34976b6 | 8148 | bfd_boolean ok; |
252b5132 RH |
8149 | |
8150 | assert (strcmp (insn->name, str) == 0); | |
8151 | ||
1f25f5d3 CD |
8152 | if (OPCODE_IS_MEMBER (insn, |
8153 | (mips_opts.isa | |
3396de36 | 8154 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 8155 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
98d3f06f | 8156 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
1f25f5d3 | 8157 | mips_arch)) |
b34976b6 | 8158 | ok = TRUE; |
bdaaa2e1 | 8159 | else |
b34976b6 | 8160 | ok = FALSE; |
bdaaa2e1 | 8161 | |
252b5132 RH |
8162 | if (insn->pinfo != INSN_MACRO) |
8163 | { | |
ec68c924 | 8164 | if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 8165 | ok = FALSE; |
252b5132 RH |
8166 | } |
8167 | ||
8168 | if (! ok) | |
8169 | { | |
8170 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8171 | && strcmp (insn->name, insn[1].name) == 0) | |
8172 | { | |
8173 | ++insn; | |
8174 | continue; | |
8175 | } | |
252b5132 | 8176 | else |
beae10d5 | 8177 | { |
268f6bed L |
8178 | if (!insn_error) |
8179 | { | |
8180 | static char buf[100]; | |
316f5878 RS |
8181 | if (mips_arch_info->is_isa) |
8182 | sprintf (buf, | |
8183 | _("opcode not supported at this ISA level (%s)"), | |
8184 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8185 | else | |
8186 | sprintf (buf, | |
8187 | _("opcode not supported on this processor: %s (%s)"), | |
8188 | mips_arch_info->name, | |
8189 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8190 | insn_error = buf; |
8191 | } | |
8192 | if (save_c) | |
8193 | *(--s) = save_c; | |
2bd7f1f3 | 8194 | return; |
252b5132 | 8195 | } |
252b5132 RH |
8196 | } |
8197 | ||
8198 | ip->insn_mo = insn; | |
8199 | ip->insn_opcode = insn->match; | |
268f6bed | 8200 | insn_error = NULL; |
252b5132 RH |
8201 | for (args = insn->args;; ++args) |
8202 | { | |
deec1734 CD |
8203 | int is_mdmx; |
8204 | ||
ad8d3bb3 | 8205 | s += strspn (s, " \t"); |
deec1734 | 8206 | is_mdmx = 0; |
252b5132 RH |
8207 | switch (*args) |
8208 | { | |
8209 | case '\0': /* end of args */ | |
8210 | if (*s == '\0') | |
8211 | return; | |
8212 | break; | |
8213 | ||
8214 | case ',': | |
8215 | if (*s++ == *args) | |
8216 | continue; | |
8217 | s--; | |
8218 | switch (*++args) | |
8219 | { | |
8220 | case 'r': | |
8221 | case 'v': | |
38487616 | 8222 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8223 | continue; |
8224 | ||
8225 | case 'w': | |
38487616 TS |
8226 | ip->insn_opcode |= lastregno << OP_SH_RT; |
8227 | continue; | |
8228 | ||
252b5132 | 8229 | case 'W': |
38487616 | 8230 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8231 | continue; |
8232 | ||
8233 | case 'V': | |
38487616 | 8234 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8235 | continue; |
8236 | } | |
8237 | break; | |
8238 | ||
8239 | case '(': | |
8240 | /* Handle optional base register. | |
8241 | Either the base register is omitted or | |
bdaaa2e1 | 8242 | we must have a left paren. */ |
252b5132 RH |
8243 | /* This is dependent on the next operand specifier |
8244 | is a base register specification. */ | |
8245 | assert (args[1] == 'b' || args[1] == '5' | |
8246 | || args[1] == '-' || args[1] == '4'); | |
8247 | if (*s == '\0') | |
8248 | return; | |
8249 | ||
8250 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8251 | case '[': |
8252 | case ']': | |
252b5132 RH |
8253 | if (*s++ == *args) |
8254 | continue; | |
8255 | break; | |
8256 | ||
8257 | case '<': /* must be at least one digit */ | |
8258 | /* | |
8259 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8260 | * than 31 or less than 0, then the shift amount should be |
8261 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8262 | * We issue a warning and mask out all but the low 5 bits. |
8263 | */ | |
8264 | my_getExpression (&imm_expr, s); | |
8265 | check_absolute_expr (ip, &imm_expr); | |
8266 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8267 | { | |
793b27f4 TS |
8268 | as_warn (_("Improper shift amount (%lu)"), |
8269 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8270 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
252b5132 | 8271 | } |
38487616 | 8272 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
252b5132 RH |
8273 | imm_expr.X_op = O_absent; |
8274 | s = expr_end; | |
8275 | continue; | |
8276 | ||
8277 | case '>': /* shift amount minus 32 */ | |
8278 | my_getExpression (&imm_expr, s); | |
8279 | check_absolute_expr (ip, &imm_expr); | |
8280 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8281 | || (unsigned long) imm_expr.X_add_number > 63) | |
8282 | break; | |
38487616 | 8283 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
252b5132 RH |
8284 | imm_expr.X_op = O_absent; |
8285 | s = expr_end; | |
8286 | continue; | |
8287 | ||
252b5132 RH |
8288 | case 'k': /* cache code */ |
8289 | case 'h': /* prefx code */ | |
8290 | my_getExpression (&imm_expr, s); | |
8291 | check_absolute_expr (ip, &imm_expr); | |
8292 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8293 | { | |
8294 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8295 | ip->insn_mo->name, | |
8296 | (unsigned long) imm_expr.X_add_number); | |
8297 | imm_expr.X_add_number &= 0x1f; | |
8298 | } | |
8299 | if (*args == 'k') | |
8300 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
8301 | else | |
8302 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
8303 | imm_expr.X_op = O_absent; | |
8304 | s = expr_end; | |
8305 | continue; | |
8306 | ||
8307 | case 'c': /* break code */ | |
8308 | my_getExpression (&imm_expr, s); | |
8309 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8310 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8311 | { |
793b27f4 TS |
8312 | as_warn (_("Illegal break code (%lu)"), |
8313 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8314 | imm_expr.X_add_number &= OP_MASK_CODE; |
252b5132 | 8315 | } |
38487616 | 8316 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
252b5132 RH |
8317 | imm_expr.X_op = O_absent; |
8318 | s = expr_end; | |
8319 | continue; | |
8320 | ||
8321 | case 'q': /* lower break code */ | |
8322 | my_getExpression (&imm_expr, s); | |
8323 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8324 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8325 | { |
793b27f4 TS |
8326 | as_warn (_("Illegal lower break code (%lu)"), |
8327 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8328 | imm_expr.X_add_number &= OP_MASK_CODE2; |
252b5132 | 8329 | } |
38487616 | 8330 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
252b5132 RH |
8331 | imm_expr.X_op = O_absent; |
8332 | s = expr_end; | |
8333 | continue; | |
8334 | ||
4372b673 | 8335 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8336 | my_getExpression (&imm_expr, s); |
156c2f8b | 8337 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8338 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8339 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8340 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8341 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
252b5132 RH |
8342 | imm_expr.X_op = O_absent; |
8343 | s = expr_end; | |
8344 | continue; | |
8345 | ||
98d3f06f | 8346 | case 'C': /* Coprocessor code */ |
beae10d5 | 8347 | my_getExpression (&imm_expr, s); |
252b5132 | 8348 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8349 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8350 | { |
793b27f4 TS |
8351 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8352 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8353 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8354 | } |
beae10d5 KH |
8355 | ip->insn_opcode |= imm_expr.X_add_number; |
8356 | imm_expr.X_op = O_absent; | |
8357 | s = expr_end; | |
8358 | continue; | |
252b5132 | 8359 | |
4372b673 NC |
8360 | case 'J': /* 19-bit wait code. */ |
8361 | my_getExpression (&imm_expr, s); | |
8362 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8363 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8364 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8365 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8366 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
4372b673 NC |
8367 | imm_expr.X_op = O_absent; |
8368 | s = expr_end; | |
8369 | continue; | |
8370 | ||
252b5132 | 8371 | case 'P': /* Performance register */ |
beae10d5 | 8372 | my_getExpression (&imm_expr, s); |
252b5132 | 8373 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8374 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 8375 | { |
793b27f4 TS |
8376 | as_warn (_("Invalid performance register (%lu)"), |
8377 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8378 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
252b5132 | 8379 | } |
38487616 | 8380 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
beae10d5 KH |
8381 | imm_expr.X_op = O_absent; |
8382 | s = expr_end; | |
8383 | continue; | |
252b5132 RH |
8384 | |
8385 | case 'b': /* base register */ | |
8386 | case 'd': /* destination register */ | |
8387 | case 's': /* source register */ | |
8388 | case 't': /* target register */ | |
8389 | case 'r': /* both target and source */ | |
8390 | case 'v': /* both dest and source */ | |
8391 | case 'w': /* both dest and target */ | |
8392 | case 'E': /* coprocessor target register */ | |
8393 | case 'G': /* coprocessor destination register */ | |
8394 | case 'x': /* ignore register name */ | |
8395 | case 'z': /* must be zero register */ | |
4372b673 | 8396 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8397 | s_reset = s; |
8398 | if (s[0] == '$') | |
8399 | { | |
8400 | ||
3882b010 | 8401 | if (ISDIGIT (s[1])) |
252b5132 RH |
8402 | { |
8403 | ++s; | |
8404 | regno = 0; | |
8405 | do | |
8406 | { | |
8407 | regno *= 10; | |
8408 | regno += *s - '0'; | |
8409 | ++s; | |
8410 | } | |
3882b010 | 8411 | while (ISDIGIT (*s)); |
252b5132 RH |
8412 | if (regno > 31) |
8413 | as_bad (_("Invalid register number (%d)"), regno); | |
8414 | } | |
8415 | else if (*args == 'E' || *args == 'G') | |
8416 | goto notreg; | |
8417 | else | |
8418 | { | |
76db943d TS |
8419 | if (s[1] == 'r' && s[2] == 'a') |
8420 | { | |
8421 | s += 3; | |
8422 | regno = RA; | |
8423 | } | |
8424 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8425 | { |
8426 | s += 3; | |
8427 | regno = FP; | |
8428 | } | |
8429 | else if (s[1] == 's' && s[2] == 'p') | |
8430 | { | |
8431 | s += 3; | |
8432 | regno = SP; | |
8433 | } | |
8434 | else if (s[1] == 'g' && s[2] == 'p') | |
8435 | { | |
8436 | s += 3; | |
8437 | regno = GP; | |
8438 | } | |
8439 | else if (s[1] == 'a' && s[2] == 't') | |
8440 | { | |
8441 | s += 3; | |
8442 | regno = AT; | |
8443 | } | |
8444 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8445 | { | |
8446 | s += 4; | |
8447 | regno = KT0; | |
8448 | } | |
8449 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8450 | { | |
8451 | s += 4; | |
8452 | regno = KT1; | |
8453 | } | |
85b51719 TS |
8454 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8455 | { | |
8456 | s += 5; | |
8457 | regno = ZERO; | |
8458 | } | |
252b5132 RH |
8459 | else if (itbl_have_entries) |
8460 | { | |
8461 | char *p, *n; | |
d7ba4a77 | 8462 | unsigned long r; |
252b5132 | 8463 | |
d7ba4a77 | 8464 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8465 | n = itbl_get_field (&p); /* n is name */ |
8466 | ||
d7ba4a77 ILT |
8467 | /* See if this is a register defined in an |
8468 | itbl entry. */ | |
8469 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8470 | { |
8471 | /* Get_field advances to the start of | |
8472 | the next field, so we need to back | |
d7ba4a77 | 8473 | rack to the end of the last field. */ |
bdaaa2e1 | 8474 | if (p) |
252b5132 | 8475 | s = p - 1; |
bdaaa2e1 | 8476 | else |
d7ba4a77 | 8477 | s = strchr (s, '\0'); |
252b5132 RH |
8478 | regno = r; |
8479 | } | |
8480 | else | |
8481 | goto notreg; | |
beae10d5 | 8482 | } |
252b5132 RH |
8483 | else |
8484 | goto notreg; | |
8485 | } | |
8486 | if (regno == AT | |
8487 | && ! mips_opts.noat | |
8488 | && *args != 'E' | |
8489 | && *args != 'G') | |
8490 | as_warn (_("Used $at without \".set noat\"")); | |
8491 | c = *args; | |
8492 | if (*s == ' ') | |
f9419b05 | 8493 | ++s; |
252b5132 RH |
8494 | if (args[1] != *s) |
8495 | { | |
8496 | if (c == 'r' || c == 'v' || c == 'w') | |
8497 | { | |
8498 | regno = lastregno; | |
8499 | s = s_reset; | |
f9419b05 | 8500 | ++args; |
252b5132 RH |
8501 | } |
8502 | } | |
8503 | /* 'z' only matches $0. */ | |
8504 | if (c == 'z' && regno != 0) | |
8505 | break; | |
8506 | ||
bdaaa2e1 KH |
8507 | /* Now that we have assembled one operand, we use the args string |
8508 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8509 | switch (c) |
8510 | { | |
8511 | case 'r': | |
8512 | case 's': | |
8513 | case 'v': | |
8514 | case 'b': | |
38487616 | 8515 | ip->insn_opcode |= regno << OP_SH_RS; |
252b5132 RH |
8516 | break; |
8517 | case 'd': | |
8518 | case 'G': | |
38487616 | 8519 | ip->insn_opcode |= regno << OP_SH_RD; |
252b5132 | 8520 | break; |
4372b673 | 8521 | case 'U': |
38487616 TS |
8522 | ip->insn_opcode |= regno << OP_SH_RD; |
8523 | ip->insn_opcode |= regno << OP_SH_RT; | |
4372b673 | 8524 | break; |
252b5132 RH |
8525 | case 'w': |
8526 | case 't': | |
8527 | case 'E': | |
38487616 | 8528 | ip->insn_opcode |= regno << OP_SH_RT; |
252b5132 RH |
8529 | break; |
8530 | case 'x': | |
8531 | /* This case exists because on the r3000 trunc | |
8532 | expands into a macro which requires a gp | |
8533 | register. On the r6000 or r4000 it is | |
8534 | assembled into a single instruction which | |
8535 | ignores the register. Thus the insn version | |
8536 | is MIPS_ISA2 and uses 'x', and the macro | |
8537 | version is MIPS_ISA1 and uses 't'. */ | |
8538 | break; | |
8539 | case 'z': | |
8540 | /* This case is for the div instruction, which | |
8541 | acts differently if the destination argument | |
8542 | is $0. This only matches $0, and is checked | |
8543 | outside the switch. */ | |
8544 | break; | |
8545 | case 'D': | |
8546 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8547 | break; | |
8548 | /* What about all other operands like 'i', which | |
8549 | can be specified in the opcode table? */ | |
8550 | } | |
8551 | lastregno = regno; | |
8552 | continue; | |
8553 | } | |
8554 | notreg: | |
8555 | switch (*args++) | |
8556 | { | |
8557 | case 'r': | |
8558 | case 'v': | |
38487616 | 8559 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8560 | continue; |
8561 | case 'w': | |
38487616 | 8562 | ip->insn_opcode |= lastregno << OP_SH_RT; |
252b5132 RH |
8563 | continue; |
8564 | } | |
8565 | break; | |
8566 | ||
deec1734 CD |
8567 | case 'O': /* MDMX alignment immediate constant. */ |
8568 | my_getExpression (&imm_expr, s); | |
8569 | check_absolute_expr (ip, &imm_expr); | |
8570 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
8571 | { | |
8572 | as_warn ("Improper align amount (%ld), using low bits", | |
8573 | (long) imm_expr.X_add_number); | |
8574 | imm_expr.X_add_number &= OP_MASK_ALN; | |
8575 | } | |
8576 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN; | |
8577 | imm_expr.X_op = O_absent; | |
8578 | s = expr_end; | |
8579 | continue; | |
8580 | ||
8581 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8582 | if (s[0] != '$') | |
8583 | { | |
8584 | /* MDMX Immediate. */ | |
8585 | my_getExpression (&imm_expr, s); | |
8586 | check_absolute_expr (ip, &imm_expr); | |
8587 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
8588 | { | |
8589 | as_warn (_("Invalid MDMX Immediate (%ld)"), | |
8590 | (long) imm_expr.X_add_number); | |
8591 | imm_expr.X_add_number &= OP_MASK_FT; | |
8592 | } | |
8593 | imm_expr.X_add_number &= OP_MASK_FT; | |
8594 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8595 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8596 | else | |
8597 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
8598 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT; | |
8599 | imm_expr.X_op = O_absent; | |
8600 | s = expr_end; | |
8601 | continue; | |
8602 | } | |
8603 | /* Not MDMX Immediate. Fall through. */ | |
8604 | case 'X': /* MDMX destination register. */ | |
8605 | case 'Y': /* MDMX source register. */ | |
8606 | case 'Z': /* MDMX target register. */ | |
8607 | is_mdmx = 1; | |
252b5132 RH |
8608 | case 'D': /* floating point destination register */ |
8609 | case 'S': /* floating point source register */ | |
8610 | case 'T': /* floating point target register */ | |
8611 | case 'R': /* floating point source register */ | |
8612 | case 'V': | |
8613 | case 'W': | |
8614 | s_reset = s; | |
deec1734 CD |
8615 | /* Accept $fN for FP and MDMX register numbers, and in |
8616 | addition accept $vN for MDMX register numbers. */ | |
8617 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8618 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8619 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8620 | { |
8621 | s += 2; | |
8622 | regno = 0; | |
8623 | do | |
8624 | { | |
8625 | regno *= 10; | |
8626 | regno += *s - '0'; | |
8627 | ++s; | |
8628 | } | |
3882b010 | 8629 | while (ISDIGIT (*s)); |
252b5132 RH |
8630 | |
8631 | if (regno > 31) | |
8632 | as_bad (_("Invalid float register number (%d)"), regno); | |
8633 | ||
8634 | if ((regno & 1) != 0 | |
ca4e0257 | 8635 | && HAVE_32BIT_FPRS |
252b5132 RH |
8636 | && ! (strcmp (str, "mtc1") == 0 |
8637 | || strcmp (str, "mfc1") == 0 | |
8638 | || strcmp (str, "lwc1") == 0 | |
8639 | || strcmp (str, "swc1") == 0 | |
8640 | || strcmp (str, "l.s") == 0 | |
8641 | || strcmp (str, "s.s") == 0)) | |
8642 | as_warn (_("Float register should be even, was %d"), | |
8643 | regno); | |
8644 | ||
8645 | c = *args; | |
8646 | if (*s == ' ') | |
f9419b05 | 8647 | ++s; |
252b5132 RH |
8648 | if (args[1] != *s) |
8649 | { | |
8650 | if (c == 'V' || c == 'W') | |
8651 | { | |
8652 | regno = lastregno; | |
8653 | s = s_reset; | |
f9419b05 | 8654 | ++args; |
252b5132 RH |
8655 | } |
8656 | } | |
8657 | switch (c) | |
8658 | { | |
8659 | case 'D': | |
deec1734 | 8660 | case 'X': |
38487616 | 8661 | ip->insn_opcode |= regno << OP_SH_FD; |
252b5132 RH |
8662 | break; |
8663 | case 'V': | |
8664 | case 'S': | |
deec1734 | 8665 | case 'Y': |
38487616 | 8666 | ip->insn_opcode |= regno << OP_SH_FS; |
252b5132 | 8667 | break; |
deec1734 CD |
8668 | case 'Q': |
8669 | /* This is like 'Z', but also needs to fix the MDMX | |
8670 | vector/scalar select bits. Note that the | |
8671 | scalar immediate case is handled above. */ | |
8672 | if (*s == '[') | |
8673 | { | |
8674 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8675 | int max_el = (is_qh ? 3 : 7); | |
8676 | s++; | |
8677 | my_getExpression(&imm_expr, s); | |
8678 | check_absolute_expr (ip, &imm_expr); | |
8679 | s = expr_end; | |
8680 | if (imm_expr.X_add_number > max_el) | |
8681 | as_bad(_("Bad element selector %ld"), | |
8682 | (long) imm_expr.X_add_number); | |
8683 | imm_expr.X_add_number &= max_el; | |
8684 | ip->insn_opcode |= (imm_expr.X_add_number | |
8685 | << (OP_SH_VSEL + | |
8686 | (is_qh ? 2 : 1))); | |
8687 | if (*s != ']') | |
8688 | as_warn(_("Expecting ']' found '%s'"), s); | |
8689 | else | |
8690 | s++; | |
8691 | } | |
8692 | else | |
8693 | { | |
8694 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8695 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8696 | << OP_SH_VSEL); | |
8697 | else | |
8698 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8699 | OP_SH_VSEL); | |
8700 | } | |
8701 | /* Fall through */ | |
252b5132 RH |
8702 | case 'W': |
8703 | case 'T': | |
deec1734 | 8704 | case 'Z': |
38487616 | 8705 | ip->insn_opcode |= regno << OP_SH_FT; |
252b5132 RH |
8706 | break; |
8707 | case 'R': | |
38487616 | 8708 | ip->insn_opcode |= regno << OP_SH_FR; |
252b5132 RH |
8709 | break; |
8710 | } | |
8711 | lastregno = regno; | |
8712 | continue; | |
8713 | } | |
8714 | ||
252b5132 RH |
8715 | switch (*args++) |
8716 | { | |
8717 | case 'V': | |
38487616 | 8718 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8719 | continue; |
8720 | case 'W': | |
38487616 | 8721 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8722 | continue; |
8723 | } | |
8724 | break; | |
8725 | ||
8726 | case 'I': | |
8727 | my_getExpression (&imm_expr, s); | |
8728 | if (imm_expr.X_op != O_big | |
8729 | && imm_expr.X_op != O_constant) | |
8730 | insn_error = _("absolute expression required"); | |
8731 | s = expr_end; | |
8732 | continue; | |
8733 | ||
8734 | case 'A': | |
8735 | my_getExpression (&offset_expr, s); | |
f6688943 | 8736 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8737 | s = expr_end; |
8738 | continue; | |
8739 | ||
8740 | case 'F': | |
8741 | case 'L': | |
8742 | case 'f': | |
8743 | case 'l': | |
8744 | { | |
8745 | int f64; | |
ca4e0257 | 8746 | int using_gprs; |
252b5132 RH |
8747 | char *save_in; |
8748 | char *err; | |
8749 | unsigned char temp[8]; | |
8750 | int len; | |
8751 | unsigned int length; | |
8752 | segT seg; | |
8753 | subsegT subseg; | |
8754 | char *p; | |
8755 | ||
8756 | /* These only appear as the last operand in an | |
8757 | instruction, and every instruction that accepts | |
8758 | them in any variant accepts them in all variants. | |
8759 | This means we don't have to worry about backing out | |
8760 | any changes if the instruction does not match. | |
8761 | ||
8762 | The difference between them is the size of the | |
8763 | floating point constant and where it goes. For 'F' | |
8764 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8765 | is 32 bits. Where the constant is placed is based | |
8766 | on how the MIPS assembler does things: | |
8767 | F -- .rdata | |
8768 | L -- .lit8 | |
8769 | f -- immediate value | |
8770 | l -- .lit4 | |
8771 | ||
8772 | The .lit4 and .lit8 sections are only used if | |
8773 | permitted by the -G argument. | |
8774 | ||
8775 | When generating embedded PIC code, we use the | |
8776 | .lit8 section but not the .lit4 section (we can do | |
8777 | .lit4 inline easily; we need to put .lit8 | |
8778 | somewhere in the data segment, and using .lit8 | |
8779 | permits the linker to eventually combine identical | |
ca4e0257 RS |
8780 | .lit8 entries). |
8781 | ||
8782 | The code below needs to know whether the target register | |
8783 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8784 | 'F' are used with GPR-based instructions and 'l' and | |
8785 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8786 | |
8787 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8788 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8789 | |
8790 | save_in = input_line_pointer; | |
8791 | input_line_pointer = s; | |
8792 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8793 | length = len; | |
8794 | s = input_line_pointer; | |
8795 | input_line_pointer = save_in; | |
8796 | if (err != NULL && *err != '\0') | |
8797 | { | |
8798 | as_bad (_("Bad floating point constant: %s"), err); | |
8799 | memset (temp, '\0', sizeof temp); | |
8800 | length = f64 ? 8 : 4; | |
8801 | } | |
8802 | ||
156c2f8b | 8803 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8804 | |
8805 | if (*args == 'f' | |
8806 | || (*args == 'l' | |
8807 | && (! USE_GLOBAL_POINTER_OPT | |
8808 | || mips_pic == EMBEDDED_PIC | |
8809 | || g_switch_value < 4 | |
8810 | || (temp[0] == 0 && temp[1] == 0) | |
8811 | || (temp[2] == 0 && temp[3] == 0)))) | |
8812 | { | |
8813 | imm_expr.X_op = O_constant; | |
8814 | if (! target_big_endian) | |
8815 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8816 | else | |
8817 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8818 | } | |
8819 | else if (length > 4 | |
119d663a | 8820 | && ! mips_disable_float_construction |
ca4e0257 RS |
8821 | /* Constants can only be constructed in GPRs and |
8822 | copied to FPRs if the GPRs are at least as wide | |
8823 | as the FPRs. Force the constant into memory if | |
8824 | we are using 64-bit FPRs but the GPRs are only | |
8825 | 32 bits wide. */ | |
8826 | && (using_gprs | |
8827 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8828 | && ((temp[0] == 0 && temp[1] == 0) |
8829 | || (temp[2] == 0 && temp[3] == 0)) | |
8830 | && ((temp[4] == 0 && temp[5] == 0) | |
8831 | || (temp[6] == 0 && temp[7] == 0))) | |
8832 | { | |
ca4e0257 RS |
8833 | /* The value is simple enough to load with a couple of |
8834 | instructions. If using 32-bit registers, set | |
8835 | imm_expr to the high order 32 bits and offset_expr to | |
8836 | the low order 32 bits. Otherwise, set imm_expr to | |
8837 | the entire 64 bit constant. */ | |
8838 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8839 | { |
8840 | imm_expr.X_op = O_constant; | |
8841 | offset_expr.X_op = O_constant; | |
8842 | if (! target_big_endian) | |
8843 | { | |
8844 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8845 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8846 | } | |
8847 | else | |
8848 | { | |
8849 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8850 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8851 | } | |
8852 | if (offset_expr.X_add_number == 0) | |
8853 | offset_expr.X_op = O_absent; | |
8854 | } | |
8855 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8856 | { | |
8857 | imm_expr.X_op = O_constant; | |
8858 | if (! target_big_endian) | |
8859 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8860 | else | |
8861 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8862 | } | |
8863 | else | |
8864 | { | |
8865 | imm_expr.X_op = O_big; | |
8866 | imm_expr.X_add_number = 4; | |
8867 | if (! target_big_endian) | |
8868 | { | |
8869 | generic_bignum[0] = bfd_getl16 (temp); | |
8870 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8871 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8872 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8873 | } | |
8874 | else | |
8875 | { | |
8876 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8877 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8878 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8879 | generic_bignum[3] = bfd_getb16 (temp); | |
8880 | } | |
8881 | } | |
8882 | } | |
8883 | else | |
8884 | { | |
8885 | const char *newname; | |
8886 | segT new_seg; | |
8887 | ||
8888 | /* Switch to the right section. */ | |
8889 | seg = now_seg; | |
8890 | subseg = now_subseg; | |
8891 | switch (*args) | |
8892 | { | |
8893 | default: /* unused default case avoids warnings. */ | |
8894 | case 'L': | |
8895 | newname = RDATA_SECTION_NAME; | |
bb2d6cd7 GK |
8896 | if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
8897 | || mips_pic == EMBEDDED_PIC) | |
252b5132 RH |
8898 | newname = ".lit8"; |
8899 | break; | |
8900 | case 'F': | |
bb2d6cd7 GK |
8901 | if (mips_pic == EMBEDDED_PIC) |
8902 | newname = ".lit8"; | |
8903 | else | |
8904 | newname = RDATA_SECTION_NAME; | |
252b5132 RH |
8905 | break; |
8906 | case 'l': | |
8907 | assert (!USE_GLOBAL_POINTER_OPT | |
8908 | || g_switch_value >= 4); | |
8909 | newname = ".lit4"; | |
8910 | break; | |
8911 | } | |
8912 | new_seg = subseg_new (newname, (subsegT) 0); | |
8913 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8914 | bfd_set_section_flags (stdoutput, new_seg, | |
8915 | (SEC_ALLOC | |
8916 | | SEC_LOAD | |
8917 | | SEC_READONLY | |
8918 | | SEC_DATA)); | |
8919 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
8920 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8921 | && strcmp (TARGET_OS, "elf") != 0) | |
8922 | record_alignment (new_seg, 4); | |
8923 | else | |
8924 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
8925 | if (seg == now_seg) | |
8926 | as_bad (_("Can't use floating point insn in this section")); | |
8927 | ||
8928 | /* Set the argument to the current address in the | |
8929 | section. */ | |
8930 | offset_expr.X_op = O_symbol; | |
8931 | offset_expr.X_add_symbol = | |
8932 | symbol_new ("L0\001", now_seg, | |
8933 | (valueT) frag_now_fix (), frag_now); | |
8934 | offset_expr.X_add_number = 0; | |
8935 | ||
8936 | /* Put the floating point number into the section. */ | |
8937 | p = frag_more ((int) length); | |
8938 | memcpy (p, temp, length); | |
8939 | ||
8940 | /* Switch back to the original section. */ | |
8941 | subseg_set (seg, subseg); | |
8942 | } | |
8943 | } | |
8944 | continue; | |
8945 | ||
8946 | case 'i': /* 16 bit unsigned immediate */ | |
8947 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 8948 | *imm_reloc = BFD_RELOC_LO16; |
252b5132 | 8949 | c = my_getSmallExpression (&imm_expr, s); |
fb1b3232 | 8950 | if (c != S_EX_NONE) |
252b5132 | 8951 | { |
fb1b3232 | 8952 | if (c != S_EX_LO) |
252b5132 | 8953 | { |
fdb987ee RS |
8954 | if (c == S_EX_HI) |
8955 | { | |
8956 | *imm_reloc = BFD_RELOC_HI16_S; | |
b34976b6 | 8957 | imm_unmatched_hi = TRUE; |
fdb987ee | 8958 | } |
ad8d3bb3 | 8959 | #ifdef OBJ_ELF |
fb1b3232 | 8960 | else if (c == S_EX_HIGHEST) |
98d3f06f | 8961 | *imm_reloc = BFD_RELOC_MIPS_HIGHEST; |
fb1b3232 | 8962 | else if (c == S_EX_HIGHER) |
98d3f06f | 8963 | *imm_reloc = BFD_RELOC_MIPS_HIGHER; |
ad8d3bb3 TS |
8964 | else if (c == S_EX_GP_REL) |
8965 | { | |
8966 | /* This occurs in NewABI only. */ | |
8967 | c = my_getSmallExpression (&imm_expr, s); | |
8968 | if (c != S_EX_NEG) | |
8969 | as_bad (_("bad composition of relocations")); | |
8970 | else | |
8971 | { | |
8972 | c = my_getSmallExpression (&imm_expr, s); | |
8973 | if (c != S_EX_LO) | |
8974 | as_bad (_("bad composition of relocations")); | |
8975 | else | |
8976 | { | |
8977 | imm_reloc[0] = BFD_RELOC_GPREL16; | |
8978 | imm_reloc[1] = BFD_RELOC_MIPS_SUB; | |
8979 | imm_reloc[2] = BFD_RELOC_LO16; | |
8980 | } | |
8981 | } | |
8982 | } | |
8983 | #endif | |
252b5132 | 8984 | else |
f6688943 | 8985 | *imm_reloc = BFD_RELOC_HI16; |
252b5132 RH |
8986 | } |
8987 | else if (imm_expr.X_op == O_constant) | |
8988 | imm_expr.X_add_number &= 0xffff; | |
8989 | } | |
8990 | if (*args == 'i') | |
8991 | { | |
fb1b3232 | 8992 | if ((c == S_EX_NONE && imm_expr.X_op != O_constant) |
252b5132 | 8993 | || ((imm_expr.X_add_number < 0 |
beae10d5 KH |
8994 | || imm_expr.X_add_number >= 0x10000) |
8995 | && imm_expr.X_op == O_constant)) | |
252b5132 RH |
8996 | { |
8997 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8998 | !strcmp (insn->name, insn[1].name)) | |
8999 | break; | |
2ae7e77b AH |
9000 | if (imm_expr.X_op == O_constant |
9001 | || imm_expr.X_op == O_big) | |
252b5132 RH |
9002 | as_bad (_("16 bit expression not in range 0..65535")); |
9003 | } | |
9004 | } | |
9005 | else | |
9006 | { | |
9007 | int more; | |
9008 | offsetT max; | |
9009 | ||
9010 | /* The upper bound should be 0x8000, but | |
9011 | unfortunately the MIPS assembler accepts numbers | |
9012 | from 0x8000 to 0xffff and sign extends them, and | |
9013 | we want to be compatible. We only permit this | |
9014 | extended range for an instruction which does not | |
9015 | provide any further alternates, since those | |
9016 | alternates may handle other cases. People should | |
9017 | use the numbers they mean, rather than relying on | |
9018 | a mysterious sign extension. */ | |
9019 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9020 | strcmp (insn->name, insn[1].name) == 0); | |
9021 | if (more) | |
9022 | max = 0x8000; | |
9023 | else | |
9024 | max = 0x10000; | |
fb1b3232 | 9025 | if ((c == S_EX_NONE && imm_expr.X_op != O_constant) |
252b5132 | 9026 | || ((imm_expr.X_add_number < -0x8000 |
beae10d5 KH |
9027 | || imm_expr.X_add_number >= max) |
9028 | && imm_expr.X_op == O_constant) | |
252b5132 RH |
9029 | || (more |
9030 | && imm_expr.X_add_number < 0 | |
ca4e0257 | 9031 | && HAVE_64BIT_GPRS |
252b5132 RH |
9032 | && imm_expr.X_unsigned |
9033 | && sizeof (imm_expr.X_add_number) <= 4)) | |
9034 | { | |
9035 | if (more) | |
9036 | break; | |
2ae7e77b AH |
9037 | if (imm_expr.X_op == O_constant |
9038 | || imm_expr.X_op == O_big) | |
252b5132 RH |
9039 | as_bad (_("16 bit expression not in range -32768..32767")); |
9040 | } | |
9041 | } | |
9042 | s = expr_end; | |
9043 | continue; | |
9044 | ||
9045 | case 'o': /* 16 bit offset */ | |
9046 | c = my_getSmallExpression (&offset_expr, s); | |
9047 | ||
9048 | /* If this value won't fit into a 16 bit offset, then go | |
9049 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9050 | code pattern. */ |
fb1b3232 | 9051 | if (c == S_EX_NONE |
252b5132 RH |
9052 | && (offset_expr.X_op != O_constant |
9053 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9054 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9055 | break; |
9056 | ||
fb1b3232 | 9057 | if (c == S_EX_HI) |
252b5132 RH |
9058 | { |
9059 | if (offset_expr.X_op != O_constant) | |
9060 | break; | |
9061 | offset_expr.X_add_number = | |
9062 | (offset_expr.X_add_number >> 16) & 0xffff; | |
9063 | } | |
f6688943 | 9064 | *offset_reloc = BFD_RELOC_LO16; |
252b5132 RH |
9065 | s = expr_end; |
9066 | continue; | |
9067 | ||
9068 | case 'p': /* pc relative offset */ | |
af6ae2ad | 9069 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9070 | my_getExpression (&offset_expr, s); |
9071 | s = expr_end; | |
9072 | continue; | |
9073 | ||
9074 | case 'u': /* upper 16 bits */ | |
9075 | c = my_getSmallExpression (&imm_expr, s); | |
f6688943 | 9076 | *imm_reloc = BFD_RELOC_LO16; |
e7d556df | 9077 | if (c != S_EX_NONE) |
252b5132 | 9078 | { |
fb1b3232 | 9079 | if (c != S_EX_LO) |
252b5132 | 9080 | { |
fdb987ee | 9081 | if (c == S_EX_HI) |
252b5132 | 9082 | { |
f6688943 | 9083 | *imm_reloc = BFD_RELOC_HI16_S; |
b34976b6 | 9084 | imm_unmatched_hi = TRUE; |
252b5132 | 9085 | } |
645dc66c TS |
9086 | #ifdef OBJ_ELF |
9087 | else if (c == S_EX_HIGHEST) | |
98d3f06f | 9088 | *imm_reloc = BFD_RELOC_MIPS_HIGHEST; |
ad8d3bb3 TS |
9089 | else if (c == S_EX_GP_REL) |
9090 | { | |
9091 | /* This occurs in NewABI only. */ | |
9092 | c = my_getSmallExpression (&imm_expr, s); | |
9093 | if (c != S_EX_NEG) | |
9094 | as_bad (_("bad composition of relocations")); | |
9095 | else | |
9096 | { | |
9097 | c = my_getSmallExpression (&imm_expr, s); | |
9098 | if (c != S_EX_HI) | |
9099 | as_bad (_("bad composition of relocations")); | |
9100 | else | |
9101 | { | |
9102 | imm_reloc[0] = BFD_RELOC_GPREL16; | |
9103 | imm_reloc[1] = BFD_RELOC_MIPS_SUB; | |
9104 | imm_reloc[2] = BFD_RELOC_HI16_S; | |
9105 | } | |
9106 | } | |
9107 | } | |
9108 | #endif | |
252b5132 | 9109 | else |
f6688943 | 9110 | *imm_reloc = BFD_RELOC_HI16; |
252b5132 RH |
9111 | } |
9112 | else if (imm_expr.X_op == O_constant) | |
9113 | imm_expr.X_add_number &= 0xffff; | |
9114 | } | |
fdb987ee RS |
9115 | else if (imm_expr.X_op == O_constant |
9116 | && (imm_expr.X_add_number < 0 | |
9117 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
9118 | as_bad (_("lui expression not in range 0..65535")); |
9119 | s = expr_end; | |
9120 | continue; | |
9121 | ||
9122 | case 'a': /* 26 bit address */ | |
9123 | my_getExpression (&offset_expr, s); | |
9124 | s = expr_end; | |
f6688943 | 9125 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
9126 | continue; |
9127 | ||
9128 | case 'N': /* 3 bit branch condition code */ | |
9129 | case 'M': /* 3 bit compare condition code */ | |
9130 | if (strncmp (s, "$fcc", 4) != 0) | |
9131 | break; | |
9132 | s += 4; | |
9133 | regno = 0; | |
9134 | do | |
9135 | { | |
9136 | regno *= 10; | |
9137 | regno += *s - '0'; | |
9138 | ++s; | |
9139 | } | |
3882b010 | 9140 | while (ISDIGIT (*s)); |
252b5132 RH |
9141 | if (regno > 7) |
9142 | as_bad (_("invalid condition code register $fcc%d"), regno); | |
9143 | if (*args == 'N') | |
9144 | ip->insn_opcode |= regno << OP_SH_BCC; | |
9145 | else | |
9146 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 9147 | continue; |
252b5132 | 9148 | |
156c2f8b NC |
9149 | case 'H': |
9150 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9151 | s += 2; | |
3882b010 | 9152 | if (ISDIGIT (*s)) |
156c2f8b NC |
9153 | { |
9154 | c = 0; | |
9155 | do | |
9156 | { | |
9157 | c *= 10; | |
9158 | c += *s - '0'; | |
9159 | ++s; | |
9160 | } | |
3882b010 | 9161 | while (ISDIGIT (*s)); |
156c2f8b NC |
9162 | } |
9163 | else | |
9164 | c = 8; /* Invalid sel value. */ | |
9165 | ||
9166 | if (c > 7) | |
9167 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9168 | ip->insn_opcode |= c; | |
9169 | continue; | |
9170 | ||
60b63b72 RS |
9171 | case 'e': |
9172 | /* Must be at least one digit. */ | |
9173 | my_getExpression (&imm_expr, s); | |
9174 | check_absolute_expr (ip, &imm_expr); | |
9175 | ||
9176 | if ((unsigned long) imm_expr.X_add_number | |
9177 | > (unsigned long) OP_MASK_VECBYTE) | |
9178 | { | |
9179 | as_bad (_("bad byte vector index (%ld)"), | |
9180 | (long) imm_expr.X_add_number); | |
9181 | imm_expr.X_add_number = 0; | |
9182 | } | |
9183 | ||
9184 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; | |
9185 | imm_expr.X_op = O_absent; | |
9186 | s = expr_end; | |
9187 | continue; | |
9188 | ||
9189 | case '%': | |
9190 | my_getExpression (&imm_expr, s); | |
9191 | check_absolute_expr (ip, &imm_expr); | |
9192 | ||
9193 | if ((unsigned long) imm_expr.X_add_number | |
9194 | > (unsigned long) OP_MASK_VECALIGN) | |
9195 | { | |
9196 | as_bad (_("bad byte vector index (%ld)"), | |
9197 | (long) imm_expr.X_add_number); | |
9198 | imm_expr.X_add_number = 0; | |
9199 | } | |
9200 | ||
9201 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; | |
9202 | imm_expr.X_op = O_absent; | |
9203 | s = expr_end; | |
9204 | continue; | |
9205 | ||
252b5132 RH |
9206 | default: |
9207 | as_bad (_("bad char = '%c'\n"), *args); | |
9208 | internalError (); | |
9209 | } | |
9210 | break; | |
9211 | } | |
9212 | /* Args don't match. */ | |
9213 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9214 | !strcmp (insn->name, insn[1].name)) | |
9215 | { | |
9216 | ++insn; | |
9217 | s = argsStart; | |
268f6bed | 9218 | insn_error = _("illegal operands"); |
252b5132 RH |
9219 | continue; |
9220 | } | |
268f6bed L |
9221 | if (save_c) |
9222 | *(--s) = save_c; | |
252b5132 RH |
9223 | insn_error = _("illegal operands"); |
9224 | return; | |
9225 | } | |
9226 | } | |
9227 | ||
9228 | /* This routine assembles an instruction into its binary format when | |
9229 | assembling for the mips16. As a side effect, it sets one of the | |
9230 | global variables imm_reloc or offset_reloc to the type of | |
9231 | relocation to do if one of the operands is an address expression. | |
9232 | It also sets mips16_small and mips16_ext if the user explicitly | |
9233 | requested a small or extended instruction. */ | |
9234 | ||
9235 | static void | |
9236 | mips16_ip (str, ip) | |
9237 | char *str; | |
9238 | struct mips_cl_insn *ip; | |
9239 | { | |
9240 | char *s; | |
9241 | const char *args; | |
9242 | struct mips_opcode *insn; | |
9243 | char *argsstart; | |
9244 | unsigned int regno; | |
9245 | unsigned int lastregno = 0; | |
9246 | char *s_reset; | |
9247 | ||
9248 | insn_error = NULL; | |
9249 | ||
b34976b6 AM |
9250 | mips16_small = FALSE; |
9251 | mips16_ext = FALSE; | |
252b5132 | 9252 | |
3882b010 | 9253 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9254 | ; |
9255 | switch (*s) | |
9256 | { | |
9257 | case '\0': | |
9258 | break; | |
9259 | ||
9260 | case ' ': | |
9261 | *s++ = '\0'; | |
9262 | break; | |
9263 | ||
9264 | case '.': | |
9265 | if (s[1] == 't' && s[2] == ' ') | |
9266 | { | |
9267 | *s = '\0'; | |
b34976b6 | 9268 | mips16_small = TRUE; |
252b5132 RH |
9269 | s += 3; |
9270 | break; | |
9271 | } | |
9272 | else if (s[1] == 'e' && s[2] == ' ') | |
9273 | { | |
9274 | *s = '\0'; | |
b34976b6 | 9275 | mips16_ext = TRUE; |
252b5132 RH |
9276 | s += 3; |
9277 | break; | |
9278 | } | |
9279 | /* Fall through. */ | |
9280 | default: | |
9281 | insn_error = _("unknown opcode"); | |
9282 | return; | |
9283 | } | |
9284 | ||
9285 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9286 | mips16_small = TRUE; |
252b5132 RH |
9287 | |
9288 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9289 | { | |
9290 | insn_error = _("unrecognized opcode"); | |
9291 | return; | |
9292 | } | |
9293 | ||
9294 | argsstart = s; | |
9295 | for (;;) | |
9296 | { | |
9297 | assert (strcmp (insn->name, str) == 0); | |
9298 | ||
9299 | ip->insn_mo = insn; | |
9300 | ip->insn_opcode = insn->match; | |
b34976b6 | 9301 | ip->use_extend = FALSE; |
252b5132 | 9302 | imm_expr.X_op = O_absent; |
f6688943 TS |
9303 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9304 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9305 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 9306 | offset_expr.X_op = O_absent; |
f6688943 TS |
9307 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9308 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9309 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9310 | for (args = insn->args; 1; ++args) |
9311 | { | |
9312 | int c; | |
9313 | ||
9314 | if (*s == ' ') | |
9315 | ++s; | |
9316 | ||
9317 | /* In this switch statement we call break if we did not find | |
9318 | a match, continue if we did find a match, or return if we | |
9319 | are done. */ | |
9320 | ||
9321 | c = *args; | |
9322 | switch (c) | |
9323 | { | |
9324 | case '\0': | |
9325 | if (*s == '\0') | |
9326 | { | |
9327 | /* Stuff the immediate value in now, if we can. */ | |
9328 | if (imm_expr.X_op == O_constant | |
f6688943 | 9329 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9330 | && insn->pinfo != INSN_MACRO) |
9331 | { | |
c4e7957c | 9332 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
b34976b6 | 9333 | imm_expr.X_add_number, TRUE, mips16_small, |
252b5132 RH |
9334 | mips16_ext, &ip->insn_opcode, |
9335 | &ip->use_extend, &ip->extend); | |
9336 | imm_expr.X_op = O_absent; | |
f6688943 | 9337 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9338 | } |
9339 | ||
9340 | return; | |
9341 | } | |
9342 | break; | |
9343 | ||
9344 | case ',': | |
9345 | if (*s++ == c) | |
9346 | continue; | |
9347 | s--; | |
9348 | switch (*++args) | |
9349 | { | |
9350 | case 'v': | |
9351 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9352 | continue; | |
9353 | case 'w': | |
9354 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9355 | continue; | |
9356 | } | |
9357 | break; | |
9358 | ||
9359 | case '(': | |
9360 | case ')': | |
9361 | if (*s++ == c) | |
9362 | continue; | |
9363 | break; | |
9364 | ||
9365 | case 'v': | |
9366 | case 'w': | |
9367 | if (s[0] != '$') | |
9368 | { | |
9369 | if (c == 'v') | |
9370 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9371 | else | |
9372 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9373 | ++args; | |
9374 | continue; | |
9375 | } | |
9376 | /* Fall through. */ | |
9377 | case 'x': | |
9378 | case 'y': | |
9379 | case 'z': | |
9380 | case 'Z': | |
9381 | case '0': | |
9382 | case 'S': | |
9383 | case 'R': | |
9384 | case 'X': | |
9385 | case 'Y': | |
9386 | if (s[0] != '$') | |
9387 | break; | |
9388 | s_reset = s; | |
3882b010 | 9389 | if (ISDIGIT (s[1])) |
252b5132 RH |
9390 | { |
9391 | ++s; | |
9392 | regno = 0; | |
9393 | do | |
9394 | { | |
9395 | regno *= 10; | |
9396 | regno += *s - '0'; | |
9397 | ++s; | |
9398 | } | |
3882b010 | 9399 | while (ISDIGIT (*s)); |
252b5132 RH |
9400 | if (regno > 31) |
9401 | { | |
9402 | as_bad (_("invalid register number (%d)"), regno); | |
9403 | regno = 2; | |
9404 | } | |
9405 | } | |
9406 | else | |
9407 | { | |
76db943d TS |
9408 | if (s[1] == 'r' && s[2] == 'a') |
9409 | { | |
9410 | s += 3; | |
9411 | regno = RA; | |
9412 | } | |
9413 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9414 | { |
9415 | s += 3; | |
9416 | regno = FP; | |
9417 | } | |
9418 | else if (s[1] == 's' && s[2] == 'p') | |
9419 | { | |
9420 | s += 3; | |
9421 | regno = SP; | |
9422 | } | |
9423 | else if (s[1] == 'g' && s[2] == 'p') | |
9424 | { | |
9425 | s += 3; | |
9426 | regno = GP; | |
9427 | } | |
9428 | else if (s[1] == 'a' && s[2] == 't') | |
9429 | { | |
9430 | s += 3; | |
9431 | regno = AT; | |
9432 | } | |
9433 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9434 | { | |
9435 | s += 4; | |
9436 | regno = KT0; | |
9437 | } | |
9438 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9439 | { | |
9440 | s += 4; | |
9441 | regno = KT1; | |
9442 | } | |
85b51719 TS |
9443 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9444 | { | |
9445 | s += 5; | |
9446 | regno = ZERO; | |
9447 | } | |
252b5132 RH |
9448 | else |
9449 | break; | |
9450 | } | |
9451 | ||
9452 | if (*s == ' ') | |
9453 | ++s; | |
9454 | if (args[1] != *s) | |
9455 | { | |
9456 | if (c == 'v' || c == 'w') | |
9457 | { | |
9458 | regno = mips16_to_32_reg_map[lastregno]; | |
9459 | s = s_reset; | |
f9419b05 | 9460 | ++args; |
252b5132 RH |
9461 | } |
9462 | } | |
9463 | ||
9464 | switch (c) | |
9465 | { | |
9466 | case 'x': | |
9467 | case 'y': | |
9468 | case 'z': | |
9469 | case 'v': | |
9470 | case 'w': | |
9471 | case 'Z': | |
9472 | regno = mips32_to_16_reg_map[regno]; | |
9473 | break; | |
9474 | ||
9475 | case '0': | |
9476 | if (regno != 0) | |
9477 | regno = ILLEGAL_REG; | |
9478 | break; | |
9479 | ||
9480 | case 'S': | |
9481 | if (regno != SP) | |
9482 | regno = ILLEGAL_REG; | |
9483 | break; | |
9484 | ||
9485 | case 'R': | |
9486 | if (regno != RA) | |
9487 | regno = ILLEGAL_REG; | |
9488 | break; | |
9489 | ||
9490 | case 'X': | |
9491 | case 'Y': | |
9492 | if (regno == AT && ! mips_opts.noat) | |
9493 | as_warn (_("used $at without \".set noat\"")); | |
9494 | break; | |
9495 | ||
9496 | default: | |
9497 | internalError (); | |
9498 | } | |
9499 | ||
9500 | if (regno == ILLEGAL_REG) | |
9501 | break; | |
9502 | ||
9503 | switch (c) | |
9504 | { | |
9505 | case 'x': | |
9506 | case 'v': | |
9507 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
9508 | break; | |
9509 | case 'y': | |
9510 | case 'w': | |
9511 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
9512 | break; | |
9513 | case 'z': | |
9514 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
9515 | break; | |
9516 | case 'Z': | |
9517 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
9518 | case '0': | |
9519 | case 'S': | |
9520 | case 'R': | |
9521 | break; | |
9522 | case 'X': | |
9523 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
9524 | break; | |
9525 | case 'Y': | |
9526 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
9527 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
9528 | break; | |
9529 | default: | |
9530 | internalError (); | |
9531 | } | |
9532 | ||
9533 | lastregno = regno; | |
9534 | continue; | |
9535 | ||
9536 | case 'P': | |
9537 | if (strncmp (s, "$pc", 3) == 0) | |
9538 | { | |
9539 | s += 3; | |
9540 | continue; | |
9541 | } | |
9542 | break; | |
9543 | ||
9544 | case '<': | |
9545 | case '>': | |
9546 | case '[': | |
9547 | case ']': | |
9548 | case '4': | |
9549 | case '5': | |
9550 | case 'H': | |
9551 | case 'W': | |
9552 | case 'D': | |
9553 | case 'j': | |
9554 | case '8': | |
9555 | case 'V': | |
9556 | case 'C': | |
9557 | case 'U': | |
9558 | case 'k': | |
9559 | case 'K': | |
9560 | if (s[0] == '%' | |
9561 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
9562 | { | |
9563 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
9564 | and generate the appropriate reloc. If the text | |
9565 | inside %gprel is not a symbol name with an | |
9566 | optional offset, then we generate a normal reloc | |
9567 | and will probably fail later. */ | |
9568 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
9569 | if (imm_expr.X_op == O_symbol) | |
9570 | { | |
b34976b6 | 9571 | mips16_ext = TRUE; |
f6688943 | 9572 | *imm_reloc = BFD_RELOC_MIPS16_GPREL; |
252b5132 | 9573 | s = expr_end; |
b34976b6 | 9574 | ip->use_extend = TRUE; |
252b5132 RH |
9575 | ip->extend = 0; |
9576 | continue; | |
9577 | } | |
9578 | } | |
9579 | else | |
9580 | { | |
9581 | /* Just pick up a normal expression. */ | |
9582 | my_getExpression (&imm_expr, s); | |
9583 | } | |
9584 | ||
9585 | if (imm_expr.X_op == O_register) | |
9586 | { | |
9587 | /* What we thought was an expression turned out to | |
9588 | be a register. */ | |
9589 | ||
9590 | if (s[0] == '(' && args[1] == '(') | |
9591 | { | |
9592 | /* It looks like the expression was omitted | |
9593 | before a register indirection, which means | |
9594 | that the expression is implicitly zero. We | |
9595 | still set up imm_expr, so that we handle | |
9596 | explicit extensions correctly. */ | |
9597 | imm_expr.X_op = O_constant; | |
9598 | imm_expr.X_add_number = 0; | |
f6688943 | 9599 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9600 | continue; |
9601 | } | |
9602 | ||
9603 | break; | |
9604 | } | |
9605 | ||
9606 | /* We need to relax this instruction. */ | |
f6688943 | 9607 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9608 | s = expr_end; |
9609 | continue; | |
9610 | ||
9611 | case 'p': | |
9612 | case 'q': | |
9613 | case 'A': | |
9614 | case 'B': | |
9615 | case 'E': | |
9616 | /* We use offset_reloc rather than imm_reloc for the PC | |
9617 | relative operands. This lets macros with both | |
9618 | immediate and address operands work correctly. */ | |
9619 | my_getExpression (&offset_expr, s); | |
9620 | ||
9621 | if (offset_expr.X_op == O_register) | |
9622 | break; | |
9623 | ||
9624 | /* We need to relax this instruction. */ | |
f6688943 | 9625 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9626 | s = expr_end; |
9627 | continue; | |
9628 | ||
9629 | case '6': /* break code */ | |
9630 | my_getExpression (&imm_expr, s); | |
9631 | check_absolute_expr (ip, &imm_expr); | |
9632 | if ((unsigned long) imm_expr.X_add_number > 63) | |
9633 | { | |
9634 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9635 | ip->insn_mo->name, | |
9636 | (unsigned long) imm_expr.X_add_number); | |
9637 | imm_expr.X_add_number &= 0x3f; | |
9638 | } | |
9639 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
9640 | imm_expr.X_op = O_absent; | |
9641 | s = expr_end; | |
9642 | continue; | |
9643 | ||
9644 | case 'a': /* 26 bit address */ | |
9645 | my_getExpression (&offset_expr, s); | |
9646 | s = expr_end; | |
f6688943 | 9647 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9648 | ip->insn_opcode <<= 16; |
9649 | continue; | |
9650 | ||
9651 | case 'l': /* register list for entry macro */ | |
9652 | case 'L': /* register list for exit macro */ | |
9653 | { | |
9654 | int mask; | |
9655 | ||
9656 | if (c == 'l') | |
9657 | mask = 0; | |
9658 | else | |
9659 | mask = 7 << 3; | |
9660 | while (*s != '\0') | |
9661 | { | |
9662 | int freg, reg1, reg2; | |
9663 | ||
9664 | while (*s == ' ' || *s == ',') | |
9665 | ++s; | |
9666 | if (*s != '$') | |
9667 | { | |
9668 | as_bad (_("can't parse register list")); | |
9669 | break; | |
9670 | } | |
9671 | ++s; | |
9672 | if (*s != 'f') | |
9673 | freg = 0; | |
9674 | else | |
9675 | { | |
9676 | freg = 1; | |
9677 | ++s; | |
9678 | } | |
9679 | reg1 = 0; | |
3882b010 | 9680 | while (ISDIGIT (*s)) |
252b5132 RH |
9681 | { |
9682 | reg1 *= 10; | |
9683 | reg1 += *s - '0'; | |
9684 | ++s; | |
9685 | } | |
9686 | if (*s == ' ') | |
9687 | ++s; | |
9688 | if (*s != '-') | |
9689 | reg2 = reg1; | |
9690 | else | |
9691 | { | |
9692 | ++s; | |
9693 | if (*s != '$') | |
9694 | break; | |
9695 | ++s; | |
9696 | if (freg) | |
9697 | { | |
9698 | if (*s == 'f') | |
9699 | ++s; | |
9700 | else | |
9701 | { | |
9702 | as_bad (_("invalid register list")); | |
9703 | break; | |
9704 | } | |
9705 | } | |
9706 | reg2 = 0; | |
3882b010 | 9707 | while (ISDIGIT (*s)) |
252b5132 RH |
9708 | { |
9709 | reg2 *= 10; | |
9710 | reg2 += *s - '0'; | |
9711 | ++s; | |
9712 | } | |
9713 | } | |
9714 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9715 | { | |
9716 | mask &= ~ (7 << 3); | |
9717 | mask |= 5 << 3; | |
9718 | } | |
9719 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9720 | { | |
9721 | mask &= ~ (7 << 3); | |
9722 | mask |= 6 << 3; | |
9723 | } | |
9724 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9725 | mask |= (reg2 - 3) << 3; | |
9726 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9727 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9728 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9729 | mask |= 1; |
9730 | else | |
9731 | { | |
9732 | as_bad (_("invalid register list")); | |
9733 | break; | |
9734 | } | |
9735 | } | |
9736 | /* The mask is filled in in the opcode table for the | |
9737 | benefit of the disassembler. We remove it before | |
9738 | applying the actual mask. */ | |
9739 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9740 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9741 | } | |
9742 | continue; | |
9743 | ||
9744 | case 'e': /* extend code */ | |
9745 | my_getExpression (&imm_expr, s); | |
9746 | check_absolute_expr (ip, &imm_expr); | |
9747 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9748 | { | |
9749 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9750 | ip->insn_mo->name, | |
9751 | (unsigned long) imm_expr.X_add_number); | |
9752 | imm_expr.X_add_number &= 0x7ff; | |
9753 | } | |
9754 | ip->insn_opcode |= imm_expr.X_add_number; | |
9755 | imm_expr.X_op = O_absent; | |
9756 | s = expr_end; | |
9757 | continue; | |
9758 | ||
9759 | default: | |
9760 | internalError (); | |
9761 | } | |
9762 | break; | |
9763 | } | |
9764 | ||
9765 | /* Args don't match. */ | |
9766 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9767 | strcmp (insn->name, insn[1].name) == 0) | |
9768 | { | |
9769 | ++insn; | |
9770 | s = argsstart; | |
9771 | continue; | |
9772 | } | |
9773 | ||
9774 | insn_error = _("illegal operands"); | |
9775 | ||
9776 | return; | |
9777 | } | |
9778 | } | |
9779 | ||
9780 | /* This structure holds information we know about a mips16 immediate | |
9781 | argument type. */ | |
9782 | ||
e972090a NC |
9783 | struct mips16_immed_operand |
9784 | { | |
252b5132 RH |
9785 | /* The type code used in the argument string in the opcode table. */ |
9786 | int type; | |
9787 | /* The number of bits in the short form of the opcode. */ | |
9788 | int nbits; | |
9789 | /* The number of bits in the extended form of the opcode. */ | |
9790 | int extbits; | |
9791 | /* The amount by which the short form is shifted when it is used; | |
9792 | for example, the sw instruction has a shift count of 2. */ | |
9793 | int shift; | |
9794 | /* The amount by which the short form is shifted when it is stored | |
9795 | into the instruction code. */ | |
9796 | int op_shift; | |
9797 | /* Non-zero if the short form is unsigned. */ | |
9798 | int unsp; | |
9799 | /* Non-zero if the extended form is unsigned. */ | |
9800 | int extu; | |
9801 | /* Non-zero if the value is PC relative. */ | |
9802 | int pcrel; | |
9803 | }; | |
9804 | ||
9805 | /* The mips16 immediate operand types. */ | |
9806 | ||
9807 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9808 | { | |
9809 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9810 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9811 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9812 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9813 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9814 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9815 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9816 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9817 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9818 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9819 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9820 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9821 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9822 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9823 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9824 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9825 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9826 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9827 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9828 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9829 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9830 | }; | |
9831 | ||
9832 | #define MIPS16_NUM_IMMED \ | |
9833 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9834 | ||
9835 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9836 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9837 | whether an extended value is needed; if one is needed, it sets | |
9838 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9839 | If SMALL is true, an unextended opcode was explicitly requested. | |
9840 | If EXT is true, an extended opcode was explicitly requested. If | |
9841 | WARN is true, warn if EXT does not match reality. */ | |
9842 | ||
9843 | static void | |
9844 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, | |
9845 | extend) | |
9846 | char *file; | |
9847 | unsigned int line; | |
9848 | int type; | |
9849 | offsetT val; | |
b34976b6 AM |
9850 | bfd_boolean warn; |
9851 | bfd_boolean small; | |
9852 | bfd_boolean ext; | |
252b5132 | 9853 | unsigned long *insn; |
b34976b6 | 9854 | bfd_boolean *use_extend; |
252b5132 RH |
9855 | unsigned short *extend; |
9856 | { | |
9857 | register const struct mips16_immed_operand *op; | |
9858 | int mintiny, maxtiny; | |
b34976b6 | 9859 | bfd_boolean needext; |
252b5132 RH |
9860 | |
9861 | op = mips16_immed_operands; | |
9862 | while (op->type != type) | |
9863 | { | |
9864 | ++op; | |
9865 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9866 | } | |
9867 | ||
9868 | if (op->unsp) | |
9869 | { | |
9870 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9871 | { | |
9872 | mintiny = 1; | |
9873 | maxtiny = 1 << op->nbits; | |
9874 | } | |
9875 | else | |
9876 | { | |
9877 | mintiny = 0; | |
9878 | maxtiny = (1 << op->nbits) - 1; | |
9879 | } | |
9880 | } | |
9881 | else | |
9882 | { | |
9883 | mintiny = - (1 << (op->nbits - 1)); | |
9884 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9885 | } | |
9886 | ||
9887 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9888 | if (type == 'p' || type == 'q') | |
9889 | val /= 2; | |
9890 | ||
9891 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9892 | || val < (mintiny << op->shift) | |
9893 | || val > (maxtiny << op->shift)) | |
b34976b6 | 9894 | needext = TRUE; |
252b5132 | 9895 | else |
b34976b6 | 9896 | needext = FALSE; |
252b5132 RH |
9897 | |
9898 | if (warn && ext && ! needext) | |
beae10d5 KH |
9899 | as_warn_where (file, line, |
9900 | _("extended operand requested but not required")); | |
252b5132 RH |
9901 | if (small && needext) |
9902 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9903 | ||
9904 | if (small || (! ext && ! needext)) | |
9905 | { | |
9906 | int insnval; | |
9907 | ||
b34976b6 | 9908 | *use_extend = FALSE; |
252b5132 RH |
9909 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
9910 | insnval <<= op->op_shift; | |
9911 | *insn |= insnval; | |
9912 | } | |
9913 | else | |
9914 | { | |
9915 | long minext, maxext; | |
9916 | int extval; | |
9917 | ||
9918 | if (op->extu) | |
9919 | { | |
9920 | minext = 0; | |
9921 | maxext = (1 << op->extbits) - 1; | |
9922 | } | |
9923 | else | |
9924 | { | |
9925 | minext = - (1 << (op->extbits - 1)); | |
9926 | maxext = (1 << (op->extbits - 1)) - 1; | |
9927 | } | |
9928 | if (val < minext || val > maxext) | |
9929 | as_bad_where (file, line, | |
9930 | _("operand value out of range for instruction")); | |
9931 | ||
b34976b6 | 9932 | *use_extend = TRUE; |
252b5132 RH |
9933 | if (op->extbits == 16) |
9934 | { | |
9935 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9936 | val &= 0x1f; | |
9937 | } | |
9938 | else if (op->extbits == 15) | |
9939 | { | |
9940 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9941 | val &= 0xf; | |
9942 | } | |
9943 | else | |
9944 | { | |
9945 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9946 | val = 0; | |
9947 | } | |
9948 | ||
9949 | *extend = (unsigned short) extval; | |
9950 | *insn |= val; | |
9951 | } | |
9952 | } | |
9953 | \f | |
ad8d3bb3 TS |
9954 | static struct percent_op_match |
9955 | { | |
9956 | const char *str; | |
9957 | const enum small_ex_type type; | |
9958 | } percent_op[] = | |
9959 | { | |
ad8d3bb3 TS |
9960 | {"%lo", S_EX_LO}, |
9961 | #ifdef OBJ_ELF | |
394f9b3a TS |
9962 | {"%call_hi", S_EX_CALL_HI}, |
9963 | {"%call_lo", S_EX_CALL_LO}, | |
ad8d3bb3 TS |
9964 | {"%call16", S_EX_CALL16}, |
9965 | {"%got_disp", S_EX_GOT_DISP}, | |
9966 | {"%got_page", S_EX_GOT_PAGE}, | |
9967 | {"%got_ofst", S_EX_GOT_OFST}, | |
9968 | {"%got_hi", S_EX_GOT_HI}, | |
9969 | {"%got_lo", S_EX_GOT_LO}, | |
394f9b3a TS |
9970 | {"%got", S_EX_GOT}, |
9971 | {"%gp_rel", S_EX_GP_REL}, | |
9972 | {"%half", S_EX_HALF}, | |
ad8d3bb3 | 9973 | {"%highest", S_EX_HIGHEST}, |
394f9b3a TS |
9974 | {"%higher", S_EX_HIGHER}, |
9975 | {"%neg", S_EX_NEG}, | |
ad8d3bb3 | 9976 | #endif |
394f9b3a | 9977 | {"%hi", S_EX_HI} |
ad8d3bb3 TS |
9978 | }; |
9979 | ||
9980 | /* Parse small expression input. STR gets adjusted to eat up whitespace. | |
9981 | It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's | |
9982 | can be nested, this is handled by blanking the innermost, parsing the | |
9983 | rest by subsequent calls. */ | |
252b5132 RH |
9984 | |
9985 | static int | |
ad8d3bb3 TS |
9986 | my_getSmallParser (str, len, nestlevel) |
9987 | char **str; | |
9988 | unsigned int *len; | |
9989 | int *nestlevel; | |
252b5132 | 9990 | { |
ad8d3bb3 TS |
9991 | *len = 0; |
9992 | *str += strspn (*str, " \t"); | |
394f9b3a | 9993 | /* Check for expression in parentheses. */ |
ad8d3bb3 | 9994 | if (**str == '(') |
252b5132 | 9995 | { |
ad8d3bb3 TS |
9996 | char *b = *str + 1 + strspn (*str + 1, " \t"); |
9997 | char *e; | |
9998 | ||
9999 | /* Check for base register. */ | |
10000 | if (b[0] == '$') | |
10001 | { | |
10002 | if (strchr (b, ')') | |
10003 | && (e = b + strcspn (b, ") \t")) | |
10004 | && e - b > 1 && e - b < 4) | |
10005 | { | |
98d3f06f KH |
10006 | if ((e - b == 3 |
10007 | && ((b[1] == 'f' && b[2] == 'p') | |
10008 | || (b[1] == 's' && b[2] == 'p') | |
10009 | || (b[1] == 'g' && b[2] == 'p') | |
10010 | || (b[1] == 'a' && b[2] == 't') | |
10011 | || (ISDIGIT (b[1]) | |
10012 | && ISDIGIT (b[2])))) | |
10013 | || (ISDIGIT (b[1]))) | |
10014 | { | |
10015 | *len = strcspn (*str, ")") + 1; | |
10016 | return S_EX_REGISTER; | |
10017 | } | |
ad8d3bb3 TS |
10018 | } |
10019 | } | |
394f9b3a | 10020 | /* Check for percent_op (in parentheses). */ |
ad8d3bb3 TS |
10021 | else if (b[0] == '%') |
10022 | { | |
10023 | *str = b; | |
394f9b3a | 10024 | return my_getPercentOp (str, len, nestlevel); |
ad8d3bb3 | 10025 | } |
76b3015f | 10026 | |
394f9b3a TS |
10027 | /* Some other expression in the parentheses, which can contain |
10028 | parentheses itself. Attempt to find the matching one. */ | |
10029 | { | |
10030 | int pcnt = 1; | |
10031 | char *s; | |
10032 | ||
10033 | *len = 1; | |
10034 | for (s = *str + 1; *s && pcnt; s++, (*len)++) | |
10035 | { | |
10036 | if (*s == '(') | |
f9419b05 | 10037 | ++pcnt; |
394f9b3a | 10038 | else if (*s == ')') |
f9419b05 | 10039 | --pcnt; |
394f9b3a TS |
10040 | } |
10041 | } | |
fb1b3232 | 10042 | } |
394f9b3a | 10043 | /* Check for percent_op (outside of parentheses). */ |
ad8d3bb3 | 10044 | else if (*str[0] == '%') |
394f9b3a TS |
10045 | return my_getPercentOp (str, len, nestlevel); |
10046 | ||
10047 | /* Any other expression. */ | |
10048 | return S_EX_NONE; | |
10049 | } | |
ad8d3bb3 | 10050 | |
394f9b3a TS |
10051 | static int |
10052 | my_getPercentOp (str, len, nestlevel) | |
10053 | char **str; | |
10054 | unsigned int *len; | |
10055 | int *nestlevel; | |
10056 | { | |
10057 | char *tmp = *str + 1; | |
10058 | unsigned int i = 0; | |
ad8d3bb3 | 10059 | |
394f9b3a TS |
10060 | while (ISALPHA (*tmp) || *tmp == '_') |
10061 | { | |
10062 | *tmp = TOLOWER (*tmp); | |
10063 | tmp++; | |
10064 | } | |
10065 | while (i < (sizeof (percent_op) / sizeof (struct percent_op_match))) | |
10066 | { | |
10067 | if (strncmp (*str, percent_op[i].str, strlen (percent_op[i].str))) | |
98d3f06f | 10068 | i++; |
394f9b3a | 10069 | else |
ad8d3bb3 | 10070 | { |
394f9b3a | 10071 | int type = percent_op[i].type; |
ad8d3bb3 | 10072 | |
394f9b3a TS |
10073 | /* Only %hi and %lo are allowed for OldABI. */ |
10074 | if (! HAVE_NEWABI && type != S_EX_HI && type != S_EX_LO) | |
10075 | return S_EX_NONE; | |
ad8d3bb3 | 10076 | |
394f9b3a | 10077 | *len = strlen (percent_op[i].str); |
f9419b05 | 10078 | ++(*nestlevel); |
394f9b3a | 10079 | return type; |
ad8d3bb3 | 10080 | } |
fb1b3232 | 10081 | } |
ad8d3bb3 TS |
10082 | return S_EX_NONE; |
10083 | } | |
10084 | ||
10085 | static int | |
10086 | my_getSmallExpression (ep, str) | |
10087 | expressionS *ep; | |
10088 | char *str; | |
10089 | { | |
10090 | static char *oldstr = NULL; | |
10091 | int c = S_EX_NONE; | |
10092 | int oldc; | |
394f9b3a | 10093 | int nestlevel = -1; |
ad8d3bb3 TS |
10094 | unsigned int len; |
10095 | ||
394f9b3a TS |
10096 | /* Don't update oldstr if the last call had nested percent_op's. We need |
10097 | it to parse the outer ones later. */ | |
ad8d3bb3 TS |
10098 | if (! oldstr) |
10099 | oldstr = str; | |
76b3015f | 10100 | |
ad8d3bb3 | 10101 | do |
fb1b3232 | 10102 | { |
ad8d3bb3 | 10103 | oldc = c; |
394f9b3a | 10104 | c = my_getSmallParser (&str, &len, &nestlevel); |
ad8d3bb3 TS |
10105 | if (c != S_EX_NONE && c != S_EX_REGISTER) |
10106 | str += len; | |
fb1b3232 | 10107 | } |
ad8d3bb3 TS |
10108 | while (c != S_EX_NONE && c != S_EX_REGISTER); |
10109 | ||
394f9b3a | 10110 | if (nestlevel >= 0) |
fb1b3232 | 10111 | { |
394f9b3a TS |
10112 | /* A percent_op was encountered. Don't try to get an expression if |
10113 | it is already blanked out. */ | |
ad8d3bb3 TS |
10114 | if (*(str + strspn (str + 1, " )")) != ')') |
10115 | { | |
10116 | char save; | |
10117 | ||
394f9b3a | 10118 | /* Let my_getExpression() stop at the closing parenthesis. */ |
ad8d3bb3 TS |
10119 | save = *(str + len); |
10120 | *(str + len) = '\0'; | |
10121 | my_getExpression (ep, str); | |
10122 | *(str + len) = save; | |
10123 | } | |
394f9b3a | 10124 | if (nestlevel > 0) |
ad8d3bb3 | 10125 | { |
394f9b3a TS |
10126 | /* Blank out including the % sign and the proper matching |
10127 | parenthesis. */ | |
10128 | int pcnt = 1; | |
10129 | char *s = strrchr (oldstr, '%'); | |
10130 | char *end; | |
10131 | ||
10132 | for (end = strchr (s, '(') + 1; *end && pcnt; end++) | |
10133 | { | |
10134 | if (*end == '(') | |
f9419b05 | 10135 | ++pcnt; |
394f9b3a | 10136 | else if (*end == ')') |
f9419b05 | 10137 | --pcnt; |
394f9b3a TS |
10138 | } |
10139 | ||
10140 | memset (s, ' ', end - s); | |
ad8d3bb3 TS |
10141 | str = oldstr; |
10142 | } | |
10143 | else | |
394f9b3a TS |
10144 | expr_end = str + len; |
10145 | ||
ad8d3bb3 | 10146 | c = oldc; |
fb1b3232 | 10147 | } |
ad8d3bb3 | 10148 | else if (c == S_EX_NONE) |
fb1b3232 | 10149 | { |
ad8d3bb3 | 10150 | my_getExpression (ep, str); |
fb1b3232 | 10151 | } |
ad8d3bb3 | 10152 | else if (c == S_EX_REGISTER) |
fb1b3232 | 10153 | { |
ad8d3bb3 TS |
10154 | ep->X_op = O_constant; |
10155 | expr_end = str; | |
10156 | ep->X_add_symbol = NULL; | |
10157 | ep->X_op_symbol = NULL; | |
10158 | ep->X_add_number = 0; | |
fb1b3232 | 10159 | } |
fb1b3232 TS |
10160 | else |
10161 | { | |
98d3f06f | 10162 | as_fatal (_("internal error")); |
fb1b3232 | 10163 | } |
252b5132 | 10164 | |
394f9b3a TS |
10165 | if (nestlevel <= 0) |
10166 | /* All percent_op's have been handled. */ | |
ad8d3bb3 | 10167 | oldstr = NULL; |
fb1b3232 | 10168 | |
fb1b3232 | 10169 | return c; |
252b5132 RH |
10170 | } |
10171 | ||
10172 | static void | |
10173 | my_getExpression (ep, str) | |
10174 | expressionS *ep; | |
10175 | char *str; | |
10176 | { | |
10177 | char *save_in; | |
98aa84af | 10178 | valueT val; |
252b5132 RH |
10179 | |
10180 | save_in = input_line_pointer; | |
10181 | input_line_pointer = str; | |
10182 | expression (ep); | |
10183 | expr_end = input_line_pointer; | |
10184 | input_line_pointer = save_in; | |
10185 | ||
10186 | /* If we are in mips16 mode, and this is an expression based on `.', | |
10187 | then we bump the value of the symbol by 1 since that is how other | |
10188 | text symbols are handled. We don't bother to handle complex | |
10189 | expressions, just `.' plus or minus a constant. */ | |
10190 | if (mips_opts.mips16 | |
10191 | && ep->X_op == O_symbol | |
10192 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10193 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10194 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10195 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10196 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10197 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10198 | } |
10199 | ||
10200 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10201 | of type TYPE, and store the appropriate bytes in *LITP. The number |
10202 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
10203 | returned, or NULL on OK. */ |
10204 | ||
10205 | char * | |
10206 | md_atof (type, litP, sizeP) | |
10207 | int type; | |
10208 | char *litP; | |
10209 | int *sizeP; | |
10210 | { | |
10211 | int prec; | |
10212 | LITTLENUM_TYPE words[4]; | |
10213 | char *t; | |
10214 | int i; | |
10215 | ||
10216 | switch (type) | |
10217 | { | |
10218 | case 'f': | |
10219 | prec = 2; | |
10220 | break; | |
10221 | ||
10222 | case 'd': | |
10223 | prec = 4; | |
10224 | break; | |
10225 | ||
10226 | default: | |
10227 | *sizeP = 0; | |
10228 | return _("bad call to md_atof"); | |
10229 | } | |
10230 | ||
10231 | t = atof_ieee (input_line_pointer, type, words); | |
10232 | if (t) | |
10233 | input_line_pointer = t; | |
10234 | ||
10235 | *sizeP = prec * 2; | |
10236 | ||
10237 | if (! target_big_endian) | |
10238 | { | |
10239 | for (i = prec - 1; i >= 0; i--) | |
10240 | { | |
10241 | md_number_to_chars (litP, (valueT) words[i], 2); | |
10242 | litP += 2; | |
10243 | } | |
10244 | } | |
10245 | else | |
10246 | { | |
10247 | for (i = 0; i < prec; i++) | |
10248 | { | |
10249 | md_number_to_chars (litP, (valueT) words[i], 2); | |
10250 | litP += 2; | |
10251 | } | |
10252 | } | |
bdaaa2e1 | 10253 | |
252b5132 RH |
10254 | return NULL; |
10255 | } | |
10256 | ||
10257 | void | |
10258 | md_number_to_chars (buf, val, n) | |
10259 | char *buf; | |
10260 | valueT val; | |
10261 | int n; | |
10262 | { | |
10263 | if (target_big_endian) | |
10264 | number_to_chars_bigendian (buf, val, n); | |
10265 | else | |
10266 | number_to_chars_littleendian (buf, val, n); | |
10267 | } | |
10268 | \f | |
ae948b86 | 10269 | #ifdef OBJ_ELF |
e013f690 TS |
10270 | static int support_64bit_objects(void) |
10271 | { | |
10272 | const char **list, **l; | |
aa3d8fdf | 10273 | int yes; |
e013f690 TS |
10274 | |
10275 | list = bfd_target_list (); | |
10276 | for (l = list; *l != NULL; l++) | |
10277 | #ifdef TE_TMIPS | |
10278 | /* This is traditional mips */ | |
10279 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10280 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10281 | #else | |
10282 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10283 | || strcmp (*l, "elf64-littlemips") == 0) | |
10284 | #endif | |
10285 | break; | |
aa3d8fdf | 10286 | yes = (*l != NULL); |
e013f690 | 10287 | free (list); |
aa3d8fdf | 10288 | return yes; |
e013f690 | 10289 | } |
ae948b86 | 10290 | #endif /* OBJ_ELF */ |
e013f690 | 10291 | |
5a38dc70 | 10292 | const char *md_shortopts = "nO::g::G:"; |
252b5132 | 10293 | |
e972090a NC |
10294 | struct option md_longopts[] = |
10295 | { | |
252b5132 RH |
10296 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) |
10297 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
10298 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
10299 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
10300 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
10301 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
10302 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
10303 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) | |
10304 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
ae948b86 TS |
10305 | #define OPTION_MIPS5 (OPTION_MD_BASE + 5) |
10306 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
10307 | #define OPTION_MIPS32 (OPTION_MD_BASE + 6) | |
10308 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
10309 | #define OPTION_MIPS64 (OPTION_MD_BASE + 7) | |
10310 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
10311 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8) | |
252b5132 | 10312 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
ae948b86 | 10313 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
252b5132 RH |
10314 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10315 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
ae948b86 | 10316 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
252b5132 RH |
10317 | {"break", no_argument, NULL, OPTION_BREAK}, |
10318 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
ae948b86 | 10319 | #define OPTION_EB (OPTION_MD_BASE + 11) |
252b5132 | 10320 | {"EB", no_argument, NULL, OPTION_EB}, |
ae948b86 | 10321 | #define OPTION_EL (OPTION_MD_BASE + 12) |
252b5132 | 10322 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 10323 | #define OPTION_MIPS16 (OPTION_MD_BASE + 13) |
252b5132 | 10324 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
ae948b86 | 10325 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14) |
252b5132 | 10326 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
ae948b86 | 10327 | #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15) |
6b76fefe | 10328 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
9ee72ff1 TS |
10329 | #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16) |
10330 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10331 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
ae948b86 TS |
10332 | #define OPTION_FP32 (OPTION_MD_BASE + 17) |
10333 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
10334 | #define OPTION_GP32 (OPTION_MD_BASE + 18) | |
c97ef257 | 10335 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
ae948b86 | 10336 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19) |
119d663a | 10337 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
ae948b86 | 10338 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20) |
119d663a | 10339 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
ae948b86 | 10340 | #define OPTION_MARCH (OPTION_MD_BASE + 21) |
ec68c924 | 10341 | {"march", required_argument, NULL, OPTION_MARCH}, |
ae948b86 | 10342 | #define OPTION_MTUNE (OPTION_MD_BASE + 22) |
ec68c924 | 10343 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
316f5878 RS |
10344 | #define OPTION_FP64 (OPTION_MD_BASE + 23) |
10345 | {"mfp64", no_argument, NULL, OPTION_FP64}, | |
ae948b86 TS |
10346 | #define OPTION_M4650 (OPTION_MD_BASE + 24) |
10347 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10348 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 25) | |
10349 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10350 | #define OPTION_M4010 (OPTION_MD_BASE + 26) | |
10351 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10352 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 27) | |
10353 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10354 | #define OPTION_M4100 (OPTION_MD_BASE + 28) | |
10355 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10356 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 29) | |
10357 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10358 | #define OPTION_M3900 (OPTION_MD_BASE + 30) | |
10359 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10360 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 31) | |
10361 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10362 | #define OPTION_GP64 (OPTION_MD_BASE + 32) | |
10363 | {"mgp64", no_argument, NULL, OPTION_GP64}, | |
1f25f5d3 CD |
10364 | #define OPTION_MIPS3D (OPTION_MD_BASE + 33) |
10365 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10366 | #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34) | |
10367 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
deec1734 CD |
10368 | #define OPTION_MDMX (OPTION_MD_BASE + 35) |
10369 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10370 | #define OPTION_NO_MDMX (OPTION_MD_BASE + 36) | |
10371 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
60b63b72 RS |
10372 | #define OPTION_FIX_VR4122 (OPTION_MD_BASE + 37) |
10373 | #define OPTION_NO_FIX_VR4122 (OPTION_MD_BASE + 38) | |
10374 | {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122}, | |
10375 | {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122}, | |
4a6a3df4 AO |
10376 | #define OPTION_RELAX_BRANCH (OPTION_MD_BASE + 39) |
10377 | #define OPTION_NO_RELAX_BRANCH (OPTION_MD_BASE + 40) | |
10378 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, | |
10379 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
156c2f8b | 10380 | #ifdef OBJ_ELF |
4a6a3df4 | 10381 | #define OPTION_ELF_BASE (OPTION_MD_BASE + 41) |
156c2f8b | 10382 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10383 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10384 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10385 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10386 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10387 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10388 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10389 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10390 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10391 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10392 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10393 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10394 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10395 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10396 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10397 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10398 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10399 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10400 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
ae948b86 | 10401 | #endif /* OBJ_ELF */ |
252b5132 RH |
10402 | {NULL, no_argument, NULL, 0} |
10403 | }; | |
156c2f8b | 10404 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10405 | |
316f5878 RS |
10406 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10407 | NEW_VALUE. Warn if another value was already specified. Note: | |
10408 | we have to defer parsing the -march and -mtune arguments in order | |
10409 | to handle 'from-abi' correctly, since the ABI might be specified | |
10410 | in a later argument. */ | |
10411 | ||
10412 | static void | |
10413 | mips_set_option_string (string_ptr, new_value) | |
10414 | const char **string_ptr, *new_value; | |
10415 | { | |
10416 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10417 | as_warn (_("A different %s was already specified, is now %s"), | |
10418 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10419 | new_value); | |
10420 | ||
10421 | *string_ptr = new_value; | |
10422 | } | |
10423 | ||
252b5132 RH |
10424 | int |
10425 | md_parse_option (c, arg) | |
10426 | int c; | |
10427 | char *arg; | |
10428 | { | |
10429 | switch (c) | |
10430 | { | |
119d663a NC |
10431 | case OPTION_CONSTRUCT_FLOATS: |
10432 | mips_disable_float_construction = 0; | |
10433 | break; | |
bdaaa2e1 | 10434 | |
119d663a NC |
10435 | case OPTION_NO_CONSTRUCT_FLOATS: |
10436 | mips_disable_float_construction = 1; | |
10437 | break; | |
bdaaa2e1 | 10438 | |
252b5132 RH |
10439 | case OPTION_TRAP: |
10440 | mips_trap = 1; | |
10441 | break; | |
10442 | ||
10443 | case OPTION_BREAK: | |
10444 | mips_trap = 0; | |
10445 | break; | |
10446 | ||
10447 | case OPTION_EB: | |
10448 | target_big_endian = 1; | |
10449 | break; | |
10450 | ||
10451 | case OPTION_EL: | |
10452 | target_big_endian = 0; | |
10453 | break; | |
10454 | ||
39c0a331 L |
10455 | case 'n': |
10456 | warn_nops = 1; | |
10457 | break; | |
10458 | ||
252b5132 RH |
10459 | case 'O': |
10460 | if (arg && arg[1] == '0') | |
10461 | mips_optimize = 1; | |
10462 | else | |
10463 | mips_optimize = 2; | |
10464 | break; | |
10465 | ||
10466 | case 'g': | |
10467 | if (arg == NULL) | |
10468 | mips_debug = 2; | |
10469 | else | |
10470 | mips_debug = atoi (arg); | |
10471 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10472 | optimizations which limit full symbolic debugging. We take | |
10473 | that to be equivalent to -O0. */ | |
10474 | if (mips_debug == 2) | |
10475 | mips_optimize = 1; | |
10476 | break; | |
10477 | ||
10478 | case OPTION_MIPS1: | |
316f5878 | 10479 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10480 | break; |
10481 | ||
10482 | case OPTION_MIPS2: | |
316f5878 | 10483 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10484 | break; |
10485 | ||
10486 | case OPTION_MIPS3: | |
316f5878 | 10487 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10488 | break; |
10489 | ||
10490 | case OPTION_MIPS4: | |
316f5878 | 10491 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10492 | break; |
10493 | ||
84ea6cf2 | 10494 | case OPTION_MIPS5: |
316f5878 | 10495 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10496 | break; |
10497 | ||
e7af610e | 10498 | case OPTION_MIPS32: |
316f5878 | 10499 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10500 | break; |
10501 | ||
84ea6cf2 | 10502 | case OPTION_MIPS64: |
316f5878 | 10503 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10504 | break; |
10505 | ||
ec68c924 | 10506 | case OPTION_MTUNE: |
316f5878 RS |
10507 | mips_set_option_string (&mips_tune_string, arg); |
10508 | break; | |
ec68c924 | 10509 | |
316f5878 RS |
10510 | case OPTION_MARCH: |
10511 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10512 | break; |
10513 | ||
10514 | case OPTION_M4650: | |
316f5878 RS |
10515 | mips_set_option_string (&mips_arch_string, "4650"); |
10516 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10517 | break; |
10518 | ||
10519 | case OPTION_NO_M4650: | |
10520 | break; | |
10521 | ||
10522 | case OPTION_M4010: | |
316f5878 RS |
10523 | mips_set_option_string (&mips_arch_string, "4010"); |
10524 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10525 | break; |
10526 | ||
10527 | case OPTION_NO_M4010: | |
10528 | break; | |
10529 | ||
10530 | case OPTION_M4100: | |
316f5878 RS |
10531 | mips_set_option_string (&mips_arch_string, "4100"); |
10532 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10533 | break; |
10534 | ||
10535 | case OPTION_NO_M4100: | |
10536 | break; | |
10537 | ||
252b5132 | 10538 | case OPTION_M3900: |
316f5878 RS |
10539 | mips_set_option_string (&mips_arch_string, "3900"); |
10540 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10541 | break; |
bdaaa2e1 | 10542 | |
252b5132 RH |
10543 | case OPTION_NO_M3900: |
10544 | break; | |
10545 | ||
deec1734 CD |
10546 | case OPTION_MDMX: |
10547 | mips_opts.ase_mdmx = 1; | |
10548 | break; | |
10549 | ||
10550 | case OPTION_NO_MDMX: | |
10551 | mips_opts.ase_mdmx = 0; | |
10552 | break; | |
10553 | ||
252b5132 RH |
10554 | case OPTION_MIPS16: |
10555 | mips_opts.mips16 = 1; | |
b34976b6 | 10556 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10557 | break; |
10558 | ||
10559 | case OPTION_NO_MIPS16: | |
10560 | mips_opts.mips16 = 0; | |
b34976b6 | 10561 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10562 | break; |
10563 | ||
1f25f5d3 CD |
10564 | case OPTION_MIPS3D: |
10565 | mips_opts.ase_mips3d = 1; | |
10566 | break; | |
10567 | ||
10568 | case OPTION_NO_MIPS3D: | |
10569 | mips_opts.ase_mips3d = 0; | |
10570 | break; | |
10571 | ||
252b5132 RH |
10572 | case OPTION_MEMBEDDED_PIC: |
10573 | mips_pic = EMBEDDED_PIC; | |
10574 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) | |
10575 | { | |
10576 | as_bad (_("-G may not be used with embedded PIC code")); | |
10577 | return 0; | |
10578 | } | |
10579 | g_switch_value = 0x7fffffff; | |
10580 | break; | |
10581 | ||
60b63b72 RS |
10582 | case OPTION_FIX_VR4122: |
10583 | mips_fix_4122_bugs = 1; | |
10584 | break; | |
10585 | ||
10586 | case OPTION_NO_FIX_VR4122: | |
10587 | mips_fix_4122_bugs = 0; | |
10588 | break; | |
10589 | ||
4a6a3df4 AO |
10590 | case OPTION_RELAX_BRANCH: |
10591 | mips_relax_branch = 1; | |
10592 | break; | |
10593 | ||
10594 | case OPTION_NO_RELAX_BRANCH: | |
10595 | mips_relax_branch = 0; | |
10596 | break; | |
10597 | ||
0f074f60 | 10598 | #ifdef OBJ_ELF |
252b5132 RH |
10599 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10600 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10601 | intended to be compatible with Irix 5. */ | |
10602 | case OPTION_CALL_SHARED: | |
10603 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10604 | { | |
10605 | as_bad (_("-call_shared is supported only for ELF format")); | |
10606 | return 0; | |
10607 | } | |
10608 | mips_pic = SVR4_PIC; | |
10609 | if (g_switch_seen && g_switch_value != 0) | |
10610 | { | |
10611 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10612 | return 0; | |
10613 | } | |
10614 | g_switch_value = 0; | |
10615 | break; | |
10616 | ||
10617 | case OPTION_NON_SHARED: | |
10618 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10619 | { | |
10620 | as_bad (_("-non_shared is supported only for ELF format")); | |
10621 | return 0; | |
10622 | } | |
10623 | mips_pic = NO_PIC; | |
10624 | break; | |
10625 | ||
10626 | /* The -xgot option tells the assembler to use 32 offsets when | |
10627 | accessing the got in SVR4_PIC mode. It is for Irix | |
10628 | compatibility. */ | |
10629 | case OPTION_XGOT: | |
10630 | mips_big_got = 1; | |
10631 | break; | |
0f074f60 | 10632 | #endif /* OBJ_ELF */ |
252b5132 RH |
10633 | |
10634 | case 'G': | |
10635 | if (! USE_GLOBAL_POINTER_OPT) | |
10636 | { | |
10637 | as_bad (_("-G is not supported for this configuration")); | |
10638 | return 0; | |
10639 | } | |
10640 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
10641 | { | |
10642 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); | |
10643 | return 0; | |
10644 | } | |
10645 | else | |
10646 | g_switch_value = atoi (arg); | |
10647 | g_switch_seen = 1; | |
10648 | break; | |
10649 | ||
0f074f60 | 10650 | #ifdef OBJ_ELF |
34ba82a8 TS |
10651 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10652 | and -mabi=64. */ | |
252b5132 | 10653 | case OPTION_32: |
34ba82a8 TS |
10654 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10655 | { | |
10656 | as_bad (_("-32 is supported for ELF format only")); | |
10657 | return 0; | |
10658 | } | |
316f5878 | 10659 | mips_abi = O32_ABI; |
252b5132 RH |
10660 | break; |
10661 | ||
e013f690 | 10662 | case OPTION_N32: |
34ba82a8 TS |
10663 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10664 | { | |
10665 | as_bad (_("-n32 is supported for ELF format only")); | |
10666 | return 0; | |
10667 | } | |
316f5878 | 10668 | mips_abi = N32_ABI; |
e013f690 | 10669 | break; |
252b5132 | 10670 | |
e013f690 | 10671 | case OPTION_64: |
34ba82a8 TS |
10672 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10673 | { | |
10674 | as_bad (_("-64 is supported for ELF format only")); | |
10675 | return 0; | |
10676 | } | |
316f5878 | 10677 | mips_abi = N64_ABI; |
e013f690 TS |
10678 | if (! support_64bit_objects()) |
10679 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10680 | break; |
ae948b86 | 10681 | #endif /* OBJ_ELF */ |
252b5132 | 10682 | |
c97ef257 | 10683 | case OPTION_GP32: |
a325df1d | 10684 | file_mips_gp32 = 1; |
c97ef257 AH |
10685 | break; |
10686 | ||
10687 | case OPTION_GP64: | |
a325df1d | 10688 | file_mips_gp32 = 0; |
c97ef257 | 10689 | break; |
252b5132 | 10690 | |
ca4e0257 | 10691 | case OPTION_FP32: |
a325df1d | 10692 | file_mips_fp32 = 1; |
316f5878 RS |
10693 | break; |
10694 | ||
10695 | case OPTION_FP64: | |
10696 | file_mips_fp32 = 0; | |
ca4e0257 RS |
10697 | break; |
10698 | ||
ae948b86 | 10699 | #ifdef OBJ_ELF |
252b5132 | 10700 | case OPTION_MABI: |
34ba82a8 TS |
10701 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10702 | { | |
10703 | as_bad (_("-mabi is supported for ELF format only")); | |
10704 | return 0; | |
10705 | } | |
e013f690 | 10706 | if (strcmp (arg, "32") == 0) |
316f5878 | 10707 | mips_abi = O32_ABI; |
e013f690 | 10708 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 10709 | mips_abi = O64_ABI; |
e013f690 | 10710 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 10711 | mips_abi = N32_ABI; |
e013f690 TS |
10712 | else if (strcmp (arg, "64") == 0) |
10713 | { | |
316f5878 | 10714 | mips_abi = N64_ABI; |
e013f690 TS |
10715 | if (! support_64bit_objects()) |
10716 | as_fatal (_("No compiled in support for 64 bit object file " | |
10717 | "format")); | |
10718 | } | |
10719 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 10720 | mips_abi = EABI_ABI; |
e013f690 | 10721 | else |
da0e507f TS |
10722 | { |
10723 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10724 | return 0; | |
10725 | } | |
252b5132 | 10726 | break; |
e013f690 | 10727 | #endif /* OBJ_ELF */ |
252b5132 | 10728 | |
6b76fefe | 10729 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 10730 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
10731 | break; |
10732 | ||
9ee72ff1 | 10733 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 10734 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
10735 | break; |
10736 | ||
ecb4347a DJ |
10737 | #ifdef OBJ_ELF |
10738 | case OPTION_MDEBUG: | |
b34976b6 | 10739 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
10740 | break; |
10741 | ||
10742 | case OPTION_NO_MDEBUG: | |
b34976b6 | 10743 | mips_flag_mdebug = FALSE; |
ecb4347a DJ |
10744 | break; |
10745 | #endif /* OBJ_ELF */ | |
10746 | ||
252b5132 RH |
10747 | default: |
10748 | return 0; | |
10749 | } | |
10750 | ||
10751 | return 1; | |
10752 | } | |
316f5878 RS |
10753 | \f |
10754 | /* Set up globals to generate code for the ISA or processor | |
10755 | described by INFO. */ | |
252b5132 | 10756 | |
252b5132 | 10757 | static void |
316f5878 RS |
10758 | mips_set_architecture (info) |
10759 | const struct mips_cpu_info *info; | |
252b5132 | 10760 | { |
316f5878 | 10761 | if (info != 0) |
252b5132 | 10762 | { |
316f5878 RS |
10763 | mips_arch_info = info; |
10764 | mips_arch = info->cpu; | |
10765 | mips_opts.isa = info->isa; | |
252b5132 | 10766 | } |
252b5132 RH |
10767 | } |
10768 | ||
252b5132 | 10769 | |
316f5878 | 10770 | /* Likewise for tuning. */ |
252b5132 | 10771 | |
316f5878 RS |
10772 | static void |
10773 | mips_set_tune (info) | |
10774 | const struct mips_cpu_info *info; | |
10775 | { | |
10776 | if (info != 0) | |
10777 | { | |
10778 | mips_tune_info = info; | |
10779 | mips_tune = info->cpu; | |
10780 | } | |
10781 | } | |
80cc45a5 | 10782 | |
34ba82a8 | 10783 | |
252b5132 | 10784 | void |
e9670677 MR |
10785 | mips_after_parse_args () |
10786 | { | |
e9670677 MR |
10787 | /* GP relative stuff not working for PE */ |
10788 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
10789 | && g_switch_value != 0) | |
10790 | { | |
10791 | if (g_switch_seen) | |
10792 | as_bad (_("-G not supported in this configuration.")); | |
10793 | g_switch_value = 0; | |
10794 | } | |
10795 | ||
22923709 RS |
10796 | /* The following code determines the architecture and register size. |
10797 | Similar code was added to GCC 3.3 (see override_options() in | |
10798 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
10799 | as much as possible. */ | |
e9670677 | 10800 | |
316f5878 RS |
10801 | if (mips_arch_string != 0) |
10802 | mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string)); | |
e9670677 | 10803 | |
316f5878 RS |
10804 | if (mips_tune_string != 0) |
10805 | mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string)); | |
e9670677 | 10806 | |
316f5878 | 10807 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 10808 | { |
316f5878 RS |
10809 | /* Handle -mipsN. At this point, file_mips_isa contains the |
10810 | ISA level specified by -mipsN, while mips_opts.isa contains | |
10811 | the -march selection (if any). */ | |
10812 | if (mips_arch_info != 0) | |
e9670677 | 10813 | { |
316f5878 RS |
10814 | /* -march takes precedence over -mipsN, since it is more descriptive. |
10815 | There's no harm in specifying both as long as the ISA levels | |
10816 | are the same. */ | |
10817 | if (file_mips_isa != mips_opts.isa) | |
10818 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), | |
10819 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
10820 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 10821 | } |
316f5878 RS |
10822 | else |
10823 | mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa)); | |
e9670677 MR |
10824 | } |
10825 | ||
316f5878 RS |
10826 | if (mips_arch_info == 0) |
10827 | mips_set_architecture (mips_parse_cpu ("default CPU", | |
10828 | MIPS_CPU_STRING_DEFAULT)); | |
e9670677 | 10829 | |
316f5878 RS |
10830 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
10831 | as_bad ("-march=%s is not compatible with the selected ABI", | |
10832 | mips_arch_info->name); | |
e9670677 | 10833 | |
316f5878 RS |
10834 | /* Optimize for mips_arch, unless -mtune selects a different processor. */ |
10835 | if (mips_tune_info == 0) | |
10836 | mips_set_tune (mips_arch_info); | |
e9670677 | 10837 | |
316f5878 | 10838 | if (file_mips_gp32 >= 0) |
e9670677 | 10839 | { |
316f5878 RS |
10840 | /* The user specified the size of the integer registers. Make sure |
10841 | it agrees with the ABI and ISA. */ | |
10842 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10843 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
10844 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
10845 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
10846 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
10847 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
10848 | } |
10849 | else | |
10850 | { | |
316f5878 RS |
10851 | /* Infer the integer register size from the ABI and processor. |
10852 | Restrict ourselves to 32-bit registers if that's all the | |
10853 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
10854 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
10855 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
10856 | } |
10857 | ||
316f5878 RS |
10858 | /* ??? GAS treats single-float processors as though they had 64-bit |
10859 | float registers (although it complains when double-precision | |
10860 | instructions are used). As things stand, saying they have 32-bit | |
10861 | registers would lead to spurious "register must be even" messages. | |
10862 | So here we assume float registers are always the same size as | |
10863 | integer ones, unless the user says otherwise. */ | |
10864 | if (file_mips_fp32 < 0) | |
10865 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 10866 | |
316f5878 | 10867 | /* End of GCC-shared inference code. */ |
e9670677 | 10868 | |
316f5878 RS |
10869 | /* ??? When do we want this flag to be set? Who uses it? */ |
10870 | if (file_mips_gp32 == 1 | |
10871 | && mips_abi == NO_ABI | |
10872 | && ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10873 | mips_32bitmode = 1; | |
e9670677 MR |
10874 | |
10875 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
10876 | as_bad (_("trap exception not supported at ISA 1")); | |
10877 | ||
e9670677 MR |
10878 | /* If the selected architecture includes support for ASEs, enable |
10879 | generation of code for them. */ | |
a4672219 TS |
10880 | if (mips_opts.mips16 == -1) |
10881 | mips_opts.mips16 = (CPU_HAS_MIPS16 (mips_arch)) ? 1 : 0; | |
ffdefa66 | 10882 | if (mips_opts.ase_mips3d == -1) |
a4672219 | 10883 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (mips_arch)) ? 1 : 0; |
ffdefa66 | 10884 | if (mips_opts.ase_mdmx == -1) |
a4672219 | 10885 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (mips_arch)) ? 1 : 0; |
e9670677 | 10886 | |
e9670677 | 10887 | file_mips_isa = mips_opts.isa; |
a4672219 | 10888 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
10889 | file_ase_mips3d = mips_opts.ase_mips3d; |
10890 | file_ase_mdmx = mips_opts.ase_mdmx; | |
10891 | mips_opts.gp32 = file_mips_gp32; | |
10892 | mips_opts.fp32 = file_mips_fp32; | |
10893 | ||
ecb4347a DJ |
10894 | if (mips_flag_mdebug < 0) |
10895 | { | |
10896 | #ifdef OBJ_MAYBE_ECOFF | |
10897 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
10898 | mips_flag_mdebug = 1; | |
10899 | else | |
10900 | #endif /* OBJ_MAYBE_ECOFF */ | |
10901 | mips_flag_mdebug = 0; | |
10902 | } | |
e9670677 MR |
10903 | } |
10904 | \f | |
10905 | void | |
252b5132 RH |
10906 | mips_init_after_args () |
10907 | { | |
10908 | /* initialize opcodes */ | |
10909 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10910 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10911 | } |
10912 | ||
10913 | long | |
10914 | md_pcrel_from (fixP) | |
10915 | fixS *fixP; | |
10916 | { | |
10917 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour | |
10918 | && fixP->fx_addsy != (symbolS *) NULL | |
10919 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
af6ae2ad | 10920 | return 4; |
252b5132 | 10921 | |
c9914766 | 10922 | /* Return the address of the delay slot. */ |
252b5132 RH |
10923 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; |
10924 | } | |
10925 | ||
252b5132 RH |
10926 | /* This is called before the symbol table is processed. In order to |
10927 | work with gcc when using mips-tfile, we must keep all local labels. | |
10928 | However, in other cases, we want to discard them. If we were | |
10929 | called with -g, but we didn't see any debugging information, it may | |
10930 | mean that gcc is smuggling debugging information through to | |
10931 | mips-tfile, in which case we must generate all local labels. */ | |
10932 | ||
10933 | void | |
10934 | mips_frob_file_before_adjust () | |
10935 | { | |
10936 | #ifndef NO_ECOFF_DEBUGGING | |
10937 | if (ECOFF_DEBUGGING | |
10938 | && mips_debug != 0 | |
10939 | && ! ecoff_debugging_seen) | |
10940 | flag_keep_locals = 1; | |
10941 | #endif | |
10942 | } | |
10943 | ||
10944 | /* Sort any unmatched HI16_S relocs so that they immediately precede | |
94f592af | 10945 | the corresponding LO reloc. This is called before md_apply_fix3 and |
252b5132 RH |
10946 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by |
10947 | explicit use of the %hi modifier. */ | |
10948 | ||
10949 | void | |
10950 | mips_frob_file () | |
10951 | { | |
10952 | struct mips_hi_fixup *l; | |
10953 | ||
10954 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10955 | { | |
10956 | segment_info_type *seginfo; | |
10957 | int pass; | |
10958 | ||
10959 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
10960 | ||
10961 | /* Check quickly whether the next fixup happens to be a matching | |
10962 | %lo. */ | |
10963 | if (l->fixp->fx_next != NULL | |
10964 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
10965 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
10966 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
10967 | continue; | |
10968 | ||
10969 | /* Look through the fixups for this segment for a matching %lo. | |
10970 | When we find one, move the %hi just in front of it. We do | |
10971 | this in two passes. In the first pass, we try to find a | |
10972 | unique %lo. In the second pass, we permit multiple %hi | |
10973 | relocs for a single %lo (this is a GNU extension). */ | |
10974 | seginfo = seg_info (l->seg); | |
10975 | for (pass = 0; pass < 2; pass++) | |
10976 | { | |
10977 | fixS *f, *prev; | |
10978 | ||
10979 | prev = NULL; | |
10980 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
10981 | { | |
10982 | /* Check whether this is a %lo fixup which matches l->fixp. */ | |
10983 | if (f->fx_r_type == BFD_RELOC_LO16 | |
10984 | && f->fx_addsy == l->fixp->fx_addsy | |
10985 | && f->fx_offset == l->fixp->fx_offset | |
10986 | && (pass == 1 | |
10987 | || prev == NULL | |
10988 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
10989 | || prev->fx_addsy != f->fx_addsy | |
10990 | || prev->fx_offset != f->fx_offset)) | |
10991 | { | |
10992 | fixS **pf; | |
10993 | ||
10994 | /* Move l->fixp before f. */ | |
10995 | for (pf = &seginfo->fix_root; | |
10996 | *pf != l->fixp; | |
10997 | pf = &(*pf)->fx_next) | |
10998 | assert (*pf != NULL); | |
10999 | ||
11000 | *pf = l->fixp->fx_next; | |
11001 | ||
11002 | l->fixp->fx_next = f; | |
11003 | if (prev == NULL) | |
11004 | seginfo->fix_root = l->fixp; | |
11005 | else | |
11006 | prev->fx_next = l->fixp; | |
11007 | ||
11008 | break; | |
11009 | } | |
11010 | ||
11011 | prev = f; | |
11012 | } | |
11013 | ||
11014 | if (f != NULL) | |
11015 | break; | |
11016 | ||
11017 | #if 0 /* GCC code motion plus incomplete dead code elimination | |
11018 | can leave a %hi without a %lo. */ | |
11019 | if (pass == 1) | |
11020 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
11021 | _("Unmatched %%hi reloc")); | |
11022 | #endif | |
11023 | } | |
11024 | } | |
11025 | } | |
11026 | ||
11027 | /* When generating embedded PIC code we need to use a special | |
11028 | relocation to represent the difference of two symbols in the .text | |
11029 | section (switch tables use a difference of this sort). See | |
11030 | include/coff/mips.h for details. This macro checks whether this | |
11031 | fixup requires the special reloc. */ | |
11032 | #define SWITCH_TABLE(fixp) \ | |
11033 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
bb2d6cd7 | 11034 | && OUTPUT_FLAVOR != bfd_target_elf_flavour \ |
252b5132 RH |
11035 | && (fixp)->fx_addsy != NULL \ |
11036 | && (fixp)->fx_subsy != NULL \ | |
11037 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
11038 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
11039 | ||
11040 | /* When generating embedded PIC code we must keep all PC relative | |
11041 | relocations, in case the linker has to relax a call. We also need | |
f6688943 TS |
11042 | to keep relocations for switch table entries. |
11043 | ||
11044 | We may have combined relocations without symbols in the N32/N64 ABI. | |
11045 | We have to prevent gas from dropping them. */ | |
252b5132 | 11046 | |
252b5132 RH |
11047 | int |
11048 | mips_force_relocation (fixp) | |
11049 | fixS *fixp; | |
11050 | { | |
11051 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
a161fe53 AM |
11052 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY |
11053 | || S_FORCE_RELOC (fixp->fx_addsy)) | |
252b5132 RH |
11054 | return 1; |
11055 | ||
f6688943 TS |
11056 | if (HAVE_NEWABI |
11057 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
11058 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
11059 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
11060 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
11061 | return 1; | |
11062 | ||
252b5132 RH |
11063 | return (mips_pic == EMBEDDED_PIC |
11064 | && (fixp->fx_pcrel | |
11065 | || SWITCH_TABLE (fixp) | |
11066 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
11067 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
11068 | } | |
11069 | ||
add55e1f RS |
11070 | #ifdef OBJ_ELF |
11071 | static int | |
11072 | mips_need_elf_addend_fixup (fixP) | |
11073 | fixS *fixP; | |
11074 | { | |
2d2bf3e0 CD |
11075 | if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) |
11076 | return 1; | |
b25a253c CD |
11077 | if (mips_pic == EMBEDDED_PIC |
11078 | && S_IS_WEAK (fixP->fx_addsy)) | |
11079 | return 1; | |
11080 | if (mips_pic != EMBEDDED_PIC | |
11081 | && (S_IS_WEAK (fixP->fx_addsy) | |
bad9ca53 | 11082 | || S_IS_EXTERNAL (fixP->fx_addsy)) |
2d2bf3e0 CD |
11083 | && !S_IS_COMMON (fixP->fx_addsy)) |
11084 | return 1; | |
11085 | if (symbol_used_in_reloc_p (fixP->fx_addsy) | |
11086 | && (((bfd_get_section_flags (stdoutput, | |
11087 | S_GET_SEGMENT (fixP->fx_addsy)) | |
631cb423 | 11088 | & (SEC_LINK_ONCE | SEC_MERGE)) != 0) |
2d2bf3e0 CD |
11089 | || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), |
11090 | ".gnu.linkonce", | |
11091 | sizeof (".gnu.linkonce") - 1))) | |
11092 | return 1; | |
11093 | return 0; | |
add55e1f RS |
11094 | } |
11095 | #endif | |
11096 | ||
252b5132 RH |
11097 | /* Apply a fixup to the object file. */ |
11098 | ||
94f592af NC |
11099 | void |
11100 | md_apply_fix3 (fixP, valP, seg) | |
252b5132 | 11101 | fixS *fixP; |
98d3f06f | 11102 | valueT *valP; |
94f592af | 11103 | segT seg ATTRIBUTE_UNUSED; |
252b5132 | 11104 | { |
874e8986 | 11105 | bfd_byte *buf; |
98aa84af AM |
11106 | long insn; |
11107 | valueT value; | |
ed6fb7bd | 11108 | static int previous_fx_r_type = 0; |
252b5132 | 11109 | |
65551fa4 CD |
11110 | /* FIXME: Maybe just return for all reloc types not listed below? |
11111 | Eric Christopher says: "This is stupid, please rewrite md_apply_fix3. */ | |
11112 | if (fixP->fx_r_type == BFD_RELOC_8) | |
11113 | return; | |
11114 | ||
252b5132 RH |
11115 | assert (fixP->fx_size == 4 |
11116 | || fixP->fx_r_type == BFD_RELOC_16 | |
f6688943 TS |
11117 | || fixP->fx_r_type == BFD_RELOC_32 |
11118 | || fixP->fx_r_type == BFD_RELOC_MIPS_JMP | |
11119 | || fixP->fx_r_type == BFD_RELOC_HI16_S | |
11120 | || fixP->fx_r_type == BFD_RELOC_LO16 | |
11121 | || fixP->fx_r_type == BFD_RELOC_GPREL16 | |
76b3015f | 11122 | || fixP->fx_r_type == BFD_RELOC_MIPS_LITERAL |
f6688943 | 11123 | || fixP->fx_r_type == BFD_RELOC_GPREL32 |
252b5132 | 11124 | || fixP->fx_r_type == BFD_RELOC_64 |
f6688943 TS |
11125 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11126 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
11127 | || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHEST | |
11128 | || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHER | |
11129 | || fixP->fx_r_type == BFD_RELOC_MIPS_SCN_DISP | |
11130 | || fixP->fx_r_type == BFD_RELOC_MIPS_REL16 | |
11131 | || fixP->fx_r_type == BFD_RELOC_MIPS_RELGOT | |
252b5132 | 11132 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
438c16b8 TS |
11133 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY |
11134 | || fixP->fx_r_type == BFD_RELOC_MIPS_JALR); | |
252b5132 | 11135 | |
98d3f06f | 11136 | value = *valP; |
252b5132 RH |
11137 | |
11138 | /* If we aren't adjusting this fixup to be against the section | |
11139 | symbol, we need to adjust the value. */ | |
11140 | #ifdef OBJ_ELF | |
11141 | if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
bb2d6cd7 | 11142 | { |
add55e1f | 11143 | if (mips_need_elf_addend_fixup (fixP)) |
98aa84af | 11144 | { |
d6e9d61a | 11145 | reloc_howto_type *howto; |
98aa84af | 11146 | valueT symval = S_GET_VALUE (fixP->fx_addsy); |
94f592af | 11147 | |
98aa84af | 11148 | value -= symval; |
d6e9d61a MR |
11149 | |
11150 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
af6ae2ad | 11151 | if (value != 0 && howto && howto->partial_inplace |
7a49a8c2 | 11152 | && (! fixP->fx_pcrel || howto->pcrel_offset)) |
98aa84af AM |
11153 | { |
11154 | /* In this case, the bfd_install_relocation routine will | |
11155 | incorrectly add the symbol value back in. We just want | |
7a49a8c2 | 11156 | the addend to appear in the object file. |
b34976b6 | 11157 | |
7a49a8c2 L |
11158 | howto->pcrel_offset is added for R_MIPS_PC16, which is |
11159 | generated for code like | |
b34976b6 | 11160 | |
7a49a8c2 L |
11161 | globl g1 .text |
11162 | .text | |
11163 | .space 20 | |
11164 | g1: | |
11165 | x: | |
11166 | bal g1 | |
11167 | */ | |
98aa84af | 11168 | value -= symval; |
7461da6e RS |
11169 | |
11170 | /* Make sure the addend is still non-zero. If it became zero | |
11171 | after the last operation, set it to a spurious value and | |
11172 | subtract the same value from the object file's contents. */ | |
11173 | if (value == 0) | |
11174 | { | |
11175 | value = 8; | |
11176 | ||
11177 | /* The in-place addends for LO16 relocations are signed; | |
11178 | leave the matching HI16 in-place addends as zero. */ | |
11179 | if (fixP->fx_r_type != BFD_RELOC_HI16_S) | |
11180 | { | |
7461da6e RS |
11181 | bfd_vma contents, mask, field; |
11182 | ||
7461da6e RS |
11183 | contents = bfd_get_bits (fixP->fx_frag->fr_literal |
11184 | + fixP->fx_where, | |
11185 | fixP->fx_size * 8, | |
11186 | target_big_endian); | |
11187 | ||
11188 | /* MASK has bits set where the relocation should go. | |
11189 | FIELD is -value, shifted into the appropriate place | |
11190 | for this relocation. */ | |
11191 | mask = 1 << (howto->bitsize - 1); | |
11192 | mask = (((mask - 1) << 1) | 1) << howto->bitpos; | |
11193 | field = (-value >> howto->rightshift) << howto->bitpos; | |
11194 | ||
11195 | bfd_put_bits ((field & mask) | (contents & ~mask), | |
11196 | fixP->fx_frag->fr_literal + fixP->fx_where, | |
11197 | fixP->fx_size * 8, | |
11198 | target_big_endian); | |
11199 | } | |
11200 | } | |
98aa84af AM |
11201 | } |
11202 | } | |
252b5132 | 11203 | |
bb2d6cd7 GK |
11204 | /* This code was generated using trial and error and so is |
11205 | fragile and not trustworthy. If you change it, you should | |
11206 | rerun the elf-rel, elf-rel2, and empic testcases and ensure | |
11207 | they still pass. */ | |
11208 | if (fixP->fx_pcrel || fixP->fx_subsy != NULL) | |
11209 | { | |
11210 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
11211 | ||
11212 | /* BFD's REL handling, for MIPS, is _very_ weird. | |
11213 | This gives the right results, but it can't possibly | |
11214 | be the way things are supposed to work. */ | |
af6ae2ad | 11215 | if (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2 |
bb2d6cd7 GK |
11216 | || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section) |
11217 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
11218 | } | |
11219 | } | |
11220 | #endif | |
252b5132 | 11221 | |
94f592af | 11222 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc. */ |
252b5132 | 11223 | |
ed6fb7bd SC |
11224 | /* We are not done if this is a composite relocation to set up gp. */ |
11225 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel | |
11226 | && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
10181a0d AO |
11227 | || (fixP->fx_r_type == BFD_RELOC_64 |
11228 | && (previous_fx_r_type == BFD_RELOC_GPREL32 | |
11229 | || previous_fx_r_type == BFD_RELOC_GPREL16)) | |
ed6fb7bd SC |
11230 | || (previous_fx_r_type == BFD_RELOC_MIPS_SUB |
11231 | && (fixP->fx_r_type == BFD_RELOC_HI16_S | |
11232 | || fixP->fx_r_type == BFD_RELOC_LO16)))) | |
252b5132 | 11233 | fixP->fx_done = 1; |
ed6fb7bd | 11234 | previous_fx_r_type = fixP->fx_r_type; |
252b5132 RH |
11235 | |
11236 | switch (fixP->fx_r_type) | |
11237 | { | |
11238 | case BFD_RELOC_MIPS_JMP: | |
e369bcce TS |
11239 | case BFD_RELOC_MIPS_SHIFT5: |
11240 | case BFD_RELOC_MIPS_SHIFT6: | |
11241 | case BFD_RELOC_MIPS_GOT_DISP: | |
11242 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11243 | case BFD_RELOC_MIPS_GOT_OFST: | |
11244 | case BFD_RELOC_MIPS_SUB: | |
11245 | case BFD_RELOC_MIPS_INSERT_A: | |
11246 | case BFD_RELOC_MIPS_INSERT_B: | |
11247 | case BFD_RELOC_MIPS_DELETE: | |
11248 | case BFD_RELOC_MIPS_HIGHEST: | |
11249 | case BFD_RELOC_MIPS_HIGHER: | |
11250 | case BFD_RELOC_MIPS_SCN_DISP: | |
11251 | case BFD_RELOC_MIPS_REL16: | |
11252 | case BFD_RELOC_MIPS_RELGOT: | |
11253 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11254 | case BFD_RELOC_HI16: |
11255 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11256 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11257 | case BFD_RELOC_MIPS_LITERAL: |
11258 | case BFD_RELOC_MIPS_CALL16: | |
11259 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11260 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11261 | case BFD_RELOC_MIPS_GOT_HI16: |
11262 | case BFD_RELOC_MIPS_GOT_LO16: | |
11263 | case BFD_RELOC_MIPS_CALL_HI16: | |
11264 | case BFD_RELOC_MIPS_CALL_LO16: | |
11265 | case BFD_RELOC_MIPS16_GPREL: | |
11266 | if (fixP->fx_pcrel) | |
11267 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11268 | _("Invalid PC relative reloc")); | |
11269 | /* Nothing needed to do. The value comes from the reloc entry */ | |
11270 | break; | |
11271 | ||
11272 | case BFD_RELOC_MIPS16_JMP: | |
11273 | /* We currently always generate a reloc against a symbol, which | |
11274 | means that we don't want an addend even if the symbol is | |
11275 | defined. */ | |
11276 | fixP->fx_addnumber = 0; | |
11277 | break; | |
11278 | ||
11279 | case BFD_RELOC_PCREL_HI16_S: | |
11280 | /* The addend for this is tricky if it is internal, so we just | |
11281 | do everything here rather than in bfd_install_relocation. */ | |
bdaaa2e1 | 11282 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
bb2d6cd7 GK |
11283 | && !fixP->fx_done |
11284 | && value != 0) | |
11285 | break; | |
11286 | if (fixP->fx_addsy | |
11287 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
11288 | { |
11289 | /* For an external symbol adjust by the address to make it | |
11290 | pcrel_offset. We use the address of the RELLO reloc | |
11291 | which follows this one. */ | |
11292 | value += (fixP->fx_next->fx_frag->fr_address | |
11293 | + fixP->fx_next->fx_where); | |
11294 | } | |
e7d556df | 11295 | value = ((value + 0x8000) >> 16) & 0xffff; |
874e8986 | 11296 | buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 RH |
11297 | if (target_big_endian) |
11298 | buf += 2; | |
874e8986 | 11299 | md_number_to_chars ((char *) buf, value, 2); |
252b5132 RH |
11300 | break; |
11301 | ||
11302 | case BFD_RELOC_PCREL_LO16: | |
11303 | /* The addend for this is tricky if it is internal, so we just | |
11304 | do everything here rather than in bfd_install_relocation. */ | |
bdaaa2e1 | 11305 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
bb2d6cd7 GK |
11306 | && !fixP->fx_done |
11307 | && value != 0) | |
11308 | break; | |
11309 | if (fixP->fx_addsy | |
11310 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 | 11311 | value += fixP->fx_frag->fr_address + fixP->fx_where; |
874e8986 | 11312 | buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 RH |
11313 | if (target_big_endian) |
11314 | buf += 2; | |
874e8986 | 11315 | md_number_to_chars ((char *) buf, value, 2); |
252b5132 RH |
11316 | break; |
11317 | ||
11318 | case BFD_RELOC_64: | |
11319 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11320 | extended value if we are only 32 bits. */ | |
11321 | if (fixP->fx_done | |
11322 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
11323 | { | |
11324 | if (8 <= sizeof (valueT)) | |
11325 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
11326 | value, 8); | |
11327 | else | |
11328 | { | |
11329 | long w1, w2; | |
11330 | long hiv; | |
11331 | ||
11332 | w1 = w2 = fixP->fx_where; | |
11333 | if (target_big_endian) | |
11334 | w1 += 4; | |
11335 | else | |
11336 | w2 += 4; | |
11337 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
11338 | if ((value & 0x80000000) != 0) | |
11339 | hiv = 0xffffffff; | |
11340 | else | |
11341 | hiv = 0; | |
11342 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
11343 | } | |
11344 | } | |
11345 | break; | |
11346 | ||
056350c6 | 11347 | case BFD_RELOC_RVA: |
252b5132 RH |
11348 | case BFD_RELOC_32: |
11349 | /* If we are deleting this reloc entry, we must fill in the | |
11350 | value now. This can happen if we have a .word which is not | |
11351 | resolved when it appears but is later defined. We also need | |
11352 | to fill in the value if this is an embedded PIC switch table | |
11353 | entry. */ | |
11354 | if (fixP->fx_done | |
11355 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
11356 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
11357 | value, 4); | |
11358 | break; | |
11359 | ||
11360 | case BFD_RELOC_16: | |
11361 | /* If we are deleting this reloc entry, we must fill in the | |
11362 | value now. */ | |
11363 | assert (fixP->fx_size == 2); | |
11364 | if (fixP->fx_done) | |
11365 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
11366 | value, 2); | |
11367 | break; | |
11368 | ||
11369 | case BFD_RELOC_LO16: | |
11370 | /* When handling an embedded PIC switch statement, we can wind | |
11371 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11372 | if (fixP->fx_done) | |
11373 | { | |
98aa84af | 11374 | if (value + 0x8000 > 0xffff) |
252b5132 RH |
11375 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11376 | _("relocation overflow")); | |
874e8986 | 11377 | buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 RH |
11378 | if (target_big_endian) |
11379 | buf += 2; | |
874e8986 | 11380 | md_number_to_chars ((char *) buf, value, 2); |
252b5132 RH |
11381 | } |
11382 | break; | |
11383 | ||
11384 | case BFD_RELOC_16_PCREL_S2: | |
cb56d3d3 TS |
11385 | if ((value & 0x3) != 0) |
11386 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11387 | _("Branch to odd address (%lx)"), (long) value); | |
11388 | ||
252b5132 RH |
11389 | /* |
11390 | * We need to save the bits in the instruction since fixup_segment() | |
11391 | * might be deleting the relocation entry (i.e., a branch within | |
11392 | * the current segment). | |
11393 | */ | |
af6ae2ad | 11394 | if (!fixP->fx_done && (value != 0 || HAVE_NEWABI)) |
bb2d6cd7 GK |
11395 | break; |
11396 | /* If 'value' is zero, the remaining reloc code won't actually | |
11397 | do the store, so it must be done here. This is probably | |
11398 | a bug somewhere. */ | |
b25a253c CD |
11399 | if (!fixP->fx_done |
11400 | && (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2 | |
11401 | || fixP->fx_addsy == NULL /* ??? */ | |
11402 | || ! S_IS_DEFINED (fixP->fx_addsy))) | |
bb2d6cd7 | 11403 | value -= fixP->fx_frag->fr_address + fixP->fx_where; |
bdaaa2e1 | 11404 | |
98aa84af | 11405 | value = (offsetT) value >> 2; |
252b5132 RH |
11406 | |
11407 | /* update old instruction data */ | |
874e8986 | 11408 | buf = (bfd_byte *) (fixP->fx_where + fixP->fx_frag->fr_literal); |
252b5132 RH |
11409 | if (target_big_endian) |
11410 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11411 | else | |
11412 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11413 | ||
98aa84af | 11414 | if (value + 0x8000 <= 0xffff) |
252b5132 RH |
11415 | insn |= value & 0xffff; |
11416 | else | |
11417 | { | |
11418 | /* The branch offset is too large. If this is an | |
11419 | unconditional branch, and we are not generating PIC code, | |
11420 | we can convert it to an absolute jump instruction. */ | |
11421 | if (mips_pic == NO_PIC | |
11422 | && fixP->fx_done | |
11423 | && fixP->fx_frag->fr_address >= text_section->vma | |
11424 | && (fixP->fx_frag->fr_address | |
11425 | < text_section->vma + text_section->_raw_size) | |
11426 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
11427 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11428 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
11429 | { | |
11430 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
11431 | insn = 0x0c000000; /* jal */ | |
11432 | else | |
11433 | insn = 0x08000000; /* j */ | |
11434 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11435 | fixP->fx_done = 0; | |
11436 | fixP->fx_addsy = section_symbol (text_section); | |
11437 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
11438 | } | |
11439 | else | |
11440 | { | |
4a6a3df4 AO |
11441 | /* If we got here, we have branch-relaxation disabled, |
11442 | and there's nothing we can do to fix this instruction | |
11443 | without turning it into a longer sequence. */ | |
252b5132 RH |
11444 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11445 | _("Branch out of range")); | |
11446 | } | |
11447 | } | |
11448 | ||
11449 | md_number_to_chars ((char *) buf, (valueT) insn, 4); | |
11450 | break; | |
11451 | ||
11452 | case BFD_RELOC_VTABLE_INHERIT: | |
11453 | fixP->fx_done = 0; | |
11454 | if (fixP->fx_addsy | |
11455 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11456 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11457 | S_SET_WEAK (fixP->fx_addsy); | |
11458 | break; | |
11459 | ||
11460 | case BFD_RELOC_VTABLE_ENTRY: | |
11461 | fixP->fx_done = 0; | |
11462 | break; | |
11463 | ||
11464 | default: | |
11465 | internalError (); | |
11466 | } | |
252b5132 RH |
11467 | } |
11468 | ||
11469 | #if 0 | |
11470 | void | |
11471 | printInsn (oc) | |
11472 | unsigned long oc; | |
11473 | { | |
11474 | const struct mips_opcode *p; | |
11475 | int treg, sreg, dreg, shamt; | |
11476 | short imm; | |
11477 | const char *args; | |
11478 | int i; | |
11479 | ||
11480 | for (i = 0; i < NUMOPCODES; ++i) | |
11481 | { | |
11482 | p = &mips_opcodes[i]; | |
11483 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
11484 | { | |
11485 | printf ("%08lx %s\t", oc, p->name); | |
11486 | treg = (oc >> 16) & 0x1f; | |
11487 | sreg = (oc >> 21) & 0x1f; | |
11488 | dreg = (oc >> 11) & 0x1f; | |
11489 | shamt = (oc >> 6) & 0x1f; | |
11490 | imm = oc; | |
11491 | for (args = p->args;; ++args) | |
11492 | { | |
11493 | switch (*args) | |
11494 | { | |
11495 | case '\0': | |
11496 | printf ("\n"); | |
11497 | break; | |
11498 | ||
11499 | case ',': | |
11500 | case '(': | |
11501 | case ')': | |
11502 | printf ("%c", *args); | |
11503 | continue; | |
11504 | ||
11505 | case 'r': | |
11506 | assert (treg == sreg); | |
11507 | printf ("$%d,$%d", treg, sreg); | |
11508 | continue; | |
11509 | ||
11510 | case 'd': | |
11511 | case 'G': | |
11512 | printf ("$%d", dreg); | |
11513 | continue; | |
11514 | ||
11515 | case 't': | |
11516 | case 'E': | |
11517 | printf ("$%d", treg); | |
11518 | continue; | |
11519 | ||
11520 | case 'k': | |
11521 | printf ("0x%x", treg); | |
11522 | continue; | |
11523 | ||
11524 | case 'b': | |
11525 | case 's': | |
11526 | printf ("$%d", sreg); | |
11527 | continue; | |
11528 | ||
11529 | case 'a': | |
11530 | printf ("0x%08lx", oc & 0x1ffffff); | |
11531 | continue; | |
11532 | ||
11533 | case 'i': | |
11534 | case 'j': | |
11535 | case 'o': | |
11536 | case 'u': | |
11537 | printf ("%d", imm); | |
11538 | continue; | |
11539 | ||
11540 | case '<': | |
11541 | case '>': | |
11542 | printf ("$%d", shamt); | |
11543 | continue; | |
11544 | ||
11545 | default: | |
11546 | internalError (); | |
11547 | } | |
11548 | break; | |
11549 | } | |
11550 | return; | |
11551 | } | |
11552 | } | |
11553 | printf (_("%08lx UNDEFINED\n"), oc); | |
11554 | } | |
11555 | #endif | |
11556 | ||
11557 | static symbolS * | |
11558 | get_symbol () | |
11559 | { | |
11560 | int c; | |
11561 | char *name; | |
11562 | symbolS *p; | |
11563 | ||
11564 | name = input_line_pointer; | |
11565 | c = get_symbol_end (); | |
11566 | p = (symbolS *) symbol_find_or_make (name); | |
11567 | *input_line_pointer = c; | |
11568 | return p; | |
11569 | } | |
11570 | ||
11571 | /* Align the current frag to a given power of two. The MIPS assembler | |
11572 | also automatically adjusts any preceding label. */ | |
11573 | ||
11574 | static void | |
11575 | mips_align (to, fill, label) | |
11576 | int to; | |
11577 | int fill; | |
11578 | symbolS *label; | |
11579 | { | |
b34976b6 | 11580 | mips_emit_delays (FALSE); |
252b5132 RH |
11581 | frag_align (to, fill, 0); |
11582 | record_alignment (now_seg, to); | |
11583 | if (label != NULL) | |
11584 | { | |
11585 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11586 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11587 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11588 | } | |
11589 | } | |
11590 | ||
11591 | /* Align to a given power of two. .align 0 turns off the automatic | |
11592 | alignment used by the data creating pseudo-ops. */ | |
11593 | ||
11594 | static void | |
11595 | s_align (x) | |
43841e91 | 11596 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11597 | { |
11598 | register int temp; | |
11599 | register long temp_fill; | |
11600 | long max_alignment = 15; | |
11601 | ||
11602 | /* | |
11603 | ||
11604 | o Note that the assembler pulls down any immediately preceeding label | |
11605 | to the aligned address. | |
11606 | o It's not documented but auto alignment is reinstated by | |
11607 | a .align pseudo instruction. | |
11608 | o Note also that after auto alignment is turned off the mips assembler | |
11609 | issues an error on attempt to assemble an improperly aligned data item. | |
11610 | We don't. | |
11611 | ||
11612 | */ | |
11613 | ||
11614 | temp = get_absolute_expression (); | |
11615 | if (temp > max_alignment) | |
11616 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11617 | else if (temp < 0) | |
11618 | { | |
11619 | as_warn (_("Alignment negative: 0 assumed.")); | |
11620 | temp = 0; | |
11621 | } | |
11622 | if (*input_line_pointer == ',') | |
11623 | { | |
f9419b05 | 11624 | ++input_line_pointer; |
252b5132 RH |
11625 | temp_fill = get_absolute_expression (); |
11626 | } | |
11627 | else | |
11628 | temp_fill = 0; | |
11629 | if (temp) | |
11630 | { | |
11631 | auto_align = 1; | |
11632 | mips_align (temp, (int) temp_fill, | |
11633 | insn_labels != NULL ? insn_labels->label : NULL); | |
11634 | } | |
11635 | else | |
11636 | { | |
11637 | auto_align = 0; | |
11638 | } | |
11639 | ||
11640 | demand_empty_rest_of_line (); | |
11641 | } | |
11642 | ||
11643 | void | |
11644 | mips_flush_pending_output () | |
11645 | { | |
b34976b6 | 11646 | mips_emit_delays (FALSE); |
252b5132 RH |
11647 | mips_clear_insn_labels (); |
11648 | } | |
11649 | ||
11650 | static void | |
11651 | s_change_sec (sec) | |
11652 | int sec; | |
11653 | { | |
11654 | segT seg; | |
11655 | ||
11656 | /* When generating embedded PIC code, we only use the .text, .lit8, | |
11657 | .sdata and .sbss sections. We change the .data and .rdata | |
11658 | pseudo-ops to use .sdata. */ | |
11659 | if (mips_pic == EMBEDDED_PIC | |
11660 | && (sec == 'd' || sec == 'r')) | |
11661 | sec = 's'; | |
11662 | ||
11663 | #ifdef OBJ_ELF | |
11664 | /* The ELF backend needs to know that we are changing sections, so | |
11665 | that .previous works correctly. We could do something like check | |
b6ff326e | 11666 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11667 | as it would not be appropriate to use it in the section changing |
11668 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11669 | This should be cleaner, somehow. */ | |
11670 | obj_elf_section_change_hook (); | |
11671 | #endif | |
11672 | ||
b34976b6 | 11673 | mips_emit_delays (FALSE); |
252b5132 RH |
11674 | switch (sec) |
11675 | { | |
11676 | case 't': | |
11677 | s_text (0); | |
11678 | break; | |
11679 | case 'd': | |
11680 | s_data (0); | |
11681 | break; | |
11682 | case 'b': | |
11683 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11684 | demand_empty_rest_of_line (); | |
11685 | break; | |
11686 | ||
11687 | case 'r': | |
11688 | if (USE_GLOBAL_POINTER_OPT) | |
11689 | { | |
11690 | seg = subseg_new (RDATA_SECTION_NAME, | |
11691 | (subsegT) get_absolute_expression ()); | |
11692 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11693 | { | |
11694 | bfd_set_section_flags (stdoutput, seg, | |
11695 | (SEC_ALLOC | |
11696 | | SEC_LOAD | |
11697 | | SEC_READONLY | |
11698 | | SEC_RELOC | |
11699 | | SEC_DATA)); | |
11700 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 11701 | record_alignment (seg, 4); |
252b5132 RH |
11702 | } |
11703 | demand_empty_rest_of_line (); | |
11704 | } | |
11705 | else | |
11706 | { | |
11707 | as_bad (_("No read only data section in this object file format")); | |
11708 | demand_empty_rest_of_line (); | |
11709 | return; | |
11710 | } | |
11711 | break; | |
11712 | ||
11713 | case 's': | |
11714 | if (USE_GLOBAL_POINTER_OPT) | |
11715 | { | |
11716 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
11717 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11718 | { | |
11719 | bfd_set_section_flags (stdoutput, seg, | |
11720 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
11721 | | SEC_DATA); | |
11722 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 11723 | record_alignment (seg, 4); |
252b5132 RH |
11724 | } |
11725 | demand_empty_rest_of_line (); | |
11726 | break; | |
11727 | } | |
11728 | else | |
11729 | { | |
11730 | as_bad (_("Global pointers not supported; recompile -G 0")); | |
11731 | demand_empty_rest_of_line (); | |
11732 | return; | |
11733 | } | |
11734 | } | |
11735 | ||
11736 | auto_align = 1; | |
11737 | } | |
b34976b6 | 11738 | |
cca86cc8 SC |
11739 | void |
11740 | s_change_section (ignore) | |
11741 | int ignore ATTRIBUTE_UNUSED; | |
11742 | { | |
7ed4a06a | 11743 | #ifdef OBJ_ELF |
cca86cc8 SC |
11744 | char *section_name; |
11745 | char c; | |
4cf0dd0d | 11746 | char next_c; |
cca86cc8 SC |
11747 | int section_type; |
11748 | int section_flag; | |
11749 | int section_entry_size; | |
11750 | int section_alignment; | |
b34976b6 | 11751 | |
7ed4a06a TS |
11752 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11753 | return; | |
11754 | ||
cca86cc8 SC |
11755 | section_name = input_line_pointer; |
11756 | c = get_symbol_end (); | |
a816d1ed AO |
11757 | if (c) |
11758 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 11759 | |
4cf0dd0d TS |
11760 | /* Do we have .section Name<,"flags">? */ |
11761 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11762 | { |
4cf0dd0d TS |
11763 | /* just after name is now '\0'. */ |
11764 | *input_line_pointer = c; | |
cca86cc8 SC |
11765 | input_line_pointer = section_name; |
11766 | obj_elf_section (ignore); | |
11767 | return; | |
11768 | } | |
11769 | input_line_pointer++; | |
11770 | ||
11771 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11772 | if (c == ',') | |
11773 | section_type = get_absolute_expression (); | |
11774 | else | |
11775 | section_type = 0; | |
11776 | if (*input_line_pointer++ == ',') | |
11777 | section_flag = get_absolute_expression (); | |
11778 | else | |
11779 | section_flag = 0; | |
11780 | if (*input_line_pointer++ == ',') | |
11781 | section_entry_size = get_absolute_expression (); | |
11782 | else | |
11783 | section_entry_size = 0; | |
11784 | if (*input_line_pointer++ == ',') | |
11785 | section_alignment = get_absolute_expression (); | |
11786 | else | |
11787 | section_alignment = 0; | |
11788 | ||
a816d1ed AO |
11789 | section_name = xstrdup (section_name); |
11790 | ||
cca86cc8 SC |
11791 | obj_elf_change_section (section_name, section_type, section_flag, |
11792 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
11793 | |
11794 | if (now_seg->name != section_name) | |
11795 | free (section_name); | |
7ed4a06a | 11796 | #endif /* OBJ_ELF */ |
cca86cc8 | 11797 | } |
252b5132 RH |
11798 | |
11799 | void | |
11800 | mips_enable_auto_align () | |
11801 | { | |
11802 | auto_align = 1; | |
11803 | } | |
11804 | ||
11805 | static void | |
11806 | s_cons (log_size) | |
11807 | int log_size; | |
11808 | { | |
11809 | symbolS *label; | |
11810 | ||
11811 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 11812 | mips_emit_delays (FALSE); |
252b5132 RH |
11813 | if (log_size > 0 && auto_align) |
11814 | mips_align (log_size, 0, label); | |
11815 | mips_clear_insn_labels (); | |
11816 | cons (1 << log_size); | |
11817 | } | |
11818 | ||
11819 | static void | |
11820 | s_float_cons (type) | |
11821 | int type; | |
11822 | { | |
11823 | symbolS *label; | |
11824 | ||
11825 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11826 | ||
b34976b6 | 11827 | mips_emit_delays (FALSE); |
252b5132 RH |
11828 | |
11829 | if (auto_align) | |
49309057 ILT |
11830 | { |
11831 | if (type == 'd') | |
11832 | mips_align (3, 0, label); | |
11833 | else | |
11834 | mips_align (2, 0, label); | |
11835 | } | |
252b5132 RH |
11836 | |
11837 | mips_clear_insn_labels (); | |
11838 | ||
11839 | float_cons (type); | |
11840 | } | |
11841 | ||
11842 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11843 | permitted to say | |
11844 | .globl foo .text | |
11845 | where foo is an undefined symbol, to mean that foo should be | |
11846 | considered to be the address of a function. */ | |
11847 | ||
11848 | static void | |
11849 | s_mips_globl (x) | |
43841e91 | 11850 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11851 | { |
11852 | char *name; | |
11853 | int c; | |
11854 | symbolS *symbolP; | |
11855 | flagword flag; | |
11856 | ||
11857 | name = input_line_pointer; | |
11858 | c = get_symbol_end (); | |
11859 | symbolP = symbol_find_or_make (name); | |
11860 | *input_line_pointer = c; | |
11861 | SKIP_WHITESPACE (); | |
11862 | ||
11863 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
11864 | being a function is apparently labelled as being an object. */ | |
11865 | flag = BSF_OBJECT; | |
11866 | ||
11867 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11868 | { | |
11869 | char *secname; | |
11870 | asection *sec; | |
11871 | ||
11872 | secname = input_line_pointer; | |
11873 | c = get_symbol_end (); | |
11874 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11875 | if (sec == NULL) | |
11876 | as_bad (_("%s: no such section"), secname); | |
11877 | *input_line_pointer = c; | |
11878 | ||
11879 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11880 | flag = BSF_FUNCTION; | |
11881 | } | |
11882 | ||
49309057 | 11883 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
11884 | |
11885 | S_SET_EXTERNAL (symbolP); | |
11886 | demand_empty_rest_of_line (); | |
11887 | } | |
11888 | ||
11889 | static void | |
11890 | s_option (x) | |
43841e91 | 11891 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11892 | { |
11893 | char *opt; | |
11894 | char c; | |
11895 | ||
11896 | opt = input_line_pointer; | |
11897 | c = get_symbol_end (); | |
11898 | ||
11899 | if (*opt == 'O') | |
11900 | { | |
11901 | /* FIXME: What does this mean? */ | |
11902 | } | |
11903 | else if (strncmp (opt, "pic", 3) == 0) | |
11904 | { | |
11905 | int i; | |
11906 | ||
11907 | i = atoi (opt + 3); | |
11908 | if (i == 0) | |
11909 | mips_pic = NO_PIC; | |
11910 | else if (i == 2) | |
11911 | mips_pic = SVR4_PIC; | |
11912 | else | |
11913 | as_bad (_(".option pic%d not supported"), i); | |
11914 | ||
11915 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) | |
11916 | { | |
11917 | if (g_switch_seen && g_switch_value != 0) | |
11918 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11919 | g_switch_value = 0; | |
11920 | bfd_set_gp_size (stdoutput, 0); | |
11921 | } | |
11922 | } | |
11923 | else | |
11924 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11925 | ||
11926 | *input_line_pointer = c; | |
11927 | demand_empty_rest_of_line (); | |
11928 | } | |
11929 | ||
11930 | /* This structure is used to hold a stack of .set values. */ | |
11931 | ||
e972090a NC |
11932 | struct mips_option_stack |
11933 | { | |
252b5132 RH |
11934 | struct mips_option_stack *next; |
11935 | struct mips_set_options options; | |
11936 | }; | |
11937 | ||
11938 | static struct mips_option_stack *mips_opts_stack; | |
11939 | ||
11940 | /* Handle the .set pseudo-op. */ | |
11941 | ||
11942 | static void | |
11943 | s_mipsset (x) | |
43841e91 | 11944 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11945 | { |
11946 | char *name = input_line_pointer, ch; | |
11947 | ||
11948 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 11949 | ++input_line_pointer; |
252b5132 RH |
11950 | ch = *input_line_pointer; |
11951 | *input_line_pointer = '\0'; | |
11952 | ||
11953 | if (strcmp (name, "reorder") == 0) | |
11954 | { | |
11955 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
11956 | { | |
11957 | /* If we still have pending nops, we can discard them. The | |
11958 | usual nop handling will insert any that are still | |
bdaaa2e1 | 11959 | needed. */ |
252b5132 RH |
11960 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
11961 | * (mips_opts.mips16 ? 2 : 4)); | |
11962 | prev_nop_frag = NULL; | |
11963 | } | |
11964 | mips_opts.noreorder = 0; | |
11965 | } | |
11966 | else if (strcmp (name, "noreorder") == 0) | |
11967 | { | |
b34976b6 | 11968 | mips_emit_delays (TRUE); |
252b5132 RH |
11969 | mips_opts.noreorder = 1; |
11970 | mips_any_noreorder = 1; | |
11971 | } | |
11972 | else if (strcmp (name, "at") == 0) | |
11973 | { | |
11974 | mips_opts.noat = 0; | |
11975 | } | |
11976 | else if (strcmp (name, "noat") == 0) | |
11977 | { | |
11978 | mips_opts.noat = 1; | |
11979 | } | |
11980 | else if (strcmp (name, "macro") == 0) | |
11981 | { | |
11982 | mips_opts.warn_about_macros = 0; | |
11983 | } | |
11984 | else if (strcmp (name, "nomacro") == 0) | |
11985 | { | |
11986 | if (mips_opts.noreorder == 0) | |
11987 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11988 | mips_opts.warn_about_macros = 1; | |
11989 | } | |
11990 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11991 | { | |
11992 | mips_opts.nomove = 0; | |
11993 | } | |
11994 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11995 | { | |
11996 | mips_opts.nomove = 1; | |
11997 | } | |
11998 | else if (strcmp (name, "bopt") == 0) | |
11999 | { | |
12000 | mips_opts.nobopt = 0; | |
12001 | } | |
12002 | else if (strcmp (name, "nobopt") == 0) | |
12003 | { | |
12004 | mips_opts.nobopt = 1; | |
12005 | } | |
12006 | else if (strcmp (name, "mips16") == 0 | |
12007 | || strcmp (name, "MIPS-16") == 0) | |
12008 | mips_opts.mips16 = 1; | |
12009 | else if (strcmp (name, "nomips16") == 0 | |
12010 | || strcmp (name, "noMIPS-16") == 0) | |
12011 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
12012 | else if (strcmp (name, "mips3d") == 0) |
12013 | mips_opts.ase_mips3d = 1; | |
12014 | else if (strcmp (name, "nomips3d") == 0) | |
12015 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
12016 | else if (strcmp (name, "mdmx") == 0) |
12017 | mips_opts.ase_mdmx = 1; | |
12018 | else if (strcmp (name, "nomdmx") == 0) | |
12019 | mips_opts.ase_mdmx = 0; | |
252b5132 RH |
12020 | else if (strncmp (name, "mips", 4) == 0) |
12021 | { | |
12022 | int isa; | |
12023 | ||
12024 | /* Permit the user to change the ISA on the fly. Needless to | |
12025 | say, misuse can cause serious problems. */ | |
12026 | isa = atoi (name + 4); | |
553178e4 | 12027 | switch (isa) |
98d3f06f KH |
12028 | { |
12029 | case 0: | |
12030 | mips_opts.gp32 = file_mips_gp32; | |
12031 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f KH |
12032 | break; |
12033 | case 1: | |
12034 | case 2: | |
12035 | case 32: | |
12036 | mips_opts.gp32 = 1; | |
12037 | mips_opts.fp32 = 1; | |
12038 | break; | |
12039 | case 3: | |
12040 | case 4: | |
12041 | case 5: | |
12042 | case 64: | |
98d3f06f KH |
12043 | mips_opts.gp32 = 0; |
12044 | mips_opts.fp32 = 0; | |
12045 | break; | |
12046 | default: | |
12047 | as_bad (_("unknown ISA level %s"), name + 4); | |
12048 | break; | |
12049 | } | |
553178e4 | 12050 | |
e7af610e | 12051 | switch (isa) |
98d3f06f KH |
12052 | { |
12053 | case 0: mips_opts.isa = file_mips_isa; break; | |
12054 | case 1: mips_opts.isa = ISA_MIPS1; break; | |
12055 | case 2: mips_opts.isa = ISA_MIPS2; break; | |
12056 | case 3: mips_opts.isa = ISA_MIPS3; break; | |
12057 | case 4: mips_opts.isa = ISA_MIPS4; break; | |
12058 | case 5: mips_opts.isa = ISA_MIPS5; break; | |
12059 | case 32: mips_opts.isa = ISA_MIPS32; break; | |
12060 | case 64: mips_opts.isa = ISA_MIPS64; break; | |
12061 | default: as_bad (_("unknown ISA level %s"), name + 4); break; | |
12062 | } | |
252b5132 RH |
12063 | } |
12064 | else if (strcmp (name, "autoextend") == 0) | |
12065 | mips_opts.noautoextend = 0; | |
12066 | else if (strcmp (name, "noautoextend") == 0) | |
12067 | mips_opts.noautoextend = 1; | |
12068 | else if (strcmp (name, "push") == 0) | |
12069 | { | |
12070 | struct mips_option_stack *s; | |
12071 | ||
12072 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
12073 | s->next = mips_opts_stack; | |
12074 | s->options = mips_opts; | |
12075 | mips_opts_stack = s; | |
12076 | } | |
12077 | else if (strcmp (name, "pop") == 0) | |
12078 | { | |
12079 | struct mips_option_stack *s; | |
12080 | ||
12081 | s = mips_opts_stack; | |
12082 | if (s == NULL) | |
12083 | as_bad (_(".set pop with no .set push")); | |
12084 | else | |
12085 | { | |
12086 | /* If we're changing the reorder mode we need to handle | |
12087 | delay slots correctly. */ | |
12088 | if (s->options.noreorder && ! mips_opts.noreorder) | |
b34976b6 | 12089 | mips_emit_delays (TRUE); |
252b5132 RH |
12090 | else if (! s->options.noreorder && mips_opts.noreorder) |
12091 | { | |
12092 | if (prev_nop_frag != NULL) | |
12093 | { | |
12094 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
12095 | * (mips_opts.mips16 ? 2 : 4)); | |
12096 | prev_nop_frag = NULL; | |
12097 | } | |
12098 | } | |
12099 | ||
12100 | mips_opts = s->options; | |
12101 | mips_opts_stack = s->next; | |
12102 | free (s); | |
12103 | } | |
12104 | } | |
12105 | else | |
12106 | { | |
12107 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
12108 | } | |
12109 | *input_line_pointer = ch; | |
12110 | demand_empty_rest_of_line (); | |
12111 | } | |
12112 | ||
12113 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
12114 | .option pic2. It means to generate SVR4 PIC calls. */ | |
12115 | ||
12116 | static void | |
12117 | s_abicalls (ignore) | |
43841e91 | 12118 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12119 | { |
12120 | mips_pic = SVR4_PIC; | |
12121 | if (USE_GLOBAL_POINTER_OPT) | |
12122 | { | |
12123 | if (g_switch_seen && g_switch_value != 0) | |
12124 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12125 | g_switch_value = 0; | |
12126 | } | |
12127 | bfd_set_gp_size (stdoutput, 0); | |
12128 | demand_empty_rest_of_line (); | |
12129 | } | |
12130 | ||
12131 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
12132 | PIC code. It sets the $gp register for the function based on the | |
12133 | function address, which is in the register named in the argument. | |
12134 | This uses a relocation against _gp_disp, which is handled specially | |
12135 | by the linker. The result is: | |
12136 | lui $gp,%hi(_gp_disp) | |
12137 | addiu $gp,$gp,%lo(_gp_disp) | |
12138 | addu $gp,$gp,.cpload argument | |
12139 | The .cpload argument is normally $25 == $t9. */ | |
12140 | ||
12141 | static void | |
12142 | s_cpload (ignore) | |
43841e91 | 12143 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12144 | { |
12145 | expressionS ex; | |
12146 | int icnt = 0; | |
12147 | ||
6478892d TS |
12148 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
12149 | .cpload is ignored. */ | |
12150 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
12151 | { |
12152 | s_ignore (0); | |
12153 | return; | |
12154 | } | |
12155 | ||
d3ecfc59 | 12156 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
12157 | if (mips_opts.noreorder == 0) |
12158 | as_warn (_(".cpload not in noreorder section")); | |
12159 | ||
12160 | ex.X_op = O_symbol; | |
12161 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
12162 | ex.X_op_symbol = NULL; | |
12163 | ex.X_add_number = 0; | |
12164 | ||
12165 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 12166 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 12167 | |
c9914766 TS |
12168 | macro_build_lui (NULL, &icnt, &ex, mips_gp_register); |
12169 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", | |
12170 | mips_gp_register, mips_gp_register, (int) BFD_RELOC_LO16); | |
252b5132 RH |
12171 | |
12172 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", | |
c9914766 | 12173 | mips_gp_register, mips_gp_register, tc_get_register (0)); |
252b5132 RH |
12174 | |
12175 | demand_empty_rest_of_line (); | |
12176 | } | |
12177 | ||
6478892d TS |
12178 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
12179 | .cpsetup $reg1, offset|$reg2, label | |
12180 | ||
12181 | If offset is given, this results in: | |
12182 | sd $gp, offset($sp) | |
956cd1d6 | 12183 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12184 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12185 | daddu $gp, $gp, $reg1 | |
6478892d TS |
12186 | |
12187 | If $reg2 is given, this results in: | |
12188 | daddu $reg2, $gp, $0 | |
956cd1d6 | 12189 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12190 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12191 | daddu $gp, $gp, $reg1 | |
12192 | $reg1 is normally $25 == $t9. */ | |
6478892d TS |
12193 | static void |
12194 | s_cpsetup (ignore) | |
12195 | int ignore ATTRIBUTE_UNUSED; | |
12196 | { | |
12197 | expressionS ex_off; | |
12198 | expressionS ex_sym; | |
12199 | int reg1; | |
12200 | int icnt = 0; | |
f21f8242 | 12201 | char *f; |
6478892d | 12202 | |
8586fc66 | 12203 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
12204 | We also need NewABI support. */ |
12205 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12206 | { | |
12207 | s_ignore (0); | |
12208 | return; | |
12209 | } | |
12210 | ||
12211 | reg1 = tc_get_register (0); | |
12212 | SKIP_WHITESPACE (); | |
12213 | if (*input_line_pointer != ',') | |
12214 | { | |
12215 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12216 | return; | |
12217 | } | |
12218 | else | |
80245285 | 12219 | ++input_line_pointer; |
6478892d TS |
12220 | SKIP_WHITESPACE (); |
12221 | if (*input_line_pointer == '$') | |
80245285 TS |
12222 | { |
12223 | mips_cpreturn_register = tc_get_register (0); | |
12224 | mips_cpreturn_offset = -1; | |
12225 | } | |
6478892d | 12226 | else |
80245285 TS |
12227 | { |
12228 | mips_cpreturn_offset = get_absolute_expression (); | |
12229 | mips_cpreturn_register = -1; | |
12230 | } | |
6478892d TS |
12231 | SKIP_WHITESPACE (); |
12232 | if (*input_line_pointer != ',') | |
12233 | { | |
12234 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12235 | return; | |
12236 | } | |
12237 | else | |
f9419b05 | 12238 | ++input_line_pointer; |
6478892d | 12239 | SKIP_WHITESPACE (); |
f21f8242 | 12240 | expression (&ex_sym); |
6478892d TS |
12241 | |
12242 | if (mips_cpreturn_register == -1) | |
12243 | { | |
12244 | ex_off.X_op = O_constant; | |
12245 | ex_off.X_add_symbol = NULL; | |
12246 | ex_off.X_op_symbol = NULL; | |
12247 | ex_off.X_add_number = mips_cpreturn_offset; | |
12248 | ||
12249 | macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)", | |
12250 | mips_gp_register, (int) BFD_RELOC_LO16, SP); | |
12251 | } | |
12252 | else | |
12253 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", | |
12254 | "d,v,t", mips_cpreturn_register, mips_gp_register, 0); | |
12255 | ||
f21f8242 AO |
12256 | /* Ensure there's room for the next two instructions, so that `f' |
12257 | doesn't end up with an address in the wrong frag. */ | |
12258 | frag_grow (8); | |
12259 | f = frag_more (0); | |
6478892d TS |
12260 | macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register, |
12261 | (int) BFD_RELOC_GPREL16); | |
f21f8242 AO |
12262 | fix_new (frag_now, f - frag_now->fr_literal, |
12263 | 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB); | |
12264 | fix_new (frag_now, f - frag_now->fr_literal, | |
12265 | 0, NULL, 0, 0, BFD_RELOC_HI16_S); | |
12266 | ||
12267 | f = frag_more (0); | |
6478892d TS |
12268 | macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j", |
12269 | mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
f21f8242 AO |
12270 | fix_new (frag_now, f - frag_now->fr_literal, |
12271 | 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB); | |
12272 | fix_new (frag_now, f - frag_now->fr_literal, | |
12273 | 0, NULL, 0, 0, BFD_RELOC_LO16); | |
12274 | ||
8586fc66 TS |
12275 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
12276 | HAVE_64BIT_ADDRESSES ? "daddu" : "addu", "d,v,t", | |
12277 | mips_gp_register, mips_gp_register, reg1); | |
6478892d TS |
12278 | |
12279 | demand_empty_rest_of_line (); | |
12280 | } | |
12281 | ||
12282 | static void | |
12283 | s_cplocal (ignore) | |
12284 | int ignore ATTRIBUTE_UNUSED; | |
12285 | { | |
12286 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
12287 | .cplocal is ignored. */ | |
12288 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12289 | { | |
12290 | s_ignore (0); | |
12291 | return; | |
12292 | } | |
12293 | ||
12294 | mips_gp_register = tc_get_register (0); | |
85b51719 | 12295 | demand_empty_rest_of_line (); |
6478892d TS |
12296 | } |
12297 | ||
252b5132 RH |
12298 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
12299 | offset from $sp. The offset is remembered, and after making a PIC | |
12300 | call $gp is restored from that location. */ | |
12301 | ||
12302 | static void | |
12303 | s_cprestore (ignore) | |
43841e91 | 12304 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12305 | { |
12306 | expressionS ex; | |
12307 | int icnt = 0; | |
12308 | ||
6478892d | 12309 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 12310 | .cprestore is ignored. */ |
6478892d | 12311 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
12312 | { |
12313 | s_ignore (0); | |
12314 | return; | |
12315 | } | |
12316 | ||
12317 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12318 | mips_cprestore_valid = 1; |
252b5132 RH |
12319 | |
12320 | ex.X_op = O_constant; | |
12321 | ex.X_add_symbol = NULL; | |
12322 | ex.X_op_symbol = NULL; | |
12323 | ex.X_add_number = mips_cprestore_offset; | |
12324 | ||
885add95 CD |
12325 | macro_build_ldst_constoffset ((char *) NULL, &icnt, &ex, |
12326 | HAVE_32BIT_ADDRESSES ? "sw" : "sd", | |
12327 | mips_gp_register, SP); | |
252b5132 RH |
12328 | |
12329 | demand_empty_rest_of_line (); | |
12330 | } | |
12331 | ||
6478892d TS |
12332 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
12333 | was given in the preceeding .gpsetup, it results in: | |
12334 | ld $gp, offset($sp) | |
76b3015f | 12335 | |
6478892d TS |
12336 | If a register $reg2 was given there, it results in: |
12337 | daddiu $gp, $gp, $reg2 | |
12338 | */ | |
12339 | static void | |
12340 | s_cpreturn (ignore) | |
12341 | int ignore ATTRIBUTE_UNUSED; | |
12342 | { | |
12343 | expressionS ex; | |
12344 | int icnt = 0; | |
12345 | ||
12346 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12347 | We also need NewABI support. */ | |
12348 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12349 | { | |
12350 | s_ignore (0); | |
12351 | return; | |
12352 | } | |
12353 | ||
12354 | if (mips_cpreturn_register == -1) | |
12355 | { | |
12356 | ex.X_op = O_constant; | |
12357 | ex.X_add_symbol = NULL; | |
12358 | ex.X_op_symbol = NULL; | |
12359 | ex.X_add_number = mips_cpreturn_offset; | |
12360 | ||
12361 | macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)", | |
12362 | mips_gp_register, (int) BFD_RELOC_LO16, SP); | |
12363 | } | |
12364 | else | |
12365 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", | |
12366 | "d,v,t", mips_gp_register, mips_cpreturn_register, 0); | |
12367 | ||
12368 | demand_empty_rest_of_line (); | |
12369 | } | |
12370 | ||
12371 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12372 | code. It sets the offset to use in gp_rel relocations. */ | |
12373 | ||
12374 | static void | |
12375 | s_gpvalue (ignore) | |
12376 | int ignore ATTRIBUTE_UNUSED; | |
12377 | { | |
12378 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12379 | We also need NewABI support. */ | |
12380 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12381 | { | |
12382 | s_ignore (0); | |
12383 | return; | |
12384 | } | |
12385 | ||
def2e0dd | 12386 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12387 | |
12388 | demand_empty_rest_of_line (); | |
12389 | } | |
12390 | ||
252b5132 RH |
12391 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12392 | code. It generates a 32 bit GP relative reloc. */ | |
12393 | ||
12394 | static void | |
12395 | s_gpword (ignore) | |
43841e91 | 12396 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12397 | { |
12398 | symbolS *label; | |
12399 | expressionS ex; | |
12400 | char *p; | |
12401 | ||
12402 | /* When not generating PIC code, this is treated as .word. */ | |
12403 | if (mips_pic != SVR4_PIC) | |
12404 | { | |
12405 | s_cons (2); | |
12406 | return; | |
12407 | } | |
12408 | ||
12409 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12410 | mips_emit_delays (TRUE); |
252b5132 RH |
12411 | if (auto_align) |
12412 | mips_align (2, 0, label); | |
12413 | mips_clear_insn_labels (); | |
12414 | ||
12415 | expression (&ex); | |
12416 | ||
12417 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12418 | { | |
12419 | as_bad (_("Unsupported use of .gpword")); | |
12420 | ignore_rest_of_line (); | |
12421 | } | |
12422 | ||
12423 | p = frag_more (4); | |
12424 | md_number_to_chars (p, (valueT) 0, 4); | |
b34976b6 | 12425 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12426 | BFD_RELOC_GPREL32); |
252b5132 RH |
12427 | |
12428 | demand_empty_rest_of_line (); | |
12429 | } | |
12430 | ||
10181a0d AO |
12431 | static void |
12432 | s_gpdword (ignore) | |
12433 | int ignore ATTRIBUTE_UNUSED; | |
12434 | { | |
12435 | symbolS *label; | |
12436 | expressionS ex; | |
12437 | char *p; | |
12438 | ||
12439 | /* When not generating PIC code, this is treated as .dword. */ | |
12440 | if (mips_pic != SVR4_PIC) | |
12441 | { | |
12442 | s_cons (3); | |
12443 | return; | |
12444 | } | |
12445 | ||
12446 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12447 | mips_emit_delays (TRUE); |
10181a0d AO |
12448 | if (auto_align) |
12449 | mips_align (3, 0, label); | |
12450 | mips_clear_insn_labels (); | |
12451 | ||
12452 | expression (&ex); | |
12453 | ||
12454 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12455 | { | |
12456 | as_bad (_("Unsupported use of .gpdword")); | |
12457 | ignore_rest_of_line (); | |
12458 | } | |
12459 | ||
12460 | p = frag_more (8); | |
12461 | md_number_to_chars (p, (valueT) 0, 8); | |
b34976b6 | 12462 | fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE, |
10181a0d AO |
12463 | BFD_RELOC_GPREL32); |
12464 | ||
12465 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
12466 | ex.X_op = O_absent; | |
12467 | ex.X_add_symbol = 0; | |
12468 | ex.X_add_number = 0; | |
b34976b6 | 12469 | fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE, |
10181a0d AO |
12470 | BFD_RELOC_64); |
12471 | ||
12472 | demand_empty_rest_of_line (); | |
12473 | } | |
12474 | ||
252b5132 RH |
12475 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12476 | tables in SVR4 PIC code. */ | |
12477 | ||
12478 | static void | |
12479 | s_cpadd (ignore) | |
43841e91 | 12480 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12481 | { |
12482 | int icnt = 0; | |
12483 | int reg; | |
12484 | ||
10181a0d AO |
12485 | /* This is ignored when not generating SVR4 PIC code. */ |
12486 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12487 | { |
12488 | s_ignore (0); | |
12489 | return; | |
12490 | } | |
12491 | ||
12492 | /* Add $gp to the register named as an argument. */ | |
12493 | reg = tc_get_register (0); | |
12494 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 12495 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 12496 | "d,v,t", reg, reg, mips_gp_register); |
252b5132 | 12497 | |
bdaaa2e1 | 12498 | demand_empty_rest_of_line (); |
252b5132 RH |
12499 | } |
12500 | ||
12501 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12502 | mips16 mode. This permits the linker to handle them specially, | |
12503 | such as generating jalx instructions when needed. We also make | |
12504 | them odd for the duration of the assembly, in order to generate the | |
12505 | right sort of code. We will make them even in the adjust_symtab | |
12506 | routine, while leaving them marked. This is convenient for the | |
12507 | debugger and the disassembler. The linker knows to make them odd | |
12508 | again. */ | |
12509 | ||
12510 | static void | |
12511 | s_insn (ignore) | |
43841e91 | 12512 | int ignore ATTRIBUTE_UNUSED; |
252b5132 | 12513 | { |
f9419b05 | 12514 | mips16_mark_labels (); |
252b5132 RH |
12515 | |
12516 | demand_empty_rest_of_line (); | |
12517 | } | |
12518 | ||
12519 | /* Handle a .stabn directive. We need these in order to mark a label | |
12520 | as being a mips16 text label correctly. Sometimes the compiler | |
12521 | will emit a label, followed by a .stabn, and then switch sections. | |
12522 | If the label and .stabn are in mips16 mode, then the label is | |
12523 | really a mips16 text label. */ | |
12524 | ||
12525 | static void | |
12526 | s_mips_stab (type) | |
12527 | int type; | |
12528 | { | |
f9419b05 | 12529 | if (type == 'n') |
252b5132 RH |
12530 | mips16_mark_labels (); |
12531 | ||
12532 | s_stab (type); | |
12533 | } | |
12534 | ||
12535 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12536 | */ | |
12537 | ||
12538 | static void | |
12539 | s_mips_weakext (ignore) | |
43841e91 | 12540 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12541 | { |
12542 | char *name; | |
12543 | int c; | |
12544 | symbolS *symbolP; | |
12545 | expressionS exp; | |
12546 | ||
12547 | name = input_line_pointer; | |
12548 | c = get_symbol_end (); | |
12549 | symbolP = symbol_find_or_make (name); | |
12550 | S_SET_WEAK (symbolP); | |
12551 | *input_line_pointer = c; | |
12552 | ||
12553 | SKIP_WHITESPACE (); | |
12554 | ||
12555 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12556 | { | |
12557 | if (S_IS_DEFINED (symbolP)) | |
12558 | { | |
956cd1d6 | 12559 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12560 | S_GET_NAME (symbolP)); |
12561 | ignore_rest_of_line (); | |
12562 | return; | |
12563 | } | |
bdaaa2e1 | 12564 | |
252b5132 RH |
12565 | if (*input_line_pointer == ',') |
12566 | { | |
12567 | ++input_line_pointer; | |
12568 | SKIP_WHITESPACE (); | |
12569 | } | |
bdaaa2e1 | 12570 | |
252b5132 RH |
12571 | expression (&exp); |
12572 | if (exp.X_op != O_symbol) | |
12573 | { | |
12574 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12575 | ignore_rest_of_line (); |
252b5132 RH |
12576 | return; |
12577 | } | |
49309057 | 12578 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12579 | } |
12580 | ||
12581 | demand_empty_rest_of_line (); | |
12582 | } | |
12583 | ||
12584 | /* Parse a register string into a number. Called from the ECOFF code | |
12585 | to parse .frame. The argument is non-zero if this is the frame | |
12586 | register, so that we can record it in mips_frame_reg. */ | |
12587 | ||
12588 | int | |
12589 | tc_get_register (frame) | |
12590 | int frame; | |
12591 | { | |
12592 | int reg; | |
12593 | ||
12594 | SKIP_WHITESPACE (); | |
12595 | if (*input_line_pointer++ != '$') | |
12596 | { | |
12597 | as_warn (_("expected `$'")); | |
85b51719 | 12598 | reg = ZERO; |
252b5132 | 12599 | } |
3882b010 | 12600 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12601 | { |
12602 | reg = get_absolute_expression (); | |
12603 | if (reg < 0 || reg >= 32) | |
12604 | { | |
12605 | as_warn (_("Bad register number")); | |
85b51719 | 12606 | reg = ZERO; |
252b5132 RH |
12607 | } |
12608 | } | |
12609 | else | |
12610 | { | |
76db943d | 12611 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12612 | { |
12613 | reg = RA; | |
12614 | input_line_pointer += 2; | |
12615 | } | |
76db943d | 12616 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12617 | { |
12618 | reg = FP; | |
12619 | input_line_pointer += 2; | |
12620 | } | |
252b5132 | 12621 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12622 | { |
12623 | reg = SP; | |
12624 | input_line_pointer += 2; | |
12625 | } | |
252b5132 | 12626 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12627 | { |
12628 | reg = GP; | |
12629 | input_line_pointer += 2; | |
12630 | } | |
252b5132 | 12631 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12632 | { |
12633 | reg = AT; | |
12634 | input_line_pointer += 2; | |
12635 | } | |
12636 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12637 | { | |
12638 | reg = KT0; | |
12639 | input_line_pointer += 3; | |
12640 | } | |
12641 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12642 | { | |
12643 | reg = KT1; | |
12644 | input_line_pointer += 3; | |
12645 | } | |
12646 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12647 | { | |
12648 | reg = ZERO; | |
12649 | input_line_pointer += 4; | |
12650 | } | |
252b5132 RH |
12651 | else |
12652 | { | |
12653 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12654 | reg = ZERO; |
12655 | while (ISALNUM(*input_line_pointer)) | |
12656 | input_line_pointer++; | |
252b5132 | 12657 | } |
252b5132 RH |
12658 | } |
12659 | if (frame) | |
7a621144 DJ |
12660 | { |
12661 | mips_frame_reg = reg != 0 ? reg : SP; | |
12662 | mips_frame_reg_valid = 1; | |
12663 | mips_cprestore_valid = 0; | |
12664 | } | |
252b5132 RH |
12665 | return reg; |
12666 | } | |
12667 | ||
12668 | valueT | |
12669 | md_section_align (seg, addr) | |
12670 | asection *seg; | |
12671 | valueT addr; | |
12672 | { | |
12673 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12674 | ||
12675 | #ifdef OBJ_ELF | |
12676 | /* We don't need to align ELF sections to the full alignment. | |
12677 | However, Irix 5 may prefer that we align them at least to a 16 | |
12678 | byte boundary. We don't bother to align the sections if we are | |
12679 | targeted for an embedded system. */ | |
12680 | if (strcmp (TARGET_OS, "elf") == 0) | |
12681 | return addr; | |
12682 | if (align > 4) | |
12683 | align = 4; | |
12684 | #endif | |
12685 | ||
12686 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12687 | } | |
12688 | ||
12689 | /* Utility routine, called from above as well. If called while the | |
12690 | input file is still being read, it's only an approximation. (For | |
12691 | example, a symbol may later become defined which appeared to be | |
12692 | undefined earlier.) */ | |
12693 | ||
12694 | static int | |
12695 | nopic_need_relax (sym, before_relaxing) | |
12696 | symbolS *sym; | |
12697 | int before_relaxing; | |
12698 | { | |
12699 | if (sym == 0) | |
12700 | return 0; | |
12701 | ||
6478892d | 12702 | if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0) |
252b5132 RH |
12703 | { |
12704 | const char *symname; | |
12705 | int change; | |
12706 | ||
c9914766 | 12707 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12708 | register. It can be if it is smaller than the -G size or if |
12709 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12710 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12711 | they can. */ |
12712 | symname = S_GET_NAME (sym); | |
12713 | if (symname != (const char *) NULL | |
12714 | && (strcmp (symname, "eprol") == 0 | |
12715 | || strcmp (symname, "etext") == 0 | |
12716 | || strcmp (symname, "_gp") == 0 | |
12717 | || strcmp (symname, "edata") == 0 | |
12718 | || strcmp (symname, "_fbss") == 0 | |
12719 | || strcmp (symname, "_fdata") == 0 | |
12720 | || strcmp (symname, "_ftext") == 0 | |
12721 | || strcmp (symname, "end") == 0 | |
12722 | || strcmp (symname, "_gp_disp") == 0)) | |
12723 | change = 1; | |
12724 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12725 | && (0 | |
12726 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12727 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12728 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12729 | <= g_switch_value)) | |
252b5132 RH |
12730 | #endif |
12731 | /* We must defer this decision until after the whole | |
12732 | file has been read, since there might be a .extern | |
12733 | after the first use of this symbol. */ | |
12734 | || (before_relaxing | |
12735 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12736 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12737 | #endif |
12738 | && S_GET_VALUE (sym) == 0) | |
12739 | || (S_GET_VALUE (sym) != 0 | |
12740 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12741 | change = 0; | |
12742 | else | |
12743 | { | |
12744 | const char *segname; | |
12745 | ||
12746 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12747 | assert (strcmp (segname, ".lit8") != 0 | |
12748 | && strcmp (segname, ".lit4") != 0); | |
12749 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12750 | && strcmp (segname, ".sbss") != 0 |
12751 | && strncmp (segname, ".sdata.", 7) != 0 | |
12752 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12753 | } |
12754 | return change; | |
12755 | } | |
12756 | else | |
c9914766 | 12757 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12758 | return 1; |
12759 | } | |
12760 | ||
12761 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an | |
12762 | extended opcode. SEC is the section the frag is in. */ | |
12763 | ||
12764 | static int | |
12765 | mips16_extended_frag (fragp, sec, stretch) | |
12766 | fragS *fragp; | |
12767 | asection *sec; | |
12768 | long stretch; | |
12769 | { | |
12770 | int type; | |
12771 | register const struct mips16_immed_operand *op; | |
12772 | offsetT val; | |
12773 | int mintiny, maxtiny; | |
12774 | segT symsec; | |
98aa84af | 12775 | fragS *sym_frag; |
252b5132 RH |
12776 | |
12777 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12778 | return 0; | |
12779 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12780 | return 1; | |
12781 | ||
12782 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12783 | op = mips16_immed_operands; | |
12784 | while (op->type != type) | |
12785 | { | |
12786 | ++op; | |
12787 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12788 | } | |
12789 | ||
12790 | if (op->unsp) | |
12791 | { | |
12792 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12793 | { | |
12794 | mintiny = 1; | |
12795 | maxtiny = 1 << op->nbits; | |
12796 | } | |
12797 | else | |
12798 | { | |
12799 | mintiny = 0; | |
12800 | maxtiny = (1 << op->nbits) - 1; | |
12801 | } | |
12802 | } | |
12803 | else | |
12804 | { | |
12805 | mintiny = - (1 << (op->nbits - 1)); | |
12806 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12807 | } | |
12808 | ||
98aa84af | 12809 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12810 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12811 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12812 | |
12813 | if (op->pcrel) | |
12814 | { | |
12815 | addressT addr; | |
12816 | ||
12817 | /* We won't have the section when we are called from | |
12818 | mips_relax_frag. However, we will always have been called | |
12819 | from md_estimate_size_before_relax first. If this is a | |
12820 | branch to a different section, we mark it as such. If SEC is | |
12821 | NULL, and the frag is not marked, then it must be a branch to | |
12822 | the same section. */ | |
12823 | if (sec == NULL) | |
12824 | { | |
12825 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12826 | return 1; | |
12827 | } | |
12828 | else | |
12829 | { | |
98aa84af | 12830 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12831 | if (symsec != sec) |
12832 | { | |
12833 | fragp->fr_subtype = | |
12834 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12835 | ||
12836 | /* FIXME: We should support this, and let the linker | |
12837 | catch branches and loads that are out of range. */ | |
12838 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12839 | _("unsupported PC relative reference to different section")); | |
12840 | ||
12841 | return 1; | |
12842 | } | |
98aa84af AM |
12843 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12844 | /* Assume non-extended on the first relaxation pass. | |
12845 | The address we have calculated will be bogus if this is | |
12846 | a forward branch to another frag, as the forward frag | |
12847 | will have fr_address == 0. */ | |
12848 | return 0; | |
252b5132 RH |
12849 | } |
12850 | ||
12851 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12852 | the same section. If the relax_marker of the symbol fragment |
12853 | differs from the relax_marker of this fragment, we have not | |
12854 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12855 | in STRETCH in order to get a better estimate of the address. |
12856 | This particularly matters because of the shift bits. */ | |
12857 | if (stretch != 0 | |
98aa84af | 12858 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12859 | { |
12860 | fragS *f; | |
12861 | ||
12862 | /* Adjust stretch for any alignment frag. Note that if have | |
12863 | been expanding the earlier code, the symbol may be | |
12864 | defined in what appears to be an earlier frag. FIXME: | |
12865 | This doesn't handle the fr_subtype field, which specifies | |
12866 | a maximum number of bytes to skip when doing an | |
12867 | alignment. */ | |
98aa84af | 12868 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12869 | { |
12870 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12871 | { | |
12872 | if (stretch < 0) | |
12873 | stretch = - ((- stretch) | |
12874 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12875 | else | |
12876 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12877 | if (stretch == 0) | |
12878 | break; | |
12879 | } | |
12880 | } | |
12881 | if (f != NULL) | |
12882 | val += stretch; | |
12883 | } | |
12884 | ||
12885 | addr = fragp->fr_address + fragp->fr_fix; | |
12886 | ||
12887 | /* The base address rules are complicated. The base address of | |
12888 | a branch is the following instruction. The base address of a | |
12889 | PC relative load or add is the instruction itself, but if it | |
12890 | is in a delay slot (in which case it can not be extended) use | |
12891 | the address of the instruction whose delay slot it is in. */ | |
12892 | if (type == 'p' || type == 'q') | |
12893 | { | |
12894 | addr += 2; | |
12895 | ||
12896 | /* If we are currently assuming that this frag should be | |
12897 | extended, then, the current address is two bytes | |
bdaaa2e1 | 12898 | higher. */ |
252b5132 RH |
12899 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
12900 | addr += 2; | |
12901 | ||
12902 | /* Ignore the low bit in the target, since it will be set | |
12903 | for a text label. */ | |
12904 | if ((val & 1) != 0) | |
12905 | --val; | |
12906 | } | |
12907 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12908 | addr -= 4; | |
12909 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12910 | addr -= 2; | |
12911 | ||
12912 | val -= addr & ~ ((1 << op->shift) - 1); | |
12913 | ||
12914 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
12915 | if (type == 'p' || type == 'q') | |
12916 | val /= 2; | |
12917 | ||
12918 | /* If any of the shifted bits are set, we must use an extended | |
12919 | opcode. If the address depends on the size of this | |
12920 | instruction, this can lead to a loop, so we arrange to always | |
12921 | use an extended opcode. We only check this when we are in | |
12922 | the main relaxation loop, when SEC is NULL. */ | |
12923 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
12924 | { | |
12925 | fragp->fr_subtype = | |
12926 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12927 | return 1; | |
12928 | } | |
12929 | ||
12930 | /* If we are about to mark a frag as extended because the value | |
12931 | is precisely maxtiny + 1, then there is a chance of an | |
12932 | infinite loop as in the following code: | |
12933 | la $4,foo | |
12934 | .skip 1020 | |
12935 | .align 2 | |
12936 | foo: | |
12937 | In this case when the la is extended, foo is 0x3fc bytes | |
12938 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
12939 | the la must be extended. To avoid this loop, we mark the | |
12940 | frag as extended if it was small, and is about to become | |
12941 | extended with a value of maxtiny + 1. */ | |
12942 | if (val == ((maxtiny + 1) << op->shift) | |
12943 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
12944 | && sec == NULL) | |
12945 | { | |
12946 | fragp->fr_subtype = | |
12947 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12948 | return 1; | |
12949 | } | |
12950 | } | |
12951 | else if (symsec != absolute_section && sec != NULL) | |
12952 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
12953 | ||
12954 | if ((val & ((1 << op->shift) - 1)) != 0 | |
12955 | || val < (mintiny << op->shift) | |
12956 | || val > (maxtiny << op->shift)) | |
12957 | return 1; | |
12958 | else | |
12959 | return 0; | |
12960 | } | |
12961 | ||
4a6a3df4 AO |
12962 | /* Compute the length of a branch sequence, and adjust the |
12963 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
12964 | worst-case length is computed, with UPDATE being used to indicate | |
12965 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
12966 | branch is to be computed. */ | |
12967 | static int | |
12968 | relaxed_branch_length (fragp, sec, update) | |
12969 | fragS *fragp; | |
12970 | asection *sec; | |
12971 | int update; | |
12972 | { | |
b34976b6 | 12973 | bfd_boolean toofar; |
4a6a3df4 AO |
12974 | int length; |
12975 | ||
12976 | if (fragp | |
12977 | && S_IS_DEFINED (fragp->fr_symbol) | |
12978 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
12979 | { | |
12980 | addressT addr; | |
12981 | offsetT val; | |
12982 | ||
12983 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
12984 | ||
12985 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
12986 | ||
12987 | val -= addr; | |
12988 | ||
12989 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
12990 | } | |
12991 | else if (fragp) | |
12992 | /* If the symbol is not defined or it's in a different segment, | |
12993 | assume the user knows what's going on and emit a short | |
12994 | branch. */ | |
b34976b6 | 12995 | toofar = FALSE; |
4a6a3df4 | 12996 | else |
b34976b6 | 12997 | toofar = TRUE; |
4a6a3df4 AO |
12998 | |
12999 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
13000 | fragp->fr_subtype | |
af6ae2ad | 13001 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
13002 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
13003 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
13004 | toofar); | |
13005 | ||
13006 | length = 4; | |
13007 | if (toofar) | |
13008 | { | |
13009 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
13010 | length += 8; | |
13011 | ||
13012 | if (mips_pic != NO_PIC) | |
13013 | { | |
13014 | /* Additional space for PIC loading of target address. */ | |
13015 | length += 8; | |
13016 | if (mips_opts.isa == ISA_MIPS1) | |
13017 | /* Additional space for $at-stabilizing nop. */ | |
13018 | length += 4; | |
13019 | } | |
13020 | ||
13021 | /* If branch is conditional. */ | |
13022 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
13023 | length += 8; | |
13024 | } | |
b34976b6 | 13025 | |
4a6a3df4 AO |
13026 | return length; |
13027 | } | |
13028 | ||
252b5132 RH |
13029 | /* Estimate the size of a frag before relaxing. Unless this is the |
13030 | mips16, we are not really relaxing here, and the final size is | |
13031 | encoded in the subtype information. For the mips16, we have to | |
13032 | decide whether we are using an extended opcode or not. */ | |
13033 | ||
252b5132 RH |
13034 | int |
13035 | md_estimate_size_before_relax (fragp, segtype) | |
13036 | fragS *fragp; | |
13037 | asection *segtype; | |
13038 | { | |
43841e91 | 13039 | int change = 0; |
b34976b6 | 13040 | bfd_boolean linkonce = FALSE; |
252b5132 | 13041 | |
4a6a3df4 AO |
13042 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13043 | { | |
13044 | ||
b34976b6 AM |
13045 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
13046 | ||
4a6a3df4 AO |
13047 | return fragp->fr_var; |
13048 | } | |
13049 | ||
252b5132 | 13050 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
13051 | /* We don't want to modify the EXTENDED bit here; it might get us |
13052 | into infinite loops. We change it only in mips_relax_frag(). */ | |
13053 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
13054 | |
13055 | if (mips_pic == NO_PIC) | |
13056 | { | |
13057 | change = nopic_need_relax (fragp->fr_symbol, 0); | |
13058 | } | |
13059 | else if (mips_pic == SVR4_PIC) | |
13060 | { | |
13061 | symbolS *sym; | |
13062 | asection *symsec; | |
13063 | ||
13064 | sym = fragp->fr_symbol; | |
13065 | ||
13066 | /* Handle the case of a symbol equated to another symbol. */ | |
e0890092 | 13067 | while (symbol_equated_reloc_p (sym)) |
252b5132 RH |
13068 | { |
13069 | symbolS *n; | |
13070 | ||
13071 | /* It's possible to get a loop here in a badly written | |
13072 | program. */ | |
49309057 | 13073 | n = symbol_get_value_expression (sym)->X_add_symbol; |
252b5132 RH |
13074 | if (n == sym) |
13075 | break; | |
13076 | sym = n; | |
13077 | } | |
13078 | ||
13079 | symsec = S_GET_SEGMENT (sym); | |
13080 | ||
8614eeee UC |
13081 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ |
13082 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
beae10d5 KH |
13083 | { |
13084 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
13085 | != 0) | |
b34976b6 | 13086 | linkonce = TRUE; |
beae10d5 KH |
13087 | |
13088 | /* The GNU toolchain uses an extension for ELF: a section | |
13089 | beginning with the magic string .gnu.linkonce is a linkonce | |
13090 | section. */ | |
13091 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
13092 | sizeof ".gnu.linkonce" - 1) == 0) | |
b34976b6 | 13093 | linkonce = TRUE; |
beae10d5 | 13094 | } |
8614eeee | 13095 | |
252b5132 RH |
13096 | /* This must duplicate the test in adjust_reloc_syms. */ |
13097 | change = (symsec != &bfd_und_section | |
13098 | && symsec != &bfd_abs_section | |
426b0403 | 13099 | && ! bfd_is_com_section (symsec) |
8614eeee | 13100 | && !linkonce |
426b0403 | 13101 | #ifdef OBJ_ELF |
ea4ff978 | 13102 | /* A global or weak symbol is treated as external. */ |
9151e8bf | 13103 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour |
b25a253c | 13104 | || (! S_IS_WEAK (sym) |
bad9ca53 TS |
13105 | && (! S_IS_EXTERNAL (sym) |
13106 | || mips_pic == EMBEDDED_PIC))) | |
426b0403 AM |
13107 | #endif |
13108 | ); | |
252b5132 RH |
13109 | } |
13110 | else | |
13111 | abort (); | |
13112 | ||
13113 | if (change) | |
13114 | { | |
13115 | /* Record the offset to the first reloc in the fr_opcode field. | |
13116 | This lets md_convert_frag and tc_gen_reloc know that the code | |
13117 | must be expanded. */ | |
13118 | fragp->fr_opcode = (fragp->fr_literal | |
13119 | + fragp->fr_fix | |
13120 | - RELAX_OLD (fragp->fr_subtype) | |
13121 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
13122 | /* FIXME: This really needs as_warn_where. */ | |
13123 | if (RELAX_WARN (fragp->fr_subtype)) | |
9a41af64 TS |
13124 | as_warn (_("AT used after \".set noat\" or macro used after " |
13125 | "\".set nomacro\"")); | |
13126 | ||
13127 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
252b5132 RH |
13128 | } |
13129 | ||
9a41af64 | 13130 | return 0; |
252b5132 RH |
13131 | } |
13132 | ||
13133 | /* This is called to see whether a reloc against a defined symbol | |
13134 | should be converted into a reloc against a section. Don't adjust | |
13135 | MIPS16 jump relocations, so we don't have to worry about the format | |
13136 | of the offset in the .o file. Don't adjust relocations against | |
13137 | mips16 symbols, so that the linker can find them if it needs to set | |
13138 | up a stub. */ | |
13139 | ||
13140 | int | |
13141 | mips_fix_adjustable (fixp) | |
13142 | fixS *fixp; | |
13143 | { | |
13144 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
13145 | return 0; | |
a161fe53 | 13146 | |
252b5132 RH |
13147 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
13148 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13149 | return 0; | |
a161fe53 | 13150 | |
252b5132 RH |
13151 | if (fixp->fx_addsy == NULL) |
13152 | return 1; | |
a161fe53 | 13153 | |
252b5132 RH |
13154 | #ifdef OBJ_ELF |
13155 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
13156 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
13157 | && fixp->fx_subsy == NULL) | |
13158 | return 0; | |
13159 | #endif | |
a161fe53 | 13160 | |
252b5132 RH |
13161 | return 1; |
13162 | } | |
13163 | ||
13164 | /* Translate internal representation of relocation info to BFD target | |
13165 | format. */ | |
13166 | ||
13167 | arelent ** | |
13168 | tc_gen_reloc (section, fixp) | |
43841e91 | 13169 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
13170 | fixS *fixp; |
13171 | { | |
13172 | static arelent *retval[4]; | |
13173 | arelent *reloc; | |
13174 | bfd_reloc_code_real_type code; | |
13175 | ||
13176 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); | |
13177 | retval[1] = NULL; | |
13178 | ||
49309057 ILT |
13179 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13180 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13181 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
13182 | ||
13183 | if (mips_pic == EMBEDDED_PIC | |
13184 | && SWITCH_TABLE (fixp)) | |
13185 | { | |
13186 | /* For a switch table entry we use a special reloc. The addend | |
13187 | is actually the difference between the reloc address and the | |
13188 | subtrahend. */ | |
13189 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
13190 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) | |
13191 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); | |
13192 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
13193 | } | |
13194 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) | |
13195 | { | |
4514d474 CD |
13196 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
13197 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 13198 | else |
4514d474 CD |
13199 | { |
13200 | /* We use a special addend for an internal RELLO reloc. */ | |
13201 | if (symbol_section_p (fixp->fx_addsy)) | |
13202 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
13203 | else | |
13204 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
13205 | } | |
252b5132 RH |
13206 | } |
13207 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
13208 | { | |
13209 | assert (fixp->fx_next != NULL | |
13210 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
4514d474 CD |
13211 | |
13212 | /* The reloc is relative to the RELLO; adjust the addend | |
252b5132 | 13213 | accordingly. */ |
4514d474 CD |
13214 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
13215 | reloc->addend = fixp->fx_next->fx_addnumber; | |
252b5132 | 13216 | else |
4514d474 CD |
13217 | { |
13218 | /* We use a special addend for an internal RELHI reloc. */ | |
13219 | if (symbol_section_p (fixp->fx_addsy)) | |
13220 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
13221 | + fixp->fx_next->fx_where | |
13222 | - S_GET_VALUE (fixp->fx_subsy)); | |
13223 | else | |
13224 | reloc->addend = (fixp->fx_addnumber | |
13225 | + fixp->fx_next->fx_frag->fr_address | |
13226 | + fixp->fx_next->fx_where); | |
13227 | } | |
252b5132 | 13228 | } |
4514d474 CD |
13229 | else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour) |
13230 | reloc->addend = fixp->fx_addnumber; | |
252b5132 RH |
13231 | else |
13232 | { | |
13233 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) | |
13234 | /* A gruesome hack which is a result of the gruesome gas reloc | |
13235 | handling. */ | |
13236 | reloc->addend = reloc->address; | |
13237 | else | |
13238 | reloc->addend = -reloc->address; | |
13239 | } | |
13240 | ||
13241 | /* If this is a variant frag, we may need to adjust the existing | |
13242 | reloc and generate a new one. */ | |
13243 | if (fixp->fx_frag->fr_opcode != NULL | |
ed6fb7bd SC |
13244 | && ((fixp->fx_r_type == BFD_RELOC_GPREL16 |
13245 | && ! HAVE_NEWABI) | |
252b5132 RH |
13246 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 |
13247 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 | |
13248 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
13249 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
13250 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
6478892d | 13251 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16) |
ed6fb7bd | 13252 | ) |
252b5132 RH |
13253 | { |
13254 | arelent *reloc2; | |
13255 | ||
13256 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); | |
13257 | ||
13258 | /* If this is not the last reloc in this frag, then we have two | |
13259 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a | |
13260 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
13261 | the second one handle all of them. */ | |
13262 | if (fixp->fx_next != NULL | |
13263 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
13264 | { | |
cdf6fd85 TS |
13265 | assert ((fixp->fx_r_type == BFD_RELOC_GPREL16 |
13266 | && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16) | |
252b5132 RH |
13267 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 |
13268 | && (fixp->fx_next->fx_r_type | |
13269 | == BFD_RELOC_MIPS_GOT_LO16)) | |
13270 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
13271 | && (fixp->fx_next->fx_r_type | |
13272 | == BFD_RELOC_MIPS_CALL_LO16))); | |
13273 | retval[0] = NULL; | |
13274 | return retval; | |
13275 | } | |
13276 | ||
13277 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
13278 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
13279 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
13280 | retval[2] = NULL; | |
49309057 ILT |
13281 | reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13282 | *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13283 | reloc2->address = (reloc->address |
13284 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
13285 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
13286 | reloc2->addend = fixp->fx_addnumber; | |
13287 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
13288 | assert (reloc2->howto != NULL); | |
13289 | ||
13290 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
13291 | { | |
13292 | arelent *reloc3; | |
13293 | ||
13294 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
13295 | retval[3] = NULL; | |
13296 | *reloc3 = *reloc2; | |
13297 | reloc3->address += 4; | |
13298 | } | |
13299 | ||
13300 | if (mips_pic == NO_PIC) | |
13301 | { | |
cdf6fd85 | 13302 | assert (fixp->fx_r_type == BFD_RELOC_GPREL16); |
252b5132 RH |
13303 | fixp->fx_r_type = BFD_RELOC_HI16_S; |
13304 | } | |
13305 | else if (mips_pic == SVR4_PIC) | |
13306 | { | |
13307 | switch (fixp->fx_r_type) | |
13308 | { | |
13309 | default: | |
13310 | abort (); | |
13311 | case BFD_RELOC_MIPS_GOT16: | |
13312 | break; | |
252b5132 RH |
13313 | case BFD_RELOC_MIPS_GOT_LO16: |
13314 | case BFD_RELOC_MIPS_CALL_LO16: | |
13315 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
13316 | break; | |
ed6fb7bd SC |
13317 | case BFD_RELOC_MIPS_CALL16: |
13318 | if (HAVE_NEWABI) | |
13319 | { | |
13320 | /* BFD_RELOC_MIPS_GOT16;*/ | |
13321 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT_PAGE; | |
13322 | reloc2->howto = bfd_reloc_type_lookup | |
13323 | (stdoutput, BFD_RELOC_MIPS_GOT_OFST); | |
13324 | } | |
13325 | else | |
13326 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
13327 | break; | |
252b5132 RH |
13328 | } |
13329 | } | |
13330 | else | |
13331 | abort (); | |
ed6fb7bd SC |
13332 | |
13333 | /* newabi uses R_MIPS_GOT_DISP for local symbols */ | |
6b70243f | 13334 | if (HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16) |
ed6fb7bd SC |
13335 | { |
13336 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT_DISP; | |
13337 | retval[1] = NULL; | |
13338 | } | |
252b5132 RH |
13339 | } |
13340 | ||
438c16b8 TS |
13341 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
13342 | entry to be used in the relocation's section offset. */ | |
13343 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
13344 | { |
13345 | reloc->address = reloc->addend; | |
13346 | reloc->addend = 0; | |
13347 | } | |
13348 | ||
13349 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that | |
13350 | fixup_segment converted a non-PC relative reloc into a PC | |
13351 | relative reloc. In such a case, we need to convert the reloc | |
13352 | code. */ | |
13353 | code = fixp->fx_r_type; | |
13354 | if (fixp->fx_pcrel) | |
13355 | { | |
13356 | switch (code) | |
13357 | { | |
13358 | case BFD_RELOC_8: | |
13359 | code = BFD_RELOC_8_PCREL; | |
13360 | break; | |
13361 | case BFD_RELOC_16: | |
13362 | code = BFD_RELOC_16_PCREL; | |
13363 | break; | |
13364 | case BFD_RELOC_32: | |
13365 | code = BFD_RELOC_32_PCREL; | |
13366 | break; | |
13367 | case BFD_RELOC_64: | |
13368 | code = BFD_RELOC_64_PCREL; | |
13369 | break; | |
13370 | case BFD_RELOC_8_PCREL: | |
13371 | case BFD_RELOC_16_PCREL: | |
13372 | case BFD_RELOC_32_PCREL: | |
13373 | case BFD_RELOC_64_PCREL: | |
13374 | case BFD_RELOC_16_PCREL_S2: | |
13375 | case BFD_RELOC_PCREL_HI16_S: | |
13376 | case BFD_RELOC_PCREL_LO16: | |
13377 | break; | |
13378 | default: | |
13379 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13380 | _("Cannot make %s relocation PC relative"), | |
13381 | bfd_get_reloc_code_name (code)); | |
13382 | } | |
13383 | } | |
13384 | ||
add55e1f RS |
13385 | #ifdef OBJ_ELF |
13386 | /* md_apply_fix3 has a double-subtraction hack to get | |
13387 | bfd_install_relocation to behave nicely. GPREL relocations are | |
13388 | handled correctly without this hack, so undo it here. We can't | |
13389 | stop md_apply_fix3 from subtracting twice in the first place since | |
13390 | the fake addend is required for variant frags above. */ | |
13391 | if (fixp->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour | |
98605598 | 13392 | && (code == BFD_RELOC_GPREL16 || code == BFD_RELOC_MIPS16_GPREL) |
add55e1f RS |
13393 | && reloc->addend != 0 |
13394 | && mips_need_elf_addend_fixup (fixp)) | |
13395 | reloc->addend += S_GET_VALUE (fixp->fx_addsy); | |
13396 | #endif | |
13397 | ||
252b5132 RH |
13398 | /* To support a PC relative reloc when generating embedded PIC code |
13399 | for ECOFF, we use a Cygnus extension. We check for that here to | |
13400 | make sure that we don't let such a reloc escape normally. */ | |
bb2d6cd7 GK |
13401 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
13402 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 RH |
13403 | && code == BFD_RELOC_16_PCREL_S2 |
13404 | && mips_pic != EMBEDDED_PIC) | |
13405 | reloc->howto = NULL; | |
13406 | else | |
13407 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
13408 | ||
13409 | if (reloc->howto == NULL) | |
13410 | { | |
13411 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13412 | _("Can not represent %s relocation in this object file format"), | |
13413 | bfd_get_reloc_code_name (code)); | |
13414 | retval[0] = NULL; | |
13415 | } | |
13416 | ||
13417 | return retval; | |
13418 | } | |
13419 | ||
13420 | /* Relax a machine dependent frag. This returns the amount by which | |
13421 | the current size of the frag should change. */ | |
13422 | ||
13423 | int | |
4a6a3df4 AO |
13424 | mips_relax_frag (sec, fragp, stretch) |
13425 | asection *sec; | |
252b5132 RH |
13426 | fragS *fragp; |
13427 | long stretch; | |
13428 | { | |
4a6a3df4 AO |
13429 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13430 | { | |
13431 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
13432 | |
13433 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
13434 | |
13435 | return fragp->fr_var - old_var; | |
13436 | } | |
13437 | ||
252b5132 RH |
13438 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
13439 | return 0; | |
13440 | ||
c4e7957c | 13441 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
13442 | { |
13443 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13444 | return 0; | |
13445 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
13446 | return 2; | |
13447 | } | |
13448 | else | |
13449 | { | |
13450 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13451 | return 0; | |
13452 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
13453 | return -2; | |
13454 | } | |
13455 | ||
13456 | return 0; | |
13457 | } | |
13458 | ||
13459 | /* Convert a machine dependent frag. */ | |
13460 | ||
13461 | void | |
13462 | md_convert_frag (abfd, asec, fragp) | |
43841e91 | 13463 | bfd *abfd ATTRIBUTE_UNUSED; |
252b5132 RH |
13464 | segT asec; |
13465 | fragS *fragp; | |
13466 | { | |
13467 | int old, new; | |
13468 | char *fixptr; | |
13469 | ||
4a6a3df4 AO |
13470 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13471 | { | |
13472 | bfd_byte *buf; | |
13473 | unsigned long insn; | |
13474 | expressionS exp; | |
13475 | fixS *fixp; | |
b34976b6 | 13476 | |
4a6a3df4 AO |
13477 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
13478 | ||
13479 | if (target_big_endian) | |
13480 | insn = bfd_getb32 (buf); | |
13481 | else | |
13482 | insn = bfd_getl32 (buf); | |
b34976b6 | 13483 | |
4a6a3df4 AO |
13484 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
13485 | { | |
13486 | /* We generate a fixup instead of applying it right now | |
13487 | because, if there are linker relaxations, we're going to | |
13488 | need the relocations. */ | |
13489 | exp.X_op = O_symbol; | |
13490 | exp.X_add_symbol = fragp->fr_symbol; | |
13491 | exp.X_add_number = fragp->fr_offset; | |
13492 | ||
13493 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13494 | 4, &exp, 1, | |
af6ae2ad | 13495 | BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
13496 | fixp->fx_file = fragp->fr_file; |
13497 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13498 | |
4a6a3df4 AO |
13499 | md_number_to_chars ((char *)buf, insn, 4); |
13500 | buf += 4; | |
13501 | } | |
13502 | else | |
13503 | { | |
13504 | int i; | |
13505 | ||
13506 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13507 | _("relaxed out-of-range branch into a jump")); | |
13508 | ||
13509 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
13510 | goto uncond; | |
13511 | ||
13512 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13513 | { | |
13514 | /* Reverse the branch. */ | |
13515 | switch ((insn >> 28) & 0xf) | |
13516 | { | |
13517 | case 4: | |
13518 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
13519 | have the condition reversed by tweaking a single | |
13520 | bit, and their opcodes all have 0x4???????. */ | |
13521 | assert ((insn & 0xf1000000) == 0x41000000); | |
13522 | insn ^= 0x00010000; | |
13523 | break; | |
13524 | ||
13525 | case 0: | |
13526 | /* bltz 0x04000000 bgez 0x04010000 | |
13527 | bltzal 0x04100000 bgezal 0x04110000 */ | |
13528 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
13529 | insn ^= 0x00010000; | |
13530 | break; | |
b34976b6 | 13531 | |
4a6a3df4 AO |
13532 | case 1: |
13533 | /* beq 0x10000000 bne 0x14000000 | |
13534 | blez 0x18000000 bgtz 0x1c000000 */ | |
13535 | insn ^= 0x04000000; | |
13536 | break; | |
13537 | ||
13538 | default: | |
13539 | abort (); | |
13540 | } | |
13541 | } | |
13542 | ||
13543 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13544 | { | |
13545 | /* Clear the and-link bit. */ | |
13546 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13547 | ||
13548 | /* bltzal 0x04100000 bgezal 0x04110000 | |
13549 | bltzall 0x04120000 bgezall 0x04130000 */ | |
13550 | insn &= ~0x00100000; | |
13551 | } | |
13552 | ||
13553 | /* Branch over the branch (if the branch was likely) or the | |
13554 | full jump (not likely case). Compute the offset from the | |
13555 | current instruction to branch to. */ | |
13556 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13557 | i = 16; | |
13558 | else | |
13559 | { | |
13560 | /* How many bytes in instructions we've already emitted? */ | |
13561 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13562 | /* How many bytes in instructions from here to the end? */ | |
13563 | i = fragp->fr_var - i; | |
13564 | } | |
13565 | /* Convert to instruction count. */ | |
13566 | i >>= 2; | |
13567 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13568 | i--; |
4a6a3df4 AO |
13569 | insn |= i; |
13570 | /* Branch over the jump. */ | |
13571 | md_number_to_chars ((char *)buf, insn, 4); | |
13572 | buf += 4; | |
13573 | ||
13574 | /* Nop */ | |
13575 | md_number_to_chars ((char*)buf, 0, 4); | |
13576 | buf += 4; | |
13577 | ||
13578 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13579 | { | |
13580 | /* beql $0, $0, 2f */ | |
13581 | insn = 0x50000000; | |
13582 | /* Compute the PC offset from the current instruction to | |
13583 | the end of the variable frag. */ | |
13584 | /* How many bytes in instructions we've already emitted? */ | |
13585 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13586 | /* How many bytes in instructions from here to the end? */ | |
13587 | i = fragp->fr_var - i; | |
13588 | /* Convert to instruction count. */ | |
13589 | i >>= 2; | |
13590 | /* Don't decrement i, because we want to branch over the | |
13591 | delay slot. */ | |
13592 | ||
13593 | insn |= i; | |
13594 | md_number_to_chars ((char *)buf, insn, 4); | |
13595 | buf += 4; | |
13596 | ||
13597 | md_number_to_chars ((char *)buf, 0, 4); | |
13598 | buf += 4; | |
13599 | } | |
13600 | ||
13601 | uncond: | |
13602 | if (mips_pic == NO_PIC) | |
13603 | { | |
13604 | /* j or jal. */ | |
13605 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13606 | ? 0x0c000000 : 0x08000000); | |
13607 | exp.X_op = O_symbol; | |
13608 | exp.X_add_symbol = fragp->fr_symbol; | |
13609 | exp.X_add_number = fragp->fr_offset; | |
13610 | ||
13611 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13612 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
13613 | fixp->fx_file = fragp->fr_file; | |
13614 | fixp->fx_line = fragp->fr_line; | |
13615 | ||
13616 | md_number_to_chars ((char*)buf, insn, 4); | |
13617 | buf += 4; | |
13618 | } | |
13619 | else | |
13620 | { | |
13621 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13622 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13623 | exp.X_op = O_symbol; | |
13624 | exp.X_add_symbol = fragp->fr_symbol; | |
13625 | exp.X_add_number = fragp->fr_offset; | |
13626 | ||
13627 | if (fragp->fr_offset) | |
13628 | { | |
13629 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13630 | exp.X_add_number = 0; | |
13631 | } | |
13632 | ||
13633 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13634 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
13635 | fixp->fx_file = fragp->fr_file; | |
13636 | fixp->fx_line = fragp->fr_line; | |
13637 | ||
13638 | md_number_to_chars ((char*)buf, insn, 4); | |
13639 | buf += 4; | |
b34976b6 | 13640 | |
4a6a3df4 AO |
13641 | if (mips_opts.isa == ISA_MIPS1) |
13642 | { | |
13643 | /* nop */ | |
13644 | md_number_to_chars ((char*)buf, 0, 4); | |
13645 | buf += 4; | |
13646 | } | |
13647 | ||
13648 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13649 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13650 | ||
13651 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13652 | 4, &exp, 0, BFD_RELOC_LO16); | |
13653 | fixp->fx_file = fragp->fr_file; | |
13654 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13655 | |
4a6a3df4 AO |
13656 | md_number_to_chars ((char*)buf, insn, 4); |
13657 | buf += 4; | |
13658 | ||
13659 | /* j(al)r $at. */ | |
13660 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13661 | insn = 0x0020f809; | |
13662 | else | |
13663 | insn = 0x00200008; | |
13664 | ||
13665 | md_number_to_chars ((char*)buf, insn, 4); | |
13666 | buf += 4; | |
13667 | } | |
13668 | } | |
13669 | ||
13670 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13671 | + fragp->fr_fix + fragp->fr_var); | |
13672 | ||
13673 | fragp->fr_fix += fragp->fr_var; | |
13674 | ||
13675 | return; | |
13676 | } | |
13677 | ||
252b5132 RH |
13678 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13679 | { | |
13680 | int type; | |
13681 | register const struct mips16_immed_operand *op; | |
b34976b6 | 13682 | bfd_boolean small, ext; |
252b5132 RH |
13683 | offsetT val; |
13684 | bfd_byte *buf; | |
13685 | unsigned long insn; | |
b34976b6 | 13686 | bfd_boolean use_extend; |
252b5132 RH |
13687 | unsigned short extend; |
13688 | ||
13689 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13690 | op = mips16_immed_operands; | |
13691 | while (op->type != type) | |
13692 | ++op; | |
13693 | ||
13694 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13695 | { | |
b34976b6 AM |
13696 | small = FALSE; |
13697 | ext = TRUE; | |
252b5132 RH |
13698 | } |
13699 | else | |
13700 | { | |
b34976b6 AM |
13701 | small = TRUE; |
13702 | ext = FALSE; | |
252b5132 RH |
13703 | } |
13704 | ||
6386f3a7 | 13705 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13706 | val = S_GET_VALUE (fragp->fr_symbol); |
13707 | if (op->pcrel) | |
13708 | { | |
13709 | addressT addr; | |
13710 | ||
13711 | addr = fragp->fr_address + fragp->fr_fix; | |
13712 | ||
13713 | /* The rules for the base address of a PC relative reloc are | |
13714 | complicated; see mips16_extended_frag. */ | |
13715 | if (type == 'p' || type == 'q') | |
13716 | { | |
13717 | addr += 2; | |
13718 | if (ext) | |
13719 | addr += 2; | |
13720 | /* Ignore the low bit in the target, since it will be | |
13721 | set for a text label. */ | |
13722 | if ((val & 1) != 0) | |
13723 | --val; | |
13724 | } | |
13725 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13726 | addr -= 4; | |
13727 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13728 | addr -= 2; | |
13729 | ||
13730 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13731 | val -= addr; | |
13732 | ||
13733 | /* Make sure the section winds up with the alignment we have | |
13734 | assumed. */ | |
13735 | if (op->shift > 0) | |
13736 | record_alignment (asec, op->shift); | |
13737 | } | |
13738 | ||
13739 | if (ext | |
13740 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13741 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13742 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13743 | _("extended instruction in delay slot")); | |
13744 | ||
13745 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13746 | ||
13747 | if (target_big_endian) | |
13748 | insn = bfd_getb16 (buf); | |
13749 | else | |
13750 | insn = bfd_getl16 (buf); | |
13751 | ||
13752 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13753 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13754 | small, ext, &insn, &use_extend, &extend); | |
13755 | ||
13756 | if (use_extend) | |
13757 | { | |
874e8986 | 13758 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
13759 | fragp->fr_fix += 2; |
13760 | buf += 2; | |
13761 | } | |
13762 | ||
874e8986 | 13763 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
13764 | fragp->fr_fix += 2; |
13765 | buf += 2; | |
13766 | } | |
13767 | else | |
13768 | { | |
13769 | if (fragp->fr_opcode == NULL) | |
13770 | return; | |
13771 | ||
13772 | old = RELAX_OLD (fragp->fr_subtype); | |
13773 | new = RELAX_NEW (fragp->fr_subtype); | |
13774 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
13775 | ||
13776 | if (new > 0) | |
13777 | memcpy (fixptr - old, fixptr, new); | |
13778 | ||
13779 | fragp->fr_fix += new - old; | |
13780 | } | |
13781 | } | |
13782 | ||
13783 | #ifdef OBJ_ELF | |
13784 | ||
13785 | /* This function is called after the relocs have been generated. | |
13786 | We've been storing mips16 text labels as odd. Here we convert them | |
13787 | back to even for the convenience of the debugger. */ | |
13788 | ||
13789 | void | |
13790 | mips_frob_file_after_relocs () | |
13791 | { | |
13792 | asymbol **syms; | |
13793 | unsigned int count, i; | |
13794 | ||
13795 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13796 | return; | |
13797 | ||
13798 | syms = bfd_get_outsymbols (stdoutput); | |
13799 | count = bfd_get_symcount (stdoutput); | |
13800 | for (i = 0; i < count; i++, syms++) | |
13801 | { | |
13802 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13803 | && ((*syms)->value & 1) != 0) | |
13804 | { | |
13805 | (*syms)->value &= ~1; | |
13806 | /* If the symbol has an odd size, it was probably computed | |
13807 | incorrectly, so adjust that as well. */ | |
13808 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13809 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13810 | } | |
13811 | } | |
13812 | } | |
13813 | ||
13814 | #endif | |
13815 | ||
13816 | /* This function is called whenever a label is defined. It is used | |
13817 | when handling branch delays; if a branch has a label, we assume we | |
13818 | can not move it. */ | |
13819 | ||
13820 | void | |
13821 | mips_define_label (sym) | |
13822 | symbolS *sym; | |
13823 | { | |
13824 | struct insn_label_list *l; | |
13825 | ||
13826 | if (free_insn_labels == NULL) | |
13827 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13828 | else | |
13829 | { | |
13830 | l = free_insn_labels; | |
13831 | free_insn_labels = l->next; | |
13832 | } | |
13833 | ||
13834 | l->label = sym; | |
13835 | l->next = insn_labels; | |
13836 | insn_labels = l; | |
13837 | } | |
13838 | \f | |
13839 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13840 | ||
13841 | /* Some special processing for a MIPS ELF file. */ | |
13842 | ||
13843 | void | |
13844 | mips_elf_final_processing () | |
13845 | { | |
13846 | /* Write out the register information. */ | |
316f5878 | 13847 | if (mips_abi != N64_ABI) |
252b5132 RH |
13848 | { |
13849 | Elf32_RegInfo s; | |
13850 | ||
13851 | s.ri_gprmask = mips_gprmask; | |
13852 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13853 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13854 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13855 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13856 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13857 | ||
13858 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13859 | ((Elf32_External_RegInfo *) | |
13860 | mips_regmask_frag)); | |
13861 | } | |
13862 | else | |
13863 | { | |
13864 | Elf64_Internal_RegInfo s; | |
13865 | ||
13866 | s.ri_gprmask = mips_gprmask; | |
13867 | s.ri_pad = 0; | |
13868 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13869 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13870 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13871 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13872 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13873 | ||
13874 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13875 | ((Elf64_External_RegInfo *) | |
13876 | mips_regmask_frag)); | |
13877 | } | |
13878 | ||
13879 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13880 | sort of BFD interface for this. */ | |
13881 | if (mips_any_noreorder) | |
13882 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13883 | if (mips_pic != NO_PIC) | |
13884 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; | |
13885 | ||
98d3f06f | 13886 | /* Set MIPS ELF flags for ASEs. */ |
a4672219 TS |
13887 | if (file_ase_mips16) |
13888 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13889 | #if 0 /* XXX FIXME */ |
13890 | if (file_ase_mips3d) | |
13891 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13892 | #endif | |
deec1734 CD |
13893 | if (file_ase_mdmx) |
13894 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13895 | |
bdaaa2e1 | 13896 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13897 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13898 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13899 | else if (mips_abi == O64_ABI) |
252b5132 | 13900 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13901 | else if (mips_abi == EABI_ABI) |
252b5132 | 13902 | { |
316f5878 | 13903 | if (!file_mips_gp32) |
252b5132 RH |
13904 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
13905 | else | |
13906 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13907 | } | |
316f5878 | 13908 | else if (mips_abi == N32_ABI) |
be00bddd TS |
13909 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13910 | ||
c9914766 | 13911 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13912 | |
13913 | if (mips_32bitmode) | |
13914 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13915 | } | |
13916 | ||
13917 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13918 | \f | |
beae10d5 KH |
13919 | typedef struct proc { |
13920 | symbolS *isym; | |
13921 | unsigned long reg_mask; | |
13922 | unsigned long reg_offset; | |
13923 | unsigned long fpreg_mask; | |
13924 | unsigned long fpreg_offset; | |
13925 | unsigned long frame_offset; | |
13926 | unsigned long frame_reg; | |
13927 | unsigned long pc_reg; | |
13928 | } procS; | |
252b5132 RH |
13929 | |
13930 | static procS cur_proc; | |
13931 | static procS *cur_proc_ptr; | |
13932 | static int numprocs; | |
13933 | ||
0a9ef439 | 13934 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13935 | |
0a9ef439 RH |
13936 | void |
13937 | mips_handle_align (fragp) | |
13938 | fragS *fragp; | |
a19d8eb0 | 13939 | { |
0a9ef439 RH |
13940 | if (fragp->fr_type != rs_align_code) |
13941 | return; | |
13942 | ||
13943 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13944 | { |
13945 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13946 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13947 | ||
0a9ef439 RH |
13948 | int bytes; |
13949 | char *p; | |
a19d8eb0 | 13950 | |
0a9ef439 RH |
13951 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13952 | p = fragp->fr_literal + fragp->fr_fix; | |
13953 | ||
13954 | if (bytes & 1) | |
13955 | { | |
13956 | *p++ = 0; | |
f9419b05 | 13957 | fragp->fr_fix++; |
0a9ef439 RH |
13958 | } |
13959 | ||
13960 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
13961 | fragp->fr_var = 2; | |
a19d8eb0 CP |
13962 | } |
13963 | ||
0a9ef439 | 13964 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
13965 | } |
13966 | ||
252b5132 RH |
13967 | static void |
13968 | md_obj_begin () | |
13969 | { | |
13970 | } | |
13971 | ||
13972 | static void | |
13973 | md_obj_end () | |
13974 | { | |
13975 | /* check for premature end, nesting errors, etc */ | |
13976 | if (cur_proc_ptr) | |
9a41af64 | 13977 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
13978 | } |
13979 | ||
13980 | static long | |
13981 | get_number () | |
13982 | { | |
13983 | int negative = 0; | |
13984 | long val = 0; | |
13985 | ||
13986 | if (*input_line_pointer == '-') | |
13987 | { | |
13988 | ++input_line_pointer; | |
13989 | negative = 1; | |
13990 | } | |
3882b010 | 13991 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 13992 | as_bad (_("expected simple number")); |
252b5132 RH |
13993 | if (input_line_pointer[0] == '0') |
13994 | { | |
13995 | if (input_line_pointer[1] == 'x') | |
13996 | { | |
13997 | input_line_pointer += 2; | |
3882b010 | 13998 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
13999 | { |
14000 | val <<= 4; | |
14001 | val |= hex_value (*input_line_pointer++); | |
14002 | } | |
14003 | return negative ? -val : val; | |
14004 | } | |
14005 | else | |
14006 | { | |
14007 | ++input_line_pointer; | |
3882b010 | 14008 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14009 | { |
14010 | val <<= 3; | |
14011 | val |= *input_line_pointer++ - '0'; | |
14012 | } | |
14013 | return negative ? -val : val; | |
14014 | } | |
14015 | } | |
3882b010 | 14016 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14017 | { |
14018 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
14019 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 14020 | as_warn (_("invalid number")); |
252b5132 RH |
14021 | return -1; |
14022 | } | |
3882b010 | 14023 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14024 | { |
14025 | val *= 10; | |
14026 | val += *input_line_pointer++ - '0'; | |
14027 | } | |
14028 | return negative ? -val : val; | |
14029 | } | |
14030 | ||
14031 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
14032 | is an initial number which is the ECOFF file index. In the non-ECOFF |
14033 | case .file implies DWARF-2. */ | |
14034 | ||
14035 | static void | |
14036 | s_mips_file (x) | |
14037 | int x ATTRIBUTE_UNUSED; | |
14038 | { | |
ecb4347a DJ |
14039 | static int first_file_directive = 0; |
14040 | ||
c5dd6aab DJ |
14041 | if (ECOFF_DEBUGGING) |
14042 | { | |
14043 | get_number (); | |
14044 | s_app_file (0); | |
14045 | } | |
14046 | else | |
ecb4347a DJ |
14047 | { |
14048 | char *filename; | |
14049 | ||
14050 | filename = dwarf2_directive_file (0); | |
14051 | ||
14052 | /* Versions of GCC up to 3.1 start files with a ".file" | |
14053 | directive even for stabs output. Make sure that this | |
14054 | ".file" is handled. Note that you need a version of GCC | |
14055 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
14056 | if (filename != NULL && ! first_file_directive) | |
14057 | { | |
14058 | (void) new_logical_line (filename, -1); | |
14059 | s_app_file_string (filename); | |
14060 | } | |
14061 | first_file_directive = 1; | |
14062 | } | |
c5dd6aab DJ |
14063 | } |
14064 | ||
14065 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
14066 | |
14067 | static void | |
c5dd6aab | 14068 | s_mips_loc (x) |
43841e91 | 14069 | int x ATTRIBUTE_UNUSED; |
252b5132 | 14070 | { |
c5dd6aab DJ |
14071 | if (!ECOFF_DEBUGGING) |
14072 | dwarf2_directive_loc (0); | |
252b5132 RH |
14073 | } |
14074 | ||
252b5132 RH |
14075 | /* The .end directive. */ |
14076 | ||
14077 | static void | |
14078 | s_mips_end (x) | |
43841e91 | 14079 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
14080 | { |
14081 | symbolS *p; | |
14082 | int maybe_text; | |
14083 | ||
7a621144 DJ |
14084 | /* Following functions need their own .frame and .cprestore directives. */ |
14085 | mips_frame_reg_valid = 0; | |
14086 | mips_cprestore_valid = 0; | |
14087 | ||
252b5132 RH |
14088 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
14089 | { | |
14090 | p = get_symbol (); | |
14091 | demand_empty_rest_of_line (); | |
14092 | } | |
14093 | else | |
14094 | p = NULL; | |
14095 | ||
14096 | #ifdef BFD_ASSEMBLER | |
14097 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
14098 | maybe_text = 1; | |
14099 | else | |
14100 | maybe_text = 0; | |
14101 | #else | |
14102 | if (now_seg != data_section && now_seg != bss_section) | |
14103 | maybe_text = 1; | |
14104 | else | |
14105 | maybe_text = 0; | |
14106 | #endif | |
14107 | ||
14108 | if (!maybe_text) | |
14109 | as_warn (_(".end not in text section")); | |
14110 | ||
14111 | if (!cur_proc_ptr) | |
14112 | { | |
14113 | as_warn (_(".end directive without a preceding .ent directive.")); | |
14114 | demand_empty_rest_of_line (); | |
14115 | return; | |
14116 | } | |
14117 | ||
14118 | if (p != NULL) | |
14119 | { | |
14120 | assert (S_GET_NAME (p)); | |
14121 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
14122 | as_warn (_(".end symbol does not match .ent symbol.")); | |
ecb4347a DJ |
14123 | |
14124 | if (debug_type == DEBUG_STABS) | |
14125 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
14126 | S_GET_NAME (p)); | |
252b5132 RH |
14127 | } |
14128 | else | |
14129 | as_warn (_(".end directive missing or unknown symbol")); | |
14130 | ||
ecb4347a DJ |
14131 | #ifdef OBJ_ELF |
14132 | /* Generate a .pdr section. */ | |
14133 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
14134 | { | |
14135 | segT saved_seg = now_seg; | |
14136 | subsegT saved_subseg = now_subseg; | |
14137 | valueT dot; | |
14138 | expressionS exp; | |
14139 | char *fragp; | |
252b5132 | 14140 | |
ecb4347a | 14141 | dot = frag_now_fix (); |
252b5132 RH |
14142 | |
14143 | #ifdef md_flush_pending_output | |
ecb4347a | 14144 | md_flush_pending_output (); |
252b5132 RH |
14145 | #endif |
14146 | ||
ecb4347a DJ |
14147 | assert (pdr_seg); |
14148 | subseg_set (pdr_seg, 0); | |
252b5132 | 14149 | |
ecb4347a DJ |
14150 | /* Write the symbol. */ |
14151 | exp.X_op = O_symbol; | |
14152 | exp.X_add_symbol = p; | |
14153 | exp.X_add_number = 0; | |
14154 | emit_expr (&exp, 4); | |
252b5132 | 14155 | |
ecb4347a | 14156 | fragp = frag_more (7 * 4); |
252b5132 | 14157 | |
ecb4347a DJ |
14158 | md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4); |
14159 | md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4); | |
14160 | md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4); | |
14161 | md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4); | |
14162 | md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4); | |
14163 | md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4); | |
14164 | md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4); | |
252b5132 | 14165 | |
ecb4347a DJ |
14166 | subseg_set (saved_seg, saved_subseg); |
14167 | } | |
14168 | #endif /* OBJ_ELF */ | |
252b5132 RH |
14169 | |
14170 | cur_proc_ptr = NULL; | |
14171 | } | |
14172 | ||
14173 | /* The .aent and .ent directives. */ | |
14174 | ||
14175 | static void | |
14176 | s_mips_ent (aent) | |
14177 | int aent; | |
14178 | { | |
252b5132 RH |
14179 | symbolS *symbolP; |
14180 | int maybe_text; | |
14181 | ||
14182 | symbolP = get_symbol (); | |
14183 | if (*input_line_pointer == ',') | |
f9419b05 | 14184 | ++input_line_pointer; |
252b5132 | 14185 | SKIP_WHITESPACE (); |
3882b010 | 14186 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 14187 | || *input_line_pointer == '-') |
874e8986 | 14188 | get_number (); |
252b5132 RH |
14189 | |
14190 | #ifdef BFD_ASSEMBLER | |
14191 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
14192 | maybe_text = 1; | |
14193 | else | |
14194 | maybe_text = 0; | |
14195 | #else | |
14196 | if (now_seg != data_section && now_seg != bss_section) | |
14197 | maybe_text = 1; | |
14198 | else | |
14199 | maybe_text = 0; | |
14200 | #endif | |
14201 | ||
14202 | if (!maybe_text) | |
14203 | as_warn (_(".ent or .aent not in text section.")); | |
14204 | ||
14205 | if (!aent && cur_proc_ptr) | |
9a41af64 | 14206 | as_warn (_("missing .end")); |
252b5132 RH |
14207 | |
14208 | if (!aent) | |
14209 | { | |
7a621144 DJ |
14210 | /* This function needs its own .frame and .cprestore directives. */ |
14211 | mips_frame_reg_valid = 0; | |
14212 | mips_cprestore_valid = 0; | |
14213 | ||
252b5132 RH |
14214 | cur_proc_ptr = &cur_proc; |
14215 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
14216 | ||
14217 | cur_proc_ptr->isym = symbolP; | |
14218 | ||
49309057 | 14219 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 14220 | |
f9419b05 | 14221 | ++numprocs; |
ecb4347a DJ |
14222 | |
14223 | if (debug_type == DEBUG_STABS) | |
14224 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
14225 | S_GET_NAME (symbolP)); | |
252b5132 RH |
14226 | } |
14227 | ||
14228 | demand_empty_rest_of_line (); | |
14229 | } | |
14230 | ||
14231 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 14232 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 14233 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 14234 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
14235 | symbol table (in the mdebug section). */ |
14236 | ||
14237 | static void | |
14238 | s_mips_frame (ignore) | |
2b3c5a5d | 14239 | int ignore ATTRIBUTE_UNUSED; |
252b5132 | 14240 | { |
ecb4347a DJ |
14241 | #ifdef OBJ_ELF |
14242 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
14243 | { | |
14244 | long val; | |
252b5132 | 14245 | |
ecb4347a DJ |
14246 | if (cur_proc_ptr == (procS *) NULL) |
14247 | { | |
14248 | as_warn (_(".frame outside of .ent")); | |
14249 | demand_empty_rest_of_line (); | |
14250 | return; | |
14251 | } | |
252b5132 | 14252 | |
ecb4347a DJ |
14253 | cur_proc_ptr->frame_reg = tc_get_register (1); |
14254 | ||
14255 | SKIP_WHITESPACE (); | |
14256 | if (*input_line_pointer++ != ',' | |
14257 | || get_absolute_expression_and_terminator (&val) != ',') | |
14258 | { | |
14259 | as_warn (_("Bad .frame directive")); | |
14260 | --input_line_pointer; | |
14261 | demand_empty_rest_of_line (); | |
14262 | return; | |
14263 | } | |
252b5132 | 14264 | |
ecb4347a DJ |
14265 | cur_proc_ptr->frame_offset = val; |
14266 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 14267 | |
252b5132 | 14268 | demand_empty_rest_of_line (); |
252b5132 | 14269 | } |
ecb4347a DJ |
14270 | else |
14271 | #endif /* OBJ_ELF */ | |
14272 | s_ignore (ignore); | |
252b5132 RH |
14273 | } |
14274 | ||
bdaaa2e1 KH |
14275 | /* The .fmask and .mask directives. If the mdebug section is present |
14276 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 14277 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 14278 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
14279 | make reference to the ecoff symbol table (in the mdebug section). */ |
14280 | ||
14281 | static void | |
14282 | s_mips_mask (reg_type) | |
14283 | char reg_type; | |
14284 | { | |
ecb4347a DJ |
14285 | #ifdef OBJ_ELF |
14286 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 14287 | { |
ecb4347a | 14288 | long mask, off; |
252b5132 | 14289 | |
ecb4347a DJ |
14290 | if (cur_proc_ptr == (procS *) NULL) |
14291 | { | |
14292 | as_warn (_(".mask/.fmask outside of .ent")); | |
14293 | demand_empty_rest_of_line (); | |
14294 | return; | |
14295 | } | |
252b5132 | 14296 | |
ecb4347a DJ |
14297 | if (get_absolute_expression_and_terminator (&mask) != ',') |
14298 | { | |
14299 | as_warn (_("Bad .mask/.fmask directive")); | |
14300 | --input_line_pointer; | |
14301 | demand_empty_rest_of_line (); | |
14302 | return; | |
14303 | } | |
252b5132 | 14304 | |
ecb4347a DJ |
14305 | off = get_absolute_expression (); |
14306 | ||
14307 | if (reg_type == 'F') | |
14308 | { | |
14309 | cur_proc_ptr->fpreg_mask = mask; | |
14310 | cur_proc_ptr->fpreg_offset = off; | |
14311 | } | |
14312 | else | |
14313 | { | |
14314 | cur_proc_ptr->reg_mask = mask; | |
14315 | cur_proc_ptr->reg_offset = off; | |
14316 | } | |
14317 | ||
14318 | demand_empty_rest_of_line (); | |
252b5132 RH |
14319 | } |
14320 | else | |
ecb4347a DJ |
14321 | #endif /* OBJ_ELF */ |
14322 | s_ignore (reg_type); | |
252b5132 RH |
14323 | } |
14324 | ||
14325 | /* The .loc directive. */ | |
14326 | ||
14327 | #if 0 | |
14328 | static void | |
14329 | s_loc (x) | |
14330 | int x; | |
14331 | { | |
14332 | symbolS *symbolP; | |
14333 | int lineno; | |
14334 | int addroff; | |
14335 | ||
14336 | assert (now_seg == text_section); | |
14337 | ||
14338 | lineno = get_number (); | |
14339 | addroff = frag_now_fix (); | |
14340 | ||
14341 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
14342 | S_SET_TYPE (symbolP, N_SLINE); | |
14343 | S_SET_OTHER (symbolP, 0); | |
14344 | S_SET_DESC (symbolP, lineno); | |
14345 | symbolP->sy_segment = now_seg; | |
14346 | } | |
14347 | #endif | |
e7af610e | 14348 | |
316f5878 RS |
14349 | /* A table describing all the processors gas knows about. Names are |
14350 | matched in the order listed. | |
e7af610e | 14351 | |
316f5878 RS |
14352 | To ease comparison, please keep this table in the same order as |
14353 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
14354 | static const struct mips_cpu_info mips_cpu_info_table[] = |
14355 | { | |
316f5878 RS |
14356 | /* Entries for generic ISAs */ |
14357 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
14358 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
14359 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
14360 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
14361 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
14362 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
14363 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, | |
14364 | ||
14365 | /* MIPS I */ | |
14366 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
14367 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
14368 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
14369 | ||
14370 | /* MIPS II */ | |
14371 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
14372 | ||
14373 | /* MIPS III */ | |
14374 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
14375 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
14376 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
14377 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
14378 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
14379 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
14380 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
14381 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
14382 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
14383 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
14384 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
14385 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
14386 | ||
14387 | /* MIPS IV */ | |
14388 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
14389 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
14390 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
14391 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
14392 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
14393 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
14394 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
14395 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
14396 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
14397 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
14398 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
14399 | { "r7000", 0, ISA_MIPS4, CPU_R5000 }, | |
14400 | ||
14401 | /* MIPS 32 */ | |
14402 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32, }, | |
14403 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
14404 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 14405 | |
316f5878 RS |
14406 | /* MIPS 64 */ |
14407 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
14408 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
e7af610e | 14409 | |
c7a23324 | 14410 | /* Broadcom SB-1 CPU core */ |
316f5878 | 14411 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 14412 | |
316f5878 RS |
14413 | /* End marker */ |
14414 | { NULL, 0, 0, 0 } | |
14415 | }; | |
e7af610e | 14416 | |
84ea6cf2 | 14417 | |
316f5878 RS |
14418 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
14419 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 14420 | |
316f5878 | 14421 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 14422 | |
b34976b6 | 14423 | static bfd_boolean |
316f5878 RS |
14424 | mips_strict_matching_cpu_name_p (canonical, given) |
14425 | const char *canonical, *given; | |
14426 | { | |
14427 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
14428 | given++, canonical++; | |
14429 | ||
14430 | return ((*given == 0 && *canonical == 0) | |
14431 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
14432 | } | |
14433 | ||
14434 | ||
14435 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
14436 | CPU name. We've traditionally allowed a lot of variation here. | |
14437 | ||
14438 | Note: this function is shared between GCC and GAS. */ | |
14439 | ||
b34976b6 | 14440 | static bfd_boolean |
316f5878 RS |
14441 | mips_matching_cpu_name_p (canonical, given) |
14442 | const char *canonical, *given; | |
14443 | { | |
14444 | /* First see if the name matches exactly, or with a final "000" | |
14445 | turned into "k". */ | |
14446 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 14447 | return TRUE; |
316f5878 RS |
14448 | |
14449 | /* If not, try comparing based on numerical designation alone. | |
14450 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
14451 | if (TOLOWER (*given) == 'r') | |
14452 | given++; | |
14453 | if (!ISDIGIT (*given)) | |
b34976b6 | 14454 | return FALSE; |
316f5878 RS |
14455 | |
14456 | /* Skip over some well-known prefixes in the canonical name, | |
14457 | hoping to find a number there too. */ | |
14458 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
14459 | canonical += 2; | |
14460 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
14461 | canonical += 2; | |
14462 | else if (TOLOWER (canonical[0]) == 'r') | |
14463 | canonical += 1; | |
14464 | ||
14465 | return mips_strict_matching_cpu_name_p (canonical, given); | |
14466 | } | |
14467 | ||
14468 | ||
14469 | /* Parse an option that takes the name of a processor as its argument. | |
14470 | OPTION is the name of the option and CPU_STRING is the argument. | |
14471 | Return the corresponding processor enumeration if the CPU_STRING is | |
14472 | recognized, otherwise report an error and return null. | |
14473 | ||
14474 | A similar function exists in GCC. */ | |
e7af610e NC |
14475 | |
14476 | static const struct mips_cpu_info * | |
316f5878 RS |
14477 | mips_parse_cpu (option, cpu_string) |
14478 | const char *option, *cpu_string; | |
e7af610e | 14479 | { |
316f5878 | 14480 | const struct mips_cpu_info *p; |
e7af610e | 14481 | |
316f5878 RS |
14482 | /* 'from-abi' selects the most compatible architecture for the given |
14483 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
14484 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
14485 | version. Look first at the -mgp options, if given, otherwise base | |
14486 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 14487 | |
316f5878 RS |
14488 | Treat NO_ABI like the EABIs. One reason to do this is that the |
14489 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
14490 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
14491 | 'mips64', just as we did in the days before 'from-abi'. */ | |
14492 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
14493 | { | |
14494 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14495 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
14496 | ||
14497 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14498 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
14499 | ||
14500 | if (file_mips_gp32 >= 0) | |
14501 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
14502 | ||
14503 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
14504 | ? ISA_MIPS3 | |
14505 | : ISA_MIPS1); | |
14506 | } | |
14507 | ||
14508 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
14509 | if (strcasecmp (cpu_string, "default") == 0) | |
14510 | return 0; | |
14511 | ||
14512 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
14513 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
14514 | return p; | |
14515 | ||
14516 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
14517 | return 0; | |
e7af610e NC |
14518 | } |
14519 | ||
316f5878 RS |
14520 | /* Return the canonical processor information for ISA (a member of the |
14521 | ISA_MIPS* enumeration). */ | |
14522 | ||
e7af610e NC |
14523 | static const struct mips_cpu_info * |
14524 | mips_cpu_info_from_isa (isa) | |
14525 | int isa; | |
14526 | { | |
14527 | int i; | |
14528 | ||
14529 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14530 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 14531 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
14532 | return (&mips_cpu_info_table[i]); |
14533 | ||
e972090a | 14534 | return NULL; |
e7af610e | 14535 | } |
316f5878 RS |
14536 | \f |
14537 | static void | |
14538 | show (stream, string, col_p, first_p) | |
14539 | FILE *stream; | |
14540 | const char *string; | |
14541 | int *col_p; | |
14542 | int *first_p; | |
14543 | { | |
14544 | if (*first_p) | |
14545 | { | |
14546 | fprintf (stream, "%24s", ""); | |
14547 | *col_p = 24; | |
14548 | } | |
14549 | else | |
14550 | { | |
14551 | fprintf (stream, ", "); | |
14552 | *col_p += 2; | |
14553 | } | |
e7af610e | 14554 | |
316f5878 RS |
14555 | if (*col_p + strlen (string) > 72) |
14556 | { | |
14557 | fprintf (stream, "\n%24s", ""); | |
14558 | *col_p = 24; | |
14559 | } | |
14560 | ||
14561 | fprintf (stream, "%s", string); | |
14562 | *col_p += strlen (string); | |
14563 | ||
14564 | *first_p = 0; | |
14565 | } | |
14566 | ||
14567 | void | |
14568 | md_show_usage (stream) | |
14569 | FILE *stream; | |
e7af610e | 14570 | { |
316f5878 RS |
14571 | int column, first; |
14572 | size_t i; | |
14573 | ||
14574 | fprintf (stream, _("\ | |
14575 | MIPS options:\n\ | |
14576 | -membedded-pic generate embedded position independent code\n\ | |
14577 | -EB generate big endian output\n\ | |
14578 | -EL generate little endian output\n\ | |
14579 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
14580 | -G NUM allow referencing objects up to NUM bytes\n\ | |
14581 | implicitly with the gp register [default 8]\n")); | |
14582 | fprintf (stream, _("\ | |
14583 | -mips1 generate MIPS ISA I instructions\n\ | |
14584 | -mips2 generate MIPS ISA II instructions\n\ | |
14585 | -mips3 generate MIPS ISA III instructions\n\ | |
14586 | -mips4 generate MIPS ISA IV instructions\n\ | |
14587 | -mips5 generate MIPS ISA V instructions\n\ | |
14588 | -mips32 generate MIPS32 ISA instructions\n\ | |
14589 | -mips64 generate MIPS64 ISA instructions\n\ | |
14590 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); | |
14591 | ||
14592 | first = 1; | |
e7af610e NC |
14593 | |
14594 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14595 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14596 | show (stream, "from-abi", &column, &first); | |
14597 | fputc ('\n', stream); | |
e7af610e | 14598 | |
316f5878 RS |
14599 | fprintf (stream, _("\ |
14600 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14601 | -no-mCPU don't generate code specific to CPU.\n\ | |
14602 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14603 | ||
14604 | first = 1; | |
14605 | ||
14606 | show (stream, "3900", &column, &first); | |
14607 | show (stream, "4010", &column, &first); | |
14608 | show (stream, "4100", &column, &first); | |
14609 | show (stream, "4650", &column, &first); | |
14610 | fputc ('\n', stream); | |
14611 | ||
14612 | fprintf (stream, _("\ | |
14613 | -mips16 generate mips16 instructions\n\ | |
14614 | -no-mips16 do not generate mips16 instructions\n")); | |
14615 | fprintf (stream, _("\ | |
14616 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ | |
14617 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
14618 | -O0 remove unneeded NOPs, do not swap branches\n\ | |
14619 | -O remove unneeded NOPs and swap branches\n\ | |
14620 | -n warn about NOPs generated from macros\n\ | |
14621 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ | |
14622 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14623 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14624 | #ifdef OBJ_ELF | |
14625 | fprintf (stream, _("\ | |
14626 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14627 | -non_shared do not generate position independent code\n\ | |
14628 | -xgot assume a 32 bit GOT\n\ | |
14629 | -mabi=ABI create ABI conformant object file for:\n")); | |
14630 | ||
14631 | first = 1; | |
14632 | ||
14633 | show (stream, "32", &column, &first); | |
14634 | show (stream, "o64", &column, &first); | |
14635 | show (stream, "n32", &column, &first); | |
14636 | show (stream, "64", &column, &first); | |
14637 | show (stream, "eabi", &column, &first); | |
14638 | ||
14639 | fputc ('\n', stream); | |
14640 | ||
14641 | fprintf (stream, _("\ | |
14642 | -32 create o32 ABI object file (default)\n\ | |
14643 | -n32 create n32 ABI object file\n\ | |
14644 | -64 create 64 ABI object file\n")); | |
14645 | #endif | |
e7af610e | 14646 | } |
14e777e0 KB |
14647 | |
14648 | enum dwarf2_format | |
14649 | mips_dwarf2_format () | |
14650 | { | |
14651 | if (mips_abi == N64_ABI) | |
14652 | return dwarf2_format_64bit_irix; | |
14653 | else | |
14654 | return dwarf2_format_32bit; | |
14655 | } |