Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
c67a084a NC |
3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
4 | Free Software Foundation, Inc. | |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
741fe287 | 93 | #define ATREG 1 |
252b5132 RH |
94 | #define TREG 24 |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
741fe287 MR |
105 | #define AT mips_opts.at |
106 | ||
252b5132 RH |
107 | /* Allow override of standard little-endian ECOFF format. */ |
108 | ||
109 | #ifndef ECOFF_LITTLE_FORMAT | |
110 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
111 | #endif | |
112 | ||
113 | extern int target_big_endian; | |
114 | ||
252b5132 | 115 | /* The name of the readonly data section. */ |
4d0d148d | 116 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 117 | ? ".rdata" \ |
056350c6 NC |
118 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
119 | ? ".rdata" \ | |
252b5132 RH |
120 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
121 | ? ".rodata" \ | |
122 | : (abort (), "")) | |
123 | ||
a4e06468 RS |
124 | /* Ways in which an instruction can be "appended" to the output. */ |
125 | enum append_method { | |
126 | /* Just add it normally. */ | |
127 | APPEND_ADD, | |
128 | ||
129 | /* Add it normally and then add a nop. */ | |
130 | APPEND_ADD_WITH_NOP, | |
131 | ||
132 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
133 | APPEND_ADD_COMPACT, | |
134 | ||
135 | /* Insert the instruction before the last one. */ | |
136 | APPEND_SWAP | |
137 | }; | |
138 | ||
47e39b9d RS |
139 | /* Information about an instruction, including its format, operands |
140 | and fixups. */ | |
141 | struct mips_cl_insn | |
142 | { | |
143 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
144 | const struct mips_opcode *insn_mo; | |
145 | ||
146 | /* True if this is a mips16 instruction and if we want the extended | |
147 | form of INSN_MO. */ | |
148 | bfd_boolean use_extend; | |
149 | ||
150 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
151 | unsigned short extend; | |
152 | ||
153 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
154 | a copy of INSN_MO->match with the operands filled in. */ | |
155 | unsigned long insn_opcode; | |
156 | ||
157 | /* The frag that contains the instruction. */ | |
158 | struct frag *frag; | |
159 | ||
160 | /* The offset into FRAG of the first instruction byte. */ | |
161 | long where; | |
162 | ||
163 | /* The relocs associated with the instruction, if any. */ | |
164 | fixS *fixp[3]; | |
165 | ||
a38419a5 RS |
166 | /* True if this entry cannot be moved from its current position. */ |
167 | unsigned int fixed_p : 1; | |
47e39b9d | 168 | |
708587a4 | 169 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
170 | unsigned int noreorder_p : 1; |
171 | ||
2fa15973 RS |
172 | /* True for mips16 instructions that jump to an absolute address. */ |
173 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
174 | |
175 | /* True if this instruction is complete. */ | |
176 | unsigned int complete_p : 1; | |
47e39b9d RS |
177 | }; |
178 | ||
a325df1d TS |
179 | /* The ABI to use. */ |
180 | enum mips_abi_level | |
181 | { | |
182 | NO_ABI = 0, | |
183 | O32_ABI, | |
184 | O64_ABI, | |
185 | N32_ABI, | |
186 | N64_ABI, | |
187 | EABI_ABI | |
188 | }; | |
189 | ||
190 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 191 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 192 | |
143d77c5 EC |
193 | /* Whether or not we have code that can call pic code. */ |
194 | int mips_abicalls = FALSE; | |
195 | ||
aa6975fb ILT |
196 | /* Whether or not we have code which can be put into a shared |
197 | library. */ | |
198 | static bfd_boolean mips_in_shared = TRUE; | |
199 | ||
252b5132 RH |
200 | /* This is the set of options which may be modified by the .set |
201 | pseudo-op. We use a struct so that .set push and .set pop are more | |
202 | reliable. */ | |
203 | ||
e972090a NC |
204 | struct mips_set_options |
205 | { | |
252b5132 RH |
206 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
207 | if it has not been initialized. Changed by `.set mipsN', and the | |
208 | -mipsN command line option, and the default CPU. */ | |
209 | int isa; | |
1f25f5d3 CD |
210 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
211 | if they have not been initialized. Changed by `.set <asename>', by | |
212 | command line options, and based on the default architecture. */ | |
213 | int ase_mips3d; | |
deec1734 | 214 | int ase_mdmx; |
e16bfa71 | 215 | int ase_smartmips; |
74cd071d | 216 | int ase_dsp; |
8b082fb1 | 217 | int ase_dspr2; |
ef2e4d86 | 218 | int ase_mt; |
252b5132 RH |
219 | /* Whether we are assembling for the mips16 processor. 0 if we are |
220 | not, 1 if we are, and -1 if the value has not been initialized. | |
221 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
222 | -nomips16 command line options, and the default CPU. */ | |
223 | int mips16; | |
224 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
225 | reorder' and `.set noreorder'. */ | |
226 | int noreorder; | |
741fe287 MR |
227 | /* Non-zero if we should not permit the register designated "assembler |
228 | temporary" to be used in instructions. The value is the register | |
229 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
230 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
231 | unsigned int at; | |
252b5132 RH |
232 | /* Non-zero if we should warn when a macro instruction expands into |
233 | more than one machine instruction. Changed by `.set nomacro' and | |
234 | `.set macro'. */ | |
235 | int warn_about_macros; | |
236 | /* Non-zero if we should not move instructions. Changed by `.set | |
237 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
238 | int nomove; | |
239 | /* Non-zero if we should not optimize branches by moving the target | |
240 | of the branch into the delay slot. Actually, we don't perform | |
241 | this optimization anyhow. Changed by `.set bopt' and `.set | |
242 | nobopt'. */ | |
243 | int nobopt; | |
244 | /* Non-zero if we should not autoextend mips16 instructions. | |
245 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
246 | int noautoextend; | |
a325df1d TS |
247 | /* Restrict general purpose registers and floating point registers |
248 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
249 | is passed but can changed if the assembler code uses .set mipsN. */ | |
250 | int gp32; | |
251 | int fp32; | |
fef14a42 TS |
252 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
253 | command line option, and the default CPU. */ | |
254 | int arch; | |
aed1a261 RS |
255 | /* True if ".set sym32" is in effect. */ |
256 | bfd_boolean sym32; | |
037b32b9 AN |
257 | /* True if floating-point operations are not allowed. Changed by .set |
258 | softfloat or .set hardfloat, by command line options -msoft-float or | |
259 | -mhard-float. The default is false. */ | |
260 | bfd_boolean soft_float; | |
261 | ||
262 | /* True if only single-precision floating-point operations are allowed. | |
263 | Changed by .set singlefloat or .set doublefloat, command-line options | |
264 | -msingle-float or -mdouble-float. The default is false. */ | |
265 | bfd_boolean single_float; | |
252b5132 RH |
266 | }; |
267 | ||
037b32b9 AN |
268 | /* This is the struct we use to hold the current set of options. Note |
269 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
270 | -1 to indicate that they have not been initialized. */ | |
271 | ||
a325df1d | 272 | /* True if -mgp32 was passed. */ |
a8e8e863 | 273 | static int file_mips_gp32 = -1; |
a325df1d TS |
274 | |
275 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 276 | static int file_mips_fp32 = -1; |
a325df1d | 277 | |
037b32b9 AN |
278 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
279 | static int file_mips_soft_float = 0; | |
280 | ||
281 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
282 | static int file_mips_single_float = 0; | |
252b5132 | 283 | |
e972090a NC |
284 | static struct mips_set_options mips_opts = |
285 | { | |
037b32b9 AN |
286 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
287 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
288 | /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG, | |
289 | /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, | |
290 | /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, | |
291 | /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 292 | }; |
252b5132 RH |
293 | |
294 | /* These variables are filled in with the masks of registers used. | |
295 | The object format code reads them and puts them in the appropriate | |
296 | place. */ | |
297 | unsigned long mips_gprmask; | |
298 | unsigned long mips_cprmask[4]; | |
299 | ||
300 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 301 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 302 | |
738f4d98 | 303 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
304 | static int file_ase_mips16; |
305 | ||
3994f87e TS |
306 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
307 | || mips_opts.isa == ISA_MIPS32R2 \ | |
308 | || mips_opts.isa == ISA_MIPS64 \ | |
309 | || mips_opts.isa == ISA_MIPS64R2) | |
310 | ||
b12dd2e4 CF |
311 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
312 | #ifdef TE_IRIX | |
1180b5a4 | 313 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 314 | #else |
1180b5a4 RS |
315 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
316 | because there's no place for any addend, the only acceptable | |
317 | expression is a bare symbol. */ | |
318 | #define MIPS_JALR_HINT_P(EXPR) \ | |
319 | (!HAVE_IN_PLACE_ADDENDS \ | |
320 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
321 | #endif |
322 | ||
1f25f5d3 CD |
323 | /* True if -mips3d was passed or implied by arguments passed on the |
324 | command line (e.g., by -march). */ | |
325 | static int file_ase_mips3d; | |
326 | ||
deec1734 CD |
327 | /* True if -mdmx was passed or implied by arguments passed on the |
328 | command line (e.g., by -march). */ | |
329 | static int file_ase_mdmx; | |
330 | ||
e16bfa71 TS |
331 | /* True if -msmartmips was passed or implied by arguments passed on the |
332 | command line (e.g., by -march). */ | |
333 | static int file_ase_smartmips; | |
334 | ||
ad3fea08 TS |
335 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
336 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 337 | |
74cd071d CF |
338 | /* True if -mdsp was passed or implied by arguments passed on the |
339 | command line (e.g., by -march). */ | |
340 | static int file_ase_dsp; | |
341 | ||
ad3fea08 TS |
342 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
343 | || mips_opts.isa == ISA_MIPS64R2) | |
344 | ||
65263ce3 TS |
345 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
346 | ||
8b082fb1 TS |
347 | /* True if -mdspr2 was passed or implied by arguments passed on the |
348 | command line (e.g., by -march). */ | |
349 | static int file_ase_dspr2; | |
350 | ||
351 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
352 | || mips_opts.isa == ISA_MIPS64R2) | |
353 | ||
ef2e4d86 CF |
354 | /* True if -mmt was passed or implied by arguments passed on the |
355 | command line (e.g., by -march). */ | |
356 | static int file_ase_mt; | |
357 | ||
ad3fea08 TS |
358 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
359 | || mips_opts.isa == ISA_MIPS64R2) | |
360 | ||
ec68c924 | 361 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 362 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 363 | static const char *mips_arch_string; |
ec68c924 EC |
364 | |
365 | /* The argument of the -mtune= flag. The architecture for which we | |
366 | are optimizing. */ | |
367 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 368 | static const char *mips_tune_string; |
ec68c924 | 369 | |
316f5878 | 370 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
371 | static int mips_32bitmode = 0; |
372 | ||
316f5878 RS |
373 | /* True if the given ABI requires 32-bit registers. */ |
374 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
375 | ||
376 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
377 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
378 | ((ABI) == N32_ABI \ | |
379 | || (ABI) == N64_ABI \ | |
316f5878 RS |
380 | || (ABI) == O64_ABI) |
381 | ||
ad3fea08 | 382 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
383 | #define ISA_HAS_64BIT_REGS(ISA) \ |
384 | ((ISA) == ISA_MIPS3 \ | |
385 | || (ISA) == ISA_MIPS4 \ | |
386 | || (ISA) == ISA_MIPS5 \ | |
387 | || (ISA) == ISA_MIPS64 \ | |
388 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 389 | |
ad3fea08 TS |
390 | /* Return true if ISA supports 64 bit wide float registers. */ |
391 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
392 | ((ISA) == ISA_MIPS3 \ | |
393 | || (ISA) == ISA_MIPS4 \ | |
394 | || (ISA) == ISA_MIPS5 \ | |
395 | || (ISA) == ISA_MIPS32R2 \ | |
396 | || (ISA) == ISA_MIPS64 \ | |
397 | || (ISA) == ISA_MIPS64R2) | |
398 | ||
af7ee8bf CD |
399 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
400 | instructions. */ | |
707bfff6 TS |
401 | #define ISA_HAS_DROR(ISA) \ |
402 | ((ISA) == ISA_MIPS64R2) | |
af7ee8bf CD |
403 | |
404 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
405 | instructions. */ | |
707bfff6 TS |
406 | #define ISA_HAS_ROR(ISA) \ |
407 | ((ISA) == ISA_MIPS32R2 \ | |
408 | || (ISA) == ISA_MIPS64R2 \ | |
409 | || mips_opts.ase_smartmips) | |
410 | ||
7455baf8 TS |
411 | /* Return true if ISA supports single-precision floats in odd registers. */ |
412 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
413 | ((ISA) == ISA_MIPS32 \ | |
414 | || (ISA) == ISA_MIPS32R2 \ | |
415 | || (ISA) == ISA_MIPS64 \ | |
416 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 417 | |
ad3fea08 TS |
418 | /* Return true if ISA supports move to/from high part of a 64-bit |
419 | floating-point register. */ | |
420 | #define ISA_HAS_MXHC1(ISA) \ | |
421 | ((ISA) == ISA_MIPS32R2 \ | |
422 | || (ISA) == ISA_MIPS64R2) | |
423 | ||
e013f690 | 424 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 425 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 426 | |
e013f690 | 427 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 428 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 429 | |
ad3fea08 TS |
430 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
431 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 432 | |
316f5878 | 433 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 434 | |
316f5878 | 435 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 436 | |
3b91255e RS |
437 | /* True if relocations are stored in-place. */ |
438 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
439 | ||
aed1a261 RS |
440 | /* The ABI-derived address size. */ |
441 | #define HAVE_64BIT_ADDRESSES \ | |
442 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
443 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 444 | |
aed1a261 RS |
445 | /* The size of symbolic constants (i.e., expressions of the form |
446 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
447 | #define HAVE_32BIT_SYMBOLS \ | |
448 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
449 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 450 | |
b7c7d6c1 TS |
451 | /* Addresses are loaded in different ways, depending on the address size |
452 | in use. The n32 ABI Documentation also mandates the use of additions | |
453 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 454 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 455 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
456 | |
457 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 458 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
459 | |
460 | #define ADDRESS_LOAD_INSN \ | |
461 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
462 | ||
463 | #define ADDRESS_STORE_INSN \ | |
464 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
465 | ||
a4672219 | 466 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
467 | #define CPU_HAS_MIPS16(cpu) \ |
468 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
469 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 470 | |
60b63b72 RS |
471 | /* True if CPU has a dror instruction. */ |
472 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
473 | ||
474 | /* True if CPU has a ror instruction. */ | |
475 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
476 | ||
dd3cbb7e NC |
477 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
478 | #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON) | |
479 | ||
b19e8a9b AN |
480 | /* True if CPU does not implement the all the coprocessor insns. For these |
481 | CPUs only those COP insns are accepted that are explicitly marked to be | |
482 | available on the CPU. ISA membership for COP insns is ignored. */ | |
483 | #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON) | |
484 | ||
c8978940 CD |
485 | /* True if mflo and mfhi can be immediately followed by instructions |
486 | which write to the HI and LO registers. | |
487 | ||
488 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
489 | (at least) two instructions between the reads of HI/LO and | |
490 | instructions which write them, and later ISAs do not. Contradicting | |
491 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
492 | the UM for the NEC Vr5000) document needing the instructions between | |
493 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
494 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
495 | earlier-ISA CPUs for which CPU documentation declares that the | |
496 | instructions are really interlocked. */ | |
497 | #define hilo_interlocks \ | |
498 | (mips_opts.isa == ISA_MIPS32 \ | |
499 | || mips_opts.isa == ISA_MIPS32R2 \ | |
500 | || mips_opts.isa == ISA_MIPS64 \ | |
501 | || mips_opts.isa == ISA_MIPS64R2 \ | |
502 | || mips_opts.arch == CPU_R4010 \ | |
503 | || mips_opts.arch == CPU_R10000 \ | |
504 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
505 | || mips_opts.arch == CPU_R14000 \ |
506 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 507 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 CD |
508 | || mips_opts.arch == CPU_VR5500 \ |
509 | ) | |
252b5132 RH |
510 | |
511 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
512 | from the GPRs after they are loaded from memory, and thus does not |
513 | require nops to be inserted. This applies to instructions marked | |
514 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
515 | level I. */ | |
252b5132 | 516 | #define gpr_interlocks \ |
e7af610e | 517 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 518 | || mips_opts.arch == CPU_R3900) |
252b5132 | 519 | |
81912461 ILT |
520 | /* Whether the processor uses hardware interlocks to avoid delays |
521 | required by coprocessor instructions, and thus does not require | |
522 | nops to be inserted. This applies to instructions marked | |
523 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
524 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
525 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
526 | levels I, II, and III. */ | |
bdaaa2e1 | 527 | /* Itbl support may require additional care here. */ |
81912461 ILT |
528 | #define cop_interlocks \ |
529 | ((mips_opts.isa != ISA_MIPS1 \ | |
530 | && mips_opts.isa != ISA_MIPS2 \ | |
531 | && mips_opts.isa != ISA_MIPS3) \ | |
532 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
533 | ) |
534 | ||
535 | /* Whether the processor uses hardware interlocks to protect reads | |
536 | from coprocessor registers after they are loaded from memory, and | |
537 | thus does not require nops to be inserted. This applies to | |
538 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
539 | requires at MIPS ISA level I. */ | |
540 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 541 | |
6b76fefe CM |
542 | /* Is this a mfhi or mflo instruction? */ |
543 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
544 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
545 | ||
546 | /* Returns true for a (non floating-point) coprocessor instruction. Reading | |
547 | or writing the condition code is only possible on the coprocessors and | |
548 | these insns are not marked with INSN_COP. Thus for these insns use the | |
a242dc0d | 549 | condition-code flags. */ |
b19e8a9b AN |
550 | #define COP_INSN(PINFO) \ |
551 | (PINFO != INSN_MACRO \ | |
a242dc0d AN |
552 | && ((PINFO) & (FP_S | FP_D)) == 0 \ |
553 | && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE))) | |
6b76fefe | 554 | |
252b5132 RH |
555 | /* MIPS PIC level. */ |
556 | ||
a161fe53 | 557 | enum mips_pic_level mips_pic; |
252b5132 | 558 | |
c9914766 | 559 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 560 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 561 | static int mips_big_got = 0; |
252b5132 RH |
562 | |
563 | /* 1 if trap instructions should used for overflow rather than break | |
564 | instructions. */ | |
c9914766 | 565 | static int mips_trap = 0; |
252b5132 | 566 | |
119d663a | 567 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 568 | by assembling two single width halves into two single width floating |
119d663a NC |
569 | point registers which just happen to alias the double width destination |
570 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 571 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
572 | automatically at assemble time. */ |
573 | static int mips_disable_float_construction; | |
574 | ||
252b5132 RH |
575 | /* Non-zero if any .set noreorder directives were used. */ |
576 | ||
577 | static int mips_any_noreorder; | |
578 | ||
6b76fefe CM |
579 | /* Non-zero if nops should be inserted when the register referenced in |
580 | an mfhi/mflo instruction is read in the next two instructions. */ | |
581 | static int mips_7000_hilo_fix; | |
582 | ||
02ffd3e4 | 583 | /* The size of objects in the small data section. */ |
156c2f8b | 584 | static unsigned int g_switch_value = 8; |
252b5132 RH |
585 | /* Whether the -G option was used. */ |
586 | static int g_switch_seen = 0; | |
587 | ||
588 | #define N_RMASK 0xc4 | |
589 | #define N_VFP 0xd4 | |
590 | ||
591 | /* If we can determine in advance that GP optimization won't be | |
592 | possible, we can skip the relaxation stuff that tries to produce | |
593 | GP-relative references. This makes delay slot optimization work | |
594 | better. | |
595 | ||
596 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
597 | gcc output. It needs to guess right for gcc, otherwise gcc |
598 | will put what it thinks is a GP-relative instruction in a branch | |
599 | delay slot. | |
252b5132 RH |
600 | |
601 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
602 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 603 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
604 | |
605 | /* handle of the OPCODE hash table */ | |
606 | static struct hash_control *op_hash = NULL; | |
607 | ||
608 | /* The opcode hash table we use for the mips16. */ | |
609 | static struct hash_control *mips16_op_hash = NULL; | |
610 | ||
611 | /* This array holds the chars that always start a comment. If the | |
612 | pre-processor is disabled, these aren't very useful */ | |
613 | const char comment_chars[] = "#"; | |
614 | ||
615 | /* This array holds the chars that only start a comment at the beginning of | |
616 | a line. If the line seems to have the form '# 123 filename' | |
617 | .line and .file directives will appear in the pre-processed output */ | |
618 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
619 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 620 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
621 | /* Also note that C style comments are always supported. */ |
622 | const char line_comment_chars[] = "#"; | |
623 | ||
bdaaa2e1 | 624 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 625 | const char line_separator_chars[] = ";"; |
252b5132 RH |
626 | |
627 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
628 | const char EXP_CHARS[] = "eE"; | |
629 | ||
630 | /* Chars that mean this number is a floating point constant */ | |
631 | /* As in 0f12.456 */ | |
632 | /* or 0d1.2345e12 */ | |
633 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
634 | ||
635 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
636 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
637 | but nothing is ideal around here. | |
638 | */ | |
639 | ||
640 | static char *insn_error; | |
641 | ||
642 | static int auto_align = 1; | |
643 | ||
644 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
645 | offset in the stack frame from which to restore the $gp register. | |
646 | This is set by the .cprestore pseudo-op, and saved in this | |
647 | variable. */ | |
648 | static offsetT mips_cprestore_offset = -1; | |
649 | ||
67c1ffbe | 650 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 651 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 652 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
653 | static offsetT mips_cpreturn_offset = -1; |
654 | static int mips_cpreturn_register = -1; | |
655 | static int mips_gp_register = GP; | |
def2e0dd | 656 | static int mips_gprel_offset = 0; |
6478892d | 657 | |
7a621144 DJ |
658 | /* Whether mips_cprestore_offset has been set in the current function |
659 | (or whether it has already been warned about, if not). */ | |
660 | static int mips_cprestore_valid = 0; | |
661 | ||
252b5132 RH |
662 | /* This is the register which holds the stack frame, as set by the |
663 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
664 | static int mips_frame_reg = SP; | |
665 | ||
7a621144 DJ |
666 | /* Whether mips_frame_reg has been set in the current function |
667 | (or whether it has already been warned about, if not). */ | |
668 | static int mips_frame_reg_valid = 0; | |
669 | ||
252b5132 RH |
670 | /* To output NOP instructions correctly, we need to keep information |
671 | about the previous two instructions. */ | |
672 | ||
673 | /* Whether we are optimizing. The default value of 2 means to remove | |
674 | unneeded NOPs and swap branch instructions when possible. A value | |
675 | of 1 means to not swap branches. A value of 0 means to always | |
676 | insert NOPs. */ | |
677 | static int mips_optimize = 2; | |
678 | ||
679 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
680 | equivalent to seeing no -g option at all. */ | |
681 | static int mips_debug = 0; | |
682 | ||
7d8e00cf RS |
683 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
684 | #define MAX_VR4130_NOPS 4 | |
685 | ||
686 | /* The maximum number of NOPs needed to fill delay slots. */ | |
687 | #define MAX_DELAY_NOPS 2 | |
688 | ||
689 | /* The maximum number of NOPs needed for any purpose. */ | |
690 | #define MAX_NOPS 4 | |
71400594 RS |
691 | |
692 | /* A list of previous instructions, with index 0 being the most recent. | |
693 | We need to look back MAX_NOPS instructions when filling delay slots | |
694 | or working around processor errata. We need to look back one | |
695 | instruction further if we're thinking about using history[0] to | |
696 | fill a branch delay slot. */ | |
697 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 698 | |
1e915849 RS |
699 | /* Nop instructions used by emit_nop. */ |
700 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
701 | ||
702 | /* The appropriate nop for the current mode. */ | |
703 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 704 | |
252b5132 RH |
705 | /* If this is set, it points to a frag holding nop instructions which |
706 | were inserted before the start of a noreorder section. If those | |
707 | nops turn out to be unnecessary, the size of the frag can be | |
708 | decreased. */ | |
709 | static fragS *prev_nop_frag; | |
710 | ||
711 | /* The number of nop instructions we created in prev_nop_frag. */ | |
712 | static int prev_nop_frag_holds; | |
713 | ||
714 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 715 | prev_nop_frag. */ |
252b5132 RH |
716 | static int prev_nop_frag_required; |
717 | ||
718 | /* The number of instructions we've seen since prev_nop_frag. */ | |
719 | static int prev_nop_frag_since; | |
720 | ||
721 | /* For ECOFF and ELF, relocations against symbols are done in two | |
722 | parts, with a HI relocation and a LO relocation. Each relocation | |
723 | has only 16 bits of space to store an addend. This means that in | |
724 | order for the linker to handle carries correctly, it must be able | |
725 | to locate both the HI and the LO relocation. This means that the | |
726 | relocations must appear in order in the relocation table. | |
727 | ||
728 | In order to implement this, we keep track of each unmatched HI | |
729 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 730 | corresponding LO relocation. */ |
252b5132 | 731 | |
e972090a NC |
732 | struct mips_hi_fixup |
733 | { | |
252b5132 RH |
734 | /* Next HI fixup. */ |
735 | struct mips_hi_fixup *next; | |
736 | /* This fixup. */ | |
737 | fixS *fixp; | |
738 | /* The section this fixup is in. */ | |
739 | segT seg; | |
740 | }; | |
741 | ||
742 | /* The list of unmatched HI relocs. */ | |
743 | ||
744 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
745 | ||
64bdfcaf RS |
746 | /* The frag containing the last explicit relocation operator. |
747 | Null if explicit relocations have not been used. */ | |
748 | ||
749 | static fragS *prev_reloc_op_frag; | |
750 | ||
252b5132 RH |
751 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
752 | ||
753 | #define X ILLEGAL_REG | |
e972090a NC |
754 | static const int mips32_to_16_reg_map[] = |
755 | { | |
252b5132 RH |
756 | X, X, 2, 3, 4, 5, 6, 7, |
757 | X, X, X, X, X, X, X, X, | |
758 | 0, 1, X, X, X, X, X, X, | |
759 | X, X, X, X, X, X, X, X | |
760 | }; | |
761 | #undef X | |
762 | ||
763 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
764 | ||
e972090a NC |
765 | static const unsigned int mips16_to_32_reg_map[] = |
766 | { | |
252b5132 RH |
767 | 16, 17, 2, 3, 4, 5, 6, 7 |
768 | }; | |
60b63b72 | 769 | |
71400594 RS |
770 | /* Classifies the kind of instructions we're interested in when |
771 | implementing -mfix-vr4120. */ | |
c67a084a NC |
772 | enum fix_vr4120_class |
773 | { | |
71400594 RS |
774 | FIX_VR4120_MACC, |
775 | FIX_VR4120_DMACC, | |
776 | FIX_VR4120_MULT, | |
777 | FIX_VR4120_DMULT, | |
778 | FIX_VR4120_DIV, | |
779 | FIX_VR4120_MTHILO, | |
780 | NUM_FIX_VR4120_CLASSES | |
781 | }; | |
782 | ||
c67a084a NC |
783 | /* ...likewise -mfix-loongson2f-jump. */ |
784 | static bfd_boolean mips_fix_loongson2f_jump; | |
785 | ||
786 | /* ...likewise -mfix-loongson2f-nop. */ | |
787 | static bfd_boolean mips_fix_loongson2f_nop; | |
788 | ||
789 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
790 | static bfd_boolean mips_fix_loongson2f; | |
791 | ||
71400594 RS |
792 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
793 | there must be at least one other instruction between an instruction | |
794 | of type X and an instruction of type Y. */ | |
795 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
796 | ||
797 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 798 | static int mips_fix_vr4120; |
4a6a3df4 | 799 | |
7d8e00cf RS |
800 | /* ...likewise -mfix-vr4130. */ |
801 | static int mips_fix_vr4130; | |
802 | ||
6a32d874 CM |
803 | /* ...likewise -mfix-24k. */ |
804 | static int mips_fix_24k; | |
805 | ||
d954098f DD |
806 | /* ...likewise -mfix-cn63xxp1 */ |
807 | static bfd_boolean mips_fix_cn63xxp1; | |
808 | ||
4a6a3df4 AO |
809 | /* We don't relax branches by default, since this causes us to expand |
810 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
811 | fail to compute the offset before expanding the macro to the most | |
812 | efficient expansion. */ | |
813 | ||
814 | static int mips_relax_branch; | |
252b5132 | 815 | \f |
4d7206a2 RS |
816 | /* The expansion of many macros depends on the type of symbol that |
817 | they refer to. For example, when generating position-dependent code, | |
818 | a macro that refers to a symbol may have two different expansions, | |
819 | one which uses GP-relative addresses and one which uses absolute | |
820 | addresses. When generating SVR4-style PIC, a macro may have | |
821 | different expansions for local and global symbols. | |
822 | ||
823 | We handle these situations by generating both sequences and putting | |
824 | them in variant frags. In position-dependent code, the first sequence | |
825 | will be the GP-relative one and the second sequence will be the | |
826 | absolute one. In SVR4 PIC, the first sequence will be for global | |
827 | symbols and the second will be for local symbols. | |
828 | ||
584892a6 RS |
829 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
830 | SECOND are the lengths of the two sequences in bytes. These fields | |
831 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
832 | the subtype has the following flags: | |
4d7206a2 | 833 | |
584892a6 RS |
834 | RELAX_USE_SECOND |
835 | Set if it has been decided that we should use the second | |
836 | sequence instead of the first. | |
837 | ||
838 | RELAX_SECOND_LONGER | |
839 | Set in the first variant frag if the macro's second implementation | |
840 | is longer than its first. This refers to the macro as a whole, | |
841 | not an individual relaxation. | |
842 | ||
843 | RELAX_NOMACRO | |
844 | Set in the first variant frag if the macro appeared in a .set nomacro | |
845 | block and if one alternative requires a warning but the other does not. | |
846 | ||
847 | RELAX_DELAY_SLOT | |
848 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
849 | delay slot. | |
4d7206a2 RS |
850 | |
851 | The frag's "opcode" points to the first fixup for relaxable code. | |
852 | ||
853 | Relaxable macros are generated using a sequence such as: | |
854 | ||
855 | relax_start (SYMBOL); | |
856 | ... generate first expansion ... | |
857 | relax_switch (); | |
858 | ... generate second expansion ... | |
859 | relax_end (); | |
860 | ||
861 | The code and fixups for the unwanted alternative are discarded | |
862 | by md_convert_frag. */ | |
584892a6 | 863 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 864 | |
584892a6 RS |
865 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
866 | #define RELAX_SECOND(X) ((X) & 0xff) | |
867 | #define RELAX_USE_SECOND 0x10000 | |
868 | #define RELAX_SECOND_LONGER 0x20000 | |
869 | #define RELAX_NOMACRO 0x40000 | |
870 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 871 | |
4a6a3df4 AO |
872 | /* Branch without likely bit. If label is out of range, we turn: |
873 | ||
874 | beq reg1, reg2, label | |
875 | delay slot | |
876 | ||
877 | into | |
878 | ||
879 | bne reg1, reg2, 0f | |
880 | nop | |
881 | j label | |
882 | 0: delay slot | |
883 | ||
884 | with the following opcode replacements: | |
885 | ||
886 | beq <-> bne | |
887 | blez <-> bgtz | |
888 | bltz <-> bgez | |
889 | bc1f <-> bc1t | |
890 | ||
891 | bltzal <-> bgezal (with jal label instead of j label) | |
892 | ||
893 | Even though keeping the delay slot instruction in the delay slot of | |
894 | the branch would be more efficient, it would be very tricky to do | |
895 | correctly, because we'd have to introduce a variable frag *after* | |
896 | the delay slot instruction, and expand that instead. Let's do it | |
897 | the easy way for now, even if the branch-not-taken case now costs | |
898 | one additional instruction. Out-of-range branches are not supposed | |
899 | to be common, anyway. | |
900 | ||
901 | Branch likely. If label is out of range, we turn: | |
902 | ||
903 | beql reg1, reg2, label | |
904 | delay slot (annulled if branch not taken) | |
905 | ||
906 | into | |
907 | ||
908 | beql reg1, reg2, 1f | |
909 | nop | |
910 | beql $0, $0, 2f | |
911 | nop | |
912 | 1: j[al] label | |
913 | delay slot (executed only if branch taken) | |
914 | 2: | |
915 | ||
916 | It would be possible to generate a shorter sequence by losing the | |
917 | likely bit, generating something like: | |
b34976b6 | 918 | |
4a6a3df4 AO |
919 | bne reg1, reg2, 0f |
920 | nop | |
921 | j[al] label | |
922 | delay slot (executed only if branch taken) | |
923 | 0: | |
924 | ||
925 | beql -> bne | |
926 | bnel -> beq | |
927 | blezl -> bgtz | |
928 | bgtzl -> blez | |
929 | bltzl -> bgez | |
930 | bgezl -> bltz | |
931 | bc1fl -> bc1t | |
932 | bc1tl -> bc1f | |
933 | ||
934 | bltzall -> bgezal (with jal label instead of j label) | |
935 | bgezall -> bltzal (ditto) | |
936 | ||
937 | ||
938 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
939 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
940 | ((relax_substateT) \ | |
941 | (0xc0000000 \ | |
942 | | ((at) & 0x1f) \ | |
943 | | ((toofar) ? 0x20 : 0) \ | |
944 | | ((link) ? 0x40 : 0) \ | |
945 | | ((likely) ? 0x80 : 0) \ | |
946 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 947 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
948 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
949 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
950 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
951 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
952 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 953 | |
252b5132 RH |
954 | /* For mips16 code, we use an entirely different form of relaxation. |
955 | mips16 supports two versions of most instructions which take | |
956 | immediate values: a small one which takes some small value, and a | |
957 | larger one which takes a 16 bit value. Since branches also follow | |
958 | this pattern, relaxing these values is required. | |
959 | ||
960 | We can assemble both mips16 and normal MIPS code in a single | |
961 | object. Therefore, we need to support this type of relaxation at | |
962 | the same time that we support the relaxation described above. We | |
963 | use the high bit of the subtype field to distinguish these cases. | |
964 | ||
965 | The information we store for this type of relaxation is the | |
966 | argument code found in the opcode file for this relocation, whether | |
967 | the user explicitly requested a small or extended form, and whether | |
968 | the relocation is in a jump or jal delay slot. That tells us the | |
969 | size of the value, and how it should be stored. We also store | |
970 | whether the fragment is considered to be extended or not. We also | |
971 | store whether this is known to be a branch to a different section, | |
972 | whether we have tried to relax this frag yet, and whether we have | |
973 | ever extended a PC relative fragment because of a shift count. */ | |
974 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
975 | (0x80000000 \ | |
976 | | ((type) & 0xff) \ | |
977 | | ((small) ? 0x100 : 0) \ | |
978 | | ((ext) ? 0x200 : 0) \ | |
979 | | ((dslot) ? 0x400 : 0) \ | |
980 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 981 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
982 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
983 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
984 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
985 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
986 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
987 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
988 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
989 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
990 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
991 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
992 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
993 | |
994 | /* Is the given value a sign-extended 32-bit value? */ | |
995 | #define IS_SEXT_32BIT_NUM(x) \ | |
996 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
997 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
998 | ||
999 | /* Is the given value a sign-extended 16-bit value? */ | |
1000 | #define IS_SEXT_16BIT_NUM(x) \ | |
1001 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1002 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1003 | ||
2051e8c4 MR |
1004 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1005 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1006 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1007 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1008 | ||
bf12938e RS |
1009 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
1010 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
1011 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
1012 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
1013 | | (((VALUE) & (MASK)) << (SHIFT))) | |
1014 | ||
1015 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
1016 | SHIFT places. */ | |
1017 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1018 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1019 | ||
1020 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1021 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1022 | ||
1023 | include/opcode/mips.h specifies operand fields using the macros | |
1024 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1025 | with "MIPS16OP" instead of "OP". */ | |
1026 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
1027 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
1028 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
1029 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1030 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1031 | ||
1032 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
1033 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
1034 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
1035 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
1036 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1037 | MIPS16OP_MASK_##FIELD, \ | |
1038 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
1039 | \f |
1040 | /* Global variables used when generating relaxable macros. See the | |
1041 | comment above RELAX_ENCODE for more details about how relaxation | |
1042 | is used. */ | |
1043 | static struct { | |
1044 | /* 0 if we're not emitting a relaxable macro. | |
1045 | 1 if we're emitting the first of the two relaxation alternatives. | |
1046 | 2 if we're emitting the second alternative. */ | |
1047 | int sequence; | |
1048 | ||
1049 | /* The first relaxable fixup in the current frag. (In other words, | |
1050 | the first fixup that refers to relaxable code.) */ | |
1051 | fixS *first_fixup; | |
1052 | ||
1053 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1054 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1055 | unsigned int sizes[2]; | |
1056 | ||
1057 | /* The symbol on which the choice of sequence depends. */ | |
1058 | symbolS *symbol; | |
1059 | } mips_relax; | |
252b5132 | 1060 | \f |
584892a6 RS |
1061 | /* Global variables used to decide whether a macro needs a warning. */ |
1062 | static struct { | |
1063 | /* True if the macro is in a branch delay slot. */ | |
1064 | bfd_boolean delay_slot_p; | |
1065 | ||
1066 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
1067 | in bytes and sizes[1] is the length of the second alternative. | |
1068 | For non-relaxable macros, both elements give the length of the | |
1069 | macro in bytes. */ | |
1070 | unsigned int sizes[2]; | |
1071 | ||
1072 | /* The first variant frag for this macro. */ | |
1073 | fragS *first_frag; | |
1074 | } mips_macro_warning; | |
1075 | \f | |
252b5132 RH |
1076 | /* Prototypes for static functions. */ |
1077 | ||
17a2f251 | 1078 | #define internalError() \ |
252b5132 | 1079 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
1080 | |
1081 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
1082 | ||
b34976b6 | 1083 | static void append_insn |
c67a084a | 1084 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *); |
7d10b47d | 1085 | static void mips_no_prev_insn (void); |
c67a084a | 1086 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1087 | static void mips16_macro_build |
03ea81db | 1088 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1089 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1090 | static void macro_start (void); |
1091 | static void macro_end (void); | |
17a2f251 TS |
1092 | static void macro (struct mips_cl_insn * ip); |
1093 | static void mips16_macro (struct mips_cl_insn * ip); | |
17a2f251 TS |
1094 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1095 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1096 | static void mips16_immed |
17a2f251 TS |
1097 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
1098 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 1099 | static size_t my_getSmallExpression |
17a2f251 TS |
1100 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1101 | static void my_getExpression (expressionS *, char *); | |
1102 | static void s_align (int); | |
1103 | static void s_change_sec (int); | |
1104 | static void s_change_section (int); | |
1105 | static void s_cons (int); | |
1106 | static void s_float_cons (int); | |
1107 | static void s_mips_globl (int); | |
1108 | static void s_option (int); | |
1109 | static void s_mipsset (int); | |
1110 | static void s_abicalls (int); | |
1111 | static void s_cpload (int); | |
1112 | static void s_cpsetup (int); | |
1113 | static void s_cplocal (int); | |
1114 | static void s_cprestore (int); | |
1115 | static void s_cpreturn (int); | |
741d6ea8 JM |
1116 | static void s_dtprelword (int); |
1117 | static void s_dtpreldword (int); | |
17a2f251 TS |
1118 | static void s_gpvalue (int); |
1119 | static void s_gpword (int); | |
1120 | static void s_gpdword (int); | |
1121 | static void s_cpadd (int); | |
1122 | static void s_insn (int); | |
1123 | static void md_obj_begin (void); | |
1124 | static void md_obj_end (void); | |
1125 | static void s_mips_ent (int); | |
1126 | static void s_mips_end (int); | |
1127 | static void s_mips_frame (int); | |
1128 | static void s_mips_mask (int reg_type); | |
1129 | static void s_mips_stab (int); | |
1130 | static void s_mips_weakext (int); | |
1131 | static void s_mips_file (int); | |
1132 | static void s_mips_loc (int); | |
1133 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1134 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1135 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
1136 | |
1137 | /* Table and functions used to map between CPU/ISA names, and | |
1138 | ISA levels, and CPU numbers. */ | |
1139 | ||
e972090a NC |
1140 | struct mips_cpu_info |
1141 | { | |
e7af610e | 1142 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1143 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1144 | int isa; /* ISA level. */ |
1145 | int cpu; /* CPU number (default CPU if ISA). */ | |
1146 | }; | |
1147 | ||
ad3fea08 TS |
1148 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1149 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1150 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1151 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1152 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1153 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1154 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
ad3fea08 | 1155 | |
17a2f251 TS |
1156 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1157 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1158 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1159 | \f |
1160 | /* Pseudo-op table. | |
1161 | ||
1162 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1163 | should be defined here, but are currently unsupported: .alias, | |
1164 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1165 | ||
1166 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1167 | specific to the type of debugging information being generated, and | |
1168 | should be defined by the object format: .aent, .begin, .bend, | |
1169 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1170 | .vreg. | |
1171 | ||
1172 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1173 | not MIPS CPU specific, but are also not specific to the object file | |
1174 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1175 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1176 | |
e972090a NC |
1177 | static const pseudo_typeS mips_pseudo_table[] = |
1178 | { | |
beae10d5 | 1179 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1180 | {"option", s_option, 0}, |
1181 | {"set", s_mipsset, 0}, | |
1182 | {"rdata", s_change_sec, 'r'}, | |
1183 | {"sdata", s_change_sec, 's'}, | |
1184 | {"livereg", s_ignore, 0}, | |
1185 | {"abicalls", s_abicalls, 0}, | |
1186 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1187 | {"cpsetup", s_cpsetup, 0}, |
1188 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1189 | {"cprestore", s_cprestore, 0}, |
6478892d | 1190 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1191 | {"dtprelword", s_dtprelword, 0}, |
1192 | {"dtpreldword", s_dtpreldword, 0}, | |
6478892d | 1193 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1194 | {"gpword", s_gpword, 0}, |
10181a0d | 1195 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1196 | {"cpadd", s_cpadd, 0}, |
1197 | {"insn", s_insn, 0}, | |
1198 | ||
beae10d5 | 1199 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1200 | chips. */ |
38a57ae7 | 1201 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1202 | {"bss", s_change_sec, 'b'}, |
1203 | {"err", s_err, 0}, | |
1204 | {"half", s_cons, 1}, | |
1205 | {"dword", s_cons, 3}, | |
1206 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1207 | {"origin", s_org, 0}, |
1208 | {"repeat", s_rept, 0}, | |
252b5132 | 1209 | |
998b3c36 MR |
1210 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1211 | {"sbss", s_change_sec, 'B'}, | |
1212 | ||
beae10d5 | 1213 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1214 | here for one reason or another. */ |
1215 | {"align", s_align, 0}, | |
1216 | {"byte", s_cons, 0}, | |
1217 | {"data", s_change_sec, 'd'}, | |
1218 | {"double", s_float_cons, 'd'}, | |
1219 | {"float", s_float_cons, 'f'}, | |
1220 | {"globl", s_mips_globl, 0}, | |
1221 | {"global", s_mips_globl, 0}, | |
1222 | {"hword", s_cons, 1}, | |
1223 | {"int", s_cons, 2}, | |
1224 | {"long", s_cons, 2}, | |
1225 | {"octa", s_cons, 4}, | |
1226 | {"quad", s_cons, 3}, | |
cca86cc8 | 1227 | {"section", s_change_section, 0}, |
252b5132 RH |
1228 | {"short", s_cons, 1}, |
1229 | {"single", s_float_cons, 'f'}, | |
1230 | {"stabn", s_mips_stab, 'n'}, | |
1231 | {"text", s_change_sec, 't'}, | |
1232 | {"word", s_cons, 2}, | |
add56521 | 1233 | |
add56521 | 1234 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1235 | |
43841e91 | 1236 | { NULL, NULL, 0 }, |
252b5132 RH |
1237 | }; |
1238 | ||
e972090a NC |
1239 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1240 | { | |
beae10d5 KH |
1241 | /* These pseudo-ops should be defined by the object file format. |
1242 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1243 | {"aent", s_mips_ent, 1}, |
1244 | {"bgnb", s_ignore, 0}, | |
1245 | {"end", s_mips_end, 0}, | |
1246 | {"endb", s_ignore, 0}, | |
1247 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1248 | {"file", s_mips_file, 0}, |
252b5132 RH |
1249 | {"fmask", s_mips_mask, 'F'}, |
1250 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1251 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1252 | {"mask", s_mips_mask, 'R'}, |
1253 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1254 | { NULL, NULL, 0 }, |
252b5132 RH |
1255 | }; |
1256 | ||
3ae8dd8d MR |
1257 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1258 | purpose of the `.dc.a' internal pseudo-op. */ | |
1259 | ||
1260 | int | |
1261 | mips_address_bytes (void) | |
1262 | { | |
1263 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1264 | } | |
1265 | ||
17a2f251 | 1266 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1267 | |
1268 | void | |
17a2f251 | 1269 | mips_pop_insert (void) |
252b5132 RH |
1270 | { |
1271 | pop_insert (mips_pseudo_table); | |
1272 | if (! ECOFF_DEBUGGING) | |
1273 | pop_insert (mips_nonecoff_pseudo_table); | |
1274 | } | |
1275 | \f | |
1276 | /* Symbols labelling the current insn. */ | |
1277 | ||
e972090a NC |
1278 | struct insn_label_list |
1279 | { | |
252b5132 RH |
1280 | struct insn_label_list *next; |
1281 | symbolS *label; | |
1282 | }; | |
1283 | ||
252b5132 | 1284 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1285 | #define label_list tc_segment_info_data.labels |
252b5132 | 1286 | |
17a2f251 | 1287 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1288 | |
1289 | static inline void | |
17a2f251 | 1290 | mips_clear_insn_labels (void) |
252b5132 RH |
1291 | { |
1292 | register struct insn_label_list **pl; | |
a8dbcb85 | 1293 | segment_info_type *si; |
252b5132 | 1294 | |
a8dbcb85 TS |
1295 | if (now_seg) |
1296 | { | |
1297 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1298 | ; | |
1299 | ||
1300 | si = seg_info (now_seg); | |
1301 | *pl = si->label_list; | |
1302 | si->label_list = NULL; | |
1303 | } | |
252b5132 | 1304 | } |
a8dbcb85 | 1305 | |
252b5132 RH |
1306 | \f |
1307 | static char *expr_end; | |
1308 | ||
1309 | /* Expressions which appear in instructions. These are set by | |
1310 | mips_ip. */ | |
1311 | ||
1312 | static expressionS imm_expr; | |
5f74bc13 | 1313 | static expressionS imm2_expr; |
252b5132 RH |
1314 | static expressionS offset_expr; |
1315 | ||
1316 | /* Relocs associated with imm_expr and offset_expr. */ | |
1317 | ||
f6688943 TS |
1318 | static bfd_reloc_code_real_type imm_reloc[3] |
1319 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1320 | static bfd_reloc_code_real_type offset_reloc[3] | |
1321 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1322 | |
252b5132 RH |
1323 | /* These are set by mips16_ip if an explicit extension is used. */ |
1324 | ||
b34976b6 | 1325 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1326 | |
7ed4a06a | 1327 | #ifdef OBJ_ELF |
ecb4347a DJ |
1328 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1329 | ECOFF debugging. */ | |
252b5132 RH |
1330 | |
1331 | static segT pdr_seg; | |
7ed4a06a | 1332 | #endif |
252b5132 | 1333 | |
e013f690 TS |
1334 | /* The default target format to use. */ |
1335 | ||
aeffff67 RS |
1336 | #if defined (TE_FreeBSD) |
1337 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1338 | #elif defined (TE_TMIPS) | |
1339 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1340 | #else | |
1341 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1342 | #endif | |
1343 | ||
e013f690 | 1344 | const char * |
17a2f251 | 1345 | mips_target_format (void) |
e013f690 TS |
1346 | { |
1347 | switch (OUTPUT_FLAVOR) | |
1348 | { | |
e013f690 TS |
1349 | case bfd_target_ecoff_flavour: |
1350 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1351 | case bfd_target_coff_flavour: | |
1352 | return "pe-mips"; | |
1353 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1354 | #ifdef TE_VXWORKS |
1355 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1356 | return (target_big_endian | |
1357 | ? "elf32-bigmips-vxworks" | |
1358 | : "elf32-littlemips-vxworks"); | |
1359 | #endif | |
e013f690 | 1360 | return (target_big_endian |
cfe86eaa | 1361 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1362 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1363 | : (HAVE_NEWABI |
aeffff67 RS |
1364 | ? ELF_TARGET ("elf32-n", "big") |
1365 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1366 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1367 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1368 | : (HAVE_NEWABI |
aeffff67 RS |
1369 | ? ELF_TARGET ("elf32-n", "little") |
1370 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1371 | default: |
1372 | abort (); | |
1373 | return NULL; | |
1374 | } | |
1375 | } | |
1376 | ||
1e915849 RS |
1377 | /* Return the length of instruction INSN. */ |
1378 | ||
1379 | static inline unsigned int | |
1380 | insn_length (const struct mips_cl_insn *insn) | |
1381 | { | |
1382 | if (!mips_opts.mips16) | |
1383 | return 4; | |
1384 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1385 | } | |
1386 | ||
1387 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1388 | ||
1389 | static void | |
1390 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1391 | { | |
1392 | size_t i; | |
1393 | ||
1394 | insn->insn_mo = mo; | |
1395 | insn->use_extend = FALSE; | |
1396 | insn->extend = 0; | |
1397 | insn->insn_opcode = mo->match; | |
1398 | insn->frag = NULL; | |
1399 | insn->where = 0; | |
1400 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1401 | insn->fixp[i] = NULL; | |
1402 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1403 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1404 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 1405 | insn->complete_p = 0; |
1e915849 RS |
1406 | } |
1407 | ||
742a56fe RS |
1408 | /* Record the current MIPS16 mode in now_seg. */ |
1409 | ||
1410 | static void | |
1411 | mips_record_mips16_mode (void) | |
1412 | { | |
1413 | segment_info_type *si; | |
1414 | ||
1415 | si = seg_info (now_seg); | |
1416 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1417 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
1418 | } | |
1419 | ||
1e915849 RS |
1420 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1421 | ||
1422 | static void | |
1423 | install_insn (const struct mips_cl_insn *insn) | |
1424 | { | |
1425 | char *f = insn->frag->fr_literal + insn->where; | |
1426 | if (!mips_opts.mips16) | |
1427 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1428 | else if (insn->mips16_absolute_jump_p) | |
1429 | { | |
1430 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1431 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1432 | } | |
1433 | else | |
1434 | { | |
1435 | if (insn->use_extend) | |
1436 | { | |
1437 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1438 | f += 2; | |
1439 | } | |
1440 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1441 | } | |
742a56fe | 1442 | mips_record_mips16_mode (); |
1e915849 RS |
1443 | } |
1444 | ||
1445 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1446 | and install the opcode in the new location. */ | |
1447 | ||
1448 | static void | |
1449 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1450 | { | |
1451 | size_t i; | |
1452 | ||
1453 | insn->frag = frag; | |
1454 | insn->where = where; | |
1455 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1456 | if (insn->fixp[i] != NULL) | |
1457 | { | |
1458 | insn->fixp[i]->fx_frag = frag; | |
1459 | insn->fixp[i]->fx_where = where; | |
1460 | } | |
1461 | install_insn (insn); | |
1462 | } | |
1463 | ||
1464 | /* Add INSN to the end of the output. */ | |
1465 | ||
1466 | static void | |
1467 | add_fixed_insn (struct mips_cl_insn *insn) | |
1468 | { | |
1469 | char *f = frag_more (insn_length (insn)); | |
1470 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1471 | } | |
1472 | ||
1473 | /* Start a variant frag and move INSN to the start of the variant part, | |
1474 | marking it as fixed. The other arguments are as for frag_var. */ | |
1475 | ||
1476 | static void | |
1477 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1478 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1479 | { | |
1480 | frag_grow (max_chars); | |
1481 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1482 | insn->fixed_p = 1; | |
1483 | frag_var (rs_machine_dependent, max_chars, var, | |
1484 | subtype, symbol, offset, NULL); | |
1485 | } | |
1486 | ||
1487 | /* Insert N copies of INSN into the history buffer, starting at | |
1488 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1489 | ||
1490 | static void | |
1491 | insert_into_history (unsigned int first, unsigned int n, | |
1492 | const struct mips_cl_insn *insn) | |
1493 | { | |
1494 | if (mips_relax.sequence != 2) | |
1495 | { | |
1496 | unsigned int i; | |
1497 | ||
1498 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1499 | if (i >= first + n) | |
1500 | history[i] = history[i - n]; | |
1501 | else | |
1502 | history[i] = *insn; | |
1503 | } | |
1504 | } | |
1505 | ||
1506 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1507 | ||
1508 | static void | |
1509 | emit_nop (void) | |
1510 | { | |
1511 | add_fixed_insn (NOP_INSN); | |
1512 | insert_into_history (0, 1, NOP_INSN); | |
1513 | } | |
1514 | ||
71400594 RS |
1515 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1516 | the idea is to make it obvious at a glance that each errata is | |
1517 | included. */ | |
1518 | ||
1519 | static void | |
1520 | init_vr4120_conflicts (void) | |
1521 | { | |
1522 | #define CONFLICT(FIRST, SECOND) \ | |
1523 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1524 | ||
1525 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1526 | CONFLICT (MACC, DIV); | |
1527 | CONFLICT (DMACC, DIV); | |
1528 | ||
1529 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1530 | CONFLICT (DMULT, DMULT); | |
1531 | CONFLICT (DMULT, DMACC); | |
1532 | CONFLICT (DMACC, DMULT); | |
1533 | CONFLICT (DMACC, DMACC); | |
1534 | ||
1535 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1536 | CONFLICT (MACC, MTHILO); | |
1537 | CONFLICT (DMACC, MTHILO); | |
1538 | ||
1539 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1540 | instruction is executed immediately after a MACC or DMACC | |
1541 | instruction, the result of [either instruction] is incorrect." */ | |
1542 | CONFLICT (MACC, MULT); | |
1543 | CONFLICT (MACC, DMULT); | |
1544 | CONFLICT (DMACC, MULT); | |
1545 | CONFLICT (DMACC, DMULT); | |
1546 | ||
1547 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1548 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1549 | DDIV or DDIVU instruction, the result of the MACC or | |
1550 | DMACC instruction is incorrect.". */ | |
1551 | CONFLICT (DMULT, MACC); | |
1552 | CONFLICT (DMULT, DMACC); | |
1553 | CONFLICT (DIV, MACC); | |
1554 | CONFLICT (DIV, DMACC); | |
1555 | ||
1556 | #undef CONFLICT | |
1557 | } | |
1558 | ||
707bfff6 TS |
1559 | struct regname { |
1560 | const char *name; | |
1561 | unsigned int num; | |
1562 | }; | |
1563 | ||
1564 | #define RTYPE_MASK 0x1ff00 | |
1565 | #define RTYPE_NUM 0x00100 | |
1566 | #define RTYPE_FPU 0x00200 | |
1567 | #define RTYPE_FCC 0x00400 | |
1568 | #define RTYPE_VEC 0x00800 | |
1569 | #define RTYPE_GP 0x01000 | |
1570 | #define RTYPE_CP0 0x02000 | |
1571 | #define RTYPE_PC 0x04000 | |
1572 | #define RTYPE_ACC 0x08000 | |
1573 | #define RTYPE_CCC 0x10000 | |
1574 | #define RNUM_MASK 0x000ff | |
1575 | #define RWARN 0x80000 | |
1576 | ||
1577 | #define GENERIC_REGISTER_NUMBERS \ | |
1578 | {"$0", RTYPE_NUM | 0}, \ | |
1579 | {"$1", RTYPE_NUM | 1}, \ | |
1580 | {"$2", RTYPE_NUM | 2}, \ | |
1581 | {"$3", RTYPE_NUM | 3}, \ | |
1582 | {"$4", RTYPE_NUM | 4}, \ | |
1583 | {"$5", RTYPE_NUM | 5}, \ | |
1584 | {"$6", RTYPE_NUM | 6}, \ | |
1585 | {"$7", RTYPE_NUM | 7}, \ | |
1586 | {"$8", RTYPE_NUM | 8}, \ | |
1587 | {"$9", RTYPE_NUM | 9}, \ | |
1588 | {"$10", RTYPE_NUM | 10}, \ | |
1589 | {"$11", RTYPE_NUM | 11}, \ | |
1590 | {"$12", RTYPE_NUM | 12}, \ | |
1591 | {"$13", RTYPE_NUM | 13}, \ | |
1592 | {"$14", RTYPE_NUM | 14}, \ | |
1593 | {"$15", RTYPE_NUM | 15}, \ | |
1594 | {"$16", RTYPE_NUM | 16}, \ | |
1595 | {"$17", RTYPE_NUM | 17}, \ | |
1596 | {"$18", RTYPE_NUM | 18}, \ | |
1597 | {"$19", RTYPE_NUM | 19}, \ | |
1598 | {"$20", RTYPE_NUM | 20}, \ | |
1599 | {"$21", RTYPE_NUM | 21}, \ | |
1600 | {"$22", RTYPE_NUM | 22}, \ | |
1601 | {"$23", RTYPE_NUM | 23}, \ | |
1602 | {"$24", RTYPE_NUM | 24}, \ | |
1603 | {"$25", RTYPE_NUM | 25}, \ | |
1604 | {"$26", RTYPE_NUM | 26}, \ | |
1605 | {"$27", RTYPE_NUM | 27}, \ | |
1606 | {"$28", RTYPE_NUM | 28}, \ | |
1607 | {"$29", RTYPE_NUM | 29}, \ | |
1608 | {"$30", RTYPE_NUM | 30}, \ | |
1609 | {"$31", RTYPE_NUM | 31} | |
1610 | ||
1611 | #define FPU_REGISTER_NAMES \ | |
1612 | {"$f0", RTYPE_FPU | 0}, \ | |
1613 | {"$f1", RTYPE_FPU | 1}, \ | |
1614 | {"$f2", RTYPE_FPU | 2}, \ | |
1615 | {"$f3", RTYPE_FPU | 3}, \ | |
1616 | {"$f4", RTYPE_FPU | 4}, \ | |
1617 | {"$f5", RTYPE_FPU | 5}, \ | |
1618 | {"$f6", RTYPE_FPU | 6}, \ | |
1619 | {"$f7", RTYPE_FPU | 7}, \ | |
1620 | {"$f8", RTYPE_FPU | 8}, \ | |
1621 | {"$f9", RTYPE_FPU | 9}, \ | |
1622 | {"$f10", RTYPE_FPU | 10}, \ | |
1623 | {"$f11", RTYPE_FPU | 11}, \ | |
1624 | {"$f12", RTYPE_FPU | 12}, \ | |
1625 | {"$f13", RTYPE_FPU | 13}, \ | |
1626 | {"$f14", RTYPE_FPU | 14}, \ | |
1627 | {"$f15", RTYPE_FPU | 15}, \ | |
1628 | {"$f16", RTYPE_FPU | 16}, \ | |
1629 | {"$f17", RTYPE_FPU | 17}, \ | |
1630 | {"$f18", RTYPE_FPU | 18}, \ | |
1631 | {"$f19", RTYPE_FPU | 19}, \ | |
1632 | {"$f20", RTYPE_FPU | 20}, \ | |
1633 | {"$f21", RTYPE_FPU | 21}, \ | |
1634 | {"$f22", RTYPE_FPU | 22}, \ | |
1635 | {"$f23", RTYPE_FPU | 23}, \ | |
1636 | {"$f24", RTYPE_FPU | 24}, \ | |
1637 | {"$f25", RTYPE_FPU | 25}, \ | |
1638 | {"$f26", RTYPE_FPU | 26}, \ | |
1639 | {"$f27", RTYPE_FPU | 27}, \ | |
1640 | {"$f28", RTYPE_FPU | 28}, \ | |
1641 | {"$f29", RTYPE_FPU | 29}, \ | |
1642 | {"$f30", RTYPE_FPU | 30}, \ | |
1643 | {"$f31", RTYPE_FPU | 31} | |
1644 | ||
1645 | #define FPU_CONDITION_CODE_NAMES \ | |
1646 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1647 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1648 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1649 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1650 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1651 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1652 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1653 | {"$fcc7", RTYPE_FCC | 7} | |
1654 | ||
1655 | #define COPROC_CONDITION_CODE_NAMES \ | |
1656 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1657 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1658 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1659 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1660 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1661 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1662 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1663 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1664 | ||
1665 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1666 | {"$a4", RTYPE_GP | 8}, \ | |
1667 | {"$a5", RTYPE_GP | 9}, \ | |
1668 | {"$a6", RTYPE_GP | 10}, \ | |
1669 | {"$a7", RTYPE_GP | 11}, \ | |
1670 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1671 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1672 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1673 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1674 | {"$t0", RTYPE_GP | 12}, \ | |
1675 | {"$t1", RTYPE_GP | 13}, \ | |
1676 | {"$t2", RTYPE_GP | 14}, \ | |
1677 | {"$t3", RTYPE_GP | 15} | |
1678 | ||
1679 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1680 | {"$t0", RTYPE_GP | 8}, \ | |
1681 | {"$t1", RTYPE_GP | 9}, \ | |
1682 | {"$t2", RTYPE_GP | 10}, \ | |
1683 | {"$t3", RTYPE_GP | 11}, \ | |
1684 | {"$t4", RTYPE_GP | 12}, \ | |
1685 | {"$t5", RTYPE_GP | 13}, \ | |
1686 | {"$t6", RTYPE_GP | 14}, \ | |
1687 | {"$t7", RTYPE_GP | 15}, \ | |
1688 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1689 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1690 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1691 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
1692 | ||
1693 | /* Remaining symbolic register names */ | |
1694 | #define SYMBOLIC_REGISTER_NAMES \ | |
1695 | {"$zero", RTYPE_GP | 0}, \ | |
1696 | {"$at", RTYPE_GP | 1}, \ | |
1697 | {"$AT", RTYPE_GP | 1}, \ | |
1698 | {"$v0", RTYPE_GP | 2}, \ | |
1699 | {"$v1", RTYPE_GP | 3}, \ | |
1700 | {"$a0", RTYPE_GP | 4}, \ | |
1701 | {"$a1", RTYPE_GP | 5}, \ | |
1702 | {"$a2", RTYPE_GP | 6}, \ | |
1703 | {"$a3", RTYPE_GP | 7}, \ | |
1704 | {"$s0", RTYPE_GP | 16}, \ | |
1705 | {"$s1", RTYPE_GP | 17}, \ | |
1706 | {"$s2", RTYPE_GP | 18}, \ | |
1707 | {"$s3", RTYPE_GP | 19}, \ | |
1708 | {"$s4", RTYPE_GP | 20}, \ | |
1709 | {"$s5", RTYPE_GP | 21}, \ | |
1710 | {"$s6", RTYPE_GP | 22}, \ | |
1711 | {"$s7", RTYPE_GP | 23}, \ | |
1712 | {"$t8", RTYPE_GP | 24}, \ | |
1713 | {"$t9", RTYPE_GP | 25}, \ | |
1714 | {"$k0", RTYPE_GP | 26}, \ | |
1715 | {"$kt0", RTYPE_GP | 26}, \ | |
1716 | {"$k1", RTYPE_GP | 27}, \ | |
1717 | {"$kt1", RTYPE_GP | 27}, \ | |
1718 | {"$gp", RTYPE_GP | 28}, \ | |
1719 | {"$sp", RTYPE_GP | 29}, \ | |
1720 | {"$s8", RTYPE_GP | 30}, \ | |
1721 | {"$fp", RTYPE_GP | 30}, \ | |
1722 | {"$ra", RTYPE_GP | 31} | |
1723 | ||
1724 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
1725 | {"$pc", RTYPE_PC | 0} | |
1726 | ||
1727 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
1728 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
1729 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
1730 | {"$v2", RTYPE_VEC | 2}, \ | |
1731 | {"$v3", RTYPE_VEC | 3}, \ | |
1732 | {"$v4", RTYPE_VEC | 4}, \ | |
1733 | {"$v5", RTYPE_VEC | 5}, \ | |
1734 | {"$v6", RTYPE_VEC | 6}, \ | |
1735 | {"$v7", RTYPE_VEC | 7}, \ | |
1736 | {"$v8", RTYPE_VEC | 8}, \ | |
1737 | {"$v9", RTYPE_VEC | 9}, \ | |
1738 | {"$v10", RTYPE_VEC | 10}, \ | |
1739 | {"$v11", RTYPE_VEC | 11}, \ | |
1740 | {"$v12", RTYPE_VEC | 12}, \ | |
1741 | {"$v13", RTYPE_VEC | 13}, \ | |
1742 | {"$v14", RTYPE_VEC | 14}, \ | |
1743 | {"$v15", RTYPE_VEC | 15}, \ | |
1744 | {"$v16", RTYPE_VEC | 16}, \ | |
1745 | {"$v17", RTYPE_VEC | 17}, \ | |
1746 | {"$v18", RTYPE_VEC | 18}, \ | |
1747 | {"$v19", RTYPE_VEC | 19}, \ | |
1748 | {"$v20", RTYPE_VEC | 20}, \ | |
1749 | {"$v21", RTYPE_VEC | 21}, \ | |
1750 | {"$v22", RTYPE_VEC | 22}, \ | |
1751 | {"$v23", RTYPE_VEC | 23}, \ | |
1752 | {"$v24", RTYPE_VEC | 24}, \ | |
1753 | {"$v25", RTYPE_VEC | 25}, \ | |
1754 | {"$v26", RTYPE_VEC | 26}, \ | |
1755 | {"$v27", RTYPE_VEC | 27}, \ | |
1756 | {"$v28", RTYPE_VEC | 28}, \ | |
1757 | {"$v29", RTYPE_VEC | 29}, \ | |
1758 | {"$v30", RTYPE_VEC | 30}, \ | |
1759 | {"$v31", RTYPE_VEC | 31} | |
1760 | ||
1761 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
1762 | {"$ac0", RTYPE_ACC | 0}, \ | |
1763 | {"$ac1", RTYPE_ACC | 1}, \ | |
1764 | {"$ac2", RTYPE_ACC | 2}, \ | |
1765 | {"$ac3", RTYPE_ACC | 3} | |
1766 | ||
1767 | static const struct regname reg_names[] = { | |
1768 | GENERIC_REGISTER_NUMBERS, | |
1769 | FPU_REGISTER_NAMES, | |
1770 | FPU_CONDITION_CODE_NAMES, | |
1771 | COPROC_CONDITION_CODE_NAMES, | |
1772 | ||
1773 | /* The $txx registers depends on the abi, | |
1774 | these will be added later into the symbol table from | |
1775 | one of the tables below once mips_abi is set after | |
1776 | parsing of arguments from the command line. */ | |
1777 | SYMBOLIC_REGISTER_NAMES, | |
1778 | ||
1779 | MIPS16_SPECIAL_REGISTER_NAMES, | |
1780 | MDMX_VECTOR_REGISTER_NAMES, | |
1781 | MIPS_DSP_ACCUMULATOR_NAMES, | |
1782 | {0, 0} | |
1783 | }; | |
1784 | ||
1785 | static const struct regname reg_names_o32[] = { | |
1786 | O32_SYMBOLIC_REGISTER_NAMES, | |
1787 | {0, 0} | |
1788 | }; | |
1789 | ||
1790 | static const struct regname reg_names_n32n64[] = { | |
1791 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
1792 | {0, 0} | |
1793 | }; | |
1794 | ||
1795 | static int | |
1796 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
1797 | { | |
1798 | symbolS *symbolP; | |
1799 | char *e; | |
1800 | char save_c; | |
1801 | int reg = -1; | |
1802 | ||
1803 | /* Find end of name. */ | |
1804 | e = *s; | |
1805 | if (is_name_beginner (*e)) | |
1806 | ++e; | |
1807 | while (is_part_of_name (*e)) | |
1808 | ++e; | |
1809 | ||
1810 | /* Terminate name. */ | |
1811 | save_c = *e; | |
1812 | *e = '\0'; | |
1813 | ||
1814 | /* Look for a register symbol. */ | |
1815 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
1816 | { | |
1817 | int r = S_GET_VALUE (symbolP); | |
1818 | if (r & types) | |
1819 | reg = r & RNUM_MASK; | |
1820 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
1821 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
1822 | reg = (r & RNUM_MASK) - 2; | |
1823 | } | |
1824 | /* Else see if this is a register defined in an itbl entry. */ | |
1825 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
1826 | { | |
1827 | char *n = *s; | |
1828 | unsigned long r; | |
1829 | ||
1830 | if (*n == '$') | |
1831 | ++n; | |
1832 | if (itbl_get_reg_val (n, &r)) | |
1833 | reg = r & RNUM_MASK; | |
1834 | } | |
1835 | ||
1836 | /* Advance to next token if a register was recognised. */ | |
1837 | if (reg >= 0) | |
1838 | *s = e; | |
1839 | else if (types & RWARN) | |
20203fb9 | 1840 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
1841 | |
1842 | *e = save_c; | |
1843 | if (regnop) | |
1844 | *regnop = reg; | |
1845 | return reg >= 0; | |
1846 | } | |
1847 | ||
037b32b9 | 1848 | /* Return TRUE if opcode MO is valid on the currently selected ISA and |
f79e2745 | 1849 | architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ |
037b32b9 AN |
1850 | |
1851 | static bfd_boolean | |
f79e2745 | 1852 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
1853 | { |
1854 | int isa = mips_opts.isa; | |
1855 | int fp_s, fp_d; | |
1856 | ||
1857 | if (mips_opts.ase_mdmx) | |
1858 | isa |= INSN_MDMX; | |
1859 | if (mips_opts.ase_dsp) | |
1860 | isa |= INSN_DSP; | |
1861 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
1862 | isa |= INSN_DSP64; | |
1863 | if (mips_opts.ase_dspr2) | |
1864 | isa |= INSN_DSPR2; | |
1865 | if (mips_opts.ase_mt) | |
1866 | isa |= INSN_MT; | |
1867 | if (mips_opts.ase_mips3d) | |
1868 | isa |= INSN_MIPS3D; | |
1869 | if (mips_opts.ase_smartmips) | |
1870 | isa |= INSN_SMARTMIPS; | |
1871 | ||
b19e8a9b AN |
1872 | /* Don't accept instructions based on the ISA if the CPU does not implement |
1873 | all the coprocessor insns. */ | |
1874 | if (NO_ISA_COP (mips_opts.arch) | |
1875 | && COP_INSN (mo->pinfo)) | |
1876 | isa = 0; | |
1877 | ||
037b32b9 AN |
1878 | if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch)) |
1879 | return FALSE; | |
1880 | ||
1881 | /* Check whether the instruction or macro requires single-precision or | |
1882 | double-precision floating-point support. Note that this information is | |
1883 | stored differently in the opcode table for insns and macros. */ | |
1884 | if (mo->pinfo == INSN_MACRO) | |
1885 | { | |
1886 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
1887 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
1888 | } | |
1889 | else | |
1890 | { | |
1891 | fp_s = mo->pinfo & FP_S; | |
1892 | fp_d = mo->pinfo & FP_D; | |
1893 | } | |
1894 | ||
1895 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
1896 | return FALSE; | |
1897 | ||
1898 | if (fp_s && mips_opts.soft_float) | |
1899 | return FALSE; | |
1900 | ||
1901 | return TRUE; | |
1902 | } | |
1903 | ||
1904 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
1905 | selected ISA and architecture. */ | |
1906 | ||
1907 | static bfd_boolean | |
1908 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
1909 | { | |
1910 | return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE; | |
1911 | } | |
1912 | ||
707bfff6 TS |
1913 | /* This function is called once, at assembler startup time. It should set up |
1914 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 1915 | |
252b5132 | 1916 | void |
17a2f251 | 1917 | md_begin (void) |
252b5132 | 1918 | { |
3994f87e | 1919 | const char *retval = NULL; |
156c2f8b | 1920 | int i = 0; |
252b5132 | 1921 | int broken = 0; |
1f25f5d3 | 1922 | |
0a44bf69 RS |
1923 | if (mips_pic != NO_PIC) |
1924 | { | |
1925 | if (g_switch_seen && g_switch_value != 0) | |
1926 | as_bad (_("-G may not be used in position-independent code")); | |
1927 | g_switch_value = 0; | |
1928 | } | |
1929 | ||
fef14a42 | 1930 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1931 | as_warn (_("Could not set architecture and machine")); |
1932 | ||
252b5132 RH |
1933 | op_hash = hash_new (); |
1934 | ||
1935 | for (i = 0; i < NUMOPCODES;) | |
1936 | { | |
1937 | const char *name = mips_opcodes[i].name; | |
1938 | ||
17a2f251 | 1939 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1940 | if (retval != NULL) |
1941 | { | |
1942 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1943 | mips_opcodes[i].name, retval); | |
1944 | /* Probably a memory allocation problem? Give up now. */ | |
1945 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1946 | } | |
1947 | do | |
1948 | { | |
1949 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1950 | { | |
1951 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1952 | broken = 1; | |
1e915849 RS |
1953 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1954 | { | |
1955 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
1956 | if (mips_fix_loongson2f_nop) |
1957 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
1958 | nop_insn.fixed_p = 1; |
1959 | } | |
252b5132 RH |
1960 | } |
1961 | ++i; | |
1962 | } | |
1963 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1964 | } | |
1965 | ||
1966 | mips16_op_hash = hash_new (); | |
1967 | ||
1968 | i = 0; | |
1969 | while (i < bfd_mips16_num_opcodes) | |
1970 | { | |
1971 | const char *name = mips16_opcodes[i].name; | |
1972 | ||
17a2f251 | 1973 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1974 | if (retval != NULL) |
1975 | as_fatal (_("internal: can't hash `%s': %s"), | |
1976 | mips16_opcodes[i].name, retval); | |
1977 | do | |
1978 | { | |
1979 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1980 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1981 | != mips16_opcodes[i].match)) | |
1982 | { | |
1983 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1984 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1985 | broken = 1; | |
1986 | } | |
1e915849 RS |
1987 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1988 | { | |
1989 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1990 | mips16_nop_insn.fixed_p = 1; | |
1991 | } | |
252b5132 RH |
1992 | ++i; |
1993 | } | |
1994 | while (i < bfd_mips16_num_opcodes | |
1995 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1996 | } | |
1997 | ||
1998 | if (broken) | |
1999 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2000 | ||
2001 | /* We add all the general register names to the symbol table. This | |
2002 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
2003 | for (i = 0; reg_names[i].name; i++) |
2004 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 2005 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
2006 | &zero_address_frag)); |
2007 | if (HAVE_NEWABI) | |
2008 | for (i = 0; reg_names_n32n64[i].name; i++) | |
2009 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 2010 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 2011 | &zero_address_frag)); |
707bfff6 TS |
2012 | else |
2013 | for (i = 0; reg_names_o32[i].name; i++) | |
2014 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 2015 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 2016 | &zero_address_frag)); |
6047c971 | 2017 | |
7d10b47d | 2018 | mips_no_prev_insn (); |
252b5132 RH |
2019 | |
2020 | mips_gprmask = 0; | |
2021 | mips_cprmask[0] = 0; | |
2022 | mips_cprmask[1] = 0; | |
2023 | mips_cprmask[2] = 0; | |
2024 | mips_cprmask[3] = 0; | |
2025 | ||
2026 | /* set the default alignment for the text section (2**2) */ | |
2027 | record_alignment (text_section, 2); | |
2028 | ||
4d0d148d | 2029 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2030 | |
707bfff6 | 2031 | #ifdef OBJ_ELF |
f43abd2b | 2032 | if (IS_ELF) |
252b5132 | 2033 | { |
0a44bf69 RS |
2034 | /* On a native system other than VxWorks, sections must be aligned |
2035 | to 16 byte boundaries. When configured for an embedded ELF | |
2036 | target, we don't bother. */ | |
c41e87e3 CF |
2037 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
2038 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
2039 | { |
2040 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2041 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2042 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2043 | } | |
2044 | ||
2045 | /* Create a .reginfo section for register masks and a .mdebug | |
2046 | section for debugging information. */ | |
2047 | { | |
2048 | segT seg; | |
2049 | subsegT subseg; | |
2050 | flagword flags; | |
2051 | segT sec; | |
2052 | ||
2053 | seg = now_seg; | |
2054 | subseg = now_subseg; | |
2055 | ||
2056 | /* The ABI says this section should be loaded so that the | |
2057 | running program can access it. However, we don't load it | |
2058 | if we are configured for an embedded target */ | |
2059 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2060 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2061 | flags |= SEC_ALLOC | SEC_LOAD; |
2062 | ||
316f5878 | 2063 | if (mips_abi != N64_ABI) |
252b5132 RH |
2064 | { |
2065 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2066 | ||
195325d2 TS |
2067 | bfd_set_section_flags (stdoutput, sec, flags); |
2068 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2069 | |
252b5132 | 2070 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2071 | } |
2072 | else | |
2073 | { | |
2074 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2075 | .reginfo section. */ | |
2076 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2077 | bfd_set_section_flags (stdoutput, sec, flags); |
2078 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2079 | |
252b5132 RH |
2080 | /* Set up the option header. */ |
2081 | { | |
2082 | Elf_Internal_Options opthdr; | |
2083 | char *f; | |
2084 | ||
2085 | opthdr.kind = ODK_REGINFO; | |
2086 | opthdr.size = (sizeof (Elf_External_Options) | |
2087 | + sizeof (Elf64_External_RegInfo)); | |
2088 | opthdr.section = 0; | |
2089 | opthdr.info = 0; | |
2090 | f = frag_more (sizeof (Elf_External_Options)); | |
2091 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2092 | (Elf_External_Options *) f); | |
2093 | ||
2094 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2095 | } | |
252b5132 RH |
2096 | } |
2097 | ||
2098 | if (ECOFF_DEBUGGING) | |
2099 | { | |
2100 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2101 | (void) bfd_set_section_flags (stdoutput, sec, | |
2102 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2103 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2104 | } | |
f43abd2b | 2105 | else if (mips_flag_pdr) |
ecb4347a DJ |
2106 | { |
2107 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2108 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2109 | SEC_READONLY | SEC_RELOC | |
2110 | | SEC_DEBUGGING); | |
2111 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2112 | } | |
252b5132 RH |
2113 | |
2114 | subseg_set (seg, subseg); | |
2115 | } | |
2116 | } | |
707bfff6 | 2117 | #endif /* OBJ_ELF */ |
252b5132 RH |
2118 | |
2119 | if (! ECOFF_DEBUGGING) | |
2120 | md_obj_begin (); | |
71400594 RS |
2121 | |
2122 | if (mips_fix_vr4120) | |
2123 | init_vr4120_conflicts (); | |
252b5132 RH |
2124 | } |
2125 | ||
2126 | void | |
17a2f251 | 2127 | md_mips_end (void) |
252b5132 | 2128 | { |
02b1ab82 | 2129 | mips_emit_delays (); |
252b5132 RH |
2130 | if (! ECOFF_DEBUGGING) |
2131 | md_obj_end (); | |
2132 | } | |
2133 | ||
2134 | void | |
17a2f251 | 2135 | md_assemble (char *str) |
252b5132 RH |
2136 | { |
2137 | struct mips_cl_insn insn; | |
f6688943 TS |
2138 | bfd_reloc_code_real_type unused_reloc[3] |
2139 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2140 | |
2141 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2142 | imm2_expr.X_op = O_absent; |
252b5132 | 2143 | offset_expr.X_op = O_absent; |
f6688943 TS |
2144 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2145 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2146 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2147 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2148 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2149 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2150 | |
2151 | if (mips_opts.mips16) | |
2152 | mips16_ip (str, &insn); | |
2153 | else | |
2154 | { | |
2155 | mips_ip (str, &insn); | |
beae10d5 KH |
2156 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2157 | str, insn.insn_opcode)); | |
252b5132 RH |
2158 | } |
2159 | ||
2160 | if (insn_error) | |
2161 | { | |
2162 | as_bad ("%s `%s'", insn_error, str); | |
2163 | return; | |
2164 | } | |
2165 | ||
2166 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
2167 | { | |
584892a6 | 2168 | macro_start (); |
252b5132 RH |
2169 | if (mips_opts.mips16) |
2170 | mips16_macro (&insn); | |
2171 | else | |
2172 | macro (&insn); | |
584892a6 | 2173 | macro_end (); |
252b5132 RH |
2174 | } |
2175 | else | |
2176 | { | |
2177 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 2178 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 2179 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 2180 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 2181 | else |
4d7206a2 | 2182 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
2183 | } |
2184 | } | |
2185 | ||
738e5348 RS |
2186 | /* Convenience functions for abstracting away the differences between |
2187 | MIPS16 and non-MIPS16 relocations. */ | |
2188 | ||
2189 | static inline bfd_boolean | |
2190 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2191 | { | |
2192 | switch (reloc) | |
2193 | { | |
2194 | case BFD_RELOC_MIPS16_JMP: | |
2195 | case BFD_RELOC_MIPS16_GPREL: | |
2196 | case BFD_RELOC_MIPS16_GOT16: | |
2197 | case BFD_RELOC_MIPS16_CALL16: | |
2198 | case BFD_RELOC_MIPS16_HI16_S: | |
2199 | case BFD_RELOC_MIPS16_HI16: | |
2200 | case BFD_RELOC_MIPS16_LO16: | |
2201 | return TRUE; | |
2202 | ||
2203 | default: | |
2204 | return FALSE; | |
2205 | } | |
2206 | } | |
2207 | ||
2208 | static inline bfd_boolean | |
2209 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2210 | { | |
2211 | return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16; | |
2212 | } | |
2213 | ||
2214 | static inline bfd_boolean | |
2215 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2216 | { | |
2217 | return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S; | |
2218 | } | |
2219 | ||
2220 | static inline bfd_boolean | |
2221 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2222 | { | |
2223 | return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16; | |
2224 | } | |
2225 | ||
5919d012 | 2226 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2227 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2228 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2229 | |
2230 | static inline bfd_boolean | |
17a2f251 | 2231 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2232 | { |
3b91255e | 2233 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2234 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2235 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2236 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2237 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2238 | } | |
2239 | ||
2240 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2241 | reloc_needs_lo_p. */ | |
2242 | ||
2243 | static inline bfd_reloc_code_real_type | |
2244 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2245 | { | |
2246 | return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16; | |
5919d012 RS |
2247 | } |
2248 | ||
2249 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2250 | relocation. */ | |
2251 | ||
2252 | static inline bfd_boolean | |
17a2f251 | 2253 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2254 | { |
2255 | return (fixp->fx_next != NULL | |
738e5348 | 2256 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2257 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2258 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2259 | } | |
2260 | ||
252b5132 RH |
2261 | /* This function returns true if modifying a register requires a |
2262 | delay. */ | |
2263 | ||
2264 | static int | |
17a2f251 | 2265 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2266 | { |
2267 | unsigned long prev_pinfo; | |
2268 | ||
47e39b9d | 2269 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2270 | if (! mips_opts.noreorder |
81912461 ILT |
2271 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2272 | && ! gpr_interlocks) | |
2273 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2274 | && ! cop_interlocks))) | |
252b5132 | 2275 | { |
81912461 ILT |
2276 | /* A load from a coprocessor or from memory. All load delays |
2277 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2278 | /* Itbl support may require additional care here. */ |
252b5132 | 2279 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 2280 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
2281 | return 1; |
2282 | } | |
2283 | ||
2284 | return 0; | |
2285 | } | |
2286 | ||
404a8071 RS |
2287 | /* Move all labels in insn_labels to the current insertion point. */ |
2288 | ||
2289 | static void | |
2290 | mips_move_labels (void) | |
2291 | { | |
a8dbcb85 | 2292 | segment_info_type *si = seg_info (now_seg); |
404a8071 RS |
2293 | struct insn_label_list *l; |
2294 | valueT val; | |
2295 | ||
a8dbcb85 | 2296 | for (l = si->label_list; l != NULL; l = l->next) |
404a8071 | 2297 | { |
9c2799c2 | 2298 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
2299 | symbol_set_frag (l->label, frag_now); |
2300 | val = (valueT) frag_now_fix (); | |
2301 | /* mips16 text labels are stored as odd. */ | |
2302 | if (mips_opts.mips16) | |
2303 | ++val; | |
2304 | S_SET_VALUE (l->label, val); | |
2305 | } | |
2306 | } | |
2307 | ||
5f0fe04b TS |
2308 | static bfd_boolean |
2309 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2310 | { | |
2311 | bfd_boolean linkonce = FALSE; | |
2312 | segT symseg = S_GET_SEGMENT (sym); | |
2313 | ||
2314 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2315 | { | |
2316 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2317 | linkonce = TRUE; | |
2318 | #ifdef OBJ_ELF | |
2319 | /* The GNU toolchain uses an extension for ELF: a section | |
2320 | beginning with the magic string .gnu.linkonce is a | |
2321 | linkonce section. */ | |
2322 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2323 | sizeof ".gnu.linkonce" - 1) == 0) | |
2324 | linkonce = TRUE; | |
2325 | #endif | |
2326 | } | |
2327 | return linkonce; | |
2328 | } | |
2329 | ||
252b5132 RH |
2330 | /* Mark instruction labels in mips16 mode. This permits the linker to |
2331 | handle them specially, such as generating jalx instructions when | |
2332 | needed. We also make them odd for the duration of the assembly, in | |
2333 | order to generate the right sort of code. We will make them even | |
2334 | in the adjust_symtab routine, while leaving them marked. This is | |
2335 | convenient for the debugger and the disassembler. The linker knows | |
2336 | to make them odd again. */ | |
2337 | ||
2338 | static void | |
17a2f251 | 2339 | mips16_mark_labels (void) |
252b5132 | 2340 | { |
a8dbcb85 TS |
2341 | segment_info_type *si = seg_info (now_seg); |
2342 | struct insn_label_list *l; | |
252b5132 | 2343 | |
a8dbcb85 TS |
2344 | if (!mips_opts.mips16) |
2345 | return; | |
2346 | ||
2347 | for (l = si->label_list; l != NULL; l = l->next) | |
2348 | { | |
2349 | symbolS *label = l->label; | |
2350 | ||
2351 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
f43abd2b | 2352 | if (IS_ELF) |
30c09090 | 2353 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); |
252b5132 | 2354 | #endif |
5f0fe04b TS |
2355 | if ((S_GET_VALUE (label) & 1) == 0 |
2356 | /* Don't adjust the address if the label is global or weak, or | |
2357 | in a link-once section, since we'll be emitting symbol reloc | |
2358 | references to it which will be patched up by the linker, and | |
2359 | the final value of the symbol may or may not be MIPS16. */ | |
2360 | && ! S_IS_WEAK (label) | |
2361 | && ! S_IS_EXTERNAL (label) | |
2362 | && ! s_is_linkonce (label, now_seg)) | |
a8dbcb85 | 2363 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); |
252b5132 RH |
2364 | } |
2365 | } | |
2366 | ||
4d7206a2 RS |
2367 | /* End the current frag. Make it a variant frag and record the |
2368 | relaxation info. */ | |
2369 | ||
2370 | static void | |
2371 | relax_close_frag (void) | |
2372 | { | |
584892a6 | 2373 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2374 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2375 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2376 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2377 | ||
2378 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2379 | mips_relax.first_fixup = 0; | |
2380 | } | |
2381 | ||
2382 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2383 | See the comment above RELAX_ENCODE for more details. */ | |
2384 | ||
2385 | static void | |
2386 | relax_start (symbolS *symbol) | |
2387 | { | |
9c2799c2 | 2388 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
2389 | mips_relax.sequence = 1; |
2390 | mips_relax.symbol = symbol; | |
2391 | } | |
2392 | ||
2393 | /* Start generating the second version of a relaxable sequence. | |
2394 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2395 | |
2396 | static void | |
4d7206a2 RS |
2397 | relax_switch (void) |
2398 | { | |
9c2799c2 | 2399 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
2400 | mips_relax.sequence = 2; |
2401 | } | |
2402 | ||
2403 | /* End the current relaxable sequence. */ | |
2404 | ||
2405 | static void | |
2406 | relax_end (void) | |
2407 | { | |
9c2799c2 | 2408 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
2409 | relax_close_frag (); |
2410 | mips_relax.sequence = 0; | |
2411 | } | |
2412 | ||
4c260379 RS |
2413 | /* Return the mask of core registers that IP reads. */ |
2414 | ||
2415 | static unsigned int | |
2416 | gpr_read_mask (const struct mips_cl_insn *ip) | |
2417 | { | |
2418 | unsigned long pinfo, pinfo2; | |
2419 | unsigned int mask; | |
2420 | ||
2421 | mask = 0; | |
2422 | pinfo = ip->insn_mo->pinfo; | |
2423 | pinfo2 = ip->insn_mo->pinfo2; | |
2424 | if (mips_opts.mips16) | |
2425 | { | |
2426 | if (pinfo & MIPS16_INSN_READ_X) | |
2427 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
2428 | if (pinfo & MIPS16_INSN_READ_Y) | |
2429 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
2430 | if (pinfo & MIPS16_INSN_READ_T) | |
2431 | mask |= 1 << TREG; | |
2432 | if (pinfo & MIPS16_INSN_READ_SP) | |
2433 | mask |= 1 << SP; | |
2434 | if (pinfo & MIPS16_INSN_READ_31) | |
2435 | mask |= 1 << RA; | |
2436 | if (pinfo & MIPS16_INSN_READ_Z) | |
2437 | mask |= 1 << (mips16_to_32_reg_map | |
2438 | [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]); | |
2439 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2440 | mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); | |
2441 | } | |
2442 | else | |
2443 | { | |
2444 | if (pinfo2 & INSN2_READ_GPR_D) | |
2445 | mask |= 1 << EXTRACT_OPERAND (RD, *ip); | |
2446 | if (pinfo & INSN_READ_GPR_T) | |
2447 | mask |= 1 << EXTRACT_OPERAND (RT, *ip); | |
2448 | if (pinfo & INSN_READ_GPR_S) | |
2449 | mask |= 1 << EXTRACT_OPERAND (RS, *ip); | |
2450 | if (pinfo2 & INSN2_READ_GPR_Z) | |
2451 | mask |= 1 << EXTRACT_OPERAND (RZ, *ip); | |
2452 | } | |
2453 | return mask & ~0; | |
2454 | } | |
2455 | ||
2456 | /* Return the mask of core registers that IP writes. */ | |
2457 | ||
2458 | static unsigned int | |
2459 | gpr_write_mask (const struct mips_cl_insn *ip) | |
2460 | { | |
2461 | unsigned long pinfo, pinfo2; | |
2462 | unsigned int mask; | |
2463 | ||
2464 | mask = 0; | |
2465 | pinfo = ip->insn_mo->pinfo; | |
2466 | pinfo2 = ip->insn_mo->pinfo2; | |
2467 | if (mips_opts.mips16) | |
2468 | { | |
2469 | if (pinfo & MIPS16_INSN_WRITE_X) | |
2470 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
2471 | if (pinfo & MIPS16_INSN_WRITE_Y) | |
2472 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
2473 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2474 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)]; | |
2475 | if (pinfo & MIPS16_INSN_WRITE_T) | |
2476 | mask |= 1 << TREG; | |
2477 | if (pinfo & MIPS16_INSN_WRITE_SP) | |
2478 | mask |= 1 << SP; | |
2479 | if (pinfo & MIPS16_INSN_WRITE_31) | |
2480 | mask |= 1 << RA; | |
2481 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2482 | mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2483 | } | |
2484 | else | |
2485 | { | |
2486 | if (pinfo & INSN_WRITE_GPR_D) | |
2487 | mask |= 1 << EXTRACT_OPERAND (RD, *ip); | |
2488 | if (pinfo & INSN_WRITE_GPR_T) | |
2489 | mask |= 1 << EXTRACT_OPERAND (RT, *ip); | |
2490 | if (pinfo & INSN_WRITE_GPR_31) | |
2491 | mask |= 1 << RA; | |
2492 | if (pinfo2 & INSN2_WRITE_GPR_Z) | |
2493 | mask |= 1 << EXTRACT_OPERAND (RZ, *ip); | |
2494 | } | |
2495 | return mask & ~0; | |
2496 | } | |
2497 | ||
2498 | /* Return the mask of floating-point registers that IP reads. */ | |
2499 | ||
2500 | static unsigned int | |
2501 | fpr_read_mask (const struct mips_cl_insn *ip) | |
2502 | { | |
2503 | unsigned long pinfo, pinfo2; | |
2504 | unsigned int mask; | |
2505 | ||
2506 | mask = 0; | |
2507 | pinfo = ip->insn_mo->pinfo; | |
2508 | pinfo2 = ip->insn_mo->pinfo2; | |
2509 | if (!mips_opts.mips16) | |
2510 | { | |
2511 | if (pinfo & INSN_READ_FPR_S) | |
2512 | mask |= 1 << EXTRACT_OPERAND (FS, *ip); | |
2513 | if (pinfo & INSN_READ_FPR_T) | |
2514 | mask |= 1 << EXTRACT_OPERAND (FT, *ip); | |
2515 | if (pinfo & INSN_READ_FPR_R) | |
2516 | mask |= 1 << EXTRACT_OPERAND (FR, *ip); | |
2517 | if (pinfo2 & INSN2_READ_FPR_Z) | |
2518 | mask |= 1 << EXTRACT_OPERAND (FZ, *ip); | |
2519 | } | |
2520 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
2521 | (This is overly pessimistic for things like cvt.d.s.) */ | |
2522 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
2523 | mask |= mask << 1; | |
2524 | return mask; | |
2525 | } | |
2526 | ||
2527 | /* Return the mask of floating-point registers that IP writes. */ | |
2528 | ||
2529 | static unsigned int | |
2530 | fpr_write_mask (const struct mips_cl_insn *ip) | |
2531 | { | |
2532 | unsigned long pinfo, pinfo2; | |
2533 | unsigned int mask; | |
2534 | ||
2535 | mask = 0; | |
2536 | pinfo = ip->insn_mo->pinfo; | |
2537 | pinfo2 = ip->insn_mo->pinfo2; | |
2538 | if (!mips_opts.mips16) | |
2539 | { | |
2540 | if (pinfo & INSN_WRITE_FPR_D) | |
2541 | mask |= 1 << EXTRACT_OPERAND (FD, *ip); | |
2542 | if (pinfo & INSN_WRITE_FPR_S) | |
2543 | mask |= 1 << EXTRACT_OPERAND (FS, *ip); | |
2544 | if (pinfo & INSN_WRITE_FPR_T) | |
2545 | mask |= 1 << EXTRACT_OPERAND (FT, *ip); | |
2546 | if (pinfo2 & INSN2_WRITE_FPR_Z) | |
2547 | mask |= 1 << EXTRACT_OPERAND (FZ, *ip); | |
2548 | } | |
2549 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
2550 | (This is overly pessimistic for things like cvt.s.d.) */ | |
2551 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
2552 | mask |= mask << 1; | |
2553 | return mask; | |
2554 | } | |
2555 | ||
71400594 RS |
2556 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
2557 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
2558 | by VR4120 errata. */ | |
4d7206a2 | 2559 | |
71400594 RS |
2560 | static unsigned int |
2561 | classify_vr4120_insn (const char *name) | |
252b5132 | 2562 | { |
71400594 RS |
2563 | if (strncmp (name, "macc", 4) == 0) |
2564 | return FIX_VR4120_MACC; | |
2565 | if (strncmp (name, "dmacc", 5) == 0) | |
2566 | return FIX_VR4120_DMACC; | |
2567 | if (strncmp (name, "mult", 4) == 0) | |
2568 | return FIX_VR4120_MULT; | |
2569 | if (strncmp (name, "dmult", 5) == 0) | |
2570 | return FIX_VR4120_DMULT; | |
2571 | if (strstr (name, "div")) | |
2572 | return FIX_VR4120_DIV; | |
2573 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
2574 | return FIX_VR4120_MTHILO; | |
2575 | return NUM_FIX_VR4120_CLASSES; | |
2576 | } | |
252b5132 | 2577 | |
ff239038 CM |
2578 | #define INSN_ERET 0x42000018 |
2579 | #define INSN_DERET 0x4200001f | |
2580 | ||
71400594 RS |
2581 | /* Return the number of instructions that must separate INSN1 and INSN2, |
2582 | where INSN1 is the earlier instruction. Return the worst-case value | |
2583 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 2584 | |
71400594 RS |
2585 | static unsigned int |
2586 | insns_between (const struct mips_cl_insn *insn1, | |
2587 | const struct mips_cl_insn *insn2) | |
2588 | { | |
2589 | unsigned long pinfo1, pinfo2; | |
4c260379 | 2590 | unsigned int mask; |
71400594 RS |
2591 | |
2592 | /* This function needs to know which pinfo flags are set for INSN2 | |
2593 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
4c260379 RS |
2594 | the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2 |
2595 | will have every flag set and INSN2_USES_GPR will always return true. */ | |
71400594 RS |
2596 | pinfo1 = insn1->insn_mo->pinfo; |
2597 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 2598 | |
4c260379 RS |
2599 | #define INSN2_USES_GPR(REG) \ |
2600 | (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0) | |
71400594 RS |
2601 | |
2602 | /* For most targets, write-after-read dependencies on the HI and LO | |
2603 | registers must be separated by at least two instructions. */ | |
2604 | if (!hilo_interlocks) | |
252b5132 | 2605 | { |
71400594 RS |
2606 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
2607 | return 2; | |
2608 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
2609 | return 2; | |
2610 | } | |
2611 | ||
2612 | /* If we're working around r7000 errata, there must be two instructions | |
2613 | between an mfhi or mflo and any instruction that uses the result. */ | |
2614 | if (mips_7000_hilo_fix | |
2615 | && MF_HILO_INSN (pinfo1) | |
4c260379 | 2616 | && INSN2_USES_GPR (EXTRACT_OPERAND (RD, *insn1))) |
71400594 RS |
2617 | return 2; |
2618 | ||
ff239038 CM |
2619 | /* If we're working around 24K errata, one instruction is required |
2620 | if an ERET or DERET is followed by a branch instruction. */ | |
2621 | if (mips_fix_24k) | |
2622 | { | |
2623 | if (insn1->insn_opcode == INSN_ERET | |
2624 | || insn1->insn_opcode == INSN_DERET) | |
2625 | { | |
2626 | if (insn2 == NULL | |
2627 | || insn2->insn_opcode == INSN_ERET | |
2628 | || insn2->insn_opcode == INSN_DERET | |
2629 | || (insn2->insn_mo->pinfo | |
2630 | & (INSN_UNCOND_BRANCH_DELAY | |
2631 | | INSN_COND_BRANCH_DELAY | |
2632 | | INSN_COND_BRANCH_LIKELY)) != 0) | |
2633 | return 1; | |
2634 | } | |
2635 | } | |
2636 | ||
71400594 RS |
2637 | /* If working around VR4120 errata, check for combinations that need |
2638 | a single intervening instruction. */ | |
2639 | if (mips_fix_vr4120) | |
2640 | { | |
2641 | unsigned int class1, class2; | |
252b5132 | 2642 | |
71400594 RS |
2643 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
2644 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 2645 | { |
71400594 RS |
2646 | if (insn2 == NULL) |
2647 | return 1; | |
2648 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
2649 | if (vr4120_conflicts[class1] & (1 << class2)) | |
2650 | return 1; | |
252b5132 | 2651 | } |
71400594 RS |
2652 | } |
2653 | ||
2654 | if (!mips_opts.mips16) | |
2655 | { | |
2656 | /* Check for GPR or coprocessor load delays. All such delays | |
2657 | are on the RT register. */ | |
2658 | /* Itbl support may require additional care here. */ | |
2659 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
2660 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 2661 | { |
71400594 | 2662 | know (pinfo1 & INSN_WRITE_GPR_T); |
4c260379 | 2663 | if (INSN2_USES_GPR (EXTRACT_OPERAND (RT, *insn1))) |
71400594 RS |
2664 | return 1; |
2665 | } | |
2666 | ||
2667 | /* Check for generic coprocessor hazards. | |
2668 | ||
2669 | This case is not handled very well. There is no special | |
2670 | knowledge of CP0 handling, and the coprocessors other than | |
2671 | the floating point unit are not distinguished at all. */ | |
2672 | /* Itbl support may require additional care here. FIXME! | |
2673 | Need to modify this to include knowledge about | |
2674 | user specified delays! */ | |
2675 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
2676 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
2677 | { | |
2678 | /* Handle cases where INSN1 writes to a known general coprocessor | |
2679 | register. There must be a one instruction delay before INSN2 | |
2680 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
2681 | mask = fpr_write_mask (insn1); |
2682 | if (mask != 0) | |
252b5132 | 2683 | { |
4c260379 | 2684 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 2685 | return 1; |
252b5132 RH |
2686 | } |
2687 | else | |
2688 | { | |
71400594 RS |
2689 | /* Read-after-write dependencies on the control registers |
2690 | require a two-instruction gap. */ | |
2691 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
2692 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2693 | return 2; | |
2694 | ||
2695 | /* We don't know exactly what INSN1 does. If INSN2 is | |
2696 | also a coprocessor instruction, assume there must be | |
2697 | a one instruction gap. */ | |
2698 | if (pinfo2 & INSN_COP) | |
2699 | return 1; | |
252b5132 RH |
2700 | } |
2701 | } | |
6b76fefe | 2702 | |
71400594 RS |
2703 | /* Check for read-after-write dependencies on the coprocessor |
2704 | control registers in cases where INSN1 does not need a general | |
2705 | coprocessor delay. This means that INSN1 is a floating point | |
2706 | comparison instruction. */ | |
2707 | /* Itbl support may require additional care here. */ | |
2708 | else if (!cop_interlocks | |
2709 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2710 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2711 | return 1; | |
2712 | } | |
6b76fefe | 2713 | |
4c260379 | 2714 | #undef INSN2_USES_GPR |
6b76fefe | 2715 | |
71400594 RS |
2716 | return 0; |
2717 | } | |
6b76fefe | 2718 | |
7d8e00cf RS |
2719 | /* Return the number of nops that would be needed to work around the |
2720 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
2721 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
2722 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
2723 | |
2724 | static int | |
932d1a1b | 2725 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
2726 | const struct mips_cl_insn *insn) |
2727 | { | |
4c260379 RS |
2728 | int i, j; |
2729 | unsigned int mask; | |
7d8e00cf RS |
2730 | |
2731 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2732 | are not affected by the errata. */ | |
2733 | if (insn != 0 | |
2734 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2735 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2736 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2737 | return 0; | |
2738 | ||
2739 | /* Search for the first MFLO or MFHI. */ | |
2740 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 2741 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
2742 | { |
2743 | /* Extract the destination register. */ | |
4c260379 | 2744 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
2745 | |
2746 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 2747 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
2748 | return 0; |
2749 | ||
2750 | /* ...or if any of the intervening instructions do. */ | |
2751 | for (j = 0; j < i; j++) | |
4c260379 | 2752 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
2753 | return 0; |
2754 | ||
932d1a1b RS |
2755 | if (i >= ignore) |
2756 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
2757 | } |
2758 | return 0; | |
2759 | } | |
2760 | ||
15be625d CM |
2761 | #define BASE_REG_EQ(INSN1, INSN2) \ |
2762 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
2763 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
2764 | ||
2765 | /* Return the minimum alignment for this store instruction. */ | |
2766 | ||
2767 | static int | |
2768 | fix_24k_align_to (const struct mips_opcode *mo) | |
2769 | { | |
2770 | if (strcmp (mo->name, "sh") == 0) | |
2771 | return 2; | |
2772 | ||
2773 | if (strcmp (mo->name, "swc1") == 0 | |
2774 | || strcmp (mo->name, "swc2") == 0 | |
2775 | || strcmp (mo->name, "sw") == 0 | |
2776 | || strcmp (mo->name, "sc") == 0 | |
2777 | || strcmp (mo->name, "s.s") == 0) | |
2778 | return 4; | |
2779 | ||
2780 | if (strcmp (mo->name, "sdc1") == 0 | |
2781 | || strcmp (mo->name, "sdc2") == 0 | |
2782 | || strcmp (mo->name, "s.d") == 0) | |
2783 | return 8; | |
2784 | ||
2785 | /* sb, swl, swr */ | |
2786 | return 1; | |
2787 | } | |
2788 | ||
2789 | struct fix_24k_store_info | |
2790 | { | |
2791 | /* Immediate offset, if any, for this store instruction. */ | |
2792 | short off; | |
2793 | /* Alignment required by this store instruction. */ | |
2794 | int align_to; | |
2795 | /* True for register offsets. */ | |
2796 | int register_offset; | |
2797 | }; | |
2798 | ||
2799 | /* Comparison function used by qsort. */ | |
2800 | ||
2801 | static int | |
2802 | fix_24k_sort (const void *a, const void *b) | |
2803 | { | |
2804 | const struct fix_24k_store_info *pos1 = a; | |
2805 | const struct fix_24k_store_info *pos2 = b; | |
2806 | ||
2807 | return (pos1->off - pos2->off); | |
2808 | } | |
2809 | ||
2810 | /* INSN is a store instruction. Try to record the store information | |
2811 | in STINFO. Return false if the information isn't known. */ | |
2812 | ||
2813 | static bfd_boolean | |
2814 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 2815 | const struct mips_cl_insn *insn) |
15be625d CM |
2816 | { |
2817 | /* The instruction must have a known offset. */ | |
2818 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
2819 | return FALSE; | |
2820 | ||
2821 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
2822 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
2823 | return TRUE; | |
2824 | } | |
2825 | ||
932d1a1b RS |
2826 | /* Return the number of nops that would be needed to work around the 24k |
2827 | "lost data on stores during refill" errata if instruction INSN | |
2828 | immediately followed the 2 instructions described by HIST. | |
2829 | Ignore hazards that are contained within the first IGNORE | |
2830 | instructions of HIST. | |
2831 | ||
2832 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
2833 | for the data cache refills and store data. The following describes | |
2834 | the scenario where the store data could be lost. | |
2835 | ||
2836 | * A data cache miss, due to either a load or a store, causing fill | |
2837 | data to be supplied by the memory subsystem | |
2838 | * The first three doublewords of fill data are returned and written | |
2839 | into the cache | |
2840 | * A sequence of four stores occurs in consecutive cycles around the | |
2841 | final doubleword of the fill: | |
2842 | * Store A | |
2843 | * Store B | |
2844 | * Store C | |
2845 | * Zero, One or more instructions | |
2846 | * Store D | |
2847 | ||
2848 | The four stores A-D must be to different doublewords of the line that | |
2849 | is being filled. The fourth instruction in the sequence above permits | |
2850 | the fill of the final doubleword to be transferred from the FSB into | |
2851 | the cache. In the sequence above, the stores may be either integer | |
2852 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
2853 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
2854 | different doublewords on the line. If the floating point unit is | |
2855 | running in 1:2 mode, it is not possible to create the sequence above | |
2856 | using only floating point store instructions. | |
15be625d CM |
2857 | |
2858 | In this case, the cache line being filled is incorrectly marked | |
2859 | invalid, thereby losing the data from any store to the line that | |
2860 | occurs between the original miss and the completion of the five | |
2861 | cycle sequence shown above. | |
2862 | ||
932d1a1b | 2863 | The workarounds are: |
15be625d | 2864 | |
932d1a1b RS |
2865 | * Run the data cache in write-through mode. |
2866 | * Insert a non-store instruction between | |
2867 | Store A and Store B or Store B and Store C. */ | |
15be625d CM |
2868 | |
2869 | static int | |
932d1a1b | 2870 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
2871 | const struct mips_cl_insn *insn) |
2872 | { | |
2873 | struct fix_24k_store_info pos[3]; | |
2874 | int align, i, base_offset; | |
2875 | ||
932d1a1b RS |
2876 | if (ignore >= 2) |
2877 | return 0; | |
2878 | ||
ab9794cf RS |
2879 | /* If the previous instruction wasn't a store, there's nothing to |
2880 | worry about. */ | |
15be625d CM |
2881 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
2882 | return 0; | |
2883 | ||
ab9794cf RS |
2884 | /* If the instructions after the previous one are unknown, we have |
2885 | to assume the worst. */ | |
2886 | if (!insn) | |
15be625d CM |
2887 | return 1; |
2888 | ||
ab9794cf RS |
2889 | /* Check whether we are dealing with three consecutive stores. */ |
2890 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
2891 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
2892 | return 0; |
2893 | ||
2894 | /* If we don't know the relationship between the store addresses, | |
2895 | assume the worst. */ | |
ab9794cf | 2896 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
2897 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
2898 | return 1; | |
2899 | ||
2900 | if (!fix_24k_record_store_info (&pos[0], insn) | |
2901 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
2902 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
2903 | return 1; | |
2904 | ||
2905 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
2906 | ||
2907 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
2908 | X bytes and such that the base register + X is known to be aligned | |
2909 | to align bytes. */ | |
2910 | ||
2911 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
2912 | align = 8; | |
2913 | else | |
2914 | { | |
2915 | align = pos[0].align_to; | |
2916 | base_offset = pos[0].off; | |
2917 | for (i = 1; i < 3; i++) | |
2918 | if (align < pos[i].align_to) | |
2919 | { | |
2920 | align = pos[i].align_to; | |
2921 | base_offset = pos[i].off; | |
2922 | } | |
2923 | for (i = 0; i < 3; i++) | |
2924 | pos[i].off -= base_offset; | |
2925 | } | |
2926 | ||
2927 | pos[0].off &= ~align + 1; | |
2928 | pos[1].off &= ~align + 1; | |
2929 | pos[2].off &= ~align + 1; | |
2930 | ||
2931 | /* If any two stores write to the same chunk, they also write to the | |
2932 | same doubleword. The offsets are still sorted at this point. */ | |
2933 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
2934 | return 0; | |
2935 | ||
2936 | /* A range of at least 9 bytes is needed for the stores to be in | |
2937 | non-overlapping doublewords. */ | |
2938 | if (pos[2].off - pos[0].off <= 8) | |
2939 | return 0; | |
2940 | ||
2941 | if (pos[2].off - pos[1].off >= 24 | |
2942 | || pos[1].off - pos[0].off >= 24 | |
2943 | || pos[2].off - pos[0].off >= 32) | |
2944 | return 0; | |
2945 | ||
2946 | return 1; | |
2947 | } | |
2948 | ||
71400594 | 2949 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 2950 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
2951 | where HIST[0] is the most recent instruction. Ignore hazards |
2952 | between INSN and the first IGNORE instructions in HIST. | |
2953 | ||
2954 | If INSN is null, return the worse-case number of nops for any | |
2955 | instruction. */ | |
bdaaa2e1 | 2956 | |
71400594 | 2957 | static int |
932d1a1b | 2958 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
2959 | const struct mips_cl_insn *insn) |
2960 | { | |
2961 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2962 | |
71400594 | 2963 | nops = 0; |
932d1a1b | 2964 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 2965 | { |
91d6fa6a | 2966 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
2967 | if (tmp_nops > nops) |
2968 | nops = tmp_nops; | |
2969 | } | |
7d8e00cf RS |
2970 | |
2971 | if (mips_fix_vr4130) | |
2972 | { | |
932d1a1b | 2973 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
2974 | if (tmp_nops > nops) |
2975 | nops = tmp_nops; | |
2976 | } | |
2977 | ||
15be625d CM |
2978 | if (mips_fix_24k) |
2979 | { | |
932d1a1b | 2980 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
2981 | if (tmp_nops > nops) |
2982 | nops = tmp_nops; | |
2983 | } | |
2984 | ||
71400594 RS |
2985 | return nops; |
2986 | } | |
252b5132 | 2987 | |
71400594 | 2988 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 2989 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
2990 | would be needed after the extended sequence, ignoring hazards |
2991 | in the first IGNORE instructions. */ | |
252b5132 | 2992 | |
71400594 | 2993 | static int |
932d1a1b RS |
2994 | nops_for_sequence (int num_insns, int ignore, |
2995 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
2996 | { |
2997 | va_list args; | |
2998 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2999 | struct mips_cl_insn *cursor; | |
3000 | int nops; | |
3001 | ||
91d6fa6a | 3002 | va_start (args, hist); |
71400594 | 3003 | cursor = buffer + num_insns; |
91d6fa6a | 3004 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
3005 | while (cursor > buffer) |
3006 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
3007 | ||
932d1a1b | 3008 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
3009 | va_end (args); |
3010 | return nops; | |
3011 | } | |
252b5132 | 3012 | |
71400594 RS |
3013 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
3014 | worst-case delay for the branch target. */ | |
252b5132 | 3015 | |
71400594 | 3016 | static int |
932d1a1b | 3017 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3018 | const struct mips_cl_insn *insn) |
3019 | { | |
3020 | int nops, tmp_nops; | |
60b63b72 | 3021 | |
932d1a1b | 3022 | nops = nops_for_insn (ignore, hist, insn); |
71400594 RS |
3023 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY |
3024 | | INSN_COND_BRANCH_DELAY | |
3025 | | INSN_COND_BRANCH_LIKELY)) | |
3026 | { | |
932d1a1b RS |
3027 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
3028 | hist, insn, NOP_INSN); | |
71400594 RS |
3029 | if (tmp_nops > nops) |
3030 | nops = tmp_nops; | |
3031 | } | |
9a2c7088 MR |
3032 | else if (mips_opts.mips16 |
3033 | && (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
3034 | | MIPS16_INSN_COND_BRANCH))) | |
71400594 | 3035 | { |
932d1a1b | 3036 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
3037 | if (tmp_nops > nops) |
3038 | nops = tmp_nops; | |
3039 | } | |
3040 | return nops; | |
3041 | } | |
3042 | ||
c67a084a NC |
3043 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
3044 | ||
3045 | static void | |
3046 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
3047 | { | |
3048 | if (strcmp (ip->insn_mo->name, "nop") == 0) | |
3049 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
3050 | } | |
3051 | ||
3052 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
3053 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
3054 | ||
3055 | static void | |
3056 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
3057 | { | |
3058 | if (strcmp (ip->insn_mo->name, "j") == 0 | |
3059 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
3060 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
3061 | { | |
3062 | int sreg; | |
3063 | expressionS ep; | |
3064 | ||
3065 | if (! mips_opts.at) | |
3066 | return; | |
3067 | ||
3068 | sreg = EXTRACT_OPERAND (RS, *ip); | |
3069 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) | |
3070 | return; | |
3071 | ||
3072 | ep.X_op = O_constant; | |
3073 | ep.X_add_number = 0xcfff0000; | |
3074 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
3075 | ep.X_add_number = 0xffff; | |
3076 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
3077 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
3078 | } | |
3079 | } | |
3080 | ||
3081 | static void | |
3082 | fix_loongson2f (struct mips_cl_insn * ip) | |
3083 | { | |
3084 | if (mips_fix_loongson2f_nop) | |
3085 | fix_loongson2f_nop (ip); | |
3086 | ||
3087 | if (mips_fix_loongson2f_jump) | |
3088 | fix_loongson2f_jump (ip); | |
3089 | } | |
3090 | ||
a4e06468 RS |
3091 | /* IP is a branch that has a delay slot, and we need to fill it |
3092 | automatically. Return true if we can do that by swapping IP | |
3093 | with the previous instruction. */ | |
3094 | ||
3095 | static bfd_boolean | |
3096 | can_swap_branch_p (struct mips_cl_insn *ip) | |
3097 | { | |
3098 | unsigned long pinfo, prev_pinfo; | |
3099 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; | |
3100 | ||
3101 | /* -O2 and above is required for this optimization. */ | |
3102 | if (mips_optimize < 2) | |
3103 | return FALSE; | |
3104 | ||
3105 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
3106 | if (mips_opts.nomove) | |
3107 | return FALSE; | |
3108 | ||
3109 | /* We can't swap if the previous instruction's position is fixed. */ | |
3110 | if (history[0].fixed_p) | |
3111 | return FALSE; | |
3112 | ||
3113 | /* If the previous previous insn was in a .set noreorder, we can't | |
3114 | swap. Actually, the MIPS assembler will swap in this situation. | |
3115 | However, gcc configured -with-gnu-as will generate code like | |
3116 | ||
3117 | .set noreorder | |
3118 | lw $4,XXX | |
3119 | .set reorder | |
3120 | INSN | |
3121 | bne $4,$0,foo | |
3122 | ||
3123 | in which we can not swap the bne and INSN. If gcc is not configured | |
3124 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
3125 | if (history[1].noreorder_p) | |
3126 | return FALSE; | |
3127 | ||
3128 | /* If the previous instruction had a fixup in mips16 mode, we can not | |
3129 | swap. This normally means that the previous instruction was a 4 | |
3130 | byte branch anyhow. */ | |
3131 | if (mips_opts.mips16 && history[0].fixp[0]) | |
3132 | return FALSE; | |
3133 | ||
3134 | /* If the branch is itself the target of a branch, we can not swap. | |
3135 | We cheat on this; all we check for is whether there is a label on | |
3136 | this instruction. If there are any branches to anything other than | |
3137 | a label, users must use .set noreorder. */ | |
3138 | if (seg_info (now_seg)->label_list) | |
3139 | return FALSE; | |
3140 | ||
3141 | /* If the previous instruction is in a variant frag other than this | |
3142 | branch's one, we cannot do the swap. This does not apply to the | |
3143 | mips16, which uses variant frags for different purposes. */ | |
3144 | if (!mips_opts.mips16 | |
3145 | && history[0].frag | |
3146 | && history[0].frag->fr_type == rs_machine_dependent) | |
3147 | return FALSE; | |
3148 | ||
3149 | /* We do not swap with a trap instruction, since it complicates trap | |
3150 | handlers to have the trap instruction be in a delay slot. */ | |
3151 | prev_pinfo = history[0].insn_mo->pinfo; | |
3152 | if (prev_pinfo & INSN_TRAP) | |
3153 | return FALSE; | |
3154 | ||
3155 | /* If the previous instruction is a sync, sync.l, or sync.p, we can | |
3156 | not swap. */ | |
3157 | if (prev_pinfo & INSN_SYNC) | |
3158 | return FALSE; | |
3159 | ||
3160 | /* If the previous instruction is an ERET or DERET, avoid the swap. */ | |
3161 | if (history[0].insn_opcode == INSN_ERET) | |
3162 | return FALSE; | |
3163 | if (history[0].insn_opcode == INSN_DERET) | |
3164 | return FALSE; | |
3165 | ||
3166 | /* Check for conflicts between the branch and the instructions | |
3167 | before the candidate delay slot. */ | |
3168 | if (nops_for_insn (0, history + 1, ip) > 0) | |
3169 | return FALSE; | |
3170 | ||
3171 | /* Check for conflicts between the swapped sequence and the | |
3172 | target of the branch. */ | |
3173 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
3174 | return FALSE; | |
3175 | ||
3176 | /* If the branch reads a register that the previous | |
3177 | instruction sets, we can not swap. */ | |
3178 | gpr_read = gpr_read_mask (ip); | |
3179 | prev_gpr_write = gpr_write_mask (&history[0]); | |
3180 | if (gpr_read & prev_gpr_write) | |
3181 | return FALSE; | |
3182 | ||
3183 | /* If the branch writes a register that the previous | |
3184 | instruction sets, we can not swap. */ | |
3185 | gpr_write = gpr_write_mask (ip); | |
3186 | if (gpr_write & prev_gpr_write) | |
3187 | return FALSE; | |
3188 | ||
3189 | /* If the branch writes a register that the previous | |
3190 | instruction reads, we can not swap. */ | |
3191 | prev_gpr_read = gpr_read_mask (&history[0]); | |
3192 | if (gpr_write & prev_gpr_read) | |
3193 | return FALSE; | |
3194 | ||
3195 | /* If one instruction sets a condition code and the | |
3196 | other one uses a condition code, we can not swap. */ | |
3197 | pinfo = ip->insn_mo->pinfo; | |
3198 | if ((pinfo & INSN_READ_COND_CODE) | |
3199 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3200 | return FALSE; | |
3201 | if ((pinfo & INSN_WRITE_COND_CODE) | |
3202 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3203 | return FALSE; | |
3204 | ||
3205 | /* If the previous instruction uses the PC, we can not swap. */ | |
3206 | if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
3207 | return FALSE; | |
3208 | ||
3209 | return TRUE; | |
3210 | } | |
3211 | ||
3212 | /* Decide how we should add IP to the instruction stream. */ | |
3213 | ||
3214 | static enum append_method | |
3215 | get_append_method (struct mips_cl_insn *ip) | |
3216 | { | |
3217 | unsigned long pinfo; | |
3218 | ||
3219 | /* The relaxed version of a macro sequence must be inherently | |
3220 | hazard-free. */ | |
3221 | if (mips_relax.sequence == 2) | |
3222 | return APPEND_ADD; | |
3223 | ||
3224 | /* We must not dabble with instructions in a ".set norerorder" block. */ | |
3225 | if (mips_opts.noreorder) | |
3226 | return APPEND_ADD; | |
3227 | ||
3228 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
3229 | pinfo = ip->insn_mo->pinfo; | |
3230 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3231 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
3232 | { | |
3233 | if (can_swap_branch_p (ip)) | |
3234 | return APPEND_SWAP; | |
3235 | ||
3236 | if (mips_opts.mips16 | |
3237 | && ISA_SUPPORTS_MIPS16E | |
3238 | && (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3239 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))) | |
3240 | return APPEND_ADD_COMPACT; | |
3241 | ||
3242 | return APPEND_ADD_WITH_NOP; | |
3243 | } | |
3244 | ||
3245 | /* We don't bother trying to track the target of branches, so there's | |
3246 | nothing we can use to fill a branch-likely slot. */ | |
3247 | if (pinfo & INSN_COND_BRANCH_LIKELY) | |
3248 | return APPEND_ADD_WITH_NOP; | |
3249 | ||
3250 | return APPEND_ADD; | |
3251 | } | |
3252 | ||
ceb94aa5 RS |
3253 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
3254 | Point IP->insn_mo to the new opcode's definition. */ | |
3255 | ||
3256 | static void | |
3257 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
3258 | { | |
3259 | const struct mips_opcode *mo, *end; | |
3260 | ||
3261 | end = &mips16_opcodes[bfd_mips16_num_opcodes]; | |
3262 | for (mo = ip->insn_mo; mo < end; mo++) | |
3263 | if ((ip->insn_opcode & mo->mask) == mo->match) | |
3264 | { | |
3265 | ip->insn_mo = mo; | |
3266 | return; | |
3267 | } | |
3268 | abort (); | |
3269 | } | |
3270 | ||
71400594 RS |
3271 | /* Output an instruction. IP is the instruction information. |
3272 | ADDRESS_EXPR is an operand of the instruction to be used with | |
3273 | RELOC_TYPE. */ | |
3274 | ||
3275 | static void | |
3276 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
3277 | bfd_reloc_code_real_type *reloc_type) | |
3278 | { | |
3994f87e | 3279 | unsigned long prev_pinfo, pinfo; |
98675402 | 3280 | unsigned long prev_pinfo2, pinfo2; |
71400594 | 3281 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 3282 | enum append_method method; |
71400594 | 3283 | |
c67a084a NC |
3284 | if (mips_fix_loongson2f) |
3285 | fix_loongson2f (ip); | |
3286 | ||
71400594 RS |
3287 | /* Mark instruction labels in mips16 mode. */ |
3288 | mips16_mark_labels (); | |
3289 | ||
738f4d98 MR |
3290 | file_ase_mips16 |= mips_opts.mips16; |
3291 | ||
71400594 | 3292 | prev_pinfo = history[0].insn_mo->pinfo; |
98675402 | 3293 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 3294 | pinfo = ip->insn_mo->pinfo; |
98675402 | 3295 | pinfo2 = ip->insn_mo->pinfo2; |
71400594 | 3296 | |
15be625d CM |
3297 | if (address_expr == NULL) |
3298 | ip->complete_p = 1; | |
3299 | else if (*reloc_type <= BFD_RELOC_UNUSED | |
3300 | && address_expr->X_op == O_constant) | |
3301 | { | |
3302 | unsigned int tmp; | |
3303 | ||
3304 | ip->complete_p = 1; | |
3305 | switch (*reloc_type) | |
3306 | { | |
3307 | case BFD_RELOC_32: | |
3308 | ip->insn_opcode |= address_expr->X_add_number; | |
3309 | break; | |
3310 | ||
3311 | case BFD_RELOC_MIPS_HIGHEST: | |
3312 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; | |
3313 | ip->insn_opcode |= tmp & 0xffff; | |
3314 | break; | |
3315 | ||
3316 | case BFD_RELOC_MIPS_HIGHER: | |
3317 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; | |
3318 | ip->insn_opcode |= tmp & 0xffff; | |
3319 | break; | |
3320 | ||
3321 | case BFD_RELOC_HI16_S: | |
3322 | tmp = (address_expr->X_add_number + 0x8000) >> 16; | |
3323 | ip->insn_opcode |= tmp & 0xffff; | |
3324 | break; | |
3325 | ||
3326 | case BFD_RELOC_HI16: | |
3327 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
3328 | break; | |
3329 | ||
3330 | case BFD_RELOC_UNUSED: | |
3331 | case BFD_RELOC_LO16: | |
3332 | case BFD_RELOC_MIPS_GOT_DISP: | |
3333 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; | |
3334 | break; | |
3335 | ||
3336 | case BFD_RELOC_MIPS_JMP: | |
3337 | if ((address_expr->X_add_number & 3) != 0) | |
3338 | as_bad (_("jump to misaligned address (0x%lx)"), | |
3339 | (unsigned long) address_expr->X_add_number); | |
3340 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
3341 | ip->complete_p = 0; | |
3342 | break; | |
3343 | ||
3344 | case BFD_RELOC_MIPS16_JMP: | |
3345 | if ((address_expr->X_add_number & 3) != 0) | |
3346 | as_bad (_("jump to misaligned address (0x%lx)"), | |
3347 | (unsigned long) address_expr->X_add_number); | |
3348 | ip->insn_opcode |= | |
3349 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
3350 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
3351 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
3352 | ip->complete_p = 0; | |
3353 | break; | |
3354 | ||
3355 | case BFD_RELOC_16_PCREL_S2: | |
3356 | if ((address_expr->X_add_number & 3) != 0) | |
3357 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3358 | (unsigned long) address_expr->X_add_number); | |
9fe77896 RS |
3359 | if (!mips_relax_branch) |
3360 | { | |
3361 | if ((address_expr->X_add_number + 0x20000) & ~0x3ffff) | |
3362 | as_bad (_("branch address range overflow (0x%lx)"), | |
3363 | (unsigned long) address_expr->X_add_number); | |
3364 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff; | |
3365 | } | |
15be625d CM |
3366 | ip->complete_p = 0; |
3367 | break; | |
3368 | ||
3369 | default: | |
3370 | internalError (); | |
3371 | } | |
3372 | } | |
3373 | ||
71400594 RS |
3374 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
3375 | { | |
3376 | /* There are a lot of optimizations we could do that we don't. | |
3377 | In particular, we do not, in general, reorder instructions. | |
3378 | If you use gcc with optimization, it will reorder | |
3379 | instructions and generally do much more optimization then we | |
3380 | do here; repeating all that work in the assembler would only | |
3381 | benefit hand written assembly code, and does not seem worth | |
3382 | it. */ | |
3383 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
3384 | ? nops_for_insn (0, history, NULL) |
3385 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 3386 | if (nops > 0) |
252b5132 RH |
3387 | { |
3388 | fragS *old_frag; | |
3389 | unsigned long old_frag_offset; | |
3390 | int i; | |
252b5132 RH |
3391 | |
3392 | old_frag = frag_now; | |
3393 | old_frag_offset = frag_now_fix (); | |
3394 | ||
3395 | for (i = 0; i < nops; i++) | |
3396 | emit_nop (); | |
3397 | ||
3398 | if (listing) | |
3399 | { | |
3400 | listing_prev_line (); | |
3401 | /* We may be at the start of a variant frag. In case we | |
3402 | are, make sure there is enough space for the frag | |
3403 | after the frags created by listing_prev_line. The | |
3404 | argument to frag_grow here must be at least as large | |
3405 | as the argument to all other calls to frag_grow in | |
3406 | this file. We don't have to worry about being in the | |
3407 | middle of a variant frag, because the variants insert | |
3408 | all needed nop instructions themselves. */ | |
3409 | frag_grow (40); | |
3410 | } | |
3411 | ||
404a8071 | 3412 | mips_move_labels (); |
252b5132 RH |
3413 | |
3414 | #ifndef NO_ECOFF_DEBUGGING | |
3415 | if (ECOFF_DEBUGGING) | |
3416 | ecoff_fix_loc (old_frag, old_frag_offset); | |
3417 | #endif | |
3418 | } | |
71400594 RS |
3419 | } |
3420 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
3421 | { | |
932d1a1b RS |
3422 | int nops; |
3423 | ||
3424 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
3425 | ignoring hazards generated by the first prev_nop_frag_since | |
3426 | instructions. */ | |
3427 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 3428 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 3429 | |
71400594 RS |
3430 | /* Enforce NOPS as a minimum. */ |
3431 | if (nops > prev_nop_frag_required) | |
3432 | prev_nop_frag_required = nops; | |
252b5132 | 3433 | |
71400594 RS |
3434 | if (prev_nop_frag_holds == prev_nop_frag_required) |
3435 | { | |
3436 | /* Settle for the current number of nops. Update the history | |
3437 | accordingly (for the benefit of any future .set reorder code). */ | |
3438 | prev_nop_frag = NULL; | |
3439 | insert_into_history (prev_nop_frag_since, | |
3440 | prev_nop_frag_holds, NOP_INSN); | |
3441 | } | |
3442 | else | |
3443 | { | |
3444 | /* Allow this instruction to replace one of the nops that was | |
3445 | tentatively added to prev_nop_frag. */ | |
3446 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
3447 | prev_nop_frag_holds--; | |
3448 | prev_nop_frag_since++; | |
252b5132 RH |
3449 | } |
3450 | } | |
3451 | ||
a4e06468 RS |
3452 | method = get_append_method (ip); |
3453 | ||
58e2ea4d MR |
3454 | #ifdef OBJ_ELF |
3455 | /* The value passed to dwarf2_emit_insn is the distance between | |
3456 | the beginning of the current instruction and the address that | |
e3a82c8e MR |
3457 | should be recorded in the debug tables. This is normally the |
3458 | current address. | |
3459 | ||
3460 | For MIPS16 debug info we want to use ISA-encoded addresses, | |
3461 | so we use -1 for an address higher by one than the current one. | |
3462 | ||
3463 | If the instruction produced is a branch that we will swap with | |
3464 | the preceding instruction, then we add the displacement by which | |
3465 | the branch will be moved backwards. This is more appropriate | |
3466 | and for MIPS16 code also prevents a debugger from placing a | |
3467 | breakpoint in the middle of the branch (and corrupting code if | |
3468 | software breakpoints are used). */ | |
3469 | dwarf2_emit_insn ((mips_opts.mips16 ? -1 : 0) | |
3470 | + (method == APPEND_SWAP ? insn_length (history) : 0)); | |
58e2ea4d MR |
3471 | #endif |
3472 | ||
4d7206a2 | 3473 | if (address_expr |
0b25d3e6 | 3474 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
3475 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
3476 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
3477 | && mips_relax_branch | |
3478 | /* Don't try branch relaxation within .set nomacro, or within | |
3479 | .set noat if we use $at for PIC computations. If it turns | |
3480 | out that the branch was out-of-range, we'll get an error. */ | |
3481 | && !mips_opts.warn_about_macros | |
741fe287 | 3482 | && (mips_opts.at || mips_pic == NO_PIC) |
d455268f MR |
3483 | /* Don't relax BPOSGE32/64 as they have no complementing branches. */ |
3484 | && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP)) | |
4a6a3df4 AO |
3485 | && !mips_opts.mips16) |
3486 | { | |
895921c9 | 3487 | relaxed_branch = TRUE; |
1e915849 RS |
3488 | add_relaxed_insn (ip, (relaxed_branch_length |
3489 | (NULL, NULL, | |
3490 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
3491 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
3492 | : 0)), 4, | |
3493 | RELAX_BRANCH_ENCODE | |
66b3e8da MR |
3494 | (AT, |
3495 | pinfo & INSN_UNCOND_BRANCH_DELAY, | |
1e915849 RS |
3496 | pinfo & INSN_COND_BRANCH_LIKELY, |
3497 | pinfo & INSN_WRITE_GPR_31, | |
3498 | 0), | |
3499 | address_expr->X_add_symbol, | |
3500 | address_expr->X_add_number); | |
4a6a3df4 AO |
3501 | *reloc_type = BFD_RELOC_UNUSED; |
3502 | } | |
3503 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
3504 | { |
3505 | /* We need to set up a variant frag. */ | |
9c2799c2 | 3506 | gas_assert (mips_opts.mips16 && address_expr != NULL); |
1e915849 RS |
3507 | add_relaxed_insn (ip, 4, 0, |
3508 | RELAX_MIPS16_ENCODE | |
3509 | (*reloc_type - BFD_RELOC_UNUSED, | |
3510 | mips16_small, mips16_ext, | |
3511 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
3512 | history[0].mips16_absolute_jump_p), | |
3513 | make_expr_symbol (address_expr), 0); | |
252b5132 | 3514 | } |
252b5132 RH |
3515 | else if (mips_opts.mips16 |
3516 | && ! ip->use_extend | |
f6688943 | 3517 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 3518 | { |
b8ee1a6e DU |
3519 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0) |
3520 | /* Make sure there is enough room to swap this instruction with | |
3521 | a following jump instruction. */ | |
3522 | frag_grow (6); | |
1e915849 | 3523 | add_fixed_insn (ip); |
252b5132 RH |
3524 | } |
3525 | else | |
3526 | { | |
3527 | if (mips_opts.mips16 | |
3528 | && mips_opts.noreorder | |
3529 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
3530 | as_warn (_("extended instruction in delay slot")); | |
3531 | ||
4d7206a2 RS |
3532 | if (mips_relax.sequence) |
3533 | { | |
3534 | /* If we've reached the end of this frag, turn it into a variant | |
3535 | frag and record the information for the instructions we've | |
3536 | written so far. */ | |
3537 | if (frag_room () < 4) | |
3538 | relax_close_frag (); | |
3539 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
3540 | } | |
3541 | ||
584892a6 RS |
3542 | if (mips_relax.sequence != 2) |
3543 | mips_macro_warning.sizes[0] += 4; | |
3544 | if (mips_relax.sequence != 1) | |
3545 | mips_macro_warning.sizes[1] += 4; | |
3546 | ||
1e915849 RS |
3547 | if (mips_opts.mips16) |
3548 | { | |
3549 | ip->fixed_p = 1; | |
3550 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
3551 | } | |
3552 | add_fixed_insn (ip); | |
252b5132 RH |
3553 | } |
3554 | ||
9fe77896 | 3555 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 3556 | { |
9fe77896 RS |
3557 | reloc_howto_type *howto; |
3558 | int i; | |
34ce925e | 3559 | |
9fe77896 RS |
3560 | /* In a compound relocation, it is the final (outermost) |
3561 | operator that determines the relocated field. */ | |
3562 | for (i = 1; i < 3; i++) | |
3563 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
3564 | break; | |
34ce925e | 3565 | |
9fe77896 RS |
3566 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
3567 | if (howto == NULL) | |
3568 | { | |
3569 | /* To reproduce this failure try assembling gas/testsuites/ | |
3570 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
3571 | assembler. */ | |
3572 | as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]); | |
3573 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); | |
3574 | } | |
23fce1e3 | 3575 | |
9fe77896 RS |
3576 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
3577 | bfd_get_reloc_size (howto), | |
3578 | address_expr, | |
3579 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
3580 | reloc_type[0]); | |
3581 | ||
3582 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
3583 | if (reloc_type[0] == BFD_RELOC_MIPS16_JMP | |
3584 | && ip->fixp[0]->fx_addsy) | |
3585 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; | |
3586 | ||
3587 | /* These relocations can have an addend that won't fit in | |
3588 | 4 octets for 64bit assembly. */ | |
3589 | if (HAVE_64BIT_GPRS | |
3590 | && ! howto->partial_inplace | |
3591 | && (reloc_type[0] == BFD_RELOC_16 | |
3592 | || reloc_type[0] == BFD_RELOC_32 | |
3593 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
3594 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
3595 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
3596 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
3597 | || reloc_type[0] == BFD_RELOC_64 | |
3598 | || reloc_type[0] == BFD_RELOC_CTOR | |
3599 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
3600 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
3601 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
3602 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
3603 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
3604 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
3605 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
3606 | || hi16_reloc_p (reloc_type[0]) | |
3607 | || lo16_reloc_p (reloc_type[0]))) | |
3608 | ip->fixp[0]->fx_no_overflow = 1; | |
3609 | ||
3610 | if (mips_relax.sequence) | |
3611 | { | |
3612 | if (mips_relax.first_fixup == 0) | |
3613 | mips_relax.first_fixup = ip->fixp[0]; | |
3614 | } | |
3615 | else if (reloc_needs_lo_p (*reloc_type)) | |
3616 | { | |
3617 | struct mips_hi_fixup *hi_fixup; | |
3618 | ||
3619 | /* Reuse the last entry if it already has a matching %lo. */ | |
3620 | hi_fixup = mips_hi_fixup_list; | |
3621 | if (hi_fixup == 0 | |
3622 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 3623 | { |
9fe77896 RS |
3624 | hi_fixup = ((struct mips_hi_fixup *) |
3625 | xmalloc (sizeof (struct mips_hi_fixup))); | |
3626 | hi_fixup->next = mips_hi_fixup_list; | |
3627 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 3628 | } |
9fe77896 RS |
3629 | hi_fixup->fixp = ip->fixp[0]; |
3630 | hi_fixup->seg = now_seg; | |
3631 | } | |
252b5132 | 3632 | |
9fe77896 RS |
3633 | /* Add fixups for the second and third relocations, if given. |
3634 | Note that the ABI allows the second relocation to be | |
3635 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
3636 | moment we only use RSS_UNDEF, but we could add support | |
3637 | for the others if it ever becomes necessary. */ | |
3638 | for (i = 1; i < 3; i++) | |
3639 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
3640 | { | |
3641 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
3642 | ip->fixp[0]->fx_size, NULL, 0, | |
3643 | FALSE, reloc_type[i]); | |
f6688943 | 3644 | |
9fe77896 RS |
3645 | /* Use fx_tcbit to mark compound relocs. */ |
3646 | ip->fixp[0]->fx_tcbit = 1; | |
3647 | ip->fixp[i]->fx_tcbit = 1; | |
3648 | } | |
252b5132 | 3649 | } |
1e915849 | 3650 | install_insn (ip); |
252b5132 RH |
3651 | |
3652 | /* Update the register mask information. */ | |
4c260379 RS |
3653 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
3654 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 3655 | |
a4e06468 | 3656 | switch (method) |
252b5132 | 3657 | { |
a4e06468 RS |
3658 | case APPEND_ADD: |
3659 | insert_into_history (0, 1, ip); | |
3660 | break; | |
3661 | ||
3662 | case APPEND_ADD_WITH_NOP: | |
3663 | insert_into_history (0, 1, ip); | |
3664 | emit_nop (); | |
3665 | if (mips_relax.sequence) | |
3666 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
3667 | break; | |
3668 | ||
3669 | case APPEND_ADD_COMPACT: | |
3670 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
3671 | gas_assert (mips_opts.mips16); | |
3672 | ip->insn_opcode |= 0x0080; | |
3673 | find_altered_mips16_opcode (ip); | |
3674 | install_insn (ip); | |
3675 | insert_into_history (0, 1, ip); | |
3676 | break; | |
3677 | ||
3678 | case APPEND_SWAP: | |
3679 | { | |
3680 | struct mips_cl_insn delay = history[0]; | |
3681 | if (mips_opts.mips16) | |
3682 | { | |
3683 | know (delay.frag == ip->frag); | |
3684 | move_insn (ip, delay.frag, delay.where); | |
3685 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
3686 | } | |
3687 | else if (relaxed_branch) | |
3688 | { | |
3689 | /* Add the delay slot instruction to the end of the | |
3690 | current frag and shrink the fixed part of the | |
3691 | original frag. If the branch occupies the tail of | |
3692 | the latter, move it backwards to cover the gap. */ | |
3693 | delay.frag->fr_fix -= 4; | |
3694 | if (delay.frag == ip->frag) | |
3695 | move_insn (ip, ip->frag, ip->where - 4); | |
3696 | add_fixed_insn (&delay); | |
3697 | } | |
3698 | else | |
3699 | { | |
3700 | move_insn (&delay, ip->frag, ip->where); | |
3701 | move_insn (ip, history[0].frag, history[0].where); | |
3702 | } | |
3703 | history[0] = *ip; | |
3704 | delay.fixed_p = 1; | |
3705 | insert_into_history (0, 1, &delay); | |
3706 | } | |
3707 | break; | |
252b5132 RH |
3708 | } |
3709 | ||
13408f1e RS |
3710 | /* If we have just completed an unconditional branch, clear the history. */ |
3711 | if ((history[1].insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3712 | || (mips_opts.mips16 | |
3713 | && (history[0].insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH))) | |
3714 | mips_no_prev_insn (); | |
3715 | ||
252b5132 RH |
3716 | /* We just output an insn, so the next one doesn't have a label. */ |
3717 | mips_clear_insn_labels (); | |
252b5132 RH |
3718 | } |
3719 | ||
7d10b47d | 3720 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
3721 | |
3722 | static void | |
7d10b47d | 3723 | mips_no_prev_insn (void) |
252b5132 | 3724 | { |
7d10b47d RS |
3725 | prev_nop_frag = NULL; |
3726 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
3727 | mips_clear_insn_labels (); |
3728 | } | |
3729 | ||
7d10b47d RS |
3730 | /* This function must be called before we emit something other than |
3731 | instructions. It is like mips_no_prev_insn except that it inserts | |
3732 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 3733 | |
7d10b47d RS |
3734 | void |
3735 | mips_emit_delays (void) | |
252b5132 RH |
3736 | { |
3737 | if (! mips_opts.noreorder) | |
3738 | { | |
932d1a1b | 3739 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
3740 | if (nops > 0) |
3741 | { | |
7d10b47d RS |
3742 | while (nops-- > 0) |
3743 | add_fixed_insn (NOP_INSN); | |
3744 | mips_move_labels (); | |
3745 | } | |
3746 | } | |
3747 | mips_no_prev_insn (); | |
3748 | } | |
3749 | ||
3750 | /* Start a (possibly nested) noreorder block. */ | |
3751 | ||
3752 | static void | |
3753 | start_noreorder (void) | |
3754 | { | |
3755 | if (mips_opts.noreorder == 0) | |
3756 | { | |
3757 | unsigned int i; | |
3758 | int nops; | |
3759 | ||
3760 | /* None of the instructions before the .set noreorder can be moved. */ | |
3761 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
3762 | history[i].fixed_p = 1; | |
3763 | ||
3764 | /* Insert any nops that might be needed between the .set noreorder | |
3765 | block and the previous instructions. We will later remove any | |
3766 | nops that turn out not to be needed. */ | |
932d1a1b | 3767 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
3768 | if (nops > 0) |
3769 | { | |
3770 | if (mips_optimize != 0) | |
252b5132 RH |
3771 | { |
3772 | /* Record the frag which holds the nop instructions, so | |
3773 | that we can remove them if we don't need them. */ | |
3774 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
3775 | prev_nop_frag = frag_now; | |
3776 | prev_nop_frag_holds = nops; | |
3777 | prev_nop_frag_required = 0; | |
3778 | prev_nop_frag_since = 0; | |
3779 | } | |
3780 | ||
3781 | for (; nops > 0; --nops) | |
1e915849 | 3782 | add_fixed_insn (NOP_INSN); |
252b5132 | 3783 | |
7d10b47d RS |
3784 | /* Move on to a new frag, so that it is safe to simply |
3785 | decrease the size of prev_nop_frag. */ | |
3786 | frag_wane (frag_now); | |
3787 | frag_new (0); | |
404a8071 | 3788 | mips_move_labels (); |
252b5132 | 3789 | } |
7d10b47d RS |
3790 | mips16_mark_labels (); |
3791 | mips_clear_insn_labels (); | |
252b5132 | 3792 | } |
7d10b47d RS |
3793 | mips_opts.noreorder++; |
3794 | mips_any_noreorder = 1; | |
3795 | } | |
252b5132 | 3796 | |
7d10b47d | 3797 | /* End a nested noreorder block. */ |
252b5132 | 3798 | |
7d10b47d RS |
3799 | static void |
3800 | end_noreorder (void) | |
3801 | { | |
6a32d874 | 3802 | |
7d10b47d RS |
3803 | mips_opts.noreorder--; |
3804 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
3805 | { | |
3806 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
3807 | handling nop insertion the .set reorder way. */ | |
3808 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
3809 | * (mips_opts.mips16 ? 2 : 4)); | |
3810 | insert_into_history (prev_nop_frag_since, | |
3811 | prev_nop_frag_required, NOP_INSN); | |
3812 | prev_nop_frag = NULL; | |
3813 | } | |
252b5132 RH |
3814 | } |
3815 | ||
584892a6 RS |
3816 | /* Set up global variables for the start of a new macro. */ |
3817 | ||
3818 | static void | |
3819 | macro_start (void) | |
3820 | { | |
3821 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
3822 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 3823 | && (history[0].insn_mo->pinfo |
584892a6 RS |
3824 | & (INSN_UNCOND_BRANCH_DELAY |
3825 | | INSN_COND_BRANCH_DELAY | |
3826 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
3827 | } | |
3828 | ||
3829 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
3830 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
3831 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
3832 | ||
3833 | static const char * | |
3834 | macro_warning (relax_substateT subtype) | |
3835 | { | |
3836 | if (subtype & RELAX_DELAY_SLOT) | |
3837 | return _("Macro instruction expanded into multiple instructions" | |
3838 | " in a branch delay slot"); | |
3839 | else if (subtype & RELAX_NOMACRO) | |
3840 | return _("Macro instruction expanded into multiple instructions"); | |
3841 | else | |
3842 | return 0; | |
3843 | } | |
3844 | ||
3845 | /* Finish up a macro. Emit warnings as appropriate. */ | |
3846 | ||
3847 | static void | |
3848 | macro_end (void) | |
3849 | { | |
3850 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
3851 | { | |
3852 | relax_substateT subtype; | |
3853 | ||
3854 | /* Set up the relaxation warning flags. */ | |
3855 | subtype = 0; | |
3856 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
3857 | subtype |= RELAX_SECOND_LONGER; | |
3858 | if (mips_opts.warn_about_macros) | |
3859 | subtype |= RELAX_NOMACRO; | |
3860 | if (mips_macro_warning.delay_slot_p) | |
3861 | subtype |= RELAX_DELAY_SLOT; | |
3862 | ||
3863 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
3864 | { | |
3865 | /* Either the macro has a single implementation or both | |
3866 | implementations are longer than 4 bytes. Emit the | |
3867 | warning now. */ | |
3868 | const char *msg = macro_warning (subtype); | |
3869 | if (msg != 0) | |
520725ea | 3870 | as_warn ("%s", msg); |
584892a6 RS |
3871 | } |
3872 | else | |
3873 | { | |
3874 | /* One implementation might need a warning but the other | |
3875 | definitely doesn't. */ | |
3876 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
3877 | } | |
3878 | } | |
3879 | } | |
3880 | ||
6e1304d8 RS |
3881 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
3882 | The first argument in *ARGS will be either the code for a single | |
3883 | relocation or -1 followed by the three codes that make up a | |
3884 | composite relocation. */ | |
3885 | ||
3886 | static void | |
3887 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
3888 | { | |
3889 | int i, next; | |
3890 | ||
3891 | next = va_arg (*args, int); | |
3892 | if (next >= 0) | |
3893 | r[0] = (bfd_reloc_code_real_type) next; | |
3894 | else | |
3895 | for (i = 0; i < 3; i++) | |
3896 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
3897 | } | |
3898 | ||
252b5132 RH |
3899 | /* Build an instruction created by a macro expansion. This is passed |
3900 | a pointer to the count of instructions created so far, an | |
3901 | expression, the name of the instruction to build, an operand format | |
3902 | string, and corresponding arguments. */ | |
3903 | ||
252b5132 | 3904 | static void |
67c0d1eb | 3905 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 3906 | { |
1e915849 | 3907 | const struct mips_opcode *mo; |
252b5132 | 3908 | struct mips_cl_insn insn; |
f6688943 | 3909 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3910 | va_list args; |
252b5132 | 3911 | |
252b5132 | 3912 | va_start (args, fmt); |
252b5132 | 3913 | |
252b5132 RH |
3914 | if (mips_opts.mips16) |
3915 | { | |
03ea81db | 3916 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
3917 | va_end (args); |
3918 | return; | |
3919 | } | |
3920 | ||
f6688943 TS |
3921 | r[0] = BFD_RELOC_UNUSED; |
3922 | r[1] = BFD_RELOC_UNUSED; | |
3923 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 | 3924 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
9c2799c2 NC |
3925 | gas_assert (mo); |
3926 | gas_assert (strcmp (name, mo->name) == 0); | |
1e915849 | 3927 | |
8b082fb1 TS |
3928 | while (1) |
3929 | { | |
3930 | /* Search until we get a match for NAME. It is assumed here that | |
3931 | macros will never generate MDMX, MIPS-3D, or MT instructions. */ | |
3932 | if (strcmp (fmt, mo->args) == 0 | |
3933 | && mo->pinfo != INSN_MACRO | |
f79e2745 | 3934 | && is_opcode_valid (mo)) |
8b082fb1 TS |
3935 | break; |
3936 | ||
1e915849 | 3937 | ++mo; |
9c2799c2 NC |
3938 | gas_assert (mo->name); |
3939 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3940 | } |
3941 | ||
1e915849 | 3942 | create_insn (&insn, mo); |
252b5132 RH |
3943 | for (;;) |
3944 | { | |
3945 | switch (*fmt++) | |
3946 | { | |
3947 | case '\0': | |
3948 | break; | |
3949 | ||
3950 | case ',': | |
3951 | case '(': | |
3952 | case ')': | |
3953 | continue; | |
3954 | ||
5f74bc13 CD |
3955 | case '+': |
3956 | switch (*fmt++) | |
3957 | { | |
3958 | case 'A': | |
3959 | case 'E': | |
bf12938e | 3960 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
3961 | continue; |
3962 | ||
3963 | case 'B': | |
3964 | case 'F': | |
3965 | /* Note that in the macro case, these arguments are already | |
3966 | in MSB form. (When handling the instruction in the | |
3967 | non-macro case, these arguments are sizes from which | |
3968 | MSB values must be calculated.) */ | |
bf12938e | 3969 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3970 | continue; |
3971 | ||
3972 | case 'C': | |
3973 | case 'G': | |
3974 | case 'H': | |
3975 | /* Note that in the macro case, these arguments are already | |
3976 | in MSBD form. (When handling the instruction in the | |
3977 | non-macro case, these arguments are sizes from which | |
3978 | MSBD values must be calculated.) */ | |
bf12938e | 3979 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3980 | continue; |
3981 | ||
dd3cbb7e NC |
3982 | case 'Q': |
3983 | INSERT_OPERAND (SEQI, insn, va_arg (args, int)); | |
3984 | continue; | |
3985 | ||
5f74bc13 CD |
3986 | default: |
3987 | internalError (); | |
3988 | } | |
3989 | continue; | |
3990 | ||
8b082fb1 TS |
3991 | case '2': |
3992 | INSERT_OPERAND (BP, insn, va_arg (args, int)); | |
3993 | continue; | |
3994 | ||
252b5132 RH |
3995 | case 't': |
3996 | case 'w': | |
3997 | case 'E': | |
bf12938e | 3998 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3999 | continue; |
4000 | ||
4001 | case 'c': | |
bf12938e | 4002 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
4003 | continue; |
4004 | ||
252b5132 RH |
4005 | case 'T': |
4006 | case 'W': | |
bf12938e | 4007 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
4008 | continue; |
4009 | ||
4010 | case 'd': | |
4011 | case 'G': | |
af7ee8bf | 4012 | case 'K': |
bf12938e | 4013 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
4014 | continue; |
4015 | ||
4372b673 NC |
4016 | case 'U': |
4017 | { | |
4018 | int tmp = va_arg (args, int); | |
4019 | ||
bf12938e RS |
4020 | INSERT_OPERAND (RT, insn, tmp); |
4021 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 4022 | continue; |
4372b673 NC |
4023 | } |
4024 | ||
252b5132 RH |
4025 | case 'V': |
4026 | case 'S': | |
bf12938e | 4027 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
4028 | continue; |
4029 | ||
4030 | case 'z': | |
4031 | continue; | |
4032 | ||
4033 | case '<': | |
bf12938e | 4034 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
4035 | continue; |
4036 | ||
4037 | case 'D': | |
bf12938e | 4038 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
4039 | continue; |
4040 | ||
4041 | case 'B': | |
bf12938e | 4042 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
4043 | continue; |
4044 | ||
4372b673 | 4045 | case 'J': |
bf12938e | 4046 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
4047 | continue; |
4048 | ||
252b5132 | 4049 | case 'q': |
bf12938e | 4050 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
4051 | continue; |
4052 | ||
4053 | case 'b': | |
4054 | case 's': | |
4055 | case 'r': | |
4056 | case 'v': | |
bf12938e | 4057 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
4058 | continue; |
4059 | ||
4060 | case 'i': | |
4061 | case 'j': | |
6e1304d8 | 4062 | macro_read_relocs (&args, r); |
9c2799c2 | 4063 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
4064 | || *r == BFD_RELOC_MIPS_HIGHER |
4065 | || *r == BFD_RELOC_HI16_S | |
4066 | || *r == BFD_RELOC_LO16 | |
4067 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
4068 | continue; | |
4069 | ||
4070 | case 'o': | |
4071 | macro_read_relocs (&args, r); | |
252b5132 RH |
4072 | continue; |
4073 | ||
4074 | case 'u': | |
6e1304d8 | 4075 | macro_read_relocs (&args, r); |
9c2799c2 | 4076 | gas_assert (ep != NULL |
90ecf173 MR |
4077 | && (ep->X_op == O_constant |
4078 | || (ep->X_op == O_symbol | |
4079 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
4080 | || *r == BFD_RELOC_HI16_S | |
4081 | || *r == BFD_RELOC_HI16 | |
4082 | || *r == BFD_RELOC_GPREL16 | |
4083 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
4084 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
4085 | continue; |
4086 | ||
4087 | case 'p': | |
9c2799c2 | 4088 | gas_assert (ep != NULL); |
bad36eac | 4089 | |
252b5132 RH |
4090 | /* |
4091 | * This allows macro() to pass an immediate expression for | |
4092 | * creating short branches without creating a symbol. | |
bad36eac DJ |
4093 | * |
4094 | * We don't allow branch relaxation for these branches, as | |
4095 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
4096 | */ |
4097 | if (ep->X_op == O_constant) | |
4098 | { | |
bad36eac DJ |
4099 | if ((ep->X_add_number & 3) != 0) |
4100 | as_bad (_("branch to misaligned address (0x%lx)"), | |
4101 | (unsigned long) ep->X_add_number); | |
4102 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
4103 | as_bad (_("branch address range overflow (0x%lx)"), | |
4104 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
4105 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
4106 | ep = NULL; | |
4107 | } | |
4108 | else | |
0b25d3e6 | 4109 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
4110 | continue; |
4111 | ||
4112 | case 'a': | |
9c2799c2 | 4113 | gas_assert (ep != NULL); |
f6688943 | 4114 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
4115 | continue; |
4116 | ||
4117 | case 'C': | |
a9e24354 | 4118 | INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long)); |
252b5132 RH |
4119 | continue; |
4120 | ||
d43b4baf | 4121 | case 'k': |
a9e24354 | 4122 | INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long)); |
d43b4baf TS |
4123 | continue; |
4124 | ||
252b5132 RH |
4125 | default: |
4126 | internalError (); | |
4127 | } | |
4128 | break; | |
4129 | } | |
4130 | va_end (args); | |
9c2799c2 | 4131 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 4132 | |
4d7206a2 | 4133 | append_insn (&insn, ep, r); |
252b5132 RH |
4134 | } |
4135 | ||
4136 | static void | |
67c0d1eb | 4137 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 4138 | va_list *args) |
252b5132 | 4139 | { |
1e915849 | 4140 | struct mips_opcode *mo; |
252b5132 | 4141 | struct mips_cl_insn insn; |
f6688943 TS |
4142 | bfd_reloc_code_real_type r[3] |
4143 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 4144 | |
1e915849 | 4145 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
4146 | gas_assert (mo); |
4147 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 4148 | |
1e915849 | 4149 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 4150 | { |
1e915849 | 4151 | ++mo; |
9c2799c2 NC |
4152 | gas_assert (mo->name); |
4153 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
4154 | } |
4155 | ||
1e915849 | 4156 | create_insn (&insn, mo); |
252b5132 RH |
4157 | for (;;) |
4158 | { | |
4159 | int c; | |
4160 | ||
4161 | c = *fmt++; | |
4162 | switch (c) | |
4163 | { | |
4164 | case '\0': | |
4165 | break; | |
4166 | ||
4167 | case ',': | |
4168 | case '(': | |
4169 | case ')': | |
4170 | continue; | |
4171 | ||
4172 | case 'y': | |
4173 | case 'w': | |
03ea81db | 4174 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
4175 | continue; |
4176 | ||
4177 | case 'x': | |
4178 | case 'v': | |
03ea81db | 4179 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
4180 | continue; |
4181 | ||
4182 | case 'z': | |
03ea81db | 4183 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
4184 | continue; |
4185 | ||
4186 | case 'Z': | |
03ea81db | 4187 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
4188 | continue; |
4189 | ||
4190 | case '0': | |
4191 | case 'S': | |
4192 | case 'P': | |
4193 | case 'R': | |
4194 | continue; | |
4195 | ||
4196 | case 'X': | |
03ea81db | 4197 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
4198 | continue; |
4199 | ||
4200 | case 'Y': | |
4201 | { | |
4202 | int regno; | |
4203 | ||
03ea81db | 4204 | regno = va_arg (*args, int); |
252b5132 | 4205 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 4206 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
4207 | } |
4208 | continue; | |
4209 | ||
4210 | case '<': | |
4211 | case '>': | |
4212 | case '4': | |
4213 | case '5': | |
4214 | case 'H': | |
4215 | case 'W': | |
4216 | case 'D': | |
4217 | case 'j': | |
4218 | case '8': | |
4219 | case 'V': | |
4220 | case 'C': | |
4221 | case 'U': | |
4222 | case 'k': | |
4223 | case 'K': | |
4224 | case 'p': | |
4225 | case 'q': | |
4226 | { | |
9c2799c2 | 4227 | gas_assert (ep != NULL); |
252b5132 RH |
4228 | |
4229 | if (ep->X_op != O_constant) | |
874e8986 | 4230 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
4231 | else |
4232 | { | |
b34976b6 AM |
4233 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
4234 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 4235 | &insn.extend); |
252b5132 | 4236 | ep = NULL; |
f6688943 | 4237 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
4238 | } |
4239 | } | |
4240 | continue; | |
4241 | ||
4242 | case '6': | |
03ea81db | 4243 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
4244 | continue; |
4245 | } | |
4246 | ||
4247 | break; | |
4248 | } | |
4249 | ||
9c2799c2 | 4250 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 4251 | |
4d7206a2 | 4252 | append_insn (&insn, ep, r); |
252b5132 RH |
4253 | } |
4254 | ||
2051e8c4 MR |
4255 | /* |
4256 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
4257 | * higher bits unset. | |
4258 | */ | |
9f872bbe | 4259 | static void |
2051e8c4 MR |
4260 | normalize_constant_expr (expressionS *ex) |
4261 | { | |
9ee2a2d4 | 4262 | if (ex->X_op == O_constant |
2051e8c4 MR |
4263 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
4264 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
4265 | - 0x80000000); | |
4266 | } | |
4267 | ||
4268 | /* | |
4269 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
4270 | * all higher bits unset. | |
4271 | */ | |
4272 | static void | |
4273 | normalize_address_expr (expressionS *ex) | |
4274 | { | |
4275 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
4276 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
4277 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
4278 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
4279 | - 0x80000000); | |
4280 | } | |
4281 | ||
438c16b8 TS |
4282 | /* |
4283 | * Generate a "jalr" instruction with a relocation hint to the called | |
4284 | * function. This occurs in NewABI PIC code. | |
4285 | */ | |
4286 | static void | |
67c0d1eb | 4287 | macro_build_jalr (expressionS *ep) |
438c16b8 | 4288 | { |
685736be | 4289 | char *f = NULL; |
b34976b6 | 4290 | |
1180b5a4 | 4291 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 4292 | { |
cc3d92a5 | 4293 | frag_grow (8); |
f21f8242 AO |
4294 | f = frag_more (0); |
4295 | } | |
67c0d1eb | 4296 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
1180b5a4 | 4297 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 4298 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 4299 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
4300 | } |
4301 | ||
252b5132 RH |
4302 | /* |
4303 | * Generate a "lui" instruction. | |
4304 | */ | |
4305 | static void | |
67c0d1eb | 4306 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
4307 | { |
4308 | expressionS high_expr; | |
1e915849 | 4309 | const struct mips_opcode *mo; |
252b5132 | 4310 | struct mips_cl_insn insn; |
f6688943 TS |
4311 | bfd_reloc_code_real_type r[3] |
4312 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
4313 | const char *name = "lui"; |
4314 | const char *fmt = "t,u"; | |
252b5132 | 4315 | |
9c2799c2 | 4316 | gas_assert (! mips_opts.mips16); |
252b5132 | 4317 | |
4d7206a2 | 4318 | high_expr = *ep; |
252b5132 RH |
4319 | |
4320 | if (high_expr.X_op == O_constant) | |
4321 | { | |
54f4ddb3 | 4322 | /* We can compute the instruction now without a relocation entry. */ |
e7d556df TS |
4323 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
4324 | >> 16) & 0xffff; | |
f6688943 | 4325 | *r = BFD_RELOC_UNUSED; |
252b5132 | 4326 | } |
78e1bb40 | 4327 | else |
252b5132 | 4328 | { |
9c2799c2 | 4329 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
4330 | /* _gp_disp is a special case, used from s_cpload. |
4331 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 4332 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 4333 | || (! HAVE_NEWABI |
aa6975fb ILT |
4334 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
4335 | || (! mips_in_shared | |
bbe506e8 TS |
4336 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
4337 | "__gnu_local_gp") == 0)); | |
f6688943 | 4338 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
4339 | } |
4340 | ||
1e915849 | 4341 | mo = hash_find (op_hash, name); |
9c2799c2 NC |
4342 | gas_assert (strcmp (name, mo->name) == 0); |
4343 | gas_assert (strcmp (fmt, mo->args) == 0); | |
1e915849 | 4344 | create_insn (&insn, mo); |
252b5132 | 4345 | |
bf12938e RS |
4346 | insn.insn_opcode = insn.insn_mo->match; |
4347 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 4348 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
4349 | { |
4350 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 4351 | append_insn (&insn, NULL, r); |
252b5132 RH |
4352 | } |
4353 | else | |
4d7206a2 | 4354 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
4355 | } |
4356 | ||
885add95 CD |
4357 | /* Generate a sequence of instructions to do a load or store from a constant |
4358 | offset off of a base register (breg) into/from a target register (treg), | |
4359 | using AT if necessary. */ | |
4360 | static void | |
67c0d1eb RS |
4361 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
4362 | int treg, int breg, int dbl) | |
885add95 | 4363 | { |
9c2799c2 | 4364 | gas_assert (ep->X_op == O_constant); |
885add95 | 4365 | |
256ab948 | 4366 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
4367 | if (!dbl) |
4368 | normalize_constant_expr (ep); | |
256ab948 | 4369 | |
67c1ffbe | 4370 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 4371 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
4372 | as_warn (_("operand overflow")); |
4373 | ||
4374 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
4375 | { | |
4376 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 4377 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
4378 | } |
4379 | else | |
4380 | { | |
4381 | /* 32-bit offset, need multiple instructions and AT, like: | |
4382 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
4383 | addu $tempreg,$tempreg,$breg | |
4384 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
4385 | to handle the complete offset. */ | |
67c0d1eb RS |
4386 | macro_build_lui (ep, AT); |
4387 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
4388 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 4389 | |
741fe287 | 4390 | if (!mips_opts.at) |
8fc2e39e | 4391 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
4392 | } |
4393 | } | |
4394 | ||
252b5132 RH |
4395 | /* set_at() |
4396 | * Generates code to set the $at register to true (one) | |
4397 | * if reg is less than the immediate expression. | |
4398 | */ | |
4399 | static void | |
67c0d1eb | 4400 | set_at (int reg, int unsignedp) |
252b5132 RH |
4401 | { |
4402 | if (imm_expr.X_op == O_constant | |
4403 | && imm_expr.X_add_number >= -0x8000 | |
4404 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
4405 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
4406 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
4407 | else |
4408 | { | |
67c0d1eb RS |
4409 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4410 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
4411 | } |
4412 | } | |
4413 | ||
4414 | /* Warn if an expression is not a constant. */ | |
4415 | ||
4416 | static void | |
17a2f251 | 4417 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
4418 | { |
4419 | if (ex->X_op == O_big) | |
4420 | as_bad (_("unsupported large constant")); | |
4421 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
4422 | as_bad (_("Instruction %s requires absolute expression"), |
4423 | ip->insn_mo->name); | |
13757d0c | 4424 | |
9ee2a2d4 MR |
4425 | if (HAVE_32BIT_GPRS) |
4426 | normalize_constant_expr (ex); | |
252b5132 RH |
4427 | } |
4428 | ||
4429 | /* Count the leading zeroes by performing a binary chop. This is a | |
4430 | bulky bit of source, but performance is a LOT better for the | |
4431 | majority of values than a simple loop to count the bits: | |
4432 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
4433 | if ((v) & (1 << (31 - lcnt))) | |
4434 | break; | |
4435 | However it is not code size friendly, and the gain will drop a bit | |
4436 | on certain cached systems. | |
4437 | */ | |
4438 | #define COUNT_TOP_ZEROES(v) \ | |
4439 | (((v) & ~0xffff) == 0 \ | |
4440 | ? ((v) & ~0xff) == 0 \ | |
4441 | ? ((v) & ~0xf) == 0 \ | |
4442 | ? ((v) & ~0x3) == 0 \ | |
4443 | ? ((v) & ~0x1) == 0 \ | |
4444 | ? !(v) \ | |
4445 | ? 32 \ | |
4446 | : 31 \ | |
4447 | : 30 \ | |
4448 | : ((v) & ~0x7) == 0 \ | |
4449 | ? 29 \ | |
4450 | : 28 \ | |
4451 | : ((v) & ~0x3f) == 0 \ | |
4452 | ? ((v) & ~0x1f) == 0 \ | |
4453 | ? 27 \ | |
4454 | : 26 \ | |
4455 | : ((v) & ~0x7f) == 0 \ | |
4456 | ? 25 \ | |
4457 | : 24 \ | |
4458 | : ((v) & ~0xfff) == 0 \ | |
4459 | ? ((v) & ~0x3ff) == 0 \ | |
4460 | ? ((v) & ~0x1ff) == 0 \ | |
4461 | ? 23 \ | |
4462 | : 22 \ | |
4463 | : ((v) & ~0x7ff) == 0 \ | |
4464 | ? 21 \ | |
4465 | : 20 \ | |
4466 | : ((v) & ~0x3fff) == 0 \ | |
4467 | ? ((v) & ~0x1fff) == 0 \ | |
4468 | ? 19 \ | |
4469 | : 18 \ | |
4470 | : ((v) & ~0x7fff) == 0 \ | |
4471 | ? 17 \ | |
4472 | : 16 \ | |
4473 | : ((v) & ~0xffffff) == 0 \ | |
4474 | ? ((v) & ~0xfffff) == 0 \ | |
4475 | ? ((v) & ~0x3ffff) == 0 \ | |
4476 | ? ((v) & ~0x1ffff) == 0 \ | |
4477 | ? 15 \ | |
4478 | : 14 \ | |
4479 | : ((v) & ~0x7ffff) == 0 \ | |
4480 | ? 13 \ | |
4481 | : 12 \ | |
4482 | : ((v) & ~0x3fffff) == 0 \ | |
4483 | ? ((v) & ~0x1fffff) == 0 \ | |
4484 | ? 11 \ | |
4485 | : 10 \ | |
4486 | : ((v) & ~0x7fffff) == 0 \ | |
4487 | ? 9 \ | |
4488 | : 8 \ | |
4489 | : ((v) & ~0xfffffff) == 0 \ | |
4490 | ? ((v) & ~0x3ffffff) == 0 \ | |
4491 | ? ((v) & ~0x1ffffff) == 0 \ | |
4492 | ? 7 \ | |
4493 | : 6 \ | |
4494 | : ((v) & ~0x7ffffff) == 0 \ | |
4495 | ? 5 \ | |
4496 | : 4 \ | |
4497 | : ((v) & ~0x3fffffff) == 0 \ | |
4498 | ? ((v) & ~0x1fffffff) == 0 \ | |
4499 | ? 3 \ | |
4500 | : 2 \ | |
4501 | : ((v) & ~0x7fffffff) == 0 \ | |
4502 | ? 1 \ | |
4503 | : 0) | |
4504 | ||
4505 | /* load_register() | |
67c1ffbe | 4506 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
4507 | * an absolute expression value into a register. |
4508 | */ | |
4509 | static void | |
67c0d1eb | 4510 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
4511 | { |
4512 | int freg; | |
4513 | expressionS hi32, lo32; | |
4514 | ||
4515 | if (ep->X_op != O_big) | |
4516 | { | |
9c2799c2 | 4517 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
4518 | |
4519 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
4520 | if (!dbl) |
4521 | normalize_constant_expr (ep); | |
256ab948 TS |
4522 | |
4523 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
4524 | { |
4525 | /* We can handle 16 bit signed values with an addiu to | |
4526 | $zero. No need to ever use daddiu here, since $zero and | |
4527 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 4528 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4529 | return; |
4530 | } | |
4531 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
4532 | { | |
4533 | /* We can handle 16 bit unsigned values with an ori to | |
4534 | $zero. */ | |
67c0d1eb | 4535 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4536 | return; |
4537 | } | |
256ab948 | 4538 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
4539 | { |
4540 | /* 32 bit values require an lui. */ | |
67c0d1eb | 4541 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4542 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 4543 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
4544 | return; |
4545 | } | |
4546 | } | |
4547 | ||
4548 | /* The value is larger than 32 bits. */ | |
4549 | ||
2051e8c4 | 4550 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 4551 | { |
55e08f71 NC |
4552 | char value[32]; |
4553 | ||
4554 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 4555 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 4556 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4557 | return; |
4558 | } | |
4559 | ||
4560 | if (ep->X_op != O_big) | |
4561 | { | |
4562 | hi32 = *ep; | |
4563 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4564 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4565 | hi32.X_add_number &= 0xffffffff; | |
4566 | lo32 = *ep; | |
4567 | lo32.X_add_number &= 0xffffffff; | |
4568 | } | |
4569 | else | |
4570 | { | |
9c2799c2 | 4571 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
4572 | if (ep->X_add_number == 3) |
4573 | generic_bignum[3] = 0; | |
4574 | else if (ep->X_add_number > 4) | |
4575 | as_bad (_("Number larger than 64 bits")); | |
4576 | lo32.X_op = O_constant; | |
4577 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
4578 | hi32.X_op = O_constant; | |
4579 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
4580 | } | |
4581 | ||
4582 | if (hi32.X_add_number == 0) | |
4583 | freg = 0; | |
4584 | else | |
4585 | { | |
4586 | int shift, bit; | |
4587 | unsigned long hi, lo; | |
4588 | ||
956cd1d6 | 4589 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
4590 | { |
4591 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
4592 | { | |
67c0d1eb | 4593 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4594 | return; |
4595 | } | |
4596 | if (lo32.X_add_number & 0x80000000) | |
4597 | { | |
67c0d1eb | 4598 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4599 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 4600 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
4601 | return; |
4602 | } | |
4603 | } | |
252b5132 RH |
4604 | |
4605 | /* Check for 16bit shifted constant. We know that hi32 is | |
4606 | non-zero, so start the mask on the first bit of the hi32 | |
4607 | value. */ | |
4608 | shift = 17; | |
4609 | do | |
beae10d5 KH |
4610 | { |
4611 | unsigned long himask, lomask; | |
4612 | ||
4613 | if (shift < 32) | |
4614 | { | |
4615 | himask = 0xffff >> (32 - shift); | |
4616 | lomask = (0xffff << shift) & 0xffffffff; | |
4617 | } | |
4618 | else | |
4619 | { | |
4620 | himask = 0xffff << (shift - 32); | |
4621 | lomask = 0; | |
4622 | } | |
4623 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
4624 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
4625 | { | |
4626 | expressionS tmp; | |
4627 | ||
4628 | tmp.X_op = O_constant; | |
4629 | if (shift < 32) | |
4630 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
4631 | | (lo32.X_add_number >> shift)); | |
4632 | else | |
4633 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
4634 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
4635 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
4636 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4637 | return; |
4638 | } | |
f9419b05 | 4639 | ++shift; |
beae10d5 KH |
4640 | } |
4641 | while (shift <= (64 - 16)); | |
252b5132 RH |
4642 | |
4643 | /* Find the bit number of the lowest one bit, and store the | |
4644 | shifted value in hi/lo. */ | |
4645 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
4646 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
4647 | if (lo != 0) | |
4648 | { | |
4649 | bit = 0; | |
4650 | while ((lo & 1) == 0) | |
4651 | { | |
4652 | lo >>= 1; | |
4653 | ++bit; | |
4654 | } | |
4655 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
4656 | hi >>= bit; | |
4657 | } | |
4658 | else | |
4659 | { | |
4660 | bit = 32; | |
4661 | while ((hi & 1) == 0) | |
4662 | { | |
4663 | hi >>= 1; | |
4664 | ++bit; | |
4665 | } | |
4666 | lo = hi; | |
4667 | hi = 0; | |
4668 | } | |
4669 | ||
4670 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
4671 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
4672 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
4673 | { |
4674 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 4675 | if (shift != 0) |
beae10d5 | 4676 | { |
252b5132 RH |
4677 | expressionS tmp; |
4678 | ||
4679 | /* This instruction will set the register to be all | |
4680 | ones. */ | |
beae10d5 KH |
4681 | tmp.X_op = O_constant; |
4682 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 4683 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4684 | if (bit != 0) |
4685 | { | |
4686 | bit += shift; | |
67c0d1eb RS |
4687 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
4688 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 4689 | } |
67c0d1eb RS |
4690 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
4691 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4692 | return; |
4693 | } | |
4694 | } | |
252b5132 RH |
4695 | |
4696 | /* Sign extend hi32 before calling load_register, because we can | |
4697 | generally get better code when we load a sign extended value. */ | |
4698 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 4699 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 4700 | load_register (reg, &hi32, 0); |
252b5132 RH |
4701 | freg = reg; |
4702 | } | |
4703 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
4704 | { | |
4705 | if (freg != 0) | |
4706 | { | |
67c0d1eb | 4707 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
4708 | freg = reg; |
4709 | } | |
4710 | } | |
4711 | else | |
4712 | { | |
4713 | expressionS mid16; | |
4714 | ||
956cd1d6 | 4715 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 4716 | { |
67c0d1eb RS |
4717 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
4718 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
4719 | return; |
4720 | } | |
252b5132 RH |
4721 | |
4722 | if (freg != 0) | |
4723 | { | |
67c0d1eb | 4724 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
4725 | freg = reg; |
4726 | } | |
4727 | mid16 = lo32; | |
4728 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
4729 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
4730 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
4731 | freg = reg; |
4732 | } | |
4733 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 4734 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
4735 | } |
4736 | ||
269137b2 TS |
4737 | static inline void |
4738 | load_delay_nop (void) | |
4739 | { | |
4740 | if (!gpr_interlocks) | |
4741 | macro_build (NULL, "nop", ""); | |
4742 | } | |
4743 | ||
252b5132 RH |
4744 | /* Load an address into a register. */ |
4745 | ||
4746 | static void | |
67c0d1eb | 4747 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 4748 | { |
252b5132 RH |
4749 | if (ep->X_op != O_constant |
4750 | && ep->X_op != O_symbol) | |
4751 | { | |
4752 | as_bad (_("expression too complex")); | |
4753 | ep->X_op = O_constant; | |
4754 | } | |
4755 | ||
4756 | if (ep->X_op == O_constant) | |
4757 | { | |
67c0d1eb | 4758 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4759 | return; |
4760 | } | |
4761 | ||
4762 | if (mips_pic == NO_PIC) | |
4763 | { | |
4764 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 4765 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4766 | Otherwise we want |
4767 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
4768 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 4769 | If we have an addend, we always use the latter form. |
76b3015f | 4770 | |
d6bc6245 TS |
4771 | With 64bit address space and a usable $at we want |
4772 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4773 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4774 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4775 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4776 | dsll32 $reg,0 | |
3a482fd5 | 4777 | daddu $reg,$reg,$at |
76b3015f | 4778 | |
c03099e6 | 4779 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4780 | on superscalar processors. |
4781 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4782 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4783 | dsll $reg,16 | |
4784 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
4785 | dsll $reg,16 | |
4786 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
4787 | |
4788 | For GP relative symbols in 64bit address space we can use | |
4789 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4790 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 4791 | { |
6caf9ef4 TS |
4792 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
4793 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
4794 | { | |
4795 | relax_start (ep->X_add_symbol); | |
4796 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
4797 | mips_gp_register, BFD_RELOC_GPREL16); | |
4798 | relax_switch (); | |
4799 | } | |
d6bc6245 | 4800 | |
741fe287 | 4801 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 4802 | { |
67c0d1eb RS |
4803 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4804 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
4805 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4806 | BFD_RELOC_MIPS_HIGHER); | |
4807 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
4808 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
4809 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
4810 | *used_at = 1; |
4811 | } | |
4812 | else | |
4813 | { | |
67c0d1eb RS |
4814 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4815 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4816 | BFD_RELOC_MIPS_HIGHER); | |
4817 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4818 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
4819 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4820 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 4821 | } |
6caf9ef4 TS |
4822 | |
4823 | if (mips_relax.sequence) | |
4824 | relax_end (); | |
d6bc6245 | 4825 | } |
252b5132 RH |
4826 | else |
4827 | { | |
d6bc6245 | 4828 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 4829 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 4830 | { |
4d7206a2 | 4831 | relax_start (ep->X_add_symbol); |
67c0d1eb | 4832 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 4833 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 4834 | relax_switch (); |
d6bc6245 | 4835 | } |
67c0d1eb RS |
4836 | macro_build_lui (ep, reg); |
4837 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
4838 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4839 | if (mips_relax.sequence) |
4840 | relax_end (); | |
d6bc6245 | 4841 | } |
252b5132 | 4842 | } |
0a44bf69 | 4843 | else if (!mips_big_got) |
252b5132 RH |
4844 | { |
4845 | expressionS ex; | |
4846 | ||
4847 | /* If this is a reference to an external symbol, we want | |
4848 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4849 | Otherwise we want | |
4850 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4851 | nop | |
4852 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
4853 | If there is a constant, it must be added in after. |
4854 | ||
ed6fb7bd | 4855 | If we have NewABI, we want |
f5040a92 AO |
4856 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
4857 | unless we're referencing a global symbol with a non-zero | |
4858 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
4859 | if (HAVE_NEWABI) |
4860 | { | |
f5040a92 AO |
4861 | if (ep->X_add_number) |
4862 | { | |
4d7206a2 | 4863 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4864 | ep->X_add_number = 0; |
4d7206a2 | 4865 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4866 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4867 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
4868 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4869 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4870 | ex.X_op = O_constant; | |
67c0d1eb | 4871 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4872 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4873 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 4874 | relax_switch (); |
f5040a92 | 4875 | } |
67c0d1eb | 4876 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4877 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
4878 | if (mips_relax.sequence) |
4879 | relax_end (); | |
ed6fb7bd SC |
4880 | } |
4881 | else | |
4882 | { | |
f5040a92 AO |
4883 | ex.X_add_number = ep->X_add_number; |
4884 | ep->X_add_number = 0; | |
67c0d1eb RS |
4885 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4886 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 4887 | load_delay_nop (); |
4d7206a2 RS |
4888 | relax_start (ep->X_add_symbol); |
4889 | relax_switch (); | |
67c0d1eb | 4890 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4891 | BFD_RELOC_LO16); |
4d7206a2 | 4892 | relax_end (); |
ed6fb7bd | 4893 | |
f5040a92 AO |
4894 | if (ex.X_add_number != 0) |
4895 | { | |
4896 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4897 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4898 | ex.X_op = O_constant; | |
67c0d1eb | 4899 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4900 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4901 | } |
252b5132 RH |
4902 | } |
4903 | } | |
0a44bf69 | 4904 | else if (mips_big_got) |
252b5132 RH |
4905 | { |
4906 | expressionS ex; | |
252b5132 RH |
4907 | |
4908 | /* This is the large GOT case. If this is a reference to an | |
4909 | external symbol, we want | |
4910 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4911 | addu $reg,$reg,$gp | |
4912 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
4913 | |
4914 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
4915 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4916 | nop | |
4917 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 4918 | If there is a constant, it must be added in after. |
f5040a92 AO |
4919 | |
4920 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
4921 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
4922 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 4923 | */ |
438c16b8 TS |
4924 | if (HAVE_NEWABI) |
4925 | { | |
4d7206a2 | 4926 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4927 | ep->X_add_number = 0; |
4d7206a2 | 4928 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4929 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4930 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4931 | reg, reg, mips_gp_register); | |
4932 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4933 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4934 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4935 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4936 | else if (ex.X_add_number) | |
4937 | { | |
4938 | ex.X_op = O_constant; | |
67c0d1eb RS |
4939 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4940 | BFD_RELOC_LO16); | |
f5040a92 AO |
4941 | } |
4942 | ||
4943 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4944 | relax_switch (); |
67c0d1eb | 4945 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4946 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4947 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4948 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4949 | relax_end (); |
438c16b8 | 4950 | } |
252b5132 | 4951 | else |
438c16b8 | 4952 | { |
f5040a92 AO |
4953 | ex.X_add_number = ep->X_add_number; |
4954 | ep->X_add_number = 0; | |
4d7206a2 | 4955 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4956 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4957 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4958 | reg, reg, mips_gp_register); | |
4959 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4960 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4961 | relax_switch (); |
4962 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4963 | { |
4964 | /* We need a nop before loading from $gp. This special | |
4965 | check is required because the lui which starts the main | |
4966 | instruction stream does not refer to $gp, and so will not | |
4967 | insert the nop which may be required. */ | |
67c0d1eb | 4968 | macro_build (NULL, "nop", ""); |
438c16b8 | 4969 | } |
67c0d1eb | 4970 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4971 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4972 | load_delay_nop (); |
67c0d1eb | 4973 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4974 | BFD_RELOC_LO16); |
4d7206a2 | 4975 | relax_end (); |
438c16b8 | 4976 | |
f5040a92 AO |
4977 | if (ex.X_add_number != 0) |
4978 | { | |
4979 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4980 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4981 | ex.X_op = O_constant; | |
67c0d1eb RS |
4982 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4983 | BFD_RELOC_LO16); | |
f5040a92 | 4984 | } |
252b5132 RH |
4985 | } |
4986 | } | |
252b5132 RH |
4987 | else |
4988 | abort (); | |
8fc2e39e | 4989 | |
741fe287 | 4990 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 4991 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
4992 | } |
4993 | ||
ea1fb5dc RS |
4994 | /* Move the contents of register SOURCE into register DEST. */ |
4995 | ||
4996 | static void | |
67c0d1eb | 4997 | move_register (int dest, int source) |
ea1fb5dc | 4998 | { |
67c0d1eb RS |
4999 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
5000 | dest, source, 0); | |
ea1fb5dc RS |
5001 | } |
5002 | ||
4d7206a2 | 5003 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
5004 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
5005 | The two alternatives are: | |
4d7206a2 RS |
5006 | |
5007 | Global symbol Local sybmol | |
5008 | ------------- ------------ | |
5009 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
5010 | ... ... | |
5011 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
5012 | ||
5013 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
5014 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
5015 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
5016 | |
5017 | static void | |
67c0d1eb | 5018 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
5019 | { |
5020 | expressionS global; | |
5021 | ||
5022 | global = *local; | |
5023 | global.X_add_number = 0; | |
5024 | ||
5025 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
5026 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
5027 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 5028 | relax_switch (); |
67c0d1eb RS |
5029 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
5030 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
5031 | relax_end (); |
5032 | } | |
5033 | ||
5034 | static void | |
67c0d1eb | 5035 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
5036 | { |
5037 | expressionS global; | |
5038 | ||
5039 | global.X_op = O_constant; | |
5040 | global.X_op_symbol = NULL; | |
5041 | global.X_add_symbol = NULL; | |
5042 | global.X_add_number = local->X_add_number; | |
5043 | ||
5044 | relax_start (local->X_add_symbol); | |
67c0d1eb | 5045 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
5046 | dest, dest, BFD_RELOC_LO16); |
5047 | relax_switch (); | |
67c0d1eb | 5048 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
5049 | relax_end (); |
5050 | } | |
5051 | ||
f6a22291 MR |
5052 | static void |
5053 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
5054 | { | |
5055 | expressionS global; | |
5056 | int hold_mips_optimize; | |
5057 | ||
5058 | global.X_op = O_constant; | |
5059 | global.X_op_symbol = NULL; | |
5060 | global.X_add_symbol = NULL; | |
5061 | global.X_add_number = local->X_add_number; | |
5062 | ||
5063 | relax_start (local->X_add_symbol); | |
5064 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
5065 | relax_switch (); | |
5066 | /* Set mips_optimize around the lui instruction to avoid | |
5067 | inserting an unnecessary nop after the lw. */ | |
5068 | hold_mips_optimize = mips_optimize; | |
5069 | mips_optimize = 2; | |
5070 | macro_build_lui (&global, tmp); | |
5071 | mips_optimize = hold_mips_optimize; | |
5072 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
5073 | relax_end (); | |
5074 | ||
5075 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
5076 | } | |
5077 | ||
252b5132 RH |
5078 | /* |
5079 | * Build macros | |
5080 | * This routine implements the seemingly endless macro or synthesized | |
5081 | * instructions and addressing modes in the mips assembly language. Many | |
5082 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 5083 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
5084 | * this verbose method. Others are not simple macros but are more like |
5085 | * optimizing code generation. | |
5086 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 5087 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
5088 | * The ensuing load upper instructions are ommited. This implies some kind |
5089 | * of global optimization. We currently only optimize within a single macro. | |
5090 | * For many of the load and store macros if the address is specified as a | |
5091 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
5092 | * first load register 'at' with zero and use it as the base register. The | |
5093 | * mips assembler simply uses register $zero. Just one tiny optimization | |
5094 | * we're missing. | |
5095 | */ | |
5096 | static void | |
17a2f251 | 5097 | macro (struct mips_cl_insn *ip) |
252b5132 | 5098 | { |
741fe287 MR |
5099 | unsigned int treg, sreg, dreg, breg; |
5100 | unsigned int tempreg; | |
252b5132 | 5101 | int mask; |
43841e91 | 5102 | int used_at = 0; |
252b5132 RH |
5103 | expressionS expr1; |
5104 | const char *s; | |
5105 | const char *s2; | |
5106 | const char *fmt; | |
5107 | int likely = 0; | |
5108 | int dbl = 0; | |
5109 | int coproc = 0; | |
5110 | int lr = 0; | |
5111 | int imm = 0; | |
1abe91b1 | 5112 | int call = 0; |
252b5132 | 5113 | int off; |
67c0d1eb | 5114 | offsetT maxnum; |
252b5132 | 5115 | bfd_reloc_code_real_type r; |
252b5132 RH |
5116 | int hold_mips_optimize; |
5117 | ||
9c2799c2 | 5118 | gas_assert (! mips_opts.mips16); |
252b5132 | 5119 | |
bbea7ebc MR |
5120 | treg = EXTRACT_OPERAND (RT, *ip); |
5121 | dreg = EXTRACT_OPERAND (RD, *ip); | |
5122 | sreg = breg = EXTRACT_OPERAND (RS, *ip); | |
252b5132 RH |
5123 | mask = ip->insn_mo->mask; |
5124 | ||
5125 | expr1.X_op = O_constant; | |
5126 | expr1.X_op_symbol = NULL; | |
5127 | expr1.X_add_symbol = NULL; | |
5128 | expr1.X_add_number = 1; | |
5129 | ||
5130 | switch (mask) | |
5131 | { | |
5132 | case M_DABS: | |
5133 | dbl = 1; | |
5134 | case M_ABS: | |
5135 | /* bgez $a0,.+12 | |
5136 | move v0,$a0 | |
5137 | sub v0,$zero,$a0 | |
5138 | */ | |
5139 | ||
7d10b47d | 5140 | start_noreorder (); |
252b5132 RH |
5141 | |
5142 | expr1.X_add_number = 8; | |
67c0d1eb | 5143 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 5144 | if (dreg == sreg) |
a605d2b3 | 5145 | macro_build (NULL, "nop", ""); |
252b5132 | 5146 | else |
67c0d1eb RS |
5147 | move_register (dreg, sreg); |
5148 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 5149 | |
7d10b47d | 5150 | end_noreorder (); |
8fc2e39e | 5151 | break; |
252b5132 RH |
5152 | |
5153 | case M_ADD_I: | |
5154 | s = "addi"; | |
5155 | s2 = "add"; | |
5156 | goto do_addi; | |
5157 | case M_ADDU_I: | |
5158 | s = "addiu"; | |
5159 | s2 = "addu"; | |
5160 | goto do_addi; | |
5161 | case M_DADD_I: | |
5162 | dbl = 1; | |
5163 | s = "daddi"; | |
5164 | s2 = "dadd"; | |
5165 | goto do_addi; | |
5166 | case M_DADDU_I: | |
5167 | dbl = 1; | |
5168 | s = "daddiu"; | |
5169 | s2 = "daddu"; | |
5170 | do_addi: | |
5171 | if (imm_expr.X_op == O_constant | |
5172 | && imm_expr.X_add_number >= -0x8000 | |
5173 | && imm_expr.X_add_number < 0x8000) | |
5174 | { | |
67c0d1eb | 5175 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 5176 | break; |
252b5132 | 5177 | } |
8fc2e39e | 5178 | used_at = 1; |
67c0d1eb RS |
5179 | load_register (AT, &imm_expr, dbl); |
5180 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
5181 | break; |
5182 | ||
5183 | case M_AND_I: | |
5184 | s = "andi"; | |
5185 | s2 = "and"; | |
5186 | goto do_bit; | |
5187 | case M_OR_I: | |
5188 | s = "ori"; | |
5189 | s2 = "or"; | |
5190 | goto do_bit; | |
5191 | case M_NOR_I: | |
5192 | s = ""; | |
5193 | s2 = "nor"; | |
5194 | goto do_bit; | |
5195 | case M_XOR_I: | |
5196 | s = "xori"; | |
5197 | s2 = "xor"; | |
5198 | do_bit: | |
5199 | if (imm_expr.X_op == O_constant | |
5200 | && imm_expr.X_add_number >= 0 | |
5201 | && imm_expr.X_add_number < 0x10000) | |
5202 | { | |
5203 | if (mask != M_NOR_I) | |
67c0d1eb | 5204 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
5205 | else |
5206 | { | |
67c0d1eb RS |
5207 | macro_build (&imm_expr, "ori", "t,r,i", |
5208 | treg, sreg, BFD_RELOC_LO16); | |
5209 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 5210 | } |
8fc2e39e | 5211 | break; |
252b5132 RH |
5212 | } |
5213 | ||
8fc2e39e | 5214 | used_at = 1; |
67c0d1eb RS |
5215 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5216 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
5217 | break; |
5218 | ||
8b082fb1 TS |
5219 | case M_BALIGN: |
5220 | switch (imm_expr.X_add_number) | |
5221 | { | |
5222 | case 0: | |
5223 | macro_build (NULL, "nop", ""); | |
5224 | break; | |
5225 | case 2: | |
5226 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
5227 | break; | |
5228 | default: | |
5229 | macro_build (NULL, "balign", "t,s,2", treg, sreg, | |
90ecf173 | 5230 | (int) imm_expr.X_add_number); |
8b082fb1 TS |
5231 | break; |
5232 | } | |
5233 | break; | |
5234 | ||
252b5132 RH |
5235 | case M_BEQ_I: |
5236 | s = "beq"; | |
5237 | goto beq_i; | |
5238 | case M_BEQL_I: | |
5239 | s = "beql"; | |
5240 | likely = 1; | |
5241 | goto beq_i; | |
5242 | case M_BNE_I: | |
5243 | s = "bne"; | |
5244 | goto beq_i; | |
5245 | case M_BNEL_I: | |
5246 | s = "bnel"; | |
5247 | likely = 1; | |
5248 | beq_i: | |
5249 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5250 | { | |
c80c840e | 5251 | macro_build (&offset_expr, s, "s,t,p", sreg, ZERO); |
8fc2e39e | 5252 | break; |
252b5132 | 5253 | } |
8fc2e39e | 5254 | used_at = 1; |
67c0d1eb RS |
5255 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5256 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
5257 | break; |
5258 | ||
5259 | case M_BGEL: | |
5260 | likely = 1; | |
5261 | case M_BGE: | |
5262 | if (treg == 0) | |
5263 | { | |
67c0d1eb | 5264 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 5265 | break; |
252b5132 RH |
5266 | } |
5267 | if (sreg == 0) | |
5268 | { | |
67c0d1eb | 5269 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 5270 | break; |
252b5132 | 5271 | } |
8fc2e39e | 5272 | used_at = 1; |
67c0d1eb | 5273 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
c80c840e | 5274 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5275 | break; |
5276 | ||
5277 | case M_BGTL_I: | |
5278 | likely = 1; | |
5279 | case M_BGT_I: | |
90ecf173 | 5280 | /* Check for > max integer. */ |
252b5132 | 5281 | maxnum = 0x7fffffff; |
ca4e0257 | 5282 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
5283 | { |
5284 | maxnum <<= 16; | |
5285 | maxnum |= 0xffff; | |
5286 | maxnum <<= 16; | |
5287 | maxnum |= 0xffff; | |
5288 | } | |
5289 | if (imm_expr.X_op == O_constant | |
5290 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 5291 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5292 | { |
5293 | do_false: | |
90ecf173 | 5294 | /* Result is always false. */ |
252b5132 | 5295 | if (! likely) |
a605d2b3 | 5296 | macro_build (NULL, "nop", ""); |
252b5132 | 5297 | else |
c80c840e | 5298 | macro_build (&offset_expr, "bnel", "s,t,p", ZERO, ZERO); |
8fc2e39e | 5299 | break; |
252b5132 RH |
5300 | } |
5301 | if (imm_expr.X_op != O_constant) | |
5302 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5303 | ++imm_expr.X_add_number; |
252b5132 RH |
5304 | /* FALLTHROUGH */ |
5305 | case M_BGE_I: | |
5306 | case M_BGEL_I: | |
5307 | if (mask == M_BGEL_I) | |
5308 | likely = 1; | |
5309 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5310 | { | |
67c0d1eb | 5311 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 5312 | break; |
252b5132 RH |
5313 | } |
5314 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5315 | { | |
67c0d1eb | 5316 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 5317 | break; |
252b5132 RH |
5318 | } |
5319 | maxnum = 0x7fffffff; | |
ca4e0257 | 5320 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
5321 | { |
5322 | maxnum <<= 16; | |
5323 | maxnum |= 0xffff; | |
5324 | maxnum <<= 16; | |
5325 | maxnum |= 0xffff; | |
5326 | } | |
5327 | maxnum = - maxnum - 1; | |
5328 | if (imm_expr.X_op == O_constant | |
5329 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 5330 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5331 | { |
5332 | do_true: | |
5333 | /* result is always true */ | |
5334 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 5335 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5336 | break; |
252b5132 | 5337 | } |
8fc2e39e | 5338 | used_at = 1; |
67c0d1eb | 5339 | set_at (sreg, 0); |
c80c840e | 5340 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5341 | break; |
5342 | ||
5343 | case M_BGEUL: | |
5344 | likely = 1; | |
5345 | case M_BGEU: | |
5346 | if (treg == 0) | |
5347 | goto do_true; | |
5348 | if (sreg == 0) | |
5349 | { | |
67c0d1eb | 5350 | macro_build (&offset_expr, likely ? "beql" : "beq", |
c80c840e | 5351 | "s,t,p", ZERO, treg); |
8fc2e39e | 5352 | break; |
252b5132 | 5353 | } |
8fc2e39e | 5354 | used_at = 1; |
67c0d1eb | 5355 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
c80c840e | 5356 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5357 | break; |
5358 | ||
5359 | case M_BGTUL_I: | |
5360 | likely = 1; | |
5361 | case M_BGTU_I: | |
5362 | if (sreg == 0 | |
ca4e0257 | 5363 | || (HAVE_32BIT_GPRS |
252b5132 | 5364 | && imm_expr.X_op == O_constant |
f01dc953 | 5365 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
5366 | goto do_false; |
5367 | if (imm_expr.X_op != O_constant) | |
5368 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5369 | ++imm_expr.X_add_number; |
252b5132 RH |
5370 | /* FALLTHROUGH */ |
5371 | case M_BGEU_I: | |
5372 | case M_BGEUL_I: | |
5373 | if (mask == M_BGEUL_I) | |
5374 | likely = 1; | |
5375 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5376 | goto do_true; | |
5377 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5378 | { | |
67c0d1eb | 5379 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
c80c840e | 5380 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5381 | break; |
252b5132 | 5382 | } |
8fc2e39e | 5383 | used_at = 1; |
67c0d1eb | 5384 | set_at (sreg, 1); |
c80c840e | 5385 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5386 | break; |
5387 | ||
5388 | case M_BGTL: | |
5389 | likely = 1; | |
5390 | case M_BGT: | |
5391 | if (treg == 0) | |
5392 | { | |
67c0d1eb | 5393 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 5394 | break; |
252b5132 RH |
5395 | } |
5396 | if (sreg == 0) | |
5397 | { | |
67c0d1eb | 5398 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 5399 | break; |
252b5132 | 5400 | } |
8fc2e39e | 5401 | used_at = 1; |
67c0d1eb | 5402 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
c80c840e | 5403 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5404 | break; |
5405 | ||
5406 | case M_BGTUL: | |
5407 | likely = 1; | |
5408 | case M_BGTU: | |
5409 | if (treg == 0) | |
5410 | { | |
67c0d1eb | 5411 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
c80c840e | 5412 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5413 | break; |
252b5132 RH |
5414 | } |
5415 | if (sreg == 0) | |
5416 | goto do_false; | |
8fc2e39e | 5417 | used_at = 1; |
67c0d1eb | 5418 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
c80c840e | 5419 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5420 | break; |
5421 | ||
5422 | case M_BLEL: | |
5423 | likely = 1; | |
5424 | case M_BLE: | |
5425 | if (treg == 0) | |
5426 | { | |
67c0d1eb | 5427 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 5428 | break; |
252b5132 RH |
5429 | } |
5430 | if (sreg == 0) | |
5431 | { | |
67c0d1eb | 5432 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 5433 | break; |
252b5132 | 5434 | } |
8fc2e39e | 5435 | used_at = 1; |
67c0d1eb | 5436 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
c80c840e | 5437 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5438 | break; |
5439 | ||
5440 | case M_BLEL_I: | |
5441 | likely = 1; | |
5442 | case M_BLE_I: | |
5443 | maxnum = 0x7fffffff; | |
ca4e0257 | 5444 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
5445 | { |
5446 | maxnum <<= 16; | |
5447 | maxnum |= 0xffff; | |
5448 | maxnum <<= 16; | |
5449 | maxnum |= 0xffff; | |
5450 | } | |
5451 | if (imm_expr.X_op == O_constant | |
5452 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 5453 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5454 | goto do_true; |
5455 | if (imm_expr.X_op != O_constant) | |
5456 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5457 | ++imm_expr.X_add_number; |
252b5132 RH |
5458 | /* FALLTHROUGH */ |
5459 | case M_BLT_I: | |
5460 | case M_BLTL_I: | |
5461 | if (mask == M_BLTL_I) | |
5462 | likely = 1; | |
5463 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5464 | { | |
67c0d1eb | 5465 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 5466 | break; |
252b5132 RH |
5467 | } |
5468 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5469 | { | |
67c0d1eb | 5470 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 5471 | break; |
252b5132 | 5472 | } |
8fc2e39e | 5473 | used_at = 1; |
67c0d1eb | 5474 | set_at (sreg, 0); |
c80c840e | 5475 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5476 | break; |
5477 | ||
5478 | case M_BLEUL: | |
5479 | likely = 1; | |
5480 | case M_BLEU: | |
5481 | if (treg == 0) | |
5482 | { | |
67c0d1eb | 5483 | macro_build (&offset_expr, likely ? "beql" : "beq", |
c80c840e | 5484 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5485 | break; |
252b5132 RH |
5486 | } |
5487 | if (sreg == 0) | |
5488 | goto do_true; | |
8fc2e39e | 5489 | used_at = 1; |
67c0d1eb | 5490 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
c80c840e | 5491 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5492 | break; |
5493 | ||
5494 | case M_BLEUL_I: | |
5495 | likely = 1; | |
5496 | case M_BLEU_I: | |
5497 | if (sreg == 0 | |
ca4e0257 | 5498 | || (HAVE_32BIT_GPRS |
252b5132 | 5499 | && imm_expr.X_op == O_constant |
f01dc953 | 5500 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
5501 | goto do_true; |
5502 | if (imm_expr.X_op != O_constant) | |
5503 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5504 | ++imm_expr.X_add_number; |
252b5132 RH |
5505 | /* FALLTHROUGH */ |
5506 | case M_BLTU_I: | |
5507 | case M_BLTUL_I: | |
5508 | if (mask == M_BLTUL_I) | |
5509 | likely = 1; | |
5510 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5511 | goto do_false; | |
5512 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5513 | { | |
67c0d1eb | 5514 | macro_build (&offset_expr, likely ? "beql" : "beq", |
c80c840e | 5515 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5516 | break; |
252b5132 | 5517 | } |
8fc2e39e | 5518 | used_at = 1; |
67c0d1eb | 5519 | set_at (sreg, 1); |
c80c840e | 5520 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5521 | break; |
5522 | ||
5523 | case M_BLTL: | |
5524 | likely = 1; | |
5525 | case M_BLT: | |
5526 | if (treg == 0) | |
5527 | { | |
67c0d1eb | 5528 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 5529 | break; |
252b5132 RH |
5530 | } |
5531 | if (sreg == 0) | |
5532 | { | |
67c0d1eb | 5533 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 5534 | break; |
252b5132 | 5535 | } |
8fc2e39e | 5536 | used_at = 1; |
67c0d1eb | 5537 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
c80c840e | 5538 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5539 | break; |
5540 | ||
5541 | case M_BLTUL: | |
5542 | likely = 1; | |
5543 | case M_BLTU: | |
5544 | if (treg == 0) | |
5545 | goto do_false; | |
5546 | if (sreg == 0) | |
5547 | { | |
67c0d1eb | 5548 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
c80c840e | 5549 | "s,t,p", ZERO, treg); |
8fc2e39e | 5550 | break; |
252b5132 | 5551 | } |
8fc2e39e | 5552 | used_at = 1; |
67c0d1eb | 5553 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
c80c840e | 5554 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5555 | break; |
5556 | ||
5f74bc13 CD |
5557 | case M_DEXT: |
5558 | { | |
d5818fca MR |
5559 | /* Use unsigned arithmetic. */ |
5560 | addressT pos; | |
5561 | addressT size; | |
5f74bc13 | 5562 | |
90ecf173 | 5563 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
5564 | { |
5565 | as_bad (_("Unsupported large constant")); | |
5566 | pos = size = 1; | |
5567 | } | |
5568 | else | |
5569 | { | |
d5818fca MR |
5570 | pos = imm_expr.X_add_number; |
5571 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
5572 | } |
5573 | ||
5574 | if (pos > 63) | |
5575 | { | |
d5818fca | 5576 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
5577 | pos = 1; |
5578 | } | |
90ecf173 | 5579 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
5580 | { |
5581 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 5582 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
5583 | size = 1; |
5584 | } | |
5585 | ||
5586 | if (size <= 32 && pos < 32) | |
5587 | { | |
5588 | s = "dext"; | |
5589 | fmt = "t,r,+A,+C"; | |
5590 | } | |
5591 | else if (size <= 32) | |
5592 | { | |
5593 | s = "dextu"; | |
5594 | fmt = "t,r,+E,+H"; | |
5595 | } | |
5596 | else | |
5597 | { | |
5598 | s = "dextm"; | |
5599 | fmt = "t,r,+A,+G"; | |
5600 | } | |
d5818fca MR |
5601 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
5602 | (int) (size - 1)); | |
5f74bc13 | 5603 | } |
8fc2e39e | 5604 | break; |
5f74bc13 CD |
5605 | |
5606 | case M_DINS: | |
5607 | { | |
d5818fca MR |
5608 | /* Use unsigned arithmetic. */ |
5609 | addressT pos; | |
5610 | addressT size; | |
5f74bc13 | 5611 | |
90ecf173 | 5612 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
5613 | { |
5614 | as_bad (_("Unsupported large constant")); | |
5615 | pos = size = 1; | |
5616 | } | |
5617 | else | |
5618 | { | |
d5818fca MR |
5619 | pos = imm_expr.X_add_number; |
5620 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
5621 | } |
5622 | ||
5623 | if (pos > 63) | |
5624 | { | |
d5818fca | 5625 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
5626 | pos = 1; |
5627 | } | |
90ecf173 | 5628 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
5629 | { |
5630 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 5631 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
5632 | size = 1; |
5633 | } | |
5634 | ||
5635 | if (pos < 32 && (pos + size - 1) < 32) | |
5636 | { | |
5637 | s = "dins"; | |
5638 | fmt = "t,r,+A,+B"; | |
5639 | } | |
5640 | else if (pos >= 32) | |
5641 | { | |
5642 | s = "dinsu"; | |
5643 | fmt = "t,r,+E,+F"; | |
5644 | } | |
5645 | else | |
5646 | { | |
5647 | s = "dinsm"; | |
5648 | fmt = "t,r,+A,+F"; | |
5649 | } | |
750bdd57 AS |
5650 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
5651 | (int) (pos + size - 1)); | |
5f74bc13 | 5652 | } |
8fc2e39e | 5653 | break; |
5f74bc13 | 5654 | |
252b5132 RH |
5655 | case M_DDIV_3: |
5656 | dbl = 1; | |
5657 | case M_DIV_3: | |
5658 | s = "mflo"; | |
5659 | goto do_div3; | |
5660 | case M_DREM_3: | |
5661 | dbl = 1; | |
5662 | case M_REM_3: | |
5663 | s = "mfhi"; | |
5664 | do_div3: | |
5665 | if (treg == 0) | |
5666 | { | |
5667 | as_warn (_("Divide by zero.")); | |
5668 | if (mips_trap) | |
c80c840e | 5669 | macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7); |
252b5132 | 5670 | else |
67c0d1eb | 5671 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5672 | break; |
252b5132 RH |
5673 | } |
5674 | ||
7d10b47d | 5675 | start_noreorder (); |
252b5132 RH |
5676 | if (mips_trap) |
5677 | { | |
c80c840e | 5678 | macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7); |
67c0d1eb | 5679 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
5680 | } |
5681 | else | |
5682 | { | |
5683 | expr1.X_add_number = 8; | |
c80c840e | 5684 | macro_build (&expr1, "bne", "s,t,p", treg, ZERO); |
67c0d1eb RS |
5685 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
5686 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
5687 | } |
5688 | expr1.X_add_number = -1; | |
8fc2e39e | 5689 | used_at = 1; |
f6a22291 | 5690 | load_register (AT, &expr1, dbl); |
252b5132 | 5691 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 5692 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
5693 | if (dbl) |
5694 | { | |
5695 | expr1.X_add_number = 1; | |
f6a22291 | 5696 | load_register (AT, &expr1, dbl); |
67c0d1eb | 5697 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
5698 | } |
5699 | else | |
5700 | { | |
5701 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 5702 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
5703 | } |
5704 | if (mips_trap) | |
5705 | { | |
67c0d1eb | 5706 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
5707 | /* We want to close the noreorder block as soon as possible, so |
5708 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5709 | end_noreorder (); |
252b5132 RH |
5710 | } |
5711 | else | |
5712 | { | |
5713 | expr1.X_add_number = 8; | |
67c0d1eb | 5714 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
a605d2b3 | 5715 | macro_build (NULL, "nop", ""); |
252b5132 RH |
5716 | |
5717 | /* We want to close the noreorder block as soon as possible, so | |
5718 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5719 | end_noreorder (); |
252b5132 | 5720 | |
67c0d1eb | 5721 | macro_build (NULL, "break", "c", 6); |
252b5132 | 5722 | } |
67c0d1eb | 5723 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
5724 | break; |
5725 | ||
5726 | case M_DIV_3I: | |
5727 | s = "div"; | |
5728 | s2 = "mflo"; | |
5729 | goto do_divi; | |
5730 | case M_DIVU_3I: | |
5731 | s = "divu"; | |
5732 | s2 = "mflo"; | |
5733 | goto do_divi; | |
5734 | case M_REM_3I: | |
5735 | s = "div"; | |
5736 | s2 = "mfhi"; | |
5737 | goto do_divi; | |
5738 | case M_REMU_3I: | |
5739 | s = "divu"; | |
5740 | s2 = "mfhi"; | |
5741 | goto do_divi; | |
5742 | case M_DDIV_3I: | |
5743 | dbl = 1; | |
5744 | s = "ddiv"; | |
5745 | s2 = "mflo"; | |
5746 | goto do_divi; | |
5747 | case M_DDIVU_3I: | |
5748 | dbl = 1; | |
5749 | s = "ddivu"; | |
5750 | s2 = "mflo"; | |
5751 | goto do_divi; | |
5752 | case M_DREM_3I: | |
5753 | dbl = 1; | |
5754 | s = "ddiv"; | |
5755 | s2 = "mfhi"; | |
5756 | goto do_divi; | |
5757 | case M_DREMU_3I: | |
5758 | dbl = 1; | |
5759 | s = "ddivu"; | |
5760 | s2 = "mfhi"; | |
5761 | do_divi: | |
5762 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5763 | { | |
5764 | as_warn (_("Divide by zero.")); | |
5765 | if (mips_trap) | |
c80c840e | 5766 | macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7); |
252b5132 | 5767 | else |
67c0d1eb | 5768 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5769 | break; |
252b5132 RH |
5770 | } |
5771 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5772 | { | |
5773 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 5774 | move_register (dreg, sreg); |
252b5132 | 5775 | else |
c80c840e | 5776 | move_register (dreg, ZERO); |
8fc2e39e | 5777 | break; |
252b5132 RH |
5778 | } |
5779 | if (imm_expr.X_op == O_constant | |
5780 | && imm_expr.X_add_number == -1 | |
5781 | && s[strlen (s) - 1] != 'u') | |
5782 | { | |
5783 | if (strcmp (s2, "mflo") == 0) | |
5784 | { | |
67c0d1eb | 5785 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
5786 | } |
5787 | else | |
c80c840e | 5788 | move_register (dreg, ZERO); |
8fc2e39e | 5789 | break; |
252b5132 RH |
5790 | } |
5791 | ||
8fc2e39e | 5792 | used_at = 1; |
67c0d1eb RS |
5793 | load_register (AT, &imm_expr, dbl); |
5794 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
5795 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
5796 | break; |
5797 | ||
5798 | case M_DIVU_3: | |
5799 | s = "divu"; | |
5800 | s2 = "mflo"; | |
5801 | goto do_divu3; | |
5802 | case M_REMU_3: | |
5803 | s = "divu"; | |
5804 | s2 = "mfhi"; | |
5805 | goto do_divu3; | |
5806 | case M_DDIVU_3: | |
5807 | s = "ddivu"; | |
5808 | s2 = "mflo"; | |
5809 | goto do_divu3; | |
5810 | case M_DREMU_3: | |
5811 | s = "ddivu"; | |
5812 | s2 = "mfhi"; | |
5813 | do_divu3: | |
7d10b47d | 5814 | start_noreorder (); |
252b5132 RH |
5815 | if (mips_trap) |
5816 | { | |
c80c840e | 5817 | macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7); |
67c0d1eb | 5818 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
5819 | /* We want to close the noreorder block as soon as possible, so |
5820 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5821 | end_noreorder (); |
252b5132 RH |
5822 | } |
5823 | else | |
5824 | { | |
5825 | expr1.X_add_number = 8; | |
c80c840e | 5826 | macro_build (&expr1, "bne", "s,t,p", treg, ZERO); |
67c0d1eb | 5827 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
5828 | |
5829 | /* We want to close the noreorder block as soon as possible, so | |
5830 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5831 | end_noreorder (); |
67c0d1eb | 5832 | macro_build (NULL, "break", "c", 7); |
252b5132 | 5833 | } |
67c0d1eb | 5834 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 5835 | break; |
252b5132 | 5836 | |
1abe91b1 MR |
5837 | case M_DLCA_AB: |
5838 | dbl = 1; | |
5839 | case M_LCA_AB: | |
5840 | call = 1; | |
5841 | goto do_la; | |
252b5132 RH |
5842 | case M_DLA_AB: |
5843 | dbl = 1; | |
5844 | case M_LA_AB: | |
1abe91b1 | 5845 | do_la: |
252b5132 RH |
5846 | /* Load the address of a symbol into a register. If breg is not |
5847 | zero, we then add a base register to it. */ | |
5848 | ||
3bec30a8 TS |
5849 | if (dbl && HAVE_32BIT_GPRS) |
5850 | as_warn (_("dla used to load 32-bit register")); | |
5851 | ||
90ecf173 | 5852 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
5853 | as_warn (_("la used to load 64-bit address")); |
5854 | ||
0c11417f MR |
5855 | if (offset_expr.X_op == O_constant |
5856 | && offset_expr.X_add_number >= -0x8000 | |
5857 | && offset_expr.X_add_number < 0x8000) | |
5858 | { | |
aed1a261 | 5859 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 5860 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 5861 | break; |
0c11417f MR |
5862 | } |
5863 | ||
741fe287 | 5864 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
5865 | { |
5866 | tempreg = AT; | |
5867 | used_at = 1; | |
5868 | } | |
5869 | else | |
5870 | { | |
5871 | tempreg = treg; | |
afdbd6d0 CD |
5872 | } |
5873 | ||
252b5132 RH |
5874 | if (offset_expr.X_op != O_symbol |
5875 | && offset_expr.X_op != O_constant) | |
5876 | { | |
f71d0d44 | 5877 | as_bad (_("Expression too complex")); |
252b5132 RH |
5878 | offset_expr.X_op = O_constant; |
5879 | } | |
5880 | ||
252b5132 | 5881 | if (offset_expr.X_op == O_constant) |
aed1a261 | 5882 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5883 | else if (mips_pic == NO_PIC) |
5884 | { | |
d6bc6245 | 5885 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 5886 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5887 | Otherwise we want |
5888 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5889 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5890 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 5891 | so we may as well always use the latter form. |
76b3015f | 5892 | |
6caf9ef4 TS |
5893 | With 64bit address space and a usable $at we want |
5894 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5895 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5896 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5897 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5898 | dsll32 $tempreg,0 | |
5899 | daddu $tempreg,$tempreg,$at | |
5900 | ||
5901 | If $at is already in use, we use a path which is suboptimal | |
5902 | on superscalar processors. | |
5903 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5904 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5905 | dsll $tempreg,16 | |
5906 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5907 | dsll $tempreg,16 | |
5908 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
5909 | ||
5910 | For GP relative symbols in 64bit address space we can use | |
5911 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5912 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 5913 | { |
6caf9ef4 TS |
5914 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
5915 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5916 | { | |
5917 | relax_start (offset_expr.X_add_symbol); | |
5918 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5919 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
5920 | relax_switch (); | |
5921 | } | |
d6bc6245 | 5922 | |
741fe287 | 5923 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 5924 | { |
67c0d1eb | 5925 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5926 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5927 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5928 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 5929 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5930 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 5931 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5932 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
5933 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
5934 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
5935 | used_at = 1; |
5936 | } | |
5937 | else | |
5938 | { | |
67c0d1eb | 5939 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5940 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5941 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5942 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
5943 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5944 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5945 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
5946 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5947 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5948 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 5949 | } |
6caf9ef4 TS |
5950 | |
5951 | if (mips_relax.sequence) | |
5952 | relax_end (); | |
98d3f06f KH |
5953 | } |
5954 | else | |
5955 | { | |
5956 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 5957 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 5958 | { |
4d7206a2 | 5959 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5960 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5961 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5962 | relax_switch (); |
98d3f06f | 5963 | } |
6943caf0 | 5964 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 5965 | as_bad (_("Offset too large")); |
67c0d1eb RS |
5966 | macro_build_lui (&offset_expr, tempreg); |
5967 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5968 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5969 | if (mips_relax.sequence) |
5970 | relax_end (); | |
98d3f06f | 5971 | } |
252b5132 | 5972 | } |
0a44bf69 | 5973 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 5974 | { |
9117d219 NC |
5975 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5976 | ||
252b5132 RH |
5977 | /* If this is a reference to an external symbol, and there |
5978 | is no constant, we want | |
5979 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5980 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5981 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5982 | For a local symbol, we want |
5983 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5984 | nop | |
5985 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5986 | ||
5987 | If we have a small constant, and this is a reference to | |
5988 | an external symbol, we want | |
5989 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5990 | nop | |
5991 | addiu $tempreg,$tempreg,<constant> | |
5992 | For a local symbol, we want the same instruction | |
5993 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5994 | addiu instruction. | |
5995 | ||
5996 | If we have a large constant, and this is a reference to | |
5997 | an external symbol, we want | |
5998 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5999 | lui $at,<hiconstant> | |
6000 | addiu $at,$at,<loconstant> | |
6001 | addu $tempreg,$tempreg,$at | |
6002 | For a local symbol, we want the same instruction | |
6003 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 6004 | addiu instruction. |
ed6fb7bd SC |
6005 | */ |
6006 | ||
4d7206a2 | 6007 | if (offset_expr.X_add_number == 0) |
252b5132 | 6008 | { |
0a44bf69 RS |
6009 | if (mips_pic == SVR4_PIC |
6010 | && breg == 0 | |
6011 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
6012 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
6013 | ||
6014 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
6015 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6016 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 6017 | if (breg != 0) |
252b5132 RH |
6018 | { |
6019 | /* We're going to put in an addu instruction using | |
6020 | tempreg, so we may as well insert the nop right | |
6021 | now. */ | |
269137b2 | 6022 | load_delay_nop (); |
252b5132 | 6023 | } |
4d7206a2 | 6024 | relax_switch (); |
67c0d1eb RS |
6025 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6026 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6027 | load_delay_nop (); |
67c0d1eb RS |
6028 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6029 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6030 | relax_end (); |
252b5132 RH |
6031 | /* FIXME: If breg == 0, and the next instruction uses |
6032 | $tempreg, then if this variant case is used an extra | |
6033 | nop will be generated. */ | |
6034 | } | |
4d7206a2 RS |
6035 | else if (offset_expr.X_add_number >= -0x8000 |
6036 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 6037 | { |
67c0d1eb | 6038 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 6039 | load_delay_nop (); |
67c0d1eb | 6040 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
6041 | } |
6042 | else | |
6043 | { | |
4d7206a2 RS |
6044 | expr1.X_add_number = offset_expr.X_add_number; |
6045 | offset_expr.X_add_number = | |
6046 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 6047 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 6048 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
6049 | /* If we are going to add in a base register, and the |
6050 | target register and the base register are the same, | |
6051 | then we are using AT as a temporary register. Since | |
6052 | we want to load the constant into AT, we add our | |
6053 | current AT (from the global offset table) and the | |
6054 | register into the register now, and pretend we were | |
6055 | not using a base register. */ | |
67c0d1eb | 6056 | if (breg == treg) |
252b5132 | 6057 | { |
269137b2 | 6058 | load_delay_nop (); |
67c0d1eb | 6059 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6060 | treg, AT, breg); |
252b5132 RH |
6061 | breg = 0; |
6062 | tempreg = treg; | |
252b5132 | 6063 | } |
f6a22291 | 6064 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
6065 | used_at = 1; |
6066 | } | |
6067 | } | |
0a44bf69 | 6068 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 6069 | { |
67c0d1eb | 6070 | int add_breg_early = 0; |
f5040a92 AO |
6071 | |
6072 | /* If this is a reference to an external, and there is no | |
6073 | constant, or local symbol (*), with or without a | |
6074 | constant, we want | |
6075 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 6076 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
6077 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
6078 | ||
6079 | If we have a small constant, and this is a reference to | |
6080 | an external symbol, we want | |
6081 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
6082 | addiu $tempreg,$tempreg,<constant> | |
6083 | ||
6084 | If we have a large constant, and this is a reference to | |
6085 | an external symbol, we want | |
6086 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
6087 | lui $at,<hiconstant> | |
6088 | addiu $at,$at,<loconstant> | |
6089 | addu $tempreg,$tempreg,$at | |
6090 | ||
6091 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
6092 | local symbols, even though it introduces an additional | |
6093 | instruction. */ | |
6094 | ||
f5040a92 AO |
6095 | if (offset_expr.X_add_number) |
6096 | { | |
4d7206a2 | 6097 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6098 | offset_expr.X_add_number = 0; |
6099 | ||
4d7206a2 | 6100 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6101 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6102 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
6103 | |
6104 | if (expr1.X_add_number >= -0x8000 | |
6105 | && expr1.X_add_number < 0x8000) | |
6106 | { | |
67c0d1eb RS |
6107 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
6108 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 6109 | } |
ecd13cd3 | 6110 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 6111 | { |
f5040a92 AO |
6112 | /* If we are going to add in a base register, and the |
6113 | target register and the base register are the same, | |
6114 | then we are using AT as a temporary register. Since | |
6115 | we want to load the constant into AT, we add our | |
6116 | current AT (from the global offset table) and the | |
6117 | register into the register now, and pretend we were | |
6118 | not using a base register. */ | |
6119 | if (breg != treg) | |
6120 | dreg = tempreg; | |
6121 | else | |
6122 | { | |
9c2799c2 | 6123 | gas_assert (tempreg == AT); |
67c0d1eb RS |
6124 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6125 | treg, AT, breg); | |
f5040a92 | 6126 | dreg = treg; |
67c0d1eb | 6127 | add_breg_early = 1; |
f5040a92 AO |
6128 | } |
6129 | ||
f6a22291 | 6130 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 6131 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6132 | dreg, dreg, AT); |
f5040a92 | 6133 | |
f5040a92 AO |
6134 | used_at = 1; |
6135 | } | |
6136 | else | |
6137 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
6138 | ||
4d7206a2 | 6139 | relax_switch (); |
f5040a92 AO |
6140 | offset_expr.X_add_number = expr1.X_add_number; |
6141 | ||
67c0d1eb RS |
6142 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6143 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
6144 | if (add_breg_early) | |
f5040a92 | 6145 | { |
67c0d1eb | 6146 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 6147 | treg, tempreg, breg); |
f5040a92 AO |
6148 | breg = 0; |
6149 | tempreg = treg; | |
6150 | } | |
4d7206a2 | 6151 | relax_end (); |
f5040a92 | 6152 | } |
4d7206a2 | 6153 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 6154 | { |
4d7206a2 | 6155 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6156 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6157 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 6158 | relax_switch (); |
67c0d1eb RS |
6159 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6160 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 6161 | relax_end (); |
f5040a92 | 6162 | } |
4d7206a2 | 6163 | else |
f5040a92 | 6164 | { |
67c0d1eb RS |
6165 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6166 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
6167 | } |
6168 | } | |
0a44bf69 | 6169 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 6170 | { |
67c0d1eb | 6171 | int gpdelay; |
9117d219 NC |
6172 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
6173 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 6174 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
6175 | |
6176 | /* This is the large GOT case. If this is a reference to an | |
6177 | external symbol, and there is no constant, we want | |
6178 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6179 | addu $tempreg,$tempreg,$gp | |
6180 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 6181 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
6182 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
6183 | addu $tempreg,$tempreg,$gp | |
6184 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
6185 | For a local symbol, we want |
6186 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6187 | nop | |
6188 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6189 | ||
6190 | If we have a small constant, and this is a reference to | |
6191 | an external symbol, we want | |
6192 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6193 | addu $tempreg,$tempreg,$gp | |
6194 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6195 | nop | |
6196 | addiu $tempreg,$tempreg,<constant> | |
6197 | For a local symbol, we want | |
6198 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6199 | nop | |
6200 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
6201 | ||
6202 | If we have a large constant, and this is a reference to | |
6203 | an external symbol, we want | |
6204 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6205 | addu $tempreg,$tempreg,$gp | |
6206 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6207 | lui $at,<hiconstant> | |
6208 | addiu $at,$at,<loconstant> | |
6209 | addu $tempreg,$tempreg,$at | |
6210 | For a local symbol, we want | |
6211 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6212 | lui $at,<hiconstant> | |
6213 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
6214 | addu $tempreg,$tempreg,$at | |
f5040a92 | 6215 | */ |
438c16b8 | 6216 | |
252b5132 RH |
6217 | expr1.X_add_number = offset_expr.X_add_number; |
6218 | offset_expr.X_add_number = 0; | |
4d7206a2 | 6219 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6220 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
6221 | if (expr1.X_add_number == 0 && breg == 0 |
6222 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
6223 | { |
6224 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
6225 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
6226 | } | |
67c0d1eb RS |
6227 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
6228 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6229 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 6230 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6231 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
6232 | if (expr1.X_add_number == 0) |
6233 | { | |
67c0d1eb | 6234 | if (breg != 0) |
252b5132 RH |
6235 | { |
6236 | /* We're going to put in an addu instruction using | |
6237 | tempreg, so we may as well insert the nop right | |
6238 | now. */ | |
269137b2 | 6239 | load_delay_nop (); |
252b5132 | 6240 | } |
252b5132 RH |
6241 | } |
6242 | else if (expr1.X_add_number >= -0x8000 | |
6243 | && expr1.X_add_number < 0x8000) | |
6244 | { | |
269137b2 | 6245 | load_delay_nop (); |
67c0d1eb | 6246 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6247 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
6248 | } |
6249 | else | |
6250 | { | |
252b5132 RH |
6251 | /* If we are going to add in a base register, and the |
6252 | target register and the base register are the same, | |
6253 | then we are using AT as a temporary register. Since | |
6254 | we want to load the constant into AT, we add our | |
6255 | current AT (from the global offset table) and the | |
6256 | register into the register now, and pretend we were | |
6257 | not using a base register. */ | |
6258 | if (breg != treg) | |
67c0d1eb | 6259 | dreg = tempreg; |
252b5132 RH |
6260 | else |
6261 | { | |
9c2799c2 | 6262 | gas_assert (tempreg == AT); |
269137b2 | 6263 | load_delay_nop (); |
67c0d1eb | 6264 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6265 | treg, AT, breg); |
252b5132 | 6266 | dreg = treg; |
252b5132 RH |
6267 | } |
6268 | ||
f6a22291 | 6269 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 6270 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 6271 | |
252b5132 RH |
6272 | used_at = 1; |
6273 | } | |
4d7206a2 RS |
6274 | offset_expr.X_add_number = |
6275 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
6276 | relax_switch (); | |
252b5132 | 6277 | |
67c0d1eb | 6278 | if (gpdelay) |
252b5132 RH |
6279 | { |
6280 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 6281 | the first instruction on the main stream does not. */ |
67c0d1eb | 6282 | macro_build (NULL, "nop", ""); |
252b5132 | 6283 | } |
ed6fb7bd | 6284 | |
67c0d1eb RS |
6285 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6286 | local_reloc_type, mips_gp_register); | |
f5040a92 | 6287 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
6288 | && expr1.X_add_number < 0x8000) |
6289 | { | |
269137b2 | 6290 | load_delay_nop (); |
67c0d1eb RS |
6291 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6292 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 6293 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
6294 | register, the external symbol case ended with a load, |
6295 | so if the symbol turns out to not be external, and | |
6296 | the next instruction uses tempreg, an unnecessary nop | |
6297 | will be inserted. */ | |
252b5132 RH |
6298 | } |
6299 | else | |
6300 | { | |
6301 | if (breg == treg) | |
6302 | { | |
6303 | /* We must add in the base register now, as in the | |
f5040a92 | 6304 | external symbol case. */ |
9c2799c2 | 6305 | gas_assert (tempreg == AT); |
269137b2 | 6306 | load_delay_nop (); |
67c0d1eb | 6307 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6308 | treg, AT, breg); |
252b5132 RH |
6309 | tempreg = treg; |
6310 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 6311 | it in in both cases. */ |
252b5132 RH |
6312 | breg = 0; |
6313 | } | |
6314 | ||
67c0d1eb RS |
6315 | macro_build_lui (&expr1, AT); |
6316 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 6317 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 6318 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6319 | tempreg, tempreg, AT); |
8fc2e39e | 6320 | used_at = 1; |
252b5132 | 6321 | } |
4d7206a2 | 6322 | relax_end (); |
252b5132 | 6323 | } |
0a44bf69 | 6324 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6325 | { |
f5040a92 AO |
6326 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
6327 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 6328 | int add_breg_early = 0; |
f5040a92 AO |
6329 | |
6330 | /* This is the large GOT case. If this is a reference to an | |
6331 | external symbol, and there is no constant, we want | |
6332 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6333 | add $tempreg,$tempreg,$gp | |
6334 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 6335 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
6336 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
6337 | add $tempreg,$tempreg,$gp | |
6338 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
6339 | ||
6340 | If we have a small constant, and this is a reference to | |
6341 | an external symbol, we want | |
6342 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6343 | add $tempreg,$tempreg,$gp | |
6344 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6345 | addi $tempreg,$tempreg,<constant> | |
6346 | ||
6347 | If we have a large constant, and this is a reference to | |
6348 | an external symbol, we want | |
6349 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6350 | addu $tempreg,$tempreg,$gp | |
6351 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6352 | lui $at,<hiconstant> | |
6353 | addi $at,$at,<loconstant> | |
6354 | add $tempreg,$tempreg,$at | |
6355 | ||
6356 | If we have NewABI, and we know it's a local symbol, we want | |
6357 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6358 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
6359 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
6360 | ||
4d7206a2 | 6361 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 6362 | |
4d7206a2 | 6363 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6364 | offset_expr.X_add_number = 0; |
6365 | ||
1abe91b1 MR |
6366 | if (expr1.X_add_number == 0 && breg == 0 |
6367 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
6368 | { |
6369 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
6370 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
6371 | } | |
67c0d1eb RS |
6372 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
6373 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6374 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
6375 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6376 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
6377 | |
6378 | if (expr1.X_add_number == 0) | |
4d7206a2 | 6379 | ; |
f5040a92 AO |
6380 | else if (expr1.X_add_number >= -0x8000 |
6381 | && expr1.X_add_number < 0x8000) | |
6382 | { | |
67c0d1eb | 6383 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6384 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 6385 | } |
ecd13cd3 | 6386 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 6387 | { |
f5040a92 AO |
6388 | /* If we are going to add in a base register, and the |
6389 | target register and the base register are the same, | |
6390 | then we are using AT as a temporary register. Since | |
6391 | we want to load the constant into AT, we add our | |
6392 | current AT (from the global offset table) and the | |
6393 | register into the register now, and pretend we were | |
6394 | not using a base register. */ | |
6395 | if (breg != treg) | |
6396 | dreg = tempreg; | |
6397 | else | |
6398 | { | |
9c2799c2 | 6399 | gas_assert (tempreg == AT); |
67c0d1eb | 6400 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6401 | treg, AT, breg); |
f5040a92 | 6402 | dreg = treg; |
67c0d1eb | 6403 | add_breg_early = 1; |
f5040a92 AO |
6404 | } |
6405 | ||
f6a22291 | 6406 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 6407 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 6408 | |
f5040a92 AO |
6409 | used_at = 1; |
6410 | } | |
6411 | else | |
6412 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
6413 | ||
4d7206a2 | 6414 | relax_switch (); |
f5040a92 | 6415 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6416 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6417 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
6418 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
6419 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
6420 | if (add_breg_early) | |
f5040a92 | 6421 | { |
67c0d1eb | 6422 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6423 | treg, tempreg, breg); |
f5040a92 AO |
6424 | breg = 0; |
6425 | tempreg = treg; | |
6426 | } | |
4d7206a2 | 6427 | relax_end (); |
f5040a92 | 6428 | } |
252b5132 RH |
6429 | else |
6430 | abort (); | |
6431 | ||
6432 | if (breg != 0) | |
aed1a261 | 6433 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
6434 | break; |
6435 | ||
52b6b6b9 JM |
6436 | case M_MSGSND: |
6437 | { | |
6438 | unsigned long temp = (treg << 16) | (0x01); | |
6439 | macro_build (NULL, "c2", "C", temp); | |
6440 | } | |
c7af4273 | 6441 | break; |
52b6b6b9 JM |
6442 | |
6443 | case M_MSGLD: | |
6444 | { | |
6445 | unsigned long temp = (0x02); | |
6446 | macro_build (NULL, "c2", "C", temp); | |
6447 | } | |
c7af4273 | 6448 | break; |
52b6b6b9 JM |
6449 | |
6450 | case M_MSGLD_T: | |
6451 | { | |
6452 | unsigned long temp = (treg << 16) | (0x02); | |
6453 | macro_build (NULL, "c2", "C", temp); | |
6454 | } | |
c7af4273 | 6455 | break; |
52b6b6b9 JM |
6456 | |
6457 | case M_MSGWAIT: | |
6458 | macro_build (NULL, "c2", "C", 3); | |
c7af4273 | 6459 | break; |
52b6b6b9 JM |
6460 | |
6461 | case M_MSGWAIT_T: | |
6462 | { | |
6463 | unsigned long temp = (treg << 16) | 0x03; | |
6464 | macro_build (NULL, "c2", "C", temp); | |
6465 | } | |
c7af4273 | 6466 | break; |
52b6b6b9 | 6467 | |
252b5132 RH |
6468 | case M_J_A: |
6469 | /* The j instruction may not be used in PIC code, since it | |
6470 | requires an absolute address. We convert it to a b | |
6471 | instruction. */ | |
6472 | if (mips_pic == NO_PIC) | |
67c0d1eb | 6473 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 6474 | else |
67c0d1eb | 6475 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6476 | break; |
252b5132 RH |
6477 | |
6478 | /* The jal instructions must be handled as macros because when | |
6479 | generating PIC code they expand to multi-instruction | |
6480 | sequences. Normally they are simple instructions. */ | |
6481 | case M_JAL_1: | |
6482 | dreg = RA; | |
6483 | /* Fall through. */ | |
6484 | case M_JAL_2: | |
3e722fb5 | 6485 | if (mips_pic == NO_PIC) |
67c0d1eb | 6486 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 6487 | else |
252b5132 RH |
6488 | { |
6489 | if (sreg != PIC_CALL_REG) | |
6490 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 6491 | |
67c0d1eb | 6492 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 6493 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 6494 | { |
6478892d TS |
6495 | if (mips_cprestore_offset < 0) |
6496 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6497 | else | |
6498 | { | |
90ecf173 | 6499 | if (!mips_frame_reg_valid) |
7a621144 DJ |
6500 | { |
6501 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6502 | /* Quiet this warning. */ | |
6503 | mips_frame_reg_valid = 1; | |
6504 | } | |
90ecf173 | 6505 | if (!mips_cprestore_valid) |
7a621144 DJ |
6506 | { |
6507 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6508 | /* Quiet this warning. */ | |
6509 | mips_cprestore_valid = 1; | |
6510 | } | |
d3fca0b5 MR |
6511 | if (mips_opts.noreorder) |
6512 | macro_build (NULL, "nop", ""); | |
6478892d | 6513 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6514 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6515 | mips_gp_register, |
256ab948 TS |
6516 | mips_frame_reg, |
6517 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6518 | } |
252b5132 RH |
6519 | } |
6520 | } | |
252b5132 | 6521 | |
8fc2e39e | 6522 | break; |
252b5132 RH |
6523 | |
6524 | case M_JAL_A: | |
6525 | if (mips_pic == NO_PIC) | |
67c0d1eb | 6526 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
6527 | else if (mips_pic == SVR4_PIC) |
6528 | { | |
6529 | /* If this is a reference to an external symbol, and we are | |
6530 | using a small GOT, we want | |
6531 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
6532 | nop | |
f9419b05 | 6533 | jalr $ra,$25 |
252b5132 RH |
6534 | nop |
6535 | lw $gp,cprestore($sp) | |
6536 | The cprestore value is set using the .cprestore | |
6537 | pseudo-op. If we are using a big GOT, we want | |
6538 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
6539 | addu $25,$25,$gp | |
6540 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
6541 | nop | |
f9419b05 | 6542 | jalr $ra,$25 |
252b5132 RH |
6543 | nop |
6544 | lw $gp,cprestore($sp) | |
6545 | If the symbol is not external, we want | |
6546 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6547 | nop | |
6548 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 6549 | jalr $ra,$25 |
252b5132 | 6550 | nop |
438c16b8 | 6551 | lw $gp,cprestore($sp) |
f5040a92 AO |
6552 | |
6553 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
6554 | sequences above, minus nops, unless the symbol is local, | |
6555 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
6556 | GOT_DISP. */ | |
438c16b8 | 6557 | if (HAVE_NEWABI) |
252b5132 | 6558 | { |
90ecf173 | 6559 | if (!mips_big_got) |
f5040a92 | 6560 | { |
4d7206a2 | 6561 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6562 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6563 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 6564 | mips_gp_register); |
4d7206a2 | 6565 | relax_switch (); |
67c0d1eb RS |
6566 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6567 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
6568 | mips_gp_register); |
6569 | relax_end (); | |
f5040a92 AO |
6570 | } |
6571 | else | |
6572 | { | |
4d7206a2 | 6573 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6574 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
6575 | BFD_RELOC_MIPS_CALL_HI16); | |
6576 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6577 | PIC_CALL_REG, mips_gp_register); | |
6578 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6579 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6580 | PIC_CALL_REG); | |
4d7206a2 | 6581 | relax_switch (); |
67c0d1eb RS |
6582 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6583 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
6584 | mips_gp_register); | |
6585 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
6586 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 6587 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 6588 | relax_end (); |
f5040a92 | 6589 | } |
684022ea | 6590 | |
67c0d1eb | 6591 | macro_build_jalr (&offset_expr); |
252b5132 RH |
6592 | } |
6593 | else | |
6594 | { | |
4d7206a2 | 6595 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 6596 | if (!mips_big_got) |
438c16b8 | 6597 | { |
67c0d1eb RS |
6598 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6599 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 6600 | mips_gp_register); |
269137b2 | 6601 | load_delay_nop (); |
4d7206a2 | 6602 | relax_switch (); |
438c16b8 | 6603 | } |
252b5132 | 6604 | else |
252b5132 | 6605 | { |
67c0d1eb RS |
6606 | int gpdelay; |
6607 | ||
6608 | gpdelay = reg_needs_delay (mips_gp_register); | |
6609 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
6610 | BFD_RELOC_MIPS_CALL_HI16); | |
6611 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6612 | PIC_CALL_REG, mips_gp_register); | |
6613 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6614 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6615 | PIC_CALL_REG); | |
269137b2 | 6616 | load_delay_nop (); |
4d7206a2 | 6617 | relax_switch (); |
67c0d1eb RS |
6618 | if (gpdelay) |
6619 | macro_build (NULL, "nop", ""); | |
252b5132 | 6620 | } |
67c0d1eb RS |
6621 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6622 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 6623 | mips_gp_register); |
269137b2 | 6624 | load_delay_nop (); |
67c0d1eb RS |
6625 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6626 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 6627 | relax_end (); |
67c0d1eb | 6628 | macro_build_jalr (&offset_expr); |
438c16b8 | 6629 | |
6478892d TS |
6630 | if (mips_cprestore_offset < 0) |
6631 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6632 | else | |
6633 | { | |
90ecf173 | 6634 | if (!mips_frame_reg_valid) |
7a621144 DJ |
6635 | { |
6636 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6637 | /* Quiet this warning. */ | |
6638 | mips_frame_reg_valid = 1; | |
6639 | } | |
90ecf173 | 6640 | if (!mips_cprestore_valid) |
7a621144 DJ |
6641 | { |
6642 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6643 | /* Quiet this warning. */ | |
6644 | mips_cprestore_valid = 1; | |
6645 | } | |
6478892d | 6646 | if (mips_opts.noreorder) |
67c0d1eb | 6647 | macro_build (NULL, "nop", ""); |
6478892d | 6648 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6649 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6650 | mips_gp_register, |
256ab948 TS |
6651 | mips_frame_reg, |
6652 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6653 | } |
252b5132 RH |
6654 | } |
6655 | } | |
0a44bf69 RS |
6656 | else if (mips_pic == VXWORKS_PIC) |
6657 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
6658 | else |
6659 | abort (); | |
6660 | ||
8fc2e39e | 6661 | break; |
252b5132 RH |
6662 | |
6663 | case M_LB_AB: | |
6664 | s = "lb"; | |
6665 | goto ld; | |
6666 | case M_LBU_AB: | |
6667 | s = "lbu"; | |
6668 | goto ld; | |
6669 | case M_LH_AB: | |
6670 | s = "lh"; | |
6671 | goto ld; | |
6672 | case M_LHU_AB: | |
6673 | s = "lhu"; | |
6674 | goto ld; | |
6675 | case M_LW_AB: | |
6676 | s = "lw"; | |
6677 | goto ld; | |
6678 | case M_LWC0_AB: | |
6679 | s = "lwc0"; | |
bdaaa2e1 | 6680 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6681 | coproc = 1; |
6682 | goto ld; | |
6683 | case M_LWC1_AB: | |
6684 | s = "lwc1"; | |
bdaaa2e1 | 6685 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6686 | coproc = 1; |
6687 | goto ld; | |
6688 | case M_LWC2_AB: | |
6689 | s = "lwc2"; | |
bdaaa2e1 | 6690 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6691 | coproc = 1; |
6692 | goto ld; | |
6693 | case M_LWC3_AB: | |
6694 | s = "lwc3"; | |
bdaaa2e1 | 6695 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6696 | coproc = 1; |
6697 | goto ld; | |
6698 | case M_LWL_AB: | |
6699 | s = "lwl"; | |
6700 | lr = 1; | |
6701 | goto ld; | |
6702 | case M_LWR_AB: | |
6703 | s = "lwr"; | |
6704 | lr = 1; | |
6705 | goto ld; | |
6706 | case M_LDC1_AB: | |
252b5132 | 6707 | s = "ldc1"; |
bdaaa2e1 | 6708 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6709 | coproc = 1; |
6710 | goto ld; | |
6711 | case M_LDC2_AB: | |
6712 | s = "ldc2"; | |
bdaaa2e1 | 6713 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6714 | coproc = 1; |
6715 | goto ld; | |
6716 | case M_LDC3_AB: | |
6717 | s = "ldc3"; | |
bdaaa2e1 | 6718 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6719 | coproc = 1; |
6720 | goto ld; | |
6721 | case M_LDL_AB: | |
6722 | s = "ldl"; | |
6723 | lr = 1; | |
6724 | goto ld; | |
6725 | case M_LDR_AB: | |
6726 | s = "ldr"; | |
6727 | lr = 1; | |
6728 | goto ld; | |
6729 | case M_LL_AB: | |
6730 | s = "ll"; | |
6731 | goto ld; | |
6732 | case M_LLD_AB: | |
6733 | s = "lld"; | |
6734 | goto ld; | |
6735 | case M_LWU_AB: | |
6736 | s = "lwu"; | |
6737 | ld: | |
8fc2e39e | 6738 | if (breg == treg || coproc || lr) |
252b5132 RH |
6739 | { |
6740 | tempreg = AT; | |
6741 | used_at = 1; | |
6742 | } | |
6743 | else | |
6744 | { | |
6745 | tempreg = treg; | |
252b5132 RH |
6746 | } |
6747 | goto ld_st; | |
6748 | case M_SB_AB: | |
6749 | s = "sb"; | |
6750 | goto st; | |
6751 | case M_SH_AB: | |
6752 | s = "sh"; | |
6753 | goto st; | |
6754 | case M_SW_AB: | |
6755 | s = "sw"; | |
6756 | goto st; | |
6757 | case M_SWC0_AB: | |
6758 | s = "swc0"; | |
bdaaa2e1 | 6759 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6760 | coproc = 1; |
6761 | goto st; | |
6762 | case M_SWC1_AB: | |
6763 | s = "swc1"; | |
bdaaa2e1 | 6764 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6765 | coproc = 1; |
6766 | goto st; | |
6767 | case M_SWC2_AB: | |
6768 | s = "swc2"; | |
bdaaa2e1 | 6769 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6770 | coproc = 1; |
6771 | goto st; | |
6772 | case M_SWC3_AB: | |
6773 | s = "swc3"; | |
bdaaa2e1 | 6774 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6775 | coproc = 1; |
6776 | goto st; | |
6777 | case M_SWL_AB: | |
6778 | s = "swl"; | |
6779 | goto st; | |
6780 | case M_SWR_AB: | |
6781 | s = "swr"; | |
6782 | goto st; | |
6783 | case M_SC_AB: | |
6784 | s = "sc"; | |
6785 | goto st; | |
6786 | case M_SCD_AB: | |
6787 | s = "scd"; | |
6788 | goto st; | |
d43b4baf TS |
6789 | case M_CACHE_AB: |
6790 | s = "cache"; | |
6791 | goto st; | |
3eebd5eb MR |
6792 | case M_PREF_AB: |
6793 | s = "pref"; | |
6794 | goto st; | |
252b5132 | 6795 | case M_SDC1_AB: |
252b5132 RH |
6796 | s = "sdc1"; |
6797 | coproc = 1; | |
bdaaa2e1 | 6798 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6799 | goto st; |
6800 | case M_SDC2_AB: | |
6801 | s = "sdc2"; | |
bdaaa2e1 | 6802 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6803 | coproc = 1; |
6804 | goto st; | |
6805 | case M_SDC3_AB: | |
6806 | s = "sdc3"; | |
bdaaa2e1 | 6807 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6808 | coproc = 1; |
6809 | goto st; | |
6810 | case M_SDL_AB: | |
6811 | s = "sdl"; | |
6812 | goto st; | |
6813 | case M_SDR_AB: | |
6814 | s = "sdr"; | |
6815 | st: | |
8fc2e39e TS |
6816 | tempreg = AT; |
6817 | used_at = 1; | |
252b5132 | 6818 | ld_st: |
b19e8a9b AN |
6819 | if (coproc |
6820 | && NO_ISA_COP (mips_opts.arch) | |
6821 | && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0) | |
6822 | { | |
f71d0d44 | 6823 | as_bad (_("Opcode not supported on this processor: %s"), |
b19e8a9b AN |
6824 | mips_cpu_info_from_arch (mips_opts.arch)->name); |
6825 | break; | |
6826 | } | |
6827 | ||
bdaaa2e1 | 6828 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6829 | if (mask == M_LWC1_AB |
6830 | || mask == M_SWC1_AB | |
6831 | || mask == M_LDC1_AB | |
6832 | || mask == M_SDC1_AB | |
6833 | || mask == M_L_DAB | |
6834 | || mask == M_S_DAB) | |
6835 | fmt = "T,o(b)"; | |
3eebd5eb | 6836 | else if (mask == M_CACHE_AB || mask == M_PREF_AB) |
d43b4baf | 6837 | fmt = "k,o(b)"; |
252b5132 RH |
6838 | else if (coproc) |
6839 | fmt = "E,o(b)"; | |
6840 | else | |
6841 | fmt = "t,o(b)"; | |
6842 | ||
6843 | if (offset_expr.X_op != O_constant | |
6844 | && offset_expr.X_op != O_symbol) | |
6845 | { | |
f71d0d44 | 6846 | as_bad (_("Expression too complex")); |
252b5132 RH |
6847 | offset_expr.X_op = O_constant; |
6848 | } | |
6849 | ||
2051e8c4 MR |
6850 | if (HAVE_32BIT_ADDRESSES |
6851 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6852 | { |
6853 | char value [32]; | |
6854 | ||
6855 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6856 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6857 | } |
2051e8c4 | 6858 | |
252b5132 RH |
6859 | /* A constant expression in PIC code can be handled just as it |
6860 | is in non PIC code. */ | |
aed1a261 RS |
6861 | if (offset_expr.X_op == O_constant) |
6862 | { | |
842f8b2a | 6863 | expr1.X_add_number = offset_expr.X_add_number; |
2051e8c4 | 6864 | normalize_address_expr (&expr1); |
842f8b2a MR |
6865 | if (!IS_SEXT_16BIT_NUM (expr1.X_add_number)) |
6866 | { | |
6867 | expr1.X_add_number = ((expr1.X_add_number + 0x8000) | |
6868 | & ~(bfd_vma) 0xffff); | |
6869 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); | |
6870 | if (breg != 0) | |
6871 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6872 | tempreg, tempreg, breg); | |
6873 | breg = tempreg; | |
6874 | } | |
6875 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg); | |
aed1a261 RS |
6876 | } |
6877 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
6878 | { |
6879 | /* If this is a reference to a GP relative symbol, and there | |
6880 | is no base register, we want | |
cdf6fd85 | 6881 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6882 | Otherwise, if there is no base register, we want |
6883 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6884 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6885 | If we have a constant, we need two instructions anyhow, | |
6886 | so we always use the latter form. | |
6887 | ||
6888 | If we have a base register, and this is a reference to a | |
6889 | GP relative symbol, we want | |
6890 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6891 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6892 | Otherwise we want |
6893 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6894 | addu $tempreg,$tempreg,$breg | |
6895 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 6896 | With a constant we always use the latter case. |
76b3015f | 6897 | |
d6bc6245 TS |
6898 | With 64bit address space and no base register and $at usable, |
6899 | we want | |
6900 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6901 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6902 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6903 | dsll32 $tempreg,0 | |
6904 | daddu $tempreg,$at | |
6905 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6906 | If we have a base register, we want | |
6907 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6908 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6909 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6910 | daddu $at,$breg | |
6911 | dsll32 $tempreg,0 | |
6912 | daddu $tempreg,$at | |
6913 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6914 | ||
6915 | Without $at we can't generate the optimal path for superscalar | |
6916 | processors here since this would require two temporary registers. | |
6917 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6918 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6919 | dsll $tempreg,16 | |
6920 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6921 | dsll $tempreg,16 | |
6922 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6923 | If we have a base register, we want | |
6924 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6925 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6926 | dsll $tempreg,16 | |
6927 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6928 | dsll $tempreg,16 | |
6929 | daddu $tempreg,$tempreg,$breg | |
6930 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 6931 | |
6caf9ef4 | 6932 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
6933 | the same sequence as in 32bit address space. */ |
6934 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 6935 | { |
aed1a261 | 6936 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
6937 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6938 | { | |
6939 | relax_start (offset_expr.X_add_symbol); | |
6940 | if (breg == 0) | |
6941 | { | |
6942 | macro_build (&offset_expr, s, fmt, treg, | |
6943 | BFD_RELOC_GPREL16, mips_gp_register); | |
6944 | } | |
6945 | else | |
6946 | { | |
6947 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6948 | tempreg, breg, mips_gp_register); | |
6949 | macro_build (&offset_expr, s, fmt, treg, | |
6950 | BFD_RELOC_GPREL16, tempreg); | |
6951 | } | |
6952 | relax_switch (); | |
6953 | } | |
d6bc6245 | 6954 | |
741fe287 | 6955 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 6956 | { |
67c0d1eb RS |
6957 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6958 | BFD_RELOC_MIPS_HIGHEST); | |
6959 | macro_build (&offset_expr, "lui", "t,u", AT, | |
6960 | BFD_RELOC_HI16_S); | |
6961 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6962 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 6963 | if (breg != 0) |
67c0d1eb RS |
6964 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
6965 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
6966 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
6967 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
6968 | tempreg); | |
d6bc6245 TS |
6969 | used_at = 1; |
6970 | } | |
6971 | else | |
6972 | { | |
67c0d1eb RS |
6973 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6974 | BFD_RELOC_MIPS_HIGHEST); | |
6975 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6976 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6977 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6978 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6979 | tempreg, BFD_RELOC_HI16_S); | |
6980 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6981 | if (breg != 0) |
67c0d1eb | 6982 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6983 | tempreg, tempreg, breg); |
67c0d1eb | 6984 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6985 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 6986 | } |
6caf9ef4 TS |
6987 | |
6988 | if (mips_relax.sequence) | |
6989 | relax_end (); | |
8fc2e39e | 6990 | break; |
d6bc6245 | 6991 | } |
256ab948 | 6992 | |
252b5132 RH |
6993 | if (breg == 0) |
6994 | { | |
67c0d1eb | 6995 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6996 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6997 | { |
4d7206a2 | 6998 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6999 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
7000 | mips_gp_register); | |
4d7206a2 | 7001 | relax_switch (); |
252b5132 | 7002 | } |
67c0d1eb RS |
7003 | macro_build_lui (&offset_expr, tempreg); |
7004 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 7005 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
7006 | if (mips_relax.sequence) |
7007 | relax_end (); | |
252b5132 RH |
7008 | } |
7009 | else | |
7010 | { | |
67c0d1eb | 7011 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 7012 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 7013 | { |
4d7206a2 | 7014 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7015 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7016 | tempreg, breg, mips_gp_register); |
67c0d1eb | 7017 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 7018 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 7019 | relax_switch (); |
252b5132 | 7020 | } |
67c0d1eb RS |
7021 | macro_build_lui (&offset_expr, tempreg); |
7022 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 7023 | tempreg, tempreg, breg); |
67c0d1eb | 7024 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 7025 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
7026 | if (mips_relax.sequence) |
7027 | relax_end (); | |
252b5132 RH |
7028 | } |
7029 | } | |
0a44bf69 | 7030 | else if (!mips_big_got) |
252b5132 | 7031 | { |
ed6fb7bd | 7032 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 7033 | |
252b5132 RH |
7034 | /* If this is a reference to an external symbol, we want |
7035 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7036 | nop | |
7037 | <op> $treg,0($tempreg) | |
7038 | Otherwise we want | |
7039 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7040 | nop | |
7041 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7042 | <op> $treg,0($tempreg) | |
f5040a92 AO |
7043 | |
7044 | For NewABI, we want | |
7045 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
7046 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
7047 | ||
252b5132 RH |
7048 | If there is a base register, we add it to $tempreg before |
7049 | the <op>. If there is a constant, we stick it in the | |
7050 | <op> instruction. We don't handle constants larger than | |
7051 | 16 bits, because we have no way to load the upper 16 bits | |
7052 | (actually, we could handle them for the subset of cases | |
7053 | in which we are not using $at). */ | |
9c2799c2 | 7054 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
7055 | if (HAVE_NEWABI) |
7056 | { | |
67c0d1eb RS |
7057 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7058 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 7059 | if (breg != 0) |
67c0d1eb | 7060 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7061 | tempreg, tempreg, breg); |
67c0d1eb | 7062 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 7063 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
7064 | break; |
7065 | } | |
252b5132 RH |
7066 | expr1.X_add_number = offset_expr.X_add_number; |
7067 | offset_expr.X_add_number = 0; | |
7068 | if (expr1.X_add_number < -0x8000 | |
7069 | || expr1.X_add_number >= 0x8000) | |
7070 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
7071 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7072 | lw_reloc_type, mips_gp_register); | |
269137b2 | 7073 | load_delay_nop (); |
4d7206a2 RS |
7074 | relax_start (offset_expr.X_add_symbol); |
7075 | relax_switch (); | |
67c0d1eb RS |
7076 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
7077 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 7078 | relax_end (); |
252b5132 | 7079 | if (breg != 0) |
67c0d1eb | 7080 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7081 | tempreg, tempreg, breg); |
67c0d1eb | 7082 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 7083 | } |
0a44bf69 | 7084 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 7085 | { |
67c0d1eb | 7086 | int gpdelay; |
252b5132 RH |
7087 | |
7088 | /* If this is a reference to an external symbol, we want | |
7089 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7090 | addu $tempreg,$tempreg,$gp | |
7091 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7092 | <op> $treg,0($tempreg) | |
7093 | Otherwise we want | |
7094 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7095 | nop | |
7096 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7097 | <op> $treg,0($tempreg) | |
7098 | If there is a base register, we add it to $tempreg before | |
7099 | the <op>. If there is a constant, we stick it in the | |
7100 | <op> instruction. We don't handle constants larger than | |
7101 | 16 bits, because we have no way to load the upper 16 bits | |
7102 | (actually, we could handle them for the subset of cases | |
f5040a92 | 7103 | in which we are not using $at). */ |
9c2799c2 | 7104 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
7105 | expr1.X_add_number = offset_expr.X_add_number; |
7106 | offset_expr.X_add_number = 0; | |
7107 | if (expr1.X_add_number < -0x8000 | |
7108 | || expr1.X_add_number >= 0x8000) | |
7109 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7110 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 7111 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7112 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 7113 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
7114 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
7115 | mips_gp_register); | |
7116 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
7117 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 7118 | relax_switch (); |
67c0d1eb RS |
7119 | if (gpdelay) |
7120 | macro_build (NULL, "nop", ""); | |
7121 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
7122 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7123 | load_delay_nop (); |
67c0d1eb RS |
7124 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
7125 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
7126 | relax_end (); |
7127 | ||
252b5132 | 7128 | if (breg != 0) |
67c0d1eb | 7129 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7130 | tempreg, tempreg, breg); |
67c0d1eb | 7131 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 7132 | } |
0a44bf69 | 7133 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 7134 | { |
f5040a92 AO |
7135 | /* If this is a reference to an external symbol, we want |
7136 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7137 | add $tempreg,$tempreg,$gp | |
7138 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7139 | <op> $treg,<ofst>($tempreg) | |
7140 | Otherwise, for local symbols, we want: | |
7141 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
7142 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 7143 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 7144 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7145 | offset_expr.X_add_number = 0; |
7146 | if (expr1.X_add_number < -0x8000 | |
7147 | || expr1.X_add_number >= 0x8000) | |
7148 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 7149 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7150 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 7151 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
7152 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
7153 | mips_gp_register); | |
7154 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
7155 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 7156 | if (breg != 0) |
67c0d1eb | 7157 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7158 | tempreg, tempreg, breg); |
67c0d1eb | 7159 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 7160 | |
4d7206a2 | 7161 | relax_switch (); |
f5040a92 | 7162 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
7163 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7164 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 7165 | if (breg != 0) |
67c0d1eb | 7166 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7167 | tempreg, tempreg, breg); |
67c0d1eb | 7168 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 7169 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 7170 | relax_end (); |
f5040a92 | 7171 | } |
252b5132 RH |
7172 | else |
7173 | abort (); | |
7174 | ||
252b5132 RH |
7175 | break; |
7176 | ||
7177 | case M_LI: | |
7178 | case M_LI_S: | |
67c0d1eb | 7179 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 7180 | break; |
252b5132 RH |
7181 | |
7182 | case M_DLI: | |
67c0d1eb | 7183 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 7184 | break; |
252b5132 RH |
7185 | |
7186 | case M_LI_SS: | |
7187 | if (imm_expr.X_op == O_constant) | |
7188 | { | |
8fc2e39e | 7189 | used_at = 1; |
67c0d1eb RS |
7190 | load_register (AT, &imm_expr, 0); |
7191 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
7192 | break; |
7193 | } | |
7194 | else | |
7195 | { | |
9c2799c2 | 7196 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
7197 | && strcmp (segment_name (S_GET_SEGMENT |
7198 | (offset_expr.X_add_symbol)), | |
7199 | ".lit4") == 0 | |
7200 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 7201 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 7202 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 7203 | break; |
252b5132 RH |
7204 | } |
7205 | ||
7206 | case M_LI_D: | |
ca4e0257 RS |
7207 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
7208 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
7209 | order 32 bits of the value and the low order 32 bits are either | |
7210 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
7211 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
7212 | { | |
ca4e0257 | 7213 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 7214 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
7215 | else |
7216 | { | |
7217 | int hreg, lreg; | |
7218 | ||
7219 | if (target_big_endian) | |
7220 | { | |
7221 | hreg = treg; | |
7222 | lreg = treg + 1; | |
7223 | } | |
7224 | else | |
7225 | { | |
7226 | hreg = treg + 1; | |
7227 | lreg = treg; | |
7228 | } | |
7229 | ||
7230 | if (hreg <= 31) | |
67c0d1eb | 7231 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
7232 | if (lreg <= 31) |
7233 | { | |
7234 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 7235 | move_register (lreg, 0); |
252b5132 RH |
7236 | else |
7237 | { | |
9c2799c2 | 7238 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 7239 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
7240 | } |
7241 | } | |
7242 | } | |
8fc2e39e | 7243 | break; |
252b5132 RH |
7244 | } |
7245 | ||
7246 | /* We know that sym is in the .rdata section. First we get the | |
7247 | upper 16 bits of the address. */ | |
7248 | if (mips_pic == NO_PIC) | |
7249 | { | |
67c0d1eb | 7250 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 7251 | used_at = 1; |
252b5132 | 7252 | } |
0a44bf69 | 7253 | else |
252b5132 | 7254 | { |
67c0d1eb RS |
7255 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
7256 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 7257 | used_at = 1; |
252b5132 | 7258 | } |
bdaaa2e1 | 7259 | |
252b5132 | 7260 | /* Now we load the register(s). */ |
ca4e0257 | 7261 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
7262 | { |
7263 | used_at = 1; | |
7264 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
7265 | } | |
252b5132 RH |
7266 | else |
7267 | { | |
8fc2e39e | 7268 | used_at = 1; |
67c0d1eb | 7269 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 7270 | if (treg != RA) |
252b5132 RH |
7271 | { |
7272 | /* FIXME: How in the world do we deal with the possible | |
7273 | overflow here? */ | |
7274 | offset_expr.X_add_number += 4; | |
67c0d1eb | 7275 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 7276 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
7277 | } |
7278 | } | |
252b5132 RH |
7279 | break; |
7280 | ||
7281 | case M_LI_DD: | |
ca4e0257 RS |
7282 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
7283 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
7284 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
7285 | the value and the low order 32 bits are either zero or in | |
7286 | OFFSET_EXPR. */ | |
252b5132 RH |
7287 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
7288 | { | |
8fc2e39e | 7289 | used_at = 1; |
67c0d1eb | 7290 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
7291 | if (HAVE_64BIT_FPRS) |
7292 | { | |
9c2799c2 | 7293 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 7294 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 7295 | } |
252b5132 RH |
7296 | else |
7297 | { | |
67c0d1eb | 7298 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 7299 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 7300 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
7301 | else |
7302 | { | |
9c2799c2 | 7303 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
7304 | load_register (AT, &offset_expr, 0); |
7305 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
7306 | } |
7307 | } | |
7308 | break; | |
7309 | } | |
7310 | ||
9c2799c2 | 7311 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 7312 | && offset_expr.X_add_number == 0); |
252b5132 RH |
7313 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
7314 | if (strcmp (s, ".lit8") == 0) | |
7315 | { | |
e7af610e | 7316 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 7317 | { |
67c0d1eb | 7318 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 7319 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 7320 | break; |
252b5132 | 7321 | } |
c9914766 | 7322 | breg = mips_gp_register; |
252b5132 RH |
7323 | r = BFD_RELOC_MIPS_LITERAL; |
7324 | goto dob; | |
7325 | } | |
7326 | else | |
7327 | { | |
9c2799c2 | 7328 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 7329 | used_at = 1; |
0a44bf69 | 7330 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
7331 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
7332 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
7333 | else |
7334 | { | |
7335 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 7336 | macro_build_lui (&offset_expr, AT); |
252b5132 | 7337 | } |
bdaaa2e1 | 7338 | |
e7af610e | 7339 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 7340 | { |
67c0d1eb RS |
7341 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
7342 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
7343 | break; |
7344 | } | |
7345 | breg = AT; | |
7346 | r = BFD_RELOC_LO16; | |
7347 | goto dob; | |
7348 | } | |
7349 | ||
7350 | case M_L_DOB: | |
252b5132 RH |
7351 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7352 | to adjust when loading from memory. */ | |
7353 | r = BFD_RELOC_LO16; | |
7354 | dob: | |
9c2799c2 | 7355 | gas_assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 7356 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 7357 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
7358 | /* FIXME: A possible overflow which I don't know how to deal |
7359 | with. */ | |
7360 | offset_expr.X_add_number += 4; | |
67c0d1eb | 7361 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 7362 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
7363 | break; |
7364 | ||
c4a68bea MR |
7365 | case M_S_DOB: |
7366 | gas_assert (mips_opts.isa == ISA_MIPS1); | |
7367 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
7368 | to adjust when storing to memory. */ | |
7369 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
7370 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
7371 | offset_expr.X_add_number += 4; | |
7372 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
7373 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
7374 | break; | |
7375 | ||
252b5132 RH |
7376 | case M_L_DAB: |
7377 | /* | |
7378 | * The MIPS assembler seems to check for X_add_number not | |
7379 | * being double aligned and generating: | |
7380 | * lui at,%hi(foo+1) | |
7381 | * addu at,at,v1 | |
7382 | * addiu at,at,%lo(foo+1) | |
7383 | * lwc1 f2,0(at) | |
7384 | * lwc1 f3,4(at) | |
7385 | * But, the resulting address is the same after relocation so why | |
7386 | * generate the extra instruction? | |
7387 | */ | |
bdaaa2e1 | 7388 | /* Itbl support may require additional care here. */ |
252b5132 | 7389 | coproc = 1; |
e7af610e | 7390 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
7391 | { |
7392 | s = "ldc1"; | |
7393 | goto ld; | |
7394 | } | |
7395 | ||
7396 | s = "lwc1"; | |
7397 | fmt = "T,o(b)"; | |
7398 | goto ldd_std; | |
7399 | ||
7400 | case M_S_DAB: | |
e7af610e | 7401 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
7402 | { |
7403 | s = "sdc1"; | |
7404 | goto st; | |
7405 | } | |
7406 | ||
7407 | s = "swc1"; | |
7408 | fmt = "T,o(b)"; | |
bdaaa2e1 | 7409 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7410 | coproc = 1; |
7411 | goto ldd_std; | |
7412 | ||
7413 | case M_LD_AB: | |
ca4e0257 | 7414 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
7415 | { |
7416 | s = "ld"; | |
7417 | goto ld; | |
7418 | } | |
7419 | ||
7420 | s = "lw"; | |
7421 | fmt = "t,o(b)"; | |
7422 | goto ldd_std; | |
7423 | ||
7424 | case M_SD_AB: | |
ca4e0257 | 7425 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
7426 | { |
7427 | s = "sd"; | |
7428 | goto st; | |
7429 | } | |
7430 | ||
7431 | s = "sw"; | |
7432 | fmt = "t,o(b)"; | |
7433 | ||
7434 | ldd_std: | |
7435 | if (offset_expr.X_op != O_symbol | |
7436 | && offset_expr.X_op != O_constant) | |
7437 | { | |
f71d0d44 | 7438 | as_bad (_("Expression too complex")); |
252b5132 RH |
7439 | offset_expr.X_op = O_constant; |
7440 | } | |
7441 | ||
2051e8c4 MR |
7442 | if (HAVE_32BIT_ADDRESSES |
7443 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
7444 | { |
7445 | char value [32]; | |
7446 | ||
7447 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 7448 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 7449 | } |
2051e8c4 | 7450 | |
252b5132 RH |
7451 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7452 | to adjust when loading from memory. We set coproc if we must | |
7453 | load $fn+1 first. */ | |
bdaaa2e1 | 7454 | /* Itbl support may require additional care here. */ |
90ecf173 | 7455 | if (!target_big_endian) |
252b5132 RH |
7456 | coproc = 0; |
7457 | ||
90ecf173 | 7458 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
7459 | { |
7460 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
7461 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
7462 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
7463 | If we have a base register, we use this |
7464 | addu $at,$breg,$gp | |
cdf6fd85 TS |
7465 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
7466 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
7467 | If this is not a GP relative symbol, we want |
7468 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7469 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7470 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7471 | If there is a base register, we add it to $at after the | |
7472 | lui instruction. If there is a constant, we always use | |
7473 | the last case. */ | |
39a59cf8 MR |
7474 | if (offset_expr.X_op == O_symbol |
7475 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7476 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 7477 | { |
4d7206a2 | 7478 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
7479 | if (breg == 0) |
7480 | { | |
c9914766 | 7481 | tempreg = mips_gp_register; |
252b5132 RH |
7482 | } |
7483 | else | |
7484 | { | |
67c0d1eb | 7485 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7486 | AT, breg, mips_gp_register); |
252b5132 | 7487 | tempreg = AT; |
252b5132 RH |
7488 | used_at = 1; |
7489 | } | |
7490 | ||
beae10d5 | 7491 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7492 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7493 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
7494 | offset_expr.X_add_number += 4; |
7495 | ||
7496 | /* Set mips_optimize to 2 to avoid inserting an | |
7497 | undesired nop. */ | |
7498 | hold_mips_optimize = mips_optimize; | |
7499 | mips_optimize = 2; | |
beae10d5 | 7500 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7501 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7502 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
7503 | mips_optimize = hold_mips_optimize; |
7504 | ||
4d7206a2 | 7505 | relax_switch (); |
252b5132 | 7506 | |
0970e49e | 7507 | offset_expr.X_add_number -= 4; |
252b5132 | 7508 | } |
8fc2e39e | 7509 | used_at = 1; |
67c0d1eb | 7510 | macro_build_lui (&offset_expr, AT); |
252b5132 | 7511 | if (breg != 0) |
67c0d1eb | 7512 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7513 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7514 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7515 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7516 | /* FIXME: How do we handle overflow here? */ |
7517 | offset_expr.X_add_number += 4; | |
beae10d5 | 7518 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7519 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7520 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
7521 | if (mips_relax.sequence) |
7522 | relax_end (); | |
bdaaa2e1 | 7523 | } |
0a44bf69 | 7524 | else if (!mips_big_got) |
252b5132 | 7525 | { |
252b5132 RH |
7526 | /* If this is a reference to an external symbol, we want |
7527 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7528 | nop | |
7529 | <op> $treg,0($at) | |
7530 | <op> $treg+1,4($at) | |
7531 | Otherwise we want | |
7532 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7533 | nop | |
7534 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7535 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7536 | If there is a base register we add it to $at before the | |
7537 | lwc1 instructions. If there is a constant we include it | |
7538 | in the lwc1 instructions. */ | |
7539 | used_at = 1; | |
7540 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
7541 | if (expr1.X_add_number < -0x8000 |
7542 | || expr1.X_add_number >= 0x8000 - 4) | |
7543 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7544 | load_got_offset (AT, &offset_expr); |
269137b2 | 7545 | load_delay_nop (); |
252b5132 | 7546 | if (breg != 0) |
67c0d1eb | 7547 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
7548 | |
7549 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7550 | nop. */ | |
7551 | hold_mips_optimize = mips_optimize; | |
7552 | mips_optimize = 2; | |
4d7206a2 | 7553 | |
beae10d5 | 7554 | /* Itbl support may require additional care here. */ |
4d7206a2 | 7555 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7556 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
7557 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7558 | expr1.X_add_number += 4; |
67c0d1eb RS |
7559 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
7560 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7561 | relax_switch (); |
67c0d1eb RS |
7562 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7563 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7564 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7565 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7566 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7567 | relax_end (); |
252b5132 | 7568 | |
4d7206a2 | 7569 | mips_optimize = hold_mips_optimize; |
252b5132 | 7570 | } |
0a44bf69 | 7571 | else if (mips_big_got) |
252b5132 | 7572 | { |
67c0d1eb | 7573 | int gpdelay; |
252b5132 RH |
7574 | |
7575 | /* If this is a reference to an external symbol, we want | |
7576 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7577 | addu $at,$at,$gp | |
7578 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
7579 | nop | |
7580 | <op> $treg,0($at) | |
7581 | <op> $treg+1,4($at) | |
7582 | Otherwise we want | |
7583 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7584 | nop | |
7585 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7586 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7587 | If there is a base register we add it to $at before the | |
7588 | lwc1 instructions. If there is a constant we include it | |
7589 | in the lwc1 instructions. */ | |
7590 | used_at = 1; | |
7591 | expr1.X_add_number = offset_expr.X_add_number; | |
7592 | offset_expr.X_add_number = 0; | |
7593 | if (expr1.X_add_number < -0x8000 | |
7594 | || expr1.X_add_number >= 0x8000 - 4) | |
7595 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7596 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 7597 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7598 | macro_build (&offset_expr, "lui", "t,u", |
7599 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
7600 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 7601 | AT, AT, mips_gp_register); |
67c0d1eb | 7602 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7603 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 7604 | load_delay_nop (); |
252b5132 | 7605 | if (breg != 0) |
67c0d1eb | 7606 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7607 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7608 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7609 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7610 | expr1.X_add_number += 4; |
7611 | ||
7612 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7613 | nop. */ | |
7614 | hold_mips_optimize = mips_optimize; | |
7615 | mips_optimize = 2; | |
beae10d5 | 7616 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7617 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7618 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7619 | mips_optimize = hold_mips_optimize; |
7620 | expr1.X_add_number -= 4; | |
7621 | ||
4d7206a2 RS |
7622 | relax_switch (); |
7623 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
7624 | if (gpdelay) |
7625 | macro_build (NULL, "nop", ""); | |
7626 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
7627 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7628 | load_delay_nop (); |
252b5132 | 7629 | if (breg != 0) |
67c0d1eb | 7630 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7631 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7632 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7633 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7634 | offset_expr.X_add_number += 4; |
252b5132 RH |
7635 | |
7636 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7637 | nop. */ | |
7638 | hold_mips_optimize = mips_optimize; | |
7639 | mips_optimize = 2; | |
beae10d5 | 7640 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7641 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7642 | BFD_RELOC_LO16, AT); | |
252b5132 | 7643 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 7644 | relax_end (); |
252b5132 | 7645 | } |
252b5132 RH |
7646 | else |
7647 | abort (); | |
7648 | ||
252b5132 RH |
7649 | break; |
7650 | ||
7651 | case M_LD_OB: | |
704897fb | 7652 | s = HAVE_64BIT_GPRS ? "ld" : "lw"; |
252b5132 RH |
7653 | goto sd_ob; |
7654 | case M_SD_OB: | |
704897fb | 7655 | s = HAVE_64BIT_GPRS ? "sd" : "sw"; |
252b5132 | 7656 | sd_ob: |
4614d845 MR |
7657 | macro_build (&offset_expr, s, "t,o(b)", treg, |
7658 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
7659 | breg); | |
704897fb MR |
7660 | if (!HAVE_64BIT_GPRS) |
7661 | { | |
7662 | offset_expr.X_add_number += 4; | |
7663 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, | |
4614d845 MR |
7664 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], |
7665 | breg); | |
704897fb | 7666 | } |
8fc2e39e | 7667 | break; |
252b5132 RH |
7668 | |
7669 | /* New code added to support COPZ instructions. | |
7670 | This code builds table entries out of the macros in mip_opcodes. | |
7671 | R4000 uses interlocks to handle coproc delays. | |
7672 | Other chips (like the R3000) require nops to be inserted for delays. | |
7673 | ||
f72c8c98 | 7674 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
7675 | In order to fill delay slots for non-interlocked chips, |
7676 | we must have a way to specify delays based on the coprocessor. | |
7677 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
7678 | What are the side-effects of the cop instruction? | |
7679 | What cache support might we have and what are its effects? | |
7680 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 7681 | What registers are read/set/modified? |
252b5132 RH |
7682 | |
7683 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 7684 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
7685 | |
7686 | case M_COP0: | |
7687 | s = "c0"; | |
7688 | goto copz; | |
7689 | case M_COP1: | |
7690 | s = "c1"; | |
7691 | goto copz; | |
7692 | case M_COP2: | |
7693 | s = "c2"; | |
7694 | goto copz; | |
7695 | case M_COP3: | |
7696 | s = "c3"; | |
7697 | copz: | |
b19e8a9b AN |
7698 | if (NO_ISA_COP (mips_opts.arch) |
7699 | && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0) | |
7700 | { | |
7701 | as_bad (_("opcode not supported on this processor: %s"), | |
7702 | mips_cpu_info_from_arch (mips_opts.arch)->name); | |
7703 | break; | |
7704 | } | |
7705 | ||
252b5132 RH |
7706 | /* For now we just do C (same as Cz). The parameter will be |
7707 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 7708 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 7709 | break; |
252b5132 | 7710 | |
ea1fb5dc | 7711 | case M_MOVE: |
67c0d1eb | 7712 | move_register (dreg, sreg); |
8fc2e39e | 7713 | break; |
ea1fb5dc | 7714 | |
252b5132 RH |
7715 | case M_DMUL: |
7716 | dbl = 1; | |
7717 | case M_MUL: | |
67c0d1eb RS |
7718 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
7719 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 7720 | break; |
252b5132 RH |
7721 | |
7722 | case M_DMUL_I: | |
7723 | dbl = 1; | |
7724 | case M_MUL_I: | |
7725 | /* The MIPS assembler some times generates shifts and adds. I'm | |
7726 | not trying to be that fancy. GCC should do this for us | |
7727 | anyway. */ | |
8fc2e39e | 7728 | used_at = 1; |
67c0d1eb RS |
7729 | load_register (AT, &imm_expr, dbl); |
7730 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
7731 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
7732 | break; |
7733 | ||
7734 | case M_DMULO_I: | |
7735 | dbl = 1; | |
7736 | case M_MULO_I: | |
7737 | imm = 1; | |
7738 | goto do_mulo; | |
7739 | ||
7740 | case M_DMULO: | |
7741 | dbl = 1; | |
7742 | case M_MULO: | |
7743 | do_mulo: | |
7d10b47d | 7744 | start_noreorder (); |
8fc2e39e | 7745 | used_at = 1; |
252b5132 | 7746 | if (imm) |
67c0d1eb RS |
7747 | load_register (AT, &imm_expr, dbl); |
7748 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
7749 | macro_build (NULL, "mflo", "d", dreg); | |
7750 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
7751 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 7752 | if (mips_trap) |
67c0d1eb | 7753 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
7754 | else |
7755 | { | |
7756 | expr1.X_add_number = 8; | |
67c0d1eb | 7757 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
a605d2b3 | 7758 | macro_build (NULL, "nop", ""); |
67c0d1eb | 7759 | macro_build (NULL, "break", "c", 6); |
252b5132 | 7760 | } |
7d10b47d | 7761 | end_noreorder (); |
67c0d1eb | 7762 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
7763 | break; |
7764 | ||
7765 | case M_DMULOU_I: | |
7766 | dbl = 1; | |
7767 | case M_MULOU_I: | |
7768 | imm = 1; | |
7769 | goto do_mulou; | |
7770 | ||
7771 | case M_DMULOU: | |
7772 | dbl = 1; | |
7773 | case M_MULOU: | |
7774 | do_mulou: | |
7d10b47d | 7775 | start_noreorder (); |
8fc2e39e | 7776 | used_at = 1; |
252b5132 | 7777 | if (imm) |
67c0d1eb RS |
7778 | load_register (AT, &imm_expr, dbl); |
7779 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 7780 | sreg, imm ? AT : treg); |
67c0d1eb RS |
7781 | macro_build (NULL, "mfhi", "d", AT); |
7782 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 7783 | if (mips_trap) |
c80c840e | 7784 | macro_build (NULL, "tne", "s,t,q", AT, ZERO, 6); |
252b5132 RH |
7785 | else |
7786 | { | |
7787 | expr1.X_add_number = 8; | |
c80c840e | 7788 | macro_build (&expr1, "beq", "s,t,p", AT, ZERO); |
a605d2b3 | 7789 | macro_build (NULL, "nop", ""); |
67c0d1eb | 7790 | macro_build (NULL, "break", "c", 6); |
252b5132 | 7791 | } |
7d10b47d | 7792 | end_noreorder (); |
252b5132 RH |
7793 | break; |
7794 | ||
771c7ce4 | 7795 | case M_DROL: |
fef14a42 | 7796 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7797 | { |
7798 | if (dreg == sreg) | |
7799 | { | |
7800 | tempreg = AT; | |
7801 | used_at = 1; | |
7802 | } | |
7803 | else | |
7804 | { | |
7805 | tempreg = dreg; | |
82dd0097 | 7806 | } |
67c0d1eb RS |
7807 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
7808 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7809 | break; |
82dd0097 | 7810 | } |
8fc2e39e | 7811 | used_at = 1; |
c80c840e | 7812 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7813 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
7814 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
7815 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7816 | break; |
7817 | ||
252b5132 | 7818 | case M_ROL: |
fef14a42 | 7819 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
7820 | { |
7821 | if (dreg == sreg) | |
7822 | { | |
7823 | tempreg = AT; | |
7824 | used_at = 1; | |
7825 | } | |
7826 | else | |
7827 | { | |
7828 | tempreg = dreg; | |
82dd0097 | 7829 | } |
67c0d1eb RS |
7830 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
7831 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7832 | break; |
82dd0097 | 7833 | } |
8fc2e39e | 7834 | used_at = 1; |
c80c840e | 7835 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7836 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
7837 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
7838 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7839 | break; |
7840 | ||
771c7ce4 TS |
7841 | case M_DROL_I: |
7842 | { | |
7843 | unsigned int rot; | |
91d6fa6a NC |
7844 | char *l; |
7845 | char *rr; | |
771c7ce4 TS |
7846 | |
7847 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7848 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7849 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7850 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
7851 | { |
7852 | rot = (64 - rot) & 0x3f; | |
7853 | if (rot >= 32) | |
67c0d1eb | 7854 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 7855 | else |
67c0d1eb | 7856 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7857 | break; |
60b63b72 | 7858 | } |
483fc7cd | 7859 | if (rot == 0) |
483fc7cd | 7860 | { |
67c0d1eb | 7861 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7862 | break; |
483fc7cd | 7863 | } |
82dd0097 | 7864 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 7865 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 7866 | rot &= 0x1f; |
8fc2e39e | 7867 | used_at = 1; |
67c0d1eb | 7868 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
91d6fa6a | 7869 | macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); |
67c0d1eb | 7870 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
7871 | } |
7872 | break; | |
7873 | ||
252b5132 | 7874 | case M_ROL_I: |
771c7ce4 TS |
7875 | { |
7876 | unsigned int rot; | |
7877 | ||
7878 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7879 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7880 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7881 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 7882 | { |
67c0d1eb | 7883 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 7884 | break; |
60b63b72 | 7885 | } |
483fc7cd | 7886 | if (rot == 0) |
483fc7cd | 7887 | { |
67c0d1eb | 7888 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7889 | break; |
483fc7cd | 7890 | } |
8fc2e39e | 7891 | used_at = 1; |
67c0d1eb RS |
7892 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
7893 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7894 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7895 | } |
7896 | break; | |
7897 | ||
7898 | case M_DROR: | |
fef14a42 | 7899 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7900 | { |
67c0d1eb | 7901 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7902 | break; |
82dd0097 | 7903 | } |
8fc2e39e | 7904 | used_at = 1; |
c80c840e | 7905 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7906 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
7907 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7908 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7909 | break; |
7910 | ||
7911 | case M_ROR: | |
fef14a42 | 7912 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7913 | { |
67c0d1eb | 7914 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7915 | break; |
82dd0097 | 7916 | } |
8fc2e39e | 7917 | used_at = 1; |
c80c840e | 7918 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7919 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
7920 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7921 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7922 | break; |
7923 | ||
771c7ce4 TS |
7924 | case M_DROR_I: |
7925 | { | |
7926 | unsigned int rot; | |
91d6fa6a NC |
7927 | char *l; |
7928 | char *rr; | |
771c7ce4 TS |
7929 | |
7930 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7931 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7932 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7933 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7934 | { |
7935 | if (rot >= 32) | |
67c0d1eb | 7936 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7937 | else |
67c0d1eb | 7938 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7939 | break; |
82dd0097 | 7940 | } |
483fc7cd | 7941 | if (rot == 0) |
483fc7cd | 7942 | { |
67c0d1eb | 7943 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7944 | break; |
483fc7cd | 7945 | } |
91d6fa6a | 7946 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
7947 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
7948 | rot &= 0x1f; | |
8fc2e39e | 7949 | used_at = 1; |
91d6fa6a | 7950 | macro_build (NULL, rr, "d,w,<", AT, sreg, rot); |
67c0d1eb RS |
7951 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); |
7952 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7953 | } |
7954 | break; | |
7955 | ||
252b5132 | 7956 | case M_ROR_I: |
771c7ce4 TS |
7957 | { |
7958 | unsigned int rot; | |
7959 | ||
7960 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7961 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7962 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7963 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7964 | { |
67c0d1eb | 7965 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7966 | break; |
82dd0097 | 7967 | } |
483fc7cd | 7968 | if (rot == 0) |
483fc7cd | 7969 | { |
67c0d1eb | 7970 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7971 | break; |
483fc7cd | 7972 | } |
8fc2e39e | 7973 | used_at = 1; |
67c0d1eb RS |
7974 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7975 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7976 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7977 | } |
252b5132 RH |
7978 | break; |
7979 | ||
252b5132 RH |
7980 | case M_SEQ: |
7981 | if (sreg == 0) | |
67c0d1eb | 7982 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7983 | else if (treg == 0) |
67c0d1eb | 7984 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7985 | else |
7986 | { | |
67c0d1eb RS |
7987 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7988 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7989 | } |
8fc2e39e | 7990 | break; |
252b5132 RH |
7991 | |
7992 | case M_SEQ_I: | |
7993 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7994 | { | |
67c0d1eb | 7995 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7996 | break; |
252b5132 RH |
7997 | } |
7998 | if (sreg == 0) | |
7999 | { | |
8000 | as_warn (_("Instruction %s: result is always false"), | |
8001 | ip->insn_mo->name); | |
67c0d1eb | 8002 | move_register (dreg, 0); |
8fc2e39e | 8003 | break; |
252b5132 | 8004 | } |
dd3cbb7e NC |
8005 | if (CPU_HAS_SEQ (mips_opts.arch) |
8006 | && -512 <= imm_expr.X_add_number | |
8007 | && imm_expr.X_add_number < 512) | |
8008 | { | |
8009 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 8010 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
8011 | break; |
8012 | } | |
252b5132 RH |
8013 | if (imm_expr.X_op == O_constant |
8014 | && imm_expr.X_add_number >= 0 | |
8015 | && imm_expr.X_add_number < 0x10000) | |
8016 | { | |
67c0d1eb | 8017 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
8018 | } |
8019 | else if (imm_expr.X_op == O_constant | |
8020 | && imm_expr.X_add_number > -0x8000 | |
8021 | && imm_expr.X_add_number < 0) | |
8022 | { | |
8023 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8024 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 8025 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 8026 | } |
dd3cbb7e NC |
8027 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
8028 | { | |
8029 | used_at = 1; | |
8030 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
8031 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
8032 | break; | |
8033 | } | |
252b5132 RH |
8034 | else |
8035 | { | |
67c0d1eb RS |
8036 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
8037 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
8038 | used_at = 1; |
8039 | } | |
67c0d1eb | 8040 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 8041 | break; |
252b5132 RH |
8042 | |
8043 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
8044 | s = "slt"; | |
8045 | goto sge; | |
8046 | case M_SGEU: | |
8047 | s = "sltu"; | |
8048 | sge: | |
67c0d1eb RS |
8049 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
8050 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 8051 | break; |
252b5132 RH |
8052 | |
8053 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
8054 | case M_SGEU_I: | |
8055 | if (imm_expr.X_op == O_constant | |
8056 | && imm_expr.X_add_number >= -0x8000 | |
8057 | && imm_expr.X_add_number < 0x8000) | |
8058 | { | |
67c0d1eb RS |
8059 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
8060 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
8061 | } |
8062 | else | |
8063 | { | |
67c0d1eb RS |
8064 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
8065 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
8066 | dreg, sreg, AT); | |
252b5132 RH |
8067 | used_at = 1; |
8068 | } | |
67c0d1eb | 8069 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 8070 | break; |
252b5132 RH |
8071 | |
8072 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
8073 | s = "slt"; | |
8074 | goto sgt; | |
8075 | case M_SGTU: | |
8076 | s = "sltu"; | |
8077 | sgt: | |
67c0d1eb | 8078 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 8079 | break; |
252b5132 RH |
8080 | |
8081 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
8082 | s = "slt"; | |
8083 | goto sgti; | |
8084 | case M_SGTU_I: | |
8085 | s = "sltu"; | |
8086 | sgti: | |
8fc2e39e | 8087 | used_at = 1; |
67c0d1eb RS |
8088 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
8089 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
8090 | break; |
8091 | ||
2396cfb9 | 8092 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
8093 | s = "slt"; |
8094 | goto sle; | |
8095 | case M_SLEU: | |
8096 | s = "sltu"; | |
8097 | sle: | |
67c0d1eb RS |
8098 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8099 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 8100 | break; |
252b5132 | 8101 | |
2396cfb9 | 8102 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
8103 | s = "slt"; |
8104 | goto slei; | |
8105 | case M_SLEU_I: | |
8106 | s = "sltu"; | |
8107 | slei: | |
8fc2e39e | 8108 | used_at = 1; |
67c0d1eb RS |
8109 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
8110 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
8111 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
8112 | break; |
8113 | ||
8114 | case M_SLT_I: | |
8115 | if (imm_expr.X_op == O_constant | |
8116 | && imm_expr.X_add_number >= -0x8000 | |
8117 | && imm_expr.X_add_number < 0x8000) | |
8118 | { | |
67c0d1eb | 8119 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 8120 | break; |
252b5132 | 8121 | } |
8fc2e39e | 8122 | used_at = 1; |
67c0d1eb RS |
8123 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
8124 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
8125 | break; |
8126 | ||
8127 | case M_SLTU_I: | |
8128 | if (imm_expr.X_op == O_constant | |
8129 | && imm_expr.X_add_number >= -0x8000 | |
8130 | && imm_expr.X_add_number < 0x8000) | |
8131 | { | |
67c0d1eb | 8132 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 8133 | BFD_RELOC_LO16); |
8fc2e39e | 8134 | break; |
252b5132 | 8135 | } |
8fc2e39e | 8136 | used_at = 1; |
67c0d1eb RS |
8137 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
8138 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
8139 | break; |
8140 | ||
8141 | case M_SNE: | |
8142 | if (sreg == 0) | |
67c0d1eb | 8143 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 8144 | else if (treg == 0) |
67c0d1eb | 8145 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
8146 | else |
8147 | { | |
67c0d1eb RS |
8148 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
8149 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 8150 | } |
8fc2e39e | 8151 | break; |
252b5132 RH |
8152 | |
8153 | case M_SNE_I: | |
8154 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
8155 | { | |
67c0d1eb | 8156 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 8157 | break; |
252b5132 RH |
8158 | } |
8159 | if (sreg == 0) | |
8160 | { | |
8161 | as_warn (_("Instruction %s: result is always true"), | |
8162 | ip->insn_mo->name); | |
67c0d1eb RS |
8163 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
8164 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 8165 | break; |
252b5132 | 8166 | } |
dd3cbb7e NC |
8167 | if (CPU_HAS_SEQ (mips_opts.arch) |
8168 | && -512 <= imm_expr.X_add_number | |
8169 | && imm_expr.X_add_number < 512) | |
8170 | { | |
8171 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 8172 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
8173 | break; |
8174 | } | |
252b5132 RH |
8175 | if (imm_expr.X_op == O_constant |
8176 | && imm_expr.X_add_number >= 0 | |
8177 | && imm_expr.X_add_number < 0x10000) | |
8178 | { | |
67c0d1eb | 8179 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
8180 | } |
8181 | else if (imm_expr.X_op == O_constant | |
8182 | && imm_expr.X_add_number > -0x8000 | |
8183 | && imm_expr.X_add_number < 0) | |
8184 | { | |
8185 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8186 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 8187 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 8188 | } |
dd3cbb7e NC |
8189 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
8190 | { | |
8191 | used_at = 1; | |
8192 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
8193 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
8194 | break; | |
8195 | } | |
252b5132 RH |
8196 | else |
8197 | { | |
67c0d1eb RS |
8198 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
8199 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
8200 | used_at = 1; |
8201 | } | |
67c0d1eb | 8202 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 8203 | break; |
252b5132 RH |
8204 | |
8205 | case M_DSUB_I: | |
8206 | dbl = 1; | |
8207 | case M_SUB_I: | |
8208 | if (imm_expr.X_op == O_constant | |
8209 | && imm_expr.X_add_number > -0x8000 | |
8210 | && imm_expr.X_add_number <= 0x8000) | |
8211 | { | |
8212 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
8213 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
8214 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 8215 | break; |
252b5132 | 8216 | } |
8fc2e39e | 8217 | used_at = 1; |
67c0d1eb RS |
8218 | load_register (AT, &imm_expr, dbl); |
8219 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
8220 | break; |
8221 | ||
8222 | case M_DSUBU_I: | |
8223 | dbl = 1; | |
8224 | case M_SUBU_I: | |
8225 | if (imm_expr.X_op == O_constant | |
8226 | && imm_expr.X_add_number > -0x8000 | |
8227 | && imm_expr.X_add_number <= 0x8000) | |
8228 | { | |
8229 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
8230 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
8231 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 8232 | break; |
252b5132 | 8233 | } |
8fc2e39e | 8234 | used_at = 1; |
67c0d1eb RS |
8235 | load_register (AT, &imm_expr, dbl); |
8236 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
8237 | break; |
8238 | ||
8239 | case M_TEQ_I: | |
8240 | s = "teq"; | |
8241 | goto trap; | |
8242 | case M_TGE_I: | |
8243 | s = "tge"; | |
8244 | goto trap; | |
8245 | case M_TGEU_I: | |
8246 | s = "tgeu"; | |
8247 | goto trap; | |
8248 | case M_TLT_I: | |
8249 | s = "tlt"; | |
8250 | goto trap; | |
8251 | case M_TLTU_I: | |
8252 | s = "tltu"; | |
8253 | goto trap; | |
8254 | case M_TNE_I: | |
8255 | s = "tne"; | |
8256 | trap: | |
8fc2e39e | 8257 | used_at = 1; |
67c0d1eb RS |
8258 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
8259 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
8260 | break; |
8261 | ||
252b5132 | 8262 | case M_TRUNCWS: |
43841e91 | 8263 | case M_TRUNCWD: |
9c2799c2 | 8264 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 8265 | used_at = 1; |
252b5132 RH |
8266 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
8267 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
8268 | ||
8269 | /* | |
8270 | * Is the double cfc1 instruction a bug in the mips assembler; | |
8271 | * or is there a reason for it? | |
8272 | */ | |
7d10b47d | 8273 | start_noreorder (); |
67c0d1eb RS |
8274 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
8275 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
8276 | macro_build (NULL, "nop", ""); | |
252b5132 | 8277 | expr1.X_add_number = 3; |
67c0d1eb | 8278 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 8279 | expr1.X_add_number = 2; |
67c0d1eb RS |
8280 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
8281 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
8282 | macro_build (NULL, "nop", ""); | |
8283 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
8284 | dreg, sreg); | |
8285 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
8286 | macro_build (NULL, "nop", ""); | |
7d10b47d | 8287 | end_noreorder (); |
252b5132 RH |
8288 | break; |
8289 | ||
8290 | case M_ULH: | |
8291 | s = "lb"; | |
8292 | goto ulh; | |
8293 | case M_ULHU: | |
8294 | s = "lbu"; | |
8295 | ulh: | |
8fc2e39e | 8296 | used_at = 1; |
252b5132 | 8297 | if (offset_expr.X_add_number >= 0x7fff) |
f71d0d44 | 8298 | as_bad (_("Operand overflow")); |
90ecf173 | 8299 | if (!target_big_endian) |
f9419b05 | 8300 | ++offset_expr.X_add_number; |
67c0d1eb | 8301 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
90ecf173 | 8302 | if (!target_big_endian) |
f9419b05 | 8303 | --offset_expr.X_add_number; |
252b5132 | 8304 | else |
f9419b05 | 8305 | ++offset_expr.X_add_number; |
67c0d1eb RS |
8306 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8307 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
8308 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8309 | break; |
8310 | ||
8311 | case M_ULD: | |
8312 | s = "ldl"; | |
8313 | s2 = "ldr"; | |
8314 | off = 7; | |
8315 | goto ulw; | |
8316 | case M_ULW: | |
8317 | s = "lwl"; | |
8318 | s2 = "lwr"; | |
8319 | off = 3; | |
8320 | ulw: | |
8321 | if (offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 8322 | as_bad (_("Operand overflow")); |
af22f5b2 CD |
8323 | if (treg != breg) |
8324 | tempreg = treg; | |
8325 | else | |
8fc2e39e TS |
8326 | { |
8327 | used_at = 1; | |
8328 | tempreg = AT; | |
8329 | } | |
90ecf173 | 8330 | if (!target_big_endian) |
252b5132 | 8331 | offset_expr.X_add_number += off; |
67c0d1eb | 8332 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
90ecf173 | 8333 | if (!target_big_endian) |
252b5132 RH |
8334 | offset_expr.X_add_number -= off; |
8335 | else | |
8336 | offset_expr.X_add_number += off; | |
67c0d1eb | 8337 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 | 8338 | |
90ecf173 | 8339 | /* If necessary, move the result in tempreg to the final destination. */ |
af22f5b2 | 8340 | if (treg == tempreg) |
8fc2e39e | 8341 | break; |
af22f5b2 | 8342 | /* Protect second load's delay slot. */ |
017315e4 | 8343 | load_delay_nop (); |
67c0d1eb | 8344 | move_register (treg, tempreg); |
af22f5b2 | 8345 | break; |
252b5132 RH |
8346 | |
8347 | case M_ULD_A: | |
8348 | s = "ldl"; | |
8349 | s2 = "ldr"; | |
8350 | off = 7; | |
8351 | goto ulwa; | |
8352 | case M_ULW_A: | |
8353 | s = "lwl"; | |
8354 | s2 = "lwr"; | |
8355 | off = 3; | |
8356 | ulwa: | |
d6bc6245 | 8357 | used_at = 1; |
67c0d1eb | 8358 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8359 | if (breg != 0) |
67c0d1eb | 8360 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
90ecf173 | 8361 | if (!target_big_endian) |
252b5132 RH |
8362 | expr1.X_add_number = off; |
8363 | else | |
8364 | expr1.X_add_number = 0; | |
67c0d1eb | 8365 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
90ecf173 | 8366 | if (!target_big_endian) |
252b5132 RH |
8367 | expr1.X_add_number = 0; |
8368 | else | |
8369 | expr1.X_add_number = off; | |
67c0d1eb | 8370 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8371 | break; |
8372 | ||
8373 | case M_ULH_A: | |
8374 | case M_ULHU_A: | |
d6bc6245 | 8375 | used_at = 1; |
67c0d1eb | 8376 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8377 | if (breg != 0) |
67c0d1eb | 8378 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8379 | if (target_big_endian) |
8380 | expr1.X_add_number = 0; | |
67c0d1eb | 8381 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 8382 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8383 | if (target_big_endian) |
8384 | expr1.X_add_number = 1; | |
8385 | else | |
8386 | expr1.X_add_number = 0; | |
67c0d1eb RS |
8387 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
8388 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
8389 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8390 | break; |
8391 | ||
8392 | case M_USH: | |
8fc2e39e | 8393 | used_at = 1; |
252b5132 | 8394 | if (offset_expr.X_add_number >= 0x7fff) |
f71d0d44 | 8395 | as_bad (_("Operand overflow")); |
252b5132 | 8396 | if (target_big_endian) |
f9419b05 | 8397 | ++offset_expr.X_add_number; |
67c0d1eb RS |
8398 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8399 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 8400 | if (target_big_endian) |
f9419b05 | 8401 | --offset_expr.X_add_number; |
252b5132 | 8402 | else |
f9419b05 | 8403 | ++offset_expr.X_add_number; |
67c0d1eb | 8404 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
8405 | break; |
8406 | ||
8407 | case M_USD: | |
8408 | s = "sdl"; | |
8409 | s2 = "sdr"; | |
8410 | off = 7; | |
8411 | goto usw; | |
8412 | case M_USW: | |
8413 | s = "swl"; | |
8414 | s2 = "swr"; | |
8415 | off = 3; | |
8416 | usw: | |
8417 | if (offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 8418 | as_bad (_("Operand overflow")); |
90ecf173 | 8419 | if (!target_big_endian) |
252b5132 | 8420 | offset_expr.X_add_number += off; |
67c0d1eb | 8421 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
90ecf173 | 8422 | if (!target_big_endian) |
252b5132 RH |
8423 | offset_expr.X_add_number -= off; |
8424 | else | |
8425 | offset_expr.X_add_number += off; | |
67c0d1eb | 8426 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 8427 | break; |
252b5132 RH |
8428 | |
8429 | case M_USD_A: | |
8430 | s = "sdl"; | |
8431 | s2 = "sdr"; | |
8432 | off = 7; | |
8433 | goto uswa; | |
8434 | case M_USW_A: | |
8435 | s = "swl"; | |
8436 | s2 = "swr"; | |
8437 | off = 3; | |
8438 | uswa: | |
d6bc6245 | 8439 | used_at = 1; |
67c0d1eb | 8440 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8441 | if (breg != 0) |
67c0d1eb | 8442 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
90ecf173 | 8443 | if (!target_big_endian) |
252b5132 RH |
8444 | expr1.X_add_number = off; |
8445 | else | |
8446 | expr1.X_add_number = 0; | |
67c0d1eb | 8447 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
90ecf173 | 8448 | if (!target_big_endian) |
252b5132 RH |
8449 | expr1.X_add_number = 0; |
8450 | else | |
8451 | expr1.X_add_number = off; | |
67c0d1eb | 8452 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8453 | break; |
8454 | ||
8455 | case M_USH_A: | |
d6bc6245 | 8456 | used_at = 1; |
67c0d1eb | 8457 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8458 | if (breg != 0) |
67c0d1eb | 8459 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
90ecf173 | 8460 | if (!target_big_endian) |
252b5132 | 8461 | expr1.X_add_number = 0; |
67c0d1eb RS |
8462 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
8463 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
90ecf173 | 8464 | if (!target_big_endian) |
252b5132 RH |
8465 | expr1.X_add_number = 1; |
8466 | else | |
8467 | expr1.X_add_number = 0; | |
67c0d1eb | 8468 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
90ecf173 | 8469 | if (!target_big_endian) |
252b5132 RH |
8470 | expr1.X_add_number = 0; |
8471 | else | |
8472 | expr1.X_add_number = 1; | |
67c0d1eb RS |
8473 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
8474 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
8475 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8476 | break; |
8477 | ||
8478 | default: | |
8479 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 8480 | are added dynamically. */ |
252b5132 RH |
8481 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
8482 | break; | |
8483 | } | |
741fe287 | 8484 | if (!mips_opts.at && used_at) |
8fc2e39e | 8485 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
8486 | } |
8487 | ||
8488 | /* Implement macros in mips16 mode. */ | |
8489 | ||
8490 | static void | |
17a2f251 | 8491 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
8492 | { |
8493 | int mask; | |
8494 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
8495 | expressionS expr1; |
8496 | int dbl; | |
8497 | const char *s, *s2, *s3; | |
8498 | ||
8499 | mask = ip->insn_mo->mask; | |
8500 | ||
bf12938e RS |
8501 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
8502 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
8503 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 8504 | |
252b5132 RH |
8505 | expr1.X_op = O_constant; |
8506 | expr1.X_op_symbol = NULL; | |
8507 | expr1.X_add_symbol = NULL; | |
8508 | expr1.X_add_number = 1; | |
8509 | ||
8510 | dbl = 0; | |
8511 | ||
8512 | switch (mask) | |
8513 | { | |
8514 | default: | |
8515 | internalError (); | |
8516 | ||
8517 | case M_DDIV_3: | |
8518 | dbl = 1; | |
8519 | case M_DIV_3: | |
8520 | s = "mflo"; | |
8521 | goto do_div3; | |
8522 | case M_DREM_3: | |
8523 | dbl = 1; | |
8524 | case M_REM_3: | |
8525 | s = "mfhi"; | |
8526 | do_div3: | |
7d10b47d | 8527 | start_noreorder (); |
67c0d1eb | 8528 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 8529 | expr1.X_add_number = 2; |
67c0d1eb RS |
8530 | macro_build (&expr1, "bnez", "x,p", yreg); |
8531 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 8532 | |
252b5132 RH |
8533 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
8534 | since that causes an overflow. We should do that as well, | |
8535 | but I don't see how to do the comparisons without a temporary | |
8536 | register. */ | |
7d10b47d | 8537 | end_noreorder (); |
67c0d1eb | 8538 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
8539 | break; |
8540 | ||
8541 | case M_DIVU_3: | |
8542 | s = "divu"; | |
8543 | s2 = "mflo"; | |
8544 | goto do_divu3; | |
8545 | case M_REMU_3: | |
8546 | s = "divu"; | |
8547 | s2 = "mfhi"; | |
8548 | goto do_divu3; | |
8549 | case M_DDIVU_3: | |
8550 | s = "ddivu"; | |
8551 | s2 = "mflo"; | |
8552 | goto do_divu3; | |
8553 | case M_DREMU_3: | |
8554 | s = "ddivu"; | |
8555 | s2 = "mfhi"; | |
8556 | do_divu3: | |
7d10b47d | 8557 | start_noreorder (); |
67c0d1eb | 8558 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 8559 | expr1.X_add_number = 2; |
67c0d1eb RS |
8560 | macro_build (&expr1, "bnez", "x,p", yreg); |
8561 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 8562 | end_noreorder (); |
67c0d1eb | 8563 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
8564 | break; |
8565 | ||
8566 | case M_DMUL: | |
8567 | dbl = 1; | |
8568 | case M_MUL: | |
67c0d1eb RS |
8569 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
8570 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 8571 | break; |
252b5132 RH |
8572 | |
8573 | case M_DSUBU_I: | |
8574 | dbl = 1; | |
8575 | goto do_subu; | |
8576 | case M_SUBU_I: | |
8577 | do_subu: | |
8578 | if (imm_expr.X_op != O_constant) | |
8579 | as_bad (_("Unsupported large constant")); | |
8580 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8581 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
8582 | break; |
8583 | ||
8584 | case M_SUBU_I_2: | |
8585 | if (imm_expr.X_op != O_constant) | |
8586 | as_bad (_("Unsupported large constant")); | |
8587 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8588 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
8589 | break; |
8590 | ||
8591 | case M_DSUBU_I_2: | |
8592 | if (imm_expr.X_op != O_constant) | |
8593 | as_bad (_("Unsupported large constant")); | |
8594 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8595 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
8596 | break; |
8597 | ||
8598 | case M_BEQ: | |
8599 | s = "cmp"; | |
8600 | s2 = "bteqz"; | |
8601 | goto do_branch; | |
8602 | case M_BNE: | |
8603 | s = "cmp"; | |
8604 | s2 = "btnez"; | |
8605 | goto do_branch; | |
8606 | case M_BLT: | |
8607 | s = "slt"; | |
8608 | s2 = "btnez"; | |
8609 | goto do_branch; | |
8610 | case M_BLTU: | |
8611 | s = "sltu"; | |
8612 | s2 = "btnez"; | |
8613 | goto do_branch; | |
8614 | case M_BLE: | |
8615 | s = "slt"; | |
8616 | s2 = "bteqz"; | |
8617 | goto do_reverse_branch; | |
8618 | case M_BLEU: | |
8619 | s = "sltu"; | |
8620 | s2 = "bteqz"; | |
8621 | goto do_reverse_branch; | |
8622 | case M_BGE: | |
8623 | s = "slt"; | |
8624 | s2 = "bteqz"; | |
8625 | goto do_branch; | |
8626 | case M_BGEU: | |
8627 | s = "sltu"; | |
8628 | s2 = "bteqz"; | |
8629 | goto do_branch; | |
8630 | case M_BGT: | |
8631 | s = "slt"; | |
8632 | s2 = "btnez"; | |
8633 | goto do_reverse_branch; | |
8634 | case M_BGTU: | |
8635 | s = "sltu"; | |
8636 | s2 = "btnez"; | |
8637 | ||
8638 | do_reverse_branch: | |
8639 | tmp = xreg; | |
8640 | xreg = yreg; | |
8641 | yreg = tmp; | |
8642 | ||
8643 | do_branch: | |
67c0d1eb RS |
8644 | macro_build (NULL, s, "x,y", xreg, yreg); |
8645 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8646 | break; |
8647 | ||
8648 | case M_BEQ_I: | |
8649 | s = "cmpi"; | |
8650 | s2 = "bteqz"; | |
8651 | s3 = "x,U"; | |
8652 | goto do_branch_i; | |
8653 | case M_BNE_I: | |
8654 | s = "cmpi"; | |
8655 | s2 = "btnez"; | |
8656 | s3 = "x,U"; | |
8657 | goto do_branch_i; | |
8658 | case M_BLT_I: | |
8659 | s = "slti"; | |
8660 | s2 = "btnez"; | |
8661 | s3 = "x,8"; | |
8662 | goto do_branch_i; | |
8663 | case M_BLTU_I: | |
8664 | s = "sltiu"; | |
8665 | s2 = "btnez"; | |
8666 | s3 = "x,8"; | |
8667 | goto do_branch_i; | |
8668 | case M_BLE_I: | |
8669 | s = "slti"; | |
8670 | s2 = "btnez"; | |
8671 | s3 = "x,8"; | |
8672 | goto do_addone_branch_i; | |
8673 | case M_BLEU_I: | |
8674 | s = "sltiu"; | |
8675 | s2 = "btnez"; | |
8676 | s3 = "x,8"; | |
8677 | goto do_addone_branch_i; | |
8678 | case M_BGE_I: | |
8679 | s = "slti"; | |
8680 | s2 = "bteqz"; | |
8681 | s3 = "x,8"; | |
8682 | goto do_branch_i; | |
8683 | case M_BGEU_I: | |
8684 | s = "sltiu"; | |
8685 | s2 = "bteqz"; | |
8686 | s3 = "x,8"; | |
8687 | goto do_branch_i; | |
8688 | case M_BGT_I: | |
8689 | s = "slti"; | |
8690 | s2 = "bteqz"; | |
8691 | s3 = "x,8"; | |
8692 | goto do_addone_branch_i; | |
8693 | case M_BGTU_I: | |
8694 | s = "sltiu"; | |
8695 | s2 = "bteqz"; | |
8696 | s3 = "x,8"; | |
8697 | ||
8698 | do_addone_branch_i: | |
8699 | if (imm_expr.X_op != O_constant) | |
8700 | as_bad (_("Unsupported large constant")); | |
8701 | ++imm_expr.X_add_number; | |
8702 | ||
8703 | do_branch_i: | |
67c0d1eb RS |
8704 | macro_build (&imm_expr, s, s3, xreg); |
8705 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8706 | break; |
8707 | ||
8708 | case M_ABS: | |
8709 | expr1.X_add_number = 0; | |
67c0d1eb | 8710 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 8711 | if (xreg != yreg) |
67c0d1eb | 8712 | move_register (xreg, yreg); |
252b5132 | 8713 | expr1.X_add_number = 2; |
67c0d1eb RS |
8714 | macro_build (&expr1, "bteqz", "p"); |
8715 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
8716 | } |
8717 | } | |
8718 | ||
8719 | /* For consistency checking, verify that all bits are specified either | |
8720 | by the match/mask part of the instruction definition, or by the | |
8721 | operand list. */ | |
8722 | static int | |
17a2f251 | 8723 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
8724 | { |
8725 | const char *p = opc->args; | |
8726 | char c; | |
8727 | unsigned long used_bits = opc->mask; | |
8728 | ||
8729 | if ((used_bits & opc->match) != opc->match) | |
8730 | { | |
8731 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8732 | opc->name, opc->args); | |
8733 | return 0; | |
8734 | } | |
8735 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8736 | while (*p) | |
8737 | switch (c = *p++) | |
8738 | { | |
8739 | case ',': break; | |
8740 | case '(': break; | |
8741 | case ')': break; | |
af7ee8bf CD |
8742 | case '+': |
8743 | switch (c = *p++) | |
8744 | { | |
9bcd4f99 TS |
8745 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
8746 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
8747 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
8748 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
8749 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8750 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8751 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8752 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8753 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
8754 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8755 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8756 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8757 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8758 | case 'I': break; | |
ef2e4d86 CF |
8759 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
8760 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
8761 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
8762 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
8763 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
8764 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
8765 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 8766 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
8767 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
8768 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
8769 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
8770 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
8771 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
8772 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
8773 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
bb35fb24 | 8774 | |
af7ee8bf CD |
8775 | default: |
8776 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8777 | c, opc->name, opc->args); | |
8778 | return 0; | |
8779 | } | |
8780 | break; | |
252b5132 RH |
8781 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8782 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8783 | case 'A': break; | |
4372b673 | 8784 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8785 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8786 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8787 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8788 | case 'F': break; | |
8789 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8790 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8791 | case 'I': break; |
e972090a | 8792 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8793 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8794 | case 'L': break; |
8795 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8796 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8797 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8798 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8799 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8800 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8801 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8802 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8803 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8804 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8805 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8806 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8807 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8808 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8809 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8810 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8811 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8812 | case 'f': break; | |
8813 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8814 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8815 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8816 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8817 | case 'l': break; | |
8818 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8819 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8820 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8821 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8822 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8823 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8824 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8825 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8826 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8827 | case 'x': break; | |
8828 | case 'z': break; | |
8829 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8830 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8831 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8832 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8833 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8834 | case '[': break; | |
8835 | case ']': break; | |
620edafd | 8836 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 8837 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
8838 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
8839 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
8840 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
8841 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8842 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
8843 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
8844 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
8845 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
8846 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
8847 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
8848 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
8849 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
8850 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
8851 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
8852 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
8853 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
252b5132 RH |
8854 | default: |
8855 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8856 | c, opc->name, opc->args); | |
8857 | return 0; | |
8858 | } | |
8859 | #undef USE_BITS | |
8860 | if (used_bits != 0xffffffff) | |
8861 | { | |
8862 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8863 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8864 | return 0; | |
8865 | } | |
8866 | return 1; | |
8867 | } | |
8868 | ||
9bcd4f99 TS |
8869 | /* UDI immediates. */ |
8870 | struct mips_immed { | |
8871 | char type; | |
8872 | unsigned int shift; | |
8873 | unsigned long mask; | |
8874 | const char * desc; | |
8875 | }; | |
8876 | ||
8877 | static const struct mips_immed mips_immed[] = { | |
8878 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
8879 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
8880 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
8881 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
8882 | { 0,0,0,0 } | |
8883 | }; | |
8884 | ||
7455baf8 TS |
8885 | /* Check whether an odd floating-point register is allowed. */ |
8886 | static int | |
8887 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
8888 | { | |
8889 | const char *s = insn->name; | |
8890 | ||
8891 | if (insn->pinfo == INSN_MACRO) | |
8892 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
8893 | return 1; | |
8894 | ||
8895 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
8896 | { | |
8897 | /* Allow odd registers for single-precision ops. */ | |
8898 | switch (insn->pinfo & (FP_S | FP_D)) | |
8899 | { | |
8900 | case FP_S: | |
8901 | case 0: | |
8902 | return 1; /* both single precision - ok */ | |
8903 | case FP_D: | |
8904 | return 0; /* both double precision - fail */ | |
8905 | default: | |
8906 | break; | |
8907 | } | |
8908 | ||
8909 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
8910 | s = strchr (insn->name, '.'); | |
8911 | if (argnum == 2) | |
8912 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
8913 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
8914 | } | |
8915 | ||
8916 | /* Single-precision coprocessor loads and moves are OK too. */ | |
8917 | if ((insn->pinfo & FP_S) | |
8918 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
8919 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
8920 | return 1; | |
8921 | ||
8922 | return 0; | |
8923 | } | |
8924 | ||
252b5132 RH |
8925 | /* This routine assembles an instruction into its binary format. As a |
8926 | side effect, it sets one of the global variables imm_reloc or | |
8927 | offset_reloc to the type of relocation to do if one of the operands | |
8928 | is an address expression. */ | |
8929 | ||
8930 | static void | |
17a2f251 | 8931 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8932 | { |
8933 | char *s; | |
8934 | const char *args; | |
43841e91 | 8935 | char c = 0; |
252b5132 RH |
8936 | struct mips_opcode *insn; |
8937 | char *argsStart; | |
8938 | unsigned int regno; | |
34224acf | 8939 | unsigned int lastregno; |
af7ee8bf | 8940 | unsigned int lastpos = 0; |
071742cf | 8941 | unsigned int limlo, limhi; |
252b5132 RH |
8942 | char *s_reset; |
8943 | char save_c = 0; | |
74cd071d | 8944 | offsetT min_range, max_range; |
707bfff6 TS |
8945 | int argnum; |
8946 | unsigned int rtype; | |
252b5132 RH |
8947 | |
8948 | insn_error = NULL; | |
8949 | ||
8950 | /* If the instruction contains a '.', we first try to match an instruction | |
8951 | including the '.'. Then we try again without the '.'. */ | |
8952 | insn = NULL; | |
3882b010 | 8953 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8954 | continue; |
8955 | ||
8956 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8957 | the call to hash_find. Save the character we replaced just in case we | |
8958 | have to re-parse the instruction. */ | |
3882b010 | 8959 | if (ISSPACE (*s)) |
252b5132 RH |
8960 | { |
8961 | save_c = *s; | |
8962 | *s++ = '\0'; | |
8963 | } | |
bdaaa2e1 | 8964 | |
252b5132 RH |
8965 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8966 | ||
8967 | /* If we didn't find the instruction in the opcode table, try again, but | |
8968 | this time with just the instruction up to, but not including the | |
8969 | first '.'. */ | |
8970 | if (insn == NULL) | |
8971 | { | |
bdaaa2e1 | 8972 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8973 | if (save_c) |
8974 | *(--s) = save_c; | |
8975 | ||
8976 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8977 | for (s = str; |
8978 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8979 | ++s) | |
252b5132 RH |
8980 | continue; |
8981 | ||
8982 | /* If we did not find a '.', then we can quit now. */ | |
8983 | if (*s != '.') | |
8984 | { | |
f71d0d44 | 8985 | insn_error = _("Unrecognized opcode"); |
252b5132 RH |
8986 | return; |
8987 | } | |
8988 | ||
8989 | /* Lookup the instruction in the hash table. */ | |
8990 | *s++ = '\0'; | |
8991 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8992 | { | |
f71d0d44 | 8993 | insn_error = _("Unrecognized opcode"); |
252b5132 RH |
8994 | return; |
8995 | } | |
252b5132 RH |
8996 | } |
8997 | ||
8998 | argsStart = s; | |
8999 | for (;;) | |
9000 | { | |
b34976b6 | 9001 | bfd_boolean ok; |
252b5132 | 9002 | |
9c2799c2 | 9003 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 9004 | |
f79e2745 | 9005 | ok = is_opcode_valid (insn); |
252b5132 RH |
9006 | if (! ok) |
9007 | { | |
9008 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9009 | && strcmp (insn->name, insn[1].name) == 0) | |
9010 | { | |
9011 | ++insn; | |
9012 | continue; | |
9013 | } | |
252b5132 | 9014 | else |
beae10d5 | 9015 | { |
268f6bed L |
9016 | if (!insn_error) |
9017 | { | |
9018 | static char buf[100]; | |
fef14a42 TS |
9019 | sprintf (buf, |
9020 | _("opcode not supported on this processor: %s (%s)"), | |
9021 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
9022 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
9023 | insn_error = buf; |
9024 | } | |
9025 | if (save_c) | |
9026 | *(--s) = save_c; | |
2bd7f1f3 | 9027 | return; |
252b5132 | 9028 | } |
252b5132 RH |
9029 | } |
9030 | ||
1e915849 | 9031 | create_insn (ip, insn); |
268f6bed | 9032 | insn_error = NULL; |
707bfff6 | 9033 | argnum = 1; |
24864476 | 9034 | lastregno = 0xffffffff; |
252b5132 RH |
9035 | for (args = insn->args;; ++args) |
9036 | { | |
deec1734 CD |
9037 | int is_mdmx; |
9038 | ||
ad8d3bb3 | 9039 | s += strspn (s, " \t"); |
deec1734 | 9040 | is_mdmx = 0; |
252b5132 RH |
9041 | switch (*args) |
9042 | { | |
9043 | case '\0': /* end of args */ | |
9044 | if (*s == '\0') | |
9045 | return; | |
9046 | break; | |
9047 | ||
90ecf173 | 9048 | case '2': /* DSP 2-bit unsigned immediate in bit 11. */ |
8b082fb1 TS |
9049 | my_getExpression (&imm_expr, s); |
9050 | check_absolute_expr (ip, &imm_expr); | |
9051 | if ((unsigned long) imm_expr.X_add_number != 1 | |
9052 | && (unsigned long) imm_expr.X_add_number != 3) | |
9053 | { | |
9054 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
9055 | (unsigned long) imm_expr.X_add_number); | |
9056 | } | |
9057 | INSERT_OPERAND (BP, *ip, imm_expr.X_add_number); | |
9058 | imm_expr.X_op = O_absent; | |
9059 | s = expr_end; | |
9060 | continue; | |
9061 | ||
90ecf173 | 9062 | case '3': /* DSP 3-bit unsigned immediate in bit 21. */ |
74cd071d CF |
9063 | my_getExpression (&imm_expr, s); |
9064 | check_absolute_expr (ip, &imm_expr); | |
9065 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
9066 | { | |
a9e24354 TS |
9067 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
9068 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 9069 | } |
a9e24354 | 9070 | INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number); |
74cd071d CF |
9071 | imm_expr.X_op = O_absent; |
9072 | s = expr_end; | |
9073 | continue; | |
9074 | ||
90ecf173 | 9075 | case '4': /* DSP 4-bit unsigned immediate in bit 21. */ |
74cd071d CF |
9076 | my_getExpression (&imm_expr, s); |
9077 | check_absolute_expr (ip, &imm_expr); | |
9078 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
9079 | { | |
a9e24354 TS |
9080 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
9081 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 9082 | } |
a9e24354 | 9083 | INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number); |
74cd071d CF |
9084 | imm_expr.X_op = O_absent; |
9085 | s = expr_end; | |
9086 | continue; | |
9087 | ||
90ecf173 | 9088 | case '5': /* DSP 8-bit unsigned immediate in bit 16. */ |
74cd071d CF |
9089 | my_getExpression (&imm_expr, s); |
9090 | check_absolute_expr (ip, &imm_expr); | |
9091 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
9092 | { | |
a9e24354 TS |
9093 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
9094 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 9095 | } |
a9e24354 | 9096 | INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number); |
74cd071d CF |
9097 | imm_expr.X_op = O_absent; |
9098 | s = expr_end; | |
9099 | continue; | |
9100 | ||
90ecf173 | 9101 | case '6': /* DSP 5-bit unsigned immediate in bit 21. */ |
74cd071d CF |
9102 | my_getExpression (&imm_expr, s); |
9103 | check_absolute_expr (ip, &imm_expr); | |
9104 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
9105 | { | |
a9e24354 TS |
9106 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
9107 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 9108 | } |
a9e24354 | 9109 | INSERT_OPERAND (RS, *ip, imm_expr.X_add_number); |
74cd071d CF |
9110 | imm_expr.X_op = O_absent; |
9111 | s = expr_end; | |
9112 | continue; | |
9113 | ||
90ecf173 | 9114 | case '7': /* Four DSP accumulators in bits 11,12. */ |
74cd071d CF |
9115 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
9116 | s[3] >= '0' && s[3] <= '3') | |
9117 | { | |
9118 | regno = s[3] - '0'; | |
9119 | s += 4; | |
a9e24354 | 9120 | INSERT_OPERAND (DSPACC, *ip, regno); |
74cd071d CF |
9121 | continue; |
9122 | } | |
9123 | else | |
9124 | as_bad (_("Invalid dsp acc register")); | |
9125 | break; | |
9126 | ||
90ecf173 | 9127 | case '8': /* DSP 6-bit unsigned immediate in bit 11. */ |
74cd071d CF |
9128 | my_getExpression (&imm_expr, s); |
9129 | check_absolute_expr (ip, &imm_expr); | |
9130 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
9131 | { | |
a9e24354 TS |
9132 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
9133 | OP_MASK_WRDSP, | |
9134 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 9135 | } |
a9e24354 | 9136 | INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
9137 | imm_expr.X_op = O_absent; |
9138 | s = expr_end; | |
9139 | continue; | |
9140 | ||
90ecf173 | 9141 | case '9': /* Four DSP accumulators in bits 21,22. */ |
74cd071d CF |
9142 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
9143 | s[3] >= '0' && s[3] <= '3') | |
9144 | { | |
9145 | regno = s[3] - '0'; | |
9146 | s += 4; | |
a9e24354 | 9147 | INSERT_OPERAND (DSPACC_S, *ip, regno); |
74cd071d CF |
9148 | continue; |
9149 | } | |
9150 | else | |
9151 | as_bad (_("Invalid dsp acc register")); | |
9152 | break; | |
9153 | ||
90ecf173 | 9154 | case '0': /* DSP 6-bit signed immediate in bit 20. */ |
74cd071d CF |
9155 | my_getExpression (&imm_expr, s); |
9156 | check_absolute_expr (ip, &imm_expr); | |
9157 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
9158 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
9159 | if (imm_expr.X_add_number < min_range || | |
9160 | imm_expr.X_add_number > max_range) | |
9161 | { | |
a9e24354 TS |
9162 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
9163 | (long) min_range, (long) max_range, | |
9164 | (long) imm_expr.X_add_number); | |
74cd071d | 9165 | } |
a9e24354 | 9166 | INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number); |
74cd071d CF |
9167 | imm_expr.X_op = O_absent; |
9168 | s = expr_end; | |
9169 | continue; | |
9170 | ||
90ecf173 | 9171 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
74cd071d CF |
9172 | my_getExpression (&imm_expr, s); |
9173 | check_absolute_expr (ip, &imm_expr); | |
9174 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
9175 | { | |
a9e24354 TS |
9176 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
9177 | OP_MASK_RDDSP, | |
9178 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 9179 | } |
a9e24354 | 9180 | INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
9181 | imm_expr.X_op = O_absent; |
9182 | s = expr_end; | |
9183 | continue; | |
9184 | ||
90ecf173 | 9185 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
74cd071d CF |
9186 | my_getExpression (&imm_expr, s); |
9187 | check_absolute_expr (ip, &imm_expr); | |
9188 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
9189 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
9190 | if (imm_expr.X_add_number < min_range || | |
9191 | imm_expr.X_add_number > max_range) | |
9192 | { | |
a9e24354 TS |
9193 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
9194 | (long) min_range, (long) max_range, | |
9195 | (long) imm_expr.X_add_number); | |
74cd071d | 9196 | } |
a9e24354 | 9197 | INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
9198 | imm_expr.X_op = O_absent; |
9199 | s = expr_end; | |
9200 | continue; | |
9201 | ||
90ecf173 | 9202 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
74cd071d CF |
9203 | my_getExpression (&imm_expr, s); |
9204 | check_absolute_expr (ip, &imm_expr); | |
9205 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
9206 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
9207 | if (imm_expr.X_add_number < min_range || | |
9208 | imm_expr.X_add_number > max_range) | |
9209 | { | |
a9e24354 TS |
9210 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
9211 | (long) min_range, (long) max_range, | |
9212 | (long) imm_expr.X_add_number); | |
74cd071d | 9213 | } |
a9e24354 | 9214 | INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number); |
74cd071d CF |
9215 | imm_expr.X_op = O_absent; |
9216 | s = expr_end; | |
9217 | continue; | |
9218 | ||
a9e24354 | 9219 | case '!': /* MT usermode flag bit. */ |
ef2e4d86 CF |
9220 | my_getExpression (&imm_expr, s); |
9221 | check_absolute_expr (ip, &imm_expr); | |
9222 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
9223 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
9224 | (unsigned long) imm_expr.X_add_number); | |
9225 | INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
9226 | imm_expr.X_op = O_absent; |
9227 | s = expr_end; | |
9228 | continue; | |
9229 | ||
a9e24354 | 9230 | case '$': /* MT load high flag bit. */ |
ef2e4d86 CF |
9231 | my_getExpression (&imm_expr, s); |
9232 | check_absolute_expr (ip, &imm_expr); | |
9233 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
9234 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
9235 | (unsigned long) imm_expr.X_add_number); | |
9236 | INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
9237 | imm_expr.X_op = O_absent; |
9238 | s = expr_end; | |
9239 | continue; | |
9240 | ||
90ecf173 | 9241 | case '*': /* Four DSP accumulators in bits 18,19. */ |
ef2e4d86 CF |
9242 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
9243 | s[3] >= '0' && s[3] <= '3') | |
9244 | { | |
9245 | regno = s[3] - '0'; | |
9246 | s += 4; | |
a9e24354 | 9247 | INSERT_OPERAND (MTACC_T, *ip, regno); |
ef2e4d86 CF |
9248 | continue; |
9249 | } | |
9250 | else | |
9251 | as_bad (_("Invalid dsp/smartmips acc register")); | |
9252 | break; | |
9253 | ||
90ecf173 | 9254 | case '&': /* Four DSP accumulators in bits 13,14. */ |
ef2e4d86 CF |
9255 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
9256 | s[3] >= '0' && s[3] <= '3') | |
9257 | { | |
9258 | regno = s[3] - '0'; | |
9259 | s += 4; | |
a9e24354 | 9260 | INSERT_OPERAND (MTACC_D, *ip, regno); |
ef2e4d86 CF |
9261 | continue; |
9262 | } | |
9263 | else | |
9264 | as_bad (_("Invalid dsp/smartmips acc register")); | |
9265 | break; | |
9266 | ||
252b5132 | 9267 | case ',': |
a339155f | 9268 | ++argnum; |
252b5132 RH |
9269 | if (*s++ == *args) |
9270 | continue; | |
9271 | s--; | |
9272 | switch (*++args) | |
9273 | { | |
9274 | case 'r': | |
9275 | case 'v': | |
bf12938e | 9276 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9277 | continue; |
9278 | ||
9279 | case 'w': | |
bf12938e | 9280 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
9281 | continue; |
9282 | ||
252b5132 | 9283 | case 'W': |
bf12938e | 9284 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9285 | continue; |
9286 | ||
9287 | case 'V': | |
bf12938e | 9288 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9289 | continue; |
9290 | } | |
9291 | break; | |
9292 | ||
9293 | case '(': | |
9294 | /* Handle optional base register. | |
9295 | Either the base register is omitted or | |
bdaaa2e1 | 9296 | we must have a left paren. */ |
252b5132 RH |
9297 | /* This is dependent on the next operand specifier |
9298 | is a base register specification. */ | |
f9bbfb18 | 9299 | gas_assert (args[1] == 'b'); |
252b5132 RH |
9300 | if (*s == '\0') |
9301 | return; | |
9302 | ||
90ecf173 | 9303 | case ')': /* These must match exactly. */ |
60b63b72 RS |
9304 | case '[': |
9305 | case ']': | |
252b5132 RH |
9306 | if (*s++ == *args) |
9307 | continue; | |
9308 | break; | |
9309 | ||
af7ee8bf CD |
9310 | case '+': /* Opcode extension character. */ |
9311 | switch (*++args) | |
9312 | { | |
9bcd4f99 TS |
9313 | case '1': /* UDI immediates. */ |
9314 | case '2': | |
9315 | case '3': | |
9316 | case '4': | |
9317 | { | |
9318 | const struct mips_immed *imm = mips_immed; | |
9319 | ||
9320 | while (imm->type && imm->type != *args) | |
9321 | ++imm; | |
9322 | if (! imm->type) | |
9323 | internalError (); | |
9324 | my_getExpression (&imm_expr, s); | |
9325 | check_absolute_expr (ip, &imm_expr); | |
9326 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
9327 | { | |
9328 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
9329 | imm->desc ? imm->desc : ip->insn_mo->name, | |
9330 | (unsigned long) imm_expr.X_add_number, | |
9331 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 9332 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
9333 | } |
9334 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
9335 | << imm->shift); | |
9336 | imm_expr.X_op = O_absent; | |
9337 | s = expr_end; | |
9338 | } | |
9339 | continue; | |
90ecf173 | 9340 | |
071742cf CD |
9341 | case 'A': /* ins/ext position, becomes LSB. */ |
9342 | limlo = 0; | |
9343 | limhi = 31; | |
5f74bc13 CD |
9344 | goto do_lsb; |
9345 | case 'E': | |
9346 | limlo = 32; | |
9347 | limhi = 63; | |
9348 | goto do_lsb; | |
90ecf173 | 9349 | do_lsb: |
071742cf CD |
9350 | my_getExpression (&imm_expr, s); |
9351 | check_absolute_expr (ip, &imm_expr); | |
9352 | if ((unsigned long) imm_expr.X_add_number < limlo | |
9353 | || (unsigned long) imm_expr.X_add_number > limhi) | |
9354 | { | |
9355 | as_bad (_("Improper position (%lu)"), | |
9356 | (unsigned long) imm_expr.X_add_number); | |
9357 | imm_expr.X_add_number = limlo; | |
9358 | } | |
9359 | lastpos = imm_expr.X_add_number; | |
bf12938e | 9360 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
9361 | imm_expr.X_op = O_absent; |
9362 | s = expr_end; | |
9363 | continue; | |
9364 | ||
9365 | case 'B': /* ins size, becomes MSB. */ | |
9366 | limlo = 1; | |
9367 | limhi = 32; | |
5f74bc13 CD |
9368 | goto do_msb; |
9369 | case 'F': | |
9370 | limlo = 33; | |
9371 | limhi = 64; | |
9372 | goto do_msb; | |
90ecf173 | 9373 | do_msb: |
071742cf CD |
9374 | my_getExpression (&imm_expr, s); |
9375 | check_absolute_expr (ip, &imm_expr); | |
9376 | /* Check for negative input so that small negative numbers | |
9377 | will not succeed incorrectly. The checks against | |
9378 | (pos+size) transitively check "size" itself, | |
9379 | assuming that "pos" is reasonable. */ | |
9380 | if ((long) imm_expr.X_add_number < 0 | |
9381 | || ((unsigned long) imm_expr.X_add_number | |
9382 | + lastpos) < limlo | |
9383 | || ((unsigned long) imm_expr.X_add_number | |
9384 | + lastpos) > limhi) | |
9385 | { | |
9386 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
9387 | (unsigned long) imm_expr.X_add_number, | |
9388 | (unsigned long) lastpos); | |
9389 | imm_expr.X_add_number = limlo - lastpos; | |
9390 | } | |
bf12938e RS |
9391 | INSERT_OPERAND (INSMSB, *ip, |
9392 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
9393 | imm_expr.X_op = O_absent; |
9394 | s = expr_end; | |
9395 | continue; | |
9396 | ||
9397 | case 'C': /* ext size, becomes MSBD. */ | |
9398 | limlo = 1; | |
9399 | limhi = 32; | |
5f74bc13 CD |
9400 | goto do_msbd; |
9401 | case 'G': | |
9402 | limlo = 33; | |
9403 | limhi = 64; | |
9404 | goto do_msbd; | |
9405 | case 'H': | |
9406 | limlo = 33; | |
9407 | limhi = 64; | |
9408 | goto do_msbd; | |
90ecf173 | 9409 | do_msbd: |
071742cf CD |
9410 | my_getExpression (&imm_expr, s); |
9411 | check_absolute_expr (ip, &imm_expr); | |
9412 | /* Check for negative input so that small negative numbers | |
9413 | will not succeed incorrectly. The checks against | |
9414 | (pos+size) transitively check "size" itself, | |
9415 | assuming that "pos" is reasonable. */ | |
9416 | if ((long) imm_expr.X_add_number < 0 | |
9417 | || ((unsigned long) imm_expr.X_add_number | |
9418 | + lastpos) < limlo | |
9419 | || ((unsigned long) imm_expr.X_add_number | |
9420 | + lastpos) > limhi) | |
9421 | { | |
9422 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
9423 | (unsigned long) imm_expr.X_add_number, | |
9424 | (unsigned long) lastpos); | |
9425 | imm_expr.X_add_number = limlo - lastpos; | |
9426 | } | |
bf12938e | 9427 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
9428 | imm_expr.X_op = O_absent; |
9429 | s = expr_end; | |
9430 | continue; | |
af7ee8bf | 9431 | |
bbcc0807 CD |
9432 | case 'D': |
9433 | /* +D is for disassembly only; never match. */ | |
9434 | break; | |
9435 | ||
5f74bc13 CD |
9436 | case 'I': |
9437 | /* "+I" is like "I", except that imm2_expr is used. */ | |
9438 | my_getExpression (&imm2_expr, s); | |
9439 | if (imm2_expr.X_op != O_big | |
9440 | && imm2_expr.X_op != O_constant) | |
9441 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9442 | if (HAVE_32BIT_GPRS) |
9443 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
9444 | s = expr_end; |
9445 | continue; | |
9446 | ||
707bfff6 | 9447 | case 'T': /* Coprocessor register. */ |
ef2e4d86 CF |
9448 | /* +T is for disassembly only; never match. */ |
9449 | break; | |
9450 | ||
707bfff6 | 9451 | case 't': /* Coprocessor register number. */ |
ef2e4d86 CF |
9452 | if (s[0] == '$' && ISDIGIT (s[1])) |
9453 | { | |
9454 | ++s; | |
9455 | regno = 0; | |
9456 | do | |
9457 | { | |
9458 | regno *= 10; | |
9459 | regno += *s - '0'; | |
9460 | ++s; | |
9461 | } | |
9462 | while (ISDIGIT (*s)); | |
9463 | if (regno > 31) | |
9464 | as_bad (_("Invalid register number (%d)"), regno); | |
9465 | else | |
9466 | { | |
a9e24354 | 9467 | INSERT_OPERAND (RT, *ip, regno); |
ef2e4d86 CF |
9468 | continue; |
9469 | } | |
9470 | } | |
9471 | else | |
9472 | as_bad (_("Invalid coprocessor 0 register number")); | |
9473 | break; | |
9474 | ||
bb35fb24 NC |
9475 | case 'x': |
9476 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
9477 | is not in the valid range. */ | |
9478 | my_getExpression (&imm_expr, s); | |
9479 | check_absolute_expr (ip, &imm_expr); | |
9480 | if ((unsigned) imm_expr.X_add_number > 31) | |
9481 | { | |
9482 | as_bad (_("Improper bit index (%lu)"), | |
9483 | (unsigned long) imm_expr.X_add_number); | |
9484 | imm_expr.X_add_number = 0; | |
9485 | } | |
9486 | INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number); | |
9487 | imm_expr.X_op = O_absent; | |
9488 | s = expr_end; | |
9489 | continue; | |
9490 | ||
9491 | case 'X': | |
9492 | /* bbit[01] bit index when bbit is used but we generate | |
9493 | bbit[01]32 because the index is over 32. Move to the | |
9494 | next candidate if index is not in the valid range. */ | |
9495 | my_getExpression (&imm_expr, s); | |
9496 | check_absolute_expr (ip, &imm_expr); | |
9497 | if ((unsigned) imm_expr.X_add_number < 32 | |
9498 | || (unsigned) imm_expr.X_add_number > 63) | |
9499 | break; | |
9500 | INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32); | |
9501 | imm_expr.X_op = O_absent; | |
9502 | s = expr_end; | |
9503 | continue; | |
9504 | ||
9505 | case 'p': | |
9506 | /* cins, cins32, exts and exts32 position field. Give error | |
9507 | if it's not in the valid range. */ | |
9508 | my_getExpression (&imm_expr, s); | |
9509 | check_absolute_expr (ip, &imm_expr); | |
9510 | if ((unsigned) imm_expr.X_add_number > 31) | |
9511 | { | |
9512 | as_bad (_("Improper position (%lu)"), | |
9513 | (unsigned long) imm_expr.X_add_number); | |
9514 | imm_expr.X_add_number = 0; | |
9515 | } | |
9516 | /* Make the pos explicit to simplify +S. */ | |
9517 | lastpos = imm_expr.X_add_number + 32; | |
9518 | INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number); | |
9519 | imm_expr.X_op = O_absent; | |
9520 | s = expr_end; | |
9521 | continue; | |
9522 | ||
9523 | case 'P': | |
9524 | /* cins, cins32, exts and exts32 position field. Move to | |
9525 | the next candidate if it's not in the valid range. */ | |
9526 | my_getExpression (&imm_expr, s); | |
9527 | check_absolute_expr (ip, &imm_expr); | |
9528 | if ((unsigned) imm_expr.X_add_number < 32 | |
9529 | || (unsigned) imm_expr.X_add_number > 63) | |
9530 | break; | |
9531 | lastpos = imm_expr.X_add_number; | |
9532 | INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32); | |
9533 | imm_expr.X_op = O_absent; | |
9534 | s = expr_end; | |
9535 | continue; | |
9536 | ||
9537 | case 's': | |
9538 | /* cins and exts length-minus-one field. */ | |
9539 | my_getExpression (&imm_expr, s); | |
9540 | check_absolute_expr (ip, &imm_expr); | |
9541 | if ((unsigned long) imm_expr.X_add_number > 31) | |
9542 | { | |
9543 | as_bad (_("Improper size (%lu)"), | |
9544 | (unsigned long) imm_expr.X_add_number); | |
9545 | imm_expr.X_add_number = 0; | |
9546 | } | |
9547 | INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number); | |
9548 | imm_expr.X_op = O_absent; | |
9549 | s = expr_end; | |
9550 | continue; | |
9551 | ||
9552 | case 'S': | |
9553 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
9554 | length-minus-one field. */ | |
9555 | my_getExpression (&imm_expr, s); | |
9556 | check_absolute_expr (ip, &imm_expr); | |
9557 | if ((long) imm_expr.X_add_number < 0 | |
9558 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
9559 | { | |
9560 | as_bad (_("Improper size (%lu)"), | |
9561 | (unsigned long) imm_expr.X_add_number); | |
9562 | imm_expr.X_add_number = 0; | |
9563 | } | |
9564 | INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number); | |
9565 | imm_expr.X_op = O_absent; | |
9566 | s = expr_end; | |
9567 | continue; | |
9568 | ||
dd3cbb7e NC |
9569 | case 'Q': |
9570 | /* seqi/snei immediate field. */ | |
9571 | my_getExpression (&imm_expr, s); | |
9572 | check_absolute_expr (ip, &imm_expr); | |
9573 | if ((long) imm_expr.X_add_number < -512 | |
9574 | || (long) imm_expr.X_add_number >= 512) | |
9575 | { | |
9576 | as_bad (_("Improper immediate (%ld)"), | |
9577 | (long) imm_expr.X_add_number); | |
9578 | imm_expr.X_add_number = 0; | |
9579 | } | |
9580 | INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number); | |
9581 | imm_expr.X_op = O_absent; | |
9582 | s = expr_end; | |
9583 | continue; | |
9584 | ||
98675402 RS |
9585 | case 'a': /* 8-bit signed offset in bit 6 */ |
9586 | my_getExpression (&imm_expr, s); | |
9587 | check_absolute_expr (ip, &imm_expr); | |
9588 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
9589 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
9590 | if (imm_expr.X_add_number < min_range | |
9591 | || imm_expr.X_add_number > max_range) | |
9592 | { | |
c95354ed | 9593 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
9594 | (long) min_range, (long) max_range, |
9595 | (long) imm_expr.X_add_number); | |
9596 | } | |
9597 | INSERT_OPERAND (OFFSET_A, *ip, imm_expr.X_add_number); | |
9598 | imm_expr.X_op = O_absent; | |
9599 | s = expr_end; | |
9600 | continue; | |
9601 | ||
9602 | case 'b': /* 8-bit signed offset in bit 3 */ | |
9603 | my_getExpression (&imm_expr, s); | |
9604 | check_absolute_expr (ip, &imm_expr); | |
9605 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
9606 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
9607 | if (imm_expr.X_add_number < min_range | |
9608 | || imm_expr.X_add_number > max_range) | |
9609 | { | |
c95354ed | 9610 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
9611 | (long) min_range, (long) max_range, |
9612 | (long) imm_expr.X_add_number); | |
9613 | } | |
9614 | INSERT_OPERAND (OFFSET_B, *ip, imm_expr.X_add_number); | |
9615 | imm_expr.X_op = O_absent; | |
9616 | s = expr_end; | |
9617 | continue; | |
9618 | ||
9619 | case 'c': /* 9-bit signed offset in bit 6 */ | |
9620 | my_getExpression (&imm_expr, s); | |
9621 | check_absolute_expr (ip, &imm_expr); | |
9622 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
9623 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
9624 | /* We check the offset range before adjusted. */ |
9625 | min_range <<= 4; | |
9626 | max_range <<= 4; | |
98675402 RS |
9627 | if (imm_expr.X_add_number < min_range |
9628 | || imm_expr.X_add_number > max_range) | |
9629 | { | |
c95354ed | 9630 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
9631 | (long) min_range, (long) max_range, |
9632 | (long) imm_expr.X_add_number); | |
9633 | } | |
c95354ed MX |
9634 | if (imm_expr.X_add_number & 0xf) |
9635 | { | |
9636 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
9637 | (long) imm_expr.X_add_number); | |
9638 | } | |
9639 | /* Right shift 4 bits to adjust the offset operand. */ | |
9640 | INSERT_OPERAND (OFFSET_C, *ip, imm_expr.X_add_number >> 4); | |
98675402 RS |
9641 | imm_expr.X_op = O_absent; |
9642 | s = expr_end; | |
9643 | continue; | |
9644 | ||
9645 | case 'z': | |
9646 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
9647 | break; | |
9648 | if (regno == AT && mips_opts.at) | |
9649 | { | |
9650 | if (mips_opts.at == ATREG) | |
9651 | as_warn (_("used $at without \".set noat\"")); | |
9652 | else | |
9653 | as_warn (_("used $%u with \".set at=$%u\""), | |
9654 | regno, mips_opts.at); | |
9655 | } | |
9656 | INSERT_OPERAND (RZ, *ip, regno); | |
9657 | continue; | |
9658 | ||
9659 | case 'Z': | |
9660 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) | |
9661 | break; | |
9662 | INSERT_OPERAND (FZ, *ip, regno); | |
9663 | continue; | |
9664 | ||
af7ee8bf | 9665 | default: |
f71d0d44 | 9666 | as_bad (_("Internal error: bad mips opcode " |
90ecf173 MR |
9667 | "(unknown extension operand type `+%c'): %s %s"), |
9668 | *args, insn->name, insn->args); | |
af7ee8bf CD |
9669 | /* Further processing is fruitless. */ |
9670 | return; | |
9671 | } | |
9672 | break; | |
9673 | ||
252b5132 RH |
9674 | case '<': /* must be at least one digit */ |
9675 | /* | |
9676 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
9677 | * than 31 or less than 0, then the shift amount should be |
9678 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
9679 | * We issue a warning and mask out all but the low 5 bits. |
9680 | */ | |
9681 | my_getExpression (&imm_expr, s); | |
9682 | check_absolute_expr (ip, &imm_expr); | |
9683 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
9684 | as_warn (_("Improper shift amount (%lu)"), |
9685 | (unsigned long) imm_expr.X_add_number); | |
9686 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9687 | imm_expr.X_op = O_absent; |
9688 | s = expr_end; | |
9689 | continue; | |
9690 | ||
9691 | case '>': /* shift amount minus 32 */ | |
9692 | my_getExpression (&imm_expr, s); | |
9693 | check_absolute_expr (ip, &imm_expr); | |
9694 | if ((unsigned long) imm_expr.X_add_number < 32 | |
9695 | || (unsigned long) imm_expr.X_add_number > 63) | |
9696 | break; | |
bf12938e | 9697 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
9698 | imm_expr.X_op = O_absent; |
9699 | s = expr_end; | |
9700 | continue; | |
9701 | ||
90ecf173 MR |
9702 | case 'k': /* CACHE code. */ |
9703 | case 'h': /* PREFX code. */ | |
9704 | case '1': /* SYNC type. */ | |
252b5132 RH |
9705 | my_getExpression (&imm_expr, s); |
9706 | check_absolute_expr (ip, &imm_expr); | |
9707 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
9708 | as_warn (_("Invalid value for `%s' (%lu)"), |
9709 | ip->insn_mo->name, | |
9710 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 9711 | if (*args == 'k') |
d954098f DD |
9712 | { |
9713 | if (mips_fix_cn63xxp1 && strcmp ("pref", insn->name) == 0) | |
9714 | switch (imm_expr.X_add_number) | |
9715 | { | |
9716 | case 5: | |
9717 | case 25: | |
9718 | case 26: | |
9719 | case 27: | |
9720 | case 28: | |
9721 | case 29: | |
9722 | case 30: | |
9723 | case 31: /* These are ok. */ | |
9724 | break; | |
9725 | ||
9726 | default: /* The rest must be changed to 28. */ | |
9727 | imm_expr.X_add_number = 28; | |
9728 | break; | |
9729 | } | |
9730 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); | |
9731 | } | |
620edafd | 9732 | else if (*args == 'h') |
bf12938e | 9733 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
620edafd CF |
9734 | else |
9735 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9736 | imm_expr.X_op = O_absent; |
9737 | s = expr_end; | |
9738 | continue; | |
9739 | ||
90ecf173 | 9740 | case 'c': /* BREAK code. */ |
252b5132 RH |
9741 | my_getExpression (&imm_expr, s); |
9742 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9743 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE) |
9744 | as_warn (_("Code for %s not in range 0..1023 (%lu)"), | |
9745 | ip->insn_mo->name, | |
bf12938e RS |
9746 | (unsigned long) imm_expr.X_add_number); |
9747 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9748 | imm_expr.X_op = O_absent; |
9749 | s = expr_end; | |
9750 | continue; | |
9751 | ||
90ecf173 | 9752 | case 'q': /* Lower BREAK code. */ |
252b5132 RH |
9753 | my_getExpression (&imm_expr, s); |
9754 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9755 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2) |
9756 | as_warn (_("Lower code for %s not in range 0..1023 (%lu)"), | |
9757 | ip->insn_mo->name, | |
bf12938e RS |
9758 | (unsigned long) imm_expr.X_add_number); |
9759 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9760 | imm_expr.X_op = O_absent; |
9761 | s = expr_end; | |
9762 | continue; | |
9763 | ||
90ecf173 | 9764 | case 'B': /* 20-bit SYSCALL/BREAK code. */ |
156c2f8b | 9765 | my_getExpression (&imm_expr, s); |
156c2f8b | 9766 | check_absolute_expr (ip, &imm_expr); |
793b27f4 | 9767 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
a9e24354 TS |
9768 | as_warn (_("Code for %s not in range 0..1048575 (%lu)"), |
9769 | ip->insn_mo->name, | |
793b27f4 | 9770 | (unsigned long) imm_expr.X_add_number); |
bf12938e | 9771 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
9772 | imm_expr.X_op = O_absent; |
9773 | s = expr_end; | |
9774 | continue; | |
9775 | ||
90ecf173 | 9776 | case 'C': /* Coprocessor code. */ |
beae10d5 | 9777 | my_getExpression (&imm_expr, s); |
252b5132 | 9778 | check_absolute_expr (ip, &imm_expr); |
a9e24354 | 9779 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ) |
252b5132 | 9780 | { |
793b27f4 TS |
9781 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
9782 | (unsigned long) imm_expr.X_add_number); | |
a9e24354 | 9783 | imm_expr.X_add_number &= OP_MASK_COPZ; |
252b5132 | 9784 | } |
a9e24354 | 9785 | INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number); |
beae10d5 KH |
9786 | imm_expr.X_op = O_absent; |
9787 | s = expr_end; | |
9788 | continue; | |
252b5132 | 9789 | |
90ecf173 | 9790 | case 'J': /* 19-bit WAIT code. */ |
4372b673 NC |
9791 | my_getExpression (&imm_expr, s); |
9792 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 9793 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
a9e24354 TS |
9794 | { |
9795 | as_warn (_("Illegal 19-bit code (%lu)"), | |
9796 | (unsigned long) imm_expr.X_add_number); | |
9797 | imm_expr.X_add_number &= OP_MASK_CODE19; | |
9798 | } | |
bf12938e | 9799 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
9800 | imm_expr.X_op = O_absent; |
9801 | s = expr_end; | |
9802 | continue; | |
9803 | ||
707bfff6 | 9804 | case 'P': /* Performance register. */ |
beae10d5 | 9805 | my_getExpression (&imm_expr, s); |
252b5132 | 9806 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 9807 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
9808 | as_warn (_("Invalid performance register (%lu)"), |
9809 | (unsigned long) imm_expr.X_add_number); | |
9810 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
9811 | imm_expr.X_op = O_absent; |
9812 | s = expr_end; | |
9813 | continue; | |
252b5132 | 9814 | |
707bfff6 TS |
9815 | case 'G': /* Coprocessor destination register. */ |
9816 | if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0) | |
9817 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no); | |
9818 | else | |
9819 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
a9e24354 | 9820 | INSERT_OPERAND (RD, *ip, regno); |
707bfff6 TS |
9821 | if (ok) |
9822 | { | |
9823 | lastregno = regno; | |
9824 | continue; | |
9825 | } | |
9826 | else | |
9827 | break; | |
9828 | ||
90ecf173 MR |
9829 | case 'b': /* Base register. */ |
9830 | case 'd': /* Destination register. */ | |
9831 | case 's': /* Source register. */ | |
9832 | case 't': /* Target register. */ | |
9833 | case 'r': /* Both target and source. */ | |
9834 | case 'v': /* Both dest and source. */ | |
9835 | case 'w': /* Both dest and target. */ | |
9836 | case 'E': /* Coprocessor target register. */ | |
9837 | case 'K': /* RDHWR destination register. */ | |
9838 | case 'x': /* Ignore register name. */ | |
9839 | case 'z': /* Must be zero register. */ | |
9840 | case 'U': /* Destination register (CLO/CLZ). */ | |
9841 | case 'g': /* Coprocessor destination register. */ | |
9842 | s_reset = s; | |
707bfff6 TS |
9843 | if (*args == 'E' || *args == 'K') |
9844 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
9845 | else | |
9846 | { | |
9847 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
9848 | if (regno == AT && mips_opts.at) |
9849 | { | |
9850 | if (mips_opts.at == ATREG) | |
f71d0d44 | 9851 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 9852 | else |
f71d0d44 | 9853 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
9854 | regno, mips_opts.at); |
9855 | } | |
707bfff6 TS |
9856 | } |
9857 | if (ok) | |
252b5132 | 9858 | { |
252b5132 RH |
9859 | c = *args; |
9860 | if (*s == ' ') | |
f9419b05 | 9861 | ++s; |
252b5132 RH |
9862 | if (args[1] != *s) |
9863 | { | |
9864 | if (c == 'r' || c == 'v' || c == 'w') | |
9865 | { | |
9866 | regno = lastregno; | |
9867 | s = s_reset; | |
f9419b05 | 9868 | ++args; |
252b5132 RH |
9869 | } |
9870 | } | |
9871 | /* 'z' only matches $0. */ | |
9872 | if (c == 'z' && regno != 0) | |
9873 | break; | |
9874 | ||
24864476 | 9875 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
9876 | { |
9877 | if (regno == lastregno) | |
90ecf173 MR |
9878 | { |
9879 | insn_error | |
f71d0d44 | 9880 | = _("Source and destination must be different"); |
e7c604dd | 9881 | continue; |
90ecf173 | 9882 | } |
24864476 | 9883 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
9884 | { |
9885 | insn_error | |
f71d0d44 | 9886 | = _("A destination register must be supplied"); |
e7c604dd | 9887 | continue; |
90ecf173 | 9888 | } |
e7c604dd | 9889 | } |
90ecf173 MR |
9890 | /* Now that we have assembled one operand, we use the args |
9891 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
9892 | switch (c) |
9893 | { | |
9894 | case 'r': | |
9895 | case 's': | |
9896 | case 'v': | |
9897 | case 'b': | |
bf12938e | 9898 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
9899 | break; |
9900 | case 'd': | |
af7ee8bf | 9901 | case 'K': |
ef2e4d86 | 9902 | case 'g': |
bf12938e | 9903 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 9904 | break; |
4372b673 | 9905 | case 'U': |
bf12938e RS |
9906 | INSERT_OPERAND (RD, *ip, regno); |
9907 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 9908 | break; |
252b5132 RH |
9909 | case 'w': |
9910 | case 't': | |
9911 | case 'E': | |
bf12938e | 9912 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
9913 | break; |
9914 | case 'x': | |
9915 | /* This case exists because on the r3000 trunc | |
9916 | expands into a macro which requires a gp | |
9917 | register. On the r6000 or r4000 it is | |
9918 | assembled into a single instruction which | |
9919 | ignores the register. Thus the insn version | |
9920 | is MIPS_ISA2 and uses 'x', and the macro | |
9921 | version is MIPS_ISA1 and uses 't'. */ | |
9922 | break; | |
9923 | case 'z': | |
9924 | /* This case is for the div instruction, which | |
9925 | acts differently if the destination argument | |
9926 | is $0. This only matches $0, and is checked | |
9927 | outside the switch. */ | |
9928 | break; | |
252b5132 RH |
9929 | } |
9930 | lastregno = regno; | |
9931 | continue; | |
9932 | } | |
252b5132 RH |
9933 | switch (*args++) |
9934 | { | |
9935 | case 'r': | |
9936 | case 'v': | |
bf12938e | 9937 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9938 | continue; |
9939 | case 'w': | |
bf12938e | 9940 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
9941 | continue; |
9942 | } | |
9943 | break; | |
9944 | ||
deec1734 CD |
9945 | case 'O': /* MDMX alignment immediate constant. */ |
9946 | my_getExpression (&imm_expr, s); | |
9947 | check_absolute_expr (ip, &imm_expr); | |
9948 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 9949 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e RS |
9950 | (long) imm_expr.X_add_number); |
9951 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9952 | imm_expr.X_op = O_absent; |
9953 | s = expr_end; | |
9954 | continue; | |
9955 | ||
9956 | case 'Q': /* MDMX vector, element sel, or const. */ | |
9957 | if (s[0] != '$') | |
9958 | { | |
9959 | /* MDMX Immediate. */ | |
9960 | my_getExpression (&imm_expr, s); | |
9961 | check_absolute_expr (ip, &imm_expr); | |
9962 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
9963 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
9964 | (long) imm_expr.X_add_number); | |
9965 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9966 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
9967 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
9968 | else | |
9969 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
9970 | imm_expr.X_op = O_absent; |
9971 | s = expr_end; | |
9972 | continue; | |
9973 | } | |
9974 | /* Not MDMX Immediate. Fall through. */ | |
9975 | case 'X': /* MDMX destination register. */ | |
9976 | case 'Y': /* MDMX source register. */ | |
9977 | case 'Z': /* MDMX target register. */ | |
9978 | is_mdmx = 1; | |
90ecf173 MR |
9979 | case 'D': /* Floating point destination register. */ |
9980 | case 'S': /* Floating point source register. */ | |
9981 | case 'T': /* Floating point target register. */ | |
9982 | case 'R': /* Floating point source register. */ | |
252b5132 RH |
9983 | case 'V': |
9984 | case 'W': | |
707bfff6 TS |
9985 | rtype = RTYPE_FPU; |
9986 | if (is_mdmx | |
9987 | || (mips_opts.ase_mdmx | |
9988 | && (ip->insn_mo->pinfo & FP_D) | |
9989 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
9990 | | INSN_COPROC_MEMORY_DELAY | |
9991 | | INSN_LOAD_COPROC_DELAY | |
9992 | | INSN_LOAD_MEMORY_DELAY | |
9993 | | INSN_STORE_MEMORY)))) | |
9994 | rtype |= RTYPE_VEC; | |
252b5132 | 9995 | s_reset = s; |
707bfff6 | 9996 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 9997 | { |
252b5132 | 9998 | if ((regno & 1) != 0 |
ca4e0257 | 9999 | && HAVE_32BIT_FPRS |
90ecf173 | 10000 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
10001 | as_warn (_("Float register should be even, was %d"), |
10002 | regno); | |
10003 | ||
10004 | c = *args; | |
10005 | if (*s == ' ') | |
f9419b05 | 10006 | ++s; |
252b5132 RH |
10007 | if (args[1] != *s) |
10008 | { | |
10009 | if (c == 'V' || c == 'W') | |
10010 | { | |
10011 | regno = lastregno; | |
10012 | s = s_reset; | |
f9419b05 | 10013 | ++args; |
252b5132 RH |
10014 | } |
10015 | } | |
10016 | switch (c) | |
10017 | { | |
10018 | case 'D': | |
deec1734 | 10019 | case 'X': |
bf12938e | 10020 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
10021 | break; |
10022 | case 'V': | |
10023 | case 'S': | |
deec1734 | 10024 | case 'Y': |
bf12938e | 10025 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 10026 | break; |
deec1734 CD |
10027 | case 'Q': |
10028 | /* This is like 'Z', but also needs to fix the MDMX | |
10029 | vector/scalar select bits. Note that the | |
10030 | scalar immediate case is handled above. */ | |
10031 | if (*s == '[') | |
10032 | { | |
10033 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
10034 | int max_el = (is_qh ? 3 : 7); | |
10035 | s++; | |
10036 | my_getExpression(&imm_expr, s); | |
10037 | check_absolute_expr (ip, &imm_expr); | |
10038 | s = expr_end; | |
10039 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
10040 | as_bad (_("Bad element selector %ld"), |
10041 | (long) imm_expr.X_add_number); | |
deec1734 CD |
10042 | imm_expr.X_add_number &= max_el; |
10043 | ip->insn_opcode |= (imm_expr.X_add_number | |
10044 | << (OP_SH_VSEL + | |
10045 | (is_qh ? 2 : 1))); | |
01a3f561 | 10046 | imm_expr.X_op = O_absent; |
deec1734 | 10047 | if (*s != ']') |
20203fb9 | 10048 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
10049 | else |
10050 | s++; | |
10051 | } | |
10052 | else | |
10053 | { | |
10054 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
10055 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
10056 | << OP_SH_VSEL); | |
10057 | else | |
10058 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
10059 | OP_SH_VSEL); | |
10060 | } | |
90ecf173 | 10061 | /* Fall through. */ |
252b5132 RH |
10062 | case 'W': |
10063 | case 'T': | |
deec1734 | 10064 | case 'Z': |
bf12938e | 10065 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
10066 | break; |
10067 | case 'R': | |
bf12938e | 10068 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
10069 | break; |
10070 | } | |
10071 | lastregno = regno; | |
10072 | continue; | |
10073 | } | |
10074 | ||
252b5132 RH |
10075 | switch (*args++) |
10076 | { | |
10077 | case 'V': | |
bf12938e | 10078 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
10079 | continue; |
10080 | case 'W': | |
bf12938e | 10081 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
10082 | continue; |
10083 | } | |
10084 | break; | |
10085 | ||
10086 | case 'I': | |
10087 | my_getExpression (&imm_expr, s); | |
10088 | if (imm_expr.X_op != O_big | |
10089 | && imm_expr.X_op != O_constant) | |
10090 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
10091 | if (HAVE_32BIT_GPRS) |
10092 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
10093 | s = expr_end; |
10094 | continue; | |
10095 | ||
10096 | case 'A': | |
10097 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 10098 | normalize_address_expr (&offset_expr); |
f6688943 | 10099 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
10100 | s = expr_end; |
10101 | continue; | |
10102 | ||
10103 | case 'F': | |
10104 | case 'L': | |
10105 | case 'f': | |
10106 | case 'l': | |
10107 | { | |
10108 | int f64; | |
ca4e0257 | 10109 | int using_gprs; |
252b5132 RH |
10110 | char *save_in; |
10111 | char *err; | |
10112 | unsigned char temp[8]; | |
10113 | int len; | |
10114 | unsigned int length; | |
10115 | segT seg; | |
10116 | subsegT subseg; | |
10117 | char *p; | |
10118 | ||
10119 | /* These only appear as the last operand in an | |
10120 | instruction, and every instruction that accepts | |
10121 | them in any variant accepts them in all variants. | |
10122 | This means we don't have to worry about backing out | |
10123 | any changes if the instruction does not match. | |
10124 | ||
10125 | The difference between them is the size of the | |
10126 | floating point constant and where it goes. For 'F' | |
10127 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
10128 | is 32 bits. Where the constant is placed is based | |
10129 | on how the MIPS assembler does things: | |
10130 | F -- .rdata | |
10131 | L -- .lit8 | |
10132 | f -- immediate value | |
10133 | l -- .lit4 | |
10134 | ||
10135 | The .lit4 and .lit8 sections are only used if | |
10136 | permitted by the -G argument. | |
10137 | ||
ca4e0257 RS |
10138 | The code below needs to know whether the target register |
10139 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
10140 | 'F' are used with GPR-based instructions and 'l' and | |
10141 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
10142 | |
10143 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 10144 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
10145 | |
10146 | save_in = input_line_pointer; | |
10147 | input_line_pointer = s; | |
10148 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
10149 | length = len; | |
10150 | s = input_line_pointer; | |
10151 | input_line_pointer = save_in; | |
10152 | if (err != NULL && *err != '\0') | |
10153 | { | |
10154 | as_bad (_("Bad floating point constant: %s"), err); | |
10155 | memset (temp, '\0', sizeof temp); | |
10156 | length = f64 ? 8 : 4; | |
10157 | } | |
10158 | ||
9c2799c2 | 10159 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
10160 | |
10161 | if (*args == 'f' | |
10162 | || (*args == 'l' | |
3e722fb5 | 10163 | && (g_switch_value < 4 |
252b5132 RH |
10164 | || (temp[0] == 0 && temp[1] == 0) |
10165 | || (temp[2] == 0 && temp[3] == 0)))) | |
10166 | { | |
10167 | imm_expr.X_op = O_constant; | |
90ecf173 | 10168 | if (!target_big_endian) |
252b5132 RH |
10169 | imm_expr.X_add_number = bfd_getl32 (temp); |
10170 | else | |
10171 | imm_expr.X_add_number = bfd_getb32 (temp); | |
10172 | } | |
10173 | else if (length > 4 | |
90ecf173 | 10174 | && !mips_disable_float_construction |
ca4e0257 RS |
10175 | /* Constants can only be constructed in GPRs and |
10176 | copied to FPRs if the GPRs are at least as wide | |
10177 | as the FPRs. Force the constant into memory if | |
10178 | we are using 64-bit FPRs but the GPRs are only | |
10179 | 32 bits wide. */ | |
10180 | && (using_gprs | |
90ecf173 | 10181 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
10182 | && ((temp[0] == 0 && temp[1] == 0) |
10183 | || (temp[2] == 0 && temp[3] == 0)) | |
10184 | && ((temp[4] == 0 && temp[5] == 0) | |
10185 | || (temp[6] == 0 && temp[7] == 0))) | |
10186 | { | |
ca4e0257 | 10187 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
10188 | instructions. If using 32-bit registers, set |
10189 | imm_expr to the high order 32 bits and offset_expr to | |
10190 | the low order 32 bits. Otherwise, set imm_expr to | |
10191 | the entire 64 bit constant. */ | |
ca4e0257 | 10192 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
10193 | { |
10194 | imm_expr.X_op = O_constant; | |
10195 | offset_expr.X_op = O_constant; | |
90ecf173 | 10196 | if (!target_big_endian) |
252b5132 RH |
10197 | { |
10198 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
10199 | offset_expr.X_add_number = bfd_getl32 (temp); | |
10200 | } | |
10201 | else | |
10202 | { | |
10203 | imm_expr.X_add_number = bfd_getb32 (temp); | |
10204 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
10205 | } | |
10206 | if (offset_expr.X_add_number == 0) | |
10207 | offset_expr.X_op = O_absent; | |
10208 | } | |
10209 | else if (sizeof (imm_expr.X_add_number) > 4) | |
10210 | { | |
10211 | imm_expr.X_op = O_constant; | |
90ecf173 | 10212 | if (!target_big_endian) |
252b5132 RH |
10213 | imm_expr.X_add_number = bfd_getl64 (temp); |
10214 | else | |
10215 | imm_expr.X_add_number = bfd_getb64 (temp); | |
10216 | } | |
10217 | else | |
10218 | { | |
10219 | imm_expr.X_op = O_big; | |
10220 | imm_expr.X_add_number = 4; | |
90ecf173 | 10221 | if (!target_big_endian) |
252b5132 RH |
10222 | { |
10223 | generic_bignum[0] = bfd_getl16 (temp); | |
10224 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
10225 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
10226 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
10227 | } | |
10228 | else | |
10229 | { | |
10230 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
10231 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
10232 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
10233 | generic_bignum[3] = bfd_getb16 (temp); | |
10234 | } | |
10235 | } | |
10236 | } | |
10237 | else | |
10238 | { | |
10239 | const char *newname; | |
10240 | segT new_seg; | |
10241 | ||
10242 | /* Switch to the right section. */ | |
10243 | seg = now_seg; | |
10244 | subseg = now_subseg; | |
10245 | switch (*args) | |
10246 | { | |
10247 | default: /* unused default case avoids warnings. */ | |
10248 | case 'L': | |
10249 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 10250 | if (g_switch_value >= 8) |
252b5132 RH |
10251 | newname = ".lit8"; |
10252 | break; | |
10253 | case 'F': | |
3e722fb5 | 10254 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
10255 | break; |
10256 | case 'l': | |
9c2799c2 | 10257 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
10258 | newname = ".lit4"; |
10259 | break; | |
10260 | } | |
10261 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 10262 | if (IS_ELF) |
252b5132 RH |
10263 | bfd_set_section_flags (stdoutput, new_seg, |
10264 | (SEC_ALLOC | |
10265 | | SEC_LOAD | |
10266 | | SEC_READONLY | |
10267 | | SEC_DATA)); | |
10268 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 10269 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
10270 | record_alignment (new_seg, 4); |
10271 | else | |
10272 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
10273 | if (seg == now_seg) | |
10274 | as_bad (_("Can't use floating point insn in this section")); | |
10275 | ||
10276 | /* Set the argument to the current address in the | |
10277 | section. */ | |
10278 | offset_expr.X_op = O_symbol; | |
8680f6e1 | 10279 | offset_expr.X_add_symbol = symbol_temp_new_now (); |
252b5132 RH |
10280 | offset_expr.X_add_number = 0; |
10281 | ||
10282 | /* Put the floating point number into the section. */ | |
10283 | p = frag_more ((int) length); | |
10284 | memcpy (p, temp, length); | |
10285 | ||
10286 | /* Switch back to the original section. */ | |
10287 | subseg_set (seg, subseg); | |
10288 | } | |
10289 | } | |
10290 | continue; | |
10291 | ||
90ecf173 MR |
10292 | case 'i': /* 16-bit unsigned immediate. */ |
10293 | case 'j': /* 16-bit signed immediate. */ | |
f6688943 | 10294 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 10295 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
10296 | { |
10297 | int more; | |
5e0116d5 RS |
10298 | offsetT minval, maxval; |
10299 | ||
10300 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
10301 | && strcmp (insn->name, insn[1].name) == 0); | |
10302 | ||
10303 | /* If the expression was written as an unsigned number, | |
10304 | only treat it as signed if there are no more | |
10305 | alternatives. */ | |
10306 | if (more | |
10307 | && *args == 'j' | |
10308 | && sizeof (imm_expr.X_add_number) <= 4 | |
10309 | && imm_expr.X_op == O_constant | |
10310 | && imm_expr.X_add_number < 0 | |
10311 | && imm_expr.X_unsigned | |
10312 | && HAVE_64BIT_GPRS) | |
10313 | break; | |
10314 | ||
10315 | /* For compatibility with older assemblers, we accept | |
10316 | 0x8000-0xffff as signed 16-bit numbers when only | |
10317 | signed numbers are allowed. */ | |
10318 | if (*args == 'i') | |
10319 | minval = 0, maxval = 0xffff; | |
10320 | else if (more) | |
10321 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 10322 | else |
5e0116d5 RS |
10323 | minval = -0x8000, maxval = 0xffff; |
10324 | ||
10325 | if (imm_expr.X_op != O_constant | |
10326 | || imm_expr.X_add_number < minval | |
10327 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
10328 | { |
10329 | if (more) | |
10330 | break; | |
2ae7e77b AH |
10331 | if (imm_expr.X_op == O_constant |
10332 | || imm_expr.X_op == O_big) | |
f71d0d44 | 10333 | as_bad (_("Expression out of range")); |
252b5132 RH |
10334 | } |
10335 | } | |
10336 | s = expr_end; | |
10337 | continue; | |
10338 | ||
90ecf173 | 10339 | case 'o': /* 16-bit offset. */ |
4614d845 MR |
10340 | offset_reloc[0] = BFD_RELOC_LO16; |
10341 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
10342 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
10343 | ||
5e0116d5 RS |
10344 | /* Check whether there is only a single bracketed expression |
10345 | left. If so, it must be the base register and the | |
10346 | constant must be zero. */ | |
10347 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
10348 | { | |
10349 | offset_expr.X_op = O_constant; | |
10350 | offset_expr.X_add_number = 0; | |
10351 | continue; | |
10352 | } | |
252b5132 RH |
10353 | |
10354 | /* If this value won't fit into a 16 bit offset, then go | |
10355 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 10356 | code pattern. */ |
5e0116d5 | 10357 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
10358 | && (offset_expr.X_op != O_constant |
10359 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 10360 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
10361 | break; |
10362 | ||
252b5132 RH |
10363 | s = expr_end; |
10364 | continue; | |
10365 | ||
90ecf173 | 10366 | case 'p': /* PC-relative offset. */ |
0b25d3e6 | 10367 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
10368 | my_getExpression (&offset_expr, s); |
10369 | s = expr_end; | |
10370 | continue; | |
10371 | ||
90ecf173 | 10372 | case 'u': /* Upper 16 bits. */ |
5e0116d5 RS |
10373 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
10374 | && imm_expr.X_op == O_constant | |
10375 | && (imm_expr.X_add_number < 0 | |
10376 | || imm_expr.X_add_number >= 0x10000)) | |
88320db2 MR |
10377 | as_bad (_("lui expression (%lu) not in range 0..65535"), |
10378 | (unsigned long) imm_expr.X_add_number); | |
252b5132 RH |
10379 | s = expr_end; |
10380 | continue; | |
10381 | ||
90ecf173 | 10382 | case 'a': /* 26-bit address. */ |
252b5132 RH |
10383 | my_getExpression (&offset_expr, s); |
10384 | s = expr_end; | |
f6688943 | 10385 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
10386 | continue; |
10387 | ||
90ecf173 MR |
10388 | case 'N': /* 3-bit branch condition code. */ |
10389 | case 'M': /* 3-bit compare condition code. */ | |
707bfff6 | 10390 | rtype = RTYPE_CCC; |
90ecf173 | 10391 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) |
707bfff6 TS |
10392 | rtype |= RTYPE_FCC; |
10393 | if (!reg_lookup (&s, rtype, ®no)) | |
252b5132 | 10394 | break; |
90ecf173 MR |
10395 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 |
10396 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
10397 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
30c378fd | 10398 | && (regno & 1) != 0) |
90ecf173 MR |
10399 | as_warn (_("Condition code register should be even for %s, " |
10400 | "was %d"), | |
20203fb9 | 10401 | str, regno); |
90ecf173 MR |
10402 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 |
10403 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
30c378fd | 10404 | && (regno & 3) != 0) |
90ecf173 MR |
10405 | as_warn (_("Condition code register should be 0 or 4 for %s, " |
10406 | "was %d"), | |
20203fb9 | 10407 | str, regno); |
252b5132 | 10408 | if (*args == 'N') |
bf12938e | 10409 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 10410 | else |
bf12938e | 10411 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 10412 | continue; |
252b5132 | 10413 | |
156c2f8b NC |
10414 | case 'H': |
10415 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
10416 | s += 2; | |
3882b010 | 10417 | if (ISDIGIT (*s)) |
156c2f8b NC |
10418 | { |
10419 | c = 0; | |
10420 | do | |
10421 | { | |
10422 | c *= 10; | |
10423 | c += *s - '0'; | |
10424 | ++s; | |
10425 | } | |
3882b010 | 10426 | while (ISDIGIT (*s)); |
156c2f8b NC |
10427 | } |
10428 | else | |
10429 | c = 8; /* Invalid sel value. */ | |
10430 | ||
10431 | if (c > 7) | |
f71d0d44 | 10432 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); |
156c2f8b NC |
10433 | ip->insn_opcode |= c; |
10434 | continue; | |
10435 | ||
60b63b72 RS |
10436 | case 'e': |
10437 | /* Must be at least one digit. */ | |
10438 | my_getExpression (&imm_expr, s); | |
10439 | check_absolute_expr (ip, &imm_expr); | |
10440 | ||
10441 | if ((unsigned long) imm_expr.X_add_number | |
10442 | > (unsigned long) OP_MASK_VECBYTE) | |
10443 | { | |
10444 | as_bad (_("bad byte vector index (%ld)"), | |
10445 | (long) imm_expr.X_add_number); | |
10446 | imm_expr.X_add_number = 0; | |
10447 | } | |
10448 | ||
bf12938e | 10449 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
10450 | imm_expr.X_op = O_absent; |
10451 | s = expr_end; | |
10452 | continue; | |
10453 | ||
10454 | case '%': | |
10455 | my_getExpression (&imm_expr, s); | |
10456 | check_absolute_expr (ip, &imm_expr); | |
10457 | ||
10458 | if ((unsigned long) imm_expr.X_add_number | |
10459 | > (unsigned long) OP_MASK_VECALIGN) | |
10460 | { | |
10461 | as_bad (_("bad byte vector index (%ld)"), | |
10462 | (long) imm_expr.X_add_number); | |
10463 | imm_expr.X_add_number = 0; | |
10464 | } | |
10465 | ||
bf12938e | 10466 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
10467 | imm_expr.X_op = O_absent; |
10468 | s = expr_end; | |
10469 | continue; | |
10470 | ||
252b5132 | 10471 | default: |
f71d0d44 | 10472 | as_bad (_("Bad char = '%c'\n"), *args); |
252b5132 RH |
10473 | internalError (); |
10474 | } | |
10475 | break; | |
10476 | } | |
10477 | /* Args don't match. */ | |
10478 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
10479 | !strcmp (insn->name, insn[1].name)) | |
10480 | { | |
10481 | ++insn; | |
10482 | s = argsStart; | |
f71d0d44 | 10483 | insn_error = _("Illegal operands"); |
252b5132 RH |
10484 | continue; |
10485 | } | |
268f6bed | 10486 | if (save_c) |
570de991 | 10487 | *(--argsStart) = save_c; |
f71d0d44 | 10488 | insn_error = _("Illegal operands"); |
252b5132 RH |
10489 | return; |
10490 | } | |
10491 | } | |
10492 | ||
0499d65b TS |
10493 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
10494 | ||
252b5132 RH |
10495 | /* This routine assembles an instruction into its binary format when |
10496 | assembling for the mips16. As a side effect, it sets one of the | |
10497 | global variables imm_reloc or offset_reloc to the type of | |
10498 | relocation to do if one of the operands is an address expression. | |
10499 | It also sets mips16_small and mips16_ext if the user explicitly | |
10500 | requested a small or extended instruction. */ | |
10501 | ||
10502 | static void | |
17a2f251 | 10503 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
10504 | { |
10505 | char *s; | |
10506 | const char *args; | |
10507 | struct mips_opcode *insn; | |
10508 | char *argsstart; | |
10509 | unsigned int regno; | |
10510 | unsigned int lastregno = 0; | |
10511 | char *s_reset; | |
d6f16593 | 10512 | size_t i; |
252b5132 RH |
10513 | |
10514 | insn_error = NULL; | |
10515 | ||
b34976b6 AM |
10516 | mips16_small = FALSE; |
10517 | mips16_ext = FALSE; | |
252b5132 | 10518 | |
3882b010 | 10519 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
10520 | ; |
10521 | switch (*s) | |
10522 | { | |
10523 | case '\0': | |
10524 | break; | |
10525 | ||
10526 | case ' ': | |
10527 | *s++ = '\0'; | |
10528 | break; | |
10529 | ||
10530 | case '.': | |
10531 | if (s[1] == 't' && s[2] == ' ') | |
10532 | { | |
10533 | *s = '\0'; | |
b34976b6 | 10534 | mips16_small = TRUE; |
252b5132 RH |
10535 | s += 3; |
10536 | break; | |
10537 | } | |
10538 | else if (s[1] == 'e' && s[2] == ' ') | |
10539 | { | |
10540 | *s = '\0'; | |
b34976b6 | 10541 | mips16_ext = TRUE; |
252b5132 RH |
10542 | s += 3; |
10543 | break; | |
10544 | } | |
10545 | /* Fall through. */ | |
10546 | default: | |
10547 | insn_error = _("unknown opcode"); | |
10548 | return; | |
10549 | } | |
10550 | ||
10551 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 10552 | mips16_small = TRUE; |
252b5132 RH |
10553 | |
10554 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
10555 | { | |
10556 | insn_error = _("unrecognized opcode"); | |
10557 | return; | |
10558 | } | |
10559 | ||
10560 | argsstart = s; | |
10561 | for (;;) | |
10562 | { | |
9b3f89ee TS |
10563 | bfd_boolean ok; |
10564 | ||
9c2799c2 | 10565 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 10566 | |
037b32b9 | 10567 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
10568 | if (! ok) |
10569 | { | |
10570 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
10571 | && strcmp (insn->name, insn[1].name) == 0) | |
10572 | { | |
10573 | ++insn; | |
10574 | continue; | |
10575 | } | |
10576 | else | |
10577 | { | |
10578 | if (!insn_error) | |
10579 | { | |
10580 | static char buf[100]; | |
10581 | sprintf (buf, | |
10582 | _("opcode not supported on this processor: %s (%s)"), | |
10583 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
10584 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
10585 | insn_error = buf; | |
10586 | } | |
10587 | return; | |
10588 | } | |
10589 | } | |
10590 | ||
1e915849 | 10591 | create_insn (ip, insn); |
252b5132 | 10592 | imm_expr.X_op = O_absent; |
f6688943 TS |
10593 | imm_reloc[0] = BFD_RELOC_UNUSED; |
10594 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
10595 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 10596 | imm2_expr.X_op = O_absent; |
252b5132 | 10597 | offset_expr.X_op = O_absent; |
f6688943 TS |
10598 | offset_reloc[0] = BFD_RELOC_UNUSED; |
10599 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
10600 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
10601 | for (args = insn->args; 1; ++args) |
10602 | { | |
10603 | int c; | |
10604 | ||
10605 | if (*s == ' ') | |
10606 | ++s; | |
10607 | ||
10608 | /* In this switch statement we call break if we did not find | |
10609 | a match, continue if we did find a match, or return if we | |
10610 | are done. */ | |
10611 | ||
10612 | c = *args; | |
10613 | switch (c) | |
10614 | { | |
10615 | case '\0': | |
10616 | if (*s == '\0') | |
10617 | { | |
10618 | /* Stuff the immediate value in now, if we can. */ | |
10619 | if (imm_expr.X_op == O_constant | |
f6688943 | 10620 | && *imm_reloc > BFD_RELOC_UNUSED |
738e5348 RS |
10621 | && *imm_reloc != BFD_RELOC_MIPS16_GOT16 |
10622 | && *imm_reloc != BFD_RELOC_MIPS16_CALL16 | |
252b5132 RH |
10623 | && insn->pinfo != INSN_MACRO) |
10624 | { | |
d6f16593 MR |
10625 | valueT tmp; |
10626 | ||
10627 | switch (*offset_reloc) | |
10628 | { | |
10629 | case BFD_RELOC_MIPS16_HI16_S: | |
10630 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
10631 | break; | |
10632 | ||
10633 | case BFD_RELOC_MIPS16_HI16: | |
10634 | tmp = imm_expr.X_add_number >> 16; | |
10635 | break; | |
10636 | ||
10637 | case BFD_RELOC_MIPS16_LO16: | |
10638 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
10639 | - 0x8000; | |
10640 | break; | |
10641 | ||
10642 | case BFD_RELOC_UNUSED: | |
10643 | tmp = imm_expr.X_add_number; | |
10644 | break; | |
10645 | ||
10646 | default: | |
10647 | internalError (); | |
10648 | } | |
10649 | *offset_reloc = BFD_RELOC_UNUSED; | |
10650 | ||
c4e7957c | 10651 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 10652 | tmp, TRUE, mips16_small, |
252b5132 RH |
10653 | mips16_ext, &ip->insn_opcode, |
10654 | &ip->use_extend, &ip->extend); | |
10655 | imm_expr.X_op = O_absent; | |
f6688943 | 10656 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
10657 | } |
10658 | ||
10659 | return; | |
10660 | } | |
10661 | break; | |
10662 | ||
10663 | case ',': | |
10664 | if (*s++ == c) | |
10665 | continue; | |
10666 | s--; | |
10667 | switch (*++args) | |
10668 | { | |
10669 | case 'v': | |
bf12938e | 10670 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
10671 | continue; |
10672 | case 'w': | |
bf12938e | 10673 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
10674 | continue; |
10675 | } | |
10676 | break; | |
10677 | ||
10678 | case '(': | |
10679 | case ')': | |
10680 | if (*s++ == c) | |
10681 | continue; | |
10682 | break; | |
10683 | ||
10684 | case 'v': | |
10685 | case 'w': | |
10686 | if (s[0] != '$') | |
10687 | { | |
10688 | if (c == 'v') | |
bf12938e | 10689 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 10690 | else |
bf12938e | 10691 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
10692 | ++args; |
10693 | continue; | |
10694 | } | |
10695 | /* Fall through. */ | |
10696 | case 'x': | |
10697 | case 'y': | |
10698 | case 'z': | |
10699 | case 'Z': | |
10700 | case '0': | |
10701 | case 'S': | |
10702 | case 'R': | |
10703 | case 'X': | |
10704 | case 'Y': | |
707bfff6 TS |
10705 | s_reset = s; |
10706 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 10707 | { |
707bfff6 | 10708 | if (c == 'v' || c == 'w') |
85b51719 | 10709 | { |
707bfff6 | 10710 | if (c == 'v') |
a9e24354 | 10711 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 10712 | else |
a9e24354 | 10713 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
10714 | ++args; |
10715 | continue; | |
85b51719 | 10716 | } |
707bfff6 | 10717 | break; |
252b5132 RH |
10718 | } |
10719 | ||
10720 | if (*s == ' ') | |
10721 | ++s; | |
10722 | if (args[1] != *s) | |
10723 | { | |
10724 | if (c == 'v' || c == 'w') | |
10725 | { | |
10726 | regno = mips16_to_32_reg_map[lastregno]; | |
10727 | s = s_reset; | |
f9419b05 | 10728 | ++args; |
252b5132 RH |
10729 | } |
10730 | } | |
10731 | ||
10732 | switch (c) | |
10733 | { | |
10734 | case 'x': | |
10735 | case 'y': | |
10736 | case 'z': | |
10737 | case 'v': | |
10738 | case 'w': | |
10739 | case 'Z': | |
10740 | regno = mips32_to_16_reg_map[regno]; | |
10741 | break; | |
10742 | ||
10743 | case '0': | |
10744 | if (regno != 0) | |
10745 | regno = ILLEGAL_REG; | |
10746 | break; | |
10747 | ||
10748 | case 'S': | |
10749 | if (regno != SP) | |
10750 | regno = ILLEGAL_REG; | |
10751 | break; | |
10752 | ||
10753 | case 'R': | |
10754 | if (regno != RA) | |
10755 | regno = ILLEGAL_REG; | |
10756 | break; | |
10757 | ||
10758 | case 'X': | |
10759 | case 'Y': | |
741fe287 MR |
10760 | if (regno == AT && mips_opts.at) |
10761 | { | |
10762 | if (mips_opts.at == ATREG) | |
10763 | as_warn (_("used $at without \".set noat\"")); | |
10764 | else | |
10765 | as_warn (_("used $%u with \".set at=$%u\""), | |
10766 | regno, mips_opts.at); | |
10767 | } | |
252b5132 RH |
10768 | break; |
10769 | ||
10770 | default: | |
10771 | internalError (); | |
10772 | } | |
10773 | ||
10774 | if (regno == ILLEGAL_REG) | |
10775 | break; | |
10776 | ||
10777 | switch (c) | |
10778 | { | |
10779 | case 'x': | |
10780 | case 'v': | |
bf12938e | 10781 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
10782 | break; |
10783 | case 'y': | |
10784 | case 'w': | |
bf12938e | 10785 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
10786 | break; |
10787 | case 'z': | |
bf12938e | 10788 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
10789 | break; |
10790 | case 'Z': | |
bf12938e | 10791 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
10792 | case '0': |
10793 | case 'S': | |
10794 | case 'R': | |
10795 | break; | |
10796 | case 'X': | |
bf12938e | 10797 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
10798 | break; |
10799 | case 'Y': | |
10800 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 10801 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
10802 | break; |
10803 | default: | |
10804 | internalError (); | |
10805 | } | |
10806 | ||
10807 | lastregno = regno; | |
10808 | continue; | |
10809 | ||
10810 | case 'P': | |
10811 | if (strncmp (s, "$pc", 3) == 0) | |
10812 | { | |
10813 | s += 3; | |
10814 | continue; | |
10815 | } | |
10816 | break; | |
10817 | ||
252b5132 RH |
10818 | case '5': |
10819 | case 'H': | |
10820 | case 'W': | |
10821 | case 'D': | |
10822 | case 'j': | |
252b5132 RH |
10823 | case 'V': |
10824 | case 'C': | |
10825 | case 'U': | |
10826 | case 'k': | |
10827 | case 'K': | |
d6f16593 MR |
10828 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
10829 | if (i > 0) | |
252b5132 | 10830 | { |
d6f16593 | 10831 | if (imm_expr.X_op != O_constant) |
252b5132 | 10832 | { |
b34976b6 | 10833 | mips16_ext = TRUE; |
b34976b6 | 10834 | ip->use_extend = TRUE; |
252b5132 | 10835 | ip->extend = 0; |
252b5132 | 10836 | } |
d6f16593 MR |
10837 | else |
10838 | { | |
10839 | /* We need to relax this instruction. */ | |
10840 | *offset_reloc = *imm_reloc; | |
10841 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
10842 | } | |
10843 | s = expr_end; | |
10844 | continue; | |
252b5132 | 10845 | } |
d6f16593 MR |
10846 | *imm_reloc = BFD_RELOC_UNUSED; |
10847 | /* Fall through. */ | |
10848 | case '<': | |
10849 | case '>': | |
10850 | case '[': | |
10851 | case ']': | |
10852 | case '4': | |
10853 | case '8': | |
10854 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
10855 | if (imm_expr.X_op == O_register) |
10856 | { | |
10857 | /* What we thought was an expression turned out to | |
10858 | be a register. */ | |
10859 | ||
10860 | if (s[0] == '(' && args[1] == '(') | |
10861 | { | |
10862 | /* It looks like the expression was omitted | |
10863 | before a register indirection, which means | |
10864 | that the expression is implicitly zero. We | |
10865 | still set up imm_expr, so that we handle | |
10866 | explicit extensions correctly. */ | |
10867 | imm_expr.X_op = O_constant; | |
10868 | imm_expr.X_add_number = 0; | |
f6688943 | 10869 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10870 | continue; |
10871 | } | |
10872 | ||
10873 | break; | |
10874 | } | |
10875 | ||
10876 | /* We need to relax this instruction. */ | |
f6688943 | 10877 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10878 | s = expr_end; |
10879 | continue; | |
10880 | ||
10881 | case 'p': | |
10882 | case 'q': | |
10883 | case 'A': | |
10884 | case 'B': | |
10885 | case 'E': | |
10886 | /* We use offset_reloc rather than imm_reloc for the PC | |
10887 | relative operands. This lets macros with both | |
10888 | immediate and address operands work correctly. */ | |
10889 | my_getExpression (&offset_expr, s); | |
10890 | ||
10891 | if (offset_expr.X_op == O_register) | |
10892 | break; | |
10893 | ||
10894 | /* We need to relax this instruction. */ | |
f6688943 | 10895 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10896 | s = expr_end; |
10897 | continue; | |
10898 | ||
10899 | case '6': /* break code */ | |
10900 | my_getExpression (&imm_expr, s); | |
10901 | check_absolute_expr (ip, &imm_expr); | |
10902 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
10903 | as_warn (_("Invalid value for `%s' (%lu)"), |
10904 | ip->insn_mo->name, | |
10905 | (unsigned long) imm_expr.X_add_number); | |
10906 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
10907 | imm_expr.X_op = O_absent; |
10908 | s = expr_end; | |
10909 | continue; | |
10910 | ||
10911 | case 'a': /* 26 bit address */ | |
10912 | my_getExpression (&offset_expr, s); | |
10913 | s = expr_end; | |
f6688943 | 10914 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
10915 | ip->insn_opcode <<= 16; |
10916 | continue; | |
10917 | ||
10918 | case 'l': /* register list for entry macro */ | |
10919 | case 'L': /* register list for exit macro */ | |
10920 | { | |
10921 | int mask; | |
10922 | ||
10923 | if (c == 'l') | |
10924 | mask = 0; | |
10925 | else | |
10926 | mask = 7 << 3; | |
10927 | while (*s != '\0') | |
10928 | { | |
707bfff6 | 10929 | unsigned int freg, reg1, reg2; |
252b5132 RH |
10930 | |
10931 | while (*s == ' ' || *s == ',') | |
10932 | ++s; | |
707bfff6 | 10933 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 10934 | freg = 0; |
707bfff6 TS |
10935 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
10936 | freg = 1; | |
252b5132 RH |
10937 | else |
10938 | { | |
707bfff6 TS |
10939 | as_bad (_("can't parse register list")); |
10940 | break; | |
252b5132 RH |
10941 | } |
10942 | if (*s == ' ') | |
10943 | ++s; | |
10944 | if (*s != '-') | |
10945 | reg2 = reg1; | |
10946 | else | |
10947 | { | |
10948 | ++s; | |
707bfff6 TS |
10949 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
10950 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 10951 | { |
707bfff6 TS |
10952 | as_bad (_("invalid register list")); |
10953 | break; | |
252b5132 RH |
10954 | } |
10955 | } | |
10956 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
10957 | { | |
10958 | mask &= ~ (7 << 3); | |
10959 | mask |= 5 << 3; | |
10960 | } | |
10961 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
10962 | { | |
10963 | mask &= ~ (7 << 3); | |
10964 | mask |= 6 << 3; | |
10965 | } | |
10966 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
10967 | mask |= (reg2 - 3) << 3; | |
10968 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
10969 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 10970 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
10971 | mask |= 1; |
10972 | else | |
10973 | { | |
10974 | as_bad (_("invalid register list")); | |
10975 | break; | |
10976 | } | |
10977 | } | |
10978 | /* The mask is filled in in the opcode table for the | |
10979 | benefit of the disassembler. We remove it before | |
10980 | applying the actual mask. */ | |
10981 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
10982 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
10983 | } | |
10984 | continue; | |
10985 | ||
0499d65b TS |
10986 | case 'm': /* Register list for save insn. */ |
10987 | case 'M': /* Register list for restore insn. */ | |
10988 | { | |
10989 | int opcode = 0; | |
10990 | int framesz = 0, seen_framesz = 0; | |
91d6fa6a | 10991 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
10992 | |
10993 | while (*s != '\0') | |
10994 | { | |
10995 | unsigned int reg1, reg2; | |
10996 | ||
10997 | SKIP_SPACE_TABS (s); | |
10998 | while (*s == ',') | |
10999 | ++s; | |
11000 | SKIP_SPACE_TABS (s); | |
11001 | ||
11002 | my_getExpression (&imm_expr, s); | |
11003 | if (imm_expr.X_op == O_constant) | |
11004 | { | |
11005 | /* Handle the frame size. */ | |
11006 | if (seen_framesz) | |
11007 | { | |
11008 | as_bad (_("more than one frame size in list")); | |
11009 | break; | |
11010 | } | |
11011 | seen_framesz = 1; | |
11012 | framesz = imm_expr.X_add_number; | |
11013 | imm_expr.X_op = O_absent; | |
11014 | s = expr_end; | |
11015 | continue; | |
11016 | } | |
11017 | ||
707bfff6 | 11018 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
11019 | { |
11020 | as_bad (_("can't parse register list")); | |
11021 | break; | |
11022 | } | |
0499d65b | 11023 | |
707bfff6 TS |
11024 | while (*s == ' ') |
11025 | ++s; | |
11026 | ||
0499d65b TS |
11027 | if (*s != '-') |
11028 | reg2 = reg1; | |
11029 | else | |
11030 | { | |
11031 | ++s; | |
707bfff6 TS |
11032 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
11033 | || reg2 < reg1) | |
0499d65b TS |
11034 | { |
11035 | as_bad (_("can't parse register list")); | |
11036 | break; | |
11037 | } | |
0499d65b TS |
11038 | } |
11039 | ||
11040 | while (reg1 <= reg2) | |
11041 | { | |
11042 | if (reg1 >= 4 && reg1 <= 7) | |
11043 | { | |
3a93f742 | 11044 | if (!seen_framesz) |
0499d65b | 11045 | /* args $a0-$a3 */ |
91d6fa6a | 11046 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
11047 | else |
11048 | /* statics $a0-$a3 */ | |
11049 | statics |= 1 << (reg1 - 4); | |
11050 | } | |
11051 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
11052 | { | |
11053 | /* $s0-$s8 */ | |
11054 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
11055 | } | |
11056 | else if (reg1 == 31) | |
11057 | { | |
11058 | /* Add $ra to insn. */ | |
11059 | opcode |= 0x40; | |
11060 | } | |
11061 | else | |
11062 | { | |
11063 | as_bad (_("unexpected register in list")); | |
11064 | break; | |
11065 | } | |
11066 | if (++reg1 == 24) | |
11067 | reg1 = 30; | |
11068 | } | |
11069 | } | |
11070 | ||
11071 | /* Encode args/statics combination. */ | |
91d6fa6a | 11072 | if (nargs & statics) |
0499d65b | 11073 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 11074 | else if (nargs == 0xf) |
0499d65b TS |
11075 | /* All $a0-$a3 are args. */ |
11076 | opcode |= MIPS16_ALL_ARGS << 16; | |
11077 | else if (statics == 0xf) | |
11078 | /* All $a0-$a3 are statics. */ | |
11079 | opcode |= MIPS16_ALL_STATICS << 16; | |
11080 | else | |
11081 | { | |
11082 | int narg = 0, nstat = 0; | |
11083 | ||
11084 | /* Count arg registers. */ | |
91d6fa6a | 11085 | while (nargs & 0x1) |
0499d65b | 11086 | { |
91d6fa6a | 11087 | nargs >>= 1; |
0499d65b TS |
11088 | narg++; |
11089 | } | |
91d6fa6a | 11090 | if (nargs != 0) |
0499d65b TS |
11091 | as_bad (_("invalid arg register list")); |
11092 | ||
11093 | /* Count static registers. */ | |
11094 | while (statics & 0x8) | |
11095 | { | |
11096 | statics = (statics << 1) & 0xf; | |
11097 | nstat++; | |
11098 | } | |
11099 | if (statics != 0) | |
11100 | as_bad (_("invalid static register list")); | |
11101 | ||
11102 | /* Encode args/statics. */ | |
11103 | opcode |= ((narg << 2) | nstat) << 16; | |
11104 | } | |
11105 | ||
11106 | /* Encode $s0/$s1. */ | |
11107 | if (sregs & (1 << 0)) /* $s0 */ | |
11108 | opcode |= 0x20; | |
11109 | if (sregs & (1 << 1)) /* $s1 */ | |
11110 | opcode |= 0x10; | |
11111 | sregs >>= 2; | |
11112 | ||
11113 | if (sregs != 0) | |
11114 | { | |
11115 | /* Count regs $s2-$s8. */ | |
11116 | int nsreg = 0; | |
11117 | while (sregs & 1) | |
11118 | { | |
11119 | sregs >>= 1; | |
11120 | nsreg++; | |
11121 | } | |
11122 | if (sregs != 0) | |
11123 | as_bad (_("invalid static register list")); | |
11124 | /* Encode $s2-$s8. */ | |
11125 | opcode |= nsreg << 24; | |
11126 | } | |
11127 | ||
11128 | /* Encode frame size. */ | |
11129 | if (!seen_framesz) | |
11130 | as_bad (_("missing frame size")); | |
11131 | else if ((framesz & 7) != 0 || framesz < 0 | |
11132 | || framesz > 0xff * 8) | |
11133 | as_bad (_("invalid frame size")); | |
11134 | else if (framesz != 128 || (opcode >> 16) != 0) | |
11135 | { | |
11136 | framesz /= 8; | |
11137 | opcode |= (((framesz & 0xf0) << 16) | |
11138 | | (framesz & 0x0f)); | |
11139 | } | |
11140 | ||
11141 | /* Finally build the instruction. */ | |
11142 | if ((opcode >> 16) != 0 || framesz == 0) | |
11143 | { | |
11144 | ip->use_extend = TRUE; | |
11145 | ip->extend = opcode >> 16; | |
11146 | } | |
11147 | ip->insn_opcode |= opcode & 0x7f; | |
11148 | } | |
11149 | continue; | |
11150 | ||
252b5132 RH |
11151 | case 'e': /* extend code */ |
11152 | my_getExpression (&imm_expr, s); | |
11153 | check_absolute_expr (ip, &imm_expr); | |
11154 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
11155 | { | |
11156 | as_warn (_("Invalid value for `%s' (%lu)"), | |
11157 | ip->insn_mo->name, | |
11158 | (unsigned long) imm_expr.X_add_number); | |
11159 | imm_expr.X_add_number &= 0x7ff; | |
11160 | } | |
11161 | ip->insn_opcode |= imm_expr.X_add_number; | |
11162 | imm_expr.X_op = O_absent; | |
11163 | s = expr_end; | |
11164 | continue; | |
11165 | ||
11166 | default: | |
11167 | internalError (); | |
11168 | } | |
11169 | break; | |
11170 | } | |
11171 | ||
11172 | /* Args don't match. */ | |
11173 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
11174 | strcmp (insn->name, insn[1].name) == 0) | |
11175 | { | |
11176 | ++insn; | |
11177 | s = argsstart; | |
11178 | continue; | |
11179 | } | |
11180 | ||
11181 | insn_error = _("illegal operands"); | |
11182 | ||
11183 | return; | |
11184 | } | |
11185 | } | |
11186 | ||
11187 | /* This structure holds information we know about a mips16 immediate | |
11188 | argument type. */ | |
11189 | ||
e972090a NC |
11190 | struct mips16_immed_operand |
11191 | { | |
252b5132 RH |
11192 | /* The type code used in the argument string in the opcode table. */ |
11193 | int type; | |
11194 | /* The number of bits in the short form of the opcode. */ | |
11195 | int nbits; | |
11196 | /* The number of bits in the extended form of the opcode. */ | |
11197 | int extbits; | |
11198 | /* The amount by which the short form is shifted when it is used; | |
11199 | for example, the sw instruction has a shift count of 2. */ | |
11200 | int shift; | |
11201 | /* The amount by which the short form is shifted when it is stored | |
11202 | into the instruction code. */ | |
11203 | int op_shift; | |
11204 | /* Non-zero if the short form is unsigned. */ | |
11205 | int unsp; | |
11206 | /* Non-zero if the extended form is unsigned. */ | |
11207 | int extu; | |
11208 | /* Non-zero if the value is PC relative. */ | |
11209 | int pcrel; | |
11210 | }; | |
11211 | ||
11212 | /* The mips16 immediate operand types. */ | |
11213 | ||
11214 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
11215 | { | |
11216 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
11217 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
11218 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
11219 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
11220 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
11221 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
11222 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
11223 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
11224 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
11225 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
11226 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
11227 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
11228 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
11229 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
11230 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
11231 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
11232 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
11233 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
11234 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
11235 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
11236 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
11237 | }; | |
11238 | ||
11239 | #define MIPS16_NUM_IMMED \ | |
11240 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
11241 | ||
11242 | /* Handle a mips16 instruction with an immediate value. This or's the | |
11243 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
11244 | whether an extended value is needed; if one is needed, it sets | |
11245 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
11246 | If SMALL is true, an unextended opcode was explicitly requested. | |
11247 | If EXT is true, an extended opcode was explicitly requested. If | |
11248 | WARN is true, warn if EXT does not match reality. */ | |
11249 | ||
11250 | static void | |
17a2f251 TS |
11251 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
11252 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
11253 | unsigned long *insn, bfd_boolean *use_extend, | |
11254 | unsigned short *extend) | |
252b5132 | 11255 | { |
3994f87e | 11256 | const struct mips16_immed_operand *op; |
252b5132 | 11257 | int mintiny, maxtiny; |
b34976b6 | 11258 | bfd_boolean needext; |
252b5132 RH |
11259 | |
11260 | op = mips16_immed_operands; | |
11261 | while (op->type != type) | |
11262 | { | |
11263 | ++op; | |
9c2799c2 | 11264 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
11265 | } |
11266 | ||
11267 | if (op->unsp) | |
11268 | { | |
11269 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
11270 | { | |
11271 | mintiny = 1; | |
11272 | maxtiny = 1 << op->nbits; | |
11273 | } | |
11274 | else | |
11275 | { | |
11276 | mintiny = 0; | |
11277 | maxtiny = (1 << op->nbits) - 1; | |
11278 | } | |
11279 | } | |
11280 | else | |
11281 | { | |
11282 | mintiny = - (1 << (op->nbits - 1)); | |
11283 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
11284 | } | |
11285 | ||
11286 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
11287 | if (type == 'p' || type == 'q') | |
11288 | val /= 2; | |
11289 | ||
11290 | if ((val & ((1 << op->shift) - 1)) != 0 | |
11291 | || val < (mintiny << op->shift) | |
11292 | || val > (maxtiny << op->shift)) | |
b34976b6 | 11293 | needext = TRUE; |
252b5132 | 11294 | else |
b34976b6 | 11295 | needext = FALSE; |
252b5132 RH |
11296 | |
11297 | if (warn && ext && ! needext) | |
beae10d5 KH |
11298 | as_warn_where (file, line, |
11299 | _("extended operand requested but not required")); | |
252b5132 RH |
11300 | if (small && needext) |
11301 | as_bad_where (file, line, _("invalid unextended operand value")); | |
11302 | ||
11303 | if (small || (! ext && ! needext)) | |
11304 | { | |
11305 | int insnval; | |
11306 | ||
b34976b6 | 11307 | *use_extend = FALSE; |
252b5132 RH |
11308 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
11309 | insnval <<= op->op_shift; | |
11310 | *insn |= insnval; | |
11311 | } | |
11312 | else | |
11313 | { | |
11314 | long minext, maxext; | |
11315 | int extval; | |
11316 | ||
11317 | if (op->extu) | |
11318 | { | |
11319 | minext = 0; | |
11320 | maxext = (1 << op->extbits) - 1; | |
11321 | } | |
11322 | else | |
11323 | { | |
11324 | minext = - (1 << (op->extbits - 1)); | |
11325 | maxext = (1 << (op->extbits - 1)) - 1; | |
11326 | } | |
11327 | if (val < minext || val > maxext) | |
11328 | as_bad_where (file, line, | |
11329 | _("operand value out of range for instruction")); | |
11330 | ||
b34976b6 | 11331 | *use_extend = TRUE; |
252b5132 RH |
11332 | if (op->extbits == 16) |
11333 | { | |
11334 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
11335 | val &= 0x1f; | |
11336 | } | |
11337 | else if (op->extbits == 15) | |
11338 | { | |
11339 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
11340 | val &= 0xf; | |
11341 | } | |
11342 | else | |
11343 | { | |
11344 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
11345 | val = 0; | |
11346 | } | |
11347 | ||
11348 | *extend = (unsigned short) extval; | |
11349 | *insn |= val; | |
11350 | } | |
11351 | } | |
11352 | \f | |
d6f16593 | 11353 | struct percent_op_match |
ad8d3bb3 | 11354 | { |
5e0116d5 RS |
11355 | const char *str; |
11356 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
11357 | }; |
11358 | ||
11359 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 11360 | { |
5e0116d5 | 11361 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 11362 | #ifdef OBJ_ELF |
5e0116d5 RS |
11363 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
11364 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
11365 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
11366 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
11367 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
11368 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
11369 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
11370 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
11371 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
11372 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
11373 | {"%half", BFD_RELOC_16}, | |
11374 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
11375 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
11376 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
11377 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
11378 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
11379 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
11380 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
11381 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
11382 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
11383 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 11384 | #endif |
5e0116d5 | 11385 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
11386 | }; |
11387 | ||
d6f16593 MR |
11388 | static const struct percent_op_match mips16_percent_op[] = |
11389 | { | |
11390 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
11391 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
11392 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
11393 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d6f16593 MR |
11394 | {"%hi", BFD_RELOC_MIPS16_HI16_S} |
11395 | }; | |
11396 | ||
252b5132 | 11397 | |
5e0116d5 RS |
11398 | /* Return true if *STR points to a relocation operator. When returning true, |
11399 | move *STR over the operator and store its relocation code in *RELOC. | |
11400 | Leave both *STR and *RELOC alone when returning false. */ | |
11401 | ||
11402 | static bfd_boolean | |
17a2f251 | 11403 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 11404 | { |
d6f16593 MR |
11405 | const struct percent_op_match *percent_op; |
11406 | size_t limit, i; | |
11407 | ||
11408 | if (mips_opts.mips16) | |
11409 | { | |
11410 | percent_op = mips16_percent_op; | |
11411 | limit = ARRAY_SIZE (mips16_percent_op); | |
11412 | } | |
11413 | else | |
11414 | { | |
11415 | percent_op = mips_percent_op; | |
11416 | limit = ARRAY_SIZE (mips_percent_op); | |
11417 | } | |
76b3015f | 11418 | |
d6f16593 | 11419 | for (i = 0; i < limit; i++) |
5e0116d5 | 11420 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 11421 | { |
3f98094e DJ |
11422 | int len = strlen (percent_op[i].str); |
11423 | ||
11424 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
11425 | continue; | |
11426 | ||
5e0116d5 RS |
11427 | *str += strlen (percent_op[i].str); |
11428 | *reloc = percent_op[i].reloc; | |
394f9b3a | 11429 | |
5e0116d5 RS |
11430 | /* Check whether the output BFD supports this relocation. |
11431 | If not, issue an error and fall back on something safe. */ | |
11432 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 11433 | { |
20203fb9 | 11434 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 11435 | percent_op[i].str); |
01a3f561 | 11436 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 11437 | } |
5e0116d5 | 11438 | return TRUE; |
394f9b3a | 11439 | } |
5e0116d5 | 11440 | return FALSE; |
394f9b3a | 11441 | } |
ad8d3bb3 | 11442 | |
ad8d3bb3 | 11443 | |
5e0116d5 RS |
11444 | /* Parse string STR as a 16-bit relocatable operand. Store the |
11445 | expression in *EP and the relocations in the array starting | |
11446 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 11447 | |
01a3f561 | 11448 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 11449 | |
5e0116d5 | 11450 | static size_t |
17a2f251 TS |
11451 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
11452 | char *str) | |
ad8d3bb3 | 11453 | { |
5e0116d5 RS |
11454 | bfd_reloc_code_real_type reversed_reloc[3]; |
11455 | size_t reloc_index, i; | |
09b8f35a RS |
11456 | int crux_depth, str_depth; |
11457 | char *crux; | |
5e0116d5 RS |
11458 | |
11459 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
11460 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
11461 | of the main expression and with CRUX_DEPTH containing the number | |
11462 | of open brackets at that point. */ | |
11463 | reloc_index = -1; | |
11464 | str_depth = 0; | |
11465 | do | |
fb1b3232 | 11466 | { |
09b8f35a RS |
11467 | reloc_index++; |
11468 | crux = str; | |
11469 | crux_depth = str_depth; | |
11470 | ||
11471 | /* Skip over whitespace and brackets, keeping count of the number | |
11472 | of brackets. */ | |
11473 | while (*str == ' ' || *str == '\t' || *str == '(') | |
11474 | if (*str++ == '(') | |
11475 | str_depth++; | |
5e0116d5 | 11476 | } |
09b8f35a RS |
11477 | while (*str == '%' |
11478 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
11479 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 11480 | |
09b8f35a | 11481 | my_getExpression (ep, crux); |
5e0116d5 | 11482 | str = expr_end; |
394f9b3a | 11483 | |
5e0116d5 | 11484 | /* Match every open bracket. */ |
09b8f35a | 11485 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 11486 | if (*str++ == ')') |
09b8f35a | 11487 | crux_depth--; |
394f9b3a | 11488 | |
09b8f35a | 11489 | if (crux_depth > 0) |
20203fb9 | 11490 | as_bad (_("unclosed '('")); |
394f9b3a | 11491 | |
5e0116d5 | 11492 | expr_end = str; |
252b5132 | 11493 | |
01a3f561 | 11494 | if (reloc_index != 0) |
64bdfcaf RS |
11495 | { |
11496 | prev_reloc_op_frag = frag_now; | |
11497 | for (i = 0; i < reloc_index; i++) | |
11498 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
11499 | } | |
fb1b3232 | 11500 | |
5e0116d5 | 11501 | return reloc_index; |
252b5132 RH |
11502 | } |
11503 | ||
11504 | static void | |
17a2f251 | 11505 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
11506 | { |
11507 | char *save_in; | |
11508 | ||
11509 | save_in = input_line_pointer; | |
11510 | input_line_pointer = str; | |
11511 | expression (ep); | |
11512 | expr_end = input_line_pointer; | |
11513 | input_line_pointer = save_in; | |
252b5132 RH |
11514 | } |
11515 | ||
252b5132 | 11516 | char * |
17a2f251 | 11517 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 11518 | { |
499ac353 | 11519 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
11520 | } |
11521 | ||
11522 | void | |
17a2f251 | 11523 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
11524 | { |
11525 | if (target_big_endian) | |
11526 | number_to_chars_bigendian (buf, val, n); | |
11527 | else | |
11528 | number_to_chars_littleendian (buf, val, n); | |
11529 | } | |
11530 | \f | |
ae948b86 | 11531 | #ifdef OBJ_ELF |
e013f690 TS |
11532 | static int support_64bit_objects(void) |
11533 | { | |
11534 | const char **list, **l; | |
aa3d8fdf | 11535 | int yes; |
e013f690 TS |
11536 | |
11537 | list = bfd_target_list (); | |
11538 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
11539 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
11540 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 11541 | break; |
aa3d8fdf | 11542 | yes = (*l != NULL); |
e013f690 | 11543 | free (list); |
aa3d8fdf | 11544 | return yes; |
e013f690 | 11545 | } |
ae948b86 | 11546 | #endif /* OBJ_ELF */ |
e013f690 | 11547 | |
78849248 | 11548 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 11549 | |
23fce1e3 NC |
11550 | enum options |
11551 | { | |
11552 | OPTION_MARCH = OPTION_MD_BASE, | |
11553 | OPTION_MTUNE, | |
11554 | OPTION_MIPS1, | |
11555 | OPTION_MIPS2, | |
11556 | OPTION_MIPS3, | |
11557 | OPTION_MIPS4, | |
11558 | OPTION_MIPS5, | |
11559 | OPTION_MIPS32, | |
11560 | OPTION_MIPS64, | |
11561 | OPTION_MIPS32R2, | |
11562 | OPTION_MIPS64R2, | |
11563 | OPTION_MIPS16, | |
11564 | OPTION_NO_MIPS16, | |
11565 | OPTION_MIPS3D, | |
11566 | OPTION_NO_MIPS3D, | |
11567 | OPTION_MDMX, | |
11568 | OPTION_NO_MDMX, | |
11569 | OPTION_DSP, | |
11570 | OPTION_NO_DSP, | |
11571 | OPTION_MT, | |
11572 | OPTION_NO_MT, | |
11573 | OPTION_SMARTMIPS, | |
11574 | OPTION_NO_SMARTMIPS, | |
11575 | OPTION_DSPR2, | |
11576 | OPTION_NO_DSPR2, | |
11577 | OPTION_COMPAT_ARCH_BASE, | |
11578 | OPTION_M4650, | |
11579 | OPTION_NO_M4650, | |
11580 | OPTION_M4010, | |
11581 | OPTION_NO_M4010, | |
11582 | OPTION_M4100, | |
11583 | OPTION_NO_M4100, | |
11584 | OPTION_M3900, | |
11585 | OPTION_NO_M3900, | |
11586 | OPTION_M7000_HILO_FIX, | |
6a32d874 CM |
11587 | OPTION_MNO_7000_HILO_FIX, |
11588 | OPTION_FIX_24K, | |
11589 | OPTION_NO_FIX_24K, | |
c67a084a NC |
11590 | OPTION_FIX_LOONGSON2F_JUMP, |
11591 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
11592 | OPTION_FIX_LOONGSON2F_NOP, | |
11593 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
23fce1e3 NC |
11594 | OPTION_FIX_VR4120, |
11595 | OPTION_NO_FIX_VR4120, | |
11596 | OPTION_FIX_VR4130, | |
11597 | OPTION_NO_FIX_VR4130, | |
d954098f DD |
11598 | OPTION_FIX_CN63XXP1, |
11599 | OPTION_NO_FIX_CN63XXP1, | |
23fce1e3 NC |
11600 | OPTION_TRAP, |
11601 | OPTION_BREAK, | |
11602 | OPTION_EB, | |
11603 | OPTION_EL, | |
11604 | OPTION_FP32, | |
11605 | OPTION_GP32, | |
11606 | OPTION_CONSTRUCT_FLOATS, | |
11607 | OPTION_NO_CONSTRUCT_FLOATS, | |
11608 | OPTION_FP64, | |
11609 | OPTION_GP64, | |
11610 | OPTION_RELAX_BRANCH, | |
11611 | OPTION_NO_RELAX_BRANCH, | |
11612 | OPTION_MSHARED, | |
11613 | OPTION_MNO_SHARED, | |
11614 | OPTION_MSYM32, | |
11615 | OPTION_MNO_SYM32, | |
11616 | OPTION_SOFT_FLOAT, | |
11617 | OPTION_HARD_FLOAT, | |
11618 | OPTION_SINGLE_FLOAT, | |
11619 | OPTION_DOUBLE_FLOAT, | |
11620 | OPTION_32, | |
11621 | #ifdef OBJ_ELF | |
11622 | OPTION_CALL_SHARED, | |
11623 | OPTION_CALL_NONPIC, | |
11624 | OPTION_NON_SHARED, | |
11625 | OPTION_XGOT, | |
11626 | OPTION_MABI, | |
11627 | OPTION_N32, | |
11628 | OPTION_64, | |
11629 | OPTION_MDEBUG, | |
11630 | OPTION_NO_MDEBUG, | |
11631 | OPTION_PDR, | |
11632 | OPTION_NO_PDR, | |
11633 | OPTION_MVXWORKS_PIC, | |
11634 | #endif /* OBJ_ELF */ | |
11635 | OPTION_END_OF_ENUM | |
11636 | }; | |
11637 | ||
e972090a NC |
11638 | struct option md_longopts[] = |
11639 | { | |
f9b4148d | 11640 | /* Options which specify architecture. */ |
f9b4148d | 11641 | {"march", required_argument, NULL, OPTION_MARCH}, |
f9b4148d | 11642 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
252b5132 RH |
11643 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
11644 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
252b5132 | 11645 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
252b5132 | 11646 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
252b5132 | 11647 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
ae948b86 | 11648 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
ae948b86 | 11649 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
ae948b86 | 11650 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d | 11651 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
5f74bc13 | 11652 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
f9b4148d CD |
11653 | |
11654 | /* Options which specify Application Specific Extensions (ASEs). */ | |
f9b4148d | 11655 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
f9b4148d | 11656 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f9b4148d | 11657 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
f9b4148d | 11658 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
f9b4148d | 11659 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
f9b4148d | 11660 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
74cd071d | 11661 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
74cd071d | 11662 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
ef2e4d86 | 11663 | {"mmt", no_argument, NULL, OPTION_MT}, |
ef2e4d86 | 11664 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
e16bfa71 | 11665 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
e16bfa71 | 11666 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
8b082fb1 | 11667 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
8b082fb1 | 11668 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
f9b4148d CD |
11669 | |
11670 | /* Old-style architecture options. Don't add more of these. */ | |
f9b4148d | 11671 | {"m4650", no_argument, NULL, OPTION_M4650}, |
f9b4148d | 11672 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
f9b4148d | 11673 | {"m4010", no_argument, NULL, OPTION_M4010}, |
f9b4148d | 11674 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
f9b4148d | 11675 | {"m4100", no_argument, NULL, OPTION_M4100}, |
f9b4148d | 11676 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
f9b4148d | 11677 | {"m3900", no_argument, NULL, OPTION_M3900}, |
f9b4148d CD |
11678 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
11679 | ||
11680 | /* Options which enable bug fixes. */ | |
f9b4148d | 11681 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
f9b4148d CD |
11682 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
11683 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
c67a084a NC |
11684 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
11685 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
11686 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
11687 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
d766e8ec RS |
11688 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
11689 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
11690 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
11691 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
6a32d874 CM |
11692 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
11693 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
d954098f DD |
11694 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
11695 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
f9b4148d CD |
11696 | |
11697 | /* Miscellaneous options. */ | |
252b5132 RH |
11698 | {"trap", no_argument, NULL, OPTION_TRAP}, |
11699 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
252b5132 RH |
11700 | {"break", no_argument, NULL, OPTION_BREAK}, |
11701 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
252b5132 | 11702 | {"EB", no_argument, NULL, OPTION_EB}, |
252b5132 | 11703 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 11704 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
c97ef257 | 11705 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
119d663a | 11706 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
119d663a | 11707 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
316f5878 | 11708 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
ae948b86 | 11709 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
4a6a3df4 AO |
11710 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
11711 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
11712 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
11713 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
11714 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
11715 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
11716 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
11717 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
037b32b9 AN |
11718 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
11719 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
23fce1e3 NC |
11720 | |
11721 | /* Strictly speaking this next option is ELF specific, | |
11722 | but we allow it for other ports as well in order to | |
11723 | make testing easier. */ | |
11724 | {"32", no_argument, NULL, OPTION_32}, | |
037b32b9 | 11725 | |
f9b4148d | 11726 | /* ELF-specific options. */ |
156c2f8b | 11727 | #ifdef OBJ_ELF |
156c2f8b NC |
11728 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
11729 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
861fb55a | 11730 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
156c2f8b NC |
11731 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
11732 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
ae948b86 | 11733 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e013f690 | 11734 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b | 11735 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a | 11736 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
ecb4347a | 11737 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
dcd410fe | 11738 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
dcd410fe | 11739 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
0a44bf69 | 11740 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
ae948b86 | 11741 | #endif /* OBJ_ELF */ |
f9b4148d | 11742 | |
252b5132 RH |
11743 | {NULL, no_argument, NULL, 0} |
11744 | }; | |
156c2f8b | 11745 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 11746 | |
316f5878 RS |
11747 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
11748 | NEW_VALUE. Warn if another value was already specified. Note: | |
11749 | we have to defer parsing the -march and -mtune arguments in order | |
11750 | to handle 'from-abi' correctly, since the ABI might be specified | |
11751 | in a later argument. */ | |
11752 | ||
11753 | static void | |
17a2f251 | 11754 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
11755 | { |
11756 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
11757 | as_warn (_("A different %s was already specified, is now %s"), | |
11758 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
11759 | new_value); | |
11760 | ||
11761 | *string_ptr = new_value; | |
11762 | } | |
11763 | ||
252b5132 | 11764 | int |
17a2f251 | 11765 | md_parse_option (int c, char *arg) |
252b5132 RH |
11766 | { |
11767 | switch (c) | |
11768 | { | |
119d663a NC |
11769 | case OPTION_CONSTRUCT_FLOATS: |
11770 | mips_disable_float_construction = 0; | |
11771 | break; | |
bdaaa2e1 | 11772 | |
119d663a NC |
11773 | case OPTION_NO_CONSTRUCT_FLOATS: |
11774 | mips_disable_float_construction = 1; | |
11775 | break; | |
bdaaa2e1 | 11776 | |
252b5132 RH |
11777 | case OPTION_TRAP: |
11778 | mips_trap = 1; | |
11779 | break; | |
11780 | ||
11781 | case OPTION_BREAK: | |
11782 | mips_trap = 0; | |
11783 | break; | |
11784 | ||
11785 | case OPTION_EB: | |
11786 | target_big_endian = 1; | |
11787 | break; | |
11788 | ||
11789 | case OPTION_EL: | |
11790 | target_big_endian = 0; | |
11791 | break; | |
11792 | ||
11793 | case 'O': | |
4ffff32f TS |
11794 | if (arg == NULL) |
11795 | mips_optimize = 1; | |
11796 | else if (arg[0] == '0') | |
11797 | mips_optimize = 0; | |
11798 | else if (arg[0] == '1') | |
252b5132 RH |
11799 | mips_optimize = 1; |
11800 | else | |
11801 | mips_optimize = 2; | |
11802 | break; | |
11803 | ||
11804 | case 'g': | |
11805 | if (arg == NULL) | |
11806 | mips_debug = 2; | |
11807 | else | |
11808 | mips_debug = atoi (arg); | |
252b5132 RH |
11809 | break; |
11810 | ||
11811 | case OPTION_MIPS1: | |
316f5878 | 11812 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
11813 | break; |
11814 | ||
11815 | case OPTION_MIPS2: | |
316f5878 | 11816 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
11817 | break; |
11818 | ||
11819 | case OPTION_MIPS3: | |
316f5878 | 11820 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
11821 | break; |
11822 | ||
11823 | case OPTION_MIPS4: | |
316f5878 | 11824 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
11825 | break; |
11826 | ||
84ea6cf2 | 11827 | case OPTION_MIPS5: |
316f5878 | 11828 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
11829 | break; |
11830 | ||
e7af610e | 11831 | case OPTION_MIPS32: |
316f5878 | 11832 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
11833 | break; |
11834 | ||
af7ee8bf CD |
11835 | case OPTION_MIPS32R2: |
11836 | file_mips_isa = ISA_MIPS32R2; | |
11837 | break; | |
11838 | ||
5f74bc13 CD |
11839 | case OPTION_MIPS64R2: |
11840 | file_mips_isa = ISA_MIPS64R2; | |
11841 | break; | |
11842 | ||
84ea6cf2 | 11843 | case OPTION_MIPS64: |
316f5878 | 11844 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
11845 | break; |
11846 | ||
ec68c924 | 11847 | case OPTION_MTUNE: |
316f5878 RS |
11848 | mips_set_option_string (&mips_tune_string, arg); |
11849 | break; | |
ec68c924 | 11850 | |
316f5878 RS |
11851 | case OPTION_MARCH: |
11852 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
11853 | break; |
11854 | ||
11855 | case OPTION_M4650: | |
316f5878 RS |
11856 | mips_set_option_string (&mips_arch_string, "4650"); |
11857 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
11858 | break; |
11859 | ||
11860 | case OPTION_NO_M4650: | |
11861 | break; | |
11862 | ||
11863 | case OPTION_M4010: | |
316f5878 RS |
11864 | mips_set_option_string (&mips_arch_string, "4010"); |
11865 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
11866 | break; |
11867 | ||
11868 | case OPTION_NO_M4010: | |
11869 | break; | |
11870 | ||
11871 | case OPTION_M4100: | |
316f5878 RS |
11872 | mips_set_option_string (&mips_arch_string, "4100"); |
11873 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
11874 | break; |
11875 | ||
11876 | case OPTION_NO_M4100: | |
11877 | break; | |
11878 | ||
252b5132 | 11879 | case OPTION_M3900: |
316f5878 RS |
11880 | mips_set_option_string (&mips_arch_string, "3900"); |
11881 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 11882 | break; |
bdaaa2e1 | 11883 | |
252b5132 RH |
11884 | case OPTION_NO_M3900: |
11885 | break; | |
11886 | ||
deec1734 CD |
11887 | case OPTION_MDMX: |
11888 | mips_opts.ase_mdmx = 1; | |
11889 | break; | |
11890 | ||
11891 | case OPTION_NO_MDMX: | |
11892 | mips_opts.ase_mdmx = 0; | |
11893 | break; | |
11894 | ||
74cd071d CF |
11895 | case OPTION_DSP: |
11896 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 11897 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
11898 | break; |
11899 | ||
11900 | case OPTION_NO_DSP: | |
8b082fb1 TS |
11901 | mips_opts.ase_dsp = 0; |
11902 | mips_opts.ase_dspr2 = 0; | |
11903 | break; | |
11904 | ||
11905 | case OPTION_DSPR2: | |
11906 | mips_opts.ase_dspr2 = 1; | |
11907 | mips_opts.ase_dsp = 1; | |
11908 | break; | |
11909 | ||
11910 | case OPTION_NO_DSPR2: | |
11911 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
11912 | mips_opts.ase_dsp = 0; |
11913 | break; | |
11914 | ||
ef2e4d86 CF |
11915 | case OPTION_MT: |
11916 | mips_opts.ase_mt = 1; | |
11917 | break; | |
11918 | ||
11919 | case OPTION_NO_MT: | |
11920 | mips_opts.ase_mt = 0; | |
11921 | break; | |
11922 | ||
252b5132 RH |
11923 | case OPTION_MIPS16: |
11924 | mips_opts.mips16 = 1; | |
7d10b47d | 11925 | mips_no_prev_insn (); |
252b5132 RH |
11926 | break; |
11927 | ||
11928 | case OPTION_NO_MIPS16: | |
11929 | mips_opts.mips16 = 0; | |
7d10b47d | 11930 | mips_no_prev_insn (); |
252b5132 RH |
11931 | break; |
11932 | ||
1f25f5d3 CD |
11933 | case OPTION_MIPS3D: |
11934 | mips_opts.ase_mips3d = 1; | |
11935 | break; | |
11936 | ||
11937 | case OPTION_NO_MIPS3D: | |
11938 | mips_opts.ase_mips3d = 0; | |
11939 | break; | |
11940 | ||
e16bfa71 TS |
11941 | case OPTION_SMARTMIPS: |
11942 | mips_opts.ase_smartmips = 1; | |
11943 | break; | |
11944 | ||
11945 | case OPTION_NO_SMARTMIPS: | |
11946 | mips_opts.ase_smartmips = 0; | |
11947 | break; | |
11948 | ||
6a32d874 CM |
11949 | case OPTION_FIX_24K: |
11950 | mips_fix_24k = 1; | |
11951 | break; | |
11952 | ||
11953 | case OPTION_NO_FIX_24K: | |
11954 | mips_fix_24k = 0; | |
11955 | break; | |
11956 | ||
c67a084a NC |
11957 | case OPTION_FIX_LOONGSON2F_JUMP: |
11958 | mips_fix_loongson2f_jump = TRUE; | |
11959 | break; | |
11960 | ||
11961 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
11962 | mips_fix_loongson2f_jump = FALSE; | |
11963 | break; | |
11964 | ||
11965 | case OPTION_FIX_LOONGSON2F_NOP: | |
11966 | mips_fix_loongson2f_nop = TRUE; | |
11967 | break; | |
11968 | ||
11969 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
11970 | mips_fix_loongson2f_nop = FALSE; | |
11971 | break; | |
11972 | ||
d766e8ec RS |
11973 | case OPTION_FIX_VR4120: |
11974 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
11975 | break; |
11976 | ||
d766e8ec RS |
11977 | case OPTION_NO_FIX_VR4120: |
11978 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
11979 | break; |
11980 | ||
7d8e00cf RS |
11981 | case OPTION_FIX_VR4130: |
11982 | mips_fix_vr4130 = 1; | |
11983 | break; | |
11984 | ||
11985 | case OPTION_NO_FIX_VR4130: | |
11986 | mips_fix_vr4130 = 0; | |
11987 | break; | |
11988 | ||
d954098f DD |
11989 | case OPTION_FIX_CN63XXP1: |
11990 | mips_fix_cn63xxp1 = TRUE; | |
11991 | break; | |
11992 | ||
11993 | case OPTION_NO_FIX_CN63XXP1: | |
11994 | mips_fix_cn63xxp1 = FALSE; | |
11995 | break; | |
11996 | ||
4a6a3df4 AO |
11997 | case OPTION_RELAX_BRANCH: |
11998 | mips_relax_branch = 1; | |
11999 | break; | |
12000 | ||
12001 | case OPTION_NO_RELAX_BRANCH: | |
12002 | mips_relax_branch = 0; | |
12003 | break; | |
12004 | ||
aa6975fb ILT |
12005 | case OPTION_MSHARED: |
12006 | mips_in_shared = TRUE; | |
12007 | break; | |
12008 | ||
12009 | case OPTION_MNO_SHARED: | |
12010 | mips_in_shared = FALSE; | |
12011 | break; | |
12012 | ||
aed1a261 RS |
12013 | case OPTION_MSYM32: |
12014 | mips_opts.sym32 = TRUE; | |
12015 | break; | |
12016 | ||
12017 | case OPTION_MNO_SYM32: | |
12018 | mips_opts.sym32 = FALSE; | |
12019 | break; | |
12020 | ||
0f074f60 | 12021 | #ifdef OBJ_ELF |
252b5132 RH |
12022 | /* When generating ELF code, we permit -KPIC and -call_shared to |
12023 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
12024 | intended to be compatible with Irix 5. */ | |
12025 | case OPTION_CALL_SHARED: | |
f43abd2b | 12026 | if (!IS_ELF) |
252b5132 RH |
12027 | { |
12028 | as_bad (_("-call_shared is supported only for ELF format")); | |
12029 | return 0; | |
12030 | } | |
12031 | mips_pic = SVR4_PIC; | |
143d77c5 | 12032 | mips_abicalls = TRUE; |
252b5132 RH |
12033 | break; |
12034 | ||
861fb55a DJ |
12035 | case OPTION_CALL_NONPIC: |
12036 | if (!IS_ELF) | |
12037 | { | |
12038 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
12039 | return 0; | |
12040 | } | |
12041 | mips_pic = NO_PIC; | |
12042 | mips_abicalls = TRUE; | |
12043 | break; | |
12044 | ||
252b5132 | 12045 | case OPTION_NON_SHARED: |
f43abd2b | 12046 | if (!IS_ELF) |
252b5132 RH |
12047 | { |
12048 | as_bad (_("-non_shared is supported only for ELF format")); | |
12049 | return 0; | |
12050 | } | |
12051 | mips_pic = NO_PIC; | |
143d77c5 | 12052 | mips_abicalls = FALSE; |
252b5132 RH |
12053 | break; |
12054 | ||
44075ae2 TS |
12055 | /* The -xgot option tells the assembler to use 32 bit offsets |
12056 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
12057 | compatibility. */ |
12058 | case OPTION_XGOT: | |
12059 | mips_big_got = 1; | |
12060 | break; | |
0f074f60 | 12061 | #endif /* OBJ_ELF */ |
252b5132 RH |
12062 | |
12063 | case 'G': | |
6caf9ef4 TS |
12064 | g_switch_value = atoi (arg); |
12065 | g_switch_seen = 1; | |
252b5132 RH |
12066 | break; |
12067 | ||
34ba82a8 TS |
12068 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
12069 | and -mabi=64. */ | |
252b5132 | 12070 | case OPTION_32: |
23fce1e3 NC |
12071 | if (IS_ELF) |
12072 | mips_abi = O32_ABI; | |
12073 | /* We silently ignore -32 for non-ELF targets. This greatly | |
12074 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
12075 | break; |
12076 | ||
23fce1e3 | 12077 | #ifdef OBJ_ELF |
e013f690 | 12078 | case OPTION_N32: |
f43abd2b | 12079 | if (!IS_ELF) |
34ba82a8 TS |
12080 | { |
12081 | as_bad (_("-n32 is supported for ELF format only")); | |
12082 | return 0; | |
12083 | } | |
316f5878 | 12084 | mips_abi = N32_ABI; |
e013f690 | 12085 | break; |
252b5132 | 12086 | |
e013f690 | 12087 | case OPTION_64: |
f43abd2b | 12088 | if (!IS_ELF) |
34ba82a8 TS |
12089 | { |
12090 | as_bad (_("-64 is supported for ELF format only")); | |
12091 | return 0; | |
12092 | } | |
316f5878 | 12093 | mips_abi = N64_ABI; |
f43abd2b | 12094 | if (!support_64bit_objects()) |
e013f690 | 12095 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 12096 | break; |
ae948b86 | 12097 | #endif /* OBJ_ELF */ |
252b5132 | 12098 | |
c97ef257 | 12099 | case OPTION_GP32: |
a325df1d | 12100 | file_mips_gp32 = 1; |
c97ef257 AH |
12101 | break; |
12102 | ||
12103 | case OPTION_GP64: | |
a325df1d | 12104 | file_mips_gp32 = 0; |
c97ef257 | 12105 | break; |
252b5132 | 12106 | |
ca4e0257 | 12107 | case OPTION_FP32: |
a325df1d | 12108 | file_mips_fp32 = 1; |
316f5878 RS |
12109 | break; |
12110 | ||
12111 | case OPTION_FP64: | |
12112 | file_mips_fp32 = 0; | |
ca4e0257 RS |
12113 | break; |
12114 | ||
037b32b9 AN |
12115 | case OPTION_SINGLE_FLOAT: |
12116 | file_mips_single_float = 1; | |
12117 | break; | |
12118 | ||
12119 | case OPTION_DOUBLE_FLOAT: | |
12120 | file_mips_single_float = 0; | |
12121 | break; | |
12122 | ||
12123 | case OPTION_SOFT_FLOAT: | |
12124 | file_mips_soft_float = 1; | |
12125 | break; | |
12126 | ||
12127 | case OPTION_HARD_FLOAT: | |
12128 | file_mips_soft_float = 0; | |
12129 | break; | |
12130 | ||
ae948b86 | 12131 | #ifdef OBJ_ELF |
252b5132 | 12132 | case OPTION_MABI: |
f43abd2b | 12133 | if (!IS_ELF) |
34ba82a8 TS |
12134 | { |
12135 | as_bad (_("-mabi is supported for ELF format only")); | |
12136 | return 0; | |
12137 | } | |
e013f690 | 12138 | if (strcmp (arg, "32") == 0) |
316f5878 | 12139 | mips_abi = O32_ABI; |
e013f690 | 12140 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 12141 | mips_abi = O64_ABI; |
e013f690 | 12142 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 12143 | mips_abi = N32_ABI; |
e013f690 TS |
12144 | else if (strcmp (arg, "64") == 0) |
12145 | { | |
316f5878 | 12146 | mips_abi = N64_ABI; |
e013f690 TS |
12147 | if (! support_64bit_objects()) |
12148 | as_fatal (_("No compiled in support for 64 bit object file " | |
12149 | "format")); | |
12150 | } | |
12151 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 12152 | mips_abi = EABI_ABI; |
e013f690 | 12153 | else |
da0e507f TS |
12154 | { |
12155 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
12156 | return 0; | |
12157 | } | |
252b5132 | 12158 | break; |
e013f690 | 12159 | #endif /* OBJ_ELF */ |
252b5132 | 12160 | |
6b76fefe | 12161 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 12162 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
12163 | break; |
12164 | ||
9ee72ff1 | 12165 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 12166 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
12167 | break; |
12168 | ||
ecb4347a DJ |
12169 | #ifdef OBJ_ELF |
12170 | case OPTION_MDEBUG: | |
b34976b6 | 12171 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
12172 | break; |
12173 | ||
12174 | case OPTION_NO_MDEBUG: | |
b34976b6 | 12175 | mips_flag_mdebug = FALSE; |
ecb4347a | 12176 | break; |
dcd410fe RO |
12177 | |
12178 | case OPTION_PDR: | |
12179 | mips_flag_pdr = TRUE; | |
12180 | break; | |
12181 | ||
12182 | case OPTION_NO_PDR: | |
12183 | mips_flag_pdr = FALSE; | |
12184 | break; | |
0a44bf69 RS |
12185 | |
12186 | case OPTION_MVXWORKS_PIC: | |
12187 | mips_pic = VXWORKS_PIC; | |
12188 | break; | |
ecb4347a DJ |
12189 | #endif /* OBJ_ELF */ |
12190 | ||
252b5132 RH |
12191 | default: |
12192 | return 0; | |
12193 | } | |
12194 | ||
c67a084a NC |
12195 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
12196 | ||
252b5132 RH |
12197 | return 1; |
12198 | } | |
316f5878 RS |
12199 | \f |
12200 | /* Set up globals to generate code for the ISA or processor | |
12201 | described by INFO. */ | |
252b5132 | 12202 | |
252b5132 | 12203 | static void |
17a2f251 | 12204 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 12205 | { |
316f5878 | 12206 | if (info != 0) |
252b5132 | 12207 | { |
fef14a42 TS |
12208 | file_mips_arch = info->cpu; |
12209 | mips_opts.arch = info->cpu; | |
316f5878 | 12210 | mips_opts.isa = info->isa; |
252b5132 | 12211 | } |
252b5132 RH |
12212 | } |
12213 | ||
252b5132 | 12214 | |
316f5878 | 12215 | /* Likewise for tuning. */ |
252b5132 | 12216 | |
316f5878 | 12217 | static void |
17a2f251 | 12218 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
12219 | { |
12220 | if (info != 0) | |
fef14a42 | 12221 | mips_tune = info->cpu; |
316f5878 | 12222 | } |
80cc45a5 | 12223 | |
34ba82a8 | 12224 | |
252b5132 | 12225 | void |
17a2f251 | 12226 | mips_after_parse_args (void) |
e9670677 | 12227 | { |
fef14a42 TS |
12228 | const struct mips_cpu_info *arch_info = 0; |
12229 | const struct mips_cpu_info *tune_info = 0; | |
12230 | ||
e9670677 | 12231 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 12232 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 12233 | { |
6caf9ef4 | 12234 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
12235 | as_bad (_("-G not supported in this configuration.")); |
12236 | g_switch_value = 0; | |
12237 | } | |
12238 | ||
cac012d6 AO |
12239 | if (mips_abi == NO_ABI) |
12240 | mips_abi = MIPS_DEFAULT_ABI; | |
12241 | ||
22923709 RS |
12242 | /* The following code determines the architecture and register size. |
12243 | Similar code was added to GCC 3.3 (see override_options() in | |
12244 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
12245 | as much as possible. */ | |
e9670677 | 12246 | |
316f5878 | 12247 | if (mips_arch_string != 0) |
fef14a42 | 12248 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 12249 | |
316f5878 | 12250 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 12251 | { |
316f5878 | 12252 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 12253 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 12254 | the -march selection (if any). */ |
fef14a42 | 12255 | if (arch_info != 0) |
e9670677 | 12256 | { |
316f5878 RS |
12257 | /* -march takes precedence over -mipsN, since it is more descriptive. |
12258 | There's no harm in specifying both as long as the ISA levels | |
12259 | are the same. */ | |
fef14a42 | 12260 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
12261 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
12262 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 12263 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 12264 | } |
316f5878 | 12265 | else |
fef14a42 | 12266 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
12267 | } |
12268 | ||
fef14a42 TS |
12269 | if (arch_info == 0) |
12270 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 12271 | |
fef14a42 | 12272 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 12273 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
12274 | arch_info->name); |
12275 | ||
12276 | mips_set_architecture (arch_info); | |
12277 | ||
12278 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
12279 | if (mips_tune_string != 0) | |
12280 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 12281 | |
fef14a42 TS |
12282 | if (tune_info == 0) |
12283 | mips_set_tune (arch_info); | |
12284 | else | |
12285 | mips_set_tune (tune_info); | |
e9670677 | 12286 | |
316f5878 | 12287 | if (file_mips_gp32 >= 0) |
e9670677 | 12288 | { |
316f5878 RS |
12289 | /* The user specified the size of the integer registers. Make sure |
12290 | it agrees with the ABI and ISA. */ | |
12291 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
12292 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
12293 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
12294 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
12295 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
12296 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
12297 | } |
12298 | else | |
12299 | { | |
316f5878 RS |
12300 | /* Infer the integer register size from the ABI and processor. |
12301 | Restrict ourselves to 32-bit registers if that's all the | |
12302 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
12303 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
12304 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
12305 | } |
12306 | ||
ad3fea08 TS |
12307 | switch (file_mips_fp32) |
12308 | { | |
12309 | default: | |
12310 | case -1: | |
12311 | /* No user specified float register size. | |
12312 | ??? GAS treats single-float processors as though they had 64-bit | |
12313 | float registers (although it complains when double-precision | |
12314 | instructions are used). As things stand, saying they have 32-bit | |
12315 | registers would lead to spurious "register must be even" messages. | |
12316 | So here we assume float registers are never smaller than the | |
12317 | integer ones. */ | |
12318 | if (file_mips_gp32 == 0) | |
12319 | /* 64-bit integer registers implies 64-bit float registers. */ | |
12320 | file_mips_fp32 = 0; | |
12321 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
12322 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
12323 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
12324 | file_mips_fp32 = 0; | |
12325 | else | |
12326 | /* 32-bit float registers. */ | |
12327 | file_mips_fp32 = 1; | |
12328 | break; | |
12329 | ||
12330 | /* The user specified the size of the float registers. Check if it | |
12331 | agrees with the ABI and ISA. */ | |
12332 | case 0: | |
12333 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
12334 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
12335 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
12336 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
12337 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
12338 | break; | |
12339 | case 1: | |
12340 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
12341 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
12342 | break; | |
12343 | } | |
e9670677 | 12344 | |
316f5878 | 12345 | /* End of GCC-shared inference code. */ |
e9670677 | 12346 | |
17a2f251 TS |
12347 | /* This flag is set when we have a 64-bit capable CPU but use only |
12348 | 32-bit wide registers. Note that EABI does not use it. */ | |
12349 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
12350 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
12351 | || mips_abi == O32_ABI)) | |
316f5878 | 12352 | mips_32bitmode = 1; |
e9670677 MR |
12353 | |
12354 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
12355 | as_bad (_("trap exception not supported at ISA 1")); | |
12356 | ||
e9670677 MR |
12357 | /* If the selected architecture includes support for ASEs, enable |
12358 | generation of code for them. */ | |
a4672219 | 12359 | if (mips_opts.mips16 == -1) |
fef14a42 | 12360 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 12361 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 12362 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
12363 | && file_mips_fp32 == 0) ? 1 : 0; |
12364 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
12365 | as_bad (_("-mfp32 used with -mips3d")); | |
12366 | ||
ffdefa66 | 12367 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 12368 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
12369 | && file_mips_fp32 == 0) ? 1 : 0; |
12370 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
12371 | as_bad (_("-mfp32 used with -mdmx")); | |
12372 | ||
12373 | if (mips_opts.ase_smartmips == -1) | |
12374 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
12375 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
20203fb9 NC |
12376 | as_warn (_("%s ISA does not support SmartMIPS"), |
12377 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 12378 | |
74cd071d | 12379 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
12380 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
12381 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
20203fb9 NC |
12382 | as_warn (_("%s ISA does not support DSP ASE"), |
12383 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 12384 | |
8b082fb1 TS |
12385 | if (mips_opts.ase_dspr2 == -1) |
12386 | { | |
12387 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
12388 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
12389 | } | |
12390 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 NC |
12391 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
12392 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 12393 | |
ef2e4d86 | 12394 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
12395 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
12396 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
20203fb9 NC |
12397 | as_warn (_("%s ISA does not support MT ASE"), |
12398 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 12399 | |
e9670677 | 12400 | file_mips_isa = mips_opts.isa; |
e9670677 MR |
12401 | file_ase_mips3d = mips_opts.ase_mips3d; |
12402 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 12403 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 12404 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 12405 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 12406 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
12407 | mips_opts.gp32 = file_mips_gp32; |
12408 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
12409 | mips_opts.soft_float = file_mips_soft_float; |
12410 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 12411 | |
ecb4347a DJ |
12412 | if (mips_flag_mdebug < 0) |
12413 | { | |
12414 | #ifdef OBJ_MAYBE_ECOFF | |
12415 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
12416 | mips_flag_mdebug = 1; | |
12417 | else | |
12418 | #endif /* OBJ_MAYBE_ECOFF */ | |
12419 | mips_flag_mdebug = 0; | |
12420 | } | |
e9670677 MR |
12421 | } |
12422 | \f | |
12423 | void | |
17a2f251 | 12424 | mips_init_after_args (void) |
252b5132 RH |
12425 | { |
12426 | /* initialize opcodes */ | |
12427 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 12428 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
12429 | } |
12430 | ||
12431 | long | |
17a2f251 | 12432 | md_pcrel_from (fixS *fixP) |
252b5132 | 12433 | { |
a7ebbfdf TS |
12434 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
12435 | switch (fixP->fx_r_type) | |
12436 | { | |
12437 | case BFD_RELOC_16_PCREL_S2: | |
12438 | case BFD_RELOC_MIPS_JMP: | |
12439 | /* Return the address of the delay slot. */ | |
12440 | return addr + 4; | |
12441 | default: | |
58ea3d6a | 12442 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
12443 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
12444 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12445 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
12446 | return addr; |
12447 | } | |
252b5132 RH |
12448 | } |
12449 | ||
252b5132 RH |
12450 | /* This is called before the symbol table is processed. In order to |
12451 | work with gcc when using mips-tfile, we must keep all local labels. | |
12452 | However, in other cases, we want to discard them. If we were | |
12453 | called with -g, but we didn't see any debugging information, it may | |
12454 | mean that gcc is smuggling debugging information through to | |
12455 | mips-tfile, in which case we must generate all local labels. */ | |
12456 | ||
12457 | void | |
17a2f251 | 12458 | mips_frob_file_before_adjust (void) |
252b5132 RH |
12459 | { |
12460 | #ifndef NO_ECOFF_DEBUGGING | |
12461 | if (ECOFF_DEBUGGING | |
12462 | && mips_debug != 0 | |
12463 | && ! ecoff_debugging_seen) | |
12464 | flag_keep_locals = 1; | |
12465 | #endif | |
12466 | } | |
12467 | ||
3b91255e | 12468 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 12469 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
12470 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
12471 | relocation operators. | |
12472 | ||
12473 | For our purposes, a %lo() expression matches a %got() or %hi() | |
12474 | expression if: | |
12475 | ||
12476 | (a) it refers to the same symbol; and | |
12477 | (b) the offset applied in the %lo() expression is no lower than | |
12478 | the offset applied in the %got() or %hi(). | |
12479 | ||
12480 | (b) allows us to cope with code like: | |
12481 | ||
12482 | lui $4,%hi(foo) | |
12483 | lh $4,%lo(foo+2)($4) | |
12484 | ||
12485 | ...which is legal on RELA targets, and has a well-defined behaviour | |
12486 | if the user knows that adding 2 to "foo" will not induce a carry to | |
12487 | the high 16 bits. | |
12488 | ||
12489 | When several %lo()s match a particular %got() or %hi(), we use the | |
12490 | following rules to distinguish them: | |
12491 | ||
12492 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
12493 | higher offsets. | |
12494 | ||
12495 | (2) %lo()s with no matching %got() or %hi() are better than those | |
12496 | that already have a matching %got() or %hi(). | |
12497 | ||
12498 | (3) later %lo()s are better than earlier %lo()s. | |
12499 | ||
12500 | These rules are applied in order. | |
12501 | ||
12502 | (1) means, among other things, that %lo()s with identical offsets are | |
12503 | chosen if they exist. | |
12504 | ||
12505 | (2) means that we won't associate several high-part relocations with | |
12506 | the same low-part relocation unless there's no alternative. Having | |
12507 | several high parts for the same low part is a GNU extension; this rule | |
12508 | allows careful users to avoid it. | |
12509 | ||
12510 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
12511 | with the last high-part relocation being at the front of the list. | |
12512 | It therefore makes sense to choose the last matching low-part | |
12513 | relocation, all other things being equal. It's also easier | |
12514 | to code that way. */ | |
252b5132 RH |
12515 | |
12516 | void | |
17a2f251 | 12517 | mips_frob_file (void) |
252b5132 RH |
12518 | { |
12519 | struct mips_hi_fixup *l; | |
35903be0 | 12520 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
12521 | |
12522 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
12523 | { | |
12524 | segment_info_type *seginfo; | |
3b91255e RS |
12525 | bfd_boolean matched_lo_p; |
12526 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 12527 | |
9c2799c2 | 12528 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 12529 | |
5919d012 RS |
12530 | /* If a GOT16 relocation turns out to be against a global symbol, |
12531 | there isn't supposed to be a matching LO. */ | |
738e5348 | 12532 | if (got16_reloc_p (l->fixp->fx_r_type) |
5919d012 RS |
12533 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) |
12534 | continue; | |
12535 | ||
12536 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
12537 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
12538 | continue; |
12539 | ||
252b5132 | 12540 | seginfo = seg_info (l->seg); |
252b5132 | 12541 | |
3b91255e RS |
12542 | /* Set HI_POS to the position of this relocation in the chain. |
12543 | Set LO_POS to the position of the chosen low-part relocation. | |
12544 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
12545 | relocation that matches an immediately-preceding high-part | |
12546 | relocation. */ | |
12547 | hi_pos = NULL; | |
12548 | lo_pos = NULL; | |
12549 | matched_lo_p = FALSE; | |
738e5348 | 12550 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 12551 | |
3b91255e RS |
12552 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
12553 | { | |
12554 | if (*pos == l->fixp) | |
12555 | hi_pos = pos; | |
12556 | ||
35903be0 | 12557 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 12558 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
12559 | && (*pos)->fx_offset >= l->fixp->fx_offset |
12560 | && (lo_pos == NULL | |
12561 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
12562 | || (!matched_lo_p | |
12563 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
12564 | lo_pos = pos; | |
12565 | ||
12566 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
12567 | && fixup_has_matching_lo_p (*pos)); | |
12568 | } | |
12569 | ||
12570 | /* If we found a match, remove the high-part relocation from its | |
12571 | current position and insert it before the low-part relocation. | |
12572 | Make the offsets match so that fixup_has_matching_lo_p() | |
12573 | will return true. | |
12574 | ||
12575 | We don't warn about unmatched high-part relocations since some | |
12576 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
12577 | instructions. */ | |
12578 | if (lo_pos != NULL) | |
12579 | { | |
12580 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
12581 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 12582 | { |
3b91255e RS |
12583 | *hi_pos = l->fixp->fx_next; |
12584 | l->fixp->fx_next = *lo_pos; | |
12585 | *lo_pos = l->fixp; | |
252b5132 | 12586 | } |
252b5132 RH |
12587 | } |
12588 | } | |
12589 | } | |
12590 | ||
3e722fb5 | 12591 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 12592 | We have to prevent gas from dropping them. */ |
252b5132 | 12593 | |
252b5132 | 12594 | int |
17a2f251 | 12595 | mips_force_relocation (fixS *fixp) |
252b5132 | 12596 | { |
ae6063d4 | 12597 | if (generic_force_reloc (fixp)) |
252b5132 RH |
12598 | return 1; |
12599 | ||
f6688943 TS |
12600 | if (HAVE_NEWABI |
12601 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
12602 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
738e5348 RS |
12603 | || hi16_reloc_p (fixp->fx_r_type) |
12604 | || lo16_reloc_p (fixp->fx_r_type))) | |
f6688943 TS |
12605 | return 1; |
12606 | ||
3e722fb5 | 12607 | return 0; |
252b5132 RH |
12608 | } |
12609 | ||
12610 | /* Apply a fixup to the object file. */ | |
12611 | ||
94f592af | 12612 | void |
55cf6793 | 12613 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 12614 | { |
874e8986 | 12615 | bfd_byte *buf; |
98aa84af | 12616 | long insn; |
a7ebbfdf | 12617 | reloc_howto_type *howto; |
252b5132 | 12618 | |
a7ebbfdf TS |
12619 | /* We ignore generic BFD relocations we don't know about. */ |
12620 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
12621 | if (! howto) | |
12622 | return; | |
65551fa4 | 12623 | |
9c2799c2 | 12624 | gas_assert (fixP->fx_size == 4 |
90ecf173 MR |
12625 | || fixP->fx_r_type == BFD_RELOC_16 |
12626 | || fixP->fx_r_type == BFD_RELOC_64 | |
12627 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
12628 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
12629 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
12630 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
12631 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 12632 | |
a7ebbfdf | 12633 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 12634 | |
9c2799c2 | 12635 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2); |
b1dca8ee RS |
12636 | |
12637 | /* Don't treat parts of a composite relocation as done. There are two | |
12638 | reasons for this: | |
12639 | ||
12640 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
12641 | should nevertheless be emitted if the first part is. | |
12642 | ||
12643 | (2) In normal usage, composite relocations are never assembly-time | |
12644 | constants. The easiest way of dealing with the pathological | |
12645 | exceptions is to generate a relocation against STN_UNDEF and | |
12646 | leave everything up to the linker. */ | |
3994f87e | 12647 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
12648 | fixP->fx_done = 1; |
12649 | ||
12650 | switch (fixP->fx_r_type) | |
12651 | { | |
3f98094e DJ |
12652 | case BFD_RELOC_MIPS_TLS_GD: |
12653 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
12654 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
12655 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
12656 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
12657 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
12658 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
12659 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
12660 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
12661 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
12662 | /* fall through */ | |
12663 | ||
252b5132 | 12664 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
12665 | case BFD_RELOC_MIPS_SHIFT5: |
12666 | case BFD_RELOC_MIPS_SHIFT6: | |
12667 | case BFD_RELOC_MIPS_GOT_DISP: | |
12668 | case BFD_RELOC_MIPS_GOT_PAGE: | |
12669 | case BFD_RELOC_MIPS_GOT_OFST: | |
12670 | case BFD_RELOC_MIPS_SUB: | |
12671 | case BFD_RELOC_MIPS_INSERT_A: | |
12672 | case BFD_RELOC_MIPS_INSERT_B: | |
12673 | case BFD_RELOC_MIPS_DELETE: | |
12674 | case BFD_RELOC_MIPS_HIGHEST: | |
12675 | case BFD_RELOC_MIPS_HIGHER: | |
12676 | case BFD_RELOC_MIPS_SCN_DISP: | |
12677 | case BFD_RELOC_MIPS_REL16: | |
12678 | case BFD_RELOC_MIPS_RELGOT: | |
12679 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
12680 | case BFD_RELOC_HI16: |
12681 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 12682 | case BFD_RELOC_GPREL16: |
252b5132 RH |
12683 | case BFD_RELOC_MIPS_LITERAL: |
12684 | case BFD_RELOC_MIPS_CALL16: | |
12685 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 12686 | case BFD_RELOC_GPREL32: |
252b5132 RH |
12687 | case BFD_RELOC_MIPS_GOT_HI16: |
12688 | case BFD_RELOC_MIPS_GOT_LO16: | |
12689 | case BFD_RELOC_MIPS_CALL_HI16: | |
12690 | case BFD_RELOC_MIPS_CALL_LO16: | |
12691 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
12692 | case BFD_RELOC_MIPS16_GOT16: |
12693 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
12694 | case BFD_RELOC_MIPS16_HI16: |
12695 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 | 12696 | case BFD_RELOC_MIPS16_JMP: |
54f4ddb3 | 12697 | /* Nothing needed to do. The value comes from the reloc entry. */ |
252b5132 RH |
12698 | break; |
12699 | ||
252b5132 RH |
12700 | case BFD_RELOC_64: |
12701 | /* This is handled like BFD_RELOC_32, but we output a sign | |
12702 | extended value if we are only 32 bits. */ | |
3e722fb5 | 12703 | if (fixP->fx_done) |
252b5132 RH |
12704 | { |
12705 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 12706 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
12707 | else |
12708 | { | |
a7ebbfdf | 12709 | valueT hiv; |
252b5132 | 12710 | |
a7ebbfdf | 12711 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
12712 | hiv = 0xffffffff; |
12713 | else | |
12714 | hiv = 0; | |
b215186b | 12715 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 12716 | *valP, 4); |
b215186b | 12717 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 12718 | hiv, 4); |
252b5132 RH |
12719 | } |
12720 | } | |
12721 | break; | |
12722 | ||
056350c6 | 12723 | case BFD_RELOC_RVA: |
252b5132 | 12724 | case BFD_RELOC_32: |
252b5132 RH |
12725 | case BFD_RELOC_16: |
12726 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
12727 | value now. This can happen if we have a .word which is not |
12728 | resolved when it appears but is later defined. */ | |
252b5132 | 12729 | if (fixP->fx_done) |
54f4ddb3 | 12730 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); |
252b5132 RH |
12731 | break; |
12732 | ||
12733 | case BFD_RELOC_LO16: | |
d6f16593 | 12734 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
12735 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
12736 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
12737 | /* When handling an embedded PIC switch statement, we can wind |
12738 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
12739 | if (fixP->fx_done) | |
12740 | { | |
a7ebbfdf | 12741 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
12742 | as_bad_where (fixP->fx_file, fixP->fx_line, |
12743 | _("relocation overflow")); | |
252b5132 RH |
12744 | if (target_big_endian) |
12745 | buf += 2; | |
2132e3a3 | 12746 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
12747 | } |
12748 | break; | |
12749 | ||
12750 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 12751 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 12752 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 12753 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 12754 | |
54f4ddb3 TS |
12755 | /* We need to save the bits in the instruction since fixup_segment() |
12756 | might be deleting the relocation entry (i.e., a branch within | |
12757 | the current segment). */ | |
a7ebbfdf | 12758 | if (! fixP->fx_done) |
bb2d6cd7 | 12759 | break; |
252b5132 | 12760 | |
54f4ddb3 | 12761 | /* Update old instruction data. */ |
252b5132 RH |
12762 | if (target_big_endian) |
12763 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
12764 | else | |
12765 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
12766 | ||
a7ebbfdf TS |
12767 | if (*valP + 0x20000 <= 0x3ffff) |
12768 | { | |
12769 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 12770 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
12771 | } |
12772 | else if (mips_pic == NO_PIC | |
12773 | && fixP->fx_done | |
12774 | && fixP->fx_frag->fr_address >= text_section->vma | |
12775 | && (fixP->fx_frag->fr_address | |
587aac4e | 12776 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
12777 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
12778 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
12779 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
12780 | { |
12781 | /* The branch offset is too large. If this is an | |
12782 | unconditional branch, and we are not generating PIC code, | |
12783 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
12784 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
12785 | insn = 0x0c000000; /* jal */ | |
252b5132 | 12786 | else |
a7ebbfdf TS |
12787 | insn = 0x08000000; /* j */ |
12788 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
12789 | fixP->fx_done = 0; | |
12790 | fixP->fx_addsy = section_symbol (text_section); | |
12791 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 12792 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
12793 | } |
12794 | else | |
12795 | { | |
12796 | /* If we got here, we have branch-relaxation disabled, | |
12797 | and there's nothing we can do to fix this instruction | |
12798 | without turning it into a longer sequence. */ | |
12799 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12800 | _("Branch out of range")); | |
252b5132 | 12801 | } |
252b5132 RH |
12802 | break; |
12803 | ||
12804 | case BFD_RELOC_VTABLE_INHERIT: | |
12805 | fixP->fx_done = 0; | |
12806 | if (fixP->fx_addsy | |
12807 | && !S_IS_DEFINED (fixP->fx_addsy) | |
12808 | && !S_IS_WEAK (fixP->fx_addsy)) | |
12809 | S_SET_WEAK (fixP->fx_addsy); | |
12810 | break; | |
12811 | ||
12812 | case BFD_RELOC_VTABLE_ENTRY: | |
12813 | fixP->fx_done = 0; | |
12814 | break; | |
12815 | ||
12816 | default: | |
12817 | internalError (); | |
12818 | } | |
a7ebbfdf TS |
12819 | |
12820 | /* Remember value for tc_gen_reloc. */ | |
12821 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
12822 | } |
12823 | ||
252b5132 | 12824 | static symbolS * |
17a2f251 | 12825 | get_symbol (void) |
252b5132 RH |
12826 | { |
12827 | int c; | |
12828 | char *name; | |
12829 | symbolS *p; | |
12830 | ||
12831 | name = input_line_pointer; | |
12832 | c = get_symbol_end (); | |
12833 | p = (symbolS *) symbol_find_or_make (name); | |
12834 | *input_line_pointer = c; | |
12835 | return p; | |
12836 | } | |
12837 | ||
742a56fe RS |
12838 | /* Align the current frag to a given power of two. If a particular |
12839 | fill byte should be used, FILL points to an integer that contains | |
12840 | that byte, otherwise FILL is null. | |
12841 | ||
12842 | The MIPS assembler also automatically adjusts any preceding | |
12843 | label. */ | |
252b5132 RH |
12844 | |
12845 | static void | |
742a56fe | 12846 | mips_align (int to, int *fill, symbolS *label) |
252b5132 | 12847 | { |
7d10b47d | 12848 | mips_emit_delays (); |
742a56fe RS |
12849 | mips_record_mips16_mode (); |
12850 | if (fill == NULL && subseg_text_p (now_seg)) | |
12851 | frag_align_code (to, 0); | |
12852 | else | |
12853 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 RH |
12854 | record_alignment (now_seg, to); |
12855 | if (label != NULL) | |
12856 | { | |
9c2799c2 | 12857 | gas_assert (S_GET_SEGMENT (label) == now_seg); |
49309057 | 12858 | symbol_set_frag (label, frag_now); |
252b5132 RH |
12859 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
12860 | } | |
12861 | } | |
12862 | ||
12863 | /* Align to a given power of two. .align 0 turns off the automatic | |
12864 | alignment used by the data creating pseudo-ops. */ | |
12865 | ||
12866 | static void | |
17a2f251 | 12867 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 12868 | { |
742a56fe | 12869 | int temp, fill_value, *fill_ptr; |
49954fb4 | 12870 | long max_alignment = 28; |
252b5132 | 12871 | |
54f4ddb3 | 12872 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 12873 | to the aligned address. |
54f4ddb3 | 12874 | o It's not documented but auto alignment is reinstated by |
252b5132 | 12875 | a .align pseudo instruction. |
54f4ddb3 | 12876 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 12877 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 12878 | We don't. */ |
252b5132 RH |
12879 | |
12880 | temp = get_absolute_expression (); | |
12881 | if (temp > max_alignment) | |
12882 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
12883 | else if (temp < 0) | |
12884 | { | |
12885 | as_warn (_("Alignment negative: 0 assumed.")); | |
12886 | temp = 0; | |
12887 | } | |
12888 | if (*input_line_pointer == ',') | |
12889 | { | |
f9419b05 | 12890 | ++input_line_pointer; |
742a56fe RS |
12891 | fill_value = get_absolute_expression (); |
12892 | fill_ptr = &fill_value; | |
252b5132 RH |
12893 | } |
12894 | else | |
742a56fe | 12895 | fill_ptr = 0; |
252b5132 RH |
12896 | if (temp) |
12897 | { | |
a8dbcb85 TS |
12898 | segment_info_type *si = seg_info (now_seg); |
12899 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 12900 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 12901 | auto_align = 1; |
742a56fe | 12902 | mips_align (temp, fill_ptr, l != NULL ? l->label : NULL); |
252b5132 RH |
12903 | } |
12904 | else | |
12905 | { | |
12906 | auto_align = 0; | |
12907 | } | |
12908 | ||
12909 | demand_empty_rest_of_line (); | |
12910 | } | |
12911 | ||
252b5132 | 12912 | static void |
17a2f251 | 12913 | s_change_sec (int sec) |
252b5132 RH |
12914 | { |
12915 | segT seg; | |
12916 | ||
252b5132 RH |
12917 | #ifdef OBJ_ELF |
12918 | /* The ELF backend needs to know that we are changing sections, so | |
12919 | that .previous works correctly. We could do something like check | |
b6ff326e | 12920 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
12921 | as it would not be appropriate to use it in the section changing |
12922 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
12923 | This should be cleaner, somehow. */ | |
f43abd2b TS |
12924 | if (IS_ELF) |
12925 | obj_elf_section_change_hook (); | |
252b5132 RH |
12926 | #endif |
12927 | ||
7d10b47d | 12928 | mips_emit_delays (); |
6a32d874 | 12929 | |
252b5132 RH |
12930 | switch (sec) |
12931 | { | |
12932 | case 't': | |
12933 | s_text (0); | |
12934 | break; | |
12935 | case 'd': | |
12936 | s_data (0); | |
12937 | break; | |
12938 | case 'b': | |
12939 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
12940 | demand_empty_rest_of_line (); | |
12941 | break; | |
12942 | ||
12943 | case 'r': | |
4d0d148d TS |
12944 | seg = subseg_new (RDATA_SECTION_NAME, |
12945 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 12946 | if (IS_ELF) |
252b5132 | 12947 | { |
4d0d148d TS |
12948 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
12949 | | SEC_READONLY | SEC_RELOC | |
12950 | | SEC_DATA)); | |
c41e87e3 | 12951 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 12952 | record_alignment (seg, 4); |
252b5132 | 12953 | } |
4d0d148d | 12954 | demand_empty_rest_of_line (); |
252b5132 RH |
12955 | break; |
12956 | ||
12957 | case 's': | |
4d0d148d | 12958 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 12959 | if (IS_ELF) |
252b5132 | 12960 | { |
4d0d148d TS |
12961 | bfd_set_section_flags (stdoutput, seg, |
12962 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 12963 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 12964 | record_alignment (seg, 4); |
252b5132 | 12965 | } |
4d0d148d TS |
12966 | demand_empty_rest_of_line (); |
12967 | break; | |
998b3c36 MR |
12968 | |
12969 | case 'B': | |
12970 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
12971 | if (IS_ELF) | |
12972 | { | |
12973 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); | |
12974 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
12975 | record_alignment (seg, 4); | |
12976 | } | |
12977 | demand_empty_rest_of_line (); | |
12978 | break; | |
252b5132 RH |
12979 | } |
12980 | ||
12981 | auto_align = 1; | |
12982 | } | |
b34976b6 | 12983 | |
cca86cc8 | 12984 | void |
17a2f251 | 12985 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 12986 | { |
7ed4a06a | 12987 | #ifdef OBJ_ELF |
cca86cc8 SC |
12988 | char *section_name; |
12989 | char c; | |
684022ea | 12990 | char next_c = 0; |
cca86cc8 SC |
12991 | int section_type; |
12992 | int section_flag; | |
12993 | int section_entry_size; | |
12994 | int section_alignment; | |
b34976b6 | 12995 | |
f43abd2b | 12996 | if (!IS_ELF) |
7ed4a06a TS |
12997 | return; |
12998 | ||
cca86cc8 SC |
12999 | section_name = input_line_pointer; |
13000 | c = get_symbol_end (); | |
a816d1ed AO |
13001 | if (c) |
13002 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 13003 | |
4cf0dd0d TS |
13004 | /* Do we have .section Name<,"flags">? */ |
13005 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 13006 | { |
4cf0dd0d TS |
13007 | /* just after name is now '\0'. */ |
13008 | *input_line_pointer = c; | |
cca86cc8 SC |
13009 | input_line_pointer = section_name; |
13010 | obj_elf_section (ignore); | |
13011 | return; | |
13012 | } | |
13013 | input_line_pointer++; | |
13014 | ||
13015 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
13016 | if (c == ',') | |
13017 | section_type = get_absolute_expression (); | |
13018 | else | |
13019 | section_type = 0; | |
13020 | if (*input_line_pointer++ == ',') | |
13021 | section_flag = get_absolute_expression (); | |
13022 | else | |
13023 | section_flag = 0; | |
13024 | if (*input_line_pointer++ == ',') | |
13025 | section_entry_size = get_absolute_expression (); | |
13026 | else | |
13027 | section_entry_size = 0; | |
13028 | if (*input_line_pointer++ == ',') | |
13029 | section_alignment = get_absolute_expression (); | |
13030 | else | |
13031 | section_alignment = 0; | |
87975d2a AM |
13032 | /* FIXME: really ignore? */ |
13033 | (void) section_alignment; | |
cca86cc8 | 13034 | |
a816d1ed AO |
13035 | section_name = xstrdup (section_name); |
13036 | ||
8ab8a5c8 RS |
13037 | /* When using the generic form of .section (as implemented by obj-elf.c), |
13038 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
13039 | traditionally had to fall back on the more common @progbits instead. | |
13040 | ||
13041 | There's nothing really harmful in this, since bfd will correct | |
13042 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 13043 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
13044 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
13045 | ||
13046 | Even so, we shouldn't force users of the MIPS .section syntax to | |
13047 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
13048 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
13049 | generic type-checking code. */ | |
13050 | if (section_type == SHT_MIPS_DWARF) | |
13051 | section_type = SHT_PROGBITS; | |
13052 | ||
cca86cc8 SC |
13053 | obj_elf_change_section (section_name, section_type, section_flag, |
13054 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
13055 | |
13056 | if (now_seg->name != section_name) | |
13057 | free (section_name); | |
7ed4a06a | 13058 | #endif /* OBJ_ELF */ |
cca86cc8 | 13059 | } |
252b5132 RH |
13060 | |
13061 | void | |
17a2f251 | 13062 | mips_enable_auto_align (void) |
252b5132 RH |
13063 | { |
13064 | auto_align = 1; | |
13065 | } | |
13066 | ||
13067 | static void | |
17a2f251 | 13068 | s_cons (int log_size) |
252b5132 | 13069 | { |
a8dbcb85 TS |
13070 | segment_info_type *si = seg_info (now_seg); |
13071 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
13072 | symbolS *label; |
13073 | ||
a8dbcb85 | 13074 | label = l != NULL ? l->label : NULL; |
7d10b47d | 13075 | mips_emit_delays (); |
252b5132 RH |
13076 | if (log_size > 0 && auto_align) |
13077 | mips_align (log_size, 0, label); | |
252b5132 | 13078 | cons (1 << log_size); |
a1facbec | 13079 | mips_clear_insn_labels (); |
252b5132 RH |
13080 | } |
13081 | ||
13082 | static void | |
17a2f251 | 13083 | s_float_cons (int type) |
252b5132 | 13084 | { |
a8dbcb85 TS |
13085 | segment_info_type *si = seg_info (now_seg); |
13086 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
13087 | symbolS *label; |
13088 | ||
a8dbcb85 | 13089 | label = l != NULL ? l->label : NULL; |
252b5132 | 13090 | |
7d10b47d | 13091 | mips_emit_delays (); |
252b5132 RH |
13092 | |
13093 | if (auto_align) | |
49309057 ILT |
13094 | { |
13095 | if (type == 'd') | |
13096 | mips_align (3, 0, label); | |
13097 | else | |
13098 | mips_align (2, 0, label); | |
13099 | } | |
252b5132 | 13100 | |
252b5132 | 13101 | float_cons (type); |
a1facbec | 13102 | mips_clear_insn_labels (); |
252b5132 RH |
13103 | } |
13104 | ||
13105 | /* Handle .globl. We need to override it because on Irix 5 you are | |
13106 | permitted to say | |
13107 | .globl foo .text | |
13108 | where foo is an undefined symbol, to mean that foo should be | |
13109 | considered to be the address of a function. */ | |
13110 | ||
13111 | static void | |
17a2f251 | 13112 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13113 | { |
13114 | char *name; | |
13115 | int c; | |
13116 | symbolS *symbolP; | |
13117 | flagword flag; | |
13118 | ||
8a06b769 | 13119 | do |
252b5132 | 13120 | { |
8a06b769 | 13121 | name = input_line_pointer; |
252b5132 | 13122 | c = get_symbol_end (); |
8a06b769 TS |
13123 | symbolP = symbol_find_or_make (name); |
13124 | S_SET_EXTERNAL (symbolP); | |
13125 | ||
252b5132 | 13126 | *input_line_pointer = c; |
8a06b769 | 13127 | SKIP_WHITESPACE (); |
252b5132 | 13128 | |
8a06b769 TS |
13129 | /* On Irix 5, every global symbol that is not explicitly labelled as |
13130 | being a function is apparently labelled as being an object. */ | |
13131 | flag = BSF_OBJECT; | |
252b5132 | 13132 | |
8a06b769 TS |
13133 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
13134 | && (*input_line_pointer != ',')) | |
13135 | { | |
13136 | char *secname; | |
13137 | asection *sec; | |
13138 | ||
13139 | secname = input_line_pointer; | |
13140 | c = get_symbol_end (); | |
13141 | sec = bfd_get_section_by_name (stdoutput, secname); | |
13142 | if (sec == NULL) | |
13143 | as_bad (_("%s: no such section"), secname); | |
13144 | *input_line_pointer = c; | |
13145 | ||
13146 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
13147 | flag = BSF_FUNCTION; | |
13148 | } | |
13149 | ||
13150 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
13151 | ||
13152 | c = *input_line_pointer; | |
13153 | if (c == ',') | |
13154 | { | |
13155 | input_line_pointer++; | |
13156 | SKIP_WHITESPACE (); | |
13157 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
13158 | c = '\n'; | |
13159 | } | |
13160 | } | |
13161 | while (c == ','); | |
252b5132 | 13162 | |
252b5132 RH |
13163 | demand_empty_rest_of_line (); |
13164 | } | |
13165 | ||
13166 | static void | |
17a2f251 | 13167 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13168 | { |
13169 | char *opt; | |
13170 | char c; | |
13171 | ||
13172 | opt = input_line_pointer; | |
13173 | c = get_symbol_end (); | |
13174 | ||
13175 | if (*opt == 'O') | |
13176 | { | |
13177 | /* FIXME: What does this mean? */ | |
13178 | } | |
13179 | else if (strncmp (opt, "pic", 3) == 0) | |
13180 | { | |
13181 | int i; | |
13182 | ||
13183 | i = atoi (opt + 3); | |
13184 | if (i == 0) | |
13185 | mips_pic = NO_PIC; | |
13186 | else if (i == 2) | |
143d77c5 | 13187 | { |
252b5132 | 13188 | mips_pic = SVR4_PIC; |
143d77c5 EC |
13189 | mips_abicalls = TRUE; |
13190 | } | |
252b5132 RH |
13191 | else |
13192 | as_bad (_(".option pic%d not supported"), i); | |
13193 | ||
4d0d148d | 13194 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
13195 | { |
13196 | if (g_switch_seen && g_switch_value != 0) | |
13197 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
13198 | g_switch_value = 0; | |
13199 | bfd_set_gp_size (stdoutput, 0); | |
13200 | } | |
13201 | } | |
13202 | else | |
13203 | as_warn (_("Unrecognized option \"%s\""), opt); | |
13204 | ||
13205 | *input_line_pointer = c; | |
13206 | demand_empty_rest_of_line (); | |
13207 | } | |
13208 | ||
13209 | /* This structure is used to hold a stack of .set values. */ | |
13210 | ||
e972090a NC |
13211 | struct mips_option_stack |
13212 | { | |
252b5132 RH |
13213 | struct mips_option_stack *next; |
13214 | struct mips_set_options options; | |
13215 | }; | |
13216 | ||
13217 | static struct mips_option_stack *mips_opts_stack; | |
13218 | ||
13219 | /* Handle the .set pseudo-op. */ | |
13220 | ||
13221 | static void | |
17a2f251 | 13222 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13223 | { |
13224 | char *name = input_line_pointer, ch; | |
13225 | ||
13226 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 13227 | ++input_line_pointer; |
252b5132 RH |
13228 | ch = *input_line_pointer; |
13229 | *input_line_pointer = '\0'; | |
13230 | ||
13231 | if (strcmp (name, "reorder") == 0) | |
13232 | { | |
7d10b47d RS |
13233 | if (mips_opts.noreorder) |
13234 | end_noreorder (); | |
252b5132 RH |
13235 | } |
13236 | else if (strcmp (name, "noreorder") == 0) | |
13237 | { | |
7d10b47d RS |
13238 | if (!mips_opts.noreorder) |
13239 | start_noreorder (); | |
252b5132 | 13240 | } |
741fe287 MR |
13241 | else if (strncmp (name, "at=", 3) == 0) |
13242 | { | |
13243 | char *s = name + 3; | |
13244 | ||
13245 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
13246 | as_bad (_("Unrecognized register name `%s'"), s); | |
13247 | } | |
252b5132 RH |
13248 | else if (strcmp (name, "at") == 0) |
13249 | { | |
741fe287 | 13250 | mips_opts.at = ATREG; |
252b5132 RH |
13251 | } |
13252 | else if (strcmp (name, "noat") == 0) | |
13253 | { | |
741fe287 | 13254 | mips_opts.at = ZERO; |
252b5132 RH |
13255 | } |
13256 | else if (strcmp (name, "macro") == 0) | |
13257 | { | |
13258 | mips_opts.warn_about_macros = 0; | |
13259 | } | |
13260 | else if (strcmp (name, "nomacro") == 0) | |
13261 | { | |
13262 | if (mips_opts.noreorder == 0) | |
13263 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
13264 | mips_opts.warn_about_macros = 1; | |
13265 | } | |
13266 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
13267 | { | |
13268 | mips_opts.nomove = 0; | |
13269 | } | |
13270 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
13271 | { | |
13272 | mips_opts.nomove = 1; | |
13273 | } | |
13274 | else if (strcmp (name, "bopt") == 0) | |
13275 | { | |
13276 | mips_opts.nobopt = 0; | |
13277 | } | |
13278 | else if (strcmp (name, "nobopt") == 0) | |
13279 | { | |
13280 | mips_opts.nobopt = 1; | |
13281 | } | |
ad3fea08 TS |
13282 | else if (strcmp (name, "gp=default") == 0) |
13283 | mips_opts.gp32 = file_mips_gp32; | |
13284 | else if (strcmp (name, "gp=32") == 0) | |
13285 | mips_opts.gp32 = 1; | |
13286 | else if (strcmp (name, "gp=64") == 0) | |
13287 | { | |
13288 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 13289 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
13290 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13291 | mips_opts.gp32 = 0; | |
13292 | } | |
13293 | else if (strcmp (name, "fp=default") == 0) | |
13294 | mips_opts.fp32 = file_mips_fp32; | |
13295 | else if (strcmp (name, "fp=32") == 0) | |
13296 | mips_opts.fp32 = 1; | |
13297 | else if (strcmp (name, "fp=64") == 0) | |
13298 | { | |
13299 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 13300 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
13301 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13302 | mips_opts.fp32 = 0; | |
13303 | } | |
037b32b9 AN |
13304 | else if (strcmp (name, "softfloat") == 0) |
13305 | mips_opts.soft_float = 1; | |
13306 | else if (strcmp (name, "hardfloat") == 0) | |
13307 | mips_opts.soft_float = 0; | |
13308 | else if (strcmp (name, "singlefloat") == 0) | |
13309 | mips_opts.single_float = 1; | |
13310 | else if (strcmp (name, "doublefloat") == 0) | |
13311 | mips_opts.single_float = 0; | |
252b5132 RH |
13312 | else if (strcmp (name, "mips16") == 0 |
13313 | || strcmp (name, "MIPS-16") == 0) | |
13314 | mips_opts.mips16 = 1; | |
13315 | else if (strcmp (name, "nomips16") == 0 | |
13316 | || strcmp (name, "noMIPS-16") == 0) | |
13317 | mips_opts.mips16 = 0; | |
e16bfa71 TS |
13318 | else if (strcmp (name, "smartmips") == 0) |
13319 | { | |
ad3fea08 | 13320 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 13321 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 TS |
13322 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13323 | mips_opts.ase_smartmips = 1; | |
13324 | } | |
13325 | else if (strcmp (name, "nosmartmips") == 0) | |
13326 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
13327 | else if (strcmp (name, "mips3d") == 0) |
13328 | mips_opts.ase_mips3d = 1; | |
13329 | else if (strcmp (name, "nomips3d") == 0) | |
13330 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
13331 | else if (strcmp (name, "mdmx") == 0) |
13332 | mips_opts.ase_mdmx = 1; | |
13333 | else if (strcmp (name, "nomdmx") == 0) | |
13334 | mips_opts.ase_mdmx = 0; | |
74cd071d | 13335 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
13336 | { |
13337 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 13338 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 TS |
13339 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13340 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 13341 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 13342 | } |
74cd071d | 13343 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
13344 | { |
13345 | mips_opts.ase_dsp = 0; | |
13346 | mips_opts.ase_dspr2 = 0; | |
13347 | } | |
13348 | else if (strcmp (name, "dspr2") == 0) | |
13349 | { | |
13350 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 13351 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 TS |
13352 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13353 | mips_opts.ase_dspr2 = 1; | |
13354 | mips_opts.ase_dsp = 1; | |
13355 | } | |
13356 | else if (strcmp (name, "nodspr2") == 0) | |
13357 | { | |
13358 | mips_opts.ase_dspr2 = 0; | |
13359 | mips_opts.ase_dsp = 0; | |
13360 | } | |
ef2e4d86 | 13361 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
13362 | { |
13363 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 13364 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 TS |
13365 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13366 | mips_opts.ase_mt = 1; | |
13367 | } | |
ef2e4d86 CF |
13368 | else if (strcmp (name, "nomt") == 0) |
13369 | mips_opts.ase_mt = 0; | |
1a2c1fad | 13370 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 13371 | { |
af7ee8bf | 13372 | int reset = 0; |
252b5132 | 13373 | |
1a2c1fad CD |
13374 | /* Permit the user to change the ISA and architecture on the fly. |
13375 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 13376 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
13377 | { |
13378 | reset = 1; | |
13379 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 13380 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
13381 | } |
13382 | else if (strncmp (name, "arch=", 5) == 0) | |
13383 | { | |
13384 | const struct mips_cpu_info *p; | |
13385 | ||
13386 | p = mips_parse_cpu("internal use", name + 5); | |
13387 | if (!p) | |
13388 | as_bad (_("unknown architecture %s"), name + 5); | |
13389 | else | |
13390 | { | |
13391 | mips_opts.arch = p->cpu; | |
13392 | mips_opts.isa = p->isa; | |
13393 | } | |
13394 | } | |
81a21e38 TS |
13395 | else if (strncmp (name, "mips", 4) == 0) |
13396 | { | |
13397 | const struct mips_cpu_info *p; | |
13398 | ||
13399 | p = mips_parse_cpu("internal use", name); | |
13400 | if (!p) | |
13401 | as_bad (_("unknown ISA level %s"), name + 4); | |
13402 | else | |
13403 | { | |
13404 | mips_opts.arch = p->cpu; | |
13405 | mips_opts.isa = p->isa; | |
13406 | } | |
13407 | } | |
af7ee8bf | 13408 | else |
81a21e38 | 13409 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
13410 | |
13411 | switch (mips_opts.isa) | |
98d3f06f KH |
13412 | { |
13413 | case 0: | |
98d3f06f | 13414 | break; |
af7ee8bf CD |
13415 | case ISA_MIPS1: |
13416 | case ISA_MIPS2: | |
13417 | case ISA_MIPS32: | |
13418 | case ISA_MIPS32R2: | |
98d3f06f KH |
13419 | mips_opts.gp32 = 1; |
13420 | mips_opts.fp32 = 1; | |
13421 | break; | |
af7ee8bf CD |
13422 | case ISA_MIPS3: |
13423 | case ISA_MIPS4: | |
13424 | case ISA_MIPS5: | |
13425 | case ISA_MIPS64: | |
5f74bc13 | 13426 | case ISA_MIPS64R2: |
98d3f06f KH |
13427 | mips_opts.gp32 = 0; |
13428 | mips_opts.fp32 = 0; | |
13429 | break; | |
13430 | default: | |
13431 | as_bad (_("unknown ISA level %s"), name + 4); | |
13432 | break; | |
13433 | } | |
af7ee8bf | 13434 | if (reset) |
98d3f06f | 13435 | { |
af7ee8bf CD |
13436 | mips_opts.gp32 = file_mips_gp32; |
13437 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 13438 | } |
252b5132 RH |
13439 | } |
13440 | else if (strcmp (name, "autoextend") == 0) | |
13441 | mips_opts.noautoextend = 0; | |
13442 | else if (strcmp (name, "noautoextend") == 0) | |
13443 | mips_opts.noautoextend = 1; | |
13444 | else if (strcmp (name, "push") == 0) | |
13445 | { | |
13446 | struct mips_option_stack *s; | |
13447 | ||
13448 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
13449 | s->next = mips_opts_stack; | |
13450 | s->options = mips_opts; | |
13451 | mips_opts_stack = s; | |
13452 | } | |
13453 | else if (strcmp (name, "pop") == 0) | |
13454 | { | |
13455 | struct mips_option_stack *s; | |
13456 | ||
13457 | s = mips_opts_stack; | |
13458 | if (s == NULL) | |
13459 | as_bad (_(".set pop with no .set push")); | |
13460 | else | |
13461 | { | |
13462 | /* If we're changing the reorder mode we need to handle | |
13463 | delay slots correctly. */ | |
13464 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 13465 | start_noreorder (); |
252b5132 | 13466 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 13467 | end_noreorder (); |
252b5132 RH |
13468 | |
13469 | mips_opts = s->options; | |
13470 | mips_opts_stack = s->next; | |
13471 | free (s); | |
13472 | } | |
13473 | } | |
aed1a261 RS |
13474 | else if (strcmp (name, "sym32") == 0) |
13475 | mips_opts.sym32 = TRUE; | |
13476 | else if (strcmp (name, "nosym32") == 0) | |
13477 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
13478 | else if (strchr (name, ',')) |
13479 | { | |
13480 | /* Generic ".set" directive; use the generic handler. */ | |
13481 | *input_line_pointer = ch; | |
13482 | input_line_pointer = name; | |
13483 | s_set (0); | |
13484 | return; | |
13485 | } | |
252b5132 RH |
13486 | else |
13487 | { | |
13488 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
13489 | } | |
13490 | *input_line_pointer = ch; | |
13491 | demand_empty_rest_of_line (); | |
13492 | } | |
13493 | ||
13494 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
13495 | .option pic2. It means to generate SVR4 PIC calls. */ | |
13496 | ||
13497 | static void | |
17a2f251 | 13498 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13499 | { |
13500 | mips_pic = SVR4_PIC; | |
143d77c5 | 13501 | mips_abicalls = TRUE; |
4d0d148d TS |
13502 | |
13503 | if (g_switch_seen && g_switch_value != 0) | |
13504 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
13505 | g_switch_value = 0; | |
13506 | ||
252b5132 RH |
13507 | bfd_set_gp_size (stdoutput, 0); |
13508 | demand_empty_rest_of_line (); | |
13509 | } | |
13510 | ||
13511 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
13512 | PIC code. It sets the $gp register for the function based on the | |
13513 | function address, which is in the register named in the argument. | |
13514 | This uses a relocation against _gp_disp, which is handled specially | |
13515 | by the linker. The result is: | |
13516 | lui $gp,%hi(_gp_disp) | |
13517 | addiu $gp,$gp,%lo(_gp_disp) | |
13518 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
13519 | The .cpload argument is normally $25 == $t9. |
13520 | ||
13521 | The -mno-shared option changes this to: | |
bbe506e8 TS |
13522 | lui $gp,%hi(__gnu_local_gp) |
13523 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
13524 | and the argument is ignored. This saves an instruction, but the |
13525 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
13526 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
13527 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
13528 | |
13529 | static void | |
17a2f251 | 13530 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13531 | { |
13532 | expressionS ex; | |
aa6975fb ILT |
13533 | int reg; |
13534 | int in_shared; | |
252b5132 | 13535 | |
6478892d TS |
13536 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
13537 | .cpload is ignored. */ | |
13538 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
13539 | { |
13540 | s_ignore (0); | |
13541 | return; | |
13542 | } | |
13543 | ||
d3ecfc59 | 13544 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
13545 | if (mips_opts.noreorder == 0) |
13546 | as_warn (_(".cpload not in noreorder section")); | |
13547 | ||
aa6975fb ILT |
13548 | reg = tc_get_register (0); |
13549 | ||
13550 | /* If we need to produce a 64-bit address, we are better off using | |
13551 | the default instruction sequence. */ | |
aed1a261 | 13552 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 13553 | |
252b5132 | 13554 | ex.X_op = O_symbol; |
bbe506e8 TS |
13555 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
13556 | "__gnu_local_gp"); | |
252b5132 RH |
13557 | ex.X_op_symbol = NULL; |
13558 | ex.X_add_number = 0; | |
13559 | ||
13560 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 13561 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 13562 | |
584892a6 | 13563 | macro_start (); |
67c0d1eb RS |
13564 | macro_build_lui (&ex, mips_gp_register); |
13565 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 13566 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
13567 | if (in_shared) |
13568 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
13569 | mips_gp_register, reg); | |
584892a6 | 13570 | macro_end (); |
252b5132 RH |
13571 | |
13572 | demand_empty_rest_of_line (); | |
13573 | } | |
13574 | ||
6478892d TS |
13575 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
13576 | .cpsetup $reg1, offset|$reg2, label | |
13577 | ||
13578 | If offset is given, this results in: | |
13579 | sd $gp, offset($sp) | |
956cd1d6 | 13580 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
13581 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
13582 | daddu $gp, $gp, $reg1 | |
6478892d TS |
13583 | |
13584 | If $reg2 is given, this results in: | |
13585 | daddu $reg2, $gp, $0 | |
956cd1d6 | 13586 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
13587 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
13588 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
13589 | $reg1 is normally $25 == $t9. |
13590 | ||
13591 | The -mno-shared option replaces the last three instructions with | |
13592 | lui $gp,%hi(_gp) | |
54f4ddb3 | 13593 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 13594 | |
6478892d | 13595 | static void |
17a2f251 | 13596 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13597 | { |
13598 | expressionS ex_off; | |
13599 | expressionS ex_sym; | |
13600 | int reg1; | |
6478892d | 13601 | |
8586fc66 | 13602 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
13603 | We also need NewABI support. */ |
13604 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13605 | { | |
13606 | s_ignore (0); | |
13607 | return; | |
13608 | } | |
13609 | ||
13610 | reg1 = tc_get_register (0); | |
13611 | SKIP_WHITESPACE (); | |
13612 | if (*input_line_pointer != ',') | |
13613 | { | |
13614 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
13615 | return; | |
13616 | } | |
13617 | else | |
80245285 | 13618 | ++input_line_pointer; |
6478892d TS |
13619 | SKIP_WHITESPACE (); |
13620 | if (*input_line_pointer == '$') | |
80245285 TS |
13621 | { |
13622 | mips_cpreturn_register = tc_get_register (0); | |
13623 | mips_cpreturn_offset = -1; | |
13624 | } | |
6478892d | 13625 | else |
80245285 TS |
13626 | { |
13627 | mips_cpreturn_offset = get_absolute_expression (); | |
13628 | mips_cpreturn_register = -1; | |
13629 | } | |
6478892d TS |
13630 | SKIP_WHITESPACE (); |
13631 | if (*input_line_pointer != ',') | |
13632 | { | |
13633 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
13634 | return; | |
13635 | } | |
13636 | else | |
f9419b05 | 13637 | ++input_line_pointer; |
6478892d | 13638 | SKIP_WHITESPACE (); |
f21f8242 | 13639 | expression (&ex_sym); |
6478892d | 13640 | |
584892a6 | 13641 | macro_start (); |
6478892d TS |
13642 | if (mips_cpreturn_register == -1) |
13643 | { | |
13644 | ex_off.X_op = O_constant; | |
13645 | ex_off.X_add_symbol = NULL; | |
13646 | ex_off.X_op_symbol = NULL; | |
13647 | ex_off.X_add_number = mips_cpreturn_offset; | |
13648 | ||
67c0d1eb | 13649 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 13650 | BFD_RELOC_LO16, SP); |
6478892d TS |
13651 | } |
13652 | else | |
67c0d1eb | 13653 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 13654 | mips_gp_register, 0); |
6478892d | 13655 | |
aed1a261 | 13656 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
13657 | { |
13658 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
13659 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
13660 | BFD_RELOC_HI16_S); | |
13661 | ||
13662 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
13663 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
13664 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
13665 | ||
13666 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
13667 | mips_gp_register, reg1); | |
13668 | } | |
13669 | else | |
13670 | { | |
13671 | expressionS ex; | |
13672 | ||
13673 | ex.X_op = O_symbol; | |
4184909a | 13674 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
13675 | ex.X_op_symbol = NULL; |
13676 | ex.X_add_number = 0; | |
6e1304d8 | 13677 | |
aa6975fb ILT |
13678 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
13679 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
13680 | ||
13681 | macro_build_lui (&ex, mips_gp_register); | |
13682 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
13683 | mips_gp_register, BFD_RELOC_LO16); | |
13684 | } | |
f21f8242 | 13685 | |
584892a6 | 13686 | macro_end (); |
6478892d TS |
13687 | |
13688 | demand_empty_rest_of_line (); | |
13689 | } | |
13690 | ||
13691 | static void | |
17a2f251 | 13692 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13693 | { |
13694 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 13695 | .cplocal is ignored. */ |
6478892d TS |
13696 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
13697 | { | |
13698 | s_ignore (0); | |
13699 | return; | |
13700 | } | |
13701 | ||
13702 | mips_gp_register = tc_get_register (0); | |
85b51719 | 13703 | demand_empty_rest_of_line (); |
6478892d TS |
13704 | } |
13705 | ||
252b5132 RH |
13706 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
13707 | offset from $sp. The offset is remembered, and after making a PIC | |
13708 | call $gp is restored from that location. */ | |
13709 | ||
13710 | static void | |
17a2f251 | 13711 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13712 | { |
13713 | expressionS ex; | |
252b5132 | 13714 | |
6478892d | 13715 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 13716 | .cprestore is ignored. */ |
6478892d | 13717 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
13718 | { |
13719 | s_ignore (0); | |
13720 | return; | |
13721 | } | |
13722 | ||
13723 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 13724 | mips_cprestore_valid = 1; |
252b5132 RH |
13725 | |
13726 | ex.X_op = O_constant; | |
13727 | ex.X_add_symbol = NULL; | |
13728 | ex.X_op_symbol = NULL; | |
13729 | ex.X_add_number = mips_cprestore_offset; | |
13730 | ||
584892a6 | 13731 | macro_start (); |
67c0d1eb RS |
13732 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
13733 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 13734 | macro_end (); |
252b5132 RH |
13735 | |
13736 | demand_empty_rest_of_line (); | |
13737 | } | |
13738 | ||
6478892d | 13739 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 13740 | was given in the preceding .cpsetup, it results in: |
6478892d | 13741 | ld $gp, offset($sp) |
76b3015f | 13742 | |
6478892d | 13743 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
13744 | daddu $gp, $reg2, $0 */ |
13745 | ||
6478892d | 13746 | static void |
17a2f251 | 13747 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13748 | { |
13749 | expressionS ex; | |
6478892d TS |
13750 | |
13751 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
13752 | We also need NewABI support. */ | |
13753 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13754 | { | |
13755 | s_ignore (0); | |
13756 | return; | |
13757 | } | |
13758 | ||
584892a6 | 13759 | macro_start (); |
6478892d TS |
13760 | if (mips_cpreturn_register == -1) |
13761 | { | |
13762 | ex.X_op = O_constant; | |
13763 | ex.X_add_symbol = NULL; | |
13764 | ex.X_op_symbol = NULL; | |
13765 | ex.X_add_number = mips_cpreturn_offset; | |
13766 | ||
67c0d1eb | 13767 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
13768 | } |
13769 | else | |
67c0d1eb | 13770 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 13771 | mips_cpreturn_register, 0); |
584892a6 | 13772 | macro_end (); |
6478892d TS |
13773 | |
13774 | demand_empty_rest_of_line (); | |
13775 | } | |
13776 | ||
741d6ea8 JM |
13777 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate |
13778 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
13779 | use in DWARF debug information. */ | |
13780 | ||
13781 | static void | |
13782 | s_dtprel_internal (size_t bytes) | |
13783 | { | |
13784 | expressionS ex; | |
13785 | char *p; | |
13786 | ||
13787 | expression (&ex); | |
13788 | ||
13789 | if (ex.X_op != O_symbol) | |
13790 | { | |
13791 | as_bad (_("Unsupported use of %s"), (bytes == 8 | |
13792 | ? ".dtpreldword" | |
13793 | : ".dtprelword")); | |
13794 | ignore_rest_of_line (); | |
13795 | } | |
13796 | ||
13797 | p = frag_more (bytes); | |
13798 | md_number_to_chars (p, 0, bytes); | |
13799 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, | |
13800 | (bytes == 8 | |
13801 | ? BFD_RELOC_MIPS_TLS_DTPREL64 | |
13802 | : BFD_RELOC_MIPS_TLS_DTPREL32)); | |
13803 | ||
13804 | demand_empty_rest_of_line (); | |
13805 | } | |
13806 | ||
13807 | /* Handle .dtprelword. */ | |
13808 | ||
13809 | static void | |
13810 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
13811 | { | |
13812 | s_dtprel_internal (4); | |
13813 | } | |
13814 | ||
13815 | /* Handle .dtpreldword. */ | |
13816 | ||
13817 | static void | |
13818 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
13819 | { | |
13820 | s_dtprel_internal (8); | |
13821 | } | |
13822 | ||
6478892d TS |
13823 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
13824 | code. It sets the offset to use in gp_rel relocations. */ | |
13825 | ||
13826 | static void | |
17a2f251 | 13827 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13828 | { |
13829 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
13830 | We also need NewABI support. */ | |
13831 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13832 | { | |
13833 | s_ignore (0); | |
13834 | return; | |
13835 | } | |
13836 | ||
def2e0dd | 13837 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
13838 | |
13839 | demand_empty_rest_of_line (); | |
13840 | } | |
13841 | ||
252b5132 RH |
13842 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
13843 | code. It generates a 32 bit GP relative reloc. */ | |
13844 | ||
13845 | static void | |
17a2f251 | 13846 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13847 | { |
a8dbcb85 TS |
13848 | segment_info_type *si; |
13849 | struct insn_label_list *l; | |
252b5132 RH |
13850 | symbolS *label; |
13851 | expressionS ex; | |
13852 | char *p; | |
13853 | ||
13854 | /* When not generating PIC code, this is treated as .word. */ | |
13855 | if (mips_pic != SVR4_PIC) | |
13856 | { | |
13857 | s_cons (2); | |
13858 | return; | |
13859 | } | |
13860 | ||
a8dbcb85 TS |
13861 | si = seg_info (now_seg); |
13862 | l = si->label_list; | |
13863 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13864 | mips_emit_delays (); |
252b5132 RH |
13865 | if (auto_align) |
13866 | mips_align (2, 0, label); | |
252b5132 RH |
13867 | |
13868 | expression (&ex); | |
a1facbec | 13869 | mips_clear_insn_labels (); |
252b5132 RH |
13870 | |
13871 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13872 | { | |
13873 | as_bad (_("Unsupported use of .gpword")); | |
13874 | ignore_rest_of_line (); | |
13875 | } | |
13876 | ||
13877 | p = frag_more (4); | |
17a2f251 | 13878 | md_number_to_chars (p, 0, 4); |
b34976b6 | 13879 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 13880 | BFD_RELOC_GPREL32); |
252b5132 RH |
13881 | |
13882 | demand_empty_rest_of_line (); | |
13883 | } | |
13884 | ||
10181a0d | 13885 | static void |
17a2f251 | 13886 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 13887 | { |
a8dbcb85 TS |
13888 | segment_info_type *si; |
13889 | struct insn_label_list *l; | |
10181a0d AO |
13890 | symbolS *label; |
13891 | expressionS ex; | |
13892 | char *p; | |
13893 | ||
13894 | /* When not generating PIC code, this is treated as .dword. */ | |
13895 | if (mips_pic != SVR4_PIC) | |
13896 | { | |
13897 | s_cons (3); | |
13898 | return; | |
13899 | } | |
13900 | ||
a8dbcb85 TS |
13901 | si = seg_info (now_seg); |
13902 | l = si->label_list; | |
13903 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13904 | mips_emit_delays (); |
10181a0d AO |
13905 | if (auto_align) |
13906 | mips_align (3, 0, label); | |
10181a0d AO |
13907 | |
13908 | expression (&ex); | |
a1facbec | 13909 | mips_clear_insn_labels (); |
10181a0d AO |
13910 | |
13911 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13912 | { | |
13913 | as_bad (_("Unsupported use of .gpdword")); | |
13914 | ignore_rest_of_line (); | |
13915 | } | |
13916 | ||
13917 | p = frag_more (8); | |
17a2f251 | 13918 | md_number_to_chars (p, 0, 8); |
a105a300 | 13919 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 13920 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
13921 | |
13922 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
13923 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
13924 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
13925 | |
13926 | demand_empty_rest_of_line (); | |
13927 | } | |
13928 | ||
252b5132 RH |
13929 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
13930 | tables in SVR4 PIC code. */ | |
13931 | ||
13932 | static void | |
17a2f251 | 13933 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13934 | { |
252b5132 RH |
13935 | int reg; |
13936 | ||
10181a0d AO |
13937 | /* This is ignored when not generating SVR4 PIC code. */ |
13938 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
13939 | { |
13940 | s_ignore (0); | |
13941 | return; | |
13942 | } | |
13943 | ||
13944 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 13945 | macro_start (); |
252b5132 | 13946 | reg = tc_get_register (0); |
67c0d1eb | 13947 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 13948 | macro_end (); |
252b5132 | 13949 | |
bdaaa2e1 | 13950 | demand_empty_rest_of_line (); |
252b5132 RH |
13951 | } |
13952 | ||
13953 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
13954 | mips16 mode. This permits the linker to handle them specially, | |
13955 | such as generating jalx instructions when needed. We also make | |
13956 | them odd for the duration of the assembly, in order to generate the | |
13957 | right sort of code. We will make them even in the adjust_symtab | |
13958 | routine, while leaving them marked. This is convenient for the | |
13959 | debugger and the disassembler. The linker knows to make them odd | |
13960 | again. */ | |
13961 | ||
13962 | static void | |
17a2f251 | 13963 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13964 | { |
f9419b05 | 13965 | mips16_mark_labels (); |
252b5132 RH |
13966 | |
13967 | demand_empty_rest_of_line (); | |
13968 | } | |
13969 | ||
13970 | /* Handle a .stabn directive. We need these in order to mark a label | |
13971 | as being a mips16 text label correctly. Sometimes the compiler | |
13972 | will emit a label, followed by a .stabn, and then switch sections. | |
13973 | If the label and .stabn are in mips16 mode, then the label is | |
13974 | really a mips16 text label. */ | |
13975 | ||
13976 | static void | |
17a2f251 | 13977 | s_mips_stab (int type) |
252b5132 | 13978 | { |
f9419b05 | 13979 | if (type == 'n') |
252b5132 RH |
13980 | mips16_mark_labels (); |
13981 | ||
13982 | s_stab (type); | |
13983 | } | |
13984 | ||
54f4ddb3 | 13985 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
13986 | |
13987 | static void | |
17a2f251 | 13988 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13989 | { |
13990 | char *name; | |
13991 | int c; | |
13992 | symbolS *symbolP; | |
13993 | expressionS exp; | |
13994 | ||
13995 | name = input_line_pointer; | |
13996 | c = get_symbol_end (); | |
13997 | symbolP = symbol_find_or_make (name); | |
13998 | S_SET_WEAK (symbolP); | |
13999 | *input_line_pointer = c; | |
14000 | ||
14001 | SKIP_WHITESPACE (); | |
14002 | ||
14003 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
14004 | { | |
14005 | if (S_IS_DEFINED (symbolP)) | |
14006 | { | |
20203fb9 | 14007 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
14008 | S_GET_NAME (symbolP)); |
14009 | ignore_rest_of_line (); | |
14010 | return; | |
14011 | } | |
bdaaa2e1 | 14012 | |
252b5132 RH |
14013 | if (*input_line_pointer == ',') |
14014 | { | |
14015 | ++input_line_pointer; | |
14016 | SKIP_WHITESPACE (); | |
14017 | } | |
bdaaa2e1 | 14018 | |
252b5132 RH |
14019 | expression (&exp); |
14020 | if (exp.X_op != O_symbol) | |
14021 | { | |
20203fb9 | 14022 | as_bad (_("bad .weakext directive")); |
98d3f06f | 14023 | ignore_rest_of_line (); |
252b5132 RH |
14024 | return; |
14025 | } | |
49309057 | 14026 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
14027 | } |
14028 | ||
14029 | demand_empty_rest_of_line (); | |
14030 | } | |
14031 | ||
14032 | /* Parse a register string into a number. Called from the ECOFF code | |
14033 | to parse .frame. The argument is non-zero if this is the frame | |
14034 | register, so that we can record it in mips_frame_reg. */ | |
14035 | ||
14036 | int | |
17a2f251 | 14037 | tc_get_register (int frame) |
252b5132 | 14038 | { |
707bfff6 | 14039 | unsigned int reg; |
252b5132 RH |
14040 | |
14041 | SKIP_WHITESPACE (); | |
707bfff6 TS |
14042 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
14043 | reg = 0; | |
252b5132 | 14044 | if (frame) |
7a621144 DJ |
14045 | { |
14046 | mips_frame_reg = reg != 0 ? reg : SP; | |
14047 | mips_frame_reg_valid = 1; | |
14048 | mips_cprestore_valid = 0; | |
14049 | } | |
252b5132 RH |
14050 | return reg; |
14051 | } | |
14052 | ||
14053 | valueT | |
17a2f251 | 14054 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
14055 | { |
14056 | int align = bfd_get_section_alignment (stdoutput, seg); | |
14057 | ||
b4c71f56 TS |
14058 | if (IS_ELF) |
14059 | { | |
14060 | /* We don't need to align ELF sections to the full alignment. | |
14061 | However, Irix 5 may prefer that we align them at least to a 16 | |
14062 | byte boundary. We don't bother to align the sections if we | |
14063 | are targeted for an embedded system. */ | |
c41e87e3 | 14064 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
14065 | return addr; |
14066 | if (align > 4) | |
14067 | align = 4; | |
14068 | } | |
252b5132 RH |
14069 | |
14070 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
14071 | } | |
14072 | ||
14073 | /* Utility routine, called from above as well. If called while the | |
14074 | input file is still being read, it's only an approximation. (For | |
14075 | example, a symbol may later become defined which appeared to be | |
14076 | undefined earlier.) */ | |
14077 | ||
14078 | static int | |
17a2f251 | 14079 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
14080 | { |
14081 | if (sym == 0) | |
14082 | return 0; | |
14083 | ||
4d0d148d | 14084 | if (g_switch_value > 0) |
252b5132 RH |
14085 | { |
14086 | const char *symname; | |
14087 | int change; | |
14088 | ||
c9914766 | 14089 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
14090 | register. It can be if it is smaller than the -G size or if |
14091 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 14092 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
14093 | they can. */ |
14094 | symname = S_GET_NAME (sym); | |
14095 | if (symname != (const char *) NULL | |
14096 | && (strcmp (symname, "eprol") == 0 | |
14097 | || strcmp (symname, "etext") == 0 | |
14098 | || strcmp (symname, "_gp") == 0 | |
14099 | || strcmp (symname, "edata") == 0 | |
14100 | || strcmp (symname, "_fbss") == 0 | |
14101 | || strcmp (symname, "_fdata") == 0 | |
14102 | || strcmp (symname, "_ftext") == 0 | |
14103 | || strcmp (symname, "end") == 0 | |
14104 | || strcmp (symname, "_gp_disp") == 0)) | |
14105 | change = 1; | |
14106 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
14107 | && (0 | |
14108 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
14109 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
14110 | && (symbol_get_obj (sym)->ecoff_extern_size | |
14111 | <= g_switch_value)) | |
252b5132 RH |
14112 | #endif |
14113 | /* We must defer this decision until after the whole | |
14114 | file has been read, since there might be a .extern | |
14115 | after the first use of this symbol. */ | |
14116 | || (before_relaxing | |
14117 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 14118 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
14119 | #endif |
14120 | && S_GET_VALUE (sym) == 0) | |
14121 | || (S_GET_VALUE (sym) != 0 | |
14122 | && S_GET_VALUE (sym) <= g_switch_value))) | |
14123 | change = 0; | |
14124 | else | |
14125 | { | |
14126 | const char *segname; | |
14127 | ||
14128 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 14129 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
14130 | && strcmp (segname, ".lit4") != 0); |
14131 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
14132 | && strcmp (segname, ".sbss") != 0 |
14133 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
14134 | && strncmp (segname, ".sbss.", 6) != 0 |
14135 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 14136 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
14137 | } |
14138 | return change; | |
14139 | } | |
14140 | else | |
c9914766 | 14141 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
14142 | return 1; |
14143 | } | |
14144 | ||
5919d012 RS |
14145 | |
14146 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
14147 | ||
14148 | static bfd_boolean | |
17a2f251 | 14149 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
14150 | { |
14151 | asection *symsec; | |
5919d012 RS |
14152 | |
14153 | /* Handle the case of a symbol equated to another symbol. */ | |
14154 | while (symbol_equated_reloc_p (sym)) | |
14155 | { | |
14156 | symbolS *n; | |
14157 | ||
5f0fe04b | 14158 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
14159 | n = symbol_get_value_expression (sym)->X_add_symbol; |
14160 | if (n == sym) | |
14161 | break; | |
14162 | sym = n; | |
14163 | } | |
14164 | ||
df1f3cda DD |
14165 | if (symbol_section_p (sym)) |
14166 | return TRUE; | |
14167 | ||
5919d012 RS |
14168 | symsec = S_GET_SEGMENT (sym); |
14169 | ||
5919d012 RS |
14170 | /* This must duplicate the test in adjust_reloc_syms. */ |
14171 | return (symsec != &bfd_und_section | |
14172 | && symsec != &bfd_abs_section | |
5f0fe04b TS |
14173 | && !bfd_is_com_section (symsec) |
14174 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
14175 | #ifdef OBJ_ELF |
14176 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 14177 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
14178 | #endif |
14179 | ); | |
14180 | } | |
14181 | ||
14182 | ||
252b5132 RH |
14183 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
14184 | extended opcode. SEC is the section the frag is in. */ | |
14185 | ||
14186 | static int | |
17a2f251 | 14187 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
14188 | { |
14189 | int type; | |
3994f87e | 14190 | const struct mips16_immed_operand *op; |
252b5132 RH |
14191 | offsetT val; |
14192 | int mintiny, maxtiny; | |
14193 | segT symsec; | |
98aa84af | 14194 | fragS *sym_frag; |
252b5132 RH |
14195 | |
14196 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
14197 | return 0; | |
14198 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
14199 | return 1; | |
14200 | ||
14201 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
14202 | op = mips16_immed_operands; | |
14203 | while (op->type != type) | |
14204 | { | |
14205 | ++op; | |
9c2799c2 | 14206 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
14207 | } |
14208 | ||
14209 | if (op->unsp) | |
14210 | { | |
14211 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
14212 | { | |
14213 | mintiny = 1; | |
14214 | maxtiny = 1 << op->nbits; | |
14215 | } | |
14216 | else | |
14217 | { | |
14218 | mintiny = 0; | |
14219 | maxtiny = (1 << op->nbits) - 1; | |
14220 | } | |
14221 | } | |
14222 | else | |
14223 | { | |
14224 | mintiny = - (1 << (op->nbits - 1)); | |
14225 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
14226 | } | |
14227 | ||
98aa84af | 14228 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 14229 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 14230 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
14231 | |
14232 | if (op->pcrel) | |
14233 | { | |
14234 | addressT addr; | |
14235 | ||
14236 | /* We won't have the section when we are called from | |
14237 | mips_relax_frag. However, we will always have been called | |
14238 | from md_estimate_size_before_relax first. If this is a | |
14239 | branch to a different section, we mark it as such. If SEC is | |
14240 | NULL, and the frag is not marked, then it must be a branch to | |
14241 | the same section. */ | |
14242 | if (sec == NULL) | |
14243 | { | |
14244 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
14245 | return 1; | |
14246 | } | |
14247 | else | |
14248 | { | |
98aa84af | 14249 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
14250 | if (symsec != sec) |
14251 | { | |
14252 | fragp->fr_subtype = | |
14253 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
14254 | ||
14255 | /* FIXME: We should support this, and let the linker | |
14256 | catch branches and loads that are out of range. */ | |
14257 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
14258 | _("unsupported PC relative reference to different section")); | |
14259 | ||
14260 | return 1; | |
14261 | } | |
98aa84af AM |
14262 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
14263 | /* Assume non-extended on the first relaxation pass. | |
14264 | The address we have calculated will be bogus if this is | |
14265 | a forward branch to another frag, as the forward frag | |
14266 | will have fr_address == 0. */ | |
14267 | return 0; | |
252b5132 RH |
14268 | } |
14269 | ||
14270 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
14271 | the same section. If the relax_marker of the symbol fragment |
14272 | differs from the relax_marker of this fragment, we have not | |
14273 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
14274 | in STRETCH in order to get a better estimate of the address. |
14275 | This particularly matters because of the shift bits. */ | |
14276 | if (stretch != 0 | |
98aa84af | 14277 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
14278 | { |
14279 | fragS *f; | |
14280 | ||
14281 | /* Adjust stretch for any alignment frag. Note that if have | |
14282 | been expanding the earlier code, the symbol may be | |
14283 | defined in what appears to be an earlier frag. FIXME: | |
14284 | This doesn't handle the fr_subtype field, which specifies | |
14285 | a maximum number of bytes to skip when doing an | |
14286 | alignment. */ | |
98aa84af | 14287 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
14288 | { |
14289 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
14290 | { | |
14291 | if (stretch < 0) | |
14292 | stretch = - ((- stretch) | |
14293 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
14294 | else | |
14295 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
14296 | if (stretch == 0) | |
14297 | break; | |
14298 | } | |
14299 | } | |
14300 | if (f != NULL) | |
14301 | val += stretch; | |
14302 | } | |
14303 | ||
14304 | addr = fragp->fr_address + fragp->fr_fix; | |
14305 | ||
14306 | /* The base address rules are complicated. The base address of | |
14307 | a branch is the following instruction. The base address of a | |
14308 | PC relative load or add is the instruction itself, but if it | |
14309 | is in a delay slot (in which case it can not be extended) use | |
14310 | the address of the instruction whose delay slot it is in. */ | |
14311 | if (type == 'p' || type == 'q') | |
14312 | { | |
14313 | addr += 2; | |
14314 | ||
14315 | /* If we are currently assuming that this frag should be | |
14316 | extended, then, the current address is two bytes | |
bdaaa2e1 | 14317 | higher. */ |
252b5132 RH |
14318 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
14319 | addr += 2; | |
14320 | ||
14321 | /* Ignore the low bit in the target, since it will be set | |
14322 | for a text label. */ | |
14323 | if ((val & 1) != 0) | |
14324 | --val; | |
14325 | } | |
14326 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
14327 | addr -= 4; | |
14328 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
14329 | addr -= 2; | |
14330 | ||
14331 | val -= addr & ~ ((1 << op->shift) - 1); | |
14332 | ||
14333 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
14334 | if (type == 'p' || type == 'q') | |
14335 | val /= 2; | |
14336 | ||
14337 | /* If any of the shifted bits are set, we must use an extended | |
14338 | opcode. If the address depends on the size of this | |
14339 | instruction, this can lead to a loop, so we arrange to always | |
14340 | use an extended opcode. We only check this when we are in | |
14341 | the main relaxation loop, when SEC is NULL. */ | |
14342 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
14343 | { | |
14344 | fragp->fr_subtype = | |
14345 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
14346 | return 1; | |
14347 | } | |
14348 | ||
14349 | /* If we are about to mark a frag as extended because the value | |
14350 | is precisely maxtiny + 1, then there is a chance of an | |
14351 | infinite loop as in the following code: | |
14352 | la $4,foo | |
14353 | .skip 1020 | |
14354 | .align 2 | |
14355 | foo: | |
14356 | In this case when the la is extended, foo is 0x3fc bytes | |
14357 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
14358 | the la must be extended. To avoid this loop, we mark the | |
14359 | frag as extended if it was small, and is about to become | |
14360 | extended with a value of maxtiny + 1. */ | |
14361 | if (val == ((maxtiny + 1) << op->shift) | |
14362 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
14363 | && sec == NULL) | |
14364 | { | |
14365 | fragp->fr_subtype = | |
14366 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
14367 | return 1; | |
14368 | } | |
14369 | } | |
14370 | else if (symsec != absolute_section && sec != NULL) | |
14371 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
14372 | ||
14373 | if ((val & ((1 << op->shift) - 1)) != 0 | |
14374 | || val < (mintiny << op->shift) | |
14375 | || val > (maxtiny << op->shift)) | |
14376 | return 1; | |
14377 | else | |
14378 | return 0; | |
14379 | } | |
14380 | ||
4a6a3df4 AO |
14381 | /* Compute the length of a branch sequence, and adjust the |
14382 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
14383 | worst-case length is computed, with UPDATE being used to indicate | |
14384 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
14385 | branch is to be computed. */ | |
14386 | static int | |
17a2f251 | 14387 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 14388 | { |
b34976b6 | 14389 | bfd_boolean toofar; |
4a6a3df4 AO |
14390 | int length; |
14391 | ||
14392 | if (fragp | |
14393 | && S_IS_DEFINED (fragp->fr_symbol) | |
14394 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
14395 | { | |
14396 | addressT addr; | |
14397 | offsetT val; | |
14398 | ||
14399 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
14400 | ||
14401 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
14402 | ||
14403 | val -= addr; | |
14404 | ||
14405 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
14406 | } | |
14407 | else if (fragp) | |
14408 | /* If the symbol is not defined or it's in a different segment, | |
14409 | assume the user knows what's going on and emit a short | |
14410 | branch. */ | |
b34976b6 | 14411 | toofar = FALSE; |
4a6a3df4 | 14412 | else |
b34976b6 | 14413 | toofar = TRUE; |
4a6a3df4 AO |
14414 | |
14415 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
14416 | fragp->fr_subtype | |
66b3e8da MR |
14417 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
14418 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
14419 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
14420 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
14421 | toofar); | |
14422 | ||
14423 | length = 4; | |
14424 | if (toofar) | |
14425 | { | |
14426 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
14427 | length += 8; | |
14428 | ||
14429 | if (mips_pic != NO_PIC) | |
14430 | { | |
14431 | /* Additional space for PIC loading of target address. */ | |
14432 | length += 8; | |
14433 | if (mips_opts.isa == ISA_MIPS1) | |
14434 | /* Additional space for $at-stabilizing nop. */ | |
14435 | length += 4; | |
14436 | } | |
14437 | ||
14438 | /* If branch is conditional. */ | |
14439 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
14440 | length += 8; | |
14441 | } | |
b34976b6 | 14442 | |
4a6a3df4 AO |
14443 | return length; |
14444 | } | |
14445 | ||
252b5132 RH |
14446 | /* Estimate the size of a frag before relaxing. Unless this is the |
14447 | mips16, we are not really relaxing here, and the final size is | |
14448 | encoded in the subtype information. For the mips16, we have to | |
14449 | decide whether we are using an extended opcode or not. */ | |
14450 | ||
252b5132 | 14451 | int |
17a2f251 | 14452 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 14453 | { |
5919d012 | 14454 | int change; |
252b5132 | 14455 | |
4a6a3df4 AO |
14456 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14457 | { | |
14458 | ||
b34976b6 AM |
14459 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
14460 | ||
4a6a3df4 AO |
14461 | return fragp->fr_var; |
14462 | } | |
14463 | ||
252b5132 | 14464 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
14465 | /* We don't want to modify the EXTENDED bit here; it might get us |
14466 | into infinite loops. We change it only in mips_relax_frag(). */ | |
14467 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
14468 | |
14469 | if (mips_pic == NO_PIC) | |
5919d012 | 14470 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 14471 | else if (mips_pic == SVR4_PIC) |
5919d012 | 14472 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
14473 | else if (mips_pic == VXWORKS_PIC) |
14474 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
14475 | change = 0; | |
252b5132 RH |
14476 | else |
14477 | abort (); | |
14478 | ||
14479 | if (change) | |
14480 | { | |
4d7206a2 | 14481 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 14482 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 14483 | } |
4d7206a2 RS |
14484 | else |
14485 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
14486 | } |
14487 | ||
14488 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 14489 | should be converted into a reloc against a section. */ |
252b5132 RH |
14490 | |
14491 | int | |
17a2f251 | 14492 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 14493 | { |
252b5132 RH |
14494 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
14495 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
14496 | return 0; | |
a161fe53 | 14497 | |
252b5132 RH |
14498 | if (fixp->fx_addsy == NULL) |
14499 | return 1; | |
a161fe53 | 14500 | |
de7e6852 RS |
14501 | /* If symbol SYM is in a mergeable section, relocations of the form |
14502 | SYM + 0 can usually be made section-relative. The mergeable data | |
14503 | is then identified by the section offset rather than by the symbol. | |
14504 | ||
14505 | However, if we're generating REL LO16 relocations, the offset is split | |
14506 | between the LO16 and parterning high part relocation. The linker will | |
14507 | need to recalculate the complete offset in order to correctly identify | |
14508 | the merge data. | |
14509 | ||
14510 | The linker has traditionally not looked for the parterning high part | |
14511 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
14512 | placed anywhere. Rather than break backwards compatibility by changing | |
14513 | this, it seems better not to force the issue, and instead keep the | |
14514 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 14515 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 14516 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
14517 | && HAVE_IN_PLACE_ADDENDS |
14518 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
14519 | return 0; | |
14520 | ||
ce70d90a MR |
14521 | /* There is no place to store an in-place offset for JALR relocations. |
14522 | Likewise an in-range offset of PC-relative relocations may overflow | |
14523 | the in-place relocatable field if recalculated against the start | |
14524 | address of the symbol's containing section. */ | |
14525 | if (HAVE_IN_PLACE_ADDENDS | |
14526 | && (fixp->fx_pcrel || fixp->fx_r_type == BFD_RELOC_MIPS_JALR)) | |
1180b5a4 RS |
14527 | return 0; |
14528 | ||
252b5132 | 14529 | #ifdef OBJ_ELF |
b314ec0e RS |
14530 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
14531 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
14532 | relocations against MIPS16 functions; in this case, the stub becomes | |
14533 | the function's canonical address. | |
14534 | ||
14535 | Floating-point stubs are stored in unique .mips16.call.* or | |
14536 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
14537 | the first relocation in section S must be against F; this is how the | |
14538 | linker determines the target function. All relocations that might | |
14539 | resolve to T must also be against F. We therefore have the following | |
14540 | restrictions, which are given in an intentionally-redundant way: | |
14541 | ||
14542 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
14543 | symbols. | |
14544 | ||
14545 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
14546 | if that stub might be used. | |
14547 | ||
14548 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
14549 | symbols. | |
14550 | ||
14551 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
14552 | that stub might be used. | |
14553 | ||
14554 | There is a further restriction: | |
14555 | ||
14556 | 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols | |
14557 | on targets with in-place addends; the relocation field cannot | |
14558 | encode the low bit. | |
14559 | ||
14560 | For simplicity, we deal with (3)-(5) by not reducing _any_ relocation | |
14561 | against a MIPS16 symbol. | |
14562 | ||
14563 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
14564 | relocation against some symbol R, no relocation against R may be | |
14565 | reduced. (Note that this deals with (2) as well as (1) because | |
14566 | relocations against global symbols will never be reduced on ELF | |
14567 | targets.) This approach is a little simpler than trying to detect | |
14568 | stub sections, and gives the "all or nothing" per-symbol consistency | |
14569 | that we have for MIPS16 symbols. */ | |
f43abd2b | 14570 | if (IS_ELF |
b314ec0e | 14571 | && fixp->fx_subsy == NULL |
30c09090 | 14572 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
b314ec0e | 14573 | || *symbol_get_tc (fixp->fx_addsy))) |
252b5132 RH |
14574 | return 0; |
14575 | #endif | |
a161fe53 | 14576 | |
252b5132 RH |
14577 | return 1; |
14578 | } | |
14579 | ||
14580 | /* Translate internal representation of relocation info to BFD target | |
14581 | format. */ | |
14582 | ||
14583 | arelent ** | |
17a2f251 | 14584 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
14585 | { |
14586 | static arelent *retval[4]; | |
14587 | arelent *reloc; | |
14588 | bfd_reloc_code_real_type code; | |
14589 | ||
4b0cff4e TS |
14590 | memset (retval, 0, sizeof(retval)); |
14591 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
14592 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
14593 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
14594 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
14595 | ||
bad36eac DJ |
14596 | if (fixp->fx_pcrel) |
14597 | { | |
9c2799c2 | 14598 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2); |
bad36eac DJ |
14599 | |
14600 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
14601 | Relocations want only the symbol offset. */ | |
14602 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 14603 | if (!IS_ELF) |
bad36eac DJ |
14604 | { |
14605 | /* A gruesome hack which is a result of the gruesome gas | |
14606 | reloc handling. What's worse, for COFF (as opposed to | |
14607 | ECOFF), we might need yet another copy of reloc->address. | |
14608 | See bfd_install_relocation. */ | |
14609 | reloc->addend += reloc->address; | |
14610 | } | |
14611 | } | |
14612 | else | |
14613 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 14614 | |
438c16b8 TS |
14615 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
14616 | entry to be used in the relocation's section offset. */ | |
14617 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
14618 | { |
14619 | reloc->address = reloc->addend; | |
14620 | reloc->addend = 0; | |
14621 | } | |
14622 | ||
252b5132 | 14623 | code = fixp->fx_r_type; |
252b5132 | 14624 | |
bad36eac | 14625 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
14626 | if (reloc->howto == NULL) |
14627 | { | |
14628 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14629 | _("Can not represent %s relocation in this object file format"), | |
14630 | bfd_get_reloc_code_name (code)); | |
14631 | retval[0] = NULL; | |
14632 | } | |
14633 | ||
14634 | return retval; | |
14635 | } | |
14636 | ||
14637 | /* Relax a machine dependent frag. This returns the amount by which | |
14638 | the current size of the frag should change. */ | |
14639 | ||
14640 | int | |
17a2f251 | 14641 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 14642 | { |
4a6a3df4 AO |
14643 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14644 | { | |
14645 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
14646 | |
14647 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
14648 | |
14649 | return fragp->fr_var - old_var; | |
14650 | } | |
14651 | ||
252b5132 RH |
14652 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
14653 | return 0; | |
14654 | ||
c4e7957c | 14655 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
14656 | { |
14657 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14658 | return 0; | |
14659 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
14660 | return 2; | |
14661 | } | |
14662 | else | |
14663 | { | |
14664 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14665 | return 0; | |
14666 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
14667 | return -2; | |
14668 | } | |
14669 | ||
14670 | return 0; | |
14671 | } | |
14672 | ||
14673 | /* Convert a machine dependent frag. */ | |
14674 | ||
14675 | void | |
17a2f251 | 14676 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 14677 | { |
4a6a3df4 AO |
14678 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14679 | { | |
14680 | bfd_byte *buf; | |
14681 | unsigned long insn; | |
14682 | expressionS exp; | |
14683 | fixS *fixp; | |
b34976b6 | 14684 | |
4a6a3df4 AO |
14685 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
14686 | ||
14687 | if (target_big_endian) | |
14688 | insn = bfd_getb32 (buf); | |
14689 | else | |
14690 | insn = bfd_getl32 (buf); | |
b34976b6 | 14691 | |
4a6a3df4 AO |
14692 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
14693 | { | |
14694 | /* We generate a fixup instead of applying it right now | |
14695 | because, if there are linker relaxations, we're going to | |
14696 | need the relocations. */ | |
14697 | exp.X_op = O_symbol; | |
14698 | exp.X_add_symbol = fragp->fr_symbol; | |
14699 | exp.X_add_number = fragp->fr_offset; | |
14700 | ||
14701 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14702 | 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
14703 | fixp->fx_file = fragp->fr_file; |
14704 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14705 | |
2132e3a3 | 14706 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14707 | buf += 4; |
14708 | } | |
14709 | else | |
14710 | { | |
14711 | int i; | |
14712 | ||
14713 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 14714 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
14715 | |
14716 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
14717 | goto uncond; | |
14718 | ||
14719 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14720 | { | |
14721 | /* Reverse the branch. */ | |
14722 | switch ((insn >> 28) & 0xf) | |
14723 | { | |
14724 | case 4: | |
14725 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
14726 | have the condition reversed by tweaking a single | |
14727 | bit, and their opcodes all have 0x4???????. */ | |
9c2799c2 | 14728 | gas_assert ((insn & 0xf1000000) == 0x41000000); |
4a6a3df4 AO |
14729 | insn ^= 0x00010000; |
14730 | break; | |
14731 | ||
14732 | case 0: | |
14733 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 14734 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 14735 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
14736 | insn ^= 0x00010000; |
14737 | break; | |
b34976b6 | 14738 | |
4a6a3df4 AO |
14739 | case 1: |
14740 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 14741 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
14742 | insn ^= 0x04000000; |
14743 | break; | |
14744 | ||
14745 | default: | |
14746 | abort (); | |
14747 | } | |
14748 | } | |
14749 | ||
14750 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
14751 | { | |
14752 | /* Clear the and-link bit. */ | |
9c2799c2 | 14753 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 14754 | |
54f4ddb3 TS |
14755 | /* bltzal 0x04100000 bgezal 0x04110000 |
14756 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
14757 | insn &= ~0x00100000; |
14758 | } | |
14759 | ||
14760 | /* Branch over the branch (if the branch was likely) or the | |
14761 | full jump (not likely case). Compute the offset from the | |
14762 | current instruction to branch to. */ | |
14763 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14764 | i = 16; | |
14765 | else | |
14766 | { | |
14767 | /* How many bytes in instructions we've already emitted? */ | |
14768 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
14769 | /* How many bytes in instructions from here to the end? */ | |
14770 | i = fragp->fr_var - i; | |
14771 | } | |
14772 | /* Convert to instruction count. */ | |
14773 | i >>= 2; | |
14774 | /* Branch counts from the next instruction. */ | |
b34976b6 | 14775 | i--; |
4a6a3df4 AO |
14776 | insn |= i; |
14777 | /* Branch over the jump. */ | |
2132e3a3 | 14778 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14779 | buf += 4; |
14780 | ||
54f4ddb3 | 14781 | /* nop */ |
2132e3a3 | 14782 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14783 | buf += 4; |
14784 | ||
14785 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14786 | { | |
14787 | /* beql $0, $0, 2f */ | |
14788 | insn = 0x50000000; | |
14789 | /* Compute the PC offset from the current instruction to | |
14790 | the end of the variable frag. */ | |
14791 | /* How many bytes in instructions we've already emitted? */ | |
14792 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
14793 | /* How many bytes in instructions from here to the end? */ | |
14794 | i = fragp->fr_var - i; | |
14795 | /* Convert to instruction count. */ | |
14796 | i >>= 2; | |
14797 | /* Don't decrement i, because we want to branch over the | |
14798 | delay slot. */ | |
14799 | ||
14800 | insn |= i; | |
2132e3a3 | 14801 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14802 | buf += 4; |
14803 | ||
2132e3a3 | 14804 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14805 | buf += 4; |
14806 | } | |
14807 | ||
14808 | uncond: | |
14809 | if (mips_pic == NO_PIC) | |
14810 | { | |
14811 | /* j or jal. */ | |
14812 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
14813 | ? 0x0c000000 : 0x08000000); | |
14814 | exp.X_op = O_symbol; | |
14815 | exp.X_add_symbol = fragp->fr_symbol; | |
14816 | exp.X_add_number = fragp->fr_offset; | |
14817 | ||
14818 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14819 | 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); |
4a6a3df4 AO |
14820 | fixp->fx_file = fragp->fr_file; |
14821 | fixp->fx_line = fragp->fr_line; | |
14822 | ||
2132e3a3 | 14823 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14824 | buf += 4; |
14825 | } | |
14826 | else | |
14827 | { | |
66b3e8da MR |
14828 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
14829 | ||
4a6a3df4 | 14830 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
14831 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
14832 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
14833 | exp.X_op = O_symbol; |
14834 | exp.X_add_symbol = fragp->fr_symbol; | |
14835 | exp.X_add_number = fragp->fr_offset; | |
14836 | ||
14837 | if (fragp->fr_offset) | |
14838 | { | |
14839 | exp.X_add_symbol = make_expr_symbol (&exp); | |
14840 | exp.X_add_number = 0; | |
14841 | } | |
14842 | ||
14843 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14844 | 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16); |
4a6a3df4 AO |
14845 | fixp->fx_file = fragp->fr_file; |
14846 | fixp->fx_line = fragp->fr_line; | |
14847 | ||
2132e3a3 | 14848 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 14849 | buf += 4; |
b34976b6 | 14850 | |
4a6a3df4 AO |
14851 | if (mips_opts.isa == ISA_MIPS1) |
14852 | { | |
14853 | /* nop */ | |
2132e3a3 | 14854 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14855 | buf += 4; |
14856 | } | |
14857 | ||
14858 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
14859 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
14860 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 AO |
14861 | |
14862 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14863 | 4, &exp, FALSE, BFD_RELOC_LO16); |
4a6a3df4 AO |
14864 | fixp->fx_file = fragp->fr_file; |
14865 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14866 | |
2132e3a3 | 14867 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14868 | buf += 4; |
14869 | ||
14870 | /* j(al)r $at. */ | |
14871 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 14872 | insn = 0x0000f809; |
4a6a3df4 | 14873 | else |
66b3e8da MR |
14874 | insn = 0x00000008; |
14875 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 14876 | |
2132e3a3 | 14877 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14878 | buf += 4; |
14879 | } | |
14880 | } | |
14881 | ||
9c2799c2 | 14882 | gas_assert (buf == (bfd_byte *)fragp->fr_literal |
4a6a3df4 AO |
14883 | + fragp->fr_fix + fragp->fr_var); |
14884 | ||
14885 | fragp->fr_fix += fragp->fr_var; | |
14886 | ||
14887 | return; | |
14888 | } | |
14889 | ||
252b5132 RH |
14890 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
14891 | { | |
14892 | int type; | |
3994f87e | 14893 | const struct mips16_immed_operand *op; |
b34976b6 | 14894 | bfd_boolean small, ext; |
252b5132 RH |
14895 | offsetT val; |
14896 | bfd_byte *buf; | |
14897 | unsigned long insn; | |
b34976b6 | 14898 | bfd_boolean use_extend; |
252b5132 RH |
14899 | unsigned short extend; |
14900 | ||
14901 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
14902 | op = mips16_immed_operands; | |
14903 | while (op->type != type) | |
14904 | ++op; | |
14905 | ||
14906 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14907 | { | |
b34976b6 AM |
14908 | small = FALSE; |
14909 | ext = TRUE; | |
252b5132 RH |
14910 | } |
14911 | else | |
14912 | { | |
b34976b6 AM |
14913 | small = TRUE; |
14914 | ext = FALSE; | |
252b5132 RH |
14915 | } |
14916 | ||
5f5f22c0 | 14917 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
14918 | if (op->pcrel) |
14919 | { | |
14920 | addressT addr; | |
14921 | ||
14922 | addr = fragp->fr_address + fragp->fr_fix; | |
14923 | ||
14924 | /* The rules for the base address of a PC relative reloc are | |
14925 | complicated; see mips16_extended_frag. */ | |
14926 | if (type == 'p' || type == 'q') | |
14927 | { | |
14928 | addr += 2; | |
14929 | if (ext) | |
14930 | addr += 2; | |
14931 | /* Ignore the low bit in the target, since it will be | |
14932 | set for a text label. */ | |
14933 | if ((val & 1) != 0) | |
14934 | --val; | |
14935 | } | |
14936 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
14937 | addr -= 4; | |
14938 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
14939 | addr -= 2; | |
14940 | ||
14941 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
14942 | val -= addr; | |
14943 | ||
14944 | /* Make sure the section winds up with the alignment we have | |
14945 | assumed. */ | |
14946 | if (op->shift > 0) | |
14947 | record_alignment (asec, op->shift); | |
14948 | } | |
14949 | ||
14950 | if (ext | |
14951 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
14952 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
14953 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
14954 | _("extended instruction in delay slot")); | |
14955 | ||
14956 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
14957 | ||
14958 | if (target_big_endian) | |
14959 | insn = bfd_getb16 (buf); | |
14960 | else | |
14961 | insn = bfd_getl16 (buf); | |
14962 | ||
14963 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
14964 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
14965 | small, ext, &insn, &use_extend, &extend); | |
14966 | ||
14967 | if (use_extend) | |
14968 | { | |
2132e3a3 | 14969 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
14970 | fragp->fr_fix += 2; |
14971 | buf += 2; | |
14972 | } | |
14973 | ||
2132e3a3 | 14974 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
14975 | fragp->fr_fix += 2; |
14976 | buf += 2; | |
14977 | } | |
14978 | else | |
14979 | { | |
4d7206a2 RS |
14980 | int first, second; |
14981 | fixS *fixp; | |
252b5132 | 14982 | |
4d7206a2 RS |
14983 | first = RELAX_FIRST (fragp->fr_subtype); |
14984 | second = RELAX_SECOND (fragp->fr_subtype); | |
14985 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 14986 | |
584892a6 RS |
14987 | /* Possibly emit a warning if we've chosen the longer option. */ |
14988 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
14989 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
14990 | { | |
14991 | const char *msg = macro_warning (fragp->fr_subtype); | |
14992 | if (msg != 0) | |
520725ea | 14993 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
584892a6 RS |
14994 | } |
14995 | ||
4d7206a2 RS |
14996 | /* Go through all the fixups for the first sequence. Disable them |
14997 | (by marking them as done) if we're going to use the second | |
14998 | sequence instead. */ | |
14999 | while (fixp | |
15000 | && fixp->fx_frag == fragp | |
15001 | && fixp->fx_where < fragp->fr_fix - second) | |
15002 | { | |
15003 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
15004 | fixp->fx_done = 1; | |
15005 | fixp = fixp->fx_next; | |
15006 | } | |
252b5132 | 15007 | |
4d7206a2 RS |
15008 | /* Go through the fixups for the second sequence. Disable them if |
15009 | we're going to use the first sequence, otherwise adjust their | |
15010 | addresses to account for the relaxation. */ | |
15011 | while (fixp && fixp->fx_frag == fragp) | |
15012 | { | |
15013 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
15014 | fixp->fx_where -= first; | |
15015 | else | |
15016 | fixp->fx_done = 1; | |
15017 | fixp = fixp->fx_next; | |
15018 | } | |
15019 | ||
15020 | /* Now modify the frag contents. */ | |
15021 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
15022 | { | |
15023 | char *start; | |
15024 | ||
15025 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
15026 | memmove (start, start + first, second); | |
15027 | fragp->fr_fix -= first; | |
15028 | } | |
15029 | else | |
15030 | fragp->fr_fix -= second; | |
252b5132 RH |
15031 | } |
15032 | } | |
15033 | ||
15034 | #ifdef OBJ_ELF | |
15035 | ||
15036 | /* This function is called after the relocs have been generated. | |
15037 | We've been storing mips16 text labels as odd. Here we convert them | |
15038 | back to even for the convenience of the debugger. */ | |
15039 | ||
15040 | void | |
17a2f251 | 15041 | mips_frob_file_after_relocs (void) |
252b5132 RH |
15042 | { |
15043 | asymbol **syms; | |
15044 | unsigned int count, i; | |
15045 | ||
f43abd2b | 15046 | if (!IS_ELF) |
252b5132 RH |
15047 | return; |
15048 | ||
15049 | syms = bfd_get_outsymbols (stdoutput); | |
15050 | count = bfd_get_symcount (stdoutput); | |
15051 | for (i = 0; i < count; i++, syms++) | |
15052 | { | |
30c09090 | 15053 | if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other) |
252b5132 RH |
15054 | && ((*syms)->value & 1) != 0) |
15055 | { | |
15056 | (*syms)->value &= ~1; | |
15057 | /* If the symbol has an odd size, it was probably computed | |
15058 | incorrectly, so adjust that as well. */ | |
15059 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
15060 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
15061 | } | |
15062 | } | |
15063 | } | |
15064 | ||
15065 | #endif | |
15066 | ||
a1facbec MR |
15067 | /* This function is called whenever a label is defined, including fake |
15068 | labels instantiated off the dot special symbol. It is used when | |
15069 | handling branch delays; if a branch has a label, we assume we cannot | |
15070 | move it. This also bumps the value of the symbol by 1 in compressed | |
15071 | code. */ | |
252b5132 RH |
15072 | |
15073 | void | |
a1facbec | 15074 | mips_record_label (symbolS *sym) |
252b5132 | 15075 | { |
a8dbcb85 | 15076 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
15077 | struct insn_label_list *l; |
15078 | ||
15079 | if (free_insn_labels == NULL) | |
15080 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
15081 | else | |
15082 | { | |
15083 | l = free_insn_labels; | |
15084 | free_insn_labels = l->next; | |
15085 | } | |
15086 | ||
15087 | l->label = sym; | |
a8dbcb85 TS |
15088 | l->next = si->label_list; |
15089 | si->label_list = l; | |
a1facbec | 15090 | } |
07a53e5c | 15091 | |
a1facbec MR |
15092 | /* This function is called as tc_frob_label() whenever a label is defined |
15093 | and adds a DWARF-2 record we only want for true labels. */ | |
15094 | ||
15095 | void | |
15096 | mips_define_label (symbolS *sym) | |
15097 | { | |
15098 | mips_record_label (sym); | |
07a53e5c RH |
15099 | #ifdef OBJ_ELF |
15100 | dwarf2_emit_label (sym); | |
15101 | #endif | |
252b5132 RH |
15102 | } |
15103 | \f | |
15104 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
15105 | ||
15106 | /* Some special processing for a MIPS ELF file. */ | |
15107 | ||
15108 | void | |
17a2f251 | 15109 | mips_elf_final_processing (void) |
252b5132 RH |
15110 | { |
15111 | /* Write out the register information. */ | |
316f5878 | 15112 | if (mips_abi != N64_ABI) |
252b5132 RH |
15113 | { |
15114 | Elf32_RegInfo s; | |
15115 | ||
15116 | s.ri_gprmask = mips_gprmask; | |
15117 | s.ri_cprmask[0] = mips_cprmask[0]; | |
15118 | s.ri_cprmask[1] = mips_cprmask[1]; | |
15119 | s.ri_cprmask[2] = mips_cprmask[2]; | |
15120 | s.ri_cprmask[3] = mips_cprmask[3]; | |
15121 | /* The gp_value field is set by the MIPS ELF backend. */ | |
15122 | ||
15123 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
15124 | ((Elf32_External_RegInfo *) | |
15125 | mips_regmask_frag)); | |
15126 | } | |
15127 | else | |
15128 | { | |
15129 | Elf64_Internal_RegInfo s; | |
15130 | ||
15131 | s.ri_gprmask = mips_gprmask; | |
15132 | s.ri_pad = 0; | |
15133 | s.ri_cprmask[0] = mips_cprmask[0]; | |
15134 | s.ri_cprmask[1] = mips_cprmask[1]; | |
15135 | s.ri_cprmask[2] = mips_cprmask[2]; | |
15136 | s.ri_cprmask[3] = mips_cprmask[3]; | |
15137 | /* The gp_value field is set by the MIPS ELF backend. */ | |
15138 | ||
15139 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
15140 | ((Elf64_External_RegInfo *) | |
15141 | mips_regmask_frag)); | |
15142 | } | |
15143 | ||
15144 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
15145 | sort of BFD interface for this. */ | |
15146 | if (mips_any_noreorder) | |
15147 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
15148 | if (mips_pic != NO_PIC) | |
143d77c5 | 15149 | { |
252b5132 | 15150 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
15151 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
15152 | } | |
15153 | if (mips_abicalls) | |
15154 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 15155 | |
98d3f06f | 15156 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
15157 | /* We may need to define a new flag for DSP ASE, and set this flag when |
15158 | file_ase_dsp is true. */ | |
8b082fb1 | 15159 | /* Same for DSP R2. */ |
ef2e4d86 CF |
15160 | /* We may need to define a new flag for MT ASE, and set this flag when |
15161 | file_ase_mt is true. */ | |
a4672219 TS |
15162 | if (file_ase_mips16) |
15163 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
15164 | #if 0 /* XXX FIXME */ |
15165 | if (file_ase_mips3d) | |
15166 | elf_elfheader (stdoutput)->e_flags |= ???; | |
15167 | #endif | |
deec1734 CD |
15168 | if (file_ase_mdmx) |
15169 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 15170 | |
bdaaa2e1 | 15171 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 15172 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 15173 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 15174 | else if (mips_abi == O64_ABI) |
252b5132 | 15175 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 15176 | else if (mips_abi == EABI_ABI) |
252b5132 | 15177 | { |
316f5878 | 15178 | if (!file_mips_gp32) |
252b5132 RH |
15179 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
15180 | else | |
15181 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
15182 | } | |
316f5878 | 15183 | else if (mips_abi == N32_ABI) |
be00bddd TS |
15184 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
15185 | ||
c9914766 | 15186 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
15187 | |
15188 | if (mips_32bitmode) | |
15189 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
15190 | |
15191 | #if 0 /* XXX FIXME */ | |
15192 | /* 32 bit code with 64 bit FP registers. */ | |
15193 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15194 | elf_elfheader (stdoutput)->e_flags |= ???; | |
15195 | #endif | |
252b5132 RH |
15196 | } |
15197 | ||
15198 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
15199 | \f | |
beae10d5 | 15200 | typedef struct proc { |
9b2f1d35 EC |
15201 | symbolS *func_sym; |
15202 | symbolS *func_end_sym; | |
beae10d5 KH |
15203 | unsigned long reg_mask; |
15204 | unsigned long reg_offset; | |
15205 | unsigned long fpreg_mask; | |
15206 | unsigned long fpreg_offset; | |
15207 | unsigned long frame_offset; | |
15208 | unsigned long frame_reg; | |
15209 | unsigned long pc_reg; | |
15210 | } procS; | |
252b5132 RH |
15211 | |
15212 | static procS cur_proc; | |
15213 | static procS *cur_proc_ptr; | |
15214 | static int numprocs; | |
15215 | ||
742a56fe RS |
15216 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal |
15217 | nop as "0". */ | |
15218 | ||
15219 | char | |
15220 | mips_nop_opcode (void) | |
15221 | { | |
15222 | return seg_info (now_seg)->tc_segment_info_data.mips16; | |
15223 | } | |
15224 | ||
15225 | /* Fill in an rs_align_code fragment. This only needs to do something | |
15226 | for MIPS16 code, where 0 is not a nop. */ | |
a19d8eb0 | 15227 | |
0a9ef439 | 15228 | void |
17a2f251 | 15229 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 15230 | { |
742a56fe | 15231 | char *p; |
c67a084a NC |
15232 | int bytes, size, excess; |
15233 | valueT opcode; | |
742a56fe | 15234 | |
0a9ef439 RH |
15235 | if (fragp->fr_type != rs_align_code) |
15236 | return; | |
15237 | ||
742a56fe RS |
15238 | p = fragp->fr_literal + fragp->fr_fix; |
15239 | if (*p) | |
a19d8eb0 | 15240 | { |
c67a084a NC |
15241 | opcode = mips16_nop_insn.insn_opcode; |
15242 | size = 2; | |
15243 | } | |
15244 | else | |
15245 | { | |
15246 | opcode = nop_insn.insn_opcode; | |
15247 | size = 4; | |
15248 | } | |
a19d8eb0 | 15249 | |
c67a084a NC |
15250 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
15251 | excess = bytes % size; | |
15252 | if (excess != 0) | |
15253 | { | |
15254 | /* If we're not inserting a whole number of instructions, | |
15255 | pad the end of the fixed part of the frag with zeros. */ | |
15256 | memset (p, 0, excess); | |
15257 | p += excess; | |
15258 | fragp->fr_fix += excess; | |
a19d8eb0 | 15259 | } |
c67a084a NC |
15260 | |
15261 | md_number_to_chars (p, opcode, size); | |
15262 | fragp->fr_var = size; | |
a19d8eb0 CP |
15263 | } |
15264 | ||
252b5132 | 15265 | static void |
17a2f251 | 15266 | md_obj_begin (void) |
252b5132 RH |
15267 | { |
15268 | } | |
15269 | ||
15270 | static void | |
17a2f251 | 15271 | md_obj_end (void) |
252b5132 | 15272 | { |
54f4ddb3 | 15273 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 15274 | if (cur_proc_ptr) |
9a41af64 | 15275 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
15276 | } |
15277 | ||
15278 | static long | |
17a2f251 | 15279 | get_number (void) |
252b5132 RH |
15280 | { |
15281 | int negative = 0; | |
15282 | long val = 0; | |
15283 | ||
15284 | if (*input_line_pointer == '-') | |
15285 | { | |
15286 | ++input_line_pointer; | |
15287 | negative = 1; | |
15288 | } | |
3882b010 | 15289 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 15290 | as_bad (_("expected simple number")); |
252b5132 RH |
15291 | if (input_line_pointer[0] == '0') |
15292 | { | |
15293 | if (input_line_pointer[1] == 'x') | |
15294 | { | |
15295 | input_line_pointer += 2; | |
3882b010 | 15296 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
15297 | { |
15298 | val <<= 4; | |
15299 | val |= hex_value (*input_line_pointer++); | |
15300 | } | |
15301 | return negative ? -val : val; | |
15302 | } | |
15303 | else | |
15304 | { | |
15305 | ++input_line_pointer; | |
3882b010 | 15306 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
15307 | { |
15308 | val <<= 3; | |
15309 | val |= *input_line_pointer++ - '0'; | |
15310 | } | |
15311 | return negative ? -val : val; | |
15312 | } | |
15313 | } | |
3882b010 | 15314 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
15315 | { |
15316 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
15317 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 15318 | as_warn (_("invalid number")); |
252b5132 RH |
15319 | return -1; |
15320 | } | |
3882b010 | 15321 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
15322 | { |
15323 | val *= 10; | |
15324 | val += *input_line_pointer++ - '0'; | |
15325 | } | |
15326 | return negative ? -val : val; | |
15327 | } | |
15328 | ||
15329 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
15330 | is an initial number which is the ECOFF file index. In the non-ECOFF |
15331 | case .file implies DWARF-2. */ | |
15332 | ||
15333 | static void | |
17a2f251 | 15334 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 15335 | { |
ecb4347a DJ |
15336 | static int first_file_directive = 0; |
15337 | ||
c5dd6aab DJ |
15338 | if (ECOFF_DEBUGGING) |
15339 | { | |
15340 | get_number (); | |
15341 | s_app_file (0); | |
15342 | } | |
15343 | else | |
ecb4347a DJ |
15344 | { |
15345 | char *filename; | |
15346 | ||
15347 | filename = dwarf2_directive_file (0); | |
15348 | ||
15349 | /* Versions of GCC up to 3.1 start files with a ".file" | |
15350 | directive even for stabs output. Make sure that this | |
15351 | ".file" is handled. Note that you need a version of GCC | |
15352 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
15353 | if (filename != NULL && ! first_file_directive) | |
15354 | { | |
15355 | (void) new_logical_line (filename, -1); | |
c04f5787 | 15356 | s_app_file_string (filename, 0); |
ecb4347a DJ |
15357 | } |
15358 | first_file_directive = 1; | |
15359 | } | |
c5dd6aab DJ |
15360 | } |
15361 | ||
15362 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
15363 | |
15364 | static void | |
17a2f251 | 15365 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 15366 | { |
c5dd6aab DJ |
15367 | if (!ECOFF_DEBUGGING) |
15368 | dwarf2_directive_loc (0); | |
252b5132 RH |
15369 | } |
15370 | ||
252b5132 RH |
15371 | /* The .end directive. */ |
15372 | ||
15373 | static void | |
17a2f251 | 15374 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15375 | { |
15376 | symbolS *p; | |
252b5132 | 15377 | |
7a621144 DJ |
15378 | /* Following functions need their own .frame and .cprestore directives. */ |
15379 | mips_frame_reg_valid = 0; | |
15380 | mips_cprestore_valid = 0; | |
15381 | ||
252b5132 RH |
15382 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
15383 | { | |
15384 | p = get_symbol (); | |
15385 | demand_empty_rest_of_line (); | |
15386 | } | |
15387 | else | |
15388 | p = NULL; | |
15389 | ||
14949570 | 15390 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
15391 | as_warn (_(".end not in text section")); |
15392 | ||
15393 | if (!cur_proc_ptr) | |
15394 | { | |
15395 | as_warn (_(".end directive without a preceding .ent directive.")); | |
15396 | demand_empty_rest_of_line (); | |
15397 | return; | |
15398 | } | |
15399 | ||
15400 | if (p != NULL) | |
15401 | { | |
9c2799c2 | 15402 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 15403 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 15404 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
15405 | |
15406 | if (debug_type == DEBUG_STABS) | |
15407 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
15408 | S_GET_NAME (p)); | |
252b5132 RH |
15409 | } |
15410 | else | |
15411 | as_warn (_(".end directive missing or unknown symbol")); | |
15412 | ||
2132e3a3 | 15413 | #ifdef OBJ_ELF |
9b2f1d35 EC |
15414 | /* Create an expression to calculate the size of the function. */ |
15415 | if (p && cur_proc_ptr) | |
15416 | { | |
15417 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
15418 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
15419 | ||
15420 | obj->size = exp; | |
15421 | exp->X_op = O_subtract; | |
15422 | exp->X_add_symbol = symbol_temp_new_now (); | |
15423 | exp->X_op_symbol = p; | |
15424 | exp->X_add_number = 0; | |
15425 | ||
15426 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
15427 | } | |
15428 | ||
ecb4347a | 15429 | /* Generate a .pdr section. */ |
f43abd2b | 15430 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
15431 | { |
15432 | segT saved_seg = now_seg; | |
15433 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
15434 | expressionS exp; |
15435 | char *fragp; | |
252b5132 | 15436 | |
252b5132 | 15437 | #ifdef md_flush_pending_output |
ecb4347a | 15438 | md_flush_pending_output (); |
252b5132 RH |
15439 | #endif |
15440 | ||
9c2799c2 | 15441 | gas_assert (pdr_seg); |
ecb4347a | 15442 | subseg_set (pdr_seg, 0); |
252b5132 | 15443 | |
ecb4347a DJ |
15444 | /* Write the symbol. */ |
15445 | exp.X_op = O_symbol; | |
15446 | exp.X_add_symbol = p; | |
15447 | exp.X_add_number = 0; | |
15448 | emit_expr (&exp, 4); | |
252b5132 | 15449 | |
ecb4347a | 15450 | fragp = frag_more (7 * 4); |
252b5132 | 15451 | |
17a2f251 TS |
15452 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
15453 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
15454 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
15455 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
15456 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
15457 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
15458 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 15459 | |
ecb4347a DJ |
15460 | subseg_set (saved_seg, saved_subseg); |
15461 | } | |
15462 | #endif /* OBJ_ELF */ | |
252b5132 RH |
15463 | |
15464 | cur_proc_ptr = NULL; | |
15465 | } | |
15466 | ||
15467 | /* The .aent and .ent directives. */ | |
15468 | ||
15469 | static void | |
17a2f251 | 15470 | s_mips_ent (int aent) |
252b5132 | 15471 | { |
252b5132 | 15472 | symbolS *symbolP; |
252b5132 RH |
15473 | |
15474 | symbolP = get_symbol (); | |
15475 | if (*input_line_pointer == ',') | |
f9419b05 | 15476 | ++input_line_pointer; |
252b5132 | 15477 | SKIP_WHITESPACE (); |
3882b010 | 15478 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 15479 | || *input_line_pointer == '-') |
874e8986 | 15480 | get_number (); |
252b5132 | 15481 | |
14949570 | 15482 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
15483 | as_warn (_(".ent or .aent not in text section.")); |
15484 | ||
15485 | if (!aent && cur_proc_ptr) | |
9a41af64 | 15486 | as_warn (_("missing .end")); |
252b5132 RH |
15487 | |
15488 | if (!aent) | |
15489 | { | |
7a621144 DJ |
15490 | /* This function needs its own .frame and .cprestore directives. */ |
15491 | mips_frame_reg_valid = 0; | |
15492 | mips_cprestore_valid = 0; | |
15493 | ||
252b5132 RH |
15494 | cur_proc_ptr = &cur_proc; |
15495 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
15496 | ||
9b2f1d35 | 15497 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 15498 | |
f9419b05 | 15499 | ++numprocs; |
ecb4347a DJ |
15500 | |
15501 | if (debug_type == DEBUG_STABS) | |
15502 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
15503 | S_GET_NAME (symbolP)); | |
252b5132 RH |
15504 | } |
15505 | ||
7c0fc524 MR |
15506 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
15507 | ||
252b5132 RH |
15508 | demand_empty_rest_of_line (); |
15509 | } | |
15510 | ||
15511 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 15512 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 15513 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 15514 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
15515 | symbol table (in the mdebug section). */ |
15516 | ||
15517 | static void | |
17a2f251 | 15518 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 15519 | { |
ecb4347a | 15520 | #ifdef OBJ_ELF |
f43abd2b | 15521 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
15522 | { |
15523 | long val; | |
252b5132 | 15524 | |
ecb4347a DJ |
15525 | if (cur_proc_ptr == (procS *) NULL) |
15526 | { | |
15527 | as_warn (_(".frame outside of .ent")); | |
15528 | demand_empty_rest_of_line (); | |
15529 | return; | |
15530 | } | |
252b5132 | 15531 | |
ecb4347a DJ |
15532 | cur_proc_ptr->frame_reg = tc_get_register (1); |
15533 | ||
15534 | SKIP_WHITESPACE (); | |
15535 | if (*input_line_pointer++ != ',' | |
15536 | || get_absolute_expression_and_terminator (&val) != ',') | |
15537 | { | |
15538 | as_warn (_("Bad .frame directive")); | |
15539 | --input_line_pointer; | |
15540 | demand_empty_rest_of_line (); | |
15541 | return; | |
15542 | } | |
252b5132 | 15543 | |
ecb4347a DJ |
15544 | cur_proc_ptr->frame_offset = val; |
15545 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 15546 | |
252b5132 | 15547 | demand_empty_rest_of_line (); |
252b5132 | 15548 | } |
ecb4347a DJ |
15549 | else |
15550 | #endif /* OBJ_ELF */ | |
15551 | s_ignore (ignore); | |
252b5132 RH |
15552 | } |
15553 | ||
bdaaa2e1 KH |
15554 | /* The .fmask and .mask directives. If the mdebug section is present |
15555 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 15556 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 15557 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
15558 | make reference to the ecoff symbol table (in the mdebug section). */ |
15559 | ||
15560 | static void | |
17a2f251 | 15561 | s_mips_mask (int reg_type) |
252b5132 | 15562 | { |
ecb4347a | 15563 | #ifdef OBJ_ELF |
f43abd2b | 15564 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 15565 | { |
ecb4347a | 15566 | long mask, off; |
252b5132 | 15567 | |
ecb4347a DJ |
15568 | if (cur_proc_ptr == (procS *) NULL) |
15569 | { | |
15570 | as_warn (_(".mask/.fmask outside of .ent")); | |
15571 | demand_empty_rest_of_line (); | |
15572 | return; | |
15573 | } | |
252b5132 | 15574 | |
ecb4347a DJ |
15575 | if (get_absolute_expression_and_terminator (&mask) != ',') |
15576 | { | |
15577 | as_warn (_("Bad .mask/.fmask directive")); | |
15578 | --input_line_pointer; | |
15579 | demand_empty_rest_of_line (); | |
15580 | return; | |
15581 | } | |
252b5132 | 15582 | |
ecb4347a DJ |
15583 | off = get_absolute_expression (); |
15584 | ||
15585 | if (reg_type == 'F') | |
15586 | { | |
15587 | cur_proc_ptr->fpreg_mask = mask; | |
15588 | cur_proc_ptr->fpreg_offset = off; | |
15589 | } | |
15590 | else | |
15591 | { | |
15592 | cur_proc_ptr->reg_mask = mask; | |
15593 | cur_proc_ptr->reg_offset = off; | |
15594 | } | |
15595 | ||
15596 | demand_empty_rest_of_line (); | |
252b5132 RH |
15597 | } |
15598 | else | |
ecb4347a DJ |
15599 | #endif /* OBJ_ELF */ |
15600 | s_ignore (reg_type); | |
252b5132 RH |
15601 | } |
15602 | ||
316f5878 RS |
15603 | /* A table describing all the processors gas knows about. Names are |
15604 | matched in the order listed. | |
e7af610e | 15605 | |
316f5878 RS |
15606 | To ease comparison, please keep this table in the same order as |
15607 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
15608 | static const struct mips_cpu_info mips_cpu_info_table[] = |
15609 | { | |
316f5878 | 15610 | /* Entries for generic ISAs */ |
ad3fea08 TS |
15611 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
15612 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
15613 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
15614 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
15615 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
15616 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
15617 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15618 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
15619 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
15620 | |
15621 | /* MIPS I */ | |
ad3fea08 TS |
15622 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
15623 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
15624 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
15625 | |
15626 | /* MIPS II */ | |
ad3fea08 | 15627 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
15628 | |
15629 | /* MIPS III */ | |
ad3fea08 TS |
15630 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
15631 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
15632 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
15633 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
15634 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
15635 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
15636 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
15637 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
15638 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
15639 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
15640 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
15641 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
b15591bb AN |
15642 | /* ST Microelectronics Loongson 2E and 2F cores */ |
15643 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
15644 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
15645 | |
15646 | /* MIPS IV */ | |
ad3fea08 TS |
15647 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
15648 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
15649 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
3aa3176b TS |
15650 | { "r14000", 0, ISA_MIPS4, CPU_R14000 }, |
15651 | { "r16000", 0, ISA_MIPS4, CPU_R16000 }, | |
ad3fea08 TS |
15652 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
15653 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
15654 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
15655 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
15656 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
15657 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
15658 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
15659 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
15660 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
15661 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
15662 | |
15663 | /* MIPS 32 */ | |
ad3fea08 TS |
15664 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
15665 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
15666 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
15667 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
15668 | ||
15669 | /* MIPS 32 Release 2 */ | |
15670 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15671 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15672 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15673 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15674 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15675 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 15676 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 15677 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 15678 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
15679 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
15680 | /* Deprecated forms of the above. */ | |
15681 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 15682 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 15683 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 15684 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 15685 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 15686 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
15687 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
15688 | /* Deprecated forms of the above. */ | |
15689 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 15690 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 15691 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
15692 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15693 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15694 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15695 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
15696 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15697 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15698 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15699 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15700 | /* Deprecated forms of the above. */ | |
15701 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15702 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
15703 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15704 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15705 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
15706 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15707 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15708 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15709 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15710 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15711 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15712 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15713 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15714 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15715 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15716 | /* Deprecated forms of the above. */ | |
15717 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15718 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15719 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15720 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a SL |
15721 | /* 1004K cores are multiprocessor versions of the 34K. */ |
15722 | { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15723 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15724 | { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15725 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15726 | { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15727 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15728 | { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15729 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 15730 | |
316f5878 | 15731 | /* MIPS 64 */ |
ad3fea08 TS |
15732 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
15733 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
15734 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 15735 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 | 15736 | |
c7a23324 | 15737 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
15738 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
15739 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
15740 | /* Broadcom SB-1A CPU core */ |
15741 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
15742 | ISA_MIPS64, CPU_SB1 }, | |
d051516a NC |
15743 | |
15744 | { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A }, | |
e7af610e | 15745 | |
ed163775 MR |
15746 | /* MIPS 64 Release 2 */ |
15747 | ||
967344c6 AN |
15748 | /* Cavium Networks Octeon CPU core */ |
15749 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
15750 | ||
52b6b6b9 JM |
15751 | /* RMI Xlr */ |
15752 | { "xlr", 0, ISA_MIPS64, CPU_XLR }, | |
15753 | ||
316f5878 RS |
15754 | /* End marker */ |
15755 | { NULL, 0, 0, 0 } | |
15756 | }; | |
e7af610e | 15757 | |
84ea6cf2 | 15758 | |
316f5878 RS |
15759 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
15760 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 15761 | |
316f5878 | 15762 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 15763 | |
b34976b6 | 15764 | static bfd_boolean |
17a2f251 | 15765 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
15766 | { |
15767 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
15768 | given++, canonical++; | |
15769 | ||
15770 | return ((*given == 0 && *canonical == 0) | |
15771 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
15772 | } | |
15773 | ||
15774 | ||
15775 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
15776 | CPU name. We've traditionally allowed a lot of variation here. | |
15777 | ||
15778 | Note: this function is shared between GCC and GAS. */ | |
15779 | ||
b34976b6 | 15780 | static bfd_boolean |
17a2f251 | 15781 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
15782 | { |
15783 | /* First see if the name matches exactly, or with a final "000" | |
15784 | turned into "k". */ | |
15785 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 15786 | return TRUE; |
316f5878 RS |
15787 | |
15788 | /* If not, try comparing based on numerical designation alone. | |
15789 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
15790 | if (TOLOWER (*given) == 'r') | |
15791 | given++; | |
15792 | if (!ISDIGIT (*given)) | |
b34976b6 | 15793 | return FALSE; |
316f5878 RS |
15794 | |
15795 | /* Skip over some well-known prefixes in the canonical name, | |
15796 | hoping to find a number there too. */ | |
15797 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
15798 | canonical += 2; | |
15799 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
15800 | canonical += 2; | |
15801 | else if (TOLOWER (canonical[0]) == 'r') | |
15802 | canonical += 1; | |
15803 | ||
15804 | return mips_strict_matching_cpu_name_p (canonical, given); | |
15805 | } | |
15806 | ||
15807 | ||
15808 | /* Parse an option that takes the name of a processor as its argument. | |
15809 | OPTION is the name of the option and CPU_STRING is the argument. | |
15810 | Return the corresponding processor enumeration if the CPU_STRING is | |
15811 | recognized, otherwise report an error and return null. | |
15812 | ||
15813 | A similar function exists in GCC. */ | |
e7af610e NC |
15814 | |
15815 | static const struct mips_cpu_info * | |
17a2f251 | 15816 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 15817 | { |
316f5878 | 15818 | const struct mips_cpu_info *p; |
e7af610e | 15819 | |
316f5878 RS |
15820 | /* 'from-abi' selects the most compatible architecture for the given |
15821 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
15822 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
15823 | version. Look first at the -mgp options, if given, otherwise base | |
15824 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 15825 | |
316f5878 RS |
15826 | Treat NO_ABI like the EABIs. One reason to do this is that the |
15827 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
15828 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
15829 | 'mips64', just as we did in the days before 'from-abi'. */ | |
15830 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
15831 | { | |
15832 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15833 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
15834 | ||
15835 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15836 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
15837 | ||
15838 | if (file_mips_gp32 >= 0) | |
15839 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
15840 | ||
15841 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
15842 | ? ISA_MIPS3 | |
15843 | : ISA_MIPS1); | |
15844 | } | |
15845 | ||
15846 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
15847 | if (strcasecmp (cpu_string, "default") == 0) | |
15848 | return 0; | |
15849 | ||
15850 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
15851 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
15852 | return p; | |
15853 | ||
20203fb9 | 15854 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 15855 | return 0; |
e7af610e NC |
15856 | } |
15857 | ||
316f5878 RS |
15858 | /* Return the canonical processor information for ISA (a member of the |
15859 | ISA_MIPS* enumeration). */ | |
15860 | ||
e7af610e | 15861 | static const struct mips_cpu_info * |
17a2f251 | 15862 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
15863 | { |
15864 | int i; | |
15865 | ||
15866 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 15867 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 15868 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
15869 | return (&mips_cpu_info_table[i]); |
15870 | ||
e972090a | 15871 | return NULL; |
e7af610e | 15872 | } |
fef14a42 TS |
15873 | |
15874 | static const struct mips_cpu_info * | |
17a2f251 | 15875 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
15876 | { |
15877 | int i; | |
15878 | ||
15879 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
15880 | if (arch == mips_cpu_info_table[i].cpu) | |
15881 | return (&mips_cpu_info_table[i]); | |
15882 | ||
15883 | return NULL; | |
15884 | } | |
316f5878 RS |
15885 | \f |
15886 | static void | |
17a2f251 | 15887 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
15888 | { |
15889 | if (*first_p) | |
15890 | { | |
15891 | fprintf (stream, "%24s", ""); | |
15892 | *col_p = 24; | |
15893 | } | |
15894 | else | |
15895 | { | |
15896 | fprintf (stream, ", "); | |
15897 | *col_p += 2; | |
15898 | } | |
e7af610e | 15899 | |
316f5878 RS |
15900 | if (*col_p + strlen (string) > 72) |
15901 | { | |
15902 | fprintf (stream, "\n%24s", ""); | |
15903 | *col_p = 24; | |
15904 | } | |
15905 | ||
15906 | fprintf (stream, "%s", string); | |
15907 | *col_p += strlen (string); | |
15908 | ||
15909 | *first_p = 0; | |
15910 | } | |
15911 | ||
15912 | void | |
17a2f251 | 15913 | md_show_usage (FILE *stream) |
e7af610e | 15914 | { |
316f5878 RS |
15915 | int column, first; |
15916 | size_t i; | |
15917 | ||
15918 | fprintf (stream, _("\ | |
15919 | MIPS options:\n\ | |
316f5878 RS |
15920 | -EB generate big endian output\n\ |
15921 | -EL generate little endian output\n\ | |
15922 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
15923 | -G NUM allow referencing objects up to NUM bytes\n\ | |
15924 | implicitly with the gp register [default 8]\n")); | |
15925 | fprintf (stream, _("\ | |
15926 | -mips1 generate MIPS ISA I instructions\n\ | |
15927 | -mips2 generate MIPS ISA II instructions\n\ | |
15928 | -mips3 generate MIPS ISA III instructions\n\ | |
15929 | -mips4 generate MIPS ISA IV instructions\n\ | |
15930 | -mips5 generate MIPS ISA V instructions\n\ | |
15931 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 15932 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 15933 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 15934 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
15935 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
15936 | ||
15937 | first = 1; | |
e7af610e NC |
15938 | |
15939 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
15940 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
15941 | show (stream, "from-abi", &column, &first); | |
15942 | fputc ('\n', stream); | |
e7af610e | 15943 | |
316f5878 RS |
15944 | fprintf (stream, _("\ |
15945 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
15946 | -no-mCPU don't generate code specific to CPU.\n\ | |
15947 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
15948 | ||
15949 | first = 1; | |
15950 | ||
15951 | show (stream, "3900", &column, &first); | |
15952 | show (stream, "4010", &column, &first); | |
15953 | show (stream, "4100", &column, &first); | |
15954 | show (stream, "4650", &column, &first); | |
15955 | fputc ('\n', stream); | |
15956 | ||
15957 | fprintf (stream, _("\ | |
15958 | -mips16 generate mips16 instructions\n\ | |
15959 | -no-mips16 do not generate mips16 instructions\n")); | |
15960 | fprintf (stream, _("\ | |
e16bfa71 TS |
15961 | -msmartmips generate smartmips instructions\n\ |
15962 | -mno-smartmips do not generate smartmips instructions\n")); | |
15963 | fprintf (stream, _("\ | |
74cd071d CF |
15964 | -mdsp generate DSP instructions\n\ |
15965 | -mno-dsp do not generate DSP instructions\n")); | |
15966 | fprintf (stream, _("\ | |
8b082fb1 TS |
15967 | -mdspr2 generate DSP R2 instructions\n\ |
15968 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
15969 | fprintf (stream, _("\ | |
ef2e4d86 CF |
15970 | -mmt generate MT instructions\n\ |
15971 | -mno-mt do not generate MT instructions\n")); | |
15972 | fprintf (stream, _("\ | |
c67a084a NC |
15973 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
15974 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 15975 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 15976 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 15977 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 15978 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
15979 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
15980 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 15981 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
15982 | -O0 remove unneeded NOPs, do not swap branches\n\ |
15983 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
15984 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
15985 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
15986 | fprintf (stream, _("\ |
15987 | -mhard-float allow floating-point instructions\n\ | |
15988 | -msoft-float do not allow floating-point instructions\n\ | |
15989 | -msingle-float only allow 32-bit floating-point operations\n\ | |
15990 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
15991 | --[no-]construct-floats [dis]allow floating point values to be constructed\n" | |
15992 | )); | |
316f5878 RS |
15993 | #ifdef OBJ_ELF |
15994 | fprintf (stream, _("\ | |
15995 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 15996 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 15997 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 15998 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 15999 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 16000 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 16001 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 16002 | position dependent (non shared) code\n\ |
316f5878 RS |
16003 | -mabi=ABI create ABI conformant object file for:\n")); |
16004 | ||
16005 | first = 1; | |
16006 | ||
16007 | show (stream, "32", &column, &first); | |
16008 | show (stream, "o64", &column, &first); | |
16009 | show (stream, "n32", &column, &first); | |
16010 | show (stream, "64", &column, &first); | |
16011 | show (stream, "eabi", &column, &first); | |
16012 | ||
16013 | fputc ('\n', stream); | |
16014 | ||
16015 | fprintf (stream, _("\ | |
16016 | -32 create o32 ABI object file (default)\n\ | |
16017 | -n32 create n32 ABI object file\n\ | |
16018 | -64 create 64 ABI object file\n")); | |
16019 | #endif | |
e7af610e | 16020 | } |
14e777e0 | 16021 | |
1575952e | 16022 | #ifdef TE_IRIX |
14e777e0 | 16023 | enum dwarf2_format |
413a266c | 16024 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 16025 | { |
369943fe | 16026 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 16027 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
16028 | else |
16029 | return dwarf2_format_32bit; | |
16030 | } | |
1575952e | 16031 | #endif |
73369e65 EC |
16032 | |
16033 | int | |
16034 | mips_dwarf2_addr_size (void) | |
16035 | { | |
6b6b3450 | 16036 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 16037 | return 8; |
73369e65 EC |
16038 | else |
16039 | return 4; | |
16040 | } | |
5862107c EC |
16041 | |
16042 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
16043 | void | |
16044 | mips_cfi_frame_initial_instructions (void) | |
16045 | { | |
16046 | cfi_add_CFA_def_cfa_register (SP); | |
16047 | } | |
16048 | ||
707bfff6 TS |
16049 | int |
16050 | tc_mips_regname_to_dw2regnum (char *regname) | |
16051 | { | |
16052 | unsigned int regnum = -1; | |
16053 | unsigned int reg; | |
16054 | ||
16055 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
16056 | regnum = reg; | |
16057 | ||
16058 | return regnum; | |
16059 | } |