Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
b3adc24a | 2 | Copyright (C) 1993-2020 Free Software Foundation, Inc. |
252b5132 RH |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
6 | Support. | |
7 | ||
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 12 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
13 | any later version. |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
22 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
23 | 02110-1301, USA. */ | |
252b5132 RH |
24 | |
25 | #include "as.h" | |
26 | #include "config.h" | |
27 | #include "subsegs.h" | |
3882b010 | 28 | #include "safe-ctype.h" |
252b5132 | 29 | |
252b5132 RH |
30 | #include "opcode/mips.h" |
31 | #include "itbl-ops.h" | |
c5dd6aab | 32 | #include "dwarf2dbg.h" |
5862107c | 33 | #include "dw2gencfi.h" |
252b5132 | 34 | |
42429eac RS |
35 | /* Check assumptions made in this file. */ |
36 | typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1]; | |
37 | typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1]; | |
38 | ||
252b5132 RH |
39 | #ifdef DEBUG |
40 | #define DBG(x) printf x | |
41 | #else | |
42 | #define DBG(x) | |
43 | #endif | |
44 | ||
263b2574 | 45 | #define streq(a, b) (strcmp (a, b) == 0) |
46 | ||
9e12b7a2 RS |
47 | #define SKIP_SPACE_TABS(S) \ |
48 | do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0) | |
49 | ||
252b5132 | 50 | /* Clean up namespace so we can include obj-elf.h too. */ |
17a2f251 TS |
51 | static int mips_output_flavor (void); |
52 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
53 | #undef OBJ_PROCESS_STAB |
54 | #undef OUTPUT_FLAVOR | |
55 | #undef S_GET_ALIGN | |
56 | #undef S_GET_SIZE | |
57 | #undef S_SET_ALIGN | |
58 | #undef S_SET_SIZE | |
252b5132 RH |
59 | #undef obj_frob_file |
60 | #undef obj_frob_file_after_relocs | |
61 | #undef obj_frob_symbol | |
62 | #undef obj_pop_insert | |
63 | #undef obj_sec_sym_ok_for_reloc | |
64 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
65 | ||
66 | #include "obj-elf.h" | |
67 | /* Fix any of them that we actually care about. */ | |
68 | #undef OUTPUT_FLAVOR | |
69 | #define OUTPUT_FLAVOR mips_output_flavor() | |
252b5132 | 70 | |
252b5132 | 71 | #include "elf/mips.h" |
252b5132 RH |
72 | |
73 | #ifndef ECOFF_DEBUGGING | |
74 | #define NO_ECOFF_DEBUGGING | |
75 | #define ECOFF_DEBUGGING 0 | |
76 | #endif | |
77 | ||
ecb4347a DJ |
78 | int mips_flag_mdebug = -1; |
79 | ||
dcd410fe RO |
80 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
81 | linker doesn't know about and discards them, but relocations against them | |
82 | remain, leading to rld crashes. */ | |
83 | #ifdef TE_IRIX | |
84 | int mips_flag_pdr = FALSE; | |
85 | #else | |
86 | int mips_flag_pdr = TRUE; | |
87 | #endif | |
88 | ||
252b5132 RH |
89 | #include "ecoff.h" |
90 | ||
252b5132 | 91 | static char *mips_regmask_frag; |
351cdf24 | 92 | static char *mips_flags_frag; |
252b5132 | 93 | |
85b51719 | 94 | #define ZERO 0 |
741fe287 | 95 | #define ATREG 1 |
df58fc94 RS |
96 | #define S0 16 |
97 | #define S7 23 | |
252b5132 RH |
98 | #define TREG 24 |
99 | #define PIC_CALL_REG 25 | |
100 | #define KT0 26 | |
101 | #define KT1 27 | |
102 | #define GP 28 | |
103 | #define SP 29 | |
104 | #define FP 30 | |
105 | #define RA 31 | |
106 | ||
107 | #define ILLEGAL_REG (32) | |
108 | ||
741fe287 MR |
109 | #define AT mips_opts.at |
110 | ||
252b5132 RH |
111 | extern int target_big_endian; |
112 | ||
252b5132 | 113 | /* The name of the readonly data section. */ |
e8044f35 | 114 | #define RDATA_SECTION_NAME ".rodata" |
252b5132 | 115 | |
a4e06468 RS |
116 | /* Ways in which an instruction can be "appended" to the output. */ |
117 | enum append_method { | |
118 | /* Just add it normally. */ | |
119 | APPEND_ADD, | |
120 | ||
121 | /* Add it normally and then add a nop. */ | |
122 | APPEND_ADD_WITH_NOP, | |
123 | ||
124 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
125 | APPEND_ADD_COMPACT, | |
126 | ||
127 | /* Insert the instruction before the last one. */ | |
128 | APPEND_SWAP | |
129 | }; | |
130 | ||
47e39b9d RS |
131 | /* Information about an instruction, including its format, operands |
132 | and fixups. */ | |
133 | struct mips_cl_insn | |
134 | { | |
135 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
136 | const struct mips_opcode *insn_mo; | |
137 | ||
47e39b9d | 138 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
139 | a copy of INSN_MO->match with the operands filled in. If we have |
140 | decided to use an extended MIPS16 instruction, this includes the | |
141 | extension. */ | |
47e39b9d RS |
142 | unsigned long insn_opcode; |
143 | ||
6f2117ba PH |
144 | /* The name if this is an label. */ |
145 | char label[16]; | |
146 | ||
147 | /* The target label name if this is an branch. */ | |
148 | char target[16]; | |
149 | ||
47e39b9d RS |
150 | /* The frag that contains the instruction. */ |
151 | struct frag *frag; | |
152 | ||
153 | /* The offset into FRAG of the first instruction byte. */ | |
154 | long where; | |
155 | ||
156 | /* The relocs associated with the instruction, if any. */ | |
157 | fixS *fixp[3]; | |
158 | ||
a38419a5 RS |
159 | /* True if this entry cannot be moved from its current position. */ |
160 | unsigned int fixed_p : 1; | |
47e39b9d | 161 | |
708587a4 | 162 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
163 | unsigned int noreorder_p : 1; |
164 | ||
2fa15973 RS |
165 | /* True for mips16 instructions that jump to an absolute address. */ |
166 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
167 | |
168 | /* True if this instruction is complete. */ | |
169 | unsigned int complete_p : 1; | |
e407c74b NC |
170 | |
171 | /* True if this instruction is cleared from history by unconditional | |
172 | branch. */ | |
173 | unsigned int cleared_p : 1; | |
47e39b9d RS |
174 | }; |
175 | ||
a325df1d TS |
176 | /* The ABI to use. */ |
177 | enum mips_abi_level | |
178 | { | |
179 | NO_ABI = 0, | |
180 | O32_ABI, | |
181 | O64_ABI, | |
182 | N32_ABI, | |
183 | N64_ABI, | |
184 | EABI_ABI | |
185 | }; | |
186 | ||
187 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 188 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 189 | |
143d77c5 EC |
190 | /* Whether or not we have code that can call pic code. */ |
191 | int mips_abicalls = FALSE; | |
192 | ||
aa6975fb ILT |
193 | /* Whether or not we have code which can be put into a shared |
194 | library. */ | |
195 | static bfd_boolean mips_in_shared = TRUE; | |
196 | ||
252b5132 RH |
197 | /* This is the set of options which may be modified by the .set |
198 | pseudo-op. We use a struct so that .set push and .set pop are more | |
199 | reliable. */ | |
200 | ||
e972090a NC |
201 | struct mips_set_options |
202 | { | |
252b5132 RH |
203 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
204 | if it has not been initialized. Changed by `.set mipsN', and the | |
205 | -mipsN command line option, and the default CPU. */ | |
206 | int isa; | |
846ef2d0 RS |
207 | /* Enabled Application Specific Extensions (ASEs). Changed by `.set |
208 | <asename>', by command line options, and based on the default | |
209 | architecture. */ | |
210 | int ase; | |
252b5132 RH |
211 | /* Whether we are assembling for the mips16 processor. 0 if we are |
212 | not, 1 if we are, and -1 if the value has not been initialized. | |
213 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
214 | -nomips16 command line options, and the default CPU. */ | |
215 | int mips16; | |
df58fc94 RS |
216 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
217 | 1 if we are, and -1 if the value has not been initialized. Changed | |
218 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
219 | and -mno-micromips command line options, and the default CPU. */ | |
220 | int micromips; | |
252b5132 RH |
221 | /* Non-zero if we should not reorder instructions. Changed by `.set |
222 | reorder' and `.set noreorder'. */ | |
223 | int noreorder; | |
741fe287 MR |
224 | /* Non-zero if we should not permit the register designated "assembler |
225 | temporary" to be used in instructions. The value is the register | |
226 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
227 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
228 | unsigned int at; | |
252b5132 RH |
229 | /* Non-zero if we should warn when a macro instruction expands into |
230 | more than one machine instruction. Changed by `.set nomacro' and | |
231 | `.set macro'. */ | |
232 | int warn_about_macros; | |
233 | /* Non-zero if we should not move instructions. Changed by `.set | |
234 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
235 | int nomove; | |
236 | /* Non-zero if we should not optimize branches by moving the target | |
237 | of the branch into the delay slot. Actually, we don't perform | |
238 | this optimization anyhow. Changed by `.set bopt' and `.set | |
239 | nobopt'. */ | |
240 | int nobopt; | |
241 | /* Non-zero if we should not autoextend mips16 instructions. | |
242 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
243 | int noautoextend; | |
833794fc MR |
244 | /* True if we should only emit 32-bit microMIPS instructions. |
245 | Changed by `.set insn32' and `.set noinsn32', and the -minsn32 | |
246 | and -mno-insn32 command line options. */ | |
247 | bfd_boolean insn32; | |
a325df1d TS |
248 | /* Restrict general purpose registers and floating point registers |
249 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
250 | is passed but can changed if the assembler code uses .set mipsN. */ | |
bad1aba3 | 251 | int gp; |
0b35dfee | 252 | int fp; |
fef14a42 TS |
253 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
254 | command line option, and the default CPU. */ | |
255 | int arch; | |
aed1a261 RS |
256 | /* True if ".set sym32" is in effect. */ |
257 | bfd_boolean sym32; | |
037b32b9 AN |
258 | /* True if floating-point operations are not allowed. Changed by .set |
259 | softfloat or .set hardfloat, by command line options -msoft-float or | |
260 | -mhard-float. The default is false. */ | |
261 | bfd_boolean soft_float; | |
262 | ||
263 | /* True if only single-precision floating-point operations are allowed. | |
264 | Changed by .set singlefloat or .set doublefloat, command-line options | |
265 | -msingle-float or -mdouble-float. The default is false. */ | |
266 | bfd_boolean single_float; | |
351cdf24 MF |
267 | |
268 | /* 1 if single-precision operations on odd-numbered registers are | |
269 | allowed. */ | |
270 | int oddspreg; | |
3315614d MF |
271 | |
272 | /* The set of ASEs that should be enabled for the user specified | |
273 | architecture. This cannot be inferred from 'arch' for all cores | |
274 | as processors only have a unique 'arch' if they add architecture | |
275 | specific instructions (UDI). */ | |
276 | int init_ase; | |
252b5132 RH |
277 | }; |
278 | ||
919731af | 279 | /* Specifies whether module level options have been checked yet. */ |
280 | static bfd_boolean file_mips_opts_checked = FALSE; | |
281 | ||
7361da2c AB |
282 | /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the |
283 | value has not been initialized. Changed by `.nan legacy' and | |
284 | `.nan 2008', and the -mnan=legacy and -mnan=2008 command line | |
285 | options, and the default CPU. */ | |
286 | static int mips_nan2008 = -1; | |
a325df1d | 287 | |
0b35dfee | 288 | /* This is the struct we use to hold the module level set of options. |
bad1aba3 | 289 | Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and |
0b35dfee | 290 | fp fields to -1 to indicate that they have not been initialized. */ |
037b32b9 | 291 | |
0b35dfee | 292 | static struct mips_set_options file_mips_opts = |
293 | { | |
294 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, | |
295 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, | |
296 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, | |
bad1aba3 | 297 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
3315614d MF |
298 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1, |
299 | /* init_ase */ 0 | |
0b35dfee | 300 | }; |
252b5132 | 301 | |
0b35dfee | 302 | /* This is similar to file_mips_opts, but for the current set of options. */ |
ba92f887 | 303 | |
e972090a NC |
304 | static struct mips_set_options mips_opts = |
305 | { | |
846ef2d0 | 306 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, |
b015e599 | 307 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, |
833794fc | 308 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, |
bad1aba3 | 309 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
3315614d MF |
310 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1, |
311 | /* init_ase */ 0 | |
e7af610e | 312 | }; |
252b5132 | 313 | |
846ef2d0 RS |
314 | /* Which bits of file_ase were explicitly set or cleared by ASE options. */ |
315 | static unsigned int file_ase_explicit; | |
316 | ||
252b5132 RH |
317 | /* These variables are filled in with the masks of registers used. |
318 | The object format code reads them and puts them in the appropriate | |
319 | place. */ | |
320 | unsigned long mips_gprmask; | |
321 | unsigned long mips_cprmask[4]; | |
322 | ||
738f4d98 | 323 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
324 | static int file_ase_mips16; |
325 | ||
3994f87e TS |
326 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
327 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
328 | || mips_opts.isa == ISA_MIPS32R3 \ |
329 | || mips_opts.isa == ISA_MIPS32R5 \ | |
3994f87e | 330 | || mips_opts.isa == ISA_MIPS64 \ |
ae52f483 AB |
331 | || mips_opts.isa == ISA_MIPS64R2 \ |
332 | || mips_opts.isa == ISA_MIPS64R3 \ | |
333 | || mips_opts.isa == ISA_MIPS64R5) | |
3994f87e | 334 | |
df58fc94 RS |
335 | /* True if any microMIPS code was produced. */ |
336 | static int file_ase_micromips; | |
337 | ||
b12dd2e4 CF |
338 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
339 | #ifdef TE_IRIX | |
1180b5a4 | 340 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 341 | #else |
1180b5a4 RS |
342 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
343 | because there's no place for any addend, the only acceptable | |
344 | expression is a bare symbol. */ | |
345 | #define MIPS_JALR_HINT_P(EXPR) \ | |
346 | (!HAVE_IN_PLACE_ADDENDS \ | |
347 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
348 | #endif |
349 | ||
ec68c924 | 350 | /* The argument of the -march= flag. The architecture we are assembling. */ |
316f5878 | 351 | static const char *mips_arch_string; |
ec68c924 EC |
352 | |
353 | /* The argument of the -mtune= flag. The architecture for which we | |
354 | are optimizing. */ | |
355 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 356 | static const char *mips_tune_string; |
ec68c924 | 357 | |
316f5878 | 358 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
359 | static int mips_32bitmode = 0; |
360 | ||
316f5878 RS |
361 | /* True if the given ABI requires 32-bit registers. */ |
362 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
363 | ||
364 | /* Likewise 64-bit registers. */ | |
707bfff6 | 365 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
134c0c8b | 366 | ((ABI) == N32_ABI \ |
707bfff6 | 367 | || (ABI) == N64_ABI \ |
316f5878 RS |
368 | || (ABI) == O64_ABI) |
369 | ||
7361da2c AB |
370 | #define ISA_IS_R6(ISA) \ |
371 | ((ISA) == ISA_MIPS32R6 \ | |
372 | || (ISA) == ISA_MIPS64R6) | |
373 | ||
ad3fea08 | 374 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
375 | #define ISA_HAS_64BIT_REGS(ISA) \ |
376 | ((ISA) == ISA_MIPS3 \ | |
377 | || (ISA) == ISA_MIPS4 \ | |
378 | || (ISA) == ISA_MIPS5 \ | |
379 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
380 | || (ISA) == ISA_MIPS64R2 \ |
381 | || (ISA) == ISA_MIPS64R3 \ | |
7361da2c AB |
382 | || (ISA) == ISA_MIPS64R5 \ |
383 | || (ISA) == ISA_MIPS64R6) | |
9ce8a5dd | 384 | |
ad3fea08 TS |
385 | /* Return true if ISA supports 64 bit wide float registers. */ |
386 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
387 | ((ISA) == ISA_MIPS3 \ | |
388 | || (ISA) == ISA_MIPS4 \ | |
389 | || (ISA) == ISA_MIPS5 \ | |
390 | || (ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
391 | || (ISA) == ISA_MIPS32R3 \ |
392 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 393 | || (ISA) == ISA_MIPS32R6 \ |
ad3fea08 | 394 | || (ISA) == ISA_MIPS64 \ |
ae52f483 AB |
395 | || (ISA) == ISA_MIPS64R2 \ |
396 | || (ISA) == ISA_MIPS64R3 \ | |
7361da2c AB |
397 | || (ISA) == ISA_MIPS64R5 \ |
398 | || (ISA) == ISA_MIPS64R6) | |
ad3fea08 | 399 | |
af7ee8bf CD |
400 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
401 | instructions. */ | |
707bfff6 | 402 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 | 403 | ((ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
404 | || (ISA) == ISA_MIPS64R3 \ |
405 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 406 | || (ISA) == ISA_MIPS64R6 \ |
df58fc94 RS |
407 | || (mips_opts.micromips \ |
408 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
409 | ) | |
af7ee8bf CD |
410 | |
411 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
412 | instructions. */ | |
707bfff6 TS |
413 | #define ISA_HAS_ROR(ISA) \ |
414 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
415 | || (ISA) == ISA_MIPS32R3 \ |
416 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 417 | || (ISA) == ISA_MIPS32R6 \ |
707bfff6 | 418 | || (ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
419 | || (ISA) == ISA_MIPS64R3 \ |
420 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 421 | || (ISA) == ISA_MIPS64R6 \ |
846ef2d0 | 422 | || (mips_opts.ase & ASE_SMARTMIPS) \ |
df58fc94 RS |
423 | || mips_opts.micromips \ |
424 | ) | |
707bfff6 | 425 | |
7455baf8 | 426 | /* Return true if ISA supports single-precision floats in odd registers. */ |
351cdf24 MF |
427 | #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\ |
428 | (((ISA) == ISA_MIPS32 \ | |
429 | || (ISA) == ISA_MIPS32R2 \ | |
430 | || (ISA) == ISA_MIPS32R3 \ | |
431 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 432 | || (ISA) == ISA_MIPS32R6 \ |
351cdf24 MF |
433 | || (ISA) == ISA_MIPS64 \ |
434 | || (ISA) == ISA_MIPS64R2 \ | |
435 | || (ISA) == ISA_MIPS64R3 \ | |
436 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 437 | || (ISA) == ISA_MIPS64R6 \ |
351cdf24 | 438 | || (CPU) == CPU_R5900) \ |
bd782c07 | 439 | && ((CPU) != CPU_GS464 \ |
9108bc33 CX |
440 | || (CPU) != CPU_GS464E \ |
441 | || (CPU) != CPU_GS264E)) | |
af7ee8bf | 442 | |
ad3fea08 TS |
443 | /* Return true if ISA supports move to/from high part of a 64-bit |
444 | floating-point register. */ | |
445 | #define ISA_HAS_MXHC1(ISA) \ | |
446 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
447 | || (ISA) == ISA_MIPS32R3 \ |
448 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c AB |
449 | || (ISA) == ISA_MIPS32R6 \ |
450 | || (ISA) == ISA_MIPS64R2 \ | |
451 | || (ISA) == ISA_MIPS64R3 \ | |
452 | || (ISA) == ISA_MIPS64R5 \ | |
453 | || (ISA) == ISA_MIPS64R6) | |
454 | ||
455 | /* Return true if ISA supports legacy NAN. */ | |
456 | #define ISA_HAS_LEGACY_NAN(ISA) \ | |
457 | ((ISA) == ISA_MIPS1 \ | |
458 | || (ISA) == ISA_MIPS2 \ | |
459 | || (ISA) == ISA_MIPS3 \ | |
460 | || (ISA) == ISA_MIPS4 \ | |
461 | || (ISA) == ISA_MIPS5 \ | |
462 | || (ISA) == ISA_MIPS32 \ | |
463 | || (ISA) == ISA_MIPS32R2 \ | |
464 | || (ISA) == ISA_MIPS32R3 \ | |
465 | || (ISA) == ISA_MIPS32R5 \ | |
466 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
467 | || (ISA) == ISA_MIPS64R2 \ |
468 | || (ISA) == ISA_MIPS64R3 \ | |
469 | || (ISA) == ISA_MIPS64R5) | |
ad3fea08 | 470 | |
bad1aba3 | 471 | #define GPR_SIZE \ |
472 | (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \ | |
473 | ? 32 \ | |
474 | : mips_opts.gp) | |
ca4e0257 | 475 | |
bad1aba3 | 476 | #define FPR_SIZE \ |
477 | (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \ | |
478 | ? 32 \ | |
479 | : mips_opts.fp) | |
ca4e0257 | 480 | |
316f5878 | 481 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 482 | |
316f5878 | 483 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 484 | |
3b91255e RS |
485 | /* True if relocations are stored in-place. */ |
486 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
487 | ||
aed1a261 RS |
488 | /* The ABI-derived address size. */ |
489 | #define HAVE_64BIT_ADDRESSES \ | |
bad1aba3 | 490 | (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) |
aed1a261 | 491 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) |
e013f690 | 492 | |
aed1a261 RS |
493 | /* The size of symbolic constants (i.e., expressions of the form |
494 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
495 | #define HAVE_32BIT_SYMBOLS \ | |
496 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
497 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 498 | |
b7c7d6c1 TS |
499 | /* Addresses are loaded in different ways, depending on the address size |
500 | in use. The n32 ABI Documentation also mandates the use of additions | |
501 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 502 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 503 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
504 | |
505 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 506 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
507 | |
508 | #define ADDRESS_LOAD_INSN \ | |
509 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
510 | ||
511 | #define ADDRESS_STORE_INSN \ | |
512 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
513 | ||
a4672219 | 514 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
515 | #define CPU_HAS_MIPS16(cpu) \ |
516 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
517 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 518 | |
2309ddf2 | 519 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
520 | #define CPU_HAS_MICROMIPS(cpu) 0 |
521 | ||
60b63b72 RS |
522 | /* True if CPU has a dror instruction. */ |
523 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
524 | ||
525 | /* True if CPU has a ror instruction. */ | |
526 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
527 | ||
6f2117ba | 528 | /* True if CPU is in the Octeon family. */ |
2c629856 N |
529 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \ |
530 | || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3) | |
dd6a37e7 | 531 | |
dd3cbb7e | 532 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 533 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 534 | |
0aa27725 RS |
535 | /* True, if CPU has support for ldc1 and sdc1. */ |
536 | #define CPU_HAS_LDC1_SDC1(CPU) \ | |
537 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) | |
538 | ||
c8978940 CD |
539 | /* True if mflo and mfhi can be immediately followed by instructions |
540 | which write to the HI and LO registers. | |
541 | ||
542 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
543 | (at least) two instructions between the reads of HI/LO and | |
544 | instructions which write them, and later ISAs do not. Contradicting | |
545 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
546 | the UM for the NEC Vr5000) document needing the instructions between | |
547 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
548 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
549 | earlier-ISA CPUs for which CPU documentation declares that the | |
550 | instructions are really interlocked. */ | |
551 | #define hilo_interlocks \ | |
552 | (mips_opts.isa == ISA_MIPS32 \ | |
553 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
554 | || mips_opts.isa == ISA_MIPS32R3 \ |
555 | || mips_opts.isa == ISA_MIPS32R5 \ | |
7361da2c | 556 | || mips_opts.isa == ISA_MIPS32R6 \ |
c8978940 CD |
557 | || mips_opts.isa == ISA_MIPS64 \ |
558 | || mips_opts.isa == ISA_MIPS64R2 \ | |
ae52f483 AB |
559 | || mips_opts.isa == ISA_MIPS64R3 \ |
560 | || mips_opts.isa == ISA_MIPS64R5 \ | |
7361da2c | 561 | || mips_opts.isa == ISA_MIPS64R6 \ |
c8978940 | 562 | || mips_opts.arch == CPU_R4010 \ |
e407c74b | 563 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
564 | || mips_opts.arch == CPU_R10000 \ |
565 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
566 | || mips_opts.arch == CPU_R14000 \ |
567 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 568 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 569 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 570 | || mips_opts.micromips \ |
c8978940 | 571 | ) |
252b5132 RH |
572 | |
573 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
574 | from the GPRs after they are loaded from memory, and thus does not |
575 | require nops to be inserted. This applies to instructions marked | |
67dc82bc | 576 | INSN_LOAD_MEMORY. These nops are only required at MIPS ISA |
df58fc94 RS |
577 | level I and microMIPS mode instructions are always interlocked. */ |
578 | #define gpr_interlocks \ | |
579 | (mips_opts.isa != ISA_MIPS1 \ | |
580 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 581 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
582 | || mips_opts.micromips \ |
583 | ) | |
252b5132 | 584 | |
81912461 ILT |
585 | /* Whether the processor uses hardware interlocks to avoid delays |
586 | required by coprocessor instructions, and thus does not require | |
587 | nops to be inserted. This applies to instructions marked | |
43885403 MF |
588 | INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between |
589 | instructions marked INSN_WRITE_COND_CODE and ones marked | |
81912461 | 590 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA |
df58fc94 RS |
591 | levels I, II, and III and microMIPS mode instructions are always |
592 | interlocked. */ | |
bdaaa2e1 | 593 | /* Itbl support may require additional care here. */ |
81912461 ILT |
594 | #define cop_interlocks \ |
595 | ((mips_opts.isa != ISA_MIPS1 \ | |
596 | && mips_opts.isa != ISA_MIPS2 \ | |
597 | && mips_opts.isa != ISA_MIPS3) \ | |
598 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 599 | || mips_opts.micromips \ |
81912461 ILT |
600 | ) |
601 | ||
602 | /* Whether the processor uses hardware interlocks to protect reads | |
603 | from coprocessor registers after they are loaded from memory, and | |
604 | thus does not require nops to be inserted. This applies to | |
605 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
606 | requires at MIPS ISA level I and microMIPS mode instructions are |
607 | always interlocked. */ | |
608 | #define cop_mem_interlocks \ | |
609 | (mips_opts.isa != ISA_MIPS1 \ | |
610 | || mips_opts.micromips \ | |
611 | ) | |
252b5132 | 612 | |
6b76fefe CM |
613 | /* Is this a mfhi or mflo instruction? */ |
614 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
615 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
616 | ||
df58fc94 RS |
617 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
618 | has been selected. This implies, in particular, that addresses of text | |
619 | labels have their LSB set. */ | |
620 | #define HAVE_CODE_COMPRESSION \ | |
621 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
622 | ||
42429eac | 623 | /* The minimum and maximum signed values that can be stored in a GPR. */ |
bad1aba3 | 624 | #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1)) |
42429eac RS |
625 | #define GPR_SMIN (-GPR_SMAX - 1) |
626 | ||
252b5132 RH |
627 | /* MIPS PIC level. */ |
628 | ||
a161fe53 | 629 | enum mips_pic_level mips_pic; |
252b5132 | 630 | |
c9914766 | 631 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 632 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 633 | static int mips_big_got = 0; |
252b5132 RH |
634 | |
635 | /* 1 if trap instructions should used for overflow rather than break | |
636 | instructions. */ | |
c9914766 | 637 | static int mips_trap = 0; |
252b5132 | 638 | |
119d663a | 639 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 640 | by assembling two single width halves into two single width floating |
119d663a NC |
641 | point registers which just happen to alias the double width destination |
642 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 643 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
644 | automatically at assemble time. */ |
645 | static int mips_disable_float_construction; | |
646 | ||
252b5132 RH |
647 | /* Non-zero if any .set noreorder directives were used. */ |
648 | ||
649 | static int mips_any_noreorder; | |
650 | ||
6b76fefe CM |
651 | /* Non-zero if nops should be inserted when the register referenced in |
652 | an mfhi/mflo instruction is read in the next two instructions. */ | |
653 | static int mips_7000_hilo_fix; | |
654 | ||
02ffd3e4 | 655 | /* The size of objects in the small data section. */ |
156c2f8b | 656 | static unsigned int g_switch_value = 8; |
252b5132 RH |
657 | /* Whether the -G option was used. */ |
658 | static int g_switch_seen = 0; | |
659 | ||
660 | #define N_RMASK 0xc4 | |
661 | #define N_VFP 0xd4 | |
662 | ||
663 | /* If we can determine in advance that GP optimization won't be | |
664 | possible, we can skip the relaxation stuff that tries to produce | |
665 | GP-relative references. This makes delay slot optimization work | |
666 | better. | |
667 | ||
668 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
669 | gcc output. It needs to guess right for gcc, otherwise gcc |
670 | will put what it thinks is a GP-relative instruction in a branch | |
671 | delay slot. | |
252b5132 RH |
672 | |
673 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
674 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 675 | static int nopic_need_relax (symbolS *, int); |
252b5132 | 676 | |
6f2117ba | 677 | /* Handle of the OPCODE hash table. */ |
252b5132 RH |
678 | static struct hash_control *op_hash = NULL; |
679 | ||
680 | /* The opcode hash table we use for the mips16. */ | |
681 | static struct hash_control *mips16_op_hash = NULL; | |
682 | ||
df58fc94 RS |
683 | /* The opcode hash table we use for the microMIPS ASE. */ |
684 | static struct hash_control *micromips_op_hash = NULL; | |
685 | ||
252b5132 | 686 | /* This array holds the chars that always start a comment. If the |
6f2117ba | 687 | pre-processor is disabled, these aren't very useful. */ |
252b5132 RH |
688 | const char comment_chars[] = "#"; |
689 | ||
690 | /* This array holds the chars that only start a comment at the beginning of | |
691 | a line. If the line seems to have the form '# 123 filename' | |
6f2117ba | 692 | .line and .file directives will appear in the pre-processed output. */ |
252b5132 RH |
693 | /* Note that input_file.c hand checks for '#' at the beginning of the |
694 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 695 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
696 | /* Also note that C style comments are always supported. */ |
697 | const char line_comment_chars[] = "#"; | |
698 | ||
bdaaa2e1 | 699 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 700 | const char line_separator_chars[] = ";"; |
252b5132 | 701 | |
6f2117ba | 702 | /* Chars that can be used to separate mant from exp in floating point nums. */ |
252b5132 RH |
703 | const char EXP_CHARS[] = "eE"; |
704 | ||
6f2117ba PH |
705 | /* Chars that mean this number is a floating point constant. |
706 | As in 0f12.456 | |
707 | or 0d1.2345e12. */ | |
252b5132 RH |
708 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
709 | ||
710 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
711 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
6f2117ba | 712 | but nothing is ideal around here. */ |
252b5132 | 713 | |
e3de51ce | 714 | /* Types of printf format used for instruction-related error messages. |
6f2117ba PH |
715 | "I" means int ("%d") and "S" means string ("%s"). */ |
716 | enum mips_insn_error_format | |
717 | { | |
e3de51ce RS |
718 | ERR_FMT_PLAIN, |
719 | ERR_FMT_I, | |
720 | ERR_FMT_SS, | |
721 | }; | |
722 | ||
723 | /* Information about an error that was found while assembling the current | |
724 | instruction. */ | |
6f2117ba PH |
725 | struct mips_insn_error |
726 | { | |
e3de51ce RS |
727 | /* We sometimes need to match an instruction against more than one |
728 | opcode table entry. Errors found during this matching are reported | |
729 | against a particular syntactic argument rather than against the | |
730 | instruction as a whole. We grade these messages so that errors | |
731 | against argument N have a greater priority than an error against | |
732 | any argument < N, since the former implies that arguments up to N | |
733 | were acceptable and that the opcode entry was therefore a closer match. | |
734 | If several matches report an error against the same argument, | |
735 | we only use that error if it is the same in all cases. | |
736 | ||
737 | min_argnum is the minimum argument number for which an error message | |
738 | should be accepted. It is 0 if MSG is against the instruction as | |
739 | a whole. */ | |
740 | int min_argnum; | |
741 | ||
742 | /* The printf()-style message, including its format and arguments. */ | |
743 | enum mips_insn_error_format format; | |
744 | const char *msg; | |
6f2117ba PH |
745 | union |
746 | { | |
e3de51ce RS |
747 | int i; |
748 | const char *ss[2]; | |
749 | } u; | |
750 | }; | |
751 | ||
752 | /* The error that should be reported for the current instruction. */ | |
753 | static struct mips_insn_error insn_error; | |
252b5132 RH |
754 | |
755 | static int auto_align = 1; | |
756 | ||
757 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
758 | offset in the stack frame from which to restore the $gp register. | |
759 | This is set by the .cprestore pseudo-op, and saved in this | |
760 | variable. */ | |
761 | static offsetT mips_cprestore_offset = -1; | |
762 | ||
67c1ffbe | 763 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 764 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 765 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
766 | static offsetT mips_cpreturn_offset = -1; |
767 | static int mips_cpreturn_register = -1; | |
768 | static int mips_gp_register = GP; | |
def2e0dd | 769 | static int mips_gprel_offset = 0; |
6478892d | 770 | |
7a621144 DJ |
771 | /* Whether mips_cprestore_offset has been set in the current function |
772 | (or whether it has already been warned about, if not). */ | |
773 | static int mips_cprestore_valid = 0; | |
774 | ||
252b5132 RH |
775 | /* This is the register which holds the stack frame, as set by the |
776 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
777 | static int mips_frame_reg = SP; | |
778 | ||
7a621144 DJ |
779 | /* Whether mips_frame_reg has been set in the current function |
780 | (or whether it has already been warned about, if not). */ | |
781 | static int mips_frame_reg_valid = 0; | |
782 | ||
252b5132 RH |
783 | /* To output NOP instructions correctly, we need to keep information |
784 | about the previous two instructions. */ | |
785 | ||
786 | /* Whether we are optimizing. The default value of 2 means to remove | |
787 | unneeded NOPs and swap branch instructions when possible. A value | |
788 | of 1 means to not swap branches. A value of 0 means to always | |
789 | insert NOPs. */ | |
790 | static int mips_optimize = 2; | |
791 | ||
792 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
793 | equivalent to seeing no -g option at all. */ | |
794 | static int mips_debug = 0; | |
795 | ||
7d8e00cf RS |
796 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
797 | #define MAX_VR4130_NOPS 4 | |
798 | ||
799 | /* The maximum number of NOPs needed to fill delay slots. */ | |
800 | #define MAX_DELAY_NOPS 2 | |
801 | ||
802 | /* The maximum number of NOPs needed for any purpose. */ | |
803 | #define MAX_NOPS 4 | |
71400594 | 804 | |
6f2117ba PH |
805 | /* The maximum range of context length of ll/sc. */ |
806 | #define MAX_LLSC_RANGE 20 | |
807 | ||
71400594 RS |
808 | /* A list of previous instructions, with index 0 being the most recent. |
809 | We need to look back MAX_NOPS instructions when filling delay slots | |
810 | or working around processor errata. We need to look back one | |
811 | instruction further if we're thinking about using history[0] to | |
812 | fill a branch delay slot. */ | |
6f2117ba | 813 | static struct mips_cl_insn history[1 + MAX_NOPS + MAX_LLSC_RANGE]; |
252b5132 | 814 | |
dec7b24b YS |
815 | /* The maximum number of LABELS detect for the same address. */ |
816 | #define MAX_LABELS_SAME 10 | |
817 | ||
fc76e730 | 818 | /* Arrays of operands for each instruction. */ |
14daeee3 | 819 | #define MAX_OPERANDS 6 |
6f2117ba PH |
820 | struct mips_operand_array |
821 | { | |
fc76e730 RS |
822 | const struct mips_operand *operand[MAX_OPERANDS]; |
823 | }; | |
824 | static struct mips_operand_array *mips_operands; | |
825 | static struct mips_operand_array *mips16_operands; | |
826 | static struct mips_operand_array *micromips_operands; | |
827 | ||
1e915849 | 828 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
829 | static struct mips_cl_insn nop_insn; |
830 | static struct mips_cl_insn mips16_nop_insn; | |
831 | static struct mips_cl_insn micromips_nop16_insn; | |
832 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 | 833 | |
6f2117ba PH |
834 | /* Sync instructions used by insert sync. */ |
835 | static struct mips_cl_insn sync_insn; | |
836 | ||
1e915849 | 837 | /* The appropriate nop for the current mode. */ |
833794fc MR |
838 | #define NOP_INSN (mips_opts.mips16 \ |
839 | ? &mips16_nop_insn \ | |
840 | : (mips_opts.micromips \ | |
841 | ? (mips_opts.insn32 \ | |
842 | ? µmips_nop32_insn \ | |
843 | : µmips_nop16_insn) \ | |
844 | : &nop_insn)) | |
df58fc94 RS |
845 | |
846 | /* The size of NOP_INSN in bytes. */ | |
833794fc MR |
847 | #define NOP_INSN_SIZE ((mips_opts.mips16 \ |
848 | || (mips_opts.micromips && !mips_opts.insn32)) \ | |
849 | ? 2 : 4) | |
252b5132 | 850 | |
252b5132 RH |
851 | /* If this is set, it points to a frag holding nop instructions which |
852 | were inserted before the start of a noreorder section. If those | |
853 | nops turn out to be unnecessary, the size of the frag can be | |
854 | decreased. */ | |
855 | static fragS *prev_nop_frag; | |
856 | ||
857 | /* The number of nop instructions we created in prev_nop_frag. */ | |
858 | static int prev_nop_frag_holds; | |
859 | ||
860 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 861 | prev_nop_frag. */ |
252b5132 RH |
862 | static int prev_nop_frag_required; |
863 | ||
864 | /* The number of instructions we've seen since prev_nop_frag. */ | |
865 | static int prev_nop_frag_since; | |
866 | ||
e8044f35 RS |
867 | /* Relocations against symbols are sometimes done in two parts, with a HI |
868 | relocation and a LO relocation. Each relocation has only 16 bits of | |
869 | space to store an addend. This means that in order for the linker to | |
870 | handle carries correctly, it must be able to locate both the HI and | |
871 | the LO relocation. This means that the relocations must appear in | |
872 | order in the relocation table. | |
252b5132 RH |
873 | |
874 | In order to implement this, we keep track of each unmatched HI | |
875 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 876 | corresponding LO relocation. */ |
252b5132 | 877 | |
e972090a NC |
878 | struct mips_hi_fixup |
879 | { | |
252b5132 RH |
880 | /* Next HI fixup. */ |
881 | struct mips_hi_fixup *next; | |
882 | /* This fixup. */ | |
883 | fixS *fixp; | |
884 | /* The section this fixup is in. */ | |
885 | segT seg; | |
886 | }; | |
887 | ||
888 | /* The list of unmatched HI relocs. */ | |
889 | ||
890 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
891 | ||
252b5132 RH |
892 | /* Map mips16 register numbers to normal MIPS register numbers. */ |
893 | ||
e972090a NC |
894 | static const unsigned int mips16_to_32_reg_map[] = |
895 | { | |
252b5132 RH |
896 | 16, 17, 2, 3, 4, 5, 6, 7 |
897 | }; | |
60b63b72 | 898 | |
df58fc94 RS |
899 | /* Map microMIPS register numbers to normal MIPS register numbers. */ |
900 | ||
df58fc94 | 901 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map |
df58fc94 RS |
902 | |
903 | /* The microMIPS registers with type h. */ | |
e76ff5ab | 904 | static const unsigned int micromips_to_32_reg_h_map1[] = |
df58fc94 RS |
905 | { |
906 | 5, 5, 6, 4, 4, 4, 4, 4 | |
907 | }; | |
e76ff5ab | 908 | static const unsigned int micromips_to_32_reg_h_map2[] = |
df58fc94 RS |
909 | { |
910 | 6, 7, 7, 21, 22, 5, 6, 7 | |
911 | }; | |
912 | ||
df58fc94 RS |
913 | /* The microMIPS registers with type m. */ |
914 | static const unsigned int micromips_to_32_reg_m_map[] = | |
915 | { | |
916 | 0, 17, 2, 3, 16, 18, 19, 20 | |
917 | }; | |
918 | ||
919 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
920 | ||
71400594 RS |
921 | /* Classifies the kind of instructions we're interested in when |
922 | implementing -mfix-vr4120. */ | |
c67a084a NC |
923 | enum fix_vr4120_class |
924 | { | |
71400594 RS |
925 | FIX_VR4120_MACC, |
926 | FIX_VR4120_DMACC, | |
927 | FIX_VR4120_MULT, | |
928 | FIX_VR4120_DMULT, | |
929 | FIX_VR4120_DIV, | |
930 | FIX_VR4120_MTHILO, | |
931 | NUM_FIX_VR4120_CLASSES | |
932 | }; | |
933 | ||
c67a084a NC |
934 | /* ...likewise -mfix-loongson2f-jump. */ |
935 | static bfd_boolean mips_fix_loongson2f_jump; | |
936 | ||
937 | /* ...likewise -mfix-loongson2f-nop. */ | |
938 | static bfd_boolean mips_fix_loongson2f_nop; | |
939 | ||
940 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
941 | static bfd_boolean mips_fix_loongson2f; | |
942 | ||
71400594 RS |
943 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
944 | there must be at least one other instruction between an instruction | |
945 | of type X and an instruction of type Y. */ | |
946 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
947 | ||
948 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 949 | static int mips_fix_vr4120; |
4a6a3df4 | 950 | |
7d8e00cf RS |
951 | /* ...likewise -mfix-vr4130. */ |
952 | static int mips_fix_vr4130; | |
953 | ||
6a32d874 CM |
954 | /* ...likewise -mfix-24k. */ |
955 | static int mips_fix_24k; | |
956 | ||
a8d14a88 CM |
957 | /* ...likewise -mfix-rm7000 */ |
958 | static int mips_fix_rm7000; | |
959 | ||
d954098f DD |
960 | /* ...likewise -mfix-cn63xxp1 */ |
961 | static bfd_boolean mips_fix_cn63xxp1; | |
962 | ||
27c634e0 FN |
963 | /* ...likewise -mfix-r5900 */ |
964 | static bfd_boolean mips_fix_r5900; | |
965 | static bfd_boolean mips_fix_r5900_explicit; | |
966 | ||
6f2117ba PH |
967 | /* ...likewise -mfix-loongson3-llsc. */ |
968 | static bfd_boolean mips_fix_loongson3_llsc = DEFAULT_MIPS_FIX_LOONGSON3_LLSC; | |
969 | ||
4a6a3df4 AO |
970 | /* We don't relax branches by default, since this causes us to expand |
971 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
972 | fail to compute the offset before expanding the macro to the most | |
973 | efficient expansion. */ | |
974 | ||
975 | static int mips_relax_branch; | |
8b10b0b3 MR |
976 | |
977 | /* TRUE if checks are suppressed for invalid branches between ISA modes. | |
978 | Needed for broken assembly produced by some GCC versions and some | |
979 | sloppy code out there, where branches to data labels are present. */ | |
980 | static bfd_boolean mips_ignore_branch_isa; | |
252b5132 | 981 | \f |
4d7206a2 RS |
982 | /* The expansion of many macros depends on the type of symbol that |
983 | they refer to. For example, when generating position-dependent code, | |
984 | a macro that refers to a symbol may have two different expansions, | |
985 | one which uses GP-relative addresses and one which uses absolute | |
986 | addresses. When generating SVR4-style PIC, a macro may have | |
987 | different expansions for local and global symbols. | |
988 | ||
989 | We handle these situations by generating both sequences and putting | |
990 | them in variant frags. In position-dependent code, the first sequence | |
991 | will be the GP-relative one and the second sequence will be the | |
992 | absolute one. In SVR4 PIC, the first sequence will be for global | |
993 | symbols and the second will be for local symbols. | |
994 | ||
584892a6 RS |
995 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
996 | SECOND are the lengths of the two sequences in bytes. These fields | |
997 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
998 | the subtype has the following flags: | |
4d7206a2 | 999 | |
ce8ad872 MR |
1000 | RELAX_PIC |
1001 | Set if generating PIC code. | |
1002 | ||
584892a6 RS |
1003 | RELAX_USE_SECOND |
1004 | Set if it has been decided that we should use the second | |
1005 | sequence instead of the first. | |
1006 | ||
1007 | RELAX_SECOND_LONGER | |
1008 | Set in the first variant frag if the macro's second implementation | |
1009 | is longer than its first. This refers to the macro as a whole, | |
1010 | not an individual relaxation. | |
1011 | ||
1012 | RELAX_NOMACRO | |
1013 | Set in the first variant frag if the macro appeared in a .set nomacro | |
1014 | block and if one alternative requires a warning but the other does not. | |
1015 | ||
1016 | RELAX_DELAY_SLOT | |
1017 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
1018 | delay slot. | |
4d7206a2 | 1019 | |
df58fc94 RS |
1020 | RELAX_DELAY_SLOT_16BIT |
1021 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
1022 | 16-bit instruction. | |
1023 | ||
1024 | RELAX_DELAY_SLOT_SIZE_FIRST | |
1025 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
1026 | the macro is of the wrong size for the branch delay slot. | |
1027 | ||
1028 | RELAX_DELAY_SLOT_SIZE_SECOND | |
1029 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
1030 | the macro is of the wrong size for the branch delay slot. | |
1031 | ||
4d7206a2 RS |
1032 | The frag's "opcode" points to the first fixup for relaxable code. |
1033 | ||
1034 | Relaxable macros are generated using a sequence such as: | |
1035 | ||
1036 | relax_start (SYMBOL); | |
1037 | ... generate first expansion ... | |
1038 | relax_switch (); | |
1039 | ... generate second expansion ... | |
1040 | relax_end (); | |
1041 | ||
1042 | The code and fixups for the unwanted alternative are discarded | |
1043 | by md_convert_frag. */ | |
ce8ad872 MR |
1044 | #define RELAX_ENCODE(FIRST, SECOND, PIC) \ |
1045 | (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0)) | |
4d7206a2 | 1046 | |
584892a6 RS |
1047 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1048 | #define RELAX_SECOND(X) ((X) & 0xff) | |
ce8ad872 MR |
1049 | #define RELAX_PIC(X) (((X) & 0x10000) != 0) |
1050 | #define RELAX_USE_SECOND 0x20000 | |
1051 | #define RELAX_SECOND_LONGER 0x40000 | |
1052 | #define RELAX_NOMACRO 0x80000 | |
1053 | #define RELAX_DELAY_SLOT 0x100000 | |
1054 | #define RELAX_DELAY_SLOT_16BIT 0x200000 | |
1055 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000 | |
1056 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000 | |
252b5132 | 1057 | |
4a6a3df4 AO |
1058 | /* Branch without likely bit. If label is out of range, we turn: |
1059 | ||
134c0c8b | 1060 | beq reg1, reg2, label |
4a6a3df4 AO |
1061 | delay slot |
1062 | ||
1063 | into | |
1064 | ||
1065 | bne reg1, reg2, 0f | |
1066 | nop | |
1067 | j label | |
1068 | 0: delay slot | |
1069 | ||
1070 | with the following opcode replacements: | |
1071 | ||
1072 | beq <-> bne | |
1073 | blez <-> bgtz | |
1074 | bltz <-> bgez | |
1075 | bc1f <-> bc1t | |
1076 | ||
1077 | bltzal <-> bgezal (with jal label instead of j label) | |
1078 | ||
1079 | Even though keeping the delay slot instruction in the delay slot of | |
1080 | the branch would be more efficient, it would be very tricky to do | |
1081 | correctly, because we'd have to introduce a variable frag *after* | |
1082 | the delay slot instruction, and expand that instead. Let's do it | |
1083 | the easy way for now, even if the branch-not-taken case now costs | |
1084 | one additional instruction. Out-of-range branches are not supposed | |
1085 | to be common, anyway. | |
1086 | ||
1087 | Branch likely. If label is out of range, we turn: | |
1088 | ||
1089 | beql reg1, reg2, label | |
1090 | delay slot (annulled if branch not taken) | |
1091 | ||
1092 | into | |
1093 | ||
1094 | beql reg1, reg2, 1f | |
1095 | nop | |
1096 | beql $0, $0, 2f | |
1097 | nop | |
1098 | 1: j[al] label | |
1099 | delay slot (executed only if branch taken) | |
1100 | 2: | |
1101 | ||
1102 | It would be possible to generate a shorter sequence by losing the | |
1103 | likely bit, generating something like: | |
b34976b6 | 1104 | |
4a6a3df4 AO |
1105 | bne reg1, reg2, 0f |
1106 | nop | |
1107 | j[al] label | |
1108 | delay slot (executed only if branch taken) | |
1109 | 0: | |
1110 | ||
1111 | beql -> bne | |
1112 | bnel -> beq | |
1113 | blezl -> bgtz | |
1114 | bgtzl -> blez | |
1115 | bltzl -> bgez | |
1116 | bgezl -> bltz | |
1117 | bc1fl -> bc1t | |
1118 | bc1tl -> bc1f | |
1119 | ||
1120 | bltzall -> bgezal (with jal label instead of j label) | |
1121 | bgezall -> bltzal (ditto) | |
1122 | ||
1123 | ||
1124 | but it's not clear that it would actually improve performance. */ | |
ce8ad872 MR |
1125 | #define RELAX_BRANCH_ENCODE(at, pic, \ |
1126 | uncond, likely, link, toofar) \ | |
66b3e8da MR |
1127 | ((relax_substateT) \ |
1128 | (0xc0000000 \ | |
1129 | | ((at) & 0x1f) \ | |
ce8ad872 MR |
1130 | | ((pic) ? 0x20 : 0) \ |
1131 | | ((toofar) ? 0x40 : 0) \ | |
1132 | | ((link) ? 0x80 : 0) \ | |
1133 | | ((likely) ? 0x100 : 0) \ | |
1134 | | ((uncond) ? 0x200 : 0))) | |
4a6a3df4 | 1135 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
ce8ad872 MR |
1136 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0) |
1137 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0) | |
1138 | #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0) | |
1139 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0) | |
1140 | #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0) | |
66b3e8da | 1141 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) |
4a6a3df4 | 1142 | |
252b5132 RH |
1143 | /* For mips16 code, we use an entirely different form of relaxation. |
1144 | mips16 supports two versions of most instructions which take | |
1145 | immediate values: a small one which takes some small value, and a | |
1146 | larger one which takes a 16 bit value. Since branches also follow | |
1147 | this pattern, relaxing these values is required. | |
1148 | ||
1149 | We can assemble both mips16 and normal MIPS code in a single | |
1150 | object. Therefore, we need to support this type of relaxation at | |
1151 | the same time that we support the relaxation described above. We | |
1152 | use the high bit of the subtype field to distinguish these cases. | |
1153 | ||
1154 | The information we store for this type of relaxation is the | |
1155 | argument code found in the opcode file for this relocation, whether | |
1156 | the user explicitly requested a small or extended form, and whether | |
1157 | the relocation is in a jump or jal delay slot. That tells us the | |
1158 | size of the value, and how it should be stored. We also store | |
1159 | whether the fragment is considered to be extended or not. We also | |
1160 | store whether this is known to be a branch to a different section, | |
1161 | whether we have tried to relax this frag yet, and whether we have | |
1162 | ever extended a PC relative fragment because of a shift count. */ | |
25499ac7 | 1163 | #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \ |
8507b6e7 MR |
1164 | small, ext, \ |
1165 | dslot, jal_dslot) \ | |
252b5132 RH |
1166 | (0x80000000 \ |
1167 | | ((type) & 0xff) \ | |
25499ac7 MR |
1168 | | ((e2) ? 0x100 : 0) \ |
1169 | | ((pic) ? 0x200 : 0) \ | |
1170 | | ((sym32) ? 0x400 : 0) \ | |
1171 | | ((nomacro) ? 0x800 : 0) \ | |
1172 | | ((small) ? 0x1000 : 0) \ | |
1173 | | ((ext) ? 0x2000 : 0) \ | |
1174 | | ((dslot) ? 0x4000 : 0) \ | |
1175 | | ((jal_dslot) ? 0x8000 : 0)) | |
8507b6e7 | 1176 | |
4a6a3df4 | 1177 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 | 1178 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
25499ac7 MR |
1179 | #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0) |
1180 | #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0) | |
1181 | #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0) | |
1182 | #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0) | |
1183 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0) | |
1184 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0) | |
1185 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0) | |
1186 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0) | |
1187 | ||
1188 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0) | |
1189 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000) | |
1190 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000) | |
1191 | #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0) | |
1192 | #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000) | |
1193 | #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000) | |
1194 | #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0) | |
1195 | #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000) | |
1196 | #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000) | |
885add95 | 1197 | |
df58fc94 RS |
1198 | /* For microMIPS code, we use relaxation similar to one we use for |
1199 | MIPS16 code. Some instructions that take immediate values support | |
1200 | two encodings: a small one which takes some small value, and a | |
1201 | larger one which takes a 16 bit value. As some branches also follow | |
1202 | this pattern, relaxing these values is required. | |
1203 | ||
1204 | We can assemble both microMIPS and normal MIPS code in a single | |
1205 | object. Therefore, we need to support this type of relaxation at | |
1206 | the same time that we support the relaxation described above. We | |
1207 | use one of the high bits of the subtype field to distinguish these | |
1208 | cases. | |
1209 | ||
1210 | The information we store for this type of relaxation is the argument | |
1211 | code found in the opcode file for this relocation, the register | |
8484fb75 MR |
1212 | selected as the assembler temporary, whether in the 32-bit |
1213 | instruction mode, whether the branch is unconditional, whether it is | |
7bd374a4 MR |
1214 | compact, whether there is no delay-slot instruction available to fill |
1215 | in, whether it stores the link address implicitly in $ra, whether | |
1216 | relaxation of out-of-range 32-bit branches to a sequence of | |
8484fb75 MR |
1217 | instructions is enabled, and whether the displacement of a branch is |
1218 | too large to fit as an immediate argument of a 16-bit and a 32-bit | |
1219 | branch, respectively. */ | |
ce8ad872 | 1220 | #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \ |
7bd374a4 | 1221 | uncond, compact, link, nods, \ |
40209cad MR |
1222 | relax32, toofar16, toofar32) \ |
1223 | (0x40000000 \ | |
1224 | | ((type) & 0xff) \ | |
1225 | | (((at) & 0x1f) << 8) \ | |
8484fb75 | 1226 | | ((insn32) ? 0x2000 : 0) \ |
ce8ad872 MR |
1227 | | ((pic) ? 0x4000 : 0) \ |
1228 | | ((uncond) ? 0x8000 : 0) \ | |
1229 | | ((compact) ? 0x10000 : 0) \ | |
1230 | | ((link) ? 0x20000 : 0) \ | |
1231 | | ((nods) ? 0x40000 : 0) \ | |
1232 | | ((relax32) ? 0x80000 : 0) \ | |
1233 | | ((toofar16) ? 0x100000 : 0) \ | |
1234 | | ((toofar32) ? 0x200000 : 0)) | |
df58fc94 RS |
1235 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1236 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1237 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
8484fb75 | 1238 | #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0) |
ce8ad872 MR |
1239 | #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0) |
1240 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0) | |
1241 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0) | |
1242 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0) | |
1243 | #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0) | |
1244 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0) | |
1245 | ||
1246 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0) | |
1247 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000) | |
1248 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000) | |
1249 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0) | |
1250 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000) | |
1251 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000) | |
df58fc94 | 1252 | |
43c0598f RS |
1253 | /* Sign-extend 16-bit value X. */ |
1254 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1255 | ||
885add95 CD |
1256 | /* Is the given value a sign-extended 32-bit value? */ |
1257 | #define IS_SEXT_32BIT_NUM(x) \ | |
1258 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1259 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1260 | ||
1261 | /* Is the given value a sign-extended 16-bit value? */ | |
1262 | #define IS_SEXT_16BIT_NUM(x) \ | |
1263 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1264 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1265 | ||
df58fc94 RS |
1266 | /* Is the given value a sign-extended 12-bit value? */ |
1267 | #define IS_SEXT_12BIT_NUM(x) \ | |
1268 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1269 | ||
7f3c4072 CM |
1270 | /* Is the given value a sign-extended 9-bit value? */ |
1271 | #define IS_SEXT_9BIT_NUM(x) \ | |
1272 | (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) | |
1273 | ||
2051e8c4 MR |
1274 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1275 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1276 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1277 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1278 | ||
bf12938e RS |
1279 | /* Extract bits MASK << SHIFT from STRUCT and shift them right |
1280 | SHIFT places. */ | |
1281 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1282 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1283 | ||
bf12938e | 1284 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ |
df58fc94 RS |
1285 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1286 | (!(MICROMIPS) \ | |
1287 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1288 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1289 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1290 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1291 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1292 | MIPS16OP_MASK_##FIELD, \ | |
1293 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1294 | |
1295 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1296 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1297 | \f |
df58fc94 RS |
1298 | /* Whether or not we are emitting a branch-likely macro. */ |
1299 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1300 | ||
4d7206a2 RS |
1301 | /* Global variables used when generating relaxable macros. See the |
1302 | comment above RELAX_ENCODE for more details about how relaxation | |
1303 | is used. */ | |
1304 | static struct { | |
1305 | /* 0 if we're not emitting a relaxable macro. | |
1306 | 1 if we're emitting the first of the two relaxation alternatives. | |
1307 | 2 if we're emitting the second alternative. */ | |
1308 | int sequence; | |
1309 | ||
1310 | /* The first relaxable fixup in the current frag. (In other words, | |
1311 | the first fixup that refers to relaxable code.) */ | |
1312 | fixS *first_fixup; | |
1313 | ||
1314 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1315 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1316 | unsigned int sizes[2]; | |
1317 | ||
1318 | /* The symbol on which the choice of sequence depends. */ | |
1319 | symbolS *symbol; | |
1320 | } mips_relax; | |
252b5132 | 1321 | \f |
584892a6 RS |
1322 | /* Global variables used to decide whether a macro needs a warning. */ |
1323 | static struct { | |
1324 | /* True if the macro is in a branch delay slot. */ | |
1325 | bfd_boolean delay_slot_p; | |
1326 | ||
df58fc94 RS |
1327 | /* Set to the length in bytes required if the macro is in a delay slot |
1328 | that requires a specific length of instruction, otherwise zero. */ | |
1329 | unsigned int delay_slot_length; | |
1330 | ||
584892a6 RS |
1331 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1332 | in bytes and sizes[1] is the length of the second alternative. | |
1333 | For non-relaxable macros, both elements give the length of the | |
1334 | macro in bytes. */ | |
1335 | unsigned int sizes[2]; | |
1336 | ||
df58fc94 RS |
1337 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1338 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1339 | is the length of the first instruction of the second alternative. | |
1340 | For non-relaxable macros, both elements give the length of the first | |
1341 | instruction in bytes. | |
1342 | ||
1343 | Set to zero if we haven't yet seen the first instruction. */ | |
1344 | unsigned int first_insn_sizes[2]; | |
1345 | ||
1346 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1347 | first alternative and insns[1] is the number of instructions for the | |
1348 | second alternative. | |
1349 | ||
1350 | For non-relaxable macros, both elements give the number of | |
1351 | instructions for the macro. */ | |
1352 | unsigned int insns[2]; | |
1353 | ||
584892a6 RS |
1354 | /* The first variant frag for this macro. */ |
1355 | fragS *first_frag; | |
1356 | } mips_macro_warning; | |
1357 | \f | |
252b5132 RH |
1358 | /* Prototypes for static functions. */ |
1359 | ||
252b5132 RH |
1360 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
1361 | ||
b34976b6 | 1362 | static void append_insn |
df58fc94 RS |
1363 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1364 | bfd_boolean expansionp); | |
7d10b47d | 1365 | static void mips_no_prev_insn (void); |
c67a084a | 1366 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1367 | static void mips16_macro_build |
03ea81db | 1368 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1369 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1370 | static void macro_start (void); |
1371 | static void macro_end (void); | |
833794fc | 1372 | static void macro (struct mips_cl_insn *ip, char *str); |
17a2f251 | 1373 | static void mips16_macro (struct mips_cl_insn * ip); |
17a2f251 TS |
1374 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1375 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
25499ac7 | 1376 | static unsigned long mips16_immed_extend (offsetT, unsigned int); |
b34976b6 | 1377 | static void mips16_immed |
3b4dbbbf | 1378 | (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
43c0598f | 1379 | unsigned int, unsigned long *); |
5e0116d5 | 1380 | static size_t my_getSmallExpression |
17a2f251 TS |
1381 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1382 | static void my_getExpression (expressionS *, char *); | |
1383 | static void s_align (int); | |
1384 | static void s_change_sec (int); | |
1385 | static void s_change_section (int); | |
1386 | static void s_cons (int); | |
1387 | static void s_float_cons (int); | |
1388 | static void s_mips_globl (int); | |
1389 | static void s_option (int); | |
1390 | static void s_mipsset (int); | |
1391 | static void s_abicalls (int); | |
1392 | static void s_cpload (int); | |
1393 | static void s_cpsetup (int); | |
1394 | static void s_cplocal (int); | |
1395 | static void s_cprestore (int); | |
1396 | static void s_cpreturn (int); | |
741d6ea8 JM |
1397 | static void s_dtprelword (int); |
1398 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1399 | static void s_tprelword (int); |
1400 | static void s_tpreldword (int); | |
17a2f251 TS |
1401 | static void s_gpvalue (int); |
1402 | static void s_gpword (int); | |
1403 | static void s_gpdword (int); | |
a3f278e2 | 1404 | static void s_ehword (int); |
17a2f251 TS |
1405 | static void s_cpadd (int); |
1406 | static void s_insn (int); | |
ba92f887 | 1407 | static void s_nan (int); |
919731af | 1408 | static void s_module (int); |
17a2f251 TS |
1409 | static void s_mips_ent (int); |
1410 | static void s_mips_end (int); | |
1411 | static void s_mips_frame (int); | |
1412 | static void s_mips_mask (int reg_type); | |
1413 | static void s_mips_stab (int); | |
1414 | static void s_mips_weakext (int); | |
1415 | static void s_mips_file (int); | |
1416 | static void s_mips_loc (int); | |
9e009953 | 1417 | static bfd_boolean pic_need_relax (symbolS *); |
4a6a3df4 | 1418 | static int relaxed_branch_length (fragS *, asection *, int); |
df58fc94 RS |
1419 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); |
1420 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
919731af | 1421 | static void file_mips_check_options (void); |
e7af610e NC |
1422 | |
1423 | /* Table and functions used to map between CPU/ISA names, and | |
1424 | ISA levels, and CPU numbers. */ | |
1425 | ||
e972090a NC |
1426 | struct mips_cpu_info |
1427 | { | |
e7af610e | 1428 | const char *name; /* CPU or ISA name. */ |
d16afab6 RS |
1429 | int flags; /* MIPS_CPU_* flags. */ |
1430 | int ase; /* Set of ASEs implemented by the CPU. */ | |
e7af610e NC |
1431 | int isa; /* ISA level. */ |
1432 | int cpu; /* CPU number (default CPU if ISA). */ | |
1433 | }; | |
1434 | ||
ad3fea08 | 1435 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
ad3fea08 | 1436 | |
17a2f251 TS |
1437 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1438 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1439 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 | 1440 | \f |
c31f3936 RS |
1441 | /* Command-line options. */ |
1442 | const char *md_shortopts = "O::g::G:"; | |
1443 | ||
1444 | enum options | |
1445 | { | |
1446 | OPTION_MARCH = OPTION_MD_BASE, | |
1447 | OPTION_MTUNE, | |
1448 | OPTION_MIPS1, | |
1449 | OPTION_MIPS2, | |
1450 | OPTION_MIPS3, | |
1451 | OPTION_MIPS4, | |
1452 | OPTION_MIPS5, | |
1453 | OPTION_MIPS32, | |
1454 | OPTION_MIPS64, | |
1455 | OPTION_MIPS32R2, | |
ae52f483 AB |
1456 | OPTION_MIPS32R3, |
1457 | OPTION_MIPS32R5, | |
7361da2c | 1458 | OPTION_MIPS32R6, |
c31f3936 | 1459 | OPTION_MIPS64R2, |
ae52f483 AB |
1460 | OPTION_MIPS64R3, |
1461 | OPTION_MIPS64R5, | |
7361da2c | 1462 | OPTION_MIPS64R6, |
c31f3936 RS |
1463 | OPTION_MIPS16, |
1464 | OPTION_NO_MIPS16, | |
1465 | OPTION_MIPS3D, | |
1466 | OPTION_NO_MIPS3D, | |
1467 | OPTION_MDMX, | |
1468 | OPTION_NO_MDMX, | |
1469 | OPTION_DSP, | |
1470 | OPTION_NO_DSP, | |
1471 | OPTION_MT, | |
1472 | OPTION_NO_MT, | |
1473 | OPTION_VIRT, | |
1474 | OPTION_NO_VIRT, | |
56d438b1 CF |
1475 | OPTION_MSA, |
1476 | OPTION_NO_MSA, | |
c31f3936 RS |
1477 | OPTION_SMARTMIPS, |
1478 | OPTION_NO_SMARTMIPS, | |
1479 | OPTION_DSPR2, | |
1480 | OPTION_NO_DSPR2, | |
8f4f9071 MF |
1481 | OPTION_DSPR3, |
1482 | OPTION_NO_DSPR3, | |
c31f3936 RS |
1483 | OPTION_EVA, |
1484 | OPTION_NO_EVA, | |
7d64c587 AB |
1485 | OPTION_XPA, |
1486 | OPTION_NO_XPA, | |
c31f3936 RS |
1487 | OPTION_MICROMIPS, |
1488 | OPTION_NO_MICROMIPS, | |
1489 | OPTION_MCU, | |
1490 | OPTION_NO_MCU, | |
25499ac7 MR |
1491 | OPTION_MIPS16E2, |
1492 | OPTION_NO_MIPS16E2, | |
730c3174 SE |
1493 | OPTION_CRC, |
1494 | OPTION_NO_CRC, | |
c31f3936 RS |
1495 | OPTION_M4650, |
1496 | OPTION_NO_M4650, | |
1497 | OPTION_M4010, | |
1498 | OPTION_NO_M4010, | |
1499 | OPTION_M4100, | |
1500 | OPTION_NO_M4100, | |
1501 | OPTION_M3900, | |
1502 | OPTION_NO_M3900, | |
1503 | OPTION_M7000_HILO_FIX, | |
1504 | OPTION_MNO_7000_HILO_FIX, | |
1505 | OPTION_FIX_24K, | |
1506 | OPTION_NO_FIX_24K, | |
a8d14a88 CM |
1507 | OPTION_FIX_RM7000, |
1508 | OPTION_NO_FIX_RM7000, | |
6f2117ba PH |
1509 | OPTION_FIX_LOONGSON3_LLSC, |
1510 | OPTION_NO_FIX_LOONGSON3_LLSC, | |
c31f3936 RS |
1511 | OPTION_FIX_LOONGSON2F_JUMP, |
1512 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
1513 | OPTION_FIX_LOONGSON2F_NOP, | |
1514 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
1515 | OPTION_FIX_VR4120, | |
1516 | OPTION_NO_FIX_VR4120, | |
1517 | OPTION_FIX_VR4130, | |
1518 | OPTION_NO_FIX_VR4130, | |
1519 | OPTION_FIX_CN63XXP1, | |
1520 | OPTION_NO_FIX_CN63XXP1, | |
27c634e0 FN |
1521 | OPTION_FIX_R5900, |
1522 | OPTION_NO_FIX_R5900, | |
c31f3936 RS |
1523 | OPTION_TRAP, |
1524 | OPTION_BREAK, | |
1525 | OPTION_EB, | |
1526 | OPTION_EL, | |
1527 | OPTION_FP32, | |
1528 | OPTION_GP32, | |
1529 | OPTION_CONSTRUCT_FLOATS, | |
1530 | OPTION_NO_CONSTRUCT_FLOATS, | |
1531 | OPTION_FP64, | |
351cdf24 | 1532 | OPTION_FPXX, |
c31f3936 RS |
1533 | OPTION_GP64, |
1534 | OPTION_RELAX_BRANCH, | |
1535 | OPTION_NO_RELAX_BRANCH, | |
8b10b0b3 MR |
1536 | OPTION_IGNORE_BRANCH_ISA, |
1537 | OPTION_NO_IGNORE_BRANCH_ISA, | |
833794fc MR |
1538 | OPTION_INSN32, |
1539 | OPTION_NO_INSN32, | |
c31f3936 RS |
1540 | OPTION_MSHARED, |
1541 | OPTION_MNO_SHARED, | |
1542 | OPTION_MSYM32, | |
1543 | OPTION_MNO_SYM32, | |
1544 | OPTION_SOFT_FLOAT, | |
1545 | OPTION_HARD_FLOAT, | |
1546 | OPTION_SINGLE_FLOAT, | |
1547 | OPTION_DOUBLE_FLOAT, | |
1548 | OPTION_32, | |
c31f3936 RS |
1549 | OPTION_CALL_SHARED, |
1550 | OPTION_CALL_NONPIC, | |
1551 | OPTION_NON_SHARED, | |
1552 | OPTION_XGOT, | |
1553 | OPTION_MABI, | |
1554 | OPTION_N32, | |
1555 | OPTION_64, | |
1556 | OPTION_MDEBUG, | |
1557 | OPTION_NO_MDEBUG, | |
1558 | OPTION_PDR, | |
1559 | OPTION_NO_PDR, | |
1560 | OPTION_MVXWORKS_PIC, | |
ba92f887 | 1561 | OPTION_NAN, |
351cdf24 MF |
1562 | OPTION_ODD_SPREG, |
1563 | OPTION_NO_ODD_SPREG, | |
6f20c942 FS |
1564 | OPTION_GINV, |
1565 | OPTION_NO_GINV, | |
8095d2f7 CX |
1566 | OPTION_LOONGSON_MMI, |
1567 | OPTION_NO_LOONGSON_MMI, | |
716c08de CX |
1568 | OPTION_LOONGSON_CAM, |
1569 | OPTION_NO_LOONGSON_CAM, | |
bdc6c06e CX |
1570 | OPTION_LOONGSON_EXT, |
1571 | OPTION_NO_LOONGSON_EXT, | |
a693765e CX |
1572 | OPTION_LOONGSON_EXT2, |
1573 | OPTION_NO_LOONGSON_EXT2, | |
c31f3936 RS |
1574 | OPTION_END_OF_ENUM |
1575 | }; | |
1576 | ||
1577 | struct option md_longopts[] = | |
1578 | { | |
1579 | /* Options which specify architecture. */ | |
1580 | {"march", required_argument, NULL, OPTION_MARCH}, | |
1581 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1582 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
1583 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
1584 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
1585 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
1586 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
1587 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
1588 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
1589 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
1590 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
ae52f483 AB |
1591 | {"mips32r3", no_argument, NULL, OPTION_MIPS32R3}, |
1592 | {"mips32r5", no_argument, NULL, OPTION_MIPS32R5}, | |
7361da2c | 1593 | {"mips32r6", no_argument, NULL, OPTION_MIPS32R6}, |
c31f3936 | 1594 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
ae52f483 AB |
1595 | {"mips64r3", no_argument, NULL, OPTION_MIPS64R3}, |
1596 | {"mips64r5", no_argument, NULL, OPTION_MIPS64R5}, | |
7361da2c | 1597 | {"mips64r6", no_argument, NULL, OPTION_MIPS64R6}, |
c31f3936 RS |
1598 | |
1599 | /* Options which specify Application Specific Extensions (ASEs). */ | |
1600 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
1601 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
1602 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
1603 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
1604 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
1605 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
1606 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
1607 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
1608 | {"mmt", no_argument, NULL, OPTION_MT}, | |
1609 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
1610 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
1611 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
1612 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, | |
1613 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, | |
8f4f9071 MF |
1614 | {"mdspr3", no_argument, NULL, OPTION_DSPR3}, |
1615 | {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3}, | |
c31f3936 RS |
1616 | {"meva", no_argument, NULL, OPTION_EVA}, |
1617 | {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, | |
1618 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, | |
1619 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
1620 | {"mmcu", no_argument, NULL, OPTION_MCU}, | |
1621 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
1622 | {"mvirt", no_argument, NULL, OPTION_VIRT}, | |
1623 | {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, | |
56d438b1 CF |
1624 | {"mmsa", no_argument, NULL, OPTION_MSA}, |
1625 | {"mno-msa", no_argument, NULL, OPTION_NO_MSA}, | |
7d64c587 AB |
1626 | {"mxpa", no_argument, NULL, OPTION_XPA}, |
1627 | {"mno-xpa", no_argument, NULL, OPTION_NO_XPA}, | |
25499ac7 MR |
1628 | {"mmips16e2", no_argument, NULL, OPTION_MIPS16E2}, |
1629 | {"mno-mips16e2", no_argument, NULL, OPTION_NO_MIPS16E2}, | |
730c3174 SE |
1630 | {"mcrc", no_argument, NULL, OPTION_CRC}, |
1631 | {"mno-crc", no_argument, NULL, OPTION_NO_CRC}, | |
6f20c942 FS |
1632 | {"mginv", no_argument, NULL, OPTION_GINV}, |
1633 | {"mno-ginv", no_argument, NULL, OPTION_NO_GINV}, | |
8095d2f7 CX |
1634 | {"mloongson-mmi", no_argument, NULL, OPTION_LOONGSON_MMI}, |
1635 | {"mno-loongson-mmi", no_argument, NULL, OPTION_NO_LOONGSON_MMI}, | |
716c08de CX |
1636 | {"mloongson-cam", no_argument, NULL, OPTION_LOONGSON_CAM}, |
1637 | {"mno-loongson-cam", no_argument, NULL, OPTION_NO_LOONGSON_CAM}, | |
bdc6c06e CX |
1638 | {"mloongson-ext", no_argument, NULL, OPTION_LOONGSON_EXT}, |
1639 | {"mno-loongson-ext", no_argument, NULL, OPTION_NO_LOONGSON_EXT}, | |
a693765e CX |
1640 | {"mloongson-ext2", no_argument, NULL, OPTION_LOONGSON_EXT2}, |
1641 | {"mno-loongson-ext2", no_argument, NULL, OPTION_NO_LOONGSON_EXT2}, | |
c31f3936 RS |
1642 | |
1643 | /* Old-style architecture options. Don't add more of these. */ | |
1644 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
1645 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
1646 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
1647 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
1648 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
1649 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
1650 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
1651 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
1652 | ||
1653 | /* Options which enable bug fixes. */ | |
1654 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
1655 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1656 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
6f2117ba PH |
1657 | {"mfix-loongson3-llsc", no_argument, NULL, OPTION_FIX_LOONGSON3_LLSC}, |
1658 | {"mno-fix-loongson3-llsc", no_argument, NULL, OPTION_NO_FIX_LOONGSON3_LLSC}, | |
c31f3936 RS |
1659 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
1660 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
1661 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
1662 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
1663 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
1664 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
1665 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
1666 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
1667 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, | |
1668 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
a8d14a88 CM |
1669 | {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000}, |
1670 | {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000}, | |
c31f3936 RS |
1671 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
1672 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
27c634e0 FN |
1673 | {"mfix-r5900", no_argument, NULL, OPTION_FIX_R5900}, |
1674 | {"mno-fix-r5900", no_argument, NULL, OPTION_NO_FIX_R5900}, | |
c31f3936 RS |
1675 | |
1676 | /* Miscellaneous options. */ | |
1677 | {"trap", no_argument, NULL, OPTION_TRAP}, | |
1678 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1679 | {"break", no_argument, NULL, OPTION_BREAK}, | |
1680 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1681 | {"EB", no_argument, NULL, OPTION_EB}, | |
1682 | {"EL", no_argument, NULL, OPTION_EL}, | |
1683 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
1684 | {"mgp32", no_argument, NULL, OPTION_GP32}, | |
1685 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, | |
1686 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, | |
1687 | {"mfp64", no_argument, NULL, OPTION_FP64}, | |
351cdf24 | 1688 | {"mfpxx", no_argument, NULL, OPTION_FPXX}, |
c31f3936 RS |
1689 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1690 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, | |
1691 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
8b10b0b3 MR |
1692 | {"mignore-branch-isa", no_argument, NULL, OPTION_IGNORE_BRANCH_ISA}, |
1693 | {"mno-ignore-branch-isa", no_argument, NULL, OPTION_NO_IGNORE_BRANCH_ISA}, | |
833794fc MR |
1694 | {"minsn32", no_argument, NULL, OPTION_INSN32}, |
1695 | {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32}, | |
c31f3936 RS |
1696 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
1697 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
1698 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
1699 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
1700 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, | |
1701 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
1702 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, | |
1703 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
351cdf24 MF |
1704 | {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG}, |
1705 | {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG}, | |
c31f3936 RS |
1706 | |
1707 | /* Strictly speaking this next option is ELF specific, | |
1708 | but we allow it for other ports as well in order to | |
1709 | make testing easier. */ | |
1710 | {"32", no_argument, NULL, OPTION_32}, | |
1711 | ||
1712 | /* ELF-specific options. */ | |
c31f3936 RS |
1713 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
1714 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
1715 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, | |
1716 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
1717 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
1718 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
1719 | {"n32", no_argument, NULL, OPTION_N32}, | |
1720 | {"64", no_argument, NULL, OPTION_64}, | |
1721 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
1722 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
1723 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
1724 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
1725 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ba92f887 | 1726 | {"mnan", required_argument, NULL, OPTION_NAN}, |
c31f3936 RS |
1727 | |
1728 | {NULL, no_argument, NULL, 0} | |
1729 | }; | |
1730 | size_t md_longopts_size = sizeof (md_longopts); | |
1731 | \f | |
c6278170 RS |
1732 | /* Information about either an Application Specific Extension or an |
1733 | optional architecture feature that, for simplicity, we treat in the | |
1734 | same way as an ASE. */ | |
1735 | struct mips_ase | |
1736 | { | |
1737 | /* The name of the ASE, used in both the command-line and .set options. */ | |
1738 | const char *name; | |
1739 | ||
1740 | /* The associated ASE_* flags. If the ASE is available on both 32-bit | |
1741 | and 64-bit architectures, the flags here refer to the subset that | |
1742 | is available on both. */ | |
1743 | unsigned int flags; | |
1744 | ||
1745 | /* The ASE_* flag used for instructions that are available on 64-bit | |
1746 | architectures but that are not included in FLAGS. */ | |
1747 | unsigned int flags64; | |
1748 | ||
1749 | /* The command-line options that turn the ASE on and off. */ | |
1750 | int option_on; | |
1751 | int option_off; | |
1752 | ||
1753 | /* The minimum required architecture revisions for MIPS32, MIPS64, | |
1754 | microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */ | |
1755 | int mips32_rev; | |
1756 | int mips64_rev; | |
1757 | int micromips32_rev; | |
1758 | int micromips64_rev; | |
7361da2c AB |
1759 | |
1760 | /* The architecture where the ASE was removed or -1 if the extension has not | |
1761 | been removed. */ | |
1762 | int rem_rev; | |
c6278170 RS |
1763 | }; |
1764 | ||
1765 | /* A table of all supported ASEs. */ | |
1766 | static const struct mips_ase mips_ases[] = { | |
1767 | { "dsp", ASE_DSP, ASE_DSP64, | |
1768 | OPTION_DSP, OPTION_NO_DSP, | |
7361da2c AB |
1769 | 2, 2, 2, 2, |
1770 | -1 }, | |
c6278170 RS |
1771 | |
1772 | { "dspr2", ASE_DSP | ASE_DSPR2, 0, | |
1773 | OPTION_DSPR2, OPTION_NO_DSPR2, | |
7361da2c AB |
1774 | 2, 2, 2, 2, |
1775 | -1 }, | |
c6278170 | 1776 | |
8f4f9071 MF |
1777 | { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0, |
1778 | OPTION_DSPR3, OPTION_NO_DSPR3, | |
1779 | 6, 6, -1, -1, | |
1780 | -1 }, | |
1781 | ||
c6278170 RS |
1782 | { "eva", ASE_EVA, 0, |
1783 | OPTION_EVA, OPTION_NO_EVA, | |
7361da2c AB |
1784 | 2, 2, 2, 2, |
1785 | -1 }, | |
c6278170 RS |
1786 | |
1787 | { "mcu", ASE_MCU, 0, | |
1788 | OPTION_MCU, OPTION_NO_MCU, | |
7361da2c AB |
1789 | 2, 2, 2, 2, |
1790 | -1 }, | |
c6278170 RS |
1791 | |
1792 | /* Deprecated in MIPS64r5, but we don't implement that yet. */ | |
1793 | { "mdmx", ASE_MDMX, 0, | |
1794 | OPTION_MDMX, OPTION_NO_MDMX, | |
7361da2c AB |
1795 | -1, 1, -1, -1, |
1796 | 6 }, | |
c6278170 RS |
1797 | |
1798 | /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */ | |
1799 | { "mips3d", ASE_MIPS3D, 0, | |
1800 | OPTION_MIPS3D, OPTION_NO_MIPS3D, | |
7361da2c AB |
1801 | 2, 1, -1, -1, |
1802 | 6 }, | |
c6278170 RS |
1803 | |
1804 | { "mt", ASE_MT, 0, | |
1805 | OPTION_MT, OPTION_NO_MT, | |
7361da2c AB |
1806 | 2, 2, -1, -1, |
1807 | -1 }, | |
c6278170 RS |
1808 | |
1809 | { "smartmips", ASE_SMARTMIPS, 0, | |
1810 | OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, | |
7361da2c AB |
1811 | 1, -1, -1, -1, |
1812 | 6 }, | |
c6278170 RS |
1813 | |
1814 | { "virt", ASE_VIRT, ASE_VIRT64, | |
1815 | OPTION_VIRT, OPTION_NO_VIRT, | |
7361da2c AB |
1816 | 2, 2, 2, 2, |
1817 | -1 }, | |
56d438b1 CF |
1818 | |
1819 | { "msa", ASE_MSA, ASE_MSA64, | |
1820 | OPTION_MSA, OPTION_NO_MSA, | |
7361da2c AB |
1821 | 2, 2, 2, 2, |
1822 | -1 }, | |
7d64c587 AB |
1823 | |
1824 | { "xpa", ASE_XPA, 0, | |
1825 | OPTION_XPA, OPTION_NO_XPA, | |
909b4e3d | 1826 | 2, 2, 2, 2, |
7361da2c | 1827 | -1 }, |
25499ac7 MR |
1828 | |
1829 | { "mips16e2", ASE_MIPS16E2, 0, | |
1830 | OPTION_MIPS16E2, OPTION_NO_MIPS16E2, | |
1831 | 2, 2, -1, -1, | |
1832 | 6 }, | |
730c3174 SE |
1833 | |
1834 | { "crc", ASE_CRC, ASE_CRC64, | |
1835 | OPTION_CRC, OPTION_NO_CRC, | |
1836 | 6, 6, -1, -1, | |
1837 | -1 }, | |
6f20c942 FS |
1838 | |
1839 | { "ginv", ASE_GINV, 0, | |
1840 | OPTION_GINV, OPTION_NO_GINV, | |
1841 | 6, 6, 6, 6, | |
1842 | -1 }, | |
8095d2f7 CX |
1843 | |
1844 | { "loongson-mmi", ASE_LOONGSON_MMI, 0, | |
1845 | OPTION_LOONGSON_MMI, OPTION_NO_LOONGSON_MMI, | |
1846 | 0, 0, -1, -1, | |
1847 | -1 }, | |
716c08de CX |
1848 | |
1849 | { "loongson-cam", ASE_LOONGSON_CAM, 0, | |
1850 | OPTION_LOONGSON_CAM, OPTION_NO_LOONGSON_CAM, | |
1851 | 0, 0, -1, -1, | |
1852 | -1 }, | |
bdc6c06e CX |
1853 | |
1854 | { "loongson-ext", ASE_LOONGSON_EXT, 0, | |
1855 | OPTION_LOONGSON_EXT, OPTION_NO_LOONGSON_EXT, | |
1856 | 0, 0, -1, -1, | |
1857 | -1 }, | |
a693765e CX |
1858 | |
1859 | { "loongson-ext2", ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2, 0, | |
1860 | OPTION_LOONGSON_EXT2, OPTION_NO_LOONGSON_EXT2, | |
1861 | 0, 0, -1, -1, | |
1862 | -1 }, | |
c6278170 RS |
1863 | }; |
1864 | ||
1865 | /* The set of ASEs that require -mfp64. */ | |
82bda27b | 1866 | #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA) |
c6278170 RS |
1867 | |
1868 | /* Groups of ASE_* flags that represent different revisions of an ASE. */ | |
1869 | static const unsigned int mips_ase_groups[] = { | |
a693765e CX |
1870 | ASE_DSP | ASE_DSPR2 | ASE_DSPR3, |
1871 | ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2 | |
c6278170 RS |
1872 | }; |
1873 | \f | |
252b5132 RH |
1874 | /* Pseudo-op table. |
1875 | ||
1876 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1877 | should be defined here, but are currently unsupported: .alias, | |
1878 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1879 | ||
1880 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1881 | specific to the type of debugging information being generated, and | |
1882 | should be defined by the object format: .aent, .begin, .bend, | |
1883 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1884 | .vreg. | |
1885 | ||
1886 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1887 | not MIPS CPU specific, but are also not specific to the object file | |
1888 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1889 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1890 | |
e972090a NC |
1891 | static const pseudo_typeS mips_pseudo_table[] = |
1892 | { | |
beae10d5 | 1893 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1894 | {"option", s_option, 0}, |
1895 | {"set", s_mipsset, 0}, | |
1896 | {"rdata", s_change_sec, 'r'}, | |
1897 | {"sdata", s_change_sec, 's'}, | |
1898 | {"livereg", s_ignore, 0}, | |
1899 | {"abicalls", s_abicalls, 0}, | |
1900 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1901 | {"cpsetup", s_cpsetup, 0}, |
1902 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1903 | {"cprestore", s_cprestore, 0}, |
6478892d | 1904 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1905 | {"dtprelword", s_dtprelword, 0}, |
1906 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1907 | {"tprelword", s_tprelword, 0}, |
1908 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1909 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1910 | {"gpword", s_gpword, 0}, |
10181a0d | 1911 | {"gpdword", s_gpdword, 0}, |
a3f278e2 | 1912 | {"ehword", s_ehword, 0}, |
252b5132 RH |
1913 | {"cpadd", s_cpadd, 0}, |
1914 | {"insn", s_insn, 0}, | |
ba92f887 | 1915 | {"nan", s_nan, 0}, |
919731af | 1916 | {"module", s_module, 0}, |
252b5132 | 1917 | |
beae10d5 | 1918 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1919 | chips. */ |
38a57ae7 | 1920 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1921 | {"bss", s_change_sec, 'b'}, |
1922 | {"err", s_err, 0}, | |
1923 | {"half", s_cons, 1}, | |
1924 | {"dword", s_cons, 3}, | |
1925 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1926 | {"origin", s_org, 0}, |
1927 | {"repeat", s_rept, 0}, | |
252b5132 | 1928 | |
998b3c36 MR |
1929 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1930 | {"sbss", s_change_sec, 'B'}, | |
1931 | ||
beae10d5 | 1932 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1933 | here for one reason or another. */ |
1934 | {"align", s_align, 0}, | |
1935 | {"byte", s_cons, 0}, | |
1936 | {"data", s_change_sec, 'd'}, | |
1937 | {"double", s_float_cons, 'd'}, | |
1938 | {"float", s_float_cons, 'f'}, | |
1939 | {"globl", s_mips_globl, 0}, | |
1940 | {"global", s_mips_globl, 0}, | |
1941 | {"hword", s_cons, 1}, | |
1942 | {"int", s_cons, 2}, | |
1943 | {"long", s_cons, 2}, | |
1944 | {"octa", s_cons, 4}, | |
1945 | {"quad", s_cons, 3}, | |
cca86cc8 | 1946 | {"section", s_change_section, 0}, |
252b5132 RH |
1947 | {"short", s_cons, 1}, |
1948 | {"single", s_float_cons, 'f'}, | |
754e2bb9 | 1949 | {"stabd", s_mips_stab, 'd'}, |
252b5132 | 1950 | {"stabn", s_mips_stab, 'n'}, |
754e2bb9 | 1951 | {"stabs", s_mips_stab, 's'}, |
252b5132 RH |
1952 | {"text", s_change_sec, 't'}, |
1953 | {"word", s_cons, 2}, | |
add56521 | 1954 | |
add56521 | 1955 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1956 | |
43841e91 | 1957 | { NULL, NULL, 0 }, |
252b5132 RH |
1958 | }; |
1959 | ||
e972090a NC |
1960 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1961 | { | |
beae10d5 KH |
1962 | /* These pseudo-ops should be defined by the object file format. |
1963 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1964 | {"aent", s_mips_ent, 1}, |
1965 | {"bgnb", s_ignore, 0}, | |
1966 | {"end", s_mips_end, 0}, | |
1967 | {"endb", s_ignore, 0}, | |
1968 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1969 | {"file", s_mips_file, 0}, |
252b5132 RH |
1970 | {"fmask", s_mips_mask, 'F'}, |
1971 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1972 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1973 | {"mask", s_mips_mask, 'R'}, |
1974 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1975 | { NULL, NULL, 0 }, |
252b5132 RH |
1976 | }; |
1977 | ||
3ae8dd8d MR |
1978 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1979 | purpose of the `.dc.a' internal pseudo-op. */ | |
1980 | ||
1981 | int | |
1982 | mips_address_bytes (void) | |
1983 | { | |
919731af | 1984 | file_mips_check_options (); |
3ae8dd8d MR |
1985 | return HAVE_64BIT_ADDRESSES ? 8 : 4; |
1986 | } | |
1987 | ||
17a2f251 | 1988 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1989 | |
1990 | void | |
17a2f251 | 1991 | mips_pop_insert (void) |
252b5132 RH |
1992 | { |
1993 | pop_insert (mips_pseudo_table); | |
1994 | if (! ECOFF_DEBUGGING) | |
1995 | pop_insert (mips_nonecoff_pseudo_table); | |
1996 | } | |
1997 | \f | |
1998 | /* Symbols labelling the current insn. */ | |
1999 | ||
e972090a NC |
2000 | struct insn_label_list |
2001 | { | |
252b5132 RH |
2002 | struct insn_label_list *next; |
2003 | symbolS *label; | |
2004 | }; | |
2005 | ||
252b5132 | 2006 | static struct insn_label_list *free_insn_labels; |
742a56fe | 2007 | #define label_list tc_segment_info_data.labels |
252b5132 | 2008 | |
17a2f251 | 2009 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
2010 | static void mips_mark_labels (void); |
2011 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
2012 | |
2013 | static inline void | |
17a2f251 | 2014 | mips_clear_insn_labels (void) |
252b5132 | 2015 | { |
ed9e98c2 | 2016 | struct insn_label_list **pl; |
a8dbcb85 | 2017 | segment_info_type *si; |
252b5132 | 2018 | |
a8dbcb85 TS |
2019 | if (now_seg) |
2020 | { | |
2021 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
2022 | ; | |
3739860c | 2023 | |
a8dbcb85 TS |
2024 | si = seg_info (now_seg); |
2025 | *pl = si->label_list; | |
2026 | si->label_list = NULL; | |
2027 | } | |
252b5132 | 2028 | } |
a8dbcb85 | 2029 | |
df58fc94 RS |
2030 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
2031 | ||
2032 | static inline void | |
2033 | mips_mark_labels (void) | |
2034 | { | |
2035 | if (HAVE_CODE_COMPRESSION) | |
2036 | mips_compressed_mark_labels (); | |
2037 | } | |
252b5132 RH |
2038 | \f |
2039 | static char *expr_end; | |
2040 | ||
e423441d | 2041 | /* An expression in a macro instruction. This is set by mips_ip and |
b0e6f033 | 2042 | mips16_ip and when populated is always an O_constant. */ |
252b5132 RH |
2043 | |
2044 | static expressionS imm_expr; | |
252b5132 | 2045 | |
77bd4346 RS |
2046 | /* The relocatable field in an instruction and the relocs associated |
2047 | with it. These variables are used for instructions like LUI and | |
2048 | JAL as well as true offsets. They are also used for address | |
2049 | operands in macros. */ | |
252b5132 | 2050 | |
77bd4346 | 2051 | static expressionS offset_expr; |
f6688943 TS |
2052 | static bfd_reloc_code_real_type offset_reloc[3] |
2053 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 2054 | |
df58fc94 RS |
2055 | /* This is set to the resulting size of the instruction to be produced |
2056 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
2057 | explicit size is supplied. */ | |
252b5132 | 2058 | |
df58fc94 | 2059 | static unsigned int forced_insn_length; |
252b5132 | 2060 | |
e1b47bd5 RS |
2061 | /* True if we are assembling an instruction. All dot symbols defined during |
2062 | this time should be treated as code labels. */ | |
2063 | ||
2064 | static bfd_boolean mips_assembling_insn; | |
2065 | ||
ecb4347a DJ |
2066 | /* The pdr segment for per procedure frame/regmask info. Not used for |
2067 | ECOFF debugging. */ | |
252b5132 RH |
2068 | |
2069 | static segT pdr_seg; | |
252b5132 | 2070 | |
e013f690 TS |
2071 | /* The default target format to use. */ |
2072 | ||
aeffff67 RS |
2073 | #if defined (TE_FreeBSD) |
2074 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
2075 | #elif defined (TE_TMIPS) | |
2076 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
2077 | #else | |
2078 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
2079 | #endif | |
2080 | ||
e013f690 | 2081 | const char * |
17a2f251 | 2082 | mips_target_format (void) |
e013f690 TS |
2083 | { |
2084 | switch (OUTPUT_FLAVOR) | |
2085 | { | |
e013f690 | 2086 | case bfd_target_elf_flavour: |
0a44bf69 RS |
2087 | #ifdef TE_VXWORKS |
2088 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
2089 | return (target_big_endian | |
2090 | ? "elf32-bigmips-vxworks" | |
2091 | : "elf32-littlemips-vxworks"); | |
2092 | #endif | |
e013f690 | 2093 | return (target_big_endian |
cfe86eaa | 2094 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 2095 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 2096 | : (HAVE_NEWABI |
aeffff67 RS |
2097 | ? ELF_TARGET ("elf32-n", "big") |
2098 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 2099 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 2100 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 2101 | : (HAVE_NEWABI |
aeffff67 RS |
2102 | ? ELF_TARGET ("elf32-n", "little") |
2103 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
2104 | default: |
2105 | abort (); | |
2106 | return NULL; | |
2107 | } | |
2108 | } | |
2109 | ||
c6278170 RS |
2110 | /* Return the ISA revision that is currently in use, or 0 if we are |
2111 | generating code for MIPS V or below. */ | |
2112 | ||
2113 | static int | |
2114 | mips_isa_rev (void) | |
2115 | { | |
2116 | if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) | |
2117 | return 2; | |
2118 | ||
ae52f483 AB |
2119 | if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3) |
2120 | return 3; | |
2121 | ||
2122 | if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5) | |
2123 | return 5; | |
2124 | ||
7361da2c AB |
2125 | if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6) |
2126 | return 6; | |
2127 | ||
c6278170 RS |
2128 | /* microMIPS implies revision 2 or above. */ |
2129 | if (mips_opts.micromips) | |
2130 | return 2; | |
2131 | ||
2132 | if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64) | |
2133 | return 1; | |
2134 | ||
2135 | return 0; | |
2136 | } | |
2137 | ||
2138 | /* Return the mask of all ASEs that are revisions of those in FLAGS. */ | |
2139 | ||
2140 | static unsigned int | |
2141 | mips_ase_mask (unsigned int flags) | |
2142 | { | |
2143 | unsigned int i; | |
2144 | ||
2145 | for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++) | |
2146 | if (flags & mips_ase_groups[i]) | |
2147 | flags |= mips_ase_groups[i]; | |
2148 | return flags; | |
2149 | } | |
2150 | ||
2151 | /* Check whether the current ISA supports ASE. Issue a warning if | |
2152 | appropriate. */ | |
2153 | ||
2154 | static void | |
2155 | mips_check_isa_supports_ase (const struct mips_ase *ase) | |
2156 | { | |
2157 | const char *base; | |
2158 | int min_rev, size; | |
2159 | static unsigned int warned_isa; | |
2160 | static unsigned int warned_fp32; | |
2161 | ||
2162 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
2163 | min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; | |
2164 | else | |
2165 | min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; | |
2166 | if ((min_rev < 0 || mips_isa_rev () < min_rev) | |
2167 | && (warned_isa & ase->flags) != ase->flags) | |
2168 | { | |
2169 | warned_isa |= ase->flags; | |
2170 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
2171 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
2172 | if (min_rev < 0) | |
1661c76c | 2173 | as_warn (_("the %d-bit %s architecture does not support the" |
c6278170 RS |
2174 | " `%s' extension"), size, base, ase->name); |
2175 | else | |
1661c76c | 2176 | as_warn (_("the `%s' extension requires %s%d revision %d or greater"), |
c6278170 RS |
2177 | ase->name, base, size, min_rev); |
2178 | } | |
7361da2c AB |
2179 | else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev) |
2180 | && (warned_isa & ase->flags) != ase->flags) | |
2181 | { | |
2182 | warned_isa |= ase->flags; | |
2183 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
2184 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
2185 | as_warn (_("the `%s' extension was removed in %s%d revision %d"), | |
2186 | ase->name, base, size, ase->rem_rev); | |
2187 | } | |
2188 | ||
c6278170 | 2189 | if ((ase->flags & FP64_ASES) |
0b35dfee | 2190 | && mips_opts.fp != 64 |
c6278170 RS |
2191 | && (warned_fp32 & ase->flags) != ase->flags) |
2192 | { | |
2193 | warned_fp32 |= ase->flags; | |
1661c76c | 2194 | as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name); |
c6278170 RS |
2195 | } |
2196 | } | |
2197 | ||
2198 | /* Check all enabled ASEs to see whether they are supported by the | |
2199 | chosen architecture. */ | |
2200 | ||
2201 | static void | |
2202 | mips_check_isa_supports_ases (void) | |
2203 | { | |
2204 | unsigned int i, mask; | |
2205 | ||
2206 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2207 | { | |
2208 | mask = mips_ase_mask (mips_ases[i].flags); | |
2209 | if ((mips_opts.ase & mask) == mips_ases[i].flags) | |
2210 | mips_check_isa_supports_ase (&mips_ases[i]); | |
2211 | } | |
2212 | } | |
2213 | ||
2214 | /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags | |
2215 | that were affected. */ | |
2216 | ||
2217 | static unsigned int | |
919731af | 2218 | mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, |
2219 | bfd_boolean enabled_p) | |
c6278170 RS |
2220 | { |
2221 | unsigned int mask; | |
2222 | ||
2223 | mask = mips_ase_mask (ase->flags); | |
919731af | 2224 | opts->ase &= ~mask; |
92cebb3d MR |
2225 | |
2226 | /* Clear combination ASE flags, which need to be recalculated based on | |
2227 | updated regular ASE settings. */ | |
41cee089 | 2228 | opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT | ASE_EVA_R6); |
92cebb3d | 2229 | |
c6278170 | 2230 | if (enabled_p) |
919731af | 2231 | opts->ase |= ase->flags; |
25499ac7 | 2232 | |
9785fc2a MR |
2233 | /* The Virtualization ASE has eXtended Physical Addressing (XPA) |
2234 | instructions which are only valid when both ASEs are enabled. | |
2235 | This sets the ASE_XPA_VIRT flag when both ASEs are present. */ | |
2236 | if ((opts->ase & (ASE_XPA | ASE_VIRT)) == (ASE_XPA | ASE_VIRT)) | |
2237 | { | |
2238 | opts->ase |= ASE_XPA_VIRT; | |
2239 | mask |= ASE_XPA_VIRT; | |
2240 | } | |
25499ac7 MR |
2241 | if ((opts->ase & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT)) |
2242 | { | |
2243 | opts->ase |= ASE_MIPS16E2_MT; | |
2244 | mask |= ASE_MIPS16E2_MT; | |
2245 | } | |
2246 | ||
41cee089 FS |
2247 | /* The EVA Extension has instructions which are only valid when the R6 ISA |
2248 | is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are | |
2249 | present. */ | |
2250 | if (((opts->ase & ASE_EVA) != 0) && ISA_IS_R6 (opts->isa)) | |
2251 | { | |
2252 | opts->ase |= ASE_EVA_R6; | |
2253 | mask |= ASE_EVA_R6; | |
2254 | } | |
2255 | ||
c6278170 RS |
2256 | return mask; |
2257 | } | |
2258 | ||
2259 | /* Return the ASE called NAME, or null if none. */ | |
2260 | ||
2261 | static const struct mips_ase * | |
2262 | mips_lookup_ase (const char *name) | |
2263 | { | |
2264 | unsigned int i; | |
2265 | ||
2266 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2267 | if (strcmp (name, mips_ases[i].name) == 0) | |
2268 | return &mips_ases[i]; | |
2269 | return NULL; | |
2270 | } | |
2271 | ||
df58fc94 | 2272 | /* Return the length of a microMIPS instruction in bytes. If bits of |
100b4f2e MR |
2273 | the mask beyond the low 16 are 0, then it is a 16-bit instruction, |
2274 | otherwise it is a 32-bit instruction. */ | |
df58fc94 RS |
2275 | |
2276 | static inline unsigned int | |
2277 | micromips_insn_length (const struct mips_opcode *mo) | |
2278 | { | |
7fd53920 | 2279 | return mips_opcode_32bit_p (mo) ? 4 : 2; |
df58fc94 RS |
2280 | } |
2281 | ||
5c04167a RS |
2282 | /* Return the length of MIPS16 instruction OPCODE. */ |
2283 | ||
2284 | static inline unsigned int | |
2285 | mips16_opcode_length (unsigned long opcode) | |
2286 | { | |
2287 | return (opcode >> 16) == 0 ? 2 : 4; | |
2288 | } | |
2289 | ||
1e915849 RS |
2290 | /* Return the length of instruction INSN. */ |
2291 | ||
2292 | static inline unsigned int | |
2293 | insn_length (const struct mips_cl_insn *insn) | |
2294 | { | |
df58fc94 RS |
2295 | if (mips_opts.micromips) |
2296 | return micromips_insn_length (insn->insn_mo); | |
2297 | else if (mips_opts.mips16) | |
5c04167a | 2298 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 2299 | else |
1e915849 | 2300 | return 4; |
1e915849 RS |
2301 | } |
2302 | ||
2303 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
2304 | ||
2305 | static void | |
2306 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
2307 | { | |
2308 | size_t i; | |
2309 | ||
2310 | insn->insn_mo = mo; | |
1e915849 RS |
2311 | insn->insn_opcode = mo->match; |
2312 | insn->frag = NULL; | |
2313 | insn->where = 0; | |
2314 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2315 | insn->fixp[i] = NULL; | |
2316 | insn->fixed_p = (mips_opts.noreorder > 0); | |
2317 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
2318 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 2319 | insn->complete_p = 0; |
e407c74b | 2320 | insn->cleared_p = 0; |
1e915849 RS |
2321 | } |
2322 | ||
fc76e730 RS |
2323 | /* Get a list of all the operands in INSN. */ |
2324 | ||
2325 | static const struct mips_operand_array * | |
2326 | insn_operands (const struct mips_cl_insn *insn) | |
2327 | { | |
2328 | if (insn->insn_mo >= &mips_opcodes[0] | |
2329 | && insn->insn_mo < &mips_opcodes[NUMOPCODES]) | |
2330 | return &mips_operands[insn->insn_mo - &mips_opcodes[0]]; | |
2331 | ||
2332 | if (insn->insn_mo >= &mips16_opcodes[0] | |
2333 | && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes]) | |
2334 | return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]]; | |
2335 | ||
2336 | if (insn->insn_mo >= µmips_opcodes[0] | |
2337 | && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes]) | |
2338 | return µmips_operands[insn->insn_mo - µmips_opcodes[0]]; | |
2339 | ||
2340 | abort (); | |
2341 | } | |
2342 | ||
2343 | /* Get a description of operand OPNO of INSN. */ | |
2344 | ||
2345 | static const struct mips_operand * | |
2346 | insn_opno (const struct mips_cl_insn *insn, unsigned opno) | |
2347 | { | |
2348 | const struct mips_operand_array *operands; | |
2349 | ||
2350 | operands = insn_operands (insn); | |
2351 | if (opno >= MAX_OPERANDS || !operands->operand[opno]) | |
2352 | abort (); | |
2353 | return operands->operand[opno]; | |
2354 | } | |
2355 | ||
e077a1c8 RS |
2356 | /* Install UVAL as the value of OPERAND in INSN. */ |
2357 | ||
2358 | static inline void | |
2359 | insn_insert_operand (struct mips_cl_insn *insn, | |
2360 | const struct mips_operand *operand, unsigned int uval) | |
2361 | { | |
25499ac7 MR |
2362 | if (mips_opts.mips16 |
2363 | && operand->type == OP_INT && operand->lsb == 0 | |
2364 | && mips_opcode_32bit_p (insn->insn_mo)) | |
2365 | insn->insn_opcode |= mips16_immed_extend (uval, operand->size); | |
2366 | else | |
2367 | insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval); | |
e077a1c8 RS |
2368 | } |
2369 | ||
fc76e730 RS |
2370 | /* Extract the value of OPERAND from INSN. */ |
2371 | ||
2372 | static inline unsigned | |
2373 | insn_extract_operand (const struct mips_cl_insn *insn, | |
2374 | const struct mips_operand *operand) | |
2375 | { | |
2376 | return mips_extract_operand (operand, insn->insn_opcode); | |
2377 | } | |
2378 | ||
df58fc94 | 2379 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
2380 | |
2381 | static void | |
df58fc94 | 2382 | mips_record_compressed_mode (void) |
742a56fe RS |
2383 | { |
2384 | segment_info_type *si; | |
2385 | ||
2386 | si = seg_info (now_seg); | |
2387 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
2388 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
2389 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
2390 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
2391 | } |
2392 | ||
4d68580a RS |
2393 | /* Read a standard MIPS instruction from BUF. */ |
2394 | ||
2395 | static unsigned long | |
2396 | read_insn (char *buf) | |
2397 | { | |
2398 | if (target_big_endian) | |
2399 | return bfd_getb32 ((bfd_byte *) buf); | |
2400 | else | |
2401 | return bfd_getl32 ((bfd_byte *) buf); | |
2402 | } | |
2403 | ||
2404 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
2405 | the next byte. */ | |
2406 | ||
2407 | static char * | |
2408 | write_insn (char *buf, unsigned int insn) | |
2409 | { | |
2410 | md_number_to_chars (buf, insn, 4); | |
2411 | return buf + 4; | |
2412 | } | |
2413 | ||
2414 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
2415 | has length LENGTH. */ | |
2416 | ||
2417 | static unsigned long | |
2418 | read_compressed_insn (char *buf, unsigned int length) | |
2419 | { | |
2420 | unsigned long insn; | |
2421 | unsigned int i; | |
2422 | ||
2423 | insn = 0; | |
2424 | for (i = 0; i < length; i += 2) | |
2425 | { | |
2426 | insn <<= 16; | |
2427 | if (target_big_endian) | |
2428 | insn |= bfd_getb16 ((char *) buf); | |
2429 | else | |
2430 | insn |= bfd_getl16 ((char *) buf); | |
2431 | buf += 2; | |
2432 | } | |
2433 | return insn; | |
2434 | } | |
2435 | ||
5c04167a RS |
2436 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
2437 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
2438 | ||
2439 | static char * | |
2440 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
2441 | { | |
2442 | unsigned int i; | |
2443 | ||
2444 | for (i = 0; i < length; i += 2) | |
2445 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
2446 | return buf + length; | |
2447 | } | |
2448 | ||
1e915849 RS |
2449 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
2450 | ||
2451 | static void | |
2452 | install_insn (const struct mips_cl_insn *insn) | |
2453 | { | |
2454 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
2455 | if (HAVE_CODE_COMPRESSION) |
2456 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 2457 | else |
4d68580a | 2458 | write_insn (f, insn->insn_opcode); |
df58fc94 | 2459 | mips_record_compressed_mode (); |
1e915849 RS |
2460 | } |
2461 | ||
2462 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
2463 | and install the opcode in the new location. */ | |
2464 | ||
2465 | static void | |
2466 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
2467 | { | |
2468 | size_t i; | |
2469 | ||
2470 | insn->frag = frag; | |
2471 | insn->where = where; | |
2472 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2473 | if (insn->fixp[i] != NULL) | |
2474 | { | |
2475 | insn->fixp[i]->fx_frag = frag; | |
2476 | insn->fixp[i]->fx_where = where; | |
2477 | } | |
2478 | install_insn (insn); | |
2479 | } | |
2480 | ||
2481 | /* Add INSN to the end of the output. */ | |
2482 | ||
2483 | static void | |
2484 | add_fixed_insn (struct mips_cl_insn *insn) | |
2485 | { | |
2486 | char *f = frag_more (insn_length (insn)); | |
2487 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
2488 | } | |
2489 | ||
2490 | /* Start a variant frag and move INSN to the start of the variant part, | |
2491 | marking it as fixed. The other arguments are as for frag_var. */ | |
2492 | ||
2493 | static void | |
2494 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
2495 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
2496 | { | |
2497 | frag_grow (max_chars); | |
2498 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
2499 | insn->fixed_p = 1; | |
2500 | frag_var (rs_machine_dependent, max_chars, var, | |
2501 | subtype, symbol, offset, NULL); | |
2502 | } | |
2503 | ||
2504 | /* Insert N copies of INSN into the history buffer, starting at | |
2505 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
2506 | ||
2507 | static void | |
2508 | insert_into_history (unsigned int first, unsigned int n, | |
2509 | const struct mips_cl_insn *insn) | |
2510 | { | |
2511 | if (mips_relax.sequence != 2) | |
2512 | { | |
2513 | unsigned int i; | |
2514 | ||
2515 | for (i = ARRAY_SIZE (history); i-- > first;) | |
2516 | if (i >= first + n) | |
2517 | history[i] = history[i - n]; | |
2518 | else | |
2519 | history[i] = *insn; | |
2520 | } | |
2521 | } | |
2522 | ||
e3de51ce RS |
2523 | /* Clear the error in insn_error. */ |
2524 | ||
2525 | static void | |
2526 | clear_insn_error (void) | |
2527 | { | |
2528 | memset (&insn_error, 0, sizeof (insn_error)); | |
2529 | } | |
2530 | ||
2531 | /* Possibly record error message MSG for the current instruction. | |
2532 | If the error is about a particular argument, ARGNUM is the 1-based | |
2533 | number of that argument, otherwise it is 0. FORMAT is the format | |
2534 | of MSG. Return true if MSG was used, false if the current message | |
2535 | was kept. */ | |
2536 | ||
2537 | static bfd_boolean | |
2538 | set_insn_error_format (int argnum, enum mips_insn_error_format format, | |
2539 | const char *msg) | |
2540 | { | |
2541 | if (argnum == 0) | |
2542 | { | |
2543 | /* Give priority to errors against specific arguments, and to | |
2544 | the first whole-instruction message. */ | |
2545 | if (insn_error.msg) | |
2546 | return FALSE; | |
2547 | } | |
2548 | else | |
2549 | { | |
2550 | /* Keep insn_error if it is against a later argument. */ | |
2551 | if (argnum < insn_error.min_argnum) | |
2552 | return FALSE; | |
2553 | ||
2554 | /* If both errors are against the same argument but are different, | |
2555 | give up on reporting a specific error for this argument. | |
2556 | See the comment about mips_insn_error for details. */ | |
2557 | if (argnum == insn_error.min_argnum | |
2558 | && insn_error.msg | |
2559 | && strcmp (insn_error.msg, msg) != 0) | |
2560 | { | |
2561 | insn_error.msg = 0; | |
2562 | insn_error.min_argnum += 1; | |
2563 | return FALSE; | |
2564 | } | |
2565 | } | |
2566 | insn_error.min_argnum = argnum; | |
2567 | insn_error.format = format; | |
2568 | insn_error.msg = msg; | |
2569 | return TRUE; | |
2570 | } | |
2571 | ||
2572 | /* Record an instruction error with no % format fields. ARGNUM and MSG are | |
2573 | as for set_insn_error_format. */ | |
2574 | ||
2575 | static void | |
2576 | set_insn_error (int argnum, const char *msg) | |
2577 | { | |
2578 | set_insn_error_format (argnum, ERR_FMT_PLAIN, msg); | |
2579 | } | |
2580 | ||
2581 | /* Record an instruction error with one %d field I. ARGNUM and MSG are | |
2582 | as for set_insn_error_format. */ | |
2583 | ||
2584 | static void | |
2585 | set_insn_error_i (int argnum, const char *msg, int i) | |
2586 | { | |
2587 | if (set_insn_error_format (argnum, ERR_FMT_I, msg)) | |
2588 | insn_error.u.i = i; | |
2589 | } | |
2590 | ||
2591 | /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG | |
2592 | are as for set_insn_error_format. */ | |
2593 | ||
2594 | static void | |
2595 | set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2) | |
2596 | { | |
2597 | if (set_insn_error_format (argnum, ERR_FMT_SS, msg)) | |
2598 | { | |
2599 | insn_error.u.ss[0] = s1; | |
2600 | insn_error.u.ss[1] = s2; | |
2601 | } | |
2602 | } | |
2603 | ||
2604 | /* Report the error in insn_error, which is against assembly code STR. */ | |
2605 | ||
2606 | static void | |
2607 | report_insn_error (const char *str) | |
2608 | { | |
e1fa0163 | 2609 | const char *msg = concat (insn_error.msg, " `%s'", NULL); |
e3de51ce | 2610 | |
e3de51ce RS |
2611 | switch (insn_error.format) |
2612 | { | |
2613 | case ERR_FMT_PLAIN: | |
2614 | as_bad (msg, str); | |
2615 | break; | |
2616 | ||
2617 | case ERR_FMT_I: | |
2618 | as_bad (msg, insn_error.u.i, str); | |
2619 | break; | |
2620 | ||
2621 | case ERR_FMT_SS: | |
2622 | as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str); | |
2623 | break; | |
2624 | } | |
e1fa0163 NC |
2625 | |
2626 | free ((char *) msg); | |
e3de51ce RS |
2627 | } |
2628 | ||
71400594 RS |
2629 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
2630 | the idea is to make it obvious at a glance that each errata is | |
2631 | included. */ | |
2632 | ||
2633 | static void | |
2634 | init_vr4120_conflicts (void) | |
2635 | { | |
2636 | #define CONFLICT(FIRST, SECOND) \ | |
2637 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
2638 | ||
2639 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
2640 | CONFLICT (MACC, DIV); | |
2641 | CONFLICT (DMACC, DIV); | |
2642 | ||
2643 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
2644 | CONFLICT (DMULT, DMULT); | |
2645 | CONFLICT (DMULT, DMACC); | |
2646 | CONFLICT (DMACC, DMULT); | |
2647 | CONFLICT (DMACC, DMACC); | |
2648 | ||
2649 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
2650 | CONFLICT (MACC, MTHILO); | |
2651 | CONFLICT (DMACC, MTHILO); | |
2652 | ||
2653 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
2654 | instruction is executed immediately after a MACC or DMACC | |
2655 | instruction, the result of [either instruction] is incorrect." */ | |
2656 | CONFLICT (MACC, MULT); | |
2657 | CONFLICT (MACC, DMULT); | |
2658 | CONFLICT (DMACC, MULT); | |
2659 | CONFLICT (DMACC, DMULT); | |
2660 | ||
2661 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
2662 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
2663 | DDIV or DDIVU instruction, the result of the MACC or | |
2664 | DMACC instruction is incorrect.". */ | |
2665 | CONFLICT (DMULT, MACC); | |
2666 | CONFLICT (DMULT, DMACC); | |
2667 | CONFLICT (DIV, MACC); | |
2668 | CONFLICT (DIV, DMACC); | |
2669 | ||
2670 | #undef CONFLICT | |
2671 | } | |
2672 | ||
707bfff6 TS |
2673 | struct regname { |
2674 | const char *name; | |
2675 | unsigned int num; | |
2676 | }; | |
2677 | ||
14daeee3 | 2678 | #define RNUM_MASK 0x00000ff |
56d438b1 | 2679 | #define RTYPE_MASK 0x0ffff00 |
14daeee3 RS |
2680 | #define RTYPE_NUM 0x0000100 |
2681 | #define RTYPE_FPU 0x0000200 | |
2682 | #define RTYPE_FCC 0x0000400 | |
2683 | #define RTYPE_VEC 0x0000800 | |
2684 | #define RTYPE_GP 0x0001000 | |
2685 | #define RTYPE_CP0 0x0002000 | |
2686 | #define RTYPE_PC 0x0004000 | |
2687 | #define RTYPE_ACC 0x0008000 | |
2688 | #define RTYPE_CCC 0x0010000 | |
2689 | #define RTYPE_VI 0x0020000 | |
2690 | #define RTYPE_VF 0x0040000 | |
2691 | #define RTYPE_R5900_I 0x0080000 | |
2692 | #define RTYPE_R5900_Q 0x0100000 | |
2693 | #define RTYPE_R5900_R 0x0200000 | |
2694 | #define RTYPE_R5900_ACC 0x0400000 | |
56d438b1 | 2695 | #define RTYPE_MSA 0x0800000 |
14daeee3 | 2696 | #define RWARN 0x8000000 |
707bfff6 TS |
2697 | |
2698 | #define GENERIC_REGISTER_NUMBERS \ | |
2699 | {"$0", RTYPE_NUM | 0}, \ | |
2700 | {"$1", RTYPE_NUM | 1}, \ | |
2701 | {"$2", RTYPE_NUM | 2}, \ | |
2702 | {"$3", RTYPE_NUM | 3}, \ | |
2703 | {"$4", RTYPE_NUM | 4}, \ | |
2704 | {"$5", RTYPE_NUM | 5}, \ | |
2705 | {"$6", RTYPE_NUM | 6}, \ | |
2706 | {"$7", RTYPE_NUM | 7}, \ | |
2707 | {"$8", RTYPE_NUM | 8}, \ | |
2708 | {"$9", RTYPE_NUM | 9}, \ | |
2709 | {"$10", RTYPE_NUM | 10}, \ | |
2710 | {"$11", RTYPE_NUM | 11}, \ | |
2711 | {"$12", RTYPE_NUM | 12}, \ | |
2712 | {"$13", RTYPE_NUM | 13}, \ | |
2713 | {"$14", RTYPE_NUM | 14}, \ | |
2714 | {"$15", RTYPE_NUM | 15}, \ | |
2715 | {"$16", RTYPE_NUM | 16}, \ | |
2716 | {"$17", RTYPE_NUM | 17}, \ | |
2717 | {"$18", RTYPE_NUM | 18}, \ | |
2718 | {"$19", RTYPE_NUM | 19}, \ | |
2719 | {"$20", RTYPE_NUM | 20}, \ | |
2720 | {"$21", RTYPE_NUM | 21}, \ | |
2721 | {"$22", RTYPE_NUM | 22}, \ | |
2722 | {"$23", RTYPE_NUM | 23}, \ | |
2723 | {"$24", RTYPE_NUM | 24}, \ | |
2724 | {"$25", RTYPE_NUM | 25}, \ | |
2725 | {"$26", RTYPE_NUM | 26}, \ | |
2726 | {"$27", RTYPE_NUM | 27}, \ | |
2727 | {"$28", RTYPE_NUM | 28}, \ | |
2728 | {"$29", RTYPE_NUM | 29}, \ | |
2729 | {"$30", RTYPE_NUM | 30}, \ | |
3739860c | 2730 | {"$31", RTYPE_NUM | 31} |
707bfff6 TS |
2731 | |
2732 | #define FPU_REGISTER_NAMES \ | |
2733 | {"$f0", RTYPE_FPU | 0}, \ | |
2734 | {"$f1", RTYPE_FPU | 1}, \ | |
2735 | {"$f2", RTYPE_FPU | 2}, \ | |
2736 | {"$f3", RTYPE_FPU | 3}, \ | |
2737 | {"$f4", RTYPE_FPU | 4}, \ | |
2738 | {"$f5", RTYPE_FPU | 5}, \ | |
2739 | {"$f6", RTYPE_FPU | 6}, \ | |
2740 | {"$f7", RTYPE_FPU | 7}, \ | |
2741 | {"$f8", RTYPE_FPU | 8}, \ | |
2742 | {"$f9", RTYPE_FPU | 9}, \ | |
2743 | {"$f10", RTYPE_FPU | 10}, \ | |
2744 | {"$f11", RTYPE_FPU | 11}, \ | |
2745 | {"$f12", RTYPE_FPU | 12}, \ | |
2746 | {"$f13", RTYPE_FPU | 13}, \ | |
2747 | {"$f14", RTYPE_FPU | 14}, \ | |
2748 | {"$f15", RTYPE_FPU | 15}, \ | |
2749 | {"$f16", RTYPE_FPU | 16}, \ | |
2750 | {"$f17", RTYPE_FPU | 17}, \ | |
2751 | {"$f18", RTYPE_FPU | 18}, \ | |
2752 | {"$f19", RTYPE_FPU | 19}, \ | |
2753 | {"$f20", RTYPE_FPU | 20}, \ | |
2754 | {"$f21", RTYPE_FPU | 21}, \ | |
2755 | {"$f22", RTYPE_FPU | 22}, \ | |
2756 | {"$f23", RTYPE_FPU | 23}, \ | |
2757 | {"$f24", RTYPE_FPU | 24}, \ | |
2758 | {"$f25", RTYPE_FPU | 25}, \ | |
2759 | {"$f26", RTYPE_FPU | 26}, \ | |
2760 | {"$f27", RTYPE_FPU | 27}, \ | |
2761 | {"$f28", RTYPE_FPU | 28}, \ | |
2762 | {"$f29", RTYPE_FPU | 29}, \ | |
2763 | {"$f30", RTYPE_FPU | 30}, \ | |
2764 | {"$f31", RTYPE_FPU | 31} | |
2765 | ||
2766 | #define FPU_CONDITION_CODE_NAMES \ | |
2767 | {"$fcc0", RTYPE_FCC | 0}, \ | |
2768 | {"$fcc1", RTYPE_FCC | 1}, \ | |
2769 | {"$fcc2", RTYPE_FCC | 2}, \ | |
2770 | {"$fcc3", RTYPE_FCC | 3}, \ | |
2771 | {"$fcc4", RTYPE_FCC | 4}, \ | |
2772 | {"$fcc5", RTYPE_FCC | 5}, \ | |
2773 | {"$fcc6", RTYPE_FCC | 6}, \ | |
2774 | {"$fcc7", RTYPE_FCC | 7} | |
2775 | ||
2776 | #define COPROC_CONDITION_CODE_NAMES \ | |
2777 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
2778 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
2779 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
2780 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
2781 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
2782 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
2783 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
2784 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
2785 | ||
2786 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
2787 | {"$a4", RTYPE_GP | 8}, \ | |
2788 | {"$a5", RTYPE_GP | 9}, \ | |
2789 | {"$a6", RTYPE_GP | 10}, \ | |
2790 | {"$a7", RTYPE_GP | 11}, \ | |
2791 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
2792 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
2793 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
2794 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
2795 | {"$t0", RTYPE_GP | 12}, \ | |
2796 | {"$t1", RTYPE_GP | 13}, \ | |
2797 | {"$t2", RTYPE_GP | 14}, \ | |
2798 | {"$t3", RTYPE_GP | 15} | |
2799 | ||
2800 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2801 | {"$t0", RTYPE_GP | 8}, \ | |
2802 | {"$t1", RTYPE_GP | 9}, \ | |
2803 | {"$t2", RTYPE_GP | 10}, \ | |
2804 | {"$t3", RTYPE_GP | 11}, \ | |
2805 | {"$t4", RTYPE_GP | 12}, \ | |
2806 | {"$t5", RTYPE_GP | 13}, \ | |
2807 | {"$t6", RTYPE_GP | 14}, \ | |
2808 | {"$t7", RTYPE_GP | 15}, \ | |
2809 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2810 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2811 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
3739860c | 2812 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ |
707bfff6 | 2813 | |
6f2117ba | 2814 | /* Remaining symbolic register names. */ |
707bfff6 TS |
2815 | #define SYMBOLIC_REGISTER_NAMES \ |
2816 | {"$zero", RTYPE_GP | 0}, \ | |
2817 | {"$at", RTYPE_GP | 1}, \ | |
2818 | {"$AT", RTYPE_GP | 1}, \ | |
2819 | {"$v0", RTYPE_GP | 2}, \ | |
2820 | {"$v1", RTYPE_GP | 3}, \ | |
2821 | {"$a0", RTYPE_GP | 4}, \ | |
2822 | {"$a1", RTYPE_GP | 5}, \ | |
2823 | {"$a2", RTYPE_GP | 6}, \ | |
2824 | {"$a3", RTYPE_GP | 7}, \ | |
2825 | {"$s0", RTYPE_GP | 16}, \ | |
2826 | {"$s1", RTYPE_GP | 17}, \ | |
2827 | {"$s2", RTYPE_GP | 18}, \ | |
2828 | {"$s3", RTYPE_GP | 19}, \ | |
2829 | {"$s4", RTYPE_GP | 20}, \ | |
2830 | {"$s5", RTYPE_GP | 21}, \ | |
2831 | {"$s6", RTYPE_GP | 22}, \ | |
2832 | {"$s7", RTYPE_GP | 23}, \ | |
2833 | {"$t8", RTYPE_GP | 24}, \ | |
2834 | {"$t9", RTYPE_GP | 25}, \ | |
2835 | {"$k0", RTYPE_GP | 26}, \ | |
2836 | {"$kt0", RTYPE_GP | 26}, \ | |
2837 | {"$k1", RTYPE_GP | 27}, \ | |
2838 | {"$kt1", RTYPE_GP | 27}, \ | |
2839 | {"$gp", RTYPE_GP | 28}, \ | |
2840 | {"$sp", RTYPE_GP | 29}, \ | |
2841 | {"$s8", RTYPE_GP | 30}, \ | |
2842 | {"$fp", RTYPE_GP | 30}, \ | |
2843 | {"$ra", RTYPE_GP | 31} | |
2844 | ||
2845 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2846 | {"$pc", RTYPE_PC | 0} | |
2847 | ||
2848 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
6f2117ba PH |
2849 | /* {"$v0", RTYPE_VEC | 0}, Clash with REG 2 above. */ \ |
2850 | /* {"$v1", RTYPE_VEC | 1}, Clash with REG 3 above. */ \ | |
707bfff6 TS |
2851 | {"$v2", RTYPE_VEC | 2}, \ |
2852 | {"$v3", RTYPE_VEC | 3}, \ | |
2853 | {"$v4", RTYPE_VEC | 4}, \ | |
2854 | {"$v5", RTYPE_VEC | 5}, \ | |
2855 | {"$v6", RTYPE_VEC | 6}, \ | |
2856 | {"$v7", RTYPE_VEC | 7}, \ | |
2857 | {"$v8", RTYPE_VEC | 8}, \ | |
2858 | {"$v9", RTYPE_VEC | 9}, \ | |
2859 | {"$v10", RTYPE_VEC | 10}, \ | |
2860 | {"$v11", RTYPE_VEC | 11}, \ | |
2861 | {"$v12", RTYPE_VEC | 12}, \ | |
2862 | {"$v13", RTYPE_VEC | 13}, \ | |
2863 | {"$v14", RTYPE_VEC | 14}, \ | |
2864 | {"$v15", RTYPE_VEC | 15}, \ | |
2865 | {"$v16", RTYPE_VEC | 16}, \ | |
2866 | {"$v17", RTYPE_VEC | 17}, \ | |
2867 | {"$v18", RTYPE_VEC | 18}, \ | |
2868 | {"$v19", RTYPE_VEC | 19}, \ | |
2869 | {"$v20", RTYPE_VEC | 20}, \ | |
2870 | {"$v21", RTYPE_VEC | 21}, \ | |
2871 | {"$v22", RTYPE_VEC | 22}, \ | |
2872 | {"$v23", RTYPE_VEC | 23}, \ | |
2873 | {"$v24", RTYPE_VEC | 24}, \ | |
2874 | {"$v25", RTYPE_VEC | 25}, \ | |
2875 | {"$v26", RTYPE_VEC | 26}, \ | |
2876 | {"$v27", RTYPE_VEC | 27}, \ | |
2877 | {"$v28", RTYPE_VEC | 28}, \ | |
2878 | {"$v29", RTYPE_VEC | 29}, \ | |
2879 | {"$v30", RTYPE_VEC | 30}, \ | |
2880 | {"$v31", RTYPE_VEC | 31} | |
2881 | ||
14daeee3 RS |
2882 | #define R5900_I_NAMES \ |
2883 | {"$I", RTYPE_R5900_I | 0} | |
2884 | ||
2885 | #define R5900_Q_NAMES \ | |
2886 | {"$Q", RTYPE_R5900_Q | 0} | |
2887 | ||
2888 | #define R5900_R_NAMES \ | |
2889 | {"$R", RTYPE_R5900_R | 0} | |
2890 | ||
2891 | #define R5900_ACC_NAMES \ | |
2892 | {"$ACC", RTYPE_R5900_ACC | 0 } | |
2893 | ||
707bfff6 TS |
2894 | #define MIPS_DSP_ACCUMULATOR_NAMES \ |
2895 | {"$ac0", RTYPE_ACC | 0}, \ | |
2896 | {"$ac1", RTYPE_ACC | 1}, \ | |
2897 | {"$ac2", RTYPE_ACC | 2}, \ | |
2898 | {"$ac3", RTYPE_ACC | 3} | |
2899 | ||
2900 | static const struct regname reg_names[] = { | |
2901 | GENERIC_REGISTER_NUMBERS, | |
2902 | FPU_REGISTER_NAMES, | |
2903 | FPU_CONDITION_CODE_NAMES, | |
2904 | COPROC_CONDITION_CODE_NAMES, | |
2905 | ||
2906 | /* The $txx registers depends on the abi, | |
2907 | these will be added later into the symbol table from | |
3739860c | 2908 | one of the tables below once mips_abi is set after |
707bfff6 TS |
2909 | parsing of arguments from the command line. */ |
2910 | SYMBOLIC_REGISTER_NAMES, | |
2911 | ||
2912 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2913 | MDMX_VECTOR_REGISTER_NAMES, | |
14daeee3 RS |
2914 | R5900_I_NAMES, |
2915 | R5900_Q_NAMES, | |
2916 | R5900_R_NAMES, | |
2917 | R5900_ACC_NAMES, | |
707bfff6 TS |
2918 | MIPS_DSP_ACCUMULATOR_NAMES, |
2919 | {0, 0} | |
2920 | }; | |
2921 | ||
2922 | static const struct regname reg_names_o32[] = { | |
2923 | O32_SYMBOLIC_REGISTER_NAMES, | |
2924 | {0, 0} | |
2925 | }; | |
2926 | ||
2927 | static const struct regname reg_names_n32n64[] = { | |
2928 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2929 | {0, 0} | |
2930 | }; | |
2931 | ||
a92713e6 RS |
2932 | /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be |
2933 | interpreted as vector registers 0 and 1. If SYMVAL is the value of one | |
2934 | of these register symbols, return the associated vector register, | |
2935 | otherwise return SYMVAL itself. */ | |
df58fc94 | 2936 | |
a92713e6 RS |
2937 | static unsigned int |
2938 | mips_prefer_vec_regno (unsigned int symval) | |
707bfff6 | 2939 | { |
a92713e6 RS |
2940 | if ((symval & -2) == (RTYPE_GP | 2)) |
2941 | return RTYPE_VEC | (symval & 1); | |
2942 | return symval; | |
2943 | } | |
2944 | ||
14daeee3 RS |
2945 | /* Return true if string [S, E) is a valid register name, storing its |
2946 | symbol value in *SYMVAL_PTR if so. */ | |
a92713e6 RS |
2947 | |
2948 | static bfd_boolean | |
14daeee3 | 2949 | mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr) |
a92713e6 | 2950 | { |
707bfff6 | 2951 | char save_c; |
14daeee3 | 2952 | symbolS *symbol; |
707bfff6 TS |
2953 | |
2954 | /* Terminate name. */ | |
2955 | save_c = *e; | |
2956 | *e = '\0'; | |
2957 | ||
a92713e6 RS |
2958 | /* Look up the name. */ |
2959 | symbol = symbol_find (s); | |
2960 | *e = save_c; | |
2961 | ||
2962 | if (!symbol || S_GET_SEGMENT (symbol) != reg_section) | |
2963 | return FALSE; | |
2964 | ||
14daeee3 RS |
2965 | *symval_ptr = S_GET_VALUE (symbol); |
2966 | return TRUE; | |
2967 | } | |
2968 | ||
2969 | /* Return true if the string at *SPTR is a valid register name. Allow it | |
2970 | to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR | |
2971 | is nonnull. | |
2972 | ||
2973 | When returning true, move *SPTR past the register, store the | |
2974 | register's symbol value in *SYMVAL_PTR and the channel mask in | |
2975 | *CHANNELS_PTR (if nonnull). The symbol value includes the register | |
2976 | number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask | |
2977 | is a 4-bit value of the form XYZW and is 0 if no suffix was given. */ | |
2978 | ||
2979 | static bfd_boolean | |
2980 | mips_parse_register (char **sptr, unsigned int *symval_ptr, | |
2981 | unsigned int *channels_ptr) | |
2982 | { | |
2983 | char *s, *e, *m; | |
2984 | const char *q; | |
2985 | unsigned int channels, symval, bit; | |
2986 | ||
2987 | /* Find end of name. */ | |
2988 | s = e = *sptr; | |
2989 | if (is_name_beginner (*e)) | |
2990 | ++e; | |
2991 | while (is_part_of_name (*e)) | |
2992 | ++e; | |
2993 | ||
2994 | channels = 0; | |
2995 | if (!mips_parse_register_1 (s, e, &symval)) | |
2996 | { | |
2997 | if (!channels_ptr) | |
2998 | return FALSE; | |
2999 | ||
3000 | /* Eat characters from the end of the string that are valid | |
3001 | channel suffixes. The preceding register must be $ACC or | |
3002 | end with a digit, so there is no ambiguity. */ | |
3003 | bit = 1; | |
3004 | m = e; | |
3005 | for (q = "wzyx"; *q; q++, bit <<= 1) | |
3006 | if (m > s && m[-1] == *q) | |
3007 | { | |
3008 | --m; | |
3009 | channels |= bit; | |
3010 | } | |
3011 | ||
3012 | if (channels == 0 | |
3013 | || !mips_parse_register_1 (s, m, &symval) | |
3014 | || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0) | |
3015 | return FALSE; | |
3016 | } | |
3017 | ||
a92713e6 | 3018 | *sptr = e; |
14daeee3 RS |
3019 | *symval_ptr = symval; |
3020 | if (channels_ptr) | |
3021 | *channels_ptr = channels; | |
a92713e6 RS |
3022 | return TRUE; |
3023 | } | |
3024 | ||
3025 | /* Check if SPTR points at a valid register specifier according to TYPES. | |
3026 | If so, then return 1, advance S to consume the specifier and store | |
3027 | the register's number in REGNOP, otherwise return 0. */ | |
3028 | ||
3029 | static int | |
3030 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
3031 | { | |
3032 | unsigned int regno; | |
3033 | ||
14daeee3 | 3034 | if (mips_parse_register (s, ®no, NULL)) |
707bfff6 | 3035 | { |
a92713e6 RS |
3036 | if (types & RTYPE_VEC) |
3037 | regno = mips_prefer_vec_regno (regno); | |
3038 | if (regno & types) | |
3039 | regno &= RNUM_MASK; | |
3040 | else | |
3041 | regno = ~0; | |
707bfff6 | 3042 | } |
a92713e6 | 3043 | else |
707bfff6 | 3044 | { |
a92713e6 | 3045 | if (types & RWARN) |
1661c76c | 3046 | as_warn (_("unrecognized register name `%s'"), *s); |
a92713e6 | 3047 | regno = ~0; |
707bfff6 | 3048 | } |
707bfff6 | 3049 | if (regnop) |
a92713e6 RS |
3050 | *regnop = regno; |
3051 | return regno <= RNUM_MASK; | |
707bfff6 TS |
3052 | } |
3053 | ||
14daeee3 RS |
3054 | /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated |
3055 | mask in *CHANNELS. Return a pointer to the first unconsumed character. */ | |
3056 | ||
3057 | static char * | |
3058 | mips_parse_vu0_channels (char *s, unsigned int *channels) | |
3059 | { | |
3060 | unsigned int i; | |
3061 | ||
3062 | *channels = 0; | |
3063 | for (i = 0; i < 4; i++) | |
3064 | if (*s == "xyzw"[i]) | |
3065 | { | |
3066 | *channels |= 1 << (3 - i); | |
3067 | ++s; | |
3068 | } | |
3069 | return s; | |
3070 | } | |
3071 | ||
a92713e6 RS |
3072 | /* Token types for parsed operand lists. */ |
3073 | enum mips_operand_token_type { | |
3074 | /* A plain register, e.g. $f2. */ | |
3075 | OT_REG, | |
df58fc94 | 3076 | |
14daeee3 RS |
3077 | /* A 4-bit XYZW channel mask. */ |
3078 | OT_CHANNELS, | |
3079 | ||
56d438b1 CF |
3080 | /* A constant vector index, e.g. [1]. */ |
3081 | OT_INTEGER_INDEX, | |
3082 | ||
3083 | /* A register vector index, e.g. [$2]. */ | |
3084 | OT_REG_INDEX, | |
df58fc94 | 3085 | |
a92713e6 RS |
3086 | /* A continuous range of registers, e.g. $s0-$s4. */ |
3087 | OT_REG_RANGE, | |
3088 | ||
3089 | /* A (possibly relocated) expression. */ | |
3090 | OT_INTEGER, | |
3091 | ||
3092 | /* A floating-point value. */ | |
3093 | OT_FLOAT, | |
3094 | ||
3095 | /* A single character. This can be '(', ')' or ',', but '(' only appears | |
3096 | before OT_REGs. */ | |
3097 | OT_CHAR, | |
3098 | ||
14daeee3 RS |
3099 | /* A doubled character, either "--" or "++". */ |
3100 | OT_DOUBLE_CHAR, | |
3101 | ||
a92713e6 RS |
3102 | /* The end of the operand list. */ |
3103 | OT_END | |
3104 | }; | |
3105 | ||
3106 | /* A parsed operand token. */ | |
3107 | struct mips_operand_token | |
3108 | { | |
3109 | /* The type of token. */ | |
3110 | enum mips_operand_token_type type; | |
3111 | union | |
3112 | { | |
56d438b1 | 3113 | /* The register symbol value for an OT_REG or OT_REG_INDEX. */ |
a92713e6 RS |
3114 | unsigned int regno; |
3115 | ||
14daeee3 RS |
3116 | /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */ |
3117 | unsigned int channels; | |
3118 | ||
56d438b1 CF |
3119 | /* The integer value of an OT_INTEGER_INDEX. */ |
3120 | addressT index; | |
a92713e6 RS |
3121 | |
3122 | /* The two register symbol values involved in an OT_REG_RANGE. */ | |
3123 | struct { | |
3124 | unsigned int regno1; | |
3125 | unsigned int regno2; | |
3126 | } reg_range; | |
3127 | ||
3128 | /* The value of an OT_INTEGER. The value is represented as an | |
3129 | expression and the relocation operators that were applied to | |
3130 | that expression. The reloc entries are BFD_RELOC_UNUSED if no | |
3131 | relocation operators were used. */ | |
3132 | struct { | |
3133 | expressionS value; | |
3134 | bfd_reloc_code_real_type relocs[3]; | |
3135 | } integer; | |
3136 | ||
3137 | /* The binary data for an OT_FLOAT constant, and the number of bytes | |
3138 | in the constant. */ | |
3139 | struct { | |
3140 | unsigned char data[8]; | |
3141 | int length; | |
3142 | } flt; | |
3143 | ||
14daeee3 | 3144 | /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */ |
a92713e6 RS |
3145 | char ch; |
3146 | } u; | |
3147 | }; | |
3148 | ||
3149 | /* An obstack used to construct lists of mips_operand_tokens. */ | |
3150 | static struct obstack mips_operand_tokens; | |
3151 | ||
3152 | /* Give TOKEN type TYPE and add it to mips_operand_tokens. */ | |
3153 | ||
3154 | static void | |
3155 | mips_add_token (struct mips_operand_token *token, | |
3156 | enum mips_operand_token_type type) | |
3157 | { | |
3158 | token->type = type; | |
3159 | obstack_grow (&mips_operand_tokens, token, sizeof (*token)); | |
3160 | } | |
3161 | ||
3162 | /* Check whether S is '(' followed by a register name. Add OT_CHAR | |
3163 | and OT_REG tokens for them if so, and return a pointer to the first | |
3164 | unconsumed character. Return null otherwise. */ | |
3165 | ||
3166 | static char * | |
3167 | mips_parse_base_start (char *s) | |
3168 | { | |
3169 | struct mips_operand_token token; | |
14daeee3 RS |
3170 | unsigned int regno, channels; |
3171 | bfd_boolean decrement_p; | |
df58fc94 | 3172 | |
a92713e6 RS |
3173 | if (*s != '(') |
3174 | return 0; | |
3175 | ||
3176 | ++s; | |
3177 | SKIP_SPACE_TABS (s); | |
14daeee3 RS |
3178 | |
3179 | /* Only match "--" as part of a base expression. In other contexts "--X" | |
3180 | is a double negative. */ | |
3181 | decrement_p = (s[0] == '-' && s[1] == '-'); | |
3182 | if (decrement_p) | |
3183 | { | |
3184 | s += 2; | |
3185 | SKIP_SPACE_TABS (s); | |
3186 | } | |
3187 | ||
3188 | /* Allow a channel specifier because that leads to better error messages | |
3189 | than treating something like "$vf0x++" as an expression. */ | |
3190 | if (!mips_parse_register (&s, ®no, &channels)) | |
a92713e6 RS |
3191 | return 0; |
3192 | ||
3193 | token.u.ch = '('; | |
3194 | mips_add_token (&token, OT_CHAR); | |
3195 | ||
14daeee3 RS |
3196 | if (decrement_p) |
3197 | { | |
3198 | token.u.ch = '-'; | |
3199 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
3200 | } | |
3201 | ||
a92713e6 RS |
3202 | token.u.regno = regno; |
3203 | mips_add_token (&token, OT_REG); | |
3204 | ||
14daeee3 RS |
3205 | if (channels) |
3206 | { | |
3207 | token.u.channels = channels; | |
3208 | mips_add_token (&token, OT_CHANNELS); | |
3209 | } | |
3210 | ||
3211 | /* For consistency, only match "++" as part of base expressions too. */ | |
3212 | SKIP_SPACE_TABS (s); | |
3213 | if (s[0] == '+' && s[1] == '+') | |
3214 | { | |
3215 | s += 2; | |
3216 | token.u.ch = '+'; | |
3217 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
3218 | } | |
3219 | ||
a92713e6 RS |
3220 | return s; |
3221 | } | |
3222 | ||
3223 | /* Parse one or more tokens from S. Return a pointer to the first | |
3224 | unconsumed character on success. Return null if an error was found | |
3225 | and store the error text in insn_error. FLOAT_FORMAT is as for | |
3226 | mips_parse_arguments. */ | |
3227 | ||
3228 | static char * | |
3229 | mips_parse_argument_token (char *s, char float_format) | |
3230 | { | |
6d4af3c2 AM |
3231 | char *end, *save_in; |
3232 | const char *err; | |
14daeee3 | 3233 | unsigned int regno1, regno2, channels; |
a92713e6 RS |
3234 | struct mips_operand_token token; |
3235 | ||
3236 | /* First look for "($reg", since we want to treat that as an | |
3237 | OT_CHAR and OT_REG rather than an expression. */ | |
3238 | end = mips_parse_base_start (s); | |
3239 | if (end) | |
3240 | return end; | |
3241 | ||
3242 | /* Handle other characters that end up as OT_CHARs. */ | |
3243 | if (*s == ')' || *s == ',') | |
3244 | { | |
3245 | token.u.ch = *s; | |
3246 | mips_add_token (&token, OT_CHAR); | |
3247 | ++s; | |
3248 | return s; | |
3249 | } | |
3250 | ||
3251 | /* Handle tokens that start with a register. */ | |
14daeee3 | 3252 | if (mips_parse_register (&s, ®no1, &channels)) |
df58fc94 | 3253 | { |
14daeee3 RS |
3254 | if (channels) |
3255 | { | |
3256 | /* A register and a VU0 channel suffix. */ | |
3257 | token.u.regno = regno1; | |
3258 | mips_add_token (&token, OT_REG); | |
3259 | ||
3260 | token.u.channels = channels; | |
3261 | mips_add_token (&token, OT_CHANNELS); | |
3262 | return s; | |
3263 | } | |
3264 | ||
a92713e6 RS |
3265 | SKIP_SPACE_TABS (s); |
3266 | if (*s == '-') | |
df58fc94 | 3267 | { |
a92713e6 RS |
3268 | /* A register range. */ |
3269 | ++s; | |
3270 | SKIP_SPACE_TABS (s); | |
14daeee3 | 3271 | if (!mips_parse_register (&s, ®no2, NULL)) |
a92713e6 | 3272 | { |
1661c76c | 3273 | set_insn_error (0, _("invalid register range")); |
a92713e6 RS |
3274 | return 0; |
3275 | } | |
df58fc94 | 3276 | |
a92713e6 RS |
3277 | token.u.reg_range.regno1 = regno1; |
3278 | token.u.reg_range.regno2 = regno2; | |
3279 | mips_add_token (&token, OT_REG_RANGE); | |
3280 | return s; | |
3281 | } | |
a92713e6 | 3282 | |
56d438b1 CF |
3283 | /* Add the register itself. */ |
3284 | token.u.regno = regno1; | |
3285 | mips_add_token (&token, OT_REG); | |
3286 | ||
3287 | /* Check for a vector index. */ | |
3288 | if (*s == '[') | |
3289 | { | |
a92713e6 RS |
3290 | ++s; |
3291 | SKIP_SPACE_TABS (s); | |
56d438b1 CF |
3292 | if (mips_parse_register (&s, &token.u.regno, NULL)) |
3293 | mips_add_token (&token, OT_REG_INDEX); | |
3294 | else | |
a92713e6 | 3295 | { |
56d438b1 CF |
3296 | expressionS element; |
3297 | ||
3298 | my_getExpression (&element, s); | |
3299 | if (element.X_op != O_constant) | |
3300 | { | |
3301 | set_insn_error (0, _("vector element must be constant")); | |
3302 | return 0; | |
3303 | } | |
3304 | s = expr_end; | |
3305 | token.u.index = element.X_add_number; | |
3306 | mips_add_token (&token, OT_INTEGER_INDEX); | |
a92713e6 | 3307 | } |
a92713e6 RS |
3308 | SKIP_SPACE_TABS (s); |
3309 | if (*s != ']') | |
3310 | { | |
1661c76c | 3311 | set_insn_error (0, _("missing `]'")); |
a92713e6 RS |
3312 | return 0; |
3313 | } | |
3314 | ++s; | |
df58fc94 | 3315 | } |
a92713e6 | 3316 | return s; |
df58fc94 RS |
3317 | } |
3318 | ||
a92713e6 RS |
3319 | if (float_format) |
3320 | { | |
3321 | /* First try to treat expressions as floats. */ | |
3322 | save_in = input_line_pointer; | |
3323 | input_line_pointer = s; | |
3324 | err = md_atof (float_format, (char *) token.u.flt.data, | |
3325 | &token.u.flt.length); | |
3326 | end = input_line_pointer; | |
3327 | input_line_pointer = save_in; | |
3328 | if (err && *err) | |
3329 | { | |
e3de51ce | 3330 | set_insn_error (0, err); |
a92713e6 RS |
3331 | return 0; |
3332 | } | |
3333 | if (s != end) | |
3334 | { | |
3335 | mips_add_token (&token, OT_FLOAT); | |
3336 | return end; | |
3337 | } | |
3338 | } | |
3339 | ||
3340 | /* Treat everything else as an integer expression. */ | |
3341 | token.u.integer.relocs[0] = BFD_RELOC_UNUSED; | |
3342 | token.u.integer.relocs[1] = BFD_RELOC_UNUSED; | |
3343 | token.u.integer.relocs[2] = BFD_RELOC_UNUSED; | |
3344 | my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s); | |
3345 | s = expr_end; | |
3346 | mips_add_token (&token, OT_INTEGER); | |
3347 | return s; | |
3348 | } | |
3349 | ||
3350 | /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f' | |
3351 | if expressions should be treated as 32-bit floating-point constants, | |
3352 | 'd' if they should be treated as 64-bit floating-point constants, | |
3353 | or 0 if they should be treated as integer expressions (the usual case). | |
3354 | ||
3355 | Return a list of tokens on success, otherwise return 0. The caller | |
3356 | must obstack_free the list after use. */ | |
3357 | ||
3358 | static struct mips_operand_token * | |
3359 | mips_parse_arguments (char *s, char float_format) | |
3360 | { | |
3361 | struct mips_operand_token token; | |
3362 | ||
3363 | SKIP_SPACE_TABS (s); | |
3364 | while (*s) | |
3365 | { | |
3366 | s = mips_parse_argument_token (s, float_format); | |
3367 | if (!s) | |
3368 | { | |
3369 | obstack_free (&mips_operand_tokens, | |
3370 | obstack_finish (&mips_operand_tokens)); | |
3371 | return 0; | |
3372 | } | |
3373 | SKIP_SPACE_TABS (s); | |
3374 | } | |
3375 | mips_add_token (&token, OT_END); | |
3376 | return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens); | |
df58fc94 RS |
3377 | } |
3378 | ||
d301a56b RS |
3379 | /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE |
3380 | and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
037b32b9 AN |
3381 | |
3382 | static bfd_boolean | |
f79e2745 | 3383 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
3384 | { |
3385 | int isa = mips_opts.isa; | |
846ef2d0 | 3386 | int ase = mips_opts.ase; |
037b32b9 | 3387 | int fp_s, fp_d; |
c6278170 | 3388 | unsigned int i; |
037b32b9 | 3389 | |
be0fcbee | 3390 | if (ISA_HAS_64BIT_REGS (isa)) |
c6278170 RS |
3391 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) |
3392 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
3393 | ase |= mips_ases[i].flags64; | |
037b32b9 | 3394 | |
d301a56b | 3395 | if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) |
037b32b9 AN |
3396 | return FALSE; |
3397 | ||
3398 | /* Check whether the instruction or macro requires single-precision or | |
3399 | double-precision floating-point support. Note that this information is | |
3400 | stored differently in the opcode table for insns and macros. */ | |
3401 | if (mo->pinfo == INSN_MACRO) | |
3402 | { | |
3403 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
3404 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
3405 | } | |
3406 | else | |
3407 | { | |
3408 | fp_s = mo->pinfo & FP_S; | |
3409 | fp_d = mo->pinfo & FP_D; | |
3410 | } | |
3411 | ||
3412 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
3413 | return FALSE; | |
3414 | ||
3415 | if (fp_s && mips_opts.soft_float) | |
3416 | return FALSE; | |
3417 | ||
3418 | return TRUE; | |
3419 | } | |
3420 | ||
3421 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
3422 | selected ISA and architecture. */ | |
3423 | ||
3424 | static bfd_boolean | |
3425 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
3426 | { | |
25499ac7 MR |
3427 | int isa = mips_opts.isa; |
3428 | int ase = mips_opts.ase; | |
3429 | unsigned int i; | |
3430 | ||
3431 | if (ISA_HAS_64BIT_REGS (isa)) | |
3432 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
3433 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
3434 | ase |= mips_ases[i].flags64; | |
3435 | ||
3436 | return opcode_is_member (mo, isa, ase, mips_opts.arch); | |
037b32b9 AN |
3437 | } |
3438 | ||
df58fc94 | 3439 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
7fd53920 MR |
3440 | explicitly requested. Always TRUE in the standard MIPS mode. |
3441 | Use is_size_valid_16 for MIPS16 opcodes. */ | |
df58fc94 RS |
3442 | |
3443 | static bfd_boolean | |
3444 | is_size_valid (const struct mips_opcode *mo) | |
3445 | { | |
3446 | if (!mips_opts.micromips) | |
3447 | return TRUE; | |
3448 | ||
833794fc MR |
3449 | if (mips_opts.insn32) |
3450 | { | |
3451 | if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4) | |
3452 | return FALSE; | |
3453 | if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0) | |
3454 | return FALSE; | |
3455 | } | |
df58fc94 RS |
3456 | if (!forced_insn_length) |
3457 | return TRUE; | |
3458 | if (mo->pinfo == INSN_MACRO) | |
3459 | return FALSE; | |
3460 | return forced_insn_length == micromips_insn_length (mo); | |
3461 | } | |
3462 | ||
7fd53920 MR |
3463 | /* Return TRUE if the size of the MIPS16 opcode MO matches one |
3464 | explicitly requested. */ | |
3465 | ||
3466 | static bfd_boolean | |
3467 | is_size_valid_16 (const struct mips_opcode *mo) | |
3468 | { | |
3469 | if (!forced_insn_length) | |
3470 | return TRUE; | |
3471 | if (mo->pinfo == INSN_MACRO) | |
3472 | return FALSE; | |
3473 | if (forced_insn_length == 2 && mips_opcode_32bit_p (mo)) | |
3474 | return FALSE; | |
0674ee5d MR |
3475 | if (forced_insn_length == 4 && (mo->pinfo2 & INSN2_SHORT_ONLY)) |
3476 | return FALSE; | |
7fd53920 MR |
3477 | return TRUE; |
3478 | } | |
3479 | ||
df58fc94 | 3480 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot |
e64af278 MR |
3481 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
3482 | ||
3483 | We don't accept macros in 16-bit delay slots to avoid a case where | |
3484 | a macro expansion fails because it relies on a preceding 32-bit real | |
3485 | instruction to have matched and does not handle the operands correctly. | |
3486 | The only macros that may expand to 16-bit instructions are JAL that | |
3487 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
3488 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
3489 | a NOP. In all these cases the macros precede any corresponding real | |
3490 | instruction definitions in the opcode table, so they will match in the | |
3491 | second pass where the size of the delay slot is ignored and therefore | |
3492 | produce correct code. */ | |
df58fc94 RS |
3493 | |
3494 | static bfd_boolean | |
3495 | is_delay_slot_valid (const struct mips_opcode *mo) | |
3496 | { | |
3497 | if (!mips_opts.micromips) | |
3498 | return TRUE; | |
3499 | ||
3500 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 3501 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
3502 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
3503 | && micromips_insn_length (mo) != 4) | |
3504 | return FALSE; | |
3505 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
3506 | && micromips_insn_length (mo) != 2) | |
3507 | return FALSE; | |
3508 | ||
3509 | return TRUE; | |
3510 | } | |
3511 | ||
fc76e730 RS |
3512 | /* For consistency checking, verify that all bits of OPCODE are specified |
3513 | either by the match/mask part of the instruction definition, or by the | |
3514 | operand list. Also build up a list of operands in OPERANDS. | |
3515 | ||
3516 | INSN_BITS says which bits of the instruction are significant. | |
3517 | If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND | |
3518 | provides the mips_operand description of each operand. DECODE_OPERAND | |
3519 | is null for MIPS16 instructions. */ | |
ab902481 RS |
3520 | |
3521 | static int | |
3522 | validate_mips_insn (const struct mips_opcode *opcode, | |
3523 | unsigned long insn_bits, | |
fc76e730 RS |
3524 | const struct mips_operand *(*decode_operand) (const char *), |
3525 | struct mips_operand_array *operands) | |
ab902481 RS |
3526 | { |
3527 | const char *s; | |
fc76e730 | 3528 | unsigned long used_bits, doubled, undefined, opno, mask; |
ab902481 RS |
3529 | const struct mips_operand *operand; |
3530 | ||
fc76e730 RS |
3531 | mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask); |
3532 | if ((mask & opcode->match) != opcode->match) | |
ab902481 RS |
3533 | { |
3534 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
3535 | opcode->name, opcode->args); | |
3536 | return 0; | |
3537 | } | |
3538 | used_bits = 0; | |
fc76e730 | 3539 | opno = 0; |
14daeee3 RS |
3540 | if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) |
3541 | used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1); | |
ab902481 RS |
3542 | for (s = opcode->args; *s; ++s) |
3543 | switch (*s) | |
3544 | { | |
3545 | case ',': | |
3546 | case '(': | |
3547 | case ')': | |
3548 | break; | |
3549 | ||
14daeee3 RS |
3550 | case '#': |
3551 | s++; | |
3552 | break; | |
3553 | ||
ab902481 | 3554 | default: |
fc76e730 | 3555 | if (!decode_operand) |
7fd53920 | 3556 | operand = decode_mips16_operand (*s, mips_opcode_32bit_p (opcode)); |
fc76e730 RS |
3557 | else |
3558 | operand = decode_operand (s); | |
3559 | if (!operand && opcode->pinfo != INSN_MACRO) | |
ab902481 RS |
3560 | { |
3561 | as_bad (_("internal: unknown operand type: %s %s"), | |
3562 | opcode->name, opcode->args); | |
3563 | return 0; | |
3564 | } | |
fc76e730 RS |
3565 | gas_assert (opno < MAX_OPERANDS); |
3566 | operands->operand[opno] = operand; | |
25499ac7 MR |
3567 | if (!decode_operand && operand |
3568 | && operand->type == OP_INT && operand->lsb == 0 | |
3569 | && mips_opcode_32bit_p (opcode)) | |
3570 | used_bits |= mips16_immed_extend (-1, operand->size); | |
3571 | else if (operand && operand->type != OP_VU0_MATCH_SUFFIX) | |
fc76e730 | 3572 | { |
14daeee3 | 3573 | used_bits = mips_insert_operand (operand, used_bits, -1); |
fc76e730 RS |
3574 | if (operand->type == OP_MDMX_IMM_REG) |
3575 | /* Bit 5 is the format selector (OB vs QH). The opcode table | |
3576 | has separate entries for each format. */ | |
3577 | used_bits &= ~(1 << (operand->lsb + 5)); | |
3578 | if (operand->type == OP_ENTRY_EXIT_LIST) | |
3579 | used_bits &= ~(mask & 0x700); | |
38bf472a MR |
3580 | /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous |
3581 | operand field that cannot be fully described with LSB/SIZE. */ | |
3582 | if (operand->type == OP_SAVE_RESTORE_LIST && operand->lsb == 6) | |
3583 | used_bits &= ~0x6000; | |
fc76e730 | 3584 | } |
ab902481 | 3585 | /* Skip prefix characters. */ |
7361da2c | 3586 | if (decode_operand && (*s == '+' || *s == 'm' || *s == '-')) |
ab902481 | 3587 | ++s; |
fc76e730 | 3588 | opno += 1; |
ab902481 RS |
3589 | break; |
3590 | } | |
fc76e730 | 3591 | doubled = used_bits & mask & insn_bits; |
ab902481 RS |
3592 | if (doubled) |
3593 | { | |
3594 | as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):" | |
3595 | " %s %s"), doubled, opcode->name, opcode->args); | |
3596 | return 0; | |
3597 | } | |
fc76e730 | 3598 | used_bits |= mask; |
ab902481 | 3599 | undefined = ~used_bits & insn_bits; |
fc76e730 | 3600 | if (opcode->pinfo != INSN_MACRO && undefined) |
ab902481 RS |
3601 | { |
3602 | as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"), | |
3603 | undefined, opcode->name, opcode->args); | |
3604 | return 0; | |
3605 | } | |
3606 | used_bits &= ~insn_bits; | |
3607 | if (used_bits) | |
3608 | { | |
3609 | as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"), | |
3610 | used_bits, opcode->name, opcode->args); | |
3611 | return 0; | |
3612 | } | |
3613 | return 1; | |
3614 | } | |
3615 | ||
fc76e730 RS |
3616 | /* The MIPS16 version of validate_mips_insn. */ |
3617 | ||
3618 | static int | |
3619 | validate_mips16_insn (const struct mips_opcode *opcode, | |
3620 | struct mips_operand_array *operands) | |
3621 | { | |
7fd53920 | 3622 | unsigned long insn_bits = mips_opcode_32bit_p (opcode) ? 0xffffffff : 0xffff; |
fc76e730 | 3623 | |
7fd53920 | 3624 | return validate_mips_insn (opcode, insn_bits, 0, operands); |
fc76e730 RS |
3625 | } |
3626 | ||
ab902481 RS |
3627 | /* The microMIPS version of validate_mips_insn. */ |
3628 | ||
3629 | static int | |
fc76e730 RS |
3630 | validate_micromips_insn (const struct mips_opcode *opc, |
3631 | struct mips_operand_array *operands) | |
ab902481 RS |
3632 | { |
3633 | unsigned long insn_bits; | |
3634 | unsigned long major; | |
3635 | unsigned int length; | |
3636 | ||
fc76e730 RS |
3637 | if (opc->pinfo == INSN_MACRO) |
3638 | return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand, | |
3639 | operands); | |
3640 | ||
ab902481 RS |
3641 | length = micromips_insn_length (opc); |
3642 | if (length != 2 && length != 4) | |
3643 | { | |
1661c76c | 3644 | as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): " |
ab902481 RS |
3645 | "%s %s"), length, opc->name, opc->args); |
3646 | return 0; | |
3647 | } | |
3648 | major = opc->match >> (10 + 8 * (length - 2)); | |
3649 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
3650 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
3651 | { | |
1661c76c | 3652 | as_bad (_("internal error: bad microMIPS opcode " |
ab902481 RS |
3653 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); |
3654 | return 0; | |
3655 | } | |
3656 | ||
3657 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
3658 | insn_bits = 1 << 4 * length; | |
3659 | insn_bits <<= 4 * length; | |
3660 | insn_bits -= 1; | |
fc76e730 RS |
3661 | return validate_mips_insn (opc, insn_bits, decode_micromips_operand, |
3662 | operands); | |
ab902481 RS |
3663 | } |
3664 | ||
707bfff6 TS |
3665 | /* This function is called once, at assembler startup time. It should set up |
3666 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 3667 | |
252b5132 | 3668 | void |
17a2f251 | 3669 | md_begin (void) |
252b5132 | 3670 | { |
3994f87e | 3671 | const char *retval = NULL; |
156c2f8b | 3672 | int i = 0; |
252b5132 | 3673 | int broken = 0; |
1f25f5d3 | 3674 | |
0a44bf69 RS |
3675 | if (mips_pic != NO_PIC) |
3676 | { | |
3677 | if (g_switch_seen && g_switch_value != 0) | |
3678 | as_bad (_("-G may not be used in position-independent code")); | |
3679 | g_switch_value = 0; | |
3680 | } | |
00acd688 CM |
3681 | else if (mips_abicalls) |
3682 | { | |
3683 | if (g_switch_seen && g_switch_value != 0) | |
3684 | as_bad (_("-G may not be used with abicalls")); | |
3685 | g_switch_value = 0; | |
3686 | } | |
0a44bf69 | 3687 | |
0b35dfee | 3688 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) |
1661c76c | 3689 | as_warn (_("could not set architecture and machine")); |
252b5132 | 3690 | |
252b5132 RH |
3691 | op_hash = hash_new (); |
3692 | ||
fc76e730 | 3693 | mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES); |
252b5132 RH |
3694 | for (i = 0; i < NUMOPCODES;) |
3695 | { | |
3696 | const char *name = mips_opcodes[i].name; | |
3697 | ||
17a2f251 | 3698 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
3699 | if (retval != NULL) |
3700 | { | |
3701 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
3702 | mips_opcodes[i].name, retval); | |
3703 | /* Probably a memory allocation problem? Give up now. */ | |
1661c76c | 3704 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3705 | } |
3706 | do | |
3707 | { | |
fc76e730 RS |
3708 | if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff, |
3709 | decode_mips_operand, &mips_operands[i])) | |
3710 | broken = 1; | |
6f2117ba | 3711 | |
fc76e730 | 3712 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
252b5132 | 3713 | { |
fc76e730 RS |
3714 | create_insn (&nop_insn, mips_opcodes + i); |
3715 | if (mips_fix_loongson2f_nop) | |
3716 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
3717 | nop_insn.fixed_p = 1; | |
252b5132 | 3718 | } |
6f2117ba PH |
3719 | |
3720 | if (sync_insn.insn_mo == NULL && strcmp (name, "sync") == 0) | |
3721 | create_insn (&sync_insn, mips_opcodes + i); | |
3722 | ||
252b5132 RH |
3723 | ++i; |
3724 | } | |
3725 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3726 | } | |
3727 | ||
3728 | mips16_op_hash = hash_new (); | |
fc76e730 RS |
3729 | mips16_operands = XCNEWVEC (struct mips_operand_array, |
3730 | bfd_mips16_num_opcodes); | |
252b5132 RH |
3731 | |
3732 | i = 0; | |
3733 | while (i < bfd_mips16_num_opcodes) | |
3734 | { | |
3735 | const char *name = mips16_opcodes[i].name; | |
3736 | ||
17a2f251 | 3737 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
3738 | if (retval != NULL) |
3739 | as_fatal (_("internal: can't hash `%s': %s"), | |
3740 | mips16_opcodes[i].name, retval); | |
3741 | do | |
3742 | { | |
fc76e730 RS |
3743 | if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i])) |
3744 | broken = 1; | |
1e915849 RS |
3745 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
3746 | { | |
3747 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
3748 | mips16_nop_insn.fixed_p = 1; | |
3749 | } | |
252b5132 RH |
3750 | ++i; |
3751 | } | |
3752 | while (i < bfd_mips16_num_opcodes | |
3753 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
3754 | } | |
3755 | ||
df58fc94 | 3756 | micromips_op_hash = hash_new (); |
fc76e730 RS |
3757 | micromips_operands = XCNEWVEC (struct mips_operand_array, |
3758 | bfd_micromips_num_opcodes); | |
df58fc94 RS |
3759 | |
3760 | i = 0; | |
3761 | while (i < bfd_micromips_num_opcodes) | |
3762 | { | |
3763 | const char *name = micromips_opcodes[i].name; | |
3764 | ||
3765 | retval = hash_insert (micromips_op_hash, name, | |
3766 | (void *) µmips_opcodes[i]); | |
3767 | if (retval != NULL) | |
3768 | as_fatal (_("internal: can't hash `%s': %s"), | |
3769 | micromips_opcodes[i].name, retval); | |
3770 | do | |
fc76e730 RS |
3771 | { |
3772 | struct mips_cl_insn *micromips_nop_insn; | |
3773 | ||
3774 | if (!validate_micromips_insn (µmips_opcodes[i], | |
3775 | µmips_operands[i])) | |
3776 | broken = 1; | |
3777 | ||
3778 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
3779 | { | |
3780 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
3781 | micromips_nop_insn = µmips_nop16_insn; | |
3782 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
3783 | micromips_nop_insn = µmips_nop32_insn; | |
3784 | else | |
3785 | continue; | |
3786 | ||
3787 | if (micromips_nop_insn->insn_mo == NULL | |
3788 | && strcmp (name, "nop") == 0) | |
3789 | { | |
3790 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
3791 | micromips_nop_insn->fixed_p = 1; | |
3792 | } | |
3793 | } | |
3794 | } | |
df58fc94 RS |
3795 | while (++i < bfd_micromips_num_opcodes |
3796 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
3797 | } | |
3798 | ||
252b5132 | 3799 | if (broken) |
1661c76c | 3800 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3801 | |
3802 | /* We add all the general register names to the symbol table. This | |
3803 | helps us detect invalid uses of them. */ | |
3739860c | 3804 | for (i = 0; reg_names[i].name; i++) |
707bfff6 | 3805 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, |
8fc4ee9b | 3806 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
3807 | &zero_address_frag)); |
3808 | if (HAVE_NEWABI) | |
3739860c | 3809 | for (i = 0; reg_names_n32n64[i].name; i++) |
707bfff6 | 3810 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, |
8fc4ee9b | 3811 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 3812 | &zero_address_frag)); |
707bfff6 | 3813 | else |
3739860c | 3814 | for (i = 0; reg_names_o32[i].name; i++) |
707bfff6 | 3815 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, |
8fc4ee9b | 3816 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 3817 | &zero_address_frag)); |
6047c971 | 3818 | |
14daeee3 RS |
3819 | for (i = 0; i < 32; i++) |
3820 | { | |
92fce9bd | 3821 | char regname[6]; |
14daeee3 RS |
3822 | |
3823 | /* R5900 VU0 floating-point register. */ | |
92fce9bd | 3824 | sprintf (regname, "$vf%d", i); |
14daeee3 RS |
3825 | symbol_table_insert (symbol_new (regname, reg_section, |
3826 | RTYPE_VF | i, &zero_address_frag)); | |
3827 | ||
3828 | /* R5900 VU0 integer register. */ | |
92fce9bd | 3829 | sprintf (regname, "$vi%d", i); |
14daeee3 RS |
3830 | symbol_table_insert (symbol_new (regname, reg_section, |
3831 | RTYPE_VI | i, &zero_address_frag)); | |
3832 | ||
56d438b1 | 3833 | /* MSA register. */ |
92fce9bd | 3834 | sprintf (regname, "$w%d", i); |
56d438b1 CF |
3835 | symbol_table_insert (symbol_new (regname, reg_section, |
3836 | RTYPE_MSA | i, &zero_address_frag)); | |
14daeee3 RS |
3837 | } |
3838 | ||
a92713e6 RS |
3839 | obstack_init (&mips_operand_tokens); |
3840 | ||
7d10b47d | 3841 | mips_no_prev_insn (); |
252b5132 RH |
3842 | |
3843 | mips_gprmask = 0; | |
3844 | mips_cprmask[0] = 0; | |
3845 | mips_cprmask[1] = 0; | |
3846 | mips_cprmask[2] = 0; | |
3847 | mips_cprmask[3] = 0; | |
3848 | ||
3849 | /* set the default alignment for the text section (2**2) */ | |
3850 | record_alignment (text_section, 2); | |
3851 | ||
4d0d148d | 3852 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 3853 | |
f3ded42a RS |
3854 | /* On a native system other than VxWorks, sections must be aligned |
3855 | to 16 byte boundaries. When configured for an embedded ELF | |
3856 | target, we don't bother. */ | |
3857 | if (strncmp (TARGET_OS, "elf", 3) != 0 | |
3858 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 | 3859 | { |
fd361982 AM |
3860 | bfd_set_section_alignment (text_section, 4); |
3861 | bfd_set_section_alignment (data_section, 4); | |
3862 | bfd_set_section_alignment (bss_section, 4); | |
f3ded42a | 3863 | } |
252b5132 | 3864 | |
f3ded42a RS |
3865 | /* Create a .reginfo section for register masks and a .mdebug |
3866 | section for debugging information. */ | |
3867 | { | |
3868 | segT seg; | |
3869 | subsegT subseg; | |
3870 | flagword flags; | |
3871 | segT sec; | |
3872 | ||
3873 | seg = now_seg; | |
3874 | subseg = now_subseg; | |
3875 | ||
3876 | /* The ABI says this section should be loaded so that the | |
3877 | running program can access it. However, we don't load it | |
6f2117ba | 3878 | if we are configured for an embedded target. */ |
f3ded42a RS |
3879 | flags = SEC_READONLY | SEC_DATA; |
3880 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
3881 | flags |= SEC_ALLOC | SEC_LOAD; | |
3882 | ||
3883 | if (mips_abi != N64_ABI) | |
252b5132 | 3884 | { |
f3ded42a | 3885 | sec = subseg_new (".reginfo", (subsegT) 0); |
bdaaa2e1 | 3886 | |
fd361982 AM |
3887 | bfd_set_section_flags (sec, flags); |
3888 | bfd_set_section_alignment (sec, HAVE_NEWABI ? 3 : 2); | |
252b5132 | 3889 | |
f3ded42a RS |
3890 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
3891 | } | |
3892 | else | |
3893 | { | |
3894 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
3895 | .reginfo section. */ | |
3896 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
fd361982 AM |
3897 | bfd_set_section_flags (sec, flags); |
3898 | bfd_set_section_alignment (sec, 3); | |
252b5132 | 3899 | |
f3ded42a RS |
3900 | /* Set up the option header. */ |
3901 | { | |
3902 | Elf_Internal_Options opthdr; | |
3903 | char *f; | |
3904 | ||
3905 | opthdr.kind = ODK_REGINFO; | |
3906 | opthdr.size = (sizeof (Elf_External_Options) | |
3907 | + sizeof (Elf64_External_RegInfo)); | |
3908 | opthdr.section = 0; | |
3909 | opthdr.info = 0; | |
3910 | f = frag_more (sizeof (Elf_External_Options)); | |
3911 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
3912 | (Elf_External_Options *) f); | |
3913 | ||
3914 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
3915 | } | |
3916 | } | |
252b5132 | 3917 | |
351cdf24 | 3918 | sec = subseg_new (".MIPS.abiflags", (subsegT) 0); |
fd361982 | 3919 | bfd_set_section_flags (sec, |
351cdf24 | 3920 | SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD); |
fd361982 | 3921 | bfd_set_section_alignment (sec, 3); |
351cdf24 MF |
3922 | mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0)); |
3923 | ||
f3ded42a RS |
3924 | if (ECOFF_DEBUGGING) |
3925 | { | |
3926 | sec = subseg_new (".mdebug", (subsegT) 0); | |
fd361982 AM |
3927 | bfd_set_section_flags (sec, SEC_HAS_CONTENTS | SEC_READONLY); |
3928 | bfd_set_section_alignment (sec, 2); | |
252b5132 | 3929 | } |
f3ded42a RS |
3930 | else if (mips_flag_pdr) |
3931 | { | |
3932 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
fd361982 AM |
3933 | bfd_set_section_flags (pdr_seg, |
3934 | SEC_READONLY | SEC_RELOC | SEC_DEBUGGING); | |
3935 | bfd_set_section_alignment (pdr_seg, 2); | |
f3ded42a RS |
3936 | } |
3937 | ||
3938 | subseg_set (seg, subseg); | |
3939 | } | |
252b5132 | 3940 | |
71400594 RS |
3941 | if (mips_fix_vr4120) |
3942 | init_vr4120_conflicts (); | |
252b5132 RH |
3943 | } |
3944 | ||
351cdf24 MF |
3945 | static inline void |
3946 | fpabi_incompatible_with (int fpabi, const char *what) | |
3947 | { | |
3948 | as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"), | |
3949 | Tag_GNU_MIPS_ABI_FP, fpabi, what); | |
3950 | } | |
3951 | ||
3952 | static inline void | |
3953 | fpabi_requires (int fpabi, const char *what) | |
3954 | { | |
3955 | as_warn (_(".gnu_attribute %d,%d requires `%s'"), | |
3956 | Tag_GNU_MIPS_ABI_FP, fpabi, what); | |
3957 | } | |
3958 | ||
3959 | /* Check -mabi and register sizes against the specified FP ABI. */ | |
3960 | static void | |
3961 | check_fpabi (int fpabi) | |
3962 | { | |
351cdf24 MF |
3963 | switch (fpabi) |
3964 | { | |
3965 | case Val_GNU_MIPS_ABI_FP_DOUBLE: | |
ea79f94a MF |
3966 | if (file_mips_opts.soft_float) |
3967 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3968 | else if (file_mips_opts.single_float) | |
3969 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3970 | if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32) |
3971 | fpabi_incompatible_with (fpabi, "gp=64 fp=32"); | |
3972 | else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64) | |
3973 | fpabi_incompatible_with (fpabi, "gp=32 fp=64"); | |
351cdf24 MF |
3974 | break; |
3975 | ||
3976 | case Val_GNU_MIPS_ABI_FP_XX: | |
3977 | if (mips_abi != O32_ABI) | |
3978 | fpabi_requires (fpabi, "-mabi=32"); | |
ea79f94a MF |
3979 | else if (file_mips_opts.soft_float) |
3980 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3981 | else if (file_mips_opts.single_float) | |
3982 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3983 | else if (file_mips_opts.fp != 0) |
3984 | fpabi_requires (fpabi, "fp=xx"); | |
351cdf24 MF |
3985 | break; |
3986 | ||
3987 | case Val_GNU_MIPS_ABI_FP_64A: | |
3988 | case Val_GNU_MIPS_ABI_FP_64: | |
3989 | if (mips_abi != O32_ABI) | |
3990 | fpabi_requires (fpabi, "-mabi=32"); | |
ea79f94a MF |
3991 | else if (file_mips_opts.soft_float) |
3992 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3993 | else if (file_mips_opts.single_float) | |
3994 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3995 | else if (file_mips_opts.fp != 64) |
3996 | fpabi_requires (fpabi, "fp=64"); | |
3997 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg) | |
3998 | fpabi_incompatible_with (fpabi, "nooddspreg"); | |
3999 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg) | |
4000 | fpabi_requires (fpabi, "nooddspreg"); | |
351cdf24 MF |
4001 | break; |
4002 | ||
4003 | case Val_GNU_MIPS_ABI_FP_SINGLE: | |
4004 | if (file_mips_opts.soft_float) | |
4005 | fpabi_incompatible_with (fpabi, "softfloat"); | |
4006 | else if (!file_mips_opts.single_float) | |
4007 | fpabi_requires (fpabi, "singlefloat"); | |
4008 | break; | |
4009 | ||
4010 | case Val_GNU_MIPS_ABI_FP_SOFT: | |
4011 | if (!file_mips_opts.soft_float) | |
4012 | fpabi_requires (fpabi, "softfloat"); | |
4013 | break; | |
4014 | ||
4015 | case Val_GNU_MIPS_ABI_FP_OLD_64: | |
4016 | as_warn (_(".gnu_attribute %d,%d is no longer supported"), | |
4017 | Tag_GNU_MIPS_ABI_FP, fpabi); | |
4018 | break; | |
4019 | ||
3350cc01 CM |
4020 | case Val_GNU_MIPS_ABI_FP_NAN2008: |
4021 | /* Silently ignore compatibility value. */ | |
4022 | break; | |
4023 | ||
351cdf24 MF |
4024 | default: |
4025 | as_warn (_(".gnu_attribute %d,%d is not a recognized" | |
4026 | " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi); | |
4027 | break; | |
4028 | } | |
351cdf24 MF |
4029 | } |
4030 | ||
919731af | 4031 | /* Perform consistency checks on the current options. */ |
4032 | ||
4033 | static void | |
4034 | mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks) | |
4035 | { | |
4036 | /* Check the size of integer registers agrees with the ABI and ISA. */ | |
4037 | if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa)) | |
4038 | as_bad (_("`gp=64' used with a 32-bit processor")); | |
4039 | else if (abi_checks | |
4040 | && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
4041 | as_bad (_("`gp=32' used with a 64-bit ABI")); | |
4042 | else if (abi_checks | |
4043 | && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
4044 | as_bad (_("`gp=64' used with a 32-bit ABI")); | |
4045 | ||
4046 | /* Check the size of the float registers agrees with the ABI and ISA. */ | |
4047 | switch (opts->fp) | |
4048 | { | |
351cdf24 MF |
4049 | case 0: |
4050 | if (!CPU_HAS_LDC1_SDC1 (opts->arch)) | |
4051 | as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions")); | |
4052 | else if (opts->single_float == 1) | |
4053 | as_bad (_("`fp=xx' cannot be used with `singlefloat'")); | |
4054 | break; | |
919731af | 4055 | case 64: |
4056 | if (!ISA_HAS_64BIT_FPRS (opts->isa)) | |
4057 | as_bad (_("`fp=64' used with a 32-bit fpu")); | |
4058 | else if (abi_checks | |
4059 | && ABI_NEEDS_32BIT_REGS (mips_abi) | |
4060 | && !ISA_HAS_MXHC1 (opts->isa)) | |
4061 | as_warn (_("`fp=64' used with a 32-bit ABI")); | |
4062 | break; | |
4063 | case 32: | |
4064 | if (abi_checks | |
4065 | && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
4066 | as_warn (_("`fp=32' used with a 64-bit ABI")); | |
5f4678bb | 4067 | if (ISA_IS_R6 (opts->isa) && opts->single_float == 0) |
7361da2c | 4068 | as_bad (_("`fp=32' used with a MIPS R6 cpu")); |
919731af | 4069 | break; |
4070 | default: | |
4071 | as_bad (_("Unknown size of floating point registers")); | |
4072 | break; | |
4073 | } | |
4074 | ||
351cdf24 MF |
4075 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg) |
4076 | as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI")); | |
4077 | ||
919731af | 4078 | if (opts->micromips == 1 && opts->mips16 == 1) |
1357373c | 4079 | as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips"); |
5f4678bb | 4080 | else if (ISA_IS_R6 (opts->isa) |
7361da2c AB |
4081 | && (opts->micromips == 1 |
4082 | || opts->mips16 == 1)) | |
1357373c | 4083 | as_fatal (_("`%s' cannot be used with `%s'"), |
7361da2c | 4084 | opts->micromips ? "micromips" : "mips16", |
5f4678bb | 4085 | mips_cpu_info_from_isa (opts->isa)->name); |
7361da2c AB |
4086 | |
4087 | if (ISA_IS_R6 (opts->isa) && mips_relax_branch) | |
4088 | as_fatal (_("branch relaxation is not supported in `%s'"), | |
4089 | mips_cpu_info_from_isa (opts->isa)->name); | |
919731af | 4090 | } |
4091 | ||
4092 | /* Perform consistency checks on the module level options exactly once. | |
4093 | This is a deferred check that happens: | |
4094 | at the first .set directive | |
4095 | or, at the first pseudo op that generates code (inc .dc.a) | |
4096 | or, at the first instruction | |
4097 | or, at the end. */ | |
4098 | ||
4099 | static void | |
4100 | file_mips_check_options (void) | |
4101 | { | |
919731af | 4102 | if (file_mips_opts_checked) |
4103 | return; | |
4104 | ||
4105 | /* The following code determines the register size. | |
4106 | Similar code was added to GCC 3.3 (see override_options() in | |
4107 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
4108 | as much as possible. */ | |
4109 | ||
4110 | if (file_mips_opts.gp < 0) | |
4111 | { | |
4112 | /* Infer the integer register size from the ABI and processor. | |
4113 | Restrict ourselves to 32-bit registers if that's all the | |
4114 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
4115 | file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
4116 | || !ISA_HAS_64BIT_REGS (file_mips_opts.isa)) | |
4117 | ? 32 : 64; | |
4118 | } | |
4119 | ||
4120 | if (file_mips_opts.fp < 0) | |
4121 | { | |
4122 | /* No user specified float register size. | |
4123 | ??? GAS treats single-float processors as though they had 64-bit | |
4124 | float registers (although it complains when double-precision | |
4125 | instructions are used). As things stand, saying they have 32-bit | |
4126 | registers would lead to spurious "register must be even" messages. | |
4127 | So here we assume float registers are never smaller than the | |
4128 | integer ones. */ | |
4129 | if (file_mips_opts.gp == 64) | |
4130 | /* 64-bit integer registers implies 64-bit float registers. */ | |
4131 | file_mips_opts.fp = 64; | |
4132 | else if ((file_mips_opts.ase & FP64_ASES) | |
4133 | && ISA_HAS_64BIT_FPRS (file_mips_opts.isa)) | |
4134 | /* Handle ASEs that require 64-bit float registers, if possible. */ | |
4135 | file_mips_opts.fp = 64; | |
7361da2c AB |
4136 | else if (ISA_IS_R6 (mips_opts.isa)) |
4137 | /* R6 implies 64-bit float registers. */ | |
4138 | file_mips_opts.fp = 64; | |
919731af | 4139 | else |
4140 | /* 32-bit float registers. */ | |
4141 | file_mips_opts.fp = 32; | |
4142 | } | |
4143 | ||
351cdf24 MF |
4144 | /* Disable operations on odd-numbered floating-point registers by default |
4145 | when using the FPXX ABI. */ | |
4146 | if (file_mips_opts.oddspreg < 0) | |
4147 | { | |
4148 | if (file_mips_opts.fp == 0) | |
4149 | file_mips_opts.oddspreg = 0; | |
4150 | else | |
4151 | file_mips_opts.oddspreg = 1; | |
4152 | } | |
4153 | ||
919731af | 4154 | /* End of GCC-shared inference code. */ |
4155 | ||
4156 | /* This flag is set when we have a 64-bit capable CPU but use only | |
4157 | 32-bit wide registers. Note that EABI does not use it. */ | |
4158 | if (ISA_HAS_64BIT_REGS (file_mips_opts.isa) | |
4159 | && ((mips_abi == NO_ABI && file_mips_opts.gp == 32) | |
4160 | || mips_abi == O32_ABI)) | |
4161 | mips_32bitmode = 1; | |
4162 | ||
4163 | if (file_mips_opts.isa == ISA_MIPS1 && mips_trap) | |
4164 | as_bad (_("trap exception not supported at ISA 1")); | |
4165 | ||
4166 | /* If the selected architecture includes support for ASEs, enable | |
4167 | generation of code for them. */ | |
4168 | if (file_mips_opts.mips16 == -1) | |
4169 | file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0; | |
4170 | if (file_mips_opts.micromips == -1) | |
4171 | file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch)) | |
4172 | ? 1 : 0; | |
4173 | ||
7361da2c AB |
4174 | if (mips_nan2008 == -1) |
4175 | mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1; | |
4176 | else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0) | |
4177 | as_fatal (_("`%s' does not support legacy NaN"), | |
4178 | mips_cpu_info_from_arch (file_mips_opts.arch)->name); | |
4179 | ||
919731af | 4180 | /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from |
4181 | being selected implicitly. */ | |
4182 | if (file_mips_opts.fp != 64) | |
4183 | file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA; | |
4184 | ||
4185 | /* If the user didn't explicitly select or deselect a particular ASE, | |
4186 | use the default setting for the CPU. */ | |
3315614d | 4187 | file_mips_opts.ase |= (file_mips_opts.init_ase & ~file_ase_explicit); |
919731af | 4188 | |
4189 | /* Set up the current options. These may change throughout assembly. */ | |
4190 | mips_opts = file_mips_opts; | |
4191 | ||
4192 | mips_check_isa_supports_ases (); | |
4193 | mips_check_options (&file_mips_opts, TRUE); | |
4194 | file_mips_opts_checked = TRUE; | |
4195 | ||
4196 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) | |
4197 | as_warn (_("could not set architecture and machine")); | |
4198 | } | |
4199 | ||
252b5132 | 4200 | void |
17a2f251 | 4201 | md_assemble (char *str) |
252b5132 RH |
4202 | { |
4203 | struct mips_cl_insn insn; | |
f6688943 TS |
4204 | bfd_reloc_code_real_type unused_reloc[3] |
4205 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 4206 | |
919731af | 4207 | file_mips_check_options (); |
4208 | ||
252b5132 | 4209 | imm_expr.X_op = O_absent; |
252b5132 | 4210 | offset_expr.X_op = O_absent; |
f6688943 TS |
4211 | offset_reloc[0] = BFD_RELOC_UNUSED; |
4212 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
4213 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 4214 | |
e1b47bd5 RS |
4215 | mips_mark_labels (); |
4216 | mips_assembling_insn = TRUE; | |
e3de51ce | 4217 | clear_insn_error (); |
e1b47bd5 | 4218 | |
252b5132 RH |
4219 | if (mips_opts.mips16) |
4220 | mips16_ip (str, &insn); | |
4221 | else | |
4222 | { | |
4223 | mips_ip (str, &insn); | |
beae10d5 KH |
4224 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
4225 | str, insn.insn_opcode)); | |
252b5132 RH |
4226 | } |
4227 | ||
e3de51ce RS |
4228 | if (insn_error.msg) |
4229 | report_insn_error (str); | |
e1b47bd5 | 4230 | else if (insn.insn_mo->pinfo == INSN_MACRO) |
252b5132 | 4231 | { |
584892a6 | 4232 | macro_start (); |
252b5132 RH |
4233 | if (mips_opts.mips16) |
4234 | mips16_macro (&insn); | |
4235 | else | |
833794fc | 4236 | macro (&insn, str); |
584892a6 | 4237 | macro_end (); |
252b5132 RH |
4238 | } |
4239 | else | |
4240 | { | |
77bd4346 | 4241 | if (offset_expr.X_op != O_absent) |
df58fc94 | 4242 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 4243 | else |
df58fc94 | 4244 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 4245 | } |
e1b47bd5 RS |
4246 | |
4247 | mips_assembling_insn = FALSE; | |
252b5132 RH |
4248 | } |
4249 | ||
738e5348 RS |
4250 | /* Convenience functions for abstracting away the differences between |
4251 | MIPS16 and non-MIPS16 relocations. */ | |
4252 | ||
4253 | static inline bfd_boolean | |
4254 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
4255 | { | |
4256 | switch (reloc) | |
4257 | { | |
4258 | case BFD_RELOC_MIPS16_JMP: | |
4259 | case BFD_RELOC_MIPS16_GPREL: | |
4260 | case BFD_RELOC_MIPS16_GOT16: | |
4261 | case BFD_RELOC_MIPS16_CALL16: | |
4262 | case BFD_RELOC_MIPS16_HI16_S: | |
4263 | case BFD_RELOC_MIPS16_HI16: | |
4264 | case BFD_RELOC_MIPS16_LO16: | |
c9775dde | 4265 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
738e5348 RS |
4266 | return TRUE; |
4267 | ||
4268 | default: | |
4269 | return FALSE; | |
4270 | } | |
4271 | } | |
4272 | ||
df58fc94 RS |
4273 | static inline bfd_boolean |
4274 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
4275 | { | |
4276 | switch (reloc) | |
4277 | { | |
4278 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
4279 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
4280 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
4281 | case BFD_RELOC_MICROMIPS_GPREL16: | |
4282 | case BFD_RELOC_MICROMIPS_JMP: | |
4283 | case BFD_RELOC_MICROMIPS_HI16: | |
4284 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4285 | case BFD_RELOC_MICROMIPS_LO16: | |
4286 | case BFD_RELOC_MICROMIPS_LITERAL: | |
4287 | case BFD_RELOC_MICROMIPS_GOT16: | |
4288 | case BFD_RELOC_MICROMIPS_CALL16: | |
4289 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
4290 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
4291 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
4292 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
4293 | case BFD_RELOC_MICROMIPS_SUB: | |
4294 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
4295 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
4296 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
4297 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4298 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4299 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
4300 | case BFD_RELOC_MICROMIPS_JALR: | |
4301 | return TRUE; | |
4302 | ||
4303 | default: | |
4304 | return FALSE; | |
4305 | } | |
4306 | } | |
4307 | ||
2309ddf2 MR |
4308 | static inline bfd_boolean |
4309 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
4310 | { | |
4311 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
4312 | } | |
4313 | ||
0e9c5a5c MR |
4314 | static inline bfd_boolean |
4315 | b_reloc_p (bfd_reloc_code_real_type reloc) | |
4316 | { | |
4317 | return (reloc == BFD_RELOC_MIPS_26_PCREL_S2 | |
4318 | || reloc == BFD_RELOC_MIPS_21_PCREL_S2 | |
4319 | || reloc == BFD_RELOC_16_PCREL_S2 | |
c9775dde | 4320 | || reloc == BFD_RELOC_MIPS16_16_PCREL_S1 |
0e9c5a5c MR |
4321 | || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
4322 | || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
4323 | || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1); | |
4324 | } | |
4325 | ||
738e5348 RS |
4326 | static inline bfd_boolean |
4327 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
4328 | { | |
2309ddf2 | 4329 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 4330 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
4331 | } |
4332 | ||
4333 | static inline bfd_boolean | |
4334 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
4335 | { | |
2309ddf2 | 4336 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 4337 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
4338 | } |
4339 | ||
4340 | static inline bfd_boolean | |
4341 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
4342 | { | |
2309ddf2 | 4343 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
4344 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
4345 | } | |
4346 | ||
df58fc94 RS |
4347 | static inline bfd_boolean |
4348 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
4349 | { | |
2309ddf2 | 4350 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
4351 | } |
4352 | ||
f2ae14a1 RS |
4353 | static inline bfd_boolean |
4354 | gprel16_reloc_p (bfd_reloc_code_real_type reloc) | |
4355 | { | |
4356 | return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL | |
4357 | || reloc == BFD_RELOC_MICROMIPS_GPREL16); | |
4358 | } | |
4359 | ||
2de39019 CM |
4360 | /* Return true if RELOC is a PC-relative relocation that does not have |
4361 | full address range. */ | |
4362 | ||
4363 | static inline bfd_boolean | |
4364 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) | |
4365 | { | |
4366 | switch (reloc) | |
4367 | { | |
4368 | case BFD_RELOC_16_PCREL_S2: | |
c9775dde | 4369 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
2de39019 CM |
4370 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
4371 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
4372 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
7361da2c AB |
4373 | case BFD_RELOC_MIPS_21_PCREL_S2: |
4374 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
4375 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
4376 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
2de39019 CM |
4377 | return TRUE; |
4378 | ||
b47468a6 | 4379 | case BFD_RELOC_32_PCREL: |
7361da2c AB |
4380 | case BFD_RELOC_HI16_S_PCREL: |
4381 | case BFD_RELOC_LO16_PCREL: | |
b47468a6 CM |
4382 | return HAVE_64BIT_ADDRESSES; |
4383 | ||
2de39019 CM |
4384 | default: |
4385 | return FALSE; | |
4386 | } | |
4387 | } | |
b47468a6 | 4388 | |
5919d012 | 4389 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
4390 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
4391 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
4392 | |
4393 | static inline bfd_boolean | |
17a2f251 | 4394 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 4395 | { |
3b91255e | 4396 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 4397 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
4398 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
4399 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
4400 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
4401 | } | |
4402 | ||
4403 | /* Return the type of %lo() reloc needed by RELOC, given that | |
4404 | reloc_needs_lo_p. */ | |
4405 | ||
4406 | static inline bfd_reloc_code_real_type | |
4407 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
4408 | { | |
df58fc94 RS |
4409 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
4410 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
4411 | : BFD_RELOC_LO16)); | |
5919d012 RS |
4412 | } |
4413 | ||
4414 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
4415 | relocation. */ | |
4416 | ||
4417 | static inline bfd_boolean | |
17a2f251 | 4418 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
4419 | { |
4420 | return (fixp->fx_next != NULL | |
738e5348 | 4421 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
4422 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
4423 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
4424 | } | |
4425 | ||
462427c4 RS |
4426 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
4427 | says whether the labels refer to text or data. */ | |
404a8071 RS |
4428 | |
4429 | static void | |
462427c4 | 4430 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
4431 | { |
4432 | struct insn_label_list *l; | |
4433 | valueT val; | |
4434 | ||
462427c4 | 4435 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 4436 | { |
9c2799c2 | 4437 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
4438 | symbol_set_frag (l->label, frag_now); |
4439 | val = (valueT) frag_now_fix (); | |
770c0151 FS |
4440 | /* MIPS16/microMIPS text labels are stored as odd. |
4441 | We just carry the ISA mode bit forward. */ | |
462427c4 | 4442 | if (text_p && HAVE_CODE_COMPRESSION) |
770c0151 | 4443 | val |= (S_GET_VALUE (l->label) & 0x1); |
404a8071 RS |
4444 | S_SET_VALUE (l->label, val); |
4445 | } | |
4446 | } | |
4447 | ||
462427c4 RS |
4448 | /* Move all labels in insn_labels to the current insertion point |
4449 | and treat them as text labels. */ | |
4450 | ||
4451 | static void | |
4452 | mips_move_text_labels (void) | |
4453 | { | |
4454 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
4455 | } | |
4456 | ||
9e009953 MR |
4457 | /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */ |
4458 | ||
5f0fe04b TS |
4459 | static bfd_boolean |
4460 | s_is_linkonce (symbolS *sym, segT from_seg) | |
4461 | { | |
4462 | bfd_boolean linkonce = FALSE; | |
4463 | segT symseg = S_GET_SEGMENT (sym); | |
4464 | ||
4465 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
4466 | { | |
fd361982 | 4467 | if ((bfd_section_flags (symseg) & SEC_LINK_ONCE)) |
5f0fe04b | 4468 | linkonce = TRUE; |
5f0fe04b TS |
4469 | /* The GNU toolchain uses an extension for ELF: a section |
4470 | beginning with the magic string .gnu.linkonce is a | |
4471 | linkonce section. */ | |
4472 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
4473 | sizeof ".gnu.linkonce" - 1) == 0) | |
4474 | linkonce = TRUE; | |
5f0fe04b TS |
4475 | } |
4476 | return linkonce; | |
4477 | } | |
4478 | ||
e1b47bd5 | 4479 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
4480 | linker to handle them specially, such as generating jalx instructions |
4481 | when needed. We also make them odd for the duration of the assembly, | |
4482 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
4483 | in the adjust_symtab routine, while leaving them marked. This is |
4484 | convenient for the debugger and the disassembler. The linker knows | |
4485 | to make them odd again. */ | |
4486 | ||
4487 | static void | |
e1b47bd5 | 4488 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 4489 | { |
df58fc94 | 4490 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 4491 | |
f3ded42a RS |
4492 | if (mips_opts.mips16) |
4493 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
4494 | else | |
4495 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
e1b47bd5 RS |
4496 | if ((S_GET_VALUE (label) & 1) == 0 |
4497 | /* Don't adjust the address if the label is global or weak, or | |
4498 | in a link-once section, since we'll be emitting symbol reloc | |
4499 | references to it which will be patched up by the linker, and | |
4500 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
4501 | && !S_IS_WEAK (label) | |
4502 | && !S_IS_EXTERNAL (label) | |
4503 | && !s_is_linkonce (label, now_seg)) | |
4504 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
4505 | } | |
4506 | ||
4507 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
4508 | ||
4509 | static void | |
4510 | mips_compressed_mark_labels (void) | |
4511 | { | |
4512 | struct insn_label_list *l; | |
4513 | ||
4514 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
4515 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
4516 | } |
4517 | ||
4d7206a2 RS |
4518 | /* End the current frag. Make it a variant frag and record the |
4519 | relaxation info. */ | |
4520 | ||
4521 | static void | |
4522 | relax_close_frag (void) | |
4523 | { | |
584892a6 | 4524 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 4525 | frag_var (rs_machine_dependent, 0, 0, |
ce8ad872 MR |
4526 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1], |
4527 | mips_pic != NO_PIC), | |
4d7206a2 RS |
4528 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
4529 | ||
4530 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
4531 | mips_relax.first_fixup = 0; | |
4532 | } | |
4533 | ||
4534 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
4535 | See the comment above RELAX_ENCODE for more details. */ | |
4536 | ||
4537 | static void | |
4538 | relax_start (symbolS *symbol) | |
4539 | { | |
9c2799c2 | 4540 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
4541 | mips_relax.sequence = 1; |
4542 | mips_relax.symbol = symbol; | |
4543 | } | |
4544 | ||
4545 | /* Start generating the second version of a relaxable sequence. | |
4546 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
4547 | |
4548 | static void | |
4d7206a2 RS |
4549 | relax_switch (void) |
4550 | { | |
9c2799c2 | 4551 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
4552 | mips_relax.sequence = 2; |
4553 | } | |
4554 | ||
4555 | /* End the current relaxable sequence. */ | |
4556 | ||
4557 | static void | |
4558 | relax_end (void) | |
4559 | { | |
9c2799c2 | 4560 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
4561 | relax_close_frag (); |
4562 | mips_relax.sequence = 0; | |
4563 | } | |
4564 | ||
11625dd8 RS |
4565 | /* Return true if IP is a delayed branch or jump. */ |
4566 | ||
4567 | static inline bfd_boolean | |
4568 | delayed_branch_p (const struct mips_cl_insn *ip) | |
4569 | { | |
4570 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4571 | | INSN_COND_BRANCH_DELAY | |
4572 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
4573 | } | |
4574 | ||
4575 | /* Return true if IP is a compact branch or jump. */ | |
4576 | ||
4577 | static inline bfd_boolean | |
4578 | compact_branch_p (const struct mips_cl_insn *ip) | |
4579 | { | |
26545944 RS |
4580 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH |
4581 | | INSN2_COND_BRANCH)) != 0; | |
11625dd8 RS |
4582 | } |
4583 | ||
4584 | /* Return true if IP is an unconditional branch or jump. */ | |
4585 | ||
4586 | static inline bfd_boolean | |
4587 | uncond_branch_p (const struct mips_cl_insn *ip) | |
4588 | { | |
4589 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
26545944 | 4590 | || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0); |
11625dd8 RS |
4591 | } |
4592 | ||
4593 | /* Return true if IP is a branch-likely instruction. */ | |
4594 | ||
4595 | static inline bfd_boolean | |
4596 | branch_likely_p (const struct mips_cl_insn *ip) | |
4597 | { | |
4598 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
4599 | } | |
4600 | ||
14fe068b RS |
4601 | /* Return the type of nop that should be used to fill the delay slot |
4602 | of delayed branch IP. */ | |
4603 | ||
4604 | static struct mips_cl_insn * | |
4605 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
4606 | { | |
4607 | if (mips_opts.micromips | |
4608 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
4609 | return µmips_nop32_insn; | |
4610 | return NOP_INSN; | |
4611 | } | |
4612 | ||
fc76e730 RS |
4613 | /* Return a mask that has bit N set if OPCODE reads the register(s) |
4614 | in operand N. */ | |
df58fc94 RS |
4615 | |
4616 | static unsigned int | |
fc76e730 | 4617 | insn_read_mask (const struct mips_opcode *opcode) |
df58fc94 | 4618 | { |
fc76e730 RS |
4619 | return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT; |
4620 | } | |
df58fc94 | 4621 | |
fc76e730 RS |
4622 | /* Return a mask that has bit N set if OPCODE writes to the register(s) |
4623 | in operand N. */ | |
4624 | ||
4625 | static unsigned int | |
4626 | insn_write_mask (const struct mips_opcode *opcode) | |
4627 | { | |
4628 | return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT; | |
4629 | } | |
4630 | ||
4631 | /* Return a mask of the registers specified by operand OPERAND of INSN. | |
4632 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4633 | is set. */ | |
4634 | ||
4635 | static unsigned int | |
4636 | operand_reg_mask (const struct mips_cl_insn *insn, | |
4637 | const struct mips_operand *operand, | |
4638 | unsigned int type_mask) | |
4639 | { | |
4640 | unsigned int uval, vsel; | |
4641 | ||
4642 | switch (operand->type) | |
df58fc94 | 4643 | { |
fc76e730 RS |
4644 | case OP_INT: |
4645 | case OP_MAPPED_INT: | |
4646 | case OP_MSB: | |
4647 | case OP_PCREL: | |
4648 | case OP_PERF_REG: | |
4649 | case OP_ADDIUSP_INT: | |
4650 | case OP_ENTRY_EXIT_LIST: | |
4651 | case OP_REPEAT_DEST_REG: | |
4652 | case OP_REPEAT_PREV_REG: | |
4653 | case OP_PC: | |
14daeee3 RS |
4654 | case OP_VU0_SUFFIX: |
4655 | case OP_VU0_MATCH_SUFFIX: | |
56d438b1 | 4656 | case OP_IMM_INDEX: |
fc76e730 RS |
4657 | abort (); |
4658 | ||
25499ac7 MR |
4659 | case OP_REG28: |
4660 | return 1 << 28; | |
4661 | ||
fc76e730 | 4662 | case OP_REG: |
0f35dbc4 | 4663 | case OP_OPTIONAL_REG: |
fc76e730 RS |
4664 | { |
4665 | const struct mips_reg_operand *reg_op; | |
4666 | ||
4667 | reg_op = (const struct mips_reg_operand *) operand; | |
4668 | if (!(type_mask & (1 << reg_op->reg_type))) | |
4669 | return 0; | |
4670 | uval = insn_extract_operand (insn, operand); | |
4671 | return 1 << mips_decode_reg_operand (reg_op, uval); | |
4672 | } | |
4673 | ||
4674 | case OP_REG_PAIR: | |
4675 | { | |
4676 | const struct mips_reg_pair_operand *pair_op; | |
4677 | ||
4678 | pair_op = (const struct mips_reg_pair_operand *) operand; | |
4679 | if (!(type_mask & (1 << pair_op->reg_type))) | |
4680 | return 0; | |
4681 | uval = insn_extract_operand (insn, operand); | |
4682 | return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]); | |
4683 | } | |
4684 | ||
4685 | case OP_CLO_CLZ_DEST: | |
4686 | if (!(type_mask & (1 << OP_REG_GP))) | |
4687 | return 0; | |
4688 | uval = insn_extract_operand (insn, operand); | |
4689 | return (1 << (uval & 31)) | (1 << (uval >> 5)); | |
4690 | ||
7361da2c AB |
4691 | case OP_SAME_RS_RT: |
4692 | if (!(type_mask & (1 << OP_REG_GP))) | |
4693 | return 0; | |
4694 | uval = insn_extract_operand (insn, operand); | |
4695 | gas_assert ((uval & 31) == (uval >> 5)); | |
4696 | return 1 << (uval & 31); | |
4697 | ||
4698 | case OP_CHECK_PREV: | |
4699 | case OP_NON_ZERO_REG: | |
4700 | if (!(type_mask & (1 << OP_REG_GP))) | |
4701 | return 0; | |
4702 | uval = insn_extract_operand (insn, operand); | |
4703 | return 1 << (uval & 31); | |
4704 | ||
fc76e730 RS |
4705 | case OP_LWM_SWM_LIST: |
4706 | abort (); | |
4707 | ||
4708 | case OP_SAVE_RESTORE_LIST: | |
4709 | abort (); | |
4710 | ||
4711 | case OP_MDMX_IMM_REG: | |
4712 | if (!(type_mask & (1 << OP_REG_VEC))) | |
4713 | return 0; | |
4714 | uval = insn_extract_operand (insn, operand); | |
4715 | vsel = uval >> 5; | |
4716 | if ((vsel & 0x18) == 0x18) | |
4717 | return 0; | |
4718 | return 1 << (uval & 31); | |
56d438b1 CF |
4719 | |
4720 | case OP_REG_INDEX: | |
4721 | if (!(type_mask & (1 << OP_REG_GP))) | |
4722 | return 0; | |
4723 | return 1 << insn_extract_operand (insn, operand); | |
df58fc94 | 4724 | } |
fc76e730 RS |
4725 | abort (); |
4726 | } | |
4727 | ||
4728 | /* Return a mask of the registers specified by operands OPNO_MASK of INSN, | |
4729 | where bit N of OPNO_MASK is set if operand N should be included. | |
4730 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4731 | is set. */ | |
4732 | ||
4733 | static unsigned int | |
4734 | insn_reg_mask (const struct mips_cl_insn *insn, | |
4735 | unsigned int type_mask, unsigned int opno_mask) | |
4736 | { | |
4737 | unsigned int opno, reg_mask; | |
4738 | ||
4739 | opno = 0; | |
4740 | reg_mask = 0; | |
4741 | while (opno_mask != 0) | |
4742 | { | |
4743 | if (opno_mask & 1) | |
4744 | reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask); | |
4745 | opno_mask >>= 1; | |
4746 | opno += 1; | |
4747 | } | |
4748 | return reg_mask; | |
df58fc94 RS |
4749 | } |
4750 | ||
4c260379 RS |
4751 | /* Return the mask of core registers that IP reads. */ |
4752 | ||
4753 | static unsigned int | |
4754 | gpr_read_mask (const struct mips_cl_insn *ip) | |
4755 | { | |
4756 | unsigned long pinfo, pinfo2; | |
4757 | unsigned int mask; | |
4758 | ||
fc76e730 | 4759 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo)); |
4c260379 RS |
4760 | pinfo = ip->insn_mo->pinfo; |
4761 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 | 4762 | if (pinfo & INSN_UDI) |
4c260379 | 4763 | { |
fc76e730 RS |
4764 | /* UDI instructions have traditionally been assumed to read RS |
4765 | and RT. */ | |
4766 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); | |
4767 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
4c260379 | 4768 | } |
fc76e730 RS |
4769 | if (pinfo & INSN_READ_GPR_24) |
4770 | mask |= 1 << 24; | |
4771 | if (pinfo2 & INSN2_READ_GPR_16) | |
4772 | mask |= 1 << 16; | |
4773 | if (pinfo2 & INSN2_READ_SP) | |
4774 | mask |= 1 << SP; | |
26545944 | 4775 | if (pinfo2 & INSN2_READ_GPR_31) |
a6a1f5e0 | 4776 | mask |= 1u << 31; |
fe35f09f RS |
4777 | /* Don't include register 0. */ |
4778 | return mask & ~1; | |
4c260379 RS |
4779 | } |
4780 | ||
4781 | /* Return the mask of core registers that IP writes. */ | |
4782 | ||
4783 | static unsigned int | |
4784 | gpr_write_mask (const struct mips_cl_insn *ip) | |
4785 | { | |
4786 | unsigned long pinfo, pinfo2; | |
4787 | unsigned int mask; | |
4788 | ||
fc76e730 | 4789 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo)); |
4c260379 RS |
4790 | pinfo = ip->insn_mo->pinfo; |
4791 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 RS |
4792 | if (pinfo & INSN_WRITE_GPR_24) |
4793 | mask |= 1 << 24; | |
4794 | if (pinfo & INSN_WRITE_GPR_31) | |
a6a1f5e0 | 4795 | mask |= 1u << 31; |
fc76e730 RS |
4796 | if (pinfo & INSN_UDI) |
4797 | /* UDI instructions have traditionally been assumed to write to RD. */ | |
4798 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
4799 | if (pinfo2 & INSN2_WRITE_SP) | |
4800 | mask |= 1 << SP; | |
fe35f09f RS |
4801 | /* Don't include register 0. */ |
4802 | return mask & ~1; | |
4c260379 RS |
4803 | } |
4804 | ||
4805 | /* Return the mask of floating-point registers that IP reads. */ | |
4806 | ||
4807 | static unsigned int | |
4808 | fpr_read_mask (const struct mips_cl_insn *ip) | |
4809 | { | |
fc76e730 | 4810 | unsigned long pinfo; |
4c260379 RS |
4811 | unsigned int mask; |
4812 | ||
9d5de888 CF |
4813 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4814 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4815 | insn_read_mask (ip->insn_mo)); |
4c260379 | 4816 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4817 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4818 | (This is overly pessimistic for things like cvt.d.s.) */ | |
bad1aba3 | 4819 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4820 | mask |= mask << 1; |
4821 | return mask; | |
4822 | } | |
4823 | ||
4824 | /* Return the mask of floating-point registers that IP writes. */ | |
4825 | ||
4826 | static unsigned int | |
4827 | fpr_write_mask (const struct mips_cl_insn *ip) | |
4828 | { | |
fc76e730 | 4829 | unsigned long pinfo; |
4c260379 RS |
4830 | unsigned int mask; |
4831 | ||
9d5de888 CF |
4832 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4833 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4834 | insn_write_mask (ip->insn_mo)); |
4c260379 | 4835 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4836 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4837 | (This is overly pessimistic for things like cvt.s.d.) */ | |
bad1aba3 | 4838 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4839 | mask |= mask << 1; |
4840 | return mask; | |
4841 | } | |
4842 | ||
a1d78564 RS |
4843 | /* Operand OPNUM of INSN is an odd-numbered floating-point register. |
4844 | Check whether that is allowed. */ | |
4845 | ||
4846 | static bfd_boolean | |
4847 | mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum) | |
4848 | { | |
4849 | const char *s = insn->name; | |
351cdf24 MF |
4850 | bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch) |
4851 | || FPR_SIZE == 64) | |
4852 | && mips_opts.oddspreg; | |
a1d78564 RS |
4853 | |
4854 | if (insn->pinfo == INSN_MACRO) | |
4855 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
4856 | return TRUE; | |
4857 | ||
351cdf24 MF |
4858 | /* Single-precision coprocessor loads and moves are OK for 32-bit registers, |
4859 | otherwise it depends on oddspreg. */ | |
4860 | if ((insn->pinfo & FP_S) | |
4861 | && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY | |
43885403 | 4862 | | INSN_LOAD_COPROC | INSN_COPROC_MOVE))) |
351cdf24 | 4863 | return FPR_SIZE == 32 || oddspreg; |
a1d78564 | 4864 | |
351cdf24 MF |
4865 | /* Allow odd registers for single-precision ops and double-precision if the |
4866 | floating-point registers are 64-bit wide. */ | |
4867 | switch (insn->pinfo & (FP_S | FP_D)) | |
4868 | { | |
4869 | case FP_S: | |
4870 | case 0: | |
4871 | return oddspreg; | |
4872 | case FP_D: | |
4873 | return FPR_SIZE == 64; | |
4874 | default: | |
4875 | break; | |
a1d78564 RS |
4876 | } |
4877 | ||
351cdf24 MF |
4878 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ |
4879 | s = strchr (insn->name, '.'); | |
4880 | if (s != NULL && opnum == 2) | |
4881 | s = strchr (s + 1, '.'); | |
4882 | if (s != NULL && (s[1] == 'w' || s[1] == 's')) | |
4883 | return oddspreg; | |
a1d78564 | 4884 | |
351cdf24 | 4885 | return FPR_SIZE == 64; |
a1d78564 RS |
4886 | } |
4887 | ||
a1d78564 RS |
4888 | /* Information about an instruction argument that we're trying to match. */ |
4889 | struct mips_arg_info | |
4890 | { | |
4891 | /* The instruction so far. */ | |
4892 | struct mips_cl_insn *insn; | |
4893 | ||
a92713e6 RS |
4894 | /* The first unconsumed operand token. */ |
4895 | struct mips_operand_token *token; | |
4896 | ||
a1d78564 RS |
4897 | /* The 1-based operand number, in terms of insn->insn_mo->args. */ |
4898 | int opnum; | |
4899 | ||
4900 | /* The 1-based argument number, for error reporting. This does not | |
4901 | count elided optional registers, etc.. */ | |
4902 | int argnum; | |
4903 | ||
4904 | /* The last OP_REG operand seen, or ILLEGAL_REG if none. */ | |
4905 | unsigned int last_regno; | |
4906 | ||
4907 | /* If the first operand was an OP_REG, this is the register that it | |
4908 | specified, otherwise it is ILLEGAL_REG. */ | |
4909 | unsigned int dest_regno; | |
4910 | ||
4911 | /* The value of the last OP_INT operand. Only used for OP_MSB, | |
4912 | where it gives the lsb position. */ | |
4913 | unsigned int last_op_int; | |
4914 | ||
60f20e8b | 4915 | /* If true, match routines should assume that no later instruction |
2b0f3761 | 4916 | alternative matches and should therefore be as accommodating as |
60f20e8b RS |
4917 | possible. Match routines should not report errors if something |
4918 | is only invalid for !LAX_MATCH. */ | |
4919 | bfd_boolean lax_match; | |
a1d78564 | 4920 | |
a1d78564 RS |
4921 | /* True if a reference to the current AT register was seen. */ |
4922 | bfd_boolean seen_at; | |
4923 | }; | |
4924 | ||
1a00e612 RS |
4925 | /* Record that the argument is out of range. */ |
4926 | ||
4927 | static void | |
4928 | match_out_of_range (struct mips_arg_info *arg) | |
4929 | { | |
4930 | set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum); | |
4931 | } | |
4932 | ||
4933 | /* Record that the argument isn't constant but needs to be. */ | |
4934 | ||
4935 | static void | |
4936 | match_not_constant (struct mips_arg_info *arg) | |
4937 | { | |
4938 | set_insn_error_i (arg->argnum, _("operand %d must be constant"), | |
4939 | arg->argnum); | |
4940 | } | |
4941 | ||
a92713e6 RS |
4942 | /* Try to match an OT_CHAR token for character CH. Consume the token |
4943 | and return true on success, otherwise return false. */ | |
a1d78564 | 4944 | |
a92713e6 RS |
4945 | static bfd_boolean |
4946 | match_char (struct mips_arg_info *arg, char ch) | |
a1d78564 | 4947 | { |
a92713e6 RS |
4948 | if (arg->token->type == OT_CHAR && arg->token->u.ch == ch) |
4949 | { | |
4950 | ++arg->token; | |
4951 | if (ch == ',') | |
4952 | arg->argnum += 1; | |
4953 | return TRUE; | |
4954 | } | |
4955 | return FALSE; | |
4956 | } | |
a1d78564 | 4957 | |
a92713e6 RS |
4958 | /* Try to get an expression from the next tokens in ARG. Consume the |
4959 | tokens and return true on success, storing the expression value in | |
4960 | VALUE and relocation types in R. */ | |
4961 | ||
4962 | static bfd_boolean | |
4963 | match_expression (struct mips_arg_info *arg, expressionS *value, | |
4964 | bfd_reloc_code_real_type *r) | |
4965 | { | |
d436c1c2 RS |
4966 | /* If the next token is a '(' that was parsed as being part of a base |
4967 | expression, assume we have an elided offset. The later match will fail | |
4968 | if this turns out to be wrong. */ | |
4969 | if (arg->token->type == OT_CHAR && arg->token->u.ch == '(') | |
a1d78564 | 4970 | { |
d436c1c2 RS |
4971 | value->X_op = O_constant; |
4972 | value->X_add_number = 0; | |
4973 | r[0] = r[1] = r[2] = BFD_RELOC_UNUSED; | |
a92713e6 RS |
4974 | return TRUE; |
4975 | } | |
4976 | ||
d436c1c2 RS |
4977 | /* Reject register-based expressions such as "0+$2" and "(($2))". |
4978 | For plain registers the default error seems more appropriate. */ | |
4979 | if (arg->token->type == OT_INTEGER | |
4980 | && arg->token->u.integer.value.X_op == O_register) | |
a92713e6 | 4981 | { |
d436c1c2 RS |
4982 | set_insn_error (arg->argnum, _("register value used as expression")); |
4983 | return FALSE; | |
a1d78564 | 4984 | } |
d436c1c2 RS |
4985 | |
4986 | if (arg->token->type == OT_INTEGER) | |
a92713e6 | 4987 | { |
d436c1c2 RS |
4988 | *value = arg->token->u.integer.value; |
4989 | memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r)); | |
4990 | ++arg->token; | |
4991 | return TRUE; | |
a92713e6 | 4992 | } |
a92713e6 | 4993 | |
d436c1c2 RS |
4994 | set_insn_error_i |
4995 | (arg->argnum, _("operand %d must be an immediate expression"), | |
4996 | arg->argnum); | |
4997 | return FALSE; | |
a92713e6 RS |
4998 | } |
4999 | ||
5000 | /* Try to get a constant expression from the next tokens in ARG. Consume | |
de194d85 | 5001 | the tokens and return true on success, storing the constant value |
a54d5f8b | 5002 | in *VALUE. */ |
a92713e6 RS |
5003 | |
5004 | static bfd_boolean | |
1a00e612 | 5005 | match_const_int (struct mips_arg_info *arg, offsetT *value) |
a92713e6 RS |
5006 | { |
5007 | expressionS ex; | |
5008 | bfd_reloc_code_real_type r[3]; | |
a1d78564 | 5009 | |
a92713e6 RS |
5010 | if (!match_expression (arg, &ex, r)) |
5011 | return FALSE; | |
5012 | ||
5013 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant) | |
a1d78564 RS |
5014 | *value = ex.X_add_number; |
5015 | else | |
5016 | { | |
c96425c5 MR |
5017 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_big) |
5018 | match_out_of_range (arg); | |
5019 | else | |
5020 | match_not_constant (arg); | |
1a00e612 | 5021 | return FALSE; |
a1d78564 | 5022 | } |
a92713e6 | 5023 | return TRUE; |
a1d78564 RS |
5024 | } |
5025 | ||
5026 | /* Return the RTYPE_* flags for a register operand of type TYPE that | |
5027 | appears in instruction OPCODE. */ | |
5028 | ||
5029 | static unsigned int | |
5030 | convert_reg_type (const struct mips_opcode *opcode, | |
5031 | enum mips_reg_operand_type type) | |
5032 | { | |
5033 | switch (type) | |
5034 | { | |
5035 | case OP_REG_GP: | |
5036 | return RTYPE_NUM | RTYPE_GP; | |
5037 | ||
5038 | case OP_REG_FP: | |
5039 | /* Allow vector register names for MDMX if the instruction is a 64-bit | |
5040 | FPR load, store or move (including moves to and from GPRs). */ | |
5041 | if ((mips_opts.ase & ASE_MDMX) | |
5042 | && (opcode->pinfo & FP_D) | |
43885403 | 5043 | && (opcode->pinfo & (INSN_COPROC_MOVE |
a1d78564 | 5044 | | INSN_COPROC_MEMORY_DELAY |
43885403 | 5045 | | INSN_LOAD_COPROC |
67dc82bc | 5046 | | INSN_LOAD_MEMORY |
a1d78564 RS |
5047 | | INSN_STORE_MEMORY))) |
5048 | return RTYPE_FPU | RTYPE_VEC; | |
5049 | return RTYPE_FPU; | |
5050 | ||
5051 | case OP_REG_CCC: | |
5052 | if (opcode->pinfo & (FP_D | FP_S)) | |
5053 | return RTYPE_CCC | RTYPE_FCC; | |
5054 | return RTYPE_CCC; | |
5055 | ||
5056 | case OP_REG_VEC: | |
5057 | if (opcode->membership & INSN_5400) | |
5058 | return RTYPE_FPU; | |
5059 | return RTYPE_FPU | RTYPE_VEC; | |
5060 | ||
5061 | case OP_REG_ACC: | |
5062 | return RTYPE_ACC; | |
5063 | ||
5064 | case OP_REG_COPRO: | |
5065 | if (opcode->name[strlen (opcode->name) - 1] == '0') | |
5066 | return RTYPE_NUM | RTYPE_CP0; | |
5067 | return RTYPE_NUM; | |
5068 | ||
5069 | case OP_REG_HW: | |
5070 | return RTYPE_NUM; | |
14daeee3 RS |
5071 | |
5072 | case OP_REG_VI: | |
5073 | return RTYPE_NUM | RTYPE_VI; | |
5074 | ||
5075 | case OP_REG_VF: | |
5076 | return RTYPE_NUM | RTYPE_VF; | |
5077 | ||
5078 | case OP_REG_R5900_I: | |
5079 | return RTYPE_R5900_I; | |
5080 | ||
5081 | case OP_REG_R5900_Q: | |
5082 | return RTYPE_R5900_Q; | |
5083 | ||
5084 | case OP_REG_R5900_R: | |
5085 | return RTYPE_R5900_R; | |
5086 | ||
5087 | case OP_REG_R5900_ACC: | |
5088 | return RTYPE_R5900_ACC; | |
56d438b1 CF |
5089 | |
5090 | case OP_REG_MSA: | |
5091 | return RTYPE_MSA; | |
5092 | ||
5093 | case OP_REG_MSA_CTRL: | |
5094 | return RTYPE_NUM; | |
a1d78564 RS |
5095 | } |
5096 | abort (); | |
5097 | } | |
5098 | ||
5099 | /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */ | |
5100 | ||
5101 | static void | |
5102 | check_regno (struct mips_arg_info *arg, | |
5103 | enum mips_reg_operand_type type, unsigned int regno) | |
5104 | { | |
5105 | if (AT && type == OP_REG_GP && regno == AT) | |
5106 | arg->seen_at = TRUE; | |
5107 | ||
5108 | if (type == OP_REG_FP | |
5109 | && (regno & 1) != 0 | |
a1d78564 | 5110 | && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum)) |
351cdf24 MF |
5111 | { |
5112 | /* This was a warning prior to introducing O32 FPXX and FP64 support | |
5113 | so maintain a warning for FP32 but raise an error for the new | |
5114 | cases. */ | |
5115 | if (FPR_SIZE == 32) | |
5116 | as_warn (_("float register should be even, was %d"), regno); | |
5117 | else | |
5118 | as_bad (_("float register should be even, was %d"), regno); | |
5119 | } | |
a1d78564 RS |
5120 | |
5121 | if (type == OP_REG_CCC) | |
5122 | { | |
5123 | const char *name; | |
5124 | size_t length; | |
5125 | ||
5126 | name = arg->insn->insn_mo->name; | |
5127 | length = strlen (name); | |
5128 | if ((regno & 1) != 0 | |
5129 | && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0) | |
5130 | || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0))) | |
1661c76c | 5131 | as_warn (_("condition code register should be even for %s, was %d"), |
a1d78564 RS |
5132 | name, regno); |
5133 | ||
5134 | if ((regno & 3) != 0 | |
5135 | && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0)) | |
1661c76c | 5136 | as_warn (_("condition code register should be 0 or 4 for %s, was %d"), |
a1d78564 RS |
5137 | name, regno); |
5138 | } | |
5139 | } | |
5140 | ||
a92713e6 RS |
5141 | /* ARG is a register with symbol value SYMVAL. Try to interpret it as |
5142 | a register of type TYPE. Return true on success, storing the register | |
5143 | number in *REGNO and warning about any dubious uses. */ | |
5144 | ||
5145 | static bfd_boolean | |
5146 | match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5147 | unsigned int symval, unsigned int *regno) | |
5148 | { | |
5149 | if (type == OP_REG_VEC) | |
5150 | symval = mips_prefer_vec_regno (symval); | |
5151 | if (!(symval & convert_reg_type (arg->insn->insn_mo, type))) | |
5152 | return FALSE; | |
5153 | ||
5154 | *regno = symval & RNUM_MASK; | |
5155 | check_regno (arg, type, *regno); | |
5156 | return TRUE; | |
5157 | } | |
5158 | ||
5159 | /* Try to interpret the next token in ARG as a register of type TYPE. | |
5160 | Consume the token and return true on success, storing the register | |
5161 | number in *REGNO. Return false on failure. */ | |
5162 | ||
5163 | static bfd_boolean | |
5164 | match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5165 | unsigned int *regno) | |
5166 | { | |
5167 | if (arg->token->type == OT_REG | |
5168 | && match_regno (arg, type, arg->token->u.regno, regno)) | |
5169 | { | |
5170 | ++arg->token; | |
5171 | return TRUE; | |
5172 | } | |
5173 | return FALSE; | |
5174 | } | |
5175 | ||
5176 | /* Try to interpret the next token in ARG as a range of registers of type TYPE. | |
5177 | Consume the token and return true on success, storing the register numbers | |
5178 | in *REGNO1 and *REGNO2. Return false on failure. */ | |
5179 | ||
5180 | static bfd_boolean | |
5181 | match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5182 | unsigned int *regno1, unsigned int *regno2) | |
5183 | { | |
5184 | if (match_reg (arg, type, regno1)) | |
5185 | { | |
5186 | *regno2 = *regno1; | |
5187 | return TRUE; | |
5188 | } | |
5189 | if (arg->token->type == OT_REG_RANGE | |
5190 | && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1) | |
5191 | && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2) | |
5192 | && *regno1 <= *regno2) | |
5193 | { | |
5194 | ++arg->token; | |
5195 | return TRUE; | |
5196 | } | |
5197 | return FALSE; | |
5198 | } | |
5199 | ||
a1d78564 RS |
5200 | /* OP_INT matcher. */ |
5201 | ||
a92713e6 | 5202 | static bfd_boolean |
a1d78564 | 5203 | match_int_operand (struct mips_arg_info *arg, |
a92713e6 | 5204 | const struct mips_operand *operand_base) |
a1d78564 RS |
5205 | { |
5206 | const struct mips_int_operand *operand; | |
3ccad066 | 5207 | unsigned int uval; |
a1d78564 RS |
5208 | int min_val, max_val, factor; |
5209 | offsetT sval; | |
a1d78564 RS |
5210 | |
5211 | operand = (const struct mips_int_operand *) operand_base; | |
5212 | factor = 1 << operand->shift; | |
3ccad066 RS |
5213 | min_val = mips_int_operand_min (operand); |
5214 | max_val = mips_int_operand_max (operand); | |
a1d78564 | 5215 | |
d436c1c2 RS |
5216 | if (operand_base->lsb == 0 |
5217 | && operand_base->size == 16 | |
5218 | && operand->shift == 0 | |
5219 | && operand->bias == 0 | |
5220 | && (operand->max_val == 32767 || operand->max_val == 65535)) | |
a1d78564 RS |
5221 | { |
5222 | /* The operand can be relocated. */ | |
a92713e6 RS |
5223 | if (!match_expression (arg, &offset_expr, offset_reloc)) |
5224 | return FALSE; | |
5225 | ||
c96425c5 MR |
5226 | if (offset_expr.X_op == O_big) |
5227 | { | |
5228 | match_out_of_range (arg); | |
5229 | return FALSE; | |
5230 | } | |
5231 | ||
a92713e6 | 5232 | if (offset_reloc[0] != BFD_RELOC_UNUSED) |
33eaf5de | 5233 | /* Relocation operators were used. Accept the argument and |
a1d78564 RS |
5234 | leave the relocation value in offset_expr and offset_relocs |
5235 | for the caller to process. */ | |
a92713e6 RS |
5236 | return TRUE; |
5237 | ||
5238 | if (offset_expr.X_op != O_constant) | |
a1d78564 | 5239 | { |
60f20e8b RS |
5240 | /* Accept non-constant operands if no later alternative matches, |
5241 | leaving it for the caller to process. */ | |
5242 | if (!arg->lax_match) | |
602b88e3 MR |
5243 | { |
5244 | match_not_constant (arg); | |
5245 | return FALSE; | |
5246 | } | |
a92713e6 RS |
5247 | offset_reloc[0] = BFD_RELOC_LO16; |
5248 | return TRUE; | |
a1d78564 | 5249 | } |
a92713e6 | 5250 | |
a1d78564 RS |
5251 | /* Clear the global state; we're going to install the operand |
5252 | ourselves. */ | |
a92713e6 | 5253 | sval = offset_expr.X_add_number; |
a1d78564 | 5254 | offset_expr.X_op = O_absent; |
60f20e8b RS |
5255 | |
5256 | /* For compatibility with older assemblers, we accept | |
5257 | 0x8000-0xffff as signed 16-bit numbers when only | |
5258 | signed numbers are allowed. */ | |
5259 | if (sval > max_val) | |
5260 | { | |
5261 | max_val = ((1 << operand_base->size) - 1) << operand->shift; | |
5262 | if (!arg->lax_match && sval <= max_val) | |
20c59b84 MR |
5263 | { |
5264 | match_out_of_range (arg); | |
5265 | return FALSE; | |
5266 | } | |
60f20e8b | 5267 | } |
a1d78564 RS |
5268 | } |
5269 | else | |
5270 | { | |
1a00e612 | 5271 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5272 | return FALSE; |
a1d78564 RS |
5273 | } |
5274 | ||
5275 | arg->last_op_int = sval; | |
5276 | ||
1a00e612 | 5277 | if (sval < min_val || sval > max_val || sval % factor) |
a1d78564 | 5278 | { |
1a00e612 RS |
5279 | match_out_of_range (arg); |
5280 | return FALSE; | |
a1d78564 RS |
5281 | } |
5282 | ||
5283 | uval = (unsigned int) sval >> operand->shift; | |
5284 | uval -= operand->bias; | |
5285 | ||
5286 | /* Handle -mfix-cn63xxp1. */ | |
5287 | if (arg->opnum == 1 | |
5288 | && mips_fix_cn63xxp1 | |
5289 | && !mips_opts.micromips | |
5290 | && strcmp ("pref", arg->insn->insn_mo->name) == 0) | |
5291 | switch (uval) | |
5292 | { | |
5293 | case 5: | |
5294 | case 25: | |
5295 | case 26: | |
5296 | case 27: | |
5297 | case 28: | |
5298 | case 29: | |
5299 | case 30: | |
5300 | case 31: | |
5301 | /* These are ok. */ | |
5302 | break; | |
5303 | ||
5304 | default: | |
5305 | /* The rest must be changed to 28. */ | |
5306 | uval = 28; | |
5307 | break; | |
5308 | } | |
5309 | ||
5310 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5311 | return TRUE; |
a1d78564 RS |
5312 | } |
5313 | ||
5314 | /* OP_MAPPED_INT matcher. */ | |
5315 | ||
a92713e6 | 5316 | static bfd_boolean |
a1d78564 | 5317 | match_mapped_int_operand (struct mips_arg_info *arg, |
a92713e6 | 5318 | const struct mips_operand *operand_base) |
a1d78564 RS |
5319 | { |
5320 | const struct mips_mapped_int_operand *operand; | |
5321 | unsigned int uval, num_vals; | |
5322 | offsetT sval; | |
5323 | ||
5324 | operand = (const struct mips_mapped_int_operand *) operand_base; | |
1a00e612 | 5325 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5326 | return FALSE; |
a1d78564 RS |
5327 | |
5328 | num_vals = 1 << operand_base->size; | |
5329 | for (uval = 0; uval < num_vals; uval++) | |
5330 | if (operand->int_map[uval] == sval) | |
5331 | break; | |
5332 | if (uval == num_vals) | |
1a00e612 RS |
5333 | { |
5334 | match_out_of_range (arg); | |
5335 | return FALSE; | |
5336 | } | |
a1d78564 RS |
5337 | |
5338 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5339 | return TRUE; |
a1d78564 RS |
5340 | } |
5341 | ||
5342 | /* OP_MSB matcher. */ | |
5343 | ||
a92713e6 | 5344 | static bfd_boolean |
a1d78564 | 5345 | match_msb_operand (struct mips_arg_info *arg, |
a92713e6 | 5346 | const struct mips_operand *operand_base) |
a1d78564 RS |
5347 | { |
5348 | const struct mips_msb_operand *operand; | |
5349 | int min_val, max_val, max_high; | |
5350 | offsetT size, sval, high; | |
5351 | ||
5352 | operand = (const struct mips_msb_operand *) operand_base; | |
5353 | min_val = operand->bias; | |
5354 | max_val = min_val + (1 << operand_base->size) - 1; | |
5355 | max_high = operand->opsize; | |
5356 | ||
1a00e612 | 5357 | if (!match_const_int (arg, &size)) |
a92713e6 | 5358 | return FALSE; |
a1d78564 RS |
5359 | |
5360 | high = size + arg->last_op_int; | |
5361 | sval = operand->add_lsb ? high : size; | |
5362 | ||
5363 | if (size < 0 || high > max_high || sval < min_val || sval > max_val) | |
5364 | { | |
1a00e612 RS |
5365 | match_out_of_range (arg); |
5366 | return FALSE; | |
a1d78564 RS |
5367 | } |
5368 | insn_insert_operand (arg->insn, operand_base, sval - min_val); | |
a92713e6 | 5369 | return TRUE; |
a1d78564 RS |
5370 | } |
5371 | ||
5372 | /* OP_REG matcher. */ | |
5373 | ||
a92713e6 | 5374 | static bfd_boolean |
a1d78564 | 5375 | match_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5376 | const struct mips_operand *operand_base) |
a1d78564 RS |
5377 | { |
5378 | const struct mips_reg_operand *operand; | |
a92713e6 | 5379 | unsigned int regno, uval, num_vals; |
a1d78564 RS |
5380 | |
5381 | operand = (const struct mips_reg_operand *) operand_base; | |
a92713e6 RS |
5382 | if (!match_reg (arg, operand->reg_type, ®no)) |
5383 | return FALSE; | |
a1d78564 RS |
5384 | |
5385 | if (operand->reg_map) | |
5386 | { | |
5387 | num_vals = 1 << operand->root.size; | |
5388 | for (uval = 0; uval < num_vals; uval++) | |
5389 | if (operand->reg_map[uval] == regno) | |
5390 | break; | |
5391 | if (num_vals == uval) | |
a92713e6 | 5392 | return FALSE; |
a1d78564 RS |
5393 | } |
5394 | else | |
5395 | uval = regno; | |
5396 | ||
a1d78564 RS |
5397 | arg->last_regno = regno; |
5398 | if (arg->opnum == 1) | |
5399 | arg->dest_regno = regno; | |
5400 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5401 | return TRUE; |
a1d78564 RS |
5402 | } |
5403 | ||
5404 | /* OP_REG_PAIR matcher. */ | |
5405 | ||
a92713e6 | 5406 | static bfd_boolean |
a1d78564 | 5407 | match_reg_pair_operand (struct mips_arg_info *arg, |
a92713e6 | 5408 | const struct mips_operand *operand_base) |
a1d78564 RS |
5409 | { |
5410 | const struct mips_reg_pair_operand *operand; | |
a92713e6 | 5411 | unsigned int regno1, regno2, uval, num_vals; |
a1d78564 RS |
5412 | |
5413 | operand = (const struct mips_reg_pair_operand *) operand_base; | |
a92713e6 RS |
5414 | if (!match_reg (arg, operand->reg_type, ®no1) |
5415 | || !match_char (arg, ',') | |
5416 | || !match_reg (arg, operand->reg_type, ®no2)) | |
5417 | return FALSE; | |
a1d78564 RS |
5418 | |
5419 | num_vals = 1 << operand_base->size; | |
5420 | for (uval = 0; uval < num_vals; uval++) | |
5421 | if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2) | |
5422 | break; | |
5423 | if (uval == num_vals) | |
a92713e6 | 5424 | return FALSE; |
a1d78564 | 5425 | |
a1d78564 | 5426 | insn_insert_operand (arg->insn, operand_base, uval); |
a92713e6 | 5427 | return TRUE; |
a1d78564 RS |
5428 | } |
5429 | ||
5430 | /* OP_PCREL matcher. The caller chooses the relocation type. */ | |
5431 | ||
a92713e6 RS |
5432 | static bfd_boolean |
5433 | match_pcrel_operand (struct mips_arg_info *arg) | |
a1d78564 | 5434 | { |
a92713e6 RS |
5435 | bfd_reloc_code_real_type r[3]; |
5436 | ||
5437 | return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED; | |
a1d78564 RS |
5438 | } |
5439 | ||
5440 | /* OP_PERF_REG matcher. */ | |
5441 | ||
a92713e6 | 5442 | static bfd_boolean |
a1d78564 | 5443 | match_perf_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5444 | const struct mips_operand *operand) |
a1d78564 RS |
5445 | { |
5446 | offsetT sval; | |
5447 | ||
1a00e612 | 5448 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5449 | return FALSE; |
a1d78564 RS |
5450 | |
5451 | if (sval != 0 | |
5452 | && (sval != 1 | |
5453 | || (mips_opts.arch == CPU_R5900 | |
5454 | && (strcmp (arg->insn->insn_mo->name, "mfps") == 0 | |
5455 | || strcmp (arg->insn->insn_mo->name, "mtps") == 0)))) | |
5456 | { | |
1a00e612 RS |
5457 | set_insn_error (arg->argnum, _("invalid performance register")); |
5458 | return FALSE; | |
a1d78564 RS |
5459 | } |
5460 | ||
5461 | insn_insert_operand (arg->insn, operand, sval); | |
a92713e6 | 5462 | return TRUE; |
a1d78564 RS |
5463 | } |
5464 | ||
5465 | /* OP_ADDIUSP matcher. */ | |
5466 | ||
a92713e6 | 5467 | static bfd_boolean |
a1d78564 | 5468 | match_addiusp_operand (struct mips_arg_info *arg, |
a92713e6 | 5469 | const struct mips_operand *operand) |
a1d78564 RS |
5470 | { |
5471 | offsetT sval; | |
5472 | unsigned int uval; | |
5473 | ||
1a00e612 | 5474 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5475 | return FALSE; |
a1d78564 RS |
5476 | |
5477 | if (sval % 4) | |
1a00e612 RS |
5478 | { |
5479 | match_out_of_range (arg); | |
5480 | return FALSE; | |
5481 | } | |
a1d78564 RS |
5482 | |
5483 | sval /= 4; | |
5484 | if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1)) | |
1a00e612 RS |
5485 | { |
5486 | match_out_of_range (arg); | |
5487 | return FALSE; | |
5488 | } | |
a1d78564 RS |
5489 | |
5490 | uval = (unsigned int) sval; | |
5491 | uval = ((uval >> 1) & ~0xff) | (uval & 0xff); | |
5492 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5493 | return TRUE; |
a1d78564 RS |
5494 | } |
5495 | ||
5496 | /* OP_CLO_CLZ_DEST matcher. */ | |
5497 | ||
a92713e6 | 5498 | static bfd_boolean |
a1d78564 | 5499 | match_clo_clz_dest_operand (struct mips_arg_info *arg, |
a92713e6 | 5500 | const struct mips_operand *operand) |
a1d78564 RS |
5501 | { |
5502 | unsigned int regno; | |
5503 | ||
a92713e6 RS |
5504 | if (!match_reg (arg, OP_REG_GP, ®no)) |
5505 | return FALSE; | |
a1d78564 | 5506 | |
a1d78564 | 5507 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); |
a92713e6 | 5508 | return TRUE; |
a1d78564 RS |
5509 | } |
5510 | ||
7361da2c AB |
5511 | /* OP_CHECK_PREV matcher. */ |
5512 | ||
5513 | static bfd_boolean | |
5514 | match_check_prev_operand (struct mips_arg_info *arg, | |
5515 | const struct mips_operand *operand_base) | |
5516 | { | |
5517 | const struct mips_check_prev_operand *operand; | |
5518 | unsigned int regno; | |
5519 | ||
5520 | operand = (const struct mips_check_prev_operand *) operand_base; | |
5521 | ||
5522 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5523 | return FALSE; | |
5524 | ||
5525 | if (!operand->zero_ok && regno == 0) | |
5526 | return FALSE; | |
5527 | ||
5528 | if ((operand->less_than_ok && regno < arg->last_regno) | |
5529 | || (operand->greater_than_ok && regno > arg->last_regno) | |
5530 | || (operand->equal_ok && regno == arg->last_regno)) | |
5531 | { | |
5532 | arg->last_regno = regno; | |
5533 | insn_insert_operand (arg->insn, operand_base, regno); | |
5534 | return TRUE; | |
5535 | } | |
5536 | ||
5537 | return FALSE; | |
5538 | } | |
5539 | ||
5540 | /* OP_SAME_RS_RT matcher. */ | |
5541 | ||
5542 | static bfd_boolean | |
5543 | match_same_rs_rt_operand (struct mips_arg_info *arg, | |
5544 | const struct mips_operand *operand) | |
5545 | { | |
5546 | unsigned int regno; | |
5547 | ||
5548 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5549 | return FALSE; | |
5550 | ||
5551 | if (regno == 0) | |
5552 | { | |
5553 | set_insn_error (arg->argnum, _("the source register must not be $0")); | |
5554 | return FALSE; | |
5555 | } | |
5556 | ||
5557 | arg->last_regno = regno; | |
5558 | ||
5559 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); | |
5560 | return TRUE; | |
5561 | } | |
5562 | ||
a1d78564 RS |
5563 | /* OP_LWM_SWM_LIST matcher. */ |
5564 | ||
a92713e6 | 5565 | static bfd_boolean |
a1d78564 | 5566 | match_lwm_swm_list_operand (struct mips_arg_info *arg, |
a92713e6 | 5567 | const struct mips_operand *operand) |
a1d78564 | 5568 | { |
a92713e6 RS |
5569 | unsigned int reglist, sregs, ra, regno1, regno2; |
5570 | struct mips_arg_info reset; | |
a1d78564 | 5571 | |
a92713e6 RS |
5572 | reglist = 0; |
5573 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) | |
5574 | return FALSE; | |
5575 | do | |
5576 | { | |
5577 | if (regno2 == FP && regno1 >= S0 && regno1 <= S7) | |
5578 | { | |
5579 | reglist |= 1 << FP; | |
5580 | regno2 = S7; | |
5581 | } | |
5582 | reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1); | |
5583 | reset = *arg; | |
5584 | } | |
5585 | while (match_char (arg, ',') | |
5586 | && match_reg_range (arg, OP_REG_GP, ®no1, ®no2)); | |
5587 | *arg = reset; | |
a1d78564 RS |
5588 | |
5589 | if (operand->size == 2) | |
5590 | { | |
5591 | /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.: | |
5592 | ||
5593 | s0, ra | |
5594 | s0, s1, ra, s2, s3 | |
5595 | s0-s2, ra | |
5596 | ||
5597 | and any permutations of these. */ | |
5598 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
a92713e6 | 5599 | return FALSE; |
a1d78564 RS |
5600 | |
5601 | sregs = (reglist >> 17) & 7; | |
5602 | ra = 0; | |
5603 | } | |
5604 | else | |
5605 | { | |
5606 | /* The list must include at least one of ra and s0-sN, | |
5607 | for 0 <= N <= 8. (Note that there is a gap between s7 and s8, | |
5608 | which are $23 and $30 respectively.) E.g.: | |
5609 | ||
5610 | ra | |
5611 | s0 | |
5612 | ra, s0, s1, s2 | |
5613 | s0-s8 | |
5614 | s0-s5, ra | |
5615 | ||
5616 | and any permutations of these. */ | |
5617 | if ((reglist & 0x3f00ffff) != 0) | |
a92713e6 | 5618 | return FALSE; |
a1d78564 RS |
5619 | |
5620 | ra = (reglist >> 27) & 0x10; | |
5621 | sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
5622 | } | |
5623 | sregs += 1; | |
5624 | if ((sregs & -sregs) != sregs) | |
a92713e6 | 5625 | return FALSE; |
a1d78564 RS |
5626 | |
5627 | insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra); | |
a92713e6 | 5628 | return TRUE; |
a1d78564 RS |
5629 | } |
5630 | ||
364215c8 RS |
5631 | /* OP_ENTRY_EXIT_LIST matcher. */ |
5632 | ||
a92713e6 | 5633 | static unsigned int |
364215c8 | 5634 | match_entry_exit_operand (struct mips_arg_info *arg, |
a92713e6 | 5635 | const struct mips_operand *operand) |
364215c8 RS |
5636 | { |
5637 | unsigned int mask; | |
5638 | bfd_boolean is_exit; | |
5639 | ||
5640 | /* The format is the same for both ENTRY and EXIT, but the constraints | |
5641 | are different. */ | |
5642 | is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0; | |
5643 | mask = (is_exit ? 7 << 3 : 0); | |
a92713e6 | 5644 | do |
364215c8 RS |
5645 | { |
5646 | unsigned int regno1, regno2; | |
5647 | bfd_boolean is_freg; | |
5648 | ||
a92713e6 | 5649 | if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
364215c8 | 5650 | is_freg = FALSE; |
a92713e6 | 5651 | else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2)) |
364215c8 RS |
5652 | is_freg = TRUE; |
5653 | else | |
a92713e6 | 5654 | return FALSE; |
364215c8 RS |
5655 | |
5656 | if (is_exit && is_freg && regno1 == 0 && regno2 < 2) | |
5657 | { | |
5658 | mask &= ~(7 << 3); | |
5659 | mask |= (5 + regno2) << 3; | |
5660 | } | |
5661 | else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7) | |
5662 | mask |= (regno2 - 3) << 3; | |
5663 | else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17) | |
5664 | mask |= (regno2 - 15) << 1; | |
5665 | else if (regno1 == RA && regno2 == RA) | |
5666 | mask |= 1; | |
5667 | else | |
a92713e6 | 5668 | return FALSE; |
364215c8 | 5669 | } |
a92713e6 RS |
5670 | while (match_char (arg, ',')); |
5671 | ||
364215c8 | 5672 | insn_insert_operand (arg->insn, operand, mask); |
a92713e6 | 5673 | return TRUE; |
364215c8 RS |
5674 | } |
5675 | ||
38bf472a MR |
5676 | /* Encode regular MIPS SAVE/RESTORE instruction operands according to |
5677 | the argument register mask AMASK, the number of static registers | |
5678 | saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1 | |
5679 | respectively, and the frame size FRAME_SIZE. */ | |
5680 | ||
5681 | static unsigned int | |
5682 | mips_encode_save_restore (unsigned int amask, unsigned int nsreg, | |
5683 | unsigned int ra, unsigned int s0, unsigned int s1, | |
5684 | unsigned int frame_size) | |
5685 | { | |
5686 | return ((nsreg << 23) | ((frame_size & 0xf0) << 15) | (amask << 15) | |
5687 | | (ra << 12) | (s0 << 11) | (s1 << 10) | ((frame_size & 0xf) << 6)); | |
5688 | } | |
5689 | ||
5690 | /* Encode MIPS16 SAVE/RESTORE instruction operands according to the | |
5691 | argument register mask AMASK, the number of static registers saved | |
5692 | NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1 | |
5693 | respectively, and the frame size FRAME_SIZE. */ | |
5694 | ||
5695 | static unsigned int | |
5696 | mips16_encode_save_restore (unsigned int amask, unsigned int nsreg, | |
5697 | unsigned int ra, unsigned int s0, unsigned int s1, | |
5698 | unsigned int frame_size) | |
5699 | { | |
5700 | unsigned int args; | |
5701 | ||
5702 | args = (ra << 6) | (s0 << 5) | (s1 << 4) | (frame_size & 0xf); | |
5703 | if (nsreg || amask || frame_size == 0 || frame_size > 16) | |
5704 | args |= (MIPS16_EXTEND | (nsreg << 24) | (amask << 16) | |
5705 | | ((frame_size & 0xf0) << 16)); | |
5706 | return args; | |
5707 | } | |
5708 | ||
364215c8 RS |
5709 | /* OP_SAVE_RESTORE_LIST matcher. */ |
5710 | ||
a92713e6 RS |
5711 | static bfd_boolean |
5712 | match_save_restore_list_operand (struct mips_arg_info *arg) | |
364215c8 RS |
5713 | { |
5714 | unsigned int opcode, args, statics, sregs; | |
5715 | unsigned int num_frame_sizes, num_args, num_statics, num_sregs; | |
38bf472a | 5716 | unsigned int arg_mask, ra, s0, s1; |
364215c8 | 5717 | offsetT frame_size; |
364215c8 | 5718 | |
364215c8 RS |
5719 | opcode = arg->insn->insn_opcode; |
5720 | frame_size = 0; | |
5721 | num_frame_sizes = 0; | |
5722 | args = 0; | |
5723 | statics = 0; | |
5724 | sregs = 0; | |
38bf472a MR |
5725 | ra = 0; |
5726 | s0 = 0; | |
5727 | s1 = 0; | |
a92713e6 | 5728 | do |
364215c8 RS |
5729 | { |
5730 | unsigned int regno1, regno2; | |
5731 | ||
a92713e6 | 5732 | if (arg->token->type == OT_INTEGER) |
364215c8 RS |
5733 | { |
5734 | /* Handle the frame size. */ | |
1a00e612 | 5735 | if (!match_const_int (arg, &frame_size)) |
a92713e6 | 5736 | return FALSE; |
364215c8 | 5737 | num_frame_sizes += 1; |
364215c8 RS |
5738 | } |
5739 | else | |
5740 | { | |
a92713e6 RS |
5741 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
5742 | return FALSE; | |
364215c8 RS |
5743 | |
5744 | while (regno1 <= regno2) | |
5745 | { | |
5746 | if (regno1 >= 4 && regno1 <= 7) | |
5747 | { | |
5748 | if (num_frame_sizes == 0) | |
5749 | /* args $a0-$a3 */ | |
5750 | args |= 1 << (regno1 - 4); | |
5751 | else | |
5752 | /* statics $a0-$a3 */ | |
5753 | statics |= 1 << (regno1 - 4); | |
5754 | } | |
5755 | else if (regno1 >= 16 && regno1 <= 23) | |
5756 | /* $s0-$s7 */ | |
5757 | sregs |= 1 << (regno1 - 16); | |
5758 | else if (regno1 == 30) | |
5759 | /* $s8 */ | |
5760 | sregs |= 1 << 8; | |
5761 | else if (regno1 == 31) | |
5762 | /* Add $ra to insn. */ | |
38bf472a | 5763 | ra = 1; |
364215c8 | 5764 | else |
a92713e6 | 5765 | return FALSE; |
364215c8 RS |
5766 | regno1 += 1; |
5767 | if (regno1 == 24) | |
5768 | regno1 = 30; | |
5769 | } | |
5770 | } | |
364215c8 | 5771 | } |
a92713e6 | 5772 | while (match_char (arg, ',')); |
364215c8 RS |
5773 | |
5774 | /* Encode args/statics combination. */ | |
5775 | if (args & statics) | |
a92713e6 | 5776 | return FALSE; |
364215c8 RS |
5777 | else if (args == 0xf) |
5778 | /* All $a0-$a3 are args. */ | |
38bf472a | 5779 | arg_mask = MIPS_SVRS_ALL_ARGS; |
364215c8 RS |
5780 | else if (statics == 0xf) |
5781 | /* All $a0-$a3 are statics. */ | |
38bf472a | 5782 | arg_mask = MIPS_SVRS_ALL_STATICS; |
364215c8 RS |
5783 | else |
5784 | { | |
5785 | /* Count arg registers. */ | |
5786 | num_args = 0; | |
5787 | while (args & 0x1) | |
5788 | { | |
5789 | args >>= 1; | |
5790 | num_args += 1; | |
5791 | } | |
5792 | if (args != 0) | |
a92713e6 | 5793 | return FALSE; |
364215c8 RS |
5794 | |
5795 | /* Count static registers. */ | |
5796 | num_statics = 0; | |
5797 | while (statics & 0x8) | |
5798 | { | |
5799 | statics = (statics << 1) & 0xf; | |
5800 | num_statics += 1; | |
5801 | } | |
5802 | if (statics != 0) | |
a92713e6 | 5803 | return FALSE; |
364215c8 RS |
5804 | |
5805 | /* Encode args/statics. */ | |
38bf472a | 5806 | arg_mask = (num_args << 2) | num_statics; |
364215c8 RS |
5807 | } |
5808 | ||
5809 | /* Encode $s0/$s1. */ | |
5810 | if (sregs & (1 << 0)) /* $s0 */ | |
38bf472a | 5811 | s0 = 1; |
364215c8 | 5812 | if (sregs & (1 << 1)) /* $s1 */ |
38bf472a | 5813 | s1 = 1; |
364215c8 RS |
5814 | sregs >>= 2; |
5815 | ||
5816 | /* Encode $s2-$s8. */ | |
5817 | num_sregs = 0; | |
5818 | while (sregs & 1) | |
5819 | { | |
5820 | sregs >>= 1; | |
5821 | num_sregs += 1; | |
5822 | } | |
5823 | if (sregs != 0) | |
a92713e6 | 5824 | return FALSE; |
364215c8 RS |
5825 | |
5826 | /* Encode frame size. */ | |
5827 | if (num_frame_sizes == 0) | |
1a00e612 RS |
5828 | { |
5829 | set_insn_error (arg->argnum, _("missing frame size")); | |
5830 | return FALSE; | |
5831 | } | |
5832 | if (num_frame_sizes > 1) | |
5833 | { | |
5834 | set_insn_error (arg->argnum, _("frame size specified twice")); | |
5835 | return FALSE; | |
5836 | } | |
5837 | if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8) | |
5838 | { | |
5839 | set_insn_error (arg->argnum, _("invalid frame size")); | |
5840 | return FALSE; | |
5841 | } | |
38bf472a | 5842 | frame_size /= 8; |
364215c8 | 5843 | |
364215c8 | 5844 | /* Finally build the instruction. */ |
38bf472a MR |
5845 | if (mips_opts.mips16) |
5846 | opcode |= mips16_encode_save_restore (arg_mask, num_sregs, ra, s0, s1, | |
5847 | frame_size); | |
5848 | else if (!mips_opts.micromips) | |
5849 | opcode |= mips_encode_save_restore (arg_mask, num_sregs, ra, s0, s1, | |
5850 | frame_size); | |
5851 | else | |
5852 | abort (); | |
5853 | ||
364215c8 | 5854 | arg->insn->insn_opcode = opcode; |
a92713e6 | 5855 | return TRUE; |
364215c8 RS |
5856 | } |
5857 | ||
a1d78564 RS |
5858 | /* OP_MDMX_IMM_REG matcher. */ |
5859 | ||
a92713e6 | 5860 | static bfd_boolean |
a1d78564 | 5861 | match_mdmx_imm_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5862 | const struct mips_operand *operand) |
a1d78564 | 5863 | { |
a92713e6 | 5864 | unsigned int regno, uval; |
a1d78564 RS |
5865 | bfd_boolean is_qh; |
5866 | const struct mips_opcode *opcode; | |
5867 | ||
5868 | /* The mips_opcode records whether this is an octobyte or quadhalf | |
5869 | instruction. Start out with that bit in place. */ | |
5870 | opcode = arg->insn->insn_mo; | |
5871 | uval = mips_extract_operand (operand, opcode->match); | |
5872 | is_qh = (uval != 0); | |
5873 | ||
56d438b1 | 5874 | if (arg->token->type == OT_REG) |
a1d78564 RS |
5875 | { |
5876 | if ((opcode->membership & INSN_5400) | |
5877 | && strcmp (opcode->name, "rzu.ob") == 0) | |
5878 | { | |
1a00e612 RS |
5879 | set_insn_error_i (arg->argnum, _("operand %d must be an immediate"), |
5880 | arg->argnum); | |
5881 | return FALSE; | |
a1d78564 RS |
5882 | } |
5883 | ||
56d438b1 CF |
5884 | if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no)) |
5885 | return FALSE; | |
5886 | ++arg->token; | |
5887 | ||
a1d78564 RS |
5888 | /* Check whether this is a vector register or a broadcast of |
5889 | a single element. */ | |
56d438b1 | 5890 | if (arg->token->type == OT_INTEGER_INDEX) |
a1d78564 | 5891 | { |
56d438b1 | 5892 | if (arg->token->u.index > (is_qh ? 3 : 7)) |
a1d78564 | 5893 | { |
1a00e612 RS |
5894 | set_insn_error (arg->argnum, _("invalid element selector")); |
5895 | return FALSE; | |
a1d78564 | 5896 | } |
56d438b1 CF |
5897 | uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5; |
5898 | ++arg->token; | |
a1d78564 RS |
5899 | } |
5900 | else | |
5901 | { | |
5902 | /* A full vector. */ | |
5903 | if ((opcode->membership & INSN_5400) | |
5904 | && (strcmp (opcode->name, "sll.ob") == 0 | |
5905 | || strcmp (opcode->name, "srl.ob") == 0)) | |
5906 | { | |
1a00e612 RS |
5907 | set_insn_error_i (arg->argnum, _("operand %d must be scalar"), |
5908 | arg->argnum); | |
5909 | return FALSE; | |
a1d78564 RS |
5910 | } |
5911 | ||
5912 | if (is_qh) | |
5913 | uval |= MDMX_FMTSEL_VEC_QH << 5; | |
5914 | else | |
5915 | uval |= MDMX_FMTSEL_VEC_OB << 5; | |
5916 | } | |
a1d78564 RS |
5917 | uval |= regno; |
5918 | } | |
5919 | else | |
5920 | { | |
5921 | offsetT sval; | |
5922 | ||
1a00e612 | 5923 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5924 | return FALSE; |
a1d78564 RS |
5925 | if (sval < 0 || sval > 31) |
5926 | { | |
1a00e612 RS |
5927 | match_out_of_range (arg); |
5928 | return FALSE; | |
a1d78564 RS |
5929 | } |
5930 | uval |= (sval & 31); | |
5931 | if (is_qh) | |
5932 | uval |= MDMX_FMTSEL_IMM_QH << 5; | |
5933 | else | |
5934 | uval |= MDMX_FMTSEL_IMM_OB << 5; | |
5935 | } | |
5936 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5937 | return TRUE; |
a1d78564 RS |
5938 | } |
5939 | ||
56d438b1 CF |
5940 | /* OP_IMM_INDEX matcher. */ |
5941 | ||
5942 | static bfd_boolean | |
5943 | match_imm_index_operand (struct mips_arg_info *arg, | |
5944 | const struct mips_operand *operand) | |
5945 | { | |
5946 | unsigned int max_val; | |
5947 | ||
5948 | if (arg->token->type != OT_INTEGER_INDEX) | |
5949 | return FALSE; | |
5950 | ||
5951 | max_val = (1 << operand->size) - 1; | |
5952 | if (arg->token->u.index > max_val) | |
5953 | { | |
5954 | match_out_of_range (arg); | |
5955 | return FALSE; | |
5956 | } | |
5957 | insn_insert_operand (arg->insn, operand, arg->token->u.index); | |
5958 | ++arg->token; | |
5959 | return TRUE; | |
5960 | } | |
5961 | ||
5962 | /* OP_REG_INDEX matcher. */ | |
5963 | ||
5964 | static bfd_boolean | |
5965 | match_reg_index_operand (struct mips_arg_info *arg, | |
5966 | const struct mips_operand *operand) | |
5967 | { | |
5968 | unsigned int regno; | |
5969 | ||
5970 | if (arg->token->type != OT_REG_INDEX) | |
5971 | return FALSE; | |
5972 | ||
5973 | if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)) | |
5974 | return FALSE; | |
5975 | ||
5976 | insn_insert_operand (arg->insn, operand, regno); | |
5977 | ++arg->token; | |
5978 | return TRUE; | |
5979 | } | |
5980 | ||
a1d78564 RS |
5981 | /* OP_PC matcher. */ |
5982 | ||
a92713e6 RS |
5983 | static bfd_boolean |
5984 | match_pc_operand (struct mips_arg_info *arg) | |
a1d78564 | 5985 | { |
a92713e6 RS |
5986 | if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC)) |
5987 | { | |
5988 | ++arg->token; | |
5989 | return TRUE; | |
5990 | } | |
5991 | return FALSE; | |
a1d78564 RS |
5992 | } |
5993 | ||
25499ac7 MR |
5994 | /* OP_REG28 matcher. */ |
5995 | ||
5996 | static bfd_boolean | |
5997 | match_reg28_operand (struct mips_arg_info *arg) | |
5998 | { | |
5999 | unsigned int regno; | |
6000 | ||
6001 | if (arg->token->type == OT_REG | |
6002 | && match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no) | |
6003 | && regno == GP) | |
6004 | { | |
6005 | ++arg->token; | |
6006 | return TRUE; | |
6007 | } | |
6008 | return FALSE; | |
6009 | } | |
6010 | ||
7361da2c AB |
6011 | /* OP_NON_ZERO_REG matcher. */ |
6012 | ||
6013 | static bfd_boolean | |
6014 | match_non_zero_reg_operand (struct mips_arg_info *arg, | |
6015 | const struct mips_operand *operand) | |
6016 | { | |
6017 | unsigned int regno; | |
6018 | ||
6019 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
6020 | return FALSE; | |
6021 | ||
6022 | if (regno == 0) | |
85bec12d MF |
6023 | { |
6024 | set_insn_error (arg->argnum, _("the source register must not be $0")); | |
6025 | return FALSE; | |
6026 | } | |
7361da2c AB |
6027 | |
6028 | arg->last_regno = regno; | |
6029 | insn_insert_operand (arg->insn, operand, regno); | |
6030 | return TRUE; | |
6031 | } | |
6032 | ||
a1d78564 RS |
6033 | /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the |
6034 | register that we need to match. */ | |
6035 | ||
a92713e6 RS |
6036 | static bfd_boolean |
6037 | match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno) | |
a1d78564 RS |
6038 | { |
6039 | unsigned int regno; | |
6040 | ||
a92713e6 | 6041 | return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno; |
a1d78564 RS |
6042 | } |
6043 | ||
33f46696 MR |
6044 | /* Try to match a floating-point constant from ARG for LI.S or LI.D. |
6045 | LENGTH is the length of the value in bytes (4 for float, 8 for double) | |
6046 | and USING_GPRS says whether the destination is a GPR rather than an FPR. | |
89565f1b RS |
6047 | |
6048 | Return the constant in IMM and OFFSET as follows: | |
6049 | ||
6050 | - If the constant should be loaded via memory, set IMM to O_absent and | |
6051 | OFFSET to the memory address. | |
6052 | ||
6053 | - Otherwise, if the constant should be loaded into two 32-bit registers, | |
6054 | set IMM to the O_constant to load into the high register and OFFSET | |
6055 | to the corresponding value for the low register. | |
6056 | ||
6057 | - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent. | |
6058 | ||
6059 | These constants only appear as the last operand in an instruction, | |
6060 | and every instruction that accepts them in any variant accepts them | |
6061 | in all variants. This means we don't have to worry about backing out | |
6062 | any changes if the instruction does not match. We just match | |
6063 | unconditionally and report an error if the constant is invalid. */ | |
6064 | ||
a92713e6 RS |
6065 | static bfd_boolean |
6066 | match_float_constant (struct mips_arg_info *arg, expressionS *imm, | |
6067 | expressionS *offset, int length, bfd_boolean using_gprs) | |
89565f1b | 6068 | { |
a92713e6 | 6069 | char *p; |
89565f1b RS |
6070 | segT seg, new_seg; |
6071 | subsegT subseg; | |
6072 | const char *newname; | |
a92713e6 | 6073 | unsigned char *data; |
89565f1b RS |
6074 | |
6075 | /* Where the constant is placed is based on how the MIPS assembler | |
6076 | does things: | |
6077 | ||
6078 | length == 4 && using_gprs -- immediate value only | |
6079 | length == 8 && using_gprs -- .rdata or immediate value | |
6080 | length == 4 && !using_gprs -- .lit4 or immediate value | |
6081 | length == 8 && !using_gprs -- .lit8 or immediate value | |
6082 | ||
6083 | The .lit4 and .lit8 sections are only used if permitted by the | |
6084 | -G argument. */ | |
a92713e6 | 6085 | if (arg->token->type != OT_FLOAT) |
1a00e612 RS |
6086 | { |
6087 | set_insn_error (arg->argnum, _("floating-point expression required")); | |
6088 | return FALSE; | |
6089 | } | |
a92713e6 RS |
6090 | |
6091 | gas_assert (arg->token->u.flt.length == length); | |
6092 | data = arg->token->u.flt.data; | |
6093 | ++arg->token; | |
89565f1b RS |
6094 | |
6095 | /* Handle 32-bit constants for which an immediate value is best. */ | |
6096 | if (length == 4 | |
6097 | && (using_gprs | |
6098 | || g_switch_value < 4 | |
6099 | || (data[0] == 0 && data[1] == 0) | |
6100 | || (data[2] == 0 && data[3] == 0))) | |
6101 | { | |
6102 | imm->X_op = O_constant; | |
6103 | if (!target_big_endian) | |
6104 | imm->X_add_number = bfd_getl32 (data); | |
6105 | else | |
6106 | imm->X_add_number = bfd_getb32 (data); | |
6107 | offset->X_op = O_absent; | |
a92713e6 | 6108 | return TRUE; |
89565f1b RS |
6109 | } |
6110 | ||
6111 | /* Handle 64-bit constants for which an immediate value is best. */ | |
6112 | if (length == 8 | |
6113 | && !mips_disable_float_construction | |
351cdf24 MF |
6114 | /* Constants can only be constructed in GPRs and copied to FPRs if the |
6115 | GPRs are at least as wide as the FPRs or MTHC1 is available. | |
6116 | Unlike most tests for 32-bit floating-point registers this check | |
6117 | specifically looks for GPR_SIZE == 32 as the FPXX ABI does not | |
6118 | permit 64-bit moves without MXHC1. | |
6119 | Force the constant into memory otherwise. */ | |
6120 | && (using_gprs | |
6121 | || GPR_SIZE == 64 | |
6122 | || ISA_HAS_MXHC1 (mips_opts.isa) | |
6123 | || FPR_SIZE == 32) | |
89565f1b RS |
6124 | && ((data[0] == 0 && data[1] == 0) |
6125 | || (data[2] == 0 && data[3] == 0)) | |
6126 | && ((data[4] == 0 && data[5] == 0) | |
6127 | || (data[6] == 0 && data[7] == 0))) | |
6128 | { | |
6129 | /* The value is simple enough to load with a couple of instructions. | |
6130 | If using 32-bit registers, set IMM to the high order 32 bits and | |
6131 | OFFSET to the low order 32 bits. Otherwise, set IMM to the entire | |
6132 | 64 bit constant. */ | |
351cdf24 | 6133 | if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64)) |
89565f1b RS |
6134 | { |
6135 | imm->X_op = O_constant; | |
6136 | offset->X_op = O_constant; | |
6137 | if (!target_big_endian) | |
6138 | { | |
6139 | imm->X_add_number = bfd_getl32 (data + 4); | |
6140 | offset->X_add_number = bfd_getl32 (data); | |
6141 | } | |
6142 | else | |
6143 | { | |
6144 | imm->X_add_number = bfd_getb32 (data); | |
6145 | offset->X_add_number = bfd_getb32 (data + 4); | |
6146 | } | |
6147 | if (offset->X_add_number == 0) | |
6148 | offset->X_op = O_absent; | |
6149 | } | |
6150 | else | |
6151 | { | |
6152 | imm->X_op = O_constant; | |
6153 | if (!target_big_endian) | |
6154 | imm->X_add_number = bfd_getl64 (data); | |
6155 | else | |
6156 | imm->X_add_number = bfd_getb64 (data); | |
6157 | offset->X_op = O_absent; | |
6158 | } | |
a92713e6 | 6159 | return TRUE; |
89565f1b RS |
6160 | } |
6161 | ||
6162 | /* Switch to the right section. */ | |
6163 | seg = now_seg; | |
6164 | subseg = now_subseg; | |
6165 | if (length == 4) | |
6166 | { | |
6167 | gas_assert (!using_gprs && g_switch_value >= 4); | |
6168 | newname = ".lit4"; | |
6169 | } | |
6170 | else | |
6171 | { | |
6172 | if (using_gprs || g_switch_value < 8) | |
6173 | newname = RDATA_SECTION_NAME; | |
6174 | else | |
6175 | newname = ".lit8"; | |
6176 | } | |
6177 | ||
6178 | new_seg = subseg_new (newname, (subsegT) 0); | |
fd361982 | 6179 | bfd_set_section_flags (new_seg, |
89565f1b RS |
6180 | SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA); |
6181 | frag_align (length == 4 ? 2 : 3, 0, 0); | |
6182 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
6183 | record_alignment (new_seg, 4); | |
6184 | else | |
6185 | record_alignment (new_seg, length == 4 ? 2 : 3); | |
6186 | if (seg == now_seg) | |
1661c76c | 6187 | as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name); |
89565f1b RS |
6188 | |
6189 | /* Set the argument to the current address in the section. */ | |
6190 | imm->X_op = O_absent; | |
6191 | offset->X_op = O_symbol; | |
6192 | offset->X_add_symbol = symbol_temp_new_now (); | |
6193 | offset->X_add_number = 0; | |
6194 | ||
6195 | /* Put the floating point number into the section. */ | |
6196 | p = frag_more (length); | |
6197 | memcpy (p, data, length); | |
6198 | ||
6199 | /* Switch back to the original section. */ | |
6200 | subseg_set (seg, subseg); | |
a92713e6 | 6201 | return TRUE; |
89565f1b RS |
6202 | } |
6203 | ||
14daeee3 RS |
6204 | /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between |
6205 | them. */ | |
6206 | ||
6207 | static bfd_boolean | |
6208 | match_vu0_suffix_operand (struct mips_arg_info *arg, | |
6209 | const struct mips_operand *operand, | |
6210 | bfd_boolean match_p) | |
6211 | { | |
6212 | unsigned int uval; | |
6213 | ||
6214 | /* The operand can be an XYZW mask or a single 2-bit channel index | |
6215 | (with X being 0). */ | |
6216 | gas_assert (operand->size == 2 || operand->size == 4); | |
6217 | ||
ee5734f0 | 6218 | /* The suffix can be omitted when it is already part of the opcode. */ |
14daeee3 | 6219 | if (arg->token->type != OT_CHANNELS) |
ee5734f0 | 6220 | return match_p; |
14daeee3 RS |
6221 | |
6222 | uval = arg->token->u.channels; | |
6223 | if (operand->size == 2) | |
6224 | { | |
6225 | /* Check that a single bit is set and convert it into a 2-bit index. */ | |
6226 | if ((uval & -uval) != uval) | |
6227 | return FALSE; | |
6228 | uval = 4 - ffs (uval); | |
6229 | } | |
6230 | ||
6231 | if (match_p && insn_extract_operand (arg->insn, operand) != uval) | |
6232 | return FALSE; | |
6233 | ||
6234 | ++arg->token; | |
6235 | if (!match_p) | |
6236 | insn_insert_operand (arg->insn, operand, uval); | |
6237 | return TRUE; | |
6238 | } | |
6239 | ||
33f46696 MR |
6240 | /* Try to match a token from ARG against OPERAND. Consume the token |
6241 | and return true on success, otherwise return false. */ | |
a1d78564 | 6242 | |
a92713e6 | 6243 | static bfd_boolean |
a1d78564 | 6244 | match_operand (struct mips_arg_info *arg, |
a92713e6 | 6245 | const struct mips_operand *operand) |
a1d78564 RS |
6246 | { |
6247 | switch (operand->type) | |
6248 | { | |
6249 | case OP_INT: | |
a92713e6 | 6250 | return match_int_operand (arg, operand); |
a1d78564 RS |
6251 | |
6252 | case OP_MAPPED_INT: | |
a92713e6 | 6253 | return match_mapped_int_operand (arg, operand); |
a1d78564 RS |
6254 | |
6255 | case OP_MSB: | |
a92713e6 | 6256 | return match_msb_operand (arg, operand); |
a1d78564 RS |
6257 | |
6258 | case OP_REG: | |
0f35dbc4 | 6259 | case OP_OPTIONAL_REG: |
a92713e6 | 6260 | return match_reg_operand (arg, operand); |
a1d78564 RS |
6261 | |
6262 | case OP_REG_PAIR: | |
a92713e6 | 6263 | return match_reg_pair_operand (arg, operand); |
a1d78564 RS |
6264 | |
6265 | case OP_PCREL: | |
a92713e6 | 6266 | return match_pcrel_operand (arg); |
a1d78564 RS |
6267 | |
6268 | case OP_PERF_REG: | |
a92713e6 | 6269 | return match_perf_reg_operand (arg, operand); |
a1d78564 RS |
6270 | |
6271 | case OP_ADDIUSP_INT: | |
a92713e6 | 6272 | return match_addiusp_operand (arg, operand); |
a1d78564 RS |
6273 | |
6274 | case OP_CLO_CLZ_DEST: | |
a92713e6 | 6275 | return match_clo_clz_dest_operand (arg, operand); |
a1d78564 RS |
6276 | |
6277 | case OP_LWM_SWM_LIST: | |
a92713e6 | 6278 | return match_lwm_swm_list_operand (arg, operand); |
a1d78564 RS |
6279 | |
6280 | case OP_ENTRY_EXIT_LIST: | |
a92713e6 | 6281 | return match_entry_exit_operand (arg, operand); |
364215c8 | 6282 | |
a1d78564 | 6283 | case OP_SAVE_RESTORE_LIST: |
a92713e6 | 6284 | return match_save_restore_list_operand (arg); |
a1d78564 RS |
6285 | |
6286 | case OP_MDMX_IMM_REG: | |
a92713e6 | 6287 | return match_mdmx_imm_reg_operand (arg, operand); |
a1d78564 RS |
6288 | |
6289 | case OP_REPEAT_DEST_REG: | |
a92713e6 | 6290 | return match_tied_reg_operand (arg, arg->dest_regno); |
a1d78564 RS |
6291 | |
6292 | case OP_REPEAT_PREV_REG: | |
a92713e6 | 6293 | return match_tied_reg_operand (arg, arg->last_regno); |
a1d78564 RS |
6294 | |
6295 | case OP_PC: | |
a92713e6 | 6296 | return match_pc_operand (arg); |
14daeee3 | 6297 | |
25499ac7 MR |
6298 | case OP_REG28: |
6299 | return match_reg28_operand (arg); | |
6300 | ||
14daeee3 RS |
6301 | case OP_VU0_SUFFIX: |
6302 | return match_vu0_suffix_operand (arg, operand, FALSE); | |
6303 | ||
6304 | case OP_VU0_MATCH_SUFFIX: | |
6305 | return match_vu0_suffix_operand (arg, operand, TRUE); | |
56d438b1 CF |
6306 | |
6307 | case OP_IMM_INDEX: | |
6308 | return match_imm_index_operand (arg, operand); | |
6309 | ||
6310 | case OP_REG_INDEX: | |
6311 | return match_reg_index_operand (arg, operand); | |
7361da2c AB |
6312 | |
6313 | case OP_SAME_RS_RT: | |
6314 | return match_same_rs_rt_operand (arg, operand); | |
6315 | ||
6316 | case OP_CHECK_PREV: | |
6317 | return match_check_prev_operand (arg, operand); | |
6318 | ||
6319 | case OP_NON_ZERO_REG: | |
6320 | return match_non_zero_reg_operand (arg, operand); | |
a1d78564 RS |
6321 | } |
6322 | abort (); | |
6323 | } | |
6324 | ||
6325 | /* ARG is the state after successfully matching an instruction. | |
6326 | Issue any queued-up warnings. */ | |
6327 | ||
6328 | static void | |
6329 | check_completed_insn (struct mips_arg_info *arg) | |
6330 | { | |
6331 | if (arg->seen_at) | |
6332 | { | |
6333 | if (AT == ATREG) | |
1661c76c | 6334 | as_warn (_("used $at without \".set noat\"")); |
a1d78564 | 6335 | else |
1661c76c | 6336 | as_warn (_("used $%u with \".set at=$%u\""), AT, AT); |
a1d78564 RS |
6337 | } |
6338 | } | |
a1d78564 | 6339 | |
85fcb30f RS |
6340 | /* Return true if modifying general-purpose register REG needs a delay. */ |
6341 | ||
6342 | static bfd_boolean | |
6343 | reg_needs_delay (unsigned int reg) | |
6344 | { | |
6345 | unsigned long prev_pinfo; | |
6346 | ||
6347 | prev_pinfo = history[0].insn_mo->pinfo; | |
6348 | if (!mips_opts.noreorder | |
67dc82bc | 6349 | && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks) |
43885403 | 6350 | || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks)) |
85fcb30f RS |
6351 | && (gpr_write_mask (&history[0]) & (1 << reg))) |
6352 | return TRUE; | |
6353 | ||
6354 | return FALSE; | |
6355 | } | |
6356 | ||
71400594 RS |
6357 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
6358 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
6359 | by VR4120 errata. */ | |
4d7206a2 | 6360 | |
71400594 RS |
6361 | static unsigned int |
6362 | classify_vr4120_insn (const char *name) | |
252b5132 | 6363 | { |
71400594 RS |
6364 | if (strncmp (name, "macc", 4) == 0) |
6365 | return FIX_VR4120_MACC; | |
6366 | if (strncmp (name, "dmacc", 5) == 0) | |
6367 | return FIX_VR4120_DMACC; | |
6368 | if (strncmp (name, "mult", 4) == 0) | |
6369 | return FIX_VR4120_MULT; | |
6370 | if (strncmp (name, "dmult", 5) == 0) | |
6371 | return FIX_VR4120_DMULT; | |
6372 | if (strstr (name, "div")) | |
6373 | return FIX_VR4120_DIV; | |
6374 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
6375 | return FIX_VR4120_MTHILO; | |
6376 | return NUM_FIX_VR4120_CLASSES; | |
6377 | } | |
252b5132 | 6378 | |
a8d14a88 CM |
6379 | #define INSN_ERET 0x42000018 |
6380 | #define INSN_DERET 0x4200001f | |
6381 | #define INSN_DMULT 0x1c | |
6382 | #define INSN_DMULTU 0x1d | |
ff239038 | 6383 | |
71400594 RS |
6384 | /* Return the number of instructions that must separate INSN1 and INSN2, |
6385 | where INSN1 is the earlier instruction. Return the worst-case value | |
6386 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 6387 | |
71400594 RS |
6388 | static unsigned int |
6389 | insns_between (const struct mips_cl_insn *insn1, | |
6390 | const struct mips_cl_insn *insn2) | |
6391 | { | |
6392 | unsigned long pinfo1, pinfo2; | |
4c260379 | 6393 | unsigned int mask; |
71400594 | 6394 | |
85fcb30f RS |
6395 | /* If INFO2 is null, pessimistically assume that all flags are set for |
6396 | the second instruction. */ | |
71400594 RS |
6397 | pinfo1 = insn1->insn_mo->pinfo; |
6398 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 6399 | |
71400594 RS |
6400 | /* For most targets, write-after-read dependencies on the HI and LO |
6401 | registers must be separated by at least two instructions. */ | |
6402 | if (!hilo_interlocks) | |
252b5132 | 6403 | { |
71400594 RS |
6404 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
6405 | return 2; | |
6406 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
6407 | return 2; | |
6408 | } | |
6409 | ||
6410 | /* If we're working around r7000 errata, there must be two instructions | |
6411 | between an mfhi or mflo and any instruction that uses the result. */ | |
6412 | if (mips_7000_hilo_fix | |
df58fc94 | 6413 | && !mips_opts.micromips |
71400594 | 6414 | && MF_HILO_INSN (pinfo1) |
85fcb30f | 6415 | && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))) |
71400594 RS |
6416 | return 2; |
6417 | ||
ff239038 CM |
6418 | /* If we're working around 24K errata, one instruction is required |
6419 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 6420 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
6421 | { |
6422 | if (insn1->insn_opcode == INSN_ERET | |
6423 | || insn1->insn_opcode == INSN_DERET) | |
6424 | { | |
6425 | if (insn2 == NULL | |
6426 | || insn2->insn_opcode == INSN_ERET | |
6427 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 6428 | || delayed_branch_p (insn2)) |
ff239038 CM |
6429 | return 1; |
6430 | } | |
6431 | } | |
6432 | ||
a8d14a88 CM |
6433 | /* If we're working around PMC RM7000 errata, there must be three |
6434 | nops between a dmult and a load instruction. */ | |
6435 | if (mips_fix_rm7000 && !mips_opts.micromips) | |
6436 | { | |
6437 | if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT | |
6438 | || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU) | |
6439 | { | |
6440 | if (pinfo2 & INSN_LOAD_MEMORY) | |
6441 | return 3; | |
6442 | } | |
6443 | } | |
6444 | ||
71400594 RS |
6445 | /* If working around VR4120 errata, check for combinations that need |
6446 | a single intervening instruction. */ | |
df58fc94 | 6447 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
6448 | { |
6449 | unsigned int class1, class2; | |
252b5132 | 6450 | |
71400594 RS |
6451 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
6452 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 6453 | { |
71400594 RS |
6454 | if (insn2 == NULL) |
6455 | return 1; | |
6456 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
6457 | if (vr4120_conflicts[class1] & (1 << class2)) | |
6458 | return 1; | |
252b5132 | 6459 | } |
71400594 RS |
6460 | } |
6461 | ||
df58fc94 | 6462 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
6463 | { |
6464 | /* Check for GPR or coprocessor load delays. All such delays | |
6465 | are on the RT register. */ | |
6466 | /* Itbl support may require additional care here. */ | |
67dc82bc | 6467 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY)) |
43885403 | 6468 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC))) |
252b5132 | 6469 | { |
85fcb30f | 6470 | if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))) |
71400594 RS |
6471 | return 1; |
6472 | } | |
6473 | ||
6474 | /* Check for generic coprocessor hazards. | |
6475 | ||
6476 | This case is not handled very well. There is no special | |
6477 | knowledge of CP0 handling, and the coprocessors other than | |
6478 | the floating point unit are not distinguished at all. */ | |
6479 | /* Itbl support may require additional care here. FIXME! | |
6480 | Need to modify this to include knowledge about | |
6481 | user specified delays! */ | |
43885403 | 6482 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE)) |
71400594 RS |
6483 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) |
6484 | { | |
6485 | /* Handle cases where INSN1 writes to a known general coprocessor | |
6486 | register. There must be a one instruction delay before INSN2 | |
6487 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
6488 | mask = fpr_write_mask (insn1); |
6489 | if (mask != 0) | |
252b5132 | 6490 | { |
4c260379 | 6491 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 6492 | return 1; |
252b5132 RH |
6493 | } |
6494 | else | |
6495 | { | |
71400594 RS |
6496 | /* Read-after-write dependencies on the control registers |
6497 | require a two-instruction gap. */ | |
6498 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
6499 | && (pinfo2 & INSN_READ_COND_CODE)) | |
6500 | return 2; | |
6501 | ||
6502 | /* We don't know exactly what INSN1 does. If INSN2 is | |
6503 | also a coprocessor instruction, assume there must be | |
6504 | a one instruction gap. */ | |
6505 | if (pinfo2 & INSN_COP) | |
6506 | return 1; | |
252b5132 RH |
6507 | } |
6508 | } | |
6b76fefe | 6509 | |
71400594 RS |
6510 | /* Check for read-after-write dependencies on the coprocessor |
6511 | control registers in cases where INSN1 does not need a general | |
6512 | coprocessor delay. This means that INSN1 is a floating point | |
6513 | comparison instruction. */ | |
6514 | /* Itbl support may require additional care here. */ | |
6515 | else if (!cop_interlocks | |
6516 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
6517 | && (pinfo2 & INSN_READ_COND_CODE)) | |
6518 | return 1; | |
6519 | } | |
6b76fefe | 6520 | |
7361da2c AB |
6521 | /* Forbidden slots can not contain Control Transfer Instructions (CTIs) |
6522 | CTIs include all branches and jumps, nal, eret, eretnc, deret, wait | |
6523 | and pause. */ | |
6524 | if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT) | |
6525 | && ((pinfo2 & INSN_NO_DELAY_SLOT) | |
6526 | || (insn2 && delayed_branch_p (insn2)))) | |
6527 | return 1; | |
6528 | ||
71400594 RS |
6529 | return 0; |
6530 | } | |
6b76fefe | 6531 | |
7d8e00cf RS |
6532 | /* Return the number of nops that would be needed to work around the |
6533 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
6534 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
6535 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
6536 | |
6537 | static int | |
932d1a1b | 6538 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
6539 | const struct mips_cl_insn *insn) |
6540 | { | |
4c260379 RS |
6541 | int i, j; |
6542 | unsigned int mask; | |
7d8e00cf RS |
6543 | |
6544 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
6545 | are not affected by the errata. */ | |
6546 | if (insn != 0 | |
6547 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
6548 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
6549 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
6550 | return 0; | |
6551 | ||
6552 | /* Search for the first MFLO or MFHI. */ | |
6553 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 6554 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
6555 | { |
6556 | /* Extract the destination register. */ | |
4c260379 | 6557 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
6558 | |
6559 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 6560 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
6561 | return 0; |
6562 | ||
6563 | /* ...or if any of the intervening instructions do. */ | |
6564 | for (j = 0; j < i; j++) | |
4c260379 | 6565 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
6566 | return 0; |
6567 | ||
932d1a1b RS |
6568 | if (i >= ignore) |
6569 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
6570 | } |
6571 | return 0; | |
6572 | } | |
6573 | ||
134c0c8b MR |
6574 | #define BASE_REG_EQ(INSN1, INSN2) \ |
6575 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
15be625d CM |
6576 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) |
6577 | ||
6578 | /* Return the minimum alignment for this store instruction. */ | |
6579 | ||
6580 | static int | |
6581 | fix_24k_align_to (const struct mips_opcode *mo) | |
6582 | { | |
6583 | if (strcmp (mo->name, "sh") == 0) | |
6584 | return 2; | |
6585 | ||
6586 | if (strcmp (mo->name, "swc1") == 0 | |
6587 | || strcmp (mo->name, "swc2") == 0 | |
6588 | || strcmp (mo->name, "sw") == 0 | |
6589 | || strcmp (mo->name, "sc") == 0 | |
6590 | || strcmp (mo->name, "s.s") == 0) | |
6591 | return 4; | |
6592 | ||
6593 | if (strcmp (mo->name, "sdc1") == 0 | |
6594 | || strcmp (mo->name, "sdc2") == 0 | |
6595 | || strcmp (mo->name, "s.d") == 0) | |
6596 | return 8; | |
6597 | ||
6598 | /* sb, swl, swr */ | |
6599 | return 1; | |
6600 | } | |
6601 | ||
6602 | struct fix_24k_store_info | |
6603 | { | |
6604 | /* Immediate offset, if any, for this store instruction. */ | |
6605 | short off; | |
6606 | /* Alignment required by this store instruction. */ | |
6607 | int align_to; | |
6608 | /* True for register offsets. */ | |
6609 | int register_offset; | |
6610 | }; | |
6611 | ||
6612 | /* Comparison function used by qsort. */ | |
6613 | ||
6614 | static int | |
6615 | fix_24k_sort (const void *a, const void *b) | |
6616 | { | |
6617 | const struct fix_24k_store_info *pos1 = a; | |
6618 | const struct fix_24k_store_info *pos2 = b; | |
6619 | ||
6620 | return (pos1->off - pos2->off); | |
6621 | } | |
6622 | ||
6623 | /* INSN is a store instruction. Try to record the store information | |
6624 | in STINFO. Return false if the information isn't known. */ | |
6625 | ||
6626 | static bfd_boolean | |
6627 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 6628 | const struct mips_cl_insn *insn) |
15be625d CM |
6629 | { |
6630 | /* The instruction must have a known offset. */ | |
6631 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
6632 | return FALSE; | |
6633 | ||
6634 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
6635 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
6636 | return TRUE; | |
6637 | } | |
6638 | ||
932d1a1b RS |
6639 | /* Return the number of nops that would be needed to work around the 24k |
6640 | "lost data on stores during refill" errata if instruction INSN | |
6641 | immediately followed the 2 instructions described by HIST. | |
6642 | Ignore hazards that are contained within the first IGNORE | |
6643 | instructions of HIST. | |
6644 | ||
6645 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
6646 | for the data cache refills and store data. The following describes | |
6647 | the scenario where the store data could be lost. | |
6648 | ||
6649 | * A data cache miss, due to either a load or a store, causing fill | |
6650 | data to be supplied by the memory subsystem | |
6651 | * The first three doublewords of fill data are returned and written | |
6652 | into the cache | |
6653 | * A sequence of four stores occurs in consecutive cycles around the | |
6654 | final doubleword of the fill: | |
6655 | * Store A | |
6656 | * Store B | |
6657 | * Store C | |
6658 | * Zero, One or more instructions | |
6659 | * Store D | |
6660 | ||
6661 | The four stores A-D must be to different doublewords of the line that | |
6662 | is being filled. The fourth instruction in the sequence above permits | |
6663 | the fill of the final doubleword to be transferred from the FSB into | |
6664 | the cache. In the sequence above, the stores may be either integer | |
6665 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
6666 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
6667 | different doublewords on the line. If the floating point unit is | |
6668 | running in 1:2 mode, it is not possible to create the sequence above | |
6669 | using only floating point store instructions. | |
15be625d CM |
6670 | |
6671 | In this case, the cache line being filled is incorrectly marked | |
6672 | invalid, thereby losing the data from any store to the line that | |
6673 | occurs between the original miss and the completion of the five | |
6674 | cycle sequence shown above. | |
6675 | ||
932d1a1b | 6676 | The workarounds are: |
15be625d | 6677 | |
932d1a1b RS |
6678 | * Run the data cache in write-through mode. |
6679 | * Insert a non-store instruction between | |
6680 | Store A and Store B or Store B and Store C. */ | |
3739860c | 6681 | |
15be625d | 6682 | static int |
932d1a1b | 6683 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
6684 | const struct mips_cl_insn *insn) |
6685 | { | |
6686 | struct fix_24k_store_info pos[3]; | |
6687 | int align, i, base_offset; | |
6688 | ||
932d1a1b RS |
6689 | if (ignore >= 2) |
6690 | return 0; | |
6691 | ||
ab9794cf RS |
6692 | /* If the previous instruction wasn't a store, there's nothing to |
6693 | worry about. */ | |
15be625d CM |
6694 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
6695 | return 0; | |
6696 | ||
ab9794cf RS |
6697 | /* If the instructions after the previous one are unknown, we have |
6698 | to assume the worst. */ | |
6699 | if (!insn) | |
15be625d CM |
6700 | return 1; |
6701 | ||
ab9794cf RS |
6702 | /* Check whether we are dealing with three consecutive stores. */ |
6703 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
6704 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
6705 | return 0; |
6706 | ||
6707 | /* If we don't know the relationship between the store addresses, | |
6708 | assume the worst. */ | |
ab9794cf | 6709 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
6710 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
6711 | return 1; | |
6712 | ||
6713 | if (!fix_24k_record_store_info (&pos[0], insn) | |
6714 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
6715 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
6716 | return 1; | |
6717 | ||
6718 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
6719 | ||
6720 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
6721 | X bytes and such that the base register + X is known to be aligned | |
6722 | to align bytes. */ | |
6723 | ||
6724 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
6725 | align = 8; | |
6726 | else | |
6727 | { | |
6728 | align = pos[0].align_to; | |
6729 | base_offset = pos[0].off; | |
6730 | for (i = 1; i < 3; i++) | |
6731 | if (align < pos[i].align_to) | |
6732 | { | |
6733 | align = pos[i].align_to; | |
6734 | base_offset = pos[i].off; | |
6735 | } | |
6736 | for (i = 0; i < 3; i++) | |
6737 | pos[i].off -= base_offset; | |
6738 | } | |
6739 | ||
6740 | pos[0].off &= ~align + 1; | |
6741 | pos[1].off &= ~align + 1; | |
6742 | pos[2].off &= ~align + 1; | |
6743 | ||
6744 | /* If any two stores write to the same chunk, they also write to the | |
6745 | same doubleword. The offsets are still sorted at this point. */ | |
6746 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
6747 | return 0; | |
6748 | ||
6749 | /* A range of at least 9 bytes is needed for the stores to be in | |
6750 | non-overlapping doublewords. */ | |
6751 | if (pos[2].off - pos[0].off <= 8) | |
6752 | return 0; | |
6753 | ||
6754 | if (pos[2].off - pos[1].off >= 24 | |
6755 | || pos[1].off - pos[0].off >= 24 | |
6756 | || pos[2].off - pos[0].off >= 32) | |
6757 | return 0; | |
6758 | ||
6759 | return 1; | |
6760 | } | |
6761 | ||
71400594 | 6762 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 6763 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
6764 | where HIST[0] is the most recent instruction. Ignore hazards |
6765 | between INSN and the first IGNORE instructions in HIST. | |
6766 | ||
6767 | If INSN is null, return the worse-case number of nops for any | |
6768 | instruction. */ | |
bdaaa2e1 | 6769 | |
71400594 | 6770 | static int |
932d1a1b | 6771 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6772 | const struct mips_cl_insn *insn) |
6773 | { | |
6774 | int i, nops, tmp_nops; | |
bdaaa2e1 | 6775 | |
71400594 | 6776 | nops = 0; |
932d1a1b | 6777 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 6778 | { |
91d6fa6a | 6779 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
6780 | if (tmp_nops > nops) |
6781 | nops = tmp_nops; | |
6782 | } | |
7d8e00cf | 6783 | |
df58fc94 | 6784 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 6785 | { |
932d1a1b | 6786 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
6787 | if (tmp_nops > nops) |
6788 | nops = tmp_nops; | |
6789 | } | |
6790 | ||
df58fc94 | 6791 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 6792 | { |
932d1a1b | 6793 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
6794 | if (tmp_nops > nops) |
6795 | nops = tmp_nops; | |
6796 | } | |
6797 | ||
71400594 RS |
6798 | return nops; |
6799 | } | |
252b5132 | 6800 | |
71400594 | 6801 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 6802 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
6803 | would be needed after the extended sequence, ignoring hazards |
6804 | in the first IGNORE instructions. */ | |
252b5132 | 6805 | |
71400594 | 6806 | static int |
932d1a1b RS |
6807 | nops_for_sequence (int num_insns, int ignore, |
6808 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
6809 | { |
6810 | va_list args; | |
6811 | struct mips_cl_insn buffer[MAX_NOPS]; | |
6812 | struct mips_cl_insn *cursor; | |
6813 | int nops; | |
6814 | ||
91d6fa6a | 6815 | va_start (args, hist); |
71400594 | 6816 | cursor = buffer + num_insns; |
91d6fa6a | 6817 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
6818 | while (cursor > buffer) |
6819 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
6820 | ||
932d1a1b | 6821 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
6822 | va_end (args); |
6823 | return nops; | |
6824 | } | |
252b5132 | 6825 | |
71400594 RS |
6826 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
6827 | worst-case delay for the branch target. */ | |
252b5132 | 6828 | |
71400594 | 6829 | static int |
932d1a1b | 6830 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6831 | const struct mips_cl_insn *insn) |
6832 | { | |
6833 | int nops, tmp_nops; | |
60b63b72 | 6834 | |
932d1a1b | 6835 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 6836 | if (delayed_branch_p (insn)) |
71400594 | 6837 | { |
932d1a1b | 6838 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 6839 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
6840 | if (tmp_nops > nops) |
6841 | nops = tmp_nops; | |
6842 | } | |
11625dd8 | 6843 | else if (compact_branch_p (insn)) |
71400594 | 6844 | { |
932d1a1b | 6845 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
6846 | if (tmp_nops > nops) |
6847 | nops = tmp_nops; | |
6848 | } | |
6849 | return nops; | |
6850 | } | |
6851 | ||
c67a084a NC |
6852 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
6853 | ||
6854 | static void | |
6855 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
6856 | { | |
df58fc94 | 6857 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6858 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
6859 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
6860 | } | |
6861 | ||
6862 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
6863 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
6864 | ||
6865 | static void | |
6866 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
6867 | { | |
df58fc94 | 6868 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6869 | if (strcmp (ip->insn_mo->name, "j") == 0 |
6870 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
6871 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
6872 | { | |
6873 | int sreg; | |
6874 | expressionS ep; | |
6875 | ||
6876 | if (! mips_opts.at) | |
6877 | return; | |
6878 | ||
df58fc94 | 6879 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
6880 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
6881 | return; | |
6882 | ||
6883 | ep.X_op = O_constant; | |
6884 | ep.X_add_number = 0xcfff0000; | |
6885 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
6886 | ep.X_add_number = 0xffff; | |
6887 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
6888 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
6889 | } | |
6890 | } | |
6891 | ||
6892 | static void | |
6893 | fix_loongson2f (struct mips_cl_insn * ip) | |
6894 | { | |
6895 | if (mips_fix_loongson2f_nop) | |
6896 | fix_loongson2f_nop (ip); | |
6897 | ||
6898 | if (mips_fix_loongson2f_jump) | |
6899 | fix_loongson2f_jump (ip); | |
6900 | } | |
6901 | ||
dec7b24b YS |
6902 | static bfd_boolean |
6903 | has_label_name (const char *arr[], size_t len ,const char *s) | |
6904 | { | |
6905 | unsigned long i; | |
6906 | for (i = 0; i < len; i++) | |
6907 | { | |
6908 | if (!arr[i]) | |
6909 | return FALSE; | |
6910 | if (streq (arr[i], s)) | |
6911 | return TRUE; | |
6912 | } | |
6913 | return FALSE; | |
6914 | } | |
6915 | ||
6916 | /* Fix loongson3 llsc errata: Insert sync before ll/lld. */ | |
6f2117ba PH |
6917 | |
6918 | static void | |
6919 | fix_loongson3_llsc (struct mips_cl_insn * ip) | |
6920 | { | |
6921 | gas_assert (!HAVE_CODE_COMPRESSION); | |
6922 | ||
6923 | /* If is an local label and the insn is not sync, | |
6924 | look forward that whether an branch between ll/sc jump to here | |
6925 | if so, insert a sync. */ | |
6926 | if (seg_info (now_seg)->label_list | |
6927 | && S_IS_LOCAL (seg_info (now_seg)->label_list->label) | |
6928 | && (strcmp (ip->insn_mo->name, "sync") != 0)) | |
6929 | { | |
6f2117ba | 6930 | unsigned long i; |
dec7b24b YS |
6931 | valueT label_value; |
6932 | const char *label_names[MAX_LABELS_SAME]; | |
6933 | const char *label_name; | |
6934 | ||
6935 | label_name = S_GET_NAME (seg_info (now_seg)->label_list->label); | |
6936 | label_names[0] = label_name; | |
6937 | struct insn_label_list *llist = seg_info (now_seg)->label_list; | |
6938 | label_value = S_GET_VALUE (llist->label); | |
6f2117ba | 6939 | |
dec7b24b YS |
6940 | for (i = 1; i < MAX_LABELS_SAME; i++) |
6941 | { | |
6942 | llist = llist->next; | |
6943 | if (!llist) | |
6944 | break; | |
6945 | if (S_GET_VALUE (llist->label) == label_value) | |
6946 | label_names[i] = S_GET_NAME (llist->label); | |
6947 | else | |
6948 | break; | |
6949 | } | |
6950 | for (; i < MAX_LABELS_SAME; i++) | |
6951 | label_names[i] = NULL; | |
6952 | ||
6953 | unsigned long lookback = ARRAY_SIZE (history); | |
6f2117ba PH |
6954 | for (i = 0; i < lookback; i++) |
6955 | { | |
6956 | if (streq (history[i].insn_mo->name, "ll") | |
6957 | || streq (history[i].insn_mo->name, "lld")) | |
6958 | break; | |
6959 | ||
6960 | if (streq (history[i].insn_mo->name, "sc") | |
6961 | || streq (history[i].insn_mo->name, "scd")) | |
6962 | { | |
6963 | unsigned long j; | |
6964 | ||
6965 | for (j = i + 1; j < lookback; j++) | |
6966 | { | |
6967 | if (streq (history[i].insn_mo->name, "ll") | |
6968 | || streq (history[i].insn_mo->name, "lld")) | |
6969 | break; | |
6970 | ||
6971 | if (delayed_branch_p (&history[j])) | |
6972 | { | |
dec7b24b YS |
6973 | if (has_label_name (label_names, |
6974 | MAX_LABELS_SAME, | |
6975 | history[j].target)) | |
6f2117ba PH |
6976 | { |
6977 | add_fixed_insn (&sync_insn); | |
6978 | insert_into_history (0, 1, &sync_insn); | |
6979 | i = lookback; | |
6980 | break; | |
6981 | } | |
6982 | } | |
6983 | } | |
6984 | } | |
6985 | } | |
6986 | } | |
6987 | /* If we find a sc, we look forward to look for an branch insn, | |
6988 | and see whether it jump back and out of ll/sc. */ | |
dec7b24b | 6989 | else if (streq (ip->insn_mo->name, "sc") || streq (ip->insn_mo->name, "scd")) |
6f2117ba PH |
6990 | { |
6991 | unsigned long lookback = ARRAY_SIZE (history) - 1; | |
6992 | unsigned long i; | |
6993 | ||
6994 | for (i = 0; i < lookback; i++) | |
6995 | { | |
6996 | if (streq (history[i].insn_mo->name, "ll") | |
6997 | || streq (history[i].insn_mo->name, "lld")) | |
6998 | break; | |
6999 | ||
7000 | if (delayed_branch_p (&history[i])) | |
7001 | { | |
7002 | unsigned long j; | |
7003 | ||
7004 | for (j = i + 1; j < lookback; j++) | |
7005 | { | |
7006 | if (streq (history[j].insn_mo->name, "ll") | |
7007 | || streq (history[i].insn_mo->name, "lld")) | |
7008 | break; | |
7009 | } | |
7010 | ||
7011 | for (; j < lookback; j++) | |
7012 | { | |
7013 | if (history[j].label[0] != '\0' | |
7014 | && streq (history[j].label, history[i].target) | |
7015 | && strcmp (history[j+1].insn_mo->name, "sync") != 0) | |
7016 | { | |
7017 | add_fixed_insn (&sync_insn); | |
7018 | insert_into_history (++j, 1, &sync_insn); | |
7019 | } | |
7020 | } | |
7021 | } | |
7022 | } | |
7023 | } | |
7024 | ||
7025 | /* Skip if there is a sync before ll/lld. */ | |
7026 | if ((strcmp (ip->insn_mo->name, "ll") == 0 | |
7027 | || strcmp (ip->insn_mo->name, "lld") == 0) | |
7028 | && (strcmp (history[0].insn_mo->name, "sync") != 0)) | |
7029 | { | |
7030 | add_fixed_insn (&sync_insn); | |
7031 | insert_into_history (0, 1, &sync_insn); | |
7032 | } | |
7033 | } | |
7034 | ||
a4e06468 RS |
7035 | /* IP is a branch that has a delay slot, and we need to fill it |
7036 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
7037 | with the previous instruction. |
7038 | ADDRESS_EXPR is an operand of the instruction to be used with | |
7039 | RELOC_TYPE. */ | |
a4e06468 RS |
7040 | |
7041 | static bfd_boolean | |
e407c74b | 7042 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 7043 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 7044 | { |
2b0c8b40 | 7045 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 | 7046 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
9d5de888 | 7047 | unsigned int fpr_read, prev_fpr_write; |
a4e06468 RS |
7048 | |
7049 | /* -O2 and above is required for this optimization. */ | |
7050 | if (mips_optimize < 2) | |
7051 | return FALSE; | |
7052 | ||
7053 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
7054 | if (mips_opts.nomove) | |
7055 | return FALSE; | |
7056 | ||
7057 | /* We can't swap if the previous instruction's position is fixed. */ | |
7058 | if (history[0].fixed_p) | |
7059 | return FALSE; | |
7060 | ||
7061 | /* If the previous previous insn was in a .set noreorder, we can't | |
7062 | swap. Actually, the MIPS assembler will swap in this situation. | |
7063 | However, gcc configured -with-gnu-as will generate code like | |
7064 | ||
7065 | .set noreorder | |
7066 | lw $4,XXX | |
7067 | .set reorder | |
7068 | INSN | |
7069 | bne $4,$0,foo | |
7070 | ||
7071 | in which we can not swap the bne and INSN. If gcc is not configured | |
7072 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
7073 | if (history[1].noreorder_p) | |
7074 | return FALSE; | |
7075 | ||
87333bb7 MR |
7076 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
7077 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
7078 | if (mips_opts.mips16 && history[0].fixp[0]) |
7079 | return FALSE; | |
7080 | ||
7081 | /* If the branch is itself the target of a branch, we can not swap. | |
7082 | We cheat on this; all we check for is whether there is a label on | |
7083 | this instruction. If there are any branches to anything other than | |
7084 | a label, users must use .set noreorder. */ | |
7085 | if (seg_info (now_seg)->label_list) | |
7086 | return FALSE; | |
7087 | ||
7088 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 7089 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
7090 | MIPS16 code, which uses variant frags for different purposes. */ |
7091 | if (!mips_opts.mips16 | |
a4e06468 RS |
7092 | && history[0].frag |
7093 | && history[0].frag->fr_type == rs_machine_dependent) | |
7094 | return FALSE; | |
7095 | ||
bcd530a7 RS |
7096 | /* We do not swap with instructions that cannot architecturally |
7097 | be placed in a branch delay slot, such as SYNC or ERET. We | |
7098 | also refrain from swapping with a trap instruction, since it | |
7099 | complicates trap handlers to have the trap instruction be in | |
7100 | a delay slot. */ | |
a4e06468 | 7101 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 7102 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
7103 | return FALSE; |
7104 | ||
7105 | /* Check for conflicts between the branch and the instructions | |
7106 | before the candidate delay slot. */ | |
7107 | if (nops_for_insn (0, history + 1, ip) > 0) | |
7108 | return FALSE; | |
7109 | ||
7110 | /* Check for conflicts between the swapped sequence and the | |
7111 | target of the branch. */ | |
7112 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
7113 | return FALSE; | |
7114 | ||
7115 | /* If the branch reads a register that the previous | |
7116 | instruction sets, we can not swap. */ | |
7117 | gpr_read = gpr_read_mask (ip); | |
7118 | prev_gpr_write = gpr_write_mask (&history[0]); | |
7119 | if (gpr_read & prev_gpr_write) | |
7120 | return FALSE; | |
7121 | ||
9d5de888 CF |
7122 | fpr_read = fpr_read_mask (ip); |
7123 | prev_fpr_write = fpr_write_mask (&history[0]); | |
7124 | if (fpr_read & prev_fpr_write) | |
7125 | return FALSE; | |
7126 | ||
a4e06468 RS |
7127 | /* If the branch writes a register that the previous |
7128 | instruction sets, we can not swap. */ | |
7129 | gpr_write = gpr_write_mask (ip); | |
7130 | if (gpr_write & prev_gpr_write) | |
7131 | return FALSE; | |
7132 | ||
7133 | /* If the branch writes a register that the previous | |
7134 | instruction reads, we can not swap. */ | |
7135 | prev_gpr_read = gpr_read_mask (&history[0]); | |
7136 | if (gpr_write & prev_gpr_read) | |
7137 | return FALSE; | |
7138 | ||
7139 | /* If one instruction sets a condition code and the | |
7140 | other one uses a condition code, we can not swap. */ | |
7141 | pinfo = ip->insn_mo->pinfo; | |
7142 | if ((pinfo & INSN_READ_COND_CODE) | |
7143 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
7144 | return FALSE; | |
7145 | if ((pinfo & INSN_WRITE_COND_CODE) | |
7146 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
7147 | return FALSE; | |
7148 | ||
7149 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 7150 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
26545944 | 7151 | if (prev_pinfo2 & INSN2_READ_PC) |
2b0c8b40 | 7152 | return FALSE; |
a4e06468 | 7153 | |
df58fc94 RS |
7154 | /* If the previous instruction has an incorrect size for a fixed |
7155 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
7156 | pinfo2 = ip->insn_mo->pinfo2; |
7157 | if (mips_opts.micromips | |
7158 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
7159 | && insn_length (history) != 2) | |
7160 | return FALSE; | |
7161 | if (mips_opts.micromips | |
7162 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
7163 | && insn_length (history) != 4) | |
7164 | return FALSE; | |
7165 | ||
33d64ca5 FN |
7166 | /* On the R5900 short loops need to be fixed by inserting a NOP in the |
7167 | branch delay slot. | |
7168 | ||
7169 | The short loop bug under certain conditions causes loops to execute | |
7170 | only once or twice. We must ensure that the assembler never | |
7171 | generates loops that satisfy all of the following conditions: | |
7172 | ||
7173 | - a loop consists of less than or equal to six instructions | |
7174 | (including the branch delay slot); | |
7175 | - a loop contains only one conditional branch instruction at the end | |
7176 | of the loop; | |
7177 | - a loop does not contain any other branch or jump instructions; | |
7178 | - a branch delay slot of the loop is not NOP (EE 2.9 or later). | |
7179 | ||
7180 | We need to do this because of a hardware bug in the R5900 chip. */ | |
27c634e0 | 7181 | if (mips_fix_r5900 |
e407c74b NC |
7182 | /* Check if instruction has a parameter, ignore "j $31". */ |
7183 | && (address_expr != NULL) | |
7184 | /* Parameter must be 16 bit. */ | |
7185 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
7186 | /* Branch to same segment. */ | |
41065f5e | 7187 | && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg) |
e407c74b | 7188 | /* Branch to same code fragment. */ |
41065f5e | 7189 | && (symbol_get_frag (address_expr->X_add_symbol) == frag_now) |
e407c74b | 7190 | /* Can only calculate branch offset if value is known. */ |
41065f5e | 7191 | && symbol_constant_p (address_expr->X_add_symbol) |
e407c74b NC |
7192 | /* Check if branch is really conditional. */ |
7193 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
7194 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
7195 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
7196 | { | |
7197 | int distance; | |
33d64ca5 FN |
7198 | /* Check if loop is shorter than or equal to 6 instructions |
7199 | including branch and delay slot. */ | |
41065f5e | 7200 | distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol); |
e407c74b NC |
7201 | if (distance <= 20) |
7202 | { | |
7203 | int i; | |
7204 | int rv; | |
7205 | ||
7206 | rv = FALSE; | |
7207 | /* When the loop includes branches or jumps, | |
7208 | it is not a short loop. */ | |
7209 | for (i = 0; i < (distance / 4); i++) | |
7210 | { | |
7211 | if ((history[i].cleared_p) | |
41065f5e | 7212 | || delayed_branch_p (&history[i])) |
e407c74b NC |
7213 | { |
7214 | rv = TRUE; | |
7215 | break; | |
7216 | } | |
7217 | } | |
535b785f | 7218 | if (!rv) |
e407c74b NC |
7219 | { |
7220 | /* Insert nop after branch to fix short loop. */ | |
7221 | return FALSE; | |
7222 | } | |
7223 | } | |
7224 | } | |
7225 | ||
a4e06468 RS |
7226 | return TRUE; |
7227 | } | |
7228 | ||
e407c74b NC |
7229 | /* Decide how we should add IP to the instruction stream. |
7230 | ADDRESS_EXPR is an operand of the instruction to be used with | |
7231 | RELOC_TYPE. */ | |
a4e06468 RS |
7232 | |
7233 | static enum append_method | |
e407c74b | 7234 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 7235 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 7236 | { |
a4e06468 RS |
7237 | /* The relaxed version of a macro sequence must be inherently |
7238 | hazard-free. */ | |
7239 | if (mips_relax.sequence == 2) | |
7240 | return APPEND_ADD; | |
7241 | ||
3b821a28 | 7242 | /* We must not dabble with instructions in a ".set noreorder" block. */ |
a4e06468 RS |
7243 | if (mips_opts.noreorder) |
7244 | return APPEND_ADD; | |
7245 | ||
7246 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 7247 | if (delayed_branch_p (ip)) |
a4e06468 | 7248 | { |
e407c74b NC |
7249 | if (!branch_likely_p (ip) |
7250 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
7251 | return APPEND_SWAP; |
7252 | ||
7253 | if (mips_opts.mips16 | |
7254 | && ISA_SUPPORTS_MIPS16E | |
fc76e730 | 7255 | && gpr_read_mask (ip) != 0) |
a4e06468 RS |
7256 | return APPEND_ADD_COMPACT; |
7257 | ||
7bd374a4 MR |
7258 | if (mips_opts.micromips |
7259 | && ((ip->insn_opcode & 0xffe0) == 0x4580 | |
7260 | || (!forced_insn_length | |
7261 | && ((ip->insn_opcode & 0xfc00) == 0xcc00 | |
7262 | || (ip->insn_opcode & 0xdc00) == 0x8c00)) | |
7263 | || (ip->insn_opcode & 0xdfe00000) == 0x94000000 | |
7264 | || (ip->insn_opcode & 0xdc1f0000) == 0x94000000)) | |
7265 | return APPEND_ADD_COMPACT; | |
7266 | ||
a4e06468 RS |
7267 | return APPEND_ADD_WITH_NOP; |
7268 | } | |
7269 | ||
a4e06468 RS |
7270 | return APPEND_ADD; |
7271 | } | |
7272 | ||
7bd374a4 MR |
7273 | /* IP is an instruction whose opcode we have just changed, END points |
7274 | to the end of the opcode table processed. Point IP->insn_mo to the | |
7275 | new opcode's definition. */ | |
ceb94aa5 RS |
7276 | |
7277 | static void | |
7bd374a4 | 7278 | find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end) |
ceb94aa5 | 7279 | { |
7bd374a4 | 7280 | const struct mips_opcode *mo; |
ceb94aa5 | 7281 | |
ceb94aa5 | 7282 | for (mo = ip->insn_mo; mo < end; mo++) |
7bd374a4 MR |
7283 | if (mo->pinfo != INSN_MACRO |
7284 | && (ip->insn_opcode & mo->mask) == mo->match) | |
ceb94aa5 RS |
7285 | { |
7286 | ip->insn_mo = mo; | |
7287 | return; | |
7288 | } | |
7289 | abort (); | |
7290 | } | |
7291 | ||
7bd374a4 MR |
7292 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
7293 | Point IP->insn_mo to the new opcode's definition. */ | |
7294 | ||
7295 | static void | |
7296 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
7297 | { | |
7298 | find_altered_opcode (ip, &mips16_opcodes[bfd_mips16_num_opcodes]); | |
7299 | } | |
7300 | ||
7301 | /* IP is a microMIPS instruction whose opcode we have just changed. | |
7302 | Point IP->insn_mo to the new opcode's definition. */ | |
7303 | ||
7304 | static void | |
7305 | find_altered_micromips_opcode (struct mips_cl_insn *ip) | |
7306 | { | |
7307 | find_altered_opcode (ip, µmips_opcodes[bfd_micromips_num_opcodes]); | |
7308 | } | |
7309 | ||
df58fc94 RS |
7310 | /* For microMIPS macros, we need to generate a local number label |
7311 | as the target of branches. */ | |
7312 | #define MICROMIPS_LABEL_CHAR '\037' | |
7313 | static unsigned long micromips_target_label; | |
7314 | static char micromips_target_name[32]; | |
7315 | ||
7316 | static char * | |
7317 | micromips_label_name (void) | |
7318 | { | |
7319 | char *p = micromips_target_name; | |
7320 | char symbol_name_temporary[24]; | |
7321 | unsigned long l; | |
7322 | int i; | |
7323 | ||
7324 | if (*p) | |
7325 | return p; | |
7326 | ||
7327 | i = 0; | |
7328 | l = micromips_target_label; | |
7329 | #ifdef LOCAL_LABEL_PREFIX | |
7330 | *p++ = LOCAL_LABEL_PREFIX; | |
7331 | #endif | |
7332 | *p++ = 'L'; | |
7333 | *p++ = MICROMIPS_LABEL_CHAR; | |
7334 | do | |
7335 | { | |
7336 | symbol_name_temporary[i++] = l % 10 + '0'; | |
7337 | l /= 10; | |
7338 | } | |
7339 | while (l != 0); | |
7340 | while (i > 0) | |
7341 | *p++ = symbol_name_temporary[--i]; | |
7342 | *p = '\0'; | |
7343 | ||
7344 | return micromips_target_name; | |
7345 | } | |
7346 | ||
7347 | static void | |
7348 | micromips_label_expr (expressionS *label_expr) | |
7349 | { | |
7350 | label_expr->X_op = O_symbol; | |
7351 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
7352 | label_expr->X_add_number = 0; | |
7353 | } | |
7354 | ||
7355 | static void | |
7356 | micromips_label_inc (void) | |
7357 | { | |
7358 | micromips_target_label++; | |
7359 | *micromips_target_name = '\0'; | |
7360 | } | |
7361 | ||
7362 | static void | |
7363 | micromips_add_label (void) | |
7364 | { | |
7365 | symbolS *s; | |
7366 | ||
7367 | s = colon (micromips_label_name ()); | |
7368 | micromips_label_inc (); | |
f3ded42a | 7369 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); |
df58fc94 RS |
7370 | } |
7371 | ||
7372 | /* If assembling microMIPS code, then return the microMIPS reloc | |
7373 | corresponding to the requested one if any. Otherwise return | |
7374 | the reloc unchanged. */ | |
7375 | ||
7376 | static bfd_reloc_code_real_type | |
7377 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
7378 | { | |
7379 | static const bfd_reloc_code_real_type relocs[][2] = | |
7380 | { | |
7381 | /* Keep sorted incrementally by the left-hand key. */ | |
7382 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
7383 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
7384 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
7385 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
7386 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
7387 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
7388 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
7389 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
7390 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
7391 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
7392 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
7393 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
7394 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
7395 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
7396 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
7397 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
7398 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
7399 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
7400 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
7401 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
7402 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
7403 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
7404 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
7405 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
7406 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
7407 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
7408 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
7409 | }; | |
7410 | bfd_reloc_code_real_type r; | |
7411 | size_t i; | |
7412 | ||
7413 | if (!mips_opts.micromips) | |
7414 | return reloc; | |
7415 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
7416 | { | |
7417 | r = relocs[i][0]; | |
7418 | if (r > reloc) | |
7419 | return reloc; | |
7420 | if (r == reloc) | |
7421 | return relocs[i][1]; | |
7422 | } | |
7423 | return reloc; | |
7424 | } | |
7425 | ||
b886a2ab RS |
7426 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
7427 | Return true on success, storing the resolved value in RESULT. */ | |
7428 | ||
7429 | static bfd_boolean | |
7430 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
7431 | offsetT *result) | |
7432 | { | |
7433 | switch (reloc) | |
7434 | { | |
7435 | case BFD_RELOC_MIPS_HIGHEST: | |
7436 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
7437 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
7438 | return TRUE; | |
7439 | ||
7440 | case BFD_RELOC_MIPS_HIGHER: | |
7441 | case BFD_RELOC_MICROMIPS_HIGHER: | |
7442 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
7443 | return TRUE; | |
7444 | ||
7445 | case BFD_RELOC_HI16_S: | |
41947d9e | 7446 | case BFD_RELOC_HI16_S_PCREL: |
b886a2ab RS |
7447 | case BFD_RELOC_MICROMIPS_HI16_S: |
7448 | case BFD_RELOC_MIPS16_HI16_S: | |
7449 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
7450 | return TRUE; | |
7451 | ||
7452 | case BFD_RELOC_HI16: | |
7453 | case BFD_RELOC_MICROMIPS_HI16: | |
7454 | case BFD_RELOC_MIPS16_HI16: | |
7455 | *result = (operand >> 16) & 0xffff; | |
7456 | return TRUE; | |
7457 | ||
7458 | case BFD_RELOC_LO16: | |
41947d9e | 7459 | case BFD_RELOC_LO16_PCREL: |
b886a2ab RS |
7460 | case BFD_RELOC_MICROMIPS_LO16: |
7461 | case BFD_RELOC_MIPS16_LO16: | |
7462 | *result = operand & 0xffff; | |
7463 | return TRUE; | |
7464 | ||
7465 | case BFD_RELOC_UNUSED: | |
7466 | *result = operand; | |
7467 | return TRUE; | |
7468 | ||
7469 | default: | |
7470 | return FALSE; | |
7471 | } | |
7472 | } | |
7473 | ||
71400594 RS |
7474 | /* Output an instruction. IP is the instruction information. |
7475 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
7476 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
7477 | a macro expansion. */ | |
71400594 RS |
7478 | |
7479 | static void | |
7480 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 7481 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 7482 | { |
14fe068b | 7483 | unsigned long prev_pinfo2, pinfo; |
71400594 | 7484 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 7485 | enum append_method method; |
2309ddf2 | 7486 | bfd_boolean relax32; |
2b0c8b40 | 7487 | int branch_disp; |
71400594 | 7488 | |
2309ddf2 | 7489 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
7490 | fix_loongson2f (ip); |
7491 | ||
6f2117ba PH |
7492 | ip->target[0] = '\0'; |
7493 | if (offset_expr.X_op == O_symbol) | |
7494 | strncpy (ip->target, S_GET_NAME (offset_expr.X_add_symbol), 15); | |
7495 | ip->label[0] = '\0'; | |
7496 | if (seg_info (now_seg)->label_list) | |
7497 | strncpy (ip->label, S_GET_NAME (seg_info (now_seg)->label_list->label), 15); | |
7498 | if (mips_fix_loongson3_llsc && !HAVE_CODE_COMPRESSION) | |
7499 | fix_loongson3_llsc (ip); | |
7500 | ||
738f4d98 | 7501 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 7502 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 7503 | |
df58fc94 | 7504 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 7505 | pinfo = ip->insn_mo->pinfo; |
df58fc94 | 7506 | |
7bd374a4 MR |
7507 | /* Don't raise alarm about `nods' frags as they'll fill in the right |
7508 | kind of nop in relaxation if required. */ | |
df58fc94 RS |
7509 | if (mips_opts.micromips |
7510 | && !expansionp | |
7bd374a4 MR |
7511 | && !(history[0].frag |
7512 | && history[0].frag->fr_type == rs_machine_dependent | |
7513 | && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) | |
7514 | && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) | |
df58fc94 RS |
7515 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 |
7516 | && micromips_insn_length (ip->insn_mo) != 2) | |
7517 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
7518 | && micromips_insn_length (ip->insn_mo) != 4))) | |
1661c76c | 7519 | as_warn (_("wrong size instruction in a %u-bit branch delay slot"), |
df58fc94 | 7520 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); |
71400594 | 7521 | |
15be625d CM |
7522 | if (address_expr == NULL) |
7523 | ip->complete_p = 1; | |
b886a2ab RS |
7524 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
7525 | && reloc_type[1] == BFD_RELOC_UNUSED | |
7526 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
7527 | && address_expr->X_op == O_constant) |
7528 | { | |
15be625d CM |
7529 | switch (*reloc_type) |
7530 | { | |
15be625d | 7531 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
7532 | { |
7533 | int shift; | |
7534 | ||
17c6c9d9 MR |
7535 | /* Shift is 2, unusually, for microMIPS JALX. */ |
7536 | shift = (mips_opts.micromips | |
7537 | && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2; | |
df58fc94 RS |
7538 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) |
7539 | as_bad (_("jump to misaligned address (0x%lx)"), | |
7540 | (unsigned long) address_expr->X_add_number); | |
7541 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7542 | & 0x3ffffff); | |
335574df | 7543 | ip->complete_p = 1; |
df58fc94 | 7544 | } |
15be625d CM |
7545 | break; |
7546 | ||
7547 | case BFD_RELOC_MIPS16_JMP: | |
7548 | if ((address_expr->X_add_number & 3) != 0) | |
7549 | as_bad (_("jump to misaligned address (0x%lx)"), | |
7550 | (unsigned long) address_expr->X_add_number); | |
7551 | ip->insn_opcode |= | |
7552 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
7553 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
7554 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 7555 | ip->complete_p = 1; |
15be625d CM |
7556 | break; |
7557 | ||
7558 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
7559 | { |
7560 | int shift; | |
7561 | ||
7562 | shift = mips_opts.micromips ? 1 : 2; | |
7563 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7564 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7565 | (unsigned long) address_expr->X_add_number); | |
7566 | if (!mips_relax_branch) | |
7567 | { | |
7568 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
7569 | & ~((1 << (shift + 16)) - 1)) | |
7570 | as_bad (_("branch address range overflow (0x%lx)"), | |
7571 | (unsigned long) address_expr->X_add_number); | |
7572 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7573 | & 0xffff); | |
7574 | } | |
df58fc94 | 7575 | } |
15be625d CM |
7576 | break; |
7577 | ||
7361da2c AB |
7578 | case BFD_RELOC_MIPS_21_PCREL_S2: |
7579 | { | |
7580 | int shift; | |
7581 | ||
7582 | shift = 2; | |
7583 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7584 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7585 | (unsigned long) address_expr->X_add_number); | |
7586 | if ((address_expr->X_add_number + (1 << (shift + 20))) | |
7587 | & ~((1 << (shift + 21)) - 1)) | |
7588 | as_bad (_("branch address range overflow (0x%lx)"), | |
7589 | (unsigned long) address_expr->X_add_number); | |
7590 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7591 | & 0x1fffff); | |
7592 | } | |
7593 | break; | |
7594 | ||
7595 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
7596 | { | |
7597 | int shift; | |
7598 | ||
7599 | shift = 2; | |
7600 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7601 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7602 | (unsigned long) address_expr->X_add_number); | |
7603 | if ((address_expr->X_add_number + (1 << (shift + 25))) | |
7604 | & ~((1 << (shift + 26)) - 1)) | |
7605 | as_bad (_("branch address range overflow (0x%lx)"), | |
7606 | (unsigned long) address_expr->X_add_number); | |
7607 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7608 | & 0x3ffffff); | |
7609 | } | |
7610 | break; | |
7611 | ||
15be625d | 7612 | default: |
b886a2ab RS |
7613 | { |
7614 | offsetT value; | |
7615 | ||
7616 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
7617 | &value)) | |
7618 | { | |
7619 | ip->insn_opcode |= value & 0xffff; | |
7620 | ip->complete_p = 1; | |
7621 | } | |
7622 | } | |
7623 | break; | |
7624 | } | |
15be625d CM |
7625 | } |
7626 | ||
71400594 RS |
7627 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
7628 | { | |
7629 | /* There are a lot of optimizations we could do that we don't. | |
7630 | In particular, we do not, in general, reorder instructions. | |
7631 | If you use gcc with optimization, it will reorder | |
7632 | instructions and generally do much more optimization then we | |
7633 | do here; repeating all that work in the assembler would only | |
7634 | benefit hand written assembly code, and does not seem worth | |
7635 | it. */ | |
7636 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
7637 | ? nops_for_insn (0, history, NULL) |
7638 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 7639 | if (nops > 0) |
252b5132 RH |
7640 | { |
7641 | fragS *old_frag; | |
7642 | unsigned long old_frag_offset; | |
7643 | int i; | |
252b5132 RH |
7644 | |
7645 | old_frag = frag_now; | |
7646 | old_frag_offset = frag_now_fix (); | |
7647 | ||
7648 | for (i = 0; i < nops; i++) | |
14fe068b RS |
7649 | add_fixed_insn (NOP_INSN); |
7650 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
7651 | |
7652 | if (listing) | |
7653 | { | |
7654 | listing_prev_line (); | |
7655 | /* We may be at the start of a variant frag. In case we | |
7656 | are, make sure there is enough space for the frag | |
7657 | after the frags created by listing_prev_line. The | |
7658 | argument to frag_grow here must be at least as large | |
7659 | as the argument to all other calls to frag_grow in | |
7660 | this file. We don't have to worry about being in the | |
7661 | middle of a variant frag, because the variants insert | |
7662 | all needed nop instructions themselves. */ | |
7663 | frag_grow (40); | |
7664 | } | |
7665 | ||
462427c4 | 7666 | mips_move_text_labels (); |
252b5132 RH |
7667 | |
7668 | #ifndef NO_ECOFF_DEBUGGING | |
7669 | if (ECOFF_DEBUGGING) | |
7670 | ecoff_fix_loc (old_frag, old_frag_offset); | |
7671 | #endif | |
7672 | } | |
71400594 RS |
7673 | } |
7674 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
7675 | { | |
932d1a1b RS |
7676 | int nops; |
7677 | ||
7678 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
7679 | ignoring hazards generated by the first prev_nop_frag_since | |
7680 | instructions. */ | |
7681 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 7682 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 7683 | |
71400594 RS |
7684 | /* Enforce NOPS as a minimum. */ |
7685 | if (nops > prev_nop_frag_required) | |
7686 | prev_nop_frag_required = nops; | |
252b5132 | 7687 | |
71400594 RS |
7688 | if (prev_nop_frag_holds == prev_nop_frag_required) |
7689 | { | |
7690 | /* Settle for the current number of nops. Update the history | |
7691 | accordingly (for the benefit of any future .set reorder code). */ | |
7692 | prev_nop_frag = NULL; | |
7693 | insert_into_history (prev_nop_frag_since, | |
7694 | prev_nop_frag_holds, NOP_INSN); | |
7695 | } | |
7696 | else | |
7697 | { | |
7698 | /* Allow this instruction to replace one of the nops that was | |
7699 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 7700 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
7701 | prev_nop_frag_holds--; |
7702 | prev_nop_frag_since++; | |
252b5132 RH |
7703 | } |
7704 | } | |
7705 | ||
e407c74b | 7706 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 7707 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 7708 | |
e410add4 RS |
7709 | dwarf2_emit_insn (0); |
7710 | /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, | |
7711 | so "move" the instruction address accordingly. | |
7712 | ||
7713 | Also, it doesn't seem appropriate for the assembler to reorder .loc | |
7714 | entries. If this instruction is a branch that we are going to swap | |
7715 | with the previous instruction, the two instructions should be | |
7716 | treated as a unit, and the debug information for both instructions | |
7717 | should refer to the start of the branch sequence. Using the | |
7718 | current position is certainly wrong when swapping a 32-bit branch | |
7719 | and a 16-bit delay slot, since the current position would then be | |
7720 | in the middle of a branch. */ | |
7721 | dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); | |
58e2ea4d | 7722 | |
df58fc94 RS |
7723 | relax32 = (mips_relax_branch |
7724 | /* Don't try branch relaxation within .set nomacro, or within | |
7725 | .set noat if we use $at for PIC computations. If it turns | |
7726 | out that the branch was out-of-range, we'll get an error. */ | |
7727 | && !mips_opts.warn_about_macros | |
7728 | && (mips_opts.at || mips_pic == NO_PIC) | |
3bf0dbfb MR |
7729 | /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F |
7730 | as they have no complementing branches. */ | |
7731 | && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); | |
df58fc94 RS |
7732 | |
7733 | if (!HAVE_CODE_COMPRESSION | |
7734 | && address_expr | |
7735 | && relax32 | |
0b25d3e6 | 7736 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 7737 | && delayed_branch_p (ip)) |
4a6a3df4 | 7738 | { |
895921c9 | 7739 | relaxed_branch = TRUE; |
1e915849 RS |
7740 | add_relaxed_insn (ip, (relaxed_branch_length |
7741 | (NULL, NULL, | |
11625dd8 RS |
7742 | uncond_branch_p (ip) ? -1 |
7743 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
7744 | : 0)), 4, |
7745 | RELAX_BRANCH_ENCODE | |
ce8ad872 | 7746 | (AT, mips_pic != NO_PIC, |
11625dd8 RS |
7747 | uncond_branch_p (ip), |
7748 | branch_likely_p (ip), | |
1e915849 RS |
7749 | pinfo & INSN_WRITE_GPR_31, |
7750 | 0), | |
7751 | address_expr->X_add_symbol, | |
7752 | address_expr->X_add_number); | |
4a6a3df4 AO |
7753 | *reloc_type = BFD_RELOC_UNUSED; |
7754 | } | |
df58fc94 RS |
7755 | else if (mips_opts.micromips |
7756 | && address_expr | |
7757 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
7758 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
7759 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
7760 | /* Don't try branch relaxation when users specify | |
7761 | 16-bit/32-bit instructions. */ | |
7762 | && !forced_insn_length) | |
df58fc94 | 7763 | { |
7bd374a4 MR |
7764 | bfd_boolean relax16 = (method != APPEND_ADD_COMPACT |
7765 | && *reloc_type > BFD_RELOC_UNUSED); | |
df58fc94 | 7766 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; |
11625dd8 | 7767 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
7bd374a4 MR |
7768 | int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT; |
7769 | int nods = method == APPEND_ADD_WITH_NOP; | |
df58fc94 | 7770 | int al = pinfo & INSN_WRITE_GPR_31; |
7bd374a4 | 7771 | int length32 = nods ? 8 : 4; |
df58fc94 RS |
7772 | |
7773 | gas_assert (address_expr != NULL); | |
7774 | gas_assert (!mips_relax.sequence); | |
7775 | ||
2b0c8b40 | 7776 | relaxed_branch = TRUE; |
7bd374a4 MR |
7777 | if (nods) |
7778 | method = APPEND_ADD; | |
7779 | if (relax32) | |
7780 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); | |
7781 | add_relaxed_insn (ip, length32, relax16 ? 2 : 4, | |
8484fb75 | 7782 | RELAX_MICROMIPS_ENCODE (type, AT, mips_opts.insn32, |
ce8ad872 | 7783 | mips_pic != NO_PIC, |
7bd374a4 | 7784 | uncond, compact, al, nods, |
40209cad | 7785 | relax32, 0, 0), |
df58fc94 RS |
7786 | address_expr->X_add_symbol, |
7787 | address_expr->X_add_number); | |
7788 | *reloc_type = BFD_RELOC_UNUSED; | |
7789 | } | |
7790 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 | 7791 | { |
7fd53920 MR |
7792 | bfd_boolean require_unextended; |
7793 | bfd_boolean require_extended; | |
88a7ef16 MR |
7794 | symbolS *symbol; |
7795 | offsetT offset; | |
7796 | ||
7fd53920 MR |
7797 | if (forced_insn_length != 0) |
7798 | { | |
7799 | require_unextended = forced_insn_length == 2; | |
7800 | require_extended = forced_insn_length == 4; | |
7801 | } | |
7802 | else | |
7803 | { | |
7804 | require_unextended = (mips_opts.noautoextend | |
7805 | && !mips_opcode_32bit_p (ip->insn_mo)); | |
7806 | require_extended = 0; | |
7807 | } | |
7808 | ||
252b5132 | 7809 | /* We need to set up a variant frag. */ |
df58fc94 | 7810 | gas_assert (address_expr != NULL); |
88a7ef16 MR |
7811 | /* Pass any `O_symbol' expression unchanged as an `expr_section' |
7812 | symbol created by `make_expr_symbol' may not get a necessary | |
7813 | external relocation produced. */ | |
7814 | if (address_expr->X_op == O_symbol) | |
7815 | { | |
7816 | symbol = address_expr->X_add_symbol; | |
7817 | offset = address_expr->X_add_number; | |
7818 | } | |
7819 | else | |
7820 | { | |
7821 | symbol = make_expr_symbol (address_expr); | |
82d808ed | 7822 | symbol_append (symbol, symbol_lastP, &symbol_rootP, &symbol_lastP); |
88a7ef16 MR |
7823 | offset = 0; |
7824 | } | |
8507b6e7 | 7825 | add_relaxed_insn (ip, 12, 0, |
1e915849 RS |
7826 | RELAX_MIPS16_ENCODE |
7827 | (*reloc_type - BFD_RELOC_UNUSED, | |
25499ac7 | 7828 | mips_opts.ase & ASE_MIPS16E2, |
8507b6e7 MR |
7829 | mips_pic != NO_PIC, |
7830 | HAVE_32BIT_SYMBOLS, | |
7831 | mips_opts.warn_about_macros, | |
7fd53920 | 7832 | require_unextended, require_extended, |
11625dd8 | 7833 | delayed_branch_p (&history[0]), |
1e915849 | 7834 | history[0].mips16_absolute_jump_p), |
88a7ef16 | 7835 | symbol, offset); |
252b5132 | 7836 | } |
5c04167a | 7837 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 7838 | { |
11625dd8 | 7839 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
7840 | /* Make sure there is enough room to swap this instruction with |
7841 | a following jump instruction. */ | |
7842 | frag_grow (6); | |
1e915849 | 7843 | add_fixed_insn (ip); |
252b5132 RH |
7844 | } |
7845 | else | |
7846 | { | |
7847 | if (mips_opts.mips16 | |
7848 | && mips_opts.noreorder | |
11625dd8 | 7849 | && delayed_branch_p (&history[0])) |
252b5132 RH |
7850 | as_warn (_("extended instruction in delay slot")); |
7851 | ||
4d7206a2 RS |
7852 | if (mips_relax.sequence) |
7853 | { | |
7854 | /* If we've reached the end of this frag, turn it into a variant | |
7855 | frag and record the information for the instructions we've | |
7856 | written so far. */ | |
7857 | if (frag_room () < 4) | |
7858 | relax_close_frag (); | |
df58fc94 | 7859 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
7860 | } |
7861 | ||
584892a6 | 7862 | if (mips_relax.sequence != 2) |
df58fc94 RS |
7863 | { |
7864 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
7865 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
7866 | mips_macro_warning.sizes[0] += insn_length (ip); | |
7867 | mips_macro_warning.insns[0]++; | |
7868 | } | |
584892a6 | 7869 | if (mips_relax.sequence != 1) |
df58fc94 RS |
7870 | { |
7871 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
7872 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
7873 | mips_macro_warning.sizes[1] += insn_length (ip); | |
7874 | mips_macro_warning.insns[1]++; | |
7875 | } | |
584892a6 | 7876 | |
1e915849 RS |
7877 | if (mips_opts.mips16) |
7878 | { | |
7879 | ip->fixed_p = 1; | |
7880 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
7881 | } | |
7882 | add_fixed_insn (ip); | |
252b5132 RH |
7883 | } |
7884 | ||
9fe77896 | 7885 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 7886 | { |
df58fc94 | 7887 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 7888 | reloc_howto_type *howto0; |
9fe77896 RS |
7889 | reloc_howto_type *howto; |
7890 | int i; | |
34ce925e | 7891 | |
df58fc94 RS |
7892 | /* Perform any necessary conversion to microMIPS relocations |
7893 | and find out how many relocations there actually are. */ | |
7894 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
7895 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
7896 | ||
9fe77896 RS |
7897 | /* In a compound relocation, it is the final (outermost) |
7898 | operator that determines the relocated field. */ | |
2309ddf2 | 7899 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
e8044f35 RS |
7900 | if (!howto) |
7901 | abort (); | |
2309ddf2 MR |
7902 | |
7903 | if (i > 1) | |
7904 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
7905 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
7906 | bfd_get_reloc_size (howto), | |
7907 | address_expr, | |
2309ddf2 MR |
7908 | howto0 && howto0->pc_relative, |
7909 | final_type[0]); | |
ce8ad872 MR |
7910 | /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */ |
7911 | ip->fixp[0]->fx_tcbit2 = mips_pic == NO_PIC; | |
9fe77896 RS |
7912 | |
7913 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 7914 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
7915 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
7916 | ||
7917 | /* These relocations can have an addend that won't fit in | |
7918 | 4 octets for 64bit assembly. */ | |
bad1aba3 | 7919 | if (GPR_SIZE == 64 |
9fe77896 RS |
7920 | && ! howto->partial_inplace |
7921 | && (reloc_type[0] == BFD_RELOC_16 | |
7922 | || reloc_type[0] == BFD_RELOC_32 | |
7923 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
7924 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
7925 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
7926 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
7927 | || reloc_type[0] == BFD_RELOC_64 | |
7928 | || reloc_type[0] == BFD_RELOC_CTOR | |
7929 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
7930 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
7931 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
7932 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
7933 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
7934 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
7935 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
7936 | || hi16_reloc_p (reloc_type[0]) | |
7937 | || lo16_reloc_p (reloc_type[0]))) | |
7938 | ip->fixp[0]->fx_no_overflow = 1; | |
7939 | ||
ddaf2c41 MR |
7940 | /* These relocations can have an addend that won't fit in 2 octets. */ |
7941 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
7942 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
7943 | ip->fixp[0]->fx_no_overflow = 1; | |
7944 | ||
9fe77896 RS |
7945 | if (mips_relax.sequence) |
7946 | { | |
7947 | if (mips_relax.first_fixup == 0) | |
7948 | mips_relax.first_fixup = ip->fixp[0]; | |
7949 | } | |
7950 | else if (reloc_needs_lo_p (*reloc_type)) | |
7951 | { | |
7952 | struct mips_hi_fixup *hi_fixup; | |
7953 | ||
7954 | /* Reuse the last entry if it already has a matching %lo. */ | |
7955 | hi_fixup = mips_hi_fixup_list; | |
7956 | if (hi_fixup == 0 | |
7957 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 7958 | { |
325801bd | 7959 | hi_fixup = XNEW (struct mips_hi_fixup); |
9fe77896 RS |
7960 | hi_fixup->next = mips_hi_fixup_list; |
7961 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 7962 | } |
9fe77896 RS |
7963 | hi_fixup->fixp = ip->fixp[0]; |
7964 | hi_fixup->seg = now_seg; | |
7965 | } | |
252b5132 | 7966 | |
9fe77896 RS |
7967 | /* Add fixups for the second and third relocations, if given. |
7968 | Note that the ABI allows the second relocation to be | |
7969 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
7970 | moment we only use RSS_UNDEF, but we could add support | |
7971 | for the others if it ever becomes necessary. */ | |
7972 | for (i = 1; i < 3; i++) | |
7973 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
7974 | { | |
7975 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
7976 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 7977 | FALSE, final_type[i]); |
f6688943 | 7978 | |
9fe77896 RS |
7979 | /* Use fx_tcbit to mark compound relocs. */ |
7980 | ip->fixp[0]->fx_tcbit = 1; | |
7981 | ip->fixp[i]->fx_tcbit = 1; | |
7982 | } | |
252b5132 | 7983 | } |
252b5132 RH |
7984 | |
7985 | /* Update the register mask information. */ | |
4c260379 RS |
7986 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
7987 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 7988 | |
a4e06468 | 7989 | switch (method) |
252b5132 | 7990 | { |
a4e06468 RS |
7991 | case APPEND_ADD: |
7992 | insert_into_history (0, 1, ip); | |
7993 | break; | |
7994 | ||
7995 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
7996 | { |
7997 | struct mips_cl_insn *nop; | |
7998 | ||
7999 | insert_into_history (0, 1, ip); | |
8000 | nop = get_delay_slot_nop (ip); | |
8001 | add_fixed_insn (nop); | |
8002 | insert_into_history (0, 1, nop); | |
8003 | if (mips_relax.sequence) | |
8004 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
8005 | } | |
a4e06468 RS |
8006 | break; |
8007 | ||
8008 | case APPEND_ADD_COMPACT: | |
8009 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
7bd374a4 MR |
8010 | if (mips_opts.mips16) |
8011 | { | |
8012 | ip->insn_opcode |= 0x0080; | |
8013 | find_altered_mips16_opcode (ip); | |
8014 | } | |
8015 | /* Convert microMIPS instructions. */ | |
8016 | else if (mips_opts.micromips) | |
8017 | { | |
8018 | /* jr16->jrc */ | |
8019 | if ((ip->insn_opcode & 0xffe0) == 0x4580) | |
8020 | ip->insn_opcode |= 0x0020; | |
8021 | /* b16->bc */ | |
8022 | else if ((ip->insn_opcode & 0xfc00) == 0xcc00) | |
8023 | ip->insn_opcode = 0x40e00000; | |
8024 | /* beqz16->beqzc, bnez16->bnezc */ | |
8025 | else if ((ip->insn_opcode & 0xdc00) == 0x8c00) | |
8026 | { | |
8027 | unsigned long regno; | |
8028 | ||
8029 | regno = ip->insn_opcode >> MICROMIPSOP_SH_MD; | |
8030 | regno &= MICROMIPSOP_MASK_MD; | |
8031 | regno = micromips_to_32_reg_d_map[regno]; | |
8032 | ip->insn_opcode = (((ip->insn_opcode << 9) & 0x00400000) | |
8033 | | (regno << MICROMIPSOP_SH_RS) | |
8034 | | 0x40a00000) ^ 0x00400000; | |
8035 | } | |
8036 | /* beqz->beqzc, bnez->bnezc */ | |
8037 | else if ((ip->insn_opcode & 0xdfe00000) == 0x94000000) | |
8038 | ip->insn_opcode = ((ip->insn_opcode & 0x001f0000) | |
8039 | | ((ip->insn_opcode >> 7) & 0x00400000) | |
8040 | | 0x40a00000) ^ 0x00400000; | |
8041 | /* beq $0->beqzc, bne $0->bnezc */ | |
8042 | else if ((ip->insn_opcode & 0xdc1f0000) == 0x94000000) | |
8043 | ip->insn_opcode = (((ip->insn_opcode >> | |
8044 | (MICROMIPSOP_SH_RT - MICROMIPSOP_SH_RS)) | |
8045 | & (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)) | |
8046 | | ((ip->insn_opcode >> 7) & 0x00400000) | |
8047 | | 0x40a00000) ^ 0x00400000; | |
8048 | else | |
8049 | abort (); | |
8050 | find_altered_micromips_opcode (ip); | |
8051 | } | |
8052 | else | |
8053 | abort (); | |
a4e06468 RS |
8054 | install_insn (ip); |
8055 | insert_into_history (0, 1, ip); | |
8056 | break; | |
8057 | ||
8058 | case APPEND_SWAP: | |
8059 | { | |
8060 | struct mips_cl_insn delay = history[0]; | |
99e7978b MF |
8061 | |
8062 | if (relaxed_branch || delay.frag != ip->frag) | |
a4e06468 RS |
8063 | { |
8064 | /* Add the delay slot instruction to the end of the | |
8065 | current frag and shrink the fixed part of the | |
8066 | original frag. If the branch occupies the tail of | |
8067 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 8068 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 8069 | if (delay.frag == ip->frag) |
2b0c8b40 | 8070 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
8071 | add_fixed_insn (&delay); |
8072 | } | |
8073 | else | |
8074 | { | |
5e35670b MR |
8075 | /* If this is not a relaxed branch and we are in the |
8076 | same frag, then just swap the instructions. */ | |
8077 | move_insn (ip, delay.frag, delay.where); | |
8078 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
a4e06468 RS |
8079 | } |
8080 | history[0] = *ip; | |
8081 | delay.fixed_p = 1; | |
8082 | insert_into_history (0, 1, &delay); | |
8083 | } | |
8084 | break; | |
252b5132 RH |
8085 | } |
8086 | ||
13408f1e | 8087 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
8088 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
8089 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
8090 | { |
8091 | unsigned int i; | |
8092 | ||
79850f26 | 8093 | mips_no_prev_insn (); |
13408f1e | 8094 | |
e407c74b | 8095 | for (i = 0; i < ARRAY_SIZE (history); i++) |
79850f26 | 8096 | history[i].cleared_p = 1; |
e407c74b NC |
8097 | } |
8098 | ||
df58fc94 RS |
8099 | /* We need to emit a label at the end of branch-likely macros. */ |
8100 | if (emit_branch_likely_macro) | |
8101 | { | |
8102 | emit_branch_likely_macro = FALSE; | |
8103 | micromips_add_label (); | |
8104 | } | |
8105 | ||
252b5132 RH |
8106 | /* We just output an insn, so the next one doesn't have a label. */ |
8107 | mips_clear_insn_labels (); | |
252b5132 RH |
8108 | } |
8109 | ||
e407c74b NC |
8110 | /* Forget that there was any previous instruction or label. |
8111 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
8112 | |
8113 | static void | |
7d10b47d | 8114 | mips_no_prev_insn (void) |
252b5132 | 8115 | { |
7d10b47d RS |
8116 | prev_nop_frag = NULL; |
8117 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
8118 | mips_clear_insn_labels (); |
8119 | } | |
8120 | ||
7d10b47d RS |
8121 | /* This function must be called before we emit something other than |
8122 | instructions. It is like mips_no_prev_insn except that it inserts | |
8123 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 8124 | |
7d10b47d RS |
8125 | void |
8126 | mips_emit_delays (void) | |
252b5132 RH |
8127 | { |
8128 | if (! mips_opts.noreorder) | |
8129 | { | |
932d1a1b | 8130 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
8131 | if (nops > 0) |
8132 | { | |
7d10b47d RS |
8133 | while (nops-- > 0) |
8134 | add_fixed_insn (NOP_INSN); | |
462427c4 | 8135 | mips_move_text_labels (); |
7d10b47d RS |
8136 | } |
8137 | } | |
8138 | mips_no_prev_insn (); | |
8139 | } | |
8140 | ||
8141 | /* Start a (possibly nested) noreorder block. */ | |
8142 | ||
8143 | static void | |
8144 | start_noreorder (void) | |
8145 | { | |
8146 | if (mips_opts.noreorder == 0) | |
8147 | { | |
8148 | unsigned int i; | |
8149 | int nops; | |
8150 | ||
8151 | /* None of the instructions before the .set noreorder can be moved. */ | |
8152 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
8153 | history[i].fixed_p = 1; | |
8154 | ||
8155 | /* Insert any nops that might be needed between the .set noreorder | |
8156 | block and the previous instructions. We will later remove any | |
8157 | nops that turn out not to be needed. */ | |
932d1a1b | 8158 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
8159 | if (nops > 0) |
8160 | { | |
8161 | if (mips_optimize != 0) | |
252b5132 RH |
8162 | { |
8163 | /* Record the frag which holds the nop instructions, so | |
8164 | that we can remove them if we don't need them. */ | |
df58fc94 | 8165 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
8166 | prev_nop_frag = frag_now; |
8167 | prev_nop_frag_holds = nops; | |
8168 | prev_nop_frag_required = 0; | |
8169 | prev_nop_frag_since = 0; | |
8170 | } | |
8171 | ||
8172 | for (; nops > 0; --nops) | |
1e915849 | 8173 | add_fixed_insn (NOP_INSN); |
252b5132 | 8174 | |
7d10b47d RS |
8175 | /* Move on to a new frag, so that it is safe to simply |
8176 | decrease the size of prev_nop_frag. */ | |
8177 | frag_wane (frag_now); | |
8178 | frag_new (0); | |
462427c4 | 8179 | mips_move_text_labels (); |
252b5132 | 8180 | } |
df58fc94 | 8181 | mips_mark_labels (); |
7d10b47d | 8182 | mips_clear_insn_labels (); |
252b5132 | 8183 | } |
7d10b47d RS |
8184 | mips_opts.noreorder++; |
8185 | mips_any_noreorder = 1; | |
8186 | } | |
252b5132 | 8187 | |
7d10b47d | 8188 | /* End a nested noreorder block. */ |
252b5132 | 8189 | |
7d10b47d RS |
8190 | static void |
8191 | end_noreorder (void) | |
8192 | { | |
8193 | mips_opts.noreorder--; | |
8194 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
8195 | { | |
8196 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
8197 | handling nop insertion the .set reorder way. */ | |
8198 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 8199 | * NOP_INSN_SIZE); |
7d10b47d RS |
8200 | insert_into_history (prev_nop_frag_since, |
8201 | prev_nop_frag_required, NOP_INSN); | |
8202 | prev_nop_frag = NULL; | |
8203 | } | |
252b5132 RH |
8204 | } |
8205 | ||
97d87491 RS |
8206 | /* Sign-extend 32-bit mode constants that have bit 31 set and all |
8207 | higher bits unset. */ | |
8208 | ||
8209 | static void | |
8210 | normalize_constant_expr (expressionS *ex) | |
8211 | { | |
8212 | if (ex->X_op == O_constant | |
8213 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
8214 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
8215 | - 0x80000000); | |
8216 | } | |
8217 | ||
8218 | /* Sign-extend 32-bit mode address offsets that have bit 31 set and | |
8219 | all higher bits unset. */ | |
8220 | ||
8221 | static void | |
8222 | normalize_address_expr (expressionS *ex) | |
8223 | { | |
8224 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
8225 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
8226 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
8227 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
8228 | - 0x80000000); | |
8229 | } | |
8230 | ||
8231 | /* Try to match TOKENS against OPCODE, storing the result in INSN. | |
8232 | Return true if the match was successful. | |
8233 | ||
8234 | OPCODE_EXTRA is a value that should be ORed into the opcode | |
8235 | (used for VU0 channel suffixes, etc.). MORE_ALTS is true if | |
8236 | there are more alternatives after OPCODE and SOFT_MATCH is | |
8237 | as for mips_arg_info. */ | |
8238 | ||
8239 | static bfd_boolean | |
8240 | match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
8241 | struct mips_operand_token *tokens, unsigned int opcode_extra, | |
60f20e8b | 8242 | bfd_boolean lax_match, bfd_boolean complete_p) |
97d87491 RS |
8243 | { |
8244 | const char *args; | |
8245 | struct mips_arg_info arg; | |
8246 | const struct mips_operand *operand; | |
8247 | char c; | |
8248 | ||
8249 | imm_expr.X_op = O_absent; | |
97d87491 RS |
8250 | offset_expr.X_op = O_absent; |
8251 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
8252 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8253 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
8254 | ||
8255 | create_insn (insn, opcode); | |
60f20e8b RS |
8256 | /* When no opcode suffix is specified, assume ".xyzw". */ |
8257 | if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0) | |
8258 | insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb; | |
8259 | else | |
8260 | insn->insn_opcode |= opcode_extra; | |
97d87491 RS |
8261 | memset (&arg, 0, sizeof (arg)); |
8262 | arg.insn = insn; | |
8263 | arg.token = tokens; | |
8264 | arg.argnum = 1; | |
8265 | arg.last_regno = ILLEGAL_REG; | |
8266 | arg.dest_regno = ILLEGAL_REG; | |
60f20e8b | 8267 | arg.lax_match = lax_match; |
97d87491 RS |
8268 | for (args = opcode->args;; ++args) |
8269 | { | |
8270 | if (arg.token->type == OT_END) | |
8271 | { | |
8272 | /* Handle unary instructions in which only one operand is given. | |
8273 | The source is then the same as the destination. */ | |
8274 | if (arg.opnum == 1 && *args == ',') | |
8275 | { | |
8276 | operand = (mips_opts.micromips | |
8277 | ? decode_micromips_operand (args + 1) | |
8278 | : decode_mips_operand (args + 1)); | |
8279 | if (operand && mips_optional_operand_p (operand)) | |
8280 | { | |
8281 | arg.token = tokens; | |
8282 | arg.argnum = 1; | |
8283 | continue; | |
8284 | } | |
8285 | } | |
8286 | ||
8287 | /* Treat elided base registers as $0. */ | |
8288 | if (strcmp (args, "(b)") == 0) | |
8289 | args += 3; | |
8290 | ||
8291 | if (args[0] == '+') | |
8292 | switch (args[1]) | |
8293 | { | |
8294 | case 'K': | |
8295 | case 'N': | |
8296 | /* The register suffix is optional. */ | |
8297 | args += 2; | |
8298 | break; | |
8299 | } | |
8300 | ||
8301 | /* Fail the match if there were too few operands. */ | |
8302 | if (*args) | |
8303 | return FALSE; | |
8304 | ||
8305 | /* Successful match. */ | |
60f20e8b RS |
8306 | if (!complete_p) |
8307 | return TRUE; | |
e3de51ce | 8308 | clear_insn_error (); |
97d87491 RS |
8309 | if (arg.dest_regno == arg.last_regno |
8310 | && strncmp (insn->insn_mo->name, "jalr", 4) == 0) | |
8311 | { | |
8312 | if (arg.opnum == 2) | |
e3de51ce | 8313 | set_insn_error |
1661c76c | 8314 | (0, _("source and destination must be different")); |
97d87491 | 8315 | else if (arg.last_regno == 31) |
e3de51ce | 8316 | set_insn_error |
1661c76c | 8317 | (0, _("a destination register must be supplied")); |
97d87491 | 8318 | } |
173d3447 CF |
8319 | else if (arg.last_regno == 31 |
8320 | && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0 | |
8321 | || strncmp (insn->insn_mo->name, "bgezal", 6) == 0)) | |
8322 | set_insn_error (0, _("the source register must not be $31")); | |
97d87491 RS |
8323 | check_completed_insn (&arg); |
8324 | return TRUE; | |
8325 | } | |
8326 | ||
8327 | /* Fail the match if the line has too many operands. */ | |
8328 | if (*args == 0) | |
8329 | return FALSE; | |
8330 | ||
8331 | /* Handle characters that need to match exactly. */ | |
8332 | if (*args == '(' || *args == ')' || *args == ',') | |
8333 | { | |
8334 | if (match_char (&arg, *args)) | |
8335 | continue; | |
8336 | return FALSE; | |
8337 | } | |
8338 | if (*args == '#') | |
8339 | { | |
8340 | ++args; | |
8341 | if (arg.token->type == OT_DOUBLE_CHAR | |
8342 | && arg.token->u.ch == *args) | |
8343 | { | |
8344 | ++arg.token; | |
8345 | continue; | |
8346 | } | |
8347 | return FALSE; | |
8348 | } | |
8349 | ||
8350 | /* Handle special macro operands. Work out the properties of | |
8351 | other operands. */ | |
8352 | arg.opnum += 1; | |
97d87491 RS |
8353 | switch (*args) |
8354 | { | |
7361da2c AB |
8355 | case '-': |
8356 | switch (args[1]) | |
8357 | { | |
8358 | case 'A': | |
8359 | *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2; | |
8360 | break; | |
8361 | ||
8362 | case 'B': | |
8363 | *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3; | |
8364 | break; | |
8365 | } | |
8366 | break; | |
8367 | ||
97d87491 RS |
8368 | case '+': |
8369 | switch (args[1]) | |
8370 | { | |
97d87491 RS |
8371 | case 'i': |
8372 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
8373 | break; | |
7361da2c AB |
8374 | |
8375 | case '\'': | |
8376 | *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2; | |
8377 | break; | |
8378 | ||
8379 | case '\"': | |
8380 | *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2; | |
8381 | break; | |
97d87491 RS |
8382 | } |
8383 | break; | |
8384 | ||
97d87491 | 8385 | case 'I': |
1a00e612 RS |
8386 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
8387 | return FALSE; | |
8388 | imm_expr.X_op = O_constant; | |
bad1aba3 | 8389 | if (GPR_SIZE == 32) |
97d87491 RS |
8390 | normalize_constant_expr (&imm_expr); |
8391 | continue; | |
8392 | ||
8393 | case 'A': | |
8394 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
8395 | { | |
8396 | /* Assume that the offset has been elided and that what | |
8397 | we saw was a base register. The match will fail later | |
8398 | if that assumption turns out to be wrong. */ | |
8399 | offset_expr.X_op = O_constant; | |
8400 | offset_expr.X_add_number = 0; | |
8401 | } | |
97d87491 | 8402 | else |
1a00e612 RS |
8403 | { |
8404 | if (!match_expression (&arg, &offset_expr, offset_reloc)) | |
8405 | return FALSE; | |
8406 | normalize_address_expr (&offset_expr); | |
8407 | } | |
97d87491 RS |
8408 | continue; |
8409 | ||
8410 | case 'F': | |
8411 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8412 | 8, TRUE)) | |
1a00e612 | 8413 | return FALSE; |
97d87491 RS |
8414 | continue; |
8415 | ||
8416 | case 'L': | |
8417 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8418 | 8, FALSE)) | |
1a00e612 | 8419 | return FALSE; |
97d87491 RS |
8420 | continue; |
8421 | ||
8422 | case 'f': | |
8423 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8424 | 4, TRUE)) | |
1a00e612 | 8425 | return FALSE; |
97d87491 RS |
8426 | continue; |
8427 | ||
8428 | case 'l': | |
8429 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8430 | 4, FALSE)) | |
1a00e612 | 8431 | return FALSE; |
97d87491 RS |
8432 | continue; |
8433 | ||
97d87491 RS |
8434 | case 'p': |
8435 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
8436 | break; | |
8437 | ||
8438 | case 'a': | |
8439 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
8440 | break; | |
8441 | ||
8442 | case 'm': | |
8443 | gas_assert (mips_opts.micromips); | |
8444 | c = args[1]; | |
8445 | switch (c) | |
8446 | { | |
8447 | case 'D': | |
8448 | case 'E': | |
8449 | if (!forced_insn_length) | |
8450 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
8451 | else if (c == 'D') | |
8452 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
8453 | else | |
8454 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
8455 | break; | |
8456 | } | |
8457 | break; | |
8458 | } | |
8459 | ||
8460 | operand = (mips_opts.micromips | |
8461 | ? decode_micromips_operand (args) | |
8462 | : decode_mips_operand (args)); | |
8463 | if (!operand) | |
8464 | abort (); | |
8465 | ||
8466 | /* Skip prefixes. */ | |
7361da2c | 8467 | if (*args == '+' || *args == 'm' || *args == '-') |
97d87491 RS |
8468 | args++; |
8469 | ||
8470 | if (mips_optional_operand_p (operand) | |
8471 | && args[1] == ',' | |
8472 | && (arg.token[0].type != OT_REG | |
8473 | || arg.token[1].type == OT_END)) | |
8474 | { | |
8475 | /* Assume that the register has been elided and is the | |
8476 | same as the first operand. */ | |
8477 | arg.token = tokens; | |
8478 | arg.argnum = 1; | |
8479 | } | |
8480 | ||
8481 | if (!match_operand (&arg, operand)) | |
8482 | return FALSE; | |
8483 | } | |
8484 | } | |
8485 | ||
8486 | /* Like match_insn, but for MIPS16. */ | |
8487 | ||
8488 | static bfd_boolean | |
8489 | match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
1a00e612 | 8490 | struct mips_operand_token *tokens) |
97d87491 RS |
8491 | { |
8492 | const char *args; | |
8493 | const struct mips_operand *operand; | |
8494 | const struct mips_operand *ext_operand; | |
82d808ed | 8495 | bfd_boolean pcrel = FALSE; |
7fd53920 | 8496 | int required_insn_length; |
97d87491 RS |
8497 | struct mips_arg_info arg; |
8498 | int relax_char; | |
8499 | ||
7fd53920 MR |
8500 | if (forced_insn_length) |
8501 | required_insn_length = forced_insn_length; | |
8502 | else if (mips_opts.noautoextend && !mips_opcode_32bit_p (opcode)) | |
8503 | required_insn_length = 2; | |
8504 | else | |
8505 | required_insn_length = 0; | |
8506 | ||
97d87491 RS |
8507 | create_insn (insn, opcode); |
8508 | imm_expr.X_op = O_absent; | |
97d87491 RS |
8509 | offset_expr.X_op = O_absent; |
8510 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
8511 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8512 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
8513 | relax_char = 0; | |
8514 | ||
8515 | memset (&arg, 0, sizeof (arg)); | |
8516 | arg.insn = insn; | |
8517 | arg.token = tokens; | |
8518 | arg.argnum = 1; | |
8519 | arg.last_regno = ILLEGAL_REG; | |
8520 | arg.dest_regno = ILLEGAL_REG; | |
97d87491 RS |
8521 | relax_char = 0; |
8522 | for (args = opcode->args;; ++args) | |
8523 | { | |
8524 | int c; | |
8525 | ||
8526 | if (arg.token->type == OT_END) | |
8527 | { | |
8528 | offsetT value; | |
8529 | ||
8530 | /* Handle unary instructions in which only one operand is given. | |
8531 | The source is then the same as the destination. */ | |
8532 | if (arg.opnum == 1 && *args == ',') | |
8533 | { | |
8534 | operand = decode_mips16_operand (args[1], FALSE); | |
8535 | if (operand && mips_optional_operand_p (operand)) | |
8536 | { | |
8537 | arg.token = tokens; | |
8538 | arg.argnum = 1; | |
8539 | continue; | |
8540 | } | |
8541 | } | |
8542 | ||
8543 | /* Fail the match if there were too few operands. */ | |
8544 | if (*args) | |
8545 | return FALSE; | |
8546 | ||
8547 | /* Successful match. Stuff the immediate value in now, if | |
8548 | we can. */ | |
e3de51ce | 8549 | clear_insn_error (); |
97d87491 RS |
8550 | if (opcode->pinfo == INSN_MACRO) |
8551 | { | |
8552 | gas_assert (relax_char == 0 || relax_char == 'p'); | |
8553 | gas_assert (*offset_reloc == BFD_RELOC_UNUSED); | |
8554 | } | |
8555 | else if (relax_char | |
8556 | && offset_expr.X_op == O_constant | |
82d808ed | 8557 | && !pcrel |
97d87491 RS |
8558 | && calculate_reloc (*offset_reloc, |
8559 | offset_expr.X_add_number, | |
8560 | &value)) | |
8561 | { | |
8562 | mips16_immed (NULL, 0, relax_char, *offset_reloc, value, | |
7fd53920 | 8563 | required_insn_length, &insn->insn_opcode); |
97d87491 RS |
8564 | offset_expr.X_op = O_absent; |
8565 | *offset_reloc = BFD_RELOC_UNUSED; | |
8566 | } | |
8567 | else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED) | |
8568 | { | |
7fd53920 | 8569 | if (required_insn_length == 2) |
e3de51ce | 8570 | set_insn_error (0, _("invalid unextended operand value")); |
25499ac7 | 8571 | else if (!mips_opcode_32bit_p (opcode)) |
1da43acc MR |
8572 | { |
8573 | forced_insn_length = 4; | |
8574 | insn->insn_opcode |= MIPS16_EXTEND; | |
8575 | } | |
97d87491 RS |
8576 | } |
8577 | else if (relax_char) | |
8578 | *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char; | |
8579 | ||
8580 | check_completed_insn (&arg); | |
8581 | return TRUE; | |
8582 | } | |
8583 | ||
8584 | /* Fail the match if the line has too many operands. */ | |
8585 | if (*args == 0) | |
8586 | return FALSE; | |
8587 | ||
8588 | /* Handle characters that need to match exactly. */ | |
8589 | if (*args == '(' || *args == ')' || *args == ',') | |
8590 | { | |
8591 | if (match_char (&arg, *args)) | |
8592 | continue; | |
8593 | return FALSE; | |
8594 | } | |
8595 | ||
8596 | arg.opnum += 1; | |
8597 | c = *args; | |
8598 | switch (c) | |
8599 | { | |
8600 | case 'p': | |
8601 | case 'q': | |
8602 | case 'A': | |
8603 | case 'B': | |
8604 | case 'E': | |
25499ac7 MR |
8605 | case 'V': |
8606 | case 'u': | |
97d87491 RS |
8607 | relax_char = c; |
8608 | break; | |
8609 | ||
8610 | case 'I': | |
1a00e612 RS |
8611 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
8612 | return FALSE; | |
8613 | imm_expr.X_op = O_constant; | |
bad1aba3 | 8614 | if (GPR_SIZE == 32) |
97d87491 RS |
8615 | normalize_constant_expr (&imm_expr); |
8616 | continue; | |
8617 | ||
8618 | case 'a': | |
8619 | case 'i': | |
8620 | *offset_reloc = BFD_RELOC_MIPS16_JMP; | |
97d87491 RS |
8621 | break; |
8622 | } | |
8623 | ||
7fd53920 | 8624 | operand = decode_mips16_operand (c, mips_opcode_32bit_p (opcode)); |
97d87491 RS |
8625 | if (!operand) |
8626 | abort (); | |
8627 | ||
82d808ed MR |
8628 | if (operand->type == OP_PCREL) |
8629 | pcrel = TRUE; | |
8630 | else | |
97d87491 RS |
8631 | { |
8632 | ext_operand = decode_mips16_operand (c, TRUE); | |
8633 | if (operand != ext_operand) | |
8634 | { | |
8635 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
8636 | { | |
8637 | offset_expr.X_op = O_constant; | |
8638 | offset_expr.X_add_number = 0; | |
8639 | relax_char = c; | |
8640 | continue; | |
8641 | } | |
8642 | ||
1a7bf198 | 8643 | if (!match_expression (&arg, &offset_expr, offset_reloc)) |
97d87491 RS |
8644 | return FALSE; |
8645 | ||
8646 | /* '8' is used for SLTI(U) and has traditionally not | |
8647 | been allowed to take relocation operators. */ | |
8648 | if (offset_reloc[0] != BFD_RELOC_UNUSED | |
8649 | && (ext_operand->size != 16 || c == '8')) | |
e295202f MR |
8650 | { |
8651 | match_not_constant (&arg); | |
8652 | return FALSE; | |
8653 | } | |
97d87491 | 8654 | |
c96425c5 MR |
8655 | if (offset_expr.X_op == O_big) |
8656 | { | |
8657 | match_out_of_range (&arg); | |
8658 | return FALSE; | |
8659 | } | |
8660 | ||
97d87491 RS |
8661 | relax_char = c; |
8662 | continue; | |
8663 | } | |
8664 | } | |
8665 | ||
8666 | if (mips_optional_operand_p (operand) | |
8667 | && args[1] == ',' | |
8668 | && (arg.token[0].type != OT_REG | |
8669 | || arg.token[1].type == OT_END)) | |
8670 | { | |
8671 | /* Assume that the register has been elided and is the | |
8672 | same as the first operand. */ | |
8673 | arg.token = tokens; | |
8674 | arg.argnum = 1; | |
8675 | } | |
8676 | ||
8677 | if (!match_operand (&arg, operand)) | |
8678 | return FALSE; | |
8679 | } | |
8680 | } | |
8681 | ||
60f20e8b RS |
8682 | /* Record that the current instruction is invalid for the current ISA. */ |
8683 | ||
8684 | static void | |
8685 | match_invalid_for_isa (void) | |
8686 | { | |
8687 | set_insn_error_ss | |
1661c76c | 8688 | (0, _("opcode not supported on this processor: %s (%s)"), |
60f20e8b RS |
8689 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
8690 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8691 | } | |
8692 | ||
8693 | /* Try to match TOKENS against a series of opcode entries, starting at FIRST. | |
8694 | Return true if a definite match or failure was found, storing any match | |
8695 | in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode | |
8696 | (to handle things like VU0 suffixes). LAX_MATCH is true if we have already | |
8697 | tried and failed to match under normal conditions and now want to try a | |
8698 | more relaxed match. */ | |
8699 | ||
8700 | static bfd_boolean | |
8701 | match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
8702 | const struct mips_opcode *past, struct mips_operand_token *tokens, | |
8703 | int opcode_extra, bfd_boolean lax_match) | |
8704 | { | |
8705 | const struct mips_opcode *opcode; | |
8706 | const struct mips_opcode *invalid_delay_slot; | |
8707 | bfd_boolean seen_valid_for_isa, seen_valid_for_size; | |
8708 | ||
8709 | /* Search for a match, ignoring alternatives that don't satisfy the | |
8710 | current ISA or forced_length. */ | |
8711 | invalid_delay_slot = 0; | |
8712 | seen_valid_for_isa = FALSE; | |
8713 | seen_valid_for_size = FALSE; | |
8714 | opcode = first; | |
8715 | do | |
8716 | { | |
8717 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
8718 | if (is_opcode_valid (opcode)) | |
8719 | { | |
8720 | seen_valid_for_isa = TRUE; | |
8721 | if (is_size_valid (opcode)) | |
8722 | { | |
8723 | bfd_boolean delay_slot_ok; | |
8724 | ||
8725 | seen_valid_for_size = TRUE; | |
8726 | delay_slot_ok = is_delay_slot_valid (opcode); | |
8727 | if (match_insn (insn, opcode, tokens, opcode_extra, | |
8728 | lax_match, delay_slot_ok)) | |
8729 | { | |
8730 | if (!delay_slot_ok) | |
8731 | { | |
8732 | if (!invalid_delay_slot) | |
8733 | invalid_delay_slot = opcode; | |
8734 | } | |
8735 | else | |
8736 | return TRUE; | |
8737 | } | |
8738 | } | |
8739 | } | |
8740 | ++opcode; | |
8741 | } | |
8742 | while (opcode < past && strcmp (opcode->name, first->name) == 0); | |
8743 | ||
8744 | /* If the only matches we found had the wrong length for the delay slot, | |
8745 | pick the first such match. We'll issue an appropriate warning later. */ | |
8746 | if (invalid_delay_slot) | |
8747 | { | |
8748 | if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra, | |
8749 | lax_match, TRUE)) | |
8750 | return TRUE; | |
8751 | abort (); | |
8752 | } | |
8753 | ||
8754 | /* Handle the case where we didn't try to match an instruction because | |
8755 | all the alternatives were incompatible with the current ISA. */ | |
8756 | if (!seen_valid_for_isa) | |
8757 | { | |
8758 | match_invalid_for_isa (); | |
8759 | return TRUE; | |
8760 | } | |
8761 | ||
8762 | /* Handle the case where we didn't try to match an instruction because | |
8763 | all the alternatives were of the wrong size. */ | |
8764 | if (!seen_valid_for_size) | |
8765 | { | |
8766 | if (mips_opts.insn32) | |
1661c76c | 8767 | set_insn_error (0, _("opcode not supported in the `insn32' mode")); |
60f20e8b RS |
8768 | else |
8769 | set_insn_error_i | |
1661c76c | 8770 | (0, _("unrecognized %d-bit version of microMIPS opcode"), |
60f20e8b RS |
8771 | 8 * forced_insn_length); |
8772 | return TRUE; | |
8773 | } | |
8774 | ||
8775 | return FALSE; | |
8776 | } | |
8777 | ||
8778 | /* Like match_insns, but for MIPS16. */ | |
8779 | ||
8780 | static bfd_boolean | |
8781 | match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
8782 | struct mips_operand_token *tokens) | |
8783 | { | |
8784 | const struct mips_opcode *opcode; | |
8785 | bfd_boolean seen_valid_for_isa; | |
7fd53920 | 8786 | bfd_boolean seen_valid_for_size; |
60f20e8b RS |
8787 | |
8788 | /* Search for a match, ignoring alternatives that don't satisfy the | |
8789 | current ISA. There are no separate entries for extended forms so | |
8790 | we deal with forced_length later. */ | |
8791 | seen_valid_for_isa = FALSE; | |
7fd53920 | 8792 | seen_valid_for_size = FALSE; |
60f20e8b RS |
8793 | opcode = first; |
8794 | do | |
8795 | { | |
8796 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
8797 | if (is_opcode_valid_16 (opcode)) | |
8798 | { | |
8799 | seen_valid_for_isa = TRUE; | |
7fd53920 MR |
8800 | if (is_size_valid_16 (opcode)) |
8801 | { | |
8802 | seen_valid_for_size = TRUE; | |
8803 | if (match_mips16_insn (insn, opcode, tokens)) | |
8804 | return TRUE; | |
8805 | } | |
60f20e8b RS |
8806 | } |
8807 | ++opcode; | |
8808 | } | |
8809 | while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes] | |
8810 | && strcmp (opcode->name, first->name) == 0); | |
8811 | ||
8812 | /* Handle the case where we didn't try to match an instruction because | |
8813 | all the alternatives were incompatible with the current ISA. */ | |
8814 | if (!seen_valid_for_isa) | |
8815 | { | |
8816 | match_invalid_for_isa (); | |
8817 | return TRUE; | |
8818 | } | |
8819 | ||
7fd53920 MR |
8820 | /* Handle the case where we didn't try to match an instruction because |
8821 | all the alternatives were of the wrong size. */ | |
8822 | if (!seen_valid_for_size) | |
8823 | { | |
8824 | if (forced_insn_length == 2) | |
8825 | set_insn_error | |
8826 | (0, _("unrecognized unextended version of MIPS16 opcode")); | |
8827 | else | |
8828 | set_insn_error | |
8829 | (0, _("unrecognized extended version of MIPS16 opcode")); | |
8830 | return TRUE; | |
8831 | } | |
8832 | ||
60f20e8b RS |
8833 | return FALSE; |
8834 | } | |
8835 | ||
584892a6 RS |
8836 | /* Set up global variables for the start of a new macro. */ |
8837 | ||
8838 | static void | |
8839 | macro_start (void) | |
8840 | { | |
8841 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
8842 | memset (&mips_macro_warning.first_insn_sizes, 0, |
8843 | sizeof (mips_macro_warning.first_insn_sizes)); | |
8844 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 8845 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 8846 | && delayed_branch_p (&history[0])); |
7bd374a4 MR |
8847 | if (history[0].frag |
8848 | && history[0].frag->fr_type == rs_machine_dependent | |
8849 | && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) | |
8850 | && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) | |
8851 | mips_macro_warning.delay_slot_length = 0; | |
8852 | else | |
8853 | switch (history[0].insn_mo->pinfo2 | |
8854 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
8855 | { | |
8856 | case INSN2_BRANCH_DELAY_32BIT: | |
8857 | mips_macro_warning.delay_slot_length = 4; | |
8858 | break; | |
8859 | case INSN2_BRANCH_DELAY_16BIT: | |
8860 | mips_macro_warning.delay_slot_length = 2; | |
8861 | break; | |
8862 | default: | |
8863 | mips_macro_warning.delay_slot_length = 0; | |
8864 | break; | |
8865 | } | |
df58fc94 | 8866 | mips_macro_warning.first_frag = NULL; |
584892a6 RS |
8867 | } |
8868 | ||
df58fc94 RS |
8869 | /* Given that a macro is longer than one instruction or of the wrong size, |
8870 | return the appropriate warning for it. Return null if no warning is | |
8871 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
8872 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
8873 | and RELAX_NOMACRO. */ | |
584892a6 RS |
8874 | |
8875 | static const char * | |
8876 | macro_warning (relax_substateT subtype) | |
8877 | { | |
8878 | if (subtype & RELAX_DELAY_SLOT) | |
1661c76c | 8879 | return _("macro instruction expanded into multiple instructions" |
584892a6 RS |
8880 | " in a branch delay slot"); |
8881 | else if (subtype & RELAX_NOMACRO) | |
1661c76c | 8882 | return _("macro instruction expanded into multiple instructions"); |
df58fc94 RS |
8883 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
8884 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
8885 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
1661c76c | 8886 | ? _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 8887 | " in a 16-bit branch delay slot") |
1661c76c | 8888 | : _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 8889 | " in a 32-bit branch delay slot")); |
584892a6 RS |
8890 | else |
8891 | return 0; | |
8892 | } | |
8893 | ||
8894 | /* Finish up a macro. Emit warnings as appropriate. */ | |
8895 | ||
8896 | static void | |
8897 | macro_end (void) | |
8898 | { | |
df58fc94 RS |
8899 | /* Relaxation warning flags. */ |
8900 | relax_substateT subtype = 0; | |
8901 | ||
8902 | /* Check delay slot size requirements. */ | |
8903 | if (mips_macro_warning.delay_slot_length == 2) | |
8904 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
8905 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 8906 | { |
df58fc94 RS |
8907 | if (mips_macro_warning.delay_slot_length |
8908 | != mips_macro_warning.first_insn_sizes[0]) | |
8909 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
8910 | if (mips_macro_warning.delay_slot_length | |
8911 | != mips_macro_warning.first_insn_sizes[1]) | |
8912 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
8913 | } | |
584892a6 | 8914 | |
df58fc94 RS |
8915 | /* Check instruction count requirements. */ |
8916 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
8917 | { | |
8918 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
8919 | subtype |= RELAX_SECOND_LONGER; |
8920 | if (mips_opts.warn_about_macros) | |
8921 | subtype |= RELAX_NOMACRO; | |
8922 | if (mips_macro_warning.delay_slot_p) | |
8923 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 8924 | } |
584892a6 | 8925 | |
df58fc94 RS |
8926 | /* If both alternatives fail to fill a delay slot correctly, |
8927 | emit the warning now. */ | |
8928 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
8929 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
8930 | { | |
8931 | relax_substateT s; | |
8932 | const char *msg; | |
8933 | ||
8934 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
8935 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
8936 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
8937 | msg = macro_warning (s); | |
8938 | if (msg != NULL) | |
8939 | as_warn ("%s", msg); | |
8940 | subtype &= ~s; | |
8941 | } | |
8942 | ||
8943 | /* If both implementations are longer than 1 instruction, then emit the | |
8944 | warning now. */ | |
8945 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
8946 | { | |
8947 | relax_substateT s; | |
8948 | const char *msg; | |
8949 | ||
8950 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
8951 | msg = macro_warning (s); | |
8952 | if (msg != NULL) | |
8953 | as_warn ("%s", msg); | |
8954 | subtype &= ~s; | |
584892a6 | 8955 | } |
df58fc94 RS |
8956 | |
8957 | /* If any flags still set, then one implementation might need a warning | |
8958 | and the other either will need one of a different kind or none at all. | |
8959 | Pass any remaining flags over to relaxation. */ | |
8960 | if (mips_macro_warning.first_frag != NULL) | |
8961 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
8962 | } |
8963 | ||
df58fc94 RS |
8964 | /* Instruction operand formats used in macros that vary between |
8965 | standard MIPS and microMIPS code. */ | |
8966 | ||
833794fc | 8967 | static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } }; |
df58fc94 RS |
8968 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; |
8969 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
8970 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
8971 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
833794fc | 8972 | static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } }; |
df58fc94 RS |
8973 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; |
8974 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
8975 | ||
833794fc | 8976 | #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32]) |
7361da2c AB |
8977 | #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \ |
8978 | : cop12_fmt[mips_opts.micromips]) | |
df58fc94 RS |
8979 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) |
8980 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
8981 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
7361da2c AB |
8982 | #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \ |
8983 | : mem12_fmt[mips_opts.micromips]) | |
833794fc | 8984 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32]) |
df58fc94 RS |
8985 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) |
8986 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
8987 | ||
6e1304d8 RS |
8988 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
8989 | The first argument in *ARGS will be either the code for a single | |
8990 | relocation or -1 followed by the three codes that make up a | |
8991 | composite relocation. */ | |
8992 | ||
8993 | static void | |
8994 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
8995 | { | |
8996 | int i, next; | |
8997 | ||
8998 | next = va_arg (*args, int); | |
8999 | if (next >= 0) | |
9000 | r[0] = (bfd_reloc_code_real_type) next; | |
9001 | else | |
f2ae14a1 RS |
9002 | { |
9003 | for (i = 0; i < 3; i++) | |
9004 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
9005 | /* This function is only used for 16-bit relocation fields. | |
9006 | To make the macro code simpler, treat an unrelocated value | |
9007 | in the same way as BFD_RELOC_LO16. */ | |
9008 | if (r[0] == BFD_RELOC_UNUSED) | |
9009 | r[0] = BFD_RELOC_LO16; | |
9010 | } | |
6e1304d8 RS |
9011 | } |
9012 | ||
252b5132 RH |
9013 | /* Build an instruction created by a macro expansion. This is passed |
9014 | a pointer to the count of instructions created so far, an | |
9015 | expression, the name of the instruction to build, an operand format | |
9016 | string, and corresponding arguments. */ | |
9017 | ||
252b5132 | 9018 | static void |
67c0d1eb | 9019 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 9020 | { |
df58fc94 | 9021 | const struct mips_opcode *mo = NULL; |
f6688943 | 9022 | bfd_reloc_code_real_type r[3]; |
df58fc94 | 9023 | const struct mips_opcode *amo; |
e077a1c8 | 9024 | const struct mips_operand *operand; |
df58fc94 RS |
9025 | struct hash_control *hash; |
9026 | struct mips_cl_insn insn; | |
252b5132 | 9027 | va_list args; |
e077a1c8 | 9028 | unsigned int uval; |
252b5132 | 9029 | |
252b5132 | 9030 | va_start (args, fmt); |
252b5132 | 9031 | |
252b5132 RH |
9032 | if (mips_opts.mips16) |
9033 | { | |
03ea81db | 9034 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
9035 | va_end (args); |
9036 | return; | |
9037 | } | |
9038 | ||
f6688943 TS |
9039 | r[0] = BFD_RELOC_UNUSED; |
9040 | r[1] = BFD_RELOC_UNUSED; | |
9041 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
9042 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
9043 | amo = (struct mips_opcode *) hash_find (hash, name); | |
9044 | gas_assert (amo); | |
9045 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 9046 | |
df58fc94 | 9047 | do |
8b082fb1 TS |
9048 | { |
9049 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 | 9050 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
33eaf5de | 9051 | We try to match an instruction that fulfills the branch delay |
df58fc94 RS |
9052 | slot instruction length requirement (if any) of the previous |
9053 | instruction. While doing this we record the first instruction | |
9054 | seen that matches all the other conditions and use it anyway | |
9055 | if the requirement cannot be met; we will issue an appropriate | |
9056 | warning later on. */ | |
9057 | if (strcmp (fmt, amo->args) == 0 | |
9058 | && amo->pinfo != INSN_MACRO | |
9059 | && is_opcode_valid (amo) | |
9060 | && is_size_valid (amo)) | |
9061 | { | |
9062 | if (is_delay_slot_valid (amo)) | |
9063 | { | |
9064 | mo = amo; | |
9065 | break; | |
9066 | } | |
9067 | else if (!mo) | |
9068 | mo = amo; | |
9069 | } | |
8b082fb1 | 9070 | |
df58fc94 RS |
9071 | ++amo; |
9072 | gas_assert (amo->name); | |
252b5132 | 9073 | } |
df58fc94 | 9074 | while (strcmp (name, amo->name) == 0); |
252b5132 | 9075 | |
df58fc94 | 9076 | gas_assert (mo); |
1e915849 | 9077 | create_insn (&insn, mo); |
e077a1c8 | 9078 | for (; *fmt; ++fmt) |
252b5132 | 9079 | { |
e077a1c8 | 9080 | switch (*fmt) |
252b5132 | 9081 | { |
252b5132 RH |
9082 | case ',': |
9083 | case '(': | |
9084 | case ')': | |
252b5132 | 9085 | case 'z': |
e077a1c8 | 9086 | break; |
252b5132 RH |
9087 | |
9088 | case 'i': | |
9089 | case 'j': | |
6e1304d8 | 9090 | macro_read_relocs (&args, r); |
9c2799c2 | 9091 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
9092 | || *r == BFD_RELOC_MIPS_HIGHER |
9093 | || *r == BFD_RELOC_HI16_S | |
9094 | || *r == BFD_RELOC_LO16 | |
14c80123 MR |
9095 | || *r == BFD_RELOC_MIPS_GOT_OFST |
9096 | || (mips_opts.micromips | |
9097 | && (*r == BFD_RELOC_16 | |
9098 | || *r == BFD_RELOC_MIPS_GOT16 | |
9099 | || *r == BFD_RELOC_MIPS_CALL16 | |
9100 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
9101 | || *r == BFD_RELOC_MIPS_GOT_LO16 | |
9102 | || *r == BFD_RELOC_MIPS_CALL_HI16 | |
9103 | || *r == BFD_RELOC_MIPS_CALL_LO16 | |
9104 | || *r == BFD_RELOC_MIPS_SUB | |
9105 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
9106 | || *r == BFD_RELOC_MIPS_HIGHEST | |
9107 | || *r == BFD_RELOC_MIPS_GOT_DISP | |
9108 | || *r == BFD_RELOC_MIPS_TLS_GD | |
9109 | || *r == BFD_RELOC_MIPS_TLS_LDM | |
9110 | || *r == BFD_RELOC_MIPS_TLS_DTPREL_HI16 | |
9111 | || *r == BFD_RELOC_MIPS_TLS_DTPREL_LO16 | |
9112 | || *r == BFD_RELOC_MIPS_TLS_GOTTPREL | |
9113 | || *r == BFD_RELOC_MIPS_TLS_TPREL_HI16 | |
9114 | || *r == BFD_RELOC_MIPS_TLS_TPREL_LO16))); | |
e077a1c8 | 9115 | break; |
e391c024 RS |
9116 | |
9117 | case 'o': | |
9118 | macro_read_relocs (&args, r); | |
e077a1c8 | 9119 | break; |
252b5132 RH |
9120 | |
9121 | case 'u': | |
6e1304d8 | 9122 | macro_read_relocs (&args, r); |
9c2799c2 | 9123 | gas_assert (ep != NULL |
90ecf173 MR |
9124 | && (ep->X_op == O_constant |
9125 | || (ep->X_op == O_symbol | |
9126 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
9127 | || *r == BFD_RELOC_HI16_S | |
9128 | || *r == BFD_RELOC_HI16 | |
9129 | || *r == BFD_RELOC_GPREL16 | |
9130 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
9131 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
e077a1c8 | 9132 | break; |
252b5132 RH |
9133 | |
9134 | case 'p': | |
9c2799c2 | 9135 | gas_assert (ep != NULL); |
bad36eac | 9136 | |
252b5132 RH |
9137 | /* |
9138 | * This allows macro() to pass an immediate expression for | |
9139 | * creating short branches without creating a symbol. | |
bad36eac DJ |
9140 | * |
9141 | * We don't allow branch relaxation for these branches, as | |
9142 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
9143 | */ |
9144 | if (ep->X_op == O_constant) | |
9145 | { | |
df58fc94 RS |
9146 | /* For microMIPS we always use relocations for branches. |
9147 | So we should not resolve immediate values. */ | |
9148 | gas_assert (!mips_opts.micromips); | |
9149 | ||
bad36eac DJ |
9150 | if ((ep->X_add_number & 3) != 0) |
9151 | as_bad (_("branch to misaligned address (0x%lx)"), | |
9152 | (unsigned long) ep->X_add_number); | |
9153 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
9154 | as_bad (_("branch address range overflow (0x%lx)"), | |
9155 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
9156 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
9157 | ep = NULL; | |
9158 | } | |
9159 | else | |
0b25d3e6 | 9160 | *r = BFD_RELOC_16_PCREL_S2; |
e077a1c8 | 9161 | break; |
252b5132 RH |
9162 | |
9163 | case 'a': | |
9c2799c2 | 9164 | gas_assert (ep != NULL); |
f6688943 | 9165 | *r = BFD_RELOC_MIPS_JMP; |
e077a1c8 | 9166 | break; |
d43b4baf | 9167 | |
252b5132 | 9168 | default: |
e077a1c8 RS |
9169 | operand = (mips_opts.micromips |
9170 | ? decode_micromips_operand (fmt) | |
9171 | : decode_mips_operand (fmt)); | |
9172 | if (!operand) | |
9173 | abort (); | |
9174 | ||
9175 | uval = va_arg (args, int); | |
9176 | if (operand->type == OP_CLO_CLZ_DEST) | |
9177 | uval |= (uval << 5); | |
9178 | insn_insert_operand (&insn, operand, uval); | |
9179 | ||
7361da2c | 9180 | if (*fmt == '+' || *fmt == 'm' || *fmt == '-') |
e077a1c8 RS |
9181 | ++fmt; |
9182 | break; | |
252b5132 | 9183 | } |
252b5132 RH |
9184 | } |
9185 | va_end (args); | |
9c2799c2 | 9186 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 9187 | |
df58fc94 | 9188 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
9189 | } |
9190 | ||
9191 | static void | |
67c0d1eb | 9192 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 9193 | va_list *args) |
252b5132 | 9194 | { |
1e915849 | 9195 | struct mips_opcode *mo; |
252b5132 | 9196 | struct mips_cl_insn insn; |
e077a1c8 | 9197 | const struct mips_operand *operand; |
f6688943 TS |
9198 | bfd_reloc_code_real_type r[3] |
9199 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 9200 | |
1e915849 | 9201 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
9202 | gas_assert (mo); |
9203 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 9204 | |
1e915849 | 9205 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 9206 | { |
1e915849 | 9207 | ++mo; |
9c2799c2 NC |
9208 | gas_assert (mo->name); |
9209 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
9210 | } |
9211 | ||
1e915849 | 9212 | create_insn (&insn, mo); |
e077a1c8 | 9213 | for (; *fmt; ++fmt) |
252b5132 RH |
9214 | { |
9215 | int c; | |
9216 | ||
e077a1c8 | 9217 | c = *fmt; |
252b5132 RH |
9218 | switch (c) |
9219 | { | |
252b5132 RH |
9220 | case ',': |
9221 | case '(': | |
9222 | case ')': | |
e077a1c8 | 9223 | break; |
252b5132 | 9224 | |
d8722d76 | 9225 | case '.': |
252b5132 RH |
9226 | case 'S': |
9227 | case 'P': | |
9228 | case 'R': | |
e077a1c8 | 9229 | break; |
252b5132 RH |
9230 | |
9231 | case '<': | |
252b5132 | 9232 | case '5': |
d8722d76 | 9233 | case 'F': |
252b5132 RH |
9234 | case 'H': |
9235 | case 'W': | |
9236 | case 'D': | |
9237 | case 'j': | |
9238 | case '8': | |
9239 | case 'V': | |
9240 | case 'C': | |
9241 | case 'U': | |
9242 | case 'k': | |
9243 | case 'K': | |
9244 | case 'p': | |
9245 | case 'q': | |
9246 | { | |
b886a2ab RS |
9247 | offsetT value; |
9248 | ||
9c2799c2 | 9249 | gas_assert (ep != NULL); |
252b5132 RH |
9250 | |
9251 | if (ep->X_op != O_constant) | |
874e8986 | 9252 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 9253 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 9254 | { |
b886a2ab | 9255 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 9256 | ep = NULL; |
f6688943 | 9257 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
9258 | } |
9259 | } | |
e077a1c8 | 9260 | break; |
252b5132 | 9261 | |
e077a1c8 RS |
9262 | default: |
9263 | operand = decode_mips16_operand (c, FALSE); | |
9264 | if (!operand) | |
9265 | abort (); | |
252b5132 | 9266 | |
4a06e5a2 | 9267 | insn_insert_operand (&insn, operand, va_arg (*args, int)); |
e077a1c8 RS |
9268 | break; |
9269 | } | |
252b5132 RH |
9270 | } |
9271 | ||
9c2799c2 | 9272 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 9273 | |
df58fc94 | 9274 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
9275 | } |
9276 | ||
438c16b8 TS |
9277 | /* |
9278 | * Generate a "jalr" instruction with a relocation hint to the called | |
9279 | * function. This occurs in NewABI PIC code. | |
9280 | */ | |
9281 | static void | |
df58fc94 | 9282 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 9283 | { |
df58fc94 RS |
9284 | static const bfd_reloc_code_real_type jalr_relocs[2] |
9285 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
9286 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
9287 | const char *jalr; | |
685736be | 9288 | char *f = NULL; |
b34976b6 | 9289 | |
1180b5a4 | 9290 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 9291 | { |
cc3d92a5 | 9292 | frag_grow (8); |
f21f8242 AO |
9293 | f = frag_more (0); |
9294 | } | |
2906b037 | 9295 | if (mips_opts.micromips) |
df58fc94 | 9296 | { |
833794fc MR |
9297 | jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32 |
9298 | ? "jalr" : "jalrs"); | |
e64af278 | 9299 | if (MIPS_JALR_HINT_P (ep) |
833794fc | 9300 | || mips_opts.insn32 |
e64af278 | 9301 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
df58fc94 RS |
9302 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
9303 | else | |
9304 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
9305 | } | |
2906b037 MR |
9306 | else |
9307 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 9308 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 9309 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
9310 | } |
9311 | ||
252b5132 RH |
9312 | /* |
9313 | * Generate a "lui" instruction. | |
9314 | */ | |
9315 | static void | |
67c0d1eb | 9316 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 9317 | { |
9c2799c2 | 9318 | gas_assert (! mips_opts.mips16); |
252b5132 | 9319 | |
df58fc94 | 9320 | if (ep->X_op != O_constant) |
252b5132 | 9321 | { |
9c2799c2 | 9322 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
9323 | /* _gp_disp is a special case, used from s_cpload. |
9324 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 9325 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 9326 | || (! HAVE_NEWABI |
aa6975fb ILT |
9327 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
9328 | || (! mips_in_shared | |
bbe506e8 TS |
9329 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
9330 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
9331 | } |
9332 | ||
df58fc94 | 9333 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
9334 | } |
9335 | ||
885add95 CD |
9336 | /* Generate a sequence of instructions to do a load or store from a constant |
9337 | offset off of a base register (breg) into/from a target register (treg), | |
9338 | using AT if necessary. */ | |
9339 | static void | |
67c0d1eb RS |
9340 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
9341 | int treg, int breg, int dbl) | |
885add95 | 9342 | { |
9c2799c2 | 9343 | gas_assert (ep->X_op == O_constant); |
885add95 | 9344 | |
256ab948 | 9345 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
9346 | if (!dbl) |
9347 | normalize_constant_expr (ep); | |
256ab948 | 9348 | |
67c1ffbe | 9349 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 9350 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
9351 | as_warn (_("operand overflow")); |
9352 | ||
9353 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
9354 | { | |
9355 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 9356 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
9357 | } |
9358 | else | |
9359 | { | |
9360 | /* 32-bit offset, need multiple instructions and AT, like: | |
9361 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
9362 | addu $tempreg,$tempreg,$breg | |
9363 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
9364 | to handle the complete offset. */ | |
67c0d1eb RS |
9365 | macro_build_lui (ep, AT); |
9366 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
9367 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 9368 | |
741fe287 | 9369 | if (!mips_opts.at) |
1661c76c | 9370 | as_bad (_("macro used $at after \".set noat\"")); |
885add95 CD |
9371 | } |
9372 | } | |
9373 | ||
252b5132 RH |
9374 | /* set_at() |
9375 | * Generates code to set the $at register to true (one) | |
9376 | * if reg is less than the immediate expression. | |
9377 | */ | |
9378 | static void | |
67c0d1eb | 9379 | set_at (int reg, int unsignedp) |
252b5132 | 9380 | { |
b0e6f033 | 9381 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 9382 | && imm_expr.X_add_number < 0x8000) |
67c0d1eb RS |
9383 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
9384 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
9385 | else |
9386 | { | |
bad1aba3 | 9387 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 9388 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); |
252b5132 RH |
9389 | } |
9390 | } | |
9391 | ||
252b5132 RH |
9392 | /* Count the leading zeroes by performing a binary chop. This is a |
9393 | bulky bit of source, but performance is a LOT better for the | |
9394 | majority of values than a simple loop to count the bits: | |
9395 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
9396 | if ((v) & (1 << (31 - lcnt))) | |
9397 | break; | |
9398 | However it is not code size friendly, and the gain will drop a bit | |
9399 | on certain cached systems. | |
9400 | */ | |
9401 | #define COUNT_TOP_ZEROES(v) \ | |
9402 | (((v) & ~0xffff) == 0 \ | |
9403 | ? ((v) & ~0xff) == 0 \ | |
9404 | ? ((v) & ~0xf) == 0 \ | |
9405 | ? ((v) & ~0x3) == 0 \ | |
9406 | ? ((v) & ~0x1) == 0 \ | |
9407 | ? !(v) \ | |
9408 | ? 32 \ | |
9409 | : 31 \ | |
9410 | : 30 \ | |
9411 | : ((v) & ~0x7) == 0 \ | |
9412 | ? 29 \ | |
9413 | : 28 \ | |
9414 | : ((v) & ~0x3f) == 0 \ | |
9415 | ? ((v) & ~0x1f) == 0 \ | |
9416 | ? 27 \ | |
9417 | : 26 \ | |
9418 | : ((v) & ~0x7f) == 0 \ | |
9419 | ? 25 \ | |
9420 | : 24 \ | |
9421 | : ((v) & ~0xfff) == 0 \ | |
9422 | ? ((v) & ~0x3ff) == 0 \ | |
9423 | ? ((v) & ~0x1ff) == 0 \ | |
9424 | ? 23 \ | |
9425 | : 22 \ | |
9426 | : ((v) & ~0x7ff) == 0 \ | |
9427 | ? 21 \ | |
9428 | : 20 \ | |
9429 | : ((v) & ~0x3fff) == 0 \ | |
9430 | ? ((v) & ~0x1fff) == 0 \ | |
9431 | ? 19 \ | |
9432 | : 18 \ | |
9433 | : ((v) & ~0x7fff) == 0 \ | |
9434 | ? 17 \ | |
9435 | : 16 \ | |
9436 | : ((v) & ~0xffffff) == 0 \ | |
9437 | ? ((v) & ~0xfffff) == 0 \ | |
9438 | ? ((v) & ~0x3ffff) == 0 \ | |
9439 | ? ((v) & ~0x1ffff) == 0 \ | |
9440 | ? 15 \ | |
9441 | : 14 \ | |
9442 | : ((v) & ~0x7ffff) == 0 \ | |
9443 | ? 13 \ | |
9444 | : 12 \ | |
9445 | : ((v) & ~0x3fffff) == 0 \ | |
9446 | ? ((v) & ~0x1fffff) == 0 \ | |
9447 | ? 11 \ | |
9448 | : 10 \ | |
9449 | : ((v) & ~0x7fffff) == 0 \ | |
9450 | ? 9 \ | |
9451 | : 8 \ | |
9452 | : ((v) & ~0xfffffff) == 0 \ | |
9453 | ? ((v) & ~0x3ffffff) == 0 \ | |
9454 | ? ((v) & ~0x1ffffff) == 0 \ | |
9455 | ? 7 \ | |
9456 | : 6 \ | |
9457 | : ((v) & ~0x7ffffff) == 0 \ | |
9458 | ? 5 \ | |
9459 | : 4 \ | |
9460 | : ((v) & ~0x3fffffff) == 0 \ | |
9461 | ? ((v) & ~0x1fffffff) == 0 \ | |
9462 | ? 3 \ | |
9463 | : 2 \ | |
9464 | : ((v) & ~0x7fffffff) == 0 \ | |
9465 | ? 1 \ | |
9466 | : 0) | |
9467 | ||
9468 | /* load_register() | |
67c1ffbe | 9469 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
9470 | * an absolute expression value into a register. |
9471 | */ | |
9472 | static void | |
67c0d1eb | 9473 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
9474 | { |
9475 | int freg; | |
9476 | expressionS hi32, lo32; | |
9477 | ||
9478 | if (ep->X_op != O_big) | |
9479 | { | |
9c2799c2 | 9480 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
9481 | |
9482 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
9483 | if (!dbl) |
9484 | normalize_constant_expr (ep); | |
256ab948 TS |
9485 | |
9486 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
9487 | { |
9488 | /* We can handle 16 bit signed values with an addiu to | |
9489 | $zero. No need to ever use daddiu here, since $zero and | |
9490 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 9491 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9492 | return; |
9493 | } | |
9494 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
9495 | { | |
9496 | /* We can handle 16 bit unsigned values with an ori to | |
9497 | $zero. */ | |
67c0d1eb | 9498 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9499 | return; |
9500 | } | |
256ab948 | 9501 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
9502 | { |
9503 | /* 32 bit values require an lui. */ | |
df58fc94 | 9504 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 9505 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 9506 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
9507 | return; |
9508 | } | |
9509 | } | |
9510 | ||
9511 | /* The value is larger than 32 bits. */ | |
9512 | ||
bad1aba3 | 9513 | if (!dbl || GPR_SIZE == 32) |
252b5132 | 9514 | { |
55e08f71 NC |
9515 | char value[32]; |
9516 | ||
9517 | sprintf_vma (value, ep->X_add_number); | |
1661c76c | 9518 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 9519 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9520 | return; |
9521 | } | |
9522 | ||
9523 | if (ep->X_op != O_big) | |
9524 | { | |
9525 | hi32 = *ep; | |
9526 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
9527 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
9528 | hi32.X_add_number &= 0xffffffff; | |
9529 | lo32 = *ep; | |
9530 | lo32.X_add_number &= 0xffffffff; | |
9531 | } | |
9532 | else | |
9533 | { | |
9c2799c2 | 9534 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
9535 | if (ep->X_add_number == 3) |
9536 | generic_bignum[3] = 0; | |
9537 | else if (ep->X_add_number > 4) | |
1661c76c | 9538 | as_bad (_("number larger than 64 bits")); |
252b5132 RH |
9539 | lo32.X_op = O_constant; |
9540 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
9541 | hi32.X_op = O_constant; | |
9542 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
9543 | } | |
9544 | ||
9545 | if (hi32.X_add_number == 0) | |
9546 | freg = 0; | |
9547 | else | |
9548 | { | |
9549 | int shift, bit; | |
9550 | unsigned long hi, lo; | |
9551 | ||
956cd1d6 | 9552 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
9553 | { |
9554 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
9555 | { | |
67c0d1eb | 9556 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
9557 | return; |
9558 | } | |
9559 | if (lo32.X_add_number & 0x80000000) | |
9560 | { | |
df58fc94 | 9561 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 9562 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 9563 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
9564 | return; |
9565 | } | |
9566 | } | |
252b5132 RH |
9567 | |
9568 | /* Check for 16bit shifted constant. We know that hi32 is | |
9569 | non-zero, so start the mask on the first bit of the hi32 | |
9570 | value. */ | |
9571 | shift = 17; | |
9572 | do | |
beae10d5 KH |
9573 | { |
9574 | unsigned long himask, lomask; | |
9575 | ||
9576 | if (shift < 32) | |
9577 | { | |
9578 | himask = 0xffff >> (32 - shift); | |
9579 | lomask = (0xffff << shift) & 0xffffffff; | |
9580 | } | |
9581 | else | |
9582 | { | |
9583 | himask = 0xffff << (shift - 32); | |
9584 | lomask = 0; | |
9585 | } | |
9586 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
9587 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
9588 | { | |
9589 | expressionS tmp; | |
9590 | ||
9591 | tmp.X_op = O_constant; | |
9592 | if (shift < 32) | |
9593 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
9594 | | (lo32.X_add_number >> shift)); | |
9595 | else | |
9596 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 9597 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 9598 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 9599 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
9600 | return; |
9601 | } | |
f9419b05 | 9602 | ++shift; |
beae10d5 KH |
9603 | } |
9604 | while (shift <= (64 - 16)); | |
252b5132 RH |
9605 | |
9606 | /* Find the bit number of the lowest one bit, and store the | |
9607 | shifted value in hi/lo. */ | |
9608 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
9609 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
9610 | if (lo != 0) | |
9611 | { | |
9612 | bit = 0; | |
9613 | while ((lo & 1) == 0) | |
9614 | { | |
9615 | lo >>= 1; | |
9616 | ++bit; | |
9617 | } | |
9618 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
9619 | hi >>= bit; | |
9620 | } | |
9621 | else | |
9622 | { | |
9623 | bit = 32; | |
9624 | while ((hi & 1) == 0) | |
9625 | { | |
9626 | hi >>= 1; | |
9627 | ++bit; | |
9628 | } | |
9629 | lo = hi; | |
9630 | hi = 0; | |
9631 | } | |
9632 | ||
9633 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
9634 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
9635 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
9636 | { |
9637 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 9638 | if (shift != 0) |
beae10d5 | 9639 | { |
252b5132 RH |
9640 | expressionS tmp; |
9641 | ||
9642 | /* This instruction will set the register to be all | |
9643 | ones. */ | |
beae10d5 KH |
9644 | tmp.X_op = O_constant; |
9645 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 9646 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
9647 | if (bit != 0) |
9648 | { | |
9649 | bit += shift; | |
df58fc94 | 9650 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 9651 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 9652 | } |
df58fc94 | 9653 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 9654 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
9655 | return; |
9656 | } | |
9657 | } | |
252b5132 RH |
9658 | |
9659 | /* Sign extend hi32 before calling load_register, because we can | |
9660 | generally get better code when we load a sign extended value. */ | |
9661 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 9662 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 9663 | load_register (reg, &hi32, 0); |
252b5132 RH |
9664 | freg = reg; |
9665 | } | |
9666 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
9667 | { | |
9668 | if (freg != 0) | |
9669 | { | |
df58fc94 | 9670 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
9671 | freg = reg; |
9672 | } | |
9673 | } | |
9674 | else | |
9675 | { | |
9676 | expressionS mid16; | |
9677 | ||
956cd1d6 | 9678 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 9679 | { |
df58fc94 RS |
9680 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
9681 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
9682 | return; |
9683 | } | |
252b5132 RH |
9684 | |
9685 | if (freg != 0) | |
9686 | { | |
df58fc94 | 9687 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
9688 | freg = reg; |
9689 | } | |
9690 | mid16 = lo32; | |
9691 | mid16.X_add_number >>= 16; | |
67c0d1eb | 9692 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 9693 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
9694 | freg = reg; |
9695 | } | |
9696 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 9697 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
9698 | } |
9699 | ||
269137b2 TS |
9700 | static inline void |
9701 | load_delay_nop (void) | |
9702 | { | |
9703 | if (!gpr_interlocks) | |
9704 | macro_build (NULL, "nop", ""); | |
9705 | } | |
9706 | ||
252b5132 RH |
9707 | /* Load an address into a register. */ |
9708 | ||
9709 | static void | |
67c0d1eb | 9710 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 9711 | { |
252b5132 RH |
9712 | if (ep->X_op != O_constant |
9713 | && ep->X_op != O_symbol) | |
9714 | { | |
9715 | as_bad (_("expression too complex")); | |
9716 | ep->X_op = O_constant; | |
9717 | } | |
9718 | ||
9719 | if (ep->X_op == O_constant) | |
9720 | { | |
67c0d1eb | 9721 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
9722 | return; |
9723 | } | |
9724 | ||
9725 | if (mips_pic == NO_PIC) | |
9726 | { | |
9727 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 9728 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
9729 | Otherwise we want |
9730 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
9731 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 9732 | If we have an addend, we always use the latter form. |
76b3015f | 9733 | |
d6bc6245 TS |
9734 | With 64bit address space and a usable $at we want |
9735 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9736 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9737 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9738 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
9739 | dsll32 $reg,0 | |
3a482fd5 | 9740 | daddu $reg,$reg,$at |
76b3015f | 9741 | |
c03099e6 | 9742 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
9743 | on superscalar processors. |
9744 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9745 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9746 | dsll $reg,16 | |
9747 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
9748 | dsll $reg,16 | |
9749 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
9750 | |
9751 | For GP relative symbols in 64bit address space we can use | |
9752 | the same sequence as in 32bit address space. */ | |
aed1a261 | 9753 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 9754 | { |
6caf9ef4 TS |
9755 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
9756 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
9757 | { | |
9758 | relax_start (ep->X_add_symbol); | |
9759 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
9760 | mips_gp_register, BFD_RELOC_GPREL16); | |
9761 | relax_switch (); | |
9762 | } | |
d6bc6245 | 9763 | |
741fe287 | 9764 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 9765 | { |
df58fc94 RS |
9766 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
9767 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
9768 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
9769 | BFD_RELOC_MIPS_HIGHER); | |
9770 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 9771 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 9772 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
9773 | *used_at = 1; |
9774 | } | |
9775 | else | |
9776 | { | |
df58fc94 | 9777 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
9778 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
9779 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 9780 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 9781 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 9782 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 9783 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 9784 | } |
6caf9ef4 TS |
9785 | |
9786 | if (mips_relax.sequence) | |
9787 | relax_end (); | |
d6bc6245 | 9788 | } |
252b5132 RH |
9789 | else |
9790 | { | |
d6bc6245 | 9791 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 9792 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 9793 | { |
4d7206a2 | 9794 | relax_start (ep->X_add_symbol); |
67c0d1eb | 9795 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 9796 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 9797 | relax_switch (); |
d6bc6245 | 9798 | } |
67c0d1eb RS |
9799 | macro_build_lui (ep, reg); |
9800 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
9801 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
9802 | if (mips_relax.sequence) |
9803 | relax_end (); | |
d6bc6245 | 9804 | } |
252b5132 | 9805 | } |
0a44bf69 | 9806 | else if (!mips_big_got) |
252b5132 RH |
9807 | { |
9808 | expressionS ex; | |
9809 | ||
9810 | /* If this is a reference to an external symbol, we want | |
9811 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9812 | Otherwise we want | |
9813 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9814 | nop | |
9815 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
9816 | If there is a constant, it must be added in after. |
9817 | ||
ed6fb7bd | 9818 | If we have NewABI, we want |
f5040a92 AO |
9819 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
9820 | unless we're referencing a global symbol with a non-zero | |
9821 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
9822 | if (HAVE_NEWABI) |
9823 | { | |
f5040a92 AO |
9824 | if (ep->X_add_number) |
9825 | { | |
4d7206a2 | 9826 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 9827 | ep->X_add_number = 0; |
4d7206a2 | 9828 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
9829 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
9830 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
9831 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
9832 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9833 | ex.X_op = O_constant; | |
67c0d1eb | 9834 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 9835 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 9836 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 9837 | relax_switch (); |
f5040a92 | 9838 | } |
67c0d1eb | 9839 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9840 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
9841 | if (mips_relax.sequence) |
9842 | relax_end (); | |
ed6fb7bd SC |
9843 | } |
9844 | else | |
9845 | { | |
f5040a92 AO |
9846 | ex.X_add_number = ep->X_add_number; |
9847 | ep->X_add_number = 0; | |
67c0d1eb RS |
9848 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
9849 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9850 | load_delay_nop (); |
4d7206a2 RS |
9851 | relax_start (ep->X_add_symbol); |
9852 | relax_switch (); | |
67c0d1eb | 9853 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 9854 | BFD_RELOC_LO16); |
4d7206a2 | 9855 | relax_end (); |
ed6fb7bd | 9856 | |
f5040a92 AO |
9857 | if (ex.X_add_number != 0) |
9858 | { | |
9859 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
9860 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9861 | ex.X_op = O_constant; | |
67c0d1eb | 9862 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 9863 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 9864 | } |
252b5132 RH |
9865 | } |
9866 | } | |
0a44bf69 | 9867 | else if (mips_big_got) |
252b5132 RH |
9868 | { |
9869 | expressionS ex; | |
252b5132 RH |
9870 | |
9871 | /* This is the large GOT case. If this is a reference to an | |
9872 | external symbol, we want | |
9873 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9874 | addu $reg,$reg,$gp | |
9875 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
9876 | |
9877 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
9878 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
9879 | nop | |
9880 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 9881 | If there is a constant, it must be added in after. |
f5040a92 AO |
9882 | |
9883 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
9884 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
9885 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 9886 | */ |
438c16b8 TS |
9887 | if (HAVE_NEWABI) |
9888 | { | |
4d7206a2 | 9889 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 9890 | ep->X_add_number = 0; |
4d7206a2 | 9891 | relax_start (ep->X_add_symbol); |
df58fc94 | 9892 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9893 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
9894 | reg, reg, mips_gp_register); | |
9895 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
9896 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
9897 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
9898 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9899 | else if (ex.X_add_number) | |
9900 | { | |
9901 | ex.X_op = O_constant; | |
67c0d1eb RS |
9902 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9903 | BFD_RELOC_LO16); | |
f5040a92 AO |
9904 | } |
9905 | ||
9906 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 9907 | relax_switch (); |
67c0d1eb | 9908 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9909 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
9910 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9911 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 9912 | relax_end (); |
438c16b8 | 9913 | } |
252b5132 | 9914 | else |
438c16b8 | 9915 | { |
f5040a92 AO |
9916 | ex.X_add_number = ep->X_add_number; |
9917 | ep->X_add_number = 0; | |
4d7206a2 | 9918 | relax_start (ep->X_add_symbol); |
df58fc94 | 9919 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9920 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
9921 | reg, reg, mips_gp_register); | |
9922 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
9923 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
9924 | relax_switch (); |
9925 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
9926 | { |
9927 | /* We need a nop before loading from $gp. This special | |
9928 | check is required because the lui which starts the main | |
9929 | instruction stream does not refer to $gp, and so will not | |
9930 | insert the nop which may be required. */ | |
67c0d1eb | 9931 | macro_build (NULL, "nop", ""); |
438c16b8 | 9932 | } |
67c0d1eb | 9933 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9934 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 9935 | load_delay_nop (); |
67c0d1eb | 9936 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 9937 | BFD_RELOC_LO16); |
4d7206a2 | 9938 | relax_end (); |
438c16b8 | 9939 | |
f5040a92 AO |
9940 | if (ex.X_add_number != 0) |
9941 | { | |
9942 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
9943 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9944 | ex.X_op = O_constant; | |
67c0d1eb RS |
9945 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9946 | BFD_RELOC_LO16); | |
f5040a92 | 9947 | } |
252b5132 RH |
9948 | } |
9949 | } | |
252b5132 RH |
9950 | else |
9951 | abort (); | |
8fc2e39e | 9952 | |
741fe287 | 9953 | if (!mips_opts.at && *used_at == 1) |
1661c76c | 9954 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
9955 | } |
9956 | ||
ea1fb5dc RS |
9957 | /* Move the contents of register SOURCE into register DEST. */ |
9958 | ||
9959 | static void | |
67c0d1eb | 9960 | move_register (int dest, int source) |
ea1fb5dc | 9961 | { |
df58fc94 RS |
9962 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
9963 | instruction specifically requires a 32-bit one. */ | |
9964 | if (mips_opts.micromips | |
833794fc | 9965 | && !mips_opts.insn32 |
df58fc94 | 9966 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
7951ca42 | 9967 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 | 9968 | else |
40fc1451 | 9969 | macro_build (NULL, "or", "d,v,t", dest, source, 0); |
ea1fb5dc RS |
9970 | } |
9971 | ||
4d7206a2 | 9972 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
9973 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
9974 | The two alternatives are: | |
4d7206a2 | 9975 | |
33eaf5de | 9976 | Global symbol Local symbol |
4d7206a2 RS |
9977 | ------------- ------------ |
9978 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
9979 | ... ... | |
9980 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
9981 | ||
9982 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
9983 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
9984 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
9985 | |
9986 | static void | |
67c0d1eb | 9987 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
9988 | { |
9989 | expressionS global; | |
9990 | ||
9991 | global = *local; | |
9992 | global.X_add_number = 0; | |
9993 | ||
9994 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
9995 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
9996 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 9997 | relax_switch (); |
67c0d1eb RS |
9998 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
9999 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
10000 | relax_end (); |
10001 | } | |
10002 | ||
10003 | static void | |
67c0d1eb | 10004 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
10005 | { |
10006 | expressionS global; | |
10007 | ||
10008 | global.X_op = O_constant; | |
10009 | global.X_op_symbol = NULL; | |
10010 | global.X_add_symbol = NULL; | |
10011 | global.X_add_number = local->X_add_number; | |
10012 | ||
10013 | relax_start (local->X_add_symbol); | |
67c0d1eb | 10014 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
10015 | dest, dest, BFD_RELOC_LO16); |
10016 | relax_switch (); | |
67c0d1eb | 10017 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
10018 | relax_end (); |
10019 | } | |
10020 | ||
f6a22291 MR |
10021 | static void |
10022 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
10023 | { | |
10024 | expressionS global; | |
10025 | int hold_mips_optimize; | |
10026 | ||
10027 | global.X_op = O_constant; | |
10028 | global.X_op_symbol = NULL; | |
10029 | global.X_add_symbol = NULL; | |
10030 | global.X_add_number = local->X_add_number; | |
10031 | ||
10032 | relax_start (local->X_add_symbol); | |
10033 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
10034 | relax_switch (); | |
10035 | /* Set mips_optimize around the lui instruction to avoid | |
10036 | inserting an unnecessary nop after the lw. */ | |
10037 | hold_mips_optimize = mips_optimize; | |
10038 | mips_optimize = 2; | |
10039 | macro_build_lui (&global, tmp); | |
10040 | mips_optimize = hold_mips_optimize; | |
10041 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
10042 | relax_end (); | |
10043 | ||
10044 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
10045 | } | |
10046 | ||
df58fc94 RS |
10047 | /* Emit a sequence of instructions to emulate a branch likely operation. |
10048 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
10049 | is its complementing branch with the original condition negated. | |
10050 | CALL is set if the original branch specified the link operation. | |
10051 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
10052 | ||
10053 | Code like this is produced in the noreorder mode: | |
10054 | ||
10055 | BRNEG <args>, 1f | |
10056 | nop | |
10057 | b <sym> | |
10058 | delay slot (executed only if branch taken) | |
10059 | 1: | |
10060 | ||
10061 | or, if CALL is set: | |
10062 | ||
10063 | BRNEG <args>, 1f | |
10064 | nop | |
10065 | bal <sym> | |
10066 | delay slot (executed only if branch taken) | |
10067 | 1: | |
10068 | ||
10069 | In the reorder mode the delay slot would be filled with a nop anyway, | |
10070 | so code produced is simply: | |
10071 | ||
10072 | BR <args>, <sym> | |
10073 | nop | |
10074 | ||
10075 | This function is used when producing code for the microMIPS ASE that | |
10076 | does not implement branch likely instructions in hardware. */ | |
10077 | ||
10078 | static void | |
10079 | macro_build_branch_likely (const char *br, const char *brneg, | |
10080 | int call, expressionS *ep, const char *fmt, | |
10081 | unsigned int sreg, unsigned int treg) | |
10082 | { | |
10083 | int noreorder = mips_opts.noreorder; | |
10084 | expressionS expr1; | |
10085 | ||
10086 | gas_assert (mips_opts.micromips); | |
10087 | start_noreorder (); | |
10088 | if (noreorder) | |
10089 | { | |
10090 | micromips_label_expr (&expr1); | |
10091 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
10092 | macro_build (NULL, "nop", ""); | |
10093 | macro_build (ep, call ? "bal" : "b", "p"); | |
10094 | ||
10095 | /* Set to true so that append_insn adds a label. */ | |
10096 | emit_branch_likely_macro = TRUE; | |
10097 | } | |
10098 | else | |
10099 | { | |
10100 | macro_build (ep, br, fmt, sreg, treg); | |
10101 | macro_build (NULL, "nop", ""); | |
10102 | } | |
10103 | end_noreorder (); | |
10104 | } | |
10105 | ||
10106 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
10107 | the condition code tested. EP specifies the branch target. */ | |
10108 | ||
10109 | static void | |
10110 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
10111 | { | |
10112 | const int call = 0; | |
10113 | const char *brneg; | |
10114 | const char *br; | |
10115 | ||
10116 | switch (type) | |
10117 | { | |
10118 | case M_BC1FL: | |
10119 | br = "bc1f"; | |
10120 | brneg = "bc1t"; | |
10121 | break; | |
10122 | case M_BC1TL: | |
10123 | br = "bc1t"; | |
10124 | brneg = "bc1f"; | |
10125 | break; | |
10126 | case M_BC2FL: | |
10127 | br = "bc2f"; | |
10128 | brneg = "bc2t"; | |
10129 | break; | |
10130 | case M_BC2TL: | |
10131 | br = "bc2t"; | |
10132 | brneg = "bc2f"; | |
10133 | break; | |
10134 | default: | |
10135 | abort (); | |
10136 | } | |
10137 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
10138 | } | |
10139 | ||
10140 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
10141 | the register tested. EP specifies the branch target. */ | |
10142 | ||
10143 | static void | |
10144 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
10145 | { | |
10146 | const char *brneg = NULL; | |
10147 | const char *br; | |
10148 | int call = 0; | |
10149 | ||
10150 | switch (type) | |
10151 | { | |
10152 | case M_BGEZ: | |
10153 | br = "bgez"; | |
10154 | break; | |
10155 | case M_BGEZL: | |
10156 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
10157 | brneg = "bltz"; | |
10158 | break; | |
10159 | case M_BGEZALL: | |
10160 | gas_assert (mips_opts.micromips); | |
833794fc | 10161 | br = mips_opts.insn32 ? "bgezal" : "bgezals"; |
df58fc94 RS |
10162 | brneg = "bltz"; |
10163 | call = 1; | |
10164 | break; | |
10165 | case M_BGTZ: | |
10166 | br = "bgtz"; | |
10167 | break; | |
10168 | case M_BGTZL: | |
10169 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
10170 | brneg = "blez"; | |
10171 | break; | |
10172 | case M_BLEZ: | |
10173 | br = "blez"; | |
10174 | break; | |
10175 | case M_BLEZL: | |
10176 | br = mips_opts.micromips ? "blez" : "blezl"; | |
10177 | brneg = "bgtz"; | |
10178 | break; | |
10179 | case M_BLTZ: | |
10180 | br = "bltz"; | |
10181 | break; | |
10182 | case M_BLTZL: | |
10183 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
10184 | brneg = "bgez"; | |
10185 | break; | |
10186 | case M_BLTZALL: | |
10187 | gas_assert (mips_opts.micromips); | |
833794fc | 10188 | br = mips_opts.insn32 ? "bltzal" : "bltzals"; |
df58fc94 RS |
10189 | brneg = "bgez"; |
10190 | call = 1; | |
10191 | break; | |
10192 | default: | |
10193 | abort (); | |
10194 | } | |
10195 | if (mips_opts.micromips && brneg) | |
10196 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
10197 | else | |
10198 | macro_build (ep, br, "s,p", sreg); | |
10199 | } | |
10200 | ||
10201 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
10202 | TREG as the registers tested. EP specifies the branch target. */ | |
10203 | ||
10204 | static void | |
10205 | macro_build_branch_rsrt (int type, expressionS *ep, | |
10206 | unsigned int sreg, unsigned int treg) | |
10207 | { | |
10208 | const char *brneg = NULL; | |
10209 | const int call = 0; | |
10210 | const char *br; | |
10211 | ||
10212 | switch (type) | |
10213 | { | |
10214 | case M_BEQ: | |
10215 | case M_BEQ_I: | |
10216 | br = "beq"; | |
10217 | break; | |
10218 | case M_BEQL: | |
10219 | case M_BEQL_I: | |
10220 | br = mips_opts.micromips ? "beq" : "beql"; | |
10221 | brneg = "bne"; | |
10222 | break; | |
10223 | case M_BNE: | |
10224 | case M_BNE_I: | |
10225 | br = "bne"; | |
10226 | break; | |
10227 | case M_BNEL: | |
10228 | case M_BNEL_I: | |
10229 | br = mips_opts.micromips ? "bne" : "bnel"; | |
10230 | brneg = "beq"; | |
10231 | break; | |
10232 | default: | |
10233 | abort (); | |
10234 | } | |
10235 | if (mips_opts.micromips && brneg) | |
10236 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
10237 | else | |
10238 | macro_build (ep, br, "s,t,p", sreg, treg); | |
10239 | } | |
10240 | ||
f2ae14a1 RS |
10241 | /* Return the high part that should be loaded in order to make the low |
10242 | part of VALUE accessible using an offset of OFFBITS bits. */ | |
10243 | ||
10244 | static offsetT | |
10245 | offset_high_part (offsetT value, unsigned int offbits) | |
10246 | { | |
10247 | offsetT bias; | |
10248 | addressT low_mask; | |
10249 | ||
10250 | if (offbits == 0) | |
10251 | return value; | |
10252 | bias = 1 << (offbits - 1); | |
10253 | low_mask = bias * 2 - 1; | |
10254 | return (value + bias) & ~low_mask; | |
10255 | } | |
10256 | ||
10257 | /* Return true if the value stored in offset_expr and offset_reloc | |
10258 | fits into a signed offset of OFFBITS bits. RANGE is the maximum | |
10259 | amount that the caller wants to add without inducing overflow | |
10260 | and ALIGN is the known alignment of the value in bytes. */ | |
10261 | ||
10262 | static bfd_boolean | |
10263 | small_offset_p (unsigned int range, unsigned int align, unsigned int offbits) | |
10264 | { | |
10265 | if (offbits == 16) | |
10266 | { | |
10267 | /* Accept any relocation operator if overflow isn't a concern. */ | |
10268 | if (range < align && *offset_reloc != BFD_RELOC_UNUSED) | |
10269 | return TRUE; | |
10270 | ||
10271 | /* These relocations are guaranteed not to overflow in correct links. */ | |
10272 | if (*offset_reloc == BFD_RELOC_MIPS_LITERAL | |
10273 | || gprel16_reloc_p (*offset_reloc)) | |
10274 | return TRUE; | |
10275 | } | |
10276 | if (offset_expr.X_op == O_constant | |
10277 | && offset_high_part (offset_expr.X_add_number, offbits) == 0 | |
10278 | && offset_high_part (offset_expr.X_add_number + range, offbits) == 0) | |
10279 | return TRUE; | |
10280 | return FALSE; | |
10281 | } | |
10282 | ||
252b5132 RH |
10283 | /* |
10284 | * Build macros | |
10285 | * This routine implements the seemingly endless macro or synthesized | |
10286 | * instructions and addressing modes in the mips assembly language. Many | |
10287 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 10288 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
10289 | * this verbose method. Others are not simple macros but are more like |
10290 | * optimizing code generation. | |
10291 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 10292 | * consecutively that would load AT with the upper half of the same address. |
2b0f3761 | 10293 | * The ensuing load upper instructions are omitted. This implies some kind |
252b5132 RH |
10294 | * of global optimization. We currently only optimize within a single macro. |
10295 | * For many of the load and store macros if the address is specified as a | |
10296 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
10297 | * first load register 'at' with zero and use it as the base register. The | |
10298 | * mips assembler simply uses register $zero. Just one tiny optimization | |
10299 | * we're missing. | |
10300 | */ | |
10301 | static void | |
833794fc | 10302 | macro (struct mips_cl_insn *ip, char *str) |
252b5132 | 10303 | { |
c0ebe874 RS |
10304 | const struct mips_operand_array *operands; |
10305 | unsigned int breg, i; | |
741fe287 | 10306 | unsigned int tempreg; |
252b5132 | 10307 | int mask; |
43841e91 | 10308 | int used_at = 0; |
df58fc94 | 10309 | expressionS label_expr; |
252b5132 | 10310 | expressionS expr1; |
df58fc94 | 10311 | expressionS *ep; |
252b5132 RH |
10312 | const char *s; |
10313 | const char *s2; | |
10314 | const char *fmt; | |
10315 | int likely = 0; | |
252b5132 | 10316 | int coproc = 0; |
7f3c4072 | 10317 | int offbits = 16; |
1abe91b1 | 10318 | int call = 0; |
df58fc94 RS |
10319 | int jals = 0; |
10320 | int dbl = 0; | |
10321 | int imm = 0; | |
10322 | int ust = 0; | |
10323 | int lp = 0; | |
a45328b9 | 10324 | int ll_sc_paired = 0; |
f2ae14a1 | 10325 | bfd_boolean large_offset; |
252b5132 | 10326 | int off; |
252b5132 | 10327 | int hold_mips_optimize; |
f2ae14a1 | 10328 | unsigned int align; |
c0ebe874 | 10329 | unsigned int op[MAX_OPERANDS]; |
252b5132 | 10330 | |
9c2799c2 | 10331 | gas_assert (! mips_opts.mips16); |
252b5132 | 10332 | |
c0ebe874 RS |
10333 | operands = insn_operands (ip); |
10334 | for (i = 0; i < MAX_OPERANDS; i++) | |
10335 | if (operands->operand[i]) | |
10336 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
10337 | else | |
10338 | op[i] = -1; | |
10339 | ||
252b5132 RH |
10340 | mask = ip->insn_mo->mask; |
10341 | ||
df58fc94 RS |
10342 | label_expr.X_op = O_constant; |
10343 | label_expr.X_op_symbol = NULL; | |
10344 | label_expr.X_add_symbol = NULL; | |
10345 | label_expr.X_add_number = 0; | |
10346 | ||
252b5132 RH |
10347 | expr1.X_op = O_constant; |
10348 | expr1.X_op_symbol = NULL; | |
10349 | expr1.X_add_symbol = NULL; | |
10350 | expr1.X_add_number = 1; | |
f2ae14a1 | 10351 | align = 1; |
252b5132 RH |
10352 | |
10353 | switch (mask) | |
10354 | { | |
10355 | case M_DABS: | |
10356 | dbl = 1; | |
1a0670f3 | 10357 | /* Fall through. */ |
252b5132 | 10358 | case M_ABS: |
df58fc94 RS |
10359 | /* bgez $a0,1f |
10360 | move v0,$a0 | |
10361 | sub v0,$zero,$a0 | |
10362 | 1: | |
10363 | */ | |
252b5132 | 10364 | |
7d10b47d | 10365 | start_noreorder (); |
252b5132 | 10366 | |
df58fc94 RS |
10367 | if (mips_opts.micromips) |
10368 | micromips_label_expr (&label_expr); | |
10369 | else | |
10370 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10371 | macro_build (&label_expr, "bgez", "s,p", op[1]); |
10372 | if (op[0] == op[1]) | |
a605d2b3 | 10373 | macro_build (NULL, "nop", ""); |
252b5132 | 10374 | else |
c0ebe874 RS |
10375 | move_register (op[0], op[1]); |
10376 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]); | |
df58fc94 RS |
10377 | if (mips_opts.micromips) |
10378 | micromips_add_label (); | |
252b5132 | 10379 | |
7d10b47d | 10380 | end_noreorder (); |
8fc2e39e | 10381 | break; |
252b5132 RH |
10382 | |
10383 | case M_ADD_I: | |
10384 | s = "addi"; | |
10385 | s2 = "add"; | |
387e7624 FS |
10386 | if (ISA_IS_R6 (mips_opts.isa)) |
10387 | goto do_addi_i; | |
10388 | else | |
10389 | goto do_addi; | |
252b5132 RH |
10390 | case M_ADDU_I: |
10391 | s = "addiu"; | |
10392 | s2 = "addu"; | |
10393 | goto do_addi; | |
10394 | case M_DADD_I: | |
10395 | dbl = 1; | |
10396 | s = "daddi"; | |
10397 | s2 = "dadd"; | |
387e7624 | 10398 | if (!mips_opts.micromips && !ISA_IS_R6 (mips_opts.isa)) |
df58fc94 | 10399 | goto do_addi; |
b0e6f033 | 10400 | if (imm_expr.X_add_number >= -0x200 |
387e7624 FS |
10401 | && imm_expr.X_add_number < 0x200 |
10402 | && !ISA_IS_R6 (mips_opts.isa)) | |
df58fc94 | 10403 | { |
b0e6f033 RS |
10404 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
10405 | (int) imm_expr.X_add_number); | |
df58fc94 RS |
10406 | break; |
10407 | } | |
10408 | goto do_addi_i; | |
252b5132 RH |
10409 | case M_DADDU_I: |
10410 | dbl = 1; | |
10411 | s = "daddiu"; | |
10412 | s2 = "daddu"; | |
10413 | do_addi: | |
b0e6f033 | 10414 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
10415 | && imm_expr.X_add_number < 0x8000) |
10416 | { | |
c0ebe874 | 10417 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 10418 | break; |
252b5132 | 10419 | } |
df58fc94 | 10420 | do_addi_i: |
8fc2e39e | 10421 | used_at = 1; |
67c0d1eb | 10422 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 10423 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
10424 | break; |
10425 | ||
10426 | case M_AND_I: | |
10427 | s = "andi"; | |
10428 | s2 = "and"; | |
10429 | goto do_bit; | |
10430 | case M_OR_I: | |
10431 | s = "ori"; | |
10432 | s2 = "or"; | |
10433 | goto do_bit; | |
10434 | case M_NOR_I: | |
10435 | s = ""; | |
10436 | s2 = "nor"; | |
10437 | goto do_bit; | |
10438 | case M_XOR_I: | |
10439 | s = "xori"; | |
10440 | s2 = "xor"; | |
10441 | do_bit: | |
b0e6f033 | 10442 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
10443 | && imm_expr.X_add_number < 0x10000) |
10444 | { | |
10445 | if (mask != M_NOR_I) | |
c0ebe874 | 10446 | macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
252b5132 RH |
10447 | else |
10448 | { | |
67c0d1eb | 10449 | macro_build (&imm_expr, "ori", "t,r,i", |
c0ebe874 RS |
10450 | op[0], op[1], BFD_RELOC_LO16); |
10451 | macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0); | |
252b5132 | 10452 | } |
8fc2e39e | 10453 | break; |
252b5132 RH |
10454 | } |
10455 | ||
8fc2e39e | 10456 | used_at = 1; |
bad1aba3 | 10457 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 10458 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
10459 | break; |
10460 | ||
8b082fb1 TS |
10461 | case M_BALIGN: |
10462 | switch (imm_expr.X_add_number) | |
10463 | { | |
10464 | case 0: | |
10465 | macro_build (NULL, "nop", ""); | |
10466 | break; | |
10467 | case 2: | |
c0ebe874 | 10468 | macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]); |
8b082fb1 | 10469 | break; |
03f66e8a MR |
10470 | case 1: |
10471 | case 3: | |
c0ebe874 | 10472 | macro_build (NULL, "balign", "t,s,2", op[0], op[1], |
90ecf173 | 10473 | (int) imm_expr.X_add_number); |
8b082fb1 | 10474 | break; |
03f66e8a MR |
10475 | default: |
10476 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
10477 | (unsigned long) imm_expr.X_add_number); | |
10478 | break; | |
8b082fb1 TS |
10479 | } |
10480 | break; | |
10481 | ||
df58fc94 RS |
10482 | case M_BC1FL: |
10483 | case M_BC1TL: | |
10484 | case M_BC2FL: | |
10485 | case M_BC2TL: | |
10486 | gas_assert (mips_opts.micromips); | |
10487 | macro_build_branch_ccl (mask, &offset_expr, | |
10488 | EXTRACT_OPERAND (1, BCC, *ip)); | |
10489 | break; | |
10490 | ||
252b5132 | 10491 | case M_BEQ_I: |
252b5132 | 10492 | case M_BEQL_I: |
252b5132 | 10493 | case M_BNE_I: |
252b5132 | 10494 | case M_BNEL_I: |
b0e6f033 | 10495 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 10496 | op[1] = 0; |
df58fc94 | 10497 | else |
252b5132 | 10498 | { |
c0ebe874 | 10499 | op[1] = AT; |
df58fc94 | 10500 | used_at = 1; |
bad1aba3 | 10501 | load_register (op[1], &imm_expr, GPR_SIZE == 64); |
252b5132 | 10502 | } |
df58fc94 RS |
10503 | /* Fall through. */ |
10504 | case M_BEQL: | |
10505 | case M_BNEL: | |
c0ebe874 | 10506 | macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]); |
252b5132 RH |
10507 | break; |
10508 | ||
10509 | case M_BGEL: | |
10510 | likely = 1; | |
1a0670f3 | 10511 | /* Fall through. */ |
252b5132 | 10512 | case M_BGE: |
c0ebe874 RS |
10513 | if (op[1] == 0) |
10514 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]); | |
10515 | else if (op[0] == 0) | |
10516 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]); | |
df58fc94 | 10517 | else |
252b5132 | 10518 | { |
df58fc94 | 10519 | used_at = 1; |
c0ebe874 | 10520 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10521 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10522 | &offset_expr, AT, ZERO); | |
252b5132 | 10523 | } |
df58fc94 RS |
10524 | break; |
10525 | ||
10526 | case M_BGEZL: | |
10527 | case M_BGEZALL: | |
10528 | case M_BGTZL: | |
10529 | case M_BLEZL: | |
10530 | case M_BLTZL: | |
10531 | case M_BLTZALL: | |
c0ebe874 | 10532 | macro_build_branch_rs (mask, &offset_expr, op[0]); |
252b5132 RH |
10533 | break; |
10534 | ||
10535 | case M_BGTL_I: | |
10536 | likely = 1; | |
1a0670f3 | 10537 | /* Fall through. */ |
252b5132 | 10538 | case M_BGT_I: |
90ecf173 | 10539 | /* Check for > max integer. */ |
b0e6f033 | 10540 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 RH |
10541 | { |
10542 | do_false: | |
90ecf173 | 10543 | /* Result is always false. */ |
252b5132 | 10544 | if (! likely) |
a605d2b3 | 10545 | macro_build (NULL, "nop", ""); |
252b5132 | 10546 | else |
df58fc94 | 10547 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 10548 | break; |
252b5132 | 10549 | } |
f9419b05 | 10550 | ++imm_expr.X_add_number; |
6f2117ba | 10551 | /* Fall through. */ |
252b5132 RH |
10552 | case M_BGE_I: |
10553 | case M_BGEL_I: | |
10554 | if (mask == M_BGEL_I) | |
10555 | likely = 1; | |
b0e6f033 | 10556 | if (imm_expr.X_add_number == 0) |
252b5132 | 10557 | { |
df58fc94 | 10558 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
c0ebe874 | 10559 | &offset_expr, op[0]); |
8fc2e39e | 10560 | break; |
252b5132 | 10561 | } |
b0e6f033 | 10562 | if (imm_expr.X_add_number == 1) |
252b5132 | 10563 | { |
df58fc94 | 10564 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
c0ebe874 | 10565 | &offset_expr, op[0]); |
8fc2e39e | 10566 | break; |
252b5132 | 10567 | } |
b0e6f033 | 10568 | if (imm_expr.X_add_number <= GPR_SMIN) |
252b5132 RH |
10569 | { |
10570 | do_true: | |
6f2117ba | 10571 | /* Result is always true. */ |
1661c76c | 10572 | as_warn (_("branch %s is always true"), ip->insn_mo->name); |
67c0d1eb | 10573 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 10574 | break; |
252b5132 | 10575 | } |
8fc2e39e | 10576 | used_at = 1; |
c0ebe874 | 10577 | set_at (op[0], 0); |
df58fc94 RS |
10578 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10579 | &offset_expr, AT, ZERO); | |
252b5132 RH |
10580 | break; |
10581 | ||
10582 | case M_BGEUL: | |
10583 | likely = 1; | |
1a0670f3 | 10584 | /* Fall through. */ |
252b5132 | 10585 | case M_BGEU: |
c0ebe874 | 10586 | if (op[1] == 0) |
252b5132 | 10587 | goto do_true; |
c0ebe874 | 10588 | else if (op[0] == 0) |
df58fc94 | 10589 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 10590 | &offset_expr, ZERO, op[1]); |
df58fc94 | 10591 | else |
252b5132 | 10592 | { |
df58fc94 | 10593 | used_at = 1; |
c0ebe874 | 10594 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10595 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10596 | &offset_expr, AT, ZERO); | |
252b5132 | 10597 | } |
252b5132 RH |
10598 | break; |
10599 | ||
10600 | case M_BGTUL_I: | |
10601 | likely = 1; | |
1a0670f3 | 10602 | /* Fall through. */ |
252b5132 | 10603 | case M_BGTU_I: |
c0ebe874 | 10604 | if (op[0] == 0 |
bad1aba3 | 10605 | || (GPR_SIZE == 32 |
f01dc953 | 10606 | && imm_expr.X_add_number == -1)) |
252b5132 | 10607 | goto do_false; |
f9419b05 | 10608 | ++imm_expr.X_add_number; |
6f2117ba | 10609 | /* Fall through. */ |
252b5132 RH |
10610 | case M_BGEU_I: |
10611 | case M_BGEUL_I: | |
10612 | if (mask == M_BGEUL_I) | |
10613 | likely = 1; | |
b0e6f033 | 10614 | if (imm_expr.X_add_number == 0) |
252b5132 | 10615 | goto do_true; |
b0e6f033 | 10616 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 10617 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 10618 | &offset_expr, op[0], ZERO); |
df58fc94 | 10619 | else |
252b5132 | 10620 | { |
df58fc94 | 10621 | used_at = 1; |
c0ebe874 | 10622 | set_at (op[0], 1); |
df58fc94 RS |
10623 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10624 | &offset_expr, AT, ZERO); | |
252b5132 | 10625 | } |
252b5132 RH |
10626 | break; |
10627 | ||
10628 | case M_BGTL: | |
10629 | likely = 1; | |
1a0670f3 | 10630 | /* Fall through. */ |
252b5132 | 10631 | case M_BGT: |
c0ebe874 RS |
10632 | if (op[1] == 0) |
10633 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]); | |
10634 | else if (op[0] == 0) | |
10635 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]); | |
df58fc94 | 10636 | else |
252b5132 | 10637 | { |
df58fc94 | 10638 | used_at = 1; |
c0ebe874 | 10639 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10640 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10641 | &offset_expr, AT, ZERO); | |
252b5132 | 10642 | } |
252b5132 RH |
10643 | break; |
10644 | ||
10645 | case M_BGTUL: | |
10646 | likely = 1; | |
1a0670f3 | 10647 | /* Fall through. */ |
252b5132 | 10648 | case M_BGTU: |
c0ebe874 | 10649 | if (op[1] == 0) |
df58fc94 | 10650 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 RS |
10651 | &offset_expr, op[0], ZERO); |
10652 | else if (op[0] == 0) | |
df58fc94 RS |
10653 | goto do_false; |
10654 | else | |
252b5132 | 10655 | { |
df58fc94 | 10656 | used_at = 1; |
c0ebe874 | 10657 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10658 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10659 | &offset_expr, AT, ZERO); | |
252b5132 | 10660 | } |
252b5132 RH |
10661 | break; |
10662 | ||
10663 | case M_BLEL: | |
10664 | likely = 1; | |
1a0670f3 | 10665 | /* Fall through. */ |
252b5132 | 10666 | case M_BLE: |
c0ebe874 RS |
10667 | if (op[1] == 0) |
10668 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); | |
10669 | else if (op[0] == 0) | |
10670 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]); | |
df58fc94 | 10671 | else |
252b5132 | 10672 | { |
df58fc94 | 10673 | used_at = 1; |
c0ebe874 | 10674 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10675 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10676 | &offset_expr, AT, ZERO); | |
252b5132 | 10677 | } |
252b5132 RH |
10678 | break; |
10679 | ||
10680 | case M_BLEL_I: | |
10681 | likely = 1; | |
1a0670f3 | 10682 | /* Fall through. */ |
252b5132 | 10683 | case M_BLE_I: |
b0e6f033 | 10684 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 | 10685 | goto do_true; |
f9419b05 | 10686 | ++imm_expr.X_add_number; |
6f2117ba | 10687 | /* Fall through. */ |
252b5132 RH |
10688 | case M_BLT_I: |
10689 | case M_BLTL_I: | |
10690 | if (mask == M_BLTL_I) | |
10691 | likely = 1; | |
b0e6f033 | 10692 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 10693 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); |
b0e6f033 | 10694 | else if (imm_expr.X_add_number == 1) |
c0ebe874 | 10695 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); |
df58fc94 | 10696 | else |
252b5132 | 10697 | { |
df58fc94 | 10698 | used_at = 1; |
c0ebe874 | 10699 | set_at (op[0], 0); |
df58fc94 RS |
10700 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10701 | &offset_expr, AT, ZERO); | |
252b5132 | 10702 | } |
252b5132 RH |
10703 | break; |
10704 | ||
10705 | case M_BLEUL: | |
10706 | likely = 1; | |
1a0670f3 | 10707 | /* Fall through. */ |
252b5132 | 10708 | case M_BLEU: |
c0ebe874 | 10709 | if (op[1] == 0) |
df58fc94 | 10710 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 RS |
10711 | &offset_expr, op[0], ZERO); |
10712 | else if (op[0] == 0) | |
df58fc94 RS |
10713 | goto do_true; |
10714 | else | |
252b5132 | 10715 | { |
df58fc94 | 10716 | used_at = 1; |
c0ebe874 | 10717 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10718 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10719 | &offset_expr, AT, ZERO); | |
252b5132 | 10720 | } |
252b5132 RH |
10721 | break; |
10722 | ||
10723 | case M_BLEUL_I: | |
10724 | likely = 1; | |
1a0670f3 | 10725 | /* Fall through. */ |
252b5132 | 10726 | case M_BLEU_I: |
c0ebe874 | 10727 | if (op[0] == 0 |
bad1aba3 | 10728 | || (GPR_SIZE == 32 |
f01dc953 | 10729 | && imm_expr.X_add_number == -1)) |
252b5132 | 10730 | goto do_true; |
f9419b05 | 10731 | ++imm_expr.X_add_number; |
6f2117ba | 10732 | /* Fall through. */ |
252b5132 RH |
10733 | case M_BLTU_I: |
10734 | case M_BLTUL_I: | |
10735 | if (mask == M_BLTUL_I) | |
10736 | likely = 1; | |
b0e6f033 | 10737 | if (imm_expr.X_add_number == 0) |
252b5132 | 10738 | goto do_false; |
b0e6f033 | 10739 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 10740 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 10741 | &offset_expr, op[0], ZERO); |
df58fc94 | 10742 | else |
252b5132 | 10743 | { |
df58fc94 | 10744 | used_at = 1; |
c0ebe874 | 10745 | set_at (op[0], 1); |
df58fc94 RS |
10746 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10747 | &offset_expr, AT, ZERO); | |
252b5132 | 10748 | } |
252b5132 RH |
10749 | break; |
10750 | ||
10751 | case M_BLTL: | |
10752 | likely = 1; | |
1a0670f3 | 10753 | /* Fall through. */ |
252b5132 | 10754 | case M_BLT: |
c0ebe874 RS |
10755 | if (op[1] == 0) |
10756 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); | |
10757 | else if (op[0] == 0) | |
10758 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]); | |
df58fc94 | 10759 | else |
252b5132 | 10760 | { |
df58fc94 | 10761 | used_at = 1; |
c0ebe874 | 10762 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10763 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10764 | &offset_expr, AT, ZERO); | |
252b5132 | 10765 | } |
252b5132 RH |
10766 | break; |
10767 | ||
10768 | case M_BLTUL: | |
10769 | likely = 1; | |
1a0670f3 | 10770 | /* Fall through. */ |
252b5132 | 10771 | case M_BLTU: |
c0ebe874 | 10772 | if (op[1] == 0) |
252b5132 | 10773 | goto do_false; |
c0ebe874 | 10774 | else if (op[0] == 0) |
df58fc94 | 10775 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 10776 | &offset_expr, ZERO, op[1]); |
df58fc94 | 10777 | else |
252b5132 | 10778 | { |
df58fc94 | 10779 | used_at = 1; |
c0ebe874 | 10780 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10781 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10782 | &offset_expr, AT, ZERO); | |
252b5132 | 10783 | } |
252b5132 RH |
10784 | break; |
10785 | ||
10786 | case M_DDIV_3: | |
10787 | dbl = 1; | |
1a0670f3 | 10788 | /* Fall through. */ |
252b5132 RH |
10789 | case M_DIV_3: |
10790 | s = "mflo"; | |
10791 | goto do_div3; | |
10792 | case M_DREM_3: | |
10793 | dbl = 1; | |
1a0670f3 | 10794 | /* Fall through. */ |
252b5132 RH |
10795 | case M_REM_3: |
10796 | s = "mfhi"; | |
10797 | do_div3: | |
c0ebe874 | 10798 | if (op[2] == 0) |
252b5132 | 10799 | { |
1661c76c | 10800 | as_warn (_("divide by zero")); |
252b5132 | 10801 | if (mips_trap) |
df58fc94 | 10802 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 10803 | else |
df58fc94 | 10804 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 10805 | break; |
252b5132 RH |
10806 | } |
10807 | ||
7d10b47d | 10808 | start_noreorder (); |
252b5132 RH |
10809 | if (mips_trap) |
10810 | { | |
c0ebe874 RS |
10811 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
10812 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
252b5132 RH |
10813 | } |
10814 | else | |
10815 | { | |
df58fc94 RS |
10816 | if (mips_opts.micromips) |
10817 | micromips_label_expr (&label_expr); | |
10818 | else | |
10819 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10820 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
10821 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
df58fc94 RS |
10822 | macro_build (NULL, "break", BRK_FMT, 7); |
10823 | if (mips_opts.micromips) | |
10824 | micromips_add_label (); | |
252b5132 RH |
10825 | } |
10826 | expr1.X_add_number = -1; | |
8fc2e39e | 10827 | used_at = 1; |
f6a22291 | 10828 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
10829 | if (mips_opts.micromips) |
10830 | micromips_label_expr (&label_expr); | |
10831 | else | |
10832 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
c0ebe874 | 10833 | macro_build (&label_expr, "bne", "s,t,p", op[2], AT); |
252b5132 RH |
10834 | if (dbl) |
10835 | { | |
10836 | expr1.X_add_number = 1; | |
f6a22291 | 10837 | load_register (AT, &expr1, dbl); |
df58fc94 | 10838 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
10839 | } |
10840 | else | |
10841 | { | |
10842 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 10843 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
10844 | } |
10845 | if (mips_trap) | |
10846 | { | |
c0ebe874 | 10847 | macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6); |
252b5132 RH |
10848 | /* We want to close the noreorder block as soon as possible, so |
10849 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10850 | end_noreorder (); |
252b5132 RH |
10851 | } |
10852 | else | |
10853 | { | |
df58fc94 RS |
10854 | if (mips_opts.micromips) |
10855 | micromips_label_expr (&label_expr); | |
10856 | else | |
10857 | label_expr.X_add_number = 8; | |
c0ebe874 | 10858 | macro_build (&label_expr, "bne", "s,t,p", op[1], AT); |
a605d2b3 | 10859 | macro_build (NULL, "nop", ""); |
252b5132 RH |
10860 | |
10861 | /* We want to close the noreorder block as soon as possible, so | |
10862 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10863 | end_noreorder (); |
252b5132 | 10864 | |
df58fc94 | 10865 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 10866 | } |
df58fc94 RS |
10867 | if (mips_opts.micromips) |
10868 | micromips_add_label (); | |
c0ebe874 | 10869 | macro_build (NULL, s, MFHL_FMT, op[0]); |
252b5132 RH |
10870 | break; |
10871 | ||
10872 | case M_DIV_3I: | |
10873 | s = "div"; | |
10874 | s2 = "mflo"; | |
10875 | goto do_divi; | |
10876 | case M_DIVU_3I: | |
10877 | s = "divu"; | |
10878 | s2 = "mflo"; | |
10879 | goto do_divi; | |
10880 | case M_REM_3I: | |
10881 | s = "div"; | |
10882 | s2 = "mfhi"; | |
10883 | goto do_divi; | |
10884 | case M_REMU_3I: | |
10885 | s = "divu"; | |
10886 | s2 = "mfhi"; | |
10887 | goto do_divi; | |
10888 | case M_DDIV_3I: | |
10889 | dbl = 1; | |
10890 | s = "ddiv"; | |
10891 | s2 = "mflo"; | |
10892 | goto do_divi; | |
10893 | case M_DDIVU_3I: | |
10894 | dbl = 1; | |
10895 | s = "ddivu"; | |
10896 | s2 = "mflo"; | |
10897 | goto do_divi; | |
10898 | case M_DREM_3I: | |
10899 | dbl = 1; | |
10900 | s = "ddiv"; | |
10901 | s2 = "mfhi"; | |
10902 | goto do_divi; | |
10903 | case M_DREMU_3I: | |
10904 | dbl = 1; | |
10905 | s = "ddivu"; | |
10906 | s2 = "mfhi"; | |
10907 | do_divi: | |
b0e6f033 | 10908 | if (imm_expr.X_add_number == 0) |
252b5132 | 10909 | { |
1661c76c | 10910 | as_warn (_("divide by zero")); |
252b5132 | 10911 | if (mips_trap) |
df58fc94 | 10912 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 10913 | else |
df58fc94 | 10914 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 10915 | break; |
252b5132 | 10916 | } |
b0e6f033 | 10917 | if (imm_expr.X_add_number == 1) |
252b5132 RH |
10918 | { |
10919 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 10920 | move_register (op[0], op[1]); |
252b5132 | 10921 | else |
c0ebe874 | 10922 | move_register (op[0], ZERO); |
8fc2e39e | 10923 | break; |
252b5132 | 10924 | } |
b0e6f033 | 10925 | if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u') |
252b5132 RH |
10926 | { |
10927 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 10928 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]); |
252b5132 | 10929 | else |
c0ebe874 | 10930 | move_register (op[0], ZERO); |
8fc2e39e | 10931 | break; |
252b5132 RH |
10932 | } |
10933 | ||
8fc2e39e | 10934 | used_at = 1; |
67c0d1eb | 10935 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
10936 | macro_build (NULL, s, "z,s,t", op[1], AT); |
10937 | macro_build (NULL, s2, MFHL_FMT, op[0]); | |
252b5132 RH |
10938 | break; |
10939 | ||
10940 | case M_DIVU_3: | |
10941 | s = "divu"; | |
10942 | s2 = "mflo"; | |
10943 | goto do_divu3; | |
10944 | case M_REMU_3: | |
10945 | s = "divu"; | |
10946 | s2 = "mfhi"; | |
10947 | goto do_divu3; | |
10948 | case M_DDIVU_3: | |
10949 | s = "ddivu"; | |
10950 | s2 = "mflo"; | |
10951 | goto do_divu3; | |
10952 | case M_DREMU_3: | |
10953 | s = "ddivu"; | |
10954 | s2 = "mfhi"; | |
10955 | do_divu3: | |
7d10b47d | 10956 | start_noreorder (); |
252b5132 RH |
10957 | if (mips_trap) |
10958 | { | |
c0ebe874 RS |
10959 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
10960 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
10961 | /* We want to close the noreorder block as soon as possible, so |
10962 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10963 | end_noreorder (); |
252b5132 RH |
10964 | } |
10965 | else | |
10966 | { | |
df58fc94 RS |
10967 | if (mips_opts.micromips) |
10968 | micromips_label_expr (&label_expr); | |
10969 | else | |
10970 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10971 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
10972 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
10973 | |
10974 | /* We want to close the noreorder block as soon as possible, so | |
10975 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10976 | end_noreorder (); |
df58fc94 RS |
10977 | macro_build (NULL, "break", BRK_FMT, 7); |
10978 | if (mips_opts.micromips) | |
10979 | micromips_add_label (); | |
252b5132 | 10980 | } |
c0ebe874 | 10981 | macro_build (NULL, s2, MFHL_FMT, op[0]); |
8fc2e39e | 10982 | break; |
252b5132 | 10983 | |
1abe91b1 MR |
10984 | case M_DLCA_AB: |
10985 | dbl = 1; | |
1a0670f3 | 10986 | /* Fall through. */ |
1abe91b1 MR |
10987 | case M_LCA_AB: |
10988 | call = 1; | |
10989 | goto do_la; | |
252b5132 RH |
10990 | case M_DLA_AB: |
10991 | dbl = 1; | |
1a0670f3 | 10992 | /* Fall through. */ |
252b5132 | 10993 | case M_LA_AB: |
1abe91b1 | 10994 | do_la: |
252b5132 RH |
10995 | /* Load the address of a symbol into a register. If breg is not |
10996 | zero, we then add a base register to it. */ | |
10997 | ||
c0ebe874 | 10998 | breg = op[2]; |
bad1aba3 | 10999 | if (dbl && GPR_SIZE == 32) |
ece794d9 MF |
11000 | as_warn (_("dla used to load 32-bit register; recommend using la " |
11001 | "instead")); | |
3bec30a8 | 11002 | |
90ecf173 | 11003 | if (!dbl && HAVE_64BIT_OBJECTS) |
ece794d9 MF |
11004 | as_warn (_("la used to load 64-bit address; recommend using dla " |
11005 | "instead")); | |
3bec30a8 | 11006 | |
f2ae14a1 | 11007 | if (small_offset_p (0, align, 16)) |
0c11417f | 11008 | { |
c0ebe874 | 11009 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg, |
f2ae14a1 | 11010 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); |
8fc2e39e | 11011 | break; |
0c11417f MR |
11012 | } |
11013 | ||
c0ebe874 | 11014 | if (mips_opts.at && (op[0] == breg)) |
afdbd6d0 CD |
11015 | { |
11016 | tempreg = AT; | |
11017 | used_at = 1; | |
11018 | } | |
11019 | else | |
c0ebe874 | 11020 | tempreg = op[0]; |
afdbd6d0 | 11021 | |
252b5132 RH |
11022 | if (offset_expr.X_op != O_symbol |
11023 | && offset_expr.X_op != O_constant) | |
11024 | { | |
1661c76c | 11025 | as_bad (_("expression too complex")); |
252b5132 RH |
11026 | offset_expr.X_op = O_constant; |
11027 | } | |
11028 | ||
252b5132 | 11029 | if (offset_expr.X_op == O_constant) |
aed1a261 | 11030 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
11031 | else if (mips_pic == NO_PIC) |
11032 | { | |
d6bc6245 | 11033 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 11034 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
11035 | Otherwise we want |
11036 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
11037 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
11038 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 11039 | so we may as well always use the latter form. |
76b3015f | 11040 | |
6caf9ef4 TS |
11041 | With 64bit address space and a usable $at we want |
11042 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
11043 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
11044 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
11045 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
11046 | dsll32 $tempreg,0 | |
11047 | daddu $tempreg,$tempreg,$at | |
11048 | ||
11049 | If $at is already in use, we use a path which is suboptimal | |
11050 | on superscalar processors. | |
11051 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
11052 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
11053 | dsll $tempreg,16 | |
11054 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
11055 | dsll $tempreg,16 | |
11056 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
11057 | ||
11058 | For GP relative symbols in 64bit address space we can use | |
11059 | the same sequence as in 32bit address space. */ | |
aed1a261 | 11060 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 11061 | { |
6caf9ef4 TS |
11062 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
11063 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
11064 | { | |
11065 | relax_start (offset_expr.X_add_symbol); | |
11066 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11067 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
11068 | relax_switch (); | |
11069 | } | |
d6bc6245 | 11070 | |
741fe287 | 11071 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 11072 | { |
df58fc94 | 11073 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 11074 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 11075 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 11076 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 11077 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 11078 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 11079 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 11080 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 11081 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 11082 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
11083 | used_at = 1; |
11084 | } | |
11085 | else | |
11086 | { | |
df58fc94 | 11087 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 11088 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 11089 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 11090 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 11091 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 11092 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 11093 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 11094 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 11095 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 11096 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 11097 | } |
6caf9ef4 TS |
11098 | |
11099 | if (mips_relax.sequence) | |
11100 | relax_end (); | |
98d3f06f KH |
11101 | } |
11102 | else | |
11103 | { | |
11104 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 11105 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 11106 | { |
4d7206a2 | 11107 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11108 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11109 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 11110 | relax_switch (); |
98d3f06f | 11111 | } |
6943caf0 | 11112 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
1661c76c | 11113 | as_bad (_("offset too large")); |
67c0d1eb RS |
11114 | macro_build_lui (&offset_expr, tempreg); |
11115 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11116 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
11117 | if (mips_relax.sequence) |
11118 | relax_end (); | |
98d3f06f | 11119 | } |
252b5132 | 11120 | } |
0a44bf69 | 11121 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 11122 | { |
9117d219 NC |
11123 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
11124 | ||
252b5132 RH |
11125 | /* If this is a reference to an external symbol, and there |
11126 | is no constant, we want | |
11127 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 11128 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 11129 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
11130 | For a local symbol, we want |
11131 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11132 | nop | |
11133 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
11134 | ||
11135 | If we have a small constant, and this is a reference to | |
11136 | an external symbol, we want | |
11137 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11138 | nop | |
11139 | addiu $tempreg,$tempreg,<constant> | |
11140 | For a local symbol, we want the same instruction | |
11141 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
11142 | addiu instruction. | |
11143 | ||
11144 | If we have a large constant, and this is a reference to | |
11145 | an external symbol, we want | |
11146 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11147 | lui $at,<hiconstant> | |
11148 | addiu $at,$at,<loconstant> | |
11149 | addu $tempreg,$tempreg,$at | |
11150 | For a local symbol, we want the same instruction | |
11151 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 11152 | addiu instruction. |
ed6fb7bd SC |
11153 | */ |
11154 | ||
4d7206a2 | 11155 | if (offset_expr.X_add_number == 0) |
252b5132 | 11156 | { |
0a44bf69 RS |
11157 | if (mips_pic == SVR4_PIC |
11158 | && breg == 0 | |
11159 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
11160 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
11161 | ||
11162 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
11163 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11164 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 11165 | if (breg != 0) |
252b5132 RH |
11166 | { |
11167 | /* We're going to put in an addu instruction using | |
11168 | tempreg, so we may as well insert the nop right | |
11169 | now. */ | |
269137b2 | 11170 | load_delay_nop (); |
252b5132 | 11171 | } |
4d7206a2 | 11172 | relax_switch (); |
67c0d1eb RS |
11173 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11174 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 11175 | load_delay_nop (); |
67c0d1eb RS |
11176 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11177 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 11178 | relax_end (); |
252b5132 RH |
11179 | /* FIXME: If breg == 0, and the next instruction uses |
11180 | $tempreg, then if this variant case is used an extra | |
11181 | nop will be generated. */ | |
11182 | } | |
4d7206a2 RS |
11183 | else if (offset_expr.X_add_number >= -0x8000 |
11184 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 11185 | { |
67c0d1eb | 11186 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 11187 | load_delay_nop (); |
67c0d1eb | 11188 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
11189 | } |
11190 | else | |
11191 | { | |
4d7206a2 RS |
11192 | expr1.X_add_number = offset_expr.X_add_number; |
11193 | offset_expr.X_add_number = | |
43c0598f | 11194 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 11195 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 11196 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
11197 | /* If we are going to add in a base register, and the |
11198 | target register and the base register are the same, | |
11199 | then we are using AT as a temporary register. Since | |
11200 | we want to load the constant into AT, we add our | |
11201 | current AT (from the global offset table) and the | |
11202 | register into the register now, and pretend we were | |
11203 | not using a base register. */ | |
c0ebe874 | 11204 | if (breg == op[0]) |
252b5132 | 11205 | { |
269137b2 | 11206 | load_delay_nop (); |
67c0d1eb | 11207 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11208 | op[0], AT, breg); |
252b5132 | 11209 | breg = 0; |
c0ebe874 | 11210 | tempreg = op[0]; |
252b5132 | 11211 | } |
f6a22291 | 11212 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
11213 | used_at = 1; |
11214 | } | |
11215 | } | |
0a44bf69 | 11216 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 11217 | { |
67c0d1eb | 11218 | int add_breg_early = 0; |
f5040a92 AO |
11219 | |
11220 | /* If this is a reference to an external, and there is no | |
11221 | constant, or local symbol (*), with or without a | |
11222 | constant, we want | |
11223 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 11224 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
11225 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
11226 | ||
11227 | If we have a small constant, and this is a reference to | |
11228 | an external symbol, we want | |
11229 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
11230 | addiu $tempreg,$tempreg,<constant> | |
11231 | ||
11232 | If we have a large constant, and this is a reference to | |
11233 | an external symbol, we want | |
11234 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
11235 | lui $at,<hiconstant> | |
11236 | addiu $at,$at,<loconstant> | |
11237 | addu $tempreg,$tempreg,$at | |
11238 | ||
11239 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
11240 | local symbols, even though it introduces an additional | |
11241 | instruction. */ | |
11242 | ||
f5040a92 AO |
11243 | if (offset_expr.X_add_number) |
11244 | { | |
4d7206a2 | 11245 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
11246 | offset_expr.X_add_number = 0; |
11247 | ||
4d7206a2 | 11248 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11249 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11250 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
11251 | |
11252 | if (expr1.X_add_number >= -0x8000 | |
11253 | && expr1.X_add_number < 0x8000) | |
11254 | { | |
67c0d1eb RS |
11255 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
11256 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 11257 | } |
ecd13cd3 | 11258 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 11259 | { |
c0ebe874 RS |
11260 | unsigned int dreg; |
11261 | ||
f5040a92 AO |
11262 | /* If we are going to add in a base register, and the |
11263 | target register and the base register are the same, | |
11264 | then we are using AT as a temporary register. Since | |
11265 | we want to load the constant into AT, we add our | |
11266 | current AT (from the global offset table) and the | |
11267 | register into the register now, and pretend we were | |
11268 | not using a base register. */ | |
c0ebe874 | 11269 | if (breg != op[0]) |
f5040a92 AO |
11270 | dreg = tempreg; |
11271 | else | |
11272 | { | |
9c2799c2 | 11273 | gas_assert (tempreg == AT); |
67c0d1eb | 11274 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11275 | op[0], AT, breg); |
11276 | dreg = op[0]; | |
67c0d1eb | 11277 | add_breg_early = 1; |
f5040a92 AO |
11278 | } |
11279 | ||
f6a22291 | 11280 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11281 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11282 | dreg, dreg, AT); |
f5040a92 | 11283 | |
f5040a92 AO |
11284 | used_at = 1; |
11285 | } | |
11286 | else | |
11287 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
11288 | ||
4d7206a2 | 11289 | relax_switch (); |
f5040a92 AO |
11290 | offset_expr.X_add_number = expr1.X_add_number; |
11291 | ||
67c0d1eb RS |
11292 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11293 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
11294 | if (add_breg_early) | |
f5040a92 | 11295 | { |
67c0d1eb | 11296 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11297 | op[0], tempreg, breg); |
f5040a92 | 11298 | breg = 0; |
c0ebe874 | 11299 | tempreg = op[0]; |
f5040a92 | 11300 | } |
4d7206a2 | 11301 | relax_end (); |
f5040a92 | 11302 | } |
4d7206a2 | 11303 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 11304 | { |
4d7206a2 | 11305 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11306 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11307 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 11308 | relax_switch (); |
67c0d1eb RS |
11309 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11310 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 11311 | relax_end (); |
f5040a92 | 11312 | } |
4d7206a2 | 11313 | else |
f5040a92 | 11314 | { |
67c0d1eb RS |
11315 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11316 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
11317 | } |
11318 | } | |
0a44bf69 | 11319 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 11320 | { |
67c0d1eb | 11321 | int gpdelay; |
9117d219 NC |
11322 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
11323 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 11324 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
11325 | |
11326 | /* This is the large GOT case. If this is a reference to an | |
11327 | external symbol, and there is no constant, we want | |
11328 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11329 | addu $tempreg,$tempreg,$gp | |
11330 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 11331 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
11332 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
11333 | addu $tempreg,$tempreg,$gp | |
11334 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
11335 | For a local symbol, we want |
11336 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11337 | nop | |
11338 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
11339 | ||
11340 | If we have a small constant, and this is a reference to | |
11341 | an external symbol, we want | |
11342 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11343 | addu $tempreg,$tempreg,$gp | |
11344 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11345 | nop | |
11346 | addiu $tempreg,$tempreg,<constant> | |
11347 | For a local symbol, we want | |
11348 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11349 | nop | |
11350 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
11351 | ||
11352 | If we have a large constant, and this is a reference to | |
11353 | an external symbol, we want | |
11354 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11355 | addu $tempreg,$tempreg,$gp | |
11356 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11357 | lui $at,<hiconstant> | |
11358 | addiu $at,$at,<loconstant> | |
11359 | addu $tempreg,$tempreg,$at | |
11360 | For a local symbol, we want | |
11361 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11362 | lui $at,<hiconstant> | |
11363 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
11364 | addu $tempreg,$tempreg,$at | |
f5040a92 | 11365 | */ |
438c16b8 | 11366 | |
252b5132 RH |
11367 | expr1.X_add_number = offset_expr.X_add_number; |
11368 | offset_expr.X_add_number = 0; | |
4d7206a2 | 11369 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 11370 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
11371 | if (expr1.X_add_number == 0 && breg == 0 |
11372 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
11373 | { |
11374 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
11375 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
11376 | } | |
df58fc94 | 11377 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 11378 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11379 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 11380 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 11381 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
11382 | if (expr1.X_add_number == 0) |
11383 | { | |
67c0d1eb | 11384 | if (breg != 0) |
252b5132 RH |
11385 | { |
11386 | /* We're going to put in an addu instruction using | |
11387 | tempreg, so we may as well insert the nop right | |
11388 | now. */ | |
269137b2 | 11389 | load_delay_nop (); |
252b5132 | 11390 | } |
252b5132 RH |
11391 | } |
11392 | else if (expr1.X_add_number >= -0x8000 | |
11393 | && expr1.X_add_number < 0x8000) | |
11394 | { | |
269137b2 | 11395 | load_delay_nop (); |
67c0d1eb | 11396 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 11397 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
11398 | } |
11399 | else | |
11400 | { | |
c0ebe874 RS |
11401 | unsigned int dreg; |
11402 | ||
252b5132 RH |
11403 | /* If we are going to add in a base register, and the |
11404 | target register and the base register are the same, | |
11405 | then we are using AT as a temporary register. Since | |
11406 | we want to load the constant into AT, we add our | |
11407 | current AT (from the global offset table) and the | |
11408 | register into the register now, and pretend we were | |
11409 | not using a base register. */ | |
c0ebe874 | 11410 | if (breg != op[0]) |
67c0d1eb | 11411 | dreg = tempreg; |
252b5132 RH |
11412 | else |
11413 | { | |
9c2799c2 | 11414 | gas_assert (tempreg == AT); |
269137b2 | 11415 | load_delay_nop (); |
67c0d1eb | 11416 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11417 | op[0], AT, breg); |
11418 | dreg = op[0]; | |
252b5132 RH |
11419 | } |
11420 | ||
f6a22291 | 11421 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11422 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 11423 | |
252b5132 RH |
11424 | used_at = 1; |
11425 | } | |
43c0598f | 11426 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 11427 | relax_switch (); |
252b5132 | 11428 | |
67c0d1eb | 11429 | if (gpdelay) |
252b5132 RH |
11430 | { |
11431 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 11432 | the first instruction on the main stream does not. */ |
67c0d1eb | 11433 | macro_build (NULL, "nop", ""); |
252b5132 | 11434 | } |
ed6fb7bd | 11435 | |
67c0d1eb RS |
11436 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11437 | local_reloc_type, mips_gp_register); | |
f5040a92 | 11438 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
11439 | && expr1.X_add_number < 0x8000) |
11440 | { | |
269137b2 | 11441 | load_delay_nop (); |
67c0d1eb RS |
11442 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11443 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 11444 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
11445 | register, the external symbol case ended with a load, |
11446 | so if the symbol turns out to not be external, and | |
11447 | the next instruction uses tempreg, an unnecessary nop | |
11448 | will be inserted. */ | |
252b5132 RH |
11449 | } |
11450 | else | |
11451 | { | |
c0ebe874 | 11452 | if (breg == op[0]) |
252b5132 RH |
11453 | { |
11454 | /* We must add in the base register now, as in the | |
f5040a92 | 11455 | external symbol case. */ |
9c2799c2 | 11456 | gas_assert (tempreg == AT); |
269137b2 | 11457 | load_delay_nop (); |
67c0d1eb | 11458 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11459 | op[0], AT, breg); |
11460 | tempreg = op[0]; | |
252b5132 | 11461 | /* We set breg to 0 because we have arranged to add |
f5040a92 | 11462 | it in in both cases. */ |
252b5132 RH |
11463 | breg = 0; |
11464 | } | |
11465 | ||
67c0d1eb RS |
11466 | macro_build_lui (&expr1, AT); |
11467 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 11468 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 11469 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11470 | tempreg, tempreg, AT); |
8fc2e39e | 11471 | used_at = 1; |
252b5132 | 11472 | } |
4d7206a2 | 11473 | relax_end (); |
252b5132 | 11474 | } |
0a44bf69 | 11475 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 11476 | { |
f5040a92 AO |
11477 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
11478 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 11479 | int add_breg_early = 0; |
f5040a92 AO |
11480 | |
11481 | /* This is the large GOT case. If this is a reference to an | |
11482 | external symbol, and there is no constant, we want | |
11483 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11484 | add $tempreg,$tempreg,$gp | |
11485 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 11486 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
11487 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
11488 | add $tempreg,$tempreg,$gp | |
11489 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
11490 | ||
11491 | If we have a small constant, and this is a reference to | |
11492 | an external symbol, we want | |
11493 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11494 | add $tempreg,$tempreg,$gp | |
11495 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11496 | addi $tempreg,$tempreg,<constant> | |
11497 | ||
11498 | If we have a large constant, and this is a reference to | |
11499 | an external symbol, we want | |
11500 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11501 | addu $tempreg,$tempreg,$gp | |
11502 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11503 | lui $at,<hiconstant> | |
11504 | addi $at,$at,<loconstant> | |
11505 | add $tempreg,$tempreg,$at | |
11506 | ||
11507 | If we have NewABI, and we know it's a local symbol, we want | |
11508 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
11509 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
11510 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
11511 | ||
4d7206a2 | 11512 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 11513 | |
4d7206a2 | 11514 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
11515 | offset_expr.X_add_number = 0; |
11516 | ||
1abe91b1 MR |
11517 | if (expr1.X_add_number == 0 && breg == 0 |
11518 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
11519 | { |
11520 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
11521 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
11522 | } | |
df58fc94 | 11523 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 11524 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11525 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
11526 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11527 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
11528 | |
11529 | if (expr1.X_add_number == 0) | |
4d7206a2 | 11530 | ; |
f5040a92 AO |
11531 | else if (expr1.X_add_number >= -0x8000 |
11532 | && expr1.X_add_number < 0x8000) | |
11533 | { | |
67c0d1eb | 11534 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 11535 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 11536 | } |
ecd13cd3 | 11537 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 11538 | { |
c0ebe874 RS |
11539 | unsigned int dreg; |
11540 | ||
f5040a92 AO |
11541 | /* If we are going to add in a base register, and the |
11542 | target register and the base register are the same, | |
11543 | then we are using AT as a temporary register. Since | |
11544 | we want to load the constant into AT, we add our | |
11545 | current AT (from the global offset table) and the | |
11546 | register into the register now, and pretend we were | |
11547 | not using a base register. */ | |
c0ebe874 | 11548 | if (breg != op[0]) |
f5040a92 AO |
11549 | dreg = tempreg; |
11550 | else | |
11551 | { | |
9c2799c2 | 11552 | gas_assert (tempreg == AT); |
67c0d1eb | 11553 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11554 | op[0], AT, breg); |
11555 | dreg = op[0]; | |
67c0d1eb | 11556 | add_breg_early = 1; |
f5040a92 AO |
11557 | } |
11558 | ||
f6a22291 | 11559 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11560 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 11561 | |
f5040a92 AO |
11562 | used_at = 1; |
11563 | } | |
11564 | else | |
11565 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
11566 | ||
4d7206a2 | 11567 | relax_switch (); |
f5040a92 | 11568 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
11569 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11570 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
11571 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
11572 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
11573 | if (add_breg_early) | |
f5040a92 | 11574 | { |
67c0d1eb | 11575 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11576 | op[0], tempreg, breg); |
f5040a92 | 11577 | breg = 0; |
c0ebe874 | 11578 | tempreg = op[0]; |
f5040a92 | 11579 | } |
4d7206a2 | 11580 | relax_end (); |
f5040a92 | 11581 | } |
252b5132 RH |
11582 | else |
11583 | abort (); | |
11584 | ||
11585 | if (breg != 0) | |
c0ebe874 | 11586 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg); |
252b5132 RH |
11587 | break; |
11588 | ||
52b6b6b9 | 11589 | case M_MSGSND: |
df58fc94 | 11590 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11591 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01); |
c7af4273 | 11592 | break; |
52b6b6b9 JM |
11593 | |
11594 | case M_MSGLD: | |
df58fc94 | 11595 | gas_assert (!mips_opts.micromips); |
c8276761 | 11596 | macro_build (NULL, "c2", "C", 0x02); |
c7af4273 | 11597 | break; |
52b6b6b9 JM |
11598 | |
11599 | case M_MSGLD_T: | |
df58fc94 | 11600 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11601 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02); |
c7af4273 | 11602 | break; |
52b6b6b9 JM |
11603 | |
11604 | case M_MSGWAIT: | |
df58fc94 | 11605 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 11606 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 11607 | break; |
52b6b6b9 JM |
11608 | |
11609 | case M_MSGWAIT_T: | |
df58fc94 | 11610 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11611 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03); |
c7af4273 | 11612 | break; |
52b6b6b9 | 11613 | |
252b5132 RH |
11614 | case M_J_A: |
11615 | /* The j instruction may not be used in PIC code, since it | |
11616 | requires an absolute address. We convert it to a b | |
11617 | instruction. */ | |
11618 | if (mips_pic == NO_PIC) | |
67c0d1eb | 11619 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 11620 | else |
67c0d1eb | 11621 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 11622 | break; |
252b5132 RH |
11623 | |
11624 | /* The jal instructions must be handled as macros because when | |
11625 | generating PIC code they expand to multi-instruction | |
11626 | sequences. Normally they are simple instructions. */ | |
df58fc94 | 11627 | case M_JALS_1: |
c0ebe874 RS |
11628 | op[1] = op[0]; |
11629 | op[0] = RA; | |
df58fc94 RS |
11630 | /* Fall through. */ |
11631 | case M_JALS_2: | |
11632 | gas_assert (mips_opts.micromips); | |
833794fc MR |
11633 | if (mips_opts.insn32) |
11634 | { | |
1661c76c | 11635 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
11636 | break; |
11637 | } | |
df58fc94 RS |
11638 | jals = 1; |
11639 | goto jal; | |
252b5132 | 11640 | case M_JAL_1: |
c0ebe874 RS |
11641 | op[1] = op[0]; |
11642 | op[0] = RA; | |
252b5132 RH |
11643 | /* Fall through. */ |
11644 | case M_JAL_2: | |
df58fc94 | 11645 | jal: |
3e722fb5 | 11646 | if (mips_pic == NO_PIC) |
df58fc94 RS |
11647 | { |
11648 | s = jals ? "jalrs" : "jalr"; | |
e64af278 | 11649 | if (mips_opts.micromips |
833794fc | 11650 | && !mips_opts.insn32 |
c0ebe874 | 11651 | && op[0] == RA |
e64af278 | 11652 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 11653 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 11654 | else |
c0ebe874 | 11655 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
df58fc94 | 11656 | } |
0a44bf69 | 11657 | else |
252b5132 | 11658 | { |
df58fc94 RS |
11659 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
11660 | && mips_cprestore_offset >= 0); | |
11661 | ||
c0ebe874 | 11662 | if (op[1] != PIC_CALL_REG) |
252b5132 | 11663 | as_warn (_("MIPS PIC call to register other than $25")); |
bdaaa2e1 | 11664 | |
833794fc MR |
11665 | s = ((mips_opts.micromips |
11666 | && !mips_opts.insn32 | |
11667 | && (!mips_opts.noreorder || cprestore)) | |
df58fc94 | 11668 | ? "jalrs" : "jalr"); |
e64af278 | 11669 | if (mips_opts.micromips |
833794fc | 11670 | && !mips_opts.insn32 |
c0ebe874 | 11671 | && op[0] == RA |
e64af278 | 11672 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 11673 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 11674 | else |
c0ebe874 | 11675 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
0a44bf69 | 11676 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 11677 | { |
6478892d | 11678 | if (mips_cprestore_offset < 0) |
1661c76c | 11679 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
11680 | else |
11681 | { | |
90ecf173 | 11682 | if (!mips_frame_reg_valid) |
7a621144 | 11683 | { |
1661c76c | 11684 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
11685 | /* Quiet this warning. */ |
11686 | mips_frame_reg_valid = 1; | |
11687 | } | |
90ecf173 | 11688 | if (!mips_cprestore_valid) |
7a621144 | 11689 | { |
1661c76c | 11690 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
11691 | /* Quiet this warning. */ |
11692 | mips_cprestore_valid = 1; | |
11693 | } | |
d3fca0b5 MR |
11694 | if (mips_opts.noreorder) |
11695 | macro_build (NULL, "nop", ""); | |
6478892d | 11696 | expr1.X_add_number = mips_cprestore_offset; |
134c0c8b | 11697 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 11698 | mips_gp_register, |
256ab948 TS |
11699 | mips_frame_reg, |
11700 | HAVE_64BIT_ADDRESSES); | |
6478892d | 11701 | } |
252b5132 RH |
11702 | } |
11703 | } | |
252b5132 | 11704 | |
8fc2e39e | 11705 | break; |
252b5132 | 11706 | |
df58fc94 RS |
11707 | case M_JALS_A: |
11708 | gas_assert (mips_opts.micromips); | |
833794fc MR |
11709 | if (mips_opts.insn32) |
11710 | { | |
1661c76c | 11711 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
11712 | break; |
11713 | } | |
df58fc94 RS |
11714 | jals = 1; |
11715 | /* Fall through. */ | |
252b5132 RH |
11716 | case M_JAL_A: |
11717 | if (mips_pic == NO_PIC) | |
df58fc94 | 11718 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
11719 | else if (mips_pic == SVR4_PIC) |
11720 | { | |
11721 | /* If this is a reference to an external symbol, and we are | |
11722 | using a small GOT, we want | |
11723 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
11724 | nop | |
f9419b05 | 11725 | jalr $ra,$25 |
252b5132 RH |
11726 | nop |
11727 | lw $gp,cprestore($sp) | |
11728 | The cprestore value is set using the .cprestore | |
11729 | pseudo-op. If we are using a big GOT, we want | |
11730 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
11731 | addu $25,$25,$gp | |
11732 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
11733 | nop | |
f9419b05 | 11734 | jalr $ra,$25 |
252b5132 RH |
11735 | nop |
11736 | lw $gp,cprestore($sp) | |
11737 | If the symbol is not external, we want | |
11738 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11739 | nop | |
11740 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 11741 | jalr $ra,$25 |
252b5132 | 11742 | nop |
438c16b8 | 11743 | lw $gp,cprestore($sp) |
f5040a92 AO |
11744 | |
11745 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
11746 | sequences above, minus nops, unless the symbol is local, | |
11747 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
11748 | GOT_DISP. */ | |
438c16b8 | 11749 | if (HAVE_NEWABI) |
252b5132 | 11750 | { |
90ecf173 | 11751 | if (!mips_big_got) |
f5040a92 | 11752 | { |
4d7206a2 | 11753 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11754 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11755 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 11756 | mips_gp_register); |
4d7206a2 | 11757 | relax_switch (); |
67c0d1eb RS |
11758 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11759 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
11760 | mips_gp_register); |
11761 | relax_end (); | |
f5040a92 AO |
11762 | } |
11763 | else | |
11764 | { | |
4d7206a2 | 11765 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 11766 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
11767 | BFD_RELOC_MIPS_CALL_HI16); |
11768 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
11769 | PIC_CALL_REG, mips_gp_register); | |
11770 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
11771 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
11772 | PIC_CALL_REG); | |
4d7206a2 | 11773 | relax_switch (); |
67c0d1eb RS |
11774 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11775 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
11776 | mips_gp_register); | |
11777 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11778 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 11779 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 11780 | relax_end (); |
f5040a92 | 11781 | } |
684022ea | 11782 | |
df58fc94 | 11783 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
11784 | } |
11785 | else | |
11786 | { | |
4d7206a2 | 11787 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 11788 | if (!mips_big_got) |
438c16b8 | 11789 | { |
67c0d1eb RS |
11790 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11791 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 11792 | mips_gp_register); |
269137b2 | 11793 | load_delay_nop (); |
4d7206a2 | 11794 | relax_switch (); |
438c16b8 | 11795 | } |
252b5132 | 11796 | else |
252b5132 | 11797 | { |
67c0d1eb RS |
11798 | int gpdelay; |
11799 | ||
11800 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 11801 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
11802 | BFD_RELOC_MIPS_CALL_HI16); |
11803 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
11804 | PIC_CALL_REG, mips_gp_register); | |
11805 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
11806 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
11807 | PIC_CALL_REG); | |
269137b2 | 11808 | load_delay_nop (); |
4d7206a2 | 11809 | relax_switch (); |
67c0d1eb RS |
11810 | if (gpdelay) |
11811 | macro_build (NULL, "nop", ""); | |
252b5132 | 11812 | } |
67c0d1eb RS |
11813 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11814 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 11815 | mips_gp_register); |
269137b2 | 11816 | load_delay_nop (); |
67c0d1eb RS |
11817 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11818 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 11819 | relax_end (); |
df58fc94 | 11820 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 11821 | |
6478892d | 11822 | if (mips_cprestore_offset < 0) |
1661c76c | 11823 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
11824 | else |
11825 | { | |
90ecf173 | 11826 | if (!mips_frame_reg_valid) |
7a621144 | 11827 | { |
1661c76c | 11828 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
11829 | /* Quiet this warning. */ |
11830 | mips_frame_reg_valid = 1; | |
11831 | } | |
90ecf173 | 11832 | if (!mips_cprestore_valid) |
7a621144 | 11833 | { |
1661c76c | 11834 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
11835 | /* Quiet this warning. */ |
11836 | mips_cprestore_valid = 1; | |
11837 | } | |
6478892d | 11838 | if (mips_opts.noreorder) |
67c0d1eb | 11839 | macro_build (NULL, "nop", ""); |
6478892d | 11840 | expr1.X_add_number = mips_cprestore_offset; |
134c0c8b | 11841 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 11842 | mips_gp_register, |
256ab948 TS |
11843 | mips_frame_reg, |
11844 | HAVE_64BIT_ADDRESSES); | |
6478892d | 11845 | } |
252b5132 RH |
11846 | } |
11847 | } | |
0a44bf69 | 11848 | else if (mips_pic == VXWORKS_PIC) |
1661c76c | 11849 | as_bad (_("non-PIC jump used in PIC library")); |
252b5132 RH |
11850 | else |
11851 | abort (); | |
11852 | ||
8fc2e39e | 11853 | break; |
252b5132 | 11854 | |
7f3c4072 | 11855 | case M_LBUE_AB: |
7f3c4072 CM |
11856 | s = "lbue"; |
11857 | fmt = "t,+j(b)"; | |
11858 | offbits = 9; | |
11859 | goto ld_st; | |
11860 | case M_LHUE_AB: | |
7f3c4072 CM |
11861 | s = "lhue"; |
11862 | fmt = "t,+j(b)"; | |
11863 | offbits = 9; | |
11864 | goto ld_st; | |
11865 | case M_LBE_AB: | |
7f3c4072 CM |
11866 | s = "lbe"; |
11867 | fmt = "t,+j(b)"; | |
11868 | offbits = 9; | |
11869 | goto ld_st; | |
11870 | case M_LHE_AB: | |
7f3c4072 CM |
11871 | s = "lhe"; |
11872 | fmt = "t,+j(b)"; | |
11873 | offbits = 9; | |
11874 | goto ld_st; | |
11875 | case M_LLE_AB: | |
7f3c4072 CM |
11876 | s = "lle"; |
11877 | fmt = "t,+j(b)"; | |
11878 | offbits = 9; | |
11879 | goto ld_st; | |
11880 | case M_LWE_AB: | |
7f3c4072 CM |
11881 | s = "lwe"; |
11882 | fmt = "t,+j(b)"; | |
11883 | offbits = 9; | |
11884 | goto ld_st; | |
11885 | case M_LWLE_AB: | |
7f3c4072 CM |
11886 | s = "lwle"; |
11887 | fmt = "t,+j(b)"; | |
11888 | offbits = 9; | |
11889 | goto ld_st; | |
11890 | case M_LWRE_AB: | |
7f3c4072 CM |
11891 | s = "lwre"; |
11892 | fmt = "t,+j(b)"; | |
11893 | offbits = 9; | |
11894 | goto ld_st; | |
11895 | case M_SBE_AB: | |
7f3c4072 CM |
11896 | s = "sbe"; |
11897 | fmt = "t,+j(b)"; | |
11898 | offbits = 9; | |
11899 | goto ld_st; | |
11900 | case M_SCE_AB: | |
7f3c4072 CM |
11901 | s = "sce"; |
11902 | fmt = "t,+j(b)"; | |
11903 | offbits = 9; | |
11904 | goto ld_st; | |
11905 | case M_SHE_AB: | |
7f3c4072 CM |
11906 | s = "she"; |
11907 | fmt = "t,+j(b)"; | |
11908 | offbits = 9; | |
11909 | goto ld_st; | |
11910 | case M_SWE_AB: | |
7f3c4072 CM |
11911 | s = "swe"; |
11912 | fmt = "t,+j(b)"; | |
11913 | offbits = 9; | |
11914 | goto ld_st; | |
11915 | case M_SWLE_AB: | |
7f3c4072 CM |
11916 | s = "swle"; |
11917 | fmt = "t,+j(b)"; | |
11918 | offbits = 9; | |
11919 | goto ld_st; | |
11920 | case M_SWRE_AB: | |
7f3c4072 CM |
11921 | s = "swre"; |
11922 | fmt = "t,+j(b)"; | |
11923 | offbits = 9; | |
11924 | goto ld_st; | |
dec0624d | 11925 | case M_ACLR_AB: |
dec0624d | 11926 | s = "aclr"; |
dec0624d | 11927 | fmt = "\\,~(b)"; |
7f3c4072 | 11928 | offbits = 12; |
dec0624d MR |
11929 | goto ld_st; |
11930 | case M_ASET_AB: | |
dec0624d | 11931 | s = "aset"; |
dec0624d | 11932 | fmt = "\\,~(b)"; |
7f3c4072 | 11933 | offbits = 12; |
dec0624d | 11934 | goto ld_st; |
252b5132 RH |
11935 | case M_LB_AB: |
11936 | s = "lb"; | |
df58fc94 | 11937 | fmt = "t,o(b)"; |
252b5132 RH |
11938 | goto ld; |
11939 | case M_LBU_AB: | |
11940 | s = "lbu"; | |
df58fc94 | 11941 | fmt = "t,o(b)"; |
252b5132 RH |
11942 | goto ld; |
11943 | case M_LH_AB: | |
11944 | s = "lh"; | |
df58fc94 | 11945 | fmt = "t,o(b)"; |
252b5132 RH |
11946 | goto ld; |
11947 | case M_LHU_AB: | |
11948 | s = "lhu"; | |
df58fc94 | 11949 | fmt = "t,o(b)"; |
252b5132 RH |
11950 | goto ld; |
11951 | case M_LW_AB: | |
11952 | s = "lw"; | |
df58fc94 | 11953 | fmt = "t,o(b)"; |
252b5132 RH |
11954 | goto ld; |
11955 | case M_LWC0_AB: | |
df58fc94 | 11956 | gas_assert (!mips_opts.micromips); |
252b5132 | 11957 | s = "lwc0"; |
df58fc94 | 11958 | fmt = "E,o(b)"; |
bdaaa2e1 | 11959 | /* Itbl support may require additional care here. */ |
252b5132 | 11960 | coproc = 1; |
df58fc94 | 11961 | goto ld_st; |
252b5132 RH |
11962 | case M_LWC1_AB: |
11963 | s = "lwc1"; | |
df58fc94 | 11964 | fmt = "T,o(b)"; |
bdaaa2e1 | 11965 | /* Itbl support may require additional care here. */ |
252b5132 | 11966 | coproc = 1; |
df58fc94 | 11967 | goto ld_st; |
252b5132 RH |
11968 | case M_LWC2_AB: |
11969 | s = "lwc2"; | |
df58fc94 | 11970 | fmt = COP12_FMT; |
7361da2c AB |
11971 | offbits = (mips_opts.micromips ? 12 |
11972 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11973 | : 16); | |
bdaaa2e1 | 11974 | /* Itbl support may require additional care here. */ |
252b5132 | 11975 | coproc = 1; |
df58fc94 | 11976 | goto ld_st; |
252b5132 | 11977 | case M_LWC3_AB: |
df58fc94 | 11978 | gas_assert (!mips_opts.micromips); |
252b5132 | 11979 | s = "lwc3"; |
df58fc94 | 11980 | fmt = "E,o(b)"; |
bdaaa2e1 | 11981 | /* Itbl support may require additional care here. */ |
252b5132 | 11982 | coproc = 1; |
df58fc94 | 11983 | goto ld_st; |
252b5132 RH |
11984 | case M_LWL_AB: |
11985 | s = "lwl"; | |
df58fc94 | 11986 | fmt = MEM12_FMT; |
7f3c4072 | 11987 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11988 | goto ld_st; |
252b5132 RH |
11989 | case M_LWR_AB: |
11990 | s = "lwr"; | |
df58fc94 | 11991 | fmt = MEM12_FMT; |
7f3c4072 | 11992 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11993 | goto ld_st; |
252b5132 | 11994 | case M_LDC1_AB: |
252b5132 | 11995 | s = "ldc1"; |
df58fc94 | 11996 | fmt = "T,o(b)"; |
bdaaa2e1 | 11997 | /* Itbl support may require additional care here. */ |
252b5132 | 11998 | coproc = 1; |
df58fc94 | 11999 | goto ld_st; |
252b5132 RH |
12000 | case M_LDC2_AB: |
12001 | s = "ldc2"; | |
df58fc94 | 12002 | fmt = COP12_FMT; |
7361da2c AB |
12003 | offbits = (mips_opts.micromips ? 12 |
12004 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
12005 | : 16); | |
bdaaa2e1 | 12006 | /* Itbl support may require additional care here. */ |
252b5132 | 12007 | coproc = 1; |
df58fc94 | 12008 | goto ld_st; |
c77c0862 | 12009 | case M_LQC2_AB: |
c77c0862 | 12010 | s = "lqc2"; |
14daeee3 | 12011 | fmt = "+7,o(b)"; |
c77c0862 RS |
12012 | /* Itbl support may require additional care here. */ |
12013 | coproc = 1; | |
12014 | goto ld_st; | |
252b5132 RH |
12015 | case M_LDC3_AB: |
12016 | s = "ldc3"; | |
df58fc94 | 12017 | fmt = "E,o(b)"; |
bdaaa2e1 | 12018 | /* Itbl support may require additional care here. */ |
252b5132 | 12019 | coproc = 1; |
df58fc94 | 12020 | goto ld_st; |
252b5132 RH |
12021 | case M_LDL_AB: |
12022 | s = "ldl"; | |
df58fc94 | 12023 | fmt = MEM12_FMT; |
7f3c4072 | 12024 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 12025 | goto ld_st; |
252b5132 RH |
12026 | case M_LDR_AB: |
12027 | s = "ldr"; | |
df58fc94 | 12028 | fmt = MEM12_FMT; |
7f3c4072 | 12029 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 12030 | goto ld_st; |
252b5132 RH |
12031 | case M_LL_AB: |
12032 | s = "ll"; | |
7361da2c AB |
12033 | fmt = LL_SC_FMT; |
12034 | offbits = (mips_opts.micromips ? 12 | |
12035 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
12036 | : 16); | |
252b5132 RH |
12037 | goto ld; |
12038 | case M_LLD_AB: | |
12039 | s = "lld"; | |
7361da2c AB |
12040 | fmt = LL_SC_FMT; |
12041 | offbits = (mips_opts.micromips ? 12 | |
12042 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
12043 | : 16); | |
252b5132 RH |
12044 | goto ld; |
12045 | case M_LWU_AB: | |
12046 | s = "lwu"; | |
df58fc94 | 12047 | fmt = MEM12_FMT; |
7f3c4072 | 12048 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
12049 | goto ld; |
12050 | case M_LWP_AB: | |
df58fc94 RS |
12051 | gas_assert (mips_opts.micromips); |
12052 | s = "lwp"; | |
12053 | fmt = "t,~(b)"; | |
7f3c4072 | 12054 | offbits = 12; |
df58fc94 RS |
12055 | lp = 1; |
12056 | goto ld; | |
12057 | case M_LDP_AB: | |
df58fc94 RS |
12058 | gas_assert (mips_opts.micromips); |
12059 | s = "ldp"; | |
12060 | fmt = "t,~(b)"; | |
7f3c4072 | 12061 | offbits = 12; |
df58fc94 RS |
12062 | lp = 1; |
12063 | goto ld; | |
a45328b9 AB |
12064 | case M_LLDP_AB: |
12065 | case M_LLWP_AB: | |
41cee089 | 12066 | case M_LLWPE_AB: |
a45328b9 AB |
12067 | s = ip->insn_mo->name; |
12068 | fmt = "t,d,s"; | |
12069 | ll_sc_paired = 1; | |
12070 | offbits = 0; | |
12071 | goto ld; | |
df58fc94 | 12072 | case M_LWM_AB: |
df58fc94 RS |
12073 | gas_assert (mips_opts.micromips); |
12074 | s = "lwm"; | |
12075 | fmt = "n,~(b)"; | |
7f3c4072 | 12076 | offbits = 12; |
df58fc94 RS |
12077 | goto ld_st; |
12078 | case M_LDM_AB: | |
df58fc94 RS |
12079 | gas_assert (mips_opts.micromips); |
12080 | s = "ldm"; | |
12081 | fmt = "n,~(b)"; | |
7f3c4072 | 12082 | offbits = 12; |
df58fc94 RS |
12083 | goto ld_st; |
12084 | ||
252b5132 | 12085 | ld: |
a45328b9 AB |
12086 | /* Try to use one the the load registers to compute the base address. |
12087 | We don't want to use $0 as tempreg. */ | |
12088 | if (ll_sc_paired) | |
12089 | { | |
12090 | if ((op[0] == ZERO && op[3] == op[1]) | |
12091 | || (op[1] == ZERO && op[3] == op[0]) | |
12092 | || (op[0] == ZERO && op[1] == ZERO)) | |
12093 | goto ld_st; | |
12094 | else if (op[0] != op[3] && op[0] != ZERO) | |
12095 | tempreg = op[0]; | |
12096 | else | |
12097 | tempreg = op[1]; | |
12098 | } | |
252b5132 | 12099 | else |
a45328b9 AB |
12100 | { |
12101 | if (op[2] == op[0] + lp || op[0] + lp == ZERO) | |
12102 | goto ld_st; | |
12103 | else | |
12104 | tempreg = op[0] + lp; | |
12105 | } | |
df58fc94 RS |
12106 | goto ld_noat; |
12107 | ||
252b5132 RH |
12108 | case M_SB_AB: |
12109 | s = "sb"; | |
df58fc94 RS |
12110 | fmt = "t,o(b)"; |
12111 | goto ld_st; | |
252b5132 RH |
12112 | case M_SH_AB: |
12113 | s = "sh"; | |
df58fc94 RS |
12114 | fmt = "t,o(b)"; |
12115 | goto ld_st; | |
252b5132 RH |
12116 | case M_SW_AB: |
12117 | s = "sw"; | |
df58fc94 RS |
12118 | fmt = "t,o(b)"; |
12119 | goto ld_st; | |
252b5132 | 12120 | case M_SWC0_AB: |
df58fc94 | 12121 | gas_assert (!mips_opts.micromips); |
252b5132 | 12122 | s = "swc0"; |
df58fc94 | 12123 | fmt = "E,o(b)"; |
bdaaa2e1 | 12124 | /* Itbl support may require additional care here. */ |
252b5132 | 12125 | coproc = 1; |
df58fc94 | 12126 | goto ld_st; |
252b5132 RH |
12127 | case M_SWC1_AB: |
12128 | s = "swc1"; | |
df58fc94 | 12129 | fmt = "T,o(b)"; |
bdaaa2e1 | 12130 | /* Itbl support may require additional care here. */ |
252b5132 | 12131 | coproc = 1; |
df58fc94 | 12132 | goto ld_st; |
252b5132 RH |
12133 | case M_SWC2_AB: |
12134 | s = "swc2"; | |
df58fc94 | 12135 | fmt = COP12_FMT; |
7361da2c AB |
12136 | offbits = (mips_opts.micromips ? 12 |
12137 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
12138 | : 16); | |
bdaaa2e1 | 12139 | /* Itbl support may require additional care here. */ |
252b5132 | 12140 | coproc = 1; |
df58fc94 | 12141 | goto ld_st; |
252b5132 | 12142 | case M_SWC3_AB: |
df58fc94 | 12143 | gas_assert (!mips_opts.micromips); |
252b5132 | 12144 | s = "swc3"; |
df58fc94 | 12145 | fmt = "E,o(b)"; |
bdaaa2e1 | 12146 | /* Itbl support may require additional care here. */ |
252b5132 | 12147 | coproc = 1; |
df58fc94 | 12148 | goto ld_st; |
252b5132 RH |
12149 | case M_SWL_AB: |
12150 | s = "swl"; | |
df58fc94 | 12151 | fmt = MEM12_FMT; |
7f3c4072 | 12152 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 12153 | goto ld_st; |
252b5132 RH |
12154 | case M_SWR_AB: |
12155 | s = "swr"; | |
df58fc94 | 12156 | fmt = MEM12_FMT; |
7f3c4072 | 12157 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 12158 | goto ld_st; |
252b5132 RH |
12159 | case M_SC_AB: |
12160 | s = "sc"; | |
7361da2c AB |
12161 | fmt = LL_SC_FMT; |
12162 | offbits = (mips_opts.micromips ? 12 | |
12163 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
12164 | : 16); | |
df58fc94 | 12165 | goto ld_st; |
252b5132 RH |
12166 | case M_SCD_AB: |
12167 | s = "scd"; | |
7361da2c AB |
12168 | fmt = LL_SC_FMT; |
12169 | offbits = (mips_opts.micromips ? 12 | |
12170 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
12171 | : 16); | |
df58fc94 | 12172 | goto ld_st; |
a45328b9 AB |
12173 | case M_SCDP_AB: |
12174 | case M_SCWP_AB: | |
41cee089 | 12175 | case M_SCWPE_AB: |
a45328b9 AB |
12176 | s = ip->insn_mo->name; |
12177 | fmt = "t,d,s"; | |
12178 | ll_sc_paired = 1; | |
12179 | offbits = 0; | |
12180 | goto ld_st; | |
d43b4baf TS |
12181 | case M_CACHE_AB: |
12182 | s = "cache"; | |
7361da2c AB |
12183 | fmt = (mips_opts.micromips ? "k,~(b)" |
12184 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" | |
12185 | : "k,o(b)"); | |
12186 | offbits = (mips_opts.micromips ? 12 | |
12187 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
12188 | : 16); | |
7f3c4072 CM |
12189 | goto ld_st; |
12190 | case M_CACHEE_AB: | |
7f3c4072 CM |
12191 | s = "cachee"; |
12192 | fmt = "k,+j(b)"; | |
12193 | offbits = 9; | |
df58fc94 | 12194 | goto ld_st; |
3eebd5eb MR |
12195 | case M_PREF_AB: |
12196 | s = "pref"; | |
7361da2c AB |
12197 | fmt = (mips_opts.micromips ? "k,~(b)" |
12198 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" | |
12199 | : "k,o(b)"); | |
12200 | offbits = (mips_opts.micromips ? 12 | |
12201 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
12202 | : 16); | |
7f3c4072 CM |
12203 | goto ld_st; |
12204 | case M_PREFE_AB: | |
7f3c4072 CM |
12205 | s = "prefe"; |
12206 | fmt = "k,+j(b)"; | |
12207 | offbits = 9; | |
df58fc94 | 12208 | goto ld_st; |
252b5132 | 12209 | case M_SDC1_AB: |
252b5132 | 12210 | s = "sdc1"; |
df58fc94 | 12211 | fmt = "T,o(b)"; |
252b5132 | 12212 | coproc = 1; |
bdaaa2e1 | 12213 | /* Itbl support may require additional care here. */ |
df58fc94 | 12214 | goto ld_st; |
252b5132 RH |
12215 | case M_SDC2_AB: |
12216 | s = "sdc2"; | |
df58fc94 | 12217 | fmt = COP12_FMT; |
7361da2c AB |
12218 | offbits = (mips_opts.micromips ? 12 |
12219 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
12220 | : 16); | |
c77c0862 RS |
12221 | /* Itbl support may require additional care here. */ |
12222 | coproc = 1; | |
12223 | goto ld_st; | |
12224 | case M_SQC2_AB: | |
c77c0862 | 12225 | s = "sqc2"; |
14daeee3 | 12226 | fmt = "+7,o(b)"; |
bdaaa2e1 | 12227 | /* Itbl support may require additional care here. */ |
252b5132 | 12228 | coproc = 1; |
df58fc94 | 12229 | goto ld_st; |
252b5132 | 12230 | case M_SDC3_AB: |
df58fc94 | 12231 | gas_assert (!mips_opts.micromips); |
252b5132 | 12232 | s = "sdc3"; |
df58fc94 | 12233 | fmt = "E,o(b)"; |
bdaaa2e1 | 12234 | /* Itbl support may require additional care here. */ |
252b5132 | 12235 | coproc = 1; |
df58fc94 | 12236 | goto ld_st; |
252b5132 RH |
12237 | case M_SDL_AB: |
12238 | s = "sdl"; | |
df58fc94 | 12239 | fmt = MEM12_FMT; |
7f3c4072 | 12240 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 12241 | goto ld_st; |
252b5132 RH |
12242 | case M_SDR_AB: |
12243 | s = "sdr"; | |
df58fc94 | 12244 | fmt = MEM12_FMT; |
7f3c4072 | 12245 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
12246 | goto ld_st; |
12247 | case M_SWP_AB: | |
df58fc94 RS |
12248 | gas_assert (mips_opts.micromips); |
12249 | s = "swp"; | |
12250 | fmt = "t,~(b)"; | |
7f3c4072 | 12251 | offbits = 12; |
df58fc94 RS |
12252 | goto ld_st; |
12253 | case M_SDP_AB: | |
df58fc94 RS |
12254 | gas_assert (mips_opts.micromips); |
12255 | s = "sdp"; | |
12256 | fmt = "t,~(b)"; | |
7f3c4072 | 12257 | offbits = 12; |
df58fc94 RS |
12258 | goto ld_st; |
12259 | case M_SWM_AB: | |
df58fc94 RS |
12260 | gas_assert (mips_opts.micromips); |
12261 | s = "swm"; | |
12262 | fmt = "n,~(b)"; | |
7f3c4072 | 12263 | offbits = 12; |
df58fc94 RS |
12264 | goto ld_st; |
12265 | case M_SDM_AB: | |
df58fc94 RS |
12266 | gas_assert (mips_opts.micromips); |
12267 | s = "sdm"; | |
12268 | fmt = "n,~(b)"; | |
7f3c4072 | 12269 | offbits = 12; |
df58fc94 RS |
12270 | |
12271 | ld_st: | |
8fc2e39e | 12272 | tempreg = AT; |
df58fc94 | 12273 | ld_noat: |
a45328b9 | 12274 | breg = ll_sc_paired ? op[3] : op[2]; |
f2ae14a1 RS |
12275 | if (small_offset_p (0, align, 16)) |
12276 | { | |
12277 | /* The first case exists for M_LD_AB and M_SD_AB, which are | |
12278 | macros for o32 but which should act like normal instructions | |
12279 | otherwise. */ | |
12280 | if (offbits == 16) | |
c0ebe874 | 12281 | macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
12282 | offset_reloc[1], offset_reloc[2], breg); |
12283 | else if (small_offset_p (0, align, offbits)) | |
12284 | { | |
12285 | if (offbits == 0) | |
a45328b9 AB |
12286 | { |
12287 | if (ll_sc_paired) | |
12288 | macro_build (NULL, s, fmt, op[0], op[1], breg); | |
12289 | else | |
12290 | macro_build (NULL, s, fmt, op[0], breg); | |
12291 | } | |
f2ae14a1 | 12292 | else |
c0ebe874 | 12293 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 12294 | (int) offset_expr.X_add_number, breg); |
f2ae14a1 RS |
12295 | } |
12296 | else | |
12297 | { | |
12298 | if (tempreg == AT) | |
12299 | used_at = 1; | |
12300 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
12301 | tempreg, breg, -1, offset_reloc[0], | |
12302 | offset_reloc[1], offset_reloc[2]); | |
12303 | if (offbits == 0) | |
a45328b9 AB |
12304 | { |
12305 | if (ll_sc_paired) | |
12306 | macro_build (NULL, s, fmt, op[0], op[1], tempreg); | |
12307 | else | |
12308 | macro_build (NULL, s, fmt, op[0], tempreg); | |
12309 | } | |
f2ae14a1 | 12310 | else |
c0ebe874 | 12311 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
f2ae14a1 RS |
12312 | } |
12313 | break; | |
12314 | } | |
12315 | ||
12316 | if (tempreg == AT) | |
12317 | used_at = 1; | |
12318 | ||
252b5132 RH |
12319 | if (offset_expr.X_op != O_constant |
12320 | && offset_expr.X_op != O_symbol) | |
12321 | { | |
1661c76c | 12322 | as_bad (_("expression too complex")); |
252b5132 RH |
12323 | offset_expr.X_op = O_constant; |
12324 | } | |
12325 | ||
2051e8c4 MR |
12326 | if (HAVE_32BIT_ADDRESSES |
12327 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
12328 | { |
12329 | char value [32]; | |
12330 | ||
12331 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 12332 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 12333 | } |
2051e8c4 | 12334 | |
252b5132 RH |
12335 | /* A constant expression in PIC code can be handled just as it |
12336 | is in non PIC code. */ | |
aed1a261 RS |
12337 | if (offset_expr.X_op == O_constant) |
12338 | { | |
f2ae14a1 RS |
12339 | expr1.X_add_number = offset_high_part (offset_expr.X_add_number, |
12340 | offbits == 0 ? 16 : offbits); | |
12341 | offset_expr.X_add_number -= expr1.X_add_number; | |
df58fc94 | 12342 | |
f2ae14a1 RS |
12343 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
12344 | if (breg != 0) | |
12345 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12346 | tempreg, tempreg, breg); | |
7f3c4072 | 12347 | if (offbits == 0) |
dd6a37e7 | 12348 | { |
f2ae14a1 | 12349 | if (offset_expr.X_add_number != 0) |
dd6a37e7 | 12350 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
f2ae14a1 | 12351 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
a45328b9 AB |
12352 | if (ll_sc_paired) |
12353 | macro_build (NULL, s, fmt, op[0], op[1], tempreg); | |
12354 | else | |
12355 | macro_build (NULL, s, fmt, op[0], tempreg); | |
dd6a37e7 | 12356 | } |
7f3c4072 | 12357 | else if (offbits == 16) |
c0ebe874 | 12358 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
df58fc94 | 12359 | else |
c0ebe874 | 12360 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 12361 | (int) offset_expr.X_add_number, tempreg); |
df58fc94 | 12362 | } |
7f3c4072 | 12363 | else if (offbits != 16) |
df58fc94 | 12364 | { |
7f3c4072 | 12365 | /* The offset field is too narrow to be used for a low-part |
2b0f3761 | 12366 | relocation, so load the whole address into the auxiliary |
f2ae14a1 RS |
12367 | register. */ |
12368 | load_address (tempreg, &offset_expr, &used_at); | |
12369 | if (breg != 0) | |
12370 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12371 | tempreg, tempreg, breg); | |
7f3c4072 | 12372 | if (offbits == 0) |
a45328b9 AB |
12373 | { |
12374 | if (ll_sc_paired) | |
12375 | macro_build (NULL, s, fmt, op[0], op[1], tempreg); | |
12376 | else | |
12377 | macro_build (NULL, s, fmt, op[0], tempreg); | |
12378 | } | |
dd6a37e7 | 12379 | else |
c0ebe874 | 12380 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
aed1a261 RS |
12381 | } |
12382 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
12383 | { |
12384 | /* If this is a reference to a GP relative symbol, and there | |
12385 | is no base register, we want | |
c0ebe874 | 12386 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
12387 | Otherwise, if there is no base register, we want |
12388 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 | 12389 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
252b5132 RH |
12390 | If we have a constant, we need two instructions anyhow, |
12391 | so we always use the latter form. | |
12392 | ||
12393 | If we have a base register, and this is a reference to a | |
12394 | GP relative symbol, we want | |
12395 | addu $tempreg,$breg,$gp | |
c0ebe874 | 12396 | <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
12397 | Otherwise we want |
12398 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12399 | addu $tempreg,$tempreg,$breg | |
c0ebe874 | 12400 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 | 12401 | With a constant we always use the latter case. |
76b3015f | 12402 | |
d6bc6245 TS |
12403 | With 64bit address space and no base register and $at usable, |
12404 | we want | |
12405 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12406 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
12407 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12408 | dsll32 $tempreg,0 | |
12409 | daddu $tempreg,$at | |
c0ebe874 | 12410 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12411 | If we have a base register, we want |
12412 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12413 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
12414 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12415 | daddu $at,$breg | |
12416 | dsll32 $tempreg,0 | |
12417 | daddu $tempreg,$at | |
c0ebe874 | 12418 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12419 | |
12420 | Without $at we can't generate the optimal path for superscalar | |
12421 | processors here since this would require two temporary registers. | |
12422 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12423 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12424 | dsll $tempreg,16 | |
12425 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12426 | dsll $tempreg,16 | |
c0ebe874 | 12427 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12428 | If we have a base register, we want |
12429 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12430 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12431 | dsll $tempreg,16 | |
12432 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12433 | dsll $tempreg,16 | |
12434 | daddu $tempreg,$tempreg,$breg | |
c0ebe874 | 12435 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
6373ee54 | 12436 | |
6caf9ef4 | 12437 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
12438 | the same sequence as in 32bit address space. */ |
12439 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 12440 | { |
aed1a261 | 12441 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
12442 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
12443 | { | |
12444 | relax_start (offset_expr.X_add_symbol); | |
12445 | if (breg == 0) | |
12446 | { | |
c0ebe874 | 12447 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
12448 | BFD_RELOC_GPREL16, mips_gp_register); |
12449 | } | |
12450 | else | |
12451 | { | |
12452 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12453 | tempreg, breg, mips_gp_register); | |
c0ebe874 | 12454 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
12455 | BFD_RELOC_GPREL16, tempreg); |
12456 | } | |
12457 | relax_switch (); | |
12458 | } | |
d6bc6245 | 12459 | |
741fe287 | 12460 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 12461 | { |
df58fc94 | 12462 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 12463 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 12464 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
12465 | BFD_RELOC_HI16_S); |
12466 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
12467 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 12468 | if (breg != 0) |
67c0d1eb | 12469 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 12470 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 12471 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
c0ebe874 | 12472 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, |
67c0d1eb | 12473 | tempreg); |
d6bc6245 TS |
12474 | used_at = 1; |
12475 | } | |
12476 | else | |
12477 | { | |
df58fc94 | 12478 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
12479 | BFD_RELOC_MIPS_HIGHEST); |
12480 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
12481 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 12482 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
12483 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
12484 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 12485 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 12486 | if (breg != 0) |
67c0d1eb | 12487 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 12488 | tempreg, tempreg, breg); |
c0ebe874 | 12489 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12490 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 12491 | } |
6caf9ef4 TS |
12492 | |
12493 | if (mips_relax.sequence) | |
12494 | relax_end (); | |
8fc2e39e | 12495 | break; |
d6bc6245 | 12496 | } |
256ab948 | 12497 | |
252b5132 RH |
12498 | if (breg == 0) |
12499 | { | |
67c0d1eb | 12500 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 12501 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12502 | { |
4d7206a2 | 12503 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 12504 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16, |
67c0d1eb | 12505 | mips_gp_register); |
4d7206a2 | 12506 | relax_switch (); |
252b5132 | 12507 | } |
67c0d1eb | 12508 | macro_build_lui (&offset_expr, tempreg); |
c0ebe874 | 12509 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12510 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
12511 | if (mips_relax.sequence) |
12512 | relax_end (); | |
252b5132 RH |
12513 | } |
12514 | else | |
12515 | { | |
67c0d1eb | 12516 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 12517 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12518 | { |
4d7206a2 | 12519 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 12520 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12521 | tempreg, breg, mips_gp_register); |
c0ebe874 | 12522 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12523 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 12524 | relax_switch (); |
252b5132 | 12525 | } |
67c0d1eb RS |
12526 | macro_build_lui (&offset_expr, tempreg); |
12527 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 12528 | tempreg, tempreg, breg); |
c0ebe874 | 12529 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12530 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
12531 | if (mips_relax.sequence) |
12532 | relax_end (); | |
252b5132 RH |
12533 | } |
12534 | } | |
0a44bf69 | 12535 | else if (!mips_big_got) |
252b5132 | 12536 | { |
ed6fb7bd | 12537 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 12538 | |
252b5132 RH |
12539 | /* If this is a reference to an external symbol, we want |
12540 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12541 | nop | |
c0ebe874 | 12542 | <op> op[0],0($tempreg) |
252b5132 RH |
12543 | Otherwise we want |
12544 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12545 | nop | |
12546 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 12547 | <op> op[0],0($tempreg) |
f5040a92 AO |
12548 | |
12549 | For NewABI, we want | |
12550 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 12551 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) |
f5040a92 | 12552 | |
252b5132 RH |
12553 | If there is a base register, we add it to $tempreg before |
12554 | the <op>. If there is a constant, we stick it in the | |
12555 | <op> instruction. We don't handle constants larger than | |
12556 | 16 bits, because we have no way to load the upper 16 bits | |
12557 | (actually, we could handle them for the subset of cases | |
12558 | in which we are not using $at). */ | |
9c2799c2 | 12559 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
12560 | if (HAVE_NEWABI) |
12561 | { | |
67c0d1eb RS |
12562 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12563 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 12564 | if (breg != 0) |
67c0d1eb | 12565 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12566 | tempreg, tempreg, breg); |
c0ebe874 | 12567 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12568 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
12569 | break; |
12570 | } | |
252b5132 RH |
12571 | expr1.X_add_number = offset_expr.X_add_number; |
12572 | offset_expr.X_add_number = 0; | |
12573 | if (expr1.X_add_number < -0x8000 | |
12574 | || expr1.X_add_number >= 0x8000) | |
12575 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
12576 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12577 | lw_reloc_type, mips_gp_register); | |
269137b2 | 12578 | load_delay_nop (); |
4d7206a2 RS |
12579 | relax_start (offset_expr.X_add_symbol); |
12580 | relax_switch (); | |
67c0d1eb RS |
12581 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
12582 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 12583 | relax_end (); |
252b5132 | 12584 | if (breg != 0) |
67c0d1eb | 12585 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12586 | tempreg, tempreg, breg); |
c0ebe874 | 12587 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 12588 | } |
0a44bf69 | 12589 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 12590 | { |
67c0d1eb | 12591 | int gpdelay; |
252b5132 RH |
12592 | |
12593 | /* If this is a reference to an external symbol, we want | |
12594 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12595 | addu $tempreg,$tempreg,$gp | |
12596 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 12597 | <op> op[0],0($tempreg) |
252b5132 RH |
12598 | Otherwise we want |
12599 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12600 | nop | |
12601 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 12602 | <op> op[0],0($tempreg) |
252b5132 RH |
12603 | If there is a base register, we add it to $tempreg before |
12604 | the <op>. If there is a constant, we stick it in the | |
12605 | <op> instruction. We don't handle constants larger than | |
12606 | 16 bits, because we have no way to load the upper 16 bits | |
12607 | (actually, we could handle them for the subset of cases | |
f5040a92 | 12608 | in which we are not using $at). */ |
9c2799c2 | 12609 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
12610 | expr1.X_add_number = offset_expr.X_add_number; |
12611 | offset_expr.X_add_number = 0; | |
12612 | if (expr1.X_add_number < -0x8000 | |
12613 | || expr1.X_add_number >= 0x8000) | |
12614 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12615 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 12616 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12617 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 12618 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
12619 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
12620 | mips_gp_register); | |
12621 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12622 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 12623 | relax_switch (); |
67c0d1eb RS |
12624 | if (gpdelay) |
12625 | macro_build (NULL, "nop", ""); | |
12626 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12627 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 12628 | load_delay_nop (); |
67c0d1eb RS |
12629 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
12630 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
12631 | relax_end (); |
12632 | ||
252b5132 | 12633 | if (breg != 0) |
67c0d1eb | 12634 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12635 | tempreg, tempreg, breg); |
c0ebe874 | 12636 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 12637 | } |
0a44bf69 | 12638 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 12639 | { |
f5040a92 AO |
12640 | /* If this is a reference to an external symbol, we want |
12641 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12642 | add $tempreg,$tempreg,$gp | |
12643 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 12644 | <op> op[0],<ofst>($tempreg) |
f5040a92 AO |
12645 | Otherwise, for local symbols, we want: |
12646 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 12647 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ |
9c2799c2 | 12648 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 12649 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
12650 | offset_expr.X_add_number = 0; |
12651 | if (expr1.X_add_number < -0x8000 | |
12652 | || expr1.X_add_number >= 0x8000) | |
12653 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 12654 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12655 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 12656 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
12657 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
12658 | mips_gp_register); | |
12659 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12660 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 12661 | if (breg != 0) |
67c0d1eb | 12662 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12663 | tempreg, tempreg, breg); |
c0ebe874 | 12664 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
684022ea | 12665 | |
4d7206a2 | 12666 | relax_switch (); |
f5040a92 | 12667 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
12668 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12669 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 12670 | if (breg != 0) |
67c0d1eb | 12671 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12672 | tempreg, tempreg, breg); |
c0ebe874 | 12673 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12674 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 12675 | relax_end (); |
f5040a92 | 12676 | } |
252b5132 RH |
12677 | else |
12678 | abort (); | |
12679 | ||
252b5132 RH |
12680 | break; |
12681 | ||
833794fc MR |
12682 | case M_JRADDIUSP: |
12683 | gas_assert (mips_opts.micromips); | |
12684 | gas_assert (mips_opts.insn32); | |
12685 | start_noreorder (); | |
12686 | macro_build (NULL, "jr", "s", RA); | |
c0ebe874 | 12687 | expr1.X_add_number = op[0] << 2; |
833794fc MR |
12688 | macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16); |
12689 | end_noreorder (); | |
12690 | break; | |
12691 | ||
12692 | case M_JRC: | |
12693 | gas_assert (mips_opts.micromips); | |
12694 | gas_assert (mips_opts.insn32); | |
c0ebe874 | 12695 | macro_build (NULL, "jr", "s", op[0]); |
833794fc MR |
12696 | if (mips_opts.noreorder) |
12697 | macro_build (NULL, "nop", ""); | |
12698 | break; | |
12699 | ||
252b5132 RH |
12700 | case M_LI: |
12701 | case M_LI_S: | |
c0ebe874 | 12702 | load_register (op[0], &imm_expr, 0); |
8fc2e39e | 12703 | break; |
252b5132 RH |
12704 | |
12705 | case M_DLI: | |
c0ebe874 | 12706 | load_register (op[0], &imm_expr, 1); |
8fc2e39e | 12707 | break; |
252b5132 RH |
12708 | |
12709 | case M_LI_SS: | |
12710 | if (imm_expr.X_op == O_constant) | |
12711 | { | |
8fc2e39e | 12712 | used_at = 1; |
67c0d1eb | 12713 | load_register (AT, &imm_expr, 0); |
c0ebe874 | 12714 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 RH |
12715 | break; |
12716 | } | |
12717 | else | |
12718 | { | |
b0e6f033 RS |
12719 | gas_assert (imm_expr.X_op == O_absent |
12720 | && offset_expr.X_op == O_symbol | |
90ecf173 MR |
12721 | && strcmp (segment_name (S_GET_SEGMENT |
12722 | (offset_expr.X_add_symbol)), | |
12723 | ".lit4") == 0 | |
12724 | && offset_expr.X_add_number == 0); | |
c0ebe874 | 12725 | macro_build (&offset_expr, "lwc1", "T,o(b)", op[0], |
17a2f251 | 12726 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 12727 | break; |
252b5132 RH |
12728 | } |
12729 | ||
12730 | case M_LI_D: | |
ca4e0257 RS |
12731 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
12732 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
12733 | order 32 bits of the value and the low order 32 bits are either | |
12734 | zero or in OFFSET_EXPR. */ | |
b0e6f033 | 12735 | if (imm_expr.X_op == O_constant) |
252b5132 | 12736 | { |
bad1aba3 | 12737 | if (GPR_SIZE == 64) |
c0ebe874 | 12738 | load_register (op[0], &imm_expr, 1); |
252b5132 RH |
12739 | else |
12740 | { | |
12741 | int hreg, lreg; | |
12742 | ||
12743 | if (target_big_endian) | |
12744 | { | |
c0ebe874 RS |
12745 | hreg = op[0]; |
12746 | lreg = op[0] + 1; | |
252b5132 RH |
12747 | } |
12748 | else | |
12749 | { | |
c0ebe874 RS |
12750 | hreg = op[0] + 1; |
12751 | lreg = op[0]; | |
252b5132 RH |
12752 | } |
12753 | ||
12754 | if (hreg <= 31) | |
67c0d1eb | 12755 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
12756 | if (lreg <= 31) |
12757 | { | |
12758 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 12759 | move_register (lreg, 0); |
252b5132 RH |
12760 | else |
12761 | { | |
9c2799c2 | 12762 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 12763 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
12764 | } |
12765 | } | |
12766 | } | |
8fc2e39e | 12767 | break; |
252b5132 | 12768 | } |
b0e6f033 | 12769 | gas_assert (imm_expr.X_op == O_absent); |
252b5132 RH |
12770 | |
12771 | /* We know that sym is in the .rdata section. First we get the | |
12772 | upper 16 bits of the address. */ | |
12773 | if (mips_pic == NO_PIC) | |
12774 | { | |
67c0d1eb | 12775 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 12776 | used_at = 1; |
252b5132 | 12777 | } |
0a44bf69 | 12778 | else |
252b5132 | 12779 | { |
67c0d1eb RS |
12780 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
12781 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 12782 | used_at = 1; |
252b5132 | 12783 | } |
bdaaa2e1 | 12784 | |
252b5132 | 12785 | /* Now we load the register(s). */ |
bad1aba3 | 12786 | if (GPR_SIZE == 64) |
8fc2e39e TS |
12787 | { |
12788 | used_at = 1; | |
c0ebe874 RS |
12789 | macro_build (&offset_expr, "ld", "t,o(b)", op[0], |
12790 | BFD_RELOC_LO16, AT); | |
8fc2e39e | 12791 | } |
252b5132 RH |
12792 | else |
12793 | { | |
8fc2e39e | 12794 | used_at = 1; |
c0ebe874 RS |
12795 | macro_build (&offset_expr, "lw", "t,o(b)", op[0], |
12796 | BFD_RELOC_LO16, AT); | |
12797 | if (op[0] != RA) | |
252b5132 RH |
12798 | { |
12799 | /* FIXME: How in the world do we deal with the possible | |
12800 | overflow here? */ | |
12801 | offset_expr.X_add_number += 4; | |
67c0d1eb | 12802 | macro_build (&offset_expr, "lw", "t,o(b)", |
c0ebe874 | 12803 | op[0] + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
12804 | } |
12805 | } | |
252b5132 RH |
12806 | break; |
12807 | ||
12808 | case M_LI_DD: | |
ca4e0257 RS |
12809 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
12810 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
12811 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
12812 | the value and the low order 32 bits are either zero or in | |
12813 | OFFSET_EXPR. */ | |
b0e6f033 | 12814 | if (imm_expr.X_op == O_constant) |
252b5132 | 12815 | { |
9b444f95 FS |
12816 | tempreg = ZERO; |
12817 | if (((FPR_SIZE == 64 && GPR_SIZE == 64) | |
12818 | || !ISA_HAS_MXHC1 (mips_opts.isa)) | |
12819 | && imm_expr.X_add_number != 0) | |
12820 | { | |
12821 | used_at = 1; | |
12822 | tempreg = AT; | |
12823 | load_register (AT, &imm_expr, FPR_SIZE == 64); | |
12824 | } | |
351cdf24 | 12825 | if (FPR_SIZE == 64 && GPR_SIZE == 64) |
9b444f95 | 12826 | macro_build (NULL, "dmtc1", "t,S", tempreg, op[0]); |
252b5132 RH |
12827 | else |
12828 | { | |
9b444f95 FS |
12829 | if (!ISA_HAS_MXHC1 (mips_opts.isa)) |
12830 | { | |
12831 | if (FPR_SIZE != 32) | |
12832 | as_bad (_("Unable to generate `%s' compliant code " | |
12833 | "without mthc1"), | |
12834 | (FPR_SIZE == 64) ? "fp64" : "fpxx"); | |
12835 | else | |
12836 | macro_build (NULL, "mtc1", "t,G", tempreg, op[0] + 1); | |
12837 | } | |
252b5132 | 12838 | if (offset_expr.X_op == O_absent) |
c0ebe874 | 12839 | macro_build (NULL, "mtc1", "t,G", 0, op[0]); |
252b5132 RH |
12840 | else |
12841 | { | |
9c2799c2 | 12842 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 12843 | load_register (AT, &offset_expr, 0); |
c0ebe874 | 12844 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 | 12845 | } |
9b444f95 FS |
12846 | if (ISA_HAS_MXHC1 (mips_opts.isa)) |
12847 | { | |
12848 | if (imm_expr.X_add_number != 0) | |
12849 | { | |
12850 | used_at = 1; | |
12851 | tempreg = AT; | |
12852 | load_register (AT, &imm_expr, 0); | |
12853 | } | |
12854 | macro_build (NULL, "mthc1", "t,G", tempreg, op[0]); | |
12855 | } | |
252b5132 RH |
12856 | } |
12857 | break; | |
12858 | } | |
12859 | ||
b0e6f033 RS |
12860 | gas_assert (imm_expr.X_op == O_absent |
12861 | && offset_expr.X_op == O_symbol | |
90ecf173 | 12862 | && offset_expr.X_add_number == 0); |
252b5132 RH |
12863 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
12864 | if (strcmp (s, ".lit8") == 0) | |
134c0c8b MR |
12865 | { |
12866 | op[2] = mips_gp_register; | |
f2ae14a1 RS |
12867 | offset_reloc[0] = BFD_RELOC_MIPS_LITERAL; |
12868 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12869 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
12870 | } |
12871 | else | |
12872 | { | |
9c2799c2 | 12873 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 12874 | used_at = 1; |
0a44bf69 | 12875 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
12876 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
12877 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
12878 | else |
12879 | { | |
12880 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 12881 | macro_build_lui (&offset_expr, AT); |
252b5132 | 12882 | } |
bdaaa2e1 | 12883 | |
c0ebe874 | 12884 | op[2] = AT; |
f2ae14a1 RS |
12885 | offset_reloc[0] = BFD_RELOC_LO16; |
12886 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12887 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
134c0c8b | 12888 | } |
f2ae14a1 | 12889 | align = 8; |
6f2117ba | 12890 | /* Fall through. */ |
c4a68bea | 12891 | |
252b5132 | 12892 | case M_L_DAB: |
6f2117ba PH |
12893 | /* The MIPS assembler seems to check for X_add_number not |
12894 | being double aligned and generating: | |
12895 | lui at,%hi(foo+1) | |
12896 | addu at,at,v1 | |
12897 | addiu at,at,%lo(foo+1) | |
12898 | lwc1 f2,0(at) | |
12899 | lwc1 f3,4(at) | |
12900 | But, the resulting address is the same after relocation so why | |
12901 | generate the extra instruction? */ | |
bdaaa2e1 | 12902 | /* Itbl support may require additional care here. */ |
252b5132 | 12903 | coproc = 1; |
df58fc94 | 12904 | fmt = "T,o(b)"; |
0aa27725 | 12905 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
12906 | { |
12907 | s = "ldc1"; | |
df58fc94 | 12908 | goto ld_st; |
252b5132 | 12909 | } |
252b5132 | 12910 | s = "lwc1"; |
252b5132 RH |
12911 | goto ldd_std; |
12912 | ||
12913 | case M_S_DAB: | |
df58fc94 RS |
12914 | gas_assert (!mips_opts.micromips); |
12915 | /* Itbl support may require additional care here. */ | |
12916 | coproc = 1; | |
12917 | fmt = "T,o(b)"; | |
0aa27725 | 12918 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
12919 | { |
12920 | s = "sdc1"; | |
df58fc94 | 12921 | goto ld_st; |
252b5132 | 12922 | } |
252b5132 | 12923 | s = "swc1"; |
252b5132 RH |
12924 | goto ldd_std; |
12925 | ||
e407c74b NC |
12926 | case M_LQ_AB: |
12927 | fmt = "t,o(b)"; | |
12928 | s = "lq"; | |
12929 | goto ld; | |
12930 | ||
12931 | case M_SQ_AB: | |
12932 | fmt = "t,o(b)"; | |
12933 | s = "sq"; | |
12934 | goto ld_st; | |
12935 | ||
252b5132 | 12936 | case M_LD_AB: |
df58fc94 | 12937 | fmt = "t,o(b)"; |
bad1aba3 | 12938 | if (GPR_SIZE == 64) |
252b5132 RH |
12939 | { |
12940 | s = "ld"; | |
12941 | goto ld; | |
12942 | } | |
252b5132 | 12943 | s = "lw"; |
252b5132 RH |
12944 | goto ldd_std; |
12945 | ||
12946 | case M_SD_AB: | |
df58fc94 | 12947 | fmt = "t,o(b)"; |
bad1aba3 | 12948 | if (GPR_SIZE == 64) |
252b5132 RH |
12949 | { |
12950 | s = "sd"; | |
df58fc94 | 12951 | goto ld_st; |
252b5132 | 12952 | } |
252b5132 | 12953 | s = "sw"; |
252b5132 RH |
12954 | |
12955 | ldd_std: | |
f2ae14a1 RS |
12956 | /* Even on a big endian machine $fn comes before $fn+1. We have |
12957 | to adjust when loading from memory. We set coproc if we must | |
12958 | load $fn+1 first. */ | |
12959 | /* Itbl support may require additional care here. */ | |
12960 | if (!target_big_endian) | |
12961 | coproc = 0; | |
12962 | ||
c0ebe874 | 12963 | breg = op[2]; |
f2ae14a1 RS |
12964 | if (small_offset_p (0, align, 16)) |
12965 | { | |
12966 | ep = &offset_expr; | |
12967 | if (!small_offset_p (4, align, 16)) | |
12968 | { | |
12969 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg, | |
12970 | -1, offset_reloc[0], offset_reloc[1], | |
12971 | offset_reloc[2]); | |
12972 | expr1.X_add_number = 0; | |
12973 | ep = &expr1; | |
12974 | breg = AT; | |
12975 | used_at = 1; | |
12976 | offset_reloc[0] = BFD_RELOC_LO16; | |
12977 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12978 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12979 | } | |
c0ebe874 | 12980 | if (strcmp (s, "lw") == 0 && op[0] == breg) |
f2ae14a1 RS |
12981 | { |
12982 | ep->X_add_number += 4; | |
c0ebe874 | 12983 | macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0], |
f2ae14a1 RS |
12984 | offset_reloc[1], offset_reloc[2], breg); |
12985 | ep->X_add_number -= 4; | |
c0ebe874 | 12986 | macro_build (ep, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
12987 | offset_reloc[1], offset_reloc[2], breg); |
12988 | } | |
12989 | else | |
12990 | { | |
c0ebe874 | 12991 | macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1, |
f2ae14a1 RS |
12992 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
12993 | breg); | |
12994 | ep->X_add_number += 4; | |
c0ebe874 | 12995 | macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1, |
f2ae14a1 RS |
12996 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
12997 | breg); | |
12998 | } | |
12999 | break; | |
13000 | } | |
13001 | ||
252b5132 RH |
13002 | if (offset_expr.X_op != O_symbol |
13003 | && offset_expr.X_op != O_constant) | |
13004 | { | |
1661c76c | 13005 | as_bad (_("expression too complex")); |
252b5132 RH |
13006 | offset_expr.X_op = O_constant; |
13007 | } | |
13008 | ||
2051e8c4 MR |
13009 | if (HAVE_32BIT_ADDRESSES |
13010 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
13011 | { |
13012 | char value [32]; | |
13013 | ||
13014 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 13015 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 13016 | } |
2051e8c4 | 13017 | |
90ecf173 | 13018 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
13019 | { |
13020 | /* If this is a reference to a GP relative symbol, we want | |
c0ebe874 RS |
13021 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
13022 | <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
13023 | If we have a base register, we use this |
13024 | addu $at,$breg,$gp | |
c0ebe874 RS |
13025 | <op> op[0],<sym>($at) (BFD_RELOC_GPREL16) |
13026 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
13027 | If this is not a GP relative symbol, we want |
13028 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 RS |
13029 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
13030 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
13031 | If there is a base register, we add it to $at after the |
13032 | lui instruction. If there is a constant, we always use | |
13033 | the last case. */ | |
39a59cf8 MR |
13034 | if (offset_expr.X_op == O_symbol |
13035 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 13036 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 13037 | { |
4d7206a2 | 13038 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
13039 | if (breg == 0) |
13040 | { | |
c9914766 | 13041 | tempreg = mips_gp_register; |
252b5132 RH |
13042 | } |
13043 | else | |
13044 | { | |
67c0d1eb | 13045 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 13046 | AT, breg, mips_gp_register); |
252b5132 | 13047 | tempreg = AT; |
252b5132 RH |
13048 | used_at = 1; |
13049 | } | |
13050 | ||
beae10d5 | 13051 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13052 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 13053 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
13054 | offset_expr.X_add_number += 4; |
13055 | ||
13056 | /* Set mips_optimize to 2 to avoid inserting an | |
13057 | undesired nop. */ | |
13058 | hold_mips_optimize = mips_optimize; | |
13059 | mips_optimize = 2; | |
beae10d5 | 13060 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13061 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 13062 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
13063 | mips_optimize = hold_mips_optimize; |
13064 | ||
4d7206a2 | 13065 | relax_switch (); |
252b5132 | 13066 | |
0970e49e | 13067 | offset_expr.X_add_number -= 4; |
252b5132 | 13068 | } |
8fc2e39e | 13069 | used_at = 1; |
f2ae14a1 RS |
13070 | if (offset_high_part (offset_expr.X_add_number, 16) |
13071 | != offset_high_part (offset_expr.X_add_number + 4, 16)) | |
13072 | { | |
13073 | load_address (AT, &offset_expr, &used_at); | |
13074 | offset_expr.X_op = O_constant; | |
13075 | offset_expr.X_add_number = 0; | |
13076 | } | |
13077 | else | |
13078 | macro_build_lui (&offset_expr, AT); | |
252b5132 | 13079 | if (breg != 0) |
67c0d1eb | 13080 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 13081 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13082 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 13083 | BFD_RELOC_LO16, AT); |
252b5132 RH |
13084 | /* FIXME: How do we handle overflow here? */ |
13085 | offset_expr.X_add_number += 4; | |
beae10d5 | 13086 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13087 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 13088 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
13089 | if (mips_relax.sequence) |
13090 | relax_end (); | |
bdaaa2e1 | 13091 | } |
0a44bf69 | 13092 | else if (!mips_big_got) |
252b5132 | 13093 | { |
252b5132 RH |
13094 | /* If this is a reference to an external symbol, we want |
13095 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
13096 | nop | |
c0ebe874 RS |
13097 | <op> op[0],0($at) |
13098 | <op> op[0]+1,4($at) | |
252b5132 RH |
13099 | Otherwise we want |
13100 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
13101 | nop | |
c0ebe874 RS |
13102 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
13103 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
13104 | If there is a base register we add it to $at before the |
13105 | lwc1 instructions. If there is a constant we include it | |
13106 | in the lwc1 instructions. */ | |
13107 | used_at = 1; | |
13108 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
13109 | if (expr1.X_add_number < -0x8000 |
13110 | || expr1.X_add_number >= 0x8000 - 4) | |
13111 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 13112 | load_got_offset (AT, &offset_expr); |
269137b2 | 13113 | load_delay_nop (); |
252b5132 | 13114 | if (breg != 0) |
67c0d1eb | 13115 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
13116 | |
13117 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
13118 | nop. */ | |
13119 | hold_mips_optimize = mips_optimize; | |
13120 | mips_optimize = 2; | |
4d7206a2 | 13121 | |
beae10d5 | 13122 | /* Itbl support may require additional care here. */ |
4d7206a2 | 13123 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 13124 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 13125 | BFD_RELOC_LO16, AT); |
4d7206a2 | 13126 | expr1.X_add_number += 4; |
c0ebe874 | 13127 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 13128 | BFD_RELOC_LO16, AT); |
4d7206a2 | 13129 | relax_switch (); |
c0ebe874 | 13130 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 13131 | BFD_RELOC_LO16, AT); |
4d7206a2 | 13132 | offset_expr.X_add_number += 4; |
c0ebe874 | 13133 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 13134 | BFD_RELOC_LO16, AT); |
4d7206a2 | 13135 | relax_end (); |
252b5132 | 13136 | |
4d7206a2 | 13137 | mips_optimize = hold_mips_optimize; |
252b5132 | 13138 | } |
0a44bf69 | 13139 | else if (mips_big_got) |
252b5132 | 13140 | { |
67c0d1eb | 13141 | int gpdelay; |
252b5132 RH |
13142 | |
13143 | /* If this is a reference to an external symbol, we want | |
13144 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
13145 | addu $at,$at,$gp | |
13146 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
13147 | nop | |
c0ebe874 RS |
13148 | <op> op[0],0($at) |
13149 | <op> op[0]+1,4($at) | |
252b5132 RH |
13150 | Otherwise we want |
13151 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
13152 | nop | |
c0ebe874 RS |
13153 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
13154 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
13155 | If there is a base register we add it to $at before the |
13156 | lwc1 instructions. If there is a constant we include it | |
13157 | in the lwc1 instructions. */ | |
13158 | used_at = 1; | |
13159 | expr1.X_add_number = offset_expr.X_add_number; | |
13160 | offset_expr.X_add_number = 0; | |
13161 | if (expr1.X_add_number < -0x8000 | |
13162 | || expr1.X_add_number >= 0x8000 - 4) | |
13163 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 13164 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 13165 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 13166 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
13167 | AT, BFD_RELOC_MIPS_GOT_HI16); |
13168 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 13169 | AT, AT, mips_gp_register); |
67c0d1eb | 13170 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 13171 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 13172 | load_delay_nop (); |
252b5132 | 13173 | if (breg != 0) |
67c0d1eb | 13174 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 13175 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13176 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 13177 | BFD_RELOC_LO16, AT); |
252b5132 RH |
13178 | expr1.X_add_number += 4; |
13179 | ||
13180 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
13181 | nop. */ | |
13182 | hold_mips_optimize = mips_optimize; | |
13183 | mips_optimize = 2; | |
beae10d5 | 13184 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13185 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 13186 | BFD_RELOC_LO16, AT); |
252b5132 RH |
13187 | mips_optimize = hold_mips_optimize; |
13188 | expr1.X_add_number -= 4; | |
13189 | ||
4d7206a2 RS |
13190 | relax_switch (); |
13191 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
13192 | if (gpdelay) |
13193 | macro_build (NULL, "nop", ""); | |
13194 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
13195 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 13196 | load_delay_nop (); |
252b5132 | 13197 | if (breg != 0) |
67c0d1eb | 13198 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 13199 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13200 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 13201 | BFD_RELOC_LO16, AT); |
4d7206a2 | 13202 | offset_expr.X_add_number += 4; |
252b5132 RH |
13203 | |
13204 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
13205 | nop. */ | |
13206 | hold_mips_optimize = mips_optimize; | |
13207 | mips_optimize = 2; | |
beae10d5 | 13208 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13209 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 13210 | BFD_RELOC_LO16, AT); |
252b5132 | 13211 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 13212 | relax_end (); |
252b5132 | 13213 | } |
252b5132 RH |
13214 | else |
13215 | abort (); | |
13216 | ||
252b5132 | 13217 | break; |
3739860c | 13218 | |
dd6a37e7 | 13219 | case M_SAA_AB: |
dd6a37e7 | 13220 | s = "saa"; |
0db377d0 | 13221 | goto saa_saad; |
dd6a37e7 | 13222 | case M_SAAD_AB: |
dd6a37e7 | 13223 | s = "saad"; |
0db377d0 MR |
13224 | saa_saad: |
13225 | gas_assert (!mips_opts.micromips); | |
7f3c4072 | 13226 | offbits = 0; |
dd6a37e7 AP |
13227 | fmt = "t,(b)"; |
13228 | goto ld_st; | |
13229 | ||
252b5132 RH |
13230 | /* New code added to support COPZ instructions. |
13231 | This code builds table entries out of the macros in mip_opcodes. | |
13232 | R4000 uses interlocks to handle coproc delays. | |
13233 | Other chips (like the R3000) require nops to be inserted for delays. | |
13234 | ||
f72c8c98 | 13235 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
13236 | In order to fill delay slots for non-interlocked chips, |
13237 | we must have a way to specify delays based on the coprocessor. | |
13238 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
13239 | What are the side-effects of the cop instruction? | |
13240 | What cache support might we have and what are its effects? | |
13241 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 13242 | What registers are read/set/modified? |
252b5132 RH |
13243 | |
13244 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 13245 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
13246 | |
13247 | case M_COP0: | |
13248 | s = "c0"; | |
13249 | goto copz; | |
13250 | case M_COP1: | |
13251 | s = "c1"; | |
13252 | goto copz; | |
13253 | case M_COP2: | |
13254 | s = "c2"; | |
13255 | goto copz; | |
13256 | case M_COP3: | |
13257 | s = "c3"; | |
13258 | copz: | |
df58fc94 | 13259 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
13260 | /* For now we just do C (same as Cz). The parameter will be |
13261 | stored in insn_opcode by mips_ip. */ | |
c8276761 | 13262 | macro_build (NULL, s, "C", (int) ip->insn_opcode); |
8fc2e39e | 13263 | break; |
252b5132 | 13264 | |
ea1fb5dc | 13265 | case M_MOVE: |
c0ebe874 | 13266 | move_register (op[0], op[1]); |
8fc2e39e | 13267 | break; |
ea1fb5dc | 13268 | |
833794fc MR |
13269 | case M_MOVEP: |
13270 | gas_assert (mips_opts.micromips); | |
13271 | gas_assert (mips_opts.insn32); | |
c0ebe874 RS |
13272 | move_register (micromips_to_32_reg_h_map1[op[0]], |
13273 | micromips_to_32_reg_m_map[op[1]]); | |
13274 | move_register (micromips_to_32_reg_h_map2[op[0]], | |
13275 | micromips_to_32_reg_n_map[op[2]]); | |
833794fc MR |
13276 | break; |
13277 | ||
252b5132 RH |
13278 | case M_DMUL: |
13279 | dbl = 1; | |
1a0670f3 | 13280 | /* Fall through. */ |
252b5132 | 13281 | case M_MUL: |
e407c74b | 13282 | if (mips_opts.arch == CPU_R5900) |
c0ebe874 RS |
13283 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1], |
13284 | op[2]); | |
e407c74b NC |
13285 | else |
13286 | { | |
c0ebe874 RS |
13287 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]); |
13288 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
e407c74b | 13289 | } |
8fc2e39e | 13290 | break; |
252b5132 RH |
13291 | |
13292 | case M_DMUL_I: | |
13293 | dbl = 1; | |
1a0670f3 | 13294 | /* Fall through. */ |
252b5132 RH |
13295 | case M_MUL_I: |
13296 | /* The MIPS assembler some times generates shifts and adds. I'm | |
13297 | not trying to be that fancy. GCC should do this for us | |
13298 | anyway. */ | |
8fc2e39e | 13299 | used_at = 1; |
67c0d1eb | 13300 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
13301 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT); |
13302 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
252b5132 RH |
13303 | break; |
13304 | ||
13305 | case M_DMULO_I: | |
13306 | dbl = 1; | |
1a0670f3 | 13307 | /* Fall through. */ |
252b5132 RH |
13308 | case M_MULO_I: |
13309 | imm = 1; | |
13310 | goto do_mulo; | |
13311 | ||
13312 | case M_DMULO: | |
13313 | dbl = 1; | |
1a0670f3 | 13314 | /* Fall through. */ |
252b5132 RH |
13315 | case M_MULO: |
13316 | do_mulo: | |
7d10b47d | 13317 | start_noreorder (); |
8fc2e39e | 13318 | used_at = 1; |
252b5132 | 13319 | if (imm) |
67c0d1eb | 13320 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
13321 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", |
13322 | op[1], imm ? AT : op[2]); | |
13323 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
13324 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31); | |
df58fc94 | 13325 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
252b5132 | 13326 | if (mips_trap) |
c0ebe874 | 13327 | macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6); |
252b5132 RH |
13328 | else |
13329 | { | |
df58fc94 RS |
13330 | if (mips_opts.micromips) |
13331 | micromips_label_expr (&label_expr); | |
13332 | else | |
13333 | label_expr.X_add_number = 8; | |
c0ebe874 | 13334 | macro_build (&label_expr, "beq", "s,t,p", op[0], AT); |
a605d2b3 | 13335 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
13336 | macro_build (NULL, "break", BRK_FMT, 6); |
13337 | if (mips_opts.micromips) | |
13338 | micromips_add_label (); | |
252b5132 | 13339 | } |
7d10b47d | 13340 | end_noreorder (); |
c0ebe874 | 13341 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 RH |
13342 | break; |
13343 | ||
13344 | case M_DMULOU_I: | |
13345 | dbl = 1; | |
1a0670f3 | 13346 | /* Fall through. */ |
252b5132 RH |
13347 | case M_MULOU_I: |
13348 | imm = 1; | |
13349 | goto do_mulou; | |
13350 | ||
13351 | case M_DMULOU: | |
13352 | dbl = 1; | |
1a0670f3 | 13353 | /* Fall through. */ |
252b5132 RH |
13354 | case M_MULOU: |
13355 | do_mulou: | |
7d10b47d | 13356 | start_noreorder (); |
8fc2e39e | 13357 | used_at = 1; |
252b5132 | 13358 | if (imm) |
67c0d1eb RS |
13359 | load_register (AT, &imm_expr, dbl); |
13360 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
c0ebe874 | 13361 | op[1], imm ? AT : op[2]); |
df58fc94 | 13362 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
c0ebe874 | 13363 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 | 13364 | if (mips_trap) |
df58fc94 | 13365 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
13366 | else |
13367 | { | |
df58fc94 RS |
13368 | if (mips_opts.micromips) |
13369 | micromips_label_expr (&label_expr); | |
13370 | else | |
13371 | label_expr.X_add_number = 8; | |
13372 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 13373 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
13374 | macro_build (NULL, "break", BRK_FMT, 6); |
13375 | if (mips_opts.micromips) | |
13376 | micromips_add_label (); | |
252b5132 | 13377 | } |
7d10b47d | 13378 | end_noreorder (); |
252b5132 RH |
13379 | break; |
13380 | ||
771c7ce4 | 13381 | case M_DROL: |
fef14a42 | 13382 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 13383 | { |
c0ebe874 | 13384 | if (op[0] == op[1]) |
82dd0097 CD |
13385 | { |
13386 | tempreg = AT; | |
13387 | used_at = 1; | |
13388 | } | |
13389 | else | |
c0ebe874 RS |
13390 | tempreg = op[0]; |
13391 | macro_build (NULL, "dnegu", "d,w", tempreg, op[2]); | |
13392 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 13393 | break; |
82dd0097 | 13394 | } |
8fc2e39e | 13395 | used_at = 1; |
c0ebe874 RS |
13396 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
13397 | macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT); | |
13398 | macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]); | |
13399 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13400 | break; |
13401 | ||
252b5132 | 13402 | case M_ROL: |
fef14a42 | 13403 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13404 | { |
c0ebe874 | 13405 | if (op[0] == op[1]) |
82dd0097 CD |
13406 | { |
13407 | tempreg = AT; | |
13408 | used_at = 1; | |
13409 | } | |
13410 | else | |
c0ebe874 RS |
13411 | tempreg = op[0]; |
13412 | macro_build (NULL, "negu", "d,w", tempreg, op[2]); | |
13413 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 13414 | break; |
82dd0097 | 13415 | } |
8fc2e39e | 13416 | used_at = 1; |
c0ebe874 RS |
13417 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
13418 | macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT); | |
13419 | macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]); | |
13420 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13421 | break; |
13422 | ||
771c7ce4 TS |
13423 | case M_DROL_I: |
13424 | { | |
13425 | unsigned int rot; | |
e0471c16 TS |
13426 | const char *l; |
13427 | const char *rr; | |
771c7ce4 | 13428 | |
771c7ce4 | 13429 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 13430 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
13431 | { |
13432 | rot = (64 - rot) & 0x3f; | |
13433 | if (rot >= 32) | |
c0ebe874 | 13434 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
60b63b72 | 13435 | else |
c0ebe874 | 13436 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13437 | break; |
60b63b72 | 13438 | } |
483fc7cd | 13439 | if (rot == 0) |
483fc7cd | 13440 | { |
c0ebe874 | 13441 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13442 | break; |
483fc7cd | 13443 | } |
82dd0097 | 13444 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 13445 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 13446 | rot &= 0x1f; |
8fc2e39e | 13447 | used_at = 1; |
c0ebe874 RS |
13448 | macro_build (NULL, l, SHFT_FMT, AT, op[1], rot); |
13449 | macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13450 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13451 | } |
13452 | break; | |
13453 | ||
252b5132 | 13454 | case M_ROL_I: |
771c7ce4 TS |
13455 | { |
13456 | unsigned int rot; | |
13457 | ||
771c7ce4 | 13458 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 13459 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 13460 | { |
c0ebe874 RS |
13461 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], |
13462 | (32 - rot) & 0x1f); | |
8fc2e39e | 13463 | break; |
60b63b72 | 13464 | } |
483fc7cd | 13465 | if (rot == 0) |
483fc7cd | 13466 | { |
c0ebe874 | 13467 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13468 | break; |
483fc7cd | 13469 | } |
8fc2e39e | 13470 | used_at = 1; |
c0ebe874 RS |
13471 | macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot); |
13472 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13473 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13474 | } |
13475 | break; | |
13476 | ||
13477 | case M_DROR: | |
fef14a42 | 13478 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 13479 | { |
c0ebe874 | 13480 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 13481 | break; |
82dd0097 | 13482 | } |
8fc2e39e | 13483 | used_at = 1; |
c0ebe874 RS |
13484 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
13485 | macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT); | |
13486 | macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]); | |
13487 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13488 | break; |
13489 | ||
13490 | case M_ROR: | |
fef14a42 | 13491 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13492 | { |
c0ebe874 | 13493 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 13494 | break; |
82dd0097 | 13495 | } |
8fc2e39e | 13496 | used_at = 1; |
c0ebe874 RS |
13497 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
13498 | macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT); | |
13499 | macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]); | |
13500 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13501 | break; |
13502 | ||
771c7ce4 TS |
13503 | case M_DROR_I: |
13504 | { | |
13505 | unsigned int rot; | |
e0471c16 TS |
13506 | const char *l; |
13507 | const char *rr; | |
771c7ce4 | 13508 | |
771c7ce4 | 13509 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 13510 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
13511 | { |
13512 | if (rot >= 32) | |
c0ebe874 | 13513 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
82dd0097 | 13514 | else |
c0ebe874 | 13515 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13516 | break; |
82dd0097 | 13517 | } |
483fc7cd | 13518 | if (rot == 0) |
483fc7cd | 13519 | { |
c0ebe874 | 13520 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13521 | break; |
483fc7cd | 13522 | } |
91d6fa6a | 13523 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
13524 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
13525 | rot &= 0x1f; | |
8fc2e39e | 13526 | used_at = 1; |
c0ebe874 RS |
13527 | macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot); |
13528 | macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13529 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13530 | } |
13531 | break; | |
13532 | ||
252b5132 | 13533 | case M_ROR_I: |
771c7ce4 TS |
13534 | { |
13535 | unsigned int rot; | |
13536 | ||
771c7ce4 | 13537 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 13538 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13539 | { |
c0ebe874 | 13540 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13541 | break; |
82dd0097 | 13542 | } |
483fc7cd | 13543 | if (rot == 0) |
483fc7cd | 13544 | { |
c0ebe874 | 13545 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13546 | break; |
483fc7cd | 13547 | } |
8fc2e39e | 13548 | used_at = 1; |
c0ebe874 RS |
13549 | macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot); |
13550 | macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13551 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 | 13552 | } |
252b5132 RH |
13553 | break; |
13554 | ||
252b5132 | 13555 | case M_SEQ: |
c0ebe874 RS |
13556 | if (op[1] == 0) |
13557 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16); | |
13558 | else if (op[2] == 0) | |
13559 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
13560 | else |
13561 | { | |
c0ebe874 RS |
13562 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
13563 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 | 13564 | } |
8fc2e39e | 13565 | break; |
252b5132 RH |
13566 | |
13567 | case M_SEQ_I: | |
b0e6f033 | 13568 | if (imm_expr.X_add_number == 0) |
252b5132 | 13569 | { |
c0ebe874 | 13570 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 13571 | break; |
252b5132 | 13572 | } |
c0ebe874 | 13573 | if (op[1] == 0) |
252b5132 | 13574 | { |
1661c76c | 13575 | as_warn (_("instruction %s: result is always false"), |
252b5132 | 13576 | ip->insn_mo->name); |
c0ebe874 | 13577 | move_register (op[0], 0); |
8fc2e39e | 13578 | break; |
252b5132 | 13579 | } |
dd3cbb7e NC |
13580 | if (CPU_HAS_SEQ (mips_opts.arch) |
13581 | && -512 <= imm_expr.X_add_number | |
13582 | && imm_expr.X_add_number < 512) | |
13583 | { | |
c0ebe874 | 13584 | macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1], |
750bdd57 | 13585 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
13586 | break; |
13587 | } | |
b0e6f033 | 13588 | if (imm_expr.X_add_number >= 0 |
252b5132 | 13589 | && imm_expr.X_add_number < 0x10000) |
c0ebe874 | 13590 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
b0e6f033 | 13591 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13592 | && imm_expr.X_add_number < 0) |
13593 | { | |
13594 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 13595 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 13596 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 13597 | } |
dd3cbb7e NC |
13598 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
13599 | { | |
13600 | used_at = 1; | |
bad1aba3 | 13601 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13602 | macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
13603 | break; |
13604 | } | |
252b5132 RH |
13605 | else |
13606 | { | |
bad1aba3 | 13607 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13608 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13609 | used_at = 1; |
13610 | } | |
c0ebe874 | 13611 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 13612 | break; |
252b5132 | 13613 | |
c0ebe874 | 13614 | case M_SGE: /* X >= Y <==> not (X < Y) */ |
252b5132 RH |
13615 | s = "slt"; |
13616 | goto sge; | |
13617 | case M_SGEU: | |
13618 | s = "sltu"; | |
13619 | sge: | |
c0ebe874 RS |
13620 | macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]); |
13621 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 13622 | break; |
252b5132 | 13623 | |
6f2117ba | 13624 | case M_SGE_I: /* X >= I <==> not (X < I). */ |
252b5132 | 13625 | case M_SGEU_I: |
b0e6f033 | 13626 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 13627 | && imm_expr.X_add_number < 0x8000) |
c0ebe874 RS |
13628 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
13629 | op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
13630 | else |
13631 | { | |
bad1aba3 | 13632 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 13633 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", |
c0ebe874 | 13634 | op[0], op[1], AT); |
252b5132 RH |
13635 | used_at = 1; |
13636 | } | |
c0ebe874 | 13637 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 13638 | break; |
252b5132 | 13639 | |
6f2117ba | 13640 | case M_SGT: /* X > Y <==> Y < X. */ |
252b5132 RH |
13641 | s = "slt"; |
13642 | goto sgt; | |
13643 | case M_SGTU: | |
13644 | s = "sltu"; | |
13645 | sgt: | |
c0ebe874 | 13646 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
8fc2e39e | 13647 | break; |
252b5132 | 13648 | |
6f2117ba | 13649 | case M_SGT_I: /* X > I <==> I < X. */ |
252b5132 RH |
13650 | s = "slt"; |
13651 | goto sgti; | |
13652 | case M_SGTU_I: | |
13653 | s = "sltu"; | |
13654 | sgti: | |
8fc2e39e | 13655 | used_at = 1; |
bad1aba3 | 13656 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13657 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
252b5132 RH |
13658 | break; |
13659 | ||
6f2117ba | 13660 | case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X). */ |
252b5132 RH |
13661 | s = "slt"; |
13662 | goto sle; | |
13663 | case M_SLEU: | |
13664 | s = "sltu"; | |
13665 | sle: | |
c0ebe874 RS |
13666 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
13667 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 13668 | break; |
252b5132 | 13669 | |
c0ebe874 | 13670 | case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */ |
252b5132 RH |
13671 | s = "slt"; |
13672 | goto slei; | |
13673 | case M_SLEU_I: | |
13674 | s = "sltu"; | |
13675 | slei: | |
8fc2e39e | 13676 | used_at = 1; |
bad1aba3 | 13677 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 RS |
13678 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
13679 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 RH |
13680 | break; |
13681 | ||
13682 | case M_SLT_I: | |
b0e6f033 | 13683 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
13684 | && imm_expr.X_add_number < 0x8000) |
13685 | { | |
c0ebe874 RS |
13686 | macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1], |
13687 | BFD_RELOC_LO16); | |
8fc2e39e | 13688 | break; |
252b5132 | 13689 | } |
8fc2e39e | 13690 | used_at = 1; |
bad1aba3 | 13691 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13692 | macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13693 | break; |
13694 | ||
13695 | case M_SLTU_I: | |
b0e6f033 | 13696 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
13697 | && imm_expr.X_add_number < 0x8000) |
13698 | { | |
c0ebe874 | 13699 | macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1], |
17a2f251 | 13700 | BFD_RELOC_LO16); |
8fc2e39e | 13701 | break; |
252b5132 | 13702 | } |
8fc2e39e | 13703 | used_at = 1; |
bad1aba3 | 13704 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13705 | macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13706 | break; |
13707 | ||
13708 | case M_SNE: | |
c0ebe874 RS |
13709 | if (op[1] == 0) |
13710 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]); | |
13711 | else if (op[2] == 0) | |
13712 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); | |
252b5132 RH |
13713 | else |
13714 | { | |
c0ebe874 RS |
13715 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
13716 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); | |
252b5132 | 13717 | } |
8fc2e39e | 13718 | break; |
252b5132 RH |
13719 | |
13720 | case M_SNE_I: | |
b0e6f033 | 13721 | if (imm_expr.X_add_number == 0) |
252b5132 | 13722 | { |
c0ebe874 | 13723 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); |
8fc2e39e | 13724 | break; |
252b5132 | 13725 | } |
c0ebe874 | 13726 | if (op[1] == 0) |
252b5132 | 13727 | { |
1661c76c | 13728 | as_warn (_("instruction %s: result is always true"), |
252b5132 | 13729 | ip->insn_mo->name); |
bad1aba3 | 13730 | macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j", |
c0ebe874 | 13731 | op[0], 0, BFD_RELOC_LO16); |
8fc2e39e | 13732 | break; |
252b5132 | 13733 | } |
dd3cbb7e NC |
13734 | if (CPU_HAS_SEQ (mips_opts.arch) |
13735 | && -512 <= imm_expr.X_add_number | |
13736 | && imm_expr.X_add_number < 512) | |
13737 | { | |
c0ebe874 | 13738 | macro_build (NULL, "snei", "t,r,+Q", op[0], op[1], |
750bdd57 | 13739 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
13740 | break; |
13741 | } | |
b0e6f033 | 13742 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
13743 | && imm_expr.X_add_number < 0x10000) |
13744 | { | |
c0ebe874 RS |
13745 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], |
13746 | BFD_RELOC_LO16); | |
252b5132 | 13747 | } |
b0e6f033 | 13748 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13749 | && imm_expr.X_add_number < 0) |
13750 | { | |
13751 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 13752 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 13753 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 13754 | } |
dd3cbb7e NC |
13755 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
13756 | { | |
13757 | used_at = 1; | |
bad1aba3 | 13758 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13759 | macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
13760 | break; |
13761 | } | |
252b5132 RH |
13762 | else |
13763 | { | |
bad1aba3 | 13764 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13765 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13766 | used_at = 1; |
13767 | } | |
c0ebe874 | 13768 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); |
8fc2e39e | 13769 | break; |
252b5132 | 13770 | |
df58fc94 RS |
13771 | case M_SUB_I: |
13772 | s = "addi"; | |
13773 | s2 = "sub"; | |
387e7624 FS |
13774 | if (ISA_IS_R6 (mips_opts.isa)) |
13775 | goto do_subi_i; | |
13776 | else | |
13777 | goto do_subi; | |
df58fc94 RS |
13778 | case M_SUBU_I: |
13779 | s = "addiu"; | |
13780 | s2 = "subu"; | |
13781 | goto do_subi; | |
252b5132 RH |
13782 | case M_DSUB_I: |
13783 | dbl = 1; | |
df58fc94 RS |
13784 | s = "daddi"; |
13785 | s2 = "dsub"; | |
387e7624 | 13786 | if (!mips_opts.micromips && !ISA_IS_R6 (mips_opts.isa)) |
df58fc94 | 13787 | goto do_subi; |
b0e6f033 | 13788 | if (imm_expr.X_add_number > -0x200 |
387e7624 FS |
13789 | && imm_expr.X_add_number <= 0x200 |
13790 | && !ISA_IS_R6 (mips_opts.isa)) | |
252b5132 | 13791 | { |
b0e6f033 RS |
13792 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
13793 | (int) -imm_expr.X_add_number); | |
8fc2e39e | 13794 | break; |
252b5132 | 13795 | } |
df58fc94 | 13796 | goto do_subi_i; |
252b5132 RH |
13797 | case M_DSUBU_I: |
13798 | dbl = 1; | |
df58fc94 RS |
13799 | s = "daddiu"; |
13800 | s2 = "dsubu"; | |
13801 | do_subi: | |
b0e6f033 | 13802 | if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13803 | && imm_expr.X_add_number <= 0x8000) |
13804 | { | |
13805 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
c0ebe874 | 13806 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 13807 | break; |
252b5132 | 13808 | } |
df58fc94 | 13809 | do_subi_i: |
8fc2e39e | 13810 | used_at = 1; |
67c0d1eb | 13811 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 13812 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13813 | break; |
13814 | ||
13815 | case M_TEQ_I: | |
13816 | s = "teq"; | |
13817 | goto trap; | |
13818 | case M_TGE_I: | |
13819 | s = "tge"; | |
13820 | goto trap; | |
13821 | case M_TGEU_I: | |
13822 | s = "tgeu"; | |
13823 | goto trap; | |
13824 | case M_TLT_I: | |
13825 | s = "tlt"; | |
13826 | goto trap; | |
13827 | case M_TLTU_I: | |
13828 | s = "tltu"; | |
13829 | goto trap; | |
13830 | case M_TNE_I: | |
13831 | s = "tne"; | |
13832 | trap: | |
8fc2e39e | 13833 | used_at = 1; |
bad1aba3 | 13834 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13835 | macro_build (NULL, s, "s,t", op[0], AT); |
252b5132 RH |
13836 | break; |
13837 | ||
252b5132 | 13838 | case M_TRUNCWS: |
43841e91 | 13839 | case M_TRUNCWD: |
df58fc94 | 13840 | gas_assert (!mips_opts.micromips); |
0aa27725 | 13841 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 13842 | used_at = 1; |
252b5132 RH |
13843 | |
13844 | /* | |
13845 | * Is the double cfc1 instruction a bug in the mips assembler; | |
13846 | * or is there a reason for it? | |
13847 | */ | |
7d10b47d | 13848 | start_noreorder (); |
c0ebe874 RS |
13849 | macro_build (NULL, "cfc1", "t,G", op[2], RA); |
13850 | macro_build (NULL, "cfc1", "t,G", op[2], RA); | |
67c0d1eb | 13851 | macro_build (NULL, "nop", ""); |
252b5132 | 13852 | expr1.X_add_number = 3; |
c0ebe874 | 13853 | macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16); |
252b5132 | 13854 | expr1.X_add_number = 2; |
67c0d1eb RS |
13855 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
13856 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
13857 | macro_build (NULL, "nop", ""); | |
13858 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
c0ebe874 RS |
13859 | op[0], op[1]); |
13860 | macro_build (NULL, "ctc1", "t,G", op[2], RA); | |
67c0d1eb | 13861 | macro_build (NULL, "nop", ""); |
7d10b47d | 13862 | end_noreorder (); |
252b5132 RH |
13863 | break; |
13864 | ||
f2ae14a1 | 13865 | case M_ULH_AB: |
252b5132 | 13866 | s = "lb"; |
df58fc94 RS |
13867 | s2 = "lbu"; |
13868 | off = 1; | |
13869 | goto uld_st; | |
f2ae14a1 | 13870 | case M_ULHU_AB: |
252b5132 | 13871 | s = "lbu"; |
df58fc94 RS |
13872 | s2 = "lbu"; |
13873 | off = 1; | |
13874 | goto uld_st; | |
f2ae14a1 | 13875 | case M_ULW_AB: |
df58fc94 RS |
13876 | s = "lwl"; |
13877 | s2 = "lwr"; | |
7f3c4072 | 13878 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
13879 | off = 3; |
13880 | goto uld_st; | |
f2ae14a1 | 13881 | case M_ULD_AB: |
252b5132 RH |
13882 | s = "ldl"; |
13883 | s2 = "ldr"; | |
7f3c4072 | 13884 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 13885 | off = 7; |
df58fc94 | 13886 | goto uld_st; |
f2ae14a1 | 13887 | case M_USH_AB: |
df58fc94 RS |
13888 | s = "sb"; |
13889 | s2 = "sb"; | |
13890 | off = 1; | |
13891 | ust = 1; | |
13892 | goto uld_st; | |
f2ae14a1 | 13893 | case M_USW_AB: |
df58fc94 RS |
13894 | s = "swl"; |
13895 | s2 = "swr"; | |
7f3c4072 | 13896 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 13897 | off = 3; |
df58fc94 RS |
13898 | ust = 1; |
13899 | goto uld_st; | |
f2ae14a1 | 13900 | case M_USD_AB: |
df58fc94 RS |
13901 | s = "sdl"; |
13902 | s2 = "sdr"; | |
7f3c4072 | 13903 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
13904 | off = 7; |
13905 | ust = 1; | |
13906 | ||
13907 | uld_st: | |
c0ebe874 | 13908 | breg = op[2]; |
f2ae14a1 | 13909 | large_offset = !small_offset_p (off, align, offbits); |
df58fc94 RS |
13910 | ep = &offset_expr; |
13911 | expr1.X_add_number = 0; | |
f2ae14a1 | 13912 | if (large_offset) |
df58fc94 RS |
13913 | { |
13914 | used_at = 1; | |
13915 | tempreg = AT; | |
f2ae14a1 RS |
13916 | if (small_offset_p (0, align, 16)) |
13917 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1, | |
13918 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
13919 | else | |
13920 | { | |
13921 | load_address (tempreg, ep, &used_at); | |
13922 | if (breg != 0) | |
13923 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
13924 | tempreg, tempreg, breg); | |
13925 | } | |
13926 | offset_reloc[0] = BFD_RELOC_LO16; | |
13927 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13928 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
df58fc94 | 13929 | breg = tempreg; |
c0ebe874 | 13930 | tempreg = op[0]; |
df58fc94 RS |
13931 | ep = &expr1; |
13932 | } | |
c0ebe874 | 13933 | else if (!ust && op[0] == breg) |
8fc2e39e TS |
13934 | { |
13935 | used_at = 1; | |
13936 | tempreg = AT; | |
13937 | } | |
252b5132 | 13938 | else |
c0ebe874 | 13939 | tempreg = op[0]; |
af22f5b2 | 13940 | |
df58fc94 RS |
13941 | if (off == 1) |
13942 | goto ulh_sh; | |
252b5132 | 13943 | |
90ecf173 | 13944 | if (!target_big_endian) |
df58fc94 | 13945 | ep->X_add_number += off; |
f2ae14a1 | 13946 | if (offbits == 12) |
c8276761 | 13947 | macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
13948 | else |
13949 | macro_build (ep, s, "t,o(b)", tempreg, -1, | |
13950 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 | 13951 | |
90ecf173 | 13952 | if (!target_big_endian) |
df58fc94 | 13953 | ep->X_add_number -= off; |
252b5132 | 13954 | else |
df58fc94 | 13955 | ep->X_add_number += off; |
f2ae14a1 | 13956 | if (offbits == 12) |
df58fc94 | 13957 | macro_build (NULL, s2, "t,~(b)", |
c8276761 | 13958 | tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
13959 | else |
13960 | macro_build (ep, s2, "t,o(b)", tempreg, -1, | |
13961 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 13962 | |
df58fc94 | 13963 | /* If necessary, move the result in tempreg to the final destination. */ |
c0ebe874 | 13964 | if (!ust && op[0] != tempreg) |
df58fc94 RS |
13965 | { |
13966 | /* Protect second load's delay slot. */ | |
13967 | load_delay_nop (); | |
c0ebe874 | 13968 | move_register (op[0], tempreg); |
df58fc94 | 13969 | } |
8fc2e39e | 13970 | break; |
252b5132 | 13971 | |
df58fc94 | 13972 | ulh_sh: |
d6bc6245 | 13973 | used_at = 1; |
df58fc94 RS |
13974 | if (target_big_endian == ust) |
13975 | ep->X_add_number += off; | |
c0ebe874 | 13976 | tempreg = ust || large_offset ? op[0] : AT; |
f2ae14a1 RS |
13977 | macro_build (ep, s, "t,o(b)", tempreg, -1, |
13978 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 RS |
13979 | |
13980 | /* For halfword transfers we need a temporary register to shuffle | |
13981 | bytes. Unfortunately for M_USH_A we have none available before | |
13982 | the next store as AT holds the base address. We deal with this | |
13983 | case by clobbering TREG and then restoring it as with ULH. */ | |
c0ebe874 | 13984 | tempreg = ust == large_offset ? op[0] : AT; |
df58fc94 | 13985 | if (ust) |
c0ebe874 | 13986 | macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8); |
df58fc94 RS |
13987 | |
13988 | if (target_big_endian == ust) | |
13989 | ep->X_add_number -= off; | |
252b5132 | 13990 | else |
df58fc94 | 13991 | ep->X_add_number += off; |
f2ae14a1 RS |
13992 | macro_build (ep, s2, "t,o(b)", tempreg, -1, |
13993 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 13994 | |
df58fc94 | 13995 | /* For M_USH_A re-retrieve the LSB. */ |
f2ae14a1 | 13996 | if (ust && large_offset) |
df58fc94 RS |
13997 | { |
13998 | if (target_big_endian) | |
13999 | ep->X_add_number += off; | |
14000 | else | |
14001 | ep->X_add_number -= off; | |
f2ae14a1 RS |
14002 | macro_build (&expr1, "lbu", "t,o(b)", AT, -1, |
14003 | offset_reloc[0], offset_reloc[1], offset_reloc[2], AT); | |
df58fc94 RS |
14004 | } |
14005 | /* For ULH and M_USH_A OR the LSB in. */ | |
f2ae14a1 | 14006 | if (!ust || large_offset) |
df58fc94 | 14007 | { |
c0ebe874 | 14008 | tempreg = !large_offset ? AT : op[0]; |
df58fc94 | 14009 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); |
c0ebe874 | 14010 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); |
df58fc94 | 14011 | } |
252b5132 RH |
14012 | break; |
14013 | ||
14014 | default: | |
14015 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 14016 | are added dynamically. */ |
1661c76c | 14017 | as_bad (_("macro %s not implemented yet"), ip->insn_mo->name); |
252b5132 RH |
14018 | break; |
14019 | } | |
741fe287 | 14020 | if (!mips_opts.at && used_at) |
1661c76c | 14021 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
14022 | } |
14023 | ||
14024 | /* Implement macros in mips16 mode. */ | |
14025 | ||
14026 | static void | |
17a2f251 | 14027 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 | 14028 | { |
c0ebe874 | 14029 | const struct mips_operand_array *operands; |
252b5132 | 14030 | int mask; |
c0ebe874 | 14031 | int tmp; |
252b5132 RH |
14032 | expressionS expr1; |
14033 | int dbl; | |
14034 | const char *s, *s2, *s3; | |
c0ebe874 RS |
14035 | unsigned int op[MAX_OPERANDS]; |
14036 | unsigned int i; | |
252b5132 RH |
14037 | |
14038 | mask = ip->insn_mo->mask; | |
14039 | ||
c0ebe874 RS |
14040 | operands = insn_operands (ip); |
14041 | for (i = 0; i < MAX_OPERANDS; i++) | |
14042 | if (operands->operand[i]) | |
14043 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
14044 | else | |
14045 | op[i] = -1; | |
252b5132 | 14046 | |
252b5132 RH |
14047 | expr1.X_op = O_constant; |
14048 | expr1.X_op_symbol = NULL; | |
14049 | expr1.X_add_symbol = NULL; | |
14050 | expr1.X_add_number = 1; | |
14051 | ||
14052 | dbl = 0; | |
14053 | ||
14054 | switch (mask) | |
14055 | { | |
14056 | default: | |
b37df7c4 | 14057 | abort (); |
252b5132 RH |
14058 | |
14059 | case M_DDIV_3: | |
14060 | dbl = 1; | |
1a0670f3 | 14061 | /* Fall through. */ |
252b5132 RH |
14062 | case M_DIV_3: |
14063 | s = "mflo"; | |
14064 | goto do_div3; | |
14065 | case M_DREM_3: | |
14066 | dbl = 1; | |
1a0670f3 | 14067 | /* Fall through. */ |
252b5132 RH |
14068 | case M_REM_3: |
14069 | s = "mfhi"; | |
14070 | do_div3: | |
7d10b47d | 14071 | start_noreorder (); |
d8722d76 | 14072 | macro_build (NULL, dbl ? "ddiv" : "div", ".,x,y", op[1], op[2]); |
252b5132 | 14073 | expr1.X_add_number = 2; |
c0ebe874 | 14074 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 14075 | macro_build (NULL, "break", "6", 7); |
bdaaa2e1 | 14076 | |
252b5132 RH |
14077 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
14078 | since that causes an overflow. We should do that as well, | |
14079 | but I don't see how to do the comparisons without a temporary | |
14080 | register. */ | |
7d10b47d | 14081 | end_noreorder (); |
c0ebe874 | 14082 | macro_build (NULL, s, "x", op[0]); |
252b5132 RH |
14083 | break; |
14084 | ||
14085 | case M_DIVU_3: | |
14086 | s = "divu"; | |
14087 | s2 = "mflo"; | |
14088 | goto do_divu3; | |
14089 | case M_REMU_3: | |
14090 | s = "divu"; | |
14091 | s2 = "mfhi"; | |
14092 | goto do_divu3; | |
14093 | case M_DDIVU_3: | |
14094 | s = "ddivu"; | |
14095 | s2 = "mflo"; | |
14096 | goto do_divu3; | |
14097 | case M_DREMU_3: | |
14098 | s = "ddivu"; | |
14099 | s2 = "mfhi"; | |
14100 | do_divu3: | |
7d10b47d | 14101 | start_noreorder (); |
d8722d76 | 14102 | macro_build (NULL, s, ".,x,y", op[1], op[2]); |
252b5132 | 14103 | expr1.X_add_number = 2; |
c0ebe874 | 14104 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 14105 | macro_build (NULL, "break", "6", 7); |
7d10b47d | 14106 | end_noreorder (); |
c0ebe874 | 14107 | macro_build (NULL, s2, "x", op[0]); |
252b5132 RH |
14108 | break; |
14109 | ||
14110 | case M_DMUL: | |
14111 | dbl = 1; | |
1a0670f3 | 14112 | /* Fall through. */ |
252b5132 | 14113 | case M_MUL: |
c0ebe874 RS |
14114 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]); |
14115 | macro_build (NULL, "mflo", "x", op[0]); | |
8fc2e39e | 14116 | break; |
252b5132 RH |
14117 | |
14118 | case M_DSUBU_I: | |
14119 | dbl = 1; | |
14120 | goto do_subu; | |
14121 | case M_SUBU_I: | |
14122 | do_subu: | |
252b5132 | 14123 | imm_expr.X_add_number = -imm_expr.X_add_number; |
d8722d76 | 14124 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,F", op[0], op[1]); |
252b5132 RH |
14125 | break; |
14126 | ||
14127 | case M_SUBU_I_2: | |
252b5132 | 14128 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 14129 | macro_build (&imm_expr, "addiu", "x,k", op[0]); |
252b5132 RH |
14130 | break; |
14131 | ||
14132 | case M_DSUBU_I_2: | |
252b5132 | 14133 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 14134 | macro_build (&imm_expr, "daddiu", "y,j", op[0]); |
252b5132 RH |
14135 | break; |
14136 | ||
14137 | case M_BEQ: | |
14138 | s = "cmp"; | |
14139 | s2 = "bteqz"; | |
14140 | goto do_branch; | |
14141 | case M_BNE: | |
14142 | s = "cmp"; | |
14143 | s2 = "btnez"; | |
14144 | goto do_branch; | |
14145 | case M_BLT: | |
14146 | s = "slt"; | |
14147 | s2 = "btnez"; | |
14148 | goto do_branch; | |
14149 | case M_BLTU: | |
14150 | s = "sltu"; | |
14151 | s2 = "btnez"; | |
14152 | goto do_branch; | |
14153 | case M_BLE: | |
14154 | s = "slt"; | |
14155 | s2 = "bteqz"; | |
14156 | goto do_reverse_branch; | |
14157 | case M_BLEU: | |
14158 | s = "sltu"; | |
14159 | s2 = "bteqz"; | |
14160 | goto do_reverse_branch; | |
14161 | case M_BGE: | |
14162 | s = "slt"; | |
14163 | s2 = "bteqz"; | |
14164 | goto do_branch; | |
14165 | case M_BGEU: | |
14166 | s = "sltu"; | |
14167 | s2 = "bteqz"; | |
14168 | goto do_branch; | |
14169 | case M_BGT: | |
14170 | s = "slt"; | |
14171 | s2 = "btnez"; | |
14172 | goto do_reverse_branch; | |
14173 | case M_BGTU: | |
14174 | s = "sltu"; | |
14175 | s2 = "btnez"; | |
14176 | ||
14177 | do_reverse_branch: | |
c0ebe874 RS |
14178 | tmp = op[1]; |
14179 | op[1] = op[0]; | |
14180 | op[0] = tmp; | |
252b5132 RH |
14181 | |
14182 | do_branch: | |
c0ebe874 | 14183 | macro_build (NULL, s, "x,y", op[0], op[1]); |
67c0d1eb | 14184 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
14185 | break; |
14186 | ||
14187 | case M_BEQ_I: | |
14188 | s = "cmpi"; | |
14189 | s2 = "bteqz"; | |
14190 | s3 = "x,U"; | |
14191 | goto do_branch_i; | |
14192 | case M_BNE_I: | |
14193 | s = "cmpi"; | |
14194 | s2 = "btnez"; | |
14195 | s3 = "x,U"; | |
14196 | goto do_branch_i; | |
14197 | case M_BLT_I: | |
14198 | s = "slti"; | |
14199 | s2 = "btnez"; | |
14200 | s3 = "x,8"; | |
14201 | goto do_branch_i; | |
14202 | case M_BLTU_I: | |
14203 | s = "sltiu"; | |
14204 | s2 = "btnez"; | |
14205 | s3 = "x,8"; | |
14206 | goto do_branch_i; | |
14207 | case M_BLE_I: | |
14208 | s = "slti"; | |
14209 | s2 = "btnez"; | |
14210 | s3 = "x,8"; | |
14211 | goto do_addone_branch_i; | |
14212 | case M_BLEU_I: | |
14213 | s = "sltiu"; | |
14214 | s2 = "btnez"; | |
14215 | s3 = "x,8"; | |
14216 | goto do_addone_branch_i; | |
14217 | case M_BGE_I: | |
14218 | s = "slti"; | |
14219 | s2 = "bteqz"; | |
14220 | s3 = "x,8"; | |
14221 | goto do_branch_i; | |
14222 | case M_BGEU_I: | |
14223 | s = "sltiu"; | |
14224 | s2 = "bteqz"; | |
14225 | s3 = "x,8"; | |
14226 | goto do_branch_i; | |
14227 | case M_BGT_I: | |
14228 | s = "slti"; | |
14229 | s2 = "bteqz"; | |
14230 | s3 = "x,8"; | |
14231 | goto do_addone_branch_i; | |
14232 | case M_BGTU_I: | |
14233 | s = "sltiu"; | |
14234 | s2 = "bteqz"; | |
14235 | s3 = "x,8"; | |
14236 | ||
14237 | do_addone_branch_i: | |
252b5132 RH |
14238 | ++imm_expr.X_add_number; |
14239 | ||
14240 | do_branch_i: | |
c0ebe874 | 14241 | macro_build (&imm_expr, s, s3, op[0]); |
67c0d1eb | 14242 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
14243 | break; |
14244 | ||
14245 | case M_ABS: | |
14246 | expr1.X_add_number = 0; | |
c0ebe874 RS |
14247 | macro_build (&expr1, "slti", "x,8", op[1]); |
14248 | if (op[0] != op[1]) | |
14249 | macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]); | |
252b5132 | 14250 | expr1.X_add_number = 2; |
67c0d1eb | 14251 | macro_build (&expr1, "bteqz", "p"); |
c0ebe874 | 14252 | macro_build (NULL, "neg", "x,w", op[0], op[0]); |
0acfaea6 | 14253 | break; |
252b5132 RH |
14254 | } |
14255 | } | |
14256 | ||
14daeee3 RS |
14257 | /* Look up instruction [START, START + LENGTH) in HASH. Record any extra |
14258 | opcode bits in *OPCODE_EXTRA. */ | |
14259 | ||
14260 | static struct mips_opcode * | |
14261 | mips_lookup_insn (struct hash_control *hash, const char *start, | |
da8bca91 | 14262 | ssize_t length, unsigned int *opcode_extra) |
14daeee3 RS |
14263 | { |
14264 | char *name, *dot, *p; | |
14265 | unsigned int mask, suffix; | |
da8bca91 | 14266 | ssize_t opend; |
14daeee3 RS |
14267 | struct mips_opcode *insn; |
14268 | ||
14269 | /* Make a copy of the instruction so that we can fiddle with it. */ | |
4ec9d7d5 | 14270 | name = xstrndup (start, length); |
14daeee3 RS |
14271 | |
14272 | /* Look up the instruction as-is. */ | |
14273 | insn = (struct mips_opcode *) hash_find (hash, name); | |
ee5734f0 | 14274 | if (insn) |
e1fa0163 | 14275 | goto end; |
14daeee3 RS |
14276 | |
14277 | dot = strchr (name, '.'); | |
14278 | if (dot && dot[1]) | |
14279 | { | |
14280 | /* Try to interpret the text after the dot as a VU0 channel suffix. */ | |
14281 | p = mips_parse_vu0_channels (dot + 1, &mask); | |
14282 | if (*p == 0 && mask != 0) | |
14283 | { | |
14284 | *dot = 0; | |
14285 | insn = (struct mips_opcode *) hash_find (hash, name); | |
14286 | *dot = '.'; | |
14287 | if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0) | |
14288 | { | |
14289 | *opcode_extra |= mask << mips_vu0_channel_mask.lsb; | |
e1fa0163 | 14290 | goto end; |
14daeee3 RS |
14291 | } |
14292 | } | |
14293 | } | |
14294 | ||
14295 | if (mips_opts.micromips) | |
14296 | { | |
14297 | /* See if there's an instruction size override suffix, | |
14298 | either `16' or `32', at the end of the mnemonic proper, | |
14299 | that defines the operation, i.e. before the first `.' | |
14300 | character if any. Strip it and retry. */ | |
14301 | opend = dot != NULL ? dot - name : length; | |
14302 | if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6') | |
14303 | suffix = 2; | |
3076e594 | 14304 | else if (opend >= 2 && name[opend - 2] == '3' && name[opend - 1] == '2') |
14daeee3 RS |
14305 | suffix = 4; |
14306 | else | |
14307 | suffix = 0; | |
14308 | if (suffix) | |
14309 | { | |
39334a61 | 14310 | memmove (name + opend - 2, name + opend, length - opend + 1); |
14daeee3 | 14311 | insn = (struct mips_opcode *) hash_find (hash, name); |
ee5734f0 | 14312 | if (insn) |
14daeee3 RS |
14313 | { |
14314 | forced_insn_length = suffix; | |
e1fa0163 | 14315 | goto end; |
14daeee3 RS |
14316 | } |
14317 | } | |
14318 | } | |
14319 | ||
e1fa0163 NC |
14320 | insn = NULL; |
14321 | end: | |
14322 | free (name); | |
14323 | return insn; | |
14daeee3 RS |
14324 | } |
14325 | ||
77bd4346 | 14326 | /* Assemble an instruction into its binary format. If the instruction |
e423441d RS |
14327 | is a macro, set imm_expr and offset_expr to the values associated |
14328 | with "I" and "A" operands respectively. Otherwise store the value | |
14329 | of the relocatable field (if any) in offset_expr. In both cases | |
14330 | set offset_reloc to the relocation operators applied to offset_expr. */ | |
252b5132 RH |
14331 | |
14332 | static void | |
60f20e8b | 14333 | mips_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 14334 | { |
60f20e8b | 14335 | const struct mips_opcode *first, *past; |
df58fc94 | 14336 | struct hash_control *hash; |
a92713e6 | 14337 | char format; |
14daeee3 | 14338 | size_t end; |
a92713e6 | 14339 | struct mips_operand_token *tokens; |
14daeee3 | 14340 | unsigned int opcode_extra; |
252b5132 | 14341 | |
df58fc94 RS |
14342 | if (mips_opts.micromips) |
14343 | { | |
14344 | hash = micromips_op_hash; | |
14345 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
14346 | } | |
14347 | else | |
14348 | { | |
14349 | hash = op_hash; | |
14350 | past = &mips_opcodes[NUMOPCODES]; | |
14351 | } | |
14352 | forced_insn_length = 0; | |
14daeee3 | 14353 | opcode_extra = 0; |
252b5132 | 14354 | |
df58fc94 | 14355 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
14356 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
14357 | continue; | |
bdaaa2e1 | 14358 | |
60f20e8b RS |
14359 | first = mips_lookup_insn (hash, str, end, &opcode_extra); |
14360 | if (first == NULL) | |
252b5132 | 14361 | { |
1661c76c | 14362 | set_insn_error (0, _("unrecognized opcode")); |
a40bc9dd | 14363 | return; |
252b5132 RH |
14364 | } |
14365 | ||
60f20e8b | 14366 | if (strcmp (first->name, "li.s") == 0) |
a92713e6 | 14367 | format = 'f'; |
60f20e8b | 14368 | else if (strcmp (first->name, "li.d") == 0) |
a92713e6 RS |
14369 | format = 'd'; |
14370 | else | |
14371 | format = 0; | |
14372 | tokens = mips_parse_arguments (str + end, format); | |
14373 | if (!tokens) | |
14374 | return; | |
14375 | ||
60f20e8b RS |
14376 | if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE) |
14377 | && !match_insns (insn, first, past, tokens, opcode_extra, TRUE)) | |
1661c76c | 14378 | set_insn_error (0, _("invalid operands")); |
df58fc94 | 14379 | |
e3de51ce | 14380 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
14381 | } |
14382 | ||
77bd4346 RS |
14383 | /* As for mips_ip, but used when assembling MIPS16 code. |
14384 | Also set forced_insn_length to the resulting instruction size in | |
14385 | bytes if the user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
14386 | |
14387 | static void | |
60f20e8b | 14388 | mips16_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 14389 | { |
1a00e612 | 14390 | char *end, *s, c; |
60f20e8b | 14391 | struct mips_opcode *first; |
a92713e6 | 14392 | struct mips_operand_token *tokens; |
3fb49709 | 14393 | unsigned int l; |
252b5132 | 14394 | |
25499ac7 | 14395 | for (s = str; *s != '\0' && *s != '.' && *s != ' '; ++s) |
252b5132 | 14396 | ; |
1a00e612 RS |
14397 | end = s; |
14398 | c = *end; | |
3fb49709 MR |
14399 | |
14400 | l = 0; | |
1a00e612 | 14401 | switch (c) |
252b5132 RH |
14402 | { |
14403 | case '\0': | |
14404 | break; | |
14405 | ||
14406 | case ' ': | |
1a00e612 | 14407 | s++; |
252b5132 RH |
14408 | break; |
14409 | ||
14410 | case '.': | |
3fb49709 MR |
14411 | s++; |
14412 | if (*s == 't') | |
252b5132 | 14413 | { |
3fb49709 MR |
14414 | l = 2; |
14415 | s++; | |
252b5132 | 14416 | } |
3fb49709 | 14417 | else if (*s == 'e') |
252b5132 | 14418 | { |
3fb49709 MR |
14419 | l = 4; |
14420 | s++; | |
252b5132 | 14421 | } |
3fb49709 MR |
14422 | if (*s == '\0') |
14423 | break; | |
14424 | else if (*s++ == ' ') | |
14425 | break; | |
1661c76c | 14426 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
14427 | return; |
14428 | } | |
3fb49709 | 14429 | forced_insn_length = l; |
252b5132 | 14430 | |
1a00e612 | 14431 | *end = 0; |
60f20e8b | 14432 | first = (struct mips_opcode *) hash_find (mips16_op_hash, str); |
1a00e612 RS |
14433 | *end = c; |
14434 | ||
60f20e8b | 14435 | if (!first) |
252b5132 | 14436 | { |
1661c76c | 14437 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
14438 | return; |
14439 | } | |
14440 | ||
a92713e6 RS |
14441 | tokens = mips_parse_arguments (s, 0); |
14442 | if (!tokens) | |
14443 | return; | |
14444 | ||
60f20e8b | 14445 | if (!match_mips16_insns (insn, first, tokens)) |
1661c76c | 14446 | set_insn_error (0, _("invalid operands")); |
252b5132 | 14447 | |
e3de51ce | 14448 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
14449 | } |
14450 | ||
b886a2ab RS |
14451 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
14452 | NBITS is the number of significant bits in VAL. */ | |
14453 | ||
14454 | static unsigned long | |
14455 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
14456 | { | |
14457 | int extval; | |
25499ac7 MR |
14458 | |
14459 | extval = 0; | |
14460 | val &= (1U << nbits) - 1; | |
14461 | if (nbits == 16 || nbits == 9) | |
b886a2ab RS |
14462 | { |
14463 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
14464 | val &= 0x1f; | |
14465 | } | |
14466 | else if (nbits == 15) | |
14467 | { | |
14468 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
14469 | val &= 0xf; | |
14470 | } | |
25499ac7 | 14471 | else if (nbits == 6) |
b886a2ab RS |
14472 | { |
14473 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14474 | val = 0; | |
14475 | } | |
14476 | return (extval << 16) | val; | |
14477 | } | |
14478 | ||
3ccad066 RS |
14479 | /* Like decode_mips16_operand, but require the operand to be defined and |
14480 | require it to be an integer. */ | |
14481 | ||
14482 | static const struct mips_int_operand * | |
14483 | mips16_immed_operand (int type, bfd_boolean extended_p) | |
14484 | { | |
14485 | const struct mips_operand *operand; | |
14486 | ||
14487 | operand = decode_mips16_operand (type, extended_p); | |
14488 | if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL)) | |
14489 | abort (); | |
14490 | return (const struct mips_int_operand *) operand; | |
14491 | } | |
14492 | ||
14493 | /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */ | |
14494 | ||
14495 | static bfd_boolean | |
14496 | mips16_immed_in_range_p (const struct mips_int_operand *operand, | |
14497 | bfd_reloc_code_real_type reloc, offsetT sval) | |
14498 | { | |
14499 | int min_val, max_val; | |
14500 | ||
14501 | min_val = mips_int_operand_min (operand); | |
14502 | max_val = mips_int_operand_max (operand); | |
14503 | if (reloc != BFD_RELOC_UNUSED) | |
14504 | { | |
14505 | if (min_val < 0) | |
14506 | sval = SEXT_16BIT (sval); | |
14507 | else | |
14508 | sval &= 0xffff; | |
14509 | } | |
14510 | ||
14511 | return (sval >= min_val | |
14512 | && sval <= max_val | |
14513 | && (sval & ((1 << operand->shift) - 1)) == 0); | |
14514 | } | |
14515 | ||
5c04167a RS |
14516 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
14517 | extending it if necessary. The instruction in *INSN may | |
14518 | already be extended. | |
14519 | ||
43c0598f RS |
14520 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
14521 | if none. In the former case, VAL is a 16-bit number with no | |
14522 | defined signedness. | |
14523 | ||
14524 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14525 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14526 | |
14527 | static void | |
3b4dbbbf | 14528 | mips16_immed (const char *file, unsigned int line, int type, |
43c0598f | 14529 | bfd_reloc_code_real_type reloc, offsetT val, |
5c04167a | 14530 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14531 | { |
3ccad066 RS |
14532 | const struct mips_int_operand *operand; |
14533 | unsigned int uval, length; | |
252b5132 | 14534 | |
3ccad066 RS |
14535 | operand = mips16_immed_operand (type, FALSE); |
14536 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
5c04167a RS |
14537 | { |
14538 | /* We need an extended instruction. */ | |
14539 | if (user_insn_length == 2) | |
14540 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14541 | else | |
14542 | *insn |= MIPS16_EXTEND; | |
14543 | } | |
14544 | else if (user_insn_length == 4) | |
14545 | { | |
14546 | /* The operand doesn't force an unextended instruction to be extended. | |
14547 | Warn if the user wanted an extended instruction anyway. */ | |
14548 | *insn |= MIPS16_EXTEND; | |
14549 | as_warn_where (file, line, | |
14550 | _("extended operand requested but not required")); | |
14551 | } | |
252b5132 | 14552 | |
3ccad066 RS |
14553 | length = mips16_opcode_length (*insn); |
14554 | if (length == 4) | |
252b5132 | 14555 | { |
3ccad066 RS |
14556 | operand = mips16_immed_operand (type, TRUE); |
14557 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
14558 | as_bad_where (file, line, | |
14559 | _("operand value out of range for instruction")); | |
252b5132 | 14560 | } |
3ccad066 | 14561 | uval = ((unsigned int) val >> operand->shift) - operand->bias; |
bdd15286 | 14562 | if (length == 2 || operand->root.lsb != 0) |
3ccad066 | 14563 | *insn = mips_insert_operand (&operand->root, *insn, uval); |
252b5132 | 14564 | else |
3ccad066 | 14565 | *insn |= mips16_immed_extend (uval, operand->root.size); |
252b5132 RH |
14566 | } |
14567 | \f | |
d6f16593 | 14568 | struct percent_op_match |
ad8d3bb3 | 14569 | { |
5e0116d5 RS |
14570 | const char *str; |
14571 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14572 | }; |
14573 | ||
14574 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14575 | { |
5e0116d5 | 14576 | {"%lo", BFD_RELOC_LO16}, |
5e0116d5 RS |
14577 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14578 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14579 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14580 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14581 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14582 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14583 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14584 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14585 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14586 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
be3f1006 | 14587 | {"%gprel", BFD_RELOC_GPREL16}, |
5e0116d5 RS |
14588 | {"%half", BFD_RELOC_16}, |
14589 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14590 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14591 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14592 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14593 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14594 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14595 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14596 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14597 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14598 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
7361da2c AB |
14599 | {"%hi", BFD_RELOC_HI16_S}, |
14600 | {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL}, | |
14601 | {"%pcrel_lo", BFD_RELOC_LO16_PCREL} | |
ad8d3bb3 TS |
14602 | }; |
14603 | ||
d6f16593 MR |
14604 | static const struct percent_op_match mips16_percent_op[] = |
14605 | { | |
14606 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
be3f1006 | 14607 | {"%gp_rel", BFD_RELOC_MIPS16_GPREL}, |
d6f16593 | 14608 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, |
738e5348 RS |
14609 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14610 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14611 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14612 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14613 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14614 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14615 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14616 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14617 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14618 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14619 | }; |
14620 | ||
252b5132 | 14621 | |
5e0116d5 RS |
14622 | /* Return true if *STR points to a relocation operator. When returning true, |
14623 | move *STR over the operator and store its relocation code in *RELOC. | |
14624 | Leave both *STR and *RELOC alone when returning false. */ | |
14625 | ||
14626 | static bfd_boolean | |
17a2f251 | 14627 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14628 | { |
d6f16593 MR |
14629 | const struct percent_op_match *percent_op; |
14630 | size_t limit, i; | |
14631 | ||
14632 | if (mips_opts.mips16) | |
14633 | { | |
14634 | percent_op = mips16_percent_op; | |
14635 | limit = ARRAY_SIZE (mips16_percent_op); | |
14636 | } | |
14637 | else | |
14638 | { | |
14639 | percent_op = mips_percent_op; | |
14640 | limit = ARRAY_SIZE (mips_percent_op); | |
14641 | } | |
76b3015f | 14642 | |
d6f16593 | 14643 | for (i = 0; i < limit; i++) |
5e0116d5 | 14644 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14645 | { |
3f98094e DJ |
14646 | int len = strlen (percent_op[i].str); |
14647 | ||
14648 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14649 | continue; | |
14650 | ||
5e0116d5 RS |
14651 | *str += strlen (percent_op[i].str); |
14652 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14653 | |
5e0116d5 RS |
14654 | /* Check whether the output BFD supports this relocation. |
14655 | If not, issue an error and fall back on something safe. */ | |
14656 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14657 | { |
20203fb9 | 14658 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14659 | percent_op[i].str); |
01a3f561 | 14660 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14661 | } |
5e0116d5 | 14662 | return TRUE; |
394f9b3a | 14663 | } |
5e0116d5 | 14664 | return FALSE; |
394f9b3a | 14665 | } |
ad8d3bb3 | 14666 | |
ad8d3bb3 | 14667 | |
5e0116d5 RS |
14668 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14669 | expression in *EP and the relocations in the array starting | |
14670 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14671 | |
01a3f561 | 14672 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14673 | |
5e0116d5 | 14674 | static size_t |
17a2f251 TS |
14675 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14676 | char *str) | |
ad8d3bb3 | 14677 | { |
5e0116d5 RS |
14678 | bfd_reloc_code_real_type reversed_reloc[3]; |
14679 | size_t reloc_index, i; | |
09b8f35a RS |
14680 | int crux_depth, str_depth; |
14681 | char *crux; | |
5e0116d5 RS |
14682 | |
14683 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14684 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14685 | of the main expression and with CRUX_DEPTH containing the number | |
14686 | of open brackets at that point. */ | |
14687 | reloc_index = -1; | |
14688 | str_depth = 0; | |
14689 | do | |
fb1b3232 | 14690 | { |
09b8f35a RS |
14691 | reloc_index++; |
14692 | crux = str; | |
14693 | crux_depth = str_depth; | |
14694 | ||
14695 | /* Skip over whitespace and brackets, keeping count of the number | |
14696 | of brackets. */ | |
14697 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14698 | if (*str++ == '(') | |
14699 | str_depth++; | |
5e0116d5 | 14700 | } |
09b8f35a RS |
14701 | while (*str == '%' |
14702 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14703 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14704 | |
09b8f35a | 14705 | my_getExpression (ep, crux); |
5e0116d5 | 14706 | str = expr_end; |
394f9b3a | 14707 | |
5e0116d5 | 14708 | /* Match every open bracket. */ |
09b8f35a | 14709 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14710 | if (*str++ == ')') |
09b8f35a | 14711 | crux_depth--; |
394f9b3a | 14712 | |
09b8f35a | 14713 | if (crux_depth > 0) |
20203fb9 | 14714 | as_bad (_("unclosed '('")); |
394f9b3a | 14715 | |
5e0116d5 | 14716 | expr_end = str; |
252b5132 | 14717 | |
ec4fcab0 MR |
14718 | for (i = 0; i < reloc_index; i++) |
14719 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
fb1b3232 | 14720 | |
5e0116d5 | 14721 | return reloc_index; |
252b5132 RH |
14722 | } |
14723 | ||
14724 | static void | |
17a2f251 | 14725 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14726 | { |
14727 | char *save_in; | |
14728 | ||
14729 | save_in = input_line_pointer; | |
14730 | input_line_pointer = str; | |
14731 | expression (ep); | |
14732 | expr_end = input_line_pointer; | |
14733 | input_line_pointer = save_in; | |
252b5132 RH |
14734 | } |
14735 | ||
6d4af3c2 | 14736 | const char * |
17a2f251 | 14737 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14738 | { |
499ac353 | 14739 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14740 | } |
14741 | ||
14742 | void | |
17a2f251 | 14743 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14744 | { |
14745 | if (target_big_endian) | |
14746 | number_to_chars_bigendian (buf, val, n); | |
14747 | else | |
14748 | number_to_chars_littleendian (buf, val, n); | |
14749 | } | |
14750 | \f | |
e013f690 TS |
14751 | static int support_64bit_objects(void) |
14752 | { | |
14753 | const char **list, **l; | |
aa3d8fdf | 14754 | int yes; |
e013f690 TS |
14755 | |
14756 | list = bfd_target_list (); | |
14757 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14758 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14759 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14760 | break; |
aa3d8fdf | 14761 | yes = (*l != NULL); |
e013f690 | 14762 | free (list); |
aa3d8fdf | 14763 | return yes; |
e013f690 TS |
14764 | } |
14765 | ||
316f5878 RS |
14766 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14767 | NEW_VALUE. Warn if another value was already specified. Note: | |
14768 | we have to defer parsing the -march and -mtune arguments in order | |
14769 | to handle 'from-abi' correctly, since the ABI might be specified | |
14770 | in a later argument. */ | |
14771 | ||
14772 | static void | |
17a2f251 | 14773 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14774 | { |
14775 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
1661c76c | 14776 | as_warn (_("a different %s was already specified, is now %s"), |
316f5878 RS |
14777 | string_ptr == &mips_arch_string ? "-march" : "-mtune", |
14778 | new_value); | |
14779 | ||
14780 | *string_ptr = new_value; | |
14781 | } | |
14782 | ||
252b5132 | 14783 | int |
17b9d67d | 14784 | md_parse_option (int c, const char *arg) |
252b5132 | 14785 | { |
c6278170 RS |
14786 | unsigned int i; |
14787 | ||
14788 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
14789 | if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) | |
14790 | { | |
919731af | 14791 | file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts, |
c6278170 RS |
14792 | c == mips_ases[i].option_on); |
14793 | return 1; | |
14794 | } | |
14795 | ||
252b5132 RH |
14796 | switch (c) |
14797 | { | |
119d663a NC |
14798 | case OPTION_CONSTRUCT_FLOATS: |
14799 | mips_disable_float_construction = 0; | |
14800 | break; | |
bdaaa2e1 | 14801 | |
119d663a NC |
14802 | case OPTION_NO_CONSTRUCT_FLOATS: |
14803 | mips_disable_float_construction = 1; | |
14804 | break; | |
bdaaa2e1 | 14805 | |
252b5132 RH |
14806 | case OPTION_TRAP: |
14807 | mips_trap = 1; | |
14808 | break; | |
14809 | ||
14810 | case OPTION_BREAK: | |
14811 | mips_trap = 0; | |
14812 | break; | |
14813 | ||
14814 | case OPTION_EB: | |
14815 | target_big_endian = 1; | |
14816 | break; | |
14817 | ||
14818 | case OPTION_EL: | |
14819 | target_big_endian = 0; | |
14820 | break; | |
14821 | ||
14822 | case 'O': | |
4ffff32f TS |
14823 | if (arg == NULL) |
14824 | mips_optimize = 1; | |
14825 | else if (arg[0] == '0') | |
14826 | mips_optimize = 0; | |
14827 | else if (arg[0] == '1') | |
252b5132 RH |
14828 | mips_optimize = 1; |
14829 | else | |
14830 | mips_optimize = 2; | |
14831 | break; | |
14832 | ||
14833 | case 'g': | |
14834 | if (arg == NULL) | |
14835 | mips_debug = 2; | |
14836 | else | |
14837 | mips_debug = atoi (arg); | |
252b5132 RH |
14838 | break; |
14839 | ||
14840 | case OPTION_MIPS1: | |
0b35dfee | 14841 | file_mips_opts.isa = ISA_MIPS1; |
252b5132 RH |
14842 | break; |
14843 | ||
14844 | case OPTION_MIPS2: | |
0b35dfee | 14845 | file_mips_opts.isa = ISA_MIPS2; |
252b5132 RH |
14846 | break; |
14847 | ||
14848 | case OPTION_MIPS3: | |
0b35dfee | 14849 | file_mips_opts.isa = ISA_MIPS3; |
252b5132 RH |
14850 | break; |
14851 | ||
14852 | case OPTION_MIPS4: | |
0b35dfee | 14853 | file_mips_opts.isa = ISA_MIPS4; |
e7af610e NC |
14854 | break; |
14855 | ||
84ea6cf2 | 14856 | case OPTION_MIPS5: |
0b35dfee | 14857 | file_mips_opts.isa = ISA_MIPS5; |
84ea6cf2 NC |
14858 | break; |
14859 | ||
e7af610e | 14860 | case OPTION_MIPS32: |
0b35dfee | 14861 | file_mips_opts.isa = ISA_MIPS32; |
252b5132 RH |
14862 | break; |
14863 | ||
af7ee8bf | 14864 | case OPTION_MIPS32R2: |
0b35dfee | 14865 | file_mips_opts.isa = ISA_MIPS32R2; |
af7ee8bf CD |
14866 | break; |
14867 | ||
ae52f483 | 14868 | case OPTION_MIPS32R3: |
0ae19f05 | 14869 | file_mips_opts.isa = ISA_MIPS32R3; |
ae52f483 AB |
14870 | break; |
14871 | ||
14872 | case OPTION_MIPS32R5: | |
0ae19f05 | 14873 | file_mips_opts.isa = ISA_MIPS32R5; |
ae52f483 AB |
14874 | break; |
14875 | ||
7361da2c AB |
14876 | case OPTION_MIPS32R6: |
14877 | file_mips_opts.isa = ISA_MIPS32R6; | |
14878 | break; | |
14879 | ||
5f74bc13 | 14880 | case OPTION_MIPS64R2: |
0b35dfee | 14881 | file_mips_opts.isa = ISA_MIPS64R2; |
5f74bc13 CD |
14882 | break; |
14883 | ||
ae52f483 | 14884 | case OPTION_MIPS64R3: |
0ae19f05 | 14885 | file_mips_opts.isa = ISA_MIPS64R3; |
ae52f483 AB |
14886 | break; |
14887 | ||
14888 | case OPTION_MIPS64R5: | |
0ae19f05 | 14889 | file_mips_opts.isa = ISA_MIPS64R5; |
ae52f483 AB |
14890 | break; |
14891 | ||
7361da2c AB |
14892 | case OPTION_MIPS64R6: |
14893 | file_mips_opts.isa = ISA_MIPS64R6; | |
14894 | break; | |
14895 | ||
84ea6cf2 | 14896 | case OPTION_MIPS64: |
0b35dfee | 14897 | file_mips_opts.isa = ISA_MIPS64; |
84ea6cf2 NC |
14898 | break; |
14899 | ||
ec68c924 | 14900 | case OPTION_MTUNE: |
316f5878 RS |
14901 | mips_set_option_string (&mips_tune_string, arg); |
14902 | break; | |
ec68c924 | 14903 | |
316f5878 RS |
14904 | case OPTION_MARCH: |
14905 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14906 | break; |
14907 | ||
14908 | case OPTION_M4650: | |
316f5878 RS |
14909 | mips_set_option_string (&mips_arch_string, "4650"); |
14910 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14911 | break; |
14912 | ||
14913 | case OPTION_NO_M4650: | |
14914 | break; | |
14915 | ||
14916 | case OPTION_M4010: | |
316f5878 RS |
14917 | mips_set_option_string (&mips_arch_string, "4010"); |
14918 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14919 | break; |
14920 | ||
14921 | case OPTION_NO_M4010: | |
14922 | break; | |
14923 | ||
14924 | case OPTION_M4100: | |
316f5878 RS |
14925 | mips_set_option_string (&mips_arch_string, "4100"); |
14926 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14927 | break; |
14928 | ||
14929 | case OPTION_NO_M4100: | |
14930 | break; | |
14931 | ||
252b5132 | 14932 | case OPTION_M3900: |
316f5878 RS |
14933 | mips_set_option_string (&mips_arch_string, "3900"); |
14934 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14935 | break; |
bdaaa2e1 | 14936 | |
252b5132 RH |
14937 | case OPTION_NO_M3900: |
14938 | break; | |
14939 | ||
df58fc94 | 14940 | case OPTION_MICROMIPS: |
919731af | 14941 | if (file_mips_opts.mips16 == 1) |
df58fc94 RS |
14942 | { |
14943 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14944 | return 0; | |
14945 | } | |
919731af | 14946 | file_mips_opts.micromips = 1; |
df58fc94 RS |
14947 | mips_no_prev_insn (); |
14948 | break; | |
14949 | ||
14950 | case OPTION_NO_MICROMIPS: | |
919731af | 14951 | file_mips_opts.micromips = 0; |
df58fc94 RS |
14952 | mips_no_prev_insn (); |
14953 | break; | |
14954 | ||
252b5132 | 14955 | case OPTION_MIPS16: |
919731af | 14956 | if (file_mips_opts.micromips == 1) |
df58fc94 RS |
14957 | { |
14958 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14959 | return 0; | |
14960 | } | |
919731af | 14961 | file_mips_opts.mips16 = 1; |
7d10b47d | 14962 | mips_no_prev_insn (); |
252b5132 RH |
14963 | break; |
14964 | ||
14965 | case OPTION_NO_MIPS16: | |
919731af | 14966 | file_mips_opts.mips16 = 0; |
7d10b47d | 14967 | mips_no_prev_insn (); |
252b5132 RH |
14968 | break; |
14969 | ||
6a32d874 CM |
14970 | case OPTION_FIX_24K: |
14971 | mips_fix_24k = 1; | |
14972 | break; | |
14973 | ||
14974 | case OPTION_NO_FIX_24K: | |
14975 | mips_fix_24k = 0; | |
14976 | break; | |
14977 | ||
a8d14a88 CM |
14978 | case OPTION_FIX_RM7000: |
14979 | mips_fix_rm7000 = 1; | |
14980 | break; | |
14981 | ||
14982 | case OPTION_NO_FIX_RM7000: | |
14983 | mips_fix_rm7000 = 0; | |
14984 | break; | |
14985 | ||
6f2117ba PH |
14986 | case OPTION_FIX_LOONGSON3_LLSC: |
14987 | mips_fix_loongson3_llsc = TRUE; | |
14988 | break; | |
14989 | ||
14990 | case OPTION_NO_FIX_LOONGSON3_LLSC: | |
14991 | mips_fix_loongson3_llsc = FALSE; | |
14992 | break; | |
14993 | ||
c67a084a NC |
14994 | case OPTION_FIX_LOONGSON2F_JUMP: |
14995 | mips_fix_loongson2f_jump = TRUE; | |
14996 | break; | |
14997 | ||
14998 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14999 | mips_fix_loongson2f_jump = FALSE; | |
15000 | break; | |
15001 | ||
15002 | case OPTION_FIX_LOONGSON2F_NOP: | |
15003 | mips_fix_loongson2f_nop = TRUE; | |
15004 | break; | |
15005 | ||
15006 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
15007 | mips_fix_loongson2f_nop = FALSE; | |
15008 | break; | |
15009 | ||
d766e8ec RS |
15010 | case OPTION_FIX_VR4120: |
15011 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
15012 | break; |
15013 | ||
d766e8ec RS |
15014 | case OPTION_NO_FIX_VR4120: |
15015 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
15016 | break; |
15017 | ||
7d8e00cf RS |
15018 | case OPTION_FIX_VR4130: |
15019 | mips_fix_vr4130 = 1; | |
15020 | break; | |
15021 | ||
15022 | case OPTION_NO_FIX_VR4130: | |
15023 | mips_fix_vr4130 = 0; | |
15024 | break; | |
15025 | ||
d954098f DD |
15026 | case OPTION_FIX_CN63XXP1: |
15027 | mips_fix_cn63xxp1 = TRUE; | |
15028 | break; | |
15029 | ||
15030 | case OPTION_NO_FIX_CN63XXP1: | |
15031 | mips_fix_cn63xxp1 = FALSE; | |
15032 | break; | |
15033 | ||
27c634e0 FN |
15034 | case OPTION_FIX_R5900: |
15035 | mips_fix_r5900 = TRUE; | |
15036 | mips_fix_r5900_explicit = TRUE; | |
15037 | break; | |
15038 | ||
15039 | case OPTION_NO_FIX_R5900: | |
15040 | mips_fix_r5900 = FALSE; | |
15041 | mips_fix_r5900_explicit = TRUE; | |
15042 | break; | |
15043 | ||
4a6a3df4 AO |
15044 | case OPTION_RELAX_BRANCH: |
15045 | mips_relax_branch = 1; | |
15046 | break; | |
15047 | ||
15048 | case OPTION_NO_RELAX_BRANCH: | |
15049 | mips_relax_branch = 0; | |
15050 | break; | |
15051 | ||
8b10b0b3 MR |
15052 | case OPTION_IGNORE_BRANCH_ISA: |
15053 | mips_ignore_branch_isa = TRUE; | |
15054 | break; | |
15055 | ||
15056 | case OPTION_NO_IGNORE_BRANCH_ISA: | |
15057 | mips_ignore_branch_isa = FALSE; | |
15058 | break; | |
15059 | ||
833794fc | 15060 | case OPTION_INSN32: |
919731af | 15061 | file_mips_opts.insn32 = TRUE; |
833794fc MR |
15062 | break; |
15063 | ||
15064 | case OPTION_NO_INSN32: | |
919731af | 15065 | file_mips_opts.insn32 = FALSE; |
833794fc MR |
15066 | break; |
15067 | ||
aa6975fb ILT |
15068 | case OPTION_MSHARED: |
15069 | mips_in_shared = TRUE; | |
15070 | break; | |
15071 | ||
15072 | case OPTION_MNO_SHARED: | |
15073 | mips_in_shared = FALSE; | |
15074 | break; | |
15075 | ||
aed1a261 | 15076 | case OPTION_MSYM32: |
919731af | 15077 | file_mips_opts.sym32 = TRUE; |
aed1a261 RS |
15078 | break; |
15079 | ||
15080 | case OPTION_MNO_SYM32: | |
919731af | 15081 | file_mips_opts.sym32 = FALSE; |
aed1a261 RS |
15082 | break; |
15083 | ||
252b5132 RH |
15084 | /* When generating ELF code, we permit -KPIC and -call_shared to |
15085 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
15086 | intended to be compatible with Irix 5. */ | |
15087 | case OPTION_CALL_SHARED: | |
252b5132 | 15088 | mips_pic = SVR4_PIC; |
143d77c5 | 15089 | mips_abicalls = TRUE; |
252b5132 RH |
15090 | break; |
15091 | ||
861fb55a | 15092 | case OPTION_CALL_NONPIC: |
861fb55a DJ |
15093 | mips_pic = NO_PIC; |
15094 | mips_abicalls = TRUE; | |
15095 | break; | |
15096 | ||
252b5132 | 15097 | case OPTION_NON_SHARED: |
252b5132 | 15098 | mips_pic = NO_PIC; |
143d77c5 | 15099 | mips_abicalls = FALSE; |
252b5132 RH |
15100 | break; |
15101 | ||
44075ae2 TS |
15102 | /* The -xgot option tells the assembler to use 32 bit offsets |
15103 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
15104 | compatibility. */ |
15105 | case OPTION_XGOT: | |
15106 | mips_big_got = 1; | |
15107 | break; | |
15108 | ||
15109 | case 'G': | |
6caf9ef4 TS |
15110 | g_switch_value = atoi (arg); |
15111 | g_switch_seen = 1; | |
252b5132 RH |
15112 | break; |
15113 | ||
34ba82a8 TS |
15114 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
15115 | and -mabi=64. */ | |
252b5132 | 15116 | case OPTION_32: |
f3ded42a | 15117 | mips_abi = O32_ABI; |
252b5132 RH |
15118 | break; |
15119 | ||
e013f690 | 15120 | case OPTION_N32: |
316f5878 | 15121 | mips_abi = N32_ABI; |
e013f690 | 15122 | break; |
252b5132 | 15123 | |
e013f690 | 15124 | case OPTION_64: |
316f5878 | 15125 | mips_abi = N64_ABI; |
f43abd2b | 15126 | if (!support_64bit_objects()) |
1661c76c | 15127 | as_fatal (_("no compiled in support for 64 bit object file format")); |
252b5132 RH |
15128 | break; |
15129 | ||
c97ef257 | 15130 | case OPTION_GP32: |
bad1aba3 | 15131 | file_mips_opts.gp = 32; |
c97ef257 AH |
15132 | break; |
15133 | ||
15134 | case OPTION_GP64: | |
bad1aba3 | 15135 | file_mips_opts.gp = 64; |
c97ef257 | 15136 | break; |
252b5132 | 15137 | |
ca4e0257 | 15138 | case OPTION_FP32: |
0b35dfee | 15139 | file_mips_opts.fp = 32; |
316f5878 RS |
15140 | break; |
15141 | ||
351cdf24 MF |
15142 | case OPTION_FPXX: |
15143 | file_mips_opts.fp = 0; | |
15144 | break; | |
15145 | ||
316f5878 | 15146 | case OPTION_FP64: |
0b35dfee | 15147 | file_mips_opts.fp = 64; |
ca4e0257 RS |
15148 | break; |
15149 | ||
351cdf24 MF |
15150 | case OPTION_ODD_SPREG: |
15151 | file_mips_opts.oddspreg = 1; | |
15152 | break; | |
15153 | ||
15154 | case OPTION_NO_ODD_SPREG: | |
15155 | file_mips_opts.oddspreg = 0; | |
15156 | break; | |
15157 | ||
037b32b9 | 15158 | case OPTION_SINGLE_FLOAT: |
0b35dfee | 15159 | file_mips_opts.single_float = 1; |
037b32b9 AN |
15160 | break; |
15161 | ||
15162 | case OPTION_DOUBLE_FLOAT: | |
0b35dfee | 15163 | file_mips_opts.single_float = 0; |
037b32b9 AN |
15164 | break; |
15165 | ||
15166 | case OPTION_SOFT_FLOAT: | |
0b35dfee | 15167 | file_mips_opts.soft_float = 1; |
037b32b9 AN |
15168 | break; |
15169 | ||
15170 | case OPTION_HARD_FLOAT: | |
0b35dfee | 15171 | file_mips_opts.soft_float = 0; |
037b32b9 AN |
15172 | break; |
15173 | ||
252b5132 | 15174 | case OPTION_MABI: |
e013f690 | 15175 | if (strcmp (arg, "32") == 0) |
316f5878 | 15176 | mips_abi = O32_ABI; |
e013f690 | 15177 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 15178 | mips_abi = O64_ABI; |
e013f690 | 15179 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 15180 | mips_abi = N32_ABI; |
e013f690 TS |
15181 | else if (strcmp (arg, "64") == 0) |
15182 | { | |
316f5878 | 15183 | mips_abi = N64_ABI; |
e013f690 | 15184 | if (! support_64bit_objects()) |
1661c76c | 15185 | as_fatal (_("no compiled in support for 64 bit object file " |
e013f690 TS |
15186 | "format")); |
15187 | } | |
15188 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 15189 | mips_abi = EABI_ABI; |
e013f690 | 15190 | else |
da0e507f TS |
15191 | { |
15192 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
15193 | return 0; | |
15194 | } | |
252b5132 RH |
15195 | break; |
15196 | ||
6b76fefe | 15197 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 15198 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
15199 | break; |
15200 | ||
9ee72ff1 | 15201 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 15202 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
15203 | break; |
15204 | ||
ecb4347a | 15205 | case OPTION_MDEBUG: |
b34976b6 | 15206 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
15207 | break; |
15208 | ||
15209 | case OPTION_NO_MDEBUG: | |
b34976b6 | 15210 | mips_flag_mdebug = FALSE; |
ecb4347a | 15211 | break; |
dcd410fe RO |
15212 | |
15213 | case OPTION_PDR: | |
15214 | mips_flag_pdr = TRUE; | |
15215 | break; | |
15216 | ||
15217 | case OPTION_NO_PDR: | |
15218 | mips_flag_pdr = FALSE; | |
15219 | break; | |
0a44bf69 RS |
15220 | |
15221 | case OPTION_MVXWORKS_PIC: | |
15222 | mips_pic = VXWORKS_PIC; | |
15223 | break; | |
ecb4347a | 15224 | |
ba92f887 MR |
15225 | case OPTION_NAN: |
15226 | if (strcmp (arg, "2008") == 0) | |
7361da2c | 15227 | mips_nan2008 = 1; |
ba92f887 | 15228 | else if (strcmp (arg, "legacy") == 0) |
7361da2c | 15229 | mips_nan2008 = 0; |
ba92f887 MR |
15230 | else |
15231 | { | |
1661c76c | 15232 | as_fatal (_("invalid NaN setting -mnan=%s"), arg); |
ba92f887 MR |
15233 | return 0; |
15234 | } | |
15235 | break; | |
15236 | ||
252b5132 RH |
15237 | default: |
15238 | return 0; | |
15239 | } | |
15240 | ||
c67a084a NC |
15241 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
15242 | ||
252b5132 RH |
15243 | return 1; |
15244 | } | |
316f5878 | 15245 | \f |
919731af | 15246 | /* Set up globals to tune for the ISA or processor described by INFO. */ |
252b5132 | 15247 | |
316f5878 | 15248 | static void |
17a2f251 | 15249 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
15250 | { |
15251 | if (info != 0) | |
fef14a42 | 15252 | mips_tune = info->cpu; |
316f5878 | 15253 | } |
80cc45a5 | 15254 | |
34ba82a8 | 15255 | |
252b5132 | 15256 | void |
17a2f251 | 15257 | mips_after_parse_args (void) |
e9670677 | 15258 | { |
fef14a42 TS |
15259 | const struct mips_cpu_info *arch_info = 0; |
15260 | const struct mips_cpu_info *tune_info = 0; | |
15261 | ||
6f2117ba | 15262 | /* GP relative stuff not working for PE. */ |
6caf9ef4 | 15263 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 15264 | { |
6caf9ef4 | 15265 | if (g_switch_seen && g_switch_value != 0) |
1661c76c | 15266 | as_bad (_("-G not supported in this configuration")); |
e9670677 MR |
15267 | g_switch_value = 0; |
15268 | } | |
15269 | ||
cac012d6 AO |
15270 | if (mips_abi == NO_ABI) |
15271 | mips_abi = MIPS_DEFAULT_ABI; | |
15272 | ||
919731af | 15273 | /* The following code determines the architecture. |
22923709 RS |
15274 | Similar code was added to GCC 3.3 (see override_options() in |
15275 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
15276 | as much as possible. */ | |
e9670677 | 15277 | |
316f5878 | 15278 | if (mips_arch_string != 0) |
fef14a42 | 15279 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 15280 | |
0b35dfee | 15281 | if (file_mips_opts.isa != ISA_UNKNOWN) |
e9670677 | 15282 | { |
0b35dfee | 15283 | /* Handle -mipsN. At this point, file_mips_opts.isa contains the |
fef14a42 | 15284 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 15285 | the -march selection (if any). */ |
fef14a42 | 15286 | if (arch_info != 0) |
e9670677 | 15287 | { |
316f5878 RS |
15288 | /* -march takes precedence over -mipsN, since it is more descriptive. |
15289 | There's no harm in specifying both as long as the ISA levels | |
15290 | are the same. */ | |
0b35dfee | 15291 | if (file_mips_opts.isa != arch_info->isa) |
1661c76c RS |
15292 | as_bad (_("-%s conflicts with the other architecture options," |
15293 | " which imply -%s"), | |
0b35dfee | 15294 | mips_cpu_info_from_isa (file_mips_opts.isa)->name, |
fef14a42 | 15295 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 15296 | } |
316f5878 | 15297 | else |
0b35dfee | 15298 | arch_info = mips_cpu_info_from_isa (file_mips_opts.isa); |
e9670677 MR |
15299 | } |
15300 | ||
fef14a42 | 15301 | if (arch_info == 0) |
95bfe26e MF |
15302 | { |
15303 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
15304 | gas_assert (arch_info); | |
15305 | } | |
e9670677 | 15306 | |
fef14a42 | 15307 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 15308 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
15309 | arch_info->name); |
15310 | ||
919731af | 15311 | file_mips_opts.arch = arch_info->cpu; |
15312 | file_mips_opts.isa = arch_info->isa; | |
3315614d | 15313 | file_mips_opts.init_ase = arch_info->ase; |
919731af | 15314 | |
41cee089 FS |
15315 | /* The EVA Extension has instructions which are only valid when the R6 ISA |
15316 | is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are | |
15317 | present. */ | |
15318 | if (((file_mips_opts.ase & ASE_EVA) != 0) && ISA_IS_R6 (file_mips_opts.isa)) | |
15319 | file_mips_opts.ase |= ASE_EVA_R6; | |
15320 | ||
919731af | 15321 | /* Set up initial mips_opts state. */ |
15322 | mips_opts = file_mips_opts; | |
15323 | ||
27c634e0 FN |
15324 | /* For the R5900 default to `-mfix-r5900' unless the user told otherwise. */ |
15325 | if (!mips_fix_r5900_explicit) | |
15326 | mips_fix_r5900 = file_mips_opts.arch == CPU_R5900; | |
15327 | ||
919731af | 15328 | /* The register size inference code is now placed in |
15329 | file_mips_check_options. */ | |
fef14a42 | 15330 | |
0b35dfee | 15331 | /* Optimize for file_mips_opts.arch, unless -mtune selects a different |
15332 | processor. */ | |
fef14a42 TS |
15333 | if (mips_tune_string != 0) |
15334 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 15335 | |
fef14a42 TS |
15336 | if (tune_info == 0) |
15337 | mips_set_tune (arch_info); | |
15338 | else | |
15339 | mips_set_tune (tune_info); | |
e9670677 | 15340 | |
ecb4347a | 15341 | if (mips_flag_mdebug < 0) |
e8044f35 | 15342 | mips_flag_mdebug = 0; |
e9670677 MR |
15343 | } |
15344 | \f | |
15345 | void | |
17a2f251 | 15346 | mips_init_after_args (void) |
252b5132 | 15347 | { |
6f2117ba | 15348 | /* Initialize opcodes. */ |
252b5132 | 15349 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; |
beae10d5 | 15350 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15351 | } |
15352 | ||
15353 | long | |
17a2f251 | 15354 | md_pcrel_from (fixS *fixP) |
252b5132 | 15355 | { |
a7ebbfdf | 15356 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
6f2117ba | 15357 | |
a7ebbfdf TS |
15358 | switch (fixP->fx_r_type) |
15359 | { | |
df58fc94 RS |
15360 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15361 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15362 | /* Return the address of the delay slot. */ | |
15363 | return addr + 2; | |
15364 | ||
15365 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15366 | case BFD_RELOC_MICROMIPS_JMP: | |
c9775dde | 15367 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
a7ebbfdf | 15368 | case BFD_RELOC_16_PCREL_S2: |
7361da2c AB |
15369 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15370 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
a7ebbfdf TS |
15371 | case BFD_RELOC_MIPS_JMP: |
15372 | /* Return the address of the delay slot. */ | |
15373 | return addr + 4; | |
df58fc94 | 15374 | |
51f6035b MR |
15375 | case BFD_RELOC_MIPS_18_PCREL_S3: |
15376 | /* Return the aligned address of the doubleword containing | |
15377 | the instruction. */ | |
15378 | return addr & ~7; | |
15379 | ||
a7ebbfdf TS |
15380 | default: |
15381 | return addr; | |
15382 | } | |
252b5132 RH |
15383 | } |
15384 | ||
252b5132 RH |
15385 | /* This is called before the symbol table is processed. In order to |
15386 | work with gcc when using mips-tfile, we must keep all local labels. | |
15387 | However, in other cases, we want to discard them. If we were | |
15388 | called with -g, but we didn't see any debugging information, it may | |
15389 | mean that gcc is smuggling debugging information through to | |
15390 | mips-tfile, in which case we must generate all local labels. */ | |
15391 | ||
15392 | void | |
17a2f251 | 15393 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15394 | { |
15395 | #ifndef NO_ECOFF_DEBUGGING | |
15396 | if (ECOFF_DEBUGGING | |
15397 | && mips_debug != 0 | |
15398 | && ! ecoff_debugging_seen) | |
15399 | flag_keep_locals = 1; | |
15400 | #endif | |
15401 | } | |
15402 | ||
3b91255e | 15403 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15404 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15405 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15406 | relocation operators. | |
15407 | ||
15408 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15409 | expression if: | |
15410 | ||
15411 | (a) it refers to the same symbol; and | |
15412 | (b) the offset applied in the %lo() expression is no lower than | |
15413 | the offset applied in the %got() or %hi(). | |
15414 | ||
15415 | (b) allows us to cope with code like: | |
15416 | ||
15417 | lui $4,%hi(foo) | |
15418 | lh $4,%lo(foo+2)($4) | |
15419 | ||
15420 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15421 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15422 | the high 16 bits. | |
15423 | ||
15424 | When several %lo()s match a particular %got() or %hi(), we use the | |
15425 | following rules to distinguish them: | |
15426 | ||
15427 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15428 | higher offsets. | |
15429 | ||
15430 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15431 | that already have a matching %got() or %hi(). | |
15432 | ||
15433 | (3) later %lo()s are better than earlier %lo()s. | |
15434 | ||
15435 | These rules are applied in order. | |
15436 | ||
15437 | (1) means, among other things, that %lo()s with identical offsets are | |
15438 | chosen if they exist. | |
15439 | ||
15440 | (2) means that we won't associate several high-part relocations with | |
15441 | the same low-part relocation unless there's no alternative. Having | |
15442 | several high parts for the same low part is a GNU extension; this rule | |
15443 | allows careful users to avoid it. | |
15444 | ||
15445 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15446 | with the last high-part relocation being at the front of the list. | |
15447 | It therefore makes sense to choose the last matching low-part | |
15448 | relocation, all other things being equal. It's also easier | |
15449 | to code that way. */ | |
252b5132 RH |
15450 | |
15451 | void | |
17a2f251 | 15452 | mips_frob_file (void) |
252b5132 RH |
15453 | { |
15454 | struct mips_hi_fixup *l; | |
35903be0 | 15455 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15456 | |
15457 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15458 | { | |
15459 | segment_info_type *seginfo; | |
3b91255e RS |
15460 | bfd_boolean matched_lo_p; |
15461 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15462 | |
9c2799c2 | 15463 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15464 | |
5919d012 | 15465 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
15466 | there isn't supposed to be a matching LO. Ignore %gots against |
15467 | constants; we'll report an error for those later. */ | |
738e5348 | 15468 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab | 15469 | && !(l->fixp->fx_addsy |
9e009953 | 15470 | && pic_need_relax (l->fixp->fx_addsy))) |
5919d012 RS |
15471 | continue; |
15472 | ||
15473 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15474 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15475 | continue; |
15476 | ||
252b5132 | 15477 | seginfo = seg_info (l->seg); |
252b5132 | 15478 | |
3b91255e RS |
15479 | /* Set HI_POS to the position of this relocation in the chain. |
15480 | Set LO_POS to the position of the chosen low-part relocation. | |
15481 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15482 | relocation that matches an immediately-preceding high-part | |
15483 | relocation. */ | |
15484 | hi_pos = NULL; | |
15485 | lo_pos = NULL; | |
15486 | matched_lo_p = FALSE; | |
738e5348 | 15487 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15488 | |
3b91255e RS |
15489 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15490 | { | |
15491 | if (*pos == l->fixp) | |
15492 | hi_pos = pos; | |
15493 | ||
35903be0 | 15494 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15495 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15496 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15497 | && (lo_pos == NULL | |
15498 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15499 | || (!matched_lo_p | |
15500 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15501 | lo_pos = pos; | |
15502 | ||
15503 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15504 | && fixup_has_matching_lo_p (*pos)); | |
15505 | } | |
15506 | ||
15507 | /* If we found a match, remove the high-part relocation from its | |
15508 | current position and insert it before the low-part relocation. | |
15509 | Make the offsets match so that fixup_has_matching_lo_p() | |
15510 | will return true. | |
15511 | ||
15512 | We don't warn about unmatched high-part relocations since some | |
15513 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15514 | instructions. */ | |
15515 | if (lo_pos != NULL) | |
15516 | { | |
15517 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15518 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15519 | { |
3b91255e RS |
15520 | *hi_pos = l->fixp->fx_next; |
15521 | l->fixp->fx_next = *lo_pos; | |
15522 | *lo_pos = l->fixp; | |
252b5132 | 15523 | } |
252b5132 RH |
15524 | } |
15525 | } | |
15526 | } | |
15527 | ||
252b5132 | 15528 | int |
17a2f251 | 15529 | mips_force_relocation (fixS *fixp) |
252b5132 | 15530 | { |
ae6063d4 | 15531 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15532 | return 1; |
15533 | ||
df58fc94 RS |
15534 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15535 | so that the linker relaxation can update targets. */ | |
15536 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15537 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15538 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15539 | return 1; | |
15540 | ||
5caa2b07 MR |
15541 | /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2 |
15542 | and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and | |
15543 | microMIPS symbols so that we can do cross-mode branch diagnostics | |
15544 | and BAL to JALX conversion by the linker. */ | |
15545 | if ((fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
9d862524 MR |
15546 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 |
15547 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2) | |
15548 | && fixp->fx_addsy | |
15549 | && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp->fx_addsy))) | |
15550 | return 1; | |
15551 | ||
7361da2c | 15552 | /* We want all PC-relative relocations to be kept for R6 relaxation. */ |
912815f0 | 15553 | if (ISA_IS_R6 (file_mips_opts.isa) |
7361da2c AB |
15554 | && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15555 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 | |
15556 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 | |
15557 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 | |
15558 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 | |
15559 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL | |
15560 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL)) | |
15561 | return 1; | |
15562 | ||
3e722fb5 | 15563 | return 0; |
252b5132 RH |
15564 | } |
15565 | ||
b416ba9b MR |
15566 | /* Implement TC_FORCE_RELOCATION_ABS. */ |
15567 | ||
15568 | bfd_boolean | |
15569 | mips_force_relocation_abs (fixS *fixp) | |
15570 | { | |
15571 | if (generic_force_reloc (fixp)) | |
15572 | return TRUE; | |
15573 | ||
15574 | /* These relocations do not have enough bits in the in-place addend | |
15575 | to hold an arbitrary absolute section's offset. */ | |
15576 | if (HAVE_IN_PLACE_ADDENDS && limited_pcrel_reloc_p (fixp->fx_r_type)) | |
15577 | return TRUE; | |
15578 | ||
15579 | return FALSE; | |
15580 | } | |
15581 | ||
b886a2ab RS |
15582 | /* Read the instruction associated with RELOC from BUF. */ |
15583 | ||
15584 | static unsigned int | |
15585 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
15586 | { | |
15587 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15588 | return read_compressed_insn (buf, 4); | |
15589 | else | |
15590 | return read_insn (buf); | |
15591 | } | |
15592 | ||
15593 | /* Write instruction INSN to BUF, given that it has been relocated | |
15594 | by RELOC. */ | |
15595 | ||
15596 | static void | |
15597 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
15598 | unsigned long insn) | |
15599 | { | |
15600 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15601 | write_compressed_insn (buf, insn, 4); | |
15602 | else | |
15603 | write_insn (buf, insn); | |
15604 | } | |
15605 | ||
9d862524 MR |
15606 | /* Return TRUE if the instruction pointed to by FIXP is an invalid jump |
15607 | to a symbol in another ISA mode, which cannot be converted to JALX. */ | |
15608 | ||
15609 | static bfd_boolean | |
15610 | fix_bad_cross_mode_jump_p (fixS *fixP) | |
15611 | { | |
15612 | unsigned long opcode; | |
15613 | int other; | |
15614 | char *buf; | |
15615 | ||
15616 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15617 | return FALSE; | |
15618 | ||
15619 | other = S_GET_OTHER (fixP->fx_addsy); | |
15620 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15621 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; | |
15622 | switch (fixP->fx_r_type) | |
15623 | { | |
15624 | case BFD_RELOC_MIPS_JMP: | |
15625 | return opcode != 0x1d && opcode != 0x03 && ELF_ST_IS_COMPRESSED (other); | |
15626 | case BFD_RELOC_MICROMIPS_JMP: | |
15627 | return opcode != 0x3c && opcode != 0x3d && !ELF_ST_IS_MICROMIPS (other); | |
15628 | default: | |
15629 | return FALSE; | |
15630 | } | |
15631 | } | |
15632 | ||
15633 | /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX | |
15634 | jump to a symbol in the same ISA mode. */ | |
15635 | ||
15636 | static bfd_boolean | |
15637 | fix_bad_same_mode_jalx_p (fixS *fixP) | |
15638 | { | |
15639 | unsigned long opcode; | |
15640 | int other; | |
15641 | char *buf; | |
15642 | ||
15643 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15644 | return FALSE; | |
15645 | ||
15646 | other = S_GET_OTHER (fixP->fx_addsy); | |
15647 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15648 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; | |
15649 | switch (fixP->fx_r_type) | |
15650 | { | |
15651 | case BFD_RELOC_MIPS_JMP: | |
15652 | return opcode == 0x1d && !ELF_ST_IS_COMPRESSED (other); | |
15653 | case BFD_RELOC_MIPS16_JMP: | |
15654 | return opcode == 0x07 && ELF_ST_IS_COMPRESSED (other); | |
15655 | case BFD_RELOC_MICROMIPS_JMP: | |
15656 | return opcode == 0x3c && ELF_ST_IS_COMPRESSED (other); | |
15657 | default: | |
15658 | return FALSE; | |
15659 | } | |
15660 | } | |
15661 | ||
15662 | /* Return TRUE if the instruction pointed to by FIXP is an invalid jump | |
15663 | to a symbol whose value plus addend is not aligned according to the | |
15664 | ultimate (after linker relaxation) jump instruction's immediate field | |
15665 | requirement, either to (1 << SHIFT), or, for jumps from microMIPS to | |
15666 | regular MIPS code, to (1 << 2). */ | |
15667 | ||
15668 | static bfd_boolean | |
15669 | fix_bad_misaligned_jump_p (fixS *fixP, int shift) | |
15670 | { | |
15671 | bfd_boolean micro_to_mips_p; | |
15672 | valueT val; | |
15673 | int other; | |
15674 | ||
15675 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15676 | return FALSE; | |
15677 | ||
15678 | other = S_GET_OTHER (fixP->fx_addsy); | |
15679 | val = S_GET_VALUE (fixP->fx_addsy) | ELF_ST_IS_COMPRESSED (other); | |
15680 | val += fixP->fx_offset; | |
15681 | micro_to_mips_p = (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
15682 | && !ELF_ST_IS_MICROMIPS (other)); | |
15683 | return ((val & ((1 << (micro_to_mips_p ? 2 : shift)) - 1)) | |
15684 | != ELF_ST_IS_COMPRESSED (other)); | |
15685 | } | |
15686 | ||
15687 | /* Return TRUE if the instruction pointed to by FIXP is an invalid branch | |
15688 | to a symbol whose annotation indicates another ISA mode. For absolute | |
a6ebf616 MR |
15689 | symbols check the ISA bit instead. |
15690 | ||
15691 | We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS | |
15692 | symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular | |
15693 | MIPS symbols and associated with BAL instructions as these instructions | |
de194d85 | 15694 | may be converted to JALX by the linker. */ |
9d862524 MR |
15695 | |
15696 | static bfd_boolean | |
15697 | fix_bad_cross_mode_branch_p (fixS *fixP) | |
15698 | { | |
15699 | bfd_boolean absolute_p; | |
15700 | unsigned long opcode; | |
15701 | asection *symsec; | |
15702 | valueT val; | |
15703 | int other; | |
15704 | char *buf; | |
15705 | ||
8b10b0b3 MR |
15706 | if (mips_ignore_branch_isa) |
15707 | return FALSE; | |
15708 | ||
9d862524 MR |
15709 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
15710 | return FALSE; | |
15711 | ||
15712 | symsec = S_GET_SEGMENT (fixP->fx_addsy); | |
15713 | absolute_p = bfd_is_abs_section (symsec); | |
15714 | ||
15715 | val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset; | |
15716 | other = S_GET_OTHER (fixP->fx_addsy); | |
15717 | ||
15718 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15719 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 16; | |
15720 | switch (fixP->fx_r_type) | |
15721 | { | |
15722 | case BFD_RELOC_16_PCREL_S2: | |
a6ebf616 MR |
15723 | return ((absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other)) |
15724 | && opcode != 0x0411); | |
15725 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15726 | return ((absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other)) | |
15727 | && opcode != 0x4060); | |
9d862524 MR |
15728 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15729 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
15730 | return absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other); | |
15731 | case BFD_RELOC_MIPS16_16_PCREL_S1: | |
15732 | return absolute_p ? !(val & 1) : !ELF_ST_IS_MIPS16 (other); | |
15733 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
15734 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
9d862524 MR |
15735 | return absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other); |
15736 | default: | |
15737 | abort (); | |
15738 | } | |
15739 | } | |
15740 | ||
15741 | /* Return TRUE if the symbol plus addend associated with a regular MIPS | |
15742 | branch instruction pointed to by FIXP is not aligned according to the | |
15743 | branch instruction's immediate field requirement. We need the addend | |
15744 | to preserve the ISA bit and also the sum must not have bit 2 set. We | |
15745 | must explicitly OR in the ISA bit from symbol annotation as the bit | |
15746 | won't be set in the symbol's value then. */ | |
15747 | ||
15748 | static bfd_boolean | |
15749 | fix_bad_misaligned_branch_p (fixS *fixP) | |
15750 | { | |
15751 | bfd_boolean absolute_p; | |
15752 | asection *symsec; | |
15753 | valueT isa_bit; | |
15754 | valueT val; | |
15755 | valueT off; | |
15756 | int other; | |
15757 | ||
15758 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15759 | return FALSE; | |
15760 | ||
15761 | symsec = S_GET_SEGMENT (fixP->fx_addsy); | |
15762 | absolute_p = bfd_is_abs_section (symsec); | |
15763 | ||
15764 | val = S_GET_VALUE (fixP->fx_addsy); | |
15765 | other = S_GET_OTHER (fixP->fx_addsy); | |
15766 | off = fixP->fx_offset; | |
15767 | ||
15768 | isa_bit = absolute_p ? (val + off) & 1 : ELF_ST_IS_COMPRESSED (other); | |
15769 | val |= ELF_ST_IS_COMPRESSED (other); | |
15770 | val += off; | |
15771 | return (val & 0x3) != isa_bit; | |
15772 | } | |
15773 | ||
52031738 FS |
15774 | /* Calculate the relocation target by masking off ISA mode bit before |
15775 | combining symbol and addend. */ | |
15776 | ||
15777 | static valueT | |
15778 | fix_bad_misaligned_address (fixS *fixP) | |
15779 | { | |
15780 | valueT val; | |
15781 | valueT off; | |
15782 | unsigned isa_mode; | |
15783 | gas_assert (fixP != NULL && fixP->fx_addsy != NULL); | |
15784 | val = S_GET_VALUE (fixP->fx_addsy); | |
15785 | off = fixP->fx_offset; | |
15786 | isa_mode = (ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixP->fx_addsy)) | |
15787 | ? 1 : 0); | |
15788 | ||
15789 | return ((val & ~isa_mode) + off); | |
15790 | } | |
15791 | ||
9d862524 MR |
15792 | /* Make the necessary checks on a regular MIPS branch pointed to by FIXP |
15793 | and its calculated value VAL. */ | |
15794 | ||
15795 | static void | |
15796 | fix_validate_branch (fixS *fixP, valueT val) | |
15797 | { | |
15798 | if (fixP->fx_done && (val & 0x3) != 0) | |
15799 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15800 | _("branch to misaligned address (0x%lx)"), | |
15801 | (long) (val + md_pcrel_from (fixP))); | |
15802 | else if (fix_bad_cross_mode_branch_p (fixP)) | |
15803 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15804 | _("branch to a symbol in another ISA mode")); | |
15805 | else if (fix_bad_misaligned_branch_p (fixP)) | |
15806 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15807 | _("branch to misaligned address (0x%lx)"), | |
52031738 | 15808 | (long) fix_bad_misaligned_address (fixP)); |
9d862524 MR |
15809 | else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x3) != 0) |
15810 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15811 | _("cannot encode misaligned addend " | |
15812 | "in the relocatable field (0x%lx)"), | |
15813 | (long) fixP->fx_offset); | |
15814 | } | |
15815 | ||
252b5132 RH |
15816 | /* Apply a fixup to the object file. */ |
15817 | ||
94f592af | 15818 | void |
55cf6793 | 15819 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15820 | { |
4d68580a | 15821 | char *buf; |
b886a2ab | 15822 | unsigned long insn; |
a7ebbfdf | 15823 | reloc_howto_type *howto; |
252b5132 | 15824 | |
d56a8dda RS |
15825 | if (fixP->fx_pcrel) |
15826 | switch (fixP->fx_r_type) | |
15827 | { | |
15828 | case BFD_RELOC_16_PCREL_S2: | |
c9775dde | 15829 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
d56a8dda RS |
15830 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15831 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15832 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15833 | case BFD_RELOC_32_PCREL: | |
7361da2c AB |
15834 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15835 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
15836 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
15837 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
15838 | case BFD_RELOC_HI16_S_PCREL: | |
15839 | case BFD_RELOC_LO16_PCREL: | |
d56a8dda RS |
15840 | break; |
15841 | ||
15842 | case BFD_RELOC_32: | |
15843 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
15844 | break; | |
15845 | ||
15846 | default: | |
15847 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15848 | _("PC-relative reference to a different section")); | |
15849 | break; | |
15850 | } | |
15851 | ||
15852 | /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations | |
15853 | that have no MIPS ELF equivalent. */ | |
15854 | if (fixP->fx_r_type != BFD_RELOC_8) | |
15855 | { | |
15856 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15857 | if (!howto) | |
15858 | return; | |
15859 | } | |
65551fa4 | 15860 | |
df58fc94 RS |
15861 | gas_assert (fixP->fx_size == 2 |
15862 | || fixP->fx_size == 4 | |
d56a8dda | 15863 | || fixP->fx_r_type == BFD_RELOC_8 |
90ecf173 MR |
15864 | || fixP->fx_r_type == BFD_RELOC_16 |
15865 | || fixP->fx_r_type == BFD_RELOC_64 | |
15866 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15867 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15868 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15869 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15870 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
2f0c68f2 CM |
15871 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64 |
15872 | || fixP->fx_r_type == BFD_RELOC_NONE); | |
252b5132 | 15873 | |
4d68580a | 15874 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15875 | |
b1dca8ee RS |
15876 | /* Don't treat parts of a composite relocation as done. There are two |
15877 | reasons for this: | |
15878 | ||
15879 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15880 | should nevertheless be emitted if the first part is. | |
15881 | ||
15882 | (2) In normal usage, composite relocations are never assembly-time | |
15883 | constants. The easiest way of dealing with the pathological | |
15884 | exceptions is to generate a relocation against STN_UNDEF and | |
15885 | leave everything up to the linker. */ | |
3994f87e | 15886 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15887 | fixP->fx_done = 1; |
15888 | ||
15889 | switch (fixP->fx_r_type) | |
15890 | { | |
3f98094e DJ |
15891 | case BFD_RELOC_MIPS_TLS_GD: |
15892 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15893 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15894 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15895 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15896 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15897 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15898 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15899 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15900 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15901 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15902 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15903 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15904 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15905 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15906 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15907 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15908 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15909 | case BFD_RELOC_MIPS16_TLS_GD: |
15910 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15911 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15912 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15913 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15914 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15915 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
4512dafa MR |
15916 | if (fixP->fx_addsy) |
15917 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
15918 | else | |
15919 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15920 | _("TLS relocation against a constant")); | |
15921 | break; | |
3f98094e | 15922 | |
252b5132 | 15923 | case BFD_RELOC_MIPS_JMP: |
9d862524 MR |
15924 | case BFD_RELOC_MIPS16_JMP: |
15925 | case BFD_RELOC_MICROMIPS_JMP: | |
15926 | { | |
15927 | int shift; | |
15928 | ||
15929 | gas_assert (!fixP->fx_done); | |
15930 | ||
15931 | /* Shift is 2, unusually, for microMIPS JALX. */ | |
15932 | if (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
15933 | && (read_compressed_insn (buf, 4) >> 26) != 0x3c) | |
15934 | shift = 1; | |
15935 | else | |
15936 | shift = 2; | |
15937 | ||
15938 | if (fix_bad_cross_mode_jump_p (fixP)) | |
15939 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15940 | _("jump to a symbol in another ISA mode")); | |
15941 | else if (fix_bad_same_mode_jalx_p (fixP)) | |
15942 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15943 | _("JALX to a symbol in the same ISA mode")); | |
15944 | else if (fix_bad_misaligned_jump_p (fixP, shift)) | |
15945 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15946 | _("jump to misaligned address (0x%lx)"), | |
52031738 | 15947 | (long) fix_bad_misaligned_address (fixP)); |
9d862524 MR |
15948 | else if (HAVE_IN_PLACE_ADDENDS |
15949 | && (fixP->fx_offset & ((1 << shift) - 1)) != 0) | |
15950 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15951 | _("cannot encode misaligned addend " | |
15952 | "in the relocatable field (0x%lx)"), | |
15953 | (long) fixP->fx_offset); | |
15954 | } | |
15955 | /* Fall through. */ | |
15956 | ||
e369bcce TS |
15957 | case BFD_RELOC_MIPS_SHIFT5: |
15958 | case BFD_RELOC_MIPS_SHIFT6: | |
15959 | case BFD_RELOC_MIPS_GOT_DISP: | |
15960 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15961 | case BFD_RELOC_MIPS_GOT_OFST: | |
15962 | case BFD_RELOC_MIPS_SUB: | |
15963 | case BFD_RELOC_MIPS_INSERT_A: | |
15964 | case BFD_RELOC_MIPS_INSERT_B: | |
15965 | case BFD_RELOC_MIPS_DELETE: | |
15966 | case BFD_RELOC_MIPS_HIGHEST: | |
15967 | case BFD_RELOC_MIPS_HIGHER: | |
15968 | case BFD_RELOC_MIPS_SCN_DISP: | |
15969 | case BFD_RELOC_MIPS_REL16: | |
15970 | case BFD_RELOC_MIPS_RELGOT: | |
15971 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15972 | case BFD_RELOC_HI16: |
15973 | case BFD_RELOC_HI16_S: | |
b886a2ab | 15974 | case BFD_RELOC_LO16: |
cdf6fd85 | 15975 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15976 | case BFD_RELOC_MIPS_LITERAL: |
15977 | case BFD_RELOC_MIPS_CALL16: | |
15978 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15979 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15980 | case BFD_RELOC_MIPS_GOT_HI16: |
15981 | case BFD_RELOC_MIPS_GOT_LO16: | |
15982 | case BFD_RELOC_MIPS_CALL_HI16: | |
15983 | case BFD_RELOC_MIPS_CALL_LO16: | |
41947d9e MR |
15984 | case BFD_RELOC_HI16_S_PCREL: |
15985 | case BFD_RELOC_LO16_PCREL: | |
252b5132 | 15986 | case BFD_RELOC_MIPS16_GPREL: |
738e5348 RS |
15987 | case BFD_RELOC_MIPS16_GOT16: |
15988 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15989 | case BFD_RELOC_MIPS16_HI16: |
15990 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 15991 | case BFD_RELOC_MIPS16_LO16: |
df58fc94 RS |
15992 | case BFD_RELOC_MICROMIPS_GOT_DISP: |
15993 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15994 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15995 | case BFD_RELOC_MICROMIPS_SUB: | |
15996 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15997 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15998 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15999 | case BFD_RELOC_MICROMIPS_JALR: | |
16000 | case BFD_RELOC_MICROMIPS_HI16: | |
16001 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 16002 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
16003 | case BFD_RELOC_MICROMIPS_GPREL16: |
16004 | case BFD_RELOC_MICROMIPS_LITERAL: | |
16005 | case BFD_RELOC_MICROMIPS_CALL16: | |
16006 | case BFD_RELOC_MICROMIPS_GOT16: | |
16007 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
16008 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
16009 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
16010 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
067ec077 | 16011 | case BFD_RELOC_MIPS_EH: |
b886a2ab RS |
16012 | if (fixP->fx_done) |
16013 | { | |
16014 | offsetT value; | |
16015 | ||
16016 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
16017 | { | |
16018 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
16019 | if (mips16_reloc_p (fixP->fx_r_type)) | |
16020 | insn |= mips16_immed_extend (value, 16); | |
16021 | else | |
16022 | insn |= (value & 0xffff); | |
16023 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
16024 | } | |
16025 | else | |
16026 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 16027 | _("unsupported constant in relocation")); |
b886a2ab | 16028 | } |
252b5132 RH |
16029 | break; |
16030 | ||
252b5132 RH |
16031 | case BFD_RELOC_64: |
16032 | /* This is handled like BFD_RELOC_32, but we output a sign | |
16033 | extended value if we are only 32 bits. */ | |
3e722fb5 | 16034 | if (fixP->fx_done) |
252b5132 RH |
16035 | { |
16036 | if (8 <= sizeof (valueT)) | |
4d68580a | 16037 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
16038 | else |
16039 | { | |
a7ebbfdf | 16040 | valueT hiv; |
252b5132 | 16041 | |
a7ebbfdf | 16042 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
16043 | hiv = 0xffffffff; |
16044 | else | |
16045 | hiv = 0; | |
4d68580a RS |
16046 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
16047 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
16048 | } |
16049 | } | |
16050 | break; | |
16051 | ||
056350c6 | 16052 | case BFD_RELOC_RVA: |
252b5132 | 16053 | case BFD_RELOC_32: |
b47468a6 | 16054 | case BFD_RELOC_32_PCREL: |
252b5132 | 16055 | case BFD_RELOC_16: |
d56a8dda | 16056 | case BFD_RELOC_8: |
252b5132 | 16057 | /* If we are deleting this reloc entry, we must fill in the |
54f4ddb3 TS |
16058 | value now. This can happen if we have a .word which is not |
16059 | resolved when it appears but is later defined. */ | |
252b5132 | 16060 | if (fixP->fx_done) |
4d68580a | 16061 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
16062 | break; |
16063 | ||
7361da2c | 16064 | case BFD_RELOC_MIPS_21_PCREL_S2: |
9d862524 | 16065 | fix_validate_branch (fixP, *valP); |
41947d9e MR |
16066 | if (!fixP->fx_done) |
16067 | break; | |
16068 | ||
16069 | if (*valP + 0x400000 <= 0x7fffff) | |
16070 | { | |
16071 | insn = read_insn (buf); | |
16072 | insn |= (*valP >> 2) & 0x1fffff; | |
16073 | write_insn (buf, insn); | |
16074 | } | |
16075 | else | |
16076 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16077 | _("branch out of range")); | |
16078 | break; | |
16079 | ||
7361da2c | 16080 | case BFD_RELOC_MIPS_26_PCREL_S2: |
9d862524 | 16081 | fix_validate_branch (fixP, *valP); |
41947d9e MR |
16082 | if (!fixP->fx_done) |
16083 | break; | |
7361da2c | 16084 | |
41947d9e MR |
16085 | if (*valP + 0x8000000 <= 0xfffffff) |
16086 | { | |
16087 | insn = read_insn (buf); | |
16088 | insn |= (*valP >> 2) & 0x3ffffff; | |
16089 | write_insn (buf, insn); | |
16090 | } | |
16091 | else | |
16092 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16093 | _("branch out of range")); | |
7361da2c AB |
16094 | break; |
16095 | ||
16096 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
717ba204 | 16097 | if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0) |
7361da2c | 16098 | as_bad_where (fixP->fx_file, fixP->fx_line, |
0866e94c MF |
16099 | _("PC-relative access using misaligned symbol (%lx)"), |
16100 | (long) S_GET_VALUE (fixP->fx_addsy)); | |
16101 | if ((fixP->fx_offset & 0x7) != 0) | |
16102 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16103 | _("PC-relative access using misaligned offset (%lx)"), | |
16104 | (long) fixP->fx_offset); | |
41947d9e MR |
16105 | if (!fixP->fx_done) |
16106 | break; | |
7361da2c | 16107 | |
41947d9e MR |
16108 | if (*valP + 0x100000 <= 0x1fffff) |
16109 | { | |
16110 | insn = read_insn (buf); | |
16111 | insn |= (*valP >> 3) & 0x3ffff; | |
16112 | write_insn (buf, insn); | |
16113 | } | |
16114 | else | |
16115 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16116 | _("PC-relative access out of range")); | |
7361da2c AB |
16117 | break; |
16118 | ||
16119 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
16120 | if ((*valP & 0x3) != 0) | |
16121 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16122 | _("PC-relative access to misaligned address (%lx)"), | |
717ba204 | 16123 | (long) *valP); |
41947d9e MR |
16124 | if (!fixP->fx_done) |
16125 | break; | |
7361da2c | 16126 | |
41947d9e MR |
16127 | if (*valP + 0x100000 <= 0x1fffff) |
16128 | { | |
16129 | insn = read_insn (buf); | |
16130 | insn |= (*valP >> 2) & 0x7ffff; | |
16131 | write_insn (buf, insn); | |
16132 | } | |
16133 | else | |
16134 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16135 | _("PC-relative access out of range")); | |
7361da2c AB |
16136 | break; |
16137 | ||
252b5132 | 16138 | case BFD_RELOC_16_PCREL_S2: |
9d862524 | 16139 | fix_validate_branch (fixP, *valP); |
cb56d3d3 | 16140 | |
54f4ddb3 TS |
16141 | /* We need to save the bits in the instruction since fixup_segment() |
16142 | might be deleting the relocation entry (i.e., a branch within | |
16143 | the current segment). */ | |
a7ebbfdf | 16144 | if (! fixP->fx_done) |
bb2d6cd7 | 16145 | break; |
252b5132 | 16146 | |
54f4ddb3 | 16147 | /* Update old instruction data. */ |
4d68580a | 16148 | insn = read_insn (buf); |
252b5132 | 16149 | |
a7ebbfdf TS |
16150 | if (*valP + 0x20000 <= 0x3ffff) |
16151 | { | |
16152 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 16153 | write_insn (buf, insn); |
a7ebbfdf | 16154 | } |
ce8ad872 | 16155 | else if (fixP->fx_tcbit2 |
a7ebbfdf TS |
16156 | && fixP->fx_done |
16157 | && fixP->fx_frag->fr_address >= text_section->vma | |
16158 | && (fixP->fx_frag->fr_address | |
fd361982 | 16159 | < text_section->vma + bfd_section_size (text_section)) |
a7ebbfdf TS |
16160 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
16161 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
16162 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
16163 | { |
16164 | /* The branch offset is too large. If this is an | |
16165 | unconditional branch, and we are not generating PIC code, | |
16166 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
16167 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
16168 | insn = 0x0c000000; /* jal */ | |
252b5132 | 16169 | else |
a7ebbfdf TS |
16170 | insn = 0x08000000; /* j */ |
16171 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
16172 | fixP->fx_done = 0; | |
16173 | fixP->fx_addsy = section_symbol (text_section); | |
16174 | *valP += md_pcrel_from (fixP); | |
4d68580a | 16175 | write_insn (buf, insn); |
a7ebbfdf TS |
16176 | } |
16177 | else | |
16178 | { | |
16179 | /* If we got here, we have branch-relaxation disabled, | |
16180 | and there's nothing we can do to fix this instruction | |
16181 | without turning it into a longer sequence. */ | |
16182 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 16183 | _("branch out of range")); |
252b5132 | 16184 | } |
252b5132 RH |
16185 | break; |
16186 | ||
c9775dde | 16187 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
df58fc94 RS |
16188 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
16189 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
16190 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
96e9ba5f | 16191 | gas_assert (!fixP->fx_done); |
9d862524 MR |
16192 | if (fix_bad_cross_mode_branch_p (fixP)) |
16193 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16194 | _("branch to a symbol in another ISA mode")); | |
16195 | else if (fixP->fx_addsy | |
16196 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) | |
16197 | && !bfd_is_abs_section (S_GET_SEGMENT (fixP->fx_addsy)) | |
16198 | && (fixP->fx_offset & 0x1) != 0) | |
16199 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16200 | _("branch to misaligned address (0x%lx)"), | |
52031738 | 16201 | (long) fix_bad_misaligned_address (fixP)); |
9d862524 MR |
16202 | else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x1) != 0) |
16203 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16204 | _("cannot encode misaligned addend " | |
16205 | "in the relocatable field (0x%lx)"), | |
16206 | (long) fixP->fx_offset); | |
df58fc94 RS |
16207 | break; |
16208 | ||
252b5132 RH |
16209 | case BFD_RELOC_VTABLE_INHERIT: |
16210 | fixP->fx_done = 0; | |
16211 | if (fixP->fx_addsy | |
16212 | && !S_IS_DEFINED (fixP->fx_addsy) | |
16213 | && !S_IS_WEAK (fixP->fx_addsy)) | |
16214 | S_SET_WEAK (fixP->fx_addsy); | |
16215 | break; | |
16216 | ||
2f0c68f2 | 16217 | case BFD_RELOC_NONE: |
252b5132 RH |
16218 | case BFD_RELOC_VTABLE_ENTRY: |
16219 | fixP->fx_done = 0; | |
16220 | break; | |
16221 | ||
16222 | default: | |
b37df7c4 | 16223 | abort (); |
252b5132 | 16224 | } |
a7ebbfdf TS |
16225 | |
16226 | /* Remember value for tc_gen_reloc. */ | |
16227 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
16228 | } |
16229 | ||
252b5132 | 16230 | static symbolS * |
17a2f251 | 16231 | get_symbol (void) |
252b5132 RH |
16232 | { |
16233 | int c; | |
16234 | char *name; | |
16235 | symbolS *p; | |
16236 | ||
d02603dc | 16237 | c = get_symbol_name (&name); |
252b5132 | 16238 | p = (symbolS *) symbol_find_or_make (name); |
d02603dc | 16239 | (void) restore_line_pointer (c); |
252b5132 RH |
16240 | return p; |
16241 | } | |
16242 | ||
742a56fe RS |
16243 | /* Align the current frag to a given power of two. If a particular |
16244 | fill byte should be used, FILL points to an integer that contains | |
16245 | that byte, otherwise FILL is null. | |
16246 | ||
462427c4 RS |
16247 | This function used to have the comment: |
16248 | ||
16249 | The MIPS assembler also automatically adjusts any preceding label. | |
16250 | ||
16251 | The implementation therefore applied the adjustment to a maximum of | |
16252 | one label. However, other label adjustments are applied to batches | |
16253 | of labels, and adjusting just one caused problems when new labels | |
16254 | were added for the sake of debugging or unwind information. | |
16255 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
16256 | |
16257 | static void | |
462427c4 | 16258 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 16259 | { |
7d10b47d | 16260 | mips_emit_delays (); |
df58fc94 | 16261 | mips_record_compressed_mode (); |
742a56fe RS |
16262 | if (fill == NULL && subseg_text_p (now_seg)) |
16263 | frag_align_code (to, 0); | |
16264 | else | |
16265 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 16266 | record_alignment (now_seg, to); |
770c0151 | 16267 | mips_move_labels (labels, subseg_text_p (now_seg)); |
252b5132 RH |
16268 | } |
16269 | ||
16270 | /* Align to a given power of two. .align 0 turns off the automatic | |
16271 | alignment used by the data creating pseudo-ops. */ | |
16272 | ||
16273 | static void | |
17a2f251 | 16274 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 16275 | { |
742a56fe | 16276 | int temp, fill_value, *fill_ptr; |
49954fb4 | 16277 | long max_alignment = 28; |
252b5132 | 16278 | |
54f4ddb3 | 16279 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 16280 | to the aligned address. |
54f4ddb3 | 16281 | o It's not documented but auto alignment is reinstated by |
252b5132 | 16282 | a .align pseudo instruction. |
54f4ddb3 | 16283 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 16284 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 16285 | We don't. */ |
252b5132 RH |
16286 | |
16287 | temp = get_absolute_expression (); | |
16288 | if (temp > max_alignment) | |
1661c76c | 16289 | as_bad (_("alignment too large, %d assumed"), temp = max_alignment); |
252b5132 RH |
16290 | else if (temp < 0) |
16291 | { | |
1661c76c | 16292 | as_warn (_("alignment negative, 0 assumed")); |
252b5132 RH |
16293 | temp = 0; |
16294 | } | |
16295 | if (*input_line_pointer == ',') | |
16296 | { | |
f9419b05 | 16297 | ++input_line_pointer; |
742a56fe RS |
16298 | fill_value = get_absolute_expression (); |
16299 | fill_ptr = &fill_value; | |
252b5132 RH |
16300 | } |
16301 | else | |
742a56fe | 16302 | fill_ptr = 0; |
252b5132 RH |
16303 | if (temp) |
16304 | { | |
a8dbcb85 TS |
16305 | segment_info_type *si = seg_info (now_seg); |
16306 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 16307 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 16308 | auto_align = 1; |
462427c4 | 16309 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
16310 | } |
16311 | else | |
16312 | { | |
16313 | auto_align = 0; | |
16314 | } | |
16315 | ||
16316 | demand_empty_rest_of_line (); | |
16317 | } | |
16318 | ||
252b5132 | 16319 | static void |
17a2f251 | 16320 | s_change_sec (int sec) |
252b5132 RH |
16321 | { |
16322 | segT seg; | |
16323 | ||
252b5132 RH |
16324 | /* The ELF backend needs to know that we are changing sections, so |
16325 | that .previous works correctly. We could do something like check | |
b6ff326e | 16326 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
16327 | as it would not be appropriate to use it in the section changing |
16328 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
16329 | This should be cleaner, somehow. */ | |
f3ded42a | 16330 | obj_elf_section_change_hook (); |
252b5132 | 16331 | |
7d10b47d | 16332 | mips_emit_delays (); |
6a32d874 | 16333 | |
252b5132 RH |
16334 | switch (sec) |
16335 | { | |
16336 | case 't': | |
16337 | s_text (0); | |
16338 | break; | |
16339 | case 'd': | |
16340 | s_data (0); | |
16341 | break; | |
16342 | case 'b': | |
16343 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
16344 | demand_empty_rest_of_line (); | |
16345 | break; | |
16346 | ||
16347 | case 'r': | |
4d0d148d TS |
16348 | seg = subseg_new (RDATA_SECTION_NAME, |
16349 | (subsegT) get_absolute_expression ()); | |
fd361982 AM |
16350 | bfd_set_section_flags (seg, (SEC_ALLOC | SEC_LOAD | SEC_READONLY |
16351 | | SEC_RELOC | SEC_DATA)); | |
f3ded42a RS |
16352 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
16353 | record_alignment (seg, 4); | |
4d0d148d | 16354 | demand_empty_rest_of_line (); |
252b5132 RH |
16355 | break; |
16356 | ||
16357 | case 's': | |
4d0d148d | 16358 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
a4dd6c97 AM |
16359 | bfd_set_section_flags (seg, (SEC_ALLOC | SEC_LOAD | SEC_RELOC |
16360 | | SEC_DATA | SEC_SMALL_DATA)); | |
f3ded42a RS |
16361 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
16362 | record_alignment (seg, 4); | |
4d0d148d TS |
16363 | demand_empty_rest_of_line (); |
16364 | break; | |
998b3c36 MR |
16365 | |
16366 | case 'B': | |
16367 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
a4dd6c97 | 16368 | bfd_set_section_flags (seg, SEC_ALLOC | SEC_SMALL_DATA); |
f3ded42a RS |
16369 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
16370 | record_alignment (seg, 4); | |
998b3c36 MR |
16371 | demand_empty_rest_of_line (); |
16372 | break; | |
252b5132 RH |
16373 | } |
16374 | ||
16375 | auto_align = 1; | |
16376 | } | |
b34976b6 | 16377 | |
cca86cc8 | 16378 | void |
17a2f251 | 16379 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 16380 | { |
d02603dc | 16381 | char *saved_ilp; |
cca86cc8 | 16382 | char *section_name; |
d02603dc | 16383 | char c, endc; |
684022ea | 16384 | char next_c = 0; |
cca86cc8 SC |
16385 | int section_type; |
16386 | int section_flag; | |
16387 | int section_entry_size; | |
16388 | int section_alignment; | |
b34976b6 | 16389 | |
d02603dc NC |
16390 | saved_ilp = input_line_pointer; |
16391 | endc = get_symbol_name (§ion_name); | |
16392 | c = (endc == '"' ? input_line_pointer[1] : endc); | |
a816d1ed | 16393 | if (c) |
d02603dc | 16394 | next_c = input_line_pointer [(endc == '"' ? 2 : 1)]; |
cca86cc8 | 16395 | |
4cf0dd0d TS |
16396 | /* Do we have .section Name<,"flags">? */ |
16397 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 16398 | { |
d02603dc NC |
16399 | /* Just after name is now '\0'. */ |
16400 | (void) restore_line_pointer (endc); | |
16401 | input_line_pointer = saved_ilp; | |
cca86cc8 SC |
16402 | obj_elf_section (ignore); |
16403 | return; | |
16404 | } | |
d02603dc NC |
16405 | |
16406 | section_name = xstrdup (section_name); | |
16407 | c = restore_line_pointer (endc); | |
16408 | ||
cca86cc8 SC |
16409 | input_line_pointer++; |
16410 | ||
16411 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
16412 | if (c == ',') | |
16413 | section_type = get_absolute_expression (); | |
16414 | else | |
16415 | section_type = 0; | |
d02603dc | 16416 | |
cca86cc8 SC |
16417 | if (*input_line_pointer++ == ',') |
16418 | section_flag = get_absolute_expression (); | |
16419 | else | |
16420 | section_flag = 0; | |
d02603dc | 16421 | |
cca86cc8 SC |
16422 | if (*input_line_pointer++ == ',') |
16423 | section_entry_size = get_absolute_expression (); | |
16424 | else | |
16425 | section_entry_size = 0; | |
d02603dc | 16426 | |
cca86cc8 SC |
16427 | if (*input_line_pointer++ == ',') |
16428 | section_alignment = get_absolute_expression (); | |
16429 | else | |
16430 | section_alignment = 0; | |
d02603dc | 16431 | |
87975d2a AM |
16432 | /* FIXME: really ignore? */ |
16433 | (void) section_alignment; | |
cca86cc8 | 16434 | |
8ab8a5c8 RS |
16435 | /* When using the generic form of .section (as implemented by obj-elf.c), |
16436 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
16437 | traditionally had to fall back on the more common @progbits instead. | |
16438 | ||
16439 | There's nothing really harmful in this, since bfd will correct | |
16440 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 16441 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
16442 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
16443 | ||
16444 | Even so, we shouldn't force users of the MIPS .section syntax to | |
16445 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
16446 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
16447 | generic type-checking code. */ | |
16448 | if (section_type == SHT_MIPS_DWARF) | |
16449 | section_type = SHT_PROGBITS; | |
16450 | ||
a8c4d40b | 16451 | obj_elf_change_section (section_name, section_type, section_flag, |
cca86cc8 | 16452 | section_entry_size, 0, 0, 0); |
a816d1ed AO |
16453 | |
16454 | if (now_seg->name != section_name) | |
16455 | free (section_name); | |
cca86cc8 | 16456 | } |
252b5132 RH |
16457 | |
16458 | void | |
17a2f251 | 16459 | mips_enable_auto_align (void) |
252b5132 RH |
16460 | { |
16461 | auto_align = 1; | |
16462 | } | |
16463 | ||
16464 | static void | |
17a2f251 | 16465 | s_cons (int log_size) |
252b5132 | 16466 | { |
a8dbcb85 TS |
16467 | segment_info_type *si = seg_info (now_seg); |
16468 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16469 | |
7d10b47d | 16470 | mips_emit_delays (); |
252b5132 | 16471 | if (log_size > 0 && auto_align) |
462427c4 | 16472 | mips_align (log_size, 0, l); |
252b5132 | 16473 | cons (1 << log_size); |
a1facbec | 16474 | mips_clear_insn_labels (); |
252b5132 RH |
16475 | } |
16476 | ||
16477 | static void | |
17a2f251 | 16478 | s_float_cons (int type) |
252b5132 | 16479 | { |
a8dbcb85 TS |
16480 | segment_info_type *si = seg_info (now_seg); |
16481 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16482 | |
7d10b47d | 16483 | mips_emit_delays (); |
252b5132 RH |
16484 | |
16485 | if (auto_align) | |
49309057 ILT |
16486 | { |
16487 | if (type == 'd') | |
462427c4 | 16488 | mips_align (3, 0, l); |
49309057 | 16489 | else |
462427c4 | 16490 | mips_align (2, 0, l); |
49309057 | 16491 | } |
252b5132 | 16492 | |
252b5132 | 16493 | float_cons (type); |
a1facbec | 16494 | mips_clear_insn_labels (); |
252b5132 RH |
16495 | } |
16496 | ||
16497 | /* Handle .globl. We need to override it because on Irix 5 you are | |
16498 | permitted to say | |
16499 | .globl foo .text | |
16500 | where foo is an undefined symbol, to mean that foo should be | |
16501 | considered to be the address of a function. */ | |
16502 | ||
16503 | static void | |
17a2f251 | 16504 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16505 | { |
16506 | char *name; | |
16507 | int c; | |
16508 | symbolS *symbolP; | |
252b5132 | 16509 | |
8a06b769 | 16510 | do |
252b5132 | 16511 | { |
d02603dc | 16512 | c = get_symbol_name (&name); |
8a06b769 TS |
16513 | symbolP = symbol_find_or_make (name); |
16514 | S_SET_EXTERNAL (symbolP); | |
16515 | ||
252b5132 | 16516 | *input_line_pointer = c; |
d02603dc | 16517 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 | 16518 | |
8a06b769 TS |
16519 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
16520 | && (*input_line_pointer != ',')) | |
16521 | { | |
16522 | char *secname; | |
16523 | asection *sec; | |
16524 | ||
d02603dc | 16525 | c = get_symbol_name (&secname); |
8a06b769 TS |
16526 | sec = bfd_get_section_by_name (stdoutput, secname); |
16527 | if (sec == NULL) | |
16528 | as_bad (_("%s: no such section"), secname); | |
d02603dc | 16529 | (void) restore_line_pointer (c); |
8a06b769 TS |
16530 | |
16531 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
d69cd47e | 16532 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
8a06b769 TS |
16533 | } |
16534 | ||
8a06b769 TS |
16535 | c = *input_line_pointer; |
16536 | if (c == ',') | |
16537 | { | |
16538 | input_line_pointer++; | |
16539 | SKIP_WHITESPACE (); | |
16540 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16541 | c = '\n'; | |
16542 | } | |
16543 | } | |
16544 | while (c == ','); | |
252b5132 | 16545 | |
252b5132 RH |
16546 | demand_empty_rest_of_line (); |
16547 | } | |
16548 | ||
d69cd47e AM |
16549 | #ifdef TE_IRIX |
16550 | /* The Irix 5 and 6 assemblers set the type of any common symbol and | |
16551 | any undefined non-function symbol to STT_OBJECT. We try to be | |
16552 | compatible, since newer Irix 5 and 6 linkers care. */ | |
16553 | ||
16554 | void | |
16555 | mips_frob_symbol (symbolS *symp ATTRIBUTE_UNUSED) | |
16556 | { | |
16557 | /* This late in assembly we can set BSF_OBJECT indiscriminately | |
16558 | and let elf.c:swap_out_syms sort out the symbol type. */ | |
16559 | flagword *flags = &symbol_get_bfdsym (symp)->flags; | |
16560 | if ((*flags & (BSF_GLOBAL | BSF_WEAK)) != 0 | |
16561 | || !S_IS_DEFINED (symp)) | |
16562 | *flags |= BSF_OBJECT; | |
16563 | } | |
16564 | #endif | |
16565 | ||
252b5132 | 16566 | static void |
17a2f251 | 16567 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16568 | { |
16569 | char *opt; | |
16570 | char c; | |
16571 | ||
d02603dc | 16572 | c = get_symbol_name (&opt); |
252b5132 RH |
16573 | |
16574 | if (*opt == 'O') | |
16575 | { | |
16576 | /* FIXME: What does this mean? */ | |
16577 | } | |
41a1578e | 16578 | else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0') |
252b5132 RH |
16579 | { |
16580 | int i; | |
16581 | ||
16582 | i = atoi (opt + 3); | |
668c5ebc MR |
16583 | if (i != 0 && i != 2) |
16584 | as_bad (_(".option pic%d not supported"), i); | |
16585 | else if (mips_pic == VXWORKS_PIC) | |
16586 | as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i); | |
16587 | else if (i == 0) | |
252b5132 RH |
16588 | mips_pic = NO_PIC; |
16589 | else if (i == 2) | |
143d77c5 | 16590 | { |
8b828383 | 16591 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16592 | mips_abicalls = TRUE; |
16593 | } | |
252b5132 | 16594 | |
4d0d148d | 16595 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16596 | { |
16597 | if (g_switch_seen && g_switch_value != 0) | |
16598 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16599 | g_switch_value = 0; | |
16600 | bfd_set_gp_size (stdoutput, 0); | |
16601 | } | |
16602 | } | |
16603 | else | |
1661c76c | 16604 | as_warn (_("unrecognized option \"%s\""), opt); |
252b5132 | 16605 | |
d02603dc | 16606 | (void) restore_line_pointer (c); |
252b5132 RH |
16607 | demand_empty_rest_of_line (); |
16608 | } | |
16609 | ||
16610 | /* This structure is used to hold a stack of .set values. */ | |
16611 | ||
e972090a NC |
16612 | struct mips_option_stack |
16613 | { | |
252b5132 RH |
16614 | struct mips_option_stack *next; |
16615 | struct mips_set_options options; | |
16616 | }; | |
16617 | ||
16618 | static struct mips_option_stack *mips_opts_stack; | |
16619 | ||
22522f88 MR |
16620 | /* Return status for .set/.module option handling. */ |
16621 | ||
16622 | enum code_option_type | |
16623 | { | |
16624 | /* Unrecognized option. */ | |
16625 | OPTION_TYPE_BAD = -1, | |
16626 | ||
16627 | /* Ordinary option. */ | |
16628 | OPTION_TYPE_NORMAL, | |
16629 | ||
16630 | /* ISA changing option. */ | |
16631 | OPTION_TYPE_ISA | |
16632 | }; | |
16633 | ||
16634 | /* Handle common .set/.module options. Return status indicating option | |
16635 | type. */ | |
16636 | ||
16637 | static enum code_option_type | |
919731af | 16638 | parse_code_option (char * name) |
252b5132 | 16639 | { |
22522f88 | 16640 | bfd_boolean isa_set = FALSE; |
c6278170 | 16641 | const struct mips_ase *ase; |
22522f88 | 16642 | |
919731af | 16643 | if (strncmp (name, "at=", 3) == 0) |
741fe287 MR |
16644 | { |
16645 | char *s = name + 3; | |
16646 | ||
16647 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
1661c76c | 16648 | as_bad (_("unrecognized register name `%s'"), s); |
741fe287 | 16649 | } |
252b5132 | 16650 | else if (strcmp (name, "at") == 0) |
919731af | 16651 | mips_opts.at = ATREG; |
252b5132 | 16652 | else if (strcmp (name, "noat") == 0) |
919731af | 16653 | mips_opts.at = ZERO; |
252b5132 | 16654 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) |
919731af | 16655 | mips_opts.nomove = 0; |
252b5132 | 16656 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) |
919731af | 16657 | mips_opts.nomove = 1; |
252b5132 | 16658 | else if (strcmp (name, "bopt") == 0) |
919731af | 16659 | mips_opts.nobopt = 0; |
252b5132 | 16660 | else if (strcmp (name, "nobopt") == 0) |
919731af | 16661 | mips_opts.nobopt = 1; |
ad3fea08 | 16662 | else if (strcmp (name, "gp=32") == 0) |
bad1aba3 | 16663 | mips_opts.gp = 32; |
ad3fea08 | 16664 | else if (strcmp (name, "gp=64") == 0) |
919731af | 16665 | mips_opts.gp = 64; |
ad3fea08 | 16666 | else if (strcmp (name, "fp=32") == 0) |
0b35dfee | 16667 | mips_opts.fp = 32; |
351cdf24 MF |
16668 | else if (strcmp (name, "fp=xx") == 0) |
16669 | mips_opts.fp = 0; | |
ad3fea08 | 16670 | else if (strcmp (name, "fp=64") == 0) |
919731af | 16671 | mips_opts.fp = 64; |
037b32b9 AN |
16672 | else if (strcmp (name, "softfloat") == 0) |
16673 | mips_opts.soft_float = 1; | |
16674 | else if (strcmp (name, "hardfloat") == 0) | |
16675 | mips_opts.soft_float = 0; | |
16676 | else if (strcmp (name, "singlefloat") == 0) | |
16677 | mips_opts.single_float = 1; | |
16678 | else if (strcmp (name, "doublefloat") == 0) | |
16679 | mips_opts.single_float = 0; | |
351cdf24 MF |
16680 | else if (strcmp (name, "nooddspreg") == 0) |
16681 | mips_opts.oddspreg = 0; | |
16682 | else if (strcmp (name, "oddspreg") == 0) | |
16683 | mips_opts.oddspreg = 1; | |
252b5132 RH |
16684 | else if (strcmp (name, "mips16") == 0 |
16685 | || strcmp (name, "MIPS-16") == 0) | |
919731af | 16686 | mips_opts.mips16 = 1; |
252b5132 RH |
16687 | else if (strcmp (name, "nomips16") == 0 |
16688 | || strcmp (name, "noMIPS-16") == 0) | |
16689 | mips_opts.mips16 = 0; | |
df58fc94 | 16690 | else if (strcmp (name, "micromips") == 0) |
919731af | 16691 | mips_opts.micromips = 1; |
df58fc94 RS |
16692 | else if (strcmp (name, "nomicromips") == 0) |
16693 | mips_opts.micromips = 0; | |
c6278170 RS |
16694 | else if (name[0] == 'n' |
16695 | && name[1] == 'o' | |
16696 | && (ase = mips_lookup_ase (name + 2))) | |
919731af | 16697 | mips_set_ase (ase, &mips_opts, FALSE); |
c6278170 | 16698 | else if ((ase = mips_lookup_ase (name))) |
919731af | 16699 | mips_set_ase (ase, &mips_opts, TRUE); |
1a2c1fad | 16700 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16701 | { |
1a2c1fad CD |
16702 | /* Permit the user to change the ISA and architecture on the fly. |
16703 | Needless to say, misuse can cause serious problems. */ | |
919731af | 16704 | if (strncmp (name, "arch=", 5) == 0) |
1a2c1fad CD |
16705 | { |
16706 | const struct mips_cpu_info *p; | |
16707 | ||
919731af | 16708 | p = mips_parse_cpu ("internal use", name + 5); |
1a2c1fad CD |
16709 | if (!p) |
16710 | as_bad (_("unknown architecture %s"), name + 5); | |
16711 | else | |
16712 | { | |
16713 | mips_opts.arch = p->cpu; | |
16714 | mips_opts.isa = p->isa; | |
22522f88 | 16715 | isa_set = TRUE; |
3315614d | 16716 | mips_opts.init_ase = p->ase; |
1a2c1fad CD |
16717 | } |
16718 | } | |
81a21e38 TS |
16719 | else if (strncmp (name, "mips", 4) == 0) |
16720 | { | |
16721 | const struct mips_cpu_info *p; | |
16722 | ||
919731af | 16723 | p = mips_parse_cpu ("internal use", name); |
81a21e38 TS |
16724 | if (!p) |
16725 | as_bad (_("unknown ISA level %s"), name + 4); | |
16726 | else | |
16727 | { | |
16728 | mips_opts.arch = p->cpu; | |
16729 | mips_opts.isa = p->isa; | |
22522f88 | 16730 | isa_set = TRUE; |
3315614d | 16731 | mips_opts.init_ase = p->ase; |
81a21e38 TS |
16732 | } |
16733 | } | |
af7ee8bf | 16734 | else |
81a21e38 | 16735 | as_bad (_("unknown ISA or architecture %s"), name); |
252b5132 RH |
16736 | } |
16737 | else if (strcmp (name, "autoextend") == 0) | |
16738 | mips_opts.noautoextend = 0; | |
16739 | else if (strcmp (name, "noautoextend") == 0) | |
16740 | mips_opts.noautoextend = 1; | |
833794fc MR |
16741 | else if (strcmp (name, "insn32") == 0) |
16742 | mips_opts.insn32 = TRUE; | |
16743 | else if (strcmp (name, "noinsn32") == 0) | |
16744 | mips_opts.insn32 = FALSE; | |
919731af | 16745 | else if (strcmp (name, "sym32") == 0) |
16746 | mips_opts.sym32 = TRUE; | |
16747 | else if (strcmp (name, "nosym32") == 0) | |
16748 | mips_opts.sym32 = FALSE; | |
16749 | else | |
22522f88 MR |
16750 | return OPTION_TYPE_BAD; |
16751 | ||
16752 | return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL; | |
919731af | 16753 | } |
16754 | ||
16755 | /* Handle the .set pseudo-op. */ | |
16756 | ||
16757 | static void | |
16758 | s_mipsset (int x ATTRIBUTE_UNUSED) | |
16759 | { | |
22522f88 | 16760 | enum code_option_type type = OPTION_TYPE_NORMAL; |
919731af | 16761 | char *name = input_line_pointer, ch; |
919731af | 16762 | |
16763 | file_mips_check_options (); | |
16764 | ||
16765 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
16766 | ++input_line_pointer; | |
16767 | ch = *input_line_pointer; | |
16768 | *input_line_pointer = '\0'; | |
16769 | ||
16770 | if (strchr (name, ',')) | |
16771 | { | |
16772 | /* Generic ".set" directive; use the generic handler. */ | |
16773 | *input_line_pointer = ch; | |
16774 | input_line_pointer = name; | |
16775 | s_set (0); | |
16776 | return; | |
16777 | } | |
16778 | ||
16779 | if (strcmp (name, "reorder") == 0) | |
16780 | { | |
16781 | if (mips_opts.noreorder) | |
16782 | end_noreorder (); | |
16783 | } | |
16784 | else if (strcmp (name, "noreorder") == 0) | |
16785 | { | |
16786 | if (!mips_opts.noreorder) | |
16787 | start_noreorder (); | |
16788 | } | |
16789 | else if (strcmp (name, "macro") == 0) | |
16790 | mips_opts.warn_about_macros = 0; | |
16791 | else if (strcmp (name, "nomacro") == 0) | |
16792 | { | |
16793 | if (mips_opts.noreorder == 0) | |
16794 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16795 | mips_opts.warn_about_macros = 1; | |
16796 | } | |
16797 | else if (strcmp (name, "gp=default") == 0) | |
16798 | mips_opts.gp = file_mips_opts.gp; | |
16799 | else if (strcmp (name, "fp=default") == 0) | |
16800 | mips_opts.fp = file_mips_opts.fp; | |
16801 | else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) | |
16802 | { | |
16803 | mips_opts.isa = file_mips_opts.isa; | |
16804 | mips_opts.arch = file_mips_opts.arch; | |
3315614d | 16805 | mips_opts.init_ase = file_mips_opts.init_ase; |
919731af | 16806 | mips_opts.gp = file_mips_opts.gp; |
16807 | mips_opts.fp = file_mips_opts.fp; | |
16808 | } | |
252b5132 RH |
16809 | else if (strcmp (name, "push") == 0) |
16810 | { | |
16811 | struct mips_option_stack *s; | |
16812 | ||
325801bd | 16813 | s = XNEW (struct mips_option_stack); |
252b5132 RH |
16814 | s->next = mips_opts_stack; |
16815 | s->options = mips_opts; | |
16816 | mips_opts_stack = s; | |
16817 | } | |
16818 | else if (strcmp (name, "pop") == 0) | |
16819 | { | |
16820 | struct mips_option_stack *s; | |
16821 | ||
16822 | s = mips_opts_stack; | |
16823 | if (s == NULL) | |
16824 | as_bad (_(".set pop with no .set push")); | |
16825 | else | |
16826 | { | |
16827 | /* If we're changing the reorder mode we need to handle | |
16828 | delay slots correctly. */ | |
16829 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16830 | start_noreorder (); |
252b5132 | 16831 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16832 | end_noreorder (); |
252b5132 RH |
16833 | |
16834 | mips_opts = s->options; | |
16835 | mips_opts_stack = s->next; | |
16836 | free (s); | |
16837 | } | |
16838 | } | |
22522f88 MR |
16839 | else |
16840 | { | |
16841 | type = parse_code_option (name); | |
16842 | if (type == OPTION_TYPE_BAD) | |
16843 | as_warn (_("tried to set unrecognized symbol: %s\n"), name); | |
16844 | } | |
919731af | 16845 | |
16846 | /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp | |
16847 | registers based on what is supported by the arch/cpu. */ | |
22522f88 | 16848 | if (type == OPTION_TYPE_ISA) |
e6559e01 | 16849 | { |
919731af | 16850 | switch (mips_opts.isa) |
16851 | { | |
16852 | case 0: | |
16853 | break; | |
16854 | case ISA_MIPS1: | |
351cdf24 MF |
16855 | /* MIPS I cannot support FPXX. */ |
16856 | mips_opts.fp = 32; | |
16857 | /* fall-through. */ | |
919731af | 16858 | case ISA_MIPS2: |
16859 | case ISA_MIPS32: | |
16860 | case ISA_MIPS32R2: | |
16861 | case ISA_MIPS32R3: | |
16862 | case ISA_MIPS32R5: | |
16863 | mips_opts.gp = 32; | |
351cdf24 MF |
16864 | if (mips_opts.fp != 0) |
16865 | mips_opts.fp = 32; | |
919731af | 16866 | break; |
7361da2c AB |
16867 | case ISA_MIPS32R6: |
16868 | mips_opts.gp = 32; | |
16869 | mips_opts.fp = 64; | |
16870 | break; | |
919731af | 16871 | case ISA_MIPS3: |
16872 | case ISA_MIPS4: | |
16873 | case ISA_MIPS5: | |
16874 | case ISA_MIPS64: | |
16875 | case ISA_MIPS64R2: | |
16876 | case ISA_MIPS64R3: | |
16877 | case ISA_MIPS64R5: | |
7361da2c | 16878 | case ISA_MIPS64R6: |
919731af | 16879 | mips_opts.gp = 64; |
351cdf24 MF |
16880 | if (mips_opts.fp != 0) |
16881 | { | |
16882 | if (mips_opts.arch == CPU_R5900) | |
16883 | mips_opts.fp = 32; | |
16884 | else | |
16885 | mips_opts.fp = 64; | |
16886 | } | |
919731af | 16887 | break; |
16888 | default: | |
16889 | as_bad (_("unknown ISA level %s"), name + 4); | |
16890 | break; | |
16891 | } | |
e6559e01 | 16892 | } |
919731af | 16893 | |
16894 | mips_check_options (&mips_opts, FALSE); | |
16895 | ||
16896 | mips_check_isa_supports_ases (); | |
16897 | *input_line_pointer = ch; | |
16898 | demand_empty_rest_of_line (); | |
16899 | } | |
16900 | ||
16901 | /* Handle the .module pseudo-op. */ | |
16902 | ||
16903 | static void | |
16904 | s_module (int ignore ATTRIBUTE_UNUSED) | |
16905 | { | |
16906 | char *name = input_line_pointer, ch; | |
16907 | ||
16908 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
16909 | ++input_line_pointer; | |
16910 | ch = *input_line_pointer; | |
16911 | *input_line_pointer = '\0'; | |
16912 | ||
16913 | if (!file_mips_opts_checked) | |
252b5132 | 16914 | { |
22522f88 | 16915 | if (parse_code_option (name) == OPTION_TYPE_BAD) |
919731af | 16916 | as_bad (_(".module used with unrecognized symbol: %s\n"), name); |
16917 | ||
16918 | /* Update module level settings from mips_opts. */ | |
16919 | file_mips_opts = mips_opts; | |
252b5132 | 16920 | } |
919731af | 16921 | else |
16922 | as_bad (_(".module is not permitted after generating code")); | |
16923 | ||
252b5132 RH |
16924 | *input_line_pointer = ch; |
16925 | demand_empty_rest_of_line (); | |
16926 | } | |
16927 | ||
16928 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16929 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16930 | ||
16931 | static void | |
17a2f251 | 16932 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16933 | { |
16934 | mips_pic = SVR4_PIC; | |
143d77c5 | 16935 | mips_abicalls = TRUE; |
4d0d148d TS |
16936 | |
16937 | if (g_switch_seen && g_switch_value != 0) | |
16938 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16939 | g_switch_value = 0; | |
16940 | ||
252b5132 RH |
16941 | bfd_set_gp_size (stdoutput, 0); |
16942 | demand_empty_rest_of_line (); | |
16943 | } | |
16944 | ||
16945 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16946 | PIC code. It sets the $gp register for the function based on the | |
16947 | function address, which is in the register named in the argument. | |
16948 | This uses a relocation against _gp_disp, which is handled specially | |
16949 | by the linker. The result is: | |
16950 | lui $gp,%hi(_gp_disp) | |
16951 | addiu $gp,$gp,%lo(_gp_disp) | |
16952 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16953 | The .cpload argument is normally $25 == $t9. |
16954 | ||
16955 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16956 | lui $gp,%hi(__gnu_local_gp) |
16957 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16958 | and the argument is ignored. This saves an instruction, but the |
16959 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16960 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16961 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16962 | |
16963 | static void | |
17a2f251 | 16964 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16965 | { |
16966 | expressionS ex; | |
aa6975fb ILT |
16967 | int reg; |
16968 | int in_shared; | |
252b5132 | 16969 | |
919731af | 16970 | file_mips_check_options (); |
16971 | ||
6478892d TS |
16972 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16973 | .cpload is ignored. */ | |
16974 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16975 | { |
16976 | s_ignore (0); | |
16977 | return; | |
16978 | } | |
16979 | ||
a276b80c MR |
16980 | if (mips_opts.mips16) |
16981 | { | |
16982 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16983 | ignore_rest_of_line (); | |
16984 | return; | |
16985 | } | |
16986 | ||
d3ecfc59 | 16987 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16988 | if (mips_opts.noreorder == 0) |
16989 | as_warn (_(".cpload not in noreorder section")); | |
16990 | ||
aa6975fb ILT |
16991 | reg = tc_get_register (0); |
16992 | ||
16993 | /* If we need to produce a 64-bit address, we are better off using | |
16994 | the default instruction sequence. */ | |
aed1a261 | 16995 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16996 | |
252b5132 | 16997 | ex.X_op = O_symbol; |
bbe506e8 TS |
16998 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16999 | "__gnu_local_gp"); | |
252b5132 RH |
17000 | ex.X_op_symbol = NULL; |
17001 | ex.X_add_number = 0; | |
17002 | ||
17003 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 17004 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 17005 | |
8a75745d MR |
17006 | mips_mark_labels (); |
17007 | mips_assembling_insn = TRUE; | |
17008 | ||
584892a6 | 17009 | macro_start (); |
67c0d1eb RS |
17010 | macro_build_lui (&ex, mips_gp_register); |
17011 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 17012 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
17013 | if (in_shared) |
17014 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
17015 | mips_gp_register, reg); | |
584892a6 | 17016 | macro_end (); |
252b5132 | 17017 | |
8a75745d | 17018 | mips_assembling_insn = FALSE; |
252b5132 RH |
17019 | demand_empty_rest_of_line (); |
17020 | } | |
17021 | ||
6478892d TS |
17022 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
17023 | .cpsetup $reg1, offset|$reg2, label | |
17024 | ||
17025 | If offset is given, this results in: | |
17026 | sd $gp, offset($sp) | |
956cd1d6 | 17027 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
17028 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
17029 | daddu $gp, $gp, $reg1 | |
6478892d TS |
17030 | |
17031 | If $reg2 is given, this results in: | |
40fc1451 | 17032 | or $reg2, $gp, $0 |
956cd1d6 | 17033 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
17034 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
17035 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
17036 | $reg1 is normally $25 == $t9. |
17037 | ||
17038 | The -mno-shared option replaces the last three instructions with | |
17039 | lui $gp,%hi(_gp) | |
54f4ddb3 | 17040 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 17041 | |
6478892d | 17042 | static void |
17a2f251 | 17043 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
17044 | { |
17045 | expressionS ex_off; | |
17046 | expressionS ex_sym; | |
17047 | int reg1; | |
6478892d | 17048 | |
919731af | 17049 | file_mips_check_options (); |
17050 | ||
8586fc66 | 17051 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
17052 | We also need NewABI support. */ |
17053 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
17054 | { | |
17055 | s_ignore (0); | |
17056 | return; | |
17057 | } | |
17058 | ||
a276b80c MR |
17059 | if (mips_opts.mips16) |
17060 | { | |
17061 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
17062 | ignore_rest_of_line (); | |
17063 | return; | |
17064 | } | |
17065 | ||
6478892d TS |
17066 | reg1 = tc_get_register (0); |
17067 | SKIP_WHITESPACE (); | |
17068 | if (*input_line_pointer != ',') | |
17069 | { | |
17070 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
17071 | return; | |
17072 | } | |
17073 | else | |
80245285 | 17074 | ++input_line_pointer; |
6478892d TS |
17075 | SKIP_WHITESPACE (); |
17076 | if (*input_line_pointer == '$') | |
80245285 TS |
17077 | { |
17078 | mips_cpreturn_register = tc_get_register (0); | |
17079 | mips_cpreturn_offset = -1; | |
17080 | } | |
6478892d | 17081 | else |
80245285 TS |
17082 | { |
17083 | mips_cpreturn_offset = get_absolute_expression (); | |
17084 | mips_cpreturn_register = -1; | |
17085 | } | |
6478892d TS |
17086 | SKIP_WHITESPACE (); |
17087 | if (*input_line_pointer != ',') | |
17088 | { | |
17089 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
17090 | return; | |
17091 | } | |
17092 | else | |
f9419b05 | 17093 | ++input_line_pointer; |
6478892d | 17094 | SKIP_WHITESPACE (); |
f21f8242 | 17095 | expression (&ex_sym); |
6478892d | 17096 | |
8a75745d MR |
17097 | mips_mark_labels (); |
17098 | mips_assembling_insn = TRUE; | |
17099 | ||
584892a6 | 17100 | macro_start (); |
6478892d TS |
17101 | if (mips_cpreturn_register == -1) |
17102 | { | |
17103 | ex_off.X_op = O_constant; | |
17104 | ex_off.X_add_symbol = NULL; | |
17105 | ex_off.X_op_symbol = NULL; | |
17106 | ex_off.X_add_number = mips_cpreturn_offset; | |
17107 | ||
67c0d1eb | 17108 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 17109 | BFD_RELOC_LO16, SP); |
6478892d TS |
17110 | } |
17111 | else | |
40fc1451 | 17112 | move_register (mips_cpreturn_register, mips_gp_register); |
6478892d | 17113 | |
aed1a261 | 17114 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 17115 | { |
df58fc94 | 17116 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
17117 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
17118 | BFD_RELOC_HI16_S); | |
17119 | ||
17120 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
17121 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
17122 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
17123 | ||
17124 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
17125 | mips_gp_register, reg1); | |
17126 | } | |
17127 | else | |
17128 | { | |
17129 | expressionS ex; | |
17130 | ||
17131 | ex.X_op = O_symbol; | |
4184909a | 17132 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
17133 | ex.X_op_symbol = NULL; |
17134 | ex.X_add_number = 0; | |
6e1304d8 | 17135 | |
aa6975fb ILT |
17136 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
17137 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
17138 | ||
17139 | macro_build_lui (&ex, mips_gp_register); | |
17140 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17141 | mips_gp_register, BFD_RELOC_LO16); | |
17142 | } | |
f21f8242 | 17143 | |
584892a6 | 17144 | macro_end (); |
6478892d | 17145 | |
8a75745d | 17146 | mips_assembling_insn = FALSE; |
6478892d TS |
17147 | demand_empty_rest_of_line (); |
17148 | } | |
17149 | ||
17150 | static void | |
17a2f251 | 17151 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d | 17152 | { |
919731af | 17153 | file_mips_check_options (); |
17154 | ||
6478892d | 17155 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, |
54f4ddb3 | 17156 | .cplocal is ignored. */ |
6478892d TS |
17157 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
17158 | { | |
17159 | s_ignore (0); | |
17160 | return; | |
17161 | } | |
17162 | ||
a276b80c MR |
17163 | if (mips_opts.mips16) |
17164 | { | |
17165 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
17166 | ignore_rest_of_line (); | |
17167 | return; | |
17168 | } | |
17169 | ||
6478892d | 17170 | mips_gp_register = tc_get_register (0); |
85b51719 | 17171 | demand_empty_rest_of_line (); |
6478892d TS |
17172 | } |
17173 | ||
252b5132 RH |
17174 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
17175 | offset from $sp. The offset is remembered, and after making a PIC | |
17176 | call $gp is restored from that location. */ | |
17177 | ||
17178 | static void | |
17a2f251 | 17179 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17180 | { |
17181 | expressionS ex; | |
252b5132 | 17182 | |
919731af | 17183 | file_mips_check_options (); |
17184 | ||
6478892d | 17185 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 17186 | .cprestore is ignored. */ |
6478892d | 17187 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
17188 | { |
17189 | s_ignore (0); | |
17190 | return; | |
17191 | } | |
17192 | ||
a276b80c MR |
17193 | if (mips_opts.mips16) |
17194 | { | |
17195 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
17196 | ignore_rest_of_line (); | |
17197 | return; | |
17198 | } | |
17199 | ||
252b5132 | 17200 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 17201 | mips_cprestore_valid = 1; |
252b5132 RH |
17202 | |
17203 | ex.X_op = O_constant; | |
17204 | ex.X_add_symbol = NULL; | |
17205 | ex.X_op_symbol = NULL; | |
17206 | ex.X_add_number = mips_cprestore_offset; | |
17207 | ||
8a75745d MR |
17208 | mips_mark_labels (); |
17209 | mips_assembling_insn = TRUE; | |
17210 | ||
584892a6 | 17211 | macro_start (); |
67c0d1eb RS |
17212 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
17213 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 17214 | macro_end (); |
252b5132 | 17215 | |
8a75745d | 17216 | mips_assembling_insn = FALSE; |
252b5132 RH |
17217 | demand_empty_rest_of_line (); |
17218 | } | |
17219 | ||
6478892d | 17220 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 17221 | was given in the preceding .cpsetup, it results in: |
6478892d | 17222 | ld $gp, offset($sp) |
76b3015f | 17223 | |
6478892d | 17224 | If a register $reg2 was given there, it results in: |
40fc1451 | 17225 | or $gp, $reg2, $0 */ |
54f4ddb3 | 17226 | |
6478892d | 17227 | static void |
17a2f251 | 17228 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
17229 | { |
17230 | expressionS ex; | |
6478892d | 17231 | |
919731af | 17232 | file_mips_check_options (); |
17233 | ||
6478892d TS |
17234 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. |
17235 | We also need NewABI support. */ | |
17236 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
17237 | { | |
17238 | s_ignore (0); | |
17239 | return; | |
17240 | } | |
17241 | ||
a276b80c MR |
17242 | if (mips_opts.mips16) |
17243 | { | |
17244 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
17245 | ignore_rest_of_line (); | |
17246 | return; | |
17247 | } | |
17248 | ||
8a75745d MR |
17249 | mips_mark_labels (); |
17250 | mips_assembling_insn = TRUE; | |
17251 | ||
584892a6 | 17252 | macro_start (); |
6478892d TS |
17253 | if (mips_cpreturn_register == -1) |
17254 | { | |
17255 | ex.X_op = O_constant; | |
17256 | ex.X_add_symbol = NULL; | |
17257 | ex.X_op_symbol = NULL; | |
17258 | ex.X_add_number = mips_cpreturn_offset; | |
17259 | ||
67c0d1eb | 17260 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
17261 | } |
17262 | else | |
40fc1451 SD |
17263 | move_register (mips_gp_register, mips_cpreturn_register); |
17264 | ||
584892a6 | 17265 | macro_end (); |
6478892d | 17266 | |
8a75745d | 17267 | mips_assembling_insn = FALSE; |
6478892d TS |
17268 | demand_empty_rest_of_line (); |
17269 | } | |
17270 | ||
d0f13682 CLT |
17271 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
17272 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
17273 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
17274 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
17275 | |
17276 | static void | |
d0f13682 CLT |
17277 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
17278 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
17279 | { |
17280 | expressionS ex; | |
17281 | char *p; | |
17282 | ||
17283 | expression (&ex); | |
17284 | ||
17285 | if (ex.X_op != O_symbol) | |
17286 | { | |
1661c76c | 17287 | as_bad (_("unsupported use of %s"), dirstr); |
741d6ea8 JM |
17288 | ignore_rest_of_line (); |
17289 | } | |
17290 | ||
17291 | p = frag_more (bytes); | |
17292 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 17293 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 17294 | demand_empty_rest_of_line (); |
de64cffd | 17295 | mips_clear_insn_labels (); |
741d6ea8 JM |
17296 | } |
17297 | ||
17298 | /* Handle .dtprelword. */ | |
17299 | ||
17300 | static void | |
17301 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
17302 | { | |
d0f13682 | 17303 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
17304 | } |
17305 | ||
17306 | /* Handle .dtpreldword. */ | |
17307 | ||
17308 | static void | |
17309 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
17310 | { | |
d0f13682 CLT |
17311 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
17312 | } | |
17313 | ||
17314 | /* Handle .tprelword. */ | |
17315 | ||
17316 | static void | |
17317 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
17318 | { | |
17319 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
17320 | } | |
17321 | ||
17322 | /* Handle .tpreldword. */ | |
17323 | ||
17324 | static void | |
17325 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
17326 | { | |
17327 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
17328 | } |
17329 | ||
6478892d TS |
17330 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
17331 | code. It sets the offset to use in gp_rel relocations. */ | |
17332 | ||
17333 | static void | |
17a2f251 | 17334 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
17335 | { |
17336 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
17337 | We also need NewABI support. */ | |
17338 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
17339 | { | |
17340 | s_ignore (0); | |
17341 | return; | |
17342 | } | |
17343 | ||
def2e0dd | 17344 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
17345 | |
17346 | demand_empty_rest_of_line (); | |
17347 | } | |
17348 | ||
252b5132 RH |
17349 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
17350 | code. It generates a 32 bit GP relative reloc. */ | |
17351 | ||
17352 | static void | |
17a2f251 | 17353 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17354 | { |
a8dbcb85 TS |
17355 | segment_info_type *si; |
17356 | struct insn_label_list *l; | |
252b5132 RH |
17357 | expressionS ex; |
17358 | char *p; | |
17359 | ||
17360 | /* When not generating PIC code, this is treated as .word. */ | |
17361 | if (mips_pic != SVR4_PIC) | |
17362 | { | |
17363 | s_cons (2); | |
17364 | return; | |
17365 | } | |
17366 | ||
a8dbcb85 TS |
17367 | si = seg_info (now_seg); |
17368 | l = si->label_list; | |
7d10b47d | 17369 | mips_emit_delays (); |
252b5132 | 17370 | if (auto_align) |
462427c4 | 17371 | mips_align (2, 0, l); |
252b5132 RH |
17372 | |
17373 | expression (&ex); | |
a1facbec | 17374 | mips_clear_insn_labels (); |
252b5132 RH |
17375 | |
17376 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17377 | { | |
1661c76c | 17378 | as_bad (_("unsupported use of .gpword")); |
252b5132 RH |
17379 | ignore_rest_of_line (); |
17380 | } | |
17381 | ||
17382 | p = frag_more (4); | |
17a2f251 | 17383 | md_number_to_chars (p, 0, 4); |
b34976b6 | 17384 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 17385 | BFD_RELOC_GPREL32); |
252b5132 RH |
17386 | |
17387 | demand_empty_rest_of_line (); | |
17388 | } | |
17389 | ||
10181a0d | 17390 | static void |
17a2f251 | 17391 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 17392 | { |
a8dbcb85 TS |
17393 | segment_info_type *si; |
17394 | struct insn_label_list *l; | |
10181a0d AO |
17395 | expressionS ex; |
17396 | char *p; | |
17397 | ||
17398 | /* When not generating PIC code, this is treated as .dword. */ | |
17399 | if (mips_pic != SVR4_PIC) | |
17400 | { | |
17401 | s_cons (3); | |
17402 | return; | |
17403 | } | |
17404 | ||
a8dbcb85 TS |
17405 | si = seg_info (now_seg); |
17406 | l = si->label_list; | |
7d10b47d | 17407 | mips_emit_delays (); |
10181a0d | 17408 | if (auto_align) |
462427c4 | 17409 | mips_align (3, 0, l); |
10181a0d AO |
17410 | |
17411 | expression (&ex); | |
a1facbec | 17412 | mips_clear_insn_labels (); |
10181a0d AO |
17413 | |
17414 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17415 | { | |
1661c76c | 17416 | as_bad (_("unsupported use of .gpdword")); |
10181a0d AO |
17417 | ignore_rest_of_line (); |
17418 | } | |
17419 | ||
17420 | p = frag_more (8); | |
17a2f251 | 17421 | md_number_to_chars (p, 0, 8); |
a105a300 | 17422 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 17423 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
17424 | |
17425 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
17426 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
17427 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
17428 | |
17429 | demand_empty_rest_of_line (); | |
17430 | } | |
17431 | ||
a3f278e2 CM |
17432 | /* Handle the .ehword pseudo-op. This is used when generating unwinding |
17433 | tables. It generates a R_MIPS_EH reloc. */ | |
17434 | ||
17435 | static void | |
17436 | s_ehword (int ignore ATTRIBUTE_UNUSED) | |
17437 | { | |
17438 | expressionS ex; | |
17439 | char *p; | |
17440 | ||
17441 | mips_emit_delays (); | |
17442 | ||
17443 | expression (&ex); | |
17444 | mips_clear_insn_labels (); | |
17445 | ||
17446 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17447 | { | |
1661c76c | 17448 | as_bad (_("unsupported use of .ehword")); |
a3f278e2 CM |
17449 | ignore_rest_of_line (); |
17450 | } | |
17451 | ||
17452 | p = frag_more (4); | |
17453 | md_number_to_chars (p, 0, 4); | |
17454 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, | |
2f0c68f2 | 17455 | BFD_RELOC_32_PCREL); |
a3f278e2 CM |
17456 | |
17457 | demand_empty_rest_of_line (); | |
17458 | } | |
17459 | ||
252b5132 RH |
17460 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
17461 | tables in SVR4 PIC code. */ | |
17462 | ||
17463 | static void | |
17a2f251 | 17464 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17465 | { |
252b5132 RH |
17466 | int reg; |
17467 | ||
919731af | 17468 | file_mips_check_options (); |
17469 | ||
10181a0d AO |
17470 | /* This is ignored when not generating SVR4 PIC code. */ |
17471 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
17472 | { |
17473 | s_ignore (0); | |
17474 | return; | |
17475 | } | |
17476 | ||
8a75745d MR |
17477 | mips_mark_labels (); |
17478 | mips_assembling_insn = TRUE; | |
17479 | ||
252b5132 | 17480 | /* Add $gp to the register named as an argument. */ |
584892a6 | 17481 | macro_start (); |
252b5132 | 17482 | reg = tc_get_register (0); |
67c0d1eb | 17483 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 17484 | macro_end (); |
252b5132 | 17485 | |
8a75745d | 17486 | mips_assembling_insn = FALSE; |
bdaaa2e1 | 17487 | demand_empty_rest_of_line (); |
252b5132 RH |
17488 | } |
17489 | ||
17490 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 17491 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
17492 | such as generating jalx instructions when needed. We also make |
17493 | them odd for the duration of the assembly, in order to generate the | |
17494 | right sort of code. We will make them even in the adjust_symtab | |
17495 | routine, while leaving them marked. This is convenient for the | |
17496 | debugger and the disassembler. The linker knows to make them odd | |
17497 | again. */ | |
17498 | ||
17499 | static void | |
17a2f251 | 17500 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17501 | { |
7bb01e2d MR |
17502 | file_mips_check_options (); |
17503 | file_ase_mips16 |= mips_opts.mips16; | |
17504 | file_ase_micromips |= mips_opts.micromips; | |
17505 | ||
df58fc94 | 17506 | mips_mark_labels (); |
252b5132 RH |
17507 | |
17508 | demand_empty_rest_of_line (); | |
17509 | } | |
17510 | ||
ba92f887 MR |
17511 | /* Handle the .nan pseudo-op. */ |
17512 | ||
17513 | static void | |
17514 | s_nan (int ignore ATTRIBUTE_UNUSED) | |
17515 | { | |
17516 | static const char str_legacy[] = "legacy"; | |
17517 | static const char str_2008[] = "2008"; | |
17518 | size_t i; | |
17519 | ||
17520 | for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++); | |
17521 | ||
17522 | if (i == sizeof (str_2008) - 1 | |
17523 | && memcmp (input_line_pointer, str_2008, i) == 0) | |
7361da2c | 17524 | mips_nan2008 = 1; |
ba92f887 MR |
17525 | else if (i == sizeof (str_legacy) - 1 |
17526 | && memcmp (input_line_pointer, str_legacy, i) == 0) | |
7361da2c AB |
17527 | { |
17528 | if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) | |
17529 | mips_nan2008 = 0; | |
17530 | else | |
17531 | as_bad (_("`%s' does not support legacy NaN"), | |
17532 | mips_cpu_info_from_isa (file_mips_opts.isa)->name); | |
17533 | } | |
ba92f887 | 17534 | else |
1661c76c | 17535 | as_bad (_("bad .nan directive")); |
ba92f887 MR |
17536 | |
17537 | input_line_pointer += i; | |
17538 | demand_empty_rest_of_line (); | |
17539 | } | |
17540 | ||
754e2bb9 RS |
17541 | /* Handle a .stab[snd] directive. Ideally these directives would be |
17542 | implemented in a transparent way, so that removing them would not | |
17543 | have any effect on the generated instructions. However, s_stab | |
17544 | internally changes the section, so in practice we need to decide | |
17545 | now whether the preceding label marks compressed code. We do not | |
17546 | support changing the compression mode of a label after a .stab* | |
17547 | directive, such as in: | |
17548 | ||
17549 | foo: | |
134c0c8b | 17550 | .stabs ... |
754e2bb9 RS |
17551 | .set mips16 |
17552 | ||
17553 | so the current mode wins. */ | |
252b5132 RH |
17554 | |
17555 | static void | |
17a2f251 | 17556 | s_mips_stab (int type) |
252b5132 | 17557 | { |
42c0794e | 17558 | file_mips_check_options (); |
754e2bb9 | 17559 | mips_mark_labels (); |
252b5132 RH |
17560 | s_stab (type); |
17561 | } | |
17562 | ||
54f4ddb3 | 17563 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
17564 | |
17565 | static void | |
17a2f251 | 17566 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17567 | { |
17568 | char *name; | |
17569 | int c; | |
17570 | symbolS *symbolP; | |
17571 | expressionS exp; | |
17572 | ||
d02603dc | 17573 | c = get_symbol_name (&name); |
252b5132 RH |
17574 | symbolP = symbol_find_or_make (name); |
17575 | S_SET_WEAK (symbolP); | |
17576 | *input_line_pointer = c; | |
17577 | ||
d02603dc | 17578 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
17579 | |
17580 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
17581 | { | |
17582 | if (S_IS_DEFINED (symbolP)) | |
17583 | { | |
20203fb9 | 17584 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
17585 | S_GET_NAME (symbolP)); |
17586 | ignore_rest_of_line (); | |
17587 | return; | |
17588 | } | |
bdaaa2e1 | 17589 | |
252b5132 RH |
17590 | if (*input_line_pointer == ',') |
17591 | { | |
17592 | ++input_line_pointer; | |
17593 | SKIP_WHITESPACE (); | |
17594 | } | |
bdaaa2e1 | 17595 | |
252b5132 RH |
17596 | expression (&exp); |
17597 | if (exp.X_op != O_symbol) | |
17598 | { | |
20203fb9 | 17599 | as_bad (_("bad .weakext directive")); |
98d3f06f | 17600 | ignore_rest_of_line (); |
252b5132 RH |
17601 | return; |
17602 | } | |
49309057 | 17603 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
17604 | } |
17605 | ||
17606 | demand_empty_rest_of_line (); | |
17607 | } | |
17608 | ||
17609 | /* Parse a register string into a number. Called from the ECOFF code | |
17610 | to parse .frame. The argument is non-zero if this is the frame | |
17611 | register, so that we can record it in mips_frame_reg. */ | |
17612 | ||
17613 | int | |
17a2f251 | 17614 | tc_get_register (int frame) |
252b5132 | 17615 | { |
707bfff6 | 17616 | unsigned int reg; |
252b5132 RH |
17617 | |
17618 | SKIP_WHITESPACE (); | |
707bfff6 TS |
17619 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
17620 | reg = 0; | |
252b5132 | 17621 | if (frame) |
7a621144 DJ |
17622 | { |
17623 | mips_frame_reg = reg != 0 ? reg : SP; | |
17624 | mips_frame_reg_valid = 1; | |
17625 | mips_cprestore_valid = 0; | |
17626 | } | |
252b5132 RH |
17627 | return reg; |
17628 | } | |
17629 | ||
17630 | valueT | |
17a2f251 | 17631 | md_section_align (asection *seg, valueT addr) |
252b5132 | 17632 | { |
fd361982 | 17633 | int align = bfd_section_alignment (seg); |
252b5132 | 17634 | |
f3ded42a RS |
17635 | /* We don't need to align ELF sections to the full alignment. |
17636 | However, Irix 5 may prefer that we align them at least to a 16 | |
17637 | byte boundary. We don't bother to align the sections if we | |
17638 | are targeted for an embedded system. */ | |
17639 | if (strncmp (TARGET_OS, "elf", 3) == 0) | |
17640 | return addr; | |
17641 | if (align > 4) | |
17642 | align = 4; | |
252b5132 | 17643 | |
8d3842cd | 17644 | return ((addr + (1 << align) - 1) & -(1 << align)); |
252b5132 RH |
17645 | } |
17646 | ||
17647 | /* Utility routine, called from above as well. If called while the | |
17648 | input file is still being read, it's only an approximation. (For | |
17649 | example, a symbol may later become defined which appeared to be | |
17650 | undefined earlier.) */ | |
17651 | ||
17652 | static int | |
17a2f251 | 17653 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17654 | { |
17655 | if (sym == 0) | |
17656 | return 0; | |
17657 | ||
4d0d148d | 17658 | if (g_switch_value > 0) |
252b5132 RH |
17659 | { |
17660 | const char *symname; | |
17661 | int change; | |
17662 | ||
c9914766 | 17663 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17664 | register. It can be if it is smaller than the -G size or if |
17665 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17666 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17667 | they can. */ |
17668 | symname = S_GET_NAME (sym); | |
17669 | if (symname != (const char *) NULL | |
17670 | && (strcmp (symname, "eprol") == 0 | |
17671 | || strcmp (symname, "etext") == 0 | |
17672 | || strcmp (symname, "_gp") == 0 | |
17673 | || strcmp (symname, "edata") == 0 | |
17674 | || strcmp (symname, "_fbss") == 0 | |
17675 | || strcmp (symname, "_fdata") == 0 | |
17676 | || strcmp (symname, "_ftext") == 0 | |
17677 | || strcmp (symname, "end") == 0 | |
17678 | || strcmp (symname, "_gp_disp") == 0)) | |
17679 | change = 1; | |
17680 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17681 | && (0 | |
17682 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17683 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17684 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17685 | <= g_switch_value)) | |
252b5132 RH |
17686 | #endif |
17687 | /* We must defer this decision until after the whole | |
17688 | file has been read, since there might be a .extern | |
17689 | after the first use of this symbol. */ | |
17690 | || (before_relaxing | |
17691 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17692 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17693 | #endif |
17694 | && S_GET_VALUE (sym) == 0) | |
17695 | || (S_GET_VALUE (sym) != 0 | |
17696 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17697 | change = 0; | |
17698 | else | |
17699 | { | |
17700 | const char *segname; | |
17701 | ||
17702 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17703 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17704 | && strcmp (segname, ".lit4") != 0); |
17705 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17706 | && strcmp (segname, ".sbss") != 0 |
17707 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17708 | && strncmp (segname, ".sbss.", 6) != 0 |
17709 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17710 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17711 | } |
17712 | return change; | |
17713 | } | |
17714 | else | |
c9914766 | 17715 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17716 | return 1; |
17717 | } | |
17718 | ||
5919d012 RS |
17719 | |
17720 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17721 | ||
17722 | static bfd_boolean | |
9e009953 | 17723 | pic_need_relax (symbolS *sym) |
5919d012 RS |
17724 | { |
17725 | asection *symsec; | |
5919d012 RS |
17726 | |
17727 | /* Handle the case of a symbol equated to another symbol. */ | |
17728 | while (symbol_equated_reloc_p (sym)) | |
17729 | { | |
17730 | symbolS *n; | |
17731 | ||
5f0fe04b | 17732 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17733 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17734 | if (n == sym) | |
17735 | break; | |
17736 | sym = n; | |
17737 | } | |
17738 | ||
df1f3cda DD |
17739 | if (symbol_section_p (sym)) |
17740 | return TRUE; | |
17741 | ||
5919d012 RS |
17742 | symsec = S_GET_SEGMENT (sym); |
17743 | ||
5919d012 | 17744 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17745 | return (!bfd_is_und_section (symsec) |
17746 | && !bfd_is_abs_section (symsec) | |
5f0fe04b | 17747 | && !bfd_is_com_section (symsec) |
5919d012 | 17748 | /* A global or weak symbol is treated as external. */ |
f3ded42a | 17749 | && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym))); |
5919d012 | 17750 | } |
14f72d45 MR |
17751 | \f |
17752 | /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP | |
17753 | convert a section-relative value VAL to the equivalent PC-relative | |
17754 | value. */ | |
17755 | ||
17756 | static offsetT | |
17757 | mips16_pcrel_val (fragS *fragp, const struct mips_pcrel_operand *pcrel_op, | |
17758 | offsetT val, long stretch) | |
17759 | { | |
17760 | fragS *sym_frag; | |
17761 | addressT addr; | |
17762 | ||
17763 | gas_assert (pcrel_op->root.root.type == OP_PCREL); | |
17764 | ||
17765 | sym_frag = symbol_get_frag (fragp->fr_symbol); | |
17766 | ||
17767 | /* If the relax_marker of the symbol fragment differs from the | |
17768 | relax_marker of this fragment, we have not yet adjusted the | |
17769 | symbol fragment fr_address. We want to add in STRETCH in | |
17770 | order to get a better estimate of the address. This | |
17771 | particularly matters because of the shift bits. */ | |
17772 | if (stretch != 0 && sym_frag->relax_marker != fragp->relax_marker) | |
17773 | { | |
17774 | fragS *f; | |
17775 | ||
17776 | /* Adjust stretch for any alignment frag. Note that if have | |
17777 | been expanding the earlier code, the symbol may be | |
17778 | defined in what appears to be an earlier frag. FIXME: | |
17779 | This doesn't handle the fr_subtype field, which specifies | |
17780 | a maximum number of bytes to skip when doing an | |
17781 | alignment. */ | |
17782 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
17783 | { | |
17784 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17785 | { | |
17786 | if (stretch < 0) | |
17787 | stretch = -(-stretch & ~((1 << (int) f->fr_offset) - 1)); | |
17788 | else | |
17789 | stretch &= ~((1 << (int) f->fr_offset) - 1); | |
17790 | if (stretch == 0) | |
17791 | break; | |
17792 | } | |
17793 | } | |
17794 | if (f != NULL) | |
17795 | val += stretch; | |
17796 | } | |
17797 | ||
17798 | addr = fragp->fr_address + fragp->fr_fix; | |
17799 | ||
17800 | /* The base address rules are complicated. The base address of | |
17801 | a branch is the following instruction. The base address of a | |
17802 | PC relative load or add is the instruction itself, but if it | |
17803 | is in a delay slot (in which case it can not be extended) use | |
17804 | the address of the instruction whose delay slot it is in. */ | |
17805 | if (pcrel_op->include_isa_bit) | |
17806 | { | |
17807 | addr += 2; | |
17808 | ||
17809 | /* If we are currently assuming that this frag should be | |
17810 | extended, then the current address is two bytes higher. */ | |
17811 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17812 | addr += 2; | |
17813 | ||
17814 | /* Ignore the low bit in the target, since it will be set | |
17815 | for a text label. */ | |
17816 | val &= -2; | |
17817 | } | |
17818 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17819 | addr -= 4; | |
17820 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17821 | addr -= 2; | |
5919d012 | 17822 | |
14f72d45 MR |
17823 | val -= addr & -(1 << pcrel_op->align_log2); |
17824 | ||
17825 | return val; | |
17826 | } | |
5919d012 | 17827 | |
252b5132 RH |
17828 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17829 | extended opcode. SEC is the section the frag is in. */ | |
17830 | ||
17831 | static int | |
17a2f251 | 17832 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 | 17833 | { |
3ccad066 | 17834 | const struct mips_int_operand *operand; |
252b5132 | 17835 | offsetT val; |
252b5132 | 17836 | segT symsec; |
14f72d45 | 17837 | int type; |
252b5132 RH |
17838 | |
17839 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17840 | return 0; | |
17841 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17842 | return 1; | |
17843 | ||
88a7ef16 | 17844 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 | 17845 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
3ccad066 | 17846 | operand = mips16_immed_operand (type, FALSE); |
88a7ef16 MR |
17847 | if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) |
17848 | || (operand->root.type == OP_PCREL | |
17849 | ? sec != symsec | |
17850 | : !bfd_is_abs_section (symsec))) | |
17851 | return 1; | |
252b5132 | 17852 | |
88a7ef16 | 17853 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; |
252b5132 | 17854 | |
3ccad066 | 17855 | if (operand->root.type == OP_PCREL) |
252b5132 | 17856 | { |
3ccad066 | 17857 | const struct mips_pcrel_operand *pcrel_op; |
3ccad066 | 17858 | offsetT maxtiny; |
252b5132 | 17859 | |
1425c41d | 17860 | if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp->fr_subtype)) |
88a7ef16 | 17861 | return 1; |
252b5132 | 17862 | |
88a7ef16 | 17863 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
14f72d45 | 17864 | val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); |
252b5132 RH |
17865 | |
17866 | /* If any of the shifted bits are set, we must use an extended | |
17867 | opcode. If the address depends on the size of this | |
17868 | instruction, this can lead to a loop, so we arrange to always | |
88a7ef16 MR |
17869 | use an extended opcode. */ |
17870 | if ((val & ((1 << operand->shift) - 1)) != 0) | |
252b5132 RH |
17871 | { |
17872 | fragp->fr_subtype = | |
1425c41d | 17873 | RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); |
252b5132 RH |
17874 | return 1; |
17875 | } | |
17876 | ||
17877 | /* If we are about to mark a frag as extended because the value | |
3ccad066 RS |
17878 | is precisely the next value above maxtiny, then there is a |
17879 | chance of an infinite loop as in the following code: | |
252b5132 RH |
17880 | la $4,foo |
17881 | .skip 1020 | |
17882 | .align 2 | |
17883 | foo: | |
17884 | In this case when the la is extended, foo is 0x3fc bytes | |
17885 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17886 | the la must be extended. To avoid this loop, we mark the | |
17887 | frag as extended if it was small, and is about to become | |
3ccad066 RS |
17888 | extended with the next value above maxtiny. */ |
17889 | maxtiny = mips_int_operand_max (operand); | |
17890 | if (val == maxtiny + (1 << operand->shift) | |
88a7ef16 | 17891 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
252b5132 RH |
17892 | { |
17893 | fragp->fr_subtype = | |
1425c41d | 17894 | RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); |
252b5132 RH |
17895 | return 1; |
17896 | } | |
17897 | } | |
252b5132 | 17898 | |
3ccad066 | 17899 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); |
252b5132 RH |
17900 | } |
17901 | ||
8507b6e7 MR |
17902 | /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs |
17903 | macro expansion. SEC is the section the frag is in. We only | |
17904 | support PC-relative instructions (LA, DLA, LW, LD) here, in | |
17905 | non-PIC code using 32-bit addressing. */ | |
17906 | ||
17907 | static int | |
17908 | mips16_macro_frag (fragS *fragp, asection *sec, long stretch) | |
17909 | { | |
17910 | const struct mips_pcrel_operand *pcrel_op; | |
17911 | const struct mips_int_operand *operand; | |
17912 | offsetT val; | |
17913 | segT symsec; | |
17914 | int type; | |
17915 | ||
17916 | gas_assert (!RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)); | |
17917 | ||
17918 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17919 | return 0; | |
17920 | if (!RELAX_MIPS16_SYM32 (fragp->fr_subtype)) | |
17921 | return 0; | |
17922 | ||
17923 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17924 | switch (type) | |
17925 | { | |
17926 | case 'A': | |
17927 | case 'B': | |
17928 | case 'E': | |
17929 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
17930 | if (bfd_is_abs_section (symsec)) | |
17931 | return 1; | |
17932 | if (RELAX_MIPS16_PIC (fragp->fr_subtype)) | |
17933 | return 0; | |
17934 | if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) || sec != symsec) | |
17935 | return 1; | |
17936 | ||
17937 | operand = mips16_immed_operand (type, TRUE); | |
17938 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17939 | pcrel_op = (const struct mips_pcrel_operand *) operand; | |
17940 | val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); | |
17941 | ||
17942 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); | |
17943 | ||
17944 | default: | |
17945 | return 0; | |
17946 | } | |
17947 | } | |
17948 | ||
4a6a3df4 AO |
17949 | /* Compute the length of a branch sequence, and adjust the |
17950 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17951 | worst-case length is computed, with UPDATE being used to indicate | |
17952 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17953 | branch is to be computed. */ | |
17954 | static int | |
17a2f251 | 17955 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17956 | { |
b34976b6 | 17957 | bfd_boolean toofar; |
4a6a3df4 AO |
17958 | int length; |
17959 | ||
17960 | if (fragp | |
17961 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17962 | && !S_IS_WEAK (fragp->fr_symbol) |
4a6a3df4 AO |
17963 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17964 | { | |
17965 | addressT addr; | |
17966 | offsetT val; | |
17967 | ||
17968 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17969 | ||
17970 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17971 | ||
17972 | val -= addr; | |
17973 | ||
17974 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17975 | } | |
4a6a3df4 | 17976 | else |
c1f61bd2 MR |
17977 | /* If the symbol is not defined or it's in a different segment, |
17978 | we emit the long sequence. */ | |
b34976b6 | 17979 | toofar = TRUE; |
4a6a3df4 AO |
17980 | |
17981 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17982 | fragp->fr_subtype | |
66b3e8da | 17983 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
ce8ad872 | 17984 | RELAX_BRANCH_PIC (fragp->fr_subtype), |
66b3e8da | 17985 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
17986 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17987 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17988 | toofar); | |
17989 | ||
17990 | length = 4; | |
17991 | if (toofar) | |
17992 | { | |
17993 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17994 | length += 8; | |
17995 | ||
ce8ad872 | 17996 | if (!fragp || RELAX_BRANCH_PIC (fragp->fr_subtype)) |
4a6a3df4 AO |
17997 | { |
17998 | /* Additional space for PIC loading of target address. */ | |
17999 | length += 8; | |
18000 | if (mips_opts.isa == ISA_MIPS1) | |
18001 | /* Additional space for $at-stabilizing nop. */ | |
18002 | length += 4; | |
18003 | } | |
18004 | ||
18005 | /* If branch is conditional. */ | |
18006 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
18007 | length += 8; | |
18008 | } | |
b34976b6 | 18009 | |
4a6a3df4 AO |
18010 | return length; |
18011 | } | |
18012 | ||
7bd374a4 MR |
18013 | /* Get a FRAG's branch instruction delay slot size, either from the |
18014 | short-delay-slot bit of a branch-and-link instruction if AL is TRUE, | |
18015 | or SHORT_INSN_SIZE otherwise. */ | |
18016 | ||
18017 | static int | |
18018 | frag_branch_delay_slot_size (fragS *fragp, bfd_boolean al, int short_insn_size) | |
18019 | { | |
18020 | char *buf = fragp->fr_literal + fragp->fr_fix; | |
18021 | ||
18022 | if (al) | |
18023 | return (read_compressed_insn (buf, 4) & 0x02000000) ? 2 : 4; | |
18024 | else | |
18025 | return short_insn_size; | |
18026 | } | |
18027 | ||
df58fc94 RS |
18028 | /* Compute the length of a branch sequence, and adjust the |
18029 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
18030 | worst-case length is computed, with UPDATE being used to indicate | |
18031 | whether an unconditional (-1), or regular (0) branch is to be | |
18032 | computed. */ | |
18033 | ||
18034 | static int | |
18035 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
18036 | { | |
7bd374a4 MR |
18037 | bfd_boolean insn32 = TRUE; |
18038 | bfd_boolean nods = TRUE; | |
ce8ad872 | 18039 | bfd_boolean pic = TRUE; |
7bd374a4 MR |
18040 | bfd_boolean al = TRUE; |
18041 | int short_insn_size; | |
df58fc94 RS |
18042 | bfd_boolean toofar; |
18043 | int length; | |
18044 | ||
7bd374a4 MR |
18045 | if (fragp) |
18046 | { | |
18047 | insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); | |
18048 | nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); | |
ce8ad872 | 18049 | pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); |
7bd374a4 MR |
18050 | al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); |
18051 | } | |
18052 | short_insn_size = insn32 ? 4 : 2; | |
18053 | ||
df58fc94 RS |
18054 | if (fragp |
18055 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 18056 | && !S_IS_WEAK (fragp->fr_symbol) |
df58fc94 RS |
18057 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
18058 | { | |
18059 | addressT addr; | |
18060 | offsetT val; | |
18061 | ||
18062 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
18063 | /* Ignore the low bit in the target, since it will be set | |
18064 | for a text label. */ | |
18065 | if ((val & 1) != 0) | |
18066 | --val; | |
18067 | ||
18068 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
18069 | ||
18070 | val -= addr; | |
18071 | ||
18072 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
18073 | } | |
df58fc94 | 18074 | else |
c1f61bd2 MR |
18075 | /* If the symbol is not defined or it's in a different segment, |
18076 | we emit the long sequence. */ | |
df58fc94 RS |
18077 | toofar = TRUE; |
18078 | ||
18079 | if (fragp && update | |
18080 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18081 | fragp->fr_subtype = (toofar | |
18082 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
18083 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
18084 | ||
18085 | length = 4; | |
18086 | if (toofar) | |
18087 | { | |
18088 | bfd_boolean compact_known = fragp != NULL; | |
18089 | bfd_boolean compact = FALSE; | |
18090 | bfd_boolean uncond; | |
18091 | ||
df58fc94 | 18092 | if (fragp) |
8484fb75 MR |
18093 | { |
18094 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
18095 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
8484fb75 | 18096 | } |
df58fc94 RS |
18097 | else |
18098 | uncond = update < 0; | |
18099 | ||
18100 | /* If label is out of range, we turn branch <br>: | |
18101 | ||
18102 | <br> label # 4 bytes | |
18103 | 0: | |
18104 | ||
18105 | into: | |
18106 | ||
18107 | j label # 4 bytes | |
8484fb75 MR |
18108 | nop # 2/4 bytes if |
18109 | # compact && (!PIC || insn32) | |
df58fc94 RS |
18110 | 0: |
18111 | */ | |
ce8ad872 | 18112 | if ((!pic || insn32) && (!compact_known || compact)) |
8484fb75 | 18113 | length += short_insn_size; |
df58fc94 RS |
18114 | |
18115 | /* If assembling PIC code, we further turn: | |
18116 | ||
18117 | j label # 4 bytes | |
18118 | ||
18119 | into: | |
18120 | ||
18121 | lw/ld at, %got(label)(gp) # 4 bytes | |
18122 | d/addiu at, %lo(label) # 4 bytes | |
8484fb75 | 18123 | jr/c at # 2/4 bytes |
df58fc94 | 18124 | */ |
ce8ad872 | 18125 | if (pic) |
8484fb75 | 18126 | length += 4 + short_insn_size; |
df58fc94 | 18127 | |
7bd374a4 MR |
18128 | /* Add an extra nop if the jump has no compact form and we need |
18129 | to fill the delay slot. */ | |
ce8ad872 | 18130 | if ((!pic || al) && nods) |
7bd374a4 MR |
18131 | length += (fragp |
18132 | ? frag_branch_delay_slot_size (fragp, al, short_insn_size) | |
18133 | : short_insn_size); | |
18134 | ||
df58fc94 RS |
18135 | /* If branch <br> is conditional, we prepend negated branch <brneg>: |
18136 | ||
18137 | <brneg> 0f # 4 bytes | |
8484fb75 | 18138 | nop # 2/4 bytes if !compact |
df58fc94 RS |
18139 | */ |
18140 | if (!uncond) | |
8484fb75 | 18141 | length += (compact_known && compact) ? 4 : 4 + short_insn_size; |
df58fc94 | 18142 | } |
7bd374a4 MR |
18143 | else if (nods) |
18144 | { | |
18145 | /* Add an extra nop to fill the delay slot. */ | |
18146 | gas_assert (fragp); | |
18147 | length += frag_branch_delay_slot_size (fragp, al, short_insn_size); | |
18148 | } | |
df58fc94 RS |
18149 | |
18150 | return length; | |
18151 | } | |
18152 | ||
18153 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
18154 | bit accordingly. */ | |
18155 | ||
18156 | static int | |
18157 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
18158 | { | |
18159 | bfd_boolean toofar; | |
18160 | ||
df58fc94 RS |
18161 | if (fragp |
18162 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 18163 | && !S_IS_WEAK (fragp->fr_symbol) |
df58fc94 RS |
18164 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
18165 | { | |
18166 | addressT addr; | |
18167 | offsetT val; | |
18168 | int type; | |
18169 | ||
18170 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
18171 | /* Ignore the low bit in the target, since it will be set | |
18172 | for a text label. */ | |
18173 | if ((val & 1) != 0) | |
18174 | --val; | |
18175 | ||
18176 | /* Assume this is a 2-byte branch. */ | |
18177 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
18178 | ||
18179 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
18180 | long branches. */ | |
18181 | ||
18182 | val -= addr; | |
18183 | ||
18184 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
18185 | if (type == 'D') | |
18186 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
18187 | else if (type == 'E') | |
18188 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
18189 | else | |
18190 | abort (); | |
18191 | } | |
18192 | else | |
18193 | /* If the symbol is not defined or it's in a different segment, | |
18194 | we emit a normal 32-bit branch. */ | |
18195 | toofar = TRUE; | |
18196 | ||
18197 | if (fragp && update | |
18198 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18199 | fragp->fr_subtype | |
18200 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
18201 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
18202 | ||
18203 | if (toofar) | |
18204 | return 4; | |
18205 | ||
18206 | return 2; | |
18207 | } | |
18208 | ||
252b5132 RH |
18209 | /* Estimate the size of a frag before relaxing. Unless this is the |
18210 | mips16, we are not really relaxing here, and the final size is | |
18211 | encoded in the subtype information. For the mips16, we have to | |
18212 | decide whether we are using an extended opcode or not. */ | |
18213 | ||
252b5132 | 18214 | int |
17a2f251 | 18215 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 18216 | { |
5919d012 | 18217 | int change; |
252b5132 | 18218 | |
4a6a3df4 AO |
18219 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18220 | { | |
18221 | ||
b34976b6 AM |
18222 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
18223 | ||
4a6a3df4 AO |
18224 | return fragp->fr_var; |
18225 | } | |
18226 | ||
252b5132 | 18227 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
8507b6e7 MR |
18228 | { |
18229 | /* We don't want to modify the EXTENDED bit here; it might get us | |
18230 | into infinite loops. We change it only in mips_relax_frag(). */ | |
18231 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) | |
25499ac7 | 18232 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 8 : 12; |
8507b6e7 MR |
18233 | else |
18234 | return RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2; | |
18235 | } | |
252b5132 | 18236 | |
df58fc94 RS |
18237 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18238 | { | |
18239 | int length = 4; | |
18240 | ||
18241 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18242 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
18243 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18244 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
18245 | fragp->fr_var = length; | |
18246 | ||
18247 | return length; | |
18248 | } | |
18249 | ||
ce8ad872 | 18250 | if (mips_pic == VXWORKS_PIC) |
0a44bf69 RS |
18251 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ |
18252 | change = 0; | |
ce8ad872 MR |
18253 | else if (RELAX_PIC (fragp->fr_subtype)) |
18254 | change = pic_need_relax (fragp->fr_symbol); | |
252b5132 | 18255 | else |
ce8ad872 | 18256 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 RH |
18257 | |
18258 | if (change) | |
18259 | { | |
4d7206a2 | 18260 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 18261 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 18262 | } |
4d7206a2 RS |
18263 | else |
18264 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
18265 | } |
18266 | ||
18267 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 18268 | should be converted into a reloc against a section. */ |
252b5132 RH |
18269 | |
18270 | int | |
17a2f251 | 18271 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 18272 | { |
252b5132 RH |
18273 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
18274 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
18275 | return 0; | |
a161fe53 | 18276 | |
252b5132 RH |
18277 | if (fixp->fx_addsy == NULL) |
18278 | return 1; | |
a161fe53 | 18279 | |
2f0c68f2 CM |
18280 | /* Allow relocs used for EH tables. */ |
18281 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) | |
18282 | return 1; | |
18283 | ||
de7e6852 RS |
18284 | /* If symbol SYM is in a mergeable section, relocations of the form |
18285 | SYM + 0 can usually be made section-relative. The mergeable data | |
18286 | is then identified by the section offset rather than by the symbol. | |
18287 | ||
18288 | However, if we're generating REL LO16 relocations, the offset is split | |
33eaf5de | 18289 | between the LO16 and partnering high part relocation. The linker will |
de7e6852 RS |
18290 | need to recalculate the complete offset in order to correctly identify |
18291 | the merge data. | |
18292 | ||
33eaf5de | 18293 | The linker has traditionally not looked for the partnering high part |
de7e6852 RS |
18294 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be |
18295 | placed anywhere. Rather than break backwards compatibility by changing | |
18296 | this, it seems better not to force the issue, and instead keep the | |
18297 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 18298 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 18299 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
18300 | && HAVE_IN_PLACE_ADDENDS |
18301 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
18302 | return 0; | |
18303 | ||
97f50151 MR |
18304 | /* There is no place to store an in-place offset for JALR relocations. */ |
18305 | if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS) | |
18306 | return 0; | |
18307 | ||
18308 | /* Likewise an in-range offset of limited PC-relative relocations may | |
2de39019 | 18309 | overflow the in-place relocatable field if recalculated against the |
7361da2c AB |
18310 | start address of the symbol's containing section. |
18311 | ||
18312 | Also, PC relative relocations for MIPS R6 need to be symbol rather than | |
18313 | section relative to allow linker relaxations to be performed later on. */ | |
97f50151 | 18314 | if (limited_pcrel_reloc_p (fixp->fx_r_type) |
912815f0 | 18315 | && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa))) |
1180b5a4 RS |
18316 | return 0; |
18317 | ||
b314ec0e RS |
18318 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
18319 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
18320 | relocations against MIPS16 functions; in this case, the stub becomes | |
18321 | the function's canonical address. | |
18322 | ||
18323 | Floating-point stubs are stored in unique .mips16.call.* or | |
18324 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
18325 | the first relocation in section S must be against F; this is how the | |
18326 | linker determines the target function. All relocations that might | |
18327 | resolve to T must also be against F. We therefore have the following | |
18328 | restrictions, which are given in an intentionally-redundant way: | |
18329 | ||
18330 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
18331 | symbols. | |
18332 | ||
18333 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
18334 | if that stub might be used. | |
18335 | ||
18336 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
18337 | symbols. | |
18338 | ||
18339 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
18340 | that stub might be used. | |
18341 | ||
18342 | There is a further restriction: | |
18343 | ||
df58fc94 | 18344 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
0e9c5a5c | 18345 | R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2, |
c9775dde MR |
18346 | R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1, |
18347 | R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1) | |
18348 | against MIPS16 or microMIPS symbols because we need to keep the | |
18349 | MIPS16 or microMIPS symbol for the purpose of mode mismatch | |
a6ebf616 MR |
18350 | detection and JAL or BAL to JALX instruction conversion in the |
18351 | linker. | |
b314ec0e | 18352 | |
df58fc94 | 18353 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
507dcb32 | 18354 | against a MIPS16 symbol. We deal with (5) by additionally leaving |
0e9c5a5c | 18355 | alone any jump and branch relocations against a microMIPS symbol. |
b314ec0e RS |
18356 | |
18357 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
18358 | relocation against some symbol R, no relocation against R may be | |
18359 | reduced. (Note that this deals with (2) as well as (1) because | |
18360 | relocations against global symbols will never be reduced on ELF | |
18361 | targets.) This approach is a little simpler than trying to detect | |
18362 | stub sections, and gives the "all or nothing" per-symbol consistency | |
18363 | that we have for MIPS16 symbols. */ | |
f3ded42a | 18364 | if (fixp->fx_subsy == NULL |
30c09090 | 18365 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
44d3da23 | 18366 | || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) |
0e9c5a5c MR |
18367 | && (jmp_reloc_p (fixp->fx_r_type) |
18368 | || b_reloc_p (fixp->fx_r_type))) | |
44d3da23 | 18369 | || *symbol_get_tc (fixp->fx_addsy))) |
252b5132 | 18370 | return 0; |
a161fe53 | 18371 | |
252b5132 RH |
18372 | return 1; |
18373 | } | |
18374 | ||
18375 | /* Translate internal representation of relocation info to BFD target | |
18376 | format. */ | |
18377 | ||
18378 | arelent ** | |
17a2f251 | 18379 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
18380 | { |
18381 | static arelent *retval[4]; | |
18382 | arelent *reloc; | |
18383 | bfd_reloc_code_real_type code; | |
18384 | ||
4b0cff4e | 18385 | memset (retval, 0, sizeof(retval)); |
325801bd TS |
18386 | reloc = retval[0] = XCNEW (arelent); |
18387 | reloc->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 18388 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
18389 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
18390 | ||
bad36eac DJ |
18391 | if (fixp->fx_pcrel) |
18392 | { | |
df58fc94 | 18393 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
c9775dde | 18394 | || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1 |
df58fc94 RS |
18395 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 |
18396 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 | 18397 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
7361da2c AB |
18398 | || fixp->fx_r_type == BFD_RELOC_32_PCREL |
18399 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 | |
18400 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 | |
18401 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 | |
18402 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 | |
18403 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL | |
18404 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL); | |
bad36eac DJ |
18405 | |
18406 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
18407 | Relocations want only the symbol offset. */ | |
51f6035b MR |
18408 | switch (fixp->fx_r_type) |
18409 | { | |
18410 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
18411 | reloc->addend = fixp->fx_addnumber + (reloc->address & ~7); | |
18412 | break; | |
18413 | default: | |
18414 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
18415 | break; | |
18416 | } | |
bad36eac | 18417 | } |
17c6c9d9 MR |
18418 | else if (HAVE_IN_PLACE_ADDENDS |
18419 | && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
18420 | && (read_compressed_insn (fixp->fx_frag->fr_literal | |
18421 | + fixp->fx_where, 4) >> 26) == 0x3c) | |
18422 | { | |
18423 | /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place | |
18424 | addend accordingly. */ | |
18425 | reloc->addend = fixp->fx_addnumber >> 1; | |
18426 | } | |
bad36eac DJ |
18427 | else |
18428 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 18429 | |
438c16b8 TS |
18430 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
18431 | entry to be used in the relocation's section offset. */ | |
18432 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
18433 | { |
18434 | reloc->address = reloc->addend; | |
18435 | reloc->addend = 0; | |
18436 | } | |
18437 | ||
252b5132 | 18438 | code = fixp->fx_r_type; |
252b5132 | 18439 | |
bad36eac | 18440 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
18441 | if (reloc->howto == NULL) |
18442 | { | |
18443 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1661c76c RS |
18444 | _("cannot represent %s relocation in this object file" |
18445 | " format"), | |
252b5132 RH |
18446 | bfd_get_reloc_code_name (code)); |
18447 | retval[0] = NULL; | |
18448 | } | |
18449 | ||
18450 | return retval; | |
18451 | } | |
18452 | ||
18453 | /* Relax a machine dependent frag. This returns the amount by which | |
18454 | the current size of the frag should change. */ | |
18455 | ||
18456 | int | |
17a2f251 | 18457 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 18458 | { |
4a6a3df4 AO |
18459 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18460 | { | |
18461 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
18462 | |
18463 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
18464 | |
18465 | return fragp->fr_var - old_var; | |
18466 | } | |
18467 | ||
df58fc94 RS |
18468 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18469 | { | |
18470 | offsetT old_var = fragp->fr_var; | |
18471 | offsetT new_var = 4; | |
18472 | ||
18473 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18474 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
18475 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18476 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
18477 | fragp->fr_var = new_var; | |
18478 | ||
18479 | return new_var - old_var; | |
18480 | } | |
18481 | ||
252b5132 RH |
18482 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
18483 | return 0; | |
18484 | ||
8507b6e7 | 18485 | if (!mips16_extended_frag (fragp, sec, stretch)) |
252b5132 | 18486 | { |
8507b6e7 MR |
18487 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
18488 | { | |
18489 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); | |
25499ac7 | 18490 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -6 : -10; |
8507b6e7 MR |
18491 | } |
18492 | else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18493 | { | |
18494 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18495 | return -2; | |
18496 | } | |
18497 | else | |
18498 | return 0; | |
18499 | } | |
18500 | else if (!mips16_macro_frag (fragp, sec, stretch)) | |
18501 | { | |
18502 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) | |
18503 | { | |
18504 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); | |
18505 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
25499ac7 | 18506 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -4 : -8; |
8507b6e7 MR |
18507 | } |
18508 | else if (!RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18509 | { | |
18510 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
18511 | return 2; | |
18512 | } | |
18513 | else | |
252b5132 | 18514 | return 0; |
252b5132 RH |
18515 | } |
18516 | else | |
18517 | { | |
8507b6e7 | 18518 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
252b5132 | 18519 | return 0; |
8507b6e7 MR |
18520 | else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
18521 | { | |
18522 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18523 | fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); | |
25499ac7 | 18524 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 4 : 8; |
8507b6e7 MR |
18525 | } |
18526 | else | |
18527 | { | |
18528 | fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); | |
25499ac7 | 18529 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 6 : 10; |
8507b6e7 | 18530 | } |
252b5132 RH |
18531 | } |
18532 | ||
18533 | return 0; | |
18534 | } | |
18535 | ||
18536 | /* Convert a machine dependent frag. */ | |
18537 | ||
18538 | void | |
17a2f251 | 18539 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 18540 | { |
4a6a3df4 AO |
18541 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18542 | { | |
4d68580a | 18543 | char *buf; |
4a6a3df4 | 18544 | unsigned long insn; |
4a6a3df4 | 18545 | fixS *fixp; |
b34976b6 | 18546 | |
4d68580a RS |
18547 | buf = fragp->fr_literal + fragp->fr_fix; |
18548 | insn = read_insn (buf); | |
b34976b6 | 18549 | |
4a6a3df4 AO |
18550 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
18551 | { | |
18552 | /* We generate a fixup instead of applying it right now | |
18553 | because, if there are linker relaxations, we're going to | |
18554 | need the relocations. */ | |
bbd27b76 MR |
18555 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18556 | fragp->fr_symbol, fragp->fr_offset, | |
18557 | TRUE, BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
18558 | fixp->fx_file = fragp->fr_file; |
18559 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18560 | |
4d68580a | 18561 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18562 | } |
18563 | else | |
18564 | { | |
18565 | int i; | |
18566 | ||
18567 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 18568 | _("relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
18569 | |
18570 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
18571 | goto uncond; | |
18572 | ||
18573 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18574 | { | |
18575 | /* Reverse the branch. */ | |
18576 | switch ((insn >> 28) & 0xf) | |
18577 | { | |
18578 | case 4: | |
56d438b1 CF |
18579 | if ((insn & 0xff000000) == 0x47000000 |
18580 | || (insn & 0xff600000) == 0x45600000) | |
18581 | { | |
18582 | /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition | |
18583 | reversed by tweaking bit 23. */ | |
18584 | insn ^= 0x00800000; | |
18585 | } | |
18586 | else | |
18587 | { | |
18588 | /* bc[0-3][tf]l? instructions can have the condition | |
18589 | reversed by tweaking a single TF bit, and their | |
18590 | opcodes all have 0x4???????. */ | |
18591 | gas_assert ((insn & 0xf3e00000) == 0x41000000); | |
18592 | insn ^= 0x00010000; | |
18593 | } | |
4a6a3df4 AO |
18594 | break; |
18595 | ||
18596 | case 0: | |
18597 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 18598 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 18599 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
18600 | insn ^= 0x00010000; |
18601 | break; | |
b34976b6 | 18602 | |
4a6a3df4 AO |
18603 | case 1: |
18604 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 18605 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
18606 | insn ^= 0x04000000; |
18607 | break; | |
18608 | ||
18609 | default: | |
18610 | abort (); | |
18611 | } | |
18612 | } | |
18613 | ||
18614 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
18615 | { | |
18616 | /* Clear the and-link bit. */ | |
9c2799c2 | 18617 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 18618 | |
54f4ddb3 TS |
18619 | /* bltzal 0x04100000 bgezal 0x04110000 |
18620 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
18621 | insn &= ~0x00100000; |
18622 | } | |
18623 | ||
18624 | /* Branch over the branch (if the branch was likely) or the | |
18625 | full jump (not likely case). Compute the offset from the | |
18626 | current instruction to branch to. */ | |
18627 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18628 | i = 16; | |
18629 | else | |
18630 | { | |
18631 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18632 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18633 | /* How many bytes in instructions from here to the end? */ |
18634 | i = fragp->fr_var - i; | |
18635 | } | |
18636 | /* Convert to instruction count. */ | |
18637 | i >>= 2; | |
18638 | /* Branch counts from the next instruction. */ | |
b34976b6 | 18639 | i--; |
4a6a3df4 AO |
18640 | insn |= i; |
18641 | /* Branch over the jump. */ | |
4d68580a | 18642 | buf = write_insn (buf, insn); |
4a6a3df4 | 18643 | |
54f4ddb3 | 18644 | /* nop */ |
4d68580a | 18645 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
18646 | |
18647 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18648 | { | |
18649 | /* beql $0, $0, 2f */ | |
18650 | insn = 0x50000000; | |
18651 | /* Compute the PC offset from the current instruction to | |
18652 | the end of the variable frag. */ | |
18653 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18654 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18655 | /* How many bytes in instructions from here to the end? */ |
18656 | i = fragp->fr_var - i; | |
18657 | /* Convert to instruction count. */ | |
18658 | i >>= 2; | |
18659 | /* Don't decrement i, because we want to branch over the | |
18660 | delay slot. */ | |
4a6a3df4 | 18661 | insn |= i; |
4a6a3df4 | 18662 | |
4d68580a RS |
18663 | buf = write_insn (buf, insn); |
18664 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18665 | } |
18666 | ||
18667 | uncond: | |
ce8ad872 | 18668 | if (!RELAX_BRANCH_PIC (fragp->fr_subtype)) |
4a6a3df4 AO |
18669 | { |
18670 | /* j or jal. */ | |
18671 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
18672 | ? 0x0c000000 : 0x08000000); | |
4a6a3df4 | 18673 | |
bbd27b76 MR |
18674 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18675 | fragp->fr_symbol, fragp->fr_offset, | |
18676 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
18677 | fixp->fx_file = fragp->fr_file; |
18678 | fixp->fx_line = fragp->fr_line; | |
18679 | ||
4d68580a | 18680 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18681 | } |
18682 | else | |
18683 | { | |
66b3e8da MR |
18684 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
18685 | ||
4a6a3df4 | 18686 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
18687 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
18688 | insn |= at << OP_SH_RT; | |
4a6a3df4 | 18689 | |
bbd27b76 MR |
18690 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18691 | fragp->fr_symbol, fragp->fr_offset, | |
18692 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
18693 | fixp->fx_file = fragp->fr_file; |
18694 | fixp->fx_line = fragp->fr_line; | |
18695 | ||
4d68580a | 18696 | buf = write_insn (buf, insn); |
b34976b6 | 18697 | |
4a6a3df4 | 18698 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
18699 | /* nop */ |
18700 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18701 | |
18702 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
18703 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
18704 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 18705 | |
bbd27b76 MR |
18706 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18707 | fragp->fr_symbol, fragp->fr_offset, | |
18708 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
18709 | fixp->fx_file = fragp->fr_file; |
18710 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18711 | |
4d68580a | 18712 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18713 | |
18714 | /* j(al)r $at. */ | |
18715 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 18716 | insn = 0x0000f809; |
4a6a3df4 | 18717 | else |
66b3e8da MR |
18718 | insn = 0x00000008; |
18719 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 18720 | |
4d68580a | 18721 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18722 | } |
18723 | } | |
18724 | ||
4a6a3df4 | 18725 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 18726 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
18727 | return; |
18728 | } | |
18729 | ||
df58fc94 RS |
18730 | /* Relax microMIPS branches. */ |
18731 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
18732 | { | |
4d68580a | 18733 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 | 18734 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
8484fb75 | 18735 | bfd_boolean insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); |
7bd374a4 | 18736 | bfd_boolean nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); |
ce8ad872 | 18737 | bfd_boolean pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); |
df58fc94 RS |
18738 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); |
18739 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18740 | bfd_boolean short_ds; |
df58fc94 | 18741 | unsigned long insn; |
df58fc94 RS |
18742 | fixS *fixp; |
18743 | ||
df58fc94 RS |
18744 | fragp->fr_fix += fragp->fr_var; |
18745 | ||
18746 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18747 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18748 | { | |
18749 | /* We generate a fixup instead of applying it right now, | |
18750 | because if there is linker relaxation, we're going to | |
18751 | need the relocations. */ | |
834a65aa MR |
18752 | switch (type) |
18753 | { | |
18754 | case 'D': | |
18755 | fixp = fix_new (fragp, buf - fragp->fr_literal, 2, | |
18756 | fragp->fr_symbol, fragp->fr_offset, | |
18757 | TRUE, BFD_RELOC_MICROMIPS_10_PCREL_S1); | |
18758 | break; | |
18759 | case 'E': | |
18760 | fixp = fix_new (fragp, buf - fragp->fr_literal, 2, | |
18761 | fragp->fr_symbol, fragp->fr_offset, | |
18762 | TRUE, BFD_RELOC_MICROMIPS_7_PCREL_S1); | |
18763 | break; | |
18764 | default: | |
18765 | abort (); | |
18766 | } | |
df58fc94 RS |
18767 | |
18768 | fixp->fx_file = fragp->fr_file; | |
18769 | fixp->fx_line = fragp->fr_line; | |
18770 | ||
18771 | /* These relocations can have an addend that won't fit in | |
18772 | 2 octets. */ | |
18773 | fixp->fx_no_overflow = 1; | |
18774 | ||
18775 | return; | |
18776 | } | |
18777 | ||
2309ddf2 | 18778 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18779 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18780 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18781 | { | |
18782 | /* We generate a fixup instead of applying it right now, | |
18783 | because if there is linker relaxation, we're going to | |
18784 | need the relocations. */ | |
bbd27b76 MR |
18785 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18786 | fragp->fr_symbol, fragp->fr_offset, | |
18787 | TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18788 | fixp->fx_file = fragp->fr_file; |
18789 | fixp->fx_line = fragp->fr_line; | |
18790 | ||
18791 | if (type == 0) | |
7bd374a4 MR |
18792 | { |
18793 | insn = read_compressed_insn (buf, 4); | |
18794 | buf += 4; | |
18795 | ||
18796 | if (nods) | |
18797 | { | |
18798 | /* Check the short-delay-slot bit. */ | |
18799 | if (!al || (insn & 0x02000000) != 0) | |
18800 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18801 | else | |
18802 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18803 | } | |
18804 | ||
18805 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
18806 | return; | |
18807 | } | |
df58fc94 RS |
18808 | } |
18809 | ||
18810 | /* Relax 16-bit branches to 32-bit branches. */ | |
18811 | if (type != 0) | |
18812 | { | |
4d68580a | 18813 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18814 | |
18815 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18816 | insn = 0x94000000; /* beq */ | |
18817 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18818 | { | |
18819 | unsigned long regno; | |
18820 | ||
18821 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18822 | regno = micromips_to_32_reg_d_map [regno]; | |
18823 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18824 | insn |= regno << MICROMIPSOP_SH_RS; | |
18825 | } | |
18826 | else | |
18827 | abort (); | |
18828 | ||
18829 | /* Nothing else to do, just write it out. */ | |
18830 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18831 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18832 | { | |
4d68580a | 18833 | buf = write_compressed_insn (buf, insn, 4); |
7bd374a4 MR |
18834 | if (nods) |
18835 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
4d68580a | 18836 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18837 | return; |
18838 | } | |
18839 | } | |
18840 | else | |
4d68580a | 18841 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18842 | |
18843 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18844 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 18845 | _("relaxed out-of-range branch into a jump")); |
df58fc94 | 18846 | |
2309ddf2 | 18847 | /* Set the short-delay-slot bit. */ |
7bd374a4 | 18848 | short_ds = !al || (insn & 0x02000000) != 0; |
df58fc94 RS |
18849 | |
18850 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18851 | { | |
18852 | symbolS *l; | |
18853 | ||
18854 | /* Reverse the branch. */ | |
18855 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18856 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18857 | insn ^= 0x20000000; | |
18858 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18859 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18860 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18861 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18862 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18863 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18864 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18865 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18866 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18867 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18868 | insn ^= 0x00400000; | |
18869 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18870 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18871 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18872 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18873 | insn ^= 0x00200000; | |
56d438b1 CF |
18874 | else if ((insn & 0xff000000) == 0x83000000 /* BZ.df |
18875 | BNZ.df */ | |
18876 | || (insn & 0xff600000) == 0x81600000) /* BZ.V | |
18877 | BNZ.V */ | |
18878 | insn ^= 0x00800000; | |
df58fc94 RS |
18879 | else |
18880 | abort (); | |
18881 | ||
18882 | if (al) | |
18883 | { | |
18884 | /* Clear the and-link and short-delay-slot bits. */ | |
18885 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18886 | ||
18887 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18888 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18889 | insn &= ~0x02200000; | |
18890 | } | |
18891 | ||
18892 | /* Make a label at the end for use with the branch. */ | |
18893 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18894 | micromips_label_inc (); | |
f3ded42a | 18895 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); |
df58fc94 RS |
18896 | |
18897 | /* Refer to it. */ | |
4d68580a RS |
18898 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18899 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18900 | fixp->fx_file = fragp->fr_file; |
18901 | fixp->fx_line = fragp->fr_line; | |
18902 | ||
18903 | /* Branch over the jump. */ | |
4d68580a | 18904 | buf = write_compressed_insn (buf, insn, 4); |
8484fb75 | 18905 | |
df58fc94 | 18906 | if (!compact) |
8484fb75 MR |
18907 | { |
18908 | /* nop */ | |
18909 | if (insn32) | |
18910 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18911 | else | |
18912 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18913 | } | |
df58fc94 RS |
18914 | } |
18915 | ||
ce8ad872 | 18916 | if (!pic) |
df58fc94 | 18917 | { |
7bd374a4 MR |
18918 | unsigned long jal = (short_ds || nods |
18919 | ? 0x74000000 : 0xf4000000); /* jal/s */ | |
2309ddf2 | 18920 | |
df58fc94 RS |
18921 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18922 | insn = al ? jal : 0xd4000000; | |
18923 | ||
bbd27b76 MR |
18924 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18925 | fragp->fr_symbol, fragp->fr_offset, | |
18926 | FALSE, BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18927 | fixp->fx_file = fragp->fr_file; |
18928 | fixp->fx_line = fragp->fr_line; | |
18929 | ||
4d68580a | 18930 | buf = write_compressed_insn (buf, insn, 4); |
8484fb75 | 18931 | |
7bd374a4 | 18932 | if (compact || nods) |
8484fb75 MR |
18933 | { |
18934 | /* nop */ | |
18935 | if (insn32) | |
18936 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18937 | else | |
18938 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18939 | } | |
df58fc94 RS |
18940 | } |
18941 | else | |
18942 | { | |
18943 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
18944 | ||
18945 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18946 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18947 | insn |= at << MICROMIPSOP_SH_RT; | |
18948 | ||
bbd27b76 MR |
18949 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18950 | fragp->fr_symbol, fragp->fr_offset, | |
18951 | FALSE, BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18952 | fixp->fx_file = fragp->fr_file; |
18953 | fixp->fx_line = fragp->fr_line; | |
18954 | ||
4d68580a | 18955 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18956 | |
18957 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18958 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18959 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18960 | ||
bbd27b76 MR |
18961 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18962 | fragp->fr_symbol, fragp->fr_offset, | |
18963 | FALSE, BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18964 | fixp->fx_file = fragp->fr_file; |
18965 | fixp->fx_line = fragp->fr_line; | |
18966 | ||
4d68580a | 18967 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18968 | |
8484fb75 MR |
18969 | if (insn32) |
18970 | { | |
18971 | /* jr/jalr $at */ | |
18972 | insn = 0x00000f3c | (al ? RA : ZERO) << MICROMIPSOP_SH_RT; | |
18973 | insn |= at << MICROMIPSOP_SH_RS; | |
18974 | ||
18975 | buf = write_compressed_insn (buf, insn, 4); | |
df58fc94 | 18976 | |
7bd374a4 | 18977 | if (compact || nods) |
8484fb75 MR |
18978 | /* nop */ |
18979 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18980 | } | |
18981 | else | |
18982 | { | |
18983 | /* jr/jrc/jalr/jalrs $at */ | |
18984 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ | |
7bd374a4 | 18985 | unsigned long jr = compact || nods ? 0x45a0 : 0x4580; /* jr/c */ |
8484fb75 MR |
18986 | |
18987 | insn = al ? jalr : jr; | |
18988 | insn |= at << MICROMIPSOP_SH_MJ; | |
18989 | ||
18990 | buf = write_compressed_insn (buf, insn, 2); | |
7bd374a4 MR |
18991 | if (al && nods) |
18992 | { | |
18993 | /* nop */ | |
18994 | if (short_ds) | |
18995 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18996 | else | |
18997 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18998 | } | |
8484fb75 | 18999 | } |
df58fc94 RS |
19000 | } |
19001 | ||
4d68580a | 19002 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
19003 | return; |
19004 | } | |
19005 | ||
252b5132 RH |
19006 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
19007 | { | |
19008 | int type; | |
3ccad066 | 19009 | const struct mips_int_operand *operand; |
252b5132 | 19010 | offsetT val; |
5c04167a | 19011 | char *buf; |
8507b6e7 | 19012 | unsigned int user_length; |
9d862524 | 19013 | bfd_boolean need_reloc; |
252b5132 | 19014 | unsigned long insn; |
8507b6e7 | 19015 | bfd_boolean mac; |
5c04167a | 19016 | bfd_boolean ext; |
88a7ef16 | 19017 | segT symsec; |
252b5132 RH |
19018 | |
19019 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
3ccad066 | 19020 | operand = mips16_immed_operand (type, FALSE); |
252b5132 | 19021 | |
8507b6e7 | 19022 | mac = RELAX_MIPS16_MACRO (fragp->fr_subtype); |
5c04167a | 19023 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
88a7ef16 | 19024 | val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset; |
9d862524 MR |
19025 | |
19026 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
19027 | need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, TRUE) | |
8507b6e7 | 19028 | || (operand->root.type == OP_PCREL && !mac |
9d862524 MR |
19029 | ? asec != symsec |
19030 | : !bfd_is_abs_section (symsec))); | |
19031 | ||
8507b6e7 | 19032 | if (operand->root.type == OP_PCREL && !mac) |
252b5132 | 19033 | { |
3ccad066 | 19034 | const struct mips_pcrel_operand *pcrel_op; |
252b5132 | 19035 | |
3ccad066 | 19036 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
252b5132 | 19037 | |
14f72d45 | 19038 | if (pcrel_op->include_isa_bit && !need_reloc) |
252b5132 | 19039 | { |
37b2d327 MR |
19040 | if (!mips_ignore_branch_isa |
19041 | && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp->fr_symbol))) | |
14f72d45 MR |
19042 | as_bad_where (fragp->fr_file, fragp->fr_line, |
19043 | _("branch to a symbol in another ISA mode")); | |
19044 | else if ((fragp->fr_offset & 0x1) != 0) | |
19045 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
19046 | _("branch to misaligned address (0x%lx)"), | |
52031738 FS |
19047 | (long) (resolve_symbol_value (fragp->fr_symbol) |
19048 | + (fragp->fr_offset & ~1))); | |
252b5132 | 19049 | } |
252b5132 | 19050 | |
14f72d45 | 19051 | val = mips16_pcrel_val (fragp, pcrel_op, val, 0); |
252b5132 RH |
19052 | |
19053 | /* Make sure the section winds up with the alignment we have | |
19054 | assumed. */ | |
3ccad066 RS |
19055 | if (operand->shift > 0) |
19056 | record_alignment (asec, operand->shift); | |
252b5132 RH |
19057 | } |
19058 | ||
8507b6e7 MR |
19059 | if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) |
19060 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
19061 | { | |
19062 | if (mac) | |
19063 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
19064 | _("macro instruction expanded into multiple " | |
19065 | "instructions in a branch delay slot")); | |
19066 | else if (ext) | |
19067 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
19068 | _("extended instruction in a branch delay slot")); | |
19069 | } | |
19070 | else if (RELAX_MIPS16_NOMACRO (fragp->fr_subtype) && mac) | |
252b5132 | 19071 | as_warn_where (fragp->fr_file, fragp->fr_line, |
8507b6e7 MR |
19072 | _("macro instruction expanded into multiple " |
19073 | "instructions")); | |
252b5132 | 19074 | |
5c04167a | 19075 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 19076 | |
4d68580a | 19077 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
19078 | if (ext) |
19079 | insn |= MIPS16_EXTEND; | |
252b5132 | 19080 | |
5c04167a RS |
19081 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
19082 | user_length = 4; | |
19083 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
19084 | user_length = 2; | |
19085 | else | |
19086 | user_length = 0; | |
19087 | ||
8507b6e7 | 19088 | if (mac) |
c9775dde | 19089 | { |
8507b6e7 MR |
19090 | unsigned long reg; |
19091 | unsigned long new; | |
19092 | unsigned long op; | |
25499ac7 | 19093 | bfd_boolean e2; |
8507b6e7 MR |
19094 | |
19095 | gas_assert (type == 'A' || type == 'B' || type == 'E'); | |
19096 | gas_assert (RELAX_MIPS16_SYM32 (fragp->fr_subtype)); | |
c9775dde | 19097 | |
25499ac7 MR |
19098 | e2 = RELAX_MIPS16_E2 (fragp->fr_subtype); |
19099 | ||
8507b6e7 | 19100 | if (need_reloc) |
c9775dde | 19101 | { |
8507b6e7 MR |
19102 | fixS *fixp; |
19103 | ||
19104 | gas_assert (!RELAX_MIPS16_PIC (fragp->fr_subtype)); | |
19105 | ||
19106 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, | |
19107 | fragp->fr_symbol, fragp->fr_offset, | |
19108 | FALSE, BFD_RELOC_MIPS16_HI16_S); | |
19109 | fixp->fx_file = fragp->fr_file; | |
19110 | fixp->fx_line = fragp->fr_line; | |
19111 | ||
25499ac7 | 19112 | fixp = fix_new (fragp, buf - fragp->fr_literal + (e2 ? 4 : 8), 4, |
8507b6e7 MR |
19113 | fragp->fr_symbol, fragp->fr_offset, |
19114 | FALSE, BFD_RELOC_MIPS16_LO16); | |
19115 | fixp->fx_file = fragp->fr_file; | |
19116 | fixp->fx_line = fragp->fr_line; | |
19117 | ||
19118 | val = 0; | |
19119 | } | |
19120 | ||
19121 | switch (insn & 0xf800) | |
19122 | { | |
19123 | case 0x0800: /* ADDIU */ | |
19124 | reg = (insn >> 8) & 0x7; | |
19125 | op = 0xf0004800 | (reg << 8); | |
c9775dde | 19126 | break; |
8507b6e7 MR |
19127 | case 0xb000: /* LW */ |
19128 | reg = (insn >> 8) & 0x7; | |
19129 | op = 0xf0009800 | (reg << 8) | (reg << 5); | |
c9775dde | 19130 | break; |
8507b6e7 MR |
19131 | case 0xf800: /* I64 */ |
19132 | reg = (insn >> 5) & 0x7; | |
19133 | switch (insn & 0x0700) | |
19134 | { | |
19135 | case 0x0400: /* LD */ | |
19136 | op = 0xf0003800 | (reg << 8) | (reg << 5); | |
19137 | break; | |
19138 | case 0x0600: /* DADDIU */ | |
19139 | op = 0xf000fd00 | (reg << 5); | |
19140 | break; | |
19141 | default: | |
19142 | abort (); | |
19143 | } | |
19144 | break; | |
19145 | default: | |
19146 | abort (); | |
c9775dde | 19147 | } |
8507b6e7 | 19148 | |
25499ac7 | 19149 | new = (e2 ? 0xf0006820 : 0xf0006800) | (reg << 8); /* LUI/LI */ |
8507b6e7 MR |
19150 | new |= mips16_immed_extend ((val + 0x8000) >> 16, 16); |
19151 | buf = write_compressed_insn (buf, new, 4); | |
25499ac7 MR |
19152 | if (!e2) |
19153 | { | |
19154 | new = 0xf4003000 | (reg << 8) | (reg << 5); /* SLL */ | |
19155 | buf = write_compressed_insn (buf, new, 4); | |
19156 | } | |
8507b6e7 MR |
19157 | op |= mips16_immed_extend (val, 16); |
19158 | buf = write_compressed_insn (buf, op, 4); | |
19159 | ||
25499ac7 | 19160 | fragp->fr_fix += e2 ? 8 : 12; |
8507b6e7 MR |
19161 | } |
19162 | else | |
19163 | { | |
19164 | unsigned int length = ext ? 4 : 2; | |
19165 | ||
19166 | if (need_reloc) | |
c9775dde | 19167 | { |
8507b6e7 | 19168 | bfd_reloc_code_real_type reloc = BFD_RELOC_NONE; |
8507b6e7 | 19169 | fixS *fixp; |
c9775dde | 19170 | |
8507b6e7 MR |
19171 | switch (type) |
19172 | { | |
19173 | case 'p': | |
19174 | case 'q': | |
19175 | reloc = BFD_RELOC_MIPS16_16_PCREL_S1; | |
19176 | break; | |
19177 | default: | |
19178 | break; | |
19179 | } | |
19180 | if (mac || reloc == BFD_RELOC_NONE) | |
19181 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
19182 | _("unsupported relocation")); | |
19183 | else if (ext) | |
19184 | { | |
bbd27b76 MR |
19185 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
19186 | fragp->fr_symbol, fragp->fr_offset, | |
19187 | TRUE, reloc); | |
8507b6e7 MR |
19188 | fixp->fx_file = fragp->fr_file; |
19189 | fixp->fx_line = fragp->fr_line; | |
19190 | } | |
19191 | else | |
19192 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
19193 | _("invalid unextended operand value")); | |
c9775dde | 19194 | } |
eefc3365 | 19195 | else |
8507b6e7 MR |
19196 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
19197 | BFD_RELOC_UNUSED, val, user_length, &insn); | |
252b5132 | 19198 | |
8507b6e7 MR |
19199 | gas_assert (mips16_opcode_length (insn) == length); |
19200 | write_compressed_insn (buf, insn, length); | |
19201 | fragp->fr_fix += length; | |
19202 | } | |
252b5132 RH |
19203 | } |
19204 | else | |
19205 | { | |
df58fc94 RS |
19206 | relax_substateT subtype = fragp->fr_subtype; |
19207 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
19208 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
871a6bd2 | 19209 | unsigned int first, second; |
4d7206a2 | 19210 | fixS *fixp; |
252b5132 | 19211 | |
df58fc94 RS |
19212 | first = RELAX_FIRST (subtype); |
19213 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 19214 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 19215 | |
df58fc94 RS |
19216 | /* If the delay slot chosen does not match the size of the instruction, |
19217 | then emit a warning. */ | |
19218 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
19219 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
19220 | { | |
19221 | relax_substateT s; | |
19222 | const char *msg; | |
19223 | ||
19224 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
19225 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
19226 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
19227 | msg = macro_warning (s); | |
19228 | if (msg != NULL) | |
db9b2be4 | 19229 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
19230 | subtype &= ~s; |
19231 | } | |
19232 | ||
584892a6 | 19233 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 19234 | if (use_second == second_longer) |
584892a6 | 19235 | { |
df58fc94 RS |
19236 | relax_substateT s; |
19237 | const char *msg; | |
19238 | ||
19239 | s = (subtype | |
19240 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
19241 | msg = macro_warning (s); | |
19242 | if (msg != NULL) | |
db9b2be4 | 19243 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 19244 | subtype &= ~s; |
584892a6 RS |
19245 | } |
19246 | ||
4d7206a2 RS |
19247 | /* Go through all the fixups for the first sequence. Disable them |
19248 | (by marking them as done) if we're going to use the second | |
19249 | sequence instead. */ | |
19250 | while (fixp | |
19251 | && fixp->fx_frag == fragp | |
90bd3c90 | 19252 | && fixp->fx_where + second < fragp->fr_fix) |
4d7206a2 | 19253 | { |
df58fc94 | 19254 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
19255 | fixp->fx_done = 1; |
19256 | fixp = fixp->fx_next; | |
19257 | } | |
252b5132 | 19258 | |
4d7206a2 RS |
19259 | /* Go through the fixups for the second sequence. Disable them if |
19260 | we're going to use the first sequence, otherwise adjust their | |
19261 | addresses to account for the relaxation. */ | |
19262 | while (fixp && fixp->fx_frag == fragp) | |
19263 | { | |
df58fc94 | 19264 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
19265 | fixp->fx_where -= first; |
19266 | else | |
19267 | fixp->fx_done = 1; | |
19268 | fixp = fixp->fx_next; | |
19269 | } | |
19270 | ||
19271 | /* Now modify the frag contents. */ | |
df58fc94 | 19272 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
19273 | { |
19274 | char *start; | |
19275 | ||
19276 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
19277 | memmove (start, start + first, second); | |
19278 | fragp->fr_fix -= first; | |
19279 | } | |
19280 | else | |
19281 | fragp->fr_fix -= second; | |
252b5132 RH |
19282 | } |
19283 | } | |
19284 | ||
252b5132 RH |
19285 | /* This function is called after the relocs have been generated. |
19286 | We've been storing mips16 text labels as odd. Here we convert them | |
19287 | back to even for the convenience of the debugger. */ | |
19288 | ||
19289 | void | |
17a2f251 | 19290 | mips_frob_file_after_relocs (void) |
252b5132 RH |
19291 | { |
19292 | asymbol **syms; | |
19293 | unsigned int count, i; | |
19294 | ||
252b5132 RH |
19295 | syms = bfd_get_outsymbols (stdoutput); |
19296 | count = bfd_get_symcount (stdoutput); | |
19297 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
19298 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
19299 | && ((*syms)->value & 1) != 0) | |
19300 | { | |
19301 | (*syms)->value &= ~1; | |
19302 | /* If the symbol has an odd size, it was probably computed | |
19303 | incorrectly, so adjust that as well. */ | |
19304 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
19305 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
19306 | } | |
252b5132 RH |
19307 | } |
19308 | ||
a1facbec MR |
19309 | /* This function is called whenever a label is defined, including fake |
19310 | labels instantiated off the dot special symbol. It is used when | |
19311 | handling branch delays; if a branch has a label, we assume we cannot | |
19312 | move it. This also bumps the value of the symbol by 1 in compressed | |
19313 | code. */ | |
252b5132 | 19314 | |
e1b47bd5 | 19315 | static void |
a1facbec | 19316 | mips_record_label (symbolS *sym) |
252b5132 | 19317 | { |
a8dbcb85 | 19318 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
19319 | struct insn_label_list *l; |
19320 | ||
19321 | if (free_insn_labels == NULL) | |
325801bd | 19322 | l = XNEW (struct insn_label_list); |
252b5132 RH |
19323 | else |
19324 | { | |
19325 | l = free_insn_labels; | |
19326 | free_insn_labels = l->next; | |
19327 | } | |
19328 | ||
19329 | l->label = sym; | |
a8dbcb85 TS |
19330 | l->next = si->label_list; |
19331 | si->label_list = l; | |
a1facbec | 19332 | } |
07a53e5c | 19333 | |
a1facbec MR |
19334 | /* This function is called as tc_frob_label() whenever a label is defined |
19335 | and adds a DWARF-2 record we only want for true labels. */ | |
19336 | ||
19337 | void | |
19338 | mips_define_label (symbolS *sym) | |
19339 | { | |
19340 | mips_record_label (sym); | |
07a53e5c | 19341 | dwarf2_emit_label (sym); |
252b5132 | 19342 | } |
e1b47bd5 RS |
19343 | |
19344 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
19345 | is defined. */ | |
19346 | ||
19347 | void | |
19348 | mips_add_dot_label (symbolS *sym) | |
19349 | { | |
19350 | mips_record_label (sym); | |
19351 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
19352 | mips_compressed_mark_label (sym); | |
19353 | } | |
252b5132 | 19354 | \f |
351cdf24 MF |
19355 | /* Converting ASE flags from internal to .MIPS.abiflags values. */ |
19356 | static unsigned int | |
19357 | mips_convert_ase_flags (int ase) | |
19358 | { | |
19359 | unsigned int ext_ases = 0; | |
19360 | ||
19361 | if (ase & ASE_DSP) | |
19362 | ext_ases |= AFL_ASE_DSP; | |
19363 | if (ase & ASE_DSPR2) | |
19364 | ext_ases |= AFL_ASE_DSPR2; | |
8f4f9071 MF |
19365 | if (ase & ASE_DSPR3) |
19366 | ext_ases |= AFL_ASE_DSPR3; | |
351cdf24 MF |
19367 | if (ase & ASE_EVA) |
19368 | ext_ases |= AFL_ASE_EVA; | |
19369 | if (ase & ASE_MCU) | |
19370 | ext_ases |= AFL_ASE_MCU; | |
19371 | if (ase & ASE_MDMX) | |
19372 | ext_ases |= AFL_ASE_MDMX; | |
19373 | if (ase & ASE_MIPS3D) | |
19374 | ext_ases |= AFL_ASE_MIPS3D; | |
19375 | if (ase & ASE_MT) | |
19376 | ext_ases |= AFL_ASE_MT; | |
19377 | if (ase & ASE_SMARTMIPS) | |
19378 | ext_ases |= AFL_ASE_SMARTMIPS; | |
19379 | if (ase & ASE_VIRT) | |
19380 | ext_ases |= AFL_ASE_VIRT; | |
19381 | if (ase & ASE_MSA) | |
19382 | ext_ases |= AFL_ASE_MSA; | |
19383 | if (ase & ASE_XPA) | |
19384 | ext_ases |= AFL_ASE_XPA; | |
25499ac7 MR |
19385 | if (ase & ASE_MIPS16E2) |
19386 | ext_ases |= file_ase_mips16 ? AFL_ASE_MIPS16E2 : 0; | |
730c3174 SE |
19387 | if (ase & ASE_CRC) |
19388 | ext_ases |= AFL_ASE_CRC; | |
6f20c942 FS |
19389 | if (ase & ASE_GINV) |
19390 | ext_ases |= AFL_ASE_GINV; | |
8095d2f7 CX |
19391 | if (ase & ASE_LOONGSON_MMI) |
19392 | ext_ases |= AFL_ASE_LOONGSON_MMI; | |
716c08de CX |
19393 | if (ase & ASE_LOONGSON_CAM) |
19394 | ext_ases |= AFL_ASE_LOONGSON_CAM; | |
bdc6c06e CX |
19395 | if (ase & ASE_LOONGSON_EXT) |
19396 | ext_ases |= AFL_ASE_LOONGSON_EXT; | |
a693765e CX |
19397 | if (ase & ASE_LOONGSON_EXT2) |
19398 | ext_ases |= AFL_ASE_LOONGSON_EXT2; | |
351cdf24 MF |
19399 | |
19400 | return ext_ases; | |
19401 | } | |
252b5132 RH |
19402 | /* Some special processing for a MIPS ELF file. */ |
19403 | ||
19404 | void | |
17a2f251 | 19405 | mips_elf_final_processing (void) |
252b5132 | 19406 | { |
351cdf24 MF |
19407 | int fpabi; |
19408 | Elf_Internal_ABIFlags_v0 flags; | |
19409 | ||
19410 | flags.version = 0; | |
19411 | flags.isa_rev = 0; | |
19412 | switch (file_mips_opts.isa) | |
19413 | { | |
19414 | case INSN_ISA1: | |
19415 | flags.isa_level = 1; | |
19416 | break; | |
19417 | case INSN_ISA2: | |
19418 | flags.isa_level = 2; | |
19419 | break; | |
19420 | case INSN_ISA3: | |
19421 | flags.isa_level = 3; | |
19422 | break; | |
19423 | case INSN_ISA4: | |
19424 | flags.isa_level = 4; | |
19425 | break; | |
19426 | case INSN_ISA5: | |
19427 | flags.isa_level = 5; | |
19428 | break; | |
19429 | case INSN_ISA32: | |
19430 | flags.isa_level = 32; | |
19431 | flags.isa_rev = 1; | |
19432 | break; | |
19433 | case INSN_ISA32R2: | |
19434 | flags.isa_level = 32; | |
19435 | flags.isa_rev = 2; | |
19436 | break; | |
19437 | case INSN_ISA32R3: | |
19438 | flags.isa_level = 32; | |
19439 | flags.isa_rev = 3; | |
19440 | break; | |
19441 | case INSN_ISA32R5: | |
19442 | flags.isa_level = 32; | |
19443 | flags.isa_rev = 5; | |
19444 | break; | |
09c14161 MF |
19445 | case INSN_ISA32R6: |
19446 | flags.isa_level = 32; | |
19447 | flags.isa_rev = 6; | |
19448 | break; | |
351cdf24 MF |
19449 | case INSN_ISA64: |
19450 | flags.isa_level = 64; | |
19451 | flags.isa_rev = 1; | |
19452 | break; | |
19453 | case INSN_ISA64R2: | |
19454 | flags.isa_level = 64; | |
19455 | flags.isa_rev = 2; | |
19456 | break; | |
19457 | case INSN_ISA64R3: | |
19458 | flags.isa_level = 64; | |
19459 | flags.isa_rev = 3; | |
19460 | break; | |
19461 | case INSN_ISA64R5: | |
19462 | flags.isa_level = 64; | |
19463 | flags.isa_rev = 5; | |
19464 | break; | |
09c14161 MF |
19465 | case INSN_ISA64R6: |
19466 | flags.isa_level = 64; | |
19467 | flags.isa_rev = 6; | |
19468 | break; | |
351cdf24 MF |
19469 | } |
19470 | ||
19471 | flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64; | |
19472 | flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE | |
19473 | : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128 | |
19474 | : (file_mips_opts.fp == 64) ? AFL_REG_64 | |
19475 | : AFL_REG_32; | |
19476 | flags.cpr2_size = AFL_REG_NONE; | |
19477 | flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
19478 | Tag_GNU_MIPS_ABI_FP); | |
19479 | flags.isa_ext = bfd_mips_isa_ext (stdoutput); | |
19480 | flags.ases = mips_convert_ase_flags (file_mips_opts.ase); | |
19481 | if (file_ase_mips16) | |
19482 | flags.ases |= AFL_ASE_MIPS16; | |
19483 | if (file_ase_micromips) | |
19484 | flags.ases |= AFL_ASE_MICROMIPS; | |
19485 | flags.flags1 = 0; | |
19486 | if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch) | |
19487 | || file_mips_opts.fp == 64) | |
19488 | && file_mips_opts.oddspreg) | |
19489 | flags.flags1 |= AFL_FLAGS1_ODDSPREG; | |
19490 | flags.flags2 = 0; | |
19491 | ||
19492 | bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags, | |
19493 | ((Elf_External_ABIFlags_v0 *) | |
19494 | mips_flags_frag)); | |
19495 | ||
252b5132 | 19496 | /* Write out the register information. */ |
316f5878 | 19497 | if (mips_abi != N64_ABI) |
252b5132 RH |
19498 | { |
19499 | Elf32_RegInfo s; | |
19500 | ||
19501 | s.ri_gprmask = mips_gprmask; | |
19502 | s.ri_cprmask[0] = mips_cprmask[0]; | |
19503 | s.ri_cprmask[1] = mips_cprmask[1]; | |
19504 | s.ri_cprmask[2] = mips_cprmask[2]; | |
19505 | s.ri_cprmask[3] = mips_cprmask[3]; | |
19506 | /* The gp_value field is set by the MIPS ELF backend. */ | |
19507 | ||
19508 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
19509 | ((Elf32_External_RegInfo *) | |
19510 | mips_regmask_frag)); | |
19511 | } | |
19512 | else | |
19513 | { | |
19514 | Elf64_Internal_RegInfo s; | |
19515 | ||
19516 | s.ri_gprmask = mips_gprmask; | |
19517 | s.ri_pad = 0; | |
19518 | s.ri_cprmask[0] = mips_cprmask[0]; | |
19519 | s.ri_cprmask[1] = mips_cprmask[1]; | |
19520 | s.ri_cprmask[2] = mips_cprmask[2]; | |
19521 | s.ri_cprmask[3] = mips_cprmask[3]; | |
19522 | /* The gp_value field is set by the MIPS ELF backend. */ | |
19523 | ||
19524 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
19525 | ((Elf64_External_RegInfo *) | |
19526 | mips_regmask_frag)); | |
19527 | } | |
19528 | ||
19529 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
19530 | sort of BFD interface for this. */ | |
19531 | if (mips_any_noreorder) | |
19532 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
19533 | if (mips_pic != NO_PIC) | |
143d77c5 | 19534 | { |
8b828383 | 19535 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
19536 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
19537 | } | |
19538 | if (mips_abicalls) | |
19539 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 19540 | |
b015e599 AP |
19541 | /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags |
19542 | defined at present; this might need to change in future. */ | |
a4672219 TS |
19543 | if (file_ase_mips16) |
19544 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
19545 | if (file_ase_micromips) |
19546 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
919731af | 19547 | if (file_mips_opts.ase & ASE_MDMX) |
deec1734 | 19548 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; |
1f25f5d3 | 19549 | |
bdaaa2e1 | 19550 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 19551 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 19552 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 19553 | else if (mips_abi == O64_ABI) |
252b5132 | 19554 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 19555 | else if (mips_abi == EABI_ABI) |
252b5132 | 19556 | { |
bad1aba3 | 19557 | if (file_mips_opts.gp == 64) |
252b5132 RH |
19558 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
19559 | else | |
19560 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
19561 | } | |
be00bddd | 19562 | |
defc8e2b | 19563 | /* Nothing to do for N32_ABI or N64_ABI. */ |
252b5132 RH |
19564 | |
19565 | if (mips_32bitmode) | |
19566 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 | 19567 | |
7361da2c | 19568 | if (mips_nan2008 == 1) |
ba92f887 MR |
19569 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008; |
19570 | ||
ad3fea08 | 19571 | /* 32 bit code with 64 bit FP registers. */ |
351cdf24 MF |
19572 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, |
19573 | Tag_GNU_MIPS_ABI_FP); | |
19574 | if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64) | |
f1c38003 | 19575 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64; |
252b5132 | 19576 | } |
252b5132 | 19577 | \f |
beae10d5 | 19578 | typedef struct proc { |
9b2f1d35 EC |
19579 | symbolS *func_sym; |
19580 | symbolS *func_end_sym; | |
beae10d5 KH |
19581 | unsigned long reg_mask; |
19582 | unsigned long reg_offset; | |
19583 | unsigned long fpreg_mask; | |
19584 | unsigned long fpreg_offset; | |
19585 | unsigned long frame_offset; | |
19586 | unsigned long frame_reg; | |
19587 | unsigned long pc_reg; | |
19588 | } procS; | |
252b5132 RH |
19589 | |
19590 | static procS cur_proc; | |
19591 | static procS *cur_proc_ptr; | |
19592 | static int numprocs; | |
19593 | ||
df58fc94 RS |
19594 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
19595 | as "2", and a normal nop as "0". */ | |
19596 | ||
19597 | #define NOP_OPCODE_MIPS 0 | |
19598 | #define NOP_OPCODE_MIPS16 1 | |
19599 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
19600 | |
19601 | char | |
19602 | mips_nop_opcode (void) | |
19603 | { | |
df58fc94 RS |
19604 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
19605 | return NOP_OPCODE_MICROMIPS; | |
19606 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
19607 | return NOP_OPCODE_MIPS16; | |
19608 | else | |
19609 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
19610 | } |
19611 | ||
df58fc94 RS |
19612 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
19613 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 19614 | |
0a9ef439 | 19615 | void |
17a2f251 | 19616 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 19617 | { |
df58fc94 | 19618 | char nop_opcode; |
742a56fe | 19619 | char *p; |
c67a084a NC |
19620 | int bytes, size, excess; |
19621 | valueT opcode; | |
742a56fe | 19622 | |
0a9ef439 RH |
19623 | if (fragp->fr_type != rs_align_code) |
19624 | return; | |
19625 | ||
742a56fe | 19626 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
19627 | nop_opcode = *p; |
19628 | switch (nop_opcode) | |
a19d8eb0 | 19629 | { |
df58fc94 RS |
19630 | case NOP_OPCODE_MICROMIPS: |
19631 | opcode = micromips_nop32_insn.insn_opcode; | |
19632 | size = 4; | |
19633 | break; | |
19634 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
19635 | opcode = mips16_nop_insn.insn_opcode; |
19636 | size = 2; | |
df58fc94 RS |
19637 | break; |
19638 | case NOP_OPCODE_MIPS: | |
19639 | default: | |
c67a084a NC |
19640 | opcode = nop_insn.insn_opcode; |
19641 | size = 4; | |
df58fc94 | 19642 | break; |
c67a084a | 19643 | } |
a19d8eb0 | 19644 | |
c67a084a NC |
19645 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
19646 | excess = bytes % size; | |
df58fc94 RS |
19647 | |
19648 | /* Handle the leading part if we're not inserting a whole number of | |
19649 | instructions, and make it the end of the fixed part of the frag. | |
19650 | Try to fit in a short microMIPS NOP if applicable and possible, | |
19651 | and use zeroes otherwise. */ | |
19652 | gas_assert (excess < 4); | |
19653 | fragp->fr_fix += excess; | |
19654 | switch (excess) | |
c67a084a | 19655 | { |
df58fc94 RS |
19656 | case 3: |
19657 | *p++ = '\0'; | |
19658 | /* Fall through. */ | |
19659 | case 2: | |
833794fc | 19660 | if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32) |
df58fc94 | 19661 | { |
4d68580a | 19662 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
19663 | break; |
19664 | } | |
19665 | *p++ = '\0'; | |
19666 | /* Fall through. */ | |
19667 | case 1: | |
19668 | *p++ = '\0'; | |
19669 | /* Fall through. */ | |
19670 | case 0: | |
19671 | break; | |
a19d8eb0 | 19672 | } |
c67a084a NC |
19673 | |
19674 | md_number_to_chars (p, opcode, size); | |
19675 | fragp->fr_var = size; | |
a19d8eb0 CP |
19676 | } |
19677 | ||
252b5132 | 19678 | static long |
17a2f251 | 19679 | get_number (void) |
252b5132 RH |
19680 | { |
19681 | int negative = 0; | |
19682 | long val = 0; | |
19683 | ||
19684 | if (*input_line_pointer == '-') | |
19685 | { | |
19686 | ++input_line_pointer; | |
19687 | negative = 1; | |
19688 | } | |
3882b010 | 19689 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 19690 | as_bad (_("expected simple number")); |
252b5132 RH |
19691 | if (input_line_pointer[0] == '0') |
19692 | { | |
19693 | if (input_line_pointer[1] == 'x') | |
19694 | { | |
19695 | input_line_pointer += 2; | |
3882b010 | 19696 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
19697 | { |
19698 | val <<= 4; | |
19699 | val |= hex_value (*input_line_pointer++); | |
19700 | } | |
19701 | return negative ? -val : val; | |
19702 | } | |
19703 | else | |
19704 | { | |
19705 | ++input_line_pointer; | |
3882b010 | 19706 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19707 | { |
19708 | val <<= 3; | |
19709 | val |= *input_line_pointer++ - '0'; | |
19710 | } | |
19711 | return negative ? -val : val; | |
19712 | } | |
19713 | } | |
3882b010 | 19714 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19715 | { |
19716 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
19717 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 19718 | as_warn (_("invalid number")); |
252b5132 RH |
19719 | return -1; |
19720 | } | |
3882b010 | 19721 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19722 | { |
19723 | val *= 10; | |
19724 | val += *input_line_pointer++ - '0'; | |
19725 | } | |
19726 | return negative ? -val : val; | |
19727 | } | |
19728 | ||
19729 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
19730 | is an initial number which is the ECOFF file index. In the non-ECOFF |
19731 | case .file implies DWARF-2. */ | |
19732 | ||
19733 | static void | |
17a2f251 | 19734 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 19735 | { |
ecb4347a DJ |
19736 | static int first_file_directive = 0; |
19737 | ||
c5dd6aab DJ |
19738 | if (ECOFF_DEBUGGING) |
19739 | { | |
19740 | get_number (); | |
19741 | s_app_file (0); | |
19742 | } | |
19743 | else | |
ecb4347a DJ |
19744 | { |
19745 | char *filename; | |
19746 | ||
68d20676 | 19747 | filename = dwarf2_directive_filename (); |
ecb4347a DJ |
19748 | |
19749 | /* Versions of GCC up to 3.1 start files with a ".file" | |
19750 | directive even for stabs output. Make sure that this | |
19751 | ".file" is handled. Note that you need a version of GCC | |
19752 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
19753 | if (filename != NULL && ! first_file_directive) | |
19754 | { | |
19755 | (void) new_logical_line (filename, -1); | |
c04f5787 | 19756 | s_app_file_string (filename, 0); |
ecb4347a DJ |
19757 | } |
19758 | first_file_directive = 1; | |
19759 | } | |
c5dd6aab DJ |
19760 | } |
19761 | ||
19762 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
19763 | |
19764 | static void | |
17a2f251 | 19765 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 19766 | { |
c5dd6aab DJ |
19767 | if (!ECOFF_DEBUGGING) |
19768 | dwarf2_directive_loc (0); | |
252b5132 RH |
19769 | } |
19770 | ||
252b5132 RH |
19771 | /* The .end directive. */ |
19772 | ||
19773 | static void | |
17a2f251 | 19774 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
19775 | { |
19776 | symbolS *p; | |
252b5132 | 19777 | |
7a621144 DJ |
19778 | /* Following functions need their own .frame and .cprestore directives. */ |
19779 | mips_frame_reg_valid = 0; | |
19780 | mips_cprestore_valid = 0; | |
19781 | ||
252b5132 RH |
19782 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
19783 | { | |
19784 | p = get_symbol (); | |
19785 | demand_empty_rest_of_line (); | |
19786 | } | |
19787 | else | |
19788 | p = NULL; | |
19789 | ||
fd361982 | 19790 | if ((bfd_section_flags (now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19791 | as_warn (_(".end not in text section")); |
19792 | ||
19793 | if (!cur_proc_ptr) | |
19794 | { | |
1661c76c | 19795 | as_warn (_(".end directive without a preceding .ent directive")); |
252b5132 RH |
19796 | demand_empty_rest_of_line (); |
19797 | return; | |
19798 | } | |
19799 | ||
19800 | if (p != NULL) | |
19801 | { | |
9c2799c2 | 19802 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 19803 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
1661c76c | 19804 | as_warn (_(".end symbol does not match .ent symbol")); |
ecb4347a DJ |
19805 | |
19806 | if (debug_type == DEBUG_STABS) | |
19807 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
19808 | S_GET_NAME (p)); | |
252b5132 RH |
19809 | } |
19810 | else | |
19811 | as_warn (_(".end directive missing or unknown symbol")); | |
19812 | ||
9b2f1d35 EC |
19813 | /* Create an expression to calculate the size of the function. */ |
19814 | if (p && cur_proc_ptr) | |
19815 | { | |
19816 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
325801bd | 19817 | expressionS *exp = XNEW (expressionS); |
9b2f1d35 EC |
19818 | |
19819 | obj->size = exp; | |
19820 | exp->X_op = O_subtract; | |
19821 | exp->X_add_symbol = symbol_temp_new_now (); | |
19822 | exp->X_op_symbol = p; | |
19823 | exp->X_add_number = 0; | |
19824 | ||
19825 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
19826 | } | |
19827 | ||
5ff6a06c MR |
19828 | #ifdef md_flush_pending_output |
19829 | md_flush_pending_output (); | |
19830 | #endif | |
19831 | ||
ecb4347a | 19832 | /* Generate a .pdr section. */ |
f3ded42a | 19833 | if (!ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
19834 | { |
19835 | segT saved_seg = now_seg; | |
19836 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
19837 | expressionS exp; |
19838 | char *fragp; | |
252b5132 | 19839 | |
9c2799c2 | 19840 | gas_assert (pdr_seg); |
ecb4347a | 19841 | subseg_set (pdr_seg, 0); |
252b5132 | 19842 | |
ecb4347a DJ |
19843 | /* Write the symbol. */ |
19844 | exp.X_op = O_symbol; | |
19845 | exp.X_add_symbol = p; | |
19846 | exp.X_add_number = 0; | |
19847 | emit_expr (&exp, 4); | |
252b5132 | 19848 | |
ecb4347a | 19849 | fragp = frag_more (7 * 4); |
252b5132 | 19850 | |
17a2f251 TS |
19851 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
19852 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
19853 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
19854 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
19855 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
19856 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
19857 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 19858 | |
ecb4347a DJ |
19859 | subseg_set (saved_seg, saved_subseg); |
19860 | } | |
252b5132 RH |
19861 | |
19862 | cur_proc_ptr = NULL; | |
19863 | } | |
19864 | ||
19865 | /* The .aent and .ent directives. */ | |
19866 | ||
19867 | static void | |
17a2f251 | 19868 | s_mips_ent (int aent) |
252b5132 | 19869 | { |
252b5132 | 19870 | symbolS *symbolP; |
252b5132 RH |
19871 | |
19872 | symbolP = get_symbol (); | |
19873 | if (*input_line_pointer == ',') | |
f9419b05 | 19874 | ++input_line_pointer; |
252b5132 | 19875 | SKIP_WHITESPACE (); |
3882b010 | 19876 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 19877 | || *input_line_pointer == '-') |
874e8986 | 19878 | get_number (); |
252b5132 | 19879 | |
fd361982 | 19880 | if ((bfd_section_flags (now_seg) & SEC_CODE) == 0) |
1661c76c | 19881 | as_warn (_(".ent or .aent not in text section")); |
252b5132 RH |
19882 | |
19883 | if (!aent && cur_proc_ptr) | |
9a41af64 | 19884 | as_warn (_("missing .end")); |
252b5132 RH |
19885 | |
19886 | if (!aent) | |
19887 | { | |
7a621144 DJ |
19888 | /* This function needs its own .frame and .cprestore directives. */ |
19889 | mips_frame_reg_valid = 0; | |
19890 | mips_cprestore_valid = 0; | |
19891 | ||
252b5132 RH |
19892 | cur_proc_ptr = &cur_proc; |
19893 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
19894 | ||
9b2f1d35 | 19895 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 19896 | |
f9419b05 | 19897 | ++numprocs; |
ecb4347a DJ |
19898 | |
19899 | if (debug_type == DEBUG_STABS) | |
19900 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
19901 | S_GET_NAME (symbolP)); | |
252b5132 RH |
19902 | } |
19903 | ||
7c0fc524 MR |
19904 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
19905 | ||
252b5132 RH |
19906 | demand_empty_rest_of_line (); |
19907 | } | |
19908 | ||
19909 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 19910 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 19911 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 19912 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
19913 | symbol table (in the mdebug section). */ |
19914 | ||
19915 | static void | |
17a2f251 | 19916 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 19917 | { |
f3ded42a RS |
19918 | if (ECOFF_DEBUGGING) |
19919 | s_ignore (ignore); | |
19920 | else | |
ecb4347a DJ |
19921 | { |
19922 | long val; | |
252b5132 | 19923 | |
ecb4347a DJ |
19924 | if (cur_proc_ptr == (procS *) NULL) |
19925 | { | |
19926 | as_warn (_(".frame outside of .ent")); | |
19927 | demand_empty_rest_of_line (); | |
19928 | return; | |
19929 | } | |
252b5132 | 19930 | |
ecb4347a DJ |
19931 | cur_proc_ptr->frame_reg = tc_get_register (1); |
19932 | ||
19933 | SKIP_WHITESPACE (); | |
19934 | if (*input_line_pointer++ != ',' | |
19935 | || get_absolute_expression_and_terminator (&val) != ',') | |
19936 | { | |
1661c76c | 19937 | as_warn (_("bad .frame directive")); |
ecb4347a DJ |
19938 | --input_line_pointer; |
19939 | demand_empty_rest_of_line (); | |
19940 | return; | |
19941 | } | |
252b5132 | 19942 | |
ecb4347a DJ |
19943 | cur_proc_ptr->frame_offset = val; |
19944 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 19945 | |
252b5132 | 19946 | demand_empty_rest_of_line (); |
252b5132 | 19947 | } |
252b5132 RH |
19948 | } |
19949 | ||
bdaaa2e1 KH |
19950 | /* The .fmask and .mask directives. If the mdebug section is present |
19951 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 19952 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 19953 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
19954 | make reference to the ecoff symbol table (in the mdebug section). */ |
19955 | ||
19956 | static void | |
17a2f251 | 19957 | s_mips_mask (int reg_type) |
252b5132 | 19958 | { |
f3ded42a RS |
19959 | if (ECOFF_DEBUGGING) |
19960 | s_ignore (reg_type); | |
19961 | else | |
252b5132 | 19962 | { |
ecb4347a | 19963 | long mask, off; |
252b5132 | 19964 | |
ecb4347a DJ |
19965 | if (cur_proc_ptr == (procS *) NULL) |
19966 | { | |
19967 | as_warn (_(".mask/.fmask outside of .ent")); | |
19968 | demand_empty_rest_of_line (); | |
19969 | return; | |
19970 | } | |
252b5132 | 19971 | |
ecb4347a DJ |
19972 | if (get_absolute_expression_and_terminator (&mask) != ',') |
19973 | { | |
1661c76c | 19974 | as_warn (_("bad .mask/.fmask directive")); |
ecb4347a DJ |
19975 | --input_line_pointer; |
19976 | demand_empty_rest_of_line (); | |
19977 | return; | |
19978 | } | |
252b5132 | 19979 | |
ecb4347a DJ |
19980 | off = get_absolute_expression (); |
19981 | ||
19982 | if (reg_type == 'F') | |
19983 | { | |
19984 | cur_proc_ptr->fpreg_mask = mask; | |
19985 | cur_proc_ptr->fpreg_offset = off; | |
19986 | } | |
19987 | else | |
19988 | { | |
19989 | cur_proc_ptr->reg_mask = mask; | |
19990 | cur_proc_ptr->reg_offset = off; | |
19991 | } | |
19992 | ||
19993 | demand_empty_rest_of_line (); | |
252b5132 | 19994 | } |
252b5132 RH |
19995 | } |
19996 | ||
316f5878 RS |
19997 | /* A table describing all the processors gas knows about. Names are |
19998 | matched in the order listed. | |
e7af610e | 19999 | |
316f5878 RS |
20000 | To ease comparison, please keep this table in the same order as |
20001 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
20002 | static const struct mips_cpu_info mips_cpu_info_table[] = |
20003 | { | |
6f2117ba | 20004 | /* Entries for generic ISAs. */ |
d16afab6 RS |
20005 | { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 }, |
20006 | { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 }, | |
20007 | { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 }, | |
20008 | { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 }, | |
20009 | { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, | |
20010 | { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, | |
20011 | { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ae52f483 AB |
20012 | { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 }, |
20013 | { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
7361da2c | 20014 | { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 }, |
d16afab6 RS |
20015 | { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, |
20016 | { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
ae52f483 AB |
20017 | { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 }, |
20018 | { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 }, | |
7361da2c | 20019 | { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 }, |
316f5878 RS |
20020 | |
20021 | /* MIPS I */ | |
d16afab6 RS |
20022 | { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, |
20023 | { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 }, | |
20024 | { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
20025 | |
20026 | /* MIPS II */ | |
d16afab6 | 20027 | { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
20028 | |
20029 | /* MIPS III */ | |
d16afab6 RS |
20030 | { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, |
20031 | { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 }, | |
20032 | { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 }, | |
20033 | { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
20034 | { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
20035 | { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
20036 | { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
20037 | { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 }, | |
20038 | { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 }, | |
20039 | { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
20040 | { "orion", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
20041 | { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 }, | |
20042 | { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, | |
6f2117ba | 20043 | /* ST Microelectronics Loongson 2E and 2F cores. */ |
d16afab6 | 20044 | { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, |
8095d2f7 | 20045 | { "loongson2f", 0, ASE_LOONGSON_MMI, ISA_MIPS3, CPU_LOONGSON_2F }, |
316f5878 RS |
20046 | |
20047 | /* MIPS IV */ | |
d16afab6 RS |
20048 | { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, |
20049 | { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 }, | |
20050 | { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 }, | |
20051 | { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 }, | |
20052 | { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 }, | |
20053 | { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
20054 | { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 }, | |
20055 | { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 }, | |
20056 | { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
20057 | { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
20058 | { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
20059 | { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
20060 | { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
20061 | { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 }, | |
20062 | { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
20063 | |
20064 | /* MIPS 32 */ | |
d16afab6 RS |
20065 | { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 }, |
20066 | { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
20067 | { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
20068 | { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
ad3fea08 TS |
20069 | |
20070 | /* MIPS 32 Release 2 */ | |
d16afab6 RS |
20071 | { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20072 | { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20073 | { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20074 | { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20075 | { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20076 | { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20077 | { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20078 | { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20079 | { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
20080 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20081 | { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
20082 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20083 | { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20084 | { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20085 | { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20086 | { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 20087 | /* Deprecated forms of the above. */ |
d16afab6 RS |
20088 | { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20089 | { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 20090 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
d16afab6 RS |
20091 | { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20092 | { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20093 | { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20094 | { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 20095 | /* Deprecated forms of the above. */ |
d16afab6 RS |
20096 | { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20097 | { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 20098 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
d16afab6 RS |
20099 | { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20100 | { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20101 | { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20102 | { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 20103 | /* Deprecated forms of the above. */ |
d16afab6 RS |
20104 | { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20105 | { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 | 20106 | /* 34Kn is a 34kc without DSP. */ |
d16afab6 | 20107 | { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 20108 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
d16afab6 RS |
20109 | { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20110 | { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20111 | { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20112 | { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20113 | { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 20114 | /* Deprecated forms of the above. */ |
d16afab6 RS |
20115 | { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20116 | { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a | 20117 | /* 1004K cores are multiprocessor versions of the 34K. */ |
d16afab6 RS |
20118 | { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20119 | { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20120 | { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20121 | { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
6f2117ba | 20122 | /* interaptiv is the new name for 1004kf. */ |
77403ce9 | 20123 | { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
38bf472a MR |
20124 | { "interaptiv-mr2", 0, |
20125 | ASE_DSP | ASE_EVA | ASE_MT | ASE_MIPS16E2 | ASE_MIPS16E2_MT, | |
20126 | ISA_MIPS32R3, CPU_INTERAPTIV_MR2 }, | |
6f2117ba | 20127 | /* M5100 family. */ |
c6e5c03a RS |
20128 | { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, |
20129 | { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
bbaa46c0 | 20130 | /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */ |
134c0c8b | 20131 | { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 }, |
32b26a03 | 20132 | |
316f5878 | 20133 | /* MIPS 64 */ |
d16afab6 RS |
20134 | { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, |
20135 | { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 }, | |
20136 | { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
20137 | { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
ad3fea08 | 20138 | |
6f2117ba | 20139 | /* Broadcom SB-1 CPU core. */ |
d16afab6 | 20140 | { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
6f2117ba | 20141 | /* Broadcom SB-1A CPU core. */ |
d16afab6 | 20142 | { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
3739860c | 20143 | |
6f2117ba PH |
20144 | /* MIPS 64 Release 2. */ |
20145 | /* Loongson CPU core. */ | |
20146 | /* -march=loongson3a is an alias of -march=gs464 for compatibility. */ | |
bdc6c06e | 20147 | { "loongson3a", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT, |
ac8cb70f CX |
20148 | ISA_MIPS64R2, CPU_GS464 }, |
20149 | { "gs464", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT, | |
20150 | ISA_MIPS64R2, CPU_GS464 }, | |
bd782c07 CX |
20151 | { "gs464e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT |
20152 | | ASE_LOONGSON_EXT2, ISA_MIPS64R2, CPU_GS464E }, | |
9108bc33 CX |
20153 | { "gs264e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT |
20154 | | ASE_LOONGSON_EXT2 | ASE_MSA | ASE_MSA64, ISA_MIPS64R2, CPU_GS264E }, | |
ed163775 | 20155 | |
6f2117ba | 20156 | /* Cavium Networks Octeon CPU core. */ |
d16afab6 RS |
20157 | { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, |
20158 | { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, | |
20159 | { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, | |
2c629856 | 20160 | { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 }, |
967344c6 | 20161 | |
52b6b6b9 | 20162 | /* RMI Xlr */ |
d16afab6 | 20163 | { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, |
52b6b6b9 | 20164 | |
55a36193 MK |
20165 | /* Broadcom XLP. |
20166 | XLP is mostly like XLR, with the prominent exception that it is | |
20167 | MIPS64R2 rather than MIPS64. */ | |
d16afab6 | 20168 | { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, |
55a36193 | 20169 | |
6f2117ba | 20170 | /* MIPS 64 Release 6. */ |
bdc8beb4 MF |
20171 | { "i6400", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
20172 | { "i6500", 0, ASE_VIRT | ASE_MSA | ASE_CRC | ASE_GINV, | |
20173 | ISA_MIPS64R6, CPU_MIPS64R6}, | |
a4968f42 | 20174 | { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
7ef0d297 | 20175 | |
6f2117ba | 20176 | /* End marker. */ |
d16afab6 | 20177 | { NULL, 0, 0, 0, 0 } |
316f5878 | 20178 | }; |
e7af610e | 20179 | |
84ea6cf2 | 20180 | |
316f5878 RS |
20181 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
20182 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 20183 | |
316f5878 | 20184 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 20185 | |
b34976b6 | 20186 | static bfd_boolean |
17a2f251 | 20187 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
20188 | { |
20189 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
20190 | given++, canonical++; | |
20191 | ||
20192 | return ((*given == 0 && *canonical == 0) | |
20193 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
20194 | } | |
20195 | ||
20196 | ||
20197 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
20198 | CPU name. We've traditionally allowed a lot of variation here. | |
20199 | ||
20200 | Note: this function is shared between GCC and GAS. */ | |
20201 | ||
b34976b6 | 20202 | static bfd_boolean |
17a2f251 | 20203 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
20204 | { |
20205 | /* First see if the name matches exactly, or with a final "000" | |
20206 | turned into "k". */ | |
20207 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 20208 | return TRUE; |
316f5878 RS |
20209 | |
20210 | /* If not, try comparing based on numerical designation alone. | |
20211 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
20212 | if (TOLOWER (*given) == 'r') | |
20213 | given++; | |
20214 | if (!ISDIGIT (*given)) | |
b34976b6 | 20215 | return FALSE; |
316f5878 RS |
20216 | |
20217 | /* Skip over some well-known prefixes in the canonical name, | |
20218 | hoping to find a number there too. */ | |
20219 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
20220 | canonical += 2; | |
20221 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
20222 | canonical += 2; | |
20223 | else if (TOLOWER (canonical[0]) == 'r') | |
20224 | canonical += 1; | |
20225 | ||
20226 | return mips_strict_matching_cpu_name_p (canonical, given); | |
20227 | } | |
20228 | ||
20229 | ||
20230 | /* Parse an option that takes the name of a processor as its argument. | |
20231 | OPTION is the name of the option and CPU_STRING is the argument. | |
20232 | Return the corresponding processor enumeration if the CPU_STRING is | |
20233 | recognized, otherwise report an error and return null. | |
20234 | ||
20235 | A similar function exists in GCC. */ | |
e7af610e NC |
20236 | |
20237 | static const struct mips_cpu_info * | |
17a2f251 | 20238 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 20239 | { |
316f5878 | 20240 | const struct mips_cpu_info *p; |
e7af610e | 20241 | |
316f5878 RS |
20242 | /* 'from-abi' selects the most compatible architecture for the given |
20243 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
20244 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
20245 | version. Look first at the -mgp options, if given, otherwise base | |
20246 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 20247 | |
316f5878 RS |
20248 | Treat NO_ABI like the EABIs. One reason to do this is that the |
20249 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
20250 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
20251 | 'mips64', just as we did in the days before 'from-abi'. */ | |
20252 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
20253 | { | |
20254 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
20255 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
20256 | ||
20257 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
20258 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
20259 | ||
bad1aba3 | 20260 | if (file_mips_opts.gp >= 0) |
20261 | return mips_cpu_info_from_isa (file_mips_opts.gp == 32 | |
0b35dfee | 20262 | ? ISA_MIPS1 : ISA_MIPS3); |
316f5878 RS |
20263 | |
20264 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
20265 | ? ISA_MIPS3 | |
20266 | : ISA_MIPS1); | |
20267 | } | |
20268 | ||
20269 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
20270 | if (strcasecmp (cpu_string, "default") == 0) | |
20271 | return 0; | |
20272 | ||
20273 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
20274 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
20275 | return p; | |
20276 | ||
1661c76c | 20277 | as_bad (_("bad value (%s) for %s"), cpu_string, option); |
316f5878 | 20278 | return 0; |
e7af610e NC |
20279 | } |
20280 | ||
316f5878 RS |
20281 | /* Return the canonical processor information for ISA (a member of the |
20282 | ISA_MIPS* enumeration). */ | |
20283 | ||
e7af610e | 20284 | static const struct mips_cpu_info * |
17a2f251 | 20285 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
20286 | { |
20287 | int i; | |
20288 | ||
20289 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 20290 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 20291 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
20292 | return (&mips_cpu_info_table[i]); |
20293 | ||
e972090a | 20294 | return NULL; |
e7af610e | 20295 | } |
fef14a42 TS |
20296 | |
20297 | static const struct mips_cpu_info * | |
17a2f251 | 20298 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
20299 | { |
20300 | int i; | |
20301 | ||
20302 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
20303 | if (arch == mips_cpu_info_table[i].cpu) | |
20304 | return (&mips_cpu_info_table[i]); | |
20305 | ||
20306 | return NULL; | |
20307 | } | |
316f5878 RS |
20308 | \f |
20309 | static void | |
17a2f251 | 20310 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
20311 | { |
20312 | if (*first_p) | |
20313 | { | |
20314 | fprintf (stream, "%24s", ""); | |
20315 | *col_p = 24; | |
20316 | } | |
20317 | else | |
20318 | { | |
20319 | fprintf (stream, ", "); | |
20320 | *col_p += 2; | |
20321 | } | |
e7af610e | 20322 | |
316f5878 RS |
20323 | if (*col_p + strlen (string) > 72) |
20324 | { | |
20325 | fprintf (stream, "\n%24s", ""); | |
20326 | *col_p = 24; | |
20327 | } | |
20328 | ||
20329 | fprintf (stream, "%s", string); | |
20330 | *col_p += strlen (string); | |
20331 | ||
20332 | *first_p = 0; | |
20333 | } | |
20334 | ||
20335 | void | |
17a2f251 | 20336 | md_show_usage (FILE *stream) |
e7af610e | 20337 | { |
316f5878 RS |
20338 | int column, first; |
20339 | size_t i; | |
20340 | ||
20341 | fprintf (stream, _("\ | |
20342 | MIPS options:\n\ | |
316f5878 RS |
20343 | -EB generate big endian output\n\ |
20344 | -EL generate little endian output\n\ | |
20345 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
20346 | -G NUM allow referencing objects up to NUM bytes\n\ | |
20347 | implicitly with the gp register [default 8]\n")); | |
20348 | fprintf (stream, _("\ | |
20349 | -mips1 generate MIPS ISA I instructions\n\ | |
20350 | -mips2 generate MIPS ISA II instructions\n\ | |
20351 | -mips3 generate MIPS ISA III instructions\n\ | |
20352 | -mips4 generate MIPS ISA IV instructions\n\ | |
20353 | -mips5 generate MIPS ISA V instructions\n\ | |
20354 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 20355 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
ae52f483 AB |
20356 | -mips32r3 generate MIPS32 release 3 ISA instructions\n\ |
20357 | -mips32r5 generate MIPS32 release 5 ISA instructions\n\ | |
7361da2c | 20358 | -mips32r6 generate MIPS32 release 6 ISA instructions\n\ |
316f5878 | 20359 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 20360 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
ae52f483 AB |
20361 | -mips64r3 generate MIPS64 release 3 ISA instructions\n\ |
20362 | -mips64r5 generate MIPS64 release 5 ISA instructions\n\ | |
7361da2c | 20363 | -mips64r6 generate MIPS64 release 6 ISA instructions\n\ |
316f5878 RS |
20364 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
20365 | ||
20366 | first = 1; | |
e7af610e NC |
20367 | |
20368 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
20369 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
20370 | show (stream, "from-abi", &column, &first); | |
20371 | fputc ('\n', stream); | |
e7af610e | 20372 | |
316f5878 RS |
20373 | fprintf (stream, _("\ |
20374 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
20375 | -no-mCPU don't generate code specific to CPU.\n\ | |
20376 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
20377 | ||
20378 | first = 1; | |
20379 | ||
20380 | show (stream, "3900", &column, &first); | |
20381 | show (stream, "4010", &column, &first); | |
20382 | show (stream, "4100", &column, &first); | |
20383 | show (stream, "4650", &column, &first); | |
20384 | fputc ('\n', stream); | |
20385 | ||
20386 | fprintf (stream, _("\ | |
20387 | -mips16 generate mips16 instructions\n\ | |
20388 | -no-mips16 do not generate mips16 instructions\n")); | |
20389 | fprintf (stream, _("\ | |
f866b262 MR |
20390 | -mmips16e2 generate MIPS16e2 instructions\n\ |
20391 | -mno-mips16e2 do not generate MIPS16e2 instructions\n")); | |
20392 | fprintf (stream, _("\ | |
df58fc94 RS |
20393 | -mmicromips generate microMIPS instructions\n\ |
20394 | -mno-micromips do not generate microMIPS instructions\n")); | |
20395 | fprintf (stream, _("\ | |
e16bfa71 | 20396 | -msmartmips generate smartmips instructions\n\ |
3739860c | 20397 | -mno-smartmips do not generate smartmips instructions\n")); |
e16bfa71 | 20398 | fprintf (stream, _("\ |
74cd071d CF |
20399 | -mdsp generate DSP instructions\n\ |
20400 | -mno-dsp do not generate DSP instructions\n")); | |
20401 | fprintf (stream, _("\ | |
8b082fb1 TS |
20402 | -mdspr2 generate DSP R2 instructions\n\ |
20403 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
20404 | fprintf (stream, _("\ | |
8f4f9071 MF |
20405 | -mdspr3 generate DSP R3 instructions\n\ |
20406 | -mno-dspr3 do not generate DSP R3 instructions\n")); | |
20407 | fprintf (stream, _("\ | |
ef2e4d86 CF |
20408 | -mmt generate MT instructions\n\ |
20409 | -mno-mt do not generate MT instructions\n")); | |
20410 | fprintf (stream, _("\ | |
dec0624d MR |
20411 | -mmcu generate MCU instructions\n\ |
20412 | -mno-mcu do not generate MCU instructions\n")); | |
20413 | fprintf (stream, _("\ | |
56d438b1 CF |
20414 | -mmsa generate MSA instructions\n\ |
20415 | -mno-msa do not generate MSA instructions\n")); | |
20416 | fprintf (stream, _("\ | |
7d64c587 AB |
20417 | -mxpa generate eXtended Physical Address (XPA) instructions\n\ |
20418 | -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n")); | |
20419 | fprintf (stream, _("\ | |
b015e599 AP |
20420 | -mvirt generate Virtualization instructions\n\ |
20421 | -mno-virt do not generate Virtualization instructions\n")); | |
20422 | fprintf (stream, _("\ | |
730c3174 SE |
20423 | -mcrc generate CRC instructions\n\ |
20424 | -mno-crc do not generate CRC instructions\n")); | |
20425 | fprintf (stream, _("\ | |
6f20c942 FS |
20426 | -mginv generate Global INValidate (GINV) instructions\n\ |
20427 | -mno-ginv do not generate Global INValidate instructions\n")); | |
20428 | fprintf (stream, _("\ | |
8095d2f7 CX |
20429 | -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\ |
20430 | -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n")); | |
20431 | fprintf (stream, _("\ | |
716c08de CX |
20432 | -mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\ |
20433 | -mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n")); | |
20434 | fprintf (stream, _("\ | |
bdc6c06e CX |
20435 | -mloongson-ext generate Loongson EXTensions (EXT) instructions\n\ |
20436 | -mno-loongson-ext do not generate Loongson EXTensions Instructions\n")); | |
20437 | fprintf (stream, _("\ | |
a693765e CX |
20438 | -mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\ |
20439 | -mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n")); | |
20440 | fprintf (stream, _("\ | |
833794fc MR |
20441 | -minsn32 only generate 32-bit microMIPS instructions\n\ |
20442 | -mno-insn32 generate all microMIPS instructions\n")); | |
6f2117ba PH |
20443 | #if DEFAULT_MIPS_FIX_LOONGSON3_LLSC |
20444 | fprintf (stream, _("\ | |
20445 | -mfix-loongson3-llsc work around Loongson3 LL/SC errata, default\n\ | |
20446 | -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n")); | |
20447 | #else | |
20448 | fprintf (stream, _("\ | |
20449 | -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\ | |
20450 | -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata, default\n")); | |
20451 | #endif | |
833794fc | 20452 | fprintf (stream, _("\ |
c67a084a NC |
20453 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
20454 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
6f2117ba PH |
20455 | -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\ |
20456 | -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n\ | |
d766e8ec | 20457 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 20458 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 20459 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 20460 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
27c634e0 | 20461 | -mfix-r5900 work around R5900 short loop errata\n\ |
316f5878 RS |
20462 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
20463 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 20464 | -msym32 assume all symbols have 32-bit values\n\ |
092a534f MR |
20465 | -O0 do not remove unneeded NOPs, do not swap branches\n\ |
20466 | -O, -O1 remove unneeded NOPs, do not swap branches\n\ | |
20467 | -O2 remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
20468 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
20469 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
20470 | fprintf (stream, _("\ |
20471 | -mhard-float allow floating-point instructions\n\ | |
20472 | -msoft-float do not allow floating-point instructions\n\ | |
20473 | -msingle-float only allow 32-bit floating-point operations\n\ | |
20474 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
3bf0dbfb | 20475 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
ba92f887 | 20476 | --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\ |
8b10b0b3 MR |
20477 | -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\ |
20478 | -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\ | |
ba92f887 MR |
20479 | -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n")); |
20480 | ||
20481 | first = 1; | |
20482 | ||
20483 | show (stream, "legacy", &column, &first); | |
20484 | show (stream, "2008", &column, &first); | |
20485 | ||
20486 | fputc ('\n', stream); | |
20487 | ||
316f5878 RS |
20488 | fprintf (stream, _("\ |
20489 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 20490 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 20491 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 20492 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 20493 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 20494 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 20495 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 20496 | position dependent (non shared) code\n\ |
316f5878 RS |
20497 | -mabi=ABI create ABI conformant object file for:\n")); |
20498 | ||
20499 | first = 1; | |
20500 | ||
20501 | show (stream, "32", &column, &first); | |
20502 | show (stream, "o64", &column, &first); | |
20503 | show (stream, "n32", &column, &first); | |
20504 | show (stream, "64", &column, &first); | |
20505 | show (stream, "eabi", &column, &first); | |
20506 | ||
20507 | fputc ('\n', stream); | |
20508 | ||
20509 | fprintf (stream, _("\ | |
b4f6242e MR |
20510 | -32 create o32 ABI object file%s\n"), |
20511 | MIPS_DEFAULT_ABI == O32_ABI ? _(" (default)") : ""); | |
20512 | fprintf (stream, _("\ | |
20513 | -n32 create n32 ABI object file%s\n"), | |
20514 | MIPS_DEFAULT_ABI == N32_ABI ? _(" (default)") : ""); | |
20515 | fprintf (stream, _("\ | |
20516 | -64 create 64 ABI object file%s\n"), | |
20517 | MIPS_DEFAULT_ABI == N64_ABI ? _(" (default)") : ""); | |
e7af610e | 20518 | } |
14e777e0 | 20519 | |
1575952e | 20520 | #ifdef TE_IRIX |
14e777e0 | 20521 | enum dwarf2_format |
413a266c | 20522 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 20523 | { |
369943fe | 20524 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 20525 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
20526 | else |
20527 | return dwarf2_format_32bit; | |
20528 | } | |
1575952e | 20529 | #endif |
73369e65 EC |
20530 | |
20531 | int | |
20532 | mips_dwarf2_addr_size (void) | |
20533 | { | |
6b6b3450 | 20534 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 20535 | return 8; |
73369e65 EC |
20536 | else |
20537 | return 4; | |
20538 | } | |
5862107c EC |
20539 | |
20540 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
20541 | void | |
20542 | mips_cfi_frame_initial_instructions (void) | |
20543 | { | |
20544 | cfi_add_CFA_def_cfa_register (SP); | |
20545 | } | |
20546 | ||
707bfff6 TS |
20547 | int |
20548 | tc_mips_regname_to_dw2regnum (char *regname) | |
20549 | { | |
20550 | unsigned int regnum = -1; | |
20551 | unsigned int reg; | |
20552 | ||
20553 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
20554 | regnum = reg; | |
20555 | ||
20556 | return regnum; | |
20557 | } | |
263b2574 | 20558 | |
20559 | /* Implement CONVERT_SYMBOLIC_ATTRIBUTE. | |
20560 | Given a symbolic attribute NAME, return the proper integer value. | |
20561 | Returns -1 if the attribute is not known. */ | |
20562 | ||
20563 | int | |
20564 | mips_convert_symbolic_attribute (const char *name) | |
20565 | { | |
20566 | static const struct | |
20567 | { | |
20568 | const char * name; | |
20569 | const int tag; | |
20570 | } | |
20571 | attribute_table[] = | |
20572 | { | |
20573 | #define T(tag) {#tag, tag} | |
20574 | T (Tag_GNU_MIPS_ABI_FP), | |
20575 | T (Tag_GNU_MIPS_ABI_MSA), | |
20576 | #undef T | |
20577 | }; | |
20578 | unsigned int i; | |
20579 | ||
20580 | if (name == NULL) | |
20581 | return -1; | |
20582 | ||
20583 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) | |
20584 | if (streq (name, attribute_table[i].name)) | |
20585 | return attribute_table[i].tag; | |
20586 | ||
20587 | return -1; | |
20588 | } | |
fd5c94ab RS |
20589 | |
20590 | void | |
20591 | md_mips_end (void) | |
20592 | { | |
351cdf24 MF |
20593 | int fpabi = Val_GNU_MIPS_ABI_FP_ANY; |
20594 | ||
fd5c94ab RS |
20595 | mips_emit_delays (); |
20596 | if (cur_proc_ptr) | |
20597 | as_warn (_("missing .end at end of assembly")); | |
919731af | 20598 | |
20599 | /* Just in case no code was emitted, do the consistency check. */ | |
20600 | file_mips_check_options (); | |
351cdf24 MF |
20601 | |
20602 | /* Set a floating-point ABI if the user did not. */ | |
20603 | if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP)) | |
20604 | { | |
20605 | /* Perform consistency checks on the floating-point ABI. */ | |
20606 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
20607 | Tag_GNU_MIPS_ABI_FP); | |
20608 | if (fpabi != Val_GNU_MIPS_ABI_FP_ANY) | |
20609 | check_fpabi (fpabi); | |
20610 | } | |
20611 | else | |
20612 | { | |
20613 | /* Soft-float gets precedence over single-float, the two options should | |
20614 | not be used together so this should not matter. */ | |
20615 | if (file_mips_opts.soft_float == 1) | |
20616 | fpabi = Val_GNU_MIPS_ABI_FP_SOFT; | |
20617 | /* Single-float gets precedence over all double_float cases. */ | |
20618 | else if (file_mips_opts.single_float == 1) | |
20619 | fpabi = Val_GNU_MIPS_ABI_FP_SINGLE; | |
20620 | else | |
20621 | { | |
20622 | switch (file_mips_opts.fp) | |
20623 | { | |
20624 | case 32: | |
20625 | if (file_mips_opts.gp == 32) | |
20626 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; | |
20627 | break; | |
20628 | case 0: | |
20629 | fpabi = Val_GNU_MIPS_ABI_FP_XX; | |
20630 | break; | |
20631 | case 64: | |
20632 | if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg) | |
20633 | fpabi = Val_GNU_MIPS_ABI_FP_64A; | |
20634 | else if (file_mips_opts.gp == 32) | |
20635 | fpabi = Val_GNU_MIPS_ABI_FP_64; | |
20636 | else | |
20637 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; | |
20638 | break; | |
20639 | } | |
20640 | } | |
20641 | ||
20642 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
20643 | Tag_GNU_MIPS_ABI_FP, fpabi); | |
20644 | } | |
fd5c94ab | 20645 | } |
2f0c68f2 CM |
20646 | |
20647 | /* Returns the relocation type required for a particular CFI encoding. */ | |
20648 | ||
20649 | bfd_reloc_code_real_type | |
20650 | mips_cfi_reloc_for_encoding (int encoding) | |
20651 | { | |
20652 | if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel)) | |
20653 | return BFD_RELOC_32_PCREL; | |
20654 | else return BFD_RELOC_NONE; | |
20655 | } |