Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
c67a084a NC |
3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
4 | Free Software Foundation, Inc. | |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
741fe287 | 93 | #define ATREG 1 |
252b5132 RH |
94 | #define TREG 24 |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
741fe287 MR |
105 | #define AT mips_opts.at |
106 | ||
252b5132 RH |
107 | /* Allow override of standard little-endian ECOFF format. */ |
108 | ||
109 | #ifndef ECOFF_LITTLE_FORMAT | |
110 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
111 | #endif | |
112 | ||
113 | extern int target_big_endian; | |
114 | ||
252b5132 | 115 | /* The name of the readonly data section. */ |
4d0d148d | 116 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 117 | ? ".rdata" \ |
056350c6 NC |
118 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
119 | ? ".rdata" \ | |
252b5132 RH |
120 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
121 | ? ".rodata" \ | |
122 | : (abort (), "")) | |
123 | ||
47e39b9d RS |
124 | /* Information about an instruction, including its format, operands |
125 | and fixups. */ | |
126 | struct mips_cl_insn | |
127 | { | |
128 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
129 | const struct mips_opcode *insn_mo; | |
130 | ||
131 | /* True if this is a mips16 instruction and if we want the extended | |
132 | form of INSN_MO. */ | |
133 | bfd_boolean use_extend; | |
134 | ||
135 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
136 | unsigned short extend; | |
137 | ||
138 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
139 | a copy of INSN_MO->match with the operands filled in. */ | |
140 | unsigned long insn_opcode; | |
141 | ||
142 | /* The frag that contains the instruction. */ | |
143 | struct frag *frag; | |
144 | ||
145 | /* The offset into FRAG of the first instruction byte. */ | |
146 | long where; | |
147 | ||
148 | /* The relocs associated with the instruction, if any. */ | |
149 | fixS *fixp[3]; | |
150 | ||
a38419a5 RS |
151 | /* True if this entry cannot be moved from its current position. */ |
152 | unsigned int fixed_p : 1; | |
47e39b9d | 153 | |
708587a4 | 154 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
155 | unsigned int noreorder_p : 1; |
156 | ||
2fa15973 RS |
157 | /* True for mips16 instructions that jump to an absolute address. */ |
158 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
159 | |
160 | /* True if this instruction is complete. */ | |
161 | unsigned int complete_p : 1; | |
47e39b9d RS |
162 | }; |
163 | ||
a325df1d TS |
164 | /* The ABI to use. */ |
165 | enum mips_abi_level | |
166 | { | |
167 | NO_ABI = 0, | |
168 | O32_ABI, | |
169 | O64_ABI, | |
170 | N32_ABI, | |
171 | N64_ABI, | |
172 | EABI_ABI | |
173 | }; | |
174 | ||
175 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 176 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 177 | |
143d77c5 EC |
178 | /* Whether or not we have code that can call pic code. */ |
179 | int mips_abicalls = FALSE; | |
180 | ||
aa6975fb ILT |
181 | /* Whether or not we have code which can be put into a shared |
182 | library. */ | |
183 | static bfd_boolean mips_in_shared = TRUE; | |
184 | ||
252b5132 RH |
185 | /* This is the set of options which may be modified by the .set |
186 | pseudo-op. We use a struct so that .set push and .set pop are more | |
187 | reliable. */ | |
188 | ||
e972090a NC |
189 | struct mips_set_options |
190 | { | |
252b5132 RH |
191 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
192 | if it has not been initialized. Changed by `.set mipsN', and the | |
193 | -mipsN command line option, and the default CPU. */ | |
194 | int isa; | |
1f25f5d3 CD |
195 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
196 | if they have not been initialized. Changed by `.set <asename>', by | |
197 | command line options, and based on the default architecture. */ | |
198 | int ase_mips3d; | |
deec1734 | 199 | int ase_mdmx; |
e16bfa71 | 200 | int ase_smartmips; |
74cd071d | 201 | int ase_dsp; |
8b082fb1 | 202 | int ase_dspr2; |
ef2e4d86 | 203 | int ase_mt; |
252b5132 RH |
204 | /* Whether we are assembling for the mips16 processor. 0 if we are |
205 | not, 1 if we are, and -1 if the value has not been initialized. | |
206 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
207 | -nomips16 command line options, and the default CPU. */ | |
208 | int mips16; | |
209 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
210 | reorder' and `.set noreorder'. */ | |
211 | int noreorder; | |
741fe287 MR |
212 | /* Non-zero if we should not permit the register designated "assembler |
213 | temporary" to be used in instructions. The value is the register | |
214 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
215 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
216 | unsigned int at; | |
252b5132 RH |
217 | /* Non-zero if we should warn when a macro instruction expands into |
218 | more than one machine instruction. Changed by `.set nomacro' and | |
219 | `.set macro'. */ | |
220 | int warn_about_macros; | |
221 | /* Non-zero if we should not move instructions. Changed by `.set | |
222 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
223 | int nomove; | |
224 | /* Non-zero if we should not optimize branches by moving the target | |
225 | of the branch into the delay slot. Actually, we don't perform | |
226 | this optimization anyhow. Changed by `.set bopt' and `.set | |
227 | nobopt'. */ | |
228 | int nobopt; | |
229 | /* Non-zero if we should not autoextend mips16 instructions. | |
230 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
231 | int noautoextend; | |
a325df1d TS |
232 | /* Restrict general purpose registers and floating point registers |
233 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
234 | is passed but can changed if the assembler code uses .set mipsN. */ | |
235 | int gp32; | |
236 | int fp32; | |
fef14a42 TS |
237 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
238 | command line option, and the default CPU. */ | |
239 | int arch; | |
aed1a261 RS |
240 | /* True if ".set sym32" is in effect. */ |
241 | bfd_boolean sym32; | |
037b32b9 AN |
242 | /* True if floating-point operations are not allowed. Changed by .set |
243 | softfloat or .set hardfloat, by command line options -msoft-float or | |
244 | -mhard-float. The default is false. */ | |
245 | bfd_boolean soft_float; | |
246 | ||
247 | /* True if only single-precision floating-point operations are allowed. | |
248 | Changed by .set singlefloat or .set doublefloat, command-line options | |
249 | -msingle-float or -mdouble-float. The default is false. */ | |
250 | bfd_boolean single_float; | |
252b5132 RH |
251 | }; |
252 | ||
037b32b9 AN |
253 | /* This is the struct we use to hold the current set of options. Note |
254 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
255 | -1 to indicate that they have not been initialized. */ | |
256 | ||
a325df1d | 257 | /* True if -mgp32 was passed. */ |
a8e8e863 | 258 | static int file_mips_gp32 = -1; |
a325df1d TS |
259 | |
260 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 261 | static int file_mips_fp32 = -1; |
a325df1d | 262 | |
037b32b9 AN |
263 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
264 | static int file_mips_soft_float = 0; | |
265 | ||
266 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
267 | static int file_mips_single_float = 0; | |
252b5132 | 268 | |
e972090a NC |
269 | static struct mips_set_options mips_opts = |
270 | { | |
037b32b9 AN |
271 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
272 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
273 | /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG, | |
274 | /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, | |
275 | /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, | |
276 | /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 277 | }; |
252b5132 RH |
278 | |
279 | /* These variables are filled in with the masks of registers used. | |
280 | The object format code reads them and puts them in the appropriate | |
281 | place. */ | |
282 | unsigned long mips_gprmask; | |
283 | unsigned long mips_cprmask[4]; | |
284 | ||
285 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 286 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 287 | |
738f4d98 | 288 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
289 | static int file_ase_mips16; |
290 | ||
3994f87e TS |
291 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
292 | || mips_opts.isa == ISA_MIPS32R2 \ | |
293 | || mips_opts.isa == ISA_MIPS64 \ | |
294 | || mips_opts.isa == ISA_MIPS64R2) | |
295 | ||
b12dd2e4 CF |
296 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
297 | #ifdef TE_IRIX | |
1180b5a4 | 298 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 299 | #else |
1180b5a4 RS |
300 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
301 | because there's no place for any addend, the only acceptable | |
302 | expression is a bare symbol. */ | |
303 | #define MIPS_JALR_HINT_P(EXPR) \ | |
304 | (!HAVE_IN_PLACE_ADDENDS \ | |
305 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
306 | #endif |
307 | ||
1f25f5d3 CD |
308 | /* True if -mips3d was passed or implied by arguments passed on the |
309 | command line (e.g., by -march). */ | |
310 | static int file_ase_mips3d; | |
311 | ||
deec1734 CD |
312 | /* True if -mdmx was passed or implied by arguments passed on the |
313 | command line (e.g., by -march). */ | |
314 | static int file_ase_mdmx; | |
315 | ||
e16bfa71 TS |
316 | /* True if -msmartmips was passed or implied by arguments passed on the |
317 | command line (e.g., by -march). */ | |
318 | static int file_ase_smartmips; | |
319 | ||
ad3fea08 TS |
320 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
321 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 322 | |
74cd071d CF |
323 | /* True if -mdsp was passed or implied by arguments passed on the |
324 | command line (e.g., by -march). */ | |
325 | static int file_ase_dsp; | |
326 | ||
ad3fea08 TS |
327 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
328 | || mips_opts.isa == ISA_MIPS64R2) | |
329 | ||
65263ce3 TS |
330 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
331 | ||
8b082fb1 TS |
332 | /* True if -mdspr2 was passed or implied by arguments passed on the |
333 | command line (e.g., by -march). */ | |
334 | static int file_ase_dspr2; | |
335 | ||
336 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
337 | || mips_opts.isa == ISA_MIPS64R2) | |
338 | ||
ef2e4d86 CF |
339 | /* True if -mmt was passed or implied by arguments passed on the |
340 | command line (e.g., by -march). */ | |
341 | static int file_ase_mt; | |
342 | ||
ad3fea08 TS |
343 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
344 | || mips_opts.isa == ISA_MIPS64R2) | |
345 | ||
ec68c924 | 346 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 347 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 348 | static const char *mips_arch_string; |
ec68c924 EC |
349 | |
350 | /* The argument of the -mtune= flag. The architecture for which we | |
351 | are optimizing. */ | |
352 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 353 | static const char *mips_tune_string; |
ec68c924 | 354 | |
316f5878 | 355 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
356 | static int mips_32bitmode = 0; |
357 | ||
316f5878 RS |
358 | /* True if the given ABI requires 32-bit registers. */ |
359 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
360 | ||
361 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
362 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
363 | ((ABI) == N32_ABI \ | |
364 | || (ABI) == N64_ABI \ | |
316f5878 RS |
365 | || (ABI) == O64_ABI) |
366 | ||
ad3fea08 | 367 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
368 | #define ISA_HAS_64BIT_REGS(ISA) \ |
369 | ((ISA) == ISA_MIPS3 \ | |
370 | || (ISA) == ISA_MIPS4 \ | |
371 | || (ISA) == ISA_MIPS5 \ | |
372 | || (ISA) == ISA_MIPS64 \ | |
373 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 374 | |
ad3fea08 TS |
375 | /* Return true if ISA supports 64 bit wide float registers. */ |
376 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
377 | ((ISA) == ISA_MIPS3 \ | |
378 | || (ISA) == ISA_MIPS4 \ | |
379 | || (ISA) == ISA_MIPS5 \ | |
380 | || (ISA) == ISA_MIPS32R2 \ | |
381 | || (ISA) == ISA_MIPS64 \ | |
382 | || (ISA) == ISA_MIPS64R2) | |
383 | ||
af7ee8bf CD |
384 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
385 | instructions. */ | |
707bfff6 TS |
386 | #define ISA_HAS_DROR(ISA) \ |
387 | ((ISA) == ISA_MIPS64R2) | |
af7ee8bf CD |
388 | |
389 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
390 | instructions. */ | |
707bfff6 TS |
391 | #define ISA_HAS_ROR(ISA) \ |
392 | ((ISA) == ISA_MIPS32R2 \ | |
393 | || (ISA) == ISA_MIPS64R2 \ | |
394 | || mips_opts.ase_smartmips) | |
395 | ||
7455baf8 TS |
396 | /* Return true if ISA supports single-precision floats in odd registers. */ |
397 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
398 | ((ISA) == ISA_MIPS32 \ | |
399 | || (ISA) == ISA_MIPS32R2 \ | |
400 | || (ISA) == ISA_MIPS64 \ | |
401 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 402 | |
ad3fea08 TS |
403 | /* Return true if ISA supports move to/from high part of a 64-bit |
404 | floating-point register. */ | |
405 | #define ISA_HAS_MXHC1(ISA) \ | |
406 | ((ISA) == ISA_MIPS32R2 \ | |
407 | || (ISA) == ISA_MIPS64R2) | |
408 | ||
e013f690 | 409 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 410 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 411 | |
e013f690 | 412 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 413 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 414 | |
ad3fea08 TS |
415 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
416 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 417 | |
316f5878 | 418 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 419 | |
316f5878 | 420 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 421 | |
3b91255e RS |
422 | /* True if relocations are stored in-place. */ |
423 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
424 | ||
aed1a261 RS |
425 | /* The ABI-derived address size. */ |
426 | #define HAVE_64BIT_ADDRESSES \ | |
427 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
428 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 429 | |
aed1a261 RS |
430 | /* The size of symbolic constants (i.e., expressions of the form |
431 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
432 | #define HAVE_32BIT_SYMBOLS \ | |
433 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
434 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 435 | |
b7c7d6c1 TS |
436 | /* Addresses are loaded in different ways, depending on the address size |
437 | in use. The n32 ABI Documentation also mandates the use of additions | |
438 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 439 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 440 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
441 | |
442 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 443 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
444 | |
445 | #define ADDRESS_LOAD_INSN \ | |
446 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
447 | ||
448 | #define ADDRESS_STORE_INSN \ | |
449 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
450 | ||
a4672219 | 451 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
452 | #define CPU_HAS_MIPS16(cpu) \ |
453 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
454 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 455 | |
60b63b72 RS |
456 | /* True if CPU has a dror instruction. */ |
457 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
458 | ||
459 | /* True if CPU has a ror instruction. */ | |
460 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
461 | ||
dd3cbb7e NC |
462 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
463 | #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON) | |
464 | ||
b19e8a9b AN |
465 | /* True if CPU does not implement the all the coprocessor insns. For these |
466 | CPUs only those COP insns are accepted that are explicitly marked to be | |
467 | available on the CPU. ISA membership for COP insns is ignored. */ | |
468 | #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON) | |
469 | ||
c8978940 CD |
470 | /* True if mflo and mfhi can be immediately followed by instructions |
471 | which write to the HI and LO registers. | |
472 | ||
473 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
474 | (at least) two instructions between the reads of HI/LO and | |
475 | instructions which write them, and later ISAs do not. Contradicting | |
476 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
477 | the UM for the NEC Vr5000) document needing the instructions between | |
478 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
479 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
480 | earlier-ISA CPUs for which CPU documentation declares that the | |
481 | instructions are really interlocked. */ | |
482 | #define hilo_interlocks \ | |
483 | (mips_opts.isa == ISA_MIPS32 \ | |
484 | || mips_opts.isa == ISA_MIPS32R2 \ | |
485 | || mips_opts.isa == ISA_MIPS64 \ | |
486 | || mips_opts.isa == ISA_MIPS64R2 \ | |
487 | || mips_opts.arch == CPU_R4010 \ | |
488 | || mips_opts.arch == CPU_R10000 \ | |
489 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
490 | || mips_opts.arch == CPU_R14000 \ |
491 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 492 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 CD |
493 | || mips_opts.arch == CPU_VR5500 \ |
494 | ) | |
252b5132 RH |
495 | |
496 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
497 | from the GPRs after they are loaded from memory, and thus does not |
498 | require nops to be inserted. This applies to instructions marked | |
499 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
500 | level I. */ | |
252b5132 | 501 | #define gpr_interlocks \ |
e7af610e | 502 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 503 | || mips_opts.arch == CPU_R3900) |
252b5132 | 504 | |
81912461 ILT |
505 | /* Whether the processor uses hardware interlocks to avoid delays |
506 | required by coprocessor instructions, and thus does not require | |
507 | nops to be inserted. This applies to instructions marked | |
508 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
509 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
510 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
511 | levels I, II, and III. */ | |
bdaaa2e1 | 512 | /* Itbl support may require additional care here. */ |
81912461 ILT |
513 | #define cop_interlocks \ |
514 | ((mips_opts.isa != ISA_MIPS1 \ | |
515 | && mips_opts.isa != ISA_MIPS2 \ | |
516 | && mips_opts.isa != ISA_MIPS3) \ | |
517 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
518 | ) |
519 | ||
520 | /* Whether the processor uses hardware interlocks to protect reads | |
521 | from coprocessor registers after they are loaded from memory, and | |
522 | thus does not require nops to be inserted. This applies to | |
523 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
524 | requires at MIPS ISA level I. */ | |
525 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 526 | |
6b76fefe CM |
527 | /* Is this a mfhi or mflo instruction? */ |
528 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
529 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
530 | ||
531 | /* Returns true for a (non floating-point) coprocessor instruction. Reading | |
532 | or writing the condition code is only possible on the coprocessors and | |
533 | these insns are not marked with INSN_COP. Thus for these insns use the | |
a242dc0d | 534 | condition-code flags. */ |
b19e8a9b AN |
535 | #define COP_INSN(PINFO) \ |
536 | (PINFO != INSN_MACRO \ | |
a242dc0d AN |
537 | && ((PINFO) & (FP_S | FP_D)) == 0 \ |
538 | && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE))) | |
6b76fefe | 539 | |
252b5132 RH |
540 | /* MIPS PIC level. */ |
541 | ||
a161fe53 | 542 | enum mips_pic_level mips_pic; |
252b5132 | 543 | |
c9914766 | 544 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 545 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 546 | static int mips_big_got = 0; |
252b5132 RH |
547 | |
548 | /* 1 if trap instructions should used for overflow rather than break | |
549 | instructions. */ | |
c9914766 | 550 | static int mips_trap = 0; |
252b5132 | 551 | |
119d663a | 552 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 553 | by assembling two single width halves into two single width floating |
119d663a NC |
554 | point registers which just happen to alias the double width destination |
555 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 556 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
557 | automatically at assemble time. */ |
558 | static int mips_disable_float_construction; | |
559 | ||
252b5132 RH |
560 | /* Non-zero if any .set noreorder directives were used. */ |
561 | ||
562 | static int mips_any_noreorder; | |
563 | ||
6b76fefe CM |
564 | /* Non-zero if nops should be inserted when the register referenced in |
565 | an mfhi/mflo instruction is read in the next two instructions. */ | |
566 | static int mips_7000_hilo_fix; | |
567 | ||
02ffd3e4 | 568 | /* The size of objects in the small data section. */ |
156c2f8b | 569 | static unsigned int g_switch_value = 8; |
252b5132 RH |
570 | /* Whether the -G option was used. */ |
571 | static int g_switch_seen = 0; | |
572 | ||
573 | #define N_RMASK 0xc4 | |
574 | #define N_VFP 0xd4 | |
575 | ||
576 | /* If we can determine in advance that GP optimization won't be | |
577 | possible, we can skip the relaxation stuff that tries to produce | |
578 | GP-relative references. This makes delay slot optimization work | |
579 | better. | |
580 | ||
581 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
582 | gcc output. It needs to guess right for gcc, otherwise gcc |
583 | will put what it thinks is a GP-relative instruction in a branch | |
584 | delay slot. | |
252b5132 RH |
585 | |
586 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
587 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 588 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
589 | |
590 | /* handle of the OPCODE hash table */ | |
591 | static struct hash_control *op_hash = NULL; | |
592 | ||
593 | /* The opcode hash table we use for the mips16. */ | |
594 | static struct hash_control *mips16_op_hash = NULL; | |
595 | ||
596 | /* This array holds the chars that always start a comment. If the | |
597 | pre-processor is disabled, these aren't very useful */ | |
598 | const char comment_chars[] = "#"; | |
599 | ||
600 | /* This array holds the chars that only start a comment at the beginning of | |
601 | a line. If the line seems to have the form '# 123 filename' | |
602 | .line and .file directives will appear in the pre-processed output */ | |
603 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
604 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 605 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
606 | /* Also note that C style comments are always supported. */ |
607 | const char line_comment_chars[] = "#"; | |
608 | ||
bdaaa2e1 | 609 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 610 | const char line_separator_chars[] = ";"; |
252b5132 RH |
611 | |
612 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
613 | const char EXP_CHARS[] = "eE"; | |
614 | ||
615 | /* Chars that mean this number is a floating point constant */ | |
616 | /* As in 0f12.456 */ | |
617 | /* or 0d1.2345e12 */ | |
618 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
619 | ||
620 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
621 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
622 | but nothing is ideal around here. | |
623 | */ | |
624 | ||
625 | static char *insn_error; | |
626 | ||
627 | static int auto_align = 1; | |
628 | ||
629 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
630 | offset in the stack frame from which to restore the $gp register. | |
631 | This is set by the .cprestore pseudo-op, and saved in this | |
632 | variable. */ | |
633 | static offsetT mips_cprestore_offset = -1; | |
634 | ||
67c1ffbe | 635 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 636 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 637 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
638 | static offsetT mips_cpreturn_offset = -1; |
639 | static int mips_cpreturn_register = -1; | |
640 | static int mips_gp_register = GP; | |
def2e0dd | 641 | static int mips_gprel_offset = 0; |
6478892d | 642 | |
7a621144 DJ |
643 | /* Whether mips_cprestore_offset has been set in the current function |
644 | (or whether it has already been warned about, if not). */ | |
645 | static int mips_cprestore_valid = 0; | |
646 | ||
252b5132 RH |
647 | /* This is the register which holds the stack frame, as set by the |
648 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
649 | static int mips_frame_reg = SP; | |
650 | ||
7a621144 DJ |
651 | /* Whether mips_frame_reg has been set in the current function |
652 | (or whether it has already been warned about, if not). */ | |
653 | static int mips_frame_reg_valid = 0; | |
654 | ||
252b5132 RH |
655 | /* To output NOP instructions correctly, we need to keep information |
656 | about the previous two instructions. */ | |
657 | ||
658 | /* Whether we are optimizing. The default value of 2 means to remove | |
659 | unneeded NOPs and swap branch instructions when possible. A value | |
660 | of 1 means to not swap branches. A value of 0 means to always | |
661 | insert NOPs. */ | |
662 | static int mips_optimize = 2; | |
663 | ||
664 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
665 | equivalent to seeing no -g option at all. */ | |
666 | static int mips_debug = 0; | |
667 | ||
7d8e00cf RS |
668 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
669 | #define MAX_VR4130_NOPS 4 | |
670 | ||
671 | /* The maximum number of NOPs needed to fill delay slots. */ | |
672 | #define MAX_DELAY_NOPS 2 | |
673 | ||
674 | /* The maximum number of NOPs needed for any purpose. */ | |
675 | #define MAX_NOPS 4 | |
71400594 RS |
676 | |
677 | /* A list of previous instructions, with index 0 being the most recent. | |
678 | We need to look back MAX_NOPS instructions when filling delay slots | |
679 | or working around processor errata. We need to look back one | |
680 | instruction further if we're thinking about using history[0] to | |
681 | fill a branch delay slot. */ | |
682 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 683 | |
1e915849 RS |
684 | /* Nop instructions used by emit_nop. */ |
685 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
686 | ||
687 | /* The appropriate nop for the current mode. */ | |
688 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 689 | |
252b5132 RH |
690 | /* If this is set, it points to a frag holding nop instructions which |
691 | were inserted before the start of a noreorder section. If those | |
692 | nops turn out to be unnecessary, the size of the frag can be | |
693 | decreased. */ | |
694 | static fragS *prev_nop_frag; | |
695 | ||
696 | /* The number of nop instructions we created in prev_nop_frag. */ | |
697 | static int prev_nop_frag_holds; | |
698 | ||
699 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 700 | prev_nop_frag. */ |
252b5132 RH |
701 | static int prev_nop_frag_required; |
702 | ||
703 | /* The number of instructions we've seen since prev_nop_frag. */ | |
704 | static int prev_nop_frag_since; | |
705 | ||
706 | /* For ECOFF and ELF, relocations against symbols are done in two | |
707 | parts, with a HI relocation and a LO relocation. Each relocation | |
708 | has only 16 bits of space to store an addend. This means that in | |
709 | order for the linker to handle carries correctly, it must be able | |
710 | to locate both the HI and the LO relocation. This means that the | |
711 | relocations must appear in order in the relocation table. | |
712 | ||
713 | In order to implement this, we keep track of each unmatched HI | |
714 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 715 | corresponding LO relocation. */ |
252b5132 | 716 | |
e972090a NC |
717 | struct mips_hi_fixup |
718 | { | |
252b5132 RH |
719 | /* Next HI fixup. */ |
720 | struct mips_hi_fixup *next; | |
721 | /* This fixup. */ | |
722 | fixS *fixp; | |
723 | /* The section this fixup is in. */ | |
724 | segT seg; | |
725 | }; | |
726 | ||
727 | /* The list of unmatched HI relocs. */ | |
728 | ||
729 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
730 | ||
64bdfcaf RS |
731 | /* The frag containing the last explicit relocation operator. |
732 | Null if explicit relocations have not been used. */ | |
733 | ||
734 | static fragS *prev_reloc_op_frag; | |
735 | ||
252b5132 RH |
736 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
737 | ||
738 | #define X ILLEGAL_REG | |
e972090a NC |
739 | static const int mips32_to_16_reg_map[] = |
740 | { | |
252b5132 RH |
741 | X, X, 2, 3, 4, 5, 6, 7, |
742 | X, X, X, X, X, X, X, X, | |
743 | 0, 1, X, X, X, X, X, X, | |
744 | X, X, X, X, X, X, X, X | |
745 | }; | |
746 | #undef X | |
747 | ||
748 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
749 | ||
e972090a NC |
750 | static const unsigned int mips16_to_32_reg_map[] = |
751 | { | |
252b5132 RH |
752 | 16, 17, 2, 3, 4, 5, 6, 7 |
753 | }; | |
60b63b72 | 754 | |
71400594 RS |
755 | /* Classifies the kind of instructions we're interested in when |
756 | implementing -mfix-vr4120. */ | |
c67a084a NC |
757 | enum fix_vr4120_class |
758 | { | |
71400594 RS |
759 | FIX_VR4120_MACC, |
760 | FIX_VR4120_DMACC, | |
761 | FIX_VR4120_MULT, | |
762 | FIX_VR4120_DMULT, | |
763 | FIX_VR4120_DIV, | |
764 | FIX_VR4120_MTHILO, | |
765 | NUM_FIX_VR4120_CLASSES | |
766 | }; | |
767 | ||
c67a084a NC |
768 | /* ...likewise -mfix-loongson2f-jump. */ |
769 | static bfd_boolean mips_fix_loongson2f_jump; | |
770 | ||
771 | /* ...likewise -mfix-loongson2f-nop. */ | |
772 | static bfd_boolean mips_fix_loongson2f_nop; | |
773 | ||
774 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
775 | static bfd_boolean mips_fix_loongson2f; | |
776 | ||
71400594 RS |
777 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
778 | there must be at least one other instruction between an instruction | |
779 | of type X and an instruction of type Y. */ | |
780 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
781 | ||
782 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 783 | static int mips_fix_vr4120; |
4a6a3df4 | 784 | |
7d8e00cf RS |
785 | /* ...likewise -mfix-vr4130. */ |
786 | static int mips_fix_vr4130; | |
787 | ||
6a32d874 CM |
788 | /* ...likewise -mfix-24k. */ |
789 | static int mips_fix_24k; | |
790 | ||
d954098f DD |
791 | /* ...likewise -mfix-cn63xxp1 */ |
792 | static bfd_boolean mips_fix_cn63xxp1; | |
793 | ||
4a6a3df4 AO |
794 | /* We don't relax branches by default, since this causes us to expand |
795 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
796 | fail to compute the offset before expanding the macro to the most | |
797 | efficient expansion. */ | |
798 | ||
799 | static int mips_relax_branch; | |
252b5132 | 800 | \f |
4d7206a2 RS |
801 | /* The expansion of many macros depends on the type of symbol that |
802 | they refer to. For example, when generating position-dependent code, | |
803 | a macro that refers to a symbol may have two different expansions, | |
804 | one which uses GP-relative addresses and one which uses absolute | |
805 | addresses. When generating SVR4-style PIC, a macro may have | |
806 | different expansions for local and global symbols. | |
807 | ||
808 | We handle these situations by generating both sequences and putting | |
809 | them in variant frags. In position-dependent code, the first sequence | |
810 | will be the GP-relative one and the second sequence will be the | |
811 | absolute one. In SVR4 PIC, the first sequence will be for global | |
812 | symbols and the second will be for local symbols. | |
813 | ||
584892a6 RS |
814 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
815 | SECOND are the lengths of the two sequences in bytes. These fields | |
816 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
817 | the subtype has the following flags: | |
4d7206a2 | 818 | |
584892a6 RS |
819 | RELAX_USE_SECOND |
820 | Set if it has been decided that we should use the second | |
821 | sequence instead of the first. | |
822 | ||
823 | RELAX_SECOND_LONGER | |
824 | Set in the first variant frag if the macro's second implementation | |
825 | is longer than its first. This refers to the macro as a whole, | |
826 | not an individual relaxation. | |
827 | ||
828 | RELAX_NOMACRO | |
829 | Set in the first variant frag if the macro appeared in a .set nomacro | |
830 | block and if one alternative requires a warning but the other does not. | |
831 | ||
832 | RELAX_DELAY_SLOT | |
833 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
834 | delay slot. | |
4d7206a2 RS |
835 | |
836 | The frag's "opcode" points to the first fixup for relaxable code. | |
837 | ||
838 | Relaxable macros are generated using a sequence such as: | |
839 | ||
840 | relax_start (SYMBOL); | |
841 | ... generate first expansion ... | |
842 | relax_switch (); | |
843 | ... generate second expansion ... | |
844 | relax_end (); | |
845 | ||
846 | The code and fixups for the unwanted alternative are discarded | |
847 | by md_convert_frag. */ | |
584892a6 | 848 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 849 | |
584892a6 RS |
850 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
851 | #define RELAX_SECOND(X) ((X) & 0xff) | |
852 | #define RELAX_USE_SECOND 0x10000 | |
853 | #define RELAX_SECOND_LONGER 0x20000 | |
854 | #define RELAX_NOMACRO 0x40000 | |
855 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 856 | |
4a6a3df4 AO |
857 | /* Branch without likely bit. If label is out of range, we turn: |
858 | ||
859 | beq reg1, reg2, label | |
860 | delay slot | |
861 | ||
862 | into | |
863 | ||
864 | bne reg1, reg2, 0f | |
865 | nop | |
866 | j label | |
867 | 0: delay slot | |
868 | ||
869 | with the following opcode replacements: | |
870 | ||
871 | beq <-> bne | |
872 | blez <-> bgtz | |
873 | bltz <-> bgez | |
874 | bc1f <-> bc1t | |
875 | ||
876 | bltzal <-> bgezal (with jal label instead of j label) | |
877 | ||
878 | Even though keeping the delay slot instruction in the delay slot of | |
879 | the branch would be more efficient, it would be very tricky to do | |
880 | correctly, because we'd have to introduce a variable frag *after* | |
881 | the delay slot instruction, and expand that instead. Let's do it | |
882 | the easy way for now, even if the branch-not-taken case now costs | |
883 | one additional instruction. Out-of-range branches are not supposed | |
884 | to be common, anyway. | |
885 | ||
886 | Branch likely. If label is out of range, we turn: | |
887 | ||
888 | beql reg1, reg2, label | |
889 | delay slot (annulled if branch not taken) | |
890 | ||
891 | into | |
892 | ||
893 | beql reg1, reg2, 1f | |
894 | nop | |
895 | beql $0, $0, 2f | |
896 | nop | |
897 | 1: j[al] label | |
898 | delay slot (executed only if branch taken) | |
899 | 2: | |
900 | ||
901 | It would be possible to generate a shorter sequence by losing the | |
902 | likely bit, generating something like: | |
b34976b6 | 903 | |
4a6a3df4 AO |
904 | bne reg1, reg2, 0f |
905 | nop | |
906 | j[al] label | |
907 | delay slot (executed only if branch taken) | |
908 | 0: | |
909 | ||
910 | beql -> bne | |
911 | bnel -> beq | |
912 | blezl -> bgtz | |
913 | bgtzl -> blez | |
914 | bltzl -> bgez | |
915 | bgezl -> bltz | |
916 | bc1fl -> bc1t | |
917 | bc1tl -> bc1f | |
918 | ||
919 | bltzall -> bgezal (with jal label instead of j label) | |
920 | bgezall -> bltzal (ditto) | |
921 | ||
922 | ||
923 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
924 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
925 | ((relax_substateT) \ | |
926 | (0xc0000000 \ | |
927 | | ((at) & 0x1f) \ | |
928 | | ((toofar) ? 0x20 : 0) \ | |
929 | | ((link) ? 0x40 : 0) \ | |
930 | | ((likely) ? 0x80 : 0) \ | |
931 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 932 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
933 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
934 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
935 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
936 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
937 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 938 | |
252b5132 RH |
939 | /* For mips16 code, we use an entirely different form of relaxation. |
940 | mips16 supports two versions of most instructions which take | |
941 | immediate values: a small one which takes some small value, and a | |
942 | larger one which takes a 16 bit value. Since branches also follow | |
943 | this pattern, relaxing these values is required. | |
944 | ||
945 | We can assemble both mips16 and normal MIPS code in a single | |
946 | object. Therefore, we need to support this type of relaxation at | |
947 | the same time that we support the relaxation described above. We | |
948 | use the high bit of the subtype field to distinguish these cases. | |
949 | ||
950 | The information we store for this type of relaxation is the | |
951 | argument code found in the opcode file for this relocation, whether | |
952 | the user explicitly requested a small or extended form, and whether | |
953 | the relocation is in a jump or jal delay slot. That tells us the | |
954 | size of the value, and how it should be stored. We also store | |
955 | whether the fragment is considered to be extended or not. We also | |
956 | store whether this is known to be a branch to a different section, | |
957 | whether we have tried to relax this frag yet, and whether we have | |
958 | ever extended a PC relative fragment because of a shift count. */ | |
959 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
960 | (0x80000000 \ | |
961 | | ((type) & 0xff) \ | |
962 | | ((small) ? 0x100 : 0) \ | |
963 | | ((ext) ? 0x200 : 0) \ | |
964 | | ((dslot) ? 0x400 : 0) \ | |
965 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 966 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
967 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
968 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
969 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
970 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
971 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
972 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
973 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
974 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
975 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
976 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
977 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
978 | |
979 | /* Is the given value a sign-extended 32-bit value? */ | |
980 | #define IS_SEXT_32BIT_NUM(x) \ | |
981 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
982 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
983 | ||
984 | /* Is the given value a sign-extended 16-bit value? */ | |
985 | #define IS_SEXT_16BIT_NUM(x) \ | |
986 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
987 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
988 | ||
2051e8c4 MR |
989 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
990 | #define IS_ZEXT_32BIT_NUM(x) \ | |
991 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
992 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
993 | ||
bf12938e RS |
994 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
995 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
996 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
997 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
998 | | (((VALUE) & (MASK)) << (SHIFT))) | |
999 | ||
1000 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
1001 | SHIFT places. */ | |
1002 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1003 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1004 | ||
1005 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1006 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1007 | ||
1008 | include/opcode/mips.h specifies operand fields using the macros | |
1009 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1010 | with "MIPS16OP" instead of "OP". */ | |
1011 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
1012 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
1013 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
1014 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1015 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1016 | ||
1017 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
1018 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
1019 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
1020 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
1021 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1022 | MIPS16OP_MASK_##FIELD, \ | |
1023 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
1024 | \f |
1025 | /* Global variables used when generating relaxable macros. See the | |
1026 | comment above RELAX_ENCODE for more details about how relaxation | |
1027 | is used. */ | |
1028 | static struct { | |
1029 | /* 0 if we're not emitting a relaxable macro. | |
1030 | 1 if we're emitting the first of the two relaxation alternatives. | |
1031 | 2 if we're emitting the second alternative. */ | |
1032 | int sequence; | |
1033 | ||
1034 | /* The first relaxable fixup in the current frag. (In other words, | |
1035 | the first fixup that refers to relaxable code.) */ | |
1036 | fixS *first_fixup; | |
1037 | ||
1038 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1039 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1040 | unsigned int sizes[2]; | |
1041 | ||
1042 | /* The symbol on which the choice of sequence depends. */ | |
1043 | symbolS *symbol; | |
1044 | } mips_relax; | |
252b5132 | 1045 | \f |
584892a6 RS |
1046 | /* Global variables used to decide whether a macro needs a warning. */ |
1047 | static struct { | |
1048 | /* True if the macro is in a branch delay slot. */ | |
1049 | bfd_boolean delay_slot_p; | |
1050 | ||
1051 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
1052 | in bytes and sizes[1] is the length of the second alternative. | |
1053 | For non-relaxable macros, both elements give the length of the | |
1054 | macro in bytes. */ | |
1055 | unsigned int sizes[2]; | |
1056 | ||
1057 | /* The first variant frag for this macro. */ | |
1058 | fragS *first_frag; | |
1059 | } mips_macro_warning; | |
1060 | \f | |
252b5132 RH |
1061 | /* Prototypes for static functions. */ |
1062 | ||
17a2f251 | 1063 | #define internalError() \ |
252b5132 | 1064 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
1065 | |
1066 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
1067 | ||
b34976b6 | 1068 | static void append_insn |
c67a084a | 1069 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *); |
7d10b47d | 1070 | static void mips_no_prev_insn (void); |
c67a084a | 1071 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1072 | static void mips16_macro_build |
03ea81db | 1073 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1074 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1075 | static void macro_start (void); |
1076 | static void macro_end (void); | |
17a2f251 TS |
1077 | static void macro (struct mips_cl_insn * ip); |
1078 | static void mips16_macro (struct mips_cl_insn * ip); | |
17a2f251 TS |
1079 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1080 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1081 | static void mips16_immed |
17a2f251 TS |
1082 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
1083 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 1084 | static size_t my_getSmallExpression |
17a2f251 TS |
1085 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1086 | static void my_getExpression (expressionS *, char *); | |
1087 | static void s_align (int); | |
1088 | static void s_change_sec (int); | |
1089 | static void s_change_section (int); | |
1090 | static void s_cons (int); | |
1091 | static void s_float_cons (int); | |
1092 | static void s_mips_globl (int); | |
1093 | static void s_option (int); | |
1094 | static void s_mipsset (int); | |
1095 | static void s_abicalls (int); | |
1096 | static void s_cpload (int); | |
1097 | static void s_cpsetup (int); | |
1098 | static void s_cplocal (int); | |
1099 | static void s_cprestore (int); | |
1100 | static void s_cpreturn (int); | |
741d6ea8 JM |
1101 | static void s_dtprelword (int); |
1102 | static void s_dtpreldword (int); | |
17a2f251 TS |
1103 | static void s_gpvalue (int); |
1104 | static void s_gpword (int); | |
1105 | static void s_gpdword (int); | |
1106 | static void s_cpadd (int); | |
1107 | static void s_insn (int); | |
1108 | static void md_obj_begin (void); | |
1109 | static void md_obj_end (void); | |
1110 | static void s_mips_ent (int); | |
1111 | static void s_mips_end (int); | |
1112 | static void s_mips_frame (int); | |
1113 | static void s_mips_mask (int reg_type); | |
1114 | static void s_mips_stab (int); | |
1115 | static void s_mips_weakext (int); | |
1116 | static void s_mips_file (int); | |
1117 | static void s_mips_loc (int); | |
1118 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1119 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1120 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
1121 | |
1122 | /* Table and functions used to map between CPU/ISA names, and | |
1123 | ISA levels, and CPU numbers. */ | |
1124 | ||
e972090a NC |
1125 | struct mips_cpu_info |
1126 | { | |
e7af610e | 1127 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1128 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1129 | int isa; /* ISA level. */ |
1130 | int cpu; /* CPU number (default CPU if ISA). */ | |
1131 | }; | |
1132 | ||
ad3fea08 TS |
1133 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1134 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1135 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1136 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1137 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1138 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1139 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
ad3fea08 | 1140 | |
17a2f251 TS |
1141 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1142 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1143 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1144 | \f |
1145 | /* Pseudo-op table. | |
1146 | ||
1147 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1148 | should be defined here, but are currently unsupported: .alias, | |
1149 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1150 | ||
1151 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1152 | specific to the type of debugging information being generated, and | |
1153 | should be defined by the object format: .aent, .begin, .bend, | |
1154 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1155 | .vreg. | |
1156 | ||
1157 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1158 | not MIPS CPU specific, but are also not specific to the object file | |
1159 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1160 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1161 | |
e972090a NC |
1162 | static const pseudo_typeS mips_pseudo_table[] = |
1163 | { | |
beae10d5 | 1164 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1165 | {"option", s_option, 0}, |
1166 | {"set", s_mipsset, 0}, | |
1167 | {"rdata", s_change_sec, 'r'}, | |
1168 | {"sdata", s_change_sec, 's'}, | |
1169 | {"livereg", s_ignore, 0}, | |
1170 | {"abicalls", s_abicalls, 0}, | |
1171 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1172 | {"cpsetup", s_cpsetup, 0}, |
1173 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1174 | {"cprestore", s_cprestore, 0}, |
6478892d | 1175 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1176 | {"dtprelword", s_dtprelword, 0}, |
1177 | {"dtpreldword", s_dtpreldword, 0}, | |
6478892d | 1178 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1179 | {"gpword", s_gpword, 0}, |
10181a0d | 1180 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1181 | {"cpadd", s_cpadd, 0}, |
1182 | {"insn", s_insn, 0}, | |
1183 | ||
beae10d5 | 1184 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1185 | chips. */ |
38a57ae7 | 1186 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1187 | {"bss", s_change_sec, 'b'}, |
1188 | {"err", s_err, 0}, | |
1189 | {"half", s_cons, 1}, | |
1190 | {"dword", s_cons, 3}, | |
1191 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1192 | {"origin", s_org, 0}, |
1193 | {"repeat", s_rept, 0}, | |
252b5132 | 1194 | |
998b3c36 MR |
1195 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1196 | {"sbss", s_change_sec, 'B'}, | |
1197 | ||
beae10d5 | 1198 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1199 | here for one reason or another. */ |
1200 | {"align", s_align, 0}, | |
1201 | {"byte", s_cons, 0}, | |
1202 | {"data", s_change_sec, 'd'}, | |
1203 | {"double", s_float_cons, 'd'}, | |
1204 | {"float", s_float_cons, 'f'}, | |
1205 | {"globl", s_mips_globl, 0}, | |
1206 | {"global", s_mips_globl, 0}, | |
1207 | {"hword", s_cons, 1}, | |
1208 | {"int", s_cons, 2}, | |
1209 | {"long", s_cons, 2}, | |
1210 | {"octa", s_cons, 4}, | |
1211 | {"quad", s_cons, 3}, | |
cca86cc8 | 1212 | {"section", s_change_section, 0}, |
252b5132 RH |
1213 | {"short", s_cons, 1}, |
1214 | {"single", s_float_cons, 'f'}, | |
1215 | {"stabn", s_mips_stab, 'n'}, | |
1216 | {"text", s_change_sec, 't'}, | |
1217 | {"word", s_cons, 2}, | |
add56521 | 1218 | |
add56521 | 1219 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1220 | |
43841e91 | 1221 | { NULL, NULL, 0 }, |
252b5132 RH |
1222 | }; |
1223 | ||
e972090a NC |
1224 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1225 | { | |
beae10d5 KH |
1226 | /* These pseudo-ops should be defined by the object file format. |
1227 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1228 | {"aent", s_mips_ent, 1}, |
1229 | {"bgnb", s_ignore, 0}, | |
1230 | {"end", s_mips_end, 0}, | |
1231 | {"endb", s_ignore, 0}, | |
1232 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1233 | {"file", s_mips_file, 0}, |
252b5132 RH |
1234 | {"fmask", s_mips_mask, 'F'}, |
1235 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1236 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1237 | {"mask", s_mips_mask, 'R'}, |
1238 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1239 | { NULL, NULL, 0 }, |
252b5132 RH |
1240 | }; |
1241 | ||
3ae8dd8d MR |
1242 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1243 | purpose of the `.dc.a' internal pseudo-op. */ | |
1244 | ||
1245 | int | |
1246 | mips_address_bytes (void) | |
1247 | { | |
1248 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1249 | } | |
1250 | ||
17a2f251 | 1251 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1252 | |
1253 | void | |
17a2f251 | 1254 | mips_pop_insert (void) |
252b5132 RH |
1255 | { |
1256 | pop_insert (mips_pseudo_table); | |
1257 | if (! ECOFF_DEBUGGING) | |
1258 | pop_insert (mips_nonecoff_pseudo_table); | |
1259 | } | |
1260 | \f | |
1261 | /* Symbols labelling the current insn. */ | |
1262 | ||
e972090a NC |
1263 | struct insn_label_list |
1264 | { | |
252b5132 RH |
1265 | struct insn_label_list *next; |
1266 | symbolS *label; | |
1267 | }; | |
1268 | ||
252b5132 | 1269 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1270 | #define label_list tc_segment_info_data.labels |
252b5132 | 1271 | |
17a2f251 | 1272 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1273 | |
1274 | static inline void | |
17a2f251 | 1275 | mips_clear_insn_labels (void) |
252b5132 RH |
1276 | { |
1277 | register struct insn_label_list **pl; | |
a8dbcb85 | 1278 | segment_info_type *si; |
252b5132 | 1279 | |
a8dbcb85 TS |
1280 | if (now_seg) |
1281 | { | |
1282 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1283 | ; | |
1284 | ||
1285 | si = seg_info (now_seg); | |
1286 | *pl = si->label_list; | |
1287 | si->label_list = NULL; | |
1288 | } | |
252b5132 | 1289 | } |
a8dbcb85 | 1290 | |
252b5132 RH |
1291 | \f |
1292 | static char *expr_end; | |
1293 | ||
1294 | /* Expressions which appear in instructions. These are set by | |
1295 | mips_ip. */ | |
1296 | ||
1297 | static expressionS imm_expr; | |
5f74bc13 | 1298 | static expressionS imm2_expr; |
252b5132 RH |
1299 | static expressionS offset_expr; |
1300 | ||
1301 | /* Relocs associated with imm_expr and offset_expr. */ | |
1302 | ||
f6688943 TS |
1303 | static bfd_reloc_code_real_type imm_reloc[3] |
1304 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1305 | static bfd_reloc_code_real_type offset_reloc[3] | |
1306 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1307 | |
252b5132 RH |
1308 | /* These are set by mips16_ip if an explicit extension is used. */ |
1309 | ||
b34976b6 | 1310 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1311 | |
7ed4a06a | 1312 | #ifdef OBJ_ELF |
ecb4347a DJ |
1313 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1314 | ECOFF debugging. */ | |
252b5132 RH |
1315 | |
1316 | static segT pdr_seg; | |
7ed4a06a | 1317 | #endif |
252b5132 | 1318 | |
e013f690 TS |
1319 | /* The default target format to use. */ |
1320 | ||
aeffff67 RS |
1321 | #if defined (TE_FreeBSD) |
1322 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1323 | #elif defined (TE_TMIPS) | |
1324 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1325 | #else | |
1326 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1327 | #endif | |
1328 | ||
e013f690 | 1329 | const char * |
17a2f251 | 1330 | mips_target_format (void) |
e013f690 TS |
1331 | { |
1332 | switch (OUTPUT_FLAVOR) | |
1333 | { | |
e013f690 TS |
1334 | case bfd_target_ecoff_flavour: |
1335 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1336 | case bfd_target_coff_flavour: | |
1337 | return "pe-mips"; | |
1338 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1339 | #ifdef TE_VXWORKS |
1340 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1341 | return (target_big_endian | |
1342 | ? "elf32-bigmips-vxworks" | |
1343 | : "elf32-littlemips-vxworks"); | |
1344 | #endif | |
e013f690 | 1345 | return (target_big_endian |
cfe86eaa | 1346 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1347 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1348 | : (HAVE_NEWABI |
aeffff67 RS |
1349 | ? ELF_TARGET ("elf32-n", "big") |
1350 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1351 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1352 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1353 | : (HAVE_NEWABI |
aeffff67 RS |
1354 | ? ELF_TARGET ("elf32-n", "little") |
1355 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1356 | default: |
1357 | abort (); | |
1358 | return NULL; | |
1359 | } | |
1360 | } | |
1361 | ||
1e915849 RS |
1362 | /* Return the length of instruction INSN. */ |
1363 | ||
1364 | static inline unsigned int | |
1365 | insn_length (const struct mips_cl_insn *insn) | |
1366 | { | |
1367 | if (!mips_opts.mips16) | |
1368 | return 4; | |
1369 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1370 | } | |
1371 | ||
1372 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1373 | ||
1374 | static void | |
1375 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1376 | { | |
1377 | size_t i; | |
1378 | ||
1379 | insn->insn_mo = mo; | |
1380 | insn->use_extend = FALSE; | |
1381 | insn->extend = 0; | |
1382 | insn->insn_opcode = mo->match; | |
1383 | insn->frag = NULL; | |
1384 | insn->where = 0; | |
1385 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1386 | insn->fixp[i] = NULL; | |
1387 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1388 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1389 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 1390 | insn->complete_p = 0; |
1e915849 RS |
1391 | } |
1392 | ||
742a56fe RS |
1393 | /* Record the current MIPS16 mode in now_seg. */ |
1394 | ||
1395 | static void | |
1396 | mips_record_mips16_mode (void) | |
1397 | { | |
1398 | segment_info_type *si; | |
1399 | ||
1400 | si = seg_info (now_seg); | |
1401 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1402 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
1403 | } | |
1404 | ||
1e915849 RS |
1405 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1406 | ||
1407 | static void | |
1408 | install_insn (const struct mips_cl_insn *insn) | |
1409 | { | |
1410 | char *f = insn->frag->fr_literal + insn->where; | |
1411 | if (!mips_opts.mips16) | |
1412 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1413 | else if (insn->mips16_absolute_jump_p) | |
1414 | { | |
1415 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1416 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1417 | } | |
1418 | else | |
1419 | { | |
1420 | if (insn->use_extend) | |
1421 | { | |
1422 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1423 | f += 2; | |
1424 | } | |
1425 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1426 | } | |
742a56fe | 1427 | mips_record_mips16_mode (); |
1e915849 RS |
1428 | } |
1429 | ||
1430 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1431 | and install the opcode in the new location. */ | |
1432 | ||
1433 | static void | |
1434 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1435 | { | |
1436 | size_t i; | |
1437 | ||
1438 | insn->frag = frag; | |
1439 | insn->where = where; | |
1440 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1441 | if (insn->fixp[i] != NULL) | |
1442 | { | |
1443 | insn->fixp[i]->fx_frag = frag; | |
1444 | insn->fixp[i]->fx_where = where; | |
1445 | } | |
1446 | install_insn (insn); | |
1447 | } | |
1448 | ||
1449 | /* Add INSN to the end of the output. */ | |
1450 | ||
1451 | static void | |
1452 | add_fixed_insn (struct mips_cl_insn *insn) | |
1453 | { | |
1454 | char *f = frag_more (insn_length (insn)); | |
1455 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1456 | } | |
1457 | ||
1458 | /* Start a variant frag and move INSN to the start of the variant part, | |
1459 | marking it as fixed. The other arguments are as for frag_var. */ | |
1460 | ||
1461 | static void | |
1462 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1463 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1464 | { | |
1465 | frag_grow (max_chars); | |
1466 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1467 | insn->fixed_p = 1; | |
1468 | frag_var (rs_machine_dependent, max_chars, var, | |
1469 | subtype, symbol, offset, NULL); | |
1470 | } | |
1471 | ||
1472 | /* Insert N copies of INSN into the history buffer, starting at | |
1473 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1474 | ||
1475 | static void | |
1476 | insert_into_history (unsigned int first, unsigned int n, | |
1477 | const struct mips_cl_insn *insn) | |
1478 | { | |
1479 | if (mips_relax.sequence != 2) | |
1480 | { | |
1481 | unsigned int i; | |
1482 | ||
1483 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1484 | if (i >= first + n) | |
1485 | history[i] = history[i - n]; | |
1486 | else | |
1487 | history[i] = *insn; | |
1488 | } | |
1489 | } | |
1490 | ||
1491 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1492 | ||
1493 | static void | |
1494 | emit_nop (void) | |
1495 | { | |
1496 | add_fixed_insn (NOP_INSN); | |
1497 | insert_into_history (0, 1, NOP_INSN); | |
1498 | } | |
1499 | ||
71400594 RS |
1500 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1501 | the idea is to make it obvious at a glance that each errata is | |
1502 | included. */ | |
1503 | ||
1504 | static void | |
1505 | init_vr4120_conflicts (void) | |
1506 | { | |
1507 | #define CONFLICT(FIRST, SECOND) \ | |
1508 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1509 | ||
1510 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1511 | CONFLICT (MACC, DIV); | |
1512 | CONFLICT (DMACC, DIV); | |
1513 | ||
1514 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1515 | CONFLICT (DMULT, DMULT); | |
1516 | CONFLICT (DMULT, DMACC); | |
1517 | CONFLICT (DMACC, DMULT); | |
1518 | CONFLICT (DMACC, DMACC); | |
1519 | ||
1520 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1521 | CONFLICT (MACC, MTHILO); | |
1522 | CONFLICT (DMACC, MTHILO); | |
1523 | ||
1524 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1525 | instruction is executed immediately after a MACC or DMACC | |
1526 | instruction, the result of [either instruction] is incorrect." */ | |
1527 | CONFLICT (MACC, MULT); | |
1528 | CONFLICT (MACC, DMULT); | |
1529 | CONFLICT (DMACC, MULT); | |
1530 | CONFLICT (DMACC, DMULT); | |
1531 | ||
1532 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1533 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1534 | DDIV or DDIVU instruction, the result of the MACC or | |
1535 | DMACC instruction is incorrect.". */ | |
1536 | CONFLICT (DMULT, MACC); | |
1537 | CONFLICT (DMULT, DMACC); | |
1538 | CONFLICT (DIV, MACC); | |
1539 | CONFLICT (DIV, DMACC); | |
1540 | ||
1541 | #undef CONFLICT | |
1542 | } | |
1543 | ||
707bfff6 TS |
1544 | struct regname { |
1545 | const char *name; | |
1546 | unsigned int num; | |
1547 | }; | |
1548 | ||
1549 | #define RTYPE_MASK 0x1ff00 | |
1550 | #define RTYPE_NUM 0x00100 | |
1551 | #define RTYPE_FPU 0x00200 | |
1552 | #define RTYPE_FCC 0x00400 | |
1553 | #define RTYPE_VEC 0x00800 | |
1554 | #define RTYPE_GP 0x01000 | |
1555 | #define RTYPE_CP0 0x02000 | |
1556 | #define RTYPE_PC 0x04000 | |
1557 | #define RTYPE_ACC 0x08000 | |
1558 | #define RTYPE_CCC 0x10000 | |
1559 | #define RNUM_MASK 0x000ff | |
1560 | #define RWARN 0x80000 | |
1561 | ||
1562 | #define GENERIC_REGISTER_NUMBERS \ | |
1563 | {"$0", RTYPE_NUM | 0}, \ | |
1564 | {"$1", RTYPE_NUM | 1}, \ | |
1565 | {"$2", RTYPE_NUM | 2}, \ | |
1566 | {"$3", RTYPE_NUM | 3}, \ | |
1567 | {"$4", RTYPE_NUM | 4}, \ | |
1568 | {"$5", RTYPE_NUM | 5}, \ | |
1569 | {"$6", RTYPE_NUM | 6}, \ | |
1570 | {"$7", RTYPE_NUM | 7}, \ | |
1571 | {"$8", RTYPE_NUM | 8}, \ | |
1572 | {"$9", RTYPE_NUM | 9}, \ | |
1573 | {"$10", RTYPE_NUM | 10}, \ | |
1574 | {"$11", RTYPE_NUM | 11}, \ | |
1575 | {"$12", RTYPE_NUM | 12}, \ | |
1576 | {"$13", RTYPE_NUM | 13}, \ | |
1577 | {"$14", RTYPE_NUM | 14}, \ | |
1578 | {"$15", RTYPE_NUM | 15}, \ | |
1579 | {"$16", RTYPE_NUM | 16}, \ | |
1580 | {"$17", RTYPE_NUM | 17}, \ | |
1581 | {"$18", RTYPE_NUM | 18}, \ | |
1582 | {"$19", RTYPE_NUM | 19}, \ | |
1583 | {"$20", RTYPE_NUM | 20}, \ | |
1584 | {"$21", RTYPE_NUM | 21}, \ | |
1585 | {"$22", RTYPE_NUM | 22}, \ | |
1586 | {"$23", RTYPE_NUM | 23}, \ | |
1587 | {"$24", RTYPE_NUM | 24}, \ | |
1588 | {"$25", RTYPE_NUM | 25}, \ | |
1589 | {"$26", RTYPE_NUM | 26}, \ | |
1590 | {"$27", RTYPE_NUM | 27}, \ | |
1591 | {"$28", RTYPE_NUM | 28}, \ | |
1592 | {"$29", RTYPE_NUM | 29}, \ | |
1593 | {"$30", RTYPE_NUM | 30}, \ | |
1594 | {"$31", RTYPE_NUM | 31} | |
1595 | ||
1596 | #define FPU_REGISTER_NAMES \ | |
1597 | {"$f0", RTYPE_FPU | 0}, \ | |
1598 | {"$f1", RTYPE_FPU | 1}, \ | |
1599 | {"$f2", RTYPE_FPU | 2}, \ | |
1600 | {"$f3", RTYPE_FPU | 3}, \ | |
1601 | {"$f4", RTYPE_FPU | 4}, \ | |
1602 | {"$f5", RTYPE_FPU | 5}, \ | |
1603 | {"$f6", RTYPE_FPU | 6}, \ | |
1604 | {"$f7", RTYPE_FPU | 7}, \ | |
1605 | {"$f8", RTYPE_FPU | 8}, \ | |
1606 | {"$f9", RTYPE_FPU | 9}, \ | |
1607 | {"$f10", RTYPE_FPU | 10}, \ | |
1608 | {"$f11", RTYPE_FPU | 11}, \ | |
1609 | {"$f12", RTYPE_FPU | 12}, \ | |
1610 | {"$f13", RTYPE_FPU | 13}, \ | |
1611 | {"$f14", RTYPE_FPU | 14}, \ | |
1612 | {"$f15", RTYPE_FPU | 15}, \ | |
1613 | {"$f16", RTYPE_FPU | 16}, \ | |
1614 | {"$f17", RTYPE_FPU | 17}, \ | |
1615 | {"$f18", RTYPE_FPU | 18}, \ | |
1616 | {"$f19", RTYPE_FPU | 19}, \ | |
1617 | {"$f20", RTYPE_FPU | 20}, \ | |
1618 | {"$f21", RTYPE_FPU | 21}, \ | |
1619 | {"$f22", RTYPE_FPU | 22}, \ | |
1620 | {"$f23", RTYPE_FPU | 23}, \ | |
1621 | {"$f24", RTYPE_FPU | 24}, \ | |
1622 | {"$f25", RTYPE_FPU | 25}, \ | |
1623 | {"$f26", RTYPE_FPU | 26}, \ | |
1624 | {"$f27", RTYPE_FPU | 27}, \ | |
1625 | {"$f28", RTYPE_FPU | 28}, \ | |
1626 | {"$f29", RTYPE_FPU | 29}, \ | |
1627 | {"$f30", RTYPE_FPU | 30}, \ | |
1628 | {"$f31", RTYPE_FPU | 31} | |
1629 | ||
1630 | #define FPU_CONDITION_CODE_NAMES \ | |
1631 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1632 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1633 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1634 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1635 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1636 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1637 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1638 | {"$fcc7", RTYPE_FCC | 7} | |
1639 | ||
1640 | #define COPROC_CONDITION_CODE_NAMES \ | |
1641 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1642 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1643 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1644 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1645 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1646 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1647 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1648 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1649 | ||
1650 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1651 | {"$a4", RTYPE_GP | 8}, \ | |
1652 | {"$a5", RTYPE_GP | 9}, \ | |
1653 | {"$a6", RTYPE_GP | 10}, \ | |
1654 | {"$a7", RTYPE_GP | 11}, \ | |
1655 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1656 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1657 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1658 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1659 | {"$t0", RTYPE_GP | 12}, \ | |
1660 | {"$t1", RTYPE_GP | 13}, \ | |
1661 | {"$t2", RTYPE_GP | 14}, \ | |
1662 | {"$t3", RTYPE_GP | 15} | |
1663 | ||
1664 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1665 | {"$t0", RTYPE_GP | 8}, \ | |
1666 | {"$t1", RTYPE_GP | 9}, \ | |
1667 | {"$t2", RTYPE_GP | 10}, \ | |
1668 | {"$t3", RTYPE_GP | 11}, \ | |
1669 | {"$t4", RTYPE_GP | 12}, \ | |
1670 | {"$t5", RTYPE_GP | 13}, \ | |
1671 | {"$t6", RTYPE_GP | 14}, \ | |
1672 | {"$t7", RTYPE_GP | 15}, \ | |
1673 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1674 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1675 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1676 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
1677 | ||
1678 | /* Remaining symbolic register names */ | |
1679 | #define SYMBOLIC_REGISTER_NAMES \ | |
1680 | {"$zero", RTYPE_GP | 0}, \ | |
1681 | {"$at", RTYPE_GP | 1}, \ | |
1682 | {"$AT", RTYPE_GP | 1}, \ | |
1683 | {"$v0", RTYPE_GP | 2}, \ | |
1684 | {"$v1", RTYPE_GP | 3}, \ | |
1685 | {"$a0", RTYPE_GP | 4}, \ | |
1686 | {"$a1", RTYPE_GP | 5}, \ | |
1687 | {"$a2", RTYPE_GP | 6}, \ | |
1688 | {"$a3", RTYPE_GP | 7}, \ | |
1689 | {"$s0", RTYPE_GP | 16}, \ | |
1690 | {"$s1", RTYPE_GP | 17}, \ | |
1691 | {"$s2", RTYPE_GP | 18}, \ | |
1692 | {"$s3", RTYPE_GP | 19}, \ | |
1693 | {"$s4", RTYPE_GP | 20}, \ | |
1694 | {"$s5", RTYPE_GP | 21}, \ | |
1695 | {"$s6", RTYPE_GP | 22}, \ | |
1696 | {"$s7", RTYPE_GP | 23}, \ | |
1697 | {"$t8", RTYPE_GP | 24}, \ | |
1698 | {"$t9", RTYPE_GP | 25}, \ | |
1699 | {"$k0", RTYPE_GP | 26}, \ | |
1700 | {"$kt0", RTYPE_GP | 26}, \ | |
1701 | {"$k1", RTYPE_GP | 27}, \ | |
1702 | {"$kt1", RTYPE_GP | 27}, \ | |
1703 | {"$gp", RTYPE_GP | 28}, \ | |
1704 | {"$sp", RTYPE_GP | 29}, \ | |
1705 | {"$s8", RTYPE_GP | 30}, \ | |
1706 | {"$fp", RTYPE_GP | 30}, \ | |
1707 | {"$ra", RTYPE_GP | 31} | |
1708 | ||
1709 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
1710 | {"$pc", RTYPE_PC | 0} | |
1711 | ||
1712 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
1713 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
1714 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
1715 | {"$v2", RTYPE_VEC | 2}, \ | |
1716 | {"$v3", RTYPE_VEC | 3}, \ | |
1717 | {"$v4", RTYPE_VEC | 4}, \ | |
1718 | {"$v5", RTYPE_VEC | 5}, \ | |
1719 | {"$v6", RTYPE_VEC | 6}, \ | |
1720 | {"$v7", RTYPE_VEC | 7}, \ | |
1721 | {"$v8", RTYPE_VEC | 8}, \ | |
1722 | {"$v9", RTYPE_VEC | 9}, \ | |
1723 | {"$v10", RTYPE_VEC | 10}, \ | |
1724 | {"$v11", RTYPE_VEC | 11}, \ | |
1725 | {"$v12", RTYPE_VEC | 12}, \ | |
1726 | {"$v13", RTYPE_VEC | 13}, \ | |
1727 | {"$v14", RTYPE_VEC | 14}, \ | |
1728 | {"$v15", RTYPE_VEC | 15}, \ | |
1729 | {"$v16", RTYPE_VEC | 16}, \ | |
1730 | {"$v17", RTYPE_VEC | 17}, \ | |
1731 | {"$v18", RTYPE_VEC | 18}, \ | |
1732 | {"$v19", RTYPE_VEC | 19}, \ | |
1733 | {"$v20", RTYPE_VEC | 20}, \ | |
1734 | {"$v21", RTYPE_VEC | 21}, \ | |
1735 | {"$v22", RTYPE_VEC | 22}, \ | |
1736 | {"$v23", RTYPE_VEC | 23}, \ | |
1737 | {"$v24", RTYPE_VEC | 24}, \ | |
1738 | {"$v25", RTYPE_VEC | 25}, \ | |
1739 | {"$v26", RTYPE_VEC | 26}, \ | |
1740 | {"$v27", RTYPE_VEC | 27}, \ | |
1741 | {"$v28", RTYPE_VEC | 28}, \ | |
1742 | {"$v29", RTYPE_VEC | 29}, \ | |
1743 | {"$v30", RTYPE_VEC | 30}, \ | |
1744 | {"$v31", RTYPE_VEC | 31} | |
1745 | ||
1746 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
1747 | {"$ac0", RTYPE_ACC | 0}, \ | |
1748 | {"$ac1", RTYPE_ACC | 1}, \ | |
1749 | {"$ac2", RTYPE_ACC | 2}, \ | |
1750 | {"$ac3", RTYPE_ACC | 3} | |
1751 | ||
1752 | static const struct regname reg_names[] = { | |
1753 | GENERIC_REGISTER_NUMBERS, | |
1754 | FPU_REGISTER_NAMES, | |
1755 | FPU_CONDITION_CODE_NAMES, | |
1756 | COPROC_CONDITION_CODE_NAMES, | |
1757 | ||
1758 | /* The $txx registers depends on the abi, | |
1759 | these will be added later into the symbol table from | |
1760 | one of the tables below once mips_abi is set after | |
1761 | parsing of arguments from the command line. */ | |
1762 | SYMBOLIC_REGISTER_NAMES, | |
1763 | ||
1764 | MIPS16_SPECIAL_REGISTER_NAMES, | |
1765 | MDMX_VECTOR_REGISTER_NAMES, | |
1766 | MIPS_DSP_ACCUMULATOR_NAMES, | |
1767 | {0, 0} | |
1768 | }; | |
1769 | ||
1770 | static const struct regname reg_names_o32[] = { | |
1771 | O32_SYMBOLIC_REGISTER_NAMES, | |
1772 | {0, 0} | |
1773 | }; | |
1774 | ||
1775 | static const struct regname reg_names_n32n64[] = { | |
1776 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
1777 | {0, 0} | |
1778 | }; | |
1779 | ||
1780 | static int | |
1781 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
1782 | { | |
1783 | symbolS *symbolP; | |
1784 | char *e; | |
1785 | char save_c; | |
1786 | int reg = -1; | |
1787 | ||
1788 | /* Find end of name. */ | |
1789 | e = *s; | |
1790 | if (is_name_beginner (*e)) | |
1791 | ++e; | |
1792 | while (is_part_of_name (*e)) | |
1793 | ++e; | |
1794 | ||
1795 | /* Terminate name. */ | |
1796 | save_c = *e; | |
1797 | *e = '\0'; | |
1798 | ||
1799 | /* Look for a register symbol. */ | |
1800 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
1801 | { | |
1802 | int r = S_GET_VALUE (symbolP); | |
1803 | if (r & types) | |
1804 | reg = r & RNUM_MASK; | |
1805 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
1806 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
1807 | reg = (r & RNUM_MASK) - 2; | |
1808 | } | |
1809 | /* Else see if this is a register defined in an itbl entry. */ | |
1810 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
1811 | { | |
1812 | char *n = *s; | |
1813 | unsigned long r; | |
1814 | ||
1815 | if (*n == '$') | |
1816 | ++n; | |
1817 | if (itbl_get_reg_val (n, &r)) | |
1818 | reg = r & RNUM_MASK; | |
1819 | } | |
1820 | ||
1821 | /* Advance to next token if a register was recognised. */ | |
1822 | if (reg >= 0) | |
1823 | *s = e; | |
1824 | else if (types & RWARN) | |
20203fb9 | 1825 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
1826 | |
1827 | *e = save_c; | |
1828 | if (regnop) | |
1829 | *regnop = reg; | |
1830 | return reg >= 0; | |
1831 | } | |
1832 | ||
037b32b9 | 1833 | /* Return TRUE if opcode MO is valid on the currently selected ISA and |
f79e2745 | 1834 | architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ |
037b32b9 AN |
1835 | |
1836 | static bfd_boolean | |
f79e2745 | 1837 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
1838 | { |
1839 | int isa = mips_opts.isa; | |
1840 | int fp_s, fp_d; | |
1841 | ||
1842 | if (mips_opts.ase_mdmx) | |
1843 | isa |= INSN_MDMX; | |
1844 | if (mips_opts.ase_dsp) | |
1845 | isa |= INSN_DSP; | |
1846 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
1847 | isa |= INSN_DSP64; | |
1848 | if (mips_opts.ase_dspr2) | |
1849 | isa |= INSN_DSPR2; | |
1850 | if (mips_opts.ase_mt) | |
1851 | isa |= INSN_MT; | |
1852 | if (mips_opts.ase_mips3d) | |
1853 | isa |= INSN_MIPS3D; | |
1854 | if (mips_opts.ase_smartmips) | |
1855 | isa |= INSN_SMARTMIPS; | |
1856 | ||
b19e8a9b AN |
1857 | /* Don't accept instructions based on the ISA if the CPU does not implement |
1858 | all the coprocessor insns. */ | |
1859 | if (NO_ISA_COP (mips_opts.arch) | |
1860 | && COP_INSN (mo->pinfo)) | |
1861 | isa = 0; | |
1862 | ||
037b32b9 AN |
1863 | if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch)) |
1864 | return FALSE; | |
1865 | ||
1866 | /* Check whether the instruction or macro requires single-precision or | |
1867 | double-precision floating-point support. Note that this information is | |
1868 | stored differently in the opcode table for insns and macros. */ | |
1869 | if (mo->pinfo == INSN_MACRO) | |
1870 | { | |
1871 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
1872 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
1873 | } | |
1874 | else | |
1875 | { | |
1876 | fp_s = mo->pinfo & FP_S; | |
1877 | fp_d = mo->pinfo & FP_D; | |
1878 | } | |
1879 | ||
1880 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
1881 | return FALSE; | |
1882 | ||
1883 | if (fp_s && mips_opts.soft_float) | |
1884 | return FALSE; | |
1885 | ||
1886 | return TRUE; | |
1887 | } | |
1888 | ||
1889 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
1890 | selected ISA and architecture. */ | |
1891 | ||
1892 | static bfd_boolean | |
1893 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
1894 | { | |
1895 | return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE; | |
1896 | } | |
1897 | ||
707bfff6 TS |
1898 | /* This function is called once, at assembler startup time. It should set up |
1899 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 1900 | |
252b5132 | 1901 | void |
17a2f251 | 1902 | md_begin (void) |
252b5132 | 1903 | { |
3994f87e | 1904 | const char *retval = NULL; |
156c2f8b | 1905 | int i = 0; |
252b5132 | 1906 | int broken = 0; |
1f25f5d3 | 1907 | |
0a44bf69 RS |
1908 | if (mips_pic != NO_PIC) |
1909 | { | |
1910 | if (g_switch_seen && g_switch_value != 0) | |
1911 | as_bad (_("-G may not be used in position-independent code")); | |
1912 | g_switch_value = 0; | |
1913 | } | |
1914 | ||
fef14a42 | 1915 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1916 | as_warn (_("Could not set architecture and machine")); |
1917 | ||
252b5132 RH |
1918 | op_hash = hash_new (); |
1919 | ||
1920 | for (i = 0; i < NUMOPCODES;) | |
1921 | { | |
1922 | const char *name = mips_opcodes[i].name; | |
1923 | ||
17a2f251 | 1924 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1925 | if (retval != NULL) |
1926 | { | |
1927 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1928 | mips_opcodes[i].name, retval); | |
1929 | /* Probably a memory allocation problem? Give up now. */ | |
1930 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1931 | } | |
1932 | do | |
1933 | { | |
1934 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1935 | { | |
1936 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1937 | broken = 1; | |
1e915849 RS |
1938 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1939 | { | |
1940 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
1941 | if (mips_fix_loongson2f_nop) |
1942 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
1943 | nop_insn.fixed_p = 1; |
1944 | } | |
252b5132 RH |
1945 | } |
1946 | ++i; | |
1947 | } | |
1948 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1949 | } | |
1950 | ||
1951 | mips16_op_hash = hash_new (); | |
1952 | ||
1953 | i = 0; | |
1954 | while (i < bfd_mips16_num_opcodes) | |
1955 | { | |
1956 | const char *name = mips16_opcodes[i].name; | |
1957 | ||
17a2f251 | 1958 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1959 | if (retval != NULL) |
1960 | as_fatal (_("internal: can't hash `%s': %s"), | |
1961 | mips16_opcodes[i].name, retval); | |
1962 | do | |
1963 | { | |
1964 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1965 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1966 | != mips16_opcodes[i].match)) | |
1967 | { | |
1968 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1969 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1970 | broken = 1; | |
1971 | } | |
1e915849 RS |
1972 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1973 | { | |
1974 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1975 | mips16_nop_insn.fixed_p = 1; | |
1976 | } | |
252b5132 RH |
1977 | ++i; |
1978 | } | |
1979 | while (i < bfd_mips16_num_opcodes | |
1980 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1981 | } | |
1982 | ||
1983 | if (broken) | |
1984 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1985 | ||
1986 | /* We add all the general register names to the symbol table. This | |
1987 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
1988 | for (i = 0; reg_names[i].name; i++) |
1989 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 1990 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
1991 | &zero_address_frag)); |
1992 | if (HAVE_NEWABI) | |
1993 | for (i = 0; reg_names_n32n64[i].name; i++) | |
1994 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 1995 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 1996 | &zero_address_frag)); |
707bfff6 TS |
1997 | else |
1998 | for (i = 0; reg_names_o32[i].name; i++) | |
1999 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 2000 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 2001 | &zero_address_frag)); |
6047c971 | 2002 | |
7d10b47d | 2003 | mips_no_prev_insn (); |
252b5132 RH |
2004 | |
2005 | mips_gprmask = 0; | |
2006 | mips_cprmask[0] = 0; | |
2007 | mips_cprmask[1] = 0; | |
2008 | mips_cprmask[2] = 0; | |
2009 | mips_cprmask[3] = 0; | |
2010 | ||
2011 | /* set the default alignment for the text section (2**2) */ | |
2012 | record_alignment (text_section, 2); | |
2013 | ||
4d0d148d | 2014 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2015 | |
707bfff6 | 2016 | #ifdef OBJ_ELF |
f43abd2b | 2017 | if (IS_ELF) |
252b5132 | 2018 | { |
0a44bf69 RS |
2019 | /* On a native system other than VxWorks, sections must be aligned |
2020 | to 16 byte boundaries. When configured for an embedded ELF | |
2021 | target, we don't bother. */ | |
c41e87e3 CF |
2022 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
2023 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
2024 | { |
2025 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2026 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2027 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2028 | } | |
2029 | ||
2030 | /* Create a .reginfo section for register masks and a .mdebug | |
2031 | section for debugging information. */ | |
2032 | { | |
2033 | segT seg; | |
2034 | subsegT subseg; | |
2035 | flagword flags; | |
2036 | segT sec; | |
2037 | ||
2038 | seg = now_seg; | |
2039 | subseg = now_subseg; | |
2040 | ||
2041 | /* The ABI says this section should be loaded so that the | |
2042 | running program can access it. However, we don't load it | |
2043 | if we are configured for an embedded target */ | |
2044 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2045 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2046 | flags |= SEC_ALLOC | SEC_LOAD; |
2047 | ||
316f5878 | 2048 | if (mips_abi != N64_ABI) |
252b5132 RH |
2049 | { |
2050 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2051 | ||
195325d2 TS |
2052 | bfd_set_section_flags (stdoutput, sec, flags); |
2053 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2054 | |
252b5132 | 2055 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2056 | } |
2057 | else | |
2058 | { | |
2059 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2060 | .reginfo section. */ | |
2061 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2062 | bfd_set_section_flags (stdoutput, sec, flags); |
2063 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2064 | |
252b5132 RH |
2065 | /* Set up the option header. */ |
2066 | { | |
2067 | Elf_Internal_Options opthdr; | |
2068 | char *f; | |
2069 | ||
2070 | opthdr.kind = ODK_REGINFO; | |
2071 | opthdr.size = (sizeof (Elf_External_Options) | |
2072 | + sizeof (Elf64_External_RegInfo)); | |
2073 | opthdr.section = 0; | |
2074 | opthdr.info = 0; | |
2075 | f = frag_more (sizeof (Elf_External_Options)); | |
2076 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2077 | (Elf_External_Options *) f); | |
2078 | ||
2079 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2080 | } | |
252b5132 RH |
2081 | } |
2082 | ||
2083 | if (ECOFF_DEBUGGING) | |
2084 | { | |
2085 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2086 | (void) bfd_set_section_flags (stdoutput, sec, | |
2087 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2088 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2089 | } | |
f43abd2b | 2090 | else if (mips_flag_pdr) |
ecb4347a DJ |
2091 | { |
2092 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2093 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2094 | SEC_READONLY | SEC_RELOC | |
2095 | | SEC_DEBUGGING); | |
2096 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2097 | } | |
252b5132 RH |
2098 | |
2099 | subseg_set (seg, subseg); | |
2100 | } | |
2101 | } | |
707bfff6 | 2102 | #endif /* OBJ_ELF */ |
252b5132 RH |
2103 | |
2104 | if (! ECOFF_DEBUGGING) | |
2105 | md_obj_begin (); | |
71400594 RS |
2106 | |
2107 | if (mips_fix_vr4120) | |
2108 | init_vr4120_conflicts (); | |
252b5132 RH |
2109 | } |
2110 | ||
2111 | void | |
17a2f251 | 2112 | md_mips_end (void) |
252b5132 | 2113 | { |
02b1ab82 | 2114 | mips_emit_delays (); |
252b5132 RH |
2115 | if (! ECOFF_DEBUGGING) |
2116 | md_obj_end (); | |
2117 | } | |
2118 | ||
2119 | void | |
17a2f251 | 2120 | md_assemble (char *str) |
252b5132 RH |
2121 | { |
2122 | struct mips_cl_insn insn; | |
f6688943 TS |
2123 | bfd_reloc_code_real_type unused_reloc[3] |
2124 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2125 | |
2126 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2127 | imm2_expr.X_op = O_absent; |
252b5132 | 2128 | offset_expr.X_op = O_absent; |
f6688943 TS |
2129 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2130 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2131 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2132 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2133 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2134 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2135 | |
2136 | if (mips_opts.mips16) | |
2137 | mips16_ip (str, &insn); | |
2138 | else | |
2139 | { | |
2140 | mips_ip (str, &insn); | |
beae10d5 KH |
2141 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2142 | str, insn.insn_opcode)); | |
252b5132 RH |
2143 | } |
2144 | ||
2145 | if (insn_error) | |
2146 | { | |
2147 | as_bad ("%s `%s'", insn_error, str); | |
2148 | return; | |
2149 | } | |
2150 | ||
2151 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
2152 | { | |
584892a6 | 2153 | macro_start (); |
252b5132 RH |
2154 | if (mips_opts.mips16) |
2155 | mips16_macro (&insn); | |
2156 | else | |
2157 | macro (&insn); | |
584892a6 | 2158 | macro_end (); |
252b5132 RH |
2159 | } |
2160 | else | |
2161 | { | |
2162 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 2163 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 2164 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 2165 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 2166 | else |
4d7206a2 | 2167 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
2168 | } |
2169 | } | |
2170 | ||
738e5348 RS |
2171 | /* Convenience functions for abstracting away the differences between |
2172 | MIPS16 and non-MIPS16 relocations. */ | |
2173 | ||
2174 | static inline bfd_boolean | |
2175 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2176 | { | |
2177 | switch (reloc) | |
2178 | { | |
2179 | case BFD_RELOC_MIPS16_JMP: | |
2180 | case BFD_RELOC_MIPS16_GPREL: | |
2181 | case BFD_RELOC_MIPS16_GOT16: | |
2182 | case BFD_RELOC_MIPS16_CALL16: | |
2183 | case BFD_RELOC_MIPS16_HI16_S: | |
2184 | case BFD_RELOC_MIPS16_HI16: | |
2185 | case BFD_RELOC_MIPS16_LO16: | |
2186 | return TRUE; | |
2187 | ||
2188 | default: | |
2189 | return FALSE; | |
2190 | } | |
2191 | } | |
2192 | ||
2193 | static inline bfd_boolean | |
2194 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2195 | { | |
2196 | return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16; | |
2197 | } | |
2198 | ||
2199 | static inline bfd_boolean | |
2200 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2201 | { | |
2202 | return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S; | |
2203 | } | |
2204 | ||
2205 | static inline bfd_boolean | |
2206 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2207 | { | |
2208 | return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16; | |
2209 | } | |
2210 | ||
5919d012 | 2211 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2212 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2213 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2214 | |
2215 | static inline bfd_boolean | |
17a2f251 | 2216 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2217 | { |
3b91255e | 2218 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2219 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2220 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2221 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2222 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2223 | } | |
2224 | ||
2225 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2226 | reloc_needs_lo_p. */ | |
2227 | ||
2228 | static inline bfd_reloc_code_real_type | |
2229 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2230 | { | |
2231 | return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16; | |
5919d012 RS |
2232 | } |
2233 | ||
2234 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2235 | relocation. */ | |
2236 | ||
2237 | static inline bfd_boolean | |
17a2f251 | 2238 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2239 | { |
2240 | return (fixp->fx_next != NULL | |
738e5348 | 2241 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2242 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2243 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2244 | } | |
2245 | ||
252b5132 RH |
2246 | /* This function returns true if modifying a register requires a |
2247 | delay. */ | |
2248 | ||
2249 | static int | |
17a2f251 | 2250 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2251 | { |
2252 | unsigned long prev_pinfo; | |
2253 | ||
47e39b9d | 2254 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2255 | if (! mips_opts.noreorder |
81912461 ILT |
2256 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2257 | && ! gpr_interlocks) | |
2258 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2259 | && ! cop_interlocks))) | |
252b5132 | 2260 | { |
81912461 ILT |
2261 | /* A load from a coprocessor or from memory. All load delays |
2262 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2263 | /* Itbl support may require additional care here. */ |
252b5132 | 2264 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 2265 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
2266 | return 1; |
2267 | } | |
2268 | ||
2269 | return 0; | |
2270 | } | |
2271 | ||
404a8071 RS |
2272 | /* Move all labels in insn_labels to the current insertion point. */ |
2273 | ||
2274 | static void | |
2275 | mips_move_labels (void) | |
2276 | { | |
a8dbcb85 | 2277 | segment_info_type *si = seg_info (now_seg); |
404a8071 RS |
2278 | struct insn_label_list *l; |
2279 | valueT val; | |
2280 | ||
a8dbcb85 | 2281 | for (l = si->label_list; l != NULL; l = l->next) |
404a8071 | 2282 | { |
9c2799c2 | 2283 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
2284 | symbol_set_frag (l->label, frag_now); |
2285 | val = (valueT) frag_now_fix (); | |
2286 | /* mips16 text labels are stored as odd. */ | |
2287 | if (mips_opts.mips16) | |
2288 | ++val; | |
2289 | S_SET_VALUE (l->label, val); | |
2290 | } | |
2291 | } | |
2292 | ||
5f0fe04b TS |
2293 | static bfd_boolean |
2294 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2295 | { | |
2296 | bfd_boolean linkonce = FALSE; | |
2297 | segT symseg = S_GET_SEGMENT (sym); | |
2298 | ||
2299 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2300 | { | |
2301 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2302 | linkonce = TRUE; | |
2303 | #ifdef OBJ_ELF | |
2304 | /* The GNU toolchain uses an extension for ELF: a section | |
2305 | beginning with the magic string .gnu.linkonce is a | |
2306 | linkonce section. */ | |
2307 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2308 | sizeof ".gnu.linkonce" - 1) == 0) | |
2309 | linkonce = TRUE; | |
2310 | #endif | |
2311 | } | |
2312 | return linkonce; | |
2313 | } | |
2314 | ||
252b5132 RH |
2315 | /* Mark instruction labels in mips16 mode. This permits the linker to |
2316 | handle them specially, such as generating jalx instructions when | |
2317 | needed. We also make them odd for the duration of the assembly, in | |
2318 | order to generate the right sort of code. We will make them even | |
2319 | in the adjust_symtab routine, while leaving them marked. This is | |
2320 | convenient for the debugger and the disassembler. The linker knows | |
2321 | to make them odd again. */ | |
2322 | ||
2323 | static void | |
17a2f251 | 2324 | mips16_mark_labels (void) |
252b5132 | 2325 | { |
a8dbcb85 TS |
2326 | segment_info_type *si = seg_info (now_seg); |
2327 | struct insn_label_list *l; | |
252b5132 | 2328 | |
a8dbcb85 TS |
2329 | if (!mips_opts.mips16) |
2330 | return; | |
2331 | ||
2332 | for (l = si->label_list; l != NULL; l = l->next) | |
2333 | { | |
2334 | symbolS *label = l->label; | |
2335 | ||
2336 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
f43abd2b | 2337 | if (IS_ELF) |
30c09090 | 2338 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); |
252b5132 | 2339 | #endif |
5f0fe04b TS |
2340 | if ((S_GET_VALUE (label) & 1) == 0 |
2341 | /* Don't adjust the address if the label is global or weak, or | |
2342 | in a link-once section, since we'll be emitting symbol reloc | |
2343 | references to it which will be patched up by the linker, and | |
2344 | the final value of the symbol may or may not be MIPS16. */ | |
2345 | && ! S_IS_WEAK (label) | |
2346 | && ! S_IS_EXTERNAL (label) | |
2347 | && ! s_is_linkonce (label, now_seg)) | |
a8dbcb85 | 2348 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); |
252b5132 RH |
2349 | } |
2350 | } | |
2351 | ||
4d7206a2 RS |
2352 | /* End the current frag. Make it a variant frag and record the |
2353 | relaxation info. */ | |
2354 | ||
2355 | static void | |
2356 | relax_close_frag (void) | |
2357 | { | |
584892a6 | 2358 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2359 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2360 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2361 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2362 | ||
2363 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2364 | mips_relax.first_fixup = 0; | |
2365 | } | |
2366 | ||
2367 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2368 | See the comment above RELAX_ENCODE for more details. */ | |
2369 | ||
2370 | static void | |
2371 | relax_start (symbolS *symbol) | |
2372 | { | |
9c2799c2 | 2373 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
2374 | mips_relax.sequence = 1; |
2375 | mips_relax.symbol = symbol; | |
2376 | } | |
2377 | ||
2378 | /* Start generating the second version of a relaxable sequence. | |
2379 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2380 | |
2381 | static void | |
4d7206a2 RS |
2382 | relax_switch (void) |
2383 | { | |
9c2799c2 | 2384 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
2385 | mips_relax.sequence = 2; |
2386 | } | |
2387 | ||
2388 | /* End the current relaxable sequence. */ | |
2389 | ||
2390 | static void | |
2391 | relax_end (void) | |
2392 | { | |
9c2799c2 | 2393 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
2394 | relax_close_frag (); |
2395 | mips_relax.sequence = 0; | |
2396 | } | |
2397 | ||
4c260379 RS |
2398 | /* Return the mask of core registers that IP reads. */ |
2399 | ||
2400 | static unsigned int | |
2401 | gpr_read_mask (const struct mips_cl_insn *ip) | |
2402 | { | |
2403 | unsigned long pinfo, pinfo2; | |
2404 | unsigned int mask; | |
2405 | ||
2406 | mask = 0; | |
2407 | pinfo = ip->insn_mo->pinfo; | |
2408 | pinfo2 = ip->insn_mo->pinfo2; | |
2409 | if (mips_opts.mips16) | |
2410 | { | |
2411 | if (pinfo & MIPS16_INSN_READ_X) | |
2412 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
2413 | if (pinfo & MIPS16_INSN_READ_Y) | |
2414 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
2415 | if (pinfo & MIPS16_INSN_READ_T) | |
2416 | mask |= 1 << TREG; | |
2417 | if (pinfo & MIPS16_INSN_READ_SP) | |
2418 | mask |= 1 << SP; | |
2419 | if (pinfo & MIPS16_INSN_READ_31) | |
2420 | mask |= 1 << RA; | |
2421 | if (pinfo & MIPS16_INSN_READ_Z) | |
2422 | mask |= 1 << (mips16_to_32_reg_map | |
2423 | [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]); | |
2424 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2425 | mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); | |
2426 | } | |
2427 | else | |
2428 | { | |
2429 | if (pinfo2 & INSN2_READ_GPR_D) | |
2430 | mask |= 1 << EXTRACT_OPERAND (RD, *ip); | |
2431 | if (pinfo & INSN_READ_GPR_T) | |
2432 | mask |= 1 << EXTRACT_OPERAND (RT, *ip); | |
2433 | if (pinfo & INSN_READ_GPR_S) | |
2434 | mask |= 1 << EXTRACT_OPERAND (RS, *ip); | |
2435 | if (pinfo2 & INSN2_READ_GPR_Z) | |
2436 | mask |= 1 << EXTRACT_OPERAND (RZ, *ip); | |
2437 | } | |
2438 | return mask & ~0; | |
2439 | } | |
2440 | ||
2441 | /* Return the mask of core registers that IP writes. */ | |
2442 | ||
2443 | static unsigned int | |
2444 | gpr_write_mask (const struct mips_cl_insn *ip) | |
2445 | { | |
2446 | unsigned long pinfo, pinfo2; | |
2447 | unsigned int mask; | |
2448 | ||
2449 | mask = 0; | |
2450 | pinfo = ip->insn_mo->pinfo; | |
2451 | pinfo2 = ip->insn_mo->pinfo2; | |
2452 | if (mips_opts.mips16) | |
2453 | { | |
2454 | if (pinfo & MIPS16_INSN_WRITE_X) | |
2455 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
2456 | if (pinfo & MIPS16_INSN_WRITE_Y) | |
2457 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
2458 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2459 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)]; | |
2460 | if (pinfo & MIPS16_INSN_WRITE_T) | |
2461 | mask |= 1 << TREG; | |
2462 | if (pinfo & MIPS16_INSN_WRITE_SP) | |
2463 | mask |= 1 << SP; | |
2464 | if (pinfo & MIPS16_INSN_WRITE_31) | |
2465 | mask |= 1 << RA; | |
2466 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2467 | mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2468 | } | |
2469 | else | |
2470 | { | |
2471 | if (pinfo & INSN_WRITE_GPR_D) | |
2472 | mask |= 1 << EXTRACT_OPERAND (RD, *ip); | |
2473 | if (pinfo & INSN_WRITE_GPR_T) | |
2474 | mask |= 1 << EXTRACT_OPERAND (RT, *ip); | |
2475 | if (pinfo & INSN_WRITE_GPR_31) | |
2476 | mask |= 1 << RA; | |
2477 | if (pinfo2 & INSN2_WRITE_GPR_Z) | |
2478 | mask |= 1 << EXTRACT_OPERAND (RZ, *ip); | |
2479 | } | |
2480 | return mask & ~0; | |
2481 | } | |
2482 | ||
2483 | /* Return the mask of floating-point registers that IP reads. */ | |
2484 | ||
2485 | static unsigned int | |
2486 | fpr_read_mask (const struct mips_cl_insn *ip) | |
2487 | { | |
2488 | unsigned long pinfo, pinfo2; | |
2489 | unsigned int mask; | |
2490 | ||
2491 | mask = 0; | |
2492 | pinfo = ip->insn_mo->pinfo; | |
2493 | pinfo2 = ip->insn_mo->pinfo2; | |
2494 | if (!mips_opts.mips16) | |
2495 | { | |
2496 | if (pinfo & INSN_READ_FPR_S) | |
2497 | mask |= 1 << EXTRACT_OPERAND (FS, *ip); | |
2498 | if (pinfo & INSN_READ_FPR_T) | |
2499 | mask |= 1 << EXTRACT_OPERAND (FT, *ip); | |
2500 | if (pinfo & INSN_READ_FPR_R) | |
2501 | mask |= 1 << EXTRACT_OPERAND (FR, *ip); | |
2502 | if (pinfo2 & INSN2_READ_FPR_Z) | |
2503 | mask |= 1 << EXTRACT_OPERAND (FZ, *ip); | |
2504 | } | |
2505 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
2506 | (This is overly pessimistic for things like cvt.d.s.) */ | |
2507 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
2508 | mask |= mask << 1; | |
2509 | return mask; | |
2510 | } | |
2511 | ||
2512 | /* Return the mask of floating-point registers that IP writes. */ | |
2513 | ||
2514 | static unsigned int | |
2515 | fpr_write_mask (const struct mips_cl_insn *ip) | |
2516 | { | |
2517 | unsigned long pinfo, pinfo2; | |
2518 | unsigned int mask; | |
2519 | ||
2520 | mask = 0; | |
2521 | pinfo = ip->insn_mo->pinfo; | |
2522 | pinfo2 = ip->insn_mo->pinfo2; | |
2523 | if (!mips_opts.mips16) | |
2524 | { | |
2525 | if (pinfo & INSN_WRITE_FPR_D) | |
2526 | mask |= 1 << EXTRACT_OPERAND (FD, *ip); | |
2527 | if (pinfo & INSN_WRITE_FPR_S) | |
2528 | mask |= 1 << EXTRACT_OPERAND (FS, *ip); | |
2529 | if (pinfo & INSN_WRITE_FPR_T) | |
2530 | mask |= 1 << EXTRACT_OPERAND (FT, *ip); | |
2531 | if (pinfo2 & INSN2_WRITE_FPR_Z) | |
2532 | mask |= 1 << EXTRACT_OPERAND (FZ, *ip); | |
2533 | } | |
2534 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
2535 | (This is overly pessimistic for things like cvt.s.d.) */ | |
2536 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
2537 | mask |= mask << 1; | |
2538 | return mask; | |
2539 | } | |
2540 | ||
71400594 RS |
2541 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
2542 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
2543 | by VR4120 errata. */ | |
4d7206a2 | 2544 | |
71400594 RS |
2545 | static unsigned int |
2546 | classify_vr4120_insn (const char *name) | |
252b5132 | 2547 | { |
71400594 RS |
2548 | if (strncmp (name, "macc", 4) == 0) |
2549 | return FIX_VR4120_MACC; | |
2550 | if (strncmp (name, "dmacc", 5) == 0) | |
2551 | return FIX_VR4120_DMACC; | |
2552 | if (strncmp (name, "mult", 4) == 0) | |
2553 | return FIX_VR4120_MULT; | |
2554 | if (strncmp (name, "dmult", 5) == 0) | |
2555 | return FIX_VR4120_DMULT; | |
2556 | if (strstr (name, "div")) | |
2557 | return FIX_VR4120_DIV; | |
2558 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
2559 | return FIX_VR4120_MTHILO; | |
2560 | return NUM_FIX_VR4120_CLASSES; | |
2561 | } | |
252b5132 | 2562 | |
ff239038 CM |
2563 | #define INSN_ERET 0x42000018 |
2564 | #define INSN_DERET 0x4200001f | |
2565 | ||
71400594 RS |
2566 | /* Return the number of instructions that must separate INSN1 and INSN2, |
2567 | where INSN1 is the earlier instruction. Return the worst-case value | |
2568 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 2569 | |
71400594 RS |
2570 | static unsigned int |
2571 | insns_between (const struct mips_cl_insn *insn1, | |
2572 | const struct mips_cl_insn *insn2) | |
2573 | { | |
2574 | unsigned long pinfo1, pinfo2; | |
4c260379 | 2575 | unsigned int mask; |
71400594 RS |
2576 | |
2577 | /* This function needs to know which pinfo flags are set for INSN2 | |
2578 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
4c260379 RS |
2579 | the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2 |
2580 | will have every flag set and INSN2_USES_GPR will always return true. */ | |
71400594 RS |
2581 | pinfo1 = insn1->insn_mo->pinfo; |
2582 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 2583 | |
4c260379 RS |
2584 | #define INSN2_USES_GPR(REG) \ |
2585 | (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0) | |
71400594 RS |
2586 | |
2587 | /* For most targets, write-after-read dependencies on the HI and LO | |
2588 | registers must be separated by at least two instructions. */ | |
2589 | if (!hilo_interlocks) | |
252b5132 | 2590 | { |
71400594 RS |
2591 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
2592 | return 2; | |
2593 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
2594 | return 2; | |
2595 | } | |
2596 | ||
2597 | /* If we're working around r7000 errata, there must be two instructions | |
2598 | between an mfhi or mflo and any instruction that uses the result. */ | |
2599 | if (mips_7000_hilo_fix | |
2600 | && MF_HILO_INSN (pinfo1) | |
4c260379 | 2601 | && INSN2_USES_GPR (EXTRACT_OPERAND (RD, *insn1))) |
71400594 RS |
2602 | return 2; |
2603 | ||
ff239038 CM |
2604 | /* If we're working around 24K errata, one instruction is required |
2605 | if an ERET or DERET is followed by a branch instruction. */ | |
2606 | if (mips_fix_24k) | |
2607 | { | |
2608 | if (insn1->insn_opcode == INSN_ERET | |
2609 | || insn1->insn_opcode == INSN_DERET) | |
2610 | { | |
2611 | if (insn2 == NULL | |
2612 | || insn2->insn_opcode == INSN_ERET | |
2613 | || insn2->insn_opcode == INSN_DERET | |
2614 | || (insn2->insn_mo->pinfo | |
2615 | & (INSN_UNCOND_BRANCH_DELAY | |
2616 | | INSN_COND_BRANCH_DELAY | |
2617 | | INSN_COND_BRANCH_LIKELY)) != 0) | |
2618 | return 1; | |
2619 | } | |
2620 | } | |
2621 | ||
71400594 RS |
2622 | /* If working around VR4120 errata, check for combinations that need |
2623 | a single intervening instruction. */ | |
2624 | if (mips_fix_vr4120) | |
2625 | { | |
2626 | unsigned int class1, class2; | |
252b5132 | 2627 | |
71400594 RS |
2628 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
2629 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 2630 | { |
71400594 RS |
2631 | if (insn2 == NULL) |
2632 | return 1; | |
2633 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
2634 | if (vr4120_conflicts[class1] & (1 << class2)) | |
2635 | return 1; | |
252b5132 | 2636 | } |
71400594 RS |
2637 | } |
2638 | ||
2639 | if (!mips_opts.mips16) | |
2640 | { | |
2641 | /* Check for GPR or coprocessor load delays. All such delays | |
2642 | are on the RT register. */ | |
2643 | /* Itbl support may require additional care here. */ | |
2644 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
2645 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 2646 | { |
71400594 | 2647 | know (pinfo1 & INSN_WRITE_GPR_T); |
4c260379 | 2648 | if (INSN2_USES_GPR (EXTRACT_OPERAND (RT, *insn1))) |
71400594 RS |
2649 | return 1; |
2650 | } | |
2651 | ||
2652 | /* Check for generic coprocessor hazards. | |
2653 | ||
2654 | This case is not handled very well. There is no special | |
2655 | knowledge of CP0 handling, and the coprocessors other than | |
2656 | the floating point unit are not distinguished at all. */ | |
2657 | /* Itbl support may require additional care here. FIXME! | |
2658 | Need to modify this to include knowledge about | |
2659 | user specified delays! */ | |
2660 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
2661 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
2662 | { | |
2663 | /* Handle cases where INSN1 writes to a known general coprocessor | |
2664 | register. There must be a one instruction delay before INSN2 | |
2665 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
2666 | mask = fpr_write_mask (insn1); |
2667 | if (mask != 0) | |
252b5132 | 2668 | { |
4c260379 | 2669 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 2670 | return 1; |
252b5132 RH |
2671 | } |
2672 | else | |
2673 | { | |
71400594 RS |
2674 | /* Read-after-write dependencies on the control registers |
2675 | require a two-instruction gap. */ | |
2676 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
2677 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2678 | return 2; | |
2679 | ||
2680 | /* We don't know exactly what INSN1 does. If INSN2 is | |
2681 | also a coprocessor instruction, assume there must be | |
2682 | a one instruction gap. */ | |
2683 | if (pinfo2 & INSN_COP) | |
2684 | return 1; | |
252b5132 RH |
2685 | } |
2686 | } | |
6b76fefe | 2687 | |
71400594 RS |
2688 | /* Check for read-after-write dependencies on the coprocessor |
2689 | control registers in cases where INSN1 does not need a general | |
2690 | coprocessor delay. This means that INSN1 is a floating point | |
2691 | comparison instruction. */ | |
2692 | /* Itbl support may require additional care here. */ | |
2693 | else if (!cop_interlocks | |
2694 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2695 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2696 | return 1; | |
2697 | } | |
6b76fefe | 2698 | |
4c260379 | 2699 | #undef INSN2_USES_GPR |
6b76fefe | 2700 | |
71400594 RS |
2701 | return 0; |
2702 | } | |
6b76fefe | 2703 | |
7d8e00cf RS |
2704 | /* Return the number of nops that would be needed to work around the |
2705 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
2706 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
2707 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
2708 | |
2709 | static int | |
932d1a1b | 2710 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
2711 | const struct mips_cl_insn *insn) |
2712 | { | |
4c260379 RS |
2713 | int i, j; |
2714 | unsigned int mask; | |
7d8e00cf RS |
2715 | |
2716 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2717 | are not affected by the errata. */ | |
2718 | if (insn != 0 | |
2719 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2720 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2721 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2722 | return 0; | |
2723 | ||
2724 | /* Search for the first MFLO or MFHI. */ | |
2725 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 2726 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
2727 | { |
2728 | /* Extract the destination register. */ | |
4c260379 | 2729 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
2730 | |
2731 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 2732 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
2733 | return 0; |
2734 | ||
2735 | /* ...or if any of the intervening instructions do. */ | |
2736 | for (j = 0; j < i; j++) | |
4c260379 | 2737 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
2738 | return 0; |
2739 | ||
932d1a1b RS |
2740 | if (i >= ignore) |
2741 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
2742 | } |
2743 | return 0; | |
2744 | } | |
2745 | ||
15be625d CM |
2746 | #define BASE_REG_EQ(INSN1, INSN2) \ |
2747 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
2748 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
2749 | ||
2750 | /* Return the minimum alignment for this store instruction. */ | |
2751 | ||
2752 | static int | |
2753 | fix_24k_align_to (const struct mips_opcode *mo) | |
2754 | { | |
2755 | if (strcmp (mo->name, "sh") == 0) | |
2756 | return 2; | |
2757 | ||
2758 | if (strcmp (mo->name, "swc1") == 0 | |
2759 | || strcmp (mo->name, "swc2") == 0 | |
2760 | || strcmp (mo->name, "sw") == 0 | |
2761 | || strcmp (mo->name, "sc") == 0 | |
2762 | || strcmp (mo->name, "s.s") == 0) | |
2763 | return 4; | |
2764 | ||
2765 | if (strcmp (mo->name, "sdc1") == 0 | |
2766 | || strcmp (mo->name, "sdc2") == 0 | |
2767 | || strcmp (mo->name, "s.d") == 0) | |
2768 | return 8; | |
2769 | ||
2770 | /* sb, swl, swr */ | |
2771 | return 1; | |
2772 | } | |
2773 | ||
2774 | struct fix_24k_store_info | |
2775 | { | |
2776 | /* Immediate offset, if any, for this store instruction. */ | |
2777 | short off; | |
2778 | /* Alignment required by this store instruction. */ | |
2779 | int align_to; | |
2780 | /* True for register offsets. */ | |
2781 | int register_offset; | |
2782 | }; | |
2783 | ||
2784 | /* Comparison function used by qsort. */ | |
2785 | ||
2786 | static int | |
2787 | fix_24k_sort (const void *a, const void *b) | |
2788 | { | |
2789 | const struct fix_24k_store_info *pos1 = a; | |
2790 | const struct fix_24k_store_info *pos2 = b; | |
2791 | ||
2792 | return (pos1->off - pos2->off); | |
2793 | } | |
2794 | ||
2795 | /* INSN is a store instruction. Try to record the store information | |
2796 | in STINFO. Return false if the information isn't known. */ | |
2797 | ||
2798 | static bfd_boolean | |
2799 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 2800 | const struct mips_cl_insn *insn) |
15be625d CM |
2801 | { |
2802 | /* The instruction must have a known offset. */ | |
2803 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
2804 | return FALSE; | |
2805 | ||
2806 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
2807 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
2808 | return TRUE; | |
2809 | } | |
2810 | ||
932d1a1b RS |
2811 | /* Return the number of nops that would be needed to work around the 24k |
2812 | "lost data on stores during refill" errata if instruction INSN | |
2813 | immediately followed the 2 instructions described by HIST. | |
2814 | Ignore hazards that are contained within the first IGNORE | |
2815 | instructions of HIST. | |
2816 | ||
2817 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
2818 | for the data cache refills and store data. The following describes | |
2819 | the scenario where the store data could be lost. | |
2820 | ||
2821 | * A data cache miss, due to either a load or a store, causing fill | |
2822 | data to be supplied by the memory subsystem | |
2823 | * The first three doublewords of fill data are returned and written | |
2824 | into the cache | |
2825 | * A sequence of four stores occurs in consecutive cycles around the | |
2826 | final doubleword of the fill: | |
2827 | * Store A | |
2828 | * Store B | |
2829 | * Store C | |
2830 | * Zero, One or more instructions | |
2831 | * Store D | |
2832 | ||
2833 | The four stores A-D must be to different doublewords of the line that | |
2834 | is being filled. The fourth instruction in the sequence above permits | |
2835 | the fill of the final doubleword to be transferred from the FSB into | |
2836 | the cache. In the sequence above, the stores may be either integer | |
2837 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
2838 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
2839 | different doublewords on the line. If the floating point unit is | |
2840 | running in 1:2 mode, it is not possible to create the sequence above | |
2841 | using only floating point store instructions. | |
15be625d CM |
2842 | |
2843 | In this case, the cache line being filled is incorrectly marked | |
2844 | invalid, thereby losing the data from any store to the line that | |
2845 | occurs between the original miss and the completion of the five | |
2846 | cycle sequence shown above. | |
2847 | ||
932d1a1b | 2848 | The workarounds are: |
15be625d | 2849 | |
932d1a1b RS |
2850 | * Run the data cache in write-through mode. |
2851 | * Insert a non-store instruction between | |
2852 | Store A and Store B or Store B and Store C. */ | |
15be625d CM |
2853 | |
2854 | static int | |
932d1a1b | 2855 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
2856 | const struct mips_cl_insn *insn) |
2857 | { | |
2858 | struct fix_24k_store_info pos[3]; | |
2859 | int align, i, base_offset; | |
2860 | ||
932d1a1b RS |
2861 | if (ignore >= 2) |
2862 | return 0; | |
2863 | ||
ab9794cf RS |
2864 | /* If the previous instruction wasn't a store, there's nothing to |
2865 | worry about. */ | |
15be625d CM |
2866 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
2867 | return 0; | |
2868 | ||
ab9794cf RS |
2869 | /* If the instructions after the previous one are unknown, we have |
2870 | to assume the worst. */ | |
2871 | if (!insn) | |
15be625d CM |
2872 | return 1; |
2873 | ||
ab9794cf RS |
2874 | /* Check whether we are dealing with three consecutive stores. */ |
2875 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
2876 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
2877 | return 0; |
2878 | ||
2879 | /* If we don't know the relationship between the store addresses, | |
2880 | assume the worst. */ | |
ab9794cf | 2881 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
2882 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
2883 | return 1; | |
2884 | ||
2885 | if (!fix_24k_record_store_info (&pos[0], insn) | |
2886 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
2887 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
2888 | return 1; | |
2889 | ||
2890 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
2891 | ||
2892 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
2893 | X bytes and such that the base register + X is known to be aligned | |
2894 | to align bytes. */ | |
2895 | ||
2896 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
2897 | align = 8; | |
2898 | else | |
2899 | { | |
2900 | align = pos[0].align_to; | |
2901 | base_offset = pos[0].off; | |
2902 | for (i = 1; i < 3; i++) | |
2903 | if (align < pos[i].align_to) | |
2904 | { | |
2905 | align = pos[i].align_to; | |
2906 | base_offset = pos[i].off; | |
2907 | } | |
2908 | for (i = 0; i < 3; i++) | |
2909 | pos[i].off -= base_offset; | |
2910 | } | |
2911 | ||
2912 | pos[0].off &= ~align + 1; | |
2913 | pos[1].off &= ~align + 1; | |
2914 | pos[2].off &= ~align + 1; | |
2915 | ||
2916 | /* If any two stores write to the same chunk, they also write to the | |
2917 | same doubleword. The offsets are still sorted at this point. */ | |
2918 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
2919 | return 0; | |
2920 | ||
2921 | /* A range of at least 9 bytes is needed for the stores to be in | |
2922 | non-overlapping doublewords. */ | |
2923 | if (pos[2].off - pos[0].off <= 8) | |
2924 | return 0; | |
2925 | ||
2926 | if (pos[2].off - pos[1].off >= 24 | |
2927 | || pos[1].off - pos[0].off >= 24 | |
2928 | || pos[2].off - pos[0].off >= 32) | |
2929 | return 0; | |
2930 | ||
2931 | return 1; | |
2932 | } | |
2933 | ||
71400594 | 2934 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 2935 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
2936 | where HIST[0] is the most recent instruction. Ignore hazards |
2937 | between INSN and the first IGNORE instructions in HIST. | |
2938 | ||
2939 | If INSN is null, return the worse-case number of nops for any | |
2940 | instruction. */ | |
bdaaa2e1 | 2941 | |
71400594 | 2942 | static int |
932d1a1b | 2943 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
2944 | const struct mips_cl_insn *insn) |
2945 | { | |
2946 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2947 | |
71400594 | 2948 | nops = 0; |
932d1a1b | 2949 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 2950 | { |
91d6fa6a | 2951 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
2952 | if (tmp_nops > nops) |
2953 | nops = tmp_nops; | |
2954 | } | |
7d8e00cf RS |
2955 | |
2956 | if (mips_fix_vr4130) | |
2957 | { | |
932d1a1b | 2958 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
2959 | if (tmp_nops > nops) |
2960 | nops = tmp_nops; | |
2961 | } | |
2962 | ||
15be625d CM |
2963 | if (mips_fix_24k) |
2964 | { | |
932d1a1b | 2965 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
2966 | if (tmp_nops > nops) |
2967 | nops = tmp_nops; | |
2968 | } | |
2969 | ||
71400594 RS |
2970 | return nops; |
2971 | } | |
252b5132 | 2972 | |
71400594 | 2973 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 2974 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
2975 | would be needed after the extended sequence, ignoring hazards |
2976 | in the first IGNORE instructions. */ | |
252b5132 | 2977 | |
71400594 | 2978 | static int |
932d1a1b RS |
2979 | nops_for_sequence (int num_insns, int ignore, |
2980 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
2981 | { |
2982 | va_list args; | |
2983 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2984 | struct mips_cl_insn *cursor; | |
2985 | int nops; | |
2986 | ||
91d6fa6a | 2987 | va_start (args, hist); |
71400594 | 2988 | cursor = buffer + num_insns; |
91d6fa6a | 2989 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
2990 | while (cursor > buffer) |
2991 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2992 | ||
932d1a1b | 2993 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
2994 | va_end (args); |
2995 | return nops; | |
2996 | } | |
252b5132 | 2997 | |
71400594 RS |
2998 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2999 | worst-case delay for the branch target. */ | |
252b5132 | 3000 | |
71400594 | 3001 | static int |
932d1a1b | 3002 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3003 | const struct mips_cl_insn *insn) |
3004 | { | |
3005 | int nops, tmp_nops; | |
60b63b72 | 3006 | |
932d1a1b | 3007 | nops = nops_for_insn (ignore, hist, insn); |
71400594 RS |
3008 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY |
3009 | | INSN_COND_BRANCH_DELAY | |
3010 | | INSN_COND_BRANCH_LIKELY)) | |
3011 | { | |
932d1a1b RS |
3012 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
3013 | hist, insn, NOP_INSN); | |
71400594 RS |
3014 | if (tmp_nops > nops) |
3015 | nops = tmp_nops; | |
3016 | } | |
9a2c7088 MR |
3017 | else if (mips_opts.mips16 |
3018 | && (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
3019 | | MIPS16_INSN_COND_BRANCH))) | |
71400594 | 3020 | { |
932d1a1b | 3021 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
3022 | if (tmp_nops > nops) |
3023 | nops = tmp_nops; | |
3024 | } | |
3025 | return nops; | |
3026 | } | |
3027 | ||
c67a084a NC |
3028 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
3029 | ||
3030 | static void | |
3031 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
3032 | { | |
3033 | if (strcmp (ip->insn_mo->name, "nop") == 0) | |
3034 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
3035 | } | |
3036 | ||
3037 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
3038 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
3039 | ||
3040 | static void | |
3041 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
3042 | { | |
3043 | if (strcmp (ip->insn_mo->name, "j") == 0 | |
3044 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
3045 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
3046 | { | |
3047 | int sreg; | |
3048 | expressionS ep; | |
3049 | ||
3050 | if (! mips_opts.at) | |
3051 | return; | |
3052 | ||
3053 | sreg = EXTRACT_OPERAND (RS, *ip); | |
3054 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) | |
3055 | return; | |
3056 | ||
3057 | ep.X_op = O_constant; | |
3058 | ep.X_add_number = 0xcfff0000; | |
3059 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
3060 | ep.X_add_number = 0xffff; | |
3061 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
3062 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
3063 | } | |
3064 | } | |
3065 | ||
3066 | static void | |
3067 | fix_loongson2f (struct mips_cl_insn * ip) | |
3068 | { | |
3069 | if (mips_fix_loongson2f_nop) | |
3070 | fix_loongson2f_nop (ip); | |
3071 | ||
3072 | if (mips_fix_loongson2f_jump) | |
3073 | fix_loongson2f_jump (ip); | |
3074 | } | |
3075 | ||
71400594 RS |
3076 | /* Output an instruction. IP is the instruction information. |
3077 | ADDRESS_EXPR is an operand of the instruction to be used with | |
3078 | RELOC_TYPE. */ | |
3079 | ||
3080 | static void | |
3081 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
3082 | bfd_reloc_code_real_type *reloc_type) | |
3083 | { | |
3994f87e | 3084 | unsigned long prev_pinfo, pinfo; |
98675402 | 3085 | unsigned long prev_pinfo2, pinfo2; |
71400594 RS |
3086 | relax_stateT prev_insn_frag_type = 0; |
3087 | bfd_boolean relaxed_branch = FALSE; | |
a8dbcb85 | 3088 | segment_info_type *si = seg_info (now_seg); |
71400594 | 3089 | |
c67a084a NC |
3090 | if (mips_fix_loongson2f) |
3091 | fix_loongson2f (ip); | |
3092 | ||
71400594 RS |
3093 | /* Mark instruction labels in mips16 mode. */ |
3094 | mips16_mark_labels (); | |
3095 | ||
738f4d98 MR |
3096 | file_ase_mips16 |= mips_opts.mips16; |
3097 | ||
71400594 | 3098 | prev_pinfo = history[0].insn_mo->pinfo; |
98675402 | 3099 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 3100 | pinfo = ip->insn_mo->pinfo; |
98675402 | 3101 | pinfo2 = ip->insn_mo->pinfo2; |
71400594 | 3102 | |
15be625d CM |
3103 | if (address_expr == NULL) |
3104 | ip->complete_p = 1; | |
3105 | else if (*reloc_type <= BFD_RELOC_UNUSED | |
3106 | && address_expr->X_op == O_constant) | |
3107 | { | |
3108 | unsigned int tmp; | |
3109 | ||
3110 | ip->complete_p = 1; | |
3111 | switch (*reloc_type) | |
3112 | { | |
3113 | case BFD_RELOC_32: | |
3114 | ip->insn_opcode |= address_expr->X_add_number; | |
3115 | break; | |
3116 | ||
3117 | case BFD_RELOC_MIPS_HIGHEST: | |
3118 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; | |
3119 | ip->insn_opcode |= tmp & 0xffff; | |
3120 | break; | |
3121 | ||
3122 | case BFD_RELOC_MIPS_HIGHER: | |
3123 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; | |
3124 | ip->insn_opcode |= tmp & 0xffff; | |
3125 | break; | |
3126 | ||
3127 | case BFD_RELOC_HI16_S: | |
3128 | tmp = (address_expr->X_add_number + 0x8000) >> 16; | |
3129 | ip->insn_opcode |= tmp & 0xffff; | |
3130 | break; | |
3131 | ||
3132 | case BFD_RELOC_HI16: | |
3133 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
3134 | break; | |
3135 | ||
3136 | case BFD_RELOC_UNUSED: | |
3137 | case BFD_RELOC_LO16: | |
3138 | case BFD_RELOC_MIPS_GOT_DISP: | |
3139 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; | |
3140 | break; | |
3141 | ||
3142 | case BFD_RELOC_MIPS_JMP: | |
3143 | if ((address_expr->X_add_number & 3) != 0) | |
3144 | as_bad (_("jump to misaligned address (0x%lx)"), | |
3145 | (unsigned long) address_expr->X_add_number); | |
3146 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
3147 | ip->complete_p = 0; | |
3148 | break; | |
3149 | ||
3150 | case BFD_RELOC_MIPS16_JMP: | |
3151 | if ((address_expr->X_add_number & 3) != 0) | |
3152 | as_bad (_("jump to misaligned address (0x%lx)"), | |
3153 | (unsigned long) address_expr->X_add_number); | |
3154 | ip->insn_opcode |= | |
3155 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
3156 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
3157 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
3158 | ip->complete_p = 0; | |
3159 | break; | |
3160 | ||
3161 | case BFD_RELOC_16_PCREL_S2: | |
3162 | if ((address_expr->X_add_number & 3) != 0) | |
3163 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3164 | (unsigned long) address_expr->X_add_number); | |
3165 | if (mips_relax_branch) | |
3166 | goto need_reloc; | |
3167 | if ((address_expr->X_add_number + 0x20000) & ~0x3ffff) | |
3168 | as_bad (_("branch address range overflow (0x%lx)"), | |
3169 | (unsigned long) address_expr->X_add_number); | |
3170 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff; | |
3171 | ip->complete_p = 0; | |
3172 | break; | |
3173 | ||
3174 | default: | |
3175 | internalError (); | |
3176 | } | |
3177 | } | |
3178 | ||
71400594 RS |
3179 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
3180 | { | |
3181 | /* There are a lot of optimizations we could do that we don't. | |
3182 | In particular, we do not, in general, reorder instructions. | |
3183 | If you use gcc with optimization, it will reorder | |
3184 | instructions and generally do much more optimization then we | |
3185 | do here; repeating all that work in the assembler would only | |
3186 | benefit hand written assembly code, and does not seem worth | |
3187 | it. */ | |
3188 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
3189 | ? nops_for_insn (0, history, NULL) |
3190 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 3191 | if (nops > 0) |
252b5132 RH |
3192 | { |
3193 | fragS *old_frag; | |
3194 | unsigned long old_frag_offset; | |
3195 | int i; | |
252b5132 RH |
3196 | |
3197 | old_frag = frag_now; | |
3198 | old_frag_offset = frag_now_fix (); | |
3199 | ||
3200 | for (i = 0; i < nops; i++) | |
3201 | emit_nop (); | |
3202 | ||
3203 | if (listing) | |
3204 | { | |
3205 | listing_prev_line (); | |
3206 | /* We may be at the start of a variant frag. In case we | |
3207 | are, make sure there is enough space for the frag | |
3208 | after the frags created by listing_prev_line. The | |
3209 | argument to frag_grow here must be at least as large | |
3210 | as the argument to all other calls to frag_grow in | |
3211 | this file. We don't have to worry about being in the | |
3212 | middle of a variant frag, because the variants insert | |
3213 | all needed nop instructions themselves. */ | |
3214 | frag_grow (40); | |
3215 | } | |
3216 | ||
404a8071 | 3217 | mips_move_labels (); |
252b5132 RH |
3218 | |
3219 | #ifndef NO_ECOFF_DEBUGGING | |
3220 | if (ECOFF_DEBUGGING) | |
3221 | ecoff_fix_loc (old_frag, old_frag_offset); | |
3222 | #endif | |
3223 | } | |
71400594 RS |
3224 | } |
3225 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
3226 | { | |
932d1a1b RS |
3227 | int nops; |
3228 | ||
3229 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
3230 | ignoring hazards generated by the first prev_nop_frag_since | |
3231 | instructions. */ | |
3232 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 3233 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 3234 | |
71400594 RS |
3235 | /* Enforce NOPS as a minimum. */ |
3236 | if (nops > prev_nop_frag_required) | |
3237 | prev_nop_frag_required = nops; | |
252b5132 | 3238 | |
71400594 RS |
3239 | if (prev_nop_frag_holds == prev_nop_frag_required) |
3240 | { | |
3241 | /* Settle for the current number of nops. Update the history | |
3242 | accordingly (for the benefit of any future .set reorder code). */ | |
3243 | prev_nop_frag = NULL; | |
3244 | insert_into_history (prev_nop_frag_since, | |
3245 | prev_nop_frag_holds, NOP_INSN); | |
3246 | } | |
3247 | else | |
3248 | { | |
3249 | /* Allow this instruction to replace one of the nops that was | |
3250 | tentatively added to prev_nop_frag. */ | |
3251 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
3252 | prev_nop_frag_holds--; | |
3253 | prev_nop_frag_since++; | |
252b5132 RH |
3254 | } |
3255 | } | |
3256 | ||
58e2ea4d MR |
3257 | #ifdef OBJ_ELF |
3258 | /* The value passed to dwarf2_emit_insn is the distance between | |
3259 | the beginning of the current instruction and the address that | |
3260 | should be recorded in the debug tables. For MIPS16 debug info | |
3261 | we want to use ISA-encoded addresses, so we pass -1 for an | |
3262 | address higher by one than the current. */ | |
3263 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
3264 | #endif | |
3265 | ||
895921c9 | 3266 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
3267 | if (history[0].frag) |
3268 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 3269 | |
4d7206a2 | 3270 | if (address_expr |
0b25d3e6 | 3271 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
3272 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
3273 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
3274 | && mips_relax_branch | |
3275 | /* Don't try branch relaxation within .set nomacro, or within | |
3276 | .set noat if we use $at for PIC computations. If it turns | |
3277 | out that the branch was out-of-range, we'll get an error. */ | |
3278 | && !mips_opts.warn_about_macros | |
741fe287 | 3279 | && (mips_opts.at || mips_pic == NO_PIC) |
d455268f MR |
3280 | /* Don't relax BPOSGE32/64 as they have no complementing branches. */ |
3281 | && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP)) | |
4a6a3df4 AO |
3282 | && !mips_opts.mips16) |
3283 | { | |
895921c9 | 3284 | relaxed_branch = TRUE; |
1e915849 RS |
3285 | add_relaxed_insn (ip, (relaxed_branch_length |
3286 | (NULL, NULL, | |
3287 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
3288 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
3289 | : 0)), 4, | |
3290 | RELAX_BRANCH_ENCODE | |
66b3e8da MR |
3291 | (AT, |
3292 | pinfo & INSN_UNCOND_BRANCH_DELAY, | |
1e915849 RS |
3293 | pinfo & INSN_COND_BRANCH_LIKELY, |
3294 | pinfo & INSN_WRITE_GPR_31, | |
3295 | 0), | |
3296 | address_expr->X_add_symbol, | |
3297 | address_expr->X_add_number); | |
4a6a3df4 AO |
3298 | *reloc_type = BFD_RELOC_UNUSED; |
3299 | } | |
3300 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
3301 | { |
3302 | /* We need to set up a variant frag. */ | |
9c2799c2 | 3303 | gas_assert (mips_opts.mips16 && address_expr != NULL); |
1e915849 RS |
3304 | add_relaxed_insn (ip, 4, 0, |
3305 | RELAX_MIPS16_ENCODE | |
3306 | (*reloc_type - BFD_RELOC_UNUSED, | |
3307 | mips16_small, mips16_ext, | |
3308 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
3309 | history[0].mips16_absolute_jump_p), | |
3310 | make_expr_symbol (address_expr), 0); | |
252b5132 | 3311 | } |
252b5132 RH |
3312 | else if (mips_opts.mips16 |
3313 | && ! ip->use_extend | |
f6688943 | 3314 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 3315 | { |
b8ee1a6e DU |
3316 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0) |
3317 | /* Make sure there is enough room to swap this instruction with | |
3318 | a following jump instruction. */ | |
3319 | frag_grow (6); | |
1e915849 | 3320 | add_fixed_insn (ip); |
252b5132 RH |
3321 | } |
3322 | else | |
3323 | { | |
3324 | if (mips_opts.mips16 | |
3325 | && mips_opts.noreorder | |
3326 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
3327 | as_warn (_("extended instruction in delay slot")); | |
3328 | ||
4d7206a2 RS |
3329 | if (mips_relax.sequence) |
3330 | { | |
3331 | /* If we've reached the end of this frag, turn it into a variant | |
3332 | frag and record the information for the instructions we've | |
3333 | written so far. */ | |
3334 | if (frag_room () < 4) | |
3335 | relax_close_frag (); | |
3336 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
3337 | } | |
3338 | ||
584892a6 RS |
3339 | if (mips_relax.sequence != 2) |
3340 | mips_macro_warning.sizes[0] += 4; | |
3341 | if (mips_relax.sequence != 1) | |
3342 | mips_macro_warning.sizes[1] += 4; | |
3343 | ||
1e915849 RS |
3344 | if (mips_opts.mips16) |
3345 | { | |
3346 | ip->fixed_p = 1; | |
3347 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
3348 | } | |
3349 | add_fixed_insn (ip); | |
252b5132 RH |
3350 | } |
3351 | ||
01a3f561 | 3352 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 | 3353 | { |
15be625d CM |
3354 | if (!ip->complete_p |
3355 | && *reloc_type < BFD_RELOC_UNUSED) | |
252b5132 | 3356 | need_reloc: |
4d7206a2 RS |
3357 | { |
3358 | reloc_howto_type *howto; | |
3359 | int i; | |
34ce925e | 3360 | |
4d7206a2 RS |
3361 | /* In a compound relocation, it is the final (outermost) |
3362 | operator that determines the relocated field. */ | |
3363 | for (i = 1; i < 3; i++) | |
3364 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
3365 | break; | |
34ce925e | 3366 | |
4d7206a2 | 3367 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
23fce1e3 NC |
3368 | if (howto == NULL) |
3369 | { | |
3370 | /* To reproduce this failure try assembling gas/testsuites/ | |
3371 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
3372 | assembler. */ | |
3373 | as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]); | |
3374 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); | |
3375 | } | |
3376 | ||
1e915849 RS |
3377 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
3378 | bfd_get_reloc_size (howto), | |
3379 | address_expr, | |
3380 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
3381 | reloc_type[0]); | |
4d7206a2 | 3382 | |
b314ec0e RS |
3383 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ |
3384 | if (reloc_type[0] == BFD_RELOC_MIPS16_JMP | |
3385 | && ip->fixp[0]->fx_addsy) | |
3386 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; | |
3387 | ||
4d7206a2 RS |
3388 | /* These relocations can have an addend that won't fit in |
3389 | 4 octets for 64bit assembly. */ | |
3390 | if (HAVE_64BIT_GPRS | |
3391 | && ! howto->partial_inplace | |
3392 | && (reloc_type[0] == BFD_RELOC_16 | |
3393 | || reloc_type[0] == BFD_RELOC_32 | |
3394 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4d7206a2 RS |
3395 | || reloc_type[0] == BFD_RELOC_GPREL16 |
3396 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
3397 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
3398 | || reloc_type[0] == BFD_RELOC_64 | |
3399 | || reloc_type[0] == BFD_RELOC_CTOR | |
3400 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
3401 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
3402 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
3403 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
3404 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
3405 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
3406 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
738e5348 RS |
3407 | || hi16_reloc_p (reloc_type[0]) |
3408 | || lo16_reloc_p (reloc_type[0]))) | |
1e915849 | 3409 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
3410 | |
3411 | if (mips_relax.sequence) | |
3412 | { | |
3413 | if (mips_relax.first_fixup == 0) | |
1e915849 | 3414 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
3415 | } |
3416 | else if (reloc_needs_lo_p (*reloc_type)) | |
3417 | { | |
3418 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 3419 | |
4d7206a2 RS |
3420 | /* Reuse the last entry if it already has a matching %lo. */ |
3421 | hi_fixup = mips_hi_fixup_list; | |
3422 | if (hi_fixup == 0 | |
3423 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
3424 | { | |
3425 | hi_fixup = ((struct mips_hi_fixup *) | |
3426 | xmalloc (sizeof (struct mips_hi_fixup))); | |
3427 | hi_fixup->next = mips_hi_fixup_list; | |
3428 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 3429 | } |
1e915849 | 3430 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
3431 | hi_fixup->seg = now_seg; |
3432 | } | |
f6688943 | 3433 | |
4d7206a2 RS |
3434 | /* Add fixups for the second and third relocations, if given. |
3435 | Note that the ABI allows the second relocation to be | |
3436 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
3437 | moment we only use RSS_UNDEF, but we could add support | |
3438 | for the others if it ever becomes necessary. */ | |
3439 | for (i = 1; i < 3; i++) | |
3440 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
3441 | { | |
1e915849 RS |
3442 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
3443 | ip->fixp[0]->fx_size, NULL, 0, | |
3444 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
3445 | |
3446 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
3447 | ip->fixp[0]->fx_tcbit = 1; |
3448 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 3449 | } |
252b5132 RH |
3450 | } |
3451 | } | |
1e915849 | 3452 | install_insn (ip); |
252b5132 RH |
3453 | |
3454 | /* Update the register mask information. */ | |
4c260379 RS |
3455 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
3456 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 3457 | |
4d7206a2 | 3458 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
3459 | { |
3460 | /* Filling the branch delay slot is more complex. We try to | |
3461 | switch the branch with the previous instruction, which we can | |
3462 | do if the previous instruction does not set up a condition | |
3463 | that the branch tests and if the branch is not itself the | |
3464 | target of any branch. */ | |
3465 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3466 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
3467 | { | |
3468 | if (mips_optimize < 2 | |
3469 | /* If we have seen .set volatile or .set nomove, don't | |
3470 | optimize. */ | |
3471 | || mips_opts.nomove != 0 | |
a38419a5 RS |
3472 | /* We can't swap if the previous instruction's position |
3473 | is fixed. */ | |
3474 | || history[0].fixed_p | |
252b5132 RH |
3475 | /* If the previous previous insn was in a .set |
3476 | noreorder, we can't swap. Actually, the MIPS | |
3477 | assembler will swap in this situation. However, gcc | |
3478 | configured -with-gnu-as will generate code like | |
3479 | .set noreorder | |
3480 | lw $4,XXX | |
3481 | .set reorder | |
3482 | INSN | |
3483 | bne $4,$0,foo | |
3484 | in which we can not swap the bne and INSN. If gcc is | |
3485 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 3486 | .set pseudo-ops. */ |
47e39b9d | 3487 | || history[1].noreorder_p |
252b5132 RH |
3488 | /* If the branch is itself the target of a branch, we |
3489 | can not swap. We cheat on this; all we check for is | |
3490 | whether there is a label on this instruction. If | |
3491 | there are any branches to anything other than a | |
3492 | label, users must use .set noreorder. */ | |
a8dbcb85 | 3493 | || si->label_list != NULL |
895921c9 MR |
3494 | /* If the previous instruction is in a variant frag |
3495 | other than this branch's one, we cannot do the swap. | |
3496 | This does not apply to the mips16, which uses variant | |
3497 | frags for different purposes. */ | |
252b5132 | 3498 | || (! mips_opts.mips16 |
895921c9 | 3499 | && prev_insn_frag_type == rs_machine_dependent) |
71400594 RS |
3500 | /* Check for conflicts between the branch and the instructions |
3501 | before the candidate delay slot. */ | |
932d1a1b | 3502 | || nops_for_insn (0, history + 1, ip) > 0 |
71400594 RS |
3503 | /* Check for conflicts between the swapped sequence and the |
3504 | target of the branch. */ | |
932d1a1b | 3505 | || nops_for_sequence (2, 0, history + 1, ip, history) > 0 |
252b5132 RH |
3506 | /* We do not swap with a trap instruction, since it |
3507 | complicates trap handlers to have the trap | |
3508 | instruction be in a delay slot. */ | |
3509 | || (prev_pinfo & INSN_TRAP) | |
3510 | /* If the branch reads a register that the previous | |
3511 | instruction sets, we can not swap. */ | |
4c260379 | 3512 | || (gpr_read_mask (ip) & gpr_write_mask (&history[0])) != 0 |
252b5132 | 3513 | /* If the branch writes a register that the previous |
4c260379 RS |
3514 | instruction sets, we can not swap. */ |
3515 | || (gpr_write_mask (ip) & gpr_write_mask (&history[0])) != 0 | |
252b5132 | 3516 | /* If the branch writes a register that the previous |
4c260379 RS |
3517 | instruction reads, we can not swap. */ |
3518 | || (gpr_write_mask (ip) & gpr_read_mask (&history[0])) != 0 | |
252b5132 RH |
3519 | /* If one instruction sets a condition code and the |
3520 | other one uses a condition code, we can not swap. */ | |
3521 | || ((pinfo & INSN_READ_COND_CODE) | |
3522 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3523 | || ((pinfo & INSN_WRITE_COND_CODE) | |
3524 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3525 | /* If the previous instruction uses the PC, we can not | |
3526 | swap. */ | |
3527 | || (mips_opts.mips16 | |
3528 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
3529 | /* If the previous instruction had a fixup in mips16 |
3530 | mode, we can not swap. This normally means that the | |
3531 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 3532 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
3533 | /* If the previous instruction is a sync, sync.l, or |
3534 | sync.p, we can not swap. */ | |
6a32d874 CM |
3535 | || (prev_pinfo & INSN_SYNC) |
3536 | /* If the previous instruction is an ERET or | |
3537 | DERET, avoid the swap. */ | |
3538 | || (history[0].insn_opcode == INSN_ERET) | |
3539 | || (history[0].insn_opcode == INSN_DERET)) | |
252b5132 | 3540 | { |
29024861 DU |
3541 | if (mips_opts.mips16 |
3542 | && (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3543 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)) | |
3994f87e | 3544 | && ISA_SUPPORTS_MIPS16E) |
29024861 DU |
3545 | { |
3546 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
3547 | ip->insn_opcode |= 0x0080; | |
3548 | install_insn (ip); | |
3549 | insert_into_history (0, 1, ip); | |
3550 | } | |
3551 | else | |
3552 | { | |
3553 | /* We could do even better for unconditional branches to | |
3554 | portions of this object file; we could pick up the | |
3555 | instruction at the destination, put it in the delay | |
3556 | slot, and bump the destination address. */ | |
3557 | insert_into_history (0, 1, ip); | |
3558 | emit_nop (); | |
3559 | } | |
3560 | ||
dd22970f ILT |
3561 | if (mips_relax.sequence) |
3562 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
3563 | } |
3564 | else | |
3565 | { | |
3566 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
3567 | struct mips_cl_insn delay = history[0]; |
3568 | if (mips_opts.mips16) | |
252b5132 | 3569 | { |
b8ee1a6e DU |
3570 | know (delay.frag == ip->frag); |
3571 | move_insn (ip, delay.frag, delay.where); | |
3572 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
1e915849 RS |
3573 | } |
3574 | else if (relaxed_branch) | |
3575 | { | |
3576 | /* Add the delay slot instruction to the end of the | |
3577 | current frag and shrink the fixed part of the | |
3578 | original frag. If the branch occupies the tail of | |
3579 | the latter, move it backwards to cover the gap. */ | |
3580 | delay.frag->fr_fix -= 4; | |
3581 | if (delay.frag == ip->frag) | |
3582 | move_insn (ip, ip->frag, ip->where - 4); | |
3583 | add_fixed_insn (&delay); | |
252b5132 RH |
3584 | } |
3585 | else | |
3586 | { | |
1e915849 RS |
3587 | move_insn (&delay, ip->frag, ip->where); |
3588 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 3589 | } |
1e915849 RS |
3590 | history[0] = *ip; |
3591 | delay.fixed_p = 1; | |
3592 | insert_into_history (0, 1, &delay); | |
252b5132 | 3593 | } |
252b5132 RH |
3594 | |
3595 | /* If that was an unconditional branch, forget the previous | |
3596 | insn information. */ | |
3597 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
6a32d874 | 3598 | { |
6a32d874 CM |
3599 | mips_no_prev_insn (); |
3600 | } | |
252b5132 RH |
3601 | } |
3602 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
3603 | { | |
3604 | /* We don't yet optimize a branch likely. What we should do | |
3605 | is look at the target, copy the instruction found there | |
3606 | into the delay slot, and increment the branch to jump to | |
3607 | the next instruction. */ | |
1e915849 | 3608 | insert_into_history (0, 1, ip); |
252b5132 | 3609 | emit_nop (); |
252b5132 RH |
3610 | } |
3611 | else | |
1e915849 | 3612 | insert_into_history (0, 1, ip); |
252b5132 | 3613 | } |
1e915849 RS |
3614 | else |
3615 | insert_into_history (0, 1, ip); | |
252b5132 RH |
3616 | |
3617 | /* We just output an insn, so the next one doesn't have a label. */ | |
3618 | mips_clear_insn_labels (); | |
252b5132 RH |
3619 | } |
3620 | ||
7d10b47d | 3621 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
3622 | |
3623 | static void | |
7d10b47d | 3624 | mips_no_prev_insn (void) |
252b5132 | 3625 | { |
7d10b47d RS |
3626 | prev_nop_frag = NULL; |
3627 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
3628 | mips_clear_insn_labels (); |
3629 | } | |
3630 | ||
7d10b47d RS |
3631 | /* This function must be called before we emit something other than |
3632 | instructions. It is like mips_no_prev_insn except that it inserts | |
3633 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 3634 | |
7d10b47d RS |
3635 | void |
3636 | mips_emit_delays (void) | |
252b5132 RH |
3637 | { |
3638 | if (! mips_opts.noreorder) | |
3639 | { | |
932d1a1b | 3640 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
3641 | if (nops > 0) |
3642 | { | |
7d10b47d RS |
3643 | while (nops-- > 0) |
3644 | add_fixed_insn (NOP_INSN); | |
3645 | mips_move_labels (); | |
3646 | } | |
3647 | } | |
3648 | mips_no_prev_insn (); | |
3649 | } | |
3650 | ||
3651 | /* Start a (possibly nested) noreorder block. */ | |
3652 | ||
3653 | static void | |
3654 | start_noreorder (void) | |
3655 | { | |
3656 | if (mips_opts.noreorder == 0) | |
3657 | { | |
3658 | unsigned int i; | |
3659 | int nops; | |
3660 | ||
3661 | /* None of the instructions before the .set noreorder can be moved. */ | |
3662 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
3663 | history[i].fixed_p = 1; | |
3664 | ||
3665 | /* Insert any nops that might be needed between the .set noreorder | |
3666 | block and the previous instructions. We will later remove any | |
3667 | nops that turn out not to be needed. */ | |
932d1a1b | 3668 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
3669 | if (nops > 0) |
3670 | { | |
3671 | if (mips_optimize != 0) | |
252b5132 RH |
3672 | { |
3673 | /* Record the frag which holds the nop instructions, so | |
3674 | that we can remove them if we don't need them. */ | |
3675 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
3676 | prev_nop_frag = frag_now; | |
3677 | prev_nop_frag_holds = nops; | |
3678 | prev_nop_frag_required = 0; | |
3679 | prev_nop_frag_since = 0; | |
3680 | } | |
3681 | ||
3682 | for (; nops > 0; --nops) | |
1e915849 | 3683 | add_fixed_insn (NOP_INSN); |
252b5132 | 3684 | |
7d10b47d RS |
3685 | /* Move on to a new frag, so that it is safe to simply |
3686 | decrease the size of prev_nop_frag. */ | |
3687 | frag_wane (frag_now); | |
3688 | frag_new (0); | |
404a8071 | 3689 | mips_move_labels (); |
252b5132 | 3690 | } |
7d10b47d RS |
3691 | mips16_mark_labels (); |
3692 | mips_clear_insn_labels (); | |
252b5132 | 3693 | } |
7d10b47d RS |
3694 | mips_opts.noreorder++; |
3695 | mips_any_noreorder = 1; | |
3696 | } | |
252b5132 | 3697 | |
7d10b47d | 3698 | /* End a nested noreorder block. */ |
252b5132 | 3699 | |
7d10b47d RS |
3700 | static void |
3701 | end_noreorder (void) | |
3702 | { | |
6a32d874 | 3703 | |
7d10b47d RS |
3704 | mips_opts.noreorder--; |
3705 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
3706 | { | |
3707 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
3708 | handling nop insertion the .set reorder way. */ | |
3709 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
3710 | * (mips_opts.mips16 ? 2 : 4)); | |
3711 | insert_into_history (prev_nop_frag_since, | |
3712 | prev_nop_frag_required, NOP_INSN); | |
3713 | prev_nop_frag = NULL; | |
3714 | } | |
252b5132 RH |
3715 | } |
3716 | ||
584892a6 RS |
3717 | /* Set up global variables for the start of a new macro. */ |
3718 | ||
3719 | static void | |
3720 | macro_start (void) | |
3721 | { | |
3722 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
3723 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 3724 | && (history[0].insn_mo->pinfo |
584892a6 RS |
3725 | & (INSN_UNCOND_BRANCH_DELAY |
3726 | | INSN_COND_BRANCH_DELAY | |
3727 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
3728 | } | |
3729 | ||
3730 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
3731 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
3732 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
3733 | ||
3734 | static const char * | |
3735 | macro_warning (relax_substateT subtype) | |
3736 | { | |
3737 | if (subtype & RELAX_DELAY_SLOT) | |
3738 | return _("Macro instruction expanded into multiple instructions" | |
3739 | " in a branch delay slot"); | |
3740 | else if (subtype & RELAX_NOMACRO) | |
3741 | return _("Macro instruction expanded into multiple instructions"); | |
3742 | else | |
3743 | return 0; | |
3744 | } | |
3745 | ||
3746 | /* Finish up a macro. Emit warnings as appropriate. */ | |
3747 | ||
3748 | static void | |
3749 | macro_end (void) | |
3750 | { | |
3751 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
3752 | { | |
3753 | relax_substateT subtype; | |
3754 | ||
3755 | /* Set up the relaxation warning flags. */ | |
3756 | subtype = 0; | |
3757 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
3758 | subtype |= RELAX_SECOND_LONGER; | |
3759 | if (mips_opts.warn_about_macros) | |
3760 | subtype |= RELAX_NOMACRO; | |
3761 | if (mips_macro_warning.delay_slot_p) | |
3762 | subtype |= RELAX_DELAY_SLOT; | |
3763 | ||
3764 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
3765 | { | |
3766 | /* Either the macro has a single implementation or both | |
3767 | implementations are longer than 4 bytes. Emit the | |
3768 | warning now. */ | |
3769 | const char *msg = macro_warning (subtype); | |
3770 | if (msg != 0) | |
520725ea | 3771 | as_warn ("%s", msg); |
584892a6 RS |
3772 | } |
3773 | else | |
3774 | { | |
3775 | /* One implementation might need a warning but the other | |
3776 | definitely doesn't. */ | |
3777 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
3778 | } | |
3779 | } | |
3780 | } | |
3781 | ||
6e1304d8 RS |
3782 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
3783 | The first argument in *ARGS will be either the code for a single | |
3784 | relocation or -1 followed by the three codes that make up a | |
3785 | composite relocation. */ | |
3786 | ||
3787 | static void | |
3788 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
3789 | { | |
3790 | int i, next; | |
3791 | ||
3792 | next = va_arg (*args, int); | |
3793 | if (next >= 0) | |
3794 | r[0] = (bfd_reloc_code_real_type) next; | |
3795 | else | |
3796 | for (i = 0; i < 3; i++) | |
3797 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
3798 | } | |
3799 | ||
252b5132 RH |
3800 | /* Build an instruction created by a macro expansion. This is passed |
3801 | a pointer to the count of instructions created so far, an | |
3802 | expression, the name of the instruction to build, an operand format | |
3803 | string, and corresponding arguments. */ | |
3804 | ||
252b5132 | 3805 | static void |
67c0d1eb | 3806 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 3807 | { |
1e915849 | 3808 | const struct mips_opcode *mo; |
252b5132 | 3809 | struct mips_cl_insn insn; |
f6688943 | 3810 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3811 | va_list args; |
252b5132 | 3812 | |
252b5132 | 3813 | va_start (args, fmt); |
252b5132 | 3814 | |
252b5132 RH |
3815 | if (mips_opts.mips16) |
3816 | { | |
03ea81db | 3817 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
3818 | va_end (args); |
3819 | return; | |
3820 | } | |
3821 | ||
f6688943 TS |
3822 | r[0] = BFD_RELOC_UNUSED; |
3823 | r[1] = BFD_RELOC_UNUSED; | |
3824 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 | 3825 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
9c2799c2 NC |
3826 | gas_assert (mo); |
3827 | gas_assert (strcmp (name, mo->name) == 0); | |
1e915849 | 3828 | |
8b082fb1 TS |
3829 | while (1) |
3830 | { | |
3831 | /* Search until we get a match for NAME. It is assumed here that | |
3832 | macros will never generate MDMX, MIPS-3D, or MT instructions. */ | |
3833 | if (strcmp (fmt, mo->args) == 0 | |
3834 | && mo->pinfo != INSN_MACRO | |
f79e2745 | 3835 | && is_opcode_valid (mo)) |
8b082fb1 TS |
3836 | break; |
3837 | ||
1e915849 | 3838 | ++mo; |
9c2799c2 NC |
3839 | gas_assert (mo->name); |
3840 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3841 | } |
3842 | ||
1e915849 | 3843 | create_insn (&insn, mo); |
252b5132 RH |
3844 | for (;;) |
3845 | { | |
3846 | switch (*fmt++) | |
3847 | { | |
3848 | case '\0': | |
3849 | break; | |
3850 | ||
3851 | case ',': | |
3852 | case '(': | |
3853 | case ')': | |
3854 | continue; | |
3855 | ||
5f74bc13 CD |
3856 | case '+': |
3857 | switch (*fmt++) | |
3858 | { | |
3859 | case 'A': | |
3860 | case 'E': | |
bf12938e | 3861 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
3862 | continue; |
3863 | ||
3864 | case 'B': | |
3865 | case 'F': | |
3866 | /* Note that in the macro case, these arguments are already | |
3867 | in MSB form. (When handling the instruction in the | |
3868 | non-macro case, these arguments are sizes from which | |
3869 | MSB values must be calculated.) */ | |
bf12938e | 3870 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3871 | continue; |
3872 | ||
3873 | case 'C': | |
3874 | case 'G': | |
3875 | case 'H': | |
3876 | /* Note that in the macro case, these arguments are already | |
3877 | in MSBD form. (When handling the instruction in the | |
3878 | non-macro case, these arguments are sizes from which | |
3879 | MSBD values must be calculated.) */ | |
bf12938e | 3880 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3881 | continue; |
3882 | ||
dd3cbb7e NC |
3883 | case 'Q': |
3884 | INSERT_OPERAND (SEQI, insn, va_arg (args, int)); | |
3885 | continue; | |
3886 | ||
5f74bc13 CD |
3887 | default: |
3888 | internalError (); | |
3889 | } | |
3890 | continue; | |
3891 | ||
8b082fb1 TS |
3892 | case '2': |
3893 | INSERT_OPERAND (BP, insn, va_arg (args, int)); | |
3894 | continue; | |
3895 | ||
252b5132 RH |
3896 | case 't': |
3897 | case 'w': | |
3898 | case 'E': | |
bf12938e | 3899 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3900 | continue; |
3901 | ||
3902 | case 'c': | |
bf12938e | 3903 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3904 | continue; |
3905 | ||
252b5132 RH |
3906 | case 'T': |
3907 | case 'W': | |
bf12938e | 3908 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3909 | continue; |
3910 | ||
3911 | case 'd': | |
3912 | case 'G': | |
af7ee8bf | 3913 | case 'K': |
bf12938e | 3914 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3915 | continue; |
3916 | ||
4372b673 NC |
3917 | case 'U': |
3918 | { | |
3919 | int tmp = va_arg (args, int); | |
3920 | ||
bf12938e RS |
3921 | INSERT_OPERAND (RT, insn, tmp); |
3922 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3923 | continue; |
4372b673 NC |
3924 | } |
3925 | ||
252b5132 RH |
3926 | case 'V': |
3927 | case 'S': | |
bf12938e | 3928 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3929 | continue; |
3930 | ||
3931 | case 'z': | |
3932 | continue; | |
3933 | ||
3934 | case '<': | |
bf12938e | 3935 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3936 | continue; |
3937 | ||
3938 | case 'D': | |
bf12938e | 3939 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3940 | continue; |
3941 | ||
3942 | case 'B': | |
bf12938e | 3943 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3944 | continue; |
3945 | ||
4372b673 | 3946 | case 'J': |
bf12938e | 3947 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3948 | continue; |
3949 | ||
252b5132 | 3950 | case 'q': |
bf12938e | 3951 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3952 | continue; |
3953 | ||
3954 | case 'b': | |
3955 | case 's': | |
3956 | case 'r': | |
3957 | case 'v': | |
bf12938e | 3958 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3959 | continue; |
3960 | ||
3961 | case 'i': | |
3962 | case 'j': | |
6e1304d8 | 3963 | macro_read_relocs (&args, r); |
9c2799c2 | 3964 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
3965 | || *r == BFD_RELOC_MIPS_HIGHER |
3966 | || *r == BFD_RELOC_HI16_S | |
3967 | || *r == BFD_RELOC_LO16 | |
3968 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
3969 | continue; | |
3970 | ||
3971 | case 'o': | |
3972 | macro_read_relocs (&args, r); | |
252b5132 RH |
3973 | continue; |
3974 | ||
3975 | case 'u': | |
6e1304d8 | 3976 | macro_read_relocs (&args, r); |
9c2799c2 | 3977 | gas_assert (ep != NULL |
90ecf173 MR |
3978 | && (ep->X_op == O_constant |
3979 | || (ep->X_op == O_symbol | |
3980 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
3981 | || *r == BFD_RELOC_HI16_S | |
3982 | || *r == BFD_RELOC_HI16 | |
3983 | || *r == BFD_RELOC_GPREL16 | |
3984 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3985 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
3986 | continue; |
3987 | ||
3988 | case 'p': | |
9c2799c2 | 3989 | gas_assert (ep != NULL); |
bad36eac | 3990 | |
252b5132 RH |
3991 | /* |
3992 | * This allows macro() to pass an immediate expression for | |
3993 | * creating short branches without creating a symbol. | |
bad36eac DJ |
3994 | * |
3995 | * We don't allow branch relaxation for these branches, as | |
3996 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
3997 | */ |
3998 | if (ep->X_op == O_constant) | |
3999 | { | |
bad36eac DJ |
4000 | if ((ep->X_add_number & 3) != 0) |
4001 | as_bad (_("branch to misaligned address (0x%lx)"), | |
4002 | (unsigned long) ep->X_add_number); | |
4003 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
4004 | as_bad (_("branch address range overflow (0x%lx)"), | |
4005 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
4006 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
4007 | ep = NULL; | |
4008 | } | |
4009 | else | |
0b25d3e6 | 4010 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
4011 | continue; |
4012 | ||
4013 | case 'a': | |
9c2799c2 | 4014 | gas_assert (ep != NULL); |
f6688943 | 4015 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
4016 | continue; |
4017 | ||
4018 | case 'C': | |
a9e24354 | 4019 | INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long)); |
252b5132 RH |
4020 | continue; |
4021 | ||
d43b4baf | 4022 | case 'k': |
a9e24354 | 4023 | INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long)); |
d43b4baf TS |
4024 | continue; |
4025 | ||
252b5132 RH |
4026 | default: |
4027 | internalError (); | |
4028 | } | |
4029 | break; | |
4030 | } | |
4031 | va_end (args); | |
9c2799c2 | 4032 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 4033 | |
4d7206a2 | 4034 | append_insn (&insn, ep, r); |
252b5132 RH |
4035 | } |
4036 | ||
4037 | static void | |
67c0d1eb | 4038 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 4039 | va_list *args) |
252b5132 | 4040 | { |
1e915849 | 4041 | struct mips_opcode *mo; |
252b5132 | 4042 | struct mips_cl_insn insn; |
f6688943 TS |
4043 | bfd_reloc_code_real_type r[3] |
4044 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 4045 | |
1e915849 | 4046 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
4047 | gas_assert (mo); |
4048 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 4049 | |
1e915849 | 4050 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 4051 | { |
1e915849 | 4052 | ++mo; |
9c2799c2 NC |
4053 | gas_assert (mo->name); |
4054 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
4055 | } |
4056 | ||
1e915849 | 4057 | create_insn (&insn, mo); |
252b5132 RH |
4058 | for (;;) |
4059 | { | |
4060 | int c; | |
4061 | ||
4062 | c = *fmt++; | |
4063 | switch (c) | |
4064 | { | |
4065 | case '\0': | |
4066 | break; | |
4067 | ||
4068 | case ',': | |
4069 | case '(': | |
4070 | case ')': | |
4071 | continue; | |
4072 | ||
4073 | case 'y': | |
4074 | case 'w': | |
03ea81db | 4075 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
4076 | continue; |
4077 | ||
4078 | case 'x': | |
4079 | case 'v': | |
03ea81db | 4080 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
4081 | continue; |
4082 | ||
4083 | case 'z': | |
03ea81db | 4084 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
4085 | continue; |
4086 | ||
4087 | case 'Z': | |
03ea81db | 4088 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
4089 | continue; |
4090 | ||
4091 | case '0': | |
4092 | case 'S': | |
4093 | case 'P': | |
4094 | case 'R': | |
4095 | continue; | |
4096 | ||
4097 | case 'X': | |
03ea81db | 4098 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
4099 | continue; |
4100 | ||
4101 | case 'Y': | |
4102 | { | |
4103 | int regno; | |
4104 | ||
03ea81db | 4105 | regno = va_arg (*args, int); |
252b5132 | 4106 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 4107 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
4108 | } |
4109 | continue; | |
4110 | ||
4111 | case '<': | |
4112 | case '>': | |
4113 | case '4': | |
4114 | case '5': | |
4115 | case 'H': | |
4116 | case 'W': | |
4117 | case 'D': | |
4118 | case 'j': | |
4119 | case '8': | |
4120 | case 'V': | |
4121 | case 'C': | |
4122 | case 'U': | |
4123 | case 'k': | |
4124 | case 'K': | |
4125 | case 'p': | |
4126 | case 'q': | |
4127 | { | |
9c2799c2 | 4128 | gas_assert (ep != NULL); |
252b5132 RH |
4129 | |
4130 | if (ep->X_op != O_constant) | |
874e8986 | 4131 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
4132 | else |
4133 | { | |
b34976b6 AM |
4134 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
4135 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 4136 | &insn.extend); |
252b5132 | 4137 | ep = NULL; |
f6688943 | 4138 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
4139 | } |
4140 | } | |
4141 | continue; | |
4142 | ||
4143 | case '6': | |
03ea81db | 4144 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
4145 | continue; |
4146 | } | |
4147 | ||
4148 | break; | |
4149 | } | |
4150 | ||
9c2799c2 | 4151 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 4152 | |
4d7206a2 | 4153 | append_insn (&insn, ep, r); |
252b5132 RH |
4154 | } |
4155 | ||
2051e8c4 MR |
4156 | /* |
4157 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
4158 | * higher bits unset. | |
4159 | */ | |
9f872bbe | 4160 | static void |
2051e8c4 MR |
4161 | normalize_constant_expr (expressionS *ex) |
4162 | { | |
9ee2a2d4 | 4163 | if (ex->X_op == O_constant |
2051e8c4 MR |
4164 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
4165 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
4166 | - 0x80000000); | |
4167 | } | |
4168 | ||
4169 | /* | |
4170 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
4171 | * all higher bits unset. | |
4172 | */ | |
4173 | static void | |
4174 | normalize_address_expr (expressionS *ex) | |
4175 | { | |
4176 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
4177 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
4178 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
4179 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
4180 | - 0x80000000); | |
4181 | } | |
4182 | ||
438c16b8 TS |
4183 | /* |
4184 | * Generate a "jalr" instruction with a relocation hint to the called | |
4185 | * function. This occurs in NewABI PIC code. | |
4186 | */ | |
4187 | static void | |
67c0d1eb | 4188 | macro_build_jalr (expressionS *ep) |
438c16b8 | 4189 | { |
685736be | 4190 | char *f = NULL; |
b34976b6 | 4191 | |
1180b5a4 | 4192 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 4193 | { |
cc3d92a5 | 4194 | frag_grow (8); |
f21f8242 AO |
4195 | f = frag_more (0); |
4196 | } | |
67c0d1eb | 4197 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
1180b5a4 | 4198 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 4199 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 4200 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
4201 | } |
4202 | ||
252b5132 RH |
4203 | /* |
4204 | * Generate a "lui" instruction. | |
4205 | */ | |
4206 | static void | |
67c0d1eb | 4207 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
4208 | { |
4209 | expressionS high_expr; | |
1e915849 | 4210 | const struct mips_opcode *mo; |
252b5132 | 4211 | struct mips_cl_insn insn; |
f6688943 TS |
4212 | bfd_reloc_code_real_type r[3] |
4213 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
4214 | const char *name = "lui"; |
4215 | const char *fmt = "t,u"; | |
252b5132 | 4216 | |
9c2799c2 | 4217 | gas_assert (! mips_opts.mips16); |
252b5132 | 4218 | |
4d7206a2 | 4219 | high_expr = *ep; |
252b5132 RH |
4220 | |
4221 | if (high_expr.X_op == O_constant) | |
4222 | { | |
54f4ddb3 | 4223 | /* We can compute the instruction now without a relocation entry. */ |
e7d556df TS |
4224 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
4225 | >> 16) & 0xffff; | |
f6688943 | 4226 | *r = BFD_RELOC_UNUSED; |
252b5132 | 4227 | } |
78e1bb40 | 4228 | else |
252b5132 | 4229 | { |
9c2799c2 | 4230 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
4231 | /* _gp_disp is a special case, used from s_cpload. |
4232 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 4233 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 4234 | || (! HAVE_NEWABI |
aa6975fb ILT |
4235 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
4236 | || (! mips_in_shared | |
bbe506e8 TS |
4237 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
4238 | "__gnu_local_gp") == 0)); | |
f6688943 | 4239 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
4240 | } |
4241 | ||
1e915849 | 4242 | mo = hash_find (op_hash, name); |
9c2799c2 NC |
4243 | gas_assert (strcmp (name, mo->name) == 0); |
4244 | gas_assert (strcmp (fmt, mo->args) == 0); | |
1e915849 | 4245 | create_insn (&insn, mo); |
252b5132 | 4246 | |
bf12938e RS |
4247 | insn.insn_opcode = insn.insn_mo->match; |
4248 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 4249 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
4250 | { |
4251 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 4252 | append_insn (&insn, NULL, r); |
252b5132 RH |
4253 | } |
4254 | else | |
4d7206a2 | 4255 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
4256 | } |
4257 | ||
885add95 CD |
4258 | /* Generate a sequence of instructions to do a load or store from a constant |
4259 | offset off of a base register (breg) into/from a target register (treg), | |
4260 | using AT if necessary. */ | |
4261 | static void | |
67c0d1eb RS |
4262 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
4263 | int treg, int breg, int dbl) | |
885add95 | 4264 | { |
9c2799c2 | 4265 | gas_assert (ep->X_op == O_constant); |
885add95 | 4266 | |
256ab948 | 4267 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
4268 | if (!dbl) |
4269 | normalize_constant_expr (ep); | |
256ab948 | 4270 | |
67c1ffbe | 4271 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 4272 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
4273 | as_warn (_("operand overflow")); |
4274 | ||
4275 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
4276 | { | |
4277 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 4278 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
4279 | } |
4280 | else | |
4281 | { | |
4282 | /* 32-bit offset, need multiple instructions and AT, like: | |
4283 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
4284 | addu $tempreg,$tempreg,$breg | |
4285 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
4286 | to handle the complete offset. */ | |
67c0d1eb RS |
4287 | macro_build_lui (ep, AT); |
4288 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
4289 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 4290 | |
741fe287 | 4291 | if (!mips_opts.at) |
8fc2e39e | 4292 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
4293 | } |
4294 | } | |
4295 | ||
252b5132 RH |
4296 | /* set_at() |
4297 | * Generates code to set the $at register to true (one) | |
4298 | * if reg is less than the immediate expression. | |
4299 | */ | |
4300 | static void | |
67c0d1eb | 4301 | set_at (int reg, int unsignedp) |
252b5132 RH |
4302 | { |
4303 | if (imm_expr.X_op == O_constant | |
4304 | && imm_expr.X_add_number >= -0x8000 | |
4305 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
4306 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
4307 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
4308 | else |
4309 | { | |
67c0d1eb RS |
4310 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4311 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
4312 | } |
4313 | } | |
4314 | ||
4315 | /* Warn if an expression is not a constant. */ | |
4316 | ||
4317 | static void | |
17a2f251 | 4318 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
4319 | { |
4320 | if (ex->X_op == O_big) | |
4321 | as_bad (_("unsupported large constant")); | |
4322 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
4323 | as_bad (_("Instruction %s requires absolute expression"), |
4324 | ip->insn_mo->name); | |
13757d0c | 4325 | |
9ee2a2d4 MR |
4326 | if (HAVE_32BIT_GPRS) |
4327 | normalize_constant_expr (ex); | |
252b5132 RH |
4328 | } |
4329 | ||
4330 | /* Count the leading zeroes by performing a binary chop. This is a | |
4331 | bulky bit of source, but performance is a LOT better for the | |
4332 | majority of values than a simple loop to count the bits: | |
4333 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
4334 | if ((v) & (1 << (31 - lcnt))) | |
4335 | break; | |
4336 | However it is not code size friendly, and the gain will drop a bit | |
4337 | on certain cached systems. | |
4338 | */ | |
4339 | #define COUNT_TOP_ZEROES(v) \ | |
4340 | (((v) & ~0xffff) == 0 \ | |
4341 | ? ((v) & ~0xff) == 0 \ | |
4342 | ? ((v) & ~0xf) == 0 \ | |
4343 | ? ((v) & ~0x3) == 0 \ | |
4344 | ? ((v) & ~0x1) == 0 \ | |
4345 | ? !(v) \ | |
4346 | ? 32 \ | |
4347 | : 31 \ | |
4348 | : 30 \ | |
4349 | : ((v) & ~0x7) == 0 \ | |
4350 | ? 29 \ | |
4351 | : 28 \ | |
4352 | : ((v) & ~0x3f) == 0 \ | |
4353 | ? ((v) & ~0x1f) == 0 \ | |
4354 | ? 27 \ | |
4355 | : 26 \ | |
4356 | : ((v) & ~0x7f) == 0 \ | |
4357 | ? 25 \ | |
4358 | : 24 \ | |
4359 | : ((v) & ~0xfff) == 0 \ | |
4360 | ? ((v) & ~0x3ff) == 0 \ | |
4361 | ? ((v) & ~0x1ff) == 0 \ | |
4362 | ? 23 \ | |
4363 | : 22 \ | |
4364 | : ((v) & ~0x7ff) == 0 \ | |
4365 | ? 21 \ | |
4366 | : 20 \ | |
4367 | : ((v) & ~0x3fff) == 0 \ | |
4368 | ? ((v) & ~0x1fff) == 0 \ | |
4369 | ? 19 \ | |
4370 | : 18 \ | |
4371 | : ((v) & ~0x7fff) == 0 \ | |
4372 | ? 17 \ | |
4373 | : 16 \ | |
4374 | : ((v) & ~0xffffff) == 0 \ | |
4375 | ? ((v) & ~0xfffff) == 0 \ | |
4376 | ? ((v) & ~0x3ffff) == 0 \ | |
4377 | ? ((v) & ~0x1ffff) == 0 \ | |
4378 | ? 15 \ | |
4379 | : 14 \ | |
4380 | : ((v) & ~0x7ffff) == 0 \ | |
4381 | ? 13 \ | |
4382 | : 12 \ | |
4383 | : ((v) & ~0x3fffff) == 0 \ | |
4384 | ? ((v) & ~0x1fffff) == 0 \ | |
4385 | ? 11 \ | |
4386 | : 10 \ | |
4387 | : ((v) & ~0x7fffff) == 0 \ | |
4388 | ? 9 \ | |
4389 | : 8 \ | |
4390 | : ((v) & ~0xfffffff) == 0 \ | |
4391 | ? ((v) & ~0x3ffffff) == 0 \ | |
4392 | ? ((v) & ~0x1ffffff) == 0 \ | |
4393 | ? 7 \ | |
4394 | : 6 \ | |
4395 | : ((v) & ~0x7ffffff) == 0 \ | |
4396 | ? 5 \ | |
4397 | : 4 \ | |
4398 | : ((v) & ~0x3fffffff) == 0 \ | |
4399 | ? ((v) & ~0x1fffffff) == 0 \ | |
4400 | ? 3 \ | |
4401 | : 2 \ | |
4402 | : ((v) & ~0x7fffffff) == 0 \ | |
4403 | ? 1 \ | |
4404 | : 0) | |
4405 | ||
4406 | /* load_register() | |
67c1ffbe | 4407 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
4408 | * an absolute expression value into a register. |
4409 | */ | |
4410 | static void | |
67c0d1eb | 4411 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
4412 | { |
4413 | int freg; | |
4414 | expressionS hi32, lo32; | |
4415 | ||
4416 | if (ep->X_op != O_big) | |
4417 | { | |
9c2799c2 | 4418 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
4419 | |
4420 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
4421 | if (!dbl) |
4422 | normalize_constant_expr (ep); | |
256ab948 TS |
4423 | |
4424 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
4425 | { |
4426 | /* We can handle 16 bit signed values with an addiu to | |
4427 | $zero. No need to ever use daddiu here, since $zero and | |
4428 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 4429 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4430 | return; |
4431 | } | |
4432 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
4433 | { | |
4434 | /* We can handle 16 bit unsigned values with an ori to | |
4435 | $zero. */ | |
67c0d1eb | 4436 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4437 | return; |
4438 | } | |
256ab948 | 4439 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
4440 | { |
4441 | /* 32 bit values require an lui. */ | |
67c0d1eb | 4442 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4443 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 4444 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
4445 | return; |
4446 | } | |
4447 | } | |
4448 | ||
4449 | /* The value is larger than 32 bits. */ | |
4450 | ||
2051e8c4 | 4451 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 4452 | { |
55e08f71 NC |
4453 | char value[32]; |
4454 | ||
4455 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 4456 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 4457 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4458 | return; |
4459 | } | |
4460 | ||
4461 | if (ep->X_op != O_big) | |
4462 | { | |
4463 | hi32 = *ep; | |
4464 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4465 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4466 | hi32.X_add_number &= 0xffffffff; | |
4467 | lo32 = *ep; | |
4468 | lo32.X_add_number &= 0xffffffff; | |
4469 | } | |
4470 | else | |
4471 | { | |
9c2799c2 | 4472 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
4473 | if (ep->X_add_number == 3) |
4474 | generic_bignum[3] = 0; | |
4475 | else if (ep->X_add_number > 4) | |
4476 | as_bad (_("Number larger than 64 bits")); | |
4477 | lo32.X_op = O_constant; | |
4478 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
4479 | hi32.X_op = O_constant; | |
4480 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
4481 | } | |
4482 | ||
4483 | if (hi32.X_add_number == 0) | |
4484 | freg = 0; | |
4485 | else | |
4486 | { | |
4487 | int shift, bit; | |
4488 | unsigned long hi, lo; | |
4489 | ||
956cd1d6 | 4490 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
4491 | { |
4492 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
4493 | { | |
67c0d1eb | 4494 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4495 | return; |
4496 | } | |
4497 | if (lo32.X_add_number & 0x80000000) | |
4498 | { | |
67c0d1eb | 4499 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4500 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 4501 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
4502 | return; |
4503 | } | |
4504 | } | |
252b5132 RH |
4505 | |
4506 | /* Check for 16bit shifted constant. We know that hi32 is | |
4507 | non-zero, so start the mask on the first bit of the hi32 | |
4508 | value. */ | |
4509 | shift = 17; | |
4510 | do | |
beae10d5 KH |
4511 | { |
4512 | unsigned long himask, lomask; | |
4513 | ||
4514 | if (shift < 32) | |
4515 | { | |
4516 | himask = 0xffff >> (32 - shift); | |
4517 | lomask = (0xffff << shift) & 0xffffffff; | |
4518 | } | |
4519 | else | |
4520 | { | |
4521 | himask = 0xffff << (shift - 32); | |
4522 | lomask = 0; | |
4523 | } | |
4524 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
4525 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
4526 | { | |
4527 | expressionS tmp; | |
4528 | ||
4529 | tmp.X_op = O_constant; | |
4530 | if (shift < 32) | |
4531 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
4532 | | (lo32.X_add_number >> shift)); | |
4533 | else | |
4534 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
4535 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
4536 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
4537 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4538 | return; |
4539 | } | |
f9419b05 | 4540 | ++shift; |
beae10d5 KH |
4541 | } |
4542 | while (shift <= (64 - 16)); | |
252b5132 RH |
4543 | |
4544 | /* Find the bit number of the lowest one bit, and store the | |
4545 | shifted value in hi/lo. */ | |
4546 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
4547 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
4548 | if (lo != 0) | |
4549 | { | |
4550 | bit = 0; | |
4551 | while ((lo & 1) == 0) | |
4552 | { | |
4553 | lo >>= 1; | |
4554 | ++bit; | |
4555 | } | |
4556 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
4557 | hi >>= bit; | |
4558 | } | |
4559 | else | |
4560 | { | |
4561 | bit = 32; | |
4562 | while ((hi & 1) == 0) | |
4563 | { | |
4564 | hi >>= 1; | |
4565 | ++bit; | |
4566 | } | |
4567 | lo = hi; | |
4568 | hi = 0; | |
4569 | } | |
4570 | ||
4571 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
4572 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
4573 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
4574 | { |
4575 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 4576 | if (shift != 0) |
beae10d5 | 4577 | { |
252b5132 RH |
4578 | expressionS tmp; |
4579 | ||
4580 | /* This instruction will set the register to be all | |
4581 | ones. */ | |
beae10d5 KH |
4582 | tmp.X_op = O_constant; |
4583 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 4584 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4585 | if (bit != 0) |
4586 | { | |
4587 | bit += shift; | |
67c0d1eb RS |
4588 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
4589 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 4590 | } |
67c0d1eb RS |
4591 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
4592 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4593 | return; |
4594 | } | |
4595 | } | |
252b5132 RH |
4596 | |
4597 | /* Sign extend hi32 before calling load_register, because we can | |
4598 | generally get better code when we load a sign extended value. */ | |
4599 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 4600 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 4601 | load_register (reg, &hi32, 0); |
252b5132 RH |
4602 | freg = reg; |
4603 | } | |
4604 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
4605 | { | |
4606 | if (freg != 0) | |
4607 | { | |
67c0d1eb | 4608 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
4609 | freg = reg; |
4610 | } | |
4611 | } | |
4612 | else | |
4613 | { | |
4614 | expressionS mid16; | |
4615 | ||
956cd1d6 | 4616 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 4617 | { |
67c0d1eb RS |
4618 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
4619 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
4620 | return; |
4621 | } | |
252b5132 RH |
4622 | |
4623 | if (freg != 0) | |
4624 | { | |
67c0d1eb | 4625 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
4626 | freg = reg; |
4627 | } | |
4628 | mid16 = lo32; | |
4629 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
4630 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
4631 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
4632 | freg = reg; |
4633 | } | |
4634 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 4635 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
4636 | } |
4637 | ||
269137b2 TS |
4638 | static inline void |
4639 | load_delay_nop (void) | |
4640 | { | |
4641 | if (!gpr_interlocks) | |
4642 | macro_build (NULL, "nop", ""); | |
4643 | } | |
4644 | ||
252b5132 RH |
4645 | /* Load an address into a register. */ |
4646 | ||
4647 | static void | |
67c0d1eb | 4648 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 4649 | { |
252b5132 RH |
4650 | if (ep->X_op != O_constant |
4651 | && ep->X_op != O_symbol) | |
4652 | { | |
4653 | as_bad (_("expression too complex")); | |
4654 | ep->X_op = O_constant; | |
4655 | } | |
4656 | ||
4657 | if (ep->X_op == O_constant) | |
4658 | { | |
67c0d1eb | 4659 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4660 | return; |
4661 | } | |
4662 | ||
4663 | if (mips_pic == NO_PIC) | |
4664 | { | |
4665 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 4666 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4667 | Otherwise we want |
4668 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
4669 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 4670 | If we have an addend, we always use the latter form. |
76b3015f | 4671 | |
d6bc6245 TS |
4672 | With 64bit address space and a usable $at we want |
4673 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4674 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4675 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4676 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4677 | dsll32 $reg,0 | |
3a482fd5 | 4678 | daddu $reg,$reg,$at |
76b3015f | 4679 | |
c03099e6 | 4680 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4681 | on superscalar processors. |
4682 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4683 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4684 | dsll $reg,16 | |
4685 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
4686 | dsll $reg,16 | |
4687 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
4688 | |
4689 | For GP relative symbols in 64bit address space we can use | |
4690 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4691 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 4692 | { |
6caf9ef4 TS |
4693 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
4694 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
4695 | { | |
4696 | relax_start (ep->X_add_symbol); | |
4697 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
4698 | mips_gp_register, BFD_RELOC_GPREL16); | |
4699 | relax_switch (); | |
4700 | } | |
d6bc6245 | 4701 | |
741fe287 | 4702 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 4703 | { |
67c0d1eb RS |
4704 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4705 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
4706 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4707 | BFD_RELOC_MIPS_HIGHER); | |
4708 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
4709 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
4710 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
4711 | *used_at = 1; |
4712 | } | |
4713 | else | |
4714 | { | |
67c0d1eb RS |
4715 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4716 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4717 | BFD_RELOC_MIPS_HIGHER); | |
4718 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4719 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
4720 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4721 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 4722 | } |
6caf9ef4 TS |
4723 | |
4724 | if (mips_relax.sequence) | |
4725 | relax_end (); | |
d6bc6245 | 4726 | } |
252b5132 RH |
4727 | else |
4728 | { | |
d6bc6245 | 4729 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 4730 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 4731 | { |
4d7206a2 | 4732 | relax_start (ep->X_add_symbol); |
67c0d1eb | 4733 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 4734 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 4735 | relax_switch (); |
d6bc6245 | 4736 | } |
67c0d1eb RS |
4737 | macro_build_lui (ep, reg); |
4738 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
4739 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4740 | if (mips_relax.sequence) |
4741 | relax_end (); | |
d6bc6245 | 4742 | } |
252b5132 | 4743 | } |
0a44bf69 | 4744 | else if (!mips_big_got) |
252b5132 RH |
4745 | { |
4746 | expressionS ex; | |
4747 | ||
4748 | /* If this is a reference to an external symbol, we want | |
4749 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4750 | Otherwise we want | |
4751 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4752 | nop | |
4753 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
4754 | If there is a constant, it must be added in after. |
4755 | ||
ed6fb7bd | 4756 | If we have NewABI, we want |
f5040a92 AO |
4757 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
4758 | unless we're referencing a global symbol with a non-zero | |
4759 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
4760 | if (HAVE_NEWABI) |
4761 | { | |
f5040a92 AO |
4762 | if (ep->X_add_number) |
4763 | { | |
4d7206a2 | 4764 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4765 | ep->X_add_number = 0; |
4d7206a2 | 4766 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4767 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4768 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
4769 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4770 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4771 | ex.X_op = O_constant; | |
67c0d1eb | 4772 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4773 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4774 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 4775 | relax_switch (); |
f5040a92 | 4776 | } |
67c0d1eb | 4777 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4778 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
4779 | if (mips_relax.sequence) |
4780 | relax_end (); | |
ed6fb7bd SC |
4781 | } |
4782 | else | |
4783 | { | |
f5040a92 AO |
4784 | ex.X_add_number = ep->X_add_number; |
4785 | ep->X_add_number = 0; | |
67c0d1eb RS |
4786 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4787 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 4788 | load_delay_nop (); |
4d7206a2 RS |
4789 | relax_start (ep->X_add_symbol); |
4790 | relax_switch (); | |
67c0d1eb | 4791 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4792 | BFD_RELOC_LO16); |
4d7206a2 | 4793 | relax_end (); |
ed6fb7bd | 4794 | |
f5040a92 AO |
4795 | if (ex.X_add_number != 0) |
4796 | { | |
4797 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4798 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4799 | ex.X_op = O_constant; | |
67c0d1eb | 4800 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4801 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4802 | } |
252b5132 RH |
4803 | } |
4804 | } | |
0a44bf69 | 4805 | else if (mips_big_got) |
252b5132 RH |
4806 | { |
4807 | expressionS ex; | |
252b5132 RH |
4808 | |
4809 | /* This is the large GOT case. If this is a reference to an | |
4810 | external symbol, we want | |
4811 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4812 | addu $reg,$reg,$gp | |
4813 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
4814 | |
4815 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
4816 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4817 | nop | |
4818 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 4819 | If there is a constant, it must be added in after. |
f5040a92 AO |
4820 | |
4821 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
4822 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
4823 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 4824 | */ |
438c16b8 TS |
4825 | if (HAVE_NEWABI) |
4826 | { | |
4d7206a2 | 4827 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4828 | ep->X_add_number = 0; |
4d7206a2 | 4829 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4830 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4831 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4832 | reg, reg, mips_gp_register); | |
4833 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4834 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4835 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4836 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4837 | else if (ex.X_add_number) | |
4838 | { | |
4839 | ex.X_op = O_constant; | |
67c0d1eb RS |
4840 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4841 | BFD_RELOC_LO16); | |
f5040a92 AO |
4842 | } |
4843 | ||
4844 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4845 | relax_switch (); |
67c0d1eb | 4846 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4847 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4848 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4849 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4850 | relax_end (); |
438c16b8 | 4851 | } |
252b5132 | 4852 | else |
438c16b8 | 4853 | { |
f5040a92 AO |
4854 | ex.X_add_number = ep->X_add_number; |
4855 | ep->X_add_number = 0; | |
4d7206a2 | 4856 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4857 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4858 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4859 | reg, reg, mips_gp_register); | |
4860 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4861 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4862 | relax_switch (); |
4863 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4864 | { |
4865 | /* We need a nop before loading from $gp. This special | |
4866 | check is required because the lui which starts the main | |
4867 | instruction stream does not refer to $gp, and so will not | |
4868 | insert the nop which may be required. */ | |
67c0d1eb | 4869 | macro_build (NULL, "nop", ""); |
438c16b8 | 4870 | } |
67c0d1eb | 4871 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4872 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4873 | load_delay_nop (); |
67c0d1eb | 4874 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4875 | BFD_RELOC_LO16); |
4d7206a2 | 4876 | relax_end (); |
438c16b8 | 4877 | |
f5040a92 AO |
4878 | if (ex.X_add_number != 0) |
4879 | { | |
4880 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4881 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4882 | ex.X_op = O_constant; | |
67c0d1eb RS |
4883 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4884 | BFD_RELOC_LO16); | |
f5040a92 | 4885 | } |
252b5132 RH |
4886 | } |
4887 | } | |
252b5132 RH |
4888 | else |
4889 | abort (); | |
8fc2e39e | 4890 | |
741fe287 | 4891 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 4892 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
4893 | } |
4894 | ||
ea1fb5dc RS |
4895 | /* Move the contents of register SOURCE into register DEST. */ |
4896 | ||
4897 | static void | |
67c0d1eb | 4898 | move_register (int dest, int source) |
ea1fb5dc | 4899 | { |
67c0d1eb RS |
4900 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4901 | dest, source, 0); | |
ea1fb5dc RS |
4902 | } |
4903 | ||
4d7206a2 | 4904 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4905 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4906 | The two alternatives are: | |
4d7206a2 RS |
4907 | |
4908 | Global symbol Local sybmol | |
4909 | ------------- ------------ | |
4910 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4911 | ... ... | |
4912 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4913 | ||
4914 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4915 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4916 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4917 | |
4918 | static void | |
67c0d1eb | 4919 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4920 | { |
4921 | expressionS global; | |
4922 | ||
4923 | global = *local; | |
4924 | global.X_add_number = 0; | |
4925 | ||
4926 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4927 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4928 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4929 | relax_switch (); |
67c0d1eb RS |
4930 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4931 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4932 | relax_end (); |
4933 | } | |
4934 | ||
4935 | static void | |
67c0d1eb | 4936 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4937 | { |
4938 | expressionS global; | |
4939 | ||
4940 | global.X_op = O_constant; | |
4941 | global.X_op_symbol = NULL; | |
4942 | global.X_add_symbol = NULL; | |
4943 | global.X_add_number = local->X_add_number; | |
4944 | ||
4945 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4946 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4947 | dest, dest, BFD_RELOC_LO16); |
4948 | relax_switch (); | |
67c0d1eb | 4949 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4950 | relax_end (); |
4951 | } | |
4952 | ||
f6a22291 MR |
4953 | static void |
4954 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4955 | { | |
4956 | expressionS global; | |
4957 | int hold_mips_optimize; | |
4958 | ||
4959 | global.X_op = O_constant; | |
4960 | global.X_op_symbol = NULL; | |
4961 | global.X_add_symbol = NULL; | |
4962 | global.X_add_number = local->X_add_number; | |
4963 | ||
4964 | relax_start (local->X_add_symbol); | |
4965 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4966 | relax_switch (); | |
4967 | /* Set mips_optimize around the lui instruction to avoid | |
4968 | inserting an unnecessary nop after the lw. */ | |
4969 | hold_mips_optimize = mips_optimize; | |
4970 | mips_optimize = 2; | |
4971 | macro_build_lui (&global, tmp); | |
4972 | mips_optimize = hold_mips_optimize; | |
4973 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4974 | relax_end (); | |
4975 | ||
4976 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4977 | } | |
4978 | ||
252b5132 RH |
4979 | /* |
4980 | * Build macros | |
4981 | * This routine implements the seemingly endless macro or synthesized | |
4982 | * instructions and addressing modes in the mips assembly language. Many | |
4983 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4984 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4985 | * this verbose method. Others are not simple macros but are more like |
4986 | * optimizing code generation. | |
4987 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4988 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4989 | * The ensuing load upper instructions are ommited. This implies some kind |
4990 | * of global optimization. We currently only optimize within a single macro. | |
4991 | * For many of the load and store macros if the address is specified as a | |
4992 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4993 | * first load register 'at' with zero and use it as the base register. The | |
4994 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4995 | * we're missing. | |
4996 | */ | |
4997 | static void | |
17a2f251 | 4998 | macro (struct mips_cl_insn *ip) |
252b5132 | 4999 | { |
741fe287 MR |
5000 | unsigned int treg, sreg, dreg, breg; |
5001 | unsigned int tempreg; | |
252b5132 | 5002 | int mask; |
43841e91 | 5003 | int used_at = 0; |
252b5132 RH |
5004 | expressionS expr1; |
5005 | const char *s; | |
5006 | const char *s2; | |
5007 | const char *fmt; | |
5008 | int likely = 0; | |
5009 | int dbl = 0; | |
5010 | int coproc = 0; | |
5011 | int lr = 0; | |
5012 | int imm = 0; | |
1abe91b1 | 5013 | int call = 0; |
252b5132 | 5014 | int off; |
67c0d1eb | 5015 | offsetT maxnum; |
252b5132 | 5016 | bfd_reloc_code_real_type r; |
252b5132 RH |
5017 | int hold_mips_optimize; |
5018 | ||
9c2799c2 | 5019 | gas_assert (! mips_opts.mips16); |
252b5132 | 5020 | |
bbea7ebc MR |
5021 | treg = EXTRACT_OPERAND (RT, *ip); |
5022 | dreg = EXTRACT_OPERAND (RD, *ip); | |
5023 | sreg = breg = EXTRACT_OPERAND (RS, *ip); | |
252b5132 RH |
5024 | mask = ip->insn_mo->mask; |
5025 | ||
5026 | expr1.X_op = O_constant; | |
5027 | expr1.X_op_symbol = NULL; | |
5028 | expr1.X_add_symbol = NULL; | |
5029 | expr1.X_add_number = 1; | |
5030 | ||
5031 | switch (mask) | |
5032 | { | |
5033 | case M_DABS: | |
5034 | dbl = 1; | |
5035 | case M_ABS: | |
5036 | /* bgez $a0,.+12 | |
5037 | move v0,$a0 | |
5038 | sub v0,$zero,$a0 | |
5039 | */ | |
5040 | ||
7d10b47d | 5041 | start_noreorder (); |
252b5132 RH |
5042 | |
5043 | expr1.X_add_number = 8; | |
67c0d1eb | 5044 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 5045 | if (dreg == sreg) |
a605d2b3 | 5046 | macro_build (NULL, "nop", ""); |
252b5132 | 5047 | else |
67c0d1eb RS |
5048 | move_register (dreg, sreg); |
5049 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 5050 | |
7d10b47d | 5051 | end_noreorder (); |
8fc2e39e | 5052 | break; |
252b5132 RH |
5053 | |
5054 | case M_ADD_I: | |
5055 | s = "addi"; | |
5056 | s2 = "add"; | |
5057 | goto do_addi; | |
5058 | case M_ADDU_I: | |
5059 | s = "addiu"; | |
5060 | s2 = "addu"; | |
5061 | goto do_addi; | |
5062 | case M_DADD_I: | |
5063 | dbl = 1; | |
5064 | s = "daddi"; | |
5065 | s2 = "dadd"; | |
5066 | goto do_addi; | |
5067 | case M_DADDU_I: | |
5068 | dbl = 1; | |
5069 | s = "daddiu"; | |
5070 | s2 = "daddu"; | |
5071 | do_addi: | |
5072 | if (imm_expr.X_op == O_constant | |
5073 | && imm_expr.X_add_number >= -0x8000 | |
5074 | && imm_expr.X_add_number < 0x8000) | |
5075 | { | |
67c0d1eb | 5076 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 5077 | break; |
252b5132 | 5078 | } |
8fc2e39e | 5079 | used_at = 1; |
67c0d1eb RS |
5080 | load_register (AT, &imm_expr, dbl); |
5081 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
5082 | break; |
5083 | ||
5084 | case M_AND_I: | |
5085 | s = "andi"; | |
5086 | s2 = "and"; | |
5087 | goto do_bit; | |
5088 | case M_OR_I: | |
5089 | s = "ori"; | |
5090 | s2 = "or"; | |
5091 | goto do_bit; | |
5092 | case M_NOR_I: | |
5093 | s = ""; | |
5094 | s2 = "nor"; | |
5095 | goto do_bit; | |
5096 | case M_XOR_I: | |
5097 | s = "xori"; | |
5098 | s2 = "xor"; | |
5099 | do_bit: | |
5100 | if (imm_expr.X_op == O_constant | |
5101 | && imm_expr.X_add_number >= 0 | |
5102 | && imm_expr.X_add_number < 0x10000) | |
5103 | { | |
5104 | if (mask != M_NOR_I) | |
67c0d1eb | 5105 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
5106 | else |
5107 | { | |
67c0d1eb RS |
5108 | macro_build (&imm_expr, "ori", "t,r,i", |
5109 | treg, sreg, BFD_RELOC_LO16); | |
5110 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 5111 | } |
8fc2e39e | 5112 | break; |
252b5132 RH |
5113 | } |
5114 | ||
8fc2e39e | 5115 | used_at = 1; |
67c0d1eb RS |
5116 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5117 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
5118 | break; |
5119 | ||
8b082fb1 TS |
5120 | case M_BALIGN: |
5121 | switch (imm_expr.X_add_number) | |
5122 | { | |
5123 | case 0: | |
5124 | macro_build (NULL, "nop", ""); | |
5125 | break; | |
5126 | case 2: | |
5127 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
5128 | break; | |
5129 | default: | |
5130 | macro_build (NULL, "balign", "t,s,2", treg, sreg, | |
90ecf173 | 5131 | (int) imm_expr.X_add_number); |
8b082fb1 TS |
5132 | break; |
5133 | } | |
5134 | break; | |
5135 | ||
252b5132 RH |
5136 | case M_BEQ_I: |
5137 | s = "beq"; | |
5138 | goto beq_i; | |
5139 | case M_BEQL_I: | |
5140 | s = "beql"; | |
5141 | likely = 1; | |
5142 | goto beq_i; | |
5143 | case M_BNE_I: | |
5144 | s = "bne"; | |
5145 | goto beq_i; | |
5146 | case M_BNEL_I: | |
5147 | s = "bnel"; | |
5148 | likely = 1; | |
5149 | beq_i: | |
5150 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5151 | { | |
c80c840e | 5152 | macro_build (&offset_expr, s, "s,t,p", sreg, ZERO); |
8fc2e39e | 5153 | break; |
252b5132 | 5154 | } |
8fc2e39e | 5155 | used_at = 1; |
67c0d1eb RS |
5156 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5157 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
5158 | break; |
5159 | ||
5160 | case M_BGEL: | |
5161 | likely = 1; | |
5162 | case M_BGE: | |
5163 | if (treg == 0) | |
5164 | { | |
67c0d1eb | 5165 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 5166 | break; |
252b5132 RH |
5167 | } |
5168 | if (sreg == 0) | |
5169 | { | |
67c0d1eb | 5170 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 5171 | break; |
252b5132 | 5172 | } |
8fc2e39e | 5173 | used_at = 1; |
67c0d1eb | 5174 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
c80c840e | 5175 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5176 | break; |
5177 | ||
5178 | case M_BGTL_I: | |
5179 | likely = 1; | |
5180 | case M_BGT_I: | |
90ecf173 | 5181 | /* Check for > max integer. */ |
252b5132 | 5182 | maxnum = 0x7fffffff; |
ca4e0257 | 5183 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
5184 | { |
5185 | maxnum <<= 16; | |
5186 | maxnum |= 0xffff; | |
5187 | maxnum <<= 16; | |
5188 | maxnum |= 0xffff; | |
5189 | } | |
5190 | if (imm_expr.X_op == O_constant | |
5191 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 5192 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5193 | { |
5194 | do_false: | |
90ecf173 | 5195 | /* Result is always false. */ |
252b5132 | 5196 | if (! likely) |
a605d2b3 | 5197 | macro_build (NULL, "nop", ""); |
252b5132 | 5198 | else |
c80c840e | 5199 | macro_build (&offset_expr, "bnel", "s,t,p", ZERO, ZERO); |
8fc2e39e | 5200 | break; |
252b5132 RH |
5201 | } |
5202 | if (imm_expr.X_op != O_constant) | |
5203 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5204 | ++imm_expr.X_add_number; |
252b5132 RH |
5205 | /* FALLTHROUGH */ |
5206 | case M_BGE_I: | |
5207 | case M_BGEL_I: | |
5208 | if (mask == M_BGEL_I) | |
5209 | likely = 1; | |
5210 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5211 | { | |
67c0d1eb | 5212 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 5213 | break; |
252b5132 RH |
5214 | } |
5215 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5216 | { | |
67c0d1eb | 5217 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 5218 | break; |
252b5132 RH |
5219 | } |
5220 | maxnum = 0x7fffffff; | |
ca4e0257 | 5221 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
5222 | { |
5223 | maxnum <<= 16; | |
5224 | maxnum |= 0xffff; | |
5225 | maxnum <<= 16; | |
5226 | maxnum |= 0xffff; | |
5227 | } | |
5228 | maxnum = - maxnum - 1; | |
5229 | if (imm_expr.X_op == O_constant | |
5230 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 5231 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5232 | { |
5233 | do_true: | |
5234 | /* result is always true */ | |
5235 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 5236 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5237 | break; |
252b5132 | 5238 | } |
8fc2e39e | 5239 | used_at = 1; |
67c0d1eb | 5240 | set_at (sreg, 0); |
c80c840e | 5241 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5242 | break; |
5243 | ||
5244 | case M_BGEUL: | |
5245 | likely = 1; | |
5246 | case M_BGEU: | |
5247 | if (treg == 0) | |
5248 | goto do_true; | |
5249 | if (sreg == 0) | |
5250 | { | |
67c0d1eb | 5251 | macro_build (&offset_expr, likely ? "beql" : "beq", |
c80c840e | 5252 | "s,t,p", ZERO, treg); |
8fc2e39e | 5253 | break; |
252b5132 | 5254 | } |
8fc2e39e | 5255 | used_at = 1; |
67c0d1eb | 5256 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
c80c840e | 5257 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5258 | break; |
5259 | ||
5260 | case M_BGTUL_I: | |
5261 | likely = 1; | |
5262 | case M_BGTU_I: | |
5263 | if (sreg == 0 | |
ca4e0257 | 5264 | || (HAVE_32BIT_GPRS |
252b5132 | 5265 | && imm_expr.X_op == O_constant |
f01dc953 | 5266 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
5267 | goto do_false; |
5268 | if (imm_expr.X_op != O_constant) | |
5269 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5270 | ++imm_expr.X_add_number; |
252b5132 RH |
5271 | /* FALLTHROUGH */ |
5272 | case M_BGEU_I: | |
5273 | case M_BGEUL_I: | |
5274 | if (mask == M_BGEUL_I) | |
5275 | likely = 1; | |
5276 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5277 | goto do_true; | |
5278 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5279 | { | |
67c0d1eb | 5280 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
c80c840e | 5281 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5282 | break; |
252b5132 | 5283 | } |
8fc2e39e | 5284 | used_at = 1; |
67c0d1eb | 5285 | set_at (sreg, 1); |
c80c840e | 5286 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5287 | break; |
5288 | ||
5289 | case M_BGTL: | |
5290 | likely = 1; | |
5291 | case M_BGT: | |
5292 | if (treg == 0) | |
5293 | { | |
67c0d1eb | 5294 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 5295 | break; |
252b5132 RH |
5296 | } |
5297 | if (sreg == 0) | |
5298 | { | |
67c0d1eb | 5299 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 5300 | break; |
252b5132 | 5301 | } |
8fc2e39e | 5302 | used_at = 1; |
67c0d1eb | 5303 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
c80c840e | 5304 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5305 | break; |
5306 | ||
5307 | case M_BGTUL: | |
5308 | likely = 1; | |
5309 | case M_BGTU: | |
5310 | if (treg == 0) | |
5311 | { | |
67c0d1eb | 5312 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
c80c840e | 5313 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5314 | break; |
252b5132 RH |
5315 | } |
5316 | if (sreg == 0) | |
5317 | goto do_false; | |
8fc2e39e | 5318 | used_at = 1; |
67c0d1eb | 5319 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
c80c840e | 5320 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5321 | break; |
5322 | ||
5323 | case M_BLEL: | |
5324 | likely = 1; | |
5325 | case M_BLE: | |
5326 | if (treg == 0) | |
5327 | { | |
67c0d1eb | 5328 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 5329 | break; |
252b5132 RH |
5330 | } |
5331 | if (sreg == 0) | |
5332 | { | |
67c0d1eb | 5333 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 5334 | break; |
252b5132 | 5335 | } |
8fc2e39e | 5336 | used_at = 1; |
67c0d1eb | 5337 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
c80c840e | 5338 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5339 | break; |
5340 | ||
5341 | case M_BLEL_I: | |
5342 | likely = 1; | |
5343 | case M_BLE_I: | |
5344 | maxnum = 0x7fffffff; | |
ca4e0257 | 5345 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
5346 | { |
5347 | maxnum <<= 16; | |
5348 | maxnum |= 0xffff; | |
5349 | maxnum <<= 16; | |
5350 | maxnum |= 0xffff; | |
5351 | } | |
5352 | if (imm_expr.X_op == O_constant | |
5353 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 5354 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5355 | goto do_true; |
5356 | if (imm_expr.X_op != O_constant) | |
5357 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5358 | ++imm_expr.X_add_number; |
252b5132 RH |
5359 | /* FALLTHROUGH */ |
5360 | case M_BLT_I: | |
5361 | case M_BLTL_I: | |
5362 | if (mask == M_BLTL_I) | |
5363 | likely = 1; | |
5364 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5365 | { | |
67c0d1eb | 5366 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 5367 | break; |
252b5132 RH |
5368 | } |
5369 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5370 | { | |
67c0d1eb | 5371 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 5372 | break; |
252b5132 | 5373 | } |
8fc2e39e | 5374 | used_at = 1; |
67c0d1eb | 5375 | set_at (sreg, 0); |
c80c840e | 5376 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5377 | break; |
5378 | ||
5379 | case M_BLEUL: | |
5380 | likely = 1; | |
5381 | case M_BLEU: | |
5382 | if (treg == 0) | |
5383 | { | |
67c0d1eb | 5384 | macro_build (&offset_expr, likely ? "beql" : "beq", |
c80c840e | 5385 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5386 | break; |
252b5132 RH |
5387 | } |
5388 | if (sreg == 0) | |
5389 | goto do_true; | |
8fc2e39e | 5390 | used_at = 1; |
67c0d1eb | 5391 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
c80c840e | 5392 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5393 | break; |
5394 | ||
5395 | case M_BLEUL_I: | |
5396 | likely = 1; | |
5397 | case M_BLEU_I: | |
5398 | if (sreg == 0 | |
ca4e0257 | 5399 | || (HAVE_32BIT_GPRS |
252b5132 | 5400 | && imm_expr.X_op == O_constant |
f01dc953 | 5401 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
5402 | goto do_true; |
5403 | if (imm_expr.X_op != O_constant) | |
5404 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5405 | ++imm_expr.X_add_number; |
252b5132 RH |
5406 | /* FALLTHROUGH */ |
5407 | case M_BLTU_I: | |
5408 | case M_BLTUL_I: | |
5409 | if (mask == M_BLTUL_I) | |
5410 | likely = 1; | |
5411 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5412 | goto do_false; | |
5413 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5414 | { | |
67c0d1eb | 5415 | macro_build (&offset_expr, likely ? "beql" : "beq", |
c80c840e | 5416 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5417 | break; |
252b5132 | 5418 | } |
8fc2e39e | 5419 | used_at = 1; |
67c0d1eb | 5420 | set_at (sreg, 1); |
c80c840e | 5421 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5422 | break; |
5423 | ||
5424 | case M_BLTL: | |
5425 | likely = 1; | |
5426 | case M_BLT: | |
5427 | if (treg == 0) | |
5428 | { | |
67c0d1eb | 5429 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 5430 | break; |
252b5132 RH |
5431 | } |
5432 | if (sreg == 0) | |
5433 | { | |
67c0d1eb | 5434 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 5435 | break; |
252b5132 | 5436 | } |
8fc2e39e | 5437 | used_at = 1; |
67c0d1eb | 5438 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
c80c840e | 5439 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5440 | break; |
5441 | ||
5442 | case M_BLTUL: | |
5443 | likely = 1; | |
5444 | case M_BLTU: | |
5445 | if (treg == 0) | |
5446 | goto do_false; | |
5447 | if (sreg == 0) | |
5448 | { | |
67c0d1eb | 5449 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
c80c840e | 5450 | "s,t,p", ZERO, treg); |
8fc2e39e | 5451 | break; |
252b5132 | 5452 | } |
8fc2e39e | 5453 | used_at = 1; |
67c0d1eb | 5454 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
c80c840e | 5455 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5456 | break; |
5457 | ||
5f74bc13 CD |
5458 | case M_DEXT: |
5459 | { | |
d5818fca MR |
5460 | /* Use unsigned arithmetic. */ |
5461 | addressT pos; | |
5462 | addressT size; | |
5f74bc13 | 5463 | |
90ecf173 | 5464 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
5465 | { |
5466 | as_bad (_("Unsupported large constant")); | |
5467 | pos = size = 1; | |
5468 | } | |
5469 | else | |
5470 | { | |
d5818fca MR |
5471 | pos = imm_expr.X_add_number; |
5472 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
5473 | } |
5474 | ||
5475 | if (pos > 63) | |
5476 | { | |
d5818fca | 5477 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
5478 | pos = 1; |
5479 | } | |
90ecf173 | 5480 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
5481 | { |
5482 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 5483 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
5484 | size = 1; |
5485 | } | |
5486 | ||
5487 | if (size <= 32 && pos < 32) | |
5488 | { | |
5489 | s = "dext"; | |
5490 | fmt = "t,r,+A,+C"; | |
5491 | } | |
5492 | else if (size <= 32) | |
5493 | { | |
5494 | s = "dextu"; | |
5495 | fmt = "t,r,+E,+H"; | |
5496 | } | |
5497 | else | |
5498 | { | |
5499 | s = "dextm"; | |
5500 | fmt = "t,r,+A,+G"; | |
5501 | } | |
d5818fca MR |
5502 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
5503 | (int) (size - 1)); | |
5f74bc13 | 5504 | } |
8fc2e39e | 5505 | break; |
5f74bc13 CD |
5506 | |
5507 | case M_DINS: | |
5508 | { | |
d5818fca MR |
5509 | /* Use unsigned arithmetic. */ |
5510 | addressT pos; | |
5511 | addressT size; | |
5f74bc13 | 5512 | |
90ecf173 | 5513 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
5514 | { |
5515 | as_bad (_("Unsupported large constant")); | |
5516 | pos = size = 1; | |
5517 | } | |
5518 | else | |
5519 | { | |
d5818fca MR |
5520 | pos = imm_expr.X_add_number; |
5521 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
5522 | } |
5523 | ||
5524 | if (pos > 63) | |
5525 | { | |
d5818fca | 5526 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
5527 | pos = 1; |
5528 | } | |
90ecf173 | 5529 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
5530 | { |
5531 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 5532 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
5533 | size = 1; |
5534 | } | |
5535 | ||
5536 | if (pos < 32 && (pos + size - 1) < 32) | |
5537 | { | |
5538 | s = "dins"; | |
5539 | fmt = "t,r,+A,+B"; | |
5540 | } | |
5541 | else if (pos >= 32) | |
5542 | { | |
5543 | s = "dinsu"; | |
5544 | fmt = "t,r,+E,+F"; | |
5545 | } | |
5546 | else | |
5547 | { | |
5548 | s = "dinsm"; | |
5549 | fmt = "t,r,+A,+F"; | |
5550 | } | |
750bdd57 AS |
5551 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
5552 | (int) (pos + size - 1)); | |
5f74bc13 | 5553 | } |
8fc2e39e | 5554 | break; |
5f74bc13 | 5555 | |
252b5132 RH |
5556 | case M_DDIV_3: |
5557 | dbl = 1; | |
5558 | case M_DIV_3: | |
5559 | s = "mflo"; | |
5560 | goto do_div3; | |
5561 | case M_DREM_3: | |
5562 | dbl = 1; | |
5563 | case M_REM_3: | |
5564 | s = "mfhi"; | |
5565 | do_div3: | |
5566 | if (treg == 0) | |
5567 | { | |
5568 | as_warn (_("Divide by zero.")); | |
5569 | if (mips_trap) | |
c80c840e | 5570 | macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7); |
252b5132 | 5571 | else |
67c0d1eb | 5572 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5573 | break; |
252b5132 RH |
5574 | } |
5575 | ||
7d10b47d | 5576 | start_noreorder (); |
252b5132 RH |
5577 | if (mips_trap) |
5578 | { | |
c80c840e | 5579 | macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7); |
67c0d1eb | 5580 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
5581 | } |
5582 | else | |
5583 | { | |
5584 | expr1.X_add_number = 8; | |
c80c840e | 5585 | macro_build (&expr1, "bne", "s,t,p", treg, ZERO); |
67c0d1eb RS |
5586 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
5587 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
5588 | } |
5589 | expr1.X_add_number = -1; | |
8fc2e39e | 5590 | used_at = 1; |
f6a22291 | 5591 | load_register (AT, &expr1, dbl); |
252b5132 | 5592 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 5593 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
5594 | if (dbl) |
5595 | { | |
5596 | expr1.X_add_number = 1; | |
f6a22291 | 5597 | load_register (AT, &expr1, dbl); |
67c0d1eb | 5598 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
5599 | } |
5600 | else | |
5601 | { | |
5602 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 5603 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
5604 | } |
5605 | if (mips_trap) | |
5606 | { | |
67c0d1eb | 5607 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
5608 | /* We want to close the noreorder block as soon as possible, so |
5609 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5610 | end_noreorder (); |
252b5132 RH |
5611 | } |
5612 | else | |
5613 | { | |
5614 | expr1.X_add_number = 8; | |
67c0d1eb | 5615 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
a605d2b3 | 5616 | macro_build (NULL, "nop", ""); |
252b5132 RH |
5617 | |
5618 | /* We want to close the noreorder block as soon as possible, so | |
5619 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5620 | end_noreorder (); |
252b5132 | 5621 | |
67c0d1eb | 5622 | macro_build (NULL, "break", "c", 6); |
252b5132 | 5623 | } |
67c0d1eb | 5624 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
5625 | break; |
5626 | ||
5627 | case M_DIV_3I: | |
5628 | s = "div"; | |
5629 | s2 = "mflo"; | |
5630 | goto do_divi; | |
5631 | case M_DIVU_3I: | |
5632 | s = "divu"; | |
5633 | s2 = "mflo"; | |
5634 | goto do_divi; | |
5635 | case M_REM_3I: | |
5636 | s = "div"; | |
5637 | s2 = "mfhi"; | |
5638 | goto do_divi; | |
5639 | case M_REMU_3I: | |
5640 | s = "divu"; | |
5641 | s2 = "mfhi"; | |
5642 | goto do_divi; | |
5643 | case M_DDIV_3I: | |
5644 | dbl = 1; | |
5645 | s = "ddiv"; | |
5646 | s2 = "mflo"; | |
5647 | goto do_divi; | |
5648 | case M_DDIVU_3I: | |
5649 | dbl = 1; | |
5650 | s = "ddivu"; | |
5651 | s2 = "mflo"; | |
5652 | goto do_divi; | |
5653 | case M_DREM_3I: | |
5654 | dbl = 1; | |
5655 | s = "ddiv"; | |
5656 | s2 = "mfhi"; | |
5657 | goto do_divi; | |
5658 | case M_DREMU_3I: | |
5659 | dbl = 1; | |
5660 | s = "ddivu"; | |
5661 | s2 = "mfhi"; | |
5662 | do_divi: | |
5663 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5664 | { | |
5665 | as_warn (_("Divide by zero.")); | |
5666 | if (mips_trap) | |
c80c840e | 5667 | macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7); |
252b5132 | 5668 | else |
67c0d1eb | 5669 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5670 | break; |
252b5132 RH |
5671 | } |
5672 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5673 | { | |
5674 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 5675 | move_register (dreg, sreg); |
252b5132 | 5676 | else |
c80c840e | 5677 | move_register (dreg, ZERO); |
8fc2e39e | 5678 | break; |
252b5132 RH |
5679 | } |
5680 | if (imm_expr.X_op == O_constant | |
5681 | && imm_expr.X_add_number == -1 | |
5682 | && s[strlen (s) - 1] != 'u') | |
5683 | { | |
5684 | if (strcmp (s2, "mflo") == 0) | |
5685 | { | |
67c0d1eb | 5686 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
5687 | } |
5688 | else | |
c80c840e | 5689 | move_register (dreg, ZERO); |
8fc2e39e | 5690 | break; |
252b5132 RH |
5691 | } |
5692 | ||
8fc2e39e | 5693 | used_at = 1; |
67c0d1eb RS |
5694 | load_register (AT, &imm_expr, dbl); |
5695 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
5696 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
5697 | break; |
5698 | ||
5699 | case M_DIVU_3: | |
5700 | s = "divu"; | |
5701 | s2 = "mflo"; | |
5702 | goto do_divu3; | |
5703 | case M_REMU_3: | |
5704 | s = "divu"; | |
5705 | s2 = "mfhi"; | |
5706 | goto do_divu3; | |
5707 | case M_DDIVU_3: | |
5708 | s = "ddivu"; | |
5709 | s2 = "mflo"; | |
5710 | goto do_divu3; | |
5711 | case M_DREMU_3: | |
5712 | s = "ddivu"; | |
5713 | s2 = "mfhi"; | |
5714 | do_divu3: | |
7d10b47d | 5715 | start_noreorder (); |
252b5132 RH |
5716 | if (mips_trap) |
5717 | { | |
c80c840e | 5718 | macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7); |
67c0d1eb | 5719 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
5720 | /* We want to close the noreorder block as soon as possible, so |
5721 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5722 | end_noreorder (); |
252b5132 RH |
5723 | } |
5724 | else | |
5725 | { | |
5726 | expr1.X_add_number = 8; | |
c80c840e | 5727 | macro_build (&expr1, "bne", "s,t,p", treg, ZERO); |
67c0d1eb | 5728 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
5729 | |
5730 | /* We want to close the noreorder block as soon as possible, so | |
5731 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5732 | end_noreorder (); |
67c0d1eb | 5733 | macro_build (NULL, "break", "c", 7); |
252b5132 | 5734 | } |
67c0d1eb | 5735 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 5736 | break; |
252b5132 | 5737 | |
1abe91b1 MR |
5738 | case M_DLCA_AB: |
5739 | dbl = 1; | |
5740 | case M_LCA_AB: | |
5741 | call = 1; | |
5742 | goto do_la; | |
252b5132 RH |
5743 | case M_DLA_AB: |
5744 | dbl = 1; | |
5745 | case M_LA_AB: | |
1abe91b1 | 5746 | do_la: |
252b5132 RH |
5747 | /* Load the address of a symbol into a register. If breg is not |
5748 | zero, we then add a base register to it. */ | |
5749 | ||
3bec30a8 TS |
5750 | if (dbl && HAVE_32BIT_GPRS) |
5751 | as_warn (_("dla used to load 32-bit register")); | |
5752 | ||
90ecf173 | 5753 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
5754 | as_warn (_("la used to load 64-bit address")); |
5755 | ||
0c11417f MR |
5756 | if (offset_expr.X_op == O_constant |
5757 | && offset_expr.X_add_number >= -0x8000 | |
5758 | && offset_expr.X_add_number < 0x8000) | |
5759 | { | |
aed1a261 | 5760 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 5761 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 5762 | break; |
0c11417f MR |
5763 | } |
5764 | ||
741fe287 | 5765 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
5766 | { |
5767 | tempreg = AT; | |
5768 | used_at = 1; | |
5769 | } | |
5770 | else | |
5771 | { | |
5772 | tempreg = treg; | |
afdbd6d0 CD |
5773 | } |
5774 | ||
252b5132 RH |
5775 | if (offset_expr.X_op != O_symbol |
5776 | && offset_expr.X_op != O_constant) | |
5777 | { | |
f71d0d44 | 5778 | as_bad (_("Expression too complex")); |
252b5132 RH |
5779 | offset_expr.X_op = O_constant; |
5780 | } | |
5781 | ||
252b5132 | 5782 | if (offset_expr.X_op == O_constant) |
aed1a261 | 5783 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5784 | else if (mips_pic == NO_PIC) |
5785 | { | |
d6bc6245 | 5786 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 5787 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5788 | Otherwise we want |
5789 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5790 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5791 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 5792 | so we may as well always use the latter form. |
76b3015f | 5793 | |
6caf9ef4 TS |
5794 | With 64bit address space and a usable $at we want |
5795 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5796 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5797 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5798 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5799 | dsll32 $tempreg,0 | |
5800 | daddu $tempreg,$tempreg,$at | |
5801 | ||
5802 | If $at is already in use, we use a path which is suboptimal | |
5803 | on superscalar processors. | |
5804 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5805 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5806 | dsll $tempreg,16 | |
5807 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5808 | dsll $tempreg,16 | |
5809 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
5810 | ||
5811 | For GP relative symbols in 64bit address space we can use | |
5812 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5813 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 5814 | { |
6caf9ef4 TS |
5815 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
5816 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5817 | { | |
5818 | relax_start (offset_expr.X_add_symbol); | |
5819 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5820 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
5821 | relax_switch (); | |
5822 | } | |
d6bc6245 | 5823 | |
741fe287 | 5824 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 5825 | { |
67c0d1eb | 5826 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5827 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5828 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5829 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 5830 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5831 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 5832 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5833 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
5834 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
5835 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
5836 | used_at = 1; |
5837 | } | |
5838 | else | |
5839 | { | |
67c0d1eb | 5840 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5841 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5842 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5843 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
5844 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5845 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5846 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
5847 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5848 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5849 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 5850 | } |
6caf9ef4 TS |
5851 | |
5852 | if (mips_relax.sequence) | |
5853 | relax_end (); | |
98d3f06f KH |
5854 | } |
5855 | else | |
5856 | { | |
5857 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 5858 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 5859 | { |
4d7206a2 | 5860 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5861 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5862 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5863 | relax_switch (); |
98d3f06f | 5864 | } |
6943caf0 | 5865 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 5866 | as_bad (_("Offset too large")); |
67c0d1eb RS |
5867 | macro_build_lui (&offset_expr, tempreg); |
5868 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5869 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5870 | if (mips_relax.sequence) |
5871 | relax_end (); | |
98d3f06f | 5872 | } |
252b5132 | 5873 | } |
0a44bf69 | 5874 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 5875 | { |
9117d219 NC |
5876 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5877 | ||
252b5132 RH |
5878 | /* If this is a reference to an external symbol, and there |
5879 | is no constant, we want | |
5880 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5881 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5882 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5883 | For a local symbol, we want |
5884 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5885 | nop | |
5886 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5887 | ||
5888 | If we have a small constant, and this is a reference to | |
5889 | an external symbol, we want | |
5890 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5891 | nop | |
5892 | addiu $tempreg,$tempreg,<constant> | |
5893 | For a local symbol, we want the same instruction | |
5894 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5895 | addiu instruction. | |
5896 | ||
5897 | If we have a large constant, and this is a reference to | |
5898 | an external symbol, we want | |
5899 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5900 | lui $at,<hiconstant> | |
5901 | addiu $at,$at,<loconstant> | |
5902 | addu $tempreg,$tempreg,$at | |
5903 | For a local symbol, we want the same instruction | |
5904 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5905 | addiu instruction. |
ed6fb7bd SC |
5906 | */ |
5907 | ||
4d7206a2 | 5908 | if (offset_expr.X_add_number == 0) |
252b5132 | 5909 | { |
0a44bf69 RS |
5910 | if (mips_pic == SVR4_PIC |
5911 | && breg == 0 | |
5912 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
5913 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
5914 | ||
5915 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5916 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5917 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5918 | if (breg != 0) |
252b5132 RH |
5919 | { |
5920 | /* We're going to put in an addu instruction using | |
5921 | tempreg, so we may as well insert the nop right | |
5922 | now. */ | |
269137b2 | 5923 | load_delay_nop (); |
252b5132 | 5924 | } |
4d7206a2 | 5925 | relax_switch (); |
67c0d1eb RS |
5926 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5927 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5928 | load_delay_nop (); |
67c0d1eb RS |
5929 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5930 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5931 | relax_end (); |
252b5132 RH |
5932 | /* FIXME: If breg == 0, and the next instruction uses |
5933 | $tempreg, then if this variant case is used an extra | |
5934 | nop will be generated. */ | |
5935 | } | |
4d7206a2 RS |
5936 | else if (offset_expr.X_add_number >= -0x8000 |
5937 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5938 | { |
67c0d1eb | 5939 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5940 | load_delay_nop (); |
67c0d1eb | 5941 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5942 | } |
5943 | else | |
5944 | { | |
4d7206a2 RS |
5945 | expr1.X_add_number = offset_expr.X_add_number; |
5946 | offset_expr.X_add_number = | |
5947 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5948 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5949 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5950 | /* If we are going to add in a base register, and the |
5951 | target register and the base register are the same, | |
5952 | then we are using AT as a temporary register. Since | |
5953 | we want to load the constant into AT, we add our | |
5954 | current AT (from the global offset table) and the | |
5955 | register into the register now, and pretend we were | |
5956 | not using a base register. */ | |
67c0d1eb | 5957 | if (breg == treg) |
252b5132 | 5958 | { |
269137b2 | 5959 | load_delay_nop (); |
67c0d1eb | 5960 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5961 | treg, AT, breg); |
252b5132 RH |
5962 | breg = 0; |
5963 | tempreg = treg; | |
252b5132 | 5964 | } |
f6a22291 | 5965 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5966 | used_at = 1; |
5967 | } | |
5968 | } | |
0a44bf69 | 5969 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 5970 | { |
67c0d1eb | 5971 | int add_breg_early = 0; |
f5040a92 AO |
5972 | |
5973 | /* If this is a reference to an external, and there is no | |
5974 | constant, or local symbol (*), with or without a | |
5975 | constant, we want | |
5976 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5977 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5978 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5979 | ||
5980 | If we have a small constant, and this is a reference to | |
5981 | an external symbol, we want | |
5982 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5983 | addiu $tempreg,$tempreg,<constant> | |
5984 | ||
5985 | If we have a large constant, and this is a reference to | |
5986 | an external symbol, we want | |
5987 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5988 | lui $at,<hiconstant> | |
5989 | addiu $at,$at,<loconstant> | |
5990 | addu $tempreg,$tempreg,$at | |
5991 | ||
5992 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5993 | local symbols, even though it introduces an additional | |
5994 | instruction. */ | |
5995 | ||
f5040a92 AO |
5996 | if (offset_expr.X_add_number) |
5997 | { | |
4d7206a2 | 5998 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5999 | offset_expr.X_add_number = 0; |
6000 | ||
4d7206a2 | 6001 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6002 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6003 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
6004 | |
6005 | if (expr1.X_add_number >= -0x8000 | |
6006 | && expr1.X_add_number < 0x8000) | |
6007 | { | |
67c0d1eb RS |
6008 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
6009 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 6010 | } |
ecd13cd3 | 6011 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 6012 | { |
f5040a92 AO |
6013 | /* If we are going to add in a base register, and the |
6014 | target register and the base register are the same, | |
6015 | then we are using AT as a temporary register. Since | |
6016 | we want to load the constant into AT, we add our | |
6017 | current AT (from the global offset table) and the | |
6018 | register into the register now, and pretend we were | |
6019 | not using a base register. */ | |
6020 | if (breg != treg) | |
6021 | dreg = tempreg; | |
6022 | else | |
6023 | { | |
9c2799c2 | 6024 | gas_assert (tempreg == AT); |
67c0d1eb RS |
6025 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6026 | treg, AT, breg); | |
f5040a92 | 6027 | dreg = treg; |
67c0d1eb | 6028 | add_breg_early = 1; |
f5040a92 AO |
6029 | } |
6030 | ||
f6a22291 | 6031 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 6032 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6033 | dreg, dreg, AT); |
f5040a92 | 6034 | |
f5040a92 AO |
6035 | used_at = 1; |
6036 | } | |
6037 | else | |
6038 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
6039 | ||
4d7206a2 | 6040 | relax_switch (); |
f5040a92 AO |
6041 | offset_expr.X_add_number = expr1.X_add_number; |
6042 | ||
67c0d1eb RS |
6043 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6044 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
6045 | if (add_breg_early) | |
f5040a92 | 6046 | { |
67c0d1eb | 6047 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 6048 | treg, tempreg, breg); |
f5040a92 AO |
6049 | breg = 0; |
6050 | tempreg = treg; | |
6051 | } | |
4d7206a2 | 6052 | relax_end (); |
f5040a92 | 6053 | } |
4d7206a2 | 6054 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 6055 | { |
4d7206a2 | 6056 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6057 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6058 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 6059 | relax_switch (); |
67c0d1eb RS |
6060 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6061 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 6062 | relax_end (); |
f5040a92 | 6063 | } |
4d7206a2 | 6064 | else |
f5040a92 | 6065 | { |
67c0d1eb RS |
6066 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6067 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
6068 | } |
6069 | } | |
0a44bf69 | 6070 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 6071 | { |
67c0d1eb | 6072 | int gpdelay; |
9117d219 NC |
6073 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
6074 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 6075 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
6076 | |
6077 | /* This is the large GOT case. If this is a reference to an | |
6078 | external symbol, and there is no constant, we want | |
6079 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6080 | addu $tempreg,$tempreg,$gp | |
6081 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 6082 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
6083 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
6084 | addu $tempreg,$tempreg,$gp | |
6085 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
6086 | For a local symbol, we want |
6087 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6088 | nop | |
6089 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6090 | ||
6091 | If we have a small constant, and this is a reference to | |
6092 | an external symbol, we want | |
6093 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6094 | addu $tempreg,$tempreg,$gp | |
6095 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6096 | nop | |
6097 | addiu $tempreg,$tempreg,<constant> | |
6098 | For a local symbol, we want | |
6099 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6100 | nop | |
6101 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
6102 | ||
6103 | If we have a large constant, and this is a reference to | |
6104 | an external symbol, we want | |
6105 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6106 | addu $tempreg,$tempreg,$gp | |
6107 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6108 | lui $at,<hiconstant> | |
6109 | addiu $at,$at,<loconstant> | |
6110 | addu $tempreg,$tempreg,$at | |
6111 | For a local symbol, we want | |
6112 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6113 | lui $at,<hiconstant> | |
6114 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
6115 | addu $tempreg,$tempreg,$at | |
f5040a92 | 6116 | */ |
438c16b8 | 6117 | |
252b5132 RH |
6118 | expr1.X_add_number = offset_expr.X_add_number; |
6119 | offset_expr.X_add_number = 0; | |
4d7206a2 | 6120 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6121 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
6122 | if (expr1.X_add_number == 0 && breg == 0 |
6123 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
6124 | { |
6125 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
6126 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
6127 | } | |
67c0d1eb RS |
6128 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
6129 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6130 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 6131 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6132 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
6133 | if (expr1.X_add_number == 0) |
6134 | { | |
67c0d1eb | 6135 | if (breg != 0) |
252b5132 RH |
6136 | { |
6137 | /* We're going to put in an addu instruction using | |
6138 | tempreg, so we may as well insert the nop right | |
6139 | now. */ | |
269137b2 | 6140 | load_delay_nop (); |
252b5132 | 6141 | } |
252b5132 RH |
6142 | } |
6143 | else if (expr1.X_add_number >= -0x8000 | |
6144 | && expr1.X_add_number < 0x8000) | |
6145 | { | |
269137b2 | 6146 | load_delay_nop (); |
67c0d1eb | 6147 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6148 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
6149 | } |
6150 | else | |
6151 | { | |
252b5132 RH |
6152 | /* If we are going to add in a base register, and the |
6153 | target register and the base register are the same, | |
6154 | then we are using AT as a temporary register. Since | |
6155 | we want to load the constant into AT, we add our | |
6156 | current AT (from the global offset table) and the | |
6157 | register into the register now, and pretend we were | |
6158 | not using a base register. */ | |
6159 | if (breg != treg) | |
67c0d1eb | 6160 | dreg = tempreg; |
252b5132 RH |
6161 | else |
6162 | { | |
9c2799c2 | 6163 | gas_assert (tempreg == AT); |
269137b2 | 6164 | load_delay_nop (); |
67c0d1eb | 6165 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6166 | treg, AT, breg); |
252b5132 | 6167 | dreg = treg; |
252b5132 RH |
6168 | } |
6169 | ||
f6a22291 | 6170 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 6171 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 6172 | |
252b5132 RH |
6173 | used_at = 1; |
6174 | } | |
4d7206a2 RS |
6175 | offset_expr.X_add_number = |
6176 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
6177 | relax_switch (); | |
252b5132 | 6178 | |
67c0d1eb | 6179 | if (gpdelay) |
252b5132 RH |
6180 | { |
6181 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 6182 | the first instruction on the main stream does not. */ |
67c0d1eb | 6183 | macro_build (NULL, "nop", ""); |
252b5132 | 6184 | } |
ed6fb7bd | 6185 | |
67c0d1eb RS |
6186 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6187 | local_reloc_type, mips_gp_register); | |
f5040a92 | 6188 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
6189 | && expr1.X_add_number < 0x8000) |
6190 | { | |
269137b2 | 6191 | load_delay_nop (); |
67c0d1eb RS |
6192 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6193 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 6194 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
6195 | register, the external symbol case ended with a load, |
6196 | so if the symbol turns out to not be external, and | |
6197 | the next instruction uses tempreg, an unnecessary nop | |
6198 | will be inserted. */ | |
252b5132 RH |
6199 | } |
6200 | else | |
6201 | { | |
6202 | if (breg == treg) | |
6203 | { | |
6204 | /* We must add in the base register now, as in the | |
f5040a92 | 6205 | external symbol case. */ |
9c2799c2 | 6206 | gas_assert (tempreg == AT); |
269137b2 | 6207 | load_delay_nop (); |
67c0d1eb | 6208 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6209 | treg, AT, breg); |
252b5132 RH |
6210 | tempreg = treg; |
6211 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 6212 | it in in both cases. */ |
252b5132 RH |
6213 | breg = 0; |
6214 | } | |
6215 | ||
67c0d1eb RS |
6216 | macro_build_lui (&expr1, AT); |
6217 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 6218 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 6219 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6220 | tempreg, tempreg, AT); |
8fc2e39e | 6221 | used_at = 1; |
252b5132 | 6222 | } |
4d7206a2 | 6223 | relax_end (); |
252b5132 | 6224 | } |
0a44bf69 | 6225 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6226 | { |
f5040a92 AO |
6227 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
6228 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 6229 | int add_breg_early = 0; |
f5040a92 AO |
6230 | |
6231 | /* This is the large GOT case. If this is a reference to an | |
6232 | external symbol, and there is no constant, we want | |
6233 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6234 | add $tempreg,$tempreg,$gp | |
6235 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 6236 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
6237 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
6238 | add $tempreg,$tempreg,$gp | |
6239 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
6240 | ||
6241 | If we have a small constant, and this is a reference to | |
6242 | an external symbol, we want | |
6243 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6244 | add $tempreg,$tempreg,$gp | |
6245 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6246 | addi $tempreg,$tempreg,<constant> | |
6247 | ||
6248 | If we have a large constant, and this is a reference to | |
6249 | an external symbol, we want | |
6250 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6251 | addu $tempreg,$tempreg,$gp | |
6252 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6253 | lui $at,<hiconstant> | |
6254 | addi $at,$at,<loconstant> | |
6255 | add $tempreg,$tempreg,$at | |
6256 | ||
6257 | If we have NewABI, and we know it's a local symbol, we want | |
6258 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6259 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
6260 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
6261 | ||
4d7206a2 | 6262 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 6263 | |
4d7206a2 | 6264 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6265 | offset_expr.X_add_number = 0; |
6266 | ||
1abe91b1 MR |
6267 | if (expr1.X_add_number == 0 && breg == 0 |
6268 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
6269 | { |
6270 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
6271 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
6272 | } | |
67c0d1eb RS |
6273 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
6274 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6275 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
6276 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6277 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
6278 | |
6279 | if (expr1.X_add_number == 0) | |
4d7206a2 | 6280 | ; |
f5040a92 AO |
6281 | else if (expr1.X_add_number >= -0x8000 |
6282 | && expr1.X_add_number < 0x8000) | |
6283 | { | |
67c0d1eb | 6284 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6285 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 6286 | } |
ecd13cd3 | 6287 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 6288 | { |
f5040a92 AO |
6289 | /* If we are going to add in a base register, and the |
6290 | target register and the base register are the same, | |
6291 | then we are using AT as a temporary register. Since | |
6292 | we want to load the constant into AT, we add our | |
6293 | current AT (from the global offset table) and the | |
6294 | register into the register now, and pretend we were | |
6295 | not using a base register. */ | |
6296 | if (breg != treg) | |
6297 | dreg = tempreg; | |
6298 | else | |
6299 | { | |
9c2799c2 | 6300 | gas_assert (tempreg == AT); |
67c0d1eb | 6301 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6302 | treg, AT, breg); |
f5040a92 | 6303 | dreg = treg; |
67c0d1eb | 6304 | add_breg_early = 1; |
f5040a92 AO |
6305 | } |
6306 | ||
f6a22291 | 6307 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 6308 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 6309 | |
f5040a92 AO |
6310 | used_at = 1; |
6311 | } | |
6312 | else | |
6313 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
6314 | ||
4d7206a2 | 6315 | relax_switch (); |
f5040a92 | 6316 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6317 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6318 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
6319 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
6320 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
6321 | if (add_breg_early) | |
f5040a92 | 6322 | { |
67c0d1eb | 6323 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6324 | treg, tempreg, breg); |
f5040a92 AO |
6325 | breg = 0; |
6326 | tempreg = treg; | |
6327 | } | |
4d7206a2 | 6328 | relax_end (); |
f5040a92 | 6329 | } |
252b5132 RH |
6330 | else |
6331 | abort (); | |
6332 | ||
6333 | if (breg != 0) | |
aed1a261 | 6334 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
6335 | break; |
6336 | ||
52b6b6b9 JM |
6337 | case M_MSGSND: |
6338 | { | |
6339 | unsigned long temp = (treg << 16) | (0x01); | |
6340 | macro_build (NULL, "c2", "C", temp); | |
6341 | } | |
c7af4273 | 6342 | break; |
52b6b6b9 JM |
6343 | |
6344 | case M_MSGLD: | |
6345 | { | |
6346 | unsigned long temp = (0x02); | |
6347 | macro_build (NULL, "c2", "C", temp); | |
6348 | } | |
c7af4273 | 6349 | break; |
52b6b6b9 JM |
6350 | |
6351 | case M_MSGLD_T: | |
6352 | { | |
6353 | unsigned long temp = (treg << 16) | (0x02); | |
6354 | macro_build (NULL, "c2", "C", temp); | |
6355 | } | |
c7af4273 | 6356 | break; |
52b6b6b9 JM |
6357 | |
6358 | case M_MSGWAIT: | |
6359 | macro_build (NULL, "c2", "C", 3); | |
c7af4273 | 6360 | break; |
52b6b6b9 JM |
6361 | |
6362 | case M_MSGWAIT_T: | |
6363 | { | |
6364 | unsigned long temp = (treg << 16) | 0x03; | |
6365 | macro_build (NULL, "c2", "C", temp); | |
6366 | } | |
c7af4273 | 6367 | break; |
52b6b6b9 | 6368 | |
252b5132 RH |
6369 | case M_J_A: |
6370 | /* The j instruction may not be used in PIC code, since it | |
6371 | requires an absolute address. We convert it to a b | |
6372 | instruction. */ | |
6373 | if (mips_pic == NO_PIC) | |
67c0d1eb | 6374 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 6375 | else |
67c0d1eb | 6376 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6377 | break; |
252b5132 RH |
6378 | |
6379 | /* The jal instructions must be handled as macros because when | |
6380 | generating PIC code they expand to multi-instruction | |
6381 | sequences. Normally they are simple instructions. */ | |
6382 | case M_JAL_1: | |
6383 | dreg = RA; | |
6384 | /* Fall through. */ | |
6385 | case M_JAL_2: | |
3e722fb5 | 6386 | if (mips_pic == NO_PIC) |
67c0d1eb | 6387 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 6388 | else |
252b5132 RH |
6389 | { |
6390 | if (sreg != PIC_CALL_REG) | |
6391 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 6392 | |
67c0d1eb | 6393 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 6394 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 6395 | { |
6478892d TS |
6396 | if (mips_cprestore_offset < 0) |
6397 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6398 | else | |
6399 | { | |
90ecf173 | 6400 | if (!mips_frame_reg_valid) |
7a621144 DJ |
6401 | { |
6402 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6403 | /* Quiet this warning. */ | |
6404 | mips_frame_reg_valid = 1; | |
6405 | } | |
90ecf173 | 6406 | if (!mips_cprestore_valid) |
7a621144 DJ |
6407 | { |
6408 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6409 | /* Quiet this warning. */ | |
6410 | mips_cprestore_valid = 1; | |
6411 | } | |
d3fca0b5 MR |
6412 | if (mips_opts.noreorder) |
6413 | macro_build (NULL, "nop", ""); | |
6478892d | 6414 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6415 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6416 | mips_gp_register, |
256ab948 TS |
6417 | mips_frame_reg, |
6418 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6419 | } |
252b5132 RH |
6420 | } |
6421 | } | |
252b5132 | 6422 | |
8fc2e39e | 6423 | break; |
252b5132 RH |
6424 | |
6425 | case M_JAL_A: | |
6426 | if (mips_pic == NO_PIC) | |
67c0d1eb | 6427 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
6428 | else if (mips_pic == SVR4_PIC) |
6429 | { | |
6430 | /* If this is a reference to an external symbol, and we are | |
6431 | using a small GOT, we want | |
6432 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
6433 | nop | |
f9419b05 | 6434 | jalr $ra,$25 |
252b5132 RH |
6435 | nop |
6436 | lw $gp,cprestore($sp) | |
6437 | The cprestore value is set using the .cprestore | |
6438 | pseudo-op. If we are using a big GOT, we want | |
6439 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
6440 | addu $25,$25,$gp | |
6441 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
6442 | nop | |
f9419b05 | 6443 | jalr $ra,$25 |
252b5132 RH |
6444 | nop |
6445 | lw $gp,cprestore($sp) | |
6446 | If the symbol is not external, we want | |
6447 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6448 | nop | |
6449 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 6450 | jalr $ra,$25 |
252b5132 | 6451 | nop |
438c16b8 | 6452 | lw $gp,cprestore($sp) |
f5040a92 AO |
6453 | |
6454 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
6455 | sequences above, minus nops, unless the symbol is local, | |
6456 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
6457 | GOT_DISP. */ | |
438c16b8 | 6458 | if (HAVE_NEWABI) |
252b5132 | 6459 | { |
90ecf173 | 6460 | if (!mips_big_got) |
f5040a92 | 6461 | { |
4d7206a2 | 6462 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6463 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6464 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 6465 | mips_gp_register); |
4d7206a2 | 6466 | relax_switch (); |
67c0d1eb RS |
6467 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6468 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
6469 | mips_gp_register); |
6470 | relax_end (); | |
f5040a92 AO |
6471 | } |
6472 | else | |
6473 | { | |
4d7206a2 | 6474 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6475 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
6476 | BFD_RELOC_MIPS_CALL_HI16); | |
6477 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6478 | PIC_CALL_REG, mips_gp_register); | |
6479 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6480 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6481 | PIC_CALL_REG); | |
4d7206a2 | 6482 | relax_switch (); |
67c0d1eb RS |
6483 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6484 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
6485 | mips_gp_register); | |
6486 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
6487 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 6488 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 6489 | relax_end (); |
f5040a92 | 6490 | } |
684022ea | 6491 | |
67c0d1eb | 6492 | macro_build_jalr (&offset_expr); |
252b5132 RH |
6493 | } |
6494 | else | |
6495 | { | |
4d7206a2 | 6496 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 6497 | if (!mips_big_got) |
438c16b8 | 6498 | { |
67c0d1eb RS |
6499 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6500 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 6501 | mips_gp_register); |
269137b2 | 6502 | load_delay_nop (); |
4d7206a2 | 6503 | relax_switch (); |
438c16b8 | 6504 | } |
252b5132 | 6505 | else |
252b5132 | 6506 | { |
67c0d1eb RS |
6507 | int gpdelay; |
6508 | ||
6509 | gpdelay = reg_needs_delay (mips_gp_register); | |
6510 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
6511 | BFD_RELOC_MIPS_CALL_HI16); | |
6512 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6513 | PIC_CALL_REG, mips_gp_register); | |
6514 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6515 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6516 | PIC_CALL_REG); | |
269137b2 | 6517 | load_delay_nop (); |
4d7206a2 | 6518 | relax_switch (); |
67c0d1eb RS |
6519 | if (gpdelay) |
6520 | macro_build (NULL, "nop", ""); | |
252b5132 | 6521 | } |
67c0d1eb RS |
6522 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6523 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 6524 | mips_gp_register); |
269137b2 | 6525 | load_delay_nop (); |
67c0d1eb RS |
6526 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6527 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 6528 | relax_end (); |
67c0d1eb | 6529 | macro_build_jalr (&offset_expr); |
438c16b8 | 6530 | |
6478892d TS |
6531 | if (mips_cprestore_offset < 0) |
6532 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6533 | else | |
6534 | { | |
90ecf173 | 6535 | if (!mips_frame_reg_valid) |
7a621144 DJ |
6536 | { |
6537 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6538 | /* Quiet this warning. */ | |
6539 | mips_frame_reg_valid = 1; | |
6540 | } | |
90ecf173 | 6541 | if (!mips_cprestore_valid) |
7a621144 DJ |
6542 | { |
6543 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6544 | /* Quiet this warning. */ | |
6545 | mips_cprestore_valid = 1; | |
6546 | } | |
6478892d | 6547 | if (mips_opts.noreorder) |
67c0d1eb | 6548 | macro_build (NULL, "nop", ""); |
6478892d | 6549 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6550 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6551 | mips_gp_register, |
256ab948 TS |
6552 | mips_frame_reg, |
6553 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6554 | } |
252b5132 RH |
6555 | } |
6556 | } | |
0a44bf69 RS |
6557 | else if (mips_pic == VXWORKS_PIC) |
6558 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
6559 | else |
6560 | abort (); | |
6561 | ||
8fc2e39e | 6562 | break; |
252b5132 RH |
6563 | |
6564 | case M_LB_AB: | |
6565 | s = "lb"; | |
6566 | goto ld; | |
6567 | case M_LBU_AB: | |
6568 | s = "lbu"; | |
6569 | goto ld; | |
6570 | case M_LH_AB: | |
6571 | s = "lh"; | |
6572 | goto ld; | |
6573 | case M_LHU_AB: | |
6574 | s = "lhu"; | |
6575 | goto ld; | |
6576 | case M_LW_AB: | |
6577 | s = "lw"; | |
6578 | goto ld; | |
6579 | case M_LWC0_AB: | |
6580 | s = "lwc0"; | |
bdaaa2e1 | 6581 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6582 | coproc = 1; |
6583 | goto ld; | |
6584 | case M_LWC1_AB: | |
6585 | s = "lwc1"; | |
bdaaa2e1 | 6586 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6587 | coproc = 1; |
6588 | goto ld; | |
6589 | case M_LWC2_AB: | |
6590 | s = "lwc2"; | |
bdaaa2e1 | 6591 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6592 | coproc = 1; |
6593 | goto ld; | |
6594 | case M_LWC3_AB: | |
6595 | s = "lwc3"; | |
bdaaa2e1 | 6596 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6597 | coproc = 1; |
6598 | goto ld; | |
6599 | case M_LWL_AB: | |
6600 | s = "lwl"; | |
6601 | lr = 1; | |
6602 | goto ld; | |
6603 | case M_LWR_AB: | |
6604 | s = "lwr"; | |
6605 | lr = 1; | |
6606 | goto ld; | |
6607 | case M_LDC1_AB: | |
252b5132 | 6608 | s = "ldc1"; |
bdaaa2e1 | 6609 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6610 | coproc = 1; |
6611 | goto ld; | |
6612 | case M_LDC2_AB: | |
6613 | s = "ldc2"; | |
bdaaa2e1 | 6614 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6615 | coproc = 1; |
6616 | goto ld; | |
6617 | case M_LDC3_AB: | |
6618 | s = "ldc3"; | |
bdaaa2e1 | 6619 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6620 | coproc = 1; |
6621 | goto ld; | |
6622 | case M_LDL_AB: | |
6623 | s = "ldl"; | |
6624 | lr = 1; | |
6625 | goto ld; | |
6626 | case M_LDR_AB: | |
6627 | s = "ldr"; | |
6628 | lr = 1; | |
6629 | goto ld; | |
6630 | case M_LL_AB: | |
6631 | s = "ll"; | |
6632 | goto ld; | |
6633 | case M_LLD_AB: | |
6634 | s = "lld"; | |
6635 | goto ld; | |
6636 | case M_LWU_AB: | |
6637 | s = "lwu"; | |
6638 | ld: | |
8fc2e39e | 6639 | if (breg == treg || coproc || lr) |
252b5132 RH |
6640 | { |
6641 | tempreg = AT; | |
6642 | used_at = 1; | |
6643 | } | |
6644 | else | |
6645 | { | |
6646 | tempreg = treg; | |
252b5132 RH |
6647 | } |
6648 | goto ld_st; | |
6649 | case M_SB_AB: | |
6650 | s = "sb"; | |
6651 | goto st; | |
6652 | case M_SH_AB: | |
6653 | s = "sh"; | |
6654 | goto st; | |
6655 | case M_SW_AB: | |
6656 | s = "sw"; | |
6657 | goto st; | |
6658 | case M_SWC0_AB: | |
6659 | s = "swc0"; | |
bdaaa2e1 | 6660 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6661 | coproc = 1; |
6662 | goto st; | |
6663 | case M_SWC1_AB: | |
6664 | s = "swc1"; | |
bdaaa2e1 | 6665 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6666 | coproc = 1; |
6667 | goto st; | |
6668 | case M_SWC2_AB: | |
6669 | s = "swc2"; | |
bdaaa2e1 | 6670 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6671 | coproc = 1; |
6672 | goto st; | |
6673 | case M_SWC3_AB: | |
6674 | s = "swc3"; | |
bdaaa2e1 | 6675 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6676 | coproc = 1; |
6677 | goto st; | |
6678 | case M_SWL_AB: | |
6679 | s = "swl"; | |
6680 | goto st; | |
6681 | case M_SWR_AB: | |
6682 | s = "swr"; | |
6683 | goto st; | |
6684 | case M_SC_AB: | |
6685 | s = "sc"; | |
6686 | goto st; | |
6687 | case M_SCD_AB: | |
6688 | s = "scd"; | |
6689 | goto st; | |
d43b4baf TS |
6690 | case M_CACHE_AB: |
6691 | s = "cache"; | |
6692 | goto st; | |
3eebd5eb MR |
6693 | case M_PREF_AB: |
6694 | s = "pref"; | |
6695 | goto st; | |
252b5132 | 6696 | case M_SDC1_AB: |
252b5132 RH |
6697 | s = "sdc1"; |
6698 | coproc = 1; | |
bdaaa2e1 | 6699 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6700 | goto st; |
6701 | case M_SDC2_AB: | |
6702 | s = "sdc2"; | |
bdaaa2e1 | 6703 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6704 | coproc = 1; |
6705 | goto st; | |
6706 | case M_SDC3_AB: | |
6707 | s = "sdc3"; | |
bdaaa2e1 | 6708 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6709 | coproc = 1; |
6710 | goto st; | |
6711 | case M_SDL_AB: | |
6712 | s = "sdl"; | |
6713 | goto st; | |
6714 | case M_SDR_AB: | |
6715 | s = "sdr"; | |
6716 | st: | |
8fc2e39e TS |
6717 | tempreg = AT; |
6718 | used_at = 1; | |
252b5132 | 6719 | ld_st: |
b19e8a9b AN |
6720 | if (coproc |
6721 | && NO_ISA_COP (mips_opts.arch) | |
6722 | && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0) | |
6723 | { | |
f71d0d44 | 6724 | as_bad (_("Opcode not supported on this processor: %s"), |
b19e8a9b AN |
6725 | mips_cpu_info_from_arch (mips_opts.arch)->name); |
6726 | break; | |
6727 | } | |
6728 | ||
bdaaa2e1 | 6729 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6730 | if (mask == M_LWC1_AB |
6731 | || mask == M_SWC1_AB | |
6732 | || mask == M_LDC1_AB | |
6733 | || mask == M_SDC1_AB | |
6734 | || mask == M_L_DAB | |
6735 | || mask == M_S_DAB) | |
6736 | fmt = "T,o(b)"; | |
3eebd5eb | 6737 | else if (mask == M_CACHE_AB || mask == M_PREF_AB) |
d43b4baf | 6738 | fmt = "k,o(b)"; |
252b5132 RH |
6739 | else if (coproc) |
6740 | fmt = "E,o(b)"; | |
6741 | else | |
6742 | fmt = "t,o(b)"; | |
6743 | ||
6744 | if (offset_expr.X_op != O_constant | |
6745 | && offset_expr.X_op != O_symbol) | |
6746 | { | |
f71d0d44 | 6747 | as_bad (_("Expression too complex")); |
252b5132 RH |
6748 | offset_expr.X_op = O_constant; |
6749 | } | |
6750 | ||
2051e8c4 MR |
6751 | if (HAVE_32BIT_ADDRESSES |
6752 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6753 | { |
6754 | char value [32]; | |
6755 | ||
6756 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6757 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6758 | } |
2051e8c4 | 6759 | |
252b5132 RH |
6760 | /* A constant expression in PIC code can be handled just as it |
6761 | is in non PIC code. */ | |
aed1a261 RS |
6762 | if (offset_expr.X_op == O_constant) |
6763 | { | |
842f8b2a | 6764 | expr1.X_add_number = offset_expr.X_add_number; |
2051e8c4 | 6765 | normalize_address_expr (&expr1); |
842f8b2a MR |
6766 | if (!IS_SEXT_16BIT_NUM (expr1.X_add_number)) |
6767 | { | |
6768 | expr1.X_add_number = ((expr1.X_add_number + 0x8000) | |
6769 | & ~(bfd_vma) 0xffff); | |
6770 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); | |
6771 | if (breg != 0) | |
6772 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6773 | tempreg, tempreg, breg); | |
6774 | breg = tempreg; | |
6775 | } | |
6776 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg); | |
aed1a261 RS |
6777 | } |
6778 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
6779 | { |
6780 | /* If this is a reference to a GP relative symbol, and there | |
6781 | is no base register, we want | |
cdf6fd85 | 6782 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6783 | Otherwise, if there is no base register, we want |
6784 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6785 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6786 | If we have a constant, we need two instructions anyhow, | |
6787 | so we always use the latter form. | |
6788 | ||
6789 | If we have a base register, and this is a reference to a | |
6790 | GP relative symbol, we want | |
6791 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6792 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6793 | Otherwise we want |
6794 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6795 | addu $tempreg,$tempreg,$breg | |
6796 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 6797 | With a constant we always use the latter case. |
76b3015f | 6798 | |
d6bc6245 TS |
6799 | With 64bit address space and no base register and $at usable, |
6800 | we want | |
6801 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6802 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6803 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6804 | dsll32 $tempreg,0 | |
6805 | daddu $tempreg,$at | |
6806 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6807 | If we have a base register, we want | |
6808 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6809 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6810 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6811 | daddu $at,$breg | |
6812 | dsll32 $tempreg,0 | |
6813 | daddu $tempreg,$at | |
6814 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6815 | ||
6816 | Without $at we can't generate the optimal path for superscalar | |
6817 | processors here since this would require two temporary registers. | |
6818 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6819 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6820 | dsll $tempreg,16 | |
6821 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6822 | dsll $tempreg,16 | |
6823 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6824 | If we have a base register, we want | |
6825 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6826 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6827 | dsll $tempreg,16 | |
6828 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6829 | dsll $tempreg,16 | |
6830 | daddu $tempreg,$tempreg,$breg | |
6831 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 6832 | |
6caf9ef4 | 6833 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
6834 | the same sequence as in 32bit address space. */ |
6835 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 6836 | { |
aed1a261 | 6837 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
6838 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6839 | { | |
6840 | relax_start (offset_expr.X_add_symbol); | |
6841 | if (breg == 0) | |
6842 | { | |
6843 | macro_build (&offset_expr, s, fmt, treg, | |
6844 | BFD_RELOC_GPREL16, mips_gp_register); | |
6845 | } | |
6846 | else | |
6847 | { | |
6848 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6849 | tempreg, breg, mips_gp_register); | |
6850 | macro_build (&offset_expr, s, fmt, treg, | |
6851 | BFD_RELOC_GPREL16, tempreg); | |
6852 | } | |
6853 | relax_switch (); | |
6854 | } | |
d6bc6245 | 6855 | |
741fe287 | 6856 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 6857 | { |
67c0d1eb RS |
6858 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6859 | BFD_RELOC_MIPS_HIGHEST); | |
6860 | macro_build (&offset_expr, "lui", "t,u", AT, | |
6861 | BFD_RELOC_HI16_S); | |
6862 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6863 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 6864 | if (breg != 0) |
67c0d1eb RS |
6865 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
6866 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
6867 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
6868 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
6869 | tempreg); | |
d6bc6245 TS |
6870 | used_at = 1; |
6871 | } | |
6872 | else | |
6873 | { | |
67c0d1eb RS |
6874 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6875 | BFD_RELOC_MIPS_HIGHEST); | |
6876 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6877 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6878 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6879 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6880 | tempreg, BFD_RELOC_HI16_S); | |
6881 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6882 | if (breg != 0) |
67c0d1eb | 6883 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6884 | tempreg, tempreg, breg); |
67c0d1eb | 6885 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6886 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 6887 | } |
6caf9ef4 TS |
6888 | |
6889 | if (mips_relax.sequence) | |
6890 | relax_end (); | |
8fc2e39e | 6891 | break; |
d6bc6245 | 6892 | } |
256ab948 | 6893 | |
252b5132 RH |
6894 | if (breg == 0) |
6895 | { | |
67c0d1eb | 6896 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6897 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6898 | { |
4d7206a2 | 6899 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6900 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6901 | mips_gp_register); | |
4d7206a2 | 6902 | relax_switch (); |
252b5132 | 6903 | } |
67c0d1eb RS |
6904 | macro_build_lui (&offset_expr, tempreg); |
6905 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6906 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6907 | if (mips_relax.sequence) |
6908 | relax_end (); | |
252b5132 RH |
6909 | } |
6910 | else | |
6911 | { | |
67c0d1eb | 6912 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6913 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6914 | { |
4d7206a2 | 6915 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6916 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6917 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6918 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6919 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6920 | relax_switch (); |
252b5132 | 6921 | } |
67c0d1eb RS |
6922 | macro_build_lui (&offset_expr, tempreg); |
6923 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6924 | tempreg, tempreg, breg); |
67c0d1eb | 6925 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6926 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6927 | if (mips_relax.sequence) |
6928 | relax_end (); | |
252b5132 RH |
6929 | } |
6930 | } | |
0a44bf69 | 6931 | else if (!mips_big_got) |
252b5132 | 6932 | { |
ed6fb7bd | 6933 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6934 | |
252b5132 RH |
6935 | /* If this is a reference to an external symbol, we want |
6936 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6937 | nop | |
6938 | <op> $treg,0($tempreg) | |
6939 | Otherwise we want | |
6940 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6941 | nop | |
6942 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6943 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6944 | |
6945 | For NewABI, we want | |
6946 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6947 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6948 | ||
252b5132 RH |
6949 | If there is a base register, we add it to $tempreg before |
6950 | the <op>. If there is a constant, we stick it in the | |
6951 | <op> instruction. We don't handle constants larger than | |
6952 | 16 bits, because we have no way to load the upper 16 bits | |
6953 | (actually, we could handle them for the subset of cases | |
6954 | in which we are not using $at). */ | |
9c2799c2 | 6955 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
6956 | if (HAVE_NEWABI) |
6957 | { | |
67c0d1eb RS |
6958 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6959 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6960 | if (breg != 0) |
67c0d1eb | 6961 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6962 | tempreg, tempreg, breg); |
67c0d1eb | 6963 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6964 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6965 | break; |
6966 | } | |
252b5132 RH |
6967 | expr1.X_add_number = offset_expr.X_add_number; |
6968 | offset_expr.X_add_number = 0; | |
6969 | if (expr1.X_add_number < -0x8000 | |
6970 | || expr1.X_add_number >= 0x8000) | |
6971 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6972 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6973 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6974 | load_delay_nop (); |
4d7206a2 RS |
6975 | relax_start (offset_expr.X_add_symbol); |
6976 | relax_switch (); | |
67c0d1eb RS |
6977 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6978 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6979 | relax_end (); |
252b5132 | 6980 | if (breg != 0) |
67c0d1eb | 6981 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6982 | tempreg, tempreg, breg); |
67c0d1eb | 6983 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6984 | } |
0a44bf69 | 6985 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 6986 | { |
67c0d1eb | 6987 | int gpdelay; |
252b5132 RH |
6988 | |
6989 | /* If this is a reference to an external symbol, we want | |
6990 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6991 | addu $tempreg,$tempreg,$gp | |
6992 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6993 | <op> $treg,0($tempreg) | |
6994 | Otherwise we want | |
6995 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6996 | nop | |
6997 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6998 | <op> $treg,0($tempreg) | |
6999 | If there is a base register, we add it to $tempreg before | |
7000 | the <op>. If there is a constant, we stick it in the | |
7001 | <op> instruction. We don't handle constants larger than | |
7002 | 16 bits, because we have no way to load the upper 16 bits | |
7003 | (actually, we could handle them for the subset of cases | |
f5040a92 | 7004 | in which we are not using $at). */ |
9c2799c2 | 7005 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
7006 | expr1.X_add_number = offset_expr.X_add_number; |
7007 | offset_expr.X_add_number = 0; | |
7008 | if (expr1.X_add_number < -0x8000 | |
7009 | || expr1.X_add_number >= 0x8000) | |
7010 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7011 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 7012 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7013 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 7014 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
7015 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
7016 | mips_gp_register); | |
7017 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
7018 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 7019 | relax_switch (); |
67c0d1eb RS |
7020 | if (gpdelay) |
7021 | macro_build (NULL, "nop", ""); | |
7022 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
7023 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7024 | load_delay_nop (); |
67c0d1eb RS |
7025 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
7026 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
7027 | relax_end (); |
7028 | ||
252b5132 | 7029 | if (breg != 0) |
67c0d1eb | 7030 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7031 | tempreg, tempreg, breg); |
67c0d1eb | 7032 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 7033 | } |
0a44bf69 | 7034 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 7035 | { |
f5040a92 AO |
7036 | /* If this is a reference to an external symbol, we want |
7037 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7038 | add $tempreg,$tempreg,$gp | |
7039 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7040 | <op> $treg,<ofst>($tempreg) | |
7041 | Otherwise, for local symbols, we want: | |
7042 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
7043 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 7044 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 7045 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7046 | offset_expr.X_add_number = 0; |
7047 | if (expr1.X_add_number < -0x8000 | |
7048 | || expr1.X_add_number >= 0x8000) | |
7049 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 7050 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7051 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 7052 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
7053 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
7054 | mips_gp_register); | |
7055 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
7056 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 7057 | if (breg != 0) |
67c0d1eb | 7058 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7059 | tempreg, tempreg, breg); |
67c0d1eb | 7060 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 7061 | |
4d7206a2 | 7062 | relax_switch (); |
f5040a92 | 7063 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
7064 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7065 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 7066 | if (breg != 0) |
67c0d1eb | 7067 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7068 | tempreg, tempreg, breg); |
67c0d1eb | 7069 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 7070 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 7071 | relax_end (); |
f5040a92 | 7072 | } |
252b5132 RH |
7073 | else |
7074 | abort (); | |
7075 | ||
252b5132 RH |
7076 | break; |
7077 | ||
7078 | case M_LI: | |
7079 | case M_LI_S: | |
67c0d1eb | 7080 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 7081 | break; |
252b5132 RH |
7082 | |
7083 | case M_DLI: | |
67c0d1eb | 7084 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 7085 | break; |
252b5132 RH |
7086 | |
7087 | case M_LI_SS: | |
7088 | if (imm_expr.X_op == O_constant) | |
7089 | { | |
8fc2e39e | 7090 | used_at = 1; |
67c0d1eb RS |
7091 | load_register (AT, &imm_expr, 0); |
7092 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
7093 | break; |
7094 | } | |
7095 | else | |
7096 | { | |
9c2799c2 | 7097 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
7098 | && strcmp (segment_name (S_GET_SEGMENT |
7099 | (offset_expr.X_add_symbol)), | |
7100 | ".lit4") == 0 | |
7101 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 7102 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 7103 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 7104 | break; |
252b5132 RH |
7105 | } |
7106 | ||
7107 | case M_LI_D: | |
ca4e0257 RS |
7108 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
7109 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
7110 | order 32 bits of the value and the low order 32 bits are either | |
7111 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
7112 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
7113 | { | |
ca4e0257 | 7114 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 7115 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
7116 | else |
7117 | { | |
7118 | int hreg, lreg; | |
7119 | ||
7120 | if (target_big_endian) | |
7121 | { | |
7122 | hreg = treg; | |
7123 | lreg = treg + 1; | |
7124 | } | |
7125 | else | |
7126 | { | |
7127 | hreg = treg + 1; | |
7128 | lreg = treg; | |
7129 | } | |
7130 | ||
7131 | if (hreg <= 31) | |
67c0d1eb | 7132 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
7133 | if (lreg <= 31) |
7134 | { | |
7135 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 7136 | move_register (lreg, 0); |
252b5132 RH |
7137 | else |
7138 | { | |
9c2799c2 | 7139 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 7140 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
7141 | } |
7142 | } | |
7143 | } | |
8fc2e39e | 7144 | break; |
252b5132 RH |
7145 | } |
7146 | ||
7147 | /* We know that sym is in the .rdata section. First we get the | |
7148 | upper 16 bits of the address. */ | |
7149 | if (mips_pic == NO_PIC) | |
7150 | { | |
67c0d1eb | 7151 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 7152 | used_at = 1; |
252b5132 | 7153 | } |
0a44bf69 | 7154 | else |
252b5132 | 7155 | { |
67c0d1eb RS |
7156 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
7157 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 7158 | used_at = 1; |
252b5132 | 7159 | } |
bdaaa2e1 | 7160 | |
252b5132 | 7161 | /* Now we load the register(s). */ |
ca4e0257 | 7162 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
7163 | { |
7164 | used_at = 1; | |
7165 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
7166 | } | |
252b5132 RH |
7167 | else |
7168 | { | |
8fc2e39e | 7169 | used_at = 1; |
67c0d1eb | 7170 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 7171 | if (treg != RA) |
252b5132 RH |
7172 | { |
7173 | /* FIXME: How in the world do we deal with the possible | |
7174 | overflow here? */ | |
7175 | offset_expr.X_add_number += 4; | |
67c0d1eb | 7176 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 7177 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
7178 | } |
7179 | } | |
252b5132 RH |
7180 | break; |
7181 | ||
7182 | case M_LI_DD: | |
ca4e0257 RS |
7183 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
7184 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
7185 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
7186 | the value and the low order 32 bits are either zero or in | |
7187 | OFFSET_EXPR. */ | |
252b5132 RH |
7188 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
7189 | { | |
8fc2e39e | 7190 | used_at = 1; |
67c0d1eb | 7191 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
7192 | if (HAVE_64BIT_FPRS) |
7193 | { | |
9c2799c2 | 7194 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 7195 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 7196 | } |
252b5132 RH |
7197 | else |
7198 | { | |
67c0d1eb | 7199 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 7200 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 7201 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
7202 | else |
7203 | { | |
9c2799c2 | 7204 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
7205 | load_register (AT, &offset_expr, 0); |
7206 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
7207 | } |
7208 | } | |
7209 | break; | |
7210 | } | |
7211 | ||
9c2799c2 | 7212 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 7213 | && offset_expr.X_add_number == 0); |
252b5132 RH |
7214 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
7215 | if (strcmp (s, ".lit8") == 0) | |
7216 | { | |
e7af610e | 7217 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 7218 | { |
67c0d1eb | 7219 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 7220 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 7221 | break; |
252b5132 | 7222 | } |
c9914766 | 7223 | breg = mips_gp_register; |
252b5132 RH |
7224 | r = BFD_RELOC_MIPS_LITERAL; |
7225 | goto dob; | |
7226 | } | |
7227 | else | |
7228 | { | |
9c2799c2 | 7229 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 7230 | used_at = 1; |
0a44bf69 | 7231 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
7232 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
7233 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
7234 | else |
7235 | { | |
7236 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 7237 | macro_build_lui (&offset_expr, AT); |
252b5132 | 7238 | } |
bdaaa2e1 | 7239 | |
e7af610e | 7240 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 7241 | { |
67c0d1eb RS |
7242 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
7243 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
7244 | break; |
7245 | } | |
7246 | breg = AT; | |
7247 | r = BFD_RELOC_LO16; | |
7248 | goto dob; | |
7249 | } | |
7250 | ||
7251 | case M_L_DOB: | |
252b5132 RH |
7252 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7253 | to adjust when loading from memory. */ | |
7254 | r = BFD_RELOC_LO16; | |
7255 | dob: | |
9c2799c2 | 7256 | gas_assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 7257 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 7258 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
7259 | /* FIXME: A possible overflow which I don't know how to deal |
7260 | with. */ | |
7261 | offset_expr.X_add_number += 4; | |
67c0d1eb | 7262 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 7263 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
7264 | break; |
7265 | ||
c4a68bea MR |
7266 | case M_S_DOB: |
7267 | gas_assert (mips_opts.isa == ISA_MIPS1); | |
7268 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
7269 | to adjust when storing to memory. */ | |
7270 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
7271 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
7272 | offset_expr.X_add_number += 4; | |
7273 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
7274 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
7275 | break; | |
7276 | ||
252b5132 RH |
7277 | case M_L_DAB: |
7278 | /* | |
7279 | * The MIPS assembler seems to check for X_add_number not | |
7280 | * being double aligned and generating: | |
7281 | * lui at,%hi(foo+1) | |
7282 | * addu at,at,v1 | |
7283 | * addiu at,at,%lo(foo+1) | |
7284 | * lwc1 f2,0(at) | |
7285 | * lwc1 f3,4(at) | |
7286 | * But, the resulting address is the same after relocation so why | |
7287 | * generate the extra instruction? | |
7288 | */ | |
bdaaa2e1 | 7289 | /* Itbl support may require additional care here. */ |
252b5132 | 7290 | coproc = 1; |
e7af610e | 7291 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
7292 | { |
7293 | s = "ldc1"; | |
7294 | goto ld; | |
7295 | } | |
7296 | ||
7297 | s = "lwc1"; | |
7298 | fmt = "T,o(b)"; | |
7299 | goto ldd_std; | |
7300 | ||
7301 | case M_S_DAB: | |
e7af610e | 7302 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
7303 | { |
7304 | s = "sdc1"; | |
7305 | goto st; | |
7306 | } | |
7307 | ||
7308 | s = "swc1"; | |
7309 | fmt = "T,o(b)"; | |
bdaaa2e1 | 7310 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7311 | coproc = 1; |
7312 | goto ldd_std; | |
7313 | ||
7314 | case M_LD_AB: | |
ca4e0257 | 7315 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
7316 | { |
7317 | s = "ld"; | |
7318 | goto ld; | |
7319 | } | |
7320 | ||
7321 | s = "lw"; | |
7322 | fmt = "t,o(b)"; | |
7323 | goto ldd_std; | |
7324 | ||
7325 | case M_SD_AB: | |
ca4e0257 | 7326 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
7327 | { |
7328 | s = "sd"; | |
7329 | goto st; | |
7330 | } | |
7331 | ||
7332 | s = "sw"; | |
7333 | fmt = "t,o(b)"; | |
7334 | ||
7335 | ldd_std: | |
7336 | if (offset_expr.X_op != O_symbol | |
7337 | && offset_expr.X_op != O_constant) | |
7338 | { | |
f71d0d44 | 7339 | as_bad (_("Expression too complex")); |
252b5132 RH |
7340 | offset_expr.X_op = O_constant; |
7341 | } | |
7342 | ||
2051e8c4 MR |
7343 | if (HAVE_32BIT_ADDRESSES |
7344 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
7345 | { |
7346 | char value [32]; | |
7347 | ||
7348 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 7349 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 7350 | } |
2051e8c4 | 7351 | |
252b5132 RH |
7352 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7353 | to adjust when loading from memory. We set coproc if we must | |
7354 | load $fn+1 first. */ | |
bdaaa2e1 | 7355 | /* Itbl support may require additional care here. */ |
90ecf173 | 7356 | if (!target_big_endian) |
252b5132 RH |
7357 | coproc = 0; |
7358 | ||
90ecf173 | 7359 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
7360 | { |
7361 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
7362 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
7363 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
7364 | If we have a base register, we use this |
7365 | addu $at,$breg,$gp | |
cdf6fd85 TS |
7366 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
7367 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
7368 | If this is not a GP relative symbol, we want |
7369 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7370 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7371 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7372 | If there is a base register, we add it to $at after the | |
7373 | lui instruction. If there is a constant, we always use | |
7374 | the last case. */ | |
39a59cf8 MR |
7375 | if (offset_expr.X_op == O_symbol |
7376 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7377 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 7378 | { |
4d7206a2 | 7379 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
7380 | if (breg == 0) |
7381 | { | |
c9914766 | 7382 | tempreg = mips_gp_register; |
252b5132 RH |
7383 | } |
7384 | else | |
7385 | { | |
67c0d1eb | 7386 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7387 | AT, breg, mips_gp_register); |
252b5132 | 7388 | tempreg = AT; |
252b5132 RH |
7389 | used_at = 1; |
7390 | } | |
7391 | ||
beae10d5 | 7392 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7393 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7394 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
7395 | offset_expr.X_add_number += 4; |
7396 | ||
7397 | /* Set mips_optimize to 2 to avoid inserting an | |
7398 | undesired nop. */ | |
7399 | hold_mips_optimize = mips_optimize; | |
7400 | mips_optimize = 2; | |
beae10d5 | 7401 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7402 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7403 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
7404 | mips_optimize = hold_mips_optimize; |
7405 | ||
4d7206a2 | 7406 | relax_switch (); |
252b5132 | 7407 | |
0970e49e | 7408 | offset_expr.X_add_number -= 4; |
252b5132 | 7409 | } |
8fc2e39e | 7410 | used_at = 1; |
67c0d1eb | 7411 | macro_build_lui (&offset_expr, AT); |
252b5132 | 7412 | if (breg != 0) |
67c0d1eb | 7413 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7414 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7415 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7416 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7417 | /* FIXME: How do we handle overflow here? */ |
7418 | offset_expr.X_add_number += 4; | |
beae10d5 | 7419 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7420 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7421 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
7422 | if (mips_relax.sequence) |
7423 | relax_end (); | |
bdaaa2e1 | 7424 | } |
0a44bf69 | 7425 | else if (!mips_big_got) |
252b5132 | 7426 | { |
252b5132 RH |
7427 | /* If this is a reference to an external symbol, we want |
7428 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7429 | nop | |
7430 | <op> $treg,0($at) | |
7431 | <op> $treg+1,4($at) | |
7432 | Otherwise we want | |
7433 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7434 | nop | |
7435 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7436 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7437 | If there is a base register we add it to $at before the | |
7438 | lwc1 instructions. If there is a constant we include it | |
7439 | in the lwc1 instructions. */ | |
7440 | used_at = 1; | |
7441 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
7442 | if (expr1.X_add_number < -0x8000 |
7443 | || expr1.X_add_number >= 0x8000 - 4) | |
7444 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7445 | load_got_offset (AT, &offset_expr); |
269137b2 | 7446 | load_delay_nop (); |
252b5132 | 7447 | if (breg != 0) |
67c0d1eb | 7448 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
7449 | |
7450 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7451 | nop. */ | |
7452 | hold_mips_optimize = mips_optimize; | |
7453 | mips_optimize = 2; | |
4d7206a2 | 7454 | |
beae10d5 | 7455 | /* Itbl support may require additional care here. */ |
4d7206a2 | 7456 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7457 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
7458 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7459 | expr1.X_add_number += 4; |
67c0d1eb RS |
7460 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
7461 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7462 | relax_switch (); |
67c0d1eb RS |
7463 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7464 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7465 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7466 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7467 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7468 | relax_end (); |
252b5132 | 7469 | |
4d7206a2 | 7470 | mips_optimize = hold_mips_optimize; |
252b5132 | 7471 | } |
0a44bf69 | 7472 | else if (mips_big_got) |
252b5132 | 7473 | { |
67c0d1eb | 7474 | int gpdelay; |
252b5132 RH |
7475 | |
7476 | /* If this is a reference to an external symbol, we want | |
7477 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7478 | addu $at,$at,$gp | |
7479 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
7480 | nop | |
7481 | <op> $treg,0($at) | |
7482 | <op> $treg+1,4($at) | |
7483 | Otherwise we want | |
7484 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7485 | nop | |
7486 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7487 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7488 | If there is a base register we add it to $at before the | |
7489 | lwc1 instructions. If there is a constant we include it | |
7490 | in the lwc1 instructions. */ | |
7491 | used_at = 1; | |
7492 | expr1.X_add_number = offset_expr.X_add_number; | |
7493 | offset_expr.X_add_number = 0; | |
7494 | if (expr1.X_add_number < -0x8000 | |
7495 | || expr1.X_add_number >= 0x8000 - 4) | |
7496 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7497 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 7498 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7499 | macro_build (&offset_expr, "lui", "t,u", |
7500 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
7501 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 7502 | AT, AT, mips_gp_register); |
67c0d1eb | 7503 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7504 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 7505 | load_delay_nop (); |
252b5132 | 7506 | if (breg != 0) |
67c0d1eb | 7507 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7508 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7509 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7510 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7511 | expr1.X_add_number += 4; |
7512 | ||
7513 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7514 | nop. */ | |
7515 | hold_mips_optimize = mips_optimize; | |
7516 | mips_optimize = 2; | |
beae10d5 | 7517 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7518 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7519 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7520 | mips_optimize = hold_mips_optimize; |
7521 | expr1.X_add_number -= 4; | |
7522 | ||
4d7206a2 RS |
7523 | relax_switch (); |
7524 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
7525 | if (gpdelay) |
7526 | macro_build (NULL, "nop", ""); | |
7527 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
7528 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7529 | load_delay_nop (); |
252b5132 | 7530 | if (breg != 0) |
67c0d1eb | 7531 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7532 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7533 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7534 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7535 | offset_expr.X_add_number += 4; |
252b5132 RH |
7536 | |
7537 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7538 | nop. */ | |
7539 | hold_mips_optimize = mips_optimize; | |
7540 | mips_optimize = 2; | |
beae10d5 | 7541 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7542 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7543 | BFD_RELOC_LO16, AT); | |
252b5132 | 7544 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 7545 | relax_end (); |
252b5132 | 7546 | } |
252b5132 RH |
7547 | else |
7548 | abort (); | |
7549 | ||
252b5132 RH |
7550 | break; |
7551 | ||
7552 | case M_LD_OB: | |
704897fb | 7553 | s = HAVE_64BIT_GPRS ? "ld" : "lw"; |
252b5132 RH |
7554 | goto sd_ob; |
7555 | case M_SD_OB: | |
704897fb | 7556 | s = HAVE_64BIT_GPRS ? "sd" : "sw"; |
252b5132 | 7557 | sd_ob: |
4614d845 MR |
7558 | macro_build (&offset_expr, s, "t,o(b)", treg, |
7559 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
7560 | breg); | |
704897fb MR |
7561 | if (!HAVE_64BIT_GPRS) |
7562 | { | |
7563 | offset_expr.X_add_number += 4; | |
7564 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, | |
4614d845 MR |
7565 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], |
7566 | breg); | |
704897fb | 7567 | } |
8fc2e39e | 7568 | break; |
252b5132 RH |
7569 | |
7570 | /* New code added to support COPZ instructions. | |
7571 | This code builds table entries out of the macros in mip_opcodes. | |
7572 | R4000 uses interlocks to handle coproc delays. | |
7573 | Other chips (like the R3000) require nops to be inserted for delays. | |
7574 | ||
f72c8c98 | 7575 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
7576 | In order to fill delay slots for non-interlocked chips, |
7577 | we must have a way to specify delays based on the coprocessor. | |
7578 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
7579 | What are the side-effects of the cop instruction? | |
7580 | What cache support might we have and what are its effects? | |
7581 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 7582 | What registers are read/set/modified? |
252b5132 RH |
7583 | |
7584 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 7585 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
7586 | |
7587 | case M_COP0: | |
7588 | s = "c0"; | |
7589 | goto copz; | |
7590 | case M_COP1: | |
7591 | s = "c1"; | |
7592 | goto copz; | |
7593 | case M_COP2: | |
7594 | s = "c2"; | |
7595 | goto copz; | |
7596 | case M_COP3: | |
7597 | s = "c3"; | |
7598 | copz: | |
b19e8a9b AN |
7599 | if (NO_ISA_COP (mips_opts.arch) |
7600 | && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0) | |
7601 | { | |
7602 | as_bad (_("opcode not supported on this processor: %s"), | |
7603 | mips_cpu_info_from_arch (mips_opts.arch)->name); | |
7604 | break; | |
7605 | } | |
7606 | ||
252b5132 RH |
7607 | /* For now we just do C (same as Cz). The parameter will be |
7608 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 7609 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 7610 | break; |
252b5132 | 7611 | |
ea1fb5dc | 7612 | case M_MOVE: |
67c0d1eb | 7613 | move_register (dreg, sreg); |
8fc2e39e | 7614 | break; |
ea1fb5dc | 7615 | |
252b5132 RH |
7616 | case M_DMUL: |
7617 | dbl = 1; | |
7618 | case M_MUL: | |
67c0d1eb RS |
7619 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
7620 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 7621 | break; |
252b5132 RH |
7622 | |
7623 | case M_DMUL_I: | |
7624 | dbl = 1; | |
7625 | case M_MUL_I: | |
7626 | /* The MIPS assembler some times generates shifts and adds. I'm | |
7627 | not trying to be that fancy. GCC should do this for us | |
7628 | anyway. */ | |
8fc2e39e | 7629 | used_at = 1; |
67c0d1eb RS |
7630 | load_register (AT, &imm_expr, dbl); |
7631 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
7632 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
7633 | break; |
7634 | ||
7635 | case M_DMULO_I: | |
7636 | dbl = 1; | |
7637 | case M_MULO_I: | |
7638 | imm = 1; | |
7639 | goto do_mulo; | |
7640 | ||
7641 | case M_DMULO: | |
7642 | dbl = 1; | |
7643 | case M_MULO: | |
7644 | do_mulo: | |
7d10b47d | 7645 | start_noreorder (); |
8fc2e39e | 7646 | used_at = 1; |
252b5132 | 7647 | if (imm) |
67c0d1eb RS |
7648 | load_register (AT, &imm_expr, dbl); |
7649 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
7650 | macro_build (NULL, "mflo", "d", dreg); | |
7651 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
7652 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 7653 | if (mips_trap) |
67c0d1eb | 7654 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
7655 | else |
7656 | { | |
7657 | expr1.X_add_number = 8; | |
67c0d1eb | 7658 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
a605d2b3 | 7659 | macro_build (NULL, "nop", ""); |
67c0d1eb | 7660 | macro_build (NULL, "break", "c", 6); |
252b5132 | 7661 | } |
7d10b47d | 7662 | end_noreorder (); |
67c0d1eb | 7663 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
7664 | break; |
7665 | ||
7666 | case M_DMULOU_I: | |
7667 | dbl = 1; | |
7668 | case M_MULOU_I: | |
7669 | imm = 1; | |
7670 | goto do_mulou; | |
7671 | ||
7672 | case M_DMULOU: | |
7673 | dbl = 1; | |
7674 | case M_MULOU: | |
7675 | do_mulou: | |
7d10b47d | 7676 | start_noreorder (); |
8fc2e39e | 7677 | used_at = 1; |
252b5132 | 7678 | if (imm) |
67c0d1eb RS |
7679 | load_register (AT, &imm_expr, dbl); |
7680 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 7681 | sreg, imm ? AT : treg); |
67c0d1eb RS |
7682 | macro_build (NULL, "mfhi", "d", AT); |
7683 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 7684 | if (mips_trap) |
c80c840e | 7685 | macro_build (NULL, "tne", "s,t,q", AT, ZERO, 6); |
252b5132 RH |
7686 | else |
7687 | { | |
7688 | expr1.X_add_number = 8; | |
c80c840e | 7689 | macro_build (&expr1, "beq", "s,t,p", AT, ZERO); |
a605d2b3 | 7690 | macro_build (NULL, "nop", ""); |
67c0d1eb | 7691 | macro_build (NULL, "break", "c", 6); |
252b5132 | 7692 | } |
7d10b47d | 7693 | end_noreorder (); |
252b5132 RH |
7694 | break; |
7695 | ||
771c7ce4 | 7696 | case M_DROL: |
fef14a42 | 7697 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7698 | { |
7699 | if (dreg == sreg) | |
7700 | { | |
7701 | tempreg = AT; | |
7702 | used_at = 1; | |
7703 | } | |
7704 | else | |
7705 | { | |
7706 | tempreg = dreg; | |
82dd0097 | 7707 | } |
67c0d1eb RS |
7708 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
7709 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7710 | break; |
82dd0097 | 7711 | } |
8fc2e39e | 7712 | used_at = 1; |
c80c840e | 7713 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7714 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
7715 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
7716 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7717 | break; |
7718 | ||
252b5132 | 7719 | case M_ROL: |
fef14a42 | 7720 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
7721 | { |
7722 | if (dreg == sreg) | |
7723 | { | |
7724 | tempreg = AT; | |
7725 | used_at = 1; | |
7726 | } | |
7727 | else | |
7728 | { | |
7729 | tempreg = dreg; | |
82dd0097 | 7730 | } |
67c0d1eb RS |
7731 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
7732 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7733 | break; |
82dd0097 | 7734 | } |
8fc2e39e | 7735 | used_at = 1; |
c80c840e | 7736 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7737 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
7738 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
7739 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7740 | break; |
7741 | ||
771c7ce4 TS |
7742 | case M_DROL_I: |
7743 | { | |
7744 | unsigned int rot; | |
91d6fa6a NC |
7745 | char *l; |
7746 | char *rr; | |
771c7ce4 TS |
7747 | |
7748 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7749 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7750 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7751 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
7752 | { |
7753 | rot = (64 - rot) & 0x3f; | |
7754 | if (rot >= 32) | |
67c0d1eb | 7755 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 7756 | else |
67c0d1eb | 7757 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7758 | break; |
60b63b72 | 7759 | } |
483fc7cd | 7760 | if (rot == 0) |
483fc7cd | 7761 | { |
67c0d1eb | 7762 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7763 | break; |
483fc7cd | 7764 | } |
82dd0097 | 7765 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 7766 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 7767 | rot &= 0x1f; |
8fc2e39e | 7768 | used_at = 1; |
67c0d1eb | 7769 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
91d6fa6a | 7770 | macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); |
67c0d1eb | 7771 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
7772 | } |
7773 | break; | |
7774 | ||
252b5132 | 7775 | case M_ROL_I: |
771c7ce4 TS |
7776 | { |
7777 | unsigned int rot; | |
7778 | ||
7779 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7780 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7781 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7782 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 7783 | { |
67c0d1eb | 7784 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 7785 | break; |
60b63b72 | 7786 | } |
483fc7cd | 7787 | if (rot == 0) |
483fc7cd | 7788 | { |
67c0d1eb | 7789 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7790 | break; |
483fc7cd | 7791 | } |
8fc2e39e | 7792 | used_at = 1; |
67c0d1eb RS |
7793 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
7794 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7795 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7796 | } |
7797 | break; | |
7798 | ||
7799 | case M_DROR: | |
fef14a42 | 7800 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7801 | { |
67c0d1eb | 7802 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7803 | break; |
82dd0097 | 7804 | } |
8fc2e39e | 7805 | used_at = 1; |
c80c840e | 7806 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7807 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
7808 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7809 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7810 | break; |
7811 | ||
7812 | case M_ROR: | |
fef14a42 | 7813 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7814 | { |
67c0d1eb | 7815 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7816 | break; |
82dd0097 | 7817 | } |
8fc2e39e | 7818 | used_at = 1; |
c80c840e | 7819 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7820 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
7821 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7822 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7823 | break; |
7824 | ||
771c7ce4 TS |
7825 | case M_DROR_I: |
7826 | { | |
7827 | unsigned int rot; | |
91d6fa6a NC |
7828 | char *l; |
7829 | char *rr; | |
771c7ce4 TS |
7830 | |
7831 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7832 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7833 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7834 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7835 | { |
7836 | if (rot >= 32) | |
67c0d1eb | 7837 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7838 | else |
67c0d1eb | 7839 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7840 | break; |
82dd0097 | 7841 | } |
483fc7cd | 7842 | if (rot == 0) |
483fc7cd | 7843 | { |
67c0d1eb | 7844 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7845 | break; |
483fc7cd | 7846 | } |
91d6fa6a | 7847 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
7848 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
7849 | rot &= 0x1f; | |
8fc2e39e | 7850 | used_at = 1; |
91d6fa6a | 7851 | macro_build (NULL, rr, "d,w,<", AT, sreg, rot); |
67c0d1eb RS |
7852 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); |
7853 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7854 | } |
7855 | break; | |
7856 | ||
252b5132 | 7857 | case M_ROR_I: |
771c7ce4 TS |
7858 | { |
7859 | unsigned int rot; | |
7860 | ||
7861 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7862 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7863 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7864 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7865 | { |
67c0d1eb | 7866 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7867 | break; |
82dd0097 | 7868 | } |
483fc7cd | 7869 | if (rot == 0) |
483fc7cd | 7870 | { |
67c0d1eb | 7871 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7872 | break; |
483fc7cd | 7873 | } |
8fc2e39e | 7874 | used_at = 1; |
67c0d1eb RS |
7875 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7876 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7877 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7878 | } |
252b5132 RH |
7879 | break; |
7880 | ||
252b5132 RH |
7881 | case M_SEQ: |
7882 | if (sreg == 0) | |
67c0d1eb | 7883 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7884 | else if (treg == 0) |
67c0d1eb | 7885 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7886 | else |
7887 | { | |
67c0d1eb RS |
7888 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7889 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7890 | } |
8fc2e39e | 7891 | break; |
252b5132 RH |
7892 | |
7893 | case M_SEQ_I: | |
7894 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7895 | { | |
67c0d1eb | 7896 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7897 | break; |
252b5132 RH |
7898 | } |
7899 | if (sreg == 0) | |
7900 | { | |
7901 | as_warn (_("Instruction %s: result is always false"), | |
7902 | ip->insn_mo->name); | |
67c0d1eb | 7903 | move_register (dreg, 0); |
8fc2e39e | 7904 | break; |
252b5132 | 7905 | } |
dd3cbb7e NC |
7906 | if (CPU_HAS_SEQ (mips_opts.arch) |
7907 | && -512 <= imm_expr.X_add_number | |
7908 | && imm_expr.X_add_number < 512) | |
7909 | { | |
7910 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 7911 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
7912 | break; |
7913 | } | |
252b5132 RH |
7914 | if (imm_expr.X_op == O_constant |
7915 | && imm_expr.X_add_number >= 0 | |
7916 | && imm_expr.X_add_number < 0x10000) | |
7917 | { | |
67c0d1eb | 7918 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7919 | } |
7920 | else if (imm_expr.X_op == O_constant | |
7921 | && imm_expr.X_add_number > -0x8000 | |
7922 | && imm_expr.X_add_number < 0) | |
7923 | { | |
7924 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7925 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7926 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 7927 | } |
dd3cbb7e NC |
7928 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
7929 | { | |
7930 | used_at = 1; | |
7931 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
7932 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
7933 | break; | |
7934 | } | |
252b5132 RH |
7935 | else |
7936 | { | |
67c0d1eb RS |
7937 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7938 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7939 | used_at = 1; |
7940 | } | |
67c0d1eb | 7941 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7942 | break; |
252b5132 RH |
7943 | |
7944 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7945 | s = "slt"; | |
7946 | goto sge; | |
7947 | case M_SGEU: | |
7948 | s = "sltu"; | |
7949 | sge: | |
67c0d1eb RS |
7950 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7951 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7952 | break; |
252b5132 RH |
7953 | |
7954 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7955 | case M_SGEU_I: | |
7956 | if (imm_expr.X_op == O_constant | |
7957 | && imm_expr.X_add_number >= -0x8000 | |
7958 | && imm_expr.X_add_number < 0x8000) | |
7959 | { | |
67c0d1eb RS |
7960 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7961 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7962 | } |
7963 | else | |
7964 | { | |
67c0d1eb RS |
7965 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7966 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7967 | dreg, sreg, AT); | |
252b5132 RH |
7968 | used_at = 1; |
7969 | } | |
67c0d1eb | 7970 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7971 | break; |
252b5132 RH |
7972 | |
7973 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7974 | s = "slt"; | |
7975 | goto sgt; | |
7976 | case M_SGTU: | |
7977 | s = "sltu"; | |
7978 | sgt: | |
67c0d1eb | 7979 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7980 | break; |
252b5132 RH |
7981 | |
7982 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7983 | s = "slt"; | |
7984 | goto sgti; | |
7985 | case M_SGTU_I: | |
7986 | s = "sltu"; | |
7987 | sgti: | |
8fc2e39e | 7988 | used_at = 1; |
67c0d1eb RS |
7989 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7990 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7991 | break; |
7992 | ||
2396cfb9 | 7993 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7994 | s = "slt"; |
7995 | goto sle; | |
7996 | case M_SLEU: | |
7997 | s = "sltu"; | |
7998 | sle: | |
67c0d1eb RS |
7999 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8000 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 8001 | break; |
252b5132 | 8002 | |
2396cfb9 | 8003 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
8004 | s = "slt"; |
8005 | goto slei; | |
8006 | case M_SLEU_I: | |
8007 | s = "sltu"; | |
8008 | slei: | |
8fc2e39e | 8009 | used_at = 1; |
67c0d1eb RS |
8010 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
8011 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
8012 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
8013 | break; |
8014 | ||
8015 | case M_SLT_I: | |
8016 | if (imm_expr.X_op == O_constant | |
8017 | && imm_expr.X_add_number >= -0x8000 | |
8018 | && imm_expr.X_add_number < 0x8000) | |
8019 | { | |
67c0d1eb | 8020 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 8021 | break; |
252b5132 | 8022 | } |
8fc2e39e | 8023 | used_at = 1; |
67c0d1eb RS |
8024 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
8025 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
8026 | break; |
8027 | ||
8028 | case M_SLTU_I: | |
8029 | if (imm_expr.X_op == O_constant | |
8030 | && imm_expr.X_add_number >= -0x8000 | |
8031 | && imm_expr.X_add_number < 0x8000) | |
8032 | { | |
67c0d1eb | 8033 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 8034 | BFD_RELOC_LO16); |
8fc2e39e | 8035 | break; |
252b5132 | 8036 | } |
8fc2e39e | 8037 | used_at = 1; |
67c0d1eb RS |
8038 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
8039 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
8040 | break; |
8041 | ||
8042 | case M_SNE: | |
8043 | if (sreg == 0) | |
67c0d1eb | 8044 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 8045 | else if (treg == 0) |
67c0d1eb | 8046 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
8047 | else |
8048 | { | |
67c0d1eb RS |
8049 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
8050 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 8051 | } |
8fc2e39e | 8052 | break; |
252b5132 RH |
8053 | |
8054 | case M_SNE_I: | |
8055 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
8056 | { | |
67c0d1eb | 8057 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 8058 | break; |
252b5132 RH |
8059 | } |
8060 | if (sreg == 0) | |
8061 | { | |
8062 | as_warn (_("Instruction %s: result is always true"), | |
8063 | ip->insn_mo->name); | |
67c0d1eb RS |
8064 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
8065 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 8066 | break; |
252b5132 | 8067 | } |
dd3cbb7e NC |
8068 | if (CPU_HAS_SEQ (mips_opts.arch) |
8069 | && -512 <= imm_expr.X_add_number | |
8070 | && imm_expr.X_add_number < 512) | |
8071 | { | |
8072 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 8073 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
8074 | break; |
8075 | } | |
252b5132 RH |
8076 | if (imm_expr.X_op == O_constant |
8077 | && imm_expr.X_add_number >= 0 | |
8078 | && imm_expr.X_add_number < 0x10000) | |
8079 | { | |
67c0d1eb | 8080 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
8081 | } |
8082 | else if (imm_expr.X_op == O_constant | |
8083 | && imm_expr.X_add_number > -0x8000 | |
8084 | && imm_expr.X_add_number < 0) | |
8085 | { | |
8086 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8087 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 8088 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 8089 | } |
dd3cbb7e NC |
8090 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
8091 | { | |
8092 | used_at = 1; | |
8093 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
8094 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
8095 | break; | |
8096 | } | |
252b5132 RH |
8097 | else |
8098 | { | |
67c0d1eb RS |
8099 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
8100 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
8101 | used_at = 1; |
8102 | } | |
67c0d1eb | 8103 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 8104 | break; |
252b5132 RH |
8105 | |
8106 | case M_DSUB_I: | |
8107 | dbl = 1; | |
8108 | case M_SUB_I: | |
8109 | if (imm_expr.X_op == O_constant | |
8110 | && imm_expr.X_add_number > -0x8000 | |
8111 | && imm_expr.X_add_number <= 0x8000) | |
8112 | { | |
8113 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
8114 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
8115 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 8116 | break; |
252b5132 | 8117 | } |
8fc2e39e | 8118 | used_at = 1; |
67c0d1eb RS |
8119 | load_register (AT, &imm_expr, dbl); |
8120 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
8121 | break; |
8122 | ||
8123 | case M_DSUBU_I: | |
8124 | dbl = 1; | |
8125 | case M_SUBU_I: | |
8126 | if (imm_expr.X_op == O_constant | |
8127 | && imm_expr.X_add_number > -0x8000 | |
8128 | && imm_expr.X_add_number <= 0x8000) | |
8129 | { | |
8130 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
8131 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
8132 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 8133 | break; |
252b5132 | 8134 | } |
8fc2e39e | 8135 | used_at = 1; |
67c0d1eb RS |
8136 | load_register (AT, &imm_expr, dbl); |
8137 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
8138 | break; |
8139 | ||
8140 | case M_TEQ_I: | |
8141 | s = "teq"; | |
8142 | goto trap; | |
8143 | case M_TGE_I: | |
8144 | s = "tge"; | |
8145 | goto trap; | |
8146 | case M_TGEU_I: | |
8147 | s = "tgeu"; | |
8148 | goto trap; | |
8149 | case M_TLT_I: | |
8150 | s = "tlt"; | |
8151 | goto trap; | |
8152 | case M_TLTU_I: | |
8153 | s = "tltu"; | |
8154 | goto trap; | |
8155 | case M_TNE_I: | |
8156 | s = "tne"; | |
8157 | trap: | |
8fc2e39e | 8158 | used_at = 1; |
67c0d1eb RS |
8159 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
8160 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
8161 | break; |
8162 | ||
252b5132 | 8163 | case M_TRUNCWS: |
43841e91 | 8164 | case M_TRUNCWD: |
9c2799c2 | 8165 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 8166 | used_at = 1; |
252b5132 RH |
8167 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
8168 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
8169 | ||
8170 | /* | |
8171 | * Is the double cfc1 instruction a bug in the mips assembler; | |
8172 | * or is there a reason for it? | |
8173 | */ | |
7d10b47d | 8174 | start_noreorder (); |
67c0d1eb RS |
8175 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
8176 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
8177 | macro_build (NULL, "nop", ""); | |
252b5132 | 8178 | expr1.X_add_number = 3; |
67c0d1eb | 8179 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 8180 | expr1.X_add_number = 2; |
67c0d1eb RS |
8181 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
8182 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
8183 | macro_build (NULL, "nop", ""); | |
8184 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
8185 | dreg, sreg); | |
8186 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
8187 | macro_build (NULL, "nop", ""); | |
7d10b47d | 8188 | end_noreorder (); |
252b5132 RH |
8189 | break; |
8190 | ||
8191 | case M_ULH: | |
8192 | s = "lb"; | |
8193 | goto ulh; | |
8194 | case M_ULHU: | |
8195 | s = "lbu"; | |
8196 | ulh: | |
8fc2e39e | 8197 | used_at = 1; |
252b5132 | 8198 | if (offset_expr.X_add_number >= 0x7fff) |
f71d0d44 | 8199 | as_bad (_("Operand overflow")); |
90ecf173 | 8200 | if (!target_big_endian) |
f9419b05 | 8201 | ++offset_expr.X_add_number; |
67c0d1eb | 8202 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
90ecf173 | 8203 | if (!target_big_endian) |
f9419b05 | 8204 | --offset_expr.X_add_number; |
252b5132 | 8205 | else |
f9419b05 | 8206 | ++offset_expr.X_add_number; |
67c0d1eb RS |
8207 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8208 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
8209 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8210 | break; |
8211 | ||
8212 | case M_ULD: | |
8213 | s = "ldl"; | |
8214 | s2 = "ldr"; | |
8215 | off = 7; | |
8216 | goto ulw; | |
8217 | case M_ULW: | |
8218 | s = "lwl"; | |
8219 | s2 = "lwr"; | |
8220 | off = 3; | |
8221 | ulw: | |
8222 | if (offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 8223 | as_bad (_("Operand overflow")); |
af22f5b2 CD |
8224 | if (treg != breg) |
8225 | tempreg = treg; | |
8226 | else | |
8fc2e39e TS |
8227 | { |
8228 | used_at = 1; | |
8229 | tempreg = AT; | |
8230 | } | |
90ecf173 | 8231 | if (!target_big_endian) |
252b5132 | 8232 | offset_expr.X_add_number += off; |
67c0d1eb | 8233 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
90ecf173 | 8234 | if (!target_big_endian) |
252b5132 RH |
8235 | offset_expr.X_add_number -= off; |
8236 | else | |
8237 | offset_expr.X_add_number += off; | |
67c0d1eb | 8238 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 | 8239 | |
90ecf173 | 8240 | /* If necessary, move the result in tempreg to the final destination. */ |
af22f5b2 | 8241 | if (treg == tempreg) |
8fc2e39e | 8242 | break; |
af22f5b2 | 8243 | /* Protect second load's delay slot. */ |
017315e4 | 8244 | load_delay_nop (); |
67c0d1eb | 8245 | move_register (treg, tempreg); |
af22f5b2 | 8246 | break; |
252b5132 RH |
8247 | |
8248 | case M_ULD_A: | |
8249 | s = "ldl"; | |
8250 | s2 = "ldr"; | |
8251 | off = 7; | |
8252 | goto ulwa; | |
8253 | case M_ULW_A: | |
8254 | s = "lwl"; | |
8255 | s2 = "lwr"; | |
8256 | off = 3; | |
8257 | ulwa: | |
d6bc6245 | 8258 | used_at = 1; |
67c0d1eb | 8259 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8260 | if (breg != 0) |
67c0d1eb | 8261 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
90ecf173 | 8262 | if (!target_big_endian) |
252b5132 RH |
8263 | expr1.X_add_number = off; |
8264 | else | |
8265 | expr1.X_add_number = 0; | |
67c0d1eb | 8266 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
90ecf173 | 8267 | if (!target_big_endian) |
252b5132 RH |
8268 | expr1.X_add_number = 0; |
8269 | else | |
8270 | expr1.X_add_number = off; | |
67c0d1eb | 8271 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8272 | break; |
8273 | ||
8274 | case M_ULH_A: | |
8275 | case M_ULHU_A: | |
d6bc6245 | 8276 | used_at = 1; |
67c0d1eb | 8277 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8278 | if (breg != 0) |
67c0d1eb | 8279 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8280 | if (target_big_endian) |
8281 | expr1.X_add_number = 0; | |
67c0d1eb | 8282 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 8283 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8284 | if (target_big_endian) |
8285 | expr1.X_add_number = 1; | |
8286 | else | |
8287 | expr1.X_add_number = 0; | |
67c0d1eb RS |
8288 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
8289 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
8290 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8291 | break; |
8292 | ||
8293 | case M_USH: | |
8fc2e39e | 8294 | used_at = 1; |
252b5132 | 8295 | if (offset_expr.X_add_number >= 0x7fff) |
f71d0d44 | 8296 | as_bad (_("Operand overflow")); |
252b5132 | 8297 | if (target_big_endian) |
f9419b05 | 8298 | ++offset_expr.X_add_number; |
67c0d1eb RS |
8299 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8300 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 8301 | if (target_big_endian) |
f9419b05 | 8302 | --offset_expr.X_add_number; |
252b5132 | 8303 | else |
f9419b05 | 8304 | ++offset_expr.X_add_number; |
67c0d1eb | 8305 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
8306 | break; |
8307 | ||
8308 | case M_USD: | |
8309 | s = "sdl"; | |
8310 | s2 = "sdr"; | |
8311 | off = 7; | |
8312 | goto usw; | |
8313 | case M_USW: | |
8314 | s = "swl"; | |
8315 | s2 = "swr"; | |
8316 | off = 3; | |
8317 | usw: | |
8318 | if (offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 8319 | as_bad (_("Operand overflow")); |
90ecf173 | 8320 | if (!target_big_endian) |
252b5132 | 8321 | offset_expr.X_add_number += off; |
67c0d1eb | 8322 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
90ecf173 | 8323 | if (!target_big_endian) |
252b5132 RH |
8324 | offset_expr.X_add_number -= off; |
8325 | else | |
8326 | offset_expr.X_add_number += off; | |
67c0d1eb | 8327 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 8328 | break; |
252b5132 RH |
8329 | |
8330 | case M_USD_A: | |
8331 | s = "sdl"; | |
8332 | s2 = "sdr"; | |
8333 | off = 7; | |
8334 | goto uswa; | |
8335 | case M_USW_A: | |
8336 | s = "swl"; | |
8337 | s2 = "swr"; | |
8338 | off = 3; | |
8339 | uswa: | |
d6bc6245 | 8340 | used_at = 1; |
67c0d1eb | 8341 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8342 | if (breg != 0) |
67c0d1eb | 8343 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
90ecf173 | 8344 | if (!target_big_endian) |
252b5132 RH |
8345 | expr1.X_add_number = off; |
8346 | else | |
8347 | expr1.X_add_number = 0; | |
67c0d1eb | 8348 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
90ecf173 | 8349 | if (!target_big_endian) |
252b5132 RH |
8350 | expr1.X_add_number = 0; |
8351 | else | |
8352 | expr1.X_add_number = off; | |
67c0d1eb | 8353 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8354 | break; |
8355 | ||
8356 | case M_USH_A: | |
d6bc6245 | 8357 | used_at = 1; |
67c0d1eb | 8358 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8359 | if (breg != 0) |
67c0d1eb | 8360 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
90ecf173 | 8361 | if (!target_big_endian) |
252b5132 | 8362 | expr1.X_add_number = 0; |
67c0d1eb RS |
8363 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
8364 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
90ecf173 | 8365 | if (!target_big_endian) |
252b5132 RH |
8366 | expr1.X_add_number = 1; |
8367 | else | |
8368 | expr1.X_add_number = 0; | |
67c0d1eb | 8369 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
90ecf173 | 8370 | if (!target_big_endian) |
252b5132 RH |
8371 | expr1.X_add_number = 0; |
8372 | else | |
8373 | expr1.X_add_number = 1; | |
67c0d1eb RS |
8374 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
8375 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
8376 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8377 | break; |
8378 | ||
8379 | default: | |
8380 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 8381 | are added dynamically. */ |
252b5132 RH |
8382 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
8383 | break; | |
8384 | } | |
741fe287 | 8385 | if (!mips_opts.at && used_at) |
8fc2e39e | 8386 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
8387 | } |
8388 | ||
8389 | /* Implement macros in mips16 mode. */ | |
8390 | ||
8391 | static void | |
17a2f251 | 8392 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
8393 | { |
8394 | int mask; | |
8395 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
8396 | expressionS expr1; |
8397 | int dbl; | |
8398 | const char *s, *s2, *s3; | |
8399 | ||
8400 | mask = ip->insn_mo->mask; | |
8401 | ||
bf12938e RS |
8402 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
8403 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
8404 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 8405 | |
252b5132 RH |
8406 | expr1.X_op = O_constant; |
8407 | expr1.X_op_symbol = NULL; | |
8408 | expr1.X_add_symbol = NULL; | |
8409 | expr1.X_add_number = 1; | |
8410 | ||
8411 | dbl = 0; | |
8412 | ||
8413 | switch (mask) | |
8414 | { | |
8415 | default: | |
8416 | internalError (); | |
8417 | ||
8418 | case M_DDIV_3: | |
8419 | dbl = 1; | |
8420 | case M_DIV_3: | |
8421 | s = "mflo"; | |
8422 | goto do_div3; | |
8423 | case M_DREM_3: | |
8424 | dbl = 1; | |
8425 | case M_REM_3: | |
8426 | s = "mfhi"; | |
8427 | do_div3: | |
7d10b47d | 8428 | start_noreorder (); |
67c0d1eb | 8429 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 8430 | expr1.X_add_number = 2; |
67c0d1eb RS |
8431 | macro_build (&expr1, "bnez", "x,p", yreg); |
8432 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 8433 | |
252b5132 RH |
8434 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
8435 | since that causes an overflow. We should do that as well, | |
8436 | but I don't see how to do the comparisons without a temporary | |
8437 | register. */ | |
7d10b47d | 8438 | end_noreorder (); |
67c0d1eb | 8439 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
8440 | break; |
8441 | ||
8442 | case M_DIVU_3: | |
8443 | s = "divu"; | |
8444 | s2 = "mflo"; | |
8445 | goto do_divu3; | |
8446 | case M_REMU_3: | |
8447 | s = "divu"; | |
8448 | s2 = "mfhi"; | |
8449 | goto do_divu3; | |
8450 | case M_DDIVU_3: | |
8451 | s = "ddivu"; | |
8452 | s2 = "mflo"; | |
8453 | goto do_divu3; | |
8454 | case M_DREMU_3: | |
8455 | s = "ddivu"; | |
8456 | s2 = "mfhi"; | |
8457 | do_divu3: | |
7d10b47d | 8458 | start_noreorder (); |
67c0d1eb | 8459 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 8460 | expr1.X_add_number = 2; |
67c0d1eb RS |
8461 | macro_build (&expr1, "bnez", "x,p", yreg); |
8462 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 8463 | end_noreorder (); |
67c0d1eb | 8464 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
8465 | break; |
8466 | ||
8467 | case M_DMUL: | |
8468 | dbl = 1; | |
8469 | case M_MUL: | |
67c0d1eb RS |
8470 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
8471 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 8472 | break; |
252b5132 RH |
8473 | |
8474 | case M_DSUBU_I: | |
8475 | dbl = 1; | |
8476 | goto do_subu; | |
8477 | case M_SUBU_I: | |
8478 | do_subu: | |
8479 | if (imm_expr.X_op != O_constant) | |
8480 | as_bad (_("Unsupported large constant")); | |
8481 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8482 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
8483 | break; |
8484 | ||
8485 | case M_SUBU_I_2: | |
8486 | if (imm_expr.X_op != O_constant) | |
8487 | as_bad (_("Unsupported large constant")); | |
8488 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8489 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
8490 | break; |
8491 | ||
8492 | case M_DSUBU_I_2: | |
8493 | if (imm_expr.X_op != O_constant) | |
8494 | as_bad (_("Unsupported large constant")); | |
8495 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8496 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
8497 | break; |
8498 | ||
8499 | case M_BEQ: | |
8500 | s = "cmp"; | |
8501 | s2 = "bteqz"; | |
8502 | goto do_branch; | |
8503 | case M_BNE: | |
8504 | s = "cmp"; | |
8505 | s2 = "btnez"; | |
8506 | goto do_branch; | |
8507 | case M_BLT: | |
8508 | s = "slt"; | |
8509 | s2 = "btnez"; | |
8510 | goto do_branch; | |
8511 | case M_BLTU: | |
8512 | s = "sltu"; | |
8513 | s2 = "btnez"; | |
8514 | goto do_branch; | |
8515 | case M_BLE: | |
8516 | s = "slt"; | |
8517 | s2 = "bteqz"; | |
8518 | goto do_reverse_branch; | |
8519 | case M_BLEU: | |
8520 | s = "sltu"; | |
8521 | s2 = "bteqz"; | |
8522 | goto do_reverse_branch; | |
8523 | case M_BGE: | |
8524 | s = "slt"; | |
8525 | s2 = "bteqz"; | |
8526 | goto do_branch; | |
8527 | case M_BGEU: | |
8528 | s = "sltu"; | |
8529 | s2 = "bteqz"; | |
8530 | goto do_branch; | |
8531 | case M_BGT: | |
8532 | s = "slt"; | |
8533 | s2 = "btnez"; | |
8534 | goto do_reverse_branch; | |
8535 | case M_BGTU: | |
8536 | s = "sltu"; | |
8537 | s2 = "btnez"; | |
8538 | ||
8539 | do_reverse_branch: | |
8540 | tmp = xreg; | |
8541 | xreg = yreg; | |
8542 | yreg = tmp; | |
8543 | ||
8544 | do_branch: | |
67c0d1eb RS |
8545 | macro_build (NULL, s, "x,y", xreg, yreg); |
8546 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8547 | break; |
8548 | ||
8549 | case M_BEQ_I: | |
8550 | s = "cmpi"; | |
8551 | s2 = "bteqz"; | |
8552 | s3 = "x,U"; | |
8553 | goto do_branch_i; | |
8554 | case M_BNE_I: | |
8555 | s = "cmpi"; | |
8556 | s2 = "btnez"; | |
8557 | s3 = "x,U"; | |
8558 | goto do_branch_i; | |
8559 | case M_BLT_I: | |
8560 | s = "slti"; | |
8561 | s2 = "btnez"; | |
8562 | s3 = "x,8"; | |
8563 | goto do_branch_i; | |
8564 | case M_BLTU_I: | |
8565 | s = "sltiu"; | |
8566 | s2 = "btnez"; | |
8567 | s3 = "x,8"; | |
8568 | goto do_branch_i; | |
8569 | case M_BLE_I: | |
8570 | s = "slti"; | |
8571 | s2 = "btnez"; | |
8572 | s3 = "x,8"; | |
8573 | goto do_addone_branch_i; | |
8574 | case M_BLEU_I: | |
8575 | s = "sltiu"; | |
8576 | s2 = "btnez"; | |
8577 | s3 = "x,8"; | |
8578 | goto do_addone_branch_i; | |
8579 | case M_BGE_I: | |
8580 | s = "slti"; | |
8581 | s2 = "bteqz"; | |
8582 | s3 = "x,8"; | |
8583 | goto do_branch_i; | |
8584 | case M_BGEU_I: | |
8585 | s = "sltiu"; | |
8586 | s2 = "bteqz"; | |
8587 | s3 = "x,8"; | |
8588 | goto do_branch_i; | |
8589 | case M_BGT_I: | |
8590 | s = "slti"; | |
8591 | s2 = "bteqz"; | |
8592 | s3 = "x,8"; | |
8593 | goto do_addone_branch_i; | |
8594 | case M_BGTU_I: | |
8595 | s = "sltiu"; | |
8596 | s2 = "bteqz"; | |
8597 | s3 = "x,8"; | |
8598 | ||
8599 | do_addone_branch_i: | |
8600 | if (imm_expr.X_op != O_constant) | |
8601 | as_bad (_("Unsupported large constant")); | |
8602 | ++imm_expr.X_add_number; | |
8603 | ||
8604 | do_branch_i: | |
67c0d1eb RS |
8605 | macro_build (&imm_expr, s, s3, xreg); |
8606 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8607 | break; |
8608 | ||
8609 | case M_ABS: | |
8610 | expr1.X_add_number = 0; | |
67c0d1eb | 8611 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 8612 | if (xreg != yreg) |
67c0d1eb | 8613 | move_register (xreg, yreg); |
252b5132 | 8614 | expr1.X_add_number = 2; |
67c0d1eb RS |
8615 | macro_build (&expr1, "bteqz", "p"); |
8616 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
8617 | } |
8618 | } | |
8619 | ||
8620 | /* For consistency checking, verify that all bits are specified either | |
8621 | by the match/mask part of the instruction definition, or by the | |
8622 | operand list. */ | |
8623 | static int | |
17a2f251 | 8624 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
8625 | { |
8626 | const char *p = opc->args; | |
8627 | char c; | |
8628 | unsigned long used_bits = opc->mask; | |
8629 | ||
8630 | if ((used_bits & opc->match) != opc->match) | |
8631 | { | |
8632 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8633 | opc->name, opc->args); | |
8634 | return 0; | |
8635 | } | |
8636 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8637 | while (*p) | |
8638 | switch (c = *p++) | |
8639 | { | |
8640 | case ',': break; | |
8641 | case '(': break; | |
8642 | case ')': break; | |
af7ee8bf CD |
8643 | case '+': |
8644 | switch (c = *p++) | |
8645 | { | |
9bcd4f99 TS |
8646 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
8647 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
8648 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
8649 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
8650 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8651 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8652 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8653 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8654 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
8655 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8656 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8657 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8658 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8659 | case 'I': break; | |
ef2e4d86 CF |
8660 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
8661 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
8662 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
8663 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
8664 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
8665 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
8666 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 8667 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
8668 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
8669 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
8670 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
8671 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
8672 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
8673 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
8674 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
bb35fb24 | 8675 | |
af7ee8bf CD |
8676 | default: |
8677 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8678 | c, opc->name, opc->args); | |
8679 | return 0; | |
8680 | } | |
8681 | break; | |
252b5132 RH |
8682 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8683 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8684 | case 'A': break; | |
4372b673 | 8685 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8686 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8687 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8688 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8689 | case 'F': break; | |
8690 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8691 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8692 | case 'I': break; |
e972090a | 8693 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8694 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8695 | case 'L': break; |
8696 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8697 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8698 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8699 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8700 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8701 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8702 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8703 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8704 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8705 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8706 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8707 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8708 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8709 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8710 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8711 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8712 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8713 | case 'f': break; | |
8714 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8715 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8716 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8717 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8718 | case 'l': break; | |
8719 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8720 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8721 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8722 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8723 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8724 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8725 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8726 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8727 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8728 | case 'x': break; | |
8729 | case 'z': break; | |
8730 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8731 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8732 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8733 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8734 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8735 | case '[': break; | |
8736 | case ']': break; | |
620edafd | 8737 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 8738 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
8739 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
8740 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
8741 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
8742 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8743 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
8744 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
8745 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
8746 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
8747 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
8748 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
8749 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
8750 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
8751 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
8752 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
8753 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
8754 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
252b5132 RH |
8755 | default: |
8756 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8757 | c, opc->name, opc->args); | |
8758 | return 0; | |
8759 | } | |
8760 | #undef USE_BITS | |
8761 | if (used_bits != 0xffffffff) | |
8762 | { | |
8763 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8764 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8765 | return 0; | |
8766 | } | |
8767 | return 1; | |
8768 | } | |
8769 | ||
9bcd4f99 TS |
8770 | /* UDI immediates. */ |
8771 | struct mips_immed { | |
8772 | char type; | |
8773 | unsigned int shift; | |
8774 | unsigned long mask; | |
8775 | const char * desc; | |
8776 | }; | |
8777 | ||
8778 | static const struct mips_immed mips_immed[] = { | |
8779 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
8780 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
8781 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
8782 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
8783 | { 0,0,0,0 } | |
8784 | }; | |
8785 | ||
7455baf8 TS |
8786 | /* Check whether an odd floating-point register is allowed. */ |
8787 | static int | |
8788 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
8789 | { | |
8790 | const char *s = insn->name; | |
8791 | ||
8792 | if (insn->pinfo == INSN_MACRO) | |
8793 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
8794 | return 1; | |
8795 | ||
8796 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
8797 | { | |
8798 | /* Allow odd registers for single-precision ops. */ | |
8799 | switch (insn->pinfo & (FP_S | FP_D)) | |
8800 | { | |
8801 | case FP_S: | |
8802 | case 0: | |
8803 | return 1; /* both single precision - ok */ | |
8804 | case FP_D: | |
8805 | return 0; /* both double precision - fail */ | |
8806 | default: | |
8807 | break; | |
8808 | } | |
8809 | ||
8810 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
8811 | s = strchr (insn->name, '.'); | |
8812 | if (argnum == 2) | |
8813 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
8814 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
8815 | } | |
8816 | ||
8817 | /* Single-precision coprocessor loads and moves are OK too. */ | |
8818 | if ((insn->pinfo & FP_S) | |
8819 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
8820 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
8821 | return 1; | |
8822 | ||
8823 | return 0; | |
8824 | } | |
8825 | ||
252b5132 RH |
8826 | /* This routine assembles an instruction into its binary format. As a |
8827 | side effect, it sets one of the global variables imm_reloc or | |
8828 | offset_reloc to the type of relocation to do if one of the operands | |
8829 | is an address expression. */ | |
8830 | ||
8831 | static void | |
17a2f251 | 8832 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8833 | { |
8834 | char *s; | |
8835 | const char *args; | |
43841e91 | 8836 | char c = 0; |
252b5132 RH |
8837 | struct mips_opcode *insn; |
8838 | char *argsStart; | |
8839 | unsigned int regno; | |
34224acf | 8840 | unsigned int lastregno; |
af7ee8bf | 8841 | unsigned int lastpos = 0; |
071742cf | 8842 | unsigned int limlo, limhi; |
252b5132 RH |
8843 | char *s_reset; |
8844 | char save_c = 0; | |
74cd071d | 8845 | offsetT min_range, max_range; |
707bfff6 TS |
8846 | int argnum; |
8847 | unsigned int rtype; | |
252b5132 RH |
8848 | |
8849 | insn_error = NULL; | |
8850 | ||
8851 | /* If the instruction contains a '.', we first try to match an instruction | |
8852 | including the '.'. Then we try again without the '.'. */ | |
8853 | insn = NULL; | |
3882b010 | 8854 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8855 | continue; |
8856 | ||
8857 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8858 | the call to hash_find. Save the character we replaced just in case we | |
8859 | have to re-parse the instruction. */ | |
3882b010 | 8860 | if (ISSPACE (*s)) |
252b5132 RH |
8861 | { |
8862 | save_c = *s; | |
8863 | *s++ = '\0'; | |
8864 | } | |
bdaaa2e1 | 8865 | |
252b5132 RH |
8866 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8867 | ||
8868 | /* If we didn't find the instruction in the opcode table, try again, but | |
8869 | this time with just the instruction up to, but not including the | |
8870 | first '.'. */ | |
8871 | if (insn == NULL) | |
8872 | { | |
bdaaa2e1 | 8873 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8874 | if (save_c) |
8875 | *(--s) = save_c; | |
8876 | ||
8877 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8878 | for (s = str; |
8879 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8880 | ++s) | |
252b5132 RH |
8881 | continue; |
8882 | ||
8883 | /* If we did not find a '.', then we can quit now. */ | |
8884 | if (*s != '.') | |
8885 | { | |
f71d0d44 | 8886 | insn_error = _("Unrecognized opcode"); |
252b5132 RH |
8887 | return; |
8888 | } | |
8889 | ||
8890 | /* Lookup the instruction in the hash table. */ | |
8891 | *s++ = '\0'; | |
8892 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8893 | { | |
f71d0d44 | 8894 | insn_error = _("Unrecognized opcode"); |
252b5132 RH |
8895 | return; |
8896 | } | |
252b5132 RH |
8897 | } |
8898 | ||
8899 | argsStart = s; | |
8900 | for (;;) | |
8901 | { | |
b34976b6 | 8902 | bfd_boolean ok; |
252b5132 | 8903 | |
9c2799c2 | 8904 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 8905 | |
f79e2745 | 8906 | ok = is_opcode_valid (insn); |
252b5132 RH |
8907 | if (! ok) |
8908 | { | |
8909 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8910 | && strcmp (insn->name, insn[1].name) == 0) | |
8911 | { | |
8912 | ++insn; | |
8913 | continue; | |
8914 | } | |
252b5132 | 8915 | else |
beae10d5 | 8916 | { |
268f6bed L |
8917 | if (!insn_error) |
8918 | { | |
8919 | static char buf[100]; | |
fef14a42 TS |
8920 | sprintf (buf, |
8921 | _("opcode not supported on this processor: %s (%s)"), | |
8922 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8923 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8924 | insn_error = buf; |
8925 | } | |
8926 | if (save_c) | |
8927 | *(--s) = save_c; | |
2bd7f1f3 | 8928 | return; |
252b5132 | 8929 | } |
252b5132 RH |
8930 | } |
8931 | ||
1e915849 | 8932 | create_insn (ip, insn); |
268f6bed | 8933 | insn_error = NULL; |
707bfff6 | 8934 | argnum = 1; |
24864476 | 8935 | lastregno = 0xffffffff; |
252b5132 RH |
8936 | for (args = insn->args;; ++args) |
8937 | { | |
deec1734 CD |
8938 | int is_mdmx; |
8939 | ||
ad8d3bb3 | 8940 | s += strspn (s, " \t"); |
deec1734 | 8941 | is_mdmx = 0; |
252b5132 RH |
8942 | switch (*args) |
8943 | { | |
8944 | case '\0': /* end of args */ | |
8945 | if (*s == '\0') | |
8946 | return; | |
8947 | break; | |
8948 | ||
90ecf173 | 8949 | case '2': /* DSP 2-bit unsigned immediate in bit 11. */ |
8b082fb1 TS |
8950 | my_getExpression (&imm_expr, s); |
8951 | check_absolute_expr (ip, &imm_expr); | |
8952 | if ((unsigned long) imm_expr.X_add_number != 1 | |
8953 | && (unsigned long) imm_expr.X_add_number != 3) | |
8954 | { | |
8955 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
8956 | (unsigned long) imm_expr.X_add_number); | |
8957 | } | |
8958 | INSERT_OPERAND (BP, *ip, imm_expr.X_add_number); | |
8959 | imm_expr.X_op = O_absent; | |
8960 | s = expr_end; | |
8961 | continue; | |
8962 | ||
90ecf173 | 8963 | case '3': /* DSP 3-bit unsigned immediate in bit 21. */ |
74cd071d CF |
8964 | my_getExpression (&imm_expr, s); |
8965 | check_absolute_expr (ip, &imm_expr); | |
8966 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
8967 | { | |
a9e24354 TS |
8968 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8969 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8970 | } |
a9e24354 | 8971 | INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number); |
74cd071d CF |
8972 | imm_expr.X_op = O_absent; |
8973 | s = expr_end; | |
8974 | continue; | |
8975 | ||
90ecf173 | 8976 | case '4': /* DSP 4-bit unsigned immediate in bit 21. */ |
74cd071d CF |
8977 | my_getExpression (&imm_expr, s); |
8978 | check_absolute_expr (ip, &imm_expr); | |
8979 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
8980 | { | |
a9e24354 TS |
8981 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8982 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8983 | } |
a9e24354 | 8984 | INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number); |
74cd071d CF |
8985 | imm_expr.X_op = O_absent; |
8986 | s = expr_end; | |
8987 | continue; | |
8988 | ||
90ecf173 | 8989 | case '5': /* DSP 8-bit unsigned immediate in bit 16. */ |
74cd071d CF |
8990 | my_getExpression (&imm_expr, s); |
8991 | check_absolute_expr (ip, &imm_expr); | |
8992 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
8993 | { | |
a9e24354 TS |
8994 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8995 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8996 | } |
a9e24354 | 8997 | INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number); |
74cd071d CF |
8998 | imm_expr.X_op = O_absent; |
8999 | s = expr_end; | |
9000 | continue; | |
9001 | ||
90ecf173 | 9002 | case '6': /* DSP 5-bit unsigned immediate in bit 21. */ |
74cd071d CF |
9003 | my_getExpression (&imm_expr, s); |
9004 | check_absolute_expr (ip, &imm_expr); | |
9005 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
9006 | { | |
a9e24354 TS |
9007 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
9008 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 9009 | } |
a9e24354 | 9010 | INSERT_OPERAND (RS, *ip, imm_expr.X_add_number); |
74cd071d CF |
9011 | imm_expr.X_op = O_absent; |
9012 | s = expr_end; | |
9013 | continue; | |
9014 | ||
90ecf173 | 9015 | case '7': /* Four DSP accumulators in bits 11,12. */ |
74cd071d CF |
9016 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
9017 | s[3] >= '0' && s[3] <= '3') | |
9018 | { | |
9019 | regno = s[3] - '0'; | |
9020 | s += 4; | |
a9e24354 | 9021 | INSERT_OPERAND (DSPACC, *ip, regno); |
74cd071d CF |
9022 | continue; |
9023 | } | |
9024 | else | |
9025 | as_bad (_("Invalid dsp acc register")); | |
9026 | break; | |
9027 | ||
90ecf173 | 9028 | case '8': /* DSP 6-bit unsigned immediate in bit 11. */ |
74cd071d CF |
9029 | my_getExpression (&imm_expr, s); |
9030 | check_absolute_expr (ip, &imm_expr); | |
9031 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
9032 | { | |
a9e24354 TS |
9033 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
9034 | OP_MASK_WRDSP, | |
9035 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 9036 | } |
a9e24354 | 9037 | INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
9038 | imm_expr.X_op = O_absent; |
9039 | s = expr_end; | |
9040 | continue; | |
9041 | ||
90ecf173 | 9042 | case '9': /* Four DSP accumulators in bits 21,22. */ |
74cd071d CF |
9043 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
9044 | s[3] >= '0' && s[3] <= '3') | |
9045 | { | |
9046 | regno = s[3] - '0'; | |
9047 | s += 4; | |
a9e24354 | 9048 | INSERT_OPERAND (DSPACC_S, *ip, regno); |
74cd071d CF |
9049 | continue; |
9050 | } | |
9051 | else | |
9052 | as_bad (_("Invalid dsp acc register")); | |
9053 | break; | |
9054 | ||
90ecf173 | 9055 | case '0': /* DSP 6-bit signed immediate in bit 20. */ |
74cd071d CF |
9056 | my_getExpression (&imm_expr, s); |
9057 | check_absolute_expr (ip, &imm_expr); | |
9058 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
9059 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
9060 | if (imm_expr.X_add_number < min_range || | |
9061 | imm_expr.X_add_number > max_range) | |
9062 | { | |
a9e24354 TS |
9063 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
9064 | (long) min_range, (long) max_range, | |
9065 | (long) imm_expr.X_add_number); | |
74cd071d | 9066 | } |
a9e24354 | 9067 | INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number); |
74cd071d CF |
9068 | imm_expr.X_op = O_absent; |
9069 | s = expr_end; | |
9070 | continue; | |
9071 | ||
90ecf173 | 9072 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
74cd071d CF |
9073 | my_getExpression (&imm_expr, s); |
9074 | check_absolute_expr (ip, &imm_expr); | |
9075 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
9076 | { | |
a9e24354 TS |
9077 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
9078 | OP_MASK_RDDSP, | |
9079 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 9080 | } |
a9e24354 | 9081 | INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
9082 | imm_expr.X_op = O_absent; |
9083 | s = expr_end; | |
9084 | continue; | |
9085 | ||
90ecf173 | 9086 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
74cd071d CF |
9087 | my_getExpression (&imm_expr, s); |
9088 | check_absolute_expr (ip, &imm_expr); | |
9089 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
9090 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
9091 | if (imm_expr.X_add_number < min_range || | |
9092 | imm_expr.X_add_number > max_range) | |
9093 | { | |
a9e24354 TS |
9094 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
9095 | (long) min_range, (long) max_range, | |
9096 | (long) imm_expr.X_add_number); | |
74cd071d | 9097 | } |
a9e24354 | 9098 | INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
9099 | imm_expr.X_op = O_absent; |
9100 | s = expr_end; | |
9101 | continue; | |
9102 | ||
90ecf173 | 9103 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
74cd071d CF |
9104 | my_getExpression (&imm_expr, s); |
9105 | check_absolute_expr (ip, &imm_expr); | |
9106 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
9107 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
9108 | if (imm_expr.X_add_number < min_range || | |
9109 | imm_expr.X_add_number > max_range) | |
9110 | { | |
a9e24354 TS |
9111 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
9112 | (long) min_range, (long) max_range, | |
9113 | (long) imm_expr.X_add_number); | |
74cd071d | 9114 | } |
a9e24354 | 9115 | INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number); |
74cd071d CF |
9116 | imm_expr.X_op = O_absent; |
9117 | s = expr_end; | |
9118 | continue; | |
9119 | ||
a9e24354 | 9120 | case '!': /* MT usermode flag bit. */ |
ef2e4d86 CF |
9121 | my_getExpression (&imm_expr, s); |
9122 | check_absolute_expr (ip, &imm_expr); | |
9123 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
9124 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
9125 | (unsigned long) imm_expr.X_add_number); | |
9126 | INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
9127 | imm_expr.X_op = O_absent; |
9128 | s = expr_end; | |
9129 | continue; | |
9130 | ||
a9e24354 | 9131 | case '$': /* MT load high flag bit. */ |
ef2e4d86 CF |
9132 | my_getExpression (&imm_expr, s); |
9133 | check_absolute_expr (ip, &imm_expr); | |
9134 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
9135 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
9136 | (unsigned long) imm_expr.X_add_number); | |
9137 | INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
9138 | imm_expr.X_op = O_absent; |
9139 | s = expr_end; | |
9140 | continue; | |
9141 | ||
90ecf173 | 9142 | case '*': /* Four DSP accumulators in bits 18,19. */ |
ef2e4d86 CF |
9143 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
9144 | s[3] >= '0' && s[3] <= '3') | |
9145 | { | |
9146 | regno = s[3] - '0'; | |
9147 | s += 4; | |
a9e24354 | 9148 | INSERT_OPERAND (MTACC_T, *ip, regno); |
ef2e4d86 CF |
9149 | continue; |
9150 | } | |
9151 | else | |
9152 | as_bad (_("Invalid dsp/smartmips acc register")); | |
9153 | break; | |
9154 | ||
90ecf173 | 9155 | case '&': /* Four DSP accumulators in bits 13,14. */ |
ef2e4d86 CF |
9156 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
9157 | s[3] >= '0' && s[3] <= '3') | |
9158 | { | |
9159 | regno = s[3] - '0'; | |
9160 | s += 4; | |
a9e24354 | 9161 | INSERT_OPERAND (MTACC_D, *ip, regno); |
ef2e4d86 CF |
9162 | continue; |
9163 | } | |
9164 | else | |
9165 | as_bad (_("Invalid dsp/smartmips acc register")); | |
9166 | break; | |
9167 | ||
252b5132 | 9168 | case ',': |
a339155f | 9169 | ++argnum; |
252b5132 RH |
9170 | if (*s++ == *args) |
9171 | continue; | |
9172 | s--; | |
9173 | switch (*++args) | |
9174 | { | |
9175 | case 'r': | |
9176 | case 'v': | |
bf12938e | 9177 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9178 | continue; |
9179 | ||
9180 | case 'w': | |
bf12938e | 9181 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
9182 | continue; |
9183 | ||
252b5132 | 9184 | case 'W': |
bf12938e | 9185 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9186 | continue; |
9187 | ||
9188 | case 'V': | |
bf12938e | 9189 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9190 | continue; |
9191 | } | |
9192 | break; | |
9193 | ||
9194 | case '(': | |
9195 | /* Handle optional base register. | |
9196 | Either the base register is omitted or | |
bdaaa2e1 | 9197 | we must have a left paren. */ |
252b5132 RH |
9198 | /* This is dependent on the next operand specifier |
9199 | is a base register specification. */ | |
f9bbfb18 | 9200 | gas_assert (args[1] == 'b'); |
252b5132 RH |
9201 | if (*s == '\0') |
9202 | return; | |
9203 | ||
90ecf173 | 9204 | case ')': /* These must match exactly. */ |
60b63b72 RS |
9205 | case '[': |
9206 | case ']': | |
252b5132 RH |
9207 | if (*s++ == *args) |
9208 | continue; | |
9209 | break; | |
9210 | ||
af7ee8bf CD |
9211 | case '+': /* Opcode extension character. */ |
9212 | switch (*++args) | |
9213 | { | |
9bcd4f99 TS |
9214 | case '1': /* UDI immediates. */ |
9215 | case '2': | |
9216 | case '3': | |
9217 | case '4': | |
9218 | { | |
9219 | const struct mips_immed *imm = mips_immed; | |
9220 | ||
9221 | while (imm->type && imm->type != *args) | |
9222 | ++imm; | |
9223 | if (! imm->type) | |
9224 | internalError (); | |
9225 | my_getExpression (&imm_expr, s); | |
9226 | check_absolute_expr (ip, &imm_expr); | |
9227 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
9228 | { | |
9229 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
9230 | imm->desc ? imm->desc : ip->insn_mo->name, | |
9231 | (unsigned long) imm_expr.X_add_number, | |
9232 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 9233 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
9234 | } |
9235 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
9236 | << imm->shift); | |
9237 | imm_expr.X_op = O_absent; | |
9238 | s = expr_end; | |
9239 | } | |
9240 | continue; | |
90ecf173 | 9241 | |
071742cf CD |
9242 | case 'A': /* ins/ext position, becomes LSB. */ |
9243 | limlo = 0; | |
9244 | limhi = 31; | |
5f74bc13 CD |
9245 | goto do_lsb; |
9246 | case 'E': | |
9247 | limlo = 32; | |
9248 | limhi = 63; | |
9249 | goto do_lsb; | |
90ecf173 | 9250 | do_lsb: |
071742cf CD |
9251 | my_getExpression (&imm_expr, s); |
9252 | check_absolute_expr (ip, &imm_expr); | |
9253 | if ((unsigned long) imm_expr.X_add_number < limlo | |
9254 | || (unsigned long) imm_expr.X_add_number > limhi) | |
9255 | { | |
9256 | as_bad (_("Improper position (%lu)"), | |
9257 | (unsigned long) imm_expr.X_add_number); | |
9258 | imm_expr.X_add_number = limlo; | |
9259 | } | |
9260 | lastpos = imm_expr.X_add_number; | |
bf12938e | 9261 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
9262 | imm_expr.X_op = O_absent; |
9263 | s = expr_end; | |
9264 | continue; | |
9265 | ||
9266 | case 'B': /* ins size, becomes MSB. */ | |
9267 | limlo = 1; | |
9268 | limhi = 32; | |
5f74bc13 CD |
9269 | goto do_msb; |
9270 | case 'F': | |
9271 | limlo = 33; | |
9272 | limhi = 64; | |
9273 | goto do_msb; | |
90ecf173 | 9274 | do_msb: |
071742cf CD |
9275 | my_getExpression (&imm_expr, s); |
9276 | check_absolute_expr (ip, &imm_expr); | |
9277 | /* Check for negative input so that small negative numbers | |
9278 | will not succeed incorrectly. The checks against | |
9279 | (pos+size) transitively check "size" itself, | |
9280 | assuming that "pos" is reasonable. */ | |
9281 | if ((long) imm_expr.X_add_number < 0 | |
9282 | || ((unsigned long) imm_expr.X_add_number | |
9283 | + lastpos) < limlo | |
9284 | || ((unsigned long) imm_expr.X_add_number | |
9285 | + lastpos) > limhi) | |
9286 | { | |
9287 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
9288 | (unsigned long) imm_expr.X_add_number, | |
9289 | (unsigned long) lastpos); | |
9290 | imm_expr.X_add_number = limlo - lastpos; | |
9291 | } | |
bf12938e RS |
9292 | INSERT_OPERAND (INSMSB, *ip, |
9293 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
9294 | imm_expr.X_op = O_absent; |
9295 | s = expr_end; | |
9296 | continue; | |
9297 | ||
9298 | case 'C': /* ext size, becomes MSBD. */ | |
9299 | limlo = 1; | |
9300 | limhi = 32; | |
5f74bc13 CD |
9301 | goto do_msbd; |
9302 | case 'G': | |
9303 | limlo = 33; | |
9304 | limhi = 64; | |
9305 | goto do_msbd; | |
9306 | case 'H': | |
9307 | limlo = 33; | |
9308 | limhi = 64; | |
9309 | goto do_msbd; | |
90ecf173 | 9310 | do_msbd: |
071742cf CD |
9311 | my_getExpression (&imm_expr, s); |
9312 | check_absolute_expr (ip, &imm_expr); | |
9313 | /* Check for negative input so that small negative numbers | |
9314 | will not succeed incorrectly. The checks against | |
9315 | (pos+size) transitively check "size" itself, | |
9316 | assuming that "pos" is reasonable. */ | |
9317 | if ((long) imm_expr.X_add_number < 0 | |
9318 | || ((unsigned long) imm_expr.X_add_number | |
9319 | + lastpos) < limlo | |
9320 | || ((unsigned long) imm_expr.X_add_number | |
9321 | + lastpos) > limhi) | |
9322 | { | |
9323 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
9324 | (unsigned long) imm_expr.X_add_number, | |
9325 | (unsigned long) lastpos); | |
9326 | imm_expr.X_add_number = limlo - lastpos; | |
9327 | } | |
bf12938e | 9328 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
9329 | imm_expr.X_op = O_absent; |
9330 | s = expr_end; | |
9331 | continue; | |
af7ee8bf | 9332 | |
bbcc0807 CD |
9333 | case 'D': |
9334 | /* +D is for disassembly only; never match. */ | |
9335 | break; | |
9336 | ||
5f74bc13 CD |
9337 | case 'I': |
9338 | /* "+I" is like "I", except that imm2_expr is used. */ | |
9339 | my_getExpression (&imm2_expr, s); | |
9340 | if (imm2_expr.X_op != O_big | |
9341 | && imm2_expr.X_op != O_constant) | |
9342 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9343 | if (HAVE_32BIT_GPRS) |
9344 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
9345 | s = expr_end; |
9346 | continue; | |
9347 | ||
707bfff6 | 9348 | case 'T': /* Coprocessor register. */ |
ef2e4d86 CF |
9349 | /* +T is for disassembly only; never match. */ |
9350 | break; | |
9351 | ||
707bfff6 | 9352 | case 't': /* Coprocessor register number. */ |
ef2e4d86 CF |
9353 | if (s[0] == '$' && ISDIGIT (s[1])) |
9354 | { | |
9355 | ++s; | |
9356 | regno = 0; | |
9357 | do | |
9358 | { | |
9359 | regno *= 10; | |
9360 | regno += *s - '0'; | |
9361 | ++s; | |
9362 | } | |
9363 | while (ISDIGIT (*s)); | |
9364 | if (regno > 31) | |
9365 | as_bad (_("Invalid register number (%d)"), regno); | |
9366 | else | |
9367 | { | |
a9e24354 | 9368 | INSERT_OPERAND (RT, *ip, regno); |
ef2e4d86 CF |
9369 | continue; |
9370 | } | |
9371 | } | |
9372 | else | |
9373 | as_bad (_("Invalid coprocessor 0 register number")); | |
9374 | break; | |
9375 | ||
bb35fb24 NC |
9376 | case 'x': |
9377 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
9378 | is not in the valid range. */ | |
9379 | my_getExpression (&imm_expr, s); | |
9380 | check_absolute_expr (ip, &imm_expr); | |
9381 | if ((unsigned) imm_expr.X_add_number > 31) | |
9382 | { | |
9383 | as_bad (_("Improper bit index (%lu)"), | |
9384 | (unsigned long) imm_expr.X_add_number); | |
9385 | imm_expr.X_add_number = 0; | |
9386 | } | |
9387 | INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number); | |
9388 | imm_expr.X_op = O_absent; | |
9389 | s = expr_end; | |
9390 | continue; | |
9391 | ||
9392 | case 'X': | |
9393 | /* bbit[01] bit index when bbit is used but we generate | |
9394 | bbit[01]32 because the index is over 32. Move to the | |
9395 | next candidate if index is not in the valid range. */ | |
9396 | my_getExpression (&imm_expr, s); | |
9397 | check_absolute_expr (ip, &imm_expr); | |
9398 | if ((unsigned) imm_expr.X_add_number < 32 | |
9399 | || (unsigned) imm_expr.X_add_number > 63) | |
9400 | break; | |
9401 | INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32); | |
9402 | imm_expr.X_op = O_absent; | |
9403 | s = expr_end; | |
9404 | continue; | |
9405 | ||
9406 | case 'p': | |
9407 | /* cins, cins32, exts and exts32 position field. Give error | |
9408 | if it's not in the valid range. */ | |
9409 | my_getExpression (&imm_expr, s); | |
9410 | check_absolute_expr (ip, &imm_expr); | |
9411 | if ((unsigned) imm_expr.X_add_number > 31) | |
9412 | { | |
9413 | as_bad (_("Improper position (%lu)"), | |
9414 | (unsigned long) imm_expr.X_add_number); | |
9415 | imm_expr.X_add_number = 0; | |
9416 | } | |
9417 | /* Make the pos explicit to simplify +S. */ | |
9418 | lastpos = imm_expr.X_add_number + 32; | |
9419 | INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number); | |
9420 | imm_expr.X_op = O_absent; | |
9421 | s = expr_end; | |
9422 | continue; | |
9423 | ||
9424 | case 'P': | |
9425 | /* cins, cins32, exts and exts32 position field. Move to | |
9426 | the next candidate if it's not in the valid range. */ | |
9427 | my_getExpression (&imm_expr, s); | |
9428 | check_absolute_expr (ip, &imm_expr); | |
9429 | if ((unsigned) imm_expr.X_add_number < 32 | |
9430 | || (unsigned) imm_expr.X_add_number > 63) | |
9431 | break; | |
9432 | lastpos = imm_expr.X_add_number; | |
9433 | INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32); | |
9434 | imm_expr.X_op = O_absent; | |
9435 | s = expr_end; | |
9436 | continue; | |
9437 | ||
9438 | case 's': | |
9439 | /* cins and exts length-minus-one field. */ | |
9440 | my_getExpression (&imm_expr, s); | |
9441 | check_absolute_expr (ip, &imm_expr); | |
9442 | if ((unsigned long) imm_expr.X_add_number > 31) | |
9443 | { | |
9444 | as_bad (_("Improper size (%lu)"), | |
9445 | (unsigned long) imm_expr.X_add_number); | |
9446 | imm_expr.X_add_number = 0; | |
9447 | } | |
9448 | INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number); | |
9449 | imm_expr.X_op = O_absent; | |
9450 | s = expr_end; | |
9451 | continue; | |
9452 | ||
9453 | case 'S': | |
9454 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
9455 | length-minus-one field. */ | |
9456 | my_getExpression (&imm_expr, s); | |
9457 | check_absolute_expr (ip, &imm_expr); | |
9458 | if ((long) imm_expr.X_add_number < 0 | |
9459 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
9460 | { | |
9461 | as_bad (_("Improper size (%lu)"), | |
9462 | (unsigned long) imm_expr.X_add_number); | |
9463 | imm_expr.X_add_number = 0; | |
9464 | } | |
9465 | INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number); | |
9466 | imm_expr.X_op = O_absent; | |
9467 | s = expr_end; | |
9468 | continue; | |
9469 | ||
dd3cbb7e NC |
9470 | case 'Q': |
9471 | /* seqi/snei immediate field. */ | |
9472 | my_getExpression (&imm_expr, s); | |
9473 | check_absolute_expr (ip, &imm_expr); | |
9474 | if ((long) imm_expr.X_add_number < -512 | |
9475 | || (long) imm_expr.X_add_number >= 512) | |
9476 | { | |
9477 | as_bad (_("Improper immediate (%ld)"), | |
9478 | (long) imm_expr.X_add_number); | |
9479 | imm_expr.X_add_number = 0; | |
9480 | } | |
9481 | INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number); | |
9482 | imm_expr.X_op = O_absent; | |
9483 | s = expr_end; | |
9484 | continue; | |
9485 | ||
98675402 RS |
9486 | case 'a': /* 8-bit signed offset in bit 6 */ |
9487 | my_getExpression (&imm_expr, s); | |
9488 | check_absolute_expr (ip, &imm_expr); | |
9489 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
9490 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
9491 | if (imm_expr.X_add_number < min_range | |
9492 | || imm_expr.X_add_number > max_range) | |
9493 | { | |
c95354ed | 9494 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
9495 | (long) min_range, (long) max_range, |
9496 | (long) imm_expr.X_add_number); | |
9497 | } | |
9498 | INSERT_OPERAND (OFFSET_A, *ip, imm_expr.X_add_number); | |
9499 | imm_expr.X_op = O_absent; | |
9500 | s = expr_end; | |
9501 | continue; | |
9502 | ||
9503 | case 'b': /* 8-bit signed offset in bit 3 */ | |
9504 | my_getExpression (&imm_expr, s); | |
9505 | check_absolute_expr (ip, &imm_expr); | |
9506 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
9507 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
9508 | if (imm_expr.X_add_number < min_range | |
9509 | || imm_expr.X_add_number > max_range) | |
9510 | { | |
c95354ed | 9511 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
9512 | (long) min_range, (long) max_range, |
9513 | (long) imm_expr.X_add_number); | |
9514 | } | |
9515 | INSERT_OPERAND (OFFSET_B, *ip, imm_expr.X_add_number); | |
9516 | imm_expr.X_op = O_absent; | |
9517 | s = expr_end; | |
9518 | continue; | |
9519 | ||
9520 | case 'c': /* 9-bit signed offset in bit 6 */ | |
9521 | my_getExpression (&imm_expr, s); | |
9522 | check_absolute_expr (ip, &imm_expr); | |
9523 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
9524 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
9525 | /* We check the offset range before adjusted. */ |
9526 | min_range <<= 4; | |
9527 | max_range <<= 4; | |
98675402 RS |
9528 | if (imm_expr.X_add_number < min_range |
9529 | || imm_expr.X_add_number > max_range) | |
9530 | { | |
c95354ed | 9531 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
9532 | (long) min_range, (long) max_range, |
9533 | (long) imm_expr.X_add_number); | |
9534 | } | |
c95354ed MX |
9535 | if (imm_expr.X_add_number & 0xf) |
9536 | { | |
9537 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
9538 | (long) imm_expr.X_add_number); | |
9539 | } | |
9540 | /* Right shift 4 bits to adjust the offset operand. */ | |
9541 | INSERT_OPERAND (OFFSET_C, *ip, imm_expr.X_add_number >> 4); | |
98675402 RS |
9542 | imm_expr.X_op = O_absent; |
9543 | s = expr_end; | |
9544 | continue; | |
9545 | ||
9546 | case 'z': | |
9547 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
9548 | break; | |
9549 | if (regno == AT && mips_opts.at) | |
9550 | { | |
9551 | if (mips_opts.at == ATREG) | |
9552 | as_warn (_("used $at without \".set noat\"")); | |
9553 | else | |
9554 | as_warn (_("used $%u with \".set at=$%u\""), | |
9555 | regno, mips_opts.at); | |
9556 | } | |
9557 | INSERT_OPERAND (RZ, *ip, regno); | |
9558 | continue; | |
9559 | ||
9560 | case 'Z': | |
9561 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) | |
9562 | break; | |
9563 | INSERT_OPERAND (FZ, *ip, regno); | |
9564 | continue; | |
9565 | ||
af7ee8bf | 9566 | default: |
f71d0d44 | 9567 | as_bad (_("Internal error: bad mips opcode " |
90ecf173 MR |
9568 | "(unknown extension operand type `+%c'): %s %s"), |
9569 | *args, insn->name, insn->args); | |
af7ee8bf CD |
9570 | /* Further processing is fruitless. */ |
9571 | return; | |
9572 | } | |
9573 | break; | |
9574 | ||
252b5132 RH |
9575 | case '<': /* must be at least one digit */ |
9576 | /* | |
9577 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
9578 | * than 31 or less than 0, then the shift amount should be |
9579 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
9580 | * We issue a warning and mask out all but the low 5 bits. |
9581 | */ | |
9582 | my_getExpression (&imm_expr, s); | |
9583 | check_absolute_expr (ip, &imm_expr); | |
9584 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
9585 | as_warn (_("Improper shift amount (%lu)"), |
9586 | (unsigned long) imm_expr.X_add_number); | |
9587 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9588 | imm_expr.X_op = O_absent; |
9589 | s = expr_end; | |
9590 | continue; | |
9591 | ||
9592 | case '>': /* shift amount minus 32 */ | |
9593 | my_getExpression (&imm_expr, s); | |
9594 | check_absolute_expr (ip, &imm_expr); | |
9595 | if ((unsigned long) imm_expr.X_add_number < 32 | |
9596 | || (unsigned long) imm_expr.X_add_number > 63) | |
9597 | break; | |
bf12938e | 9598 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
9599 | imm_expr.X_op = O_absent; |
9600 | s = expr_end; | |
9601 | continue; | |
9602 | ||
90ecf173 MR |
9603 | case 'k': /* CACHE code. */ |
9604 | case 'h': /* PREFX code. */ | |
9605 | case '1': /* SYNC type. */ | |
252b5132 RH |
9606 | my_getExpression (&imm_expr, s); |
9607 | check_absolute_expr (ip, &imm_expr); | |
9608 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
9609 | as_warn (_("Invalid value for `%s' (%lu)"), |
9610 | ip->insn_mo->name, | |
9611 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 9612 | if (*args == 'k') |
d954098f DD |
9613 | { |
9614 | if (mips_fix_cn63xxp1 && strcmp ("pref", insn->name) == 0) | |
9615 | switch (imm_expr.X_add_number) | |
9616 | { | |
9617 | case 5: | |
9618 | case 25: | |
9619 | case 26: | |
9620 | case 27: | |
9621 | case 28: | |
9622 | case 29: | |
9623 | case 30: | |
9624 | case 31: /* These are ok. */ | |
9625 | break; | |
9626 | ||
9627 | default: /* The rest must be changed to 28. */ | |
9628 | imm_expr.X_add_number = 28; | |
9629 | break; | |
9630 | } | |
9631 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); | |
9632 | } | |
620edafd | 9633 | else if (*args == 'h') |
bf12938e | 9634 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
620edafd CF |
9635 | else |
9636 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9637 | imm_expr.X_op = O_absent; |
9638 | s = expr_end; | |
9639 | continue; | |
9640 | ||
90ecf173 | 9641 | case 'c': /* BREAK code. */ |
252b5132 RH |
9642 | my_getExpression (&imm_expr, s); |
9643 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9644 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE) |
9645 | as_warn (_("Code for %s not in range 0..1023 (%lu)"), | |
9646 | ip->insn_mo->name, | |
bf12938e RS |
9647 | (unsigned long) imm_expr.X_add_number); |
9648 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9649 | imm_expr.X_op = O_absent; |
9650 | s = expr_end; | |
9651 | continue; | |
9652 | ||
90ecf173 | 9653 | case 'q': /* Lower BREAK code. */ |
252b5132 RH |
9654 | my_getExpression (&imm_expr, s); |
9655 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9656 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2) |
9657 | as_warn (_("Lower code for %s not in range 0..1023 (%lu)"), | |
9658 | ip->insn_mo->name, | |
bf12938e RS |
9659 | (unsigned long) imm_expr.X_add_number); |
9660 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9661 | imm_expr.X_op = O_absent; |
9662 | s = expr_end; | |
9663 | continue; | |
9664 | ||
90ecf173 | 9665 | case 'B': /* 20-bit SYSCALL/BREAK code. */ |
156c2f8b | 9666 | my_getExpression (&imm_expr, s); |
156c2f8b | 9667 | check_absolute_expr (ip, &imm_expr); |
793b27f4 | 9668 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
a9e24354 TS |
9669 | as_warn (_("Code for %s not in range 0..1048575 (%lu)"), |
9670 | ip->insn_mo->name, | |
793b27f4 | 9671 | (unsigned long) imm_expr.X_add_number); |
bf12938e | 9672 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
9673 | imm_expr.X_op = O_absent; |
9674 | s = expr_end; | |
9675 | continue; | |
9676 | ||
90ecf173 | 9677 | case 'C': /* Coprocessor code. */ |
beae10d5 | 9678 | my_getExpression (&imm_expr, s); |
252b5132 | 9679 | check_absolute_expr (ip, &imm_expr); |
a9e24354 | 9680 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ) |
252b5132 | 9681 | { |
793b27f4 TS |
9682 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
9683 | (unsigned long) imm_expr.X_add_number); | |
a9e24354 | 9684 | imm_expr.X_add_number &= OP_MASK_COPZ; |
252b5132 | 9685 | } |
a9e24354 | 9686 | INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number); |
beae10d5 KH |
9687 | imm_expr.X_op = O_absent; |
9688 | s = expr_end; | |
9689 | continue; | |
252b5132 | 9690 | |
90ecf173 | 9691 | case 'J': /* 19-bit WAIT code. */ |
4372b673 NC |
9692 | my_getExpression (&imm_expr, s); |
9693 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 9694 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
a9e24354 TS |
9695 | { |
9696 | as_warn (_("Illegal 19-bit code (%lu)"), | |
9697 | (unsigned long) imm_expr.X_add_number); | |
9698 | imm_expr.X_add_number &= OP_MASK_CODE19; | |
9699 | } | |
bf12938e | 9700 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
9701 | imm_expr.X_op = O_absent; |
9702 | s = expr_end; | |
9703 | continue; | |
9704 | ||
707bfff6 | 9705 | case 'P': /* Performance register. */ |
beae10d5 | 9706 | my_getExpression (&imm_expr, s); |
252b5132 | 9707 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 9708 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
9709 | as_warn (_("Invalid performance register (%lu)"), |
9710 | (unsigned long) imm_expr.X_add_number); | |
9711 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
9712 | imm_expr.X_op = O_absent; |
9713 | s = expr_end; | |
9714 | continue; | |
252b5132 | 9715 | |
707bfff6 TS |
9716 | case 'G': /* Coprocessor destination register. */ |
9717 | if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0) | |
9718 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no); | |
9719 | else | |
9720 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
a9e24354 | 9721 | INSERT_OPERAND (RD, *ip, regno); |
707bfff6 TS |
9722 | if (ok) |
9723 | { | |
9724 | lastregno = regno; | |
9725 | continue; | |
9726 | } | |
9727 | else | |
9728 | break; | |
9729 | ||
90ecf173 MR |
9730 | case 'b': /* Base register. */ |
9731 | case 'd': /* Destination register. */ | |
9732 | case 's': /* Source register. */ | |
9733 | case 't': /* Target register. */ | |
9734 | case 'r': /* Both target and source. */ | |
9735 | case 'v': /* Both dest and source. */ | |
9736 | case 'w': /* Both dest and target. */ | |
9737 | case 'E': /* Coprocessor target register. */ | |
9738 | case 'K': /* RDHWR destination register. */ | |
9739 | case 'x': /* Ignore register name. */ | |
9740 | case 'z': /* Must be zero register. */ | |
9741 | case 'U': /* Destination register (CLO/CLZ). */ | |
9742 | case 'g': /* Coprocessor destination register. */ | |
9743 | s_reset = s; | |
707bfff6 TS |
9744 | if (*args == 'E' || *args == 'K') |
9745 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
9746 | else | |
9747 | { | |
9748 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
9749 | if (regno == AT && mips_opts.at) |
9750 | { | |
9751 | if (mips_opts.at == ATREG) | |
f71d0d44 | 9752 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 9753 | else |
f71d0d44 | 9754 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
9755 | regno, mips_opts.at); |
9756 | } | |
707bfff6 TS |
9757 | } |
9758 | if (ok) | |
252b5132 | 9759 | { |
252b5132 RH |
9760 | c = *args; |
9761 | if (*s == ' ') | |
f9419b05 | 9762 | ++s; |
252b5132 RH |
9763 | if (args[1] != *s) |
9764 | { | |
9765 | if (c == 'r' || c == 'v' || c == 'w') | |
9766 | { | |
9767 | regno = lastregno; | |
9768 | s = s_reset; | |
f9419b05 | 9769 | ++args; |
252b5132 RH |
9770 | } |
9771 | } | |
9772 | /* 'z' only matches $0. */ | |
9773 | if (c == 'z' && regno != 0) | |
9774 | break; | |
9775 | ||
24864476 | 9776 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
9777 | { |
9778 | if (regno == lastregno) | |
90ecf173 MR |
9779 | { |
9780 | insn_error | |
f71d0d44 | 9781 | = _("Source and destination must be different"); |
e7c604dd | 9782 | continue; |
90ecf173 | 9783 | } |
24864476 | 9784 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
9785 | { |
9786 | insn_error | |
f71d0d44 | 9787 | = _("A destination register must be supplied"); |
e7c604dd | 9788 | continue; |
90ecf173 | 9789 | } |
e7c604dd | 9790 | } |
90ecf173 MR |
9791 | /* Now that we have assembled one operand, we use the args |
9792 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
9793 | switch (c) |
9794 | { | |
9795 | case 'r': | |
9796 | case 's': | |
9797 | case 'v': | |
9798 | case 'b': | |
bf12938e | 9799 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
9800 | break; |
9801 | case 'd': | |
af7ee8bf | 9802 | case 'K': |
ef2e4d86 | 9803 | case 'g': |
bf12938e | 9804 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 9805 | break; |
4372b673 | 9806 | case 'U': |
bf12938e RS |
9807 | INSERT_OPERAND (RD, *ip, regno); |
9808 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 9809 | break; |
252b5132 RH |
9810 | case 'w': |
9811 | case 't': | |
9812 | case 'E': | |
bf12938e | 9813 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
9814 | break; |
9815 | case 'x': | |
9816 | /* This case exists because on the r3000 trunc | |
9817 | expands into a macro which requires a gp | |
9818 | register. On the r6000 or r4000 it is | |
9819 | assembled into a single instruction which | |
9820 | ignores the register. Thus the insn version | |
9821 | is MIPS_ISA2 and uses 'x', and the macro | |
9822 | version is MIPS_ISA1 and uses 't'. */ | |
9823 | break; | |
9824 | case 'z': | |
9825 | /* This case is for the div instruction, which | |
9826 | acts differently if the destination argument | |
9827 | is $0. This only matches $0, and is checked | |
9828 | outside the switch. */ | |
9829 | break; | |
252b5132 RH |
9830 | } |
9831 | lastregno = regno; | |
9832 | continue; | |
9833 | } | |
252b5132 RH |
9834 | switch (*args++) |
9835 | { | |
9836 | case 'r': | |
9837 | case 'v': | |
bf12938e | 9838 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9839 | continue; |
9840 | case 'w': | |
bf12938e | 9841 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
9842 | continue; |
9843 | } | |
9844 | break; | |
9845 | ||
deec1734 CD |
9846 | case 'O': /* MDMX alignment immediate constant. */ |
9847 | my_getExpression (&imm_expr, s); | |
9848 | check_absolute_expr (ip, &imm_expr); | |
9849 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 9850 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e RS |
9851 | (long) imm_expr.X_add_number); |
9852 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9853 | imm_expr.X_op = O_absent; |
9854 | s = expr_end; | |
9855 | continue; | |
9856 | ||
9857 | case 'Q': /* MDMX vector, element sel, or const. */ | |
9858 | if (s[0] != '$') | |
9859 | { | |
9860 | /* MDMX Immediate. */ | |
9861 | my_getExpression (&imm_expr, s); | |
9862 | check_absolute_expr (ip, &imm_expr); | |
9863 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
9864 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
9865 | (long) imm_expr.X_add_number); | |
9866 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9867 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
9868 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
9869 | else | |
9870 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
9871 | imm_expr.X_op = O_absent; |
9872 | s = expr_end; | |
9873 | continue; | |
9874 | } | |
9875 | /* Not MDMX Immediate. Fall through. */ | |
9876 | case 'X': /* MDMX destination register. */ | |
9877 | case 'Y': /* MDMX source register. */ | |
9878 | case 'Z': /* MDMX target register. */ | |
9879 | is_mdmx = 1; | |
90ecf173 MR |
9880 | case 'D': /* Floating point destination register. */ |
9881 | case 'S': /* Floating point source register. */ | |
9882 | case 'T': /* Floating point target register. */ | |
9883 | case 'R': /* Floating point source register. */ | |
252b5132 RH |
9884 | case 'V': |
9885 | case 'W': | |
707bfff6 TS |
9886 | rtype = RTYPE_FPU; |
9887 | if (is_mdmx | |
9888 | || (mips_opts.ase_mdmx | |
9889 | && (ip->insn_mo->pinfo & FP_D) | |
9890 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
9891 | | INSN_COPROC_MEMORY_DELAY | |
9892 | | INSN_LOAD_COPROC_DELAY | |
9893 | | INSN_LOAD_MEMORY_DELAY | |
9894 | | INSN_STORE_MEMORY)))) | |
9895 | rtype |= RTYPE_VEC; | |
252b5132 | 9896 | s_reset = s; |
707bfff6 | 9897 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 9898 | { |
252b5132 | 9899 | if ((regno & 1) != 0 |
ca4e0257 | 9900 | && HAVE_32BIT_FPRS |
90ecf173 | 9901 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
9902 | as_warn (_("Float register should be even, was %d"), |
9903 | regno); | |
9904 | ||
9905 | c = *args; | |
9906 | if (*s == ' ') | |
f9419b05 | 9907 | ++s; |
252b5132 RH |
9908 | if (args[1] != *s) |
9909 | { | |
9910 | if (c == 'V' || c == 'W') | |
9911 | { | |
9912 | regno = lastregno; | |
9913 | s = s_reset; | |
f9419b05 | 9914 | ++args; |
252b5132 RH |
9915 | } |
9916 | } | |
9917 | switch (c) | |
9918 | { | |
9919 | case 'D': | |
deec1734 | 9920 | case 'X': |
bf12938e | 9921 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
9922 | break; |
9923 | case 'V': | |
9924 | case 'S': | |
deec1734 | 9925 | case 'Y': |
bf12938e | 9926 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 9927 | break; |
deec1734 CD |
9928 | case 'Q': |
9929 | /* This is like 'Z', but also needs to fix the MDMX | |
9930 | vector/scalar select bits. Note that the | |
9931 | scalar immediate case is handled above. */ | |
9932 | if (*s == '[') | |
9933 | { | |
9934 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
9935 | int max_el = (is_qh ? 3 : 7); | |
9936 | s++; | |
9937 | my_getExpression(&imm_expr, s); | |
9938 | check_absolute_expr (ip, &imm_expr); | |
9939 | s = expr_end; | |
9940 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
9941 | as_bad (_("Bad element selector %ld"), |
9942 | (long) imm_expr.X_add_number); | |
deec1734 CD |
9943 | imm_expr.X_add_number &= max_el; |
9944 | ip->insn_opcode |= (imm_expr.X_add_number | |
9945 | << (OP_SH_VSEL + | |
9946 | (is_qh ? 2 : 1))); | |
01a3f561 | 9947 | imm_expr.X_op = O_absent; |
deec1734 | 9948 | if (*s != ']') |
20203fb9 | 9949 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
9950 | else |
9951 | s++; | |
9952 | } | |
9953 | else | |
9954 | { | |
9955 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
9956 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
9957 | << OP_SH_VSEL); | |
9958 | else | |
9959 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
9960 | OP_SH_VSEL); | |
9961 | } | |
90ecf173 | 9962 | /* Fall through. */ |
252b5132 RH |
9963 | case 'W': |
9964 | case 'T': | |
deec1734 | 9965 | case 'Z': |
bf12938e | 9966 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
9967 | break; |
9968 | case 'R': | |
bf12938e | 9969 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
9970 | break; |
9971 | } | |
9972 | lastregno = regno; | |
9973 | continue; | |
9974 | } | |
9975 | ||
252b5132 RH |
9976 | switch (*args++) |
9977 | { | |
9978 | case 'V': | |
bf12938e | 9979 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9980 | continue; |
9981 | case 'W': | |
bf12938e | 9982 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9983 | continue; |
9984 | } | |
9985 | break; | |
9986 | ||
9987 | case 'I': | |
9988 | my_getExpression (&imm_expr, s); | |
9989 | if (imm_expr.X_op != O_big | |
9990 | && imm_expr.X_op != O_constant) | |
9991 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9992 | if (HAVE_32BIT_GPRS) |
9993 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
9994 | s = expr_end; |
9995 | continue; | |
9996 | ||
9997 | case 'A': | |
9998 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 9999 | normalize_address_expr (&offset_expr); |
f6688943 | 10000 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
10001 | s = expr_end; |
10002 | continue; | |
10003 | ||
10004 | case 'F': | |
10005 | case 'L': | |
10006 | case 'f': | |
10007 | case 'l': | |
10008 | { | |
10009 | int f64; | |
ca4e0257 | 10010 | int using_gprs; |
252b5132 RH |
10011 | char *save_in; |
10012 | char *err; | |
10013 | unsigned char temp[8]; | |
10014 | int len; | |
10015 | unsigned int length; | |
10016 | segT seg; | |
10017 | subsegT subseg; | |
10018 | char *p; | |
10019 | ||
10020 | /* These only appear as the last operand in an | |
10021 | instruction, and every instruction that accepts | |
10022 | them in any variant accepts them in all variants. | |
10023 | This means we don't have to worry about backing out | |
10024 | any changes if the instruction does not match. | |
10025 | ||
10026 | The difference between them is the size of the | |
10027 | floating point constant and where it goes. For 'F' | |
10028 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
10029 | is 32 bits. Where the constant is placed is based | |
10030 | on how the MIPS assembler does things: | |
10031 | F -- .rdata | |
10032 | L -- .lit8 | |
10033 | f -- immediate value | |
10034 | l -- .lit4 | |
10035 | ||
10036 | The .lit4 and .lit8 sections are only used if | |
10037 | permitted by the -G argument. | |
10038 | ||
ca4e0257 RS |
10039 | The code below needs to know whether the target register |
10040 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
10041 | 'F' are used with GPR-based instructions and 'l' and | |
10042 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
10043 | |
10044 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 10045 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
10046 | |
10047 | save_in = input_line_pointer; | |
10048 | input_line_pointer = s; | |
10049 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
10050 | length = len; | |
10051 | s = input_line_pointer; | |
10052 | input_line_pointer = save_in; | |
10053 | if (err != NULL && *err != '\0') | |
10054 | { | |
10055 | as_bad (_("Bad floating point constant: %s"), err); | |
10056 | memset (temp, '\0', sizeof temp); | |
10057 | length = f64 ? 8 : 4; | |
10058 | } | |
10059 | ||
9c2799c2 | 10060 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
10061 | |
10062 | if (*args == 'f' | |
10063 | || (*args == 'l' | |
3e722fb5 | 10064 | && (g_switch_value < 4 |
252b5132 RH |
10065 | || (temp[0] == 0 && temp[1] == 0) |
10066 | || (temp[2] == 0 && temp[3] == 0)))) | |
10067 | { | |
10068 | imm_expr.X_op = O_constant; | |
90ecf173 | 10069 | if (!target_big_endian) |
252b5132 RH |
10070 | imm_expr.X_add_number = bfd_getl32 (temp); |
10071 | else | |
10072 | imm_expr.X_add_number = bfd_getb32 (temp); | |
10073 | } | |
10074 | else if (length > 4 | |
90ecf173 | 10075 | && !mips_disable_float_construction |
ca4e0257 RS |
10076 | /* Constants can only be constructed in GPRs and |
10077 | copied to FPRs if the GPRs are at least as wide | |
10078 | as the FPRs. Force the constant into memory if | |
10079 | we are using 64-bit FPRs but the GPRs are only | |
10080 | 32 bits wide. */ | |
10081 | && (using_gprs | |
90ecf173 | 10082 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
10083 | && ((temp[0] == 0 && temp[1] == 0) |
10084 | || (temp[2] == 0 && temp[3] == 0)) | |
10085 | && ((temp[4] == 0 && temp[5] == 0) | |
10086 | || (temp[6] == 0 && temp[7] == 0))) | |
10087 | { | |
ca4e0257 | 10088 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
10089 | instructions. If using 32-bit registers, set |
10090 | imm_expr to the high order 32 bits and offset_expr to | |
10091 | the low order 32 bits. Otherwise, set imm_expr to | |
10092 | the entire 64 bit constant. */ | |
ca4e0257 | 10093 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
10094 | { |
10095 | imm_expr.X_op = O_constant; | |
10096 | offset_expr.X_op = O_constant; | |
90ecf173 | 10097 | if (!target_big_endian) |
252b5132 RH |
10098 | { |
10099 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
10100 | offset_expr.X_add_number = bfd_getl32 (temp); | |
10101 | } | |
10102 | else | |
10103 | { | |
10104 | imm_expr.X_add_number = bfd_getb32 (temp); | |
10105 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
10106 | } | |
10107 | if (offset_expr.X_add_number == 0) | |
10108 | offset_expr.X_op = O_absent; | |
10109 | } | |
10110 | else if (sizeof (imm_expr.X_add_number) > 4) | |
10111 | { | |
10112 | imm_expr.X_op = O_constant; | |
90ecf173 | 10113 | if (!target_big_endian) |
252b5132 RH |
10114 | imm_expr.X_add_number = bfd_getl64 (temp); |
10115 | else | |
10116 | imm_expr.X_add_number = bfd_getb64 (temp); | |
10117 | } | |
10118 | else | |
10119 | { | |
10120 | imm_expr.X_op = O_big; | |
10121 | imm_expr.X_add_number = 4; | |
90ecf173 | 10122 | if (!target_big_endian) |
252b5132 RH |
10123 | { |
10124 | generic_bignum[0] = bfd_getl16 (temp); | |
10125 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
10126 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
10127 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
10128 | } | |
10129 | else | |
10130 | { | |
10131 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
10132 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
10133 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
10134 | generic_bignum[3] = bfd_getb16 (temp); | |
10135 | } | |
10136 | } | |
10137 | } | |
10138 | else | |
10139 | { | |
10140 | const char *newname; | |
10141 | segT new_seg; | |
10142 | ||
10143 | /* Switch to the right section. */ | |
10144 | seg = now_seg; | |
10145 | subseg = now_subseg; | |
10146 | switch (*args) | |
10147 | { | |
10148 | default: /* unused default case avoids warnings. */ | |
10149 | case 'L': | |
10150 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 10151 | if (g_switch_value >= 8) |
252b5132 RH |
10152 | newname = ".lit8"; |
10153 | break; | |
10154 | case 'F': | |
3e722fb5 | 10155 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
10156 | break; |
10157 | case 'l': | |
9c2799c2 | 10158 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
10159 | newname = ".lit4"; |
10160 | break; | |
10161 | } | |
10162 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 10163 | if (IS_ELF) |
252b5132 RH |
10164 | bfd_set_section_flags (stdoutput, new_seg, |
10165 | (SEC_ALLOC | |
10166 | | SEC_LOAD | |
10167 | | SEC_READONLY | |
10168 | | SEC_DATA)); | |
10169 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 10170 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
10171 | record_alignment (new_seg, 4); |
10172 | else | |
10173 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
10174 | if (seg == now_seg) | |
10175 | as_bad (_("Can't use floating point insn in this section")); | |
10176 | ||
10177 | /* Set the argument to the current address in the | |
10178 | section. */ | |
10179 | offset_expr.X_op = O_symbol; | |
8680f6e1 | 10180 | offset_expr.X_add_symbol = symbol_temp_new_now (); |
252b5132 RH |
10181 | offset_expr.X_add_number = 0; |
10182 | ||
10183 | /* Put the floating point number into the section. */ | |
10184 | p = frag_more ((int) length); | |
10185 | memcpy (p, temp, length); | |
10186 | ||
10187 | /* Switch back to the original section. */ | |
10188 | subseg_set (seg, subseg); | |
10189 | } | |
10190 | } | |
10191 | continue; | |
10192 | ||
90ecf173 MR |
10193 | case 'i': /* 16-bit unsigned immediate. */ |
10194 | case 'j': /* 16-bit signed immediate. */ | |
f6688943 | 10195 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 10196 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
10197 | { |
10198 | int more; | |
5e0116d5 RS |
10199 | offsetT minval, maxval; |
10200 | ||
10201 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
10202 | && strcmp (insn->name, insn[1].name) == 0); | |
10203 | ||
10204 | /* If the expression was written as an unsigned number, | |
10205 | only treat it as signed if there are no more | |
10206 | alternatives. */ | |
10207 | if (more | |
10208 | && *args == 'j' | |
10209 | && sizeof (imm_expr.X_add_number) <= 4 | |
10210 | && imm_expr.X_op == O_constant | |
10211 | && imm_expr.X_add_number < 0 | |
10212 | && imm_expr.X_unsigned | |
10213 | && HAVE_64BIT_GPRS) | |
10214 | break; | |
10215 | ||
10216 | /* For compatibility with older assemblers, we accept | |
10217 | 0x8000-0xffff as signed 16-bit numbers when only | |
10218 | signed numbers are allowed. */ | |
10219 | if (*args == 'i') | |
10220 | minval = 0, maxval = 0xffff; | |
10221 | else if (more) | |
10222 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 10223 | else |
5e0116d5 RS |
10224 | minval = -0x8000, maxval = 0xffff; |
10225 | ||
10226 | if (imm_expr.X_op != O_constant | |
10227 | || imm_expr.X_add_number < minval | |
10228 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
10229 | { |
10230 | if (more) | |
10231 | break; | |
2ae7e77b AH |
10232 | if (imm_expr.X_op == O_constant |
10233 | || imm_expr.X_op == O_big) | |
f71d0d44 | 10234 | as_bad (_("Expression out of range")); |
252b5132 RH |
10235 | } |
10236 | } | |
10237 | s = expr_end; | |
10238 | continue; | |
10239 | ||
90ecf173 | 10240 | case 'o': /* 16-bit offset. */ |
4614d845 MR |
10241 | offset_reloc[0] = BFD_RELOC_LO16; |
10242 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
10243 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
10244 | ||
5e0116d5 RS |
10245 | /* Check whether there is only a single bracketed expression |
10246 | left. If so, it must be the base register and the | |
10247 | constant must be zero. */ | |
10248 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
10249 | { | |
10250 | offset_expr.X_op = O_constant; | |
10251 | offset_expr.X_add_number = 0; | |
10252 | continue; | |
10253 | } | |
252b5132 RH |
10254 | |
10255 | /* If this value won't fit into a 16 bit offset, then go | |
10256 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 10257 | code pattern. */ |
5e0116d5 | 10258 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
10259 | && (offset_expr.X_op != O_constant |
10260 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 10261 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
10262 | break; |
10263 | ||
252b5132 RH |
10264 | s = expr_end; |
10265 | continue; | |
10266 | ||
90ecf173 | 10267 | case 'p': /* PC-relative offset. */ |
0b25d3e6 | 10268 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
10269 | my_getExpression (&offset_expr, s); |
10270 | s = expr_end; | |
10271 | continue; | |
10272 | ||
90ecf173 | 10273 | case 'u': /* Upper 16 bits. */ |
5e0116d5 RS |
10274 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
10275 | && imm_expr.X_op == O_constant | |
10276 | && (imm_expr.X_add_number < 0 | |
10277 | || imm_expr.X_add_number >= 0x10000)) | |
88320db2 MR |
10278 | as_bad (_("lui expression (%lu) not in range 0..65535"), |
10279 | (unsigned long) imm_expr.X_add_number); | |
252b5132 RH |
10280 | s = expr_end; |
10281 | continue; | |
10282 | ||
90ecf173 | 10283 | case 'a': /* 26-bit address. */ |
252b5132 RH |
10284 | my_getExpression (&offset_expr, s); |
10285 | s = expr_end; | |
f6688943 | 10286 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
10287 | continue; |
10288 | ||
90ecf173 MR |
10289 | case 'N': /* 3-bit branch condition code. */ |
10290 | case 'M': /* 3-bit compare condition code. */ | |
707bfff6 | 10291 | rtype = RTYPE_CCC; |
90ecf173 | 10292 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) |
707bfff6 TS |
10293 | rtype |= RTYPE_FCC; |
10294 | if (!reg_lookup (&s, rtype, ®no)) | |
252b5132 | 10295 | break; |
90ecf173 MR |
10296 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 |
10297 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
10298 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
30c378fd | 10299 | && (regno & 1) != 0) |
90ecf173 MR |
10300 | as_warn (_("Condition code register should be even for %s, " |
10301 | "was %d"), | |
20203fb9 | 10302 | str, regno); |
90ecf173 MR |
10303 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 |
10304 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
30c378fd | 10305 | && (regno & 3) != 0) |
90ecf173 MR |
10306 | as_warn (_("Condition code register should be 0 or 4 for %s, " |
10307 | "was %d"), | |
20203fb9 | 10308 | str, regno); |
252b5132 | 10309 | if (*args == 'N') |
bf12938e | 10310 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 10311 | else |
bf12938e | 10312 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 10313 | continue; |
252b5132 | 10314 | |
156c2f8b NC |
10315 | case 'H': |
10316 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
10317 | s += 2; | |
3882b010 | 10318 | if (ISDIGIT (*s)) |
156c2f8b NC |
10319 | { |
10320 | c = 0; | |
10321 | do | |
10322 | { | |
10323 | c *= 10; | |
10324 | c += *s - '0'; | |
10325 | ++s; | |
10326 | } | |
3882b010 | 10327 | while (ISDIGIT (*s)); |
156c2f8b NC |
10328 | } |
10329 | else | |
10330 | c = 8; /* Invalid sel value. */ | |
10331 | ||
10332 | if (c > 7) | |
f71d0d44 | 10333 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); |
156c2f8b NC |
10334 | ip->insn_opcode |= c; |
10335 | continue; | |
10336 | ||
60b63b72 RS |
10337 | case 'e': |
10338 | /* Must be at least one digit. */ | |
10339 | my_getExpression (&imm_expr, s); | |
10340 | check_absolute_expr (ip, &imm_expr); | |
10341 | ||
10342 | if ((unsigned long) imm_expr.X_add_number | |
10343 | > (unsigned long) OP_MASK_VECBYTE) | |
10344 | { | |
10345 | as_bad (_("bad byte vector index (%ld)"), | |
10346 | (long) imm_expr.X_add_number); | |
10347 | imm_expr.X_add_number = 0; | |
10348 | } | |
10349 | ||
bf12938e | 10350 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
10351 | imm_expr.X_op = O_absent; |
10352 | s = expr_end; | |
10353 | continue; | |
10354 | ||
10355 | case '%': | |
10356 | my_getExpression (&imm_expr, s); | |
10357 | check_absolute_expr (ip, &imm_expr); | |
10358 | ||
10359 | if ((unsigned long) imm_expr.X_add_number | |
10360 | > (unsigned long) OP_MASK_VECALIGN) | |
10361 | { | |
10362 | as_bad (_("bad byte vector index (%ld)"), | |
10363 | (long) imm_expr.X_add_number); | |
10364 | imm_expr.X_add_number = 0; | |
10365 | } | |
10366 | ||
bf12938e | 10367 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
10368 | imm_expr.X_op = O_absent; |
10369 | s = expr_end; | |
10370 | continue; | |
10371 | ||
252b5132 | 10372 | default: |
f71d0d44 | 10373 | as_bad (_("Bad char = '%c'\n"), *args); |
252b5132 RH |
10374 | internalError (); |
10375 | } | |
10376 | break; | |
10377 | } | |
10378 | /* Args don't match. */ | |
10379 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
10380 | !strcmp (insn->name, insn[1].name)) | |
10381 | { | |
10382 | ++insn; | |
10383 | s = argsStart; | |
f71d0d44 | 10384 | insn_error = _("Illegal operands"); |
252b5132 RH |
10385 | continue; |
10386 | } | |
268f6bed | 10387 | if (save_c) |
570de991 | 10388 | *(--argsStart) = save_c; |
f71d0d44 | 10389 | insn_error = _("Illegal operands"); |
252b5132 RH |
10390 | return; |
10391 | } | |
10392 | } | |
10393 | ||
0499d65b TS |
10394 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
10395 | ||
252b5132 RH |
10396 | /* This routine assembles an instruction into its binary format when |
10397 | assembling for the mips16. As a side effect, it sets one of the | |
10398 | global variables imm_reloc or offset_reloc to the type of | |
10399 | relocation to do if one of the operands is an address expression. | |
10400 | It also sets mips16_small and mips16_ext if the user explicitly | |
10401 | requested a small or extended instruction. */ | |
10402 | ||
10403 | static void | |
17a2f251 | 10404 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
10405 | { |
10406 | char *s; | |
10407 | const char *args; | |
10408 | struct mips_opcode *insn; | |
10409 | char *argsstart; | |
10410 | unsigned int regno; | |
10411 | unsigned int lastregno = 0; | |
10412 | char *s_reset; | |
d6f16593 | 10413 | size_t i; |
252b5132 RH |
10414 | |
10415 | insn_error = NULL; | |
10416 | ||
b34976b6 AM |
10417 | mips16_small = FALSE; |
10418 | mips16_ext = FALSE; | |
252b5132 | 10419 | |
3882b010 | 10420 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
10421 | ; |
10422 | switch (*s) | |
10423 | { | |
10424 | case '\0': | |
10425 | break; | |
10426 | ||
10427 | case ' ': | |
10428 | *s++ = '\0'; | |
10429 | break; | |
10430 | ||
10431 | case '.': | |
10432 | if (s[1] == 't' && s[2] == ' ') | |
10433 | { | |
10434 | *s = '\0'; | |
b34976b6 | 10435 | mips16_small = TRUE; |
252b5132 RH |
10436 | s += 3; |
10437 | break; | |
10438 | } | |
10439 | else if (s[1] == 'e' && s[2] == ' ') | |
10440 | { | |
10441 | *s = '\0'; | |
b34976b6 | 10442 | mips16_ext = TRUE; |
252b5132 RH |
10443 | s += 3; |
10444 | break; | |
10445 | } | |
10446 | /* Fall through. */ | |
10447 | default: | |
10448 | insn_error = _("unknown opcode"); | |
10449 | return; | |
10450 | } | |
10451 | ||
10452 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 10453 | mips16_small = TRUE; |
252b5132 RH |
10454 | |
10455 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
10456 | { | |
10457 | insn_error = _("unrecognized opcode"); | |
10458 | return; | |
10459 | } | |
10460 | ||
10461 | argsstart = s; | |
10462 | for (;;) | |
10463 | { | |
9b3f89ee TS |
10464 | bfd_boolean ok; |
10465 | ||
9c2799c2 | 10466 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 10467 | |
037b32b9 | 10468 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
10469 | if (! ok) |
10470 | { | |
10471 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
10472 | && strcmp (insn->name, insn[1].name) == 0) | |
10473 | { | |
10474 | ++insn; | |
10475 | continue; | |
10476 | } | |
10477 | else | |
10478 | { | |
10479 | if (!insn_error) | |
10480 | { | |
10481 | static char buf[100]; | |
10482 | sprintf (buf, | |
10483 | _("opcode not supported on this processor: %s (%s)"), | |
10484 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
10485 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
10486 | insn_error = buf; | |
10487 | } | |
10488 | return; | |
10489 | } | |
10490 | } | |
10491 | ||
1e915849 | 10492 | create_insn (ip, insn); |
252b5132 | 10493 | imm_expr.X_op = O_absent; |
f6688943 TS |
10494 | imm_reloc[0] = BFD_RELOC_UNUSED; |
10495 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
10496 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 10497 | imm2_expr.X_op = O_absent; |
252b5132 | 10498 | offset_expr.X_op = O_absent; |
f6688943 TS |
10499 | offset_reloc[0] = BFD_RELOC_UNUSED; |
10500 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
10501 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
10502 | for (args = insn->args; 1; ++args) |
10503 | { | |
10504 | int c; | |
10505 | ||
10506 | if (*s == ' ') | |
10507 | ++s; | |
10508 | ||
10509 | /* In this switch statement we call break if we did not find | |
10510 | a match, continue if we did find a match, or return if we | |
10511 | are done. */ | |
10512 | ||
10513 | c = *args; | |
10514 | switch (c) | |
10515 | { | |
10516 | case '\0': | |
10517 | if (*s == '\0') | |
10518 | { | |
10519 | /* Stuff the immediate value in now, if we can. */ | |
10520 | if (imm_expr.X_op == O_constant | |
f6688943 | 10521 | && *imm_reloc > BFD_RELOC_UNUSED |
738e5348 RS |
10522 | && *imm_reloc != BFD_RELOC_MIPS16_GOT16 |
10523 | && *imm_reloc != BFD_RELOC_MIPS16_CALL16 | |
252b5132 RH |
10524 | && insn->pinfo != INSN_MACRO) |
10525 | { | |
d6f16593 MR |
10526 | valueT tmp; |
10527 | ||
10528 | switch (*offset_reloc) | |
10529 | { | |
10530 | case BFD_RELOC_MIPS16_HI16_S: | |
10531 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
10532 | break; | |
10533 | ||
10534 | case BFD_RELOC_MIPS16_HI16: | |
10535 | tmp = imm_expr.X_add_number >> 16; | |
10536 | break; | |
10537 | ||
10538 | case BFD_RELOC_MIPS16_LO16: | |
10539 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
10540 | - 0x8000; | |
10541 | break; | |
10542 | ||
10543 | case BFD_RELOC_UNUSED: | |
10544 | tmp = imm_expr.X_add_number; | |
10545 | break; | |
10546 | ||
10547 | default: | |
10548 | internalError (); | |
10549 | } | |
10550 | *offset_reloc = BFD_RELOC_UNUSED; | |
10551 | ||
c4e7957c | 10552 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 10553 | tmp, TRUE, mips16_small, |
252b5132 RH |
10554 | mips16_ext, &ip->insn_opcode, |
10555 | &ip->use_extend, &ip->extend); | |
10556 | imm_expr.X_op = O_absent; | |
f6688943 | 10557 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
10558 | } |
10559 | ||
10560 | return; | |
10561 | } | |
10562 | break; | |
10563 | ||
10564 | case ',': | |
10565 | if (*s++ == c) | |
10566 | continue; | |
10567 | s--; | |
10568 | switch (*++args) | |
10569 | { | |
10570 | case 'v': | |
bf12938e | 10571 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
10572 | continue; |
10573 | case 'w': | |
bf12938e | 10574 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
10575 | continue; |
10576 | } | |
10577 | break; | |
10578 | ||
10579 | case '(': | |
10580 | case ')': | |
10581 | if (*s++ == c) | |
10582 | continue; | |
10583 | break; | |
10584 | ||
10585 | case 'v': | |
10586 | case 'w': | |
10587 | if (s[0] != '$') | |
10588 | { | |
10589 | if (c == 'v') | |
bf12938e | 10590 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 10591 | else |
bf12938e | 10592 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
10593 | ++args; |
10594 | continue; | |
10595 | } | |
10596 | /* Fall through. */ | |
10597 | case 'x': | |
10598 | case 'y': | |
10599 | case 'z': | |
10600 | case 'Z': | |
10601 | case '0': | |
10602 | case 'S': | |
10603 | case 'R': | |
10604 | case 'X': | |
10605 | case 'Y': | |
707bfff6 TS |
10606 | s_reset = s; |
10607 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 10608 | { |
707bfff6 | 10609 | if (c == 'v' || c == 'w') |
85b51719 | 10610 | { |
707bfff6 | 10611 | if (c == 'v') |
a9e24354 | 10612 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 10613 | else |
a9e24354 | 10614 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
10615 | ++args; |
10616 | continue; | |
85b51719 | 10617 | } |
707bfff6 | 10618 | break; |
252b5132 RH |
10619 | } |
10620 | ||
10621 | if (*s == ' ') | |
10622 | ++s; | |
10623 | if (args[1] != *s) | |
10624 | { | |
10625 | if (c == 'v' || c == 'w') | |
10626 | { | |
10627 | regno = mips16_to_32_reg_map[lastregno]; | |
10628 | s = s_reset; | |
f9419b05 | 10629 | ++args; |
252b5132 RH |
10630 | } |
10631 | } | |
10632 | ||
10633 | switch (c) | |
10634 | { | |
10635 | case 'x': | |
10636 | case 'y': | |
10637 | case 'z': | |
10638 | case 'v': | |
10639 | case 'w': | |
10640 | case 'Z': | |
10641 | regno = mips32_to_16_reg_map[regno]; | |
10642 | break; | |
10643 | ||
10644 | case '0': | |
10645 | if (regno != 0) | |
10646 | regno = ILLEGAL_REG; | |
10647 | break; | |
10648 | ||
10649 | case 'S': | |
10650 | if (regno != SP) | |
10651 | regno = ILLEGAL_REG; | |
10652 | break; | |
10653 | ||
10654 | case 'R': | |
10655 | if (regno != RA) | |
10656 | regno = ILLEGAL_REG; | |
10657 | break; | |
10658 | ||
10659 | case 'X': | |
10660 | case 'Y': | |
741fe287 MR |
10661 | if (regno == AT && mips_opts.at) |
10662 | { | |
10663 | if (mips_opts.at == ATREG) | |
10664 | as_warn (_("used $at without \".set noat\"")); | |
10665 | else | |
10666 | as_warn (_("used $%u with \".set at=$%u\""), | |
10667 | regno, mips_opts.at); | |
10668 | } | |
252b5132 RH |
10669 | break; |
10670 | ||
10671 | default: | |
10672 | internalError (); | |
10673 | } | |
10674 | ||
10675 | if (regno == ILLEGAL_REG) | |
10676 | break; | |
10677 | ||
10678 | switch (c) | |
10679 | { | |
10680 | case 'x': | |
10681 | case 'v': | |
bf12938e | 10682 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
10683 | break; |
10684 | case 'y': | |
10685 | case 'w': | |
bf12938e | 10686 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
10687 | break; |
10688 | case 'z': | |
bf12938e | 10689 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
10690 | break; |
10691 | case 'Z': | |
bf12938e | 10692 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
10693 | case '0': |
10694 | case 'S': | |
10695 | case 'R': | |
10696 | break; | |
10697 | case 'X': | |
bf12938e | 10698 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
10699 | break; |
10700 | case 'Y': | |
10701 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 10702 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
10703 | break; |
10704 | default: | |
10705 | internalError (); | |
10706 | } | |
10707 | ||
10708 | lastregno = regno; | |
10709 | continue; | |
10710 | ||
10711 | case 'P': | |
10712 | if (strncmp (s, "$pc", 3) == 0) | |
10713 | { | |
10714 | s += 3; | |
10715 | continue; | |
10716 | } | |
10717 | break; | |
10718 | ||
252b5132 RH |
10719 | case '5': |
10720 | case 'H': | |
10721 | case 'W': | |
10722 | case 'D': | |
10723 | case 'j': | |
252b5132 RH |
10724 | case 'V': |
10725 | case 'C': | |
10726 | case 'U': | |
10727 | case 'k': | |
10728 | case 'K': | |
d6f16593 MR |
10729 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
10730 | if (i > 0) | |
252b5132 | 10731 | { |
d6f16593 | 10732 | if (imm_expr.X_op != O_constant) |
252b5132 | 10733 | { |
b34976b6 | 10734 | mips16_ext = TRUE; |
b34976b6 | 10735 | ip->use_extend = TRUE; |
252b5132 | 10736 | ip->extend = 0; |
252b5132 | 10737 | } |
d6f16593 MR |
10738 | else |
10739 | { | |
10740 | /* We need to relax this instruction. */ | |
10741 | *offset_reloc = *imm_reloc; | |
10742 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
10743 | } | |
10744 | s = expr_end; | |
10745 | continue; | |
252b5132 | 10746 | } |
d6f16593 MR |
10747 | *imm_reloc = BFD_RELOC_UNUSED; |
10748 | /* Fall through. */ | |
10749 | case '<': | |
10750 | case '>': | |
10751 | case '[': | |
10752 | case ']': | |
10753 | case '4': | |
10754 | case '8': | |
10755 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
10756 | if (imm_expr.X_op == O_register) |
10757 | { | |
10758 | /* What we thought was an expression turned out to | |
10759 | be a register. */ | |
10760 | ||
10761 | if (s[0] == '(' && args[1] == '(') | |
10762 | { | |
10763 | /* It looks like the expression was omitted | |
10764 | before a register indirection, which means | |
10765 | that the expression is implicitly zero. We | |
10766 | still set up imm_expr, so that we handle | |
10767 | explicit extensions correctly. */ | |
10768 | imm_expr.X_op = O_constant; | |
10769 | imm_expr.X_add_number = 0; | |
f6688943 | 10770 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10771 | continue; |
10772 | } | |
10773 | ||
10774 | break; | |
10775 | } | |
10776 | ||
10777 | /* We need to relax this instruction. */ | |
f6688943 | 10778 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10779 | s = expr_end; |
10780 | continue; | |
10781 | ||
10782 | case 'p': | |
10783 | case 'q': | |
10784 | case 'A': | |
10785 | case 'B': | |
10786 | case 'E': | |
10787 | /* We use offset_reloc rather than imm_reloc for the PC | |
10788 | relative operands. This lets macros with both | |
10789 | immediate and address operands work correctly. */ | |
10790 | my_getExpression (&offset_expr, s); | |
10791 | ||
10792 | if (offset_expr.X_op == O_register) | |
10793 | break; | |
10794 | ||
10795 | /* We need to relax this instruction. */ | |
f6688943 | 10796 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10797 | s = expr_end; |
10798 | continue; | |
10799 | ||
10800 | case '6': /* break code */ | |
10801 | my_getExpression (&imm_expr, s); | |
10802 | check_absolute_expr (ip, &imm_expr); | |
10803 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
10804 | as_warn (_("Invalid value for `%s' (%lu)"), |
10805 | ip->insn_mo->name, | |
10806 | (unsigned long) imm_expr.X_add_number); | |
10807 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
10808 | imm_expr.X_op = O_absent; |
10809 | s = expr_end; | |
10810 | continue; | |
10811 | ||
10812 | case 'a': /* 26 bit address */ | |
10813 | my_getExpression (&offset_expr, s); | |
10814 | s = expr_end; | |
f6688943 | 10815 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
10816 | ip->insn_opcode <<= 16; |
10817 | continue; | |
10818 | ||
10819 | case 'l': /* register list for entry macro */ | |
10820 | case 'L': /* register list for exit macro */ | |
10821 | { | |
10822 | int mask; | |
10823 | ||
10824 | if (c == 'l') | |
10825 | mask = 0; | |
10826 | else | |
10827 | mask = 7 << 3; | |
10828 | while (*s != '\0') | |
10829 | { | |
707bfff6 | 10830 | unsigned int freg, reg1, reg2; |
252b5132 RH |
10831 | |
10832 | while (*s == ' ' || *s == ',') | |
10833 | ++s; | |
707bfff6 | 10834 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 10835 | freg = 0; |
707bfff6 TS |
10836 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
10837 | freg = 1; | |
252b5132 RH |
10838 | else |
10839 | { | |
707bfff6 TS |
10840 | as_bad (_("can't parse register list")); |
10841 | break; | |
252b5132 RH |
10842 | } |
10843 | if (*s == ' ') | |
10844 | ++s; | |
10845 | if (*s != '-') | |
10846 | reg2 = reg1; | |
10847 | else | |
10848 | { | |
10849 | ++s; | |
707bfff6 TS |
10850 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
10851 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 10852 | { |
707bfff6 TS |
10853 | as_bad (_("invalid register list")); |
10854 | break; | |
252b5132 RH |
10855 | } |
10856 | } | |
10857 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
10858 | { | |
10859 | mask &= ~ (7 << 3); | |
10860 | mask |= 5 << 3; | |
10861 | } | |
10862 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
10863 | { | |
10864 | mask &= ~ (7 << 3); | |
10865 | mask |= 6 << 3; | |
10866 | } | |
10867 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
10868 | mask |= (reg2 - 3) << 3; | |
10869 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
10870 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 10871 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
10872 | mask |= 1; |
10873 | else | |
10874 | { | |
10875 | as_bad (_("invalid register list")); | |
10876 | break; | |
10877 | } | |
10878 | } | |
10879 | /* The mask is filled in in the opcode table for the | |
10880 | benefit of the disassembler. We remove it before | |
10881 | applying the actual mask. */ | |
10882 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
10883 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
10884 | } | |
10885 | continue; | |
10886 | ||
0499d65b TS |
10887 | case 'm': /* Register list for save insn. */ |
10888 | case 'M': /* Register list for restore insn. */ | |
10889 | { | |
10890 | int opcode = 0; | |
10891 | int framesz = 0, seen_framesz = 0; | |
91d6fa6a | 10892 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
10893 | |
10894 | while (*s != '\0') | |
10895 | { | |
10896 | unsigned int reg1, reg2; | |
10897 | ||
10898 | SKIP_SPACE_TABS (s); | |
10899 | while (*s == ',') | |
10900 | ++s; | |
10901 | SKIP_SPACE_TABS (s); | |
10902 | ||
10903 | my_getExpression (&imm_expr, s); | |
10904 | if (imm_expr.X_op == O_constant) | |
10905 | { | |
10906 | /* Handle the frame size. */ | |
10907 | if (seen_framesz) | |
10908 | { | |
10909 | as_bad (_("more than one frame size in list")); | |
10910 | break; | |
10911 | } | |
10912 | seen_framesz = 1; | |
10913 | framesz = imm_expr.X_add_number; | |
10914 | imm_expr.X_op = O_absent; | |
10915 | s = expr_end; | |
10916 | continue; | |
10917 | } | |
10918 | ||
707bfff6 | 10919 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
10920 | { |
10921 | as_bad (_("can't parse register list")); | |
10922 | break; | |
10923 | } | |
0499d65b | 10924 | |
707bfff6 TS |
10925 | while (*s == ' ') |
10926 | ++s; | |
10927 | ||
0499d65b TS |
10928 | if (*s != '-') |
10929 | reg2 = reg1; | |
10930 | else | |
10931 | { | |
10932 | ++s; | |
707bfff6 TS |
10933 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
10934 | || reg2 < reg1) | |
0499d65b TS |
10935 | { |
10936 | as_bad (_("can't parse register list")); | |
10937 | break; | |
10938 | } | |
0499d65b TS |
10939 | } |
10940 | ||
10941 | while (reg1 <= reg2) | |
10942 | { | |
10943 | if (reg1 >= 4 && reg1 <= 7) | |
10944 | { | |
3a93f742 | 10945 | if (!seen_framesz) |
0499d65b | 10946 | /* args $a0-$a3 */ |
91d6fa6a | 10947 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
10948 | else |
10949 | /* statics $a0-$a3 */ | |
10950 | statics |= 1 << (reg1 - 4); | |
10951 | } | |
10952 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
10953 | { | |
10954 | /* $s0-$s8 */ | |
10955 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
10956 | } | |
10957 | else if (reg1 == 31) | |
10958 | { | |
10959 | /* Add $ra to insn. */ | |
10960 | opcode |= 0x40; | |
10961 | } | |
10962 | else | |
10963 | { | |
10964 | as_bad (_("unexpected register in list")); | |
10965 | break; | |
10966 | } | |
10967 | if (++reg1 == 24) | |
10968 | reg1 = 30; | |
10969 | } | |
10970 | } | |
10971 | ||
10972 | /* Encode args/statics combination. */ | |
91d6fa6a | 10973 | if (nargs & statics) |
0499d65b | 10974 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 10975 | else if (nargs == 0xf) |
0499d65b TS |
10976 | /* All $a0-$a3 are args. */ |
10977 | opcode |= MIPS16_ALL_ARGS << 16; | |
10978 | else if (statics == 0xf) | |
10979 | /* All $a0-$a3 are statics. */ | |
10980 | opcode |= MIPS16_ALL_STATICS << 16; | |
10981 | else | |
10982 | { | |
10983 | int narg = 0, nstat = 0; | |
10984 | ||
10985 | /* Count arg registers. */ | |
91d6fa6a | 10986 | while (nargs & 0x1) |
0499d65b | 10987 | { |
91d6fa6a | 10988 | nargs >>= 1; |
0499d65b TS |
10989 | narg++; |
10990 | } | |
91d6fa6a | 10991 | if (nargs != 0) |
0499d65b TS |
10992 | as_bad (_("invalid arg register list")); |
10993 | ||
10994 | /* Count static registers. */ | |
10995 | while (statics & 0x8) | |
10996 | { | |
10997 | statics = (statics << 1) & 0xf; | |
10998 | nstat++; | |
10999 | } | |
11000 | if (statics != 0) | |
11001 | as_bad (_("invalid static register list")); | |
11002 | ||
11003 | /* Encode args/statics. */ | |
11004 | opcode |= ((narg << 2) | nstat) << 16; | |
11005 | } | |
11006 | ||
11007 | /* Encode $s0/$s1. */ | |
11008 | if (sregs & (1 << 0)) /* $s0 */ | |
11009 | opcode |= 0x20; | |
11010 | if (sregs & (1 << 1)) /* $s1 */ | |
11011 | opcode |= 0x10; | |
11012 | sregs >>= 2; | |
11013 | ||
11014 | if (sregs != 0) | |
11015 | { | |
11016 | /* Count regs $s2-$s8. */ | |
11017 | int nsreg = 0; | |
11018 | while (sregs & 1) | |
11019 | { | |
11020 | sregs >>= 1; | |
11021 | nsreg++; | |
11022 | } | |
11023 | if (sregs != 0) | |
11024 | as_bad (_("invalid static register list")); | |
11025 | /* Encode $s2-$s8. */ | |
11026 | opcode |= nsreg << 24; | |
11027 | } | |
11028 | ||
11029 | /* Encode frame size. */ | |
11030 | if (!seen_framesz) | |
11031 | as_bad (_("missing frame size")); | |
11032 | else if ((framesz & 7) != 0 || framesz < 0 | |
11033 | || framesz > 0xff * 8) | |
11034 | as_bad (_("invalid frame size")); | |
11035 | else if (framesz != 128 || (opcode >> 16) != 0) | |
11036 | { | |
11037 | framesz /= 8; | |
11038 | opcode |= (((framesz & 0xf0) << 16) | |
11039 | | (framesz & 0x0f)); | |
11040 | } | |
11041 | ||
11042 | /* Finally build the instruction. */ | |
11043 | if ((opcode >> 16) != 0 || framesz == 0) | |
11044 | { | |
11045 | ip->use_extend = TRUE; | |
11046 | ip->extend = opcode >> 16; | |
11047 | } | |
11048 | ip->insn_opcode |= opcode & 0x7f; | |
11049 | } | |
11050 | continue; | |
11051 | ||
252b5132 RH |
11052 | case 'e': /* extend code */ |
11053 | my_getExpression (&imm_expr, s); | |
11054 | check_absolute_expr (ip, &imm_expr); | |
11055 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
11056 | { | |
11057 | as_warn (_("Invalid value for `%s' (%lu)"), | |
11058 | ip->insn_mo->name, | |
11059 | (unsigned long) imm_expr.X_add_number); | |
11060 | imm_expr.X_add_number &= 0x7ff; | |
11061 | } | |
11062 | ip->insn_opcode |= imm_expr.X_add_number; | |
11063 | imm_expr.X_op = O_absent; | |
11064 | s = expr_end; | |
11065 | continue; | |
11066 | ||
11067 | default: | |
11068 | internalError (); | |
11069 | } | |
11070 | break; | |
11071 | } | |
11072 | ||
11073 | /* Args don't match. */ | |
11074 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
11075 | strcmp (insn->name, insn[1].name) == 0) | |
11076 | { | |
11077 | ++insn; | |
11078 | s = argsstart; | |
11079 | continue; | |
11080 | } | |
11081 | ||
11082 | insn_error = _("illegal operands"); | |
11083 | ||
11084 | return; | |
11085 | } | |
11086 | } | |
11087 | ||
11088 | /* This structure holds information we know about a mips16 immediate | |
11089 | argument type. */ | |
11090 | ||
e972090a NC |
11091 | struct mips16_immed_operand |
11092 | { | |
252b5132 RH |
11093 | /* The type code used in the argument string in the opcode table. */ |
11094 | int type; | |
11095 | /* The number of bits in the short form of the opcode. */ | |
11096 | int nbits; | |
11097 | /* The number of bits in the extended form of the opcode. */ | |
11098 | int extbits; | |
11099 | /* The amount by which the short form is shifted when it is used; | |
11100 | for example, the sw instruction has a shift count of 2. */ | |
11101 | int shift; | |
11102 | /* The amount by which the short form is shifted when it is stored | |
11103 | into the instruction code. */ | |
11104 | int op_shift; | |
11105 | /* Non-zero if the short form is unsigned. */ | |
11106 | int unsp; | |
11107 | /* Non-zero if the extended form is unsigned. */ | |
11108 | int extu; | |
11109 | /* Non-zero if the value is PC relative. */ | |
11110 | int pcrel; | |
11111 | }; | |
11112 | ||
11113 | /* The mips16 immediate operand types. */ | |
11114 | ||
11115 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
11116 | { | |
11117 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
11118 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
11119 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
11120 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
11121 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
11122 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
11123 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
11124 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
11125 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
11126 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
11127 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
11128 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
11129 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
11130 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
11131 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
11132 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
11133 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
11134 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
11135 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
11136 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
11137 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
11138 | }; | |
11139 | ||
11140 | #define MIPS16_NUM_IMMED \ | |
11141 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
11142 | ||
11143 | /* Handle a mips16 instruction with an immediate value. This or's the | |
11144 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
11145 | whether an extended value is needed; if one is needed, it sets | |
11146 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
11147 | If SMALL is true, an unextended opcode was explicitly requested. | |
11148 | If EXT is true, an extended opcode was explicitly requested. If | |
11149 | WARN is true, warn if EXT does not match reality. */ | |
11150 | ||
11151 | static void | |
17a2f251 TS |
11152 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
11153 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
11154 | unsigned long *insn, bfd_boolean *use_extend, | |
11155 | unsigned short *extend) | |
252b5132 | 11156 | { |
3994f87e | 11157 | const struct mips16_immed_operand *op; |
252b5132 | 11158 | int mintiny, maxtiny; |
b34976b6 | 11159 | bfd_boolean needext; |
252b5132 RH |
11160 | |
11161 | op = mips16_immed_operands; | |
11162 | while (op->type != type) | |
11163 | { | |
11164 | ++op; | |
9c2799c2 | 11165 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
11166 | } |
11167 | ||
11168 | if (op->unsp) | |
11169 | { | |
11170 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
11171 | { | |
11172 | mintiny = 1; | |
11173 | maxtiny = 1 << op->nbits; | |
11174 | } | |
11175 | else | |
11176 | { | |
11177 | mintiny = 0; | |
11178 | maxtiny = (1 << op->nbits) - 1; | |
11179 | } | |
11180 | } | |
11181 | else | |
11182 | { | |
11183 | mintiny = - (1 << (op->nbits - 1)); | |
11184 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
11185 | } | |
11186 | ||
11187 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
11188 | if (type == 'p' || type == 'q') | |
11189 | val /= 2; | |
11190 | ||
11191 | if ((val & ((1 << op->shift) - 1)) != 0 | |
11192 | || val < (mintiny << op->shift) | |
11193 | || val > (maxtiny << op->shift)) | |
b34976b6 | 11194 | needext = TRUE; |
252b5132 | 11195 | else |
b34976b6 | 11196 | needext = FALSE; |
252b5132 RH |
11197 | |
11198 | if (warn && ext && ! needext) | |
beae10d5 KH |
11199 | as_warn_where (file, line, |
11200 | _("extended operand requested but not required")); | |
252b5132 RH |
11201 | if (small && needext) |
11202 | as_bad_where (file, line, _("invalid unextended operand value")); | |
11203 | ||
11204 | if (small || (! ext && ! needext)) | |
11205 | { | |
11206 | int insnval; | |
11207 | ||
b34976b6 | 11208 | *use_extend = FALSE; |
252b5132 RH |
11209 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
11210 | insnval <<= op->op_shift; | |
11211 | *insn |= insnval; | |
11212 | } | |
11213 | else | |
11214 | { | |
11215 | long minext, maxext; | |
11216 | int extval; | |
11217 | ||
11218 | if (op->extu) | |
11219 | { | |
11220 | minext = 0; | |
11221 | maxext = (1 << op->extbits) - 1; | |
11222 | } | |
11223 | else | |
11224 | { | |
11225 | minext = - (1 << (op->extbits - 1)); | |
11226 | maxext = (1 << (op->extbits - 1)) - 1; | |
11227 | } | |
11228 | if (val < minext || val > maxext) | |
11229 | as_bad_where (file, line, | |
11230 | _("operand value out of range for instruction")); | |
11231 | ||
b34976b6 | 11232 | *use_extend = TRUE; |
252b5132 RH |
11233 | if (op->extbits == 16) |
11234 | { | |
11235 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
11236 | val &= 0x1f; | |
11237 | } | |
11238 | else if (op->extbits == 15) | |
11239 | { | |
11240 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
11241 | val &= 0xf; | |
11242 | } | |
11243 | else | |
11244 | { | |
11245 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
11246 | val = 0; | |
11247 | } | |
11248 | ||
11249 | *extend = (unsigned short) extval; | |
11250 | *insn |= val; | |
11251 | } | |
11252 | } | |
11253 | \f | |
d6f16593 | 11254 | struct percent_op_match |
ad8d3bb3 | 11255 | { |
5e0116d5 RS |
11256 | const char *str; |
11257 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
11258 | }; |
11259 | ||
11260 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 11261 | { |
5e0116d5 | 11262 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 11263 | #ifdef OBJ_ELF |
5e0116d5 RS |
11264 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
11265 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
11266 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
11267 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
11268 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
11269 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
11270 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
11271 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
11272 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
11273 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
11274 | {"%half", BFD_RELOC_16}, | |
11275 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
11276 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
11277 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
11278 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
11279 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
11280 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
11281 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
11282 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
11283 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
11284 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 11285 | #endif |
5e0116d5 | 11286 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
11287 | }; |
11288 | ||
d6f16593 MR |
11289 | static const struct percent_op_match mips16_percent_op[] = |
11290 | { | |
11291 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
11292 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
11293 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
11294 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d6f16593 MR |
11295 | {"%hi", BFD_RELOC_MIPS16_HI16_S} |
11296 | }; | |
11297 | ||
252b5132 | 11298 | |
5e0116d5 RS |
11299 | /* Return true if *STR points to a relocation operator. When returning true, |
11300 | move *STR over the operator and store its relocation code in *RELOC. | |
11301 | Leave both *STR and *RELOC alone when returning false. */ | |
11302 | ||
11303 | static bfd_boolean | |
17a2f251 | 11304 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 11305 | { |
d6f16593 MR |
11306 | const struct percent_op_match *percent_op; |
11307 | size_t limit, i; | |
11308 | ||
11309 | if (mips_opts.mips16) | |
11310 | { | |
11311 | percent_op = mips16_percent_op; | |
11312 | limit = ARRAY_SIZE (mips16_percent_op); | |
11313 | } | |
11314 | else | |
11315 | { | |
11316 | percent_op = mips_percent_op; | |
11317 | limit = ARRAY_SIZE (mips_percent_op); | |
11318 | } | |
76b3015f | 11319 | |
d6f16593 | 11320 | for (i = 0; i < limit; i++) |
5e0116d5 | 11321 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 11322 | { |
3f98094e DJ |
11323 | int len = strlen (percent_op[i].str); |
11324 | ||
11325 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
11326 | continue; | |
11327 | ||
5e0116d5 RS |
11328 | *str += strlen (percent_op[i].str); |
11329 | *reloc = percent_op[i].reloc; | |
394f9b3a | 11330 | |
5e0116d5 RS |
11331 | /* Check whether the output BFD supports this relocation. |
11332 | If not, issue an error and fall back on something safe. */ | |
11333 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 11334 | { |
20203fb9 | 11335 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 11336 | percent_op[i].str); |
01a3f561 | 11337 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 11338 | } |
5e0116d5 | 11339 | return TRUE; |
394f9b3a | 11340 | } |
5e0116d5 | 11341 | return FALSE; |
394f9b3a | 11342 | } |
ad8d3bb3 | 11343 | |
ad8d3bb3 | 11344 | |
5e0116d5 RS |
11345 | /* Parse string STR as a 16-bit relocatable operand. Store the |
11346 | expression in *EP and the relocations in the array starting | |
11347 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 11348 | |
01a3f561 | 11349 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 11350 | |
5e0116d5 | 11351 | static size_t |
17a2f251 TS |
11352 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
11353 | char *str) | |
ad8d3bb3 | 11354 | { |
5e0116d5 RS |
11355 | bfd_reloc_code_real_type reversed_reloc[3]; |
11356 | size_t reloc_index, i; | |
09b8f35a RS |
11357 | int crux_depth, str_depth; |
11358 | char *crux; | |
5e0116d5 RS |
11359 | |
11360 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
11361 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
11362 | of the main expression and with CRUX_DEPTH containing the number | |
11363 | of open brackets at that point. */ | |
11364 | reloc_index = -1; | |
11365 | str_depth = 0; | |
11366 | do | |
fb1b3232 | 11367 | { |
09b8f35a RS |
11368 | reloc_index++; |
11369 | crux = str; | |
11370 | crux_depth = str_depth; | |
11371 | ||
11372 | /* Skip over whitespace and brackets, keeping count of the number | |
11373 | of brackets. */ | |
11374 | while (*str == ' ' || *str == '\t' || *str == '(') | |
11375 | if (*str++ == '(') | |
11376 | str_depth++; | |
5e0116d5 | 11377 | } |
09b8f35a RS |
11378 | while (*str == '%' |
11379 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
11380 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 11381 | |
09b8f35a | 11382 | my_getExpression (ep, crux); |
5e0116d5 | 11383 | str = expr_end; |
394f9b3a | 11384 | |
5e0116d5 | 11385 | /* Match every open bracket. */ |
09b8f35a | 11386 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 11387 | if (*str++ == ')') |
09b8f35a | 11388 | crux_depth--; |
394f9b3a | 11389 | |
09b8f35a | 11390 | if (crux_depth > 0) |
20203fb9 | 11391 | as_bad (_("unclosed '('")); |
394f9b3a | 11392 | |
5e0116d5 | 11393 | expr_end = str; |
252b5132 | 11394 | |
01a3f561 | 11395 | if (reloc_index != 0) |
64bdfcaf RS |
11396 | { |
11397 | prev_reloc_op_frag = frag_now; | |
11398 | for (i = 0; i < reloc_index; i++) | |
11399 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
11400 | } | |
fb1b3232 | 11401 | |
5e0116d5 | 11402 | return reloc_index; |
252b5132 RH |
11403 | } |
11404 | ||
11405 | static void | |
17a2f251 | 11406 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
11407 | { |
11408 | char *save_in; | |
11409 | ||
11410 | save_in = input_line_pointer; | |
11411 | input_line_pointer = str; | |
11412 | expression (ep); | |
11413 | expr_end = input_line_pointer; | |
11414 | input_line_pointer = save_in; | |
252b5132 RH |
11415 | } |
11416 | ||
252b5132 | 11417 | char * |
17a2f251 | 11418 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 11419 | { |
499ac353 | 11420 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
11421 | } |
11422 | ||
11423 | void | |
17a2f251 | 11424 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
11425 | { |
11426 | if (target_big_endian) | |
11427 | number_to_chars_bigendian (buf, val, n); | |
11428 | else | |
11429 | number_to_chars_littleendian (buf, val, n); | |
11430 | } | |
11431 | \f | |
ae948b86 | 11432 | #ifdef OBJ_ELF |
e013f690 TS |
11433 | static int support_64bit_objects(void) |
11434 | { | |
11435 | const char **list, **l; | |
aa3d8fdf | 11436 | int yes; |
e013f690 TS |
11437 | |
11438 | list = bfd_target_list (); | |
11439 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
11440 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
11441 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 11442 | break; |
aa3d8fdf | 11443 | yes = (*l != NULL); |
e013f690 | 11444 | free (list); |
aa3d8fdf | 11445 | return yes; |
e013f690 | 11446 | } |
ae948b86 | 11447 | #endif /* OBJ_ELF */ |
e013f690 | 11448 | |
78849248 | 11449 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 11450 | |
23fce1e3 NC |
11451 | enum options |
11452 | { | |
11453 | OPTION_MARCH = OPTION_MD_BASE, | |
11454 | OPTION_MTUNE, | |
11455 | OPTION_MIPS1, | |
11456 | OPTION_MIPS2, | |
11457 | OPTION_MIPS3, | |
11458 | OPTION_MIPS4, | |
11459 | OPTION_MIPS5, | |
11460 | OPTION_MIPS32, | |
11461 | OPTION_MIPS64, | |
11462 | OPTION_MIPS32R2, | |
11463 | OPTION_MIPS64R2, | |
11464 | OPTION_MIPS16, | |
11465 | OPTION_NO_MIPS16, | |
11466 | OPTION_MIPS3D, | |
11467 | OPTION_NO_MIPS3D, | |
11468 | OPTION_MDMX, | |
11469 | OPTION_NO_MDMX, | |
11470 | OPTION_DSP, | |
11471 | OPTION_NO_DSP, | |
11472 | OPTION_MT, | |
11473 | OPTION_NO_MT, | |
11474 | OPTION_SMARTMIPS, | |
11475 | OPTION_NO_SMARTMIPS, | |
11476 | OPTION_DSPR2, | |
11477 | OPTION_NO_DSPR2, | |
11478 | OPTION_COMPAT_ARCH_BASE, | |
11479 | OPTION_M4650, | |
11480 | OPTION_NO_M4650, | |
11481 | OPTION_M4010, | |
11482 | OPTION_NO_M4010, | |
11483 | OPTION_M4100, | |
11484 | OPTION_NO_M4100, | |
11485 | OPTION_M3900, | |
11486 | OPTION_NO_M3900, | |
11487 | OPTION_M7000_HILO_FIX, | |
6a32d874 CM |
11488 | OPTION_MNO_7000_HILO_FIX, |
11489 | OPTION_FIX_24K, | |
11490 | OPTION_NO_FIX_24K, | |
c67a084a NC |
11491 | OPTION_FIX_LOONGSON2F_JUMP, |
11492 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
11493 | OPTION_FIX_LOONGSON2F_NOP, | |
11494 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
23fce1e3 NC |
11495 | OPTION_FIX_VR4120, |
11496 | OPTION_NO_FIX_VR4120, | |
11497 | OPTION_FIX_VR4130, | |
11498 | OPTION_NO_FIX_VR4130, | |
d954098f DD |
11499 | OPTION_FIX_CN63XXP1, |
11500 | OPTION_NO_FIX_CN63XXP1, | |
23fce1e3 NC |
11501 | OPTION_TRAP, |
11502 | OPTION_BREAK, | |
11503 | OPTION_EB, | |
11504 | OPTION_EL, | |
11505 | OPTION_FP32, | |
11506 | OPTION_GP32, | |
11507 | OPTION_CONSTRUCT_FLOATS, | |
11508 | OPTION_NO_CONSTRUCT_FLOATS, | |
11509 | OPTION_FP64, | |
11510 | OPTION_GP64, | |
11511 | OPTION_RELAX_BRANCH, | |
11512 | OPTION_NO_RELAX_BRANCH, | |
11513 | OPTION_MSHARED, | |
11514 | OPTION_MNO_SHARED, | |
11515 | OPTION_MSYM32, | |
11516 | OPTION_MNO_SYM32, | |
11517 | OPTION_SOFT_FLOAT, | |
11518 | OPTION_HARD_FLOAT, | |
11519 | OPTION_SINGLE_FLOAT, | |
11520 | OPTION_DOUBLE_FLOAT, | |
11521 | OPTION_32, | |
11522 | #ifdef OBJ_ELF | |
11523 | OPTION_CALL_SHARED, | |
11524 | OPTION_CALL_NONPIC, | |
11525 | OPTION_NON_SHARED, | |
11526 | OPTION_XGOT, | |
11527 | OPTION_MABI, | |
11528 | OPTION_N32, | |
11529 | OPTION_64, | |
11530 | OPTION_MDEBUG, | |
11531 | OPTION_NO_MDEBUG, | |
11532 | OPTION_PDR, | |
11533 | OPTION_NO_PDR, | |
11534 | OPTION_MVXWORKS_PIC, | |
11535 | #endif /* OBJ_ELF */ | |
11536 | OPTION_END_OF_ENUM | |
11537 | }; | |
11538 | ||
e972090a NC |
11539 | struct option md_longopts[] = |
11540 | { | |
f9b4148d | 11541 | /* Options which specify architecture. */ |
f9b4148d | 11542 | {"march", required_argument, NULL, OPTION_MARCH}, |
f9b4148d | 11543 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
252b5132 RH |
11544 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
11545 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
252b5132 | 11546 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
252b5132 | 11547 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
252b5132 | 11548 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
ae948b86 | 11549 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
ae948b86 | 11550 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
ae948b86 | 11551 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d | 11552 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
5f74bc13 | 11553 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
f9b4148d CD |
11554 | |
11555 | /* Options which specify Application Specific Extensions (ASEs). */ | |
f9b4148d | 11556 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
f9b4148d | 11557 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f9b4148d | 11558 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
f9b4148d | 11559 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
f9b4148d | 11560 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
f9b4148d | 11561 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
74cd071d | 11562 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
74cd071d | 11563 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
ef2e4d86 | 11564 | {"mmt", no_argument, NULL, OPTION_MT}, |
ef2e4d86 | 11565 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
e16bfa71 | 11566 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
e16bfa71 | 11567 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
8b082fb1 | 11568 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
8b082fb1 | 11569 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
f9b4148d CD |
11570 | |
11571 | /* Old-style architecture options. Don't add more of these. */ | |
f9b4148d | 11572 | {"m4650", no_argument, NULL, OPTION_M4650}, |
f9b4148d | 11573 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
f9b4148d | 11574 | {"m4010", no_argument, NULL, OPTION_M4010}, |
f9b4148d | 11575 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
f9b4148d | 11576 | {"m4100", no_argument, NULL, OPTION_M4100}, |
f9b4148d | 11577 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
f9b4148d | 11578 | {"m3900", no_argument, NULL, OPTION_M3900}, |
f9b4148d CD |
11579 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
11580 | ||
11581 | /* Options which enable bug fixes. */ | |
f9b4148d | 11582 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
f9b4148d CD |
11583 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
11584 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
c67a084a NC |
11585 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
11586 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
11587 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
11588 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
d766e8ec RS |
11589 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
11590 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
11591 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
11592 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
6a32d874 CM |
11593 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
11594 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
d954098f DD |
11595 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
11596 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
f9b4148d CD |
11597 | |
11598 | /* Miscellaneous options. */ | |
252b5132 RH |
11599 | {"trap", no_argument, NULL, OPTION_TRAP}, |
11600 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
252b5132 RH |
11601 | {"break", no_argument, NULL, OPTION_BREAK}, |
11602 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
252b5132 | 11603 | {"EB", no_argument, NULL, OPTION_EB}, |
252b5132 | 11604 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 11605 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
c97ef257 | 11606 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
119d663a | 11607 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
119d663a | 11608 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
316f5878 | 11609 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
ae948b86 | 11610 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
4a6a3df4 AO |
11611 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
11612 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
11613 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
11614 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
11615 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
11616 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
11617 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
11618 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
037b32b9 AN |
11619 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
11620 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
23fce1e3 NC |
11621 | |
11622 | /* Strictly speaking this next option is ELF specific, | |
11623 | but we allow it for other ports as well in order to | |
11624 | make testing easier. */ | |
11625 | {"32", no_argument, NULL, OPTION_32}, | |
037b32b9 | 11626 | |
f9b4148d | 11627 | /* ELF-specific options. */ |
156c2f8b | 11628 | #ifdef OBJ_ELF |
156c2f8b NC |
11629 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
11630 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
861fb55a | 11631 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
156c2f8b NC |
11632 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
11633 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
ae948b86 | 11634 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e013f690 | 11635 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b | 11636 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a | 11637 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
ecb4347a | 11638 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
dcd410fe | 11639 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
dcd410fe | 11640 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
0a44bf69 | 11641 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
ae948b86 | 11642 | #endif /* OBJ_ELF */ |
f9b4148d | 11643 | |
252b5132 RH |
11644 | {NULL, no_argument, NULL, 0} |
11645 | }; | |
156c2f8b | 11646 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 11647 | |
316f5878 RS |
11648 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
11649 | NEW_VALUE. Warn if another value was already specified. Note: | |
11650 | we have to defer parsing the -march and -mtune arguments in order | |
11651 | to handle 'from-abi' correctly, since the ABI might be specified | |
11652 | in a later argument. */ | |
11653 | ||
11654 | static void | |
17a2f251 | 11655 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
11656 | { |
11657 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
11658 | as_warn (_("A different %s was already specified, is now %s"), | |
11659 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
11660 | new_value); | |
11661 | ||
11662 | *string_ptr = new_value; | |
11663 | } | |
11664 | ||
252b5132 | 11665 | int |
17a2f251 | 11666 | md_parse_option (int c, char *arg) |
252b5132 RH |
11667 | { |
11668 | switch (c) | |
11669 | { | |
119d663a NC |
11670 | case OPTION_CONSTRUCT_FLOATS: |
11671 | mips_disable_float_construction = 0; | |
11672 | break; | |
bdaaa2e1 | 11673 | |
119d663a NC |
11674 | case OPTION_NO_CONSTRUCT_FLOATS: |
11675 | mips_disable_float_construction = 1; | |
11676 | break; | |
bdaaa2e1 | 11677 | |
252b5132 RH |
11678 | case OPTION_TRAP: |
11679 | mips_trap = 1; | |
11680 | break; | |
11681 | ||
11682 | case OPTION_BREAK: | |
11683 | mips_trap = 0; | |
11684 | break; | |
11685 | ||
11686 | case OPTION_EB: | |
11687 | target_big_endian = 1; | |
11688 | break; | |
11689 | ||
11690 | case OPTION_EL: | |
11691 | target_big_endian = 0; | |
11692 | break; | |
11693 | ||
11694 | case 'O': | |
4ffff32f TS |
11695 | if (arg == NULL) |
11696 | mips_optimize = 1; | |
11697 | else if (arg[0] == '0') | |
11698 | mips_optimize = 0; | |
11699 | else if (arg[0] == '1') | |
252b5132 RH |
11700 | mips_optimize = 1; |
11701 | else | |
11702 | mips_optimize = 2; | |
11703 | break; | |
11704 | ||
11705 | case 'g': | |
11706 | if (arg == NULL) | |
11707 | mips_debug = 2; | |
11708 | else | |
11709 | mips_debug = atoi (arg); | |
252b5132 RH |
11710 | break; |
11711 | ||
11712 | case OPTION_MIPS1: | |
316f5878 | 11713 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
11714 | break; |
11715 | ||
11716 | case OPTION_MIPS2: | |
316f5878 | 11717 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
11718 | break; |
11719 | ||
11720 | case OPTION_MIPS3: | |
316f5878 | 11721 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
11722 | break; |
11723 | ||
11724 | case OPTION_MIPS4: | |
316f5878 | 11725 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
11726 | break; |
11727 | ||
84ea6cf2 | 11728 | case OPTION_MIPS5: |
316f5878 | 11729 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
11730 | break; |
11731 | ||
e7af610e | 11732 | case OPTION_MIPS32: |
316f5878 | 11733 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
11734 | break; |
11735 | ||
af7ee8bf CD |
11736 | case OPTION_MIPS32R2: |
11737 | file_mips_isa = ISA_MIPS32R2; | |
11738 | break; | |
11739 | ||
5f74bc13 CD |
11740 | case OPTION_MIPS64R2: |
11741 | file_mips_isa = ISA_MIPS64R2; | |
11742 | break; | |
11743 | ||
84ea6cf2 | 11744 | case OPTION_MIPS64: |
316f5878 | 11745 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
11746 | break; |
11747 | ||
ec68c924 | 11748 | case OPTION_MTUNE: |
316f5878 RS |
11749 | mips_set_option_string (&mips_tune_string, arg); |
11750 | break; | |
ec68c924 | 11751 | |
316f5878 RS |
11752 | case OPTION_MARCH: |
11753 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
11754 | break; |
11755 | ||
11756 | case OPTION_M4650: | |
316f5878 RS |
11757 | mips_set_option_string (&mips_arch_string, "4650"); |
11758 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
11759 | break; |
11760 | ||
11761 | case OPTION_NO_M4650: | |
11762 | break; | |
11763 | ||
11764 | case OPTION_M4010: | |
316f5878 RS |
11765 | mips_set_option_string (&mips_arch_string, "4010"); |
11766 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
11767 | break; |
11768 | ||
11769 | case OPTION_NO_M4010: | |
11770 | break; | |
11771 | ||
11772 | case OPTION_M4100: | |
316f5878 RS |
11773 | mips_set_option_string (&mips_arch_string, "4100"); |
11774 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
11775 | break; |
11776 | ||
11777 | case OPTION_NO_M4100: | |
11778 | break; | |
11779 | ||
252b5132 | 11780 | case OPTION_M3900: |
316f5878 RS |
11781 | mips_set_option_string (&mips_arch_string, "3900"); |
11782 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 11783 | break; |
bdaaa2e1 | 11784 | |
252b5132 RH |
11785 | case OPTION_NO_M3900: |
11786 | break; | |
11787 | ||
deec1734 CD |
11788 | case OPTION_MDMX: |
11789 | mips_opts.ase_mdmx = 1; | |
11790 | break; | |
11791 | ||
11792 | case OPTION_NO_MDMX: | |
11793 | mips_opts.ase_mdmx = 0; | |
11794 | break; | |
11795 | ||
74cd071d CF |
11796 | case OPTION_DSP: |
11797 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 11798 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
11799 | break; |
11800 | ||
11801 | case OPTION_NO_DSP: | |
8b082fb1 TS |
11802 | mips_opts.ase_dsp = 0; |
11803 | mips_opts.ase_dspr2 = 0; | |
11804 | break; | |
11805 | ||
11806 | case OPTION_DSPR2: | |
11807 | mips_opts.ase_dspr2 = 1; | |
11808 | mips_opts.ase_dsp = 1; | |
11809 | break; | |
11810 | ||
11811 | case OPTION_NO_DSPR2: | |
11812 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
11813 | mips_opts.ase_dsp = 0; |
11814 | break; | |
11815 | ||
ef2e4d86 CF |
11816 | case OPTION_MT: |
11817 | mips_opts.ase_mt = 1; | |
11818 | break; | |
11819 | ||
11820 | case OPTION_NO_MT: | |
11821 | mips_opts.ase_mt = 0; | |
11822 | break; | |
11823 | ||
252b5132 RH |
11824 | case OPTION_MIPS16: |
11825 | mips_opts.mips16 = 1; | |
7d10b47d | 11826 | mips_no_prev_insn (); |
252b5132 RH |
11827 | break; |
11828 | ||
11829 | case OPTION_NO_MIPS16: | |
11830 | mips_opts.mips16 = 0; | |
7d10b47d | 11831 | mips_no_prev_insn (); |
252b5132 RH |
11832 | break; |
11833 | ||
1f25f5d3 CD |
11834 | case OPTION_MIPS3D: |
11835 | mips_opts.ase_mips3d = 1; | |
11836 | break; | |
11837 | ||
11838 | case OPTION_NO_MIPS3D: | |
11839 | mips_opts.ase_mips3d = 0; | |
11840 | break; | |
11841 | ||
e16bfa71 TS |
11842 | case OPTION_SMARTMIPS: |
11843 | mips_opts.ase_smartmips = 1; | |
11844 | break; | |
11845 | ||
11846 | case OPTION_NO_SMARTMIPS: | |
11847 | mips_opts.ase_smartmips = 0; | |
11848 | break; | |
11849 | ||
6a32d874 CM |
11850 | case OPTION_FIX_24K: |
11851 | mips_fix_24k = 1; | |
11852 | break; | |
11853 | ||
11854 | case OPTION_NO_FIX_24K: | |
11855 | mips_fix_24k = 0; | |
11856 | break; | |
11857 | ||
c67a084a NC |
11858 | case OPTION_FIX_LOONGSON2F_JUMP: |
11859 | mips_fix_loongson2f_jump = TRUE; | |
11860 | break; | |
11861 | ||
11862 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
11863 | mips_fix_loongson2f_jump = FALSE; | |
11864 | break; | |
11865 | ||
11866 | case OPTION_FIX_LOONGSON2F_NOP: | |
11867 | mips_fix_loongson2f_nop = TRUE; | |
11868 | break; | |
11869 | ||
11870 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
11871 | mips_fix_loongson2f_nop = FALSE; | |
11872 | break; | |
11873 | ||
d766e8ec RS |
11874 | case OPTION_FIX_VR4120: |
11875 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
11876 | break; |
11877 | ||
d766e8ec RS |
11878 | case OPTION_NO_FIX_VR4120: |
11879 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
11880 | break; |
11881 | ||
7d8e00cf RS |
11882 | case OPTION_FIX_VR4130: |
11883 | mips_fix_vr4130 = 1; | |
11884 | break; | |
11885 | ||
11886 | case OPTION_NO_FIX_VR4130: | |
11887 | mips_fix_vr4130 = 0; | |
11888 | break; | |
11889 | ||
d954098f DD |
11890 | case OPTION_FIX_CN63XXP1: |
11891 | mips_fix_cn63xxp1 = TRUE; | |
11892 | break; | |
11893 | ||
11894 | case OPTION_NO_FIX_CN63XXP1: | |
11895 | mips_fix_cn63xxp1 = FALSE; | |
11896 | break; | |
11897 | ||
4a6a3df4 AO |
11898 | case OPTION_RELAX_BRANCH: |
11899 | mips_relax_branch = 1; | |
11900 | break; | |
11901 | ||
11902 | case OPTION_NO_RELAX_BRANCH: | |
11903 | mips_relax_branch = 0; | |
11904 | break; | |
11905 | ||
aa6975fb ILT |
11906 | case OPTION_MSHARED: |
11907 | mips_in_shared = TRUE; | |
11908 | break; | |
11909 | ||
11910 | case OPTION_MNO_SHARED: | |
11911 | mips_in_shared = FALSE; | |
11912 | break; | |
11913 | ||
aed1a261 RS |
11914 | case OPTION_MSYM32: |
11915 | mips_opts.sym32 = TRUE; | |
11916 | break; | |
11917 | ||
11918 | case OPTION_MNO_SYM32: | |
11919 | mips_opts.sym32 = FALSE; | |
11920 | break; | |
11921 | ||
0f074f60 | 11922 | #ifdef OBJ_ELF |
252b5132 RH |
11923 | /* When generating ELF code, we permit -KPIC and -call_shared to |
11924 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
11925 | intended to be compatible with Irix 5. */ | |
11926 | case OPTION_CALL_SHARED: | |
f43abd2b | 11927 | if (!IS_ELF) |
252b5132 RH |
11928 | { |
11929 | as_bad (_("-call_shared is supported only for ELF format")); | |
11930 | return 0; | |
11931 | } | |
11932 | mips_pic = SVR4_PIC; | |
143d77c5 | 11933 | mips_abicalls = TRUE; |
252b5132 RH |
11934 | break; |
11935 | ||
861fb55a DJ |
11936 | case OPTION_CALL_NONPIC: |
11937 | if (!IS_ELF) | |
11938 | { | |
11939 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
11940 | return 0; | |
11941 | } | |
11942 | mips_pic = NO_PIC; | |
11943 | mips_abicalls = TRUE; | |
11944 | break; | |
11945 | ||
252b5132 | 11946 | case OPTION_NON_SHARED: |
f43abd2b | 11947 | if (!IS_ELF) |
252b5132 RH |
11948 | { |
11949 | as_bad (_("-non_shared is supported only for ELF format")); | |
11950 | return 0; | |
11951 | } | |
11952 | mips_pic = NO_PIC; | |
143d77c5 | 11953 | mips_abicalls = FALSE; |
252b5132 RH |
11954 | break; |
11955 | ||
44075ae2 TS |
11956 | /* The -xgot option tells the assembler to use 32 bit offsets |
11957 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
11958 | compatibility. */ |
11959 | case OPTION_XGOT: | |
11960 | mips_big_got = 1; | |
11961 | break; | |
0f074f60 | 11962 | #endif /* OBJ_ELF */ |
252b5132 RH |
11963 | |
11964 | case 'G': | |
6caf9ef4 TS |
11965 | g_switch_value = atoi (arg); |
11966 | g_switch_seen = 1; | |
252b5132 RH |
11967 | break; |
11968 | ||
34ba82a8 TS |
11969 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
11970 | and -mabi=64. */ | |
252b5132 | 11971 | case OPTION_32: |
23fce1e3 NC |
11972 | if (IS_ELF) |
11973 | mips_abi = O32_ABI; | |
11974 | /* We silently ignore -32 for non-ELF targets. This greatly | |
11975 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
11976 | break; |
11977 | ||
23fce1e3 | 11978 | #ifdef OBJ_ELF |
e013f690 | 11979 | case OPTION_N32: |
f43abd2b | 11980 | if (!IS_ELF) |
34ba82a8 TS |
11981 | { |
11982 | as_bad (_("-n32 is supported for ELF format only")); | |
11983 | return 0; | |
11984 | } | |
316f5878 | 11985 | mips_abi = N32_ABI; |
e013f690 | 11986 | break; |
252b5132 | 11987 | |
e013f690 | 11988 | case OPTION_64: |
f43abd2b | 11989 | if (!IS_ELF) |
34ba82a8 TS |
11990 | { |
11991 | as_bad (_("-64 is supported for ELF format only")); | |
11992 | return 0; | |
11993 | } | |
316f5878 | 11994 | mips_abi = N64_ABI; |
f43abd2b | 11995 | if (!support_64bit_objects()) |
e013f690 | 11996 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 11997 | break; |
ae948b86 | 11998 | #endif /* OBJ_ELF */ |
252b5132 | 11999 | |
c97ef257 | 12000 | case OPTION_GP32: |
a325df1d | 12001 | file_mips_gp32 = 1; |
c97ef257 AH |
12002 | break; |
12003 | ||
12004 | case OPTION_GP64: | |
a325df1d | 12005 | file_mips_gp32 = 0; |
c97ef257 | 12006 | break; |
252b5132 | 12007 | |
ca4e0257 | 12008 | case OPTION_FP32: |
a325df1d | 12009 | file_mips_fp32 = 1; |
316f5878 RS |
12010 | break; |
12011 | ||
12012 | case OPTION_FP64: | |
12013 | file_mips_fp32 = 0; | |
ca4e0257 RS |
12014 | break; |
12015 | ||
037b32b9 AN |
12016 | case OPTION_SINGLE_FLOAT: |
12017 | file_mips_single_float = 1; | |
12018 | break; | |
12019 | ||
12020 | case OPTION_DOUBLE_FLOAT: | |
12021 | file_mips_single_float = 0; | |
12022 | break; | |
12023 | ||
12024 | case OPTION_SOFT_FLOAT: | |
12025 | file_mips_soft_float = 1; | |
12026 | break; | |
12027 | ||
12028 | case OPTION_HARD_FLOAT: | |
12029 | file_mips_soft_float = 0; | |
12030 | break; | |
12031 | ||
ae948b86 | 12032 | #ifdef OBJ_ELF |
252b5132 | 12033 | case OPTION_MABI: |
f43abd2b | 12034 | if (!IS_ELF) |
34ba82a8 TS |
12035 | { |
12036 | as_bad (_("-mabi is supported for ELF format only")); | |
12037 | return 0; | |
12038 | } | |
e013f690 | 12039 | if (strcmp (arg, "32") == 0) |
316f5878 | 12040 | mips_abi = O32_ABI; |
e013f690 | 12041 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 12042 | mips_abi = O64_ABI; |
e013f690 | 12043 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 12044 | mips_abi = N32_ABI; |
e013f690 TS |
12045 | else if (strcmp (arg, "64") == 0) |
12046 | { | |
316f5878 | 12047 | mips_abi = N64_ABI; |
e013f690 TS |
12048 | if (! support_64bit_objects()) |
12049 | as_fatal (_("No compiled in support for 64 bit object file " | |
12050 | "format")); | |
12051 | } | |
12052 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 12053 | mips_abi = EABI_ABI; |
e013f690 | 12054 | else |
da0e507f TS |
12055 | { |
12056 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
12057 | return 0; | |
12058 | } | |
252b5132 | 12059 | break; |
e013f690 | 12060 | #endif /* OBJ_ELF */ |
252b5132 | 12061 | |
6b76fefe | 12062 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 12063 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
12064 | break; |
12065 | ||
9ee72ff1 | 12066 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 12067 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
12068 | break; |
12069 | ||
ecb4347a DJ |
12070 | #ifdef OBJ_ELF |
12071 | case OPTION_MDEBUG: | |
b34976b6 | 12072 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
12073 | break; |
12074 | ||
12075 | case OPTION_NO_MDEBUG: | |
b34976b6 | 12076 | mips_flag_mdebug = FALSE; |
ecb4347a | 12077 | break; |
dcd410fe RO |
12078 | |
12079 | case OPTION_PDR: | |
12080 | mips_flag_pdr = TRUE; | |
12081 | break; | |
12082 | ||
12083 | case OPTION_NO_PDR: | |
12084 | mips_flag_pdr = FALSE; | |
12085 | break; | |
0a44bf69 RS |
12086 | |
12087 | case OPTION_MVXWORKS_PIC: | |
12088 | mips_pic = VXWORKS_PIC; | |
12089 | break; | |
ecb4347a DJ |
12090 | #endif /* OBJ_ELF */ |
12091 | ||
252b5132 RH |
12092 | default: |
12093 | return 0; | |
12094 | } | |
12095 | ||
c67a084a NC |
12096 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
12097 | ||
252b5132 RH |
12098 | return 1; |
12099 | } | |
316f5878 RS |
12100 | \f |
12101 | /* Set up globals to generate code for the ISA or processor | |
12102 | described by INFO. */ | |
252b5132 | 12103 | |
252b5132 | 12104 | static void |
17a2f251 | 12105 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 12106 | { |
316f5878 | 12107 | if (info != 0) |
252b5132 | 12108 | { |
fef14a42 TS |
12109 | file_mips_arch = info->cpu; |
12110 | mips_opts.arch = info->cpu; | |
316f5878 | 12111 | mips_opts.isa = info->isa; |
252b5132 | 12112 | } |
252b5132 RH |
12113 | } |
12114 | ||
252b5132 | 12115 | |
316f5878 | 12116 | /* Likewise for tuning. */ |
252b5132 | 12117 | |
316f5878 | 12118 | static void |
17a2f251 | 12119 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
12120 | { |
12121 | if (info != 0) | |
fef14a42 | 12122 | mips_tune = info->cpu; |
316f5878 | 12123 | } |
80cc45a5 | 12124 | |
34ba82a8 | 12125 | |
252b5132 | 12126 | void |
17a2f251 | 12127 | mips_after_parse_args (void) |
e9670677 | 12128 | { |
fef14a42 TS |
12129 | const struct mips_cpu_info *arch_info = 0; |
12130 | const struct mips_cpu_info *tune_info = 0; | |
12131 | ||
e9670677 | 12132 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 12133 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 12134 | { |
6caf9ef4 | 12135 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
12136 | as_bad (_("-G not supported in this configuration.")); |
12137 | g_switch_value = 0; | |
12138 | } | |
12139 | ||
cac012d6 AO |
12140 | if (mips_abi == NO_ABI) |
12141 | mips_abi = MIPS_DEFAULT_ABI; | |
12142 | ||
22923709 RS |
12143 | /* The following code determines the architecture and register size. |
12144 | Similar code was added to GCC 3.3 (see override_options() in | |
12145 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
12146 | as much as possible. */ | |
e9670677 | 12147 | |
316f5878 | 12148 | if (mips_arch_string != 0) |
fef14a42 | 12149 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 12150 | |
316f5878 | 12151 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 12152 | { |
316f5878 | 12153 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 12154 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 12155 | the -march selection (if any). */ |
fef14a42 | 12156 | if (arch_info != 0) |
e9670677 | 12157 | { |
316f5878 RS |
12158 | /* -march takes precedence over -mipsN, since it is more descriptive. |
12159 | There's no harm in specifying both as long as the ISA levels | |
12160 | are the same. */ | |
fef14a42 | 12161 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
12162 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
12163 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 12164 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 12165 | } |
316f5878 | 12166 | else |
fef14a42 | 12167 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
12168 | } |
12169 | ||
fef14a42 TS |
12170 | if (arch_info == 0) |
12171 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 12172 | |
fef14a42 | 12173 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 12174 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
12175 | arch_info->name); |
12176 | ||
12177 | mips_set_architecture (arch_info); | |
12178 | ||
12179 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
12180 | if (mips_tune_string != 0) | |
12181 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 12182 | |
fef14a42 TS |
12183 | if (tune_info == 0) |
12184 | mips_set_tune (arch_info); | |
12185 | else | |
12186 | mips_set_tune (tune_info); | |
e9670677 | 12187 | |
316f5878 | 12188 | if (file_mips_gp32 >= 0) |
e9670677 | 12189 | { |
316f5878 RS |
12190 | /* The user specified the size of the integer registers. Make sure |
12191 | it agrees with the ABI and ISA. */ | |
12192 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
12193 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
12194 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
12195 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
12196 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
12197 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
12198 | } |
12199 | else | |
12200 | { | |
316f5878 RS |
12201 | /* Infer the integer register size from the ABI and processor. |
12202 | Restrict ourselves to 32-bit registers if that's all the | |
12203 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
12204 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
12205 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
12206 | } |
12207 | ||
ad3fea08 TS |
12208 | switch (file_mips_fp32) |
12209 | { | |
12210 | default: | |
12211 | case -1: | |
12212 | /* No user specified float register size. | |
12213 | ??? GAS treats single-float processors as though they had 64-bit | |
12214 | float registers (although it complains when double-precision | |
12215 | instructions are used). As things stand, saying they have 32-bit | |
12216 | registers would lead to spurious "register must be even" messages. | |
12217 | So here we assume float registers are never smaller than the | |
12218 | integer ones. */ | |
12219 | if (file_mips_gp32 == 0) | |
12220 | /* 64-bit integer registers implies 64-bit float registers. */ | |
12221 | file_mips_fp32 = 0; | |
12222 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
12223 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
12224 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
12225 | file_mips_fp32 = 0; | |
12226 | else | |
12227 | /* 32-bit float registers. */ | |
12228 | file_mips_fp32 = 1; | |
12229 | break; | |
12230 | ||
12231 | /* The user specified the size of the float registers. Check if it | |
12232 | agrees with the ABI and ISA. */ | |
12233 | case 0: | |
12234 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
12235 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
12236 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
12237 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
12238 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
12239 | break; | |
12240 | case 1: | |
12241 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
12242 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
12243 | break; | |
12244 | } | |
e9670677 | 12245 | |
316f5878 | 12246 | /* End of GCC-shared inference code. */ |
e9670677 | 12247 | |
17a2f251 TS |
12248 | /* This flag is set when we have a 64-bit capable CPU but use only |
12249 | 32-bit wide registers. Note that EABI does not use it. */ | |
12250 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
12251 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
12252 | || mips_abi == O32_ABI)) | |
316f5878 | 12253 | mips_32bitmode = 1; |
e9670677 MR |
12254 | |
12255 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
12256 | as_bad (_("trap exception not supported at ISA 1")); | |
12257 | ||
e9670677 MR |
12258 | /* If the selected architecture includes support for ASEs, enable |
12259 | generation of code for them. */ | |
a4672219 | 12260 | if (mips_opts.mips16 == -1) |
fef14a42 | 12261 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 12262 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 12263 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
12264 | && file_mips_fp32 == 0) ? 1 : 0; |
12265 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
12266 | as_bad (_("-mfp32 used with -mips3d")); | |
12267 | ||
ffdefa66 | 12268 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 12269 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
12270 | && file_mips_fp32 == 0) ? 1 : 0; |
12271 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
12272 | as_bad (_("-mfp32 used with -mdmx")); | |
12273 | ||
12274 | if (mips_opts.ase_smartmips == -1) | |
12275 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
12276 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
20203fb9 NC |
12277 | as_warn (_("%s ISA does not support SmartMIPS"), |
12278 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 12279 | |
74cd071d | 12280 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
12281 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
12282 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
20203fb9 NC |
12283 | as_warn (_("%s ISA does not support DSP ASE"), |
12284 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 12285 | |
8b082fb1 TS |
12286 | if (mips_opts.ase_dspr2 == -1) |
12287 | { | |
12288 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
12289 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
12290 | } | |
12291 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 NC |
12292 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
12293 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 12294 | |
ef2e4d86 | 12295 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
12296 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
12297 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
20203fb9 NC |
12298 | as_warn (_("%s ISA does not support MT ASE"), |
12299 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 12300 | |
e9670677 | 12301 | file_mips_isa = mips_opts.isa; |
e9670677 MR |
12302 | file_ase_mips3d = mips_opts.ase_mips3d; |
12303 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 12304 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 12305 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 12306 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 12307 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
12308 | mips_opts.gp32 = file_mips_gp32; |
12309 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
12310 | mips_opts.soft_float = file_mips_soft_float; |
12311 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 12312 | |
ecb4347a DJ |
12313 | if (mips_flag_mdebug < 0) |
12314 | { | |
12315 | #ifdef OBJ_MAYBE_ECOFF | |
12316 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
12317 | mips_flag_mdebug = 1; | |
12318 | else | |
12319 | #endif /* OBJ_MAYBE_ECOFF */ | |
12320 | mips_flag_mdebug = 0; | |
12321 | } | |
e9670677 MR |
12322 | } |
12323 | \f | |
12324 | void | |
17a2f251 | 12325 | mips_init_after_args (void) |
252b5132 RH |
12326 | { |
12327 | /* initialize opcodes */ | |
12328 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 12329 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
12330 | } |
12331 | ||
12332 | long | |
17a2f251 | 12333 | md_pcrel_from (fixS *fixP) |
252b5132 | 12334 | { |
a7ebbfdf TS |
12335 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
12336 | switch (fixP->fx_r_type) | |
12337 | { | |
12338 | case BFD_RELOC_16_PCREL_S2: | |
12339 | case BFD_RELOC_MIPS_JMP: | |
12340 | /* Return the address of the delay slot. */ | |
12341 | return addr + 4; | |
12342 | default: | |
58ea3d6a | 12343 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
12344 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
12345 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12346 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
12347 | return addr; |
12348 | } | |
252b5132 RH |
12349 | } |
12350 | ||
252b5132 RH |
12351 | /* This is called before the symbol table is processed. In order to |
12352 | work with gcc when using mips-tfile, we must keep all local labels. | |
12353 | However, in other cases, we want to discard them. If we were | |
12354 | called with -g, but we didn't see any debugging information, it may | |
12355 | mean that gcc is smuggling debugging information through to | |
12356 | mips-tfile, in which case we must generate all local labels. */ | |
12357 | ||
12358 | void | |
17a2f251 | 12359 | mips_frob_file_before_adjust (void) |
252b5132 RH |
12360 | { |
12361 | #ifndef NO_ECOFF_DEBUGGING | |
12362 | if (ECOFF_DEBUGGING | |
12363 | && mips_debug != 0 | |
12364 | && ! ecoff_debugging_seen) | |
12365 | flag_keep_locals = 1; | |
12366 | #endif | |
12367 | } | |
12368 | ||
3b91255e | 12369 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 12370 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
12371 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
12372 | relocation operators. | |
12373 | ||
12374 | For our purposes, a %lo() expression matches a %got() or %hi() | |
12375 | expression if: | |
12376 | ||
12377 | (a) it refers to the same symbol; and | |
12378 | (b) the offset applied in the %lo() expression is no lower than | |
12379 | the offset applied in the %got() or %hi(). | |
12380 | ||
12381 | (b) allows us to cope with code like: | |
12382 | ||
12383 | lui $4,%hi(foo) | |
12384 | lh $4,%lo(foo+2)($4) | |
12385 | ||
12386 | ...which is legal on RELA targets, and has a well-defined behaviour | |
12387 | if the user knows that adding 2 to "foo" will not induce a carry to | |
12388 | the high 16 bits. | |
12389 | ||
12390 | When several %lo()s match a particular %got() or %hi(), we use the | |
12391 | following rules to distinguish them: | |
12392 | ||
12393 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
12394 | higher offsets. | |
12395 | ||
12396 | (2) %lo()s with no matching %got() or %hi() are better than those | |
12397 | that already have a matching %got() or %hi(). | |
12398 | ||
12399 | (3) later %lo()s are better than earlier %lo()s. | |
12400 | ||
12401 | These rules are applied in order. | |
12402 | ||
12403 | (1) means, among other things, that %lo()s with identical offsets are | |
12404 | chosen if they exist. | |
12405 | ||
12406 | (2) means that we won't associate several high-part relocations with | |
12407 | the same low-part relocation unless there's no alternative. Having | |
12408 | several high parts for the same low part is a GNU extension; this rule | |
12409 | allows careful users to avoid it. | |
12410 | ||
12411 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
12412 | with the last high-part relocation being at the front of the list. | |
12413 | It therefore makes sense to choose the last matching low-part | |
12414 | relocation, all other things being equal. It's also easier | |
12415 | to code that way. */ | |
252b5132 RH |
12416 | |
12417 | void | |
17a2f251 | 12418 | mips_frob_file (void) |
252b5132 RH |
12419 | { |
12420 | struct mips_hi_fixup *l; | |
35903be0 | 12421 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
12422 | |
12423 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
12424 | { | |
12425 | segment_info_type *seginfo; | |
3b91255e RS |
12426 | bfd_boolean matched_lo_p; |
12427 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 12428 | |
9c2799c2 | 12429 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 12430 | |
5919d012 RS |
12431 | /* If a GOT16 relocation turns out to be against a global symbol, |
12432 | there isn't supposed to be a matching LO. */ | |
738e5348 | 12433 | if (got16_reloc_p (l->fixp->fx_r_type) |
5919d012 RS |
12434 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) |
12435 | continue; | |
12436 | ||
12437 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
12438 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
12439 | continue; |
12440 | ||
252b5132 | 12441 | seginfo = seg_info (l->seg); |
252b5132 | 12442 | |
3b91255e RS |
12443 | /* Set HI_POS to the position of this relocation in the chain. |
12444 | Set LO_POS to the position of the chosen low-part relocation. | |
12445 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
12446 | relocation that matches an immediately-preceding high-part | |
12447 | relocation. */ | |
12448 | hi_pos = NULL; | |
12449 | lo_pos = NULL; | |
12450 | matched_lo_p = FALSE; | |
738e5348 | 12451 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 12452 | |
3b91255e RS |
12453 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
12454 | { | |
12455 | if (*pos == l->fixp) | |
12456 | hi_pos = pos; | |
12457 | ||
35903be0 | 12458 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 12459 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
12460 | && (*pos)->fx_offset >= l->fixp->fx_offset |
12461 | && (lo_pos == NULL | |
12462 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
12463 | || (!matched_lo_p | |
12464 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
12465 | lo_pos = pos; | |
12466 | ||
12467 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
12468 | && fixup_has_matching_lo_p (*pos)); | |
12469 | } | |
12470 | ||
12471 | /* If we found a match, remove the high-part relocation from its | |
12472 | current position and insert it before the low-part relocation. | |
12473 | Make the offsets match so that fixup_has_matching_lo_p() | |
12474 | will return true. | |
12475 | ||
12476 | We don't warn about unmatched high-part relocations since some | |
12477 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
12478 | instructions. */ | |
12479 | if (lo_pos != NULL) | |
12480 | { | |
12481 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
12482 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 12483 | { |
3b91255e RS |
12484 | *hi_pos = l->fixp->fx_next; |
12485 | l->fixp->fx_next = *lo_pos; | |
12486 | *lo_pos = l->fixp; | |
252b5132 | 12487 | } |
252b5132 RH |
12488 | } |
12489 | } | |
12490 | } | |
12491 | ||
3e722fb5 | 12492 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 12493 | We have to prevent gas from dropping them. */ |
252b5132 | 12494 | |
252b5132 | 12495 | int |
17a2f251 | 12496 | mips_force_relocation (fixS *fixp) |
252b5132 | 12497 | { |
ae6063d4 | 12498 | if (generic_force_reloc (fixp)) |
252b5132 RH |
12499 | return 1; |
12500 | ||
f6688943 TS |
12501 | if (HAVE_NEWABI |
12502 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
12503 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
738e5348 RS |
12504 | || hi16_reloc_p (fixp->fx_r_type) |
12505 | || lo16_reloc_p (fixp->fx_r_type))) | |
f6688943 TS |
12506 | return 1; |
12507 | ||
3e722fb5 | 12508 | return 0; |
252b5132 RH |
12509 | } |
12510 | ||
12511 | /* Apply a fixup to the object file. */ | |
12512 | ||
94f592af | 12513 | void |
55cf6793 | 12514 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 12515 | { |
874e8986 | 12516 | bfd_byte *buf; |
98aa84af | 12517 | long insn; |
a7ebbfdf | 12518 | reloc_howto_type *howto; |
252b5132 | 12519 | |
a7ebbfdf TS |
12520 | /* We ignore generic BFD relocations we don't know about. */ |
12521 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
12522 | if (! howto) | |
12523 | return; | |
65551fa4 | 12524 | |
9c2799c2 | 12525 | gas_assert (fixP->fx_size == 4 |
90ecf173 MR |
12526 | || fixP->fx_r_type == BFD_RELOC_16 |
12527 | || fixP->fx_r_type == BFD_RELOC_64 | |
12528 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
12529 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
12530 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
12531 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
12532 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 12533 | |
a7ebbfdf | 12534 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 12535 | |
9c2799c2 | 12536 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2); |
b1dca8ee RS |
12537 | |
12538 | /* Don't treat parts of a composite relocation as done. There are two | |
12539 | reasons for this: | |
12540 | ||
12541 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
12542 | should nevertheless be emitted if the first part is. | |
12543 | ||
12544 | (2) In normal usage, composite relocations are never assembly-time | |
12545 | constants. The easiest way of dealing with the pathological | |
12546 | exceptions is to generate a relocation against STN_UNDEF and | |
12547 | leave everything up to the linker. */ | |
3994f87e | 12548 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
12549 | fixP->fx_done = 1; |
12550 | ||
12551 | switch (fixP->fx_r_type) | |
12552 | { | |
3f98094e DJ |
12553 | case BFD_RELOC_MIPS_TLS_GD: |
12554 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
12555 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
12556 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
12557 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
12558 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
12559 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
12560 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
12561 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
12562 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
12563 | /* fall through */ | |
12564 | ||
252b5132 | 12565 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
12566 | case BFD_RELOC_MIPS_SHIFT5: |
12567 | case BFD_RELOC_MIPS_SHIFT6: | |
12568 | case BFD_RELOC_MIPS_GOT_DISP: | |
12569 | case BFD_RELOC_MIPS_GOT_PAGE: | |
12570 | case BFD_RELOC_MIPS_GOT_OFST: | |
12571 | case BFD_RELOC_MIPS_SUB: | |
12572 | case BFD_RELOC_MIPS_INSERT_A: | |
12573 | case BFD_RELOC_MIPS_INSERT_B: | |
12574 | case BFD_RELOC_MIPS_DELETE: | |
12575 | case BFD_RELOC_MIPS_HIGHEST: | |
12576 | case BFD_RELOC_MIPS_HIGHER: | |
12577 | case BFD_RELOC_MIPS_SCN_DISP: | |
12578 | case BFD_RELOC_MIPS_REL16: | |
12579 | case BFD_RELOC_MIPS_RELGOT: | |
12580 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
12581 | case BFD_RELOC_HI16: |
12582 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 12583 | case BFD_RELOC_GPREL16: |
252b5132 RH |
12584 | case BFD_RELOC_MIPS_LITERAL: |
12585 | case BFD_RELOC_MIPS_CALL16: | |
12586 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 12587 | case BFD_RELOC_GPREL32: |
252b5132 RH |
12588 | case BFD_RELOC_MIPS_GOT_HI16: |
12589 | case BFD_RELOC_MIPS_GOT_LO16: | |
12590 | case BFD_RELOC_MIPS_CALL_HI16: | |
12591 | case BFD_RELOC_MIPS_CALL_LO16: | |
12592 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
12593 | case BFD_RELOC_MIPS16_GOT16: |
12594 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
12595 | case BFD_RELOC_MIPS16_HI16: |
12596 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 | 12597 | case BFD_RELOC_MIPS16_JMP: |
54f4ddb3 | 12598 | /* Nothing needed to do. The value comes from the reloc entry. */ |
252b5132 RH |
12599 | break; |
12600 | ||
252b5132 RH |
12601 | case BFD_RELOC_64: |
12602 | /* This is handled like BFD_RELOC_32, but we output a sign | |
12603 | extended value if we are only 32 bits. */ | |
3e722fb5 | 12604 | if (fixP->fx_done) |
252b5132 RH |
12605 | { |
12606 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 12607 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
12608 | else |
12609 | { | |
a7ebbfdf | 12610 | valueT hiv; |
252b5132 | 12611 | |
a7ebbfdf | 12612 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
12613 | hiv = 0xffffffff; |
12614 | else | |
12615 | hiv = 0; | |
b215186b | 12616 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 12617 | *valP, 4); |
b215186b | 12618 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 12619 | hiv, 4); |
252b5132 RH |
12620 | } |
12621 | } | |
12622 | break; | |
12623 | ||
056350c6 | 12624 | case BFD_RELOC_RVA: |
252b5132 | 12625 | case BFD_RELOC_32: |
252b5132 RH |
12626 | case BFD_RELOC_16: |
12627 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
12628 | value now. This can happen if we have a .word which is not |
12629 | resolved when it appears but is later defined. */ | |
252b5132 | 12630 | if (fixP->fx_done) |
54f4ddb3 | 12631 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); |
252b5132 RH |
12632 | break; |
12633 | ||
12634 | case BFD_RELOC_LO16: | |
d6f16593 | 12635 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
12636 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
12637 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
12638 | /* When handling an embedded PIC switch statement, we can wind |
12639 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
12640 | if (fixP->fx_done) | |
12641 | { | |
a7ebbfdf | 12642 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
12643 | as_bad_where (fixP->fx_file, fixP->fx_line, |
12644 | _("relocation overflow")); | |
252b5132 RH |
12645 | if (target_big_endian) |
12646 | buf += 2; | |
2132e3a3 | 12647 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
12648 | } |
12649 | break; | |
12650 | ||
12651 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 12652 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 12653 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 12654 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 12655 | |
54f4ddb3 TS |
12656 | /* We need to save the bits in the instruction since fixup_segment() |
12657 | might be deleting the relocation entry (i.e., a branch within | |
12658 | the current segment). */ | |
a7ebbfdf | 12659 | if (! fixP->fx_done) |
bb2d6cd7 | 12660 | break; |
252b5132 | 12661 | |
54f4ddb3 | 12662 | /* Update old instruction data. */ |
252b5132 RH |
12663 | if (target_big_endian) |
12664 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
12665 | else | |
12666 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
12667 | ||
a7ebbfdf TS |
12668 | if (*valP + 0x20000 <= 0x3ffff) |
12669 | { | |
12670 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 12671 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
12672 | } |
12673 | else if (mips_pic == NO_PIC | |
12674 | && fixP->fx_done | |
12675 | && fixP->fx_frag->fr_address >= text_section->vma | |
12676 | && (fixP->fx_frag->fr_address | |
587aac4e | 12677 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
12678 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
12679 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
12680 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
12681 | { |
12682 | /* The branch offset is too large. If this is an | |
12683 | unconditional branch, and we are not generating PIC code, | |
12684 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
12685 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
12686 | insn = 0x0c000000; /* jal */ | |
252b5132 | 12687 | else |
a7ebbfdf TS |
12688 | insn = 0x08000000; /* j */ |
12689 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
12690 | fixP->fx_done = 0; | |
12691 | fixP->fx_addsy = section_symbol (text_section); | |
12692 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 12693 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
12694 | } |
12695 | else | |
12696 | { | |
12697 | /* If we got here, we have branch-relaxation disabled, | |
12698 | and there's nothing we can do to fix this instruction | |
12699 | without turning it into a longer sequence. */ | |
12700 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12701 | _("Branch out of range")); | |
252b5132 | 12702 | } |
252b5132 RH |
12703 | break; |
12704 | ||
12705 | case BFD_RELOC_VTABLE_INHERIT: | |
12706 | fixP->fx_done = 0; | |
12707 | if (fixP->fx_addsy | |
12708 | && !S_IS_DEFINED (fixP->fx_addsy) | |
12709 | && !S_IS_WEAK (fixP->fx_addsy)) | |
12710 | S_SET_WEAK (fixP->fx_addsy); | |
12711 | break; | |
12712 | ||
12713 | case BFD_RELOC_VTABLE_ENTRY: | |
12714 | fixP->fx_done = 0; | |
12715 | break; | |
12716 | ||
12717 | default: | |
12718 | internalError (); | |
12719 | } | |
a7ebbfdf TS |
12720 | |
12721 | /* Remember value for tc_gen_reloc. */ | |
12722 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
12723 | } |
12724 | ||
252b5132 | 12725 | static symbolS * |
17a2f251 | 12726 | get_symbol (void) |
252b5132 RH |
12727 | { |
12728 | int c; | |
12729 | char *name; | |
12730 | symbolS *p; | |
12731 | ||
12732 | name = input_line_pointer; | |
12733 | c = get_symbol_end (); | |
12734 | p = (symbolS *) symbol_find_or_make (name); | |
12735 | *input_line_pointer = c; | |
12736 | return p; | |
12737 | } | |
12738 | ||
742a56fe RS |
12739 | /* Align the current frag to a given power of two. If a particular |
12740 | fill byte should be used, FILL points to an integer that contains | |
12741 | that byte, otherwise FILL is null. | |
12742 | ||
12743 | The MIPS assembler also automatically adjusts any preceding | |
12744 | label. */ | |
252b5132 RH |
12745 | |
12746 | static void | |
742a56fe | 12747 | mips_align (int to, int *fill, symbolS *label) |
252b5132 | 12748 | { |
7d10b47d | 12749 | mips_emit_delays (); |
742a56fe RS |
12750 | mips_record_mips16_mode (); |
12751 | if (fill == NULL && subseg_text_p (now_seg)) | |
12752 | frag_align_code (to, 0); | |
12753 | else | |
12754 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 RH |
12755 | record_alignment (now_seg, to); |
12756 | if (label != NULL) | |
12757 | { | |
9c2799c2 | 12758 | gas_assert (S_GET_SEGMENT (label) == now_seg); |
49309057 | 12759 | symbol_set_frag (label, frag_now); |
252b5132 RH |
12760 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
12761 | } | |
12762 | } | |
12763 | ||
12764 | /* Align to a given power of two. .align 0 turns off the automatic | |
12765 | alignment used by the data creating pseudo-ops. */ | |
12766 | ||
12767 | static void | |
17a2f251 | 12768 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 12769 | { |
742a56fe | 12770 | int temp, fill_value, *fill_ptr; |
49954fb4 | 12771 | long max_alignment = 28; |
252b5132 | 12772 | |
54f4ddb3 | 12773 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 12774 | to the aligned address. |
54f4ddb3 | 12775 | o It's not documented but auto alignment is reinstated by |
252b5132 | 12776 | a .align pseudo instruction. |
54f4ddb3 | 12777 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 12778 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 12779 | We don't. */ |
252b5132 RH |
12780 | |
12781 | temp = get_absolute_expression (); | |
12782 | if (temp > max_alignment) | |
12783 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
12784 | else if (temp < 0) | |
12785 | { | |
12786 | as_warn (_("Alignment negative: 0 assumed.")); | |
12787 | temp = 0; | |
12788 | } | |
12789 | if (*input_line_pointer == ',') | |
12790 | { | |
f9419b05 | 12791 | ++input_line_pointer; |
742a56fe RS |
12792 | fill_value = get_absolute_expression (); |
12793 | fill_ptr = &fill_value; | |
252b5132 RH |
12794 | } |
12795 | else | |
742a56fe | 12796 | fill_ptr = 0; |
252b5132 RH |
12797 | if (temp) |
12798 | { | |
a8dbcb85 TS |
12799 | segment_info_type *si = seg_info (now_seg); |
12800 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 12801 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 12802 | auto_align = 1; |
742a56fe | 12803 | mips_align (temp, fill_ptr, l != NULL ? l->label : NULL); |
252b5132 RH |
12804 | } |
12805 | else | |
12806 | { | |
12807 | auto_align = 0; | |
12808 | } | |
12809 | ||
12810 | demand_empty_rest_of_line (); | |
12811 | } | |
12812 | ||
252b5132 | 12813 | static void |
17a2f251 | 12814 | s_change_sec (int sec) |
252b5132 RH |
12815 | { |
12816 | segT seg; | |
12817 | ||
252b5132 RH |
12818 | #ifdef OBJ_ELF |
12819 | /* The ELF backend needs to know that we are changing sections, so | |
12820 | that .previous works correctly. We could do something like check | |
b6ff326e | 12821 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
12822 | as it would not be appropriate to use it in the section changing |
12823 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
12824 | This should be cleaner, somehow. */ | |
f43abd2b TS |
12825 | if (IS_ELF) |
12826 | obj_elf_section_change_hook (); | |
252b5132 RH |
12827 | #endif |
12828 | ||
7d10b47d | 12829 | mips_emit_delays (); |
6a32d874 | 12830 | |
252b5132 RH |
12831 | switch (sec) |
12832 | { | |
12833 | case 't': | |
12834 | s_text (0); | |
12835 | break; | |
12836 | case 'd': | |
12837 | s_data (0); | |
12838 | break; | |
12839 | case 'b': | |
12840 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
12841 | demand_empty_rest_of_line (); | |
12842 | break; | |
12843 | ||
12844 | case 'r': | |
4d0d148d TS |
12845 | seg = subseg_new (RDATA_SECTION_NAME, |
12846 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 12847 | if (IS_ELF) |
252b5132 | 12848 | { |
4d0d148d TS |
12849 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
12850 | | SEC_READONLY | SEC_RELOC | |
12851 | | SEC_DATA)); | |
c41e87e3 | 12852 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 12853 | record_alignment (seg, 4); |
252b5132 | 12854 | } |
4d0d148d | 12855 | demand_empty_rest_of_line (); |
252b5132 RH |
12856 | break; |
12857 | ||
12858 | case 's': | |
4d0d148d | 12859 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 12860 | if (IS_ELF) |
252b5132 | 12861 | { |
4d0d148d TS |
12862 | bfd_set_section_flags (stdoutput, seg, |
12863 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 12864 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 12865 | record_alignment (seg, 4); |
252b5132 | 12866 | } |
4d0d148d TS |
12867 | demand_empty_rest_of_line (); |
12868 | break; | |
998b3c36 MR |
12869 | |
12870 | case 'B': | |
12871 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
12872 | if (IS_ELF) | |
12873 | { | |
12874 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); | |
12875 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
12876 | record_alignment (seg, 4); | |
12877 | } | |
12878 | demand_empty_rest_of_line (); | |
12879 | break; | |
252b5132 RH |
12880 | } |
12881 | ||
12882 | auto_align = 1; | |
12883 | } | |
b34976b6 | 12884 | |
cca86cc8 | 12885 | void |
17a2f251 | 12886 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 12887 | { |
7ed4a06a | 12888 | #ifdef OBJ_ELF |
cca86cc8 SC |
12889 | char *section_name; |
12890 | char c; | |
684022ea | 12891 | char next_c = 0; |
cca86cc8 SC |
12892 | int section_type; |
12893 | int section_flag; | |
12894 | int section_entry_size; | |
12895 | int section_alignment; | |
b34976b6 | 12896 | |
f43abd2b | 12897 | if (!IS_ELF) |
7ed4a06a TS |
12898 | return; |
12899 | ||
cca86cc8 SC |
12900 | section_name = input_line_pointer; |
12901 | c = get_symbol_end (); | |
a816d1ed AO |
12902 | if (c) |
12903 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 12904 | |
4cf0dd0d TS |
12905 | /* Do we have .section Name<,"flags">? */ |
12906 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 12907 | { |
4cf0dd0d TS |
12908 | /* just after name is now '\0'. */ |
12909 | *input_line_pointer = c; | |
cca86cc8 SC |
12910 | input_line_pointer = section_name; |
12911 | obj_elf_section (ignore); | |
12912 | return; | |
12913 | } | |
12914 | input_line_pointer++; | |
12915 | ||
12916 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
12917 | if (c == ',') | |
12918 | section_type = get_absolute_expression (); | |
12919 | else | |
12920 | section_type = 0; | |
12921 | if (*input_line_pointer++ == ',') | |
12922 | section_flag = get_absolute_expression (); | |
12923 | else | |
12924 | section_flag = 0; | |
12925 | if (*input_line_pointer++ == ',') | |
12926 | section_entry_size = get_absolute_expression (); | |
12927 | else | |
12928 | section_entry_size = 0; | |
12929 | if (*input_line_pointer++ == ',') | |
12930 | section_alignment = get_absolute_expression (); | |
12931 | else | |
12932 | section_alignment = 0; | |
87975d2a AM |
12933 | /* FIXME: really ignore? */ |
12934 | (void) section_alignment; | |
cca86cc8 | 12935 | |
a816d1ed AO |
12936 | section_name = xstrdup (section_name); |
12937 | ||
8ab8a5c8 RS |
12938 | /* When using the generic form of .section (as implemented by obj-elf.c), |
12939 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
12940 | traditionally had to fall back on the more common @progbits instead. | |
12941 | ||
12942 | There's nothing really harmful in this, since bfd will correct | |
12943 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 12944 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
12945 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
12946 | ||
12947 | Even so, we shouldn't force users of the MIPS .section syntax to | |
12948 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
12949 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
12950 | generic type-checking code. */ | |
12951 | if (section_type == SHT_MIPS_DWARF) | |
12952 | section_type = SHT_PROGBITS; | |
12953 | ||
cca86cc8 SC |
12954 | obj_elf_change_section (section_name, section_type, section_flag, |
12955 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
12956 | |
12957 | if (now_seg->name != section_name) | |
12958 | free (section_name); | |
7ed4a06a | 12959 | #endif /* OBJ_ELF */ |
cca86cc8 | 12960 | } |
252b5132 RH |
12961 | |
12962 | void | |
17a2f251 | 12963 | mips_enable_auto_align (void) |
252b5132 RH |
12964 | { |
12965 | auto_align = 1; | |
12966 | } | |
12967 | ||
12968 | static void | |
17a2f251 | 12969 | s_cons (int log_size) |
252b5132 | 12970 | { |
a8dbcb85 TS |
12971 | segment_info_type *si = seg_info (now_seg); |
12972 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12973 | symbolS *label; |
12974 | ||
a8dbcb85 | 12975 | label = l != NULL ? l->label : NULL; |
7d10b47d | 12976 | mips_emit_delays (); |
252b5132 RH |
12977 | if (log_size > 0 && auto_align) |
12978 | mips_align (log_size, 0, label); | |
252b5132 | 12979 | cons (1 << log_size); |
a1facbec | 12980 | mips_clear_insn_labels (); |
252b5132 RH |
12981 | } |
12982 | ||
12983 | static void | |
17a2f251 | 12984 | s_float_cons (int type) |
252b5132 | 12985 | { |
a8dbcb85 TS |
12986 | segment_info_type *si = seg_info (now_seg); |
12987 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12988 | symbolS *label; |
12989 | ||
a8dbcb85 | 12990 | label = l != NULL ? l->label : NULL; |
252b5132 | 12991 | |
7d10b47d | 12992 | mips_emit_delays (); |
252b5132 RH |
12993 | |
12994 | if (auto_align) | |
49309057 ILT |
12995 | { |
12996 | if (type == 'd') | |
12997 | mips_align (3, 0, label); | |
12998 | else | |
12999 | mips_align (2, 0, label); | |
13000 | } | |
252b5132 | 13001 | |
252b5132 | 13002 | float_cons (type); |
a1facbec | 13003 | mips_clear_insn_labels (); |
252b5132 RH |
13004 | } |
13005 | ||
13006 | /* Handle .globl. We need to override it because on Irix 5 you are | |
13007 | permitted to say | |
13008 | .globl foo .text | |
13009 | where foo is an undefined symbol, to mean that foo should be | |
13010 | considered to be the address of a function. */ | |
13011 | ||
13012 | static void | |
17a2f251 | 13013 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13014 | { |
13015 | char *name; | |
13016 | int c; | |
13017 | symbolS *symbolP; | |
13018 | flagword flag; | |
13019 | ||
8a06b769 | 13020 | do |
252b5132 | 13021 | { |
8a06b769 | 13022 | name = input_line_pointer; |
252b5132 | 13023 | c = get_symbol_end (); |
8a06b769 TS |
13024 | symbolP = symbol_find_or_make (name); |
13025 | S_SET_EXTERNAL (symbolP); | |
13026 | ||
252b5132 | 13027 | *input_line_pointer = c; |
8a06b769 | 13028 | SKIP_WHITESPACE (); |
252b5132 | 13029 | |
8a06b769 TS |
13030 | /* On Irix 5, every global symbol that is not explicitly labelled as |
13031 | being a function is apparently labelled as being an object. */ | |
13032 | flag = BSF_OBJECT; | |
252b5132 | 13033 | |
8a06b769 TS |
13034 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
13035 | && (*input_line_pointer != ',')) | |
13036 | { | |
13037 | char *secname; | |
13038 | asection *sec; | |
13039 | ||
13040 | secname = input_line_pointer; | |
13041 | c = get_symbol_end (); | |
13042 | sec = bfd_get_section_by_name (stdoutput, secname); | |
13043 | if (sec == NULL) | |
13044 | as_bad (_("%s: no such section"), secname); | |
13045 | *input_line_pointer = c; | |
13046 | ||
13047 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
13048 | flag = BSF_FUNCTION; | |
13049 | } | |
13050 | ||
13051 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
13052 | ||
13053 | c = *input_line_pointer; | |
13054 | if (c == ',') | |
13055 | { | |
13056 | input_line_pointer++; | |
13057 | SKIP_WHITESPACE (); | |
13058 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
13059 | c = '\n'; | |
13060 | } | |
13061 | } | |
13062 | while (c == ','); | |
252b5132 | 13063 | |
252b5132 RH |
13064 | demand_empty_rest_of_line (); |
13065 | } | |
13066 | ||
13067 | static void | |
17a2f251 | 13068 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13069 | { |
13070 | char *opt; | |
13071 | char c; | |
13072 | ||
13073 | opt = input_line_pointer; | |
13074 | c = get_symbol_end (); | |
13075 | ||
13076 | if (*opt == 'O') | |
13077 | { | |
13078 | /* FIXME: What does this mean? */ | |
13079 | } | |
13080 | else if (strncmp (opt, "pic", 3) == 0) | |
13081 | { | |
13082 | int i; | |
13083 | ||
13084 | i = atoi (opt + 3); | |
13085 | if (i == 0) | |
13086 | mips_pic = NO_PIC; | |
13087 | else if (i == 2) | |
143d77c5 | 13088 | { |
252b5132 | 13089 | mips_pic = SVR4_PIC; |
143d77c5 EC |
13090 | mips_abicalls = TRUE; |
13091 | } | |
252b5132 RH |
13092 | else |
13093 | as_bad (_(".option pic%d not supported"), i); | |
13094 | ||
4d0d148d | 13095 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
13096 | { |
13097 | if (g_switch_seen && g_switch_value != 0) | |
13098 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
13099 | g_switch_value = 0; | |
13100 | bfd_set_gp_size (stdoutput, 0); | |
13101 | } | |
13102 | } | |
13103 | else | |
13104 | as_warn (_("Unrecognized option \"%s\""), opt); | |
13105 | ||
13106 | *input_line_pointer = c; | |
13107 | demand_empty_rest_of_line (); | |
13108 | } | |
13109 | ||
13110 | /* This structure is used to hold a stack of .set values. */ | |
13111 | ||
e972090a NC |
13112 | struct mips_option_stack |
13113 | { | |
252b5132 RH |
13114 | struct mips_option_stack *next; |
13115 | struct mips_set_options options; | |
13116 | }; | |
13117 | ||
13118 | static struct mips_option_stack *mips_opts_stack; | |
13119 | ||
13120 | /* Handle the .set pseudo-op. */ | |
13121 | ||
13122 | static void | |
17a2f251 | 13123 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13124 | { |
13125 | char *name = input_line_pointer, ch; | |
13126 | ||
13127 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 13128 | ++input_line_pointer; |
252b5132 RH |
13129 | ch = *input_line_pointer; |
13130 | *input_line_pointer = '\0'; | |
13131 | ||
13132 | if (strcmp (name, "reorder") == 0) | |
13133 | { | |
7d10b47d RS |
13134 | if (mips_opts.noreorder) |
13135 | end_noreorder (); | |
252b5132 RH |
13136 | } |
13137 | else if (strcmp (name, "noreorder") == 0) | |
13138 | { | |
7d10b47d RS |
13139 | if (!mips_opts.noreorder) |
13140 | start_noreorder (); | |
252b5132 | 13141 | } |
741fe287 MR |
13142 | else if (strncmp (name, "at=", 3) == 0) |
13143 | { | |
13144 | char *s = name + 3; | |
13145 | ||
13146 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
13147 | as_bad (_("Unrecognized register name `%s'"), s); | |
13148 | } | |
252b5132 RH |
13149 | else if (strcmp (name, "at") == 0) |
13150 | { | |
741fe287 | 13151 | mips_opts.at = ATREG; |
252b5132 RH |
13152 | } |
13153 | else if (strcmp (name, "noat") == 0) | |
13154 | { | |
741fe287 | 13155 | mips_opts.at = ZERO; |
252b5132 RH |
13156 | } |
13157 | else if (strcmp (name, "macro") == 0) | |
13158 | { | |
13159 | mips_opts.warn_about_macros = 0; | |
13160 | } | |
13161 | else if (strcmp (name, "nomacro") == 0) | |
13162 | { | |
13163 | if (mips_opts.noreorder == 0) | |
13164 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
13165 | mips_opts.warn_about_macros = 1; | |
13166 | } | |
13167 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
13168 | { | |
13169 | mips_opts.nomove = 0; | |
13170 | } | |
13171 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
13172 | { | |
13173 | mips_opts.nomove = 1; | |
13174 | } | |
13175 | else if (strcmp (name, "bopt") == 0) | |
13176 | { | |
13177 | mips_opts.nobopt = 0; | |
13178 | } | |
13179 | else if (strcmp (name, "nobopt") == 0) | |
13180 | { | |
13181 | mips_opts.nobopt = 1; | |
13182 | } | |
ad3fea08 TS |
13183 | else if (strcmp (name, "gp=default") == 0) |
13184 | mips_opts.gp32 = file_mips_gp32; | |
13185 | else if (strcmp (name, "gp=32") == 0) | |
13186 | mips_opts.gp32 = 1; | |
13187 | else if (strcmp (name, "gp=64") == 0) | |
13188 | { | |
13189 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 13190 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
13191 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13192 | mips_opts.gp32 = 0; | |
13193 | } | |
13194 | else if (strcmp (name, "fp=default") == 0) | |
13195 | mips_opts.fp32 = file_mips_fp32; | |
13196 | else if (strcmp (name, "fp=32") == 0) | |
13197 | mips_opts.fp32 = 1; | |
13198 | else if (strcmp (name, "fp=64") == 0) | |
13199 | { | |
13200 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 13201 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
13202 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13203 | mips_opts.fp32 = 0; | |
13204 | } | |
037b32b9 AN |
13205 | else if (strcmp (name, "softfloat") == 0) |
13206 | mips_opts.soft_float = 1; | |
13207 | else if (strcmp (name, "hardfloat") == 0) | |
13208 | mips_opts.soft_float = 0; | |
13209 | else if (strcmp (name, "singlefloat") == 0) | |
13210 | mips_opts.single_float = 1; | |
13211 | else if (strcmp (name, "doublefloat") == 0) | |
13212 | mips_opts.single_float = 0; | |
252b5132 RH |
13213 | else if (strcmp (name, "mips16") == 0 |
13214 | || strcmp (name, "MIPS-16") == 0) | |
13215 | mips_opts.mips16 = 1; | |
13216 | else if (strcmp (name, "nomips16") == 0 | |
13217 | || strcmp (name, "noMIPS-16") == 0) | |
13218 | mips_opts.mips16 = 0; | |
e16bfa71 TS |
13219 | else if (strcmp (name, "smartmips") == 0) |
13220 | { | |
ad3fea08 | 13221 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 13222 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 TS |
13223 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13224 | mips_opts.ase_smartmips = 1; | |
13225 | } | |
13226 | else if (strcmp (name, "nosmartmips") == 0) | |
13227 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
13228 | else if (strcmp (name, "mips3d") == 0) |
13229 | mips_opts.ase_mips3d = 1; | |
13230 | else if (strcmp (name, "nomips3d") == 0) | |
13231 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
13232 | else if (strcmp (name, "mdmx") == 0) |
13233 | mips_opts.ase_mdmx = 1; | |
13234 | else if (strcmp (name, "nomdmx") == 0) | |
13235 | mips_opts.ase_mdmx = 0; | |
74cd071d | 13236 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
13237 | { |
13238 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 13239 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 TS |
13240 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13241 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 13242 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 13243 | } |
74cd071d | 13244 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
13245 | { |
13246 | mips_opts.ase_dsp = 0; | |
13247 | mips_opts.ase_dspr2 = 0; | |
13248 | } | |
13249 | else if (strcmp (name, "dspr2") == 0) | |
13250 | { | |
13251 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 13252 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 TS |
13253 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13254 | mips_opts.ase_dspr2 = 1; | |
13255 | mips_opts.ase_dsp = 1; | |
13256 | } | |
13257 | else if (strcmp (name, "nodspr2") == 0) | |
13258 | { | |
13259 | mips_opts.ase_dspr2 = 0; | |
13260 | mips_opts.ase_dsp = 0; | |
13261 | } | |
ef2e4d86 | 13262 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
13263 | { |
13264 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 13265 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 TS |
13266 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13267 | mips_opts.ase_mt = 1; | |
13268 | } | |
ef2e4d86 CF |
13269 | else if (strcmp (name, "nomt") == 0) |
13270 | mips_opts.ase_mt = 0; | |
1a2c1fad | 13271 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 13272 | { |
af7ee8bf | 13273 | int reset = 0; |
252b5132 | 13274 | |
1a2c1fad CD |
13275 | /* Permit the user to change the ISA and architecture on the fly. |
13276 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 13277 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
13278 | { |
13279 | reset = 1; | |
13280 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 13281 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
13282 | } |
13283 | else if (strncmp (name, "arch=", 5) == 0) | |
13284 | { | |
13285 | const struct mips_cpu_info *p; | |
13286 | ||
13287 | p = mips_parse_cpu("internal use", name + 5); | |
13288 | if (!p) | |
13289 | as_bad (_("unknown architecture %s"), name + 5); | |
13290 | else | |
13291 | { | |
13292 | mips_opts.arch = p->cpu; | |
13293 | mips_opts.isa = p->isa; | |
13294 | } | |
13295 | } | |
81a21e38 TS |
13296 | else if (strncmp (name, "mips", 4) == 0) |
13297 | { | |
13298 | const struct mips_cpu_info *p; | |
13299 | ||
13300 | p = mips_parse_cpu("internal use", name); | |
13301 | if (!p) | |
13302 | as_bad (_("unknown ISA level %s"), name + 4); | |
13303 | else | |
13304 | { | |
13305 | mips_opts.arch = p->cpu; | |
13306 | mips_opts.isa = p->isa; | |
13307 | } | |
13308 | } | |
af7ee8bf | 13309 | else |
81a21e38 | 13310 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
13311 | |
13312 | switch (mips_opts.isa) | |
98d3f06f KH |
13313 | { |
13314 | case 0: | |
98d3f06f | 13315 | break; |
af7ee8bf CD |
13316 | case ISA_MIPS1: |
13317 | case ISA_MIPS2: | |
13318 | case ISA_MIPS32: | |
13319 | case ISA_MIPS32R2: | |
98d3f06f KH |
13320 | mips_opts.gp32 = 1; |
13321 | mips_opts.fp32 = 1; | |
13322 | break; | |
af7ee8bf CD |
13323 | case ISA_MIPS3: |
13324 | case ISA_MIPS4: | |
13325 | case ISA_MIPS5: | |
13326 | case ISA_MIPS64: | |
5f74bc13 | 13327 | case ISA_MIPS64R2: |
98d3f06f KH |
13328 | mips_opts.gp32 = 0; |
13329 | mips_opts.fp32 = 0; | |
13330 | break; | |
13331 | default: | |
13332 | as_bad (_("unknown ISA level %s"), name + 4); | |
13333 | break; | |
13334 | } | |
af7ee8bf | 13335 | if (reset) |
98d3f06f | 13336 | { |
af7ee8bf CD |
13337 | mips_opts.gp32 = file_mips_gp32; |
13338 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 13339 | } |
252b5132 RH |
13340 | } |
13341 | else if (strcmp (name, "autoextend") == 0) | |
13342 | mips_opts.noautoextend = 0; | |
13343 | else if (strcmp (name, "noautoextend") == 0) | |
13344 | mips_opts.noautoextend = 1; | |
13345 | else if (strcmp (name, "push") == 0) | |
13346 | { | |
13347 | struct mips_option_stack *s; | |
13348 | ||
13349 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
13350 | s->next = mips_opts_stack; | |
13351 | s->options = mips_opts; | |
13352 | mips_opts_stack = s; | |
13353 | } | |
13354 | else if (strcmp (name, "pop") == 0) | |
13355 | { | |
13356 | struct mips_option_stack *s; | |
13357 | ||
13358 | s = mips_opts_stack; | |
13359 | if (s == NULL) | |
13360 | as_bad (_(".set pop with no .set push")); | |
13361 | else | |
13362 | { | |
13363 | /* If we're changing the reorder mode we need to handle | |
13364 | delay slots correctly. */ | |
13365 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 13366 | start_noreorder (); |
252b5132 | 13367 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 13368 | end_noreorder (); |
252b5132 RH |
13369 | |
13370 | mips_opts = s->options; | |
13371 | mips_opts_stack = s->next; | |
13372 | free (s); | |
13373 | } | |
13374 | } | |
aed1a261 RS |
13375 | else if (strcmp (name, "sym32") == 0) |
13376 | mips_opts.sym32 = TRUE; | |
13377 | else if (strcmp (name, "nosym32") == 0) | |
13378 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
13379 | else if (strchr (name, ',')) |
13380 | { | |
13381 | /* Generic ".set" directive; use the generic handler. */ | |
13382 | *input_line_pointer = ch; | |
13383 | input_line_pointer = name; | |
13384 | s_set (0); | |
13385 | return; | |
13386 | } | |
252b5132 RH |
13387 | else |
13388 | { | |
13389 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
13390 | } | |
13391 | *input_line_pointer = ch; | |
13392 | demand_empty_rest_of_line (); | |
13393 | } | |
13394 | ||
13395 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
13396 | .option pic2. It means to generate SVR4 PIC calls. */ | |
13397 | ||
13398 | static void | |
17a2f251 | 13399 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13400 | { |
13401 | mips_pic = SVR4_PIC; | |
143d77c5 | 13402 | mips_abicalls = TRUE; |
4d0d148d TS |
13403 | |
13404 | if (g_switch_seen && g_switch_value != 0) | |
13405 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
13406 | g_switch_value = 0; | |
13407 | ||
252b5132 RH |
13408 | bfd_set_gp_size (stdoutput, 0); |
13409 | demand_empty_rest_of_line (); | |
13410 | } | |
13411 | ||
13412 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
13413 | PIC code. It sets the $gp register for the function based on the | |
13414 | function address, which is in the register named in the argument. | |
13415 | This uses a relocation against _gp_disp, which is handled specially | |
13416 | by the linker. The result is: | |
13417 | lui $gp,%hi(_gp_disp) | |
13418 | addiu $gp,$gp,%lo(_gp_disp) | |
13419 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
13420 | The .cpload argument is normally $25 == $t9. |
13421 | ||
13422 | The -mno-shared option changes this to: | |
bbe506e8 TS |
13423 | lui $gp,%hi(__gnu_local_gp) |
13424 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
13425 | and the argument is ignored. This saves an instruction, but the |
13426 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
13427 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
13428 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
13429 | |
13430 | static void | |
17a2f251 | 13431 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13432 | { |
13433 | expressionS ex; | |
aa6975fb ILT |
13434 | int reg; |
13435 | int in_shared; | |
252b5132 | 13436 | |
6478892d TS |
13437 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
13438 | .cpload is ignored. */ | |
13439 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
13440 | { |
13441 | s_ignore (0); | |
13442 | return; | |
13443 | } | |
13444 | ||
d3ecfc59 | 13445 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
13446 | if (mips_opts.noreorder == 0) |
13447 | as_warn (_(".cpload not in noreorder section")); | |
13448 | ||
aa6975fb ILT |
13449 | reg = tc_get_register (0); |
13450 | ||
13451 | /* If we need to produce a 64-bit address, we are better off using | |
13452 | the default instruction sequence. */ | |
aed1a261 | 13453 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 13454 | |
252b5132 | 13455 | ex.X_op = O_symbol; |
bbe506e8 TS |
13456 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
13457 | "__gnu_local_gp"); | |
252b5132 RH |
13458 | ex.X_op_symbol = NULL; |
13459 | ex.X_add_number = 0; | |
13460 | ||
13461 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 13462 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 13463 | |
584892a6 | 13464 | macro_start (); |
67c0d1eb RS |
13465 | macro_build_lui (&ex, mips_gp_register); |
13466 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 13467 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
13468 | if (in_shared) |
13469 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
13470 | mips_gp_register, reg); | |
584892a6 | 13471 | macro_end (); |
252b5132 RH |
13472 | |
13473 | demand_empty_rest_of_line (); | |
13474 | } | |
13475 | ||
6478892d TS |
13476 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
13477 | .cpsetup $reg1, offset|$reg2, label | |
13478 | ||
13479 | If offset is given, this results in: | |
13480 | sd $gp, offset($sp) | |
956cd1d6 | 13481 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
13482 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
13483 | daddu $gp, $gp, $reg1 | |
6478892d TS |
13484 | |
13485 | If $reg2 is given, this results in: | |
13486 | daddu $reg2, $gp, $0 | |
956cd1d6 | 13487 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
13488 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
13489 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
13490 | $reg1 is normally $25 == $t9. |
13491 | ||
13492 | The -mno-shared option replaces the last three instructions with | |
13493 | lui $gp,%hi(_gp) | |
54f4ddb3 | 13494 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 13495 | |
6478892d | 13496 | static void |
17a2f251 | 13497 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13498 | { |
13499 | expressionS ex_off; | |
13500 | expressionS ex_sym; | |
13501 | int reg1; | |
6478892d | 13502 | |
8586fc66 | 13503 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
13504 | We also need NewABI support. */ |
13505 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13506 | { | |
13507 | s_ignore (0); | |
13508 | return; | |
13509 | } | |
13510 | ||
13511 | reg1 = tc_get_register (0); | |
13512 | SKIP_WHITESPACE (); | |
13513 | if (*input_line_pointer != ',') | |
13514 | { | |
13515 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
13516 | return; | |
13517 | } | |
13518 | else | |
80245285 | 13519 | ++input_line_pointer; |
6478892d TS |
13520 | SKIP_WHITESPACE (); |
13521 | if (*input_line_pointer == '$') | |
80245285 TS |
13522 | { |
13523 | mips_cpreturn_register = tc_get_register (0); | |
13524 | mips_cpreturn_offset = -1; | |
13525 | } | |
6478892d | 13526 | else |
80245285 TS |
13527 | { |
13528 | mips_cpreturn_offset = get_absolute_expression (); | |
13529 | mips_cpreturn_register = -1; | |
13530 | } | |
6478892d TS |
13531 | SKIP_WHITESPACE (); |
13532 | if (*input_line_pointer != ',') | |
13533 | { | |
13534 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
13535 | return; | |
13536 | } | |
13537 | else | |
f9419b05 | 13538 | ++input_line_pointer; |
6478892d | 13539 | SKIP_WHITESPACE (); |
f21f8242 | 13540 | expression (&ex_sym); |
6478892d | 13541 | |
584892a6 | 13542 | macro_start (); |
6478892d TS |
13543 | if (mips_cpreturn_register == -1) |
13544 | { | |
13545 | ex_off.X_op = O_constant; | |
13546 | ex_off.X_add_symbol = NULL; | |
13547 | ex_off.X_op_symbol = NULL; | |
13548 | ex_off.X_add_number = mips_cpreturn_offset; | |
13549 | ||
67c0d1eb | 13550 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 13551 | BFD_RELOC_LO16, SP); |
6478892d TS |
13552 | } |
13553 | else | |
67c0d1eb | 13554 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 13555 | mips_gp_register, 0); |
6478892d | 13556 | |
aed1a261 | 13557 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
13558 | { |
13559 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
13560 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
13561 | BFD_RELOC_HI16_S); | |
13562 | ||
13563 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
13564 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
13565 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
13566 | ||
13567 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
13568 | mips_gp_register, reg1); | |
13569 | } | |
13570 | else | |
13571 | { | |
13572 | expressionS ex; | |
13573 | ||
13574 | ex.X_op = O_symbol; | |
4184909a | 13575 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
13576 | ex.X_op_symbol = NULL; |
13577 | ex.X_add_number = 0; | |
6e1304d8 | 13578 | |
aa6975fb ILT |
13579 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
13580 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
13581 | ||
13582 | macro_build_lui (&ex, mips_gp_register); | |
13583 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
13584 | mips_gp_register, BFD_RELOC_LO16); | |
13585 | } | |
f21f8242 | 13586 | |
584892a6 | 13587 | macro_end (); |
6478892d TS |
13588 | |
13589 | demand_empty_rest_of_line (); | |
13590 | } | |
13591 | ||
13592 | static void | |
17a2f251 | 13593 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13594 | { |
13595 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 13596 | .cplocal is ignored. */ |
6478892d TS |
13597 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
13598 | { | |
13599 | s_ignore (0); | |
13600 | return; | |
13601 | } | |
13602 | ||
13603 | mips_gp_register = tc_get_register (0); | |
85b51719 | 13604 | demand_empty_rest_of_line (); |
6478892d TS |
13605 | } |
13606 | ||
252b5132 RH |
13607 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
13608 | offset from $sp. The offset is remembered, and after making a PIC | |
13609 | call $gp is restored from that location. */ | |
13610 | ||
13611 | static void | |
17a2f251 | 13612 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13613 | { |
13614 | expressionS ex; | |
252b5132 | 13615 | |
6478892d | 13616 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 13617 | .cprestore is ignored. */ |
6478892d | 13618 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
13619 | { |
13620 | s_ignore (0); | |
13621 | return; | |
13622 | } | |
13623 | ||
13624 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 13625 | mips_cprestore_valid = 1; |
252b5132 RH |
13626 | |
13627 | ex.X_op = O_constant; | |
13628 | ex.X_add_symbol = NULL; | |
13629 | ex.X_op_symbol = NULL; | |
13630 | ex.X_add_number = mips_cprestore_offset; | |
13631 | ||
584892a6 | 13632 | macro_start (); |
67c0d1eb RS |
13633 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
13634 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 13635 | macro_end (); |
252b5132 RH |
13636 | |
13637 | demand_empty_rest_of_line (); | |
13638 | } | |
13639 | ||
6478892d | 13640 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 13641 | was given in the preceding .cpsetup, it results in: |
6478892d | 13642 | ld $gp, offset($sp) |
76b3015f | 13643 | |
6478892d | 13644 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
13645 | daddu $gp, $reg2, $0 */ |
13646 | ||
6478892d | 13647 | static void |
17a2f251 | 13648 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13649 | { |
13650 | expressionS ex; | |
6478892d TS |
13651 | |
13652 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
13653 | We also need NewABI support. */ | |
13654 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13655 | { | |
13656 | s_ignore (0); | |
13657 | return; | |
13658 | } | |
13659 | ||
584892a6 | 13660 | macro_start (); |
6478892d TS |
13661 | if (mips_cpreturn_register == -1) |
13662 | { | |
13663 | ex.X_op = O_constant; | |
13664 | ex.X_add_symbol = NULL; | |
13665 | ex.X_op_symbol = NULL; | |
13666 | ex.X_add_number = mips_cpreturn_offset; | |
13667 | ||
67c0d1eb | 13668 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
13669 | } |
13670 | else | |
67c0d1eb | 13671 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 13672 | mips_cpreturn_register, 0); |
584892a6 | 13673 | macro_end (); |
6478892d TS |
13674 | |
13675 | demand_empty_rest_of_line (); | |
13676 | } | |
13677 | ||
741d6ea8 JM |
13678 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate |
13679 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
13680 | use in DWARF debug information. */ | |
13681 | ||
13682 | static void | |
13683 | s_dtprel_internal (size_t bytes) | |
13684 | { | |
13685 | expressionS ex; | |
13686 | char *p; | |
13687 | ||
13688 | expression (&ex); | |
13689 | ||
13690 | if (ex.X_op != O_symbol) | |
13691 | { | |
13692 | as_bad (_("Unsupported use of %s"), (bytes == 8 | |
13693 | ? ".dtpreldword" | |
13694 | : ".dtprelword")); | |
13695 | ignore_rest_of_line (); | |
13696 | } | |
13697 | ||
13698 | p = frag_more (bytes); | |
13699 | md_number_to_chars (p, 0, bytes); | |
13700 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, | |
13701 | (bytes == 8 | |
13702 | ? BFD_RELOC_MIPS_TLS_DTPREL64 | |
13703 | : BFD_RELOC_MIPS_TLS_DTPREL32)); | |
13704 | ||
13705 | demand_empty_rest_of_line (); | |
13706 | } | |
13707 | ||
13708 | /* Handle .dtprelword. */ | |
13709 | ||
13710 | static void | |
13711 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
13712 | { | |
13713 | s_dtprel_internal (4); | |
13714 | } | |
13715 | ||
13716 | /* Handle .dtpreldword. */ | |
13717 | ||
13718 | static void | |
13719 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
13720 | { | |
13721 | s_dtprel_internal (8); | |
13722 | } | |
13723 | ||
6478892d TS |
13724 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
13725 | code. It sets the offset to use in gp_rel relocations. */ | |
13726 | ||
13727 | static void | |
17a2f251 | 13728 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13729 | { |
13730 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
13731 | We also need NewABI support. */ | |
13732 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13733 | { | |
13734 | s_ignore (0); | |
13735 | return; | |
13736 | } | |
13737 | ||
def2e0dd | 13738 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
13739 | |
13740 | demand_empty_rest_of_line (); | |
13741 | } | |
13742 | ||
252b5132 RH |
13743 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
13744 | code. It generates a 32 bit GP relative reloc. */ | |
13745 | ||
13746 | static void | |
17a2f251 | 13747 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13748 | { |
a8dbcb85 TS |
13749 | segment_info_type *si; |
13750 | struct insn_label_list *l; | |
252b5132 RH |
13751 | symbolS *label; |
13752 | expressionS ex; | |
13753 | char *p; | |
13754 | ||
13755 | /* When not generating PIC code, this is treated as .word. */ | |
13756 | if (mips_pic != SVR4_PIC) | |
13757 | { | |
13758 | s_cons (2); | |
13759 | return; | |
13760 | } | |
13761 | ||
a8dbcb85 TS |
13762 | si = seg_info (now_seg); |
13763 | l = si->label_list; | |
13764 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13765 | mips_emit_delays (); |
252b5132 RH |
13766 | if (auto_align) |
13767 | mips_align (2, 0, label); | |
252b5132 RH |
13768 | |
13769 | expression (&ex); | |
a1facbec | 13770 | mips_clear_insn_labels (); |
252b5132 RH |
13771 | |
13772 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13773 | { | |
13774 | as_bad (_("Unsupported use of .gpword")); | |
13775 | ignore_rest_of_line (); | |
13776 | } | |
13777 | ||
13778 | p = frag_more (4); | |
17a2f251 | 13779 | md_number_to_chars (p, 0, 4); |
b34976b6 | 13780 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 13781 | BFD_RELOC_GPREL32); |
252b5132 RH |
13782 | |
13783 | demand_empty_rest_of_line (); | |
13784 | } | |
13785 | ||
10181a0d | 13786 | static void |
17a2f251 | 13787 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 13788 | { |
a8dbcb85 TS |
13789 | segment_info_type *si; |
13790 | struct insn_label_list *l; | |
10181a0d AO |
13791 | symbolS *label; |
13792 | expressionS ex; | |
13793 | char *p; | |
13794 | ||
13795 | /* When not generating PIC code, this is treated as .dword. */ | |
13796 | if (mips_pic != SVR4_PIC) | |
13797 | { | |
13798 | s_cons (3); | |
13799 | return; | |
13800 | } | |
13801 | ||
a8dbcb85 TS |
13802 | si = seg_info (now_seg); |
13803 | l = si->label_list; | |
13804 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13805 | mips_emit_delays (); |
10181a0d AO |
13806 | if (auto_align) |
13807 | mips_align (3, 0, label); | |
10181a0d AO |
13808 | |
13809 | expression (&ex); | |
a1facbec | 13810 | mips_clear_insn_labels (); |
10181a0d AO |
13811 | |
13812 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13813 | { | |
13814 | as_bad (_("Unsupported use of .gpdword")); | |
13815 | ignore_rest_of_line (); | |
13816 | } | |
13817 | ||
13818 | p = frag_more (8); | |
17a2f251 | 13819 | md_number_to_chars (p, 0, 8); |
a105a300 | 13820 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 13821 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
13822 | |
13823 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
13824 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
13825 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
13826 | |
13827 | demand_empty_rest_of_line (); | |
13828 | } | |
13829 | ||
252b5132 RH |
13830 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
13831 | tables in SVR4 PIC code. */ | |
13832 | ||
13833 | static void | |
17a2f251 | 13834 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13835 | { |
252b5132 RH |
13836 | int reg; |
13837 | ||
10181a0d AO |
13838 | /* This is ignored when not generating SVR4 PIC code. */ |
13839 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
13840 | { |
13841 | s_ignore (0); | |
13842 | return; | |
13843 | } | |
13844 | ||
13845 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 13846 | macro_start (); |
252b5132 | 13847 | reg = tc_get_register (0); |
67c0d1eb | 13848 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 13849 | macro_end (); |
252b5132 | 13850 | |
bdaaa2e1 | 13851 | demand_empty_rest_of_line (); |
252b5132 RH |
13852 | } |
13853 | ||
13854 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
13855 | mips16 mode. This permits the linker to handle them specially, | |
13856 | such as generating jalx instructions when needed. We also make | |
13857 | them odd for the duration of the assembly, in order to generate the | |
13858 | right sort of code. We will make them even in the adjust_symtab | |
13859 | routine, while leaving them marked. This is convenient for the | |
13860 | debugger and the disassembler. The linker knows to make them odd | |
13861 | again. */ | |
13862 | ||
13863 | static void | |
17a2f251 | 13864 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13865 | { |
f9419b05 | 13866 | mips16_mark_labels (); |
252b5132 RH |
13867 | |
13868 | demand_empty_rest_of_line (); | |
13869 | } | |
13870 | ||
13871 | /* Handle a .stabn directive. We need these in order to mark a label | |
13872 | as being a mips16 text label correctly. Sometimes the compiler | |
13873 | will emit a label, followed by a .stabn, and then switch sections. | |
13874 | If the label and .stabn are in mips16 mode, then the label is | |
13875 | really a mips16 text label. */ | |
13876 | ||
13877 | static void | |
17a2f251 | 13878 | s_mips_stab (int type) |
252b5132 | 13879 | { |
f9419b05 | 13880 | if (type == 'n') |
252b5132 RH |
13881 | mips16_mark_labels (); |
13882 | ||
13883 | s_stab (type); | |
13884 | } | |
13885 | ||
54f4ddb3 | 13886 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
13887 | |
13888 | static void | |
17a2f251 | 13889 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13890 | { |
13891 | char *name; | |
13892 | int c; | |
13893 | symbolS *symbolP; | |
13894 | expressionS exp; | |
13895 | ||
13896 | name = input_line_pointer; | |
13897 | c = get_symbol_end (); | |
13898 | symbolP = symbol_find_or_make (name); | |
13899 | S_SET_WEAK (symbolP); | |
13900 | *input_line_pointer = c; | |
13901 | ||
13902 | SKIP_WHITESPACE (); | |
13903 | ||
13904 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
13905 | { | |
13906 | if (S_IS_DEFINED (symbolP)) | |
13907 | { | |
20203fb9 | 13908 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
13909 | S_GET_NAME (symbolP)); |
13910 | ignore_rest_of_line (); | |
13911 | return; | |
13912 | } | |
bdaaa2e1 | 13913 | |
252b5132 RH |
13914 | if (*input_line_pointer == ',') |
13915 | { | |
13916 | ++input_line_pointer; | |
13917 | SKIP_WHITESPACE (); | |
13918 | } | |
bdaaa2e1 | 13919 | |
252b5132 RH |
13920 | expression (&exp); |
13921 | if (exp.X_op != O_symbol) | |
13922 | { | |
20203fb9 | 13923 | as_bad (_("bad .weakext directive")); |
98d3f06f | 13924 | ignore_rest_of_line (); |
252b5132 RH |
13925 | return; |
13926 | } | |
49309057 | 13927 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
13928 | } |
13929 | ||
13930 | demand_empty_rest_of_line (); | |
13931 | } | |
13932 | ||
13933 | /* Parse a register string into a number. Called from the ECOFF code | |
13934 | to parse .frame. The argument is non-zero if this is the frame | |
13935 | register, so that we can record it in mips_frame_reg. */ | |
13936 | ||
13937 | int | |
17a2f251 | 13938 | tc_get_register (int frame) |
252b5132 | 13939 | { |
707bfff6 | 13940 | unsigned int reg; |
252b5132 RH |
13941 | |
13942 | SKIP_WHITESPACE (); | |
707bfff6 TS |
13943 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
13944 | reg = 0; | |
252b5132 | 13945 | if (frame) |
7a621144 DJ |
13946 | { |
13947 | mips_frame_reg = reg != 0 ? reg : SP; | |
13948 | mips_frame_reg_valid = 1; | |
13949 | mips_cprestore_valid = 0; | |
13950 | } | |
252b5132 RH |
13951 | return reg; |
13952 | } | |
13953 | ||
13954 | valueT | |
17a2f251 | 13955 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
13956 | { |
13957 | int align = bfd_get_section_alignment (stdoutput, seg); | |
13958 | ||
b4c71f56 TS |
13959 | if (IS_ELF) |
13960 | { | |
13961 | /* We don't need to align ELF sections to the full alignment. | |
13962 | However, Irix 5 may prefer that we align them at least to a 16 | |
13963 | byte boundary. We don't bother to align the sections if we | |
13964 | are targeted for an embedded system. */ | |
c41e87e3 | 13965 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
13966 | return addr; |
13967 | if (align > 4) | |
13968 | align = 4; | |
13969 | } | |
252b5132 RH |
13970 | |
13971 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
13972 | } | |
13973 | ||
13974 | /* Utility routine, called from above as well. If called while the | |
13975 | input file is still being read, it's only an approximation. (For | |
13976 | example, a symbol may later become defined which appeared to be | |
13977 | undefined earlier.) */ | |
13978 | ||
13979 | static int | |
17a2f251 | 13980 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
13981 | { |
13982 | if (sym == 0) | |
13983 | return 0; | |
13984 | ||
4d0d148d | 13985 | if (g_switch_value > 0) |
252b5132 RH |
13986 | { |
13987 | const char *symname; | |
13988 | int change; | |
13989 | ||
c9914766 | 13990 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
13991 | register. It can be if it is smaller than the -G size or if |
13992 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 13993 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
13994 | they can. */ |
13995 | symname = S_GET_NAME (sym); | |
13996 | if (symname != (const char *) NULL | |
13997 | && (strcmp (symname, "eprol") == 0 | |
13998 | || strcmp (symname, "etext") == 0 | |
13999 | || strcmp (symname, "_gp") == 0 | |
14000 | || strcmp (symname, "edata") == 0 | |
14001 | || strcmp (symname, "_fbss") == 0 | |
14002 | || strcmp (symname, "_fdata") == 0 | |
14003 | || strcmp (symname, "_ftext") == 0 | |
14004 | || strcmp (symname, "end") == 0 | |
14005 | || strcmp (symname, "_gp_disp") == 0)) | |
14006 | change = 1; | |
14007 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
14008 | && (0 | |
14009 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
14010 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
14011 | && (symbol_get_obj (sym)->ecoff_extern_size | |
14012 | <= g_switch_value)) | |
252b5132 RH |
14013 | #endif |
14014 | /* We must defer this decision until after the whole | |
14015 | file has been read, since there might be a .extern | |
14016 | after the first use of this symbol. */ | |
14017 | || (before_relaxing | |
14018 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 14019 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
14020 | #endif |
14021 | && S_GET_VALUE (sym) == 0) | |
14022 | || (S_GET_VALUE (sym) != 0 | |
14023 | && S_GET_VALUE (sym) <= g_switch_value))) | |
14024 | change = 0; | |
14025 | else | |
14026 | { | |
14027 | const char *segname; | |
14028 | ||
14029 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 14030 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
14031 | && strcmp (segname, ".lit4") != 0); |
14032 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
14033 | && strcmp (segname, ".sbss") != 0 |
14034 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
14035 | && strncmp (segname, ".sbss.", 6) != 0 |
14036 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 14037 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
14038 | } |
14039 | return change; | |
14040 | } | |
14041 | else | |
c9914766 | 14042 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
14043 | return 1; |
14044 | } | |
14045 | ||
5919d012 RS |
14046 | |
14047 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
14048 | ||
14049 | static bfd_boolean | |
17a2f251 | 14050 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
14051 | { |
14052 | asection *symsec; | |
5919d012 RS |
14053 | |
14054 | /* Handle the case of a symbol equated to another symbol. */ | |
14055 | while (symbol_equated_reloc_p (sym)) | |
14056 | { | |
14057 | symbolS *n; | |
14058 | ||
5f0fe04b | 14059 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
14060 | n = symbol_get_value_expression (sym)->X_add_symbol; |
14061 | if (n == sym) | |
14062 | break; | |
14063 | sym = n; | |
14064 | } | |
14065 | ||
df1f3cda DD |
14066 | if (symbol_section_p (sym)) |
14067 | return TRUE; | |
14068 | ||
5919d012 RS |
14069 | symsec = S_GET_SEGMENT (sym); |
14070 | ||
5919d012 RS |
14071 | /* This must duplicate the test in adjust_reloc_syms. */ |
14072 | return (symsec != &bfd_und_section | |
14073 | && symsec != &bfd_abs_section | |
5f0fe04b TS |
14074 | && !bfd_is_com_section (symsec) |
14075 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
14076 | #ifdef OBJ_ELF |
14077 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 14078 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
14079 | #endif |
14080 | ); | |
14081 | } | |
14082 | ||
14083 | ||
252b5132 RH |
14084 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
14085 | extended opcode. SEC is the section the frag is in. */ | |
14086 | ||
14087 | static int | |
17a2f251 | 14088 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
14089 | { |
14090 | int type; | |
3994f87e | 14091 | const struct mips16_immed_operand *op; |
252b5132 RH |
14092 | offsetT val; |
14093 | int mintiny, maxtiny; | |
14094 | segT symsec; | |
98aa84af | 14095 | fragS *sym_frag; |
252b5132 RH |
14096 | |
14097 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
14098 | return 0; | |
14099 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
14100 | return 1; | |
14101 | ||
14102 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
14103 | op = mips16_immed_operands; | |
14104 | while (op->type != type) | |
14105 | { | |
14106 | ++op; | |
9c2799c2 | 14107 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
14108 | } |
14109 | ||
14110 | if (op->unsp) | |
14111 | { | |
14112 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
14113 | { | |
14114 | mintiny = 1; | |
14115 | maxtiny = 1 << op->nbits; | |
14116 | } | |
14117 | else | |
14118 | { | |
14119 | mintiny = 0; | |
14120 | maxtiny = (1 << op->nbits) - 1; | |
14121 | } | |
14122 | } | |
14123 | else | |
14124 | { | |
14125 | mintiny = - (1 << (op->nbits - 1)); | |
14126 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
14127 | } | |
14128 | ||
98aa84af | 14129 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 14130 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 14131 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
14132 | |
14133 | if (op->pcrel) | |
14134 | { | |
14135 | addressT addr; | |
14136 | ||
14137 | /* We won't have the section when we are called from | |
14138 | mips_relax_frag. However, we will always have been called | |
14139 | from md_estimate_size_before_relax first. If this is a | |
14140 | branch to a different section, we mark it as such. If SEC is | |
14141 | NULL, and the frag is not marked, then it must be a branch to | |
14142 | the same section. */ | |
14143 | if (sec == NULL) | |
14144 | { | |
14145 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
14146 | return 1; | |
14147 | } | |
14148 | else | |
14149 | { | |
98aa84af | 14150 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
14151 | if (symsec != sec) |
14152 | { | |
14153 | fragp->fr_subtype = | |
14154 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
14155 | ||
14156 | /* FIXME: We should support this, and let the linker | |
14157 | catch branches and loads that are out of range. */ | |
14158 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
14159 | _("unsupported PC relative reference to different section")); | |
14160 | ||
14161 | return 1; | |
14162 | } | |
98aa84af AM |
14163 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
14164 | /* Assume non-extended on the first relaxation pass. | |
14165 | The address we have calculated will be bogus if this is | |
14166 | a forward branch to another frag, as the forward frag | |
14167 | will have fr_address == 0. */ | |
14168 | return 0; | |
252b5132 RH |
14169 | } |
14170 | ||
14171 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
14172 | the same section. If the relax_marker of the symbol fragment |
14173 | differs from the relax_marker of this fragment, we have not | |
14174 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
14175 | in STRETCH in order to get a better estimate of the address. |
14176 | This particularly matters because of the shift bits. */ | |
14177 | if (stretch != 0 | |
98aa84af | 14178 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
14179 | { |
14180 | fragS *f; | |
14181 | ||
14182 | /* Adjust stretch for any alignment frag. Note that if have | |
14183 | been expanding the earlier code, the symbol may be | |
14184 | defined in what appears to be an earlier frag. FIXME: | |
14185 | This doesn't handle the fr_subtype field, which specifies | |
14186 | a maximum number of bytes to skip when doing an | |
14187 | alignment. */ | |
98aa84af | 14188 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
14189 | { |
14190 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
14191 | { | |
14192 | if (stretch < 0) | |
14193 | stretch = - ((- stretch) | |
14194 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
14195 | else | |
14196 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
14197 | if (stretch == 0) | |
14198 | break; | |
14199 | } | |
14200 | } | |
14201 | if (f != NULL) | |
14202 | val += stretch; | |
14203 | } | |
14204 | ||
14205 | addr = fragp->fr_address + fragp->fr_fix; | |
14206 | ||
14207 | /* The base address rules are complicated. The base address of | |
14208 | a branch is the following instruction. The base address of a | |
14209 | PC relative load or add is the instruction itself, but if it | |
14210 | is in a delay slot (in which case it can not be extended) use | |
14211 | the address of the instruction whose delay slot it is in. */ | |
14212 | if (type == 'p' || type == 'q') | |
14213 | { | |
14214 | addr += 2; | |
14215 | ||
14216 | /* If we are currently assuming that this frag should be | |
14217 | extended, then, the current address is two bytes | |
bdaaa2e1 | 14218 | higher. */ |
252b5132 RH |
14219 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
14220 | addr += 2; | |
14221 | ||
14222 | /* Ignore the low bit in the target, since it will be set | |
14223 | for a text label. */ | |
14224 | if ((val & 1) != 0) | |
14225 | --val; | |
14226 | } | |
14227 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
14228 | addr -= 4; | |
14229 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
14230 | addr -= 2; | |
14231 | ||
14232 | val -= addr & ~ ((1 << op->shift) - 1); | |
14233 | ||
14234 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
14235 | if (type == 'p' || type == 'q') | |
14236 | val /= 2; | |
14237 | ||
14238 | /* If any of the shifted bits are set, we must use an extended | |
14239 | opcode. If the address depends on the size of this | |
14240 | instruction, this can lead to a loop, so we arrange to always | |
14241 | use an extended opcode. We only check this when we are in | |
14242 | the main relaxation loop, when SEC is NULL. */ | |
14243 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
14244 | { | |
14245 | fragp->fr_subtype = | |
14246 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
14247 | return 1; | |
14248 | } | |
14249 | ||
14250 | /* If we are about to mark a frag as extended because the value | |
14251 | is precisely maxtiny + 1, then there is a chance of an | |
14252 | infinite loop as in the following code: | |
14253 | la $4,foo | |
14254 | .skip 1020 | |
14255 | .align 2 | |
14256 | foo: | |
14257 | In this case when the la is extended, foo is 0x3fc bytes | |
14258 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
14259 | the la must be extended. To avoid this loop, we mark the | |
14260 | frag as extended if it was small, and is about to become | |
14261 | extended with a value of maxtiny + 1. */ | |
14262 | if (val == ((maxtiny + 1) << op->shift) | |
14263 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
14264 | && sec == NULL) | |
14265 | { | |
14266 | fragp->fr_subtype = | |
14267 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
14268 | return 1; | |
14269 | } | |
14270 | } | |
14271 | else if (symsec != absolute_section && sec != NULL) | |
14272 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
14273 | ||
14274 | if ((val & ((1 << op->shift) - 1)) != 0 | |
14275 | || val < (mintiny << op->shift) | |
14276 | || val > (maxtiny << op->shift)) | |
14277 | return 1; | |
14278 | else | |
14279 | return 0; | |
14280 | } | |
14281 | ||
4a6a3df4 AO |
14282 | /* Compute the length of a branch sequence, and adjust the |
14283 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
14284 | worst-case length is computed, with UPDATE being used to indicate | |
14285 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
14286 | branch is to be computed. */ | |
14287 | static int | |
17a2f251 | 14288 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 14289 | { |
b34976b6 | 14290 | bfd_boolean toofar; |
4a6a3df4 AO |
14291 | int length; |
14292 | ||
14293 | if (fragp | |
14294 | && S_IS_DEFINED (fragp->fr_symbol) | |
14295 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
14296 | { | |
14297 | addressT addr; | |
14298 | offsetT val; | |
14299 | ||
14300 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
14301 | ||
14302 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
14303 | ||
14304 | val -= addr; | |
14305 | ||
14306 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
14307 | } | |
14308 | else if (fragp) | |
14309 | /* If the symbol is not defined or it's in a different segment, | |
14310 | assume the user knows what's going on and emit a short | |
14311 | branch. */ | |
b34976b6 | 14312 | toofar = FALSE; |
4a6a3df4 | 14313 | else |
b34976b6 | 14314 | toofar = TRUE; |
4a6a3df4 AO |
14315 | |
14316 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
14317 | fragp->fr_subtype | |
66b3e8da MR |
14318 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
14319 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
14320 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
14321 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
14322 | toofar); | |
14323 | ||
14324 | length = 4; | |
14325 | if (toofar) | |
14326 | { | |
14327 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
14328 | length += 8; | |
14329 | ||
14330 | if (mips_pic != NO_PIC) | |
14331 | { | |
14332 | /* Additional space for PIC loading of target address. */ | |
14333 | length += 8; | |
14334 | if (mips_opts.isa == ISA_MIPS1) | |
14335 | /* Additional space for $at-stabilizing nop. */ | |
14336 | length += 4; | |
14337 | } | |
14338 | ||
14339 | /* If branch is conditional. */ | |
14340 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
14341 | length += 8; | |
14342 | } | |
b34976b6 | 14343 | |
4a6a3df4 AO |
14344 | return length; |
14345 | } | |
14346 | ||
252b5132 RH |
14347 | /* Estimate the size of a frag before relaxing. Unless this is the |
14348 | mips16, we are not really relaxing here, and the final size is | |
14349 | encoded in the subtype information. For the mips16, we have to | |
14350 | decide whether we are using an extended opcode or not. */ | |
14351 | ||
252b5132 | 14352 | int |
17a2f251 | 14353 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 14354 | { |
5919d012 | 14355 | int change; |
252b5132 | 14356 | |
4a6a3df4 AO |
14357 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14358 | { | |
14359 | ||
b34976b6 AM |
14360 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
14361 | ||
4a6a3df4 AO |
14362 | return fragp->fr_var; |
14363 | } | |
14364 | ||
252b5132 | 14365 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
14366 | /* We don't want to modify the EXTENDED bit here; it might get us |
14367 | into infinite loops. We change it only in mips_relax_frag(). */ | |
14368 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
14369 | |
14370 | if (mips_pic == NO_PIC) | |
5919d012 | 14371 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 14372 | else if (mips_pic == SVR4_PIC) |
5919d012 | 14373 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
14374 | else if (mips_pic == VXWORKS_PIC) |
14375 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
14376 | change = 0; | |
252b5132 RH |
14377 | else |
14378 | abort (); | |
14379 | ||
14380 | if (change) | |
14381 | { | |
4d7206a2 | 14382 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 14383 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 14384 | } |
4d7206a2 RS |
14385 | else |
14386 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
14387 | } |
14388 | ||
14389 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 14390 | should be converted into a reloc against a section. */ |
252b5132 RH |
14391 | |
14392 | int | |
17a2f251 | 14393 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 14394 | { |
252b5132 RH |
14395 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
14396 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
14397 | return 0; | |
a161fe53 | 14398 | |
252b5132 RH |
14399 | if (fixp->fx_addsy == NULL) |
14400 | return 1; | |
a161fe53 | 14401 | |
de7e6852 RS |
14402 | /* If symbol SYM is in a mergeable section, relocations of the form |
14403 | SYM + 0 can usually be made section-relative. The mergeable data | |
14404 | is then identified by the section offset rather than by the symbol. | |
14405 | ||
14406 | However, if we're generating REL LO16 relocations, the offset is split | |
14407 | between the LO16 and parterning high part relocation. The linker will | |
14408 | need to recalculate the complete offset in order to correctly identify | |
14409 | the merge data. | |
14410 | ||
14411 | The linker has traditionally not looked for the parterning high part | |
14412 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
14413 | placed anywhere. Rather than break backwards compatibility by changing | |
14414 | this, it seems better not to force the issue, and instead keep the | |
14415 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 14416 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 14417 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
14418 | && HAVE_IN_PLACE_ADDENDS |
14419 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
14420 | return 0; | |
14421 | ||
ce70d90a MR |
14422 | /* There is no place to store an in-place offset for JALR relocations. |
14423 | Likewise an in-range offset of PC-relative relocations may overflow | |
14424 | the in-place relocatable field if recalculated against the start | |
14425 | address of the symbol's containing section. */ | |
14426 | if (HAVE_IN_PLACE_ADDENDS | |
14427 | && (fixp->fx_pcrel || fixp->fx_r_type == BFD_RELOC_MIPS_JALR)) | |
1180b5a4 RS |
14428 | return 0; |
14429 | ||
252b5132 | 14430 | #ifdef OBJ_ELF |
b314ec0e RS |
14431 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
14432 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
14433 | relocations against MIPS16 functions; in this case, the stub becomes | |
14434 | the function's canonical address. | |
14435 | ||
14436 | Floating-point stubs are stored in unique .mips16.call.* or | |
14437 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
14438 | the first relocation in section S must be against F; this is how the | |
14439 | linker determines the target function. All relocations that might | |
14440 | resolve to T must also be against F. We therefore have the following | |
14441 | restrictions, which are given in an intentionally-redundant way: | |
14442 | ||
14443 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
14444 | symbols. | |
14445 | ||
14446 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
14447 | if that stub might be used. | |
14448 | ||
14449 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
14450 | symbols. | |
14451 | ||
14452 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
14453 | that stub might be used. | |
14454 | ||
14455 | There is a further restriction: | |
14456 | ||
14457 | 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols | |
14458 | on targets with in-place addends; the relocation field cannot | |
14459 | encode the low bit. | |
14460 | ||
14461 | For simplicity, we deal with (3)-(5) by not reducing _any_ relocation | |
14462 | against a MIPS16 symbol. | |
14463 | ||
14464 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
14465 | relocation against some symbol R, no relocation against R may be | |
14466 | reduced. (Note that this deals with (2) as well as (1) because | |
14467 | relocations against global symbols will never be reduced on ELF | |
14468 | targets.) This approach is a little simpler than trying to detect | |
14469 | stub sections, and gives the "all or nothing" per-symbol consistency | |
14470 | that we have for MIPS16 symbols. */ | |
f43abd2b | 14471 | if (IS_ELF |
b314ec0e | 14472 | && fixp->fx_subsy == NULL |
30c09090 | 14473 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
b314ec0e | 14474 | || *symbol_get_tc (fixp->fx_addsy))) |
252b5132 RH |
14475 | return 0; |
14476 | #endif | |
a161fe53 | 14477 | |
252b5132 RH |
14478 | return 1; |
14479 | } | |
14480 | ||
14481 | /* Translate internal representation of relocation info to BFD target | |
14482 | format. */ | |
14483 | ||
14484 | arelent ** | |
17a2f251 | 14485 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
14486 | { |
14487 | static arelent *retval[4]; | |
14488 | arelent *reloc; | |
14489 | bfd_reloc_code_real_type code; | |
14490 | ||
4b0cff4e TS |
14491 | memset (retval, 0, sizeof(retval)); |
14492 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
14493 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
14494 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
14495 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
14496 | ||
bad36eac DJ |
14497 | if (fixp->fx_pcrel) |
14498 | { | |
9c2799c2 | 14499 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2); |
bad36eac DJ |
14500 | |
14501 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
14502 | Relocations want only the symbol offset. */ | |
14503 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 14504 | if (!IS_ELF) |
bad36eac DJ |
14505 | { |
14506 | /* A gruesome hack which is a result of the gruesome gas | |
14507 | reloc handling. What's worse, for COFF (as opposed to | |
14508 | ECOFF), we might need yet another copy of reloc->address. | |
14509 | See bfd_install_relocation. */ | |
14510 | reloc->addend += reloc->address; | |
14511 | } | |
14512 | } | |
14513 | else | |
14514 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 14515 | |
438c16b8 TS |
14516 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
14517 | entry to be used in the relocation's section offset. */ | |
14518 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
14519 | { |
14520 | reloc->address = reloc->addend; | |
14521 | reloc->addend = 0; | |
14522 | } | |
14523 | ||
252b5132 | 14524 | code = fixp->fx_r_type; |
252b5132 | 14525 | |
bad36eac | 14526 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
14527 | if (reloc->howto == NULL) |
14528 | { | |
14529 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14530 | _("Can not represent %s relocation in this object file format"), | |
14531 | bfd_get_reloc_code_name (code)); | |
14532 | retval[0] = NULL; | |
14533 | } | |
14534 | ||
14535 | return retval; | |
14536 | } | |
14537 | ||
14538 | /* Relax a machine dependent frag. This returns the amount by which | |
14539 | the current size of the frag should change. */ | |
14540 | ||
14541 | int | |
17a2f251 | 14542 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 14543 | { |
4a6a3df4 AO |
14544 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14545 | { | |
14546 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
14547 | |
14548 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
14549 | |
14550 | return fragp->fr_var - old_var; | |
14551 | } | |
14552 | ||
252b5132 RH |
14553 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
14554 | return 0; | |
14555 | ||
c4e7957c | 14556 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
14557 | { |
14558 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14559 | return 0; | |
14560 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
14561 | return 2; | |
14562 | } | |
14563 | else | |
14564 | { | |
14565 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14566 | return 0; | |
14567 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
14568 | return -2; | |
14569 | } | |
14570 | ||
14571 | return 0; | |
14572 | } | |
14573 | ||
14574 | /* Convert a machine dependent frag. */ | |
14575 | ||
14576 | void | |
17a2f251 | 14577 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 14578 | { |
4a6a3df4 AO |
14579 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14580 | { | |
14581 | bfd_byte *buf; | |
14582 | unsigned long insn; | |
14583 | expressionS exp; | |
14584 | fixS *fixp; | |
b34976b6 | 14585 | |
4a6a3df4 AO |
14586 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
14587 | ||
14588 | if (target_big_endian) | |
14589 | insn = bfd_getb32 (buf); | |
14590 | else | |
14591 | insn = bfd_getl32 (buf); | |
b34976b6 | 14592 | |
4a6a3df4 AO |
14593 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
14594 | { | |
14595 | /* We generate a fixup instead of applying it right now | |
14596 | because, if there are linker relaxations, we're going to | |
14597 | need the relocations. */ | |
14598 | exp.X_op = O_symbol; | |
14599 | exp.X_add_symbol = fragp->fr_symbol; | |
14600 | exp.X_add_number = fragp->fr_offset; | |
14601 | ||
14602 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14603 | 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
14604 | fixp->fx_file = fragp->fr_file; |
14605 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14606 | |
2132e3a3 | 14607 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14608 | buf += 4; |
14609 | } | |
14610 | else | |
14611 | { | |
14612 | int i; | |
14613 | ||
14614 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 14615 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
14616 | |
14617 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
14618 | goto uncond; | |
14619 | ||
14620 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14621 | { | |
14622 | /* Reverse the branch. */ | |
14623 | switch ((insn >> 28) & 0xf) | |
14624 | { | |
14625 | case 4: | |
14626 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
14627 | have the condition reversed by tweaking a single | |
14628 | bit, and their opcodes all have 0x4???????. */ | |
9c2799c2 | 14629 | gas_assert ((insn & 0xf1000000) == 0x41000000); |
4a6a3df4 AO |
14630 | insn ^= 0x00010000; |
14631 | break; | |
14632 | ||
14633 | case 0: | |
14634 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 14635 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 14636 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
14637 | insn ^= 0x00010000; |
14638 | break; | |
b34976b6 | 14639 | |
4a6a3df4 AO |
14640 | case 1: |
14641 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 14642 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
14643 | insn ^= 0x04000000; |
14644 | break; | |
14645 | ||
14646 | default: | |
14647 | abort (); | |
14648 | } | |
14649 | } | |
14650 | ||
14651 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
14652 | { | |
14653 | /* Clear the and-link bit. */ | |
9c2799c2 | 14654 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 14655 | |
54f4ddb3 TS |
14656 | /* bltzal 0x04100000 bgezal 0x04110000 |
14657 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
14658 | insn &= ~0x00100000; |
14659 | } | |
14660 | ||
14661 | /* Branch over the branch (if the branch was likely) or the | |
14662 | full jump (not likely case). Compute the offset from the | |
14663 | current instruction to branch to. */ | |
14664 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14665 | i = 16; | |
14666 | else | |
14667 | { | |
14668 | /* How many bytes in instructions we've already emitted? */ | |
14669 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
14670 | /* How many bytes in instructions from here to the end? */ | |
14671 | i = fragp->fr_var - i; | |
14672 | } | |
14673 | /* Convert to instruction count. */ | |
14674 | i >>= 2; | |
14675 | /* Branch counts from the next instruction. */ | |
b34976b6 | 14676 | i--; |
4a6a3df4 AO |
14677 | insn |= i; |
14678 | /* Branch over the jump. */ | |
2132e3a3 | 14679 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14680 | buf += 4; |
14681 | ||
54f4ddb3 | 14682 | /* nop */ |
2132e3a3 | 14683 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14684 | buf += 4; |
14685 | ||
14686 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14687 | { | |
14688 | /* beql $0, $0, 2f */ | |
14689 | insn = 0x50000000; | |
14690 | /* Compute the PC offset from the current instruction to | |
14691 | the end of the variable frag. */ | |
14692 | /* How many bytes in instructions we've already emitted? */ | |
14693 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
14694 | /* How many bytes in instructions from here to the end? */ | |
14695 | i = fragp->fr_var - i; | |
14696 | /* Convert to instruction count. */ | |
14697 | i >>= 2; | |
14698 | /* Don't decrement i, because we want to branch over the | |
14699 | delay slot. */ | |
14700 | ||
14701 | insn |= i; | |
2132e3a3 | 14702 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14703 | buf += 4; |
14704 | ||
2132e3a3 | 14705 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14706 | buf += 4; |
14707 | } | |
14708 | ||
14709 | uncond: | |
14710 | if (mips_pic == NO_PIC) | |
14711 | { | |
14712 | /* j or jal. */ | |
14713 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
14714 | ? 0x0c000000 : 0x08000000); | |
14715 | exp.X_op = O_symbol; | |
14716 | exp.X_add_symbol = fragp->fr_symbol; | |
14717 | exp.X_add_number = fragp->fr_offset; | |
14718 | ||
14719 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14720 | 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); |
4a6a3df4 AO |
14721 | fixp->fx_file = fragp->fr_file; |
14722 | fixp->fx_line = fragp->fr_line; | |
14723 | ||
2132e3a3 | 14724 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14725 | buf += 4; |
14726 | } | |
14727 | else | |
14728 | { | |
66b3e8da MR |
14729 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
14730 | ||
4a6a3df4 | 14731 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
14732 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
14733 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
14734 | exp.X_op = O_symbol; |
14735 | exp.X_add_symbol = fragp->fr_symbol; | |
14736 | exp.X_add_number = fragp->fr_offset; | |
14737 | ||
14738 | if (fragp->fr_offset) | |
14739 | { | |
14740 | exp.X_add_symbol = make_expr_symbol (&exp); | |
14741 | exp.X_add_number = 0; | |
14742 | } | |
14743 | ||
14744 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14745 | 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16); |
4a6a3df4 AO |
14746 | fixp->fx_file = fragp->fr_file; |
14747 | fixp->fx_line = fragp->fr_line; | |
14748 | ||
2132e3a3 | 14749 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 14750 | buf += 4; |
b34976b6 | 14751 | |
4a6a3df4 AO |
14752 | if (mips_opts.isa == ISA_MIPS1) |
14753 | { | |
14754 | /* nop */ | |
2132e3a3 | 14755 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14756 | buf += 4; |
14757 | } | |
14758 | ||
14759 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
14760 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
14761 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 AO |
14762 | |
14763 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14764 | 4, &exp, FALSE, BFD_RELOC_LO16); |
4a6a3df4 AO |
14765 | fixp->fx_file = fragp->fr_file; |
14766 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14767 | |
2132e3a3 | 14768 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14769 | buf += 4; |
14770 | ||
14771 | /* j(al)r $at. */ | |
14772 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 14773 | insn = 0x0000f809; |
4a6a3df4 | 14774 | else |
66b3e8da MR |
14775 | insn = 0x00000008; |
14776 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 14777 | |
2132e3a3 | 14778 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14779 | buf += 4; |
14780 | } | |
14781 | } | |
14782 | ||
9c2799c2 | 14783 | gas_assert (buf == (bfd_byte *)fragp->fr_literal |
4a6a3df4 AO |
14784 | + fragp->fr_fix + fragp->fr_var); |
14785 | ||
14786 | fragp->fr_fix += fragp->fr_var; | |
14787 | ||
14788 | return; | |
14789 | } | |
14790 | ||
252b5132 RH |
14791 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
14792 | { | |
14793 | int type; | |
3994f87e | 14794 | const struct mips16_immed_operand *op; |
b34976b6 | 14795 | bfd_boolean small, ext; |
252b5132 RH |
14796 | offsetT val; |
14797 | bfd_byte *buf; | |
14798 | unsigned long insn; | |
b34976b6 | 14799 | bfd_boolean use_extend; |
252b5132 RH |
14800 | unsigned short extend; |
14801 | ||
14802 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
14803 | op = mips16_immed_operands; | |
14804 | while (op->type != type) | |
14805 | ++op; | |
14806 | ||
14807 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14808 | { | |
b34976b6 AM |
14809 | small = FALSE; |
14810 | ext = TRUE; | |
252b5132 RH |
14811 | } |
14812 | else | |
14813 | { | |
b34976b6 AM |
14814 | small = TRUE; |
14815 | ext = FALSE; | |
252b5132 RH |
14816 | } |
14817 | ||
5f5f22c0 | 14818 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
14819 | if (op->pcrel) |
14820 | { | |
14821 | addressT addr; | |
14822 | ||
14823 | addr = fragp->fr_address + fragp->fr_fix; | |
14824 | ||
14825 | /* The rules for the base address of a PC relative reloc are | |
14826 | complicated; see mips16_extended_frag. */ | |
14827 | if (type == 'p' || type == 'q') | |
14828 | { | |
14829 | addr += 2; | |
14830 | if (ext) | |
14831 | addr += 2; | |
14832 | /* Ignore the low bit in the target, since it will be | |
14833 | set for a text label. */ | |
14834 | if ((val & 1) != 0) | |
14835 | --val; | |
14836 | } | |
14837 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
14838 | addr -= 4; | |
14839 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
14840 | addr -= 2; | |
14841 | ||
14842 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
14843 | val -= addr; | |
14844 | ||
14845 | /* Make sure the section winds up with the alignment we have | |
14846 | assumed. */ | |
14847 | if (op->shift > 0) | |
14848 | record_alignment (asec, op->shift); | |
14849 | } | |
14850 | ||
14851 | if (ext | |
14852 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
14853 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
14854 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
14855 | _("extended instruction in delay slot")); | |
14856 | ||
14857 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
14858 | ||
14859 | if (target_big_endian) | |
14860 | insn = bfd_getb16 (buf); | |
14861 | else | |
14862 | insn = bfd_getl16 (buf); | |
14863 | ||
14864 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
14865 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
14866 | small, ext, &insn, &use_extend, &extend); | |
14867 | ||
14868 | if (use_extend) | |
14869 | { | |
2132e3a3 | 14870 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
14871 | fragp->fr_fix += 2; |
14872 | buf += 2; | |
14873 | } | |
14874 | ||
2132e3a3 | 14875 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
14876 | fragp->fr_fix += 2; |
14877 | buf += 2; | |
14878 | } | |
14879 | else | |
14880 | { | |
4d7206a2 RS |
14881 | int first, second; |
14882 | fixS *fixp; | |
252b5132 | 14883 | |
4d7206a2 RS |
14884 | first = RELAX_FIRST (fragp->fr_subtype); |
14885 | second = RELAX_SECOND (fragp->fr_subtype); | |
14886 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 14887 | |
584892a6 RS |
14888 | /* Possibly emit a warning if we've chosen the longer option. */ |
14889 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
14890 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
14891 | { | |
14892 | const char *msg = macro_warning (fragp->fr_subtype); | |
14893 | if (msg != 0) | |
520725ea | 14894 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
584892a6 RS |
14895 | } |
14896 | ||
4d7206a2 RS |
14897 | /* Go through all the fixups for the first sequence. Disable them |
14898 | (by marking them as done) if we're going to use the second | |
14899 | sequence instead. */ | |
14900 | while (fixp | |
14901 | && fixp->fx_frag == fragp | |
14902 | && fixp->fx_where < fragp->fr_fix - second) | |
14903 | { | |
14904 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14905 | fixp->fx_done = 1; | |
14906 | fixp = fixp->fx_next; | |
14907 | } | |
252b5132 | 14908 | |
4d7206a2 RS |
14909 | /* Go through the fixups for the second sequence. Disable them if |
14910 | we're going to use the first sequence, otherwise adjust their | |
14911 | addresses to account for the relaxation. */ | |
14912 | while (fixp && fixp->fx_frag == fragp) | |
14913 | { | |
14914 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14915 | fixp->fx_where -= first; | |
14916 | else | |
14917 | fixp->fx_done = 1; | |
14918 | fixp = fixp->fx_next; | |
14919 | } | |
14920 | ||
14921 | /* Now modify the frag contents. */ | |
14922 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14923 | { | |
14924 | char *start; | |
14925 | ||
14926 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
14927 | memmove (start, start + first, second); | |
14928 | fragp->fr_fix -= first; | |
14929 | } | |
14930 | else | |
14931 | fragp->fr_fix -= second; | |
252b5132 RH |
14932 | } |
14933 | } | |
14934 | ||
14935 | #ifdef OBJ_ELF | |
14936 | ||
14937 | /* This function is called after the relocs have been generated. | |
14938 | We've been storing mips16 text labels as odd. Here we convert them | |
14939 | back to even for the convenience of the debugger. */ | |
14940 | ||
14941 | void | |
17a2f251 | 14942 | mips_frob_file_after_relocs (void) |
252b5132 RH |
14943 | { |
14944 | asymbol **syms; | |
14945 | unsigned int count, i; | |
14946 | ||
f43abd2b | 14947 | if (!IS_ELF) |
252b5132 RH |
14948 | return; |
14949 | ||
14950 | syms = bfd_get_outsymbols (stdoutput); | |
14951 | count = bfd_get_symcount (stdoutput); | |
14952 | for (i = 0; i < count; i++, syms++) | |
14953 | { | |
30c09090 | 14954 | if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other) |
252b5132 RH |
14955 | && ((*syms)->value & 1) != 0) |
14956 | { | |
14957 | (*syms)->value &= ~1; | |
14958 | /* If the symbol has an odd size, it was probably computed | |
14959 | incorrectly, so adjust that as well. */ | |
14960 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
14961 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
14962 | } | |
14963 | } | |
14964 | } | |
14965 | ||
14966 | #endif | |
14967 | ||
a1facbec MR |
14968 | /* This function is called whenever a label is defined, including fake |
14969 | labels instantiated off the dot special symbol. It is used when | |
14970 | handling branch delays; if a branch has a label, we assume we cannot | |
14971 | move it. This also bumps the value of the symbol by 1 in compressed | |
14972 | code. */ | |
252b5132 RH |
14973 | |
14974 | void | |
a1facbec | 14975 | mips_record_label (symbolS *sym) |
252b5132 | 14976 | { |
a8dbcb85 | 14977 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
14978 | struct insn_label_list *l; |
14979 | ||
14980 | if (free_insn_labels == NULL) | |
14981 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
14982 | else | |
14983 | { | |
14984 | l = free_insn_labels; | |
14985 | free_insn_labels = l->next; | |
14986 | } | |
14987 | ||
14988 | l->label = sym; | |
a8dbcb85 TS |
14989 | l->next = si->label_list; |
14990 | si->label_list = l; | |
a1facbec | 14991 | } |
07a53e5c | 14992 | |
a1facbec MR |
14993 | /* This function is called as tc_frob_label() whenever a label is defined |
14994 | and adds a DWARF-2 record we only want for true labels. */ | |
14995 | ||
14996 | void | |
14997 | mips_define_label (symbolS *sym) | |
14998 | { | |
14999 | mips_record_label (sym); | |
07a53e5c RH |
15000 | #ifdef OBJ_ELF |
15001 | dwarf2_emit_label (sym); | |
15002 | #endif | |
252b5132 RH |
15003 | } |
15004 | \f | |
15005 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
15006 | ||
15007 | /* Some special processing for a MIPS ELF file. */ | |
15008 | ||
15009 | void | |
17a2f251 | 15010 | mips_elf_final_processing (void) |
252b5132 RH |
15011 | { |
15012 | /* Write out the register information. */ | |
316f5878 | 15013 | if (mips_abi != N64_ABI) |
252b5132 RH |
15014 | { |
15015 | Elf32_RegInfo s; | |
15016 | ||
15017 | s.ri_gprmask = mips_gprmask; | |
15018 | s.ri_cprmask[0] = mips_cprmask[0]; | |
15019 | s.ri_cprmask[1] = mips_cprmask[1]; | |
15020 | s.ri_cprmask[2] = mips_cprmask[2]; | |
15021 | s.ri_cprmask[3] = mips_cprmask[3]; | |
15022 | /* The gp_value field is set by the MIPS ELF backend. */ | |
15023 | ||
15024 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
15025 | ((Elf32_External_RegInfo *) | |
15026 | mips_regmask_frag)); | |
15027 | } | |
15028 | else | |
15029 | { | |
15030 | Elf64_Internal_RegInfo s; | |
15031 | ||
15032 | s.ri_gprmask = mips_gprmask; | |
15033 | s.ri_pad = 0; | |
15034 | s.ri_cprmask[0] = mips_cprmask[0]; | |
15035 | s.ri_cprmask[1] = mips_cprmask[1]; | |
15036 | s.ri_cprmask[2] = mips_cprmask[2]; | |
15037 | s.ri_cprmask[3] = mips_cprmask[3]; | |
15038 | /* The gp_value field is set by the MIPS ELF backend. */ | |
15039 | ||
15040 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
15041 | ((Elf64_External_RegInfo *) | |
15042 | mips_regmask_frag)); | |
15043 | } | |
15044 | ||
15045 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
15046 | sort of BFD interface for this. */ | |
15047 | if (mips_any_noreorder) | |
15048 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
15049 | if (mips_pic != NO_PIC) | |
143d77c5 | 15050 | { |
252b5132 | 15051 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
15052 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
15053 | } | |
15054 | if (mips_abicalls) | |
15055 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 15056 | |
98d3f06f | 15057 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
15058 | /* We may need to define a new flag for DSP ASE, and set this flag when |
15059 | file_ase_dsp is true. */ | |
8b082fb1 | 15060 | /* Same for DSP R2. */ |
ef2e4d86 CF |
15061 | /* We may need to define a new flag for MT ASE, and set this flag when |
15062 | file_ase_mt is true. */ | |
a4672219 TS |
15063 | if (file_ase_mips16) |
15064 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
15065 | #if 0 /* XXX FIXME */ |
15066 | if (file_ase_mips3d) | |
15067 | elf_elfheader (stdoutput)->e_flags |= ???; | |
15068 | #endif | |
deec1734 CD |
15069 | if (file_ase_mdmx) |
15070 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 15071 | |
bdaaa2e1 | 15072 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 15073 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 15074 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 15075 | else if (mips_abi == O64_ABI) |
252b5132 | 15076 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 15077 | else if (mips_abi == EABI_ABI) |
252b5132 | 15078 | { |
316f5878 | 15079 | if (!file_mips_gp32) |
252b5132 RH |
15080 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
15081 | else | |
15082 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
15083 | } | |
316f5878 | 15084 | else if (mips_abi == N32_ABI) |
be00bddd TS |
15085 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
15086 | ||
c9914766 | 15087 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
15088 | |
15089 | if (mips_32bitmode) | |
15090 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
15091 | |
15092 | #if 0 /* XXX FIXME */ | |
15093 | /* 32 bit code with 64 bit FP registers. */ | |
15094 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15095 | elf_elfheader (stdoutput)->e_flags |= ???; | |
15096 | #endif | |
252b5132 RH |
15097 | } |
15098 | ||
15099 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
15100 | \f | |
beae10d5 | 15101 | typedef struct proc { |
9b2f1d35 EC |
15102 | symbolS *func_sym; |
15103 | symbolS *func_end_sym; | |
beae10d5 KH |
15104 | unsigned long reg_mask; |
15105 | unsigned long reg_offset; | |
15106 | unsigned long fpreg_mask; | |
15107 | unsigned long fpreg_offset; | |
15108 | unsigned long frame_offset; | |
15109 | unsigned long frame_reg; | |
15110 | unsigned long pc_reg; | |
15111 | } procS; | |
252b5132 RH |
15112 | |
15113 | static procS cur_proc; | |
15114 | static procS *cur_proc_ptr; | |
15115 | static int numprocs; | |
15116 | ||
742a56fe RS |
15117 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal |
15118 | nop as "0". */ | |
15119 | ||
15120 | char | |
15121 | mips_nop_opcode (void) | |
15122 | { | |
15123 | return seg_info (now_seg)->tc_segment_info_data.mips16; | |
15124 | } | |
15125 | ||
15126 | /* Fill in an rs_align_code fragment. This only needs to do something | |
15127 | for MIPS16 code, where 0 is not a nop. */ | |
a19d8eb0 | 15128 | |
0a9ef439 | 15129 | void |
17a2f251 | 15130 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 15131 | { |
742a56fe | 15132 | char *p; |
c67a084a NC |
15133 | int bytes, size, excess; |
15134 | valueT opcode; | |
742a56fe | 15135 | |
0a9ef439 RH |
15136 | if (fragp->fr_type != rs_align_code) |
15137 | return; | |
15138 | ||
742a56fe RS |
15139 | p = fragp->fr_literal + fragp->fr_fix; |
15140 | if (*p) | |
a19d8eb0 | 15141 | { |
c67a084a NC |
15142 | opcode = mips16_nop_insn.insn_opcode; |
15143 | size = 2; | |
15144 | } | |
15145 | else | |
15146 | { | |
15147 | opcode = nop_insn.insn_opcode; | |
15148 | size = 4; | |
15149 | } | |
a19d8eb0 | 15150 | |
c67a084a NC |
15151 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
15152 | excess = bytes % size; | |
15153 | if (excess != 0) | |
15154 | { | |
15155 | /* If we're not inserting a whole number of instructions, | |
15156 | pad the end of the fixed part of the frag with zeros. */ | |
15157 | memset (p, 0, excess); | |
15158 | p += excess; | |
15159 | fragp->fr_fix += excess; | |
a19d8eb0 | 15160 | } |
c67a084a NC |
15161 | |
15162 | md_number_to_chars (p, opcode, size); | |
15163 | fragp->fr_var = size; | |
a19d8eb0 CP |
15164 | } |
15165 | ||
252b5132 | 15166 | static void |
17a2f251 | 15167 | md_obj_begin (void) |
252b5132 RH |
15168 | { |
15169 | } | |
15170 | ||
15171 | static void | |
17a2f251 | 15172 | md_obj_end (void) |
252b5132 | 15173 | { |
54f4ddb3 | 15174 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 15175 | if (cur_proc_ptr) |
9a41af64 | 15176 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
15177 | } |
15178 | ||
15179 | static long | |
17a2f251 | 15180 | get_number (void) |
252b5132 RH |
15181 | { |
15182 | int negative = 0; | |
15183 | long val = 0; | |
15184 | ||
15185 | if (*input_line_pointer == '-') | |
15186 | { | |
15187 | ++input_line_pointer; | |
15188 | negative = 1; | |
15189 | } | |
3882b010 | 15190 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 15191 | as_bad (_("expected simple number")); |
252b5132 RH |
15192 | if (input_line_pointer[0] == '0') |
15193 | { | |
15194 | if (input_line_pointer[1] == 'x') | |
15195 | { | |
15196 | input_line_pointer += 2; | |
3882b010 | 15197 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
15198 | { |
15199 | val <<= 4; | |
15200 | val |= hex_value (*input_line_pointer++); | |
15201 | } | |
15202 | return negative ? -val : val; | |
15203 | } | |
15204 | else | |
15205 | { | |
15206 | ++input_line_pointer; | |
3882b010 | 15207 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
15208 | { |
15209 | val <<= 3; | |
15210 | val |= *input_line_pointer++ - '0'; | |
15211 | } | |
15212 | return negative ? -val : val; | |
15213 | } | |
15214 | } | |
3882b010 | 15215 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
15216 | { |
15217 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
15218 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 15219 | as_warn (_("invalid number")); |
252b5132 RH |
15220 | return -1; |
15221 | } | |
3882b010 | 15222 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
15223 | { |
15224 | val *= 10; | |
15225 | val += *input_line_pointer++ - '0'; | |
15226 | } | |
15227 | return negative ? -val : val; | |
15228 | } | |
15229 | ||
15230 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
15231 | is an initial number which is the ECOFF file index. In the non-ECOFF |
15232 | case .file implies DWARF-2. */ | |
15233 | ||
15234 | static void | |
17a2f251 | 15235 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 15236 | { |
ecb4347a DJ |
15237 | static int first_file_directive = 0; |
15238 | ||
c5dd6aab DJ |
15239 | if (ECOFF_DEBUGGING) |
15240 | { | |
15241 | get_number (); | |
15242 | s_app_file (0); | |
15243 | } | |
15244 | else | |
ecb4347a DJ |
15245 | { |
15246 | char *filename; | |
15247 | ||
15248 | filename = dwarf2_directive_file (0); | |
15249 | ||
15250 | /* Versions of GCC up to 3.1 start files with a ".file" | |
15251 | directive even for stabs output. Make sure that this | |
15252 | ".file" is handled. Note that you need a version of GCC | |
15253 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
15254 | if (filename != NULL && ! first_file_directive) | |
15255 | { | |
15256 | (void) new_logical_line (filename, -1); | |
c04f5787 | 15257 | s_app_file_string (filename, 0); |
ecb4347a DJ |
15258 | } |
15259 | first_file_directive = 1; | |
15260 | } | |
c5dd6aab DJ |
15261 | } |
15262 | ||
15263 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
15264 | |
15265 | static void | |
17a2f251 | 15266 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 15267 | { |
c5dd6aab DJ |
15268 | if (!ECOFF_DEBUGGING) |
15269 | dwarf2_directive_loc (0); | |
252b5132 RH |
15270 | } |
15271 | ||
252b5132 RH |
15272 | /* The .end directive. */ |
15273 | ||
15274 | static void | |
17a2f251 | 15275 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15276 | { |
15277 | symbolS *p; | |
252b5132 | 15278 | |
7a621144 DJ |
15279 | /* Following functions need their own .frame and .cprestore directives. */ |
15280 | mips_frame_reg_valid = 0; | |
15281 | mips_cprestore_valid = 0; | |
15282 | ||
252b5132 RH |
15283 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
15284 | { | |
15285 | p = get_symbol (); | |
15286 | demand_empty_rest_of_line (); | |
15287 | } | |
15288 | else | |
15289 | p = NULL; | |
15290 | ||
14949570 | 15291 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
15292 | as_warn (_(".end not in text section")); |
15293 | ||
15294 | if (!cur_proc_ptr) | |
15295 | { | |
15296 | as_warn (_(".end directive without a preceding .ent directive.")); | |
15297 | demand_empty_rest_of_line (); | |
15298 | return; | |
15299 | } | |
15300 | ||
15301 | if (p != NULL) | |
15302 | { | |
9c2799c2 | 15303 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 15304 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 15305 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
15306 | |
15307 | if (debug_type == DEBUG_STABS) | |
15308 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
15309 | S_GET_NAME (p)); | |
252b5132 RH |
15310 | } |
15311 | else | |
15312 | as_warn (_(".end directive missing or unknown symbol")); | |
15313 | ||
2132e3a3 | 15314 | #ifdef OBJ_ELF |
9b2f1d35 EC |
15315 | /* Create an expression to calculate the size of the function. */ |
15316 | if (p && cur_proc_ptr) | |
15317 | { | |
15318 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
15319 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
15320 | ||
15321 | obj->size = exp; | |
15322 | exp->X_op = O_subtract; | |
15323 | exp->X_add_symbol = symbol_temp_new_now (); | |
15324 | exp->X_op_symbol = p; | |
15325 | exp->X_add_number = 0; | |
15326 | ||
15327 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
15328 | } | |
15329 | ||
ecb4347a | 15330 | /* Generate a .pdr section. */ |
f43abd2b | 15331 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
15332 | { |
15333 | segT saved_seg = now_seg; | |
15334 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
15335 | expressionS exp; |
15336 | char *fragp; | |
252b5132 | 15337 | |
252b5132 | 15338 | #ifdef md_flush_pending_output |
ecb4347a | 15339 | md_flush_pending_output (); |
252b5132 RH |
15340 | #endif |
15341 | ||
9c2799c2 | 15342 | gas_assert (pdr_seg); |
ecb4347a | 15343 | subseg_set (pdr_seg, 0); |
252b5132 | 15344 | |
ecb4347a DJ |
15345 | /* Write the symbol. */ |
15346 | exp.X_op = O_symbol; | |
15347 | exp.X_add_symbol = p; | |
15348 | exp.X_add_number = 0; | |
15349 | emit_expr (&exp, 4); | |
252b5132 | 15350 | |
ecb4347a | 15351 | fragp = frag_more (7 * 4); |
252b5132 | 15352 | |
17a2f251 TS |
15353 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
15354 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
15355 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
15356 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
15357 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
15358 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
15359 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 15360 | |
ecb4347a DJ |
15361 | subseg_set (saved_seg, saved_subseg); |
15362 | } | |
15363 | #endif /* OBJ_ELF */ | |
252b5132 RH |
15364 | |
15365 | cur_proc_ptr = NULL; | |
15366 | } | |
15367 | ||
15368 | /* The .aent and .ent directives. */ | |
15369 | ||
15370 | static void | |
17a2f251 | 15371 | s_mips_ent (int aent) |
252b5132 | 15372 | { |
252b5132 | 15373 | symbolS *symbolP; |
252b5132 RH |
15374 | |
15375 | symbolP = get_symbol (); | |
15376 | if (*input_line_pointer == ',') | |
f9419b05 | 15377 | ++input_line_pointer; |
252b5132 | 15378 | SKIP_WHITESPACE (); |
3882b010 | 15379 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 15380 | || *input_line_pointer == '-') |
874e8986 | 15381 | get_number (); |
252b5132 | 15382 | |
14949570 | 15383 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
15384 | as_warn (_(".ent or .aent not in text section.")); |
15385 | ||
15386 | if (!aent && cur_proc_ptr) | |
9a41af64 | 15387 | as_warn (_("missing .end")); |
252b5132 RH |
15388 | |
15389 | if (!aent) | |
15390 | { | |
7a621144 DJ |
15391 | /* This function needs its own .frame and .cprestore directives. */ |
15392 | mips_frame_reg_valid = 0; | |
15393 | mips_cprestore_valid = 0; | |
15394 | ||
252b5132 RH |
15395 | cur_proc_ptr = &cur_proc; |
15396 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
15397 | ||
9b2f1d35 | 15398 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 15399 | |
f9419b05 | 15400 | ++numprocs; |
ecb4347a DJ |
15401 | |
15402 | if (debug_type == DEBUG_STABS) | |
15403 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
15404 | S_GET_NAME (symbolP)); | |
252b5132 RH |
15405 | } |
15406 | ||
7c0fc524 MR |
15407 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
15408 | ||
252b5132 RH |
15409 | demand_empty_rest_of_line (); |
15410 | } | |
15411 | ||
15412 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 15413 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 15414 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 15415 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
15416 | symbol table (in the mdebug section). */ |
15417 | ||
15418 | static void | |
17a2f251 | 15419 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 15420 | { |
ecb4347a | 15421 | #ifdef OBJ_ELF |
f43abd2b | 15422 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
15423 | { |
15424 | long val; | |
252b5132 | 15425 | |
ecb4347a DJ |
15426 | if (cur_proc_ptr == (procS *) NULL) |
15427 | { | |
15428 | as_warn (_(".frame outside of .ent")); | |
15429 | demand_empty_rest_of_line (); | |
15430 | return; | |
15431 | } | |
252b5132 | 15432 | |
ecb4347a DJ |
15433 | cur_proc_ptr->frame_reg = tc_get_register (1); |
15434 | ||
15435 | SKIP_WHITESPACE (); | |
15436 | if (*input_line_pointer++ != ',' | |
15437 | || get_absolute_expression_and_terminator (&val) != ',') | |
15438 | { | |
15439 | as_warn (_("Bad .frame directive")); | |
15440 | --input_line_pointer; | |
15441 | demand_empty_rest_of_line (); | |
15442 | return; | |
15443 | } | |
252b5132 | 15444 | |
ecb4347a DJ |
15445 | cur_proc_ptr->frame_offset = val; |
15446 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 15447 | |
252b5132 | 15448 | demand_empty_rest_of_line (); |
252b5132 | 15449 | } |
ecb4347a DJ |
15450 | else |
15451 | #endif /* OBJ_ELF */ | |
15452 | s_ignore (ignore); | |
252b5132 RH |
15453 | } |
15454 | ||
bdaaa2e1 KH |
15455 | /* The .fmask and .mask directives. If the mdebug section is present |
15456 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 15457 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 15458 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
15459 | make reference to the ecoff symbol table (in the mdebug section). */ |
15460 | ||
15461 | static void | |
17a2f251 | 15462 | s_mips_mask (int reg_type) |
252b5132 | 15463 | { |
ecb4347a | 15464 | #ifdef OBJ_ELF |
f43abd2b | 15465 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 15466 | { |
ecb4347a | 15467 | long mask, off; |
252b5132 | 15468 | |
ecb4347a DJ |
15469 | if (cur_proc_ptr == (procS *) NULL) |
15470 | { | |
15471 | as_warn (_(".mask/.fmask outside of .ent")); | |
15472 | demand_empty_rest_of_line (); | |
15473 | return; | |
15474 | } | |
252b5132 | 15475 | |
ecb4347a DJ |
15476 | if (get_absolute_expression_and_terminator (&mask) != ',') |
15477 | { | |
15478 | as_warn (_("Bad .mask/.fmask directive")); | |
15479 | --input_line_pointer; | |
15480 | demand_empty_rest_of_line (); | |
15481 | return; | |
15482 | } | |
252b5132 | 15483 | |
ecb4347a DJ |
15484 | off = get_absolute_expression (); |
15485 | ||
15486 | if (reg_type == 'F') | |
15487 | { | |
15488 | cur_proc_ptr->fpreg_mask = mask; | |
15489 | cur_proc_ptr->fpreg_offset = off; | |
15490 | } | |
15491 | else | |
15492 | { | |
15493 | cur_proc_ptr->reg_mask = mask; | |
15494 | cur_proc_ptr->reg_offset = off; | |
15495 | } | |
15496 | ||
15497 | demand_empty_rest_of_line (); | |
252b5132 RH |
15498 | } |
15499 | else | |
ecb4347a DJ |
15500 | #endif /* OBJ_ELF */ |
15501 | s_ignore (reg_type); | |
252b5132 RH |
15502 | } |
15503 | ||
316f5878 RS |
15504 | /* A table describing all the processors gas knows about. Names are |
15505 | matched in the order listed. | |
e7af610e | 15506 | |
316f5878 RS |
15507 | To ease comparison, please keep this table in the same order as |
15508 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
15509 | static const struct mips_cpu_info mips_cpu_info_table[] = |
15510 | { | |
316f5878 | 15511 | /* Entries for generic ISAs */ |
ad3fea08 TS |
15512 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
15513 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
15514 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
15515 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
15516 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
15517 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
15518 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15519 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
15520 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
15521 | |
15522 | /* MIPS I */ | |
ad3fea08 TS |
15523 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
15524 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
15525 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
15526 | |
15527 | /* MIPS II */ | |
ad3fea08 | 15528 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
15529 | |
15530 | /* MIPS III */ | |
ad3fea08 TS |
15531 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
15532 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
15533 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
15534 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
15535 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
15536 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
15537 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
15538 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
15539 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
15540 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
15541 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
15542 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
b15591bb AN |
15543 | /* ST Microelectronics Loongson 2E and 2F cores */ |
15544 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
15545 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
15546 | |
15547 | /* MIPS IV */ | |
ad3fea08 TS |
15548 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
15549 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
15550 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
3aa3176b TS |
15551 | { "r14000", 0, ISA_MIPS4, CPU_R14000 }, |
15552 | { "r16000", 0, ISA_MIPS4, CPU_R16000 }, | |
ad3fea08 TS |
15553 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
15554 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
15555 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
15556 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
15557 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
15558 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
15559 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
15560 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
15561 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
15562 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
15563 | |
15564 | /* MIPS 32 */ | |
ad3fea08 TS |
15565 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
15566 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
15567 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
15568 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
15569 | ||
15570 | /* MIPS 32 Release 2 */ | |
15571 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15572 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15573 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15574 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15575 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15576 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 15577 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 15578 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 15579 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
15580 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
15581 | /* Deprecated forms of the above. */ | |
15582 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 15583 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 15584 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 15585 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 15586 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 15587 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
15588 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
15589 | /* Deprecated forms of the above. */ | |
15590 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 15591 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 15592 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
15593 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15594 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15595 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15596 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
15597 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15598 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15599 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15600 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15601 | /* Deprecated forms of the above. */ | |
15602 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15603 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
15604 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15605 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15606 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
15607 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15608 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15609 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15610 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15611 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15612 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15613 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15614 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15615 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15616 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15617 | /* Deprecated forms of the above. */ | |
15618 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15619 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15620 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15621 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a SL |
15622 | /* 1004K cores are multiprocessor versions of the 34K. */ |
15623 | { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15624 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15625 | { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15626 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15627 | { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15628 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15629 | { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15630 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 15631 | |
316f5878 | 15632 | /* MIPS 64 */ |
ad3fea08 TS |
15633 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
15634 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
15635 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 15636 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 | 15637 | |
c7a23324 | 15638 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
15639 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
15640 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
15641 | /* Broadcom SB-1A CPU core */ |
15642 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
15643 | ISA_MIPS64, CPU_SB1 }, | |
d051516a NC |
15644 | |
15645 | { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A }, | |
e7af610e | 15646 | |
ed163775 MR |
15647 | /* MIPS 64 Release 2 */ |
15648 | ||
967344c6 AN |
15649 | /* Cavium Networks Octeon CPU core */ |
15650 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
15651 | ||
52b6b6b9 JM |
15652 | /* RMI Xlr */ |
15653 | { "xlr", 0, ISA_MIPS64, CPU_XLR }, | |
15654 | ||
316f5878 RS |
15655 | /* End marker */ |
15656 | { NULL, 0, 0, 0 } | |
15657 | }; | |
e7af610e | 15658 | |
84ea6cf2 | 15659 | |
316f5878 RS |
15660 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
15661 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 15662 | |
316f5878 | 15663 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 15664 | |
b34976b6 | 15665 | static bfd_boolean |
17a2f251 | 15666 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
15667 | { |
15668 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
15669 | given++, canonical++; | |
15670 | ||
15671 | return ((*given == 0 && *canonical == 0) | |
15672 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
15673 | } | |
15674 | ||
15675 | ||
15676 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
15677 | CPU name. We've traditionally allowed a lot of variation here. | |
15678 | ||
15679 | Note: this function is shared between GCC and GAS. */ | |
15680 | ||
b34976b6 | 15681 | static bfd_boolean |
17a2f251 | 15682 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
15683 | { |
15684 | /* First see if the name matches exactly, or with a final "000" | |
15685 | turned into "k". */ | |
15686 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 15687 | return TRUE; |
316f5878 RS |
15688 | |
15689 | /* If not, try comparing based on numerical designation alone. | |
15690 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
15691 | if (TOLOWER (*given) == 'r') | |
15692 | given++; | |
15693 | if (!ISDIGIT (*given)) | |
b34976b6 | 15694 | return FALSE; |
316f5878 RS |
15695 | |
15696 | /* Skip over some well-known prefixes in the canonical name, | |
15697 | hoping to find a number there too. */ | |
15698 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
15699 | canonical += 2; | |
15700 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
15701 | canonical += 2; | |
15702 | else if (TOLOWER (canonical[0]) == 'r') | |
15703 | canonical += 1; | |
15704 | ||
15705 | return mips_strict_matching_cpu_name_p (canonical, given); | |
15706 | } | |
15707 | ||
15708 | ||
15709 | /* Parse an option that takes the name of a processor as its argument. | |
15710 | OPTION is the name of the option and CPU_STRING is the argument. | |
15711 | Return the corresponding processor enumeration if the CPU_STRING is | |
15712 | recognized, otherwise report an error and return null. | |
15713 | ||
15714 | A similar function exists in GCC. */ | |
e7af610e NC |
15715 | |
15716 | static const struct mips_cpu_info * | |
17a2f251 | 15717 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 15718 | { |
316f5878 | 15719 | const struct mips_cpu_info *p; |
e7af610e | 15720 | |
316f5878 RS |
15721 | /* 'from-abi' selects the most compatible architecture for the given |
15722 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
15723 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
15724 | version. Look first at the -mgp options, if given, otherwise base | |
15725 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 15726 | |
316f5878 RS |
15727 | Treat NO_ABI like the EABIs. One reason to do this is that the |
15728 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
15729 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
15730 | 'mips64', just as we did in the days before 'from-abi'. */ | |
15731 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
15732 | { | |
15733 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15734 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
15735 | ||
15736 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15737 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
15738 | ||
15739 | if (file_mips_gp32 >= 0) | |
15740 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
15741 | ||
15742 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
15743 | ? ISA_MIPS3 | |
15744 | : ISA_MIPS1); | |
15745 | } | |
15746 | ||
15747 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
15748 | if (strcasecmp (cpu_string, "default") == 0) | |
15749 | return 0; | |
15750 | ||
15751 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
15752 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
15753 | return p; | |
15754 | ||
20203fb9 | 15755 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 15756 | return 0; |
e7af610e NC |
15757 | } |
15758 | ||
316f5878 RS |
15759 | /* Return the canonical processor information for ISA (a member of the |
15760 | ISA_MIPS* enumeration). */ | |
15761 | ||
e7af610e | 15762 | static const struct mips_cpu_info * |
17a2f251 | 15763 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
15764 | { |
15765 | int i; | |
15766 | ||
15767 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 15768 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 15769 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
15770 | return (&mips_cpu_info_table[i]); |
15771 | ||
e972090a | 15772 | return NULL; |
e7af610e | 15773 | } |
fef14a42 TS |
15774 | |
15775 | static const struct mips_cpu_info * | |
17a2f251 | 15776 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
15777 | { |
15778 | int i; | |
15779 | ||
15780 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
15781 | if (arch == mips_cpu_info_table[i].cpu) | |
15782 | return (&mips_cpu_info_table[i]); | |
15783 | ||
15784 | return NULL; | |
15785 | } | |
316f5878 RS |
15786 | \f |
15787 | static void | |
17a2f251 | 15788 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
15789 | { |
15790 | if (*first_p) | |
15791 | { | |
15792 | fprintf (stream, "%24s", ""); | |
15793 | *col_p = 24; | |
15794 | } | |
15795 | else | |
15796 | { | |
15797 | fprintf (stream, ", "); | |
15798 | *col_p += 2; | |
15799 | } | |
e7af610e | 15800 | |
316f5878 RS |
15801 | if (*col_p + strlen (string) > 72) |
15802 | { | |
15803 | fprintf (stream, "\n%24s", ""); | |
15804 | *col_p = 24; | |
15805 | } | |
15806 | ||
15807 | fprintf (stream, "%s", string); | |
15808 | *col_p += strlen (string); | |
15809 | ||
15810 | *first_p = 0; | |
15811 | } | |
15812 | ||
15813 | void | |
17a2f251 | 15814 | md_show_usage (FILE *stream) |
e7af610e | 15815 | { |
316f5878 RS |
15816 | int column, first; |
15817 | size_t i; | |
15818 | ||
15819 | fprintf (stream, _("\ | |
15820 | MIPS options:\n\ | |
316f5878 RS |
15821 | -EB generate big endian output\n\ |
15822 | -EL generate little endian output\n\ | |
15823 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
15824 | -G NUM allow referencing objects up to NUM bytes\n\ | |
15825 | implicitly with the gp register [default 8]\n")); | |
15826 | fprintf (stream, _("\ | |
15827 | -mips1 generate MIPS ISA I instructions\n\ | |
15828 | -mips2 generate MIPS ISA II instructions\n\ | |
15829 | -mips3 generate MIPS ISA III instructions\n\ | |
15830 | -mips4 generate MIPS ISA IV instructions\n\ | |
15831 | -mips5 generate MIPS ISA V instructions\n\ | |
15832 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 15833 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 15834 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 15835 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
15836 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
15837 | ||
15838 | first = 1; | |
e7af610e NC |
15839 | |
15840 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
15841 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
15842 | show (stream, "from-abi", &column, &first); | |
15843 | fputc ('\n', stream); | |
e7af610e | 15844 | |
316f5878 RS |
15845 | fprintf (stream, _("\ |
15846 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
15847 | -no-mCPU don't generate code specific to CPU.\n\ | |
15848 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
15849 | ||
15850 | first = 1; | |
15851 | ||
15852 | show (stream, "3900", &column, &first); | |
15853 | show (stream, "4010", &column, &first); | |
15854 | show (stream, "4100", &column, &first); | |
15855 | show (stream, "4650", &column, &first); | |
15856 | fputc ('\n', stream); | |
15857 | ||
15858 | fprintf (stream, _("\ | |
15859 | -mips16 generate mips16 instructions\n\ | |
15860 | -no-mips16 do not generate mips16 instructions\n")); | |
15861 | fprintf (stream, _("\ | |
e16bfa71 TS |
15862 | -msmartmips generate smartmips instructions\n\ |
15863 | -mno-smartmips do not generate smartmips instructions\n")); | |
15864 | fprintf (stream, _("\ | |
74cd071d CF |
15865 | -mdsp generate DSP instructions\n\ |
15866 | -mno-dsp do not generate DSP instructions\n")); | |
15867 | fprintf (stream, _("\ | |
8b082fb1 TS |
15868 | -mdspr2 generate DSP R2 instructions\n\ |
15869 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
15870 | fprintf (stream, _("\ | |
ef2e4d86 CF |
15871 | -mmt generate MT instructions\n\ |
15872 | -mno-mt do not generate MT instructions\n")); | |
15873 | fprintf (stream, _("\ | |
c67a084a NC |
15874 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
15875 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 15876 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 15877 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 15878 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 15879 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
15880 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
15881 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 15882 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
15883 | -O0 remove unneeded NOPs, do not swap branches\n\ |
15884 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
15885 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
15886 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
15887 | fprintf (stream, _("\ |
15888 | -mhard-float allow floating-point instructions\n\ | |
15889 | -msoft-float do not allow floating-point instructions\n\ | |
15890 | -msingle-float only allow 32-bit floating-point operations\n\ | |
15891 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
15892 | --[no-]construct-floats [dis]allow floating point values to be constructed\n" | |
15893 | )); | |
316f5878 RS |
15894 | #ifdef OBJ_ELF |
15895 | fprintf (stream, _("\ | |
15896 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 15897 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 15898 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 15899 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 15900 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 15901 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 15902 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 15903 | position dependent (non shared) code\n\ |
316f5878 RS |
15904 | -mabi=ABI create ABI conformant object file for:\n")); |
15905 | ||
15906 | first = 1; | |
15907 | ||
15908 | show (stream, "32", &column, &first); | |
15909 | show (stream, "o64", &column, &first); | |
15910 | show (stream, "n32", &column, &first); | |
15911 | show (stream, "64", &column, &first); | |
15912 | show (stream, "eabi", &column, &first); | |
15913 | ||
15914 | fputc ('\n', stream); | |
15915 | ||
15916 | fprintf (stream, _("\ | |
15917 | -32 create o32 ABI object file (default)\n\ | |
15918 | -n32 create n32 ABI object file\n\ | |
15919 | -64 create 64 ABI object file\n")); | |
15920 | #endif | |
e7af610e | 15921 | } |
14e777e0 | 15922 | |
1575952e | 15923 | #ifdef TE_IRIX |
14e777e0 | 15924 | enum dwarf2_format |
413a266c | 15925 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 15926 | { |
369943fe | 15927 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 15928 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
15929 | else |
15930 | return dwarf2_format_32bit; | |
15931 | } | |
1575952e | 15932 | #endif |
73369e65 EC |
15933 | |
15934 | int | |
15935 | mips_dwarf2_addr_size (void) | |
15936 | { | |
6b6b3450 | 15937 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 15938 | return 8; |
73369e65 EC |
15939 | else |
15940 | return 4; | |
15941 | } | |
5862107c EC |
15942 | |
15943 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
15944 | void | |
15945 | mips_cfi_frame_initial_instructions (void) | |
15946 | { | |
15947 | cfi_add_CFA_def_cfa_register (SP); | |
15948 | } | |
15949 | ||
707bfff6 TS |
15950 | int |
15951 | tc_mips_regname_to_dw2regnum (char *regname) | |
15952 | { | |
15953 | unsigned int regnum = -1; | |
15954 | unsigned int reg; | |
15955 | ||
15956 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
15957 | regnum = reg; | |
15958 | ||
15959 | return regnum; | |
15960 | } |