Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
ebd1c875 | 3 | 2003, 2004, 2005, 2006 Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
23 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
24 | 02110-1301, USA. */ | |
252b5132 RH |
25 | |
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 RH |
31 | #include "opcode/mips.h" |
32 | #include "itbl-ops.h" | |
c5dd6aab | 33 | #include "dwarf2dbg.h" |
5862107c | 34 | #include "dw2gencfi.h" |
252b5132 RH |
35 | |
36 | #ifdef DEBUG | |
37 | #define DBG(x) printf x | |
38 | #else | |
39 | #define DBG(x) | |
40 | #endif | |
41 | ||
42 | #ifdef OBJ_MAYBE_ELF | |
43 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
44 | static int mips_output_flavor (void); |
45 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
46 | #undef OBJ_PROCESS_STAB |
47 | #undef OUTPUT_FLAVOR | |
48 | #undef S_GET_ALIGN | |
49 | #undef S_GET_SIZE | |
50 | #undef S_SET_ALIGN | |
51 | #undef S_SET_SIZE | |
252b5132 RH |
52 | #undef obj_frob_file |
53 | #undef obj_frob_file_after_relocs | |
54 | #undef obj_frob_symbol | |
55 | #undef obj_pop_insert | |
56 | #undef obj_sec_sym_ok_for_reloc | |
57 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
58 | ||
59 | #include "obj-elf.h" | |
60 | /* Fix any of them that we actually care about. */ | |
61 | #undef OUTPUT_FLAVOR | |
62 | #define OUTPUT_FLAVOR mips_output_flavor() | |
63 | #endif | |
64 | ||
65 | #if defined (OBJ_ELF) | |
66 | #include "elf/mips.h" | |
67 | #endif | |
68 | ||
69 | #ifndef ECOFF_DEBUGGING | |
70 | #define NO_ECOFF_DEBUGGING | |
71 | #define ECOFF_DEBUGGING 0 | |
72 | #endif | |
73 | ||
ecb4347a DJ |
74 | int mips_flag_mdebug = -1; |
75 | ||
dcd410fe RO |
76 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
77 | linker doesn't know about and discards them, but relocations against them | |
78 | remain, leading to rld crashes. */ | |
79 | #ifdef TE_IRIX | |
80 | int mips_flag_pdr = FALSE; | |
81 | #else | |
82 | int mips_flag_pdr = TRUE; | |
83 | #endif | |
84 | ||
252b5132 RH |
85 | #include "ecoff.h" |
86 | ||
87 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
88 | static char *mips_regmask_frag; | |
89 | #endif | |
90 | ||
85b51719 | 91 | #define ZERO 0 |
252b5132 RH |
92 | #define AT 1 |
93 | #define TREG 24 | |
94 | #define PIC_CALL_REG 25 | |
95 | #define KT0 26 | |
96 | #define KT1 27 | |
97 | #define GP 28 | |
98 | #define SP 29 | |
99 | #define FP 30 | |
100 | #define RA 31 | |
101 | ||
102 | #define ILLEGAL_REG (32) | |
103 | ||
104 | /* Allow override of standard little-endian ECOFF format. */ | |
105 | ||
106 | #ifndef ECOFF_LITTLE_FORMAT | |
107 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
108 | #endif | |
109 | ||
110 | extern int target_big_endian; | |
111 | ||
252b5132 | 112 | /* The name of the readonly data section. */ |
4d0d148d | 113 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 114 | ? ".rdata" \ |
056350c6 NC |
115 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
116 | ? ".rdata" \ | |
252b5132 RH |
117 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
118 | ? ".rodata" \ | |
119 | : (abort (), "")) | |
120 | ||
47e39b9d RS |
121 | /* Information about an instruction, including its format, operands |
122 | and fixups. */ | |
123 | struct mips_cl_insn | |
124 | { | |
125 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
126 | const struct mips_opcode *insn_mo; | |
127 | ||
128 | /* True if this is a mips16 instruction and if we want the extended | |
129 | form of INSN_MO. */ | |
130 | bfd_boolean use_extend; | |
131 | ||
132 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
133 | unsigned short extend; | |
134 | ||
135 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
136 | a copy of INSN_MO->match with the operands filled in. */ | |
137 | unsigned long insn_opcode; | |
138 | ||
139 | /* The frag that contains the instruction. */ | |
140 | struct frag *frag; | |
141 | ||
142 | /* The offset into FRAG of the first instruction byte. */ | |
143 | long where; | |
144 | ||
145 | /* The relocs associated with the instruction, if any. */ | |
146 | fixS *fixp[3]; | |
147 | ||
a38419a5 RS |
148 | /* True if this entry cannot be moved from its current position. */ |
149 | unsigned int fixed_p : 1; | |
47e39b9d | 150 | |
708587a4 | 151 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
152 | unsigned int noreorder_p : 1; |
153 | ||
2fa15973 RS |
154 | /* True for mips16 instructions that jump to an absolute address. */ |
155 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
156 | }; |
157 | ||
a325df1d TS |
158 | /* The ABI to use. */ |
159 | enum mips_abi_level | |
160 | { | |
161 | NO_ABI = 0, | |
162 | O32_ABI, | |
163 | O64_ABI, | |
164 | N32_ABI, | |
165 | N64_ABI, | |
166 | EABI_ABI | |
167 | }; | |
168 | ||
169 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 170 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 171 | |
143d77c5 EC |
172 | /* Whether or not we have code that can call pic code. */ |
173 | int mips_abicalls = FALSE; | |
174 | ||
aa6975fb ILT |
175 | /* Whether or not we have code which can be put into a shared |
176 | library. */ | |
177 | static bfd_boolean mips_in_shared = TRUE; | |
178 | ||
252b5132 RH |
179 | /* This is the set of options which may be modified by the .set |
180 | pseudo-op. We use a struct so that .set push and .set pop are more | |
181 | reliable. */ | |
182 | ||
e972090a NC |
183 | struct mips_set_options |
184 | { | |
252b5132 RH |
185 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
186 | if it has not been initialized. Changed by `.set mipsN', and the | |
187 | -mipsN command line option, and the default CPU. */ | |
188 | int isa; | |
1f25f5d3 CD |
189 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
190 | if they have not been initialized. Changed by `.set <asename>', by | |
191 | command line options, and based on the default architecture. */ | |
192 | int ase_mips3d; | |
deec1734 | 193 | int ase_mdmx; |
e16bfa71 | 194 | int ase_smartmips; |
74cd071d | 195 | int ase_dsp; |
8b082fb1 | 196 | int ase_dspr2; |
ef2e4d86 | 197 | int ase_mt; |
252b5132 RH |
198 | /* Whether we are assembling for the mips16 processor. 0 if we are |
199 | not, 1 if we are, and -1 if the value has not been initialized. | |
200 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
201 | -nomips16 command line options, and the default CPU. */ | |
202 | int mips16; | |
203 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
204 | reorder' and `.set noreorder'. */ | |
205 | int noreorder; | |
206 | /* Non-zero if we should not permit the $at ($1) register to be used | |
207 | in instructions. Changed by `.set at' and `.set noat'. */ | |
208 | int noat; | |
209 | /* Non-zero if we should warn when a macro instruction expands into | |
210 | more than one machine instruction. Changed by `.set nomacro' and | |
211 | `.set macro'. */ | |
212 | int warn_about_macros; | |
213 | /* Non-zero if we should not move instructions. Changed by `.set | |
214 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
215 | int nomove; | |
216 | /* Non-zero if we should not optimize branches by moving the target | |
217 | of the branch into the delay slot. Actually, we don't perform | |
218 | this optimization anyhow. Changed by `.set bopt' and `.set | |
219 | nobopt'. */ | |
220 | int nobopt; | |
221 | /* Non-zero if we should not autoextend mips16 instructions. | |
222 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
223 | int noautoextend; | |
a325df1d TS |
224 | /* Restrict general purpose registers and floating point registers |
225 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
226 | is passed but can changed if the assembler code uses .set mipsN. */ | |
227 | int gp32; | |
228 | int fp32; | |
fef14a42 TS |
229 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
230 | command line option, and the default CPU. */ | |
231 | int arch; | |
aed1a261 RS |
232 | /* True if ".set sym32" is in effect. */ |
233 | bfd_boolean sym32; | |
252b5132 RH |
234 | }; |
235 | ||
a325df1d | 236 | /* True if -mgp32 was passed. */ |
a8e8e863 | 237 | static int file_mips_gp32 = -1; |
a325df1d TS |
238 | |
239 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 240 | static int file_mips_fp32 = -1; |
a325df1d | 241 | |
252b5132 | 242 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 243 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 244 | -1 to indicate that they have not been initialized. */ |
252b5132 | 245 | |
e972090a NC |
246 | static struct mips_set_options mips_opts = |
247 | { | |
8b082fb1 | 248 | ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE |
e7af610e | 249 | }; |
252b5132 RH |
250 | |
251 | /* These variables are filled in with the masks of registers used. | |
252 | The object format code reads them and puts them in the appropriate | |
253 | place. */ | |
254 | unsigned long mips_gprmask; | |
255 | unsigned long mips_cprmask[4]; | |
256 | ||
257 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 258 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 259 | |
a4672219 TS |
260 | /* True if -mips16 was passed or implied by arguments passed on the |
261 | command line (e.g., by -march). */ | |
262 | static int file_ase_mips16; | |
263 | ||
3994f87e TS |
264 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
265 | || mips_opts.isa == ISA_MIPS32R2 \ | |
266 | || mips_opts.isa == ISA_MIPS64 \ | |
267 | || mips_opts.isa == ISA_MIPS64R2) | |
268 | ||
1f25f5d3 CD |
269 | /* True if -mips3d was passed or implied by arguments passed on the |
270 | command line (e.g., by -march). */ | |
271 | static int file_ase_mips3d; | |
272 | ||
deec1734 CD |
273 | /* True if -mdmx was passed or implied by arguments passed on the |
274 | command line (e.g., by -march). */ | |
275 | static int file_ase_mdmx; | |
276 | ||
e16bfa71 TS |
277 | /* True if -msmartmips was passed or implied by arguments passed on the |
278 | command line (e.g., by -march). */ | |
279 | static int file_ase_smartmips; | |
280 | ||
ad3fea08 TS |
281 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
282 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 283 | |
74cd071d CF |
284 | /* True if -mdsp was passed or implied by arguments passed on the |
285 | command line (e.g., by -march). */ | |
286 | static int file_ase_dsp; | |
287 | ||
ad3fea08 TS |
288 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
289 | || mips_opts.isa == ISA_MIPS64R2) | |
290 | ||
65263ce3 TS |
291 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
292 | ||
8b082fb1 TS |
293 | /* True if -mdspr2 was passed or implied by arguments passed on the |
294 | command line (e.g., by -march). */ | |
295 | static int file_ase_dspr2; | |
296 | ||
297 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
298 | || mips_opts.isa == ISA_MIPS64R2) | |
299 | ||
ef2e4d86 CF |
300 | /* True if -mmt was passed or implied by arguments passed on the |
301 | command line (e.g., by -march). */ | |
302 | static int file_ase_mt; | |
303 | ||
ad3fea08 TS |
304 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
305 | || mips_opts.isa == ISA_MIPS64R2) | |
306 | ||
ec68c924 | 307 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 308 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 309 | static const char *mips_arch_string; |
ec68c924 EC |
310 | |
311 | /* The argument of the -mtune= flag. The architecture for which we | |
312 | are optimizing. */ | |
313 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 314 | static const char *mips_tune_string; |
ec68c924 | 315 | |
316f5878 | 316 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
317 | static int mips_32bitmode = 0; |
318 | ||
316f5878 RS |
319 | /* True if the given ABI requires 32-bit registers. */ |
320 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
321 | ||
322 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
323 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
324 | ((ABI) == N32_ABI \ | |
325 | || (ABI) == N64_ABI \ | |
316f5878 RS |
326 | || (ABI) == O64_ABI) |
327 | ||
ad3fea08 | 328 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
329 | #define ISA_HAS_64BIT_REGS(ISA) \ |
330 | ((ISA) == ISA_MIPS3 \ | |
331 | || (ISA) == ISA_MIPS4 \ | |
332 | || (ISA) == ISA_MIPS5 \ | |
333 | || (ISA) == ISA_MIPS64 \ | |
334 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 335 | |
ad3fea08 TS |
336 | /* Return true if ISA supports 64 bit wide float registers. */ |
337 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
338 | ((ISA) == ISA_MIPS3 \ | |
339 | || (ISA) == ISA_MIPS4 \ | |
340 | || (ISA) == ISA_MIPS5 \ | |
341 | || (ISA) == ISA_MIPS32R2 \ | |
342 | || (ISA) == ISA_MIPS64 \ | |
343 | || (ISA) == ISA_MIPS64R2) | |
344 | ||
af7ee8bf CD |
345 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
346 | instructions. */ | |
707bfff6 TS |
347 | #define ISA_HAS_DROR(ISA) \ |
348 | ((ISA) == ISA_MIPS64R2) | |
af7ee8bf CD |
349 | |
350 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
351 | instructions. */ | |
707bfff6 TS |
352 | #define ISA_HAS_ROR(ISA) \ |
353 | ((ISA) == ISA_MIPS32R2 \ | |
354 | || (ISA) == ISA_MIPS64R2 \ | |
355 | || mips_opts.ase_smartmips) | |
356 | ||
7455baf8 TS |
357 | /* Return true if ISA supports single-precision floats in odd registers. */ |
358 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
359 | ((ISA) == ISA_MIPS32 \ | |
360 | || (ISA) == ISA_MIPS32R2 \ | |
361 | || (ISA) == ISA_MIPS64 \ | |
362 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 363 | |
ad3fea08 TS |
364 | /* Return true if ISA supports move to/from high part of a 64-bit |
365 | floating-point register. */ | |
366 | #define ISA_HAS_MXHC1(ISA) \ | |
367 | ((ISA) == ISA_MIPS32R2 \ | |
368 | || (ISA) == ISA_MIPS64R2) | |
369 | ||
e013f690 | 370 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 371 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 372 | |
e013f690 | 373 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 374 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 375 | |
ad3fea08 TS |
376 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
377 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 378 | |
316f5878 | 379 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 380 | |
316f5878 | 381 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 382 | |
3b91255e RS |
383 | /* True if relocations are stored in-place. */ |
384 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
385 | ||
aed1a261 RS |
386 | /* The ABI-derived address size. */ |
387 | #define HAVE_64BIT_ADDRESSES \ | |
388 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
389 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 390 | |
aed1a261 RS |
391 | /* The size of symbolic constants (i.e., expressions of the form |
392 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
393 | #define HAVE_32BIT_SYMBOLS \ | |
394 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
395 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 396 | |
b7c7d6c1 TS |
397 | /* Addresses are loaded in different ways, depending on the address size |
398 | in use. The n32 ABI Documentation also mandates the use of additions | |
399 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 400 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 401 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
402 | |
403 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 404 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
405 | |
406 | #define ADDRESS_LOAD_INSN \ | |
407 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
408 | ||
409 | #define ADDRESS_STORE_INSN \ | |
410 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
411 | ||
a4672219 | 412 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
413 | #define CPU_HAS_MIPS16(cpu) \ |
414 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
415 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 416 | |
60b63b72 RS |
417 | /* True if CPU has a dror instruction. */ |
418 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
419 | ||
420 | /* True if CPU has a ror instruction. */ | |
421 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
422 | ||
c8978940 CD |
423 | /* True if mflo and mfhi can be immediately followed by instructions |
424 | which write to the HI and LO registers. | |
425 | ||
426 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
427 | (at least) two instructions between the reads of HI/LO and | |
428 | instructions which write them, and later ISAs do not. Contradicting | |
429 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
430 | the UM for the NEC Vr5000) document needing the instructions between | |
431 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
432 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
433 | earlier-ISA CPUs for which CPU documentation declares that the | |
434 | instructions are really interlocked. */ | |
435 | #define hilo_interlocks \ | |
436 | (mips_opts.isa == ISA_MIPS32 \ | |
437 | || mips_opts.isa == ISA_MIPS32R2 \ | |
438 | || mips_opts.isa == ISA_MIPS64 \ | |
439 | || mips_opts.isa == ISA_MIPS64R2 \ | |
440 | || mips_opts.arch == CPU_R4010 \ | |
441 | || mips_opts.arch == CPU_R10000 \ | |
442 | || mips_opts.arch == CPU_R12000 \ | |
443 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
444 | || mips_opts.arch == CPU_VR5500 \ |
445 | ) | |
252b5132 RH |
446 | |
447 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
448 | from the GPRs after they are loaded from memory, and thus does not |
449 | require nops to be inserted. This applies to instructions marked | |
450 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
451 | level I. */ | |
252b5132 | 452 | #define gpr_interlocks \ |
e7af610e | 453 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 454 | || mips_opts.arch == CPU_R3900) |
252b5132 | 455 | |
81912461 ILT |
456 | /* Whether the processor uses hardware interlocks to avoid delays |
457 | required by coprocessor instructions, and thus does not require | |
458 | nops to be inserted. This applies to instructions marked | |
459 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
460 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
461 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
462 | levels I, II, and III. */ | |
bdaaa2e1 | 463 | /* Itbl support may require additional care here. */ |
81912461 ILT |
464 | #define cop_interlocks \ |
465 | ((mips_opts.isa != ISA_MIPS1 \ | |
466 | && mips_opts.isa != ISA_MIPS2 \ | |
467 | && mips_opts.isa != ISA_MIPS3) \ | |
468 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
469 | ) |
470 | ||
471 | /* Whether the processor uses hardware interlocks to protect reads | |
472 | from coprocessor registers after they are loaded from memory, and | |
473 | thus does not require nops to be inserted. This applies to | |
474 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
475 | requires at MIPS ISA level I. */ | |
476 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 477 | |
6b76fefe CM |
478 | /* Is this a mfhi or mflo instruction? */ |
479 | #define MF_HILO_INSN(PINFO) \ | |
480 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
481 | ||
252b5132 RH |
482 | /* MIPS PIC level. */ |
483 | ||
a161fe53 | 484 | enum mips_pic_level mips_pic; |
252b5132 | 485 | |
c9914766 | 486 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 487 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 488 | static int mips_big_got = 0; |
252b5132 RH |
489 | |
490 | /* 1 if trap instructions should used for overflow rather than break | |
491 | instructions. */ | |
c9914766 | 492 | static int mips_trap = 0; |
252b5132 | 493 | |
119d663a | 494 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 495 | by assembling two single width halves into two single width floating |
119d663a NC |
496 | point registers which just happen to alias the double width destination |
497 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 498 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
499 | automatically at assemble time. */ |
500 | static int mips_disable_float_construction; | |
501 | ||
252b5132 RH |
502 | /* Non-zero if any .set noreorder directives were used. */ |
503 | ||
504 | static int mips_any_noreorder; | |
505 | ||
6b76fefe CM |
506 | /* Non-zero if nops should be inserted when the register referenced in |
507 | an mfhi/mflo instruction is read in the next two instructions. */ | |
508 | static int mips_7000_hilo_fix; | |
509 | ||
252b5132 | 510 | /* The size of the small data section. */ |
156c2f8b | 511 | static unsigned int g_switch_value = 8; |
252b5132 RH |
512 | /* Whether the -G option was used. */ |
513 | static int g_switch_seen = 0; | |
514 | ||
515 | #define N_RMASK 0xc4 | |
516 | #define N_VFP 0xd4 | |
517 | ||
518 | /* If we can determine in advance that GP optimization won't be | |
519 | possible, we can skip the relaxation stuff that tries to produce | |
520 | GP-relative references. This makes delay slot optimization work | |
521 | better. | |
522 | ||
523 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
524 | gcc output. It needs to guess right for gcc, otherwise gcc |
525 | will put what it thinks is a GP-relative instruction in a branch | |
526 | delay slot. | |
252b5132 RH |
527 | |
528 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
529 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 530 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
531 | |
532 | /* handle of the OPCODE hash table */ | |
533 | static struct hash_control *op_hash = NULL; | |
534 | ||
535 | /* The opcode hash table we use for the mips16. */ | |
536 | static struct hash_control *mips16_op_hash = NULL; | |
537 | ||
538 | /* This array holds the chars that always start a comment. If the | |
539 | pre-processor is disabled, these aren't very useful */ | |
540 | const char comment_chars[] = "#"; | |
541 | ||
542 | /* This array holds the chars that only start a comment at the beginning of | |
543 | a line. If the line seems to have the form '# 123 filename' | |
544 | .line and .file directives will appear in the pre-processed output */ | |
545 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
546 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 547 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
548 | /* Also note that C style comments are always supported. */ |
549 | const char line_comment_chars[] = "#"; | |
550 | ||
bdaaa2e1 | 551 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 552 | const char line_separator_chars[] = ";"; |
252b5132 RH |
553 | |
554 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
555 | const char EXP_CHARS[] = "eE"; | |
556 | ||
557 | /* Chars that mean this number is a floating point constant */ | |
558 | /* As in 0f12.456 */ | |
559 | /* or 0d1.2345e12 */ | |
560 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
561 | ||
562 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
563 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
564 | but nothing is ideal around here. | |
565 | */ | |
566 | ||
567 | static char *insn_error; | |
568 | ||
569 | static int auto_align = 1; | |
570 | ||
571 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
572 | offset in the stack frame from which to restore the $gp register. | |
573 | This is set by the .cprestore pseudo-op, and saved in this | |
574 | variable. */ | |
575 | static offsetT mips_cprestore_offset = -1; | |
576 | ||
67c1ffbe | 577 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 578 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 579 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
580 | static offsetT mips_cpreturn_offset = -1; |
581 | static int mips_cpreturn_register = -1; | |
582 | static int mips_gp_register = GP; | |
def2e0dd | 583 | static int mips_gprel_offset = 0; |
6478892d | 584 | |
7a621144 DJ |
585 | /* Whether mips_cprestore_offset has been set in the current function |
586 | (or whether it has already been warned about, if not). */ | |
587 | static int mips_cprestore_valid = 0; | |
588 | ||
252b5132 RH |
589 | /* This is the register which holds the stack frame, as set by the |
590 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
591 | static int mips_frame_reg = SP; | |
592 | ||
7a621144 DJ |
593 | /* Whether mips_frame_reg has been set in the current function |
594 | (or whether it has already been warned about, if not). */ | |
595 | static int mips_frame_reg_valid = 0; | |
596 | ||
252b5132 RH |
597 | /* To output NOP instructions correctly, we need to keep information |
598 | about the previous two instructions. */ | |
599 | ||
600 | /* Whether we are optimizing. The default value of 2 means to remove | |
601 | unneeded NOPs and swap branch instructions when possible. A value | |
602 | of 1 means to not swap branches. A value of 0 means to always | |
603 | insert NOPs. */ | |
604 | static int mips_optimize = 2; | |
605 | ||
606 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
607 | equivalent to seeing no -g option at all. */ | |
608 | static int mips_debug = 0; | |
609 | ||
7d8e00cf RS |
610 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
611 | #define MAX_VR4130_NOPS 4 | |
612 | ||
613 | /* The maximum number of NOPs needed to fill delay slots. */ | |
614 | #define MAX_DELAY_NOPS 2 | |
615 | ||
616 | /* The maximum number of NOPs needed for any purpose. */ | |
617 | #define MAX_NOPS 4 | |
71400594 RS |
618 | |
619 | /* A list of previous instructions, with index 0 being the most recent. | |
620 | We need to look back MAX_NOPS instructions when filling delay slots | |
621 | or working around processor errata. We need to look back one | |
622 | instruction further if we're thinking about using history[0] to | |
623 | fill a branch delay slot. */ | |
624 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 625 | |
1e915849 RS |
626 | /* Nop instructions used by emit_nop. */ |
627 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
628 | ||
629 | /* The appropriate nop for the current mode. */ | |
630 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 631 | |
252b5132 RH |
632 | /* If this is set, it points to a frag holding nop instructions which |
633 | were inserted before the start of a noreorder section. If those | |
634 | nops turn out to be unnecessary, the size of the frag can be | |
635 | decreased. */ | |
636 | static fragS *prev_nop_frag; | |
637 | ||
638 | /* The number of nop instructions we created in prev_nop_frag. */ | |
639 | static int prev_nop_frag_holds; | |
640 | ||
641 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 642 | prev_nop_frag. */ |
252b5132 RH |
643 | static int prev_nop_frag_required; |
644 | ||
645 | /* The number of instructions we've seen since prev_nop_frag. */ | |
646 | static int prev_nop_frag_since; | |
647 | ||
648 | /* For ECOFF and ELF, relocations against symbols are done in two | |
649 | parts, with a HI relocation and a LO relocation. Each relocation | |
650 | has only 16 bits of space to store an addend. This means that in | |
651 | order for the linker to handle carries correctly, it must be able | |
652 | to locate both the HI and the LO relocation. This means that the | |
653 | relocations must appear in order in the relocation table. | |
654 | ||
655 | In order to implement this, we keep track of each unmatched HI | |
656 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 657 | corresponding LO relocation. */ |
252b5132 | 658 | |
e972090a NC |
659 | struct mips_hi_fixup |
660 | { | |
252b5132 RH |
661 | /* Next HI fixup. */ |
662 | struct mips_hi_fixup *next; | |
663 | /* This fixup. */ | |
664 | fixS *fixp; | |
665 | /* The section this fixup is in. */ | |
666 | segT seg; | |
667 | }; | |
668 | ||
669 | /* The list of unmatched HI relocs. */ | |
670 | ||
671 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
672 | ||
64bdfcaf RS |
673 | /* The frag containing the last explicit relocation operator. |
674 | Null if explicit relocations have not been used. */ | |
675 | ||
676 | static fragS *prev_reloc_op_frag; | |
677 | ||
252b5132 RH |
678 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
679 | ||
680 | #define X ILLEGAL_REG | |
e972090a NC |
681 | static const int mips32_to_16_reg_map[] = |
682 | { | |
252b5132 RH |
683 | X, X, 2, 3, 4, 5, 6, 7, |
684 | X, X, X, X, X, X, X, X, | |
685 | 0, 1, X, X, X, X, X, X, | |
686 | X, X, X, X, X, X, X, X | |
687 | }; | |
688 | #undef X | |
689 | ||
690 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
691 | ||
e972090a NC |
692 | static const unsigned int mips16_to_32_reg_map[] = |
693 | { | |
252b5132 RH |
694 | 16, 17, 2, 3, 4, 5, 6, 7 |
695 | }; | |
60b63b72 | 696 | |
71400594 RS |
697 | /* Classifies the kind of instructions we're interested in when |
698 | implementing -mfix-vr4120. */ | |
699 | enum fix_vr4120_class { | |
700 | FIX_VR4120_MACC, | |
701 | FIX_VR4120_DMACC, | |
702 | FIX_VR4120_MULT, | |
703 | FIX_VR4120_DMULT, | |
704 | FIX_VR4120_DIV, | |
705 | FIX_VR4120_MTHILO, | |
706 | NUM_FIX_VR4120_CLASSES | |
707 | }; | |
708 | ||
709 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if | |
710 | there must be at least one other instruction between an instruction | |
711 | of type X and an instruction of type Y. */ | |
712 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
713 | ||
714 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 715 | static int mips_fix_vr4120; |
4a6a3df4 | 716 | |
7d8e00cf RS |
717 | /* ...likewise -mfix-vr4130. */ |
718 | static int mips_fix_vr4130; | |
719 | ||
4a6a3df4 AO |
720 | /* We don't relax branches by default, since this causes us to expand |
721 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
722 | fail to compute the offset before expanding the macro to the most | |
723 | efficient expansion. */ | |
724 | ||
725 | static int mips_relax_branch; | |
252b5132 | 726 | \f |
4d7206a2 RS |
727 | /* The expansion of many macros depends on the type of symbol that |
728 | they refer to. For example, when generating position-dependent code, | |
729 | a macro that refers to a symbol may have two different expansions, | |
730 | one which uses GP-relative addresses and one which uses absolute | |
731 | addresses. When generating SVR4-style PIC, a macro may have | |
732 | different expansions for local and global symbols. | |
733 | ||
734 | We handle these situations by generating both sequences and putting | |
735 | them in variant frags. In position-dependent code, the first sequence | |
736 | will be the GP-relative one and the second sequence will be the | |
737 | absolute one. In SVR4 PIC, the first sequence will be for global | |
738 | symbols and the second will be for local symbols. | |
739 | ||
584892a6 RS |
740 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
741 | SECOND are the lengths of the two sequences in bytes. These fields | |
742 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
743 | the subtype has the following flags: | |
4d7206a2 | 744 | |
584892a6 RS |
745 | RELAX_USE_SECOND |
746 | Set if it has been decided that we should use the second | |
747 | sequence instead of the first. | |
748 | ||
749 | RELAX_SECOND_LONGER | |
750 | Set in the first variant frag if the macro's second implementation | |
751 | is longer than its first. This refers to the macro as a whole, | |
752 | not an individual relaxation. | |
753 | ||
754 | RELAX_NOMACRO | |
755 | Set in the first variant frag if the macro appeared in a .set nomacro | |
756 | block and if one alternative requires a warning but the other does not. | |
757 | ||
758 | RELAX_DELAY_SLOT | |
759 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
760 | delay slot. | |
4d7206a2 RS |
761 | |
762 | The frag's "opcode" points to the first fixup for relaxable code. | |
763 | ||
764 | Relaxable macros are generated using a sequence such as: | |
765 | ||
766 | relax_start (SYMBOL); | |
767 | ... generate first expansion ... | |
768 | relax_switch (); | |
769 | ... generate second expansion ... | |
770 | relax_end (); | |
771 | ||
772 | The code and fixups for the unwanted alternative are discarded | |
773 | by md_convert_frag. */ | |
584892a6 | 774 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 775 | |
584892a6 RS |
776 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
777 | #define RELAX_SECOND(X) ((X) & 0xff) | |
778 | #define RELAX_USE_SECOND 0x10000 | |
779 | #define RELAX_SECOND_LONGER 0x20000 | |
780 | #define RELAX_NOMACRO 0x40000 | |
781 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 782 | |
4a6a3df4 AO |
783 | /* Branch without likely bit. If label is out of range, we turn: |
784 | ||
785 | beq reg1, reg2, label | |
786 | delay slot | |
787 | ||
788 | into | |
789 | ||
790 | bne reg1, reg2, 0f | |
791 | nop | |
792 | j label | |
793 | 0: delay slot | |
794 | ||
795 | with the following opcode replacements: | |
796 | ||
797 | beq <-> bne | |
798 | blez <-> bgtz | |
799 | bltz <-> bgez | |
800 | bc1f <-> bc1t | |
801 | ||
802 | bltzal <-> bgezal (with jal label instead of j label) | |
803 | ||
804 | Even though keeping the delay slot instruction in the delay slot of | |
805 | the branch would be more efficient, it would be very tricky to do | |
806 | correctly, because we'd have to introduce a variable frag *after* | |
807 | the delay slot instruction, and expand that instead. Let's do it | |
808 | the easy way for now, even if the branch-not-taken case now costs | |
809 | one additional instruction. Out-of-range branches are not supposed | |
810 | to be common, anyway. | |
811 | ||
812 | Branch likely. If label is out of range, we turn: | |
813 | ||
814 | beql reg1, reg2, label | |
815 | delay slot (annulled if branch not taken) | |
816 | ||
817 | into | |
818 | ||
819 | beql reg1, reg2, 1f | |
820 | nop | |
821 | beql $0, $0, 2f | |
822 | nop | |
823 | 1: j[al] label | |
824 | delay slot (executed only if branch taken) | |
825 | 2: | |
826 | ||
827 | It would be possible to generate a shorter sequence by losing the | |
828 | likely bit, generating something like: | |
b34976b6 | 829 | |
4a6a3df4 AO |
830 | bne reg1, reg2, 0f |
831 | nop | |
832 | j[al] label | |
833 | delay slot (executed only if branch taken) | |
834 | 0: | |
835 | ||
836 | beql -> bne | |
837 | bnel -> beq | |
838 | blezl -> bgtz | |
839 | bgtzl -> blez | |
840 | bltzl -> bgez | |
841 | bgezl -> bltz | |
842 | bc1fl -> bc1t | |
843 | bc1tl -> bc1f | |
844 | ||
845 | bltzall -> bgezal (with jal label instead of j label) | |
846 | bgezall -> bltzal (ditto) | |
847 | ||
848 | ||
849 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 850 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
851 | ((relax_substateT) \ |
852 | (0xc0000000 \ | |
853 | | ((toofar) ? 1 : 0) \ | |
854 | | ((link) ? 2 : 0) \ | |
855 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 856 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 857 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
858 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
859 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
860 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 861 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 862 | |
252b5132 RH |
863 | /* For mips16 code, we use an entirely different form of relaxation. |
864 | mips16 supports two versions of most instructions which take | |
865 | immediate values: a small one which takes some small value, and a | |
866 | larger one which takes a 16 bit value. Since branches also follow | |
867 | this pattern, relaxing these values is required. | |
868 | ||
869 | We can assemble both mips16 and normal MIPS code in a single | |
870 | object. Therefore, we need to support this type of relaxation at | |
871 | the same time that we support the relaxation described above. We | |
872 | use the high bit of the subtype field to distinguish these cases. | |
873 | ||
874 | The information we store for this type of relaxation is the | |
875 | argument code found in the opcode file for this relocation, whether | |
876 | the user explicitly requested a small or extended form, and whether | |
877 | the relocation is in a jump or jal delay slot. That tells us the | |
878 | size of the value, and how it should be stored. We also store | |
879 | whether the fragment is considered to be extended or not. We also | |
880 | store whether this is known to be a branch to a different section, | |
881 | whether we have tried to relax this frag yet, and whether we have | |
882 | ever extended a PC relative fragment because of a shift count. */ | |
883 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
884 | (0x80000000 \ | |
885 | | ((type) & 0xff) \ | |
886 | | ((small) ? 0x100 : 0) \ | |
887 | | ((ext) ? 0x200 : 0) \ | |
888 | | ((dslot) ? 0x400 : 0) \ | |
889 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 890 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
891 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
892 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
893 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
894 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
895 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
896 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
897 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
898 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
899 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
900 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
901 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
902 | |
903 | /* Is the given value a sign-extended 32-bit value? */ | |
904 | #define IS_SEXT_32BIT_NUM(x) \ | |
905 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
906 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
907 | ||
908 | /* Is the given value a sign-extended 16-bit value? */ | |
909 | #define IS_SEXT_16BIT_NUM(x) \ | |
910 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
911 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
912 | ||
2051e8c4 MR |
913 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
914 | #define IS_ZEXT_32BIT_NUM(x) \ | |
915 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
916 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
917 | ||
bf12938e RS |
918 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
919 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
920 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
921 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
922 | | (((VALUE) & (MASK)) << (SHIFT))) | |
923 | ||
924 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
925 | SHIFT places. */ | |
926 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
927 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
928 | ||
929 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
930 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
931 | ||
932 | include/opcode/mips.h specifies operand fields using the macros | |
933 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
934 | with "MIPS16OP" instead of "OP". */ | |
935 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
936 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
937 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
938 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
939 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
940 | ||
941 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
942 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
943 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
944 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
945 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
946 | MIPS16OP_MASK_##FIELD, \ | |
947 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
948 | \f |
949 | /* Global variables used when generating relaxable macros. See the | |
950 | comment above RELAX_ENCODE for more details about how relaxation | |
951 | is used. */ | |
952 | static struct { | |
953 | /* 0 if we're not emitting a relaxable macro. | |
954 | 1 if we're emitting the first of the two relaxation alternatives. | |
955 | 2 if we're emitting the second alternative. */ | |
956 | int sequence; | |
957 | ||
958 | /* The first relaxable fixup in the current frag. (In other words, | |
959 | the first fixup that refers to relaxable code.) */ | |
960 | fixS *first_fixup; | |
961 | ||
962 | /* sizes[0] says how many bytes of the first alternative are stored in | |
963 | the current frag. Likewise sizes[1] for the second alternative. */ | |
964 | unsigned int sizes[2]; | |
965 | ||
966 | /* The symbol on which the choice of sequence depends. */ | |
967 | symbolS *symbol; | |
968 | } mips_relax; | |
252b5132 | 969 | \f |
584892a6 RS |
970 | /* Global variables used to decide whether a macro needs a warning. */ |
971 | static struct { | |
972 | /* True if the macro is in a branch delay slot. */ | |
973 | bfd_boolean delay_slot_p; | |
974 | ||
975 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
976 | in bytes and sizes[1] is the length of the second alternative. | |
977 | For non-relaxable macros, both elements give the length of the | |
978 | macro in bytes. */ | |
979 | unsigned int sizes[2]; | |
980 | ||
981 | /* The first variant frag for this macro. */ | |
982 | fragS *first_frag; | |
983 | } mips_macro_warning; | |
984 | \f | |
252b5132 RH |
985 | /* Prototypes for static functions. */ |
986 | ||
17a2f251 | 987 | #define internalError() \ |
252b5132 | 988 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
989 | |
990 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
991 | ||
b34976b6 | 992 | static void append_insn |
4d7206a2 | 993 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
7d10b47d | 994 | static void mips_no_prev_insn (void); |
b34976b6 | 995 | static void mips16_macro_build |
67c0d1eb RS |
996 | (expressionS *, const char *, const char *, va_list); |
997 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
998 | static void macro_start (void); |
999 | static void macro_end (void); | |
17a2f251 TS |
1000 | static void macro (struct mips_cl_insn * ip); |
1001 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 1002 | #ifdef LOSING_COMPILER |
17a2f251 | 1003 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 1004 | #endif |
17a2f251 TS |
1005 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1006 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1007 | static void mips16_immed |
17a2f251 TS |
1008 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
1009 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 1010 | static size_t my_getSmallExpression |
17a2f251 TS |
1011 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1012 | static void my_getExpression (expressionS *, char *); | |
1013 | static void s_align (int); | |
1014 | static void s_change_sec (int); | |
1015 | static void s_change_section (int); | |
1016 | static void s_cons (int); | |
1017 | static void s_float_cons (int); | |
1018 | static void s_mips_globl (int); | |
1019 | static void s_option (int); | |
1020 | static void s_mipsset (int); | |
1021 | static void s_abicalls (int); | |
1022 | static void s_cpload (int); | |
1023 | static void s_cpsetup (int); | |
1024 | static void s_cplocal (int); | |
1025 | static void s_cprestore (int); | |
1026 | static void s_cpreturn (int); | |
1027 | static void s_gpvalue (int); | |
1028 | static void s_gpword (int); | |
1029 | static void s_gpdword (int); | |
1030 | static void s_cpadd (int); | |
1031 | static void s_insn (int); | |
1032 | static void md_obj_begin (void); | |
1033 | static void md_obj_end (void); | |
1034 | static void s_mips_ent (int); | |
1035 | static void s_mips_end (int); | |
1036 | static void s_mips_frame (int); | |
1037 | static void s_mips_mask (int reg_type); | |
1038 | static void s_mips_stab (int); | |
1039 | static void s_mips_weakext (int); | |
1040 | static void s_mips_file (int); | |
1041 | static void s_mips_loc (int); | |
1042 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1043 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1044 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
1045 | |
1046 | /* Table and functions used to map between CPU/ISA names, and | |
1047 | ISA levels, and CPU numbers. */ | |
1048 | ||
e972090a NC |
1049 | struct mips_cpu_info |
1050 | { | |
e7af610e | 1051 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1052 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1053 | int isa; /* ISA level. */ |
1054 | int cpu; /* CPU number (default CPU if ISA). */ | |
1055 | }; | |
1056 | ||
ad3fea08 TS |
1057 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1058 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1059 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1060 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1061 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1062 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1063 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
ad3fea08 | 1064 | |
17a2f251 TS |
1065 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1066 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1067 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1068 | \f |
1069 | /* Pseudo-op table. | |
1070 | ||
1071 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1072 | should be defined here, but are currently unsupported: .alias, | |
1073 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1074 | ||
1075 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1076 | specific to the type of debugging information being generated, and | |
1077 | should be defined by the object format: .aent, .begin, .bend, | |
1078 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1079 | .vreg. | |
1080 | ||
1081 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1082 | not MIPS CPU specific, but are also not specific to the object file | |
1083 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1084 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1085 | |
e972090a NC |
1086 | static const pseudo_typeS mips_pseudo_table[] = |
1087 | { | |
beae10d5 | 1088 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1089 | {"option", s_option, 0}, |
1090 | {"set", s_mipsset, 0}, | |
1091 | {"rdata", s_change_sec, 'r'}, | |
1092 | {"sdata", s_change_sec, 's'}, | |
1093 | {"livereg", s_ignore, 0}, | |
1094 | {"abicalls", s_abicalls, 0}, | |
1095 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1096 | {"cpsetup", s_cpsetup, 0}, |
1097 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1098 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
1099 | {"cpreturn", s_cpreturn, 0}, |
1100 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 1101 | {"gpword", s_gpword, 0}, |
10181a0d | 1102 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1103 | {"cpadd", s_cpadd, 0}, |
1104 | {"insn", s_insn, 0}, | |
1105 | ||
beae10d5 | 1106 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
1107 | chips. */ |
1108 | {"asciiz", stringer, 1}, | |
1109 | {"bss", s_change_sec, 'b'}, | |
1110 | {"err", s_err, 0}, | |
1111 | {"half", s_cons, 1}, | |
1112 | {"dword", s_cons, 3}, | |
1113 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1114 | {"origin", s_org, 0}, |
1115 | {"repeat", s_rept, 0}, | |
252b5132 | 1116 | |
beae10d5 | 1117 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1118 | here for one reason or another. */ |
1119 | {"align", s_align, 0}, | |
1120 | {"byte", s_cons, 0}, | |
1121 | {"data", s_change_sec, 'd'}, | |
1122 | {"double", s_float_cons, 'd'}, | |
1123 | {"float", s_float_cons, 'f'}, | |
1124 | {"globl", s_mips_globl, 0}, | |
1125 | {"global", s_mips_globl, 0}, | |
1126 | {"hword", s_cons, 1}, | |
1127 | {"int", s_cons, 2}, | |
1128 | {"long", s_cons, 2}, | |
1129 | {"octa", s_cons, 4}, | |
1130 | {"quad", s_cons, 3}, | |
cca86cc8 | 1131 | {"section", s_change_section, 0}, |
252b5132 RH |
1132 | {"short", s_cons, 1}, |
1133 | {"single", s_float_cons, 'f'}, | |
1134 | {"stabn", s_mips_stab, 'n'}, | |
1135 | {"text", s_change_sec, 't'}, | |
1136 | {"word", s_cons, 2}, | |
add56521 | 1137 | |
add56521 | 1138 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1139 | |
43841e91 | 1140 | { NULL, NULL, 0 }, |
252b5132 RH |
1141 | }; |
1142 | ||
e972090a NC |
1143 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1144 | { | |
beae10d5 KH |
1145 | /* These pseudo-ops should be defined by the object file format. |
1146 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1147 | {"aent", s_mips_ent, 1}, |
1148 | {"bgnb", s_ignore, 0}, | |
1149 | {"end", s_mips_end, 0}, | |
1150 | {"endb", s_ignore, 0}, | |
1151 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1152 | {"file", s_mips_file, 0}, |
252b5132 RH |
1153 | {"fmask", s_mips_mask, 'F'}, |
1154 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1155 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1156 | {"mask", s_mips_mask, 'R'}, |
1157 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1158 | { NULL, NULL, 0 }, |
252b5132 RH |
1159 | }; |
1160 | ||
17a2f251 | 1161 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1162 | |
1163 | void | |
17a2f251 | 1164 | mips_pop_insert (void) |
252b5132 RH |
1165 | { |
1166 | pop_insert (mips_pseudo_table); | |
1167 | if (! ECOFF_DEBUGGING) | |
1168 | pop_insert (mips_nonecoff_pseudo_table); | |
1169 | } | |
1170 | \f | |
1171 | /* Symbols labelling the current insn. */ | |
1172 | ||
e972090a NC |
1173 | struct insn_label_list |
1174 | { | |
252b5132 RH |
1175 | struct insn_label_list *next; |
1176 | symbolS *label; | |
1177 | }; | |
1178 | ||
252b5132 | 1179 | static struct insn_label_list *free_insn_labels; |
a8dbcb85 | 1180 | #define label_list tc_segment_info_data |
252b5132 | 1181 | |
17a2f251 | 1182 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1183 | |
1184 | static inline void | |
17a2f251 | 1185 | mips_clear_insn_labels (void) |
252b5132 RH |
1186 | { |
1187 | register struct insn_label_list **pl; | |
a8dbcb85 | 1188 | segment_info_type *si; |
252b5132 | 1189 | |
a8dbcb85 TS |
1190 | if (now_seg) |
1191 | { | |
1192 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1193 | ; | |
1194 | ||
1195 | si = seg_info (now_seg); | |
1196 | *pl = si->label_list; | |
1197 | si->label_list = NULL; | |
1198 | } | |
252b5132 | 1199 | } |
a8dbcb85 | 1200 | |
252b5132 RH |
1201 | \f |
1202 | static char *expr_end; | |
1203 | ||
1204 | /* Expressions which appear in instructions. These are set by | |
1205 | mips_ip. */ | |
1206 | ||
1207 | static expressionS imm_expr; | |
5f74bc13 | 1208 | static expressionS imm2_expr; |
252b5132 RH |
1209 | static expressionS offset_expr; |
1210 | ||
1211 | /* Relocs associated with imm_expr and offset_expr. */ | |
1212 | ||
f6688943 TS |
1213 | static bfd_reloc_code_real_type imm_reloc[3] |
1214 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1215 | static bfd_reloc_code_real_type offset_reloc[3] | |
1216 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1217 | |
252b5132 RH |
1218 | /* These are set by mips16_ip if an explicit extension is used. */ |
1219 | ||
b34976b6 | 1220 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1221 | |
7ed4a06a | 1222 | #ifdef OBJ_ELF |
ecb4347a DJ |
1223 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1224 | ECOFF debugging. */ | |
252b5132 RH |
1225 | |
1226 | static segT pdr_seg; | |
7ed4a06a | 1227 | #endif |
252b5132 | 1228 | |
e013f690 TS |
1229 | /* The default target format to use. */ |
1230 | ||
1231 | const char * | |
17a2f251 | 1232 | mips_target_format (void) |
e013f690 TS |
1233 | { |
1234 | switch (OUTPUT_FLAVOR) | |
1235 | { | |
e013f690 TS |
1236 | case bfd_target_ecoff_flavour: |
1237 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1238 | case bfd_target_coff_flavour: | |
1239 | return "pe-mips"; | |
1240 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1241 | #ifdef TE_VXWORKS |
1242 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1243 | return (target_big_endian | |
1244 | ? "elf32-bigmips-vxworks" | |
1245 | : "elf32-littlemips-vxworks"); | |
1246 | #endif | |
e013f690 | 1247 | #ifdef TE_TMIPS |
cfe86eaa | 1248 | /* This is traditional mips. */ |
e013f690 | 1249 | return (target_big_endian |
cfe86eaa TS |
1250 | ? (HAVE_64BIT_OBJECTS |
1251 | ? "elf64-tradbigmips" | |
1252 | : (HAVE_NEWABI | |
1253 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1254 | : (HAVE_64BIT_OBJECTS | |
1255 | ? "elf64-tradlittlemips" | |
1256 | : (HAVE_NEWABI | |
1257 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1258 | #else |
1259 | return (target_big_endian | |
cfe86eaa TS |
1260 | ? (HAVE_64BIT_OBJECTS |
1261 | ? "elf64-bigmips" | |
1262 | : (HAVE_NEWABI | |
1263 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1264 | : (HAVE_64BIT_OBJECTS | |
1265 | ? "elf64-littlemips" | |
1266 | : (HAVE_NEWABI | |
1267 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1268 | #endif |
1269 | default: | |
1270 | abort (); | |
1271 | return NULL; | |
1272 | } | |
1273 | } | |
1274 | ||
1e915849 RS |
1275 | /* Return the length of instruction INSN. */ |
1276 | ||
1277 | static inline unsigned int | |
1278 | insn_length (const struct mips_cl_insn *insn) | |
1279 | { | |
1280 | if (!mips_opts.mips16) | |
1281 | return 4; | |
1282 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1283 | } | |
1284 | ||
1285 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1286 | ||
1287 | static void | |
1288 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1289 | { | |
1290 | size_t i; | |
1291 | ||
1292 | insn->insn_mo = mo; | |
1293 | insn->use_extend = FALSE; | |
1294 | insn->extend = 0; | |
1295 | insn->insn_opcode = mo->match; | |
1296 | insn->frag = NULL; | |
1297 | insn->where = 0; | |
1298 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1299 | insn->fixp[i] = NULL; | |
1300 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1301 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1302 | insn->mips16_absolute_jump_p = 0; | |
1303 | } | |
1304 | ||
1305 | /* Install INSN at the location specified by its "frag" and "where" fields. */ | |
1306 | ||
1307 | static void | |
1308 | install_insn (const struct mips_cl_insn *insn) | |
1309 | { | |
1310 | char *f = insn->frag->fr_literal + insn->where; | |
1311 | if (!mips_opts.mips16) | |
1312 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1313 | else if (insn->mips16_absolute_jump_p) | |
1314 | { | |
1315 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1316 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1317 | } | |
1318 | else | |
1319 | { | |
1320 | if (insn->use_extend) | |
1321 | { | |
1322 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1323 | f += 2; | |
1324 | } | |
1325 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1326 | } | |
1327 | } | |
1328 | ||
1329 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1330 | and install the opcode in the new location. */ | |
1331 | ||
1332 | static void | |
1333 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1334 | { | |
1335 | size_t i; | |
1336 | ||
1337 | insn->frag = frag; | |
1338 | insn->where = where; | |
1339 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1340 | if (insn->fixp[i] != NULL) | |
1341 | { | |
1342 | insn->fixp[i]->fx_frag = frag; | |
1343 | insn->fixp[i]->fx_where = where; | |
1344 | } | |
1345 | install_insn (insn); | |
1346 | } | |
1347 | ||
1348 | /* Add INSN to the end of the output. */ | |
1349 | ||
1350 | static void | |
1351 | add_fixed_insn (struct mips_cl_insn *insn) | |
1352 | { | |
1353 | char *f = frag_more (insn_length (insn)); | |
1354 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1355 | } | |
1356 | ||
1357 | /* Start a variant frag and move INSN to the start of the variant part, | |
1358 | marking it as fixed. The other arguments are as for frag_var. */ | |
1359 | ||
1360 | static void | |
1361 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1362 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1363 | { | |
1364 | frag_grow (max_chars); | |
1365 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1366 | insn->fixed_p = 1; | |
1367 | frag_var (rs_machine_dependent, max_chars, var, | |
1368 | subtype, symbol, offset, NULL); | |
1369 | } | |
1370 | ||
1371 | /* Insert N copies of INSN into the history buffer, starting at | |
1372 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1373 | ||
1374 | static void | |
1375 | insert_into_history (unsigned int first, unsigned int n, | |
1376 | const struct mips_cl_insn *insn) | |
1377 | { | |
1378 | if (mips_relax.sequence != 2) | |
1379 | { | |
1380 | unsigned int i; | |
1381 | ||
1382 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1383 | if (i >= first + n) | |
1384 | history[i] = history[i - n]; | |
1385 | else | |
1386 | history[i] = *insn; | |
1387 | } | |
1388 | } | |
1389 | ||
1390 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1391 | ||
1392 | static void | |
1393 | emit_nop (void) | |
1394 | { | |
1395 | add_fixed_insn (NOP_INSN); | |
1396 | insert_into_history (0, 1, NOP_INSN); | |
1397 | } | |
1398 | ||
71400594 RS |
1399 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1400 | the idea is to make it obvious at a glance that each errata is | |
1401 | included. */ | |
1402 | ||
1403 | static void | |
1404 | init_vr4120_conflicts (void) | |
1405 | { | |
1406 | #define CONFLICT(FIRST, SECOND) \ | |
1407 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1408 | ||
1409 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1410 | CONFLICT (MACC, DIV); | |
1411 | CONFLICT (DMACC, DIV); | |
1412 | ||
1413 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1414 | CONFLICT (DMULT, DMULT); | |
1415 | CONFLICT (DMULT, DMACC); | |
1416 | CONFLICT (DMACC, DMULT); | |
1417 | CONFLICT (DMACC, DMACC); | |
1418 | ||
1419 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1420 | CONFLICT (MACC, MTHILO); | |
1421 | CONFLICT (DMACC, MTHILO); | |
1422 | ||
1423 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1424 | instruction is executed immediately after a MACC or DMACC | |
1425 | instruction, the result of [either instruction] is incorrect." */ | |
1426 | CONFLICT (MACC, MULT); | |
1427 | CONFLICT (MACC, DMULT); | |
1428 | CONFLICT (DMACC, MULT); | |
1429 | CONFLICT (DMACC, DMULT); | |
1430 | ||
1431 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1432 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1433 | DDIV or DDIVU instruction, the result of the MACC or | |
1434 | DMACC instruction is incorrect.". */ | |
1435 | CONFLICT (DMULT, MACC); | |
1436 | CONFLICT (DMULT, DMACC); | |
1437 | CONFLICT (DIV, MACC); | |
1438 | CONFLICT (DIV, DMACC); | |
1439 | ||
1440 | #undef CONFLICT | |
1441 | } | |
1442 | ||
707bfff6 TS |
1443 | struct regname { |
1444 | const char *name; | |
1445 | unsigned int num; | |
1446 | }; | |
1447 | ||
1448 | #define RTYPE_MASK 0x1ff00 | |
1449 | #define RTYPE_NUM 0x00100 | |
1450 | #define RTYPE_FPU 0x00200 | |
1451 | #define RTYPE_FCC 0x00400 | |
1452 | #define RTYPE_VEC 0x00800 | |
1453 | #define RTYPE_GP 0x01000 | |
1454 | #define RTYPE_CP0 0x02000 | |
1455 | #define RTYPE_PC 0x04000 | |
1456 | #define RTYPE_ACC 0x08000 | |
1457 | #define RTYPE_CCC 0x10000 | |
1458 | #define RNUM_MASK 0x000ff | |
1459 | #define RWARN 0x80000 | |
1460 | ||
1461 | #define GENERIC_REGISTER_NUMBERS \ | |
1462 | {"$0", RTYPE_NUM | 0}, \ | |
1463 | {"$1", RTYPE_NUM | 1}, \ | |
1464 | {"$2", RTYPE_NUM | 2}, \ | |
1465 | {"$3", RTYPE_NUM | 3}, \ | |
1466 | {"$4", RTYPE_NUM | 4}, \ | |
1467 | {"$5", RTYPE_NUM | 5}, \ | |
1468 | {"$6", RTYPE_NUM | 6}, \ | |
1469 | {"$7", RTYPE_NUM | 7}, \ | |
1470 | {"$8", RTYPE_NUM | 8}, \ | |
1471 | {"$9", RTYPE_NUM | 9}, \ | |
1472 | {"$10", RTYPE_NUM | 10}, \ | |
1473 | {"$11", RTYPE_NUM | 11}, \ | |
1474 | {"$12", RTYPE_NUM | 12}, \ | |
1475 | {"$13", RTYPE_NUM | 13}, \ | |
1476 | {"$14", RTYPE_NUM | 14}, \ | |
1477 | {"$15", RTYPE_NUM | 15}, \ | |
1478 | {"$16", RTYPE_NUM | 16}, \ | |
1479 | {"$17", RTYPE_NUM | 17}, \ | |
1480 | {"$18", RTYPE_NUM | 18}, \ | |
1481 | {"$19", RTYPE_NUM | 19}, \ | |
1482 | {"$20", RTYPE_NUM | 20}, \ | |
1483 | {"$21", RTYPE_NUM | 21}, \ | |
1484 | {"$22", RTYPE_NUM | 22}, \ | |
1485 | {"$23", RTYPE_NUM | 23}, \ | |
1486 | {"$24", RTYPE_NUM | 24}, \ | |
1487 | {"$25", RTYPE_NUM | 25}, \ | |
1488 | {"$26", RTYPE_NUM | 26}, \ | |
1489 | {"$27", RTYPE_NUM | 27}, \ | |
1490 | {"$28", RTYPE_NUM | 28}, \ | |
1491 | {"$29", RTYPE_NUM | 29}, \ | |
1492 | {"$30", RTYPE_NUM | 30}, \ | |
1493 | {"$31", RTYPE_NUM | 31} | |
1494 | ||
1495 | #define FPU_REGISTER_NAMES \ | |
1496 | {"$f0", RTYPE_FPU | 0}, \ | |
1497 | {"$f1", RTYPE_FPU | 1}, \ | |
1498 | {"$f2", RTYPE_FPU | 2}, \ | |
1499 | {"$f3", RTYPE_FPU | 3}, \ | |
1500 | {"$f4", RTYPE_FPU | 4}, \ | |
1501 | {"$f5", RTYPE_FPU | 5}, \ | |
1502 | {"$f6", RTYPE_FPU | 6}, \ | |
1503 | {"$f7", RTYPE_FPU | 7}, \ | |
1504 | {"$f8", RTYPE_FPU | 8}, \ | |
1505 | {"$f9", RTYPE_FPU | 9}, \ | |
1506 | {"$f10", RTYPE_FPU | 10}, \ | |
1507 | {"$f11", RTYPE_FPU | 11}, \ | |
1508 | {"$f12", RTYPE_FPU | 12}, \ | |
1509 | {"$f13", RTYPE_FPU | 13}, \ | |
1510 | {"$f14", RTYPE_FPU | 14}, \ | |
1511 | {"$f15", RTYPE_FPU | 15}, \ | |
1512 | {"$f16", RTYPE_FPU | 16}, \ | |
1513 | {"$f17", RTYPE_FPU | 17}, \ | |
1514 | {"$f18", RTYPE_FPU | 18}, \ | |
1515 | {"$f19", RTYPE_FPU | 19}, \ | |
1516 | {"$f20", RTYPE_FPU | 20}, \ | |
1517 | {"$f21", RTYPE_FPU | 21}, \ | |
1518 | {"$f22", RTYPE_FPU | 22}, \ | |
1519 | {"$f23", RTYPE_FPU | 23}, \ | |
1520 | {"$f24", RTYPE_FPU | 24}, \ | |
1521 | {"$f25", RTYPE_FPU | 25}, \ | |
1522 | {"$f26", RTYPE_FPU | 26}, \ | |
1523 | {"$f27", RTYPE_FPU | 27}, \ | |
1524 | {"$f28", RTYPE_FPU | 28}, \ | |
1525 | {"$f29", RTYPE_FPU | 29}, \ | |
1526 | {"$f30", RTYPE_FPU | 30}, \ | |
1527 | {"$f31", RTYPE_FPU | 31} | |
1528 | ||
1529 | #define FPU_CONDITION_CODE_NAMES \ | |
1530 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1531 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1532 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1533 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1534 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1535 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1536 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1537 | {"$fcc7", RTYPE_FCC | 7} | |
1538 | ||
1539 | #define COPROC_CONDITION_CODE_NAMES \ | |
1540 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1541 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1542 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1543 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1544 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1545 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1546 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1547 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1548 | ||
1549 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1550 | {"$a4", RTYPE_GP | 8}, \ | |
1551 | {"$a5", RTYPE_GP | 9}, \ | |
1552 | {"$a6", RTYPE_GP | 10}, \ | |
1553 | {"$a7", RTYPE_GP | 11}, \ | |
1554 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1555 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1556 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1557 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1558 | {"$t0", RTYPE_GP | 12}, \ | |
1559 | {"$t1", RTYPE_GP | 13}, \ | |
1560 | {"$t2", RTYPE_GP | 14}, \ | |
1561 | {"$t3", RTYPE_GP | 15} | |
1562 | ||
1563 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1564 | {"$t0", RTYPE_GP | 8}, \ | |
1565 | {"$t1", RTYPE_GP | 9}, \ | |
1566 | {"$t2", RTYPE_GP | 10}, \ | |
1567 | {"$t3", RTYPE_GP | 11}, \ | |
1568 | {"$t4", RTYPE_GP | 12}, \ | |
1569 | {"$t5", RTYPE_GP | 13}, \ | |
1570 | {"$t6", RTYPE_GP | 14}, \ | |
1571 | {"$t7", RTYPE_GP | 15}, \ | |
1572 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1573 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1574 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1575 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
1576 | ||
1577 | /* Remaining symbolic register names */ | |
1578 | #define SYMBOLIC_REGISTER_NAMES \ | |
1579 | {"$zero", RTYPE_GP | 0}, \ | |
1580 | {"$at", RTYPE_GP | 1}, \ | |
1581 | {"$AT", RTYPE_GP | 1}, \ | |
1582 | {"$v0", RTYPE_GP | 2}, \ | |
1583 | {"$v1", RTYPE_GP | 3}, \ | |
1584 | {"$a0", RTYPE_GP | 4}, \ | |
1585 | {"$a1", RTYPE_GP | 5}, \ | |
1586 | {"$a2", RTYPE_GP | 6}, \ | |
1587 | {"$a3", RTYPE_GP | 7}, \ | |
1588 | {"$s0", RTYPE_GP | 16}, \ | |
1589 | {"$s1", RTYPE_GP | 17}, \ | |
1590 | {"$s2", RTYPE_GP | 18}, \ | |
1591 | {"$s3", RTYPE_GP | 19}, \ | |
1592 | {"$s4", RTYPE_GP | 20}, \ | |
1593 | {"$s5", RTYPE_GP | 21}, \ | |
1594 | {"$s6", RTYPE_GP | 22}, \ | |
1595 | {"$s7", RTYPE_GP | 23}, \ | |
1596 | {"$t8", RTYPE_GP | 24}, \ | |
1597 | {"$t9", RTYPE_GP | 25}, \ | |
1598 | {"$k0", RTYPE_GP | 26}, \ | |
1599 | {"$kt0", RTYPE_GP | 26}, \ | |
1600 | {"$k1", RTYPE_GP | 27}, \ | |
1601 | {"$kt1", RTYPE_GP | 27}, \ | |
1602 | {"$gp", RTYPE_GP | 28}, \ | |
1603 | {"$sp", RTYPE_GP | 29}, \ | |
1604 | {"$s8", RTYPE_GP | 30}, \ | |
1605 | {"$fp", RTYPE_GP | 30}, \ | |
1606 | {"$ra", RTYPE_GP | 31} | |
1607 | ||
1608 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
1609 | {"$pc", RTYPE_PC | 0} | |
1610 | ||
1611 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
1612 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
1613 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
1614 | {"$v2", RTYPE_VEC | 2}, \ | |
1615 | {"$v3", RTYPE_VEC | 3}, \ | |
1616 | {"$v4", RTYPE_VEC | 4}, \ | |
1617 | {"$v5", RTYPE_VEC | 5}, \ | |
1618 | {"$v6", RTYPE_VEC | 6}, \ | |
1619 | {"$v7", RTYPE_VEC | 7}, \ | |
1620 | {"$v8", RTYPE_VEC | 8}, \ | |
1621 | {"$v9", RTYPE_VEC | 9}, \ | |
1622 | {"$v10", RTYPE_VEC | 10}, \ | |
1623 | {"$v11", RTYPE_VEC | 11}, \ | |
1624 | {"$v12", RTYPE_VEC | 12}, \ | |
1625 | {"$v13", RTYPE_VEC | 13}, \ | |
1626 | {"$v14", RTYPE_VEC | 14}, \ | |
1627 | {"$v15", RTYPE_VEC | 15}, \ | |
1628 | {"$v16", RTYPE_VEC | 16}, \ | |
1629 | {"$v17", RTYPE_VEC | 17}, \ | |
1630 | {"$v18", RTYPE_VEC | 18}, \ | |
1631 | {"$v19", RTYPE_VEC | 19}, \ | |
1632 | {"$v20", RTYPE_VEC | 20}, \ | |
1633 | {"$v21", RTYPE_VEC | 21}, \ | |
1634 | {"$v22", RTYPE_VEC | 22}, \ | |
1635 | {"$v23", RTYPE_VEC | 23}, \ | |
1636 | {"$v24", RTYPE_VEC | 24}, \ | |
1637 | {"$v25", RTYPE_VEC | 25}, \ | |
1638 | {"$v26", RTYPE_VEC | 26}, \ | |
1639 | {"$v27", RTYPE_VEC | 27}, \ | |
1640 | {"$v28", RTYPE_VEC | 28}, \ | |
1641 | {"$v29", RTYPE_VEC | 29}, \ | |
1642 | {"$v30", RTYPE_VEC | 30}, \ | |
1643 | {"$v31", RTYPE_VEC | 31} | |
1644 | ||
1645 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
1646 | {"$ac0", RTYPE_ACC | 0}, \ | |
1647 | {"$ac1", RTYPE_ACC | 1}, \ | |
1648 | {"$ac2", RTYPE_ACC | 2}, \ | |
1649 | {"$ac3", RTYPE_ACC | 3} | |
1650 | ||
1651 | static const struct regname reg_names[] = { | |
1652 | GENERIC_REGISTER_NUMBERS, | |
1653 | FPU_REGISTER_NAMES, | |
1654 | FPU_CONDITION_CODE_NAMES, | |
1655 | COPROC_CONDITION_CODE_NAMES, | |
1656 | ||
1657 | /* The $txx registers depends on the abi, | |
1658 | these will be added later into the symbol table from | |
1659 | one of the tables below once mips_abi is set after | |
1660 | parsing of arguments from the command line. */ | |
1661 | SYMBOLIC_REGISTER_NAMES, | |
1662 | ||
1663 | MIPS16_SPECIAL_REGISTER_NAMES, | |
1664 | MDMX_VECTOR_REGISTER_NAMES, | |
1665 | MIPS_DSP_ACCUMULATOR_NAMES, | |
1666 | {0, 0} | |
1667 | }; | |
1668 | ||
1669 | static const struct regname reg_names_o32[] = { | |
1670 | O32_SYMBOLIC_REGISTER_NAMES, | |
1671 | {0, 0} | |
1672 | }; | |
1673 | ||
1674 | static const struct regname reg_names_n32n64[] = { | |
1675 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
1676 | {0, 0} | |
1677 | }; | |
1678 | ||
1679 | static int | |
1680 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
1681 | { | |
1682 | symbolS *symbolP; | |
1683 | char *e; | |
1684 | char save_c; | |
1685 | int reg = -1; | |
1686 | ||
1687 | /* Find end of name. */ | |
1688 | e = *s; | |
1689 | if (is_name_beginner (*e)) | |
1690 | ++e; | |
1691 | while (is_part_of_name (*e)) | |
1692 | ++e; | |
1693 | ||
1694 | /* Terminate name. */ | |
1695 | save_c = *e; | |
1696 | *e = '\0'; | |
1697 | ||
1698 | /* Look for a register symbol. */ | |
1699 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
1700 | { | |
1701 | int r = S_GET_VALUE (symbolP); | |
1702 | if (r & types) | |
1703 | reg = r & RNUM_MASK; | |
1704 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
1705 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
1706 | reg = (r & RNUM_MASK) - 2; | |
1707 | } | |
1708 | /* Else see if this is a register defined in an itbl entry. */ | |
1709 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
1710 | { | |
1711 | char *n = *s; | |
1712 | unsigned long r; | |
1713 | ||
1714 | if (*n == '$') | |
1715 | ++n; | |
1716 | if (itbl_get_reg_val (n, &r)) | |
1717 | reg = r & RNUM_MASK; | |
1718 | } | |
1719 | ||
1720 | /* Advance to next token if a register was recognised. */ | |
1721 | if (reg >= 0) | |
1722 | *s = e; | |
1723 | else if (types & RWARN) | |
1724 | as_warn ("Unrecognized register name `%s'", *s); | |
1725 | ||
1726 | *e = save_c; | |
1727 | if (regnop) | |
1728 | *regnop = reg; | |
1729 | return reg >= 0; | |
1730 | } | |
1731 | ||
1732 | /* This function is called once, at assembler startup time. It should set up | |
1733 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 1734 | |
252b5132 | 1735 | void |
17a2f251 | 1736 | md_begin (void) |
252b5132 | 1737 | { |
3994f87e | 1738 | const char *retval = NULL; |
156c2f8b | 1739 | int i = 0; |
252b5132 | 1740 | int broken = 0; |
1f25f5d3 | 1741 | |
0a44bf69 RS |
1742 | if (mips_pic != NO_PIC) |
1743 | { | |
1744 | if (g_switch_seen && g_switch_value != 0) | |
1745 | as_bad (_("-G may not be used in position-independent code")); | |
1746 | g_switch_value = 0; | |
1747 | } | |
1748 | ||
fef14a42 | 1749 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1750 | as_warn (_("Could not set architecture and machine")); |
1751 | ||
252b5132 RH |
1752 | op_hash = hash_new (); |
1753 | ||
1754 | for (i = 0; i < NUMOPCODES;) | |
1755 | { | |
1756 | const char *name = mips_opcodes[i].name; | |
1757 | ||
17a2f251 | 1758 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1759 | if (retval != NULL) |
1760 | { | |
1761 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1762 | mips_opcodes[i].name, retval); | |
1763 | /* Probably a memory allocation problem? Give up now. */ | |
1764 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1765 | } | |
1766 | do | |
1767 | { | |
1768 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1769 | { | |
1770 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1771 | broken = 1; | |
1e915849 RS |
1772 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1773 | { | |
1774 | create_insn (&nop_insn, mips_opcodes + i); | |
1775 | nop_insn.fixed_p = 1; | |
1776 | } | |
252b5132 RH |
1777 | } |
1778 | ++i; | |
1779 | } | |
1780 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1781 | } | |
1782 | ||
1783 | mips16_op_hash = hash_new (); | |
1784 | ||
1785 | i = 0; | |
1786 | while (i < bfd_mips16_num_opcodes) | |
1787 | { | |
1788 | const char *name = mips16_opcodes[i].name; | |
1789 | ||
17a2f251 | 1790 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1791 | if (retval != NULL) |
1792 | as_fatal (_("internal: can't hash `%s': %s"), | |
1793 | mips16_opcodes[i].name, retval); | |
1794 | do | |
1795 | { | |
1796 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1797 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1798 | != mips16_opcodes[i].match)) | |
1799 | { | |
1800 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1801 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1802 | broken = 1; | |
1803 | } | |
1e915849 RS |
1804 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1805 | { | |
1806 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1807 | mips16_nop_insn.fixed_p = 1; | |
1808 | } | |
252b5132 RH |
1809 | ++i; |
1810 | } | |
1811 | while (i < bfd_mips16_num_opcodes | |
1812 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1813 | } | |
1814 | ||
1815 | if (broken) | |
1816 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1817 | ||
1818 | /* We add all the general register names to the symbol table. This | |
1819 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
1820 | for (i = 0; reg_names[i].name; i++) |
1821 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
1822 | reg_names[i].num, // & RNUM_MASK, | |
1823 | &zero_address_frag)); | |
1824 | if (HAVE_NEWABI) | |
1825 | for (i = 0; reg_names_n32n64[i].name; i++) | |
1826 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
1827 | reg_names_n32n64[i].num, // & RNUM_MASK, | |
252b5132 | 1828 | &zero_address_frag)); |
707bfff6 TS |
1829 | else |
1830 | for (i = 0; reg_names_o32[i].name; i++) | |
1831 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
1832 | reg_names_o32[i].num, // & RNUM_MASK, | |
6047c971 | 1833 | &zero_address_frag)); |
6047c971 | 1834 | |
7d10b47d | 1835 | mips_no_prev_insn (); |
252b5132 RH |
1836 | |
1837 | mips_gprmask = 0; | |
1838 | mips_cprmask[0] = 0; | |
1839 | mips_cprmask[1] = 0; | |
1840 | mips_cprmask[2] = 0; | |
1841 | mips_cprmask[3] = 0; | |
1842 | ||
1843 | /* set the default alignment for the text section (2**2) */ | |
1844 | record_alignment (text_section, 2); | |
1845 | ||
4d0d148d | 1846 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 1847 | |
707bfff6 | 1848 | #ifdef OBJ_ELF |
f43abd2b | 1849 | if (IS_ELF) |
252b5132 | 1850 | { |
0a44bf69 RS |
1851 | /* On a native system other than VxWorks, sections must be aligned |
1852 | to 16 byte boundaries. When configured for an embedded ELF | |
1853 | target, we don't bother. */ | |
1854 | if (strcmp (TARGET_OS, "elf") != 0 | |
1855 | && strcmp (TARGET_OS, "vxworks") != 0) | |
252b5132 RH |
1856 | { |
1857 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1858 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1859 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1860 | } | |
1861 | ||
1862 | /* Create a .reginfo section for register masks and a .mdebug | |
1863 | section for debugging information. */ | |
1864 | { | |
1865 | segT seg; | |
1866 | subsegT subseg; | |
1867 | flagword flags; | |
1868 | segT sec; | |
1869 | ||
1870 | seg = now_seg; | |
1871 | subseg = now_subseg; | |
1872 | ||
1873 | /* The ABI says this section should be loaded so that the | |
1874 | running program can access it. However, we don't load it | |
1875 | if we are configured for an embedded target */ | |
1876 | flags = SEC_READONLY | SEC_DATA; | |
1877 | if (strcmp (TARGET_OS, "elf") != 0) | |
1878 | flags |= SEC_ALLOC | SEC_LOAD; | |
1879 | ||
316f5878 | 1880 | if (mips_abi != N64_ABI) |
252b5132 RH |
1881 | { |
1882 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1883 | ||
195325d2 TS |
1884 | bfd_set_section_flags (stdoutput, sec, flags); |
1885 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1886 | |
252b5132 | 1887 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
1888 | } |
1889 | else | |
1890 | { | |
1891 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1892 | .reginfo section. */ | |
1893 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1894 | bfd_set_section_flags (stdoutput, sec, flags); |
1895 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 1896 | |
252b5132 RH |
1897 | /* Set up the option header. */ |
1898 | { | |
1899 | Elf_Internal_Options opthdr; | |
1900 | char *f; | |
1901 | ||
1902 | opthdr.kind = ODK_REGINFO; | |
1903 | opthdr.size = (sizeof (Elf_External_Options) | |
1904 | + sizeof (Elf64_External_RegInfo)); | |
1905 | opthdr.section = 0; | |
1906 | opthdr.info = 0; | |
1907 | f = frag_more (sizeof (Elf_External_Options)); | |
1908 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1909 | (Elf_External_Options *) f); | |
1910 | ||
1911 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1912 | } | |
252b5132 RH |
1913 | } |
1914 | ||
1915 | if (ECOFF_DEBUGGING) | |
1916 | { | |
1917 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1918 | (void) bfd_set_section_flags (stdoutput, sec, | |
1919 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1920 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1921 | } | |
f43abd2b | 1922 | else if (mips_flag_pdr) |
ecb4347a DJ |
1923 | { |
1924 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1925 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1926 | SEC_READONLY | SEC_RELOC | |
1927 | | SEC_DEBUGGING); | |
1928 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1929 | } | |
252b5132 RH |
1930 | |
1931 | subseg_set (seg, subseg); | |
1932 | } | |
1933 | } | |
707bfff6 | 1934 | #endif /* OBJ_ELF */ |
252b5132 RH |
1935 | |
1936 | if (! ECOFF_DEBUGGING) | |
1937 | md_obj_begin (); | |
71400594 RS |
1938 | |
1939 | if (mips_fix_vr4120) | |
1940 | init_vr4120_conflicts (); | |
252b5132 RH |
1941 | } |
1942 | ||
1943 | void | |
17a2f251 | 1944 | md_mips_end (void) |
252b5132 RH |
1945 | { |
1946 | if (! ECOFF_DEBUGGING) | |
1947 | md_obj_end (); | |
1948 | } | |
1949 | ||
1950 | void | |
17a2f251 | 1951 | md_assemble (char *str) |
252b5132 RH |
1952 | { |
1953 | struct mips_cl_insn insn; | |
f6688943 TS |
1954 | bfd_reloc_code_real_type unused_reloc[3] |
1955 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1956 | |
1957 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1958 | imm2_expr.X_op = O_absent; |
252b5132 | 1959 | offset_expr.X_op = O_absent; |
f6688943 TS |
1960 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1961 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1962 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1963 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1964 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1965 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1966 | |
1967 | if (mips_opts.mips16) | |
1968 | mips16_ip (str, &insn); | |
1969 | else | |
1970 | { | |
1971 | mips_ip (str, &insn); | |
beae10d5 KH |
1972 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1973 | str, insn.insn_opcode)); | |
252b5132 RH |
1974 | } |
1975 | ||
1976 | if (insn_error) | |
1977 | { | |
1978 | as_bad ("%s `%s'", insn_error, str); | |
1979 | return; | |
1980 | } | |
1981 | ||
1982 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1983 | { | |
584892a6 | 1984 | macro_start (); |
252b5132 RH |
1985 | if (mips_opts.mips16) |
1986 | mips16_macro (&insn); | |
1987 | else | |
1988 | macro (&insn); | |
584892a6 | 1989 | macro_end (); |
252b5132 RH |
1990 | } |
1991 | else | |
1992 | { | |
1993 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 1994 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 1995 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 1996 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 1997 | else |
4d7206a2 | 1998 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
1999 | } |
2000 | } | |
2001 | ||
5919d012 | 2002 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2003 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2004 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2005 | |
2006 | static inline bfd_boolean | |
17a2f251 | 2007 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2008 | { |
3b91255e RS |
2009 | return (HAVE_IN_PLACE_ADDENDS |
2010 | && (reloc == BFD_RELOC_HI16_S | |
0a44bf69 RS |
2011 | || reloc == BFD_RELOC_MIPS16_HI16_S |
2012 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); | |
2013 | all GOT16 relocations evaluate to "G". */ | |
2014 | || (reloc == BFD_RELOC_MIPS_GOT16 && mips_pic != VXWORKS_PIC))); | |
5919d012 RS |
2015 | } |
2016 | ||
2017 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2018 | relocation. */ | |
2019 | ||
2020 | static inline bfd_boolean | |
17a2f251 | 2021 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2022 | { |
2023 | return (fixp->fx_next != NULL | |
d6f16593 MR |
2024 | && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16 |
2025 | || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
5919d012 RS |
2026 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2027 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2028 | } | |
2029 | ||
252b5132 RH |
2030 | /* See whether instruction IP reads register REG. CLASS is the type |
2031 | of register. */ | |
2032 | ||
2033 | static int | |
71400594 | 2034 | insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg, |
17a2f251 | 2035 | enum mips_regclass class) |
252b5132 RH |
2036 | { |
2037 | if (class == MIPS16_REG) | |
2038 | { | |
2039 | assert (mips_opts.mips16); | |
2040 | reg = mips16_to_32_reg_map[reg]; | |
2041 | class = MIPS_GR_REG; | |
2042 | } | |
2043 | ||
85b51719 TS |
2044 | /* Don't report on general register ZERO, since it never changes. */ |
2045 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
2046 | return 0; |
2047 | ||
2048 | if (class == MIPS_FP_REG) | |
2049 | { | |
2050 | assert (! mips_opts.mips16); | |
2051 | /* If we are called with either $f0 or $f1, we must check $f0. | |
2052 | This is not optimal, because it will introduce an unnecessary | |
2053 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
2054 | need to distinguish reading both $f0 and $f1 or just one of | |
2055 | them. Note that we don't have to check the other way, | |
2056 | because there is no instruction that sets both $f0 and $f1 | |
2057 | and requires a delay. */ | |
2058 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 2059 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
2060 | == (reg &~ (unsigned) 1))) |
2061 | return 1; | |
2062 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 2063 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
2064 | == (reg &~ (unsigned) 1))) |
2065 | return 1; | |
2066 | } | |
2067 | else if (! mips_opts.mips16) | |
2068 | { | |
2069 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 2070 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
2071 | return 1; |
2072 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 2073 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 RH |
2074 | return 1; |
2075 | } | |
2076 | else | |
2077 | { | |
2078 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 2079 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
2080 | return 1; |
2081 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 2082 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
2083 | return 1; |
2084 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2085 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
2086 | == reg)) |
2087 | return 1; | |
2088 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
2089 | return 1; | |
2090 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
2091 | return 1; | |
2092 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
2093 | return 1; | |
2094 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 2095 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
2096 | return 1; |
2097 | } | |
2098 | ||
2099 | return 0; | |
2100 | } | |
2101 | ||
2102 | /* This function returns true if modifying a register requires a | |
2103 | delay. */ | |
2104 | ||
2105 | static int | |
17a2f251 | 2106 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2107 | { |
2108 | unsigned long prev_pinfo; | |
2109 | ||
47e39b9d | 2110 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2111 | if (! mips_opts.noreorder |
81912461 ILT |
2112 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2113 | && ! gpr_interlocks) | |
2114 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2115 | && ! cop_interlocks))) | |
252b5132 | 2116 | { |
81912461 ILT |
2117 | /* A load from a coprocessor or from memory. All load delays |
2118 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2119 | /* Itbl support may require additional care here. */ |
252b5132 | 2120 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 2121 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
2122 | return 1; |
2123 | } | |
2124 | ||
2125 | return 0; | |
2126 | } | |
2127 | ||
404a8071 RS |
2128 | /* Move all labels in insn_labels to the current insertion point. */ |
2129 | ||
2130 | static void | |
2131 | mips_move_labels (void) | |
2132 | { | |
a8dbcb85 | 2133 | segment_info_type *si = seg_info (now_seg); |
404a8071 RS |
2134 | struct insn_label_list *l; |
2135 | valueT val; | |
2136 | ||
a8dbcb85 | 2137 | for (l = si->label_list; l != NULL; l = l->next) |
404a8071 RS |
2138 | { |
2139 | assert (S_GET_SEGMENT (l->label) == now_seg); | |
2140 | symbol_set_frag (l->label, frag_now); | |
2141 | val = (valueT) frag_now_fix (); | |
2142 | /* mips16 text labels are stored as odd. */ | |
2143 | if (mips_opts.mips16) | |
2144 | ++val; | |
2145 | S_SET_VALUE (l->label, val); | |
2146 | } | |
2147 | } | |
2148 | ||
5f0fe04b TS |
2149 | static bfd_boolean |
2150 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2151 | { | |
2152 | bfd_boolean linkonce = FALSE; | |
2153 | segT symseg = S_GET_SEGMENT (sym); | |
2154 | ||
2155 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2156 | { | |
2157 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2158 | linkonce = TRUE; | |
2159 | #ifdef OBJ_ELF | |
2160 | /* The GNU toolchain uses an extension for ELF: a section | |
2161 | beginning with the magic string .gnu.linkonce is a | |
2162 | linkonce section. */ | |
2163 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2164 | sizeof ".gnu.linkonce" - 1) == 0) | |
2165 | linkonce = TRUE; | |
2166 | #endif | |
2167 | } | |
2168 | return linkonce; | |
2169 | } | |
2170 | ||
252b5132 RH |
2171 | /* Mark instruction labels in mips16 mode. This permits the linker to |
2172 | handle them specially, such as generating jalx instructions when | |
2173 | needed. We also make them odd for the duration of the assembly, in | |
2174 | order to generate the right sort of code. We will make them even | |
2175 | in the adjust_symtab routine, while leaving them marked. This is | |
2176 | convenient for the debugger and the disassembler. The linker knows | |
2177 | to make them odd again. */ | |
2178 | ||
2179 | static void | |
17a2f251 | 2180 | mips16_mark_labels (void) |
252b5132 | 2181 | { |
a8dbcb85 TS |
2182 | segment_info_type *si = seg_info (now_seg); |
2183 | struct insn_label_list *l; | |
252b5132 | 2184 | |
a8dbcb85 TS |
2185 | if (!mips_opts.mips16) |
2186 | return; | |
2187 | ||
2188 | for (l = si->label_list; l != NULL; l = l->next) | |
2189 | { | |
2190 | symbolS *label = l->label; | |
2191 | ||
2192 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
f43abd2b | 2193 | if (IS_ELF) |
a8dbcb85 | 2194 | S_SET_OTHER (label, STO_MIPS16); |
252b5132 | 2195 | #endif |
5f0fe04b TS |
2196 | if ((S_GET_VALUE (label) & 1) == 0 |
2197 | /* Don't adjust the address if the label is global or weak, or | |
2198 | in a link-once section, since we'll be emitting symbol reloc | |
2199 | references to it which will be patched up by the linker, and | |
2200 | the final value of the symbol may or may not be MIPS16. */ | |
2201 | && ! S_IS_WEAK (label) | |
2202 | && ! S_IS_EXTERNAL (label) | |
2203 | && ! s_is_linkonce (label, now_seg)) | |
a8dbcb85 | 2204 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); |
252b5132 RH |
2205 | } |
2206 | } | |
2207 | ||
4d7206a2 RS |
2208 | /* End the current frag. Make it a variant frag and record the |
2209 | relaxation info. */ | |
2210 | ||
2211 | static void | |
2212 | relax_close_frag (void) | |
2213 | { | |
584892a6 | 2214 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2215 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2216 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2217 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2218 | ||
2219 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2220 | mips_relax.first_fixup = 0; | |
2221 | } | |
2222 | ||
2223 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2224 | See the comment above RELAX_ENCODE for more details. */ | |
2225 | ||
2226 | static void | |
2227 | relax_start (symbolS *symbol) | |
2228 | { | |
2229 | assert (mips_relax.sequence == 0); | |
2230 | mips_relax.sequence = 1; | |
2231 | mips_relax.symbol = symbol; | |
2232 | } | |
2233 | ||
2234 | /* Start generating the second version of a relaxable sequence. | |
2235 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2236 | |
2237 | static void | |
4d7206a2 RS |
2238 | relax_switch (void) |
2239 | { | |
2240 | assert (mips_relax.sequence == 1); | |
2241 | mips_relax.sequence = 2; | |
2242 | } | |
2243 | ||
2244 | /* End the current relaxable sequence. */ | |
2245 | ||
2246 | static void | |
2247 | relax_end (void) | |
2248 | { | |
2249 | assert (mips_relax.sequence == 2); | |
2250 | relax_close_frag (); | |
2251 | mips_relax.sequence = 0; | |
2252 | } | |
2253 | ||
71400594 RS |
2254 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
2255 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
2256 | by VR4120 errata. */ | |
4d7206a2 | 2257 | |
71400594 RS |
2258 | static unsigned int |
2259 | classify_vr4120_insn (const char *name) | |
252b5132 | 2260 | { |
71400594 RS |
2261 | if (strncmp (name, "macc", 4) == 0) |
2262 | return FIX_VR4120_MACC; | |
2263 | if (strncmp (name, "dmacc", 5) == 0) | |
2264 | return FIX_VR4120_DMACC; | |
2265 | if (strncmp (name, "mult", 4) == 0) | |
2266 | return FIX_VR4120_MULT; | |
2267 | if (strncmp (name, "dmult", 5) == 0) | |
2268 | return FIX_VR4120_DMULT; | |
2269 | if (strstr (name, "div")) | |
2270 | return FIX_VR4120_DIV; | |
2271 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
2272 | return FIX_VR4120_MTHILO; | |
2273 | return NUM_FIX_VR4120_CLASSES; | |
2274 | } | |
252b5132 | 2275 | |
71400594 RS |
2276 | /* Return the number of instructions that must separate INSN1 and INSN2, |
2277 | where INSN1 is the earlier instruction. Return the worst-case value | |
2278 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 2279 | |
71400594 RS |
2280 | static unsigned int |
2281 | insns_between (const struct mips_cl_insn *insn1, | |
2282 | const struct mips_cl_insn *insn2) | |
2283 | { | |
2284 | unsigned long pinfo1, pinfo2; | |
2285 | ||
2286 | /* This function needs to know which pinfo flags are set for INSN2 | |
2287 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
2288 | the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2 | |
2289 | will have every flag set and INSN2_USES_REG will always return true. */ | |
2290 | pinfo1 = insn1->insn_mo->pinfo; | |
2291 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 2292 | |
71400594 RS |
2293 | #define INSN2_USES_REG(REG, CLASS) \ |
2294 | (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS)) | |
2295 | ||
2296 | /* For most targets, write-after-read dependencies on the HI and LO | |
2297 | registers must be separated by at least two instructions. */ | |
2298 | if (!hilo_interlocks) | |
252b5132 | 2299 | { |
71400594 RS |
2300 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
2301 | return 2; | |
2302 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
2303 | return 2; | |
2304 | } | |
2305 | ||
2306 | /* If we're working around r7000 errata, there must be two instructions | |
2307 | between an mfhi or mflo and any instruction that uses the result. */ | |
2308 | if (mips_7000_hilo_fix | |
2309 | && MF_HILO_INSN (pinfo1) | |
2310 | && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG)) | |
2311 | return 2; | |
2312 | ||
2313 | /* If working around VR4120 errata, check for combinations that need | |
2314 | a single intervening instruction. */ | |
2315 | if (mips_fix_vr4120) | |
2316 | { | |
2317 | unsigned int class1, class2; | |
252b5132 | 2318 | |
71400594 RS |
2319 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
2320 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 2321 | { |
71400594 RS |
2322 | if (insn2 == NULL) |
2323 | return 1; | |
2324 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
2325 | if (vr4120_conflicts[class1] & (1 << class2)) | |
2326 | return 1; | |
252b5132 | 2327 | } |
71400594 RS |
2328 | } |
2329 | ||
2330 | if (!mips_opts.mips16) | |
2331 | { | |
2332 | /* Check for GPR or coprocessor load delays. All such delays | |
2333 | are on the RT register. */ | |
2334 | /* Itbl support may require additional care here. */ | |
2335 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
2336 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 2337 | { |
71400594 RS |
2338 | know (pinfo1 & INSN_WRITE_GPR_T); |
2339 | if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG)) | |
2340 | return 1; | |
2341 | } | |
2342 | ||
2343 | /* Check for generic coprocessor hazards. | |
2344 | ||
2345 | This case is not handled very well. There is no special | |
2346 | knowledge of CP0 handling, and the coprocessors other than | |
2347 | the floating point unit are not distinguished at all. */ | |
2348 | /* Itbl support may require additional care here. FIXME! | |
2349 | Need to modify this to include knowledge about | |
2350 | user specified delays! */ | |
2351 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
2352 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
2353 | { | |
2354 | /* Handle cases where INSN1 writes to a known general coprocessor | |
2355 | register. There must be a one instruction delay before INSN2 | |
2356 | if INSN2 reads that register, otherwise no delay is needed. */ | |
2357 | if (pinfo1 & INSN_WRITE_FPR_T) | |
252b5132 | 2358 | { |
71400594 RS |
2359 | if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG)) |
2360 | return 1; | |
252b5132 | 2361 | } |
71400594 | 2362 | else if (pinfo1 & INSN_WRITE_FPR_S) |
252b5132 | 2363 | { |
71400594 RS |
2364 | if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG)) |
2365 | return 1; | |
252b5132 RH |
2366 | } |
2367 | else | |
2368 | { | |
71400594 RS |
2369 | /* Read-after-write dependencies on the control registers |
2370 | require a two-instruction gap. */ | |
2371 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
2372 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2373 | return 2; | |
2374 | ||
2375 | /* We don't know exactly what INSN1 does. If INSN2 is | |
2376 | also a coprocessor instruction, assume there must be | |
2377 | a one instruction gap. */ | |
2378 | if (pinfo2 & INSN_COP) | |
2379 | return 1; | |
252b5132 RH |
2380 | } |
2381 | } | |
6b76fefe | 2382 | |
71400594 RS |
2383 | /* Check for read-after-write dependencies on the coprocessor |
2384 | control registers in cases where INSN1 does not need a general | |
2385 | coprocessor delay. This means that INSN1 is a floating point | |
2386 | comparison instruction. */ | |
2387 | /* Itbl support may require additional care here. */ | |
2388 | else if (!cop_interlocks | |
2389 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2390 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2391 | return 1; | |
2392 | } | |
6b76fefe | 2393 | |
71400594 | 2394 | #undef INSN2_USES_REG |
6b76fefe | 2395 | |
71400594 RS |
2396 | return 0; |
2397 | } | |
6b76fefe | 2398 | |
7d8e00cf RS |
2399 | /* Return the number of nops that would be needed to work around the |
2400 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
2401 | the MAX_VR4130_NOPS instructions described by HISTORY. */ | |
2402 | ||
2403 | static int | |
2404 | nops_for_vr4130 (const struct mips_cl_insn *history, | |
2405 | const struct mips_cl_insn *insn) | |
2406 | { | |
2407 | int i, j, reg; | |
2408 | ||
2409 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2410 | are not affected by the errata. */ | |
2411 | if (insn != 0 | |
2412 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2413 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2414 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2415 | return 0; | |
2416 | ||
2417 | /* Search for the first MFLO or MFHI. */ | |
2418 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
2419 | if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo)) | |
2420 | { | |
2421 | /* Extract the destination register. */ | |
2422 | if (mips_opts.mips16) | |
2423 | reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])]; | |
2424 | else | |
2425 | reg = EXTRACT_OPERAND (RD, history[i]); | |
2426 | ||
2427 | /* No nops are needed if INSN reads that register. */ | |
2428 | if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG)) | |
2429 | return 0; | |
2430 | ||
2431 | /* ...or if any of the intervening instructions do. */ | |
2432 | for (j = 0; j < i; j++) | |
2433 | if (insn_uses_reg (&history[j], reg, MIPS_GR_REG)) | |
2434 | return 0; | |
2435 | ||
2436 | return MAX_VR4130_NOPS - i; | |
2437 | } | |
2438 | return 0; | |
2439 | } | |
2440 | ||
71400594 RS |
2441 | /* Return the number of nops that would be needed if instruction INSN |
2442 | immediately followed the MAX_NOPS instructions given by HISTORY, | |
2443 | where HISTORY[0] is the most recent instruction. If INSN is null, | |
2444 | return the worse-case number of nops for any instruction. */ | |
bdaaa2e1 | 2445 | |
71400594 RS |
2446 | static int |
2447 | nops_for_insn (const struct mips_cl_insn *history, | |
2448 | const struct mips_cl_insn *insn) | |
2449 | { | |
2450 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2451 | |
71400594 | 2452 | nops = 0; |
7d8e00cf | 2453 | for (i = 0; i < MAX_DELAY_NOPS; i++) |
71400594 RS |
2454 | if (!history[i].noreorder_p) |
2455 | { | |
2456 | tmp_nops = insns_between (history + i, insn) - i; | |
2457 | if (tmp_nops > nops) | |
2458 | nops = tmp_nops; | |
2459 | } | |
7d8e00cf RS |
2460 | |
2461 | if (mips_fix_vr4130) | |
2462 | { | |
2463 | tmp_nops = nops_for_vr4130 (history, insn); | |
2464 | if (tmp_nops > nops) | |
2465 | nops = tmp_nops; | |
2466 | } | |
2467 | ||
71400594 RS |
2468 | return nops; |
2469 | } | |
252b5132 | 2470 | |
71400594 RS |
2471 | /* The variable arguments provide NUM_INSNS extra instructions that |
2472 | might be added to HISTORY. Return the largest number of nops that | |
2473 | would be needed after the extended sequence. */ | |
252b5132 | 2474 | |
71400594 RS |
2475 | static int |
2476 | nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...) | |
2477 | { | |
2478 | va_list args; | |
2479 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2480 | struct mips_cl_insn *cursor; | |
2481 | int nops; | |
2482 | ||
2483 | va_start (args, history); | |
2484 | cursor = buffer + num_insns; | |
2485 | memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor)); | |
2486 | while (cursor > buffer) | |
2487 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2488 | ||
2489 | nops = nops_for_insn (buffer, NULL); | |
2490 | va_end (args); | |
2491 | return nops; | |
2492 | } | |
252b5132 | 2493 | |
71400594 RS |
2494 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2495 | worst-case delay for the branch target. */ | |
252b5132 | 2496 | |
71400594 RS |
2497 | static int |
2498 | nops_for_insn_or_target (const struct mips_cl_insn *history, | |
2499 | const struct mips_cl_insn *insn) | |
2500 | { | |
2501 | int nops, tmp_nops; | |
60b63b72 | 2502 | |
71400594 RS |
2503 | nops = nops_for_insn (history, insn); |
2504 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2505 | | INSN_COND_BRANCH_DELAY | |
2506 | | INSN_COND_BRANCH_LIKELY)) | |
2507 | { | |
2508 | tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN); | |
2509 | if (tmp_nops > nops) | |
2510 | nops = tmp_nops; | |
2511 | } | |
2512 | else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH)) | |
2513 | { | |
2514 | tmp_nops = nops_for_sequence (1, history, insn); | |
2515 | if (tmp_nops > nops) | |
2516 | nops = tmp_nops; | |
2517 | } | |
2518 | return nops; | |
2519 | } | |
2520 | ||
2521 | /* Output an instruction. IP is the instruction information. | |
2522 | ADDRESS_EXPR is an operand of the instruction to be used with | |
2523 | RELOC_TYPE. */ | |
2524 | ||
2525 | static void | |
2526 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
2527 | bfd_reloc_code_real_type *reloc_type) | |
2528 | { | |
3994f87e | 2529 | unsigned long prev_pinfo, pinfo; |
71400594 RS |
2530 | relax_stateT prev_insn_frag_type = 0; |
2531 | bfd_boolean relaxed_branch = FALSE; | |
a8dbcb85 | 2532 | segment_info_type *si = seg_info (now_seg); |
71400594 RS |
2533 | |
2534 | /* Mark instruction labels in mips16 mode. */ | |
2535 | mips16_mark_labels (); | |
2536 | ||
2537 | prev_pinfo = history[0].insn_mo->pinfo; | |
2538 | pinfo = ip->insn_mo->pinfo; | |
2539 | ||
2540 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) | |
2541 | { | |
2542 | /* There are a lot of optimizations we could do that we don't. | |
2543 | In particular, we do not, in general, reorder instructions. | |
2544 | If you use gcc with optimization, it will reorder | |
2545 | instructions and generally do much more optimization then we | |
2546 | do here; repeating all that work in the assembler would only | |
2547 | benefit hand written assembly code, and does not seem worth | |
2548 | it. */ | |
2549 | int nops = (mips_optimize == 0 | |
2550 | ? nops_for_insn (history, NULL) | |
2551 | : nops_for_insn_or_target (history, ip)); | |
2552 | if (nops > 0) | |
252b5132 RH |
2553 | { |
2554 | fragS *old_frag; | |
2555 | unsigned long old_frag_offset; | |
2556 | int i; | |
252b5132 RH |
2557 | |
2558 | old_frag = frag_now; | |
2559 | old_frag_offset = frag_now_fix (); | |
2560 | ||
2561 | for (i = 0; i < nops; i++) | |
2562 | emit_nop (); | |
2563 | ||
2564 | if (listing) | |
2565 | { | |
2566 | listing_prev_line (); | |
2567 | /* We may be at the start of a variant frag. In case we | |
2568 | are, make sure there is enough space for the frag | |
2569 | after the frags created by listing_prev_line. The | |
2570 | argument to frag_grow here must be at least as large | |
2571 | as the argument to all other calls to frag_grow in | |
2572 | this file. We don't have to worry about being in the | |
2573 | middle of a variant frag, because the variants insert | |
2574 | all needed nop instructions themselves. */ | |
2575 | frag_grow (40); | |
2576 | } | |
2577 | ||
404a8071 | 2578 | mips_move_labels (); |
252b5132 RH |
2579 | |
2580 | #ifndef NO_ECOFF_DEBUGGING | |
2581 | if (ECOFF_DEBUGGING) | |
2582 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2583 | #endif | |
2584 | } | |
71400594 RS |
2585 | } |
2586 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
2587 | { | |
2588 | /* Work out how many nops in prev_nop_frag are needed by IP. */ | |
2589 | int nops = nops_for_insn_or_target (history, ip); | |
2590 | assert (nops <= prev_nop_frag_holds); | |
252b5132 | 2591 | |
71400594 RS |
2592 | /* Enforce NOPS as a minimum. */ |
2593 | if (nops > prev_nop_frag_required) | |
2594 | prev_nop_frag_required = nops; | |
252b5132 | 2595 | |
71400594 RS |
2596 | if (prev_nop_frag_holds == prev_nop_frag_required) |
2597 | { | |
2598 | /* Settle for the current number of nops. Update the history | |
2599 | accordingly (for the benefit of any future .set reorder code). */ | |
2600 | prev_nop_frag = NULL; | |
2601 | insert_into_history (prev_nop_frag_since, | |
2602 | prev_nop_frag_holds, NOP_INSN); | |
2603 | } | |
2604 | else | |
2605 | { | |
2606 | /* Allow this instruction to replace one of the nops that was | |
2607 | tentatively added to prev_nop_frag. */ | |
2608 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2609 | prev_nop_frag_holds--; | |
2610 | prev_nop_frag_since++; | |
252b5132 RH |
2611 | } |
2612 | } | |
2613 | ||
58e2ea4d MR |
2614 | #ifdef OBJ_ELF |
2615 | /* The value passed to dwarf2_emit_insn is the distance between | |
2616 | the beginning of the current instruction and the address that | |
2617 | should be recorded in the debug tables. For MIPS16 debug info | |
2618 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2619 | address higher by one than the current. */ | |
2620 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2621 | #endif | |
2622 | ||
895921c9 | 2623 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2624 | if (history[0].frag) |
2625 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2626 | |
4d7206a2 | 2627 | if (address_expr |
0b25d3e6 | 2628 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2629 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2630 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2631 | && mips_relax_branch | |
2632 | /* Don't try branch relaxation within .set nomacro, or within | |
2633 | .set noat if we use $at for PIC computations. If it turns | |
2634 | out that the branch was out-of-range, we'll get an error. */ | |
2635 | && !mips_opts.warn_about_macros | |
2636 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2637 | && !mips_opts.mips16) | |
2638 | { | |
895921c9 | 2639 | relaxed_branch = TRUE; |
1e915849 RS |
2640 | add_relaxed_insn (ip, (relaxed_branch_length |
2641 | (NULL, NULL, | |
2642 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2643 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
2644 | : 0)), 4, | |
2645 | RELAX_BRANCH_ENCODE | |
2646 | (pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2647 | pinfo & INSN_COND_BRANCH_LIKELY, | |
2648 | pinfo & INSN_WRITE_GPR_31, | |
2649 | 0), | |
2650 | address_expr->X_add_symbol, | |
2651 | address_expr->X_add_number); | |
4a6a3df4 AO |
2652 | *reloc_type = BFD_RELOC_UNUSED; |
2653 | } | |
2654 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2655 | { |
2656 | /* We need to set up a variant frag. */ | |
2657 | assert (mips_opts.mips16 && address_expr != NULL); | |
1e915849 RS |
2658 | add_relaxed_insn (ip, 4, 0, |
2659 | RELAX_MIPS16_ENCODE | |
2660 | (*reloc_type - BFD_RELOC_UNUSED, | |
2661 | mips16_small, mips16_ext, | |
2662 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2663 | history[0].mips16_absolute_jump_p), | |
2664 | make_expr_symbol (address_expr), 0); | |
252b5132 | 2665 | } |
252b5132 RH |
2666 | else if (mips_opts.mips16 |
2667 | && ! ip->use_extend | |
f6688943 | 2668 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 2669 | { |
b8ee1a6e DU |
2670 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0) |
2671 | /* Make sure there is enough room to swap this instruction with | |
2672 | a following jump instruction. */ | |
2673 | frag_grow (6); | |
1e915849 | 2674 | add_fixed_insn (ip); |
252b5132 RH |
2675 | } |
2676 | else | |
2677 | { | |
2678 | if (mips_opts.mips16 | |
2679 | && mips_opts.noreorder | |
2680 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2681 | as_warn (_("extended instruction in delay slot")); | |
2682 | ||
4d7206a2 RS |
2683 | if (mips_relax.sequence) |
2684 | { | |
2685 | /* If we've reached the end of this frag, turn it into a variant | |
2686 | frag and record the information for the instructions we've | |
2687 | written so far. */ | |
2688 | if (frag_room () < 4) | |
2689 | relax_close_frag (); | |
2690 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2691 | } | |
2692 | ||
584892a6 RS |
2693 | if (mips_relax.sequence != 2) |
2694 | mips_macro_warning.sizes[0] += 4; | |
2695 | if (mips_relax.sequence != 1) | |
2696 | mips_macro_warning.sizes[1] += 4; | |
2697 | ||
1e915849 RS |
2698 | if (mips_opts.mips16) |
2699 | { | |
2700 | ip->fixed_p = 1; | |
2701 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
2702 | } | |
2703 | add_fixed_insn (ip); | |
252b5132 RH |
2704 | } |
2705 | ||
01a3f561 | 2706 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2707 | { |
2708 | if (address_expr->X_op == O_constant) | |
2709 | { | |
f17c130b | 2710 | unsigned int tmp; |
f6688943 TS |
2711 | |
2712 | switch (*reloc_type) | |
252b5132 RH |
2713 | { |
2714 | case BFD_RELOC_32: | |
2715 | ip->insn_opcode |= address_expr->X_add_number; | |
2716 | break; | |
2717 | ||
f6688943 | 2718 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2719 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2720 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2721 | break; |
2722 | ||
2723 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
2724 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
2725 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2726 | break; |
2727 | ||
2728 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
2729 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
2730 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2731 | break; |
2732 | ||
2733 | case BFD_RELOC_HI16: | |
2734 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2735 | break; | |
2736 | ||
01a3f561 | 2737 | case BFD_RELOC_UNUSED: |
252b5132 | 2738 | case BFD_RELOC_LO16: |
ed6fb7bd | 2739 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2740 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2741 | break; | |
2742 | ||
2743 | case BFD_RELOC_MIPS_JMP: | |
2744 | if ((address_expr->X_add_number & 3) != 0) | |
2745 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2746 | (unsigned long) address_expr->X_add_number); | |
2747 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
2748 | break; | |
2749 | ||
2750 | case BFD_RELOC_MIPS16_JMP: | |
2751 | if ((address_expr->X_add_number & 3) != 0) | |
2752 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2753 | (unsigned long) address_expr->X_add_number); | |
2754 | ip->insn_opcode |= | |
2755 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2756 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2757 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2758 | break; | |
2759 | ||
252b5132 | 2760 | case BFD_RELOC_16_PCREL_S2: |
bad36eac DJ |
2761 | if ((address_expr->X_add_number & 3) != 0) |
2762 | as_bad (_("branch to misaligned address (0x%lx)"), | |
2763 | (unsigned long) address_expr->X_add_number); | |
2764 | if (mips_relax_branch) | |
2765 | goto need_reloc; | |
2766 | if ((address_expr->X_add_number + 0x20000) & ~0x3ffff) | |
2767 | as_bad (_("branch address range overflow (0x%lx)"), | |
2768 | (unsigned long) address_expr->X_add_number); | |
2769 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff; | |
2770 | break; | |
252b5132 RH |
2771 | |
2772 | default: | |
2773 | internalError (); | |
2774 | } | |
2775 | } | |
01a3f561 | 2776 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 2777 | need_reloc: |
4d7206a2 RS |
2778 | { |
2779 | reloc_howto_type *howto; | |
2780 | int i; | |
34ce925e | 2781 | |
4d7206a2 RS |
2782 | /* In a compound relocation, it is the final (outermost) |
2783 | operator that determines the relocated field. */ | |
2784 | for (i = 1; i < 3; i++) | |
2785 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2786 | break; | |
34ce925e | 2787 | |
4d7206a2 | 2788 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
1e915849 RS |
2789 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
2790 | bfd_get_reloc_size (howto), | |
2791 | address_expr, | |
2792 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2793 | reloc_type[0]); | |
4d7206a2 RS |
2794 | |
2795 | /* These relocations can have an addend that won't fit in | |
2796 | 4 octets for 64bit assembly. */ | |
2797 | if (HAVE_64BIT_GPRS | |
2798 | && ! howto->partial_inplace | |
2799 | && (reloc_type[0] == BFD_RELOC_16 | |
2800 | || reloc_type[0] == BFD_RELOC_32 | |
2801 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2802 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2803 | || reloc_type[0] == BFD_RELOC_LO16 | |
2804 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2805 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2806 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2807 | || reloc_type[0] == BFD_RELOC_64 | |
2808 | || reloc_type[0] == BFD_RELOC_CTOR | |
2809 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2810 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2811 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2812 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2813 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
2814 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
2815 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
2816 | || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S | |
2817 | || reloc_type[0] == BFD_RELOC_MIPS16_LO16)) | |
1e915849 | 2818 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
2819 | |
2820 | if (mips_relax.sequence) | |
2821 | { | |
2822 | if (mips_relax.first_fixup == 0) | |
1e915849 | 2823 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
2824 | } |
2825 | else if (reloc_needs_lo_p (*reloc_type)) | |
2826 | { | |
2827 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2828 | |
4d7206a2 RS |
2829 | /* Reuse the last entry if it already has a matching %lo. */ |
2830 | hi_fixup = mips_hi_fixup_list; | |
2831 | if (hi_fixup == 0 | |
2832 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2833 | { | |
2834 | hi_fixup = ((struct mips_hi_fixup *) | |
2835 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2836 | hi_fixup->next = mips_hi_fixup_list; | |
2837 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2838 | } |
1e915849 | 2839 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
2840 | hi_fixup->seg = now_seg; |
2841 | } | |
f6688943 | 2842 | |
4d7206a2 RS |
2843 | /* Add fixups for the second and third relocations, if given. |
2844 | Note that the ABI allows the second relocation to be | |
2845 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2846 | moment we only use RSS_UNDEF, but we could add support | |
2847 | for the others if it ever becomes necessary. */ | |
2848 | for (i = 1; i < 3; i++) | |
2849 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2850 | { | |
1e915849 RS |
2851 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
2852 | ip->fixp[0]->fx_size, NULL, 0, | |
2853 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
2854 | |
2855 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
2856 | ip->fixp[0]->fx_tcbit = 1; |
2857 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 2858 | } |
252b5132 RH |
2859 | } |
2860 | } | |
1e915849 | 2861 | install_insn (ip); |
252b5132 RH |
2862 | |
2863 | /* Update the register mask information. */ | |
2864 | if (! mips_opts.mips16) | |
2865 | { | |
2866 | if (pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2867 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 2868 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 2869 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 2870 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 2871 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 2872 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 2873 | mips_gprmask |= 1 << RA; |
252b5132 | 2874 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 2875 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 2876 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 2877 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 2878 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 2879 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 2880 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 2881 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
252b5132 RH |
2882 | if (pinfo & INSN_COP) |
2883 | { | |
bdaaa2e1 KH |
2884 | /* We don't keep enough information to sort these cases out. |
2885 | The itbl support does keep this information however, although | |
2886 | we currently don't support itbl fprmats as part of the cop | |
2887 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2888 | } |
2889 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2890 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2891 | } |
2892 | else | |
2893 | { | |
2894 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 2895 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 2896 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 2897 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 2898 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 2899 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
2900 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
2901 | mips_gprmask |= 1 << TREG; | |
2902 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2903 | mips_gprmask |= 1 << SP; | |
2904 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2905 | mips_gprmask |= 1 << RA; | |
2906 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2907 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2908 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2909 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 2910 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 2911 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
2912 | } |
2913 | ||
4d7206a2 | 2914 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2915 | { |
2916 | /* Filling the branch delay slot is more complex. We try to | |
2917 | switch the branch with the previous instruction, which we can | |
2918 | do if the previous instruction does not set up a condition | |
2919 | that the branch tests and if the branch is not itself the | |
2920 | target of any branch. */ | |
2921 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2922 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2923 | { | |
2924 | if (mips_optimize < 2 | |
2925 | /* If we have seen .set volatile or .set nomove, don't | |
2926 | optimize. */ | |
2927 | || mips_opts.nomove != 0 | |
a38419a5 RS |
2928 | /* We can't swap if the previous instruction's position |
2929 | is fixed. */ | |
2930 | || history[0].fixed_p | |
252b5132 RH |
2931 | /* If the previous previous insn was in a .set |
2932 | noreorder, we can't swap. Actually, the MIPS | |
2933 | assembler will swap in this situation. However, gcc | |
2934 | configured -with-gnu-as will generate code like | |
2935 | .set noreorder | |
2936 | lw $4,XXX | |
2937 | .set reorder | |
2938 | INSN | |
2939 | bne $4,$0,foo | |
2940 | in which we can not swap the bne and INSN. If gcc is | |
2941 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 2942 | .set pseudo-ops. */ |
47e39b9d | 2943 | || history[1].noreorder_p |
252b5132 RH |
2944 | /* If the branch is itself the target of a branch, we |
2945 | can not swap. We cheat on this; all we check for is | |
2946 | whether there is a label on this instruction. If | |
2947 | there are any branches to anything other than a | |
2948 | label, users must use .set noreorder. */ | |
a8dbcb85 | 2949 | || si->label_list != NULL |
895921c9 MR |
2950 | /* If the previous instruction is in a variant frag |
2951 | other than this branch's one, we cannot do the swap. | |
2952 | This does not apply to the mips16, which uses variant | |
2953 | frags for different purposes. */ | |
252b5132 | 2954 | || (! mips_opts.mips16 |
895921c9 | 2955 | && prev_insn_frag_type == rs_machine_dependent) |
71400594 RS |
2956 | /* Check for conflicts between the branch and the instructions |
2957 | before the candidate delay slot. */ | |
2958 | || nops_for_insn (history + 1, ip) > 0 | |
2959 | /* Check for conflicts between the swapped sequence and the | |
2960 | target of the branch. */ | |
2961 | || nops_for_sequence (2, history + 1, ip, history) > 0 | |
252b5132 RH |
2962 | /* We do not swap with a trap instruction, since it |
2963 | complicates trap handlers to have the trap | |
2964 | instruction be in a delay slot. */ | |
2965 | || (prev_pinfo & INSN_TRAP) | |
2966 | /* If the branch reads a register that the previous | |
2967 | instruction sets, we can not swap. */ | |
2968 | || (! mips_opts.mips16 | |
2969 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 2970 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
2971 | MIPS_GR_REG)) |
2972 | || (! mips_opts.mips16 | |
2973 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2974 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 RH |
2975 | MIPS_GR_REG)) |
2976 | || (mips_opts.mips16 | |
2977 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
2978 | && (insn_uses_reg |
2979 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
2980 | MIPS16_REG))) | |
252b5132 | 2981 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
2982 | && (insn_uses_reg |
2983 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
2984 | MIPS16_REG))) | |
252b5132 | 2985 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
2986 | && (insn_uses_reg |
2987 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
2988 | MIPS16_REG))) | |
252b5132 RH |
2989 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
2990 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2991 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2992 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2993 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2994 | && insn_uses_reg (ip, | |
47e39b9d RS |
2995 | MIPS16OP_EXTRACT_REG32R |
2996 | (history[0].insn_opcode), | |
252b5132 RH |
2997 | MIPS_GR_REG)))) |
2998 | /* If the branch writes a register that the previous | |
2999 | instruction sets, we can not swap (we know that | |
3000 | branches write only to RD or to $31). */ | |
3001 | || (! mips_opts.mips16 | |
3002 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
3003 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3004 | && (EXTRACT_OPERAND (RT, history[0]) |
3005 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3006 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3007 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
3008 | || (! mips_opts.mips16 |
3009 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
3010 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3011 | && (EXTRACT_OPERAND (RD, history[0]) |
3012 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3013 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3014 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
3015 | || (mips_opts.mips16 |
3016 | && (pinfo & MIPS16_INSN_WRITE_31) | |
3017 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
3018 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 3019 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
3020 | == RA)))) |
3021 | /* If the branch writes a register that the previous | |
3022 | instruction reads, we can not swap (we know that | |
3023 | branches only write to RD or to $31). */ | |
3024 | || (! mips_opts.mips16 | |
3025 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 3026 | && insn_uses_reg (&history[0], |
bf12938e | 3027 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
3028 | MIPS_GR_REG)) |
3029 | || (! mips_opts.mips16 | |
3030 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 3031 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3032 | || (mips_opts.mips16 |
3033 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 3034 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3035 | /* If one instruction sets a condition code and the |
3036 | other one uses a condition code, we can not swap. */ | |
3037 | || ((pinfo & INSN_READ_COND_CODE) | |
3038 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3039 | || ((pinfo & INSN_WRITE_COND_CODE) | |
3040 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3041 | /* If the previous instruction uses the PC, we can not | |
3042 | swap. */ | |
3043 | || (mips_opts.mips16 | |
3044 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
3045 | /* If the previous instruction had a fixup in mips16 |
3046 | mode, we can not swap. This normally means that the | |
3047 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 3048 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
3049 | /* If the previous instruction is a sync, sync.l, or |
3050 | sync.p, we can not swap. */ | |
f173e82e | 3051 | || (prev_pinfo & INSN_SYNC)) |
252b5132 | 3052 | { |
29024861 DU |
3053 | if (mips_opts.mips16 |
3054 | && (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3055 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)) | |
3994f87e | 3056 | && ISA_SUPPORTS_MIPS16E) |
29024861 DU |
3057 | { |
3058 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
3059 | ip->insn_opcode |= 0x0080; | |
3060 | install_insn (ip); | |
3061 | insert_into_history (0, 1, ip); | |
3062 | } | |
3063 | else | |
3064 | { | |
3065 | /* We could do even better for unconditional branches to | |
3066 | portions of this object file; we could pick up the | |
3067 | instruction at the destination, put it in the delay | |
3068 | slot, and bump the destination address. */ | |
3069 | insert_into_history (0, 1, ip); | |
3070 | emit_nop (); | |
3071 | } | |
3072 | ||
dd22970f ILT |
3073 | if (mips_relax.sequence) |
3074 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
3075 | } |
3076 | else | |
3077 | { | |
3078 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
3079 | struct mips_cl_insn delay = history[0]; |
3080 | if (mips_opts.mips16) | |
252b5132 | 3081 | { |
b8ee1a6e DU |
3082 | know (delay.frag == ip->frag); |
3083 | move_insn (ip, delay.frag, delay.where); | |
3084 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
1e915849 RS |
3085 | } |
3086 | else if (relaxed_branch) | |
3087 | { | |
3088 | /* Add the delay slot instruction to the end of the | |
3089 | current frag and shrink the fixed part of the | |
3090 | original frag. If the branch occupies the tail of | |
3091 | the latter, move it backwards to cover the gap. */ | |
3092 | delay.frag->fr_fix -= 4; | |
3093 | if (delay.frag == ip->frag) | |
3094 | move_insn (ip, ip->frag, ip->where - 4); | |
3095 | add_fixed_insn (&delay); | |
252b5132 RH |
3096 | } |
3097 | else | |
3098 | { | |
1e915849 RS |
3099 | move_insn (&delay, ip->frag, ip->where); |
3100 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 3101 | } |
1e915849 RS |
3102 | history[0] = *ip; |
3103 | delay.fixed_p = 1; | |
3104 | insert_into_history (0, 1, &delay); | |
252b5132 | 3105 | } |
252b5132 RH |
3106 | |
3107 | /* If that was an unconditional branch, forget the previous | |
3108 | insn information. */ | |
3109 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
7d10b47d | 3110 | mips_no_prev_insn (); |
252b5132 RH |
3111 | } |
3112 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
3113 | { | |
3114 | /* We don't yet optimize a branch likely. What we should do | |
3115 | is look at the target, copy the instruction found there | |
3116 | into the delay slot, and increment the branch to jump to | |
3117 | the next instruction. */ | |
1e915849 | 3118 | insert_into_history (0, 1, ip); |
252b5132 | 3119 | emit_nop (); |
252b5132 RH |
3120 | } |
3121 | else | |
1e915849 | 3122 | insert_into_history (0, 1, ip); |
252b5132 | 3123 | } |
1e915849 RS |
3124 | else |
3125 | insert_into_history (0, 1, ip); | |
252b5132 RH |
3126 | |
3127 | /* We just output an insn, so the next one doesn't have a label. */ | |
3128 | mips_clear_insn_labels (); | |
252b5132 RH |
3129 | } |
3130 | ||
7d10b47d | 3131 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
3132 | |
3133 | static void | |
7d10b47d | 3134 | mips_no_prev_insn (void) |
252b5132 | 3135 | { |
7d10b47d RS |
3136 | prev_nop_frag = NULL; |
3137 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
3138 | mips_clear_insn_labels (); |
3139 | } | |
3140 | ||
7d10b47d RS |
3141 | /* This function must be called before we emit something other than |
3142 | instructions. It is like mips_no_prev_insn except that it inserts | |
3143 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 3144 | |
7d10b47d RS |
3145 | void |
3146 | mips_emit_delays (void) | |
252b5132 RH |
3147 | { |
3148 | if (! mips_opts.noreorder) | |
3149 | { | |
71400594 | 3150 | int nops = nops_for_insn (history, NULL); |
252b5132 RH |
3151 | if (nops > 0) |
3152 | { | |
7d10b47d RS |
3153 | while (nops-- > 0) |
3154 | add_fixed_insn (NOP_INSN); | |
3155 | mips_move_labels (); | |
3156 | } | |
3157 | } | |
3158 | mips_no_prev_insn (); | |
3159 | } | |
3160 | ||
3161 | /* Start a (possibly nested) noreorder block. */ | |
3162 | ||
3163 | static void | |
3164 | start_noreorder (void) | |
3165 | { | |
3166 | if (mips_opts.noreorder == 0) | |
3167 | { | |
3168 | unsigned int i; | |
3169 | int nops; | |
3170 | ||
3171 | /* None of the instructions before the .set noreorder can be moved. */ | |
3172 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
3173 | history[i].fixed_p = 1; | |
3174 | ||
3175 | /* Insert any nops that might be needed between the .set noreorder | |
3176 | block and the previous instructions. We will later remove any | |
3177 | nops that turn out not to be needed. */ | |
3178 | nops = nops_for_insn (history, NULL); | |
3179 | if (nops > 0) | |
3180 | { | |
3181 | if (mips_optimize != 0) | |
252b5132 RH |
3182 | { |
3183 | /* Record the frag which holds the nop instructions, so | |
3184 | that we can remove them if we don't need them. */ | |
3185 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
3186 | prev_nop_frag = frag_now; | |
3187 | prev_nop_frag_holds = nops; | |
3188 | prev_nop_frag_required = 0; | |
3189 | prev_nop_frag_since = 0; | |
3190 | } | |
3191 | ||
3192 | for (; nops > 0; --nops) | |
1e915849 | 3193 | add_fixed_insn (NOP_INSN); |
252b5132 | 3194 | |
7d10b47d RS |
3195 | /* Move on to a new frag, so that it is safe to simply |
3196 | decrease the size of prev_nop_frag. */ | |
3197 | frag_wane (frag_now); | |
3198 | frag_new (0); | |
404a8071 | 3199 | mips_move_labels (); |
252b5132 | 3200 | } |
7d10b47d RS |
3201 | mips16_mark_labels (); |
3202 | mips_clear_insn_labels (); | |
252b5132 | 3203 | } |
7d10b47d RS |
3204 | mips_opts.noreorder++; |
3205 | mips_any_noreorder = 1; | |
3206 | } | |
252b5132 | 3207 | |
7d10b47d | 3208 | /* End a nested noreorder block. */ |
252b5132 | 3209 | |
7d10b47d RS |
3210 | static void |
3211 | end_noreorder (void) | |
3212 | { | |
3213 | mips_opts.noreorder--; | |
3214 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
3215 | { | |
3216 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
3217 | handling nop insertion the .set reorder way. */ | |
3218 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
3219 | * (mips_opts.mips16 ? 2 : 4)); | |
3220 | insert_into_history (prev_nop_frag_since, | |
3221 | prev_nop_frag_required, NOP_INSN); | |
3222 | prev_nop_frag = NULL; | |
3223 | } | |
252b5132 RH |
3224 | } |
3225 | ||
584892a6 RS |
3226 | /* Set up global variables for the start of a new macro. */ |
3227 | ||
3228 | static void | |
3229 | macro_start (void) | |
3230 | { | |
3231 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
3232 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 3233 | && (history[0].insn_mo->pinfo |
584892a6 RS |
3234 | & (INSN_UNCOND_BRANCH_DELAY |
3235 | | INSN_COND_BRANCH_DELAY | |
3236 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
3237 | } | |
3238 | ||
3239 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
3240 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
3241 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
3242 | ||
3243 | static const char * | |
3244 | macro_warning (relax_substateT subtype) | |
3245 | { | |
3246 | if (subtype & RELAX_DELAY_SLOT) | |
3247 | return _("Macro instruction expanded into multiple instructions" | |
3248 | " in a branch delay slot"); | |
3249 | else if (subtype & RELAX_NOMACRO) | |
3250 | return _("Macro instruction expanded into multiple instructions"); | |
3251 | else | |
3252 | return 0; | |
3253 | } | |
3254 | ||
3255 | /* Finish up a macro. Emit warnings as appropriate. */ | |
3256 | ||
3257 | static void | |
3258 | macro_end (void) | |
3259 | { | |
3260 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
3261 | { | |
3262 | relax_substateT subtype; | |
3263 | ||
3264 | /* Set up the relaxation warning flags. */ | |
3265 | subtype = 0; | |
3266 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
3267 | subtype |= RELAX_SECOND_LONGER; | |
3268 | if (mips_opts.warn_about_macros) | |
3269 | subtype |= RELAX_NOMACRO; | |
3270 | if (mips_macro_warning.delay_slot_p) | |
3271 | subtype |= RELAX_DELAY_SLOT; | |
3272 | ||
3273 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
3274 | { | |
3275 | /* Either the macro has a single implementation or both | |
3276 | implementations are longer than 4 bytes. Emit the | |
3277 | warning now. */ | |
3278 | const char *msg = macro_warning (subtype); | |
3279 | if (msg != 0) | |
3280 | as_warn (msg); | |
3281 | } | |
3282 | else | |
3283 | { | |
3284 | /* One implementation might need a warning but the other | |
3285 | definitely doesn't. */ | |
3286 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
3287 | } | |
3288 | } | |
3289 | } | |
3290 | ||
6e1304d8 RS |
3291 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
3292 | The first argument in *ARGS will be either the code for a single | |
3293 | relocation or -1 followed by the three codes that make up a | |
3294 | composite relocation. */ | |
3295 | ||
3296 | static void | |
3297 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
3298 | { | |
3299 | int i, next; | |
3300 | ||
3301 | next = va_arg (*args, int); | |
3302 | if (next >= 0) | |
3303 | r[0] = (bfd_reloc_code_real_type) next; | |
3304 | else | |
3305 | for (i = 0; i < 3; i++) | |
3306 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
3307 | } | |
3308 | ||
252b5132 RH |
3309 | /* Build an instruction created by a macro expansion. This is passed |
3310 | a pointer to the count of instructions created so far, an | |
3311 | expression, the name of the instruction to build, an operand format | |
3312 | string, and corresponding arguments. */ | |
3313 | ||
252b5132 | 3314 | static void |
67c0d1eb | 3315 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 3316 | { |
1e915849 | 3317 | const struct mips_opcode *mo; |
252b5132 | 3318 | struct mips_cl_insn insn; |
f6688943 | 3319 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3320 | va_list args; |
252b5132 | 3321 | |
252b5132 | 3322 | va_start (args, fmt); |
252b5132 | 3323 | |
252b5132 RH |
3324 | if (mips_opts.mips16) |
3325 | { | |
67c0d1eb | 3326 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
3327 | va_end (args); |
3328 | return; | |
3329 | } | |
3330 | ||
f6688943 TS |
3331 | r[0] = BFD_RELOC_UNUSED; |
3332 | r[1] = BFD_RELOC_UNUSED; | |
3333 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 RS |
3334 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
3335 | assert (mo); | |
3336 | assert (strcmp (name, mo->name) == 0); | |
3337 | ||
8b082fb1 TS |
3338 | while (1) |
3339 | { | |
3340 | /* Search until we get a match for NAME. It is assumed here that | |
3341 | macros will never generate MDMX, MIPS-3D, or MT instructions. */ | |
3342 | if (strcmp (fmt, mo->args) == 0 | |
3343 | && mo->pinfo != INSN_MACRO | |
3344 | && OPCODE_IS_MEMBER (mo, | |
1e915849 | 3345 | (mips_opts.isa |
9b3f89ee | 3346 | | (mips_opts.mips16 ? INSN_MIPS16 : 0) |
8b082fb1 TS |
3347 | | (mips_opts.ase_dsp ? INSN_DSP : 0) |
3348 | | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
3349 | ? INSN_DSP64 : 0) | |
3350 | | (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0) | |
e16bfa71 | 3351 | | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)), |
fef14a42 | 3352 | mips_opts.arch) |
8b082fb1 TS |
3353 | && (mips_opts.arch != CPU_R4650 || (mo->pinfo & FP_D) == 0)) |
3354 | break; | |
3355 | ||
1e915849 RS |
3356 | ++mo; |
3357 | assert (mo->name); | |
3358 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3359 | } |
3360 | ||
1e915849 | 3361 | create_insn (&insn, mo); |
252b5132 RH |
3362 | for (;;) |
3363 | { | |
3364 | switch (*fmt++) | |
3365 | { | |
3366 | case '\0': | |
3367 | break; | |
3368 | ||
3369 | case ',': | |
3370 | case '(': | |
3371 | case ')': | |
3372 | continue; | |
3373 | ||
5f74bc13 CD |
3374 | case '+': |
3375 | switch (*fmt++) | |
3376 | { | |
3377 | case 'A': | |
3378 | case 'E': | |
bf12938e | 3379 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
3380 | continue; |
3381 | ||
3382 | case 'B': | |
3383 | case 'F': | |
3384 | /* Note that in the macro case, these arguments are already | |
3385 | in MSB form. (When handling the instruction in the | |
3386 | non-macro case, these arguments are sizes from which | |
3387 | MSB values must be calculated.) */ | |
bf12938e | 3388 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3389 | continue; |
3390 | ||
3391 | case 'C': | |
3392 | case 'G': | |
3393 | case 'H': | |
3394 | /* Note that in the macro case, these arguments are already | |
3395 | in MSBD form. (When handling the instruction in the | |
3396 | non-macro case, these arguments are sizes from which | |
3397 | MSBD values must be calculated.) */ | |
bf12938e | 3398 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3399 | continue; |
3400 | ||
3401 | default: | |
3402 | internalError (); | |
3403 | } | |
3404 | continue; | |
3405 | ||
8b082fb1 TS |
3406 | case '2': |
3407 | INSERT_OPERAND (BP, insn, va_arg (args, int)); | |
3408 | continue; | |
3409 | ||
252b5132 RH |
3410 | case 't': |
3411 | case 'w': | |
3412 | case 'E': | |
bf12938e | 3413 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3414 | continue; |
3415 | ||
3416 | case 'c': | |
bf12938e | 3417 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3418 | continue; |
3419 | ||
252b5132 RH |
3420 | case 'T': |
3421 | case 'W': | |
bf12938e | 3422 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3423 | continue; |
3424 | ||
3425 | case 'd': | |
3426 | case 'G': | |
af7ee8bf | 3427 | case 'K': |
bf12938e | 3428 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3429 | continue; |
3430 | ||
4372b673 NC |
3431 | case 'U': |
3432 | { | |
3433 | int tmp = va_arg (args, int); | |
3434 | ||
bf12938e RS |
3435 | INSERT_OPERAND (RT, insn, tmp); |
3436 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3437 | continue; |
4372b673 NC |
3438 | } |
3439 | ||
252b5132 RH |
3440 | case 'V': |
3441 | case 'S': | |
bf12938e | 3442 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3443 | continue; |
3444 | ||
3445 | case 'z': | |
3446 | continue; | |
3447 | ||
3448 | case '<': | |
bf12938e | 3449 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3450 | continue; |
3451 | ||
3452 | case 'D': | |
bf12938e | 3453 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3454 | continue; |
3455 | ||
3456 | case 'B': | |
bf12938e | 3457 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3458 | continue; |
3459 | ||
4372b673 | 3460 | case 'J': |
bf12938e | 3461 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3462 | continue; |
3463 | ||
252b5132 | 3464 | case 'q': |
bf12938e | 3465 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3466 | continue; |
3467 | ||
3468 | case 'b': | |
3469 | case 's': | |
3470 | case 'r': | |
3471 | case 'v': | |
bf12938e | 3472 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3473 | continue; |
3474 | ||
3475 | case 'i': | |
3476 | case 'j': | |
3477 | case 'o': | |
6e1304d8 | 3478 | macro_read_relocs (&args, r); |
cdf6fd85 | 3479 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3480 | || *r == BFD_RELOC_MIPS_LITERAL |
3481 | || *r == BFD_RELOC_MIPS_HIGHER | |
3482 | || *r == BFD_RELOC_HI16_S | |
3483 | || *r == BFD_RELOC_LO16 | |
3484 | || *r == BFD_RELOC_MIPS_GOT16 | |
3485 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3486 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3487 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3488 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3489 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3490 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3491 | continue; |
3492 | ||
3493 | case 'u': | |
6e1304d8 | 3494 | macro_read_relocs (&args, r); |
252b5132 RH |
3495 | assert (ep != NULL |
3496 | && (ep->X_op == O_constant | |
3497 | || (ep->X_op == O_symbol | |
f6688943 TS |
3498 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3499 | || *r == BFD_RELOC_HI16_S | |
3500 | || *r == BFD_RELOC_HI16 | |
3501 | || *r == BFD_RELOC_GPREL16 | |
3502 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3503 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3504 | continue; |
3505 | ||
3506 | case 'p': | |
3507 | assert (ep != NULL); | |
bad36eac | 3508 | |
252b5132 RH |
3509 | /* |
3510 | * This allows macro() to pass an immediate expression for | |
3511 | * creating short branches without creating a symbol. | |
bad36eac DJ |
3512 | * |
3513 | * We don't allow branch relaxation for these branches, as | |
3514 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
3515 | */ |
3516 | if (ep->X_op == O_constant) | |
3517 | { | |
bad36eac DJ |
3518 | if ((ep->X_add_number & 3) != 0) |
3519 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3520 | (unsigned long) ep->X_add_number); | |
3521 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
3522 | as_bad (_("branch address range overflow (0x%lx)"), | |
3523 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3524 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
3525 | ep = NULL; | |
3526 | } | |
3527 | else | |
0b25d3e6 | 3528 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3529 | continue; |
3530 | ||
3531 | case 'a': | |
3532 | assert (ep != NULL); | |
f6688943 | 3533 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3534 | continue; |
3535 | ||
3536 | case 'C': | |
a9e24354 | 3537 | INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long)); |
252b5132 RH |
3538 | continue; |
3539 | ||
d43b4baf | 3540 | case 'k': |
a9e24354 | 3541 | INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long)); |
d43b4baf TS |
3542 | continue; |
3543 | ||
252b5132 RH |
3544 | default: |
3545 | internalError (); | |
3546 | } | |
3547 | break; | |
3548 | } | |
3549 | va_end (args); | |
f6688943 | 3550 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3551 | |
4d7206a2 | 3552 | append_insn (&insn, ep, r); |
252b5132 RH |
3553 | } |
3554 | ||
3555 | static void | |
67c0d1eb | 3556 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3557 | va_list args) |
252b5132 | 3558 | { |
1e915849 | 3559 | struct mips_opcode *mo; |
252b5132 | 3560 | struct mips_cl_insn insn; |
f6688943 TS |
3561 | bfd_reloc_code_real_type r[3] |
3562 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3563 | |
1e915849 RS |
3564 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3565 | assert (mo); | |
3566 | assert (strcmp (name, mo->name) == 0); | |
252b5132 | 3567 | |
1e915849 | 3568 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 3569 | { |
1e915849 RS |
3570 | ++mo; |
3571 | assert (mo->name); | |
3572 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3573 | } |
3574 | ||
1e915849 | 3575 | create_insn (&insn, mo); |
252b5132 RH |
3576 | for (;;) |
3577 | { | |
3578 | int c; | |
3579 | ||
3580 | c = *fmt++; | |
3581 | switch (c) | |
3582 | { | |
3583 | case '\0': | |
3584 | break; | |
3585 | ||
3586 | case ',': | |
3587 | case '(': | |
3588 | case ')': | |
3589 | continue; | |
3590 | ||
3591 | case 'y': | |
3592 | case 'w': | |
bf12938e | 3593 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int)); |
252b5132 RH |
3594 | continue; |
3595 | ||
3596 | case 'x': | |
3597 | case 'v': | |
bf12938e | 3598 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int)); |
252b5132 RH |
3599 | continue; |
3600 | ||
3601 | case 'z': | |
bf12938e | 3602 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int)); |
252b5132 RH |
3603 | continue; |
3604 | ||
3605 | case 'Z': | |
bf12938e | 3606 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int)); |
252b5132 RH |
3607 | continue; |
3608 | ||
3609 | case '0': | |
3610 | case 'S': | |
3611 | case 'P': | |
3612 | case 'R': | |
3613 | continue; | |
3614 | ||
3615 | case 'X': | |
bf12938e | 3616 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int)); |
252b5132 RH |
3617 | continue; |
3618 | ||
3619 | case 'Y': | |
3620 | { | |
3621 | int regno; | |
3622 | ||
3623 | regno = va_arg (args, int); | |
3624 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
a9e24354 | 3625 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
3626 | } |
3627 | continue; | |
3628 | ||
3629 | case '<': | |
3630 | case '>': | |
3631 | case '4': | |
3632 | case '5': | |
3633 | case 'H': | |
3634 | case 'W': | |
3635 | case 'D': | |
3636 | case 'j': | |
3637 | case '8': | |
3638 | case 'V': | |
3639 | case 'C': | |
3640 | case 'U': | |
3641 | case 'k': | |
3642 | case 'K': | |
3643 | case 'p': | |
3644 | case 'q': | |
3645 | { | |
3646 | assert (ep != NULL); | |
3647 | ||
3648 | if (ep->X_op != O_constant) | |
874e8986 | 3649 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3650 | else |
3651 | { | |
b34976b6 AM |
3652 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3653 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3654 | &insn.extend); |
252b5132 | 3655 | ep = NULL; |
f6688943 | 3656 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3657 | } |
3658 | } | |
3659 | continue; | |
3660 | ||
3661 | case '6': | |
bf12938e | 3662 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int)); |
252b5132 RH |
3663 | continue; |
3664 | } | |
3665 | ||
3666 | break; | |
3667 | } | |
3668 | ||
f6688943 | 3669 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3670 | |
4d7206a2 | 3671 | append_insn (&insn, ep, r); |
252b5132 RH |
3672 | } |
3673 | ||
2051e8c4 MR |
3674 | /* |
3675 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
3676 | * higher bits unset. | |
3677 | */ | |
9f872bbe | 3678 | static void |
2051e8c4 MR |
3679 | normalize_constant_expr (expressionS *ex) |
3680 | { | |
9ee2a2d4 | 3681 | if (ex->X_op == O_constant |
2051e8c4 MR |
3682 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
3683 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3684 | - 0x80000000); | |
3685 | } | |
3686 | ||
3687 | /* | |
3688 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
3689 | * all higher bits unset. | |
3690 | */ | |
3691 | static void | |
3692 | normalize_address_expr (expressionS *ex) | |
3693 | { | |
3694 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
3695 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
3696 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
3697 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3698 | - 0x80000000); | |
3699 | } | |
3700 | ||
438c16b8 TS |
3701 | /* |
3702 | * Generate a "jalr" instruction with a relocation hint to the called | |
3703 | * function. This occurs in NewABI PIC code. | |
3704 | */ | |
3705 | static void | |
67c0d1eb | 3706 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3707 | { |
685736be | 3708 | char *f = NULL; |
b34976b6 | 3709 | |
438c16b8 | 3710 | if (HAVE_NEWABI) |
f21f8242 | 3711 | { |
cc3d92a5 | 3712 | frag_grow (8); |
f21f8242 AO |
3713 | f = frag_more (0); |
3714 | } | |
67c0d1eb | 3715 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3716 | if (HAVE_NEWABI) |
f21f8242 | 3717 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3718 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3719 | } |
3720 | ||
252b5132 RH |
3721 | /* |
3722 | * Generate a "lui" instruction. | |
3723 | */ | |
3724 | static void | |
67c0d1eb | 3725 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3726 | { |
3727 | expressionS high_expr; | |
1e915849 | 3728 | const struct mips_opcode *mo; |
252b5132 | 3729 | struct mips_cl_insn insn; |
f6688943 TS |
3730 | bfd_reloc_code_real_type r[3] |
3731 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3732 | const char *name = "lui"; |
3733 | const char *fmt = "t,u"; | |
252b5132 RH |
3734 | |
3735 | assert (! mips_opts.mips16); | |
3736 | ||
4d7206a2 | 3737 | high_expr = *ep; |
252b5132 RH |
3738 | |
3739 | if (high_expr.X_op == O_constant) | |
3740 | { | |
54f4ddb3 | 3741 | /* We can compute the instruction now without a relocation entry. */ |
e7d556df TS |
3742 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3743 | >> 16) & 0xffff; | |
f6688943 | 3744 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3745 | } |
78e1bb40 | 3746 | else |
252b5132 RH |
3747 | { |
3748 | assert (ep->X_op == O_symbol); | |
bbe506e8 TS |
3749 | /* _gp_disp is a special case, used from s_cpload. |
3750 | __gnu_local_gp is used if mips_no_shared. */ | |
252b5132 | 3751 | assert (mips_pic == NO_PIC |
78e1bb40 | 3752 | || (! HAVE_NEWABI |
aa6975fb ILT |
3753 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
3754 | || (! mips_in_shared | |
bbe506e8 TS |
3755 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
3756 | "__gnu_local_gp") == 0)); | |
f6688943 | 3757 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3758 | } |
3759 | ||
1e915849 RS |
3760 | mo = hash_find (op_hash, name); |
3761 | assert (strcmp (name, mo->name) == 0); | |
3762 | assert (strcmp (fmt, mo->args) == 0); | |
3763 | create_insn (&insn, mo); | |
252b5132 | 3764 | |
bf12938e RS |
3765 | insn.insn_opcode = insn.insn_mo->match; |
3766 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 3767 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3768 | { |
3769 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3770 | append_insn (&insn, NULL, r); |
252b5132 RH |
3771 | } |
3772 | else | |
4d7206a2 | 3773 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3774 | } |
3775 | ||
885add95 CD |
3776 | /* Generate a sequence of instructions to do a load or store from a constant |
3777 | offset off of a base register (breg) into/from a target register (treg), | |
3778 | using AT if necessary. */ | |
3779 | static void | |
67c0d1eb RS |
3780 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3781 | int treg, int breg, int dbl) | |
885add95 CD |
3782 | { |
3783 | assert (ep->X_op == O_constant); | |
3784 | ||
256ab948 | 3785 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
3786 | if (!dbl) |
3787 | normalize_constant_expr (ep); | |
256ab948 | 3788 | |
67c1ffbe | 3789 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3790 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3791 | as_warn (_("operand overflow")); |
3792 | ||
3793 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3794 | { | |
3795 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3796 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3797 | } |
3798 | else | |
3799 | { | |
3800 | /* 32-bit offset, need multiple instructions and AT, like: | |
3801 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3802 | addu $tempreg,$tempreg,$breg | |
3803 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3804 | to handle the complete offset. */ | |
67c0d1eb RS |
3805 | macro_build_lui (ep, AT); |
3806 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3807 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 CD |
3808 | |
3809 | if (mips_opts.noat) | |
8fc2e39e | 3810 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
3811 | } |
3812 | } | |
3813 | ||
252b5132 RH |
3814 | /* set_at() |
3815 | * Generates code to set the $at register to true (one) | |
3816 | * if reg is less than the immediate expression. | |
3817 | */ | |
3818 | static void | |
67c0d1eb | 3819 | set_at (int reg, int unsignedp) |
252b5132 RH |
3820 | { |
3821 | if (imm_expr.X_op == O_constant | |
3822 | && imm_expr.X_add_number >= -0x8000 | |
3823 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3824 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3825 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3826 | else |
3827 | { | |
67c0d1eb RS |
3828 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3829 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3830 | } |
3831 | } | |
3832 | ||
3833 | /* Warn if an expression is not a constant. */ | |
3834 | ||
3835 | static void | |
17a2f251 | 3836 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3837 | { |
3838 | if (ex->X_op == O_big) | |
3839 | as_bad (_("unsupported large constant")); | |
3840 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
3841 | as_bad (_("Instruction %s requires absolute expression"), |
3842 | ip->insn_mo->name); | |
13757d0c | 3843 | |
9ee2a2d4 MR |
3844 | if (HAVE_32BIT_GPRS) |
3845 | normalize_constant_expr (ex); | |
252b5132 RH |
3846 | } |
3847 | ||
3848 | /* Count the leading zeroes by performing a binary chop. This is a | |
3849 | bulky bit of source, but performance is a LOT better for the | |
3850 | majority of values than a simple loop to count the bits: | |
3851 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3852 | if ((v) & (1 << (31 - lcnt))) | |
3853 | break; | |
3854 | However it is not code size friendly, and the gain will drop a bit | |
3855 | on certain cached systems. | |
3856 | */ | |
3857 | #define COUNT_TOP_ZEROES(v) \ | |
3858 | (((v) & ~0xffff) == 0 \ | |
3859 | ? ((v) & ~0xff) == 0 \ | |
3860 | ? ((v) & ~0xf) == 0 \ | |
3861 | ? ((v) & ~0x3) == 0 \ | |
3862 | ? ((v) & ~0x1) == 0 \ | |
3863 | ? !(v) \ | |
3864 | ? 32 \ | |
3865 | : 31 \ | |
3866 | : 30 \ | |
3867 | : ((v) & ~0x7) == 0 \ | |
3868 | ? 29 \ | |
3869 | : 28 \ | |
3870 | : ((v) & ~0x3f) == 0 \ | |
3871 | ? ((v) & ~0x1f) == 0 \ | |
3872 | ? 27 \ | |
3873 | : 26 \ | |
3874 | : ((v) & ~0x7f) == 0 \ | |
3875 | ? 25 \ | |
3876 | : 24 \ | |
3877 | : ((v) & ~0xfff) == 0 \ | |
3878 | ? ((v) & ~0x3ff) == 0 \ | |
3879 | ? ((v) & ~0x1ff) == 0 \ | |
3880 | ? 23 \ | |
3881 | : 22 \ | |
3882 | : ((v) & ~0x7ff) == 0 \ | |
3883 | ? 21 \ | |
3884 | : 20 \ | |
3885 | : ((v) & ~0x3fff) == 0 \ | |
3886 | ? ((v) & ~0x1fff) == 0 \ | |
3887 | ? 19 \ | |
3888 | : 18 \ | |
3889 | : ((v) & ~0x7fff) == 0 \ | |
3890 | ? 17 \ | |
3891 | : 16 \ | |
3892 | : ((v) & ~0xffffff) == 0 \ | |
3893 | ? ((v) & ~0xfffff) == 0 \ | |
3894 | ? ((v) & ~0x3ffff) == 0 \ | |
3895 | ? ((v) & ~0x1ffff) == 0 \ | |
3896 | ? 15 \ | |
3897 | : 14 \ | |
3898 | : ((v) & ~0x7ffff) == 0 \ | |
3899 | ? 13 \ | |
3900 | : 12 \ | |
3901 | : ((v) & ~0x3fffff) == 0 \ | |
3902 | ? ((v) & ~0x1fffff) == 0 \ | |
3903 | ? 11 \ | |
3904 | : 10 \ | |
3905 | : ((v) & ~0x7fffff) == 0 \ | |
3906 | ? 9 \ | |
3907 | : 8 \ | |
3908 | : ((v) & ~0xfffffff) == 0 \ | |
3909 | ? ((v) & ~0x3ffffff) == 0 \ | |
3910 | ? ((v) & ~0x1ffffff) == 0 \ | |
3911 | ? 7 \ | |
3912 | : 6 \ | |
3913 | : ((v) & ~0x7ffffff) == 0 \ | |
3914 | ? 5 \ | |
3915 | : 4 \ | |
3916 | : ((v) & ~0x3fffffff) == 0 \ | |
3917 | ? ((v) & ~0x1fffffff) == 0 \ | |
3918 | ? 3 \ | |
3919 | : 2 \ | |
3920 | : ((v) & ~0x7fffffff) == 0 \ | |
3921 | ? 1 \ | |
3922 | : 0) | |
3923 | ||
3924 | /* load_register() | |
67c1ffbe | 3925 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3926 | * an absolute expression value into a register. |
3927 | */ | |
3928 | static void | |
67c0d1eb | 3929 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3930 | { |
3931 | int freg; | |
3932 | expressionS hi32, lo32; | |
3933 | ||
3934 | if (ep->X_op != O_big) | |
3935 | { | |
3936 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3937 | |
3938 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
3939 | if (!dbl) |
3940 | normalize_constant_expr (ep); | |
256ab948 TS |
3941 | |
3942 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3943 | { |
3944 | /* We can handle 16 bit signed values with an addiu to | |
3945 | $zero. No need to ever use daddiu here, since $zero and | |
3946 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3947 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3948 | return; |
3949 | } | |
3950 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3951 | { | |
3952 | /* We can handle 16 bit unsigned values with an ori to | |
3953 | $zero. */ | |
67c0d1eb | 3954 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3955 | return; |
3956 | } | |
256ab948 | 3957 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3958 | { |
3959 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3960 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3961 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3962 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3963 | return; |
3964 | } | |
3965 | } | |
3966 | ||
3967 | /* The value is larger than 32 bits. */ | |
3968 | ||
2051e8c4 | 3969 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 3970 | { |
55e08f71 NC |
3971 | char value[32]; |
3972 | ||
3973 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 3974 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 3975 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3976 | return; |
3977 | } | |
3978 | ||
3979 | if (ep->X_op != O_big) | |
3980 | { | |
3981 | hi32 = *ep; | |
3982 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3983 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3984 | hi32.X_add_number &= 0xffffffff; | |
3985 | lo32 = *ep; | |
3986 | lo32.X_add_number &= 0xffffffff; | |
3987 | } | |
3988 | else | |
3989 | { | |
3990 | assert (ep->X_add_number > 2); | |
3991 | if (ep->X_add_number == 3) | |
3992 | generic_bignum[3] = 0; | |
3993 | else if (ep->X_add_number > 4) | |
3994 | as_bad (_("Number larger than 64 bits")); | |
3995 | lo32.X_op = O_constant; | |
3996 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3997 | hi32.X_op = O_constant; | |
3998 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3999 | } | |
4000 | ||
4001 | if (hi32.X_add_number == 0) | |
4002 | freg = 0; | |
4003 | else | |
4004 | { | |
4005 | int shift, bit; | |
4006 | unsigned long hi, lo; | |
4007 | ||
956cd1d6 | 4008 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
4009 | { |
4010 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
4011 | { | |
67c0d1eb | 4012 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4013 | return; |
4014 | } | |
4015 | if (lo32.X_add_number & 0x80000000) | |
4016 | { | |
67c0d1eb | 4017 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4018 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 4019 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
4020 | return; |
4021 | } | |
4022 | } | |
252b5132 RH |
4023 | |
4024 | /* Check for 16bit shifted constant. We know that hi32 is | |
4025 | non-zero, so start the mask on the first bit of the hi32 | |
4026 | value. */ | |
4027 | shift = 17; | |
4028 | do | |
beae10d5 KH |
4029 | { |
4030 | unsigned long himask, lomask; | |
4031 | ||
4032 | if (shift < 32) | |
4033 | { | |
4034 | himask = 0xffff >> (32 - shift); | |
4035 | lomask = (0xffff << shift) & 0xffffffff; | |
4036 | } | |
4037 | else | |
4038 | { | |
4039 | himask = 0xffff << (shift - 32); | |
4040 | lomask = 0; | |
4041 | } | |
4042 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
4043 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
4044 | { | |
4045 | expressionS tmp; | |
4046 | ||
4047 | tmp.X_op = O_constant; | |
4048 | if (shift < 32) | |
4049 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
4050 | | (lo32.X_add_number >> shift)); | |
4051 | else | |
4052 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
4053 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
4054 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
4055 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4056 | return; |
4057 | } | |
f9419b05 | 4058 | ++shift; |
beae10d5 KH |
4059 | } |
4060 | while (shift <= (64 - 16)); | |
252b5132 RH |
4061 | |
4062 | /* Find the bit number of the lowest one bit, and store the | |
4063 | shifted value in hi/lo. */ | |
4064 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
4065 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
4066 | if (lo != 0) | |
4067 | { | |
4068 | bit = 0; | |
4069 | while ((lo & 1) == 0) | |
4070 | { | |
4071 | lo >>= 1; | |
4072 | ++bit; | |
4073 | } | |
4074 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
4075 | hi >>= bit; | |
4076 | } | |
4077 | else | |
4078 | { | |
4079 | bit = 32; | |
4080 | while ((hi & 1) == 0) | |
4081 | { | |
4082 | hi >>= 1; | |
4083 | ++bit; | |
4084 | } | |
4085 | lo = hi; | |
4086 | hi = 0; | |
4087 | } | |
4088 | ||
4089 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
4090 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
4091 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
4092 | { |
4093 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 4094 | if (shift != 0) |
beae10d5 | 4095 | { |
252b5132 RH |
4096 | expressionS tmp; |
4097 | ||
4098 | /* This instruction will set the register to be all | |
4099 | ones. */ | |
beae10d5 KH |
4100 | tmp.X_op = O_constant; |
4101 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 4102 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4103 | if (bit != 0) |
4104 | { | |
4105 | bit += shift; | |
67c0d1eb RS |
4106 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
4107 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 4108 | } |
67c0d1eb RS |
4109 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
4110 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4111 | return; |
4112 | } | |
4113 | } | |
252b5132 RH |
4114 | |
4115 | /* Sign extend hi32 before calling load_register, because we can | |
4116 | generally get better code when we load a sign extended value. */ | |
4117 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 4118 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 4119 | load_register (reg, &hi32, 0); |
252b5132 RH |
4120 | freg = reg; |
4121 | } | |
4122 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
4123 | { | |
4124 | if (freg != 0) | |
4125 | { | |
67c0d1eb | 4126 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
4127 | freg = reg; |
4128 | } | |
4129 | } | |
4130 | else | |
4131 | { | |
4132 | expressionS mid16; | |
4133 | ||
956cd1d6 | 4134 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 4135 | { |
67c0d1eb RS |
4136 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
4137 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
4138 | return; |
4139 | } | |
252b5132 RH |
4140 | |
4141 | if (freg != 0) | |
4142 | { | |
67c0d1eb | 4143 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
4144 | freg = reg; |
4145 | } | |
4146 | mid16 = lo32; | |
4147 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
4148 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
4149 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
4150 | freg = reg; |
4151 | } | |
4152 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 4153 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
4154 | } |
4155 | ||
269137b2 TS |
4156 | static inline void |
4157 | load_delay_nop (void) | |
4158 | { | |
4159 | if (!gpr_interlocks) | |
4160 | macro_build (NULL, "nop", ""); | |
4161 | } | |
4162 | ||
252b5132 RH |
4163 | /* Load an address into a register. */ |
4164 | ||
4165 | static void | |
67c0d1eb | 4166 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 4167 | { |
252b5132 RH |
4168 | if (ep->X_op != O_constant |
4169 | && ep->X_op != O_symbol) | |
4170 | { | |
4171 | as_bad (_("expression too complex")); | |
4172 | ep->X_op = O_constant; | |
4173 | } | |
4174 | ||
4175 | if (ep->X_op == O_constant) | |
4176 | { | |
67c0d1eb | 4177 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4178 | return; |
4179 | } | |
4180 | ||
4181 | if (mips_pic == NO_PIC) | |
4182 | { | |
4183 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 4184 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4185 | Otherwise we want |
4186 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
4187 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 4188 | If we have an addend, we always use the latter form. |
76b3015f | 4189 | |
d6bc6245 TS |
4190 | With 64bit address space and a usable $at we want |
4191 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4192 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4193 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4194 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4195 | dsll32 $reg,0 | |
3a482fd5 | 4196 | daddu $reg,$reg,$at |
76b3015f | 4197 | |
c03099e6 | 4198 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4199 | on superscalar processors. |
4200 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4201 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4202 | dsll $reg,16 | |
4203 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
4204 | dsll $reg,16 | |
4205 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
4206 | |
4207 | For GP relative symbols in 64bit address space we can use | |
4208 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4209 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 4210 | { |
6caf9ef4 TS |
4211 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
4212 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
4213 | { | |
4214 | relax_start (ep->X_add_symbol); | |
4215 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
4216 | mips_gp_register, BFD_RELOC_GPREL16); | |
4217 | relax_switch (); | |
4218 | } | |
d6bc6245 | 4219 | |
b8285c27 | 4220 | if (*used_at == 0 && !mips_opts.noat) |
d6bc6245 | 4221 | { |
67c0d1eb RS |
4222 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4223 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
4224 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4225 | BFD_RELOC_MIPS_HIGHER); | |
4226 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
4227 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
4228 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
4229 | *used_at = 1; |
4230 | } | |
4231 | else | |
4232 | { | |
67c0d1eb RS |
4233 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4234 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4235 | BFD_RELOC_MIPS_HIGHER); | |
4236 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4237 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
4238 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4239 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 4240 | } |
6caf9ef4 TS |
4241 | |
4242 | if (mips_relax.sequence) | |
4243 | relax_end (); | |
d6bc6245 | 4244 | } |
252b5132 RH |
4245 | else |
4246 | { | |
d6bc6245 | 4247 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 4248 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 4249 | { |
4d7206a2 | 4250 | relax_start (ep->X_add_symbol); |
67c0d1eb | 4251 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 4252 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 4253 | relax_switch (); |
d6bc6245 | 4254 | } |
67c0d1eb RS |
4255 | macro_build_lui (ep, reg); |
4256 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
4257 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4258 | if (mips_relax.sequence) |
4259 | relax_end (); | |
d6bc6245 | 4260 | } |
252b5132 | 4261 | } |
0a44bf69 | 4262 | else if (!mips_big_got) |
252b5132 RH |
4263 | { |
4264 | expressionS ex; | |
4265 | ||
4266 | /* If this is a reference to an external symbol, we want | |
4267 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4268 | Otherwise we want | |
4269 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4270 | nop | |
4271 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
4272 | If there is a constant, it must be added in after. |
4273 | ||
ed6fb7bd | 4274 | If we have NewABI, we want |
f5040a92 AO |
4275 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
4276 | unless we're referencing a global symbol with a non-zero | |
4277 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
4278 | if (HAVE_NEWABI) |
4279 | { | |
f5040a92 AO |
4280 | if (ep->X_add_number) |
4281 | { | |
4d7206a2 | 4282 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4283 | ep->X_add_number = 0; |
4d7206a2 | 4284 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4285 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4286 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
4287 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4288 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4289 | ex.X_op = O_constant; | |
67c0d1eb | 4290 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4291 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4292 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 4293 | relax_switch (); |
f5040a92 | 4294 | } |
67c0d1eb | 4295 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4296 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
4297 | if (mips_relax.sequence) |
4298 | relax_end (); | |
ed6fb7bd SC |
4299 | } |
4300 | else | |
4301 | { | |
f5040a92 AO |
4302 | ex.X_add_number = ep->X_add_number; |
4303 | ep->X_add_number = 0; | |
67c0d1eb RS |
4304 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4305 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 4306 | load_delay_nop (); |
4d7206a2 RS |
4307 | relax_start (ep->X_add_symbol); |
4308 | relax_switch (); | |
67c0d1eb | 4309 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4310 | BFD_RELOC_LO16); |
4d7206a2 | 4311 | relax_end (); |
ed6fb7bd | 4312 | |
f5040a92 AO |
4313 | if (ex.X_add_number != 0) |
4314 | { | |
4315 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4316 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4317 | ex.X_op = O_constant; | |
67c0d1eb | 4318 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4319 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4320 | } |
252b5132 RH |
4321 | } |
4322 | } | |
0a44bf69 | 4323 | else if (mips_big_got) |
252b5132 RH |
4324 | { |
4325 | expressionS ex; | |
252b5132 RH |
4326 | |
4327 | /* This is the large GOT case. If this is a reference to an | |
4328 | external symbol, we want | |
4329 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4330 | addu $reg,$reg,$gp | |
4331 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
4332 | |
4333 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
4334 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4335 | nop | |
4336 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 4337 | If there is a constant, it must be added in after. |
f5040a92 AO |
4338 | |
4339 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
4340 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
4341 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 4342 | */ |
438c16b8 TS |
4343 | if (HAVE_NEWABI) |
4344 | { | |
4d7206a2 | 4345 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4346 | ep->X_add_number = 0; |
4d7206a2 | 4347 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4348 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4349 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4350 | reg, reg, mips_gp_register); | |
4351 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4352 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4353 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4354 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4355 | else if (ex.X_add_number) | |
4356 | { | |
4357 | ex.X_op = O_constant; | |
67c0d1eb RS |
4358 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4359 | BFD_RELOC_LO16); | |
f5040a92 AO |
4360 | } |
4361 | ||
4362 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4363 | relax_switch (); |
67c0d1eb | 4364 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4365 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4366 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4367 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4368 | relax_end (); |
438c16b8 | 4369 | } |
252b5132 | 4370 | else |
438c16b8 | 4371 | { |
f5040a92 AO |
4372 | ex.X_add_number = ep->X_add_number; |
4373 | ep->X_add_number = 0; | |
4d7206a2 | 4374 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4375 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4376 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4377 | reg, reg, mips_gp_register); | |
4378 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4379 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4380 | relax_switch (); |
4381 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4382 | { |
4383 | /* We need a nop before loading from $gp. This special | |
4384 | check is required because the lui which starts the main | |
4385 | instruction stream does not refer to $gp, and so will not | |
4386 | insert the nop which may be required. */ | |
67c0d1eb | 4387 | macro_build (NULL, "nop", ""); |
438c16b8 | 4388 | } |
67c0d1eb | 4389 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4390 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4391 | load_delay_nop (); |
67c0d1eb | 4392 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4393 | BFD_RELOC_LO16); |
4d7206a2 | 4394 | relax_end (); |
438c16b8 | 4395 | |
f5040a92 AO |
4396 | if (ex.X_add_number != 0) |
4397 | { | |
4398 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4399 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4400 | ex.X_op = O_constant; | |
67c0d1eb RS |
4401 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4402 | BFD_RELOC_LO16); | |
f5040a92 | 4403 | } |
252b5132 RH |
4404 | } |
4405 | } | |
252b5132 RH |
4406 | else |
4407 | abort (); | |
8fc2e39e TS |
4408 | |
4409 | if (mips_opts.noat && *used_at == 1) | |
4410 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
4411 | } |
4412 | ||
ea1fb5dc RS |
4413 | /* Move the contents of register SOURCE into register DEST. */ |
4414 | ||
4415 | static void | |
67c0d1eb | 4416 | move_register (int dest, int source) |
ea1fb5dc | 4417 | { |
67c0d1eb RS |
4418 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4419 | dest, source, 0); | |
ea1fb5dc RS |
4420 | } |
4421 | ||
4d7206a2 | 4422 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4423 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4424 | The two alternatives are: | |
4d7206a2 RS |
4425 | |
4426 | Global symbol Local sybmol | |
4427 | ------------- ------------ | |
4428 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4429 | ... ... | |
4430 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4431 | ||
4432 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4433 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4434 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4435 | |
4436 | static void | |
67c0d1eb | 4437 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4438 | { |
4439 | expressionS global; | |
4440 | ||
4441 | global = *local; | |
4442 | global.X_add_number = 0; | |
4443 | ||
4444 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4445 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4446 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4447 | relax_switch (); |
67c0d1eb RS |
4448 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4449 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4450 | relax_end (); |
4451 | } | |
4452 | ||
4453 | static void | |
67c0d1eb | 4454 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4455 | { |
4456 | expressionS global; | |
4457 | ||
4458 | global.X_op = O_constant; | |
4459 | global.X_op_symbol = NULL; | |
4460 | global.X_add_symbol = NULL; | |
4461 | global.X_add_number = local->X_add_number; | |
4462 | ||
4463 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4464 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4465 | dest, dest, BFD_RELOC_LO16); |
4466 | relax_switch (); | |
67c0d1eb | 4467 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4468 | relax_end (); |
4469 | } | |
4470 | ||
f6a22291 MR |
4471 | static void |
4472 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4473 | { | |
4474 | expressionS global; | |
4475 | int hold_mips_optimize; | |
4476 | ||
4477 | global.X_op = O_constant; | |
4478 | global.X_op_symbol = NULL; | |
4479 | global.X_add_symbol = NULL; | |
4480 | global.X_add_number = local->X_add_number; | |
4481 | ||
4482 | relax_start (local->X_add_symbol); | |
4483 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4484 | relax_switch (); | |
4485 | /* Set mips_optimize around the lui instruction to avoid | |
4486 | inserting an unnecessary nop after the lw. */ | |
4487 | hold_mips_optimize = mips_optimize; | |
4488 | mips_optimize = 2; | |
4489 | macro_build_lui (&global, tmp); | |
4490 | mips_optimize = hold_mips_optimize; | |
4491 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4492 | relax_end (); | |
4493 | ||
4494 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4495 | } | |
4496 | ||
252b5132 RH |
4497 | /* |
4498 | * Build macros | |
4499 | * This routine implements the seemingly endless macro or synthesized | |
4500 | * instructions and addressing modes in the mips assembly language. Many | |
4501 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4502 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4503 | * this verbose method. Others are not simple macros but are more like |
4504 | * optimizing code generation. | |
4505 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4506 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4507 | * The ensuing load upper instructions are ommited. This implies some kind |
4508 | * of global optimization. We currently only optimize within a single macro. | |
4509 | * For many of the load and store macros if the address is specified as a | |
4510 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4511 | * first load register 'at' with zero and use it as the base register. The | |
4512 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4513 | * we're missing. | |
4514 | */ | |
4515 | static void | |
17a2f251 | 4516 | macro (struct mips_cl_insn *ip) |
252b5132 | 4517 | { |
3994f87e | 4518 | int treg, sreg, dreg, breg; |
252b5132 RH |
4519 | int tempreg; |
4520 | int mask; | |
43841e91 | 4521 | int used_at = 0; |
252b5132 RH |
4522 | expressionS expr1; |
4523 | const char *s; | |
4524 | const char *s2; | |
4525 | const char *fmt; | |
4526 | int likely = 0; | |
4527 | int dbl = 0; | |
4528 | int coproc = 0; | |
4529 | int lr = 0; | |
4530 | int imm = 0; | |
1abe91b1 | 4531 | int call = 0; |
252b5132 | 4532 | int off; |
67c0d1eb | 4533 | offsetT maxnum; |
252b5132 | 4534 | bfd_reloc_code_real_type r; |
252b5132 RH |
4535 | int hold_mips_optimize; |
4536 | ||
4537 | assert (! mips_opts.mips16); | |
4538 | ||
4539 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4540 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4541 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4542 | mask = ip->insn_mo->mask; | |
4543 | ||
4544 | expr1.X_op = O_constant; | |
4545 | expr1.X_op_symbol = NULL; | |
4546 | expr1.X_add_symbol = NULL; | |
4547 | expr1.X_add_number = 1; | |
4548 | ||
4549 | switch (mask) | |
4550 | { | |
4551 | case M_DABS: | |
4552 | dbl = 1; | |
4553 | case M_ABS: | |
4554 | /* bgez $a0,.+12 | |
4555 | move v0,$a0 | |
4556 | sub v0,$zero,$a0 | |
4557 | */ | |
4558 | ||
7d10b47d | 4559 | start_noreorder (); |
252b5132 RH |
4560 | |
4561 | expr1.X_add_number = 8; | |
67c0d1eb | 4562 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4563 | if (dreg == sreg) |
67c0d1eb | 4564 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4565 | else |
67c0d1eb RS |
4566 | move_register (dreg, sreg); |
4567 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 4568 | |
7d10b47d | 4569 | end_noreorder (); |
8fc2e39e | 4570 | break; |
252b5132 RH |
4571 | |
4572 | case M_ADD_I: | |
4573 | s = "addi"; | |
4574 | s2 = "add"; | |
4575 | goto do_addi; | |
4576 | case M_ADDU_I: | |
4577 | s = "addiu"; | |
4578 | s2 = "addu"; | |
4579 | goto do_addi; | |
4580 | case M_DADD_I: | |
4581 | dbl = 1; | |
4582 | s = "daddi"; | |
4583 | s2 = "dadd"; | |
4584 | goto do_addi; | |
4585 | case M_DADDU_I: | |
4586 | dbl = 1; | |
4587 | s = "daddiu"; | |
4588 | s2 = "daddu"; | |
4589 | do_addi: | |
4590 | if (imm_expr.X_op == O_constant | |
4591 | && imm_expr.X_add_number >= -0x8000 | |
4592 | && imm_expr.X_add_number < 0x8000) | |
4593 | { | |
67c0d1eb | 4594 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4595 | break; |
252b5132 | 4596 | } |
8fc2e39e | 4597 | used_at = 1; |
67c0d1eb RS |
4598 | load_register (AT, &imm_expr, dbl); |
4599 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4600 | break; |
4601 | ||
4602 | case M_AND_I: | |
4603 | s = "andi"; | |
4604 | s2 = "and"; | |
4605 | goto do_bit; | |
4606 | case M_OR_I: | |
4607 | s = "ori"; | |
4608 | s2 = "or"; | |
4609 | goto do_bit; | |
4610 | case M_NOR_I: | |
4611 | s = ""; | |
4612 | s2 = "nor"; | |
4613 | goto do_bit; | |
4614 | case M_XOR_I: | |
4615 | s = "xori"; | |
4616 | s2 = "xor"; | |
4617 | do_bit: | |
4618 | if (imm_expr.X_op == O_constant | |
4619 | && imm_expr.X_add_number >= 0 | |
4620 | && imm_expr.X_add_number < 0x10000) | |
4621 | { | |
4622 | if (mask != M_NOR_I) | |
67c0d1eb | 4623 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4624 | else |
4625 | { | |
67c0d1eb RS |
4626 | macro_build (&imm_expr, "ori", "t,r,i", |
4627 | treg, sreg, BFD_RELOC_LO16); | |
4628 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4629 | } |
8fc2e39e | 4630 | break; |
252b5132 RH |
4631 | } |
4632 | ||
8fc2e39e | 4633 | used_at = 1; |
67c0d1eb RS |
4634 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4635 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4636 | break; |
4637 | ||
8b082fb1 TS |
4638 | case M_BALIGN: |
4639 | switch (imm_expr.X_add_number) | |
4640 | { | |
4641 | case 0: | |
4642 | macro_build (NULL, "nop", ""); | |
4643 | break; | |
4644 | case 2: | |
4645 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
4646 | break; | |
4647 | default: | |
4648 | macro_build (NULL, "balign", "t,s,2", treg, sreg, | |
4649 | (int)imm_expr.X_add_number); | |
4650 | break; | |
4651 | } | |
4652 | break; | |
4653 | ||
252b5132 RH |
4654 | case M_BEQ_I: |
4655 | s = "beq"; | |
4656 | goto beq_i; | |
4657 | case M_BEQL_I: | |
4658 | s = "beql"; | |
4659 | likely = 1; | |
4660 | goto beq_i; | |
4661 | case M_BNE_I: | |
4662 | s = "bne"; | |
4663 | goto beq_i; | |
4664 | case M_BNEL_I: | |
4665 | s = "bnel"; | |
4666 | likely = 1; | |
4667 | beq_i: | |
4668 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4669 | { | |
67c0d1eb | 4670 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
8fc2e39e | 4671 | break; |
252b5132 | 4672 | } |
8fc2e39e | 4673 | used_at = 1; |
67c0d1eb RS |
4674 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4675 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4676 | break; |
4677 | ||
4678 | case M_BGEL: | |
4679 | likely = 1; | |
4680 | case M_BGE: | |
4681 | if (treg == 0) | |
4682 | { | |
67c0d1eb | 4683 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4684 | break; |
252b5132 RH |
4685 | } |
4686 | if (sreg == 0) | |
4687 | { | |
67c0d1eb | 4688 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 4689 | break; |
252b5132 | 4690 | } |
8fc2e39e | 4691 | used_at = 1; |
67c0d1eb RS |
4692 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4693 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4694 | break; |
4695 | ||
4696 | case M_BGTL_I: | |
4697 | likely = 1; | |
4698 | case M_BGT_I: | |
4699 | /* check for > max integer */ | |
4700 | maxnum = 0x7fffffff; | |
ca4e0257 | 4701 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4702 | { |
4703 | maxnum <<= 16; | |
4704 | maxnum |= 0xffff; | |
4705 | maxnum <<= 16; | |
4706 | maxnum |= 0xffff; | |
4707 | } | |
4708 | if (imm_expr.X_op == O_constant | |
4709 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4710 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4711 | { |
4712 | do_false: | |
4713 | /* result is always false */ | |
4714 | if (! likely) | |
67c0d1eb | 4715 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4716 | else |
67c0d1eb | 4717 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
8fc2e39e | 4718 | break; |
252b5132 RH |
4719 | } |
4720 | if (imm_expr.X_op != O_constant) | |
4721 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4722 | ++imm_expr.X_add_number; |
252b5132 RH |
4723 | /* FALLTHROUGH */ |
4724 | case M_BGE_I: | |
4725 | case M_BGEL_I: | |
4726 | if (mask == M_BGEL_I) | |
4727 | likely = 1; | |
4728 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4729 | { | |
67c0d1eb | 4730 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4731 | break; |
252b5132 RH |
4732 | } |
4733 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4734 | { | |
67c0d1eb | 4735 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4736 | break; |
252b5132 RH |
4737 | } |
4738 | maxnum = 0x7fffffff; | |
ca4e0257 | 4739 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4740 | { |
4741 | maxnum <<= 16; | |
4742 | maxnum |= 0xffff; | |
4743 | maxnum <<= 16; | |
4744 | maxnum |= 0xffff; | |
4745 | } | |
4746 | maxnum = - maxnum - 1; | |
4747 | if (imm_expr.X_op == O_constant | |
4748 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4749 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4750 | { |
4751 | do_true: | |
4752 | /* result is always true */ | |
4753 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4754 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 4755 | break; |
252b5132 | 4756 | } |
8fc2e39e | 4757 | used_at = 1; |
67c0d1eb RS |
4758 | set_at (sreg, 0); |
4759 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4760 | break; |
4761 | ||
4762 | case M_BGEUL: | |
4763 | likely = 1; | |
4764 | case M_BGEU: | |
4765 | if (treg == 0) | |
4766 | goto do_true; | |
4767 | if (sreg == 0) | |
4768 | { | |
67c0d1eb | 4769 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4770 | "s,t,p", 0, treg); |
8fc2e39e | 4771 | break; |
252b5132 | 4772 | } |
8fc2e39e | 4773 | used_at = 1; |
67c0d1eb RS |
4774 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4775 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4776 | break; |
4777 | ||
4778 | case M_BGTUL_I: | |
4779 | likely = 1; | |
4780 | case M_BGTU_I: | |
4781 | if (sreg == 0 | |
ca4e0257 | 4782 | || (HAVE_32BIT_GPRS |
252b5132 | 4783 | && imm_expr.X_op == O_constant |
956cd1d6 | 4784 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4785 | goto do_false; |
4786 | if (imm_expr.X_op != O_constant) | |
4787 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4788 | ++imm_expr.X_add_number; |
252b5132 RH |
4789 | /* FALLTHROUGH */ |
4790 | case M_BGEU_I: | |
4791 | case M_BGEUL_I: | |
4792 | if (mask == M_BGEUL_I) | |
4793 | likely = 1; | |
4794 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4795 | goto do_true; | |
4796 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4797 | { | |
67c0d1eb | 4798 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4799 | "s,t,p", sreg, 0); |
8fc2e39e | 4800 | break; |
252b5132 | 4801 | } |
8fc2e39e | 4802 | used_at = 1; |
67c0d1eb RS |
4803 | set_at (sreg, 1); |
4804 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4805 | break; |
4806 | ||
4807 | case M_BGTL: | |
4808 | likely = 1; | |
4809 | case M_BGT: | |
4810 | if (treg == 0) | |
4811 | { | |
67c0d1eb | 4812 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4813 | break; |
252b5132 RH |
4814 | } |
4815 | if (sreg == 0) | |
4816 | { | |
67c0d1eb | 4817 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 4818 | break; |
252b5132 | 4819 | } |
8fc2e39e | 4820 | used_at = 1; |
67c0d1eb RS |
4821 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4822 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4823 | break; |
4824 | ||
4825 | case M_BGTUL: | |
4826 | likely = 1; | |
4827 | case M_BGTU: | |
4828 | if (treg == 0) | |
4829 | { | |
67c0d1eb | 4830 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4831 | "s,t,p", sreg, 0); |
8fc2e39e | 4832 | break; |
252b5132 RH |
4833 | } |
4834 | if (sreg == 0) | |
4835 | goto do_false; | |
8fc2e39e | 4836 | used_at = 1; |
67c0d1eb RS |
4837 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4838 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4839 | break; |
4840 | ||
4841 | case M_BLEL: | |
4842 | likely = 1; | |
4843 | case M_BLE: | |
4844 | if (treg == 0) | |
4845 | { | |
67c0d1eb | 4846 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4847 | break; |
252b5132 RH |
4848 | } |
4849 | if (sreg == 0) | |
4850 | { | |
67c0d1eb | 4851 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 4852 | break; |
252b5132 | 4853 | } |
8fc2e39e | 4854 | used_at = 1; |
67c0d1eb RS |
4855 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4856 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4857 | break; |
4858 | ||
4859 | case M_BLEL_I: | |
4860 | likely = 1; | |
4861 | case M_BLE_I: | |
4862 | maxnum = 0x7fffffff; | |
ca4e0257 | 4863 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4864 | { |
4865 | maxnum <<= 16; | |
4866 | maxnum |= 0xffff; | |
4867 | maxnum <<= 16; | |
4868 | maxnum |= 0xffff; | |
4869 | } | |
4870 | if (imm_expr.X_op == O_constant | |
4871 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4872 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4873 | goto do_true; |
4874 | if (imm_expr.X_op != O_constant) | |
4875 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4876 | ++imm_expr.X_add_number; |
252b5132 RH |
4877 | /* FALLTHROUGH */ |
4878 | case M_BLT_I: | |
4879 | case M_BLTL_I: | |
4880 | if (mask == M_BLTL_I) | |
4881 | likely = 1; | |
4882 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4883 | { | |
67c0d1eb | 4884 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4885 | break; |
252b5132 RH |
4886 | } |
4887 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4888 | { | |
67c0d1eb | 4889 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4890 | break; |
252b5132 | 4891 | } |
8fc2e39e | 4892 | used_at = 1; |
67c0d1eb RS |
4893 | set_at (sreg, 0); |
4894 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4895 | break; |
4896 | ||
4897 | case M_BLEUL: | |
4898 | likely = 1; | |
4899 | case M_BLEU: | |
4900 | if (treg == 0) | |
4901 | { | |
67c0d1eb | 4902 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4903 | "s,t,p", sreg, 0); |
8fc2e39e | 4904 | break; |
252b5132 RH |
4905 | } |
4906 | if (sreg == 0) | |
4907 | goto do_true; | |
8fc2e39e | 4908 | used_at = 1; |
67c0d1eb RS |
4909 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4910 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4911 | break; |
4912 | ||
4913 | case M_BLEUL_I: | |
4914 | likely = 1; | |
4915 | case M_BLEU_I: | |
4916 | if (sreg == 0 | |
ca4e0257 | 4917 | || (HAVE_32BIT_GPRS |
252b5132 | 4918 | && imm_expr.X_op == O_constant |
956cd1d6 | 4919 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4920 | goto do_true; |
4921 | if (imm_expr.X_op != O_constant) | |
4922 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4923 | ++imm_expr.X_add_number; |
252b5132 RH |
4924 | /* FALLTHROUGH */ |
4925 | case M_BLTU_I: | |
4926 | case M_BLTUL_I: | |
4927 | if (mask == M_BLTUL_I) | |
4928 | likely = 1; | |
4929 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4930 | goto do_false; | |
4931 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4932 | { | |
67c0d1eb | 4933 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 | 4934 | "s,t,p", sreg, 0); |
8fc2e39e | 4935 | break; |
252b5132 | 4936 | } |
8fc2e39e | 4937 | used_at = 1; |
67c0d1eb RS |
4938 | set_at (sreg, 1); |
4939 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4940 | break; |
4941 | ||
4942 | case M_BLTL: | |
4943 | likely = 1; | |
4944 | case M_BLT: | |
4945 | if (treg == 0) | |
4946 | { | |
67c0d1eb | 4947 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4948 | break; |
252b5132 RH |
4949 | } |
4950 | if (sreg == 0) | |
4951 | { | |
67c0d1eb | 4952 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 4953 | break; |
252b5132 | 4954 | } |
8fc2e39e | 4955 | used_at = 1; |
67c0d1eb RS |
4956 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4957 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4958 | break; |
4959 | ||
4960 | case M_BLTUL: | |
4961 | likely = 1; | |
4962 | case M_BLTU: | |
4963 | if (treg == 0) | |
4964 | goto do_false; | |
4965 | if (sreg == 0) | |
4966 | { | |
67c0d1eb | 4967 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4968 | "s,t,p", 0, treg); |
8fc2e39e | 4969 | break; |
252b5132 | 4970 | } |
8fc2e39e | 4971 | used_at = 1; |
67c0d1eb RS |
4972 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4973 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4974 | break; |
4975 | ||
5f74bc13 CD |
4976 | case M_DEXT: |
4977 | { | |
4978 | unsigned long pos; | |
4979 | unsigned long size; | |
4980 | ||
4981 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4982 | { | |
4983 | as_bad (_("Unsupported large constant")); | |
4984 | pos = size = 1; | |
4985 | } | |
4986 | else | |
4987 | { | |
4988 | pos = (unsigned long) imm_expr.X_add_number; | |
4989 | size = (unsigned long) imm2_expr.X_add_number; | |
4990 | } | |
4991 | ||
4992 | if (pos > 63) | |
4993 | { | |
4994 | as_bad (_("Improper position (%lu)"), pos); | |
4995 | pos = 1; | |
4996 | } | |
4997 | if (size == 0 || size > 64 | |
4998 | || (pos + size - 1) > 63) | |
4999 | { | |
5000 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
5001 | size, pos); | |
5002 | size = 1; | |
5003 | } | |
5004 | ||
5005 | if (size <= 32 && pos < 32) | |
5006 | { | |
5007 | s = "dext"; | |
5008 | fmt = "t,r,+A,+C"; | |
5009 | } | |
5010 | else if (size <= 32) | |
5011 | { | |
5012 | s = "dextu"; | |
5013 | fmt = "t,r,+E,+H"; | |
5014 | } | |
5015 | else | |
5016 | { | |
5017 | s = "dextm"; | |
5018 | fmt = "t,r,+A,+G"; | |
5019 | } | |
67c0d1eb | 5020 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 | 5021 | } |
8fc2e39e | 5022 | break; |
5f74bc13 CD |
5023 | |
5024 | case M_DINS: | |
5025 | { | |
5026 | unsigned long pos; | |
5027 | unsigned long size; | |
5028 | ||
5029 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
5030 | { | |
5031 | as_bad (_("Unsupported large constant")); | |
5032 | pos = size = 1; | |
5033 | } | |
5034 | else | |
5035 | { | |
5036 | pos = (unsigned long) imm_expr.X_add_number; | |
5037 | size = (unsigned long) imm2_expr.X_add_number; | |
5038 | } | |
5039 | ||
5040 | if (pos > 63) | |
5041 | { | |
5042 | as_bad (_("Improper position (%lu)"), pos); | |
5043 | pos = 1; | |
5044 | } | |
5045 | if (size == 0 || size > 64 | |
5046 | || (pos + size - 1) > 63) | |
5047 | { | |
5048 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
5049 | size, pos); | |
5050 | size = 1; | |
5051 | } | |
5052 | ||
5053 | if (pos < 32 && (pos + size - 1) < 32) | |
5054 | { | |
5055 | s = "dins"; | |
5056 | fmt = "t,r,+A,+B"; | |
5057 | } | |
5058 | else if (pos >= 32) | |
5059 | { | |
5060 | s = "dinsu"; | |
5061 | fmt = "t,r,+E,+F"; | |
5062 | } | |
5063 | else | |
5064 | { | |
5065 | s = "dinsm"; | |
5066 | fmt = "t,r,+A,+F"; | |
5067 | } | |
67c0d1eb RS |
5068 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
5069 | pos + size - 1); | |
5f74bc13 | 5070 | } |
8fc2e39e | 5071 | break; |
5f74bc13 | 5072 | |
252b5132 RH |
5073 | case M_DDIV_3: |
5074 | dbl = 1; | |
5075 | case M_DIV_3: | |
5076 | s = "mflo"; | |
5077 | goto do_div3; | |
5078 | case M_DREM_3: | |
5079 | dbl = 1; | |
5080 | case M_REM_3: | |
5081 | s = "mfhi"; | |
5082 | do_div3: | |
5083 | if (treg == 0) | |
5084 | { | |
5085 | as_warn (_("Divide by zero.")); | |
5086 | if (mips_trap) | |
67c0d1eb | 5087 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 5088 | else |
67c0d1eb | 5089 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5090 | break; |
252b5132 RH |
5091 | } |
5092 | ||
7d10b47d | 5093 | start_noreorder (); |
252b5132 RH |
5094 | if (mips_trap) |
5095 | { | |
67c0d1eb RS |
5096 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
5097 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
5098 | } |
5099 | else | |
5100 | { | |
5101 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5102 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
5103 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
5104 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
5105 | } |
5106 | expr1.X_add_number = -1; | |
8fc2e39e | 5107 | used_at = 1; |
f6a22291 | 5108 | load_register (AT, &expr1, dbl); |
252b5132 | 5109 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 5110 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
5111 | if (dbl) |
5112 | { | |
5113 | expr1.X_add_number = 1; | |
f6a22291 | 5114 | load_register (AT, &expr1, dbl); |
67c0d1eb | 5115 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
5116 | } |
5117 | else | |
5118 | { | |
5119 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 5120 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
5121 | } |
5122 | if (mips_trap) | |
5123 | { | |
67c0d1eb | 5124 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
5125 | /* We want to close the noreorder block as soon as possible, so |
5126 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5127 | end_noreorder (); |
252b5132 RH |
5128 | } |
5129 | else | |
5130 | { | |
5131 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5132 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
5133 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
5134 | |
5135 | /* We want to close the noreorder block as soon as possible, so | |
5136 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5137 | end_noreorder (); |
252b5132 | 5138 | |
67c0d1eb | 5139 | macro_build (NULL, "break", "c", 6); |
252b5132 | 5140 | } |
67c0d1eb | 5141 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
5142 | break; |
5143 | ||
5144 | case M_DIV_3I: | |
5145 | s = "div"; | |
5146 | s2 = "mflo"; | |
5147 | goto do_divi; | |
5148 | case M_DIVU_3I: | |
5149 | s = "divu"; | |
5150 | s2 = "mflo"; | |
5151 | goto do_divi; | |
5152 | case M_REM_3I: | |
5153 | s = "div"; | |
5154 | s2 = "mfhi"; | |
5155 | goto do_divi; | |
5156 | case M_REMU_3I: | |
5157 | s = "divu"; | |
5158 | s2 = "mfhi"; | |
5159 | goto do_divi; | |
5160 | case M_DDIV_3I: | |
5161 | dbl = 1; | |
5162 | s = "ddiv"; | |
5163 | s2 = "mflo"; | |
5164 | goto do_divi; | |
5165 | case M_DDIVU_3I: | |
5166 | dbl = 1; | |
5167 | s = "ddivu"; | |
5168 | s2 = "mflo"; | |
5169 | goto do_divi; | |
5170 | case M_DREM_3I: | |
5171 | dbl = 1; | |
5172 | s = "ddiv"; | |
5173 | s2 = "mfhi"; | |
5174 | goto do_divi; | |
5175 | case M_DREMU_3I: | |
5176 | dbl = 1; | |
5177 | s = "ddivu"; | |
5178 | s2 = "mfhi"; | |
5179 | do_divi: | |
5180 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5181 | { | |
5182 | as_warn (_("Divide by zero.")); | |
5183 | if (mips_trap) | |
67c0d1eb | 5184 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 5185 | else |
67c0d1eb | 5186 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5187 | break; |
252b5132 RH |
5188 | } |
5189 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5190 | { | |
5191 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 5192 | move_register (dreg, sreg); |
252b5132 | 5193 | else |
67c0d1eb | 5194 | move_register (dreg, 0); |
8fc2e39e | 5195 | break; |
252b5132 RH |
5196 | } |
5197 | if (imm_expr.X_op == O_constant | |
5198 | && imm_expr.X_add_number == -1 | |
5199 | && s[strlen (s) - 1] != 'u') | |
5200 | { | |
5201 | if (strcmp (s2, "mflo") == 0) | |
5202 | { | |
67c0d1eb | 5203 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
5204 | } |
5205 | else | |
67c0d1eb | 5206 | move_register (dreg, 0); |
8fc2e39e | 5207 | break; |
252b5132 RH |
5208 | } |
5209 | ||
8fc2e39e | 5210 | used_at = 1; |
67c0d1eb RS |
5211 | load_register (AT, &imm_expr, dbl); |
5212 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
5213 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
5214 | break; |
5215 | ||
5216 | case M_DIVU_3: | |
5217 | s = "divu"; | |
5218 | s2 = "mflo"; | |
5219 | goto do_divu3; | |
5220 | case M_REMU_3: | |
5221 | s = "divu"; | |
5222 | s2 = "mfhi"; | |
5223 | goto do_divu3; | |
5224 | case M_DDIVU_3: | |
5225 | s = "ddivu"; | |
5226 | s2 = "mflo"; | |
5227 | goto do_divu3; | |
5228 | case M_DREMU_3: | |
5229 | s = "ddivu"; | |
5230 | s2 = "mfhi"; | |
5231 | do_divu3: | |
7d10b47d | 5232 | start_noreorder (); |
252b5132 RH |
5233 | if (mips_trap) |
5234 | { | |
67c0d1eb RS |
5235 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
5236 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
5237 | /* We want to close the noreorder block as soon as possible, so |
5238 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5239 | end_noreorder (); |
252b5132 RH |
5240 | } |
5241 | else | |
5242 | { | |
5243 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5244 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
5245 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
5246 | |
5247 | /* We want to close the noreorder block as soon as possible, so | |
5248 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5249 | end_noreorder (); |
67c0d1eb | 5250 | macro_build (NULL, "break", "c", 7); |
252b5132 | 5251 | } |
67c0d1eb | 5252 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 5253 | break; |
252b5132 | 5254 | |
1abe91b1 MR |
5255 | case M_DLCA_AB: |
5256 | dbl = 1; | |
5257 | case M_LCA_AB: | |
5258 | call = 1; | |
5259 | goto do_la; | |
252b5132 RH |
5260 | case M_DLA_AB: |
5261 | dbl = 1; | |
5262 | case M_LA_AB: | |
1abe91b1 | 5263 | do_la: |
252b5132 RH |
5264 | /* Load the address of a symbol into a register. If breg is not |
5265 | zero, we then add a base register to it. */ | |
5266 | ||
3bec30a8 TS |
5267 | if (dbl && HAVE_32BIT_GPRS) |
5268 | as_warn (_("dla used to load 32-bit register")); | |
5269 | ||
c90bbe5b | 5270 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
5271 | as_warn (_("la used to load 64-bit address")); |
5272 | ||
0c11417f MR |
5273 | if (offset_expr.X_op == O_constant |
5274 | && offset_expr.X_add_number >= -0x8000 | |
5275 | && offset_expr.X_add_number < 0x8000) | |
5276 | { | |
aed1a261 | 5277 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 5278 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 5279 | break; |
0c11417f MR |
5280 | } |
5281 | ||
b8285c27 | 5282 | if (!mips_opts.noat && (treg == breg)) |
afdbd6d0 CD |
5283 | { |
5284 | tempreg = AT; | |
5285 | used_at = 1; | |
5286 | } | |
5287 | else | |
5288 | { | |
5289 | tempreg = treg; | |
afdbd6d0 CD |
5290 | } |
5291 | ||
252b5132 RH |
5292 | if (offset_expr.X_op != O_symbol |
5293 | && offset_expr.X_op != O_constant) | |
5294 | { | |
5295 | as_bad (_("expression too complex")); | |
5296 | offset_expr.X_op = O_constant; | |
5297 | } | |
5298 | ||
252b5132 | 5299 | if (offset_expr.X_op == O_constant) |
aed1a261 | 5300 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5301 | else if (mips_pic == NO_PIC) |
5302 | { | |
d6bc6245 | 5303 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 5304 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5305 | Otherwise we want |
5306 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5307 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5308 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 5309 | so we may as well always use the latter form. |
76b3015f | 5310 | |
6caf9ef4 TS |
5311 | With 64bit address space and a usable $at we want |
5312 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5313 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5314 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5315 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5316 | dsll32 $tempreg,0 | |
5317 | daddu $tempreg,$tempreg,$at | |
5318 | ||
5319 | If $at is already in use, we use a path which is suboptimal | |
5320 | on superscalar processors. | |
5321 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5322 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5323 | dsll $tempreg,16 | |
5324 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5325 | dsll $tempreg,16 | |
5326 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
5327 | ||
5328 | For GP relative symbols in 64bit address space we can use | |
5329 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5330 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 5331 | { |
6caf9ef4 TS |
5332 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
5333 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5334 | { | |
5335 | relax_start (offset_expr.X_add_symbol); | |
5336 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5337 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
5338 | relax_switch (); | |
5339 | } | |
d6bc6245 | 5340 | |
b8285c27 | 5341 | if (used_at == 0 && !mips_opts.noat) |
98d3f06f | 5342 | { |
67c0d1eb | 5343 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5344 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5345 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5346 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 5347 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5348 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 5349 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5350 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
5351 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
5352 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
5353 | used_at = 1; |
5354 | } | |
5355 | else | |
5356 | { | |
67c0d1eb | 5357 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5358 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5359 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5360 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
5361 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5362 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5363 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
5364 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5365 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5366 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 5367 | } |
6caf9ef4 TS |
5368 | |
5369 | if (mips_relax.sequence) | |
5370 | relax_end (); | |
98d3f06f KH |
5371 | } |
5372 | else | |
5373 | { | |
5374 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 5375 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 5376 | { |
4d7206a2 | 5377 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5378 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5379 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5380 | relax_switch (); |
98d3f06f | 5381 | } |
6943caf0 ILT |
5382 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
5383 | as_bad (_("offset too large")); | |
67c0d1eb RS |
5384 | macro_build_lui (&offset_expr, tempreg); |
5385 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5386 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5387 | if (mips_relax.sequence) |
5388 | relax_end (); | |
98d3f06f | 5389 | } |
252b5132 | 5390 | } |
0a44bf69 | 5391 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 5392 | { |
9117d219 NC |
5393 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5394 | ||
252b5132 RH |
5395 | /* If this is a reference to an external symbol, and there |
5396 | is no constant, we want | |
5397 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5398 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5399 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5400 | For a local symbol, we want |
5401 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5402 | nop | |
5403 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5404 | ||
5405 | If we have a small constant, and this is a reference to | |
5406 | an external symbol, we want | |
5407 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5408 | nop | |
5409 | addiu $tempreg,$tempreg,<constant> | |
5410 | For a local symbol, we want the same instruction | |
5411 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5412 | addiu instruction. | |
5413 | ||
5414 | If we have a large constant, and this is a reference to | |
5415 | an external symbol, we want | |
5416 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5417 | lui $at,<hiconstant> | |
5418 | addiu $at,$at,<loconstant> | |
5419 | addu $tempreg,$tempreg,$at | |
5420 | For a local symbol, we want the same instruction | |
5421 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5422 | addiu instruction. |
ed6fb7bd SC |
5423 | */ |
5424 | ||
4d7206a2 | 5425 | if (offset_expr.X_add_number == 0) |
252b5132 | 5426 | { |
0a44bf69 RS |
5427 | if (mips_pic == SVR4_PIC |
5428 | && breg == 0 | |
5429 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
5430 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
5431 | ||
5432 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5433 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5434 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5435 | if (breg != 0) |
252b5132 RH |
5436 | { |
5437 | /* We're going to put in an addu instruction using | |
5438 | tempreg, so we may as well insert the nop right | |
5439 | now. */ | |
269137b2 | 5440 | load_delay_nop (); |
252b5132 | 5441 | } |
4d7206a2 | 5442 | relax_switch (); |
67c0d1eb RS |
5443 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5444 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5445 | load_delay_nop (); |
67c0d1eb RS |
5446 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5447 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5448 | relax_end (); |
252b5132 RH |
5449 | /* FIXME: If breg == 0, and the next instruction uses |
5450 | $tempreg, then if this variant case is used an extra | |
5451 | nop will be generated. */ | |
5452 | } | |
4d7206a2 RS |
5453 | else if (offset_expr.X_add_number >= -0x8000 |
5454 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5455 | { |
67c0d1eb | 5456 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5457 | load_delay_nop (); |
67c0d1eb | 5458 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5459 | } |
5460 | else | |
5461 | { | |
4d7206a2 RS |
5462 | expr1.X_add_number = offset_expr.X_add_number; |
5463 | offset_expr.X_add_number = | |
5464 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5465 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5466 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5467 | /* If we are going to add in a base register, and the |
5468 | target register and the base register are the same, | |
5469 | then we are using AT as a temporary register. Since | |
5470 | we want to load the constant into AT, we add our | |
5471 | current AT (from the global offset table) and the | |
5472 | register into the register now, and pretend we were | |
5473 | not using a base register. */ | |
67c0d1eb | 5474 | if (breg == treg) |
252b5132 | 5475 | { |
269137b2 | 5476 | load_delay_nop (); |
67c0d1eb | 5477 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5478 | treg, AT, breg); |
252b5132 RH |
5479 | breg = 0; |
5480 | tempreg = treg; | |
252b5132 | 5481 | } |
f6a22291 | 5482 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5483 | used_at = 1; |
5484 | } | |
5485 | } | |
0a44bf69 | 5486 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 5487 | { |
67c0d1eb | 5488 | int add_breg_early = 0; |
f5040a92 AO |
5489 | |
5490 | /* If this is a reference to an external, and there is no | |
5491 | constant, or local symbol (*), with or without a | |
5492 | constant, we want | |
5493 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5494 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5495 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5496 | ||
5497 | If we have a small constant, and this is a reference to | |
5498 | an external symbol, we want | |
5499 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5500 | addiu $tempreg,$tempreg,<constant> | |
5501 | ||
5502 | If we have a large constant, and this is a reference to | |
5503 | an external symbol, we want | |
5504 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5505 | lui $at,<hiconstant> | |
5506 | addiu $at,$at,<loconstant> | |
5507 | addu $tempreg,$tempreg,$at | |
5508 | ||
5509 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5510 | local symbols, even though it introduces an additional | |
5511 | instruction. */ | |
5512 | ||
f5040a92 AO |
5513 | if (offset_expr.X_add_number) |
5514 | { | |
4d7206a2 | 5515 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5516 | offset_expr.X_add_number = 0; |
5517 | ||
4d7206a2 | 5518 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5519 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5520 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5521 | |
5522 | if (expr1.X_add_number >= -0x8000 | |
5523 | && expr1.X_add_number < 0x8000) | |
5524 | { | |
67c0d1eb RS |
5525 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5526 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5527 | } |
ecd13cd3 | 5528 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5529 | { |
5530 | int dreg; | |
5531 | ||
5532 | /* If we are going to add in a base register, and the | |
5533 | target register and the base register are the same, | |
5534 | then we are using AT as a temporary register. Since | |
5535 | we want to load the constant into AT, we add our | |
5536 | current AT (from the global offset table) and the | |
5537 | register into the register now, and pretend we were | |
5538 | not using a base register. */ | |
5539 | if (breg != treg) | |
5540 | dreg = tempreg; | |
5541 | else | |
5542 | { | |
5543 | assert (tempreg == AT); | |
67c0d1eb RS |
5544 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5545 | treg, AT, breg); | |
f5040a92 | 5546 | dreg = treg; |
67c0d1eb | 5547 | add_breg_early = 1; |
f5040a92 AO |
5548 | } |
5549 | ||
f6a22291 | 5550 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5551 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5552 | dreg, dreg, AT); |
f5040a92 | 5553 | |
f5040a92 AO |
5554 | used_at = 1; |
5555 | } | |
5556 | else | |
5557 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5558 | ||
4d7206a2 | 5559 | relax_switch (); |
f5040a92 AO |
5560 | offset_expr.X_add_number = expr1.X_add_number; |
5561 | ||
67c0d1eb RS |
5562 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5563 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5564 | if (add_breg_early) | |
f5040a92 | 5565 | { |
67c0d1eb | 5566 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5567 | treg, tempreg, breg); |
f5040a92 AO |
5568 | breg = 0; |
5569 | tempreg = treg; | |
5570 | } | |
4d7206a2 | 5571 | relax_end (); |
f5040a92 | 5572 | } |
4d7206a2 | 5573 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5574 | { |
4d7206a2 | 5575 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5576 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5577 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5578 | relax_switch (); |
67c0d1eb RS |
5579 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5580 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5581 | relax_end (); |
f5040a92 | 5582 | } |
4d7206a2 | 5583 | else |
f5040a92 | 5584 | { |
67c0d1eb RS |
5585 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5586 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5587 | } |
5588 | } | |
0a44bf69 | 5589 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 5590 | { |
67c0d1eb | 5591 | int gpdelay; |
9117d219 NC |
5592 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5593 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5594 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5595 | |
5596 | /* This is the large GOT case. If this is a reference to an | |
5597 | external symbol, and there is no constant, we want | |
5598 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5599 | addu $tempreg,$tempreg,$gp | |
5600 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5601 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5602 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5603 | addu $tempreg,$tempreg,$gp | |
5604 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5605 | For a local symbol, we want |
5606 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5607 | nop | |
5608 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5609 | ||
5610 | If we have a small constant, and this is a reference to | |
5611 | an external symbol, we want | |
5612 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5613 | addu $tempreg,$tempreg,$gp | |
5614 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5615 | nop | |
5616 | addiu $tempreg,$tempreg,<constant> | |
5617 | For a local symbol, we want | |
5618 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5619 | nop | |
5620 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5621 | ||
5622 | If we have a large constant, and this is a reference to | |
5623 | an external symbol, we want | |
5624 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5625 | addu $tempreg,$tempreg,$gp | |
5626 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5627 | lui $at,<hiconstant> | |
5628 | addiu $at,$at,<loconstant> | |
5629 | addu $tempreg,$tempreg,$at | |
5630 | For a local symbol, we want | |
5631 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5632 | lui $at,<hiconstant> | |
5633 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5634 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5635 | */ |
438c16b8 | 5636 | |
252b5132 RH |
5637 | expr1.X_add_number = offset_expr.X_add_number; |
5638 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5639 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5640 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5641 | if (expr1.X_add_number == 0 && breg == 0 |
5642 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5643 | { |
5644 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5645 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5646 | } | |
67c0d1eb RS |
5647 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5648 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5649 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5650 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5651 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5652 | if (expr1.X_add_number == 0) |
5653 | { | |
67c0d1eb | 5654 | if (breg != 0) |
252b5132 RH |
5655 | { |
5656 | /* We're going to put in an addu instruction using | |
5657 | tempreg, so we may as well insert the nop right | |
5658 | now. */ | |
269137b2 | 5659 | load_delay_nop (); |
252b5132 | 5660 | } |
252b5132 RH |
5661 | } |
5662 | else if (expr1.X_add_number >= -0x8000 | |
5663 | && expr1.X_add_number < 0x8000) | |
5664 | { | |
269137b2 | 5665 | load_delay_nop (); |
67c0d1eb | 5666 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5667 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5668 | } |
5669 | else | |
5670 | { | |
67c0d1eb | 5671 | int dreg; |
252b5132 RH |
5672 | |
5673 | /* If we are going to add in a base register, and the | |
5674 | target register and the base register are the same, | |
5675 | then we are using AT as a temporary register. Since | |
5676 | we want to load the constant into AT, we add our | |
5677 | current AT (from the global offset table) and the | |
5678 | register into the register now, and pretend we were | |
5679 | not using a base register. */ | |
5680 | if (breg != treg) | |
67c0d1eb | 5681 | dreg = tempreg; |
252b5132 RH |
5682 | else |
5683 | { | |
5684 | assert (tempreg == AT); | |
269137b2 | 5685 | load_delay_nop (); |
67c0d1eb | 5686 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5687 | treg, AT, breg); |
252b5132 | 5688 | dreg = treg; |
252b5132 RH |
5689 | } |
5690 | ||
f6a22291 | 5691 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5692 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5693 | |
252b5132 RH |
5694 | used_at = 1; |
5695 | } | |
4d7206a2 RS |
5696 | offset_expr.X_add_number = |
5697 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5698 | relax_switch (); | |
252b5132 | 5699 | |
67c0d1eb | 5700 | if (gpdelay) |
252b5132 RH |
5701 | { |
5702 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5703 | the first instruction on the main stream does not. */ |
67c0d1eb | 5704 | macro_build (NULL, "nop", ""); |
252b5132 | 5705 | } |
ed6fb7bd | 5706 | |
67c0d1eb RS |
5707 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5708 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5709 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5710 | && expr1.X_add_number < 0x8000) |
5711 | { | |
269137b2 | 5712 | load_delay_nop (); |
67c0d1eb RS |
5713 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5714 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5715 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5716 | register, the external symbol case ended with a load, |
5717 | so if the symbol turns out to not be external, and | |
5718 | the next instruction uses tempreg, an unnecessary nop | |
5719 | will be inserted. */ | |
252b5132 RH |
5720 | } |
5721 | else | |
5722 | { | |
5723 | if (breg == treg) | |
5724 | { | |
5725 | /* We must add in the base register now, as in the | |
f5040a92 | 5726 | external symbol case. */ |
252b5132 | 5727 | assert (tempreg == AT); |
269137b2 | 5728 | load_delay_nop (); |
67c0d1eb | 5729 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5730 | treg, AT, breg); |
252b5132 RH |
5731 | tempreg = treg; |
5732 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5733 | it in in both cases. */ |
252b5132 RH |
5734 | breg = 0; |
5735 | } | |
5736 | ||
67c0d1eb RS |
5737 | macro_build_lui (&expr1, AT); |
5738 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5739 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5740 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5741 | tempreg, tempreg, AT); |
8fc2e39e | 5742 | used_at = 1; |
252b5132 | 5743 | } |
4d7206a2 | 5744 | relax_end (); |
252b5132 | 5745 | } |
0a44bf69 | 5746 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 5747 | { |
f5040a92 AO |
5748 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5749 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5750 | int add_breg_early = 0; |
f5040a92 AO |
5751 | |
5752 | /* This is the large GOT case. If this is a reference to an | |
5753 | external symbol, and there is no constant, we want | |
5754 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5755 | add $tempreg,$tempreg,$gp | |
5756 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5757 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5758 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5759 | add $tempreg,$tempreg,$gp | |
5760 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5761 | ||
5762 | If we have a small constant, and this is a reference to | |
5763 | an external symbol, we want | |
5764 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5765 | add $tempreg,$tempreg,$gp | |
5766 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5767 | addi $tempreg,$tempreg,<constant> | |
5768 | ||
5769 | If we have a large constant, and this is a reference to | |
5770 | an external symbol, we want | |
5771 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5772 | addu $tempreg,$tempreg,$gp | |
5773 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5774 | lui $at,<hiconstant> | |
5775 | addi $at,$at,<loconstant> | |
5776 | add $tempreg,$tempreg,$at | |
5777 | ||
5778 | If we have NewABI, and we know it's a local symbol, we want | |
5779 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5780 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5781 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5782 | ||
4d7206a2 | 5783 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5784 | |
4d7206a2 | 5785 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5786 | offset_expr.X_add_number = 0; |
5787 | ||
1abe91b1 MR |
5788 | if (expr1.X_add_number == 0 && breg == 0 |
5789 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5790 | { |
5791 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5792 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5793 | } | |
67c0d1eb RS |
5794 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5795 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5796 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5797 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5798 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5799 | |
5800 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5801 | ; |
f5040a92 AO |
5802 | else if (expr1.X_add_number >= -0x8000 |
5803 | && expr1.X_add_number < 0x8000) | |
5804 | { | |
67c0d1eb | 5805 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5806 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5807 | } |
ecd13cd3 | 5808 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5809 | { |
5810 | int dreg; | |
5811 | ||
5812 | /* If we are going to add in a base register, and the | |
5813 | target register and the base register are the same, | |
5814 | then we are using AT as a temporary register. Since | |
5815 | we want to load the constant into AT, we add our | |
5816 | current AT (from the global offset table) and the | |
5817 | register into the register now, and pretend we were | |
5818 | not using a base register. */ | |
5819 | if (breg != treg) | |
5820 | dreg = tempreg; | |
5821 | else | |
5822 | { | |
5823 | assert (tempreg == AT); | |
67c0d1eb | 5824 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5825 | treg, AT, breg); |
f5040a92 | 5826 | dreg = treg; |
67c0d1eb | 5827 | add_breg_early = 1; |
f5040a92 AO |
5828 | } |
5829 | ||
f6a22291 | 5830 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5831 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5832 | |
f5040a92 AO |
5833 | used_at = 1; |
5834 | } | |
5835 | else | |
5836 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5837 | ||
4d7206a2 | 5838 | relax_switch (); |
f5040a92 | 5839 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5840 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5841 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5842 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5843 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5844 | if (add_breg_early) | |
f5040a92 | 5845 | { |
67c0d1eb | 5846 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5847 | treg, tempreg, breg); |
f5040a92 AO |
5848 | breg = 0; |
5849 | tempreg = treg; | |
5850 | } | |
4d7206a2 | 5851 | relax_end (); |
f5040a92 | 5852 | } |
252b5132 RH |
5853 | else |
5854 | abort (); | |
5855 | ||
5856 | if (breg != 0) | |
aed1a261 | 5857 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
5858 | break; |
5859 | ||
5860 | case M_J_A: | |
5861 | /* The j instruction may not be used in PIC code, since it | |
5862 | requires an absolute address. We convert it to a b | |
5863 | instruction. */ | |
5864 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5865 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5866 | else |
67c0d1eb | 5867 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5868 | break; |
252b5132 RH |
5869 | |
5870 | /* The jal instructions must be handled as macros because when | |
5871 | generating PIC code they expand to multi-instruction | |
5872 | sequences. Normally they are simple instructions. */ | |
5873 | case M_JAL_1: | |
5874 | dreg = RA; | |
5875 | /* Fall through. */ | |
5876 | case M_JAL_2: | |
3e722fb5 | 5877 | if (mips_pic == NO_PIC) |
67c0d1eb | 5878 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 5879 | else |
252b5132 RH |
5880 | { |
5881 | if (sreg != PIC_CALL_REG) | |
5882 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5883 | |
67c0d1eb | 5884 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 5885 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 5886 | { |
6478892d TS |
5887 | if (mips_cprestore_offset < 0) |
5888 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5889 | else | |
5890 | { | |
7a621144 DJ |
5891 | if (! mips_frame_reg_valid) |
5892 | { | |
5893 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5894 | /* Quiet this warning. */ | |
5895 | mips_frame_reg_valid = 1; | |
5896 | } | |
5897 | if (! mips_cprestore_valid) | |
5898 | { | |
5899 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5900 | /* Quiet this warning. */ | |
5901 | mips_cprestore_valid = 1; | |
5902 | } | |
6478892d | 5903 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5904 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5905 | mips_gp_register, |
256ab948 TS |
5906 | mips_frame_reg, |
5907 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5908 | } |
252b5132 RH |
5909 | } |
5910 | } | |
252b5132 | 5911 | |
8fc2e39e | 5912 | break; |
252b5132 RH |
5913 | |
5914 | case M_JAL_A: | |
5915 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5916 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5917 | else if (mips_pic == SVR4_PIC) |
5918 | { | |
5919 | /* If this is a reference to an external symbol, and we are | |
5920 | using a small GOT, we want | |
5921 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5922 | nop | |
f9419b05 | 5923 | jalr $ra,$25 |
252b5132 RH |
5924 | nop |
5925 | lw $gp,cprestore($sp) | |
5926 | The cprestore value is set using the .cprestore | |
5927 | pseudo-op. If we are using a big GOT, we want | |
5928 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5929 | addu $25,$25,$gp | |
5930 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5931 | nop | |
f9419b05 | 5932 | jalr $ra,$25 |
252b5132 RH |
5933 | nop |
5934 | lw $gp,cprestore($sp) | |
5935 | If the symbol is not external, we want | |
5936 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5937 | nop | |
5938 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5939 | jalr $ra,$25 |
252b5132 | 5940 | nop |
438c16b8 | 5941 | lw $gp,cprestore($sp) |
f5040a92 AO |
5942 | |
5943 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5944 | sequences above, minus nops, unless the symbol is local, | |
5945 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5946 | GOT_DISP. */ | |
438c16b8 | 5947 | if (HAVE_NEWABI) |
252b5132 | 5948 | { |
f5040a92 AO |
5949 | if (! mips_big_got) |
5950 | { | |
4d7206a2 | 5951 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5952 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5953 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5954 | mips_gp_register); |
4d7206a2 | 5955 | relax_switch (); |
67c0d1eb RS |
5956 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5957 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5958 | mips_gp_register); |
5959 | relax_end (); | |
f5040a92 AO |
5960 | } |
5961 | else | |
5962 | { | |
4d7206a2 | 5963 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5964 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5965 | BFD_RELOC_MIPS_CALL_HI16); | |
5966 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5967 | PIC_CALL_REG, mips_gp_register); | |
5968 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5969 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5970 | PIC_CALL_REG); | |
4d7206a2 | 5971 | relax_switch (); |
67c0d1eb RS |
5972 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5973 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
5974 | mips_gp_register); | |
5975 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5976 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 5977 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 5978 | relax_end (); |
f5040a92 | 5979 | } |
684022ea | 5980 | |
67c0d1eb | 5981 | macro_build_jalr (&offset_expr); |
252b5132 RH |
5982 | } |
5983 | else | |
5984 | { | |
4d7206a2 | 5985 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
5986 | if (! mips_big_got) |
5987 | { | |
67c0d1eb RS |
5988 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5989 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 5990 | mips_gp_register); |
269137b2 | 5991 | load_delay_nop (); |
4d7206a2 | 5992 | relax_switch (); |
438c16b8 | 5993 | } |
252b5132 | 5994 | else |
252b5132 | 5995 | { |
67c0d1eb RS |
5996 | int gpdelay; |
5997 | ||
5998 | gpdelay = reg_needs_delay (mips_gp_register); | |
5999 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
6000 | BFD_RELOC_MIPS_CALL_HI16); | |
6001 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6002 | PIC_CALL_REG, mips_gp_register); | |
6003 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6004 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6005 | PIC_CALL_REG); | |
269137b2 | 6006 | load_delay_nop (); |
4d7206a2 | 6007 | relax_switch (); |
67c0d1eb RS |
6008 | if (gpdelay) |
6009 | macro_build (NULL, "nop", ""); | |
252b5132 | 6010 | } |
67c0d1eb RS |
6011 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6012 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 6013 | mips_gp_register); |
269137b2 | 6014 | load_delay_nop (); |
67c0d1eb RS |
6015 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6016 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 6017 | relax_end (); |
67c0d1eb | 6018 | macro_build_jalr (&offset_expr); |
438c16b8 | 6019 | |
6478892d TS |
6020 | if (mips_cprestore_offset < 0) |
6021 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6022 | else | |
6023 | { | |
7a621144 DJ |
6024 | if (! mips_frame_reg_valid) |
6025 | { | |
6026 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6027 | /* Quiet this warning. */ | |
6028 | mips_frame_reg_valid = 1; | |
6029 | } | |
6030 | if (! mips_cprestore_valid) | |
6031 | { | |
6032 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6033 | /* Quiet this warning. */ | |
6034 | mips_cprestore_valid = 1; | |
6035 | } | |
6478892d | 6036 | if (mips_opts.noreorder) |
67c0d1eb | 6037 | macro_build (NULL, "nop", ""); |
6478892d | 6038 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6039 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6040 | mips_gp_register, |
256ab948 TS |
6041 | mips_frame_reg, |
6042 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6043 | } |
252b5132 RH |
6044 | } |
6045 | } | |
0a44bf69 RS |
6046 | else if (mips_pic == VXWORKS_PIC) |
6047 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
6048 | else |
6049 | abort (); | |
6050 | ||
8fc2e39e | 6051 | break; |
252b5132 RH |
6052 | |
6053 | case M_LB_AB: | |
6054 | s = "lb"; | |
6055 | goto ld; | |
6056 | case M_LBU_AB: | |
6057 | s = "lbu"; | |
6058 | goto ld; | |
6059 | case M_LH_AB: | |
6060 | s = "lh"; | |
6061 | goto ld; | |
6062 | case M_LHU_AB: | |
6063 | s = "lhu"; | |
6064 | goto ld; | |
6065 | case M_LW_AB: | |
6066 | s = "lw"; | |
6067 | goto ld; | |
6068 | case M_LWC0_AB: | |
6069 | s = "lwc0"; | |
bdaaa2e1 | 6070 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6071 | coproc = 1; |
6072 | goto ld; | |
6073 | case M_LWC1_AB: | |
6074 | s = "lwc1"; | |
bdaaa2e1 | 6075 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6076 | coproc = 1; |
6077 | goto ld; | |
6078 | case M_LWC2_AB: | |
6079 | s = "lwc2"; | |
bdaaa2e1 | 6080 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6081 | coproc = 1; |
6082 | goto ld; | |
6083 | case M_LWC3_AB: | |
6084 | s = "lwc3"; | |
bdaaa2e1 | 6085 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6086 | coproc = 1; |
6087 | goto ld; | |
6088 | case M_LWL_AB: | |
6089 | s = "lwl"; | |
6090 | lr = 1; | |
6091 | goto ld; | |
6092 | case M_LWR_AB: | |
6093 | s = "lwr"; | |
6094 | lr = 1; | |
6095 | goto ld; | |
6096 | case M_LDC1_AB: | |
fef14a42 | 6097 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6098 | { |
6099 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6100 | break; |
252b5132 RH |
6101 | } |
6102 | s = "ldc1"; | |
bdaaa2e1 | 6103 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6104 | coproc = 1; |
6105 | goto ld; | |
6106 | case M_LDC2_AB: | |
6107 | s = "ldc2"; | |
bdaaa2e1 | 6108 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6109 | coproc = 1; |
6110 | goto ld; | |
6111 | case M_LDC3_AB: | |
6112 | s = "ldc3"; | |
bdaaa2e1 | 6113 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6114 | coproc = 1; |
6115 | goto ld; | |
6116 | case M_LDL_AB: | |
6117 | s = "ldl"; | |
6118 | lr = 1; | |
6119 | goto ld; | |
6120 | case M_LDR_AB: | |
6121 | s = "ldr"; | |
6122 | lr = 1; | |
6123 | goto ld; | |
6124 | case M_LL_AB: | |
6125 | s = "ll"; | |
6126 | goto ld; | |
6127 | case M_LLD_AB: | |
6128 | s = "lld"; | |
6129 | goto ld; | |
6130 | case M_LWU_AB: | |
6131 | s = "lwu"; | |
6132 | ld: | |
8fc2e39e | 6133 | if (breg == treg || coproc || lr) |
252b5132 RH |
6134 | { |
6135 | tempreg = AT; | |
6136 | used_at = 1; | |
6137 | } | |
6138 | else | |
6139 | { | |
6140 | tempreg = treg; | |
252b5132 RH |
6141 | } |
6142 | goto ld_st; | |
6143 | case M_SB_AB: | |
6144 | s = "sb"; | |
6145 | goto st; | |
6146 | case M_SH_AB: | |
6147 | s = "sh"; | |
6148 | goto st; | |
6149 | case M_SW_AB: | |
6150 | s = "sw"; | |
6151 | goto st; | |
6152 | case M_SWC0_AB: | |
6153 | s = "swc0"; | |
bdaaa2e1 | 6154 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6155 | coproc = 1; |
6156 | goto st; | |
6157 | case M_SWC1_AB: | |
6158 | s = "swc1"; | |
bdaaa2e1 | 6159 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6160 | coproc = 1; |
6161 | goto st; | |
6162 | case M_SWC2_AB: | |
6163 | s = "swc2"; | |
bdaaa2e1 | 6164 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6165 | coproc = 1; |
6166 | goto st; | |
6167 | case M_SWC3_AB: | |
6168 | s = "swc3"; | |
bdaaa2e1 | 6169 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6170 | coproc = 1; |
6171 | goto st; | |
6172 | case M_SWL_AB: | |
6173 | s = "swl"; | |
6174 | goto st; | |
6175 | case M_SWR_AB: | |
6176 | s = "swr"; | |
6177 | goto st; | |
6178 | case M_SC_AB: | |
6179 | s = "sc"; | |
6180 | goto st; | |
6181 | case M_SCD_AB: | |
6182 | s = "scd"; | |
6183 | goto st; | |
d43b4baf TS |
6184 | case M_CACHE_AB: |
6185 | s = "cache"; | |
6186 | goto st; | |
252b5132 | 6187 | case M_SDC1_AB: |
fef14a42 | 6188 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6189 | { |
6190 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6191 | break; |
252b5132 RH |
6192 | } |
6193 | s = "sdc1"; | |
6194 | coproc = 1; | |
bdaaa2e1 | 6195 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6196 | goto st; |
6197 | case M_SDC2_AB: | |
6198 | s = "sdc2"; | |
bdaaa2e1 | 6199 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6200 | coproc = 1; |
6201 | goto st; | |
6202 | case M_SDC3_AB: | |
6203 | s = "sdc3"; | |
bdaaa2e1 | 6204 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6205 | coproc = 1; |
6206 | goto st; | |
6207 | case M_SDL_AB: | |
6208 | s = "sdl"; | |
6209 | goto st; | |
6210 | case M_SDR_AB: | |
6211 | s = "sdr"; | |
6212 | st: | |
8fc2e39e TS |
6213 | tempreg = AT; |
6214 | used_at = 1; | |
252b5132 | 6215 | ld_st: |
bdaaa2e1 | 6216 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6217 | if (mask == M_LWC1_AB |
6218 | || mask == M_SWC1_AB | |
6219 | || mask == M_LDC1_AB | |
6220 | || mask == M_SDC1_AB | |
6221 | || mask == M_L_DAB | |
6222 | || mask == M_S_DAB) | |
6223 | fmt = "T,o(b)"; | |
d43b4baf TS |
6224 | else if (mask == M_CACHE_AB) |
6225 | fmt = "k,o(b)"; | |
252b5132 RH |
6226 | else if (coproc) |
6227 | fmt = "E,o(b)"; | |
6228 | else | |
6229 | fmt = "t,o(b)"; | |
6230 | ||
6231 | if (offset_expr.X_op != O_constant | |
6232 | && offset_expr.X_op != O_symbol) | |
6233 | { | |
6234 | as_bad (_("expression too complex")); | |
6235 | offset_expr.X_op = O_constant; | |
6236 | } | |
6237 | ||
2051e8c4 MR |
6238 | if (HAVE_32BIT_ADDRESSES |
6239 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6240 | { |
6241 | char value [32]; | |
6242 | ||
6243 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6244 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6245 | } |
2051e8c4 | 6246 | |
252b5132 RH |
6247 | /* A constant expression in PIC code can be handled just as it |
6248 | is in non PIC code. */ | |
aed1a261 RS |
6249 | if (offset_expr.X_op == O_constant) |
6250 | { | |
aed1a261 RS |
6251 | expr1.X_add_number = ((offset_expr.X_add_number + 0x8000) |
6252 | & ~(bfd_vma) 0xffff); | |
2051e8c4 | 6253 | normalize_address_expr (&expr1); |
aed1a261 RS |
6254 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
6255 | if (breg != 0) | |
6256 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6257 | tempreg, tempreg, breg); | |
6258 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); | |
6259 | } | |
6260 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
6261 | { |
6262 | /* If this is a reference to a GP relative symbol, and there | |
6263 | is no base register, we want | |
cdf6fd85 | 6264 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6265 | Otherwise, if there is no base register, we want |
6266 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6267 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6268 | If we have a constant, we need two instructions anyhow, | |
6269 | so we always use the latter form. | |
6270 | ||
6271 | If we have a base register, and this is a reference to a | |
6272 | GP relative symbol, we want | |
6273 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6274 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6275 | Otherwise we want |
6276 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6277 | addu $tempreg,$tempreg,$breg | |
6278 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 6279 | With a constant we always use the latter case. |
76b3015f | 6280 | |
d6bc6245 TS |
6281 | With 64bit address space and no base register and $at usable, |
6282 | we want | |
6283 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6284 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6285 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6286 | dsll32 $tempreg,0 | |
6287 | daddu $tempreg,$at | |
6288 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6289 | If we have a base register, we want | |
6290 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6291 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6292 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6293 | daddu $at,$breg | |
6294 | dsll32 $tempreg,0 | |
6295 | daddu $tempreg,$at | |
6296 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6297 | ||
6298 | Without $at we can't generate the optimal path for superscalar | |
6299 | processors here since this would require two temporary registers. | |
6300 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6301 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6302 | dsll $tempreg,16 | |
6303 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6304 | dsll $tempreg,16 | |
6305 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6306 | If we have a base register, we want | |
6307 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6308 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6309 | dsll $tempreg,16 | |
6310 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6311 | dsll $tempreg,16 | |
6312 | daddu $tempreg,$tempreg,$breg | |
6313 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 6314 | |
6caf9ef4 | 6315 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
6316 | the same sequence as in 32bit address space. */ |
6317 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 6318 | { |
aed1a261 | 6319 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
6320 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6321 | { | |
6322 | relax_start (offset_expr.X_add_symbol); | |
6323 | if (breg == 0) | |
6324 | { | |
6325 | macro_build (&offset_expr, s, fmt, treg, | |
6326 | BFD_RELOC_GPREL16, mips_gp_register); | |
6327 | } | |
6328 | else | |
6329 | { | |
6330 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6331 | tempreg, breg, mips_gp_register); | |
6332 | macro_build (&offset_expr, s, fmt, treg, | |
6333 | BFD_RELOC_GPREL16, tempreg); | |
6334 | } | |
6335 | relax_switch (); | |
6336 | } | |
d6bc6245 | 6337 | |
b8285c27 | 6338 | if (used_at == 0 && !mips_opts.noat) |
d6bc6245 | 6339 | { |
67c0d1eb RS |
6340 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6341 | BFD_RELOC_MIPS_HIGHEST); | |
6342 | macro_build (&offset_expr, "lui", "t,u", AT, | |
6343 | BFD_RELOC_HI16_S); | |
6344 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6345 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 6346 | if (breg != 0) |
67c0d1eb RS |
6347 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
6348 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
6349 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
6350 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
6351 | tempreg); | |
d6bc6245 TS |
6352 | used_at = 1; |
6353 | } | |
6354 | else | |
6355 | { | |
67c0d1eb RS |
6356 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6357 | BFD_RELOC_MIPS_HIGHEST); | |
6358 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6359 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6360 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6361 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6362 | tempreg, BFD_RELOC_HI16_S); | |
6363 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6364 | if (breg != 0) |
67c0d1eb | 6365 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6366 | tempreg, tempreg, breg); |
67c0d1eb | 6367 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6368 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 6369 | } |
6caf9ef4 TS |
6370 | |
6371 | if (mips_relax.sequence) | |
6372 | relax_end (); | |
8fc2e39e | 6373 | break; |
d6bc6245 | 6374 | } |
256ab948 | 6375 | |
252b5132 RH |
6376 | if (breg == 0) |
6377 | { | |
67c0d1eb | 6378 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6379 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6380 | { |
4d7206a2 | 6381 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6382 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6383 | mips_gp_register); | |
4d7206a2 | 6384 | relax_switch (); |
252b5132 | 6385 | } |
67c0d1eb RS |
6386 | macro_build_lui (&offset_expr, tempreg); |
6387 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6388 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6389 | if (mips_relax.sequence) |
6390 | relax_end (); | |
252b5132 RH |
6391 | } |
6392 | else | |
6393 | { | |
67c0d1eb | 6394 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6395 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6396 | { |
4d7206a2 | 6397 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6398 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6399 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6400 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6401 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6402 | relax_switch (); |
252b5132 | 6403 | } |
67c0d1eb RS |
6404 | macro_build_lui (&offset_expr, tempreg); |
6405 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6406 | tempreg, tempreg, breg); |
67c0d1eb | 6407 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6408 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6409 | if (mips_relax.sequence) |
6410 | relax_end (); | |
252b5132 RH |
6411 | } |
6412 | } | |
0a44bf69 | 6413 | else if (!mips_big_got) |
252b5132 | 6414 | { |
ed6fb7bd | 6415 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6416 | |
252b5132 RH |
6417 | /* If this is a reference to an external symbol, we want |
6418 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6419 | nop | |
6420 | <op> $treg,0($tempreg) | |
6421 | Otherwise we want | |
6422 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6423 | nop | |
6424 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6425 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6426 | |
6427 | For NewABI, we want | |
6428 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6429 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6430 | ||
252b5132 RH |
6431 | If there is a base register, we add it to $tempreg before |
6432 | the <op>. If there is a constant, we stick it in the | |
6433 | <op> instruction. We don't handle constants larger than | |
6434 | 16 bits, because we have no way to load the upper 16 bits | |
6435 | (actually, we could handle them for the subset of cases | |
6436 | in which we are not using $at). */ | |
6437 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6438 | if (HAVE_NEWABI) |
6439 | { | |
67c0d1eb RS |
6440 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6441 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6442 | if (breg != 0) |
67c0d1eb | 6443 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6444 | tempreg, tempreg, breg); |
67c0d1eb | 6445 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6446 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6447 | break; |
6448 | } | |
252b5132 RH |
6449 | expr1.X_add_number = offset_expr.X_add_number; |
6450 | offset_expr.X_add_number = 0; | |
6451 | if (expr1.X_add_number < -0x8000 | |
6452 | || expr1.X_add_number >= 0x8000) | |
6453 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6454 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6455 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6456 | load_delay_nop (); |
4d7206a2 RS |
6457 | relax_start (offset_expr.X_add_symbol); |
6458 | relax_switch (); | |
67c0d1eb RS |
6459 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6460 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6461 | relax_end (); |
252b5132 | 6462 | if (breg != 0) |
67c0d1eb | 6463 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6464 | tempreg, tempreg, breg); |
67c0d1eb | 6465 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6466 | } |
0a44bf69 | 6467 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 6468 | { |
67c0d1eb | 6469 | int gpdelay; |
252b5132 RH |
6470 | |
6471 | /* If this is a reference to an external symbol, we want | |
6472 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6473 | addu $tempreg,$tempreg,$gp | |
6474 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6475 | <op> $treg,0($tempreg) | |
6476 | Otherwise we want | |
6477 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6478 | nop | |
6479 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6480 | <op> $treg,0($tempreg) | |
6481 | If there is a base register, we add it to $tempreg before | |
6482 | the <op>. If there is a constant, we stick it in the | |
6483 | <op> instruction. We don't handle constants larger than | |
6484 | 16 bits, because we have no way to load the upper 16 bits | |
6485 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6486 | in which we are not using $at). */ |
252b5132 RH |
6487 | assert (offset_expr.X_op == O_symbol); |
6488 | expr1.X_add_number = offset_expr.X_add_number; | |
6489 | offset_expr.X_add_number = 0; | |
6490 | if (expr1.X_add_number < -0x8000 | |
6491 | || expr1.X_add_number >= 0x8000) | |
6492 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6493 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6494 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6495 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6496 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6497 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6498 | mips_gp_register); | |
6499 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6500 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6501 | relax_switch (); |
67c0d1eb RS |
6502 | if (gpdelay) |
6503 | macro_build (NULL, "nop", ""); | |
6504 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6505 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6506 | load_delay_nop (); |
67c0d1eb RS |
6507 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6508 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6509 | relax_end (); |
6510 | ||
252b5132 | 6511 | if (breg != 0) |
67c0d1eb | 6512 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6513 | tempreg, tempreg, breg); |
67c0d1eb | 6514 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6515 | } |
0a44bf69 | 6516 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6517 | { |
f5040a92 AO |
6518 | /* If this is a reference to an external symbol, we want |
6519 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6520 | add $tempreg,$tempreg,$gp | |
6521 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6522 | <op> $treg,<ofst>($tempreg) | |
6523 | Otherwise, for local symbols, we want: | |
6524 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6525 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6526 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6527 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6528 | offset_expr.X_add_number = 0; |
6529 | if (expr1.X_add_number < -0x8000 | |
6530 | || expr1.X_add_number >= 0x8000) | |
6531 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6532 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6533 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6534 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6535 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6536 | mips_gp_register); | |
6537 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6538 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6539 | if (breg != 0) |
67c0d1eb | 6540 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6541 | tempreg, tempreg, breg); |
67c0d1eb | 6542 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6543 | |
4d7206a2 | 6544 | relax_switch (); |
f5040a92 | 6545 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6546 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6547 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6548 | if (breg != 0) |
67c0d1eb | 6549 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6550 | tempreg, tempreg, breg); |
67c0d1eb | 6551 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6552 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6553 | relax_end (); |
f5040a92 | 6554 | } |
252b5132 RH |
6555 | else |
6556 | abort (); | |
6557 | ||
252b5132 RH |
6558 | break; |
6559 | ||
6560 | case M_LI: | |
6561 | case M_LI_S: | |
67c0d1eb | 6562 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6563 | break; |
252b5132 RH |
6564 | |
6565 | case M_DLI: | |
67c0d1eb | 6566 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6567 | break; |
252b5132 RH |
6568 | |
6569 | case M_LI_SS: | |
6570 | if (imm_expr.X_op == O_constant) | |
6571 | { | |
8fc2e39e | 6572 | used_at = 1; |
67c0d1eb RS |
6573 | load_register (AT, &imm_expr, 0); |
6574 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6575 | break; |
6576 | } | |
6577 | else | |
6578 | { | |
6579 | assert (offset_expr.X_op == O_symbol | |
6580 | && strcmp (segment_name (S_GET_SEGMENT | |
6581 | (offset_expr.X_add_symbol)), | |
6582 | ".lit4") == 0 | |
6583 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6584 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6585 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6586 | break; |
252b5132 RH |
6587 | } |
6588 | ||
6589 | case M_LI_D: | |
ca4e0257 RS |
6590 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6591 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6592 | order 32 bits of the value and the low order 32 bits are either | |
6593 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6594 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6595 | { | |
ca4e0257 | 6596 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6597 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6598 | else |
6599 | { | |
6600 | int hreg, lreg; | |
6601 | ||
6602 | if (target_big_endian) | |
6603 | { | |
6604 | hreg = treg; | |
6605 | lreg = treg + 1; | |
6606 | } | |
6607 | else | |
6608 | { | |
6609 | hreg = treg + 1; | |
6610 | lreg = treg; | |
6611 | } | |
6612 | ||
6613 | if (hreg <= 31) | |
67c0d1eb | 6614 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6615 | if (lreg <= 31) |
6616 | { | |
6617 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6618 | move_register (lreg, 0); |
252b5132 RH |
6619 | else |
6620 | { | |
6621 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6622 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6623 | } |
6624 | } | |
6625 | } | |
8fc2e39e | 6626 | break; |
252b5132 RH |
6627 | } |
6628 | ||
6629 | /* We know that sym is in the .rdata section. First we get the | |
6630 | upper 16 bits of the address. */ | |
6631 | if (mips_pic == NO_PIC) | |
6632 | { | |
67c0d1eb | 6633 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6634 | used_at = 1; |
252b5132 | 6635 | } |
0a44bf69 | 6636 | else |
252b5132 | 6637 | { |
67c0d1eb RS |
6638 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6639 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6640 | used_at = 1; |
252b5132 | 6641 | } |
bdaaa2e1 | 6642 | |
252b5132 | 6643 | /* Now we load the register(s). */ |
ca4e0257 | 6644 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6645 | { |
6646 | used_at = 1; | |
6647 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
6648 | } | |
252b5132 RH |
6649 | else |
6650 | { | |
8fc2e39e | 6651 | used_at = 1; |
67c0d1eb | 6652 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6653 | if (treg != RA) |
252b5132 RH |
6654 | { |
6655 | /* FIXME: How in the world do we deal with the possible | |
6656 | overflow here? */ | |
6657 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6658 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6659 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6660 | } |
6661 | } | |
252b5132 RH |
6662 | break; |
6663 | ||
6664 | case M_LI_DD: | |
ca4e0257 RS |
6665 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6666 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6667 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6668 | the value and the low order 32 bits are either zero or in | |
6669 | OFFSET_EXPR. */ | |
252b5132 RH |
6670 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6671 | { | |
8fc2e39e | 6672 | used_at = 1; |
67c0d1eb | 6673 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6674 | if (HAVE_64BIT_FPRS) |
6675 | { | |
6676 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6677 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6678 | } |
252b5132 RH |
6679 | else |
6680 | { | |
67c0d1eb | 6681 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6682 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6683 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6684 | else |
6685 | { | |
6686 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6687 | load_register (AT, &offset_expr, 0); |
6688 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6689 | } |
6690 | } | |
6691 | break; | |
6692 | } | |
6693 | ||
6694 | assert (offset_expr.X_op == O_symbol | |
6695 | && offset_expr.X_add_number == 0); | |
6696 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6697 | if (strcmp (s, ".lit8") == 0) | |
6698 | { | |
e7af610e | 6699 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6700 | { |
67c0d1eb | 6701 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6702 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6703 | break; |
252b5132 | 6704 | } |
c9914766 | 6705 | breg = mips_gp_register; |
252b5132 RH |
6706 | r = BFD_RELOC_MIPS_LITERAL; |
6707 | goto dob; | |
6708 | } | |
6709 | else | |
6710 | { | |
6711 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
8fc2e39e | 6712 | used_at = 1; |
0a44bf69 | 6713 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
6714 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6715 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6716 | else |
6717 | { | |
6718 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6719 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6720 | } |
bdaaa2e1 | 6721 | |
e7af610e | 6722 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6723 | { |
67c0d1eb RS |
6724 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6725 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6726 | break; |
6727 | } | |
6728 | breg = AT; | |
6729 | r = BFD_RELOC_LO16; | |
6730 | goto dob; | |
6731 | } | |
6732 | ||
6733 | case M_L_DOB: | |
fef14a42 | 6734 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6735 | { |
6736 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6737 | break; |
252b5132 RH |
6738 | } |
6739 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6740 | to adjust when loading from memory. */ | |
6741 | r = BFD_RELOC_LO16; | |
6742 | dob: | |
e7af610e | 6743 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6744 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6745 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6746 | /* FIXME: A possible overflow which I don't know how to deal |
6747 | with. */ | |
6748 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6749 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6750 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
6751 | break; |
6752 | ||
6753 | case M_L_DAB: | |
6754 | /* | |
6755 | * The MIPS assembler seems to check for X_add_number not | |
6756 | * being double aligned and generating: | |
6757 | * lui at,%hi(foo+1) | |
6758 | * addu at,at,v1 | |
6759 | * addiu at,at,%lo(foo+1) | |
6760 | * lwc1 f2,0(at) | |
6761 | * lwc1 f3,4(at) | |
6762 | * But, the resulting address is the same after relocation so why | |
6763 | * generate the extra instruction? | |
6764 | */ | |
fef14a42 | 6765 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6766 | { |
6767 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6768 | break; |
252b5132 | 6769 | } |
bdaaa2e1 | 6770 | /* Itbl support may require additional care here. */ |
252b5132 | 6771 | coproc = 1; |
e7af610e | 6772 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6773 | { |
6774 | s = "ldc1"; | |
6775 | goto ld; | |
6776 | } | |
6777 | ||
6778 | s = "lwc1"; | |
6779 | fmt = "T,o(b)"; | |
6780 | goto ldd_std; | |
6781 | ||
6782 | case M_S_DAB: | |
fef14a42 | 6783 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6784 | { |
6785 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6786 | break; |
252b5132 RH |
6787 | } |
6788 | ||
e7af610e | 6789 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6790 | { |
6791 | s = "sdc1"; | |
6792 | goto st; | |
6793 | } | |
6794 | ||
6795 | s = "swc1"; | |
6796 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6797 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6798 | coproc = 1; |
6799 | goto ldd_std; | |
6800 | ||
6801 | case M_LD_AB: | |
ca4e0257 | 6802 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6803 | { |
6804 | s = "ld"; | |
6805 | goto ld; | |
6806 | } | |
6807 | ||
6808 | s = "lw"; | |
6809 | fmt = "t,o(b)"; | |
6810 | goto ldd_std; | |
6811 | ||
6812 | case M_SD_AB: | |
ca4e0257 | 6813 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6814 | { |
6815 | s = "sd"; | |
6816 | goto st; | |
6817 | } | |
6818 | ||
6819 | s = "sw"; | |
6820 | fmt = "t,o(b)"; | |
6821 | ||
6822 | ldd_std: | |
6823 | if (offset_expr.X_op != O_symbol | |
6824 | && offset_expr.X_op != O_constant) | |
6825 | { | |
6826 | as_bad (_("expression too complex")); | |
6827 | offset_expr.X_op = O_constant; | |
6828 | } | |
6829 | ||
2051e8c4 MR |
6830 | if (HAVE_32BIT_ADDRESSES |
6831 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6832 | { |
6833 | char value [32]; | |
6834 | ||
6835 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6836 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6837 | } |
2051e8c4 | 6838 | |
252b5132 RH |
6839 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6840 | to adjust when loading from memory. We set coproc if we must | |
6841 | load $fn+1 first. */ | |
bdaaa2e1 | 6842 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6843 | if (! target_big_endian) |
6844 | coproc = 0; | |
6845 | ||
6846 | if (mips_pic == NO_PIC | |
6847 | || offset_expr.X_op == O_constant) | |
6848 | { | |
6849 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6850 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6851 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6852 | If we have a base register, we use this |
6853 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6854 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6855 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6856 | If this is not a GP relative symbol, we want |
6857 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6858 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6859 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6860 | If there is a base register, we add it to $at after the | |
6861 | lui instruction. If there is a constant, we always use | |
6862 | the last case. */ | |
39a59cf8 MR |
6863 | if (offset_expr.X_op == O_symbol |
6864 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 6865 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6866 | { |
4d7206a2 | 6867 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6868 | if (breg == 0) |
6869 | { | |
c9914766 | 6870 | tempreg = mips_gp_register; |
252b5132 RH |
6871 | } |
6872 | else | |
6873 | { | |
67c0d1eb | 6874 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6875 | AT, breg, mips_gp_register); |
252b5132 | 6876 | tempreg = AT; |
252b5132 RH |
6877 | used_at = 1; |
6878 | } | |
6879 | ||
beae10d5 | 6880 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6881 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6882 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6883 | offset_expr.X_add_number += 4; |
6884 | ||
6885 | /* Set mips_optimize to 2 to avoid inserting an | |
6886 | undesired nop. */ | |
6887 | hold_mips_optimize = mips_optimize; | |
6888 | mips_optimize = 2; | |
beae10d5 | 6889 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6890 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6891 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6892 | mips_optimize = hold_mips_optimize; |
6893 | ||
4d7206a2 | 6894 | relax_switch (); |
252b5132 RH |
6895 | |
6896 | /* We just generated two relocs. When tc_gen_reloc | |
6897 | handles this case, it will skip the first reloc and | |
6898 | handle the second. The second reloc already has an | |
6899 | extra addend of 4, which we added above. We must | |
6900 | subtract it out, and then subtract another 4 to make | |
6901 | the first reloc come out right. The second reloc | |
6902 | will come out right because we are going to add 4 to | |
6903 | offset_expr when we build its instruction below. | |
6904 | ||
6905 | If we have a symbol, then we don't want to include | |
6906 | the offset, because it will wind up being included | |
6907 | when we generate the reloc. */ | |
6908 | ||
6909 | if (offset_expr.X_op == O_constant) | |
6910 | offset_expr.X_add_number -= 8; | |
6911 | else | |
6912 | { | |
6913 | offset_expr.X_add_number = -4; | |
6914 | offset_expr.X_op = O_constant; | |
6915 | } | |
6916 | } | |
8fc2e39e | 6917 | used_at = 1; |
67c0d1eb | 6918 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6919 | if (breg != 0) |
67c0d1eb | 6920 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6921 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6922 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6923 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6924 | /* FIXME: How do we handle overflow here? */ |
6925 | offset_expr.X_add_number += 4; | |
beae10d5 | 6926 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6927 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6928 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6929 | if (mips_relax.sequence) |
6930 | relax_end (); | |
bdaaa2e1 | 6931 | } |
0a44bf69 | 6932 | else if (!mips_big_got) |
252b5132 | 6933 | { |
252b5132 RH |
6934 | /* If this is a reference to an external symbol, we want |
6935 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6936 | nop | |
6937 | <op> $treg,0($at) | |
6938 | <op> $treg+1,4($at) | |
6939 | Otherwise we want | |
6940 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6941 | nop | |
6942 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6943 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6944 | If there is a base register we add it to $at before the | |
6945 | lwc1 instructions. If there is a constant we include it | |
6946 | in the lwc1 instructions. */ | |
6947 | used_at = 1; | |
6948 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6949 | if (expr1.X_add_number < -0x8000 |
6950 | || expr1.X_add_number >= 0x8000 - 4) | |
6951 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6952 | load_got_offset (AT, &offset_expr); |
269137b2 | 6953 | load_delay_nop (); |
252b5132 | 6954 | if (breg != 0) |
67c0d1eb | 6955 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6956 | |
6957 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6958 | nop. */ | |
6959 | hold_mips_optimize = mips_optimize; | |
6960 | mips_optimize = 2; | |
4d7206a2 | 6961 | |
beae10d5 | 6962 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6963 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6964 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6965 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6966 | expr1.X_add_number += 4; |
67c0d1eb RS |
6967 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6968 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6969 | relax_switch (); |
67c0d1eb RS |
6970 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6971 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6972 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6973 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6974 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6975 | relax_end (); |
252b5132 | 6976 | |
4d7206a2 | 6977 | mips_optimize = hold_mips_optimize; |
252b5132 | 6978 | } |
0a44bf69 | 6979 | else if (mips_big_got) |
252b5132 | 6980 | { |
67c0d1eb | 6981 | int gpdelay; |
252b5132 RH |
6982 | |
6983 | /* If this is a reference to an external symbol, we want | |
6984 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6985 | addu $at,$at,$gp | |
6986 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6987 | nop | |
6988 | <op> $treg,0($at) | |
6989 | <op> $treg+1,4($at) | |
6990 | Otherwise we want | |
6991 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6992 | nop | |
6993 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6994 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6995 | If there is a base register we add it to $at before the | |
6996 | lwc1 instructions. If there is a constant we include it | |
6997 | in the lwc1 instructions. */ | |
6998 | used_at = 1; | |
6999 | expr1.X_add_number = offset_expr.X_add_number; | |
7000 | offset_expr.X_add_number = 0; | |
7001 | if (expr1.X_add_number < -0x8000 | |
7002 | || expr1.X_add_number >= 0x8000 - 4) | |
7003 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7004 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 7005 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7006 | macro_build (&offset_expr, "lui", "t,u", |
7007 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
7008 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 7009 | AT, AT, mips_gp_register); |
67c0d1eb | 7010 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7011 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 7012 | load_delay_nop (); |
252b5132 | 7013 | if (breg != 0) |
67c0d1eb | 7014 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7015 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7016 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7017 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7018 | expr1.X_add_number += 4; |
7019 | ||
7020 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7021 | nop. */ | |
7022 | hold_mips_optimize = mips_optimize; | |
7023 | mips_optimize = 2; | |
beae10d5 | 7024 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7025 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7026 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7027 | mips_optimize = hold_mips_optimize; |
7028 | expr1.X_add_number -= 4; | |
7029 | ||
4d7206a2 RS |
7030 | relax_switch (); |
7031 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
7032 | if (gpdelay) |
7033 | macro_build (NULL, "nop", ""); | |
7034 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
7035 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7036 | load_delay_nop (); |
252b5132 | 7037 | if (breg != 0) |
67c0d1eb | 7038 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7039 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7040 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7041 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7042 | offset_expr.X_add_number += 4; |
252b5132 RH |
7043 | |
7044 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7045 | nop. */ | |
7046 | hold_mips_optimize = mips_optimize; | |
7047 | mips_optimize = 2; | |
beae10d5 | 7048 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7049 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7050 | BFD_RELOC_LO16, AT); | |
252b5132 | 7051 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 7052 | relax_end (); |
252b5132 | 7053 | } |
252b5132 RH |
7054 | else |
7055 | abort (); | |
7056 | ||
252b5132 RH |
7057 | break; |
7058 | ||
7059 | case M_LD_OB: | |
7060 | s = "lw"; | |
7061 | goto sd_ob; | |
7062 | case M_SD_OB: | |
7063 | s = "sw"; | |
7064 | sd_ob: | |
ca4e0257 | 7065 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 7066 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 7067 | offset_expr.X_add_number += 4; |
67c0d1eb | 7068 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
8fc2e39e | 7069 | break; |
252b5132 RH |
7070 | |
7071 | /* New code added to support COPZ instructions. | |
7072 | This code builds table entries out of the macros in mip_opcodes. | |
7073 | R4000 uses interlocks to handle coproc delays. | |
7074 | Other chips (like the R3000) require nops to be inserted for delays. | |
7075 | ||
f72c8c98 | 7076 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
7077 | In order to fill delay slots for non-interlocked chips, |
7078 | we must have a way to specify delays based on the coprocessor. | |
7079 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
7080 | What are the side-effects of the cop instruction? | |
7081 | What cache support might we have and what are its effects? | |
7082 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 7083 | What registers are read/set/modified? |
252b5132 RH |
7084 | |
7085 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 7086 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
7087 | |
7088 | case M_COP0: | |
7089 | s = "c0"; | |
7090 | goto copz; | |
7091 | case M_COP1: | |
7092 | s = "c1"; | |
7093 | goto copz; | |
7094 | case M_COP2: | |
7095 | s = "c2"; | |
7096 | goto copz; | |
7097 | case M_COP3: | |
7098 | s = "c3"; | |
7099 | copz: | |
7100 | /* For now we just do C (same as Cz). The parameter will be | |
7101 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 7102 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 7103 | break; |
252b5132 | 7104 | |
ea1fb5dc | 7105 | case M_MOVE: |
67c0d1eb | 7106 | move_register (dreg, sreg); |
8fc2e39e | 7107 | break; |
ea1fb5dc | 7108 | |
252b5132 RH |
7109 | #ifdef LOSING_COMPILER |
7110 | default: | |
7111 | /* Try and see if this is a new itbl instruction. | |
7112 | This code builds table entries out of the macros in mip_opcodes. | |
7113 | FIXME: For now we just assemble the expression and pass it's | |
7114 | value along as a 32-bit immediate. | |
bdaaa2e1 | 7115 | We may want to have the assembler assemble this value, |
252b5132 RH |
7116 | so that we gain the assembler's knowledge of delay slots, |
7117 | symbols, etc. | |
7118 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 7119 | if (itbl_have_entries |
252b5132 | 7120 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 7121 | { |
252b5132 RH |
7122 | s = ip->insn_mo->name; |
7123 | s2 = "cop3"; | |
7124 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 7125 | macro_build (&immed_expr, s, "C"); |
8fc2e39e | 7126 | break; |
beae10d5 | 7127 | } |
252b5132 | 7128 | macro2 (ip); |
8fc2e39e | 7129 | break; |
252b5132 | 7130 | } |
8fc2e39e TS |
7131 | if (mips_opts.noat && used_at) |
7132 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 | 7133 | } |
bdaaa2e1 | 7134 | |
252b5132 | 7135 | static void |
17a2f251 | 7136 | macro2 (struct mips_cl_insn *ip) |
252b5132 | 7137 | { |
3994f87e | 7138 | int treg, sreg, dreg, breg; |
252b5132 RH |
7139 | int tempreg; |
7140 | int mask; | |
252b5132 RH |
7141 | int used_at; |
7142 | expressionS expr1; | |
7143 | const char *s; | |
7144 | const char *s2; | |
7145 | const char *fmt; | |
7146 | int likely = 0; | |
7147 | int dbl = 0; | |
7148 | int coproc = 0; | |
7149 | int lr = 0; | |
7150 | int imm = 0; | |
7151 | int off; | |
7152 | offsetT maxnum; | |
7153 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 7154 | |
252b5132 RH |
7155 | treg = (ip->insn_opcode >> 16) & 0x1f; |
7156 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
7157 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
7158 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 7159 | |
252b5132 RH |
7160 | expr1.X_op = O_constant; |
7161 | expr1.X_op_symbol = NULL; | |
7162 | expr1.X_add_symbol = NULL; | |
7163 | expr1.X_add_number = 1; | |
bdaaa2e1 | 7164 | |
252b5132 RH |
7165 | switch (mask) |
7166 | { | |
7167 | #endif /* LOSING_COMPILER */ | |
7168 | ||
7169 | case M_DMUL: | |
7170 | dbl = 1; | |
7171 | case M_MUL: | |
67c0d1eb RS |
7172 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
7173 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 7174 | break; |
252b5132 RH |
7175 | |
7176 | case M_DMUL_I: | |
7177 | dbl = 1; | |
7178 | case M_MUL_I: | |
7179 | /* The MIPS assembler some times generates shifts and adds. I'm | |
7180 | not trying to be that fancy. GCC should do this for us | |
7181 | anyway. */ | |
8fc2e39e | 7182 | used_at = 1; |
67c0d1eb RS |
7183 | load_register (AT, &imm_expr, dbl); |
7184 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
7185 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
7186 | break; |
7187 | ||
7188 | case M_DMULO_I: | |
7189 | dbl = 1; | |
7190 | case M_MULO_I: | |
7191 | imm = 1; | |
7192 | goto do_mulo; | |
7193 | ||
7194 | case M_DMULO: | |
7195 | dbl = 1; | |
7196 | case M_MULO: | |
7197 | do_mulo: | |
7d10b47d | 7198 | start_noreorder (); |
8fc2e39e | 7199 | used_at = 1; |
252b5132 | 7200 | if (imm) |
67c0d1eb RS |
7201 | load_register (AT, &imm_expr, dbl); |
7202 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
7203 | macro_build (NULL, "mflo", "d", dreg); | |
7204 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
7205 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 7206 | if (mips_trap) |
67c0d1eb | 7207 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
7208 | else |
7209 | { | |
7210 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7211 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
7212 | macro_build (NULL, "nop", "", 0); | |
7213 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 7214 | } |
7d10b47d | 7215 | end_noreorder (); |
67c0d1eb | 7216 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
7217 | break; |
7218 | ||
7219 | case M_DMULOU_I: | |
7220 | dbl = 1; | |
7221 | case M_MULOU_I: | |
7222 | imm = 1; | |
7223 | goto do_mulou; | |
7224 | ||
7225 | case M_DMULOU: | |
7226 | dbl = 1; | |
7227 | case M_MULOU: | |
7228 | do_mulou: | |
7d10b47d | 7229 | start_noreorder (); |
8fc2e39e | 7230 | used_at = 1; |
252b5132 | 7231 | if (imm) |
67c0d1eb RS |
7232 | load_register (AT, &imm_expr, dbl); |
7233 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 7234 | sreg, imm ? AT : treg); |
67c0d1eb RS |
7235 | macro_build (NULL, "mfhi", "d", AT); |
7236 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 7237 | if (mips_trap) |
67c0d1eb | 7238 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
7239 | else |
7240 | { | |
7241 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7242 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
7243 | macro_build (NULL, "nop", "", 0); | |
7244 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 7245 | } |
7d10b47d | 7246 | end_noreorder (); |
252b5132 RH |
7247 | break; |
7248 | ||
771c7ce4 | 7249 | case M_DROL: |
fef14a42 | 7250 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7251 | { |
7252 | if (dreg == sreg) | |
7253 | { | |
7254 | tempreg = AT; | |
7255 | used_at = 1; | |
7256 | } | |
7257 | else | |
7258 | { | |
7259 | tempreg = dreg; | |
82dd0097 | 7260 | } |
67c0d1eb RS |
7261 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
7262 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7263 | break; |
82dd0097 | 7264 | } |
8fc2e39e | 7265 | used_at = 1; |
67c0d1eb RS |
7266 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7267 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
7268 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
7269 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7270 | break; |
7271 | ||
252b5132 | 7272 | case M_ROL: |
fef14a42 | 7273 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
7274 | { |
7275 | if (dreg == sreg) | |
7276 | { | |
7277 | tempreg = AT; | |
7278 | used_at = 1; | |
7279 | } | |
7280 | else | |
7281 | { | |
7282 | tempreg = dreg; | |
82dd0097 | 7283 | } |
67c0d1eb RS |
7284 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
7285 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7286 | break; |
82dd0097 | 7287 | } |
8fc2e39e | 7288 | used_at = 1; |
67c0d1eb RS |
7289 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7290 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
7291 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
7292 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7293 | break; |
7294 | ||
771c7ce4 TS |
7295 | case M_DROL_I: |
7296 | { | |
7297 | unsigned int rot; | |
82dd0097 | 7298 | char *l, *r; |
771c7ce4 TS |
7299 | |
7300 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7301 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7302 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7303 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
7304 | { |
7305 | rot = (64 - rot) & 0x3f; | |
7306 | if (rot >= 32) | |
67c0d1eb | 7307 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 7308 | else |
67c0d1eb | 7309 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7310 | break; |
60b63b72 | 7311 | } |
483fc7cd | 7312 | if (rot == 0) |
483fc7cd | 7313 | { |
67c0d1eb | 7314 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7315 | break; |
483fc7cd | 7316 | } |
82dd0097 CD |
7317 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
7318 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
7319 | rot &= 0x1f; | |
8fc2e39e | 7320 | used_at = 1; |
67c0d1eb RS |
7321 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
7322 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7323 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7324 | } |
7325 | break; | |
7326 | ||
252b5132 | 7327 | case M_ROL_I: |
771c7ce4 TS |
7328 | { |
7329 | unsigned int rot; | |
7330 | ||
7331 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7332 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7333 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7334 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 7335 | { |
67c0d1eb | 7336 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 7337 | break; |
60b63b72 | 7338 | } |
483fc7cd | 7339 | if (rot == 0) |
483fc7cd | 7340 | { |
67c0d1eb | 7341 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7342 | break; |
483fc7cd | 7343 | } |
8fc2e39e | 7344 | used_at = 1; |
67c0d1eb RS |
7345 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
7346 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7347 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7348 | } |
7349 | break; | |
7350 | ||
7351 | case M_DROR: | |
fef14a42 | 7352 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7353 | { |
67c0d1eb | 7354 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7355 | break; |
82dd0097 | 7356 | } |
8fc2e39e | 7357 | used_at = 1; |
67c0d1eb RS |
7358 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7359 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
7360 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7361 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7362 | break; |
7363 | ||
7364 | case M_ROR: | |
fef14a42 | 7365 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7366 | { |
67c0d1eb | 7367 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7368 | break; |
82dd0097 | 7369 | } |
8fc2e39e | 7370 | used_at = 1; |
67c0d1eb RS |
7371 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7372 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
7373 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7374 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7375 | break; |
7376 | ||
771c7ce4 TS |
7377 | case M_DROR_I: |
7378 | { | |
7379 | unsigned int rot; | |
82dd0097 | 7380 | char *l, *r; |
771c7ce4 TS |
7381 | |
7382 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7383 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7384 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7385 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7386 | { |
7387 | if (rot >= 32) | |
67c0d1eb | 7388 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7389 | else |
67c0d1eb | 7390 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7391 | break; |
82dd0097 | 7392 | } |
483fc7cd | 7393 | if (rot == 0) |
483fc7cd | 7394 | { |
67c0d1eb | 7395 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7396 | break; |
483fc7cd | 7397 | } |
82dd0097 CD |
7398 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7399 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7400 | rot &= 0x1f; | |
8fc2e39e | 7401 | used_at = 1; |
67c0d1eb RS |
7402 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
7403 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7404 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7405 | } |
7406 | break; | |
7407 | ||
252b5132 | 7408 | case M_ROR_I: |
771c7ce4 TS |
7409 | { |
7410 | unsigned int rot; | |
7411 | ||
7412 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7413 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7414 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7415 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7416 | { |
67c0d1eb | 7417 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7418 | break; |
82dd0097 | 7419 | } |
483fc7cd | 7420 | if (rot == 0) |
483fc7cd | 7421 | { |
67c0d1eb | 7422 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7423 | break; |
483fc7cd | 7424 | } |
8fc2e39e | 7425 | used_at = 1; |
67c0d1eb RS |
7426 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7427 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7428 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7429 | } |
252b5132 RH |
7430 | break; |
7431 | ||
7432 | case M_S_DOB: | |
fef14a42 | 7433 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
7434 | { |
7435 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 7436 | break; |
252b5132 | 7437 | } |
e7af610e | 7438 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7439 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7440 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7441 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7442 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7443 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7444 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7445 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8fc2e39e | 7446 | break; |
252b5132 RH |
7447 | |
7448 | case M_SEQ: | |
7449 | if (sreg == 0) | |
67c0d1eb | 7450 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7451 | else if (treg == 0) |
67c0d1eb | 7452 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7453 | else |
7454 | { | |
67c0d1eb RS |
7455 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7456 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7457 | } |
8fc2e39e | 7458 | break; |
252b5132 RH |
7459 | |
7460 | case M_SEQ_I: | |
7461 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7462 | { | |
67c0d1eb | 7463 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7464 | break; |
252b5132 RH |
7465 | } |
7466 | if (sreg == 0) | |
7467 | { | |
7468 | as_warn (_("Instruction %s: result is always false"), | |
7469 | ip->insn_mo->name); | |
67c0d1eb | 7470 | move_register (dreg, 0); |
8fc2e39e | 7471 | break; |
252b5132 RH |
7472 | } |
7473 | if (imm_expr.X_op == O_constant | |
7474 | && imm_expr.X_add_number >= 0 | |
7475 | && imm_expr.X_add_number < 0x10000) | |
7476 | { | |
67c0d1eb | 7477 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7478 | } |
7479 | else if (imm_expr.X_op == O_constant | |
7480 | && imm_expr.X_add_number > -0x8000 | |
7481 | && imm_expr.X_add_number < 0) | |
7482 | { | |
7483 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7484 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7485 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7486 | } |
7487 | else | |
7488 | { | |
67c0d1eb RS |
7489 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7490 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7491 | used_at = 1; |
7492 | } | |
67c0d1eb | 7493 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7494 | break; |
252b5132 RH |
7495 | |
7496 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7497 | s = "slt"; | |
7498 | goto sge; | |
7499 | case M_SGEU: | |
7500 | s = "sltu"; | |
7501 | sge: | |
67c0d1eb RS |
7502 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7503 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7504 | break; |
252b5132 RH |
7505 | |
7506 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7507 | case M_SGEU_I: | |
7508 | if (imm_expr.X_op == O_constant | |
7509 | && imm_expr.X_add_number >= -0x8000 | |
7510 | && imm_expr.X_add_number < 0x8000) | |
7511 | { | |
67c0d1eb RS |
7512 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7513 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7514 | } |
7515 | else | |
7516 | { | |
67c0d1eb RS |
7517 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7518 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7519 | dreg, sreg, AT); | |
252b5132 RH |
7520 | used_at = 1; |
7521 | } | |
67c0d1eb | 7522 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7523 | break; |
252b5132 RH |
7524 | |
7525 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7526 | s = "slt"; | |
7527 | goto sgt; | |
7528 | case M_SGTU: | |
7529 | s = "sltu"; | |
7530 | sgt: | |
67c0d1eb | 7531 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7532 | break; |
252b5132 RH |
7533 | |
7534 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7535 | s = "slt"; | |
7536 | goto sgti; | |
7537 | case M_SGTU_I: | |
7538 | s = "sltu"; | |
7539 | sgti: | |
8fc2e39e | 7540 | used_at = 1; |
67c0d1eb RS |
7541 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7542 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7543 | break; |
7544 | ||
2396cfb9 | 7545 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7546 | s = "slt"; |
7547 | goto sle; | |
7548 | case M_SLEU: | |
7549 | s = "sltu"; | |
7550 | sle: | |
67c0d1eb RS |
7551 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7552 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7553 | break; |
252b5132 | 7554 | |
2396cfb9 | 7555 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7556 | s = "slt"; |
7557 | goto slei; | |
7558 | case M_SLEU_I: | |
7559 | s = "sltu"; | |
7560 | slei: | |
8fc2e39e | 7561 | used_at = 1; |
67c0d1eb RS |
7562 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7563 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7564 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7565 | break; |
7566 | ||
7567 | case M_SLT_I: | |
7568 | if (imm_expr.X_op == O_constant | |
7569 | && imm_expr.X_add_number >= -0x8000 | |
7570 | && imm_expr.X_add_number < 0x8000) | |
7571 | { | |
67c0d1eb | 7572 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7573 | break; |
252b5132 | 7574 | } |
8fc2e39e | 7575 | used_at = 1; |
67c0d1eb RS |
7576 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7577 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7578 | break; |
7579 | ||
7580 | case M_SLTU_I: | |
7581 | if (imm_expr.X_op == O_constant | |
7582 | && imm_expr.X_add_number >= -0x8000 | |
7583 | && imm_expr.X_add_number < 0x8000) | |
7584 | { | |
67c0d1eb | 7585 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7586 | BFD_RELOC_LO16); |
8fc2e39e | 7587 | break; |
252b5132 | 7588 | } |
8fc2e39e | 7589 | used_at = 1; |
67c0d1eb RS |
7590 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7591 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7592 | break; |
7593 | ||
7594 | case M_SNE: | |
7595 | if (sreg == 0) | |
67c0d1eb | 7596 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7597 | else if (treg == 0) |
67c0d1eb | 7598 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7599 | else |
7600 | { | |
67c0d1eb RS |
7601 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7602 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7603 | } |
8fc2e39e | 7604 | break; |
252b5132 RH |
7605 | |
7606 | case M_SNE_I: | |
7607 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7608 | { | |
67c0d1eb | 7609 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7610 | break; |
252b5132 RH |
7611 | } |
7612 | if (sreg == 0) | |
7613 | { | |
7614 | as_warn (_("Instruction %s: result is always true"), | |
7615 | ip->insn_mo->name); | |
67c0d1eb RS |
7616 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7617 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7618 | break; |
252b5132 RH |
7619 | } |
7620 | if (imm_expr.X_op == O_constant | |
7621 | && imm_expr.X_add_number >= 0 | |
7622 | && imm_expr.X_add_number < 0x10000) | |
7623 | { | |
67c0d1eb | 7624 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7625 | } |
7626 | else if (imm_expr.X_op == O_constant | |
7627 | && imm_expr.X_add_number > -0x8000 | |
7628 | && imm_expr.X_add_number < 0) | |
7629 | { | |
7630 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7631 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7632 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7633 | } |
7634 | else | |
7635 | { | |
67c0d1eb RS |
7636 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7637 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7638 | used_at = 1; |
7639 | } | |
67c0d1eb | 7640 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7641 | break; |
252b5132 RH |
7642 | |
7643 | case M_DSUB_I: | |
7644 | dbl = 1; | |
7645 | case M_SUB_I: | |
7646 | if (imm_expr.X_op == O_constant | |
7647 | && imm_expr.X_add_number > -0x8000 | |
7648 | && imm_expr.X_add_number <= 0x8000) | |
7649 | { | |
7650 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7651 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7652 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7653 | break; |
252b5132 | 7654 | } |
8fc2e39e | 7655 | used_at = 1; |
67c0d1eb RS |
7656 | load_register (AT, &imm_expr, dbl); |
7657 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7658 | break; |
7659 | ||
7660 | case M_DSUBU_I: | |
7661 | dbl = 1; | |
7662 | case M_SUBU_I: | |
7663 | if (imm_expr.X_op == O_constant | |
7664 | && imm_expr.X_add_number > -0x8000 | |
7665 | && imm_expr.X_add_number <= 0x8000) | |
7666 | { | |
7667 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7668 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7669 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7670 | break; |
252b5132 | 7671 | } |
8fc2e39e | 7672 | used_at = 1; |
67c0d1eb RS |
7673 | load_register (AT, &imm_expr, dbl); |
7674 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7675 | break; |
7676 | ||
7677 | case M_TEQ_I: | |
7678 | s = "teq"; | |
7679 | goto trap; | |
7680 | case M_TGE_I: | |
7681 | s = "tge"; | |
7682 | goto trap; | |
7683 | case M_TGEU_I: | |
7684 | s = "tgeu"; | |
7685 | goto trap; | |
7686 | case M_TLT_I: | |
7687 | s = "tlt"; | |
7688 | goto trap; | |
7689 | case M_TLTU_I: | |
7690 | s = "tltu"; | |
7691 | goto trap; | |
7692 | case M_TNE_I: | |
7693 | s = "tne"; | |
7694 | trap: | |
8fc2e39e | 7695 | used_at = 1; |
67c0d1eb RS |
7696 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7697 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7698 | break; |
7699 | ||
252b5132 | 7700 | case M_TRUNCWS: |
43841e91 | 7701 | case M_TRUNCWD: |
e7af610e | 7702 | assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 7703 | used_at = 1; |
252b5132 RH |
7704 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7705 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7706 | ||
7707 | /* | |
7708 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7709 | * or is there a reason for it? | |
7710 | */ | |
7d10b47d | 7711 | start_noreorder (); |
67c0d1eb RS |
7712 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7713 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7714 | macro_build (NULL, "nop", ""); | |
252b5132 | 7715 | expr1.X_add_number = 3; |
67c0d1eb | 7716 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7717 | expr1.X_add_number = 2; |
67c0d1eb RS |
7718 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7719 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7720 | macro_build (NULL, "nop", ""); | |
7721 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7722 | dreg, sreg); | |
7723 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7724 | macro_build (NULL, "nop", ""); | |
7d10b47d | 7725 | end_noreorder (); |
252b5132 RH |
7726 | break; |
7727 | ||
7728 | case M_ULH: | |
7729 | s = "lb"; | |
7730 | goto ulh; | |
7731 | case M_ULHU: | |
7732 | s = "lbu"; | |
7733 | ulh: | |
8fc2e39e | 7734 | used_at = 1; |
252b5132 RH |
7735 | if (offset_expr.X_add_number >= 0x7fff) |
7736 | as_bad (_("operand overflow")); | |
252b5132 | 7737 | if (! target_big_endian) |
f9419b05 | 7738 | ++offset_expr.X_add_number; |
67c0d1eb | 7739 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7740 | if (! target_big_endian) |
f9419b05 | 7741 | --offset_expr.X_add_number; |
252b5132 | 7742 | else |
f9419b05 | 7743 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7744 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7745 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7746 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7747 | break; |
7748 | ||
7749 | case M_ULD: | |
7750 | s = "ldl"; | |
7751 | s2 = "ldr"; | |
7752 | off = 7; | |
7753 | goto ulw; | |
7754 | case M_ULW: | |
7755 | s = "lwl"; | |
7756 | s2 = "lwr"; | |
7757 | off = 3; | |
7758 | ulw: | |
7759 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7760 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7761 | if (treg != breg) |
7762 | tempreg = treg; | |
7763 | else | |
8fc2e39e TS |
7764 | { |
7765 | used_at = 1; | |
7766 | tempreg = AT; | |
7767 | } | |
252b5132 RH |
7768 | if (! target_big_endian) |
7769 | offset_expr.X_add_number += off; | |
67c0d1eb | 7770 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7771 | if (! target_big_endian) |
7772 | offset_expr.X_add_number -= off; | |
7773 | else | |
7774 | offset_expr.X_add_number += off; | |
67c0d1eb | 7775 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7776 | |
7777 | /* If necessary, move the result in tempreg the final destination. */ | |
7778 | if (treg == tempreg) | |
8fc2e39e | 7779 | break; |
af22f5b2 | 7780 | /* Protect second load's delay slot. */ |
017315e4 | 7781 | load_delay_nop (); |
67c0d1eb | 7782 | move_register (treg, tempreg); |
af22f5b2 | 7783 | break; |
252b5132 RH |
7784 | |
7785 | case M_ULD_A: | |
7786 | s = "ldl"; | |
7787 | s2 = "ldr"; | |
7788 | off = 7; | |
7789 | goto ulwa; | |
7790 | case M_ULW_A: | |
7791 | s = "lwl"; | |
7792 | s2 = "lwr"; | |
7793 | off = 3; | |
7794 | ulwa: | |
d6bc6245 | 7795 | used_at = 1; |
67c0d1eb | 7796 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7797 | if (breg != 0) |
67c0d1eb | 7798 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7799 | if (! target_big_endian) |
7800 | expr1.X_add_number = off; | |
7801 | else | |
7802 | expr1.X_add_number = 0; | |
67c0d1eb | 7803 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7804 | if (! target_big_endian) |
7805 | expr1.X_add_number = 0; | |
7806 | else | |
7807 | expr1.X_add_number = off; | |
67c0d1eb | 7808 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7809 | break; |
7810 | ||
7811 | case M_ULH_A: | |
7812 | case M_ULHU_A: | |
d6bc6245 | 7813 | used_at = 1; |
67c0d1eb | 7814 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7815 | if (breg != 0) |
67c0d1eb | 7816 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7817 | if (target_big_endian) |
7818 | expr1.X_add_number = 0; | |
67c0d1eb | 7819 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7820 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7821 | if (target_big_endian) |
7822 | expr1.X_add_number = 1; | |
7823 | else | |
7824 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7825 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7826 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7827 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7828 | break; |
7829 | ||
7830 | case M_USH: | |
8fc2e39e | 7831 | used_at = 1; |
252b5132 RH |
7832 | if (offset_expr.X_add_number >= 0x7fff) |
7833 | as_bad (_("operand overflow")); | |
7834 | if (target_big_endian) | |
f9419b05 | 7835 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7836 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7837 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7838 | if (target_big_endian) |
f9419b05 | 7839 | --offset_expr.X_add_number; |
252b5132 | 7840 | else |
f9419b05 | 7841 | ++offset_expr.X_add_number; |
67c0d1eb | 7842 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7843 | break; |
7844 | ||
7845 | case M_USD: | |
7846 | s = "sdl"; | |
7847 | s2 = "sdr"; | |
7848 | off = 7; | |
7849 | goto usw; | |
7850 | case M_USW: | |
7851 | s = "swl"; | |
7852 | s2 = "swr"; | |
7853 | off = 3; | |
7854 | usw: | |
7855 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7856 | as_bad (_("operand overflow")); | |
7857 | if (! target_big_endian) | |
7858 | offset_expr.X_add_number += off; | |
67c0d1eb | 7859 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7860 | if (! target_big_endian) |
7861 | offset_expr.X_add_number -= off; | |
7862 | else | |
7863 | offset_expr.X_add_number += off; | |
67c0d1eb | 7864 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 7865 | break; |
252b5132 RH |
7866 | |
7867 | case M_USD_A: | |
7868 | s = "sdl"; | |
7869 | s2 = "sdr"; | |
7870 | off = 7; | |
7871 | goto uswa; | |
7872 | case M_USW_A: | |
7873 | s = "swl"; | |
7874 | s2 = "swr"; | |
7875 | off = 3; | |
7876 | uswa: | |
d6bc6245 | 7877 | used_at = 1; |
67c0d1eb | 7878 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7879 | if (breg != 0) |
67c0d1eb | 7880 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7881 | if (! target_big_endian) |
7882 | expr1.X_add_number = off; | |
7883 | else | |
7884 | expr1.X_add_number = 0; | |
67c0d1eb | 7885 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7886 | if (! target_big_endian) |
7887 | expr1.X_add_number = 0; | |
7888 | else | |
7889 | expr1.X_add_number = off; | |
67c0d1eb | 7890 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7891 | break; |
7892 | ||
7893 | case M_USH_A: | |
d6bc6245 | 7894 | used_at = 1; |
67c0d1eb | 7895 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7896 | if (breg != 0) |
67c0d1eb | 7897 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7898 | if (! target_big_endian) |
7899 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7900 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7901 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7902 | if (! target_big_endian) |
7903 | expr1.X_add_number = 1; | |
7904 | else | |
7905 | expr1.X_add_number = 0; | |
67c0d1eb | 7906 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7907 | if (! target_big_endian) |
7908 | expr1.X_add_number = 0; | |
7909 | else | |
7910 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7911 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7912 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7913 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7914 | break; |
7915 | ||
7916 | default: | |
7917 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7918 | are added dynamically. */ |
252b5132 RH |
7919 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7920 | break; | |
7921 | } | |
8fc2e39e TS |
7922 | if (mips_opts.noat && used_at) |
7923 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
7924 | } |
7925 | ||
7926 | /* Implement macros in mips16 mode. */ | |
7927 | ||
7928 | static void | |
17a2f251 | 7929 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7930 | { |
7931 | int mask; | |
7932 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7933 | expressionS expr1; |
7934 | int dbl; | |
7935 | const char *s, *s2, *s3; | |
7936 | ||
7937 | mask = ip->insn_mo->mask; | |
7938 | ||
bf12938e RS |
7939 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
7940 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
7941 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 7942 | |
252b5132 RH |
7943 | expr1.X_op = O_constant; |
7944 | expr1.X_op_symbol = NULL; | |
7945 | expr1.X_add_symbol = NULL; | |
7946 | expr1.X_add_number = 1; | |
7947 | ||
7948 | dbl = 0; | |
7949 | ||
7950 | switch (mask) | |
7951 | { | |
7952 | default: | |
7953 | internalError (); | |
7954 | ||
7955 | case M_DDIV_3: | |
7956 | dbl = 1; | |
7957 | case M_DIV_3: | |
7958 | s = "mflo"; | |
7959 | goto do_div3; | |
7960 | case M_DREM_3: | |
7961 | dbl = 1; | |
7962 | case M_REM_3: | |
7963 | s = "mfhi"; | |
7964 | do_div3: | |
7d10b47d | 7965 | start_noreorder (); |
67c0d1eb | 7966 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7967 | expr1.X_add_number = 2; |
67c0d1eb RS |
7968 | macro_build (&expr1, "bnez", "x,p", yreg); |
7969 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7970 | |
252b5132 RH |
7971 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7972 | since that causes an overflow. We should do that as well, | |
7973 | but I don't see how to do the comparisons without a temporary | |
7974 | register. */ | |
7d10b47d | 7975 | end_noreorder (); |
67c0d1eb | 7976 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
7977 | break; |
7978 | ||
7979 | case M_DIVU_3: | |
7980 | s = "divu"; | |
7981 | s2 = "mflo"; | |
7982 | goto do_divu3; | |
7983 | case M_REMU_3: | |
7984 | s = "divu"; | |
7985 | s2 = "mfhi"; | |
7986 | goto do_divu3; | |
7987 | case M_DDIVU_3: | |
7988 | s = "ddivu"; | |
7989 | s2 = "mflo"; | |
7990 | goto do_divu3; | |
7991 | case M_DREMU_3: | |
7992 | s = "ddivu"; | |
7993 | s2 = "mfhi"; | |
7994 | do_divu3: | |
7d10b47d | 7995 | start_noreorder (); |
67c0d1eb | 7996 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7997 | expr1.X_add_number = 2; |
67c0d1eb RS |
7998 | macro_build (&expr1, "bnez", "x,p", yreg); |
7999 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 8000 | end_noreorder (); |
67c0d1eb | 8001 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
8002 | break; |
8003 | ||
8004 | case M_DMUL: | |
8005 | dbl = 1; | |
8006 | case M_MUL: | |
67c0d1eb RS |
8007 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
8008 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 8009 | break; |
252b5132 RH |
8010 | |
8011 | case M_DSUBU_I: | |
8012 | dbl = 1; | |
8013 | goto do_subu; | |
8014 | case M_SUBU_I: | |
8015 | do_subu: | |
8016 | if (imm_expr.X_op != O_constant) | |
8017 | as_bad (_("Unsupported large constant")); | |
8018 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8019 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
8020 | break; |
8021 | ||
8022 | case M_SUBU_I_2: | |
8023 | if (imm_expr.X_op != O_constant) | |
8024 | as_bad (_("Unsupported large constant")); | |
8025 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8026 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
8027 | break; |
8028 | ||
8029 | case M_DSUBU_I_2: | |
8030 | if (imm_expr.X_op != O_constant) | |
8031 | as_bad (_("Unsupported large constant")); | |
8032 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8033 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
8034 | break; |
8035 | ||
8036 | case M_BEQ: | |
8037 | s = "cmp"; | |
8038 | s2 = "bteqz"; | |
8039 | goto do_branch; | |
8040 | case M_BNE: | |
8041 | s = "cmp"; | |
8042 | s2 = "btnez"; | |
8043 | goto do_branch; | |
8044 | case M_BLT: | |
8045 | s = "slt"; | |
8046 | s2 = "btnez"; | |
8047 | goto do_branch; | |
8048 | case M_BLTU: | |
8049 | s = "sltu"; | |
8050 | s2 = "btnez"; | |
8051 | goto do_branch; | |
8052 | case M_BLE: | |
8053 | s = "slt"; | |
8054 | s2 = "bteqz"; | |
8055 | goto do_reverse_branch; | |
8056 | case M_BLEU: | |
8057 | s = "sltu"; | |
8058 | s2 = "bteqz"; | |
8059 | goto do_reverse_branch; | |
8060 | case M_BGE: | |
8061 | s = "slt"; | |
8062 | s2 = "bteqz"; | |
8063 | goto do_branch; | |
8064 | case M_BGEU: | |
8065 | s = "sltu"; | |
8066 | s2 = "bteqz"; | |
8067 | goto do_branch; | |
8068 | case M_BGT: | |
8069 | s = "slt"; | |
8070 | s2 = "btnez"; | |
8071 | goto do_reverse_branch; | |
8072 | case M_BGTU: | |
8073 | s = "sltu"; | |
8074 | s2 = "btnez"; | |
8075 | ||
8076 | do_reverse_branch: | |
8077 | tmp = xreg; | |
8078 | xreg = yreg; | |
8079 | yreg = tmp; | |
8080 | ||
8081 | do_branch: | |
67c0d1eb RS |
8082 | macro_build (NULL, s, "x,y", xreg, yreg); |
8083 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8084 | break; |
8085 | ||
8086 | case M_BEQ_I: | |
8087 | s = "cmpi"; | |
8088 | s2 = "bteqz"; | |
8089 | s3 = "x,U"; | |
8090 | goto do_branch_i; | |
8091 | case M_BNE_I: | |
8092 | s = "cmpi"; | |
8093 | s2 = "btnez"; | |
8094 | s3 = "x,U"; | |
8095 | goto do_branch_i; | |
8096 | case M_BLT_I: | |
8097 | s = "slti"; | |
8098 | s2 = "btnez"; | |
8099 | s3 = "x,8"; | |
8100 | goto do_branch_i; | |
8101 | case M_BLTU_I: | |
8102 | s = "sltiu"; | |
8103 | s2 = "btnez"; | |
8104 | s3 = "x,8"; | |
8105 | goto do_branch_i; | |
8106 | case M_BLE_I: | |
8107 | s = "slti"; | |
8108 | s2 = "btnez"; | |
8109 | s3 = "x,8"; | |
8110 | goto do_addone_branch_i; | |
8111 | case M_BLEU_I: | |
8112 | s = "sltiu"; | |
8113 | s2 = "btnez"; | |
8114 | s3 = "x,8"; | |
8115 | goto do_addone_branch_i; | |
8116 | case M_BGE_I: | |
8117 | s = "slti"; | |
8118 | s2 = "bteqz"; | |
8119 | s3 = "x,8"; | |
8120 | goto do_branch_i; | |
8121 | case M_BGEU_I: | |
8122 | s = "sltiu"; | |
8123 | s2 = "bteqz"; | |
8124 | s3 = "x,8"; | |
8125 | goto do_branch_i; | |
8126 | case M_BGT_I: | |
8127 | s = "slti"; | |
8128 | s2 = "bteqz"; | |
8129 | s3 = "x,8"; | |
8130 | goto do_addone_branch_i; | |
8131 | case M_BGTU_I: | |
8132 | s = "sltiu"; | |
8133 | s2 = "bteqz"; | |
8134 | s3 = "x,8"; | |
8135 | ||
8136 | do_addone_branch_i: | |
8137 | if (imm_expr.X_op != O_constant) | |
8138 | as_bad (_("Unsupported large constant")); | |
8139 | ++imm_expr.X_add_number; | |
8140 | ||
8141 | do_branch_i: | |
67c0d1eb RS |
8142 | macro_build (&imm_expr, s, s3, xreg); |
8143 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8144 | break; |
8145 | ||
8146 | case M_ABS: | |
8147 | expr1.X_add_number = 0; | |
67c0d1eb | 8148 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 8149 | if (xreg != yreg) |
67c0d1eb | 8150 | move_register (xreg, yreg); |
252b5132 | 8151 | expr1.X_add_number = 2; |
67c0d1eb RS |
8152 | macro_build (&expr1, "bteqz", "p"); |
8153 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
8154 | } |
8155 | } | |
8156 | ||
8157 | /* For consistency checking, verify that all bits are specified either | |
8158 | by the match/mask part of the instruction definition, or by the | |
8159 | operand list. */ | |
8160 | static int | |
17a2f251 | 8161 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
8162 | { |
8163 | const char *p = opc->args; | |
8164 | char c; | |
8165 | unsigned long used_bits = opc->mask; | |
8166 | ||
8167 | if ((used_bits & opc->match) != opc->match) | |
8168 | { | |
8169 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8170 | opc->name, opc->args); | |
8171 | return 0; | |
8172 | } | |
8173 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8174 | while (*p) | |
8175 | switch (c = *p++) | |
8176 | { | |
8177 | case ',': break; | |
8178 | case '(': break; | |
8179 | case ')': break; | |
af7ee8bf CD |
8180 | case '+': |
8181 | switch (c = *p++) | |
8182 | { | |
9bcd4f99 TS |
8183 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
8184 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
8185 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
8186 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
8187 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8188 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8189 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8190 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8191 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
8192 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8193 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8194 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8195 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8196 | case 'I': break; | |
ef2e4d86 CF |
8197 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
8198 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
8199 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
af7ee8bf CD |
8200 | default: |
8201 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8202 | c, opc->name, opc->args); | |
8203 | return 0; | |
8204 | } | |
8205 | break; | |
252b5132 RH |
8206 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8207 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8208 | case 'A': break; | |
4372b673 | 8209 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8210 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8211 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8212 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8213 | case 'F': break; | |
8214 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8215 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8216 | case 'I': break; |
e972090a | 8217 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8218 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8219 | case 'L': break; |
8220 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8221 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8222 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8223 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8224 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8225 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8226 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8227 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8228 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8229 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8230 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8231 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8232 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8233 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8234 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8235 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8236 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8237 | case 'f': break; | |
8238 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8239 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8240 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8241 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8242 | case 'l': break; | |
8243 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8244 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8245 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8246 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8247 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8248 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8249 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8250 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8251 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8252 | case 'x': break; | |
8253 | case 'z': break; | |
8254 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8255 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8256 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8257 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8258 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8259 | case '[': break; | |
8260 | case ']': break; | |
8b082fb1 | 8261 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
8262 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
8263 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
8264 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
8265 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8266 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
8267 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
8268 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
8269 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
8270 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
8271 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
8272 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
8273 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
8274 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
8275 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
8276 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
8277 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
252b5132 RH |
8278 | default: |
8279 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8280 | c, opc->name, opc->args); | |
8281 | return 0; | |
8282 | } | |
8283 | #undef USE_BITS | |
8284 | if (used_bits != 0xffffffff) | |
8285 | { | |
8286 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8287 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8288 | return 0; | |
8289 | } | |
8290 | return 1; | |
8291 | } | |
8292 | ||
9bcd4f99 TS |
8293 | /* UDI immediates. */ |
8294 | struct mips_immed { | |
8295 | char type; | |
8296 | unsigned int shift; | |
8297 | unsigned long mask; | |
8298 | const char * desc; | |
8299 | }; | |
8300 | ||
8301 | static const struct mips_immed mips_immed[] = { | |
8302 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
8303 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
8304 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
8305 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
8306 | { 0,0,0,0 } | |
8307 | }; | |
8308 | ||
7455baf8 TS |
8309 | /* Check whether an odd floating-point register is allowed. */ |
8310 | static int | |
8311 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
8312 | { | |
8313 | const char *s = insn->name; | |
8314 | ||
8315 | if (insn->pinfo == INSN_MACRO) | |
8316 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
8317 | return 1; | |
8318 | ||
8319 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
8320 | { | |
8321 | /* Allow odd registers for single-precision ops. */ | |
8322 | switch (insn->pinfo & (FP_S | FP_D)) | |
8323 | { | |
8324 | case FP_S: | |
8325 | case 0: | |
8326 | return 1; /* both single precision - ok */ | |
8327 | case FP_D: | |
8328 | return 0; /* both double precision - fail */ | |
8329 | default: | |
8330 | break; | |
8331 | } | |
8332 | ||
8333 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
8334 | s = strchr (insn->name, '.'); | |
8335 | if (argnum == 2) | |
8336 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
8337 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
8338 | } | |
8339 | ||
8340 | /* Single-precision coprocessor loads and moves are OK too. */ | |
8341 | if ((insn->pinfo & FP_S) | |
8342 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
8343 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
8344 | return 1; | |
8345 | ||
8346 | return 0; | |
8347 | } | |
8348 | ||
252b5132 RH |
8349 | /* This routine assembles an instruction into its binary format. As a |
8350 | side effect, it sets one of the global variables imm_reloc or | |
8351 | offset_reloc to the type of relocation to do if one of the operands | |
8352 | is an address expression. */ | |
8353 | ||
8354 | static void | |
17a2f251 | 8355 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8356 | { |
8357 | char *s; | |
8358 | const char *args; | |
43841e91 | 8359 | char c = 0; |
252b5132 RH |
8360 | struct mips_opcode *insn; |
8361 | char *argsStart; | |
8362 | unsigned int regno; | |
8363 | unsigned int lastregno = 0; | |
af7ee8bf | 8364 | unsigned int lastpos = 0; |
071742cf | 8365 | unsigned int limlo, limhi; |
252b5132 RH |
8366 | char *s_reset; |
8367 | char save_c = 0; | |
74cd071d | 8368 | offsetT min_range, max_range; |
707bfff6 TS |
8369 | int argnum; |
8370 | unsigned int rtype; | |
252b5132 RH |
8371 | |
8372 | insn_error = NULL; | |
8373 | ||
8374 | /* If the instruction contains a '.', we first try to match an instruction | |
8375 | including the '.'. Then we try again without the '.'. */ | |
8376 | insn = NULL; | |
3882b010 | 8377 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8378 | continue; |
8379 | ||
8380 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8381 | the call to hash_find. Save the character we replaced just in case we | |
8382 | have to re-parse the instruction. */ | |
3882b010 | 8383 | if (ISSPACE (*s)) |
252b5132 RH |
8384 | { |
8385 | save_c = *s; | |
8386 | *s++ = '\0'; | |
8387 | } | |
bdaaa2e1 | 8388 | |
252b5132 RH |
8389 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8390 | ||
8391 | /* If we didn't find the instruction in the opcode table, try again, but | |
8392 | this time with just the instruction up to, but not including the | |
8393 | first '.'. */ | |
8394 | if (insn == NULL) | |
8395 | { | |
bdaaa2e1 | 8396 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8397 | if (save_c) |
8398 | *(--s) = save_c; | |
8399 | ||
8400 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8401 | for (s = str; |
8402 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8403 | ++s) | |
252b5132 RH |
8404 | continue; |
8405 | ||
8406 | /* If we did not find a '.', then we can quit now. */ | |
8407 | if (*s != '.') | |
8408 | { | |
8409 | insn_error = "unrecognized opcode"; | |
8410 | return; | |
8411 | } | |
8412 | ||
8413 | /* Lookup the instruction in the hash table. */ | |
8414 | *s++ = '\0'; | |
8415 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8416 | { | |
8417 | insn_error = "unrecognized opcode"; | |
8418 | return; | |
8419 | } | |
252b5132 RH |
8420 | } |
8421 | ||
8422 | argsStart = s; | |
8423 | for (;;) | |
8424 | { | |
b34976b6 | 8425 | bfd_boolean ok; |
252b5132 RH |
8426 | |
8427 | assert (strcmp (insn->name, str) == 0); | |
8428 | ||
1f25f5d3 CD |
8429 | if (OPCODE_IS_MEMBER (insn, |
8430 | (mips_opts.isa | |
9b3f89ee TS |
8431 | /* We don't check for mips_opts.mips16 here since |
8432 | we want to allow jalx if -mips16 was specified | |
8433 | on the command line. */ | |
3396de36 | 8434 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 8435 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
74cd071d | 8436 | | (mips_opts.ase_dsp ? INSN_DSP : 0) |
65263ce3 TS |
8437 | | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) |
8438 | ? INSN_DSP64 : 0) | |
8b082fb1 | 8439 | | (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0) |
ef2e4d86 | 8440 | | (mips_opts.ase_mt ? INSN_MT : 0) |
e16bfa71 TS |
8441 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0) |
8442 | | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)), | |
fef14a42 | 8443 | mips_opts.arch)) |
b34976b6 | 8444 | ok = TRUE; |
bdaaa2e1 | 8445 | else |
b34976b6 | 8446 | ok = FALSE; |
bdaaa2e1 | 8447 | |
252b5132 RH |
8448 | if (insn->pinfo != INSN_MACRO) |
8449 | { | |
fef14a42 | 8450 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 8451 | ok = FALSE; |
252b5132 RH |
8452 | } |
8453 | ||
8454 | if (! ok) | |
8455 | { | |
8456 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8457 | && strcmp (insn->name, insn[1].name) == 0) | |
8458 | { | |
8459 | ++insn; | |
8460 | continue; | |
8461 | } | |
252b5132 | 8462 | else |
beae10d5 | 8463 | { |
268f6bed L |
8464 | if (!insn_error) |
8465 | { | |
8466 | static char buf[100]; | |
fef14a42 TS |
8467 | sprintf (buf, |
8468 | _("opcode not supported on this processor: %s (%s)"), | |
8469 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8470 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8471 | insn_error = buf; |
8472 | } | |
8473 | if (save_c) | |
8474 | *(--s) = save_c; | |
2bd7f1f3 | 8475 | return; |
252b5132 | 8476 | } |
252b5132 RH |
8477 | } |
8478 | ||
1e915849 | 8479 | create_insn (ip, insn); |
268f6bed | 8480 | insn_error = NULL; |
707bfff6 | 8481 | argnum = 1; |
252b5132 RH |
8482 | for (args = insn->args;; ++args) |
8483 | { | |
deec1734 CD |
8484 | int is_mdmx; |
8485 | ||
ad8d3bb3 | 8486 | s += strspn (s, " \t"); |
deec1734 | 8487 | is_mdmx = 0; |
252b5132 RH |
8488 | switch (*args) |
8489 | { | |
8490 | case '\0': /* end of args */ | |
8491 | if (*s == '\0') | |
8492 | return; | |
8493 | break; | |
8494 | ||
8b082fb1 TS |
8495 | case '2': /* dsp 2-bit unsigned immediate in bit 11 */ |
8496 | my_getExpression (&imm_expr, s); | |
8497 | check_absolute_expr (ip, &imm_expr); | |
8498 | if ((unsigned long) imm_expr.X_add_number != 1 | |
8499 | && (unsigned long) imm_expr.X_add_number != 3) | |
8500 | { | |
8501 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
8502 | (unsigned long) imm_expr.X_add_number); | |
8503 | } | |
8504 | INSERT_OPERAND (BP, *ip, imm_expr.X_add_number); | |
8505 | imm_expr.X_op = O_absent; | |
8506 | s = expr_end; | |
8507 | continue; | |
8508 | ||
74cd071d CF |
8509 | case '3': /* dsp 3-bit unsigned immediate in bit 21 */ |
8510 | my_getExpression (&imm_expr, s); | |
8511 | check_absolute_expr (ip, &imm_expr); | |
8512 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
8513 | { | |
a9e24354 TS |
8514 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8515 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8516 | } |
a9e24354 | 8517 | INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number); |
74cd071d CF |
8518 | imm_expr.X_op = O_absent; |
8519 | s = expr_end; | |
8520 | continue; | |
8521 | ||
8522 | case '4': /* dsp 4-bit unsigned immediate in bit 21 */ | |
8523 | my_getExpression (&imm_expr, s); | |
8524 | check_absolute_expr (ip, &imm_expr); | |
8525 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
8526 | { | |
a9e24354 TS |
8527 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8528 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8529 | } |
a9e24354 | 8530 | INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number); |
74cd071d CF |
8531 | imm_expr.X_op = O_absent; |
8532 | s = expr_end; | |
8533 | continue; | |
8534 | ||
8535 | case '5': /* dsp 8-bit unsigned immediate in bit 16 */ | |
8536 | my_getExpression (&imm_expr, s); | |
8537 | check_absolute_expr (ip, &imm_expr); | |
8538 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
8539 | { | |
a9e24354 TS |
8540 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8541 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8542 | } |
a9e24354 | 8543 | INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number); |
74cd071d CF |
8544 | imm_expr.X_op = O_absent; |
8545 | s = expr_end; | |
8546 | continue; | |
8547 | ||
8548 | case '6': /* dsp 5-bit unsigned immediate in bit 21 */ | |
8549 | my_getExpression (&imm_expr, s); | |
8550 | check_absolute_expr (ip, &imm_expr); | |
8551 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
8552 | { | |
a9e24354 TS |
8553 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8554 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8555 | } |
a9e24354 | 8556 | INSERT_OPERAND (RS, *ip, imm_expr.X_add_number); |
74cd071d CF |
8557 | imm_expr.X_op = O_absent; |
8558 | s = expr_end; | |
8559 | continue; | |
8560 | ||
8561 | case '7': /* four dsp accumulators in bits 11,12 */ | |
8562 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8563 | s[3] >= '0' && s[3] <= '3') | |
8564 | { | |
8565 | regno = s[3] - '0'; | |
8566 | s += 4; | |
a9e24354 | 8567 | INSERT_OPERAND (DSPACC, *ip, regno); |
74cd071d CF |
8568 | continue; |
8569 | } | |
8570 | else | |
8571 | as_bad (_("Invalid dsp acc register")); | |
8572 | break; | |
8573 | ||
8574 | case '8': /* dsp 6-bit unsigned immediate in bit 11 */ | |
8575 | my_getExpression (&imm_expr, s); | |
8576 | check_absolute_expr (ip, &imm_expr); | |
8577 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
8578 | { | |
a9e24354 TS |
8579 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8580 | OP_MASK_WRDSP, | |
8581 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8582 | } |
a9e24354 | 8583 | INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8584 | imm_expr.X_op = O_absent; |
8585 | s = expr_end; | |
8586 | continue; | |
8587 | ||
8588 | case '9': /* four dsp accumulators in bits 21,22 */ | |
8589 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8590 | s[3] >= '0' && s[3] <= '3') | |
8591 | { | |
8592 | regno = s[3] - '0'; | |
8593 | s += 4; | |
a9e24354 | 8594 | INSERT_OPERAND (DSPACC_S, *ip, regno); |
74cd071d CF |
8595 | continue; |
8596 | } | |
8597 | else | |
8598 | as_bad (_("Invalid dsp acc register")); | |
8599 | break; | |
8600 | ||
8601 | case '0': /* dsp 6-bit signed immediate in bit 20 */ | |
8602 | my_getExpression (&imm_expr, s); | |
8603 | check_absolute_expr (ip, &imm_expr); | |
8604 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
8605 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
8606 | if (imm_expr.X_add_number < min_range || | |
8607 | imm_expr.X_add_number > max_range) | |
8608 | { | |
a9e24354 TS |
8609 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8610 | (long) min_range, (long) max_range, | |
8611 | (long) imm_expr.X_add_number); | |
74cd071d | 8612 | } |
a9e24354 | 8613 | INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number); |
74cd071d CF |
8614 | imm_expr.X_op = O_absent; |
8615 | s = expr_end; | |
8616 | continue; | |
8617 | ||
8618 | case '\'': /* dsp 6-bit unsigned immediate in bit 16 */ | |
8619 | my_getExpression (&imm_expr, s); | |
8620 | check_absolute_expr (ip, &imm_expr); | |
8621 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
8622 | { | |
a9e24354 TS |
8623 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8624 | OP_MASK_RDDSP, | |
8625 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8626 | } |
a9e24354 | 8627 | INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8628 | imm_expr.X_op = O_absent; |
8629 | s = expr_end; | |
8630 | continue; | |
8631 | ||
8632 | case ':': /* dsp 7-bit signed immediate in bit 19 */ | |
8633 | my_getExpression (&imm_expr, s); | |
8634 | check_absolute_expr (ip, &imm_expr); | |
8635 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
8636 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
8637 | if (imm_expr.X_add_number < min_range || | |
8638 | imm_expr.X_add_number > max_range) | |
8639 | { | |
a9e24354 TS |
8640 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8641 | (long) min_range, (long) max_range, | |
8642 | (long) imm_expr.X_add_number); | |
74cd071d | 8643 | } |
a9e24354 | 8644 | INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
8645 | imm_expr.X_op = O_absent; |
8646 | s = expr_end; | |
8647 | continue; | |
8648 | ||
8649 | case '@': /* dsp 10-bit signed immediate in bit 16 */ | |
8650 | my_getExpression (&imm_expr, s); | |
8651 | check_absolute_expr (ip, &imm_expr); | |
8652 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
8653 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
8654 | if (imm_expr.X_add_number < min_range || | |
8655 | imm_expr.X_add_number > max_range) | |
8656 | { | |
a9e24354 TS |
8657 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8658 | (long) min_range, (long) max_range, | |
8659 | (long) imm_expr.X_add_number); | |
74cd071d | 8660 | } |
a9e24354 | 8661 | INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number); |
74cd071d CF |
8662 | imm_expr.X_op = O_absent; |
8663 | s = expr_end; | |
8664 | continue; | |
8665 | ||
a9e24354 | 8666 | case '!': /* MT usermode flag bit. */ |
ef2e4d86 CF |
8667 | my_getExpression (&imm_expr, s); |
8668 | check_absolute_expr (ip, &imm_expr); | |
8669 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
8670 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
8671 | (unsigned long) imm_expr.X_add_number); | |
8672 | INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8673 | imm_expr.X_op = O_absent; |
8674 | s = expr_end; | |
8675 | continue; | |
8676 | ||
a9e24354 | 8677 | case '$': /* MT load high flag bit. */ |
ef2e4d86 CF |
8678 | my_getExpression (&imm_expr, s); |
8679 | check_absolute_expr (ip, &imm_expr); | |
8680 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
8681 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
8682 | (unsigned long) imm_expr.X_add_number); | |
8683 | INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8684 | imm_expr.X_op = O_absent; |
8685 | s = expr_end; | |
8686 | continue; | |
8687 | ||
8688 | case '*': /* four dsp accumulators in bits 18,19 */ | |
8689 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8690 | s[3] >= '0' && s[3] <= '3') | |
8691 | { | |
8692 | regno = s[3] - '0'; | |
8693 | s += 4; | |
a9e24354 | 8694 | INSERT_OPERAND (MTACC_T, *ip, regno); |
ef2e4d86 CF |
8695 | continue; |
8696 | } | |
8697 | else | |
8698 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8699 | break; | |
8700 | ||
8701 | case '&': /* four dsp accumulators in bits 13,14 */ | |
8702 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8703 | s[3] >= '0' && s[3] <= '3') | |
8704 | { | |
8705 | regno = s[3] - '0'; | |
8706 | s += 4; | |
a9e24354 | 8707 | INSERT_OPERAND (MTACC_D, *ip, regno); |
ef2e4d86 CF |
8708 | continue; |
8709 | } | |
8710 | else | |
8711 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8712 | break; | |
8713 | ||
252b5132 | 8714 | case ',': |
a339155f | 8715 | ++argnum; |
252b5132 RH |
8716 | if (*s++ == *args) |
8717 | continue; | |
8718 | s--; | |
8719 | switch (*++args) | |
8720 | { | |
8721 | case 'r': | |
8722 | case 'v': | |
bf12938e | 8723 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8724 | continue; |
8725 | ||
8726 | case 'w': | |
bf12938e | 8727 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
8728 | continue; |
8729 | ||
252b5132 | 8730 | case 'W': |
bf12938e | 8731 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8732 | continue; |
8733 | ||
8734 | case 'V': | |
bf12938e | 8735 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8736 | continue; |
8737 | } | |
8738 | break; | |
8739 | ||
8740 | case '(': | |
8741 | /* Handle optional base register. | |
8742 | Either the base register is omitted or | |
bdaaa2e1 | 8743 | we must have a left paren. */ |
252b5132 RH |
8744 | /* This is dependent on the next operand specifier |
8745 | is a base register specification. */ | |
8746 | assert (args[1] == 'b' || args[1] == '5' | |
8747 | || args[1] == '-' || args[1] == '4'); | |
8748 | if (*s == '\0') | |
8749 | return; | |
8750 | ||
8751 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8752 | case '[': |
8753 | case ']': | |
252b5132 RH |
8754 | if (*s++ == *args) |
8755 | continue; | |
8756 | break; | |
8757 | ||
af7ee8bf CD |
8758 | case '+': /* Opcode extension character. */ |
8759 | switch (*++args) | |
8760 | { | |
9bcd4f99 TS |
8761 | case '1': /* UDI immediates. */ |
8762 | case '2': | |
8763 | case '3': | |
8764 | case '4': | |
8765 | { | |
8766 | const struct mips_immed *imm = mips_immed; | |
8767 | ||
8768 | while (imm->type && imm->type != *args) | |
8769 | ++imm; | |
8770 | if (! imm->type) | |
8771 | internalError (); | |
8772 | my_getExpression (&imm_expr, s); | |
8773 | check_absolute_expr (ip, &imm_expr); | |
8774 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
8775 | { | |
8776 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
8777 | imm->desc ? imm->desc : ip->insn_mo->name, | |
8778 | (unsigned long) imm_expr.X_add_number, | |
8779 | (unsigned long) imm_expr.X_add_number); | |
8780 | imm_expr.X_add_number &= imm->mask; | |
8781 | } | |
8782 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
8783 | << imm->shift); | |
8784 | imm_expr.X_op = O_absent; | |
8785 | s = expr_end; | |
8786 | } | |
8787 | continue; | |
8788 | ||
071742cf CD |
8789 | case 'A': /* ins/ext position, becomes LSB. */ |
8790 | limlo = 0; | |
8791 | limhi = 31; | |
5f74bc13 CD |
8792 | goto do_lsb; |
8793 | case 'E': | |
8794 | limlo = 32; | |
8795 | limhi = 63; | |
8796 | goto do_lsb; | |
8797 | do_lsb: | |
071742cf CD |
8798 | my_getExpression (&imm_expr, s); |
8799 | check_absolute_expr (ip, &imm_expr); | |
8800 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8801 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8802 | { | |
8803 | as_bad (_("Improper position (%lu)"), | |
8804 | (unsigned long) imm_expr.X_add_number); | |
8805 | imm_expr.X_add_number = limlo; | |
8806 | } | |
8807 | lastpos = imm_expr.X_add_number; | |
bf12938e | 8808 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
8809 | imm_expr.X_op = O_absent; |
8810 | s = expr_end; | |
8811 | continue; | |
8812 | ||
8813 | case 'B': /* ins size, becomes MSB. */ | |
8814 | limlo = 1; | |
8815 | limhi = 32; | |
5f74bc13 CD |
8816 | goto do_msb; |
8817 | case 'F': | |
8818 | limlo = 33; | |
8819 | limhi = 64; | |
8820 | goto do_msb; | |
8821 | do_msb: | |
071742cf CD |
8822 | my_getExpression (&imm_expr, s); |
8823 | check_absolute_expr (ip, &imm_expr); | |
8824 | /* Check for negative input so that small negative numbers | |
8825 | will not succeed incorrectly. The checks against | |
8826 | (pos+size) transitively check "size" itself, | |
8827 | assuming that "pos" is reasonable. */ | |
8828 | if ((long) imm_expr.X_add_number < 0 | |
8829 | || ((unsigned long) imm_expr.X_add_number | |
8830 | + lastpos) < limlo | |
8831 | || ((unsigned long) imm_expr.X_add_number | |
8832 | + lastpos) > limhi) | |
8833 | { | |
8834 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8835 | (unsigned long) imm_expr.X_add_number, | |
8836 | (unsigned long) lastpos); | |
8837 | imm_expr.X_add_number = limlo - lastpos; | |
8838 | } | |
bf12938e RS |
8839 | INSERT_OPERAND (INSMSB, *ip, |
8840 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
8841 | imm_expr.X_op = O_absent; |
8842 | s = expr_end; | |
8843 | continue; | |
8844 | ||
8845 | case 'C': /* ext size, becomes MSBD. */ | |
8846 | limlo = 1; | |
8847 | limhi = 32; | |
5f74bc13 CD |
8848 | goto do_msbd; |
8849 | case 'G': | |
8850 | limlo = 33; | |
8851 | limhi = 64; | |
8852 | goto do_msbd; | |
8853 | case 'H': | |
8854 | limlo = 33; | |
8855 | limhi = 64; | |
8856 | goto do_msbd; | |
8857 | do_msbd: | |
071742cf CD |
8858 | my_getExpression (&imm_expr, s); |
8859 | check_absolute_expr (ip, &imm_expr); | |
8860 | /* Check for negative input so that small negative numbers | |
8861 | will not succeed incorrectly. The checks against | |
8862 | (pos+size) transitively check "size" itself, | |
8863 | assuming that "pos" is reasonable. */ | |
8864 | if ((long) imm_expr.X_add_number < 0 | |
8865 | || ((unsigned long) imm_expr.X_add_number | |
8866 | + lastpos) < limlo | |
8867 | || ((unsigned long) imm_expr.X_add_number | |
8868 | + lastpos) > limhi) | |
8869 | { | |
8870 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8871 | (unsigned long) imm_expr.X_add_number, | |
8872 | (unsigned long) lastpos); | |
8873 | imm_expr.X_add_number = limlo - lastpos; | |
8874 | } | |
bf12938e | 8875 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
8876 | imm_expr.X_op = O_absent; |
8877 | s = expr_end; | |
8878 | continue; | |
af7ee8bf | 8879 | |
bbcc0807 CD |
8880 | case 'D': |
8881 | /* +D is for disassembly only; never match. */ | |
8882 | break; | |
8883 | ||
5f74bc13 CD |
8884 | case 'I': |
8885 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8886 | my_getExpression (&imm2_expr, s); | |
8887 | if (imm2_expr.X_op != O_big | |
8888 | && imm2_expr.X_op != O_constant) | |
8889 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
8890 | if (HAVE_32BIT_GPRS) |
8891 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
8892 | s = expr_end; |
8893 | continue; | |
8894 | ||
707bfff6 | 8895 | case 'T': /* Coprocessor register. */ |
ef2e4d86 CF |
8896 | /* +T is for disassembly only; never match. */ |
8897 | break; | |
8898 | ||
707bfff6 | 8899 | case 't': /* Coprocessor register number. */ |
ef2e4d86 CF |
8900 | if (s[0] == '$' && ISDIGIT (s[1])) |
8901 | { | |
8902 | ++s; | |
8903 | regno = 0; | |
8904 | do | |
8905 | { | |
8906 | regno *= 10; | |
8907 | regno += *s - '0'; | |
8908 | ++s; | |
8909 | } | |
8910 | while (ISDIGIT (*s)); | |
8911 | if (regno > 31) | |
8912 | as_bad (_("Invalid register number (%d)"), regno); | |
8913 | else | |
8914 | { | |
a9e24354 | 8915 | INSERT_OPERAND (RT, *ip, regno); |
ef2e4d86 CF |
8916 | continue; |
8917 | } | |
8918 | } | |
8919 | else | |
8920 | as_bad (_("Invalid coprocessor 0 register number")); | |
8921 | break; | |
8922 | ||
af7ee8bf CD |
8923 | default: |
8924 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8925 | *args, insn->name, insn->args); | |
8926 | /* Further processing is fruitless. */ | |
8927 | return; | |
8928 | } | |
8929 | break; | |
8930 | ||
252b5132 RH |
8931 | case '<': /* must be at least one digit */ |
8932 | /* | |
8933 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8934 | * than 31 or less than 0, then the shift amount should be |
8935 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8936 | * We issue a warning and mask out all but the low 5 bits. |
8937 | */ | |
8938 | my_getExpression (&imm_expr, s); | |
8939 | check_absolute_expr (ip, &imm_expr); | |
8940 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8941 | as_warn (_("Improper shift amount (%lu)"), |
8942 | (unsigned long) imm_expr.X_add_number); | |
8943 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8944 | imm_expr.X_op = O_absent; |
8945 | s = expr_end; | |
8946 | continue; | |
8947 | ||
8948 | case '>': /* shift amount minus 32 */ | |
8949 | my_getExpression (&imm_expr, s); | |
8950 | check_absolute_expr (ip, &imm_expr); | |
8951 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8952 | || (unsigned long) imm_expr.X_add_number > 63) | |
8953 | break; | |
bf12938e | 8954 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
8955 | imm_expr.X_op = O_absent; |
8956 | s = expr_end; | |
8957 | continue; | |
8958 | ||
252b5132 RH |
8959 | case 'k': /* cache code */ |
8960 | case 'h': /* prefx code */ | |
8961 | my_getExpression (&imm_expr, s); | |
8962 | check_absolute_expr (ip, &imm_expr); | |
8963 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8964 | as_warn (_("Invalid value for `%s' (%lu)"), |
8965 | ip->insn_mo->name, | |
8966 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 8967 | if (*args == 'k') |
bf12938e | 8968 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); |
252b5132 | 8969 | else |
bf12938e | 8970 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
252b5132 RH |
8971 | imm_expr.X_op = O_absent; |
8972 | s = expr_end; | |
8973 | continue; | |
8974 | ||
8975 | case 'c': /* break code */ | |
8976 | my_getExpression (&imm_expr, s); | |
8977 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
8978 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE) |
8979 | as_warn (_("Code for %s not in range 0..1023 (%lu)"), | |
8980 | ip->insn_mo->name, | |
bf12938e RS |
8981 | (unsigned long) imm_expr.X_add_number); |
8982 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8983 | imm_expr.X_op = O_absent; |
8984 | s = expr_end; | |
8985 | continue; | |
8986 | ||
8987 | case 'q': /* lower break code */ | |
8988 | my_getExpression (&imm_expr, s); | |
8989 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
8990 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2) |
8991 | as_warn (_("Lower code for %s not in range 0..1023 (%lu)"), | |
8992 | ip->insn_mo->name, | |
bf12938e RS |
8993 | (unsigned long) imm_expr.X_add_number); |
8994 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8995 | imm_expr.X_op = O_absent; |
8996 | s = expr_end; | |
8997 | continue; | |
8998 | ||
4372b673 | 8999 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 9000 | my_getExpression (&imm_expr, s); |
156c2f8b | 9001 | check_absolute_expr (ip, &imm_expr); |
793b27f4 | 9002 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
a9e24354 TS |
9003 | as_warn (_("Code for %s not in range 0..1048575 (%lu)"), |
9004 | ip->insn_mo->name, | |
793b27f4 | 9005 | (unsigned long) imm_expr.X_add_number); |
bf12938e | 9006 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
9007 | imm_expr.X_op = O_absent; |
9008 | s = expr_end; | |
9009 | continue; | |
9010 | ||
98d3f06f | 9011 | case 'C': /* Coprocessor code */ |
beae10d5 | 9012 | my_getExpression (&imm_expr, s); |
252b5132 | 9013 | check_absolute_expr (ip, &imm_expr); |
a9e24354 | 9014 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ) |
252b5132 | 9015 | { |
793b27f4 TS |
9016 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
9017 | (unsigned long) imm_expr.X_add_number); | |
a9e24354 | 9018 | imm_expr.X_add_number &= OP_MASK_COPZ; |
252b5132 | 9019 | } |
a9e24354 | 9020 | INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number); |
beae10d5 KH |
9021 | imm_expr.X_op = O_absent; |
9022 | s = expr_end; | |
9023 | continue; | |
252b5132 | 9024 | |
4372b673 NC |
9025 | case 'J': /* 19-bit wait code. */ |
9026 | my_getExpression (&imm_expr, s); | |
9027 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 9028 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
a9e24354 TS |
9029 | { |
9030 | as_warn (_("Illegal 19-bit code (%lu)"), | |
9031 | (unsigned long) imm_expr.X_add_number); | |
9032 | imm_expr.X_add_number &= OP_MASK_CODE19; | |
9033 | } | |
bf12938e | 9034 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
9035 | imm_expr.X_op = O_absent; |
9036 | s = expr_end; | |
9037 | continue; | |
9038 | ||
707bfff6 | 9039 | case 'P': /* Performance register. */ |
beae10d5 | 9040 | my_getExpression (&imm_expr, s); |
252b5132 | 9041 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 9042 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
9043 | as_warn (_("Invalid performance register (%lu)"), |
9044 | (unsigned long) imm_expr.X_add_number); | |
9045 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
9046 | imm_expr.X_op = O_absent; |
9047 | s = expr_end; | |
9048 | continue; | |
252b5132 | 9049 | |
707bfff6 TS |
9050 | case 'G': /* Coprocessor destination register. */ |
9051 | if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0) | |
9052 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no); | |
9053 | else | |
9054 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
a9e24354 | 9055 | INSERT_OPERAND (RD, *ip, regno); |
707bfff6 TS |
9056 | if (ok) |
9057 | { | |
9058 | lastregno = regno; | |
9059 | continue; | |
9060 | } | |
9061 | else | |
9062 | break; | |
9063 | ||
252b5132 RH |
9064 | case 'b': /* base register */ |
9065 | case 'd': /* destination register */ | |
9066 | case 's': /* source register */ | |
9067 | case 't': /* target register */ | |
9068 | case 'r': /* both target and source */ | |
9069 | case 'v': /* both dest and source */ | |
9070 | case 'w': /* both dest and target */ | |
9071 | case 'E': /* coprocessor target register */ | |
af7ee8bf | 9072 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
9073 | case 'x': /* ignore register name */ |
9074 | case 'z': /* must be zero register */ | |
4372b673 | 9075 | case 'U': /* destination register (clo/clz). */ |
ef2e4d86 | 9076 | case 'g': /* coprocessor destination register */ |
707bfff6 TS |
9077 | s_reset = s; |
9078 | if (*args == 'E' || *args == 'K') | |
9079 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
9080 | else | |
9081 | { | |
9082 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
9083 | if (regno == AT && ! mips_opts.noat) | |
9084 | as_warn ("Used $at without \".set noat\""); | |
9085 | } | |
9086 | if (ok) | |
252b5132 | 9087 | { |
252b5132 RH |
9088 | c = *args; |
9089 | if (*s == ' ') | |
f9419b05 | 9090 | ++s; |
252b5132 RH |
9091 | if (args[1] != *s) |
9092 | { | |
9093 | if (c == 'r' || c == 'v' || c == 'w') | |
9094 | { | |
9095 | regno = lastregno; | |
9096 | s = s_reset; | |
f9419b05 | 9097 | ++args; |
252b5132 RH |
9098 | } |
9099 | } | |
9100 | /* 'z' only matches $0. */ | |
9101 | if (c == 'z' && regno != 0) | |
9102 | break; | |
9103 | ||
bdaaa2e1 KH |
9104 | /* Now that we have assembled one operand, we use the args string |
9105 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
9106 | switch (c) |
9107 | { | |
9108 | case 'r': | |
9109 | case 's': | |
9110 | case 'v': | |
9111 | case 'b': | |
bf12938e | 9112 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
9113 | break; |
9114 | case 'd': | |
9115 | case 'G': | |
af7ee8bf | 9116 | case 'K': |
ef2e4d86 | 9117 | case 'g': |
bf12938e | 9118 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 9119 | break; |
4372b673 | 9120 | case 'U': |
bf12938e RS |
9121 | INSERT_OPERAND (RD, *ip, regno); |
9122 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 9123 | break; |
252b5132 RH |
9124 | case 'w': |
9125 | case 't': | |
9126 | case 'E': | |
bf12938e | 9127 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
9128 | break; |
9129 | case 'x': | |
9130 | /* This case exists because on the r3000 trunc | |
9131 | expands into a macro which requires a gp | |
9132 | register. On the r6000 or r4000 it is | |
9133 | assembled into a single instruction which | |
9134 | ignores the register. Thus the insn version | |
9135 | is MIPS_ISA2 and uses 'x', and the macro | |
9136 | version is MIPS_ISA1 and uses 't'. */ | |
9137 | break; | |
9138 | case 'z': | |
9139 | /* This case is for the div instruction, which | |
9140 | acts differently if the destination argument | |
9141 | is $0. This only matches $0, and is checked | |
9142 | outside the switch. */ | |
9143 | break; | |
9144 | case 'D': | |
9145 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
9146 | break; | |
9147 | /* What about all other operands like 'i', which | |
9148 | can be specified in the opcode table? */ | |
9149 | } | |
9150 | lastregno = regno; | |
9151 | continue; | |
9152 | } | |
252b5132 RH |
9153 | switch (*args++) |
9154 | { | |
9155 | case 'r': | |
9156 | case 'v': | |
bf12938e | 9157 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9158 | continue; |
9159 | case 'w': | |
bf12938e | 9160 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
9161 | continue; |
9162 | } | |
9163 | break; | |
9164 | ||
deec1734 CD |
9165 | case 'O': /* MDMX alignment immediate constant. */ |
9166 | my_getExpression (&imm_expr, s); | |
9167 | check_absolute_expr (ip, &imm_expr); | |
9168 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
bf12938e RS |
9169 | as_warn ("Improper align amount (%ld), using low bits", |
9170 | (long) imm_expr.X_add_number); | |
9171 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9172 | imm_expr.X_op = O_absent; |
9173 | s = expr_end; | |
9174 | continue; | |
9175 | ||
9176 | case 'Q': /* MDMX vector, element sel, or const. */ | |
9177 | if (s[0] != '$') | |
9178 | { | |
9179 | /* MDMX Immediate. */ | |
9180 | my_getExpression (&imm_expr, s); | |
9181 | check_absolute_expr (ip, &imm_expr); | |
9182 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
9183 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
9184 | (long) imm_expr.X_add_number); | |
9185 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9186 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
9187 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
9188 | else | |
9189 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
9190 | imm_expr.X_op = O_absent; |
9191 | s = expr_end; | |
9192 | continue; | |
9193 | } | |
9194 | /* Not MDMX Immediate. Fall through. */ | |
9195 | case 'X': /* MDMX destination register. */ | |
9196 | case 'Y': /* MDMX source register. */ | |
9197 | case 'Z': /* MDMX target register. */ | |
9198 | is_mdmx = 1; | |
252b5132 RH |
9199 | case 'D': /* floating point destination register */ |
9200 | case 'S': /* floating point source register */ | |
9201 | case 'T': /* floating point target register */ | |
9202 | case 'R': /* floating point source register */ | |
9203 | case 'V': | |
9204 | case 'W': | |
707bfff6 TS |
9205 | rtype = RTYPE_FPU; |
9206 | if (is_mdmx | |
9207 | || (mips_opts.ase_mdmx | |
9208 | && (ip->insn_mo->pinfo & FP_D) | |
9209 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
9210 | | INSN_COPROC_MEMORY_DELAY | |
9211 | | INSN_LOAD_COPROC_DELAY | |
9212 | | INSN_LOAD_MEMORY_DELAY | |
9213 | | INSN_STORE_MEMORY)))) | |
9214 | rtype |= RTYPE_VEC; | |
252b5132 | 9215 | s_reset = s; |
707bfff6 | 9216 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 9217 | { |
252b5132 | 9218 | if ((regno & 1) != 0 |
ca4e0257 | 9219 | && HAVE_32BIT_FPRS |
7455baf8 | 9220 | && ! mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
9221 | as_warn (_("Float register should be even, was %d"), |
9222 | regno); | |
9223 | ||
9224 | c = *args; | |
9225 | if (*s == ' ') | |
f9419b05 | 9226 | ++s; |
252b5132 RH |
9227 | if (args[1] != *s) |
9228 | { | |
9229 | if (c == 'V' || c == 'W') | |
9230 | { | |
9231 | regno = lastregno; | |
9232 | s = s_reset; | |
f9419b05 | 9233 | ++args; |
252b5132 RH |
9234 | } |
9235 | } | |
9236 | switch (c) | |
9237 | { | |
9238 | case 'D': | |
deec1734 | 9239 | case 'X': |
bf12938e | 9240 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
9241 | break; |
9242 | case 'V': | |
9243 | case 'S': | |
deec1734 | 9244 | case 'Y': |
bf12938e | 9245 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 9246 | break; |
deec1734 CD |
9247 | case 'Q': |
9248 | /* This is like 'Z', but also needs to fix the MDMX | |
9249 | vector/scalar select bits. Note that the | |
9250 | scalar immediate case is handled above. */ | |
9251 | if (*s == '[') | |
9252 | { | |
9253 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
9254 | int max_el = (is_qh ? 3 : 7); | |
9255 | s++; | |
9256 | my_getExpression(&imm_expr, s); | |
9257 | check_absolute_expr (ip, &imm_expr); | |
9258 | s = expr_end; | |
9259 | if (imm_expr.X_add_number > max_el) | |
9260 | as_bad(_("Bad element selector %ld"), | |
9261 | (long) imm_expr.X_add_number); | |
9262 | imm_expr.X_add_number &= max_el; | |
9263 | ip->insn_opcode |= (imm_expr.X_add_number | |
9264 | << (OP_SH_VSEL + | |
9265 | (is_qh ? 2 : 1))); | |
01a3f561 | 9266 | imm_expr.X_op = O_absent; |
deec1734 CD |
9267 | if (*s != ']') |
9268 | as_warn(_("Expecting ']' found '%s'"), s); | |
9269 | else | |
9270 | s++; | |
9271 | } | |
9272 | else | |
9273 | { | |
9274 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
9275 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
9276 | << OP_SH_VSEL); | |
9277 | else | |
9278 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
9279 | OP_SH_VSEL); | |
9280 | } | |
9281 | /* Fall through */ | |
252b5132 RH |
9282 | case 'W': |
9283 | case 'T': | |
deec1734 | 9284 | case 'Z': |
bf12938e | 9285 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
9286 | break; |
9287 | case 'R': | |
bf12938e | 9288 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
9289 | break; |
9290 | } | |
9291 | lastregno = regno; | |
9292 | continue; | |
9293 | } | |
9294 | ||
252b5132 RH |
9295 | switch (*args++) |
9296 | { | |
9297 | case 'V': | |
bf12938e | 9298 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9299 | continue; |
9300 | case 'W': | |
bf12938e | 9301 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9302 | continue; |
9303 | } | |
9304 | break; | |
9305 | ||
9306 | case 'I': | |
9307 | my_getExpression (&imm_expr, s); | |
9308 | if (imm_expr.X_op != O_big | |
9309 | && imm_expr.X_op != O_constant) | |
9310 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9311 | if (HAVE_32BIT_GPRS) |
9312 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
9313 | s = expr_end; |
9314 | continue; | |
9315 | ||
9316 | case 'A': | |
9317 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 9318 | normalize_address_expr (&offset_expr); |
f6688943 | 9319 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
9320 | s = expr_end; |
9321 | continue; | |
9322 | ||
9323 | case 'F': | |
9324 | case 'L': | |
9325 | case 'f': | |
9326 | case 'l': | |
9327 | { | |
9328 | int f64; | |
ca4e0257 | 9329 | int using_gprs; |
252b5132 RH |
9330 | char *save_in; |
9331 | char *err; | |
9332 | unsigned char temp[8]; | |
9333 | int len; | |
9334 | unsigned int length; | |
9335 | segT seg; | |
9336 | subsegT subseg; | |
9337 | char *p; | |
9338 | ||
9339 | /* These only appear as the last operand in an | |
9340 | instruction, and every instruction that accepts | |
9341 | them in any variant accepts them in all variants. | |
9342 | This means we don't have to worry about backing out | |
9343 | any changes if the instruction does not match. | |
9344 | ||
9345 | The difference between them is the size of the | |
9346 | floating point constant and where it goes. For 'F' | |
9347 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
9348 | is 32 bits. Where the constant is placed is based | |
9349 | on how the MIPS assembler does things: | |
9350 | F -- .rdata | |
9351 | L -- .lit8 | |
9352 | f -- immediate value | |
9353 | l -- .lit4 | |
9354 | ||
9355 | The .lit4 and .lit8 sections are only used if | |
9356 | permitted by the -G argument. | |
9357 | ||
ca4e0257 RS |
9358 | The code below needs to know whether the target register |
9359 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
9360 | 'F' are used with GPR-based instructions and 'l' and | |
9361 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
9362 | |
9363 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 9364 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
9365 | |
9366 | save_in = input_line_pointer; | |
9367 | input_line_pointer = s; | |
9368 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
9369 | length = len; | |
9370 | s = input_line_pointer; | |
9371 | input_line_pointer = save_in; | |
9372 | if (err != NULL && *err != '\0') | |
9373 | { | |
9374 | as_bad (_("Bad floating point constant: %s"), err); | |
9375 | memset (temp, '\0', sizeof temp); | |
9376 | length = f64 ? 8 : 4; | |
9377 | } | |
9378 | ||
156c2f8b | 9379 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
9380 | |
9381 | if (*args == 'f' | |
9382 | || (*args == 'l' | |
3e722fb5 | 9383 | && (g_switch_value < 4 |
252b5132 RH |
9384 | || (temp[0] == 0 && temp[1] == 0) |
9385 | || (temp[2] == 0 && temp[3] == 0)))) | |
9386 | { | |
9387 | imm_expr.X_op = O_constant; | |
9388 | if (! target_big_endian) | |
9389 | imm_expr.X_add_number = bfd_getl32 (temp); | |
9390 | else | |
9391 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9392 | } | |
9393 | else if (length > 4 | |
119d663a | 9394 | && ! mips_disable_float_construction |
ca4e0257 RS |
9395 | /* Constants can only be constructed in GPRs and |
9396 | copied to FPRs if the GPRs are at least as wide | |
9397 | as the FPRs. Force the constant into memory if | |
9398 | we are using 64-bit FPRs but the GPRs are only | |
9399 | 32 bits wide. */ | |
9400 | && (using_gprs | |
9401 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
9402 | && ((temp[0] == 0 && temp[1] == 0) |
9403 | || (temp[2] == 0 && temp[3] == 0)) | |
9404 | && ((temp[4] == 0 && temp[5] == 0) | |
9405 | || (temp[6] == 0 && temp[7] == 0))) | |
9406 | { | |
ca4e0257 RS |
9407 | /* The value is simple enough to load with a couple of |
9408 | instructions. If using 32-bit registers, set | |
9409 | imm_expr to the high order 32 bits and offset_expr to | |
9410 | the low order 32 bits. Otherwise, set imm_expr to | |
9411 | the entire 64 bit constant. */ | |
9412 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
9413 | { |
9414 | imm_expr.X_op = O_constant; | |
9415 | offset_expr.X_op = O_constant; | |
9416 | if (! target_big_endian) | |
9417 | { | |
9418 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
9419 | offset_expr.X_add_number = bfd_getl32 (temp); | |
9420 | } | |
9421 | else | |
9422 | { | |
9423 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9424 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
9425 | } | |
9426 | if (offset_expr.X_add_number == 0) | |
9427 | offset_expr.X_op = O_absent; | |
9428 | } | |
9429 | else if (sizeof (imm_expr.X_add_number) > 4) | |
9430 | { | |
9431 | imm_expr.X_op = O_constant; | |
9432 | if (! target_big_endian) | |
9433 | imm_expr.X_add_number = bfd_getl64 (temp); | |
9434 | else | |
9435 | imm_expr.X_add_number = bfd_getb64 (temp); | |
9436 | } | |
9437 | else | |
9438 | { | |
9439 | imm_expr.X_op = O_big; | |
9440 | imm_expr.X_add_number = 4; | |
9441 | if (! target_big_endian) | |
9442 | { | |
9443 | generic_bignum[0] = bfd_getl16 (temp); | |
9444 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
9445 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
9446 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
9447 | } | |
9448 | else | |
9449 | { | |
9450 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9451 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9452 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9453 | generic_bignum[3] = bfd_getb16 (temp); | |
9454 | } | |
9455 | } | |
9456 | } | |
9457 | else | |
9458 | { | |
9459 | const char *newname; | |
9460 | segT new_seg; | |
9461 | ||
9462 | /* Switch to the right section. */ | |
9463 | seg = now_seg; | |
9464 | subseg = now_subseg; | |
9465 | switch (*args) | |
9466 | { | |
9467 | default: /* unused default case avoids warnings. */ | |
9468 | case 'L': | |
9469 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 9470 | if (g_switch_value >= 8) |
252b5132 RH |
9471 | newname = ".lit8"; |
9472 | break; | |
9473 | case 'F': | |
3e722fb5 | 9474 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
9475 | break; |
9476 | case 'l': | |
4d0d148d | 9477 | assert (g_switch_value >= 4); |
252b5132 RH |
9478 | newname = ".lit4"; |
9479 | break; | |
9480 | } | |
9481 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 9482 | if (IS_ELF) |
252b5132 RH |
9483 | bfd_set_section_flags (stdoutput, new_seg, |
9484 | (SEC_ALLOC | |
9485 | | SEC_LOAD | |
9486 | | SEC_READONLY | |
9487 | | SEC_DATA)); | |
9488 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
f43abd2b | 9489 | if (IS_ELF && strcmp (TARGET_OS, "elf") != 0) |
252b5132 RH |
9490 | record_alignment (new_seg, 4); |
9491 | else | |
9492 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
9493 | if (seg == now_seg) | |
9494 | as_bad (_("Can't use floating point insn in this section")); | |
9495 | ||
9496 | /* Set the argument to the current address in the | |
9497 | section. */ | |
9498 | offset_expr.X_op = O_symbol; | |
9499 | offset_expr.X_add_symbol = | |
9500 | symbol_new ("L0\001", now_seg, | |
9501 | (valueT) frag_now_fix (), frag_now); | |
9502 | offset_expr.X_add_number = 0; | |
9503 | ||
9504 | /* Put the floating point number into the section. */ | |
9505 | p = frag_more ((int) length); | |
9506 | memcpy (p, temp, length); | |
9507 | ||
9508 | /* Switch back to the original section. */ | |
9509 | subseg_set (seg, subseg); | |
9510 | } | |
9511 | } | |
9512 | continue; | |
9513 | ||
9514 | case 'i': /* 16 bit unsigned immediate */ | |
9515 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 9516 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9517 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9518 | { |
9519 | int more; | |
5e0116d5 RS |
9520 | offsetT minval, maxval; |
9521 | ||
9522 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9523 | && strcmp (insn->name, insn[1].name) == 0); | |
9524 | ||
9525 | /* If the expression was written as an unsigned number, | |
9526 | only treat it as signed if there are no more | |
9527 | alternatives. */ | |
9528 | if (more | |
9529 | && *args == 'j' | |
9530 | && sizeof (imm_expr.X_add_number) <= 4 | |
9531 | && imm_expr.X_op == O_constant | |
9532 | && imm_expr.X_add_number < 0 | |
9533 | && imm_expr.X_unsigned | |
9534 | && HAVE_64BIT_GPRS) | |
9535 | break; | |
9536 | ||
9537 | /* For compatibility with older assemblers, we accept | |
9538 | 0x8000-0xffff as signed 16-bit numbers when only | |
9539 | signed numbers are allowed. */ | |
9540 | if (*args == 'i') | |
9541 | minval = 0, maxval = 0xffff; | |
9542 | else if (more) | |
9543 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9544 | else |
5e0116d5 RS |
9545 | minval = -0x8000, maxval = 0xffff; |
9546 | ||
9547 | if (imm_expr.X_op != O_constant | |
9548 | || imm_expr.X_add_number < minval | |
9549 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
9550 | { |
9551 | if (more) | |
9552 | break; | |
2ae7e77b AH |
9553 | if (imm_expr.X_op == O_constant |
9554 | || imm_expr.X_op == O_big) | |
5e0116d5 | 9555 | as_bad (_("expression out of range")); |
252b5132 RH |
9556 | } |
9557 | } | |
9558 | s = expr_end; | |
9559 | continue; | |
9560 | ||
9561 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
9562 | /* Check whether there is only a single bracketed expression |
9563 | left. If so, it must be the base register and the | |
9564 | constant must be zero. */ | |
9565 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
9566 | { | |
9567 | offset_expr.X_op = O_constant; | |
9568 | offset_expr.X_add_number = 0; | |
9569 | continue; | |
9570 | } | |
252b5132 RH |
9571 | |
9572 | /* If this value won't fit into a 16 bit offset, then go | |
9573 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9574 | code pattern. */ |
5e0116d5 | 9575 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
9576 | && (offset_expr.X_op != O_constant |
9577 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9578 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9579 | break; |
9580 | ||
252b5132 RH |
9581 | s = expr_end; |
9582 | continue; | |
9583 | ||
9584 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 9585 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9586 | my_getExpression (&offset_expr, s); |
9587 | s = expr_end; | |
9588 | continue; | |
9589 | ||
9590 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
9591 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
9592 | && imm_expr.X_op == O_constant | |
9593 | && (imm_expr.X_add_number < 0 | |
9594 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
9595 | as_bad (_("lui expression not in range 0..65535")); |
9596 | s = expr_end; | |
9597 | continue; | |
9598 | ||
9599 | case 'a': /* 26 bit address */ | |
9600 | my_getExpression (&offset_expr, s); | |
9601 | s = expr_end; | |
f6688943 | 9602 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
9603 | continue; |
9604 | ||
9605 | case 'N': /* 3 bit branch condition code */ | |
9606 | case 'M': /* 3 bit compare condition code */ | |
707bfff6 TS |
9607 | rtype = RTYPE_CCC; |
9608 | if (ip->insn_mo->pinfo & (FP_D| FP_S)) | |
9609 | rtype |= RTYPE_FCC; | |
9610 | if (!reg_lookup (&s, rtype, ®no)) | |
252b5132 | 9611 | break; |
30c378fd CD |
9612 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 |
9613 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
9614 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
9615 | && (regno & 1) != 0) | |
9616 | as_warn(_("Condition code register should be even for %s, was %d"), | |
9617 | str, regno); | |
9618 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
9619 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
9620 | && (regno & 3) != 0) | |
9621 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
9622 | str, regno); | |
252b5132 | 9623 | if (*args == 'N') |
bf12938e | 9624 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 9625 | else |
bf12938e | 9626 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 9627 | continue; |
252b5132 | 9628 | |
156c2f8b NC |
9629 | case 'H': |
9630 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9631 | s += 2; | |
3882b010 | 9632 | if (ISDIGIT (*s)) |
156c2f8b NC |
9633 | { |
9634 | c = 0; | |
9635 | do | |
9636 | { | |
9637 | c *= 10; | |
9638 | c += *s - '0'; | |
9639 | ++s; | |
9640 | } | |
3882b010 | 9641 | while (ISDIGIT (*s)); |
156c2f8b NC |
9642 | } |
9643 | else | |
9644 | c = 8; /* Invalid sel value. */ | |
9645 | ||
9646 | if (c > 7) | |
9647 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9648 | ip->insn_opcode |= c; | |
9649 | continue; | |
9650 | ||
60b63b72 RS |
9651 | case 'e': |
9652 | /* Must be at least one digit. */ | |
9653 | my_getExpression (&imm_expr, s); | |
9654 | check_absolute_expr (ip, &imm_expr); | |
9655 | ||
9656 | if ((unsigned long) imm_expr.X_add_number | |
9657 | > (unsigned long) OP_MASK_VECBYTE) | |
9658 | { | |
9659 | as_bad (_("bad byte vector index (%ld)"), | |
9660 | (long) imm_expr.X_add_number); | |
9661 | imm_expr.X_add_number = 0; | |
9662 | } | |
9663 | ||
bf12938e | 9664 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9665 | imm_expr.X_op = O_absent; |
9666 | s = expr_end; | |
9667 | continue; | |
9668 | ||
9669 | case '%': | |
9670 | my_getExpression (&imm_expr, s); | |
9671 | check_absolute_expr (ip, &imm_expr); | |
9672 | ||
9673 | if ((unsigned long) imm_expr.X_add_number | |
9674 | > (unsigned long) OP_MASK_VECALIGN) | |
9675 | { | |
9676 | as_bad (_("bad byte vector index (%ld)"), | |
9677 | (long) imm_expr.X_add_number); | |
9678 | imm_expr.X_add_number = 0; | |
9679 | } | |
9680 | ||
bf12938e | 9681 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9682 | imm_expr.X_op = O_absent; |
9683 | s = expr_end; | |
9684 | continue; | |
9685 | ||
252b5132 RH |
9686 | default: |
9687 | as_bad (_("bad char = '%c'\n"), *args); | |
9688 | internalError (); | |
9689 | } | |
9690 | break; | |
9691 | } | |
9692 | /* Args don't match. */ | |
9693 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9694 | !strcmp (insn->name, insn[1].name)) | |
9695 | { | |
9696 | ++insn; | |
9697 | s = argsStart; | |
268f6bed | 9698 | insn_error = _("illegal operands"); |
252b5132 RH |
9699 | continue; |
9700 | } | |
268f6bed L |
9701 | if (save_c) |
9702 | *(--s) = save_c; | |
252b5132 RH |
9703 | insn_error = _("illegal operands"); |
9704 | return; | |
9705 | } | |
9706 | } | |
9707 | ||
0499d65b TS |
9708 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
9709 | ||
252b5132 RH |
9710 | /* This routine assembles an instruction into its binary format when |
9711 | assembling for the mips16. As a side effect, it sets one of the | |
9712 | global variables imm_reloc or offset_reloc to the type of | |
9713 | relocation to do if one of the operands is an address expression. | |
9714 | It also sets mips16_small and mips16_ext if the user explicitly | |
9715 | requested a small or extended instruction. */ | |
9716 | ||
9717 | static void | |
17a2f251 | 9718 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9719 | { |
9720 | char *s; | |
9721 | const char *args; | |
9722 | struct mips_opcode *insn; | |
9723 | char *argsstart; | |
9724 | unsigned int regno; | |
9725 | unsigned int lastregno = 0; | |
9726 | char *s_reset; | |
d6f16593 | 9727 | size_t i; |
252b5132 RH |
9728 | |
9729 | insn_error = NULL; | |
9730 | ||
b34976b6 AM |
9731 | mips16_small = FALSE; |
9732 | mips16_ext = FALSE; | |
252b5132 | 9733 | |
3882b010 | 9734 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9735 | ; |
9736 | switch (*s) | |
9737 | { | |
9738 | case '\0': | |
9739 | break; | |
9740 | ||
9741 | case ' ': | |
9742 | *s++ = '\0'; | |
9743 | break; | |
9744 | ||
9745 | case '.': | |
9746 | if (s[1] == 't' && s[2] == ' ') | |
9747 | { | |
9748 | *s = '\0'; | |
b34976b6 | 9749 | mips16_small = TRUE; |
252b5132 RH |
9750 | s += 3; |
9751 | break; | |
9752 | } | |
9753 | else if (s[1] == 'e' && s[2] == ' ') | |
9754 | { | |
9755 | *s = '\0'; | |
b34976b6 | 9756 | mips16_ext = TRUE; |
252b5132 RH |
9757 | s += 3; |
9758 | break; | |
9759 | } | |
9760 | /* Fall through. */ | |
9761 | default: | |
9762 | insn_error = _("unknown opcode"); | |
9763 | return; | |
9764 | } | |
9765 | ||
9766 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9767 | mips16_small = TRUE; |
252b5132 RH |
9768 | |
9769 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9770 | { | |
9771 | insn_error = _("unrecognized opcode"); | |
9772 | return; | |
9773 | } | |
9774 | ||
9775 | argsstart = s; | |
9776 | for (;;) | |
9777 | { | |
9b3f89ee TS |
9778 | bfd_boolean ok; |
9779 | ||
252b5132 RH |
9780 | assert (strcmp (insn->name, str) == 0); |
9781 | ||
9b3f89ee TS |
9782 | if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_opts.arch)) |
9783 | ok = TRUE; | |
9784 | else | |
9785 | ok = FALSE; | |
9786 | ||
9787 | if (! ok) | |
9788 | { | |
9789 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
9790 | && strcmp (insn->name, insn[1].name) == 0) | |
9791 | { | |
9792 | ++insn; | |
9793 | continue; | |
9794 | } | |
9795 | else | |
9796 | { | |
9797 | if (!insn_error) | |
9798 | { | |
9799 | static char buf[100]; | |
9800 | sprintf (buf, | |
9801 | _("opcode not supported on this processor: %s (%s)"), | |
9802 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
9803 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
9804 | insn_error = buf; | |
9805 | } | |
9806 | return; | |
9807 | } | |
9808 | } | |
9809 | ||
1e915849 | 9810 | create_insn (ip, insn); |
252b5132 | 9811 | imm_expr.X_op = O_absent; |
f6688943 TS |
9812 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9813 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9814 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9815 | imm2_expr.X_op = O_absent; |
252b5132 | 9816 | offset_expr.X_op = O_absent; |
f6688943 TS |
9817 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9818 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9819 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9820 | for (args = insn->args; 1; ++args) |
9821 | { | |
9822 | int c; | |
9823 | ||
9824 | if (*s == ' ') | |
9825 | ++s; | |
9826 | ||
9827 | /* In this switch statement we call break if we did not find | |
9828 | a match, continue if we did find a match, or return if we | |
9829 | are done. */ | |
9830 | ||
9831 | c = *args; | |
9832 | switch (c) | |
9833 | { | |
9834 | case '\0': | |
9835 | if (*s == '\0') | |
9836 | { | |
9837 | /* Stuff the immediate value in now, if we can. */ | |
9838 | if (imm_expr.X_op == O_constant | |
f6688943 | 9839 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9840 | && insn->pinfo != INSN_MACRO) |
9841 | { | |
d6f16593 MR |
9842 | valueT tmp; |
9843 | ||
9844 | switch (*offset_reloc) | |
9845 | { | |
9846 | case BFD_RELOC_MIPS16_HI16_S: | |
9847 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
9848 | break; | |
9849 | ||
9850 | case BFD_RELOC_MIPS16_HI16: | |
9851 | tmp = imm_expr.X_add_number >> 16; | |
9852 | break; | |
9853 | ||
9854 | case BFD_RELOC_MIPS16_LO16: | |
9855 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
9856 | - 0x8000; | |
9857 | break; | |
9858 | ||
9859 | case BFD_RELOC_UNUSED: | |
9860 | tmp = imm_expr.X_add_number; | |
9861 | break; | |
9862 | ||
9863 | default: | |
9864 | internalError (); | |
9865 | } | |
9866 | *offset_reloc = BFD_RELOC_UNUSED; | |
9867 | ||
c4e7957c | 9868 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 9869 | tmp, TRUE, mips16_small, |
252b5132 RH |
9870 | mips16_ext, &ip->insn_opcode, |
9871 | &ip->use_extend, &ip->extend); | |
9872 | imm_expr.X_op = O_absent; | |
f6688943 | 9873 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9874 | } |
9875 | ||
9876 | return; | |
9877 | } | |
9878 | break; | |
9879 | ||
9880 | case ',': | |
9881 | if (*s++ == c) | |
9882 | continue; | |
9883 | s--; | |
9884 | switch (*++args) | |
9885 | { | |
9886 | case 'v': | |
bf12938e | 9887 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
9888 | continue; |
9889 | case 'w': | |
bf12938e | 9890 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9891 | continue; |
9892 | } | |
9893 | break; | |
9894 | ||
9895 | case '(': | |
9896 | case ')': | |
9897 | if (*s++ == c) | |
9898 | continue; | |
9899 | break; | |
9900 | ||
9901 | case 'v': | |
9902 | case 'w': | |
9903 | if (s[0] != '$') | |
9904 | { | |
9905 | if (c == 'v') | |
bf12938e | 9906 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 9907 | else |
bf12938e | 9908 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9909 | ++args; |
9910 | continue; | |
9911 | } | |
9912 | /* Fall through. */ | |
9913 | case 'x': | |
9914 | case 'y': | |
9915 | case 'z': | |
9916 | case 'Z': | |
9917 | case '0': | |
9918 | case 'S': | |
9919 | case 'R': | |
9920 | case 'X': | |
9921 | case 'Y': | |
707bfff6 TS |
9922 | s_reset = s; |
9923 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 9924 | { |
707bfff6 | 9925 | if (c == 'v' || c == 'w') |
85b51719 | 9926 | { |
707bfff6 | 9927 | if (c == 'v') |
a9e24354 | 9928 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 9929 | else |
a9e24354 | 9930 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
9931 | ++args; |
9932 | continue; | |
85b51719 | 9933 | } |
707bfff6 | 9934 | break; |
252b5132 RH |
9935 | } |
9936 | ||
9937 | if (*s == ' ') | |
9938 | ++s; | |
9939 | if (args[1] != *s) | |
9940 | { | |
9941 | if (c == 'v' || c == 'w') | |
9942 | { | |
9943 | regno = mips16_to_32_reg_map[lastregno]; | |
9944 | s = s_reset; | |
f9419b05 | 9945 | ++args; |
252b5132 RH |
9946 | } |
9947 | } | |
9948 | ||
9949 | switch (c) | |
9950 | { | |
9951 | case 'x': | |
9952 | case 'y': | |
9953 | case 'z': | |
9954 | case 'v': | |
9955 | case 'w': | |
9956 | case 'Z': | |
9957 | regno = mips32_to_16_reg_map[regno]; | |
9958 | break; | |
9959 | ||
9960 | case '0': | |
9961 | if (regno != 0) | |
9962 | regno = ILLEGAL_REG; | |
9963 | break; | |
9964 | ||
9965 | case 'S': | |
9966 | if (regno != SP) | |
9967 | regno = ILLEGAL_REG; | |
9968 | break; | |
9969 | ||
9970 | case 'R': | |
9971 | if (regno != RA) | |
9972 | regno = ILLEGAL_REG; | |
9973 | break; | |
9974 | ||
9975 | case 'X': | |
9976 | case 'Y': | |
9977 | if (regno == AT && ! mips_opts.noat) | |
9978 | as_warn (_("used $at without \".set noat\"")); | |
9979 | break; | |
9980 | ||
9981 | default: | |
9982 | internalError (); | |
9983 | } | |
9984 | ||
9985 | if (regno == ILLEGAL_REG) | |
9986 | break; | |
9987 | ||
9988 | switch (c) | |
9989 | { | |
9990 | case 'x': | |
9991 | case 'v': | |
bf12938e | 9992 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
9993 | break; |
9994 | case 'y': | |
9995 | case 'w': | |
bf12938e | 9996 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
9997 | break; |
9998 | case 'z': | |
bf12938e | 9999 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
10000 | break; |
10001 | case 'Z': | |
bf12938e | 10002 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
10003 | case '0': |
10004 | case 'S': | |
10005 | case 'R': | |
10006 | break; | |
10007 | case 'X': | |
bf12938e | 10008 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
10009 | break; |
10010 | case 'Y': | |
10011 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 10012 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
10013 | break; |
10014 | default: | |
10015 | internalError (); | |
10016 | } | |
10017 | ||
10018 | lastregno = regno; | |
10019 | continue; | |
10020 | ||
10021 | case 'P': | |
10022 | if (strncmp (s, "$pc", 3) == 0) | |
10023 | { | |
10024 | s += 3; | |
10025 | continue; | |
10026 | } | |
10027 | break; | |
10028 | ||
252b5132 RH |
10029 | case '5': |
10030 | case 'H': | |
10031 | case 'W': | |
10032 | case 'D': | |
10033 | case 'j': | |
252b5132 RH |
10034 | case 'V': |
10035 | case 'C': | |
10036 | case 'U': | |
10037 | case 'k': | |
10038 | case 'K': | |
d6f16593 MR |
10039 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
10040 | if (i > 0) | |
252b5132 | 10041 | { |
d6f16593 | 10042 | if (imm_expr.X_op != O_constant) |
252b5132 | 10043 | { |
b34976b6 | 10044 | mips16_ext = TRUE; |
b34976b6 | 10045 | ip->use_extend = TRUE; |
252b5132 | 10046 | ip->extend = 0; |
252b5132 | 10047 | } |
d6f16593 MR |
10048 | else |
10049 | { | |
10050 | /* We need to relax this instruction. */ | |
10051 | *offset_reloc = *imm_reloc; | |
10052 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
10053 | } | |
10054 | s = expr_end; | |
10055 | continue; | |
252b5132 | 10056 | } |
d6f16593 MR |
10057 | *imm_reloc = BFD_RELOC_UNUSED; |
10058 | /* Fall through. */ | |
10059 | case '<': | |
10060 | case '>': | |
10061 | case '[': | |
10062 | case ']': | |
10063 | case '4': | |
10064 | case '8': | |
10065 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
10066 | if (imm_expr.X_op == O_register) |
10067 | { | |
10068 | /* What we thought was an expression turned out to | |
10069 | be a register. */ | |
10070 | ||
10071 | if (s[0] == '(' && args[1] == '(') | |
10072 | { | |
10073 | /* It looks like the expression was omitted | |
10074 | before a register indirection, which means | |
10075 | that the expression is implicitly zero. We | |
10076 | still set up imm_expr, so that we handle | |
10077 | explicit extensions correctly. */ | |
10078 | imm_expr.X_op = O_constant; | |
10079 | imm_expr.X_add_number = 0; | |
f6688943 | 10080 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10081 | continue; |
10082 | } | |
10083 | ||
10084 | break; | |
10085 | } | |
10086 | ||
10087 | /* We need to relax this instruction. */ | |
f6688943 | 10088 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10089 | s = expr_end; |
10090 | continue; | |
10091 | ||
10092 | case 'p': | |
10093 | case 'q': | |
10094 | case 'A': | |
10095 | case 'B': | |
10096 | case 'E': | |
10097 | /* We use offset_reloc rather than imm_reloc for the PC | |
10098 | relative operands. This lets macros with both | |
10099 | immediate and address operands work correctly. */ | |
10100 | my_getExpression (&offset_expr, s); | |
10101 | ||
10102 | if (offset_expr.X_op == O_register) | |
10103 | break; | |
10104 | ||
10105 | /* We need to relax this instruction. */ | |
f6688943 | 10106 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10107 | s = expr_end; |
10108 | continue; | |
10109 | ||
10110 | case '6': /* break code */ | |
10111 | my_getExpression (&imm_expr, s); | |
10112 | check_absolute_expr (ip, &imm_expr); | |
10113 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
10114 | as_warn (_("Invalid value for `%s' (%lu)"), |
10115 | ip->insn_mo->name, | |
10116 | (unsigned long) imm_expr.X_add_number); | |
10117 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
10118 | imm_expr.X_op = O_absent; |
10119 | s = expr_end; | |
10120 | continue; | |
10121 | ||
10122 | case 'a': /* 26 bit address */ | |
10123 | my_getExpression (&offset_expr, s); | |
10124 | s = expr_end; | |
f6688943 | 10125 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
10126 | ip->insn_opcode <<= 16; |
10127 | continue; | |
10128 | ||
10129 | case 'l': /* register list for entry macro */ | |
10130 | case 'L': /* register list for exit macro */ | |
10131 | { | |
10132 | int mask; | |
10133 | ||
10134 | if (c == 'l') | |
10135 | mask = 0; | |
10136 | else | |
10137 | mask = 7 << 3; | |
10138 | while (*s != '\0') | |
10139 | { | |
707bfff6 | 10140 | unsigned int freg, reg1, reg2; |
252b5132 RH |
10141 | |
10142 | while (*s == ' ' || *s == ',') | |
10143 | ++s; | |
707bfff6 | 10144 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 10145 | freg = 0; |
707bfff6 TS |
10146 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
10147 | freg = 1; | |
252b5132 RH |
10148 | else |
10149 | { | |
707bfff6 TS |
10150 | as_bad (_("can't parse register list")); |
10151 | break; | |
252b5132 RH |
10152 | } |
10153 | if (*s == ' ') | |
10154 | ++s; | |
10155 | if (*s != '-') | |
10156 | reg2 = reg1; | |
10157 | else | |
10158 | { | |
10159 | ++s; | |
707bfff6 TS |
10160 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
10161 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 10162 | { |
707bfff6 TS |
10163 | as_bad (_("invalid register list")); |
10164 | break; | |
252b5132 RH |
10165 | } |
10166 | } | |
10167 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
10168 | { | |
10169 | mask &= ~ (7 << 3); | |
10170 | mask |= 5 << 3; | |
10171 | } | |
10172 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
10173 | { | |
10174 | mask &= ~ (7 << 3); | |
10175 | mask |= 6 << 3; | |
10176 | } | |
10177 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
10178 | mask |= (reg2 - 3) << 3; | |
10179 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
10180 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 10181 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
10182 | mask |= 1; |
10183 | else | |
10184 | { | |
10185 | as_bad (_("invalid register list")); | |
10186 | break; | |
10187 | } | |
10188 | } | |
10189 | /* The mask is filled in in the opcode table for the | |
10190 | benefit of the disassembler. We remove it before | |
10191 | applying the actual mask. */ | |
10192 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
10193 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
10194 | } | |
10195 | continue; | |
10196 | ||
0499d65b TS |
10197 | case 'm': /* Register list for save insn. */ |
10198 | case 'M': /* Register list for restore insn. */ | |
10199 | { | |
10200 | int opcode = 0; | |
10201 | int framesz = 0, seen_framesz = 0; | |
10202 | int args = 0, statics = 0, sregs = 0; | |
10203 | ||
10204 | while (*s != '\0') | |
10205 | { | |
10206 | unsigned int reg1, reg2; | |
10207 | ||
10208 | SKIP_SPACE_TABS (s); | |
10209 | while (*s == ',') | |
10210 | ++s; | |
10211 | SKIP_SPACE_TABS (s); | |
10212 | ||
10213 | my_getExpression (&imm_expr, s); | |
10214 | if (imm_expr.X_op == O_constant) | |
10215 | { | |
10216 | /* Handle the frame size. */ | |
10217 | if (seen_framesz) | |
10218 | { | |
10219 | as_bad (_("more than one frame size in list")); | |
10220 | break; | |
10221 | } | |
10222 | seen_framesz = 1; | |
10223 | framesz = imm_expr.X_add_number; | |
10224 | imm_expr.X_op = O_absent; | |
10225 | s = expr_end; | |
10226 | continue; | |
10227 | } | |
10228 | ||
707bfff6 | 10229 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
10230 | { |
10231 | as_bad (_("can't parse register list")); | |
10232 | break; | |
10233 | } | |
0499d65b | 10234 | |
707bfff6 TS |
10235 | while (*s == ' ') |
10236 | ++s; | |
10237 | ||
0499d65b TS |
10238 | if (*s != '-') |
10239 | reg2 = reg1; | |
10240 | else | |
10241 | { | |
10242 | ++s; | |
707bfff6 TS |
10243 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
10244 | || reg2 < reg1) | |
0499d65b TS |
10245 | { |
10246 | as_bad (_("can't parse register list")); | |
10247 | break; | |
10248 | } | |
0499d65b TS |
10249 | } |
10250 | ||
10251 | while (reg1 <= reg2) | |
10252 | { | |
10253 | if (reg1 >= 4 && reg1 <= 7) | |
10254 | { | |
3a93f742 | 10255 | if (!seen_framesz) |
0499d65b TS |
10256 | /* args $a0-$a3 */ |
10257 | args |= 1 << (reg1 - 4); | |
10258 | else | |
10259 | /* statics $a0-$a3 */ | |
10260 | statics |= 1 << (reg1 - 4); | |
10261 | } | |
10262 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
10263 | { | |
10264 | /* $s0-$s8 */ | |
10265 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
10266 | } | |
10267 | else if (reg1 == 31) | |
10268 | { | |
10269 | /* Add $ra to insn. */ | |
10270 | opcode |= 0x40; | |
10271 | } | |
10272 | else | |
10273 | { | |
10274 | as_bad (_("unexpected register in list")); | |
10275 | break; | |
10276 | } | |
10277 | if (++reg1 == 24) | |
10278 | reg1 = 30; | |
10279 | } | |
10280 | } | |
10281 | ||
10282 | /* Encode args/statics combination. */ | |
10283 | if (args & statics) | |
10284 | as_bad (_("arg/static registers overlap")); | |
10285 | else if (args == 0xf) | |
10286 | /* All $a0-$a3 are args. */ | |
10287 | opcode |= MIPS16_ALL_ARGS << 16; | |
10288 | else if (statics == 0xf) | |
10289 | /* All $a0-$a3 are statics. */ | |
10290 | opcode |= MIPS16_ALL_STATICS << 16; | |
10291 | else | |
10292 | { | |
10293 | int narg = 0, nstat = 0; | |
10294 | ||
10295 | /* Count arg registers. */ | |
10296 | while (args & 0x1) | |
10297 | { | |
10298 | args >>= 1; | |
10299 | narg++; | |
10300 | } | |
10301 | if (args != 0) | |
10302 | as_bad (_("invalid arg register list")); | |
10303 | ||
10304 | /* Count static registers. */ | |
10305 | while (statics & 0x8) | |
10306 | { | |
10307 | statics = (statics << 1) & 0xf; | |
10308 | nstat++; | |
10309 | } | |
10310 | if (statics != 0) | |
10311 | as_bad (_("invalid static register list")); | |
10312 | ||
10313 | /* Encode args/statics. */ | |
10314 | opcode |= ((narg << 2) | nstat) << 16; | |
10315 | } | |
10316 | ||
10317 | /* Encode $s0/$s1. */ | |
10318 | if (sregs & (1 << 0)) /* $s0 */ | |
10319 | opcode |= 0x20; | |
10320 | if (sregs & (1 << 1)) /* $s1 */ | |
10321 | opcode |= 0x10; | |
10322 | sregs >>= 2; | |
10323 | ||
10324 | if (sregs != 0) | |
10325 | { | |
10326 | /* Count regs $s2-$s8. */ | |
10327 | int nsreg = 0; | |
10328 | while (sregs & 1) | |
10329 | { | |
10330 | sregs >>= 1; | |
10331 | nsreg++; | |
10332 | } | |
10333 | if (sregs != 0) | |
10334 | as_bad (_("invalid static register list")); | |
10335 | /* Encode $s2-$s8. */ | |
10336 | opcode |= nsreg << 24; | |
10337 | } | |
10338 | ||
10339 | /* Encode frame size. */ | |
10340 | if (!seen_framesz) | |
10341 | as_bad (_("missing frame size")); | |
10342 | else if ((framesz & 7) != 0 || framesz < 0 | |
10343 | || framesz > 0xff * 8) | |
10344 | as_bad (_("invalid frame size")); | |
10345 | else if (framesz != 128 || (opcode >> 16) != 0) | |
10346 | { | |
10347 | framesz /= 8; | |
10348 | opcode |= (((framesz & 0xf0) << 16) | |
10349 | | (framesz & 0x0f)); | |
10350 | } | |
10351 | ||
10352 | /* Finally build the instruction. */ | |
10353 | if ((opcode >> 16) != 0 || framesz == 0) | |
10354 | { | |
10355 | ip->use_extend = TRUE; | |
10356 | ip->extend = opcode >> 16; | |
10357 | } | |
10358 | ip->insn_opcode |= opcode & 0x7f; | |
10359 | } | |
10360 | continue; | |
10361 | ||
252b5132 RH |
10362 | case 'e': /* extend code */ |
10363 | my_getExpression (&imm_expr, s); | |
10364 | check_absolute_expr (ip, &imm_expr); | |
10365 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
10366 | { | |
10367 | as_warn (_("Invalid value for `%s' (%lu)"), | |
10368 | ip->insn_mo->name, | |
10369 | (unsigned long) imm_expr.X_add_number); | |
10370 | imm_expr.X_add_number &= 0x7ff; | |
10371 | } | |
10372 | ip->insn_opcode |= imm_expr.X_add_number; | |
10373 | imm_expr.X_op = O_absent; | |
10374 | s = expr_end; | |
10375 | continue; | |
10376 | ||
10377 | default: | |
10378 | internalError (); | |
10379 | } | |
10380 | break; | |
10381 | } | |
10382 | ||
10383 | /* Args don't match. */ | |
10384 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
10385 | strcmp (insn->name, insn[1].name) == 0) | |
10386 | { | |
10387 | ++insn; | |
10388 | s = argsstart; | |
10389 | continue; | |
10390 | } | |
10391 | ||
10392 | insn_error = _("illegal operands"); | |
10393 | ||
10394 | return; | |
10395 | } | |
10396 | } | |
10397 | ||
10398 | /* This structure holds information we know about a mips16 immediate | |
10399 | argument type. */ | |
10400 | ||
e972090a NC |
10401 | struct mips16_immed_operand |
10402 | { | |
252b5132 RH |
10403 | /* The type code used in the argument string in the opcode table. */ |
10404 | int type; | |
10405 | /* The number of bits in the short form of the opcode. */ | |
10406 | int nbits; | |
10407 | /* The number of bits in the extended form of the opcode. */ | |
10408 | int extbits; | |
10409 | /* The amount by which the short form is shifted when it is used; | |
10410 | for example, the sw instruction has a shift count of 2. */ | |
10411 | int shift; | |
10412 | /* The amount by which the short form is shifted when it is stored | |
10413 | into the instruction code. */ | |
10414 | int op_shift; | |
10415 | /* Non-zero if the short form is unsigned. */ | |
10416 | int unsp; | |
10417 | /* Non-zero if the extended form is unsigned. */ | |
10418 | int extu; | |
10419 | /* Non-zero if the value is PC relative. */ | |
10420 | int pcrel; | |
10421 | }; | |
10422 | ||
10423 | /* The mips16 immediate operand types. */ | |
10424 | ||
10425 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
10426 | { | |
10427 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10428 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10429 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10430 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10431 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
10432 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10433 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10434 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10435 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10436 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
10437 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10438 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10439 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10440 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
10441 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10442 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10443 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10444 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10445 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
10446 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
10447 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
10448 | }; | |
10449 | ||
10450 | #define MIPS16_NUM_IMMED \ | |
10451 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
10452 | ||
10453 | /* Handle a mips16 instruction with an immediate value. This or's the | |
10454 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
10455 | whether an extended value is needed; if one is needed, it sets | |
10456 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
10457 | If SMALL is true, an unextended opcode was explicitly requested. | |
10458 | If EXT is true, an extended opcode was explicitly requested. If | |
10459 | WARN is true, warn if EXT does not match reality. */ | |
10460 | ||
10461 | static void | |
17a2f251 TS |
10462 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
10463 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
10464 | unsigned long *insn, bfd_boolean *use_extend, | |
10465 | unsigned short *extend) | |
252b5132 | 10466 | { |
3994f87e | 10467 | const struct mips16_immed_operand *op; |
252b5132 | 10468 | int mintiny, maxtiny; |
b34976b6 | 10469 | bfd_boolean needext; |
252b5132 RH |
10470 | |
10471 | op = mips16_immed_operands; | |
10472 | while (op->type != type) | |
10473 | { | |
10474 | ++op; | |
10475 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10476 | } | |
10477 | ||
10478 | if (op->unsp) | |
10479 | { | |
10480 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10481 | { | |
10482 | mintiny = 1; | |
10483 | maxtiny = 1 << op->nbits; | |
10484 | } | |
10485 | else | |
10486 | { | |
10487 | mintiny = 0; | |
10488 | maxtiny = (1 << op->nbits) - 1; | |
10489 | } | |
10490 | } | |
10491 | else | |
10492 | { | |
10493 | mintiny = - (1 << (op->nbits - 1)); | |
10494 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10495 | } | |
10496 | ||
10497 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10498 | if (type == 'p' || type == 'q') | |
10499 | val /= 2; | |
10500 | ||
10501 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10502 | || val < (mintiny << op->shift) | |
10503 | || val > (maxtiny << op->shift)) | |
b34976b6 | 10504 | needext = TRUE; |
252b5132 | 10505 | else |
b34976b6 | 10506 | needext = FALSE; |
252b5132 RH |
10507 | |
10508 | if (warn && ext && ! needext) | |
beae10d5 KH |
10509 | as_warn_where (file, line, |
10510 | _("extended operand requested but not required")); | |
252b5132 RH |
10511 | if (small && needext) |
10512 | as_bad_where (file, line, _("invalid unextended operand value")); | |
10513 | ||
10514 | if (small || (! ext && ! needext)) | |
10515 | { | |
10516 | int insnval; | |
10517 | ||
b34976b6 | 10518 | *use_extend = FALSE; |
252b5132 RH |
10519 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
10520 | insnval <<= op->op_shift; | |
10521 | *insn |= insnval; | |
10522 | } | |
10523 | else | |
10524 | { | |
10525 | long minext, maxext; | |
10526 | int extval; | |
10527 | ||
10528 | if (op->extu) | |
10529 | { | |
10530 | minext = 0; | |
10531 | maxext = (1 << op->extbits) - 1; | |
10532 | } | |
10533 | else | |
10534 | { | |
10535 | minext = - (1 << (op->extbits - 1)); | |
10536 | maxext = (1 << (op->extbits - 1)) - 1; | |
10537 | } | |
10538 | if (val < minext || val > maxext) | |
10539 | as_bad_where (file, line, | |
10540 | _("operand value out of range for instruction")); | |
10541 | ||
b34976b6 | 10542 | *use_extend = TRUE; |
252b5132 RH |
10543 | if (op->extbits == 16) |
10544 | { | |
10545 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
10546 | val &= 0x1f; | |
10547 | } | |
10548 | else if (op->extbits == 15) | |
10549 | { | |
10550 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
10551 | val &= 0xf; | |
10552 | } | |
10553 | else | |
10554 | { | |
10555 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
10556 | val = 0; | |
10557 | } | |
10558 | ||
10559 | *extend = (unsigned short) extval; | |
10560 | *insn |= val; | |
10561 | } | |
10562 | } | |
10563 | \f | |
d6f16593 | 10564 | struct percent_op_match |
ad8d3bb3 | 10565 | { |
5e0116d5 RS |
10566 | const char *str; |
10567 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
10568 | }; |
10569 | ||
10570 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 10571 | { |
5e0116d5 | 10572 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 10573 | #ifdef OBJ_ELF |
5e0116d5 RS |
10574 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
10575 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
10576 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
10577 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
10578 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
10579 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
10580 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
10581 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
10582 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
10583 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
10584 | {"%half", BFD_RELOC_16}, | |
10585 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
10586 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
10587 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
10588 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
10589 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
10590 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
10591 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
10592 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
10593 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
10594 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 10595 | #endif |
5e0116d5 | 10596 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
10597 | }; |
10598 | ||
d6f16593 MR |
10599 | static const struct percent_op_match mips16_percent_op[] = |
10600 | { | |
10601 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
10602 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
10603 | {"%hi", BFD_RELOC_MIPS16_HI16_S} | |
10604 | }; | |
10605 | ||
252b5132 | 10606 | |
5e0116d5 RS |
10607 | /* Return true if *STR points to a relocation operator. When returning true, |
10608 | move *STR over the operator and store its relocation code in *RELOC. | |
10609 | Leave both *STR and *RELOC alone when returning false. */ | |
10610 | ||
10611 | static bfd_boolean | |
17a2f251 | 10612 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 10613 | { |
d6f16593 MR |
10614 | const struct percent_op_match *percent_op; |
10615 | size_t limit, i; | |
10616 | ||
10617 | if (mips_opts.mips16) | |
10618 | { | |
10619 | percent_op = mips16_percent_op; | |
10620 | limit = ARRAY_SIZE (mips16_percent_op); | |
10621 | } | |
10622 | else | |
10623 | { | |
10624 | percent_op = mips_percent_op; | |
10625 | limit = ARRAY_SIZE (mips_percent_op); | |
10626 | } | |
76b3015f | 10627 | |
d6f16593 | 10628 | for (i = 0; i < limit; i++) |
5e0116d5 | 10629 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 10630 | { |
3f98094e DJ |
10631 | int len = strlen (percent_op[i].str); |
10632 | ||
10633 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
10634 | continue; | |
10635 | ||
5e0116d5 RS |
10636 | *str += strlen (percent_op[i].str); |
10637 | *reloc = percent_op[i].reloc; | |
394f9b3a | 10638 | |
5e0116d5 RS |
10639 | /* Check whether the output BFD supports this relocation. |
10640 | If not, issue an error and fall back on something safe. */ | |
10641 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 10642 | { |
5e0116d5 RS |
10643 | as_bad ("relocation %s isn't supported by the current ABI", |
10644 | percent_op[i].str); | |
01a3f561 | 10645 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 10646 | } |
5e0116d5 | 10647 | return TRUE; |
394f9b3a | 10648 | } |
5e0116d5 | 10649 | return FALSE; |
394f9b3a | 10650 | } |
ad8d3bb3 | 10651 | |
ad8d3bb3 | 10652 | |
5e0116d5 RS |
10653 | /* Parse string STR as a 16-bit relocatable operand. Store the |
10654 | expression in *EP and the relocations in the array starting | |
10655 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 10656 | |
01a3f561 | 10657 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 10658 | |
5e0116d5 | 10659 | static size_t |
17a2f251 TS |
10660 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
10661 | char *str) | |
ad8d3bb3 | 10662 | { |
5e0116d5 RS |
10663 | bfd_reloc_code_real_type reversed_reloc[3]; |
10664 | size_t reloc_index, i; | |
09b8f35a RS |
10665 | int crux_depth, str_depth; |
10666 | char *crux; | |
5e0116d5 RS |
10667 | |
10668 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
10669 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
10670 | of the main expression and with CRUX_DEPTH containing the number | |
10671 | of open brackets at that point. */ | |
10672 | reloc_index = -1; | |
10673 | str_depth = 0; | |
10674 | do | |
fb1b3232 | 10675 | { |
09b8f35a RS |
10676 | reloc_index++; |
10677 | crux = str; | |
10678 | crux_depth = str_depth; | |
10679 | ||
10680 | /* Skip over whitespace and brackets, keeping count of the number | |
10681 | of brackets. */ | |
10682 | while (*str == ' ' || *str == '\t' || *str == '(') | |
10683 | if (*str++ == '(') | |
10684 | str_depth++; | |
5e0116d5 | 10685 | } |
09b8f35a RS |
10686 | while (*str == '%' |
10687 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
10688 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 10689 | |
09b8f35a | 10690 | my_getExpression (ep, crux); |
5e0116d5 | 10691 | str = expr_end; |
394f9b3a | 10692 | |
5e0116d5 | 10693 | /* Match every open bracket. */ |
09b8f35a | 10694 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 10695 | if (*str++ == ')') |
09b8f35a | 10696 | crux_depth--; |
394f9b3a | 10697 | |
09b8f35a | 10698 | if (crux_depth > 0) |
5e0116d5 | 10699 | as_bad ("unclosed '('"); |
394f9b3a | 10700 | |
5e0116d5 | 10701 | expr_end = str; |
252b5132 | 10702 | |
01a3f561 | 10703 | if (reloc_index != 0) |
64bdfcaf RS |
10704 | { |
10705 | prev_reloc_op_frag = frag_now; | |
10706 | for (i = 0; i < reloc_index; i++) | |
10707 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
10708 | } | |
fb1b3232 | 10709 | |
5e0116d5 | 10710 | return reloc_index; |
252b5132 RH |
10711 | } |
10712 | ||
10713 | static void | |
17a2f251 | 10714 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
10715 | { |
10716 | char *save_in; | |
98aa84af | 10717 | valueT val; |
252b5132 RH |
10718 | |
10719 | save_in = input_line_pointer; | |
10720 | input_line_pointer = str; | |
10721 | expression (ep); | |
10722 | expr_end = input_line_pointer; | |
10723 | input_line_pointer = save_in; | |
10724 | ||
10725 | /* If we are in mips16 mode, and this is an expression based on `.', | |
10726 | then we bump the value of the symbol by 1 since that is how other | |
10727 | text symbols are handled. We don't bother to handle complex | |
10728 | expressions, just `.' plus or minus a constant. */ | |
10729 | if (mips_opts.mips16 | |
10730 | && ep->X_op == O_symbol | |
10731 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10732 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10733 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10734 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10735 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10736 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10737 | } |
10738 | ||
10739 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10740 | of type TYPE, and store the appropriate bytes in *LITP. The number |
10741 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
10742 | returned, or NULL on OK. */ |
10743 | ||
10744 | char * | |
17a2f251 | 10745 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
10746 | { |
10747 | int prec; | |
10748 | LITTLENUM_TYPE words[4]; | |
10749 | char *t; | |
10750 | int i; | |
10751 | ||
10752 | switch (type) | |
10753 | { | |
10754 | case 'f': | |
10755 | prec = 2; | |
10756 | break; | |
10757 | ||
10758 | case 'd': | |
10759 | prec = 4; | |
10760 | break; | |
10761 | ||
10762 | default: | |
10763 | *sizeP = 0; | |
10764 | return _("bad call to md_atof"); | |
10765 | } | |
10766 | ||
10767 | t = atof_ieee (input_line_pointer, type, words); | |
10768 | if (t) | |
10769 | input_line_pointer = t; | |
10770 | ||
10771 | *sizeP = prec * 2; | |
10772 | ||
10773 | if (! target_big_endian) | |
10774 | { | |
10775 | for (i = prec - 1; i >= 0; i--) | |
10776 | { | |
17a2f251 | 10777 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10778 | litP += 2; |
10779 | } | |
10780 | } | |
10781 | else | |
10782 | { | |
10783 | for (i = 0; i < prec; i++) | |
10784 | { | |
17a2f251 | 10785 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10786 | litP += 2; |
10787 | } | |
10788 | } | |
bdaaa2e1 | 10789 | |
252b5132 RH |
10790 | return NULL; |
10791 | } | |
10792 | ||
10793 | void | |
17a2f251 | 10794 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
10795 | { |
10796 | if (target_big_endian) | |
10797 | number_to_chars_bigendian (buf, val, n); | |
10798 | else | |
10799 | number_to_chars_littleendian (buf, val, n); | |
10800 | } | |
10801 | \f | |
ae948b86 | 10802 | #ifdef OBJ_ELF |
e013f690 TS |
10803 | static int support_64bit_objects(void) |
10804 | { | |
10805 | const char **list, **l; | |
aa3d8fdf | 10806 | int yes; |
e013f690 TS |
10807 | |
10808 | list = bfd_target_list (); | |
10809 | for (l = list; *l != NULL; l++) | |
10810 | #ifdef TE_TMIPS | |
10811 | /* This is traditional mips */ | |
10812 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10813 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10814 | #else | |
10815 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10816 | || strcmp (*l, "elf64-littlemips") == 0) | |
10817 | #endif | |
10818 | break; | |
aa3d8fdf | 10819 | yes = (*l != NULL); |
e013f690 | 10820 | free (list); |
aa3d8fdf | 10821 | return yes; |
e013f690 | 10822 | } |
ae948b86 | 10823 | #endif /* OBJ_ELF */ |
e013f690 | 10824 | |
78849248 | 10825 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 10826 | |
e972090a NC |
10827 | struct option md_longopts[] = |
10828 | { | |
f9b4148d CD |
10829 | /* Options which specify architecture. */ |
10830 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10831 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10832 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10833 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10834 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10835 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10836 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10837 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10838 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10839 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10840 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10841 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10842 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10843 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10844 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10845 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10846 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10847 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10848 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10849 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10850 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10851 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10852 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10853 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10854 | |
10855 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10856 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10857 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10858 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10859 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10860 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10861 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10862 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10863 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10864 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10865 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10866 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10867 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10868 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
74cd071d CF |
10869 | #define OPTION_DSP (OPTION_ASE_BASE + 6) |
10870 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
10871 | #define OPTION_NO_DSP (OPTION_ASE_BASE + 7) | |
10872 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
ef2e4d86 CF |
10873 | #define OPTION_MT (OPTION_ASE_BASE + 8) |
10874 | {"mmt", no_argument, NULL, OPTION_MT}, | |
10875 | #define OPTION_NO_MT (OPTION_ASE_BASE + 9) | |
10876 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
e16bfa71 TS |
10877 | #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10) |
10878 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
10879 | #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11) | |
10880 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
8b082fb1 TS |
10881 | #define OPTION_DSPR2 (OPTION_ASE_BASE + 12) |
10882 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, | |
10883 | #define OPTION_NO_DSPR2 (OPTION_ASE_BASE + 13) | |
10884 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, | |
f9b4148d CD |
10885 | |
10886 | /* Old-style architecture options. Don't add more of these. */ | |
8b082fb1 | 10887 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 14) |
f9b4148d CD |
10888 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) |
10889 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10890 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10891 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10892 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10893 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10894 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10895 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10896 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10897 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10898 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10899 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10900 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10901 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10902 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10903 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10904 | ||
10905 | /* Options which enable bug fixes. */ | |
10906 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10907 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10908 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10909 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10910 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10911 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
10912 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
10913 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
10914 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
10915 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
10916 | #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4) |
10917 | #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5) | |
10918 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
10919 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
f9b4148d CD |
10920 | |
10921 | /* Miscellaneous options. */ | |
7d8e00cf | 10922 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6) |
1ffcab4b | 10923 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
10924 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10925 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 10926 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
10927 | {"break", no_argument, NULL, OPTION_BREAK}, |
10928 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 10929 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 10930 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 10931 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 10932 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 10933 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 10934 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 10935 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 10936 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 10937 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 10938 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 10939 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10940 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 10941 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 10942 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 10943 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 10944 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
10945 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
10946 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
10947 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10948 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
10949 | #define OPTION_MSHARED (OPTION_MISC_BASE + 12) |
10950 | #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13) | |
10951 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
10952 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
10953 | #define OPTION_MSYM32 (OPTION_MISC_BASE + 14) |
10954 | #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15) | |
10955 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
10956 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
f9b4148d CD |
10957 | |
10958 | /* ELF-specific options. */ | |
156c2f8b | 10959 | #ifdef OBJ_ELF |
aed1a261 | 10960 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16) |
156c2f8b | 10961 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10962 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10963 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10964 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10965 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10966 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10967 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10968 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10969 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10970 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10971 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10972 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10973 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10974 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10975 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10976 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10977 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10978 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10979 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10980 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10981 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10982 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10983 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
0a44bf69 RS |
10984 | #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11) |
10985 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ae948b86 | 10986 | #endif /* OBJ_ELF */ |
f9b4148d | 10987 | |
252b5132 RH |
10988 | {NULL, no_argument, NULL, 0} |
10989 | }; | |
156c2f8b | 10990 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10991 | |
316f5878 RS |
10992 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10993 | NEW_VALUE. Warn if another value was already specified. Note: | |
10994 | we have to defer parsing the -march and -mtune arguments in order | |
10995 | to handle 'from-abi' correctly, since the ABI might be specified | |
10996 | in a later argument. */ | |
10997 | ||
10998 | static void | |
17a2f251 | 10999 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
11000 | { |
11001 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
11002 | as_warn (_("A different %s was already specified, is now %s"), | |
11003 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
11004 | new_value); | |
11005 | ||
11006 | *string_ptr = new_value; | |
11007 | } | |
11008 | ||
252b5132 | 11009 | int |
17a2f251 | 11010 | md_parse_option (int c, char *arg) |
252b5132 RH |
11011 | { |
11012 | switch (c) | |
11013 | { | |
119d663a NC |
11014 | case OPTION_CONSTRUCT_FLOATS: |
11015 | mips_disable_float_construction = 0; | |
11016 | break; | |
bdaaa2e1 | 11017 | |
119d663a NC |
11018 | case OPTION_NO_CONSTRUCT_FLOATS: |
11019 | mips_disable_float_construction = 1; | |
11020 | break; | |
bdaaa2e1 | 11021 | |
252b5132 RH |
11022 | case OPTION_TRAP: |
11023 | mips_trap = 1; | |
11024 | break; | |
11025 | ||
11026 | case OPTION_BREAK: | |
11027 | mips_trap = 0; | |
11028 | break; | |
11029 | ||
11030 | case OPTION_EB: | |
11031 | target_big_endian = 1; | |
11032 | break; | |
11033 | ||
11034 | case OPTION_EL: | |
11035 | target_big_endian = 0; | |
11036 | break; | |
11037 | ||
11038 | case 'O': | |
11039 | if (arg && arg[1] == '0') | |
11040 | mips_optimize = 1; | |
11041 | else | |
11042 | mips_optimize = 2; | |
11043 | break; | |
11044 | ||
11045 | case 'g': | |
11046 | if (arg == NULL) | |
11047 | mips_debug = 2; | |
11048 | else | |
11049 | mips_debug = atoi (arg); | |
252b5132 RH |
11050 | break; |
11051 | ||
11052 | case OPTION_MIPS1: | |
316f5878 | 11053 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
11054 | break; |
11055 | ||
11056 | case OPTION_MIPS2: | |
316f5878 | 11057 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
11058 | break; |
11059 | ||
11060 | case OPTION_MIPS3: | |
316f5878 | 11061 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
11062 | break; |
11063 | ||
11064 | case OPTION_MIPS4: | |
316f5878 | 11065 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
11066 | break; |
11067 | ||
84ea6cf2 | 11068 | case OPTION_MIPS5: |
316f5878 | 11069 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
11070 | break; |
11071 | ||
e7af610e | 11072 | case OPTION_MIPS32: |
316f5878 | 11073 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
11074 | break; |
11075 | ||
af7ee8bf CD |
11076 | case OPTION_MIPS32R2: |
11077 | file_mips_isa = ISA_MIPS32R2; | |
11078 | break; | |
11079 | ||
5f74bc13 CD |
11080 | case OPTION_MIPS64R2: |
11081 | file_mips_isa = ISA_MIPS64R2; | |
11082 | break; | |
11083 | ||
84ea6cf2 | 11084 | case OPTION_MIPS64: |
316f5878 | 11085 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
11086 | break; |
11087 | ||
ec68c924 | 11088 | case OPTION_MTUNE: |
316f5878 RS |
11089 | mips_set_option_string (&mips_tune_string, arg); |
11090 | break; | |
ec68c924 | 11091 | |
316f5878 RS |
11092 | case OPTION_MARCH: |
11093 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
11094 | break; |
11095 | ||
11096 | case OPTION_M4650: | |
316f5878 RS |
11097 | mips_set_option_string (&mips_arch_string, "4650"); |
11098 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
11099 | break; |
11100 | ||
11101 | case OPTION_NO_M4650: | |
11102 | break; | |
11103 | ||
11104 | case OPTION_M4010: | |
316f5878 RS |
11105 | mips_set_option_string (&mips_arch_string, "4010"); |
11106 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
11107 | break; |
11108 | ||
11109 | case OPTION_NO_M4010: | |
11110 | break; | |
11111 | ||
11112 | case OPTION_M4100: | |
316f5878 RS |
11113 | mips_set_option_string (&mips_arch_string, "4100"); |
11114 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
11115 | break; |
11116 | ||
11117 | case OPTION_NO_M4100: | |
11118 | break; | |
11119 | ||
252b5132 | 11120 | case OPTION_M3900: |
316f5878 RS |
11121 | mips_set_option_string (&mips_arch_string, "3900"); |
11122 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 11123 | break; |
bdaaa2e1 | 11124 | |
252b5132 RH |
11125 | case OPTION_NO_M3900: |
11126 | break; | |
11127 | ||
deec1734 CD |
11128 | case OPTION_MDMX: |
11129 | mips_opts.ase_mdmx = 1; | |
11130 | break; | |
11131 | ||
11132 | case OPTION_NO_MDMX: | |
11133 | mips_opts.ase_mdmx = 0; | |
11134 | break; | |
11135 | ||
74cd071d CF |
11136 | case OPTION_DSP: |
11137 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 11138 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
11139 | break; |
11140 | ||
11141 | case OPTION_NO_DSP: | |
8b082fb1 TS |
11142 | mips_opts.ase_dsp = 0; |
11143 | mips_opts.ase_dspr2 = 0; | |
11144 | break; | |
11145 | ||
11146 | case OPTION_DSPR2: | |
11147 | mips_opts.ase_dspr2 = 1; | |
11148 | mips_opts.ase_dsp = 1; | |
11149 | break; | |
11150 | ||
11151 | case OPTION_NO_DSPR2: | |
11152 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
11153 | mips_opts.ase_dsp = 0; |
11154 | break; | |
11155 | ||
ef2e4d86 CF |
11156 | case OPTION_MT: |
11157 | mips_opts.ase_mt = 1; | |
11158 | break; | |
11159 | ||
11160 | case OPTION_NO_MT: | |
11161 | mips_opts.ase_mt = 0; | |
11162 | break; | |
11163 | ||
252b5132 RH |
11164 | case OPTION_MIPS16: |
11165 | mips_opts.mips16 = 1; | |
7d10b47d | 11166 | mips_no_prev_insn (); |
252b5132 RH |
11167 | break; |
11168 | ||
11169 | case OPTION_NO_MIPS16: | |
11170 | mips_opts.mips16 = 0; | |
7d10b47d | 11171 | mips_no_prev_insn (); |
252b5132 RH |
11172 | break; |
11173 | ||
1f25f5d3 CD |
11174 | case OPTION_MIPS3D: |
11175 | mips_opts.ase_mips3d = 1; | |
11176 | break; | |
11177 | ||
11178 | case OPTION_NO_MIPS3D: | |
11179 | mips_opts.ase_mips3d = 0; | |
11180 | break; | |
11181 | ||
e16bfa71 TS |
11182 | case OPTION_SMARTMIPS: |
11183 | mips_opts.ase_smartmips = 1; | |
11184 | break; | |
11185 | ||
11186 | case OPTION_NO_SMARTMIPS: | |
11187 | mips_opts.ase_smartmips = 0; | |
11188 | break; | |
11189 | ||
d766e8ec RS |
11190 | case OPTION_FIX_VR4120: |
11191 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
11192 | break; |
11193 | ||
d766e8ec RS |
11194 | case OPTION_NO_FIX_VR4120: |
11195 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
11196 | break; |
11197 | ||
7d8e00cf RS |
11198 | case OPTION_FIX_VR4130: |
11199 | mips_fix_vr4130 = 1; | |
11200 | break; | |
11201 | ||
11202 | case OPTION_NO_FIX_VR4130: | |
11203 | mips_fix_vr4130 = 0; | |
11204 | break; | |
11205 | ||
4a6a3df4 AO |
11206 | case OPTION_RELAX_BRANCH: |
11207 | mips_relax_branch = 1; | |
11208 | break; | |
11209 | ||
11210 | case OPTION_NO_RELAX_BRANCH: | |
11211 | mips_relax_branch = 0; | |
11212 | break; | |
11213 | ||
aa6975fb ILT |
11214 | case OPTION_MSHARED: |
11215 | mips_in_shared = TRUE; | |
11216 | break; | |
11217 | ||
11218 | case OPTION_MNO_SHARED: | |
11219 | mips_in_shared = FALSE; | |
11220 | break; | |
11221 | ||
aed1a261 RS |
11222 | case OPTION_MSYM32: |
11223 | mips_opts.sym32 = TRUE; | |
11224 | break; | |
11225 | ||
11226 | case OPTION_MNO_SYM32: | |
11227 | mips_opts.sym32 = FALSE; | |
11228 | break; | |
11229 | ||
0f074f60 | 11230 | #ifdef OBJ_ELF |
252b5132 RH |
11231 | /* When generating ELF code, we permit -KPIC and -call_shared to |
11232 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
11233 | intended to be compatible with Irix 5. */ | |
11234 | case OPTION_CALL_SHARED: | |
f43abd2b | 11235 | if (!IS_ELF) |
252b5132 RH |
11236 | { |
11237 | as_bad (_("-call_shared is supported only for ELF format")); | |
11238 | return 0; | |
11239 | } | |
11240 | mips_pic = SVR4_PIC; | |
143d77c5 | 11241 | mips_abicalls = TRUE; |
252b5132 RH |
11242 | break; |
11243 | ||
11244 | case OPTION_NON_SHARED: | |
f43abd2b | 11245 | if (!IS_ELF) |
252b5132 RH |
11246 | { |
11247 | as_bad (_("-non_shared is supported only for ELF format")); | |
11248 | return 0; | |
11249 | } | |
11250 | mips_pic = NO_PIC; | |
143d77c5 | 11251 | mips_abicalls = FALSE; |
252b5132 RH |
11252 | break; |
11253 | ||
44075ae2 TS |
11254 | /* The -xgot option tells the assembler to use 32 bit offsets |
11255 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
11256 | compatibility. */ |
11257 | case OPTION_XGOT: | |
11258 | mips_big_got = 1; | |
11259 | break; | |
0f074f60 | 11260 | #endif /* OBJ_ELF */ |
252b5132 RH |
11261 | |
11262 | case 'G': | |
6caf9ef4 TS |
11263 | g_switch_value = atoi (arg); |
11264 | g_switch_seen = 1; | |
252b5132 RH |
11265 | break; |
11266 | ||
0f074f60 | 11267 | #ifdef OBJ_ELF |
34ba82a8 TS |
11268 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
11269 | and -mabi=64. */ | |
252b5132 | 11270 | case OPTION_32: |
f43abd2b | 11271 | if (!IS_ELF) |
34ba82a8 TS |
11272 | { |
11273 | as_bad (_("-32 is supported for ELF format only")); | |
11274 | return 0; | |
11275 | } | |
316f5878 | 11276 | mips_abi = O32_ABI; |
252b5132 RH |
11277 | break; |
11278 | ||
e013f690 | 11279 | case OPTION_N32: |
f43abd2b | 11280 | if (!IS_ELF) |
34ba82a8 TS |
11281 | { |
11282 | as_bad (_("-n32 is supported for ELF format only")); | |
11283 | return 0; | |
11284 | } | |
316f5878 | 11285 | mips_abi = N32_ABI; |
e013f690 | 11286 | break; |
252b5132 | 11287 | |
e013f690 | 11288 | case OPTION_64: |
f43abd2b | 11289 | if (!IS_ELF) |
34ba82a8 TS |
11290 | { |
11291 | as_bad (_("-64 is supported for ELF format only")); | |
11292 | return 0; | |
11293 | } | |
316f5878 | 11294 | mips_abi = N64_ABI; |
f43abd2b | 11295 | if (!support_64bit_objects()) |
e013f690 | 11296 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 11297 | break; |
ae948b86 | 11298 | #endif /* OBJ_ELF */ |
252b5132 | 11299 | |
c97ef257 | 11300 | case OPTION_GP32: |
a325df1d | 11301 | file_mips_gp32 = 1; |
c97ef257 AH |
11302 | break; |
11303 | ||
11304 | case OPTION_GP64: | |
a325df1d | 11305 | file_mips_gp32 = 0; |
c97ef257 | 11306 | break; |
252b5132 | 11307 | |
ca4e0257 | 11308 | case OPTION_FP32: |
a325df1d | 11309 | file_mips_fp32 = 1; |
316f5878 RS |
11310 | break; |
11311 | ||
11312 | case OPTION_FP64: | |
11313 | file_mips_fp32 = 0; | |
ca4e0257 RS |
11314 | break; |
11315 | ||
ae948b86 | 11316 | #ifdef OBJ_ELF |
252b5132 | 11317 | case OPTION_MABI: |
f43abd2b | 11318 | if (!IS_ELF) |
34ba82a8 TS |
11319 | { |
11320 | as_bad (_("-mabi is supported for ELF format only")); | |
11321 | return 0; | |
11322 | } | |
e013f690 | 11323 | if (strcmp (arg, "32") == 0) |
316f5878 | 11324 | mips_abi = O32_ABI; |
e013f690 | 11325 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 11326 | mips_abi = O64_ABI; |
e013f690 | 11327 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 11328 | mips_abi = N32_ABI; |
e013f690 TS |
11329 | else if (strcmp (arg, "64") == 0) |
11330 | { | |
316f5878 | 11331 | mips_abi = N64_ABI; |
e013f690 TS |
11332 | if (! support_64bit_objects()) |
11333 | as_fatal (_("No compiled in support for 64 bit object file " | |
11334 | "format")); | |
11335 | } | |
11336 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 11337 | mips_abi = EABI_ABI; |
e013f690 | 11338 | else |
da0e507f TS |
11339 | { |
11340 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
11341 | return 0; | |
11342 | } | |
252b5132 | 11343 | break; |
e013f690 | 11344 | #endif /* OBJ_ELF */ |
252b5132 | 11345 | |
6b76fefe | 11346 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 11347 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
11348 | break; |
11349 | ||
9ee72ff1 | 11350 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 11351 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
11352 | break; |
11353 | ||
ecb4347a DJ |
11354 | #ifdef OBJ_ELF |
11355 | case OPTION_MDEBUG: | |
b34976b6 | 11356 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
11357 | break; |
11358 | ||
11359 | case OPTION_NO_MDEBUG: | |
b34976b6 | 11360 | mips_flag_mdebug = FALSE; |
ecb4347a | 11361 | break; |
dcd410fe RO |
11362 | |
11363 | case OPTION_PDR: | |
11364 | mips_flag_pdr = TRUE; | |
11365 | break; | |
11366 | ||
11367 | case OPTION_NO_PDR: | |
11368 | mips_flag_pdr = FALSE; | |
11369 | break; | |
0a44bf69 RS |
11370 | |
11371 | case OPTION_MVXWORKS_PIC: | |
11372 | mips_pic = VXWORKS_PIC; | |
11373 | break; | |
ecb4347a DJ |
11374 | #endif /* OBJ_ELF */ |
11375 | ||
252b5132 RH |
11376 | default: |
11377 | return 0; | |
11378 | } | |
11379 | ||
11380 | return 1; | |
11381 | } | |
316f5878 RS |
11382 | \f |
11383 | /* Set up globals to generate code for the ISA or processor | |
11384 | described by INFO. */ | |
252b5132 | 11385 | |
252b5132 | 11386 | static void |
17a2f251 | 11387 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 11388 | { |
316f5878 | 11389 | if (info != 0) |
252b5132 | 11390 | { |
fef14a42 TS |
11391 | file_mips_arch = info->cpu; |
11392 | mips_opts.arch = info->cpu; | |
316f5878 | 11393 | mips_opts.isa = info->isa; |
252b5132 | 11394 | } |
252b5132 RH |
11395 | } |
11396 | ||
252b5132 | 11397 | |
316f5878 | 11398 | /* Likewise for tuning. */ |
252b5132 | 11399 | |
316f5878 | 11400 | static void |
17a2f251 | 11401 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
11402 | { |
11403 | if (info != 0) | |
fef14a42 | 11404 | mips_tune = info->cpu; |
316f5878 | 11405 | } |
80cc45a5 | 11406 | |
34ba82a8 | 11407 | |
252b5132 | 11408 | void |
17a2f251 | 11409 | mips_after_parse_args (void) |
e9670677 | 11410 | { |
fef14a42 TS |
11411 | const struct mips_cpu_info *arch_info = 0; |
11412 | const struct mips_cpu_info *tune_info = 0; | |
11413 | ||
e9670677 | 11414 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 11415 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 11416 | { |
6caf9ef4 | 11417 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
11418 | as_bad (_("-G not supported in this configuration.")); |
11419 | g_switch_value = 0; | |
11420 | } | |
11421 | ||
cac012d6 AO |
11422 | if (mips_abi == NO_ABI) |
11423 | mips_abi = MIPS_DEFAULT_ABI; | |
11424 | ||
22923709 RS |
11425 | /* The following code determines the architecture and register size. |
11426 | Similar code was added to GCC 3.3 (see override_options() in | |
11427 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
11428 | as much as possible. */ | |
e9670677 | 11429 | |
316f5878 | 11430 | if (mips_arch_string != 0) |
fef14a42 | 11431 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 11432 | |
316f5878 | 11433 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 11434 | { |
316f5878 | 11435 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 11436 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 11437 | the -march selection (if any). */ |
fef14a42 | 11438 | if (arch_info != 0) |
e9670677 | 11439 | { |
316f5878 RS |
11440 | /* -march takes precedence over -mipsN, since it is more descriptive. |
11441 | There's no harm in specifying both as long as the ISA levels | |
11442 | are the same. */ | |
fef14a42 | 11443 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
11444 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
11445 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 11446 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 11447 | } |
316f5878 | 11448 | else |
fef14a42 | 11449 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
11450 | } |
11451 | ||
fef14a42 TS |
11452 | if (arch_info == 0) |
11453 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 11454 | |
fef14a42 | 11455 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 11456 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
11457 | arch_info->name); |
11458 | ||
11459 | mips_set_architecture (arch_info); | |
11460 | ||
11461 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
11462 | if (mips_tune_string != 0) | |
11463 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 11464 | |
fef14a42 TS |
11465 | if (tune_info == 0) |
11466 | mips_set_tune (arch_info); | |
11467 | else | |
11468 | mips_set_tune (tune_info); | |
e9670677 | 11469 | |
316f5878 | 11470 | if (file_mips_gp32 >= 0) |
e9670677 | 11471 | { |
316f5878 RS |
11472 | /* The user specified the size of the integer registers. Make sure |
11473 | it agrees with the ABI and ISA. */ | |
11474 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
11475 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
11476 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11477 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
11478 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
11479 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
11480 | } |
11481 | else | |
11482 | { | |
316f5878 RS |
11483 | /* Infer the integer register size from the ABI and processor. |
11484 | Restrict ourselves to 32-bit registers if that's all the | |
11485 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
11486 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11487 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
11488 | } |
11489 | ||
ad3fea08 TS |
11490 | switch (file_mips_fp32) |
11491 | { | |
11492 | default: | |
11493 | case -1: | |
11494 | /* No user specified float register size. | |
11495 | ??? GAS treats single-float processors as though they had 64-bit | |
11496 | float registers (although it complains when double-precision | |
11497 | instructions are used). As things stand, saying they have 32-bit | |
11498 | registers would lead to spurious "register must be even" messages. | |
11499 | So here we assume float registers are never smaller than the | |
11500 | integer ones. */ | |
11501 | if (file_mips_gp32 == 0) | |
11502 | /* 64-bit integer registers implies 64-bit float registers. */ | |
11503 | file_mips_fp32 = 0; | |
11504 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
11505 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
11506 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
11507 | file_mips_fp32 = 0; | |
11508 | else | |
11509 | /* 32-bit float registers. */ | |
11510 | file_mips_fp32 = 1; | |
11511 | break; | |
11512 | ||
11513 | /* The user specified the size of the float registers. Check if it | |
11514 | agrees with the ABI and ISA. */ | |
11515 | case 0: | |
11516 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
11517 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
11518 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11519 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
11520 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
11521 | break; | |
11522 | case 1: | |
11523 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11524 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
11525 | break; | |
11526 | } | |
e9670677 | 11527 | |
316f5878 | 11528 | /* End of GCC-shared inference code. */ |
e9670677 | 11529 | |
17a2f251 TS |
11530 | /* This flag is set when we have a 64-bit capable CPU but use only |
11531 | 32-bit wide registers. Note that EABI does not use it. */ | |
11532 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
11533 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
11534 | || mips_abi == O32_ABI)) | |
316f5878 | 11535 | mips_32bitmode = 1; |
e9670677 MR |
11536 | |
11537 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
11538 | as_bad (_("trap exception not supported at ISA 1")); | |
11539 | ||
e9670677 MR |
11540 | /* If the selected architecture includes support for ASEs, enable |
11541 | generation of code for them. */ | |
a4672219 | 11542 | if (mips_opts.mips16 == -1) |
fef14a42 | 11543 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 11544 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 11545 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
11546 | && file_mips_fp32 == 0) ? 1 : 0; |
11547 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
11548 | as_bad (_("-mfp32 used with -mips3d")); | |
11549 | ||
ffdefa66 | 11550 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 11551 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
11552 | && file_mips_fp32 == 0) ? 1 : 0; |
11553 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
11554 | as_bad (_("-mfp32 used with -mdmx")); | |
11555 | ||
11556 | if (mips_opts.ase_smartmips == -1) | |
11557 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
11558 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
11559 | as_warn ("%s ISA does not support SmartMIPS", | |
11560 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11561 | ||
74cd071d | 11562 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
11563 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
11564 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
11565 | as_warn ("%s ISA does not support DSP ASE", | |
11566 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11567 | ||
8b082fb1 TS |
11568 | if (mips_opts.ase_dspr2 == -1) |
11569 | { | |
11570 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
11571 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
11572 | } | |
11573 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
11574 | as_warn ("%s ISA does not support DSP R2 ASE", | |
11575 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11576 | ||
ef2e4d86 | 11577 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
11578 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
11579 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
8b082fb1 | 11580 | as_warn ("%s ISA does not support MT ASE", |
ad3fea08 | 11581 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
e9670677 | 11582 | |
e9670677 | 11583 | file_mips_isa = mips_opts.isa; |
a4672219 | 11584 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
11585 | file_ase_mips3d = mips_opts.ase_mips3d; |
11586 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 11587 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 11588 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 11589 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 11590 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
11591 | mips_opts.gp32 = file_mips_gp32; |
11592 | mips_opts.fp32 = file_mips_fp32; | |
11593 | ||
ecb4347a DJ |
11594 | if (mips_flag_mdebug < 0) |
11595 | { | |
11596 | #ifdef OBJ_MAYBE_ECOFF | |
11597 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
11598 | mips_flag_mdebug = 1; | |
11599 | else | |
11600 | #endif /* OBJ_MAYBE_ECOFF */ | |
11601 | mips_flag_mdebug = 0; | |
11602 | } | |
e9670677 MR |
11603 | } |
11604 | \f | |
11605 | void | |
17a2f251 | 11606 | mips_init_after_args (void) |
252b5132 RH |
11607 | { |
11608 | /* initialize opcodes */ | |
11609 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 11610 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
11611 | } |
11612 | ||
11613 | long | |
17a2f251 | 11614 | md_pcrel_from (fixS *fixP) |
252b5132 | 11615 | { |
a7ebbfdf TS |
11616 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
11617 | switch (fixP->fx_r_type) | |
11618 | { | |
11619 | case BFD_RELOC_16_PCREL_S2: | |
11620 | case BFD_RELOC_MIPS_JMP: | |
11621 | /* Return the address of the delay slot. */ | |
11622 | return addr + 4; | |
11623 | default: | |
58ea3d6a | 11624 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
11625 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
11626 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11627 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
11628 | return addr; |
11629 | } | |
252b5132 RH |
11630 | } |
11631 | ||
252b5132 RH |
11632 | /* This is called before the symbol table is processed. In order to |
11633 | work with gcc when using mips-tfile, we must keep all local labels. | |
11634 | However, in other cases, we want to discard them. If we were | |
11635 | called with -g, but we didn't see any debugging information, it may | |
11636 | mean that gcc is smuggling debugging information through to | |
11637 | mips-tfile, in which case we must generate all local labels. */ | |
11638 | ||
11639 | void | |
17a2f251 | 11640 | mips_frob_file_before_adjust (void) |
252b5132 RH |
11641 | { |
11642 | #ifndef NO_ECOFF_DEBUGGING | |
11643 | if (ECOFF_DEBUGGING | |
11644 | && mips_debug != 0 | |
11645 | && ! ecoff_debugging_seen) | |
11646 | flag_keep_locals = 1; | |
11647 | #endif | |
11648 | } | |
11649 | ||
3b91255e | 11650 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 11651 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
11652 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
11653 | relocation operators. | |
11654 | ||
11655 | For our purposes, a %lo() expression matches a %got() or %hi() | |
11656 | expression if: | |
11657 | ||
11658 | (a) it refers to the same symbol; and | |
11659 | (b) the offset applied in the %lo() expression is no lower than | |
11660 | the offset applied in the %got() or %hi(). | |
11661 | ||
11662 | (b) allows us to cope with code like: | |
11663 | ||
11664 | lui $4,%hi(foo) | |
11665 | lh $4,%lo(foo+2)($4) | |
11666 | ||
11667 | ...which is legal on RELA targets, and has a well-defined behaviour | |
11668 | if the user knows that adding 2 to "foo" will not induce a carry to | |
11669 | the high 16 bits. | |
11670 | ||
11671 | When several %lo()s match a particular %got() or %hi(), we use the | |
11672 | following rules to distinguish them: | |
11673 | ||
11674 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
11675 | higher offsets. | |
11676 | ||
11677 | (2) %lo()s with no matching %got() or %hi() are better than those | |
11678 | that already have a matching %got() or %hi(). | |
11679 | ||
11680 | (3) later %lo()s are better than earlier %lo()s. | |
11681 | ||
11682 | These rules are applied in order. | |
11683 | ||
11684 | (1) means, among other things, that %lo()s with identical offsets are | |
11685 | chosen if they exist. | |
11686 | ||
11687 | (2) means that we won't associate several high-part relocations with | |
11688 | the same low-part relocation unless there's no alternative. Having | |
11689 | several high parts for the same low part is a GNU extension; this rule | |
11690 | allows careful users to avoid it. | |
11691 | ||
11692 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
11693 | with the last high-part relocation being at the front of the list. | |
11694 | It therefore makes sense to choose the last matching low-part | |
11695 | relocation, all other things being equal. It's also easier | |
11696 | to code that way. */ | |
252b5132 RH |
11697 | |
11698 | void | |
17a2f251 | 11699 | mips_frob_file (void) |
252b5132 RH |
11700 | { |
11701 | struct mips_hi_fixup *l; | |
11702 | ||
11703 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
11704 | { | |
11705 | segment_info_type *seginfo; | |
3b91255e RS |
11706 | bfd_boolean matched_lo_p; |
11707 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 11708 | |
5919d012 | 11709 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 11710 | |
5919d012 RS |
11711 | /* If a GOT16 relocation turns out to be against a global symbol, |
11712 | there isn't supposed to be a matching LO. */ | |
11713 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
11714 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
11715 | continue; | |
11716 | ||
11717 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
11718 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
11719 | continue; |
11720 | ||
252b5132 | 11721 | seginfo = seg_info (l->seg); |
252b5132 | 11722 | |
3b91255e RS |
11723 | /* Set HI_POS to the position of this relocation in the chain. |
11724 | Set LO_POS to the position of the chosen low-part relocation. | |
11725 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
11726 | relocation that matches an immediately-preceding high-part | |
11727 | relocation. */ | |
11728 | hi_pos = NULL; | |
11729 | lo_pos = NULL; | |
11730 | matched_lo_p = FALSE; | |
11731 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) | |
11732 | { | |
11733 | if (*pos == l->fixp) | |
11734 | hi_pos = pos; | |
11735 | ||
704803a9 MR |
11736 | if (((*pos)->fx_r_type == BFD_RELOC_LO16 |
11737 | || (*pos)->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
3b91255e RS |
11738 | && (*pos)->fx_addsy == l->fixp->fx_addsy |
11739 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
11740 | && (lo_pos == NULL | |
11741 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
11742 | || (!matched_lo_p | |
11743 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
11744 | lo_pos = pos; | |
11745 | ||
11746 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
11747 | && fixup_has_matching_lo_p (*pos)); | |
11748 | } | |
11749 | ||
11750 | /* If we found a match, remove the high-part relocation from its | |
11751 | current position and insert it before the low-part relocation. | |
11752 | Make the offsets match so that fixup_has_matching_lo_p() | |
11753 | will return true. | |
11754 | ||
11755 | We don't warn about unmatched high-part relocations since some | |
11756 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
11757 | instructions. */ | |
11758 | if (lo_pos != NULL) | |
11759 | { | |
11760 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
11761 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 11762 | { |
3b91255e RS |
11763 | *hi_pos = l->fixp->fx_next; |
11764 | l->fixp->fx_next = *lo_pos; | |
11765 | *lo_pos = l->fixp; | |
252b5132 | 11766 | } |
252b5132 RH |
11767 | } |
11768 | } | |
11769 | } | |
11770 | ||
3e722fb5 | 11771 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 11772 | We have to prevent gas from dropping them. */ |
252b5132 | 11773 | |
252b5132 | 11774 | int |
17a2f251 | 11775 | mips_force_relocation (fixS *fixp) |
252b5132 | 11776 | { |
ae6063d4 | 11777 | if (generic_force_reloc (fixp)) |
252b5132 RH |
11778 | return 1; |
11779 | ||
f6688943 TS |
11780 | if (HAVE_NEWABI |
11781 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
11782 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
11783 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
11784 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
11785 | return 1; | |
11786 | ||
3e722fb5 | 11787 | return 0; |
252b5132 RH |
11788 | } |
11789 | ||
11790 | /* Apply a fixup to the object file. */ | |
11791 | ||
94f592af | 11792 | void |
55cf6793 | 11793 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11794 | { |
874e8986 | 11795 | bfd_byte *buf; |
98aa84af | 11796 | long insn; |
a7ebbfdf | 11797 | reloc_howto_type *howto; |
252b5132 | 11798 | |
a7ebbfdf TS |
11799 | /* We ignore generic BFD relocations we don't know about. */ |
11800 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
11801 | if (! howto) | |
11802 | return; | |
65551fa4 | 11803 | |
252b5132 RH |
11804 | assert (fixP->fx_size == 4 |
11805 | || fixP->fx_r_type == BFD_RELOC_16 | |
11806 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
11807 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11808 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 11809 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 11810 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 11811 | |
a7ebbfdf | 11812 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 11813 | |
3994f87e | 11814 | assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2); |
b1dca8ee RS |
11815 | |
11816 | /* Don't treat parts of a composite relocation as done. There are two | |
11817 | reasons for this: | |
11818 | ||
11819 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
11820 | should nevertheless be emitted if the first part is. | |
11821 | ||
11822 | (2) In normal usage, composite relocations are never assembly-time | |
11823 | constants. The easiest way of dealing with the pathological | |
11824 | exceptions is to generate a relocation against STN_UNDEF and | |
11825 | leave everything up to the linker. */ | |
3994f87e | 11826 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
11827 | fixP->fx_done = 1; |
11828 | ||
11829 | switch (fixP->fx_r_type) | |
11830 | { | |
3f98094e DJ |
11831 | case BFD_RELOC_MIPS_TLS_GD: |
11832 | case BFD_RELOC_MIPS_TLS_LDM: | |
11833 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: | |
11834 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
11835 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
11836 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
11837 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
11838 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
11839 | /* fall through */ | |
11840 | ||
252b5132 | 11841 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
11842 | case BFD_RELOC_MIPS_SHIFT5: |
11843 | case BFD_RELOC_MIPS_SHIFT6: | |
11844 | case BFD_RELOC_MIPS_GOT_DISP: | |
11845 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11846 | case BFD_RELOC_MIPS_GOT_OFST: | |
11847 | case BFD_RELOC_MIPS_SUB: | |
11848 | case BFD_RELOC_MIPS_INSERT_A: | |
11849 | case BFD_RELOC_MIPS_INSERT_B: | |
11850 | case BFD_RELOC_MIPS_DELETE: | |
11851 | case BFD_RELOC_MIPS_HIGHEST: | |
11852 | case BFD_RELOC_MIPS_HIGHER: | |
11853 | case BFD_RELOC_MIPS_SCN_DISP: | |
11854 | case BFD_RELOC_MIPS_REL16: | |
11855 | case BFD_RELOC_MIPS_RELGOT: | |
11856 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11857 | case BFD_RELOC_HI16: |
11858 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11859 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11860 | case BFD_RELOC_MIPS_LITERAL: |
11861 | case BFD_RELOC_MIPS_CALL16: | |
11862 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11863 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11864 | case BFD_RELOC_MIPS_GOT_HI16: |
11865 | case BFD_RELOC_MIPS_GOT_LO16: | |
11866 | case BFD_RELOC_MIPS_CALL_HI16: | |
11867 | case BFD_RELOC_MIPS_CALL_LO16: | |
11868 | case BFD_RELOC_MIPS16_GPREL: | |
d6f16593 MR |
11869 | case BFD_RELOC_MIPS16_HI16: |
11870 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 | 11871 | case BFD_RELOC_MIPS16_JMP: |
54f4ddb3 | 11872 | /* Nothing needed to do. The value comes from the reloc entry. */ |
252b5132 RH |
11873 | break; |
11874 | ||
252b5132 RH |
11875 | case BFD_RELOC_64: |
11876 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11877 | extended value if we are only 32 bits. */ | |
3e722fb5 | 11878 | if (fixP->fx_done) |
252b5132 RH |
11879 | { |
11880 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 11881 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
11882 | else |
11883 | { | |
a7ebbfdf | 11884 | valueT hiv; |
252b5132 | 11885 | |
a7ebbfdf | 11886 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11887 | hiv = 0xffffffff; |
11888 | else | |
11889 | hiv = 0; | |
b215186b | 11890 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 11891 | *valP, 4); |
b215186b | 11892 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 11893 | hiv, 4); |
252b5132 RH |
11894 | } |
11895 | } | |
11896 | break; | |
11897 | ||
056350c6 | 11898 | case BFD_RELOC_RVA: |
252b5132 | 11899 | case BFD_RELOC_32: |
252b5132 RH |
11900 | case BFD_RELOC_16: |
11901 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
11902 | value now. This can happen if we have a .word which is not |
11903 | resolved when it appears but is later defined. */ | |
252b5132 | 11904 | if (fixP->fx_done) |
54f4ddb3 | 11905 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); |
252b5132 RH |
11906 | break; |
11907 | ||
11908 | case BFD_RELOC_LO16: | |
d6f16593 | 11909 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
11910 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
11911 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
11912 | /* When handling an embedded PIC switch statement, we can wind |
11913 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11914 | if (fixP->fx_done) | |
11915 | { | |
a7ebbfdf | 11916 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11917 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11918 | _("relocation overflow")); | |
252b5132 RH |
11919 | if (target_big_endian) |
11920 | buf += 2; | |
2132e3a3 | 11921 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11922 | } |
11923 | break; | |
11924 | ||
11925 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11926 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11927 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 11928 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 11929 | |
54f4ddb3 TS |
11930 | /* We need to save the bits in the instruction since fixup_segment() |
11931 | might be deleting the relocation entry (i.e., a branch within | |
11932 | the current segment). */ | |
a7ebbfdf | 11933 | if (! fixP->fx_done) |
bb2d6cd7 | 11934 | break; |
252b5132 | 11935 | |
54f4ddb3 | 11936 | /* Update old instruction data. */ |
252b5132 RH |
11937 | if (target_big_endian) |
11938 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11939 | else | |
11940 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11941 | ||
a7ebbfdf TS |
11942 | if (*valP + 0x20000 <= 0x3ffff) |
11943 | { | |
11944 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 11945 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11946 | } |
11947 | else if (mips_pic == NO_PIC | |
11948 | && fixP->fx_done | |
11949 | && fixP->fx_frag->fr_address >= text_section->vma | |
11950 | && (fixP->fx_frag->fr_address | |
587aac4e | 11951 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
11952 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
11953 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11954 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11955 | { |
11956 | /* The branch offset is too large. If this is an | |
11957 | unconditional branch, and we are not generating PIC code, | |
11958 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11959 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11960 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11961 | else |
a7ebbfdf TS |
11962 | insn = 0x08000000; /* j */ |
11963 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11964 | fixP->fx_done = 0; | |
11965 | fixP->fx_addsy = section_symbol (text_section); | |
11966 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 11967 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11968 | } |
11969 | else | |
11970 | { | |
11971 | /* If we got here, we have branch-relaxation disabled, | |
11972 | and there's nothing we can do to fix this instruction | |
11973 | without turning it into a longer sequence. */ | |
11974 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11975 | _("Branch out of range")); | |
252b5132 | 11976 | } |
252b5132 RH |
11977 | break; |
11978 | ||
11979 | case BFD_RELOC_VTABLE_INHERIT: | |
11980 | fixP->fx_done = 0; | |
11981 | if (fixP->fx_addsy | |
11982 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11983 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11984 | S_SET_WEAK (fixP->fx_addsy); | |
11985 | break; | |
11986 | ||
11987 | case BFD_RELOC_VTABLE_ENTRY: | |
11988 | fixP->fx_done = 0; | |
11989 | break; | |
11990 | ||
11991 | default: | |
11992 | internalError (); | |
11993 | } | |
a7ebbfdf TS |
11994 | |
11995 | /* Remember value for tc_gen_reloc. */ | |
11996 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11997 | } |
11998 | ||
252b5132 | 11999 | static symbolS * |
17a2f251 | 12000 | get_symbol (void) |
252b5132 RH |
12001 | { |
12002 | int c; | |
12003 | char *name; | |
12004 | symbolS *p; | |
12005 | ||
12006 | name = input_line_pointer; | |
12007 | c = get_symbol_end (); | |
12008 | p = (symbolS *) symbol_find_or_make (name); | |
12009 | *input_line_pointer = c; | |
12010 | return p; | |
12011 | } | |
12012 | ||
12013 | /* Align the current frag to a given power of two. The MIPS assembler | |
12014 | also automatically adjusts any preceding label. */ | |
12015 | ||
12016 | static void | |
17a2f251 | 12017 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 12018 | { |
7d10b47d | 12019 | mips_emit_delays (); |
252b5132 RH |
12020 | frag_align (to, fill, 0); |
12021 | record_alignment (now_seg, to); | |
12022 | if (label != NULL) | |
12023 | { | |
12024 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 12025 | symbol_set_frag (label, frag_now); |
252b5132 RH |
12026 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
12027 | } | |
12028 | } | |
12029 | ||
12030 | /* Align to a given power of two. .align 0 turns off the automatic | |
12031 | alignment used by the data creating pseudo-ops. */ | |
12032 | ||
12033 | static void | |
17a2f251 | 12034 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 12035 | { |
3994f87e TS |
12036 | int temp; |
12037 | long temp_fill; | |
252b5132 RH |
12038 | long max_alignment = 15; |
12039 | ||
54f4ddb3 | 12040 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 12041 | to the aligned address. |
54f4ddb3 | 12042 | o It's not documented but auto alignment is reinstated by |
252b5132 | 12043 | a .align pseudo instruction. |
54f4ddb3 | 12044 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 12045 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 12046 | We don't. */ |
252b5132 RH |
12047 | |
12048 | temp = get_absolute_expression (); | |
12049 | if (temp > max_alignment) | |
12050 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
12051 | else if (temp < 0) | |
12052 | { | |
12053 | as_warn (_("Alignment negative: 0 assumed.")); | |
12054 | temp = 0; | |
12055 | } | |
12056 | if (*input_line_pointer == ',') | |
12057 | { | |
f9419b05 | 12058 | ++input_line_pointer; |
252b5132 RH |
12059 | temp_fill = get_absolute_expression (); |
12060 | } | |
12061 | else | |
12062 | temp_fill = 0; | |
12063 | if (temp) | |
12064 | { | |
a8dbcb85 TS |
12065 | segment_info_type *si = seg_info (now_seg); |
12066 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 12067 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 12068 | auto_align = 1; |
a8dbcb85 | 12069 | mips_align (temp, (int) temp_fill, l != NULL ? l->label : NULL); |
252b5132 RH |
12070 | } |
12071 | else | |
12072 | { | |
12073 | auto_align = 0; | |
12074 | } | |
12075 | ||
12076 | demand_empty_rest_of_line (); | |
12077 | } | |
12078 | ||
252b5132 | 12079 | static void |
17a2f251 | 12080 | s_change_sec (int sec) |
252b5132 RH |
12081 | { |
12082 | segT seg; | |
12083 | ||
252b5132 RH |
12084 | #ifdef OBJ_ELF |
12085 | /* The ELF backend needs to know that we are changing sections, so | |
12086 | that .previous works correctly. We could do something like check | |
b6ff326e | 12087 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
12088 | as it would not be appropriate to use it in the section changing |
12089 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
12090 | This should be cleaner, somehow. */ | |
f43abd2b TS |
12091 | if (IS_ELF) |
12092 | obj_elf_section_change_hook (); | |
252b5132 RH |
12093 | #endif |
12094 | ||
7d10b47d | 12095 | mips_emit_delays (); |
252b5132 RH |
12096 | switch (sec) |
12097 | { | |
12098 | case 't': | |
12099 | s_text (0); | |
12100 | break; | |
12101 | case 'd': | |
12102 | s_data (0); | |
12103 | break; | |
12104 | case 'b': | |
12105 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
12106 | demand_empty_rest_of_line (); | |
12107 | break; | |
12108 | ||
12109 | case 'r': | |
4d0d148d TS |
12110 | seg = subseg_new (RDATA_SECTION_NAME, |
12111 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 12112 | if (IS_ELF) |
252b5132 | 12113 | { |
4d0d148d TS |
12114 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
12115 | | SEC_READONLY | SEC_RELOC | |
12116 | | SEC_DATA)); | |
12117 | if (strcmp (TARGET_OS, "elf") != 0) | |
12118 | record_alignment (seg, 4); | |
252b5132 | 12119 | } |
4d0d148d | 12120 | demand_empty_rest_of_line (); |
252b5132 RH |
12121 | break; |
12122 | ||
12123 | case 's': | |
4d0d148d | 12124 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 12125 | if (IS_ELF) |
252b5132 | 12126 | { |
4d0d148d TS |
12127 | bfd_set_section_flags (stdoutput, seg, |
12128 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
12129 | if (strcmp (TARGET_OS, "elf") != 0) | |
12130 | record_alignment (seg, 4); | |
252b5132 | 12131 | } |
4d0d148d TS |
12132 | demand_empty_rest_of_line (); |
12133 | break; | |
252b5132 RH |
12134 | } |
12135 | ||
12136 | auto_align = 1; | |
12137 | } | |
b34976b6 | 12138 | |
cca86cc8 | 12139 | void |
17a2f251 | 12140 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 12141 | { |
7ed4a06a | 12142 | #ifdef OBJ_ELF |
cca86cc8 SC |
12143 | char *section_name; |
12144 | char c; | |
684022ea | 12145 | char next_c = 0; |
cca86cc8 SC |
12146 | int section_type; |
12147 | int section_flag; | |
12148 | int section_entry_size; | |
12149 | int section_alignment; | |
b34976b6 | 12150 | |
f43abd2b | 12151 | if (!IS_ELF) |
7ed4a06a TS |
12152 | return; |
12153 | ||
cca86cc8 SC |
12154 | section_name = input_line_pointer; |
12155 | c = get_symbol_end (); | |
a816d1ed AO |
12156 | if (c) |
12157 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 12158 | |
4cf0dd0d TS |
12159 | /* Do we have .section Name<,"flags">? */ |
12160 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 12161 | { |
4cf0dd0d TS |
12162 | /* just after name is now '\0'. */ |
12163 | *input_line_pointer = c; | |
cca86cc8 SC |
12164 | input_line_pointer = section_name; |
12165 | obj_elf_section (ignore); | |
12166 | return; | |
12167 | } | |
12168 | input_line_pointer++; | |
12169 | ||
12170 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
12171 | if (c == ',') | |
12172 | section_type = get_absolute_expression (); | |
12173 | else | |
12174 | section_type = 0; | |
12175 | if (*input_line_pointer++ == ',') | |
12176 | section_flag = get_absolute_expression (); | |
12177 | else | |
12178 | section_flag = 0; | |
12179 | if (*input_line_pointer++ == ',') | |
12180 | section_entry_size = get_absolute_expression (); | |
12181 | else | |
12182 | section_entry_size = 0; | |
12183 | if (*input_line_pointer++ == ',') | |
12184 | section_alignment = get_absolute_expression (); | |
12185 | else | |
12186 | section_alignment = 0; | |
12187 | ||
a816d1ed AO |
12188 | section_name = xstrdup (section_name); |
12189 | ||
8ab8a5c8 RS |
12190 | /* When using the generic form of .section (as implemented by obj-elf.c), |
12191 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
12192 | traditionally had to fall back on the more common @progbits instead. | |
12193 | ||
12194 | There's nothing really harmful in this, since bfd will correct | |
12195 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 12196 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
12197 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
12198 | ||
12199 | Even so, we shouldn't force users of the MIPS .section syntax to | |
12200 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
12201 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
12202 | generic type-checking code. */ | |
12203 | if (section_type == SHT_MIPS_DWARF) | |
12204 | section_type = SHT_PROGBITS; | |
12205 | ||
cca86cc8 SC |
12206 | obj_elf_change_section (section_name, section_type, section_flag, |
12207 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
12208 | |
12209 | if (now_seg->name != section_name) | |
12210 | free (section_name); | |
7ed4a06a | 12211 | #endif /* OBJ_ELF */ |
cca86cc8 | 12212 | } |
252b5132 RH |
12213 | |
12214 | void | |
17a2f251 | 12215 | mips_enable_auto_align (void) |
252b5132 RH |
12216 | { |
12217 | auto_align = 1; | |
12218 | } | |
12219 | ||
12220 | static void | |
17a2f251 | 12221 | s_cons (int log_size) |
252b5132 | 12222 | { |
a8dbcb85 TS |
12223 | segment_info_type *si = seg_info (now_seg); |
12224 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12225 | symbolS *label; |
12226 | ||
a8dbcb85 | 12227 | label = l != NULL ? l->label : NULL; |
7d10b47d | 12228 | mips_emit_delays (); |
252b5132 RH |
12229 | if (log_size > 0 && auto_align) |
12230 | mips_align (log_size, 0, label); | |
12231 | mips_clear_insn_labels (); | |
12232 | cons (1 << log_size); | |
12233 | } | |
12234 | ||
12235 | static void | |
17a2f251 | 12236 | s_float_cons (int type) |
252b5132 | 12237 | { |
a8dbcb85 TS |
12238 | segment_info_type *si = seg_info (now_seg); |
12239 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12240 | symbolS *label; |
12241 | ||
a8dbcb85 | 12242 | label = l != NULL ? l->label : NULL; |
252b5132 | 12243 | |
7d10b47d | 12244 | mips_emit_delays (); |
252b5132 RH |
12245 | |
12246 | if (auto_align) | |
49309057 ILT |
12247 | { |
12248 | if (type == 'd') | |
12249 | mips_align (3, 0, label); | |
12250 | else | |
12251 | mips_align (2, 0, label); | |
12252 | } | |
252b5132 RH |
12253 | |
12254 | mips_clear_insn_labels (); | |
12255 | ||
12256 | float_cons (type); | |
12257 | } | |
12258 | ||
12259 | /* Handle .globl. We need to override it because on Irix 5 you are | |
12260 | permitted to say | |
12261 | .globl foo .text | |
12262 | where foo is an undefined symbol, to mean that foo should be | |
12263 | considered to be the address of a function. */ | |
12264 | ||
12265 | static void | |
17a2f251 | 12266 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12267 | { |
12268 | char *name; | |
12269 | int c; | |
12270 | symbolS *symbolP; | |
12271 | flagword flag; | |
12272 | ||
8a06b769 | 12273 | do |
252b5132 | 12274 | { |
8a06b769 | 12275 | name = input_line_pointer; |
252b5132 | 12276 | c = get_symbol_end (); |
8a06b769 TS |
12277 | symbolP = symbol_find_or_make (name); |
12278 | S_SET_EXTERNAL (symbolP); | |
12279 | ||
252b5132 | 12280 | *input_line_pointer = c; |
8a06b769 | 12281 | SKIP_WHITESPACE (); |
252b5132 | 12282 | |
8a06b769 TS |
12283 | /* On Irix 5, every global symbol that is not explicitly labelled as |
12284 | being a function is apparently labelled as being an object. */ | |
12285 | flag = BSF_OBJECT; | |
252b5132 | 12286 | |
8a06b769 TS |
12287 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
12288 | && (*input_line_pointer != ',')) | |
12289 | { | |
12290 | char *secname; | |
12291 | asection *sec; | |
12292 | ||
12293 | secname = input_line_pointer; | |
12294 | c = get_symbol_end (); | |
12295 | sec = bfd_get_section_by_name (stdoutput, secname); | |
12296 | if (sec == NULL) | |
12297 | as_bad (_("%s: no such section"), secname); | |
12298 | *input_line_pointer = c; | |
12299 | ||
12300 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
12301 | flag = BSF_FUNCTION; | |
12302 | } | |
12303 | ||
12304 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
12305 | ||
12306 | c = *input_line_pointer; | |
12307 | if (c == ',') | |
12308 | { | |
12309 | input_line_pointer++; | |
12310 | SKIP_WHITESPACE (); | |
12311 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
12312 | c = '\n'; | |
12313 | } | |
12314 | } | |
12315 | while (c == ','); | |
252b5132 | 12316 | |
252b5132 RH |
12317 | demand_empty_rest_of_line (); |
12318 | } | |
12319 | ||
12320 | static void | |
17a2f251 | 12321 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12322 | { |
12323 | char *opt; | |
12324 | char c; | |
12325 | ||
12326 | opt = input_line_pointer; | |
12327 | c = get_symbol_end (); | |
12328 | ||
12329 | if (*opt == 'O') | |
12330 | { | |
12331 | /* FIXME: What does this mean? */ | |
12332 | } | |
12333 | else if (strncmp (opt, "pic", 3) == 0) | |
12334 | { | |
12335 | int i; | |
12336 | ||
12337 | i = atoi (opt + 3); | |
12338 | if (i == 0) | |
12339 | mips_pic = NO_PIC; | |
12340 | else if (i == 2) | |
143d77c5 | 12341 | { |
252b5132 | 12342 | mips_pic = SVR4_PIC; |
143d77c5 EC |
12343 | mips_abicalls = TRUE; |
12344 | } | |
252b5132 RH |
12345 | else |
12346 | as_bad (_(".option pic%d not supported"), i); | |
12347 | ||
4d0d148d | 12348 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
12349 | { |
12350 | if (g_switch_seen && g_switch_value != 0) | |
12351 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12352 | g_switch_value = 0; | |
12353 | bfd_set_gp_size (stdoutput, 0); | |
12354 | } | |
12355 | } | |
12356 | else | |
12357 | as_warn (_("Unrecognized option \"%s\""), opt); | |
12358 | ||
12359 | *input_line_pointer = c; | |
12360 | demand_empty_rest_of_line (); | |
12361 | } | |
12362 | ||
12363 | /* This structure is used to hold a stack of .set values. */ | |
12364 | ||
e972090a NC |
12365 | struct mips_option_stack |
12366 | { | |
252b5132 RH |
12367 | struct mips_option_stack *next; |
12368 | struct mips_set_options options; | |
12369 | }; | |
12370 | ||
12371 | static struct mips_option_stack *mips_opts_stack; | |
12372 | ||
12373 | /* Handle the .set pseudo-op. */ | |
12374 | ||
12375 | static void | |
17a2f251 | 12376 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12377 | { |
12378 | char *name = input_line_pointer, ch; | |
12379 | ||
12380 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 12381 | ++input_line_pointer; |
252b5132 RH |
12382 | ch = *input_line_pointer; |
12383 | *input_line_pointer = '\0'; | |
12384 | ||
12385 | if (strcmp (name, "reorder") == 0) | |
12386 | { | |
7d10b47d RS |
12387 | if (mips_opts.noreorder) |
12388 | end_noreorder (); | |
252b5132 RH |
12389 | } |
12390 | else if (strcmp (name, "noreorder") == 0) | |
12391 | { | |
7d10b47d RS |
12392 | if (!mips_opts.noreorder) |
12393 | start_noreorder (); | |
252b5132 RH |
12394 | } |
12395 | else if (strcmp (name, "at") == 0) | |
12396 | { | |
12397 | mips_opts.noat = 0; | |
12398 | } | |
12399 | else if (strcmp (name, "noat") == 0) | |
12400 | { | |
12401 | mips_opts.noat = 1; | |
12402 | } | |
12403 | else if (strcmp (name, "macro") == 0) | |
12404 | { | |
12405 | mips_opts.warn_about_macros = 0; | |
12406 | } | |
12407 | else if (strcmp (name, "nomacro") == 0) | |
12408 | { | |
12409 | if (mips_opts.noreorder == 0) | |
12410 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
12411 | mips_opts.warn_about_macros = 1; | |
12412 | } | |
12413 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
12414 | { | |
12415 | mips_opts.nomove = 0; | |
12416 | } | |
12417 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
12418 | { | |
12419 | mips_opts.nomove = 1; | |
12420 | } | |
12421 | else if (strcmp (name, "bopt") == 0) | |
12422 | { | |
12423 | mips_opts.nobopt = 0; | |
12424 | } | |
12425 | else if (strcmp (name, "nobopt") == 0) | |
12426 | { | |
12427 | mips_opts.nobopt = 1; | |
12428 | } | |
ad3fea08 TS |
12429 | else if (strcmp (name, "gp=default") == 0) |
12430 | mips_opts.gp32 = file_mips_gp32; | |
12431 | else if (strcmp (name, "gp=32") == 0) | |
12432 | mips_opts.gp32 = 1; | |
12433 | else if (strcmp (name, "gp=64") == 0) | |
12434 | { | |
12435 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
12436 | as_warn ("%s isa does not support 64-bit registers", | |
12437 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12438 | mips_opts.gp32 = 0; | |
12439 | } | |
12440 | else if (strcmp (name, "fp=default") == 0) | |
12441 | mips_opts.fp32 = file_mips_fp32; | |
12442 | else if (strcmp (name, "fp=32") == 0) | |
12443 | mips_opts.fp32 = 1; | |
12444 | else if (strcmp (name, "fp=64") == 0) | |
12445 | { | |
12446 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
12447 | as_warn ("%s isa does not support 64-bit floating point registers", | |
12448 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12449 | mips_opts.fp32 = 0; | |
12450 | } | |
252b5132 RH |
12451 | else if (strcmp (name, "mips16") == 0 |
12452 | || strcmp (name, "MIPS-16") == 0) | |
12453 | mips_opts.mips16 = 1; | |
12454 | else if (strcmp (name, "nomips16") == 0 | |
12455 | || strcmp (name, "noMIPS-16") == 0) | |
12456 | mips_opts.mips16 = 0; | |
e16bfa71 TS |
12457 | else if (strcmp (name, "smartmips") == 0) |
12458 | { | |
ad3fea08 | 12459 | if (!ISA_SUPPORTS_SMARTMIPS) |
e16bfa71 TS |
12460 | as_warn ("%s ISA does not support SmartMIPS ASE", |
12461 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12462 | mips_opts.ase_smartmips = 1; | |
12463 | } | |
12464 | else if (strcmp (name, "nosmartmips") == 0) | |
12465 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
12466 | else if (strcmp (name, "mips3d") == 0) |
12467 | mips_opts.ase_mips3d = 1; | |
12468 | else if (strcmp (name, "nomips3d") == 0) | |
12469 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
12470 | else if (strcmp (name, "mdmx") == 0) |
12471 | mips_opts.ase_mdmx = 1; | |
12472 | else if (strcmp (name, "nomdmx") == 0) | |
12473 | mips_opts.ase_mdmx = 0; | |
74cd071d | 12474 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
12475 | { |
12476 | if (!ISA_SUPPORTS_DSP_ASE) | |
12477 | as_warn ("%s ISA does not support DSP ASE", | |
12478 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12479 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 12480 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 12481 | } |
74cd071d | 12482 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
12483 | { |
12484 | mips_opts.ase_dsp = 0; | |
12485 | mips_opts.ase_dspr2 = 0; | |
12486 | } | |
12487 | else if (strcmp (name, "dspr2") == 0) | |
12488 | { | |
12489 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
12490 | as_warn ("%s ISA does not support DSP R2 ASE", | |
12491 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12492 | mips_opts.ase_dspr2 = 1; | |
12493 | mips_opts.ase_dsp = 1; | |
12494 | } | |
12495 | else if (strcmp (name, "nodspr2") == 0) | |
12496 | { | |
12497 | mips_opts.ase_dspr2 = 0; | |
12498 | mips_opts.ase_dsp = 0; | |
12499 | } | |
ef2e4d86 | 12500 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
12501 | { |
12502 | if (!ISA_SUPPORTS_MT_ASE) | |
12503 | as_warn ("%s ISA does not support MT ASE", | |
12504 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12505 | mips_opts.ase_mt = 1; | |
12506 | } | |
ef2e4d86 CF |
12507 | else if (strcmp (name, "nomt") == 0) |
12508 | mips_opts.ase_mt = 0; | |
1a2c1fad | 12509 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 12510 | { |
af7ee8bf | 12511 | int reset = 0; |
252b5132 | 12512 | |
1a2c1fad CD |
12513 | /* Permit the user to change the ISA and architecture on the fly. |
12514 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 12515 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
12516 | { |
12517 | reset = 1; | |
12518 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 12519 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
12520 | } |
12521 | else if (strncmp (name, "arch=", 5) == 0) | |
12522 | { | |
12523 | const struct mips_cpu_info *p; | |
12524 | ||
12525 | p = mips_parse_cpu("internal use", name + 5); | |
12526 | if (!p) | |
12527 | as_bad (_("unknown architecture %s"), name + 5); | |
12528 | else | |
12529 | { | |
12530 | mips_opts.arch = p->cpu; | |
12531 | mips_opts.isa = p->isa; | |
12532 | } | |
12533 | } | |
81a21e38 TS |
12534 | else if (strncmp (name, "mips", 4) == 0) |
12535 | { | |
12536 | const struct mips_cpu_info *p; | |
12537 | ||
12538 | p = mips_parse_cpu("internal use", name); | |
12539 | if (!p) | |
12540 | as_bad (_("unknown ISA level %s"), name + 4); | |
12541 | else | |
12542 | { | |
12543 | mips_opts.arch = p->cpu; | |
12544 | mips_opts.isa = p->isa; | |
12545 | } | |
12546 | } | |
af7ee8bf | 12547 | else |
81a21e38 | 12548 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
12549 | |
12550 | switch (mips_opts.isa) | |
98d3f06f KH |
12551 | { |
12552 | case 0: | |
98d3f06f | 12553 | break; |
af7ee8bf CD |
12554 | case ISA_MIPS1: |
12555 | case ISA_MIPS2: | |
12556 | case ISA_MIPS32: | |
12557 | case ISA_MIPS32R2: | |
98d3f06f KH |
12558 | mips_opts.gp32 = 1; |
12559 | mips_opts.fp32 = 1; | |
12560 | break; | |
af7ee8bf CD |
12561 | case ISA_MIPS3: |
12562 | case ISA_MIPS4: | |
12563 | case ISA_MIPS5: | |
12564 | case ISA_MIPS64: | |
5f74bc13 | 12565 | case ISA_MIPS64R2: |
98d3f06f KH |
12566 | mips_opts.gp32 = 0; |
12567 | mips_opts.fp32 = 0; | |
12568 | break; | |
12569 | default: | |
12570 | as_bad (_("unknown ISA level %s"), name + 4); | |
12571 | break; | |
12572 | } | |
af7ee8bf | 12573 | if (reset) |
98d3f06f | 12574 | { |
af7ee8bf CD |
12575 | mips_opts.gp32 = file_mips_gp32; |
12576 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 12577 | } |
252b5132 RH |
12578 | } |
12579 | else if (strcmp (name, "autoextend") == 0) | |
12580 | mips_opts.noautoextend = 0; | |
12581 | else if (strcmp (name, "noautoextend") == 0) | |
12582 | mips_opts.noautoextend = 1; | |
12583 | else if (strcmp (name, "push") == 0) | |
12584 | { | |
12585 | struct mips_option_stack *s; | |
12586 | ||
12587 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
12588 | s->next = mips_opts_stack; | |
12589 | s->options = mips_opts; | |
12590 | mips_opts_stack = s; | |
12591 | } | |
12592 | else if (strcmp (name, "pop") == 0) | |
12593 | { | |
12594 | struct mips_option_stack *s; | |
12595 | ||
12596 | s = mips_opts_stack; | |
12597 | if (s == NULL) | |
12598 | as_bad (_(".set pop with no .set push")); | |
12599 | else | |
12600 | { | |
12601 | /* If we're changing the reorder mode we need to handle | |
12602 | delay slots correctly. */ | |
12603 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 12604 | start_noreorder (); |
252b5132 | 12605 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 12606 | end_noreorder (); |
252b5132 RH |
12607 | |
12608 | mips_opts = s->options; | |
12609 | mips_opts_stack = s->next; | |
12610 | free (s); | |
12611 | } | |
12612 | } | |
aed1a261 RS |
12613 | else if (strcmp (name, "sym32") == 0) |
12614 | mips_opts.sym32 = TRUE; | |
12615 | else if (strcmp (name, "nosym32") == 0) | |
12616 | mips_opts.sym32 = FALSE; | |
252b5132 RH |
12617 | else |
12618 | { | |
12619 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
12620 | } | |
12621 | *input_line_pointer = ch; | |
12622 | demand_empty_rest_of_line (); | |
12623 | } | |
12624 | ||
12625 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
12626 | .option pic2. It means to generate SVR4 PIC calls. */ | |
12627 | ||
12628 | static void | |
17a2f251 | 12629 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12630 | { |
12631 | mips_pic = SVR4_PIC; | |
143d77c5 | 12632 | mips_abicalls = TRUE; |
4d0d148d TS |
12633 | |
12634 | if (g_switch_seen && g_switch_value != 0) | |
12635 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12636 | g_switch_value = 0; | |
12637 | ||
252b5132 RH |
12638 | bfd_set_gp_size (stdoutput, 0); |
12639 | demand_empty_rest_of_line (); | |
12640 | } | |
12641 | ||
12642 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
12643 | PIC code. It sets the $gp register for the function based on the | |
12644 | function address, which is in the register named in the argument. | |
12645 | This uses a relocation against _gp_disp, which is handled specially | |
12646 | by the linker. The result is: | |
12647 | lui $gp,%hi(_gp_disp) | |
12648 | addiu $gp,$gp,%lo(_gp_disp) | |
12649 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
12650 | The .cpload argument is normally $25 == $t9. |
12651 | ||
12652 | The -mno-shared option changes this to: | |
bbe506e8 TS |
12653 | lui $gp,%hi(__gnu_local_gp) |
12654 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
12655 | and the argument is ignored. This saves an instruction, but the |
12656 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
12657 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
12658 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
12659 | |
12660 | static void | |
17a2f251 | 12661 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12662 | { |
12663 | expressionS ex; | |
aa6975fb ILT |
12664 | int reg; |
12665 | int in_shared; | |
252b5132 | 12666 | |
6478892d TS |
12667 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
12668 | .cpload is ignored. */ | |
12669 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
12670 | { |
12671 | s_ignore (0); | |
12672 | return; | |
12673 | } | |
12674 | ||
d3ecfc59 | 12675 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
12676 | if (mips_opts.noreorder == 0) |
12677 | as_warn (_(".cpload not in noreorder section")); | |
12678 | ||
aa6975fb ILT |
12679 | reg = tc_get_register (0); |
12680 | ||
12681 | /* If we need to produce a 64-bit address, we are better off using | |
12682 | the default instruction sequence. */ | |
aed1a261 | 12683 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 12684 | |
252b5132 | 12685 | ex.X_op = O_symbol; |
bbe506e8 TS |
12686 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
12687 | "__gnu_local_gp"); | |
252b5132 RH |
12688 | ex.X_op_symbol = NULL; |
12689 | ex.X_add_number = 0; | |
12690 | ||
12691 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 12692 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 12693 | |
584892a6 | 12694 | macro_start (); |
67c0d1eb RS |
12695 | macro_build_lui (&ex, mips_gp_register); |
12696 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 12697 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
12698 | if (in_shared) |
12699 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
12700 | mips_gp_register, reg); | |
584892a6 | 12701 | macro_end (); |
252b5132 RH |
12702 | |
12703 | demand_empty_rest_of_line (); | |
12704 | } | |
12705 | ||
6478892d TS |
12706 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
12707 | .cpsetup $reg1, offset|$reg2, label | |
12708 | ||
12709 | If offset is given, this results in: | |
12710 | sd $gp, offset($sp) | |
956cd1d6 | 12711 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12712 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12713 | daddu $gp, $gp, $reg1 | |
6478892d TS |
12714 | |
12715 | If $reg2 is given, this results in: | |
12716 | daddu $reg2, $gp, $0 | |
956cd1d6 | 12717 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12718 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12719 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
12720 | $reg1 is normally $25 == $t9. |
12721 | ||
12722 | The -mno-shared option replaces the last three instructions with | |
12723 | lui $gp,%hi(_gp) | |
54f4ddb3 | 12724 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 12725 | |
6478892d | 12726 | static void |
17a2f251 | 12727 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12728 | { |
12729 | expressionS ex_off; | |
12730 | expressionS ex_sym; | |
12731 | int reg1; | |
6478892d | 12732 | |
8586fc66 | 12733 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
12734 | We also need NewABI support. */ |
12735 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12736 | { | |
12737 | s_ignore (0); | |
12738 | return; | |
12739 | } | |
12740 | ||
12741 | reg1 = tc_get_register (0); | |
12742 | SKIP_WHITESPACE (); | |
12743 | if (*input_line_pointer != ',') | |
12744 | { | |
12745 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12746 | return; | |
12747 | } | |
12748 | else | |
80245285 | 12749 | ++input_line_pointer; |
6478892d TS |
12750 | SKIP_WHITESPACE (); |
12751 | if (*input_line_pointer == '$') | |
80245285 TS |
12752 | { |
12753 | mips_cpreturn_register = tc_get_register (0); | |
12754 | mips_cpreturn_offset = -1; | |
12755 | } | |
6478892d | 12756 | else |
80245285 TS |
12757 | { |
12758 | mips_cpreturn_offset = get_absolute_expression (); | |
12759 | mips_cpreturn_register = -1; | |
12760 | } | |
6478892d TS |
12761 | SKIP_WHITESPACE (); |
12762 | if (*input_line_pointer != ',') | |
12763 | { | |
12764 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12765 | return; | |
12766 | } | |
12767 | else | |
f9419b05 | 12768 | ++input_line_pointer; |
6478892d | 12769 | SKIP_WHITESPACE (); |
f21f8242 | 12770 | expression (&ex_sym); |
6478892d | 12771 | |
584892a6 | 12772 | macro_start (); |
6478892d TS |
12773 | if (mips_cpreturn_register == -1) |
12774 | { | |
12775 | ex_off.X_op = O_constant; | |
12776 | ex_off.X_add_symbol = NULL; | |
12777 | ex_off.X_op_symbol = NULL; | |
12778 | ex_off.X_add_number = mips_cpreturn_offset; | |
12779 | ||
67c0d1eb | 12780 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 12781 | BFD_RELOC_LO16, SP); |
6478892d TS |
12782 | } |
12783 | else | |
67c0d1eb | 12784 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 12785 | mips_gp_register, 0); |
6478892d | 12786 | |
aed1a261 | 12787 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
12788 | { |
12789 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
12790 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
12791 | BFD_RELOC_HI16_S); | |
12792 | ||
12793 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
12794 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
12795 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
12796 | ||
12797 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
12798 | mips_gp_register, reg1); | |
12799 | } | |
12800 | else | |
12801 | { | |
12802 | expressionS ex; | |
12803 | ||
12804 | ex.X_op = O_symbol; | |
4184909a | 12805 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
12806 | ex.X_op_symbol = NULL; |
12807 | ex.X_add_number = 0; | |
6e1304d8 | 12808 | |
aa6975fb ILT |
12809 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
12810 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
12811 | ||
12812 | macro_build_lui (&ex, mips_gp_register); | |
12813 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
12814 | mips_gp_register, BFD_RELOC_LO16); | |
12815 | } | |
f21f8242 | 12816 | |
584892a6 | 12817 | macro_end (); |
6478892d TS |
12818 | |
12819 | demand_empty_rest_of_line (); | |
12820 | } | |
12821 | ||
12822 | static void | |
17a2f251 | 12823 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12824 | { |
12825 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 12826 | .cplocal is ignored. */ |
6478892d TS |
12827 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
12828 | { | |
12829 | s_ignore (0); | |
12830 | return; | |
12831 | } | |
12832 | ||
12833 | mips_gp_register = tc_get_register (0); | |
85b51719 | 12834 | demand_empty_rest_of_line (); |
6478892d TS |
12835 | } |
12836 | ||
252b5132 RH |
12837 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
12838 | offset from $sp. The offset is remembered, and after making a PIC | |
12839 | call $gp is restored from that location. */ | |
12840 | ||
12841 | static void | |
17a2f251 | 12842 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12843 | { |
12844 | expressionS ex; | |
252b5132 | 12845 | |
6478892d | 12846 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 12847 | .cprestore is ignored. */ |
6478892d | 12848 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
12849 | { |
12850 | s_ignore (0); | |
12851 | return; | |
12852 | } | |
12853 | ||
12854 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12855 | mips_cprestore_valid = 1; |
252b5132 RH |
12856 | |
12857 | ex.X_op = O_constant; | |
12858 | ex.X_add_symbol = NULL; | |
12859 | ex.X_op_symbol = NULL; | |
12860 | ex.X_add_number = mips_cprestore_offset; | |
12861 | ||
584892a6 | 12862 | macro_start (); |
67c0d1eb RS |
12863 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
12864 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 12865 | macro_end (); |
252b5132 RH |
12866 | |
12867 | demand_empty_rest_of_line (); | |
12868 | } | |
12869 | ||
6478892d | 12870 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 12871 | was given in the preceding .cpsetup, it results in: |
6478892d | 12872 | ld $gp, offset($sp) |
76b3015f | 12873 | |
6478892d | 12874 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
12875 | daddu $gp, $reg2, $0 */ |
12876 | ||
6478892d | 12877 | static void |
17a2f251 | 12878 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12879 | { |
12880 | expressionS ex; | |
6478892d TS |
12881 | |
12882 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12883 | We also need NewABI support. */ | |
12884 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12885 | { | |
12886 | s_ignore (0); | |
12887 | return; | |
12888 | } | |
12889 | ||
584892a6 | 12890 | macro_start (); |
6478892d TS |
12891 | if (mips_cpreturn_register == -1) |
12892 | { | |
12893 | ex.X_op = O_constant; | |
12894 | ex.X_add_symbol = NULL; | |
12895 | ex.X_op_symbol = NULL; | |
12896 | ex.X_add_number = mips_cpreturn_offset; | |
12897 | ||
67c0d1eb | 12898 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
12899 | } |
12900 | else | |
67c0d1eb | 12901 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 12902 | mips_cpreturn_register, 0); |
584892a6 | 12903 | macro_end (); |
6478892d TS |
12904 | |
12905 | demand_empty_rest_of_line (); | |
12906 | } | |
12907 | ||
12908 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12909 | code. It sets the offset to use in gp_rel relocations. */ | |
12910 | ||
12911 | static void | |
17a2f251 | 12912 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12913 | { |
12914 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12915 | We also need NewABI support. */ | |
12916 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12917 | { | |
12918 | s_ignore (0); | |
12919 | return; | |
12920 | } | |
12921 | ||
def2e0dd | 12922 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12923 | |
12924 | demand_empty_rest_of_line (); | |
12925 | } | |
12926 | ||
252b5132 RH |
12927 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12928 | code. It generates a 32 bit GP relative reloc. */ | |
12929 | ||
12930 | static void | |
17a2f251 | 12931 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12932 | { |
a8dbcb85 TS |
12933 | segment_info_type *si; |
12934 | struct insn_label_list *l; | |
252b5132 RH |
12935 | symbolS *label; |
12936 | expressionS ex; | |
12937 | char *p; | |
12938 | ||
12939 | /* When not generating PIC code, this is treated as .word. */ | |
12940 | if (mips_pic != SVR4_PIC) | |
12941 | { | |
12942 | s_cons (2); | |
12943 | return; | |
12944 | } | |
12945 | ||
a8dbcb85 TS |
12946 | si = seg_info (now_seg); |
12947 | l = si->label_list; | |
12948 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 12949 | mips_emit_delays (); |
252b5132 RH |
12950 | if (auto_align) |
12951 | mips_align (2, 0, label); | |
12952 | mips_clear_insn_labels (); | |
12953 | ||
12954 | expression (&ex); | |
12955 | ||
12956 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12957 | { | |
12958 | as_bad (_("Unsupported use of .gpword")); | |
12959 | ignore_rest_of_line (); | |
12960 | } | |
12961 | ||
12962 | p = frag_more (4); | |
17a2f251 | 12963 | md_number_to_chars (p, 0, 4); |
b34976b6 | 12964 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12965 | BFD_RELOC_GPREL32); |
252b5132 RH |
12966 | |
12967 | demand_empty_rest_of_line (); | |
12968 | } | |
12969 | ||
10181a0d | 12970 | static void |
17a2f251 | 12971 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 12972 | { |
a8dbcb85 TS |
12973 | segment_info_type *si; |
12974 | struct insn_label_list *l; | |
10181a0d AO |
12975 | symbolS *label; |
12976 | expressionS ex; | |
12977 | char *p; | |
12978 | ||
12979 | /* When not generating PIC code, this is treated as .dword. */ | |
12980 | if (mips_pic != SVR4_PIC) | |
12981 | { | |
12982 | s_cons (3); | |
12983 | return; | |
12984 | } | |
12985 | ||
a8dbcb85 TS |
12986 | si = seg_info (now_seg); |
12987 | l = si->label_list; | |
12988 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 12989 | mips_emit_delays (); |
10181a0d AO |
12990 | if (auto_align) |
12991 | mips_align (3, 0, label); | |
12992 | mips_clear_insn_labels (); | |
12993 | ||
12994 | expression (&ex); | |
12995 | ||
12996 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12997 | { | |
12998 | as_bad (_("Unsupported use of .gpdword")); | |
12999 | ignore_rest_of_line (); | |
13000 | } | |
13001 | ||
13002 | p = frag_more (8); | |
17a2f251 | 13003 | md_number_to_chars (p, 0, 8); |
a105a300 | 13004 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 13005 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
13006 | |
13007 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
13008 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
13009 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
13010 | |
13011 | demand_empty_rest_of_line (); | |
13012 | } | |
13013 | ||
252b5132 RH |
13014 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
13015 | tables in SVR4 PIC code. */ | |
13016 | ||
13017 | static void | |
17a2f251 | 13018 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13019 | { |
252b5132 RH |
13020 | int reg; |
13021 | ||
10181a0d AO |
13022 | /* This is ignored when not generating SVR4 PIC code. */ |
13023 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
13024 | { |
13025 | s_ignore (0); | |
13026 | return; | |
13027 | } | |
13028 | ||
13029 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 13030 | macro_start (); |
252b5132 | 13031 | reg = tc_get_register (0); |
67c0d1eb | 13032 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 13033 | macro_end (); |
252b5132 | 13034 | |
bdaaa2e1 | 13035 | demand_empty_rest_of_line (); |
252b5132 RH |
13036 | } |
13037 | ||
13038 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
13039 | mips16 mode. This permits the linker to handle them specially, | |
13040 | such as generating jalx instructions when needed. We also make | |
13041 | them odd for the duration of the assembly, in order to generate the | |
13042 | right sort of code. We will make them even in the adjust_symtab | |
13043 | routine, while leaving them marked. This is convenient for the | |
13044 | debugger and the disassembler. The linker knows to make them odd | |
13045 | again. */ | |
13046 | ||
13047 | static void | |
17a2f251 | 13048 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13049 | { |
f9419b05 | 13050 | mips16_mark_labels (); |
252b5132 RH |
13051 | |
13052 | demand_empty_rest_of_line (); | |
13053 | } | |
13054 | ||
13055 | /* Handle a .stabn directive. We need these in order to mark a label | |
13056 | as being a mips16 text label correctly. Sometimes the compiler | |
13057 | will emit a label, followed by a .stabn, and then switch sections. | |
13058 | If the label and .stabn are in mips16 mode, then the label is | |
13059 | really a mips16 text label. */ | |
13060 | ||
13061 | static void | |
17a2f251 | 13062 | s_mips_stab (int type) |
252b5132 | 13063 | { |
f9419b05 | 13064 | if (type == 'n') |
252b5132 RH |
13065 | mips16_mark_labels (); |
13066 | ||
13067 | s_stab (type); | |
13068 | } | |
13069 | ||
54f4ddb3 | 13070 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
13071 | |
13072 | static void | |
17a2f251 | 13073 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13074 | { |
13075 | char *name; | |
13076 | int c; | |
13077 | symbolS *symbolP; | |
13078 | expressionS exp; | |
13079 | ||
13080 | name = input_line_pointer; | |
13081 | c = get_symbol_end (); | |
13082 | symbolP = symbol_find_or_make (name); | |
13083 | S_SET_WEAK (symbolP); | |
13084 | *input_line_pointer = c; | |
13085 | ||
13086 | SKIP_WHITESPACE (); | |
13087 | ||
13088 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
13089 | { | |
13090 | if (S_IS_DEFINED (symbolP)) | |
13091 | { | |
956cd1d6 | 13092 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
13093 | S_GET_NAME (symbolP)); |
13094 | ignore_rest_of_line (); | |
13095 | return; | |
13096 | } | |
bdaaa2e1 | 13097 | |
252b5132 RH |
13098 | if (*input_line_pointer == ',') |
13099 | { | |
13100 | ++input_line_pointer; | |
13101 | SKIP_WHITESPACE (); | |
13102 | } | |
bdaaa2e1 | 13103 | |
252b5132 RH |
13104 | expression (&exp); |
13105 | if (exp.X_op != O_symbol) | |
13106 | { | |
13107 | as_bad ("bad .weakext directive"); | |
98d3f06f | 13108 | ignore_rest_of_line (); |
252b5132 RH |
13109 | return; |
13110 | } | |
49309057 | 13111 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
13112 | } |
13113 | ||
13114 | demand_empty_rest_of_line (); | |
13115 | } | |
13116 | ||
13117 | /* Parse a register string into a number. Called from the ECOFF code | |
13118 | to parse .frame. The argument is non-zero if this is the frame | |
13119 | register, so that we can record it in mips_frame_reg. */ | |
13120 | ||
13121 | int | |
17a2f251 | 13122 | tc_get_register (int frame) |
252b5132 | 13123 | { |
707bfff6 | 13124 | unsigned int reg; |
252b5132 RH |
13125 | |
13126 | SKIP_WHITESPACE (); | |
707bfff6 TS |
13127 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
13128 | reg = 0; | |
252b5132 | 13129 | if (frame) |
7a621144 DJ |
13130 | { |
13131 | mips_frame_reg = reg != 0 ? reg : SP; | |
13132 | mips_frame_reg_valid = 1; | |
13133 | mips_cprestore_valid = 0; | |
13134 | } | |
252b5132 RH |
13135 | return reg; |
13136 | } | |
13137 | ||
13138 | valueT | |
17a2f251 | 13139 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
13140 | { |
13141 | int align = bfd_get_section_alignment (stdoutput, seg); | |
13142 | ||
b4c71f56 TS |
13143 | if (IS_ELF) |
13144 | { | |
13145 | /* We don't need to align ELF sections to the full alignment. | |
13146 | However, Irix 5 may prefer that we align them at least to a 16 | |
13147 | byte boundary. We don't bother to align the sections if we | |
13148 | are targeted for an embedded system. */ | |
13149 | if (strcmp (TARGET_OS, "elf") == 0) | |
13150 | return addr; | |
13151 | if (align > 4) | |
13152 | align = 4; | |
13153 | } | |
252b5132 RH |
13154 | |
13155 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
13156 | } | |
13157 | ||
13158 | /* Utility routine, called from above as well. If called while the | |
13159 | input file is still being read, it's only an approximation. (For | |
13160 | example, a symbol may later become defined which appeared to be | |
13161 | undefined earlier.) */ | |
13162 | ||
13163 | static int | |
17a2f251 | 13164 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
13165 | { |
13166 | if (sym == 0) | |
13167 | return 0; | |
13168 | ||
4d0d148d | 13169 | if (g_switch_value > 0) |
252b5132 RH |
13170 | { |
13171 | const char *symname; | |
13172 | int change; | |
13173 | ||
c9914766 | 13174 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
13175 | register. It can be if it is smaller than the -G size or if |
13176 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 13177 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
13178 | they can. */ |
13179 | symname = S_GET_NAME (sym); | |
13180 | if (symname != (const char *) NULL | |
13181 | && (strcmp (symname, "eprol") == 0 | |
13182 | || strcmp (symname, "etext") == 0 | |
13183 | || strcmp (symname, "_gp") == 0 | |
13184 | || strcmp (symname, "edata") == 0 | |
13185 | || strcmp (symname, "_fbss") == 0 | |
13186 | || strcmp (symname, "_fdata") == 0 | |
13187 | || strcmp (symname, "_ftext") == 0 | |
13188 | || strcmp (symname, "end") == 0 | |
13189 | || strcmp (symname, "_gp_disp") == 0)) | |
13190 | change = 1; | |
13191 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
13192 | && (0 | |
13193 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
13194 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
13195 | && (symbol_get_obj (sym)->ecoff_extern_size | |
13196 | <= g_switch_value)) | |
252b5132 RH |
13197 | #endif |
13198 | /* We must defer this decision until after the whole | |
13199 | file has been read, since there might be a .extern | |
13200 | after the first use of this symbol. */ | |
13201 | || (before_relaxing | |
13202 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 13203 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
13204 | #endif |
13205 | && S_GET_VALUE (sym) == 0) | |
13206 | || (S_GET_VALUE (sym) != 0 | |
13207 | && S_GET_VALUE (sym) <= g_switch_value))) | |
13208 | change = 0; | |
13209 | else | |
13210 | { | |
13211 | const char *segname; | |
13212 | ||
13213 | segname = segment_name (S_GET_SEGMENT (sym)); | |
13214 | assert (strcmp (segname, ".lit8") != 0 | |
13215 | && strcmp (segname, ".lit4") != 0); | |
13216 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
13217 | && strcmp (segname, ".sbss") != 0 |
13218 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
13219 | && strncmp (segname, ".sbss.", 6) != 0 |
13220 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 13221 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
13222 | } |
13223 | return change; | |
13224 | } | |
13225 | else | |
c9914766 | 13226 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
13227 | return 1; |
13228 | } | |
13229 | ||
5919d012 RS |
13230 | |
13231 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
13232 | ||
13233 | static bfd_boolean | |
17a2f251 | 13234 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
13235 | { |
13236 | asection *symsec; | |
5919d012 RS |
13237 | |
13238 | /* Handle the case of a symbol equated to another symbol. */ | |
13239 | while (symbol_equated_reloc_p (sym)) | |
13240 | { | |
13241 | symbolS *n; | |
13242 | ||
5f0fe04b | 13243 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
13244 | n = symbol_get_value_expression (sym)->X_add_symbol; |
13245 | if (n == sym) | |
13246 | break; | |
13247 | sym = n; | |
13248 | } | |
13249 | ||
df1f3cda DD |
13250 | if (symbol_section_p (sym)) |
13251 | return TRUE; | |
13252 | ||
5919d012 RS |
13253 | symsec = S_GET_SEGMENT (sym); |
13254 | ||
5919d012 RS |
13255 | /* This must duplicate the test in adjust_reloc_syms. */ |
13256 | return (symsec != &bfd_und_section | |
13257 | && symsec != &bfd_abs_section | |
5f0fe04b TS |
13258 | && !bfd_is_com_section (symsec) |
13259 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
13260 | #ifdef OBJ_ELF |
13261 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 13262 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
13263 | #endif |
13264 | ); | |
13265 | } | |
13266 | ||
13267 | ||
252b5132 RH |
13268 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
13269 | extended opcode. SEC is the section the frag is in. */ | |
13270 | ||
13271 | static int | |
17a2f251 | 13272 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
13273 | { |
13274 | int type; | |
3994f87e | 13275 | const struct mips16_immed_operand *op; |
252b5132 RH |
13276 | offsetT val; |
13277 | int mintiny, maxtiny; | |
13278 | segT symsec; | |
98aa84af | 13279 | fragS *sym_frag; |
252b5132 RH |
13280 | |
13281 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
13282 | return 0; | |
13283 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
13284 | return 1; | |
13285 | ||
13286 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13287 | op = mips16_immed_operands; | |
13288 | while (op->type != type) | |
13289 | { | |
13290 | ++op; | |
13291 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
13292 | } | |
13293 | ||
13294 | if (op->unsp) | |
13295 | { | |
13296 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13297 | { | |
13298 | mintiny = 1; | |
13299 | maxtiny = 1 << op->nbits; | |
13300 | } | |
13301 | else | |
13302 | { | |
13303 | mintiny = 0; | |
13304 | maxtiny = (1 << op->nbits) - 1; | |
13305 | } | |
13306 | } | |
13307 | else | |
13308 | { | |
13309 | mintiny = - (1 << (op->nbits - 1)); | |
13310 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13311 | } | |
13312 | ||
98aa84af | 13313 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 13314 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 13315 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
13316 | |
13317 | if (op->pcrel) | |
13318 | { | |
13319 | addressT addr; | |
13320 | ||
13321 | /* We won't have the section when we are called from | |
13322 | mips_relax_frag. However, we will always have been called | |
13323 | from md_estimate_size_before_relax first. If this is a | |
13324 | branch to a different section, we mark it as such. If SEC is | |
13325 | NULL, and the frag is not marked, then it must be a branch to | |
13326 | the same section. */ | |
13327 | if (sec == NULL) | |
13328 | { | |
13329 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
13330 | return 1; | |
13331 | } | |
13332 | else | |
13333 | { | |
98aa84af | 13334 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
13335 | if (symsec != sec) |
13336 | { | |
13337 | fragp->fr_subtype = | |
13338 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13339 | ||
13340 | /* FIXME: We should support this, and let the linker | |
13341 | catch branches and loads that are out of range. */ | |
13342 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
13343 | _("unsupported PC relative reference to different section")); | |
13344 | ||
13345 | return 1; | |
13346 | } | |
98aa84af AM |
13347 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
13348 | /* Assume non-extended on the first relaxation pass. | |
13349 | The address we have calculated will be bogus if this is | |
13350 | a forward branch to another frag, as the forward frag | |
13351 | will have fr_address == 0. */ | |
13352 | return 0; | |
252b5132 RH |
13353 | } |
13354 | ||
13355 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
13356 | the same section. If the relax_marker of the symbol fragment |
13357 | differs from the relax_marker of this fragment, we have not | |
13358 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
13359 | in STRETCH in order to get a better estimate of the address. |
13360 | This particularly matters because of the shift bits. */ | |
13361 | if (stretch != 0 | |
98aa84af | 13362 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
13363 | { |
13364 | fragS *f; | |
13365 | ||
13366 | /* Adjust stretch for any alignment frag. Note that if have | |
13367 | been expanding the earlier code, the symbol may be | |
13368 | defined in what appears to be an earlier frag. FIXME: | |
13369 | This doesn't handle the fr_subtype field, which specifies | |
13370 | a maximum number of bytes to skip when doing an | |
13371 | alignment. */ | |
98aa84af | 13372 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
13373 | { |
13374 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
13375 | { | |
13376 | if (stretch < 0) | |
13377 | stretch = - ((- stretch) | |
13378 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
13379 | else | |
13380 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
13381 | if (stretch == 0) | |
13382 | break; | |
13383 | } | |
13384 | } | |
13385 | if (f != NULL) | |
13386 | val += stretch; | |
13387 | } | |
13388 | ||
13389 | addr = fragp->fr_address + fragp->fr_fix; | |
13390 | ||
13391 | /* The base address rules are complicated. The base address of | |
13392 | a branch is the following instruction. The base address of a | |
13393 | PC relative load or add is the instruction itself, but if it | |
13394 | is in a delay slot (in which case it can not be extended) use | |
13395 | the address of the instruction whose delay slot it is in. */ | |
13396 | if (type == 'p' || type == 'q') | |
13397 | { | |
13398 | addr += 2; | |
13399 | ||
13400 | /* If we are currently assuming that this frag should be | |
13401 | extended, then, the current address is two bytes | |
bdaaa2e1 | 13402 | higher. */ |
252b5132 RH |
13403 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
13404 | addr += 2; | |
13405 | ||
13406 | /* Ignore the low bit in the target, since it will be set | |
13407 | for a text label. */ | |
13408 | if ((val & 1) != 0) | |
13409 | --val; | |
13410 | } | |
13411 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13412 | addr -= 4; | |
13413 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13414 | addr -= 2; | |
13415 | ||
13416 | val -= addr & ~ ((1 << op->shift) - 1); | |
13417 | ||
13418 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
13419 | if (type == 'p' || type == 'q') | |
13420 | val /= 2; | |
13421 | ||
13422 | /* If any of the shifted bits are set, we must use an extended | |
13423 | opcode. If the address depends on the size of this | |
13424 | instruction, this can lead to a loop, so we arrange to always | |
13425 | use an extended opcode. We only check this when we are in | |
13426 | the main relaxation loop, when SEC is NULL. */ | |
13427 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
13428 | { | |
13429 | fragp->fr_subtype = | |
13430 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13431 | return 1; | |
13432 | } | |
13433 | ||
13434 | /* If we are about to mark a frag as extended because the value | |
13435 | is precisely maxtiny + 1, then there is a chance of an | |
13436 | infinite loop as in the following code: | |
13437 | la $4,foo | |
13438 | .skip 1020 | |
13439 | .align 2 | |
13440 | foo: | |
13441 | In this case when the la is extended, foo is 0x3fc bytes | |
13442 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
13443 | the la must be extended. To avoid this loop, we mark the | |
13444 | frag as extended if it was small, and is about to become | |
13445 | extended with a value of maxtiny + 1. */ | |
13446 | if (val == ((maxtiny + 1) << op->shift) | |
13447 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
13448 | && sec == NULL) | |
13449 | { | |
13450 | fragp->fr_subtype = | |
13451 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13452 | return 1; | |
13453 | } | |
13454 | } | |
13455 | else if (symsec != absolute_section && sec != NULL) | |
13456 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
13457 | ||
13458 | if ((val & ((1 << op->shift) - 1)) != 0 | |
13459 | || val < (mintiny << op->shift) | |
13460 | || val > (maxtiny << op->shift)) | |
13461 | return 1; | |
13462 | else | |
13463 | return 0; | |
13464 | } | |
13465 | ||
4a6a3df4 AO |
13466 | /* Compute the length of a branch sequence, and adjust the |
13467 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
13468 | worst-case length is computed, with UPDATE being used to indicate | |
13469 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
13470 | branch is to be computed. */ | |
13471 | static int | |
17a2f251 | 13472 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 13473 | { |
b34976b6 | 13474 | bfd_boolean toofar; |
4a6a3df4 AO |
13475 | int length; |
13476 | ||
13477 | if (fragp | |
13478 | && S_IS_DEFINED (fragp->fr_symbol) | |
13479 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
13480 | { | |
13481 | addressT addr; | |
13482 | offsetT val; | |
13483 | ||
13484 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
13485 | ||
13486 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
13487 | ||
13488 | val -= addr; | |
13489 | ||
13490 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
13491 | } | |
13492 | else if (fragp) | |
13493 | /* If the symbol is not defined or it's in a different segment, | |
13494 | assume the user knows what's going on and emit a short | |
13495 | branch. */ | |
b34976b6 | 13496 | toofar = FALSE; |
4a6a3df4 | 13497 | else |
b34976b6 | 13498 | toofar = TRUE; |
4a6a3df4 AO |
13499 | |
13500 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
13501 | fragp->fr_subtype | |
af6ae2ad | 13502 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
13503 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
13504 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
13505 | toofar); | |
13506 | ||
13507 | length = 4; | |
13508 | if (toofar) | |
13509 | { | |
13510 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
13511 | length += 8; | |
13512 | ||
13513 | if (mips_pic != NO_PIC) | |
13514 | { | |
13515 | /* Additional space for PIC loading of target address. */ | |
13516 | length += 8; | |
13517 | if (mips_opts.isa == ISA_MIPS1) | |
13518 | /* Additional space for $at-stabilizing nop. */ | |
13519 | length += 4; | |
13520 | } | |
13521 | ||
13522 | /* If branch is conditional. */ | |
13523 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
13524 | length += 8; | |
13525 | } | |
b34976b6 | 13526 | |
4a6a3df4 AO |
13527 | return length; |
13528 | } | |
13529 | ||
252b5132 RH |
13530 | /* Estimate the size of a frag before relaxing. Unless this is the |
13531 | mips16, we are not really relaxing here, and the final size is | |
13532 | encoded in the subtype information. For the mips16, we have to | |
13533 | decide whether we are using an extended opcode or not. */ | |
13534 | ||
252b5132 | 13535 | int |
17a2f251 | 13536 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 13537 | { |
5919d012 | 13538 | int change; |
252b5132 | 13539 | |
4a6a3df4 AO |
13540 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13541 | { | |
13542 | ||
b34976b6 AM |
13543 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
13544 | ||
4a6a3df4 AO |
13545 | return fragp->fr_var; |
13546 | } | |
13547 | ||
252b5132 | 13548 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
13549 | /* We don't want to modify the EXTENDED bit here; it might get us |
13550 | into infinite loops. We change it only in mips_relax_frag(). */ | |
13551 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
13552 | |
13553 | if (mips_pic == NO_PIC) | |
5919d012 | 13554 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 13555 | else if (mips_pic == SVR4_PIC) |
5919d012 | 13556 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
13557 | else if (mips_pic == VXWORKS_PIC) |
13558 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
13559 | change = 0; | |
252b5132 RH |
13560 | else |
13561 | abort (); | |
13562 | ||
13563 | if (change) | |
13564 | { | |
4d7206a2 | 13565 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 13566 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 13567 | } |
4d7206a2 RS |
13568 | else |
13569 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
13570 | } |
13571 | ||
13572 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 13573 | should be converted into a reloc against a section. */ |
252b5132 RH |
13574 | |
13575 | int | |
17a2f251 | 13576 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 13577 | { |
252b5132 RH |
13578 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
13579 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13580 | return 0; | |
a161fe53 | 13581 | |
252b5132 RH |
13582 | if (fixp->fx_addsy == NULL) |
13583 | return 1; | |
a161fe53 | 13584 | |
de7e6852 RS |
13585 | /* If symbol SYM is in a mergeable section, relocations of the form |
13586 | SYM + 0 can usually be made section-relative. The mergeable data | |
13587 | is then identified by the section offset rather than by the symbol. | |
13588 | ||
13589 | However, if we're generating REL LO16 relocations, the offset is split | |
13590 | between the LO16 and parterning high part relocation. The linker will | |
13591 | need to recalculate the complete offset in order to correctly identify | |
13592 | the merge data. | |
13593 | ||
13594 | The linker has traditionally not looked for the parterning high part | |
13595 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
13596 | placed anywhere. Rather than break backwards compatibility by changing | |
13597 | this, it seems better not to force the issue, and instead keep the | |
13598 | original symbol. This will work with either linker behavior. */ | |
704803a9 MR |
13599 | if ((fixp->fx_r_type == BFD_RELOC_LO16 |
13600 | || fixp->fx_r_type == BFD_RELOC_MIPS16_LO16 | |
13601 | || reloc_needs_lo_p (fixp->fx_r_type)) | |
de7e6852 RS |
13602 | && HAVE_IN_PLACE_ADDENDS |
13603 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
13604 | return 0; | |
13605 | ||
252b5132 | 13606 | #ifdef OBJ_ELF |
de7e6852 RS |
13607 | /* Don't adjust relocations against mips16 symbols, so that the linker |
13608 | can find them if it needs to set up a stub. */ | |
f43abd2b | 13609 | if (IS_ELF |
252b5132 RH |
13610 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 |
13611 | && fixp->fx_subsy == NULL) | |
13612 | return 0; | |
13613 | #endif | |
a161fe53 | 13614 | |
252b5132 RH |
13615 | return 1; |
13616 | } | |
13617 | ||
13618 | /* Translate internal representation of relocation info to BFD target | |
13619 | format. */ | |
13620 | ||
13621 | arelent ** | |
17a2f251 | 13622 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13623 | { |
13624 | static arelent *retval[4]; | |
13625 | arelent *reloc; | |
13626 | bfd_reloc_code_real_type code; | |
13627 | ||
4b0cff4e TS |
13628 | memset (retval, 0, sizeof(retval)); |
13629 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
13630 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13631 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13632 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
13633 | ||
bad36eac DJ |
13634 | if (fixp->fx_pcrel) |
13635 | { | |
13636 | assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2); | |
13637 | ||
13638 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
13639 | Relocations want only the symbol offset. */ | |
13640 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 13641 | if (!IS_ELF) |
bad36eac DJ |
13642 | { |
13643 | /* A gruesome hack which is a result of the gruesome gas | |
13644 | reloc handling. What's worse, for COFF (as opposed to | |
13645 | ECOFF), we might need yet another copy of reloc->address. | |
13646 | See bfd_install_relocation. */ | |
13647 | reloc->addend += reloc->address; | |
13648 | } | |
13649 | } | |
13650 | else | |
13651 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 13652 | |
438c16b8 TS |
13653 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
13654 | entry to be used in the relocation's section offset. */ | |
13655 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
13656 | { |
13657 | reloc->address = reloc->addend; | |
13658 | reloc->addend = 0; | |
13659 | } | |
13660 | ||
252b5132 | 13661 | code = fixp->fx_r_type; |
252b5132 | 13662 | |
bad36eac | 13663 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
13664 | if (reloc->howto == NULL) |
13665 | { | |
13666 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13667 | _("Can not represent %s relocation in this object file format"), | |
13668 | bfd_get_reloc_code_name (code)); | |
13669 | retval[0] = NULL; | |
13670 | } | |
13671 | ||
13672 | return retval; | |
13673 | } | |
13674 | ||
13675 | /* Relax a machine dependent frag. This returns the amount by which | |
13676 | the current size of the frag should change. */ | |
13677 | ||
13678 | int | |
17a2f251 | 13679 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 13680 | { |
4a6a3df4 AO |
13681 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13682 | { | |
13683 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
13684 | |
13685 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
13686 | |
13687 | return fragp->fr_var - old_var; | |
13688 | } | |
13689 | ||
252b5132 RH |
13690 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
13691 | return 0; | |
13692 | ||
c4e7957c | 13693 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
13694 | { |
13695 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13696 | return 0; | |
13697 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
13698 | return 2; | |
13699 | } | |
13700 | else | |
13701 | { | |
13702 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13703 | return 0; | |
13704 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
13705 | return -2; | |
13706 | } | |
13707 | ||
13708 | return 0; | |
13709 | } | |
13710 | ||
13711 | /* Convert a machine dependent frag. */ | |
13712 | ||
13713 | void | |
17a2f251 | 13714 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 13715 | { |
4a6a3df4 AO |
13716 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13717 | { | |
13718 | bfd_byte *buf; | |
13719 | unsigned long insn; | |
13720 | expressionS exp; | |
13721 | fixS *fixp; | |
b34976b6 | 13722 | |
4a6a3df4 AO |
13723 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
13724 | ||
13725 | if (target_big_endian) | |
13726 | insn = bfd_getb32 (buf); | |
13727 | else | |
13728 | insn = bfd_getl32 (buf); | |
b34976b6 | 13729 | |
4a6a3df4 AO |
13730 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
13731 | { | |
13732 | /* We generate a fixup instead of applying it right now | |
13733 | because, if there are linker relaxations, we're going to | |
13734 | need the relocations. */ | |
13735 | exp.X_op = O_symbol; | |
13736 | exp.X_add_symbol = fragp->fr_symbol; | |
13737 | exp.X_add_number = fragp->fr_offset; | |
13738 | ||
13739 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 13740 | 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
13741 | fixp->fx_file = fragp->fr_file; |
13742 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13743 | |
2132e3a3 | 13744 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13745 | buf += 4; |
13746 | } | |
13747 | else | |
13748 | { | |
13749 | int i; | |
13750 | ||
13751 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13752 | _("relaxed out-of-range branch into a jump")); | |
13753 | ||
13754 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
13755 | goto uncond; | |
13756 | ||
13757 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13758 | { | |
13759 | /* Reverse the branch. */ | |
13760 | switch ((insn >> 28) & 0xf) | |
13761 | { | |
13762 | case 4: | |
13763 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
13764 | have the condition reversed by tweaking a single | |
13765 | bit, and their opcodes all have 0x4???????. */ | |
13766 | assert ((insn & 0xf1000000) == 0x41000000); | |
13767 | insn ^= 0x00010000; | |
13768 | break; | |
13769 | ||
13770 | case 0: | |
13771 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 13772 | bltzal 0x04100000 bgezal 0x04110000 */ |
4a6a3df4 AO |
13773 | assert ((insn & 0xfc0e0000) == 0x04000000); |
13774 | insn ^= 0x00010000; | |
13775 | break; | |
b34976b6 | 13776 | |
4a6a3df4 AO |
13777 | case 1: |
13778 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 13779 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
13780 | insn ^= 0x04000000; |
13781 | break; | |
13782 | ||
13783 | default: | |
13784 | abort (); | |
13785 | } | |
13786 | } | |
13787 | ||
13788 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13789 | { | |
13790 | /* Clear the and-link bit. */ | |
13791 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13792 | ||
54f4ddb3 TS |
13793 | /* bltzal 0x04100000 bgezal 0x04110000 |
13794 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
13795 | insn &= ~0x00100000; |
13796 | } | |
13797 | ||
13798 | /* Branch over the branch (if the branch was likely) or the | |
13799 | full jump (not likely case). Compute the offset from the | |
13800 | current instruction to branch to. */ | |
13801 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13802 | i = 16; | |
13803 | else | |
13804 | { | |
13805 | /* How many bytes in instructions we've already emitted? */ | |
13806 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13807 | /* How many bytes in instructions from here to the end? */ | |
13808 | i = fragp->fr_var - i; | |
13809 | } | |
13810 | /* Convert to instruction count. */ | |
13811 | i >>= 2; | |
13812 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13813 | i--; |
4a6a3df4 AO |
13814 | insn |= i; |
13815 | /* Branch over the jump. */ | |
2132e3a3 | 13816 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13817 | buf += 4; |
13818 | ||
54f4ddb3 | 13819 | /* nop */ |
2132e3a3 | 13820 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13821 | buf += 4; |
13822 | ||
13823 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13824 | { | |
13825 | /* beql $0, $0, 2f */ | |
13826 | insn = 0x50000000; | |
13827 | /* Compute the PC offset from the current instruction to | |
13828 | the end of the variable frag. */ | |
13829 | /* How many bytes in instructions we've already emitted? */ | |
13830 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13831 | /* How many bytes in instructions from here to the end? */ | |
13832 | i = fragp->fr_var - i; | |
13833 | /* Convert to instruction count. */ | |
13834 | i >>= 2; | |
13835 | /* Don't decrement i, because we want to branch over the | |
13836 | delay slot. */ | |
13837 | ||
13838 | insn |= i; | |
2132e3a3 | 13839 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13840 | buf += 4; |
13841 | ||
2132e3a3 | 13842 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13843 | buf += 4; |
13844 | } | |
13845 | ||
13846 | uncond: | |
13847 | if (mips_pic == NO_PIC) | |
13848 | { | |
13849 | /* j or jal. */ | |
13850 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13851 | ? 0x0c000000 : 0x08000000); | |
13852 | exp.X_op = O_symbol; | |
13853 | exp.X_add_symbol = fragp->fr_symbol; | |
13854 | exp.X_add_number = fragp->fr_offset; | |
13855 | ||
13856 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 13857 | 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); |
4a6a3df4 AO |
13858 | fixp->fx_file = fragp->fr_file; |
13859 | fixp->fx_line = fragp->fr_line; | |
13860 | ||
2132e3a3 | 13861 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13862 | buf += 4; |
13863 | } | |
13864 | else | |
13865 | { | |
13866 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13867 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13868 | exp.X_op = O_symbol; | |
13869 | exp.X_add_symbol = fragp->fr_symbol; | |
13870 | exp.X_add_number = fragp->fr_offset; | |
13871 | ||
13872 | if (fragp->fr_offset) | |
13873 | { | |
13874 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13875 | exp.X_add_number = 0; | |
13876 | } | |
13877 | ||
13878 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 13879 | 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16); |
4a6a3df4 AO |
13880 | fixp->fx_file = fragp->fr_file; |
13881 | fixp->fx_line = fragp->fr_line; | |
13882 | ||
2132e3a3 | 13883 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 13884 | buf += 4; |
b34976b6 | 13885 | |
4a6a3df4 AO |
13886 | if (mips_opts.isa == ISA_MIPS1) |
13887 | { | |
13888 | /* nop */ | |
2132e3a3 | 13889 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13890 | buf += 4; |
13891 | } | |
13892 | ||
13893 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13894 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13895 | ||
13896 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 13897 | 4, &exp, FALSE, BFD_RELOC_LO16); |
4a6a3df4 AO |
13898 | fixp->fx_file = fragp->fr_file; |
13899 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13900 | |
2132e3a3 | 13901 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13902 | buf += 4; |
13903 | ||
13904 | /* j(al)r $at. */ | |
13905 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13906 | insn = 0x0020f809; | |
13907 | else | |
13908 | insn = 0x00200008; | |
13909 | ||
2132e3a3 | 13910 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13911 | buf += 4; |
13912 | } | |
13913 | } | |
13914 | ||
13915 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13916 | + fragp->fr_fix + fragp->fr_var); | |
13917 | ||
13918 | fragp->fr_fix += fragp->fr_var; | |
13919 | ||
13920 | return; | |
13921 | } | |
13922 | ||
252b5132 RH |
13923 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13924 | { | |
13925 | int type; | |
3994f87e | 13926 | const struct mips16_immed_operand *op; |
b34976b6 | 13927 | bfd_boolean small, ext; |
252b5132 RH |
13928 | offsetT val; |
13929 | bfd_byte *buf; | |
13930 | unsigned long insn; | |
b34976b6 | 13931 | bfd_boolean use_extend; |
252b5132 RH |
13932 | unsigned short extend; |
13933 | ||
13934 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13935 | op = mips16_immed_operands; | |
13936 | while (op->type != type) | |
13937 | ++op; | |
13938 | ||
13939 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13940 | { | |
b34976b6 AM |
13941 | small = FALSE; |
13942 | ext = TRUE; | |
252b5132 RH |
13943 | } |
13944 | else | |
13945 | { | |
b34976b6 AM |
13946 | small = TRUE; |
13947 | ext = FALSE; | |
252b5132 RH |
13948 | } |
13949 | ||
6386f3a7 | 13950 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13951 | val = S_GET_VALUE (fragp->fr_symbol); |
13952 | if (op->pcrel) | |
13953 | { | |
13954 | addressT addr; | |
13955 | ||
13956 | addr = fragp->fr_address + fragp->fr_fix; | |
13957 | ||
13958 | /* The rules for the base address of a PC relative reloc are | |
13959 | complicated; see mips16_extended_frag. */ | |
13960 | if (type == 'p' || type == 'q') | |
13961 | { | |
13962 | addr += 2; | |
13963 | if (ext) | |
13964 | addr += 2; | |
13965 | /* Ignore the low bit in the target, since it will be | |
13966 | set for a text label. */ | |
13967 | if ((val & 1) != 0) | |
13968 | --val; | |
13969 | } | |
13970 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13971 | addr -= 4; | |
13972 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13973 | addr -= 2; | |
13974 | ||
13975 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13976 | val -= addr; | |
13977 | ||
13978 | /* Make sure the section winds up with the alignment we have | |
13979 | assumed. */ | |
13980 | if (op->shift > 0) | |
13981 | record_alignment (asec, op->shift); | |
13982 | } | |
13983 | ||
13984 | if (ext | |
13985 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13986 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13987 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13988 | _("extended instruction in delay slot")); | |
13989 | ||
13990 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13991 | ||
13992 | if (target_big_endian) | |
13993 | insn = bfd_getb16 (buf); | |
13994 | else | |
13995 | insn = bfd_getl16 (buf); | |
13996 | ||
13997 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13998 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13999 | small, ext, &insn, &use_extend, &extend); | |
14000 | ||
14001 | if (use_extend) | |
14002 | { | |
2132e3a3 | 14003 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
14004 | fragp->fr_fix += 2; |
14005 | buf += 2; | |
14006 | } | |
14007 | ||
2132e3a3 | 14008 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
14009 | fragp->fr_fix += 2; |
14010 | buf += 2; | |
14011 | } | |
14012 | else | |
14013 | { | |
4d7206a2 RS |
14014 | int first, second; |
14015 | fixS *fixp; | |
252b5132 | 14016 | |
4d7206a2 RS |
14017 | first = RELAX_FIRST (fragp->fr_subtype); |
14018 | second = RELAX_SECOND (fragp->fr_subtype); | |
14019 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 14020 | |
584892a6 RS |
14021 | /* Possibly emit a warning if we've chosen the longer option. */ |
14022 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
14023 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
14024 | { | |
14025 | const char *msg = macro_warning (fragp->fr_subtype); | |
14026 | if (msg != 0) | |
14027 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
14028 | } | |
14029 | ||
4d7206a2 RS |
14030 | /* Go through all the fixups for the first sequence. Disable them |
14031 | (by marking them as done) if we're going to use the second | |
14032 | sequence instead. */ | |
14033 | while (fixp | |
14034 | && fixp->fx_frag == fragp | |
14035 | && fixp->fx_where < fragp->fr_fix - second) | |
14036 | { | |
14037 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14038 | fixp->fx_done = 1; | |
14039 | fixp = fixp->fx_next; | |
14040 | } | |
252b5132 | 14041 | |
4d7206a2 RS |
14042 | /* Go through the fixups for the second sequence. Disable them if |
14043 | we're going to use the first sequence, otherwise adjust their | |
14044 | addresses to account for the relaxation. */ | |
14045 | while (fixp && fixp->fx_frag == fragp) | |
14046 | { | |
14047 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14048 | fixp->fx_where -= first; | |
14049 | else | |
14050 | fixp->fx_done = 1; | |
14051 | fixp = fixp->fx_next; | |
14052 | } | |
14053 | ||
14054 | /* Now modify the frag contents. */ | |
14055 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14056 | { | |
14057 | char *start; | |
14058 | ||
14059 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
14060 | memmove (start, start + first, second); | |
14061 | fragp->fr_fix -= first; | |
14062 | } | |
14063 | else | |
14064 | fragp->fr_fix -= second; | |
252b5132 RH |
14065 | } |
14066 | } | |
14067 | ||
14068 | #ifdef OBJ_ELF | |
14069 | ||
14070 | /* This function is called after the relocs have been generated. | |
14071 | We've been storing mips16 text labels as odd. Here we convert them | |
14072 | back to even for the convenience of the debugger. */ | |
14073 | ||
14074 | void | |
17a2f251 | 14075 | mips_frob_file_after_relocs (void) |
252b5132 RH |
14076 | { |
14077 | asymbol **syms; | |
14078 | unsigned int count, i; | |
14079 | ||
f43abd2b | 14080 | if (!IS_ELF) |
252b5132 RH |
14081 | return; |
14082 | ||
14083 | syms = bfd_get_outsymbols (stdoutput); | |
14084 | count = bfd_get_symcount (stdoutput); | |
14085 | for (i = 0; i < count; i++, syms++) | |
14086 | { | |
14087 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
14088 | && ((*syms)->value & 1) != 0) | |
14089 | { | |
14090 | (*syms)->value &= ~1; | |
14091 | /* If the symbol has an odd size, it was probably computed | |
14092 | incorrectly, so adjust that as well. */ | |
14093 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
14094 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
14095 | } | |
14096 | } | |
14097 | } | |
14098 | ||
14099 | #endif | |
14100 | ||
14101 | /* This function is called whenever a label is defined. It is used | |
14102 | when handling branch delays; if a branch has a label, we assume we | |
14103 | can not move it. */ | |
14104 | ||
14105 | void | |
17a2f251 | 14106 | mips_define_label (symbolS *sym) |
252b5132 | 14107 | { |
a8dbcb85 | 14108 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
14109 | struct insn_label_list *l; |
14110 | ||
14111 | if (free_insn_labels == NULL) | |
14112 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
14113 | else | |
14114 | { | |
14115 | l = free_insn_labels; | |
14116 | free_insn_labels = l->next; | |
14117 | } | |
14118 | ||
14119 | l->label = sym; | |
a8dbcb85 TS |
14120 | l->next = si->label_list; |
14121 | si->label_list = l; | |
07a53e5c RH |
14122 | |
14123 | #ifdef OBJ_ELF | |
14124 | dwarf2_emit_label (sym); | |
14125 | #endif | |
252b5132 RH |
14126 | } |
14127 | \f | |
14128 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14129 | ||
14130 | /* Some special processing for a MIPS ELF file. */ | |
14131 | ||
14132 | void | |
17a2f251 | 14133 | mips_elf_final_processing (void) |
252b5132 RH |
14134 | { |
14135 | /* Write out the register information. */ | |
316f5878 | 14136 | if (mips_abi != N64_ABI) |
252b5132 RH |
14137 | { |
14138 | Elf32_RegInfo s; | |
14139 | ||
14140 | s.ri_gprmask = mips_gprmask; | |
14141 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14142 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14143 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14144 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14145 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14146 | ||
14147 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
14148 | ((Elf32_External_RegInfo *) | |
14149 | mips_regmask_frag)); | |
14150 | } | |
14151 | else | |
14152 | { | |
14153 | Elf64_Internal_RegInfo s; | |
14154 | ||
14155 | s.ri_gprmask = mips_gprmask; | |
14156 | s.ri_pad = 0; | |
14157 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14158 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14159 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14160 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14161 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14162 | ||
14163 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
14164 | ((Elf64_External_RegInfo *) | |
14165 | mips_regmask_frag)); | |
14166 | } | |
14167 | ||
14168 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
14169 | sort of BFD interface for this. */ | |
14170 | if (mips_any_noreorder) | |
14171 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
14172 | if (mips_pic != NO_PIC) | |
143d77c5 | 14173 | { |
252b5132 | 14174 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
14175 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
14176 | } | |
14177 | if (mips_abicalls) | |
14178 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 14179 | |
98d3f06f | 14180 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
14181 | /* We may need to define a new flag for DSP ASE, and set this flag when |
14182 | file_ase_dsp is true. */ | |
8b082fb1 | 14183 | /* Same for DSP R2. */ |
ef2e4d86 CF |
14184 | /* We may need to define a new flag for MT ASE, and set this flag when |
14185 | file_ase_mt is true. */ | |
a4672219 TS |
14186 | if (file_ase_mips16) |
14187 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
14188 | #if 0 /* XXX FIXME */ |
14189 | if (file_ase_mips3d) | |
14190 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14191 | #endif | |
deec1734 CD |
14192 | if (file_ase_mdmx) |
14193 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 14194 | |
bdaaa2e1 | 14195 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 14196 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 14197 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 14198 | else if (mips_abi == O64_ABI) |
252b5132 | 14199 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 14200 | else if (mips_abi == EABI_ABI) |
252b5132 | 14201 | { |
316f5878 | 14202 | if (!file_mips_gp32) |
252b5132 RH |
14203 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
14204 | else | |
14205 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
14206 | } | |
316f5878 | 14207 | else if (mips_abi == N32_ABI) |
be00bddd TS |
14208 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
14209 | ||
c9914766 | 14210 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
14211 | |
14212 | if (mips_32bitmode) | |
14213 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
14214 | |
14215 | #if 0 /* XXX FIXME */ | |
14216 | /* 32 bit code with 64 bit FP registers. */ | |
14217 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14218 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14219 | #endif | |
252b5132 RH |
14220 | } |
14221 | ||
14222 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
14223 | \f | |
beae10d5 | 14224 | typedef struct proc { |
9b2f1d35 EC |
14225 | symbolS *func_sym; |
14226 | symbolS *func_end_sym; | |
beae10d5 KH |
14227 | unsigned long reg_mask; |
14228 | unsigned long reg_offset; | |
14229 | unsigned long fpreg_mask; | |
14230 | unsigned long fpreg_offset; | |
14231 | unsigned long frame_offset; | |
14232 | unsigned long frame_reg; | |
14233 | unsigned long pc_reg; | |
14234 | } procS; | |
252b5132 RH |
14235 | |
14236 | static procS cur_proc; | |
14237 | static procS *cur_proc_ptr; | |
14238 | static int numprocs; | |
14239 | ||
0a9ef439 | 14240 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 14241 | |
0a9ef439 | 14242 | void |
17a2f251 | 14243 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 14244 | { |
0a9ef439 RH |
14245 | if (fragp->fr_type != rs_align_code) |
14246 | return; | |
14247 | ||
14248 | if (mips_opts.mips16) | |
a19d8eb0 CP |
14249 | { |
14250 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
14251 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
14252 | ||
0a9ef439 RH |
14253 | int bytes; |
14254 | char *p; | |
a19d8eb0 | 14255 | |
0a9ef439 RH |
14256 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
14257 | p = fragp->fr_literal + fragp->fr_fix; | |
14258 | ||
14259 | if (bytes & 1) | |
14260 | { | |
14261 | *p++ = 0; | |
f9419b05 | 14262 | fragp->fr_fix++; |
0a9ef439 RH |
14263 | } |
14264 | ||
14265 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
14266 | fragp->fr_var = 2; | |
a19d8eb0 CP |
14267 | } |
14268 | ||
0a9ef439 | 14269 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
14270 | } |
14271 | ||
252b5132 | 14272 | static void |
17a2f251 | 14273 | md_obj_begin (void) |
252b5132 RH |
14274 | { |
14275 | } | |
14276 | ||
14277 | static void | |
17a2f251 | 14278 | md_obj_end (void) |
252b5132 | 14279 | { |
54f4ddb3 | 14280 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 14281 | if (cur_proc_ptr) |
9a41af64 | 14282 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
14283 | } |
14284 | ||
14285 | static long | |
17a2f251 | 14286 | get_number (void) |
252b5132 RH |
14287 | { |
14288 | int negative = 0; | |
14289 | long val = 0; | |
14290 | ||
14291 | if (*input_line_pointer == '-') | |
14292 | { | |
14293 | ++input_line_pointer; | |
14294 | negative = 1; | |
14295 | } | |
3882b010 | 14296 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 14297 | as_bad (_("expected simple number")); |
252b5132 RH |
14298 | if (input_line_pointer[0] == '0') |
14299 | { | |
14300 | if (input_line_pointer[1] == 'x') | |
14301 | { | |
14302 | input_line_pointer += 2; | |
3882b010 | 14303 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
14304 | { |
14305 | val <<= 4; | |
14306 | val |= hex_value (*input_line_pointer++); | |
14307 | } | |
14308 | return negative ? -val : val; | |
14309 | } | |
14310 | else | |
14311 | { | |
14312 | ++input_line_pointer; | |
3882b010 | 14313 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14314 | { |
14315 | val <<= 3; | |
14316 | val |= *input_line_pointer++ - '0'; | |
14317 | } | |
14318 | return negative ? -val : val; | |
14319 | } | |
14320 | } | |
3882b010 | 14321 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14322 | { |
14323 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
14324 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 14325 | as_warn (_("invalid number")); |
252b5132 RH |
14326 | return -1; |
14327 | } | |
3882b010 | 14328 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14329 | { |
14330 | val *= 10; | |
14331 | val += *input_line_pointer++ - '0'; | |
14332 | } | |
14333 | return negative ? -val : val; | |
14334 | } | |
14335 | ||
14336 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
14337 | is an initial number which is the ECOFF file index. In the non-ECOFF |
14338 | case .file implies DWARF-2. */ | |
14339 | ||
14340 | static void | |
17a2f251 | 14341 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 14342 | { |
ecb4347a DJ |
14343 | static int first_file_directive = 0; |
14344 | ||
c5dd6aab DJ |
14345 | if (ECOFF_DEBUGGING) |
14346 | { | |
14347 | get_number (); | |
14348 | s_app_file (0); | |
14349 | } | |
14350 | else | |
ecb4347a DJ |
14351 | { |
14352 | char *filename; | |
14353 | ||
14354 | filename = dwarf2_directive_file (0); | |
14355 | ||
14356 | /* Versions of GCC up to 3.1 start files with a ".file" | |
14357 | directive even for stabs output. Make sure that this | |
14358 | ".file" is handled. Note that you need a version of GCC | |
14359 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
14360 | if (filename != NULL && ! first_file_directive) | |
14361 | { | |
14362 | (void) new_logical_line (filename, -1); | |
c04f5787 | 14363 | s_app_file_string (filename, 0); |
ecb4347a DJ |
14364 | } |
14365 | first_file_directive = 1; | |
14366 | } | |
c5dd6aab DJ |
14367 | } |
14368 | ||
14369 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
14370 | |
14371 | static void | |
17a2f251 | 14372 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 14373 | { |
c5dd6aab DJ |
14374 | if (!ECOFF_DEBUGGING) |
14375 | dwarf2_directive_loc (0); | |
252b5132 RH |
14376 | } |
14377 | ||
252b5132 RH |
14378 | /* The .end directive. */ |
14379 | ||
14380 | static void | |
17a2f251 | 14381 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
14382 | { |
14383 | symbolS *p; | |
252b5132 | 14384 | |
7a621144 DJ |
14385 | /* Following functions need their own .frame and .cprestore directives. */ |
14386 | mips_frame_reg_valid = 0; | |
14387 | mips_cprestore_valid = 0; | |
14388 | ||
252b5132 RH |
14389 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
14390 | { | |
14391 | p = get_symbol (); | |
14392 | demand_empty_rest_of_line (); | |
14393 | } | |
14394 | else | |
14395 | p = NULL; | |
14396 | ||
14949570 | 14397 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14398 | as_warn (_(".end not in text section")); |
14399 | ||
14400 | if (!cur_proc_ptr) | |
14401 | { | |
14402 | as_warn (_(".end directive without a preceding .ent directive.")); | |
14403 | demand_empty_rest_of_line (); | |
14404 | return; | |
14405 | } | |
14406 | ||
14407 | if (p != NULL) | |
14408 | { | |
14409 | assert (S_GET_NAME (p)); | |
9b2f1d35 | 14410 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 14411 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
14412 | |
14413 | if (debug_type == DEBUG_STABS) | |
14414 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
14415 | S_GET_NAME (p)); | |
252b5132 RH |
14416 | } |
14417 | else | |
14418 | as_warn (_(".end directive missing or unknown symbol")); | |
14419 | ||
2132e3a3 | 14420 | #ifdef OBJ_ELF |
9b2f1d35 EC |
14421 | /* Create an expression to calculate the size of the function. */ |
14422 | if (p && cur_proc_ptr) | |
14423 | { | |
14424 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
14425 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
14426 | ||
14427 | obj->size = exp; | |
14428 | exp->X_op = O_subtract; | |
14429 | exp->X_add_symbol = symbol_temp_new_now (); | |
14430 | exp->X_op_symbol = p; | |
14431 | exp->X_add_number = 0; | |
14432 | ||
14433 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
14434 | } | |
14435 | ||
ecb4347a | 14436 | /* Generate a .pdr section. */ |
f43abd2b | 14437 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
14438 | { |
14439 | segT saved_seg = now_seg; | |
14440 | subsegT saved_subseg = now_subseg; | |
14441 | valueT dot; | |
14442 | expressionS exp; | |
14443 | char *fragp; | |
252b5132 | 14444 | |
ecb4347a | 14445 | dot = frag_now_fix (); |
252b5132 RH |
14446 | |
14447 | #ifdef md_flush_pending_output | |
ecb4347a | 14448 | md_flush_pending_output (); |
252b5132 RH |
14449 | #endif |
14450 | ||
ecb4347a DJ |
14451 | assert (pdr_seg); |
14452 | subseg_set (pdr_seg, 0); | |
252b5132 | 14453 | |
ecb4347a DJ |
14454 | /* Write the symbol. */ |
14455 | exp.X_op = O_symbol; | |
14456 | exp.X_add_symbol = p; | |
14457 | exp.X_add_number = 0; | |
14458 | emit_expr (&exp, 4); | |
252b5132 | 14459 | |
ecb4347a | 14460 | fragp = frag_more (7 * 4); |
252b5132 | 14461 | |
17a2f251 TS |
14462 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
14463 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
14464 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
14465 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
14466 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
14467 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
14468 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 14469 | |
ecb4347a DJ |
14470 | subseg_set (saved_seg, saved_subseg); |
14471 | } | |
14472 | #endif /* OBJ_ELF */ | |
252b5132 RH |
14473 | |
14474 | cur_proc_ptr = NULL; | |
14475 | } | |
14476 | ||
14477 | /* The .aent and .ent directives. */ | |
14478 | ||
14479 | static void | |
17a2f251 | 14480 | s_mips_ent (int aent) |
252b5132 | 14481 | { |
252b5132 | 14482 | symbolS *symbolP; |
252b5132 RH |
14483 | |
14484 | symbolP = get_symbol (); | |
14485 | if (*input_line_pointer == ',') | |
f9419b05 | 14486 | ++input_line_pointer; |
252b5132 | 14487 | SKIP_WHITESPACE (); |
3882b010 | 14488 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 14489 | || *input_line_pointer == '-') |
874e8986 | 14490 | get_number (); |
252b5132 | 14491 | |
14949570 | 14492 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14493 | as_warn (_(".ent or .aent not in text section.")); |
14494 | ||
14495 | if (!aent && cur_proc_ptr) | |
9a41af64 | 14496 | as_warn (_("missing .end")); |
252b5132 RH |
14497 | |
14498 | if (!aent) | |
14499 | { | |
7a621144 DJ |
14500 | /* This function needs its own .frame and .cprestore directives. */ |
14501 | mips_frame_reg_valid = 0; | |
14502 | mips_cprestore_valid = 0; | |
14503 | ||
252b5132 RH |
14504 | cur_proc_ptr = &cur_proc; |
14505 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
14506 | ||
9b2f1d35 | 14507 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 14508 | |
49309057 | 14509 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 14510 | |
f9419b05 | 14511 | ++numprocs; |
ecb4347a DJ |
14512 | |
14513 | if (debug_type == DEBUG_STABS) | |
14514 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
14515 | S_GET_NAME (symbolP)); | |
252b5132 RH |
14516 | } |
14517 | ||
14518 | demand_empty_rest_of_line (); | |
14519 | } | |
14520 | ||
14521 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 14522 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 14523 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 14524 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
14525 | symbol table (in the mdebug section). */ |
14526 | ||
14527 | static void | |
17a2f251 | 14528 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 14529 | { |
ecb4347a | 14530 | #ifdef OBJ_ELF |
f43abd2b | 14531 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
14532 | { |
14533 | long val; | |
252b5132 | 14534 | |
ecb4347a DJ |
14535 | if (cur_proc_ptr == (procS *) NULL) |
14536 | { | |
14537 | as_warn (_(".frame outside of .ent")); | |
14538 | demand_empty_rest_of_line (); | |
14539 | return; | |
14540 | } | |
252b5132 | 14541 | |
ecb4347a DJ |
14542 | cur_proc_ptr->frame_reg = tc_get_register (1); |
14543 | ||
14544 | SKIP_WHITESPACE (); | |
14545 | if (*input_line_pointer++ != ',' | |
14546 | || get_absolute_expression_and_terminator (&val) != ',') | |
14547 | { | |
14548 | as_warn (_("Bad .frame directive")); | |
14549 | --input_line_pointer; | |
14550 | demand_empty_rest_of_line (); | |
14551 | return; | |
14552 | } | |
252b5132 | 14553 | |
ecb4347a DJ |
14554 | cur_proc_ptr->frame_offset = val; |
14555 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 14556 | |
252b5132 | 14557 | demand_empty_rest_of_line (); |
252b5132 | 14558 | } |
ecb4347a DJ |
14559 | else |
14560 | #endif /* OBJ_ELF */ | |
14561 | s_ignore (ignore); | |
252b5132 RH |
14562 | } |
14563 | ||
bdaaa2e1 KH |
14564 | /* The .fmask and .mask directives. If the mdebug section is present |
14565 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 14566 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 14567 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
14568 | make reference to the ecoff symbol table (in the mdebug section). */ |
14569 | ||
14570 | static void | |
17a2f251 | 14571 | s_mips_mask (int reg_type) |
252b5132 | 14572 | { |
ecb4347a | 14573 | #ifdef OBJ_ELF |
f43abd2b | 14574 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 14575 | { |
ecb4347a | 14576 | long mask, off; |
252b5132 | 14577 | |
ecb4347a DJ |
14578 | if (cur_proc_ptr == (procS *) NULL) |
14579 | { | |
14580 | as_warn (_(".mask/.fmask outside of .ent")); | |
14581 | demand_empty_rest_of_line (); | |
14582 | return; | |
14583 | } | |
252b5132 | 14584 | |
ecb4347a DJ |
14585 | if (get_absolute_expression_and_terminator (&mask) != ',') |
14586 | { | |
14587 | as_warn (_("Bad .mask/.fmask directive")); | |
14588 | --input_line_pointer; | |
14589 | demand_empty_rest_of_line (); | |
14590 | return; | |
14591 | } | |
252b5132 | 14592 | |
ecb4347a DJ |
14593 | off = get_absolute_expression (); |
14594 | ||
14595 | if (reg_type == 'F') | |
14596 | { | |
14597 | cur_proc_ptr->fpreg_mask = mask; | |
14598 | cur_proc_ptr->fpreg_offset = off; | |
14599 | } | |
14600 | else | |
14601 | { | |
14602 | cur_proc_ptr->reg_mask = mask; | |
14603 | cur_proc_ptr->reg_offset = off; | |
14604 | } | |
14605 | ||
14606 | demand_empty_rest_of_line (); | |
252b5132 RH |
14607 | } |
14608 | else | |
ecb4347a DJ |
14609 | #endif /* OBJ_ELF */ |
14610 | s_ignore (reg_type); | |
252b5132 RH |
14611 | } |
14612 | ||
316f5878 RS |
14613 | /* A table describing all the processors gas knows about. Names are |
14614 | matched in the order listed. | |
e7af610e | 14615 | |
316f5878 RS |
14616 | To ease comparison, please keep this table in the same order as |
14617 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
14618 | static const struct mips_cpu_info mips_cpu_info_table[] = |
14619 | { | |
316f5878 | 14620 | /* Entries for generic ISAs */ |
ad3fea08 TS |
14621 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
14622 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
14623 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
14624 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
14625 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
14626 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
14627 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14628 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
14629 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
14630 | |
14631 | /* MIPS I */ | |
ad3fea08 TS |
14632 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
14633 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
14634 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
14635 | |
14636 | /* MIPS II */ | |
ad3fea08 | 14637 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
14638 | |
14639 | /* MIPS III */ | |
ad3fea08 TS |
14640 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
14641 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
14642 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
14643 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
14644 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
14645 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
14646 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
14647 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
14648 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
14649 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
14650 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
14651 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
316f5878 RS |
14652 | |
14653 | /* MIPS IV */ | |
ad3fea08 TS |
14654 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
14655 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
14656 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
14657 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
14658 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
14659 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
14660 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
14661 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
14662 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
14663 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
14664 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
14665 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
14666 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
14667 | |
14668 | /* MIPS 32 */ | |
ad3fea08 TS |
14669 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
14670 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
14671 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
14672 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
14673 | ||
14674 | /* MIPS 32 Release 2 */ | |
14675 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14676 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14677 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14678 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14679 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14680 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 TS |
14681 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
14682 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14683 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 14684 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 TS |
14685 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
14686 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 14687 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 14688 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
14689 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
14690 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14691 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
14692 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14693 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
14694 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
14695 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
14696 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
14697 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14698 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
14699 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14700 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
14701 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 14702 | |
316f5878 | 14703 | /* MIPS 64 */ |
ad3fea08 TS |
14704 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
14705 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
14706 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 14707 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 TS |
14708 | |
14709 | /* MIPS 64 Release 2 */ | |
e7af610e | 14710 | |
c7a23324 | 14711 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
14712 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
14713 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
14714 | /* Broadcom SB-1A CPU core */ |
14715 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
14716 | ISA_MIPS64, CPU_SB1 }, | |
e7af610e | 14717 | |
316f5878 RS |
14718 | /* End marker */ |
14719 | { NULL, 0, 0, 0 } | |
14720 | }; | |
e7af610e | 14721 | |
84ea6cf2 | 14722 | |
316f5878 RS |
14723 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
14724 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 14725 | |
316f5878 | 14726 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 14727 | |
b34976b6 | 14728 | static bfd_boolean |
17a2f251 | 14729 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14730 | { |
14731 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
14732 | given++, canonical++; | |
14733 | ||
14734 | return ((*given == 0 && *canonical == 0) | |
14735 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
14736 | } | |
14737 | ||
14738 | ||
14739 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
14740 | CPU name. We've traditionally allowed a lot of variation here. | |
14741 | ||
14742 | Note: this function is shared between GCC and GAS. */ | |
14743 | ||
b34976b6 | 14744 | static bfd_boolean |
17a2f251 | 14745 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14746 | { |
14747 | /* First see if the name matches exactly, or with a final "000" | |
14748 | turned into "k". */ | |
14749 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 14750 | return TRUE; |
316f5878 RS |
14751 | |
14752 | /* If not, try comparing based on numerical designation alone. | |
14753 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
14754 | if (TOLOWER (*given) == 'r') | |
14755 | given++; | |
14756 | if (!ISDIGIT (*given)) | |
b34976b6 | 14757 | return FALSE; |
316f5878 RS |
14758 | |
14759 | /* Skip over some well-known prefixes in the canonical name, | |
14760 | hoping to find a number there too. */ | |
14761 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
14762 | canonical += 2; | |
14763 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
14764 | canonical += 2; | |
14765 | else if (TOLOWER (canonical[0]) == 'r') | |
14766 | canonical += 1; | |
14767 | ||
14768 | return mips_strict_matching_cpu_name_p (canonical, given); | |
14769 | } | |
14770 | ||
14771 | ||
14772 | /* Parse an option that takes the name of a processor as its argument. | |
14773 | OPTION is the name of the option and CPU_STRING is the argument. | |
14774 | Return the corresponding processor enumeration if the CPU_STRING is | |
14775 | recognized, otherwise report an error and return null. | |
14776 | ||
14777 | A similar function exists in GCC. */ | |
e7af610e NC |
14778 | |
14779 | static const struct mips_cpu_info * | |
17a2f251 | 14780 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 14781 | { |
316f5878 | 14782 | const struct mips_cpu_info *p; |
e7af610e | 14783 | |
316f5878 RS |
14784 | /* 'from-abi' selects the most compatible architecture for the given |
14785 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
14786 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
14787 | version. Look first at the -mgp options, if given, otherwise base | |
14788 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 14789 | |
316f5878 RS |
14790 | Treat NO_ABI like the EABIs. One reason to do this is that the |
14791 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
14792 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
14793 | 'mips64', just as we did in the days before 'from-abi'. */ | |
14794 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
14795 | { | |
14796 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14797 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
14798 | ||
14799 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14800 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
14801 | ||
14802 | if (file_mips_gp32 >= 0) | |
14803 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
14804 | ||
14805 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
14806 | ? ISA_MIPS3 | |
14807 | : ISA_MIPS1); | |
14808 | } | |
14809 | ||
14810 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
14811 | if (strcasecmp (cpu_string, "default") == 0) | |
14812 | return 0; | |
14813 | ||
14814 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
14815 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
14816 | return p; | |
14817 | ||
14818 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
14819 | return 0; | |
e7af610e NC |
14820 | } |
14821 | ||
316f5878 RS |
14822 | /* Return the canonical processor information for ISA (a member of the |
14823 | ISA_MIPS* enumeration). */ | |
14824 | ||
e7af610e | 14825 | static const struct mips_cpu_info * |
17a2f251 | 14826 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
14827 | { |
14828 | int i; | |
14829 | ||
14830 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 14831 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 14832 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
14833 | return (&mips_cpu_info_table[i]); |
14834 | ||
e972090a | 14835 | return NULL; |
e7af610e | 14836 | } |
fef14a42 TS |
14837 | |
14838 | static const struct mips_cpu_info * | |
17a2f251 | 14839 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
14840 | { |
14841 | int i; | |
14842 | ||
14843 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14844 | if (arch == mips_cpu_info_table[i].cpu) | |
14845 | return (&mips_cpu_info_table[i]); | |
14846 | ||
14847 | return NULL; | |
14848 | } | |
316f5878 RS |
14849 | \f |
14850 | static void | |
17a2f251 | 14851 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
14852 | { |
14853 | if (*first_p) | |
14854 | { | |
14855 | fprintf (stream, "%24s", ""); | |
14856 | *col_p = 24; | |
14857 | } | |
14858 | else | |
14859 | { | |
14860 | fprintf (stream, ", "); | |
14861 | *col_p += 2; | |
14862 | } | |
e7af610e | 14863 | |
316f5878 RS |
14864 | if (*col_p + strlen (string) > 72) |
14865 | { | |
14866 | fprintf (stream, "\n%24s", ""); | |
14867 | *col_p = 24; | |
14868 | } | |
14869 | ||
14870 | fprintf (stream, "%s", string); | |
14871 | *col_p += strlen (string); | |
14872 | ||
14873 | *first_p = 0; | |
14874 | } | |
14875 | ||
14876 | void | |
17a2f251 | 14877 | md_show_usage (FILE *stream) |
e7af610e | 14878 | { |
316f5878 RS |
14879 | int column, first; |
14880 | size_t i; | |
14881 | ||
14882 | fprintf (stream, _("\ | |
14883 | MIPS options:\n\ | |
316f5878 RS |
14884 | -EB generate big endian output\n\ |
14885 | -EL generate little endian output\n\ | |
14886 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
14887 | -G NUM allow referencing objects up to NUM bytes\n\ | |
14888 | implicitly with the gp register [default 8]\n")); | |
14889 | fprintf (stream, _("\ | |
14890 | -mips1 generate MIPS ISA I instructions\n\ | |
14891 | -mips2 generate MIPS ISA II instructions\n\ | |
14892 | -mips3 generate MIPS ISA III instructions\n\ | |
14893 | -mips4 generate MIPS ISA IV instructions\n\ | |
14894 | -mips5 generate MIPS ISA V instructions\n\ | |
14895 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 14896 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 14897 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 14898 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
14899 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
14900 | ||
14901 | first = 1; | |
e7af610e NC |
14902 | |
14903 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14904 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14905 | show (stream, "from-abi", &column, &first); | |
14906 | fputc ('\n', stream); | |
e7af610e | 14907 | |
316f5878 RS |
14908 | fprintf (stream, _("\ |
14909 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14910 | -no-mCPU don't generate code specific to CPU.\n\ | |
14911 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14912 | ||
14913 | first = 1; | |
14914 | ||
14915 | show (stream, "3900", &column, &first); | |
14916 | show (stream, "4010", &column, &first); | |
14917 | show (stream, "4100", &column, &first); | |
14918 | show (stream, "4650", &column, &first); | |
14919 | fputc ('\n', stream); | |
14920 | ||
14921 | fprintf (stream, _("\ | |
14922 | -mips16 generate mips16 instructions\n\ | |
14923 | -no-mips16 do not generate mips16 instructions\n")); | |
14924 | fprintf (stream, _("\ | |
e16bfa71 TS |
14925 | -msmartmips generate smartmips instructions\n\ |
14926 | -mno-smartmips do not generate smartmips instructions\n")); | |
14927 | fprintf (stream, _("\ | |
74cd071d CF |
14928 | -mdsp generate DSP instructions\n\ |
14929 | -mno-dsp do not generate DSP instructions\n")); | |
14930 | fprintf (stream, _("\ | |
8b082fb1 TS |
14931 | -mdspr2 generate DSP R2 instructions\n\ |
14932 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
14933 | fprintf (stream, _("\ | |
ef2e4d86 CF |
14934 | -mmt generate MT instructions\n\ |
14935 | -mno-mt do not generate MT instructions\n")); | |
14936 | fprintf (stream, _("\ | |
d766e8ec | 14937 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 14938 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
316f5878 RS |
14939 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
14940 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 14941 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
14942 | -O0 remove unneeded NOPs, do not swap branches\n\ |
14943 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
14944 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
14945 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14946 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14947 | #ifdef OBJ_ELF | |
14948 | fprintf (stream, _("\ | |
14949 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14950 | -non_shared do not generate position independent code\n\ | |
14951 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 14952 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 14953 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 14954 | position dependent (non shared) code\n\ |
316f5878 RS |
14955 | -mabi=ABI create ABI conformant object file for:\n")); |
14956 | ||
14957 | first = 1; | |
14958 | ||
14959 | show (stream, "32", &column, &first); | |
14960 | show (stream, "o64", &column, &first); | |
14961 | show (stream, "n32", &column, &first); | |
14962 | show (stream, "64", &column, &first); | |
14963 | show (stream, "eabi", &column, &first); | |
14964 | ||
14965 | fputc ('\n', stream); | |
14966 | ||
14967 | fprintf (stream, _("\ | |
14968 | -32 create o32 ABI object file (default)\n\ | |
14969 | -n32 create n32 ABI object file\n\ | |
14970 | -64 create 64 ABI object file\n")); | |
14971 | #endif | |
e7af610e | 14972 | } |
14e777e0 KB |
14973 | |
14974 | enum dwarf2_format | |
17a2f251 | 14975 | mips_dwarf2_format (void) |
14e777e0 KB |
14976 | { |
14977 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14978 | { |
14979 | #ifdef TE_IRIX | |
14980 | return dwarf2_format_64bit_irix; | |
14981 | #else | |
14982 | return dwarf2_format_64bit; | |
14983 | #endif | |
14984 | } | |
14e777e0 KB |
14985 | else |
14986 | return dwarf2_format_32bit; | |
14987 | } | |
73369e65 EC |
14988 | |
14989 | int | |
14990 | mips_dwarf2_addr_size (void) | |
14991 | { | |
14992 | if (mips_abi == N64_ABI) | |
14993 | return 8; | |
73369e65 EC |
14994 | else |
14995 | return 4; | |
14996 | } | |
5862107c EC |
14997 | |
14998 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
14999 | void | |
15000 | mips_cfi_frame_initial_instructions (void) | |
15001 | { | |
15002 | cfi_add_CFA_def_cfa_register (SP); | |
15003 | } | |
15004 | ||
707bfff6 TS |
15005 | int |
15006 | tc_mips_regname_to_dw2regnum (char *regname) | |
15007 | { | |
15008 | unsigned int regnum = -1; | |
15009 | unsigned int reg; | |
15010 | ||
15011 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
15012 | regnum = reg; | |
15013 | ||
15014 | return regnum; | |
15015 | } |