Commit | Line | Data |
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3d3c5039 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
fb251650 | 2 | Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc. |
3d3c5039 ILT |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
fb251650 ILT |
21 | along with GAS; see the file COPYING. If not, write to the Free |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
3d3c5039 ILT |
24 | |
25 | #include "as.h" | |
8358c818 | 26 | #include "config.h" |
9da4c5d1 | 27 | #include "subsegs.h" |
3d3c5039 ILT |
28 | |
29 | #include <ctype.h> | |
30 | ||
1dc1e798 | 31 | #ifdef USE_STDARG |
3d3c5039 | 32 | #include <stdarg.h> |
1dc1e798 KR |
33 | #endif |
34 | #ifdef USE_VARARGS | |
3d3c5039 | 35 | #include <varargs.h> |
1dc1e798 | 36 | #endif |
3d3c5039 | 37 | |
918692a5 | 38 | #include "opcode/mips.h" |
3d3c5039 | 39 | |
739708fa KR |
40 | #ifdef OBJ_MAYBE_ELF |
41 | /* Clean up namespace so we can include obj-elf.h too. */ | |
42 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
43 | #undef OBJ_PROCESS_STAB | |
44 | #undef OUTPUT_FLAVOR | |
45 | #undef S_GET_ALIGN | |
46 | #undef S_GET_SIZE | |
47 | #undef S_SET_ALIGN | |
48 | #undef S_SET_SIZE | |
49 | #undef TARGET_SYMBOL_FIELDS | |
50 | #undef obj_frob_file | |
cc5703cd | 51 | #undef obj_frob_file_after_relocs |
739708fa KR |
52 | #undef obj_frob_symbol |
53 | #undef obj_pop_insert | |
54 | #undef obj_sec_sym_ok_for_reloc | |
55 | ||
56 | #include "obj-elf.h" | |
57 | /* Fix any of them that we actually care about. */ | |
58 | #undef OUTPUT_FLAVOR | |
59 | #define OUTPUT_FLAVOR mips_output_flavor() | |
60 | #endif | |
61 | ||
62 | #if defined (OBJ_ELF) | |
f2a663d3 | 63 | #include "elf/mips.h" |
1dc1e798 | 64 | #endif |
f2a663d3 | 65 | |
739708fa | 66 | #ifndef ECOFF_DEBUGGING |
c625fc23 | 67 | #define NO_ECOFF_DEBUGGING |
739708fa KR |
68 | #define ECOFF_DEBUGGING 0 |
69 | #endif | |
70 | ||
22ba90ce ILT |
71 | #include "ecoff.h" |
72 | ||
a8aed9dd | 73 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 74 | static char *mips_regmask_frag; |
a8aed9dd | 75 | #endif |
f2a663d3 | 76 | |
3d3c5039 | 77 | #define AT 1 |
cc5703cd | 78 | #define TREG 24 |
9226253a | 79 | #define PIC_CALL_REG 25 |
b2b8c24e ILT |
80 | #define KT0 26 |
81 | #define KT1 27 | |
670a50eb | 82 | #define GP 28 |
9226253a ILT |
83 | #define SP 29 |
84 | #define FP 30 | |
3d3c5039 ILT |
85 | #define RA 31 |
86 | ||
cc5703cd ILT |
87 | #define ILLEGAL_REG (32) |
88 | ||
1dc1e798 | 89 | extern int target_big_endian; |
88225433 | 90 | |
7f9880e5 ILT |
91 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the |
92 | 32 bit ABI. This has no meaning for ECOFF. */ | |
93 | static int mips_64; | |
94 | ||
04cb3372 | 95 | /* The default target format to use. */ |
1dc1e798 KR |
96 | const char * |
97 | mips_target_format () | |
98 | { | |
99 | switch (OUTPUT_FLAVOR) | |
100 | { | |
101 | case bfd_target_aout_flavour: | |
102 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
103 | case bfd_target_ecoff_flavour: | |
104 | return target_big_endian ? "ecoff-bigmips" : "ecoff-littlemips"; | |
105 | case bfd_target_elf_flavour: | |
7f9880e5 ILT |
106 | return (target_big_endian |
107 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
108 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
1dc1e798 KR |
109 | default: |
110 | abort (); | |
111 | } | |
112 | } | |
04cb3372 | 113 | |
d2c71068 | 114 | /* The name of the readonly data section. */ |
1dc1e798 KR |
115 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
116 | ? ".data" \ | |
117 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
118 | ? ".rdata" \ | |
119 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ | |
120 | ? ".rodata" \ | |
121 | : (abort (), "")) | |
d2c71068 | 122 | |
1aa6938e ILT |
123 | /* These variables are filled in with the masks of registers used. |
124 | The object format code reads them and puts them in the appropriate | |
125 | place. */ | |
126 | unsigned long mips_gprmask; | |
127 | unsigned long mips_cprmask[4]; | |
128 | ||
1051c97f ILT |
129 | /* MIPS ISA (Instruction Set Architecture) level (may be changed |
130 | temporarily using .set mipsN). */ | |
8358c818 ILT |
131 | static int mips_isa = -1; |
132 | ||
1051c97f ILT |
133 | /* MIPS ISA we are using for this output file. */ |
134 | static int file_mips_isa; | |
135 | ||
cc5703cd ILT |
136 | /* Whether we are assembling for the mips16 processor. */ |
137 | static int mips16 = -1; | |
138 | ||
8c63448a | 139 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
4bb0cc41 | 140 | static int mips_cpu = -1; |
8c63448a | 141 | |
b2b8c24e ILT |
142 | /* Whether the 4650 instructions (mad/madu) are permitted. */ |
143 | static int mips_4650 = -1; | |
144 | ||
e532b44c ILT |
145 | /* Whether the 4010 instructions are permitted. */ |
146 | static int mips_4010 = -1; | |
147 | ||
c625fc23 JSC |
148 | /* Whether the 4100 MADD16 and DMADD16 are permitted. */ |
149 | static int mips_4100 = -1; | |
150 | ||
e532b44c ILT |
151 | /* Whether the processor uses hardware interlocks, and thus does not |
152 | require nops to be inserted. */ | |
153 | static int interlocks = -1; | |
154 | ||
344a8d61 JSC |
155 | /* As with "interlocks" this is used by hardware that has FP |
156 | (co-processor) interlocks. */ | |
157 | static int cop_interlocks = -1; | |
158 | ||
d9aba805 ILT |
159 | /* MIPS PIC level. */ |
160 | ||
161 | enum mips_pic_level | |
162 | { | |
163 | /* Do not generate PIC code. */ | |
164 | NO_PIC, | |
165 | ||
166 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
167 | not sure what it is supposed to do. */ | |
168 | IRIX4_PIC, | |
169 | ||
170 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
171 | SVR4_PIC, | |
172 | ||
173 | /* Generate PIC code without using a global offset table: the data | |
174 | segment has a maximum size of 64K, all data references are off | |
175 | the $gp register, and all text references are PC relative. This | |
176 | is used on some embedded systems. */ | |
177 | EMBEDDED_PIC | |
178 | }; | |
179 | ||
180 | static enum mips_pic_level mips_pic; | |
9226253a | 181 | |
fb251650 ILT |
182 | /* 1 if we should generate 32 bit offsets from the GP register in |
183 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
184 | static int mips_big_got; | |
185 | ||
8ea7f4e8 ILT |
186 | /* 1 if trap instructions should used for overflow rather than break |
187 | instructions. */ | |
188 | static int mips_trap; | |
189 | ||
cc5703cd ILT |
190 | /* 1 if we should autoextend mips16 instructions. */ |
191 | static int mips16_autoextend = 1; | |
192 | ||
3d3c5039 ILT |
193 | static int mips_warn_about_macros; |
194 | static int mips_noreorder; | |
0dd2d296 | 195 | static int mips_any_noreorder; |
3d3c5039 ILT |
196 | static int mips_nomove; |
197 | static int mips_noat; | |
198 | static int mips_nobopt; | |
199 | ||
670a50eb ILT |
200 | /* The size of the small data section. */ |
201 | static int g_switch_value = 8; | |
42562568 ILT |
202 | /* Whether the -G option was used. */ |
203 | static int g_switch_seen = 0; | |
670a50eb | 204 | |
3d3c5039 ILT |
205 | #define N_RMASK 0xc4 |
206 | #define N_VFP 0xd4 | |
207 | ||
d8a1c247 KR |
208 | /* If we can determine in advance that GP optimization won't be |
209 | possible, we can skip the relaxation stuff that tries to produce | |
210 | GP-relative references. This makes delay slot optimization work | |
211 | better. | |
212 | ||
213 | This function can only provide a guess, but it seems to work for | |
214 | gcc output. If it guesses wrong, the only loss should be in | |
215 | efficiency; it shouldn't introduce any bugs. | |
216 | ||
217 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
218 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
219 | static int nopic_need_relax PARAMS ((symbolS *)); | |
220 | ||
3d3c5039 ILT |
221 | /* handle of the OPCODE hash table */ |
222 | static struct hash_control *op_hash = NULL; | |
223 | ||
cc5703cd ILT |
224 | /* The opcode hash table we use for the mips16. */ |
225 | static struct hash_control *mips16_op_hash = NULL; | |
226 | ||
3d3c5039 ILT |
227 | /* This array holds the chars that always start a comment. If the |
228 | pre-processor is disabled, these aren't very useful */ | |
229 | const char comment_chars[] = "#"; | |
230 | ||
231 | /* This array holds the chars that only start a comment at the beginning of | |
232 | a line. If the line seems to have the form '# 123 filename' | |
233 | .line and .file directives will appear in the pre-processed output */ | |
234 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
235 | first line of the input file. This is because the compiler outputs | |
236 | #NO_APP at the beginning of its output. */ | |
237 | /* Also note that C style comments are always supported. */ | |
238 | const char line_comment_chars[] = "#"; | |
239 | ||
240 | /* This array holds machine specific line separator characters. */ | |
241 | const char line_separator_chars[] = ""; | |
242 | ||
243 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
244 | const char EXP_CHARS[] = "eE"; | |
245 | ||
246 | /* Chars that mean this number is a floating point constant */ | |
247 | /* As in 0f12.456 */ | |
248 | /* or 0d1.2345e12 */ | |
249 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
250 | ||
251 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
252 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
253 | but nothing is ideal around here. | |
254 | */ | |
255 | ||
670a50eb | 256 | static char *insn_error; |
3d3c5039 | 257 | |
22ba90ce | 258 | static int byte_order; |
3d3c5039 ILT |
259 | |
260 | static int auto_align = 1; | |
becfe05e ILT |
261 | |
262 | /* Symbol labelling the current insn. */ | |
263 | static symbolS *insn_label; | |
264 | ||
9226253a ILT |
265 | /* When outputting SVR4 PIC code, the assembler needs to know the |
266 | offset in the stack frame from which to restore the $gp register. | |
267 | This is set by the .cprestore pseudo-op, and saved in this | |
268 | variable. */ | |
0dd2d296 ILT |
269 | static offsetT mips_cprestore_offset = -1; |
270 | ||
271 | /* This is the register which holds the stack frame, as set by the | |
272 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
273 | static int mips_frame_reg = SP; | |
9226253a | 274 | |
becfe05e ILT |
275 | /* To output NOP instructions correctly, we need to keep information |
276 | about the previous two instructions. */ | |
277 | ||
0aa07269 ILT |
278 | /* Whether we are optimizing. The default value of 2 means to remove |
279 | unneeded NOPs and swap branch instructions when possible. A value | |
280 | of 1 means to not swap branches. A value of 0 means to always | |
281 | insert NOPs. */ | |
282 | static int mips_optimize = 2; | |
4e95866e | 283 | |
22ba90ce ILT |
284 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
285 | equivalent to seeing no -g option at all. */ | |
286 | static int mips_debug = 0; | |
287 | ||
becfe05e ILT |
288 | /* The previous instruction. */ |
289 | static struct mips_cl_insn prev_insn; | |
290 | ||
291 | /* The instruction before prev_insn. */ | |
292 | static struct mips_cl_insn prev_prev_insn; | |
293 | ||
294 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
295 | point the insn_mo field at this dummy integer. */ | |
296 | static const struct mips_opcode dummy_opcode = { 0 }; | |
297 | ||
298 | /* Non-zero if prev_insn is valid. */ | |
299 | static int prev_insn_valid; | |
300 | ||
301 | /* The frag for the previous instruction. */ | |
302 | static struct frag *prev_insn_frag; | |
303 | ||
304 | /* The offset into prev_insn_frag for the previous instruction. */ | |
305 | static long prev_insn_where; | |
306 | ||
307 | /* The reloc for the previous instruction, if any. */ | |
308 | static fixS *prev_insn_fixp; | |
309 | ||
310 | /* Non-zero if the previous instruction was in a delay slot. */ | |
311 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
312 | |
313 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
314 | static int prev_insn_unreordered; | |
315 | ||
cc5703cd ILT |
316 | /* Non-zero if the previous instruction uses an extend opcode (if |
317 | mips16). */ | |
318 | static int prev_insn_extended; | |
319 | ||
4e95866e ILT |
320 | /* Non-zero if the previous previous instruction was in a .set |
321 | noreorder. */ | |
322 | static int prev_prev_insn_unreordered; | |
867a58b3 ILT |
323 | |
324 | /* For ECOFF and ELF, relocations against symbols are done in two | |
325 | parts, with a HI relocation and a LO relocation. Each relocation | |
326 | has only 16 bits of space to store an addend. This means that in | |
327 | order for the linker to handle carries correctly, it must be able | |
328 | to locate both the HI and the LO relocation. This means that the | |
329 | relocations must appear in order in the relocation table. | |
330 | ||
331 | In order to implement this, we keep track of each unmatched HI | |
332 | relocation. We then sort them so that they immediately precede the | |
333 | corresponding LO relocation. */ | |
334 | ||
335 | struct mips_hi_fixup | |
336 | { | |
337 | /* Next HI fixup. */ | |
338 | struct mips_hi_fixup *next; | |
339 | /* This fixup. */ | |
340 | fixS *fixp; | |
341 | /* The section this fixup is in. */ | |
342 | segT seg; | |
343 | }; | |
344 | ||
345 | /* The list of unmatched HI relocs. */ | |
346 | ||
347 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
cc5703cd ILT |
348 | |
349 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
350 | ||
351 | #define X ILLEGAL_REG | |
352 | static const int mips32_to_16_reg_map[] = | |
353 | { | |
354 | X, X, 2, 3, 4, 5, 6, 7, | |
355 | X, X, X, X, X, X, X, X, | |
356 | 0, 1, X, X, X, X, X, X, | |
357 | X, X, X, X, X, X, X, X | |
358 | }; | |
359 | #undef X | |
360 | ||
361 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
362 | ||
363 | static const int mips16_to_32_reg_map[] = | |
364 | { | |
365 | 16, 17, 2, 3, 4, 5, 6, 7 | |
366 | }; | |
3d3c5039 | 367 | \f |
0dd2d296 ILT |
368 | /* Since the MIPS does not have multiple forms of PC relative |
369 | instructions, we do not have to do relaxing as is done on other | |
370 | platforms. However, we do have to handle GP relative addressing | |
371 | correctly, which turns out to be a similar problem. | |
372 | ||
373 | Every macro that refers to a symbol can occur in (at least) two | |
374 | forms, one with GP relative addressing and one without. For | |
375 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 376 | a macro instruction like this: |
0dd2d296 ILT |
377 | lw $4,i |
378 | If i can be addressed off the GP register (this is true if it is in | |
379 | the .sbss or .sdata section, or if it is known to be smaller than | |
380 | the -G argument) this will generate the following instruction: | |
381 | lw $4,i($gp) | |
382 | This instruction will use a GPREL reloc. If i can not be addressed | |
383 | off the GP register, the following instruction sequence will be used: | |
384 | lui $at,i | |
385 | lw $4,i($at) | |
386 | In this case the first instruction will have a HI16 reloc, and the | |
387 | second reloc will have a LO16 reloc. Both relocs will be against | |
388 | the symbol i. | |
389 | ||
390 | The issue here is that we may not know whether i is GP addressable | |
391 | until after we see the instruction that uses it. Therefore, we | |
392 | want to be able to choose the final instruction sequence only at | |
393 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 394 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
395 | end of assembly. |
396 | ||
397 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
398 | addressing in quite the same way, but the issue still arises as |
399 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
400 | |
401 | We handle these issues by actually generating both possible | |
402 | instruction sequences. The longer one is put in a frag_var with | |
403 | type rs_machine_dependent. We encode what to do with the frag in | |
404 | the subtype field. We encode (1) the number of existing bytes to | |
405 | replace, (2) the number of new bytes to use, (3) the offset from | |
406 | the start of the existing bytes to the first reloc we must generate | |
407 | (that is, the offset is applied from the start of the existing | |
408 | bytes after they are replaced by the new bytes, if any), (4) the | |
409 | offset from the start of the existing bytes to the second reloc, | |
410 | (5) whether a third reloc is needed (the third reloc is always four | |
411 | bytes after the second reloc), and (6) whether to warn if this | |
412 | variant is used (this is sometimes needed if .set nomacro or .set | |
413 | noat is in effect). All these numbers are reasonably small. | |
414 | ||
415 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
416 | ensure that delay slots are handled correctly. Fortunately, there |
417 | are a limited number of cases. When the second instruction | |
418 | sequence is generated, append_insn is directed to maintain the | |
419 | existing delay slot information, so it continues to apply to any | |
420 | code after the second instruction sequence. This means that the | |
421 | second instruction sequence must not impose any requirements not | |
422 | required by the first instruction sequence. | |
0dd2d296 ILT |
423 | |
424 | These variant frags are then handled in functions called by the | |
425 | machine independent code. md_estimate_size_before_relax returns | |
426 | the final size of the frag. md_convert_frag sets up the final form | |
427 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
428 | one if needed. */ | |
429 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
430 | ((relax_substateT) \ | |
cc5703cd | 431 | (((old) << 23) \ |
0dd2d296 ILT |
432 | | ((new) << 16) \ |
433 | | (((reloc1) + 64) << 9) \ | |
434 | | (((reloc2) + 64) << 2) \ | |
435 | | ((reloc3) ? (1 << 1) : 0) \ | |
436 | | ((warn) ? 1 : 0))) | |
cc5703cd ILT |
437 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) |
438 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
483971bd KR |
439 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) |
440 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
0dd2d296 ILT |
441 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
442 | #define RELAX_WARN(i) ((i) & 1) | |
cc5703cd ILT |
443 | |
444 | /* For mips16 code, we use an entirely different form of relaxation. | |
445 | mips16 supports two versions of most instructions which take | |
446 | immediate values: a small one which takes some small value, and a | |
447 | larger one which takes a 16 bit value. Since branches also follow | |
448 | this pattern, relaxing these values is required. | |
449 | ||
450 | We can assemble both mips16 and normal MIPS code in a single | |
451 | object. Therefore, we need to support this type of relaxation at | |
452 | the same time that we support the relaxation described above. We | |
453 | use the high bit of the subtype field to distinguish these cases. | |
454 | ||
455 | The information we store for this type of relaxation is simply the | |
456 | argument code found in the opcode file for this relocation. That | |
457 | tells us the size of the value, and how it should be stored. We | |
458 | also store whether the fragment is considered to be extended or | |
459 | not. We also store whether this is known to be a branch to a | |
460 | different section, whether we have tried to relax this frag yet, | |
461 | and whether we have ever extended a PC relative fragment because of | |
462 | a shift count. */ | |
463 | #define RELAX_MIPS16_ENCODE(type) \ | |
464 | (0x80000000 | ((type) & 0xff)) | |
465 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) | |
466 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
467 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x100) != 0) | |
468 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x100) | |
469 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x100) | |
470 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x200) != 0) | |
471 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x200) | |
472 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x200) | |
0dd2d296 | 473 | \f |
3d3c5039 ILT |
474 | /* Prototypes for static functions. */ |
475 | ||
476 | #ifdef __STDC__ | |
477 | #define internalError() \ | |
478 | as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__) | |
479 | #else | |
480 | #define internalError() as_fatal ("MIPS internal Error"); | |
481 | #endif | |
482 | ||
cc5703cd ILT |
483 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
484 | ||
becfe05e | 485 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
cc5703cd | 486 | unsigned int reg, enum mips_regclass class)); |
fb251650 | 487 | static int reg_needs_delay PARAMS ((int)); |
0dd2d296 ILT |
488 | static void append_insn PARAMS ((char *place, |
489 | struct mips_cl_insn * ip, | |
670a50eb | 490 | expressionS * p, |
867a58b3 ILT |
491 | bfd_reloc_code_real_type r, |
492 | boolean)); | |
becfe05e ILT |
493 | static void mips_no_prev_insn PARAMS ((void)); |
494 | static void mips_emit_delays PARAMS ((void)); | |
c625fc23 | 495 | #ifdef USE_STDARG |
0dd2d296 | 496 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
497 | const char *name, const char *fmt, |
498 | ...)); | |
c625fc23 JSC |
499 | #else |
500 | static void macro_build (); | |
501 | #endif | |
cc5703cd ILT |
502 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, |
503 | const char *, const char *, | |
504 | va_list)); | |
0dd2d296 ILT |
505 | static void macro_build_lui PARAMS ((char *place, int *counter, |
506 | expressionS * ep, int regnum)); | |
6e8dda9c | 507 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 508 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 509 | expressionS *)); |
d8a1c247 | 510 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
0dd2d296 | 511 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); |
670a50eb | 512 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
cc5703cd | 513 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
514 | #ifdef LOSING_COMPILER |
515 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
516 | #endif | |
670a50eb | 517 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
cc5703cd ILT |
518 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
519 | static void mips16_immed PARAMS ((int, offsetT, boolean, boolean, boolean, | |
520 | unsigned long *, boolean *, | |
521 | unsigned short *)); | |
670a50eb ILT |
522 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); |
523 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 524 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 525 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 ILT |
526 | static void s_align PARAMS ((int)); |
527 | static void s_change_sec PARAMS ((int)); | |
528 | static void s_cons PARAMS ((int)); | |
3d3c5039 | 529 | static void s_float_cons PARAMS ((int)); |
c1444ec4 | 530 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
531 | static void s_option PARAMS ((int)); |
532 | static void s_mipsset PARAMS ((int)); | |
9226253a ILT |
533 | static void s_abicalls PARAMS ((int)); |
534 | static void s_cpload PARAMS ((int)); | |
535 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
536 | static void s_gpword PARAMS ((int)); |
537 | static void s_cpadd PARAMS ((int)); | |
3d3c5039 ILT |
538 | static void md_obj_begin PARAMS ((void)); |
539 | static void md_obj_end PARAMS ((void)); | |
540 | static long get_number PARAMS ((void)); | |
541 | static void s_ent PARAMS ((int)); | |
542 | static void s_mipsend PARAMS ((int)); | |
543 | static void s_file PARAMS ((int)); | |
cc5703cd | 544 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); |
3d3c5039 ILT |
545 | \f |
546 | /* Pseudo-op table. | |
547 | ||
548 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
549 | should be defined here, but are currently unsupported: .alias, | |
550 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
551 | ||
552 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
553 | specific to the type of debugging information being generated, and | |
554 | should be defined by the object format: .aent, .begin, .bend, | |
555 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
556 | .vreg. | |
557 | ||
558 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
559 | not MIPS CPU specific, but are also not specific to the object file | |
560 | format. This file is probably the best place to define them, but | |
561 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
562 | .struct, .weakext. */ | |
563 | ||
739708fa | 564 | static const pseudo_typeS mips_pseudo_table[] = |
3d3c5039 | 565 | { |
670a50eb ILT |
566 | /* MIPS specific pseudo-ops. */ |
567 | {"option", s_option, 0}, | |
568 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
569 | {"rdata", s_change_sec, 'r'}, |
570 | {"sdata", s_change_sec, 's'}, | |
571 | {"livereg", s_ignore, 0}, | |
739708fa KR |
572 | {"abicalls", s_abicalls, 0}, |
573 | {"cpload", s_cpload, 0}, | |
574 | {"cprestore", s_cprestore, 0}, | |
575 | {"gpword", s_gpword, 0}, | |
576 | {"cpadd", s_cpadd, 0}, | |
3d3c5039 | 577 | |
670a50eb | 578 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 579 | chips. */ |
739708fa | 580 | {"asciiz", stringer, 1}, |
670a50eb ILT |
581 | {"bss", s_change_sec, 'b'}, |
582 | {"err", s_err, 0}, | |
583 | {"half", s_cons, 1}, | |
52aa70b5 | 584 | {"dword", s_cons, 3}, |
3d3c5039 | 585 | |
670a50eb | 586 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 587 | here for one reason or another. */ |
670a50eb ILT |
588 | {"align", s_align, 0}, |
589 | {"byte", s_cons, 0}, | |
590 | {"data", s_change_sec, 'd'}, | |
becfe05e | 591 | {"double", s_float_cons, 'd'}, |
becfe05e | 592 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
593 | {"globl", s_mips_globl, 0}, |
594 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
595 | {"hword", s_cons, 1}, |
596 | {"int", s_cons, 2}, | |
597 | {"long", s_cons, 2}, | |
598 | {"octa", s_cons, 4}, | |
599 | {"quad", s_cons, 3}, | |
600 | {"short", s_cons, 1}, | |
601 | {"single", s_float_cons, 'f'}, | |
670a50eb ILT |
602 | {"text", s_change_sec, 't'}, |
603 | {"word", s_cons, 2}, | |
739708fa KR |
604 | { 0 }, |
605 | }; | |
3d3c5039 | 606 | |
739708fa | 607 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { |
670a50eb | 608 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 609 | However, a.out doesn't support them, so we have versions here. */ |
670a50eb | 610 | {"aent", s_ent, 1}, |
9226253a | 611 | {"bgnb", s_ignore, 0}, |
670a50eb | 612 | {"end", s_mipsend, 0}, |
9226253a | 613 | {"endb", s_ignore, 0}, |
670a50eb ILT |
614 | {"ent", s_ent, 0}, |
615 | {"file", s_file, 0}, | |
616 | {"fmask", s_ignore, 'F'}, | |
617 | {"frame", s_ignore, 0}, | |
618 | {"loc", s_ignore, 0}, | |
619 | {"mask", s_ignore, 'R'}, | |
620 | {"verstamp", s_ignore, 0}, | |
739708fa KR |
621 | { 0 }, |
622 | }; | |
61420a20 | 623 | |
739708fa KR |
624 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
625 | ||
626 | void | |
627 | mips_pop_insert () | |
628 | { | |
629 | pop_insert (mips_pseudo_table); | |
630 | if (! ECOFF_DEBUGGING) | |
631 | pop_insert (mips_nonecoff_pseudo_table); | |
739708fa | 632 | } |
3d3c5039 | 633 | \f |
3d3c5039 ILT |
634 | static char *expr_end; |
635 | ||
867a58b3 ILT |
636 | /* Expressions which appear in instructions. These are set by |
637 | mips_ip. */ | |
638 | ||
3d3c5039 ILT |
639 | static expressionS imm_expr; |
640 | static expressionS offset_expr; | |
867a58b3 ILT |
641 | |
642 | /* Relocs associated with imm_expr and offset_expr. */ | |
643 | ||
3d3c5039 ILT |
644 | static bfd_reloc_code_real_type imm_reloc; |
645 | static bfd_reloc_code_real_type offset_reloc; | |
646 | ||
867a58b3 ILT |
647 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ |
648 | ||
649 | static boolean imm_unmatched_hi; | |
650 | ||
3d3c5039 ILT |
651 | /* |
652 | * This function is called once, at assembler startup time. It should | |
653 | * set up all the tables, etc. that the MD part of the assembler will need. | |
654 | */ | |
655 | void | |
670a50eb | 656 | md_begin () |
3d3c5039 | 657 | { |
0dd2d296 | 658 | boolean ok = false; |
604633ae | 659 | register const char *retval = NULL; |
670a50eb | 660 | register unsigned int i = 0; |
3d3c5039 | 661 | |
8358c818 ILT |
662 | if (mips_isa == -1) |
663 | { | |
8c63448a ILT |
664 | const char *cpu; |
665 | char *a = NULL; | |
666 | ||
667 | cpu = TARGET_CPU; | |
668 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
669 | { | |
670 | a = xmalloc (sizeof TARGET_CPU); | |
671 | strcpy (a, TARGET_CPU); | |
672 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
673 | cpu = a; | |
674 | } | |
675 | ||
676 | if (strcmp (cpu, "mips") == 0) | |
677 | { | |
678 | mips_isa = 1; | |
4bb0cc41 ILT |
679 | if (mips_cpu == -1) |
680 | mips_cpu = 3000; | |
8c63448a ILT |
681 | } |
682 | else if (strcmp (cpu, "r6000") == 0 | |
683 | || strcmp (cpu, "mips2") == 0) | |
684 | { | |
685 | mips_isa = 2; | |
4bb0cc41 ILT |
686 | if (mips_cpu == -1) |
687 | mips_cpu = 6000; | |
8c63448a ILT |
688 | } |
689 | else if (strcmp (cpu, "mips64") == 0 | |
690 | || strcmp (cpu, "r4000") == 0 | |
691 | || strcmp (cpu, "mips3") == 0) | |
692 | { | |
693 | mips_isa = 3; | |
4bb0cc41 ILT |
694 | if (mips_cpu == -1) |
695 | mips_cpu = 4000; | |
8c63448a ILT |
696 | } |
697 | else if (strcmp (cpu, "r4400") == 0) | |
698 | { | |
699 | mips_isa = 3; | |
4bb0cc41 ILT |
700 | if (mips_cpu == -1) |
701 | mips_cpu = 4400; | |
8c63448a ILT |
702 | } |
703 | else if (strcmp (cpu, "mips64orion") == 0 | |
704 | || strcmp (cpu, "r4600") == 0) | |
705 | { | |
706 | mips_isa = 3; | |
4bb0cc41 ILT |
707 | if (mips_cpu == -1) |
708 | mips_cpu = 4600; | |
8c63448a | 709 | } |
b2b8c24e ILT |
710 | else if (strcmp (cpu, "r4650") == 0) |
711 | { | |
712 | mips_isa = 3; | |
713 | if (mips_cpu == -1) | |
714 | mips_cpu = 4650; | |
715 | if (mips_4650 == -1) | |
716 | mips_4650 = 1; | |
717 | } | |
c625fc23 JSC |
718 | else if (strcmp (cpu, "mips64vr4300") == 0) |
719 | { | |
720 | mips_isa = 3; | |
721 | if (mips_cpu == -1) | |
722 | mips_cpu = 4300; | |
723 | } | |
724 | else if (strcmp (cpu, "mips64vr4100") == 0) | |
725 | { | |
726 | mips_isa = 3; | |
727 | if (mips_cpu == -1) | |
728 | mips_cpu = 4100; | |
729 | if (mips_4100 == -1) | |
730 | mips_4100 = 1; | |
731 | } | |
e532b44c ILT |
732 | else if (strcmp (cpu, "r4010") == 0) |
733 | { | |
734 | mips_isa = 2; | |
735 | if (mips_cpu == -1) | |
736 | mips_cpu = 4010; | |
737 | if (mips_4010 == -1) | |
738 | mips_4010 = 1; | |
739 | } | |
517078c1 ILT |
740 | else if (strcmp (cpu, "r5000") == 0 |
741 | || strcmp (cpu, "mips64vr5000") == 0) | |
742 | { | |
743 | mips_isa = 4; | |
744 | if (mips_cpu == -1) | |
745 | mips_cpu = 5000; | |
746 | } | |
d8a1c247 KR |
747 | else if (strcmp (cpu, "r8000") == 0 |
748 | || strcmp (cpu, "mips4") == 0) | |
749 | { | |
750 | mips_isa = 4; | |
751 | if (mips_cpu == -1) | |
752 | mips_cpu = 8000; | |
753 | } | |
754 | else if (strcmp (cpu, "r10000") == 0) | |
755 | { | |
756 | mips_isa = 4; | |
757 | if (mips_cpu == -1) | |
758 | mips_cpu = 10000; | |
759 | } | |
cc5703cd ILT |
760 | else if (strcmp (cpu, "mips16") == 0) |
761 | { | |
762 | mips_isa = 3; | |
763 | if (mips_cpu == -1) | |
764 | mips_cpu = 0; /* FIXME */ | |
765 | } | |
8358c818 | 766 | else |
8c63448a ILT |
767 | { |
768 | mips_isa = 1; | |
4bb0cc41 ILT |
769 | if (mips_cpu == -1) |
770 | mips_cpu = 3000; | |
8c63448a ILT |
771 | } |
772 | ||
773 | if (a != NULL) | |
774 | free (a); | |
8358c818 ILT |
775 | } |
776 | ||
cc5703cd ILT |
777 | if (mips16 < 0) |
778 | { | |
779 | if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) | |
780 | mips16 = 1; | |
781 | else | |
782 | mips16 = 0; | |
783 | } | |
784 | ||
b2b8c24e ILT |
785 | if (mips_4650 < 0) |
786 | mips_4650 = 0; | |
787 | ||
e532b44c ILT |
788 | if (mips_4010 < 0) |
789 | mips_4010 = 0; | |
790 | ||
c625fc23 JSC |
791 | if (mips_4100 < 0) |
792 | mips_4100 = 0; | |
793 | ||
ca296aab | 794 | if (mips_4650 || mips_4010 || mips_4100 || mips_cpu == 4300) |
e532b44c ILT |
795 | interlocks = 1; |
796 | else | |
797 | interlocks = 0; | |
798 | ||
ca296aab | 799 | if (mips_cpu == 4300) |
344a8d61 JSC |
800 | cop_interlocks = 1; |
801 | else | |
802 | cop_interlocks = 0; | |
803 | ||
8ea7f4e8 ILT |
804 | if (mips_isa < 2 && mips_trap) |
805 | as_bad ("trap exception not supported at ISA 1"); | |
806 | ||
97f99d11 ILT |
807 | switch (mips_isa) |
808 | { | |
809 | case 1: | |
810 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
811 | break; | |
812 | case 2: | |
813 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
814 | break; | |
815 | case 3: | |
816 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
817 | break; | |
d8a1c247 KR |
818 | case 4: |
819 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
820 | break; | |
97f99d11 ILT |
821 | } |
822 | if (! ok) | |
823 | as_warn ("Could not set architecture and machine"); | |
824 | ||
1051c97f ILT |
825 | file_mips_isa = mips_isa; |
826 | ||
13fe1379 ILT |
827 | op_hash = hash_new (); |
828 | ||
670a50eb ILT |
829 | for (i = 0; i < NUMOPCODES;) |
830 | { | |
831 | const char *name = mips_opcodes[i].name; | |
832 | ||
604633ae | 833 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 834 | if (retval != NULL) |
670a50eb ILT |
835 | { |
836 | fprintf (stderr, "internal error: can't hash `%s': %s\n", | |
837 | mips_opcodes[i].name, retval); | |
838 | as_fatal ("Broken assembler. No assembly attempted."); | |
839 | } | |
840 | do | |
841 | { | |
8358c818 ILT |
842 | if (mips_opcodes[i].pinfo != INSN_MACRO |
843 | && ((mips_opcodes[i].match & mips_opcodes[i].mask) | |
844 | != mips_opcodes[i].match)) | |
670a50eb ILT |
845 | { |
846 | fprintf (stderr, "internal error: bad opcode: `%s' \"%s\"\n", | |
847 | mips_opcodes[i].name, mips_opcodes[i].args); | |
848 | as_fatal ("Broken assembler. No assembly attempted."); | |
3d3c5039 | 849 | } |
670a50eb ILT |
850 | ++i; |
851 | } | |
852 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
853 | } |
854 | ||
cc5703cd ILT |
855 | mips16_op_hash = hash_new (); |
856 | ||
857 | i = 0; | |
858 | while (i < bfd_mips16_num_opcodes) | |
859 | { | |
860 | const char *name = mips16_opcodes[i].name; | |
861 | ||
862 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
863 | if (retval != NULL) | |
864 | as_fatal ("internal error: can't hash `%s': %s\n", | |
865 | mips16_opcodes[i].name, retval); | |
866 | do | |
867 | { | |
868 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
869 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
870 | != mips16_opcodes[i].match)) | |
871 | as_fatal ("internal error: bad opcode: `%s' \"%s\"\n", | |
872 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
873 | ++i; | |
874 | } | |
875 | while (i < bfd_mips16_num_opcodes | |
876 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
877 | } | |
878 | ||
becfe05e ILT |
879 | mips_no_prev_insn (); |
880 | ||
1aa6938e ILT |
881 | mips_gprmask = 0; |
882 | mips_cprmask[0] = 0; | |
883 | mips_cprmask[1] = 0; | |
884 | mips_cprmask[2] = 0; | |
885 | mips_cprmask[3] = 0; | |
886 | ||
8358c818 ILT |
887 | /* set the default alignment for the text section (2**2) */ |
888 | record_alignment (text_section, 2); | |
889 | ||
1dc1e798 KR |
890 | if (USE_GLOBAL_POINTER_OPT) |
891 | bfd_set_gp_size (stdoutput, g_switch_value); | |
abdad6bc | 892 | |
1dc1e798 KR |
893 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
894 | { | |
895 | /* Sections must be aligned to 16 byte boundaries. */ | |
896 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
897 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
898 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
899 | ||
900 | /* Create a .reginfo section for register masks and a .mdebug | |
901 | section for debugging information. */ | |
902 | { | |
903 | segT seg; | |
904 | subsegT subseg; | |
905 | segT sec; | |
906 | ||
907 | seg = now_seg; | |
908 | subseg = now_subseg; | |
1dc1e798 | 909 | |
87178180 ILT |
910 | if (! mips_64) |
911 | { | |
912 | sec = subseg_new (".reginfo", (subsegT) 0); | |
8358c818 | 913 | |
87178180 ILT |
914 | /* The ABI says this section should be loaded so that the |
915 | running program can access it. */ | |
916 | (void) bfd_set_section_flags (stdoutput, sec, | |
917 | (SEC_ALLOC | SEC_LOAD | |
918 | | SEC_READONLY | SEC_DATA)); | |
919 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
920 | ||
f2a663d3 | 921 | #ifdef OBJ_ELF |
87178180 | 922 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
1dc1e798 | 923 | #endif |
87178180 ILT |
924 | } |
925 | else | |
926 | { | |
927 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
928 | .reginfo section. */ | |
929 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
930 | (void) bfd_set_section_flags (stdoutput, sec, | |
931 | (SEC_ALLOC | SEC_LOAD | |
932 | | SEC_READONLY | SEC_DATA)); | |
933 | (void) bfd_set_section_alignment (stdoutput, sec, 3); | |
934 | ||
935 | #ifdef OBJ_ELF | |
936 | /* Set up the option header. */ | |
937 | { | |
938 | Elf_Internal_Options opthdr; | |
939 | char *f; | |
940 | ||
941 | opthdr.kind = ODK_REGINFO; | |
942 | opthdr.size = (sizeof (Elf_External_Options) | |
943 | + sizeof (Elf64_External_RegInfo)); | |
944 | opthdr.section = 0; | |
945 | opthdr.info = 0; | |
946 | f = frag_more (sizeof (Elf_External_Options)); | |
947 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
948 | (Elf_External_Options *) f); | |
949 | ||
950 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
951 | } | |
952 | #endif | |
953 | } | |
f2a663d3 | 954 | |
739708fa KR |
955 | if (ECOFF_DEBUGGING) |
956 | { | |
957 | sec = subseg_new (".mdebug", (subsegT) 0); | |
958 | (void) bfd_set_section_flags (stdoutput, sec, | |
959 | SEC_HAS_CONTENTS | SEC_READONLY); | |
960 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
961 | } | |
0dd2d296 | 962 | |
1dc1e798 KR |
963 | subseg_set (seg, subseg); |
964 | } | |
965 | } | |
f2a663d3 | 966 | |
739708fa KR |
967 | if (! ECOFF_DEBUGGING) |
968 | md_obj_begin (); | |
3d3c5039 ILT |
969 | } |
970 | ||
971 | void | |
13fe1379 | 972 | md_mips_end () |
3d3c5039 | 973 | { |
739708fa KR |
974 | if (! ECOFF_DEBUGGING) |
975 | md_obj_end (); | |
3d3c5039 ILT |
976 | } |
977 | ||
978 | void | |
670a50eb ILT |
979 | md_assemble (str) |
980 | char *str; | |
3d3c5039 | 981 | { |
670a50eb | 982 | struct mips_cl_insn insn; |
3d3c5039 | 983 | |
5ac34ac3 | 984 | imm_expr.X_op = O_absent; |
867a58b3 ILT |
985 | imm_reloc = BFD_RELOC_UNUSED; |
986 | imm_unmatched_hi = false; | |
5ac34ac3 | 987 | offset_expr.X_op = O_absent; |
867a58b3 | 988 | offset_reloc = BFD_RELOC_UNUSED; |
3d3c5039 | 989 | |
cc5703cd ILT |
990 | if (mips16) |
991 | mips16_ip (str, &insn); | |
992 | else | |
993 | mips_ip (str, &insn); | |
994 | ||
670a50eb ILT |
995 | if (insn_error) |
996 | { | |
997 | as_bad ("%s `%s'", insn_error, str); | |
998 | return; | |
999 | } | |
cc5703cd | 1000 | |
670a50eb ILT |
1001 | if (insn.insn_mo->pinfo == INSN_MACRO) |
1002 | { | |
cc5703cd ILT |
1003 | if (mips16) |
1004 | mips16_macro (&insn); | |
1005 | else | |
1006 | macro (&insn); | |
3d3c5039 | 1007 | } |
670a50eb ILT |
1008 | else |
1009 | { | |
5ac34ac3 | 1010 | if (imm_expr.X_op != O_absent) |
867a58b3 ILT |
1011 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, |
1012 | imm_unmatched_hi); | |
5ac34ac3 | 1013 | else if (offset_expr.X_op != O_absent) |
867a58b3 | 1014 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); |
670a50eb | 1015 | else |
867a58b3 | 1016 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); |
3d3c5039 ILT |
1017 | } |
1018 | } | |
1019 | ||
cc5703cd ILT |
1020 | /* See whether instruction IP reads register REG. CLASS is the type |
1021 | of register. */ | |
becfe05e ILT |
1022 | |
1023 | static int | |
cc5703cd | 1024 | insn_uses_reg (ip, reg, class) |
becfe05e | 1025 | struct mips_cl_insn *ip; |
604633ae | 1026 | unsigned int reg; |
cc5703cd | 1027 | enum mips_regclass class; |
becfe05e | 1028 | { |
cc5703cd ILT |
1029 | if (class == MIPS16_REG) |
1030 | { | |
1031 | assert (mips16); | |
1032 | reg = mips16_to_32_reg_map[reg]; | |
1033 | class = MIPS_GR_REG; | |
1034 | } | |
1035 | ||
becfe05e | 1036 | /* Don't report on general register 0, since it never changes. */ |
cc5703cd | 1037 | if (class == MIPS_GR_REG && reg == 0) |
becfe05e ILT |
1038 | return 0; |
1039 | ||
cc5703cd | 1040 | if (class == MIPS_FP_REG) |
becfe05e | 1041 | { |
cc5703cd | 1042 | assert (! mips16); |
becfe05e ILT |
1043 | /* If we are called with either $f0 or $f1, we must check $f0. |
1044 | This is not optimal, because it will introduce an unnecessary | |
1045 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1046 | need to distinguish reading both $f0 and $f1 or just one of | |
1047 | them. Note that we don't have to check the other way, | |
1048 | because there is no instruction that sets both $f0 and $f1 | |
1049 | and requires a delay. */ | |
1050 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
604633ae ILT |
1051 | && (((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) |
1052 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
1053 | return 1; |
1054 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
604633ae ILT |
1055 | && (((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) |
1056 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
1057 | return 1; |
1058 | } | |
cc5703cd | 1059 | else if (! mips16) |
becfe05e ILT |
1060 | { |
1061 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1062 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1063 | return 1; | |
1064 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1065 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1066 | return 1; | |
1067 | } | |
cc5703cd ILT |
1068 | else |
1069 | { | |
1070 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1071 | && ((ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) == reg) | |
1072 | return 1; | |
1073 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1074 | && ((ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY) == reg) | |
1075 | return 1; | |
1076 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1077 | && ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1078 | & MIPS16OP_MASK_MOVE32Z) == reg) | |
1079 | return 1; | |
1080 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1081 | return 1; | |
1082 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1083 | return 1; | |
1084 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1085 | return 1; | |
1086 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1087 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1088 | & MIPS16OP_MASK_REGR32) == reg) | |
1089 | return 1; | |
1090 | } | |
becfe05e ILT |
1091 | |
1092 | return 0; | |
1093 | } | |
1094 | ||
fb251650 ILT |
1095 | /* This function returns true if modifying a register requires a |
1096 | delay. */ | |
1097 | ||
1098 | static int | |
1099 | reg_needs_delay (reg) | |
1100 | int reg; | |
1101 | { | |
1102 | unsigned long prev_pinfo; | |
1103 | ||
1104 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1105 | if (! mips_noreorder | |
1106 | && mips_isa < 4 | |
1107 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1108 | || (mips_isa < 2 | |
1109 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1110 | { | |
1111 | /* A load from a coprocessor or from memory. All load | |
1112 | delays delay the use of general register rt for one | |
1113 | instruction on the r3000. The r6000 and r4000 use | |
1114 | interlocks. */ | |
1115 | know (prev_pinfo & INSN_WRITE_GPR_T); | |
1116 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1117 | return 1; | |
1118 | } | |
1119 | ||
1120 | return 0; | |
1121 | } | |
1122 | ||
0dd2d296 ILT |
1123 | /* Output an instruction. PLACE is where to put the instruction; if |
1124 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1125 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1126 | used with RELOC_TYPE. */ | |
3d3c5039 | 1127 | |
3d3c5039 | 1128 | static void |
867a58b3 | 1129 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) |
0dd2d296 | 1130 | char *place; |
670a50eb ILT |
1131 | struct mips_cl_insn *ip; |
1132 | expressionS *address_expr; | |
1133 | bfd_reloc_code_real_type reloc_type; | |
867a58b3 | 1134 | boolean unmatched_hi; |
3d3c5039 | 1135 | { |
1aa6938e | 1136 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 1137 | char *f; |
becfe05e ILT |
1138 | fixS *fixp; |
1139 | int nops = 0; | |
3d3c5039 | 1140 | |
1aa6938e ILT |
1141 | prev_pinfo = prev_insn.insn_mo->pinfo; |
1142 | pinfo = ip->insn_mo->pinfo; | |
1143 | ||
0dd2d296 | 1144 | if (place == NULL && ! mips_noreorder) |
becfe05e ILT |
1145 | { |
1146 | /* If the previous insn required any delay slots, see if we need | |
8358c818 | 1147 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 1148 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
1149 | (1) a load from memory delay |
1150 | (2) a load from a coprocessor delay | |
1151 | (3) an unconditional branch delay | |
1152 | (4) a conditional branch delay | |
1153 | (5) a move to coprocessor register delay | |
1154 | (6) a load coprocessor register from memory delay | |
1155 | (7) a coprocessor condition code delay | |
1156 | (8) a HI/LO special register delay | |
becfe05e ILT |
1157 | |
1158 | There are a lot of optimizations we could do that we don't. | |
1159 | In particular, we do not, in general, reorder instructions. | |
1160 | If you use gcc with optimization, it will reorder | |
1161 | instructions and generally do much more optimization then we | |
1162 | do here; repeating all that work in the assembler would only | |
1163 | benefit hand written assembly code, and does not seem worth | |
1164 | it. */ | |
1165 | ||
1166 | /* This is how a NOP is emitted. */ | |
cc5703cd ILT |
1167 | #define emit_nop() \ |
1168 | (mips16 \ | |
1169 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1170 | : md_number_to_chars (frag_more (4), 0, 4)) | |
becfe05e ILT |
1171 | |
1172 | /* The previous insn might require a delay slot, depending upon | |
1173 | the contents of the current insn. */ | |
cc5703cd ILT |
1174 | if (! mips16 |
1175 | && mips_isa < 4 | |
5af96dce ILT |
1176 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1177 | && ! cop_interlocks) | |
d8a1c247 KR |
1178 | || (mips_isa < 2 |
1179 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
8358c818 ILT |
1180 | { |
1181 | /* A load from a coprocessor or from memory. All load | |
1182 | delays delay the use of general register rt for one | |
1183 | instruction on the r3000. The r6000 and r4000 use | |
1184 | interlocks. */ | |
1aa6938e | 1185 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
1186 | if (mips_optimize == 0 |
1187 | || insn_uses_reg (ip, | |
1188 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1189 | & OP_MASK_RT), | |
cc5703cd | 1190 | MIPS_GR_REG)) |
becfe05e ILT |
1191 | ++nops; |
1192 | } | |
cc5703cd ILT |
1193 | else if (! mips16 |
1194 | && mips_isa < 4 | |
5af96dce ILT |
1195 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
1196 | && ! cop_interlocks) | |
d8a1c247 KR |
1197 | || (mips_isa < 2 |
1198 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
1199 | { |
1200 | /* A generic coprocessor delay. The previous instruction | |
1201 | modified a coprocessor general or control register. If | |
1202 | it modified a control register, we need to avoid any | |
1203 | coprocessor instruction (this is probably not always | |
1204 | required, but it sometimes is). If it modified a general | |
1205 | register, we avoid using that register. | |
1206 | ||
8358c818 ILT |
1207 | On the r6000 and r4000 loading a coprocessor register |
1208 | from memory is interlocked, and does not require a delay. | |
1209 | ||
becfe05e ILT |
1210 | This case is not handled very well. There is no special |
1211 | knowledge of CP0 handling, and the coprocessors other | |
1212 | than the floating point unit are not distinguished at | |
1213 | all. */ | |
1aa6938e | 1214 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 1215 | { |
0aa07269 ILT |
1216 | if (mips_optimize == 0 |
1217 | || insn_uses_reg (ip, | |
8358c818 ILT |
1218 | ((prev_insn.insn_opcode >> OP_SH_FT) |
1219 | & OP_MASK_FT), | |
cc5703cd | 1220 | MIPS_FP_REG)) |
becfe05e ILT |
1221 | ++nops; |
1222 | } | |
1aa6938e | 1223 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 1224 | { |
0aa07269 ILT |
1225 | if (mips_optimize == 0 |
1226 | || insn_uses_reg (ip, | |
8358c818 ILT |
1227 | ((prev_insn.insn_opcode >> OP_SH_FS) |
1228 | & OP_MASK_FS), | |
cc5703cd | 1229 | MIPS_FP_REG)) |
becfe05e ILT |
1230 | ++nops; |
1231 | } | |
1232 | else | |
1233 | { | |
1234 | /* We don't know exactly what the previous instruction | |
1235 | does. If the current instruction uses a coprocessor | |
1236 | register, we must insert a NOP. If previous | |
1237 | instruction may set the condition codes, and the | |
1238 | current instruction uses them, we must insert two | |
1239 | NOPS. */ | |
0aa07269 | 1240 | if (mips_optimize == 0 |
1aa6938e ILT |
1241 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
1242 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 1243 | nops += 2; |
1aa6938e | 1244 | else if (pinfo & INSN_COP) |
becfe05e ILT |
1245 | ++nops; |
1246 | } | |
1247 | } | |
cc5703cd ILT |
1248 | else if (! mips16 |
1249 | && mips_isa < 4 | |
344a8d61 JSC |
1250 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1251 | && ! cop_interlocks) | |
becfe05e ILT |
1252 | { |
1253 | /* The previous instruction sets the coprocessor condition | |
1254 | codes, but does not require a general coprocessor delay | |
1255 | (this means it is a floating point comparison | |
1256 | instruction). If this instruction uses the condition | |
1257 | codes, we need to insert a single NOP. */ | |
0aa07269 | 1258 | if (mips_optimize == 0 |
1aa6938e | 1259 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1260 | ++nops; |
1261 | } | |
1aa6938e | 1262 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
1263 | { |
1264 | /* The previous instruction reads the LO register; if the | |
1265 | current instruction writes to the LO register, we must | |
517078c1 | 1266 | insert two NOPS. Some newer processors have interlocks. */ |
e532b44c | 1267 | if (! interlocks |
b2b8c24e ILT |
1268 | && (mips_optimize == 0 |
1269 | || (pinfo & INSN_WRITE_LO))) | |
becfe05e ILT |
1270 | nops += 2; |
1271 | } | |
1272 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1273 | { | |
1274 | /* The previous instruction reads the HI register; if the | |
1275 | current instruction writes to the HI register, we must | |
517078c1 | 1276 | insert a NOP. Some newer processors have interlocks. */ |
e532b44c | 1277 | if (! interlocks |
b2b8c24e ILT |
1278 | && (mips_optimize == 0 |
1279 | || (pinfo & INSN_WRITE_HI))) | |
becfe05e ILT |
1280 | nops += 2; |
1281 | } | |
1282 | ||
1283 | /* There are two cases which require two intervening | |
1284 | instructions: 1) setting the condition codes using a move to | |
1285 | coprocessor instruction which requires a general coprocessor | |
1286 | delay and then reading the condition codes 2) reading the HI | |
517078c1 ILT |
1287 | or LO register and then writing to it (except on processors |
1288 | which have interlocks). If we are not already emitting a NOP | |
1289 | instruction, we must check for these cases compared to the | |
1290 | instruction previous to the previous instruction. */ | |
becfe05e | 1291 | if (nops == 0 |
cc5703cd ILT |
1292 | && ((! mips16 |
1293 | && mips_isa < 4 | |
d8a1c247 | 1294 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
becfe05e | 1295 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
344a8d61 JSC |
1296 | && (pinfo & INSN_READ_COND_CODE) |
1297 | && ! cop_interlocks) | |
becfe05e | 1298 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) |
b2b8c24e | 1299 | && (pinfo & INSN_WRITE_LO) |
e532b44c | 1300 | && ! interlocks) |
becfe05e | 1301 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
b2b8c24e | 1302 | && (pinfo & INSN_WRITE_HI) |
e532b44c | 1303 | && ! interlocks))) |
becfe05e ILT |
1304 | ++nops; |
1305 | ||
0dd2d296 ILT |
1306 | /* If we are being given a nop instruction, don't bother with |
1307 | one of the nops we would otherwise output. This will only | |
1308 | happen when a nop instruction is used with mips_optimize set | |
1309 | to 0. */ | |
cc5703cd | 1310 | if (nops > 0 && ip->insn_opcode == (mips16 ? 0x6500 : 0)) |
0dd2d296 ILT |
1311 | --nops; |
1312 | ||
becfe05e ILT |
1313 | /* Now emit the right number of NOP instructions. */ |
1314 | if (nops > 0) | |
1315 | { | |
5af96dce ILT |
1316 | fragS *old_frag; |
1317 | unsigned long old_frag_offset; | |
8c63448a ILT |
1318 | int i; |
1319 | ||
5af96dce ILT |
1320 | old_frag = frag_now; |
1321 | old_frag_offset = frag_now_fix (); | |
1322 | ||
8c63448a | 1323 | for (i = 0; i < nops; i++) |
becfe05e | 1324 | emit_nop (); |
5af96dce | 1325 | |
af255ca0 | 1326 | if (listing) |
546f5536 ILT |
1327 | { |
1328 | listing_prev_line (); | |
1329 | /* We may be at the start of a variant frag. In case we | |
1330 | are, make sure there is enough space for the frag | |
1331 | after the frags created by listing_prev_line. The | |
1332 | argument to frag_grow here must be at least as large | |
1333 | as the argument to all other calls to frag_grow in | |
1334 | this file. We don't have to worry about being in the | |
1335 | middle of a variant frag, because the variants insert | |
1336 | all needed nop instructions themselves. */ | |
1337 | frag_grow (40); | |
1338 | } | |
5af96dce | 1339 | |
becfe05e ILT |
1340 | if (insn_label != NULL) |
1341 | { | |
1342 | assert (S_GET_SEGMENT (insn_label) == now_seg); | |
1343 | insn_label->sy_frag = frag_now; | |
604633ae | 1344 | S_SET_VALUE (insn_label, (valueT) frag_now_fix ()); |
becfe05e | 1345 | } |
5af96dce ILT |
1346 | |
1347 | #ifndef NO_ECOFF_DEBUGGING | |
1348 | if (ECOFF_DEBUGGING) | |
1349 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1350 | #endif | |
becfe05e ILT |
1351 | } |
1352 | } | |
1353 | ||
cc5703cd ILT |
1354 | if (reloc_type > BFD_RELOC_UNUSED) |
1355 | { | |
1356 | /* We need to set up a variant frag. */ | |
1357 | assert (mips16 && address_expr != NULL); | |
1358 | f = frag_var (rs_machine_dependent, 4, 0, | |
1359 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED), | |
1360 | make_expr_symbol (address_expr), (long) 0, | |
1361 | (char *) NULL); | |
1362 | } | |
1363 | else if (place != NULL) | |
0dd2d296 | 1364 | f = place; |
cc5703cd ILT |
1365 | else if (mips16 && ! ip->use_extend && reloc_type != BFD_RELOC_MIPS16_JMP) |
1366 | f = frag_more (2); | |
1367 | else | |
1368 | f = frag_more (4); | |
becfe05e | 1369 | fixp = NULL; |
cc5703cd | 1370 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) |
670a50eb | 1371 | { |
5ac34ac3 | 1372 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
1373 | { |
1374 | switch (reloc_type) | |
1375 | { | |
3d3c5039 | 1376 | case BFD_RELOC_32: |
670a50eb ILT |
1377 | ip->insn_opcode |= address_expr->X_add_number; |
1378 | break; | |
3d3c5039 ILT |
1379 | |
1380 | case BFD_RELOC_LO16: | |
670a50eb ILT |
1381 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
1382 | break; | |
3d3c5039 ILT |
1383 | |
1384 | case BFD_RELOC_MIPS_JMP: | |
5e1e8f23 ILT |
1385 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
1386 | break; | |
1387 | ||
cc5703cd ILT |
1388 | case BFD_RELOC_MIPS16_JMP: |
1389 | ip->insn_opcode |= | |
1390 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1391 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1392 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1393 | break; | |
1394 | ||
3d3c5039 | 1395 | case BFD_RELOC_16_PCREL_S2: |
670a50eb | 1396 | goto need_reloc; |
3d3c5039 ILT |
1397 | |
1398 | default: | |
670a50eb | 1399 | internalError (); |
3d3c5039 | 1400 | } |
670a50eb ILT |
1401 | } |
1402 | else | |
1403 | { | |
3d3c5039 | 1404 | need_reloc: |
0dd2d296 ILT |
1405 | /* Don't generate a reloc if we are writing into a variant |
1406 | frag. */ | |
1407 | if (place == NULL) | |
867a58b3 ILT |
1408 | { |
1409 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1410 | address_expr, | |
1411 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1412 | reloc_type); | |
1413 | if (unmatched_hi) | |
1414 | { | |
1415 | struct mips_hi_fixup *hi_fixup; | |
1416 | ||
1417 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1418 | hi_fixup = ((struct mips_hi_fixup *) | |
1419 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1420 | hi_fixup->fixp = fixp; | |
1421 | hi_fixup->seg = now_seg; | |
1422 | hi_fixup->next = mips_hi_fixup_list; | |
1423 | mips_hi_fixup_list = hi_fixup; | |
1424 | } | |
1425 | } | |
3d3c5039 ILT |
1426 | } |
1427 | } | |
becfe05e | 1428 | |
cc5703cd ILT |
1429 | if (! mips16 || reloc_type == BFD_RELOC_MIPS16_JMP) |
1430 | md_number_to_chars (f, ip->insn_opcode, 4); | |
1431 | else | |
1432 | { | |
1433 | if (ip->use_extend) | |
1434 | { | |
1435 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1436 | f += 2; | |
1437 | } | |
1438 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1439 | } | |
670a50eb | 1440 | |
1aa6938e | 1441 | /* Update the register mask information. */ |
cc5703cd ILT |
1442 | if (! mips16) |
1443 | { | |
1444 | if (pinfo & INSN_WRITE_GPR_D) | |
1445 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1446 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1447 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1448 | if (pinfo & INSN_READ_GPR_S) | |
1449 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1450 | if (pinfo & INSN_WRITE_GPR_31) | |
1451 | mips_gprmask |= 1 << 31; | |
1452 | if (pinfo & INSN_WRITE_FPR_D) | |
1453 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1454 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1455 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1456 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1457 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1458 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1459 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1460 | if (pinfo & INSN_COP) | |
1461 | { | |
1462 | /* We don't keep enough information to sort these cases out. */ | |
1463 | } | |
1464 | /* Never set the bit for $0, which is always zero. */ | |
1465 | mips_gprmask &=~ 1 << 0; | |
1466 | } | |
1467 | else | |
1aa6938e | 1468 | { |
cc5703cd ILT |
1469 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) |
1470 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1471 | & MIPS16OP_MASK_RX); | |
1472 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1473 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1474 | & MIPS16OP_MASK_RY); | |
1475 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1476 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1477 | & MIPS16OP_MASK_RZ); | |
1478 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1479 | mips_gprmask |= 1 << TREG; | |
1480 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1481 | mips_gprmask |= 1 << SP; | |
1482 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1483 | mips_gprmask |= 1 << RA; | |
1484 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1485 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1486 | if (pinfo & MIPS16_INSN_READ_Z) | |
1487 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1488 | & MIPS16OP_MASK_MOVE32Z); | |
1489 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1490 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1491 | & MIPS16OP_MASK_REGR32); | |
1aa6938e | 1492 | } |
1aa6938e | 1493 | |
0dd2d296 | 1494 | if (place == NULL && ! mips_noreorder) |
670a50eb | 1495 | { |
becfe05e ILT |
1496 | /* Filling the branch delay slot is more complex. We try to |
1497 | switch the branch with the previous instruction, which we can | |
1498 | do if the previous instruction does not set up a condition | |
1499 | that the branch tests and if the branch is not itself the | |
1500 | target of any branch. */ | |
1aa6938e ILT |
1501 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
1502 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 1503 | { |
0aa07269 | 1504 | if (mips_optimize < 2 |
19ed8960 ILT |
1505 | /* If we have seen .set volatile or .set nomove, don't |
1506 | optimize. */ | |
1507 | || mips_nomove != 0 | |
4e95866e ILT |
1508 | /* If we had to emit any NOP instructions, then we |
1509 | already know we can not swap. */ | |
1510 | || nops != 0 | |
becfe05e ILT |
1511 | /* If we don't even know the previous insn, we can not |
1512 | swap. */ | |
1513 | || ! prev_insn_valid | |
1514 | /* If the previous insn is already in a branch delay | |
1515 | slot, then we can not swap. */ | |
1516 | || prev_insn_is_delay_slot | |
4e95866e ILT |
1517 | /* If the previous previous insn was in a .set |
1518 | noreorder, we can't swap. Actually, the MIPS | |
1519 | assembler will swap in this situation. However, gcc | |
1520 | configured -with-gnu-as will generate code like | |
1521 | .set noreorder | |
1522 | lw $4,XXX | |
1523 | .set reorder | |
1524 | INSN | |
1525 | bne $4,$0,foo | |
1526 | in which we can not swap the bne and INSN. If gcc is | |
1527 | not configured -with-gnu-as, it does not output the | |
1528 | .set pseudo-ops. We don't have to check | |
1529 | prev_insn_unreordered, because prev_insn_valid will | |
1530 | be 0 in that case. We don't want to use | |
1531 | prev_prev_insn_valid, because we do want to be able | |
1532 | to swap at the start of a function. */ | |
1533 | || prev_prev_insn_unreordered | |
becfe05e ILT |
1534 | /* If the branch is itself the target of a branch, we |
1535 | can not swap. We cheat on this; all we check for is | |
1536 | whether there is a label on this instruction. If | |
1537 | there are any branches to anything other than a | |
1538 | label, users must use .set noreorder. */ | |
1539 | || insn_label != NULL | |
777ad64d | 1540 | /* If the previous instruction is in a variant frag, we |
cc5703cd ILT |
1541 | can not do the swap. This does not apply to the |
1542 | mips16, which uses variant frags for different | |
1543 | purposes. */ | |
1544 | || (! mips16 | |
1545 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
becfe05e ILT |
1546 | /* If the branch reads the condition codes, we don't |
1547 | even try to swap, because in the sequence | |
1548 | ctc1 $X,$31 | |
1549 | INSN | |
1550 | INSN | |
1551 | bc1t LABEL | |
1552 | we can not swap, and I don't feel like handling that | |
1553 | case. */ | |
cc5703cd ILT |
1554 | || (! mips16 |
1555 | && mips_isa < 4 | |
d8a1c247 | 1556 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1557 | /* We can not swap with an instruction that requires a |
1558 | delay slot, becase the target of the branch might | |
1559 | interfere with that instruction. */ | |
cc5703cd ILT |
1560 | || (! mips16 |
1561 | && mips_isa < 4 | |
d8a1c247 KR |
1562 | && (prev_pinfo |
1563 | & (INSN_LOAD_COPROC_DELAY | |
1564 | | INSN_COPROC_MOVE_DELAY | |
1565 | | INSN_WRITE_COND_CODE))) | |
e532b44c | 1566 | || (! interlocks |
b2b8c24e ILT |
1567 | && (prev_pinfo |
1568 | & (INSN_READ_LO | |
1569 | | INSN_READ_HI))) | |
cc5703cd ILT |
1570 | || (! mips16 |
1571 | && mips_isa < 2 | |
1aa6938e | 1572 | && (prev_pinfo |
8358c818 ILT |
1573 | & (INSN_LOAD_MEMORY_DELAY |
1574 | | INSN_COPROC_MEMORY_DELAY))) | |
becfe05e | 1575 | /* We can not swap with a branch instruction. */ |
1aa6938e | 1576 | || (prev_pinfo |
6e8dda9c ILT |
1577 | & (INSN_UNCOND_BRANCH_DELAY |
1578 | | INSN_COND_BRANCH_DELAY | |
1579 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
1580 | /* We do not swap with a trap instruction, since it |
1581 | complicates trap handlers to have the trap | |
1582 | instruction be in a delay slot. */ | |
1aa6938e | 1583 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
1584 | /* If the branch reads a register that the previous |
1585 | instruction sets, we can not swap. */ | |
cc5703cd ILT |
1586 | || (! mips16 |
1587 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
becfe05e ILT |
1588 | && insn_uses_reg (ip, |
1589 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1590 | & OP_MASK_RT), | |
cc5703cd ILT |
1591 | MIPS_GR_REG)) |
1592 | || (! mips16 | |
1593 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
becfe05e ILT |
1594 | && insn_uses_reg (ip, |
1595 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
1596 | & OP_MASK_RD), | |
cc5703cd ILT |
1597 | MIPS_GR_REG)) |
1598 | || (mips16 | |
1599 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
1600 | && insn_uses_reg (ip, | |
1601 | ((prev_insn.insn_opcode | |
1602 | >> MIPS16OP_SH_RX) | |
1603 | & MIPS16OP_MASK_RX), | |
1604 | MIPS16_REG)) | |
1605 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
1606 | && insn_uses_reg (ip, | |
1607 | ((prev_insn.insn_opcode | |
1608 | >> MIPS16OP_SH_RY) | |
1609 | & MIPS16OP_MASK_RY), | |
1610 | MIPS16_REG)) | |
1611 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
1612 | && insn_uses_reg (ip, | |
1613 | ((prev_insn.insn_opcode | |
1614 | >> MIPS16OP_SH_RZ) | |
1615 | & MIPS16OP_MASK_RZ), | |
1616 | MIPS16_REG)) | |
1617 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
1618 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
1619 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1620 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
1621 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1622 | && insn_uses_reg (ip, | |
1623 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
1624 | insn_opcode), | |
1625 | MIPS_GR_REG)))) | |
1849d646 ILT |
1626 | /* If the branch writes a register that the previous |
1627 | instruction sets, we can not swap (we know that | |
1628 | branches write only to RD or to $31). */ | |
cc5703cd ILT |
1629 | || (! mips16 |
1630 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
1aa6938e | 1631 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1632 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
1633 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1634 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1635 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
1636 | & OP_MASK_RT) | |
1637 | == 31)))) | |
cc5703cd ILT |
1638 | || (! mips16 |
1639 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
1aa6938e | 1640 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1641 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
1642 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1643 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1644 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
1645 | & OP_MASK_RD) | |
1646 | == 31)))) | |
cc5703cd ILT |
1647 | || (mips16 |
1648 | && (pinfo & MIPS16_INSN_WRITE_31) | |
1649 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1650 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1651 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
1652 | == RA)))) | |
becfe05e ILT |
1653 | /* If the branch writes a register that the previous |
1654 | instruction reads, we can not swap (we know that | |
1655 | branches only write to RD or to $31). */ | |
cc5703cd ILT |
1656 | || (! mips16 |
1657 | && (pinfo & INSN_WRITE_GPR_D) | |
becfe05e ILT |
1658 | && insn_uses_reg (&prev_insn, |
1659 | ((ip->insn_opcode >> OP_SH_RD) | |
1660 | & OP_MASK_RD), | |
cc5703cd ILT |
1661 | MIPS_GR_REG)) |
1662 | || (! mips16 | |
1663 | && (pinfo & INSN_WRITE_GPR_31) | |
1664 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
1665 | || (mips16 | |
1666 | && (pinfo & MIPS16_INSN_WRITE_31) | |
1667 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
5b63f465 ILT |
1668 | /* If we are generating embedded PIC code, the branch |
1669 | might be expanded into a sequence which uses $at, so | |
1670 | we can't swap with an instruction which reads it. */ | |
1671 | || (mips_pic == EMBEDDED_PIC | |
cc5703cd | 1672 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) |
becfe05e ILT |
1673 | /* If the previous previous instruction has a load |
1674 | delay, and sets a register that the branch reads, we | |
1675 | can not swap. */ | |
cc5703cd ILT |
1676 | || (! mips16 |
1677 | && mips_isa < 4 | |
d8a1c247 KR |
1678 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
1679 | || (mips_isa < 2 | |
1680 | && (prev_prev_insn.insn_mo->pinfo | |
1681 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
1682 | && insn_uses_reg (ip, |
1683 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
1684 | & OP_MASK_RT), | |
cc5703cd | 1685 | MIPS_GR_REG)) |
d31a3f5e ILT |
1686 | /* If one instruction sets a condition code and the |
1687 | other one uses a condition code, we can not swap. */ | |
1688 | || ((pinfo & INSN_READ_COND_CODE) | |
1689 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
1690 | || ((pinfo & INSN_WRITE_COND_CODE) | |
cc5703cd ILT |
1691 | && (prev_pinfo & INSN_READ_COND_CODE)) |
1692 | /* If the previous instruction uses the PC, we can not | |
1693 | swap. */ | |
1694 | || (mips16 | |
1695 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
1696 | /* If the previous instruction was extended, we can not | |
1697 | swap. */ | |
1698 | || (mips16 && prev_insn_extended) | |
1699 | /* If the previous instruction had a fixup in mips16 | |
1700 | mode, we can not swap. This normally means that the | |
1701 | previous instruction was a 4 byte branch anyhow. */ | |
1702 | || (mips16 && prev_insn_fixp)) | |
becfe05e ILT |
1703 | { |
1704 | /* We could do even better for unconditional branches to | |
1705 | portions of this object file; we could pick up the | |
1706 | instruction at the destination, put it in the delay | |
1707 | slot, and bump the destination address. */ | |
1708 | emit_nop (); | |
1709 | /* Update the previous insn information. */ | |
1710 | prev_prev_insn = *ip; | |
1711 | prev_insn.insn_mo = &dummy_opcode; | |
1712 | } | |
1713 | else | |
1714 | { | |
becfe05e | 1715 | /* It looks like we can actually do the swap. */ |
cc5703cd ILT |
1716 | if (! mips16) |
1717 | { | |
1718 | char *prev_f; | |
1719 | char temp[4]; | |
1720 | ||
1721 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1722 | memcpy (temp, prev_f, 4); | |
1723 | memcpy (prev_f, f, 4); | |
1724 | memcpy (f, temp, 4); | |
1725 | if (prev_insn_fixp) | |
1726 | { | |
1727 | prev_insn_fixp->fx_frag = frag_now; | |
1728 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
1729 | } | |
1730 | if (fixp) | |
1731 | { | |
1732 | fixp->fx_frag = prev_insn_frag; | |
1733 | fixp->fx_where = prev_insn_where; | |
1734 | } | |
1735 | } | |
1736 | else if (reloc_type > BFD_RELOC_UNUSED) | |
becfe05e | 1737 | { |
cc5703cd ILT |
1738 | char *prev_f; |
1739 | char temp[2]; | |
1740 | ||
1741 | /* We are in mips16 mode, and we have just created a | |
1742 | variant frag. We need to extract the old | |
1743 | instruction from the end of the previous frag, | |
1744 | and add it to a new frag. */ | |
1745 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1746 | memcpy (temp, prev_f, 2); | |
1747 | prev_insn_frag->fr_fix -= 2; | |
1748 | if (prev_insn_frag->fr_type == rs_machine_dependent) | |
1749 | { | |
1750 | assert (prev_insn_where == prev_insn_frag->fr_fix); | |
1751 | memcpy (prev_f, prev_f + 2, 2); | |
1752 | } | |
1753 | memcpy (frag_more (2), temp, 2); | |
becfe05e | 1754 | } |
cc5703cd | 1755 | else |
becfe05e | 1756 | { |
cc5703cd ILT |
1757 | char *prev_f; |
1758 | char temp[2]; | |
1759 | ||
1760 | assert (prev_insn_fixp == NULL); | |
1761 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1762 | memcpy (temp, prev_f, 2); | |
1763 | memcpy (prev_f, f, 2); | |
1764 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
1765 | memcpy (f, temp, 2); | |
1766 | else | |
1767 | { | |
1768 | memcpy (f, f + 2, 2); | |
1769 | memcpy (f + 2, temp, 2); | |
1770 | } | |
1771 | if (fixp) | |
1772 | { | |
1773 | fixp->fx_frag = prev_insn_frag; | |
1774 | fixp->fx_where = prev_insn_where; | |
1775 | } | |
becfe05e | 1776 | } |
cc5703cd | 1777 | |
becfe05e ILT |
1778 | /* Update the previous insn information; leave prev_insn |
1779 | unchanged. */ | |
1780 | prev_prev_insn = *ip; | |
1781 | } | |
1782 | prev_insn_is_delay_slot = 1; | |
1783 | ||
1784 | /* If that was an unconditional branch, forget the previous | |
1785 | insn information. */ | |
1aa6938e | 1786 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
1787 | { |
1788 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1789 | prev_insn.insn_mo = &dummy_opcode; | |
1790 | } | |
1791 | } | |
1aa6938e | 1792 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
1793 | { |
1794 | /* We don't yet optimize a branch likely. What we should do | |
1795 | is look at the target, copy the instruction found there | |
1796 | into the delay slot, and increment the branch to jump to | |
1797 | the next instruction. */ | |
1798 | emit_nop (); | |
1799 | /* Update the previous insn information. */ | |
1800 | prev_prev_insn = *ip; | |
1801 | prev_insn.insn_mo = &dummy_opcode; | |
1802 | } | |
becfe05e | 1803 | else |
670a50eb | 1804 | { |
becfe05e ILT |
1805 | /* Update the previous insn information. */ |
1806 | if (nops > 0) | |
1807 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1808 | else | |
1809 | prev_prev_insn = prev_insn; | |
1810 | prev_insn = *ip; | |
1811 | ||
1812 | /* Any time we see a branch, we always fill the delay slot | |
1813 | immediately; since this insn is not a branch, we know it | |
1814 | is not in a delay slot. */ | |
1815 | prev_insn_is_delay_slot = 0; | |
1816 | } | |
1817 | ||
4e95866e ILT |
1818 | prev_prev_insn_unreordered = prev_insn_unreordered; |
1819 | prev_insn_unreordered = 0; | |
becfe05e ILT |
1820 | prev_insn_frag = frag_now; |
1821 | prev_insn_where = f - frag_now->fr_literal; | |
1822 | prev_insn_fixp = fixp; | |
cc5703cd ILT |
1823 | if (mips16) |
1824 | prev_insn_extended = ip->use_extend || reloc_type > BFD_RELOC_UNUSED; | |
becfe05e ILT |
1825 | prev_insn_valid = 1; |
1826 | } | |
3d3c5039 | 1827 | |
becfe05e ILT |
1828 | /* We just output an insn, so the next one doesn't have a label. */ |
1829 | insn_label = NULL; | |
1830 | } | |
1831 | ||
1832 | /* This function forgets that there was any previous instruction or | |
1833 | label. */ | |
1834 | ||
1835 | static void | |
1836 | mips_no_prev_insn () | |
1837 | { | |
1838 | prev_insn.insn_mo = &dummy_opcode; | |
1839 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1840 | prev_insn_valid = 0; | |
1841 | prev_insn_is_delay_slot = 0; | |
4e95866e | 1842 | prev_insn_unreordered = 0; |
cc5703cd | 1843 | prev_insn_extended = 0; |
4e95866e | 1844 | prev_prev_insn_unreordered = 0; |
becfe05e ILT |
1845 | insn_label = NULL; |
1846 | } | |
1847 | ||
1848 | /* This function must be called whenever we turn on noreorder or emit | |
1849 | something other than instructions. It inserts any NOPS which might | |
1850 | be needed by the previous instruction, and clears the information | |
1851 | kept for the previous instructions. */ | |
1852 | ||
1853 | static void | |
1854 | mips_emit_delays () | |
1855 | { | |
1856 | if (! mips_noreorder) | |
1857 | { | |
1858 | int nop; | |
1859 | ||
1860 | nop = 0; | |
cc5703cd ILT |
1861 | if ((! mips16 |
1862 | && mips_isa < 4 | |
344a8d61 JSC |
1863 | && (! cop_interlocks |
1864 | && (prev_insn.insn_mo->pinfo | |
1865 | & (INSN_LOAD_COPROC_DELAY | |
1866 | | INSN_COPROC_MOVE_DELAY | |
1867 | | INSN_WRITE_COND_CODE)))) | |
e532b44c | 1868 | || (! interlocks |
b2b8c24e ILT |
1869 | && (prev_insn.insn_mo->pinfo |
1870 | & (INSN_READ_LO | |
1871 | | INSN_READ_HI))) | |
cc5703cd ILT |
1872 | || (! mips16 |
1873 | && mips_isa < 2 | |
8358c818 ILT |
1874 | && (prev_insn.insn_mo->pinfo |
1875 | & (INSN_LOAD_MEMORY_DELAY | |
1876 | | INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
1877 | { |
1878 | nop = 1; | |
cc5703cd ILT |
1879 | if ((! mips16 |
1880 | && mips_isa < 4 | |
344a8d61 JSC |
1881 | && (! cop_interlocks |
1882 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 1883 | || (! interlocks |
b2b8c24e ILT |
1884 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1885 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
becfe05e ILT |
1886 | emit_nop (); |
1887 | } | |
cc5703cd ILT |
1888 | else if ((! mips16 |
1889 | && mips_isa < 4 | |
344a8d61 JSC |
1890 | && (! cop_interlocks |
1891 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 1892 | || (! interlocks |
b2b8c24e ILT |
1893 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1894 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
becfe05e ILT |
1895 | nop = 1; |
1896 | if (nop) | |
670a50eb | 1897 | { |
becfe05e ILT |
1898 | emit_nop (); |
1899 | if (insn_label != NULL) | |
1900 | { | |
1901 | assert (S_GET_SEGMENT (insn_label) == now_seg); | |
1902 | insn_label->sy_frag = frag_now; | |
604633ae | 1903 | S_SET_VALUE (insn_label, (valueT) frag_now_fix ()); |
becfe05e | 1904 | } |
3d3c5039 ILT |
1905 | } |
1906 | } | |
0221ddf7 ILT |
1907 | |
1908 | mips_no_prev_insn (); | |
3d3c5039 ILT |
1909 | } |
1910 | ||
670a50eb ILT |
1911 | /* Build an instruction created by a macro expansion. This is passed |
1912 | a pointer to the count of instructions created so far, an | |
1913 | expression, the name of the instruction to build, an operand format | |
1914 | string, and corresponding arguments. */ | |
1915 | ||
1dc1e798 | 1916 | #ifdef USE_STDARG |
3d3c5039 | 1917 | static void |
0dd2d296 ILT |
1918 | macro_build (char *place, |
1919 | int *counter, | |
670a50eb | 1920 | expressionS * ep, |
3d3c5039 ILT |
1921 | const char *name, |
1922 | const char *fmt, | |
1923 | ...) | |
1dc1e798 | 1924 | #else |
3d3c5039 | 1925 | static void |
0dd2d296 ILT |
1926 | macro_build (place, counter, ep, name, fmt, va_alist) |
1927 | char *place; | |
3d3c5039 ILT |
1928 | int *counter; |
1929 | expressionS *ep; | |
1930 | const char *name; | |
1931 | const char *fmt; | |
1932 | va_dcl | |
1dc1e798 | 1933 | #endif |
3d3c5039 | 1934 | { |
670a50eb ILT |
1935 | struct mips_cl_insn insn; |
1936 | bfd_reloc_code_real_type r; | |
1937 | va_list args; | |
3d3c5039 | 1938 | |
1dc1e798 | 1939 | #ifdef USE_STDARG |
670a50eb | 1940 | va_start (args, fmt); |
3d3c5039 | 1941 | #else |
670a50eb | 1942 | va_start (args); |
3d3c5039 ILT |
1943 | #endif |
1944 | ||
670a50eb ILT |
1945 | /* |
1946 | * If the macro is about to expand into a second instruction, | |
1947 | * print a warning if needed. We need to pass ip as a parameter | |
1948 | * to generate a better warning message here... | |
1949 | */ | |
0dd2d296 | 1950 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
1951 | as_warn ("Macro instruction expanded into multiple instructions"); |
1952 | ||
0dd2d296 ILT |
1953 | if (place == NULL) |
1954 | *counter += 1; /* bump instruction counter */ | |
670a50eb | 1955 | |
cc5703cd ILT |
1956 | if (mips16) |
1957 | { | |
1958 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
1959 | va_end (args); | |
1960 | return; | |
1961 | } | |
1962 | ||
670a50eb ILT |
1963 | r = BFD_RELOC_UNUSED; |
1964 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
1965 | assert (insn.insn_mo); | |
1966 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
1967 | ||
9226253a | 1968 | while (strcmp (fmt, insn.insn_mo->args) != 0 |
c625fc23 JSC |
1969 | || insn.insn_mo->pinfo == INSN_MACRO |
1970 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA2 | |
1971 | && mips_isa < 2) | |
1972 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA3 | |
1973 | && mips_isa < 3) | |
1974 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA4 | |
1975 | && mips_isa < 4) | |
1976 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4650 | |
1977 | && ! mips_4650) | |
1978 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4010 | |
1979 | && ! mips_4010) | |
1980 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4100 | |
1981 | && ! mips_4100)) | |
670a50eb ILT |
1982 | { |
1983 | ++insn.insn_mo; | |
1984 | assert (insn.insn_mo->name); | |
1985 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 1986 | } |
670a50eb ILT |
1987 | insn.insn_opcode = insn.insn_mo->match; |
1988 | for (;;) | |
1989 | { | |
1990 | switch (*fmt++) | |
1991 | { | |
3d3c5039 | 1992 | case '\0': |
670a50eb | 1993 | break; |
3d3c5039 ILT |
1994 | |
1995 | case ',': | |
1996 | case '(': | |
1997 | case ')': | |
670a50eb | 1998 | continue; |
3d3c5039 ILT |
1999 | |
2000 | case 't': | |
2001 | case 'w': | |
918692a5 | 2002 | case 'E': |
670a50eb ILT |
2003 | insn.insn_opcode |= va_arg (args, int) << 16; |
2004 | continue; | |
3d3c5039 ILT |
2005 | |
2006 | case 'c': | |
2007 | case 'T': | |
2008 | case 'W': | |
670a50eb ILT |
2009 | insn.insn_opcode |= va_arg (args, int) << 16; |
2010 | continue; | |
3d3c5039 ILT |
2011 | |
2012 | case 'd': | |
918692a5 | 2013 | case 'G': |
670a50eb ILT |
2014 | insn.insn_opcode |= va_arg (args, int) << 11; |
2015 | continue; | |
3d3c5039 ILT |
2016 | |
2017 | case 'V': | |
2018 | case 'S': | |
670a50eb ILT |
2019 | insn.insn_opcode |= va_arg (args, int) << 11; |
2020 | continue; | |
3d3c5039 | 2021 | |
ff3a5c18 ILT |
2022 | case 'z': |
2023 | continue; | |
2024 | ||
3d3c5039 | 2025 | case '<': |
670a50eb ILT |
2026 | insn.insn_opcode |= va_arg (args, int) << 6; |
2027 | continue; | |
3d3c5039 ILT |
2028 | |
2029 | case 'D': | |
670a50eb ILT |
2030 | insn.insn_opcode |= va_arg (args, int) << 6; |
2031 | continue; | |
3d3c5039 | 2032 | |
918692a5 ILT |
2033 | case 'B': |
2034 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2035 | continue; | |
2036 | ||
3d3c5039 ILT |
2037 | case 'b': |
2038 | case 's': | |
2039 | case 'r': | |
2040 | case 'v': | |
670a50eb ILT |
2041 | insn.insn_opcode |= va_arg (args, int) << 21; |
2042 | continue; | |
3d3c5039 ILT |
2043 | |
2044 | case 'i': | |
2045 | case 'j': | |
2046 | case 'o': | |
9226253a | 2047 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
2048 | assert (r == BFD_RELOC_MIPS_GPREL |
2049 | || r == BFD_RELOC_MIPS_LITERAL | |
2050 | || r == BFD_RELOC_LO16 | |
2051 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c | 2052 | || r == BFD_RELOC_MIPS_CALL16 |
fb251650 ILT |
2053 | || r == BFD_RELOC_MIPS_GOT_LO16 |
2054 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
ecd4ca1c ILT |
2055 | || (ep->X_op == O_subtract |
2056 | && now_seg == text_section | |
ecd4ca1c | 2057 | && r == BFD_RELOC_PCREL_LO16)); |
670a50eb | 2058 | continue; |
3d3c5039 | 2059 | |
6e8dda9c | 2060 | case 'u': |
ecd4ca1c ILT |
2061 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
2062 | assert (ep != NULL | |
2063 | && (ep->X_op == O_constant | |
2064 | || (ep->X_op == O_symbol | |
2065 | && (r == BFD_RELOC_HI16_S | |
fb251650 ILT |
2066 | || r == BFD_RELOC_HI16 |
2067 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2068 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
ecd4ca1c ILT |
2069 | || (ep->X_op == O_subtract |
2070 | && now_seg == text_section | |
ecd4ca1c ILT |
2071 | && r == BFD_RELOC_PCREL_HI16_S))); |
2072 | if (ep->X_op == O_constant) | |
2073 | { | |
2074 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2075 | ep = NULL; | |
2076 | r = BFD_RELOC_UNUSED; | |
2077 | } | |
6e8dda9c ILT |
2078 | continue; |
2079 | ||
3d3c5039 | 2080 | case 'p': |
670a50eb ILT |
2081 | assert (ep != NULL); |
2082 | /* | |
2083 | * This allows macro() to pass an immediate expression for | |
2084 | * creating short branches without creating a symbol. | |
2085 | * Note that the expression still might come from the assembly | |
2086 | * input, in which case the value is not checked for range nor | |
2087 | * is a relocation entry generated (yuck). | |
2088 | */ | |
5ac34ac3 | 2089 | if (ep->X_op == O_constant) |
670a50eb ILT |
2090 | { |
2091 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2092 | ep = NULL; | |
2093 | } | |
2094 | else | |
2095 | r = BFD_RELOC_16_PCREL_S2; | |
2096 | continue; | |
3d3c5039 | 2097 | |
9226253a ILT |
2098 | case 'a': |
2099 | assert (ep != NULL); | |
2100 | r = BFD_RELOC_MIPS_JMP; | |
2101 | continue; | |
2102 | ||
3d3c5039 | 2103 | default: |
670a50eb | 2104 | internalError (); |
3d3c5039 | 2105 | } |
670a50eb | 2106 | break; |
3d3c5039 | 2107 | } |
670a50eb ILT |
2108 | va_end (args); |
2109 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2110 | ||
867a58b3 | 2111 | append_insn (place, &insn, ep, r, false); |
3d3c5039 ILT |
2112 | } |
2113 | ||
cc5703cd ILT |
2114 | static void |
2115 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2116 | char *place; | |
2117 | int *counter; | |
2118 | expressionS *ep; | |
2119 | const char *name; | |
2120 | const char *fmt; | |
2121 | va_list args; | |
2122 | { | |
2123 | struct mips_cl_insn insn; | |
2124 | bfd_reloc_code_real_type r; | |
2125 | ||
2126 | r = BFD_RELOC_UNUSED; | |
2127 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2128 | assert (insn.insn_mo); | |
2129 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2130 | ||
2131 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2132 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2133 | { | |
2134 | ++insn.insn_mo; | |
2135 | assert (insn.insn_mo->name); | |
2136 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2137 | } | |
2138 | ||
2139 | insn.insn_opcode = insn.insn_mo->match; | |
2140 | insn.use_extend = false; | |
2141 | ||
2142 | for (;;) | |
2143 | { | |
2144 | int c; | |
2145 | ||
2146 | c = *fmt++; | |
2147 | switch (c) | |
2148 | { | |
2149 | case '\0': | |
2150 | break; | |
2151 | ||
2152 | case ',': | |
2153 | case '(': | |
2154 | case ')': | |
2155 | continue; | |
2156 | ||
2157 | case 'y': | |
2158 | case 'w': | |
2159 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2160 | continue; | |
2161 | ||
2162 | case 'x': | |
2163 | case 'v': | |
2164 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2165 | continue; | |
2166 | ||
2167 | case 'z': | |
2168 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2169 | continue; | |
2170 | ||
2171 | case 'Z': | |
2172 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2173 | continue; | |
2174 | ||
2175 | case '0': | |
2176 | case 'S': | |
2177 | case 'P': | |
2178 | case 'R': | |
2179 | continue; | |
2180 | ||
2181 | case 'X': | |
2182 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2183 | continue; | |
2184 | ||
2185 | case 'Y': | |
2186 | { | |
2187 | int regno; | |
2188 | ||
2189 | regno = va_arg (args, int); | |
2190 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2191 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2192 | } | |
2193 | continue; | |
2194 | ||
2195 | case '<': | |
2196 | case '>': | |
2197 | case '4': | |
2198 | case '5': | |
2199 | case 'H': | |
2200 | case 'W': | |
2201 | case 'D': | |
2202 | case 'j': | |
2203 | case '8': | |
2204 | case 'V': | |
2205 | case 'C': | |
2206 | case 'U': | |
2207 | case 'k': | |
2208 | case 'K': | |
2209 | case 'p': | |
2210 | case 'q': | |
2211 | { | |
2212 | assert (ep != NULL); | |
2213 | ||
2214 | if (ep->X_op != O_constant) | |
2215 | r = BFD_RELOC_UNUSED + c; | |
2216 | else | |
2217 | { | |
2218 | mips16_immed (c, ep->X_add_number, false, false, false, | |
2219 | &insn.insn_opcode, &insn.use_extend, | |
2220 | &insn.extend); | |
2221 | ep = NULL; | |
2222 | r = BFD_RELOC_UNUSED; | |
2223 | } | |
2224 | } | |
2225 | continue; | |
2226 | ||
2227 | case '6': | |
2228 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2229 | continue; | |
2230 | } | |
2231 | ||
2232 | break; | |
2233 | } | |
2234 | ||
2235 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2236 | ||
2237 | append_insn (place, &insn, ep, r, false); | |
2238 | } | |
2239 | ||
3d3c5039 ILT |
2240 | /* |
2241 | * Generate a "lui" instruction. | |
2242 | */ | |
2243 | static void | |
0dd2d296 ILT |
2244 | macro_build_lui (place, counter, ep, regnum) |
2245 | char *place; | |
3d3c5039 ILT |
2246 | int *counter; |
2247 | expressionS *ep; | |
2248 | int regnum; | |
2249 | { | |
670a50eb ILT |
2250 | expressionS high_expr; |
2251 | struct mips_cl_insn insn; | |
2252 | bfd_reloc_code_real_type r; | |
2253 | CONST char *name = "lui"; | |
2254 | CONST char *fmt = "t,u"; | |
2255 | ||
cc5703cd ILT |
2256 | assert (! mips16); |
2257 | ||
0dd2d296 ILT |
2258 | if (place == NULL) |
2259 | high_expr = *ep; | |
2260 | else | |
2261 | { | |
2262 | high_expr.X_op = O_constant; | |
fb251650 | 2263 | high_expr.X_add_number = ep->X_add_number; |
0dd2d296 | 2264 | } |
670a50eb | 2265 | |
5ac34ac3 | 2266 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
2267 | { |
2268 | /* we can compute the instruction now without a relocation entry */ | |
2269 | if (high_expr.X_add_number & 0x8000) | |
2270 | high_expr.X_add_number += 0x10000; | |
2271 | high_expr.X_add_number = | |
2272 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2273 | r = BFD_RELOC_UNUSED; | |
2274 | } | |
2275 | else | |
0dd2d296 ILT |
2276 | { |
2277 | assert (ep->X_op == O_symbol); | |
2278 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 2279 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
2280 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
2281 | r = BFD_RELOC_HI16_S; | |
2282 | } | |
670a50eb ILT |
2283 | |
2284 | /* | |
2285 | * If the macro is about to expand into a second instruction, | |
2286 | * print a warning if needed. We need to pass ip as a parameter | |
2287 | * to generate a better warning message here... | |
2288 | */ | |
0dd2d296 | 2289 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2290 | as_warn ("Macro instruction expanded into multiple instructions"); |
2291 | ||
0dd2d296 ILT |
2292 | if (place == NULL) |
2293 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
2294 | |
2295 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2296 | assert (insn.insn_mo); | |
2297 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2298 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2299 | ||
0dd2d296 | 2300 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
2301 | if (r == BFD_RELOC_UNUSED) |
2302 | { | |
2303 | insn.insn_opcode |= high_expr.X_add_number; | |
867a58b3 | 2304 | append_insn (place, &insn, NULL, r, false); |
670a50eb ILT |
2305 | } |
2306 | else | |
867a58b3 | 2307 | append_insn (place, &insn, &high_expr, r, false); |
3d3c5039 ILT |
2308 | } |
2309 | ||
2310 | /* set_at() | |
2311 | * Generates code to set the $at register to true (one) | |
2312 | * if reg is less than the immediate expression. | |
2313 | */ | |
2314 | static void | |
6e8dda9c | 2315 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
2316 | int *counter; |
2317 | int reg; | |
6e8dda9c | 2318 | int unsignedp; |
3d3c5039 | 2319 | { |
6e8dda9c | 2320 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
0dd2d296 | 2321 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 2322 | unsignedp ? "sltiu" : "slti", |
9226253a | 2323 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 2324 | else |
670a50eb | 2325 | { |
d8a1c247 | 2326 | load_register (counter, AT, &imm_expr, 0); |
0dd2d296 | 2327 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
2328 | unsignedp ? "sltu" : "slt", |
2329 | "d,v,t", AT, reg, AT); | |
670a50eb | 2330 | } |
3d3c5039 ILT |
2331 | } |
2332 | ||
6e8dda9c | 2333 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
2334 | |
2335 | static void | |
19ed8960 | 2336 | check_absolute_expr (ip, ex) |
3d3c5039 | 2337 | struct mips_cl_insn *ip; |
19ed8960 | 2338 | expressionS *ex; |
3d3c5039 | 2339 | { |
19ed8960 | 2340 | if (ex->X_op != O_constant) |
670a50eb | 2341 | as_warn ("Instruction %s requires absolute expression", ip->insn_mo->name); |
3d3c5039 ILT |
2342 | } |
2343 | ||
ff8716f5 JSC |
2344 | /* Count the leading zeroes by performing a binary chop. This is a |
2345 | bulky bit of source, but performance is a LOT better for the | |
2346 | majority of values than a simple loop to count the bits: | |
2347 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2348 | if ((v) & (1 << (31 - lcnt))) | |
2349 | break; | |
2350 | However it is not code size friendly, and the gain will drop a bit | |
2351 | on certain cached systems. | |
2352 | */ | |
2353 | #define COUNT_TOP_ZEROES(v) \ | |
2354 | (((v) & ~0xffff) == 0 \ | |
2355 | ? ((v) & ~0xff) == 0 \ | |
2356 | ? ((v) & ~0xf) == 0 \ | |
2357 | ? ((v) & ~0x3) == 0 \ | |
2358 | ? ((v) & ~0x1) == 0 \ | |
2359 | ? !(v) \ | |
2360 | ? 32 \ | |
2361 | : 31 \ | |
2362 | : 30 \ | |
2363 | : ((v) & ~0x7) == 0 \ | |
2364 | ? 29 \ | |
2365 | : 28 \ | |
2366 | : ((v) & ~0x3f) == 0 \ | |
2367 | ? ((v) & ~0x1f) == 0 \ | |
2368 | ? 27 \ | |
2369 | : 26 \ | |
2370 | : ((v) & ~0x7f) == 0 \ | |
2371 | ? 25 \ | |
2372 | : 24 \ | |
2373 | : ((v) & ~0xfff) == 0 \ | |
2374 | ? ((v) & ~0x3ff) == 0 \ | |
2375 | ? ((v) & ~0x1ff) == 0 \ | |
2376 | ? 23 \ | |
2377 | : 22 \ | |
2378 | : ((v) & ~0x7ff) == 0 \ | |
2379 | ? 21 \ | |
2380 | : 20 \ | |
2381 | : ((v) & ~0x3fff) == 0 \ | |
2382 | ? ((v) & ~0x1fff) == 0 \ | |
2383 | ? 19 \ | |
2384 | : 18 \ | |
2385 | : ((v) & ~0x7fff) == 0 \ | |
2386 | ? 17 \ | |
2387 | : 16 \ | |
2388 | : ((v) & ~0xffffff) == 0 \ | |
2389 | ? ((v) & ~0xfffff) == 0 \ | |
2390 | ? ((v) & ~0x3ffff) == 0 \ | |
2391 | ? ((v) & ~0x1ffff) == 0 \ | |
2392 | ? 15 \ | |
2393 | : 14 \ | |
2394 | : ((v) & ~0x7ffff) == 0 \ | |
2395 | ? 13 \ | |
2396 | : 12 \ | |
2397 | : ((v) & ~0x3fffff) == 0 \ | |
2398 | ? ((v) & ~0x1fffff) == 0 \ | |
2399 | ? 11 \ | |
2400 | : 10 \ | |
2401 | : ((v) & ~0x7fffff) == 0 \ | |
2402 | ? 9 \ | |
2403 | : 8 \ | |
2404 | : ((v) & ~0xfffffff) == 0 \ | |
2405 | ? ((v) & ~0x3ffffff) == 0 \ | |
2406 | ? ((v) & ~0x1ffffff) == 0 \ | |
2407 | ? 7 \ | |
2408 | : 6 \ | |
2409 | : ((v) & ~0x7ffffff) == 0 \ | |
2410 | ? 5 \ | |
2411 | : 4 \ | |
2412 | : ((v) & ~0x3fffffff) == 0 \ | |
2413 | ? ((v) & ~0x1fffffff) == 0 \ | |
2414 | ? 3 \ | |
2415 | : 2 \ | |
2416 | : ((v) & ~0x7fffffff) == 0 \ | |
2417 | ? 1 \ | |
2418 | : 0) | |
2419 | ||
3d3c5039 ILT |
2420 | /* load_register() |
2421 | * This routine generates the least number of instructions neccessary to load | |
2422 | * an absolute expression value into a register. | |
2423 | */ | |
2424 | static void | |
d8a1c247 | 2425 | load_register (counter, reg, ep, dbl) |
670a50eb | 2426 | int *counter; |
670a50eb ILT |
2427 | int reg; |
2428 | expressionS *ep; | |
d8a1c247 | 2429 | int dbl; |
3d3c5039 | 2430 | { |
d8a1c247 | 2431 | int shift, freg; |
ff8716f5 | 2432 | expressionS hi32, lo32, tmp; |
847a01cd ILT |
2433 | |
2434 | if (ep->X_op != O_big) | |
6e8dda9c | 2435 | { |
847a01cd | 2436 | assert (ep->X_op == O_constant); |
d8a1c247 KR |
2437 | if (ep->X_add_number < 0x8000 |
2438 | && (ep->X_add_number >= 0 | |
2439 | || (ep->X_add_number >= -0x8000 | |
2440 | && (! dbl | |
2441 | || ! ep->X_unsigned | |
2442 | || sizeof (ep->X_add_number) > 4)))) | |
847a01cd ILT |
2443 | { |
2444 | /* We can handle 16 bit signed values with an addiu to | |
2445 | $zero. No need to ever use daddiu here, since $zero and | |
2446 | the result are always correct in 32 bit mode. */ | |
2447 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
2448 | (int) BFD_RELOC_LO16); | |
2449 | return; | |
2450 | } | |
2451 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
2452 | { | |
2453 | /* We can handle 16 bit unsigned values with an ori to | |
2454 | $zero. */ | |
2455 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
2456 | (int) BFD_RELOC_LO16); | |
2457 | return; | |
2458 | } | |
98bfd087 ILT |
2459 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
2460 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
2461 | == ~ (offsetT) 0x7fffffff)) | |
2462 | && (! dbl | |
2463 | || ! ep->X_unsigned | |
2464 | || sizeof (ep->X_add_number) > 4 | |
2465 | || (ep->X_add_number & 0x80000000) == 0)) | |
ff8716f5 | 2466 | || ((mips_isa < 3 || !dbl) |
0267c6c9 | 2467 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)) |
847a01cd ILT |
2468 | { |
2469 | /* 32 bit values require an lui. */ | |
2470 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2471 | (int) BFD_RELOC_HI16); | |
2472 | if ((ep->X_add_number & 0xffff) != 0) | |
2473 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
2474 | (int) BFD_RELOC_LO16); | |
2475 | return; | |
2476 | } | |
6e8dda9c | 2477 | } |
847a01cd ILT |
2478 | |
2479 | /* The value is larger than 32 bits. */ | |
2480 | ||
2481 | if (mips_isa < 3) | |
670a50eb | 2482 | { |
6e8dda9c | 2483 | as_bad ("Number larger than 32 bits"); |
0dd2d296 | 2484 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 2485 | (int) BFD_RELOC_LO16); |
847a01cd | 2486 | return; |
6e8dda9c | 2487 | } |
6e8dda9c | 2488 | |
847a01cd ILT |
2489 | if (ep->X_op != O_big) |
2490 | { | |
6e8dda9c ILT |
2491 | hi32 = *ep; |
2492 | shift = 32; | |
2493 | hi32.X_add_number >>= shift; | |
2494 | hi32.X_add_number &= 0xffffffff; | |
2495 | if ((hi32.X_add_number & 0x80000000) != 0) | |
2496 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
6e8dda9c ILT |
2497 | lo32 = *ep; |
2498 | lo32.X_add_number &= 0xffffffff; | |
670a50eb | 2499 | } |
847a01cd ILT |
2500 | else |
2501 | { | |
2502 | assert (ep->X_add_number > 2); | |
2503 | if (ep->X_add_number == 3) | |
2504 | generic_bignum[3] = 0; | |
2505 | else if (ep->X_add_number > 4) | |
2506 | as_bad ("Number larger than 64 bits"); | |
2507 | lo32.X_op = O_constant; | |
2508 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
2509 | hi32.X_op = O_constant; | |
2510 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
2511 | } | |
2512 | ||
d8a1c247 KR |
2513 | if (hi32.X_add_number == 0) |
2514 | freg = 0; | |
2515 | else | |
2516 | { | |
fb251650 ILT |
2517 | if (hi32.X_add_number == 0xffffffff) |
2518 | { | |
2519 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
2520 | { | |
2521 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", reg, 0, | |
2522 | (int) BFD_RELOC_LO16); | |
2523 | return; | |
2524 | } | |
2525 | if (lo32.X_add_number & 0x80000000) | |
2526 | { | |
2527 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2528 | (int) BFD_RELOC_HI16); | |
2529 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, reg, | |
2530 | (int) BFD_RELOC_LO16); | |
2531 | return; | |
2532 | } | |
2533 | } | |
ff8716f5 JSC |
2534 | |
2535 | /* Check for 16bit shifted constant: */ | |
2536 | shift = 32; | |
2537 | tmp.X_add_number = hi32.X_add_number << shift | lo32.X_add_number; | |
2538 | /* We know that hi32 is non-zero, so start the mask on the first | |
2539 | bit of the hi32 value: */ | |
2540 | shift = 17; | |
2541 | do | |
2542 | { | |
2543 | if ((tmp.X_add_number & ~((offsetT)0xffff << shift)) == 0) | |
2544 | { | |
2545 | tmp.X_op = O_constant; | |
2546 | tmp.X_add_number >>= shift; | |
2547 | macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, | |
2548 | (int) BFD_RELOC_LO16); | |
2549 | macro_build ((char *) NULL, counter, NULL, | |
2550 | (shift >= 32) ? "dsll32" : "dsll", | |
2551 | "d,w,<", reg, reg, (shift >= 32) ? shift - 32 : shift); | |
2552 | return; | |
2553 | } | |
2554 | shift++; | |
2555 | } while (shift <= (64 - 16)); | |
2556 | ||
2557 | freg = 0; | |
2558 | shift = 32; | |
2559 | tmp.X_add_number = hi32.X_add_number << shift | lo32.X_add_number; | |
2560 | while ((tmp.X_add_number & 1) == 0) | |
2561 | { | |
2562 | tmp.X_add_number >>= 1; | |
2563 | freg++; | |
2564 | } | |
2565 | if (((tmp.X_add_number + 1) & tmp.X_add_number) == 0) /* (power-of-2 - 1) */ | |
2566 | { | |
2567 | shift = COUNT_TOP_ZEROES((unsigned int)hi32.X_add_number); | |
2568 | if (shift != 0) | |
2569 | { | |
2570 | tmp.X_op = O_constant; | |
2571 | tmp.X_add_number = (offsetT)-1; | |
2572 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", reg, 0, | |
2573 | (int) BFD_RELOC_LO16); /* set all ones */ | |
2574 | if (freg != 0) | |
2575 | { | |
2576 | freg += shift; | |
2577 | macro_build ((char *) NULL, counter, NULL, | |
2578 | (freg >= 32) ? "dsll32" : "dsll", | |
2579 | "d,w,<", reg, reg, | |
2580 | (freg >= 32) ? freg - 32 : freg); | |
2581 | } | |
2582 | macro_build ((char *) NULL, counter, NULL, (shift >= 32) ? "dsrl32" : "dsrl", | |
2583 | "d,w,<", reg, reg, (shift >= 32) ? shift - 32 : shift); | |
2584 | return; | |
2585 | } | |
2586 | } | |
d8a1c247 KR |
2587 | load_register (counter, reg, &hi32, 0); |
2588 | freg = reg; | |
2589 | } | |
847a01cd | 2590 | if ((lo32.X_add_number & 0xffff0000) == 0) |
d8a1c247 KR |
2591 | { |
2592 | if (freg != 0) | |
2593 | { | |
2594 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
2595 | freg, 0); | |
2596 | freg = reg; | |
2597 | } | |
2598 | } | |
847a01cd ILT |
2599 | else |
2600 | { | |
2601 | expressionS mid16; | |
2602 | ||
fb251650 ILT |
2603 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) |
2604 | { | |
2605 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2606 | (int) BFD_RELOC_HI16); | |
2607 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
ff8716f5 | 2608 | reg, 0); |
fb251650 ILT |
2609 | return; |
2610 | } | |
2611 | ||
d8a1c247 KR |
2612 | if (freg != 0) |
2613 | { | |
2614 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
2615 | freg, 16); | |
2616 | freg = reg; | |
2617 | } | |
847a01cd ILT |
2618 | mid16 = lo32; |
2619 | mid16.X_add_number >>= 16; | |
2620 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
d8a1c247 | 2621 | freg, (int) BFD_RELOC_LO16); |
847a01cd ILT |
2622 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
2623 | reg, 16); | |
d8a1c247 | 2624 | freg = reg; |
847a01cd ILT |
2625 | } |
2626 | if ((lo32.X_add_number & 0xffff) != 0) | |
d8a1c247 | 2627 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
847a01cd | 2628 | (int) BFD_RELOC_LO16); |
3d3c5039 ILT |
2629 | } |
2630 | ||
0dd2d296 ILT |
2631 | /* Load an address into a register. */ |
2632 | ||
2633 | static void | |
2634 | load_address (counter, reg, ep) | |
2635 | int *counter; | |
2636 | int reg; | |
2637 | expressionS *ep; | |
2638 | { | |
2639 | char *p; | |
2640 | ||
2641 | if (ep->X_op != O_constant | |
2642 | && ep->X_op != O_symbol) | |
2643 | { | |
2644 | as_bad ("expression too complex"); | |
2645 | ep->X_op = O_constant; | |
2646 | } | |
2647 | ||
2648 | if (ep->X_op == O_constant) | |
d9aba805 | 2649 | { |
d8a1c247 | 2650 | load_register (counter, reg, ep, 0); |
d9aba805 ILT |
2651 | return; |
2652 | } | |
2653 | ||
2654 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
2655 | { |
2656 | /* If this is a reference to a GP relative symbol, we want | |
2657 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
2658 | Otherwise we want | |
04cb3372 | 2659 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
2660 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
2661 | If we have an addend, we always use the latter form. */ | |
7a15a226 ILT |
2662 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET |
2663 | || nopic_need_relax (ep->X_add_symbol)) | |
0dd2d296 ILT |
2664 | p = NULL; |
2665 | else | |
2666 | { | |
8ea7f4e8 | 2667 | frag_grow (20); |
0dd2d296 ILT |
2668 | macro_build ((char *) NULL, counter, ep, |
2669 | mips_isa < 3 ? "addiu" : "daddiu", | |
2670 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
2671 | p = frag_var (rs_machine_dependent, 8, 0, | |
847a01cd | 2672 | RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros), |
0dd2d296 ILT |
2673 | ep->X_add_symbol, (long) 0, (char *) NULL); |
2674 | } | |
2675 | macro_build_lui (p, counter, ep, reg); | |
2676 | if (p != NULL) | |
2677 | p += 4; | |
2678 | macro_build (p, counter, ep, | |
2679 | mips_isa < 3 ? "addiu" : "daddiu", | |
2680 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2681 | } | |
fb251650 | 2682 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
2683 | { |
2684 | expressionS ex; | |
2685 | ||
2686 | /* If this is a reference to an external symbol, we want | |
2687 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2688 | Otherwise we want | |
2689 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2690 | nop | |
2691 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 2692 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
2693 | ex.X_add_number = ep->X_add_number; |
2694 | ep->X_add_number = 0; | |
8ea7f4e8 | 2695 | frag_grow (20); |
0dd2d296 ILT |
2696 | macro_build ((char *) NULL, counter, ep, |
2697 | mips_isa < 3 ? "lw" : "ld", | |
2698 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
2699 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
2700 | p = frag_var (rs_machine_dependent, 4, 0, | |
2701 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros), | |
2702 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
2703 | macro_build (p, counter, ep, | |
2704 | mips_isa < 3 ? "addiu" : "daddiu", | |
2705 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2706 | if (ex.X_add_number != 0) | |
2707 | { | |
2708 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
2709 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
2710 | ex.X_op = O_constant; | |
fb251650 ILT |
2711 | macro_build ((char *) NULL, counter, &ex, |
2712 | mips_isa < 3 ? "addiu" : "daddiu", | |
2713 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2714 | } | |
2715 | } | |
2716 | else if (mips_pic == SVR4_PIC) | |
2717 | { | |
2718 | expressionS ex; | |
2719 | int off; | |
2720 | ||
2721 | /* This is the large GOT case. If this is a reference to an | |
2722 | external symbol, we want | |
2723 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
2724 | addu $reg,$reg,$gp | |
2725 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
2726 | Otherwise, for a reference to a local symbol, we want | |
2727 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2728 | nop | |
2729 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
2730 | If there is a constant, it must be added in after. */ | |
2731 | ex.X_add_number = ep->X_add_number; | |
2732 | ep->X_add_number = 0; | |
2733 | if (reg_needs_delay (GP)) | |
2734 | off = 4; | |
2735 | else | |
2736 | off = 0; | |
2737 | frag_grow (32); | |
2738 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2739 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
2740 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
2741 | mips_isa < 3 ? "addu" : "daddu", | |
2742 | "d,v,t", reg, reg, GP); | |
2743 | macro_build ((char *) NULL, counter, ep, | |
2744 | mips_isa < 3 ? "lw" : "ld", | |
2745 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); | |
2746 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
2747 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
2748 | mips_warn_about_macros), | |
2749 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
2750 | if (off > 0) | |
2751 | { | |
2752 | /* We need a nop before loading from $gp. This special | |
2753 | check is required because the lui which starts the main | |
2754 | instruction stream does not refer to $gp, and so will not | |
2755 | insert the nop which may be required. */ | |
2756 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
2757 | p += 4; | |
2758 | } | |
2759 | macro_build (p, counter, ep, | |
2760 | mips_isa < 3 ? "lw" : "ld", | |
2761 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
2762 | p += 4; | |
2763 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
2764 | p += 4; | |
2765 | macro_build (p, counter, ep, | |
2766 | mips_isa < 3 ? "addiu" : "daddiu", | |
2767 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2768 | if (ex.X_add_number != 0) | |
2769 | { | |
2770 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
2771 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
2772 | ex.X_op = O_constant; | |
2773 | macro_build ((char *) NULL, counter, &ex, | |
0dd2d296 ILT |
2774 | mips_isa < 3 ? "addiu" : "daddiu", |
2775 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2776 | } | |
d9aba805 ILT |
2777 | } |
2778 | else if (mips_pic == EMBEDDED_PIC) | |
2779 | { | |
2780 | /* We always do | |
2781 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
2782 | */ | |
2783 | macro_build ((char *) NULL, counter, ep, | |
2784 | mips_isa < 3 ? "addiu" : "daddiu", | |
2785 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
2786 | } | |
2787 | else | |
2788 | abort (); | |
0dd2d296 ILT |
2789 | } |
2790 | ||
3d3c5039 ILT |
2791 | /* |
2792 | * Build macros | |
2793 | * This routine implements the seemingly endless macro or synthesized | |
2794 | * instructions and addressing modes in the mips assembly language. Many | |
2795 | * of these macros are simple and are similar to each other. These could | |
2796 | * probably be handled by some kind of table or grammer aproach instead of | |
2797 | * this verbose method. Others are not simple macros but are more like | |
2798 | * optimizing code generation. | |
2799 | * One interesting optimization is when several store macros appear | |
2800 | * consecutivly that would load AT with the upper half of the same address. | |
2801 | * The ensuing load upper instructions are ommited. This implies some kind | |
2802 | * of global optimization. We currently only optimize within a single macro. | |
2803 | * For many of the load and store macros if the address is specified as a | |
2804 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
2805 | * first load register 'at' with zero and use it as the base register. The | |
2806 | * mips assembler simply uses register $zero. Just one tiny optimization | |
2807 | * we're missing. | |
2808 | */ | |
2809 | static void | |
2810 | macro (ip) | |
2811 | struct mips_cl_insn *ip; | |
2812 | { | |
670a50eb ILT |
2813 | register int treg, sreg, dreg, breg; |
2814 | int tempreg; | |
2815 | int mask; | |
2816 | int icnt = 0; | |
2817 | int used_at; | |
670a50eb ILT |
2818 | expressionS expr1; |
2819 | const char *s; | |
8358c818 | 2820 | const char *s2; |
670a50eb | 2821 | const char *fmt; |
8358c818 ILT |
2822 | int likely = 0; |
2823 | int dbl = 0; | |
2824 | int coproc = 0; | |
b2b8c24e | 2825 | int lr = 0; |
6e8dda9c | 2826 | offsetT maxnum; |
adcf2b9d | 2827 | int off; |
9226253a | 2828 | bfd_reloc_code_real_type r; |
0dd2d296 | 2829 | char *p; |
55933a58 | 2830 | int hold_mips_optimize; |
670a50eb | 2831 | |
cc5703cd ILT |
2832 | assert (! mips16); |
2833 | ||
670a50eb ILT |
2834 | treg = (ip->insn_opcode >> 16) & 0x1f; |
2835 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
2836 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
2837 | mask = ip->insn_mo->mask; | |
2838 | ||
5ac34ac3 ILT |
2839 | expr1.X_op = O_constant; |
2840 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
2841 | expr1.X_add_symbol = NULL; |
2842 | expr1.X_add_number = 1; | |
2843 | ||
2844 | switch (mask) | |
2845 | { | |
6e8dda9c ILT |
2846 | case M_DABS: |
2847 | dbl = 1; | |
3d3c5039 | 2848 | case M_ABS: |
6e8dda9c ILT |
2849 | /* bgez $a0,.+12 |
2850 | move v0,$a0 | |
2851 | sub v0,$zero,$a0 | |
2852 | */ | |
3d3c5039 | 2853 | |
becfe05e ILT |
2854 | mips_emit_delays (); |
2855 | ++mips_noreorder; | |
0dd2d296 | 2856 | mips_any_noreorder = 1; |
3d3c5039 | 2857 | |
670a50eb | 2858 | expr1.X_add_number = 8; |
0dd2d296 | 2859 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 2860 | if (dreg == sreg) |
0dd2d296 | 2861 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 2862 | else |
0dd2d296 ILT |
2863 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
2864 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
2865 | dbl ? "dsub" : "sub", |
2866 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 2867 | |
becfe05e | 2868 | --mips_noreorder; |
670a50eb | 2869 | return; |
3d3c5039 ILT |
2870 | |
2871 | case M_ADD_I: | |
8358c818 ILT |
2872 | s = "addi"; |
2873 | s2 = "add"; | |
2874 | goto do_addi; | |
3d3c5039 | 2875 | case M_ADDU_I: |
8358c818 ILT |
2876 | s = "addiu"; |
2877 | s2 = "addu"; | |
2878 | goto do_addi; | |
2879 | case M_DADD_I: | |
6e8dda9c | 2880 | dbl = 1; |
8358c818 ILT |
2881 | s = "daddi"; |
2882 | s2 = "dadd"; | |
2883 | goto do_addi; | |
2884 | case M_DADDU_I: | |
6e8dda9c | 2885 | dbl = 1; |
8358c818 ILT |
2886 | s = "daddiu"; |
2887 | s2 = "daddu"; | |
2888 | do_addi: | |
6e8dda9c | 2889 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 2890 | { |
0dd2d296 | 2891 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 2892 | (int) BFD_RELOC_LO16); |
670a50eb | 2893 | return; |
3d3c5039 | 2894 | } |
d8a1c247 | 2895 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 2896 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 2897 | break; |
3d3c5039 ILT |
2898 | |
2899 | case M_AND_I: | |
6e8dda9c ILT |
2900 | s = "andi"; |
2901 | s2 = "and"; | |
2902 | goto do_bit; | |
3d3c5039 | 2903 | case M_OR_I: |
6e8dda9c ILT |
2904 | s = "ori"; |
2905 | s2 = "or"; | |
2906 | goto do_bit; | |
3d3c5039 | 2907 | case M_NOR_I: |
6e8dda9c ILT |
2908 | s = ""; |
2909 | s2 = "nor"; | |
2910 | goto do_bit; | |
3d3c5039 | 2911 | case M_XOR_I: |
6e8dda9c ILT |
2912 | s = "xori"; |
2913 | s2 = "xor"; | |
2914 | do_bit: | |
2915 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) | |
670a50eb | 2916 | { |
6e8dda9c | 2917 | if (mask != M_NOR_I) |
0dd2d296 ILT |
2918 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
2919 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 2920 | else |
670a50eb | 2921 | { |
0dd2d296 ILT |
2922 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
2923 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 2924 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 2925 | treg, treg, 0); |
3d3c5039 | 2926 | } |
6e8dda9c | 2927 | return; |
3d3c5039 | 2928 | } |
6e8dda9c | 2929 | |
d8a1c247 | 2930 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 2931 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 2932 | break; |
3d3c5039 ILT |
2933 | |
2934 | case M_BEQ_I: | |
8358c818 ILT |
2935 | s = "beq"; |
2936 | goto beq_i; | |
2937 | case M_BEQL_I: | |
2938 | s = "beql"; | |
2939 | likely = 1; | |
2940 | goto beq_i; | |
3d3c5039 | 2941 | case M_BNE_I: |
8358c818 ILT |
2942 | s = "bne"; |
2943 | goto beq_i; | |
2944 | case M_BNEL_I: | |
2945 | s = "bnel"; | |
2946 | likely = 1; | |
2947 | beq_i: | |
670a50eb ILT |
2948 | if (imm_expr.X_add_number == 0) |
2949 | { | |
0dd2d296 ILT |
2950 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
2951 | 0); | |
670a50eb ILT |
2952 | return; |
2953 | } | |
d8a1c247 | 2954 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 2955 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 2956 | break; |
3d3c5039 | 2957 | |
8358c818 ILT |
2958 | case M_BGEL: |
2959 | likely = 1; | |
3d3c5039 | 2960 | case M_BGE: |
670a50eb ILT |
2961 | if (treg == 0) |
2962 | { | |
0dd2d296 | 2963 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2964 | likely ? "bgezl" : "bgez", |
2965 | "s,p", sreg); | |
670a50eb | 2966 | return; |
3d3c5039 | 2967 | } |
9a7d824a ILT |
2968 | if (sreg == 0) |
2969 | { | |
0dd2d296 | 2970 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2971 | likely ? "blezl" : "blez", |
2972 | "s,p", treg); | |
9a7d824a ILT |
2973 | return; |
2974 | } | |
0dd2d296 ILT |
2975 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
2976 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2977 | likely ? "beql" : "beq", |
2978 | "s,t,p", AT, 0); | |
670a50eb | 2979 | break; |
3d3c5039 | 2980 | |
8358c818 ILT |
2981 | case M_BGTL_I: |
2982 | likely = 1; | |
3d3c5039 | 2983 | case M_BGT_I: |
9a7d824a | 2984 | /* check for > max integer */ |
6e8dda9c ILT |
2985 | maxnum = 0x7fffffff; |
2986 | if (mips_isa >= 3) | |
2987 | { | |
2988 | maxnum <<= 16; | |
2989 | maxnum |= 0xffff; | |
2990 | maxnum <<= 16; | |
2991 | maxnum |= 0xffff; | |
2992 | } | |
7b777690 ILT |
2993 | if (imm_expr.X_add_number >= maxnum |
2994 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
2995 | { |
2996 | do_false: | |
2997 | /* result is always false */ | |
8358c818 ILT |
2998 | if (! likely) |
2999 | { | |
3000 | as_warn ("Branch %s is always false (nop)", ip->insn_mo->name); | |
0dd2d296 | 3001 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
3002 | } |
3003 | else | |
3004 | { | |
3005 | as_warn ("Branch likely %s is always false", ip->insn_mo->name); | |
0dd2d296 ILT |
3006 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
3007 | "s,t,p", 0, 0); | |
8358c818 | 3008 | } |
9a7d824a ILT |
3009 | return; |
3010 | } | |
670a50eb ILT |
3011 | imm_expr.X_add_number++; |
3012 | /* FALLTHROUGH */ | |
3d3c5039 | 3013 | case M_BGE_I: |
8358c818 ILT |
3014 | case M_BGEL_I: |
3015 | if (mask == M_BGEL_I) | |
3016 | likely = 1; | |
670a50eb ILT |
3017 | if (imm_expr.X_add_number == 0) |
3018 | { | |
0dd2d296 | 3019 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3020 | likely ? "bgezl" : "bgez", |
3021 | "s,p", sreg); | |
670a50eb | 3022 | return; |
3d3c5039 | 3023 | } |
670a50eb ILT |
3024 | if (imm_expr.X_add_number == 1) |
3025 | { | |
0dd2d296 | 3026 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3027 | likely ? "bgtzl" : "bgtz", |
3028 | "s,p", sreg); | |
670a50eb | 3029 | return; |
3d3c5039 | 3030 | } |
6e8dda9c ILT |
3031 | maxnum = 0x7fffffff; |
3032 | if (mips_isa >= 3) | |
3033 | { | |
3034 | maxnum <<= 16; | |
3035 | maxnum |= 0xffff; | |
3036 | maxnum <<= 16; | |
3037 | maxnum |= 0xffff; | |
3038 | } | |
3039 | maxnum = - maxnum - 1; | |
7b777690 ILT |
3040 | if (imm_expr.X_add_number <= maxnum |
3041 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3042 | { |
3043 | do_true: | |
3044 | /* result is always true */ | |
3045 | as_warn ("Branch %s is always true", ip->insn_mo->name); | |
0dd2d296 | 3046 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
3047 | return; |
3048 | } | |
6e8dda9c | 3049 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3050 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3051 | likely ? "beql" : "beq", |
3052 | "s,t,p", AT, 0); | |
670a50eb | 3053 | break; |
3d3c5039 | 3054 | |
8358c818 ILT |
3055 | case M_BGEUL: |
3056 | likely = 1; | |
3d3c5039 | 3057 | case M_BGEU: |
670a50eb | 3058 | if (treg == 0) |
9a7d824a ILT |
3059 | goto do_true; |
3060 | if (sreg == 0) | |
670a50eb | 3061 | { |
0dd2d296 | 3062 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3063 | likely ? "beql" : "beq", |
3064 | "s,t,p", 0, treg); | |
670a50eb | 3065 | return; |
3d3c5039 | 3066 | } |
0dd2d296 ILT |
3067 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3068 | treg); | |
3069 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3070 | likely ? "beql" : "beq", |
3071 | "s,t,p", AT, 0); | |
670a50eb | 3072 | break; |
3d3c5039 | 3073 | |
8358c818 ILT |
3074 | case M_BGTUL_I: |
3075 | likely = 1; | |
9a7d824a | 3076 | case M_BGTU_I: |
6e8dda9c | 3077 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
3078 | goto do_false; |
3079 | imm_expr.X_add_number++; | |
3080 | /* FALLTHROUGH */ | |
3d3c5039 | 3081 | case M_BGEU_I: |
8358c818 ILT |
3082 | case M_BGEUL_I: |
3083 | if (mask == M_BGEUL_I) | |
3084 | likely = 1; | |
670a50eb | 3085 | if (imm_expr.X_add_number == 0) |
9a7d824a | 3086 | goto do_true; |
670a50eb ILT |
3087 | if (imm_expr.X_add_number == 1) |
3088 | { | |
0dd2d296 | 3089 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3090 | likely ? "bnel" : "bne", |
3091 | "s,t,p", sreg, 0); | |
670a50eb | 3092 | return; |
3d3c5039 | 3093 | } |
6e8dda9c | 3094 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3095 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3096 | likely ? "beql" : "beq", |
3097 | "s,t,p", AT, 0); | |
670a50eb | 3098 | break; |
3d3c5039 | 3099 | |
8358c818 ILT |
3100 | case M_BGTL: |
3101 | likely = 1; | |
3d3c5039 | 3102 | case M_BGT: |
670a50eb ILT |
3103 | if (treg == 0) |
3104 | { | |
0dd2d296 | 3105 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3106 | likely ? "bgtzl" : "bgtz", |
3107 | "s,p", sreg); | |
670a50eb | 3108 | return; |
3d3c5039 | 3109 | } |
9a7d824a ILT |
3110 | if (sreg == 0) |
3111 | { | |
0dd2d296 | 3112 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3113 | likely ? "bltzl" : "bltz", |
3114 | "s,p", treg); | |
9a7d824a ILT |
3115 | return; |
3116 | } | |
0dd2d296 ILT |
3117 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3118 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3119 | likely ? "bnel" : "bne", |
3120 | "s,t,p", AT, 0); | |
670a50eb | 3121 | break; |
3d3c5039 | 3122 | |
8358c818 ILT |
3123 | case M_BGTUL: |
3124 | likely = 1; | |
3d3c5039 | 3125 | case M_BGTU: |
670a50eb ILT |
3126 | if (treg == 0) |
3127 | { | |
0dd2d296 | 3128 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3129 | likely ? "bnel" : "bne", |
3130 | "s,t,p", sreg, 0); | |
670a50eb | 3131 | return; |
3d3c5039 | 3132 | } |
9a7d824a ILT |
3133 | if (sreg == 0) |
3134 | goto do_false; | |
0dd2d296 ILT |
3135 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3136 | sreg); | |
3137 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3138 | likely ? "bnel" : "bne", |
3139 | "s,t,p", AT, 0); | |
670a50eb | 3140 | break; |
3d3c5039 | 3141 | |
8358c818 ILT |
3142 | case M_BLEL: |
3143 | likely = 1; | |
3d3c5039 | 3144 | case M_BLE: |
670a50eb ILT |
3145 | if (treg == 0) |
3146 | { | |
0dd2d296 | 3147 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3148 | likely ? "blezl" : "blez", |
3149 | "s,p", sreg); | |
670a50eb ILT |
3150 | return; |
3151 | } | |
9a7d824a ILT |
3152 | if (sreg == 0) |
3153 | { | |
0dd2d296 | 3154 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3155 | likely ? "bgezl" : "bgez", |
3156 | "s,p", treg); | |
9a7d824a ILT |
3157 | return; |
3158 | } | |
0dd2d296 ILT |
3159 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3160 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3161 | likely ? "beql" : "beq", |
3162 | "s,t,p", AT, 0); | |
670a50eb | 3163 | break; |
3d3c5039 | 3164 | |
8358c818 ILT |
3165 | case M_BLEL_I: |
3166 | likely = 1; | |
3d3c5039 | 3167 | case M_BLE_I: |
6e8dda9c ILT |
3168 | maxnum = 0x7fffffff; |
3169 | if (mips_isa >= 3) | |
3170 | { | |
3171 | maxnum <<= 16; | |
3172 | maxnum |= 0xffff; | |
3173 | maxnum <<= 16; | |
3174 | maxnum |= 0xffff; | |
3175 | } | |
7b777690 ILT |
3176 | if (imm_expr.X_add_number >= maxnum |
3177 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3178 | goto do_true; |
3179 | imm_expr.X_add_number++; | |
3180 | /* FALLTHROUGH */ | |
9a7d824a | 3181 | case M_BLT_I: |
8358c818 ILT |
3182 | case M_BLTL_I: |
3183 | if (mask == M_BLTL_I) | |
3184 | likely = 1; | |
670a50eb ILT |
3185 | if (imm_expr.X_add_number == 0) |
3186 | { | |
0dd2d296 | 3187 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3188 | likely ? "bltzl" : "bltz", |
3189 | "s,p", sreg); | |
670a50eb ILT |
3190 | return; |
3191 | } | |
9a7d824a | 3192 | if (imm_expr.X_add_number == 1) |
670a50eb | 3193 | { |
0dd2d296 | 3194 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3195 | likely ? "blezl" : "blez", |
3196 | "s,p", sreg); | |
670a50eb ILT |
3197 | return; |
3198 | } | |
6e8dda9c | 3199 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3200 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3201 | likely ? "bnel" : "bne", |
3202 | "s,t,p", AT, 0); | |
670a50eb | 3203 | break; |
3d3c5039 | 3204 | |
8358c818 ILT |
3205 | case M_BLEUL: |
3206 | likely = 1; | |
3d3c5039 | 3207 | case M_BLEU: |
670a50eb ILT |
3208 | if (treg == 0) |
3209 | { | |
0dd2d296 | 3210 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3211 | likely ? "beql" : "beq", |
3212 | "s,t,p", sreg, 0); | |
670a50eb | 3213 | return; |
3d3c5039 | 3214 | } |
9a7d824a ILT |
3215 | if (sreg == 0) |
3216 | goto do_true; | |
0dd2d296 ILT |
3217 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3218 | sreg); | |
3219 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3220 | likely ? "beql" : "beq", |
3221 | "s,t,p", AT, 0); | |
670a50eb | 3222 | break; |
3d3c5039 | 3223 | |
8358c818 ILT |
3224 | case M_BLEUL_I: |
3225 | likely = 1; | |
3d3c5039 | 3226 | case M_BLEU_I: |
6e8dda9c | 3227 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
3228 | goto do_true; |
3229 | imm_expr.X_add_number++; | |
3230 | /* FALLTHROUGH */ | |
9a7d824a | 3231 | case M_BLTU_I: |
8358c818 ILT |
3232 | case M_BLTUL_I: |
3233 | if (mask == M_BLTUL_I) | |
3234 | likely = 1; | |
670a50eb | 3235 | if (imm_expr.X_add_number == 0) |
9a7d824a ILT |
3236 | goto do_false; |
3237 | if (imm_expr.X_add_number == 1) | |
670a50eb | 3238 | { |
0dd2d296 | 3239 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3240 | likely ? "beql" : "beq", |
3241 | "s,t,p", sreg, 0); | |
670a50eb | 3242 | return; |
3d3c5039 | 3243 | } |
6e8dda9c | 3244 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3245 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3246 | likely ? "bnel" : "bne", |
3247 | "s,t,p", AT, 0); | |
670a50eb | 3248 | break; |
3d3c5039 | 3249 | |
8358c818 ILT |
3250 | case M_BLTL: |
3251 | likely = 1; | |
3d3c5039 | 3252 | case M_BLT: |
670a50eb ILT |
3253 | if (treg == 0) |
3254 | { | |
0dd2d296 | 3255 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3256 | likely ? "bltzl" : "bltz", |
3257 | "s,p", sreg); | |
670a50eb | 3258 | return; |
3d3c5039 | 3259 | } |
9a7d824a | 3260 | if (sreg == 0) |
670a50eb | 3261 | { |
0dd2d296 | 3262 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3263 | likely ? "bgtzl" : "bgtz", |
3264 | "s,p", treg); | |
670a50eb | 3265 | return; |
3d3c5039 | 3266 | } |
0dd2d296 ILT |
3267 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3268 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3269 | likely ? "bnel" : "bne", |
3270 | "s,t,p", AT, 0); | |
670a50eb | 3271 | break; |
3d3c5039 | 3272 | |
8358c818 ILT |
3273 | case M_BLTUL: |
3274 | likely = 1; | |
3d3c5039 | 3275 | case M_BLTU: |
670a50eb | 3276 | if (treg == 0) |
9a7d824a ILT |
3277 | goto do_false; |
3278 | if (sreg == 0) | |
670a50eb | 3279 | { |
0dd2d296 | 3280 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3281 | likely ? "bnel" : "bne", |
3282 | "s,t,p", 0, treg); | |
670a50eb ILT |
3283 | return; |
3284 | } | |
0dd2d296 ILT |
3285 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3286 | treg); | |
3287 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3288 | likely ? "bnel" : "bne", |
3289 | "s,t,p", AT, 0); | |
670a50eb | 3290 | break; |
3d3c5039 | 3291 | |
8358c818 ILT |
3292 | case M_DDIV_3: |
3293 | dbl = 1; | |
3d3c5039 | 3294 | case M_DIV_3: |
8358c818 ILT |
3295 | s = "mflo"; |
3296 | goto do_div3; | |
3297 | case M_DREM_3: | |
3298 | dbl = 1; | |
3d3c5039 | 3299 | case M_REM_3: |
8358c818 ILT |
3300 | s = "mfhi"; |
3301 | do_div3: | |
670a50eb ILT |
3302 | if (treg == 0) |
3303 | { | |
3304 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3305 | if (mips_trap) |
3306 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3307 | else | |
3308 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3309 | return; |
3310 | } | |
3311 | ||
becfe05e ILT |
3312 | mips_emit_delays (); |
3313 | ++mips_noreorder; | |
0dd2d296 ILT |
3314 | mips_any_noreorder = 1; |
3315 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 | 3316 | dbl ? "ddiv" : "div", |
ff3a5c18 | 3317 | "z,s,t", sreg, treg); |
8ea7f4e8 ILT |
3318 | if (mips_trap) |
3319 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3320 | else | |
3321 | { | |
3322 | expr1.X_add_number = 8; | |
3323 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3324 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3325 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3326 | } | |
670a50eb | 3327 | expr1.X_add_number = -1; |
0dd2d296 | 3328 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 3329 | dbl ? "daddiu" : "addiu", |
9226253a | 3330 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 3331 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 3332 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
3333 | if (dbl) |
3334 | { | |
3335 | expr1.X_add_number = 1; | |
0dd2d296 | 3336 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 3337 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
3338 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
3339 | 31); | |
8358c818 ILT |
3340 | } |
3341 | else | |
3342 | { | |
3343 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
3344 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
3345 | (int) BFD_RELOC_HI16); | |
8358c818 | 3346 | } |
8ea7f4e8 ILT |
3347 | if (mips_trap) |
3348 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
3349 | else | |
3350 | { | |
3351 | expr1.X_add_number = 8; | |
3352 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
3353 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3354 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
3355 | } | |
becfe05e | 3356 | --mips_noreorder; |
0dd2d296 | 3357 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 3358 | break; |
3d3c5039 ILT |
3359 | |
3360 | case M_DIV_3I: | |
8358c818 ILT |
3361 | s = "div"; |
3362 | s2 = "mflo"; | |
3363 | goto do_divi; | |
3d3c5039 | 3364 | case M_DIVU_3I: |
8358c818 ILT |
3365 | s = "divu"; |
3366 | s2 = "mflo"; | |
3367 | goto do_divi; | |
3d3c5039 | 3368 | case M_REM_3I: |
8358c818 ILT |
3369 | s = "div"; |
3370 | s2 = "mfhi"; | |
3371 | goto do_divi; | |
3d3c5039 | 3372 | case M_REMU_3I: |
8358c818 ILT |
3373 | s = "divu"; |
3374 | s2 = "mfhi"; | |
3375 | goto do_divi; | |
3376 | case M_DDIV_3I: | |
3377 | dbl = 1; | |
3378 | s = "ddiv"; | |
3379 | s2 = "mflo"; | |
3380 | goto do_divi; | |
3381 | case M_DDIVU_3I: | |
3382 | dbl = 1; | |
3383 | s = "ddivu"; | |
3384 | s2 = "mflo"; | |
3385 | goto do_divi; | |
3386 | case M_DREM_3I: | |
3387 | dbl = 1; | |
3388 | s = "ddiv"; | |
3389 | s2 = "mfhi"; | |
3390 | goto do_divi; | |
3391 | case M_DREMU_3I: | |
3392 | dbl = 1; | |
3393 | s = "ddivu"; | |
3394 | s2 = "mfhi"; | |
3395 | do_divi: | |
670a50eb ILT |
3396 | if (imm_expr.X_add_number == 0) |
3397 | { | |
3398 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3399 | if (mips_trap) |
3400 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3401 | else | |
3402 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3403 | return; |
3404 | } | |
3405 | if (imm_expr.X_add_number == 1) | |
3406 | { | |
8358c818 | 3407 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
3408 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
3409 | sreg); | |
3d3c5039 | 3410 | else |
0dd2d296 | 3411 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
3412 | return; |
3413 | } | |
8358c818 ILT |
3414 | if (imm_expr.X_add_number == -1 |
3415 | && s[strlen (s) - 1] != 'u') | |
3416 | { | |
3417 | if (strcmp (s2, "mflo") == 0) | |
3418 | { | |
3419 | if (dbl) | |
0dd2d296 ILT |
3420 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
3421 | sreg); | |
8358c818 | 3422 | else |
0dd2d296 ILT |
3423 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
3424 | sreg); | |
8358c818 ILT |
3425 | } |
3426 | else | |
0dd2d296 | 3427 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
3428 | return; |
3429 | } | |
3d3c5039 | 3430 | |
d8a1c247 | 3431 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 ILT |
3432 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
3433 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
3434 | break; |
3435 | ||
3436 | case M_DIVU_3: | |
8358c818 ILT |
3437 | s = "divu"; |
3438 | s2 = "mflo"; | |
3439 | goto do_divu3; | |
670a50eb | 3440 | case M_REMU_3: |
8358c818 ILT |
3441 | s = "divu"; |
3442 | s2 = "mfhi"; | |
3443 | goto do_divu3; | |
3444 | case M_DDIVU_3: | |
3445 | s = "ddivu"; | |
3446 | s2 = "mflo"; | |
3447 | goto do_divu3; | |
3448 | case M_DREMU_3: | |
3449 | s = "ddivu"; | |
3450 | s2 = "mfhi"; | |
3451 | do_divu3: | |
becfe05e ILT |
3452 | mips_emit_delays (); |
3453 | ++mips_noreorder; | |
0dd2d296 ILT |
3454 | mips_any_noreorder = 1; |
3455 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
8ea7f4e8 ILT |
3456 | if (mips_trap) |
3457 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3458 | else | |
3459 | { | |
3460 | expr1.X_add_number = 8; | |
3461 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3462 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3463 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3464 | } | |
becfe05e | 3465 | --mips_noreorder; |
0dd2d296 | 3466 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 3467 | return; |
3d3c5039 | 3468 | |
d8a1c247 KR |
3469 | case M_DLA_AB: |
3470 | dbl = 1; | |
0dd2d296 | 3471 | case M_LA_AB: |
d9aba805 ILT |
3472 | /* Load the address of a symbol into a register. If breg is not |
3473 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
3474 | |
3475 | /* When generating embedded PIC code, we permit expressions of | |
3476 | the form | |
3477 | la $4,foo-bar | |
3478 | where bar is an address in the .text section. These are used | |
3479 | when getting the addresses of functions. We don't permit | |
3480 | X_add_number to be non-zero, because if the symbol is | |
3481 | external the relaxing code needs to know that any addend is | |
3482 | purely the offset to X_op_symbol. */ | |
3483 | if (mips_pic == EMBEDDED_PIC | |
3484 | && offset_expr.X_op == O_subtract | |
3485 | && now_seg == text_section | |
847a01cd ILT |
3486 | && (offset_expr.X_op_symbol->sy_value.X_op == O_constant |
3487 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
3488 | : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol | |
3489 | && (S_GET_SEGMENT (offset_expr.X_op_symbol | |
3490 | ->sy_value.X_add_symbol) | |
3491 | == text_section))) | |
ecd4ca1c ILT |
3492 | && breg == 0 |
3493 | && offset_expr.X_add_number == 0) | |
3494 | { | |
3495 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3496 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
3497 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3498 | mips_isa < 3 ? "addiu" : "daddiu", | |
3499 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); | |
3500 | return; | |
3501 | } | |
3502 | ||
0dd2d296 ILT |
3503 | if (offset_expr.X_op != O_symbol |
3504 | && offset_expr.X_op != O_constant) | |
670a50eb | 3505 | { |
0dd2d296 ILT |
3506 | as_bad ("expression too complex"); |
3507 | offset_expr.X_op = O_constant; | |
3508 | } | |
3509 | ||
3510 | if (treg == breg) | |
3511 | { | |
3512 | tempreg = AT; | |
3513 | used_at = 1; | |
3d3c5039 | 3514 | } |
670a50eb ILT |
3515 | else |
3516 | { | |
0dd2d296 ILT |
3517 | tempreg = treg; |
3518 | used_at = 0; | |
670a50eb | 3519 | } |
3d3c5039 | 3520 | |
5ac34ac3 | 3521 | if (offset_expr.X_op == O_constant) |
d8a1c247 | 3522 | load_register (&icnt, tempreg, &offset_expr, dbl); |
d9aba805 | 3523 | else if (mips_pic == NO_PIC) |
670a50eb | 3524 | { |
0dd2d296 ILT |
3525 | /* If this is a reference to an GP relative symbol, we want |
3526 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3527 | Otherwise we want | |
3528 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
3529 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3530 | If we have a constant, we need two instructions anyhow, | |
3531 | so we may as well always use the latter form. */ | |
7a15a226 | 3532 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 3533 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
3534 | p = NULL; |
3535 | else | |
3536 | { | |
8ea7f4e8 | 3537 | frag_grow (20); |
0dd2d296 ILT |
3538 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3539 | mips_isa < 3 ? "addiu" : "daddiu", | |
3540 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3541 | p = frag_var (rs_machine_dependent, 8, 0, | |
3542 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3543 | mips_warn_about_macros), | |
3544 | offset_expr.X_add_symbol, (long) 0, | |
3545 | (char *) NULL); | |
3546 | } | |
3547 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
3548 | if (p != NULL) | |
3549 | p += 4; | |
3550 | macro_build (p, &icnt, &offset_expr, | |
6e8dda9c | 3551 | mips_isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3552 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
3553 | } | |
fb251650 | 3554 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3555 | { |
3556 | /* If this is a reference to an external symbol, and there | |
3557 | is no constant, we want | |
3558 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3559 | For a local symbol, we want | |
3560 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3561 | nop | |
3562 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3563 | ||
3564 | If we have a small constant, and this is a reference to | |
3565 | an external symbol, we want | |
3566 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3567 | nop | |
3568 | addiu $tempreg,$tempreg,<constant> | |
3569 | For a local symbol, we want the same instruction | |
3570 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
3571 | addiu instruction. | |
3572 | ||
3573 | If we have a large constant, and this is a reference to | |
3574 | an external symbol, we want | |
3575 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3576 | lui $at,<hiconstant> | |
3577 | addiu $at,$at,<loconstant> | |
3578 | addu $tempreg,$tempreg,$at | |
3579 | For a local symbol, we want the same instruction | |
3580 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
3581 | addiu instruction. */ | |
3582 | expr1.X_add_number = offset_expr.X_add_number; | |
3583 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 3584 | frag_grow (32); |
0dd2d296 | 3585 | macro_build ((char *) NULL, &icnt, &offset_expr, |
d8a1c247 | 3586 | dbl ? "ld" : "lw", |
0dd2d296 ILT |
3587 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3588 | if (expr1.X_add_number == 0) | |
3589 | { | |
3590 | int off; | |
3591 | ||
3592 | if (breg == 0) | |
3593 | off = 0; | |
3594 | else | |
3595 | { | |
3596 | /* We're going to put in an addu instruction using | |
3597 | tempreg, so we may as well insert the nop right | |
3598 | now. */ | |
3599 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3600 | "nop", ""); | |
3601 | off = 4; | |
3602 | } | |
3603 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
3604 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
3605 | (breg == 0 | |
3606 | ? mips_warn_about_macros | |
3607 | : 0)), | |
3608 | offset_expr.X_add_symbol, (long) 0, | |
3609 | (char *) NULL); | |
3610 | if (breg == 0) | |
3611 | { | |
3612 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3613 | p += 4; | |
3614 | } | |
3615 | macro_build (p, &icnt, &expr1, | |
3616 | mips_isa < 3 ? "addiu" : "daddiu", | |
3617 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3618 | /* FIXME: If breg == 0, and the next instruction uses | |
3619 | $tempreg, then if this variant case is used an extra | |
3620 | nop will be generated. */ | |
3621 | } | |
3622 | else if (expr1.X_add_number >= -0x8000 | |
3623 | && expr1.X_add_number < 0x8000) | |
3624 | { | |
3625 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3626 | "nop", ""); | |
3627 | macro_build ((char *) NULL, &icnt, &expr1, | |
3628 | mips_isa < 3 ? "addiu" : "daddiu", | |
3629 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3630 | (void) frag_var (rs_machine_dependent, 0, 0, | |
3631 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
3632 | offset_expr.X_add_symbol, (long) 0, | |
3633 | (char *) NULL); | |
3634 | } | |
3635 | else | |
3636 | { | |
3637 | int off1; | |
3638 | ||
3639 | /* If we are going to add in a base register, and the | |
3640 | target register and the base register are the same, | |
3641 | then we are using AT as a temporary register. Since | |
3642 | we want to load the constant into AT, we add our | |
3643 | current AT (from the global offset table) and the | |
3644 | register into the register now, and pretend we were | |
3645 | not using a base register. */ | |
3646 | if (breg != treg) | |
3647 | off1 = 0; | |
3648 | else | |
3649 | { | |
3650 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3651 | "nop", ""); | |
3652 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3653 | mips_isa < 3 ? "addu" : "daddu", | |
3654 | "d,v,t", treg, AT, breg); | |
3655 | breg = 0; | |
3656 | tempreg = treg; | |
3657 | off1 = -8; | |
3658 | } | |
3659 | ||
55933a58 ILT |
3660 | /* Set mips_optimize around the lui instruction to avoid |
3661 | inserting an unnecessary nop after the lw. */ | |
3662 | hold_mips_optimize = mips_optimize; | |
3663 | mips_optimize = 2; | |
0dd2d296 | 3664 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
3665 | mips_optimize = hold_mips_optimize; |
3666 | ||
0dd2d296 ILT |
3667 | macro_build ((char *) NULL, &icnt, &expr1, |
3668 | mips_isa < 3 ? "addiu" : "daddiu", | |
3669 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
3670 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3671 | mips_isa < 3 ? "addu" : "daddu", | |
3672 | "d,v,t", tempreg, tempreg, AT); | |
3673 | (void) frag_var (rs_machine_dependent, 0, 0, | |
3674 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
3675 | offset_expr.X_add_symbol, (long) 0, | |
3676 | (char *) NULL); | |
3677 | used_at = 1; | |
3678 | } | |
670a50eb | 3679 | } |
fb251650 ILT |
3680 | else if (mips_pic == SVR4_PIC) |
3681 | { | |
3682 | int gpdel; | |
3683 | ||
3684 | /* This is the large GOT case. If this is a reference to an | |
3685 | external symbol, and there is no constant, we want | |
3686 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3687 | addu $tempreg,$tempreg,$gp | |
3688 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3689 | For a local symbol, we want | |
3690 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3691 | nop | |
3692 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3693 | ||
3694 | If we have a small constant, and this is a reference to | |
3695 | an external symbol, we want | |
3696 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3697 | addu $tempreg,$tempreg,$gp | |
3698 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3699 | nop | |
3700 | addiu $tempreg,$tempreg,<constant> | |
3701 | For a local symbol, we want | |
3702 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3703 | nop | |
3704 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
3705 | ||
3706 | If we have a large constant, and this is a reference to | |
3707 | an external symbol, we want | |
3708 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3709 | addu $tempreg,$tempreg,$gp | |
3710 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3711 | lui $at,<hiconstant> | |
3712 | addiu $at,$at,<loconstant> | |
3713 | addu $tempreg,$tempreg,$at | |
3714 | For a local symbol, we want | |
3715 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3716 | lui $at,<hiconstant> | |
3717 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
3718 | addu $tempreg,$tempreg,$at | |
3719 | */ | |
3720 | expr1.X_add_number = offset_expr.X_add_number; | |
3721 | offset_expr.X_add_number = 0; | |
3722 | frag_grow (52); | |
3723 | if (reg_needs_delay (GP)) | |
3724 | gpdel = 4; | |
3725 | else | |
3726 | gpdel = 0; | |
3727 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3728 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
3729 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3730 | mips_isa < 3 ? "addu" : "daddu", | |
3731 | "d,v,t", tempreg, tempreg, GP); | |
3732 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3733 | dbl ? "ld" : "lw", | |
3734 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
3735 | tempreg); | |
3736 | if (expr1.X_add_number == 0) | |
3737 | { | |
3738 | int off; | |
3739 | ||
3740 | if (breg == 0) | |
3741 | off = 0; | |
3742 | else | |
3743 | { | |
3744 | /* We're going to put in an addu instruction using | |
3745 | tempreg, so we may as well insert the nop right | |
3746 | now. */ | |
3747 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3748 | "nop", ""); | |
3749 | off = 4; | |
3750 | } | |
3751 | ||
3752 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
3753 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
3754 | 8 + gpdel, 0, | |
3755 | (breg == 0 | |
3756 | ? mips_warn_about_macros | |
3757 | : 0)), | |
3758 | offset_expr.X_add_symbol, (long) 0, | |
3759 | (char *) NULL); | |
3760 | } | |
3761 | else if (expr1.X_add_number >= -0x8000 | |
3762 | && expr1.X_add_number < 0x8000) | |
3763 | { | |
3764 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3765 | "nop", ""); | |
3766 | macro_build ((char *) NULL, &icnt, &expr1, | |
3767 | mips_isa < 3 ? "addiu" : "daddiu", | |
3768 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3769 | ||
3770 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
3771 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
3772 | (breg == 0 | |
3773 | ? mips_warn_about_macros | |
3774 | : 0)), | |
3775 | offset_expr.X_add_symbol, (long) 0, | |
3776 | (char *) NULL); | |
3777 | } | |
3778 | else | |
3779 | { | |
3780 | int adj, dreg; | |
3781 | ||
3782 | /* If we are going to add in a base register, and the | |
3783 | target register and the base register are the same, | |
3784 | then we are using AT as a temporary register. Since | |
3785 | we want to load the constant into AT, we add our | |
3786 | current AT (from the global offset table) and the | |
3787 | register into the register now, and pretend we were | |
3788 | not using a base register. */ | |
3789 | if (breg != treg) | |
3790 | { | |
3791 | adj = 0; | |
3792 | dreg = tempreg; | |
3793 | } | |
3794 | else | |
3795 | { | |
3796 | assert (tempreg == AT); | |
3797 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3798 | "nop", ""); | |
3799 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3800 | mips_isa < 3 ? "addu" : "daddu", | |
3801 | "d,v,t", treg, AT, breg); | |
3802 | dreg = treg; | |
3803 | adj = 8; | |
3804 | } | |
3805 | ||
3806 | /* Set mips_optimize around the lui instruction to avoid | |
3807 | inserting an unnecessary nop after the lw. */ | |
3808 | hold_mips_optimize = mips_optimize; | |
3809 | mips_optimize = 2; | |
3810 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
3811 | mips_optimize = hold_mips_optimize; | |
3812 | ||
3813 | macro_build ((char *) NULL, &icnt, &expr1, | |
3814 | mips_isa < 3 ? "addiu" : "daddiu", | |
3815 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
3816 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3817 | mips_isa < 3 ? "addu" : "daddu", | |
3818 | "d,v,t", dreg, dreg, AT); | |
3819 | ||
3820 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
3821 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
3822 | 8 + gpdel, 0, | |
3823 | (breg == 0 | |
3824 | ? mips_warn_about_macros | |
3825 | : 0)), | |
3826 | offset_expr.X_add_symbol, (long) 0, | |
3827 | (char *) NULL); | |
3828 | ||
3829 | used_at = 1; | |
3830 | } | |
3831 | ||
3832 | if (gpdel > 0) | |
3833 | { | |
3834 | /* This is needed because this instruction uses $gp, but | |
3835 | the first instruction on the main stream does not. */ | |
3836 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3837 | p += 4; | |
3838 | } | |
3839 | macro_build (p, &icnt, &offset_expr, | |
3840 | dbl ? "ld" : "lw", | |
3841 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3842 | p += 4; | |
3843 | if (expr1.X_add_number >= -0x8000 | |
3844 | && expr1.X_add_number < 0x8000) | |
3845 | { | |
3846 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3847 | p += 4; | |
3848 | macro_build (p, &icnt, &expr1, | |
3849 | mips_isa < 3 ? "addiu" : "daddiu", | |
3850 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3851 | /* FIXME: If add_number is 0, and there was no base | |
3852 | register, the external symbol case ended with a load, | |
3853 | so if the symbol turns out to not be external, and | |
3854 | the next instruction uses tempreg, an unnecessary nop | |
3855 | will be inserted. */ | |
3856 | } | |
3857 | else | |
3858 | { | |
3859 | if (breg == treg) | |
3860 | { | |
3861 | /* We must add in the base register now, as in the | |
3862 | external symbol case. */ | |
3863 | assert (tempreg == AT); | |
3864 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3865 | p += 4; | |
3866 | macro_build (p, &icnt, (expressionS *) NULL, | |
3867 | mips_isa < 3 ? "addu" : "daddu", | |
3868 | "d,v,t", treg, AT, breg); | |
3869 | p += 4; | |
3870 | tempreg = treg; | |
3871 | /* We set breg to 0 because we have arranged to add | |
3872 | it in in both cases. */ | |
3873 | breg = 0; | |
3874 | } | |
3875 | ||
3876 | macro_build_lui (p, &icnt, &expr1, AT); | |
3877 | p += 4; | |
3878 | macro_build (p, &icnt, &expr1, | |
3879 | mips_isa < 3 ? "addiu" : "daddiu", | |
3880 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
3881 | p += 4; | |
3882 | macro_build (p, &icnt, (expressionS *) NULL, | |
3883 | mips_isa < 3 ? "addu" : "daddu", | |
3884 | "d,v,t", tempreg, tempreg, AT); | |
3885 | p += 4; | |
3886 | } | |
3887 | } | |
d9aba805 ILT |
3888 | else if (mips_pic == EMBEDDED_PIC) |
3889 | { | |
3890 | /* We use | |
3891 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3892 | */ | |
3893 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3894 | mips_isa < 3 ? "addiu" : "daddiu", | |
3895 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3896 | } | |
3897 | else | |
3898 | abort (); | |
0dd2d296 | 3899 | |
670a50eb | 3900 | if (breg != 0) |
0dd2d296 ILT |
3901 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3902 | mips_isa < 3 ? "addu" : "daddu", | |
3903 | "d,v,t", treg, tempreg, breg); | |
3904 | ||
3905 | if (! used_at) | |
3906 | return; | |
3907 | ||
3908 | break; | |
3909 | ||
3910 | case M_J_A: | |
3911 | /* The j instruction may not be used in PIC code, since it | |
3912 | requires an absolute address. We convert it to a b | |
3913 | instruction. */ | |
d9aba805 | 3914 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
3915 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
3916 | else | |
3917 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 3918 | return; |
3d3c5039 | 3919 | |
9226253a ILT |
3920 | /* The jal instructions must be handled as macros because when |
3921 | generating PIC code they expand to multi-instruction | |
3922 | sequences. Normally they are simple instructions. */ | |
3923 | case M_JAL_1: | |
3924 | dreg = RA; | |
3925 | /* Fall through. */ | |
3926 | case M_JAL_2: | |
d9aba805 ILT |
3927 | if (mips_pic == NO_PIC |
3928 | || mips_pic == EMBEDDED_PIC) | |
3929 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
3930 | "d,s", dreg, sreg); | |
3931 | else if (mips_pic == SVR4_PIC) | |
9226253a | 3932 | { |
d9aba805 ILT |
3933 | if (sreg != PIC_CALL_REG) |
3934 | as_warn ("MIPS PIC call to register other than $25"); | |
3935 | ||
0dd2d296 ILT |
3936 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
3937 | "d,s", dreg, sreg); | |
d9aba805 ILT |
3938 | if (mips_cprestore_offset < 0) |
3939 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
3940 | else | |
3941 | { | |
3942 | expr1.X_add_number = mips_cprestore_offset; | |
3943 | macro_build ((char *) NULL, &icnt, &expr1, | |
3944 | mips_isa < 3 ? "lw" : "ld", | |
3945 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
3946 | } | |
9226253a | 3947 | } |
0dd2d296 | 3948 | else |
d9aba805 ILT |
3949 | abort (); |
3950 | ||
9226253a ILT |
3951 | return; |
3952 | ||
3953 | case M_JAL_A: | |
d9aba805 ILT |
3954 | if (mips_pic == NO_PIC) |
3955 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
3956 | else if (mips_pic == SVR4_PIC) | |
9226253a | 3957 | { |
fb251650 ILT |
3958 | /* If this is a reference to an external symbol, and we are |
3959 | using a small GOT, we want | |
d9aba805 ILT |
3960 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
3961 | nop | |
3962 | jalr $25 | |
3963 | nop | |
3964 | lw $gp,cprestore($sp) | |
3965 | The cprestore value is set using the .cprestore | |
fb251650 ILT |
3966 | pseudo-op. If we are using a big GOT, we want |
3967 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
3968 | addu $25,$25,$gp | |
3969 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
3970 | nop | |
3971 | jalr $25 | |
3972 | nop | |
3973 | lw $gp,cprestore($sp) | |
3974 | If the symbol is not external, we want | |
d9aba805 ILT |
3975 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3976 | nop | |
3977 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
3978 | jalr $25 | |
3979 | nop | |
fb251650 ILT |
3980 | lw $gp,cprestore($sp) */ |
3981 | frag_grow (40); | |
3982 | if (! mips_big_got) | |
3983 | { | |
3984 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3985 | mips_isa < 3 ? "lw" : "ld", | |
3986 | "t,o(b)", PIC_CALL_REG, | |
3987 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
3988 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3989 | "nop", ""); | |
3990 | p = frag_var (rs_machine_dependent, 4, 0, | |
3991 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
3992 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
3993 | } | |
3994 | else | |
3995 | { | |
3996 | int gpdel; | |
3997 | ||
3998 | if (reg_needs_delay (GP)) | |
3999 | gpdel = 4; | |
4000 | else | |
4001 | gpdel = 0; | |
4002 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4003 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4004 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4005 | mips_isa < 3 ? "addu" : "daddu", | |
4006 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); | |
4007 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4008 | mips_isa < 3 ? "lw" : "ld", | |
4009 | "t,o(b)", PIC_CALL_REG, | |
4010 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4011 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4012 | "nop", ""); | |
4013 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4014 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4015 | 0, 0), | |
4016 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4017 | if (gpdel > 0) | |
4018 | { | |
4019 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4020 | p += 4; | |
4021 | } | |
4022 | macro_build (p, &icnt, &offset_expr, | |
4023 | mips_isa < 3 ? "lw" : "ld", | |
4024 | "t,o(b)", PIC_CALL_REG, | |
4025 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4026 | p += 4; | |
4027 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4028 | p += 4; | |
4029 | } | |
d9aba805 ILT |
4030 | macro_build (p, &icnt, &offset_expr, |
4031 | mips_isa < 3 ? "addiu" : "daddiu", | |
4032 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
4033 | (int) BFD_RELOC_LO16); | |
4034 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4035 | "jalr", "s", PIC_CALL_REG); | |
4036 | if (mips_cprestore_offset < 0) | |
4037 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4038 | else | |
4039 | { | |
4040 | if (mips_noreorder) | |
4041 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4042 | "nop", ""); | |
4043 | expr1.X_add_number = mips_cprestore_offset; | |
4044 | macro_build ((char *) NULL, &icnt, &expr1, | |
4045 | mips_isa < 3 ? "lw" : "ld", | |
4046 | "t,o(b)", GP, (int) BFD_RELOC_LO16, | |
4047 | mips_frame_reg); | |
4048 | } | |
0dd2d296 | 4049 | } |
d9aba805 | 4050 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
4051 | { |
4052 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4053 | /* The linker may expand the call to a longer sequence which | |
4054 | uses $at, so we must break rather than return. */ | |
4055 | break; | |
4056 | } | |
d9aba805 ILT |
4057 | else |
4058 | abort (); | |
4059 | ||
9226253a ILT |
4060 | return; |
4061 | ||
3d3c5039 | 4062 | case M_LB_AB: |
670a50eb ILT |
4063 | s = "lb"; |
4064 | goto ld; | |
3d3c5039 | 4065 | case M_LBU_AB: |
670a50eb ILT |
4066 | s = "lbu"; |
4067 | goto ld; | |
3d3c5039 | 4068 | case M_LH_AB: |
670a50eb ILT |
4069 | s = "lh"; |
4070 | goto ld; | |
3d3c5039 | 4071 | case M_LHU_AB: |
670a50eb ILT |
4072 | s = "lhu"; |
4073 | goto ld; | |
3d3c5039 | 4074 | case M_LW_AB: |
670a50eb ILT |
4075 | s = "lw"; |
4076 | goto ld; | |
3d3c5039 | 4077 | case M_LWC0_AB: |
670a50eb | 4078 | s = "lwc0"; |
8358c818 | 4079 | coproc = 1; |
670a50eb | 4080 | goto ld; |
3d3c5039 | 4081 | case M_LWC1_AB: |
670a50eb | 4082 | s = "lwc1"; |
8358c818 | 4083 | coproc = 1; |
670a50eb | 4084 | goto ld; |
3d3c5039 | 4085 | case M_LWC2_AB: |
670a50eb | 4086 | s = "lwc2"; |
8358c818 | 4087 | coproc = 1; |
670a50eb | 4088 | goto ld; |
3d3c5039 | 4089 | case M_LWC3_AB: |
670a50eb | 4090 | s = "lwc3"; |
8358c818 | 4091 | coproc = 1; |
670a50eb | 4092 | goto ld; |
3d3c5039 | 4093 | case M_LWL_AB: |
670a50eb | 4094 | s = "lwl"; |
b2b8c24e | 4095 | lr = 1; |
670a50eb | 4096 | goto ld; |
3d3c5039 | 4097 | case M_LWR_AB: |
670a50eb | 4098 | s = "lwr"; |
b2b8c24e | 4099 | lr = 1; |
8358c818 ILT |
4100 | goto ld; |
4101 | case M_LDC1_AB: | |
4102 | s = "ldc1"; | |
4103 | coproc = 1; | |
4104 | goto ld; | |
4105 | case M_LDC2_AB: | |
4106 | s = "ldc2"; | |
4107 | coproc = 1; | |
4108 | goto ld; | |
4109 | case M_LDC3_AB: | |
4110 | s = "ldc3"; | |
4111 | coproc = 1; | |
4112 | goto ld; | |
4113 | case M_LDL_AB: | |
4114 | s = "ldl"; | |
b2b8c24e | 4115 | lr = 1; |
8358c818 ILT |
4116 | goto ld; |
4117 | case M_LDR_AB: | |
4118 | s = "ldr"; | |
b2b8c24e | 4119 | lr = 1; |
8358c818 ILT |
4120 | goto ld; |
4121 | case M_LL_AB: | |
4122 | s = "ll"; | |
4123 | goto ld; | |
4124 | case M_LLD_AB: | |
4125 | s = "lld"; | |
4126 | goto ld; | |
4127 | case M_LWU_AB: | |
4128 | s = "lwu"; | |
3d3c5039 | 4129 | ld: |
b2b8c24e | 4130 | if (breg == treg || coproc || lr) |
670a50eb ILT |
4131 | { |
4132 | tempreg = AT; | |
4133 | used_at = 1; | |
4134 | } | |
4135 | else | |
4136 | { | |
4137 | tempreg = treg; | |
4138 | used_at = 0; | |
4139 | } | |
4140 | goto ld_st; | |
3d3c5039 | 4141 | case M_SB_AB: |
670a50eb ILT |
4142 | s = "sb"; |
4143 | goto st; | |
3d3c5039 | 4144 | case M_SH_AB: |
670a50eb ILT |
4145 | s = "sh"; |
4146 | goto st; | |
3d3c5039 | 4147 | case M_SW_AB: |
670a50eb ILT |
4148 | s = "sw"; |
4149 | goto st; | |
3d3c5039 | 4150 | case M_SWC0_AB: |
670a50eb | 4151 | s = "swc0"; |
8358c818 | 4152 | coproc = 1; |
670a50eb | 4153 | goto st; |
3d3c5039 | 4154 | case M_SWC1_AB: |
670a50eb | 4155 | s = "swc1"; |
8358c818 | 4156 | coproc = 1; |
670a50eb | 4157 | goto st; |
3d3c5039 | 4158 | case M_SWC2_AB: |
670a50eb | 4159 | s = "swc2"; |
8358c818 | 4160 | coproc = 1; |
670a50eb | 4161 | goto st; |
3d3c5039 | 4162 | case M_SWC3_AB: |
670a50eb | 4163 | s = "swc3"; |
8358c818 | 4164 | coproc = 1; |
670a50eb | 4165 | goto st; |
3d3c5039 | 4166 | case M_SWL_AB: |
670a50eb ILT |
4167 | s = "swl"; |
4168 | goto st; | |
3d3c5039 | 4169 | case M_SWR_AB: |
670a50eb | 4170 | s = "swr"; |
8358c818 ILT |
4171 | goto st; |
4172 | case M_SC_AB: | |
4173 | s = "sc"; | |
4174 | goto st; | |
4175 | case M_SCD_AB: | |
4176 | s = "scd"; | |
4177 | goto st; | |
4178 | case M_SDC1_AB: | |
4179 | s = "sdc1"; | |
4180 | coproc = 1; | |
4181 | goto st; | |
4182 | case M_SDC2_AB: | |
4183 | s = "sdc2"; | |
4184 | coproc = 1; | |
4185 | goto st; | |
4186 | case M_SDC3_AB: | |
4187 | s = "sdc3"; | |
4188 | coproc = 1; | |
4189 | goto st; | |
4190 | case M_SDL_AB: | |
4191 | s = "sdl"; | |
4192 | goto st; | |
4193 | case M_SDR_AB: | |
4194 | s = "sdr"; | |
3d3c5039 | 4195 | st: |
670a50eb ILT |
4196 | tempreg = AT; |
4197 | used_at = 1; | |
3d3c5039 | 4198 | ld_st: |
8358c818 ILT |
4199 | if (mask == M_LWC1_AB |
4200 | || mask == M_SWC1_AB | |
8358c818 | 4201 | || mask == M_LDC1_AB |
0dd2d296 ILT |
4202 | || mask == M_SDC1_AB |
4203 | || mask == M_L_DAB | |
4204 | || mask == M_S_DAB) | |
670a50eb | 4205 | fmt = "T,o(b)"; |
8358c818 | 4206 | else if (coproc) |
19ed8960 | 4207 | fmt = "E,o(b)"; |
670a50eb ILT |
4208 | else |
4209 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
4210 | |
4211 | if (offset_expr.X_op != O_constant | |
4212 | && offset_expr.X_op != O_symbol) | |
4213 | { | |
4214 | as_bad ("expression too complex"); | |
4215 | offset_expr.X_op = O_constant; | |
4216 | } | |
4217 | ||
4218 | /* A constant expression in PIC code can be handled just as it | |
4219 | is in non PIC code. */ | |
d9aba805 | 4220 | if (mips_pic == NO_PIC |
0dd2d296 | 4221 | || offset_expr.X_op == O_constant) |
670a50eb | 4222 | { |
0dd2d296 ILT |
4223 | /* If this is a reference to a GP relative symbol, and there |
4224 | is no base register, we want | |
4225 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 4226 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
4227 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
4228 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4229 | If we have a constant, we need two instructions anyhow, | |
4230 | so we always use the latter form. | |
4231 | ||
4232 | If we have a base register, and this is a reference to a | |
4233 | GP relative symbol, we want | |
4234 | addu $tempreg,$breg,$gp | |
4235 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4236 | Otherwise we want | |
4237 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4238 | addu $tempreg,$tempreg,$breg | |
4239 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4240 | With a constant we always use the latter case. */ | |
670a50eb ILT |
4241 | if (breg == 0) |
4242 | { | |
7a15a226 | 4243 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4244 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
4245 | p = NULL; |
4246 | else | |
4247 | { | |
8ea7f4e8 | 4248 | frag_grow (20); |
0dd2d296 ILT |
4249 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4250 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4251 | p = frag_var (rs_machine_dependent, 8, 0, | |
4252 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
8197b589 ILT |
4253 | (mips_warn_about_macros |
4254 | || (used_at && mips_noat))), | |
0dd2d296 ILT |
4255 | offset_expr.X_add_symbol, (long) 0, |
4256 | (char *) NULL); | |
8197b589 | 4257 | used_at = 0; |
0dd2d296 ILT |
4258 | } |
4259 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4260 | if (p != NULL) | |
4261 | p += 4; | |
4262 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4263 | (int) BFD_RELOC_LO16, tempreg); | |
4264 | } | |
4265 | else | |
4266 | { | |
7a15a226 | 4267 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4268 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
4269 | p = NULL; |
4270 | else | |
4271 | { | |
8ea7f4e8 | 4272 | frag_grow (28); |
0dd2d296 ILT |
4273 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4274 | mips_isa < 3 ? "addu" : "daddu", | |
4275 | "d,v,t", tempreg, breg, GP); | |
4276 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4277 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4278 | p = frag_var (rs_machine_dependent, 12, 0, | |
4279 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
4280 | offset_expr.X_add_symbol, (long) 0, | |
4281 | (char *) NULL); | |
4282 | } | |
4283 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4284 | if (p != NULL) | |
4285 | p += 4; | |
4286 | macro_build (p, &icnt, (expressionS *) NULL, | |
4287 | mips_isa < 3 ? "addu" : "daddu", | |
4288 | "d,v,t", tempreg, tempreg, breg); | |
4289 | if (p != NULL) | |
4290 | p += 4; | |
4291 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4292 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4293 | } |
670a50eb | 4294 | } |
fb251650 | 4295 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 4296 | { |
0dd2d296 ILT |
4297 | /* If this is a reference to an external symbol, we want |
4298 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4299 | nop | |
4300 | <op> $treg,0($tempreg) | |
4301 | Otherwise we want | |
4302 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4303 | nop | |
4304 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4305 | <op> $treg,0($tempreg) | |
4306 | If there is a base register, we add it to $tempreg before | |
4307 | the <op>. If there is a constant, we stick it in the | |
4308 | <op> instruction. We don't handle constants larger than | |
4309 | 16 bits, because we have no way to load the upper 16 bits | |
4310 | (actually, we could handle them for the subset of cases | |
4311 | in which we are not using $at). */ | |
4312 | assert (offset_expr.X_op == O_symbol); | |
4313 | expr1.X_add_number = offset_expr.X_add_number; | |
4314 | offset_expr.X_add_number = 0; | |
4315 | if (expr1.X_add_number < -0x8000 | |
4316 | || expr1.X_add_number >= 0x8000) | |
4317 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
8ea7f4e8 | 4318 | frag_grow (20); |
0dd2d296 ILT |
4319 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4320 | mips_isa < 3 ? "lw" : "ld", | |
4321 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4322 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
4323 | p = frag_var (rs_machine_dependent, 4, 0, | |
4324 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
4325 | offset_expr.X_add_symbol, (long) 0, | |
4326 | (char *) NULL); | |
4327 | macro_build (p, &icnt, &offset_expr, | |
4328 | mips_isa < 3 ? "addiu" : "daddiu", | |
4329 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
670a50eb | 4330 | if (breg != 0) |
0dd2d296 | 4331 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c ILT |
4332 | mips_isa < 3 ? "addu" : "daddu", |
4333 | "d,v,t", tempreg, tempreg, breg); | |
0dd2d296 ILT |
4334 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
4335 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4336 | } |
fb251650 ILT |
4337 | else if (mips_pic == SVR4_PIC) |
4338 | { | |
4339 | int gpdel; | |
4340 | ||
4341 | /* If this is a reference to an external symbol, we want | |
4342 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4343 | addu $tempreg,$tempreg,$gp | |
4344 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4345 | <op> $treg,0($tempreg) | |
4346 | Otherwise we want | |
4347 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4348 | nop | |
4349 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4350 | <op> $treg,0($tempreg) | |
4351 | If there is a base register, we add it to $tempreg before | |
4352 | the <op>. If there is a constant, we stick it in the | |
4353 | <op> instruction. We don't handle constants larger than | |
4354 | 16 bits, because we have no way to load the upper 16 bits | |
4355 | (actually, we could handle them for the subset of cases | |
4356 | in which we are not using $at). */ | |
4357 | assert (offset_expr.X_op == O_symbol); | |
4358 | expr1.X_add_number = offset_expr.X_add_number; | |
4359 | offset_expr.X_add_number = 0; | |
4360 | if (expr1.X_add_number < -0x8000 | |
4361 | || expr1.X_add_number >= 0x8000) | |
4362 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4363 | if (reg_needs_delay (GP)) | |
4364 | gpdel = 4; | |
4365 | else | |
4366 | gpdel = 0; | |
4367 | frag_grow (36); | |
4368 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4369 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4370 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4371 | mips_isa < 3 ? "addu" : "daddu", | |
4372 | "d,v,t", tempreg, tempreg, GP); | |
4373 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4374 | mips_isa < 3 ? "lw" : "ld", | |
867a58b3 ILT |
4375 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
4376 | tempreg); | |
fb251650 ILT |
4377 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
4378 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
4379 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4380 | if (gpdel > 0) | |
4381 | { | |
4382 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4383 | p += 4; | |
4384 | } | |
4385 | macro_build (p, &icnt, &offset_expr, | |
4386 | mips_isa < 3 ? "lw" : "ld", | |
867a58b3 | 4387 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
fb251650 ILT |
4388 | p += 4; |
4389 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4390 | p += 4; | |
4391 | macro_build (p, &icnt, &offset_expr, | |
4392 | mips_isa < 3 ? "addiu" : "daddiu", | |
4393 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4394 | if (breg != 0) | |
4395 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4396 | mips_isa < 3 ? "addu" : "daddu", | |
4397 | "d,v,t", tempreg, tempreg, breg); | |
4398 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
4399 | (int) BFD_RELOC_LO16, tempreg); | |
4400 | } | |
d9aba805 ILT |
4401 | else if (mips_pic == EMBEDDED_PIC) |
4402 | { | |
4403 | /* If there is no base register, we want | |
4404 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4405 | If there is a base register, we want | |
4406 | addu $tempreg,$breg,$gp | |
4407 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4408 | */ | |
4409 | assert (offset_expr.X_op == O_symbol); | |
4410 | if (breg == 0) | |
4411 | { | |
4412 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4413 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4414 | used_at = 0; | |
4415 | } | |
4416 | else | |
4417 | { | |
4418 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4419 | mips_isa < 3 ? "addu" : "daddu", | |
4420 | "d,v,t", tempreg, breg, GP); | |
4421 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4422 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4423 | } | |
4424 | } | |
4425 | else | |
4426 | abort (); | |
0dd2d296 ILT |
4427 | |
4428 | if (! used_at) | |
4429 | return; | |
4430 | ||
4431 | break; | |
3d3c5039 ILT |
4432 | |
4433 | case M_LI: | |
19ed8960 | 4434 | case M_LI_S: |
d8a1c247 KR |
4435 | load_register (&icnt, treg, &imm_expr, 0); |
4436 | return; | |
4437 | ||
4438 | case M_DLI: | |
4439 | load_register (&icnt, treg, &imm_expr, 1); | |
670a50eb | 4440 | return; |
3d3c5039 | 4441 | |
0dd2d296 | 4442 | case M_LI_SS: |
55933a58 | 4443 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 4444 | { |
d8a1c247 | 4445 | load_register (&icnt, AT, &imm_expr, 0); |
d2c71068 ILT |
4446 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4447 | "mtc1", "t,G", AT, treg); | |
4448 | break; | |
0dd2d296 | 4449 | } |
d9aba805 | 4450 | else |
d2c71068 | 4451 | { |
55933a58 ILT |
4452 | assert (offset_expr.X_op == O_symbol |
4453 | && strcmp (segment_name (S_GET_SEGMENT | |
4454 | (offset_expr.X_add_symbol)), | |
4455 | ".lit4") == 0 | |
4456 | && offset_expr.X_add_number == 0); | |
4457 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
4458 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
4459 | return; |
4460 | } | |
0dd2d296 | 4461 | |
3d3c5039 | 4462 | case M_LI_D: |
d9aba805 ILT |
4463 | /* We know that sym is in the .rdata section. First we get the |
4464 | upper 16 bits of the address. */ | |
4465 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
4466 | { |
4467 | /* FIXME: This won't work for a 64 bit address. */ | |
4468 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4469 | } | |
d9aba805 | 4470 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
4471 | { |
4472 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4473 | mips_isa < 3 ? "lw" : "ld", | |
4474 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4475 | } | |
d9aba805 ILT |
4476 | else if (mips_pic == EMBEDDED_PIC) |
4477 | { | |
4478 | /* For embedded PIC we pick up the entire address off $gp in | |
4479 | a single instruction. */ | |
4480 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4481 | mips_isa < 3 ? "addiu" : "daddiu", | |
4482 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4483 | offset_expr.X_op = O_constant; | |
4484 | offset_expr.X_add_number = 0; | |
4485 | } | |
4486 | else | |
4487 | abort (); | |
4488 | ||
0dd2d296 | 4489 | /* Now we load the register(s). */ |
8358c818 | 4490 | if (mips_isa >= 3) |
0dd2d296 ILT |
4491 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
4492 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
4493 | else |
4494 | { | |
0dd2d296 ILT |
4495 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
4496 | treg, (int) BFD_RELOC_LO16, AT); | |
4497 | if (treg != 31) | |
4498 | { | |
4499 | /* FIXME: How in the world do we deal with the possible | |
4500 | overflow here? */ | |
4501 | offset_expr.X_add_number += 4; | |
4502 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
4503 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
4504 | } | |
8358c818 | 4505 | } |
d2c71068 ILT |
4506 | |
4507 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
4508 | does not become a variant frag. */ | |
4509 | frag_wane (frag_now); | |
4510 | frag_new (0); | |
4511 | ||
670a50eb | 4512 | break; |
3d3c5039 ILT |
4513 | |
4514 | case M_LI_DD: | |
55933a58 ILT |
4515 | assert (offset_expr.X_op == O_symbol |
4516 | && offset_expr.X_add_number == 0); | |
4517 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
4518 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 4519 | { |
0dd2d296 ILT |
4520 | if (mips_isa >= 2) |
4521 | { | |
4522 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
4523 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
4524 | return; | |
4525 | } | |
4526 | breg = GP; | |
4527 | r = BFD_RELOC_MIPS_LITERAL; | |
4528 | goto dob; | |
4529 | } | |
55933a58 | 4530 | else |
0dd2d296 | 4531 | { |
55933a58 ILT |
4532 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
4533 | if (mips_pic == SVR4_PIC) | |
4534 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4535 | mips_isa < 3 ? "lw" : "ld", | |
4536 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4537 | else | |
4538 | { | |
4539 | /* FIXME: This won't work for a 64 bit address. */ | |
4540 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4541 | } | |
4542 | ||
0dd2d296 ILT |
4543 | if (mips_isa >= 2) |
4544 | { | |
4545 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 4546 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
94b68f04 ILT |
4547 | |
4548 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
4549 | that this does not become a variant frag. */ | |
4550 | frag_wane (frag_now); | |
4551 | frag_new (0); | |
4552 | ||
0dd2d296 ILT |
4553 | break; |
4554 | } | |
4555 | breg = AT; | |
4556 | r = BFD_RELOC_LO16; | |
4557 | goto dob; | |
8358c818 | 4558 | } |
9226253a | 4559 | |
3d3c5039 | 4560 | case M_L_DOB: |
9a7d824a ILT |
4561 | /* Even on a big endian machine $fn comes before $fn+1. We have |
4562 | to adjust when loading from memory. */ | |
9226253a ILT |
4563 | r = BFD_RELOC_LO16; |
4564 | dob: | |
8358c818 | 4565 | assert (mips_isa < 2); |
0dd2d296 | 4566 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
9a7d824a | 4567 | byte_order == LITTLE_ENDIAN ? treg : treg + 1, |
9226253a | 4568 | (int) r, breg); |
0dd2d296 ILT |
4569 | /* FIXME: A possible overflow which I don't know how to deal |
4570 | with. */ | |
670a50eb | 4571 | offset_expr.X_add_number += 4; |
0dd2d296 | 4572 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
9a7d824a | 4573 | byte_order == LITTLE_ENDIAN ? treg + 1 : treg, |
9226253a | 4574 | (int) r, breg); |
d2c71068 ILT |
4575 | |
4576 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
4577 | does not become a variant frag. */ | |
4578 | frag_wane (frag_now); | |
4579 | frag_new (0); | |
4580 | ||
0dd2d296 ILT |
4581 | if (breg != AT) |
4582 | return; | |
4583 | break; | |
3d3c5039 ILT |
4584 | |
4585 | case M_L_DAB: | |
670a50eb ILT |
4586 | /* |
4587 | * The MIPS assembler seems to check for X_add_number not | |
4588 | * being double aligned and generating: | |
4589 | * lui at,%hi(foo+1) | |
4590 | * addu at,at,v1 | |
4591 | * addiu at,at,%lo(foo+1) | |
4592 | * lwc1 f2,0(at) | |
4593 | * lwc1 f3,4(at) | |
4594 | * But, the resulting address is the same after relocation so why | |
4595 | * generate the extra instruction? | |
4596 | */ | |
4032d3f0 | 4597 | coproc = 1; |
0dd2d296 | 4598 | if (mips_isa >= 2) |
670a50eb | 4599 | { |
0dd2d296 ILT |
4600 | s = "ldc1"; |
4601 | goto ld; | |
670a50eb | 4602 | } |
0dd2d296 ILT |
4603 | |
4604 | s = "lwc1"; | |
4605 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
4606 | goto ldd_std; |
4607 | ||
4608 | case M_S_DAB: | |
8358c818 | 4609 | if (mips_isa >= 2) |
8358c818 | 4610 | { |
0dd2d296 ILT |
4611 | s = "sdc1"; |
4612 | goto st; | |
8358c818 | 4613 | } |
3d3c5039 | 4614 | |
0dd2d296 ILT |
4615 | s = "swc1"; |
4616 | fmt = "T,o(b)"; | |
4617 | coproc = 1; | |
4618 | goto ldd_std; | |
3d3c5039 ILT |
4619 | |
4620 | case M_LD_AB: | |
0dd2d296 | 4621 | if (mips_isa >= 3) |
670a50eb | 4622 | { |
0dd2d296 ILT |
4623 | s = "ld"; |
4624 | goto ld; | |
670a50eb | 4625 | } |
0dd2d296 ILT |
4626 | |
4627 | s = "lw"; | |
4628 | fmt = "t,o(b)"; | |
4629 | goto ldd_std; | |
4630 | ||
4631 | case M_SD_AB: | |
4632 | if (mips_isa >= 3) | |
670a50eb | 4633 | { |
0dd2d296 ILT |
4634 | s = "sd"; |
4635 | goto st; | |
670a50eb | 4636 | } |
0dd2d296 | 4637 | |
670a50eb | 4638 | s = "sw"; |
0dd2d296 ILT |
4639 | fmt = "t,o(b)"; |
4640 | ||
4641 | ldd_std: | |
4642 | if (offset_expr.X_op != O_symbol | |
4643 | && offset_expr.X_op != O_constant) | |
670a50eb | 4644 | { |
0dd2d296 ILT |
4645 | as_bad ("expression too complex"); |
4646 | offset_expr.X_op = O_constant; | |
4647 | } | |
4648 | ||
4649 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
4650 | to adjust when loading from memory. We set coproc if we must | |
4651 | load $fn+1 first. */ | |
4652 | if (byte_order == LITTLE_ENDIAN) | |
4653 | coproc = 0; | |
4654 | ||
d9aba805 | 4655 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
4656 | || offset_expr.X_op == O_constant) |
4657 | { | |
4658 | /* If this is a reference to a GP relative symbol, we want | |
4659 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4660 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
4661 | If we have a base register, we use this | |
4662 | addu $at,$breg,$gp | |
4663 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
4664 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
4665 | If this is not a GP relative symbol, we want | |
4666 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4667 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
4668 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
4669 | If there is a base register, we add it to $at after the | |
4670 | lui instruction. If there is a constant, we always use | |
4671 | the last case. */ | |
7a15a226 | 4672 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4673 | || nopic_need_relax (offset_expr.X_add_symbol)) |
670a50eb | 4674 | { |
0dd2d296 ILT |
4675 | p = NULL; |
4676 | used_at = 1; | |
670a50eb ILT |
4677 | } |
4678 | else | |
0dd2d296 ILT |
4679 | { |
4680 | int off; | |
4681 | ||
4682 | if (breg == 0) | |
4683 | { | |
8ea7f4e8 | 4684 | frag_grow (28); |
0dd2d296 ILT |
4685 | tempreg = GP; |
4686 | off = 0; | |
4687 | used_at = 0; | |
4688 | } | |
4689 | else | |
4690 | { | |
8ea7f4e8 | 4691 | frag_grow (36); |
0dd2d296 ILT |
4692 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4693 | mips_isa < 3 ? "addu" : "daddu", | |
4694 | "d,v,t", AT, breg, GP); | |
4695 | tempreg = AT; | |
4696 | off = 4; | |
4697 | used_at = 1; | |
4698 | } | |
4699 | ||
4700 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4701 | coproc ? treg + 1 : treg, | |
4702 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4703 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
4704 | |
4705 | /* Set mips_optimize to 2 to avoid inserting an | |
4706 | undesired nop. */ | |
4707 | hold_mips_optimize = mips_optimize; | |
4708 | mips_optimize = 2; | |
0dd2d296 ILT |
4709 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4710 | coproc ? treg : treg + 1, | |
4711 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
4712 | mips_optimize = hold_mips_optimize; |
4713 | ||
0dd2d296 ILT |
4714 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
4715 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
8197b589 | 4716 | used_at && mips_noat), |
0dd2d296 ILT |
4717 | offset_expr.X_add_symbol, (long) 0, |
4718 | (char *) NULL); | |
777ad64d ILT |
4719 | |
4720 | /* We just generated two relocs. When tc_gen_reloc | |
4721 | handles this case, it will skip the first reloc and | |
4722 | handle the second. The second reloc already has an | |
4723 | extra addend of 4, which we added above. We must | |
4724 | subtract it out, and then subtract another 4 to make | |
4725 | the first reloc come out right. The second reloc | |
4726 | will come out right because we are going to add 4 to | |
4727 | offset_expr when we build its instruction below. */ | |
4728 | offset_expr.X_add_number -= 8; | |
0dd2d296 ILT |
4729 | offset_expr.X_op = O_constant; |
4730 | } | |
4731 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
4732 | if (p != NULL) | |
4733 | p += 4; | |
4734 | if (breg != 0) | |
4735 | { | |
4736 | macro_build (p, &icnt, (expressionS *) NULL, | |
4737 | mips_isa < 3 ? "addu" : "daddu", | |
4738 | "d,v,t", AT, breg, AT); | |
4739 | if (p != NULL) | |
4740 | p += 4; | |
4741 | } | |
4742 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
4743 | coproc ? treg + 1 : treg, | |
4744 | (int) BFD_RELOC_LO16, AT); | |
4745 | if (p != NULL) | |
4746 | p += 4; | |
4747 | /* FIXME: How do we handle overflow here? */ | |
4748 | offset_expr.X_add_number += 4; | |
4749 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
4750 | coproc ? treg : treg + 1, | |
4751 | (int) BFD_RELOC_LO16, AT); | |
4752 | } | |
fb251650 | 4753 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 4754 | { |
0dd2d296 ILT |
4755 | int off; |
4756 | ||
4757 | /* If this is a reference to an external symbol, we want | |
4758 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4759 | nop | |
4760 | <op> $treg,0($at) | |
4761 | <op> $treg+1,4($at) | |
4762 | Otherwise we want | |
4763 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4764 | nop | |
4765 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
4766 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
4767 | If there is a base register we add it to $at before the | |
4768 | lwc1 instructions. If there is a constant we include it | |
4769 | in the lwc1 instructions. */ | |
4770 | used_at = 1; | |
4771 | expr1.X_add_number = offset_expr.X_add_number; | |
4772 | offset_expr.X_add_number = 0; | |
4773 | if (expr1.X_add_number < -0x8000 | |
4774 | || expr1.X_add_number >= 0x8000 - 4) | |
4775 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4776 | if (breg == 0) | |
4777 | off = 0; | |
4778 | else | |
4779 | off = 4; | |
8ea7f4e8 | 4780 | frag_grow (24 + off); |
0dd2d296 ILT |
4781 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4782 | mips_isa < 3 ? "lw" : "ld", | |
4783 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4784 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 4785 | if (breg != 0) |
0dd2d296 | 4786 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c | 4787 | mips_isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
4788 | "d,v,t", AT, breg, AT); |
4789 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
4790 | coproc ? treg + 1 : treg, | |
4791 | (int) BFD_RELOC_LO16, AT); | |
4792 | expr1.X_add_number += 4; | |
55933a58 ILT |
4793 | |
4794 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
4795 | nop. */ | |
4796 | hold_mips_optimize = mips_optimize; | |
4797 | mips_optimize = 2; | |
0dd2d296 ILT |
4798 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
4799 | coproc ? treg : treg + 1, | |
4800 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
4801 | mips_optimize = hold_mips_optimize; |
4802 | ||
0dd2d296 ILT |
4803 | (void) frag_var (rs_machine_dependent, 0, 0, |
4804 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
4805 | offset_expr.X_add_symbol, (long) 0, | |
4806 | (char *) NULL); | |
8358c818 | 4807 | } |
fb251650 ILT |
4808 | else if (mips_pic == SVR4_PIC) |
4809 | { | |
4810 | int gpdel, off; | |
4811 | ||
4812 | /* If this is a reference to an external symbol, we want | |
4813 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4814 | addu $at,$at,$gp | |
4815 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
4816 | nop | |
4817 | <op> $treg,0($at) | |
4818 | <op> $treg+1,4($at) | |
4819 | Otherwise we want | |
4820 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4821 | nop | |
4822 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
4823 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
4824 | If there is a base register we add it to $at before the | |
4825 | lwc1 instructions. If there is a constant we include it | |
4826 | in the lwc1 instructions. */ | |
4827 | used_at = 1; | |
4828 | expr1.X_add_number = offset_expr.X_add_number; | |
4829 | offset_expr.X_add_number = 0; | |
4830 | if (expr1.X_add_number < -0x8000 | |
4831 | || expr1.X_add_number >= 0x8000 - 4) | |
4832 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4833 | if (reg_needs_delay (GP)) | |
4834 | gpdel = 4; | |
4835 | else | |
4836 | gpdel = 0; | |
4837 | if (breg == 0) | |
4838 | off = 0; | |
4839 | else | |
4840 | off = 4; | |
4841 | frag_grow (56); | |
4842 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4843 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4844 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4845 | mips_isa < 3 ? "addu" : "daddu", | |
4846 | "d,v,t", AT, AT, GP); | |
4847 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4848 | mips_isa < 3 ? "lw" : "ld", | |
4849 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); | |
4850 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
4851 | if (breg != 0) | |
4852 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4853 | mips_isa < 3 ? "addu" : "daddu", | |
4854 | "d,v,t", AT, breg, AT); | |
4855 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
4856 | coproc ? treg + 1 : treg, | |
4857 | (int) BFD_RELOC_LO16, AT); | |
4858 | expr1.X_add_number += 4; | |
4859 | ||
4860 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
4861 | nop. */ | |
4862 | hold_mips_optimize = mips_optimize; | |
4863 | mips_optimize = 2; | |
4864 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
4865 | coproc ? treg : treg + 1, | |
4866 | (int) BFD_RELOC_LO16, AT); | |
4867 | mips_optimize = hold_mips_optimize; | |
4868 | expr1.X_add_number -= 4; | |
4869 | ||
4870 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
4871 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
4872 | 8 + gpdel + off, 1, 0), | |
4873 | offset_expr.X_add_symbol, (long) 0, | |
4874 | (char *) NULL); | |
4875 | if (gpdel > 0) | |
4876 | { | |
4877 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4878 | p += 4; | |
4879 | } | |
4880 | macro_build (p, &icnt, &offset_expr, | |
4881 | mips_isa < 3 ? "lw" : "ld", | |
4882 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4883 | p += 4; | |
4884 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4885 | p += 4; | |
4886 | if (breg != 0) | |
4887 | { | |
4888 | macro_build (p, &icnt, (expressionS *) NULL, | |
4889 | mips_isa < 3 ? "addu" : "daddu", | |
4890 | "d,v,t", AT, breg, AT); | |
4891 | p += 4; | |
4892 | } | |
4893 | macro_build (p, &icnt, &expr1, s, fmt, | |
4894 | coproc ? treg + 1 : treg, | |
4895 | (int) BFD_RELOC_LO16, AT); | |
4896 | p += 4; | |
4897 | expr1.X_add_number += 4; | |
4898 | ||
4899 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
4900 | nop. */ | |
4901 | hold_mips_optimize = mips_optimize; | |
4902 | mips_optimize = 2; | |
4903 | macro_build (p, &icnt, &expr1, s, fmt, | |
4904 | coproc ? treg : treg + 1, | |
4905 | (int) BFD_RELOC_LO16, AT); | |
4906 | mips_optimize = hold_mips_optimize; | |
4907 | } | |
d9aba805 ILT |
4908 | else if (mips_pic == EMBEDDED_PIC) |
4909 | { | |
4910 | /* If there is no base register, we use | |
4911 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4912 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
4913 | If we have a base register, we use | |
4914 | addu $at,$breg,$gp | |
4915 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
4916 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
4917 | */ | |
4918 | if (breg == 0) | |
4919 | { | |
4920 | tempreg = GP; | |
4921 | used_at = 0; | |
4922 | } | |
4923 | else | |
4924 | { | |
4925 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4926 | mips_isa < 3 ? "addu" : "daddu", | |
4927 | "d,v,t", AT, breg, GP); | |
4928 | tempreg = AT; | |
4929 | used_at = 1; | |
4930 | } | |
4931 | ||
4932 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4933 | coproc ? treg + 1 : treg, | |
4934 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4935 | offset_expr.X_add_number += 4; | |
4936 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4937 | coproc ? treg : treg + 1, | |
4938 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4939 | } | |
4940 | else | |
4941 | abort (); | |
0dd2d296 ILT |
4942 | |
4943 | if (! used_at) | |
4944 | return; | |
4945 | ||
4946 | break; | |
4947 | ||
4948 | case M_LD_OB: | |
4949 | s = "lw"; | |
4950 | goto sd_ob; | |
4951 | case M_SD_OB: | |
4952 | s = "sw"; | |
4953 | sd_ob: | |
4954 | assert (mips_isa < 3); | |
4955 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
4956 | (int) BFD_RELOC_LO16, breg); | |
4957 | offset_expr.X_add_number += 4; | |
4958 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
4959 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 4960 | return; |
917fae09 SS |
4961 | #ifdef LOSING_COMPILER |
4962 | default: | |
4963 | macro2 (ip); | |
4964 | return; | |
4965 | } | |
4966 | if (mips_noat) | |
4967 | as_warn ("Macro used $at after \".set noat\""); | |
4968 | } | |
4969 | ||
4970 | static void | |
4971 | macro2 (ip) | |
4972 | struct mips_cl_insn *ip; | |
4973 | { | |
4974 | register int treg, sreg, dreg, breg; | |
4975 | int tempreg; | |
4976 | int mask; | |
4977 | int icnt = 0; | |
4978 | int used_at; | |
4979 | expressionS expr1; | |
4980 | const char *s; | |
4981 | const char *s2; | |
4982 | const char *fmt; | |
4983 | int likely = 0; | |
4984 | int dbl = 0; | |
4985 | int coproc = 0; | |
adcf2b9d ILT |
4986 | int lr = 0; |
4987 | int off; | |
917fae09 SS |
4988 | offsetT maxnum; |
4989 | bfd_reloc_code_real_type r; | |
4990 | char *p; | |
4991 | ||
4992 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4993 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4994 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4995 | mask = ip->insn_mo->mask; | |
4996 | ||
4997 | expr1.X_op = O_constant; | |
4998 | expr1.X_op_symbol = NULL; | |
4999 | expr1.X_add_symbol = NULL; | |
5000 | expr1.X_add_number = 1; | |
5001 | ||
5002 | switch (mask) | |
5003 | { | |
5004 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 5005 | |
8358c818 ILT |
5006 | case M_DMUL: |
5007 | dbl = 1; | |
3d3c5039 | 5008 | case M_MUL: |
0dd2d296 | 5009 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5010 | dbl ? "dmultu" : "multu", |
5011 | "s,t", sreg, treg); | |
0dd2d296 | 5012 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5013 | return; |
3d3c5039 | 5014 | |
8358c818 ILT |
5015 | case M_DMUL_I: |
5016 | dbl = 1; | |
3d3c5039 | 5017 | case M_MUL_I: |
8358c818 ILT |
5018 | /* The MIPS assembler some times generates shifts and adds. I'm |
5019 | not trying to be that fancy. GCC should do this for us | |
5020 | anyway. */ | |
d8a1c247 | 5021 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5022 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5023 | dbl ? "dmult" : "mult", |
5024 | "s,t", sreg, AT); | |
0dd2d296 | 5025 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5026 | break; |
3d3c5039 | 5027 | |
8358c818 ILT |
5028 | case M_DMULO: |
5029 | dbl = 1; | |
5030 | case M_MULO: | |
5031 | mips_emit_delays (); | |
5032 | ++mips_noreorder; | |
0dd2d296 ILT |
5033 | mips_any_noreorder = 1; |
5034 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5035 | dbl ? "dmult" : "mult", |
5036 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5037 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
5038 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5039 | dbl ? "dsra32" : "sra", |
5040 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 5041 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
5042 | if (mips_trap) |
5043 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
5044 | else | |
5045 | { | |
5046 | expr1.X_add_number = 8; | |
5047 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
5048 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5049 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5050 | } | |
8358c818 | 5051 | --mips_noreorder; |
0dd2d296 | 5052 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
5053 | break; |
5054 | ||
5055 | case M_DMULOU: | |
5056 | dbl = 1; | |
5057 | case M_MULOU: | |
5058 | mips_emit_delays (); | |
5059 | ++mips_noreorder; | |
0dd2d296 ILT |
5060 | mips_any_noreorder = 1; |
5061 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5062 | dbl ? "dmultu" : "multu", |
5063 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5064 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
5065 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
5066 | if (mips_trap) |
5067 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
5068 | else | |
5069 | { | |
5070 | expr1.X_add_number = 8; | |
5071 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
5072 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5073 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5074 | } | |
8358c818 ILT |
5075 | --mips_noreorder; |
5076 | break; | |
5077 | ||
3d3c5039 | 5078 | case M_ROL: |
0dd2d296 ILT |
5079 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5080 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
5081 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
5082 | treg); | |
5083 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5084 | break; |
3d3c5039 ILT |
5085 | |
5086 | case M_ROL_I: | |
0dd2d296 | 5087 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
a40aee38 | 5088 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5089 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
a40aee38 | 5090 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5091 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5092 | break; |
3d3c5039 ILT |
5093 | |
5094 | case M_ROR: | |
0dd2d296 ILT |
5095 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5096 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
5097 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
5098 | treg); | |
5099 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5100 | break; |
3d3c5039 ILT |
5101 | |
5102 | case M_ROR_I: | |
0dd2d296 | 5103 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
a40aee38 | 5104 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5105 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
a40aee38 | 5106 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5107 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5108 | break; |
3d3c5039 ILT |
5109 | |
5110 | case M_S_DOB: | |
8358c818 | 5111 | assert (mips_isa < 2); |
9a7d824a ILT |
5112 | /* Even on a big endian machine $fn comes before $fn+1. We have |
5113 | to adjust when storing to memory. */ | |
0dd2d296 | 5114 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
9a7d824a | 5115 | byte_order == LITTLE_ENDIAN ? treg : treg + 1, |
9226253a | 5116 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5117 | offset_expr.X_add_number += 4; |
0dd2d296 | 5118 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
9a7d824a | 5119 | byte_order == LITTLE_ENDIAN ? treg + 1 : treg, |
9226253a | 5120 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5121 | return; |
3d3c5039 | 5122 | |
3d3c5039 | 5123 | case M_SEQ: |
670a50eb | 5124 | if (sreg == 0) |
0dd2d296 ILT |
5125 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5126 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 5127 | else if (treg == 0) |
0dd2d296 ILT |
5128 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5129 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
5130 | else |
5131 | { | |
0dd2d296 ILT |
5132 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5133 | sreg, treg); | |
5134 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
5135 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 5136 | } |
670a50eb | 5137 | return; |
3d3c5039 ILT |
5138 | |
5139 | case M_SEQ_I: | |
670a50eb ILT |
5140 | if (imm_expr.X_add_number == 0) |
5141 | { | |
0dd2d296 ILT |
5142 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5143 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5144 | return; |
3d3c5039 | 5145 | } |
670a50eb ILT |
5146 | if (sreg == 0) |
5147 | { | |
9a7d824a | 5148 | as_warn ("Instruction %s: result is always false", |
6e8dda9c | 5149 | ip->insn_mo->name); |
0dd2d296 | 5150 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 5151 | return; |
3d3c5039 | 5152 | } |
6e8dda9c | 5153 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 5154 | { |
0dd2d296 ILT |
5155 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
5156 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5157 | used_at = 0; |
6e8dda9c ILT |
5158 | } |
5159 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
5160 | { | |
5161 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5162 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 5163 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a ILT |
5164 | "t,r,j", dreg, sreg, |
5165 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
5166 | used_at = 0; |
5167 | } | |
5168 | else | |
5169 | { | |
d8a1c247 | 5170 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5171 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5172 | sreg, AT); | |
670a50eb ILT |
5173 | used_at = 1; |
5174 | } | |
0dd2d296 | 5175 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 5176 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5177 | if (used_at) |
5178 | break; | |
5179 | return; | |
3d3c5039 ILT |
5180 | |
5181 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
5182 | s = "slt"; |
5183 | goto sge; | |
3d3c5039 | 5184 | case M_SGEU: |
670a50eb | 5185 | s = "sltu"; |
3d3c5039 | 5186 | sge: |
0dd2d296 ILT |
5187 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
5188 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5189 | (int) BFD_RELOC_LO16); |
670a50eb | 5190 | return; |
3d3c5039 | 5191 | |
670a50eb | 5192 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 5193 | case M_SGEU_I: |
6e8dda9c | 5194 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5195 | { |
0dd2d296 | 5196 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5197 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 5198 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
5199 | used_at = 0; |
5200 | } | |
5201 | else | |
5202 | { | |
d8a1c247 | 5203 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5204 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
5205 | mask == M_SGE_I ? "slt" : "sltu", |
5206 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
5207 | used_at = 1; |
5208 | } | |
0dd2d296 | 5209 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 5210 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5211 | if (used_at) |
5212 | break; | |
5213 | return; | |
3d3c5039 ILT |
5214 | |
5215 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
5216 | s = "slt"; |
5217 | goto sgt; | |
3d3c5039 | 5218 | case M_SGTU: |
670a50eb | 5219 | s = "sltu"; |
3d3c5039 | 5220 | sgt: |
0dd2d296 | 5221 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 5222 | return; |
3d3c5039 | 5223 | |
670a50eb ILT |
5224 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
5225 | s = "slt"; | |
5226 | goto sgti; | |
3d3c5039 | 5227 | case M_SGTU_I: |
670a50eb | 5228 | s = "sltu"; |
3d3c5039 | 5229 | sgti: |
d8a1c247 | 5230 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5231 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 5232 | break; |
3d3c5039 | 5233 | |
670a50eb ILT |
5234 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
5235 | s = "slt"; | |
5236 | goto sle; | |
3d3c5039 | 5237 | case M_SLEU: |
670a50eb | 5238 | s = "sltu"; |
3d3c5039 | 5239 | sle: |
0dd2d296 ILT |
5240 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
5241 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5242 | (int) BFD_RELOC_LO16); |
670a50eb | 5243 | return; |
3d3c5039 | 5244 | |
670a50eb ILT |
5245 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
5246 | s = "slt"; | |
5247 | goto slei; | |
3d3c5039 | 5248 | case M_SLEU_I: |
670a50eb | 5249 | s = "sltu"; |
3d3c5039 | 5250 | slei: |
d8a1c247 | 5251 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5252 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
5253 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5254 | (int) BFD_RELOC_LO16); |
670a50eb | 5255 | break; |
3d3c5039 ILT |
5256 | |
5257 | case M_SLT_I: | |
6e8dda9c | 5258 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5259 | { |
0dd2d296 ILT |
5260 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
5261 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5262 | return; |
3d3c5039 | 5263 | } |
d8a1c247 | 5264 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5265 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 5266 | break; |
3d3c5039 ILT |
5267 | |
5268 | case M_SLTU_I: | |
6e8dda9c | 5269 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5270 | { |
0dd2d296 ILT |
5271 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
5272 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5273 | return; |
3d3c5039 | 5274 | } |
d8a1c247 | 5275 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5276 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
5277 | AT); | |
670a50eb | 5278 | break; |
3d3c5039 ILT |
5279 | |
5280 | case M_SNE: | |
670a50eb | 5281 | if (sreg == 0) |
0dd2d296 ILT |
5282 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5283 | treg); | |
670a50eb | 5284 | else if (treg == 0) |
0dd2d296 ILT |
5285 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5286 | sreg); | |
670a50eb ILT |
5287 | else |
5288 | { | |
0dd2d296 ILT |
5289 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5290 | sreg, treg); | |
5291 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
5292 | dreg); | |
3d3c5039 | 5293 | } |
670a50eb | 5294 | return; |
3d3c5039 ILT |
5295 | |
5296 | case M_SNE_I: | |
670a50eb ILT |
5297 | if (imm_expr.X_add_number == 0) |
5298 | { | |
0dd2d296 ILT |
5299 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5300 | sreg); | |
670a50eb | 5301 | return; |
3d3c5039 | 5302 | } |
670a50eb ILT |
5303 | if (sreg == 0) |
5304 | { | |
9a7d824a | 5305 | as_warn ("Instruction %s: result is always true", |
6e8dda9c | 5306 | ip->insn_mo->name); |
0dd2d296 | 5307 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5308 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 5309 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 5310 | return; |
3d3c5039 | 5311 | } |
6e8dda9c | 5312 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 5313 | { |
0dd2d296 ILT |
5314 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
5315 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5316 | used_at = 0; |
6e8dda9c ILT |
5317 | } |
5318 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
5319 | { | |
5320 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5321 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 5322 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 5323 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
5324 | used_at = 0; |
5325 | } | |
5326 | else | |
5327 | { | |
d8a1c247 | 5328 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5329 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5330 | sreg, AT); | |
670a50eb ILT |
5331 | used_at = 1; |
5332 | } | |
0dd2d296 | 5333 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
5334 | if (used_at) |
5335 | break; | |
5336 | return; | |
3d3c5039 | 5337 | |
8358c818 ILT |
5338 | case M_DSUB_I: |
5339 | dbl = 1; | |
3d3c5039 | 5340 | case M_SUB_I: |
6e8dda9c | 5341 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
5342 | { |
5343 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5344 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5345 | dbl ? "daddi" : "addi", |
9226253a | 5346 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 5347 | return; |
3d3c5039 | 5348 | } |
d8a1c247 | 5349 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5350 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5351 | dbl ? "dsub" : "sub", |
5352 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 5353 | break; |
3d3c5039 | 5354 | |
8358c818 ILT |
5355 | case M_DSUBU_I: |
5356 | dbl = 1; | |
3d3c5039 | 5357 | case M_SUBU_I: |
6e8dda9c | 5358 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
5359 | { |
5360 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5361 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5362 | dbl ? "daddiu" : "addiu", |
9226253a | 5363 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 5364 | return; |
3d3c5039 | 5365 | } |
d8a1c247 | 5366 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5367 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5368 | dbl ? "dsubu" : "subu", |
5369 | "d,v,t", dreg, sreg, AT); | |
5370 | break; | |
5371 | ||
5372 | case M_TEQ_I: | |
5373 | s = "teq"; | |
5374 | goto trap; | |
5375 | case M_TGE_I: | |
5376 | s = "tge"; | |
5377 | goto trap; | |
5378 | case M_TGEU_I: | |
5379 | s = "tgeu"; | |
5380 | goto trap; | |
5381 | case M_TLT_I: | |
5382 | s = "tlt"; | |
5383 | goto trap; | |
5384 | case M_TLTU_I: | |
5385 | s = "tltu"; | |
5386 | goto trap; | |
5387 | case M_TNE_I: | |
5388 | s = "tne"; | |
5389 | trap: | |
d8a1c247 | 5390 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5391 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 5392 | break; |
3d3c5039 ILT |
5393 | |
5394 | case M_TRUNCWD: | |
5395 | case M_TRUNCWS: | |
8358c818 | 5396 | assert (mips_isa < 2); |
670a50eb ILT |
5397 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
5398 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
5399 | ||
5400 | /* | |
5401 | * Is the double cfc1 instruction a bug in the mips assembler; | |
5402 | * or is there a reason for it? | |
5403 | */ | |
becfe05e ILT |
5404 | mips_emit_delays (); |
5405 | ++mips_noreorder; | |
0dd2d296 ILT |
5406 | mips_any_noreorder = 1; |
5407 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
5408 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
5409 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 5410 | expr1.X_add_number = 3; |
0dd2d296 | 5411 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 5412 | (int) BFD_RELOC_LO16); |
670a50eb | 5413 | expr1.X_add_number = 2; |
0dd2d296 | 5414 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 5415 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
5416 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
5417 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
5418 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 5419 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
5420 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
5421 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
becfe05e | 5422 | --mips_noreorder; |
670a50eb | 5423 | break; |
3d3c5039 ILT |
5424 | |
5425 | case M_ULH: | |
670a50eb ILT |
5426 | s = "lb"; |
5427 | goto ulh; | |
3d3c5039 | 5428 | case M_ULHU: |
670a50eb | 5429 | s = "lbu"; |
3d3c5039 | 5430 | ulh: |
8ea7f4e8 ILT |
5431 | if (offset_expr.X_add_number >= 0x7fff) |
5432 | as_bad ("operand overflow"); | |
670a50eb | 5433 | /* avoid load delay */ |
8ea7f4e8 ILT |
5434 | if (byte_order == LITTLE_ENDIAN) |
5435 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5436 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 5437 | (int) BFD_RELOC_LO16, breg); |
8ea7f4e8 ILT |
5438 | if (byte_order == LITTLE_ENDIAN) |
5439 | offset_expr.X_add_number -= 1; | |
5440 | else | |
5441 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5442 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 5443 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
5444 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
5445 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 5446 | break; |
3d3c5039 | 5447 | |
adcf2b9d ILT |
5448 | case M_ULD: |
5449 | s = "ldl"; | |
5450 | s2 = "ldr"; | |
5451 | off = 7; | |
5452 | goto ulw; | |
3d3c5039 | 5453 | case M_ULW: |
adcf2b9d ILT |
5454 | s = "lwl"; |
5455 | s2 = "lwr"; | |
5456 | off = 3; | |
5457 | ulw: | |
5458 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 ILT |
5459 | as_bad ("operand overflow"); |
5460 | if (byte_order == LITTLE_ENDIAN) | |
adcf2b9d ILT |
5461 | offset_expr.X_add_number += off; |
5462 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 5463 | (int) BFD_RELOC_LO16, breg); |
8ea7f4e8 | 5464 | if (byte_order == LITTLE_ENDIAN) |
adcf2b9d | 5465 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 5466 | else |
adcf2b9d ILT |
5467 | offset_expr.X_add_number += off; |
5468 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 5469 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5470 | return; |
3d3c5039 | 5471 | |
adcf2b9d ILT |
5472 | case M_ULD_A: |
5473 | s = "ldl"; | |
5474 | s2 = "ldr"; | |
5475 | off = 7; | |
5476 | goto ulwa; | |
5477 | case M_ULW_A: | |
5478 | s = "lwl"; | |
5479 | s2 = "lwr"; | |
5480 | off = 3; | |
5481 | ulwa: | |
5482 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
5483 | if (breg != 0) |
5484 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5485 | mips_isa < 3 ? "addu" : "daddu", | |
5486 | "d,v,t", AT, AT, breg); | |
adcf2b9d ILT |
5487 | if (byte_order == LITTLE_ENDIAN) |
5488 | expr1.X_add_number = off; | |
5489 | else | |
5490 | expr1.X_add_number = 0; | |
5491 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
5492 | (int) BFD_RELOC_LO16, AT); | |
5493 | if (byte_order == LITTLE_ENDIAN) | |
5494 | expr1.X_add_number = 0; | |
5495 | else | |
5496 | expr1.X_add_number = off; | |
5497 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
5498 | (int) BFD_RELOC_LO16, AT); | |
5499 | break; | |
5500 | ||
3d3c5039 ILT |
5501 | case M_ULH_A: |
5502 | case M_ULHU_A: | |
0dd2d296 | 5503 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
5504 | if (breg != 0) |
5505 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5506 | mips_isa < 3 ? "addu" : "daddu", | |
5507 | "d,v,t", AT, AT, breg); | |
adcf2b9d ILT |
5508 | if (byte_order == BIG_ENDIAN) |
5509 | expr1.X_add_number = 0; | |
5510 | macro_build ((char *) NULL, &icnt, &expr1, | |
5511 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
5512 | (int) BFD_RELOC_LO16, AT); | |
5513 | if (byte_order == BIG_ENDIAN) | |
5514 | expr1.X_add_number = 1; | |
670a50eb | 5515 | else |
adcf2b9d ILT |
5516 | expr1.X_add_number = 0; |
5517 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
5518 | (int) BFD_RELOC_LO16, AT); | |
5519 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
5520 | treg, 8); | |
5521 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
5522 | treg, AT); | |
670a50eb | 5523 | break; |
3d3c5039 ILT |
5524 | |
5525 | case M_USH: | |
8ea7f4e8 ILT |
5526 | if (offset_expr.X_add_number >= 0x7fff) |
5527 | as_bad ("operand overflow"); | |
5528 | if (byte_order == BIG_ENDIAN) | |
5529 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5530 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 5531 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 5532 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
8ea7f4e8 ILT |
5533 | if (byte_order == BIG_ENDIAN) |
5534 | offset_expr.X_add_number -= 1; | |
5535 | else | |
5536 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5537 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 5538 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5539 | break; |
3d3c5039 | 5540 | |
adcf2b9d ILT |
5541 | case M_USD: |
5542 | s = "sdl"; | |
5543 | s2 = "sdr"; | |
5544 | off = 7; | |
5545 | goto usw; | |
3d3c5039 | 5546 | case M_USW: |
adcf2b9d ILT |
5547 | s = "swl"; |
5548 | s2 = "swr"; | |
5549 | off = 3; | |
5550 | usw: | |
5551 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 ILT |
5552 | as_bad ("operand overflow"); |
5553 | if (byte_order == LITTLE_ENDIAN) | |
adcf2b9d ILT |
5554 | offset_expr.X_add_number += off; |
5555 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 5556 | (int) BFD_RELOC_LO16, breg); |
8ea7f4e8 | 5557 | if (byte_order == LITTLE_ENDIAN) |
adcf2b9d | 5558 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 5559 | else |
adcf2b9d ILT |
5560 | offset_expr.X_add_number += off; |
5561 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 5562 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5563 | return; |
3d3c5039 | 5564 | |
adcf2b9d ILT |
5565 | case M_USD_A: |
5566 | s = "sdl"; | |
5567 | s2 = "sdr"; | |
5568 | off = 7; | |
5569 | goto uswa; | |
3d3c5039 | 5570 | case M_USW_A: |
adcf2b9d ILT |
5571 | s = "swl"; |
5572 | s2 = "swr"; | |
5573 | off = 3; | |
5574 | uswa: | |
0dd2d296 | 5575 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
5576 | if (breg != 0) |
5577 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5578 | mips_isa < 3 ? "addu" : "daddu", | |
5579 | "d,v,t", AT, AT, breg); | |
adcf2b9d ILT |
5580 | if (byte_order == LITTLE_ENDIAN) |
5581 | expr1.X_add_number = off; | |
670a50eb | 5582 | else |
adcf2b9d ILT |
5583 | expr1.X_add_number = 0; |
5584 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
5585 | (int) BFD_RELOC_LO16, AT); | |
5586 | if (byte_order == LITTLE_ENDIAN) | |
5587 | expr1.X_add_number = 0; | |
5588 | else | |
5589 | expr1.X_add_number = off; | |
5590 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
5591 | (int) BFD_RELOC_LO16, AT); | |
5592 | break; | |
5593 | ||
5594 | case M_USH_A: | |
5595 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
5596 | if (breg != 0) |
5597 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5598 | mips_isa < 3 ? "addu" : "daddu", | |
5599 | "d,v,t", AT, AT, breg); | |
adcf2b9d ILT |
5600 | if (byte_order == LITTLE_ENDIAN) |
5601 | expr1.X_add_number = 0; | |
5602 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
5603 | (int) BFD_RELOC_LO16, AT); | |
5604 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
5605 | treg, 8); | |
5606 | if (byte_order == LITTLE_ENDIAN) | |
5607 | expr1.X_add_number = 1; | |
5608 | else | |
5609 | expr1.X_add_number = 0; | |
5610 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
5611 | (int) BFD_RELOC_LO16, AT); | |
5612 | if (byte_order == LITTLE_ENDIAN) | |
5613 | expr1.X_add_number = 0; | |
5614 | else | |
5615 | expr1.X_add_number = 1; | |
5616 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
5617 | (int) BFD_RELOC_LO16, AT); | |
5618 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
5619 | treg, 8); | |
5620 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
5621 | treg, AT); | |
670a50eb | 5622 | break; |
3d3c5039 ILT |
5623 | |
5624 | default: | |
670a50eb | 5625 | as_bad ("Macro %s not implemented yet", ip->insn_mo->name); |
8358c818 | 5626 | break; |
3d3c5039 | 5627 | } |
670a50eb ILT |
5628 | if (mips_noat) |
5629 | as_warn ("Macro used $at after \".set noat\""); | |
3d3c5039 ILT |
5630 | } |
5631 | ||
cc5703cd | 5632 | /* Implement macros in mips16 mode. */ |
3d3c5039 | 5633 | |
3d3c5039 | 5634 | static void |
cc5703cd | 5635 | mips16_macro (ip) |
3d3c5039 ILT |
5636 | struct mips_cl_insn *ip; |
5637 | { | |
cc5703cd ILT |
5638 | int mask; |
5639 | int xreg, yreg, zreg, tmp; | |
5640 | int icnt; | |
5641 | expressionS expr1; | |
5642 | int dbl; | |
5643 | const char *s, *s2, *s3; | |
3d3c5039 | 5644 | |
cc5703cd | 5645 | mask = ip->insn_mo->mask; |
3d3c5039 | 5646 | |
cc5703cd ILT |
5647 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
5648 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
5649 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
8358c818 | 5650 | |
cc5703cd | 5651 | icnt = 0; |
8358c818 | 5652 | |
cc5703cd ILT |
5653 | expr1.X_op = O_constant; |
5654 | expr1.X_op_symbol = NULL; | |
5655 | expr1.X_add_symbol = NULL; | |
5656 | expr1.X_add_number = 1; | |
8358c818 | 5657 | |
cc5703cd | 5658 | dbl = 0; |
517078c1 | 5659 | |
cc5703cd ILT |
5660 | switch (mask) |
5661 | { | |
5662 | default: | |
5663 | internalError (); | |
5664 | ||
5665 | case M_DDIV_3: | |
5666 | dbl = 1; | |
5667 | case M_DIV_3: | |
5668 | s = "mflo"; | |
5669 | goto do_div3; | |
5670 | case M_DREM_3: | |
5671 | dbl = 1; | |
5672 | case M_REM_3: | |
5673 | s = "mfhi"; | |
5674 | do_div3: | |
5675 | mips_emit_delays (); | |
5676 | ++mips_noreorder; | |
5677 | mips_any_noreorder = 1; | |
5678 | macro_build ((char *) NULL, &icnt, NULL, | |
5679 | dbl ? "ddiv" : "div", | |
5680 | "0,x,y", xreg, yreg); | |
5681 | expr1.X_add_number = 4; | |
5682 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
5683 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
5684 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); | |
5685 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, | |
5686 | since that causes an overflow. We should do that as well, | |
5687 | but I don't see how to do the comparisons without a temporary | |
5688 | register. */ | |
5689 | --mips_noreorder; | |
5690 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); | |
5691 | break; | |
5692 | ||
5693 | case M_DIVU_3: | |
5694 | s = "divu"; | |
5695 | s2 = "mflo"; | |
5696 | goto do_divu3; | |
5697 | case M_REMU_3: | |
5698 | s = "divu"; | |
5699 | s2 = "mfhi"; | |
5700 | goto do_divu3; | |
5701 | case M_DDIVU_3: | |
5702 | s = "ddivu"; | |
5703 | s2 = "mflo"; | |
5704 | goto do_divu3; | |
5705 | case M_DREMU_3: | |
5706 | s = "ddivu"; | |
5707 | s2 = "mfhi"; | |
5708 | do_divu3: | |
5709 | mips_emit_delays (); | |
5710 | ++mips_noreorder; | |
5711 | mips_any_noreorder = 1; | |
5712 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
5713 | expr1.X_add_number = 4; | |
5714 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
5715 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5716 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); | |
5717 | --mips_noreorder; | |
5718 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); | |
5719 | break; | |
5720 | ||
5721 | case M_DSUBU_I: | |
5722 | dbl = 1; | |
5723 | goto do_subu; | |
5724 | case M_SUBU_I: | |
5725 | do_subu: | |
5726 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
5727 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
5728 | dbl ? "daddiu" : "addiu", | |
5729 | "y,x,4", yreg, xreg); | |
5730 | break; | |
5731 | ||
5732 | case M_SUBU_I_2: | |
5733 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
5734 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
5735 | "x,k", xreg); | |
5736 | break; | |
5737 | ||
5738 | case M_DSUBU_I_2: | |
5739 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
5740 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
5741 | "y,j", yreg); | |
5742 | break; | |
5743 | ||
5744 | case M_BEQ: | |
5745 | s = "cmp"; | |
5746 | s2 = "bteqz"; | |
5747 | goto do_branch; | |
5748 | case M_BNE: | |
5749 | s = "cmp"; | |
5750 | s2 = "btnez"; | |
5751 | goto do_branch; | |
5752 | case M_BLT: | |
5753 | s = "slt"; | |
5754 | s2 = "btnez"; | |
5755 | goto do_branch; | |
5756 | case M_BLTU: | |
5757 | s = "sltu"; | |
5758 | s2 = "btnez"; | |
5759 | goto do_branch; | |
5760 | case M_BLE: | |
5761 | s = "slt"; | |
5762 | s2 = "bteqz"; | |
5763 | goto do_reverse_branch; | |
5764 | case M_BLEU: | |
5765 | s = "sltu"; | |
5766 | s2 = "bteqz"; | |
5767 | goto do_reverse_branch; | |
5768 | case M_BGE: | |
5769 | s = "slt"; | |
5770 | s2 = "bteqz"; | |
5771 | goto do_branch; | |
5772 | case M_BGEU: | |
5773 | s = "sltu"; | |
5774 | s2 = "bteqz"; | |
5775 | goto do_branch; | |
5776 | case M_BGT: | |
5777 | s = "slt"; | |
5778 | s2 = "btnez"; | |
5779 | goto do_reverse_branch; | |
5780 | case M_BGTU: | |
5781 | s = "sltu"; | |
5782 | s2 = "btnez"; | |
5783 | ||
5784 | do_reverse_branch: | |
5785 | tmp = xreg; | |
5786 | xreg = yreg; | |
5787 | yreg = tmp; | |
5788 | ||
5789 | do_branch: | |
5790 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
5791 | xreg, yreg); | |
5792 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
5793 | break; | |
5794 | ||
5795 | case M_BEQ_I: | |
5796 | s = "cmpi"; | |
5797 | s2 = "bteqz"; | |
5798 | s3 = "x,U"; | |
5799 | goto do_branch_i; | |
5800 | case M_BNE_I: | |
5801 | s = "cmpi"; | |
5802 | s2 = "btnez"; | |
5803 | s3 = "x,U"; | |
5804 | goto do_branch_i; | |
5805 | case M_BLT_I: | |
5806 | s = "slti"; | |
5807 | s2 = "btnez"; | |
5808 | s3 = "x,8"; | |
5809 | goto do_branch_i; | |
5810 | case M_BLTU_I: | |
5811 | s = "sltiu"; | |
5812 | s2 = "btnez"; | |
5813 | s3 = "x,8"; | |
5814 | goto do_branch_i; | |
5815 | case M_BLE_I: | |
5816 | s = "slti"; | |
5817 | s2 = "btnez"; | |
5818 | s3 = "x,8"; | |
5819 | goto do_addone_branch_i; | |
5820 | case M_BLEU_I: | |
5821 | s = "sltiu"; | |
5822 | s2 = "btnez"; | |
5823 | s3 = "x,8"; | |
5824 | goto do_addone_branch_i; | |
5825 | case M_BGE_I: | |
5826 | s = "slti"; | |
5827 | s2 = "bteqz"; | |
5828 | s3 = "x,8"; | |
5829 | goto do_branch_i; | |
5830 | case M_BGEU_I: | |
5831 | s = "sltiu"; | |
5832 | s2 = "bteqz"; | |
5833 | s3 = "x,8"; | |
5834 | goto do_branch_i; | |
5835 | case M_BGT_I: | |
5836 | s = "slti"; | |
5837 | s2 = "bteqz"; | |
5838 | s3 = "x,8"; | |
5839 | goto do_addone_branch_i; | |
5840 | case M_BGTU_I: | |
5841 | s = "sltiu"; | |
5842 | s2 = "bteqz"; | |
5843 | s3 = "x,8"; | |
5844 | ||
5845 | do_addone_branch_i: | |
5846 | ++imm_expr.X_add_number; | |
5847 | ||
5848 | do_branch_i: | |
5849 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
5850 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
5851 | break; | |
5852 | } | |
5853 | } | |
5854 | ||
5855 | /* This routine assembles an instruction into its binary format. As a | |
5856 | side effect, it sets one of the global variables imm_reloc or | |
5857 | offset_reloc to the type of relocation to do if one of the operands | |
5858 | is an address expression. */ | |
5859 | ||
5860 | static void | |
5861 | mips_ip (str, ip) | |
5862 | char *str; | |
5863 | struct mips_cl_insn *ip; | |
5864 | { | |
5865 | char *s; | |
5866 | const char *args; | |
5867 | char c; | |
5868 | struct mips_opcode *insn; | |
5869 | char *argsStart; | |
5870 | unsigned int regno; | |
5871 | unsigned int lastregno = 0; | |
5872 | char *s_reset; | |
5873 | ||
5874 | insn_error = NULL; | |
5875 | ||
5876 | for (s = str; islower (*s) || (*s >= '0' && *s <= '3') || *s == '6' || *s == '.'; ++s) | |
5877 | continue; | |
5878 | switch (*s) | |
5879 | { | |
5880 | case '\0': | |
5881 | break; | |
5882 | ||
5883 | case ' ': | |
5884 | *s++ = '\0'; | |
5885 | break; | |
5886 | ||
5887 | default: | |
5888 | as_fatal ("Unknown opcode: `%s'", str); | |
5889 | } | |
5890 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
5891 | { | |
5892 | insn_error = "unrecognized opcode"; | |
5893 | return; | |
5894 | } | |
5895 | argsStart = s; | |
5896 | for (;;) | |
5897 | { | |
5898 | int insn_isa; | |
5899 | ||
5900 | assert (strcmp (insn->name, str) == 0); | |
5901 | ||
5902 | if (insn->pinfo == INSN_MACRO) | |
5903 | insn_isa = insn->match; | |
5904 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA2) | |
5905 | insn_isa = 2; | |
5906 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA3) | |
5907 | insn_isa = 3; | |
5908 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA4) | |
5909 | insn_isa = 4; | |
5910 | else | |
5911 | insn_isa = 1; | |
5912 | ||
5913 | if (insn_isa > mips_isa | |
5914 | || ((insn->pinfo & INSN_ISA) == INSN_4650 | |
5915 | && ! mips_4650) | |
5916 | || ((insn->pinfo & INSN_ISA) == INSN_4010 | |
5917 | && ! mips_4010) | |
5918 | || ((insn->pinfo & INSN_ISA) == INSN_4100 | |
5919 | && ! mips_4100)) | |
5920 | { | |
5921 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
5922 | && strcmp (insn->name, insn[1].name) == 0) | |
5923 | { | |
5924 | ++insn; | |
5925 | continue; | |
5926 | } | |
5927 | if (insn_isa <= mips_isa) | |
5928 | insn_error = "opcode not supported on this processor"; | |
5929 | else | |
5930 | { | |
5931 | static char buf[100]; | |
5932 | ||
5933 | sprintf (buf, "opcode requires -mips%d or greater", insn_isa); | |
5934 | insn_error = buf; | |
5935 | } | |
5936 | return; | |
5937 | } | |
8358c818 | 5938 | |
670a50eb ILT |
5939 | ip->insn_mo = insn; |
5940 | ip->insn_opcode = insn->match; | |
5941 | for (args = insn->args;; ++args) | |
5942 | { | |
5943 | if (*s == ' ') | |
5944 | ++s; | |
5945 | switch (*args) | |
5946 | { | |
5947 | case '\0': /* end of args */ | |
5948 | if (*s == '\0') | |
5949 | return; | |
5950 | break; | |
3d3c5039 ILT |
5951 | |
5952 | case ',': | |
670a50eb ILT |
5953 | if (*s++ == *args) |
5954 | continue; | |
5955 | s--; | |
5956 | switch (*++args) | |
5957 | { | |
3d3c5039 ILT |
5958 | case 'r': |
5959 | case 'v': | |
670a50eb ILT |
5960 | ip->insn_opcode |= lastregno << 21; |
5961 | continue; | |
3d3c5039 ILT |
5962 | |
5963 | case 'w': | |
5964 | case 'W': | |
670a50eb ILT |
5965 | ip->insn_opcode |= lastregno << 16; |
5966 | continue; | |
3d3c5039 ILT |
5967 | |
5968 | case 'V': | |
670a50eb ILT |
5969 | ip->insn_opcode |= lastregno << 11; |
5970 | continue; | |
3d3c5039 | 5971 | } |
670a50eb | 5972 | break; |
3d3c5039 ILT |
5973 | |
5974 | case '(': | |
670a50eb ILT |
5975 | /* handle optional base register. |
5976 | Either the base register is omitted or | |
5977 | we must have a left paren. */ | |
5978 | /* this is dependent on the next operand specifier | |
5979 | is a 'b' for base register */ | |
5980 | assert (args[1] == 'b'); | |
5981 | if (*s == '\0') | |
5982 | return; | |
3d3c5039 | 5983 | |
670a50eb ILT |
5984 | case ')': /* these must match exactly */ |
5985 | if (*s++ == *args) | |
3d3c5039 | 5986 | continue; |
670a50eb ILT |
5987 | break; |
5988 | ||
5989 | case '<': /* must be at least one digit */ | |
5990 | /* | |
5991 | * According to the manual, if the shift amount is greater | |
5992 | * than 31 or less than 0 the the shift amount should be | |
5993 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 5994 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
5995 | */ |
5996 | my_getExpression (&imm_expr, s); | |
5997 | check_absolute_expr (ip, &imm_expr); | |
5998 | if ((unsigned long) imm_expr.X_add_number > 31) | |
5999 | { | |
58d4951d ILT |
6000 | as_warn ("Improper shift amount (%ld)", |
6001 | (long) imm_expr.X_add_number); | |
9226253a | 6002 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
6003 | } |
6004 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 6005 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6006 | s = expr_end; |
6007 | continue; | |
6008 | ||
56c96faa ILT |
6009 | case '>': /* shift amount minus 32 */ |
6010 | my_getExpression (&imm_expr, s); | |
6011 | check_absolute_expr (ip, &imm_expr); | |
6012 | if ((unsigned long) imm_expr.X_add_number < 32 | |
6013 | || (unsigned long) imm_expr.X_add_number > 63) | |
6014 | break; | |
6015 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
6016 | imm_expr.X_op = O_absent; | |
6017 | s = expr_end; | |
6018 | continue; | |
6019 | ||
9226253a | 6020 | case 'k': /* cache code */ |
d8a1c247 | 6021 | case 'h': /* prefx code */ |
9226253a ILT |
6022 | my_getExpression (&imm_expr, s); |
6023 | check_absolute_expr (ip, &imm_expr); | |
6024 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6025 | { | |
d8a1c247 KR |
6026 | as_warn ("Invalid value for `%s' (%lu)", |
6027 | ip->insn_mo->name, | |
9226253a ILT |
6028 | (unsigned long) imm_expr.X_add_number); |
6029 | imm_expr.X_add_number &= 0x1f; | |
6030 | } | |
d8a1c247 KR |
6031 | if (*args == 'k') |
6032 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
6033 | else | |
6034 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
9226253a ILT |
6035 | imm_expr.X_op = O_absent; |
6036 | s = expr_end; | |
6037 | continue; | |
6038 | ||
670a50eb ILT |
6039 | case 'c': /* break code */ |
6040 | my_getExpression (&imm_expr, s); | |
6041 | check_absolute_expr (ip, &imm_expr); | |
6042 | if ((unsigned) imm_expr.X_add_number > 1023) | |
58d4951d ILT |
6043 | as_warn ("Illegal break code (%ld)", |
6044 | (long) imm_expr.X_add_number); | |
670a50eb | 6045 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 6046 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6047 | s = expr_end; |
6048 | continue; | |
6049 | ||
918692a5 ILT |
6050 | case 'B': /* syscall code */ |
6051 | my_getExpression (&imm_expr, s); | |
6052 | check_absolute_expr (ip, &imm_expr); | |
6053 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
58d4951d ILT |
6054 | as_warn ("Illegal syscall code (%ld)", |
6055 | (long) imm_expr.X_add_number); | |
918692a5 | 6056 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 6057 | imm_expr.X_op = O_absent; |
918692a5 ILT |
6058 | s = expr_end; |
6059 | continue; | |
6060 | ||
0aa07269 ILT |
6061 | case 'C': /* Coprocessor code */ |
6062 | my_getExpression (&imm_expr, s); | |
6063 | check_absolute_expr (ip, &imm_expr); | |
6064 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
6065 | { | |
58d4951d ILT |
6066 | as_warn ("Coproccesor code > 25 bits (%ld)", |
6067 | (long) imm_expr.X_add_number); | |
0aa07269 ILT |
6068 | imm_expr.X_add_number &= ((1<<25) - 1); |
6069 | } | |
6070 | ip->insn_opcode |= imm_expr.X_add_number; | |
6071 | imm_expr.X_op = O_absent; | |
6072 | s = expr_end; | |
6073 | continue; | |
6074 | ||
670a50eb ILT |
6075 | case 'b': /* base register */ |
6076 | case 'd': /* destination register */ | |
6077 | case 's': /* source register */ | |
6078 | case 't': /* target register */ | |
6079 | case 'r': /* both target and source */ | |
6080 | case 'v': /* both dest and source */ | |
6081 | case 'w': /* both dest and target */ | |
918692a5 ILT |
6082 | case 'E': /* coprocessor target register */ |
6083 | case 'G': /* coprocessor destination register */ | |
8358c818 | 6084 | case 'x': /* ignore register name */ |
ff3a5c18 | 6085 | case 'z': /* must be zero register */ |
670a50eb ILT |
6086 | s_reset = s; |
6087 | if (s[0] == '$') | |
6088 | { | |
6089 | if (isdigit (s[1])) | |
6090 | { | |
6091 | ++s; | |
6092 | regno = 0; | |
6093 | do | |
6094 | { | |
6095 | regno *= 10; | |
6096 | regno += *s - '0'; | |
6097 | ++s; | |
6098 | } | |
6099 | while (isdigit (*s)); | |
0aa07269 ILT |
6100 | if (regno > 31) |
6101 | as_bad ("Invalid register number (%d)", regno); | |
670a50eb | 6102 | } |
0dd2d296 ILT |
6103 | else if (*args == 'E' || *args == 'G') |
6104 | goto notreg; | |
6105 | else | |
670a50eb | 6106 | { |
0aa07269 ILT |
6107 | if (s[1] == 'f' && s[2] == 'p') |
6108 | { | |
6109 | s += 3; | |
9226253a | 6110 | regno = FP; |
0aa07269 ILT |
6111 | } |
6112 | else if (s[1] == 's' && s[2] == 'p') | |
6113 | { | |
6114 | s += 3; | |
9226253a | 6115 | regno = SP; |
0aa07269 ILT |
6116 | } |
6117 | else if (s[1] == 'g' && s[2] == 'p') | |
6118 | { | |
6119 | s += 3; | |
9226253a | 6120 | regno = GP; |
0aa07269 ILT |
6121 | } |
6122 | else if (s[1] == 'a' && s[2] == 't') | |
6123 | { | |
6124 | s += 3; | |
9226253a | 6125 | regno = AT; |
0aa07269 | 6126 | } |
b2b8c24e ILT |
6127 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
6128 | { | |
6129 | s += 4; | |
6130 | regno = KT0; | |
6131 | } | |
6132 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
6133 | { | |
6134 | s += 4; | |
6135 | regno = KT1; | |
6136 | } | |
0aa07269 ILT |
6137 | else |
6138 | goto notreg; | |
670a50eb | 6139 | } |
9753202d ILT |
6140 | if (regno == AT |
6141 | && ! mips_noat | |
6142 | && *args != 'E' | |
6143 | && *args != 'G') | |
13fe1379 | 6144 | as_warn ("Used $at without \".set noat\""); |
670a50eb ILT |
6145 | c = *args; |
6146 | if (*s == ' ') | |
6147 | s++; | |
6148 | if (args[1] != *s) | |
6149 | { | |
6150 | if (c == 'r' || c == 'v' || c == 'w') | |
6151 | { | |
6152 | regno = lastregno; | |
6153 | s = s_reset; | |
6154 | args++; | |
6155 | } | |
6156 | } | |
ff3a5c18 ILT |
6157 | /* 'z' only matches $0. */ |
6158 | if (c == 'z' && regno != 0) | |
6159 | break; | |
670a50eb ILT |
6160 | switch (c) |
6161 | { | |
3d3c5039 ILT |
6162 | case 'r': |
6163 | case 's': | |
6164 | case 'v': | |
6165 | case 'b': | |
670a50eb ILT |
6166 | ip->insn_opcode |= regno << 21; |
6167 | break; | |
3d3c5039 | 6168 | case 'd': |
918692a5 | 6169 | case 'G': |
670a50eb ILT |
6170 | ip->insn_opcode |= regno << 11; |
6171 | break; | |
3d3c5039 ILT |
6172 | case 'w': |
6173 | case 't': | |
918692a5 | 6174 | case 'E': |
670a50eb | 6175 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
6176 | break; |
6177 | case 'x': | |
6178 | /* This case exists because on the r3000 trunc | |
6179 | expands into a macro which requires a gp | |
6180 | register. On the r6000 or r4000 it is | |
6181 | assembled into a single instruction which | |
6182 | ignores the register. Thus the insn version | |
6183 | is MIPS_ISA2 and uses 'x', and the macro | |
6184 | version is MIPS_ISA1 and uses 't'. */ | |
6185 | break; | |
ff3a5c18 ILT |
6186 | case 'z': |
6187 | /* This case is for the div instruction, which | |
6188 | acts differently if the destination argument | |
6189 | is $0. This only matches $0, and is checked | |
6190 | outside the switch. */ | |
6191 | break; | |
3d3c5039 | 6192 | } |
670a50eb ILT |
6193 | lastregno = regno; |
6194 | continue; | |
3d3c5039 ILT |
6195 | } |
6196 | notreg: | |
670a50eb ILT |
6197 | switch (*args++) |
6198 | { | |
3d3c5039 ILT |
6199 | case 'r': |
6200 | case 'v': | |
670a50eb ILT |
6201 | ip->insn_opcode |= lastregno << 21; |
6202 | continue; | |
3d3c5039 | 6203 | case 'w': |
670a50eb ILT |
6204 | ip->insn_opcode |= lastregno << 16; |
6205 | continue; | |
3d3c5039 | 6206 | } |
670a50eb | 6207 | break; |
3d3c5039 | 6208 | |
670a50eb ILT |
6209 | case 'D': /* floating point destination register */ |
6210 | case 'S': /* floating point source register */ | |
6211 | case 'T': /* floating point target register */ | |
d8a1c247 | 6212 | case 'R': /* floating point source register */ |
3d3c5039 ILT |
6213 | case 'V': |
6214 | case 'W': | |
670a50eb ILT |
6215 | s_reset = s; |
6216 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
6217 | { | |
6218 | s += 2; | |
6219 | regno = 0; | |
6220 | do | |
6221 | { | |
6222 | regno *= 10; | |
6223 | regno += *s - '0'; | |
6224 | ++s; | |
6225 | } | |
6226 | while (isdigit (*s)); | |
6227 | ||
6228 | if (regno > 31) | |
6229 | as_bad ("Invalid float register number (%d)", regno); | |
6230 | ||
9226253a ILT |
6231 | if ((regno & 1) != 0 |
6232 | && mips_isa < 3 | |
538034cf ILT |
6233 | && ! (strcmp (str, "mtc1") == 0 |
6234 | || strcmp (str, "mfc1") == 0 | |
6235 | || strcmp (str, "lwc1") == 0 | |
6236 | || strcmp (str, "swc1") == 0 | |
6237 | || strcmp (str, "l.s") == 0 | |
6238 | || strcmp (str, "s.s") == 0)) | |
670a50eb ILT |
6239 | as_warn ("Float register should be even, was %d", |
6240 | regno); | |
6241 | ||
6242 | c = *args; | |
6243 | if (*s == ' ') | |
6244 | s++; | |
6245 | if (args[1] != *s) | |
6246 | { | |
6247 | if (c == 'V' || c == 'W') | |
6248 | { | |
6249 | regno = lastregno; | |
6250 | s = s_reset; | |
6251 | args++; | |
3d3c5039 ILT |
6252 | } |
6253 | } | |
670a50eb ILT |
6254 | switch (c) |
6255 | { | |
3d3c5039 | 6256 | case 'D': |
670a50eb ILT |
6257 | ip->insn_opcode |= regno << 6; |
6258 | break; | |
3d3c5039 ILT |
6259 | case 'V': |
6260 | case 'S': | |
670a50eb ILT |
6261 | ip->insn_opcode |= regno << 11; |
6262 | break; | |
3d3c5039 ILT |
6263 | case 'W': |
6264 | case 'T': | |
670a50eb | 6265 | ip->insn_opcode |= regno << 16; |
d8a1c247 KR |
6266 | break; |
6267 | case 'R': | |
6268 | ip->insn_opcode |= regno << 21; | |
6269 | break; | |
3d3c5039 | 6270 | } |
670a50eb ILT |
6271 | lastregno = regno; |
6272 | continue; | |
3d3c5039 | 6273 | } |
670a50eb ILT |
6274 | switch (*args++) |
6275 | { | |
3d3c5039 | 6276 | case 'V': |
670a50eb ILT |
6277 | ip->insn_opcode |= lastregno << 11; |
6278 | continue; | |
3d3c5039 | 6279 | case 'W': |
670a50eb ILT |
6280 | ip->insn_opcode |= lastregno << 16; |
6281 | continue; | |
3d3c5039 | 6282 | } |
670a50eb | 6283 | break; |
3d3c5039 ILT |
6284 | |
6285 | case 'I': | |
670a50eb | 6286 | my_getExpression (&imm_expr, s); |
9753202d ILT |
6287 | if (imm_expr.X_op != O_big |
6288 | && imm_expr.X_op != O_constant) | |
6289 | insn_error = "absolute expression required"; | |
670a50eb ILT |
6290 | s = expr_end; |
6291 | continue; | |
3d3c5039 ILT |
6292 | |
6293 | case 'A': | |
670a50eb ILT |
6294 | my_getExpression (&offset_expr, s); |
6295 | imm_reloc = BFD_RELOC_32; | |
6296 | s = expr_end; | |
6297 | continue; | |
3d3c5039 ILT |
6298 | |
6299 | case 'F': | |
19ed8960 ILT |
6300 | case 'L': |
6301 | case 'f': | |
6302 | case 'l': | |
6303 | { | |
6304 | int f64; | |
6305 | char *save_in; | |
6306 | char *err; | |
6307 | unsigned char temp[8]; | |
604633ae ILT |
6308 | int len; |
6309 | unsigned int length; | |
19ed8960 ILT |
6310 | segT seg; |
6311 | subsegT subseg; | |
6312 | char *p; | |
6313 | ||
6314 | /* These only appear as the last operand in an | |
6315 | instruction, and every instruction that accepts | |
6316 | them in any variant accepts them in all variants. | |
6317 | This means we don't have to worry about backing out | |
6318 | any changes if the instruction does not match. | |
6319 | ||
6320 | The difference between them is the size of the | |
6321 | floating point constant and where it goes. For 'F' | |
6322 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
6323 | is 32 bits. Where the constant is placed is based | |
6324 | on how the MIPS assembler does things: | |
6325 | F -- .rdata | |
6326 | L -- .lit8 | |
6327 | f -- immediate value | |
6328 | l -- .lit4 | |
0dd2d296 | 6329 | |
55933a58 ILT |
6330 | The .lit4 and .lit8 sections are only used if |
6331 | permitted by the -G argument. | |
6332 | ||
6333 | When generating embedded PIC code, we use the | |
6334 | .lit8 section but not the .lit4 section (we can do | |
6335 | .lit4 inline easily; we need to put .lit8 | |
6336 | somewhere in the data segment, and using .lit8 | |
6337 | permits the linker to eventually combine identical | |
6338 | .lit8 entries). */ | |
19ed8960 ILT |
6339 | |
6340 | f64 = *args == 'F' || *args == 'L'; | |
6341 | ||
6342 | save_in = input_line_pointer; | |
6343 | input_line_pointer = s; | |
604633ae ILT |
6344 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
6345 | length = len; | |
19ed8960 ILT |
6346 | s = input_line_pointer; |
6347 | input_line_pointer = save_in; | |
6348 | if (err != NULL && *err != '\0') | |
6349 | { | |
6350 | as_bad ("Bad floating point constant: %s", err); | |
6351 | memset (temp, '\0', sizeof temp); | |
6352 | length = f64 ? 8 : 4; | |
6353 | } | |
6354 | ||
6355 | assert (length == (f64 ? 8 : 4)); | |
6356 | ||
0dd2d296 | 6357 | if (*args == 'f' |
55933a58 | 6358 | || (*args == 'l' |
1dc1e798 KR |
6359 | && (! USE_GLOBAL_POINTER_OPT |
6360 | || mips_pic == EMBEDDED_PIC | |
1113140a | 6361 | || g_switch_value < 4) |
1113140a | 6362 | )) |
19ed8960 ILT |
6363 | { |
6364 | imm_expr.X_op = O_constant; | |
6365 | if (byte_order == LITTLE_ENDIAN) | |
6366 | imm_expr.X_add_number = | |
6367 | (((((((int) temp[3] << 8) | |
6368 | | temp[2]) << 8) | |
6369 | | temp[1]) << 8) | |
6370 | | temp[0]); | |
6371 | else | |
6372 | imm_expr.X_add_number = | |
6373 | (((((((int) temp[0] << 8) | |
6374 | | temp[1]) << 8) | |
6375 | | temp[2]) << 8) | |
6376 | | temp[3]); | |
6377 | } | |
6378 | else | |
6379 | { | |
0dd2d296 ILT |
6380 | const char *newname; |
6381 | segT new_seg; | |
6382 | ||
19ed8960 ILT |
6383 | /* Switch to the right section. */ |
6384 | seg = now_seg; | |
6385 | subseg = now_subseg; | |
6386 | switch (*args) | |
6387 | { | |
0dd2d296 | 6388 | default: /* unused default case avoids warnings. */ |
19ed8960 | 6389 | case 'L': |
1113140a | 6390 | newname = RDATA_SECTION_NAME; |
1dc1e798 | 6391 | if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
1113140a | 6392 | newname = ".lit8"; |
0dd2d296 ILT |
6393 | break; |
6394 | case 'F': | |
d2c71068 | 6395 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
6396 | break; |
6397 | case 'l': | |
1dc1e798 KR |
6398 | assert (!USE_GLOBAL_POINTER_OPT |
6399 | || g_switch_value >= 4); | |
0dd2d296 | 6400 | newname = ".lit4"; |
19ed8960 ILT |
6401 | break; |
6402 | } | |
0dd2d296 | 6403 | new_seg = subseg_new (newname, (subsegT) 0); |
9b61d62b ILT |
6404 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
6405 | bfd_set_section_flags (stdoutput, new_seg, | |
6406 | (SEC_ALLOC | |
6407 | | SEC_LOAD | |
6408 | | SEC_READONLY | |
6409 | | SEC_DATA)); | |
0221ddf7 | 6410 | frag_align (*args == 'l' ? 2 : 3, 0); |
1dc1e798 KR |
6411 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
6412 | record_alignment (new_seg, 4); | |
6413 | else | |
6414 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
19ed8960 ILT |
6415 | if (seg == now_seg) |
6416 | as_bad ("Can't use floating point insn in this section"); | |
6417 | ||
6418 | /* Set the argument to the current address in the | |
6e8dda9c | 6419 | section. */ |
19ed8960 ILT |
6420 | offset_expr.X_op = O_symbol; |
6421 | offset_expr.X_add_symbol = | |
6422 | symbol_new ("L0\001", now_seg, | |
6423 | (valueT) frag_now_fix (), frag_now); | |
6424 | offset_expr.X_add_number = 0; | |
6425 | ||
6426 | /* Put the floating point number into the section. */ | |
604633ae | 6427 | p = frag_more ((int) length); |
19ed8960 ILT |
6428 | memcpy (p, temp, length); |
6429 | ||
6430 | /* Switch back to the original section. */ | |
6431 | subseg_set (seg, subseg); | |
6432 | } | |
6433 | } | |
670a50eb ILT |
6434 | continue; |
6435 | ||
6436 | case 'i': /* 16 bit unsigned immediate */ | |
6437 | case 'j': /* 16 bit signed immediate */ | |
6438 | imm_reloc = BFD_RELOC_LO16; | |
6439 | c = my_getSmallExpression (&imm_expr, s); | |
344a8d61 | 6440 | if (c != '\0') |
670a50eb ILT |
6441 | { |
6442 | if (c != 'l') | |
6443 | { | |
5ac34ac3 | 6444 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
6445 | imm_expr.X_add_number = |
6446 | (imm_expr.X_add_number >> 16) & 0xffff; | |
6447 | else if (c == 'h') | |
867a58b3 ILT |
6448 | { |
6449 | imm_reloc = BFD_RELOC_HI16_S; | |
6450 | imm_unmatched_hi = true; | |
6451 | } | |
670a50eb ILT |
6452 | else |
6453 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 6454 | } |
670a50eb | 6455 | } |
670a50eb ILT |
6456 | if (*args == 'i') |
6457 | { | |
344a8d61 | 6458 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
6459 | || ((imm_expr.X_add_number < 0 |
6460 | || imm_expr.X_add_number >= 0x10000) | |
6461 | && imm_expr.X_op == O_constant)) | |
99c24539 ILT |
6462 | { |
6463 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6464 | !strcmp (insn->name, insn[1].name)) | |
6465 | break; | |
9753202d ILT |
6466 | if (imm_expr.X_op != O_constant |
6467 | && imm_expr.X_op != O_big) | |
6468 | insn_error = "absolute expression required"; | |
6469 | else | |
6470 | as_bad ("16 bit expression not in range 0..65535"); | |
99c24539 | 6471 | } |
670a50eb ILT |
6472 | } |
6473 | else | |
6474 | { | |
d9aba805 ILT |
6475 | int more; |
6476 | offsetT max; | |
6477 | ||
be22008b ILT |
6478 | /* The upper bound should be 0x8000, but |
6479 | unfortunately the MIPS assembler accepts numbers | |
6480 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
6481 | we want to be compatible. We only permit this |
6482 | extended range for an instruction which does not | |
6483 | provide any further alternates, since those | |
6484 | alternates may handle other cases. People should | |
6485 | use the numbers they mean, rather than relying on | |
6486 | a mysterious sign extension. */ | |
6487 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6488 | strcmp (insn->name, insn[1].name) == 0); | |
6489 | if (more) | |
6490 | max = 0x8000; | |
6491 | else | |
6492 | max = 0x10000; | |
344a8d61 | 6493 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
6494 | || ((imm_expr.X_add_number < -0x8000 |
6495 | || imm_expr.X_add_number >= max) | |
6496 | && imm_expr.X_op == O_constant) | |
d8a1c247 KR |
6497 | || (more |
6498 | && imm_expr.X_add_number < 0 | |
6499 | && mips_isa >= 3 | |
6500 | && imm_expr.X_unsigned | |
6501 | && sizeof (imm_expr.X_add_number) <= 4)) | |
99c24539 | 6502 | { |
d9aba805 | 6503 | if (more) |
99c24539 | 6504 | break; |
9753202d ILT |
6505 | if (imm_expr.X_op != O_constant |
6506 | && imm_expr.X_op != O_big) | |
6507 | insn_error = "absolute expression required"; | |
6508 | else | |
6509 | as_bad ("16 bit expression not in range -32768..32767"); | |
99c24539 | 6510 | } |
3d3c5039 | 6511 | } |
670a50eb ILT |
6512 | s = expr_end; |
6513 | continue; | |
6514 | ||
6515 | case 'o': /* 16 bit offset */ | |
6516 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
6517 | |
6518 | /* If this value won't fit into a 16 bit offset, then go | |
6519 | find a macro that will generate the 32 bit offset | |
6520 | code pattern. As a special hack, we accept the | |
6521 | difference of two local symbols as a constant. This | |
6522 | is required to suppose embedded PIC switches, which | |
6523 | use an instruction which looks like | |
6524 | lw $4,$L12-$LS12($4) | |
6525 | The problem with handling this in a more general | |
6526 | fashion is that the macro function doesn't expect to | |
6527 | see anything which can be handled in a single | |
6528 | constant instruction. */ | |
6f0b87c3 SS |
6529 | if (c == 0 |
6530 | && (offset_expr.X_op != O_constant | |
6531 | || offset_expr.X_add_number >= 0x8000 | |
6532 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
6533 | && (mips_pic != EMBEDDED_PIC |
6534 | || offset_expr.X_op != O_subtract | |
9da4c5d1 ILT |
6535 | || now_seg != text_section |
6536 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
6537 | != text_section))) | |
670a50eb | 6538 | break; |
3d3c5039 | 6539 | |
670a50eb ILT |
6540 | offset_reloc = BFD_RELOC_LO16; |
6541 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
6542 | { |
6543 | assert (offset_expr.X_op == O_constant); | |
6544 | offset_expr.X_add_number = | |
6545 | (offset_expr.X_add_number >> 16) & 0xffff; | |
6546 | } | |
cc5703cd ILT |
6547 | s = expr_end; |
6548 | continue; | |
6549 | ||
6550 | case 'p': /* pc relative offset */ | |
6551 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
6552 | my_getExpression (&offset_expr, s); | |
6553 | s = expr_end; | |
6554 | continue; | |
6555 | ||
6556 | case 'u': /* upper 16 bits */ | |
6557 | c = my_getSmallExpression (&imm_expr, s); | |
6558 | if (imm_expr.X_op == O_constant | |
6559 | && (imm_expr.X_add_number < 0 | |
6560 | || imm_expr.X_add_number >= 0x10000)) | |
6561 | as_bad ("lui expression not in range 0..65535"); | |
6562 | imm_reloc = BFD_RELOC_LO16; | |
6563 | if (c) | |
6564 | { | |
6565 | if (c != 'l') | |
6566 | { | |
6567 | if (imm_expr.X_op == O_constant) | |
6568 | imm_expr.X_add_number = | |
6569 | (imm_expr.X_add_number >> 16) & 0xffff; | |
6570 | else if (c == 'h') | |
6571 | { | |
6572 | imm_reloc = BFD_RELOC_HI16_S; | |
6573 | imm_unmatched_hi = true; | |
6574 | } | |
6575 | else | |
6576 | imm_reloc = BFD_RELOC_HI16; | |
6577 | } | |
6578 | } | |
6579 | s = expr_end; | |
6580 | continue; | |
6581 | ||
6582 | case 'a': /* 26 bit address */ | |
6583 | my_getExpression (&offset_expr, s); | |
6584 | s = expr_end; | |
6585 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
6586 | continue; | |
6587 | ||
6588 | case 'N': /* 3 bit branch condition code */ | |
6589 | case 'M': /* 3 bit compare condition code */ | |
6590 | if (strncmp (s, "$fcc", 4) != 0) | |
6591 | break; | |
6592 | s += 4; | |
6593 | regno = 0; | |
6594 | do | |
6595 | { | |
6596 | regno *= 10; | |
6597 | regno += *s - '0'; | |
6598 | ++s; | |
6599 | } | |
6600 | while (isdigit (*s)); | |
6601 | if (regno > 7) | |
6602 | as_bad ("invalid condition code register $fcc%d", regno); | |
6603 | if (*args == 'N') | |
6604 | ip->insn_opcode |= regno << OP_SH_BCC; | |
6605 | else | |
6606 | ip->insn_opcode |= regno << OP_SH_CCC; | |
6607 | continue; | |
6608 | ||
6609 | default: | |
6610 | fprintf (stderr, "bad char = '%c'\n", *args); | |
6611 | internalError (); | |
6612 | } | |
6613 | break; | |
6614 | } | |
6615 | /* Args don't match. */ | |
6616 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6617 | !strcmp (insn->name, insn[1].name)) | |
6618 | { | |
6619 | ++insn; | |
6620 | s = argsStart; | |
6621 | continue; | |
6622 | } | |
6623 | insn_error = "illegal operands"; | |
6624 | return; | |
6625 | } | |
6626 | } | |
6627 | ||
6628 | /* This routine assembles an instruction into its binary format when | |
6629 | assembling for the mips16. As a side effect, it sets one of the | |
6630 | global variables imm_reloc or offset_reloc to the type of | |
6631 | relocation to do if one of the operands is an address expression. */ | |
6632 | ||
6633 | static void | |
6634 | mips16_ip (str, ip) | |
6635 | char *str; | |
6636 | struct mips_cl_insn *ip; | |
6637 | { | |
6638 | char *s; | |
6639 | boolean small, ext; | |
6640 | const char *args; | |
6641 | struct mips_opcode *insn; | |
6642 | char *argsstart; | |
6643 | unsigned int regno; | |
6644 | unsigned int lastregno = 0; | |
6645 | char *s_reset; | |
6646 | ||
6647 | insn_error = NULL; | |
6648 | ||
6649 | small = false; | |
6650 | ext = false; | |
6651 | ||
6652 | for (s = str; islower (*s); ++s) | |
6653 | ; | |
6654 | switch (*s) | |
6655 | { | |
6656 | case '\0': | |
6657 | break; | |
6658 | ||
6659 | case ' ': | |
6660 | *s++ = '\0'; | |
6661 | break; | |
6662 | ||
6663 | case '.': | |
6664 | if (s[1] == 't' && s[2] == ' ') | |
6665 | { | |
6666 | *s = '\0'; | |
6667 | small = true; | |
6668 | s += 3; | |
6669 | break; | |
6670 | } | |
6671 | else if (s[1] == 'e' && s[2] == ' ') | |
6672 | { | |
6673 | *s = '\0'; | |
6674 | ext = true; | |
6675 | s += 3; | |
6676 | break; | |
6677 | } | |
6678 | /* Fall through. */ | |
6679 | default: | |
6680 | insn_error = "unknown opcode"; | |
6681 | return; | |
6682 | } | |
6683 | ||
6684 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
6685 | { | |
6686 | insn_error = "unrecognized opcode"; | |
6687 | return; | |
6688 | } | |
6689 | ||
6690 | argsstart = s; | |
6691 | for (;;) | |
6692 | { | |
6693 | assert (strcmp (insn->name, str) == 0); | |
6694 | ||
6695 | ip->insn_mo = insn; | |
6696 | ip->insn_opcode = insn->match; | |
6697 | ip->use_extend = false; | |
6698 | imm_expr.X_op = O_absent; | |
6699 | imm_reloc = BFD_RELOC_UNUSED; | |
6700 | offset_expr.X_op = O_absent; | |
6701 | offset_reloc = BFD_RELOC_UNUSED; | |
6702 | for (args = insn->args; 1; ++args) | |
6703 | { | |
6704 | int c; | |
6705 | ||
6706 | if (*s == ' ') | |
6707 | ++s; | |
6708 | ||
6709 | /* In this switch statement we call break if we did not find | |
6710 | a match, continue if we did find a match, or return if we | |
6711 | are done. */ | |
6712 | ||
6713 | c = *args; | |
6714 | switch (c) | |
6715 | { | |
6716 | case '\0': | |
6717 | if (*s == '\0') | |
6718 | { | |
6719 | /* Stuff the immediate value in now, if we can. */ | |
6720 | if (imm_expr.X_op == O_constant | |
6721 | && imm_reloc > BFD_RELOC_UNUSED | |
6722 | && insn->pinfo != INSN_MACRO) | |
6723 | { | |
6724 | mips16_immed (imm_reloc - BFD_RELOC_UNUSED, | |
6725 | imm_expr.X_add_number, true, small, ext, | |
6726 | &ip->insn_opcode, &ip->use_extend, | |
6727 | &ip->extend); | |
6728 | imm_expr.X_op = O_absent; | |
6729 | imm_reloc = BFD_RELOC_UNUSED; | |
6730 | } | |
6731 | ||
6732 | return; | |
6733 | } | |
6734 | break; | |
6735 | ||
6736 | case ',': | |
6737 | if (*s++ == c) | |
6738 | continue; | |
6739 | s--; | |
6740 | switch (*++args) | |
6741 | { | |
6742 | case 'v': | |
6743 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
6744 | continue; | |
6745 | case 'w': | |
6746 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
6747 | continue; | |
6748 | } | |
6749 | break; | |
6750 | ||
6751 | case '(': | |
6752 | case ')': | |
6753 | if (*s++ == c) | |
6754 | continue; | |
6755 | break; | |
6756 | ||
6757 | case 'v': | |
6758 | case 'w': | |
6759 | if (s[0] != '$') | |
6760 | { | |
6761 | if (c == 'v') | |
6762 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
6763 | else | |
6764 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
6765 | ++args; | |
6766 | continue; | |
6767 | } | |
6768 | /* Fall through. */ | |
6769 | case 'x': | |
6770 | case 'y': | |
6771 | case 'z': | |
6772 | case 'Z': | |
6773 | case '0': | |
6774 | case 'S': | |
6775 | case 'R': | |
6776 | case 'X': | |
6777 | case 'Y': | |
6778 | if (s[0] != '$') | |
6779 | break; | |
6780 | s_reset = s; | |
6781 | if (isdigit (s[1])) | |
6782 | { | |
6783 | ++s; | |
6784 | regno = 0; | |
6785 | do | |
6786 | { | |
6787 | regno *= 10; | |
6788 | regno += *s - '0'; | |
6789 | ++s; | |
6790 | } | |
6791 | while (isdigit (*s)); | |
6792 | if (regno > 31) | |
6793 | { | |
6794 | as_bad ("invalid register number (%d)", regno); | |
6795 | regno = 2; | |
6796 | } | |
6797 | } | |
6798 | else | |
6799 | { | |
6800 | if (s[1] == 'f' && s[2] == 'p') | |
6801 | { | |
6802 | s += 3; | |
6803 | regno = FP; | |
6804 | } | |
6805 | else if (s[1] == 's' && s[2] == 'p') | |
6806 | { | |
6807 | s += 3; | |
6808 | regno = SP; | |
6809 | } | |
6810 | else if (s[1] == 'g' && s[2] == 'p') | |
6811 | { | |
6812 | s += 3; | |
6813 | regno = GP; | |
6814 | } | |
6815 | else if (s[1] == 'a' && s[2] == 't') | |
6816 | { | |
6817 | s += 3; | |
6818 | regno = AT; | |
6819 | } | |
6820 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
6821 | { | |
6822 | s += 4; | |
6823 | regno = KT0; | |
6824 | } | |
6825 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
6826 | { | |
6827 | s += 4; | |
6828 | regno = KT1; | |
6829 | } | |
6830 | else | |
6831 | break; | |
6832 | } | |
6833 | ||
6834 | if (*s == ' ') | |
6835 | ++s; | |
6836 | if (args[1] != *s) | |
6837 | { | |
6838 | if (c == 'v' || c == 'w') | |
6839 | { | |
6840 | regno = mips16_to_32_reg_map[lastregno]; | |
6841 | s = s_reset; | |
6842 | args++; | |
6843 | } | |
6844 | } | |
6845 | ||
6846 | switch (c) | |
6847 | { | |
6848 | case 'x': | |
6849 | case 'y': | |
6850 | case 'z': | |
6851 | case 'v': | |
6852 | case 'w': | |
6853 | case 'Z': | |
6854 | regno = mips32_to_16_reg_map[regno]; | |
6855 | break; | |
6856 | ||
6857 | case '0': | |
6858 | if (regno != 0) | |
6859 | regno = ILLEGAL_REG; | |
6860 | break; | |
6861 | ||
6862 | case 'S': | |
6863 | if (regno != SP) | |
6864 | regno = ILLEGAL_REG; | |
6865 | break; | |
6866 | ||
6867 | case 'R': | |
6868 | if (regno != RA) | |
6869 | regno = ILLEGAL_REG; | |
6870 | break; | |
6871 | ||
6872 | case 'X': | |
6873 | case 'Y': | |
6874 | if (regno == AT && ! mips_noat) | |
6875 | as_warn ("used $at without \".set noat\""); | |
6876 | break; | |
6877 | ||
6878 | default: | |
6879 | internalError (); | |
6880 | } | |
6881 | ||
6882 | if (regno == ILLEGAL_REG) | |
6883 | break; | |
6884 | ||
6885 | switch (c) | |
6886 | { | |
6887 | case 'x': | |
6888 | case 'v': | |
6889 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
6890 | break; | |
6891 | case 'y': | |
6892 | case 'w': | |
6893 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
6894 | break; | |
6895 | case 'z': | |
6896 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
6897 | break; | |
6898 | case 'Z': | |
6899 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
6900 | case '0': | |
6901 | case 'S': | |
6902 | case 'R': | |
6903 | break; | |
6904 | case 'X': | |
6905 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
6906 | break; | |
6907 | case 'Y': | |
6908 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
6909 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
6910 | break; | |
6911 | default: | |
6912 | internalError (); | |
6913 | } | |
6914 | ||
6915 | lastregno = regno; | |
6916 | continue; | |
6917 | ||
6918 | case 'P': | |
6919 | if (strncmp (s, "$pc", 3) == 0) | |
6920 | { | |
6921 | s += 3; | |
6922 | continue; | |
6923 | } | |
6924 | break; | |
6925 | ||
6926 | case '<': | |
6927 | case '>': | |
6928 | case '[': | |
6929 | case ']': | |
6930 | case '4': | |
6931 | case '5': | |
6932 | case 'H': | |
6933 | case 'W': | |
6934 | case 'D': | |
6935 | case 'j': | |
6936 | case '8': | |
6937 | case 'V': | |
6938 | case 'C': | |
6939 | case 'U': | |
6940 | case 'k': | |
6941 | case 'K': | |
6942 | if (s[0] == '$' && isdigit (s[1])) | |
6943 | { | |
6944 | /* Looks like a register name. */ | |
6945 | break; | |
6946 | } | |
6947 | my_getExpression (&imm_expr, s); | |
6948 | /* We need to relax this instruction. */ | |
6949 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
6950 | s = expr_end; | |
6951 | continue; | |
6952 | ||
6953 | case 'p': | |
6954 | case 'q': | |
6955 | case 'A': | |
6956 | case 'B': | |
6957 | case 'E': | |
6958 | /* We use offset_reloc rather than imm_reloc for the PC | |
6959 | relative operands. This lets macros with both | |
6960 | immediate and address operands work correctly. */ | |
6961 | if (s[0] == '$' && isdigit (s[1])) | |
6962 | { | |
6963 | /* Looks like a register name. */ | |
6964 | break; | |
6965 | } | |
670a50eb | 6966 | my_getExpression (&offset_expr, s); |
cc5703cd ILT |
6967 | /* We need to relax this instruction. */ |
6968 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
670a50eb ILT |
6969 | s = expr_end; |
6970 | continue; | |
6971 | ||
cc5703cd ILT |
6972 | case '6': /* break code */ |
6973 | my_getExpression (&imm_expr, s); | |
6974 | check_absolute_expr (ip, &imm_expr); | |
6975 | if ((unsigned long) imm_expr.X_add_number > 63) | |
670a50eb | 6976 | { |
cc5703cd ILT |
6977 | as_warn ("Invalid value for `%s' (%lu)", |
6978 | ip->insn_mo->name, | |
6979 | (unsigned long) imm_expr.X_add_number); | |
6980 | imm_expr.X_add_number &= 0x3f; | |
3d3c5039 | 6981 | } |
cc5703cd ILT |
6982 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; |
6983 | imm_expr.X_op = O_absent; | |
670a50eb ILT |
6984 | s = expr_end; |
6985 | continue; | |
3d3c5039 | 6986 | |
670a50eb ILT |
6987 | case 'a': /* 26 bit address */ |
6988 | my_getExpression (&offset_expr, s); | |
6989 | s = expr_end; | |
cc5703cd ILT |
6990 | offset_reloc = BFD_RELOC_MIPS16_JMP; |
6991 | ip->insn_opcode <<= 16; | |
670a50eb | 6992 | continue; |
3d3c5039 | 6993 | |
cc5703cd ILT |
6994 | case 'l': /* register list for entry macro */ |
6995 | case 'L': /* register list for exit macro */ | |
6996 | { | |
6997 | int mask; | |
6998 | ||
6999 | if (c == 'l') | |
7000 | mask = 0; | |
7001 | else | |
7002 | mask = 7 << 3; | |
7003 | while (*s != '\0') | |
7004 | { | |
7005 | int reg1, reg2; | |
7006 | ||
7007 | while (*s == ' ' || *s == ',') | |
7008 | ++s; | |
7009 | if (*s != '$') | |
7010 | { | |
7011 | as_bad ("can't parse register list"); | |
7012 | break; | |
7013 | } | |
7014 | ++s; | |
7015 | reg1 = 0; | |
7016 | while (isdigit (*s)) | |
7017 | { | |
7018 | reg1 *= 10; | |
7019 | reg1 += *s - '0'; | |
7020 | ++s; | |
7021 | } | |
7022 | if (*s == ' ') | |
7023 | ++s; | |
7024 | if (*s != '-') | |
7025 | reg2 = reg1; | |
7026 | else | |
7027 | { | |
7028 | ++s; | |
7029 | if (*s != '$') | |
7030 | break; | |
7031 | ++s; | |
7032 | reg2 = 0; | |
7033 | while (isdigit (*s)) | |
7034 | { | |
7035 | reg2 *= 10; | |
7036 | reg2 += *s - '0'; | |
7037 | ++s; | |
7038 | } | |
7039 | } | |
7040 | if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
7041 | mask |= (reg2 - 3) << 3; | |
7042 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
7043 | mask |= (reg2 - 15) << 1; | |
7044 | else if (reg1 == 31 && reg2 == 31) | |
7045 | mask |= 1; | |
7046 | else | |
7047 | as_bad ("invalid register list"); | |
7048 | } | |
7049 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
7050 | } | |
7051 | continue; | |
d8a1c247 | 7052 | |
3d3c5039 | 7053 | default: |
670a50eb | 7054 | internalError (); |
3d3c5039 | 7055 | } |
670a50eb | 7056 | break; |
3d3c5039 | 7057 | } |
cc5703cd | 7058 | |
670a50eb | 7059 | /* Args don't match. */ |
cc5703cd ILT |
7060 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && |
7061 | strcmp (insn->name, insn[1].name) == 0) | |
670a50eb ILT |
7062 | { |
7063 | ++insn; | |
cc5703cd | 7064 | s = argsstart; |
670a50eb | 7065 | continue; |
3d3c5039 | 7066 | } |
cc5703cd | 7067 | |
9753202d | 7068 | insn_error = "illegal operands"; |
cc5703cd | 7069 | |
670a50eb | 7070 | return; |
3d3c5039 ILT |
7071 | } |
7072 | } | |
7073 | ||
cc5703cd ILT |
7074 | /* This structure holds information we know about a mips16 immediate |
7075 | argument type. */ | |
7076 | ||
7077 | struct mips16_immed_operand | |
7078 | { | |
7079 | /* The type code used in the argument string in the opcode table. */ | |
7080 | int type; | |
7081 | /* The number of bits in the short form of the opcode. */ | |
7082 | int nbits; | |
7083 | /* The number of bits in the extended form of the opcode. */ | |
7084 | int extbits; | |
7085 | /* The amount by which the short form is shifted when it is used; | |
7086 | for example, the sw instruction has a shift count of 2. */ | |
7087 | int shift; | |
7088 | /* The amount by which the short form is shifted when it is stored | |
7089 | into the instruction code. */ | |
7090 | int op_shift; | |
7091 | /* Non-zero if the short form is unsigned. */ | |
7092 | int unsp; | |
7093 | /* Non-zero if the extended form is unsigned. */ | |
7094 | int extu; | |
7095 | /* Non-zero if the value is PC relative. */ | |
7096 | int pcrel; | |
7097 | }; | |
7098 | ||
7099 | /* The mips16 immediate operand types. */ | |
7100 | ||
7101 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
7102 | { | |
7103 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7104 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7105 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7106 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7107 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
7108 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7109 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7110 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7111 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7112 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
7113 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7114 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7115 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7116 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
7117 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7118 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7119 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7120 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7121 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
7122 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
7123 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
7124 | }; | |
7125 | ||
7126 | #define MIPS16_NUM_IMMED \ | |
7127 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
7128 | ||
7129 | /* Handle a mips16 instruction with an immediate value. This or's the | |
7130 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
7131 | whether an extended value is needed; if one is needed, it sets | |
7132 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
7133 | If SMALL is true, an unextended opcode was explicitly requested. | |
7134 | If EXT is true, an extended opcode was explicitly requested. If | |
7135 | WARN is true, warn if EXT does not match reality. */ | |
7136 | ||
7137 | static void | |
7138 | mips16_immed (type, val, warn, small, ext, insn, use_extend, extend) | |
7139 | int type; | |
7140 | offsetT val; | |
7141 | boolean warn; | |
7142 | boolean small; | |
7143 | boolean ext; | |
7144 | unsigned long *insn; | |
7145 | boolean *use_extend; | |
7146 | unsigned short *extend; | |
7147 | { | |
7148 | register const struct mips16_immed_operand *op; | |
7149 | int mintiny, maxtiny; | |
7150 | boolean needext; | |
7151 | ||
7152 | op = mips16_immed_operands; | |
7153 | while (op->type != type) | |
7154 | { | |
7155 | ++op; | |
7156 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
7157 | } | |
7158 | ||
7159 | if (op->unsp) | |
7160 | { | |
7161 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
7162 | { | |
7163 | mintiny = 1; | |
7164 | maxtiny = 1 << op->nbits; | |
7165 | } | |
7166 | else | |
7167 | { | |
7168 | mintiny = 0; | |
7169 | maxtiny = (1 << op->nbits) - 1; | |
7170 | } | |
7171 | } | |
7172 | else | |
7173 | { | |
7174 | mintiny = - (1 << (op->nbits - 1)); | |
7175 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
7176 | } | |
7177 | ||
7178 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
7179 | if (type == 'p' || type == 'q') | |
7180 | { | |
7181 | if ((val & 1) != 0) | |
7182 | as_bad ("branch to odd address"); | |
7183 | val /= 2; | |
7184 | } | |
7185 | ||
7186 | if ((val & ((1 << op->shift) - 1)) != 0 | |
7187 | || val < (mintiny << op->shift) | |
7188 | || val > (maxtiny << op->shift)) | |
7189 | needext = true; | |
7190 | else | |
7191 | needext = false; | |
7192 | ||
7193 | if (warn && ext && ! needext) | |
7194 | as_warn ("extended operand requested but not required"); | |
7195 | if ((small || ! mips16_autoextend) && needext) | |
7196 | as_bad ("invalid unextended operand value"); | |
7197 | ||
7198 | if (small || (! ext && ! needext)) | |
7199 | { | |
7200 | int insnval; | |
7201 | ||
7202 | *use_extend = false; | |
7203 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
7204 | insnval <<= op->op_shift; | |
7205 | *insn |= insnval; | |
7206 | } | |
7207 | else | |
7208 | { | |
7209 | long minext, maxext; | |
7210 | int extval; | |
7211 | ||
7212 | if (op->extu) | |
7213 | { | |
7214 | minext = 0; | |
7215 | maxext = (1 << op->extbits) - 1; | |
7216 | } | |
7217 | else | |
7218 | { | |
7219 | minext = - (1 << (op->extbits - 1)); | |
7220 | maxext = (1 << (op->extbits - 1)) - 1; | |
7221 | } | |
7222 | if (val < minext || val > maxext) | |
7223 | as_bad ("operand value out of range for instruction"); | |
7224 | ||
7225 | *use_extend = true; | |
7226 | if (op->extbits == 16) | |
7227 | { | |
7228 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
7229 | val &= 0x1f; | |
7230 | } | |
7231 | else if (op->extbits == 15) | |
7232 | { | |
7233 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
7234 | val &= 0xf; | |
7235 | } | |
7236 | else | |
7237 | { | |
7238 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
7239 | val = 0; | |
7240 | } | |
7241 | ||
7242 | *extend = (unsigned short) extval; | |
7243 | *insn |= val; | |
7244 | } | |
7245 | } | |
7246 | \f | |
3d3c5039 ILT |
7247 | #define LP '(' |
7248 | #define RP ')' | |
7249 | ||
7250 | static int | |
7251 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
7252 | expressionS *ep; |
7253 | char *str; | |
3d3c5039 | 7254 | { |
670a50eb ILT |
7255 | char *sp; |
7256 | int c = 0; | |
7257 | ||
7258 | if (*str == ' ') | |
7259 | str++; | |
7260 | if (*str == LP | |
7261 | || (*str == '%' && | |
7262 | ((str[1] == 'h' && str[2] == 'i') | |
7263 | || (str[1] == 'H' && str[2] == 'I') | |
7264 | || (str[1] == 'l' && str[2] == 'o')) | |
7265 | && str[3] == LP)) | |
7266 | { | |
7267 | if (*str == LP) | |
7268 | c = 0; | |
7269 | else | |
7270 | { | |
7271 | c = str[1]; | |
7272 | str += 3; | |
7273 | } | |
7274 | ||
7275 | /* | |
7276 | * A small expression may be followed by a base register. | |
7277 | * Scan to the end of this operand, and then back over a possible | |
7278 | * base register. Then scan the small expression up to that | |
7279 | * point. (Based on code in sparc.c...) | |
7280 | */ | |
7281 | for (sp = str; *sp && *sp != ','; sp++) | |
7282 | ; | |
7283 | if (sp - 4 >= str && sp[-1] == RP) | |
7284 | { | |
7285 | if (isdigit (sp[-2])) | |
7286 | { | |
7287 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
7288 | ; | |
7289 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
7290 | { | |
7291 | sp--; | |
7292 | goto do_it; | |
3d3c5039 | 7293 | } |
670a50eb ILT |
7294 | } |
7295 | else if (sp - 5 >= str | |
7296 | && sp[-5] == LP | |
7297 | && sp[-4] == '$' | |
7298 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
7299 | || (sp[-3] == 's' && sp[-2] == 'p') | |
7300 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
7301 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
7302 | { | |
7303 | sp -= 5; | |
3d3c5039 | 7304 | do_it: |
670a50eb ILT |
7305 | if (sp == str) |
7306 | { | |
7307 | /* no expression means zero offset */ | |
7308 | if (c) | |
7309 | { | |
7310 | /* %xx(reg) is an error */ | |
5ac34ac3 | 7311 | ep->X_op = O_absent; |
670a50eb | 7312 | expr_end = str - 3; |
3d3c5039 | 7313 | } |
670a50eb ILT |
7314 | else |
7315 | { | |
52aa70b5 | 7316 | ep->X_op = O_constant; |
670a50eb ILT |
7317 | expr_end = sp; |
7318 | } | |
7319 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 7320 | ep->X_op_symbol = NULL; |
670a50eb ILT |
7321 | ep->X_add_number = 0; |
7322 | } | |
7323 | else | |
7324 | { | |
7325 | *sp = '\0'; | |
7326 | my_getExpression (ep, str); | |
7327 | *sp = LP; | |
3d3c5039 | 7328 | } |
670a50eb | 7329 | return c; |
3d3c5039 ILT |
7330 | } |
7331 | } | |
7332 | } | |
670a50eb ILT |
7333 | my_getExpression (ep, str); |
7334 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
7335 | } |
7336 | ||
7337 | static void | |
7338 | my_getExpression (ep, str) | |
670a50eb ILT |
7339 | expressionS *ep; |
7340 | char *str; | |
3d3c5039 | 7341 | { |
670a50eb | 7342 | char *save_in; |
670a50eb ILT |
7343 | |
7344 | save_in = input_line_pointer; | |
7345 | input_line_pointer = str; | |
5ac34ac3 | 7346 | expression (ep); |
670a50eb ILT |
7347 | expr_end = input_line_pointer; |
7348 | input_line_pointer = save_in; | |
3d3c5039 ILT |
7349 | } |
7350 | ||
becfe05e ILT |
7351 | /* Turn a string in input_line_pointer into a floating point constant |
7352 | of type type, and store the appropriate bytes in *litP. The number | |
7353 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
7354 | returned, or NULL on OK. */ | |
7355 | ||
3d3c5039 | 7356 | char * |
670a50eb | 7357 | md_atof (type, litP, sizeP) |
becfe05e | 7358 | int type; |
3d3c5039 ILT |
7359 | char *litP; |
7360 | int *sizeP; | |
7361 | { | |
becfe05e ILT |
7362 | int prec; |
7363 | LITTLENUM_TYPE words[4]; | |
7364 | char *t; | |
7365 | int i; | |
7366 | ||
7367 | switch (type) | |
7368 | { | |
7369 | case 'f': | |
7370 | prec = 2; | |
7371 | break; | |
7372 | ||
7373 | case 'd': | |
7374 | prec = 4; | |
7375 | break; | |
7376 | ||
7377 | default: | |
7378 | *sizeP = 0; | |
7379 | return "bad call to md_atof"; | |
7380 | } | |
7381 | ||
7382 | t = atof_ieee (input_line_pointer, type, words); | |
7383 | if (t) | |
7384 | input_line_pointer = t; | |
7385 | ||
7386 | *sizeP = prec * 2; | |
7387 | ||
7388 | if (byte_order == LITTLE_ENDIAN) | |
7389 | { | |
7390 | for (i = prec - 1; i >= 0; i--) | |
7391 | { | |
7392 | md_number_to_chars (litP, (valueT) words[i], 2); | |
7393 | litP += 2; | |
7394 | } | |
7395 | } | |
7396 | else | |
7397 | { | |
7398 | for (i = 0; i < prec; i++) | |
7399 | { | |
7400 | md_number_to_chars (litP, (valueT) words[i], 2); | |
7401 | litP += 2; | |
7402 | } | |
7403 | } | |
7404 | ||
670a50eb | 7405 | return NULL; |
3d3c5039 ILT |
7406 | } |
7407 | ||
7408 | void | |
7409 | md_number_to_chars (buf, val, n) | |
7410 | char *buf; | |
918692a5 | 7411 | valueT val; |
3d3c5039 ILT |
7412 | int n; |
7413 | { | |
670a50eb ILT |
7414 | switch (byte_order) |
7415 | { | |
3d3c5039 | 7416 | case LITTLE_ENDIAN: |
13fe1379 ILT |
7417 | number_to_chars_littleendian (buf, val, n); |
7418 | break; | |
3d3c5039 ILT |
7419 | |
7420 | case BIG_ENDIAN: | |
13fe1379 ILT |
7421 | number_to_chars_bigendian (buf, val, n); |
7422 | break; | |
3d3c5039 ILT |
7423 | |
7424 | default: | |
670a50eb | 7425 | internalError (); |
3d3c5039 ILT |
7426 | } |
7427 | } | |
f3d817d8 | 7428 | \f |
e8d4d475 | 7429 | CONST char *md_shortopts = "O::g::G:"; |
1dc1e798 | 7430 | |
f3d817d8 DM |
7431 | struct option md_longopts[] = { |
7432 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
7433 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
7434 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
7435 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
7436 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
7437 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
7438 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
d8a1c247 KR |
7439 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
7440 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
7441 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
f3d817d8 | 7442 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
d8a1c247 | 7443 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) |
f3d817d8 | 7444 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
d8a1c247 | 7445 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
f3d817d8 DM |
7446 | {"trap", no_argument, NULL, OPTION_TRAP}, |
7447 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
d8a1c247 | 7448 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
f3d817d8 DM |
7449 | {"break", no_argument, NULL, OPTION_BREAK}, |
7450 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
d8a1c247 | 7451 | #define OPTION_EB (OPTION_MD_BASE + 11) |
e8d4d475 | 7452 | {"EB", no_argument, NULL, OPTION_EB}, |
d8a1c247 | 7453 | #define OPTION_EL (OPTION_MD_BASE + 12) |
e8d4d475 | 7454 | {"EL", no_argument, NULL, OPTION_EL}, |
d8a1c247 | 7455 | #define OPTION_M4650 (OPTION_MD_BASE + 13) |
b2b8c24e | 7456 | {"m4650", no_argument, NULL, OPTION_M4650}, |
d8a1c247 | 7457 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) |
b2b8c24e | 7458 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
e532b44c ILT |
7459 | #define OPTION_M4010 (OPTION_MD_BASE + 15) |
7460 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
7461 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
7462 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
c625fc23 JSC |
7463 | #define OPTION_M4100 (OPTION_MD_BASE + 17) |
7464 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
7465 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
7466 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
cc5703cd | 7467 | #define OPTION_MIPS16 (OPTION_MD_BASE + 22) |
943321c0 | 7468 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
cc5703cd | 7469 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23) |
943321c0 | 7470 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f3d817d8 | 7471 | |
d8a1c247 | 7472 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) |
1dc1e798 | 7473 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) |
fb251650 | 7474 | #define OPTION_XGOT (OPTION_MD_BASE + 19) |
7f9880e5 ILT |
7475 | #define OPTION_32 (OPTION_MD_BASE + 20) |
7476 | #define OPTION_64 (OPTION_MD_BASE + 21) | |
1dc1e798 | 7477 | #ifdef OBJ_ELF |
f3d817d8 | 7478 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
fb251650 | 7479 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
f3d817d8 | 7480 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
f3d817d8 | 7481 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
7f9880e5 ILT |
7482 | {"32", no_argument, NULL, OPTION_32}, |
7483 | {"64", no_argument, NULL, OPTION_64}, | |
f3d817d8 DM |
7484 | #endif |
7485 | ||
7486 | {NULL, no_argument, NULL, 0} | |
7487 | }; | |
7488 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
7489 | |
7490 | int | |
f3d817d8 DM |
7491 | md_parse_option (c, arg) |
7492 | int c; | |
7493 | char *arg; | |
3d3c5039 | 7494 | { |
f3d817d8 | 7495 | switch (c) |
670a50eb | 7496 | { |
f3d817d8 DM |
7497 | case OPTION_TRAP: |
7498 | mips_trap = 1; | |
7499 | break; | |
670a50eb | 7500 | |
f3d817d8 DM |
7501 | case OPTION_BREAK: |
7502 | mips_trap = 0; | |
7503 | break; | |
7504 | ||
e8d4d475 | 7505 | case OPTION_EB: |
1dc1e798 | 7506 | target_big_endian = 1; |
e8d4d475 | 7507 | break; |
04cb3372 | 7508 | |
e8d4d475 | 7509 | case OPTION_EL: |
1dc1e798 | 7510 | target_big_endian = 0; |
f3d817d8 | 7511 | break; |
670a50eb | 7512 | |
f3d817d8 DM |
7513 | case 'O': |
7514 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
7515 | mips_optimize = 1; |
7516 | else | |
7517 | mips_optimize = 2; | |
f3d817d8 | 7518 | break; |
0aa07269 | 7519 | |
f3d817d8 | 7520 | case 'g': |
22ba90ce ILT |
7521 | if (arg == NULL) |
7522 | mips_debug = 2; | |
7523 | else | |
7524 | mips_debug = atoi (arg); | |
7525 | /* When the MIPS assembler sees -g or -g2, it does not do | |
7526 | optimizations which limit full symbolic debugging. We take | |
7527 | that to be equivalent to -O0. */ | |
7528 | if (mips_debug == 2) | |
0aa07269 | 7529 | mips_optimize = 0; |
f3d817d8 | 7530 | break; |
4e95866e | 7531 | |
f3d817d8 DM |
7532 | case OPTION_MIPS1: |
7533 | mips_isa = 1; | |
4bb0cc41 ILT |
7534 | if (mips_cpu == -1) |
7535 | mips_cpu = 3000; | |
f3d817d8 | 7536 | break; |
8358c818 | 7537 | |
f3d817d8 DM |
7538 | case OPTION_MIPS2: |
7539 | mips_isa = 2; | |
4bb0cc41 ILT |
7540 | if (mips_cpu == -1) |
7541 | mips_cpu = 6000; | |
f3d817d8 | 7542 | break; |
8358c818 | 7543 | |
f3d817d8 DM |
7544 | case OPTION_MIPS3: |
7545 | mips_isa = 3; | |
4bb0cc41 ILT |
7546 | if (mips_cpu == -1) |
7547 | mips_cpu = 4000; | |
f3d817d8 | 7548 | break; |
8358c818 | 7549 | |
d8a1c247 KR |
7550 | case OPTION_MIPS4: |
7551 | mips_isa = 4; | |
7552 | if (mips_cpu == -1) | |
7553 | mips_cpu = 8000; | |
7554 | break; | |
7555 | ||
f3d817d8 DM |
7556 | case OPTION_MCPU: |
7557 | { | |
7558 | char *p; | |
7559 | ||
7560 | /* Identify the processor type */ | |
7561 | p = arg; | |
7562 | if (strcmp (p, "default") == 0 | |
7563 | || strcmp (p, "DEFAULT") == 0) | |
4bb0cc41 | 7564 | mips_cpu = -1; |
f3d817d8 DM |
7565 | else |
7566 | { | |
c625fc23 JSC |
7567 | int sv = 0; |
7568 | ||
7569 | /* We need to cope with the various "vr" prefixes for the 4300 | |
7570 | processor. */ | |
7571 | if (*p == 'v' || *p == 'V') | |
7572 | { | |
7573 | sv = 1; | |
7574 | p++; | |
7575 | } | |
7576 | ||
f3d817d8 DM |
7577 | if (*p == 'r' || *p == 'R') |
7578 | p++; | |
8358c818 | 7579 | |
4bb0cc41 | 7580 | mips_cpu = -1; |
f3d817d8 DM |
7581 | switch (*p) |
7582 | { | |
d8a1c247 KR |
7583 | case '1': |
7584 | if (strcmp (p, "10000") == 0 | |
7585 | || strcmp (p, "10k") == 0 | |
7586 | || strcmp (p, "10K") == 0) | |
7587 | mips_cpu = 10000; | |
7588 | break; | |
7589 | ||
f3d817d8 DM |
7590 | case '2': |
7591 | if (strcmp (p, "2000") == 0 | |
7592 | || strcmp (p, "2k") == 0 | |
7593 | || strcmp (p, "2K") == 0) | |
4bb0cc41 | 7594 | mips_cpu = 2000; |
f3d817d8 | 7595 | break; |
8358c818 | 7596 | |
f3d817d8 DM |
7597 | case '3': |
7598 | if (strcmp (p, "3000") == 0 | |
7599 | || strcmp (p, "3k") == 0 | |
7600 | || strcmp (p, "3K") == 0) | |
4bb0cc41 | 7601 | mips_cpu = 3000; |
f3d817d8 | 7602 | break; |
8358c818 | 7603 | |
f3d817d8 DM |
7604 | case '4': |
7605 | if (strcmp (p, "4000") == 0 | |
7606 | || strcmp (p, "4k") == 0 | |
8c63448a | 7607 | || strcmp (p, "4K") == 0) |
4bb0cc41 | 7608 | mips_cpu = 4000; |
c625fc23 JSC |
7609 | else if (strcmp (p, "4100") == 0) |
7610 | { | |
7611 | mips_cpu = 4100; | |
7612 | if (mips_4100 < 0) | |
7613 | mips_4100 = 1; | |
7614 | } | |
7615 | else if (strcmp (p, "4300") == 0) | |
7616 | mips_cpu = 4300; | |
8c63448a | 7617 | else if (strcmp (p, "4400") == 0) |
4bb0cc41 | 7618 | mips_cpu = 4400; |
8c63448a | 7619 | else if (strcmp (p, "4600") == 0) |
4bb0cc41 | 7620 | mips_cpu = 4600; |
b2b8c24e ILT |
7621 | else if (strcmp (p, "4650") == 0) |
7622 | { | |
7623 | mips_cpu = 4650; | |
7624 | if (mips_4650 < 0) | |
7625 | mips_4650 = 1; | |
7626 | } | |
e532b44c ILT |
7627 | else if (strcmp (p, "4010") == 0) |
7628 | { | |
7629 | mips_cpu = 4010; | |
7630 | if (mips_4010 < 0) | |
7631 | mips_4010 = 1; | |
7632 | } | |
f3d817d8 | 7633 | break; |
8358c818 | 7634 | |
517078c1 ILT |
7635 | case '5': |
7636 | if (strcmp (p, "5000") == 0 | |
7637 | || strcmp (p, "5k") == 0 | |
7638 | || strcmp (p, "5K") == 0) | |
7639 | mips_cpu = 5000; | |
7640 | break; | |
7641 | ||
f3d817d8 DM |
7642 | case '6': |
7643 | if (strcmp (p, "6000") == 0 | |
7644 | || strcmp (p, "6k") == 0 | |
7645 | || strcmp (p, "6K") == 0) | |
4bb0cc41 | 7646 | mips_cpu = 6000; |
f3d817d8 | 7647 | break; |
55933a58 | 7648 | |
d8a1c247 KR |
7649 | case '8': |
7650 | if (strcmp (p, "8000") == 0 | |
7651 | || strcmp (p, "8k") == 0 | |
7652 | || strcmp (p, "8K") == 0) | |
7653 | mips_cpu = 8000; | |
7654 | break; | |
7655 | ||
55933a58 ILT |
7656 | case 'o': |
7657 | if (strcmp (p, "orion") == 0) | |
4bb0cc41 | 7658 | mips_cpu = 4600; |
55933a58 | 7659 | break; |
f3d817d8 | 7660 | } |
8358c818 | 7661 | |
517078c1 | 7662 | if (sv && mips_cpu != 4300 && mips_cpu != 4100 && mips_cpu != 5000) |
c625fc23 JSC |
7663 | { |
7664 | as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg); | |
7665 | return 0; | |
7666 | } | |
7667 | ||
4bb0cc41 | 7668 | if (mips_cpu == -1) |
f3d817d8 DM |
7669 | { |
7670 | as_bad ("invalid architecture -mcpu=%s", arg); | |
7671 | return 0; | |
7672 | } | |
7673 | } | |
7674 | } | |
7675 | break; | |
8358c818 | 7676 | |
b2b8c24e ILT |
7677 | case OPTION_M4650: |
7678 | mips_4650 = 1; | |
7679 | break; | |
7680 | ||
7681 | case OPTION_NO_M4650: | |
7682 | mips_4650 = 0; | |
7683 | break; | |
7684 | ||
e532b44c ILT |
7685 | case OPTION_M4010: |
7686 | mips_4010 = 1; | |
7687 | break; | |
7688 | ||
7689 | case OPTION_NO_M4010: | |
7690 | mips_4010 = 0; | |
7691 | break; | |
7692 | ||
c625fc23 JSC |
7693 | case OPTION_M4100: |
7694 | mips_4100 = 1; | |
7695 | break; | |
7696 | ||
7697 | case OPTION_NO_M4100: | |
7698 | mips_4100 = 0; | |
7699 | break; | |
7700 | ||
cc5703cd ILT |
7701 | case OPTION_MIPS16: |
7702 | mips16 = 1; | |
7703 | mips_no_prev_insn (); | |
7704 | break; | |
7705 | ||
7706 | case OPTION_NO_MIPS16: | |
7707 | mips16 = 0; | |
7708 | mips_no_prev_insn (); | |
7709 | break; | |
7710 | ||
f3d817d8 | 7711 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 7712 | mips_pic = EMBEDDED_PIC; |
1dc1e798 | 7713 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
f3d817d8 DM |
7714 | { |
7715 | as_bad ("-G may not be used with embedded PIC code"); | |
7716 | return 0; | |
7717 | } | |
5b63f465 | 7718 | g_switch_value = 0x7fffffff; |
f3d817d8 | 7719 | break; |
d9aba805 | 7720 | |
fb251650 ILT |
7721 | /* When generating ELF code, we permit -KPIC and -call_shared to |
7722 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
7723 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 7724 | case OPTION_CALL_SHARED: |
1dc1e798 KR |
7725 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
7726 | { | |
7727 | as_bad ("-call_shared is supported only for ELF format"); | |
7728 | return 0; | |
7729 | } | |
d9aba805 ILT |
7730 | mips_pic = SVR4_PIC; |
7731 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 DM |
7732 | { |
7733 | as_bad ("-G may not be used with SVR4 PIC code"); | |
7734 | return 0; | |
7735 | } | |
d9aba805 | 7736 | g_switch_value = 0; |
f3d817d8 DM |
7737 | break; |
7738 | ||
7739 | case OPTION_NON_SHARED: | |
1dc1e798 KR |
7740 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
7741 | { | |
7742 | as_bad ("-non_shared is supported only for ELF format"); | |
7743 | return 0; | |
7744 | } | |
d9aba805 | 7745 | mips_pic = NO_PIC; |
f3d817d8 | 7746 | break; |
8358c818 | 7747 | |
fb251650 ILT |
7748 | /* The -xgot option tells the assembler to use 32 offsets when |
7749 | accessing the got in SVR4_PIC mode. It is for Irix | |
7750 | compatibility. */ | |
7751 | case OPTION_XGOT: | |
7752 | mips_big_got = 1; | |
7753 | break; | |
7754 | ||
f3d817d8 | 7755 | case 'G': |
1dc1e798 KR |
7756 | if (! USE_GLOBAL_POINTER_OPT) |
7757 | { | |
7758 | as_bad ("-G is not supported for this configuration"); | |
7759 | return 0; | |
7760 | } | |
7761 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
670a50eb | 7762 | { |
f3d817d8 DM |
7763 | as_bad ("-G may not be used with SVR4 or embedded PIC code"); |
7764 | return 0; | |
670a50eb ILT |
7765 | } |
7766 | else | |
f3d817d8 | 7767 | g_switch_value = atoi (arg); |
42562568 | 7768 | g_switch_seen = 1; |
f3d817d8 | 7769 | break; |
4e95866e | 7770 | |
7f9880e5 ILT |
7771 | /* The -32 and -64 options tell the assembler to output the 32 |
7772 | bit or the 64 bit MIPS ELF format. */ | |
7773 | case OPTION_32: | |
7774 | mips_64 = 0; | |
7775 | break; | |
7776 | ||
7777 | case OPTION_64: | |
9c44af60 ILT |
7778 | { |
7779 | const char **list, **l; | |
7780 | ||
7781 | list = bfd_target_list (); | |
7782 | for (l = list; *l != NULL; l++) | |
7783 | if (strcmp (*l, "elf64-bigmips") == 0 | |
7784 | || strcmp (*l, "elf64-littlemips") == 0) | |
7785 | break; | |
7786 | if (*l == NULL) | |
7787 | as_fatal ("No compiled in support for 64 bit object file format"); | |
7788 | free (list); | |
7789 | mips_64 = 1; | |
7790 | } | |
7f9880e5 ILT |
7791 | break; |
7792 | ||
f3d817d8 DM |
7793 | default: |
7794 | return 0; | |
8ea7f4e8 ILT |
7795 | } |
7796 | ||
f3d817d8 | 7797 | return 1; |
8ea7f4e8 ILT |
7798 | } |
7799 | ||
f3d817d8 DM |
7800 | void |
7801 | md_show_usage (stream) | |
7802 | FILE *stream; | |
7803 | { | |
7804 | fprintf(stream, "\ | |
7805 | MIPS options:\n\ | |
7806 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
7807 | -EB generate big endian output\n\ |
7808 | -EL generate little endian output\n\ | |
7809 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
7810 | -G NUM allow referencing objects up to NUM bytes\n\ | |
6f0b87c3 SS |
7811 | implicitly with the gp register [default 8]\n"); |
7812 | fprintf(stream, "\ | |
f3d817d8 DM |
7813 | -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\ |
7814 | -mips2, -mcpu=r6000 generate code for r6000\n\ | |
7815 | -mips3, -mcpu=r4000 generate code for r4000\n\ | |
d8a1c247 | 7816 | -mips4, -mcpu=r8000 generate code for r8000\n\ |
c625fc23 | 7817 | -mcpu=vr4300 generate code for vr4300\n\ |
fb251650 | 7818 | -mcpu=vr4100 generate code for vr4100\n\ |
e532b44c ILT |
7819 | -m4650 permit R4650 instructions\n\ |
7820 | -no-m4650 do not permit R4650 instructions\n\ | |
7821 | -m4010 permit R4010 instructions\n\ | |
7822 | -no-m4010 do not permit R4010 instructions\n\ | |
c625fc23 JSC |
7823 | -m4100 permit VR4100 instructions\n\ |
7824 | -no-m4100 do not permit VR4100 instructions\n"); | |
7825 | fprintf(stream, "\ | |
cc5703cd ILT |
7826 | -mips16 generate mips16 instructions\n\ |
7827 | -no-mips16 do not generate mips16 instructions\n"); | |
7828 | fprintf(stream, "\ | |
f3d817d8 DM |
7829 | -O0 remove unneeded NOPs, do not swap branches\n\ |
7830 | -O remove unneeded NOPs and swap branches\n\ | |
7831 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
7832 | --break, --no-trap break exception on div by 0 and mult overflow\n"); | |
7833 | #ifdef OBJ_ELF | |
7834 | fprintf(stream, "\ | |
7835 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
fb251650 | 7836 | -non_shared do not generate position independent code\n\ |
7f9880e5 ILT |
7837 | -xgot assume a 32 bit GOT\n\ |
7838 | -32 create 32 bit object file (default)\n\ | |
7839 | -64 create 64 bit object file\n"); | |
f3d817d8 DM |
7840 | #endif |
7841 | } | |
22ba90ce ILT |
7842 | |
7843 | void | |
7844 | mips_init_after_args () | |
7845 | { | |
7846 | if (target_big_endian) | |
7847 | byte_order = BIG_ENDIAN; | |
7848 | else | |
7849 | byte_order = LITTLE_ENDIAN; | |
7850 | } | |
f3d817d8 | 7851 | \f |
3d3c5039 ILT |
7852 | long |
7853 | md_pcrel_from (fixP) | |
7854 | fixS *fixP; | |
7855 | { | |
1dc1e798 KR |
7856 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
7857 | && fixP->fx_addsy != (symbolS *) NULL | |
5b63f465 ILT |
7858 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
7859 | { | |
7860 | /* This makes a branch to an undefined symbol be a branch to the | |
7861 | current location. */ | |
7862 | return 4; | |
7863 | } | |
5b63f465 | 7864 | |
670a50eb ILT |
7865 | /* return the address of the delay slot */ |
7866 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
7867 | } |
7868 | ||
abdad6bc ILT |
7869 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
7870 | reloc for a cons. We could use the definition there, except that | |
7871 | we want to handle 64 bit relocs specially. */ | |
7872 | ||
7873 | void | |
7874 | cons_fix_new_mips (frag, where, nbytes, exp) | |
7875 | fragS *frag; | |
7876 | int where; | |
7877 | unsigned int nbytes; | |
7878 | expressionS *exp; | |
7879 | { | |
bf39474f | 7880 | #ifndef OBJ_ELF |
abdad6bc | 7881 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a |
7f9880e5 ILT |
7882 | 4 byte reloc. */ |
7883 | if (nbytes == 8 && ! mips_64) | |
abdad6bc ILT |
7884 | { |
7885 | if (byte_order == BIG_ENDIAN) | |
7886 | where += 4; | |
7887 | nbytes = 4; | |
7888 | } | |
bf39474f | 7889 | #endif |
abdad6bc | 7890 | |
7f9880e5 | 7891 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) |
abdad6bc ILT |
7892 | as_bad ("Unsupported reloc size %d", nbytes); |
7893 | ||
7894 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
7f9880e5 ILT |
7895 | (nbytes == 2 |
7896 | ? BFD_RELOC_16 | |
7897 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
abdad6bc ILT |
7898 | } |
7899 | ||
867a58b3 ILT |
7900 | /* Sort any unmatched HI16_S relocs so that they immediately precede |
7901 | the corresponding LO reloc. This is called before md_apply_fix and | |
7902 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
7903 | explicit use of the %hi modifier. */ | |
7904 | ||
7905 | void | |
7906 | mips_frob_file () | |
7907 | { | |
7908 | struct mips_hi_fixup *l; | |
7909 | ||
7910 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
7911 | { | |
7912 | segment_info_type *seginfo; | |
9b61d62b | 7913 | int pass; |
867a58b3 ILT |
7914 | |
7915 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
7916 | ||
7917 | /* Check quickly whether the next fixup happens to be a matching | |
7918 | %lo. */ | |
7919 | if (l->fixp->fx_next != NULL | |
7920 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
7921 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
7922 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
7923 | continue; | |
7924 | ||
7925 | /* Look through the fixups for this segment for a matching %lo. | |
9b61d62b ILT |
7926 | When we find one, move the %hi just in front of it. We do |
7927 | this in two passes. In the first pass, we try to find a | |
7928 | unique %lo. In the second pass, we permit multiple %hi | |
7929 | relocs for a single %lo (this is a GNU extension). */ | |
867a58b3 | 7930 | seginfo = seg_info (l->seg); |
9b61d62b ILT |
7931 | for (pass = 0; pass < 2; pass++) |
7932 | { | |
7933 | fixS *f, *prev; | |
7934 | ||
7935 | prev = NULL; | |
7936 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
867a58b3 | 7937 | { |
9b61d62b ILT |
7938 | /* Check whether this is a %lo fixup which matches l->fixp. */ |
7939 | if (f->fx_r_type == BFD_RELOC_LO16 | |
7940 | && f->fx_addsy == l->fixp->fx_addsy | |
7941 | && f->fx_offset == l->fixp->fx_offset | |
7942 | && (pass == 1 | |
7943 | || prev == NULL | |
7944 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
7945 | || prev->fx_addsy != f->fx_addsy | |
7946 | || prev->fx_offset != f->fx_offset)) | |
7947 | { | |
7948 | fixS **pf; | |
867a58b3 | 7949 | |
9b61d62b ILT |
7950 | /* Move l->fixp before f. */ |
7951 | for (pf = &seginfo->fix_root; | |
7952 | *pf != l->fixp; | |
7953 | pf = &(*pf)->fx_next) | |
7954 | assert (*pf != NULL); | |
867a58b3 | 7955 | |
9b61d62b | 7956 | *pf = l->fixp->fx_next; |
867a58b3 | 7957 | |
9b61d62b ILT |
7958 | l->fixp->fx_next = f; |
7959 | if (prev == NULL) | |
7960 | seginfo->fix_root = l->fixp; | |
7961 | else | |
7962 | prev->fx_next = l->fixp; | |
867a58b3 | 7963 | |
9b61d62b ILT |
7964 | break; |
7965 | } | |
7966 | ||
7967 | prev = f; | |
867a58b3 ILT |
7968 | } |
7969 | ||
9b61d62b ILT |
7970 | if (f != NULL) |
7971 | break; | |
867a58b3 | 7972 | |
9b61d62b ILT |
7973 | if (pass == 1) |
7974 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
7975 | "Unmatched %%hi reloc"); | |
7976 | } | |
867a58b3 ILT |
7977 | } |
7978 | } | |
7979 | ||
1c803e52 ILT |
7980 | /* When generating embedded PIC code we need to use a special |
7981 | relocation to represent the difference of two symbols in the .text | |
7982 | section (switch tables use a difference of this sort). See | |
7983 | include/coff/mips.h for details. This macro checks whether this | |
7984 | fixup requires the special reloc. */ | |
7985 | #define SWITCH_TABLE(fixp) \ | |
7986 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
7987 | && (fixp)->fx_addsy != NULL \ | |
7988 | && (fixp)->fx_subsy != NULL \ | |
7989 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
7990 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
7991 | ||
5b63f465 | 7992 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
7993 | relocations, in case the linker has to relax a call. We also need |
7994 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
7995 | |
7996 | /*ARGSUSED*/ | |
7997 | int | |
7998 | mips_force_relocation (fixp) | |
7999 | fixS *fixp; | |
8000 | { | |
1c803e52 | 8001 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
8002 | && (fixp->fx_pcrel |
8003 | || SWITCH_TABLE (fixp) | |
8004 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
8005 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
8006 | } |
8007 | ||
8008 | /* Apply a fixup to the object file. */ | |
8009 | ||
3d3c5039 ILT |
8010 | int |
8011 | md_apply_fix (fixP, valueP) | |
8012 | fixS *fixP; | |
918692a5 | 8013 | valueT *valueP; |
3d3c5039 | 8014 | { |
670a50eb ILT |
8015 | unsigned char *buf; |
8016 | long insn, value; | |
3d3c5039 | 8017 | |
bf39474f ILT |
8018 | assert (fixP->fx_size == 4 |
8019 | || fixP->fx_r_type == BFD_RELOC_16 | |
8020 | || fixP->fx_r_type == BFD_RELOC_64); | |
3d3c5039 | 8021 | |
670a50eb ILT |
8022 | value = *valueP; |
8023 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ | |
3d3c5039 | 8024 | |
5b63f465 ILT |
8025 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
8026 | fixP->fx_done = 1; | |
8027 | ||
670a50eb ILT |
8028 | switch (fixP->fx_r_type) |
8029 | { | |
3d3c5039 ILT |
8030 | case BFD_RELOC_MIPS_JMP: |
8031 | case BFD_RELOC_HI16: | |
8032 | case BFD_RELOC_HI16_S: | |
670a50eb | 8033 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
8034 | case BFD_RELOC_MIPS_LITERAL: |
8035 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
8036 | case BFD_RELOC_MIPS_GOT16: |
8037 | case BFD_RELOC_MIPS_GPREL32: | |
fb251650 ILT |
8038 | case BFD_RELOC_MIPS_GOT_HI16: |
8039 | case BFD_RELOC_MIPS_GOT_LO16: | |
8040 | case BFD_RELOC_MIPS_CALL_HI16: | |
8041 | case BFD_RELOC_MIPS_CALL_LO16: | |
ecd4ca1c | 8042 | if (fixP->fx_pcrel) |
7b777690 ILT |
8043 | as_bad_where (fixP->fx_file, fixP->fx_line, |
8044 | "Invalid PC relative reloc"); | |
670a50eb | 8045 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 8046 | break; |
3d3c5039 | 8047 | |
cc5703cd ILT |
8048 | case BFD_RELOC_MIPS16_JMP: |
8049 | /* We currently always generate a reloc against a symbol, which | |
8050 | means that we don't want an addend even if the symbol is | |
8051 | defined. */ | |
8052 | fixP->fx_addnumber = 0; | |
8053 | break; | |
8054 | ||
ecd4ca1c ILT |
8055 | case BFD_RELOC_PCREL_HI16_S: |
8056 | /* The addend for this is tricky if it is internal, so we just | |
8057 | do everything here rather than in bfd_perform_relocation. */ | |
8058 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
8059 | { | |
8060 | /* For an external symbol adjust by the address to make it | |
8061 | pcrel_offset. We use the address of the RELLO reloc | |
8062 | which follows this one. */ | |
8063 | value += (fixP->fx_next->fx_frag->fr_address | |
8064 | + fixP->fx_next->fx_where); | |
8065 | } | |
8066 | if (value & 0x8000) | |
8067 | value += 0x10000; | |
8068 | value >>= 16; | |
0221ddf7 | 8069 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
ecd4ca1c ILT |
8070 | if (byte_order == BIG_ENDIAN) |
8071 | buf += 2; | |
8072 | md_number_to_chars (buf, value, 2); | |
8073 | break; | |
8074 | ||
8075 | case BFD_RELOC_PCREL_LO16: | |
8076 | /* The addend for this is tricky if it is internal, so we just | |
8077 | do everything here rather than in bfd_perform_relocation. */ | |
8078 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
8079 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 8080 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
ecd4ca1c ILT |
8081 | if (byte_order == BIG_ENDIAN) |
8082 | buf += 2; | |
8083 | md_number_to_chars (buf, value, 2); | |
8084 | break; | |
8085 | ||
bf39474f ILT |
8086 | case BFD_RELOC_64: |
8087 | /* This is handled like BFD_RELOC_32, but we output a sign | |
8088 | extended value if we are only 32 bits. */ | |
8089 | if (fixP->fx_done | |
8090 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
8091 | { | |
8092 | if (8 <= sizeof (valueT)) | |
8093 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
8094 | value, 8); | |
8095 | else | |
8096 | { | |
8097 | long w1, w2; | |
8098 | long hiv; | |
8099 | ||
8100 | w1 = w2 = fixP->fx_where; | |
8101 | if (byte_order == BIG_ENDIAN) | |
8102 | w1 += 4; | |
8103 | else | |
8104 | w2 += 4; | |
8105 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
8106 | if ((value & 0x80000000) != 0) | |
8107 | hiv = 0xffffffff; | |
8108 | else | |
8109 | hiv = 0; | |
8110 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
8111 | } | |
8112 | } | |
8113 | break; | |
8114 | ||
f3645945 ILT |
8115 | case BFD_RELOC_32: |
8116 | /* If we are deleting this reloc entry, we must fill in the | |
8117 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
8118 | resolved when it appears but is later defined. We also need |
8119 | to fill in the value if this is an embedded PIC switch table | |
8120 | entry. */ | |
8121 | if (fixP->fx_done | |
8122 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
8123 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
8124 | value, 4); | |
8125 | break; | |
8126 | ||
49ad0c4c ILT |
8127 | case BFD_RELOC_16: |
8128 | /* If we are deleting this reloc entry, we must fill in the | |
8129 | value now. */ | |
8130 | assert (fixP->fx_size == 2); | |
8131 | if (fixP->fx_done) | |
8132 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
8133 | value, 2); | |
8134 | break; | |
8135 | ||
f3645945 ILT |
8136 | case BFD_RELOC_LO16: |
8137 | /* When handling an embedded PIC switch statement, we can wind | |
8138 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
8139 | if (fixP->fx_done) | |
8140 | { | |
8141 | if (value < -0x8000 || value > 0x7fff) | |
8142 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8143 | "relocation overflow"); | |
0221ddf7 | 8144 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
f3645945 ILT |
8145 | if (byte_order == BIG_ENDIAN) |
8146 | buf += 2; | |
8147 | md_number_to_chars (buf, value, 2); | |
8148 | } | |
8149 | break; | |
8150 | ||
3d3c5039 | 8151 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
8152 | /* |
8153 | * We need to save the bits in the instruction since fixup_segment() | |
8154 | * might be deleting the relocation entry (i.e., a branch within | |
8155 | * the current segment). | |
8156 | */ | |
cc5703cd ILT |
8157 | /* TinyRISC can branch to odd addresses */ |
8158 | if ((value & (mips16 ? 0x1 : 0x3)) != 0) | |
7b777690 ILT |
8159 | as_warn_where (fixP->fx_file, fixP->fx_line, |
8160 | "Branch to odd address (%lx)", value); | |
670a50eb | 8161 | value >>= 2; |
670a50eb ILT |
8162 | |
8163 | /* update old instruction data */ | |
8164 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
8165 | switch (byte_order) | |
8166 | { | |
3d3c5039 | 8167 | case LITTLE_ENDIAN: |
670a50eb ILT |
8168 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; |
8169 | break; | |
3d3c5039 ILT |
8170 | |
8171 | case BIG_ENDIAN: | |
670a50eb ILT |
8172 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; |
8173 | break; | |
3d3c5039 ILT |
8174 | |
8175 | default: | |
670a50eb ILT |
8176 | internalError (); |
8177 | return 0; | |
3d3c5039 | 8178 | } |
9da4c5d1 ILT |
8179 | |
8180 | if (value >= -0x8000 && value < 0x8000) | |
8181 | insn |= value & 0xffff; | |
8182 | else | |
8183 | { | |
8184 | /* The branch offset is too large. If this is an | |
8185 | unconditional branch, and we are not generating PIC code, | |
8186 | we can convert it to an absolute jump instruction. */ | |
8187 | if (mips_pic == NO_PIC | |
8188 | && fixP->fx_done | |
8189 | && fixP->fx_frag->fr_address >= text_section->vma | |
8190 | && (fixP->fx_frag->fr_address | |
8191 | < text_section->vma + text_section->_raw_size) | |
8192 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
8193 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
8194 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
8195 | { | |
8196 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
8197 | insn = 0x0c000000; /* jal */ | |
8198 | else | |
8199 | insn = 0x08000000; /* j */ | |
8200 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
8201 | fixP->fx_done = 0; | |
8202 | fixP->fx_addsy = section_symbol (text_section); | |
8203 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
8204 | } | |
8205 | else | |
8206 | { | |
8207 | /* FIXME. It would be possible in principle to handle | |
8208 | conditional branches which overflow. They could be | |
8209 | transformed into a branch around a jump. This would | |
8210 | require setting up variant frags for each different | |
8211 | branch type. The native MIPS assembler attempts to | |
8212 | handle these cases, but it appears to do it | |
8213 | incorrectly. */ | |
8214 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8215 | "Relocation overflow"); | |
8216 | } | |
8217 | } | |
8218 | ||
604633ae | 8219 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 8220 | break; |
3d3c5039 ILT |
8221 | |
8222 | default: | |
670a50eb | 8223 | internalError (); |
3d3c5039 | 8224 | } |
5b63f465 | 8225 | |
670a50eb | 8226 | return 1; |
3d3c5039 ILT |
8227 | } |
8228 | ||
8229 | #if 0 | |
8230 | void | |
670a50eb ILT |
8231 | printInsn (oc) |
8232 | unsigned long oc; | |
3d3c5039 | 8233 | { |
670a50eb ILT |
8234 | const struct mips_opcode *p; |
8235 | int treg, sreg, dreg, shamt; | |
8236 | short imm; | |
8237 | const char *args; | |
8238 | int i; | |
3d3c5039 | 8239 | |
670a50eb ILT |
8240 | for (i = 0; i < NUMOPCODES; ++i) |
8241 | { | |
8242 | p = &mips_opcodes[i]; | |
8243 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
8244 | { | |
8245 | printf ("%08lx %s\t", oc, p->name); | |
8246 | treg = (oc >> 16) & 0x1f; | |
8247 | sreg = (oc >> 21) & 0x1f; | |
8248 | dreg = (oc >> 11) & 0x1f; | |
8249 | shamt = (oc >> 6) & 0x1f; | |
8250 | imm = oc; | |
8251 | for (args = p->args;; ++args) | |
8252 | { | |
8253 | switch (*args) | |
8254 | { | |
3d3c5039 | 8255 | case '\0': |
670a50eb ILT |
8256 | printf ("\n"); |
8257 | break; | |
3d3c5039 ILT |
8258 | |
8259 | case ',': | |
8260 | case '(': | |
8261 | case ')': | |
670a50eb ILT |
8262 | printf ("%c", *args); |
8263 | continue; | |
3d3c5039 ILT |
8264 | |
8265 | case 'r': | |
670a50eb ILT |
8266 | assert (treg == sreg); |
8267 | printf ("$%d,$%d", treg, sreg); | |
8268 | continue; | |
3d3c5039 ILT |
8269 | |
8270 | case 'd': | |
918692a5 | 8271 | case 'G': |
670a50eb ILT |
8272 | printf ("$%d", dreg); |
8273 | continue; | |
3d3c5039 ILT |
8274 | |
8275 | case 't': | |
918692a5 | 8276 | case 'E': |
670a50eb ILT |
8277 | printf ("$%d", treg); |
8278 | continue; | |
3d3c5039 | 8279 | |
9226253a ILT |
8280 | case 'k': |
8281 | printf ("0x%x", treg); | |
8282 | continue; | |
8283 | ||
3d3c5039 ILT |
8284 | case 'b': |
8285 | case 's': | |
670a50eb ILT |
8286 | printf ("$%d", sreg); |
8287 | continue; | |
3d3c5039 ILT |
8288 | |
8289 | case 'a': | |
670a50eb ILT |
8290 | printf ("0x%08lx", oc & 0x1ffffff); |
8291 | continue; | |
3d3c5039 ILT |
8292 | |
8293 | case 'i': | |
8294 | case 'j': | |
8295 | case 'o': | |
8296 | case 'u': | |
670a50eb ILT |
8297 | printf ("%d", imm); |
8298 | continue; | |
3d3c5039 ILT |
8299 | |
8300 | case '<': | |
56c96faa | 8301 | case '>': |
670a50eb ILT |
8302 | printf ("$%d", shamt); |
8303 | continue; | |
3d3c5039 ILT |
8304 | |
8305 | default: | |
670a50eb | 8306 | internalError (); |
3d3c5039 | 8307 | } |
670a50eb | 8308 | break; |
3d3c5039 | 8309 | } |
670a50eb | 8310 | return; |
3d3c5039 ILT |
8311 | } |
8312 | } | |
670a50eb | 8313 | printf ("%08lx UNDEFINED\n", oc); |
3d3c5039 ILT |
8314 | } |
8315 | #endif | |
8316 | ||
8317 | static symbolS * | |
8318 | get_symbol () | |
8319 | { | |
670a50eb ILT |
8320 | int c; |
8321 | char *name; | |
8322 | symbolS *p; | |
8323 | ||
8324 | name = input_line_pointer; | |
8325 | c = get_symbol_end (); | |
8326 | p = (symbolS *) symbol_find_or_make (name); | |
8327 | *input_line_pointer = c; | |
8328 | return p; | |
3d3c5039 ILT |
8329 | } |
8330 | ||
becfe05e ILT |
8331 | /* Align the current frag to a given power of two. The MIPS assembler |
8332 | also automatically adjusts any preceding label. */ | |
8333 | ||
8334 | static void | |
23dc1ae3 | 8335 | mips_align (to, fill, label) |
becfe05e ILT |
8336 | int to; |
8337 | int fill; | |
23dc1ae3 | 8338 | symbolS *label; |
becfe05e ILT |
8339 | { |
8340 | mips_emit_delays (); | |
8341 | frag_align (to, fill); | |
8342 | record_alignment (now_seg, to); | |
23dc1ae3 | 8343 | if (label != NULL) |
becfe05e | 8344 | { |
23dc1ae3 ILT |
8345 | assert (S_GET_SEGMENT (label) == now_seg); |
8346 | label->sy_frag = frag_now; | |
8347 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
8348 | } |
8349 | } | |
8350 | ||
8351 | /* Align to a given power of two. .align 0 turns off the automatic | |
8352 | alignment used by the data creating pseudo-ops. */ | |
8353 | ||
3d3c5039 ILT |
8354 | static void |
8355 | s_align (x) | |
8356 | int x; | |
8357 | { | |
670a50eb ILT |
8358 | register int temp; |
8359 | register long temp_fill; | |
8360 | long max_alignment = 15; | |
3d3c5039 | 8361 | |
670a50eb | 8362 | /* |
3d3c5039 ILT |
8363 | |
8364 | o Note that the assembler pulls down any immediately preceeding label | |
8365 | to the aligned address. | |
8366 | o It's not documented but auto alignment is reinstated by | |
8367 | a .align pseudo instruction. | |
8368 | o Note also that after auto alignment is turned off the mips assembler | |
8369 | issues an error on attempt to assemble an improperly aligned data item. | |
8370 | We don't. | |
8371 | ||
8372 | */ | |
8373 | ||
670a50eb ILT |
8374 | temp = get_absolute_expression (); |
8375 | if (temp > max_alignment) | |
8376 | as_bad ("Alignment too large: %d. assumed.", temp = max_alignment); | |
8377 | else if (temp < 0) | |
8378 | { | |
8379 | as_warn ("Alignment negative: 0 assumed."); | |
8380 | temp = 0; | |
8381 | } | |
8382 | if (*input_line_pointer == ',') | |
8383 | { | |
8384 | input_line_pointer++; | |
8385 | temp_fill = get_absolute_expression (); | |
8386 | } | |
8387 | else | |
8388 | temp_fill = 0; | |
8389 | if (temp) | |
8390 | { | |
8391 | auto_align = 1; | |
23dc1ae3 | 8392 | mips_align (temp, (int) temp_fill, insn_label); |
3d3c5039 | 8393 | } |
670a50eb ILT |
8394 | else |
8395 | { | |
8396 | auto_align = 0; | |
3d3c5039 ILT |
8397 | } |
8398 | ||
670a50eb | 8399 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
8400 | } |
8401 | ||
739708fa KR |
8402 | void |
8403 | mips_flush_pending_output () | |
becfe05e ILT |
8404 | { |
8405 | mips_emit_delays (); | |
1849d646 | 8406 | insn_label = NULL; |
becfe05e ILT |
8407 | } |
8408 | ||
3d3c5039 ILT |
8409 | static void |
8410 | s_change_sec (sec) | |
8411 | int sec; | |
8412 | { | |
88225433 | 8413 | segT seg; |
becfe05e | 8414 | |
5b63f465 ILT |
8415 | /* When generating embedded PIC code, we only use the .text, .lit8, |
8416 | .sdata and .sbss sections. We change the .data and .rdata | |
8417 | pseudo-ops to use .sdata. */ | |
8418 | if (mips_pic == EMBEDDED_PIC | |
8419 | && (sec == 'd' || sec == 'r')) | |
8420 | sec = 's'; | |
8421 | ||
becfe05e | 8422 | mips_emit_delays (); |
670a50eb ILT |
8423 | switch (sec) |
8424 | { | |
3d3c5039 | 8425 | case 't': |
604633ae | 8426 | s_text (0); |
670a50eb | 8427 | break; |
3d3c5039 | 8428 | case 'd': |
604633ae | 8429 | s_data (0); |
670a50eb | 8430 | break; |
3d3c5039 | 8431 | case 'b': |
670a50eb | 8432 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
8433 | demand_empty_rest_of_line (); |
8434 | break; | |
88225433 ILT |
8435 | |
8436 | case 'r': | |
1dc1e798 KR |
8437 | if (USE_GLOBAL_POINTER_OPT) |
8438 | { | |
8439 | seg = subseg_new (RDATA_SECTION_NAME, | |
8440 | (subsegT) get_absolute_expression ()); | |
8441 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8442 | { | |
8443 | bfd_set_section_flags (stdoutput, seg, | |
8444 | (SEC_ALLOC | |
8445 | | SEC_LOAD | |
8446 | | SEC_READONLY | |
8447 | | SEC_RELOC | |
8448 | | SEC_DATA)); | |
8449 | bfd_set_section_alignment (stdoutput, seg, 4); | |
8450 | } | |
8451 | demand_empty_rest_of_line (); | |
8452 | } | |
8453 | else | |
8454 | { | |
8455 | as_bad ("No read only data section in this object file format"); | |
8456 | demand_empty_rest_of_line (); | |
8457 | return; | |
8458 | } | |
88225433 | 8459 | break; |
88225433 ILT |
8460 | |
8461 | case 's': | |
1dc1e798 KR |
8462 | if (USE_GLOBAL_POINTER_OPT) |
8463 | { | |
8464 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
8465 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8466 | { | |
8467 | bfd_set_section_flags (stdoutput, seg, | |
8468 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
8469 | | SEC_DATA); | |
8470 | bfd_set_section_alignment (stdoutput, seg, 4); | |
8471 | } | |
8472 | demand_empty_rest_of_line (); | |
8473 | break; | |
8474 | } | |
8475 | else | |
8476 | { | |
8477 | as_bad ("Global pointers not supported; recompile -G 0"); | |
8478 | demand_empty_rest_of_line (); | |
8479 | return; | |
8480 | } | |
3d3c5039 | 8481 | } |
88225433 | 8482 | |
670a50eb | 8483 | auto_align = 1; |
3d3c5039 ILT |
8484 | } |
8485 | ||
739708fa KR |
8486 | void |
8487 | mips_enable_auto_align () | |
9da4c5d1 | 8488 | { |
9da4c5d1 ILT |
8489 | auto_align = 1; |
8490 | } | |
8491 | ||
3d3c5039 ILT |
8492 | static void |
8493 | s_cons (log_size) | |
8494 | int log_size; | |
8495 | { | |
23dc1ae3 ILT |
8496 | symbolS *label; |
8497 | ||
8498 | label = insn_label; | |
becfe05e | 8499 | mips_emit_delays (); |
670a50eb | 8500 | if (log_size > 0 && auto_align) |
23dc1ae3 | 8501 | mips_align (log_size, 0, label); |
1849d646 | 8502 | insn_label = NULL; |
670a50eb | 8503 | cons (1 << log_size); |
3d3c5039 ILT |
8504 | } |
8505 | ||
3d3c5039 | 8506 | static void |
becfe05e ILT |
8507 | s_float_cons (type) |
8508 | int type; | |
3d3c5039 | 8509 | { |
23dc1ae3 ILT |
8510 | symbolS *label; |
8511 | ||
8512 | label = insn_label; | |
8513 | ||
becfe05e | 8514 | mips_emit_delays (); |
670a50eb ILT |
8515 | |
8516 | if (auto_align) | |
becfe05e | 8517 | if (type == 'd') |
23dc1ae3 | 8518 | mips_align (3, 0, label); |
670a50eb | 8519 | else |
23dc1ae3 | 8520 | mips_align (2, 0, label); |
670a50eb | 8521 | |
1849d646 ILT |
8522 | insn_label = NULL; |
8523 | ||
becfe05e | 8524 | float_cons (type); |
3d3c5039 ILT |
8525 | } |
8526 | ||
c1444ec4 ILT |
8527 | /* Handle .globl. We need to override it because on Irix 5 you are |
8528 | permitted to say | |
8529 | .globl foo .text | |
8530 | where foo is an undefined symbol, to mean that foo should be | |
8531 | considered to be the address of a function. */ | |
8532 | ||
8533 | static void | |
8534 | s_mips_globl (x) | |
8535 | int x; | |
8536 | { | |
8537 | char *name; | |
8538 | int c; | |
8539 | symbolS *symbolP; | |
fb251650 | 8540 | flagword flag; |
c1444ec4 ILT |
8541 | |
8542 | name = input_line_pointer; | |
8543 | c = get_symbol_end (); | |
8544 | symbolP = symbol_find_or_make (name); | |
8545 | *input_line_pointer = c; | |
8546 | SKIP_WHITESPACE (); | |
fb251650 ILT |
8547 | |
8548 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
8549 | being a function is apparently labelled as being an object. */ | |
8550 | flag = BSF_OBJECT; | |
8551 | ||
c1444ec4 ILT |
8552 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
8553 | { | |
8554 | char *secname; | |
8555 | asection *sec; | |
8556 | ||
8557 | secname = input_line_pointer; | |
8558 | c = get_symbol_end (); | |
8559 | sec = bfd_get_section_by_name (stdoutput, secname); | |
8560 | if (sec == NULL) | |
8561 | as_bad ("%s: no such section", secname); | |
8562 | *input_line_pointer = c; | |
8563 | ||
8564 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
fb251650 | 8565 | flag = BSF_FUNCTION; |
c1444ec4 ILT |
8566 | } |
8567 | ||
fb251650 ILT |
8568 | symbolP->bsym->flags |= flag; |
8569 | ||
c1444ec4 ILT |
8570 | S_SET_EXTERNAL (symbolP); |
8571 | demand_empty_rest_of_line (); | |
8572 | } | |
8573 | ||
3d3c5039 ILT |
8574 | static void |
8575 | s_option (x) | |
8576 | int x; | |
8577 | { | |
dd3f1f76 ILT |
8578 | char *opt; |
8579 | char c; | |
8580 | ||
8581 | opt = input_line_pointer; | |
8582 | c = get_symbol_end (); | |
8583 | ||
dd3f1f76 | 8584 | if (*opt == 'O') |
9226253a ILT |
8585 | { |
8586 | /* FIXME: What does this mean? */ | |
8587 | } | |
dd3f1f76 | 8588 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 8589 | { |
d9aba805 | 8590 | int i; |
42562568 | 8591 | |
d9aba805 ILT |
8592 | i = atoi (opt + 3); |
8593 | if (i == 0) | |
8594 | mips_pic = NO_PIC; | |
8595 | else if (i == 2) | |
8596 | mips_pic = SVR4_PIC; | |
8597 | else | |
8598 | as_bad (".option pic%d not supported", i); | |
8599 | ||
1dc1e798 | 8600 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
42562568 ILT |
8601 | { |
8602 | if (g_switch_seen && g_switch_value != 0) | |
d9aba805 | 8603 | as_warn ("-G may not be used with SVR4 PIC code"); |
42562568 ILT |
8604 | g_switch_value = 0; |
8605 | bfd_set_gp_size (stdoutput, 0); | |
8606 | } | |
9226253a | 8607 | } |
dd3f1f76 ILT |
8608 | else |
8609 | as_warn ("Unrecognized option \"%s\"", opt); | |
8610 | ||
8611 | *input_line_pointer = c; | |
670a50eb | 8612 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
8613 | } |
8614 | ||
8615 | static void | |
8616 | s_mipsset (x) | |
8617 | int x; | |
8618 | { | |
670a50eb ILT |
8619 | char *name = input_line_pointer, ch; |
8620 | ||
8621 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
8622 | input_line_pointer++; | |
8623 | ch = *input_line_pointer; | |
8624 | *input_line_pointer = '\0'; | |
8625 | ||
8626 | if (strcmp (name, "reorder") == 0) | |
8627 | { | |
4e95866e ILT |
8628 | if (mips_noreorder) |
8629 | { | |
8630 | prev_insn_unreordered = 1; | |
8631 | prev_prev_insn_unreordered = 1; | |
8632 | } | |
670a50eb ILT |
8633 | mips_noreorder = 0; |
8634 | } | |
8635 | else if (strcmp (name, "noreorder") == 0) | |
8636 | { | |
becfe05e | 8637 | mips_emit_delays (); |
670a50eb | 8638 | mips_noreorder = 1; |
0dd2d296 | 8639 | mips_any_noreorder = 1; |
670a50eb ILT |
8640 | } |
8641 | else if (strcmp (name, "at") == 0) | |
8642 | { | |
8643 | mips_noat = 0; | |
8644 | } | |
8645 | else if (strcmp (name, "noat") == 0) | |
8646 | { | |
8647 | mips_noat = 1; | |
3d3c5039 | 8648 | } |
670a50eb ILT |
8649 | else if (strcmp (name, "macro") == 0) |
8650 | { | |
8651 | mips_warn_about_macros = 0; | |
8652 | } | |
8653 | else if (strcmp (name, "nomacro") == 0) | |
8654 | { | |
8655 | if (mips_noreorder == 0) | |
8656 | as_bad ("`noreorder' must be set before `nomacro'"); | |
8657 | mips_warn_about_macros = 1; | |
8658 | } | |
8659 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
8660 | { | |
8661 | mips_nomove = 0; | |
8662 | } | |
8663 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
8664 | { | |
8665 | mips_nomove = 1; | |
8666 | } | |
8667 | else if (strcmp (name, "bopt") == 0) | |
8668 | { | |
8669 | mips_nobopt = 0; | |
8670 | } | |
8671 | else if (strcmp (name, "nobopt") == 0) | |
8672 | { | |
8673 | mips_nobopt = 1; | |
8674 | } | |
943321c0 ILT |
8675 | else if (strcmp (name, "mips16") == 0 |
8676 | || strcmp (name, "MIPS-16") == 0) | |
8677 | mips16 = 1; | |
8678 | else if (strcmp (name, "nomips16") == 0 | |
8679 | || strcmp (name, "noMIPS-16") == 0) | |
8680 | mips16 = 0; | |
1051c97f ILT |
8681 | else if (strncmp (name, "mips", 4) == 0) |
8682 | { | |
8683 | int isa; | |
8684 | ||
8685 | /* Permit the user to change the ISA on the fly. Needless to | |
8686 | say, misuse can cause serious problems. */ | |
8687 | isa = atoi (name + 4); | |
8688 | if (isa == 0) | |
8689 | mips_isa = file_mips_isa; | |
d8a1c247 | 8690 | else if (isa < 1 || isa > 4) |
1051c97f ILT |
8691 | as_bad ("unknown ISA level"); |
8692 | else | |
8693 | mips_isa = isa; | |
8694 | } | |
cc5703cd ILT |
8695 | else if (strcmp (name, "autoextend") == 0) |
8696 | mips16_autoextend = 1; | |
8697 | else if (strcmp (name, "noautoextend") == 0) | |
8698 | mips16_autoextend = 0; | |
670a50eb ILT |
8699 | else |
8700 | { | |
8701 | as_warn ("Tried to set unrecognized symbol: %s\n", name); | |
8702 | } | |
8703 | *input_line_pointer = ch; | |
8704 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
8705 | } |
8706 | ||
9226253a ILT |
8707 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
8708 | .option pic2. It means to generate SVR4 PIC calls. */ | |
8709 | ||
8710 | static void | |
8711 | s_abicalls (ignore) | |
8712 | int ignore; | |
8713 | { | |
d9aba805 | 8714 | mips_pic = SVR4_PIC; |
1dc1e798 KR |
8715 | if (USE_GLOBAL_POINTER_OPT) |
8716 | { | |
8717 | if (g_switch_seen && g_switch_value != 0) | |
8718 | as_warn ("-G may not be used with SVR4 PIC code"); | |
8719 | g_switch_value = 0; | |
8720 | } | |
d9aba805 | 8721 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
8722 | demand_empty_rest_of_line (); |
8723 | } | |
8724 | ||
8725 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
8726 | PIC code. It sets the $gp register for the function based on the | |
8727 | function address, which is in the register named in the argument. | |
8728 | This uses a relocation against _gp_disp, which is handled specially | |
8729 | by the linker. The result is: | |
8730 | lui $gp,%hi(_gp_disp) | |
8731 | addiu $gp,$gp,%lo(_gp_disp) | |
8732 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 8733 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
8734 | |
8735 | static void | |
8736 | s_cpload (ignore) | |
8737 | int ignore; | |
8738 | { | |
8739 | expressionS ex; | |
8740 | int icnt = 0; | |
8741 | ||
d9aba805 ILT |
8742 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
8743 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
8744 | { |
8745 | s_ignore (0); | |
8746 | return; | |
8747 | } | |
8748 | ||
8749 | /* .cpload should be a in .set noreorder section. */ | |
8750 | if (mips_noreorder == 0) | |
8751 | as_warn (".cpload not in noreorder section"); | |
8752 | ||
9226253a ILT |
8753 | ex.X_op = O_symbol; |
8754 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
8755 | ex.X_op_symbol = NULL; | |
8756 | ex.X_add_number = 0; | |
8757 | ||
fb251650 ILT |
8758 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
8759 | ex.X_add_symbol->bsym->flags |= BSF_OBJECT; | |
8760 | ||
0dd2d296 ILT |
8761 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
8762 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
8763 | (int) BFD_RELOC_LO16); |
8764 | ||
0dd2d296 ILT |
8765 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
8766 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
8767 | |
8768 | demand_empty_rest_of_line (); | |
8769 | } | |
8770 | ||
8771 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
8772 | offset from $sp. The offset is remembered, and after making a PIC | |
8773 | call $gp is restored from that location. */ | |
8774 | ||
8775 | static void | |
8776 | s_cprestore (ignore) | |
8777 | int ignore; | |
8778 | { | |
8779 | expressionS ex; | |
8780 | int icnt = 0; | |
8781 | ||
d9aba805 ILT |
8782 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
8783 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
8784 | { |
8785 | s_ignore (0); | |
8786 | return; | |
8787 | } | |
8788 | ||
9226253a ILT |
8789 | mips_cprestore_offset = get_absolute_expression (); |
8790 | ||
8791 | ex.X_op = O_constant; | |
8792 | ex.X_add_symbol = NULL; | |
8793 | ex.X_op_symbol = NULL; | |
8794 | ex.X_add_number = mips_cprestore_offset; | |
8795 | ||
0dd2d296 | 8796 | macro_build ((char *) NULL, &icnt, &ex, |
9226253a ILT |
8797 | mips_isa < 3 ? "sw" : "sd", |
8798 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); | |
8799 | ||
8800 | demand_empty_rest_of_line (); | |
8801 | } | |
8802 | ||
0dd2d296 ILT |
8803 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
8804 | code. It generates a 32 bit GP relative reloc. */ | |
8805 | ||
8806 | static void | |
8807 | s_gpword (ignore) | |
8808 | int ignore; | |
8809 | { | |
23dc1ae3 | 8810 | symbolS *label; |
0dd2d296 ILT |
8811 | expressionS ex; |
8812 | char *p; | |
8813 | ||
8814 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 8815 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
8816 | { |
8817 | s_cons (2); | |
8818 | return; | |
8819 | } | |
8820 | ||
23dc1ae3 | 8821 | label = insn_label; |
0dd2d296 ILT |
8822 | mips_emit_delays (); |
8823 | if (auto_align) | |
23dc1ae3 | 8824 | mips_align (2, 0, label); |
0dd2d296 ILT |
8825 | insn_label = NULL; |
8826 | ||
8827 | expression (&ex); | |
8828 | ||
8829 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
8830 | { | |
8831 | as_bad ("Unsupported use of .gpword"); | |
8832 | ignore_rest_of_line (); | |
8833 | } | |
8834 | ||
8835 | p = frag_more (4); | |
8836 | md_number_to_chars (p, (valueT) 0, 4); | |
8837 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
8838 | BFD_RELOC_MIPS_GPREL32); | |
8839 | ||
8840 | demand_empty_rest_of_line (); | |
8841 | } | |
8842 | ||
8843 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
8844 | tables in SVR4 PIC code. */ | |
8845 | ||
8846 | static void | |
8847 | s_cpadd (ignore) | |
8848 | int ignore; | |
8849 | { | |
8850 | int icnt = 0; | |
8851 | int reg; | |
8852 | ||
8853 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 8854 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
8855 | { |
8856 | s_ignore (0); | |
8857 | return; | |
8858 | } | |
8859 | ||
8860 | /* Add $gp to the register named as an argument. */ | |
8861 | reg = tc_get_register (0); | |
8862 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
8863 | mips_isa < 3 ? "addu" : "daddu", | |
8864 | "d,v,t", reg, reg, GP); | |
8865 | ||
8866 | demand_empty_rest_of_line (); | |
8867 | } | |
8868 | ||
9226253a | 8869 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
8870 | to parse .frame. The argument is non-zero if this is the frame |
8871 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 8872 | |
3d3c5039 | 8873 | int |
0dd2d296 ILT |
8874 | tc_get_register (frame) |
8875 | int frame; | |
3d3c5039 ILT |
8876 | { |
8877 | int reg; | |
8878 | ||
8879 | SKIP_WHITESPACE (); | |
8880 | if (*input_line_pointer++ != '$') | |
8881 | { | |
8882 | as_warn ("expected `$'"); | |
0dd2d296 | 8883 | reg = 0; |
3d3c5039 | 8884 | } |
0dd2d296 | 8885 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
8886 | { |
8887 | reg = get_absolute_expression (); | |
8888 | if (reg < 0 || reg >= 32) | |
8889 | { | |
8890 | as_warn ("Bad register number"); | |
8891 | reg = 0; | |
8892 | } | |
8893 | } | |
8894 | else | |
8895 | { | |
8896 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 8897 | reg = FP; |
3d3c5039 | 8898 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 8899 | reg = SP; |
3d3c5039 | 8900 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 8901 | reg = GP; |
3d3c5039 | 8902 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 8903 | reg = AT; |
3d3c5039 ILT |
8904 | else |
8905 | { | |
8906 | as_warn ("Unrecognized register name"); | |
0dd2d296 | 8907 | reg = 0; |
3d3c5039 ILT |
8908 | } |
8909 | input_line_pointer += 2; | |
8910 | } | |
0dd2d296 ILT |
8911 | if (frame) |
8912 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
8913 | return reg; |
8914 | } | |
8915 | ||
0dd2d296 ILT |
8916 | valueT |
8917 | md_section_align (seg, addr) | |
8918 | asection *seg; | |
8919 | valueT addr; | |
8920 | { | |
8921 | int align = bfd_get_section_alignment (stdoutput, seg); | |
8922 | ||
cf32394d ILT |
8923 | #ifdef OBJ_ELF |
8924 | /* We don't need to align ELF sections to the full alignment. | |
8925 | However, Irix 5 may prefer that we align them at least to a 16 | |
8926 | byte boundary. */ | |
943321c0 ILT |
8927 | if (align > 4) |
8928 | align = 4; | |
10a14e36 | 8929 | #endif |
cf32394d ILT |
8930 | |
8931 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
0dd2d296 ILT |
8932 | } |
8933 | ||
d8a1c247 KR |
8934 | /* Utility routine, called from above as well. If called while the |
8935 | input file is still being read, it's only an approximation. (For | |
8936 | example, a symbol may later become defined which appeared to be | |
8937 | undefined earlier.) */ | |
22ba90ce ILT |
8938 | |
8939 | static int | |
8940 | nopic_need_relax (sym) | |
d8a1c247 KR |
8941 | symbolS *sym; |
8942 | { | |
8943 | if (sym == 0) | |
8944 | return 0; | |
8945 | ||
1dc1e798 KR |
8946 | if (USE_GLOBAL_POINTER_OPT) |
8947 | { | |
8948 | const char *symname; | |
8949 | int change; | |
8950 | ||
8951 | /* Find out whether this symbol can be referenced off the GP | |
8952 | register. It can be if it is smaller than the -G size or if | |
8953 | it is in the .sdata or .sbss section. Certain symbols can | |
8954 | not be referenced off the GP, although it appears as though | |
8955 | they can. */ | |
8956 | symname = S_GET_NAME (sym); | |
8957 | if (symname != (const char *) NULL | |
8958 | && (strcmp (symname, "eprol") == 0 | |
8959 | || strcmp (symname, "etext") == 0 | |
8960 | || strcmp (symname, "_gp") == 0 | |
8961 | || strcmp (symname, "edata") == 0 | |
8962 | || strcmp (symname, "_fbss") == 0 | |
8963 | || strcmp (symname, "_fdata") == 0 | |
8964 | || strcmp (symname, "_ftext") == 0 | |
8965 | || strcmp (symname, "end") == 0 | |
8966 | || strcmp (symname, "_gp_disp") == 0)) | |
8967 | change = 1; | |
8968 | else if (! S_IS_DEFINED (sym) | |
c625fc23 JSC |
8969 | && (0 |
8970 | #ifndef NO_ECOFF_DEBUGGING | |
8971 | || (sym->ecoff_extern_size != 0 | |
8972 | && sym->ecoff_extern_size <= g_switch_value) | |
8973 | #endif | |
1dc1e798 KR |
8974 | || (S_GET_VALUE (sym) != 0 |
8975 | && S_GET_VALUE (sym) <= g_switch_value))) | |
8976 | change = 0; | |
8977 | else | |
8978 | { | |
8979 | const char *segname; | |
d8a1c247 | 8980 | |
1dc1e798 KR |
8981 | segname = segment_name (S_GET_SEGMENT (sym)); |
8982 | assert (strcmp (segname, ".lit8") != 0 | |
8983 | && strcmp (segname, ".lit4") != 0); | |
8984 | change = (strcmp (segname, ".sdata") != 0 | |
8985 | && strcmp (segname, ".sbss") != 0); | |
8986 | } | |
8987 | return change; | |
8988 | } | |
8989 | else | |
8990 | /* We are not optimizing for the GP register. */ | |
8991 | return 1; | |
d8a1c247 KR |
8992 | } |
8993 | ||
cc5703cd ILT |
8994 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
8995 | extended opcode. SEC is the section the frag is in. */ | |
8996 | ||
8997 | static int | |
8998 | mips16_extended_frag (fragp, sec, stretch) | |
8999 | fragS *fragp; | |
9000 | asection *sec; | |
9001 | long stretch; | |
9002 | { | |
9003 | int type; | |
9004 | register const struct mips16_immed_operand *op; | |
9005 | offsetT val; | |
9006 | int mintiny, maxtiny; | |
9007 | ||
9008 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
9009 | op = mips16_immed_operands; | |
9010 | while (op->type != type) | |
9011 | { | |
9012 | ++op; | |
9013 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9014 | } | |
9015 | ||
9016 | if (op->unsp) | |
9017 | { | |
9018 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9019 | { | |
9020 | mintiny = 1; | |
9021 | maxtiny = 1 << op->nbits; | |
9022 | } | |
9023 | else | |
9024 | { | |
9025 | mintiny = 0; | |
9026 | maxtiny = (1 << op->nbits) - 1; | |
9027 | } | |
9028 | } | |
9029 | else | |
9030 | { | |
9031 | mintiny = - (1 << (op->nbits - 1)); | |
9032 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9033 | } | |
9034 | ||
9035 | /* FIXME: If this is an expression symbol, this will fix its value. | |
9036 | If the expression is actually a subtraction of two symbols in the | |
9037 | segment being relaxed, the value will get fixed inappropriately. */ | |
9038 | val = S_GET_VALUE (fragp->fr_symbol); | |
9039 | ||
9040 | /* When we are called, symbol values are offsets within a frag. The | |
9041 | address of the frag has not yet been added into the value. */ | |
9042 | val += fragp->fr_symbol->sy_frag->fr_address; | |
9043 | ||
9044 | if (op->pcrel) | |
9045 | { | |
9046 | addressT addr; | |
9047 | ||
9048 | /* We won't have the section when we are called from | |
9049 | mips_relax_frag. However, we will always have been called | |
9050 | from md_estimate_size_before_relax first. If this is a | |
9051 | branch to a different section, we mark it as such. If SEC is | |
9052 | NULL, and the frag is not marked, then it must be a branch to | |
9053 | the same section. */ | |
9054 | if (sec == NULL) | |
9055 | { | |
9056 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
9057 | return 1; | |
9058 | } | |
9059 | else | |
9060 | { | |
9061 | if (S_GET_SEGMENT (fragp->fr_symbol) != sec) | |
9062 | { | |
9063 | fragp->fr_subtype = | |
9064 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9065 | ||
9066 | /* FIXME: We should support this, and let the linker | |
9067 | catch branches and loads that are out of range. */ | |
9068 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
9069 | "unsupported PC relative reference to different section"); | |
9070 | ||
9071 | return 1; | |
9072 | } | |
9073 | } | |
9074 | ||
9075 | /* In this case, we know for sure that the symbol fragment is in | |
9076 | the same section. If the fr_address of the symbol fragment | |
9077 | is greater then the address of this fragment we want to add | |
9078 | in STRETCH in order to get a better estimate of the address. | |
9079 | This particularly matters because of the shift bits. */ | |
9080 | if (stretch != 0 | |
9081 | && fragp->fr_symbol->sy_frag->fr_address >= fragp->fr_address) | |
9082 | { | |
9083 | fragS *f; | |
9084 | ||
9085 | /* Adjust stretch for any alignment frag. */ | |
9086 | for (f = fragp; f != fragp->fr_symbol->sy_frag; f = f->fr_next) | |
9087 | { | |
9088 | assert (f != NULL); | |
9089 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
9090 | { | |
9091 | if (stretch < 0) | |
9092 | stretch = - ((- stretch) | |
9093 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
9094 | else | |
9095 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
9096 | if (stretch == 0) | |
9097 | break; | |
9098 | } | |
9099 | } | |
9100 | val += stretch; | |
9101 | } | |
9102 | ||
9103 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
9104 | ||
9105 | /* If we are currently assuming that this frag should be | |
9106 | extended, then the current address is two bytes higher. */ | |
9107 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9108 | addr += 2; | |
9109 | ||
9110 | val -= addr & ~ ((1 << op->shift) - 1); | |
9111 | ||
9112 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9113 | if (type == 'p' || type == 'q') | |
9114 | val /= 2; | |
9115 | ||
9116 | /* If any of the shifted bits are set, we must use an extended | |
9117 | opcode. If the address depends on the size of this | |
9118 | instruction, this can lead to a loop, so we arrange to always | |
9119 | use an extended opcode. */ | |
9120 | if ((val & ((1 << op->shift) - 1)) != 0) | |
9121 | { | |
9122 | fragp->fr_subtype = | |
9123 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9124 | return 1; | |
9125 | } | |
9126 | } | |
9127 | ||
9128 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9129 | || val < (mintiny << op->shift) | |
9130 | || val > (maxtiny << op->shift)) | |
9131 | return 1; | |
9132 | else | |
9133 | return 0; | |
9134 | } | |
9135 | ||
9136 | /* Estimate the size of a frag before relaxing. Unless this is the | |
9137 | mips16, we are not really relaxing here, and the final size is | |
9138 | encoded in the subtype information. For the mips16, we have to | |
9139 | decide whether we are using an extended opcode or not. */ | |
22ba90ce | 9140 | |
0dd2d296 ILT |
9141 | /*ARGSUSED*/ |
9142 | int | |
9143 | md_estimate_size_before_relax (fragp, segtype) | |
9144 | fragS *fragp; | |
9145 | asection *segtype; | |
9146 | { | |
9147 | int change; | |
9148 | ||
cc5703cd ILT |
9149 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
9150 | { | |
9151 | if (mips16_extended_frag (fragp, segtype, 0)) | |
9152 | { | |
9153 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
9154 | return 4; | |
9155 | } | |
9156 | else | |
9157 | { | |
9158 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
9159 | return 2; | |
9160 | } | |
9161 | } | |
9162 | ||
d9aba805 | 9163 | if (mips_pic == NO_PIC) |
0dd2d296 | 9164 | { |
d8a1c247 | 9165 | change = nopic_need_relax (fragp->fr_symbol); |
0dd2d296 | 9166 | } |
d9aba805 | 9167 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
9168 | { |
9169 | asection *symsec = fragp->fr_symbol->bsym->section; | |
9170 | ||
9171 | /* This must duplicate the test in adjust_reloc_syms. */ | |
9172 | change = (symsec != &bfd_und_section | |
9173 | && symsec != &bfd_abs_section | |
9174 | && ! bfd_is_com_section (symsec)); | |
9175 | } | |
d9aba805 ILT |
9176 | else |
9177 | abort (); | |
0dd2d296 ILT |
9178 | |
9179 | if (change) | |
9180 | { | |
9181 | /* Record the offset to the first reloc in the fr_opcode field. | |
9182 | This lets md_convert_frag and tc_gen_reloc know that the code | |
9183 | must be expanded. */ | |
9184 | fragp->fr_opcode = (fragp->fr_literal | |
9185 | + fragp->fr_fix | |
9186 | - RELAX_OLD (fragp->fr_subtype) | |
9187 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
9188 | /* FIXME: This really needs as_warn_where. */ | |
9189 | if (RELAX_WARN (fragp->fr_subtype)) | |
9190 | as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\""); | |
9191 | } | |
9192 | ||
9193 | if (! change) | |
9194 | return 0; | |
9195 | else | |
9196 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
9197 | } | |
9198 | ||
9199 | /* Translate internal representation of relocation info to BFD target | |
9200 | format. */ | |
9201 | ||
9202 | arelent ** | |
3d3c5039 ILT |
9203 | tc_gen_reloc (section, fixp) |
9204 | asection *section; | |
9205 | fixS *fixp; | |
9206 | { | |
0dd2d296 | 9207 | static arelent *retval[4]; |
3d3c5039 | 9208 | arelent *reloc; |
a8aed9dd | 9209 | bfd_reloc_code_real_type code; |
3d3c5039 | 9210 | |
0dd2d296 ILT |
9211 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
9212 | retval[1] = NULL; | |
3d3c5039 ILT |
9213 | |
9214 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
9215 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
9216 | |
9217 | if (mips_pic == EMBEDDED_PIC | |
9218 | && SWITCH_TABLE (fixp)) | |
9219 | { | |
9220 | /* For a switch table entry we use a special reloc. The addend | |
9221 | is actually the difference between the reloc address and the | |
9222 | subtrahend. */ | |
9223 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
1dc1e798 KR |
9224 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
9225 | as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc"); | |
1c803e52 ILT |
9226 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
9227 | } | |
ecd4ca1c ILT |
9228 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
9229 | { | |
9230 | /* We use a special addend for an internal RELLO reloc. */ | |
9231 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
9232 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
9233 | else | |
9234 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
9235 | } | |
9236 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
9237 | { | |
9238 | assert (fixp->fx_next != NULL | |
9239 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
9240 | /* We use a special addend for an internal RELHI reloc. The | |
9241 | reloc is relative to the RELLO; adjust the addend | |
9242 | accordingly. */ | |
9243 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
9244 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
9245 | + fixp->fx_next->fx_where | |
9246 | - S_GET_VALUE (fixp->fx_subsy)); | |
9247 | else | |
9248 | reloc->addend = (fixp->fx_addnumber | |
9249 | + fixp->fx_next->fx_frag->fr_address | |
9250 | + fixp->fx_next->fx_where); | |
9251 | } | |
1c803e52 | 9252 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
9253 | reloc->addend = fixp->fx_addnumber; |
9254 | else | |
5b63f465 | 9255 | { |
1dc1e798 KR |
9256 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
9257 | /* A gruesome hack which is a result of the gruesome gas reloc | |
9258 | handling. */ | |
9259 | reloc->addend = reloc->address; | |
9260 | else | |
9261 | reloc->addend = -reloc->address; | |
5b63f465 | 9262 | } |
0dd2d296 ILT |
9263 | |
9264 | /* If this is a variant frag, we may need to adjust the existing | |
9265 | reloc and generate a new one. */ | |
9266 | if (fixp->fx_frag->fr_opcode != NULL | |
9267 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
9268 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
fb251650 ILT |
9269 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
9270 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
9271 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
9272 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
9273 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
0dd2d296 ILT |
9274 | { |
9275 | arelent *reloc2; | |
9276 | ||
cc5703cd ILT |
9277 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); |
9278 | ||
0dd2d296 | 9279 | /* If this is not the last reloc in this frag, then we have two |
fb251650 ILT |
9280 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
9281 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
9282 | the second one handle all of them. */ | |
0dd2d296 ILT |
9283 | if (fixp->fx_next != NULL |
9284 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
9285 | { | |
fb251650 ILT |
9286 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
9287 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
9288 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
9289 | && (fixp->fx_next->fx_r_type | |
9290 | == BFD_RELOC_MIPS_GOT_LO16)) | |
9291 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
9292 | && (fixp->fx_next->fx_r_type | |
9293 | == BFD_RELOC_MIPS_CALL_LO16))); | |
0dd2d296 ILT |
9294 | retval[0] = NULL; |
9295 | return retval; | |
9296 | } | |
9297 | ||
9298 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
9299 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
9300 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
9301 | retval[2] = NULL; | |
9302 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
9303 | reloc2->address = (reloc->address | |
9304 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
9305 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
9306 | reloc2->addend = fixp->fx_addnumber; | |
9307 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
9308 | assert (reloc2->howto != NULL); | |
9309 | ||
9310 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
9311 | { | |
9312 | arelent *reloc3; | |
9313 | ||
9314 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
9315 | retval[3] = NULL; | |
9316 | *reloc3 = *reloc2; | |
9317 | reloc3->address += 4; | |
9318 | } | |
9319 | ||
d9aba805 | 9320 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
9321 | { |
9322 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
9323 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
9324 | } | |
d9aba805 | 9325 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 9326 | { |
fb251650 | 9327 | switch (fixp->fx_r_type) |
0dd2d296 | 9328 | { |
fb251650 ILT |
9329 | default: |
9330 | abort (); | |
9331 | case BFD_RELOC_MIPS_GOT16: | |
9332 | break; | |
9333 | case BFD_RELOC_MIPS_CALL16: | |
9334 | case BFD_RELOC_MIPS_GOT_LO16: | |
9335 | case BFD_RELOC_MIPS_CALL_LO16: | |
0dd2d296 | 9336 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
fb251650 | 9337 | break; |
0dd2d296 ILT |
9338 | } |
9339 | } | |
d9aba805 ILT |
9340 | else |
9341 | abort (); | |
0dd2d296 ILT |
9342 | } |
9343 | ||
a8aed9dd ILT |
9344 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that |
9345 | fixup_segment converted a non-PC relative reloc into a PC | |
9346 | relative reloc. In such a case, we need to convert the reloc | |
9347 | code. */ | |
9348 | code = fixp->fx_r_type; | |
9349 | if (fixp->fx_pcrel) | |
9350 | { | |
9351 | switch (code) | |
9352 | { | |
9353 | case BFD_RELOC_8: | |
9354 | code = BFD_RELOC_8_PCREL; | |
9355 | break; | |
9356 | case BFD_RELOC_16: | |
9357 | code = BFD_RELOC_16_PCREL; | |
9358 | break; | |
9359 | case BFD_RELOC_32: | |
9360 | code = BFD_RELOC_32_PCREL; | |
9361 | break; | |
bf39474f ILT |
9362 | case BFD_RELOC_64: |
9363 | code = BFD_RELOC_64_PCREL; | |
9364 | break; | |
a8aed9dd ILT |
9365 | case BFD_RELOC_8_PCREL: |
9366 | case BFD_RELOC_16_PCREL: | |
9367 | case BFD_RELOC_32_PCREL: | |
bf39474f | 9368 | case BFD_RELOC_64_PCREL: |
a8aed9dd | 9369 | case BFD_RELOC_16_PCREL_S2: |
97aca1bc ILT |
9370 | case BFD_RELOC_PCREL_HI16_S: |
9371 | case BFD_RELOC_PCREL_LO16: | |
a8aed9dd ILT |
9372 | break; |
9373 | default: | |
9374 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
9375 | "Cannot make %s relocation PC relative", | |
9376 | bfd_get_reloc_code_name (code)); | |
9377 | } | |
9378 | } | |
9379 | ||
d9aba805 ILT |
9380 | /* To support a PC relative reloc when generating embedded PIC code |
9381 | for ECOFF, we use a Cygnus extension. We check for that here to | |
9382 | make sure that we don't let such a reloc escape normally. */ | |
1dc1e798 | 9383 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
a8aed9dd | 9384 | && code == BFD_RELOC_16_PCREL_S2 |
d9aba805 ILT |
9385 | && mips_pic != EMBEDDED_PIC) |
9386 | reloc->howto = NULL; | |
9387 | else | |
a8aed9dd | 9388 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
0dd2d296 | 9389 | |
52aa70b5 JW |
9390 | if (reloc->howto == NULL) |
9391 | { | |
9392 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
a8aed9dd ILT |
9393 | "Can not represent %s relocation in this object file format", |
9394 | bfd_get_reloc_code_name (code)); | |
0dd2d296 | 9395 | retval[0] = NULL; |
52aa70b5 | 9396 | } |
3d3c5039 | 9397 | |
0dd2d296 | 9398 | return retval; |
3d3c5039 ILT |
9399 | } |
9400 | ||
cc5703cd ILT |
9401 | /* Relax a machine dependent frag. This returns the amount by which |
9402 | the current size of the frag should change. */ | |
9403 | ||
9404 | int | |
9405 | mips_relax_frag (fragp, stretch) | |
9406 | fragS *fragp; | |
9407 | long stretch; | |
9408 | { | |
9409 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
9410 | return 0; | |
9411 | ||
9412 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
9413 | { | |
9414 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9415 | return 0; | |
9416 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
9417 | return 2; | |
9418 | } | |
9419 | else | |
9420 | { | |
9421 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9422 | return 0; | |
9423 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
9424 | return -2; | |
9425 | } | |
9426 | ||
9427 | return 0; | |
9428 | } | |
9429 | ||
0dd2d296 ILT |
9430 | /* Convert a machine dependent frag. */ |
9431 | ||
9432 | void | |
9433 | md_convert_frag (abfd, asec, fragp) | |
9434 | bfd *abfd; | |
9435 | segT asec; | |
9436 | fragS *fragp; | |
3d3c5039 | 9437 | { |
0dd2d296 ILT |
9438 | int old, new; |
9439 | char *fixptr; | |
3d3c5039 | 9440 | |
cc5703cd ILT |
9441 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
9442 | { | |
9443 | int type; | |
9444 | register const struct mips16_immed_operand *op; | |
9445 | boolean small, ext; | |
9446 | offsetT val; | |
9447 | bfd_byte *buf; | |
9448 | unsigned long insn; | |
9449 | boolean use_extend; | |
9450 | unsigned short extend; | |
9451 | ||
9452 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
9453 | op = mips16_immed_operands; | |
9454 | while (op->type != type) | |
9455 | ++op; | |
9456 | ||
9457 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9458 | { | |
9459 | small = false; | |
9460 | ext = true; | |
9461 | } | |
9462 | else | |
9463 | { | |
9464 | small = true; | |
9465 | ext = false; | |
9466 | } | |
9467 | ||
9468 | val = S_GET_VALUE (fragp->fr_symbol); | |
9469 | val += fragp->fr_symbol->sy_frag->fr_address; | |
9470 | if (op->pcrel) | |
9471 | { | |
9472 | addressT addr; | |
9473 | ||
9474 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
9475 | if (ext) | |
9476 | addr += 2; | |
9477 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
9478 | val -= addr; | |
9479 | } | |
9480 | ||
9481 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
9482 | ||
9483 | switch (byte_order) | |
9484 | { | |
9485 | default: | |
9486 | internalError (); | |
9487 | case LITTLE_ENDIAN: | |
9488 | insn = bfd_getl16 (buf); | |
9489 | break; | |
9490 | case BIG_ENDIAN: | |
9491 | insn = bfd_getb16 (buf); | |
9492 | break; | |
9493 | } | |
9494 | ||
9495 | mips16_immed (type, val, false, small, ext, &insn, &use_extend, &extend); | |
9496 | ||
9497 | if (use_extend) | |
9498 | { | |
9499 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
9500 | fragp->fr_fix += 2; | |
9501 | buf += 2; | |
9502 | } | |
3d3c5039 | 9503 | |
cc5703cd ILT |
9504 | md_number_to_chars (buf, insn, 2); |
9505 | fragp->fr_fix += 2; | |
9506 | buf += 2; | |
9507 | } | |
9508 | else | |
9509 | { | |
9510 | if (fragp->fr_opcode == NULL) | |
9511 | return; | |
0dd2d296 | 9512 | |
cc5703cd ILT |
9513 | old = RELAX_OLD (fragp->fr_subtype); |
9514 | new = RELAX_NEW (fragp->fr_subtype); | |
9515 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
0dd2d296 | 9516 | |
cc5703cd ILT |
9517 | if (new > 0) |
9518 | memcpy (fixptr - old, fixptr, new); | |
9519 | ||
9520 | fragp->fr_fix += new - old; | |
9521 | } | |
0dd2d296 | 9522 | } |
becfe05e ILT |
9523 | |
9524 | /* This function is called whenever a label is defined. It is used | |
9525 | when handling branch delays; if a branch has a label, we assume we | |
9526 | can not move it. */ | |
9527 | ||
9528 | void | |
9529 | mips_define_label (sym) | |
9530 | symbolS *sym; | |
9531 | { | |
9532 | insn_label = sym; | |
cc5703cd ILT |
9533 | #ifdef OBJ_ELF |
9534 | if (mips16) | |
9535 | S_SET_OTHER (insn_label, STO_MIPS16); | |
9536 | #endif | |
becfe05e | 9537 | } |
22ba90ce ILT |
9538 | |
9539 | /* Decide whether a label is local. This is called by LOCAL_LABEL. | |
9540 | In order to work with gcc when using mips-tfile, we must keep all | |
9541 | local labels. However, in other cases, we want to discard them, | |
9542 | since they are useless. */ | |
9543 | ||
9544 | int | |
9545 | mips_local_label (name) | |
9546 | const char *name; | |
9547 | { | |
c625fc23 | 9548 | #ifndef NO_ECOFF_DEBUGGING |
22ba90ce ILT |
9549 | if (ECOFF_DEBUGGING |
9550 | && mips_debug != 0 | |
9551 | && ! ecoff_debugging_seen) | |
9552 | { | |
9553 | /* We were called with -g, but we didn't see any debugging | |
9554 | information. That may mean that gcc is smuggling debugging | |
9555 | information through to mips-tfile, in which case we must | |
9556 | generate all local labels. */ | |
9557 | return 0; | |
9558 | } | |
c625fc23 | 9559 | #endif |
22ba90ce ILT |
9560 | |
9561 | /* Here it's OK to discard local labels. */ | |
9562 | ||
3af584b4 | 9563 | return name[0] == '$'; |
22ba90ce | 9564 | } |
3d3c5039 | 9565 | \f |
739708fa | 9566 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 9567 | |
0dd2d296 | 9568 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
9569 | |
9570 | void | |
9571 | mips_elf_final_processing () | |
9572 | { | |
87178180 ILT |
9573 | /* Write out the register information. */ |
9574 | if (! mips_64) | |
9575 | { | |
9576 | Elf32_RegInfo s; | |
9577 | ||
9578 | s.ri_gprmask = mips_gprmask; | |
9579 | s.ri_cprmask[0] = mips_cprmask[0]; | |
9580 | s.ri_cprmask[1] = mips_cprmask[1]; | |
9581 | s.ri_cprmask[2] = mips_cprmask[2]; | |
9582 | s.ri_cprmask[3] = mips_cprmask[3]; | |
9583 | /* The gp_value field is set by the MIPS ELF backend. */ | |
9584 | ||
9585 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
9586 | ((Elf32_External_RegInfo *) | |
9587 | mips_regmask_frag)); | |
9588 | } | |
9589 | else | |
9590 | { | |
9591 | Elf64_Internal_RegInfo s; | |
9592 | ||
9593 | s.ri_gprmask = mips_gprmask; | |
9594 | s.ri_pad = 0; | |
9595 | s.ri_cprmask[0] = mips_cprmask[0]; | |
9596 | s.ri_cprmask[1] = mips_cprmask[1]; | |
9597 | s.ri_cprmask[2] = mips_cprmask[2]; | |
9598 | s.ri_cprmask[3] = mips_cprmask[3]; | |
9599 | /* The gp_value field is set by the MIPS ELF backend. */ | |
9600 | ||
9601 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
9602 | ((Elf64_External_RegInfo *) | |
9603 | mips_regmask_frag)); | |
9604 | } | |
0dd2d296 ILT |
9605 | |
9606 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
9607 | sort of BFD interface for this. */ | |
9608 | if (mips_any_noreorder) | |
9609 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 9610 | if (mips_pic != NO_PIC) |
0dd2d296 | 9611 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
9612 | } |
9613 | ||
739708fa | 9614 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
f2a663d3 | 9615 | \f |
3d3c5039 ILT |
9616 | /* These functions should really be defined by the object file format, |
9617 | since they are related to debugging information. However, this | |
9618 | code has to work for the a.out format, which does not define them, | |
9619 | so we provide simple versions here. These don't actually generate | |
9620 | any debugging information, but they do simple checking and someday | |
9621 | somebody may make them useful. */ | |
9622 | ||
670a50eb ILT |
9623 | typedef struct loc |
9624 | { | |
9625 | struct loc *loc_next; | |
9626 | unsigned long loc_fileno; | |
9627 | unsigned long loc_lineno; | |
9628 | unsigned long loc_offset; | |
9629 | unsigned short loc_delta; | |
9630 | unsigned short loc_count; | |
3d3c5039 | 9631 | #if 0 |
670a50eb | 9632 | fragS *loc_frag; |
3d3c5039 | 9633 | #endif |
670a50eb ILT |
9634 | } |
9635 | locS; | |
3d3c5039 | 9636 | |
670a50eb ILT |
9637 | typedef struct proc |
9638 | { | |
3d3c5039 ILT |
9639 | struct proc *proc_next; |
9640 | struct symbol *proc_isym; | |
9641 | struct symbol *proc_end; | |
9642 | unsigned long proc_reg_mask; | |
9643 | unsigned long proc_reg_offset; | |
9644 | unsigned long proc_fpreg_mask; | |
9645 | unsigned long proc_fpreg_offset; | |
9646 | unsigned long proc_frameoffset; | |
9647 | unsigned long proc_framereg; | |
9648 | unsigned long proc_pcreg; | |
9649 | locS *proc_iline; | |
9650 | struct file *proc_file; | |
9651 | int proc_index; | |
670a50eb ILT |
9652 | } |
9653 | procS; | |
3d3c5039 | 9654 | |
670a50eb ILT |
9655 | typedef struct file |
9656 | { | |
3d3c5039 ILT |
9657 | struct file *file_next; |
9658 | unsigned long file_fileno; | |
9659 | struct symbol *file_symbol; | |
9660 | struct symbol *file_end; | |
9661 | struct proc *file_proc; | |
9662 | int file_numprocs; | |
670a50eb ILT |
9663 | } |
9664 | fileS; | |
3d3c5039 ILT |
9665 | |
9666 | static struct obstack proc_frags; | |
9667 | static procS *proc_lastP; | |
9668 | static procS *proc_rootP; | |
9669 | static int numprocs; | |
9670 | ||
9671 | static void | |
9672 | md_obj_begin () | |
9673 | { | |
670a50eb | 9674 | obstack_begin (&proc_frags, 0x2000); |
3d3c5039 ILT |
9675 | } |
9676 | ||
9677 | static void | |
9678 | md_obj_end () | |
9679 | { | |
9680 | /* check for premature end, nesting errors, etc */ | |
9681 | if (proc_lastP && proc_lastP->proc_end == NULL) | |
670a50eb | 9682 | as_warn ("missing `.end' at end of assembly"); |
3d3c5039 ILT |
9683 | } |
9684 | ||
3d3c5039 ILT |
9685 | static long |
9686 | get_number () | |
9687 | { | |
670a50eb ILT |
9688 | int negative = 0; |
9689 | long val = 0; | |
3d3c5039 | 9690 | |
670a50eb ILT |
9691 | if (*input_line_pointer == '-') |
9692 | { | |
9693 | ++input_line_pointer; | |
9694 | negative = 1; | |
3d3c5039 | 9695 | } |
670a50eb ILT |
9696 | if (!isdigit (*input_line_pointer)) |
9697 | as_bad ("Expected simple number."); | |
9698 | if (input_line_pointer[0] == '0') | |
9699 | { | |
9700 | if (input_line_pointer[1] == 'x') | |
9701 | { | |
9702 | input_line_pointer += 2; | |
9703 | while (isxdigit (*input_line_pointer)) | |
9704 | { | |
9705 | val <<= 4; | |
3a762a0b | 9706 | val |= hex_value (*input_line_pointer++); |
3d3c5039 | 9707 | } |
670a50eb ILT |
9708 | return negative ? -val : val; |
9709 | } | |
9710 | else | |
9711 | { | |
9712 | ++input_line_pointer; | |
9713 | while (isdigit (*input_line_pointer)) | |
9714 | { | |
9715 | val <<= 3; | |
9716 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 9717 | } |
670a50eb | 9718 | return negative ? -val : val; |
3d3c5039 ILT |
9719 | } |
9720 | } | |
670a50eb ILT |
9721 | if (!isdigit (*input_line_pointer)) |
9722 | { | |
9723 | printf (" *input_line_pointer == '%c' 0x%02x\n", | |
9724 | *input_line_pointer, *input_line_pointer); | |
9725 | as_warn ("Invalid number"); | |
9726 | return -1; | |
3d3c5039 | 9727 | } |
670a50eb ILT |
9728 | while (isdigit (*input_line_pointer)) |
9729 | { | |
9730 | val *= 10; | |
9731 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 9732 | } |
670a50eb | 9733 | return negative ? -val : val; |
3d3c5039 ILT |
9734 | } |
9735 | ||
9736 | /* The .file directive; just like the usual .file directive, but there | |
9737 | is an initial number which is the ECOFF file index. */ | |
9738 | ||
9739 | static void | |
9740 | s_file (x) | |
9741 | int x; | |
9742 | { | |
670a50eb | 9743 | int line; |
3d3c5039 | 9744 | |
670a50eb | 9745 | line = get_number (); |
9a7d824a | 9746 | s_app_file (0); |
3d3c5039 ILT |
9747 | } |
9748 | ||
9749 | ||
9750 | /* The .end directive. */ | |
9751 | ||
9752 | static void | |
9753 | s_mipsend (x) | |
9754 | int x; | |
9755 | { | |
670a50eb ILT |
9756 | symbolS *p; |
9757 | ||
9758 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
9759 | { | |
9760 | p = get_symbol (); | |
9761 | demand_empty_rest_of_line (); | |
9762 | } | |
9763 | else | |
9764 | p = NULL; | |
9765 | if (now_seg != text_section) | |
9766 | as_warn (".end not in text section"); | |
9767 | if (!proc_lastP) | |
9768 | { | |
9769 | as_warn (".end and no .ent seen yet."); | |
9770 | return; | |
3d3c5039 ILT |
9771 | } |
9772 | ||
670a50eb ILT |
9773 | if (p != NULL) |
9774 | { | |
9775 | assert (S_GET_NAME (p)); | |
9776 | if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) | |
9777 | as_warn (".end symbol does not match .ent symbol."); | |
3d3c5039 ILT |
9778 | } |
9779 | ||
670a50eb | 9780 | proc_lastP->proc_end = (symbolS *) 1; |
3d3c5039 ILT |
9781 | } |
9782 | ||
9783 | /* The .aent and .ent directives. */ | |
9784 | ||
9785 | static void | |
9786 | s_ent (aent) | |
9787 | int aent; | |
9788 | { | |
670a50eb ILT |
9789 | int number = 0; |
9790 | procS *procP; | |
9791 | symbolS *symbolP; | |
9792 | ||
9793 | symbolP = get_symbol (); | |
9794 | if (*input_line_pointer == ',') | |
9795 | input_line_pointer++; | |
dd3f1f76 | 9796 | SKIP_WHITESPACE (); |
670a50eb ILT |
9797 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
9798 | number = get_number (); | |
9799 | if (now_seg != text_section) | |
9800 | as_warn (".ent or .aent not in text section."); | |
9801 | ||
9802 | if (!aent && proc_lastP && proc_lastP->proc_end == NULL) | |
9803 | as_warn ("missing `.end'"); | |
9804 | ||
9805 | if (!aent) | |
9806 | { | |
9807 | procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); | |
9808 | procP->proc_isym = symbolP; | |
9809 | procP->proc_reg_mask = 0; | |
9810 | procP->proc_reg_offset = 0; | |
9811 | procP->proc_fpreg_mask = 0; | |
9812 | procP->proc_fpreg_offset = 0; | |
9813 | procP->proc_frameoffset = 0; | |
9814 | procP->proc_framereg = 0; | |
9815 | procP->proc_pcreg = 0; | |
9816 | procP->proc_end = NULL; | |
9817 | procP->proc_next = NULL; | |
9818 | if (proc_lastP) | |
9819 | proc_lastP->proc_next = procP; | |
9820 | else | |
9821 | proc_rootP = procP; | |
9822 | proc_lastP = procP; | |
9823 | numprocs++; | |
3d3c5039 | 9824 | } |
670a50eb | 9825 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
9826 | } |
9827 | ||
9828 | /* The .frame directive. */ | |
9829 | ||
88225433 | 9830 | #if 0 |
3d3c5039 ILT |
9831 | static void |
9832 | s_frame (x) | |
670a50eb | 9833 | int x; |
3d3c5039 | 9834 | { |
670a50eb ILT |
9835 | char str[100]; |
9836 | symbolS *symP; | |
9837 | int frame_reg; | |
9838 | int frame_off; | |
9839 | int pcreg; | |
9840 | ||
0dd2d296 | 9841 | frame_reg = tc_get_register (1); |
670a50eb ILT |
9842 | if (*input_line_pointer == ',') |
9843 | input_line_pointer++; | |
5ac34ac3 | 9844 | frame_off = get_absolute_expression (); |
670a50eb ILT |
9845 | if (*input_line_pointer == ',') |
9846 | input_line_pointer++; | |
0dd2d296 | 9847 | pcreg = tc_get_register (0); |
670a50eb ILT |
9848 | |
9849 | /* bob third eye */ | |
9850 | assert (proc_rootP); | |
9851 | proc_rootP->proc_framereg = frame_reg; | |
9852 | proc_rootP->proc_frameoffset = frame_off; | |
9853 | proc_rootP->proc_pcreg = pcreg; | |
9854 | /* bob macho .frame */ | |
9855 | ||
9856 | /* We don't have to write out a frame stab for unoptimized code. */ | |
9226253a | 9857 | if (!(frame_reg == FP && frame_off == 0)) |
670a50eb ILT |
9858 | { |
9859 | if (!proc_lastP) | |
9860 | as_warn ("No .ent for .frame to use."); | |
9861 | (void) sprintf (str, "R%d;%d", frame_reg, frame_off); | |
9862 | symP = symbol_new (str, N_VFP, 0, frag_now); | |
9863 | S_SET_TYPE (symP, N_RMASK); | |
9864 | S_SET_OTHER (symP, 0); | |
9865 | S_SET_DESC (symP, 0); | |
9866 | symP->sy_forward = proc_lastP->proc_isym; | |
9867 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 9868 | } |
670a50eb | 9869 | demand_empty_rest_of_line (); |
3d3c5039 | 9870 | } |
88225433 | 9871 | #endif |
3d3c5039 ILT |
9872 | |
9873 | /* The .fmask and .mask directives. */ | |
9874 | ||
88225433 | 9875 | #if 0 |
3d3c5039 ILT |
9876 | static void |
9877 | s_mask (reg_type) | |
9878 | char reg_type; | |
9879 | { | |
670a50eb ILT |
9880 | char str[100], *strP; |
9881 | symbolS *symP; | |
9882 | int i; | |
9883 | unsigned int mask; | |
9884 | int off; | |
9885 | ||
9886 | mask = get_number (); | |
9887 | if (*input_line_pointer == ',') | |
9888 | input_line_pointer++; | |
9889 | off = get_absolute_expression (); | |
9890 | ||
9891 | /* bob only for coff */ | |
9892 | assert (proc_rootP); | |
9893 | if (reg_type == 'F') | |
9894 | { | |
9895 | proc_rootP->proc_fpreg_mask = mask; | |
9896 | proc_rootP->proc_fpreg_offset = off; | |
3d3c5039 | 9897 | } |
670a50eb ILT |
9898 | else |
9899 | { | |
9900 | proc_rootP->proc_reg_mask = mask; | |
9901 | proc_rootP->proc_reg_offset = off; | |
9902 | } | |
9903 | ||
9904 | /* bob macho .mask + .fmask */ | |
3d3c5039 | 9905 | |
670a50eb ILT |
9906 | /* We don't have to write out a mask stab if no saved regs. */ |
9907 | if (!(mask == 0)) | |
9908 | { | |
9909 | if (!proc_lastP) | |
9910 | as_warn ("No .ent for .mask to use."); | |
9911 | strP = str; | |
9912 | for (i = 0; i < 32; i++) | |
9913 | { | |
9914 | if (mask % 2) | |
9915 | { | |
9916 | sprintf (strP, "%c%d,", reg_type, i); | |
9917 | strP += strlen (strP); | |
9918 | } | |
3d3c5039 | 9919 | mask /= 2; |
670a50eb ILT |
9920 | } |
9921 | sprintf (strP, ";%d,", off); | |
9922 | symP = symbol_new (str, N_RMASK, 0, frag_now); | |
9923 | S_SET_TYPE (symP, N_RMASK); | |
9924 | S_SET_OTHER (symP, 0); | |
9925 | S_SET_DESC (symP, 0); | |
9926 | symP->sy_forward = proc_lastP->proc_isym; | |
9927 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 9928 | } |
3d3c5039 | 9929 | } |
88225433 | 9930 | #endif |
3d3c5039 ILT |
9931 | |
9932 | /* The .loc directive. */ | |
9933 | ||
88225433 | 9934 | #if 0 |
3d3c5039 ILT |
9935 | static void |
9936 | s_loc (x) | |
9937 | int x; | |
9938 | { | |
670a50eb ILT |
9939 | symbolS *symbolP; |
9940 | int lineno; | |
9941 | int addroff; | |
3d3c5039 | 9942 | |
670a50eb | 9943 | assert (now_seg == text_section); |
3d3c5039 | 9944 | |
670a50eb | 9945 | lineno = get_number (); |
87e48495 | 9946 | addroff = frag_now_fix (); |
3d3c5039 | 9947 | |
670a50eb ILT |
9948 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
9949 | S_SET_TYPE (symbolP, N_SLINE); | |
9950 | S_SET_OTHER (symbolP, 0); | |
9951 | S_SET_DESC (symbolP, lineno); | |
9952 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 9953 | } |
88225433 | 9954 | #endif |