Commit | Line | Data |
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3d3c5039 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
65d2c7d3 | 2 | Copyright (C) 1993, 94, 95, 96, 97, 1998 Free Software Foundation, Inc. |
3d3c5039 ILT |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
fb251650 ILT |
21 | along with GAS; see the file COPYING. If not, write to the Free |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
3d3c5039 ILT |
24 | |
25 | #include "as.h" | |
8358c818 | 26 | #include "config.h" |
9da4c5d1 | 27 | #include "subsegs.h" |
3d3c5039 ILT |
28 | |
29 | #include <ctype.h> | |
30 | ||
1dc1e798 | 31 | #ifdef USE_STDARG |
3d3c5039 | 32 | #include <stdarg.h> |
1dc1e798 KR |
33 | #endif |
34 | #ifdef USE_VARARGS | |
3d3c5039 | 35 | #include <varargs.h> |
1dc1e798 | 36 | #endif |
3d3c5039 | 37 | |
918692a5 | 38 | #include "opcode/mips.h" |
efec4a28 DP |
39 | #include "itbl-ops.h" |
40 | ||
41 | #ifdef DEBUG | |
42 | #define DBG(x) printf x | |
43 | #else | |
44 | #define DBG(x) | |
45 | #endif | |
3d3c5039 | 46 | |
739708fa KR |
47 | #ifdef OBJ_MAYBE_ELF |
48 | /* Clean up namespace so we can include obj-elf.h too. */ | |
7cd06f44 | 49 | static int mips_output_flavor PARAMS ((void)); |
739708fa KR |
50 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } |
51 | #undef OBJ_PROCESS_STAB | |
52 | #undef OUTPUT_FLAVOR | |
53 | #undef S_GET_ALIGN | |
54 | #undef S_GET_SIZE | |
55 | #undef S_SET_ALIGN | |
56 | #undef S_SET_SIZE | |
57 | #undef TARGET_SYMBOL_FIELDS | |
58 | #undef obj_frob_file | |
cc5703cd | 59 | #undef obj_frob_file_after_relocs |
739708fa KR |
60 | #undef obj_frob_symbol |
61 | #undef obj_pop_insert | |
62 | #undef obj_sec_sym_ok_for_reloc | |
a3e8c5b7 | 63 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES |
739708fa KR |
64 | |
65 | #include "obj-elf.h" | |
66 | /* Fix any of them that we actually care about. */ | |
67 | #undef OUTPUT_FLAVOR | |
68 | #define OUTPUT_FLAVOR mips_output_flavor() | |
69 | #endif | |
70 | ||
71 | #if defined (OBJ_ELF) | |
f2a663d3 | 72 | #include "elf/mips.h" |
1dc1e798 | 73 | #endif |
f2a663d3 | 74 | |
739708fa | 75 | #ifndef ECOFF_DEBUGGING |
c625fc23 | 76 | #define NO_ECOFF_DEBUGGING |
739708fa KR |
77 | #define ECOFF_DEBUGGING 0 |
78 | #endif | |
79 | ||
22ba90ce ILT |
80 | #include "ecoff.h" |
81 | ||
a8aed9dd | 82 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 83 | static char *mips_regmask_frag; |
a8aed9dd | 84 | #endif |
f2a663d3 | 85 | |
3d3c5039 | 86 | #define AT 1 |
cc5703cd | 87 | #define TREG 24 |
9226253a | 88 | #define PIC_CALL_REG 25 |
b2b8c24e ILT |
89 | #define KT0 26 |
90 | #define KT1 27 | |
670a50eb | 91 | #define GP 28 |
9226253a ILT |
92 | #define SP 29 |
93 | #define FP 30 | |
3d3c5039 ILT |
94 | #define RA 31 |
95 | ||
cc5703cd ILT |
96 | #define ILLEGAL_REG (32) |
97 | ||
af942793 SS |
98 | /* Allow override of standard little-endian ECOFF format. */ |
99 | ||
100 | #ifndef ECOFF_LITTLE_FORMAT | |
101 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
102 | #endif | |
103 | ||
1dc1e798 | 104 | extern int target_big_endian; |
88225433 | 105 | |
7f9880e5 | 106 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the |
6fd819cf GRK |
107 | 32 bit ABI. This has no meaning for ECOFF. |
108 | Note that the default is always 32 bit, even if "configured" for | |
109 | 64 bit [e.g. --target=mips64-elf]. */ | |
7f9880e5 ILT |
110 | static int mips_64; |
111 | ||
04cb3372 | 112 | /* The default target format to use. */ |
1dc1e798 KR |
113 | const char * |
114 | mips_target_format () | |
115 | { | |
116 | switch (OUTPUT_FLAVOR) | |
117 | { | |
118 | case bfd_target_aout_flavour: | |
119 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
120 | case bfd_target_ecoff_flavour: | |
af942793 | 121 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; |
1dc1e798 | 122 | case bfd_target_elf_flavour: |
7f9880e5 ILT |
123 | return (target_big_endian |
124 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
125 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
1dc1e798 KR |
126 | default: |
127 | abort (); | |
a3e8c5b7 | 128 | return NULL; |
1dc1e798 KR |
129 | } |
130 | } | |
04cb3372 | 131 | |
d2c71068 | 132 | /* The name of the readonly data section. */ |
1dc1e798 KR |
133 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
134 | ? ".data" \ | |
135 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
136 | ? ".rdata" \ | |
137 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ | |
138 | ? ".rodata" \ | |
139 | : (abort (), "")) | |
d2c71068 | 140 | |
3c83da8a JW |
141 | /* This is the set of options which may be modified by the .set |
142 | pseudo-op. We use a struct so that .set push and .set pop are more | |
622b1860 ILT |
143 | reliable. |
144 | ||
145 | FIXME: The CPU specific variables (mips_4010, et. al.) should | |
146 | probably be in here as well, and there should probably be some way | |
147 | to set them. */ | |
3c83da8a JW |
148 | |
149 | struct mips_set_options | |
150 | { | |
151 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 | |
152 | if it has not been initialized. Changed by `.set mipsN', and the | |
153 | -mipsN command line option, and the default CPU. */ | |
154 | int isa; | |
155 | /* Whether we are assembling for the mips16 processor. 0 if we are | |
156 | not, 1 if we are, and -1 if the value has not been initialized. | |
157 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
158 | -nomips16 command line options, and the default CPU. */ | |
159 | int mips16; | |
160 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
161 | reorder' and `.set noreorder'. */ | |
162 | int noreorder; | |
163 | /* Non-zero if we should not permit the $at ($1) register to be used | |
164 | in instructions. Changed by `.set at' and `.set noat'. */ | |
165 | int noat; | |
166 | /* Non-zero if we should warn when a macro instruction expands into | |
167 | more than one machine instruction. Changed by `.set nomacro' and | |
168 | `.set macro'. */ | |
169 | int warn_about_macros; | |
170 | /* Non-zero if we should not move instructions. Changed by `.set | |
171 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
172 | int nomove; | |
173 | /* Non-zero if we should not optimize branches by moving the target | |
174 | of the branch into the delay slot. Actually, we don't perform | |
175 | this optimization anyhow. Changed by `.set bopt' and `.set | |
176 | nobopt'. */ | |
177 | int nobopt; | |
178 | /* Non-zero if we should not autoextend mips16 instructions. | |
179 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
180 | int noautoextend; | |
181 | }; | |
182 | ||
183 | /* This is the struct we use to hold the current set of options. Note | |
184 | that we must set the isa and mips16 fields to -1 to indicate that | |
185 | they have not been initialized. */ | |
186 | ||
187 | static struct mips_set_options mips_opts = { -1, -1 }; | |
188 | ||
1aa6938e ILT |
189 | /* These variables are filled in with the masks of registers used. |
190 | The object format code reads them and puts them in the appropriate | |
191 | place. */ | |
192 | unsigned long mips_gprmask; | |
193 | unsigned long mips_cprmask[4]; | |
194 | ||
1051c97f ILT |
195 | /* MIPS ISA we are using for this output file. */ |
196 | static int file_mips_isa; | |
197 | ||
8c63448a | 198 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
4bb0cc41 | 199 | static int mips_cpu = -1; |
8c63448a | 200 | |
b2b8c24e ILT |
201 | /* Whether the 4650 instructions (mad/madu) are permitted. */ |
202 | static int mips_4650 = -1; | |
203 | ||
e532b44c ILT |
204 | /* Whether the 4010 instructions are permitted. */ |
205 | static int mips_4010 = -1; | |
206 | ||
c625fc23 JSC |
207 | /* Whether the 4100 MADD16 and DMADD16 are permitted. */ |
208 | static int mips_4100 = -1; | |
209 | ||
2d035a50 GRK |
210 | /* start-sanitize-vr4320 */ |
211 | /* Whether NEC vr4320 instructions are permitted. */ | |
212 | static int mips_4320 = -1; | |
213 | ||
214 | /* end-sanitize-vr4320 */ | |
6b34ac5a | 215 | /* start-sanitize-cygnus */ |
aa2e0460 KR |
216 | /* Whether NEC vr5400 instructions are permitted. */ |
217 | static int mips_5400 = -1; | |
218 | ||
6b34ac5a | 219 | /* end-sanitize-cygnus */ |
276c2d7d GRK |
220 | /* start-sanitize-r5900 */ |
221 | /* Whether Toshiba r5900 instructions are permitted. */ | |
222 | static int mips_5900 = -1; | |
276c2d7d | 223 | |
aa2e0460 | 224 | /* end-sanitize-r5900 */ |
5c6f5923 GRK |
225 | /* Whether Toshiba r3900 instructions are permitted. */ |
226 | static int mips_3900 = -1; | |
227 | ||
42444087 GRK |
228 | /* start-sanitize-tx49 */ |
229 | /* Whether Toshiba r4900 instructions are permitted. */ | |
230 | static int mips_4900 = -1; | |
231 | ||
232 | /* end-sanitize-tx49 */ | |
4e96260f JL |
233 | /* start-sanitize-tx19 */ |
234 | /* The tx19 (r1900) is a mips16 decoder with a tx39(r3900) behind it. | |
235 | The tx19 related options and configuration bits are handled by | |
236 | the tx39 flags. */ | |
237 | /* end-sanitize-tx19 */ | |
238 | ||
5c6f5923 GRK |
239 | /* Whether the processor uses hardware interlocks to protect |
240 | reads from the HI and LO registers, and thus does not | |
622b1860 ILT |
241 | require nops to be inserted. |
242 | ||
243 | FIXME: We really should not be checking mips_cpu here. The -mcpu= | |
244 | option is documented to not do anything special. In gcc, the | |
245 | -mcpu= option only affects scheduling, and does not affect code | |
246 | generation. Each test of -mcpu= here should actually be testing a | |
247 | specific variable, such as mips_4010, and each such variable should | |
248 | have a command line option to set it. The -mcpu= option may be | |
249 | used to set the default value of these options, as is the case for | |
250 | mips_4010. */ | |
251 | ||
2cf51495 | 252 | #define hilo_interlocks (mips_4010 || mips_3900 \ |
4ebda395 | 253 | /* start-sanitize-tx49 */ \ |
42444087 | 254 | || mips_cpu == 4900 || mips_4900 \ |
4ebda395 | 255 | /* end-sanitize-tx49 */ \ |
2d035a50 GRK |
256 | /* start-sanitize-vr4320 */ \ |
257 | || mips_cpu == 4320 \ | |
258 | /* end-sanitize-vr4320 */ \ | |
be294de6 | 259 | /* start-sanitize-r5900 */ \ |
ec85f6bc | 260 | || mips_5900 \ |
be294de6 | 261 | /* end-sanitize-r5900 */ \ |
4ebda395 | 262 | ) |
5c6f5923 | 263 | |
a3e8c5b7 ILT |
264 | /* Whether the processor uses hardware interlocks to protect reads |
265 | from the GPRs, and thus does not require nops to be inserted. */ | |
266 | #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900) | |
6b34ac5a | 267 | /* start-sanitize-cygnus */ |
1c6f3441 ILT |
268 | #undef gpr_interlocks |
269 | #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900 || mips_5400) | |
6b34ac5a | 270 | /* end-sanitize-cygnus */ |
1c6f3441 | 271 | |
e532b44c | 272 | |
5c6f5923 | 273 | /* As with other "interlocks" this is used by hardware that has FP |
344a8d61 | 274 | (co-processor) interlocks. */ |
efec4a28 | 275 | /* Itbl support may require additional care here. */ |
2d035a50 GRK |
276 | #define cop_interlocks (mips_cpu == 4300 \ |
277 | /* start-sanitize-vr4320 */ \ | |
278 | || mips_cpu == 4320 \ | |
279 | /* end-sanitize-vr4320 */ \ | |
6b34ac5a | 280 | /* start-sanitize-cygnus */ \ |
2d035a50 | 281 | || mips_cpu == 5400 \ |
6b34ac5a | 282 | /* end-sanitize-cygnus */ \ |
2d035a50 | 283 | ) |
344a8d61 | 284 | |
d9aba805 ILT |
285 | /* MIPS PIC level. */ |
286 | ||
287 | enum mips_pic_level | |
288 | { | |
289 | /* Do not generate PIC code. */ | |
290 | NO_PIC, | |
291 | ||
292 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
293 | not sure what it is supposed to do. */ | |
294 | IRIX4_PIC, | |
295 | ||
296 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
297 | SVR4_PIC, | |
298 | ||
299 | /* Generate PIC code without using a global offset table: the data | |
300 | segment has a maximum size of 64K, all data references are off | |
301 | the $gp register, and all text references are PC relative. This | |
302 | is used on some embedded systems. */ | |
303 | EMBEDDED_PIC | |
304 | }; | |
305 | ||
306 | static enum mips_pic_level mips_pic; | |
9226253a | 307 | |
fb251650 ILT |
308 | /* 1 if we should generate 32 bit offsets from the GP register in |
309 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
310 | static int mips_big_got; | |
311 | ||
8ea7f4e8 ILT |
312 | /* 1 if trap instructions should used for overflow rather than break |
313 | instructions. */ | |
314 | static int mips_trap; | |
315 | ||
3c83da8a | 316 | /* Non-zero if any .set noreorder directives were used. */ |
cc5703cd | 317 | |
0dd2d296 | 318 | static int mips_any_noreorder; |
3d3c5039 | 319 | |
670a50eb ILT |
320 | /* The size of the small data section. */ |
321 | static int g_switch_value = 8; | |
42562568 ILT |
322 | /* Whether the -G option was used. */ |
323 | static int g_switch_seen = 0; | |
670a50eb | 324 | |
3d3c5039 ILT |
325 | #define N_RMASK 0xc4 |
326 | #define N_VFP 0xd4 | |
327 | ||
d8a1c247 KR |
328 | /* If we can determine in advance that GP optimization won't be |
329 | possible, we can skip the relaxation stuff that tries to produce | |
330 | GP-relative references. This makes delay slot optimization work | |
331 | better. | |
332 | ||
333 | This function can only provide a guess, but it seems to work for | |
334 | gcc output. If it guesses wrong, the only loss should be in | |
335 | efficiency; it shouldn't introduce any bugs. | |
336 | ||
337 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
338 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
85ce5635 | 339 | static int nopic_need_relax PARAMS ((symbolS *, int)); |
d8a1c247 | 340 | |
3d3c5039 ILT |
341 | /* handle of the OPCODE hash table */ |
342 | static struct hash_control *op_hash = NULL; | |
343 | ||
cc5703cd ILT |
344 | /* The opcode hash table we use for the mips16. */ |
345 | static struct hash_control *mips16_op_hash = NULL; | |
346 | ||
3d3c5039 ILT |
347 | /* This array holds the chars that always start a comment. If the |
348 | pre-processor is disabled, these aren't very useful */ | |
349 | const char comment_chars[] = "#"; | |
350 | ||
351 | /* This array holds the chars that only start a comment at the beginning of | |
352 | a line. If the line seems to have the form '# 123 filename' | |
353 | .line and .file directives will appear in the pre-processed output */ | |
354 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
355 | first line of the input file. This is because the compiler outputs | |
356 | #NO_APP at the beginning of its output. */ | |
357 | /* Also note that C style comments are always supported. */ | |
358 | const char line_comment_chars[] = "#"; | |
359 | ||
360 | /* This array holds machine specific line separator characters. */ | |
361 | const char line_separator_chars[] = ""; | |
362 | ||
363 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
364 | const char EXP_CHARS[] = "eE"; | |
365 | ||
366 | /* Chars that mean this number is a floating point constant */ | |
367 | /* As in 0f12.456 */ | |
368 | /* or 0d1.2345e12 */ | |
369 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
370 | ||
371 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
372 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
373 | but nothing is ideal around here. | |
374 | */ | |
375 | ||
670a50eb | 376 | static char *insn_error; |
3d3c5039 | 377 | |
3d3c5039 | 378 | static int auto_align = 1; |
becfe05e | 379 | |
9226253a ILT |
380 | /* When outputting SVR4 PIC code, the assembler needs to know the |
381 | offset in the stack frame from which to restore the $gp register. | |
382 | This is set by the .cprestore pseudo-op, and saved in this | |
383 | variable. */ | |
0dd2d296 ILT |
384 | static offsetT mips_cprestore_offset = -1; |
385 | ||
386 | /* This is the register which holds the stack frame, as set by the | |
387 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
388 | static int mips_frame_reg = SP; | |
9226253a | 389 | |
becfe05e ILT |
390 | /* To output NOP instructions correctly, we need to keep information |
391 | about the previous two instructions. */ | |
392 | ||
0aa07269 ILT |
393 | /* Whether we are optimizing. The default value of 2 means to remove |
394 | unneeded NOPs and swap branch instructions when possible. A value | |
395 | of 1 means to not swap branches. A value of 0 means to always | |
396 | insert NOPs. */ | |
397 | static int mips_optimize = 2; | |
4e95866e | 398 | |
22ba90ce ILT |
399 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
400 | equivalent to seeing no -g option at all. */ | |
401 | static int mips_debug = 0; | |
402 | ||
becfe05e ILT |
403 | /* The previous instruction. */ |
404 | static struct mips_cl_insn prev_insn; | |
405 | ||
406 | /* The instruction before prev_insn. */ | |
407 | static struct mips_cl_insn prev_prev_insn; | |
408 | ||
409 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
410 | point the insn_mo field at this dummy integer. */ | |
411 | static const struct mips_opcode dummy_opcode = { 0 }; | |
412 | ||
413 | /* Non-zero if prev_insn is valid. */ | |
414 | static int prev_insn_valid; | |
415 | ||
416 | /* The frag for the previous instruction. */ | |
417 | static struct frag *prev_insn_frag; | |
418 | ||
419 | /* The offset into prev_insn_frag for the previous instruction. */ | |
420 | static long prev_insn_where; | |
421 | ||
a677feeb ILT |
422 | /* The reloc type for the previous instruction, if any. */ |
423 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
424 | ||
becfe05e ILT |
425 | /* The reloc for the previous instruction, if any. */ |
426 | static fixS *prev_insn_fixp; | |
427 | ||
428 | /* Non-zero if the previous instruction was in a delay slot. */ | |
429 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
430 | |
431 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
432 | static int prev_insn_unreordered; | |
433 | ||
cc5703cd ILT |
434 | /* Non-zero if the previous instruction uses an extend opcode (if |
435 | mips16). */ | |
436 | static int prev_insn_extended; | |
437 | ||
4e95866e ILT |
438 | /* Non-zero if the previous previous instruction was in a .set |
439 | noreorder. */ | |
440 | static int prev_prev_insn_unreordered; | |
867a58b3 | 441 | |
7e656649 RH |
442 | /* start-sanitize-branchbug4011 */ |
443 | /* Non-zero if the previous insn had one or more labels */ | |
444 | static int prev_insn_labels; | |
445 | ||
446 | /* end-sanitize-branchbug4011 */ | |
4a1cb507 ILT |
447 | /* If this is set, it points to a frag holding nop instructions which |
448 | were inserted before the start of a noreorder section. If those | |
449 | nops turn out to be unnecessary, the size of the frag can be | |
450 | decreased. */ | |
451 | static fragS *prev_nop_frag; | |
452 | ||
453 | /* The number of nop instructions we created in prev_nop_frag. */ | |
454 | static int prev_nop_frag_holds; | |
455 | ||
456 | /* The number of nop instructions that we know we need in | |
457 | prev_nop_frag. */ | |
458 | static int prev_nop_frag_required; | |
459 | ||
460 | /* The number of instructions we've seen since prev_nop_frag. */ | |
461 | static int prev_nop_frag_since; | |
462 | ||
867a58b3 ILT |
463 | /* For ECOFF and ELF, relocations against symbols are done in two |
464 | parts, with a HI relocation and a LO relocation. Each relocation | |
465 | has only 16 bits of space to store an addend. This means that in | |
466 | order for the linker to handle carries correctly, it must be able | |
467 | to locate both the HI and the LO relocation. This means that the | |
468 | relocations must appear in order in the relocation table. | |
469 | ||
470 | In order to implement this, we keep track of each unmatched HI | |
471 | relocation. We then sort them so that they immediately precede the | |
472 | corresponding LO relocation. */ | |
473 | ||
474 | struct mips_hi_fixup | |
475 | { | |
476 | /* Next HI fixup. */ | |
477 | struct mips_hi_fixup *next; | |
478 | /* This fixup. */ | |
479 | fixS *fixp; | |
480 | /* The section this fixup is in. */ | |
481 | segT seg; | |
482 | }; | |
483 | ||
484 | /* The list of unmatched HI relocs. */ | |
485 | ||
486 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
cc5703cd ILT |
487 | |
488 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
489 | ||
490 | #define X ILLEGAL_REG | |
491 | static const int mips32_to_16_reg_map[] = | |
492 | { | |
493 | X, X, 2, 3, 4, 5, 6, 7, | |
494 | X, X, X, X, X, X, X, X, | |
495 | 0, 1, X, X, X, X, X, X, | |
496 | X, X, X, X, X, X, X, X | |
497 | }; | |
498 | #undef X | |
499 | ||
500 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
501 | ||
502 | static const int mips16_to_32_reg_map[] = | |
503 | { | |
504 | 16, 17, 2, 3, 4, 5, 6, 7 | |
505 | }; | |
3d3c5039 | 506 | \f |
0dd2d296 ILT |
507 | /* Since the MIPS does not have multiple forms of PC relative |
508 | instructions, we do not have to do relaxing as is done on other | |
509 | platforms. However, we do have to handle GP relative addressing | |
510 | correctly, which turns out to be a similar problem. | |
511 | ||
512 | Every macro that refers to a symbol can occur in (at least) two | |
513 | forms, one with GP relative addressing and one without. For | |
514 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 515 | a macro instruction like this: |
0dd2d296 ILT |
516 | lw $4,i |
517 | If i can be addressed off the GP register (this is true if it is in | |
518 | the .sbss or .sdata section, or if it is known to be smaller than | |
519 | the -G argument) this will generate the following instruction: | |
520 | lw $4,i($gp) | |
521 | This instruction will use a GPREL reloc. If i can not be addressed | |
522 | off the GP register, the following instruction sequence will be used: | |
523 | lui $at,i | |
524 | lw $4,i($at) | |
525 | In this case the first instruction will have a HI16 reloc, and the | |
526 | second reloc will have a LO16 reloc. Both relocs will be against | |
527 | the symbol i. | |
528 | ||
529 | The issue here is that we may not know whether i is GP addressable | |
530 | until after we see the instruction that uses it. Therefore, we | |
531 | want to be able to choose the final instruction sequence only at | |
532 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 533 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
534 | end of assembly. |
535 | ||
536 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
537 | addressing in quite the same way, but the issue still arises as |
538 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
539 | |
540 | We handle these issues by actually generating both possible | |
541 | instruction sequences. The longer one is put in a frag_var with | |
542 | type rs_machine_dependent. We encode what to do with the frag in | |
543 | the subtype field. We encode (1) the number of existing bytes to | |
544 | replace, (2) the number of new bytes to use, (3) the offset from | |
545 | the start of the existing bytes to the first reloc we must generate | |
546 | (that is, the offset is applied from the start of the existing | |
547 | bytes after they are replaced by the new bytes, if any), (4) the | |
548 | offset from the start of the existing bytes to the second reloc, | |
549 | (5) whether a third reloc is needed (the third reloc is always four | |
550 | bytes after the second reloc), and (6) whether to warn if this | |
551 | variant is used (this is sometimes needed if .set nomacro or .set | |
552 | noat is in effect). All these numbers are reasonably small. | |
553 | ||
554 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
555 | ensure that delay slots are handled correctly. Fortunately, there |
556 | are a limited number of cases. When the second instruction | |
557 | sequence is generated, append_insn is directed to maintain the | |
558 | existing delay slot information, so it continues to apply to any | |
559 | code after the second instruction sequence. This means that the | |
560 | second instruction sequence must not impose any requirements not | |
561 | required by the first instruction sequence. | |
0dd2d296 ILT |
562 | |
563 | These variant frags are then handled in functions called by the | |
564 | machine independent code. md_estimate_size_before_relax returns | |
565 | the final size of the frag. md_convert_frag sets up the final form | |
566 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
567 | one if needed. */ | |
568 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
569 | ((relax_substateT) \ | |
cc5703cd | 570 | (((old) << 23) \ |
0dd2d296 ILT |
571 | | ((new) << 16) \ |
572 | | (((reloc1) + 64) << 9) \ | |
573 | | (((reloc2) + 64) << 2) \ | |
574 | | ((reloc3) ? (1 << 1) : 0) \ | |
575 | | ((warn) ? 1 : 0))) | |
cc5703cd ILT |
576 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) |
577 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
483971bd KR |
578 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) |
579 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
0dd2d296 ILT |
580 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
581 | #define RELAX_WARN(i) ((i) & 1) | |
cc5703cd ILT |
582 | |
583 | /* For mips16 code, we use an entirely different form of relaxation. | |
584 | mips16 supports two versions of most instructions which take | |
585 | immediate values: a small one which takes some small value, and a | |
586 | larger one which takes a 16 bit value. Since branches also follow | |
587 | this pattern, relaxing these values is required. | |
588 | ||
589 | We can assemble both mips16 and normal MIPS code in a single | |
590 | object. Therefore, we need to support this type of relaxation at | |
591 | the same time that we support the relaxation described above. We | |
592 | use the high bit of the subtype field to distinguish these cases. | |
593 | ||
a677feeb ILT |
594 | The information we store for this type of relaxation is the |
595 | argument code found in the opcode file for this relocation, whether | |
596 | the user explicitly requested a small or extended form, and whether | |
597 | the relocation is in a jump or jal delay slot. That tells us the | |
598 | size of the value, and how it should be stored. We also store | |
599 | whether the fragment is considered to be extended or not. We also | |
600 | store whether this is known to be a branch to a different section, | |
601 | whether we have tried to relax this frag yet, and whether we have | |
602 | ever extended a PC relative fragment because of a shift count. */ | |
603 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
604 | (0x80000000 \ | |
605 | | ((type) & 0xff) \ | |
606 | | ((small) ? 0x100 : 0) \ | |
607 | | ((ext) ? 0x200 : 0) \ | |
608 | | ((dslot) ? 0x400 : 0) \ | |
609 | | ((jal_dslot) ? 0x800 : 0)) | |
cc5703cd ILT |
610 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) |
611 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
8728fa92 ILT |
612 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) |
613 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
a677feeb ILT |
614 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) |
615 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
616 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
617 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
618 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
619 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
620 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
621 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
7e656649 RH |
622 | /* start-sanitize-branchbug4011 */ |
623 | /* The 4011 core has a bug in it's branch processing that | |
624 | an be avoided if branches never branches (where branches | |
625 | are defined as those starting with 'b'). We do this here | |
626 | by insuring that labels are not directly on branch instructions, | |
627 | and if they are inserting a no-op between the label and the | |
628 | branch. */ | |
629 | static int mips_fix_4011_branch_bug = 0; | |
630 | /* end-sanitize-branchbug4011 */ | |
0dd2d296 | 631 | \f |
3d3c5039 ILT |
632 | /* Prototypes for static functions. */ |
633 | ||
634 | #ifdef __STDC__ | |
635 | #define internalError() \ | |
48401fcf | 636 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
3d3c5039 | 637 | #else |
48401fcf | 638 | #define internalError() as_fatal (_("MIPS internal Error")); |
3d3c5039 ILT |
639 | #endif |
640 | ||
cc5703cd ILT |
641 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
642 | ||
becfe05e | 643 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
cc5703cd | 644 | unsigned int reg, enum mips_regclass class)); |
fb251650 | 645 | static int reg_needs_delay PARAMS ((int)); |
3c83da8a | 646 | static void mips16_mark_labels PARAMS ((void)); |
0dd2d296 ILT |
647 | static void append_insn PARAMS ((char *place, |
648 | struct mips_cl_insn * ip, | |
670a50eb | 649 | expressionS * p, |
867a58b3 ILT |
650 | bfd_reloc_code_real_type r, |
651 | boolean)); | |
4a1cb507 | 652 | static void mips_no_prev_insn PARAMS ((int)); |
fbcfacb7 | 653 | static void mips_emit_delays PARAMS ((boolean)); |
c625fc23 | 654 | #ifdef USE_STDARG |
0dd2d296 | 655 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
656 | const char *name, const char *fmt, |
657 | ...)); | |
c625fc23 JSC |
658 | #else |
659 | static void macro_build (); | |
660 | #endif | |
cc5703cd ILT |
661 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, |
662 | const char *, const char *, | |
663 | va_list)); | |
0dd2d296 ILT |
664 | static void macro_build_lui PARAMS ((char *place, int *counter, |
665 | expressionS * ep, int regnum)); | |
6e8dda9c | 666 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 667 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 668 | expressionS *)); |
d8a1c247 | 669 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
0dd2d296 | 670 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); |
670a50eb | 671 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
cc5703cd | 672 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
673 | #ifdef LOSING_COMPILER |
674 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
675 | #endif | |
670a50eb | 676 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
cc5703cd | 677 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
15e69f98 ILT |
678 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, |
679 | boolean, boolean, unsigned long *, | |
680 | boolean *, unsigned short *)); | |
670a50eb ILT |
681 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); |
682 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 683 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 684 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 ILT |
685 | static void s_align PARAMS ((int)); |
686 | static void s_change_sec PARAMS ((int)); | |
687 | static void s_cons PARAMS ((int)); | |
3d3c5039 | 688 | static void s_float_cons PARAMS ((int)); |
c1444ec4 | 689 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
690 | static void s_option PARAMS ((int)); |
691 | static void s_mipsset PARAMS ((int)); | |
9226253a ILT |
692 | static void s_abicalls PARAMS ((int)); |
693 | static void s_cpload PARAMS ((int)); | |
694 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
695 | static void s_gpword PARAMS ((int)); |
696 | static void s_cpadd PARAMS ((int)); | |
ed3eb786 | 697 | static void s_insn PARAMS ((int)); |
3d3c5039 ILT |
698 | static void md_obj_begin PARAMS ((void)); |
699 | static void md_obj_end PARAMS ((void)); | |
700 | static long get_number PARAMS ((void)); | |
993b4e8d RU |
701 | static void s_mips_ent PARAMS ((int)); |
702 | static void s_mips_end PARAMS ((int)); | |
703 | static void s_mips_frame PARAMS ((int)); | |
704 | static void s_mips_mask PARAMS ((int)); | |
3c83da8a | 705 | static void s_mips_stab PARAMS ((int)); |
3c69baf9 | 706 | static void s_mips_weakext PARAMS ((int)); |
993b4e8d | 707 | static void s_file PARAMS ((int)); |
cc5703cd | 708 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); |
aa2e0460 | 709 | |
3c69baf9 | 710 | |
aa2e0460 | 711 | static int validate_mips_insn PARAMS ((const struct mips_opcode *)); |
3d3c5039 ILT |
712 | \f |
713 | /* Pseudo-op table. | |
714 | ||
715 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
716 | should be defined here, but are currently unsupported: .alias, | |
717 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
718 | ||
719 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
720 | specific to the type of debugging information being generated, and | |
721 | should be defined by the object format: .aent, .begin, .bend, | |
722 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
723 | .vreg. | |
724 | ||
725 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
726 | not MIPS CPU specific, but are also not specific to the object file | |
727 | format. This file is probably the best place to define them, but | |
728 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
3c69baf9 | 729 | .struct. */ |
3d3c5039 | 730 | |
739708fa | 731 | static const pseudo_typeS mips_pseudo_table[] = |
3d3c5039 | 732 | { |
670a50eb ILT |
733 | /* MIPS specific pseudo-ops. */ |
734 | {"option", s_option, 0}, | |
735 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
736 | {"rdata", s_change_sec, 'r'}, |
737 | {"sdata", s_change_sec, 's'}, | |
738 | {"livereg", s_ignore, 0}, | |
739708fa KR |
739 | {"abicalls", s_abicalls, 0}, |
740 | {"cpload", s_cpload, 0}, | |
741 | {"cprestore", s_cprestore, 0}, | |
742 | {"gpword", s_gpword, 0}, | |
743 | {"cpadd", s_cpadd, 0}, | |
ed3eb786 | 744 | {"insn", s_insn, 0}, |
3d3c5039 | 745 | |
670a50eb | 746 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 747 | chips. */ |
739708fa | 748 | {"asciiz", stringer, 1}, |
670a50eb ILT |
749 | {"bss", s_change_sec, 'b'}, |
750 | {"err", s_err, 0}, | |
751 | {"half", s_cons, 1}, | |
52aa70b5 | 752 | {"dword", s_cons, 3}, |
3c69baf9 | 753 | {"weakext", s_mips_weakext, 0}, |
3d3c5039 | 754 | |
670a50eb | 755 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 756 | here for one reason or another. */ |
670a50eb ILT |
757 | {"align", s_align, 0}, |
758 | {"byte", s_cons, 0}, | |
759 | {"data", s_change_sec, 'd'}, | |
becfe05e | 760 | {"double", s_float_cons, 'd'}, |
becfe05e | 761 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
762 | {"globl", s_mips_globl, 0}, |
763 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
764 | {"hword", s_cons, 1}, |
765 | {"int", s_cons, 2}, | |
766 | {"long", s_cons, 2}, | |
767 | {"octa", s_cons, 4}, | |
768 | {"quad", s_cons, 3}, | |
769 | {"short", s_cons, 1}, | |
770 | {"single", s_float_cons, 'f'}, | |
3c83da8a | 771 | {"stabn", s_mips_stab, 'n'}, |
670a50eb ILT |
772 | {"text", s_change_sec, 't'}, |
773 | {"word", s_cons, 2}, | |
739708fa KR |
774 | { 0 }, |
775 | }; | |
3d3c5039 | 776 | |
739708fa | 777 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { |
670a50eb | 778 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 779 | However, a.out doesn't support them, so we have versions here. */ |
993b4e8d | 780 | {"aent", s_mips_ent, 1}, |
9226253a | 781 | {"bgnb", s_ignore, 0}, |
993b4e8d | 782 | {"end", s_mips_end, 0}, |
9226253a | 783 | {"endb", s_ignore, 0}, |
993b4e8d | 784 | {"ent", s_mips_ent, 0}, |
670a50eb | 785 | {"file", s_file, 0}, |
993b4e8d RU |
786 | {"fmask", s_mips_mask, 'F'}, |
787 | {"frame", s_mips_frame, 0}, | |
670a50eb | 788 | {"loc", s_ignore, 0}, |
993b4e8d | 789 | {"mask", s_mips_mask, 'R'}, |
670a50eb | 790 | {"verstamp", s_ignore, 0}, |
739708fa KR |
791 | { 0 }, |
792 | }; | |
61420a20 | 793 | |
739708fa KR |
794 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
795 | ||
796 | void | |
797 | mips_pop_insert () | |
798 | { | |
799 | pop_insert (mips_pseudo_table); | |
800 | if (! ECOFF_DEBUGGING) | |
801 | pop_insert (mips_nonecoff_pseudo_table); | |
739708fa | 802 | } |
3d3c5039 | 803 | \f |
fbcfacb7 ILT |
804 | /* Symbols labelling the current insn. */ |
805 | ||
806 | struct insn_label_list | |
807 | { | |
808 | struct insn_label_list *next; | |
809 | symbolS *label; | |
810 | }; | |
811 | ||
812 | static struct insn_label_list *insn_labels; | |
813 | static struct insn_label_list *free_insn_labels; | |
814 | ||
815 | static void mips_clear_insn_labels PARAMS ((void)); | |
816 | ||
817 | static inline void | |
818 | mips_clear_insn_labels () | |
819 | { | |
820 | register struct insn_label_list **pl; | |
821 | ||
822 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
823 | ; | |
824 | *pl = insn_labels; | |
825 | insn_labels = NULL; | |
826 | } | |
827 | \f | |
3d3c5039 ILT |
828 | static char *expr_end; |
829 | ||
867a58b3 ILT |
830 | /* Expressions which appear in instructions. These are set by |
831 | mips_ip. */ | |
832 | ||
3d3c5039 ILT |
833 | static expressionS imm_expr; |
834 | static expressionS offset_expr; | |
867a58b3 ILT |
835 | |
836 | /* Relocs associated with imm_expr and offset_expr. */ | |
837 | ||
3d3c5039 ILT |
838 | static bfd_reloc_code_real_type imm_reloc; |
839 | static bfd_reloc_code_real_type offset_reloc; | |
840 | ||
867a58b3 ILT |
841 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ |
842 | ||
843 | static boolean imm_unmatched_hi; | |
844 | ||
8728fa92 ILT |
845 | /* These are set by mips16_ip if an explicit extension is used. */ |
846 | ||
847 | static boolean mips16_small, mips16_ext; | |
848 | ||
993b4e8d RU |
849 | #ifdef MIPS_STABS_ELF |
850 | /* The pdr segment for per procedure frame/regmask info */ | |
851 | ||
852 | static segT pdr_seg; | |
853 | #endif | |
854 | ||
3d3c5039 ILT |
855 | /* |
856 | * This function is called once, at assembler startup time. It should | |
857 | * set up all the tables, etc. that the MD part of the assembler will need. | |
858 | */ | |
859 | void | |
670a50eb | 860 | md_begin () |
3d3c5039 | 861 | { |
0dd2d296 | 862 | boolean ok = false; |
604633ae | 863 | register const char *retval = NULL; |
670a50eb | 864 | register unsigned int i = 0; |
1724c79e GRK |
865 | const char *cpu; |
866 | char *a = NULL; | |
aa2e0460 | 867 | int broken = 0; |
3d3c5039 | 868 | |
1724c79e GRK |
869 | cpu = TARGET_CPU; |
870 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
8358c818 | 871 | { |
1724c79e GRK |
872 | a = xmalloc (sizeof TARGET_CPU); |
873 | strcpy (a, TARGET_CPU); | |
874 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
875 | cpu = a; | |
876 | } | |
8c63448a | 877 | |
1724c79e GRK |
878 | if (mips_cpu < 0) |
879 | { | |
880 | /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is | |
881 | just the generic 'mips', in which case set mips_cpu based | |
882 | on the given ISA, if any. */ | |
8c63448a ILT |
883 | |
884 | if (strcmp (cpu, "mips") == 0) | |
1724c79e GRK |
885 | { |
886 | if (mips_opts.isa < 0) | |
887 | mips_cpu = 3000; | |
888 | ||
889 | else if (mips_opts.isa == 2) | |
890 | mips_cpu = 6000; | |
891 | ||
892 | else if (mips_opts.isa == 3) | |
893 | mips_cpu = 4000; | |
894 | ||
895 | else if (mips_opts.isa == 4) | |
896 | mips_cpu = 8000; | |
897 | ||
898 | else | |
899 | mips_cpu = 3000; | |
900 | } | |
901 | ||
5c6f5923 | 902 | else if (strcmp (cpu, "r3900") == 0 |
6fd819cf | 903 | || strcmp (cpu, "mipstx39") == 0 |
4e96260f JL |
904 | /* start-sanitize-tx19 */ |
905 | || strcmp (cpu, "r1900") == 0 | |
906 | || strcmp (cpu, "mipstx19") == 0 | |
907 | /* end-sanitize-tx19 */ | |
908 | ) | |
1724c79e GRK |
909 | mips_cpu = 3900; |
910 | ||
8c63448a ILT |
911 | else if (strcmp (cpu, "r6000") == 0 |
912 | || strcmp (cpu, "mips2") == 0) | |
1724c79e GRK |
913 | mips_cpu = 6000; |
914 | ||
8c63448a ILT |
915 | else if (strcmp (cpu, "mips64") == 0 |
916 | || strcmp (cpu, "r4000") == 0 | |
917 | || strcmp (cpu, "mips3") == 0) | |
1724c79e GRK |
918 | mips_cpu = 4000; |
919 | ||
8c63448a | 920 | else if (strcmp (cpu, "r4400") == 0) |
1724c79e GRK |
921 | mips_cpu = 4400; |
922 | ||
8c63448a ILT |
923 | else if (strcmp (cpu, "mips64orion") == 0 |
924 | || strcmp (cpu, "r4600") == 0) | |
1724c79e GRK |
925 | mips_cpu = 4600; |
926 | ||
b2b8c24e | 927 | else if (strcmp (cpu, "r4650") == 0) |
1724c79e GRK |
928 | mips_cpu = 4650; |
929 | ||
c625fc23 | 930 | else if (strcmp (cpu, "mips64vr4300") == 0) |
1724c79e GRK |
931 | mips_cpu = 4300; |
932 | ||
2d035a50 GRK |
933 | /* start-sanitize-vr4320 */ |
934 | else if (strcmp (cpu, "r4320") == 0 | |
935 | || strcmp (cpu, "mips64vr4320") == 0) | |
936 | mips_cpu = 4320; | |
937 | ||
938 | /* end-sanitize-vr4320 */ | |
e599ab16 | 939 | else if (strcmp (cpu, "mips64vr4100") == 0) |
1724c79e GRK |
940 | mips_cpu = 4100; |
941 | ||
e532b44c | 942 | else if (strcmp (cpu, "r4010") == 0) |
1724c79e GRK |
943 | mips_cpu = 4010; |
944 | ||
4ebda395 GRK |
945 | /* start-sanitize-tx49 */ |
946 | else if (strcmp (cpu, "mips64tx49") == 0) | |
1724c79e | 947 | mips_cpu = 4900; |
4ebda395 | 948 | /* end-sanitize-tx49 */ |
1724c79e | 949 | |
517078c1 ILT |
950 | else if (strcmp (cpu, "r5000") == 0 |
951 | || strcmp (cpu, "mips64vr5000") == 0) | |
1724c79e GRK |
952 | mips_cpu = 5000; |
953 | ||
6b34ac5a | 954 | /* start-sanitize-cygnus */ |
aa2e0460 | 955 | else if (strcmp (cpu, "r5400") == 0 |
b3ed1af3 KR |
956 | || strcmp (cpu, "mips64vr5400") == 0) |
957 | mips_cpu = 5400; | |
6b34ac5a | 958 | /* end-sanitize-cygnus */ |
1724c79e | 959 | |
276c2d7d GRK |
960 | /* start-sanitize-r5900 */ |
961 | else if (strcmp (cpu, "r5900") == 0 | |
1724c79e GRK |
962 | || strcmp (cpu, "mips64r5900") == 0) |
963 | mips_cpu = 5900; | |
276c2d7d | 964 | /* end-sanitize-r5900 */ |
1724c79e | 965 | |
d8a1c247 KR |
966 | else if (strcmp (cpu, "r8000") == 0 |
967 | || strcmp (cpu, "mips4") == 0) | |
1724c79e GRK |
968 | mips_cpu = 8000; |
969 | ||
d8a1c247 | 970 | else if (strcmp (cpu, "r10000") == 0) |
1724c79e GRK |
971 | mips_cpu = 10000; |
972 | ||
cc5703cd | 973 | else if (strcmp (cpu, "mips16") == 0) |
1724c79e GRK |
974 | mips_cpu = 0; /* FIXME */ |
975 | ||
8358c818 | 976 | else |
1724c79e GRK |
977 | mips_cpu = 3000; |
978 | } | |
8c63448a | 979 | |
1724c79e GRK |
980 | if (mips_opts.isa == -1) |
981 | { | |
982 | if (mips_cpu == 3000 | |
983 | || mips_cpu == 3900) | |
984 | mips_opts.isa = 1; | |
985 | ||
986 | else if (mips_cpu == 6000 | |
987 | || mips_cpu == 4010) | |
988 | mips_opts.isa = 2; | |
989 | ||
990 | else if (mips_cpu == 4000 | |
991 | || mips_cpu == 4100 | |
992 | || mips_cpu == 4400 | |
993 | || mips_cpu == 4300 | |
2d035a50 GRK |
994 | /* start-sanitize-vr4320 */ |
995 | || mips_cpu == 4320 | |
059a6388 | 996 | /* end-sanitize-vr4320 */ |
1724c79e GRK |
997 | || mips_cpu == 4600 |
998 | /* start-sanitize-tx49 */ | |
999 | || mips_cpu == 4900 | |
1000 | /* end-sanitize-tx49 */ | |
1001 | /* start-sanitize-r5900 */ | |
1002 | || mips_cpu == 5900 | |
1003 | /* end-sanitize-r5900 */ | |
1004 | || mips_cpu == 4650) | |
1005 | mips_opts.isa = 3; | |
1006 | ||
1007 | else if (mips_cpu == 5000 | |
6b34ac5a | 1008 | /* start-sanitize-cygnus */ |
1724c79e | 1009 | || mips_cpu == 5400 |
6b34ac5a | 1010 | /* end-sanitize-cygnus */ |
1724c79e GRK |
1011 | || mips_cpu == 8000 |
1012 | || mips_cpu == 10000) | |
1013 | mips_opts.isa = 4; | |
1014 | ||
1015 | else | |
1016 | mips_opts.isa = 1; | |
8358c818 ILT |
1017 | } |
1018 | ||
3c83da8a | 1019 | if (mips_opts.mips16 < 0) |
cc5703cd ILT |
1020 | { |
1021 | if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) | |
3c83da8a | 1022 | mips_opts.mips16 = 1; |
cc5703cd | 1023 | else |
3c83da8a | 1024 | mips_opts.mips16 = 0; |
cc5703cd ILT |
1025 | } |
1026 | ||
b2b8c24e | 1027 | if (mips_4650 < 0) |
1724c79e | 1028 | mips_4650 = (mips_cpu == 4650); |
b2b8c24e | 1029 | |
e532b44c | 1030 | if (mips_4010 < 0) |
1724c79e | 1031 | mips_4010 = (mips_cpu == 4010); |
e532b44c | 1032 | |
c625fc23 | 1033 | if (mips_4100 < 0) |
1724c79e | 1034 | mips_4100 = (mips_cpu == 4100); |
c625fc23 | 1035 | |
2d035a50 GRK |
1036 | /* start-sanitize-vr4320 */ |
1037 | if (mips_4320 < 0) | |
1038 | mips_4320 = (mips_cpu == 4320); | |
1039 | ||
1040 | /* end-sanitize-vr4320 */ | |
6b34ac5a | 1041 | /* start-sanitize-cygnus */ |
aa2e0460 | 1042 | if (mips_5400 < 0) |
1724c79e | 1043 | mips_5400 = (mips_cpu == 5400); |
6b34ac5a | 1044 | /* end-sanitize-cygnus */ |
1724c79e | 1045 | |
276c2d7d GRK |
1046 | /* start-sanitize-r5900 */ |
1047 | if (mips_5900 < 0) | |
1724c79e | 1048 | mips_5900 = (mips_cpu == 5900); |
aa2e0460 | 1049 | /* end-sanitize-r5900 */ |
1724c79e | 1050 | |
5c6f5923 | 1051 | if (mips_3900 < 0) |
1724c79e GRK |
1052 | mips_3900 = (mips_cpu == 3900); |
1053 | ||
42444087 GRK |
1054 | /* start-sanitize-tx49 */ |
1055 | if (mips_4900 < 0) | |
1056 | mips_4900 = (mips_cpu == 4900); | |
1724c79e | 1057 | |
42444087 | 1058 | /* end-sanitize-tx49 */ |
1724c79e GRK |
1059 | |
1060 | /* End of TARGET_CPU processing, get rid of malloced memory | |
1061 | if necessary. */ | |
1062 | cpu = NULL; | |
1063 | if (a != NULL) | |
1064 | { | |
1065 | free (a); | |
1066 | a = NULL; | |
1067 | } | |
1068 | ||
3c83da8a | 1069 | if (mips_opts.isa < 2 && mips_trap) |
48401fcf | 1070 | as_bad (_("trap exception not supported at ISA 1")); |
8ea7f4e8 | 1071 | |
9a1f3160 | 1072 | if (mips_cpu != 0 && mips_cpu != -1) |
97f99d11 | 1073 | { |
9a1f3160 JL |
1074 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_cpu); |
1075 | } | |
1076 | else | |
1077 | { | |
1078 | switch (mips_opts.isa) | |
1079 | { | |
1080 | case 1: | |
1081 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
1082 | break; | |
1083 | case 2: | |
1084 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
1085 | break; | |
1086 | case 3: | |
1087 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
1088 | break; | |
1089 | case 4: | |
1090 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
1091 | break; | |
1092 | } | |
97f99d11 | 1093 | } |
9a1f3160 | 1094 | |
97f99d11 | 1095 | if (! ok) |
48401fcf | 1096 | as_warn (_("Could not set architecture and machine")); |
97f99d11 | 1097 | |
3c83da8a | 1098 | file_mips_isa = mips_opts.isa; |
1051c97f | 1099 | |
13fe1379 ILT |
1100 | op_hash = hash_new (); |
1101 | ||
670a50eb ILT |
1102 | for (i = 0; i < NUMOPCODES;) |
1103 | { | |
1104 | const char *name = mips_opcodes[i].name; | |
1105 | ||
604633ae | 1106 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 1107 | if (retval != NULL) |
670a50eb | 1108 | { |
48401fcf | 1109 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), |
670a50eb | 1110 | mips_opcodes[i].name, retval); |
aa2e0460 | 1111 | /* Probably a memory allocation problem? Give up now. */ |
48401fcf | 1112 | as_fatal (_("Broken assembler. No assembly attempted.")); |
670a50eb ILT |
1113 | } |
1114 | do | |
1115 | { | |
aa2e0460 | 1116 | if (mips_opcodes[i].pinfo != INSN_MACRO) |
670a50eb | 1117 | { |
aa2e0460 KR |
1118 | if (!validate_mips_insn (&mips_opcodes[i])) |
1119 | broken = 1; | |
3d3c5039 | 1120 | } |
670a50eb ILT |
1121 | ++i; |
1122 | } | |
1123 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
1124 | } |
1125 | ||
cc5703cd ILT |
1126 | mips16_op_hash = hash_new (); |
1127 | ||
1128 | i = 0; | |
1129 | while (i < bfd_mips16_num_opcodes) | |
1130 | { | |
1131 | const char *name = mips16_opcodes[i].name; | |
1132 | ||
1133 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1134 | if (retval != NULL) | |
48401fcf | 1135 | as_fatal (_("internal: can't hash `%s': %s"), |
cc5703cd ILT |
1136 | mips16_opcodes[i].name, retval); |
1137 | do | |
1138 | { | |
1139 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1140 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1141 | != mips16_opcodes[i].match)) | |
aa2e0460 | 1142 | { |
48401fcf | 1143 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), |
aa2e0460 KR |
1144 | mips16_opcodes[i].name, mips16_opcodes[i].args); |
1145 | broken = 1; | |
1146 | } | |
cc5703cd ILT |
1147 | ++i; |
1148 | } | |
1149 | while (i < bfd_mips16_num_opcodes | |
1150 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1151 | } | |
1152 | ||
aa2e0460 | 1153 | if (broken) |
48401fcf | 1154 | as_fatal (_("Broken assembler. No assembly attempted.")); |
aa2e0460 | 1155 | |
ebf28372 ILT |
1156 | /* We add all the general register names to the symbol table. This |
1157 | helps us detect invalid uses of them. */ | |
1158 | for (i = 0; i < 32; i++) | |
1159 | { | |
1160 | char buf[5]; | |
1161 | ||
1162 | sprintf (buf, "$%d", i); | |
1163 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1164 | &zero_address_frag)); | |
1165 | } | |
1166 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
1167 | &zero_address_frag)); | |
1168 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1169 | &zero_address_frag)); | |
1170 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1171 | &zero_address_frag)); | |
1172 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1173 | &zero_address_frag)); | |
1174 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1175 | &zero_address_frag)); | |
1176 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1177 | &zero_address_frag)); | |
1178 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
1179 | &zero_address_frag)); | |
1180 | ||
4a1cb507 | 1181 | mips_no_prev_insn (false); |
becfe05e | 1182 | |
1aa6938e ILT |
1183 | mips_gprmask = 0; |
1184 | mips_cprmask[0] = 0; | |
1185 | mips_cprmask[1] = 0; | |
1186 | mips_cprmask[2] = 0; | |
1187 | mips_cprmask[3] = 0; | |
1188 | ||
8358c818 | 1189 | /* set the default alignment for the text section (2**2) */ |
f5e38044 | 1190 | record_alignment (text_section, 2); |
8358c818 | 1191 | |
1dc1e798 KR |
1192 | if (USE_GLOBAL_POINTER_OPT) |
1193 | bfd_set_gp_size (stdoutput, g_switch_value); | |
abdad6bc | 1194 | |
1dc1e798 KR |
1195 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1196 | { | |
08e17202 ILT |
1197 | /* On a native system, sections must be aligned to 16 byte |
1198 | boundaries. When configured for an embedded ELF target, we | |
1199 | don't bother. */ | |
1200 | if (strcmp (TARGET_OS, "elf") != 0) | |
1201 | { | |
1202 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1203 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1204 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1205 | } | |
1dc1e798 KR |
1206 | |
1207 | /* Create a .reginfo section for register masks and a .mdebug | |
1208 | section for debugging information. */ | |
1209 | { | |
1210 | segT seg; | |
1211 | subsegT subseg; | |
b3a64736 | 1212 | flagword flags; |
1dc1e798 KR |
1213 | segT sec; |
1214 | ||
1215 | seg = now_seg; | |
1216 | subseg = now_subseg; | |
1dc1e798 | 1217 | |
b3a64736 ILT |
1218 | /* The ABI says this section should be loaded so that the |
1219 | running program can access it. However, we don't load it | |
1220 | if we are configured for an embedded target */ | |
1221 | flags = SEC_READONLY | SEC_DATA; | |
1222 | if (strcmp (TARGET_OS, "elf") != 0) | |
1223 | flags |= SEC_ALLOC | SEC_LOAD; | |
1224 | ||
87178180 ILT |
1225 | if (! mips_64) |
1226 | { | |
1227 | sec = subseg_new (".reginfo", (subsegT) 0); | |
8358c818 | 1228 | |
b3a64736 ILT |
1229 | |
1230 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
87178180 ILT |
1231 | (void) bfd_set_section_alignment (stdoutput, sec, 2); |
1232 | ||
f2a663d3 | 1233 | #ifdef OBJ_ELF |
87178180 | 1234 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
1dc1e798 | 1235 | #endif |
87178180 ILT |
1236 | } |
1237 | else | |
1238 | { | |
1239 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1240 | .reginfo section. */ | |
1241 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
b3a64736 | 1242 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
87178180 ILT |
1243 | (void) bfd_set_section_alignment (stdoutput, sec, 3); |
1244 | ||
1245 | #ifdef OBJ_ELF | |
1246 | /* Set up the option header. */ | |
1247 | { | |
1248 | Elf_Internal_Options opthdr; | |
1249 | char *f; | |
1250 | ||
1251 | opthdr.kind = ODK_REGINFO; | |
1252 | opthdr.size = (sizeof (Elf_External_Options) | |
1253 | + sizeof (Elf64_External_RegInfo)); | |
1254 | opthdr.section = 0; | |
1255 | opthdr.info = 0; | |
1256 | f = frag_more (sizeof (Elf_External_Options)); | |
1257 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1258 | (Elf_External_Options *) f); | |
1259 | ||
1260 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1261 | } | |
1262 | #endif | |
1263 | } | |
f2a663d3 | 1264 | |
739708fa KR |
1265 | if (ECOFF_DEBUGGING) |
1266 | { | |
1267 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1268 | (void) bfd_set_section_flags (stdoutput, sec, | |
1269 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1270 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1271 | } | |
0dd2d296 | 1272 | |
993b4e8d RU |
1273 | #ifdef MIPS_STABS_ELF |
1274 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1275 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1276 | SEC_READONLY | SEC_RELOC | SEC_DEBUGGING); | |
1277 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1278 | #endif | |
1279 | ||
1dc1e798 KR |
1280 | subseg_set (seg, subseg); |
1281 | } | |
1282 | } | |
f2a663d3 | 1283 | |
739708fa KR |
1284 | if (! ECOFF_DEBUGGING) |
1285 | md_obj_begin (); | |
3d3c5039 ILT |
1286 | } |
1287 | ||
1288 | void | |
13fe1379 | 1289 | md_mips_end () |
3d3c5039 | 1290 | { |
739708fa KR |
1291 | if (! ECOFF_DEBUGGING) |
1292 | md_obj_end (); | |
3d3c5039 ILT |
1293 | } |
1294 | ||
1295 | void | |
670a50eb ILT |
1296 | md_assemble (str) |
1297 | char *str; | |
3d3c5039 | 1298 | { |
670a50eb | 1299 | struct mips_cl_insn insn; |
3d3c5039 | 1300 | |
5ac34ac3 | 1301 | imm_expr.X_op = O_absent; |
867a58b3 ILT |
1302 | imm_reloc = BFD_RELOC_UNUSED; |
1303 | imm_unmatched_hi = false; | |
5ac34ac3 | 1304 | offset_expr.X_op = O_absent; |
867a58b3 | 1305 | offset_reloc = BFD_RELOC_UNUSED; |
3d3c5039 | 1306 | |
3c83da8a | 1307 | if (mips_opts.mips16) |
cc5703cd ILT |
1308 | mips16_ip (str, &insn); |
1309 | else | |
efec4a28 | 1310 | { |
9218cee0 | 1311 | mips_ip (str, &insn); |
48401fcf | 1312 | DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
efec4a28 DP |
1313 | str, insn.insn_opcode)); |
1314 | } | |
cc5703cd | 1315 | |
670a50eb ILT |
1316 | if (insn_error) |
1317 | { | |
1318 | as_bad ("%s `%s'", insn_error, str); | |
1319 | return; | |
1320 | } | |
cc5703cd | 1321 | |
670a50eb ILT |
1322 | if (insn.insn_mo->pinfo == INSN_MACRO) |
1323 | { | |
3c83da8a | 1324 | if (mips_opts.mips16) |
cc5703cd ILT |
1325 | mips16_macro (&insn); |
1326 | else | |
1327 | macro (&insn); | |
3d3c5039 | 1328 | } |
670a50eb ILT |
1329 | else |
1330 | { | |
5ac34ac3 | 1331 | if (imm_expr.X_op != O_absent) |
867a58b3 ILT |
1332 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, |
1333 | imm_unmatched_hi); | |
5ac34ac3 | 1334 | else if (offset_expr.X_op != O_absent) |
867a58b3 | 1335 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); |
670a50eb | 1336 | else |
867a58b3 | 1337 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); |
3d3c5039 ILT |
1338 | } |
1339 | } | |
1340 | ||
cc5703cd ILT |
1341 | /* See whether instruction IP reads register REG. CLASS is the type |
1342 | of register. */ | |
becfe05e ILT |
1343 | |
1344 | static int | |
cc5703cd | 1345 | insn_uses_reg (ip, reg, class) |
becfe05e | 1346 | struct mips_cl_insn *ip; |
604633ae | 1347 | unsigned int reg; |
cc5703cd | 1348 | enum mips_regclass class; |
becfe05e | 1349 | { |
cc5703cd ILT |
1350 | if (class == MIPS16_REG) |
1351 | { | |
3c83da8a | 1352 | assert (mips_opts.mips16); |
cc5703cd ILT |
1353 | reg = mips16_to_32_reg_map[reg]; |
1354 | class = MIPS_GR_REG; | |
1355 | } | |
1356 | ||
becfe05e | 1357 | /* Don't report on general register 0, since it never changes. */ |
cc5703cd | 1358 | if (class == MIPS_GR_REG && reg == 0) |
becfe05e ILT |
1359 | return 0; |
1360 | ||
cc5703cd | 1361 | if (class == MIPS_FP_REG) |
becfe05e | 1362 | { |
3c83da8a | 1363 | assert (! mips_opts.mips16); |
becfe05e ILT |
1364 | /* If we are called with either $f0 or $f1, we must check $f0. |
1365 | This is not optimal, because it will introduce an unnecessary | |
1366 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1367 | need to distinguish reading both $f0 and $f1 or just one of | |
1368 | them. Note that we don't have to check the other way, | |
1369 | because there is no instruction that sets both $f0 and $f1 | |
1370 | and requires a delay. */ | |
1371 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
68952421 | 1372 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) |
604633ae | 1373 | == (reg &~ (unsigned) 1))) |
becfe05e ILT |
1374 | return 1; |
1375 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
68952421 | 1376 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) |
604633ae | 1377 | == (reg &~ (unsigned) 1))) |
becfe05e ILT |
1378 | return 1; |
1379 | } | |
3c83da8a | 1380 | else if (! mips_opts.mips16) |
becfe05e ILT |
1381 | { |
1382 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1383 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1384 | return 1; | |
1385 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1386 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1387 | return 1; | |
1388 | } | |
cc5703cd ILT |
1389 | else |
1390 | { | |
1391 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
23ac3ca1 ILT |
1392 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) |
1393 | & MIPS16OP_MASK_RX)] | |
1394 | == reg)) | |
cc5703cd ILT |
1395 | return 1; |
1396 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
23ac3ca1 ILT |
1397 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) |
1398 | & MIPS16OP_MASK_RY)] | |
1399 | == reg)) | |
cc5703cd ILT |
1400 | return 1; |
1401 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
23ac3ca1 ILT |
1402 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) |
1403 | & MIPS16OP_MASK_MOVE32Z)] | |
1404 | == reg)) | |
cc5703cd ILT |
1405 | return 1; |
1406 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1407 | return 1; | |
1408 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1409 | return 1; | |
1410 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1411 | return 1; | |
1412 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1413 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1414 | & MIPS16OP_MASK_REGR32) == reg) | |
1415 | return 1; | |
1416 | } | |
becfe05e ILT |
1417 | |
1418 | return 0; | |
1419 | } | |
1420 | ||
fb251650 ILT |
1421 | /* This function returns true if modifying a register requires a |
1422 | delay. */ | |
1423 | ||
1424 | static int | |
1425 | reg_needs_delay (reg) | |
1426 | int reg; | |
1427 | { | |
1428 | unsigned long prev_pinfo; | |
1429 | ||
1430 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
3c83da8a JW |
1431 | if (! mips_opts.noreorder |
1432 | && mips_opts.isa < 4 | |
fb251650 | 1433 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
5c6f5923 | 1434 | || (! gpr_interlocks |
fb251650 ILT |
1435 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) |
1436 | { | |
1437 | /* A load from a coprocessor or from memory. All load | |
1438 | delays delay the use of general register rt for one | |
1439 | instruction on the r3000. The r6000 and r4000 use | |
1440 | interlocks. */ | |
efec4a28 | 1441 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
1442 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1443 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1444 | return 1; | |
1445 | } | |
1446 | ||
1447 | return 0; | |
1448 | } | |
1449 | ||
3c83da8a JW |
1450 | /* Mark instruction labels in mips16 mode. This permits the linker to |
1451 | handle them specially, such as generating jalx instructions when | |
1452 | needed. We also make them odd for the duration of the assembly, in | |
1453 | order to generate the right sort of code. We will make them even | |
1454 | in the adjust_symtab routine, while leaving them marked. This is | |
1455 | convenient for the debugger and the disassembler. The linker knows | |
1456 | to make them odd again. */ | |
1457 | ||
1458 | static void | |
1459 | mips16_mark_labels () | |
1460 | { | |
1461 | if (mips_opts.mips16) | |
1462 | { | |
1463 | struct insn_label_list *l; | |
1464 | ||
1465 | for (l = insn_labels; l != NULL; l = l->next) | |
1466 | { | |
68952421 | 1467 | #ifdef OBJ_ELF |
3c83da8a JW |
1468 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1469 | S_SET_OTHER (l->label, STO_MIPS16); | |
1470 | #endif | |
1471 | if ((l->label->sy_value.X_add_number & 1) == 0) | |
1472 | ++l->label->sy_value.X_add_number; | |
1473 | } | |
1474 | } | |
1475 | } | |
1476 | ||
0dd2d296 ILT |
1477 | /* Output an instruction. PLACE is where to put the instruction; if |
1478 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1479 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1480 | used with RELOC_TYPE. */ | |
3d3c5039 | 1481 | |
3d3c5039 | 1482 | static void |
867a58b3 | 1483 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) |
0dd2d296 | 1484 | char *place; |
670a50eb ILT |
1485 | struct mips_cl_insn *ip; |
1486 | expressionS *address_expr; | |
1487 | bfd_reloc_code_real_type reloc_type; | |
867a58b3 | 1488 | boolean unmatched_hi; |
3d3c5039 | 1489 | { |
1aa6938e | 1490 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 1491 | char *f; |
becfe05e ILT |
1492 | fixS *fixp; |
1493 | int nops = 0; | |
7e656649 RH |
1494 | /* start-sanitize-branchbug4011 */ |
1495 | int label_nop = 0; /* True if a no-op needs to appear between | |
1496 | the current insn and the current labels */ | |
1497 | /* end-sanitize-branchbug4011 */ | |
3d3c5039 | 1498 | |
3c83da8a JW |
1499 | /* Mark instruction labels in mips16 mode. */ |
1500 | if (mips_opts.mips16) | |
1501 | mips16_mark_labels (); | |
fbcfacb7 | 1502 | |
1aa6938e ILT |
1503 | prev_pinfo = prev_insn.insn_mo->pinfo; |
1504 | pinfo = ip->insn_mo->pinfo; | |
1505 | ||
3c83da8a | 1506 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) |
becfe05e | 1507 | { |
4a1cb507 ILT |
1508 | int prev_prev_nop; |
1509 | ||
becfe05e | 1510 | /* If the previous insn required any delay slots, see if we need |
8358c818 | 1511 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 1512 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
1513 | (1) a load from memory delay |
1514 | (2) a load from a coprocessor delay | |
1515 | (3) an unconditional branch delay | |
1516 | (4) a conditional branch delay | |
1517 | (5) a move to coprocessor register delay | |
1518 | (6) a load coprocessor register from memory delay | |
1519 | (7) a coprocessor condition code delay | |
1520 | (8) a HI/LO special register delay | |
becfe05e ILT |
1521 | |
1522 | There are a lot of optimizations we could do that we don't. | |
1523 | In particular, we do not, in general, reorder instructions. | |
1524 | If you use gcc with optimization, it will reorder | |
1525 | instructions and generally do much more optimization then we | |
1526 | do here; repeating all that work in the assembler would only | |
1527 | benefit hand written assembly code, and does not seem worth | |
1528 | it. */ | |
1529 | ||
1530 | /* This is how a NOP is emitted. */ | |
cc5703cd | 1531 | #define emit_nop() \ |
3c83da8a | 1532 | (mips_opts.mips16 \ |
cc5703cd ILT |
1533 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ |
1534 | : md_number_to_chars (frag_more (4), 0, 4)) | |
becfe05e ILT |
1535 | |
1536 | /* The previous insn might require a delay slot, depending upon | |
1537 | the contents of the current insn. */ | |
3c83da8a JW |
1538 | if (! mips_opts.mips16 |
1539 | && mips_opts.isa < 4 | |
5af96dce ILT |
1540 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1541 | && ! cop_interlocks) | |
5c6f5923 | 1542 | || (! gpr_interlocks |
d8a1c247 | 1543 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) |
8358c818 ILT |
1544 | { |
1545 | /* A load from a coprocessor or from memory. All load | |
1546 | delays delay the use of general register rt for one | |
1547 | instruction on the r3000. The r6000 and r4000 use | |
1548 | interlocks. */ | |
efec4a28 | 1549 | /* Itbl support may require additional care here. */ |
1aa6938e | 1550 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
1551 | if (mips_optimize == 0 |
1552 | || insn_uses_reg (ip, | |
1553 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1554 | & OP_MASK_RT), | |
cc5703cd | 1555 | MIPS_GR_REG)) |
becfe05e ILT |
1556 | ++nops; |
1557 | } | |
3c83da8a JW |
1558 | else if (! mips_opts.mips16 |
1559 | && mips_opts.isa < 4 | |
5af96dce ILT |
1560 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
1561 | && ! cop_interlocks) | |
3c83da8a | 1562 | || (mips_opts.isa < 2 |
d8a1c247 | 1563 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
becfe05e ILT |
1564 | { |
1565 | /* A generic coprocessor delay. The previous instruction | |
1566 | modified a coprocessor general or control register. If | |
1567 | it modified a control register, we need to avoid any | |
1568 | coprocessor instruction (this is probably not always | |
1569 | required, but it sometimes is). If it modified a general | |
1570 | register, we avoid using that register. | |
1571 | ||
8358c818 ILT |
1572 | On the r6000 and r4000 loading a coprocessor register |
1573 | from memory is interlocked, and does not require a delay. | |
1574 | ||
becfe05e ILT |
1575 | This case is not handled very well. There is no special |
1576 | knowledge of CP0 handling, and the coprocessors other | |
1577 | than the floating point unit are not distinguished at | |
1578 | all. */ | |
efec4a28 DP |
1579 | /* Itbl support may require additional care here. FIXME! |
1580 | Need to modify this to include knowledge about | |
1581 | user specified delays! */ | |
1aa6938e | 1582 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 1583 | { |
0aa07269 ILT |
1584 | if (mips_optimize == 0 |
1585 | || insn_uses_reg (ip, | |
8358c818 ILT |
1586 | ((prev_insn.insn_opcode >> OP_SH_FT) |
1587 | & OP_MASK_FT), | |
cc5703cd | 1588 | MIPS_FP_REG)) |
becfe05e ILT |
1589 | ++nops; |
1590 | } | |
1aa6938e | 1591 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 1592 | { |
0aa07269 ILT |
1593 | if (mips_optimize == 0 |
1594 | || insn_uses_reg (ip, | |
8358c818 ILT |
1595 | ((prev_insn.insn_opcode >> OP_SH_FS) |
1596 | & OP_MASK_FS), | |
cc5703cd | 1597 | MIPS_FP_REG)) |
becfe05e ILT |
1598 | ++nops; |
1599 | } | |
1600 | else | |
1601 | { | |
1602 | /* We don't know exactly what the previous instruction | |
1603 | does. If the current instruction uses a coprocessor | |
1604 | register, we must insert a NOP. If previous | |
1605 | instruction may set the condition codes, and the | |
1606 | current instruction uses them, we must insert two | |
1607 | NOPS. */ | |
efec4a28 | 1608 | /* Itbl support may require additional care here. */ |
0aa07269 | 1609 | if (mips_optimize == 0 |
1aa6938e ILT |
1610 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
1611 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 1612 | nops += 2; |
1aa6938e | 1613 | else if (pinfo & INSN_COP) |
becfe05e ILT |
1614 | ++nops; |
1615 | } | |
1616 | } | |
3c83da8a JW |
1617 | else if (! mips_opts.mips16 |
1618 | && mips_opts.isa < 4 | |
344a8d61 JSC |
1619 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1620 | && ! cop_interlocks) | |
becfe05e ILT |
1621 | { |
1622 | /* The previous instruction sets the coprocessor condition | |
1623 | codes, but does not require a general coprocessor delay | |
1624 | (this means it is a floating point comparison | |
1625 | instruction). If this instruction uses the condition | |
1626 | codes, we need to insert a single NOP. */ | |
efec4a28 | 1627 | /* Itbl support may require additional care here. */ |
0aa07269 | 1628 | if (mips_optimize == 0 |
1aa6938e | 1629 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1630 | ++nops; |
1631 | } | |
1aa6938e | 1632 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
1633 | { |
1634 | /* The previous instruction reads the LO register; if the | |
1635 | current instruction writes to the LO register, we must | |
517078c1 | 1636 | insert two NOPS. Some newer processors have interlocks. */ |
5c6f5923 | 1637 | if (! hilo_interlocks |
b2b8c24e ILT |
1638 | && (mips_optimize == 0 |
1639 | || (pinfo & INSN_WRITE_LO))) | |
becfe05e ILT |
1640 | nops += 2; |
1641 | } | |
1642 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1643 | { | |
1644 | /* The previous instruction reads the HI register; if the | |
1645 | current instruction writes to the HI register, we must | |
517078c1 | 1646 | insert a NOP. Some newer processors have interlocks. */ |
5c6f5923 | 1647 | if (! hilo_interlocks |
b2b8c24e ILT |
1648 | && (mips_optimize == 0 |
1649 | || (pinfo & INSN_WRITE_HI))) | |
becfe05e ILT |
1650 | nops += 2; |
1651 | } | |
1652 | ||
4a1cb507 ILT |
1653 | /* If the previous instruction was in a noreorder section, then |
1654 | we don't want to insert the nop after all. */ | |
efec4a28 | 1655 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
1656 | if (prev_insn_unreordered) |
1657 | nops = 0; | |
1658 | ||
becfe05e ILT |
1659 | /* There are two cases which require two intervening |
1660 | instructions: 1) setting the condition codes using a move to | |
1661 | coprocessor instruction which requires a general coprocessor | |
1662 | delay and then reading the condition codes 2) reading the HI | |
517078c1 ILT |
1663 | or LO register and then writing to it (except on processors |
1664 | which have interlocks). If we are not already emitting a NOP | |
1665 | instruction, we must check for these cases compared to the | |
1666 | instruction previous to the previous instruction. */ | |
3c83da8a JW |
1667 | if ((! mips_opts.mips16 |
1668 | && mips_opts.isa < 4 | |
4a1cb507 ILT |
1669 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1670 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1671 | && (pinfo & INSN_READ_COND_CODE) | |
1672 | && ! cop_interlocks) | |
1673 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1674 | && (pinfo & INSN_WRITE_LO) | |
5c6f5923 | 1675 | && ! hilo_interlocks) |
4a1cb507 ILT |
1676 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1677 | && (pinfo & INSN_WRITE_HI) | |
5c6f5923 | 1678 | && ! hilo_interlocks)) |
4a1cb507 ILT |
1679 | prev_prev_nop = 1; |
1680 | else | |
1681 | prev_prev_nop = 0; | |
1682 | ||
1683 | if (prev_prev_insn_unreordered) | |
1684 | prev_prev_nop = 0; | |
1685 | ||
1686 | if (prev_prev_nop && nops == 0) | |
becfe05e ILT |
1687 | ++nops; |
1688 | ||
0dd2d296 ILT |
1689 | /* If we are being given a nop instruction, don't bother with |
1690 | one of the nops we would otherwise output. This will only | |
1691 | happen when a nop instruction is used with mips_optimize set | |
1692 | to 0. */ | |
4a1cb507 | 1693 | if (nops > 0 |
3c83da8a JW |
1694 | && ! mips_opts.noreorder |
1695 | && ip->insn_opcode == (mips_opts.mips16 ? 0x6500 : 0)) | |
0dd2d296 ILT |
1696 | --nops; |
1697 | ||
7e656649 RH |
1698 | /* start-sanitize-branchbug4011 */ |
1699 | /* If we have a label on a branch insn, we need at least one no-op | |
1700 | between the label and the branch. The pinfo flags in this test | |
1701 | must cover all the kinds of branches. */ | |
1702 | if (mips_fix_4011_branch_bug | |
1703 | && insn_labels != NULL | |
1704 | && (ip->insn_mo->pinfo | |
1705 | & (INSN_UNCOND_BRANCH_DELAY | |
1706 | |INSN_COND_BRANCH_DELAY | |
1707 | |INSN_COND_BRANCH_LIKELY))) | |
1708 | { | |
1709 | label_nop = 1; | |
1710 | ||
1711 | /* Make sure we've got at least one nop. */ | |
1712 | if (nops == 0) | |
1713 | nops = 1; | |
1714 | } | |
1715 | ||
1716 | /* end-sanitize-branchbug4011 */ | |
becfe05e | 1717 | /* Now emit the right number of NOP instructions. */ |
3c83da8a | 1718 | if (nops > 0 && ! mips_opts.noreorder) |
becfe05e | 1719 | { |
5af96dce ILT |
1720 | fragS *old_frag; |
1721 | unsigned long old_frag_offset; | |
8c63448a | 1722 | int i; |
fbcfacb7 | 1723 | struct insn_label_list *l; |
8c63448a | 1724 | |
5af96dce ILT |
1725 | old_frag = frag_now; |
1726 | old_frag_offset = frag_now_fix (); | |
1727 | ||
7e656649 RH |
1728 | /* start-sanitize-branchbug4011 */ |
1729 | /* Emit the nops that should be before the label. */ | |
1730 | if (label_nop) | |
1731 | nops -= 1; | |
1732 | ||
1733 | /* end-sanitize-branchbug4011 */ | |
8c63448a | 1734 | for (i = 0; i < nops; i++) |
becfe05e | 1735 | emit_nop (); |
5af96dce | 1736 | |
af255ca0 | 1737 | if (listing) |
546f5536 ILT |
1738 | { |
1739 | listing_prev_line (); | |
1740 | /* We may be at the start of a variant frag. In case we | |
1741 | are, make sure there is enough space for the frag | |
1742 | after the frags created by listing_prev_line. The | |
1743 | argument to frag_grow here must be at least as large | |
1744 | as the argument to all other calls to frag_grow in | |
1745 | this file. We don't have to worry about being in the | |
1746 | middle of a variant frag, because the variants insert | |
1747 | all needed nop instructions themselves. */ | |
1748 | frag_grow (40); | |
1749 | } | |
5af96dce | 1750 | |
fbcfacb7 | 1751 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 1752 | { |
fbcfacb7 ILT |
1753 | assert (S_GET_SEGMENT (l->label) == now_seg); |
1754 | l->label->sy_frag = frag_now; | |
1755 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
1756 | /* mips16 text labels are stored as odd. */ | |
3c83da8a | 1757 | if (mips_opts.mips16) |
fbcfacb7 | 1758 | ++l->label->sy_value.X_add_number; |
becfe05e | 1759 | } |
5af96dce ILT |
1760 | |
1761 | #ifndef NO_ECOFF_DEBUGGING | |
1762 | if (ECOFF_DEBUGGING) | |
1763 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1764 | #endif | |
7e656649 RH |
1765 | /* start-sanitize-branchbug4011 */ |
1766 | if (label_nop) | |
1767 | { | |
1768 | /* Emit the nop after the label, and return the | |
1769 | nop count to it's proper value. */ | |
1770 | emit_nop (); | |
1771 | nops += 1; | |
1772 | } | |
1773 | /* end-sanitize-branchbug4011 */ | |
becfe05e | 1774 | } |
4a1cb507 ILT |
1775 | else if (prev_nop_frag != NULL) |
1776 | { | |
1777 | /* We have a frag holding nops we may be able to remove. If | |
1778 | we don't need any nops, we can decrease the size of | |
1779 | prev_nop_frag by the size of one instruction. If we do | |
1780 | need some nops, we count them in prev_nops_required. */ | |
1781 | if (prev_nop_frag_since == 0) | |
1782 | { | |
1783 | if (nops == 0) | |
1784 | { | |
3c83da8a | 1785 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; |
4a1cb507 ILT |
1786 | --prev_nop_frag_holds; |
1787 | } | |
1788 | else | |
1789 | prev_nop_frag_required += nops; | |
1790 | } | |
1791 | else | |
1792 | { | |
1793 | if (prev_prev_nop == 0) | |
1794 | { | |
3c83da8a | 1795 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; |
4a1cb507 ILT |
1796 | --prev_nop_frag_holds; |
1797 | } | |
1798 | else | |
1799 | ++prev_nop_frag_required; | |
1800 | } | |
1801 | ||
1802 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1803 | prev_nop_frag = NULL; | |
1804 | ||
1805 | ++prev_nop_frag_since; | |
1806 | ||
1807 | /* Sanity check: by the time we reach the second instruction | |
1808 | after prev_nop_frag, we should have used up all the nops | |
1809 | one way or another. */ | |
1810 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1811 | } | |
becfe05e | 1812 | } |
4a1cb507 | 1813 | |
cc5703cd ILT |
1814 | if (reloc_type > BFD_RELOC_UNUSED) |
1815 | { | |
1816 | /* We need to set up a variant frag. */ | |
3c83da8a | 1817 | assert (mips_opts.mips16 && address_expr != NULL); |
cc5703cd | 1818 | f = frag_var (rs_machine_dependent, 4, 0, |
8728fa92 | 1819 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, |
a677feeb ILT |
1820 | mips16_small, mips16_ext, |
1821 | (prev_pinfo | |
1822 | & INSN_UNCOND_BRANCH_DELAY), | |
1823 | (prev_insn_reloc_type | |
1824 | == BFD_RELOC_MIPS16_JMP)), | |
f59fb6ca | 1825 | make_expr_symbol (address_expr), (offsetT) 0, |
cc5703cd ILT |
1826 | (char *) NULL); |
1827 | } | |
1828 | else if (place != NULL) | |
0dd2d296 | 1829 | f = place; |
3c83da8a JW |
1830 | else if (mips_opts.mips16 |
1831 | && ! ip->use_extend | |
1832 | && reloc_type != BFD_RELOC_MIPS16_JMP) | |
08e17202 ILT |
1833 | { |
1834 | /* Make sure there is enough room to swap this instruction with | |
1835 | a following jump instruction. */ | |
1836 | frag_grow (6); | |
1837 | f = frag_more (2); | |
1838 | } | |
cc5703cd | 1839 | else |
035936da | 1840 | { |
3c83da8a JW |
1841 | if (mips_opts.mips16 |
1842 | && mips_opts.noreorder | |
035936da | 1843 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) |
48401fcf | 1844 | as_warn (_("extended instruction in delay slot")); |
035936da ILT |
1845 | |
1846 | f = frag_more (4); | |
1847 | } | |
1848 | ||
becfe05e | 1849 | fixp = NULL; |
cc5703cd | 1850 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) |
670a50eb | 1851 | { |
5ac34ac3 | 1852 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
1853 | { |
1854 | switch (reloc_type) | |
1855 | { | |
3d3c5039 | 1856 | case BFD_RELOC_32: |
670a50eb ILT |
1857 | ip->insn_opcode |= address_expr->X_add_number; |
1858 | break; | |
3d3c5039 ILT |
1859 | |
1860 | case BFD_RELOC_LO16: | |
670a50eb ILT |
1861 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
1862 | break; | |
3d3c5039 ILT |
1863 | |
1864 | case BFD_RELOC_MIPS_JMP: | |
39bb58e0 | 1865 | if ((address_expr->X_add_number & 3) != 0) |
48401fcf | 1866 | as_bad (_("jump to misaligned address (0x%lx)"), |
39bb58e0 | 1867 | (unsigned long) address_expr->X_add_number); |
5e1e8f23 ILT |
1868 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
1869 | break; | |
1870 | ||
cc5703cd | 1871 | case BFD_RELOC_MIPS16_JMP: |
39bb58e0 | 1872 | if ((address_expr->X_add_number & 3) != 0) |
48401fcf | 1873 | as_bad (_("jump to misaligned address (0x%lx)"), |
39bb58e0 | 1874 | (unsigned long) address_expr->X_add_number); |
cc5703cd ILT |
1875 | ip->insn_opcode |= |
1876 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1877 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1878 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1879 | break; | |
1880 | ||
3c69baf9 | 1881 | /* start-sanitize-r5900 */ |
0bc0e337 JL |
1882 | case BFD_RELOC_MIPS15_S3: |
1883 | ip->insn_opcode |= ((imm_expr.X_add_number & 0x7fff) >> 3) << 6; | |
1884 | break; | |
3c69baf9 | 1885 | /* end-sanitize-r5900 */ |
0bc0e337 | 1886 | |
3d3c5039 | 1887 | case BFD_RELOC_16_PCREL_S2: |
670a50eb | 1888 | goto need_reloc; |
3d3c5039 ILT |
1889 | |
1890 | default: | |
670a50eb | 1891 | internalError (); |
3d3c5039 | 1892 | } |
670a50eb ILT |
1893 | } |
1894 | else | |
1895 | { | |
3d3c5039 | 1896 | need_reloc: |
0dd2d296 ILT |
1897 | /* Don't generate a reloc if we are writing into a variant |
1898 | frag. */ | |
1899 | if (place == NULL) | |
867a58b3 ILT |
1900 | { |
1901 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1902 | address_expr, | |
1903 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1904 | reloc_type); | |
1905 | if (unmatched_hi) | |
1906 | { | |
1907 | struct mips_hi_fixup *hi_fixup; | |
1908 | ||
1909 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1910 | hi_fixup = ((struct mips_hi_fixup *) | |
1911 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1912 | hi_fixup->fixp = fixp; | |
1913 | hi_fixup->seg = now_seg; | |
1914 | hi_fixup->next = mips_hi_fixup_list; | |
1915 | mips_hi_fixup_list = hi_fixup; | |
1916 | } | |
1917 | } | |
3d3c5039 ILT |
1918 | } |
1919 | } | |
becfe05e | 1920 | |
3c83da8a | 1921 | if (! mips_opts.mips16) |
cc5703cd | 1922 | md_number_to_chars (f, ip->insn_opcode, 4); |
16262668 ILT |
1923 | else if (reloc_type == BFD_RELOC_MIPS16_JMP) |
1924 | { | |
1925 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
1926 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
1927 | } | |
cc5703cd ILT |
1928 | else |
1929 | { | |
1930 | if (ip->use_extend) | |
1931 | { | |
1932 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1933 | f += 2; | |
1934 | } | |
1935 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1936 | } | |
670a50eb | 1937 | |
1aa6938e | 1938 | /* Update the register mask information. */ |
3c83da8a | 1939 | if (! mips_opts.mips16) |
cc5703cd ILT |
1940 | { |
1941 | if (pinfo & INSN_WRITE_GPR_D) | |
1942 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1943 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1944 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1945 | if (pinfo & INSN_READ_GPR_S) | |
1946 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1947 | if (pinfo & INSN_WRITE_GPR_31) | |
1948 | mips_gprmask |= 1 << 31; | |
1949 | if (pinfo & INSN_WRITE_FPR_D) | |
1950 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1951 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1952 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1953 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1954 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1955 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1956 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1957 | if (pinfo & INSN_COP) | |
1958 | { | |
efec4a28 DP |
1959 | /* We don't keep enough information to sort these cases out. |
1960 | The itbl support does keep this information however, although | |
1961 | we currently don't support itbl fprmats as part of the cop | |
1962 | instruction. May want to add this support in the future. */ | |
cc5703cd ILT |
1963 | } |
1964 | /* Never set the bit for $0, which is always zero. */ | |
1965 | mips_gprmask &=~ 1 << 0; | |
1966 | } | |
1967 | else | |
1aa6938e | 1968 | { |
cc5703cd ILT |
1969 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) |
1970 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1971 | & MIPS16OP_MASK_RX); | |
1972 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1973 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1974 | & MIPS16OP_MASK_RY); | |
1975 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1976 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1977 | & MIPS16OP_MASK_RZ); | |
1978 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1979 | mips_gprmask |= 1 << TREG; | |
1980 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1981 | mips_gprmask |= 1 << SP; | |
1982 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1983 | mips_gprmask |= 1 << RA; | |
1984 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1985 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1986 | if (pinfo & MIPS16_INSN_READ_Z) | |
1987 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1988 | & MIPS16OP_MASK_MOVE32Z); | |
1989 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1990 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1991 | & MIPS16OP_MASK_REGR32); | |
1aa6938e | 1992 | } |
1aa6938e | 1993 | |
3c83da8a | 1994 | if (place == NULL && ! mips_opts.noreorder) |
670a50eb | 1995 | { |
becfe05e ILT |
1996 | /* Filling the branch delay slot is more complex. We try to |
1997 | switch the branch with the previous instruction, which we can | |
1998 | do if the previous instruction does not set up a condition | |
1999 | that the branch tests and if the branch is not itself the | |
2000 | target of any branch. */ | |
1aa6938e ILT |
2001 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
2002 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 2003 | { |
0aa07269 | 2004 | if (mips_optimize < 2 |
19ed8960 ILT |
2005 | /* If we have seen .set volatile or .set nomove, don't |
2006 | optimize. */ | |
3c83da8a | 2007 | || mips_opts.nomove != 0 |
4e95866e ILT |
2008 | /* If we had to emit any NOP instructions, then we |
2009 | already know we can not swap. */ | |
2010 | || nops != 0 | |
becfe05e ILT |
2011 | /* If we don't even know the previous insn, we can not |
2012 | swap. */ | |
2013 | || ! prev_insn_valid | |
2014 | /* If the previous insn is already in a branch delay | |
2015 | slot, then we can not swap. */ | |
2016 | || prev_insn_is_delay_slot | |
7e656649 RH |
2017 | /* start-sanitize-branchbug4011 */ |
2018 | /* We can't swap the branch back to a previous label */ | |
2019 | || (mips_fix_4011_branch_bug && prev_insn_labels) | |
2020 | /* end-sanitize-branchbug4011 */ | |
4e95866e ILT |
2021 | /* If the previous previous insn was in a .set |
2022 | noreorder, we can't swap. Actually, the MIPS | |
2023 | assembler will swap in this situation. However, gcc | |
2024 | configured -with-gnu-as will generate code like | |
2025 | .set noreorder | |
2026 | lw $4,XXX | |
2027 | .set reorder | |
2028 | INSN | |
2029 | bne $4,$0,foo | |
2030 | in which we can not swap the bne and INSN. If gcc is | |
2031 | not configured -with-gnu-as, it does not output the | |
2032 | .set pseudo-ops. We don't have to check | |
2033 | prev_insn_unreordered, because prev_insn_valid will | |
2034 | be 0 in that case. We don't want to use | |
2035 | prev_prev_insn_valid, because we do want to be able | |
2036 | to swap at the start of a function. */ | |
2037 | || prev_prev_insn_unreordered | |
becfe05e ILT |
2038 | /* If the branch is itself the target of a branch, we |
2039 | can not swap. We cheat on this; all we check for is | |
2040 | whether there is a label on this instruction. If | |
2041 | there are any branches to anything other than a | |
2042 | label, users must use .set noreorder. */ | |
fbcfacb7 | 2043 | || insn_labels != NULL |
777ad64d | 2044 | /* If the previous instruction is in a variant frag, we |
cc5703cd ILT |
2045 | can not do the swap. This does not apply to the |
2046 | mips16, which uses variant frags for different | |
2047 | purposes. */ | |
3c83da8a | 2048 | || (! mips_opts.mips16 |
cc5703cd | 2049 | && prev_insn_frag->fr_type == rs_machine_dependent) |
becfe05e ILT |
2050 | /* If the branch reads the condition codes, we don't |
2051 | even try to swap, because in the sequence | |
2052 | ctc1 $X,$31 | |
2053 | INSN | |
2054 | INSN | |
2055 | bc1t LABEL | |
2056 | we can not swap, and I don't feel like handling that | |
2057 | case. */ | |
3c83da8a JW |
2058 | || (! mips_opts.mips16 |
2059 | && mips_opts.isa < 4 | |
d8a1c247 | 2060 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
2061 | /* We can not swap with an instruction that requires a |
2062 | delay slot, becase the target of the branch might | |
2063 | interfere with that instruction. */ | |
3c83da8a JW |
2064 | || (! mips_opts.mips16 |
2065 | && mips_opts.isa < 4 | |
d8a1c247 | 2066 | && (prev_pinfo |
efec4a28 | 2067 | /* Itbl support may require additional care here. */ |
d8a1c247 KR |
2068 | & (INSN_LOAD_COPROC_DELAY |
2069 | | INSN_COPROC_MOVE_DELAY | |
2070 | | INSN_WRITE_COND_CODE))) | |
5c6f5923 | 2071 | || (! hilo_interlocks |
b2b8c24e ILT |
2072 | && (prev_pinfo |
2073 | & (INSN_READ_LO | |
2074 | | INSN_READ_HI))) | |
5c6f5923 GRK |
2075 | || (! mips_opts.mips16 |
2076 | && ! gpr_interlocks | |
2077 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
3c83da8a JW |
2078 | || (! mips_opts.mips16 |
2079 | && mips_opts.isa < 2 | |
5c6f5923 GRK |
2080 | /* Itbl support may require additional care here. */ |
2081 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) | |
becfe05e | 2082 | /* We can not swap with a branch instruction. */ |
1aa6938e | 2083 | || (prev_pinfo |
6e8dda9c ILT |
2084 | & (INSN_UNCOND_BRANCH_DELAY |
2085 | | INSN_COND_BRANCH_DELAY | |
2086 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
2087 | /* We do not swap with a trap instruction, since it |
2088 | complicates trap handlers to have the trap | |
2089 | instruction be in a delay slot. */ | |
1aa6938e | 2090 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
2091 | /* If the branch reads a register that the previous |
2092 | instruction sets, we can not swap. */ | |
3c83da8a | 2093 | || (! mips_opts.mips16 |
cc5703cd | 2094 | && (prev_pinfo & INSN_WRITE_GPR_T) |
becfe05e ILT |
2095 | && insn_uses_reg (ip, |
2096 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2097 | & OP_MASK_RT), | |
cc5703cd | 2098 | MIPS_GR_REG)) |
3c83da8a | 2099 | || (! mips_opts.mips16 |
cc5703cd | 2100 | && (prev_pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
2101 | && insn_uses_reg (ip, |
2102 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2103 | & OP_MASK_RD), | |
cc5703cd | 2104 | MIPS_GR_REG)) |
3c83da8a | 2105 | || (mips_opts.mips16 |
cc5703cd ILT |
2106 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) |
2107 | && insn_uses_reg (ip, | |
2108 | ((prev_insn.insn_opcode | |
2109 | >> MIPS16OP_SH_RX) | |
2110 | & MIPS16OP_MASK_RX), | |
2111 | MIPS16_REG)) | |
2112 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2113 | && insn_uses_reg (ip, | |
2114 | ((prev_insn.insn_opcode | |
2115 | >> MIPS16OP_SH_RY) | |
2116 | & MIPS16OP_MASK_RY), | |
2117 | MIPS16_REG)) | |
2118 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2119 | && insn_uses_reg (ip, | |
2120 | ((prev_insn.insn_opcode | |
2121 | >> MIPS16OP_SH_RZ) | |
2122 | & MIPS16OP_MASK_RZ), | |
2123 | MIPS16_REG)) | |
2124 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2125 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2126 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2127 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2128 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2129 | && insn_uses_reg (ip, | |
2130 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2131 | insn_opcode), | |
2132 | MIPS_GR_REG)))) | |
1849d646 ILT |
2133 | /* If the branch writes a register that the previous |
2134 | instruction sets, we can not swap (we know that | |
2135 | branches write only to RD or to $31). */ | |
3c83da8a | 2136 | || (! mips_opts.mips16 |
cc5703cd | 2137 | && (prev_pinfo & INSN_WRITE_GPR_T) |
1aa6938e | 2138 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
2139 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
2140 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 2141 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
2142 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
2143 | & OP_MASK_RT) | |
2144 | == 31)))) | |
3c83da8a | 2145 | || (! mips_opts.mips16 |
cc5703cd | 2146 | && (prev_pinfo & INSN_WRITE_GPR_D) |
1aa6938e | 2147 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
2148 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
2149 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 2150 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
2151 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
2152 | & OP_MASK_RD) | |
2153 | == 31)))) | |
3c83da8a | 2154 | || (mips_opts.mips16 |
cc5703cd ILT |
2155 | && (pinfo & MIPS16_INSN_WRITE_31) |
2156 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2157 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2158 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2159 | == RA)))) | |
becfe05e ILT |
2160 | /* If the branch writes a register that the previous |
2161 | instruction reads, we can not swap (we know that | |
2162 | branches only write to RD or to $31). */ | |
3c83da8a | 2163 | || (! mips_opts.mips16 |
cc5703cd | 2164 | && (pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
2165 | && insn_uses_reg (&prev_insn, |
2166 | ((ip->insn_opcode >> OP_SH_RD) | |
2167 | & OP_MASK_RD), | |
cc5703cd | 2168 | MIPS_GR_REG)) |
3c83da8a | 2169 | || (! mips_opts.mips16 |
cc5703cd ILT |
2170 | && (pinfo & INSN_WRITE_GPR_31) |
2171 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
3c83da8a | 2172 | || (mips_opts.mips16 |
cc5703cd ILT |
2173 | && (pinfo & MIPS16_INSN_WRITE_31) |
2174 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
5b63f465 ILT |
2175 | /* If we are generating embedded PIC code, the branch |
2176 | might be expanded into a sequence which uses $at, so | |
2177 | we can't swap with an instruction which reads it. */ | |
2178 | || (mips_pic == EMBEDDED_PIC | |
cc5703cd | 2179 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) |
becfe05e ILT |
2180 | /* If the previous previous instruction has a load |
2181 | delay, and sets a register that the branch reads, we | |
2182 | can not swap. */ | |
3c83da8a JW |
2183 | || (! mips_opts.mips16 |
2184 | && mips_opts.isa < 4 | |
efec4a28 | 2185 | /* Itbl support may require additional care here. */ |
d8a1c247 | 2186 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
5c6f5923 | 2187 | || (! gpr_interlocks |
d8a1c247 KR |
2188 | && (prev_prev_insn.insn_mo->pinfo |
2189 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
2190 | && insn_uses_reg (ip, |
2191 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2192 | & OP_MASK_RT), | |
cc5703cd | 2193 | MIPS_GR_REG)) |
d31a3f5e ILT |
2194 | /* If one instruction sets a condition code and the |
2195 | other one uses a condition code, we can not swap. */ | |
2196 | || ((pinfo & INSN_READ_COND_CODE) | |
2197 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2198 | || ((pinfo & INSN_WRITE_COND_CODE) | |
cc5703cd ILT |
2199 | && (prev_pinfo & INSN_READ_COND_CODE)) |
2200 | /* If the previous instruction uses the PC, we can not | |
2201 | swap. */ | |
3c83da8a | 2202 | || (mips_opts.mips16 |
cc5703cd ILT |
2203 | && (prev_pinfo & MIPS16_INSN_READ_PC)) |
2204 | /* If the previous instruction was extended, we can not | |
2205 | swap. */ | |
3c83da8a | 2206 | || (mips_opts.mips16 && prev_insn_extended) |
cc5703cd ILT |
2207 | /* If the previous instruction had a fixup in mips16 |
2208 | mode, we can not swap. This normally means that the | |
2209 | previous instruction was a 4 byte branch anyhow. */ | |
3c83da8a | 2210 | || (mips_opts.mips16 && prev_insn_fixp)) |
becfe05e ILT |
2211 | { |
2212 | /* We could do even better for unconditional branches to | |
2213 | portions of this object file; we could pick up the | |
2214 | instruction at the destination, put it in the delay | |
2215 | slot, and bump the destination address. */ | |
2216 | emit_nop (); | |
2217 | /* Update the previous insn information. */ | |
2218 | prev_prev_insn = *ip; | |
2219 | prev_insn.insn_mo = &dummy_opcode; | |
2220 | } | |
2221 | else | |
2222 | { | |
becfe05e | 2223 | /* It looks like we can actually do the swap. */ |
3c83da8a | 2224 | if (! mips_opts.mips16) |
cc5703cd ILT |
2225 | { |
2226 | char *prev_f; | |
2227 | char temp[4]; | |
2228 | ||
2229 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2230 | memcpy (temp, prev_f, 4); | |
2231 | memcpy (prev_f, f, 4); | |
2232 | memcpy (f, temp, 4); | |
2233 | if (prev_insn_fixp) | |
2234 | { | |
2235 | prev_insn_fixp->fx_frag = frag_now; | |
2236 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
2237 | } | |
2238 | if (fixp) | |
2239 | { | |
2240 | fixp->fx_frag = prev_insn_frag; | |
2241 | fixp->fx_where = prev_insn_where; | |
2242 | } | |
2243 | } | |
cc5703cd | 2244 | else |
becfe05e | 2245 | { |
cc5703cd ILT |
2246 | char *prev_f; |
2247 | char temp[2]; | |
2248 | ||
2249 | assert (prev_insn_fixp == NULL); | |
2250 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2251 | memcpy (temp, prev_f, 2); | |
2252 | memcpy (prev_f, f, 2); | |
2253 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
9cd4e6cc ILT |
2254 | { |
2255 | assert (reloc_type == BFD_RELOC_UNUSED); | |
2256 | memcpy (f, temp, 2); | |
2257 | } | |
cc5703cd ILT |
2258 | else |
2259 | { | |
2260 | memcpy (f, f + 2, 2); | |
2261 | memcpy (f + 2, temp, 2); | |
2262 | } | |
2263 | if (fixp) | |
2264 | { | |
2265 | fixp->fx_frag = prev_insn_frag; | |
2266 | fixp->fx_where = prev_insn_where; | |
2267 | } | |
becfe05e | 2268 | } |
cc5703cd | 2269 | |
becfe05e ILT |
2270 | /* Update the previous insn information; leave prev_insn |
2271 | unchanged. */ | |
2272 | prev_prev_insn = *ip; | |
2273 | } | |
2274 | prev_insn_is_delay_slot = 1; | |
2275 | ||
2276 | /* If that was an unconditional branch, forget the previous | |
2277 | insn information. */ | |
1aa6938e | 2278 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
2279 | { |
2280 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2281 | prev_insn.insn_mo = &dummy_opcode; | |
2282 | } | |
a677feeb ILT |
2283 | |
2284 | prev_insn_fixp = NULL; | |
2285 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2286 | prev_insn_extended = 0; | |
becfe05e | 2287 | } |
1aa6938e | 2288 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
2289 | { |
2290 | /* We don't yet optimize a branch likely. What we should do | |
2291 | is look at the target, copy the instruction found there | |
2292 | into the delay slot, and increment the branch to jump to | |
2293 | the next instruction. */ | |
2294 | emit_nop (); | |
2295 | /* Update the previous insn information. */ | |
2296 | prev_prev_insn = *ip; | |
2297 | prev_insn.insn_mo = &dummy_opcode; | |
a677feeb ILT |
2298 | prev_insn_fixp = NULL; |
2299 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2300 | prev_insn_extended = 0; | |
8358c818 | 2301 | } |
becfe05e | 2302 | else |
670a50eb | 2303 | { |
becfe05e ILT |
2304 | /* Update the previous insn information. */ |
2305 | if (nops > 0) | |
2306 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2307 | else | |
2308 | prev_prev_insn = prev_insn; | |
2309 | prev_insn = *ip; | |
2310 | ||
2311 | /* Any time we see a branch, we always fill the delay slot | |
2312 | immediately; since this insn is not a branch, we know it | |
2313 | is not in a delay slot. */ | |
2314 | prev_insn_is_delay_slot = 0; | |
a677feeb ILT |
2315 | |
2316 | prev_insn_fixp = fixp; | |
2317 | prev_insn_reloc_type = reloc_type; | |
3c83da8a | 2318 | if (mips_opts.mips16) |
a677feeb ILT |
2319 | prev_insn_extended = (ip->use_extend |
2320 | || reloc_type > BFD_RELOC_UNUSED); | |
becfe05e ILT |
2321 | } |
2322 | ||
4e95866e ILT |
2323 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2324 | prev_insn_unreordered = 0; | |
becfe05e ILT |
2325 | prev_insn_frag = frag_now; |
2326 | prev_insn_where = f - frag_now->fr_literal; | |
becfe05e | 2327 | prev_insn_valid = 1; |
7e656649 RH |
2328 | /* start-sanitize-branchbug4011 */ |
2329 | prev_insn_labels = !! insn_labels; | |
2330 | /* end-sanitize-branchbug4011 */ | |
becfe05e | 2331 | } |
fbcfacb7 | 2332 | else if (place == NULL) |
a677feeb | 2333 | { |
fbcfacb7 | 2334 | /* We need to record a bit of information even when we are not |
a677feeb ILT |
2335 | reordering, in order to determine the base address for mips16 |
2336 | PC relative relocs. */ | |
4a1cb507 | 2337 | prev_prev_insn = prev_insn; |
a677feeb ILT |
2338 | prev_insn = *ip; |
2339 | prev_insn_reloc_type = reloc_type; | |
4a1cb507 ILT |
2340 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2341 | prev_insn_unreordered = 1; | |
7e656649 RH |
2342 | /* start-sanitize-branchbug4011 */ |
2343 | prev_insn_labels = !! insn_labels; | |
2344 | /* end-sanitize-branchbug4011 */ | |
a677feeb | 2345 | } |
3d3c5039 | 2346 | |
becfe05e | 2347 | /* We just output an insn, so the next one doesn't have a label. */ |
fbcfacb7 | 2348 | mips_clear_insn_labels (); |
b073d428 ILT |
2349 | |
2350 | /* We must ensure that a fixup associated with an unmatched %hi | |
2351 | reloc does not become a variant frag. Otherwise, the | |
2352 | rearrangement of %hi relocs in frob_file may confuse | |
2353 | tc_gen_reloc. */ | |
2354 | if (unmatched_hi) | |
2355 | { | |
2356 | frag_wane (frag_now); | |
2357 | frag_new (0); | |
2358 | } | |
becfe05e ILT |
2359 | } |
2360 | ||
2361 | /* This function forgets that there was any previous instruction or | |
4a1cb507 ILT |
2362 | label. If PRESERVE is non-zero, it remembers enough information to |
2363 | know whether nops are needed before a noreorder section. */ | |
becfe05e ILT |
2364 | |
2365 | static void | |
4a1cb507 ILT |
2366 | mips_no_prev_insn (preserve) |
2367 | int preserve; | |
becfe05e | 2368 | { |
4a1cb507 ILT |
2369 | if (! preserve) |
2370 | { | |
2371 | prev_insn.insn_mo = &dummy_opcode; | |
2372 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2373 | prev_nop_frag = NULL; | |
2374 | prev_nop_frag_holds = 0; | |
2375 | prev_nop_frag_required = 0; | |
2376 | prev_nop_frag_since = 0; | |
2377 | } | |
becfe05e ILT |
2378 | prev_insn_valid = 0; |
2379 | prev_insn_is_delay_slot = 0; | |
4e95866e | 2380 | prev_insn_unreordered = 0; |
cc5703cd | 2381 | prev_insn_extended = 0; |
7e656649 RH |
2382 | /* start-sanitize-branchbug4011 */ |
2383 | prev_insn_labels = 0; | |
2384 | /* end-sanitize-branchbug4011 */ | |
a677feeb | 2385 | prev_insn_reloc_type = BFD_RELOC_UNUSED; |
4e95866e | 2386 | prev_prev_insn_unreordered = 0; |
fbcfacb7 | 2387 | mips_clear_insn_labels (); |
becfe05e ILT |
2388 | } |
2389 | ||
2390 | /* This function must be called whenever we turn on noreorder or emit | |
2391 | something other than instructions. It inserts any NOPS which might | |
2392 | be needed by the previous instruction, and clears the information | |
fbcfacb7 ILT |
2393 | kept for the previous instructions. The INSNS parameter is true if |
2394 | instructions are to follow. */ | |
becfe05e ILT |
2395 | |
2396 | static void | |
fbcfacb7 ILT |
2397 | mips_emit_delays (insns) |
2398 | boolean insns; | |
becfe05e | 2399 | { |
3c83da8a | 2400 | if (! mips_opts.noreorder) |
becfe05e | 2401 | { |
4a1cb507 | 2402 | int nops; |
becfe05e | 2403 | |
4a1cb507 | 2404 | nops = 0; |
3c83da8a JW |
2405 | if ((! mips_opts.mips16 |
2406 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2407 | && (! cop_interlocks |
2408 | && (prev_insn.insn_mo->pinfo | |
2409 | & (INSN_LOAD_COPROC_DELAY | |
2410 | | INSN_COPROC_MOVE_DELAY | |
2411 | | INSN_WRITE_COND_CODE)))) | |
5c6f5923 | 2412 | || (! hilo_interlocks |
b2b8c24e ILT |
2413 | && (prev_insn.insn_mo->pinfo |
2414 | & (INSN_READ_LO | |
2415 | | INSN_READ_HI))) | |
5c6f5923 GRK |
2416 | || (! mips_opts.mips16 |
2417 | && ! gpr_interlocks | |
2418 | && (prev_insn.insn_mo->pinfo | |
2419 | & INSN_LOAD_MEMORY_DELAY)) | |
3c83da8a JW |
2420 | || (! mips_opts.mips16 |
2421 | && mips_opts.isa < 2 | |
8358c818 | 2422 | && (prev_insn.insn_mo->pinfo |
5c6f5923 | 2423 | & INSN_COPROC_MEMORY_DELAY))) |
becfe05e | 2424 | { |
efec4a28 | 2425 | /* Itbl support may require additional care here. */ |
4a1cb507 | 2426 | ++nops; |
3c83da8a JW |
2427 | if ((! mips_opts.mips16 |
2428 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2429 | && (! cop_interlocks |
2430 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
5c6f5923 | 2431 | || (! hilo_interlocks |
b2b8c24e ILT |
2432 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2433 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 ILT |
2434 | ++nops; |
2435 | ||
2436 | if (prev_insn_unreordered) | |
2437 | nops = 0; | |
becfe05e | 2438 | } |
3c83da8a JW |
2439 | else if ((! mips_opts.mips16 |
2440 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2441 | && (! cop_interlocks |
2442 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
5c6f5923 | 2443 | || (! hilo_interlocks |
b2b8c24e ILT |
2444 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2445 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 | 2446 | { |
efec4a28 | 2447 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
2448 | if (! prev_prev_insn_unreordered) |
2449 | ++nops; | |
2450 | } | |
2451 | ||
2452 | if (nops > 0) | |
670a50eb | 2453 | { |
fbcfacb7 ILT |
2454 | struct insn_label_list *l; |
2455 | ||
4a1cb507 ILT |
2456 | if (insns) |
2457 | { | |
2458 | /* Record the frag which holds the nop instructions, so | |
2459 | that we can remove them if we don't need them. */ | |
3c83da8a | 2460 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); |
4a1cb507 ILT |
2461 | prev_nop_frag = frag_now; |
2462 | prev_nop_frag_holds = nops; | |
2463 | prev_nop_frag_required = 0; | |
2464 | prev_nop_frag_since = 0; | |
2465 | } | |
2466 | ||
2467 | for (; nops > 0; --nops) | |
2468 | emit_nop (); | |
2469 | ||
2470 | if (insns) | |
2471 | { | |
2472 | /* Move on to a new frag, so that it is safe to simply | |
2473 | decrease the size of prev_nop_frag. */ | |
2474 | frag_wane (frag_now); | |
2475 | frag_new (0); | |
2476 | } | |
2477 | ||
fbcfacb7 | 2478 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 2479 | { |
fbcfacb7 ILT |
2480 | assert (S_GET_SEGMENT (l->label) == now_seg); |
2481 | l->label->sy_frag = frag_now; | |
2482 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
2483 | /* mips16 text labels are stored as odd. */ | |
3c83da8a | 2484 | if (mips_opts.mips16) |
fbcfacb7 | 2485 | ++l->label->sy_value.X_add_number; |
becfe05e | 2486 | } |
3d3c5039 ILT |
2487 | } |
2488 | } | |
0221ddf7 | 2489 | |
3c83da8a JW |
2490 | /* Mark instruction labels in mips16 mode. */ |
2491 | if (mips_opts.mips16 && insns) | |
2492 | mips16_mark_labels (); | |
fbcfacb7 | 2493 | |
4a1cb507 | 2494 | mips_no_prev_insn (insns); |
3d3c5039 ILT |
2495 | } |
2496 | ||
670a50eb ILT |
2497 | /* Build an instruction created by a macro expansion. This is passed |
2498 | a pointer to the count of instructions created so far, an | |
2499 | expression, the name of the instruction to build, an operand format | |
2500 | string, and corresponding arguments. */ | |
2501 | ||
1dc1e798 | 2502 | #ifdef USE_STDARG |
3d3c5039 | 2503 | static void |
0dd2d296 ILT |
2504 | macro_build (char *place, |
2505 | int *counter, | |
670a50eb | 2506 | expressionS * ep, |
3d3c5039 ILT |
2507 | const char *name, |
2508 | const char *fmt, | |
2509 | ...) | |
1dc1e798 | 2510 | #else |
3d3c5039 | 2511 | static void |
0dd2d296 ILT |
2512 | macro_build (place, counter, ep, name, fmt, va_alist) |
2513 | char *place; | |
3d3c5039 ILT |
2514 | int *counter; |
2515 | expressionS *ep; | |
2516 | const char *name; | |
2517 | const char *fmt; | |
2518 | va_dcl | |
1dc1e798 | 2519 | #endif |
3d3c5039 | 2520 | { |
670a50eb ILT |
2521 | struct mips_cl_insn insn; |
2522 | bfd_reloc_code_real_type r; | |
2523 | va_list args; | |
931a1858 | 2524 | int insn_isa; |
3d3c5039 | 2525 | |
1dc1e798 | 2526 | #ifdef USE_STDARG |
670a50eb | 2527 | va_start (args, fmt); |
3d3c5039 | 2528 | #else |
670a50eb | 2529 | va_start (args); |
3d3c5039 ILT |
2530 | #endif |
2531 | ||
670a50eb ILT |
2532 | /* |
2533 | * If the macro is about to expand into a second instruction, | |
2534 | * print a warning if needed. We need to pass ip as a parameter | |
2535 | * to generate a better warning message here... | |
2536 | */ | |
3c83da8a | 2537 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) |
48401fcf | 2538 | as_warn (_("Macro instruction expanded into multiple instructions")); |
670a50eb | 2539 | |
0dd2d296 ILT |
2540 | if (place == NULL) |
2541 | *counter += 1; /* bump instruction counter */ | |
670a50eb | 2542 | |
3c83da8a | 2543 | if (mips_opts.mips16) |
cc5703cd ILT |
2544 | { |
2545 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2546 | va_end (args); | |
2547 | return; | |
2548 | } | |
2549 | ||
670a50eb ILT |
2550 | r = BFD_RELOC_UNUSED; |
2551 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2552 | assert (insn.insn_mo); | |
2553 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2554 | ||
931a1858 JL |
2555 | /* Search until we get a match for NAME. */ |
2556 | while (1) | |
670a50eb | 2557 | { |
1c6f3441 | 2558 | if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA1) |
931a1858 JL |
2559 | insn_isa = 1; |
2560 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA2) | |
2561 | insn_isa = 2; | |
2562 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA3) | |
2563 | insn_isa = 3; | |
2564 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA4) | |
2565 | insn_isa = 4; | |
2566 | else | |
2567 | insn_isa = 15; | |
2568 | ||
a652f74c ILT |
2569 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2570 | && insn.insn_mo->pinfo != INSN_MACRO | |
2571 | && (insn_isa <= mips_opts.isa | |
2572 | || (mips_4650 | |
2573 | && (insn.insn_mo->membership & INSN_4650) != 0) | |
2574 | || (mips_4010 | |
2575 | && (insn.insn_mo->membership & INSN_4010) != 0) | |
2576 | || (mips_4100 | |
2577 | && (insn.insn_mo->membership & INSN_4100) != 0) | |
2d035a50 GRK |
2578 | /* start-sanitize-vr4320 */ |
2579 | || (mips_4320 | |
2580 | && (insn.insn_mo->membership & INSN_4320) != 0) | |
2581 | /* end-sanitize-vr4320 */ | |
42444087 GRK |
2582 | /* start-sanitize-tx49 */ |
2583 | || (mips_4900 | |
2584 | && (insn.insn_mo->membership & INSN_4900) != 0) | |
2585 | /* end-sanitize-tx49 */ | |
a652f74c ILT |
2586 | /* start-sanitize-r5900 */ |
2587 | || (mips_5900 | |
2588 | && (insn.insn_mo->membership & INSN_5900) != 0) | |
2589 | /* end-sanitize-r5900 */ | |
6b34ac5a | 2590 | /* start-sanitize-cygnus */ |
aa2e0460 KR |
2591 | || (mips_5400 |
2592 | && (insn.insn_mo->membership & INSN_5400) != 0) | |
6b34ac5a | 2593 | /* end-sanitize-cygnus */ |
a652f74c ILT |
2594 | || (mips_3900 |
2595 | && (insn.insn_mo->membership & INSN_3900) != 0)) | |
2596 | /* start-sanitize-r5900 */ | |
2597 | && (! mips_5900 || (insn.insn_mo->pinfo & FP_D) == 0) | |
2598 | /* end-sanitize-r5900 */ | |
2599 | && (! mips_4650 || (insn.insn_mo->pinfo & FP_D) == 0)) | |
2600 | break; | |
931a1858 | 2601 | |
a652f74c ILT |
2602 | ++insn.insn_mo; |
2603 | assert (insn.insn_mo->name); | |
2604 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 2605 | } |
931a1858 | 2606 | |
670a50eb ILT |
2607 | insn.insn_opcode = insn.insn_mo->match; |
2608 | for (;;) | |
2609 | { | |
2610 | switch (*fmt++) | |
2611 | { | |
3d3c5039 | 2612 | case '\0': |
670a50eb | 2613 | break; |
3d3c5039 ILT |
2614 | |
2615 | case ',': | |
2616 | case '(': | |
2617 | case ')': | |
670a50eb | 2618 | continue; |
3d3c5039 ILT |
2619 | |
2620 | case 't': | |
2621 | case 'w': | |
918692a5 | 2622 | case 'E': |
670a50eb ILT |
2623 | insn.insn_opcode |= va_arg (args, int) << 16; |
2624 | continue; | |
3d3c5039 ILT |
2625 | |
2626 | case 'c': | |
2627 | case 'T': | |
2628 | case 'W': | |
670a50eb ILT |
2629 | insn.insn_opcode |= va_arg (args, int) << 16; |
2630 | continue; | |
3d3c5039 ILT |
2631 | |
2632 | case 'd': | |
918692a5 | 2633 | case 'G': |
670a50eb ILT |
2634 | insn.insn_opcode |= va_arg (args, int) << 11; |
2635 | continue; | |
3d3c5039 ILT |
2636 | |
2637 | case 'V': | |
2638 | case 'S': | |
670a50eb ILT |
2639 | insn.insn_opcode |= va_arg (args, int) << 11; |
2640 | continue; | |
3d3c5039 | 2641 | |
ff3a5c18 ILT |
2642 | case 'z': |
2643 | continue; | |
2644 | ||
3d3c5039 | 2645 | case '<': |
670a50eb ILT |
2646 | insn.insn_opcode |= va_arg (args, int) << 6; |
2647 | continue; | |
3d3c5039 ILT |
2648 | |
2649 | case 'D': | |
670a50eb ILT |
2650 | insn.insn_opcode |= va_arg (args, int) << 6; |
2651 | continue; | |
3d3c5039 | 2652 | |
918692a5 ILT |
2653 | case 'B': |
2654 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2655 | continue; | |
2656 | ||
40f0c904 FCE |
2657 | case 'q': |
2658 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2659 | continue; | |
2660 | ||
3d3c5039 ILT |
2661 | case 'b': |
2662 | case 's': | |
2663 | case 'r': | |
2664 | case 'v': | |
670a50eb ILT |
2665 | insn.insn_opcode |= va_arg (args, int) << 21; |
2666 | continue; | |
3d3c5039 ILT |
2667 | |
2668 | case 'i': | |
2669 | case 'j': | |
2670 | case 'o': | |
9226253a | 2671 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
2672 | assert (r == BFD_RELOC_MIPS_GPREL |
2673 | || r == BFD_RELOC_MIPS_LITERAL | |
2674 | || r == BFD_RELOC_LO16 | |
2675 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c | 2676 | || r == BFD_RELOC_MIPS_CALL16 |
fb251650 ILT |
2677 | || r == BFD_RELOC_MIPS_GOT_LO16 |
2678 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
ecd4ca1c ILT |
2679 | || (ep->X_op == O_subtract |
2680 | && now_seg == text_section | |
ecd4ca1c | 2681 | && r == BFD_RELOC_PCREL_LO16)); |
670a50eb | 2682 | continue; |
3d3c5039 | 2683 | |
6e8dda9c | 2684 | case 'u': |
ecd4ca1c ILT |
2685 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
2686 | assert (ep != NULL | |
2687 | && (ep->X_op == O_constant | |
2688 | || (ep->X_op == O_symbol | |
2689 | && (r == BFD_RELOC_HI16_S | |
fb251650 ILT |
2690 | || r == BFD_RELOC_HI16 |
2691 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2692 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
ecd4ca1c ILT |
2693 | || (ep->X_op == O_subtract |
2694 | && now_seg == text_section | |
ecd4ca1c ILT |
2695 | && r == BFD_RELOC_PCREL_HI16_S))); |
2696 | if (ep->X_op == O_constant) | |
2697 | { | |
2698 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2699 | ep = NULL; | |
2700 | r = BFD_RELOC_UNUSED; | |
2701 | } | |
6e8dda9c ILT |
2702 | continue; |
2703 | ||
3d3c5039 | 2704 | case 'p': |
670a50eb ILT |
2705 | assert (ep != NULL); |
2706 | /* | |
2707 | * This allows macro() to pass an immediate expression for | |
2708 | * creating short branches without creating a symbol. | |
2709 | * Note that the expression still might come from the assembly | |
2710 | * input, in which case the value is not checked for range nor | |
2711 | * is a relocation entry generated (yuck). | |
2712 | */ | |
5ac34ac3 | 2713 | if (ep->X_op == O_constant) |
670a50eb ILT |
2714 | { |
2715 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2716 | ep = NULL; | |
2717 | } | |
2718 | else | |
2719 | r = BFD_RELOC_16_PCREL_S2; | |
2720 | continue; | |
3d3c5039 | 2721 | |
9226253a ILT |
2722 | case 'a': |
2723 | assert (ep != NULL); | |
2724 | r = BFD_RELOC_MIPS_JMP; | |
2725 | continue; | |
2726 | ||
65d2c7d3 JL |
2727 | case 'C': |
2728 | insn.insn_opcode |= va_arg (args, unsigned long); | |
2729 | continue; | |
2730 | ||
3d3c5039 | 2731 | default: |
670a50eb | 2732 | internalError (); |
3d3c5039 | 2733 | } |
670a50eb | 2734 | break; |
3d3c5039 | 2735 | } |
670a50eb ILT |
2736 | va_end (args); |
2737 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2738 | ||
867a58b3 | 2739 | append_insn (place, &insn, ep, r, false); |
3d3c5039 ILT |
2740 | } |
2741 | ||
cc5703cd ILT |
2742 | static void |
2743 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2744 | char *place; | |
2745 | int *counter; | |
2746 | expressionS *ep; | |
2747 | const char *name; | |
2748 | const char *fmt; | |
2749 | va_list args; | |
2750 | { | |
2751 | struct mips_cl_insn insn; | |
2752 | bfd_reloc_code_real_type r; | |
2753 | ||
2754 | r = BFD_RELOC_UNUSED; | |
2755 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2756 | assert (insn.insn_mo); | |
2757 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2758 | ||
2759 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2760 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2761 | { | |
2762 | ++insn.insn_mo; | |
2763 | assert (insn.insn_mo->name); | |
2764 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2765 | } | |
2766 | ||
2767 | insn.insn_opcode = insn.insn_mo->match; | |
2768 | insn.use_extend = false; | |
2769 | ||
2770 | for (;;) | |
2771 | { | |
2772 | int c; | |
2773 | ||
2774 | c = *fmt++; | |
2775 | switch (c) | |
2776 | { | |
2777 | case '\0': | |
2778 | break; | |
2779 | ||
2780 | case ',': | |
2781 | case '(': | |
2782 | case ')': | |
2783 | continue; | |
2784 | ||
2785 | case 'y': | |
2786 | case 'w': | |
2787 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2788 | continue; | |
2789 | ||
2790 | case 'x': | |
2791 | case 'v': | |
2792 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2793 | continue; | |
2794 | ||
2795 | case 'z': | |
2796 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2797 | continue; | |
2798 | ||
2799 | case 'Z': | |
2800 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2801 | continue; | |
2802 | ||
2803 | case '0': | |
2804 | case 'S': | |
2805 | case 'P': | |
2806 | case 'R': | |
2807 | continue; | |
2808 | ||
2809 | case 'X': | |
2810 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2811 | continue; | |
2812 | ||
2813 | case 'Y': | |
2814 | { | |
2815 | int regno; | |
2816 | ||
2817 | regno = va_arg (args, int); | |
2818 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2819 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2820 | } | |
2821 | continue; | |
2822 | ||
2823 | case '<': | |
2824 | case '>': | |
2825 | case '4': | |
2826 | case '5': | |
2827 | case 'H': | |
2828 | case 'W': | |
2829 | case 'D': | |
2830 | case 'j': | |
2831 | case '8': | |
2832 | case 'V': | |
2833 | case 'C': | |
2834 | case 'U': | |
2835 | case 'k': | |
2836 | case 'K': | |
2837 | case 'p': | |
2838 | case 'q': | |
2839 | { | |
2840 | assert (ep != NULL); | |
2841 | ||
2842 | if (ep->X_op != O_constant) | |
2843 | r = BFD_RELOC_UNUSED + c; | |
2844 | else | |
2845 | { | |
15e69f98 ILT |
2846 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, |
2847 | false, false, &insn.insn_opcode, | |
2848 | &insn.use_extend, &insn.extend); | |
cc5703cd ILT |
2849 | ep = NULL; |
2850 | r = BFD_RELOC_UNUSED; | |
2851 | } | |
2852 | } | |
2853 | continue; | |
2854 | ||
2855 | case '6': | |
2856 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2857 | continue; | |
2858 | } | |
2859 | ||
2860 | break; | |
2861 | } | |
2862 | ||
2863 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2864 | ||
2865 | append_insn (place, &insn, ep, r, false); | |
2866 | } | |
2867 | ||
3d3c5039 ILT |
2868 | /* |
2869 | * Generate a "lui" instruction. | |
2870 | */ | |
2871 | static void | |
0dd2d296 ILT |
2872 | macro_build_lui (place, counter, ep, regnum) |
2873 | char *place; | |
3d3c5039 ILT |
2874 | int *counter; |
2875 | expressionS *ep; | |
2876 | int regnum; | |
2877 | { | |
670a50eb ILT |
2878 | expressionS high_expr; |
2879 | struct mips_cl_insn insn; | |
2880 | bfd_reloc_code_real_type r; | |
2881 | CONST char *name = "lui"; | |
2882 | CONST char *fmt = "t,u"; | |
2883 | ||
3c83da8a | 2884 | assert (! mips_opts.mips16); |
cc5703cd | 2885 | |
0dd2d296 ILT |
2886 | if (place == NULL) |
2887 | high_expr = *ep; | |
2888 | else | |
2889 | { | |
2890 | high_expr.X_op = O_constant; | |
fb251650 | 2891 | high_expr.X_add_number = ep->X_add_number; |
0dd2d296 | 2892 | } |
670a50eb | 2893 | |
5ac34ac3 | 2894 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
2895 | { |
2896 | /* we can compute the instruction now without a relocation entry */ | |
2897 | if (high_expr.X_add_number & 0x8000) | |
2898 | high_expr.X_add_number += 0x10000; | |
2899 | high_expr.X_add_number = | |
2900 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2901 | r = BFD_RELOC_UNUSED; | |
2902 | } | |
2903 | else | |
0dd2d296 ILT |
2904 | { |
2905 | assert (ep->X_op == O_symbol); | |
2906 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 2907 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
2908 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
2909 | r = BFD_RELOC_HI16_S; | |
2910 | } | |
670a50eb ILT |
2911 | |
2912 | /* | |
2913 | * If the macro is about to expand into a second instruction, | |
2914 | * print a warning if needed. We need to pass ip as a parameter | |
2915 | * to generate a better warning message here... | |
2916 | */ | |
3c83da8a | 2917 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) |
48401fcf | 2918 | as_warn (_("Macro instruction expanded into multiple instructions")); |
670a50eb | 2919 | |
0dd2d296 ILT |
2920 | if (place == NULL) |
2921 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
2922 | |
2923 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2924 | assert (insn.insn_mo); | |
2925 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2926 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2927 | ||
0dd2d296 | 2928 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
2929 | if (r == BFD_RELOC_UNUSED) |
2930 | { | |
2931 | insn.insn_opcode |= high_expr.X_add_number; | |
867a58b3 | 2932 | append_insn (place, &insn, NULL, r, false); |
670a50eb ILT |
2933 | } |
2934 | else | |
867a58b3 | 2935 | append_insn (place, &insn, &high_expr, r, false); |
3d3c5039 ILT |
2936 | } |
2937 | ||
2938 | /* set_at() | |
2939 | * Generates code to set the $at register to true (one) | |
2940 | * if reg is less than the immediate expression. | |
2941 | */ | |
2942 | static void | |
6e8dda9c | 2943 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
2944 | int *counter; |
2945 | int reg; | |
6e8dda9c | 2946 | int unsignedp; |
3d3c5039 | 2947 | { |
5c6f5923 GRK |
2948 | if (imm_expr.X_op == O_constant |
2949 | && imm_expr.X_add_number >= -0x8000 | |
2950 | && imm_expr.X_add_number < 0x8000) | |
0dd2d296 | 2951 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 2952 | unsignedp ? "sltiu" : "slti", |
9226253a | 2953 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 2954 | else |
670a50eb | 2955 | { |
d8a1c247 | 2956 | load_register (counter, AT, &imm_expr, 0); |
0dd2d296 | 2957 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
2958 | unsignedp ? "sltu" : "slt", |
2959 | "d,v,t", AT, reg, AT); | |
670a50eb | 2960 | } |
3d3c5039 ILT |
2961 | } |
2962 | ||
6e8dda9c | 2963 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
2964 | |
2965 | static void | |
19ed8960 | 2966 | check_absolute_expr (ip, ex) |
3d3c5039 | 2967 | struct mips_cl_insn *ip; |
19ed8960 | 2968 | expressionS *ex; |
3d3c5039 | 2969 | { |
5c6f5923 | 2970 | if (ex->X_op == O_big) |
48401fcf | 2971 | as_bad (_("unsupported large constant")); |
5c6f5923 | 2972 | else if (ex->X_op != O_constant) |
48401fcf | 2973 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); |
3d3c5039 ILT |
2974 | } |
2975 | ||
ff8716f5 JSC |
2976 | /* Count the leading zeroes by performing a binary chop. This is a |
2977 | bulky bit of source, but performance is a LOT better for the | |
2978 | majority of values than a simple loop to count the bits: | |
2979 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2980 | if ((v) & (1 << (31 - lcnt))) | |
2981 | break; | |
2982 | However it is not code size friendly, and the gain will drop a bit | |
2983 | on certain cached systems. | |
2984 | */ | |
2985 | #define COUNT_TOP_ZEROES(v) \ | |
2986 | (((v) & ~0xffff) == 0 \ | |
2987 | ? ((v) & ~0xff) == 0 \ | |
2988 | ? ((v) & ~0xf) == 0 \ | |
2989 | ? ((v) & ~0x3) == 0 \ | |
2990 | ? ((v) & ~0x1) == 0 \ | |
2991 | ? !(v) \ | |
2992 | ? 32 \ | |
2993 | : 31 \ | |
2994 | : 30 \ | |
2995 | : ((v) & ~0x7) == 0 \ | |
2996 | ? 29 \ | |
2997 | : 28 \ | |
2998 | : ((v) & ~0x3f) == 0 \ | |
2999 | ? ((v) & ~0x1f) == 0 \ | |
3000 | ? 27 \ | |
3001 | : 26 \ | |
3002 | : ((v) & ~0x7f) == 0 \ | |
3003 | ? 25 \ | |
3004 | : 24 \ | |
3005 | : ((v) & ~0xfff) == 0 \ | |
3006 | ? ((v) & ~0x3ff) == 0 \ | |
3007 | ? ((v) & ~0x1ff) == 0 \ | |
3008 | ? 23 \ | |
3009 | : 22 \ | |
3010 | : ((v) & ~0x7ff) == 0 \ | |
3011 | ? 21 \ | |
3012 | : 20 \ | |
3013 | : ((v) & ~0x3fff) == 0 \ | |
3014 | ? ((v) & ~0x1fff) == 0 \ | |
3015 | ? 19 \ | |
3016 | : 18 \ | |
3017 | : ((v) & ~0x7fff) == 0 \ | |
3018 | ? 17 \ | |
3019 | : 16 \ | |
3020 | : ((v) & ~0xffffff) == 0 \ | |
3021 | ? ((v) & ~0xfffff) == 0 \ | |
3022 | ? ((v) & ~0x3ffff) == 0 \ | |
3023 | ? ((v) & ~0x1ffff) == 0 \ | |
3024 | ? 15 \ | |
3025 | : 14 \ | |
3026 | : ((v) & ~0x7ffff) == 0 \ | |
3027 | ? 13 \ | |
3028 | : 12 \ | |
3029 | : ((v) & ~0x3fffff) == 0 \ | |
3030 | ? ((v) & ~0x1fffff) == 0 \ | |
3031 | ? 11 \ | |
3032 | : 10 \ | |
3033 | : ((v) & ~0x7fffff) == 0 \ | |
3034 | ? 9 \ | |
3035 | : 8 \ | |
3036 | : ((v) & ~0xfffffff) == 0 \ | |
3037 | ? ((v) & ~0x3ffffff) == 0 \ | |
3038 | ? ((v) & ~0x1ffffff) == 0 \ | |
3039 | ? 7 \ | |
3040 | : 6 \ | |
3041 | : ((v) & ~0x7ffffff) == 0 \ | |
3042 | ? 5 \ | |
3043 | : 4 \ | |
3044 | : ((v) & ~0x3fffffff) == 0 \ | |
3045 | ? ((v) & ~0x1fffffff) == 0 \ | |
3046 | ? 3 \ | |
3047 | : 2 \ | |
3048 | : ((v) & ~0x7fffffff) == 0 \ | |
3049 | ? 1 \ | |
3050 | : 0) | |
3051 | ||
3d3c5039 ILT |
3052 | /* load_register() |
3053 | * This routine generates the least number of instructions neccessary to load | |
3054 | * an absolute expression value into a register. | |
3055 | */ | |
3056 | static void | |
d8a1c247 | 3057 | load_register (counter, reg, ep, dbl) |
670a50eb | 3058 | int *counter; |
670a50eb ILT |
3059 | int reg; |
3060 | expressionS *ep; | |
d8a1c247 | 3061 | int dbl; |
3d3c5039 | 3062 | { |
c36a90ef ILT |
3063 | int freg; |
3064 | expressionS hi32, lo32; | |
847a01cd ILT |
3065 | |
3066 | if (ep->X_op != O_big) | |
6e8dda9c | 3067 | { |
847a01cd | 3068 | assert (ep->X_op == O_constant); |
d8a1c247 KR |
3069 | if (ep->X_add_number < 0x8000 |
3070 | && (ep->X_add_number >= 0 | |
3071 | || (ep->X_add_number >= -0x8000 | |
3072 | && (! dbl | |
3073 | || ! ep->X_unsigned | |
3074 | || sizeof (ep->X_add_number) > 4)))) | |
847a01cd ILT |
3075 | { |
3076 | /* We can handle 16 bit signed values with an addiu to | |
3077 | $zero. No need to ever use daddiu here, since $zero and | |
3078 | the result are always correct in 32 bit mode. */ | |
3079 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
3080 | (int) BFD_RELOC_LO16); | |
3081 | return; | |
3082 | } | |
3083 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3084 | { | |
3085 | /* We can handle 16 bit unsigned values with an ori to | |
3086 | $zero. */ | |
3087 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
3088 | (int) BFD_RELOC_LO16); | |
3089 | return; | |
3090 | } | |
98bfd087 ILT |
3091 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
3092 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
3093 | == ~ (offsetT) 0x7fffffff)) | |
3094 | && (! dbl | |
3095 | || ! ep->X_unsigned | |
3096 | || sizeof (ep->X_add_number) > 4 | |
3097 | || (ep->X_add_number & 0x80000000) == 0)) | |
3c83da8a | 3098 | || ((mips_opts.isa < 3 || ! dbl) |
f59fb6ca | 3099 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
3c83da8a | 3100 | || (mips_opts.isa < 3 |
f59fb6ca ILT |
3101 | && ! dbl |
3102 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
3103 | == ~ (offsetT) 0xffffffff))) | |
847a01cd ILT |
3104 | { |
3105 | /* 32 bit values require an lui. */ | |
3106 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3107 | (int) BFD_RELOC_HI16); | |
3108 | if ((ep->X_add_number & 0xffff) != 0) | |
3109 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
3110 | (int) BFD_RELOC_LO16); | |
3111 | return; | |
3112 | } | |
6e8dda9c | 3113 | } |
847a01cd ILT |
3114 | |
3115 | /* The value is larger than 32 bits. */ | |
3116 | ||
3c83da8a | 3117 | if (mips_opts.isa < 3) |
670a50eb | 3118 | { |
48401fcf | 3119 | as_bad (_("Number larger than 32 bits")); |
0dd2d296 | 3120 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 3121 | (int) BFD_RELOC_LO16); |
847a01cd | 3122 | return; |
6e8dda9c | 3123 | } |
6e8dda9c | 3124 | |
847a01cd ILT |
3125 | if (ep->X_op != O_big) |
3126 | { | |
6e8dda9c | 3127 | hi32 = *ep; |
c36a90ef ILT |
3128 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
3129 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
6e8dda9c | 3130 | hi32.X_add_number &= 0xffffffff; |
6e8dda9c ILT |
3131 | lo32 = *ep; |
3132 | lo32.X_add_number &= 0xffffffff; | |
670a50eb | 3133 | } |
847a01cd ILT |
3134 | else |
3135 | { | |
3136 | assert (ep->X_add_number > 2); | |
3137 | if (ep->X_add_number == 3) | |
3138 | generic_bignum[3] = 0; | |
3139 | else if (ep->X_add_number > 4) | |
48401fcf | 3140 | as_bad (_("Number larger than 64 bits")); |
847a01cd ILT |
3141 | lo32.X_op = O_constant; |
3142 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3143 | hi32.X_op = O_constant; | |
3144 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3145 | } | |
3146 | ||
d8a1c247 KR |
3147 | if (hi32.X_add_number == 0) |
3148 | freg = 0; | |
3149 | else | |
3150 | { | |
c36a90ef ILT |
3151 | int shift, bit; |
3152 | unsigned long hi, lo; | |
3153 | ||
fb251650 ILT |
3154 | if (hi32.X_add_number == 0xffffffff) |
3155 | { | |
3156 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3157 | { | |
c36a90ef ILT |
3158 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", |
3159 | reg, 0, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
3160 | return; |
3161 | } | |
3162 | if (lo32.X_add_number & 0x80000000) | |
3163 | { | |
3164 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3165 | (int) BFD_RELOC_HI16); | |
c36a90ef ILT |
3166 | if (lo32.X_add_number & 0xffff) |
3167 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
3168 | reg, reg, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
3169 | return; |
3170 | } | |
3171 | } | |
ff8716f5 | 3172 | |
c36a90ef ILT |
3173 | /* Check for 16bit shifted constant. We know that hi32 is |
3174 | non-zero, so start the mask on the first bit of the hi32 | |
3175 | value. */ | |
ff8716f5 JSC |
3176 | shift = 17; |
3177 | do | |
3178 | { | |
c36a90ef ILT |
3179 | unsigned long himask, lomask; |
3180 | ||
3181 | if (shift < 32) | |
3182 | { | |
3183 | himask = 0xffff >> (32 - shift); | |
3184 | lomask = (0xffff << shift) & 0xffffffff; | |
3185 | } | |
3186 | else | |
3187 | { | |
3188 | himask = 0xffff << (shift - 32); | |
3189 | lomask = 0; | |
3190 | } | |
3191 | if ((hi32.X_add_number & ~ (offsetT) himask) == 0 | |
3192 | && (lo32.X_add_number & ~ (offsetT) lomask) == 0) | |
3193 | { | |
3194 | expressionS tmp; | |
3195 | ||
3196 | tmp.X_op = O_constant; | |
3197 | if (shift < 32) | |
3198 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3199 | | (lo32.X_add_number >> shift)); | |
3200 | else | |
3201 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
3202 | macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, | |
3203 | (int) BFD_RELOC_LO16); | |
3204 | macro_build ((char *) NULL, counter, NULL, | |
3205 | (shift >= 32) ? "dsll32" : "dsll", | |
3206 | "d,w,<", reg, reg, | |
3207 | (shift >= 32) ? shift - 32 : shift); | |
3208 | return; | |
3209 | } | |
ff8716f5 JSC |
3210 | shift++; |
3211 | } while (shift <= (64 - 16)); | |
3212 | ||
c36a90ef ILT |
3213 | /* Find the bit number of the lowest one bit, and store the |
3214 | shifted value in hi/lo. */ | |
3215 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3216 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3217 | if (lo != 0) | |
3218 | { | |
3219 | bit = 0; | |
3220 | while ((lo & 1) == 0) | |
3221 | { | |
3222 | lo >>= 1; | |
3223 | ++bit; | |
3224 | } | |
3225 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3226 | hi >>= bit; | |
3227 | } | |
3228 | else | |
3229 | { | |
3230 | bit = 32; | |
3231 | while ((hi & 1) == 0) | |
3232 | { | |
3233 | hi >>= 1; | |
3234 | ++bit; | |
3235 | } | |
3236 | lo = hi; | |
3237 | hi = 0; | |
3238 | } | |
3239 | ||
3240 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3241 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3242 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
ff8716f5 | 3243 | { |
c36a90ef | 3244 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); |
ff8716f5 JSC |
3245 | if (shift != 0) |
3246 | { | |
c36a90ef ILT |
3247 | expressionS tmp; |
3248 | ||
3249 | /* This instruction will set the register to be all | |
3250 | ones. */ | |
ff8716f5 | 3251 | tmp.X_op = O_constant; |
c36a90ef ILT |
3252 | tmp.X_add_number = (offsetT) -1; |
3253 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
3254 | reg, 0, (int) BFD_RELOC_LO16); | |
3255 | if (bit != 0) | |
ff8716f5 | 3256 | { |
c36a90ef | 3257 | bit += shift; |
ff8716f5 | 3258 | macro_build ((char *) NULL, counter, NULL, |
c36a90ef | 3259 | (bit >= 32) ? "dsll32" : "dsll", |
ff8716f5 | 3260 | "d,w,<", reg, reg, |
c36a90ef | 3261 | (bit >= 32) ? bit - 32 : bit); |
ff8716f5 | 3262 | } |
c36a90ef ILT |
3263 | macro_build ((char *) NULL, counter, NULL, |
3264 | (shift >= 32) ? "dsrl32" : "dsrl", | |
3265 | "d,w,<", reg, reg, | |
3266 | (shift >= 32) ? shift - 32 : shift); | |
ff8716f5 JSC |
3267 | return; |
3268 | } | |
3269 | } | |
c36a90ef ILT |
3270 | |
3271 | /* Sign extend hi32 before calling load_register, because we can | |
3272 | generally get better code when we load a sign extended value. */ | |
3273 | if ((hi32.X_add_number & 0x80000000) != 0) | |
3274 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
d8a1c247 KR |
3275 | load_register (counter, reg, &hi32, 0); |
3276 | freg = reg; | |
3277 | } | |
847a01cd | 3278 | if ((lo32.X_add_number & 0xffff0000) == 0) |
d8a1c247 KR |
3279 | { |
3280 | if (freg != 0) | |
3281 | { | |
3282 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
3283 | freg, 0); | |
3284 | freg = reg; | |
3285 | } | |
3286 | } | |
847a01cd ILT |
3287 | else |
3288 | { | |
3289 | expressionS mid16; | |
3290 | ||
fb251650 ILT |
3291 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) |
3292 | { | |
3293 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3294 | (int) BFD_RELOC_HI16); | |
3295 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
ff8716f5 | 3296 | reg, 0); |
fb251650 ILT |
3297 | return; |
3298 | } | |
3299 | ||
d8a1c247 KR |
3300 | if (freg != 0) |
3301 | { | |
3302 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
3303 | freg, 16); | |
3304 | freg = reg; | |
3305 | } | |
847a01cd ILT |
3306 | mid16 = lo32; |
3307 | mid16.X_add_number >>= 16; | |
3308 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
d8a1c247 | 3309 | freg, (int) BFD_RELOC_LO16); |
847a01cd ILT |
3310 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
3311 | reg, 16); | |
d8a1c247 | 3312 | freg = reg; |
847a01cd ILT |
3313 | } |
3314 | if ((lo32.X_add_number & 0xffff) != 0) | |
d8a1c247 | 3315 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
847a01cd | 3316 | (int) BFD_RELOC_LO16); |
3d3c5039 ILT |
3317 | } |
3318 | ||
0dd2d296 ILT |
3319 | /* Load an address into a register. */ |
3320 | ||
3321 | static void | |
3322 | load_address (counter, reg, ep) | |
3323 | int *counter; | |
3324 | int reg; | |
3325 | expressionS *ep; | |
3326 | { | |
3327 | char *p; | |
3328 | ||
3329 | if (ep->X_op != O_constant | |
3330 | && ep->X_op != O_symbol) | |
3331 | { | |
48401fcf | 3332 | as_bad (_("expression too complex")); |
0dd2d296 ILT |
3333 | ep->X_op = O_constant; |
3334 | } | |
3335 | ||
3336 | if (ep->X_op == O_constant) | |
d9aba805 | 3337 | { |
d8a1c247 | 3338 | load_register (counter, reg, ep, 0); |
d9aba805 ILT |
3339 | return; |
3340 | } | |
3341 | ||
3342 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
3343 | { |
3344 | /* If this is a reference to a GP relative symbol, we want | |
3345 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3346 | Otherwise we want | |
04cb3372 | 3347 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
3348 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
3349 | If we have an addend, we always use the latter form. */ | |
7a15a226 | 3350 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 3351 | || nopic_need_relax (ep->X_add_symbol, 1)) |
0dd2d296 ILT |
3352 | p = NULL; |
3353 | else | |
3354 | { | |
8ea7f4e8 | 3355 | frag_grow (20); |
0dd2d296 | 3356 | macro_build ((char *) NULL, counter, ep, |
9a1f3160 JL |
3357 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3358 | || mips_opts.isa < 3) | |
3359 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3360 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
3361 | p = frag_var (rs_machine_dependent, 8, 0, | |
3c83da8a JW |
3362 | RELAX_ENCODE (4, 8, 0, 4, 0, |
3363 | mips_opts.warn_about_macros), | |
f59fb6ca | 3364 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
0dd2d296 ILT |
3365 | } |
3366 | macro_build_lui (p, counter, ep, reg); | |
3367 | if (p != NULL) | |
3368 | p += 4; | |
3369 | macro_build (p, counter, ep, | |
9a1f3160 JL |
3370 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3371 | || mips_opts.isa < 3) | |
3372 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3373 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3374 | } | |
fb251650 | 3375 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3376 | { |
3377 | expressionS ex; | |
3378 | ||
3379 | /* If this is a reference to an external symbol, we want | |
3380 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3381 | Otherwise we want | |
3382 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3383 | nop | |
3384 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 3385 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
3386 | ex.X_add_number = ep->X_add_number; |
3387 | ep->X_add_number = 0; | |
8ea7f4e8 | 3388 | frag_grow (20); |
0dd2d296 | 3389 | macro_build ((char *) NULL, counter, ep, |
9a1f3160 JL |
3390 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3391 | || mips_opts.isa < 3) | |
3392 | ? "lw" : "ld"), | |
0dd2d296 ILT |
3393 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3394 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3395 | p = frag_var (rs_machine_dependent, 4, 0, | |
3c83da8a | 3396 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), |
f59fb6ca | 3397 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
0dd2d296 | 3398 | macro_build (p, counter, ep, |
9a1f3160 JL |
3399 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3400 | || mips_opts.isa < 3) | |
3401 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3402 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3403 | if (ex.X_add_number != 0) | |
3404 | { | |
3405 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
48401fcf | 3406 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
0dd2d296 | 3407 | ex.X_op = O_constant; |
fb251650 | 3408 | macro_build ((char *) NULL, counter, &ex, |
9a1f3160 JL |
3409 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3410 | || mips_opts.isa < 3) | |
3411 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
3412 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3413 | } | |
3414 | } | |
3415 | else if (mips_pic == SVR4_PIC) | |
3416 | { | |
3417 | expressionS ex; | |
3418 | int off; | |
3419 | ||
3420 | /* This is the large GOT case. If this is a reference to an | |
3421 | external symbol, we want | |
3422 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3423 | addu $reg,$reg,$gp | |
3424 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3425 | Otherwise, for a reference to a local symbol, we want | |
3426 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3427 | nop | |
3428 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3429 | If there is a constant, it must be added in after. */ | |
3430 | ex.X_add_number = ep->X_add_number; | |
3431 | ep->X_add_number = 0; | |
3432 | if (reg_needs_delay (GP)) | |
3433 | off = 4; | |
3434 | else | |
3435 | off = 0; | |
3436 | frag_grow (32); | |
3437 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3438 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3439 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
9a1f3160 JL |
3440 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3441 | || mips_opts.isa < 3) | |
3442 | ? "addu" : "daddu"), | |
fb251650 ILT |
3443 | "d,v,t", reg, reg, GP); |
3444 | macro_build ((char *) NULL, counter, ep, | |
9a1f3160 JL |
3445 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3446 | || mips_opts.isa < 3) | |
3447 | ? "lw" : "ld"), | |
fb251650 ILT |
3448 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); |
3449 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3450 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3c83da8a | 3451 | mips_opts.warn_about_macros), |
f59fb6ca | 3452 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
fb251650 ILT |
3453 | if (off > 0) |
3454 | { | |
3455 | /* We need a nop before loading from $gp. This special | |
3456 | check is required because the lui which starts the main | |
3457 | instruction stream does not refer to $gp, and so will not | |
3458 | insert the nop which may be required. */ | |
3459 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3460 | p += 4; | |
3461 | } | |
3462 | macro_build (p, counter, ep, | |
9a1f3160 JL |
3463 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3464 | || mips_opts.isa < 3) | |
3465 | ? "lw" : "ld"), | |
fb251650 ILT |
3466 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3467 | p += 4; | |
3468 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3469 | p += 4; | |
3470 | macro_build (p, counter, ep, | |
9a1f3160 JL |
3471 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3472 | || mips_opts.isa < 3) | |
3473 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
3474 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3475 | if (ex.X_add_number != 0) | |
3476 | { | |
3477 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
48401fcf | 3478 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
fb251650 ILT |
3479 | ex.X_op = O_constant; |
3480 | macro_build ((char *) NULL, counter, &ex, | |
9a1f3160 JL |
3481 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3482 | || mips_opts.isa < 3) | |
3483 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3484 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3485 | } | |
d9aba805 ILT |
3486 | } |
3487 | else if (mips_pic == EMBEDDED_PIC) | |
3488 | { | |
3489 | /* We always do | |
3490 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3491 | */ | |
3492 | macro_build ((char *) NULL, counter, ep, | |
9a1f3160 JL |
3493 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3494 | || mips_opts.isa < 3) | |
3495 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
3496 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
3497 | } | |
3498 | else | |
3499 | abort (); | |
0dd2d296 ILT |
3500 | } |
3501 | ||
3d3c5039 ILT |
3502 | /* |
3503 | * Build macros | |
3504 | * This routine implements the seemingly endless macro or synthesized | |
3505 | * instructions and addressing modes in the mips assembly language. Many | |
3506 | * of these macros are simple and are similar to each other. These could | |
3507 | * probably be handled by some kind of table or grammer aproach instead of | |
3508 | * this verbose method. Others are not simple macros but are more like | |
3509 | * optimizing code generation. | |
3510 | * One interesting optimization is when several store macros appear | |
3511 | * consecutivly that would load AT with the upper half of the same address. | |
3512 | * The ensuing load upper instructions are ommited. This implies some kind | |
3513 | * of global optimization. We currently only optimize within a single macro. | |
3514 | * For many of the load and store macros if the address is specified as a | |
3515 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3516 | * first load register 'at' with zero and use it as the base register. The | |
3517 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3518 | * we're missing. | |
3519 | */ | |
3520 | static void | |
3521 | macro (ip) | |
3522 | struct mips_cl_insn *ip; | |
3523 | { | |
670a50eb ILT |
3524 | register int treg, sreg, dreg, breg; |
3525 | int tempreg; | |
3526 | int mask; | |
3527 | int icnt = 0; | |
3528 | int used_at; | |
670a50eb ILT |
3529 | expressionS expr1; |
3530 | const char *s; | |
8358c818 | 3531 | const char *s2; |
670a50eb | 3532 | const char *fmt; |
8358c818 ILT |
3533 | int likely = 0; |
3534 | int dbl = 0; | |
3535 | int coproc = 0; | |
b2b8c24e | 3536 | int lr = 0; |
40f0c904 | 3537 | int imm = 0; |
6e8dda9c | 3538 | offsetT maxnum; |
adcf2b9d | 3539 | int off; |
9226253a | 3540 | bfd_reloc_code_real_type r; |
0dd2d296 | 3541 | char *p; |
55933a58 | 3542 | int hold_mips_optimize; |
670a50eb | 3543 | |
3c83da8a | 3544 | assert (! mips_opts.mips16); |
cc5703cd | 3545 | |
670a50eb ILT |
3546 | treg = (ip->insn_opcode >> 16) & 0x1f; |
3547 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3548 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3549 | mask = ip->insn_mo->mask; | |
3550 | ||
5ac34ac3 ILT |
3551 | expr1.X_op = O_constant; |
3552 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
3553 | expr1.X_add_symbol = NULL; |
3554 | expr1.X_add_number = 1; | |
3555 | ||
3556 | switch (mask) | |
3557 | { | |
6e8dda9c ILT |
3558 | case M_DABS: |
3559 | dbl = 1; | |
3d3c5039 | 3560 | case M_ABS: |
6e8dda9c ILT |
3561 | /* bgez $a0,.+12 |
3562 | move v0,$a0 | |
3563 | sub v0,$zero,$a0 | |
3564 | */ | |
3d3c5039 | 3565 | |
fbcfacb7 | 3566 | mips_emit_delays (true); |
3c83da8a | 3567 | ++mips_opts.noreorder; |
0dd2d296 | 3568 | mips_any_noreorder = 1; |
3d3c5039 | 3569 | |
670a50eb | 3570 | expr1.X_add_number = 8; |
0dd2d296 | 3571 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 3572 | if (dreg == sreg) |
0dd2d296 | 3573 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 3574 | else |
0dd2d296 ILT |
3575 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
3576 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
3577 | dbl ? "dsub" : "sub", |
3578 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 3579 | |
3c83da8a | 3580 | --mips_opts.noreorder; |
670a50eb | 3581 | return; |
3d3c5039 ILT |
3582 | |
3583 | case M_ADD_I: | |
8358c818 ILT |
3584 | s = "addi"; |
3585 | s2 = "add"; | |
3586 | goto do_addi; | |
3d3c5039 | 3587 | case M_ADDU_I: |
8358c818 ILT |
3588 | s = "addiu"; |
3589 | s2 = "addu"; | |
3590 | goto do_addi; | |
3591 | case M_DADD_I: | |
6e8dda9c | 3592 | dbl = 1; |
8358c818 ILT |
3593 | s = "daddi"; |
3594 | s2 = "dadd"; | |
3595 | goto do_addi; | |
3596 | case M_DADDU_I: | |
6e8dda9c | 3597 | dbl = 1; |
8358c818 ILT |
3598 | s = "daddiu"; |
3599 | s2 = "daddu"; | |
3600 | do_addi: | |
5c6f5923 GRK |
3601 | if (imm_expr.X_op == O_constant |
3602 | && imm_expr.X_add_number >= -0x8000 | |
3603 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 3604 | { |
0dd2d296 | 3605 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 3606 | (int) BFD_RELOC_LO16); |
670a50eb | 3607 | return; |
3d3c5039 | 3608 | } |
d8a1c247 | 3609 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 3610 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3611 | break; |
3d3c5039 ILT |
3612 | |
3613 | case M_AND_I: | |
6e8dda9c ILT |
3614 | s = "andi"; |
3615 | s2 = "and"; | |
3616 | goto do_bit; | |
3d3c5039 | 3617 | case M_OR_I: |
6e8dda9c ILT |
3618 | s = "ori"; |
3619 | s2 = "or"; | |
3620 | goto do_bit; | |
3d3c5039 | 3621 | case M_NOR_I: |
6e8dda9c ILT |
3622 | s = ""; |
3623 | s2 = "nor"; | |
3624 | goto do_bit; | |
3d3c5039 | 3625 | case M_XOR_I: |
6e8dda9c ILT |
3626 | s = "xori"; |
3627 | s2 = "xor"; | |
3628 | do_bit: | |
5c6f5923 GRK |
3629 | if (imm_expr.X_op == O_constant |
3630 | && imm_expr.X_add_number >= 0 | |
3631 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 3632 | { |
6e8dda9c | 3633 | if (mask != M_NOR_I) |
0dd2d296 ILT |
3634 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
3635 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 3636 | else |
670a50eb | 3637 | { |
0dd2d296 ILT |
3638 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
3639 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 3640 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 3641 | treg, treg, 0); |
3d3c5039 | 3642 | } |
6e8dda9c | 3643 | return; |
3d3c5039 | 3644 | } |
6e8dda9c | 3645 | |
d8a1c247 | 3646 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3647 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3648 | break; |
3d3c5039 ILT |
3649 | |
3650 | case M_BEQ_I: | |
8358c818 ILT |
3651 | s = "beq"; |
3652 | goto beq_i; | |
3653 | case M_BEQL_I: | |
3654 | s = "beql"; | |
3655 | likely = 1; | |
3656 | goto beq_i; | |
3d3c5039 | 3657 | case M_BNE_I: |
8358c818 ILT |
3658 | s = "bne"; |
3659 | goto beq_i; | |
3660 | case M_BNEL_I: | |
3661 | s = "bnel"; | |
3662 | likely = 1; | |
3663 | beq_i: | |
5c6f5923 | 3664 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3665 | { |
0dd2d296 ILT |
3666 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
3667 | 0); | |
670a50eb ILT |
3668 | return; |
3669 | } | |
d8a1c247 | 3670 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3671 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 3672 | break; |
3d3c5039 | 3673 | |
8358c818 ILT |
3674 | case M_BGEL: |
3675 | likely = 1; | |
3d3c5039 | 3676 | case M_BGE: |
670a50eb ILT |
3677 | if (treg == 0) |
3678 | { | |
0dd2d296 | 3679 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3680 | likely ? "bgezl" : "bgez", |
3681 | "s,p", sreg); | |
670a50eb | 3682 | return; |
3d3c5039 | 3683 | } |
9a7d824a ILT |
3684 | if (sreg == 0) |
3685 | { | |
0dd2d296 | 3686 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3687 | likely ? "blezl" : "blez", |
3688 | "s,p", treg); | |
9a7d824a ILT |
3689 | return; |
3690 | } | |
0dd2d296 ILT |
3691 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3692 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3693 | likely ? "beql" : "beq", |
3694 | "s,t,p", AT, 0); | |
670a50eb | 3695 | break; |
3d3c5039 | 3696 | |
8358c818 ILT |
3697 | case M_BGTL_I: |
3698 | likely = 1; | |
3d3c5039 | 3699 | case M_BGT_I: |
9a7d824a | 3700 | /* check for > max integer */ |
6e8dda9c | 3701 | maxnum = 0x7fffffff; |
5c6f5923 | 3702 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3703 | { |
3704 | maxnum <<= 16; | |
3705 | maxnum |= 0xffff; | |
3706 | maxnum <<= 16; | |
3707 | maxnum |= 0xffff; | |
3708 | } | |
5c6f5923 GRK |
3709 | if (imm_expr.X_op == O_constant |
3710 | && imm_expr.X_add_number >= maxnum | |
3c83da8a | 3711 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a ILT |
3712 | { |
3713 | do_false: | |
3714 | /* result is always false */ | |
8358c818 ILT |
3715 | if (! likely) |
3716 | { | |
48401fcf | 3717 | as_warn (_("Branch %s is always false (nop)"), ip->insn_mo->name); |
0dd2d296 | 3718 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
3719 | } |
3720 | else | |
3721 | { | |
48401fcf | 3722 | as_warn (_("Branch likely %s is always false"), ip->insn_mo->name); |
0dd2d296 ILT |
3723 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
3724 | "s,t,p", 0, 0); | |
8358c818 | 3725 | } |
9a7d824a ILT |
3726 | return; |
3727 | } | |
5c6f5923 | 3728 | if (imm_expr.X_op != O_constant) |
48401fcf | 3729 | as_bad (_("Unsupported large constant")); |
670a50eb ILT |
3730 | imm_expr.X_add_number++; |
3731 | /* FALLTHROUGH */ | |
3d3c5039 | 3732 | case M_BGE_I: |
8358c818 ILT |
3733 | case M_BGEL_I: |
3734 | if (mask == M_BGEL_I) | |
3735 | likely = 1; | |
5c6f5923 | 3736 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3737 | { |
0dd2d296 | 3738 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3739 | likely ? "bgezl" : "bgez", |
3740 | "s,p", sreg); | |
670a50eb | 3741 | return; |
3d3c5039 | 3742 | } |
5c6f5923 | 3743 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3744 | { |
0dd2d296 | 3745 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3746 | likely ? "bgtzl" : "bgtz", |
3747 | "s,p", sreg); | |
670a50eb | 3748 | return; |
3d3c5039 | 3749 | } |
6e8dda9c | 3750 | maxnum = 0x7fffffff; |
5c6f5923 | 3751 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3752 | { |
3753 | maxnum <<= 16; | |
3754 | maxnum |= 0xffff; | |
3755 | maxnum <<= 16; | |
3756 | maxnum |= 0xffff; | |
3757 | } | |
3758 | maxnum = - maxnum - 1; | |
5c6f5923 GRK |
3759 | if (imm_expr.X_op == O_constant |
3760 | && imm_expr.X_add_number <= maxnum | |
3c83da8a | 3761 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a ILT |
3762 | { |
3763 | do_true: | |
3764 | /* result is always true */ | |
48401fcf | 3765 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); |
0dd2d296 | 3766 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
3767 | return; |
3768 | } | |
6e8dda9c | 3769 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3770 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3771 | likely ? "beql" : "beq", |
3772 | "s,t,p", AT, 0); | |
670a50eb | 3773 | break; |
3d3c5039 | 3774 | |
8358c818 ILT |
3775 | case M_BGEUL: |
3776 | likely = 1; | |
3d3c5039 | 3777 | case M_BGEU: |
670a50eb | 3778 | if (treg == 0) |
9a7d824a ILT |
3779 | goto do_true; |
3780 | if (sreg == 0) | |
670a50eb | 3781 | { |
0dd2d296 | 3782 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3783 | likely ? "beql" : "beq", |
3784 | "s,t,p", 0, treg); | |
670a50eb | 3785 | return; |
3d3c5039 | 3786 | } |
0dd2d296 ILT |
3787 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3788 | treg); | |
3789 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3790 | likely ? "beql" : "beq", |
3791 | "s,t,p", AT, 0); | |
670a50eb | 3792 | break; |
3d3c5039 | 3793 | |
8358c818 ILT |
3794 | case M_BGTUL_I: |
3795 | likely = 1; | |
9a7d824a | 3796 | case M_BGTU_I: |
5c6f5923 GRK |
3797 | if (sreg == 0 |
3798 | || (mips_opts.isa < 3 | |
3799 | && imm_expr.X_op == O_constant | |
3800 | && imm_expr.X_add_number == 0xffffffff)) | |
9a7d824a | 3801 | goto do_false; |
5c6f5923 | 3802 | if (imm_expr.X_op != O_constant) |
48401fcf | 3803 | as_bad (_("Unsupported large constant")); |
9a7d824a ILT |
3804 | imm_expr.X_add_number++; |
3805 | /* FALLTHROUGH */ | |
3d3c5039 | 3806 | case M_BGEU_I: |
8358c818 ILT |
3807 | case M_BGEUL_I: |
3808 | if (mask == M_BGEUL_I) | |
3809 | likely = 1; | |
5c6f5923 | 3810 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
9a7d824a | 3811 | goto do_true; |
5c6f5923 | 3812 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3813 | { |
0dd2d296 | 3814 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3815 | likely ? "bnel" : "bne", |
3816 | "s,t,p", sreg, 0); | |
670a50eb | 3817 | return; |
3d3c5039 | 3818 | } |
6e8dda9c | 3819 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3820 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3821 | likely ? "beql" : "beq", |
3822 | "s,t,p", AT, 0); | |
670a50eb | 3823 | break; |
3d3c5039 | 3824 | |
8358c818 ILT |
3825 | case M_BGTL: |
3826 | likely = 1; | |
3d3c5039 | 3827 | case M_BGT: |
670a50eb ILT |
3828 | if (treg == 0) |
3829 | { | |
0dd2d296 | 3830 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3831 | likely ? "bgtzl" : "bgtz", |
3832 | "s,p", sreg); | |
670a50eb | 3833 | return; |
3d3c5039 | 3834 | } |
9a7d824a ILT |
3835 | if (sreg == 0) |
3836 | { | |
0dd2d296 | 3837 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3838 | likely ? "bltzl" : "bltz", |
3839 | "s,p", treg); | |
9a7d824a ILT |
3840 | return; |
3841 | } | |
0dd2d296 ILT |
3842 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3843 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3844 | likely ? "bnel" : "bne", |
3845 | "s,t,p", AT, 0); | |
670a50eb | 3846 | break; |
3d3c5039 | 3847 | |
8358c818 ILT |
3848 | case M_BGTUL: |
3849 | likely = 1; | |
3d3c5039 | 3850 | case M_BGTU: |
670a50eb ILT |
3851 | if (treg == 0) |
3852 | { | |
0dd2d296 | 3853 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3854 | likely ? "bnel" : "bne", |
3855 | "s,t,p", sreg, 0); | |
670a50eb | 3856 | return; |
3d3c5039 | 3857 | } |
9a7d824a ILT |
3858 | if (sreg == 0) |
3859 | goto do_false; | |
0dd2d296 ILT |
3860 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3861 | sreg); | |
3862 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3863 | likely ? "bnel" : "bne", |
3864 | "s,t,p", AT, 0); | |
670a50eb | 3865 | break; |
3d3c5039 | 3866 | |
8358c818 ILT |
3867 | case M_BLEL: |
3868 | likely = 1; | |
3d3c5039 | 3869 | case M_BLE: |
670a50eb ILT |
3870 | if (treg == 0) |
3871 | { | |
0dd2d296 | 3872 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3873 | likely ? "blezl" : "blez", |
3874 | "s,p", sreg); | |
670a50eb ILT |
3875 | return; |
3876 | } | |
9a7d824a ILT |
3877 | if (sreg == 0) |
3878 | { | |
0dd2d296 | 3879 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3880 | likely ? "bgezl" : "bgez", |
3881 | "s,p", treg); | |
9a7d824a ILT |
3882 | return; |
3883 | } | |
0dd2d296 ILT |
3884 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3885 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3886 | likely ? "beql" : "beq", |
3887 | "s,t,p", AT, 0); | |
670a50eb | 3888 | break; |
3d3c5039 | 3889 | |
8358c818 ILT |
3890 | case M_BLEL_I: |
3891 | likely = 1; | |
3d3c5039 | 3892 | case M_BLE_I: |
6e8dda9c | 3893 | maxnum = 0x7fffffff; |
5c6f5923 | 3894 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3895 | { |
3896 | maxnum <<= 16; | |
3897 | maxnum |= 0xffff; | |
3898 | maxnum <<= 16; | |
3899 | maxnum |= 0xffff; | |
3900 | } | |
5c6f5923 GRK |
3901 | if (imm_expr.X_op == O_constant |
3902 | && imm_expr.X_add_number >= maxnum | |
3c83da8a | 3903 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a | 3904 | goto do_true; |
5c6f5923 | 3905 | if (imm_expr.X_op != O_constant) |
48401fcf | 3906 | as_bad (_("Unsupported large constant")); |
9a7d824a ILT |
3907 | imm_expr.X_add_number++; |
3908 | /* FALLTHROUGH */ | |
9a7d824a | 3909 | case M_BLT_I: |
8358c818 ILT |
3910 | case M_BLTL_I: |
3911 | if (mask == M_BLTL_I) | |
3912 | likely = 1; | |
5c6f5923 | 3913 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3914 | { |
0dd2d296 | 3915 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3916 | likely ? "bltzl" : "bltz", |
3917 | "s,p", sreg); | |
670a50eb ILT |
3918 | return; |
3919 | } | |
5c6f5923 | 3920 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3921 | { |
0dd2d296 | 3922 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3923 | likely ? "blezl" : "blez", |
3924 | "s,p", sreg); | |
670a50eb ILT |
3925 | return; |
3926 | } | |
6e8dda9c | 3927 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3928 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3929 | likely ? "bnel" : "bne", |
3930 | "s,t,p", AT, 0); | |
670a50eb | 3931 | break; |
3d3c5039 | 3932 | |
8358c818 ILT |
3933 | case M_BLEUL: |
3934 | likely = 1; | |
3d3c5039 | 3935 | case M_BLEU: |
670a50eb ILT |
3936 | if (treg == 0) |
3937 | { | |
0dd2d296 | 3938 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3939 | likely ? "beql" : "beq", |
3940 | "s,t,p", sreg, 0); | |
670a50eb | 3941 | return; |
3d3c5039 | 3942 | } |
9a7d824a ILT |
3943 | if (sreg == 0) |
3944 | goto do_true; | |
0dd2d296 ILT |
3945 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3946 | sreg); | |
3947 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3948 | likely ? "beql" : "beq", |
3949 | "s,t,p", AT, 0); | |
670a50eb | 3950 | break; |
3d3c5039 | 3951 | |
8358c818 ILT |
3952 | case M_BLEUL_I: |
3953 | likely = 1; | |
3d3c5039 | 3954 | case M_BLEU_I: |
5c6f5923 GRK |
3955 | if (sreg == 0 |
3956 | || (mips_opts.isa < 3 | |
3957 | && imm_expr.X_op == O_constant | |
3958 | && imm_expr.X_add_number == 0xffffffff)) | |
9a7d824a | 3959 | goto do_true; |
5c6f5923 | 3960 | if (imm_expr.X_op != O_constant) |
48401fcf | 3961 | as_bad (_("Unsupported large constant")); |
9a7d824a ILT |
3962 | imm_expr.X_add_number++; |
3963 | /* FALLTHROUGH */ | |
9a7d824a | 3964 | case M_BLTU_I: |
8358c818 ILT |
3965 | case M_BLTUL_I: |
3966 | if (mask == M_BLTUL_I) | |
3967 | likely = 1; | |
5c6f5923 | 3968 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
9a7d824a | 3969 | goto do_false; |
5c6f5923 | 3970 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3971 | { |
0dd2d296 | 3972 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3973 | likely ? "beql" : "beq", |
3974 | "s,t,p", sreg, 0); | |
670a50eb | 3975 | return; |
3d3c5039 | 3976 | } |
6e8dda9c | 3977 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3978 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3979 | likely ? "bnel" : "bne", |
3980 | "s,t,p", AT, 0); | |
670a50eb | 3981 | break; |
3d3c5039 | 3982 | |
8358c818 ILT |
3983 | case M_BLTL: |
3984 | likely = 1; | |
3d3c5039 | 3985 | case M_BLT: |
670a50eb ILT |
3986 | if (treg == 0) |
3987 | { | |
0dd2d296 | 3988 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3989 | likely ? "bltzl" : "bltz", |
3990 | "s,p", sreg); | |
670a50eb | 3991 | return; |
3d3c5039 | 3992 | } |
9a7d824a | 3993 | if (sreg == 0) |
670a50eb | 3994 | { |
0dd2d296 | 3995 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3996 | likely ? "bgtzl" : "bgtz", |
3997 | "s,p", treg); | |
670a50eb | 3998 | return; |
3d3c5039 | 3999 | } |
0dd2d296 ILT |
4000 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
4001 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
4002 | likely ? "bnel" : "bne", |
4003 | "s,t,p", AT, 0); | |
670a50eb | 4004 | break; |
3d3c5039 | 4005 | |
8358c818 ILT |
4006 | case M_BLTUL: |
4007 | likely = 1; | |
3d3c5039 | 4008 | case M_BLTU: |
670a50eb | 4009 | if (treg == 0) |
9a7d824a ILT |
4010 | goto do_false; |
4011 | if (sreg == 0) | |
670a50eb | 4012 | { |
0dd2d296 | 4013 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
4014 | likely ? "bnel" : "bne", |
4015 | "s,t,p", 0, treg); | |
670a50eb ILT |
4016 | return; |
4017 | } | |
0dd2d296 ILT |
4018 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
4019 | treg); | |
4020 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
4021 | likely ? "bnel" : "bne", |
4022 | "s,t,p", AT, 0); | |
670a50eb | 4023 | break; |
3d3c5039 | 4024 | |
8358c818 ILT |
4025 | case M_DDIV_3: |
4026 | dbl = 1; | |
3d3c5039 | 4027 | case M_DIV_3: |
8358c818 ILT |
4028 | s = "mflo"; |
4029 | goto do_div3; | |
4030 | case M_DREM_3: | |
4031 | dbl = 1; | |
3d3c5039 | 4032 | case M_REM_3: |
8358c818 ILT |
4033 | s = "mfhi"; |
4034 | do_div3: | |
670a50eb ILT |
4035 | if (treg == 0) |
4036 | { | |
48401fcf | 4037 | as_warn (_("Divide by zero.")); |
8ea7f4e8 ILT |
4038 | if (mips_trap) |
4039 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
4040 | else | |
d9c2c0c5 FCE |
4041 | /* start-sanitize-r5900 */ |
4042 | if (mips_5900) | |
4043 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); | |
4044 | else | |
4045 | /* end-sanitize-r5900 */ | |
4046 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
4047 | return; |
4048 | } | |
4049 | ||
fbcfacb7 | 4050 | mips_emit_delays (true); |
3c83da8a | 4051 | ++mips_opts.noreorder; |
0dd2d296 | 4052 | mips_any_noreorder = 1; |
8ea7f4e8 | 4053 | if (mips_trap) |
6c4b811d JL |
4054 | { |
4055 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
4056 | macro_build ((char *) NULL, &icnt, NULL, | |
4057 | dbl ? "ddiv" : "div", | |
4058 | "z,s,t", sreg, treg); | |
4059 | } | |
8ea7f4e8 ILT |
4060 | else |
4061 | { | |
4062 | expr1.X_add_number = 8; | |
4063 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
6c4b811d JL |
4064 | macro_build ((char *) NULL, &icnt, NULL, |
4065 | dbl ? "ddiv" : "div", | |
4066 | "z,s,t", sreg, treg); | |
d9c2c0c5 FCE |
4067 | /* start-sanitize-r5900 */ |
4068 | if (mips_5900) | |
4069 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); | |
4070 | else | |
4071 | /* end-sanitize-r5900 */ | |
4072 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
8ea7f4e8 | 4073 | } |
670a50eb | 4074 | expr1.X_add_number = -1; |
0dd2d296 | 4075 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 4076 | dbl ? "daddiu" : "addiu", |
9226253a | 4077 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 4078 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 4079 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
4080 | if (dbl) |
4081 | { | |
4082 | expr1.X_add_number = 1; | |
0dd2d296 | 4083 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 4084 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
4085 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
4086 | 31); | |
8358c818 ILT |
4087 | } |
4088 | else | |
4089 | { | |
4090 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
4091 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
4092 | (int) BFD_RELOC_HI16); | |
8358c818 | 4093 | } |
8ea7f4e8 | 4094 | if (mips_trap) |
edc8f76e JL |
4095 | { |
4096 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
4097 | /* We want to close the noreorder block as soon as possible, so | |
4098 | that later insns are available for delay slot filling. */ | |
4099 | --mips_opts.noreorder; | |
4100 | } | |
8ea7f4e8 ILT |
4101 | else |
4102 | { | |
4103 | expr1.X_add_number = 8; | |
4104 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
4105 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
d9c2c0c5 | 4106 | |
edc8f76e JL |
4107 | /* We want to close the noreorder block as soon as possible, so |
4108 | that later insns are available for delay slot filling. */ | |
4109 | --mips_opts.noreorder; | |
4110 | ||
d9c2c0c5 FCE |
4111 | /* start-sanitize-r5900 */ |
4112 | if (mips_5900) | |
4113 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 6); | |
4114 | else | |
4115 | /* end-sanitize-r5900 */ | |
4116 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
8ea7f4e8 | 4117 | } |
0dd2d296 | 4118 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 4119 | break; |
3d3c5039 ILT |
4120 | |
4121 | case M_DIV_3I: | |
8358c818 ILT |
4122 | s = "div"; |
4123 | s2 = "mflo"; | |
4124 | goto do_divi; | |
3d3c5039 | 4125 | case M_DIVU_3I: |
8358c818 ILT |
4126 | s = "divu"; |
4127 | s2 = "mflo"; | |
4128 | goto do_divi; | |
3d3c5039 | 4129 | case M_REM_3I: |
8358c818 ILT |
4130 | s = "div"; |
4131 | s2 = "mfhi"; | |
4132 | goto do_divi; | |
3d3c5039 | 4133 | case M_REMU_3I: |
8358c818 ILT |
4134 | s = "divu"; |
4135 | s2 = "mfhi"; | |
4136 | goto do_divi; | |
4137 | case M_DDIV_3I: | |
4138 | dbl = 1; | |
4139 | s = "ddiv"; | |
4140 | s2 = "mflo"; | |
4141 | goto do_divi; | |
4142 | case M_DDIVU_3I: | |
4143 | dbl = 1; | |
4144 | s = "ddivu"; | |
4145 | s2 = "mflo"; | |
4146 | goto do_divi; | |
4147 | case M_DREM_3I: | |
4148 | dbl = 1; | |
4149 | s = "ddiv"; | |
4150 | s2 = "mfhi"; | |
4151 | goto do_divi; | |
4152 | case M_DREMU_3I: | |
4153 | dbl = 1; | |
4154 | s = "ddivu"; | |
4155 | s2 = "mfhi"; | |
4156 | do_divi: | |
5c6f5923 | 4157 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 4158 | { |
48401fcf | 4159 | as_warn (_("Divide by zero.")); |
8ea7f4e8 ILT |
4160 | if (mips_trap) |
4161 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
4162 | else | |
d9c2c0c5 FCE |
4163 | /* start-sanitize-r5900 */ |
4164 | if (mips_5900) | |
4165 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); | |
4166 | else | |
4167 | /* end-sanitize-r5900 */ | |
4168 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
4169 | return; |
4170 | } | |
5c6f5923 | 4171 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 4172 | { |
8358c818 | 4173 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
4174 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
4175 | sreg); | |
3d3c5039 | 4176 | else |
0dd2d296 | 4177 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
4178 | return; |
4179 | } | |
5c6f5923 GRK |
4180 | if (imm_expr.X_op == O_constant |
4181 | && imm_expr.X_add_number == -1 | |
8358c818 ILT |
4182 | && s[strlen (s) - 1] != 'u') |
4183 | { | |
4184 | if (strcmp (s2, "mflo") == 0) | |
4185 | { | |
4186 | if (dbl) | |
0dd2d296 ILT |
4187 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
4188 | sreg); | |
8358c818 | 4189 | else |
0dd2d296 ILT |
4190 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
4191 | sreg); | |
8358c818 ILT |
4192 | } |
4193 | else | |
0dd2d296 | 4194 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
4195 | return; |
4196 | } | |
3d3c5039 | 4197 | |
d8a1c247 | 4198 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 ILT |
4199 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
4200 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
4201 | break; |
4202 | ||
4203 | case M_DIVU_3: | |
8358c818 ILT |
4204 | s = "divu"; |
4205 | s2 = "mflo"; | |
4206 | goto do_divu3; | |
670a50eb | 4207 | case M_REMU_3: |
8358c818 ILT |
4208 | s = "divu"; |
4209 | s2 = "mfhi"; | |
4210 | goto do_divu3; | |
4211 | case M_DDIVU_3: | |
4212 | s = "ddivu"; | |
4213 | s2 = "mflo"; | |
4214 | goto do_divu3; | |
4215 | case M_DREMU_3: | |
4216 | s = "ddivu"; | |
4217 | s2 = "mfhi"; | |
4218 | do_divu3: | |
fbcfacb7 | 4219 | mips_emit_delays (true); |
3c83da8a | 4220 | ++mips_opts.noreorder; |
0dd2d296 | 4221 | mips_any_noreorder = 1; |
8ea7f4e8 | 4222 | if (mips_trap) |
6c4b811d JL |
4223 | { |
4224 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
4225 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
edc8f76e JL |
4226 | /* We want to close the noreorder block as soon as possible, so |
4227 | that later insns are available for delay slot filling. */ | |
4228 | --mips_opts.noreorder; | |
6c4b811d | 4229 | } |
8ea7f4e8 ILT |
4230 | else |
4231 | { | |
4232 | expr1.X_add_number = 8; | |
4233 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
6c4b811d | 4234 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); |
edc8f76e JL |
4235 | |
4236 | /* We want to close the noreorder block as soon as possible, so | |
4237 | that later insns are available for delay slot filling. */ | |
4238 | --mips_opts.noreorder; | |
d9c2c0c5 FCE |
4239 | /* start-sanitize-r5900 */ |
4240 | if (mips_5900) | |
4241 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); | |
4242 | else | |
4243 | /* end-sanitize-r5900 */ | |
4244 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
8ea7f4e8 | 4245 | } |
0dd2d296 | 4246 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 4247 | return; |
3d3c5039 | 4248 | |
d8a1c247 KR |
4249 | case M_DLA_AB: |
4250 | dbl = 1; | |
0dd2d296 | 4251 | case M_LA_AB: |
d9aba805 ILT |
4252 | /* Load the address of a symbol into a register. If breg is not |
4253 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
4254 | |
4255 | /* When generating embedded PIC code, we permit expressions of | |
4256 | the form | |
4257 | la $4,foo-bar | |
4258 | where bar is an address in the .text section. These are used | |
4259 | when getting the addresses of functions. We don't permit | |
4260 | X_add_number to be non-zero, because if the symbol is | |
4261 | external the relaxing code needs to know that any addend is | |
4262 | purely the offset to X_op_symbol. */ | |
4263 | if (mips_pic == EMBEDDED_PIC | |
4264 | && offset_expr.X_op == O_subtract | |
4265 | && now_seg == text_section | |
847a01cd ILT |
4266 | && (offset_expr.X_op_symbol->sy_value.X_op == O_constant |
4267 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
4268 | : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol | |
4269 | && (S_GET_SEGMENT (offset_expr.X_op_symbol | |
4270 | ->sy_value.X_add_symbol) | |
4271 | == text_section))) | |
ecd4ca1c ILT |
4272 | && breg == 0 |
4273 | && offset_expr.X_add_number == 0) | |
4274 | { | |
4275 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4276 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
4277 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4278 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4279 | || mips_opts.isa < 3) | |
4280 | ? "addiu" : "daddiu"), | |
ecd4ca1c ILT |
4281 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); |
4282 | return; | |
4283 | } | |
4284 | ||
0dd2d296 ILT |
4285 | if (offset_expr.X_op != O_symbol |
4286 | && offset_expr.X_op != O_constant) | |
670a50eb | 4287 | { |
48401fcf | 4288 | as_bad (_("expression too complex")); |
0dd2d296 ILT |
4289 | offset_expr.X_op = O_constant; |
4290 | } | |
4291 | ||
4292 | if (treg == breg) | |
4293 | { | |
4294 | tempreg = AT; | |
4295 | used_at = 1; | |
3d3c5039 | 4296 | } |
670a50eb ILT |
4297 | else |
4298 | { | |
0dd2d296 ILT |
4299 | tempreg = treg; |
4300 | used_at = 0; | |
670a50eb | 4301 | } |
3d3c5039 | 4302 | |
5ac34ac3 | 4303 | if (offset_expr.X_op == O_constant) |
d8a1c247 | 4304 | load_register (&icnt, tempreg, &offset_expr, dbl); |
d9aba805 | 4305 | else if (mips_pic == NO_PIC) |
670a50eb | 4306 | { |
0dd2d296 ILT |
4307 | /* If this is a reference to an GP relative symbol, we want |
4308 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4309 | Otherwise we want | |
4310 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4311 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4312 | If we have a constant, we need two instructions anyhow, | |
4313 | so we may as well always use the latter form. */ | |
7a15a226 | 4314 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 4315 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
4316 | p = NULL; |
4317 | else | |
4318 | { | |
8ea7f4e8 | 4319 | frag_grow (20); |
0dd2d296 | 4320 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a1f3160 JL |
4321 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4322 | || mips_opts.isa < 3) | |
4323 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4324 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
4325 | p = frag_var (rs_machine_dependent, 8, 0, | |
4326 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3c83da8a | 4327 | mips_opts.warn_about_macros), |
f59fb6ca | 4328 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4329 | (char *) NULL); |
4330 | } | |
4331 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4332 | if (p != NULL) | |
4333 | p += 4; | |
4334 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
4335 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4336 | || mips_opts.isa < 3) | |
4337 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4338 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4339 | } | |
fb251650 | 4340 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
4341 | { |
4342 | /* If this is a reference to an external symbol, and there | |
4343 | is no constant, we want | |
4344 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4345 | For a local symbol, we want | |
4346 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4347 | nop | |
4348 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4349 | ||
4350 | If we have a small constant, and this is a reference to | |
4351 | an external symbol, we want | |
4352 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4353 | nop | |
4354 | addiu $tempreg,$tempreg,<constant> | |
4355 | For a local symbol, we want the same instruction | |
4356 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4357 | addiu instruction. | |
4358 | ||
4359 | If we have a large constant, and this is a reference to | |
4360 | an external symbol, we want | |
4361 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4362 | lui $at,<hiconstant> | |
4363 | addiu $at,$at,<loconstant> | |
4364 | addu $tempreg,$tempreg,$at | |
4365 | For a local symbol, we want the same instruction | |
4366 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4367 | addiu instruction. */ | |
4368 | expr1.X_add_number = offset_expr.X_add_number; | |
4369 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 4370 | frag_grow (32); |
0dd2d296 | 4371 | macro_build ((char *) NULL, &icnt, &offset_expr, |
d8a1c247 | 4372 | dbl ? "ld" : "lw", |
0dd2d296 ILT |
4373 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
4374 | if (expr1.X_add_number == 0) | |
4375 | { | |
4376 | int off; | |
4377 | ||
4378 | if (breg == 0) | |
4379 | off = 0; | |
4380 | else | |
4381 | { | |
4382 | /* We're going to put in an addu instruction using | |
4383 | tempreg, so we may as well insert the nop right | |
4384 | now. */ | |
4385 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4386 | "nop", ""); | |
4387 | off = 4; | |
4388 | } | |
4389 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4390 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4391 | (breg == 0 | |
3c83da8a | 4392 | ? mips_opts.warn_about_macros |
0dd2d296 | 4393 | : 0)), |
f59fb6ca | 4394 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4395 | (char *) NULL); |
4396 | if (breg == 0) | |
4397 | { | |
4398 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4399 | p += 4; | |
4400 | } | |
4401 | macro_build (p, &icnt, &expr1, | |
9a1f3160 JL |
4402 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4403 | || mips_opts.isa < 3) | |
4404 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4405 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4406 | /* FIXME: If breg == 0, and the next instruction uses | |
4407 | $tempreg, then if this variant case is used an extra | |
4408 | nop will be generated. */ | |
4409 | } | |
4410 | else if (expr1.X_add_number >= -0x8000 | |
4411 | && expr1.X_add_number < 0x8000) | |
4412 | { | |
4413 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4414 | "nop", ""); | |
4415 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4416 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4417 | || mips_opts.isa < 3) | |
4418 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4419 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4420 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4421 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
f59fb6ca | 4422 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4423 | (char *) NULL); |
4424 | } | |
4425 | else | |
4426 | { | |
4427 | int off1; | |
4428 | ||
4429 | /* If we are going to add in a base register, and the | |
4430 | target register and the base register are the same, | |
4431 | then we are using AT as a temporary register. Since | |
4432 | we want to load the constant into AT, we add our | |
4433 | current AT (from the global offset table) and the | |
4434 | register into the register now, and pretend we were | |
4435 | not using a base register. */ | |
4436 | if (breg != treg) | |
4437 | off1 = 0; | |
4438 | else | |
4439 | { | |
4440 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4441 | "nop", ""); | |
4442 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4443 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4444 | || mips_opts.isa < 3) | |
4445 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
4446 | "d,v,t", treg, AT, breg); |
4447 | breg = 0; | |
4448 | tempreg = treg; | |
4449 | off1 = -8; | |
4450 | } | |
4451 | ||
55933a58 ILT |
4452 | /* Set mips_optimize around the lui instruction to avoid |
4453 | inserting an unnecessary nop after the lw. */ | |
4454 | hold_mips_optimize = mips_optimize; | |
4455 | mips_optimize = 2; | |
0dd2d296 | 4456 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
4457 | mips_optimize = hold_mips_optimize; |
4458 | ||
0dd2d296 | 4459 | macro_build ((char *) NULL, &icnt, &expr1, |
9a1f3160 JL |
4460 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4461 | || mips_opts.isa < 3) | |
4462 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4463 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4464 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4465 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4466 | || mips_opts.isa < 3) | |
4467 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
4468 | "d,v,t", tempreg, tempreg, AT); |
4469 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4470 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
f59fb6ca | 4471 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4472 | (char *) NULL); |
4473 | used_at = 1; | |
4474 | } | |
670a50eb | 4475 | } |
fb251650 ILT |
4476 | else if (mips_pic == SVR4_PIC) |
4477 | { | |
4478 | int gpdel; | |
4479 | ||
4480 | /* This is the large GOT case. If this is a reference to an | |
4481 | external symbol, and there is no constant, we want | |
4482 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4483 | addu $tempreg,$tempreg,$gp | |
4484 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4485 | For a local symbol, we want | |
4486 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4487 | nop | |
4488 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4489 | ||
4490 | If we have a small constant, and this is a reference to | |
4491 | an external symbol, we want | |
4492 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4493 | addu $tempreg,$tempreg,$gp | |
4494 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4495 | nop | |
4496 | addiu $tempreg,$tempreg,<constant> | |
4497 | For a local symbol, we want | |
4498 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4499 | nop | |
4500 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4501 | ||
4502 | If we have a large constant, and this is a reference to | |
4503 | an external symbol, we want | |
4504 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4505 | addu $tempreg,$tempreg,$gp | |
4506 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4507 | lui $at,<hiconstant> | |
4508 | addiu $at,$at,<loconstant> | |
4509 | addu $tempreg,$tempreg,$at | |
4510 | For a local symbol, we want | |
4511 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4512 | lui $at,<hiconstant> | |
4513 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4514 | addu $tempreg,$tempreg,$at | |
4515 | */ | |
4516 | expr1.X_add_number = offset_expr.X_add_number; | |
4517 | offset_expr.X_add_number = 0; | |
4518 | frag_grow (52); | |
4519 | if (reg_needs_delay (GP)) | |
4520 | gpdel = 4; | |
4521 | else | |
4522 | gpdel = 0; | |
4523 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4524 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4525 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4526 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4527 | || mips_opts.isa < 3) | |
4528 | ? "addu" : "daddu"), | |
fb251650 ILT |
4529 | "d,v,t", tempreg, tempreg, GP); |
4530 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4531 | dbl ? "ld" : "lw", | |
4532 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
4533 | tempreg); | |
4534 | if (expr1.X_add_number == 0) | |
4535 | { | |
4536 | int off; | |
4537 | ||
4538 | if (breg == 0) | |
4539 | off = 0; | |
4540 | else | |
4541 | { | |
4542 | /* We're going to put in an addu instruction using | |
4543 | tempreg, so we may as well insert the nop right | |
4544 | now. */ | |
4545 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4546 | "nop", ""); | |
4547 | off = 4; | |
4548 | } | |
4549 | ||
4550 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4551 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
4552 | 8 + gpdel, 0, | |
4553 | (breg == 0 | |
3c83da8a | 4554 | ? mips_opts.warn_about_macros |
fb251650 | 4555 | : 0)), |
f59fb6ca | 4556 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4557 | (char *) NULL); |
4558 | } | |
4559 | else if (expr1.X_add_number >= -0x8000 | |
4560 | && expr1.X_add_number < 0x8000) | |
4561 | { | |
4562 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4563 | "nop", ""); | |
4564 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4565 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4566 | || mips_opts.isa < 3) | |
4567 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4568 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4569 | ||
4570 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4571 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4572 | (breg == 0 | |
3c83da8a | 4573 | ? mips_opts.warn_about_macros |
fb251650 | 4574 | : 0)), |
f59fb6ca | 4575 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4576 | (char *) NULL); |
4577 | } | |
4578 | else | |
4579 | { | |
4580 | int adj, dreg; | |
4581 | ||
4582 | /* If we are going to add in a base register, and the | |
4583 | target register and the base register are the same, | |
4584 | then we are using AT as a temporary register. Since | |
4585 | we want to load the constant into AT, we add our | |
4586 | current AT (from the global offset table) and the | |
4587 | register into the register now, and pretend we were | |
4588 | not using a base register. */ | |
4589 | if (breg != treg) | |
4590 | { | |
4591 | adj = 0; | |
4592 | dreg = tempreg; | |
4593 | } | |
4594 | else | |
4595 | { | |
4596 | assert (tempreg == AT); | |
4597 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4598 | "nop", ""); | |
4599 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4600 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4601 | || mips_opts.isa < 3) | |
4602 | ? "addu" : "daddu"), | |
fb251650 ILT |
4603 | "d,v,t", treg, AT, breg); |
4604 | dreg = treg; | |
4605 | adj = 8; | |
4606 | } | |
4607 | ||
4608 | /* Set mips_optimize around the lui instruction to avoid | |
4609 | inserting an unnecessary nop after the lw. */ | |
4610 | hold_mips_optimize = mips_optimize; | |
4611 | mips_optimize = 2; | |
4612 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4613 | mips_optimize = hold_mips_optimize; | |
4614 | ||
4615 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4616 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4617 | || mips_opts.isa < 3) | |
4618 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4619 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4620 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4621 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4622 | || mips_opts.isa < 3) | |
4623 | ? "addu" : "daddu"), | |
fb251650 ILT |
4624 | "d,v,t", dreg, dreg, AT); |
4625 | ||
4626 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4627 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4628 | 8 + gpdel, 0, | |
4629 | (breg == 0 | |
3c83da8a | 4630 | ? mips_opts.warn_about_macros |
fb251650 | 4631 | : 0)), |
f59fb6ca | 4632 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4633 | (char *) NULL); |
4634 | ||
4635 | used_at = 1; | |
4636 | } | |
4637 | ||
4638 | if (gpdel > 0) | |
4639 | { | |
4640 | /* This is needed because this instruction uses $gp, but | |
4641 | the first instruction on the main stream does not. */ | |
4642 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4643 | p += 4; | |
4644 | } | |
4645 | macro_build (p, &icnt, &offset_expr, | |
4646 | dbl ? "ld" : "lw", | |
4647 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4648 | p += 4; | |
4649 | if (expr1.X_add_number >= -0x8000 | |
4650 | && expr1.X_add_number < 0x8000) | |
4651 | { | |
4652 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4653 | p += 4; | |
4654 | macro_build (p, &icnt, &expr1, | |
9a1f3160 JL |
4655 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4656 | || mips_opts.isa < 3) | |
4657 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4658 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4659 | /* FIXME: If add_number is 0, and there was no base | |
4660 | register, the external symbol case ended with a load, | |
4661 | so if the symbol turns out to not be external, and | |
4662 | the next instruction uses tempreg, an unnecessary nop | |
4663 | will be inserted. */ | |
4664 | } | |
4665 | else | |
4666 | { | |
4667 | if (breg == treg) | |
4668 | { | |
4669 | /* We must add in the base register now, as in the | |
4670 | external symbol case. */ | |
4671 | assert (tempreg == AT); | |
4672 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4673 | p += 4; | |
4674 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4675 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4676 | || mips_opts.isa < 3) | |
4677 | ? "addu" : "daddu"), | |
fb251650 ILT |
4678 | "d,v,t", treg, AT, breg); |
4679 | p += 4; | |
4680 | tempreg = treg; | |
4681 | /* We set breg to 0 because we have arranged to add | |
4682 | it in in both cases. */ | |
4683 | breg = 0; | |
4684 | } | |
4685 | ||
4686 | macro_build_lui (p, &icnt, &expr1, AT); | |
4687 | p += 4; | |
4688 | macro_build (p, &icnt, &expr1, | |
9a1f3160 JL |
4689 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4690 | || mips_opts.isa < 3) | |
4691 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4692 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4693 | p += 4; | |
4694 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4695 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4696 | || mips_opts.isa < 3) | |
4697 | ? "addu" : "daddu"), | |
fb251650 ILT |
4698 | "d,v,t", tempreg, tempreg, AT); |
4699 | p += 4; | |
4700 | } | |
4701 | } | |
d9aba805 ILT |
4702 | else if (mips_pic == EMBEDDED_PIC) |
4703 | { | |
4704 | /* We use | |
4705 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4706 | */ | |
4707 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4708 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4709 | || mips_opts.isa < 3) | |
4710 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
4711 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
4712 | } | |
4713 | else | |
4714 | abort (); | |
0dd2d296 | 4715 | |
670a50eb | 4716 | if (breg != 0) |
0dd2d296 | 4717 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
4718 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4719 | || mips_opts.isa < 3) | |
4720 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
4721 | "d,v,t", treg, tempreg, breg); |
4722 | ||
4723 | if (! used_at) | |
4724 | return; | |
4725 | ||
4726 | break; | |
4727 | ||
4728 | case M_J_A: | |
4729 | /* The j instruction may not be used in PIC code, since it | |
4730 | requires an absolute address. We convert it to a b | |
4731 | instruction. */ | |
d9aba805 | 4732 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
4733 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
4734 | else | |
4735 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 4736 | return; |
3d3c5039 | 4737 | |
9226253a ILT |
4738 | /* The jal instructions must be handled as macros because when |
4739 | generating PIC code they expand to multi-instruction | |
4740 | sequences. Normally they are simple instructions. */ | |
4741 | case M_JAL_1: | |
4742 | dreg = RA; | |
4743 | /* Fall through. */ | |
4744 | case M_JAL_2: | |
d9aba805 ILT |
4745 | if (mips_pic == NO_PIC |
4746 | || mips_pic == EMBEDDED_PIC) | |
4747 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4748 | "d,s", dreg, sreg); | |
4749 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4750 | { |
d9aba805 | 4751 | if (sreg != PIC_CALL_REG) |
48401fcf | 4752 | as_warn (_("MIPS PIC call to register other than $25")); |
d9aba805 | 4753 | |
0dd2d296 ILT |
4754 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
4755 | "d,s", dreg, sreg); | |
d9aba805 | 4756 | if (mips_cprestore_offset < 0) |
48401fcf | 4757 | as_warn (_("No .cprestore pseudo-op used in PIC code")); |
d9aba805 ILT |
4758 | else |
4759 | { | |
4760 | expr1.X_add_number = mips_cprestore_offset; | |
4761 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4762 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4763 | || mips_opts.isa < 3) | |
4764 | ? "lw" : "ld"), | |
d9aba805 ILT |
4765 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); |
4766 | } | |
9226253a | 4767 | } |
0dd2d296 | 4768 | else |
d9aba805 ILT |
4769 | abort (); |
4770 | ||
9226253a ILT |
4771 | return; |
4772 | ||
4773 | case M_JAL_A: | |
d9aba805 ILT |
4774 | if (mips_pic == NO_PIC) |
4775 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4776 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4777 | { |
fb251650 ILT |
4778 | /* If this is a reference to an external symbol, and we are |
4779 | using a small GOT, we want | |
d9aba805 ILT |
4780 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
4781 | nop | |
4782 | jalr $25 | |
4783 | nop | |
4784 | lw $gp,cprestore($sp) | |
4785 | The cprestore value is set using the .cprestore | |
fb251650 ILT |
4786 | pseudo-op. If we are using a big GOT, we want |
4787 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4788 | addu $25,$25,$gp | |
4789 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4790 | nop | |
4791 | jalr $25 | |
4792 | nop | |
4793 | lw $gp,cprestore($sp) | |
4794 | If the symbol is not external, we want | |
d9aba805 ILT |
4795 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4796 | nop | |
4797 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4798 | jalr $25 | |
4799 | nop | |
fb251650 ILT |
4800 | lw $gp,cprestore($sp) */ |
4801 | frag_grow (40); | |
4802 | if (! mips_big_got) | |
4803 | { | |
4804 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4805 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4806 | || mips_opts.isa < 3) | |
4807 | ? "lw" : "ld"), | |
fb251650 ILT |
4808 | "t,o(b)", PIC_CALL_REG, |
4809 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4810 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4811 | "nop", ""); | |
4812 | p = frag_var (rs_machine_dependent, 4, 0, | |
4813 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
f59fb6ca ILT |
4814 | offset_expr.X_add_symbol, (offsetT) 0, |
4815 | (char *) NULL); | |
fb251650 ILT |
4816 | } |
4817 | else | |
4818 | { | |
4819 | int gpdel; | |
4820 | ||
4821 | if (reg_needs_delay (GP)) | |
4822 | gpdel = 4; | |
4823 | else | |
4824 | gpdel = 0; | |
4825 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4826 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4827 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4828 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4829 | || mips_opts.isa < 3) | |
4830 | ? "addu" : "daddu"), | |
fb251650 ILT |
4831 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); |
4832 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4833 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4834 | || mips_opts.isa < 3) | |
4835 | ? "lw" : "ld"), | |
fb251650 ILT |
4836 | "t,o(b)", PIC_CALL_REG, |
4837 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4838 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4839 | "nop", ""); | |
4840 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4841 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4842 | 0, 0), | |
f59fb6ca ILT |
4843 | offset_expr.X_add_symbol, (offsetT) 0, |
4844 | (char *) NULL); | |
fb251650 ILT |
4845 | if (gpdel > 0) |
4846 | { | |
4847 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4848 | p += 4; | |
4849 | } | |
4850 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
4851 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4852 | || mips_opts.isa < 3) | |
4853 | ? "lw" : "ld"), | |
fb251650 ILT |
4854 | "t,o(b)", PIC_CALL_REG, |
4855 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4856 | p += 4; | |
4857 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4858 | p += 4; | |
4859 | } | |
d9aba805 | 4860 | macro_build (p, &icnt, &offset_expr, |
9a1f3160 JL |
4861 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4862 | || mips_opts.isa < 3) | |
4863 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
4864 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
4865 | (int) BFD_RELOC_LO16); | |
4866 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4867 | "jalr", "s", PIC_CALL_REG); | |
4868 | if (mips_cprestore_offset < 0) | |
48401fcf | 4869 | as_warn (_("No .cprestore pseudo-op used in PIC code")); |
d9aba805 ILT |
4870 | else |
4871 | { | |
3c83da8a | 4872 | if (mips_opts.noreorder) |
d9aba805 ILT |
4873 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4874 | "nop", ""); | |
4875 | expr1.X_add_number = mips_cprestore_offset; | |
4876 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4877 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4878 | || mips_opts.isa < 3) | |
4879 | ? "lw" : "ld"), | |
d9aba805 ILT |
4880 | "t,o(b)", GP, (int) BFD_RELOC_LO16, |
4881 | mips_frame_reg); | |
4882 | } | |
0dd2d296 | 4883 | } |
d9aba805 | 4884 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
4885 | { |
4886 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4887 | /* The linker may expand the call to a longer sequence which | |
4888 | uses $at, so we must break rather than return. */ | |
4889 | break; | |
4890 | } | |
d9aba805 ILT |
4891 | else |
4892 | abort (); | |
4893 | ||
9226253a ILT |
4894 | return; |
4895 | ||
3d3c5039 | 4896 | case M_LB_AB: |
670a50eb ILT |
4897 | s = "lb"; |
4898 | goto ld; | |
3d3c5039 | 4899 | case M_LBU_AB: |
670a50eb ILT |
4900 | s = "lbu"; |
4901 | goto ld; | |
3d3c5039 | 4902 | case M_LH_AB: |
670a50eb ILT |
4903 | s = "lh"; |
4904 | goto ld; | |
3d3c5039 | 4905 | case M_LHU_AB: |
670a50eb ILT |
4906 | s = "lhu"; |
4907 | goto ld; | |
3d3c5039 | 4908 | case M_LW_AB: |
670a50eb ILT |
4909 | s = "lw"; |
4910 | goto ld; | |
3d3c5039 | 4911 | case M_LWC0_AB: |
670a50eb | 4912 | s = "lwc0"; |
efec4a28 | 4913 | /* Itbl support may require additional care here. */ |
8358c818 | 4914 | coproc = 1; |
670a50eb | 4915 | goto ld; |
3d3c5039 | 4916 | case M_LWC1_AB: |
670a50eb | 4917 | s = "lwc1"; |
efec4a28 | 4918 | /* Itbl support may require additional care here. */ |
8358c818 | 4919 | coproc = 1; |
670a50eb | 4920 | goto ld; |
3d3c5039 | 4921 | case M_LWC2_AB: |
670a50eb | 4922 | s = "lwc2"; |
efec4a28 | 4923 | /* Itbl support may require additional care here. */ |
8358c818 | 4924 | coproc = 1; |
670a50eb | 4925 | goto ld; |
3d3c5039 | 4926 | case M_LWC3_AB: |
670a50eb | 4927 | s = "lwc3"; |
efec4a28 | 4928 | /* Itbl support may require additional care here. */ |
8358c818 | 4929 | coproc = 1; |
670a50eb | 4930 | goto ld; |
3d3c5039 | 4931 | case M_LWL_AB: |
670a50eb | 4932 | s = "lwl"; |
b2b8c24e | 4933 | lr = 1; |
670a50eb | 4934 | goto ld; |
3d3c5039 | 4935 | case M_LWR_AB: |
670a50eb | 4936 | s = "lwr"; |
b2b8c24e | 4937 | lr = 1; |
8358c818 ILT |
4938 | goto ld; |
4939 | case M_LDC1_AB: | |
1c6f3441 ILT |
4940 | if (mips_4650) |
4941 | { | |
48401fcf | 4942 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
4943 | return; |
4944 | } | |
8358c818 | 4945 | s = "ldc1"; |
efec4a28 | 4946 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4947 | coproc = 1; |
4948 | goto ld; | |
4949 | case M_LDC2_AB: | |
4950 | s = "ldc2"; | |
efec4a28 | 4951 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4952 | coproc = 1; |
4953 | goto ld; | |
4954 | case M_LDC3_AB: | |
4955 | s = "ldc3"; | |
efec4a28 | 4956 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4957 | coproc = 1; |
4958 | goto ld; | |
4959 | case M_LDL_AB: | |
4960 | s = "ldl"; | |
b2b8c24e | 4961 | lr = 1; |
8358c818 ILT |
4962 | goto ld; |
4963 | case M_LDR_AB: | |
4964 | s = "ldr"; | |
b2b8c24e | 4965 | lr = 1; |
8358c818 ILT |
4966 | goto ld; |
4967 | case M_LL_AB: | |
4968 | s = "ll"; | |
4969 | goto ld; | |
4970 | case M_LLD_AB: | |
4971 | s = "lld"; | |
4972 | goto ld; | |
4973 | case M_LWU_AB: | |
4974 | s = "lwu"; | |
3d3c5039 | 4975 | ld: |
b2b8c24e | 4976 | if (breg == treg || coproc || lr) |
670a50eb ILT |
4977 | { |
4978 | tempreg = AT; | |
4979 | used_at = 1; | |
4980 | } | |
4981 | else | |
4982 | { | |
4983 | tempreg = treg; | |
4984 | used_at = 0; | |
4985 | } | |
4986 | goto ld_st; | |
3d3c5039 | 4987 | case M_SB_AB: |
670a50eb ILT |
4988 | s = "sb"; |
4989 | goto st; | |
3d3c5039 | 4990 | case M_SH_AB: |
670a50eb ILT |
4991 | s = "sh"; |
4992 | goto st; | |
3d3c5039 | 4993 | case M_SW_AB: |
670a50eb ILT |
4994 | s = "sw"; |
4995 | goto st; | |
3d3c5039 | 4996 | case M_SWC0_AB: |
670a50eb | 4997 | s = "swc0"; |
efec4a28 | 4998 | /* Itbl support may require additional care here. */ |
8358c818 | 4999 | coproc = 1; |
670a50eb | 5000 | goto st; |
3d3c5039 | 5001 | case M_SWC1_AB: |
670a50eb | 5002 | s = "swc1"; |
efec4a28 | 5003 | /* Itbl support may require additional care here. */ |
8358c818 | 5004 | coproc = 1; |
670a50eb | 5005 | goto st; |
3d3c5039 | 5006 | case M_SWC2_AB: |
670a50eb | 5007 | s = "swc2"; |
efec4a28 | 5008 | /* Itbl support may require additional care here. */ |
8358c818 | 5009 | coproc = 1; |
670a50eb | 5010 | goto st; |
3d3c5039 | 5011 | case M_SWC3_AB: |
670a50eb | 5012 | s = "swc3"; |
efec4a28 | 5013 | /* Itbl support may require additional care here. */ |
8358c818 | 5014 | coproc = 1; |
670a50eb | 5015 | goto st; |
3d3c5039 | 5016 | case M_SWL_AB: |
670a50eb ILT |
5017 | s = "swl"; |
5018 | goto st; | |
3d3c5039 | 5019 | case M_SWR_AB: |
670a50eb | 5020 | s = "swr"; |
8358c818 ILT |
5021 | goto st; |
5022 | case M_SC_AB: | |
5023 | s = "sc"; | |
5024 | goto st; | |
5025 | case M_SCD_AB: | |
5026 | s = "scd"; | |
5027 | goto st; | |
5028 | case M_SDC1_AB: | |
1c6f3441 ILT |
5029 | if (mips_4650) |
5030 | { | |
48401fcf | 5031 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
5032 | return; |
5033 | } | |
8358c818 ILT |
5034 | s = "sdc1"; |
5035 | coproc = 1; | |
efec4a28 | 5036 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
5037 | goto st; |
5038 | case M_SDC2_AB: | |
5039 | s = "sdc2"; | |
efec4a28 | 5040 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
5041 | coproc = 1; |
5042 | goto st; | |
5043 | case M_SDC3_AB: | |
5044 | s = "sdc3"; | |
efec4a28 | 5045 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
5046 | coproc = 1; |
5047 | goto st; | |
5048 | case M_SDL_AB: | |
5049 | s = "sdl"; | |
5050 | goto st; | |
5051 | case M_SDR_AB: | |
5052 | s = "sdr"; | |
3d3c5039 | 5053 | st: |
670a50eb ILT |
5054 | tempreg = AT; |
5055 | used_at = 1; | |
3d3c5039 | 5056 | ld_st: |
efec4a28 | 5057 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
5058 | if (mask == M_LWC1_AB |
5059 | || mask == M_SWC1_AB | |
8358c818 | 5060 | || mask == M_LDC1_AB |
0dd2d296 ILT |
5061 | || mask == M_SDC1_AB |
5062 | || mask == M_L_DAB | |
5063 | || mask == M_S_DAB) | |
670a50eb | 5064 | fmt = "T,o(b)"; |
8358c818 | 5065 | else if (coproc) |
19ed8960 | 5066 | fmt = "E,o(b)"; |
670a50eb ILT |
5067 | else |
5068 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
5069 | |
5070 | if (offset_expr.X_op != O_constant | |
5071 | && offset_expr.X_op != O_symbol) | |
5072 | { | |
48401fcf | 5073 | as_bad (_("expression too complex")); |
0dd2d296 ILT |
5074 | offset_expr.X_op = O_constant; |
5075 | } | |
5076 | ||
5077 | /* A constant expression in PIC code can be handled just as it | |
5078 | is in non PIC code. */ | |
d9aba805 | 5079 | if (mips_pic == NO_PIC |
0dd2d296 | 5080 | || offset_expr.X_op == O_constant) |
670a50eb | 5081 | { |
0dd2d296 ILT |
5082 | /* If this is a reference to a GP relative symbol, and there |
5083 | is no base register, we want | |
5084 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 5085 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
5086 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
5087 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5088 | If we have a constant, we need two instructions anyhow, | |
5089 | so we always use the latter form. | |
5090 | ||
5091 | If we have a base register, and this is a reference to a | |
5092 | GP relative symbol, we want | |
5093 | addu $tempreg,$breg,$gp | |
5094 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
5095 | Otherwise we want | |
5096 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5097 | addu $tempreg,$tempreg,$breg | |
5098 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5099 | With a constant we always use the latter case. */ | |
670a50eb ILT |
5100 | if (breg == 0) |
5101 | { | |
7a15a226 | 5102 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 5103 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
5104 | p = NULL; |
5105 | else | |
5106 | { | |
8ea7f4e8 | 5107 | frag_grow (20); |
0dd2d296 ILT |
5108 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5109 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
5110 | p = frag_var (rs_machine_dependent, 8, 0, | |
5111 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3c83da8a JW |
5112 | (mips_opts.warn_about_macros |
5113 | || (used_at | |
5114 | && mips_opts.noat))), | |
f59fb6ca | 5115 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5116 | (char *) NULL); |
8197b589 | 5117 | used_at = 0; |
0dd2d296 ILT |
5118 | } |
5119 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5120 | if (p != NULL) | |
5121 | p += 4; | |
5122 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5123 | (int) BFD_RELOC_LO16, tempreg); | |
5124 | } | |
5125 | else | |
5126 | { | |
7a15a226 | 5127 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 5128 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
5129 | p = NULL; |
5130 | else | |
5131 | { | |
8ea7f4e8 | 5132 | frag_grow (28); |
0dd2d296 | 5133 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
5134 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5135 | || mips_opts.isa < 3) | |
5136 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
5137 | "d,v,t", tempreg, breg, GP); |
5138 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5139 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5140 | p = frag_var (rs_machine_dependent, 12, 0, | |
5141 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
f59fb6ca | 5142 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
5143 | (char *) NULL); |
5144 | } | |
5145 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5146 | if (p != NULL) | |
5147 | p += 4; | |
5148 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5149 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5150 | || mips_opts.isa < 3) | |
5151 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
5152 | "d,v,t", tempreg, tempreg, breg); |
5153 | if (p != NULL) | |
5154 | p += 4; | |
5155 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5156 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 5157 | } |
670a50eb | 5158 | } |
fb251650 | 5159 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 5160 | { |
0dd2d296 ILT |
5161 | /* If this is a reference to an external symbol, we want |
5162 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5163 | nop | |
5164 | <op> $treg,0($tempreg) | |
5165 | Otherwise we want | |
5166 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5167 | nop | |
5168 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5169 | <op> $treg,0($tempreg) | |
5170 | If there is a base register, we add it to $tempreg before | |
5171 | the <op>. If there is a constant, we stick it in the | |
5172 | <op> instruction. We don't handle constants larger than | |
5173 | 16 bits, because we have no way to load the upper 16 bits | |
5174 | (actually, we could handle them for the subset of cases | |
5175 | in which we are not using $at). */ | |
5176 | assert (offset_expr.X_op == O_symbol); | |
5177 | expr1.X_add_number = offset_expr.X_add_number; | |
5178 | offset_expr.X_add_number = 0; | |
5179 | if (expr1.X_add_number < -0x8000 | |
5180 | || expr1.X_add_number >= 0x8000) | |
48401fcf | 5181 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
8ea7f4e8 | 5182 | frag_grow (20); |
0dd2d296 | 5183 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a1f3160 JL |
5184 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5185 | || mips_opts.isa < 3) | |
5186 | ? "lw" : "ld"), | |
0dd2d296 ILT |
5187 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
5188 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5189 | p = frag_var (rs_machine_dependent, 4, 0, | |
5190 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
f59fb6ca | 5191 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
5192 | (char *) NULL); |
5193 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5194 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5195 | || mips_opts.isa < 3) | |
5196 | ? "addiu" : "daddiu"), | |
0dd2d296 | 5197 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
670a50eb | 5198 | if (breg != 0) |
0dd2d296 | 5199 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
5200 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5201 | || mips_opts.isa < 3) | |
5202 | ? "addu" : "daddu"), | |
6e8dda9c | 5203 | "d,v,t", tempreg, tempreg, breg); |
0dd2d296 ILT |
5204 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
5205 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 5206 | } |
fb251650 ILT |
5207 | else if (mips_pic == SVR4_PIC) |
5208 | { | |
5209 | int gpdel; | |
5210 | ||
5211 | /* If this is a reference to an external symbol, we want | |
5212 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5213 | addu $tempreg,$tempreg,$gp | |
5214 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5215 | <op> $treg,0($tempreg) | |
5216 | Otherwise we want | |
5217 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5218 | nop | |
5219 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5220 | <op> $treg,0($tempreg) | |
5221 | If there is a base register, we add it to $tempreg before | |
5222 | the <op>. If there is a constant, we stick it in the | |
5223 | <op> instruction. We don't handle constants larger than | |
5224 | 16 bits, because we have no way to load the upper 16 bits | |
5225 | (actually, we could handle them for the subset of cases | |
5226 | in which we are not using $at). */ | |
5227 | assert (offset_expr.X_op == O_symbol); | |
5228 | expr1.X_add_number = offset_expr.X_add_number; | |
5229 | offset_expr.X_add_number = 0; | |
5230 | if (expr1.X_add_number < -0x8000 | |
5231 | || expr1.X_add_number >= 0x8000) | |
48401fcf | 5232 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
fb251650 ILT |
5233 | if (reg_needs_delay (GP)) |
5234 | gpdel = 4; | |
5235 | else | |
5236 | gpdel = 0; | |
5237 | frag_grow (36); | |
5238 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5239 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5240 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5241 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5242 | || mips_opts.isa < 3) | |
5243 | ? "addu" : "daddu"), | |
fb251650 ILT |
5244 | "d,v,t", tempreg, tempreg, GP); |
5245 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5246 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5247 | || mips_opts.isa < 3) | |
5248 | ? "lw" : "ld"), | |
867a58b3 ILT |
5249 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
5250 | tempreg); | |
fb251650 ILT |
5251 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
5252 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
f59fb6ca | 5253 | offset_expr.X_add_symbol, (offsetT) 0, (char *) NULL); |
fb251650 ILT |
5254 | if (gpdel > 0) |
5255 | { | |
5256 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5257 | p += 4; | |
5258 | } | |
5259 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5260 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5261 | || mips_opts.isa < 3) | |
5262 | ? "lw" : "ld"), | |
867a58b3 | 5263 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
fb251650 ILT |
5264 | p += 4; |
5265 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5266 | p += 4; | |
5267 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5268 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5269 | || mips_opts.isa < 3) | |
5270 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
5271 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5272 | if (breg != 0) | |
5273 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5274 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5275 | || mips_opts.isa < 3) | |
5276 | ? "addu" : "daddu"), | |
fb251650 ILT |
5277 | "d,v,t", tempreg, tempreg, breg); |
5278 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5279 | (int) BFD_RELOC_LO16, tempreg); | |
5280 | } | |
d9aba805 ILT |
5281 | else if (mips_pic == EMBEDDED_PIC) |
5282 | { | |
5283 | /* If there is no base register, we want | |
5284 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5285 | If there is a base register, we want | |
5286 | addu $tempreg,$breg,$gp | |
5287 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
5288 | */ | |
5289 | assert (offset_expr.X_op == O_symbol); | |
5290 | if (breg == 0) | |
5291 | { | |
5292 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5293 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
5294 | used_at = 0; | |
5295 | } | |
5296 | else | |
5297 | { | |
5298 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5299 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5300 | || mips_opts.isa < 3) | |
5301 | ? "addu" : "daddu"), | |
d9aba805 ILT |
5302 | "d,v,t", tempreg, breg, GP); |
5303 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5304 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5305 | } | |
5306 | } | |
5307 | else | |
5308 | abort (); | |
0dd2d296 ILT |
5309 | |
5310 | if (! used_at) | |
5311 | return; | |
5312 | ||
5313 | break; | |
3d3c5039 ILT |
5314 | |
5315 | case M_LI: | |
19ed8960 | 5316 | case M_LI_S: |
d8a1c247 KR |
5317 | load_register (&icnt, treg, &imm_expr, 0); |
5318 | return; | |
5319 | ||
5320 | case M_DLI: | |
5321 | load_register (&icnt, treg, &imm_expr, 1); | |
670a50eb | 5322 | return; |
3d3c5039 | 5323 | |
0dd2d296 | 5324 | case M_LI_SS: |
55933a58 | 5325 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 5326 | { |
d8a1c247 | 5327 | load_register (&icnt, AT, &imm_expr, 0); |
d2c71068 ILT |
5328 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
5329 | "mtc1", "t,G", AT, treg); | |
5330 | break; | |
0dd2d296 | 5331 | } |
d9aba805 | 5332 | else |
d2c71068 | 5333 | { |
55933a58 ILT |
5334 | assert (offset_expr.X_op == O_symbol |
5335 | && strcmp (segment_name (S_GET_SEGMENT | |
5336 | (offset_expr.X_add_symbol)), | |
5337 | ".lit4") == 0 | |
5338 | && offset_expr.X_add_number == 0); | |
5339 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
5340 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
5341 | return; |
5342 | } | |
0dd2d296 | 5343 | |
3d3c5039 | 5344 | case M_LI_D: |
a5586bdc ILT |
5345 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is |
5346 | the entire value, and in mips1 mode it is the high order 32 | |
5347 | bits of the value and the low order 32 bits are either zero | |
5348 | or in offset_expr. */ | |
5349 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5350 | { | |
517640d9 ILT |
5351 | if (mips_opts.isa >= 3) |
5352 | load_register (&icnt, treg, &imm_expr, 1); | |
5353 | else | |
a5586bdc | 5354 | { |
517640d9 ILT |
5355 | int hreg, lreg; |
5356 | ||
5357 | if (target_big_endian) | |
5358 | { | |
5359 | hreg = treg; | |
5360 | lreg = treg + 1; | |
5361 | } | |
a5586bdc ILT |
5362 | else |
5363 | { | |
517640d9 ILT |
5364 | hreg = treg + 1; |
5365 | lreg = treg; | |
5366 | } | |
5367 | ||
5368 | if (hreg <= 31) | |
5369 | load_register (&icnt, hreg, &imm_expr, 0); | |
5370 | if (lreg <= 31) | |
5371 | { | |
5372 | if (offset_expr.X_op == O_absent) | |
5373 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", | |
5374 | lreg, 0); | |
5375 | else | |
5376 | { | |
5377 | assert (offset_expr.X_op == O_constant); | |
5378 | load_register (&icnt, lreg, &offset_expr, 0); | |
5379 | } | |
a5586bdc ILT |
5380 | } |
5381 | } | |
5382 | return; | |
5383 | } | |
5384 | ||
d9aba805 ILT |
5385 | /* We know that sym is in the .rdata section. First we get the |
5386 | upper 16 bits of the address. */ | |
5387 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
5388 | { |
5389 | /* FIXME: This won't work for a 64 bit address. */ | |
5390 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5391 | } | |
d9aba805 | 5392 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
5393 | { |
5394 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5395 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5396 | || mips_opts.isa < 3) | |
5397 | ? "lw" : "ld"), | |
0dd2d296 ILT |
5398 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5399 | } | |
d9aba805 ILT |
5400 | else if (mips_pic == EMBEDDED_PIC) |
5401 | { | |
5402 | /* For embedded PIC we pick up the entire address off $gp in | |
5403 | a single instruction. */ | |
5404 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5405 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5406 | || mips_opts.isa < 3) | |
5407 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
5408 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); |
5409 | offset_expr.X_op = O_constant; | |
5410 | offset_expr.X_add_number = 0; | |
5411 | } | |
5412 | else | |
5413 | abort (); | |
5414 | ||
0dd2d296 | 5415 | /* Now we load the register(s). */ |
3c83da8a | 5416 | if (mips_opts.isa >= 3) |
0dd2d296 ILT |
5417 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
5418 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
5419 | else |
5420 | { | |
0dd2d296 ILT |
5421 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
5422 | treg, (int) BFD_RELOC_LO16, AT); | |
5423 | if (treg != 31) | |
5424 | { | |
5425 | /* FIXME: How in the world do we deal with the possible | |
5426 | overflow here? */ | |
5427 | offset_expr.X_add_number += 4; | |
5428 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5429 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
5430 | } | |
8358c818 | 5431 | } |
d2c71068 ILT |
5432 | |
5433 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5434 | does not become a variant frag. */ | |
5435 | frag_wane (frag_now); | |
5436 | frag_new (0); | |
5437 | ||
670a50eb | 5438 | break; |
3d3c5039 ILT |
5439 | |
5440 | case M_LI_DD: | |
a5586bdc ILT |
5441 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is |
5442 | the entire value, and in mips1 mode it is the high order 32 | |
5443 | bits of the value and the low order 32 bits are either zero | |
5444 | or in offset_expr. */ | |
5445 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5446 | { | |
5447 | load_register (&icnt, AT, &imm_expr, mips_opts.isa >= 3); | |
5448 | if (mips_opts.isa >= 3) | |
5449 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5450 | "dmtc1", "t,S", AT, treg); | |
5451 | else | |
5452 | { | |
5453 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5454 | "mtc1", "t,G", AT, treg + 1); | |
5455 | if (offset_expr.X_op == O_absent) | |
5456 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5457 | "mtc1", "t,G", 0, treg); | |
5458 | else | |
5459 | { | |
5460 | assert (offset_expr.X_op == O_constant); | |
5461 | load_register (&icnt, AT, &offset_expr, 0); | |
5462 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5463 | "mtc1", "t,G", AT, treg); | |
5464 | } | |
5465 | } | |
5466 | break; | |
5467 | } | |
5468 | ||
55933a58 ILT |
5469 | assert (offset_expr.X_op == O_symbol |
5470 | && offset_expr.X_add_number == 0); | |
5471 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
5472 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 5473 | { |
3c83da8a | 5474 | if (mips_opts.isa >= 2) |
0dd2d296 ILT |
5475 | { |
5476 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5477 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5478 | return; | |
5479 | } | |
5480 | breg = GP; | |
5481 | r = BFD_RELOC_MIPS_LITERAL; | |
5482 | goto dob; | |
5483 | } | |
55933a58 | 5484 | else |
0dd2d296 | 5485 | { |
55933a58 ILT |
5486 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
5487 | if (mips_pic == SVR4_PIC) | |
5488 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5489 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5490 | || mips_opts.isa < 3) | |
5491 | ? "lw" : "ld"), | |
55933a58 ILT |
5492 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5493 | else | |
5494 | { | |
5495 | /* FIXME: This won't work for a 64 bit address. */ | |
5496 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5497 | } | |
5498 | ||
3c83da8a | 5499 | if (mips_opts.isa >= 2) |
0dd2d296 ILT |
5500 | { |
5501 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 5502 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
94b68f04 ILT |
5503 | |
5504 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
5505 | that this does not become a variant frag. */ | |
5506 | frag_wane (frag_now); | |
5507 | frag_new (0); | |
5508 | ||
0dd2d296 ILT |
5509 | break; |
5510 | } | |
5511 | breg = AT; | |
5512 | r = BFD_RELOC_LO16; | |
5513 | goto dob; | |
8358c818 | 5514 | } |
9226253a | 5515 | |
3d3c5039 | 5516 | case M_L_DOB: |
1c6f3441 ILT |
5517 | if (mips_4650) |
5518 | { | |
48401fcf | 5519 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
5520 | return; |
5521 | } | |
9a7d824a ILT |
5522 | /* Even on a big endian machine $fn comes before $fn+1. We have |
5523 | to adjust when loading from memory. */ | |
9226253a ILT |
5524 | r = BFD_RELOC_LO16; |
5525 | dob: | |
3c83da8a | 5526 | assert (mips_opts.isa < 2); |
0dd2d296 | 5527 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 5528 | target_big_endian ? treg + 1 : treg, |
9226253a | 5529 | (int) r, breg); |
0dd2d296 ILT |
5530 | /* FIXME: A possible overflow which I don't know how to deal |
5531 | with. */ | |
670a50eb | 5532 | offset_expr.X_add_number += 4; |
0dd2d296 | 5533 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 5534 | target_big_endian ? treg : treg + 1, |
9226253a | 5535 | (int) r, breg); |
d2c71068 ILT |
5536 | |
5537 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5538 | does not become a variant frag. */ | |
5539 | frag_wane (frag_now); | |
5540 | frag_new (0); | |
5541 | ||
0dd2d296 ILT |
5542 | if (breg != AT) |
5543 | return; | |
5544 | break; | |
3d3c5039 ILT |
5545 | |
5546 | case M_L_DAB: | |
670a50eb ILT |
5547 | /* |
5548 | * The MIPS assembler seems to check for X_add_number not | |
5549 | * being double aligned and generating: | |
5550 | * lui at,%hi(foo+1) | |
5551 | * addu at,at,v1 | |
5552 | * addiu at,at,%lo(foo+1) | |
5553 | * lwc1 f2,0(at) | |
5554 | * lwc1 f3,4(at) | |
5555 | * But, the resulting address is the same after relocation so why | |
5556 | * generate the extra instruction? | |
5557 | */ | |
1c6f3441 ILT |
5558 | if (mips_4650) |
5559 | { | |
48401fcf | 5560 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
5561 | return; |
5562 | } | |
efec4a28 | 5563 | /* Itbl support may require additional care here. */ |
4032d3f0 | 5564 | coproc = 1; |
3c83da8a | 5565 | if (mips_opts.isa >= 2) |
670a50eb | 5566 | { |
0dd2d296 ILT |
5567 | s = "ldc1"; |
5568 | goto ld; | |
670a50eb | 5569 | } |
0dd2d296 ILT |
5570 | |
5571 | s = "lwc1"; | |
5572 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
5573 | goto ldd_std; |
5574 | ||
5575 | case M_S_DAB: | |
1c6f3441 ILT |
5576 | if (mips_4650) |
5577 | { | |
48401fcf | 5578 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
5579 | return; |
5580 | } | |
5581 | ||
3c83da8a | 5582 | if (mips_opts.isa >= 2) |
8358c818 | 5583 | { |
0dd2d296 ILT |
5584 | s = "sdc1"; |
5585 | goto st; | |
8358c818 | 5586 | } |
3d3c5039 | 5587 | |
0dd2d296 ILT |
5588 | s = "swc1"; |
5589 | fmt = "T,o(b)"; | |
efec4a28 | 5590 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5591 | coproc = 1; |
5592 | goto ldd_std; | |
3d3c5039 ILT |
5593 | |
5594 | case M_LD_AB: | |
3c83da8a | 5595 | if (mips_opts.isa >= 3) |
670a50eb | 5596 | { |
0dd2d296 ILT |
5597 | s = "ld"; |
5598 | goto ld; | |
670a50eb | 5599 | } |
0dd2d296 ILT |
5600 | |
5601 | s = "lw"; | |
5602 | fmt = "t,o(b)"; | |
5603 | goto ldd_std; | |
5604 | ||
5605 | case M_SD_AB: | |
3c83da8a | 5606 | if (mips_opts.isa >= 3) |
670a50eb | 5607 | { |
0dd2d296 ILT |
5608 | s = "sd"; |
5609 | goto st; | |
670a50eb | 5610 | } |
0dd2d296 | 5611 | |
670a50eb | 5612 | s = "sw"; |
0dd2d296 ILT |
5613 | fmt = "t,o(b)"; |
5614 | ||
5615 | ldd_std: | |
5616 | if (offset_expr.X_op != O_symbol | |
5617 | && offset_expr.X_op != O_constant) | |
670a50eb | 5618 | { |
48401fcf | 5619 | as_bad (_("expression too complex")); |
0dd2d296 ILT |
5620 | offset_expr.X_op = O_constant; |
5621 | } | |
5622 | ||
5623 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5624 | to adjust when loading from memory. We set coproc if we must | |
5625 | load $fn+1 first. */ | |
efec4a28 | 5626 | /* Itbl support may require additional care here. */ |
b9129c6f | 5627 | if (! target_big_endian) |
0dd2d296 ILT |
5628 | coproc = 0; |
5629 | ||
d9aba805 | 5630 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
5631 | || offset_expr.X_op == O_constant) |
5632 | { | |
5633 | /* If this is a reference to a GP relative symbol, we want | |
5634 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5635 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5636 | If we have a base register, we use this | |
5637 | addu $at,$breg,$gp | |
5638 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5639 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5640 | If this is not a GP relative symbol, we want | |
5641 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5642 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5643 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5644 | If there is a base register, we add it to $at after the | |
5645 | lui instruction. If there is a constant, we always use | |
5646 | the last case. */ | |
7a15a226 | 5647 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 5648 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
670a50eb | 5649 | { |
0dd2d296 ILT |
5650 | p = NULL; |
5651 | used_at = 1; | |
670a50eb ILT |
5652 | } |
5653 | else | |
0dd2d296 ILT |
5654 | { |
5655 | int off; | |
5656 | ||
5657 | if (breg == 0) | |
5658 | { | |
8ea7f4e8 | 5659 | frag_grow (28); |
0dd2d296 ILT |
5660 | tempreg = GP; |
5661 | off = 0; | |
5662 | used_at = 0; | |
5663 | } | |
5664 | else | |
5665 | { | |
8ea7f4e8 | 5666 | frag_grow (36); |
0dd2d296 | 5667 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
5668 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5669 | || mips_opts.isa < 3) | |
5670 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
5671 | "d,v,t", AT, breg, GP); |
5672 | tempreg = AT; | |
5673 | off = 4; | |
5674 | used_at = 1; | |
5675 | } | |
5676 | ||
efec4a28 | 5677 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5678 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5679 | coproc ? treg + 1 : treg, | |
5680 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5681 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
5682 | |
5683 | /* Set mips_optimize to 2 to avoid inserting an | |
5684 | undesired nop. */ | |
5685 | hold_mips_optimize = mips_optimize; | |
5686 | mips_optimize = 2; | |
efec4a28 | 5687 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5688 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5689 | coproc ? treg : treg + 1, | |
5690 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
5691 | mips_optimize = hold_mips_optimize; |
5692 | ||
0dd2d296 ILT |
5693 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
5694 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
3c83da8a | 5695 | used_at && mips_opts.noat), |
f59fb6ca | 5696 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5697 | (char *) NULL); |
777ad64d ILT |
5698 | |
5699 | /* We just generated two relocs. When tc_gen_reloc | |
5700 | handles this case, it will skip the first reloc and | |
5701 | handle the second. The second reloc already has an | |
5702 | extra addend of 4, which we added above. We must | |
5703 | subtract it out, and then subtract another 4 to make | |
5704 | the first reloc come out right. The second reloc | |
5705 | will come out right because we are going to add 4 to | |
703f5e6e ILT |
5706 | offset_expr when we build its instruction below. |
5707 | ||
5708 | If we have a symbol, then we don't want to include | |
5709 | the offset, because it will wind up being included | |
5710 | when we generate the reloc. */ | |
5711 | ||
5712 | if (offset_expr.X_op == O_constant) | |
5713 | offset_expr.X_add_number -= 8; | |
5714 | else | |
5715 | { | |
5716 | offset_expr.X_add_number = -4; | |
5717 | offset_expr.X_op = O_constant; | |
5718 | } | |
0dd2d296 ILT |
5719 | } |
5720 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
5721 | if (p != NULL) | |
5722 | p += 4; | |
5723 | if (breg != 0) | |
5724 | { | |
5725 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5726 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5727 | || mips_opts.isa < 3) | |
5728 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
5729 | "d,v,t", AT, breg, AT); |
5730 | if (p != NULL) | |
5731 | p += 4; | |
5732 | } | |
efec4a28 | 5733 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5734 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5735 | coproc ? treg + 1 : treg, | |
5736 | (int) BFD_RELOC_LO16, AT); | |
5737 | if (p != NULL) | |
5738 | p += 4; | |
5739 | /* FIXME: How do we handle overflow here? */ | |
5740 | offset_expr.X_add_number += 4; | |
efec4a28 | 5741 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5742 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5743 | coproc ? treg : treg + 1, | |
5744 | (int) BFD_RELOC_LO16, AT); | |
5745 | } | |
fb251650 | 5746 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 5747 | { |
0dd2d296 ILT |
5748 | int off; |
5749 | ||
5750 | /* If this is a reference to an external symbol, we want | |
5751 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5752 | nop | |
5753 | <op> $treg,0($at) | |
5754 | <op> $treg+1,4($at) | |
5755 | Otherwise we want | |
5756 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5757 | nop | |
5758 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5759 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5760 | If there is a base register we add it to $at before the | |
5761 | lwc1 instructions. If there is a constant we include it | |
5762 | in the lwc1 instructions. */ | |
5763 | used_at = 1; | |
5764 | expr1.X_add_number = offset_expr.X_add_number; | |
5765 | offset_expr.X_add_number = 0; | |
5766 | if (expr1.X_add_number < -0x8000 | |
5767 | || expr1.X_add_number >= 0x8000 - 4) | |
48401fcf | 5768 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
0dd2d296 ILT |
5769 | if (breg == 0) |
5770 | off = 0; | |
5771 | else | |
5772 | off = 4; | |
8ea7f4e8 | 5773 | frag_grow (24 + off); |
0dd2d296 | 5774 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a1f3160 JL |
5775 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5776 | || mips_opts.isa < 3) | |
5777 | ? "lw" : "ld"), | |
0dd2d296 ILT |
5778 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5779 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 5780 | if (breg != 0) |
0dd2d296 | 5781 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
5782 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5783 | || mips_opts.isa < 3) | |
5784 | ? "addu" : "daddu"), | |
0dd2d296 | 5785 | "d,v,t", AT, breg, AT); |
efec4a28 | 5786 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5787 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5788 | coproc ? treg + 1 : treg, | |
5789 | (int) BFD_RELOC_LO16, AT); | |
5790 | expr1.X_add_number += 4; | |
55933a58 ILT |
5791 | |
5792 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5793 | nop. */ | |
5794 | hold_mips_optimize = mips_optimize; | |
5795 | mips_optimize = 2; | |
efec4a28 | 5796 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5797 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5798 | coproc ? treg : treg + 1, | |
5799 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
5800 | mips_optimize = hold_mips_optimize; |
5801 | ||
0dd2d296 ILT |
5802 | (void) frag_var (rs_machine_dependent, 0, 0, |
5803 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
f59fb6ca | 5804 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5805 | (char *) NULL); |
8358c818 | 5806 | } |
fb251650 ILT |
5807 | else if (mips_pic == SVR4_PIC) |
5808 | { | |
5809 | int gpdel, off; | |
5810 | ||
5811 | /* If this is a reference to an external symbol, we want | |
5812 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5813 | addu $at,$at,$gp | |
5814 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
5815 | nop | |
5816 | <op> $treg,0($at) | |
5817 | <op> $treg+1,4($at) | |
5818 | Otherwise we want | |
5819 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5820 | nop | |
5821 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5822 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5823 | If there is a base register we add it to $at before the | |
5824 | lwc1 instructions. If there is a constant we include it | |
5825 | in the lwc1 instructions. */ | |
5826 | used_at = 1; | |
5827 | expr1.X_add_number = offset_expr.X_add_number; | |
5828 | offset_expr.X_add_number = 0; | |
5829 | if (expr1.X_add_number < -0x8000 | |
5830 | || expr1.X_add_number >= 0x8000 - 4) | |
48401fcf | 5831 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
fb251650 ILT |
5832 | if (reg_needs_delay (GP)) |
5833 | gpdel = 4; | |
5834 | else | |
5835 | gpdel = 0; | |
5836 | if (breg == 0) | |
5837 | off = 0; | |
5838 | else | |
5839 | off = 4; | |
5840 | frag_grow (56); | |
5841 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5842 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5843 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5844 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5845 | || mips_opts.isa < 3) | |
5846 | ? "addu" : "daddu"), | |
fb251650 ILT |
5847 | "d,v,t", AT, AT, GP); |
5848 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5849 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5850 | || mips_opts.isa < 3) | |
5851 | ? "lw" : "ld"), | |
fb251650 ILT |
5852 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); |
5853 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5854 | if (breg != 0) | |
5855 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5856 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5857 | || mips_opts.isa < 3) | |
5858 | ? "addu" : "daddu"), | |
fb251650 | 5859 | "d,v,t", AT, breg, AT); |
efec4a28 | 5860 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5861 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5862 | coproc ? treg + 1 : treg, | |
5863 | (int) BFD_RELOC_LO16, AT); | |
5864 | expr1.X_add_number += 4; | |
5865 | ||
5866 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5867 | nop. */ | |
5868 | hold_mips_optimize = mips_optimize; | |
5869 | mips_optimize = 2; | |
efec4a28 | 5870 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5871 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5872 | coproc ? treg : treg + 1, | |
5873 | (int) BFD_RELOC_LO16, AT); | |
5874 | mips_optimize = hold_mips_optimize; | |
5875 | expr1.X_add_number -= 4; | |
5876 | ||
5877 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5878 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5879 | 8 + gpdel + off, 1, 0), | |
f59fb6ca | 5880 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
5881 | (char *) NULL); |
5882 | if (gpdel > 0) | |
5883 | { | |
5884 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5885 | p += 4; | |
5886 | } | |
5887 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5888 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5889 | || mips_opts.isa < 3) | |
5890 | ? "lw" : "ld"), | |
fb251650 ILT |
5891 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5892 | p += 4; | |
5893 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5894 | p += 4; | |
5895 | if (breg != 0) | |
5896 | { | |
5897 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5898 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5899 | || mips_opts.isa < 3) | |
5900 | ? "addu" : "daddu"), | |
fb251650 ILT |
5901 | "d,v,t", AT, breg, AT); |
5902 | p += 4; | |
5903 | } | |
efec4a28 | 5904 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5905 | macro_build (p, &icnt, &expr1, s, fmt, |
5906 | coproc ? treg + 1 : treg, | |
5907 | (int) BFD_RELOC_LO16, AT); | |
5908 | p += 4; | |
5909 | expr1.X_add_number += 4; | |
5910 | ||
5911 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5912 | nop. */ | |
5913 | hold_mips_optimize = mips_optimize; | |
5914 | mips_optimize = 2; | |
efec4a28 | 5915 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5916 | macro_build (p, &icnt, &expr1, s, fmt, |
5917 | coproc ? treg : treg + 1, | |
5918 | (int) BFD_RELOC_LO16, AT); | |
5919 | mips_optimize = hold_mips_optimize; | |
5920 | } | |
d9aba805 ILT |
5921 | else if (mips_pic == EMBEDDED_PIC) |
5922 | { | |
5923 | /* If there is no base register, we use | |
5924 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5925 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5926 | If we have a base register, we use | |
5927 | addu $at,$breg,$gp | |
5928 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5929 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5930 | */ | |
5931 | if (breg == 0) | |
5932 | { | |
5933 | tempreg = GP; | |
5934 | used_at = 0; | |
5935 | } | |
5936 | else | |
5937 | { | |
5938 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5939 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5940 | || mips_opts.isa < 3) | |
5941 | ? "addu" : "daddu"), | |
d9aba805 ILT |
5942 | "d,v,t", AT, breg, GP); |
5943 | tempreg = AT; | |
5944 | used_at = 1; | |
5945 | } | |
5946 | ||
efec4a28 | 5947 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5948 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5949 | coproc ? treg + 1 : treg, | |
5950 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5951 | offset_expr.X_add_number += 4; | |
efec4a28 | 5952 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5953 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5954 | coproc ? treg : treg + 1, | |
5955 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5956 | } | |
5957 | else | |
5958 | abort (); | |
0dd2d296 ILT |
5959 | |
5960 | if (! used_at) | |
5961 | return; | |
5962 | ||
5963 | break; | |
5964 | ||
5965 | case M_LD_OB: | |
5966 | s = "lw"; | |
5967 | goto sd_ob; | |
5968 | case M_SD_OB: | |
5969 | s = "sw"; | |
5970 | sd_ob: | |
9a1f3160 | 5971 | assert (bfd_arch_bits_per_address (stdoutput) == 32 || mips_opts.isa < 3); |
0dd2d296 ILT |
5972 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
5973 | (int) BFD_RELOC_LO16, breg); | |
5974 | offset_expr.X_add_number += 4; | |
5975 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5976 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 5977 | return; |
efec4a28 DP |
5978 | |
5979 | /* New code added to support COPZ instructions. | |
5980 | This code builds table entries out of the macros in mip_opcodes. | |
5981 | R4000 uses interlocks to handle coproc delays. | |
5982 | Other chips (like the R3000) require nops to be inserted for delays. | |
5983 | ||
5984 | FIXME: Currently, we require that the user handle delays. | |
5985 | In order to fill delay slots for non-interlocked chips, | |
5986 | we must have a way to specify delays based on the coprocessor. | |
5987 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
5988 | What are the side-effects of the cop instruction? | |
5989 | What cache support might we have and what are its effects? | |
5990 | Both coprocessor & memory require delays. how long??? | |
5991 | What registers are read/set/modified? | |
5992 | ||
5993 | If an itbl is provided to interpret cop instructions, | |
5994 | this knowledge can be encoded in the itbl spec. */ | |
5995 | ||
5996 | case M_COP0: | |
65d2c7d3 | 5997 | s = "c0"; |
efec4a28 DP |
5998 | goto copz; |
5999 | case M_COP1: | |
65d2c7d3 | 6000 | s = "c1"; |
efec4a28 DP |
6001 | goto copz; |
6002 | case M_COP2: | |
65d2c7d3 | 6003 | s = "c2"; |
efec4a28 DP |
6004 | goto copz; |
6005 | case M_COP3: | |
65d2c7d3 | 6006 | s = "c3"; |
efec4a28 | 6007 | copz: |
65d2c7d3 JL |
6008 | /* For now we just do C (same as Cz). The parameter will be |
6009 | stored in insn_opcode by mips_ip. */ | |
6010 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", | |
6011 | ip->insn_opcode); | |
efec4a28 DP |
6012 | return; |
6013 | ||
917fae09 SS |
6014 | #ifdef LOSING_COMPILER |
6015 | default: | |
efec4a28 DP |
6016 | /* Try and see if this is a new itbl instruction. |
6017 | This code builds table entries out of the macros in mip_opcodes. | |
6018 | FIXME: For now we just assemble the expression and pass it's | |
6019 | value along as a 32-bit immediate. | |
6020 | We may want to have the assembler assemble this value, | |
6021 | so that we gain the assembler's knowledge of delay slots, | |
6022 | symbols, etc. | |
6023 | Would it be more efficient to use mask (id) here? */ | |
6024 | if (itbl_have_entries | |
9218cee0 | 6025 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
efec4a28 DP |
6026 | { |
6027 | s = ip->insn_mo->name; | |
6028 | s2 = "cop3"; | |
9218cee0 | 6029 | coproc = ITBL_DECODE_PNUM (immed_expr);; |
efec4a28 DP |
6030 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); |
6031 | return; | |
6032 | } | |
917fae09 SS |
6033 | macro2 (ip); |
6034 | return; | |
6035 | } | |
3c83da8a | 6036 | if (mips_opts.noat) |
48401fcf | 6037 | as_warn (_("Macro used $at after \".set noat\"")); |
917fae09 SS |
6038 | } |
6039 | ||
6040 | static void | |
6041 | macro2 (ip) | |
6042 | struct mips_cl_insn *ip; | |
6043 | { | |
6044 | register int treg, sreg, dreg, breg; | |
6045 | int tempreg; | |
6046 | int mask; | |
6047 | int icnt = 0; | |
6048 | int used_at; | |
6049 | expressionS expr1; | |
6050 | const char *s; | |
6051 | const char *s2; | |
6052 | const char *fmt; | |
6053 | int likely = 0; | |
6054 | int dbl = 0; | |
6055 | int coproc = 0; | |
adcf2b9d | 6056 | int lr = 0; |
40f0c904 | 6057 | int imm = 0; |
adcf2b9d | 6058 | int off; |
917fae09 SS |
6059 | offsetT maxnum; |
6060 | bfd_reloc_code_real_type r; | |
6061 | char *p; | |
6062 | ||
6063 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
6064 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6065 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6066 | mask = ip->insn_mo->mask; | |
6067 | ||
6068 | expr1.X_op = O_constant; | |
6069 | expr1.X_op_symbol = NULL; | |
6070 | expr1.X_add_symbol = NULL; | |
6071 | expr1.X_add_number = 1; | |
6072 | ||
6073 | switch (mask) | |
6074 | { | |
6075 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 6076 | |
8358c818 ILT |
6077 | case M_DMUL: |
6078 | dbl = 1; | |
3d3c5039 | 6079 | case M_MUL: |
0dd2d296 | 6080 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6081 | dbl ? "dmultu" : "multu", |
6082 | "s,t", sreg, treg); | |
0dd2d296 | 6083 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 6084 | return; |
3d3c5039 | 6085 | |
8358c818 ILT |
6086 | case M_DMUL_I: |
6087 | dbl = 1; | |
3d3c5039 | 6088 | case M_MUL_I: |
8358c818 ILT |
6089 | /* The MIPS assembler some times generates shifts and adds. I'm |
6090 | not trying to be that fancy. GCC should do this for us | |
6091 | anyway. */ | |
d8a1c247 | 6092 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 6093 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6094 | dbl ? "dmult" : "mult", |
6095 | "s,t", sreg, AT); | |
0dd2d296 | 6096 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 6097 | break; |
3d3c5039 | 6098 | |
40f0c904 FCE |
6099 | case M_DMULO_I: |
6100 | dbl = 1; | |
6101 | case M_MULO_I: | |
6102 | imm = 1; | |
6103 | goto do_mulo; | |
6104 | ||
8358c818 ILT |
6105 | case M_DMULO: |
6106 | dbl = 1; | |
6107 | case M_MULO: | |
40f0c904 | 6108 | do_mulo: |
fbcfacb7 | 6109 | mips_emit_delays (true); |
3c83da8a | 6110 | ++mips_opts.noreorder; |
0dd2d296 | 6111 | mips_any_noreorder = 1; |
40f0c904 FCE |
6112 | if (imm) |
6113 | load_register (&icnt, AT, &imm_expr, dbl); | |
0dd2d296 | 6114 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 | 6115 | dbl ? "dmult" : "mult", |
40f0c904 | 6116 | "s,t", sreg, imm ? AT : treg); |
0dd2d296 ILT |
6117 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
6118 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
6119 | dbl ? "dsra32" : "sra", |
6120 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 6121 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
6122 | if (mips_trap) |
6123 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
6124 | else | |
6125 | { | |
6126 | expr1.X_add_number = 8; | |
6127 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
6128 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
d9c2c0c5 FCE |
6129 | /* start-sanitize-r5900 */ |
6130 | if (mips_5900) | |
6131 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 6); | |
6132 | else | |
6133 | /* end-sanitize-r5900 */ | |
6134 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
8ea7f4e8 | 6135 | } |
3c83da8a | 6136 | --mips_opts.noreorder; |
0dd2d296 | 6137 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
6138 | break; |
6139 | ||
40f0c904 FCE |
6140 | case M_DMULOU_I: |
6141 | dbl = 1; | |
6142 | case M_MULOU_I: | |
6143 | imm = 1; | |
6144 | goto do_mulou; | |
6145 | ||
8358c818 ILT |
6146 | case M_DMULOU: |
6147 | dbl = 1; | |
6148 | case M_MULOU: | |
40f0c904 | 6149 | do_mulou: |
fbcfacb7 | 6150 | mips_emit_delays (true); |
3c83da8a | 6151 | ++mips_opts.noreorder; |
0dd2d296 | 6152 | mips_any_noreorder = 1; |
40f0c904 FCE |
6153 | if (imm) |
6154 | load_register (&icnt, AT, &imm_expr, dbl); | |
0dd2d296 | 6155 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 | 6156 | dbl ? "dmultu" : "multu", |
40f0c904 | 6157 | "s,t", sreg, imm ? AT : treg); |
0dd2d296 ILT |
6158 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
6159 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
6160 | if (mips_trap) |
6161 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
6162 | else | |
6163 | { | |
6164 | expr1.X_add_number = 8; | |
6165 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
6166 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
d9c2c0c5 FCE |
6167 | /* start-sanitize-r5900 */ |
6168 | if (mips_5900) | |
6169 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 6); | |
6170 | else | |
6171 | /* end-sanitize-r5900 */ | |
6172 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
8ea7f4e8 | 6173 | } |
3c83da8a | 6174 | --mips_opts.noreorder; |
8358c818 ILT |
6175 | break; |
6176 | ||
3d3c5039 | 6177 | case M_ROL: |
0dd2d296 ILT |
6178 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
6179 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6180 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
6181 | treg); | |
6182 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 6183 | break; |
3d3c5039 ILT |
6184 | |
6185 | case M_ROL_I: | |
5c6f5923 | 6186 | if (imm_expr.X_op != O_constant) |
48401fcf | 6187 | as_bad (_("rotate count too large")); |
0dd2d296 | 6188 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
a40aee38 | 6189 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 6190 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
a40aee38 | 6191 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 6192 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 6193 | break; |
3d3c5039 ILT |
6194 | |
6195 | case M_ROR: | |
0dd2d296 ILT |
6196 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
6197 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
6198 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
6199 | treg); | |
6200 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 6201 | break; |
3d3c5039 ILT |
6202 | |
6203 | case M_ROR_I: | |
5c6f5923 | 6204 | if (imm_expr.X_op != O_constant) |
48401fcf | 6205 | as_bad (_("rotate count too large")); |
0dd2d296 | 6206 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
a40aee38 | 6207 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 6208 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
a40aee38 | 6209 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 6210 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 6211 | break; |
3d3c5039 ILT |
6212 | |
6213 | case M_S_DOB: | |
1c6f3441 ILT |
6214 | if (mips_4650) |
6215 | { | |
48401fcf | 6216 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
6217 | return; |
6218 | } | |
3c83da8a | 6219 | assert (mips_opts.isa < 2); |
9a7d824a ILT |
6220 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6221 | to adjust when storing to memory. */ | |
0dd2d296 | 6222 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 6223 | target_big_endian ? treg + 1 : treg, |
9226253a | 6224 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6225 | offset_expr.X_add_number += 4; |
0dd2d296 | 6226 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 6227 | target_big_endian ? treg : treg + 1, |
9226253a | 6228 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6229 | return; |
3d3c5039 | 6230 | |
3d3c5039 | 6231 | case M_SEQ: |
670a50eb | 6232 | if (sreg == 0) |
0dd2d296 ILT |
6233 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6234 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 6235 | else if (treg == 0) |
0dd2d296 ILT |
6236 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6237 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
6238 | else |
6239 | { | |
0dd2d296 ILT |
6240 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6241 | sreg, treg); | |
6242 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6243 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 6244 | } |
670a50eb | 6245 | return; |
3d3c5039 ILT |
6246 | |
6247 | case M_SEQ_I: | |
5c6f5923 | 6248 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 6249 | { |
0dd2d296 ILT |
6250 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6251 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6252 | return; |
3d3c5039 | 6253 | } |
670a50eb ILT |
6254 | if (sreg == 0) |
6255 | { | |
48401fcf | 6256 | as_warn (_("Instruction %s: result is always false"), |
6e8dda9c | 6257 | ip->insn_mo->name); |
0dd2d296 | 6258 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 6259 | return; |
3d3c5039 | 6260 | } |
5c6f5923 GRK |
6261 | if (imm_expr.X_op == O_constant |
6262 | && imm_expr.X_add_number >= 0 | |
6263 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 6264 | { |
0dd2d296 ILT |
6265 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
6266 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6267 | used_at = 0; |
6e8dda9c | 6268 | } |
5c6f5923 GRK |
6269 | else if (imm_expr.X_op == O_constant |
6270 | && imm_expr.X_add_number > -0x8000 | |
6271 | && imm_expr.X_add_number < 0) | |
6e8dda9c ILT |
6272 | { |
6273 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6274 | macro_build ((char *) NULL, &icnt, &imm_expr, |
9a1f3160 JL |
6275 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6276 | || mips_opts.isa < 3) | |
6277 | ? "addiu" : "daddiu"), | |
9226253a ILT |
6278 | "t,r,j", dreg, sreg, |
6279 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
6280 | used_at = 0; |
6281 | } | |
6282 | else | |
6283 | { | |
d8a1c247 | 6284 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6285 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6286 | sreg, AT); | |
670a50eb ILT |
6287 | used_at = 1; |
6288 | } | |
0dd2d296 | 6289 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 6290 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
6291 | if (used_at) |
6292 | break; | |
6293 | return; | |
3d3c5039 ILT |
6294 | |
6295 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
6296 | s = "slt"; |
6297 | goto sge; | |
3d3c5039 | 6298 | case M_SGEU: |
670a50eb | 6299 | s = "sltu"; |
3d3c5039 | 6300 | sge: |
0dd2d296 ILT |
6301 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
6302 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 6303 | (int) BFD_RELOC_LO16); |
670a50eb | 6304 | return; |
3d3c5039 | 6305 | |
670a50eb | 6306 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 6307 | case M_SGEU_I: |
5c6f5923 GRK |
6308 | if (imm_expr.X_op == O_constant |
6309 | && imm_expr.X_add_number >= -0x8000 | |
6310 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 6311 | { |
6b34ac5a | 6312 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 6313 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 6314 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
6315 | used_at = 0; |
6316 | } | |
6317 | else | |
6318 | { | |
d8a1c247 | 6319 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6320 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
6321 | mask == M_SGE_I ? "slt" : "sltu", |
6322 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
6323 | used_at = 1; |
6324 | } | |
0dd2d296 | 6325 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 6326 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
6327 | if (used_at) |
6328 | break; | |
6329 | return; | |
3d3c5039 ILT |
6330 | |
6331 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
6332 | s = "slt"; |
6333 | goto sgt; | |
3d3c5039 | 6334 | case M_SGTU: |
670a50eb | 6335 | s = "sltu"; |
3d3c5039 | 6336 | sgt: |
0dd2d296 | 6337 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 6338 | return; |
3d3c5039 | 6339 | |
670a50eb ILT |
6340 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
6341 | s = "slt"; | |
6342 | goto sgti; | |
3d3c5039 | 6343 | case M_SGTU_I: |
670a50eb | 6344 | s = "sltu"; |
3d3c5039 | 6345 | sgti: |
d8a1c247 | 6346 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6347 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 6348 | break; |
3d3c5039 | 6349 | |
670a50eb ILT |
6350 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
6351 | s = "slt"; | |
6352 | goto sle; | |
3d3c5039 | 6353 | case M_SLEU: |
670a50eb | 6354 | s = "sltu"; |
3d3c5039 | 6355 | sle: |
0dd2d296 ILT |
6356 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
6357 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 6358 | (int) BFD_RELOC_LO16); |
670a50eb | 6359 | return; |
3d3c5039 | 6360 | |
670a50eb ILT |
6361 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
6362 | s = "slt"; | |
6363 | goto slei; | |
3d3c5039 | 6364 | case M_SLEU_I: |
670a50eb | 6365 | s = "sltu"; |
3d3c5039 | 6366 | slei: |
d8a1c247 | 6367 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6368 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
6369 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 6370 | (int) BFD_RELOC_LO16); |
670a50eb | 6371 | break; |
3d3c5039 ILT |
6372 | |
6373 | case M_SLT_I: | |
5c6f5923 GRK |
6374 | if (imm_expr.X_op == O_constant |
6375 | && imm_expr.X_add_number >= -0x8000 | |
6376 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 6377 | { |
0dd2d296 ILT |
6378 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
6379 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6380 | return; |
3d3c5039 | 6381 | } |
d8a1c247 | 6382 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6383 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 6384 | break; |
3d3c5039 ILT |
6385 | |
6386 | case M_SLTU_I: | |
5c6f5923 GRK |
6387 | if (imm_expr.X_op == O_constant |
6388 | && imm_expr.X_add_number >= -0x8000 | |
6389 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 6390 | { |
0dd2d296 ILT |
6391 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
6392 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6393 | return; |
3d3c5039 | 6394 | } |
d8a1c247 | 6395 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6396 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
6397 | AT); | |
670a50eb | 6398 | break; |
3d3c5039 ILT |
6399 | |
6400 | case M_SNE: | |
670a50eb | 6401 | if (sreg == 0) |
0dd2d296 ILT |
6402 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
6403 | treg); | |
670a50eb | 6404 | else if (treg == 0) |
0dd2d296 ILT |
6405 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
6406 | sreg); | |
670a50eb ILT |
6407 | else |
6408 | { | |
0dd2d296 ILT |
6409 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6410 | sreg, treg); | |
6411 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6412 | dreg); | |
3d3c5039 | 6413 | } |
670a50eb | 6414 | return; |
3d3c5039 ILT |
6415 | |
6416 | case M_SNE_I: | |
5c6f5923 | 6417 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 6418 | { |
0dd2d296 ILT |
6419 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
6420 | sreg); | |
670a50eb | 6421 | return; |
3d3c5039 | 6422 | } |
670a50eb ILT |
6423 | if (sreg == 0) |
6424 | { | |
48401fcf | 6425 | as_warn (_("Instruction %s: result is always true"), |
6e8dda9c | 6426 | ip->insn_mo->name); |
0dd2d296 | 6427 | macro_build ((char *) NULL, &icnt, &expr1, |
9a1f3160 JL |
6428 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6429 | || mips_opts.isa < 3) | |
6430 | ? "addiu" : "daddiu"), | |
9226253a | 6431 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 6432 | return; |
3d3c5039 | 6433 | } |
5c6f5923 GRK |
6434 | if (imm_expr.X_op == O_constant |
6435 | && imm_expr.X_add_number >= 0 | |
6436 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 6437 | { |
0dd2d296 ILT |
6438 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
6439 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6440 | used_at = 0; |
6e8dda9c | 6441 | } |
5c6f5923 GRK |
6442 | else if (imm_expr.X_op == O_constant |
6443 | && imm_expr.X_add_number > -0x8000 | |
6444 | && imm_expr.X_add_number < 0) | |
6e8dda9c ILT |
6445 | { |
6446 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6447 | macro_build ((char *) NULL, &icnt, &imm_expr, |
9a1f3160 JL |
6448 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6449 | || mips_opts.isa < 3) | |
6450 | ? "addiu" : "daddiu"), | |
9226253a | 6451 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
6452 | used_at = 0; |
6453 | } | |
6454 | else | |
6455 | { | |
d8a1c247 | 6456 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6457 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6458 | sreg, AT); | |
670a50eb ILT |
6459 | used_at = 1; |
6460 | } | |
0dd2d296 | 6461 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
6462 | if (used_at) |
6463 | break; | |
6464 | return; | |
3d3c5039 | 6465 | |
8358c818 ILT |
6466 | case M_DSUB_I: |
6467 | dbl = 1; | |
3d3c5039 | 6468 | case M_SUB_I: |
5c6f5923 GRK |
6469 | if (imm_expr.X_op == O_constant |
6470 | && imm_expr.X_add_number > -0x8000 | |
6471 | && imm_expr.X_add_number <= 0x8000) | |
670a50eb ILT |
6472 | { |
6473 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6474 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 6475 | dbl ? "daddi" : "addi", |
9226253a | 6476 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 6477 | return; |
3d3c5039 | 6478 | } |
d8a1c247 | 6479 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 6480 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6481 | dbl ? "dsub" : "sub", |
6482 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 6483 | break; |
3d3c5039 | 6484 | |
8358c818 ILT |
6485 | case M_DSUBU_I: |
6486 | dbl = 1; | |
3d3c5039 | 6487 | case M_SUBU_I: |
5c6f5923 GRK |
6488 | if (imm_expr.X_op == O_constant |
6489 | && imm_expr.X_add_number > -0x8000 | |
6490 | && imm_expr.X_add_number <= 0x8000) | |
670a50eb ILT |
6491 | { |
6492 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6493 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 6494 | dbl ? "daddiu" : "addiu", |
9226253a | 6495 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 6496 | return; |
3d3c5039 | 6497 | } |
d8a1c247 | 6498 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 6499 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6500 | dbl ? "dsubu" : "subu", |
6501 | "d,v,t", dreg, sreg, AT); | |
6502 | break; | |
6503 | ||
6504 | case M_TEQ_I: | |
6505 | s = "teq"; | |
6506 | goto trap; | |
6507 | case M_TGE_I: | |
6508 | s = "tge"; | |
6509 | goto trap; | |
6510 | case M_TGEU_I: | |
6511 | s = "tgeu"; | |
6512 | goto trap; | |
6513 | case M_TLT_I: | |
6514 | s = "tlt"; | |
6515 | goto trap; | |
6516 | case M_TLTU_I: | |
6517 | s = "tltu"; | |
6518 | goto trap; | |
6519 | case M_TNE_I: | |
6520 | s = "tne"; | |
6521 | trap: | |
d8a1c247 | 6522 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6523 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 6524 | break; |
3d3c5039 ILT |
6525 | |
6526 | case M_TRUNCWD: | |
6527 | case M_TRUNCWS: | |
3c83da8a | 6528 | assert (mips_opts.isa < 2); |
670a50eb ILT |
6529 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
6530 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
6531 | ||
6532 | /* | |
6533 | * Is the double cfc1 instruction a bug in the mips assembler; | |
6534 | * or is there a reason for it? | |
6535 | */ | |
fbcfacb7 | 6536 | mips_emit_delays (true); |
3c83da8a | 6537 | ++mips_opts.noreorder; |
0dd2d296 ILT |
6538 | mips_any_noreorder = 1; |
6539 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6540 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6541 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 6542 | expr1.X_add_number = 3; |
0dd2d296 | 6543 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 6544 | (int) BFD_RELOC_LO16); |
670a50eb | 6545 | expr1.X_add_number = 2; |
0dd2d296 | 6546 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 6547 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
6548 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
6549 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6550 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 6551 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
6552 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
6553 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
3c83da8a | 6554 | --mips_opts.noreorder; |
670a50eb | 6555 | break; |
3d3c5039 ILT |
6556 | |
6557 | case M_ULH: | |
670a50eb ILT |
6558 | s = "lb"; |
6559 | goto ulh; | |
3d3c5039 | 6560 | case M_ULHU: |
670a50eb | 6561 | s = "lbu"; |
3d3c5039 | 6562 | ulh: |
8ea7f4e8 | 6563 | if (offset_expr.X_add_number >= 0x7fff) |
48401fcf | 6564 | as_bad (_("operand overflow")); |
670a50eb | 6565 | /* avoid load delay */ |
b9129c6f | 6566 | if (! target_big_endian) |
8ea7f4e8 | 6567 | offset_expr.X_add_number += 1; |
0dd2d296 | 6568 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 6569 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6570 | if (! target_big_endian) |
8ea7f4e8 ILT |
6571 | offset_expr.X_add_number -= 1; |
6572 | else | |
6573 | offset_expr.X_add_number += 1; | |
0dd2d296 | 6574 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 6575 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
6576 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
6577 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 6578 | break; |
3d3c5039 | 6579 | |
adcf2b9d ILT |
6580 | case M_ULD: |
6581 | s = "ldl"; | |
6582 | s2 = "ldr"; | |
6583 | off = 7; | |
6584 | goto ulw; | |
3d3c5039 | 6585 | case M_ULW: |
adcf2b9d ILT |
6586 | s = "lwl"; |
6587 | s2 = "lwr"; | |
6588 | off = 3; | |
6589 | ulw: | |
6590 | if (offset_expr.X_add_number >= 0x8000 - off) | |
48401fcf | 6591 | as_bad (_("operand overflow")); |
b9129c6f | 6592 | if (! target_big_endian) |
adcf2b9d ILT |
6593 | offset_expr.X_add_number += off; |
6594 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 6595 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6596 | if (! target_big_endian) |
adcf2b9d | 6597 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 6598 | else |
adcf2b9d ILT |
6599 | offset_expr.X_add_number += off; |
6600 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 6601 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6602 | return; |
3d3c5039 | 6603 | |
adcf2b9d ILT |
6604 | case M_ULD_A: |
6605 | s = "ldl"; | |
6606 | s2 = "ldr"; | |
6607 | off = 7; | |
6608 | goto ulwa; | |
6609 | case M_ULW_A: | |
6610 | s = "lwl"; | |
6611 | s2 = "lwr"; | |
6612 | off = 3; | |
6613 | ulwa: | |
6614 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
6615 | if (breg != 0) |
6616 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6617 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6618 | || mips_opts.isa < 3) | |
6619 | ? "addu" : "daddu"), | |
c625fc23 | 6620 | "d,v,t", AT, AT, breg); |
b9129c6f | 6621 | if (! target_big_endian) |
adcf2b9d ILT |
6622 | expr1.X_add_number = off; |
6623 | else | |
6624 | expr1.X_add_number = 0; | |
6625 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6626 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6627 | if (! target_big_endian) |
adcf2b9d ILT |
6628 | expr1.X_add_number = 0; |
6629 | else | |
6630 | expr1.X_add_number = off; | |
6631 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6632 | (int) BFD_RELOC_LO16, AT); | |
6633 | break; | |
6634 | ||
3d3c5039 ILT |
6635 | case M_ULH_A: |
6636 | case M_ULHU_A: | |
0dd2d296 | 6637 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
6638 | if (breg != 0) |
6639 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6640 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6641 | || mips_opts.isa < 3) | |
6642 | ? "addu" : "daddu"), | |
c625fc23 | 6643 | "d,v,t", AT, AT, breg); |
b9129c6f | 6644 | if (target_big_endian) |
adcf2b9d ILT |
6645 | expr1.X_add_number = 0; |
6646 | macro_build ((char *) NULL, &icnt, &expr1, | |
6647 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
6648 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6649 | if (target_big_endian) |
adcf2b9d | 6650 | expr1.X_add_number = 1; |
670a50eb | 6651 | else |
adcf2b9d ILT |
6652 | expr1.X_add_number = 0; |
6653 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6654 | (int) BFD_RELOC_LO16, AT); | |
6655 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6656 | treg, 8); | |
6657 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6658 | treg, AT); | |
670a50eb | 6659 | break; |
3d3c5039 ILT |
6660 | |
6661 | case M_USH: | |
8ea7f4e8 | 6662 | if (offset_expr.X_add_number >= 0x7fff) |
48401fcf | 6663 | as_bad (_("operand overflow")); |
b9129c6f | 6664 | if (target_big_endian) |
8ea7f4e8 | 6665 | offset_expr.X_add_number += 1; |
0dd2d296 | 6666 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 6667 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 6668 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
b9129c6f | 6669 | if (target_big_endian) |
8ea7f4e8 ILT |
6670 | offset_expr.X_add_number -= 1; |
6671 | else | |
6672 | offset_expr.X_add_number += 1; | |
0dd2d296 | 6673 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 6674 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6675 | break; |
3d3c5039 | 6676 | |
adcf2b9d ILT |
6677 | case M_USD: |
6678 | s = "sdl"; | |
6679 | s2 = "sdr"; | |
6680 | off = 7; | |
6681 | goto usw; | |
3d3c5039 | 6682 | case M_USW: |
adcf2b9d ILT |
6683 | s = "swl"; |
6684 | s2 = "swr"; | |
6685 | off = 3; | |
6686 | usw: | |
6687 | if (offset_expr.X_add_number >= 0x8000 - off) | |
48401fcf | 6688 | as_bad (_("operand overflow")); |
b9129c6f | 6689 | if (! target_big_endian) |
adcf2b9d ILT |
6690 | offset_expr.X_add_number += off; |
6691 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 6692 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6693 | if (! target_big_endian) |
adcf2b9d | 6694 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 6695 | else |
adcf2b9d ILT |
6696 | offset_expr.X_add_number += off; |
6697 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 6698 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6699 | return; |
3d3c5039 | 6700 | |
adcf2b9d ILT |
6701 | case M_USD_A: |
6702 | s = "sdl"; | |
6703 | s2 = "sdr"; | |
6704 | off = 7; | |
6705 | goto uswa; | |
3d3c5039 | 6706 | case M_USW_A: |
adcf2b9d ILT |
6707 | s = "swl"; |
6708 | s2 = "swr"; | |
6709 | off = 3; | |
6710 | uswa: | |
0dd2d296 | 6711 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
6712 | if (breg != 0) |
6713 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6714 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6715 | || mips_opts.isa < 3) | |
6716 | ? "addu" : "daddu"), | |
c625fc23 | 6717 | "d,v,t", AT, AT, breg); |
b9129c6f | 6718 | if (! target_big_endian) |
adcf2b9d | 6719 | expr1.X_add_number = off; |
670a50eb | 6720 | else |
adcf2b9d ILT |
6721 | expr1.X_add_number = 0; |
6722 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6723 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6724 | if (! target_big_endian) |
adcf2b9d ILT |
6725 | expr1.X_add_number = 0; |
6726 | else | |
6727 | expr1.X_add_number = off; | |
6728 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6729 | (int) BFD_RELOC_LO16, AT); | |
6730 | break; | |
6731 | ||
6732 | case M_USH_A: | |
6733 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
6734 | if (breg != 0) |
6735 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6736 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6737 | || mips_opts.isa < 3) | |
6738 | ? "addu" : "daddu"), | |
c625fc23 | 6739 | "d,v,t", AT, AT, breg); |
b9129c6f | 6740 | if (! target_big_endian) |
adcf2b9d ILT |
6741 | expr1.X_add_number = 0; |
6742 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6743 | (int) BFD_RELOC_LO16, AT); | |
6744 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
6745 | treg, 8); | |
b9129c6f | 6746 | if (! target_big_endian) |
adcf2b9d ILT |
6747 | expr1.X_add_number = 1; |
6748 | else | |
6749 | expr1.X_add_number = 0; | |
6750 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6751 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6752 | if (! target_big_endian) |
adcf2b9d ILT |
6753 | expr1.X_add_number = 0; |
6754 | else | |
6755 | expr1.X_add_number = 1; | |
6756 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6757 | (int) BFD_RELOC_LO16, AT); | |
6758 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6759 | treg, 8); | |
6760 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6761 | treg, AT); | |
670a50eb | 6762 | break; |
3d3c5039 ILT |
6763 | |
6764 | default: | |
9218cee0 ILT |
6765 | /* FIXME: Check if this is one of the itbl macros, since they |
6766 | are added dynamically. */ | |
48401fcf | 6767 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
8358c818 | 6768 | break; |
3d3c5039 | 6769 | } |
3c83da8a | 6770 | if (mips_opts.noat) |
48401fcf | 6771 | as_warn (_("Macro used $at after \".set noat\"")); |
3d3c5039 ILT |
6772 | } |
6773 | ||
cc5703cd | 6774 | /* Implement macros in mips16 mode. */ |
3d3c5039 | 6775 | |
3d3c5039 | 6776 | static void |
cc5703cd | 6777 | mips16_macro (ip) |
3d3c5039 ILT |
6778 | struct mips_cl_insn *ip; |
6779 | { | |
cc5703cd ILT |
6780 | int mask; |
6781 | int xreg, yreg, zreg, tmp; | |
6782 | int icnt; | |
6783 | expressionS expr1; | |
6784 | int dbl; | |
6785 | const char *s, *s2, *s3; | |
3d3c5039 | 6786 | |
cc5703cd | 6787 | mask = ip->insn_mo->mask; |
3d3c5039 | 6788 | |
cc5703cd ILT |
6789 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
6790 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
6791 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
8358c818 | 6792 | |
cc5703cd | 6793 | icnt = 0; |
8358c818 | 6794 | |
cc5703cd ILT |
6795 | expr1.X_op = O_constant; |
6796 | expr1.X_op_symbol = NULL; | |
6797 | expr1.X_add_symbol = NULL; | |
6798 | expr1.X_add_number = 1; | |
8358c818 | 6799 | |
cc5703cd | 6800 | dbl = 0; |
517078c1 | 6801 | |
cc5703cd ILT |
6802 | switch (mask) |
6803 | { | |
6804 | default: | |
6805 | internalError (); | |
6806 | ||
6807 | case M_DDIV_3: | |
6808 | dbl = 1; | |
6809 | case M_DIV_3: | |
6810 | s = "mflo"; | |
6811 | goto do_div3; | |
6812 | case M_DREM_3: | |
6813 | dbl = 1; | |
6814 | case M_REM_3: | |
6815 | s = "mfhi"; | |
6816 | do_div3: | |
fbcfacb7 | 6817 | mips_emit_delays (true); |
3c83da8a | 6818 | ++mips_opts.noreorder; |
cc5703cd ILT |
6819 | mips_any_noreorder = 1; |
6820 | macro_build ((char *) NULL, &icnt, NULL, | |
6821 | dbl ? "ddiv" : "div", | |
6822 | "0,x,y", xreg, yreg); | |
8a8121d5 | 6823 | expr1.X_add_number = 2; |
cc5703cd | 6824 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
d9c2c0c5 FCE |
6825 | /* start-sanitize-r5900 */ |
6826 | if (mips_5900) | |
6827 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); | |
6828 | else | |
6829 | /* end-sanitize-r5900 */ | |
6830 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); | |
6831 | ||
cc5703cd ILT |
6832 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
6833 | since that causes an overflow. We should do that as well, | |
6834 | but I don't see how to do the comparisons without a temporary | |
6835 | register. */ | |
3c83da8a | 6836 | --mips_opts.noreorder; |
cc5703cd ILT |
6837 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); |
6838 | break; | |
6839 | ||
6840 | case M_DIVU_3: | |
6841 | s = "divu"; | |
6842 | s2 = "mflo"; | |
6843 | goto do_divu3; | |
6844 | case M_REMU_3: | |
6845 | s = "divu"; | |
6846 | s2 = "mfhi"; | |
6847 | goto do_divu3; | |
6848 | case M_DDIVU_3: | |
6849 | s = "ddivu"; | |
6850 | s2 = "mflo"; | |
6851 | goto do_divu3; | |
6852 | case M_DREMU_3: | |
6853 | s = "ddivu"; | |
6854 | s2 = "mfhi"; | |
6855 | do_divu3: | |
fbcfacb7 | 6856 | mips_emit_delays (true); |
3c83da8a | 6857 | ++mips_opts.noreorder; |
cc5703cd ILT |
6858 | mips_any_noreorder = 1; |
6859 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
8a8121d5 | 6860 | expr1.X_add_number = 2; |
cc5703cd | 6861 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
d9c2c0c5 FCE |
6862 | /* start-sanitize-r5900 */ |
6863 | if (mips_5900) | |
6864 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); | |
6865 | else | |
6866 | /* end-sanitize-r5900 */ | |
6867 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); | |
3c83da8a | 6868 | --mips_opts.noreorder; |
cc5703cd ILT |
6869 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); |
6870 | break; | |
6871 | ||
08438bef ILT |
6872 | case M_DMUL: |
6873 | dbl = 1; | |
6874 | case M_MUL: | |
6875 | macro_build ((char *) NULL, &icnt, NULL, | |
6876 | dbl ? "dmultu" : "multu", | |
6877 | "x,y", xreg, yreg); | |
6878 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "x", zreg); | |
6879 | return; | |
6880 | ||
cc5703cd ILT |
6881 | case M_DSUBU_I: |
6882 | dbl = 1; | |
6883 | goto do_subu; | |
6884 | case M_SUBU_I: | |
6885 | do_subu: | |
5c6f5923 | 6886 | if (imm_expr.X_op != O_constant) |
48401fcf | 6887 | as_bad (_("Unsupported large constant")); |
cc5703cd ILT |
6888 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6889 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6890 | dbl ? "daddiu" : "addiu", | |
6891 | "y,x,4", yreg, xreg); | |
6892 | break; | |
6893 | ||
6894 | case M_SUBU_I_2: | |
5c6f5923 | 6895 | if (imm_expr.X_op != O_constant) |
48401fcf | 6896 | as_bad (_("Unsupported large constant")); |
cc5703cd ILT |
6897 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6898 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
6899 | "x,k", xreg); | |
6900 | break; | |
6901 | ||
6902 | case M_DSUBU_I_2: | |
5c6f5923 | 6903 | if (imm_expr.X_op != O_constant) |
48401fcf | 6904 | as_bad (_("Unsupported large constant")); |
cc5703cd ILT |
6905 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6906 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
6907 | "y,j", yreg); | |
6908 | break; | |
6909 | ||
6910 | case M_BEQ: | |
6911 | s = "cmp"; | |
6912 | s2 = "bteqz"; | |
6913 | goto do_branch; | |
6914 | case M_BNE: | |
6915 | s = "cmp"; | |
6916 | s2 = "btnez"; | |
6917 | goto do_branch; | |
6918 | case M_BLT: | |
6919 | s = "slt"; | |
6920 | s2 = "btnez"; | |
6921 | goto do_branch; | |
6922 | case M_BLTU: | |
6923 | s = "sltu"; | |
6924 | s2 = "btnez"; | |
6925 | goto do_branch; | |
6926 | case M_BLE: | |
6927 | s = "slt"; | |
6928 | s2 = "bteqz"; | |
6929 | goto do_reverse_branch; | |
6930 | case M_BLEU: | |
6931 | s = "sltu"; | |
6932 | s2 = "bteqz"; | |
6933 | goto do_reverse_branch; | |
6934 | case M_BGE: | |
6935 | s = "slt"; | |
6936 | s2 = "bteqz"; | |
6937 | goto do_branch; | |
6938 | case M_BGEU: | |
6939 | s = "sltu"; | |
6940 | s2 = "bteqz"; | |
6941 | goto do_branch; | |
6942 | case M_BGT: | |
6943 | s = "slt"; | |
6944 | s2 = "btnez"; | |
6945 | goto do_reverse_branch; | |
6946 | case M_BGTU: | |
6947 | s = "sltu"; | |
6948 | s2 = "btnez"; | |
6949 | ||
6950 | do_reverse_branch: | |
6951 | tmp = xreg; | |
6952 | xreg = yreg; | |
6953 | yreg = tmp; | |
6954 | ||
6955 | do_branch: | |
6956 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
6957 | xreg, yreg); | |
6958 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6959 | break; | |
6960 | ||
6961 | case M_BEQ_I: | |
6962 | s = "cmpi"; | |
6963 | s2 = "bteqz"; | |
6964 | s3 = "x,U"; | |
6965 | goto do_branch_i; | |
6966 | case M_BNE_I: | |
6967 | s = "cmpi"; | |
6968 | s2 = "btnez"; | |
6969 | s3 = "x,U"; | |
6970 | goto do_branch_i; | |
6971 | case M_BLT_I: | |
6972 | s = "slti"; | |
6973 | s2 = "btnez"; | |
6974 | s3 = "x,8"; | |
6975 | goto do_branch_i; | |
6976 | case M_BLTU_I: | |
6977 | s = "sltiu"; | |
6978 | s2 = "btnez"; | |
6979 | s3 = "x,8"; | |
6980 | goto do_branch_i; | |
6981 | case M_BLE_I: | |
6982 | s = "slti"; | |
6983 | s2 = "btnez"; | |
6984 | s3 = "x,8"; | |
6985 | goto do_addone_branch_i; | |
6986 | case M_BLEU_I: | |
6987 | s = "sltiu"; | |
6988 | s2 = "btnez"; | |
6989 | s3 = "x,8"; | |
6990 | goto do_addone_branch_i; | |
6991 | case M_BGE_I: | |
6992 | s = "slti"; | |
6993 | s2 = "bteqz"; | |
6994 | s3 = "x,8"; | |
6995 | goto do_branch_i; | |
6996 | case M_BGEU_I: | |
6997 | s = "sltiu"; | |
6998 | s2 = "bteqz"; | |
6999 | s3 = "x,8"; | |
7000 | goto do_branch_i; | |
7001 | case M_BGT_I: | |
7002 | s = "slti"; | |
7003 | s2 = "bteqz"; | |
7004 | s3 = "x,8"; | |
7005 | goto do_addone_branch_i; | |
7006 | case M_BGTU_I: | |
7007 | s = "sltiu"; | |
7008 | s2 = "bteqz"; | |
7009 | s3 = "x,8"; | |
7010 | ||
7011 | do_addone_branch_i: | |
5c6f5923 | 7012 | if (imm_expr.X_op != O_constant) |
48401fcf | 7013 | as_bad (_("Unsupported large constant")); |
cc5703cd ILT |
7014 | ++imm_expr.X_add_number; |
7015 | ||
7016 | do_branch_i: | |
7017 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
7018 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
7019 | break; | |
18e0764d ILT |
7020 | |
7021 | case M_ABS: | |
7022 | expr1.X_add_number = 0; | |
7023 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
7024 | if (xreg != yreg) | |
7025 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
7026 | "move", "y,X", xreg, yreg); | |
7027 | expr1.X_add_number = 2; | |
7028 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
7029 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
7030 | "neg", "x,w", xreg, xreg); | |
cc5703cd ILT |
7031 | } |
7032 | } | |
7033 | ||
aa2e0460 KR |
7034 | /* For consistency checking, verify that all bits are specified either |
7035 | by the match/mask part of the instruction definition, or by the | |
7036 | operand list. */ | |
7037 | static int | |
7038 | validate_mips_insn (opc) | |
7039 | const struct mips_opcode *opc; | |
7040 | { | |
7041 | const char *p = opc->args; | |
7042 | char c; | |
7043 | unsigned long used_bits = opc->mask; | |
7044 | ||
7045 | if ((used_bits & opc->match) != opc->match) | |
7046 | { | |
48401fcf | 7047 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), |
aa2e0460 KR |
7048 | opc->name, opc->args); |
7049 | return 0; | |
7050 | } | |
7051 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7052 | while (*p) | |
7053 | switch (c = *p++) | |
7054 | { | |
7055 | case ',': break; | |
7056 | case '(': break; | |
7057 | case ')': break; | |
7058 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7059 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7060 | case 'A': break; | |
7061 | case 'B': USE_BITS (OP_MASK_SYSCALL, OP_SH_SYSCALL); break; | |
7062 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; | |
7063 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7064 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7065 | case 'F': break; | |
7066 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7067 | case 'I': break; | |
7068 | case 'L': break; | |
7069 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7070 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
7071 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; | |
7072 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7073 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7074 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7075 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7076 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; | |
7077 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7078 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7079 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7080 | case 'f': break; | |
7081 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7082 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7083 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7084 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7085 | case 'l': break; | |
7086 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7087 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
40f0c904 | 7088 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; |
aa2e0460 KR |
7089 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; |
7090 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7091 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7092 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7093 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7094 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7095 | case 'x': break; | |
7096 | case 'z': break; | |
aa2e0460 | 7097 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; |
3c69baf9 GRK |
7098 | /* start-sanitize-r5900 */ |
7099 | case '0': USE_BITS (OP_MASK_VADDI, OP_SH_VADDI); break; | |
7100 | case '1': USE_BITS (OP_MASK_VUTREG, OP_SH_VUTREG); break; | |
7101 | case '2': USE_BITS (OP_MASK_VUSREG, OP_SH_VUSREG); break; | |
7102 | case '3': USE_BITS (OP_MASK_VUDREG, OP_SH_VUDREG); break; | |
7103 | case '4': USE_BITS (OP_MASK_VUTREG, OP_SH_VUTREG); break; | |
7104 | case '5': USE_BITS (OP_MASK_VUSREG, OP_SH_VUSREG); break; | |
7105 | case '6': USE_BITS (OP_MASK_VUDREG, OP_SH_VUDREG); break; | |
7106 | case '7': | |
7107 | USE_BITS (OP_MASK_VUTREG, OP_SH_VUTREG); | |
7108 | USE_BITS (OP_MASK_VUFTF, OP_SH_VUFTF); | |
7109 | break; | |
7110 | case '8': | |
7111 | USE_BITS (OP_MASK_VUSREG, OP_SH_VUSREG); | |
7112 | USE_BITS (OP_MASK_VUFSF, OP_SH_VUFSF); | |
7113 | break; | |
7114 | case '9': break; | |
7115 | case 'K': break; | |
7116 | case 'X': break; | |
7117 | case 'U': break; | |
7118 | case 'Q': break; | |
7119 | case 'J': break; | |
7120 | case 'O': USE_BITS (OP_MASK_VUCALLMS, OP_SH_VUCALLMS);break; | |
7121 | case '&': USE_BITS (OP_MASK_VUDEST, OP_SH_VUDEST); break; | |
be294de6 | 7122 | case ';': break; |
3c69baf9 GRK |
7123 | case '#': |
7124 | p++; | |
7125 | break; | |
7126 | case '-': break; | |
7127 | case '+': break; | |
7128 | /* end-sanitize-r5900 */ | |
6b34ac5a | 7129 | /* start-sanitize-cygnus */ |
aa2e0460 KR |
7130 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
7131 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
7132 | case '[': break; | |
7133 | case ']': break; | |
6b34ac5a | 7134 | /* end-sanitize-cygnus */ |
aa2e0460 | 7135 | default: |
48401fcf | 7136 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), |
aa2e0460 KR |
7137 | c, opc->name, opc->args); |
7138 | return 0; | |
7139 | } | |
7140 | #undef USE_BITS | |
aa2e0460 KR |
7141 | if (used_bits != 0xffffffff) |
7142 | { | |
48401fcf | 7143 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), |
aa2e0460 KR |
7144 | ~used_bits & 0xffffffff, opc->name, opc->args); |
7145 | return 0; | |
7146 | } | |
7147 | return 1; | |
7148 | } | |
7149 | ||
cc5703cd ILT |
7150 | /* This routine assembles an instruction into its binary format. As a |
7151 | side effect, it sets one of the global variables imm_reloc or | |
7152 | offset_reloc to the type of relocation to do if one of the operands | |
7153 | is an address expression. */ | |
7154 | ||
7155 | static void | |
7156 | mips_ip (str, ip) | |
7157 | char *str; | |
7158 | struct mips_cl_insn *ip; | |
7159 | { | |
7160 | char *s; | |
7161 | const char *args; | |
7162 | char c; | |
7163 | struct mips_opcode *insn; | |
7164 | char *argsStart; | |
7165 | unsigned int regno; | |
7166 | unsigned int lastregno = 0; | |
7167 | char *s_reset; | |
059a6388 | 7168 | char save_c = 0; |
48401fcf | 7169 | int full_opcode_match = 1; |
cc5703cd ILT |
7170 | |
7171 | insn_error = NULL; | |
7172 | ||
059a6388 JL |
7173 | /* If the instruction contains a '.', we first try to match an instruction |
7174 | including the '.'. Then we try again without the '.'. */ | |
7175 | insn = NULL; | |
e2e5acfa | 7176 | for (s = str; *s != '\0' && !isspace(*s); ++s) |
cc5703cd | 7177 | continue; |
059a6388 JL |
7178 | |
7179 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7180 | the call to hash_find. Save the character we replaced just in case we | |
7181 | have to re-parse the instruction. */ | |
1857d1e6 | 7182 | if (isspace (*s)) |
059a6388 JL |
7183 | { |
7184 | save_c = *s; | |
7185 | *s++ = '\0'; | |
7186 | } | |
7187 | ||
7188 | insn = (struct mips_opcode *) hash_find (op_hash, str); | |
1857d1e6 | 7189 | |
059a6388 JL |
7190 | /* If we didn't find the instruction in the opcode table, try again, but |
7191 | this time with just the instruction up to, but not including the | |
7192 | first '.'. */ | |
7193 | if (insn == NULL) | |
cc5703cd | 7194 | { |
059a6388 JL |
7195 | /* Restore the character we overwrite above (if any). */ |
7196 | if (save_c) | |
7197 | *(--s) = save_c; | |
7198 | ||
7199 | /* Scan up to the first '.' or whitespace. */ | |
7200 | for (s = str; *s != '\0' && *s != '.' && !isspace (*s); ++s) | |
7201 | continue; | |
7202 | ||
7203 | /* If we did not find a '.', then we can quit now. */ | |
7204 | if (*s != '.') | |
7205 | { | |
7206 | insn_error = "unrecognized opcode"; | |
7207 | return; | |
7208 | } | |
7209 | ||
7210 | /* Lookup the instruction in the hash table. */ | |
7211 | *s++ = '\0'; | |
7212 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7213 | { | |
7214 | insn_error = "unrecognized opcode"; | |
7215 | return; | |
7216 | } | |
48401fcf TT |
7217 | |
7218 | full_opcode_match = 0; | |
cc5703cd | 7219 | } |
059a6388 | 7220 | |
cc5703cd ILT |
7221 | argsStart = s; |
7222 | for (;;) | |
7223 | { | |
7224 | int insn_isa; | |
a652f74c | 7225 | boolean ok; |
cc5703cd ILT |
7226 | |
7227 | assert (strcmp (insn->name, str) == 0); | |
7228 | ||
1c6f3441 | 7229 | if ((insn->membership & INSN_ISA) == INSN_ISA1) |
931a1858 | 7230 | insn_isa = 1; |
5c6f5923 | 7231 | else if ((insn->membership & INSN_ISA) == INSN_ISA2) |
cc5703cd | 7232 | insn_isa = 2; |
5c6f5923 | 7233 | else if ((insn->membership & INSN_ISA) == INSN_ISA3) |
cc5703cd | 7234 | insn_isa = 3; |
5c6f5923 | 7235 | else if ((insn->membership & INSN_ISA) == INSN_ISA4) |
cc5703cd ILT |
7236 | insn_isa = 4; |
7237 | else | |
931a1858 | 7238 | insn_isa = 15; |
cc5703cd | 7239 | |
a652f74c ILT |
7240 | if (insn_isa <= mips_opts.isa) |
7241 | ok = true; | |
7242 | else if (insn->pinfo == INSN_MACRO) | |
7243 | ok = false; | |
7244 | else if ((mips_4650 && (insn->membership & INSN_4650) != 0) | |
7245 | || (mips_4010 && (insn->membership & INSN_4010) != 0) | |
7246 | || (mips_4100 && (insn->membership & INSN_4100) != 0) | |
2d035a50 GRK |
7247 | /* start-sanitize-vr4320 */ |
7248 | || (mips_4320 && (insn->membership & INSN_4320) != 0) | |
7249 | /* end-sanitize-vr4320 */ | |
42444087 GRK |
7250 | /* start-sanitize-tx49 */ |
7251 | || (mips_4900 && (insn->membership & INSN_4900) != 0) | |
7252 | /* end-sanitize-tx49 */ | |
a652f74c ILT |
7253 | /* start-sanitize-r5900 */ |
7254 | || (mips_5900 && (insn->membership & INSN_5900) != 0) | |
7255 | /* end-sanitize-r5900 */ | |
6b34ac5a | 7256 | /* start-sanitize-cygnus */ |
aa2e0460 | 7257 | || (mips_5400 && (insn->membership & INSN_5400) != 0) |
6b34ac5a | 7258 | /* end-sanitize-cygnus */ |
a652f74c | 7259 | || (mips_3900 && (insn->membership & INSN_3900) != 0)) |
1c6f3441 | 7260 | ok = true; |
a652f74c ILT |
7261 | else |
7262 | ok = false; | |
7263 | ||
b2cf4548 DE |
7264 | if (insn->pinfo != INSN_MACRO) |
7265 | { | |
7266 | if (mips_4650 && (insn->pinfo & FP_D) != 0) | |
7267 | ok = false; | |
7268 | /* start-sanitize-r5900 */ | |
7269 | if (mips_5900 && (insn->pinfo & FP_D) != 0) | |
7270 | ok = false; | |
7271 | /* end-sanitize-r5900 */ | |
7272 | } | |
1c6f3441 | 7273 | |
a652f74c | 7274 | if (! ok) |
cc5703cd ILT |
7275 | { |
7276 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7277 | && strcmp (insn->name, insn[1].name) == 0) | |
7278 | { | |
7279 | ++insn; | |
7280 | continue; | |
7281 | } | |
6fd819cf GRK |
7282 | if (insn_isa == 15 |
7283 | || insn_isa <= mips_opts.isa) | |
48401fcf | 7284 | insn_error = _("opcode not supported on this processor"); |
cc5703cd ILT |
7285 | else |
7286 | { | |
7287 | static char buf[100]; | |
7288 | ||
48401fcf | 7289 | sprintf (buf, _("opcode requires -mips%d or greater"), insn_isa); |
cc5703cd ILT |
7290 | insn_error = buf; |
7291 | } | |
7292 | return; | |
7293 | } | |
8358c818 | 7294 | |
670a50eb ILT |
7295 | ip->insn_mo = insn; |
7296 | ip->insn_opcode = insn->match; | |
7297 | for (args = insn->args;; ++args) | |
7298 | { | |
7299 | if (*s == ' ') | |
7300 | ++s; | |
7301 | switch (*args) | |
7302 | { | |
7303 | case '\0': /* end of args */ | |
7304 | if (*s == '\0') | |
7305 | return; | |
7306 | break; | |
3d3c5039 ILT |
7307 | |
7308 | case ',': | |
670a50eb ILT |
7309 | if (*s++ == *args) |
7310 | continue; | |
7311 | s--; | |
7312 | switch (*++args) | |
7313 | { | |
3d3c5039 ILT |
7314 | case 'r': |
7315 | case 'v': | |
670a50eb ILT |
7316 | ip->insn_opcode |= lastregno << 21; |
7317 | continue; | |
3d3c5039 ILT |
7318 | |
7319 | case 'w': | |
7320 | case 'W': | |
670a50eb ILT |
7321 | ip->insn_opcode |= lastregno << 16; |
7322 | continue; | |
3d3c5039 ILT |
7323 | |
7324 | case 'V': | |
670a50eb ILT |
7325 | ip->insn_opcode |= lastregno << 11; |
7326 | continue; | |
3d3c5039 | 7327 | } |
670a50eb | 7328 | break; |
3d3c5039 ILT |
7329 | |
7330 | case '(': | |
059a6388 | 7331 | /* Handle optional base register. |
670a50eb ILT |
7332 | Either the base register is omitted or |
7333 | we must have a left paren. */ | |
059a6388 JL |
7334 | /* This is dependent on the next operand specifier |
7335 | is a base register specification. */ | |
7336 | assert (args[1] == 'b' || args[1] == '5' | |
7337 | || args[1] == '-' || args[1] == '4'); | |
670a50eb ILT |
7338 | if (*s == '\0') |
7339 | return; | |
3d3c5039 | 7340 | |
670a50eb | 7341 | case ')': /* these must match exactly */ |
6b34ac5a | 7342 | /* start-sanitize-cygnus */ |
aa2e0460 KR |
7343 | case '[': |
7344 | case ']': | |
6b34ac5a | 7345 | /* end-sanitize-cygnus */ |
059a6388 JL |
7346 | /* start-sanitize-r5900 */ |
7347 | case '-': | |
7348 | case '+': | |
7349 | /* end-sanitize-r5900 */ | |
670a50eb | 7350 | if (*s++ == *args) |
3d3c5039 | 7351 | continue; |
670a50eb ILT |
7352 | break; |
7353 | ||
7354 | case '<': /* must be at least one digit */ | |
7355 | /* | |
7356 | * According to the manual, if the shift amount is greater | |
7357 | * than 31 or less than 0 the the shift amount should be | |
7358 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 7359 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
7360 | */ |
7361 | my_getExpression (&imm_expr, s); | |
7362 | check_absolute_expr (ip, &imm_expr); | |
7363 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7364 | { | |
48401fcf | 7365 | as_warn (_("Improper shift amount (%ld)"), |
58d4951d | 7366 | (long) imm_expr.X_add_number); |
9226253a | 7367 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
7368 | } |
7369 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 7370 | imm_expr.X_op = O_absent; |
670a50eb ILT |
7371 | s = expr_end; |
7372 | continue; | |
7373 | ||
56c96faa ILT |
7374 | case '>': /* shift amount minus 32 */ |
7375 | my_getExpression (&imm_expr, s); | |
7376 | check_absolute_expr (ip, &imm_expr); | |
7377 | if ((unsigned long) imm_expr.X_add_number < 32 | |
7378 | || (unsigned long) imm_expr.X_add_number > 63) | |
7379 | break; | |
7380 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
7381 | imm_expr.X_op = O_absent; | |
7382 | s = expr_end; | |
7383 | continue; | |
7384 | ||
059a6388 JL |
7385 | /* start-sanitize-r5900 */ |
7386 | case '0': /* 5 bit signed immediate at 6 */ | |
7387 | my_getExpression (&imm_expr, s); | |
7388 | check_absolute_expr (ip, &imm_expr); | |
7389 | if ((c == '\0' && imm_expr.X_op != O_constant) | |
7390 | || ((imm_expr.X_add_number < -16 | |
7391 | || imm_expr.X_add_number >= 16) | |
7392 | && imm_expr.X_op == O_constant)) | |
7393 | { | |
7394 | if (imm_expr.X_op != O_constant | |
7395 | && imm_expr.X_op != O_big) | |
7396 | insn_error = "absolute expression required"; | |
7397 | else | |
48401fcf | 7398 | as_bad (_("5 bit expression not in range -16..15")); |
059a6388 JL |
7399 | } |
7400 | ip->insn_opcode |= (imm_expr.X_add_number) << 6; | |
7401 | imm_expr.X_op = O_absent; | |
7402 | s = expr_end; | |
7403 | continue; | |
7404 | ||
65a17223 | 7405 | case '9': /* vi27 for vcallmsr */ |
7e656649 RH |
7406 | if (strncmp (s, "$vi27", 5) == 0) |
7407 | s += 5; | |
7408 | else if (strncmp (s, "vi27", 4) == 0) | |
059a6388 JL |
7409 | s += 4; |
7410 | else | |
48401fcf | 7411 | as_bad (_("expected vi27")); |
059a6388 JL |
7412 | continue; |
7413 | ||
981ce186 JL |
7414 | case '#': /* escape character */ |
7415 | /* '#' specifies that we've got an optional suffix to this | |
059a6388 JL |
7416 | operand that must match exactly (if it exists). */ |
7417 | if (*s != '\0' && *s != ',' | |
7418 | && *s != ' ' && *s != '\t' && *s != '\n') | |
7419 | { | |
7420 | if (*s == *(args + 1)) | |
7421 | { | |
7422 | s++; | |
7423 | args++; | |
7424 | continue; | |
7425 | } | |
7426 | break; | |
7427 | } | |
7428 | args++; | |
7429 | continue; | |
7430 | ||
7431 | case 'K': /* DEST operand completer (optional), must | |
7432 | match previous dest if specified. */ | |
7433 | case '&': /* DEST instruction completer */ | |
be294de6 | 7434 | case ';': /* DEST instruction completer, must be xyz */ |
059a6388 JL |
7435 | { |
7436 | int w,x,y,z; | |
7437 | static int last_h; | |
7438 | ||
7439 | w = x = y = z = 0; | |
7440 | ||
7441 | /* Parse the completer. */ | |
7442 | s_reset = s; | |
48401fcf TT |
7443 | while ((!full_opcode_match || *args == 'K') |
7444 | && *s != '\0' && *s != ' ' && *s != ',') | |
059a6388 JL |
7445 | { |
7446 | if (*s == 'w') | |
7447 | w++; | |
7448 | else if (*s == 'x') | |
7449 | x++; | |
7450 | else if (*s == 'y') | |
7451 | y++; | |
7452 | else if (*s == 'z') | |
7453 | z++; | |
7454 | else | |
7455 | { | |
7456 | insn_error = "Invalid dest specification"; | |
48401fcf | 7457 | break; |
059a6388 JL |
7458 | } |
7459 | s++; | |
7460 | } | |
7461 | ||
48401fcf TT |
7462 | if (insn_error) |
7463 | continue; | |
7464 | ||
059a6388 JL |
7465 | /* Each completer can only appear once. */ |
7466 | if (w > 1 || x > 1 || y > 1 || z > 1) | |
7467 | { | |
7468 | insn_error = "Invalid dest specification"; | |
7469 | continue; | |
7470 | } | |
7471 | ||
7472 | /* If this is the opcode completer, then we must insert | |
7473 | the appropriate value into the insn. */ | |
7474 | if (*args == '&') | |
7475 | { | |
48401fcf TT |
7476 | /* Not strictly in the specs, but requested by users. */ |
7477 | if (w == 0 && x == 0 && y == 0 && z == 0) | |
7478 | w = x = y = z = 1; | |
7479 | ||
059a6388 JL |
7480 | ip->insn_opcode |= ((w << 21) | (x << 24) |
7481 | | (y << 23) | (z << 22)); | |
7482 | last_h = (w << 3) | (x << 0) | (y << 1) | (z << 2); | |
7483 | } | |
be294de6 JL |
7484 | else if (*args == ';') |
7485 | { | |
7486 | /* This implicitly has the .xyz completer. */ | |
7487 | if (w == 0 && x == 0 && y == 0 && z == 0) | |
7488 | x = y = z = 1; | |
7489 | ||
7490 | if (w != 0 || x != 1 || y != 1 || z != 1) | |
7491 | { | |
7492 | insn_error = "Invalid dest specification"; | |
7493 | continue; | |
7494 | } | |
7495 | ||
7496 | last_h = (w << 3) | (x << 0) | (y << 1) | (z << 2); | |
7497 | } | |
059a6388 JL |
7498 | else |
7499 | { | |
7500 | int temp; | |
7501 | ||
7502 | /* This is the operand completer, make sure it matches | |
7503 | the previous opcode completer. */ | |
7504 | temp = (w << 3) | (x << 0) | (y << 1) | (z << 2); | |
7505 | if (temp && temp != last_h) | |
7506 | { | |
7507 | insn_error = "DEST field in operand does not match DEST field in instruction"; | |
7508 | continue; | |
7509 | } | |
7510 | ||
7511 | } | |
7512 | ||
7513 | continue; | |
7514 | } | |
7515 | ||
7516 | case 'J': /* vu0 I register */ | |
7517 | if (s[0] == 'I') | |
7518 | s += 1; | |
7519 | else | |
7520 | insn_error = "operand `I' expected"; | |
7521 | continue; | |
7522 | ||
7523 | case 'Q': /* vu0 Q register */ | |
7524 | if (s[0] == 'Q') | |
7525 | s += 1; | |
7526 | else | |
7527 | insn_error = "operand `Q' expected"; | |
7528 | continue; | |
7529 | ||
7530 | case 'X': /* vu0 R register */ | |
7531 | if (s[0] == 'R') | |
7532 | s += 1; | |
7533 | else | |
7534 | insn_error = "operand `R' expected"; | |
7535 | continue; | |
7536 | ||
7537 | case 'U': /* vu0 ACC register */ | |
7538 | if (s[0] == 'A' && s[1] == 'C' && s[2] == 'C') | |
7539 | s += 3; | |
7540 | else | |
7541 | insn_error = "operand `ACC' expected"; | |
7542 | continue; | |
0bc0e337 JL |
7543 | |
7544 | case 'O': | |
7545 | my_getSmallExpression (&imm_expr, s); | |
7546 | imm_reloc = BFD_RELOC_MIPS15_S3; | |
7547 | s = expr_end; | |
7548 | continue; | |
059a6388 JL |
7549 | /* end-sanitize-r5900 */ |
7550 | ||
9226253a | 7551 | case 'k': /* cache code */ |
d8a1c247 | 7552 | case 'h': /* prefx code */ |
9226253a ILT |
7553 | my_getExpression (&imm_expr, s); |
7554 | check_absolute_expr (ip, &imm_expr); | |
7555 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7556 | { | |
48401fcf | 7557 | as_warn (_("Invalid value for `%s' (%lu)"), |
d8a1c247 | 7558 | ip->insn_mo->name, |
9226253a ILT |
7559 | (unsigned long) imm_expr.X_add_number); |
7560 | imm_expr.X_add_number &= 0x1f; | |
7561 | } | |
d8a1c247 KR |
7562 | if (*args == 'k') |
7563 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
7564 | else | |
7565 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
9226253a ILT |
7566 | imm_expr.X_op = O_absent; |
7567 | s = expr_end; | |
7568 | continue; | |
7569 | ||
670a50eb ILT |
7570 | case 'c': /* break code */ |
7571 | my_getExpression (&imm_expr, s); | |
7572 | check_absolute_expr (ip, &imm_expr); | |
7573 | if ((unsigned) imm_expr.X_add_number > 1023) | |
40f0c904 FCE |
7574 | { |
7575 | as_warn (_("Illegal break code (%ld)"), | |
7576 | (long) imm_expr.X_add_number); | |
7577 | imm_expr.X_add_number &= 0x3ff; | |
7578 | } | |
670a50eb | 7579 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 7580 | imm_expr.X_op = O_absent; |
670a50eb ILT |
7581 | s = expr_end; |
7582 | continue; | |
7583 | ||
40f0c904 FCE |
7584 | case 'q': /* lower break code */ |
7585 | my_getExpression (&imm_expr, s); | |
7586 | check_absolute_expr (ip, &imm_expr); | |
7587 | if ((unsigned) imm_expr.X_add_number > 1023) | |
7588 | { | |
7589 | as_warn (_("Illegal lower break code (%ld)"), | |
7590 | (long) imm_expr.X_add_number); | |
7591 | imm_expr.X_add_number &= 0x3ff; | |
7592 | } | |
7593 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
7594 | imm_expr.X_op = O_absent; | |
7595 | s = expr_end; | |
7596 | continue; | |
7597 | ||
918692a5 ILT |
7598 | case 'B': /* syscall code */ |
7599 | my_getExpression (&imm_expr, s); | |
7600 | check_absolute_expr (ip, &imm_expr); | |
7601 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
48401fcf | 7602 | as_warn (_("Illegal syscall code (%ld)"), |
58d4951d | 7603 | (long) imm_expr.X_add_number); |
918692a5 | 7604 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 7605 | imm_expr.X_op = O_absent; |
918692a5 ILT |
7606 | s = expr_end; |
7607 | continue; | |
7608 | ||
0aa07269 ILT |
7609 | case 'C': /* Coprocessor code */ |
7610 | my_getExpression (&imm_expr, s); | |
7611 | check_absolute_expr (ip, &imm_expr); | |
7612 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
7613 | { | |
48401fcf | 7614 | as_warn (_("Coproccesor code > 25 bits (%ld)"), |
58d4951d | 7615 | (long) imm_expr.X_add_number); |
0aa07269 ILT |
7616 | imm_expr.X_add_number &= ((1<<25) - 1); |
7617 | } | |
7618 | ip->insn_opcode |= imm_expr.X_add_number; | |
7619 | imm_expr.X_op = O_absent; | |
7620 | s = expr_end; | |
7621 | continue; | |
7622 | ||
65d2c7d3 JL |
7623 | case 'P': /* Performance register */ |
7624 | my_getExpression (&imm_expr, s); | |
7625 | check_absolute_expr (ip, &imm_expr); | |
7626 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) | |
7627 | { | |
48401fcf | 7628 | as_warn (_("Invalidate performance regster (%ld)"), |
65d2c7d3 JL |
7629 | (long) imm_expr.X_add_number); |
7630 | imm_expr.X_add_number &= 1; | |
7631 | } | |
7632 | ip->insn_opcode |= (imm_expr.X_add_number << 1); | |
7633 | imm_expr.X_op = O_absent; | |
7634 | s = expr_end; | |
7635 | continue; | |
7636 | ||
670a50eb ILT |
7637 | case 'b': /* base register */ |
7638 | case 'd': /* destination register */ | |
7639 | case 's': /* source register */ | |
7640 | case 't': /* target register */ | |
7641 | case 'r': /* both target and source */ | |
7642 | case 'v': /* both dest and source */ | |
7643 | case 'w': /* both dest and target */ | |
918692a5 ILT |
7644 | case 'E': /* coprocessor target register */ |
7645 | case 'G': /* coprocessor destination register */ | |
8358c818 | 7646 | case 'x': /* ignore register name */ |
ff3a5c18 | 7647 | case 'z': /* must be zero register */ |
670a50eb ILT |
7648 | s_reset = s; |
7649 | if (s[0] == '$') | |
7650 | { | |
7e656649 RH |
7651 | /* start-sanitize-r5900 */ |
7652 | /* Allow "$viNN" as coprocessor register name */ | |
7653 | if (mips_5900 | |
7654 | && *args == 'G' | |
7655 | && s[1] == 'v' | |
7656 | && s[2] == 'i') | |
7657 | { | |
7658 | s += 2; | |
7659 | } | |
7660 | /* end-sanitize-r5900 */ | |
7661 | ||
670a50eb ILT |
7662 | if (isdigit (s[1])) |
7663 | { | |
7664 | ++s; | |
7665 | regno = 0; | |
7666 | do | |
7667 | { | |
7668 | regno *= 10; | |
7669 | regno += *s - '0'; | |
7670 | ++s; | |
7671 | } | |
7672 | while (isdigit (*s)); | |
0aa07269 | 7673 | if (regno > 31) |
48401fcf | 7674 | as_bad (_("Invalid register number (%d)"), regno); |
670a50eb | 7675 | } |
0dd2d296 ILT |
7676 | else if (*args == 'E' || *args == 'G') |
7677 | goto notreg; | |
7678 | else | |
670a50eb | 7679 | { |
0aa07269 ILT |
7680 | if (s[1] == 'f' && s[2] == 'p') |
7681 | { | |
7682 | s += 3; | |
9226253a | 7683 | regno = FP; |
0aa07269 ILT |
7684 | } |
7685 | else if (s[1] == 's' && s[2] == 'p') | |
7686 | { | |
7687 | s += 3; | |
9226253a | 7688 | regno = SP; |
0aa07269 ILT |
7689 | } |
7690 | else if (s[1] == 'g' && s[2] == 'p') | |
7691 | { | |
7692 | s += 3; | |
9226253a | 7693 | regno = GP; |
0aa07269 ILT |
7694 | } |
7695 | else if (s[1] == 'a' && s[2] == 't') | |
7696 | { | |
7697 | s += 3; | |
9226253a | 7698 | regno = AT; |
0aa07269 | 7699 | } |
b2b8c24e ILT |
7700 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
7701 | { | |
7702 | s += 4; | |
7703 | regno = KT0; | |
7704 | } | |
7705 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7706 | { | |
7707 | s += 4; | |
7708 | regno = KT1; | |
7709 | } | |
efec4a28 DP |
7710 | else if (itbl_have_entries) |
7711 | { | |
7712 | char *p, *n; | |
7713 | int r; | |
7714 | ||
7715 | p = s+1; /* advance past '$' */ | |
9218cee0 | 7716 | n = itbl_get_field (&p); /* n is name */ |
efec4a28 DP |
7717 | |
7718 | /* See if this is a register defined in an | |
7719 | itbl entry */ | |
9218cee0 ILT |
7720 | r = itbl_get_reg_val (n); |
7721 | if (r) | |
efec4a28 | 7722 | { |
9218cee0 ILT |
7723 | /* Get_field advances to the start of |
7724 | the next field, so we need to back | |
7725 | rack to the end of the last field. */ | |
efec4a28 | 7726 | if (p) |
9218cee0 | 7727 | s = p - 1; |
efec4a28 | 7728 | else |
9218cee0 | 7729 | s = strchr (s,'\0'); |
efec4a28 DP |
7730 | regno = r; |
7731 | } | |
7732 | else | |
7733 | goto notreg; | |
7734 | } | |
0aa07269 ILT |
7735 | else |
7736 | goto notreg; | |
670a50eb | 7737 | } |
9753202d | 7738 | if (regno == AT |
3c83da8a | 7739 | && ! mips_opts.noat |
9753202d ILT |
7740 | && *args != 'E' |
7741 | && *args != 'G') | |
48401fcf | 7742 | as_warn (_("Used $at without \".set noat\"")); |
670a50eb ILT |
7743 | c = *args; |
7744 | if (*s == ' ') | |
7745 | s++; | |
7746 | if (args[1] != *s) | |
7747 | { | |
7748 | if (c == 'r' || c == 'v' || c == 'w') | |
7749 | { | |
7750 | regno = lastregno; | |
7751 | s = s_reset; | |
7752 | args++; | |
7753 | } | |
7754 | } | |
ff3a5c18 ILT |
7755 | /* 'z' only matches $0. */ |
7756 | if (c == 'z' && regno != 0) | |
7757 | break; | |
efec4a28 DP |
7758 | |
7759 | /* Now that we have assembled one operand, we use the args string | |
7760 | * to figure out where it goes in the instruction. */ | |
670a50eb ILT |
7761 | switch (c) |
7762 | { | |
3d3c5039 ILT |
7763 | case 'r': |
7764 | case 's': | |
7765 | case 'v': | |
7766 | case 'b': | |
670a50eb ILT |
7767 | ip->insn_opcode |= regno << 21; |
7768 | break; | |
3d3c5039 | 7769 | case 'd': |
918692a5 | 7770 | case 'G': |
670a50eb ILT |
7771 | ip->insn_opcode |= regno << 11; |
7772 | break; | |
3d3c5039 ILT |
7773 | case 'w': |
7774 | case 't': | |
918692a5 | 7775 | case 'E': |
670a50eb | 7776 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
7777 | break; |
7778 | case 'x': | |
7779 | /* This case exists because on the r3000 trunc | |
7780 | expands into a macro which requires a gp | |
7781 | register. On the r6000 or r4000 it is | |
7782 | assembled into a single instruction which | |
7783 | ignores the register. Thus the insn version | |
7784 | is MIPS_ISA2 and uses 'x', and the macro | |
7785 | version is MIPS_ISA1 and uses 't'. */ | |
7786 | break; | |
ff3a5c18 ILT |
7787 | case 'z': |
7788 | /* This case is for the div instruction, which | |
7789 | acts differently if the destination argument | |
7790 | is $0. This only matches $0, and is checked | |
7791 | outside the switch. */ | |
7792 | break; | |
efec4a28 DP |
7793 | case 'D': |
7794 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
7795 | break; | |
9218cee0 ILT |
7796 | /* What about all other operands like 'i', which |
7797 | can be specified in the opcode table? */ | |
3d3c5039 | 7798 | } |
670a50eb ILT |
7799 | lastregno = regno; |
7800 | continue; | |
3d3c5039 ILT |
7801 | } |
7802 | notreg: | |
670a50eb ILT |
7803 | switch (*args++) |
7804 | { | |
3d3c5039 ILT |
7805 | case 'r': |
7806 | case 'v': | |
670a50eb ILT |
7807 | ip->insn_opcode |= lastregno << 21; |
7808 | continue; | |
3d3c5039 | 7809 | case 'w': |
670a50eb ILT |
7810 | ip->insn_opcode |= lastregno << 16; |
7811 | continue; | |
3d3c5039 | 7812 | } |
670a50eb | 7813 | break; |
3d3c5039 | 7814 | |
670a50eb ILT |
7815 | case 'D': /* floating point destination register */ |
7816 | case 'S': /* floating point source register */ | |
7817 | case 'T': /* floating point target register */ | |
d8a1c247 | 7818 | case 'R': /* floating point source register */ |
3d3c5039 ILT |
7819 | case 'V': |
7820 | case 'W': | |
059a6388 JL |
7821 | /* start-sanitize-r5900 */ |
7822 | case '1': /* vu0 fp reg position 1 */ | |
7823 | case '2': /* vu0 fp reg position 2 */ | |
7824 | case '3': /* vu0 fp reg position 3 */ | |
7825 | case '4': /* vu0 int reg position 1 */ | |
7826 | case '5': /* vu0 int reg position 2 */ | |
7827 | case '6': /* vu0 int reg position 3 */ | |
7828 | case '7': /* vu0 fp reg with ftf modifier */ | |
7829 | case '8': /* vu0 fp reg with fsf modifier */ | |
7830 | /* end-sanitize-r5900 */ | |
670a50eb ILT |
7831 | s_reset = s; |
7832 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
7833 | { | |
7834 | s += 2; | |
7835 | regno = 0; | |
7836 | do | |
7837 | { | |
7838 | regno *= 10; | |
7839 | regno += *s - '0'; | |
7840 | ++s; | |
7841 | } | |
7842 | while (isdigit (*s)); | |
7843 | ||
7844 | if (regno > 31) | |
48401fcf | 7845 | as_bad (_("Invalid float register number (%d)"), regno); |
670a50eb | 7846 | |
9226253a | 7847 | if ((regno & 1) != 0 |
3c83da8a | 7848 | && mips_opts.isa < 3 |
538034cf ILT |
7849 | && ! (strcmp (str, "mtc1") == 0 |
7850 | || strcmp (str, "mfc1") == 0 | |
7851 | || strcmp (str, "lwc1") == 0 | |
7852 | || strcmp (str, "swc1") == 0 | |
7853 | || strcmp (str, "l.s") == 0 | |
7854 | || strcmp (str, "s.s") == 0)) | |
48401fcf | 7855 | as_warn (_("Float register should be even, was %d"), |
670a50eb ILT |
7856 | regno); |
7857 | ||
7858 | c = *args; | |
7859 | if (*s == ' ') | |
7860 | s++; | |
7861 | if (args[1] != *s) | |
7862 | { | |
7863 | if (c == 'V' || c == 'W') | |
7864 | { | |
7865 | regno = lastregno; | |
7866 | s = s_reset; | |
7867 | args++; | |
3d3c5039 ILT |
7868 | } |
7869 | } | |
670a50eb ILT |
7870 | switch (c) |
7871 | { | |
3d3c5039 | 7872 | case 'D': |
670a50eb ILT |
7873 | ip->insn_opcode |= regno << 6; |
7874 | break; | |
3d3c5039 ILT |
7875 | case 'V': |
7876 | case 'S': | |
670a50eb ILT |
7877 | ip->insn_opcode |= regno << 11; |
7878 | break; | |
3d3c5039 ILT |
7879 | case 'W': |
7880 | case 'T': | |
670a50eb | 7881 | ip->insn_opcode |= regno << 16; |
d8a1c247 KR |
7882 | break; |
7883 | case 'R': | |
7884 | ip->insn_opcode |= regno << 21; | |
7885 | break; | |
3d3c5039 | 7886 | } |
670a50eb ILT |
7887 | lastregno = regno; |
7888 | continue; | |
3d3c5039 | 7889 | } |
059a6388 JL |
7890 | |
7891 | /* start-sanitize-r5900 */ | |
7e656649 RH |
7892 | /* Handle vf and vi regsiters for vu0. Handle optional |
7893 | `$' prefix. */ | |
7894 | ||
7895 | if ((s[0] == 'v' | |
7896 | && (s[1] == 'f' || s[1] == 'i') | |
7897 | && isdigit (s[2])) | |
7898 | || | |
7899 | (s[0] == '$' | |
7900 | && s[1] == 'v' | |
7901 | && (s[2] == 'f' || s[2] == 'i') | |
7902 | && isdigit (s[3]))) | |
7903 | { | |
7904 | if(s[0] == '$') | |
7905 | ++s; | |
059a6388 JL |
7906 | s += 2; |
7907 | regno = 0; | |
7908 | do | |
7909 | { | |
7910 | regno *= 10; | |
7911 | regno += *s - '0'; | |
7912 | ++s; | |
7913 | } | |
7914 | while (isdigit (*s)); | |
7915 | ||
7916 | if (regno > 31) | |
48401fcf | 7917 | as_bad (_("Invalid vu0 register number (%d)"), regno); |
059a6388 JL |
7918 | |
7919 | c = *args; | |
7920 | ||
7921 | if (c == '7' || c == '8') | |
7922 | { | |
7923 | int value; | |
7924 | ||
7925 | switch (*s) | |
7926 | { | |
7927 | case 'w': | |
7928 | value = 3; | |
7929 | s++; | |
7930 | ip->insn_opcode |= value << (c == '7' ? 23 : 21); | |
7931 | break; | |
7932 | case 'x': | |
7933 | value = 0; | |
7934 | s++; | |
7935 | ip->insn_opcode |= value << (c == '7' ? 23 : 21); | |
7936 | break; | |
7937 | case 'y': | |
7938 | value = 1; | |
7939 | s++; | |
7940 | ip->insn_opcode |= value << (c == '7' ? 23 : 21); | |
7941 | break; | |
7942 | case 'z': | |
7943 | value = 2; | |
7944 | s++; | |
7945 | ip->insn_opcode |= value << (c == '7' ? 23 : 21); | |
7946 | break; | |
7947 | default: | |
48401fcf | 7948 | as_bad (_("Invalid FSF/FTF specification")); |
059a6388 JL |
7949 | } |
7950 | } | |
7951 | ||
7952 | if (*s == ' ') | |
7953 | s++; | |
7954 | if (args[1] != *s) | |
7955 | { | |
7956 | if (c == 'V' || c == 'W') | |
7957 | { | |
7958 | regno = lastregno; | |
7959 | s = s_reset; | |
7960 | args++; | |
7961 | } | |
7962 | } | |
7963 | switch (c) | |
7964 | { | |
7965 | case '1': | |
7966 | case '4': | |
7967 | case '7': | |
7968 | ip->insn_opcode |= regno << 16; | |
7969 | break; | |
7970 | case '2': | |
7971 | case '5': | |
7972 | case '8': | |
7973 | ip->insn_opcode |= regno << 11; | |
7974 | break; | |
7975 | case '3': | |
7976 | case '6': | |
7977 | ip->insn_opcode |= regno << 6; | |
7978 | break; | |
7979 | } | |
7980 | lastregno = regno; | |
7981 | continue; | |
7982 | } | |
7983 | /* end-sanitize-r5900 */ | |
7984 | ||
670a50eb ILT |
7985 | switch (*args++) |
7986 | { | |
3d3c5039 | 7987 | case 'V': |
670a50eb ILT |
7988 | ip->insn_opcode |= lastregno << 11; |
7989 | continue; | |
3d3c5039 | 7990 | case 'W': |
670a50eb ILT |
7991 | ip->insn_opcode |= lastregno << 16; |
7992 | continue; | |
3d3c5039 | 7993 | } |
670a50eb | 7994 | break; |
3d3c5039 ILT |
7995 | |
7996 | case 'I': | |
670a50eb | 7997 | my_getExpression (&imm_expr, s); |
9753202d ILT |
7998 | if (imm_expr.X_op != O_big |
7999 | && imm_expr.X_op != O_constant) | |
48401fcf | 8000 | insn_error = _("absolute expression required"); |
670a50eb ILT |
8001 | s = expr_end; |
8002 | continue; | |
3d3c5039 ILT |
8003 | |
8004 | case 'A': | |
670a50eb ILT |
8005 | my_getExpression (&offset_expr, s); |
8006 | imm_reloc = BFD_RELOC_32; | |
8007 | s = expr_end; | |
8008 | continue; | |
3d3c5039 ILT |
8009 | |
8010 | case 'F': | |
19ed8960 ILT |
8011 | case 'L': |
8012 | case 'f': | |
8013 | case 'l': | |
8014 | { | |
8015 | int f64; | |
8016 | char *save_in; | |
8017 | char *err; | |
8018 | unsigned char temp[8]; | |
604633ae ILT |
8019 | int len; |
8020 | unsigned int length; | |
19ed8960 ILT |
8021 | segT seg; |
8022 | subsegT subseg; | |
8023 | char *p; | |
8024 | ||
8025 | /* These only appear as the last operand in an | |
8026 | instruction, and every instruction that accepts | |
8027 | them in any variant accepts them in all variants. | |
8028 | This means we don't have to worry about backing out | |
8029 | any changes if the instruction does not match. | |
8030 | ||
8031 | The difference between them is the size of the | |
8032 | floating point constant and where it goes. For 'F' | |
8033 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8034 | is 32 bits. Where the constant is placed is based | |
8035 | on how the MIPS assembler does things: | |
8036 | F -- .rdata | |
8037 | L -- .lit8 | |
8038 | f -- immediate value | |
8039 | l -- .lit4 | |
0dd2d296 | 8040 | |
55933a58 ILT |
8041 | The .lit4 and .lit8 sections are only used if |
8042 | permitted by the -G argument. | |
8043 | ||
8044 | When generating embedded PIC code, we use the | |
8045 | .lit8 section but not the .lit4 section (we can do | |
8046 | .lit4 inline easily; we need to put .lit8 | |
8047 | somewhere in the data segment, and using .lit8 | |
8048 | permits the linker to eventually combine identical | |
8049 | .lit8 entries). */ | |
19ed8960 ILT |
8050 | |
8051 | f64 = *args == 'F' || *args == 'L'; | |
8052 | ||
8053 | save_in = input_line_pointer; | |
8054 | input_line_pointer = s; | |
604633ae ILT |
8055 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
8056 | length = len; | |
19ed8960 ILT |
8057 | s = input_line_pointer; |
8058 | input_line_pointer = save_in; | |
8059 | if (err != NULL && *err != '\0') | |
8060 | { | |
48401fcf | 8061 | as_bad (_("Bad floating point constant: %s"), err); |
19ed8960 ILT |
8062 | memset (temp, '\0', sizeof temp); |
8063 | length = f64 ? 8 : 4; | |
8064 | } | |
8065 | ||
8066 | assert (length == (f64 ? 8 : 4)); | |
8067 | ||
0dd2d296 | 8068 | if (*args == 'f' |
55933a58 | 8069 | || (*args == 'l' |
1dc1e798 KR |
8070 | && (! USE_GLOBAL_POINTER_OPT |
8071 | || mips_pic == EMBEDDED_PIC | |
a5586bdc ILT |
8072 | || g_switch_value < 4 |
8073 | || (temp[0] == 0 && temp[1] == 0) | |
8074 | || (temp[2] == 0 && temp[3] == 0)))) | |
19ed8960 ILT |
8075 | { |
8076 | imm_expr.X_op = O_constant; | |
b9129c6f | 8077 | if (! target_big_endian) |
a5586bdc | 8078 | imm_expr.X_add_number = bfd_getl32 (temp); |
19ed8960 | 8079 | else |
a5586bdc ILT |
8080 | imm_expr.X_add_number = bfd_getb32 (temp); |
8081 | } | |
8082 | else if (length > 4 | |
8083 | && ((temp[0] == 0 && temp[1] == 0) | |
8084 | || (temp[2] == 0 && temp[3] == 0)) | |
8085 | && ((temp[4] == 0 && temp[5] == 0) | |
8086 | || (temp[6] == 0 && temp[7] == 0))) | |
8087 | { | |
8088 | /* The value is simple enough to load with a | |
8089 | couple of instructions. In mips1 mode, set | |
8090 | imm_expr to the high order 32 bits and | |
8091 | offset_expr to the low order 32 bits. | |
8092 | Otherwise, set imm_expr to the entire 64 bit | |
8093 | constant. */ | |
8094 | if (mips_opts.isa < 3) | |
8095 | { | |
8096 | imm_expr.X_op = O_constant; | |
8097 | offset_expr.X_op = O_constant; | |
8098 | if (! target_big_endian) | |
8099 | { | |
8100 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8101 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8102 | } | |
8103 | else | |
8104 | { | |
8105 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8106 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8107 | } | |
8108 | if (offset_expr.X_add_number == 0) | |
8109 | offset_expr.X_op = O_absent; | |
8110 | } | |
8111 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8112 | { | |
8113 | imm_expr.X_op = O_constant; | |
8114 | if (! target_big_endian) | |
8115 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8116 | else | |
8117 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8118 | } | |
8119 | else | |
8120 | { | |
8121 | imm_expr.X_op = O_big; | |
8122 | imm_expr.X_add_number = 4; | |
8123 | if (! target_big_endian) | |
8124 | { | |
8125 | generic_bignum[0] = bfd_getl16 (temp); | |
8126 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8127 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8128 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8129 | } | |
8130 | else | |
8131 | { | |
8132 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8133 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8134 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8135 | generic_bignum[3] = bfd_getb16 (temp); | |
8136 | } | |
8137 | } | |
19ed8960 ILT |
8138 | } |
8139 | else | |
8140 | { | |
0dd2d296 ILT |
8141 | const char *newname; |
8142 | segT new_seg; | |
8143 | ||
19ed8960 ILT |
8144 | /* Switch to the right section. */ |
8145 | seg = now_seg; | |
8146 | subseg = now_subseg; | |
8147 | switch (*args) | |
8148 | { | |
0dd2d296 | 8149 | default: /* unused default case avoids warnings. */ |
19ed8960 | 8150 | case 'L': |
1113140a | 8151 | newname = RDATA_SECTION_NAME; |
1dc1e798 | 8152 | if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
1113140a | 8153 | newname = ".lit8"; |
0dd2d296 ILT |
8154 | break; |
8155 | case 'F': | |
d2c71068 | 8156 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
8157 | break; |
8158 | case 'l': | |
1dc1e798 KR |
8159 | assert (!USE_GLOBAL_POINTER_OPT |
8160 | || g_switch_value >= 4); | |
0dd2d296 | 8161 | newname = ".lit4"; |
19ed8960 ILT |
8162 | break; |
8163 | } | |
0dd2d296 | 8164 | new_seg = subseg_new (newname, (subsegT) 0); |
9b61d62b ILT |
8165 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
8166 | bfd_set_section_flags (stdoutput, new_seg, | |
8167 | (SEC_ALLOC | |
8168 | | SEC_LOAD | |
8169 | | SEC_READONLY | |
8170 | | SEC_DATA)); | |
e2e5acfa JW |
8171 | frag_align (*args == 'l' ? 2 : 3, 0, 0); |
8172 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8173 | && strcmp (TARGET_OS, "elf") != 0) | |
1dc1e798 KR |
8174 | record_alignment (new_seg, 4); |
8175 | else | |
8176 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
19ed8960 | 8177 | if (seg == now_seg) |
48401fcf | 8178 | as_bad (_("Can't use floating point insn in this section")); |
19ed8960 ILT |
8179 | |
8180 | /* Set the argument to the current address in the | |
6e8dda9c | 8181 | section. */ |
19ed8960 ILT |
8182 | offset_expr.X_op = O_symbol; |
8183 | offset_expr.X_add_symbol = | |
8184 | symbol_new ("L0\001", now_seg, | |
8185 | (valueT) frag_now_fix (), frag_now); | |
8186 | offset_expr.X_add_number = 0; | |
8187 | ||
8188 | /* Put the floating point number into the section. */ | |
604633ae | 8189 | p = frag_more ((int) length); |
19ed8960 ILT |
8190 | memcpy (p, temp, length); |
8191 | ||
8192 | /* Switch back to the original section. */ | |
8193 | subseg_set (seg, subseg); | |
8194 | } | |
8195 | } | |
670a50eb ILT |
8196 | continue; |
8197 | ||
8198 | case 'i': /* 16 bit unsigned immediate */ | |
8199 | case 'j': /* 16 bit signed immediate */ | |
8200 | imm_reloc = BFD_RELOC_LO16; | |
8201 | c = my_getSmallExpression (&imm_expr, s); | |
344a8d61 | 8202 | if (c != '\0') |
670a50eb ILT |
8203 | { |
8204 | if (c != 'l') | |
8205 | { | |
5ac34ac3 | 8206 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
8207 | imm_expr.X_add_number = |
8208 | (imm_expr.X_add_number >> 16) & 0xffff; | |
8209 | else if (c == 'h') | |
867a58b3 ILT |
8210 | { |
8211 | imm_reloc = BFD_RELOC_HI16_S; | |
8212 | imm_unmatched_hi = true; | |
8213 | } | |
670a50eb ILT |
8214 | else |
8215 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 8216 | } |
6b34ac5a ILT |
8217 | else if (imm_expr.X_op == O_constant) |
8218 | imm_expr.X_add_number &= 0xffff; | |
670a50eb | 8219 | } |
670a50eb ILT |
8220 | if (*args == 'i') |
8221 | { | |
344a8d61 | 8222 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
8223 | || ((imm_expr.X_add_number < 0 |
8224 | || imm_expr.X_add_number >= 0x10000) | |
8225 | && imm_expr.X_op == O_constant)) | |
99c24539 ILT |
8226 | { |
8227 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8228 | !strcmp (insn->name, insn[1].name)) | |
8229 | break; | |
9753202d ILT |
8230 | if (imm_expr.X_op != O_constant |
8231 | && imm_expr.X_op != O_big) | |
48401fcf | 8232 | insn_error = _("absolute expression required"); |
9753202d | 8233 | else |
48401fcf | 8234 | as_bad (_("16 bit expression not in range 0..65535")); |
99c24539 | 8235 | } |
670a50eb ILT |
8236 | } |
8237 | else | |
8238 | { | |
d9aba805 ILT |
8239 | int more; |
8240 | offsetT max; | |
8241 | ||
be22008b ILT |
8242 | /* The upper bound should be 0x8000, but |
8243 | unfortunately the MIPS assembler accepts numbers | |
8244 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
8245 | we want to be compatible. We only permit this |
8246 | extended range for an instruction which does not | |
8247 | provide any further alternates, since those | |
8248 | alternates may handle other cases. People should | |
8249 | use the numbers they mean, rather than relying on | |
8250 | a mysterious sign extension. */ | |
8251 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8252 | strcmp (insn->name, insn[1].name) == 0); | |
8253 | if (more) | |
8254 | max = 0x8000; | |
8255 | else | |
8256 | max = 0x10000; | |
344a8d61 | 8257 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
8258 | || ((imm_expr.X_add_number < -0x8000 |
8259 | || imm_expr.X_add_number >= max) | |
8260 | && imm_expr.X_op == O_constant) | |
d8a1c247 KR |
8261 | || (more |
8262 | && imm_expr.X_add_number < 0 | |
3c83da8a | 8263 | && mips_opts.isa >= 3 |
d8a1c247 KR |
8264 | && imm_expr.X_unsigned |
8265 | && sizeof (imm_expr.X_add_number) <= 4)) | |
99c24539 | 8266 | { |
d9aba805 | 8267 | if (more) |
99c24539 | 8268 | break; |
9753202d ILT |
8269 | if (imm_expr.X_op != O_constant |
8270 | && imm_expr.X_op != O_big) | |
48401fcf | 8271 | insn_error = _("absolute expression required"); |
9753202d | 8272 | else |
48401fcf | 8273 | as_bad (_("16 bit expression not in range -32768..32767")); |
99c24539 | 8274 | } |
3d3c5039 | 8275 | } |
670a50eb ILT |
8276 | s = expr_end; |
8277 | continue; | |
8278 | ||
8279 | case 'o': /* 16 bit offset */ | |
8280 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
8281 | |
8282 | /* If this value won't fit into a 16 bit offset, then go | |
8283 | find a macro that will generate the 32 bit offset | |
8284 | code pattern. As a special hack, we accept the | |
8285 | difference of two local symbols as a constant. This | |
8286 | is required to suppose embedded PIC switches, which | |
8287 | use an instruction which looks like | |
8288 | lw $4,$L12-$LS12($4) | |
8289 | The problem with handling this in a more general | |
8290 | fashion is that the macro function doesn't expect to | |
8291 | see anything which can be handled in a single | |
8292 | constant instruction. */ | |
6f0b87c3 SS |
8293 | if (c == 0 |
8294 | && (offset_expr.X_op != O_constant | |
8295 | || offset_expr.X_add_number >= 0x8000 | |
8296 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
8297 | && (mips_pic != EMBEDDED_PIC |
8298 | || offset_expr.X_op != O_subtract | |
9da4c5d1 ILT |
8299 | || now_seg != text_section |
8300 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
8301 | != text_section))) | |
670a50eb | 8302 | break; |
3d3c5039 | 8303 | |
670a50eb ILT |
8304 | offset_reloc = BFD_RELOC_LO16; |
8305 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
8306 | { |
8307 | assert (offset_expr.X_op == O_constant); | |
8308 | offset_expr.X_add_number = | |
8309 | (offset_expr.X_add_number >> 16) & 0xffff; | |
8310 | } | |
cc5703cd ILT |
8311 | s = expr_end; |
8312 | continue; | |
8313 | ||
8314 | case 'p': /* pc relative offset */ | |
8315 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
8316 | my_getExpression (&offset_expr, s); | |
8317 | s = expr_end; | |
8318 | continue; | |
8319 | ||
8320 | case 'u': /* upper 16 bits */ | |
8321 | c = my_getSmallExpression (&imm_expr, s); | |
cc5703cd ILT |
8322 | imm_reloc = BFD_RELOC_LO16; |
8323 | if (c) | |
8324 | { | |
8325 | if (c != 'l') | |
8326 | { | |
8327 | if (imm_expr.X_op == O_constant) | |
8328 | imm_expr.X_add_number = | |
8329 | (imm_expr.X_add_number >> 16) & 0xffff; | |
8330 | else if (c == 'h') | |
8331 | { | |
8332 | imm_reloc = BFD_RELOC_HI16_S; | |
8333 | imm_unmatched_hi = true; | |
8334 | } | |
8335 | else | |
8336 | imm_reloc = BFD_RELOC_HI16; | |
8337 | } | |
6b34ac5a ILT |
8338 | else if (imm_expr.X_op == O_constant) |
8339 | imm_expr.X_add_number &= 0xffff; | |
cc5703cd | 8340 | } |
6b34ac5a ILT |
8341 | if (imm_expr.X_op == O_constant |
8342 | && (imm_expr.X_add_number < 0 | |
8343 | || imm_expr.X_add_number >= 0x10000)) | |
8344 | as_bad (_("lui expression not in range 0..65535")); | |
cc5703cd ILT |
8345 | s = expr_end; |
8346 | continue; | |
8347 | ||
8348 | case 'a': /* 26 bit address */ | |
8349 | my_getExpression (&offset_expr, s); | |
8350 | s = expr_end; | |
8351 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
8352 | continue; | |
8353 | ||
8354 | case 'N': /* 3 bit branch condition code */ | |
8355 | case 'M': /* 3 bit compare condition code */ | |
8356 | if (strncmp (s, "$fcc", 4) != 0) | |
8357 | break; | |
8358 | s += 4; | |
8359 | regno = 0; | |
8360 | do | |
8361 | { | |
8362 | regno *= 10; | |
8363 | regno += *s - '0'; | |
8364 | ++s; | |
8365 | } | |
8366 | while (isdigit (*s)); | |
8367 | if (regno > 7) | |
48401fcf | 8368 | as_bad (_("invalid condition code register $fcc%d"), regno); |
cc5703cd ILT |
8369 | if (*args == 'N') |
8370 | ip->insn_opcode |= regno << OP_SH_BCC; | |
8371 | else | |
8372 | ip->insn_opcode |= regno << OP_SH_CCC; | |
8373 | continue; | |
8374 | ||
6b34ac5a | 8375 | /* start-sanitize-cygnus */ |
b3ed1af3 KR |
8376 | case 'e': /* must be at least one digit */ |
8377 | my_getExpression (&imm_expr, s); | |
8378 | check_absolute_expr (ip, &imm_expr); | |
8379 | if ((unsigned long) imm_expr.X_add_number > (unsigned long) OP_MASK_VECBYTE) | |
8380 | { | |
48401fcf | 8381 | as_bad (_("bad byte vector index (%ld)"), |
b3ed1af3 KR |
8382 | (long) imm_expr.X_add_number); |
8383 | imm_expr.X_add_number = imm_expr.X_add_number; | |
8384 | } | |
8385 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; | |
8386 | imm_expr.X_op = O_absent; | |
8387 | s = expr_end; | |
8388 | continue; | |
8389 | ||
8390 | case '%': | |
8391 | my_getExpression (&imm_expr, s); | |
8392 | check_absolute_expr (ip, &imm_expr); | |
8393 | if ((unsigned long) imm_expr.X_add_number > (unsigned long) OP_MASK_VECALIGN) | |
8394 | { | |
48401fcf | 8395 | as_bad (_("bad byte vector index (%ld)"), |
b3ed1af3 KR |
8396 | (long) imm_expr.X_add_number); |
8397 | imm_expr.X_add_number = imm_expr.X_add_number; | |
8398 | } | |
8399 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; | |
8400 | imm_expr.X_op = O_absent; | |
8401 | s = expr_end; | |
8402 | continue; | |
8403 | ||
6b34ac5a | 8404 | /* end-sanitize-cygnus */ |
cc5703cd | 8405 | default: |
48401fcf | 8406 | as_bad (_("bad char = '%c'\n"), *args); |
cc5703cd ILT |
8407 | internalError (); |
8408 | } | |
8409 | break; | |
8410 | } | |
8411 | /* Args don't match. */ | |
8412 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8413 | !strcmp (insn->name, insn[1].name)) | |
8414 | { | |
8415 | ++insn; | |
8416 | s = argsStart; | |
8417 | continue; | |
8418 | } | |
48401fcf | 8419 | insn_error = _("illegal operands"); |
cc5703cd ILT |
8420 | return; |
8421 | } | |
8422 | } | |
8423 | ||
8424 | /* This routine assembles an instruction into its binary format when | |
8425 | assembling for the mips16. As a side effect, it sets one of the | |
8426 | global variables imm_reloc or offset_reloc to the type of | |
8728fa92 ILT |
8427 | relocation to do if one of the operands is an address expression. |
8428 | It also sets mips16_small and mips16_ext if the user explicitly | |
8429 | requested a small or extended instruction. */ | |
cc5703cd ILT |
8430 | |
8431 | static void | |
8432 | mips16_ip (str, ip) | |
8433 | char *str; | |
8434 | struct mips_cl_insn *ip; | |
8435 | { | |
8436 | char *s; | |
cc5703cd ILT |
8437 | const char *args; |
8438 | struct mips_opcode *insn; | |
8439 | char *argsstart; | |
8440 | unsigned int regno; | |
8441 | unsigned int lastregno = 0; | |
8442 | char *s_reset; | |
8443 | ||
8444 | insn_error = NULL; | |
8445 | ||
8728fa92 ILT |
8446 | mips16_small = false; |
8447 | mips16_ext = false; | |
cc5703cd ILT |
8448 | |
8449 | for (s = str; islower (*s); ++s) | |
8450 | ; | |
8451 | switch (*s) | |
8452 | { | |
8453 | case '\0': | |
8454 | break; | |
8455 | ||
8456 | case ' ': | |
8457 | *s++ = '\0'; | |
8458 | break; | |
8459 | ||
8460 | case '.': | |
8461 | if (s[1] == 't' && s[2] == ' ') | |
8462 | { | |
8463 | *s = '\0'; | |
8728fa92 | 8464 | mips16_small = true; |
cc5703cd ILT |
8465 | s += 3; |
8466 | break; | |
8467 | } | |
8468 | else if (s[1] == 'e' && s[2] == ' ') | |
8469 | { | |
8470 | *s = '\0'; | |
8728fa92 | 8471 | mips16_ext = true; |
cc5703cd ILT |
8472 | s += 3; |
8473 | break; | |
8474 | } | |
8475 | /* Fall through. */ | |
8476 | default: | |
48401fcf | 8477 | insn_error = _("unknown opcode"); |
cc5703cd ILT |
8478 | return; |
8479 | } | |
8480 | ||
3c83da8a | 8481 | if (mips_opts.noautoextend && ! mips16_ext) |
8728fa92 ILT |
8482 | mips16_small = true; |
8483 | ||
cc5703cd ILT |
8484 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) |
8485 | { | |
48401fcf | 8486 | insn_error = _("unrecognized opcode"); |
cc5703cd ILT |
8487 | return; |
8488 | } | |
8489 | ||
8490 | argsstart = s; | |
8491 | for (;;) | |
8492 | { | |
8493 | assert (strcmp (insn->name, str) == 0); | |
8494 | ||
8495 | ip->insn_mo = insn; | |
8496 | ip->insn_opcode = insn->match; | |
8497 | ip->use_extend = false; | |
8498 | imm_expr.X_op = O_absent; | |
8499 | imm_reloc = BFD_RELOC_UNUSED; | |
8500 | offset_expr.X_op = O_absent; | |
8501 | offset_reloc = BFD_RELOC_UNUSED; | |
8502 | for (args = insn->args; 1; ++args) | |
8503 | { | |
8504 | int c; | |
8505 | ||
8506 | if (*s == ' ') | |
8507 | ++s; | |
8508 | ||
8509 | /* In this switch statement we call break if we did not find | |
8510 | a match, continue if we did find a match, or return if we | |
8511 | are done. */ | |
8512 | ||
8513 | c = *args; | |
8514 | switch (c) | |
8515 | { | |
8516 | case '\0': | |
8517 | if (*s == '\0') | |
8518 | { | |
8519 | /* Stuff the immediate value in now, if we can. */ | |
8520 | if (imm_expr.X_op == O_constant | |
8521 | && imm_reloc > BFD_RELOC_UNUSED | |
8522 | && insn->pinfo != INSN_MACRO) | |
8523 | { | |
15e69f98 ILT |
8524 | mips16_immed ((char *) NULL, 0, |
8525 | imm_reloc - BFD_RELOC_UNUSED, | |
8728fa92 ILT |
8526 | imm_expr.X_add_number, true, mips16_small, |
8527 | mips16_ext, &ip->insn_opcode, | |
8528 | &ip->use_extend, &ip->extend); | |
cc5703cd ILT |
8529 | imm_expr.X_op = O_absent; |
8530 | imm_reloc = BFD_RELOC_UNUSED; | |
8531 | } | |
8532 | ||
8533 | return; | |
8534 | } | |
8535 | break; | |
8536 | ||
8537 | case ',': | |
8538 | if (*s++ == c) | |
8539 | continue; | |
8540 | s--; | |
8541 | switch (*++args) | |
8542 | { | |
8543 | case 'v': | |
8544 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8545 | continue; | |
8546 | case 'w': | |
8547 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8548 | continue; | |
8549 | } | |
8550 | break; | |
8551 | ||
8552 | case '(': | |
8553 | case ')': | |
8554 | if (*s++ == c) | |
8555 | continue; | |
8556 | break; | |
8557 | ||
8558 | case 'v': | |
8559 | case 'w': | |
8560 | if (s[0] != '$') | |
8561 | { | |
8562 | if (c == 'v') | |
8563 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8564 | else | |
8565 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8566 | ++args; | |
8567 | continue; | |
8568 | } | |
8569 | /* Fall through. */ | |
8570 | case 'x': | |
8571 | case 'y': | |
8572 | case 'z': | |
8573 | case 'Z': | |
8574 | case '0': | |
8575 | case 'S': | |
8576 | case 'R': | |
8577 | case 'X': | |
8578 | case 'Y': | |
8579 | if (s[0] != '$') | |
8580 | break; | |
8581 | s_reset = s; | |
8582 | if (isdigit (s[1])) | |
8583 | { | |
8584 | ++s; | |
8585 | regno = 0; | |
8586 | do | |
8587 | { | |
8588 | regno *= 10; | |
8589 | regno += *s - '0'; | |
8590 | ++s; | |
8591 | } | |
8592 | while (isdigit (*s)); | |
8593 | if (regno > 31) | |
8594 | { | |
48401fcf | 8595 | as_bad (_("invalid register number (%d)"), regno); |
cc5703cd ILT |
8596 | regno = 2; |
8597 | } | |
8598 | } | |
8599 | else | |
8600 | { | |
8601 | if (s[1] == 'f' && s[2] == 'p') | |
8602 | { | |
8603 | s += 3; | |
8604 | regno = FP; | |
8605 | } | |
8606 | else if (s[1] == 's' && s[2] == 'p') | |
8607 | { | |
8608 | s += 3; | |
8609 | regno = SP; | |
8610 | } | |
8611 | else if (s[1] == 'g' && s[2] == 'p') | |
8612 | { | |
8613 | s += 3; | |
8614 | regno = GP; | |
8615 | } | |
8616 | else if (s[1] == 'a' && s[2] == 't') | |
8617 | { | |
8618 | s += 3; | |
8619 | regno = AT; | |
8620 | } | |
8621 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8622 | { | |
8623 | s += 4; | |
8624 | regno = KT0; | |
8625 | } | |
8626 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8627 | { | |
8628 | s += 4; | |
8629 | regno = KT1; | |
8630 | } | |
8631 | else | |
8632 | break; | |
8633 | } | |
8634 | ||
8635 | if (*s == ' ') | |
8636 | ++s; | |
8637 | if (args[1] != *s) | |
8638 | { | |
8639 | if (c == 'v' || c == 'w') | |
8640 | { | |
8641 | regno = mips16_to_32_reg_map[lastregno]; | |
8642 | s = s_reset; | |
8643 | args++; | |
8644 | } | |
8645 | } | |
8646 | ||
8647 | switch (c) | |
8648 | { | |
8649 | case 'x': | |
8650 | case 'y': | |
8651 | case 'z': | |
8652 | case 'v': | |
8653 | case 'w': | |
8654 | case 'Z': | |
8655 | regno = mips32_to_16_reg_map[regno]; | |
8656 | break; | |
8657 | ||
8658 | case '0': | |
8659 | if (regno != 0) | |
8660 | regno = ILLEGAL_REG; | |
8661 | break; | |
8662 | ||
8663 | case 'S': | |
8664 | if (regno != SP) | |
8665 | regno = ILLEGAL_REG; | |
8666 | break; | |
8667 | ||
8668 | case 'R': | |
8669 | if (regno != RA) | |
8670 | regno = ILLEGAL_REG; | |
8671 | break; | |
8672 | ||
8673 | case 'X': | |
8674 | case 'Y': | |
3c83da8a | 8675 | if (regno == AT && ! mips_opts.noat) |
48401fcf | 8676 | as_warn (_("used $at without \".set noat\"")); |
cc5703cd ILT |
8677 | break; |
8678 | ||
8679 | default: | |
8680 | internalError (); | |
8681 | } | |
8682 | ||
8683 | if (regno == ILLEGAL_REG) | |
8684 | break; | |
8685 | ||
8686 | switch (c) | |
8687 | { | |
8688 | case 'x': | |
8689 | case 'v': | |
8690 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
8691 | break; | |
8692 | case 'y': | |
8693 | case 'w': | |
8694 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
8695 | break; | |
8696 | case 'z': | |
8697 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
8698 | break; | |
8699 | case 'Z': | |
8700 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
8701 | case '0': | |
8702 | case 'S': | |
8703 | case 'R': | |
8704 | break; | |
8705 | case 'X': | |
8706 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
8707 | break; | |
8708 | case 'Y': | |
8709 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
8710 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
8711 | break; | |
8712 | default: | |
8713 | internalError (); | |
8714 | } | |
8715 | ||
8716 | lastregno = regno; | |
8717 | continue; | |
8718 | ||
8719 | case 'P': | |
8720 | if (strncmp (s, "$pc", 3) == 0) | |
8721 | { | |
8722 | s += 3; | |
8723 | continue; | |
8724 | } | |
8725 | break; | |
8726 | ||
8727 | case '<': | |
8728 | case '>': | |
8729 | case '[': | |
8730 | case ']': | |
8731 | case '4': | |
8732 | case '5': | |
8733 | case 'H': | |
8734 | case 'W': | |
8735 | case 'D': | |
8736 | case 'j': | |
8737 | case '8': | |
8738 | case 'V': | |
8739 | case 'C': | |
8740 | case 'U': | |
8741 | case 'k': | |
8742 | case 'K': | |
16262668 ILT |
8743 | if (s[0] == '%' |
8744 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
8745 | { | |
8746 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
8747 | and generate the appropriate reloc. If the text | |
8748 | inside %gprel is not a symbol name with an | |
8749 | optional offset, then we generate a normal reloc | |
8750 | and will probably fail later. */ | |
8751 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
8752 | if (imm_expr.X_op == O_symbol) | |
8753 | { | |
8754 | mips16_ext = true; | |
8755 | imm_reloc = BFD_RELOC_MIPS16_GPREL; | |
8756 | s = expr_end; | |
8757 | ip->use_extend = true; | |
8758 | ip->extend = 0; | |
8759 | continue; | |
8760 | } | |
8761 | } | |
8762 | else | |
8763 | { | |
8764 | /* Just pick up a normal expression. */ | |
8765 | my_getExpression (&imm_expr, s); | |
8766 | } | |
8767 | ||
ebf28372 ILT |
8768 | if (imm_expr.X_op == O_register) |
8769 | { | |
8770 | /* What we thought was an expression turned out to | |
8771 | be a register. */ | |
8772 | ||
8773 | if (s[0] == '(' && args[1] == '(') | |
8774 | { | |
8775 | /* It looks like the expression was omitted | |
8776 | before a register indirection, which means | |
8777 | that the expression is implicitly zero. We | |
8778 | still set up imm_expr, so that we handle | |
8779 | explicit extensions correctly. */ | |
8780 | imm_expr.X_op = O_constant; | |
8781 | imm_expr.X_add_number = 0; | |
8782 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8783 | continue; | |
8784 | } | |
8785 | ||
8786 | break; | |
8787 | } | |
8788 | ||
cc5703cd ILT |
8789 | /* We need to relax this instruction. */ |
8790 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8791 | s = expr_end; | |
8792 | continue; | |
8793 | ||
8794 | case 'p': | |
8795 | case 'q': | |
8796 | case 'A': | |
8797 | case 'B': | |
8798 | case 'E': | |
8799 | /* We use offset_reloc rather than imm_reloc for the PC | |
8800 | relative operands. This lets macros with both | |
8801 | immediate and address operands work correctly. */ | |
670a50eb | 8802 | my_getExpression (&offset_expr, s); |
ebf28372 ILT |
8803 | |
8804 | if (offset_expr.X_op == O_register) | |
8805 | break; | |
8806 | ||
cc5703cd ILT |
8807 | /* We need to relax this instruction. */ |
8808 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
670a50eb ILT |
8809 | s = expr_end; |
8810 | continue; | |
8811 | ||
cc5703cd ILT |
8812 | case '6': /* break code */ |
8813 | my_getExpression (&imm_expr, s); | |
8814 | check_absolute_expr (ip, &imm_expr); | |
8815 | if ((unsigned long) imm_expr.X_add_number > 63) | |
670a50eb | 8816 | { |
48401fcf | 8817 | as_warn (_("Invalid value for `%s' (%lu)"), |
cc5703cd ILT |
8818 | ip->insn_mo->name, |
8819 | (unsigned long) imm_expr.X_add_number); | |
8820 | imm_expr.X_add_number &= 0x3f; | |
3d3c5039 | 8821 | } |
cc5703cd ILT |
8822 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; |
8823 | imm_expr.X_op = O_absent; | |
670a50eb ILT |
8824 | s = expr_end; |
8825 | continue; | |
3d3c5039 | 8826 | |
670a50eb ILT |
8827 | case 'a': /* 26 bit address */ |
8828 | my_getExpression (&offset_expr, s); | |
8829 | s = expr_end; | |
cc5703cd ILT |
8830 | offset_reloc = BFD_RELOC_MIPS16_JMP; |
8831 | ip->insn_opcode <<= 16; | |
670a50eb | 8832 | continue; |
3d3c5039 | 8833 | |
cc5703cd ILT |
8834 | case 'l': /* register list for entry macro */ |
8835 | case 'L': /* register list for exit macro */ | |
8836 | { | |
8837 | int mask; | |
8838 | ||
8839 | if (c == 'l') | |
8840 | mask = 0; | |
8841 | else | |
8842 | mask = 7 << 3; | |
8843 | while (*s != '\0') | |
8844 | { | |
c9167640 | 8845 | int freg, reg1, reg2; |
cc5703cd ILT |
8846 | |
8847 | while (*s == ' ' || *s == ',') | |
8848 | ++s; | |
8849 | if (*s != '$') | |
8850 | { | |
48401fcf | 8851 | as_bad (_("can't parse register list")); |
cc5703cd ILT |
8852 | break; |
8853 | } | |
8854 | ++s; | |
c9167640 ILT |
8855 | if (*s != 'f') |
8856 | freg = 0; | |
8857 | else | |
8858 | { | |
8859 | freg = 1; | |
8860 | ++s; | |
8861 | } | |
cc5703cd ILT |
8862 | reg1 = 0; |
8863 | while (isdigit (*s)) | |
8864 | { | |
8865 | reg1 *= 10; | |
8866 | reg1 += *s - '0'; | |
8867 | ++s; | |
8868 | } | |
8869 | if (*s == ' ') | |
8870 | ++s; | |
8871 | if (*s != '-') | |
8872 | reg2 = reg1; | |
8873 | else | |
8874 | { | |
8875 | ++s; | |
8876 | if (*s != '$') | |
8877 | break; | |
8878 | ++s; | |
c9167640 ILT |
8879 | if (freg) |
8880 | { | |
8881 | if (*s == 'f') | |
8882 | ++s; | |
8883 | else | |
8884 | { | |
48401fcf | 8885 | as_bad (_("invalid register list")); |
c9167640 ILT |
8886 | break; |
8887 | } | |
8888 | } | |
cc5703cd ILT |
8889 | reg2 = 0; |
8890 | while (isdigit (*s)) | |
8891 | { | |
8892 | reg2 *= 10; | |
8893 | reg2 += *s - '0'; | |
8894 | ++s; | |
8895 | } | |
8896 | } | |
c9167640 ILT |
8897 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') |
8898 | { | |
8899 | mask &= ~ (7 << 3); | |
8900 | mask |= 5 << 3; | |
8901 | } | |
8902 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
8903 | { | |
8904 | mask &= ~ (7 << 3); | |
8905 | mask |= 6 << 3; | |
8906 | } | |
8907 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
cc5703cd ILT |
8908 | mask |= (reg2 - 3) << 3; |
8909 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
8910 | mask |= (reg2 - 15) << 1; | |
8911 | else if (reg1 == 31 && reg2 == 31) | |
8912 | mask |= 1; | |
8913 | else | |
c9167640 | 8914 | { |
48401fcf | 8915 | as_bad (_("invalid register list")); |
c9167640 ILT |
8916 | break; |
8917 | } | |
cc5703cd | 8918 | } |
c9167640 ILT |
8919 | /* The mask is filled in in the opcode table for the |
8920 | benefit of the disassembler. We remove it before | |
8921 | applying the actual mask. */ | |
8922 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
cc5703cd ILT |
8923 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; |
8924 | } | |
8925 | continue; | |
d8a1c247 | 8926 | |
56bb6eee ILT |
8927 | case 'e': /* extend code */ |
8928 | my_getExpression (&imm_expr, s); | |
8929 | check_absolute_expr (ip, &imm_expr); | |
8930 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
8931 | { | |
48401fcf | 8932 | as_warn (_("Invalid value for `%s' (%lu)"), |
56bb6eee ILT |
8933 | ip->insn_mo->name, |
8934 | (unsigned long) imm_expr.X_add_number); | |
8935 | imm_expr.X_add_number &= 0x7ff; | |
8936 | } | |
8937 | ip->insn_opcode |= imm_expr.X_add_number; | |
8938 | imm_expr.X_op = O_absent; | |
8939 | s = expr_end; | |
8940 | continue; | |
8941 | ||
3d3c5039 | 8942 | default: |
670a50eb | 8943 | internalError (); |
3d3c5039 | 8944 | } |
670a50eb | 8945 | break; |
3d3c5039 | 8946 | } |
cc5703cd | 8947 | |
670a50eb | 8948 | /* Args don't match. */ |
cc5703cd ILT |
8949 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && |
8950 | strcmp (insn->name, insn[1].name) == 0) | |
670a50eb ILT |
8951 | { |
8952 | ++insn; | |
cc5703cd | 8953 | s = argsstart; |
670a50eb | 8954 | continue; |
3d3c5039 | 8955 | } |
cc5703cd | 8956 | |
48401fcf | 8957 | insn_error = _("illegal operands"); |
cc5703cd | 8958 | |
670a50eb | 8959 | return; |
3d3c5039 ILT |
8960 | } |
8961 | } | |
8962 | ||
cc5703cd ILT |
8963 | /* This structure holds information we know about a mips16 immediate |
8964 | argument type. */ | |
8965 | ||
8966 | struct mips16_immed_operand | |
8967 | { | |
8968 | /* The type code used in the argument string in the opcode table. */ | |
8969 | int type; | |
8970 | /* The number of bits in the short form of the opcode. */ | |
8971 | int nbits; | |
8972 | /* The number of bits in the extended form of the opcode. */ | |
8973 | int extbits; | |
8974 | /* The amount by which the short form is shifted when it is used; | |
8975 | for example, the sw instruction has a shift count of 2. */ | |
8976 | int shift; | |
8977 | /* The amount by which the short form is shifted when it is stored | |
8978 | into the instruction code. */ | |
8979 | int op_shift; | |
8980 | /* Non-zero if the short form is unsigned. */ | |
8981 | int unsp; | |
8982 | /* Non-zero if the extended form is unsigned. */ | |
8983 | int extu; | |
8984 | /* Non-zero if the value is PC relative. */ | |
8985 | int pcrel; | |
8986 | }; | |
8987 | ||
8988 | /* The mips16 immediate operand types. */ | |
8989 | ||
8990 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
8991 | { | |
8992 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8993 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8994 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8995 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8996 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
8997 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8998 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8999 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9000 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9001 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9002 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9003 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9004 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9005 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9006 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9007 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9008 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9009 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9010 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9011 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9012 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9013 | }; | |
9014 | ||
9015 | #define MIPS16_NUM_IMMED \ | |
9016 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9017 | ||
9018 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9019 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9020 | whether an extended value is needed; if one is needed, it sets | |
9021 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9022 | If SMALL is true, an unextended opcode was explicitly requested. | |
9023 | If EXT is true, an extended opcode was explicitly requested. If | |
9024 | WARN is true, warn if EXT does not match reality. */ | |
9025 | ||
9026 | static void | |
15e69f98 ILT |
9027 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, |
9028 | extend) | |
9029 | char *file; | |
9030 | unsigned int line; | |
cc5703cd ILT |
9031 | int type; |
9032 | offsetT val; | |
9033 | boolean warn; | |
9034 | boolean small; | |
9035 | boolean ext; | |
9036 | unsigned long *insn; | |
9037 | boolean *use_extend; | |
9038 | unsigned short *extend; | |
9039 | { | |
9040 | register const struct mips16_immed_operand *op; | |
9041 | int mintiny, maxtiny; | |
9042 | boolean needext; | |
9043 | ||
9044 | op = mips16_immed_operands; | |
9045 | while (op->type != type) | |
9046 | { | |
9047 | ++op; | |
9048 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9049 | } | |
9050 | ||
9051 | if (op->unsp) | |
9052 | { | |
9053 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9054 | { | |
9055 | mintiny = 1; | |
9056 | maxtiny = 1 << op->nbits; | |
9057 | } | |
9058 | else | |
9059 | { | |
9060 | mintiny = 0; | |
9061 | maxtiny = (1 << op->nbits) - 1; | |
9062 | } | |
9063 | } | |
9064 | else | |
9065 | { | |
9066 | mintiny = - (1 << (op->nbits - 1)); | |
9067 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9068 | } | |
9069 | ||
9070 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9071 | if (type == 'p' || type == 'q') | |
fbcfacb7 | 9072 | val /= 2; |
cc5703cd ILT |
9073 | |
9074 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9075 | || val < (mintiny << op->shift) | |
9076 | || val > (maxtiny << op->shift)) | |
9077 | needext = true; | |
9078 | else | |
9079 | needext = false; | |
9080 | ||
9081 | if (warn && ext && ! needext) | |
48401fcf | 9082 | as_warn_where (file, line, _("extended operand requested but not required")); |
8728fa92 | 9083 | if (small && needext) |
48401fcf | 9084 | as_bad_where (file, line, _("invalid unextended operand value")); |
cc5703cd ILT |
9085 | |
9086 | if (small || (! ext && ! needext)) | |
9087 | { | |
9088 | int insnval; | |
9089 | ||
9090 | *use_extend = false; | |
9091 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
9092 | insnval <<= op->op_shift; | |
9093 | *insn |= insnval; | |
9094 | } | |
9095 | else | |
9096 | { | |
9097 | long minext, maxext; | |
9098 | int extval; | |
9099 | ||
9100 | if (op->extu) | |
9101 | { | |
9102 | minext = 0; | |
9103 | maxext = (1 << op->extbits) - 1; | |
9104 | } | |
9105 | else | |
9106 | { | |
9107 | minext = - (1 << (op->extbits - 1)); | |
9108 | maxext = (1 << (op->extbits - 1)) - 1; | |
9109 | } | |
9110 | if (val < minext || val > maxext) | |
15e69f98 | 9111 | as_bad_where (file, line, |
48401fcf | 9112 | _("operand value out of range for instruction")); |
cc5703cd ILT |
9113 | |
9114 | *use_extend = true; | |
9115 | if (op->extbits == 16) | |
9116 | { | |
9117 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9118 | val &= 0x1f; | |
9119 | } | |
9120 | else if (op->extbits == 15) | |
9121 | { | |
9122 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9123 | val &= 0xf; | |
9124 | } | |
9125 | else | |
9126 | { | |
9127 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9128 | val = 0; | |
9129 | } | |
9130 | ||
9131 | *extend = (unsigned short) extval; | |
9132 | *insn |= val; | |
9133 | } | |
9134 | } | |
9135 | \f | |
3d3c5039 ILT |
9136 | #define LP '(' |
9137 | #define RP ')' | |
9138 | ||
9139 | static int | |
9140 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
9141 | expressionS *ep; |
9142 | char *str; | |
3d3c5039 | 9143 | { |
670a50eb ILT |
9144 | char *sp; |
9145 | int c = 0; | |
9146 | ||
9147 | if (*str == ' ') | |
9148 | str++; | |
9149 | if (*str == LP | |
9150 | || (*str == '%' && | |
9151 | ((str[1] == 'h' && str[2] == 'i') | |
9152 | || (str[1] == 'H' && str[2] == 'I') | |
9153 | || (str[1] == 'l' && str[2] == 'o')) | |
9154 | && str[3] == LP)) | |
9155 | { | |
9156 | if (*str == LP) | |
9157 | c = 0; | |
9158 | else | |
9159 | { | |
9160 | c = str[1]; | |
9161 | str += 3; | |
9162 | } | |
9163 | ||
9164 | /* | |
9165 | * A small expression may be followed by a base register. | |
9166 | * Scan to the end of this operand, and then back over a possible | |
9167 | * base register. Then scan the small expression up to that | |
9168 | * point. (Based on code in sparc.c...) | |
9169 | */ | |
9170 | for (sp = str; *sp && *sp != ','; sp++) | |
9171 | ; | |
9172 | if (sp - 4 >= str && sp[-1] == RP) | |
9173 | { | |
9174 | if (isdigit (sp[-2])) | |
9175 | { | |
9176 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
9177 | ; | |
9178 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
9179 | { | |
9180 | sp--; | |
9181 | goto do_it; | |
3d3c5039 | 9182 | } |
670a50eb ILT |
9183 | } |
9184 | else if (sp - 5 >= str | |
9185 | && sp[-5] == LP | |
9186 | && sp[-4] == '$' | |
9187 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
9188 | || (sp[-3] == 's' && sp[-2] == 'p') | |
9189 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
9190 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
9191 | { | |
9192 | sp -= 5; | |
3d3c5039 | 9193 | do_it: |
670a50eb ILT |
9194 | if (sp == str) |
9195 | { | |
9196 | /* no expression means zero offset */ | |
9197 | if (c) | |
9198 | { | |
9199 | /* %xx(reg) is an error */ | |
5ac34ac3 | 9200 | ep->X_op = O_absent; |
670a50eb | 9201 | expr_end = str - 3; |
3d3c5039 | 9202 | } |
670a50eb ILT |
9203 | else |
9204 | { | |
52aa70b5 | 9205 | ep->X_op = O_constant; |
670a50eb ILT |
9206 | expr_end = sp; |
9207 | } | |
9208 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 9209 | ep->X_op_symbol = NULL; |
670a50eb ILT |
9210 | ep->X_add_number = 0; |
9211 | } | |
9212 | else | |
9213 | { | |
9214 | *sp = '\0'; | |
9215 | my_getExpression (ep, str); | |
9216 | *sp = LP; | |
3d3c5039 | 9217 | } |
670a50eb | 9218 | return c; |
3d3c5039 ILT |
9219 | } |
9220 | } | |
9221 | } | |
670a50eb ILT |
9222 | my_getExpression (ep, str); |
9223 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
9224 | } |
9225 | ||
9226 | static void | |
9227 | my_getExpression (ep, str) | |
670a50eb ILT |
9228 | expressionS *ep; |
9229 | char *str; | |
3d3c5039 | 9230 | { |
670a50eb | 9231 | char *save_in; |
670a50eb ILT |
9232 | |
9233 | save_in = input_line_pointer; | |
9234 | input_line_pointer = str; | |
5ac34ac3 | 9235 | expression (ep); |
670a50eb ILT |
9236 | expr_end = input_line_pointer; |
9237 | input_line_pointer = save_in; | |
eb17f56c ILT |
9238 | |
9239 | /* If we are in mips16 mode, and this is an expression based on `.', | |
9240 | then we bump the value of the symbol by 1 since that is how other | |
9241 | text symbols are handled. We don't bother to handle complex | |
9242 | expressions, just `.' plus or minus a constant. */ | |
3c83da8a | 9243 | if (mips_opts.mips16 |
eb17f56c ILT |
9244 | && ep->X_op == O_symbol |
9245 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
9246 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
9247 | && ep->X_add_symbol->sy_frag == frag_now | |
9248 | && ep->X_add_symbol->sy_value.X_op == O_constant | |
9249 | && ep->X_add_symbol->sy_value.X_add_number == frag_now_fix ()) | |
9250 | ++ep->X_add_symbol->sy_value.X_add_number; | |
3d3c5039 ILT |
9251 | } |
9252 | ||
becfe05e ILT |
9253 | /* Turn a string in input_line_pointer into a floating point constant |
9254 | of type type, and store the appropriate bytes in *litP. The number | |
9255 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
9256 | returned, or NULL on OK. */ | |
9257 | ||
3d3c5039 | 9258 | char * |
670a50eb | 9259 | md_atof (type, litP, sizeP) |
becfe05e | 9260 | int type; |
3d3c5039 ILT |
9261 | char *litP; |
9262 | int *sizeP; | |
9263 | { | |
becfe05e ILT |
9264 | int prec; |
9265 | LITTLENUM_TYPE words[4]; | |
9266 | char *t; | |
9267 | int i; | |
9268 | ||
9269 | switch (type) | |
9270 | { | |
9271 | case 'f': | |
9272 | prec = 2; | |
9273 | break; | |
9274 | ||
9275 | case 'd': | |
9276 | prec = 4; | |
9277 | break; | |
9278 | ||
9279 | default: | |
9280 | *sizeP = 0; | |
48401fcf | 9281 | return _("bad call to md_atof"); |
becfe05e ILT |
9282 | } |
9283 | ||
9284 | t = atof_ieee (input_line_pointer, type, words); | |
9285 | if (t) | |
9286 | input_line_pointer = t; | |
9287 | ||
9288 | *sizeP = prec * 2; | |
9289 | ||
b9129c6f | 9290 | if (! target_big_endian) |
becfe05e ILT |
9291 | { |
9292 | for (i = prec - 1; i >= 0; i--) | |
9293 | { | |
9294 | md_number_to_chars (litP, (valueT) words[i], 2); | |
9295 | litP += 2; | |
9296 | } | |
9297 | } | |
9298 | else | |
9299 | { | |
9300 | for (i = 0; i < prec; i++) | |
9301 | { | |
9302 | md_number_to_chars (litP, (valueT) words[i], 2); | |
9303 | litP += 2; | |
9304 | } | |
9305 | } | |
9306 | ||
670a50eb | 9307 | return NULL; |
3d3c5039 ILT |
9308 | } |
9309 | ||
9310 | void | |
9311 | md_number_to_chars (buf, val, n) | |
9312 | char *buf; | |
918692a5 | 9313 | valueT val; |
3d3c5039 ILT |
9314 | int n; |
9315 | { | |
b9129c6f ILT |
9316 | if (target_big_endian) |
9317 | number_to_chars_bigendian (buf, val, n); | |
9318 | else | |
9319 | number_to_chars_littleendian (buf, val, n); | |
3d3c5039 | 9320 | } |
f3d817d8 | 9321 | \f |
e8d4d475 | 9322 | CONST char *md_shortopts = "O::g::G:"; |
1dc1e798 | 9323 | |
f3d817d8 DM |
9324 | struct option md_longopts[] = { |
9325 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
9326 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
9327 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
9328 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
9329 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
9330 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
9331 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
d8a1c247 KR |
9332 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
9333 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
9334 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
f3d817d8 | 9335 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
d8a1c247 | 9336 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) |
f3d817d8 | 9337 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
d8a1c247 | 9338 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
f3d817d8 DM |
9339 | {"trap", no_argument, NULL, OPTION_TRAP}, |
9340 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
d8a1c247 | 9341 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
f3d817d8 DM |
9342 | {"break", no_argument, NULL, OPTION_BREAK}, |
9343 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
d8a1c247 | 9344 | #define OPTION_EB (OPTION_MD_BASE + 11) |
e8d4d475 | 9345 | {"EB", no_argument, NULL, OPTION_EB}, |
d8a1c247 | 9346 | #define OPTION_EL (OPTION_MD_BASE + 12) |
e8d4d475 | 9347 | {"EL", no_argument, NULL, OPTION_EL}, |
d8a1c247 | 9348 | #define OPTION_M4650 (OPTION_MD_BASE + 13) |
b2b8c24e | 9349 | {"m4650", no_argument, NULL, OPTION_M4650}, |
d8a1c247 | 9350 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) |
b2b8c24e | 9351 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
e532b44c ILT |
9352 | #define OPTION_M4010 (OPTION_MD_BASE + 15) |
9353 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
9354 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
9355 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
c625fc23 JSC |
9356 | #define OPTION_M4100 (OPTION_MD_BASE + 17) |
9357 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
9358 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
9359 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
cc5703cd | 9360 | #define OPTION_MIPS16 (OPTION_MD_BASE + 22) |
943321c0 | 9361 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
cc5703cd | 9362 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23) |
943321c0 | 9363 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
46a92fde | 9364 | /* start-sanitize-r5900 */ |
276c2d7d GRK |
9365 | #define OPTION_M5900 (OPTION_MD_BASE + 24) |
9366 | {"m5900", no_argument, NULL, OPTION_M5900}, | |
9367 | #define OPTION_NO_M5900 (OPTION_MD_BASE + 25) | |
9368 | {"no-m5900", no_argument, NULL, OPTION_NO_M5900}, | |
46a92fde | 9369 | /* end-sanitize-r5900 */ |
5c6f5923 GRK |
9370 | #define OPTION_M3900 (OPTION_MD_BASE + 26) |
9371 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
9372 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 27) | |
9373 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
4e96260f JL |
9374 | |
9375 | /* start-sanitize-tx19 */ | |
9376 | {"m1900", no_argument, NULL, OPTION_M3900}, | |
9377 | {"no-m1900", no_argument, NULL, OPTION_NO_M3900}, | |
9378 | /* end-sanitize-tx19 */ | |
f3d817d8 | 9379 | |
6b34ac5a | 9380 | /* start-sanitize-cygnus */ |
aa2e0460 KR |
9381 | #define OPTION_M5400 (OPTION_MD_BASE + 28) |
9382 | {"m5400", no_argument, NULL, OPTION_M5400}, | |
9383 | #define OPTION_NO_M5400 (OPTION_MD_BASE + 29) | |
9384 | {"no-m5400", no_argument, NULL, OPTION_NO_M5400}, | |
9385 | ||
6b34ac5a | 9386 | /* end-sanitize-cygnus */ |
42444087 GRK |
9387 | /* start-sanitize-tx49 */ |
9388 | #define OPTION_M4900 (OPTION_MD_BASE + 30) | |
9389 | {"m4900", no_argument, NULL, OPTION_M4900}, | |
9390 | #define OPTION_NO_M4900 (OPTION_MD_BASE + 31) | |
9391 | {"no-m4900", no_argument, NULL, OPTION_NO_M4900}, | |
9392 | ||
9393 | /* end-sanitize-tx49 */ | |
2d035a50 GRK |
9394 | /* start-sanitize-vr4320 */ |
9395 | #define OPTION_M4320 (OPTION_MD_BASE + 32) | |
9396 | {"m4320", no_argument, NULL, OPTION_M4320}, | |
9397 | #define OPTION_NO_M4320 (OPTION_MD_BASE + 33) | |
9398 | {"no-m4320", no_argument, NULL, OPTION_NO_M4320}, | |
9399 | ||
9400 | /* end-sanitize-vr4320 */ | |
7e656649 RH |
9401 | /* start-sanitize-branchbug4011 */ |
9402 | #define OPTION_FIX_4011_BRANCH_BUG (OPTION_MD_BASE + 34) | |
9403 | {"fix-4011-branch-bug", no_argument, NULL, OPTION_FIX_4011_BRANCH_BUG}, | |
9404 | #define OPTION_NO_FIX_4011_BRANCH_BUG (OPTION_MD_BASE + 35) | |
9405 | {"no-fix-4011-branch-bug", no_argument, NULL, OPTION_NO_FIX_4011_BRANCH_BUG}, | |
9406 | /* end-sanitize-branchbug4011 */ | |
d8a1c247 | 9407 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) |
1dc1e798 | 9408 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) |
fb251650 | 9409 | #define OPTION_XGOT (OPTION_MD_BASE + 19) |
7f9880e5 ILT |
9410 | #define OPTION_32 (OPTION_MD_BASE + 20) |
9411 | #define OPTION_64 (OPTION_MD_BASE + 21) | |
1dc1e798 | 9412 | #ifdef OBJ_ELF |
f3d817d8 | 9413 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
fb251650 | 9414 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
f3d817d8 | 9415 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
f3d817d8 | 9416 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
7f9880e5 ILT |
9417 | {"32", no_argument, NULL, OPTION_32}, |
9418 | {"64", no_argument, NULL, OPTION_64}, | |
f3d817d8 DM |
9419 | #endif |
9420 | ||
9421 | {NULL, no_argument, NULL, 0} | |
9422 | }; | |
9423 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
9424 | |
9425 | int | |
f3d817d8 DM |
9426 | md_parse_option (c, arg) |
9427 | int c; | |
9428 | char *arg; | |
3d3c5039 | 9429 | { |
f3d817d8 | 9430 | switch (c) |
670a50eb | 9431 | { |
f3d817d8 DM |
9432 | case OPTION_TRAP: |
9433 | mips_trap = 1; | |
9434 | break; | |
670a50eb | 9435 | |
f3d817d8 DM |
9436 | case OPTION_BREAK: |
9437 | mips_trap = 0; | |
9438 | break; | |
9439 | ||
e8d4d475 | 9440 | case OPTION_EB: |
1dc1e798 | 9441 | target_big_endian = 1; |
e8d4d475 | 9442 | break; |
04cb3372 | 9443 | |
e8d4d475 | 9444 | case OPTION_EL: |
1dc1e798 | 9445 | target_big_endian = 0; |
f3d817d8 | 9446 | break; |
670a50eb | 9447 | |
f3d817d8 DM |
9448 | case 'O': |
9449 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
9450 | mips_optimize = 1; |
9451 | else | |
9452 | mips_optimize = 2; | |
f3d817d8 | 9453 | break; |
0aa07269 | 9454 | |
f3d817d8 | 9455 | case 'g': |
22ba90ce ILT |
9456 | if (arg == NULL) |
9457 | mips_debug = 2; | |
9458 | else | |
9459 | mips_debug = atoi (arg); | |
9460 | /* When the MIPS assembler sees -g or -g2, it does not do | |
9461 | optimizations which limit full symbolic debugging. We take | |
9462 | that to be equivalent to -O0. */ | |
9463 | if (mips_debug == 2) | |
05874c2e | 9464 | mips_optimize = 1; |
f3d817d8 | 9465 | break; |
4e95866e | 9466 | |
f3d817d8 | 9467 | case OPTION_MIPS1: |
3c83da8a | 9468 | mips_opts.isa = 1; |
f3d817d8 | 9469 | break; |
8358c818 | 9470 | |
f3d817d8 | 9471 | case OPTION_MIPS2: |
3c83da8a | 9472 | mips_opts.isa = 2; |
f3d817d8 | 9473 | break; |
8358c818 | 9474 | |
f3d817d8 | 9475 | case OPTION_MIPS3: |
3c83da8a | 9476 | mips_opts.isa = 3; |
f3d817d8 | 9477 | break; |
8358c818 | 9478 | |
d8a1c247 | 9479 | case OPTION_MIPS4: |
3c83da8a | 9480 | mips_opts.isa = 4; |
d8a1c247 KR |
9481 | break; |
9482 | ||
f3d817d8 DM |
9483 | case OPTION_MCPU: |
9484 | { | |
9485 | char *p; | |
9486 | ||
9487 | /* Identify the processor type */ | |
9488 | p = arg; | |
9489 | if (strcmp (p, "default") == 0 | |
9490 | || strcmp (p, "DEFAULT") == 0) | |
4bb0cc41 | 9491 | mips_cpu = -1; |
f3d817d8 DM |
9492 | else |
9493 | { | |
c625fc23 JSC |
9494 | int sv = 0; |
9495 | ||
9496 | /* We need to cope with the various "vr" prefixes for the 4300 | |
9497 | processor. */ | |
9498 | if (*p == 'v' || *p == 'V') | |
9499 | { | |
9500 | sv = 1; | |
9501 | p++; | |
9502 | } | |
9503 | ||
f3d817d8 DM |
9504 | if (*p == 'r' || *p == 'R') |
9505 | p++; | |
8358c818 | 9506 | |
4bb0cc41 | 9507 | mips_cpu = -1; |
f3d817d8 DM |
9508 | switch (*p) |
9509 | { | |
d8a1c247 KR |
9510 | case '1': |
9511 | if (strcmp (p, "10000") == 0 | |
9512 | || strcmp (p, "10k") == 0 | |
9513 | || strcmp (p, "10K") == 0) | |
9514 | mips_cpu = 10000; | |
4e96260f JL |
9515 | /* start-sanitize-tx19 */ |
9516 | else if (strcmp (p, "1900") == 0) | |
9517 | mips_cpu = 3900; | |
9518 | /* end-sanitize-tx19 */ | |
d8a1c247 KR |
9519 | break; |
9520 | ||
f3d817d8 DM |
9521 | case '2': |
9522 | if (strcmp (p, "2000") == 0 | |
9523 | || strcmp (p, "2k") == 0 | |
9524 | || strcmp (p, "2K") == 0) | |
4bb0cc41 | 9525 | mips_cpu = 2000; |
f3d817d8 | 9526 | break; |
8358c818 | 9527 | |
f3d817d8 DM |
9528 | case '3': |
9529 | if (strcmp (p, "3000") == 0 | |
9530 | || strcmp (p, "3k") == 0 | |
9531 | || strcmp (p, "3K") == 0) | |
4bb0cc41 | 9532 | mips_cpu = 3000; |
5c6f5923 GRK |
9533 | else if (strcmp (p, "3900") == 0) |
9534 | mips_cpu = 3900; | |
f3d817d8 | 9535 | break; |
8358c818 | 9536 | |
f3d817d8 DM |
9537 | case '4': |
9538 | if (strcmp (p, "4000") == 0 | |
9539 | || strcmp (p, "4k") == 0 | |
8c63448a | 9540 | || strcmp (p, "4K") == 0) |
4bb0cc41 | 9541 | mips_cpu = 4000; |
c625fc23 | 9542 | else if (strcmp (p, "4100") == 0) |
c625fc23 | 9543 | mips_cpu = 4100; |
c625fc23 JSC |
9544 | else if (strcmp (p, "4300") == 0) |
9545 | mips_cpu = 4300; | |
2d035a50 GRK |
9546 | /* start-sanitize-vr4320 */ |
9547 | else if (strcmp (p, "4320") == 0) | |
9548 | mips_cpu = 4320; | |
9549 | /* end-sanitize-vr4320 */ | |
8c63448a | 9550 | else if (strcmp (p, "4400") == 0) |
4bb0cc41 | 9551 | mips_cpu = 4400; |
8c63448a | 9552 | else if (strcmp (p, "4600") == 0) |
4bb0cc41 | 9553 | mips_cpu = 4600; |
b2b8c24e | 9554 | else if (strcmp (p, "4650") == 0) |
b2b8c24e | 9555 | mips_cpu = 4650; |
4ebda395 GRK |
9556 | /* start-sanitize-tx49 */ |
9557 | else if (strcmp (p, "4900") == 0) | |
9558 | mips_cpu = 4900; | |
9559 | /* end-sanitize-tx49 */ | |
e532b44c | 9560 | else if (strcmp (p, "4010") == 0) |
1724c79e | 9561 | mips_cpu = 4010; |
f3d817d8 | 9562 | break; |
8358c818 | 9563 | |
517078c1 ILT |
9564 | case '5': |
9565 | if (strcmp (p, "5000") == 0 | |
9566 | || strcmp (p, "5k") == 0 | |
9567 | || strcmp (p, "5K") == 0) | |
9568 | mips_cpu = 5000; | |
6b34ac5a | 9569 | /* start-sanitize-cygnus */ |
aa2e0460 KR |
9570 | else if (strcmp (p, "5400") == 0) |
9571 | mips_cpu = 5400; | |
6b34ac5a | 9572 | /* end-sanitize-cygnus */ |
276c2d7d GRK |
9573 | /* start-sanitize-r5900 */ |
9574 | else if (strcmp (p, "5900") == 0) | |
9575 | mips_cpu = 5900; | |
9576 | /* end-sanitize-r5900 */ | |
517078c1 ILT |
9577 | break; |
9578 | ||
f3d817d8 DM |
9579 | case '6': |
9580 | if (strcmp (p, "6000") == 0 | |
9581 | || strcmp (p, "6k") == 0 | |
9582 | || strcmp (p, "6K") == 0) | |
4bb0cc41 | 9583 | mips_cpu = 6000; |
f3d817d8 | 9584 | break; |
55933a58 | 9585 | |
d8a1c247 KR |
9586 | case '8': |
9587 | if (strcmp (p, "8000") == 0 | |
9588 | || strcmp (p, "8k") == 0 | |
9589 | || strcmp (p, "8K") == 0) | |
9590 | mips_cpu = 8000; | |
9591 | break; | |
9592 | ||
55933a58 ILT |
9593 | case 'o': |
9594 | if (strcmp (p, "orion") == 0) | |
4bb0cc41 | 9595 | mips_cpu = 4600; |
55933a58 | 9596 | break; |
f3d817d8 | 9597 | } |
8358c818 | 9598 | |
b3ed1af3 KR |
9599 | if (sv |
9600 | && (mips_cpu != 4300 | |
9601 | && mips_cpu != 4100 | |
2d035a50 GRK |
9602 | /* start-sanitize-vr4320 */ |
9603 | && mips_cpu != 4320 | |
9604 | /* end-sanitize-vr4320 */ | |
6b34ac5a | 9605 | /* start-sanitize-cygnus */ |
b3ed1af3 | 9606 | && mips_cpu != 5400 |
6b34ac5a | 9607 | /* end-sanitize-cygnus */ |
b3ed1af3 | 9608 | && mips_cpu != 5000)) |
c625fc23 | 9609 | { |
48401fcf | 9610 | as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg); |
c625fc23 JSC |
9611 | return 0; |
9612 | } | |
9613 | ||
4bb0cc41 | 9614 | if (mips_cpu == -1) |
f3d817d8 | 9615 | { |
48401fcf | 9616 | as_bad (_("invalid architecture -mcpu=%s"), arg); |
f3d817d8 DM |
9617 | return 0; |
9618 | } | |
9619 | } | |
9620 | } | |
9621 | break; | |
8358c818 | 9622 | |
b2b8c24e ILT |
9623 | case OPTION_M4650: |
9624 | mips_4650 = 1; | |
9625 | break; | |
9626 | ||
9627 | case OPTION_NO_M4650: | |
9628 | mips_4650 = 0; | |
9629 | break; | |
9630 | ||
e532b44c ILT |
9631 | case OPTION_M4010: |
9632 | mips_4010 = 1; | |
9633 | break; | |
9634 | ||
9635 | case OPTION_NO_M4010: | |
9636 | mips_4010 = 0; | |
9637 | break; | |
9638 | ||
c625fc23 JSC |
9639 | case OPTION_M4100: |
9640 | mips_4100 = 1; | |
9641 | break; | |
9642 | ||
9643 | case OPTION_NO_M4100: | |
9644 | mips_4100 = 0; | |
9645 | break; | |
9646 | ||
276c2d7d GRK |
9647 | /* start-sanitize-r5900 */ |
9648 | case OPTION_M5900: | |
9649 | mips_5900 = 1; | |
9650 | break; | |
9651 | ||
9652 | case OPTION_NO_M5900: | |
9653 | mips_5900 = 0; | |
9654 | break; | |
9655 | /* end-sanitize-r5900 */ | |
9656 | ||
2d035a50 GRK |
9657 | /* start-sanitize-vr4320 */ |
9658 | case OPTION_M4320: | |
9659 | mips_4320 = 1; | |
9660 | break; | |
9661 | ||
9662 | case OPTION_NO_M4320: | |
9663 | mips_4320 = 0; | |
9664 | break; | |
9665 | ||
9666 | /* end-sanitize-vr4320 */ | |
6b34ac5a | 9667 | /* start-sanitize-cygnus */ |
aa2e0460 KR |
9668 | case OPTION_M5400: |
9669 | mips_5400 = 1; | |
9670 | break; | |
9671 | ||
9672 | case OPTION_NO_M5400: | |
9673 | mips_5400 = 0; | |
9674 | break; | |
9675 | ||
6b34ac5a | 9676 | /* end-sanitize-cygnus */ |
5c6f5923 GRK |
9677 | case OPTION_M3900: |
9678 | mips_3900 = 1; | |
9679 | break; | |
9680 | ||
9681 | case OPTION_NO_M3900: | |
9682 | mips_3900 = 0; | |
9683 | break; | |
9684 | ||
42444087 GRK |
9685 | /* start-sanitize-tx49 */ |
9686 | case OPTION_M4900: | |
9687 | mips_4900 = 1; | |
9688 | break; | |
9689 | ||
9690 | case OPTION_NO_M4900: | |
9691 | mips_4900 = 0; | |
9692 | break; | |
9693 | ||
9694 | /* end-sanitize-tx49 */ | |
cc5703cd | 9695 | case OPTION_MIPS16: |
3c83da8a | 9696 | mips_opts.mips16 = 1; |
4a1cb507 | 9697 | mips_no_prev_insn (false); |
cc5703cd ILT |
9698 | break; |
9699 | ||
9700 | case OPTION_NO_MIPS16: | |
3c83da8a | 9701 | mips_opts.mips16 = 0; |
4a1cb507 | 9702 | mips_no_prev_insn (false); |
cc5703cd ILT |
9703 | break; |
9704 | ||
f3d817d8 | 9705 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 9706 | mips_pic = EMBEDDED_PIC; |
1dc1e798 | 9707 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
f3d817d8 | 9708 | { |
48401fcf | 9709 | as_bad (_("-G may not be used with embedded PIC code")); |
f3d817d8 DM |
9710 | return 0; |
9711 | } | |
5b63f465 | 9712 | g_switch_value = 0x7fffffff; |
f3d817d8 | 9713 | break; |
d9aba805 | 9714 | |
fb251650 ILT |
9715 | /* When generating ELF code, we permit -KPIC and -call_shared to |
9716 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
9717 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 9718 | case OPTION_CALL_SHARED: |
1dc1e798 KR |
9719 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
9720 | { | |
48401fcf | 9721 | as_bad (_("-call_shared is supported only for ELF format")); |
1dc1e798 KR |
9722 | return 0; |
9723 | } | |
d9aba805 ILT |
9724 | mips_pic = SVR4_PIC; |
9725 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 | 9726 | { |
48401fcf | 9727 | as_bad (_("-G may not be used with SVR4 PIC code")); |
f3d817d8 DM |
9728 | return 0; |
9729 | } | |
d9aba805 | 9730 | g_switch_value = 0; |
f3d817d8 DM |
9731 | break; |
9732 | ||
9733 | case OPTION_NON_SHARED: | |
1dc1e798 KR |
9734 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
9735 | { | |
48401fcf | 9736 | as_bad (_("-non_shared is supported only for ELF format")); |
1dc1e798 KR |
9737 | return 0; |
9738 | } | |
d9aba805 | 9739 | mips_pic = NO_PIC; |
f3d817d8 | 9740 | break; |
8358c818 | 9741 | |
fb251650 ILT |
9742 | /* The -xgot option tells the assembler to use 32 offsets when |
9743 | accessing the got in SVR4_PIC mode. It is for Irix | |
9744 | compatibility. */ | |
9745 | case OPTION_XGOT: | |
9746 | mips_big_got = 1; | |
9747 | break; | |
9748 | ||
f3d817d8 | 9749 | case 'G': |
1dc1e798 KR |
9750 | if (! USE_GLOBAL_POINTER_OPT) |
9751 | { | |
48401fcf | 9752 | as_bad (_("-G is not supported for this configuration")); |
1dc1e798 KR |
9753 | return 0; |
9754 | } | |
9755 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
670a50eb | 9756 | { |
48401fcf | 9757 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); |
f3d817d8 | 9758 | return 0; |
670a50eb ILT |
9759 | } |
9760 | else | |
f3d817d8 | 9761 | g_switch_value = atoi (arg); |
42562568 | 9762 | g_switch_seen = 1; |
f3d817d8 | 9763 | break; |
4e95866e | 9764 | |
7f9880e5 ILT |
9765 | /* The -32 and -64 options tell the assembler to output the 32 |
9766 | bit or the 64 bit MIPS ELF format. */ | |
9767 | case OPTION_32: | |
9768 | mips_64 = 0; | |
9769 | break; | |
9770 | ||
9771 | case OPTION_64: | |
9c44af60 ILT |
9772 | { |
9773 | const char **list, **l; | |
9774 | ||
9775 | list = bfd_target_list (); | |
9776 | for (l = list; *l != NULL; l++) | |
9777 | if (strcmp (*l, "elf64-bigmips") == 0 | |
9778 | || strcmp (*l, "elf64-littlemips") == 0) | |
9779 | break; | |
9780 | if (*l == NULL) | |
48401fcf | 9781 | as_fatal (_("No compiled in support for 64 bit object file format")); |
9c44af60 ILT |
9782 | free (list); |
9783 | mips_64 = 1; | |
9784 | } | |
7f9880e5 ILT |
9785 | break; |
9786 | ||
7e656649 RH |
9787 | /* start-sanitize-branchbug4011 */ |
9788 | case OPTION_FIX_4011_BRANCH_BUG: | |
9789 | mips_fix_4011_branch_bug = 1; | |
9790 | break; | |
9791 | ||
9792 | case OPTION_NO_FIX_4011_BRANCH_BUG: | |
9793 | mips_fix_4011_branch_bug = 0; | |
9794 | break; | |
9795 | ||
9796 | /* end-sanitize-branchbug4011 */ | |
f3d817d8 DM |
9797 | default: |
9798 | return 0; | |
8ea7f4e8 ILT |
9799 | } |
9800 | ||
f3d817d8 | 9801 | return 1; |
8ea7f4e8 ILT |
9802 | } |
9803 | ||
f3d817d8 DM |
9804 | void |
9805 | md_show_usage (stream) | |
9806 | FILE *stream; | |
9807 | { | |
48401fcf | 9808 | fprintf(stream, _("\ |
f3d817d8 DM |
9809 | MIPS options:\n\ |
9810 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
9811 | -EB generate big endian output\n\ |
9812 | -EL generate little endian output\n\ | |
9813 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
9814 | -G NUM allow referencing objects up to NUM bytes\n\ | |
48401fcf TT |
9815 | implicitly with the gp register [default 8]\n")); |
9816 | fprintf(stream, _("\ | |
31493cdf ILT |
9817 | -mips1 generate MIPS ISA I instructions\n\ |
9818 | -mips2 generate MIPS ISA II instructions\n\ | |
9819 | -mips3 generate MIPS ISA III instructions\n\ | |
9820 | -mips4 generate MIPS ISA IV instructions\n\ | |
c625fc23 | 9821 | -mcpu=vr4300 generate code for vr4300\n\ |
fb251650 | 9822 | -mcpu=vr4100 generate code for vr4100\n\ |
e532b44c ILT |
9823 | -m4650 permit R4650 instructions\n\ |
9824 | -no-m4650 do not permit R4650 instructions\n\ | |
9825 | -m4010 permit R4010 instructions\n\ | |
9826 | -no-m4010 do not permit R4010 instructions\n\ | |
c625fc23 | 9827 | -m4100 permit VR4100 instructions\n\ |
48401fcf TT |
9828 | -no-m4100 do not permit VR4100 instructions\n")); |
9829 | fprintf(stream, _("\ | |
cc5703cd | 9830 | -mips16 generate mips16 instructions\n\ |
48401fcf TT |
9831 | -no-mips16 do not generate mips16 instructions\n")); |
9832 | fprintf(stream, _("\ | |
f3d817d8 DM |
9833 | -O0 remove unneeded NOPs, do not swap branches\n\ |
9834 | -O remove unneeded NOPs and swap branches\n\ | |
9835 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
48401fcf | 9836 | --break, --no-trap break exception on div by 0 and mult overflow\n")); |
f3d817d8 | 9837 | #ifdef OBJ_ELF |
48401fcf | 9838 | fprintf(stream, _("\ |
f3d817d8 | 9839 | -KPIC, -call_shared generate SVR4 position independent code\n\ |
fb251650 | 9840 | -non_shared do not generate position independent code\n\ |
7f9880e5 ILT |
9841 | -xgot assume a 32 bit GOT\n\ |
9842 | -32 create 32 bit object file (default)\n\ | |
48401fcf | 9843 | -64 create 64 bit object file\n")); |
f3d817d8 DM |
9844 | #endif |
9845 | } | |
9846 | \f | |
efec4a28 DP |
9847 | void |
9848 | mips_init_after_args () | |
9849 | { | |
af942793 SS |
9850 | /* initialize opcodes */ |
9851 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
9852 | mips_opcodes = (struct mips_opcode*) mips_builtin_opcodes; | |
efec4a28 DP |
9853 | } |
9854 | ||
3d3c5039 ILT |
9855 | long |
9856 | md_pcrel_from (fixP) | |
9857 | fixS *fixP; | |
9858 | { | |
1dc1e798 KR |
9859 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
9860 | && fixP->fx_addsy != (symbolS *) NULL | |
5b63f465 ILT |
9861 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
9862 | { | |
9863 | /* This makes a branch to an undefined symbol be a branch to the | |
9864 | current location. */ | |
9865 | return 4; | |
9866 | } | |
5b63f465 | 9867 | |
670a50eb ILT |
9868 | /* return the address of the delay slot */ |
9869 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
9870 | } |
9871 | ||
abdad6bc ILT |
9872 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
9873 | reloc for a cons. We could use the definition there, except that | |
9874 | we want to handle 64 bit relocs specially. */ | |
9875 | ||
9876 | void | |
9877 | cons_fix_new_mips (frag, where, nbytes, exp) | |
9878 | fragS *frag; | |
9879 | int where; | |
9880 | unsigned int nbytes; | |
9881 | expressionS *exp; | |
9882 | { | |
bf39474f | 9883 | #ifndef OBJ_ELF |
abdad6bc | 9884 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a |
7f9880e5 ILT |
9885 | 4 byte reloc. */ |
9886 | if (nbytes == 8 && ! mips_64) | |
abdad6bc | 9887 | { |
b9129c6f | 9888 | if (target_big_endian) |
abdad6bc ILT |
9889 | where += 4; |
9890 | nbytes = 4; | |
9891 | } | |
bf39474f | 9892 | #endif |
abdad6bc | 9893 | |
7f9880e5 | 9894 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) |
48401fcf | 9895 | as_bad (_("Unsupported reloc size %d"), nbytes); |
abdad6bc ILT |
9896 | |
9897 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
7f9880e5 ILT |
9898 | (nbytes == 2 |
9899 | ? BFD_RELOC_16 | |
9900 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
abdad6bc ILT |
9901 | } |
9902 | ||
23604921 ILT |
9903 | /* This is called before the symbol table is processed. In order to |
9904 | work with gcc when using mips-tfile, we must keep all local labels. | |
9905 | However, in other cases, we want to discard them. If we were | |
9906 | called with -g, but we didn't see any debugging information, it may | |
9907 | mean that gcc is smuggling debugging information through to | |
9908 | mips-tfile, in which case we must generate all local labels. */ | |
9909 | ||
9910 | void | |
9911 | mips_frob_file_before_adjust () | |
9912 | { | |
9913 | #ifndef NO_ECOFF_DEBUGGING | |
9914 | if (ECOFF_DEBUGGING | |
9915 | && mips_debug != 0 | |
9916 | && ! ecoff_debugging_seen) | |
9917 | flag_keep_locals = 1; | |
9918 | #endif | |
9919 | } | |
9920 | ||
867a58b3 ILT |
9921 | /* Sort any unmatched HI16_S relocs so that they immediately precede |
9922 | the corresponding LO reloc. This is called before md_apply_fix and | |
9923 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
9924 | explicit use of the %hi modifier. */ | |
9925 | ||
9926 | void | |
9927 | mips_frob_file () | |
9928 | { | |
9929 | struct mips_hi_fixup *l; | |
9930 | ||
9931 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
9932 | { | |
9933 | segment_info_type *seginfo; | |
9b61d62b | 9934 | int pass; |
867a58b3 ILT |
9935 | |
9936 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
9937 | ||
9938 | /* Check quickly whether the next fixup happens to be a matching | |
9939 | %lo. */ | |
9940 | if (l->fixp->fx_next != NULL | |
9941 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
9942 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
9943 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
9944 | continue; | |
9945 | ||
9946 | /* Look through the fixups for this segment for a matching %lo. | |
9b61d62b ILT |
9947 | When we find one, move the %hi just in front of it. We do |
9948 | this in two passes. In the first pass, we try to find a | |
9949 | unique %lo. In the second pass, we permit multiple %hi | |
9950 | relocs for a single %lo (this is a GNU extension). */ | |
867a58b3 | 9951 | seginfo = seg_info (l->seg); |
9b61d62b ILT |
9952 | for (pass = 0; pass < 2; pass++) |
9953 | { | |
9954 | fixS *f, *prev; | |
9955 | ||
9956 | prev = NULL; | |
9957 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
867a58b3 | 9958 | { |
9b61d62b ILT |
9959 | /* Check whether this is a %lo fixup which matches l->fixp. */ |
9960 | if (f->fx_r_type == BFD_RELOC_LO16 | |
9961 | && f->fx_addsy == l->fixp->fx_addsy | |
9962 | && f->fx_offset == l->fixp->fx_offset | |
9963 | && (pass == 1 | |
9964 | || prev == NULL | |
9965 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
9966 | || prev->fx_addsy != f->fx_addsy | |
9967 | || prev->fx_offset != f->fx_offset)) | |
9968 | { | |
9969 | fixS **pf; | |
867a58b3 | 9970 | |
9b61d62b ILT |
9971 | /* Move l->fixp before f. */ |
9972 | for (pf = &seginfo->fix_root; | |
9973 | *pf != l->fixp; | |
9974 | pf = &(*pf)->fx_next) | |
9975 | assert (*pf != NULL); | |
867a58b3 | 9976 | |
9b61d62b | 9977 | *pf = l->fixp->fx_next; |
867a58b3 | 9978 | |
9b61d62b ILT |
9979 | l->fixp->fx_next = f; |
9980 | if (prev == NULL) | |
9981 | seginfo->fix_root = l->fixp; | |
9982 | else | |
9983 | prev->fx_next = l->fixp; | |
867a58b3 | 9984 | |
9b61d62b ILT |
9985 | break; |
9986 | } | |
9987 | ||
9988 | prev = f; | |
867a58b3 ILT |
9989 | } |
9990 | ||
9b61d62b ILT |
9991 | if (f != NULL) |
9992 | break; | |
867a58b3 | 9993 | |
9b61d62b ILT |
9994 | if (pass == 1) |
9995 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
48401fcf | 9996 | _("Unmatched %%hi reloc")); |
9b61d62b | 9997 | } |
867a58b3 ILT |
9998 | } |
9999 | } | |
10000 | ||
1c803e52 ILT |
10001 | /* When generating embedded PIC code we need to use a special |
10002 | relocation to represent the difference of two symbols in the .text | |
10003 | section (switch tables use a difference of this sort). See | |
10004 | include/coff/mips.h for details. This macro checks whether this | |
10005 | fixup requires the special reloc. */ | |
10006 | #define SWITCH_TABLE(fixp) \ | |
10007 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
10008 | && (fixp)->fx_addsy != NULL \ | |
10009 | && (fixp)->fx_subsy != NULL \ | |
10010 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
10011 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
10012 | ||
5b63f465 | 10013 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
10014 | relocations, in case the linker has to relax a call. We also need |
10015 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
10016 | |
10017 | /*ARGSUSED*/ | |
10018 | int | |
10019 | mips_force_relocation (fixp) | |
10020 | fixS *fixp; | |
10021 | { | |
7e656649 RH |
10022 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
10023 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
10024 | return 1; | |
10025 | ||
1c803e52 | 10026 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
10027 | && (fixp->fx_pcrel |
10028 | || SWITCH_TABLE (fixp) | |
10029 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
10030 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
10031 | } |
10032 | ||
10033 | /* Apply a fixup to the object file. */ | |
10034 | ||
3d3c5039 ILT |
10035 | int |
10036 | md_apply_fix (fixP, valueP) | |
10037 | fixS *fixP; | |
918692a5 | 10038 | valueT *valueP; |
3d3c5039 | 10039 | { |
670a50eb ILT |
10040 | unsigned char *buf; |
10041 | long insn, value; | |
3d3c5039 | 10042 | |
bf39474f ILT |
10043 | assert (fixP->fx_size == 4 |
10044 | || fixP->fx_r_type == BFD_RELOC_16 | |
7e656649 RH |
10045 | || fixP->fx_r_type == BFD_RELOC_64 |
10046 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
10047 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); | |
3d3c5039 | 10048 | |
670a50eb | 10049 | value = *valueP; |
1748b9d8 ILT |
10050 | |
10051 | /* If we aren't adjusting this fixup to be against the section | |
10052 | symbol, we need to adjust the value. */ | |
68952421 | 10053 | #ifdef OBJ_ELF |
1748b9d8 | 10054 | if (fixP->fx_addsy != NULL |
1748b9d8 | 10055 | && OUTPUT_FLAVOR == bfd_target_elf_flavour |
622b1860 ILT |
10056 | && (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16 |
10057 | || S_IS_WEAK (fixP->fx_addsy))) | |
1748b9d8 ILT |
10058 | { |
10059 | value -= S_GET_VALUE (fixP->fx_addsy); | |
10060 | if (value != 0 && ! fixP->fx_pcrel) | |
10061 | { | |
10062 | /* In this case, the bfd_install_relocation routine will | |
10063 | incorrectly add the symbol value back in. We just want | |
10064 | the addend to appear in the object file. */ | |
10065 | value -= S_GET_VALUE (fixP->fx_addsy); | |
10066 | } | |
10067 | } | |
10068 | #endif | |
10069 | ||
670a50eb | 10070 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ |
3d3c5039 | 10071 | |
5b63f465 ILT |
10072 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
10073 | fixP->fx_done = 1; | |
10074 | ||
670a50eb ILT |
10075 | switch (fixP->fx_r_type) |
10076 | { | |
3d3c5039 ILT |
10077 | case BFD_RELOC_MIPS_JMP: |
10078 | case BFD_RELOC_HI16: | |
10079 | case BFD_RELOC_HI16_S: | |
670a50eb | 10080 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
10081 | case BFD_RELOC_MIPS_LITERAL: |
10082 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
10083 | case BFD_RELOC_MIPS_GOT16: |
10084 | case BFD_RELOC_MIPS_GPREL32: | |
fb251650 ILT |
10085 | case BFD_RELOC_MIPS_GOT_HI16: |
10086 | case BFD_RELOC_MIPS_GOT_LO16: | |
10087 | case BFD_RELOC_MIPS_CALL_HI16: | |
10088 | case BFD_RELOC_MIPS_CALL_LO16: | |
16262668 | 10089 | case BFD_RELOC_MIPS16_GPREL: |
0bc0e337 JL |
10090 | /* start-sanitize-r5900 */ |
10091 | case BFD_RELOC_MIPS15_S3: | |
10092 | /* end-sanitize-r5900 */ | |
ecd4ca1c | 10093 | if (fixP->fx_pcrel) |
7b777690 | 10094 | as_bad_where (fixP->fx_file, fixP->fx_line, |
48401fcf | 10095 | _("Invalid PC relative reloc")); |
670a50eb | 10096 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 10097 | break; |
3d3c5039 | 10098 | |
cc5703cd ILT |
10099 | case BFD_RELOC_MIPS16_JMP: |
10100 | /* We currently always generate a reloc against a symbol, which | |
10101 | means that we don't want an addend even if the symbol is | |
10102 | defined. */ | |
10103 | fixP->fx_addnumber = 0; | |
10104 | break; | |
10105 | ||
ecd4ca1c ILT |
10106 | case BFD_RELOC_PCREL_HI16_S: |
10107 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 10108 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
10109 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
10110 | { | |
10111 | /* For an external symbol adjust by the address to make it | |
10112 | pcrel_offset. We use the address of the RELLO reloc | |
10113 | which follows this one. */ | |
10114 | value += (fixP->fx_next->fx_frag->fr_address | |
10115 | + fixP->fx_next->fx_where); | |
10116 | } | |
10117 | if (value & 0x8000) | |
10118 | value += 0x10000; | |
10119 | value >>= 16; | |
0221ddf7 | 10120 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 10121 | if (target_big_endian) |
ecd4ca1c ILT |
10122 | buf += 2; |
10123 | md_number_to_chars (buf, value, 2); | |
10124 | break; | |
10125 | ||
10126 | case BFD_RELOC_PCREL_LO16: | |
10127 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 10128 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
10129 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
10130 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 10131 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 10132 | if (target_big_endian) |
ecd4ca1c ILT |
10133 | buf += 2; |
10134 | md_number_to_chars (buf, value, 2); | |
10135 | break; | |
10136 | ||
bf39474f ILT |
10137 | case BFD_RELOC_64: |
10138 | /* This is handled like BFD_RELOC_32, but we output a sign | |
10139 | extended value if we are only 32 bits. */ | |
10140 | if (fixP->fx_done | |
10141 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
10142 | { | |
10143 | if (8 <= sizeof (valueT)) | |
10144 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
10145 | value, 8); | |
10146 | else | |
10147 | { | |
10148 | long w1, w2; | |
10149 | long hiv; | |
10150 | ||
10151 | w1 = w2 = fixP->fx_where; | |
b9129c6f | 10152 | if (target_big_endian) |
bf39474f ILT |
10153 | w1 += 4; |
10154 | else | |
10155 | w2 += 4; | |
10156 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
10157 | if ((value & 0x80000000) != 0) | |
10158 | hiv = 0xffffffff; | |
10159 | else | |
10160 | hiv = 0; | |
10161 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
10162 | } | |
10163 | } | |
10164 | break; | |
10165 | ||
f3645945 ILT |
10166 | case BFD_RELOC_32: |
10167 | /* If we are deleting this reloc entry, we must fill in the | |
10168 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
10169 | resolved when it appears but is later defined. We also need |
10170 | to fill in the value if this is an embedded PIC switch table | |
10171 | entry. */ | |
10172 | if (fixP->fx_done | |
10173 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
10174 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
10175 | value, 4); | |
10176 | break; | |
10177 | ||
49ad0c4c ILT |
10178 | case BFD_RELOC_16: |
10179 | /* If we are deleting this reloc entry, we must fill in the | |
10180 | value now. */ | |
10181 | assert (fixP->fx_size == 2); | |
10182 | if (fixP->fx_done) | |
10183 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
10184 | value, 2); | |
10185 | break; | |
10186 | ||
f3645945 ILT |
10187 | case BFD_RELOC_LO16: |
10188 | /* When handling an embedded PIC switch statement, we can wind | |
10189 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
10190 | if (fixP->fx_done) | |
10191 | { | |
10192 | if (value < -0x8000 || value > 0x7fff) | |
10193 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
48401fcf | 10194 | _("relocation overflow")); |
0221ddf7 | 10195 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 10196 | if (target_big_endian) |
f3645945 ILT |
10197 | buf += 2; |
10198 | md_number_to_chars (buf, value, 2); | |
10199 | } | |
10200 | break; | |
10201 | ||
3d3c5039 | 10202 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
10203 | /* |
10204 | * We need to save the bits in the instruction since fixup_segment() | |
10205 | * might be deleting the relocation entry (i.e., a branch within | |
10206 | * the current segment). | |
10207 | */ | |
fbcfacb7 | 10208 | if ((value & 0x3) != 0) |
3b320c48 | 10209 | as_bad_where (fixP->fx_file, fixP->fx_line, |
48401fcf | 10210 | _("Branch to odd address (%lx)"), value); |
670a50eb | 10211 | value >>= 2; |
670a50eb ILT |
10212 | |
10213 | /* update old instruction data */ | |
10214 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
b9129c6f ILT |
10215 | if (target_big_endian) |
10216 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
10217 | else | |
10218 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
9da4c5d1 ILT |
10219 | |
10220 | if (value >= -0x8000 && value < 0x8000) | |
10221 | insn |= value & 0xffff; | |
10222 | else | |
10223 | { | |
10224 | /* The branch offset is too large. If this is an | |
10225 | unconditional branch, and we are not generating PIC code, | |
10226 | we can convert it to an absolute jump instruction. */ | |
10227 | if (mips_pic == NO_PIC | |
10228 | && fixP->fx_done | |
10229 | && fixP->fx_frag->fr_address >= text_section->vma | |
10230 | && (fixP->fx_frag->fr_address | |
10231 | < text_section->vma + text_section->_raw_size) | |
10232 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
10233 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
10234 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
10235 | { | |
10236 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
10237 | insn = 0x0c000000; /* jal */ | |
10238 | else | |
10239 | insn = 0x08000000; /* j */ | |
10240 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
10241 | fixP->fx_done = 0; | |
10242 | fixP->fx_addsy = section_symbol (text_section); | |
10243 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
10244 | } | |
10245 | else | |
10246 | { | |
10247 | /* FIXME. It would be possible in principle to handle | |
10248 | conditional branches which overflow. They could be | |
10249 | transformed into a branch around a jump. This would | |
10250 | require setting up variant frags for each different | |
10251 | branch type. The native MIPS assembler attempts to | |
10252 | handle these cases, but it appears to do it | |
10253 | incorrectly. */ | |
10254 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
48401fcf | 10255 | _("Branch out of range")); |
9da4c5d1 ILT |
10256 | } |
10257 | } | |
10258 | ||
604633ae | 10259 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 10260 | break; |
3d3c5039 | 10261 | |
7e656649 RH |
10262 | case BFD_RELOC_VTABLE_INHERIT: |
10263 | fixP->fx_done = 0; | |
10264 | if (fixP->fx_addsy | |
10265 | && !S_IS_DEFINED (fixP->fx_addsy) | |
10266 | && !S_IS_WEAK (fixP->fx_addsy)) | |
10267 | S_SET_WEAK (fixP->fx_addsy); | |
10268 | break; | |
10269 | ||
10270 | case BFD_RELOC_VTABLE_ENTRY: | |
10271 | fixP->fx_done = 0; | |
10272 | break; | |
10273 | ||
3d3c5039 | 10274 | default: |
670a50eb | 10275 | internalError (); |
3d3c5039 | 10276 | } |
5b63f465 | 10277 | |
670a50eb | 10278 | return 1; |
3d3c5039 ILT |
10279 | } |
10280 | ||
10281 | #if 0 | |
10282 | void | |
670a50eb ILT |
10283 | printInsn (oc) |
10284 | unsigned long oc; | |
3d3c5039 | 10285 | { |
670a50eb ILT |
10286 | const struct mips_opcode *p; |
10287 | int treg, sreg, dreg, shamt; | |
10288 | short imm; | |
10289 | const char *args; | |
10290 | int i; | |
3d3c5039 | 10291 | |
670a50eb ILT |
10292 | for (i = 0; i < NUMOPCODES; ++i) |
10293 | { | |
10294 | p = &mips_opcodes[i]; | |
10295 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
10296 | { | |
10297 | printf ("%08lx %s\t", oc, p->name); | |
10298 | treg = (oc >> 16) & 0x1f; | |
10299 | sreg = (oc >> 21) & 0x1f; | |
10300 | dreg = (oc >> 11) & 0x1f; | |
10301 | shamt = (oc >> 6) & 0x1f; | |
10302 | imm = oc; | |
10303 | for (args = p->args;; ++args) | |
10304 | { | |
10305 | switch (*args) | |
10306 | { | |
3d3c5039 | 10307 | case '\0': |
670a50eb ILT |
10308 | printf ("\n"); |
10309 | break; | |
3d3c5039 ILT |
10310 | |
10311 | case ',': | |
10312 | case '(': | |
10313 | case ')': | |
670a50eb ILT |
10314 | printf ("%c", *args); |
10315 | continue; | |
3d3c5039 ILT |
10316 | |
10317 | case 'r': | |
670a50eb ILT |
10318 | assert (treg == sreg); |
10319 | printf ("$%d,$%d", treg, sreg); | |
10320 | continue; | |
3d3c5039 ILT |
10321 | |
10322 | case 'd': | |
918692a5 | 10323 | case 'G': |
670a50eb ILT |
10324 | printf ("$%d", dreg); |
10325 | continue; | |
3d3c5039 ILT |
10326 | |
10327 | case 't': | |
918692a5 | 10328 | case 'E': |
670a50eb ILT |
10329 | printf ("$%d", treg); |
10330 | continue; | |
3d3c5039 | 10331 | |
9226253a ILT |
10332 | case 'k': |
10333 | printf ("0x%x", treg); | |
10334 | continue; | |
10335 | ||
3d3c5039 ILT |
10336 | case 'b': |
10337 | case 's': | |
670a50eb ILT |
10338 | printf ("$%d", sreg); |
10339 | continue; | |
3d3c5039 ILT |
10340 | |
10341 | case 'a': | |
670a50eb ILT |
10342 | printf ("0x%08lx", oc & 0x1ffffff); |
10343 | continue; | |
3d3c5039 ILT |
10344 | |
10345 | case 'i': | |
10346 | case 'j': | |
10347 | case 'o': | |
10348 | case 'u': | |
670a50eb ILT |
10349 | printf ("%d", imm); |
10350 | continue; | |
3d3c5039 ILT |
10351 | |
10352 | case '<': | |
56c96faa | 10353 | case '>': |
670a50eb ILT |
10354 | printf ("$%d", shamt); |
10355 | continue; | |
3d3c5039 ILT |
10356 | |
10357 | default: | |
670a50eb | 10358 | internalError (); |
3d3c5039 | 10359 | } |
670a50eb | 10360 | break; |
3d3c5039 | 10361 | } |
670a50eb | 10362 | return; |
3d3c5039 ILT |
10363 | } |
10364 | } | |
48401fcf | 10365 | printf (_("%08lx UNDEFINED\n"), oc); |
3d3c5039 ILT |
10366 | } |
10367 | #endif | |
10368 | ||
10369 | static symbolS * | |
10370 | get_symbol () | |
10371 | { | |
670a50eb ILT |
10372 | int c; |
10373 | char *name; | |
10374 | symbolS *p; | |
10375 | ||
10376 | name = input_line_pointer; | |
10377 | c = get_symbol_end (); | |
10378 | p = (symbolS *) symbol_find_or_make (name); | |
10379 | *input_line_pointer = c; | |
10380 | return p; | |
3d3c5039 ILT |
10381 | } |
10382 | ||
becfe05e ILT |
10383 | /* Align the current frag to a given power of two. The MIPS assembler |
10384 | also automatically adjusts any preceding label. */ | |
10385 | ||
10386 | static void | |
23dc1ae3 | 10387 | mips_align (to, fill, label) |
becfe05e ILT |
10388 | int to; |
10389 | int fill; | |
23dc1ae3 | 10390 | symbolS *label; |
becfe05e | 10391 | { |
fbcfacb7 | 10392 | mips_emit_delays (false); |
e2e5acfa | 10393 | frag_align (to, fill, 0); |
becfe05e | 10394 | record_alignment (now_seg, to); |
23dc1ae3 | 10395 | if (label != NULL) |
becfe05e | 10396 | { |
23dc1ae3 ILT |
10397 | assert (S_GET_SEGMENT (label) == now_seg); |
10398 | label->sy_frag = frag_now; | |
10399 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
10400 | } |
10401 | } | |
10402 | ||
10403 | /* Align to a given power of two. .align 0 turns off the automatic | |
10404 | alignment used by the data creating pseudo-ops. */ | |
10405 | ||
3d3c5039 ILT |
10406 | static void |
10407 | s_align (x) | |
10408 | int x; | |
10409 | { | |
670a50eb ILT |
10410 | register int temp; |
10411 | register long temp_fill; | |
10412 | long max_alignment = 15; | |
3d3c5039 | 10413 | |
670a50eb | 10414 | /* |
3d3c5039 ILT |
10415 | |
10416 | o Note that the assembler pulls down any immediately preceeding label | |
10417 | to the aligned address. | |
10418 | o It's not documented but auto alignment is reinstated by | |
10419 | a .align pseudo instruction. | |
10420 | o Note also that after auto alignment is turned off the mips assembler | |
10421 | issues an error on attempt to assemble an improperly aligned data item. | |
10422 | We don't. | |
10423 | ||
10424 | */ | |
10425 | ||
670a50eb ILT |
10426 | temp = get_absolute_expression (); |
10427 | if (temp > max_alignment) | |
48401fcf | 10428 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); |
670a50eb ILT |
10429 | else if (temp < 0) |
10430 | { | |
48401fcf | 10431 | as_warn (_("Alignment negative: 0 assumed.")); |
670a50eb ILT |
10432 | temp = 0; |
10433 | } | |
10434 | if (*input_line_pointer == ',') | |
10435 | { | |
10436 | input_line_pointer++; | |
10437 | temp_fill = get_absolute_expression (); | |
10438 | } | |
10439 | else | |
10440 | temp_fill = 0; | |
10441 | if (temp) | |
10442 | { | |
10443 | auto_align = 1; | |
fbcfacb7 ILT |
10444 | mips_align (temp, (int) temp_fill, |
10445 | insn_labels != NULL ? insn_labels->label : NULL); | |
3d3c5039 | 10446 | } |
670a50eb ILT |
10447 | else |
10448 | { | |
10449 | auto_align = 0; | |
3d3c5039 ILT |
10450 | } |
10451 | ||
670a50eb | 10452 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
10453 | } |
10454 | ||
739708fa KR |
10455 | void |
10456 | mips_flush_pending_output () | |
becfe05e | 10457 | { |
fbcfacb7 ILT |
10458 | mips_emit_delays (false); |
10459 | mips_clear_insn_labels (); | |
becfe05e ILT |
10460 | } |
10461 | ||
3d3c5039 ILT |
10462 | static void |
10463 | s_change_sec (sec) | |
10464 | int sec; | |
10465 | { | |
88225433 | 10466 | segT seg; |
becfe05e | 10467 | |
5b63f465 ILT |
10468 | /* When generating embedded PIC code, we only use the .text, .lit8, |
10469 | .sdata and .sbss sections. We change the .data and .rdata | |
10470 | pseudo-ops to use .sdata. */ | |
10471 | if (mips_pic == EMBEDDED_PIC | |
10472 | && (sec == 'd' || sec == 'r')) | |
10473 | sec = 's'; | |
10474 | ||
acdc7ce3 ILT |
10475 | #ifdef OBJ_ELF |
10476 | /* The ELF backend needs to know that we are changing sections, so | |
10477 | that .previous works correctly. We could do something like check | |
10478 | for a obj_section_change_hook macro, but that might be confusing | |
10479 | as it would not be appropriate to use it in the section changing | |
10480 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
10481 | This should be cleaner, somehow. */ | |
10482 | obj_elf_section_change_hook (); | |
10483 | #endif | |
10484 | ||
fbcfacb7 | 10485 | mips_emit_delays (false); |
670a50eb ILT |
10486 | switch (sec) |
10487 | { | |
3d3c5039 | 10488 | case 't': |
604633ae | 10489 | s_text (0); |
670a50eb | 10490 | break; |
3d3c5039 | 10491 | case 'd': |
604633ae | 10492 | s_data (0); |
670a50eb | 10493 | break; |
3d3c5039 | 10494 | case 'b': |
670a50eb | 10495 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
10496 | demand_empty_rest_of_line (); |
10497 | break; | |
88225433 ILT |
10498 | |
10499 | case 'r': | |
1dc1e798 KR |
10500 | if (USE_GLOBAL_POINTER_OPT) |
10501 | { | |
10502 | seg = subseg_new (RDATA_SECTION_NAME, | |
10503 | (subsegT) get_absolute_expression ()); | |
10504 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
10505 | { | |
10506 | bfd_set_section_flags (stdoutput, seg, | |
10507 | (SEC_ALLOC | |
10508 | | SEC_LOAD | |
10509 | | SEC_READONLY | |
10510 | | SEC_RELOC | |
10511 | | SEC_DATA)); | |
08e17202 ILT |
10512 | if (strcmp (TARGET_OS, "elf") != 0) |
10513 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
10514 | } |
10515 | demand_empty_rest_of_line (); | |
10516 | } | |
10517 | else | |
10518 | { | |
48401fcf | 10519 | as_bad (_("No read only data section in this object file format")); |
1dc1e798 KR |
10520 | demand_empty_rest_of_line (); |
10521 | return; | |
10522 | } | |
88225433 | 10523 | break; |
88225433 ILT |
10524 | |
10525 | case 's': | |
1dc1e798 KR |
10526 | if (USE_GLOBAL_POINTER_OPT) |
10527 | { | |
10528 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
10529 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
10530 | { | |
10531 | bfd_set_section_flags (stdoutput, seg, | |
10532 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
10533 | | SEC_DATA); | |
08e17202 ILT |
10534 | if (strcmp (TARGET_OS, "elf") != 0) |
10535 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
10536 | } |
10537 | demand_empty_rest_of_line (); | |
10538 | break; | |
10539 | } | |
10540 | else | |
10541 | { | |
48401fcf | 10542 | as_bad (_("Global pointers not supported; recompile -G 0")); |
1dc1e798 KR |
10543 | demand_empty_rest_of_line (); |
10544 | return; | |
10545 | } | |
3d3c5039 | 10546 | } |
88225433 | 10547 | |
670a50eb | 10548 | auto_align = 1; |
3d3c5039 ILT |
10549 | } |
10550 | ||
739708fa KR |
10551 | void |
10552 | mips_enable_auto_align () | |
9da4c5d1 | 10553 | { |
9da4c5d1 ILT |
10554 | auto_align = 1; |
10555 | } | |
10556 | ||
3d3c5039 ILT |
10557 | static void |
10558 | s_cons (log_size) | |
10559 | int log_size; | |
10560 | { | |
23dc1ae3 ILT |
10561 | symbolS *label; |
10562 | ||
fbcfacb7 ILT |
10563 | label = insn_labels != NULL ? insn_labels->label : NULL; |
10564 | mips_emit_delays (false); | |
670a50eb | 10565 | if (log_size > 0 && auto_align) |
23dc1ae3 | 10566 | mips_align (log_size, 0, label); |
fbcfacb7 | 10567 | mips_clear_insn_labels (); |
670a50eb | 10568 | cons (1 << log_size); |
3d3c5039 ILT |
10569 | } |
10570 | ||
3d3c5039 | 10571 | static void |
becfe05e ILT |
10572 | s_float_cons (type) |
10573 | int type; | |
3d3c5039 | 10574 | { |
23dc1ae3 ILT |
10575 | symbolS *label; |
10576 | ||
fbcfacb7 | 10577 | label = insn_labels != NULL ? insn_labels->label : NULL; |
23dc1ae3 | 10578 | |
fbcfacb7 | 10579 | mips_emit_delays (false); |
670a50eb ILT |
10580 | |
10581 | if (auto_align) | |
becfe05e | 10582 | if (type == 'd') |
23dc1ae3 | 10583 | mips_align (3, 0, label); |
670a50eb | 10584 | else |
23dc1ae3 | 10585 | mips_align (2, 0, label); |
670a50eb | 10586 | |
fbcfacb7 | 10587 | mips_clear_insn_labels (); |
1849d646 | 10588 | |
becfe05e | 10589 | float_cons (type); |
3d3c5039 ILT |
10590 | } |
10591 | ||
c1444ec4 ILT |
10592 | /* Handle .globl. We need to override it because on Irix 5 you are |
10593 | permitted to say | |
10594 | .globl foo .text | |
10595 | where foo is an undefined symbol, to mean that foo should be | |
10596 | considered to be the address of a function. */ | |
10597 | ||
10598 | static void | |
10599 | s_mips_globl (x) | |
10600 | int x; | |
10601 | { | |
10602 | char *name; | |
10603 | int c; | |
10604 | symbolS *symbolP; | |
fb251650 | 10605 | flagword flag; |
c1444ec4 ILT |
10606 | |
10607 | name = input_line_pointer; | |
10608 | c = get_symbol_end (); | |
10609 | symbolP = symbol_find_or_make (name); | |
10610 | *input_line_pointer = c; | |
10611 | SKIP_WHITESPACE (); | |
fb251650 ILT |
10612 | |
10613 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
10614 | being a function is apparently labelled as being an object. */ | |
10615 | flag = BSF_OBJECT; | |
10616 | ||
c1444ec4 ILT |
10617 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
10618 | { | |
10619 | char *secname; | |
10620 | asection *sec; | |
10621 | ||
10622 | secname = input_line_pointer; | |
10623 | c = get_symbol_end (); | |
10624 | sec = bfd_get_section_by_name (stdoutput, secname); | |
10625 | if (sec == NULL) | |
48401fcf | 10626 | as_bad (_("%s: no such section"), secname); |
c1444ec4 ILT |
10627 | *input_line_pointer = c; |
10628 | ||
10629 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
fb251650 | 10630 | flag = BSF_FUNCTION; |
c1444ec4 ILT |
10631 | } |
10632 | ||
fb251650 ILT |
10633 | symbolP->bsym->flags |= flag; |
10634 | ||
c1444ec4 ILT |
10635 | S_SET_EXTERNAL (symbolP); |
10636 | demand_empty_rest_of_line (); | |
10637 | } | |
10638 | ||
3d3c5039 ILT |
10639 | static void |
10640 | s_option (x) | |
10641 | int x; | |
10642 | { | |
dd3f1f76 ILT |
10643 | char *opt; |
10644 | char c; | |
10645 | ||
10646 | opt = input_line_pointer; | |
10647 | c = get_symbol_end (); | |
10648 | ||
dd3f1f76 | 10649 | if (*opt == 'O') |
9226253a ILT |
10650 | { |
10651 | /* FIXME: What does this mean? */ | |
10652 | } | |
dd3f1f76 | 10653 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 10654 | { |
d9aba805 | 10655 | int i; |
42562568 | 10656 | |
d9aba805 ILT |
10657 | i = atoi (opt + 3); |
10658 | if (i == 0) | |
10659 | mips_pic = NO_PIC; | |
10660 | else if (i == 2) | |
10661 | mips_pic = SVR4_PIC; | |
10662 | else | |
48401fcf | 10663 | as_bad (_(".option pic%d not supported"), i); |
d9aba805 | 10664 | |
1dc1e798 | 10665 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
42562568 ILT |
10666 | { |
10667 | if (g_switch_seen && g_switch_value != 0) | |
48401fcf | 10668 | as_warn (_("-G may not be used with SVR4 PIC code")); |
42562568 ILT |
10669 | g_switch_value = 0; |
10670 | bfd_set_gp_size (stdoutput, 0); | |
10671 | } | |
9226253a | 10672 | } |
dd3f1f76 | 10673 | else |
48401fcf | 10674 | as_warn (_("Unrecognized option \"%s\""), opt); |
dd3f1f76 ILT |
10675 | |
10676 | *input_line_pointer = c; | |
670a50eb | 10677 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
10678 | } |
10679 | ||
3c83da8a JW |
10680 | /* This structure is used to hold a stack of .set values. */ |
10681 | ||
10682 | struct mips_option_stack | |
10683 | { | |
10684 | struct mips_option_stack *next; | |
10685 | struct mips_set_options options; | |
10686 | }; | |
10687 | ||
10688 | static struct mips_option_stack *mips_opts_stack; | |
10689 | ||
10690 | /* Handle the .set pseudo-op. */ | |
10691 | ||
3d3c5039 ILT |
10692 | static void |
10693 | s_mipsset (x) | |
10694 | int x; | |
10695 | { | |
670a50eb ILT |
10696 | char *name = input_line_pointer, ch; |
10697 | ||
10698 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10699 | input_line_pointer++; | |
10700 | ch = *input_line_pointer; | |
10701 | *input_line_pointer = '\0'; | |
10702 | ||
10703 | if (strcmp (name, "reorder") == 0) | |
10704 | { | |
3c83da8a | 10705 | if (mips_opts.noreorder && prev_nop_frag != NULL) |
4e95866e | 10706 | { |
4a1cb507 ILT |
10707 | /* If we still have pending nops, we can discard them. The |
10708 | usual nop handling will insert any that are still | |
10709 | needed. */ | |
3c83da8a JW |
10710 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
10711 | * (mips_opts.mips16 ? 2 : 4)); | |
4a1cb507 | 10712 | prev_nop_frag = NULL; |
4e95866e | 10713 | } |
3c83da8a | 10714 | mips_opts.noreorder = 0; |
670a50eb ILT |
10715 | } |
10716 | else if (strcmp (name, "noreorder") == 0) | |
10717 | { | |
fbcfacb7 | 10718 | mips_emit_delays (true); |
3c83da8a | 10719 | mips_opts.noreorder = 1; |
0dd2d296 | 10720 | mips_any_noreorder = 1; |
670a50eb ILT |
10721 | } |
10722 | else if (strcmp (name, "at") == 0) | |
10723 | { | |
3c83da8a | 10724 | mips_opts.noat = 0; |
670a50eb ILT |
10725 | } |
10726 | else if (strcmp (name, "noat") == 0) | |
10727 | { | |
3c83da8a | 10728 | mips_opts.noat = 1; |
3d3c5039 | 10729 | } |
670a50eb ILT |
10730 | else if (strcmp (name, "macro") == 0) |
10731 | { | |
3c83da8a | 10732 | mips_opts.warn_about_macros = 0; |
670a50eb ILT |
10733 | } |
10734 | else if (strcmp (name, "nomacro") == 0) | |
10735 | { | |
3c83da8a | 10736 | if (mips_opts.noreorder == 0) |
48401fcf | 10737 | as_bad (_("`noreorder' must be set before `nomacro'")); |
3c83da8a | 10738 | mips_opts.warn_about_macros = 1; |
670a50eb ILT |
10739 | } |
10740 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
10741 | { | |
3c83da8a | 10742 | mips_opts.nomove = 0; |
670a50eb ILT |
10743 | } |
10744 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
10745 | { | |
3c83da8a | 10746 | mips_opts.nomove = 1; |
670a50eb ILT |
10747 | } |
10748 | else if (strcmp (name, "bopt") == 0) | |
10749 | { | |
3c83da8a | 10750 | mips_opts.nobopt = 0; |
670a50eb ILT |
10751 | } |
10752 | else if (strcmp (name, "nobopt") == 0) | |
10753 | { | |
3c83da8a | 10754 | mips_opts.nobopt = 1; |
670a50eb | 10755 | } |
943321c0 ILT |
10756 | else if (strcmp (name, "mips16") == 0 |
10757 | || strcmp (name, "MIPS-16") == 0) | |
3c83da8a | 10758 | mips_opts.mips16 = 1; |
943321c0 ILT |
10759 | else if (strcmp (name, "nomips16") == 0 |
10760 | || strcmp (name, "noMIPS-16") == 0) | |
3c83da8a | 10761 | mips_opts.mips16 = 0; |
1051c97f ILT |
10762 | else if (strncmp (name, "mips", 4) == 0) |
10763 | { | |
10764 | int isa; | |
10765 | ||
10766 | /* Permit the user to change the ISA on the fly. Needless to | |
10767 | say, misuse can cause serious problems. */ | |
10768 | isa = atoi (name + 4); | |
10769 | if (isa == 0) | |
3c83da8a | 10770 | mips_opts.isa = file_mips_isa; |
d8a1c247 | 10771 | else if (isa < 1 || isa > 4) |
48401fcf | 10772 | as_bad (_("unknown ISA level")); |
1051c97f | 10773 | else |
3c83da8a | 10774 | mips_opts.isa = isa; |
1051c97f | 10775 | } |
cc5703cd | 10776 | else if (strcmp (name, "autoextend") == 0) |
3c83da8a | 10777 | mips_opts.noautoextend = 0; |
cc5703cd | 10778 | else if (strcmp (name, "noautoextend") == 0) |
3c83da8a JW |
10779 | mips_opts.noautoextend = 1; |
10780 | else if (strcmp (name, "push") == 0) | |
10781 | { | |
10782 | struct mips_option_stack *s; | |
10783 | ||
10784 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
10785 | s->next = mips_opts_stack; | |
10786 | s->options = mips_opts; | |
10787 | mips_opts_stack = s; | |
10788 | } | |
10789 | else if (strcmp (name, "pop") == 0) | |
10790 | { | |
10791 | struct mips_option_stack *s; | |
10792 | ||
10793 | s = mips_opts_stack; | |
10794 | if (s == NULL) | |
48401fcf | 10795 | as_bad (_(".set pop with no .set push")); |
3c83da8a JW |
10796 | else |
10797 | { | |
10798 | /* If we're changing the reorder mode we need to handle | |
10799 | delay slots correctly. */ | |
10800 | if (s->options.noreorder && ! mips_opts.noreorder) | |
10801 | mips_emit_delays (true); | |
10802 | else if (! s->options.noreorder && mips_opts.noreorder) | |
10803 | { | |
10804 | if (prev_nop_frag != NULL) | |
10805 | { | |
10806 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
10807 | * (mips_opts.mips16 ? 2 : 4)); | |
10808 | prev_nop_frag = NULL; | |
10809 | } | |
10810 | } | |
10811 | ||
10812 | mips_opts = s->options; | |
10813 | mips_opts_stack = s->next; | |
10814 | free (s); | |
10815 | } | |
10816 | } | |
670a50eb ILT |
10817 | else |
10818 | { | |
48401fcf | 10819 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); |
670a50eb ILT |
10820 | } |
10821 | *input_line_pointer = ch; | |
10822 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
10823 | } |
10824 | ||
9226253a ILT |
10825 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
10826 | .option pic2. It means to generate SVR4 PIC calls. */ | |
10827 | ||
10828 | static void | |
10829 | s_abicalls (ignore) | |
10830 | int ignore; | |
10831 | { | |
d9aba805 | 10832 | mips_pic = SVR4_PIC; |
1dc1e798 KR |
10833 | if (USE_GLOBAL_POINTER_OPT) |
10834 | { | |
10835 | if (g_switch_seen && g_switch_value != 0) | |
48401fcf | 10836 | as_warn (_("-G may not be used with SVR4 PIC code")); |
1dc1e798 KR |
10837 | g_switch_value = 0; |
10838 | } | |
d9aba805 | 10839 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
10840 | demand_empty_rest_of_line (); |
10841 | } | |
10842 | ||
10843 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
10844 | PIC code. It sets the $gp register for the function based on the | |
10845 | function address, which is in the register named in the argument. | |
10846 | This uses a relocation against _gp_disp, which is handled specially | |
10847 | by the linker. The result is: | |
10848 | lui $gp,%hi(_gp_disp) | |
10849 | addiu $gp,$gp,%lo(_gp_disp) | |
10850 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 10851 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
10852 | |
10853 | static void | |
10854 | s_cpload (ignore) | |
10855 | int ignore; | |
10856 | { | |
10857 | expressionS ex; | |
10858 | int icnt = 0; | |
10859 | ||
d9aba805 ILT |
10860 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
10861 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
10862 | { |
10863 | s_ignore (0); | |
10864 | return; | |
10865 | } | |
10866 | ||
10867 | /* .cpload should be a in .set noreorder section. */ | |
3c83da8a | 10868 | if (mips_opts.noreorder == 0) |
48401fcf | 10869 | as_warn (_(".cpload not in noreorder section")); |
0dd2d296 | 10870 | |
9226253a ILT |
10871 | ex.X_op = O_symbol; |
10872 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
10873 | ex.X_op_symbol = NULL; | |
10874 | ex.X_add_number = 0; | |
10875 | ||
fb251650 ILT |
10876 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
10877 | ex.X_add_symbol->bsym->flags |= BSF_OBJECT; | |
10878 | ||
0dd2d296 ILT |
10879 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
10880 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
10881 | (int) BFD_RELOC_LO16); |
10882 | ||
0dd2d296 ILT |
10883 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
10884 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
10885 | |
10886 | demand_empty_rest_of_line (); | |
10887 | } | |
10888 | ||
10889 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
10890 | offset from $sp. The offset is remembered, and after making a PIC | |
10891 | call $gp is restored from that location. */ | |
10892 | ||
10893 | static void | |
10894 | s_cprestore (ignore) | |
10895 | int ignore; | |
10896 | { | |
10897 | expressionS ex; | |
10898 | int icnt = 0; | |
10899 | ||
d9aba805 ILT |
10900 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
10901 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
10902 | { |
10903 | s_ignore (0); | |
10904 | return; | |
10905 | } | |
10906 | ||
9226253a ILT |
10907 | mips_cprestore_offset = get_absolute_expression (); |
10908 | ||
10909 | ex.X_op = O_constant; | |
10910 | ex.X_add_symbol = NULL; | |
10911 | ex.X_op_symbol = NULL; | |
10912 | ex.X_add_number = mips_cprestore_offset; | |
10913 | ||
0dd2d296 | 10914 | macro_build ((char *) NULL, &icnt, &ex, |
9a1f3160 JL |
10915 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
10916 | || mips_opts.isa < 3) | |
10917 | ? "sw" : "sd"), | |
9226253a ILT |
10918 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); |
10919 | ||
10920 | demand_empty_rest_of_line (); | |
10921 | } | |
10922 | ||
0dd2d296 ILT |
10923 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
10924 | code. It generates a 32 bit GP relative reloc. */ | |
10925 | ||
10926 | static void | |
10927 | s_gpword (ignore) | |
10928 | int ignore; | |
10929 | { | |
23dc1ae3 | 10930 | symbolS *label; |
0dd2d296 ILT |
10931 | expressionS ex; |
10932 | char *p; | |
10933 | ||
10934 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 10935 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
10936 | { |
10937 | s_cons (2); | |
10938 | return; | |
10939 | } | |
10940 | ||
fbcfacb7 ILT |
10941 | label = insn_labels != NULL ? insn_labels->label : NULL; |
10942 | mips_emit_delays (true); | |
0dd2d296 | 10943 | if (auto_align) |
23dc1ae3 | 10944 | mips_align (2, 0, label); |
fbcfacb7 | 10945 | mips_clear_insn_labels (); |
0dd2d296 ILT |
10946 | |
10947 | expression (&ex); | |
10948 | ||
10949 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
10950 | { | |
48401fcf | 10951 | as_bad (_("Unsupported use of .gpword")); |
0dd2d296 ILT |
10952 | ignore_rest_of_line (); |
10953 | } | |
10954 | ||
10955 | p = frag_more (4); | |
10956 | md_number_to_chars (p, (valueT) 0, 4); | |
10957 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
10958 | BFD_RELOC_MIPS_GPREL32); | |
10959 | ||
10960 | demand_empty_rest_of_line (); | |
10961 | } | |
10962 | ||
10963 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
10964 | tables in SVR4 PIC code. */ | |
10965 | ||
10966 | static void | |
10967 | s_cpadd (ignore) | |
10968 | int ignore; | |
10969 | { | |
10970 | int icnt = 0; | |
10971 | int reg; | |
10972 | ||
10973 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 10974 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
10975 | { |
10976 | s_ignore (0); | |
10977 | return; | |
10978 | } | |
10979 | ||
10980 | /* Add $gp to the register named as an argument. */ | |
10981 | reg = tc_get_register (0); | |
10982 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
10983 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
10984 | || mips_opts.isa < 3) | |
10985 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
10986 | "d,v,t", reg, reg, GP); |
10987 | ||
10988 | demand_empty_rest_of_line (); | |
10989 | } | |
10990 | ||
ed3eb786 ILT |
10991 | /* Handle the .insn pseudo-op. This marks instruction labels in |
10992 | mips16 mode. This permits the linker to handle them specially, | |
10993 | such as generating jalx instructions when needed. We also make | |
10994 | them odd for the duration of the assembly, in order to generate the | |
10995 | right sort of code. We will make them even in the adjust_symtab | |
10996 | routine, while leaving them marked. This is convenient for the | |
10997 | debugger and the disassembler. The linker knows to make them odd | |
10998 | again. */ | |
10999 | ||
11000 | static void | |
11001 | s_insn (ignore) | |
11002 | int ignore; | |
11003 | { | |
3c83da8a JW |
11004 | if (mips_opts.mips16) |
11005 | mips16_mark_labels (); | |
ed3eb786 | 11006 | |
3c83da8a JW |
11007 | demand_empty_rest_of_line (); |
11008 | } | |
ed3eb786 | 11009 | |
3c83da8a JW |
11010 | /* Handle a .stabn directive. We need these in order to mark a label |
11011 | as being a mips16 text label correctly. Sometimes the compiler | |
11012 | will emit a label, followed by a .stabn, and then switch sections. | |
11013 | If the label and .stabn are in mips16 mode, then the label is | |
11014 | really a mips16 text label. */ | |
ed3eb786 | 11015 | |
3c83da8a JW |
11016 | static void |
11017 | s_mips_stab (type) | |
11018 | int type; | |
11019 | { | |
11020 | if (type == 'n' && mips_opts.mips16) | |
11021 | mips16_mark_labels (); | |
11022 | ||
11023 | s_stab (type); | |
ed3eb786 ILT |
11024 | } |
11025 | ||
3c69baf9 GRK |
11026 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. |
11027 | */ | |
11028 | ||
11029 | static void | |
11030 | s_mips_weakext (ignore) | |
11031 | int ignore; | |
11032 | { | |
11033 | char *name; | |
11034 | int c; | |
11035 | symbolS *symbolP; | |
11036 | expressionS exp; | |
11037 | ||
11038 | name = input_line_pointer; | |
11039 | c = get_symbol_end (); | |
11040 | symbolP = symbol_find_or_make (name); | |
11041 | S_SET_WEAK (symbolP); | |
11042 | *input_line_pointer = c; | |
11043 | ||
11044 | SKIP_WHITESPACE (); | |
11045 | ||
11046 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11047 | { | |
11048 | if (S_IS_DEFINED (symbolP)) | |
11049 | { | |
11050 | as_bad ("Ignoring attempt to redefine symbol `%s'.", | |
11051 | S_GET_NAME (symbolP)); | |
11052 | ignore_rest_of_line (); | |
11053 | return; | |
11054 | } | |
11055 | ||
11056 | if (*input_line_pointer == ',') | |
11057 | { | |
11058 | ++input_line_pointer; | |
11059 | SKIP_WHITESPACE (); | |
11060 | } | |
11061 | ||
11062 | expression (&exp); | |
11063 | if (exp.X_op != O_symbol) | |
11064 | { | |
11065 | as_bad ("bad .weakext directive"); | |
11066 | ignore_rest_of_line(); | |
11067 | return; | |
11068 | } | |
11069 | symbolP->sy_value = exp; | |
11070 | } | |
11071 | ||
11072 | demand_empty_rest_of_line (); | |
11073 | } | |
11074 | ||
9226253a | 11075 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
11076 | to parse .frame. The argument is non-zero if this is the frame |
11077 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 11078 | |
3d3c5039 | 11079 | int |
0dd2d296 ILT |
11080 | tc_get_register (frame) |
11081 | int frame; | |
3d3c5039 ILT |
11082 | { |
11083 | int reg; | |
11084 | ||
11085 | SKIP_WHITESPACE (); | |
11086 | if (*input_line_pointer++ != '$') | |
11087 | { | |
48401fcf | 11088 | as_warn (_("expected `$'")); |
0dd2d296 | 11089 | reg = 0; |
3d3c5039 | 11090 | } |
0dd2d296 | 11091 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
11092 | { |
11093 | reg = get_absolute_expression (); | |
11094 | if (reg < 0 || reg >= 32) | |
11095 | { | |
48401fcf | 11096 | as_warn (_("Bad register number")); |
3d3c5039 ILT |
11097 | reg = 0; |
11098 | } | |
11099 | } | |
11100 | else | |
11101 | { | |
11102 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 11103 | reg = FP; |
3d3c5039 | 11104 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 11105 | reg = SP; |
3d3c5039 | 11106 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 11107 | reg = GP; |
3d3c5039 | 11108 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 11109 | reg = AT; |
3d3c5039 ILT |
11110 | else |
11111 | { | |
48401fcf | 11112 | as_warn (_("Unrecognized register name")); |
0dd2d296 | 11113 | reg = 0; |
3d3c5039 ILT |
11114 | } |
11115 | input_line_pointer += 2; | |
11116 | } | |
0dd2d296 ILT |
11117 | if (frame) |
11118 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
11119 | return reg; |
11120 | } | |
11121 | ||
0dd2d296 ILT |
11122 | valueT |
11123 | md_section_align (seg, addr) | |
11124 | asection *seg; | |
11125 | valueT addr; | |
11126 | { | |
11127 | int align = bfd_get_section_alignment (stdoutput, seg); | |
11128 | ||
cf32394d ILT |
11129 | #ifdef OBJ_ELF |
11130 | /* We don't need to align ELF sections to the full alignment. | |
11131 | However, Irix 5 may prefer that we align them at least to a 16 | |
08e17202 ILT |
11132 | byte boundary. We don't bother to align the sections if we are |
11133 | targeted for an embedded system. */ | |
11134 | if (strcmp (TARGET_OS, "elf") == 0) | |
11135 | return addr; | |
943321c0 ILT |
11136 | if (align > 4) |
11137 | align = 4; | |
10a14e36 | 11138 | #endif |
cf32394d ILT |
11139 | |
11140 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
0dd2d296 ILT |
11141 | } |
11142 | ||
d8a1c247 KR |
11143 | /* Utility routine, called from above as well. If called while the |
11144 | input file is still being read, it's only an approximation. (For | |
11145 | example, a symbol may later become defined which appeared to be | |
11146 | undefined earlier.) */ | |
22ba90ce ILT |
11147 | |
11148 | static int | |
85ce5635 | 11149 | nopic_need_relax (sym, before_relaxing) |
d8a1c247 | 11150 | symbolS *sym; |
85ce5635 | 11151 | int before_relaxing; |
d8a1c247 KR |
11152 | { |
11153 | if (sym == 0) | |
11154 | return 0; | |
11155 | ||
1dc1e798 KR |
11156 | if (USE_GLOBAL_POINTER_OPT) |
11157 | { | |
11158 | const char *symname; | |
11159 | int change; | |
11160 | ||
11161 | /* Find out whether this symbol can be referenced off the GP | |
11162 | register. It can be if it is smaller than the -G size or if | |
11163 | it is in the .sdata or .sbss section. Certain symbols can | |
11164 | not be referenced off the GP, although it appears as though | |
11165 | they can. */ | |
11166 | symname = S_GET_NAME (sym); | |
11167 | if (symname != (const char *) NULL | |
11168 | && (strcmp (symname, "eprol") == 0 | |
11169 | || strcmp (symname, "etext") == 0 | |
11170 | || strcmp (symname, "_gp") == 0 | |
11171 | || strcmp (symname, "edata") == 0 | |
11172 | || strcmp (symname, "_fbss") == 0 | |
11173 | || strcmp (symname, "_fdata") == 0 | |
11174 | || strcmp (symname, "_ftext") == 0 | |
11175 | || strcmp (symname, "end") == 0 | |
11176 | || strcmp (symname, "_gp_disp") == 0)) | |
11177 | change = 1; | |
23ac3ca1 | 11178 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) |
c625fc23 JSC |
11179 | && (0 |
11180 | #ifndef NO_ECOFF_DEBUGGING | |
11181 | || (sym->ecoff_extern_size != 0 | |
11182 | && sym->ecoff_extern_size <= g_switch_value) | |
a5586bdc | 11183 | #endif |
85ce5635 ILT |
11184 | /* We must defer this decision until after the whole |
11185 | file has been read, since there might be a .extern | |
11186 | after the first use of this symbol. */ | |
a5586bdc ILT |
11187 | || (before_relaxing |
11188 | #ifndef NO_ECOFF_DEBUGGING | |
11189 | && sym->ecoff_extern_size == 0 | |
c625fc23 | 11190 | #endif |
a5586bdc | 11191 | && S_GET_VALUE (sym) == 0) |
1dc1e798 KR |
11192 | || (S_GET_VALUE (sym) != 0 |
11193 | && S_GET_VALUE (sym) <= g_switch_value))) | |
11194 | change = 0; | |
11195 | else | |
11196 | { | |
11197 | const char *segname; | |
d8a1c247 | 11198 | |
1dc1e798 KR |
11199 | segname = segment_name (S_GET_SEGMENT (sym)); |
11200 | assert (strcmp (segname, ".lit8") != 0 | |
11201 | && strcmp (segname, ".lit4") != 0); | |
11202 | change = (strcmp (segname, ".sdata") != 0 | |
11203 | && strcmp (segname, ".sbss") != 0); | |
11204 | } | |
11205 | return change; | |
11206 | } | |
11207 | else | |
11208 | /* We are not optimizing for the GP register. */ | |
11209 | return 1; | |
d8a1c247 KR |
11210 | } |
11211 | ||
cc5703cd ILT |
11212 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
11213 | extended opcode. SEC is the section the frag is in. */ | |
11214 | ||
11215 | static int | |
11216 | mips16_extended_frag (fragp, sec, stretch) | |
11217 | fragS *fragp; | |
11218 | asection *sec; | |
11219 | long stretch; | |
11220 | { | |
11221 | int type; | |
11222 | register const struct mips16_immed_operand *op; | |
11223 | offsetT val; | |
11224 | int mintiny, maxtiny; | |
f74ba7a3 | 11225 | segT symsec; |
cc5703cd | 11226 | |
8728fa92 ILT |
11227 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) |
11228 | return 0; | |
11229 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
11230 | return 1; | |
11231 | ||
cc5703cd ILT |
11232 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
11233 | op = mips16_immed_operands; | |
11234 | while (op->type != type) | |
11235 | { | |
11236 | ++op; | |
11237 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
11238 | } | |
11239 | ||
11240 | if (op->unsp) | |
11241 | { | |
11242 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
11243 | { | |
11244 | mintiny = 1; | |
11245 | maxtiny = 1 << op->nbits; | |
11246 | } | |
11247 | else | |
11248 | { | |
11249 | mintiny = 0; | |
11250 | maxtiny = (1 << op->nbits) - 1; | |
11251 | } | |
11252 | } | |
11253 | else | |
11254 | { | |
11255 | mintiny = - (1 << (op->nbits - 1)); | |
11256 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
11257 | } | |
11258 | ||
f74ba7a3 ILT |
11259 | /* We can't call S_GET_VALUE here, because we don't want to lock in |
11260 | a particular frag address. */ | |
11261 | if (fragp->fr_symbol->sy_value.X_op == O_constant) | |
11262 | { | |
11263 | val = (fragp->fr_symbol->sy_value.X_add_number | |
11264 | + fragp->fr_symbol->sy_frag->fr_address); | |
11265 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
11266 | } | |
11267 | else if (fragp->fr_symbol->sy_value.X_op == O_symbol | |
11268 | && (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_op | |
11269 | == O_constant)) | |
11270 | { | |
11271 | val = (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_add_number | |
11272 | + fragp->fr_symbol->sy_value.X_add_symbol->sy_frag->fr_address | |
11273 | + fragp->fr_symbol->sy_value.X_add_number | |
11274 | + fragp->fr_symbol->sy_frag->fr_address); | |
11275 | symsec = S_GET_SEGMENT (fragp->fr_symbol->sy_value.X_add_symbol); | |
11276 | } | |
11277 | else | |
11278 | return 1; | |
cc5703cd ILT |
11279 | |
11280 | if (op->pcrel) | |
11281 | { | |
11282 | addressT addr; | |
11283 | ||
11284 | /* We won't have the section when we are called from | |
11285 | mips_relax_frag. However, we will always have been called | |
11286 | from md_estimate_size_before_relax first. If this is a | |
11287 | branch to a different section, we mark it as such. If SEC is | |
11288 | NULL, and the frag is not marked, then it must be a branch to | |
11289 | the same section. */ | |
11290 | if (sec == NULL) | |
11291 | { | |
11292 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
11293 | return 1; | |
11294 | } | |
11295 | else | |
11296 | { | |
f74ba7a3 | 11297 | if (symsec != sec) |
cc5703cd ILT |
11298 | { |
11299 | fragp->fr_subtype = | |
11300 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
11301 | ||
11302 | /* FIXME: We should support this, and let the linker | |
11303 | catch branches and loads that are out of range. */ | |
11304 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
48401fcf | 11305 | _("unsupported PC relative reference to different section")); |
cc5703cd ILT |
11306 | |
11307 | return 1; | |
11308 | } | |
11309 | } | |
11310 | ||
11311 | /* In this case, we know for sure that the symbol fragment is in | |
11312 | the same section. If the fr_address of the symbol fragment | |
11313 | is greater then the address of this fragment we want to add | |
11314 | in STRETCH in order to get a better estimate of the address. | |
11315 | This particularly matters because of the shift bits. */ | |
11316 | if (stretch != 0 | |
11317 | && fragp->fr_symbol->sy_frag->fr_address >= fragp->fr_address) | |
11318 | { | |
11319 | fragS *f; | |
11320 | ||
a941619c ILT |
11321 | /* Adjust stretch for any alignment frag. Note that if have |
11322 | been expanding the earlier code, the symbol may be | |
11323 | defined in what appears to be an earlier frag. FIXME: | |
11324 | This doesn't handle the fr_subtype field, which specifies | |
11325 | a maximum number of bytes to skip when doing an | |
11326 | alignment. */ | |
11327 | for (f = fragp; | |
11328 | f != NULL && f != fragp->fr_symbol->sy_frag; | |
11329 | f = f->fr_next) | |
cc5703cd | 11330 | { |
cc5703cd ILT |
11331 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) |
11332 | { | |
11333 | if (stretch < 0) | |
11334 | stretch = - ((- stretch) | |
11335 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
11336 | else | |
11337 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
11338 | if (stretch == 0) | |
11339 | break; | |
11340 | } | |
11341 | } | |
a941619c ILT |
11342 | if (f != NULL) |
11343 | val += stretch; | |
cc5703cd ILT |
11344 | } |
11345 | ||
a677feeb ILT |
11346 | addr = fragp->fr_address + fragp->fr_fix; |
11347 | ||
11348 | /* The base address rules are complicated. The base address of | |
11349 | a branch is the following instruction. The base address of a | |
11350 | PC relative load or add is the instruction itself, but if it | |
319305a7 ILT |
11351 | is in a delay slot (in which case it can not be extended) use |
11352 | the address of the instruction whose delay slot it is in. */ | |
a677feeb | 11353 | if (type == 'p' || type == 'q') |
fbcfacb7 ILT |
11354 | { |
11355 | addr += 2; | |
319305a7 ILT |
11356 | |
11357 | /* If we are currently assuming that this frag should be | |
11358 | extended, then, the current address is two bytes | |
11359 | higher. */ | |
11360 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11361 | addr += 2; | |
11362 | ||
fbcfacb7 ILT |
11363 | /* Ignore the low bit in the target, since it will be set |
11364 | for a text label. */ | |
11365 | if ((val & 1) != 0) | |
11366 | --val; | |
11367 | } | |
a677feeb ILT |
11368 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
11369 | addr -= 4; | |
11370 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
11371 | addr -= 2; | |
cc5703cd | 11372 | |
cc5703cd ILT |
11373 | val -= addr & ~ ((1 << op->shift) - 1); |
11374 | ||
11375 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
11376 | if (type == 'p' || type == 'q') | |
11377 | val /= 2; | |
11378 | ||
11379 | /* If any of the shifted bits are set, we must use an extended | |
11380 | opcode. If the address depends on the size of this | |
11381 | instruction, this can lead to a loop, so we arrange to always | |
559c664a ILT |
11382 | use an extended opcode. We only check this when we are in |
11383 | the main relaxation loop, when SEC is NULL. */ | |
11384 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
11385 | { | |
11386 | fragp->fr_subtype = | |
11387 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
11388 | return 1; | |
11389 | } | |
11390 | ||
11391 | /* If we are about to mark a frag as extended because the value | |
11392 | is precisely maxtiny + 1, then there is a chance of an | |
11393 | infinite loop as in the following code: | |
11394 | la $4,foo | |
11395 | .skip 1020 | |
11396 | .align 2 | |
11397 | foo: | |
11398 | In this case when the la is extended, foo is 0x3fc bytes | |
11399 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
11400 | the la must be extended. To avoid this loop, we mark the | |
11401 | frag as extended if it was small, and is about to become | |
11402 | extended with a value of maxtiny + 1. */ | |
11403 | if (val == ((maxtiny + 1) << op->shift) | |
11404 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
11405 | && sec == NULL) | |
cc5703cd ILT |
11406 | { |
11407 | fragp->fr_subtype = | |
11408 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
11409 | return 1; | |
11410 | } | |
11411 | } | |
41a0ed22 | 11412 | else if (symsec != absolute_section && sec != NULL) |
48401fcf | 11413 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); |
cc5703cd ILT |
11414 | |
11415 | if ((val & ((1 << op->shift) - 1)) != 0 | |
11416 | || val < (mintiny << op->shift) | |
11417 | || val > (maxtiny << op->shift)) | |
11418 | return 1; | |
11419 | else | |
11420 | return 0; | |
11421 | } | |
11422 | ||
11423 | /* Estimate the size of a frag before relaxing. Unless this is the | |
11424 | mips16, we are not really relaxing here, and the final size is | |
11425 | encoded in the subtype information. For the mips16, we have to | |
11426 | decide whether we are using an extended opcode or not. */ | |
22ba90ce | 11427 | |
0dd2d296 ILT |
11428 | /*ARGSUSED*/ |
11429 | int | |
11430 | md_estimate_size_before_relax (fragp, segtype) | |
11431 | fragS *fragp; | |
11432 | asection *segtype; | |
11433 | { | |
11434 | int change; | |
11435 | ||
cc5703cd ILT |
11436 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
11437 | { | |
11438 | if (mips16_extended_frag (fragp, segtype, 0)) | |
11439 | { | |
11440 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
11441 | return 4; | |
11442 | } | |
11443 | else | |
11444 | { | |
11445 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
11446 | return 2; | |
11447 | } | |
11448 | } | |
11449 | ||
d9aba805 | 11450 | if (mips_pic == NO_PIC) |
0dd2d296 | 11451 | { |
85ce5635 | 11452 | change = nopic_need_relax (fragp->fr_symbol, 0); |
0dd2d296 | 11453 | } |
d9aba805 | 11454 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 11455 | { |
46a92fde ILT |
11456 | symbolS *sym; |
11457 | asection *symsec; | |
11458 | ||
11459 | sym = fragp->fr_symbol; | |
11460 | ||
11461 | /* Handle the case of a symbol equated to another symbol. */ | |
11462 | while (sym->sy_value.X_op == O_symbol | |
11463 | && (! S_IS_DEFINED (sym) || S_IS_COMMON (sym))) | |
11464 | { | |
11465 | symbolS *n; | |
11466 | ||
11467 | /* It's possible to get a loop here in a badly written | |
11468 | program. */ | |
11469 | n = sym->sy_value.X_add_symbol; | |
11470 | if (n == sym) | |
11471 | break; | |
11472 | sym = n; | |
11473 | } | |
11474 | ||
11475 | symsec = S_GET_SEGMENT (sym); | |
0dd2d296 ILT |
11476 | |
11477 | /* This must duplicate the test in adjust_reloc_syms. */ | |
11478 | change = (symsec != &bfd_und_section | |
11479 | && symsec != &bfd_abs_section | |
11480 | && ! bfd_is_com_section (symsec)); | |
11481 | } | |
d9aba805 ILT |
11482 | else |
11483 | abort (); | |
0dd2d296 ILT |
11484 | |
11485 | if (change) | |
11486 | { | |
11487 | /* Record the offset to the first reloc in the fr_opcode field. | |
11488 | This lets md_convert_frag and tc_gen_reloc know that the code | |
11489 | must be expanded. */ | |
11490 | fragp->fr_opcode = (fragp->fr_literal | |
11491 | + fragp->fr_fix | |
11492 | - RELAX_OLD (fragp->fr_subtype) | |
11493 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
11494 | /* FIXME: This really needs as_warn_where. */ | |
11495 | if (RELAX_WARN (fragp->fr_subtype)) | |
48401fcf | 11496 | as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\"")); |
0dd2d296 ILT |
11497 | } |
11498 | ||
11499 | if (! change) | |
11500 | return 0; | |
11501 | else | |
11502 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
11503 | } | |
11504 | ||
0d7f9025 ILT |
11505 | /* This is called to see whether a reloc against a defined symbol |
11506 | should be converted into a reloc against a section. Don't adjust | |
11507 | MIPS16 jump relocations, so we don't have to worry about the format | |
11508 | of the offset in the .o file. Don't adjust relocations against | |
6927c24d ILT |
11509 | mips16 symbols, so that the linker can find them if it needs to set |
11510 | up a stub. */ | |
0d7f9025 ILT |
11511 | |
11512 | int | |
11513 | mips_fix_adjustable (fixp) | |
11514 | fixS *fixp; | |
11515 | { | |
11516 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
11517 | return 0; | |
7e656649 RH |
11518 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
11519 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11520 | return 0; | |
0d7f9025 ILT |
11521 | if (fixp->fx_addsy == NULL) |
11522 | return 1; | |
68952421 | 11523 | #ifdef OBJ_ELF |
0d7f9025 | 11524 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
46a92fde ILT |
11525 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 |
11526 | && fixp->fx_subsy == NULL) | |
0d7f9025 ILT |
11527 | return 0; |
11528 | #endif | |
11529 | return 1; | |
11530 | } | |
11531 | ||
0dd2d296 ILT |
11532 | /* Translate internal representation of relocation info to BFD target |
11533 | format. */ | |
11534 | ||
11535 | arelent ** | |
3d3c5039 ILT |
11536 | tc_gen_reloc (section, fixp) |
11537 | asection *section; | |
11538 | fixS *fixp; | |
11539 | { | |
0dd2d296 | 11540 | static arelent *retval[4]; |
3d3c5039 | 11541 | arelent *reloc; |
a8aed9dd | 11542 | bfd_reloc_code_real_type code; |
3d3c5039 | 11543 | |
0dd2d296 ILT |
11544 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
11545 | retval[1] = NULL; | |
3d3c5039 ILT |
11546 | |
11547 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
11548 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
11549 | |
11550 | if (mips_pic == EMBEDDED_PIC | |
11551 | && SWITCH_TABLE (fixp)) | |
11552 | { | |
11553 | /* For a switch table entry we use a special reloc. The addend | |
11554 | is actually the difference between the reloc address and the | |
11555 | subtrahend. */ | |
11556 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
1dc1e798 | 11557 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
48401fcf | 11558 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); |
1c803e52 ILT |
11559 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
11560 | } | |
ecd4ca1c ILT |
11561 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
11562 | { | |
11563 | /* We use a special addend for an internal RELLO reloc. */ | |
11564 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
11565 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
11566 | else | |
11567 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
11568 | } | |
11569 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
11570 | { | |
11571 | assert (fixp->fx_next != NULL | |
11572 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
11573 | /* We use a special addend for an internal RELHI reloc. The | |
11574 | reloc is relative to the RELLO; adjust the addend | |
11575 | accordingly. */ | |
11576 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
11577 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
11578 | + fixp->fx_next->fx_where | |
11579 | - S_GET_VALUE (fixp->fx_subsy)); | |
11580 | else | |
11581 | reloc->addend = (fixp->fx_addnumber | |
11582 | + fixp->fx_next->fx_frag->fr_address | |
11583 | + fixp->fx_next->fx_where); | |
11584 | } | |
1c803e52 | 11585 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
11586 | reloc->addend = fixp->fx_addnumber; |
11587 | else | |
5b63f465 | 11588 | { |
1dc1e798 KR |
11589 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
11590 | /* A gruesome hack which is a result of the gruesome gas reloc | |
11591 | handling. */ | |
11592 | reloc->addend = reloc->address; | |
11593 | else | |
11594 | reloc->addend = -reloc->address; | |
5b63f465 | 11595 | } |
0dd2d296 ILT |
11596 | |
11597 | /* If this is a variant frag, we may need to adjust the existing | |
11598 | reloc and generate a new one. */ | |
11599 | if (fixp->fx_frag->fr_opcode != NULL | |
11600 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
11601 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
fb251650 ILT |
11602 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
11603 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
11604 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
11605 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
11606 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
0dd2d296 ILT |
11607 | { |
11608 | arelent *reloc2; | |
11609 | ||
cc5703cd ILT |
11610 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); |
11611 | ||
0dd2d296 | 11612 | /* If this is not the last reloc in this frag, then we have two |
fb251650 ILT |
11613 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
11614 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
11615 | the second one handle all of them. */ | |
0dd2d296 ILT |
11616 | if (fixp->fx_next != NULL |
11617 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
11618 | { | |
fb251650 ILT |
11619 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
11620 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
11621 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
11622 | && (fixp->fx_next->fx_r_type | |
11623 | == BFD_RELOC_MIPS_GOT_LO16)) | |
11624 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
11625 | && (fixp->fx_next->fx_r_type | |
11626 | == BFD_RELOC_MIPS_CALL_LO16))); | |
0dd2d296 ILT |
11627 | retval[0] = NULL; |
11628 | return retval; | |
11629 | } | |
11630 | ||
11631 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
11632 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
11633 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
11634 | retval[2] = NULL; | |
11635 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
11636 | reloc2->address = (reloc->address | |
11637 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
11638 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
11639 | reloc2->addend = fixp->fx_addnumber; | |
11640 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
11641 | assert (reloc2->howto != NULL); | |
11642 | ||
11643 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
11644 | { | |
11645 | arelent *reloc3; | |
11646 | ||
11647 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
11648 | retval[3] = NULL; | |
11649 | *reloc3 = *reloc2; | |
11650 | reloc3->address += 4; | |
11651 | } | |
11652 | ||
d9aba805 | 11653 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
11654 | { |
11655 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
11656 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
11657 | } | |
d9aba805 | 11658 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 11659 | { |
fb251650 | 11660 | switch (fixp->fx_r_type) |
0dd2d296 | 11661 | { |
fb251650 ILT |
11662 | default: |
11663 | abort (); | |
11664 | case BFD_RELOC_MIPS_GOT16: | |
11665 | break; | |
11666 | case BFD_RELOC_MIPS_CALL16: | |
11667 | case BFD_RELOC_MIPS_GOT_LO16: | |
11668 | case BFD_RELOC_MIPS_CALL_LO16: | |
0dd2d296 | 11669 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
fb251650 | 11670 | break; |
0dd2d296 ILT |
11671 | } |
11672 | } | |
d9aba805 ILT |
11673 | else |
11674 | abort (); | |
0dd2d296 ILT |
11675 | } |
11676 | ||
7e656649 RH |
11677 | /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry |
11678 | to be used in the relocation's section offset. */ | |
11679 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11680 | { | |
11681 | reloc->address = reloc->addend; | |
11682 | reloc->addend = 0; | |
11683 | } | |
11684 | ||
a8aed9dd ILT |
11685 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that |
11686 | fixup_segment converted a non-PC relative reloc into a PC | |
11687 | relative reloc. In such a case, we need to convert the reloc | |
11688 | code. */ | |
11689 | code = fixp->fx_r_type; | |
11690 | if (fixp->fx_pcrel) | |
11691 | { | |
11692 | switch (code) | |
11693 | { | |
11694 | case BFD_RELOC_8: | |
11695 | code = BFD_RELOC_8_PCREL; | |
11696 | break; | |
11697 | case BFD_RELOC_16: | |
11698 | code = BFD_RELOC_16_PCREL; | |
11699 | break; | |
11700 | case BFD_RELOC_32: | |
11701 | code = BFD_RELOC_32_PCREL; | |
11702 | break; | |
bf39474f ILT |
11703 | case BFD_RELOC_64: |
11704 | code = BFD_RELOC_64_PCREL; | |
11705 | break; | |
a8aed9dd ILT |
11706 | case BFD_RELOC_8_PCREL: |
11707 | case BFD_RELOC_16_PCREL: | |
11708 | case BFD_RELOC_32_PCREL: | |
bf39474f | 11709 | case BFD_RELOC_64_PCREL: |
a8aed9dd | 11710 | case BFD_RELOC_16_PCREL_S2: |
97aca1bc ILT |
11711 | case BFD_RELOC_PCREL_HI16_S: |
11712 | case BFD_RELOC_PCREL_LO16: | |
a8aed9dd ILT |
11713 | break; |
11714 | default: | |
11715 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
48401fcf | 11716 | _("Cannot make %s relocation PC relative"), |
a8aed9dd ILT |
11717 | bfd_get_reloc_code_name (code)); |
11718 | } | |
11719 | } | |
11720 | ||
d9aba805 ILT |
11721 | /* To support a PC relative reloc when generating embedded PIC code |
11722 | for ECOFF, we use a Cygnus extension. We check for that here to | |
11723 | make sure that we don't let such a reloc escape normally. */ | |
1dc1e798 | 11724 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
a8aed9dd | 11725 | && code == BFD_RELOC_16_PCREL_S2 |
d9aba805 ILT |
11726 | && mips_pic != EMBEDDED_PIC) |
11727 | reloc->howto = NULL; | |
11728 | else | |
a8aed9dd | 11729 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
0dd2d296 | 11730 | |
52aa70b5 JW |
11731 | if (reloc->howto == NULL) |
11732 | { | |
11733 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
48401fcf | 11734 | _("Can not represent %s relocation in this object file format"), |
a8aed9dd | 11735 | bfd_get_reloc_code_name (code)); |
0dd2d296 | 11736 | retval[0] = NULL; |
52aa70b5 | 11737 | } |
3d3c5039 | 11738 | |
0dd2d296 | 11739 | return retval; |
3d3c5039 ILT |
11740 | } |
11741 | ||
cc5703cd ILT |
11742 | /* Relax a machine dependent frag. This returns the amount by which |
11743 | the current size of the frag should change. */ | |
11744 | ||
11745 | int | |
11746 | mips_relax_frag (fragp, stretch) | |
11747 | fragS *fragp; | |
11748 | long stretch; | |
11749 | { | |
11750 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
11751 | return 0; | |
11752 | ||
11753 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
11754 | { | |
11755 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11756 | return 0; | |
11757 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
11758 | return 2; | |
11759 | } | |
11760 | else | |
11761 | { | |
11762 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11763 | return 0; | |
11764 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
11765 | return -2; | |
11766 | } | |
11767 | ||
11768 | return 0; | |
11769 | } | |
11770 | ||
0dd2d296 ILT |
11771 | /* Convert a machine dependent frag. */ |
11772 | ||
11773 | void | |
11774 | md_convert_frag (abfd, asec, fragp) | |
11775 | bfd *abfd; | |
11776 | segT asec; | |
11777 | fragS *fragp; | |
3d3c5039 | 11778 | { |
0dd2d296 ILT |
11779 | int old, new; |
11780 | char *fixptr; | |
3d3c5039 | 11781 | |
cc5703cd ILT |
11782 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
11783 | { | |
11784 | int type; | |
11785 | register const struct mips16_immed_operand *op; | |
11786 | boolean small, ext; | |
11787 | offsetT val; | |
11788 | bfd_byte *buf; | |
11789 | unsigned long insn; | |
11790 | boolean use_extend; | |
11791 | unsigned short extend; | |
11792 | ||
11793 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
11794 | op = mips16_immed_operands; | |
11795 | while (op->type != type) | |
11796 | ++op; | |
11797 | ||
11798 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11799 | { | |
11800 | small = false; | |
11801 | ext = true; | |
11802 | } | |
11803 | else | |
11804 | { | |
11805 | small = true; | |
11806 | ext = false; | |
11807 | } | |
11808 | ||
b637f306 | 11809 | resolve_symbol_value (fragp->fr_symbol, 1); |
cc5703cd | 11810 | val = S_GET_VALUE (fragp->fr_symbol); |
cc5703cd ILT |
11811 | if (op->pcrel) |
11812 | { | |
11813 | addressT addr; | |
11814 | ||
a677feeb ILT |
11815 | addr = fragp->fr_address + fragp->fr_fix; |
11816 | ||
11817 | /* The rules for the base address of a PC relative reloc are | |
11818 | complicated; see mips16_extended_frag. */ | |
11819 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
11820 | { |
11821 | addr += 2; | |
319305a7 ILT |
11822 | if (ext) |
11823 | addr += 2; | |
fbcfacb7 ILT |
11824 | /* Ignore the low bit in the target, since it will be |
11825 | set for a text label. */ | |
11826 | if ((val & 1) != 0) | |
11827 | --val; | |
11828 | } | |
a677feeb ILT |
11829 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
11830 | addr -= 4; | |
11831 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
11832 | addr -= 2; | |
11833 | ||
cc5703cd ILT |
11834 | addr &= ~ (addressT) ((1 << op->shift) - 1); |
11835 | val -= addr; | |
a677feeb ILT |
11836 | |
11837 | /* Make sure the section winds up with the alignment we have | |
11838 | assumed. */ | |
11839 | if (op->shift > 0) | |
11840 | record_alignment (asec, op->shift); | |
cc5703cd ILT |
11841 | } |
11842 | ||
035936da ILT |
11843 | if (ext |
11844 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
11845 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
11846 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
48401fcf | 11847 | _("extended instruction in delay slot")); |
035936da | 11848 | |
cc5703cd ILT |
11849 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); |
11850 | ||
b9129c6f ILT |
11851 | if (target_big_endian) |
11852 | insn = bfd_getb16 (buf); | |
11853 | else | |
11854 | insn = bfd_getl16 (buf); | |
cc5703cd | 11855 | |
31a2c6ff ILT |
11856 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, |
11857 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
11858 | small, ext, &insn, &use_extend, &extend); | |
cc5703cd ILT |
11859 | |
11860 | if (use_extend) | |
11861 | { | |
11862 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
11863 | fragp->fr_fix += 2; | |
11864 | buf += 2; | |
11865 | } | |
3d3c5039 | 11866 | |
cc5703cd ILT |
11867 | md_number_to_chars (buf, insn, 2); |
11868 | fragp->fr_fix += 2; | |
11869 | buf += 2; | |
11870 | } | |
11871 | else | |
11872 | { | |
11873 | if (fragp->fr_opcode == NULL) | |
11874 | return; | |
0dd2d296 | 11875 | |
cc5703cd ILT |
11876 | old = RELAX_OLD (fragp->fr_subtype); |
11877 | new = RELAX_NEW (fragp->fr_subtype); | |
11878 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
0dd2d296 | 11879 | |
cc5703cd ILT |
11880 | if (new > 0) |
11881 | memcpy (fixptr - old, fixptr, new); | |
11882 | ||
11883 | fragp->fr_fix += new - old; | |
11884 | } | |
0dd2d296 | 11885 | } |
becfe05e | 11886 | |
fbcfacb7 ILT |
11887 | #ifdef OBJ_ELF |
11888 | ||
11889 | /* This function is called after the relocs have been generated. | |
11890 | We've been storing mips16 text labels as odd. Here we convert them | |
11891 | back to even for the convenience of the debugger. */ | |
11892 | ||
11893 | void | |
11894 | mips_frob_file_after_relocs () | |
11895 | { | |
11896 | asymbol **syms; | |
11897 | unsigned int count, i; | |
11898 | ||
11899 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
11900 | return; | |
11901 | ||
11902 | syms = bfd_get_outsymbols (stdoutput); | |
11903 | count = bfd_get_symcount (stdoutput); | |
11904 | for (i = 0; i < count; i++, syms++) | |
11905 | { | |
11906 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
11907 | && ((*syms)->value & 1) != 0) | |
11908 | { | |
11909 | (*syms)->value &= ~1; | |
11910 | /* If the symbol has an odd size, it was probably computed | |
11911 | incorrectly, so adjust that as well. */ | |
11912 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
11913 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
11914 | } | |
11915 | } | |
11916 | } | |
11917 | ||
11918 | #endif | |
11919 | ||
becfe05e ILT |
11920 | /* This function is called whenever a label is defined. It is used |
11921 | when handling branch delays; if a branch has a label, we assume we | |
11922 | can not move it. */ | |
11923 | ||
11924 | void | |
11925 | mips_define_label (sym) | |
11926 | symbolS *sym; | |
11927 | { | |
fbcfacb7 ILT |
11928 | struct insn_label_list *l; |
11929 | ||
11930 | if (free_insn_labels == NULL) | |
11931 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
11932 | else | |
11933 | { | |
11934 | l = free_insn_labels; | |
11935 | free_insn_labels = l->next; | |
11936 | } | |
11937 | ||
11938 | l->label = sym; | |
11939 | l->next = insn_labels; | |
11940 | insn_labels = l; | |
becfe05e | 11941 | } |
3d3c5039 | 11942 | \f |
739708fa | 11943 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 11944 | |
0dd2d296 | 11945 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
11946 | |
11947 | void | |
11948 | mips_elf_final_processing () | |
11949 | { | |
87178180 ILT |
11950 | /* Write out the register information. */ |
11951 | if (! mips_64) | |
11952 | { | |
11953 | Elf32_RegInfo s; | |
11954 | ||
11955 | s.ri_gprmask = mips_gprmask; | |
11956 | s.ri_cprmask[0] = mips_cprmask[0]; | |
11957 | s.ri_cprmask[1] = mips_cprmask[1]; | |
11958 | s.ri_cprmask[2] = mips_cprmask[2]; | |
11959 | s.ri_cprmask[3] = mips_cprmask[3]; | |
11960 | /* The gp_value field is set by the MIPS ELF backend. */ | |
11961 | ||
11962 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
11963 | ((Elf32_External_RegInfo *) | |
11964 | mips_regmask_frag)); | |
11965 | } | |
11966 | else | |
11967 | { | |
11968 | Elf64_Internal_RegInfo s; | |
11969 | ||
11970 | s.ri_gprmask = mips_gprmask; | |
11971 | s.ri_pad = 0; | |
11972 | s.ri_cprmask[0] = mips_cprmask[0]; | |
11973 | s.ri_cprmask[1] = mips_cprmask[1]; | |
11974 | s.ri_cprmask[2] = mips_cprmask[2]; | |
11975 | s.ri_cprmask[3] = mips_cprmask[3]; | |
11976 | /* The gp_value field is set by the MIPS ELF backend. */ | |
11977 | ||
11978 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
11979 | ((Elf64_External_RegInfo *) | |
11980 | mips_regmask_frag)); | |
11981 | } | |
0dd2d296 ILT |
11982 | |
11983 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
11984 | sort of BFD interface for this. */ | |
11985 | if (mips_any_noreorder) | |
11986 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 11987 | if (mips_pic != NO_PIC) |
0dd2d296 | 11988 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
11989 | } |
11990 | ||
739708fa | 11991 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
f2a663d3 | 11992 | \f |
670a50eb ILT |
11993 | typedef struct proc |
11994 | { | |
993b4e8d RU |
11995 | struct symbol *isym; |
11996 | unsigned long reg_mask; | |
11997 | unsigned long reg_offset; | |
11998 | unsigned long fpreg_mask; | |
11999 | unsigned long fpreg_offset; | |
12000 | unsigned long frame_offset; | |
12001 | unsigned long frame_reg; | |
12002 | unsigned long pc_reg; | |
670a50eb ILT |
12003 | } |
12004 | procS; | |
3d3c5039 | 12005 | |
993b4e8d RU |
12006 | static procS cur_proc; |
12007 | static procS *cur_proc_ptr; | |
3d3c5039 ILT |
12008 | static int numprocs; |
12009 | ||
12010 | static void | |
12011 | md_obj_begin () | |
12012 | { | |
3d3c5039 ILT |
12013 | } |
12014 | ||
12015 | static void | |
12016 | md_obj_end () | |
12017 | { | |
12018 | /* check for premature end, nesting errors, etc */ | |
993b4e8d | 12019 | if (cur_proc_ptr) |
48401fcf | 12020 | as_warn (_("missing `.end' at end of assembly")); |
3d3c5039 ILT |
12021 | } |
12022 | ||
3d3c5039 ILT |
12023 | static long |
12024 | get_number () | |
12025 | { | |
670a50eb ILT |
12026 | int negative = 0; |
12027 | long val = 0; | |
3d3c5039 | 12028 | |
670a50eb ILT |
12029 | if (*input_line_pointer == '-') |
12030 | { | |
12031 | ++input_line_pointer; | |
12032 | negative = 1; | |
3d3c5039 | 12033 | } |
670a50eb | 12034 | if (!isdigit (*input_line_pointer)) |
48401fcf | 12035 | as_bad (_("Expected simple number.")); |
670a50eb ILT |
12036 | if (input_line_pointer[0] == '0') |
12037 | { | |
12038 | if (input_line_pointer[1] == 'x') | |
12039 | { | |
12040 | input_line_pointer += 2; | |
12041 | while (isxdigit (*input_line_pointer)) | |
12042 | { | |
12043 | val <<= 4; | |
3a762a0b | 12044 | val |= hex_value (*input_line_pointer++); |
3d3c5039 | 12045 | } |
670a50eb ILT |
12046 | return negative ? -val : val; |
12047 | } | |
12048 | else | |
12049 | { | |
12050 | ++input_line_pointer; | |
12051 | while (isdigit (*input_line_pointer)) | |
12052 | { | |
12053 | val <<= 3; | |
12054 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 12055 | } |
670a50eb | 12056 | return negative ? -val : val; |
3d3c5039 ILT |
12057 | } |
12058 | } | |
670a50eb ILT |
12059 | if (!isdigit (*input_line_pointer)) |
12060 | { | |
48401fcf | 12061 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), |
670a50eb | 12062 | *input_line_pointer, *input_line_pointer); |
48401fcf | 12063 | as_warn (_("Invalid number")); |
670a50eb | 12064 | return -1; |
3d3c5039 | 12065 | } |
670a50eb ILT |
12066 | while (isdigit (*input_line_pointer)) |
12067 | { | |
12068 | val *= 10; | |
12069 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 12070 | } |
670a50eb | 12071 | return negative ? -val : val; |
3d3c5039 ILT |
12072 | } |
12073 | ||
12074 | /* The .file directive; just like the usual .file directive, but there | |
12075 | is an initial number which is the ECOFF file index. */ | |
12076 | ||
12077 | static void | |
12078 | s_file (x) | |
12079 | int x; | |
12080 | { | |
670a50eb | 12081 | int line; |
3d3c5039 | 12082 | |
670a50eb | 12083 | line = get_number (); |
9a7d824a | 12084 | s_app_file (0); |
3d3c5039 ILT |
12085 | } |
12086 | ||
12087 | ||
12088 | /* The .end directive. */ | |
12089 | ||
12090 | static void | |
993b4e8d | 12091 | s_mips_end (x) |
3d3c5039 ILT |
12092 | int x; |
12093 | { | |
670a50eb | 12094 | symbolS *p; |
993b4e8d | 12095 | int maybe_text; |
670a50eb ILT |
12096 | |
12097 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
12098 | { | |
12099 | p = get_symbol (); | |
12100 | demand_empty_rest_of_line (); | |
12101 | } | |
12102 | else | |
12103 | p = NULL; | |
993b4e8d RU |
12104 | |
12105 | #ifdef BFD_ASSEMBLER | |
12106 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
12107 | maybe_text = 1; | |
12108 | else | |
12109 | maybe_text = 0; | |
12110 | #else | |
12111 | if (now_seg != data_section && now_seg != bss_section) | |
12112 | maybe_text = 1; | |
12113 | else | |
12114 | maybe_text = 0; | |
12115 | #endif | |
12116 | ||
12117 | if (!maybe_text) | |
48401fcf | 12118 | as_warn (_(".end not in text section")); |
993b4e8d RU |
12119 | |
12120 | if (!cur_proc_ptr) | |
670a50eb | 12121 | { |
993b4e8d RU |
12122 | as_warn (_(".end directive without a preceding .ent directive.")); |
12123 | demand_empty_rest_of_line (); | |
670a50eb | 12124 | return; |
3d3c5039 ILT |
12125 | } |
12126 | ||
670a50eb ILT |
12127 | if (p != NULL) |
12128 | { | |
12129 | assert (S_GET_NAME (p)); | |
993b4e8d | 12130 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) |
48401fcf | 12131 | as_warn (_(".end symbol does not match .ent symbol.")); |
3d3c5039 | 12132 | } |
993b4e8d RU |
12133 | else |
12134 | as_warn (_(".end directive missing or unknown symbol")); | |
12135 | ||
12136 | #ifdef MIPS_STABS_ELF | |
12137 | { | |
12138 | segT saved_seg = now_seg; | |
12139 | subsegT saved_subseg = now_subseg; | |
12140 | fragS *saved_frag = frag_now; | |
12141 | valueT dot; | |
12142 | segT seg; | |
12143 | expressionS exp; | |
12144 | char *fragp; | |
12145 | ||
12146 | dot = frag_now_fix (); | |
12147 | ||
12148 | #ifdef md_flush_pending_output | |
12149 | md_flush_pending_output (); | |
12150 | #endif | |
12151 | ||
12152 | assert (pdr_seg); | |
12153 | subseg_set (pdr_seg, 0); | |
12154 | ||
12155 | /* Write the symbol */ | |
12156 | exp.X_op = O_symbol; | |
12157 | exp.X_add_symbol = p; | |
12158 | exp.X_add_number = 0; | |
12159 | emit_expr (&exp, 4); | |
3d3c5039 | 12160 | |
993b4e8d RU |
12161 | fragp = frag_more (7*4); |
12162 | ||
12163 | md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4); | |
12164 | md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4); | |
12165 | md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4); | |
12166 | md_number_to_chars (fragp +12, (valueT) cur_proc_ptr->fpreg_offset, 4); | |
12167 | md_number_to_chars (fragp +16, (valueT) cur_proc_ptr->frame_offset, 4); | |
12168 | md_number_to_chars (fragp +20, (valueT) cur_proc_ptr->frame_reg, 4); | |
12169 | md_number_to_chars (fragp +24, (valueT) cur_proc_ptr->pc_reg, 4); | |
12170 | ||
12171 | subseg_set (saved_seg, saved_subseg); | |
12172 | } | |
12173 | #endif | |
12174 | ||
12175 | cur_proc_ptr = NULL; | |
3d3c5039 ILT |
12176 | } |
12177 | ||
12178 | /* The .aent and .ent directives. */ | |
12179 | ||
12180 | static void | |
993b4e8d | 12181 | s_mips_ent (aent) |
3d3c5039 ILT |
12182 | int aent; |
12183 | { | |
670a50eb | 12184 | int number = 0; |
670a50eb | 12185 | symbolS *symbolP; |
993b4e8d | 12186 | int maybe_text; |
670a50eb ILT |
12187 | |
12188 | symbolP = get_symbol (); | |
12189 | if (*input_line_pointer == ',') | |
12190 | input_line_pointer++; | |
dd3f1f76 | 12191 | SKIP_WHITESPACE (); |
670a50eb ILT |
12192 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
12193 | number = get_number (); | |
993b4e8d RU |
12194 | |
12195 | #ifdef BFD_ASSEMBLER | |
12196 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
12197 | maybe_text = 1; | |
12198 | else | |
12199 | maybe_text = 0; | |
12200 | #else | |
12201 | if (now_seg != data_section && now_seg != bss_section) | |
12202 | maybe_text = 1; | |
12203 | else | |
12204 | maybe_text = 0; | |
12205 | #endif | |
12206 | ||
12207 | if (!maybe_text) | |
48401fcf | 12208 | as_warn (_(".ent or .aent not in text section.")); |
670a50eb | 12209 | |
993b4e8d | 12210 | if (!aent && cur_proc_ptr) |
48401fcf | 12211 | as_warn (_("missing `.end'")); |
670a50eb ILT |
12212 | |
12213 | if (!aent) | |
12214 | { | |
993b4e8d RU |
12215 | cur_proc_ptr = &cur_proc; |
12216 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
12217 | ||
12218 | cur_proc_ptr->isym = symbolP; | |
6b34ac5a ILT |
12219 | |
12220 | symbolP->bsym->flags |= BSF_FUNCTION; | |
12221 | ||
670a50eb | 12222 | numprocs++; |
3d3c5039 | 12223 | } |
993b4e8d | 12224 | |
670a50eb | 12225 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
12226 | } |
12227 | ||
993b4e8d RU |
12228 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) |
12229 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, | |
12230 | s_mips_frame is used so that we can set the PDR information correctly. | |
12231 | We can't use the ecoff routines because they make reference to the ecoff | |
12232 | symbol table (in the mdebug section). */ | |
3d3c5039 ILT |
12233 | |
12234 | static void | |
993b4e8d RU |
12235 | s_mips_frame (ignore) |
12236 | int ignore; | |
3d3c5039 | 12237 | { |
993b4e8d | 12238 | #ifdef MIPS_STABS_ELF |
670a50eb | 12239 | |
993b4e8d RU |
12240 | long val; |
12241 | ||
12242 | if (cur_proc_ptr == (procS *) NULL) | |
12243 | { | |
12244 | as_warn (_(".frame outside of .ent")); | |
12245 | demand_empty_rest_of_line (); | |
12246 | return; | |
3d3c5039 | 12247 | } |
993b4e8d RU |
12248 | |
12249 | cur_proc_ptr->frame_reg = tc_get_register (1); | |
12250 | ||
12251 | SKIP_WHITESPACE (); | |
12252 | if (*input_line_pointer++ != ',' | |
12253 | || get_absolute_expression_and_terminator (&val) != ',') | |
12254 | { | |
12255 | as_warn (_("Bad .frame directive")); | |
12256 | --input_line_pointer; | |
12257 | demand_empty_rest_of_line (); | |
12258 | return; | |
12259 | } | |
12260 | ||
12261 | cur_proc_ptr->frame_offset = val; | |
12262 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
12263 | ||
670a50eb | 12264 | demand_empty_rest_of_line (); |
993b4e8d RU |
12265 | #else |
12266 | s_ignore (ignore); | |
12267 | #endif /* MIPS_STABS_ELF */ | |
3d3c5039 ILT |
12268 | } |
12269 | ||
993b4e8d RU |
12270 | /* The .fmask and .mask directives. If the mdebug section is present |
12271 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
12272 | embedded targets, s_mips_mask is used so that we can set the PDR | |
12273 | information correctly. We can't use the ecoff routines because they | |
12274 | make reference to the ecoff symbol table (in the mdebug section). */ | |
3d3c5039 ILT |
12275 | |
12276 | static void | |
993b4e8d | 12277 | s_mips_mask (reg_type) |
3d3c5039 ILT |
12278 | char reg_type; |
12279 | { | |
993b4e8d RU |
12280 | #ifdef MIPS_STABS_ELF |
12281 | long mask, off; | |
12282 | ||
12283 | if (cur_proc_ptr == (procS *) NULL) | |
12284 | { | |
12285 | as_warn (_(".mask/.fmask outside of .ent")); | |
12286 | demand_empty_rest_of_line (); | |
12287 | return; | |
12288 | } | |
12289 | ||
12290 | if (get_absolute_expression_and_terminator (&mask) != ',') | |
12291 | { | |
12292 | as_warn (_("Bad .mask/.fmask directive")); | |
12293 | --input_line_pointer; | |
12294 | demand_empty_rest_of_line (); | |
12295 | return; | |
12296 | } | |
670a50eb | 12297 | |
670a50eb ILT |
12298 | off = get_absolute_expression (); |
12299 | ||
670a50eb ILT |
12300 | if (reg_type == 'F') |
12301 | { | |
993b4e8d RU |
12302 | cur_proc_ptr->fpreg_mask = mask; |
12303 | cur_proc_ptr->fpreg_offset = off; | |
3d3c5039 | 12304 | } |
670a50eb ILT |
12305 | else |
12306 | { | |
993b4e8d RU |
12307 | cur_proc_ptr->reg_mask = mask; |
12308 | cur_proc_ptr->reg_offset = off; | |
670a50eb ILT |
12309 | } |
12310 | ||
993b4e8d RU |
12311 | demand_empty_rest_of_line (); |
12312 | #else | |
12313 | s_ignore (reg_type); | |
12314 | #endif /* MIPS_STABS_ELF */ | |
3d3c5039 ILT |
12315 | } |
12316 | ||
12317 | /* The .loc directive. */ | |
12318 | ||
88225433 | 12319 | #if 0 |
3d3c5039 ILT |
12320 | static void |
12321 | s_loc (x) | |
12322 | int x; | |
12323 | { | |
670a50eb ILT |
12324 | symbolS *symbolP; |
12325 | int lineno; | |
12326 | int addroff; | |
3d3c5039 | 12327 | |
670a50eb | 12328 | assert (now_seg == text_section); |
3d3c5039 | 12329 | |
670a50eb | 12330 | lineno = get_number (); |
87e48495 | 12331 | addroff = frag_now_fix (); |
3d3c5039 | 12332 | |
670a50eb ILT |
12333 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
12334 | S_SET_TYPE (symbolP, N_SLINE); | |
12335 | S_SET_OTHER (symbolP, 0); | |
12336 | S_SET_DESC (symbolP, lineno); | |
12337 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 12338 | } |
88225433 | 12339 | #endif |
993b4e8d RU |
12340 | |
12341 | ||
12342 |