Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
056350c6 | 2 | Copyright (C) 1993, 94, 95, 96, 97, 98, 1999, 2000 Free Software Foundation, Inc. |
252b5132 RH |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
6 | Support. | |
7 | ||
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to the Free | |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
24 | ||
25 | #include "as.h" | |
26 | #include "config.h" | |
27 | #include "subsegs.h" | |
28 | ||
29 | #include <ctype.h> | |
30 | ||
31 | #ifdef USE_STDARG | |
32 | #include <stdarg.h> | |
33 | #endif | |
34 | #ifdef USE_VARARGS | |
35 | #include <varargs.h> | |
36 | #endif | |
37 | ||
38 | #include "opcode/mips.h" | |
39 | #include "itbl-ops.h" | |
40 | ||
41 | #ifdef DEBUG | |
42 | #define DBG(x) printf x | |
43 | #else | |
44 | #define DBG(x) | |
45 | #endif | |
46 | ||
47 | #ifdef OBJ_MAYBE_ELF | |
48 | /* Clean up namespace so we can include obj-elf.h too. */ | |
49 | static int mips_output_flavor PARAMS ((void)); | |
50 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
51 | #undef OBJ_PROCESS_STAB | |
52 | #undef OUTPUT_FLAVOR | |
53 | #undef S_GET_ALIGN | |
54 | #undef S_GET_SIZE | |
55 | #undef S_SET_ALIGN | |
56 | #undef S_SET_SIZE | |
252b5132 RH |
57 | #undef obj_frob_file |
58 | #undef obj_frob_file_after_relocs | |
59 | #undef obj_frob_symbol | |
60 | #undef obj_pop_insert | |
61 | #undef obj_sec_sym_ok_for_reloc | |
62 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
63 | ||
64 | #include "obj-elf.h" | |
65 | /* Fix any of them that we actually care about. */ | |
66 | #undef OUTPUT_FLAVOR | |
67 | #define OUTPUT_FLAVOR mips_output_flavor() | |
68 | #endif | |
69 | ||
70 | #if defined (OBJ_ELF) | |
71 | #include "elf/mips.h" | |
72 | #endif | |
73 | ||
74 | #ifndef ECOFF_DEBUGGING | |
75 | #define NO_ECOFF_DEBUGGING | |
76 | #define ECOFF_DEBUGGING 0 | |
77 | #endif | |
78 | ||
79 | #include "ecoff.h" | |
80 | ||
81 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
82 | static char *mips_regmask_frag; | |
83 | #endif | |
84 | ||
85 | #define AT 1 | |
86 | #define TREG 24 | |
87 | #define PIC_CALL_REG 25 | |
88 | #define KT0 26 | |
89 | #define KT1 27 | |
90 | #define GP 28 | |
91 | #define SP 29 | |
92 | #define FP 30 | |
93 | #define RA 31 | |
94 | ||
95 | #define ILLEGAL_REG (32) | |
96 | ||
97 | /* Allow override of standard little-endian ECOFF format. */ | |
98 | ||
99 | #ifndef ECOFF_LITTLE_FORMAT | |
100 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
101 | #endif | |
102 | ||
103 | extern int target_big_endian; | |
104 | ||
105 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the | |
106 | 32 bit ABI. This has no meaning for ECOFF. | |
107 | Note that the default is always 32 bit, even if "configured" for | |
108 | 64 bit [e.g. --target=mips64-elf]. */ | |
109 | static int mips_64; | |
110 | ||
111 | /* The default target format to use. */ | |
112 | const char * | |
113 | mips_target_format () | |
114 | { | |
115 | switch (OUTPUT_FLAVOR) | |
116 | { | |
117 | case bfd_target_aout_flavour: | |
118 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
119 | case bfd_target_ecoff_flavour: | |
120 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
056350c6 NC |
121 | case bfd_target_coff_flavour: |
122 | return "pe-mips"; | |
252b5132 | 123 | case bfd_target_elf_flavour: |
8614eeee UC |
124 | #ifdef TE_TMIPS |
125 | /* This is traditional mips */ | |
126 | return (target_big_endian | |
127 | ? "elf32-tradbigmips" : "elf32-tradlittlemips"); | |
128 | #else | |
252b5132 RH |
129 | return (target_big_endian |
130 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
131 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
8614eeee | 132 | #endif |
252b5132 RH |
133 | default: |
134 | abort (); | |
135 | return NULL; | |
136 | } | |
137 | } | |
138 | ||
139 | /* The name of the readonly data section. */ | |
140 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ | |
141 | ? ".data" \ | |
142 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
143 | ? ".rdata" \ | |
056350c6 NC |
144 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
145 | ? ".rdata" \ | |
252b5132 RH |
146 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
147 | ? ".rodata" \ | |
148 | : (abort (), "")) | |
149 | ||
150 | /* This is the set of options which may be modified by the .set | |
151 | pseudo-op. We use a struct so that .set push and .set pop are more | |
152 | reliable. */ | |
153 | ||
154 | struct mips_set_options | |
155 | { | |
156 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 | |
157 | if it has not been initialized. Changed by `.set mipsN', and the | |
158 | -mipsN command line option, and the default CPU. */ | |
159 | int isa; | |
160 | /* Whether we are assembling for the mips16 processor. 0 if we are | |
161 | not, 1 if we are, and -1 if the value has not been initialized. | |
162 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
163 | -nomips16 command line options, and the default CPU. */ | |
164 | int mips16; | |
165 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
166 | reorder' and `.set noreorder'. */ | |
167 | int noreorder; | |
168 | /* Non-zero if we should not permit the $at ($1) register to be used | |
169 | in instructions. Changed by `.set at' and `.set noat'. */ | |
170 | int noat; | |
171 | /* Non-zero if we should warn when a macro instruction expands into | |
172 | more than one machine instruction. Changed by `.set nomacro' and | |
173 | `.set macro'. */ | |
174 | int warn_about_macros; | |
175 | /* Non-zero if we should not move instructions. Changed by `.set | |
176 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
177 | int nomove; | |
178 | /* Non-zero if we should not optimize branches by moving the target | |
179 | of the branch into the delay slot. Actually, we don't perform | |
180 | this optimization anyhow. Changed by `.set bopt' and `.set | |
181 | nobopt'. */ | |
182 | int nobopt; | |
183 | /* Non-zero if we should not autoextend mips16 instructions. | |
184 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
185 | int noautoextend; | |
186 | }; | |
187 | ||
188 | /* This is the struct we use to hold the current set of options. Note | |
189 | that we must set the isa and mips16 fields to -1 to indicate that | |
190 | they have not been initialized. */ | |
191 | ||
43841e91 | 192 | static struct mips_set_options mips_opts = { -1, -1, 0, 0, 0, 0, 0, 0 }; |
252b5132 RH |
193 | |
194 | /* These variables are filled in with the masks of registers used. | |
195 | The object format code reads them and puts them in the appropriate | |
196 | place. */ | |
197 | unsigned long mips_gprmask; | |
198 | unsigned long mips_cprmask[4]; | |
199 | ||
200 | /* MIPS ISA we are using for this output file. */ | |
201 | static int file_mips_isa; | |
202 | ||
203 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ | |
204 | static int mips_cpu = -1; | |
205 | ||
206 | /* The argument of the -mabi= flag. */ | |
207 | static char* mips_abi_string = 0; | |
208 | ||
209 | /* Wether we should mark the file EABI64 or EABI32. */ | |
210 | static int mips_eabi64 = 0; | |
211 | ||
212 | /* If they asked for mips1 or mips2 and a cpu that is | |
213 | mips3 or greater, then mark the object file 32BITMODE. */ | |
214 | static int mips_32bitmode = 0; | |
215 | ||
c97ef257 AH |
216 | /* True if -mgp32 was passed. */ |
217 | static int mips_gp32 = 0; | |
218 | ||
9ce8a5dd GRK |
219 | /* Some ISA's have delay slots for instructions which read or write |
220 | from a coprocessor (eg. mips1-mips3); some don't (eg mips4). | |
221 | Return true if instructions marked INSN_LOAD_COPROC_DELAY, | |
222 | INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a | |
223 | delay slot in this ISA. The uses of this macro assume that any | |
224 | ISA that has delay slots for one of these, has them for all. They | |
225 | also assume that ISAs which don't have delays for these insns, don't | |
226 | have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */ | |
227 | #define ISA_HAS_COPROC_DELAYS(ISA) ( \ | |
228 | (ISA) == 1 \ | |
229 | || (ISA) == 2 \ | |
230 | || (ISA) == 3 \ | |
231 | ) | |
232 | ||
233 | /* Return true if ISA supports 64 bit gp register instructions. */ | |
234 | #define ISA_HAS_64BIT_REGS(ISA) ( \ | |
235 | (ISA) == 3 \ | |
236 | || (ISA) == 4 \ | |
237 | ) | |
238 | ||
252b5132 RH |
239 | /* Whether the processor uses hardware interlocks to protect |
240 | reads from the HI and LO registers, and thus does not | |
241 | require nops to be inserted. | |
242 | ||
243 | FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO: | |
244 | -mcpu=FOO schedules for FOO, but still produces code that meets the | |
245 | requirements of MIPS ISA I. For example, it won't generate any | |
246 | FOO-specific instructions, and it will still assume that any | |
247 | scheduling hazards described in MIPS ISA I are there, even if FOO | |
248 | has interlocks. -mFOO gives GCC permission to generate code that | |
249 | will only run on a FOO; it will generate FOO-specific instructions, | |
250 | and assume interlocks provided by a FOO. | |
251 | ||
252 | However, GAS currently doesn't make this distinction; before Jan 28 | |
253 | 1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's | |
254 | assumptions. The GCC driver passes these flags through to GAS, so | |
255 | if GAS actually does anything that doesn't meet MIPS ISA I with | |
256 | -mFOO, then GCC's -mcpu=FOO flag isn't going to work. | |
257 | ||
258 | And furthermore, it did not assume that -mFOO implied -mcpu=FOO, | |
259 | which seems senseless --- why generate code which will only run on | |
260 | a FOO, but schedule for something else? | |
261 | ||
262 | So now, at least, -mcpu=FOO and -mFOO are exactly equivalent. | |
263 | ||
264 | -- Jim Blandy <jimb@cygnus.com> */ | |
265 | ||
266 | #define hilo_interlocks (mips_cpu == 4010 \ | |
267 | ) | |
268 | ||
269 | /* Whether the processor uses hardware interlocks to protect reads | |
270 | from the GPRs, and thus does not require nops to be inserted. */ | |
271 | #define gpr_interlocks \ | |
9ce8a5dd | 272 | (mips_opts.isa != 1 \ |
252b5132 RH |
273 | || mips_cpu == 3900) |
274 | ||
275 | /* As with other "interlocks" this is used by hardware that has FP | |
276 | (co-processor) interlocks. */ | |
277 | /* Itbl support may require additional care here. */ | |
278 | #define cop_interlocks (mips_cpu == 4300 \ | |
279 | ) | |
280 | ||
6b76fefe CM |
281 | /* Is this a mfhi or mflo instruction? */ |
282 | #define MF_HILO_INSN(PINFO) \ | |
283 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
284 | ||
252b5132 RH |
285 | /* MIPS PIC level. */ |
286 | ||
287 | enum mips_pic_level | |
288 | { | |
289 | /* Do not generate PIC code. */ | |
290 | NO_PIC, | |
291 | ||
292 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
293 | not sure what it is supposed to do. */ | |
294 | IRIX4_PIC, | |
295 | ||
296 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
297 | SVR4_PIC, | |
298 | ||
299 | /* Generate PIC code without using a global offset table: the data | |
300 | segment has a maximum size of 64K, all data references are off | |
301 | the $gp register, and all text references are PC relative. This | |
302 | is used on some embedded systems. */ | |
303 | EMBEDDED_PIC | |
304 | }; | |
305 | ||
306 | static enum mips_pic_level mips_pic; | |
307 | ||
308 | /* 1 if we should generate 32 bit offsets from the GP register in | |
309 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
310 | static int mips_big_got; | |
311 | ||
312 | /* 1 if trap instructions should used for overflow rather than break | |
313 | instructions. */ | |
314 | static int mips_trap; | |
315 | ||
119d663a NC |
316 | /* 1 if double width floating point constants should not be constructed |
317 | by a assembling two single width halves into two single width floating | |
318 | point registers which just happen to alias the double width destination | |
319 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 320 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
321 | automatically at assemble time. */ |
322 | static int mips_disable_float_construction; | |
323 | ||
252b5132 RH |
324 | /* Non-zero if any .set noreorder directives were used. */ |
325 | ||
326 | static int mips_any_noreorder; | |
327 | ||
6b76fefe CM |
328 | /* Non-zero if nops should be inserted when the register referenced in |
329 | an mfhi/mflo instruction is read in the next two instructions. */ | |
330 | static int mips_7000_hilo_fix; | |
331 | ||
252b5132 RH |
332 | /* The size of the small data section. */ |
333 | static int g_switch_value = 8; | |
334 | /* Whether the -G option was used. */ | |
335 | static int g_switch_seen = 0; | |
336 | ||
337 | #define N_RMASK 0xc4 | |
338 | #define N_VFP 0xd4 | |
339 | ||
340 | /* If we can determine in advance that GP optimization won't be | |
341 | possible, we can skip the relaxation stuff that tries to produce | |
342 | GP-relative references. This makes delay slot optimization work | |
343 | better. | |
344 | ||
345 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
346 | gcc output. It needs to guess right for gcc, otherwise gcc |
347 | will put what it thinks is a GP-relative instruction in a branch | |
348 | delay slot. | |
252b5132 RH |
349 | |
350 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
351 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
352 | static int nopic_need_relax PARAMS ((symbolS *, int)); | |
353 | ||
354 | /* handle of the OPCODE hash table */ | |
355 | static struct hash_control *op_hash = NULL; | |
356 | ||
357 | /* The opcode hash table we use for the mips16. */ | |
358 | static struct hash_control *mips16_op_hash = NULL; | |
359 | ||
360 | /* This array holds the chars that always start a comment. If the | |
361 | pre-processor is disabled, these aren't very useful */ | |
362 | const char comment_chars[] = "#"; | |
363 | ||
364 | /* This array holds the chars that only start a comment at the beginning of | |
365 | a line. If the line seems to have the form '# 123 filename' | |
366 | .line and .file directives will appear in the pre-processed output */ | |
367 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
368 | first line of the input file. This is because the compiler outputs | |
369 | #NO_APP at the beginning of its output. */ | |
370 | /* Also note that C style comments are always supported. */ | |
371 | const char line_comment_chars[] = "#"; | |
372 | ||
373 | /* This array holds machine specific line separator characters. */ | |
63a0b638 | 374 | const char line_separator_chars[] = ";"; |
252b5132 RH |
375 | |
376 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
377 | const char EXP_CHARS[] = "eE"; | |
378 | ||
379 | /* Chars that mean this number is a floating point constant */ | |
380 | /* As in 0f12.456 */ | |
381 | /* or 0d1.2345e12 */ | |
382 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
383 | ||
384 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
385 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
386 | but nothing is ideal around here. | |
387 | */ | |
388 | ||
389 | static char *insn_error; | |
390 | ||
391 | static int auto_align = 1; | |
392 | ||
393 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
394 | offset in the stack frame from which to restore the $gp register. | |
395 | This is set by the .cprestore pseudo-op, and saved in this | |
396 | variable. */ | |
397 | static offsetT mips_cprestore_offset = -1; | |
398 | ||
399 | /* This is the register which holds the stack frame, as set by the | |
400 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
401 | static int mips_frame_reg = SP; | |
402 | ||
403 | /* To output NOP instructions correctly, we need to keep information | |
404 | about the previous two instructions. */ | |
405 | ||
406 | /* Whether we are optimizing. The default value of 2 means to remove | |
407 | unneeded NOPs and swap branch instructions when possible. A value | |
408 | of 1 means to not swap branches. A value of 0 means to always | |
409 | insert NOPs. */ | |
410 | static int mips_optimize = 2; | |
411 | ||
412 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
413 | equivalent to seeing no -g option at all. */ | |
414 | static int mips_debug = 0; | |
415 | ||
416 | /* The previous instruction. */ | |
417 | static struct mips_cl_insn prev_insn; | |
418 | ||
419 | /* The instruction before prev_insn. */ | |
420 | static struct mips_cl_insn prev_prev_insn; | |
421 | ||
422 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
423 | point the insn_mo field at this dummy integer. */ | |
43841e91 | 424 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
252b5132 RH |
425 | |
426 | /* Non-zero if prev_insn is valid. */ | |
427 | static int prev_insn_valid; | |
428 | ||
429 | /* The frag for the previous instruction. */ | |
430 | static struct frag *prev_insn_frag; | |
431 | ||
432 | /* The offset into prev_insn_frag for the previous instruction. */ | |
433 | static long prev_insn_where; | |
434 | ||
435 | /* The reloc type for the previous instruction, if any. */ | |
436 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
437 | ||
438 | /* The reloc for the previous instruction, if any. */ | |
439 | static fixS *prev_insn_fixp; | |
440 | ||
441 | /* Non-zero if the previous instruction was in a delay slot. */ | |
442 | static int prev_insn_is_delay_slot; | |
443 | ||
444 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
445 | static int prev_insn_unreordered; | |
446 | ||
447 | /* Non-zero if the previous instruction uses an extend opcode (if | |
448 | mips16). */ | |
449 | static int prev_insn_extended; | |
450 | ||
451 | /* Non-zero if the previous previous instruction was in a .set | |
452 | noreorder. */ | |
453 | static int prev_prev_insn_unreordered; | |
454 | ||
455 | /* If this is set, it points to a frag holding nop instructions which | |
456 | were inserted before the start of a noreorder section. If those | |
457 | nops turn out to be unnecessary, the size of the frag can be | |
458 | decreased. */ | |
459 | static fragS *prev_nop_frag; | |
460 | ||
461 | /* The number of nop instructions we created in prev_nop_frag. */ | |
462 | static int prev_nop_frag_holds; | |
463 | ||
464 | /* The number of nop instructions that we know we need in | |
465 | prev_nop_frag. */ | |
466 | static int prev_nop_frag_required; | |
467 | ||
468 | /* The number of instructions we've seen since prev_nop_frag. */ | |
469 | static int prev_nop_frag_since; | |
470 | ||
471 | /* For ECOFF and ELF, relocations against symbols are done in two | |
472 | parts, with a HI relocation and a LO relocation. Each relocation | |
473 | has only 16 bits of space to store an addend. This means that in | |
474 | order for the linker to handle carries correctly, it must be able | |
475 | to locate both the HI and the LO relocation. This means that the | |
476 | relocations must appear in order in the relocation table. | |
477 | ||
478 | In order to implement this, we keep track of each unmatched HI | |
479 | relocation. We then sort them so that they immediately precede the | |
480 | corresponding LO relocation. */ | |
481 | ||
482 | struct mips_hi_fixup | |
483 | { | |
484 | /* Next HI fixup. */ | |
485 | struct mips_hi_fixup *next; | |
486 | /* This fixup. */ | |
487 | fixS *fixp; | |
488 | /* The section this fixup is in. */ | |
489 | segT seg; | |
490 | }; | |
491 | ||
492 | /* The list of unmatched HI relocs. */ | |
493 | ||
494 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
495 | ||
496 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
497 | ||
498 | #define X ILLEGAL_REG | |
499 | static const int mips32_to_16_reg_map[] = | |
500 | { | |
501 | X, X, 2, 3, 4, 5, 6, 7, | |
502 | X, X, X, X, X, X, X, X, | |
503 | 0, 1, X, X, X, X, X, X, | |
504 | X, X, X, X, X, X, X, X | |
505 | }; | |
506 | #undef X | |
507 | ||
508 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
509 | ||
510 | static const int mips16_to_32_reg_map[] = | |
511 | { | |
512 | 16, 17, 2, 3, 4, 5, 6, 7 | |
513 | }; | |
514 | \f | |
515 | /* Since the MIPS does not have multiple forms of PC relative | |
516 | instructions, we do not have to do relaxing as is done on other | |
517 | platforms. However, we do have to handle GP relative addressing | |
518 | correctly, which turns out to be a similar problem. | |
519 | ||
520 | Every macro that refers to a symbol can occur in (at least) two | |
521 | forms, one with GP relative addressing and one without. For | |
522 | example, loading a global variable into a register generally uses | |
523 | a macro instruction like this: | |
524 | lw $4,i | |
525 | If i can be addressed off the GP register (this is true if it is in | |
526 | the .sbss or .sdata section, or if it is known to be smaller than | |
527 | the -G argument) this will generate the following instruction: | |
528 | lw $4,i($gp) | |
529 | This instruction will use a GPREL reloc. If i can not be addressed | |
530 | off the GP register, the following instruction sequence will be used: | |
531 | lui $at,i | |
532 | lw $4,i($at) | |
533 | In this case the first instruction will have a HI16 reloc, and the | |
534 | second reloc will have a LO16 reloc. Both relocs will be against | |
535 | the symbol i. | |
536 | ||
537 | The issue here is that we may not know whether i is GP addressable | |
538 | until after we see the instruction that uses it. Therefore, we | |
539 | want to be able to choose the final instruction sequence only at | |
540 | the end of the assembly. This is similar to the way other | |
541 | platforms choose the size of a PC relative instruction only at the | |
542 | end of assembly. | |
543 | ||
544 | When generating position independent code we do not use GP | |
545 | addressing in quite the same way, but the issue still arises as | |
546 | external symbols and local symbols must be handled differently. | |
547 | ||
548 | We handle these issues by actually generating both possible | |
549 | instruction sequences. The longer one is put in a frag_var with | |
550 | type rs_machine_dependent. We encode what to do with the frag in | |
551 | the subtype field. We encode (1) the number of existing bytes to | |
552 | replace, (2) the number of new bytes to use, (3) the offset from | |
553 | the start of the existing bytes to the first reloc we must generate | |
554 | (that is, the offset is applied from the start of the existing | |
555 | bytes after they are replaced by the new bytes, if any), (4) the | |
556 | offset from the start of the existing bytes to the second reloc, | |
557 | (5) whether a third reloc is needed (the third reloc is always four | |
558 | bytes after the second reloc), and (6) whether to warn if this | |
559 | variant is used (this is sometimes needed if .set nomacro or .set | |
560 | noat is in effect). All these numbers are reasonably small. | |
561 | ||
562 | Generating two instruction sequences must be handled carefully to | |
563 | ensure that delay slots are handled correctly. Fortunately, there | |
564 | are a limited number of cases. When the second instruction | |
565 | sequence is generated, append_insn is directed to maintain the | |
566 | existing delay slot information, so it continues to apply to any | |
567 | code after the second instruction sequence. This means that the | |
568 | second instruction sequence must not impose any requirements not | |
569 | required by the first instruction sequence. | |
570 | ||
571 | These variant frags are then handled in functions called by the | |
572 | machine independent code. md_estimate_size_before_relax returns | |
573 | the final size of the frag. md_convert_frag sets up the final form | |
574 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
575 | one if needed. */ | |
576 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
577 | ((relax_substateT) \ | |
578 | (((old) << 23) \ | |
579 | | ((new) << 16) \ | |
580 | | (((reloc1) + 64) << 9) \ | |
581 | | (((reloc2) + 64) << 2) \ | |
582 | | ((reloc3) ? (1 << 1) : 0) \ | |
583 | | ((warn) ? 1 : 0))) | |
584 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) | |
585 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
586 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) | |
587 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
588 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) | |
589 | #define RELAX_WARN(i) ((i) & 1) | |
590 | ||
591 | /* For mips16 code, we use an entirely different form of relaxation. | |
592 | mips16 supports two versions of most instructions which take | |
593 | immediate values: a small one which takes some small value, and a | |
594 | larger one which takes a 16 bit value. Since branches also follow | |
595 | this pattern, relaxing these values is required. | |
596 | ||
597 | We can assemble both mips16 and normal MIPS code in a single | |
598 | object. Therefore, we need to support this type of relaxation at | |
599 | the same time that we support the relaxation described above. We | |
600 | use the high bit of the subtype field to distinguish these cases. | |
601 | ||
602 | The information we store for this type of relaxation is the | |
603 | argument code found in the opcode file for this relocation, whether | |
604 | the user explicitly requested a small or extended form, and whether | |
605 | the relocation is in a jump or jal delay slot. That tells us the | |
606 | size of the value, and how it should be stored. We also store | |
607 | whether the fragment is considered to be extended or not. We also | |
608 | store whether this is known to be a branch to a different section, | |
609 | whether we have tried to relax this frag yet, and whether we have | |
610 | ever extended a PC relative fragment because of a shift count. */ | |
611 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
612 | (0x80000000 \ | |
613 | | ((type) & 0xff) \ | |
614 | | ((small) ? 0x100 : 0) \ | |
615 | | ((ext) ? 0x200 : 0) \ | |
616 | | ((dslot) ? 0x400 : 0) \ | |
617 | | ((jal_dslot) ? 0x800 : 0)) | |
618 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) | |
619 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
620 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
621 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
622 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
623 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
624 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
625 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
626 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
627 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
628 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
629 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
630 | \f | |
631 | /* Prototypes for static functions. */ | |
632 | ||
633 | #ifdef __STDC__ | |
634 | #define internalError() \ | |
635 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) | |
636 | #else | |
637 | #define internalError() as_fatal (_("MIPS internal Error")); | |
638 | #endif | |
639 | ||
640 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
641 | ||
642 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, | |
643 | unsigned int reg, enum mips_regclass class)); | |
644 | static int reg_needs_delay PARAMS ((int)); | |
645 | static void mips16_mark_labels PARAMS ((void)); | |
646 | static void append_insn PARAMS ((char *place, | |
647 | struct mips_cl_insn * ip, | |
648 | expressionS * p, | |
649 | bfd_reloc_code_real_type r, | |
650 | boolean)); | |
651 | static void mips_no_prev_insn PARAMS ((int)); | |
652 | static void mips_emit_delays PARAMS ((boolean)); | |
653 | #ifdef USE_STDARG | |
654 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, | |
655 | const char *name, const char *fmt, | |
656 | ...)); | |
657 | #else | |
658 | static void macro_build (); | |
659 | #endif | |
660 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, | |
661 | const char *, const char *, | |
662 | va_list)); | |
663 | static void macro_build_lui PARAMS ((char *place, int *counter, | |
664 | expressionS * ep, int regnum)); | |
665 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); | |
666 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, | |
667 | expressionS *)); | |
668 | static void load_register PARAMS ((int *, int, expressionS *, int)); | |
669 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); | |
670 | static void macro PARAMS ((struct mips_cl_insn * ip)); | |
671 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); | |
672 | #ifdef LOSING_COMPILER | |
673 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
674 | #endif | |
675 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); | |
676 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); | |
677 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, | |
678 | boolean, boolean, unsigned long *, | |
679 | boolean *, unsigned short *)); | |
680 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); | |
681 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
682 | static symbolS *get_symbol PARAMS ((void)); | |
683 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); | |
684 | static void s_align PARAMS ((int)); | |
685 | static void s_change_sec PARAMS ((int)); | |
686 | static void s_cons PARAMS ((int)); | |
687 | static void s_float_cons PARAMS ((int)); | |
688 | static void s_mips_globl PARAMS ((int)); | |
689 | static void s_option PARAMS ((int)); | |
690 | static void s_mipsset PARAMS ((int)); | |
691 | static void s_abicalls PARAMS ((int)); | |
692 | static void s_cpload PARAMS ((int)); | |
693 | static void s_cprestore PARAMS ((int)); | |
694 | static void s_gpword PARAMS ((int)); | |
695 | static void s_cpadd PARAMS ((int)); | |
696 | static void s_insn PARAMS ((int)); | |
697 | static void md_obj_begin PARAMS ((void)); | |
698 | static void md_obj_end PARAMS ((void)); | |
699 | static long get_number PARAMS ((void)); | |
700 | static void s_mips_ent PARAMS ((int)); | |
701 | static void s_mips_end PARAMS ((int)); | |
702 | static void s_mips_frame PARAMS ((int)); | |
703 | static void s_mips_mask PARAMS ((int)); | |
704 | static void s_mips_stab PARAMS ((int)); | |
705 | static void s_mips_weakext PARAMS ((int)); | |
706 | static void s_file PARAMS ((int)); | |
707 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); | |
708 | ||
709 | ||
710 | static int validate_mips_insn PARAMS ((const struct mips_opcode *)); | |
711 | \f | |
712 | /* Pseudo-op table. | |
713 | ||
714 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
715 | should be defined here, but are currently unsupported: .alias, | |
716 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
717 | ||
718 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
719 | specific to the type of debugging information being generated, and | |
720 | should be defined by the object format: .aent, .begin, .bend, | |
721 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
722 | .vreg. | |
723 | ||
724 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
725 | not MIPS CPU specific, but are also not specific to the object file | |
726 | format. This file is probably the best place to define them, but | |
727 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
728 | .struct. */ | |
729 | ||
730 | static const pseudo_typeS mips_pseudo_table[] = | |
731 | { | |
732 | /* MIPS specific pseudo-ops. */ | |
733 | {"option", s_option, 0}, | |
734 | {"set", s_mipsset, 0}, | |
735 | {"rdata", s_change_sec, 'r'}, | |
736 | {"sdata", s_change_sec, 's'}, | |
737 | {"livereg", s_ignore, 0}, | |
738 | {"abicalls", s_abicalls, 0}, | |
739 | {"cpload", s_cpload, 0}, | |
740 | {"cprestore", s_cprestore, 0}, | |
741 | {"gpword", s_gpword, 0}, | |
742 | {"cpadd", s_cpadd, 0}, | |
743 | {"insn", s_insn, 0}, | |
744 | ||
745 | /* Relatively generic pseudo-ops that happen to be used on MIPS | |
746 | chips. */ | |
747 | {"asciiz", stringer, 1}, | |
748 | {"bss", s_change_sec, 'b'}, | |
749 | {"err", s_err, 0}, | |
750 | {"half", s_cons, 1}, | |
751 | {"dword", s_cons, 3}, | |
752 | {"weakext", s_mips_weakext, 0}, | |
753 | ||
754 | /* These pseudo-ops are defined in read.c, but must be overridden | |
755 | here for one reason or another. */ | |
756 | {"align", s_align, 0}, | |
757 | {"byte", s_cons, 0}, | |
758 | {"data", s_change_sec, 'd'}, | |
759 | {"double", s_float_cons, 'd'}, | |
760 | {"float", s_float_cons, 'f'}, | |
761 | {"globl", s_mips_globl, 0}, | |
762 | {"global", s_mips_globl, 0}, | |
763 | {"hword", s_cons, 1}, | |
764 | {"int", s_cons, 2}, | |
765 | {"long", s_cons, 2}, | |
766 | {"octa", s_cons, 4}, | |
767 | {"quad", s_cons, 3}, | |
768 | {"short", s_cons, 1}, | |
769 | {"single", s_float_cons, 'f'}, | |
770 | {"stabn", s_mips_stab, 'n'}, | |
771 | {"text", s_change_sec, 't'}, | |
772 | {"word", s_cons, 2}, | |
43841e91 | 773 | { NULL, NULL, 0 }, |
252b5132 RH |
774 | }; |
775 | ||
776 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { | |
777 | /* These pseudo-ops should be defined by the object file format. | |
778 | However, a.out doesn't support them, so we have versions here. */ | |
779 | {"aent", s_mips_ent, 1}, | |
780 | {"bgnb", s_ignore, 0}, | |
781 | {"end", s_mips_end, 0}, | |
782 | {"endb", s_ignore, 0}, | |
783 | {"ent", s_mips_ent, 0}, | |
784 | {"file", s_file, 0}, | |
785 | {"fmask", s_mips_mask, 'F'}, | |
786 | {"frame", s_mips_frame, 0}, | |
787 | {"loc", s_ignore, 0}, | |
788 | {"mask", s_mips_mask, 'R'}, | |
789 | {"verstamp", s_ignore, 0}, | |
43841e91 | 790 | { NULL, NULL, 0 }, |
252b5132 RH |
791 | }; |
792 | ||
793 | extern void pop_insert PARAMS ((const pseudo_typeS *)); | |
794 | ||
795 | void | |
796 | mips_pop_insert () | |
797 | { | |
798 | pop_insert (mips_pseudo_table); | |
799 | if (! ECOFF_DEBUGGING) | |
800 | pop_insert (mips_nonecoff_pseudo_table); | |
801 | } | |
802 | \f | |
803 | /* Symbols labelling the current insn. */ | |
804 | ||
805 | struct insn_label_list | |
806 | { | |
807 | struct insn_label_list *next; | |
808 | symbolS *label; | |
809 | }; | |
810 | ||
811 | static struct insn_label_list *insn_labels; | |
812 | static struct insn_label_list *free_insn_labels; | |
813 | ||
814 | static void mips_clear_insn_labels PARAMS ((void)); | |
815 | ||
816 | static inline void | |
817 | mips_clear_insn_labels () | |
818 | { | |
819 | register struct insn_label_list **pl; | |
820 | ||
821 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
822 | ; | |
823 | *pl = insn_labels; | |
824 | insn_labels = NULL; | |
825 | } | |
826 | \f | |
827 | static char *expr_end; | |
828 | ||
829 | /* Expressions which appear in instructions. These are set by | |
830 | mips_ip. */ | |
831 | ||
832 | static expressionS imm_expr; | |
833 | static expressionS offset_expr; | |
834 | ||
835 | /* Relocs associated with imm_expr and offset_expr. */ | |
836 | ||
837 | static bfd_reloc_code_real_type imm_reloc; | |
838 | static bfd_reloc_code_real_type offset_reloc; | |
839 | ||
840 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ | |
841 | ||
842 | static boolean imm_unmatched_hi; | |
843 | ||
844 | /* These are set by mips16_ip if an explicit extension is used. */ | |
845 | ||
846 | static boolean mips16_small, mips16_ext; | |
847 | ||
848 | #ifdef MIPS_STABS_ELF | |
849 | /* The pdr segment for per procedure frame/regmask info */ | |
850 | ||
851 | static segT pdr_seg; | |
852 | #endif | |
853 | ||
854 | /* | |
855 | * This function is called once, at assembler startup time. It should | |
856 | * set up all the tables, etc. that the MD part of the assembler will need. | |
857 | */ | |
858 | void | |
859 | md_begin () | |
860 | { | |
861 | boolean ok = false; | |
862 | register const char *retval = NULL; | |
863 | register unsigned int i = 0; | |
864 | const char *cpu; | |
865 | char *a = NULL; | |
866 | int broken = 0; | |
867 | int mips_isa_from_cpu; | |
868 | ||
056350c6 NC |
869 | /* GP relative stuff not working for PE */ |
870 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
871 | && g_switch_value != 0) | |
872 | { | |
873 | if (g_switch_seen) | |
874 | as_bad (_("-G not supported in this configuration.")); | |
875 | g_switch_value = 0; | |
876 | } | |
877 | ||
252b5132 RH |
878 | cpu = TARGET_CPU; |
879 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
880 | { | |
881 | a = xmalloc (sizeof TARGET_CPU); | |
882 | strcpy (a, TARGET_CPU); | |
883 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
884 | cpu = a; | |
885 | } | |
886 | ||
887 | if (mips_cpu < 0) | |
888 | { | |
889 | /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is | |
890 | just the generic 'mips', in which case set mips_cpu based | |
891 | on the given ISA, if any. */ | |
892 | ||
893 | if (strcmp (cpu, "mips") == 0) | |
894 | { | |
9ce8a5dd GRK |
895 | if (mips_opts.isa < 0) |
896 | mips_cpu = 3000; | |
252b5132 | 897 | |
9ce8a5dd | 898 | else if (mips_opts.isa == 2) |
252b5132 RH |
899 | mips_cpu = 6000; |
900 | ||
901 | else if (mips_opts.isa == 3) | |
902 | mips_cpu = 4000; | |
903 | ||
904 | else if (mips_opts.isa == 4) | |
905 | mips_cpu = 8000; | |
906 | ||
907 | else | |
908 | mips_cpu = 3000; | |
909 | } | |
910 | ||
911 | else if (strcmp (cpu, "r3900") == 0 | |
912 | || strcmp (cpu, "mipstx39") == 0 | |
913 | ) | |
914 | mips_cpu = 3900; | |
915 | ||
916 | else if (strcmp (cpu, "r6000") == 0 | |
917 | || strcmp (cpu, "mips2") == 0) | |
918 | mips_cpu = 6000; | |
919 | ||
920 | else if (strcmp (cpu, "mips64") == 0 | |
921 | || strcmp (cpu, "r4000") == 0 | |
922 | || strcmp (cpu, "mips3") == 0) | |
923 | mips_cpu = 4000; | |
924 | ||
925 | else if (strcmp (cpu, "r4400") == 0) | |
926 | mips_cpu = 4400; | |
927 | ||
928 | else if (strcmp (cpu, "mips64orion") == 0 | |
929 | || strcmp (cpu, "r4600") == 0) | |
930 | mips_cpu = 4600; | |
931 | ||
932 | else if (strcmp (cpu, "r4650") == 0) | |
933 | mips_cpu = 4650; | |
934 | ||
935 | else if (strcmp (cpu, "mips64vr4300") == 0) | |
936 | mips_cpu = 4300; | |
937 | ||
938 | else if (strcmp (cpu, "mips64vr4111") == 0) | |
939 | mips_cpu = 4111; | |
940 | ||
941 | else if (strcmp (cpu, "mips64vr4100") == 0) | |
942 | mips_cpu = 4100; | |
943 | ||
944 | else if (strcmp (cpu, "r4010") == 0) | |
945 | mips_cpu = 4010; | |
946 | ||
947 | ||
948 | else if (strcmp (cpu, "r5000") == 0 | |
949 | || strcmp (cpu, "mips64vr5000") == 0) | |
950 | mips_cpu = 5000; | |
951 | ||
952 | ||
953 | ||
954 | else if (strcmp (cpu, "r8000") == 0 | |
955 | || strcmp (cpu, "mips4") == 0) | |
956 | mips_cpu = 8000; | |
957 | ||
958 | else if (strcmp (cpu, "r10000") == 0) | |
959 | mips_cpu = 10000; | |
960 | ||
961 | else if (strcmp (cpu, "mips16") == 0) | |
962 | mips_cpu = 0; /* FIXME */ | |
963 | ||
964 | else | |
965 | mips_cpu = 3000; | |
966 | } | |
967 | ||
968 | if (mips_cpu == 3000 | |
969 | || mips_cpu == 3900) | |
970 | mips_isa_from_cpu = 1; | |
971 | ||
972 | else if (mips_cpu == 6000 | |
973 | || mips_cpu == 4010) | |
974 | mips_isa_from_cpu = 2; | |
975 | ||
976 | else if (mips_cpu == 4000 | |
977 | || mips_cpu == 4100 | |
978 | || mips_cpu == 4111 | |
979 | || mips_cpu == 4400 | |
980 | || mips_cpu == 4300 | |
981 | || mips_cpu == 4600 | |
982 | || mips_cpu == 4650) | |
983 | mips_isa_from_cpu = 3; | |
984 | ||
985 | else if (mips_cpu == 5000 | |
986 | || mips_cpu == 8000 | |
987 | || mips_cpu == 10000) | |
988 | mips_isa_from_cpu = 4; | |
989 | ||
990 | else | |
991 | mips_isa_from_cpu = -1; | |
992 | ||
993 | if (mips_opts.isa == -1) | |
994 | { | |
995 | if (mips_isa_from_cpu != -1) | |
996 | mips_opts.isa = mips_isa_from_cpu; | |
997 | else | |
998 | mips_opts.isa = 1; | |
999 | } | |
1000 | ||
1001 | if (mips_opts.mips16 < 0) | |
1002 | { | |
1003 | if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) | |
1004 | mips_opts.mips16 = 1; | |
1005 | else | |
1006 | mips_opts.mips16 = 0; | |
1007 | } | |
1008 | ||
1009 | /* End of TARGET_CPU processing, get rid of malloced memory | |
1010 | if necessary. */ | |
1011 | cpu = NULL; | |
1012 | if (a != NULL) | |
1013 | { | |
1014 | free (a); | |
1015 | a = NULL; | |
1016 | } | |
1017 | ||
9ce8a5dd | 1018 | if (mips_opts.isa == 1 && mips_trap) |
252b5132 RH |
1019 | as_bad (_("trap exception not supported at ISA 1")); |
1020 | ||
1021 | /* Set the EABI kind based on the ISA before the user gets | |
1022 | to change the ISA with directives. This isn't really | |
1023 | the best, but then neither is basing the abi on the isa. */ | |
9ce8a5dd | 1024 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 RH |
1025 | && mips_abi_string |
1026 | && 0 == strcmp (mips_abi_string,"eabi")) | |
1027 | mips_eabi64 = 1; | |
1028 | ||
1029 | if (mips_cpu != 0 && mips_cpu != -1) | |
1030 | { | |
1031 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_cpu); | |
9ce8a5dd | 1032 | |
252b5132 RH |
1033 | /* If they asked for mips1 or mips2 and a cpu that is |
1034 | mips3 or greater, then mark the object file 32BITMODE. */ | |
1035 | if (mips_isa_from_cpu != -1 | |
9ce8a5dd GRK |
1036 | && ! ISA_HAS_64BIT_REGS (mips_opts.isa) |
1037 | && ISA_HAS_64BIT_REGS (mips_isa_from_cpu)) | |
252b5132 RH |
1038 | mips_32bitmode = 1; |
1039 | } | |
1040 | else | |
1041 | { | |
1042 | switch (mips_opts.isa) | |
1043 | { | |
1044 | case 1: | |
1045 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
1046 | break; | |
1047 | case 2: | |
1048 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
1049 | break; | |
1050 | case 3: | |
1051 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
1052 | break; | |
1053 | case 4: | |
1054 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
1055 | break; | |
1056 | } | |
1057 | } | |
1058 | ||
1059 | if (! ok) | |
1060 | as_warn (_("Could not set architecture and machine")); | |
1061 | ||
1062 | file_mips_isa = mips_opts.isa; | |
1063 | ||
1064 | op_hash = hash_new (); | |
1065 | ||
1066 | for (i = 0; i < NUMOPCODES;) | |
1067 | { | |
1068 | const char *name = mips_opcodes[i].name; | |
1069 | ||
1070 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); | |
1071 | if (retval != NULL) | |
1072 | { | |
1073 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1074 | mips_opcodes[i].name, retval); | |
1075 | /* Probably a memory allocation problem? Give up now. */ | |
1076 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1077 | } | |
1078 | do | |
1079 | { | |
1080 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1081 | { | |
1082 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1083 | broken = 1; | |
1084 | } | |
1085 | ++i; | |
1086 | } | |
1087 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1088 | } | |
1089 | ||
1090 | mips16_op_hash = hash_new (); | |
1091 | ||
1092 | i = 0; | |
1093 | while (i < bfd_mips16_num_opcodes) | |
1094 | { | |
1095 | const char *name = mips16_opcodes[i].name; | |
1096 | ||
1097 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1098 | if (retval != NULL) | |
1099 | as_fatal (_("internal: can't hash `%s': %s"), | |
1100 | mips16_opcodes[i].name, retval); | |
1101 | do | |
1102 | { | |
1103 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1104 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1105 | != mips16_opcodes[i].match)) | |
1106 | { | |
1107 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1108 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1109 | broken = 1; | |
1110 | } | |
1111 | ++i; | |
1112 | } | |
1113 | while (i < bfd_mips16_num_opcodes | |
1114 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1115 | } | |
1116 | ||
1117 | if (broken) | |
1118 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1119 | ||
1120 | /* We add all the general register names to the symbol table. This | |
1121 | helps us detect invalid uses of them. */ | |
1122 | for (i = 0; i < 32; i++) | |
1123 | { | |
1124 | char buf[5]; | |
1125 | ||
1126 | sprintf (buf, "$%d", i); | |
1127 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1128 | &zero_address_frag)); | |
1129 | } | |
1130 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
1131 | &zero_address_frag)); | |
1132 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1133 | &zero_address_frag)); | |
1134 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1135 | &zero_address_frag)); | |
1136 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1137 | &zero_address_frag)); | |
1138 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1139 | &zero_address_frag)); | |
1140 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1141 | &zero_address_frag)); | |
1142 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
1143 | &zero_address_frag)); | |
1144 | ||
1145 | mips_no_prev_insn (false); | |
1146 | ||
1147 | mips_gprmask = 0; | |
1148 | mips_cprmask[0] = 0; | |
1149 | mips_cprmask[1] = 0; | |
1150 | mips_cprmask[2] = 0; | |
1151 | mips_cprmask[3] = 0; | |
1152 | ||
1153 | /* set the default alignment for the text section (2**2) */ | |
1154 | record_alignment (text_section, 2); | |
1155 | ||
1156 | if (USE_GLOBAL_POINTER_OPT) | |
1157 | bfd_set_gp_size (stdoutput, g_switch_value); | |
1158 | ||
1159 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1160 | { | |
1161 | /* On a native system, sections must be aligned to 16 byte | |
1162 | boundaries. When configured for an embedded ELF target, we | |
1163 | don't bother. */ | |
1164 | if (strcmp (TARGET_OS, "elf") != 0) | |
1165 | { | |
1166 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1167 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1168 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1169 | } | |
1170 | ||
1171 | /* Create a .reginfo section for register masks and a .mdebug | |
1172 | section for debugging information. */ | |
1173 | { | |
1174 | segT seg; | |
1175 | subsegT subseg; | |
1176 | flagword flags; | |
1177 | segT sec; | |
1178 | ||
1179 | seg = now_seg; | |
1180 | subseg = now_subseg; | |
1181 | ||
1182 | /* The ABI says this section should be loaded so that the | |
1183 | running program can access it. However, we don't load it | |
1184 | if we are configured for an embedded target */ | |
1185 | flags = SEC_READONLY | SEC_DATA; | |
1186 | if (strcmp (TARGET_OS, "elf") != 0) | |
1187 | flags |= SEC_ALLOC | SEC_LOAD; | |
1188 | ||
1189 | if (! mips_64) | |
1190 | { | |
1191 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1192 | ||
1193 | ||
1194 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
1195 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1196 | ||
1197 | #ifdef OBJ_ELF | |
1198 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1199 | #endif | |
1200 | } | |
1201 | else | |
1202 | { | |
1203 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1204 | .reginfo section. */ | |
1205 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
1206 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
1207 | (void) bfd_set_section_alignment (stdoutput, sec, 3); | |
1208 | ||
1209 | #ifdef OBJ_ELF | |
1210 | /* Set up the option header. */ | |
1211 | { | |
1212 | Elf_Internal_Options opthdr; | |
1213 | char *f; | |
1214 | ||
1215 | opthdr.kind = ODK_REGINFO; | |
1216 | opthdr.size = (sizeof (Elf_External_Options) | |
1217 | + sizeof (Elf64_External_RegInfo)); | |
1218 | opthdr.section = 0; | |
1219 | opthdr.info = 0; | |
1220 | f = frag_more (sizeof (Elf_External_Options)); | |
1221 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1222 | (Elf_External_Options *) f); | |
1223 | ||
1224 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1225 | } | |
1226 | #endif | |
1227 | } | |
1228 | ||
1229 | if (ECOFF_DEBUGGING) | |
1230 | { | |
1231 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1232 | (void) bfd_set_section_flags (stdoutput, sec, | |
1233 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1234 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1235 | } | |
1236 | ||
1237 | #ifdef MIPS_STABS_ELF | |
1238 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1239 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1240 | SEC_READONLY | SEC_RELOC | SEC_DEBUGGING); | |
1241 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1242 | #endif | |
1243 | ||
1244 | subseg_set (seg, subseg); | |
1245 | } | |
1246 | } | |
1247 | ||
1248 | if (! ECOFF_DEBUGGING) | |
1249 | md_obj_begin (); | |
1250 | } | |
1251 | ||
1252 | void | |
1253 | md_mips_end () | |
1254 | { | |
1255 | if (! ECOFF_DEBUGGING) | |
1256 | md_obj_end (); | |
1257 | } | |
1258 | ||
1259 | void | |
1260 | md_assemble (str) | |
1261 | char *str; | |
1262 | { | |
1263 | struct mips_cl_insn insn; | |
1264 | ||
1265 | imm_expr.X_op = O_absent; | |
1266 | imm_reloc = BFD_RELOC_UNUSED; | |
1267 | imm_unmatched_hi = false; | |
1268 | offset_expr.X_op = O_absent; | |
1269 | offset_reloc = BFD_RELOC_UNUSED; | |
1270 | ||
1271 | if (mips_opts.mips16) | |
1272 | mips16_ip (str, &insn); | |
1273 | else | |
1274 | { | |
1275 | mips_ip (str, &insn); | |
1276 | DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), | |
1277 | str, insn.insn_opcode)); | |
1278 | } | |
1279 | ||
1280 | if (insn_error) | |
1281 | { | |
1282 | as_bad ("%s `%s'", insn_error, str); | |
1283 | return; | |
1284 | } | |
1285 | ||
1286 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1287 | { | |
1288 | if (mips_opts.mips16) | |
1289 | mips16_macro (&insn); | |
1290 | else | |
1291 | macro (&insn); | |
1292 | } | |
1293 | else | |
1294 | { | |
1295 | if (imm_expr.X_op != O_absent) | |
1296 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, | |
1297 | imm_unmatched_hi); | |
1298 | else if (offset_expr.X_op != O_absent) | |
1299 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); | |
1300 | else | |
1301 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); | |
1302 | } | |
1303 | } | |
1304 | ||
1305 | /* See whether instruction IP reads register REG. CLASS is the type | |
1306 | of register. */ | |
1307 | ||
1308 | static int | |
1309 | insn_uses_reg (ip, reg, class) | |
1310 | struct mips_cl_insn *ip; | |
1311 | unsigned int reg; | |
1312 | enum mips_regclass class; | |
1313 | { | |
1314 | if (class == MIPS16_REG) | |
1315 | { | |
1316 | assert (mips_opts.mips16); | |
1317 | reg = mips16_to_32_reg_map[reg]; | |
1318 | class = MIPS_GR_REG; | |
1319 | } | |
1320 | ||
1321 | /* Don't report on general register 0, since it never changes. */ | |
1322 | if (class == MIPS_GR_REG && reg == 0) | |
1323 | return 0; | |
1324 | ||
1325 | if (class == MIPS_FP_REG) | |
1326 | { | |
1327 | assert (! mips_opts.mips16); | |
1328 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1329 | This is not optimal, because it will introduce an unnecessary | |
1330 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1331 | need to distinguish reading both $f0 and $f1 or just one of | |
1332 | them. Note that we don't have to check the other way, | |
1333 | because there is no instruction that sets both $f0 and $f1 | |
1334 | and requires a delay. */ | |
1335 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1336 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1337 | == (reg &~ (unsigned) 1))) | |
1338 | return 1; | |
1339 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1340 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1341 | == (reg &~ (unsigned) 1))) | |
1342 | return 1; | |
1343 | } | |
1344 | else if (! mips_opts.mips16) | |
1345 | { | |
1346 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1347 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1348 | return 1; | |
1349 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1350 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1351 | return 1; | |
1352 | } | |
1353 | else | |
1354 | { | |
1355 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1356 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1357 | & MIPS16OP_MASK_RX)] | |
1358 | == reg)) | |
1359 | return 1; | |
1360 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1361 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1362 | & MIPS16OP_MASK_RY)] | |
1363 | == reg)) | |
1364 | return 1; | |
1365 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1366 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1367 | & MIPS16OP_MASK_MOVE32Z)] | |
1368 | == reg)) | |
1369 | return 1; | |
1370 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1371 | return 1; | |
1372 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1373 | return 1; | |
1374 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1375 | return 1; | |
1376 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1377 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1378 | & MIPS16OP_MASK_REGR32) == reg) | |
1379 | return 1; | |
1380 | } | |
1381 | ||
1382 | return 0; | |
1383 | } | |
1384 | ||
1385 | /* This function returns true if modifying a register requires a | |
1386 | delay. */ | |
1387 | ||
1388 | static int | |
1389 | reg_needs_delay (reg) | |
1390 | int reg; | |
1391 | { | |
1392 | unsigned long prev_pinfo; | |
1393 | ||
1394 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1395 | if (! mips_opts.noreorder | |
9ce8a5dd | 1396 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1397 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1398 | || (! gpr_interlocks | |
1399 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1400 | { | |
1401 | /* A load from a coprocessor or from memory. All load | |
1402 | delays delay the use of general register rt for one | |
1403 | instruction on the r3000. The r6000 and r4000 use | |
1404 | interlocks. */ | |
1405 | /* Itbl support may require additional care here. */ | |
1406 | know (prev_pinfo & INSN_WRITE_GPR_T); | |
1407 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1408 | return 1; | |
1409 | } | |
1410 | ||
1411 | return 0; | |
1412 | } | |
1413 | ||
1414 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1415 | handle them specially, such as generating jalx instructions when | |
1416 | needed. We also make them odd for the duration of the assembly, in | |
1417 | order to generate the right sort of code. We will make them even | |
1418 | in the adjust_symtab routine, while leaving them marked. This is | |
1419 | convenient for the debugger and the disassembler. The linker knows | |
1420 | to make them odd again. */ | |
1421 | ||
1422 | static void | |
1423 | mips16_mark_labels () | |
1424 | { | |
1425 | if (mips_opts.mips16) | |
1426 | { | |
1427 | struct insn_label_list *l; | |
1428 | ||
1429 | for (l = insn_labels; l != NULL; l = l->next) | |
1430 | { | |
1431 | #ifdef OBJ_ELF | |
1432 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1433 | S_SET_OTHER (l->label, STO_MIPS16); | |
1434 | #endif | |
49309057 ILT |
1435 | if ((S_GET_VALUE (l->label) & 1) == 0) |
1436 | S_SET_VALUE (l->label, S_GET_VALUE (l->label) + 1); | |
252b5132 RH |
1437 | } |
1438 | } | |
1439 | } | |
1440 | ||
1441 | /* Output an instruction. PLACE is where to put the instruction; if | |
1442 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1443 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1444 | used with RELOC_TYPE. */ | |
1445 | ||
1446 | static void | |
1447 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) | |
1448 | char *place; | |
1449 | struct mips_cl_insn *ip; | |
1450 | expressionS *address_expr; | |
1451 | bfd_reloc_code_real_type reloc_type; | |
1452 | boolean unmatched_hi; | |
1453 | { | |
1454 | register unsigned long prev_pinfo, pinfo; | |
1455 | char *f; | |
1456 | fixS *fixp; | |
1457 | int nops = 0; | |
1458 | ||
1459 | /* Mark instruction labels in mips16 mode. */ | |
1460 | if (mips_opts.mips16) | |
1461 | mips16_mark_labels (); | |
1462 | ||
1463 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1464 | pinfo = ip->insn_mo->pinfo; | |
1465 | ||
1466 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) | |
1467 | { | |
1468 | int prev_prev_nop; | |
1469 | ||
1470 | /* If the previous insn required any delay slots, see if we need | |
1471 | to insert a NOP or two. There are eight kinds of possible | |
1472 | hazards, of which an instruction can have at most one type. | |
1473 | (1) a load from memory delay | |
1474 | (2) a load from a coprocessor delay | |
1475 | (3) an unconditional branch delay | |
1476 | (4) a conditional branch delay | |
1477 | (5) a move to coprocessor register delay | |
1478 | (6) a load coprocessor register from memory delay | |
1479 | (7) a coprocessor condition code delay | |
1480 | (8) a HI/LO special register delay | |
1481 | ||
1482 | There are a lot of optimizations we could do that we don't. | |
1483 | In particular, we do not, in general, reorder instructions. | |
1484 | If you use gcc with optimization, it will reorder | |
1485 | instructions and generally do much more optimization then we | |
1486 | do here; repeating all that work in the assembler would only | |
1487 | benefit hand written assembly code, and does not seem worth | |
1488 | it. */ | |
1489 | ||
1490 | /* This is how a NOP is emitted. */ | |
1491 | #define emit_nop() \ | |
1492 | (mips_opts.mips16 \ | |
1493 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1494 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1495 | ||
1496 | /* The previous insn might require a delay slot, depending upon | |
1497 | the contents of the current insn. */ | |
1498 | if (! mips_opts.mips16 | |
9ce8a5dd | 1499 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1500 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1501 | && ! cop_interlocks) | |
1502 | || (! gpr_interlocks | |
1503 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1504 | { | |
1505 | /* A load from a coprocessor or from memory. All load | |
1506 | delays delay the use of general register rt for one | |
1507 | instruction on the r3000. The r6000 and r4000 use | |
1508 | interlocks. */ | |
1509 | /* Itbl support may require additional care here. */ | |
1510 | know (prev_pinfo & INSN_WRITE_GPR_T); | |
1511 | if (mips_optimize == 0 | |
1512 | || insn_uses_reg (ip, | |
1513 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1514 | & OP_MASK_RT), | |
1515 | MIPS_GR_REG)) | |
1516 | ++nops; | |
1517 | } | |
1518 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1519 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1520 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
1521 | && ! cop_interlocks) | |
9ce8a5dd | 1522 | || (mips_opts.isa == 1 |
252b5132 RH |
1523 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
1524 | { | |
1525 | /* A generic coprocessor delay. The previous instruction | |
1526 | modified a coprocessor general or control register. If | |
1527 | it modified a control register, we need to avoid any | |
1528 | coprocessor instruction (this is probably not always | |
1529 | required, but it sometimes is). If it modified a general | |
1530 | register, we avoid using that register. | |
1531 | ||
1532 | On the r6000 and r4000 loading a coprocessor register | |
1533 | from memory is interlocked, and does not require a delay. | |
1534 | ||
1535 | This case is not handled very well. There is no special | |
1536 | knowledge of CP0 handling, and the coprocessors other | |
1537 | than the floating point unit are not distinguished at | |
1538 | all. */ | |
1539 | /* Itbl support may require additional care here. FIXME! | |
1540 | Need to modify this to include knowledge about | |
1541 | user specified delays! */ | |
1542 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1543 | { | |
1544 | if (mips_optimize == 0 | |
1545 | || insn_uses_reg (ip, | |
1546 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1547 | & OP_MASK_FT), | |
1548 | MIPS_FP_REG)) | |
1549 | ++nops; | |
1550 | } | |
1551 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1552 | { | |
1553 | if (mips_optimize == 0 | |
1554 | || insn_uses_reg (ip, | |
1555 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1556 | & OP_MASK_FS), | |
1557 | MIPS_FP_REG)) | |
1558 | ++nops; | |
1559 | } | |
1560 | else | |
1561 | { | |
1562 | /* We don't know exactly what the previous instruction | |
1563 | does. If the current instruction uses a coprocessor | |
1564 | register, we must insert a NOP. If previous | |
1565 | instruction may set the condition codes, and the | |
1566 | current instruction uses them, we must insert two | |
1567 | NOPS. */ | |
1568 | /* Itbl support may require additional care here. */ | |
1569 | if (mips_optimize == 0 | |
1570 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1571 | && (pinfo & INSN_READ_COND_CODE))) | |
1572 | nops += 2; | |
1573 | else if (pinfo & INSN_COP) | |
1574 | ++nops; | |
1575 | } | |
1576 | } | |
1577 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1578 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1579 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1580 | && ! cop_interlocks) | |
1581 | { | |
1582 | /* The previous instruction sets the coprocessor condition | |
1583 | codes, but does not require a general coprocessor delay | |
1584 | (this means it is a floating point comparison | |
1585 | instruction). If this instruction uses the condition | |
1586 | codes, we need to insert a single NOP. */ | |
1587 | /* Itbl support may require additional care here. */ | |
1588 | if (mips_optimize == 0 | |
1589 | || (pinfo & INSN_READ_COND_CODE)) | |
1590 | ++nops; | |
1591 | } | |
6b76fefe CM |
1592 | |
1593 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1594 | previous insn was an mfhi/mflo and the current insn | |
1595 | reads the register that the mfhi/mflo wrote to, then | |
1596 | insert two nops. */ | |
1597 | ||
1598 | else if (mips_7000_hilo_fix | |
1599 | && MF_HILO_INSN (prev_pinfo) | |
1600 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
1601 | & OP_MASK_RD), | |
1602 | MIPS_GR_REG)) | |
1603 | ||
1604 | { | |
1605 | nops += 2; | |
1606 | } | |
1607 | ||
1608 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1609 | 2nd previous insn was an mfhi/mflo and the current insn | |
1610 | reads the register that the mfhi/mflo wrote to, then | |
1611 | insert one nop. */ | |
1612 | ||
1613 | else if (mips_7000_hilo_fix | |
1614 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1615 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1616 | & OP_MASK_RD), | |
1617 | MIPS_GR_REG)) | |
1618 | ||
1619 | { | |
1620 | nops += 1; | |
1621 | } | |
1622 | ||
252b5132 RH |
1623 | else if (prev_pinfo & INSN_READ_LO) |
1624 | { | |
1625 | /* The previous instruction reads the LO register; if the | |
1626 | current instruction writes to the LO register, we must | |
1627 | insert two NOPS. Some newer processors have interlocks. | |
1628 | Also the tx39's multiply instructions can be exectuted | |
1629 | immediatly after a read from HI/LO (without the delay), | |
1630 | though the tx39's divide insns still do require the | |
1631 | delay. */ | |
1632 | if (! (hilo_interlocks | |
1633 | || (mips_cpu == 3900 && (pinfo & INSN_MULT))) | |
1634 | && (mips_optimize == 0 | |
1635 | || (pinfo & INSN_WRITE_LO))) | |
1636 | nops += 2; | |
1637 | /* Most mips16 branch insns don't have a delay slot. | |
1638 | If a read from LO is immediately followed by a branch | |
1639 | to a write to LO we have a read followed by a write | |
1640 | less than 2 insns away. We assume the target of | |
1641 | a branch might be a write to LO, and insert a nop | |
1642 | between a read and an immediately following branch. */ | |
1643 | else if (mips_opts.mips16 | |
1644 | && (mips_optimize == 0 | |
1645 | || (pinfo & MIPS16_INSN_BRANCH))) | |
1646 | nops += 1; | |
1647 | } | |
1648 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1649 | { | |
1650 | /* The previous instruction reads the HI register; if the | |
1651 | current instruction writes to the HI register, we must | |
1652 | insert a NOP. Some newer processors have interlocks. | |
1653 | Also the note tx39's multiply above. */ | |
1654 | if (! (hilo_interlocks | |
1655 | || (mips_cpu == 3900 && (pinfo & INSN_MULT))) | |
1656 | && (mips_optimize == 0 | |
1657 | || (pinfo & INSN_WRITE_HI))) | |
1658 | nops += 2; | |
1659 | /* Most mips16 branch insns don't have a delay slot. | |
1660 | If a read from HI is immediately followed by a branch | |
1661 | to a write to HI we have a read followed by a write | |
1662 | less than 2 insns away. We assume the target of | |
1663 | a branch might be a write to HI, and insert a nop | |
1664 | between a read and an immediately following branch. */ | |
1665 | else if (mips_opts.mips16 | |
1666 | && (mips_optimize == 0 | |
1667 | || (pinfo & MIPS16_INSN_BRANCH))) | |
1668 | nops += 1; | |
1669 | } | |
1670 | ||
1671 | /* If the previous instruction was in a noreorder section, then | |
1672 | we don't want to insert the nop after all. */ | |
1673 | /* Itbl support may require additional care here. */ | |
1674 | if (prev_insn_unreordered) | |
1675 | nops = 0; | |
1676 | ||
1677 | /* There are two cases which require two intervening | |
1678 | instructions: 1) setting the condition codes using a move to | |
1679 | coprocessor instruction which requires a general coprocessor | |
1680 | delay and then reading the condition codes 2) reading the HI | |
1681 | or LO register and then writing to it (except on processors | |
1682 | which have interlocks). If we are not already emitting a NOP | |
1683 | instruction, we must check for these cases compared to the | |
1684 | instruction previous to the previous instruction. */ | |
1685 | if ((! mips_opts.mips16 | |
9ce8a5dd | 1686 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1687 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1688 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1689 | && (pinfo & INSN_READ_COND_CODE) | |
1690 | && ! cop_interlocks) | |
1691 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1692 | && (pinfo & INSN_WRITE_LO) | |
1693 | && ! (hilo_interlocks | |
1694 | || (mips_cpu == 3900 && (pinfo & INSN_MULT)))) | |
1695 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1696 | && (pinfo & INSN_WRITE_HI) | |
1697 | && ! (hilo_interlocks | |
1698 | || (mips_cpu == 3900 && (pinfo & INSN_MULT))))) | |
1699 | prev_prev_nop = 1; | |
1700 | else | |
1701 | prev_prev_nop = 0; | |
1702 | ||
1703 | if (prev_prev_insn_unreordered) | |
1704 | prev_prev_nop = 0; | |
1705 | ||
1706 | if (prev_prev_nop && nops == 0) | |
1707 | ++nops; | |
1708 | ||
1709 | /* If we are being given a nop instruction, don't bother with | |
1710 | one of the nops we would otherwise output. This will only | |
1711 | happen when a nop instruction is used with mips_optimize set | |
1712 | to 0. */ | |
1713 | if (nops > 0 | |
1714 | && ! mips_opts.noreorder | |
1715 | && ip->insn_opcode == (mips_opts.mips16 ? 0x6500 : 0)) | |
1716 | --nops; | |
1717 | ||
1718 | /* Now emit the right number of NOP instructions. */ | |
1719 | if (nops > 0 && ! mips_opts.noreorder) | |
1720 | { | |
1721 | fragS *old_frag; | |
1722 | unsigned long old_frag_offset; | |
1723 | int i; | |
1724 | struct insn_label_list *l; | |
1725 | ||
1726 | old_frag = frag_now; | |
1727 | old_frag_offset = frag_now_fix (); | |
1728 | ||
1729 | for (i = 0; i < nops; i++) | |
1730 | emit_nop (); | |
1731 | ||
1732 | if (listing) | |
1733 | { | |
1734 | listing_prev_line (); | |
1735 | /* We may be at the start of a variant frag. In case we | |
1736 | are, make sure there is enough space for the frag | |
1737 | after the frags created by listing_prev_line. The | |
1738 | argument to frag_grow here must be at least as large | |
1739 | as the argument to all other calls to frag_grow in | |
1740 | this file. We don't have to worry about being in the | |
1741 | middle of a variant frag, because the variants insert | |
1742 | all needed nop instructions themselves. */ | |
1743 | frag_grow (40); | |
1744 | } | |
1745 | ||
1746 | for (l = insn_labels; l != NULL; l = l->next) | |
1747 | { | |
1748 | assert (S_GET_SEGMENT (l->label) == now_seg); | |
49309057 | 1749 | symbol_set_frag (l->label, frag_now); |
252b5132 RH |
1750 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); |
1751 | /* mips16 text labels are stored as odd. */ | |
1752 | if (mips_opts.mips16) | |
49309057 | 1753 | S_SET_VALUE (l->label, S_GET_VALUE (l->label) + 1); |
252b5132 RH |
1754 | } |
1755 | ||
1756 | #ifndef NO_ECOFF_DEBUGGING | |
1757 | if (ECOFF_DEBUGGING) | |
1758 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1759 | #endif | |
1760 | } | |
1761 | else if (prev_nop_frag != NULL) | |
1762 | { | |
1763 | /* We have a frag holding nops we may be able to remove. If | |
1764 | we don't need any nops, we can decrease the size of | |
1765 | prev_nop_frag by the size of one instruction. If we do | |
1766 | need some nops, we count them in prev_nops_required. */ | |
1767 | if (prev_nop_frag_since == 0) | |
1768 | { | |
1769 | if (nops == 0) | |
1770 | { | |
1771 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1772 | --prev_nop_frag_holds; | |
1773 | } | |
1774 | else | |
1775 | prev_nop_frag_required += nops; | |
1776 | } | |
1777 | else | |
1778 | { | |
1779 | if (prev_prev_nop == 0) | |
1780 | { | |
1781 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1782 | --prev_nop_frag_holds; | |
1783 | } | |
1784 | else | |
1785 | ++prev_nop_frag_required; | |
1786 | } | |
1787 | ||
1788 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1789 | prev_nop_frag = NULL; | |
1790 | ||
1791 | ++prev_nop_frag_since; | |
1792 | ||
1793 | /* Sanity check: by the time we reach the second instruction | |
1794 | after prev_nop_frag, we should have used up all the nops | |
1795 | one way or another. */ | |
1796 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1797 | } | |
1798 | } | |
1799 | ||
1800 | if (reloc_type > BFD_RELOC_UNUSED) | |
1801 | { | |
1802 | /* We need to set up a variant frag. */ | |
1803 | assert (mips_opts.mips16 && address_expr != NULL); | |
1804 | f = frag_var (rs_machine_dependent, 4, 0, | |
1805 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, | |
1806 | mips16_small, mips16_ext, | |
1807 | (prev_pinfo | |
1808 | & INSN_UNCOND_BRANCH_DELAY), | |
1809 | (prev_insn_reloc_type | |
1810 | == BFD_RELOC_MIPS16_JMP)), | |
1811 | make_expr_symbol (address_expr), (offsetT) 0, | |
1812 | (char *) NULL); | |
1813 | } | |
1814 | else if (place != NULL) | |
1815 | f = place; | |
1816 | else if (mips_opts.mips16 | |
1817 | && ! ip->use_extend | |
1818 | && reloc_type != BFD_RELOC_MIPS16_JMP) | |
1819 | { | |
1820 | /* Make sure there is enough room to swap this instruction with | |
1821 | a following jump instruction. */ | |
1822 | frag_grow (6); | |
1823 | f = frag_more (2); | |
1824 | } | |
1825 | else | |
1826 | { | |
1827 | if (mips_opts.mips16 | |
1828 | && mips_opts.noreorder | |
1829 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
1830 | as_warn (_("extended instruction in delay slot")); | |
1831 | ||
1832 | f = frag_more (4); | |
1833 | } | |
1834 | ||
1835 | fixp = NULL; | |
1836 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) | |
1837 | { | |
1838 | if (address_expr->X_op == O_constant) | |
1839 | { | |
1840 | switch (reloc_type) | |
1841 | { | |
1842 | case BFD_RELOC_32: | |
1843 | ip->insn_opcode |= address_expr->X_add_number; | |
1844 | break; | |
1845 | ||
1846 | case BFD_RELOC_LO16: | |
1847 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; | |
1848 | break; | |
1849 | ||
1850 | case BFD_RELOC_MIPS_JMP: | |
1851 | if ((address_expr->X_add_number & 3) != 0) | |
1852 | as_bad (_("jump to misaligned address (0x%lx)"), | |
1853 | (unsigned long) address_expr->X_add_number); | |
1854 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
1855 | break; | |
1856 | ||
1857 | case BFD_RELOC_MIPS16_JMP: | |
1858 | if ((address_expr->X_add_number & 3) != 0) | |
1859 | as_bad (_("jump to misaligned address (0x%lx)"), | |
1860 | (unsigned long) address_expr->X_add_number); | |
1861 | ip->insn_opcode |= | |
1862 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1863 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1864 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1865 | break; | |
1866 | ||
1867 | ||
1868 | case BFD_RELOC_16_PCREL_S2: | |
1869 | goto need_reloc; | |
1870 | ||
1871 | default: | |
1872 | internalError (); | |
1873 | } | |
1874 | } | |
1875 | else | |
1876 | { | |
1877 | need_reloc: | |
1878 | /* Don't generate a reloc if we are writing into a variant | |
1879 | frag. */ | |
1880 | if (place == NULL) | |
1881 | { | |
1882 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1883 | address_expr, | |
1884 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1885 | reloc_type); | |
1886 | if (unmatched_hi) | |
1887 | { | |
1888 | struct mips_hi_fixup *hi_fixup; | |
1889 | ||
1890 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1891 | hi_fixup = ((struct mips_hi_fixup *) | |
1892 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1893 | hi_fixup->fixp = fixp; | |
1894 | hi_fixup->seg = now_seg; | |
1895 | hi_fixup->next = mips_hi_fixup_list; | |
1896 | mips_hi_fixup_list = hi_fixup; | |
1897 | } | |
1898 | } | |
1899 | } | |
1900 | } | |
1901 | ||
1902 | if (! mips_opts.mips16) | |
1903 | md_number_to_chars (f, ip->insn_opcode, 4); | |
1904 | else if (reloc_type == BFD_RELOC_MIPS16_JMP) | |
1905 | { | |
1906 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
1907 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
1908 | } | |
1909 | else | |
1910 | { | |
1911 | if (ip->use_extend) | |
1912 | { | |
1913 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1914 | f += 2; | |
1915 | } | |
1916 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1917 | } | |
1918 | ||
1919 | /* Update the register mask information. */ | |
1920 | if (! mips_opts.mips16) | |
1921 | { | |
1922 | if (pinfo & INSN_WRITE_GPR_D) | |
1923 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1924 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1925 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1926 | if (pinfo & INSN_READ_GPR_S) | |
1927 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1928 | if (pinfo & INSN_WRITE_GPR_31) | |
1929 | mips_gprmask |= 1 << 31; | |
1930 | if (pinfo & INSN_WRITE_FPR_D) | |
1931 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1932 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1933 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1934 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1935 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1936 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1937 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1938 | if (pinfo & INSN_COP) | |
1939 | { | |
1940 | /* We don't keep enough information to sort these cases out. | |
1941 | The itbl support does keep this information however, although | |
1942 | we currently don't support itbl fprmats as part of the cop | |
1943 | instruction. May want to add this support in the future. */ | |
1944 | } | |
1945 | /* Never set the bit for $0, which is always zero. */ | |
1946 | mips_gprmask &=~ 1 << 0; | |
1947 | } | |
1948 | else | |
1949 | { | |
1950 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
1951 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1952 | & MIPS16OP_MASK_RX); | |
1953 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1954 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1955 | & MIPS16OP_MASK_RY); | |
1956 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1957 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1958 | & MIPS16OP_MASK_RZ); | |
1959 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1960 | mips_gprmask |= 1 << TREG; | |
1961 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1962 | mips_gprmask |= 1 << SP; | |
1963 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1964 | mips_gprmask |= 1 << RA; | |
1965 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1966 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1967 | if (pinfo & MIPS16_INSN_READ_Z) | |
1968 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1969 | & MIPS16OP_MASK_MOVE32Z); | |
1970 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1971 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1972 | & MIPS16OP_MASK_REGR32); | |
1973 | } | |
1974 | ||
1975 | if (place == NULL && ! mips_opts.noreorder) | |
1976 | { | |
1977 | /* Filling the branch delay slot is more complex. We try to | |
1978 | switch the branch with the previous instruction, which we can | |
1979 | do if the previous instruction does not set up a condition | |
1980 | that the branch tests and if the branch is not itself the | |
1981 | target of any branch. */ | |
1982 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
1983 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
1984 | { | |
1985 | if (mips_optimize < 2 | |
1986 | /* If we have seen .set volatile or .set nomove, don't | |
1987 | optimize. */ | |
1988 | || mips_opts.nomove != 0 | |
1989 | /* If we had to emit any NOP instructions, then we | |
1990 | already know we can not swap. */ | |
1991 | || nops != 0 | |
1992 | /* If we don't even know the previous insn, we can not | |
1993 | swap. */ | |
1994 | || ! prev_insn_valid | |
1995 | /* If the previous insn is already in a branch delay | |
1996 | slot, then we can not swap. */ | |
1997 | || prev_insn_is_delay_slot | |
1998 | /* If the previous previous insn was in a .set | |
1999 | noreorder, we can't swap. Actually, the MIPS | |
2000 | assembler will swap in this situation. However, gcc | |
2001 | configured -with-gnu-as will generate code like | |
2002 | .set noreorder | |
2003 | lw $4,XXX | |
2004 | .set reorder | |
2005 | INSN | |
2006 | bne $4,$0,foo | |
2007 | in which we can not swap the bne and INSN. If gcc is | |
2008 | not configured -with-gnu-as, it does not output the | |
2009 | .set pseudo-ops. We don't have to check | |
2010 | prev_insn_unreordered, because prev_insn_valid will | |
2011 | be 0 in that case. We don't want to use | |
2012 | prev_prev_insn_valid, because we do want to be able | |
2013 | to swap at the start of a function. */ | |
2014 | || prev_prev_insn_unreordered | |
2015 | /* If the branch is itself the target of a branch, we | |
2016 | can not swap. We cheat on this; all we check for is | |
2017 | whether there is a label on this instruction. If | |
2018 | there are any branches to anything other than a | |
2019 | label, users must use .set noreorder. */ | |
2020 | || insn_labels != NULL | |
2021 | /* If the previous instruction is in a variant frag, we | |
2022 | can not do the swap. This does not apply to the | |
2023 | mips16, which uses variant frags for different | |
2024 | purposes. */ | |
2025 | || (! mips_opts.mips16 | |
2026 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
2027 | /* If the branch reads the condition codes, we don't | |
2028 | even try to swap, because in the sequence | |
2029 | ctc1 $X,$31 | |
2030 | INSN | |
2031 | INSN | |
2032 | bc1t LABEL | |
2033 | we can not swap, and I don't feel like handling that | |
2034 | case. */ | |
2035 | || (! mips_opts.mips16 | |
9ce8a5dd | 2036 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2037 | && (pinfo & INSN_READ_COND_CODE)) |
2038 | /* We can not swap with an instruction that requires a | |
2039 | delay slot, becase the target of the branch might | |
2040 | interfere with that instruction. */ | |
2041 | || (! mips_opts.mips16 | |
9ce8a5dd | 2042 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2043 | && (prev_pinfo |
2044 | /* Itbl support may require additional care here. */ | |
2045 | & (INSN_LOAD_COPROC_DELAY | |
2046 | | INSN_COPROC_MOVE_DELAY | |
2047 | | INSN_WRITE_COND_CODE))) | |
2048 | || (! (hilo_interlocks | |
2049 | || (mips_cpu == 3900 && (pinfo & INSN_MULT))) | |
2050 | && (prev_pinfo | |
2051 | & (INSN_READ_LO | |
2052 | | INSN_READ_HI))) | |
2053 | || (! mips_opts.mips16 | |
2054 | && ! gpr_interlocks | |
2055 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
2056 | || (! mips_opts.mips16 | |
9ce8a5dd | 2057 | && mips_opts.isa == 1 |
252b5132 RH |
2058 | /* Itbl support may require additional care here. */ |
2059 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) | |
2060 | /* We can not swap with a branch instruction. */ | |
2061 | || (prev_pinfo | |
2062 | & (INSN_UNCOND_BRANCH_DELAY | |
2063 | | INSN_COND_BRANCH_DELAY | |
2064 | | INSN_COND_BRANCH_LIKELY)) | |
2065 | /* We do not swap with a trap instruction, since it | |
2066 | complicates trap handlers to have the trap | |
2067 | instruction be in a delay slot. */ | |
2068 | || (prev_pinfo & INSN_TRAP) | |
2069 | /* If the branch reads a register that the previous | |
2070 | instruction sets, we can not swap. */ | |
2071 | || (! mips_opts.mips16 | |
2072 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2073 | && insn_uses_reg (ip, | |
2074 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2075 | & OP_MASK_RT), | |
2076 | MIPS_GR_REG)) | |
2077 | || (! mips_opts.mips16 | |
2078 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2079 | && insn_uses_reg (ip, | |
2080 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2081 | & OP_MASK_RD), | |
2082 | MIPS_GR_REG)) | |
2083 | || (mips_opts.mips16 | |
2084 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2085 | && insn_uses_reg (ip, | |
2086 | ((prev_insn.insn_opcode | |
2087 | >> MIPS16OP_SH_RX) | |
2088 | & MIPS16OP_MASK_RX), | |
2089 | MIPS16_REG)) | |
2090 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2091 | && insn_uses_reg (ip, | |
2092 | ((prev_insn.insn_opcode | |
2093 | >> MIPS16OP_SH_RY) | |
2094 | & MIPS16OP_MASK_RY), | |
2095 | MIPS16_REG)) | |
2096 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2097 | && insn_uses_reg (ip, | |
2098 | ((prev_insn.insn_opcode | |
2099 | >> MIPS16OP_SH_RZ) | |
2100 | & MIPS16OP_MASK_RZ), | |
2101 | MIPS16_REG)) | |
2102 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2103 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2104 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2105 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2106 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2107 | && insn_uses_reg (ip, | |
2108 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2109 | insn_opcode), | |
2110 | MIPS_GR_REG)))) | |
2111 | /* If the branch writes a register that the previous | |
2112 | instruction sets, we can not swap (we know that | |
2113 | branches write only to RD or to $31). */ | |
2114 | || (! mips_opts.mips16 | |
2115 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2116 | && (((pinfo & INSN_WRITE_GPR_D) | |
2117 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2118 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2119 | || ((pinfo & INSN_WRITE_GPR_31) | |
2120 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2121 | & OP_MASK_RT) | |
2122 | == 31)))) | |
2123 | || (! mips_opts.mips16 | |
2124 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2125 | && (((pinfo & INSN_WRITE_GPR_D) | |
2126 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2127 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2128 | || ((pinfo & INSN_WRITE_GPR_31) | |
2129 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2130 | & OP_MASK_RD) | |
2131 | == 31)))) | |
2132 | || (mips_opts.mips16 | |
2133 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2134 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2135 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2136 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2137 | == RA)))) | |
2138 | /* If the branch writes a register that the previous | |
2139 | instruction reads, we can not swap (we know that | |
2140 | branches only write to RD or to $31). */ | |
2141 | || (! mips_opts.mips16 | |
2142 | && (pinfo & INSN_WRITE_GPR_D) | |
2143 | && insn_uses_reg (&prev_insn, | |
2144 | ((ip->insn_opcode >> OP_SH_RD) | |
2145 | & OP_MASK_RD), | |
2146 | MIPS_GR_REG)) | |
2147 | || (! mips_opts.mips16 | |
2148 | && (pinfo & INSN_WRITE_GPR_31) | |
2149 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
2150 | || (mips_opts.mips16 | |
2151 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2152 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
2153 | /* If we are generating embedded PIC code, the branch | |
2154 | might be expanded into a sequence which uses $at, so | |
2155 | we can't swap with an instruction which reads it. */ | |
2156 | || (mips_pic == EMBEDDED_PIC | |
2157 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) | |
2158 | /* If the previous previous instruction has a load | |
2159 | delay, and sets a register that the branch reads, we | |
2160 | can not swap. */ | |
2161 | || (! mips_opts.mips16 | |
9ce8a5dd | 2162 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2163 | /* Itbl support may require additional care here. */ |
2164 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) | |
2165 | || (! gpr_interlocks | |
2166 | && (prev_prev_insn.insn_mo->pinfo | |
2167 | & INSN_LOAD_MEMORY_DELAY))) | |
2168 | && insn_uses_reg (ip, | |
2169 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2170 | & OP_MASK_RT), | |
2171 | MIPS_GR_REG)) | |
2172 | /* If one instruction sets a condition code and the | |
2173 | other one uses a condition code, we can not swap. */ | |
2174 | || ((pinfo & INSN_READ_COND_CODE) | |
2175 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2176 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2177 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2178 | /* If the previous instruction uses the PC, we can not | |
2179 | swap. */ | |
2180 | || (mips_opts.mips16 | |
2181 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2182 | /* If the previous instruction was extended, we can not | |
2183 | swap. */ | |
2184 | || (mips_opts.mips16 && prev_insn_extended) | |
2185 | /* If the previous instruction had a fixup in mips16 | |
2186 | mode, we can not swap. This normally means that the | |
2187 | previous instruction was a 4 byte branch anyhow. */ | |
2188 | || (mips_opts.mips16 && prev_insn_fixp) | |
2189 | /* If the previous instruction is a sync, sync.l, or | |
2190 | sync.p, we can not swap. */ | |
f173e82e | 2191 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2192 | { |
2193 | /* We could do even better for unconditional branches to | |
2194 | portions of this object file; we could pick up the | |
2195 | instruction at the destination, put it in the delay | |
2196 | slot, and bump the destination address. */ | |
2197 | emit_nop (); | |
2198 | /* Update the previous insn information. */ | |
2199 | prev_prev_insn = *ip; | |
2200 | prev_insn.insn_mo = &dummy_opcode; | |
2201 | } | |
2202 | else | |
2203 | { | |
2204 | /* It looks like we can actually do the swap. */ | |
2205 | if (! mips_opts.mips16) | |
2206 | { | |
2207 | char *prev_f; | |
2208 | char temp[4]; | |
2209 | ||
2210 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2211 | memcpy (temp, prev_f, 4); | |
2212 | memcpy (prev_f, f, 4); | |
2213 | memcpy (f, temp, 4); | |
2214 | if (prev_insn_fixp) | |
2215 | { | |
2216 | prev_insn_fixp->fx_frag = frag_now; | |
2217 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
2218 | } | |
2219 | if (fixp) | |
2220 | { | |
2221 | fixp->fx_frag = prev_insn_frag; | |
2222 | fixp->fx_where = prev_insn_where; | |
2223 | } | |
2224 | } | |
2225 | else | |
2226 | { | |
2227 | char *prev_f; | |
2228 | char temp[2]; | |
2229 | ||
2230 | assert (prev_insn_fixp == NULL); | |
2231 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2232 | memcpy (temp, prev_f, 2); | |
2233 | memcpy (prev_f, f, 2); | |
2234 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
2235 | { | |
2236 | assert (reloc_type == BFD_RELOC_UNUSED); | |
2237 | memcpy (f, temp, 2); | |
2238 | } | |
2239 | else | |
2240 | { | |
2241 | memcpy (f, f + 2, 2); | |
2242 | memcpy (f + 2, temp, 2); | |
2243 | } | |
2244 | if (fixp) | |
2245 | { | |
2246 | fixp->fx_frag = prev_insn_frag; | |
2247 | fixp->fx_where = prev_insn_where; | |
2248 | } | |
2249 | } | |
2250 | ||
2251 | /* Update the previous insn information; leave prev_insn | |
2252 | unchanged. */ | |
2253 | prev_prev_insn = *ip; | |
2254 | } | |
2255 | prev_insn_is_delay_slot = 1; | |
2256 | ||
2257 | /* If that was an unconditional branch, forget the previous | |
2258 | insn information. */ | |
2259 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2260 | { | |
2261 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2262 | prev_insn.insn_mo = &dummy_opcode; | |
2263 | } | |
2264 | ||
2265 | prev_insn_fixp = NULL; | |
2266 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2267 | prev_insn_extended = 0; | |
2268 | } | |
2269 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2270 | { | |
2271 | /* We don't yet optimize a branch likely. What we should do | |
2272 | is look at the target, copy the instruction found there | |
2273 | into the delay slot, and increment the branch to jump to | |
2274 | the next instruction. */ | |
2275 | emit_nop (); | |
2276 | /* Update the previous insn information. */ | |
2277 | prev_prev_insn = *ip; | |
2278 | prev_insn.insn_mo = &dummy_opcode; | |
2279 | prev_insn_fixp = NULL; | |
2280 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2281 | prev_insn_extended = 0; | |
2282 | } | |
2283 | else | |
2284 | { | |
2285 | /* Update the previous insn information. */ | |
2286 | if (nops > 0) | |
2287 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2288 | else | |
2289 | prev_prev_insn = prev_insn; | |
2290 | prev_insn = *ip; | |
2291 | ||
2292 | /* Any time we see a branch, we always fill the delay slot | |
2293 | immediately; since this insn is not a branch, we know it | |
2294 | is not in a delay slot. */ | |
2295 | prev_insn_is_delay_slot = 0; | |
2296 | ||
2297 | prev_insn_fixp = fixp; | |
2298 | prev_insn_reloc_type = reloc_type; | |
2299 | if (mips_opts.mips16) | |
2300 | prev_insn_extended = (ip->use_extend | |
2301 | || reloc_type > BFD_RELOC_UNUSED); | |
2302 | } | |
2303 | ||
2304 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2305 | prev_insn_unreordered = 0; | |
2306 | prev_insn_frag = frag_now; | |
2307 | prev_insn_where = f - frag_now->fr_literal; | |
2308 | prev_insn_valid = 1; | |
2309 | } | |
2310 | else if (place == NULL) | |
2311 | { | |
2312 | /* We need to record a bit of information even when we are not | |
2313 | reordering, in order to determine the base address for mips16 | |
2314 | PC relative relocs. */ | |
2315 | prev_prev_insn = prev_insn; | |
2316 | prev_insn = *ip; | |
2317 | prev_insn_reloc_type = reloc_type; | |
2318 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2319 | prev_insn_unreordered = 1; | |
2320 | } | |
2321 | ||
2322 | /* We just output an insn, so the next one doesn't have a label. */ | |
2323 | mips_clear_insn_labels (); | |
2324 | ||
2325 | /* We must ensure that a fixup associated with an unmatched %hi | |
2326 | reloc does not become a variant frag. Otherwise, the | |
2327 | rearrangement of %hi relocs in frob_file may confuse | |
2328 | tc_gen_reloc. */ | |
2329 | if (unmatched_hi) | |
2330 | { | |
2331 | frag_wane (frag_now); | |
2332 | frag_new (0); | |
2333 | } | |
2334 | } | |
2335 | ||
2336 | /* This function forgets that there was any previous instruction or | |
2337 | label. If PRESERVE is non-zero, it remembers enough information to | |
2338 | know whether nops are needed before a noreorder section. */ | |
2339 | ||
2340 | static void | |
2341 | mips_no_prev_insn (preserve) | |
2342 | int preserve; | |
2343 | { | |
2344 | if (! preserve) | |
2345 | { | |
2346 | prev_insn.insn_mo = &dummy_opcode; | |
2347 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2348 | prev_nop_frag = NULL; | |
2349 | prev_nop_frag_holds = 0; | |
2350 | prev_nop_frag_required = 0; | |
2351 | prev_nop_frag_since = 0; | |
2352 | } | |
2353 | prev_insn_valid = 0; | |
2354 | prev_insn_is_delay_slot = 0; | |
2355 | prev_insn_unreordered = 0; | |
2356 | prev_insn_extended = 0; | |
2357 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2358 | prev_prev_insn_unreordered = 0; | |
2359 | mips_clear_insn_labels (); | |
2360 | } | |
2361 | ||
2362 | /* This function must be called whenever we turn on noreorder or emit | |
2363 | something other than instructions. It inserts any NOPS which might | |
2364 | be needed by the previous instruction, and clears the information | |
2365 | kept for the previous instructions. The INSNS parameter is true if | |
2366 | instructions are to follow. */ | |
2367 | ||
2368 | static void | |
2369 | mips_emit_delays (insns) | |
2370 | boolean insns; | |
2371 | { | |
2372 | if (! mips_opts.noreorder) | |
2373 | { | |
2374 | int nops; | |
2375 | ||
2376 | nops = 0; | |
2377 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2378 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2379 | && (! cop_interlocks |
2380 | && (prev_insn.insn_mo->pinfo | |
2381 | & (INSN_LOAD_COPROC_DELAY | |
2382 | | INSN_COPROC_MOVE_DELAY | |
2383 | | INSN_WRITE_COND_CODE)))) | |
2384 | || (! hilo_interlocks | |
2385 | && (prev_insn.insn_mo->pinfo | |
2386 | & (INSN_READ_LO | |
2387 | | INSN_READ_HI))) | |
2388 | || (! mips_opts.mips16 | |
2389 | && ! gpr_interlocks | |
2390 | && (prev_insn.insn_mo->pinfo | |
2391 | & INSN_LOAD_MEMORY_DELAY)) | |
2392 | || (! mips_opts.mips16 | |
9ce8a5dd | 2393 | && mips_opts.isa == 1 |
252b5132 RH |
2394 | && (prev_insn.insn_mo->pinfo |
2395 | & INSN_COPROC_MEMORY_DELAY))) | |
2396 | { | |
2397 | /* Itbl support may require additional care here. */ | |
2398 | ++nops; | |
2399 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2400 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2401 | && (! cop_interlocks |
2402 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2403 | || (! hilo_interlocks | |
2404 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2405 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2406 | ++nops; | |
2407 | ||
2408 | if (prev_insn_unreordered) | |
2409 | nops = 0; | |
2410 | } | |
2411 | else if ((! mips_opts.mips16 | |
9ce8a5dd | 2412 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2413 | && (! cop_interlocks |
2414 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2415 | || (! hilo_interlocks | |
2416 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2417 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2418 | { | |
2419 | /* Itbl support may require additional care here. */ | |
2420 | if (! prev_prev_insn_unreordered) | |
2421 | ++nops; | |
2422 | } | |
2423 | ||
2424 | if (nops > 0) | |
2425 | { | |
2426 | struct insn_label_list *l; | |
2427 | ||
2428 | if (insns) | |
2429 | { | |
2430 | /* Record the frag which holds the nop instructions, so | |
2431 | that we can remove them if we don't need them. */ | |
2432 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2433 | prev_nop_frag = frag_now; | |
2434 | prev_nop_frag_holds = nops; | |
2435 | prev_nop_frag_required = 0; | |
2436 | prev_nop_frag_since = 0; | |
2437 | } | |
2438 | ||
2439 | for (; nops > 0; --nops) | |
2440 | emit_nop (); | |
2441 | ||
2442 | if (insns) | |
2443 | { | |
2444 | /* Move on to a new frag, so that it is safe to simply | |
2445 | decrease the size of prev_nop_frag. */ | |
2446 | frag_wane (frag_now); | |
2447 | frag_new (0); | |
2448 | } | |
2449 | ||
2450 | for (l = insn_labels; l != NULL; l = l->next) | |
2451 | { | |
2452 | assert (S_GET_SEGMENT (l->label) == now_seg); | |
49309057 | 2453 | symbol_set_frag (l->label, frag_now); |
252b5132 RH |
2454 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); |
2455 | /* mips16 text labels are stored as odd. */ | |
2456 | if (mips_opts.mips16) | |
49309057 | 2457 | S_SET_VALUE (l->label, S_GET_VALUE (l->label) + 1); |
252b5132 RH |
2458 | } |
2459 | } | |
2460 | } | |
2461 | ||
2462 | /* Mark instruction labels in mips16 mode. */ | |
2463 | if (mips_opts.mips16 && insns) | |
2464 | mips16_mark_labels (); | |
2465 | ||
2466 | mips_no_prev_insn (insns); | |
2467 | } | |
2468 | ||
2469 | /* Build an instruction created by a macro expansion. This is passed | |
2470 | a pointer to the count of instructions created so far, an | |
2471 | expression, the name of the instruction to build, an operand format | |
2472 | string, and corresponding arguments. */ | |
2473 | ||
2474 | #ifdef USE_STDARG | |
2475 | static void | |
2476 | macro_build (char *place, | |
2477 | int *counter, | |
2478 | expressionS * ep, | |
2479 | const char *name, | |
2480 | const char *fmt, | |
2481 | ...) | |
2482 | #else | |
2483 | static void | |
2484 | macro_build (place, counter, ep, name, fmt, va_alist) | |
2485 | char *place; | |
2486 | int *counter; | |
2487 | expressionS *ep; | |
2488 | const char *name; | |
2489 | const char *fmt; | |
2490 | va_dcl | |
2491 | #endif | |
2492 | { | |
2493 | struct mips_cl_insn insn; | |
2494 | bfd_reloc_code_real_type r; | |
2495 | va_list args; | |
252b5132 RH |
2496 | |
2497 | #ifdef USE_STDARG | |
2498 | va_start (args, fmt); | |
2499 | #else | |
2500 | va_start (args); | |
2501 | #endif | |
2502 | ||
2503 | /* | |
2504 | * If the macro is about to expand into a second instruction, | |
2505 | * print a warning if needed. We need to pass ip as a parameter | |
2506 | * to generate a better warning message here... | |
2507 | */ | |
2508 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2509 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2510 | ||
2511 | if (place == NULL) | |
2512 | *counter += 1; /* bump instruction counter */ | |
2513 | ||
2514 | if (mips_opts.mips16) | |
2515 | { | |
2516 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2517 | va_end (args); | |
2518 | return; | |
2519 | } | |
2520 | ||
2521 | r = BFD_RELOC_UNUSED; | |
2522 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2523 | assert (insn.insn_mo); | |
2524 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2525 | ||
2526 | /* Search until we get a match for NAME. */ | |
2527 | while (1) | |
2528 | { | |
252b5132 RH |
2529 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2530 | && insn.insn_mo->pinfo != INSN_MACRO | |
c97ef257 AH |
2531 | && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_cpu, |
2532 | mips_gp32) | |
252b5132 RH |
2533 | && (mips_cpu != 4650 || (insn.insn_mo->pinfo & FP_D) == 0)) |
2534 | break; | |
2535 | ||
2536 | ++insn.insn_mo; | |
2537 | assert (insn.insn_mo->name); | |
2538 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2539 | } | |
2540 | ||
2541 | insn.insn_opcode = insn.insn_mo->match; | |
2542 | for (;;) | |
2543 | { | |
2544 | switch (*fmt++) | |
2545 | { | |
2546 | case '\0': | |
2547 | break; | |
2548 | ||
2549 | case ',': | |
2550 | case '(': | |
2551 | case ')': | |
2552 | continue; | |
2553 | ||
2554 | case 't': | |
2555 | case 'w': | |
2556 | case 'E': | |
2557 | insn.insn_opcode |= va_arg (args, int) << 16; | |
2558 | continue; | |
2559 | ||
2560 | case 'c': | |
2561 | case 'T': | |
2562 | case 'W': | |
2563 | insn.insn_opcode |= va_arg (args, int) << 16; | |
2564 | continue; | |
2565 | ||
2566 | case 'd': | |
2567 | case 'G': | |
2568 | insn.insn_opcode |= va_arg (args, int) << 11; | |
2569 | continue; | |
2570 | ||
2571 | case 'V': | |
2572 | case 'S': | |
2573 | insn.insn_opcode |= va_arg (args, int) << 11; | |
2574 | continue; | |
2575 | ||
2576 | case 'z': | |
2577 | continue; | |
2578 | ||
2579 | case '<': | |
2580 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2581 | continue; | |
2582 | ||
2583 | case 'D': | |
2584 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2585 | continue; | |
2586 | ||
2587 | case 'B': | |
2588 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2589 | continue; | |
2590 | ||
2591 | case 'q': | |
2592 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2593 | continue; | |
2594 | ||
2595 | case 'b': | |
2596 | case 's': | |
2597 | case 'r': | |
2598 | case 'v': | |
2599 | insn.insn_opcode |= va_arg (args, int) << 21; | |
2600 | continue; | |
2601 | ||
2602 | case 'i': | |
2603 | case 'j': | |
2604 | case 'o': | |
2605 | r = (bfd_reloc_code_real_type) va_arg (args, int); | |
2606 | assert (r == BFD_RELOC_MIPS_GPREL | |
2607 | || r == BFD_RELOC_MIPS_LITERAL | |
2608 | || r == BFD_RELOC_LO16 | |
2609 | || r == BFD_RELOC_MIPS_GOT16 | |
2610 | || r == BFD_RELOC_MIPS_CALL16 | |
2611 | || r == BFD_RELOC_MIPS_GOT_LO16 | |
2612 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
2613 | || (ep->X_op == O_subtract | |
252b5132 RH |
2614 | && r == BFD_RELOC_PCREL_LO16)); |
2615 | continue; | |
2616 | ||
2617 | case 'u': | |
2618 | r = (bfd_reloc_code_real_type) va_arg (args, int); | |
2619 | assert (ep != NULL | |
2620 | && (ep->X_op == O_constant | |
2621 | || (ep->X_op == O_symbol | |
2622 | && (r == BFD_RELOC_HI16_S | |
2623 | || r == BFD_RELOC_HI16 | |
2624 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2625 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
2626 | || (ep->X_op == O_subtract | |
252b5132 RH |
2627 | && r == BFD_RELOC_PCREL_HI16_S))); |
2628 | if (ep->X_op == O_constant) | |
2629 | { | |
2630 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2631 | ep = NULL; | |
2632 | r = BFD_RELOC_UNUSED; | |
2633 | } | |
2634 | continue; | |
2635 | ||
2636 | case 'p': | |
2637 | assert (ep != NULL); | |
2638 | /* | |
2639 | * This allows macro() to pass an immediate expression for | |
2640 | * creating short branches without creating a symbol. | |
2641 | * Note that the expression still might come from the assembly | |
2642 | * input, in which case the value is not checked for range nor | |
2643 | * is a relocation entry generated (yuck). | |
2644 | */ | |
2645 | if (ep->X_op == O_constant) | |
2646 | { | |
2647 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2648 | ep = NULL; | |
2649 | } | |
2650 | else | |
2651 | r = BFD_RELOC_16_PCREL_S2; | |
2652 | continue; | |
2653 | ||
2654 | case 'a': | |
2655 | assert (ep != NULL); | |
2656 | r = BFD_RELOC_MIPS_JMP; | |
2657 | continue; | |
2658 | ||
2659 | case 'C': | |
2660 | insn.insn_opcode |= va_arg (args, unsigned long); | |
2661 | continue; | |
2662 | ||
2663 | default: | |
2664 | internalError (); | |
2665 | } | |
2666 | break; | |
2667 | } | |
2668 | va_end (args); | |
2669 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2670 | ||
2671 | append_insn (place, &insn, ep, r, false); | |
2672 | } | |
2673 | ||
2674 | static void | |
2675 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2676 | char *place; | |
43841e91 | 2677 | int *counter ATTRIBUTE_UNUSED; |
252b5132 RH |
2678 | expressionS *ep; |
2679 | const char *name; | |
2680 | const char *fmt; | |
2681 | va_list args; | |
2682 | { | |
2683 | struct mips_cl_insn insn; | |
2684 | bfd_reloc_code_real_type r; | |
2685 | ||
2686 | r = BFD_RELOC_UNUSED; | |
2687 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2688 | assert (insn.insn_mo); | |
2689 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2690 | ||
2691 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2692 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2693 | { | |
2694 | ++insn.insn_mo; | |
2695 | assert (insn.insn_mo->name); | |
2696 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2697 | } | |
2698 | ||
2699 | insn.insn_opcode = insn.insn_mo->match; | |
2700 | insn.use_extend = false; | |
2701 | ||
2702 | for (;;) | |
2703 | { | |
2704 | int c; | |
2705 | ||
2706 | c = *fmt++; | |
2707 | switch (c) | |
2708 | { | |
2709 | case '\0': | |
2710 | break; | |
2711 | ||
2712 | case ',': | |
2713 | case '(': | |
2714 | case ')': | |
2715 | continue; | |
2716 | ||
2717 | case 'y': | |
2718 | case 'w': | |
2719 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2720 | continue; | |
2721 | ||
2722 | case 'x': | |
2723 | case 'v': | |
2724 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2725 | continue; | |
2726 | ||
2727 | case 'z': | |
2728 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2729 | continue; | |
2730 | ||
2731 | case 'Z': | |
2732 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2733 | continue; | |
2734 | ||
2735 | case '0': | |
2736 | case 'S': | |
2737 | case 'P': | |
2738 | case 'R': | |
2739 | continue; | |
2740 | ||
2741 | case 'X': | |
2742 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2743 | continue; | |
2744 | ||
2745 | case 'Y': | |
2746 | { | |
2747 | int regno; | |
2748 | ||
2749 | regno = va_arg (args, int); | |
2750 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2751 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2752 | } | |
2753 | continue; | |
2754 | ||
2755 | case '<': | |
2756 | case '>': | |
2757 | case '4': | |
2758 | case '5': | |
2759 | case 'H': | |
2760 | case 'W': | |
2761 | case 'D': | |
2762 | case 'j': | |
2763 | case '8': | |
2764 | case 'V': | |
2765 | case 'C': | |
2766 | case 'U': | |
2767 | case 'k': | |
2768 | case 'K': | |
2769 | case 'p': | |
2770 | case 'q': | |
2771 | { | |
2772 | assert (ep != NULL); | |
2773 | ||
2774 | if (ep->X_op != O_constant) | |
2775 | r = BFD_RELOC_UNUSED + c; | |
2776 | else | |
2777 | { | |
2778 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, | |
2779 | false, false, &insn.insn_opcode, | |
2780 | &insn.use_extend, &insn.extend); | |
2781 | ep = NULL; | |
2782 | r = BFD_RELOC_UNUSED; | |
2783 | } | |
2784 | } | |
2785 | continue; | |
2786 | ||
2787 | case '6': | |
2788 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2789 | continue; | |
2790 | } | |
2791 | ||
2792 | break; | |
2793 | } | |
2794 | ||
2795 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2796 | ||
2797 | append_insn (place, &insn, ep, r, false); | |
2798 | } | |
2799 | ||
2800 | /* | |
2801 | * Generate a "lui" instruction. | |
2802 | */ | |
2803 | static void | |
2804 | macro_build_lui (place, counter, ep, regnum) | |
2805 | char *place; | |
2806 | int *counter; | |
2807 | expressionS *ep; | |
2808 | int regnum; | |
2809 | { | |
2810 | expressionS high_expr; | |
2811 | struct mips_cl_insn insn; | |
2812 | bfd_reloc_code_real_type r; | |
2813 | CONST char *name = "lui"; | |
2814 | CONST char *fmt = "t,u"; | |
2815 | ||
2816 | assert (! mips_opts.mips16); | |
2817 | ||
2818 | if (place == NULL) | |
2819 | high_expr = *ep; | |
2820 | else | |
2821 | { | |
2822 | high_expr.X_op = O_constant; | |
2823 | high_expr.X_add_number = ep->X_add_number; | |
2824 | } | |
2825 | ||
2826 | if (high_expr.X_op == O_constant) | |
2827 | { | |
2828 | /* we can compute the instruction now without a relocation entry */ | |
2829 | if (high_expr.X_add_number & 0x8000) | |
2830 | high_expr.X_add_number += 0x10000; | |
2831 | high_expr.X_add_number = | |
2832 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2833 | r = BFD_RELOC_UNUSED; | |
2834 | } | |
2835 | else | |
2836 | { | |
2837 | assert (ep->X_op == O_symbol); | |
2838 | /* _gp_disp is a special case, used from s_cpload. */ | |
2839 | assert (mips_pic == NO_PIC | |
2840 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); | |
2841 | r = BFD_RELOC_HI16_S; | |
2842 | } | |
2843 | ||
2844 | /* | |
2845 | * If the macro is about to expand into a second instruction, | |
2846 | * print a warning if needed. We need to pass ip as a parameter | |
2847 | * to generate a better warning message here... | |
2848 | */ | |
2849 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2850 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2851 | ||
2852 | if (place == NULL) | |
2853 | *counter += 1; /* bump instruction counter */ | |
2854 | ||
2855 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2856 | assert (insn.insn_mo); | |
2857 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2858 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2859 | ||
2860 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
2861 | if (r == BFD_RELOC_UNUSED) | |
2862 | { | |
2863 | insn.insn_opcode |= high_expr.X_add_number; | |
2864 | append_insn (place, &insn, NULL, r, false); | |
2865 | } | |
2866 | else | |
2867 | append_insn (place, &insn, &high_expr, r, false); | |
2868 | } | |
2869 | ||
2870 | /* set_at() | |
2871 | * Generates code to set the $at register to true (one) | |
2872 | * if reg is less than the immediate expression. | |
2873 | */ | |
2874 | static void | |
2875 | set_at (counter, reg, unsignedp) | |
2876 | int *counter; | |
2877 | int reg; | |
2878 | int unsignedp; | |
2879 | { | |
2880 | if (imm_expr.X_op == O_constant | |
2881 | && imm_expr.X_add_number >= -0x8000 | |
2882 | && imm_expr.X_add_number < 0x8000) | |
2883 | macro_build ((char *) NULL, counter, &imm_expr, | |
2884 | unsignedp ? "sltiu" : "slti", | |
2885 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); | |
2886 | else | |
2887 | { | |
2888 | load_register (counter, AT, &imm_expr, 0); | |
2889 | macro_build ((char *) NULL, counter, NULL, | |
2890 | unsignedp ? "sltu" : "slt", | |
2891 | "d,v,t", AT, reg, AT); | |
2892 | } | |
2893 | } | |
2894 | ||
2895 | /* Warn if an expression is not a constant. */ | |
2896 | ||
2897 | static void | |
2898 | check_absolute_expr (ip, ex) | |
2899 | struct mips_cl_insn *ip; | |
2900 | expressionS *ex; | |
2901 | { | |
2902 | if (ex->X_op == O_big) | |
2903 | as_bad (_("unsupported large constant")); | |
2904 | else if (ex->X_op != O_constant) | |
2905 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
2906 | } | |
2907 | ||
2908 | /* Count the leading zeroes by performing a binary chop. This is a | |
2909 | bulky bit of source, but performance is a LOT better for the | |
2910 | majority of values than a simple loop to count the bits: | |
2911 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2912 | if ((v) & (1 << (31 - lcnt))) | |
2913 | break; | |
2914 | However it is not code size friendly, and the gain will drop a bit | |
2915 | on certain cached systems. | |
2916 | */ | |
2917 | #define COUNT_TOP_ZEROES(v) \ | |
2918 | (((v) & ~0xffff) == 0 \ | |
2919 | ? ((v) & ~0xff) == 0 \ | |
2920 | ? ((v) & ~0xf) == 0 \ | |
2921 | ? ((v) & ~0x3) == 0 \ | |
2922 | ? ((v) & ~0x1) == 0 \ | |
2923 | ? !(v) \ | |
2924 | ? 32 \ | |
2925 | : 31 \ | |
2926 | : 30 \ | |
2927 | : ((v) & ~0x7) == 0 \ | |
2928 | ? 29 \ | |
2929 | : 28 \ | |
2930 | : ((v) & ~0x3f) == 0 \ | |
2931 | ? ((v) & ~0x1f) == 0 \ | |
2932 | ? 27 \ | |
2933 | : 26 \ | |
2934 | : ((v) & ~0x7f) == 0 \ | |
2935 | ? 25 \ | |
2936 | : 24 \ | |
2937 | : ((v) & ~0xfff) == 0 \ | |
2938 | ? ((v) & ~0x3ff) == 0 \ | |
2939 | ? ((v) & ~0x1ff) == 0 \ | |
2940 | ? 23 \ | |
2941 | : 22 \ | |
2942 | : ((v) & ~0x7ff) == 0 \ | |
2943 | ? 21 \ | |
2944 | : 20 \ | |
2945 | : ((v) & ~0x3fff) == 0 \ | |
2946 | ? ((v) & ~0x1fff) == 0 \ | |
2947 | ? 19 \ | |
2948 | : 18 \ | |
2949 | : ((v) & ~0x7fff) == 0 \ | |
2950 | ? 17 \ | |
2951 | : 16 \ | |
2952 | : ((v) & ~0xffffff) == 0 \ | |
2953 | ? ((v) & ~0xfffff) == 0 \ | |
2954 | ? ((v) & ~0x3ffff) == 0 \ | |
2955 | ? ((v) & ~0x1ffff) == 0 \ | |
2956 | ? 15 \ | |
2957 | : 14 \ | |
2958 | : ((v) & ~0x7ffff) == 0 \ | |
2959 | ? 13 \ | |
2960 | : 12 \ | |
2961 | : ((v) & ~0x3fffff) == 0 \ | |
2962 | ? ((v) & ~0x1fffff) == 0 \ | |
2963 | ? 11 \ | |
2964 | : 10 \ | |
2965 | : ((v) & ~0x7fffff) == 0 \ | |
2966 | ? 9 \ | |
2967 | : 8 \ | |
2968 | : ((v) & ~0xfffffff) == 0 \ | |
2969 | ? ((v) & ~0x3ffffff) == 0 \ | |
2970 | ? ((v) & ~0x1ffffff) == 0 \ | |
2971 | ? 7 \ | |
2972 | : 6 \ | |
2973 | : ((v) & ~0x7ffffff) == 0 \ | |
2974 | ? 5 \ | |
2975 | : 4 \ | |
2976 | : ((v) & ~0x3fffffff) == 0 \ | |
2977 | ? ((v) & ~0x1fffffff) == 0 \ | |
2978 | ? 3 \ | |
2979 | : 2 \ | |
2980 | : ((v) & ~0x7fffffff) == 0 \ | |
2981 | ? 1 \ | |
2982 | : 0) | |
2983 | ||
2984 | /* load_register() | |
2985 | * This routine generates the least number of instructions neccessary to load | |
2986 | * an absolute expression value into a register. | |
2987 | */ | |
2988 | static void | |
2989 | load_register (counter, reg, ep, dbl) | |
2990 | int *counter; | |
2991 | int reg; | |
2992 | expressionS *ep; | |
2993 | int dbl; | |
2994 | { | |
2995 | int freg; | |
2996 | expressionS hi32, lo32; | |
2997 | ||
2998 | if (ep->X_op != O_big) | |
2999 | { | |
3000 | assert (ep->X_op == O_constant); | |
3001 | if (ep->X_add_number < 0x8000 | |
3002 | && (ep->X_add_number >= 0 | |
3003 | || (ep->X_add_number >= -0x8000 | |
3004 | && (! dbl | |
3005 | || ! ep->X_unsigned | |
3006 | || sizeof (ep->X_add_number) > 4)))) | |
3007 | { | |
3008 | /* We can handle 16 bit signed values with an addiu to | |
3009 | $zero. No need to ever use daddiu here, since $zero and | |
3010 | the result are always correct in 32 bit mode. */ | |
3011 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
3012 | (int) BFD_RELOC_LO16); | |
3013 | return; | |
3014 | } | |
3015 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3016 | { | |
3017 | /* We can handle 16 bit unsigned values with an ori to | |
3018 | $zero. */ | |
3019 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
3020 | (int) BFD_RELOC_LO16); | |
3021 | return; | |
3022 | } | |
3023 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 | |
3024 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
3025 | == ~ (offsetT) 0x7fffffff)) | |
3026 | && (! dbl | |
3027 | || ! ep->X_unsigned | |
3028 | || sizeof (ep->X_add_number) > 4 | |
3029 | || (ep->X_add_number & 0x80000000) == 0)) | |
9ce8a5dd | 3030 | || ((! ISA_HAS_64BIT_REGS (mips_opts.isa) || ! dbl) |
252b5132 | 3031 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
9ce8a5dd | 3032 | || (! ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 RH |
3033 | && ! dbl |
3034 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
3035 | == ~ (offsetT) 0xffffffff))) | |
3036 | { | |
3037 | /* 32 bit values require an lui. */ | |
3038 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3039 | (int) BFD_RELOC_HI16); | |
3040 | if ((ep->X_add_number & 0xffff) != 0) | |
3041 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
3042 | (int) BFD_RELOC_LO16); | |
3043 | return; | |
3044 | } | |
3045 | } | |
3046 | ||
3047 | /* The value is larger than 32 bits. */ | |
3048 | ||
9ce8a5dd | 3049 | if (! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3050 | { |
3051 | as_bad (_("Number larger than 32 bits")); | |
3052 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
3053 | (int) BFD_RELOC_LO16); | |
3054 | return; | |
3055 | } | |
3056 | ||
3057 | if (ep->X_op != O_big) | |
3058 | { | |
3059 | hi32 = *ep; | |
3060 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3061 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3062 | hi32.X_add_number &= 0xffffffff; | |
3063 | lo32 = *ep; | |
3064 | lo32.X_add_number &= 0xffffffff; | |
3065 | } | |
3066 | else | |
3067 | { | |
3068 | assert (ep->X_add_number > 2); | |
3069 | if (ep->X_add_number == 3) | |
3070 | generic_bignum[3] = 0; | |
3071 | else if (ep->X_add_number > 4) | |
3072 | as_bad (_("Number larger than 64 bits")); | |
3073 | lo32.X_op = O_constant; | |
3074 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3075 | hi32.X_op = O_constant; | |
3076 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3077 | } | |
3078 | ||
3079 | if (hi32.X_add_number == 0) | |
3080 | freg = 0; | |
3081 | else | |
3082 | { | |
3083 | int shift, bit; | |
3084 | unsigned long hi, lo; | |
3085 | ||
3086 | if (hi32.X_add_number == 0xffffffff) | |
3087 | { | |
3088 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3089 | { | |
3090 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", | |
3091 | reg, 0, (int) BFD_RELOC_LO16); | |
3092 | return; | |
3093 | } | |
3094 | if (lo32.X_add_number & 0x80000000) | |
3095 | { | |
3096 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3097 | (int) BFD_RELOC_HI16); | |
3098 | if (lo32.X_add_number & 0xffff) | |
3099 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
3100 | reg, reg, (int) BFD_RELOC_LO16); | |
3101 | return; | |
3102 | } | |
3103 | } | |
3104 | ||
3105 | /* Check for 16bit shifted constant. We know that hi32 is | |
3106 | non-zero, so start the mask on the first bit of the hi32 | |
3107 | value. */ | |
3108 | shift = 17; | |
3109 | do | |
3110 | { | |
3111 | unsigned long himask, lomask; | |
3112 | ||
3113 | if (shift < 32) | |
3114 | { | |
3115 | himask = 0xffff >> (32 - shift); | |
3116 | lomask = (0xffff << shift) & 0xffffffff; | |
3117 | } | |
3118 | else | |
3119 | { | |
3120 | himask = 0xffff << (shift - 32); | |
3121 | lomask = 0; | |
3122 | } | |
3123 | if ((hi32.X_add_number & ~ (offsetT) himask) == 0 | |
3124 | && (lo32.X_add_number & ~ (offsetT) lomask) == 0) | |
3125 | { | |
3126 | expressionS tmp; | |
3127 | ||
3128 | tmp.X_op = O_constant; | |
3129 | if (shift < 32) | |
3130 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3131 | | (lo32.X_add_number >> shift)); | |
3132 | else | |
3133 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
3134 | macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, | |
3135 | (int) BFD_RELOC_LO16); | |
3136 | macro_build ((char *) NULL, counter, NULL, | |
3137 | (shift >= 32) ? "dsll32" : "dsll", | |
3138 | "d,w,<", reg, reg, | |
3139 | (shift >= 32) ? shift - 32 : shift); | |
3140 | return; | |
3141 | } | |
3142 | shift++; | |
3143 | } while (shift <= (64 - 16)); | |
3144 | ||
3145 | /* Find the bit number of the lowest one bit, and store the | |
3146 | shifted value in hi/lo. */ | |
3147 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3148 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3149 | if (lo != 0) | |
3150 | { | |
3151 | bit = 0; | |
3152 | while ((lo & 1) == 0) | |
3153 | { | |
3154 | lo >>= 1; | |
3155 | ++bit; | |
3156 | } | |
3157 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3158 | hi >>= bit; | |
3159 | } | |
3160 | else | |
3161 | { | |
3162 | bit = 32; | |
3163 | while ((hi & 1) == 0) | |
3164 | { | |
3165 | hi >>= 1; | |
3166 | ++bit; | |
3167 | } | |
3168 | lo = hi; | |
3169 | hi = 0; | |
3170 | } | |
3171 | ||
3172 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3173 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3174 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
3175 | { | |
3176 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
3177 | if (shift != 0) | |
3178 | { | |
3179 | expressionS tmp; | |
3180 | ||
3181 | /* This instruction will set the register to be all | |
3182 | ones. */ | |
3183 | tmp.X_op = O_constant; | |
3184 | tmp.X_add_number = (offsetT) -1; | |
3185 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
3186 | reg, 0, (int) BFD_RELOC_LO16); | |
3187 | if (bit != 0) | |
3188 | { | |
3189 | bit += shift; | |
3190 | macro_build ((char *) NULL, counter, NULL, | |
3191 | (bit >= 32) ? "dsll32" : "dsll", | |
3192 | "d,w,<", reg, reg, | |
3193 | (bit >= 32) ? bit - 32 : bit); | |
3194 | } | |
3195 | macro_build ((char *) NULL, counter, NULL, | |
3196 | (shift >= 32) ? "dsrl32" : "dsrl", | |
3197 | "d,w,<", reg, reg, | |
3198 | (shift >= 32) ? shift - 32 : shift); | |
3199 | return; | |
3200 | } | |
3201 | } | |
3202 | ||
3203 | /* Sign extend hi32 before calling load_register, because we can | |
3204 | generally get better code when we load a sign extended value. */ | |
3205 | if ((hi32.X_add_number & 0x80000000) != 0) | |
3206 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
3207 | load_register (counter, reg, &hi32, 0); | |
3208 | freg = reg; | |
3209 | } | |
3210 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3211 | { | |
3212 | if (freg != 0) | |
3213 | { | |
3214 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
3215 | freg, 0); | |
3216 | freg = reg; | |
3217 | } | |
3218 | } | |
3219 | else | |
3220 | { | |
3221 | expressionS mid16; | |
3222 | ||
3223 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) | |
3224 | { | |
3225 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3226 | (int) BFD_RELOC_HI16); | |
3227 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
3228 | reg, 0); | |
3229 | return; | |
3230 | } | |
3231 | ||
3232 | if (freg != 0) | |
3233 | { | |
3234 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
3235 | freg, 16); | |
3236 | freg = reg; | |
3237 | } | |
3238 | mid16 = lo32; | |
3239 | mid16.X_add_number >>= 16; | |
3240 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
3241 | freg, (int) BFD_RELOC_LO16); | |
3242 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
3243 | reg, 16); | |
3244 | freg = reg; | |
3245 | } | |
3246 | if ((lo32.X_add_number & 0xffff) != 0) | |
3247 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, | |
3248 | (int) BFD_RELOC_LO16); | |
3249 | } | |
3250 | ||
3251 | /* Load an address into a register. */ | |
3252 | ||
3253 | static void | |
3254 | load_address (counter, reg, ep) | |
3255 | int *counter; | |
3256 | int reg; | |
3257 | expressionS *ep; | |
3258 | { | |
3259 | char *p; | |
3260 | ||
3261 | if (ep->X_op != O_constant | |
3262 | && ep->X_op != O_symbol) | |
3263 | { | |
3264 | as_bad (_("expression too complex")); | |
3265 | ep->X_op = O_constant; | |
3266 | } | |
3267 | ||
3268 | if (ep->X_op == O_constant) | |
3269 | { | |
3270 | load_register (counter, reg, ep, 0); | |
3271 | return; | |
3272 | } | |
3273 | ||
3274 | if (mips_pic == NO_PIC) | |
3275 | { | |
3276 | /* If this is a reference to a GP relative symbol, we want | |
3277 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3278 | Otherwise we want | |
3279 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3280 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3281 | If we have an addend, we always use the latter form. */ | |
3282 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET | |
3283 | || nopic_need_relax (ep->X_add_symbol, 1)) | |
3284 | p = NULL; | |
3285 | else | |
3286 | { | |
3287 | frag_grow (20); | |
3288 | macro_build ((char *) NULL, counter, ep, | |
3289 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3290 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3291 | ? "addiu" : "daddiu"), |
3292 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3293 | p = frag_var (rs_machine_dependent, 8, 0, | |
3294 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3295 | mips_opts.warn_about_macros), | |
3296 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3297 | } | |
3298 | macro_build_lui (p, counter, ep, reg); | |
3299 | if (p != NULL) | |
3300 | p += 4; | |
3301 | macro_build (p, counter, ep, | |
3302 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3303 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3304 | ? "addiu" : "daddiu"), |
3305 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3306 | } | |
3307 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3308 | { | |
3309 | expressionS ex; | |
3310 | ||
3311 | /* If this is a reference to an external symbol, we want | |
3312 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3313 | Otherwise we want | |
3314 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3315 | nop | |
3316 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3317 | If there is a constant, it must be added in after. */ | |
3318 | ex.X_add_number = ep->X_add_number; | |
3319 | ep->X_add_number = 0; | |
3320 | frag_grow (20); | |
3321 | macro_build ((char *) NULL, counter, ep, | |
3322 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3323 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3324 | ? "lw" : "ld"), |
3325 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3326 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3327 | p = frag_var (rs_machine_dependent, 4, 0, | |
3328 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), | |
3329 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3330 | macro_build (p, counter, ep, | |
3331 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3332 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3333 | ? "addiu" : "daddiu"), |
3334 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3335 | if (ex.X_add_number != 0) | |
3336 | { | |
3337 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3338 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3339 | ex.X_op = O_constant; | |
3340 | macro_build ((char *) NULL, counter, &ex, | |
3341 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3342 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3343 | ? "addiu" : "daddiu"), |
3344 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3345 | } | |
3346 | } | |
3347 | else if (mips_pic == SVR4_PIC) | |
3348 | { | |
3349 | expressionS ex; | |
3350 | int off; | |
3351 | ||
3352 | /* This is the large GOT case. If this is a reference to an | |
3353 | external symbol, we want | |
3354 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3355 | addu $reg,$reg,$gp | |
3356 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3357 | Otherwise, for a reference to a local symbol, we want | |
3358 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3359 | nop | |
3360 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3361 | If there is a constant, it must be added in after. */ | |
3362 | ex.X_add_number = ep->X_add_number; | |
3363 | ep->X_add_number = 0; | |
3364 | if (reg_needs_delay (GP)) | |
3365 | off = 4; | |
3366 | else | |
3367 | off = 0; | |
3368 | frag_grow (32); | |
3369 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3370 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3371 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
3372 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3373 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3374 | ? "addu" : "daddu"), |
3375 | "d,v,t", reg, reg, GP); | |
3376 | macro_build ((char *) NULL, counter, ep, | |
3377 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3378 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3379 | ? "lw" : "ld"), |
3380 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); | |
3381 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3382 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3383 | mips_opts.warn_about_macros), | |
3384 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3385 | if (off > 0) | |
3386 | { | |
3387 | /* We need a nop before loading from $gp. This special | |
3388 | check is required because the lui which starts the main | |
3389 | instruction stream does not refer to $gp, and so will not | |
3390 | insert the nop which may be required. */ | |
3391 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3392 | p += 4; | |
3393 | } | |
3394 | macro_build (p, counter, ep, | |
3395 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3396 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3397 | ? "lw" : "ld"), |
3398 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3399 | p += 4; | |
3400 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3401 | p += 4; | |
3402 | macro_build (p, counter, ep, | |
3403 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3404 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3405 | ? "addiu" : "daddiu"), |
3406 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3407 | if (ex.X_add_number != 0) | |
3408 | { | |
3409 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3410 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3411 | ex.X_op = O_constant; | |
3412 | macro_build ((char *) NULL, counter, &ex, | |
3413 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3414 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3415 | ? "addiu" : "daddiu"), |
3416 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3417 | } | |
3418 | } | |
3419 | else if (mips_pic == EMBEDDED_PIC) | |
3420 | { | |
3421 | /* We always do | |
3422 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3423 | */ | |
3424 | macro_build ((char *) NULL, counter, ep, | |
3425 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3426 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3427 | ? "addiu" : "daddiu"), |
3428 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3429 | } | |
3430 | else | |
3431 | abort (); | |
3432 | } | |
3433 | ||
3434 | /* | |
3435 | * Build macros | |
3436 | * This routine implements the seemingly endless macro or synthesized | |
3437 | * instructions and addressing modes in the mips assembly language. Many | |
3438 | * of these macros are simple and are similar to each other. These could | |
3439 | * probably be handled by some kind of table or grammer aproach instead of | |
3440 | * this verbose method. Others are not simple macros but are more like | |
3441 | * optimizing code generation. | |
3442 | * One interesting optimization is when several store macros appear | |
3443 | * consecutivly that would load AT with the upper half of the same address. | |
3444 | * The ensuing load upper instructions are ommited. This implies some kind | |
3445 | * of global optimization. We currently only optimize within a single macro. | |
3446 | * For many of the load and store macros if the address is specified as a | |
3447 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3448 | * first load register 'at' with zero and use it as the base register. The | |
3449 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3450 | * we're missing. | |
3451 | */ | |
3452 | static void | |
3453 | macro (ip) | |
3454 | struct mips_cl_insn *ip; | |
3455 | { | |
3456 | register int treg, sreg, dreg, breg; | |
3457 | int tempreg; | |
3458 | int mask; | |
3459 | int icnt = 0; | |
43841e91 | 3460 | int used_at = 0; |
252b5132 RH |
3461 | expressionS expr1; |
3462 | const char *s; | |
3463 | const char *s2; | |
3464 | const char *fmt; | |
3465 | int likely = 0; | |
3466 | int dbl = 0; | |
3467 | int coproc = 0; | |
3468 | int lr = 0; | |
3469 | int imm = 0; | |
3470 | offsetT maxnum; | |
3471 | int off; | |
3472 | bfd_reloc_code_real_type r; | |
3473 | char *p; | |
3474 | int hold_mips_optimize; | |
3475 | ||
3476 | assert (! mips_opts.mips16); | |
3477 | ||
3478 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
3479 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3480 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3481 | mask = ip->insn_mo->mask; | |
3482 | ||
3483 | expr1.X_op = O_constant; | |
3484 | expr1.X_op_symbol = NULL; | |
3485 | expr1.X_add_symbol = NULL; | |
3486 | expr1.X_add_number = 1; | |
3487 | ||
3488 | switch (mask) | |
3489 | { | |
3490 | case M_DABS: | |
3491 | dbl = 1; | |
3492 | case M_ABS: | |
3493 | /* bgez $a0,.+12 | |
3494 | move v0,$a0 | |
3495 | sub v0,$zero,$a0 | |
3496 | */ | |
3497 | ||
3498 | mips_emit_delays (true); | |
3499 | ++mips_opts.noreorder; | |
3500 | mips_any_noreorder = 1; | |
3501 | ||
3502 | expr1.X_add_number = 8; | |
3503 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); | |
3504 | if (dreg == sreg) | |
3505 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3506 | else | |
3507 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); | |
3508 | macro_build ((char *) NULL, &icnt, NULL, | |
3509 | dbl ? "dsub" : "sub", | |
3510 | "d,v,t", dreg, 0, sreg); | |
3511 | ||
3512 | --mips_opts.noreorder; | |
3513 | return; | |
3514 | ||
3515 | case M_ADD_I: | |
3516 | s = "addi"; | |
3517 | s2 = "add"; | |
3518 | goto do_addi; | |
3519 | case M_ADDU_I: | |
3520 | s = "addiu"; | |
3521 | s2 = "addu"; | |
3522 | goto do_addi; | |
3523 | case M_DADD_I: | |
3524 | dbl = 1; | |
3525 | s = "daddi"; | |
3526 | s2 = "dadd"; | |
3527 | goto do_addi; | |
3528 | case M_DADDU_I: | |
3529 | dbl = 1; | |
3530 | s = "daddiu"; | |
3531 | s2 = "daddu"; | |
3532 | do_addi: | |
3533 | if (imm_expr.X_op == O_constant | |
3534 | && imm_expr.X_add_number >= -0x8000 | |
3535 | && imm_expr.X_add_number < 0x8000) | |
3536 | { | |
3537 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, | |
3538 | (int) BFD_RELOC_LO16); | |
3539 | return; | |
3540 | } | |
3541 | load_register (&icnt, AT, &imm_expr, dbl); | |
3542 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); | |
3543 | break; | |
3544 | ||
3545 | case M_AND_I: | |
3546 | s = "andi"; | |
3547 | s2 = "and"; | |
3548 | goto do_bit; | |
3549 | case M_OR_I: | |
3550 | s = "ori"; | |
3551 | s2 = "or"; | |
3552 | goto do_bit; | |
3553 | case M_NOR_I: | |
3554 | s = ""; | |
3555 | s2 = "nor"; | |
3556 | goto do_bit; | |
3557 | case M_XOR_I: | |
3558 | s = "xori"; | |
3559 | s2 = "xor"; | |
3560 | do_bit: | |
3561 | if (imm_expr.X_op == O_constant | |
3562 | && imm_expr.X_add_number >= 0 | |
3563 | && imm_expr.X_add_number < 0x10000) | |
3564 | { | |
3565 | if (mask != M_NOR_I) | |
3566 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, | |
3567 | sreg, (int) BFD_RELOC_LO16); | |
3568 | else | |
3569 | { | |
3570 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", | |
3571 | treg, sreg, (int) BFD_RELOC_LO16); | |
3572 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", | |
3573 | treg, treg, 0); | |
3574 | } | |
3575 | return; | |
3576 | } | |
3577 | ||
3578 | load_register (&icnt, AT, &imm_expr, 0); | |
3579 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); | |
3580 | break; | |
3581 | ||
3582 | case M_BEQ_I: | |
3583 | s = "beq"; | |
3584 | goto beq_i; | |
3585 | case M_BEQL_I: | |
3586 | s = "beql"; | |
3587 | likely = 1; | |
3588 | goto beq_i; | |
3589 | case M_BNE_I: | |
3590 | s = "bne"; | |
3591 | goto beq_i; | |
3592 | case M_BNEL_I: | |
3593 | s = "bnel"; | |
3594 | likely = 1; | |
3595 | beq_i: | |
3596 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3597 | { | |
3598 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, | |
3599 | 0); | |
3600 | return; | |
3601 | } | |
3602 | load_register (&icnt, AT, &imm_expr, 0); | |
3603 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); | |
3604 | break; | |
3605 | ||
3606 | case M_BGEL: | |
3607 | likely = 1; | |
3608 | case M_BGE: | |
3609 | if (treg == 0) | |
3610 | { | |
3611 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3612 | likely ? "bgezl" : "bgez", | |
3613 | "s,p", sreg); | |
3614 | return; | |
3615 | } | |
3616 | if (sreg == 0) | |
3617 | { | |
3618 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3619 | likely ? "blezl" : "blez", | |
3620 | "s,p", treg); | |
3621 | return; | |
3622 | } | |
3623 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); | |
3624 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3625 | likely ? "beql" : "beq", | |
3626 | "s,t,p", AT, 0); | |
3627 | break; | |
3628 | ||
3629 | case M_BGTL_I: | |
3630 | likely = 1; | |
3631 | case M_BGT_I: | |
3632 | /* check for > max integer */ | |
3633 | maxnum = 0x7fffffff; | |
9ce8a5dd | 3634 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4) |
252b5132 RH |
3635 | { |
3636 | maxnum <<= 16; | |
3637 | maxnum |= 0xffff; | |
3638 | maxnum <<= 16; | |
3639 | maxnum |= 0xffff; | |
3640 | } | |
3641 | if (imm_expr.X_op == O_constant | |
3642 | && imm_expr.X_add_number >= maxnum | |
9ce8a5dd | 3643 | && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4)) |
252b5132 RH |
3644 | { |
3645 | do_false: | |
3646 | /* result is always false */ | |
3647 | if (! likely) | |
3648 | { | |
3649 | as_warn (_("Branch %s is always false (nop)"), ip->insn_mo->name); | |
3650 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3651 | } | |
3652 | else | |
3653 | { | |
3654 | as_warn (_("Branch likely %s is always false"), ip->insn_mo->name); | |
3655 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", | |
3656 | "s,t,p", 0, 0); | |
3657 | } | |
3658 | return; | |
3659 | } | |
3660 | if (imm_expr.X_op != O_constant) | |
3661 | as_bad (_("Unsupported large constant")); | |
3662 | imm_expr.X_add_number++; | |
3663 | /* FALLTHROUGH */ | |
3664 | case M_BGE_I: | |
3665 | case M_BGEL_I: | |
3666 | if (mask == M_BGEL_I) | |
3667 | likely = 1; | |
3668 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3669 | { | |
3670 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3671 | likely ? "bgezl" : "bgez", | |
3672 | "s,p", sreg); | |
3673 | return; | |
3674 | } | |
3675 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
3676 | { | |
3677 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3678 | likely ? "bgtzl" : "bgtz", | |
3679 | "s,p", sreg); | |
3680 | return; | |
3681 | } | |
3682 | maxnum = 0x7fffffff; | |
9ce8a5dd | 3683 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4) |
252b5132 RH |
3684 | { |
3685 | maxnum <<= 16; | |
3686 | maxnum |= 0xffff; | |
3687 | maxnum <<= 16; | |
3688 | maxnum |= 0xffff; | |
3689 | } | |
3690 | maxnum = - maxnum - 1; | |
3691 | if (imm_expr.X_op == O_constant | |
3692 | && imm_expr.X_add_number <= maxnum | |
9ce8a5dd | 3693 | && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4)) |
252b5132 RH |
3694 | { |
3695 | do_true: | |
3696 | /* result is always true */ | |
3697 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
3698 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
3699 | return; | |
3700 | } | |
3701 | set_at (&icnt, sreg, 0); | |
3702 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3703 | likely ? "beql" : "beq", | |
3704 | "s,t,p", AT, 0); | |
3705 | break; | |
3706 | ||
3707 | case M_BGEUL: | |
3708 | likely = 1; | |
3709 | case M_BGEU: | |
3710 | if (treg == 0) | |
3711 | goto do_true; | |
3712 | if (sreg == 0) | |
3713 | { | |
3714 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3715 | likely ? "beql" : "beq", | |
3716 | "s,t,p", 0, treg); | |
3717 | return; | |
3718 | } | |
3719 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, | |
3720 | treg); | |
3721 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3722 | likely ? "beql" : "beq", | |
3723 | "s,t,p", AT, 0); | |
3724 | break; | |
3725 | ||
3726 | case M_BGTUL_I: | |
3727 | likely = 1; | |
3728 | case M_BGTU_I: | |
3729 | if (sreg == 0 | |
9ce8a5dd | 3730 | || (! ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 RH |
3731 | && imm_expr.X_op == O_constant |
3732 | && imm_expr.X_add_number == 0xffffffff)) | |
3733 | goto do_false; | |
3734 | if (imm_expr.X_op != O_constant) | |
3735 | as_bad (_("Unsupported large constant")); | |
3736 | imm_expr.X_add_number++; | |
3737 | /* FALLTHROUGH */ | |
3738 | case M_BGEU_I: | |
3739 | case M_BGEUL_I: | |
3740 | if (mask == M_BGEUL_I) | |
3741 | likely = 1; | |
3742 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3743 | goto do_true; | |
3744 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
3745 | { | |
3746 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3747 | likely ? "bnel" : "bne", | |
3748 | "s,t,p", sreg, 0); | |
3749 | return; | |
3750 | } | |
3751 | set_at (&icnt, sreg, 1); | |
3752 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3753 | likely ? "beql" : "beq", | |
3754 | "s,t,p", AT, 0); | |
3755 | break; | |
3756 | ||
3757 | case M_BGTL: | |
3758 | likely = 1; | |
3759 | case M_BGT: | |
3760 | if (treg == 0) | |
3761 | { | |
3762 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3763 | likely ? "bgtzl" : "bgtz", | |
3764 | "s,p", sreg); | |
3765 | return; | |
3766 | } | |
3767 | if (sreg == 0) | |
3768 | { | |
3769 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3770 | likely ? "bltzl" : "bltz", | |
3771 | "s,p", treg); | |
3772 | return; | |
3773 | } | |
3774 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); | |
3775 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3776 | likely ? "bnel" : "bne", | |
3777 | "s,t,p", AT, 0); | |
3778 | break; | |
3779 | ||
3780 | case M_BGTUL: | |
3781 | likely = 1; | |
3782 | case M_BGTU: | |
3783 | if (treg == 0) | |
3784 | { | |
3785 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3786 | likely ? "bnel" : "bne", | |
3787 | "s,t,p", sreg, 0); | |
3788 | return; | |
3789 | } | |
3790 | if (sreg == 0) | |
3791 | goto do_false; | |
3792 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, | |
3793 | sreg); | |
3794 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3795 | likely ? "bnel" : "bne", | |
3796 | "s,t,p", AT, 0); | |
3797 | break; | |
3798 | ||
3799 | case M_BLEL: | |
3800 | likely = 1; | |
3801 | case M_BLE: | |
3802 | if (treg == 0) | |
3803 | { | |
3804 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3805 | likely ? "blezl" : "blez", | |
3806 | "s,p", sreg); | |
3807 | return; | |
3808 | } | |
3809 | if (sreg == 0) | |
3810 | { | |
3811 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3812 | likely ? "bgezl" : "bgez", | |
3813 | "s,p", treg); | |
3814 | return; | |
3815 | } | |
3816 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); | |
3817 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3818 | likely ? "beql" : "beq", | |
3819 | "s,t,p", AT, 0); | |
3820 | break; | |
3821 | ||
3822 | case M_BLEL_I: | |
3823 | likely = 1; | |
3824 | case M_BLE_I: | |
3825 | maxnum = 0x7fffffff; | |
9ce8a5dd | 3826 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4) |
252b5132 RH |
3827 | { |
3828 | maxnum <<= 16; | |
3829 | maxnum |= 0xffff; | |
3830 | maxnum <<= 16; | |
3831 | maxnum |= 0xffff; | |
3832 | } | |
3833 | if (imm_expr.X_op == O_constant | |
3834 | && imm_expr.X_add_number >= maxnum | |
9ce8a5dd | 3835 | && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4)) |
252b5132 RH |
3836 | goto do_true; |
3837 | if (imm_expr.X_op != O_constant) | |
3838 | as_bad (_("Unsupported large constant")); | |
3839 | imm_expr.X_add_number++; | |
3840 | /* FALLTHROUGH */ | |
3841 | case M_BLT_I: | |
3842 | case M_BLTL_I: | |
3843 | if (mask == M_BLTL_I) | |
3844 | likely = 1; | |
3845 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3846 | { | |
3847 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3848 | likely ? "bltzl" : "bltz", | |
3849 | "s,p", sreg); | |
3850 | return; | |
3851 | } | |
3852 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
3853 | { | |
3854 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3855 | likely ? "blezl" : "blez", | |
3856 | "s,p", sreg); | |
3857 | return; | |
3858 | } | |
3859 | set_at (&icnt, sreg, 0); | |
3860 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3861 | likely ? "bnel" : "bne", | |
3862 | "s,t,p", AT, 0); | |
3863 | break; | |
3864 | ||
3865 | case M_BLEUL: | |
3866 | likely = 1; | |
3867 | case M_BLEU: | |
3868 | if (treg == 0) | |
3869 | { | |
3870 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3871 | likely ? "beql" : "beq", | |
3872 | "s,t,p", sreg, 0); | |
3873 | return; | |
3874 | } | |
3875 | if (sreg == 0) | |
3876 | goto do_true; | |
3877 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, | |
3878 | sreg); | |
3879 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3880 | likely ? "beql" : "beq", | |
3881 | "s,t,p", AT, 0); | |
3882 | break; | |
3883 | ||
3884 | case M_BLEUL_I: | |
3885 | likely = 1; | |
3886 | case M_BLEU_I: | |
3887 | if (sreg == 0 | |
9ce8a5dd | 3888 | || (! ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 RH |
3889 | && imm_expr.X_op == O_constant |
3890 | && imm_expr.X_add_number == 0xffffffff)) | |
3891 | goto do_true; | |
3892 | if (imm_expr.X_op != O_constant) | |
3893 | as_bad (_("Unsupported large constant")); | |
3894 | imm_expr.X_add_number++; | |
3895 | /* FALLTHROUGH */ | |
3896 | case M_BLTU_I: | |
3897 | case M_BLTUL_I: | |
3898 | if (mask == M_BLTUL_I) | |
3899 | likely = 1; | |
3900 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3901 | goto do_false; | |
3902 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
3903 | { | |
3904 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3905 | likely ? "beql" : "beq", | |
3906 | "s,t,p", sreg, 0); | |
3907 | return; | |
3908 | } | |
3909 | set_at (&icnt, sreg, 1); | |
3910 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3911 | likely ? "bnel" : "bne", | |
3912 | "s,t,p", AT, 0); | |
3913 | break; | |
3914 | ||
3915 | case M_BLTL: | |
3916 | likely = 1; | |
3917 | case M_BLT: | |
3918 | if (treg == 0) | |
3919 | { | |
3920 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3921 | likely ? "bltzl" : "bltz", | |
3922 | "s,p", sreg); | |
3923 | return; | |
3924 | } | |
3925 | if (sreg == 0) | |
3926 | { | |
3927 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3928 | likely ? "bgtzl" : "bgtz", | |
3929 | "s,p", treg); | |
3930 | return; | |
3931 | } | |
3932 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); | |
3933 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3934 | likely ? "bnel" : "bne", | |
3935 | "s,t,p", AT, 0); | |
3936 | break; | |
3937 | ||
3938 | case M_BLTUL: | |
3939 | likely = 1; | |
3940 | case M_BLTU: | |
3941 | if (treg == 0) | |
3942 | goto do_false; | |
3943 | if (sreg == 0) | |
3944 | { | |
3945 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3946 | likely ? "bnel" : "bne", | |
3947 | "s,t,p", 0, treg); | |
3948 | return; | |
3949 | } | |
3950 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, | |
3951 | treg); | |
3952 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3953 | likely ? "bnel" : "bne", | |
3954 | "s,t,p", AT, 0); | |
3955 | break; | |
3956 | ||
3957 | case M_DDIV_3: | |
3958 | dbl = 1; | |
3959 | case M_DIV_3: | |
3960 | s = "mflo"; | |
3961 | goto do_div3; | |
3962 | case M_DREM_3: | |
3963 | dbl = 1; | |
3964 | case M_REM_3: | |
3965 | s = "mfhi"; | |
3966 | do_div3: | |
3967 | if (treg == 0) | |
3968 | { | |
3969 | as_warn (_("Divide by zero.")); | |
3970 | if (mips_trap) | |
3971 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3972 | else | |
3973 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3974 | return; | |
3975 | } | |
3976 | ||
3977 | mips_emit_delays (true); | |
3978 | ++mips_opts.noreorder; | |
3979 | mips_any_noreorder = 1; | |
3980 | if (mips_trap) | |
3981 | { | |
3982 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3983 | macro_build ((char *) NULL, &icnt, NULL, | |
3984 | dbl ? "ddiv" : "div", | |
3985 | "z,s,t", sreg, treg); | |
3986 | } | |
3987 | else | |
3988 | { | |
3989 | expr1.X_add_number = 8; | |
3990 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3991 | macro_build ((char *) NULL, &icnt, NULL, | |
3992 | dbl ? "ddiv" : "div", | |
3993 | "z,s,t", sreg, treg); | |
3994 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3995 | } | |
3996 | expr1.X_add_number = -1; | |
3997 | macro_build ((char *) NULL, &icnt, &expr1, | |
3998 | dbl ? "daddiu" : "addiu", | |
3999 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); | |
4000 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
4001 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); | |
4002 | if (dbl) | |
4003 | { | |
4004 | expr1.X_add_number = 1; | |
4005 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, | |
4006 | (int) BFD_RELOC_LO16); | |
4007 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, | |
4008 | 31); | |
4009 | } | |
4010 | else | |
4011 | { | |
4012 | expr1.X_add_number = 0x80000000; | |
4013 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, | |
4014 | (int) BFD_RELOC_HI16); | |
4015 | } | |
4016 | if (mips_trap) | |
4017 | { | |
4018 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
4019 | /* We want to close the noreorder block as soon as possible, so | |
4020 | that later insns are available for delay slot filling. */ | |
4021 | --mips_opts.noreorder; | |
4022 | } | |
4023 | else | |
4024 | { | |
4025 | expr1.X_add_number = 8; | |
4026 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
4027 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
4028 | ||
4029 | /* We want to close the noreorder block as soon as possible, so | |
4030 | that later insns are available for delay slot filling. */ | |
4031 | --mips_opts.noreorder; | |
4032 | ||
4033 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
4034 | } | |
4035 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); | |
4036 | break; | |
4037 | ||
4038 | case M_DIV_3I: | |
4039 | s = "div"; | |
4040 | s2 = "mflo"; | |
4041 | goto do_divi; | |
4042 | case M_DIVU_3I: | |
4043 | s = "divu"; | |
4044 | s2 = "mflo"; | |
4045 | goto do_divi; | |
4046 | case M_REM_3I: | |
4047 | s = "div"; | |
4048 | s2 = "mfhi"; | |
4049 | goto do_divi; | |
4050 | case M_REMU_3I: | |
4051 | s = "divu"; | |
4052 | s2 = "mfhi"; | |
4053 | goto do_divi; | |
4054 | case M_DDIV_3I: | |
4055 | dbl = 1; | |
4056 | s = "ddiv"; | |
4057 | s2 = "mflo"; | |
4058 | goto do_divi; | |
4059 | case M_DDIVU_3I: | |
4060 | dbl = 1; | |
4061 | s = "ddivu"; | |
4062 | s2 = "mflo"; | |
4063 | goto do_divi; | |
4064 | case M_DREM_3I: | |
4065 | dbl = 1; | |
4066 | s = "ddiv"; | |
4067 | s2 = "mfhi"; | |
4068 | goto do_divi; | |
4069 | case M_DREMU_3I: | |
4070 | dbl = 1; | |
4071 | s = "ddivu"; | |
4072 | s2 = "mfhi"; | |
4073 | do_divi: | |
4074 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4075 | { | |
4076 | as_warn (_("Divide by zero.")); | |
4077 | if (mips_trap) | |
4078 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
4079 | else | |
4080 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
4081 | return; | |
4082 | } | |
4083 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4084 | { | |
4085 | if (strcmp (s2, "mflo") == 0) | |
4086 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, | |
4087 | sreg); | |
4088 | else | |
4089 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); | |
4090 | return; | |
4091 | } | |
4092 | if (imm_expr.X_op == O_constant | |
4093 | && imm_expr.X_add_number == -1 | |
4094 | && s[strlen (s) - 1] != 'u') | |
4095 | { | |
4096 | if (strcmp (s2, "mflo") == 0) | |
4097 | { | |
4098 | if (dbl) | |
4099 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, | |
4100 | sreg); | |
4101 | else | |
4102 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, | |
4103 | sreg); | |
4104 | } | |
4105 | else | |
4106 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); | |
4107 | return; | |
4108 | } | |
4109 | ||
4110 | load_register (&icnt, AT, &imm_expr, dbl); | |
4111 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); | |
4112 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
4113 | break; | |
4114 | ||
4115 | case M_DIVU_3: | |
4116 | s = "divu"; | |
4117 | s2 = "mflo"; | |
4118 | goto do_divu3; | |
4119 | case M_REMU_3: | |
4120 | s = "divu"; | |
4121 | s2 = "mfhi"; | |
4122 | goto do_divu3; | |
4123 | case M_DDIVU_3: | |
4124 | s = "ddivu"; | |
4125 | s2 = "mflo"; | |
4126 | goto do_divu3; | |
4127 | case M_DREMU_3: | |
4128 | s = "ddivu"; | |
4129 | s2 = "mfhi"; | |
4130 | do_divu3: | |
4131 | mips_emit_delays (true); | |
4132 | ++mips_opts.noreorder; | |
4133 | mips_any_noreorder = 1; | |
4134 | if (mips_trap) | |
4135 | { | |
4136 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
4137 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
4138 | /* We want to close the noreorder block as soon as possible, so | |
4139 | that later insns are available for delay slot filling. */ | |
4140 | --mips_opts.noreorder; | |
4141 | } | |
4142 | else | |
4143 | { | |
4144 | expr1.X_add_number = 8; | |
4145 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
4146 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
4147 | ||
4148 | /* We want to close the noreorder block as soon as possible, so | |
4149 | that later insns are available for delay slot filling. */ | |
4150 | --mips_opts.noreorder; | |
4151 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
4152 | } | |
4153 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
4154 | return; | |
4155 | ||
4156 | case M_DLA_AB: | |
4157 | dbl = 1; | |
4158 | case M_LA_AB: | |
4159 | /* Load the address of a symbol into a register. If breg is not | |
4160 | zero, we then add a base register to it. */ | |
4161 | ||
4162 | /* When generating embedded PIC code, we permit expressions of | |
4163 | the form | |
4164 | la $4,foo-bar | |
bb2d6cd7 | 4165 | where bar is an address in the current section. These are used |
252b5132 RH |
4166 | when getting the addresses of functions. We don't permit |
4167 | X_add_number to be non-zero, because if the symbol is | |
4168 | external the relaxing code needs to know that any addend is | |
4169 | purely the offset to X_op_symbol. */ | |
4170 | if (mips_pic == EMBEDDED_PIC | |
4171 | && offset_expr.X_op == O_subtract | |
49309057 | 4172 | && (symbol_constant_p (offset_expr.X_op_symbol) |
bb2d6cd7 | 4173 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg |
49309057 ILT |
4174 | : (symbol_equated_p (offset_expr.X_op_symbol) |
4175 | && (S_GET_SEGMENT | |
4176 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
4177 | ->X_add_symbol) | |
bb2d6cd7 | 4178 | == now_seg))) |
252b5132 | 4179 | && breg == 0 |
bb2d6cd7 GK |
4180 | && (offset_expr.X_add_number == 0 |
4181 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
252b5132 RH |
4182 | { |
4183 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4184 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
4185 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4186 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4187 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4188 | ? "addiu" : "daddiu"), |
4189 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); | |
4190 | return; | |
4191 | } | |
4192 | ||
4193 | if (offset_expr.X_op != O_symbol | |
4194 | && offset_expr.X_op != O_constant) | |
4195 | { | |
4196 | as_bad (_("expression too complex")); | |
4197 | offset_expr.X_op = O_constant; | |
4198 | } | |
4199 | ||
4200 | if (treg == breg) | |
4201 | { | |
4202 | tempreg = AT; | |
4203 | used_at = 1; | |
4204 | } | |
4205 | else | |
4206 | { | |
4207 | tempreg = treg; | |
4208 | used_at = 0; | |
4209 | } | |
4210 | ||
4211 | if (offset_expr.X_op == O_constant) | |
4212 | load_register (&icnt, tempreg, &offset_expr, dbl); | |
4213 | else if (mips_pic == NO_PIC) | |
4214 | { | |
4215 | /* If this is a reference to an GP relative symbol, we want | |
4216 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4217 | Otherwise we want | |
4218 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4219 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4220 | If we have a constant, we need two instructions anyhow, | |
4221 | so we may as well always use the latter form. */ | |
4222 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET | |
4223 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4224 | p = NULL; | |
4225 | else | |
4226 | { | |
4227 | frag_grow (20); | |
4228 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4229 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4230 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4231 | ? "addiu" : "daddiu"), |
4232 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4233 | p = frag_var (rs_machine_dependent, 8, 0, | |
4234 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
4235 | mips_opts.warn_about_macros), | |
4236 | offset_expr.X_add_symbol, (offsetT) 0, | |
4237 | (char *) NULL); | |
4238 | } | |
4239 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4240 | if (p != NULL) | |
4241 | p += 4; | |
4242 | macro_build (p, &icnt, &offset_expr, | |
4243 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4244 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4245 | ? "addiu" : "daddiu"), |
4246 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4247 | } | |
4248 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
4249 | { | |
4250 | /* If this is a reference to an external symbol, and there | |
4251 | is no constant, we want | |
4252 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4253 | For a local symbol, we want | |
4254 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4255 | nop | |
4256 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4257 | ||
4258 | If we have a small constant, and this is a reference to | |
4259 | an external symbol, we want | |
4260 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4261 | nop | |
4262 | addiu $tempreg,$tempreg,<constant> | |
4263 | For a local symbol, we want the same instruction | |
4264 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4265 | addiu instruction. | |
4266 | ||
4267 | If we have a large constant, and this is a reference to | |
4268 | an external symbol, we want | |
4269 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4270 | lui $at,<hiconstant> | |
4271 | addiu $at,$at,<loconstant> | |
4272 | addu $tempreg,$tempreg,$at | |
4273 | For a local symbol, we want the same instruction | |
4274 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4275 | addiu instruction. */ | |
4276 | expr1.X_add_number = offset_expr.X_add_number; | |
4277 | offset_expr.X_add_number = 0; | |
4278 | frag_grow (32); | |
4279 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4280 | dbl ? "ld" : "lw", | |
4281 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4282 | if (expr1.X_add_number == 0) | |
4283 | { | |
4284 | int off; | |
4285 | ||
4286 | if (breg == 0) | |
4287 | off = 0; | |
4288 | else | |
4289 | { | |
4290 | /* We're going to put in an addu instruction using | |
4291 | tempreg, so we may as well insert the nop right | |
4292 | now. */ | |
4293 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4294 | "nop", ""); | |
4295 | off = 4; | |
4296 | } | |
4297 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4298 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4299 | (breg == 0 | |
4300 | ? mips_opts.warn_about_macros | |
4301 | : 0)), | |
4302 | offset_expr.X_add_symbol, (offsetT) 0, | |
4303 | (char *) NULL); | |
4304 | if (breg == 0) | |
4305 | { | |
4306 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4307 | p += 4; | |
4308 | } | |
4309 | macro_build (p, &icnt, &expr1, | |
4310 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4311 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4312 | ? "addiu" : "daddiu"), |
4313 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4314 | /* FIXME: If breg == 0, and the next instruction uses | |
4315 | $tempreg, then if this variant case is used an extra | |
4316 | nop will be generated. */ | |
4317 | } | |
4318 | else if (expr1.X_add_number >= -0x8000 | |
4319 | && expr1.X_add_number < 0x8000) | |
4320 | { | |
4321 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4322 | "nop", ""); | |
4323 | macro_build ((char *) NULL, &icnt, &expr1, | |
4324 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4325 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4326 | ? "addiu" : "daddiu"), |
4327 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4328 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4329 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
4330 | offset_expr.X_add_symbol, (offsetT) 0, | |
4331 | (char *) NULL); | |
4332 | } | |
4333 | else | |
4334 | { | |
4335 | int off1; | |
4336 | ||
4337 | /* If we are going to add in a base register, and the | |
4338 | target register and the base register are the same, | |
4339 | then we are using AT as a temporary register. Since | |
4340 | we want to load the constant into AT, we add our | |
4341 | current AT (from the global offset table) and the | |
4342 | register into the register now, and pretend we were | |
4343 | not using a base register. */ | |
4344 | if (breg != treg) | |
4345 | off1 = 0; | |
4346 | else | |
4347 | { | |
4348 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4349 | "nop", ""); | |
4350 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4351 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4352 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4353 | ? "addu" : "daddu"), |
4354 | "d,v,t", treg, AT, breg); | |
4355 | breg = 0; | |
4356 | tempreg = treg; | |
4357 | off1 = -8; | |
4358 | } | |
4359 | ||
4360 | /* Set mips_optimize around the lui instruction to avoid | |
4361 | inserting an unnecessary nop after the lw. */ | |
4362 | hold_mips_optimize = mips_optimize; | |
4363 | mips_optimize = 2; | |
4364 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4365 | mips_optimize = hold_mips_optimize; | |
4366 | ||
4367 | macro_build ((char *) NULL, &icnt, &expr1, | |
4368 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4369 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4370 | ? "addiu" : "daddiu"), |
4371 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4372 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4373 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4374 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4375 | ? "addu" : "daddu"), |
4376 | "d,v,t", tempreg, tempreg, AT); | |
4377 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4378 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
4379 | offset_expr.X_add_symbol, (offsetT) 0, | |
4380 | (char *) NULL); | |
4381 | used_at = 1; | |
4382 | } | |
4383 | } | |
4384 | else if (mips_pic == SVR4_PIC) | |
4385 | { | |
4386 | int gpdel; | |
4387 | ||
4388 | /* This is the large GOT case. If this is a reference to an | |
4389 | external symbol, and there is no constant, we want | |
4390 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4391 | addu $tempreg,$tempreg,$gp | |
4392 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4393 | For a local symbol, we want | |
4394 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4395 | nop | |
4396 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4397 | ||
4398 | If we have a small constant, and this is a reference to | |
4399 | an external symbol, we want | |
4400 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4401 | addu $tempreg,$tempreg,$gp | |
4402 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4403 | nop | |
4404 | addiu $tempreg,$tempreg,<constant> | |
4405 | For a local symbol, we want | |
4406 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4407 | nop | |
4408 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4409 | ||
4410 | If we have a large constant, and this is a reference to | |
4411 | an external symbol, we want | |
4412 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4413 | addu $tempreg,$tempreg,$gp | |
4414 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4415 | lui $at,<hiconstant> | |
4416 | addiu $at,$at,<loconstant> | |
4417 | addu $tempreg,$tempreg,$at | |
4418 | For a local symbol, we want | |
4419 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4420 | lui $at,<hiconstant> | |
4421 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4422 | addu $tempreg,$tempreg,$at | |
4423 | */ | |
4424 | expr1.X_add_number = offset_expr.X_add_number; | |
4425 | offset_expr.X_add_number = 0; | |
4426 | frag_grow (52); | |
4427 | if (reg_needs_delay (GP)) | |
4428 | gpdel = 4; | |
4429 | else | |
4430 | gpdel = 0; | |
4431 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4432 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4433 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4434 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4435 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4436 | ? "addu" : "daddu"), |
4437 | "d,v,t", tempreg, tempreg, GP); | |
4438 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4439 | dbl ? "ld" : "lw", | |
4440 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
4441 | tempreg); | |
4442 | if (expr1.X_add_number == 0) | |
4443 | { | |
4444 | int off; | |
4445 | ||
4446 | if (breg == 0) | |
4447 | off = 0; | |
4448 | else | |
4449 | { | |
4450 | /* We're going to put in an addu instruction using | |
4451 | tempreg, so we may as well insert the nop right | |
4452 | now. */ | |
4453 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4454 | "nop", ""); | |
4455 | off = 4; | |
4456 | } | |
4457 | ||
4458 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4459 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
4460 | 8 + gpdel, 0, | |
4461 | (breg == 0 | |
4462 | ? mips_opts.warn_about_macros | |
4463 | : 0)), | |
4464 | offset_expr.X_add_symbol, (offsetT) 0, | |
4465 | (char *) NULL); | |
4466 | } | |
4467 | else if (expr1.X_add_number >= -0x8000 | |
4468 | && expr1.X_add_number < 0x8000) | |
4469 | { | |
4470 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4471 | "nop", ""); | |
4472 | macro_build ((char *) NULL, &icnt, &expr1, | |
4473 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4474 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4475 | ? "addiu" : "daddiu"), |
4476 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4477 | ||
4478 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4479 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4480 | (breg == 0 | |
4481 | ? mips_opts.warn_about_macros | |
4482 | : 0)), | |
4483 | offset_expr.X_add_symbol, (offsetT) 0, | |
4484 | (char *) NULL); | |
4485 | } | |
4486 | else | |
4487 | { | |
4488 | int adj, dreg; | |
4489 | ||
4490 | /* If we are going to add in a base register, and the | |
4491 | target register and the base register are the same, | |
4492 | then we are using AT as a temporary register. Since | |
4493 | we want to load the constant into AT, we add our | |
4494 | current AT (from the global offset table) and the | |
4495 | register into the register now, and pretend we were | |
4496 | not using a base register. */ | |
4497 | if (breg != treg) | |
4498 | { | |
4499 | adj = 0; | |
4500 | dreg = tempreg; | |
4501 | } | |
4502 | else | |
4503 | { | |
4504 | assert (tempreg == AT); | |
4505 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4506 | "nop", ""); | |
4507 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4508 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4509 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4510 | ? "addu" : "daddu"), |
4511 | "d,v,t", treg, AT, breg); | |
4512 | dreg = treg; | |
4513 | adj = 8; | |
4514 | } | |
4515 | ||
4516 | /* Set mips_optimize around the lui instruction to avoid | |
4517 | inserting an unnecessary nop after the lw. */ | |
4518 | hold_mips_optimize = mips_optimize; | |
4519 | mips_optimize = 2; | |
4520 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4521 | mips_optimize = hold_mips_optimize; | |
4522 | ||
4523 | macro_build ((char *) NULL, &icnt, &expr1, | |
4524 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4525 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4526 | ? "addiu" : "daddiu"), |
4527 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4528 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4529 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4530 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4531 | ? "addu" : "daddu"), |
4532 | "d,v,t", dreg, dreg, AT); | |
4533 | ||
4534 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4535 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4536 | 8 + gpdel, 0, | |
4537 | (breg == 0 | |
4538 | ? mips_opts.warn_about_macros | |
4539 | : 0)), | |
4540 | offset_expr.X_add_symbol, (offsetT) 0, | |
4541 | (char *) NULL); | |
4542 | ||
4543 | used_at = 1; | |
4544 | } | |
4545 | ||
4546 | if (gpdel > 0) | |
4547 | { | |
4548 | /* This is needed because this instruction uses $gp, but | |
4549 | the first instruction on the main stream does not. */ | |
4550 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4551 | p += 4; | |
4552 | } | |
4553 | macro_build (p, &icnt, &offset_expr, | |
4554 | dbl ? "ld" : "lw", | |
4555 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4556 | p += 4; | |
4557 | if (expr1.X_add_number >= -0x8000 | |
4558 | && expr1.X_add_number < 0x8000) | |
4559 | { | |
4560 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4561 | p += 4; | |
4562 | macro_build (p, &icnt, &expr1, | |
4563 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4564 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4565 | ? "addiu" : "daddiu"), |
4566 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4567 | /* FIXME: If add_number is 0, and there was no base | |
4568 | register, the external symbol case ended with a load, | |
4569 | so if the symbol turns out to not be external, and | |
4570 | the next instruction uses tempreg, an unnecessary nop | |
4571 | will be inserted. */ | |
4572 | } | |
4573 | else | |
4574 | { | |
4575 | if (breg == treg) | |
4576 | { | |
4577 | /* We must add in the base register now, as in the | |
4578 | external symbol case. */ | |
4579 | assert (tempreg == AT); | |
4580 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4581 | p += 4; | |
4582 | macro_build (p, &icnt, (expressionS *) NULL, | |
4583 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4584 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4585 | ? "addu" : "daddu"), |
4586 | "d,v,t", treg, AT, breg); | |
4587 | p += 4; | |
4588 | tempreg = treg; | |
4589 | /* We set breg to 0 because we have arranged to add | |
4590 | it in in both cases. */ | |
4591 | breg = 0; | |
4592 | } | |
4593 | ||
4594 | macro_build_lui (p, &icnt, &expr1, AT); | |
4595 | p += 4; | |
4596 | macro_build (p, &icnt, &expr1, | |
4597 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4598 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4599 | ? "addiu" : "daddiu"), |
4600 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4601 | p += 4; | |
4602 | macro_build (p, &icnt, (expressionS *) NULL, | |
4603 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4604 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4605 | ? "addu" : "daddu"), |
4606 | "d,v,t", tempreg, tempreg, AT); | |
4607 | p += 4; | |
4608 | } | |
4609 | } | |
4610 | else if (mips_pic == EMBEDDED_PIC) | |
4611 | { | |
4612 | /* We use | |
4613 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4614 | */ | |
4615 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4616 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4617 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4618 | ? "addiu" : "daddiu"), |
4619 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4620 | } | |
4621 | else | |
4622 | abort (); | |
4623 | ||
4624 | if (breg != 0) | |
4625 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4626 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4627 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4628 | ? "addu" : "daddu"), |
4629 | "d,v,t", treg, tempreg, breg); | |
4630 | ||
4631 | if (! used_at) | |
4632 | return; | |
4633 | ||
4634 | break; | |
4635 | ||
4636 | case M_J_A: | |
4637 | /* The j instruction may not be used in PIC code, since it | |
4638 | requires an absolute address. We convert it to a b | |
4639 | instruction. */ | |
4640 | if (mips_pic == NO_PIC) | |
4641 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); | |
4642 | else | |
4643 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
4644 | return; | |
4645 | ||
4646 | /* The jal instructions must be handled as macros because when | |
4647 | generating PIC code they expand to multi-instruction | |
4648 | sequences. Normally they are simple instructions. */ | |
4649 | case M_JAL_1: | |
4650 | dreg = RA; | |
4651 | /* Fall through. */ | |
4652 | case M_JAL_2: | |
4653 | if (mips_pic == NO_PIC | |
4654 | || mips_pic == EMBEDDED_PIC) | |
4655 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4656 | "d,s", dreg, sreg); | |
4657 | else if (mips_pic == SVR4_PIC) | |
4658 | { | |
4659 | if (sreg != PIC_CALL_REG) | |
4660 | as_warn (_("MIPS PIC call to register other than $25")); | |
4661 | ||
4662 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4663 | "d,s", dreg, sreg); | |
4664 | if (mips_cprestore_offset < 0) | |
4665 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
4666 | else | |
4667 | { | |
4668 | expr1.X_add_number = mips_cprestore_offset; | |
4669 | macro_build ((char *) NULL, &icnt, &expr1, | |
4670 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4671 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4672 | ? "lw" : "ld"), |
4673 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
4674 | } | |
4675 | } | |
4676 | else | |
4677 | abort (); | |
4678 | ||
4679 | return; | |
4680 | ||
4681 | case M_JAL_A: | |
4682 | if (mips_pic == NO_PIC) | |
4683 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4684 | else if (mips_pic == SVR4_PIC) | |
4685 | { | |
4686 | /* If this is a reference to an external symbol, and we are | |
4687 | using a small GOT, we want | |
4688 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
4689 | nop | |
4690 | jalr $25 | |
4691 | nop | |
4692 | lw $gp,cprestore($sp) | |
4693 | The cprestore value is set using the .cprestore | |
4694 | pseudo-op. If we are using a big GOT, we want | |
4695 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4696 | addu $25,$25,$gp | |
4697 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4698 | nop | |
4699 | jalr $25 | |
4700 | nop | |
4701 | lw $gp,cprestore($sp) | |
4702 | If the symbol is not external, we want | |
4703 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4704 | nop | |
4705 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4706 | jalr $25 | |
4707 | nop | |
4708 | lw $gp,cprestore($sp) */ | |
4709 | frag_grow (40); | |
4710 | if (! mips_big_got) | |
4711 | { | |
4712 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4713 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4714 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4715 | ? "lw" : "ld"), |
4716 | "t,o(b)", PIC_CALL_REG, | |
4717 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4718 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4719 | "nop", ""); | |
4720 | p = frag_var (rs_machine_dependent, 4, 0, | |
4721 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
4722 | offset_expr.X_add_symbol, (offsetT) 0, | |
4723 | (char *) NULL); | |
4724 | } | |
4725 | else | |
4726 | { | |
4727 | int gpdel; | |
4728 | ||
4729 | if (reg_needs_delay (GP)) | |
4730 | gpdel = 4; | |
4731 | else | |
4732 | gpdel = 0; | |
4733 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4734 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4735 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4736 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4737 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4738 | ? "addu" : "daddu"), |
4739 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); | |
4740 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4741 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4742 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4743 | ? "lw" : "ld"), |
4744 | "t,o(b)", PIC_CALL_REG, | |
4745 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4746 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4747 | "nop", ""); | |
4748 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4749 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4750 | 0, 0), | |
4751 | offset_expr.X_add_symbol, (offsetT) 0, | |
4752 | (char *) NULL); | |
4753 | if (gpdel > 0) | |
4754 | { | |
4755 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4756 | p += 4; | |
4757 | } | |
4758 | macro_build (p, &icnt, &offset_expr, | |
4759 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4760 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4761 | ? "lw" : "ld"), |
4762 | "t,o(b)", PIC_CALL_REG, | |
4763 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4764 | p += 4; | |
4765 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4766 | p += 4; | |
4767 | } | |
4768 | macro_build (p, &icnt, &offset_expr, | |
4769 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4770 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4771 | ? "addiu" : "daddiu"), |
4772 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
4773 | (int) BFD_RELOC_LO16); | |
4774 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4775 | "jalr", "s", PIC_CALL_REG); | |
4776 | if (mips_cprestore_offset < 0) | |
4777 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
4778 | else | |
4779 | { | |
4780 | if (mips_opts.noreorder) | |
4781 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4782 | "nop", ""); | |
4783 | expr1.X_add_number = mips_cprestore_offset; | |
4784 | macro_build ((char *) NULL, &icnt, &expr1, | |
4785 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4786 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4787 | ? "lw" : "ld"), |
4788 | "t,o(b)", GP, (int) BFD_RELOC_LO16, | |
4789 | mips_frame_reg); | |
4790 | } | |
4791 | } | |
4792 | else if (mips_pic == EMBEDDED_PIC) | |
4793 | { | |
4794 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4795 | /* The linker may expand the call to a longer sequence which | |
4796 | uses $at, so we must break rather than return. */ | |
4797 | break; | |
4798 | } | |
4799 | else | |
4800 | abort (); | |
4801 | ||
4802 | return; | |
4803 | ||
4804 | case M_LB_AB: | |
4805 | s = "lb"; | |
4806 | goto ld; | |
4807 | case M_LBU_AB: | |
4808 | s = "lbu"; | |
4809 | goto ld; | |
4810 | case M_LH_AB: | |
4811 | s = "lh"; | |
4812 | goto ld; | |
4813 | case M_LHU_AB: | |
4814 | s = "lhu"; | |
4815 | goto ld; | |
4816 | case M_LW_AB: | |
4817 | s = "lw"; | |
4818 | goto ld; | |
4819 | case M_LWC0_AB: | |
4820 | s = "lwc0"; | |
4821 | /* Itbl support may require additional care here. */ | |
4822 | coproc = 1; | |
4823 | goto ld; | |
4824 | case M_LWC1_AB: | |
4825 | s = "lwc1"; | |
4826 | /* Itbl support may require additional care here. */ | |
4827 | coproc = 1; | |
4828 | goto ld; | |
4829 | case M_LWC2_AB: | |
4830 | s = "lwc2"; | |
4831 | /* Itbl support may require additional care here. */ | |
4832 | coproc = 1; | |
4833 | goto ld; | |
4834 | case M_LWC3_AB: | |
4835 | s = "lwc3"; | |
4836 | /* Itbl support may require additional care here. */ | |
4837 | coproc = 1; | |
4838 | goto ld; | |
4839 | case M_LWL_AB: | |
4840 | s = "lwl"; | |
4841 | lr = 1; | |
4842 | goto ld; | |
4843 | case M_LWR_AB: | |
4844 | s = "lwr"; | |
4845 | lr = 1; | |
4846 | goto ld; | |
4847 | case M_LDC1_AB: | |
4848 | if (mips_cpu == 4650) | |
4849 | { | |
4850 | as_bad (_("opcode not supported on this processor")); | |
4851 | return; | |
4852 | } | |
4853 | s = "ldc1"; | |
4854 | /* Itbl support may require additional care here. */ | |
4855 | coproc = 1; | |
4856 | goto ld; | |
4857 | case M_LDC2_AB: | |
4858 | s = "ldc2"; | |
4859 | /* Itbl support may require additional care here. */ | |
4860 | coproc = 1; | |
4861 | goto ld; | |
4862 | case M_LDC3_AB: | |
4863 | s = "ldc3"; | |
4864 | /* Itbl support may require additional care here. */ | |
4865 | coproc = 1; | |
4866 | goto ld; | |
4867 | case M_LDL_AB: | |
4868 | s = "ldl"; | |
4869 | lr = 1; | |
4870 | goto ld; | |
4871 | case M_LDR_AB: | |
4872 | s = "ldr"; | |
4873 | lr = 1; | |
4874 | goto ld; | |
4875 | case M_LL_AB: | |
4876 | s = "ll"; | |
4877 | goto ld; | |
4878 | case M_LLD_AB: | |
4879 | s = "lld"; | |
4880 | goto ld; | |
4881 | case M_LWU_AB: | |
4882 | s = "lwu"; | |
4883 | ld: | |
4884 | if (breg == treg || coproc || lr) | |
4885 | { | |
4886 | tempreg = AT; | |
4887 | used_at = 1; | |
4888 | } | |
4889 | else | |
4890 | { | |
4891 | tempreg = treg; | |
4892 | used_at = 0; | |
4893 | } | |
4894 | goto ld_st; | |
4895 | case M_SB_AB: | |
4896 | s = "sb"; | |
4897 | goto st; | |
4898 | case M_SH_AB: | |
4899 | s = "sh"; | |
4900 | goto st; | |
4901 | case M_SW_AB: | |
4902 | s = "sw"; | |
4903 | goto st; | |
4904 | case M_SWC0_AB: | |
4905 | s = "swc0"; | |
4906 | /* Itbl support may require additional care here. */ | |
4907 | coproc = 1; | |
4908 | goto st; | |
4909 | case M_SWC1_AB: | |
4910 | s = "swc1"; | |
4911 | /* Itbl support may require additional care here. */ | |
4912 | coproc = 1; | |
4913 | goto st; | |
4914 | case M_SWC2_AB: | |
4915 | s = "swc2"; | |
4916 | /* Itbl support may require additional care here. */ | |
4917 | coproc = 1; | |
4918 | goto st; | |
4919 | case M_SWC3_AB: | |
4920 | s = "swc3"; | |
4921 | /* Itbl support may require additional care here. */ | |
4922 | coproc = 1; | |
4923 | goto st; | |
4924 | case M_SWL_AB: | |
4925 | s = "swl"; | |
4926 | goto st; | |
4927 | case M_SWR_AB: | |
4928 | s = "swr"; | |
4929 | goto st; | |
4930 | case M_SC_AB: | |
4931 | s = "sc"; | |
4932 | goto st; | |
4933 | case M_SCD_AB: | |
4934 | s = "scd"; | |
4935 | goto st; | |
4936 | case M_SDC1_AB: | |
4937 | if (mips_cpu == 4650) | |
4938 | { | |
4939 | as_bad (_("opcode not supported on this processor")); | |
4940 | return; | |
4941 | } | |
4942 | s = "sdc1"; | |
4943 | coproc = 1; | |
4944 | /* Itbl support may require additional care here. */ | |
4945 | goto st; | |
4946 | case M_SDC2_AB: | |
4947 | s = "sdc2"; | |
4948 | /* Itbl support may require additional care here. */ | |
4949 | coproc = 1; | |
4950 | goto st; | |
4951 | case M_SDC3_AB: | |
4952 | s = "sdc3"; | |
4953 | /* Itbl support may require additional care here. */ | |
4954 | coproc = 1; | |
4955 | goto st; | |
4956 | case M_SDL_AB: | |
4957 | s = "sdl"; | |
4958 | goto st; | |
4959 | case M_SDR_AB: | |
4960 | s = "sdr"; | |
4961 | st: | |
4962 | tempreg = AT; | |
4963 | used_at = 1; | |
4964 | ld_st: | |
4965 | /* Itbl support may require additional care here. */ | |
4966 | if (mask == M_LWC1_AB | |
4967 | || mask == M_SWC1_AB | |
4968 | || mask == M_LDC1_AB | |
4969 | || mask == M_SDC1_AB | |
4970 | || mask == M_L_DAB | |
4971 | || mask == M_S_DAB) | |
4972 | fmt = "T,o(b)"; | |
4973 | else if (coproc) | |
4974 | fmt = "E,o(b)"; | |
4975 | else | |
4976 | fmt = "t,o(b)"; | |
4977 | ||
4978 | if (offset_expr.X_op != O_constant | |
4979 | && offset_expr.X_op != O_symbol) | |
4980 | { | |
4981 | as_bad (_("expression too complex")); | |
4982 | offset_expr.X_op = O_constant; | |
4983 | } | |
4984 | ||
4985 | /* A constant expression in PIC code can be handled just as it | |
4986 | is in non PIC code. */ | |
4987 | if (mips_pic == NO_PIC | |
4988 | || offset_expr.X_op == O_constant) | |
4989 | { | |
4990 | /* If this is a reference to a GP relative symbol, and there | |
4991 | is no base register, we want | |
4992 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4993 | Otherwise, if there is no base register, we want | |
4994 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4995 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4996 | If we have a constant, we need two instructions anyhow, | |
4997 | so we always use the latter form. | |
4998 | ||
4999 | If we have a base register, and this is a reference to a | |
5000 | GP relative symbol, we want | |
5001 | addu $tempreg,$breg,$gp | |
5002 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
5003 | Otherwise we want | |
5004 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5005 | addu $tempreg,$tempreg,$breg | |
5006 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5007 | With a constant we always use the latter case. */ | |
5008 | if (breg == 0) | |
5009 | { | |
5010 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET | |
5011 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5012 | p = NULL; | |
5013 | else | |
5014 | { | |
5015 | frag_grow (20); | |
5016 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5017 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
5018 | p = frag_var (rs_machine_dependent, 8, 0, | |
5019 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
5020 | (mips_opts.warn_about_macros | |
5021 | || (used_at | |
5022 | && mips_opts.noat))), | |
5023 | offset_expr.X_add_symbol, (offsetT) 0, | |
5024 | (char *) NULL); | |
5025 | used_at = 0; | |
5026 | } | |
5027 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5028 | if (p != NULL) | |
5029 | p += 4; | |
5030 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5031 | (int) BFD_RELOC_LO16, tempreg); | |
5032 | } | |
5033 | else | |
5034 | { | |
5035 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET | |
5036 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5037 | p = NULL; | |
5038 | else | |
5039 | { | |
5040 | frag_grow (28); | |
5041 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5042 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5043 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5044 | ? "addu" : "daddu"), |
5045 | "d,v,t", tempreg, breg, GP); | |
5046 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5047 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5048 | p = frag_var (rs_machine_dependent, 12, 0, | |
5049 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
5050 | offset_expr.X_add_symbol, (offsetT) 0, | |
5051 | (char *) NULL); | |
5052 | } | |
5053 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5054 | if (p != NULL) | |
5055 | p += 4; | |
5056 | macro_build (p, &icnt, (expressionS *) NULL, | |
5057 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5058 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5059 | ? "addu" : "daddu"), |
5060 | "d,v,t", tempreg, tempreg, breg); | |
5061 | if (p != NULL) | |
5062 | p += 4; | |
5063 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5064 | (int) BFD_RELOC_LO16, tempreg); | |
5065 | } | |
5066 | } | |
5067 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
5068 | { | |
5069 | /* If this is a reference to an external symbol, we want | |
5070 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5071 | nop | |
5072 | <op> $treg,0($tempreg) | |
5073 | Otherwise we want | |
5074 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5075 | nop | |
5076 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5077 | <op> $treg,0($tempreg) | |
5078 | If there is a base register, we add it to $tempreg before | |
5079 | the <op>. If there is a constant, we stick it in the | |
5080 | <op> instruction. We don't handle constants larger than | |
5081 | 16 bits, because we have no way to load the upper 16 bits | |
5082 | (actually, we could handle them for the subset of cases | |
5083 | in which we are not using $at). */ | |
5084 | assert (offset_expr.X_op == O_symbol); | |
5085 | expr1.X_add_number = offset_expr.X_add_number; | |
5086 | offset_expr.X_add_number = 0; | |
5087 | if (expr1.X_add_number < -0x8000 | |
5088 | || expr1.X_add_number >= 0x8000) | |
5089 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5090 | frag_grow (20); | |
5091 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5092 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5093 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5094 | ? "lw" : "ld"), |
5095 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5096 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5097 | p = frag_var (rs_machine_dependent, 4, 0, | |
5098 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
5099 | offset_expr.X_add_symbol, (offsetT) 0, | |
5100 | (char *) NULL); | |
5101 | macro_build (p, &icnt, &offset_expr, | |
5102 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5103 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5104 | ? "addiu" : "daddiu"), |
5105 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
5106 | if (breg != 0) | |
5107 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5108 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5109 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5110 | ? "addu" : "daddu"), |
5111 | "d,v,t", tempreg, tempreg, breg); | |
5112 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5113 | (int) BFD_RELOC_LO16, tempreg); | |
5114 | } | |
5115 | else if (mips_pic == SVR4_PIC) | |
5116 | { | |
5117 | int gpdel; | |
5118 | ||
5119 | /* If this is a reference to an external symbol, we want | |
5120 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5121 | addu $tempreg,$tempreg,$gp | |
5122 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5123 | <op> $treg,0($tempreg) | |
5124 | Otherwise we want | |
5125 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5126 | nop | |
5127 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5128 | <op> $treg,0($tempreg) | |
5129 | If there is a base register, we add it to $tempreg before | |
5130 | the <op>. If there is a constant, we stick it in the | |
5131 | <op> instruction. We don't handle constants larger than | |
5132 | 16 bits, because we have no way to load the upper 16 bits | |
5133 | (actually, we could handle them for the subset of cases | |
5134 | in which we are not using $at). */ | |
5135 | assert (offset_expr.X_op == O_symbol); | |
5136 | expr1.X_add_number = offset_expr.X_add_number; | |
5137 | offset_expr.X_add_number = 0; | |
5138 | if (expr1.X_add_number < -0x8000 | |
5139 | || expr1.X_add_number >= 0x8000) | |
5140 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5141 | if (reg_needs_delay (GP)) | |
5142 | gpdel = 4; | |
5143 | else | |
5144 | gpdel = 0; | |
5145 | frag_grow (36); | |
5146 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5147 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5148 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5149 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5150 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5151 | ? "addu" : "daddu"), |
5152 | "d,v,t", tempreg, tempreg, GP); | |
5153 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5154 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5155 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5156 | ? "lw" : "ld"), |
5157 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
5158 | tempreg); | |
5159 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5160 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
5161 | offset_expr.X_add_symbol, (offsetT) 0, (char *) NULL); | |
5162 | if (gpdel > 0) | |
5163 | { | |
5164 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5165 | p += 4; | |
5166 | } | |
5167 | macro_build (p, &icnt, &offset_expr, | |
5168 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5169 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5170 | ? "lw" : "ld"), |
5171 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5172 | p += 4; | |
5173 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5174 | p += 4; | |
5175 | macro_build (p, &icnt, &offset_expr, | |
5176 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5177 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5178 | ? "addiu" : "daddiu"), |
5179 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
5180 | if (breg != 0) | |
5181 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5182 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5183 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5184 | ? "addu" : "daddu"), |
5185 | "d,v,t", tempreg, tempreg, breg); | |
5186 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5187 | (int) BFD_RELOC_LO16, tempreg); | |
5188 | } | |
5189 | else if (mips_pic == EMBEDDED_PIC) | |
5190 | { | |
5191 | /* If there is no base register, we want | |
5192 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5193 | If there is a base register, we want | |
5194 | addu $tempreg,$breg,$gp | |
5195 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
5196 | */ | |
5197 | assert (offset_expr.X_op == O_symbol); | |
5198 | if (breg == 0) | |
5199 | { | |
5200 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5201 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
5202 | used_at = 0; | |
5203 | } | |
5204 | else | |
5205 | { | |
5206 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5207 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5208 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5209 | ? "addu" : "daddu"), |
5210 | "d,v,t", tempreg, breg, GP); | |
5211 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5212 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5213 | } | |
5214 | } | |
5215 | else | |
5216 | abort (); | |
5217 | ||
5218 | if (! used_at) | |
5219 | return; | |
5220 | ||
5221 | break; | |
5222 | ||
5223 | case M_LI: | |
5224 | case M_LI_S: | |
5225 | load_register (&icnt, treg, &imm_expr, 0); | |
5226 | return; | |
5227 | ||
5228 | case M_DLI: | |
5229 | load_register (&icnt, treg, &imm_expr, 1); | |
5230 | return; | |
5231 | ||
5232 | case M_LI_SS: | |
5233 | if (imm_expr.X_op == O_constant) | |
5234 | { | |
5235 | load_register (&icnt, AT, &imm_expr, 0); | |
5236 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5237 | "mtc1", "t,G", AT, treg); | |
5238 | break; | |
5239 | } | |
5240 | else | |
5241 | { | |
5242 | assert (offset_expr.X_op == O_symbol | |
5243 | && strcmp (segment_name (S_GET_SEGMENT | |
5244 | (offset_expr.X_add_symbol)), | |
5245 | ".lit4") == 0 | |
5246 | && offset_expr.X_add_number == 0); | |
5247 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
5248 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5249 | return; | |
5250 | } | |
5251 | ||
5252 | case M_LI_D: | |
5253 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is | |
5254 | the entire value, and in mips1 mode it is the high order 32 | |
5255 | bits of the value and the low order 32 bits are either zero | |
5256 | or in offset_expr. */ | |
5257 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5258 | { | |
9ce8a5dd | 5259 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5260 | load_register (&icnt, treg, &imm_expr, 1); |
5261 | else | |
5262 | { | |
5263 | int hreg, lreg; | |
5264 | ||
5265 | if (target_big_endian) | |
5266 | { | |
5267 | hreg = treg; | |
5268 | lreg = treg + 1; | |
5269 | } | |
5270 | else | |
5271 | { | |
5272 | hreg = treg + 1; | |
5273 | lreg = treg; | |
5274 | } | |
5275 | ||
5276 | if (hreg <= 31) | |
5277 | load_register (&icnt, hreg, &imm_expr, 0); | |
5278 | if (lreg <= 31) | |
5279 | { | |
5280 | if (offset_expr.X_op == O_absent) | |
5281 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", | |
5282 | lreg, 0); | |
5283 | else | |
5284 | { | |
5285 | assert (offset_expr.X_op == O_constant); | |
5286 | load_register (&icnt, lreg, &offset_expr, 0); | |
5287 | } | |
5288 | } | |
5289 | } | |
5290 | return; | |
5291 | } | |
5292 | ||
5293 | /* We know that sym is in the .rdata section. First we get the | |
5294 | upper 16 bits of the address. */ | |
5295 | if (mips_pic == NO_PIC) | |
5296 | { | |
5297 | /* FIXME: This won't work for a 64 bit address. */ | |
5298 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5299 | } | |
5300 | else if (mips_pic == SVR4_PIC) | |
5301 | { | |
5302 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5303 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5304 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5305 | ? "lw" : "ld"), |
5306 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5307 | } | |
5308 | else if (mips_pic == EMBEDDED_PIC) | |
5309 | { | |
5310 | /* For embedded PIC we pick up the entire address off $gp in | |
5311 | a single instruction. */ | |
5312 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5313 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5314 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5315 | ? "addiu" : "daddiu"), |
5316 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); | |
5317 | offset_expr.X_op = O_constant; | |
5318 | offset_expr.X_add_number = 0; | |
5319 | } | |
5320 | else | |
5321 | abort (); | |
5322 | ||
5323 | /* Now we load the register(s). */ | |
9ce8a5dd | 5324 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5325 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
5326 | treg, (int) BFD_RELOC_LO16, AT); | |
5327 | else | |
5328 | { | |
5329 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5330 | treg, (int) BFD_RELOC_LO16, AT); | |
5331 | if (treg != 31) | |
5332 | { | |
5333 | /* FIXME: How in the world do we deal with the possible | |
5334 | overflow here? */ | |
5335 | offset_expr.X_add_number += 4; | |
5336 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5337 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
5338 | } | |
5339 | } | |
5340 | ||
5341 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5342 | does not become a variant frag. */ | |
5343 | frag_wane (frag_now); | |
5344 | frag_new (0); | |
5345 | ||
5346 | break; | |
5347 | ||
5348 | case M_LI_DD: | |
5349 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is | |
5350 | the entire value, and in mips1 mode it is the high order 32 | |
5351 | bits of the value and the low order 32 bits are either zero | |
5352 | or in offset_expr. */ | |
5353 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5354 | { | |
9ce8a5dd GRK |
5355 | load_register (&icnt, AT, &imm_expr, ISA_HAS_64BIT_REGS (mips_opts.isa)); |
5356 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
252b5132 RH |
5357 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
5358 | "dmtc1", "t,S", AT, treg); | |
5359 | else | |
5360 | { | |
5361 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5362 | "mtc1", "t,G", AT, treg + 1); | |
5363 | if (offset_expr.X_op == O_absent) | |
5364 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5365 | "mtc1", "t,G", 0, treg); | |
5366 | else | |
5367 | { | |
5368 | assert (offset_expr.X_op == O_constant); | |
5369 | load_register (&icnt, AT, &offset_expr, 0); | |
5370 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5371 | "mtc1", "t,G", AT, treg); | |
5372 | } | |
5373 | } | |
5374 | break; | |
5375 | } | |
5376 | ||
5377 | assert (offset_expr.X_op == O_symbol | |
5378 | && offset_expr.X_add_number == 0); | |
5379 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
5380 | if (strcmp (s, ".lit8") == 0) | |
5381 | { | |
9ce8a5dd | 5382 | if (mips_opts.isa != 1) |
252b5132 RH |
5383 | { |
5384 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5385 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5386 | return; | |
5387 | } | |
5388 | breg = GP; | |
5389 | r = BFD_RELOC_MIPS_LITERAL; | |
5390 | goto dob; | |
5391 | } | |
5392 | else | |
5393 | { | |
5394 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
5395 | if (mips_pic == SVR4_PIC) | |
5396 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5397 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5398 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5399 | ? "lw" : "ld"), |
5400 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5401 | else | |
5402 | { | |
5403 | /* FIXME: This won't work for a 64 bit address. */ | |
5404 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5405 | } | |
5406 | ||
9ce8a5dd | 5407 | if (mips_opts.isa != 1) |
252b5132 RH |
5408 | { |
5409 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5410 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); | |
5411 | ||
5412 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
5413 | that this does not become a variant frag. */ | |
5414 | frag_wane (frag_now); | |
5415 | frag_new (0); | |
5416 | ||
5417 | break; | |
5418 | } | |
5419 | breg = AT; | |
5420 | r = BFD_RELOC_LO16; | |
5421 | goto dob; | |
5422 | } | |
5423 | ||
5424 | case M_L_DOB: | |
5425 | if (mips_cpu == 4650) | |
5426 | { | |
5427 | as_bad (_("opcode not supported on this processor")); | |
5428 | return; | |
5429 | } | |
5430 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5431 | to adjust when loading from memory. */ | |
5432 | r = BFD_RELOC_LO16; | |
5433 | dob: | |
9ce8a5dd | 5434 | assert (mips_opts.isa == 1); |
252b5132 RH |
5435 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
5436 | target_big_endian ? treg + 1 : treg, | |
5437 | (int) r, breg); | |
5438 | /* FIXME: A possible overflow which I don't know how to deal | |
5439 | with. */ | |
5440 | offset_expr.X_add_number += 4; | |
5441 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
5442 | target_big_endian ? treg : treg + 1, | |
5443 | (int) r, breg); | |
5444 | ||
5445 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5446 | does not become a variant frag. */ | |
5447 | frag_wane (frag_now); | |
5448 | frag_new (0); | |
5449 | ||
5450 | if (breg != AT) | |
5451 | return; | |
5452 | break; | |
5453 | ||
5454 | case M_L_DAB: | |
5455 | /* | |
5456 | * The MIPS assembler seems to check for X_add_number not | |
5457 | * being double aligned and generating: | |
5458 | * lui at,%hi(foo+1) | |
5459 | * addu at,at,v1 | |
5460 | * addiu at,at,%lo(foo+1) | |
5461 | * lwc1 f2,0(at) | |
5462 | * lwc1 f3,4(at) | |
5463 | * But, the resulting address is the same after relocation so why | |
5464 | * generate the extra instruction? | |
5465 | */ | |
5466 | if (mips_cpu == 4650) | |
5467 | { | |
5468 | as_bad (_("opcode not supported on this processor")); | |
5469 | return; | |
5470 | } | |
5471 | /* Itbl support may require additional care here. */ | |
5472 | coproc = 1; | |
9ce8a5dd | 5473 | if (mips_opts.isa != 1) |
252b5132 RH |
5474 | { |
5475 | s = "ldc1"; | |
5476 | goto ld; | |
5477 | } | |
5478 | ||
5479 | s = "lwc1"; | |
5480 | fmt = "T,o(b)"; | |
5481 | goto ldd_std; | |
5482 | ||
5483 | case M_S_DAB: | |
5484 | if (mips_cpu == 4650) | |
5485 | { | |
5486 | as_bad (_("opcode not supported on this processor")); | |
5487 | return; | |
5488 | } | |
5489 | ||
9ce8a5dd | 5490 | if (mips_opts.isa != 1) |
252b5132 RH |
5491 | { |
5492 | s = "sdc1"; | |
5493 | goto st; | |
5494 | } | |
5495 | ||
5496 | s = "swc1"; | |
5497 | fmt = "T,o(b)"; | |
5498 | /* Itbl support may require additional care here. */ | |
5499 | coproc = 1; | |
5500 | goto ldd_std; | |
5501 | ||
5502 | case M_LD_AB: | |
9ce8a5dd | 5503 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5504 | { |
5505 | s = "ld"; | |
5506 | goto ld; | |
5507 | } | |
5508 | ||
5509 | s = "lw"; | |
5510 | fmt = "t,o(b)"; | |
5511 | goto ldd_std; | |
5512 | ||
5513 | case M_SD_AB: | |
9ce8a5dd | 5514 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5515 | { |
5516 | s = "sd"; | |
5517 | goto st; | |
5518 | } | |
5519 | ||
5520 | s = "sw"; | |
5521 | fmt = "t,o(b)"; | |
5522 | ||
5523 | ldd_std: | |
5524 | if (offset_expr.X_op != O_symbol | |
5525 | && offset_expr.X_op != O_constant) | |
5526 | { | |
5527 | as_bad (_("expression too complex")); | |
5528 | offset_expr.X_op = O_constant; | |
5529 | } | |
5530 | ||
5531 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5532 | to adjust when loading from memory. We set coproc if we must | |
5533 | load $fn+1 first. */ | |
5534 | /* Itbl support may require additional care here. */ | |
5535 | if (! target_big_endian) | |
5536 | coproc = 0; | |
5537 | ||
5538 | if (mips_pic == NO_PIC | |
5539 | || offset_expr.X_op == O_constant) | |
5540 | { | |
5541 | /* If this is a reference to a GP relative symbol, we want | |
5542 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5543 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5544 | If we have a base register, we use this | |
5545 | addu $at,$breg,$gp | |
5546 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5547 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5548 | If this is not a GP relative symbol, we want | |
5549 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5550 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5551 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5552 | If there is a base register, we add it to $at after the | |
5553 | lui instruction. If there is a constant, we always use | |
5554 | the last case. */ | |
5555 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET | |
5556 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5557 | { | |
5558 | p = NULL; | |
5559 | used_at = 1; | |
5560 | } | |
5561 | else | |
5562 | { | |
5563 | int off; | |
5564 | ||
5565 | if (breg == 0) | |
5566 | { | |
5567 | frag_grow (28); | |
5568 | tempreg = GP; | |
5569 | off = 0; | |
5570 | used_at = 0; | |
5571 | } | |
5572 | else | |
5573 | { | |
5574 | frag_grow (36); | |
5575 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5576 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5577 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5578 | ? "addu" : "daddu"), |
5579 | "d,v,t", AT, breg, GP); | |
5580 | tempreg = AT; | |
5581 | off = 4; | |
5582 | used_at = 1; | |
5583 | } | |
5584 | ||
5585 | /* Itbl support may require additional care here. */ | |
5586 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5587 | coproc ? treg + 1 : treg, | |
5588 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5589 | offset_expr.X_add_number += 4; | |
5590 | ||
5591 | /* Set mips_optimize to 2 to avoid inserting an | |
5592 | undesired nop. */ | |
5593 | hold_mips_optimize = mips_optimize; | |
5594 | mips_optimize = 2; | |
5595 | /* Itbl support may require additional care here. */ | |
5596 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5597 | coproc ? treg : treg + 1, | |
5598 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5599 | mips_optimize = hold_mips_optimize; | |
5600 | ||
5601 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
5602 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
5603 | used_at && mips_opts.noat), | |
5604 | offset_expr.X_add_symbol, (offsetT) 0, | |
5605 | (char *) NULL); | |
5606 | ||
5607 | /* We just generated two relocs. When tc_gen_reloc | |
5608 | handles this case, it will skip the first reloc and | |
5609 | handle the second. The second reloc already has an | |
5610 | extra addend of 4, which we added above. We must | |
5611 | subtract it out, and then subtract another 4 to make | |
5612 | the first reloc come out right. The second reloc | |
5613 | will come out right because we are going to add 4 to | |
5614 | offset_expr when we build its instruction below. | |
5615 | ||
5616 | If we have a symbol, then we don't want to include | |
5617 | the offset, because it will wind up being included | |
5618 | when we generate the reloc. */ | |
5619 | ||
5620 | if (offset_expr.X_op == O_constant) | |
5621 | offset_expr.X_add_number -= 8; | |
5622 | else | |
5623 | { | |
5624 | offset_expr.X_add_number = -4; | |
5625 | offset_expr.X_op = O_constant; | |
5626 | } | |
5627 | } | |
5628 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
5629 | if (p != NULL) | |
5630 | p += 4; | |
5631 | if (breg != 0) | |
5632 | { | |
5633 | macro_build (p, &icnt, (expressionS *) NULL, | |
5634 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5635 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5636 | ? "addu" : "daddu"), |
5637 | "d,v,t", AT, breg, AT); | |
5638 | if (p != NULL) | |
5639 | p += 4; | |
5640 | } | |
5641 | /* Itbl support may require additional care here. */ | |
5642 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
5643 | coproc ? treg + 1 : treg, | |
5644 | (int) BFD_RELOC_LO16, AT); | |
5645 | if (p != NULL) | |
5646 | p += 4; | |
5647 | /* FIXME: How do we handle overflow here? */ | |
5648 | offset_expr.X_add_number += 4; | |
5649 | /* Itbl support may require additional care here. */ | |
5650 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
5651 | coproc ? treg : treg + 1, | |
5652 | (int) BFD_RELOC_LO16, AT); | |
5653 | } | |
5654 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
5655 | { | |
5656 | int off; | |
5657 | ||
5658 | /* If this is a reference to an external symbol, we want | |
5659 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5660 | nop | |
5661 | <op> $treg,0($at) | |
5662 | <op> $treg+1,4($at) | |
5663 | Otherwise we want | |
5664 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5665 | nop | |
5666 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5667 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5668 | If there is a base register we add it to $at before the | |
5669 | lwc1 instructions. If there is a constant we include it | |
5670 | in the lwc1 instructions. */ | |
5671 | used_at = 1; | |
5672 | expr1.X_add_number = offset_expr.X_add_number; | |
5673 | offset_expr.X_add_number = 0; | |
5674 | if (expr1.X_add_number < -0x8000 | |
5675 | || expr1.X_add_number >= 0x8000 - 4) | |
5676 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5677 | if (breg == 0) | |
5678 | off = 0; | |
5679 | else | |
5680 | off = 4; | |
5681 | frag_grow (24 + off); | |
5682 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5683 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5684 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5685 | ? "lw" : "ld"), |
5686 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5687 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5688 | if (breg != 0) | |
5689 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5690 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5691 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5692 | ? "addu" : "daddu"), |
5693 | "d,v,t", AT, breg, AT); | |
5694 | /* Itbl support may require additional care here. */ | |
5695 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
5696 | coproc ? treg + 1 : treg, | |
5697 | (int) BFD_RELOC_LO16, AT); | |
5698 | expr1.X_add_number += 4; | |
5699 | ||
5700 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5701 | nop. */ | |
5702 | hold_mips_optimize = mips_optimize; | |
5703 | mips_optimize = 2; | |
5704 | /* Itbl support may require additional care here. */ | |
5705 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
5706 | coproc ? treg : treg + 1, | |
5707 | (int) BFD_RELOC_LO16, AT); | |
5708 | mips_optimize = hold_mips_optimize; | |
5709 | ||
5710 | (void) frag_var (rs_machine_dependent, 0, 0, | |
5711 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
5712 | offset_expr.X_add_symbol, (offsetT) 0, | |
5713 | (char *) NULL); | |
5714 | } | |
5715 | else if (mips_pic == SVR4_PIC) | |
5716 | { | |
5717 | int gpdel, off; | |
5718 | ||
5719 | /* If this is a reference to an external symbol, we want | |
5720 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5721 | addu $at,$at,$gp | |
5722 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
5723 | nop | |
5724 | <op> $treg,0($at) | |
5725 | <op> $treg+1,4($at) | |
5726 | Otherwise we want | |
5727 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5728 | nop | |
5729 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5730 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5731 | If there is a base register we add it to $at before the | |
5732 | lwc1 instructions. If there is a constant we include it | |
5733 | in the lwc1 instructions. */ | |
5734 | used_at = 1; | |
5735 | expr1.X_add_number = offset_expr.X_add_number; | |
5736 | offset_expr.X_add_number = 0; | |
5737 | if (expr1.X_add_number < -0x8000 | |
5738 | || expr1.X_add_number >= 0x8000 - 4) | |
5739 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5740 | if (reg_needs_delay (GP)) | |
5741 | gpdel = 4; | |
5742 | else | |
5743 | gpdel = 0; | |
5744 | if (breg == 0) | |
5745 | off = 0; | |
5746 | else | |
5747 | off = 4; | |
5748 | frag_grow (56); | |
5749 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5750 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5751 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5752 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5753 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5754 | ? "addu" : "daddu"), |
5755 | "d,v,t", AT, AT, GP); | |
5756 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5757 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5758 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5759 | ? "lw" : "ld"), |
5760 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); | |
5761 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5762 | if (breg != 0) | |
5763 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5764 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5765 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5766 | ? "addu" : "daddu"), |
5767 | "d,v,t", AT, breg, AT); | |
5768 | /* Itbl support may require additional care here. */ | |
5769 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
5770 | coproc ? treg + 1 : treg, | |
5771 | (int) BFD_RELOC_LO16, AT); | |
5772 | expr1.X_add_number += 4; | |
5773 | ||
5774 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5775 | nop. */ | |
5776 | hold_mips_optimize = mips_optimize; | |
5777 | mips_optimize = 2; | |
5778 | /* Itbl support may require additional care here. */ | |
5779 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
5780 | coproc ? treg : treg + 1, | |
5781 | (int) BFD_RELOC_LO16, AT); | |
5782 | mips_optimize = hold_mips_optimize; | |
5783 | expr1.X_add_number -= 4; | |
5784 | ||
5785 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5786 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5787 | 8 + gpdel + off, 1, 0), | |
5788 | offset_expr.X_add_symbol, (offsetT) 0, | |
5789 | (char *) NULL); | |
5790 | if (gpdel > 0) | |
5791 | { | |
5792 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5793 | p += 4; | |
5794 | } | |
5795 | macro_build (p, &icnt, &offset_expr, | |
5796 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5797 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5798 | ? "lw" : "ld"), |
5799 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5800 | p += 4; | |
5801 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5802 | p += 4; | |
5803 | if (breg != 0) | |
5804 | { | |
5805 | macro_build (p, &icnt, (expressionS *) NULL, | |
5806 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5807 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5808 | ? "addu" : "daddu"), |
5809 | "d,v,t", AT, breg, AT); | |
5810 | p += 4; | |
5811 | } | |
5812 | /* Itbl support may require additional care here. */ | |
5813 | macro_build (p, &icnt, &expr1, s, fmt, | |
5814 | coproc ? treg + 1 : treg, | |
5815 | (int) BFD_RELOC_LO16, AT); | |
5816 | p += 4; | |
5817 | expr1.X_add_number += 4; | |
5818 | ||
5819 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5820 | nop. */ | |
5821 | hold_mips_optimize = mips_optimize; | |
5822 | mips_optimize = 2; | |
5823 | /* Itbl support may require additional care here. */ | |
5824 | macro_build (p, &icnt, &expr1, s, fmt, | |
5825 | coproc ? treg : treg + 1, | |
5826 | (int) BFD_RELOC_LO16, AT); | |
5827 | mips_optimize = hold_mips_optimize; | |
5828 | } | |
5829 | else if (mips_pic == EMBEDDED_PIC) | |
5830 | { | |
5831 | /* If there is no base register, we use | |
5832 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5833 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5834 | If we have a base register, we use | |
5835 | addu $at,$breg,$gp | |
5836 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5837 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5838 | */ | |
5839 | if (breg == 0) | |
5840 | { | |
5841 | tempreg = GP; | |
5842 | used_at = 0; | |
5843 | } | |
5844 | else | |
5845 | { | |
5846 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5847 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5848 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5849 | ? "addu" : "daddu"), |
5850 | "d,v,t", AT, breg, GP); | |
5851 | tempreg = AT; | |
5852 | used_at = 1; | |
5853 | } | |
5854 | ||
5855 | /* Itbl support may require additional care here. */ | |
5856 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5857 | coproc ? treg + 1 : treg, | |
5858 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5859 | offset_expr.X_add_number += 4; | |
5860 | /* Itbl support may require additional care here. */ | |
5861 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5862 | coproc ? treg : treg + 1, | |
5863 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5864 | } | |
5865 | else | |
5866 | abort (); | |
5867 | ||
5868 | if (! used_at) | |
5869 | return; | |
5870 | ||
5871 | break; | |
5872 | ||
5873 | case M_LD_OB: | |
5874 | s = "lw"; | |
5875 | goto sd_ob; | |
5876 | case M_SD_OB: | |
5877 | s = "sw"; | |
5878 | sd_ob: | |
9ce8a5dd GRK |
5879 | assert (bfd_arch_bits_per_address (stdoutput) == 32 |
5880 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
252b5132 RH |
5881 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
5882 | (int) BFD_RELOC_LO16, breg); | |
5883 | offset_expr.X_add_number += 4; | |
5884 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5885 | (int) BFD_RELOC_LO16, breg); | |
5886 | return; | |
5887 | ||
5888 | /* New code added to support COPZ instructions. | |
5889 | This code builds table entries out of the macros in mip_opcodes. | |
5890 | R4000 uses interlocks to handle coproc delays. | |
5891 | Other chips (like the R3000) require nops to be inserted for delays. | |
5892 | ||
5893 | FIXME: Currently, we require that the user handle delays. | |
5894 | In order to fill delay slots for non-interlocked chips, | |
5895 | we must have a way to specify delays based on the coprocessor. | |
5896 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
5897 | What are the side-effects of the cop instruction? | |
5898 | What cache support might we have and what are its effects? | |
5899 | Both coprocessor & memory require delays. how long??? | |
5900 | What registers are read/set/modified? | |
5901 | ||
5902 | If an itbl is provided to interpret cop instructions, | |
5903 | this knowledge can be encoded in the itbl spec. */ | |
5904 | ||
5905 | case M_COP0: | |
5906 | s = "c0"; | |
5907 | goto copz; | |
5908 | case M_COP1: | |
5909 | s = "c1"; | |
5910 | goto copz; | |
5911 | case M_COP2: | |
5912 | s = "c2"; | |
5913 | goto copz; | |
5914 | case M_COP3: | |
5915 | s = "c3"; | |
5916 | copz: | |
5917 | /* For now we just do C (same as Cz). The parameter will be | |
5918 | stored in insn_opcode by mips_ip. */ | |
5919 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", | |
5920 | ip->insn_opcode); | |
5921 | return; | |
5922 | ||
5923 | #ifdef LOSING_COMPILER | |
5924 | default: | |
5925 | /* Try and see if this is a new itbl instruction. | |
5926 | This code builds table entries out of the macros in mip_opcodes. | |
5927 | FIXME: For now we just assemble the expression and pass it's | |
5928 | value along as a 32-bit immediate. | |
5929 | We may want to have the assembler assemble this value, | |
5930 | so that we gain the assembler's knowledge of delay slots, | |
5931 | symbols, etc. | |
5932 | Would it be more efficient to use mask (id) here? */ | |
5933 | if (itbl_have_entries | |
5934 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) | |
5935 | { | |
5936 | s = ip->insn_mo->name; | |
5937 | s2 = "cop3"; | |
5938 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
5939 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); | |
5940 | return; | |
5941 | } | |
5942 | macro2 (ip); | |
5943 | return; | |
5944 | } | |
5945 | if (mips_opts.noat) | |
5946 | as_warn (_("Macro used $at after \".set noat\"")); | |
5947 | } | |
5948 | ||
5949 | static void | |
5950 | macro2 (ip) | |
5951 | struct mips_cl_insn *ip; | |
5952 | { | |
5953 | register int treg, sreg, dreg, breg; | |
5954 | int tempreg; | |
5955 | int mask; | |
5956 | int icnt = 0; | |
5957 | int used_at; | |
5958 | expressionS expr1; | |
5959 | const char *s; | |
5960 | const char *s2; | |
5961 | const char *fmt; | |
5962 | int likely = 0; | |
5963 | int dbl = 0; | |
5964 | int coproc = 0; | |
5965 | int lr = 0; | |
5966 | int imm = 0; | |
5967 | int off; | |
5968 | offsetT maxnum; | |
5969 | bfd_reloc_code_real_type r; | |
5970 | char *p; | |
5971 | ||
5972 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
5973 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
5974 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
5975 | mask = ip->insn_mo->mask; | |
5976 | ||
5977 | expr1.X_op = O_constant; | |
5978 | expr1.X_op_symbol = NULL; | |
5979 | expr1.X_add_symbol = NULL; | |
5980 | expr1.X_add_number = 1; | |
5981 | ||
5982 | switch (mask) | |
5983 | { | |
5984 | #endif /* LOSING_COMPILER */ | |
5985 | ||
5986 | case M_DMUL: | |
5987 | dbl = 1; | |
5988 | case M_MUL: | |
5989 | macro_build ((char *) NULL, &icnt, NULL, | |
5990 | dbl ? "dmultu" : "multu", | |
5991 | "s,t", sreg, treg); | |
5992 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
5993 | return; | |
5994 | ||
5995 | case M_DMUL_I: | |
5996 | dbl = 1; | |
5997 | case M_MUL_I: | |
5998 | /* The MIPS assembler some times generates shifts and adds. I'm | |
5999 | not trying to be that fancy. GCC should do this for us | |
6000 | anyway. */ | |
6001 | load_register (&icnt, AT, &imm_expr, dbl); | |
6002 | macro_build ((char *) NULL, &icnt, NULL, | |
6003 | dbl ? "dmult" : "mult", | |
6004 | "s,t", sreg, AT); | |
6005 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
6006 | break; | |
6007 | ||
6008 | case M_DMULO_I: | |
6009 | dbl = 1; | |
6010 | case M_MULO_I: | |
6011 | imm = 1; | |
6012 | goto do_mulo; | |
6013 | ||
6014 | case M_DMULO: | |
6015 | dbl = 1; | |
6016 | case M_MULO: | |
6017 | do_mulo: | |
6018 | mips_emit_delays (true); | |
6019 | ++mips_opts.noreorder; | |
6020 | mips_any_noreorder = 1; | |
6021 | if (imm) | |
6022 | load_register (&icnt, AT, &imm_expr, dbl); | |
6023 | macro_build ((char *) NULL, &icnt, NULL, | |
6024 | dbl ? "dmult" : "mult", | |
6025 | "s,t", sreg, imm ? AT : treg); | |
6026 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
6027 | macro_build ((char *) NULL, &icnt, NULL, | |
6028 | dbl ? "dsra32" : "sra", | |
6029 | "d,w,<", dreg, dreg, 31); | |
6030 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); | |
6031 | if (mips_trap) | |
6032 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
6033 | else | |
6034 | { | |
6035 | expr1.X_add_number = 8; | |
6036 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
6037 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
6038 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
6039 | } | |
6040 | --mips_opts.noreorder; | |
6041 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
6042 | break; | |
6043 | ||
6044 | case M_DMULOU_I: | |
6045 | dbl = 1; | |
6046 | case M_MULOU_I: | |
6047 | imm = 1; | |
6048 | goto do_mulou; | |
6049 | ||
6050 | case M_DMULOU: | |
6051 | dbl = 1; | |
6052 | case M_MULOU: | |
6053 | do_mulou: | |
6054 | mips_emit_delays (true); | |
6055 | ++mips_opts.noreorder; | |
6056 | mips_any_noreorder = 1; | |
6057 | if (imm) | |
6058 | load_register (&icnt, AT, &imm_expr, dbl); | |
6059 | macro_build ((char *) NULL, &icnt, NULL, | |
6060 | dbl ? "dmultu" : "multu", | |
6061 | "s,t", sreg, imm ? AT : treg); | |
6062 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); | |
6063 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
6064 | if (mips_trap) | |
6065 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
6066 | else | |
6067 | { | |
6068 | expr1.X_add_number = 8; | |
6069 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
6070 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
6071 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
6072 | } | |
6073 | --mips_opts.noreorder; | |
6074 | break; | |
6075 | ||
6076 | case M_ROL: | |
6077 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); | |
6078 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6079 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
6080 | treg); | |
6081 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
6082 | break; | |
6083 | ||
6084 | case M_ROL_I: | |
6085 | if (imm_expr.X_op != O_constant) | |
6086 | as_bad (_("rotate count too large")); | |
6087 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, | |
6088 | (int) (imm_expr.X_add_number & 0x1f)); | |
6089 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, | |
6090 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); | |
6091 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
6092 | break; | |
6093 | ||
6094 | case M_ROR: | |
6095 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); | |
6096 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
6097 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
6098 | treg); | |
6099 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
6100 | break; | |
6101 | ||
6102 | case M_ROR_I: | |
6103 | if (imm_expr.X_op != O_constant) | |
6104 | as_bad (_("rotate count too large")); | |
6105 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, | |
6106 | (int) (imm_expr.X_add_number & 0x1f)); | |
6107 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, | |
6108 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); | |
6109 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
6110 | break; | |
6111 | ||
6112 | case M_S_DOB: | |
6113 | if (mips_cpu == 4650) | |
6114 | { | |
6115 | as_bad (_("opcode not supported on this processor")); | |
6116 | return; | |
6117 | } | |
9ce8a5dd | 6118 | assert (mips_opts.isa == 1); |
252b5132 RH |
6119 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6120 | to adjust when storing to memory. */ | |
6121 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
6122 | target_big_endian ? treg + 1 : treg, | |
6123 | (int) BFD_RELOC_LO16, breg); | |
6124 | offset_expr.X_add_number += 4; | |
6125 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
6126 | target_big_endian ? treg : treg + 1, | |
6127 | (int) BFD_RELOC_LO16, breg); | |
6128 | return; | |
6129 | ||
6130 | case M_SEQ: | |
6131 | if (sreg == 0) | |
6132 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6133 | treg, (int) BFD_RELOC_LO16); | |
6134 | else if (treg == 0) | |
6135 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6136 | sreg, (int) BFD_RELOC_LO16); | |
6137 | else | |
6138 | { | |
6139 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6140 | sreg, treg); | |
6141 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6142 | dreg, (int) BFD_RELOC_LO16); | |
6143 | } | |
6144 | return; | |
6145 | ||
6146 | case M_SEQ_I: | |
6147 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6148 | { | |
6149 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6150 | sreg, (int) BFD_RELOC_LO16); | |
6151 | return; | |
6152 | } | |
6153 | if (sreg == 0) | |
6154 | { | |
6155 | as_warn (_("Instruction %s: result is always false"), | |
6156 | ip->insn_mo->name); | |
6157 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); | |
6158 | return; | |
6159 | } | |
6160 | if (imm_expr.X_op == O_constant | |
6161 | && imm_expr.X_add_number >= 0 | |
6162 | && imm_expr.X_add_number < 0x10000) | |
6163 | { | |
6164 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, | |
6165 | sreg, (int) BFD_RELOC_LO16); | |
6166 | used_at = 0; | |
6167 | } | |
6168 | else if (imm_expr.X_op == O_constant | |
6169 | && imm_expr.X_add_number > -0x8000 | |
6170 | && imm_expr.X_add_number < 0) | |
6171 | { | |
6172 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6173 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6174 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6175 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6176 | ? "addiu" : "daddiu"), |
6177 | "t,r,j", dreg, sreg, | |
6178 | (int) BFD_RELOC_LO16); | |
6179 | used_at = 0; | |
6180 | } | |
6181 | else | |
6182 | { | |
6183 | load_register (&icnt, AT, &imm_expr, 0); | |
6184 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6185 | sreg, AT); | |
6186 | used_at = 1; | |
6187 | } | |
6188 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, | |
6189 | (int) BFD_RELOC_LO16); | |
6190 | if (used_at) | |
6191 | break; | |
6192 | return; | |
6193 | ||
6194 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
6195 | s = "slt"; | |
6196 | goto sge; | |
6197 | case M_SGEU: | |
6198 | s = "sltu"; | |
6199 | sge: | |
6200 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); | |
6201 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6202 | (int) BFD_RELOC_LO16); | |
6203 | return; | |
6204 | ||
6205 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
6206 | case M_SGEU_I: | |
6207 | if (imm_expr.X_op == O_constant | |
6208 | && imm_expr.X_add_number >= -0x8000 | |
6209 | && imm_expr.X_add_number < 0x8000) | |
6210 | { | |
6211 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6212 | mask == M_SGE_I ? "slti" : "sltiu", | |
6213 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6214 | used_at = 0; | |
6215 | } | |
6216 | else | |
6217 | { | |
6218 | load_register (&icnt, AT, &imm_expr, 0); | |
6219 | macro_build ((char *) NULL, &icnt, NULL, | |
6220 | mask == M_SGE_I ? "slt" : "sltu", | |
6221 | "d,v,t", dreg, sreg, AT); | |
6222 | used_at = 1; | |
6223 | } | |
6224 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6225 | (int) BFD_RELOC_LO16); | |
6226 | if (used_at) | |
6227 | break; | |
6228 | return; | |
6229 | ||
6230 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
6231 | s = "slt"; | |
6232 | goto sgt; | |
6233 | case M_SGTU: | |
6234 | s = "sltu"; | |
6235 | sgt: | |
6236 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); | |
6237 | return; | |
6238 | ||
6239 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
6240 | s = "slt"; | |
6241 | goto sgti; | |
6242 | case M_SGTU_I: | |
6243 | s = "sltu"; | |
6244 | sgti: | |
6245 | load_register (&icnt, AT, &imm_expr, 0); | |
6246 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); | |
6247 | break; | |
6248 | ||
6249 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ | |
6250 | s = "slt"; | |
6251 | goto sle; | |
6252 | case M_SLEU: | |
6253 | s = "sltu"; | |
6254 | sle: | |
6255 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); | |
6256 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6257 | (int) BFD_RELOC_LO16); | |
6258 | return; | |
6259 | ||
6260 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ | |
6261 | s = "slt"; | |
6262 | goto slei; | |
6263 | case M_SLEU_I: | |
6264 | s = "sltu"; | |
6265 | slei: | |
6266 | load_register (&icnt, AT, &imm_expr, 0); | |
6267 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); | |
6268 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6269 | (int) BFD_RELOC_LO16); | |
6270 | break; | |
6271 | ||
6272 | case M_SLT_I: | |
6273 | if (imm_expr.X_op == O_constant | |
6274 | && imm_expr.X_add_number >= -0x8000 | |
6275 | && imm_expr.X_add_number < 0x8000) | |
6276 | { | |
6277 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", | |
6278 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6279 | return; | |
6280 | } | |
6281 | load_register (&icnt, AT, &imm_expr, 0); | |
6282 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); | |
6283 | break; | |
6284 | ||
6285 | case M_SLTU_I: | |
6286 | if (imm_expr.X_op == O_constant | |
6287 | && imm_expr.X_add_number >= -0x8000 | |
6288 | && imm_expr.X_add_number < 0x8000) | |
6289 | { | |
6290 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", | |
6291 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6292 | return; | |
6293 | } | |
6294 | load_register (&icnt, AT, &imm_expr, 0); | |
6295 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, | |
6296 | AT); | |
6297 | break; | |
6298 | ||
6299 | case M_SNE: | |
6300 | if (sreg == 0) | |
6301 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6302 | treg); | |
6303 | else if (treg == 0) | |
6304 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6305 | sreg); | |
6306 | else | |
6307 | { | |
6308 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6309 | sreg, treg); | |
6310 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6311 | dreg); | |
6312 | } | |
6313 | return; | |
6314 | ||
6315 | case M_SNE_I: | |
6316 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6317 | { | |
6318 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6319 | sreg); | |
6320 | return; | |
6321 | } | |
6322 | if (sreg == 0) | |
6323 | { | |
6324 | as_warn (_("Instruction %s: result is always true"), | |
6325 | ip->insn_mo->name); | |
6326 | macro_build ((char *) NULL, &icnt, &expr1, | |
6327 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6328 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6329 | ? "addiu" : "daddiu"), |
6330 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); | |
6331 | return; | |
6332 | } | |
6333 | if (imm_expr.X_op == O_constant | |
6334 | && imm_expr.X_add_number >= 0 | |
6335 | && imm_expr.X_add_number < 0x10000) | |
6336 | { | |
6337 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", | |
6338 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6339 | used_at = 0; | |
6340 | } | |
6341 | else if (imm_expr.X_op == O_constant | |
6342 | && imm_expr.X_add_number > -0x8000 | |
6343 | && imm_expr.X_add_number < 0) | |
6344 | { | |
6345 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6346 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6347 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6348 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6349 | ? "addiu" : "daddiu"), |
6350 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6351 | used_at = 0; | |
6352 | } | |
6353 | else | |
6354 | { | |
6355 | load_register (&icnt, AT, &imm_expr, 0); | |
6356 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6357 | sreg, AT); | |
6358 | used_at = 1; | |
6359 | } | |
6360 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
6361 | if (used_at) | |
6362 | break; | |
6363 | return; | |
6364 | ||
6365 | case M_DSUB_I: | |
6366 | dbl = 1; | |
6367 | case M_SUB_I: | |
6368 | if (imm_expr.X_op == O_constant | |
6369 | && imm_expr.X_add_number > -0x8000 | |
6370 | && imm_expr.X_add_number <= 0x8000) | |
6371 | { | |
6372 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6373 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6374 | dbl ? "daddi" : "addi", | |
6375 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6376 | return; | |
6377 | } | |
6378 | load_register (&icnt, AT, &imm_expr, dbl); | |
6379 | macro_build ((char *) NULL, &icnt, NULL, | |
6380 | dbl ? "dsub" : "sub", | |
6381 | "d,v,t", dreg, sreg, AT); | |
6382 | break; | |
6383 | ||
6384 | case M_DSUBU_I: | |
6385 | dbl = 1; | |
6386 | case M_SUBU_I: | |
6387 | if (imm_expr.X_op == O_constant | |
6388 | && imm_expr.X_add_number > -0x8000 | |
6389 | && imm_expr.X_add_number <= 0x8000) | |
6390 | { | |
6391 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6392 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6393 | dbl ? "daddiu" : "addiu", | |
6394 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6395 | return; | |
6396 | } | |
6397 | load_register (&icnt, AT, &imm_expr, dbl); | |
6398 | macro_build ((char *) NULL, &icnt, NULL, | |
6399 | dbl ? "dsubu" : "subu", | |
6400 | "d,v,t", dreg, sreg, AT); | |
6401 | break; | |
6402 | ||
6403 | case M_TEQ_I: | |
6404 | s = "teq"; | |
6405 | goto trap; | |
6406 | case M_TGE_I: | |
6407 | s = "tge"; | |
6408 | goto trap; | |
6409 | case M_TGEU_I: | |
6410 | s = "tgeu"; | |
6411 | goto trap; | |
6412 | case M_TLT_I: | |
6413 | s = "tlt"; | |
6414 | goto trap; | |
6415 | case M_TLTU_I: | |
6416 | s = "tltu"; | |
6417 | goto trap; | |
6418 | case M_TNE_I: | |
6419 | s = "tne"; | |
6420 | trap: | |
6421 | load_register (&icnt, AT, &imm_expr, 0); | |
6422 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); | |
6423 | break; | |
6424 | ||
252b5132 | 6425 | case M_TRUNCWS: |
43841e91 | 6426 | case M_TRUNCWD: |
9ce8a5dd | 6427 | assert (mips_opts.isa == 1); |
252b5132 RH |
6428 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
6429 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
6430 | ||
6431 | /* | |
6432 | * Is the double cfc1 instruction a bug in the mips assembler; | |
6433 | * or is there a reason for it? | |
6434 | */ | |
6435 | mips_emit_delays (true); | |
6436 | ++mips_opts.noreorder; | |
6437 | mips_any_noreorder = 1; | |
6438 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6439 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6440 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6441 | expr1.X_add_number = 3; | |
6442 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, | |
6443 | (int) BFD_RELOC_LO16); | |
6444 | expr1.X_add_number = 2; | |
6445 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, | |
6446 | (int) BFD_RELOC_LO16); | |
6447 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); | |
6448 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6449 | macro_build ((char *) NULL, &icnt, NULL, | |
6450 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); | |
6451 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); | |
6452 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6453 | --mips_opts.noreorder; | |
6454 | break; | |
6455 | ||
6456 | case M_ULH: | |
6457 | s = "lb"; | |
6458 | goto ulh; | |
6459 | case M_ULHU: | |
6460 | s = "lbu"; | |
6461 | ulh: | |
6462 | if (offset_expr.X_add_number >= 0x7fff) | |
6463 | as_bad (_("operand overflow")); | |
6464 | /* avoid load delay */ | |
6465 | if (! target_big_endian) | |
6466 | offset_expr.X_add_number += 1; | |
6467 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
6468 | (int) BFD_RELOC_LO16, breg); | |
6469 | if (! target_big_endian) | |
6470 | offset_expr.X_add_number -= 1; | |
6471 | else | |
6472 | offset_expr.X_add_number += 1; | |
6473 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, | |
6474 | (int) BFD_RELOC_LO16, breg); | |
6475 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); | |
6476 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
6477 | break; | |
6478 | ||
6479 | case M_ULD: | |
6480 | s = "ldl"; | |
6481 | s2 = "ldr"; | |
6482 | off = 7; | |
6483 | goto ulw; | |
6484 | case M_ULW: | |
6485 | s = "lwl"; | |
6486 | s2 = "lwr"; | |
6487 | off = 3; | |
6488 | ulw: | |
6489 | if (offset_expr.X_add_number >= 0x8000 - off) | |
6490 | as_bad (_("operand overflow")); | |
6491 | if (! target_big_endian) | |
6492 | offset_expr.X_add_number += off; | |
6493 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
6494 | (int) BFD_RELOC_LO16, breg); | |
6495 | if (! target_big_endian) | |
6496 | offset_expr.X_add_number -= off; | |
6497 | else | |
6498 | offset_expr.X_add_number += off; | |
6499 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
6500 | (int) BFD_RELOC_LO16, breg); | |
6501 | return; | |
6502 | ||
6503 | case M_ULD_A: | |
6504 | s = "ldl"; | |
6505 | s2 = "ldr"; | |
6506 | off = 7; | |
6507 | goto ulwa; | |
6508 | case M_ULW_A: | |
6509 | s = "lwl"; | |
6510 | s2 = "lwr"; | |
6511 | off = 3; | |
6512 | ulwa: | |
6513 | load_address (&icnt, AT, &offset_expr); | |
6514 | if (breg != 0) | |
6515 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6516 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6517 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6518 | ? "addu" : "daddu"), |
6519 | "d,v,t", AT, AT, breg); | |
6520 | if (! target_big_endian) | |
6521 | expr1.X_add_number = off; | |
6522 | else | |
6523 | expr1.X_add_number = 0; | |
6524 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6525 | (int) BFD_RELOC_LO16, AT); | |
6526 | if (! target_big_endian) | |
6527 | expr1.X_add_number = 0; | |
6528 | else | |
6529 | expr1.X_add_number = off; | |
6530 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6531 | (int) BFD_RELOC_LO16, AT); | |
6532 | break; | |
6533 | ||
6534 | case M_ULH_A: | |
6535 | case M_ULHU_A: | |
6536 | load_address (&icnt, AT, &offset_expr); | |
6537 | if (breg != 0) | |
6538 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6539 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6540 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6541 | ? "addu" : "daddu"), |
6542 | "d,v,t", AT, AT, breg); | |
6543 | if (target_big_endian) | |
6544 | expr1.X_add_number = 0; | |
6545 | macro_build ((char *) NULL, &icnt, &expr1, | |
6546 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
6547 | (int) BFD_RELOC_LO16, AT); | |
6548 | if (target_big_endian) | |
6549 | expr1.X_add_number = 1; | |
6550 | else | |
6551 | expr1.X_add_number = 0; | |
6552 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6553 | (int) BFD_RELOC_LO16, AT); | |
6554 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6555 | treg, 8); | |
6556 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6557 | treg, AT); | |
6558 | break; | |
6559 | ||
6560 | case M_USH: | |
6561 | if (offset_expr.X_add_number >= 0x7fff) | |
6562 | as_bad (_("operand overflow")); | |
6563 | if (target_big_endian) | |
6564 | offset_expr.X_add_number += 1; | |
6565 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, | |
6566 | (int) BFD_RELOC_LO16, breg); | |
6567 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); | |
6568 | if (target_big_endian) | |
6569 | offset_expr.X_add_number -= 1; | |
6570 | else | |
6571 | offset_expr.X_add_number += 1; | |
6572 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, | |
6573 | (int) BFD_RELOC_LO16, breg); | |
6574 | break; | |
6575 | ||
6576 | case M_USD: | |
6577 | s = "sdl"; | |
6578 | s2 = "sdr"; | |
6579 | off = 7; | |
6580 | goto usw; | |
6581 | case M_USW: | |
6582 | s = "swl"; | |
6583 | s2 = "swr"; | |
6584 | off = 3; | |
6585 | usw: | |
6586 | if (offset_expr.X_add_number >= 0x8000 - off) | |
6587 | as_bad (_("operand overflow")); | |
6588 | if (! target_big_endian) | |
6589 | offset_expr.X_add_number += off; | |
6590 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
6591 | (int) BFD_RELOC_LO16, breg); | |
6592 | if (! target_big_endian) | |
6593 | offset_expr.X_add_number -= off; | |
6594 | else | |
6595 | offset_expr.X_add_number += off; | |
6596 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
6597 | (int) BFD_RELOC_LO16, breg); | |
6598 | return; | |
6599 | ||
6600 | case M_USD_A: | |
6601 | s = "sdl"; | |
6602 | s2 = "sdr"; | |
6603 | off = 7; | |
6604 | goto uswa; | |
6605 | case M_USW_A: | |
6606 | s = "swl"; | |
6607 | s2 = "swr"; | |
6608 | off = 3; | |
6609 | uswa: | |
6610 | load_address (&icnt, AT, &offset_expr); | |
6611 | if (breg != 0) | |
6612 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6613 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6614 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6615 | ? "addu" : "daddu"), |
6616 | "d,v,t", AT, AT, breg); | |
6617 | if (! target_big_endian) | |
6618 | expr1.X_add_number = off; | |
6619 | else | |
6620 | expr1.X_add_number = 0; | |
6621 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6622 | (int) BFD_RELOC_LO16, AT); | |
6623 | if (! target_big_endian) | |
6624 | expr1.X_add_number = 0; | |
6625 | else | |
6626 | expr1.X_add_number = off; | |
6627 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6628 | (int) BFD_RELOC_LO16, AT); | |
6629 | break; | |
6630 | ||
6631 | case M_USH_A: | |
6632 | load_address (&icnt, AT, &offset_expr); | |
6633 | if (breg != 0) | |
6634 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6635 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6636 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6637 | ? "addu" : "daddu"), |
6638 | "d,v,t", AT, AT, breg); | |
6639 | if (! target_big_endian) | |
6640 | expr1.X_add_number = 0; | |
6641 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6642 | (int) BFD_RELOC_LO16, AT); | |
6643 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
6644 | treg, 8); | |
6645 | if (! target_big_endian) | |
6646 | expr1.X_add_number = 1; | |
6647 | else | |
6648 | expr1.X_add_number = 0; | |
6649 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6650 | (int) BFD_RELOC_LO16, AT); | |
6651 | if (! target_big_endian) | |
6652 | expr1.X_add_number = 0; | |
6653 | else | |
6654 | expr1.X_add_number = 1; | |
6655 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6656 | (int) BFD_RELOC_LO16, AT); | |
6657 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6658 | treg, 8); | |
6659 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6660 | treg, AT); | |
6661 | break; | |
6662 | ||
6663 | default: | |
6664 | /* FIXME: Check if this is one of the itbl macros, since they | |
6665 | are added dynamically. */ | |
6666 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); | |
6667 | break; | |
6668 | } | |
6669 | if (mips_opts.noat) | |
6670 | as_warn (_("Macro used $at after \".set noat\"")); | |
6671 | } | |
6672 | ||
6673 | /* Implement macros in mips16 mode. */ | |
6674 | ||
6675 | static void | |
6676 | mips16_macro (ip) | |
6677 | struct mips_cl_insn *ip; | |
6678 | { | |
6679 | int mask; | |
6680 | int xreg, yreg, zreg, tmp; | |
6681 | int icnt; | |
6682 | expressionS expr1; | |
6683 | int dbl; | |
6684 | const char *s, *s2, *s3; | |
6685 | ||
6686 | mask = ip->insn_mo->mask; | |
6687 | ||
6688 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
6689 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
6690 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
6691 | ||
6692 | icnt = 0; | |
6693 | ||
6694 | expr1.X_op = O_constant; | |
6695 | expr1.X_op_symbol = NULL; | |
6696 | expr1.X_add_symbol = NULL; | |
6697 | expr1.X_add_number = 1; | |
6698 | ||
6699 | dbl = 0; | |
6700 | ||
6701 | switch (mask) | |
6702 | { | |
6703 | default: | |
6704 | internalError (); | |
6705 | ||
6706 | case M_DDIV_3: | |
6707 | dbl = 1; | |
6708 | case M_DIV_3: | |
6709 | s = "mflo"; | |
6710 | goto do_div3; | |
6711 | case M_DREM_3: | |
6712 | dbl = 1; | |
6713 | case M_REM_3: | |
6714 | s = "mfhi"; | |
6715 | do_div3: | |
6716 | mips_emit_delays (true); | |
6717 | ++mips_opts.noreorder; | |
6718 | mips_any_noreorder = 1; | |
6719 | macro_build ((char *) NULL, &icnt, NULL, | |
6720 | dbl ? "ddiv" : "div", | |
6721 | "0,x,y", xreg, yreg); | |
6722 | expr1.X_add_number = 2; | |
6723 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
6724 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); | |
6725 | ||
6726 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, | |
6727 | since that causes an overflow. We should do that as well, | |
6728 | but I don't see how to do the comparisons without a temporary | |
6729 | register. */ | |
6730 | --mips_opts.noreorder; | |
6731 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); | |
6732 | break; | |
6733 | ||
6734 | case M_DIVU_3: | |
6735 | s = "divu"; | |
6736 | s2 = "mflo"; | |
6737 | goto do_divu3; | |
6738 | case M_REMU_3: | |
6739 | s = "divu"; | |
6740 | s2 = "mfhi"; | |
6741 | goto do_divu3; | |
6742 | case M_DDIVU_3: | |
6743 | s = "ddivu"; | |
6744 | s2 = "mflo"; | |
6745 | goto do_divu3; | |
6746 | case M_DREMU_3: | |
6747 | s = "ddivu"; | |
6748 | s2 = "mfhi"; | |
6749 | do_divu3: | |
6750 | mips_emit_delays (true); | |
6751 | ++mips_opts.noreorder; | |
6752 | mips_any_noreorder = 1; | |
6753 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
6754 | expr1.X_add_number = 2; | |
6755 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
6756 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); | |
6757 | --mips_opts.noreorder; | |
6758 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); | |
6759 | break; | |
6760 | ||
6761 | case M_DMUL: | |
6762 | dbl = 1; | |
6763 | case M_MUL: | |
6764 | macro_build ((char *) NULL, &icnt, NULL, | |
6765 | dbl ? "dmultu" : "multu", | |
6766 | "x,y", xreg, yreg); | |
6767 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "x", zreg); | |
6768 | return; | |
6769 | ||
6770 | case M_DSUBU_I: | |
6771 | dbl = 1; | |
6772 | goto do_subu; | |
6773 | case M_SUBU_I: | |
6774 | do_subu: | |
6775 | if (imm_expr.X_op != O_constant) | |
6776 | as_bad (_("Unsupported large constant")); | |
6777 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6778 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6779 | dbl ? "daddiu" : "addiu", | |
6780 | "y,x,4", yreg, xreg); | |
6781 | break; | |
6782 | ||
6783 | case M_SUBU_I_2: | |
6784 | if (imm_expr.X_op != O_constant) | |
6785 | as_bad (_("Unsupported large constant")); | |
6786 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6787 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
6788 | "x,k", xreg); | |
6789 | break; | |
6790 | ||
6791 | case M_DSUBU_I_2: | |
6792 | if (imm_expr.X_op != O_constant) | |
6793 | as_bad (_("Unsupported large constant")); | |
6794 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6795 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
6796 | "y,j", yreg); | |
6797 | break; | |
6798 | ||
6799 | case M_BEQ: | |
6800 | s = "cmp"; | |
6801 | s2 = "bteqz"; | |
6802 | goto do_branch; | |
6803 | case M_BNE: | |
6804 | s = "cmp"; | |
6805 | s2 = "btnez"; | |
6806 | goto do_branch; | |
6807 | case M_BLT: | |
6808 | s = "slt"; | |
6809 | s2 = "btnez"; | |
6810 | goto do_branch; | |
6811 | case M_BLTU: | |
6812 | s = "sltu"; | |
6813 | s2 = "btnez"; | |
6814 | goto do_branch; | |
6815 | case M_BLE: | |
6816 | s = "slt"; | |
6817 | s2 = "bteqz"; | |
6818 | goto do_reverse_branch; | |
6819 | case M_BLEU: | |
6820 | s = "sltu"; | |
6821 | s2 = "bteqz"; | |
6822 | goto do_reverse_branch; | |
6823 | case M_BGE: | |
6824 | s = "slt"; | |
6825 | s2 = "bteqz"; | |
6826 | goto do_branch; | |
6827 | case M_BGEU: | |
6828 | s = "sltu"; | |
6829 | s2 = "bteqz"; | |
6830 | goto do_branch; | |
6831 | case M_BGT: | |
6832 | s = "slt"; | |
6833 | s2 = "btnez"; | |
6834 | goto do_reverse_branch; | |
6835 | case M_BGTU: | |
6836 | s = "sltu"; | |
6837 | s2 = "btnez"; | |
6838 | ||
6839 | do_reverse_branch: | |
6840 | tmp = xreg; | |
6841 | xreg = yreg; | |
6842 | yreg = tmp; | |
6843 | ||
6844 | do_branch: | |
6845 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
6846 | xreg, yreg); | |
6847 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6848 | break; | |
6849 | ||
6850 | case M_BEQ_I: | |
6851 | s = "cmpi"; | |
6852 | s2 = "bteqz"; | |
6853 | s3 = "x,U"; | |
6854 | goto do_branch_i; | |
6855 | case M_BNE_I: | |
6856 | s = "cmpi"; | |
6857 | s2 = "btnez"; | |
6858 | s3 = "x,U"; | |
6859 | goto do_branch_i; | |
6860 | case M_BLT_I: | |
6861 | s = "slti"; | |
6862 | s2 = "btnez"; | |
6863 | s3 = "x,8"; | |
6864 | goto do_branch_i; | |
6865 | case M_BLTU_I: | |
6866 | s = "sltiu"; | |
6867 | s2 = "btnez"; | |
6868 | s3 = "x,8"; | |
6869 | goto do_branch_i; | |
6870 | case M_BLE_I: | |
6871 | s = "slti"; | |
6872 | s2 = "btnez"; | |
6873 | s3 = "x,8"; | |
6874 | goto do_addone_branch_i; | |
6875 | case M_BLEU_I: | |
6876 | s = "sltiu"; | |
6877 | s2 = "btnez"; | |
6878 | s3 = "x,8"; | |
6879 | goto do_addone_branch_i; | |
6880 | case M_BGE_I: | |
6881 | s = "slti"; | |
6882 | s2 = "bteqz"; | |
6883 | s3 = "x,8"; | |
6884 | goto do_branch_i; | |
6885 | case M_BGEU_I: | |
6886 | s = "sltiu"; | |
6887 | s2 = "bteqz"; | |
6888 | s3 = "x,8"; | |
6889 | goto do_branch_i; | |
6890 | case M_BGT_I: | |
6891 | s = "slti"; | |
6892 | s2 = "bteqz"; | |
6893 | s3 = "x,8"; | |
6894 | goto do_addone_branch_i; | |
6895 | case M_BGTU_I: | |
6896 | s = "sltiu"; | |
6897 | s2 = "bteqz"; | |
6898 | s3 = "x,8"; | |
6899 | ||
6900 | do_addone_branch_i: | |
6901 | if (imm_expr.X_op != O_constant) | |
6902 | as_bad (_("Unsupported large constant")); | |
6903 | ++imm_expr.X_add_number; | |
6904 | ||
6905 | do_branch_i: | |
6906 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
6907 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6908 | break; | |
6909 | ||
6910 | case M_ABS: | |
6911 | expr1.X_add_number = 0; | |
6912 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
6913 | if (xreg != yreg) | |
6914 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6915 | "move", "y,X", xreg, yreg); | |
6916 | expr1.X_add_number = 2; | |
6917 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
6918 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6919 | "neg", "x,w", xreg, xreg); | |
6920 | } | |
6921 | } | |
6922 | ||
6923 | /* For consistency checking, verify that all bits are specified either | |
6924 | by the match/mask part of the instruction definition, or by the | |
6925 | operand list. */ | |
6926 | static int | |
6927 | validate_mips_insn (opc) | |
6928 | const struct mips_opcode *opc; | |
6929 | { | |
6930 | const char *p = opc->args; | |
6931 | char c; | |
6932 | unsigned long used_bits = opc->mask; | |
6933 | ||
6934 | if ((used_bits & opc->match) != opc->match) | |
6935 | { | |
6936 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
6937 | opc->name, opc->args); | |
6938 | return 0; | |
6939 | } | |
6940 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
6941 | while (*p) | |
6942 | switch (c = *p++) | |
6943 | { | |
6944 | case ',': break; | |
6945 | case '(': break; | |
6946 | case ')': break; | |
6947 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
6948 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
6949 | case 'A': break; | |
6950 | case 'B': USE_BITS (OP_MASK_SYSCALL, OP_SH_SYSCALL); break; | |
6951 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; | |
6952 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
6953 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6954 | case 'F': break; | |
6955 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
6956 | case 'I': break; | |
6957 | case 'L': break; | |
6958 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
6959 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
6960 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; | |
6961 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
6962 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
6963 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
6964 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
6965 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; | |
6966 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6967 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
6968 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
6969 | case 'f': break; | |
6970 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
6971 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
6972 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6973 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
6974 | case 'l': break; | |
6975 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6976 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6977 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
6978 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6979 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6980 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6981 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
6982 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6983 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6984 | case 'x': break; | |
6985 | case 'z': break; | |
6986 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
6987 | default: | |
6988 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
6989 | c, opc->name, opc->args); | |
6990 | return 0; | |
6991 | } | |
6992 | #undef USE_BITS | |
6993 | if (used_bits != 0xffffffff) | |
6994 | { | |
6995 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
6996 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
6997 | return 0; | |
6998 | } | |
6999 | return 1; | |
7000 | } | |
7001 | ||
7002 | /* This routine assembles an instruction into its binary format. As a | |
7003 | side effect, it sets one of the global variables imm_reloc or | |
7004 | offset_reloc to the type of relocation to do if one of the operands | |
7005 | is an address expression. */ | |
7006 | ||
7007 | static void | |
7008 | mips_ip (str, ip) | |
7009 | char *str; | |
7010 | struct mips_cl_insn *ip; | |
7011 | { | |
7012 | char *s; | |
7013 | const char *args; | |
43841e91 | 7014 | char c = 0; |
252b5132 RH |
7015 | struct mips_opcode *insn; |
7016 | char *argsStart; | |
7017 | unsigned int regno; | |
7018 | unsigned int lastregno = 0; | |
7019 | char *s_reset; | |
7020 | char save_c = 0; | |
7021 | int full_opcode_match = 1; | |
7022 | ||
7023 | insn_error = NULL; | |
7024 | ||
7025 | /* If the instruction contains a '.', we first try to match an instruction | |
7026 | including the '.'. Then we try again without the '.'. */ | |
7027 | insn = NULL; | |
d9a62219 | 7028 | for (s = str; *s != '\0' && !isspace ((unsigned char) *s); ++s) |
252b5132 RH |
7029 | continue; |
7030 | ||
7031 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7032 | the call to hash_find. Save the character we replaced just in case we | |
7033 | have to re-parse the instruction. */ | |
d9a62219 | 7034 | if (isspace ((unsigned char) *s)) |
252b5132 RH |
7035 | { |
7036 | save_c = *s; | |
7037 | *s++ = '\0'; | |
7038 | } | |
7039 | ||
7040 | insn = (struct mips_opcode *) hash_find (op_hash, str); | |
7041 | ||
7042 | /* If we didn't find the instruction in the opcode table, try again, but | |
7043 | this time with just the instruction up to, but not including the | |
7044 | first '.'. */ | |
7045 | if (insn == NULL) | |
7046 | { | |
7047 | /* Restore the character we overwrite above (if any). */ | |
7048 | if (save_c) | |
7049 | *(--s) = save_c; | |
7050 | ||
7051 | /* Scan up to the first '.' or whitespace. */ | |
d9a62219 | 7052 | for (s = str; *s != '\0' && *s != '.' && !isspace ((unsigned char) *s); ++s) |
252b5132 RH |
7053 | continue; |
7054 | ||
7055 | /* If we did not find a '.', then we can quit now. */ | |
7056 | if (*s != '.') | |
7057 | { | |
7058 | insn_error = "unrecognized opcode"; | |
7059 | return; | |
7060 | } | |
7061 | ||
7062 | /* Lookup the instruction in the hash table. */ | |
7063 | *s++ = '\0'; | |
7064 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7065 | { | |
7066 | insn_error = "unrecognized opcode"; | |
7067 | return; | |
7068 | } | |
7069 | ||
7070 | full_opcode_match = 0; | |
7071 | } | |
7072 | ||
7073 | argsStart = s; | |
7074 | for (;;) | |
7075 | { | |
252b5132 RH |
7076 | boolean ok; |
7077 | ||
7078 | assert (strcmp (insn->name, str) == 0); | |
7079 | ||
c97ef257 | 7080 | if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_cpu, mips_gp32)) |
252b5132 | 7081 | ok = true; |
2bd7f1f3 | 7082 | else |
252b5132 | 7083 | ok = false; |
2bd7f1f3 | 7084 | |
252b5132 RH |
7085 | if (insn->pinfo != INSN_MACRO) |
7086 | { | |
7087 | if (mips_cpu == 4650 && (insn->pinfo & FP_D) != 0) | |
7088 | ok = false; | |
7089 | } | |
7090 | ||
7091 | if (! ok) | |
7092 | { | |
7093 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7094 | && strcmp (insn->name, insn[1].name) == 0) | |
7095 | { | |
7096 | ++insn; | |
7097 | continue; | |
7098 | } | |
252b5132 | 7099 | else |
43841e91 | 7100 | { |
252b5132 | 7101 | static char buf[100]; |
2bd7f1f3 GRK |
7102 | sprintf (buf, |
7103 | _("opcode not supported on this processor: %d (MIPS%d)"), | |
7104 | mips_cpu, mips_opts.isa); | |
7105 | ||
252b5132 | 7106 | insn_error = buf; |
2bd7f1f3 | 7107 | return; |
252b5132 | 7108 | } |
252b5132 RH |
7109 | } |
7110 | ||
7111 | ip->insn_mo = insn; | |
7112 | ip->insn_opcode = insn->match; | |
7113 | for (args = insn->args;; ++args) | |
7114 | { | |
7115 | if (*s == ' ') | |
7116 | ++s; | |
7117 | switch (*args) | |
7118 | { | |
7119 | case '\0': /* end of args */ | |
7120 | if (*s == '\0') | |
7121 | return; | |
7122 | break; | |
7123 | ||
7124 | case ',': | |
7125 | if (*s++ == *args) | |
7126 | continue; | |
7127 | s--; | |
7128 | switch (*++args) | |
7129 | { | |
7130 | case 'r': | |
7131 | case 'v': | |
7132 | ip->insn_opcode |= lastregno << 21; | |
7133 | continue; | |
7134 | ||
7135 | case 'w': | |
7136 | case 'W': | |
7137 | ip->insn_opcode |= lastregno << 16; | |
7138 | continue; | |
7139 | ||
7140 | case 'V': | |
7141 | ip->insn_opcode |= lastregno << 11; | |
7142 | continue; | |
7143 | } | |
7144 | break; | |
7145 | ||
7146 | case '(': | |
7147 | /* Handle optional base register. | |
7148 | Either the base register is omitted or | |
7149 | we must have a left paren. */ | |
7150 | /* This is dependent on the next operand specifier | |
7151 | is a base register specification. */ | |
7152 | assert (args[1] == 'b' || args[1] == '5' | |
7153 | || args[1] == '-' || args[1] == '4'); | |
7154 | if (*s == '\0') | |
7155 | return; | |
7156 | ||
7157 | case ')': /* these must match exactly */ | |
7158 | if (*s++ == *args) | |
7159 | continue; | |
7160 | break; | |
7161 | ||
7162 | case '<': /* must be at least one digit */ | |
7163 | /* | |
7164 | * According to the manual, if the shift amount is greater | |
7165 | * than 31 or less than 0 the the shift amount should be | |
7166 | * mod 32. In reality the mips assembler issues an error. | |
7167 | * We issue a warning and mask out all but the low 5 bits. | |
7168 | */ | |
7169 | my_getExpression (&imm_expr, s); | |
7170 | check_absolute_expr (ip, &imm_expr); | |
7171 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7172 | { | |
7173 | as_warn (_("Improper shift amount (%ld)"), | |
7174 | (long) imm_expr.X_add_number); | |
7175 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; | |
7176 | } | |
7177 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
7178 | imm_expr.X_op = O_absent; | |
7179 | s = expr_end; | |
7180 | continue; | |
7181 | ||
7182 | case '>': /* shift amount minus 32 */ | |
7183 | my_getExpression (&imm_expr, s); | |
7184 | check_absolute_expr (ip, &imm_expr); | |
7185 | if ((unsigned long) imm_expr.X_add_number < 32 | |
7186 | || (unsigned long) imm_expr.X_add_number > 63) | |
7187 | break; | |
7188 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
7189 | imm_expr.X_op = O_absent; | |
7190 | s = expr_end; | |
7191 | continue; | |
7192 | ||
7193 | ||
7194 | case 'k': /* cache code */ | |
7195 | case 'h': /* prefx code */ | |
7196 | my_getExpression (&imm_expr, s); | |
7197 | check_absolute_expr (ip, &imm_expr); | |
7198 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7199 | { | |
7200 | as_warn (_("Invalid value for `%s' (%lu)"), | |
7201 | ip->insn_mo->name, | |
7202 | (unsigned long) imm_expr.X_add_number); | |
7203 | imm_expr.X_add_number &= 0x1f; | |
7204 | } | |
7205 | if (*args == 'k') | |
7206 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
7207 | else | |
7208 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
7209 | imm_expr.X_op = O_absent; | |
7210 | s = expr_end; | |
7211 | continue; | |
7212 | ||
7213 | case 'c': /* break code */ | |
7214 | my_getExpression (&imm_expr, s); | |
7215 | check_absolute_expr (ip, &imm_expr); | |
7216 | if ((unsigned) imm_expr.X_add_number > 1023) | |
7217 | { | |
7218 | as_warn (_("Illegal break code (%ld)"), | |
7219 | (long) imm_expr.X_add_number); | |
7220 | imm_expr.X_add_number &= 0x3ff; | |
7221 | } | |
7222 | ip->insn_opcode |= imm_expr.X_add_number << 16; | |
7223 | imm_expr.X_op = O_absent; | |
7224 | s = expr_end; | |
7225 | continue; | |
7226 | ||
7227 | case 'q': /* lower break code */ | |
7228 | my_getExpression (&imm_expr, s); | |
7229 | check_absolute_expr (ip, &imm_expr); | |
7230 | if ((unsigned) imm_expr.X_add_number > 1023) | |
7231 | { | |
7232 | as_warn (_("Illegal lower break code (%ld)"), | |
7233 | (long) imm_expr.X_add_number); | |
7234 | imm_expr.X_add_number &= 0x3ff; | |
7235 | } | |
7236 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
7237 | imm_expr.X_op = O_absent; | |
7238 | s = expr_end; | |
7239 | continue; | |
7240 | ||
7241 | case 'B': /* syscall code */ | |
7242 | my_getExpression (&imm_expr, s); | |
7243 | check_absolute_expr (ip, &imm_expr); | |
7244 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
7245 | as_warn (_("Illegal syscall code (%ld)"), | |
7246 | (long) imm_expr.X_add_number); | |
7247 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
7248 | imm_expr.X_op = O_absent; | |
7249 | s = expr_end; | |
7250 | continue; | |
7251 | ||
7252 | case 'C': /* Coprocessor code */ | |
7253 | my_getExpression (&imm_expr, s); | |
7254 | check_absolute_expr (ip, &imm_expr); | |
7255 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
7256 | { | |
7257 | as_warn (_("Coproccesor code > 25 bits (%ld)"), | |
7258 | (long) imm_expr.X_add_number); | |
7259 | imm_expr.X_add_number &= ((1<<25) - 1); | |
7260 | } | |
7261 | ip->insn_opcode |= imm_expr.X_add_number; | |
7262 | imm_expr.X_op = O_absent; | |
7263 | s = expr_end; | |
7264 | continue; | |
7265 | ||
7266 | case 'P': /* Performance register */ | |
7267 | my_getExpression (&imm_expr, s); | |
7268 | check_absolute_expr (ip, &imm_expr); | |
7269 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) | |
7270 | { | |
7271 | as_warn (_("Invalidate performance regster (%ld)"), | |
7272 | (long) imm_expr.X_add_number); | |
7273 | imm_expr.X_add_number &= 1; | |
7274 | } | |
7275 | ip->insn_opcode |= (imm_expr.X_add_number << 1); | |
7276 | imm_expr.X_op = O_absent; | |
7277 | s = expr_end; | |
7278 | continue; | |
7279 | ||
7280 | case 'b': /* base register */ | |
7281 | case 'd': /* destination register */ | |
7282 | case 's': /* source register */ | |
7283 | case 't': /* target register */ | |
7284 | case 'r': /* both target and source */ | |
7285 | case 'v': /* both dest and source */ | |
7286 | case 'w': /* both dest and target */ | |
7287 | case 'E': /* coprocessor target register */ | |
7288 | case 'G': /* coprocessor destination register */ | |
7289 | case 'x': /* ignore register name */ | |
7290 | case 'z': /* must be zero register */ | |
7291 | s_reset = s; | |
7292 | if (s[0] == '$') | |
7293 | { | |
7294 | ||
d9a62219 | 7295 | if (isdigit ((unsigned char) s[1])) |
252b5132 RH |
7296 | { |
7297 | ++s; | |
7298 | regno = 0; | |
7299 | do | |
7300 | { | |
7301 | regno *= 10; | |
7302 | regno += *s - '0'; | |
7303 | ++s; | |
7304 | } | |
d9a62219 | 7305 | while (isdigit ((unsigned char) *s)); |
252b5132 RH |
7306 | if (regno > 31) |
7307 | as_bad (_("Invalid register number (%d)"), regno); | |
7308 | } | |
7309 | else if (*args == 'E' || *args == 'G') | |
7310 | goto notreg; | |
7311 | else | |
7312 | { | |
7313 | if (s[1] == 'f' && s[2] == 'p') | |
7314 | { | |
7315 | s += 3; | |
7316 | regno = FP; | |
7317 | } | |
7318 | else if (s[1] == 's' && s[2] == 'p') | |
7319 | { | |
7320 | s += 3; | |
7321 | regno = SP; | |
7322 | } | |
7323 | else if (s[1] == 'g' && s[2] == 'p') | |
7324 | { | |
7325 | s += 3; | |
7326 | regno = GP; | |
7327 | } | |
7328 | else if (s[1] == 'a' && s[2] == 't') | |
7329 | { | |
7330 | s += 3; | |
7331 | regno = AT; | |
7332 | } | |
7333 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
7334 | { | |
7335 | s += 4; | |
7336 | regno = KT0; | |
7337 | } | |
7338 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7339 | { | |
7340 | s += 4; | |
7341 | regno = KT1; | |
7342 | } | |
7343 | else if (itbl_have_entries) | |
7344 | { | |
7345 | char *p, *n; | |
d7ba4a77 | 7346 | unsigned long r; |
252b5132 | 7347 | |
d7ba4a77 | 7348 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
7349 | n = itbl_get_field (&p); /* n is name */ |
7350 | ||
d7ba4a77 ILT |
7351 | /* See if this is a register defined in an |
7352 | itbl entry. */ | |
7353 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
7354 | { |
7355 | /* Get_field advances to the start of | |
7356 | the next field, so we need to back | |
d7ba4a77 | 7357 | rack to the end of the last field. */ |
252b5132 RH |
7358 | if (p) |
7359 | s = p - 1; | |
7360 | else | |
d7ba4a77 | 7361 | s = strchr (s, '\0'); |
252b5132 RH |
7362 | regno = r; |
7363 | } | |
7364 | else | |
7365 | goto notreg; | |
7366 | } | |
7367 | else | |
7368 | goto notreg; | |
7369 | } | |
7370 | if (regno == AT | |
7371 | && ! mips_opts.noat | |
7372 | && *args != 'E' | |
7373 | && *args != 'G') | |
7374 | as_warn (_("Used $at without \".set noat\"")); | |
7375 | c = *args; | |
7376 | if (*s == ' ') | |
7377 | s++; | |
7378 | if (args[1] != *s) | |
7379 | { | |
7380 | if (c == 'r' || c == 'v' || c == 'w') | |
7381 | { | |
7382 | regno = lastregno; | |
7383 | s = s_reset; | |
7384 | args++; | |
7385 | } | |
7386 | } | |
7387 | /* 'z' only matches $0. */ | |
7388 | if (c == 'z' && regno != 0) | |
7389 | break; | |
7390 | ||
7391 | /* Now that we have assembled one operand, we use the args string | |
7392 | * to figure out where it goes in the instruction. */ | |
7393 | switch (c) | |
7394 | { | |
7395 | case 'r': | |
7396 | case 's': | |
7397 | case 'v': | |
7398 | case 'b': | |
7399 | ip->insn_opcode |= regno << 21; | |
7400 | break; | |
7401 | case 'd': | |
7402 | case 'G': | |
7403 | ip->insn_opcode |= regno << 11; | |
7404 | break; | |
7405 | case 'w': | |
7406 | case 't': | |
7407 | case 'E': | |
7408 | ip->insn_opcode |= regno << 16; | |
7409 | break; | |
7410 | case 'x': | |
7411 | /* This case exists because on the r3000 trunc | |
7412 | expands into a macro which requires a gp | |
7413 | register. On the r6000 or r4000 it is | |
7414 | assembled into a single instruction which | |
7415 | ignores the register. Thus the insn version | |
7416 | is MIPS_ISA2 and uses 'x', and the macro | |
7417 | version is MIPS_ISA1 and uses 't'. */ | |
7418 | break; | |
7419 | case 'z': | |
7420 | /* This case is for the div instruction, which | |
7421 | acts differently if the destination argument | |
7422 | is $0. This only matches $0, and is checked | |
7423 | outside the switch. */ | |
7424 | break; | |
7425 | case 'D': | |
7426 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
7427 | break; | |
7428 | /* What about all other operands like 'i', which | |
7429 | can be specified in the opcode table? */ | |
7430 | } | |
7431 | lastregno = regno; | |
7432 | continue; | |
7433 | } | |
7434 | notreg: | |
7435 | switch (*args++) | |
7436 | { | |
7437 | case 'r': | |
7438 | case 'v': | |
7439 | ip->insn_opcode |= lastregno << 21; | |
7440 | continue; | |
7441 | case 'w': | |
7442 | ip->insn_opcode |= lastregno << 16; | |
7443 | continue; | |
7444 | } | |
7445 | break; | |
7446 | ||
7447 | case 'D': /* floating point destination register */ | |
7448 | case 'S': /* floating point source register */ | |
7449 | case 'T': /* floating point target register */ | |
7450 | case 'R': /* floating point source register */ | |
7451 | case 'V': | |
7452 | case 'W': | |
7453 | s_reset = s; | |
d9a62219 | 7454 | if (s[0] == '$' && s[1] == 'f' && isdigit ((unsigned char) s[2])) |
252b5132 RH |
7455 | { |
7456 | s += 2; | |
7457 | regno = 0; | |
7458 | do | |
7459 | { | |
7460 | regno *= 10; | |
7461 | regno += *s - '0'; | |
7462 | ++s; | |
7463 | } | |
d9a62219 | 7464 | while (isdigit ((unsigned char) *s)); |
252b5132 RH |
7465 | |
7466 | if (regno > 31) | |
7467 | as_bad (_("Invalid float register number (%d)"), regno); | |
7468 | ||
7469 | if ((regno & 1) != 0 | |
9ce8a5dd | 7470 | && ! ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 RH |
7471 | && ! (strcmp (str, "mtc1") == 0 |
7472 | || strcmp (str, "mfc1") == 0 | |
7473 | || strcmp (str, "lwc1") == 0 | |
7474 | || strcmp (str, "swc1") == 0 | |
7475 | || strcmp (str, "l.s") == 0 | |
7476 | || strcmp (str, "s.s") == 0)) | |
7477 | as_warn (_("Float register should be even, was %d"), | |
7478 | regno); | |
7479 | ||
7480 | c = *args; | |
7481 | if (*s == ' ') | |
7482 | s++; | |
7483 | if (args[1] != *s) | |
7484 | { | |
7485 | if (c == 'V' || c == 'W') | |
7486 | { | |
7487 | regno = lastregno; | |
7488 | s = s_reset; | |
7489 | args++; | |
7490 | } | |
7491 | } | |
7492 | switch (c) | |
7493 | { | |
7494 | case 'D': | |
7495 | ip->insn_opcode |= regno << 6; | |
7496 | break; | |
7497 | case 'V': | |
7498 | case 'S': | |
7499 | ip->insn_opcode |= regno << 11; | |
7500 | break; | |
7501 | case 'W': | |
7502 | case 'T': | |
7503 | ip->insn_opcode |= regno << 16; | |
7504 | break; | |
7505 | case 'R': | |
7506 | ip->insn_opcode |= regno << 21; | |
7507 | break; | |
7508 | } | |
7509 | lastregno = regno; | |
7510 | continue; | |
7511 | } | |
7512 | ||
7513 | ||
7514 | switch (*args++) | |
7515 | { | |
7516 | case 'V': | |
7517 | ip->insn_opcode |= lastregno << 11; | |
7518 | continue; | |
7519 | case 'W': | |
7520 | ip->insn_opcode |= lastregno << 16; | |
7521 | continue; | |
7522 | } | |
7523 | break; | |
7524 | ||
7525 | case 'I': | |
7526 | my_getExpression (&imm_expr, s); | |
7527 | if (imm_expr.X_op != O_big | |
7528 | && imm_expr.X_op != O_constant) | |
7529 | insn_error = _("absolute expression required"); | |
7530 | s = expr_end; | |
7531 | continue; | |
7532 | ||
7533 | case 'A': | |
7534 | my_getExpression (&offset_expr, s); | |
7535 | imm_reloc = BFD_RELOC_32; | |
7536 | s = expr_end; | |
7537 | continue; | |
7538 | ||
7539 | case 'F': | |
7540 | case 'L': | |
7541 | case 'f': | |
7542 | case 'l': | |
7543 | { | |
7544 | int f64; | |
7545 | char *save_in; | |
7546 | char *err; | |
7547 | unsigned char temp[8]; | |
7548 | int len; | |
7549 | unsigned int length; | |
7550 | segT seg; | |
7551 | subsegT subseg; | |
7552 | char *p; | |
7553 | ||
7554 | /* These only appear as the last operand in an | |
7555 | instruction, and every instruction that accepts | |
7556 | them in any variant accepts them in all variants. | |
7557 | This means we don't have to worry about backing out | |
7558 | any changes if the instruction does not match. | |
7559 | ||
7560 | The difference between them is the size of the | |
7561 | floating point constant and where it goes. For 'F' | |
7562 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
7563 | is 32 bits. Where the constant is placed is based | |
7564 | on how the MIPS assembler does things: | |
7565 | F -- .rdata | |
7566 | L -- .lit8 | |
7567 | f -- immediate value | |
7568 | l -- .lit4 | |
7569 | ||
7570 | The .lit4 and .lit8 sections are only used if | |
7571 | permitted by the -G argument. | |
7572 | ||
7573 | When generating embedded PIC code, we use the | |
7574 | .lit8 section but not the .lit4 section (we can do | |
7575 | .lit4 inline easily; we need to put .lit8 | |
7576 | somewhere in the data segment, and using .lit8 | |
7577 | permits the linker to eventually combine identical | |
7578 | .lit8 entries). */ | |
7579 | ||
7580 | f64 = *args == 'F' || *args == 'L'; | |
7581 | ||
7582 | save_in = input_line_pointer; | |
7583 | input_line_pointer = s; | |
7584 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
7585 | length = len; | |
7586 | s = input_line_pointer; | |
7587 | input_line_pointer = save_in; | |
7588 | if (err != NULL && *err != '\0') | |
7589 | { | |
7590 | as_bad (_("Bad floating point constant: %s"), err); | |
7591 | memset (temp, '\0', sizeof temp); | |
7592 | length = f64 ? 8 : 4; | |
7593 | } | |
7594 | ||
7595 | assert (length == (f64 ? 8 : 4)); | |
7596 | ||
7597 | if (*args == 'f' | |
7598 | || (*args == 'l' | |
7599 | && (! USE_GLOBAL_POINTER_OPT | |
7600 | || mips_pic == EMBEDDED_PIC | |
7601 | || g_switch_value < 4 | |
7602 | || (temp[0] == 0 && temp[1] == 0) | |
7603 | || (temp[2] == 0 && temp[3] == 0)))) | |
7604 | { | |
7605 | imm_expr.X_op = O_constant; | |
7606 | if (! target_big_endian) | |
7607 | imm_expr.X_add_number = bfd_getl32 (temp); | |
7608 | else | |
7609 | imm_expr.X_add_number = bfd_getb32 (temp); | |
7610 | } | |
7611 | else if (length > 4 | |
119d663a | 7612 | && ! mips_disable_float_construction |
252b5132 RH |
7613 | && ((temp[0] == 0 && temp[1] == 0) |
7614 | || (temp[2] == 0 && temp[3] == 0)) | |
7615 | && ((temp[4] == 0 && temp[5] == 0) | |
7616 | || (temp[6] == 0 && temp[7] == 0))) | |
7617 | { | |
7618 | /* The value is simple enough to load with a | |
7619 | couple of instructions. In mips1 mode, set | |
7620 | imm_expr to the high order 32 bits and | |
7621 | offset_expr to the low order 32 bits. | |
7622 | Otherwise, set imm_expr to the entire 64 bit | |
7623 | constant. */ | |
9ce8a5dd | 7624 | if (! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
7625 | { |
7626 | imm_expr.X_op = O_constant; | |
7627 | offset_expr.X_op = O_constant; | |
7628 | if (! target_big_endian) | |
7629 | { | |
7630 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
7631 | offset_expr.X_add_number = bfd_getl32 (temp); | |
7632 | } | |
7633 | else | |
7634 | { | |
7635 | imm_expr.X_add_number = bfd_getb32 (temp); | |
7636 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
7637 | } | |
7638 | if (offset_expr.X_add_number == 0) | |
7639 | offset_expr.X_op = O_absent; | |
7640 | } | |
7641 | else if (sizeof (imm_expr.X_add_number) > 4) | |
7642 | { | |
7643 | imm_expr.X_op = O_constant; | |
7644 | if (! target_big_endian) | |
7645 | imm_expr.X_add_number = bfd_getl64 (temp); | |
7646 | else | |
7647 | imm_expr.X_add_number = bfd_getb64 (temp); | |
7648 | } | |
7649 | else | |
7650 | { | |
7651 | imm_expr.X_op = O_big; | |
7652 | imm_expr.X_add_number = 4; | |
7653 | if (! target_big_endian) | |
7654 | { | |
7655 | generic_bignum[0] = bfd_getl16 (temp); | |
7656 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
7657 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
7658 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
7659 | } | |
7660 | else | |
7661 | { | |
7662 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
7663 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
7664 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
7665 | generic_bignum[3] = bfd_getb16 (temp); | |
7666 | } | |
7667 | } | |
7668 | } | |
7669 | else | |
7670 | { | |
7671 | const char *newname; | |
7672 | segT new_seg; | |
7673 | ||
7674 | /* Switch to the right section. */ | |
7675 | seg = now_seg; | |
7676 | subseg = now_subseg; | |
7677 | switch (*args) | |
7678 | { | |
7679 | default: /* unused default case avoids warnings. */ | |
7680 | case 'L': | |
7681 | newname = RDATA_SECTION_NAME; | |
bb2d6cd7 GK |
7682 | if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
7683 | || mips_pic == EMBEDDED_PIC) | |
252b5132 RH |
7684 | newname = ".lit8"; |
7685 | break; | |
7686 | case 'F': | |
bb2d6cd7 GK |
7687 | if (mips_pic == EMBEDDED_PIC) |
7688 | newname = ".lit8"; | |
7689 | else | |
7690 | newname = RDATA_SECTION_NAME; | |
252b5132 RH |
7691 | break; |
7692 | case 'l': | |
7693 | assert (!USE_GLOBAL_POINTER_OPT | |
7694 | || g_switch_value >= 4); | |
7695 | newname = ".lit4"; | |
7696 | break; | |
7697 | } | |
7698 | new_seg = subseg_new (newname, (subsegT) 0); | |
7699 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
7700 | bfd_set_section_flags (stdoutput, new_seg, | |
7701 | (SEC_ALLOC | |
7702 | | SEC_LOAD | |
7703 | | SEC_READONLY | |
7704 | | SEC_DATA)); | |
7705 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
7706 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
7707 | && strcmp (TARGET_OS, "elf") != 0) | |
7708 | record_alignment (new_seg, 4); | |
7709 | else | |
7710 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
7711 | if (seg == now_seg) | |
7712 | as_bad (_("Can't use floating point insn in this section")); | |
7713 | ||
7714 | /* Set the argument to the current address in the | |
7715 | section. */ | |
7716 | offset_expr.X_op = O_symbol; | |
7717 | offset_expr.X_add_symbol = | |
7718 | symbol_new ("L0\001", now_seg, | |
7719 | (valueT) frag_now_fix (), frag_now); | |
7720 | offset_expr.X_add_number = 0; | |
7721 | ||
7722 | /* Put the floating point number into the section. */ | |
7723 | p = frag_more ((int) length); | |
7724 | memcpy (p, temp, length); | |
7725 | ||
7726 | /* Switch back to the original section. */ | |
7727 | subseg_set (seg, subseg); | |
7728 | } | |
7729 | } | |
7730 | continue; | |
7731 | ||
7732 | case 'i': /* 16 bit unsigned immediate */ | |
7733 | case 'j': /* 16 bit signed immediate */ | |
7734 | imm_reloc = BFD_RELOC_LO16; | |
7735 | c = my_getSmallExpression (&imm_expr, s); | |
7736 | if (c != '\0') | |
7737 | { | |
7738 | if (c != 'l') | |
7739 | { | |
7740 | if (imm_expr.X_op == O_constant) | |
7741 | imm_expr.X_add_number = | |
7742 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7743 | else if (c == 'h') | |
7744 | { | |
7745 | imm_reloc = BFD_RELOC_HI16_S; | |
7746 | imm_unmatched_hi = true; | |
7747 | } | |
7748 | else | |
7749 | imm_reloc = BFD_RELOC_HI16; | |
7750 | } | |
7751 | else if (imm_expr.X_op == O_constant) | |
7752 | imm_expr.X_add_number &= 0xffff; | |
7753 | } | |
7754 | if (*args == 'i') | |
7755 | { | |
7756 | if ((c == '\0' && imm_expr.X_op != O_constant) | |
7757 | || ((imm_expr.X_add_number < 0 | |
7758 | || imm_expr.X_add_number >= 0x10000) | |
7759 | && imm_expr.X_op == O_constant)) | |
7760 | { | |
7761 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7762 | !strcmp (insn->name, insn[1].name)) | |
7763 | break; | |
2ae7e77b AH |
7764 | if (imm_expr.X_op == O_constant |
7765 | || imm_expr.X_op == O_big) | |
252b5132 RH |
7766 | as_bad (_("16 bit expression not in range 0..65535")); |
7767 | } | |
7768 | } | |
7769 | else | |
7770 | { | |
7771 | int more; | |
7772 | offsetT max; | |
7773 | ||
7774 | /* The upper bound should be 0x8000, but | |
7775 | unfortunately the MIPS assembler accepts numbers | |
7776 | from 0x8000 to 0xffff and sign extends them, and | |
7777 | we want to be compatible. We only permit this | |
7778 | extended range for an instruction which does not | |
7779 | provide any further alternates, since those | |
7780 | alternates may handle other cases. People should | |
7781 | use the numbers they mean, rather than relying on | |
7782 | a mysterious sign extension. */ | |
7783 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7784 | strcmp (insn->name, insn[1].name) == 0); | |
7785 | if (more) | |
7786 | max = 0x8000; | |
7787 | else | |
7788 | max = 0x10000; | |
7789 | if ((c == '\0' && imm_expr.X_op != O_constant) | |
7790 | || ((imm_expr.X_add_number < -0x8000 | |
7791 | || imm_expr.X_add_number >= max) | |
7792 | && imm_expr.X_op == O_constant) | |
7793 | || (more | |
7794 | && imm_expr.X_add_number < 0 | |
9ce8a5dd | 7795 | && ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 RH |
7796 | && imm_expr.X_unsigned |
7797 | && sizeof (imm_expr.X_add_number) <= 4)) | |
7798 | { | |
7799 | if (more) | |
7800 | break; | |
2ae7e77b AH |
7801 | if (imm_expr.X_op == O_constant |
7802 | || imm_expr.X_op == O_big) | |
252b5132 RH |
7803 | as_bad (_("16 bit expression not in range -32768..32767")); |
7804 | } | |
7805 | } | |
7806 | s = expr_end; | |
7807 | continue; | |
7808 | ||
7809 | case 'o': /* 16 bit offset */ | |
7810 | c = my_getSmallExpression (&offset_expr, s); | |
7811 | ||
7812 | /* If this value won't fit into a 16 bit offset, then go | |
7813 | find a macro that will generate the 32 bit offset | |
7814 | code pattern. As a special hack, we accept the | |
7815 | difference of two local symbols as a constant. This | |
7816 | is required to suppose embedded PIC switches, which | |
7817 | use an instruction which looks like | |
7818 | lw $4,$L12-$LS12($4) | |
7819 | The problem with handling this in a more general | |
7820 | fashion is that the macro function doesn't expect to | |
7821 | see anything which can be handled in a single | |
7822 | constant instruction. */ | |
7823 | if (c == 0 | |
7824 | && (offset_expr.X_op != O_constant | |
7825 | || offset_expr.X_add_number >= 0x8000 | |
7826 | || offset_expr.X_add_number < -0x8000) | |
7827 | && (mips_pic != EMBEDDED_PIC | |
7828 | || offset_expr.X_op != O_subtract | |
252b5132 | 7829 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) |
bb2d6cd7 | 7830 | != now_seg))) |
252b5132 RH |
7831 | break; |
7832 | ||
7833 | if (c == 'h' || c == 'H') | |
7834 | { | |
7835 | if (offset_expr.X_op != O_constant) | |
7836 | break; | |
7837 | offset_expr.X_add_number = | |
7838 | (offset_expr.X_add_number >> 16) & 0xffff; | |
7839 | } | |
7840 | offset_reloc = BFD_RELOC_LO16; | |
7841 | s = expr_end; | |
7842 | continue; | |
7843 | ||
7844 | case 'p': /* pc relative offset */ | |
7845 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
7846 | my_getExpression (&offset_expr, s); | |
7847 | s = expr_end; | |
7848 | continue; | |
7849 | ||
7850 | case 'u': /* upper 16 bits */ | |
7851 | c = my_getSmallExpression (&imm_expr, s); | |
7852 | imm_reloc = BFD_RELOC_LO16; | |
7853 | if (c) | |
7854 | { | |
7855 | if (c != 'l') | |
7856 | { | |
7857 | if (imm_expr.X_op == O_constant) | |
7858 | imm_expr.X_add_number = | |
7859 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7860 | else if (c == 'h') | |
7861 | { | |
7862 | imm_reloc = BFD_RELOC_HI16_S; | |
7863 | imm_unmatched_hi = true; | |
7864 | } | |
7865 | else | |
7866 | imm_reloc = BFD_RELOC_HI16; | |
7867 | } | |
7868 | else if (imm_expr.X_op == O_constant) | |
7869 | imm_expr.X_add_number &= 0xffff; | |
7870 | } | |
7871 | if (imm_expr.X_op == O_constant | |
7872 | && (imm_expr.X_add_number < 0 | |
7873 | || imm_expr.X_add_number >= 0x10000)) | |
7874 | as_bad (_("lui expression not in range 0..65535")); | |
7875 | s = expr_end; | |
7876 | continue; | |
7877 | ||
7878 | case 'a': /* 26 bit address */ | |
7879 | my_getExpression (&offset_expr, s); | |
7880 | s = expr_end; | |
7881 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
7882 | continue; | |
7883 | ||
7884 | case 'N': /* 3 bit branch condition code */ | |
7885 | case 'M': /* 3 bit compare condition code */ | |
7886 | if (strncmp (s, "$fcc", 4) != 0) | |
7887 | break; | |
7888 | s += 4; | |
7889 | regno = 0; | |
7890 | do | |
7891 | { | |
7892 | regno *= 10; | |
7893 | regno += *s - '0'; | |
7894 | ++s; | |
7895 | } | |
d9a62219 | 7896 | while (isdigit ((unsigned char) *s)); |
252b5132 RH |
7897 | if (regno > 7) |
7898 | as_bad (_("invalid condition code register $fcc%d"), regno); | |
7899 | if (*args == 'N') | |
7900 | ip->insn_opcode |= regno << OP_SH_BCC; | |
7901 | else | |
7902 | ip->insn_opcode |= regno << OP_SH_CCC; | |
7903 | continue; | |
7904 | ||
7905 | default: | |
7906 | as_bad (_("bad char = '%c'\n"), *args); | |
7907 | internalError (); | |
7908 | } | |
7909 | break; | |
7910 | } | |
7911 | /* Args don't match. */ | |
7912 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7913 | !strcmp (insn->name, insn[1].name)) | |
7914 | { | |
7915 | ++insn; | |
7916 | s = argsStart; | |
7917 | continue; | |
7918 | } | |
7919 | insn_error = _("illegal operands"); | |
7920 | return; | |
7921 | } | |
7922 | } | |
7923 | ||
7924 | /* This routine assembles an instruction into its binary format when | |
7925 | assembling for the mips16. As a side effect, it sets one of the | |
7926 | global variables imm_reloc or offset_reloc to the type of | |
7927 | relocation to do if one of the operands is an address expression. | |
7928 | It also sets mips16_small and mips16_ext if the user explicitly | |
7929 | requested a small or extended instruction. */ | |
7930 | ||
7931 | static void | |
7932 | mips16_ip (str, ip) | |
7933 | char *str; | |
7934 | struct mips_cl_insn *ip; | |
7935 | { | |
7936 | char *s; | |
7937 | const char *args; | |
7938 | struct mips_opcode *insn; | |
7939 | char *argsstart; | |
7940 | unsigned int regno; | |
7941 | unsigned int lastregno = 0; | |
7942 | char *s_reset; | |
7943 | ||
7944 | insn_error = NULL; | |
7945 | ||
7946 | mips16_small = false; | |
7947 | mips16_ext = false; | |
7948 | ||
d9a62219 | 7949 | for (s = str; islower ((unsigned char) *s); ++s) |
252b5132 RH |
7950 | ; |
7951 | switch (*s) | |
7952 | { | |
7953 | case '\0': | |
7954 | break; | |
7955 | ||
7956 | case ' ': | |
7957 | *s++ = '\0'; | |
7958 | break; | |
7959 | ||
7960 | case '.': | |
7961 | if (s[1] == 't' && s[2] == ' ') | |
7962 | { | |
7963 | *s = '\0'; | |
7964 | mips16_small = true; | |
7965 | s += 3; | |
7966 | break; | |
7967 | } | |
7968 | else if (s[1] == 'e' && s[2] == ' ') | |
7969 | { | |
7970 | *s = '\0'; | |
7971 | mips16_ext = true; | |
7972 | s += 3; | |
7973 | break; | |
7974 | } | |
7975 | /* Fall through. */ | |
7976 | default: | |
7977 | insn_error = _("unknown opcode"); | |
7978 | return; | |
7979 | } | |
7980 | ||
7981 | if (mips_opts.noautoextend && ! mips16_ext) | |
7982 | mips16_small = true; | |
7983 | ||
7984 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
7985 | { | |
7986 | insn_error = _("unrecognized opcode"); | |
7987 | return; | |
7988 | } | |
7989 | ||
7990 | argsstart = s; | |
7991 | for (;;) | |
7992 | { | |
7993 | assert (strcmp (insn->name, str) == 0); | |
7994 | ||
7995 | ip->insn_mo = insn; | |
7996 | ip->insn_opcode = insn->match; | |
7997 | ip->use_extend = false; | |
7998 | imm_expr.X_op = O_absent; | |
7999 | imm_reloc = BFD_RELOC_UNUSED; | |
8000 | offset_expr.X_op = O_absent; | |
8001 | offset_reloc = BFD_RELOC_UNUSED; | |
8002 | for (args = insn->args; 1; ++args) | |
8003 | { | |
8004 | int c; | |
8005 | ||
8006 | if (*s == ' ') | |
8007 | ++s; | |
8008 | ||
8009 | /* In this switch statement we call break if we did not find | |
8010 | a match, continue if we did find a match, or return if we | |
8011 | are done. */ | |
8012 | ||
8013 | c = *args; | |
8014 | switch (c) | |
8015 | { | |
8016 | case '\0': | |
8017 | if (*s == '\0') | |
8018 | { | |
8019 | /* Stuff the immediate value in now, if we can. */ | |
8020 | if (imm_expr.X_op == O_constant | |
8021 | && imm_reloc > BFD_RELOC_UNUSED | |
8022 | && insn->pinfo != INSN_MACRO) | |
8023 | { | |
8024 | mips16_immed ((char *) NULL, 0, | |
8025 | imm_reloc - BFD_RELOC_UNUSED, | |
8026 | imm_expr.X_add_number, true, mips16_small, | |
8027 | mips16_ext, &ip->insn_opcode, | |
8028 | &ip->use_extend, &ip->extend); | |
8029 | imm_expr.X_op = O_absent; | |
8030 | imm_reloc = BFD_RELOC_UNUSED; | |
8031 | } | |
8032 | ||
8033 | return; | |
8034 | } | |
8035 | break; | |
8036 | ||
8037 | case ',': | |
8038 | if (*s++ == c) | |
8039 | continue; | |
8040 | s--; | |
8041 | switch (*++args) | |
8042 | { | |
8043 | case 'v': | |
8044 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8045 | continue; | |
8046 | case 'w': | |
8047 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8048 | continue; | |
8049 | } | |
8050 | break; | |
8051 | ||
8052 | case '(': | |
8053 | case ')': | |
8054 | if (*s++ == c) | |
8055 | continue; | |
8056 | break; | |
8057 | ||
8058 | case 'v': | |
8059 | case 'w': | |
8060 | if (s[0] != '$') | |
8061 | { | |
8062 | if (c == 'v') | |
8063 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8064 | else | |
8065 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8066 | ++args; | |
8067 | continue; | |
8068 | } | |
8069 | /* Fall through. */ | |
8070 | case 'x': | |
8071 | case 'y': | |
8072 | case 'z': | |
8073 | case 'Z': | |
8074 | case '0': | |
8075 | case 'S': | |
8076 | case 'R': | |
8077 | case 'X': | |
8078 | case 'Y': | |
8079 | if (s[0] != '$') | |
8080 | break; | |
8081 | s_reset = s; | |
d9a62219 | 8082 | if (isdigit ((unsigned char) s[1])) |
252b5132 RH |
8083 | { |
8084 | ++s; | |
8085 | regno = 0; | |
8086 | do | |
8087 | { | |
8088 | regno *= 10; | |
8089 | regno += *s - '0'; | |
8090 | ++s; | |
8091 | } | |
d9a62219 | 8092 | while (isdigit ((unsigned char) *s)); |
252b5132 RH |
8093 | if (regno > 31) |
8094 | { | |
8095 | as_bad (_("invalid register number (%d)"), regno); | |
8096 | regno = 2; | |
8097 | } | |
8098 | } | |
8099 | else | |
8100 | { | |
8101 | if (s[1] == 'f' && s[2] == 'p') | |
8102 | { | |
8103 | s += 3; | |
8104 | regno = FP; | |
8105 | } | |
8106 | else if (s[1] == 's' && s[2] == 'p') | |
8107 | { | |
8108 | s += 3; | |
8109 | regno = SP; | |
8110 | } | |
8111 | else if (s[1] == 'g' && s[2] == 'p') | |
8112 | { | |
8113 | s += 3; | |
8114 | regno = GP; | |
8115 | } | |
8116 | else if (s[1] == 'a' && s[2] == 't') | |
8117 | { | |
8118 | s += 3; | |
8119 | regno = AT; | |
8120 | } | |
8121 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8122 | { | |
8123 | s += 4; | |
8124 | regno = KT0; | |
8125 | } | |
8126 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8127 | { | |
8128 | s += 4; | |
8129 | regno = KT1; | |
8130 | } | |
8131 | else | |
8132 | break; | |
8133 | } | |
8134 | ||
8135 | if (*s == ' ') | |
8136 | ++s; | |
8137 | if (args[1] != *s) | |
8138 | { | |
8139 | if (c == 'v' || c == 'w') | |
8140 | { | |
8141 | regno = mips16_to_32_reg_map[lastregno]; | |
8142 | s = s_reset; | |
8143 | args++; | |
8144 | } | |
8145 | } | |
8146 | ||
8147 | switch (c) | |
8148 | { | |
8149 | case 'x': | |
8150 | case 'y': | |
8151 | case 'z': | |
8152 | case 'v': | |
8153 | case 'w': | |
8154 | case 'Z': | |
8155 | regno = mips32_to_16_reg_map[regno]; | |
8156 | break; | |
8157 | ||
8158 | case '0': | |
8159 | if (regno != 0) | |
8160 | regno = ILLEGAL_REG; | |
8161 | break; | |
8162 | ||
8163 | case 'S': | |
8164 | if (regno != SP) | |
8165 | regno = ILLEGAL_REG; | |
8166 | break; | |
8167 | ||
8168 | case 'R': | |
8169 | if (regno != RA) | |
8170 | regno = ILLEGAL_REG; | |
8171 | break; | |
8172 | ||
8173 | case 'X': | |
8174 | case 'Y': | |
8175 | if (regno == AT && ! mips_opts.noat) | |
8176 | as_warn (_("used $at without \".set noat\"")); | |
8177 | break; | |
8178 | ||
8179 | default: | |
8180 | internalError (); | |
8181 | } | |
8182 | ||
8183 | if (regno == ILLEGAL_REG) | |
8184 | break; | |
8185 | ||
8186 | switch (c) | |
8187 | { | |
8188 | case 'x': | |
8189 | case 'v': | |
8190 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
8191 | break; | |
8192 | case 'y': | |
8193 | case 'w': | |
8194 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
8195 | break; | |
8196 | case 'z': | |
8197 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
8198 | break; | |
8199 | case 'Z': | |
8200 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
8201 | case '0': | |
8202 | case 'S': | |
8203 | case 'R': | |
8204 | break; | |
8205 | case 'X': | |
8206 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
8207 | break; | |
8208 | case 'Y': | |
8209 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
8210 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
8211 | break; | |
8212 | default: | |
8213 | internalError (); | |
8214 | } | |
8215 | ||
8216 | lastregno = regno; | |
8217 | continue; | |
8218 | ||
8219 | case 'P': | |
8220 | if (strncmp (s, "$pc", 3) == 0) | |
8221 | { | |
8222 | s += 3; | |
8223 | continue; | |
8224 | } | |
8225 | break; | |
8226 | ||
8227 | case '<': | |
8228 | case '>': | |
8229 | case '[': | |
8230 | case ']': | |
8231 | case '4': | |
8232 | case '5': | |
8233 | case 'H': | |
8234 | case 'W': | |
8235 | case 'D': | |
8236 | case 'j': | |
8237 | case '8': | |
8238 | case 'V': | |
8239 | case 'C': | |
8240 | case 'U': | |
8241 | case 'k': | |
8242 | case 'K': | |
8243 | if (s[0] == '%' | |
8244 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
8245 | { | |
8246 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
8247 | and generate the appropriate reloc. If the text | |
8248 | inside %gprel is not a symbol name with an | |
8249 | optional offset, then we generate a normal reloc | |
8250 | and will probably fail later. */ | |
8251 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
8252 | if (imm_expr.X_op == O_symbol) | |
8253 | { | |
8254 | mips16_ext = true; | |
8255 | imm_reloc = BFD_RELOC_MIPS16_GPREL; | |
8256 | s = expr_end; | |
8257 | ip->use_extend = true; | |
8258 | ip->extend = 0; | |
8259 | continue; | |
8260 | } | |
8261 | } | |
8262 | else | |
8263 | { | |
8264 | /* Just pick up a normal expression. */ | |
8265 | my_getExpression (&imm_expr, s); | |
8266 | } | |
8267 | ||
8268 | if (imm_expr.X_op == O_register) | |
8269 | { | |
8270 | /* What we thought was an expression turned out to | |
8271 | be a register. */ | |
8272 | ||
8273 | if (s[0] == '(' && args[1] == '(') | |
8274 | { | |
8275 | /* It looks like the expression was omitted | |
8276 | before a register indirection, which means | |
8277 | that the expression is implicitly zero. We | |
8278 | still set up imm_expr, so that we handle | |
8279 | explicit extensions correctly. */ | |
8280 | imm_expr.X_op = O_constant; | |
8281 | imm_expr.X_add_number = 0; | |
8282 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8283 | continue; | |
8284 | } | |
8285 | ||
8286 | break; | |
8287 | } | |
8288 | ||
8289 | /* We need to relax this instruction. */ | |
8290 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8291 | s = expr_end; | |
8292 | continue; | |
8293 | ||
8294 | case 'p': | |
8295 | case 'q': | |
8296 | case 'A': | |
8297 | case 'B': | |
8298 | case 'E': | |
8299 | /* We use offset_reloc rather than imm_reloc for the PC | |
8300 | relative operands. This lets macros with both | |
8301 | immediate and address operands work correctly. */ | |
8302 | my_getExpression (&offset_expr, s); | |
8303 | ||
8304 | if (offset_expr.X_op == O_register) | |
8305 | break; | |
8306 | ||
8307 | /* We need to relax this instruction. */ | |
8308 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
8309 | s = expr_end; | |
8310 | continue; | |
8311 | ||
8312 | case '6': /* break code */ | |
8313 | my_getExpression (&imm_expr, s); | |
8314 | check_absolute_expr (ip, &imm_expr); | |
8315 | if ((unsigned long) imm_expr.X_add_number > 63) | |
8316 | { | |
8317 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8318 | ip->insn_mo->name, | |
8319 | (unsigned long) imm_expr.X_add_number); | |
8320 | imm_expr.X_add_number &= 0x3f; | |
8321 | } | |
8322 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
8323 | imm_expr.X_op = O_absent; | |
8324 | s = expr_end; | |
8325 | continue; | |
8326 | ||
8327 | case 'a': /* 26 bit address */ | |
8328 | my_getExpression (&offset_expr, s); | |
8329 | s = expr_end; | |
8330 | offset_reloc = BFD_RELOC_MIPS16_JMP; | |
8331 | ip->insn_opcode <<= 16; | |
8332 | continue; | |
8333 | ||
8334 | case 'l': /* register list for entry macro */ | |
8335 | case 'L': /* register list for exit macro */ | |
8336 | { | |
8337 | int mask; | |
8338 | ||
8339 | if (c == 'l') | |
8340 | mask = 0; | |
8341 | else | |
8342 | mask = 7 << 3; | |
8343 | while (*s != '\0') | |
8344 | { | |
8345 | int freg, reg1, reg2; | |
8346 | ||
8347 | while (*s == ' ' || *s == ',') | |
8348 | ++s; | |
8349 | if (*s != '$') | |
8350 | { | |
8351 | as_bad (_("can't parse register list")); | |
8352 | break; | |
8353 | } | |
8354 | ++s; | |
8355 | if (*s != 'f') | |
8356 | freg = 0; | |
8357 | else | |
8358 | { | |
8359 | freg = 1; | |
8360 | ++s; | |
8361 | } | |
8362 | reg1 = 0; | |
d9a62219 | 8363 | while (isdigit ((unsigned char) *s)) |
252b5132 RH |
8364 | { |
8365 | reg1 *= 10; | |
8366 | reg1 += *s - '0'; | |
8367 | ++s; | |
8368 | } | |
8369 | if (*s == ' ') | |
8370 | ++s; | |
8371 | if (*s != '-') | |
8372 | reg2 = reg1; | |
8373 | else | |
8374 | { | |
8375 | ++s; | |
8376 | if (*s != '$') | |
8377 | break; | |
8378 | ++s; | |
8379 | if (freg) | |
8380 | { | |
8381 | if (*s == 'f') | |
8382 | ++s; | |
8383 | else | |
8384 | { | |
8385 | as_bad (_("invalid register list")); | |
8386 | break; | |
8387 | } | |
8388 | } | |
8389 | reg2 = 0; | |
d9a62219 | 8390 | while (isdigit ((unsigned char) *s)) |
252b5132 RH |
8391 | { |
8392 | reg2 *= 10; | |
8393 | reg2 += *s - '0'; | |
8394 | ++s; | |
8395 | } | |
8396 | } | |
8397 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
8398 | { | |
8399 | mask &= ~ (7 << 3); | |
8400 | mask |= 5 << 3; | |
8401 | } | |
8402 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
8403 | { | |
8404 | mask &= ~ (7 << 3); | |
8405 | mask |= 6 << 3; | |
8406 | } | |
8407 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
8408 | mask |= (reg2 - 3) << 3; | |
8409 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
8410 | mask |= (reg2 - 15) << 1; | |
8411 | else if (reg1 == 31 && reg2 == 31) | |
8412 | mask |= 1; | |
8413 | else | |
8414 | { | |
8415 | as_bad (_("invalid register list")); | |
8416 | break; | |
8417 | } | |
8418 | } | |
8419 | /* The mask is filled in in the opcode table for the | |
8420 | benefit of the disassembler. We remove it before | |
8421 | applying the actual mask. */ | |
8422 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
8423 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
8424 | } | |
8425 | continue; | |
8426 | ||
8427 | case 'e': /* extend code */ | |
8428 | my_getExpression (&imm_expr, s); | |
8429 | check_absolute_expr (ip, &imm_expr); | |
8430 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
8431 | { | |
8432 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8433 | ip->insn_mo->name, | |
8434 | (unsigned long) imm_expr.X_add_number); | |
8435 | imm_expr.X_add_number &= 0x7ff; | |
8436 | } | |
8437 | ip->insn_opcode |= imm_expr.X_add_number; | |
8438 | imm_expr.X_op = O_absent; | |
8439 | s = expr_end; | |
8440 | continue; | |
8441 | ||
8442 | default: | |
8443 | internalError (); | |
8444 | } | |
8445 | break; | |
8446 | } | |
8447 | ||
8448 | /* Args don't match. */ | |
8449 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
8450 | strcmp (insn->name, insn[1].name) == 0) | |
8451 | { | |
8452 | ++insn; | |
8453 | s = argsstart; | |
8454 | continue; | |
8455 | } | |
8456 | ||
8457 | insn_error = _("illegal operands"); | |
8458 | ||
8459 | return; | |
8460 | } | |
8461 | } | |
8462 | ||
8463 | /* This structure holds information we know about a mips16 immediate | |
8464 | argument type. */ | |
8465 | ||
8466 | struct mips16_immed_operand | |
8467 | { | |
8468 | /* The type code used in the argument string in the opcode table. */ | |
8469 | int type; | |
8470 | /* The number of bits in the short form of the opcode. */ | |
8471 | int nbits; | |
8472 | /* The number of bits in the extended form of the opcode. */ | |
8473 | int extbits; | |
8474 | /* The amount by which the short form is shifted when it is used; | |
8475 | for example, the sw instruction has a shift count of 2. */ | |
8476 | int shift; | |
8477 | /* The amount by which the short form is shifted when it is stored | |
8478 | into the instruction code. */ | |
8479 | int op_shift; | |
8480 | /* Non-zero if the short form is unsigned. */ | |
8481 | int unsp; | |
8482 | /* Non-zero if the extended form is unsigned. */ | |
8483 | int extu; | |
8484 | /* Non-zero if the value is PC relative. */ | |
8485 | int pcrel; | |
8486 | }; | |
8487 | ||
8488 | /* The mips16 immediate operand types. */ | |
8489 | ||
8490 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
8491 | { | |
8492 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8493 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8494 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8495 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8496 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
8497 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8498 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8499 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8500 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8501 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
8502 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8503 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8504 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8505 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
8506 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
8507 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
8508 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
8509 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
8510 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
8511 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
8512 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
8513 | }; | |
8514 | ||
8515 | #define MIPS16_NUM_IMMED \ | |
8516 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
8517 | ||
8518 | /* Handle a mips16 instruction with an immediate value. This or's the | |
8519 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
8520 | whether an extended value is needed; if one is needed, it sets | |
8521 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
8522 | If SMALL is true, an unextended opcode was explicitly requested. | |
8523 | If EXT is true, an extended opcode was explicitly requested. If | |
8524 | WARN is true, warn if EXT does not match reality. */ | |
8525 | ||
8526 | static void | |
8527 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, | |
8528 | extend) | |
8529 | char *file; | |
8530 | unsigned int line; | |
8531 | int type; | |
8532 | offsetT val; | |
8533 | boolean warn; | |
8534 | boolean small; | |
8535 | boolean ext; | |
8536 | unsigned long *insn; | |
8537 | boolean *use_extend; | |
8538 | unsigned short *extend; | |
8539 | { | |
8540 | register const struct mips16_immed_operand *op; | |
8541 | int mintiny, maxtiny; | |
8542 | boolean needext; | |
8543 | ||
8544 | op = mips16_immed_operands; | |
8545 | while (op->type != type) | |
8546 | { | |
8547 | ++op; | |
8548 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
8549 | } | |
8550 | ||
8551 | if (op->unsp) | |
8552 | { | |
8553 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
8554 | { | |
8555 | mintiny = 1; | |
8556 | maxtiny = 1 << op->nbits; | |
8557 | } | |
8558 | else | |
8559 | { | |
8560 | mintiny = 0; | |
8561 | maxtiny = (1 << op->nbits) - 1; | |
8562 | } | |
8563 | } | |
8564 | else | |
8565 | { | |
8566 | mintiny = - (1 << (op->nbits - 1)); | |
8567 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
8568 | } | |
8569 | ||
8570 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
8571 | if (type == 'p' || type == 'q') | |
8572 | val /= 2; | |
8573 | ||
8574 | if ((val & ((1 << op->shift) - 1)) != 0 | |
8575 | || val < (mintiny << op->shift) | |
8576 | || val > (maxtiny << op->shift)) | |
8577 | needext = true; | |
8578 | else | |
8579 | needext = false; | |
8580 | ||
8581 | if (warn && ext && ! needext) | |
8582 | as_warn_where (file, line, _("extended operand requested but not required")); | |
8583 | if (small && needext) | |
8584 | as_bad_where (file, line, _("invalid unextended operand value")); | |
8585 | ||
8586 | if (small || (! ext && ! needext)) | |
8587 | { | |
8588 | int insnval; | |
8589 | ||
8590 | *use_extend = false; | |
8591 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
8592 | insnval <<= op->op_shift; | |
8593 | *insn |= insnval; | |
8594 | } | |
8595 | else | |
8596 | { | |
8597 | long minext, maxext; | |
8598 | int extval; | |
8599 | ||
8600 | if (op->extu) | |
8601 | { | |
8602 | minext = 0; | |
8603 | maxext = (1 << op->extbits) - 1; | |
8604 | } | |
8605 | else | |
8606 | { | |
8607 | minext = - (1 << (op->extbits - 1)); | |
8608 | maxext = (1 << (op->extbits - 1)) - 1; | |
8609 | } | |
8610 | if (val < minext || val > maxext) | |
8611 | as_bad_where (file, line, | |
8612 | _("operand value out of range for instruction")); | |
8613 | ||
8614 | *use_extend = true; | |
8615 | if (op->extbits == 16) | |
8616 | { | |
8617 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
8618 | val &= 0x1f; | |
8619 | } | |
8620 | else if (op->extbits == 15) | |
8621 | { | |
8622 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
8623 | val &= 0xf; | |
8624 | } | |
8625 | else | |
8626 | { | |
8627 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
8628 | val = 0; | |
8629 | } | |
8630 | ||
8631 | *extend = (unsigned short) extval; | |
8632 | *insn |= val; | |
8633 | } | |
8634 | } | |
8635 | \f | |
8636 | #define LP '(' | |
8637 | #define RP ')' | |
8638 | ||
8639 | static int | |
8640 | my_getSmallExpression (ep, str) | |
8641 | expressionS *ep; | |
8642 | char *str; | |
8643 | { | |
8644 | char *sp; | |
8645 | int c = 0; | |
8646 | ||
8647 | if (*str == ' ') | |
8648 | str++; | |
8649 | if (*str == LP | |
8650 | || (*str == '%' && | |
8651 | ((str[1] == 'h' && str[2] == 'i') | |
8652 | || (str[1] == 'H' && str[2] == 'I') | |
8653 | || (str[1] == 'l' && str[2] == 'o')) | |
8654 | && str[3] == LP)) | |
8655 | { | |
8656 | if (*str == LP) | |
8657 | c = 0; | |
8658 | else | |
8659 | { | |
8660 | c = str[1]; | |
8661 | str += 3; | |
8662 | } | |
8663 | ||
8664 | /* | |
8665 | * A small expression may be followed by a base register. | |
8666 | * Scan to the end of this operand, and then back over a possible | |
8667 | * base register. Then scan the small expression up to that | |
8668 | * point. (Based on code in sparc.c...) | |
8669 | */ | |
8670 | for (sp = str; *sp && *sp != ','; sp++) | |
8671 | ; | |
8672 | if (sp - 4 >= str && sp[-1] == RP) | |
8673 | { | |
d9a62219 | 8674 | if (isdigit ((unsigned char) sp[-2])) |
252b5132 | 8675 | { |
d9a62219 | 8676 | for (sp -= 3; sp >= str && isdigit ((unsigned char) *sp); sp--) |
252b5132 RH |
8677 | ; |
8678 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
8679 | { | |
8680 | sp--; | |
8681 | goto do_it; | |
8682 | } | |
8683 | } | |
8684 | else if (sp - 5 >= str | |
8685 | && sp[-5] == LP | |
8686 | && sp[-4] == '$' | |
8687 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
8688 | || (sp[-3] == 's' && sp[-2] == 'p') | |
8689 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
8690 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
8691 | { | |
8692 | sp -= 5; | |
8693 | do_it: | |
8694 | if (sp == str) | |
8695 | { | |
8696 | /* no expression means zero offset */ | |
8697 | if (c) | |
8698 | { | |
8699 | /* %xx(reg) is an error */ | |
8700 | ep->X_op = O_absent; | |
8701 | expr_end = str - 3; | |
8702 | } | |
8703 | else | |
8704 | { | |
8705 | ep->X_op = O_constant; | |
8706 | expr_end = sp; | |
8707 | } | |
8708 | ep->X_add_symbol = NULL; | |
8709 | ep->X_op_symbol = NULL; | |
8710 | ep->X_add_number = 0; | |
8711 | } | |
8712 | else | |
8713 | { | |
8714 | *sp = '\0'; | |
8715 | my_getExpression (ep, str); | |
8716 | *sp = LP; | |
8717 | } | |
8718 | return c; | |
8719 | } | |
8720 | } | |
8721 | } | |
8722 | my_getExpression (ep, str); | |
8723 | return c; /* => %hi or %lo encountered */ | |
8724 | } | |
8725 | ||
8726 | static void | |
8727 | my_getExpression (ep, str) | |
8728 | expressionS *ep; | |
8729 | char *str; | |
8730 | { | |
8731 | char *save_in; | |
8732 | ||
8733 | save_in = input_line_pointer; | |
8734 | input_line_pointer = str; | |
8735 | expression (ep); | |
8736 | expr_end = input_line_pointer; | |
8737 | input_line_pointer = save_in; | |
8738 | ||
8739 | /* If we are in mips16 mode, and this is an expression based on `.', | |
8740 | then we bump the value of the symbol by 1 since that is how other | |
8741 | text symbols are handled. We don't bother to handle complex | |
8742 | expressions, just `.' plus or minus a constant. */ | |
8743 | if (mips_opts.mips16 | |
8744 | && ep->X_op == O_symbol | |
8745 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
8746 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
8747 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
8748 | && symbol_constant_p (ep->X_add_symbol) | |
8749 | && S_GET_VALUE (ep->X_add_symbol) == frag_now_fix ()) | |
8750 | S_SET_VALUE (ep->X_add_symbol, S_GET_VALUE (ep->X_add_symbol) + 1); | |
252b5132 RH |
8751 | } |
8752 | ||
8753 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
8754 | of type TYPE, and store the appropriate bytes in *LITP. The number |
8755 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
8756 | returned, or NULL on OK. */ |
8757 | ||
8758 | char * | |
8759 | md_atof (type, litP, sizeP) | |
8760 | int type; | |
8761 | char *litP; | |
8762 | int *sizeP; | |
8763 | { | |
8764 | int prec; | |
8765 | LITTLENUM_TYPE words[4]; | |
8766 | char *t; | |
8767 | int i; | |
8768 | ||
8769 | switch (type) | |
8770 | { | |
8771 | case 'f': | |
8772 | prec = 2; | |
8773 | break; | |
8774 | ||
8775 | case 'd': | |
8776 | prec = 4; | |
8777 | break; | |
8778 | ||
8779 | default: | |
8780 | *sizeP = 0; | |
8781 | return _("bad call to md_atof"); | |
8782 | } | |
8783 | ||
8784 | t = atof_ieee (input_line_pointer, type, words); | |
8785 | if (t) | |
8786 | input_line_pointer = t; | |
8787 | ||
8788 | *sizeP = prec * 2; | |
8789 | ||
8790 | if (! target_big_endian) | |
8791 | { | |
8792 | for (i = prec - 1; i >= 0; i--) | |
8793 | { | |
8794 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8795 | litP += 2; | |
8796 | } | |
8797 | } | |
8798 | else | |
8799 | { | |
8800 | for (i = 0; i < prec; i++) | |
8801 | { | |
8802 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8803 | litP += 2; | |
8804 | } | |
8805 | } | |
8806 | ||
8807 | return NULL; | |
8808 | } | |
8809 | ||
8810 | void | |
8811 | md_number_to_chars (buf, val, n) | |
8812 | char *buf; | |
8813 | valueT val; | |
8814 | int n; | |
8815 | { | |
8816 | if (target_big_endian) | |
8817 | number_to_chars_bigendian (buf, val, n); | |
8818 | else | |
8819 | number_to_chars_littleendian (buf, val, n); | |
8820 | } | |
8821 | \f | |
8822 | CONST char *md_shortopts = "O::g::G:"; | |
8823 | ||
8824 | struct option md_longopts[] = { | |
8825 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
8826 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
8827 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
8828 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
8829 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
8830 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
8831 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
8832 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) | |
8833 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
8834 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
8835 | {"mcpu", required_argument, NULL, OPTION_MCPU}, | |
8836 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) | |
8837 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, | |
119d663a NC |
8838 | |
8839 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) | |
8840 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) | |
8841 | ||
252b5132 RH |
8842 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
8843 | {"trap", no_argument, NULL, OPTION_TRAP}, | |
8844 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
8845 | #define OPTION_BREAK (OPTION_MD_BASE + 10) | |
8846 | {"break", no_argument, NULL, OPTION_BREAK}, | |
8847 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
8848 | #define OPTION_EB (OPTION_MD_BASE + 11) | |
8849 | {"EB", no_argument, NULL, OPTION_EB}, | |
8850 | #define OPTION_EL (OPTION_MD_BASE + 12) | |
8851 | {"EL", no_argument, NULL, OPTION_EL}, | |
8852 | #define OPTION_M4650 (OPTION_MD_BASE + 13) | |
8853 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
8854 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) | |
8855 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
8856 | #define OPTION_M4010 (OPTION_MD_BASE + 15) | |
8857 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
8858 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
8859 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
8860 | #define OPTION_M4100 (OPTION_MD_BASE + 17) | |
8861 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
8862 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
8863 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
119d663a NC |
8864 | |
8865 | #define OPTION_XGOT (OPTION_MD_BASE + 19) | |
8866 | #define OPTION_32 (OPTION_MD_BASE + 20) | |
8867 | #define OPTION_64 (OPTION_MD_BASE + 21) | |
8868 | ||
252b5132 RH |
8869 | #define OPTION_MIPS16 (OPTION_MD_BASE + 22) |
8870 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
8871 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23) | |
8872 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
119d663a | 8873 | |
252b5132 RH |
8874 | #define OPTION_M3900 (OPTION_MD_BASE + 26) |
8875 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
8876 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 27) | |
8877 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
8878 | ||
252b5132 RH |
8879 | #define OPTION_MABI (OPTION_MD_BASE + 38) |
8880 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
8881 | ||
6b76fefe CM |
8882 | #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 39) |
8883 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
8884 | #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 40) | |
8885 | {"no-fix-7000", no_argument, NULL, OPTION_NO_M7000_HILO_FIX}, | |
8886 | ||
252b5132 RH |
8887 | #ifdef OBJ_ELF |
8888 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, | |
8889 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
8890 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
8891 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
8892 | {"32", no_argument, NULL, OPTION_32}, | |
8893 | {"64", no_argument, NULL, OPTION_64}, | |
8894 | #endif | |
8895 | ||
c97ef257 AH |
8896 | #define OPTION_GP32 (OPTION_MD_BASE + 41) |
8897 | #define OPTION_GP64 (OPTION_MD_BASE + 42) | |
8898 | {"mgp32", no_argument, NULL, OPTION_GP32}, | |
8899 | {"mgp64", no_argument, NULL, OPTION_GP64}, | |
8900 | ||
119d663a NC |
8901 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 43) |
8902 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, | |
8903 | ||
8904 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 44) | |
8905 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, | |
8906 | ||
252b5132 RH |
8907 | {NULL, no_argument, NULL, 0} |
8908 | }; | |
8909 | size_t md_longopts_size = sizeof(md_longopts); | |
8910 | ||
8911 | int | |
8912 | md_parse_option (c, arg) | |
8913 | int c; | |
8914 | char *arg; | |
8915 | { | |
8916 | switch (c) | |
8917 | { | |
119d663a NC |
8918 | case OPTION_CONSTRUCT_FLOATS: |
8919 | mips_disable_float_construction = 0; | |
8920 | break; | |
8921 | ||
8922 | case OPTION_NO_CONSTRUCT_FLOATS: | |
8923 | mips_disable_float_construction = 1; | |
8924 | break; | |
8925 | ||
252b5132 RH |
8926 | case OPTION_TRAP: |
8927 | mips_trap = 1; | |
8928 | break; | |
8929 | ||
8930 | case OPTION_BREAK: | |
8931 | mips_trap = 0; | |
8932 | break; | |
8933 | ||
8934 | case OPTION_EB: | |
8935 | target_big_endian = 1; | |
8936 | break; | |
8937 | ||
8938 | case OPTION_EL: | |
8939 | target_big_endian = 0; | |
8940 | break; | |
8941 | ||
8942 | case 'O': | |
8943 | if (arg && arg[1] == '0') | |
8944 | mips_optimize = 1; | |
8945 | else | |
8946 | mips_optimize = 2; | |
8947 | break; | |
8948 | ||
8949 | case 'g': | |
8950 | if (arg == NULL) | |
8951 | mips_debug = 2; | |
8952 | else | |
8953 | mips_debug = atoi (arg); | |
8954 | /* When the MIPS assembler sees -g or -g2, it does not do | |
8955 | optimizations which limit full symbolic debugging. We take | |
8956 | that to be equivalent to -O0. */ | |
8957 | if (mips_debug == 2) | |
8958 | mips_optimize = 1; | |
8959 | break; | |
8960 | ||
8961 | case OPTION_MIPS1: | |
8962 | mips_opts.isa = 1; | |
8963 | break; | |
8964 | ||
8965 | case OPTION_MIPS2: | |
8966 | mips_opts.isa = 2; | |
8967 | break; | |
8968 | ||
8969 | case OPTION_MIPS3: | |
8970 | mips_opts.isa = 3; | |
8971 | break; | |
8972 | ||
8973 | case OPTION_MIPS4: | |
8974 | mips_opts.isa = 4; | |
8975 | break; | |
8976 | ||
8977 | case OPTION_MCPU: | |
8978 | { | |
8979 | char *p; | |
8980 | ||
8981 | /* Identify the processor type */ | |
8982 | p = arg; | |
8983 | if (strcmp (p, "default") == 0 | |
8984 | || strcmp (p, "DEFAULT") == 0) | |
8985 | mips_cpu = -1; | |
8986 | else | |
8987 | { | |
8988 | int sv = 0; | |
8989 | ||
8990 | /* We need to cope with the various "vr" prefixes for the 4300 | |
8991 | processor. */ | |
8992 | if (*p == 'v' || *p == 'V') | |
8993 | { | |
8994 | sv = 1; | |
8995 | p++; | |
8996 | } | |
8997 | ||
8998 | if (*p == 'r' || *p == 'R') | |
8999 | p++; | |
9000 | ||
9001 | mips_cpu = -1; | |
9002 | switch (*p) | |
9003 | { | |
9004 | case '1': | |
9005 | if (strcmp (p, "10000") == 0 | |
9006 | || strcmp (p, "10k") == 0 | |
9007 | || strcmp (p, "10K") == 0) | |
9008 | mips_cpu = 10000; | |
9009 | break; | |
9010 | ||
9011 | case '2': | |
9012 | if (strcmp (p, "2000") == 0 | |
9013 | || strcmp (p, "2k") == 0 | |
9014 | || strcmp (p, "2K") == 0) | |
9015 | mips_cpu = 2000; | |
9016 | break; | |
9017 | ||
9018 | case '3': | |
9019 | if (strcmp (p, "3000") == 0 | |
9020 | || strcmp (p, "3k") == 0 | |
9021 | || strcmp (p, "3K") == 0) | |
9022 | mips_cpu = 3000; | |
9023 | else if (strcmp (p, "3900") == 0) | |
9024 | mips_cpu = 3900; | |
9025 | break; | |
9026 | ||
9027 | case '4': | |
9028 | if (strcmp (p, "4000") == 0 | |
9029 | || strcmp (p, "4k") == 0 | |
9030 | || strcmp (p, "4K") == 0) | |
9031 | mips_cpu = 4000; | |
9032 | else if (strcmp (p, "4100") == 0) | |
9033 | mips_cpu = 4100; | |
9034 | else if (strcmp (p, "4111") == 0) | |
9035 | mips_cpu = 4111; | |
9036 | else if (strcmp (p, "4300") == 0) | |
9037 | mips_cpu = 4300; | |
9038 | else if (strcmp (p, "4400") == 0) | |
9039 | mips_cpu = 4400; | |
9040 | else if (strcmp (p, "4600") == 0) | |
9041 | mips_cpu = 4600; | |
9042 | else if (strcmp (p, "4650") == 0) | |
9043 | mips_cpu = 4650; | |
9044 | else if (strcmp (p, "4010") == 0) | |
9045 | mips_cpu = 4010; | |
9046 | break; | |
9047 | ||
9048 | case '5': | |
9049 | if (strcmp (p, "5000") == 0 | |
9050 | || strcmp (p, "5k") == 0 | |
9051 | || strcmp (p, "5K") == 0) | |
9052 | mips_cpu = 5000; | |
9053 | break; | |
9054 | ||
9055 | case '6': | |
9056 | if (strcmp (p, "6000") == 0 | |
9057 | || strcmp (p, "6k") == 0 | |
9058 | || strcmp (p, "6K") == 0) | |
9059 | mips_cpu = 6000; | |
9060 | break; | |
9061 | ||
9062 | case '8': | |
9063 | if (strcmp (p, "8000") == 0 | |
9064 | || strcmp (p, "8k") == 0 | |
9065 | || strcmp (p, "8K") == 0) | |
9066 | mips_cpu = 8000; | |
9067 | break; | |
9068 | ||
9069 | case 'o': | |
9070 | if (strcmp (p, "orion") == 0) | |
9071 | mips_cpu = 4600; | |
9072 | break; | |
252b5132 | 9073 | |
b946ec34 NC |
9074 | case 'm': |
9075 | case 'M': | |
9076 | switch (atoi (p + 1)) | |
9077 | { | |
9078 | case 5200: | |
9079 | case 5230: | |
9080 | case 5231: | |
9081 | case 5261: | |
9082 | case 5721: | |
9083 | case 7000: | |
9084 | mips_cpu = 5000; | |
9085 | break; | |
9086 | default: | |
9087 | break; | |
9088 | } | |
9089 | } | |
9090 | ||
252b5132 RH |
9091 | if (sv |
9092 | && (mips_cpu != 4300 | |
9093 | && mips_cpu != 4100 | |
9094 | && mips_cpu != 4111 | |
9095 | && mips_cpu != 5000)) | |
9096 | { | |
9097 | as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg); | |
9098 | return 0; | |
9099 | } | |
9100 | ||
9101 | if (mips_cpu == -1) | |
9102 | { | |
9103 | as_bad (_("invalid architecture -mcpu=%s"), arg); | |
9104 | return 0; | |
9105 | } | |
9106 | } | |
9107 | } | |
9108 | break; | |
9109 | ||
9110 | case OPTION_M4650: | |
9111 | mips_cpu = 4650; | |
9112 | break; | |
9113 | ||
9114 | case OPTION_NO_M4650: | |
9115 | break; | |
9116 | ||
9117 | case OPTION_M4010: | |
9118 | mips_cpu = 4010; | |
9119 | break; | |
9120 | ||
9121 | case OPTION_NO_M4010: | |
9122 | break; | |
9123 | ||
9124 | case OPTION_M4100: | |
9125 | mips_cpu = 4100; | |
9126 | break; | |
9127 | ||
9128 | case OPTION_NO_M4100: | |
9129 | break; | |
9130 | ||
9131 | ||
9132 | case OPTION_M3900: | |
9133 | mips_cpu = 3900; | |
9134 | break; | |
9135 | ||
9136 | case OPTION_NO_M3900: | |
9137 | break; | |
9138 | ||
9139 | case OPTION_MIPS16: | |
9140 | mips_opts.mips16 = 1; | |
9141 | mips_no_prev_insn (false); | |
9142 | break; | |
9143 | ||
9144 | case OPTION_NO_MIPS16: | |
9145 | mips_opts.mips16 = 0; | |
9146 | mips_no_prev_insn (false); | |
9147 | break; | |
9148 | ||
9149 | case OPTION_MEMBEDDED_PIC: | |
9150 | mips_pic = EMBEDDED_PIC; | |
9151 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) | |
9152 | { | |
9153 | as_bad (_("-G may not be used with embedded PIC code")); | |
9154 | return 0; | |
9155 | } | |
9156 | g_switch_value = 0x7fffffff; | |
9157 | break; | |
9158 | ||
9159 | /* When generating ELF code, we permit -KPIC and -call_shared to | |
9160 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
9161 | intended to be compatible with Irix 5. */ | |
9162 | case OPTION_CALL_SHARED: | |
9163 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
9164 | { | |
9165 | as_bad (_("-call_shared is supported only for ELF format")); | |
9166 | return 0; | |
9167 | } | |
9168 | mips_pic = SVR4_PIC; | |
9169 | if (g_switch_seen && g_switch_value != 0) | |
9170 | { | |
9171 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
9172 | return 0; | |
9173 | } | |
9174 | g_switch_value = 0; | |
9175 | break; | |
9176 | ||
9177 | case OPTION_NON_SHARED: | |
9178 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
9179 | { | |
9180 | as_bad (_("-non_shared is supported only for ELF format")); | |
9181 | return 0; | |
9182 | } | |
9183 | mips_pic = NO_PIC; | |
9184 | break; | |
9185 | ||
9186 | /* The -xgot option tells the assembler to use 32 offsets when | |
9187 | accessing the got in SVR4_PIC mode. It is for Irix | |
9188 | compatibility. */ | |
9189 | case OPTION_XGOT: | |
9190 | mips_big_got = 1; | |
9191 | break; | |
9192 | ||
9193 | case 'G': | |
9194 | if (! USE_GLOBAL_POINTER_OPT) | |
9195 | { | |
9196 | as_bad (_("-G is not supported for this configuration")); | |
9197 | return 0; | |
9198 | } | |
9199 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
9200 | { | |
9201 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); | |
9202 | return 0; | |
9203 | } | |
9204 | else | |
9205 | g_switch_value = atoi (arg); | |
9206 | g_switch_seen = 1; | |
9207 | break; | |
9208 | ||
9209 | /* The -32 and -64 options tell the assembler to output the 32 | |
9210 | bit or the 64 bit MIPS ELF format. */ | |
9211 | case OPTION_32: | |
9212 | mips_64 = 0; | |
9213 | break; | |
9214 | ||
9215 | case OPTION_64: | |
9216 | { | |
9217 | const char **list, **l; | |
9218 | ||
9219 | list = bfd_target_list (); | |
9220 | for (l = list; *l != NULL; l++) | |
9221 | if (strcmp (*l, "elf64-bigmips") == 0 | |
9222 | || strcmp (*l, "elf64-littlemips") == 0) | |
9223 | break; | |
9224 | if (*l == NULL) | |
9225 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
9226 | free (list); | |
9227 | mips_64 = 1; | |
9228 | } | |
9229 | break; | |
9230 | ||
c97ef257 AH |
9231 | case OPTION_GP32: |
9232 | mips_gp32 = 1; | |
9233 | mips_64 = 0; | |
9234 | ||
9235 | /* We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
9236 | flag in object files because to do so would make it | |
9237 | impossible to link with libraries compiled without "-gp32". | |
9238 | This is unnecessarily restrictive. | |
9239 | ||
9240 | We could solve this problem by adding "-gp32" multilibs to | |
9241 | gcc, but to set this flag before gcc is built with such | |
9242 | multilibs will break too many systems. */ | |
9243 | ||
9244 | /* mips_32bitmode = 1; */ | |
9245 | break; | |
9246 | ||
9247 | case OPTION_GP64: | |
9248 | mips_gp32 = 0; | |
9249 | mips_64 = 1; | |
9250 | /* mips_32bitmode = 0; */ | |
9251 | break; | |
252b5132 RH |
9252 | |
9253 | case OPTION_MABI: | |
9254 | if (strcmp (arg,"32") == 0 | |
9255 | || strcmp (arg,"n32") == 0 | |
9256 | || strcmp (arg,"64") == 0 | |
9257 | || strcmp (arg,"o64") == 0 | |
9258 | || strcmp (arg,"eabi") == 0) | |
9259 | mips_abi_string = arg; | |
9260 | break; | |
9261 | ||
6b76fefe CM |
9262 | case OPTION_M7000_HILO_FIX: |
9263 | mips_7000_hilo_fix = true; | |
9264 | break; | |
9265 | ||
9266 | case OPTION_NO_M7000_HILO_FIX: | |
9267 | mips_7000_hilo_fix = false; | |
9268 | break; | |
9269 | ||
252b5132 RH |
9270 | default: |
9271 | return 0; | |
9272 | } | |
9273 | ||
9274 | return 1; | |
9275 | } | |
9276 | ||
9277 | ||
9278 | static void | |
9279 | show (stream, string, col_p, first_p) | |
9280 | FILE *stream; | |
9281 | char *string; | |
9282 | int *col_p; | |
9283 | int *first_p; | |
9284 | { | |
9285 | if (*first_p) | |
9286 | { | |
9287 | fprintf (stream, "%24s", ""); | |
9288 | *col_p = 24; | |
9289 | } | |
9290 | else | |
9291 | { | |
9292 | fprintf (stream, ", "); | |
9293 | *col_p += 2; | |
9294 | } | |
9295 | ||
9296 | if (*col_p + strlen (string) > 72) | |
9297 | { | |
9298 | fprintf (stream, "\n%24s", ""); | |
9299 | *col_p = 24; | |
9300 | } | |
9301 | ||
9302 | fprintf (stream, "%s", string); | |
9303 | *col_p += strlen (string); | |
9304 | ||
9305 | *first_p = 0; | |
9306 | } | |
9307 | ||
9308 | ||
9309 | void | |
9310 | md_show_usage (stream) | |
9311 | FILE *stream; | |
9312 | { | |
9313 | int column, first; | |
9314 | ||
9315 | fprintf(stream, _("\ | |
9316 | MIPS options:\n\ | |
9317 | -membedded-pic generate embedded position independent code\n\ | |
9318 | -EB generate big endian output\n\ | |
9319 | -EL generate little endian output\n\ | |
9320 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
9321 | -G NUM allow referencing objects up to NUM bytes\n\ | |
9322 | implicitly with the gp register [default 8]\n")); | |
9323 | fprintf(stream, _("\ | |
9324 | -mips1 generate MIPS ISA I instructions\n\ | |
9325 | -mips2 generate MIPS ISA II instructions\n\ | |
9326 | -mips3 generate MIPS ISA III instructions\n\ | |
9327 | -mips4 generate MIPS ISA IV instructions\n\ | |
9328 | -mcpu=CPU generate code for CPU, where CPU is one of:\n")); | |
9329 | ||
9330 | first = 1; | |
9331 | ||
9332 | show (stream, "2000", &column, &first); | |
9333 | show (stream, "3000", &column, &first); | |
9334 | show (stream, "3900", &column, &first); | |
9335 | show (stream, "4000", &column, &first); | |
9336 | show (stream, "4010", &column, &first); | |
9337 | show (stream, "4100", &column, &first); | |
9338 | show (stream, "4111", &column, &first); | |
9339 | show (stream, "4300", &column, &first); | |
9340 | show (stream, "4400", &column, &first); | |
9341 | show (stream, "4600", &column, &first); | |
9342 | show (stream, "4650", &column, &first); | |
9343 | show (stream, "5000", &column, &first); | |
9344 | show (stream, "6000", &column, &first); | |
9345 | show (stream, "8000", &column, &first); | |
9346 | show (stream, "10000", &column, &first); | |
9347 | fputc ('\n', stream); | |
9348 | ||
9349 | fprintf (stream, _("\ | |
9350 | -mCPU equivalent to -mcpu=CPU.\n\ | |
9351 | -no-mCPU don't generate code specific to CPU.\n\ | |
9352 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
9353 | ||
9354 | first = 1; | |
9355 | ||
9356 | show (stream, "3900", &column, &first); | |
9357 | show (stream, "4010", &column, &first); | |
9358 | show (stream, "4100", &column, &first); | |
9359 | show (stream, "4650", &column, &first); | |
9360 | fputc ('\n', stream); | |
9361 | ||
9362 | fprintf(stream, _("\ | |
9363 | -mips16 generate mips16 instructions\n\ | |
9364 | -no-mips16 do not generate mips16 instructions\n")); | |
9365 | fprintf(stream, _("\ | |
9366 | -O0 remove unneeded NOPs, do not swap branches\n\ | |
9367 | -O remove unneeded NOPs and swap branches\n\ | |
119d663a | 9368 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
252b5132 RH |
9369 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
9370 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
9371 | #ifdef OBJ_ELF | |
9372 | fprintf(stream, _("\ | |
9373 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
9374 | -non_shared do not generate position independent code\n\ | |
9375 | -xgot assume a 32 bit GOT\n\ | |
9376 | -32 create 32 bit object file (default)\n\ | |
9377 | -64 create 64 bit object file\n")); | |
9378 | #endif | |
9379 | } | |
9380 | \f | |
9381 | void | |
9382 | mips_init_after_args () | |
9383 | { | |
9384 | /* initialize opcodes */ | |
9385 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
9386 | mips_opcodes = (struct mips_opcode*) mips_builtin_opcodes; | |
9387 | } | |
9388 | ||
9389 | long | |
9390 | md_pcrel_from (fixP) | |
9391 | fixS *fixP; | |
9392 | { | |
9393 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour | |
9394 | && fixP->fx_addsy != (symbolS *) NULL | |
9395 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
9396 | { | |
9397 | /* This makes a branch to an undefined symbol be a branch to the | |
9398 | current location. */ | |
9399 | return 4; | |
9400 | } | |
9401 | ||
9402 | /* return the address of the delay slot */ | |
9403 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
9404 | } | |
9405 | ||
9406 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a | |
9407 | reloc for a cons. We could use the definition there, except that | |
9408 | we want to handle 64 bit relocs specially. */ | |
9409 | ||
9410 | void | |
9411 | cons_fix_new_mips (frag, where, nbytes, exp) | |
43841e91 | 9412 | fragS *frag ATTRIBUTE_UNUSED; |
252b5132 RH |
9413 | int where; |
9414 | unsigned int nbytes; | |
9415 | expressionS *exp; | |
9416 | { | |
9417 | #ifndef OBJ_ELF | |
9418 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a | |
9419 | 4 byte reloc. */ | |
9420 | if (nbytes == 8 && ! mips_64) | |
9421 | { | |
9422 | if (target_big_endian) | |
9423 | where += 4; | |
9424 | nbytes = 4; | |
9425 | } | |
9426 | #endif | |
9427 | ||
9428 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) | |
9429 | as_bad (_("Unsupported reloc size %d"), nbytes); | |
9430 | ||
9431 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
9432 | (nbytes == 2 | |
9433 | ? BFD_RELOC_16 | |
9434 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
9435 | } | |
9436 | ||
9437 | /* This is called before the symbol table is processed. In order to | |
9438 | work with gcc when using mips-tfile, we must keep all local labels. | |
9439 | However, in other cases, we want to discard them. If we were | |
9440 | called with -g, but we didn't see any debugging information, it may | |
9441 | mean that gcc is smuggling debugging information through to | |
9442 | mips-tfile, in which case we must generate all local labels. */ | |
9443 | ||
9444 | void | |
9445 | mips_frob_file_before_adjust () | |
9446 | { | |
9447 | #ifndef NO_ECOFF_DEBUGGING | |
9448 | if (ECOFF_DEBUGGING | |
9449 | && mips_debug != 0 | |
9450 | && ! ecoff_debugging_seen) | |
9451 | flag_keep_locals = 1; | |
9452 | #endif | |
9453 | } | |
9454 | ||
9455 | /* Sort any unmatched HI16_S relocs so that they immediately precede | |
9456 | the corresponding LO reloc. This is called before md_apply_fix and | |
9457 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
9458 | explicit use of the %hi modifier. */ | |
9459 | ||
9460 | void | |
9461 | mips_frob_file () | |
9462 | { | |
9463 | struct mips_hi_fixup *l; | |
9464 | ||
9465 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
9466 | { | |
9467 | segment_info_type *seginfo; | |
9468 | int pass; | |
9469 | ||
9470 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
9471 | ||
9472 | /* Check quickly whether the next fixup happens to be a matching | |
9473 | %lo. */ | |
9474 | if (l->fixp->fx_next != NULL | |
9475 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
9476 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
9477 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
9478 | continue; | |
9479 | ||
9480 | /* Look through the fixups for this segment for a matching %lo. | |
9481 | When we find one, move the %hi just in front of it. We do | |
9482 | this in two passes. In the first pass, we try to find a | |
9483 | unique %lo. In the second pass, we permit multiple %hi | |
9484 | relocs for a single %lo (this is a GNU extension). */ | |
9485 | seginfo = seg_info (l->seg); | |
9486 | for (pass = 0; pass < 2; pass++) | |
9487 | { | |
9488 | fixS *f, *prev; | |
9489 | ||
9490 | prev = NULL; | |
9491 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
9492 | { | |
9493 | /* Check whether this is a %lo fixup which matches l->fixp. */ | |
9494 | if (f->fx_r_type == BFD_RELOC_LO16 | |
9495 | && f->fx_addsy == l->fixp->fx_addsy | |
9496 | && f->fx_offset == l->fixp->fx_offset | |
9497 | && (pass == 1 | |
9498 | || prev == NULL | |
9499 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
9500 | || prev->fx_addsy != f->fx_addsy | |
9501 | || prev->fx_offset != f->fx_offset)) | |
9502 | { | |
9503 | fixS **pf; | |
9504 | ||
9505 | /* Move l->fixp before f. */ | |
9506 | for (pf = &seginfo->fix_root; | |
9507 | *pf != l->fixp; | |
9508 | pf = &(*pf)->fx_next) | |
9509 | assert (*pf != NULL); | |
9510 | ||
9511 | *pf = l->fixp->fx_next; | |
9512 | ||
9513 | l->fixp->fx_next = f; | |
9514 | if (prev == NULL) | |
9515 | seginfo->fix_root = l->fixp; | |
9516 | else | |
9517 | prev->fx_next = l->fixp; | |
9518 | ||
9519 | break; | |
9520 | } | |
9521 | ||
9522 | prev = f; | |
9523 | } | |
9524 | ||
9525 | if (f != NULL) | |
9526 | break; | |
9527 | ||
9528 | #if 0 /* GCC code motion plus incomplete dead code elimination | |
9529 | can leave a %hi without a %lo. */ | |
9530 | if (pass == 1) | |
9531 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
9532 | _("Unmatched %%hi reloc")); | |
9533 | #endif | |
9534 | } | |
9535 | } | |
9536 | } | |
9537 | ||
9538 | /* When generating embedded PIC code we need to use a special | |
9539 | relocation to represent the difference of two symbols in the .text | |
9540 | section (switch tables use a difference of this sort). See | |
9541 | include/coff/mips.h for details. This macro checks whether this | |
9542 | fixup requires the special reloc. */ | |
9543 | #define SWITCH_TABLE(fixp) \ | |
9544 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
bb2d6cd7 | 9545 | && OUTPUT_FLAVOR != bfd_target_elf_flavour \ |
252b5132 RH |
9546 | && (fixp)->fx_addsy != NULL \ |
9547 | && (fixp)->fx_subsy != NULL \ | |
9548 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
9549 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
9550 | ||
9551 | /* When generating embedded PIC code we must keep all PC relative | |
9552 | relocations, in case the linker has to relax a call. We also need | |
9553 | to keep relocations for switch table entries. */ | |
9554 | ||
9555 | /*ARGSUSED*/ | |
9556 | int | |
9557 | mips_force_relocation (fixp) | |
9558 | fixS *fixp; | |
9559 | { | |
9560 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
9561 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
9562 | return 1; | |
9563 | ||
9564 | return (mips_pic == EMBEDDED_PIC | |
9565 | && (fixp->fx_pcrel | |
9566 | || SWITCH_TABLE (fixp) | |
9567 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
9568 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
9569 | } | |
9570 | ||
9571 | /* Apply a fixup to the object file. */ | |
9572 | ||
9573 | int | |
9574 | md_apply_fix (fixP, valueP) | |
9575 | fixS *fixP; | |
9576 | valueT *valueP; | |
9577 | { | |
9578 | unsigned char *buf; | |
9579 | long insn, value; | |
9580 | ||
9581 | assert (fixP->fx_size == 4 | |
9582 | || fixP->fx_r_type == BFD_RELOC_16 | |
9583 | || fixP->fx_r_type == BFD_RELOC_64 | |
9584 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
9585 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); | |
9586 | ||
9587 | value = *valueP; | |
9588 | ||
9589 | /* If we aren't adjusting this fixup to be against the section | |
9590 | symbol, we need to adjust the value. */ | |
9591 | #ifdef OBJ_ELF | |
9592 | if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
bb2d6cd7 | 9593 | { |
252b5132 RH |
9594 | if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16 |
9595 | || S_IS_WEAK (fixP->fx_addsy) | |
49309057 ILT |
9596 | || (symbol_used_in_reloc_p (fixP->fx_addsy) |
9597 | && (((bfd_get_section_flags (stdoutput, | |
bb2d6cd7 GK |
9598 | S_GET_SEGMENT (fixP->fx_addsy)) |
9599 | & SEC_LINK_ONCE) != 0) | |
9600 | || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), | |
9601 | ".gnu.linkonce", | |
9602 | sizeof (".gnu.linkonce") - 1)))) | |
252b5132 RH |
9603 | |
9604 | { | |
9605 | value -= S_GET_VALUE (fixP->fx_addsy); | |
9606 | if (value != 0 && ! fixP->fx_pcrel) | |
9607 | { | |
9608 | /* In this case, the bfd_install_relocation routine will | |
9609 | incorrectly add the symbol value back in. We just want | |
bb2d6cd7 GK |
9610 | the addend to appear in the object file. |
9611 | FIXME: If this makes VALUE zero, we're toast. */ | |
252b5132 RH |
9612 | value -= S_GET_VALUE (fixP->fx_addsy); |
9613 | } | |
9614 | } | |
252b5132 | 9615 | |
bb2d6cd7 GK |
9616 | /* This code was generated using trial and error and so is |
9617 | fragile and not trustworthy. If you change it, you should | |
9618 | rerun the elf-rel, elf-rel2, and empic testcases and ensure | |
9619 | they still pass. */ | |
9620 | if (fixP->fx_pcrel || fixP->fx_subsy != NULL) | |
9621 | { | |
9622 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
9623 | ||
9624 | /* BFD's REL handling, for MIPS, is _very_ weird. | |
9625 | This gives the right results, but it can't possibly | |
9626 | be the way things are supposed to work. */ | |
9627 | if (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2 | |
9628 | || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section) | |
9629 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
9630 | } | |
9631 | } | |
9632 | #endif | |
252b5132 RH |
9633 | |
9634 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ | |
9635 | ||
9636 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) | |
9637 | fixP->fx_done = 1; | |
9638 | ||
9639 | switch (fixP->fx_r_type) | |
9640 | { | |
9641 | case BFD_RELOC_MIPS_JMP: | |
9642 | case BFD_RELOC_HI16: | |
9643 | case BFD_RELOC_HI16_S: | |
9644 | case BFD_RELOC_MIPS_GPREL: | |
9645 | case BFD_RELOC_MIPS_LITERAL: | |
9646 | case BFD_RELOC_MIPS_CALL16: | |
9647 | case BFD_RELOC_MIPS_GOT16: | |
9648 | case BFD_RELOC_MIPS_GPREL32: | |
9649 | case BFD_RELOC_MIPS_GOT_HI16: | |
9650 | case BFD_RELOC_MIPS_GOT_LO16: | |
9651 | case BFD_RELOC_MIPS_CALL_HI16: | |
9652 | case BFD_RELOC_MIPS_CALL_LO16: | |
9653 | case BFD_RELOC_MIPS16_GPREL: | |
9654 | if (fixP->fx_pcrel) | |
9655 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
9656 | _("Invalid PC relative reloc")); | |
9657 | /* Nothing needed to do. The value comes from the reloc entry */ | |
9658 | break; | |
9659 | ||
9660 | case BFD_RELOC_MIPS16_JMP: | |
9661 | /* We currently always generate a reloc against a symbol, which | |
9662 | means that we don't want an addend even if the symbol is | |
9663 | defined. */ | |
9664 | fixP->fx_addnumber = 0; | |
9665 | break; | |
9666 | ||
9667 | case BFD_RELOC_PCREL_HI16_S: | |
9668 | /* The addend for this is tricky if it is internal, so we just | |
9669 | do everything here rather than in bfd_install_relocation. */ | |
bb2d6cd7 GK |
9670 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
9671 | && !fixP->fx_done | |
9672 | && value != 0) | |
9673 | break; | |
9674 | if (fixP->fx_addsy | |
9675 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
9676 | { |
9677 | /* For an external symbol adjust by the address to make it | |
9678 | pcrel_offset. We use the address of the RELLO reloc | |
9679 | which follows this one. */ | |
9680 | value += (fixP->fx_next->fx_frag->fr_address | |
9681 | + fixP->fx_next->fx_where); | |
9682 | } | |
9683 | if (value & 0x8000) | |
9684 | value += 0x10000; | |
9685 | value >>= 16; | |
9686 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; | |
9687 | if (target_big_endian) | |
9688 | buf += 2; | |
9689 | md_number_to_chars (buf, value, 2); | |
9690 | break; | |
9691 | ||
9692 | case BFD_RELOC_PCREL_LO16: | |
9693 | /* The addend for this is tricky if it is internal, so we just | |
9694 | do everything here rather than in bfd_install_relocation. */ | |
bb2d6cd7 GK |
9695 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
9696 | && !fixP->fx_done | |
9697 | && value != 0) | |
9698 | break; | |
9699 | if (fixP->fx_addsy | |
9700 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
9701 | value += fixP->fx_frag->fr_address + fixP->fx_where; |
9702 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; | |
9703 | if (target_big_endian) | |
9704 | buf += 2; | |
9705 | md_number_to_chars (buf, value, 2); | |
9706 | break; | |
9707 | ||
9708 | case BFD_RELOC_64: | |
9709 | /* This is handled like BFD_RELOC_32, but we output a sign | |
9710 | extended value if we are only 32 bits. */ | |
9711 | if (fixP->fx_done | |
9712 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
9713 | { | |
9714 | if (8 <= sizeof (valueT)) | |
9715 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9716 | value, 8); | |
9717 | else | |
9718 | { | |
9719 | long w1, w2; | |
9720 | long hiv; | |
9721 | ||
9722 | w1 = w2 = fixP->fx_where; | |
9723 | if (target_big_endian) | |
9724 | w1 += 4; | |
9725 | else | |
9726 | w2 += 4; | |
9727 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
9728 | if ((value & 0x80000000) != 0) | |
9729 | hiv = 0xffffffff; | |
9730 | else | |
9731 | hiv = 0; | |
9732 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
9733 | } | |
9734 | } | |
9735 | break; | |
9736 | ||
056350c6 | 9737 | case BFD_RELOC_RVA: |
252b5132 RH |
9738 | case BFD_RELOC_32: |
9739 | /* If we are deleting this reloc entry, we must fill in the | |
9740 | value now. This can happen if we have a .word which is not | |
9741 | resolved when it appears but is later defined. We also need | |
9742 | to fill in the value if this is an embedded PIC switch table | |
9743 | entry. */ | |
9744 | if (fixP->fx_done | |
9745 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
9746 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9747 | value, 4); | |
9748 | break; | |
9749 | ||
9750 | case BFD_RELOC_16: | |
9751 | /* If we are deleting this reloc entry, we must fill in the | |
9752 | value now. */ | |
9753 | assert (fixP->fx_size == 2); | |
9754 | if (fixP->fx_done) | |
9755 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9756 | value, 2); | |
9757 | break; | |
9758 | ||
9759 | case BFD_RELOC_LO16: | |
9760 | /* When handling an embedded PIC switch statement, we can wind | |
9761 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
9762 | if (fixP->fx_done) | |
9763 | { | |
9764 | if (value < -0x8000 || value > 0x7fff) | |
9765 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
9766 | _("relocation overflow")); | |
9767 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; | |
9768 | if (target_big_endian) | |
9769 | buf += 2; | |
9770 | md_number_to_chars (buf, value, 2); | |
9771 | } | |
9772 | break; | |
9773 | ||
9774 | case BFD_RELOC_16_PCREL_S2: | |
9775 | /* | |
9776 | * We need to save the bits in the instruction since fixup_segment() | |
9777 | * might be deleting the relocation entry (i.e., a branch within | |
9778 | * the current segment). | |
9779 | */ | |
9780 | if ((value & 0x3) != 0) | |
9781 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
9782 | _("Branch to odd address (%lx)"), value); | |
bb2d6cd7 GK |
9783 | |
9784 | if (!fixP->fx_done && value != 0) | |
9785 | break; | |
9786 | /* If 'value' is zero, the remaining reloc code won't actually | |
9787 | do the store, so it must be done here. This is probably | |
9788 | a bug somewhere. */ | |
9789 | if (!fixP->fx_done) | |
9790 | value -= fixP->fx_frag->fr_address + fixP->fx_where; | |
9791 | ||
252b5132 RH |
9792 | value >>= 2; |
9793 | ||
9794 | /* update old instruction data */ | |
9795 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
9796 | if (target_big_endian) | |
9797 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
9798 | else | |
9799 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
9800 | ||
9801 | if (value >= -0x8000 && value < 0x8000) | |
9802 | insn |= value & 0xffff; | |
9803 | else | |
9804 | { | |
9805 | /* The branch offset is too large. If this is an | |
9806 | unconditional branch, and we are not generating PIC code, | |
9807 | we can convert it to an absolute jump instruction. */ | |
9808 | if (mips_pic == NO_PIC | |
9809 | && fixP->fx_done | |
9810 | && fixP->fx_frag->fr_address >= text_section->vma | |
9811 | && (fixP->fx_frag->fr_address | |
9812 | < text_section->vma + text_section->_raw_size) | |
9813 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
9814 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
9815 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
9816 | { | |
9817 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
9818 | insn = 0x0c000000; /* jal */ | |
9819 | else | |
9820 | insn = 0x08000000; /* j */ | |
9821 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
9822 | fixP->fx_done = 0; | |
9823 | fixP->fx_addsy = section_symbol (text_section); | |
9824 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
9825 | } | |
9826 | else | |
9827 | { | |
9828 | /* FIXME. It would be possible in principle to handle | |
9829 | conditional branches which overflow. They could be | |
9830 | transformed into a branch around a jump. This would | |
9831 | require setting up variant frags for each different | |
9832 | branch type. The native MIPS assembler attempts to | |
9833 | handle these cases, but it appears to do it | |
9834 | incorrectly. */ | |
9835 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
9836 | _("Branch out of range")); | |
9837 | } | |
9838 | } | |
9839 | ||
9840 | md_number_to_chars ((char *) buf, (valueT) insn, 4); | |
9841 | break; | |
9842 | ||
9843 | case BFD_RELOC_VTABLE_INHERIT: | |
9844 | fixP->fx_done = 0; | |
9845 | if (fixP->fx_addsy | |
9846 | && !S_IS_DEFINED (fixP->fx_addsy) | |
9847 | && !S_IS_WEAK (fixP->fx_addsy)) | |
9848 | S_SET_WEAK (fixP->fx_addsy); | |
9849 | break; | |
9850 | ||
9851 | case BFD_RELOC_VTABLE_ENTRY: | |
9852 | fixP->fx_done = 0; | |
9853 | break; | |
9854 | ||
9855 | default: | |
9856 | internalError (); | |
9857 | } | |
9858 | ||
9859 | return 1; | |
9860 | } | |
9861 | ||
9862 | #if 0 | |
9863 | void | |
9864 | printInsn (oc) | |
9865 | unsigned long oc; | |
9866 | { | |
9867 | const struct mips_opcode *p; | |
9868 | int treg, sreg, dreg, shamt; | |
9869 | short imm; | |
9870 | const char *args; | |
9871 | int i; | |
9872 | ||
9873 | for (i = 0; i < NUMOPCODES; ++i) | |
9874 | { | |
9875 | p = &mips_opcodes[i]; | |
9876 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
9877 | { | |
9878 | printf ("%08lx %s\t", oc, p->name); | |
9879 | treg = (oc >> 16) & 0x1f; | |
9880 | sreg = (oc >> 21) & 0x1f; | |
9881 | dreg = (oc >> 11) & 0x1f; | |
9882 | shamt = (oc >> 6) & 0x1f; | |
9883 | imm = oc; | |
9884 | for (args = p->args;; ++args) | |
9885 | { | |
9886 | switch (*args) | |
9887 | { | |
9888 | case '\0': | |
9889 | printf ("\n"); | |
9890 | break; | |
9891 | ||
9892 | case ',': | |
9893 | case '(': | |
9894 | case ')': | |
9895 | printf ("%c", *args); | |
9896 | continue; | |
9897 | ||
9898 | case 'r': | |
9899 | assert (treg == sreg); | |
9900 | printf ("$%d,$%d", treg, sreg); | |
9901 | continue; | |
9902 | ||
9903 | case 'd': | |
9904 | case 'G': | |
9905 | printf ("$%d", dreg); | |
9906 | continue; | |
9907 | ||
9908 | case 't': | |
9909 | case 'E': | |
9910 | printf ("$%d", treg); | |
9911 | continue; | |
9912 | ||
9913 | case 'k': | |
9914 | printf ("0x%x", treg); | |
9915 | continue; | |
9916 | ||
9917 | case 'b': | |
9918 | case 's': | |
9919 | printf ("$%d", sreg); | |
9920 | continue; | |
9921 | ||
9922 | case 'a': | |
9923 | printf ("0x%08lx", oc & 0x1ffffff); | |
9924 | continue; | |
9925 | ||
9926 | case 'i': | |
9927 | case 'j': | |
9928 | case 'o': | |
9929 | case 'u': | |
9930 | printf ("%d", imm); | |
9931 | continue; | |
9932 | ||
9933 | case '<': | |
9934 | case '>': | |
9935 | printf ("$%d", shamt); | |
9936 | continue; | |
9937 | ||
9938 | default: | |
9939 | internalError (); | |
9940 | } | |
9941 | break; | |
9942 | } | |
9943 | return; | |
9944 | } | |
9945 | } | |
9946 | printf (_("%08lx UNDEFINED\n"), oc); | |
9947 | } | |
9948 | #endif | |
9949 | ||
9950 | static symbolS * | |
9951 | get_symbol () | |
9952 | { | |
9953 | int c; | |
9954 | char *name; | |
9955 | symbolS *p; | |
9956 | ||
9957 | name = input_line_pointer; | |
9958 | c = get_symbol_end (); | |
9959 | p = (symbolS *) symbol_find_or_make (name); | |
9960 | *input_line_pointer = c; | |
9961 | return p; | |
9962 | } | |
9963 | ||
9964 | /* Align the current frag to a given power of two. The MIPS assembler | |
9965 | also automatically adjusts any preceding label. */ | |
9966 | ||
9967 | static void | |
9968 | mips_align (to, fill, label) | |
9969 | int to; | |
9970 | int fill; | |
9971 | symbolS *label; | |
9972 | { | |
9973 | mips_emit_delays (false); | |
9974 | frag_align (to, fill, 0); | |
9975 | record_alignment (now_seg, to); | |
9976 | if (label != NULL) | |
9977 | { | |
9978 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 9979 | symbol_set_frag (label, frag_now); |
252b5132 RH |
9980 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
9981 | } | |
9982 | } | |
9983 | ||
9984 | /* Align to a given power of two. .align 0 turns off the automatic | |
9985 | alignment used by the data creating pseudo-ops. */ | |
9986 | ||
9987 | static void | |
9988 | s_align (x) | |
43841e91 | 9989 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
9990 | { |
9991 | register int temp; | |
9992 | register long temp_fill; | |
9993 | long max_alignment = 15; | |
9994 | ||
9995 | /* | |
9996 | ||
9997 | o Note that the assembler pulls down any immediately preceeding label | |
9998 | to the aligned address. | |
9999 | o It's not documented but auto alignment is reinstated by | |
10000 | a .align pseudo instruction. | |
10001 | o Note also that after auto alignment is turned off the mips assembler | |
10002 | issues an error on attempt to assemble an improperly aligned data item. | |
10003 | We don't. | |
10004 | ||
10005 | */ | |
10006 | ||
10007 | temp = get_absolute_expression (); | |
10008 | if (temp > max_alignment) | |
10009 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
10010 | else if (temp < 0) | |
10011 | { | |
10012 | as_warn (_("Alignment negative: 0 assumed.")); | |
10013 | temp = 0; | |
10014 | } | |
10015 | if (*input_line_pointer == ',') | |
10016 | { | |
10017 | input_line_pointer++; | |
10018 | temp_fill = get_absolute_expression (); | |
10019 | } | |
10020 | else | |
10021 | temp_fill = 0; | |
10022 | if (temp) | |
10023 | { | |
10024 | auto_align = 1; | |
10025 | mips_align (temp, (int) temp_fill, | |
10026 | insn_labels != NULL ? insn_labels->label : NULL); | |
10027 | } | |
10028 | else | |
10029 | { | |
10030 | auto_align = 0; | |
10031 | } | |
10032 | ||
10033 | demand_empty_rest_of_line (); | |
10034 | } | |
10035 | ||
10036 | void | |
10037 | mips_flush_pending_output () | |
10038 | { | |
10039 | mips_emit_delays (false); | |
10040 | mips_clear_insn_labels (); | |
10041 | } | |
10042 | ||
10043 | static void | |
10044 | s_change_sec (sec) | |
10045 | int sec; | |
10046 | { | |
10047 | segT seg; | |
10048 | ||
10049 | /* When generating embedded PIC code, we only use the .text, .lit8, | |
10050 | .sdata and .sbss sections. We change the .data and .rdata | |
10051 | pseudo-ops to use .sdata. */ | |
10052 | if (mips_pic == EMBEDDED_PIC | |
10053 | && (sec == 'd' || sec == 'r')) | |
10054 | sec = 's'; | |
10055 | ||
10056 | #ifdef OBJ_ELF | |
10057 | /* The ELF backend needs to know that we are changing sections, so | |
10058 | that .previous works correctly. We could do something like check | |
10059 | for a obj_section_change_hook macro, but that might be confusing | |
10060 | as it would not be appropriate to use it in the section changing | |
10061 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
10062 | This should be cleaner, somehow. */ | |
10063 | obj_elf_section_change_hook (); | |
10064 | #endif | |
10065 | ||
10066 | mips_emit_delays (false); | |
10067 | switch (sec) | |
10068 | { | |
10069 | case 't': | |
10070 | s_text (0); | |
10071 | break; | |
10072 | case 'd': | |
10073 | s_data (0); | |
10074 | break; | |
10075 | case 'b': | |
10076 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
10077 | demand_empty_rest_of_line (); | |
10078 | break; | |
10079 | ||
10080 | case 'r': | |
10081 | if (USE_GLOBAL_POINTER_OPT) | |
10082 | { | |
10083 | seg = subseg_new (RDATA_SECTION_NAME, | |
10084 | (subsegT) get_absolute_expression ()); | |
10085 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
10086 | { | |
10087 | bfd_set_section_flags (stdoutput, seg, | |
10088 | (SEC_ALLOC | |
10089 | | SEC_LOAD | |
10090 | | SEC_READONLY | |
10091 | | SEC_RELOC | |
10092 | | SEC_DATA)); | |
10093 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 10094 | record_alignment (seg, 4); |
252b5132 RH |
10095 | } |
10096 | demand_empty_rest_of_line (); | |
10097 | } | |
10098 | else | |
10099 | { | |
10100 | as_bad (_("No read only data section in this object file format")); | |
10101 | demand_empty_rest_of_line (); | |
10102 | return; | |
10103 | } | |
10104 | break; | |
10105 | ||
10106 | case 's': | |
10107 | if (USE_GLOBAL_POINTER_OPT) | |
10108 | { | |
10109 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
10110 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
10111 | { | |
10112 | bfd_set_section_flags (stdoutput, seg, | |
10113 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
10114 | | SEC_DATA); | |
10115 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 10116 | record_alignment (seg, 4); |
252b5132 RH |
10117 | } |
10118 | demand_empty_rest_of_line (); | |
10119 | break; | |
10120 | } | |
10121 | else | |
10122 | { | |
10123 | as_bad (_("Global pointers not supported; recompile -G 0")); | |
10124 | demand_empty_rest_of_line (); | |
10125 | return; | |
10126 | } | |
10127 | } | |
10128 | ||
10129 | auto_align = 1; | |
10130 | } | |
10131 | ||
10132 | void | |
10133 | mips_enable_auto_align () | |
10134 | { | |
10135 | auto_align = 1; | |
10136 | } | |
10137 | ||
10138 | static void | |
10139 | s_cons (log_size) | |
10140 | int log_size; | |
10141 | { | |
10142 | symbolS *label; | |
10143 | ||
10144 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
10145 | mips_emit_delays (false); | |
10146 | if (log_size > 0 && auto_align) | |
10147 | mips_align (log_size, 0, label); | |
10148 | mips_clear_insn_labels (); | |
10149 | cons (1 << log_size); | |
10150 | } | |
10151 | ||
10152 | static void | |
10153 | s_float_cons (type) | |
10154 | int type; | |
10155 | { | |
10156 | symbolS *label; | |
10157 | ||
10158 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
10159 | ||
10160 | mips_emit_delays (false); | |
10161 | ||
10162 | if (auto_align) | |
49309057 ILT |
10163 | { |
10164 | if (type == 'd') | |
10165 | mips_align (3, 0, label); | |
10166 | else | |
10167 | mips_align (2, 0, label); | |
10168 | } | |
252b5132 RH |
10169 | |
10170 | mips_clear_insn_labels (); | |
10171 | ||
10172 | float_cons (type); | |
10173 | } | |
10174 | ||
10175 | /* Handle .globl. We need to override it because on Irix 5 you are | |
10176 | permitted to say | |
10177 | .globl foo .text | |
10178 | where foo is an undefined symbol, to mean that foo should be | |
10179 | considered to be the address of a function. */ | |
10180 | ||
10181 | static void | |
10182 | s_mips_globl (x) | |
43841e91 | 10183 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
10184 | { |
10185 | char *name; | |
10186 | int c; | |
10187 | symbolS *symbolP; | |
10188 | flagword flag; | |
10189 | ||
10190 | name = input_line_pointer; | |
10191 | c = get_symbol_end (); | |
10192 | symbolP = symbol_find_or_make (name); | |
10193 | *input_line_pointer = c; | |
10194 | SKIP_WHITESPACE (); | |
10195 | ||
10196 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
10197 | being a function is apparently labelled as being an object. */ | |
10198 | flag = BSF_OBJECT; | |
10199 | ||
10200 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
10201 | { | |
10202 | char *secname; | |
10203 | asection *sec; | |
10204 | ||
10205 | secname = input_line_pointer; | |
10206 | c = get_symbol_end (); | |
10207 | sec = bfd_get_section_by_name (stdoutput, secname); | |
10208 | if (sec == NULL) | |
10209 | as_bad (_("%s: no such section"), secname); | |
10210 | *input_line_pointer = c; | |
10211 | ||
10212 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
10213 | flag = BSF_FUNCTION; | |
10214 | } | |
10215 | ||
49309057 | 10216 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
10217 | |
10218 | S_SET_EXTERNAL (symbolP); | |
10219 | demand_empty_rest_of_line (); | |
10220 | } | |
10221 | ||
10222 | static void | |
10223 | s_option (x) | |
43841e91 | 10224 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
10225 | { |
10226 | char *opt; | |
10227 | char c; | |
10228 | ||
10229 | opt = input_line_pointer; | |
10230 | c = get_symbol_end (); | |
10231 | ||
10232 | if (*opt == 'O') | |
10233 | { | |
10234 | /* FIXME: What does this mean? */ | |
10235 | } | |
10236 | else if (strncmp (opt, "pic", 3) == 0) | |
10237 | { | |
10238 | int i; | |
10239 | ||
10240 | i = atoi (opt + 3); | |
10241 | if (i == 0) | |
10242 | mips_pic = NO_PIC; | |
10243 | else if (i == 2) | |
10244 | mips_pic = SVR4_PIC; | |
10245 | else | |
10246 | as_bad (_(".option pic%d not supported"), i); | |
10247 | ||
10248 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) | |
10249 | { | |
10250 | if (g_switch_seen && g_switch_value != 0) | |
10251 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
10252 | g_switch_value = 0; | |
10253 | bfd_set_gp_size (stdoutput, 0); | |
10254 | } | |
10255 | } | |
10256 | else | |
10257 | as_warn (_("Unrecognized option \"%s\""), opt); | |
10258 | ||
10259 | *input_line_pointer = c; | |
10260 | demand_empty_rest_of_line (); | |
10261 | } | |
10262 | ||
10263 | /* This structure is used to hold a stack of .set values. */ | |
10264 | ||
10265 | struct mips_option_stack | |
10266 | { | |
10267 | struct mips_option_stack *next; | |
10268 | struct mips_set_options options; | |
10269 | }; | |
10270 | ||
10271 | static struct mips_option_stack *mips_opts_stack; | |
10272 | ||
10273 | /* Handle the .set pseudo-op. */ | |
10274 | ||
10275 | static void | |
10276 | s_mipsset (x) | |
43841e91 | 10277 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
10278 | { |
10279 | char *name = input_line_pointer, ch; | |
10280 | ||
10281 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10282 | input_line_pointer++; | |
10283 | ch = *input_line_pointer; | |
10284 | *input_line_pointer = '\0'; | |
10285 | ||
10286 | if (strcmp (name, "reorder") == 0) | |
10287 | { | |
10288 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
10289 | { | |
10290 | /* If we still have pending nops, we can discard them. The | |
10291 | usual nop handling will insert any that are still | |
10292 | needed. */ | |
10293 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
10294 | * (mips_opts.mips16 ? 2 : 4)); | |
10295 | prev_nop_frag = NULL; | |
10296 | } | |
10297 | mips_opts.noreorder = 0; | |
10298 | } | |
10299 | else if (strcmp (name, "noreorder") == 0) | |
10300 | { | |
10301 | mips_emit_delays (true); | |
10302 | mips_opts.noreorder = 1; | |
10303 | mips_any_noreorder = 1; | |
10304 | } | |
10305 | else if (strcmp (name, "at") == 0) | |
10306 | { | |
10307 | mips_opts.noat = 0; | |
10308 | } | |
10309 | else if (strcmp (name, "noat") == 0) | |
10310 | { | |
10311 | mips_opts.noat = 1; | |
10312 | } | |
10313 | else if (strcmp (name, "macro") == 0) | |
10314 | { | |
10315 | mips_opts.warn_about_macros = 0; | |
10316 | } | |
10317 | else if (strcmp (name, "nomacro") == 0) | |
10318 | { | |
10319 | if (mips_opts.noreorder == 0) | |
10320 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
10321 | mips_opts.warn_about_macros = 1; | |
10322 | } | |
10323 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
10324 | { | |
10325 | mips_opts.nomove = 0; | |
10326 | } | |
10327 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
10328 | { | |
10329 | mips_opts.nomove = 1; | |
10330 | } | |
10331 | else if (strcmp (name, "bopt") == 0) | |
10332 | { | |
10333 | mips_opts.nobopt = 0; | |
10334 | } | |
10335 | else if (strcmp (name, "nobopt") == 0) | |
10336 | { | |
10337 | mips_opts.nobopt = 1; | |
10338 | } | |
10339 | else if (strcmp (name, "mips16") == 0 | |
10340 | || strcmp (name, "MIPS-16") == 0) | |
10341 | mips_opts.mips16 = 1; | |
10342 | else if (strcmp (name, "nomips16") == 0 | |
10343 | || strcmp (name, "noMIPS-16") == 0) | |
10344 | mips_opts.mips16 = 0; | |
10345 | else if (strncmp (name, "mips", 4) == 0) | |
10346 | { | |
10347 | int isa; | |
10348 | ||
10349 | /* Permit the user to change the ISA on the fly. Needless to | |
10350 | say, misuse can cause serious problems. */ | |
10351 | isa = atoi (name + 4); | |
10352 | if (isa == 0) | |
10353 | mips_opts.isa = file_mips_isa; | |
10354 | else if (isa < 1 || isa > 4) | |
10355 | as_bad (_("unknown ISA level")); | |
10356 | else | |
10357 | mips_opts.isa = isa; | |
10358 | } | |
10359 | else if (strcmp (name, "autoextend") == 0) | |
10360 | mips_opts.noautoextend = 0; | |
10361 | else if (strcmp (name, "noautoextend") == 0) | |
10362 | mips_opts.noautoextend = 1; | |
10363 | else if (strcmp (name, "push") == 0) | |
10364 | { | |
10365 | struct mips_option_stack *s; | |
10366 | ||
10367 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
10368 | s->next = mips_opts_stack; | |
10369 | s->options = mips_opts; | |
10370 | mips_opts_stack = s; | |
10371 | } | |
10372 | else if (strcmp (name, "pop") == 0) | |
10373 | { | |
10374 | struct mips_option_stack *s; | |
10375 | ||
10376 | s = mips_opts_stack; | |
10377 | if (s == NULL) | |
10378 | as_bad (_(".set pop with no .set push")); | |
10379 | else | |
10380 | { | |
10381 | /* If we're changing the reorder mode we need to handle | |
10382 | delay slots correctly. */ | |
10383 | if (s->options.noreorder && ! mips_opts.noreorder) | |
10384 | mips_emit_delays (true); | |
10385 | else if (! s->options.noreorder && mips_opts.noreorder) | |
10386 | { | |
10387 | if (prev_nop_frag != NULL) | |
10388 | { | |
10389 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
10390 | * (mips_opts.mips16 ? 2 : 4)); | |
10391 | prev_nop_frag = NULL; | |
10392 | } | |
10393 | } | |
10394 | ||
10395 | mips_opts = s->options; | |
10396 | mips_opts_stack = s->next; | |
10397 | free (s); | |
10398 | } | |
10399 | } | |
10400 | else | |
10401 | { | |
10402 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
10403 | } | |
10404 | *input_line_pointer = ch; | |
10405 | demand_empty_rest_of_line (); | |
10406 | } | |
10407 | ||
10408 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
10409 | .option pic2. It means to generate SVR4 PIC calls. */ | |
10410 | ||
10411 | static void | |
10412 | s_abicalls (ignore) | |
43841e91 | 10413 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10414 | { |
10415 | mips_pic = SVR4_PIC; | |
10416 | if (USE_GLOBAL_POINTER_OPT) | |
10417 | { | |
10418 | if (g_switch_seen && g_switch_value != 0) | |
10419 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
10420 | g_switch_value = 0; | |
10421 | } | |
10422 | bfd_set_gp_size (stdoutput, 0); | |
10423 | demand_empty_rest_of_line (); | |
10424 | } | |
10425 | ||
10426 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
10427 | PIC code. It sets the $gp register for the function based on the | |
10428 | function address, which is in the register named in the argument. | |
10429 | This uses a relocation against _gp_disp, which is handled specially | |
10430 | by the linker. The result is: | |
10431 | lui $gp,%hi(_gp_disp) | |
10432 | addiu $gp,$gp,%lo(_gp_disp) | |
10433 | addu $gp,$gp,.cpload argument | |
10434 | The .cpload argument is normally $25 == $t9. */ | |
10435 | ||
10436 | static void | |
10437 | s_cpload (ignore) | |
43841e91 | 10438 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10439 | { |
10440 | expressionS ex; | |
10441 | int icnt = 0; | |
10442 | ||
10443 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ | |
10444 | if (mips_pic != SVR4_PIC) | |
10445 | { | |
10446 | s_ignore (0); | |
10447 | return; | |
10448 | } | |
10449 | ||
10450 | /* .cpload should be a in .set noreorder section. */ | |
10451 | if (mips_opts.noreorder == 0) | |
10452 | as_warn (_(".cpload not in noreorder section")); | |
10453 | ||
10454 | ex.X_op = O_symbol; | |
10455 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
10456 | ex.X_op_symbol = NULL; | |
10457 | ex.X_add_number = 0; | |
10458 | ||
10459 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 10460 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 RH |
10461 | |
10462 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); | |
10463 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
10464 | (int) BFD_RELOC_LO16); | |
10465 | ||
10466 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", | |
10467 | GP, GP, tc_get_register (0)); | |
10468 | ||
10469 | demand_empty_rest_of_line (); | |
10470 | } | |
10471 | ||
10472 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
10473 | offset from $sp. The offset is remembered, and after making a PIC | |
10474 | call $gp is restored from that location. */ | |
10475 | ||
10476 | static void | |
10477 | s_cprestore (ignore) | |
43841e91 | 10478 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10479 | { |
10480 | expressionS ex; | |
10481 | int icnt = 0; | |
10482 | ||
10483 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ | |
10484 | if (mips_pic != SVR4_PIC) | |
10485 | { | |
10486 | s_ignore (0); | |
10487 | return; | |
10488 | } | |
10489 | ||
10490 | mips_cprestore_offset = get_absolute_expression (); | |
10491 | ||
10492 | ex.X_op = O_constant; | |
10493 | ex.X_add_symbol = NULL; | |
10494 | ex.X_op_symbol = NULL; | |
10495 | ex.X_add_number = mips_cprestore_offset; | |
10496 | ||
10497 | macro_build ((char *) NULL, &icnt, &ex, | |
10498 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 10499 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
10500 | ? "sw" : "sd"), |
10501 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); | |
10502 | ||
10503 | demand_empty_rest_of_line (); | |
10504 | } | |
10505 | ||
10506 | /* Handle the .gpword pseudo-op. This is used when generating PIC | |
10507 | code. It generates a 32 bit GP relative reloc. */ | |
10508 | ||
10509 | static void | |
10510 | s_gpword (ignore) | |
43841e91 | 10511 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10512 | { |
10513 | symbolS *label; | |
10514 | expressionS ex; | |
10515 | char *p; | |
10516 | ||
10517 | /* When not generating PIC code, this is treated as .word. */ | |
10518 | if (mips_pic != SVR4_PIC) | |
10519 | { | |
10520 | s_cons (2); | |
10521 | return; | |
10522 | } | |
10523 | ||
10524 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
10525 | mips_emit_delays (true); | |
10526 | if (auto_align) | |
10527 | mips_align (2, 0, label); | |
10528 | mips_clear_insn_labels (); | |
10529 | ||
10530 | expression (&ex); | |
10531 | ||
10532 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
10533 | { | |
10534 | as_bad (_("Unsupported use of .gpword")); | |
10535 | ignore_rest_of_line (); | |
10536 | } | |
10537 | ||
10538 | p = frag_more (4); | |
10539 | md_number_to_chars (p, (valueT) 0, 4); | |
10540 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
10541 | BFD_RELOC_MIPS_GPREL32); | |
10542 | ||
10543 | demand_empty_rest_of_line (); | |
10544 | } | |
10545 | ||
10546 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
10547 | tables in SVR4 PIC code. */ | |
10548 | ||
10549 | static void | |
10550 | s_cpadd (ignore) | |
43841e91 | 10551 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10552 | { |
10553 | int icnt = 0; | |
10554 | int reg; | |
10555 | ||
10556 | /* This is ignored when not generating SVR4 PIC code. */ | |
10557 | if (mips_pic != SVR4_PIC) | |
10558 | { | |
10559 | s_ignore (0); | |
10560 | return; | |
10561 | } | |
10562 | ||
10563 | /* Add $gp to the register named as an argument. */ | |
10564 | reg = tc_get_register (0); | |
10565 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
10566 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 10567 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
10568 | ? "addu" : "daddu"), |
10569 | "d,v,t", reg, reg, GP); | |
10570 | ||
10571 | demand_empty_rest_of_line (); | |
10572 | } | |
10573 | ||
10574 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
10575 | mips16 mode. This permits the linker to handle them specially, | |
10576 | such as generating jalx instructions when needed. We also make | |
10577 | them odd for the duration of the assembly, in order to generate the | |
10578 | right sort of code. We will make them even in the adjust_symtab | |
10579 | routine, while leaving them marked. This is convenient for the | |
10580 | debugger and the disassembler. The linker knows to make them odd | |
10581 | again. */ | |
10582 | ||
10583 | static void | |
10584 | s_insn (ignore) | |
43841e91 | 10585 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10586 | { |
10587 | if (mips_opts.mips16) | |
10588 | mips16_mark_labels (); | |
10589 | ||
10590 | demand_empty_rest_of_line (); | |
10591 | } | |
10592 | ||
10593 | /* Handle a .stabn directive. We need these in order to mark a label | |
10594 | as being a mips16 text label correctly. Sometimes the compiler | |
10595 | will emit a label, followed by a .stabn, and then switch sections. | |
10596 | If the label and .stabn are in mips16 mode, then the label is | |
10597 | really a mips16 text label. */ | |
10598 | ||
10599 | static void | |
10600 | s_mips_stab (type) | |
10601 | int type; | |
10602 | { | |
10603 | if (type == 'n' && mips_opts.mips16) | |
10604 | mips16_mark_labels (); | |
10605 | ||
10606 | s_stab (type); | |
10607 | } | |
10608 | ||
10609 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
10610 | */ | |
10611 | ||
10612 | static void | |
10613 | s_mips_weakext (ignore) | |
43841e91 | 10614 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
10615 | { |
10616 | char *name; | |
10617 | int c; | |
10618 | symbolS *symbolP; | |
10619 | expressionS exp; | |
10620 | ||
10621 | name = input_line_pointer; | |
10622 | c = get_symbol_end (); | |
10623 | symbolP = symbol_find_or_make (name); | |
10624 | S_SET_WEAK (symbolP); | |
10625 | *input_line_pointer = c; | |
10626 | ||
10627 | SKIP_WHITESPACE (); | |
10628 | ||
10629 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
10630 | { | |
10631 | if (S_IS_DEFINED (symbolP)) | |
10632 | { | |
10633 | as_bad ("Ignoring attempt to redefine symbol `%s'.", | |
10634 | S_GET_NAME (symbolP)); | |
10635 | ignore_rest_of_line (); | |
10636 | return; | |
10637 | } | |
10638 | ||
10639 | if (*input_line_pointer == ',') | |
10640 | { | |
10641 | ++input_line_pointer; | |
10642 | SKIP_WHITESPACE (); | |
10643 | } | |
10644 | ||
10645 | expression (&exp); | |
10646 | if (exp.X_op != O_symbol) | |
10647 | { | |
10648 | as_bad ("bad .weakext directive"); | |
10649 | ignore_rest_of_line(); | |
10650 | return; | |
10651 | } | |
49309057 | 10652 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
10653 | } |
10654 | ||
10655 | demand_empty_rest_of_line (); | |
10656 | } | |
10657 | ||
10658 | /* Parse a register string into a number. Called from the ECOFF code | |
10659 | to parse .frame. The argument is non-zero if this is the frame | |
10660 | register, so that we can record it in mips_frame_reg. */ | |
10661 | ||
10662 | int | |
10663 | tc_get_register (frame) | |
10664 | int frame; | |
10665 | { | |
10666 | int reg; | |
10667 | ||
10668 | SKIP_WHITESPACE (); | |
10669 | if (*input_line_pointer++ != '$') | |
10670 | { | |
10671 | as_warn (_("expected `$'")); | |
10672 | reg = 0; | |
10673 | } | |
10674 | else if (isdigit ((unsigned char) *input_line_pointer)) | |
10675 | { | |
10676 | reg = get_absolute_expression (); | |
10677 | if (reg < 0 || reg >= 32) | |
10678 | { | |
10679 | as_warn (_("Bad register number")); | |
10680 | reg = 0; | |
10681 | } | |
10682 | } | |
10683 | else | |
10684 | { | |
10685 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
10686 | reg = FP; | |
10687 | else if (strncmp (input_line_pointer, "sp", 2) == 0) | |
10688 | reg = SP; | |
10689 | else if (strncmp (input_line_pointer, "gp", 2) == 0) | |
10690 | reg = GP; | |
10691 | else if (strncmp (input_line_pointer, "at", 2) == 0) | |
10692 | reg = AT; | |
10693 | else | |
10694 | { | |
10695 | as_warn (_("Unrecognized register name")); | |
10696 | reg = 0; | |
10697 | } | |
10698 | input_line_pointer += 2; | |
10699 | } | |
10700 | if (frame) | |
10701 | mips_frame_reg = reg != 0 ? reg : SP; | |
10702 | return reg; | |
10703 | } | |
10704 | ||
10705 | valueT | |
10706 | md_section_align (seg, addr) | |
10707 | asection *seg; | |
10708 | valueT addr; | |
10709 | { | |
10710 | int align = bfd_get_section_alignment (stdoutput, seg); | |
10711 | ||
10712 | #ifdef OBJ_ELF | |
10713 | /* We don't need to align ELF sections to the full alignment. | |
10714 | However, Irix 5 may prefer that we align them at least to a 16 | |
10715 | byte boundary. We don't bother to align the sections if we are | |
10716 | targeted for an embedded system. */ | |
10717 | if (strcmp (TARGET_OS, "elf") == 0) | |
10718 | return addr; | |
10719 | if (align > 4) | |
10720 | align = 4; | |
10721 | #endif | |
10722 | ||
10723 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
10724 | } | |
10725 | ||
10726 | /* Utility routine, called from above as well. If called while the | |
10727 | input file is still being read, it's only an approximation. (For | |
10728 | example, a symbol may later become defined which appeared to be | |
10729 | undefined earlier.) */ | |
10730 | ||
10731 | static int | |
10732 | nopic_need_relax (sym, before_relaxing) | |
10733 | symbolS *sym; | |
10734 | int before_relaxing; | |
10735 | { | |
10736 | if (sym == 0) | |
10737 | return 0; | |
10738 | ||
10739 | if (USE_GLOBAL_POINTER_OPT) | |
10740 | { | |
10741 | const char *symname; | |
10742 | int change; | |
10743 | ||
10744 | /* Find out whether this symbol can be referenced off the GP | |
10745 | register. It can be if it is smaller than the -G size or if | |
10746 | it is in the .sdata or .sbss section. Certain symbols can | |
10747 | not be referenced off the GP, although it appears as though | |
10748 | they can. */ | |
10749 | symname = S_GET_NAME (sym); | |
10750 | if (symname != (const char *) NULL | |
10751 | && (strcmp (symname, "eprol") == 0 | |
10752 | || strcmp (symname, "etext") == 0 | |
10753 | || strcmp (symname, "_gp") == 0 | |
10754 | || strcmp (symname, "edata") == 0 | |
10755 | || strcmp (symname, "_fbss") == 0 | |
10756 | || strcmp (symname, "_fdata") == 0 | |
10757 | || strcmp (symname, "_ftext") == 0 | |
10758 | || strcmp (symname, "end") == 0 | |
10759 | || strcmp (symname, "_gp_disp") == 0)) | |
10760 | change = 1; | |
10761 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
10762 | && (0 | |
10763 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
10764 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
10765 | && (symbol_get_obj (sym)->ecoff_extern_size | |
10766 | <= g_switch_value)) | |
252b5132 RH |
10767 | #endif |
10768 | /* We must defer this decision until after the whole | |
10769 | file has been read, since there might be a .extern | |
10770 | after the first use of this symbol. */ | |
10771 | || (before_relaxing | |
10772 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 10773 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
10774 | #endif |
10775 | && S_GET_VALUE (sym) == 0) | |
10776 | || (S_GET_VALUE (sym) != 0 | |
10777 | && S_GET_VALUE (sym) <= g_switch_value))) | |
10778 | change = 0; | |
10779 | else | |
10780 | { | |
10781 | const char *segname; | |
10782 | ||
10783 | segname = segment_name (S_GET_SEGMENT (sym)); | |
10784 | assert (strcmp (segname, ".lit8") != 0 | |
10785 | && strcmp (segname, ".lit4") != 0); | |
10786 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
10787 | && strcmp (segname, ".sbss") != 0 |
10788 | && strncmp (segname, ".sdata.", 7) != 0 | |
10789 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
10790 | } |
10791 | return change; | |
10792 | } | |
10793 | else | |
10794 | /* We are not optimizing for the GP register. */ | |
10795 | return 1; | |
10796 | } | |
10797 | ||
10798 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an | |
10799 | extended opcode. SEC is the section the frag is in. */ | |
10800 | ||
10801 | static int | |
10802 | mips16_extended_frag (fragp, sec, stretch) | |
10803 | fragS *fragp; | |
10804 | asection *sec; | |
10805 | long stretch; | |
10806 | { | |
10807 | int type; | |
10808 | register const struct mips16_immed_operand *op; | |
10809 | offsetT val; | |
10810 | int mintiny, maxtiny; | |
10811 | segT symsec; | |
10812 | ||
10813 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
10814 | return 0; | |
10815 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
10816 | return 1; | |
10817 | ||
10818 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
10819 | op = mips16_immed_operands; | |
10820 | while (op->type != type) | |
10821 | { | |
10822 | ++op; | |
10823 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10824 | } | |
10825 | ||
10826 | if (op->unsp) | |
10827 | { | |
10828 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10829 | { | |
10830 | mintiny = 1; | |
10831 | maxtiny = 1 << op->nbits; | |
10832 | } | |
10833 | else | |
10834 | { | |
10835 | mintiny = 0; | |
10836 | maxtiny = (1 << op->nbits) - 1; | |
10837 | } | |
10838 | } | |
10839 | else | |
10840 | { | |
10841 | mintiny = - (1 << (op->nbits - 1)); | |
10842 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10843 | } | |
10844 | ||
49309057 ILT |
10845 | /* We can't always call S_GET_VALUE here, because we don't want to |
10846 | lock in a particular frag address. */ | |
10847 | if (symbol_constant_p (fragp->fr_symbol)) | |
252b5132 | 10848 | { |
49309057 ILT |
10849 | val = (S_GET_VALUE (fragp->fr_symbol) |
10850 | + symbol_get_frag (fragp->fr_symbol)->fr_address); | |
252b5132 RH |
10851 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
10852 | } | |
49309057 ILT |
10853 | else if (symbol_equated_p (fragp->fr_symbol) |
10854 | && (symbol_constant_p | |
10855 | (symbol_get_value_expression (fragp->fr_symbol)->X_add_symbol))) | |
252b5132 | 10856 | { |
49309057 ILT |
10857 | symbolS *eqsym; |
10858 | ||
10859 | eqsym = symbol_get_value_expression (fragp->fr_symbol)->X_add_symbol; | |
10860 | val = (S_GET_VALUE (eqsym) | |
10861 | + symbol_get_frag (eqsym)->fr_address | |
10862 | + symbol_get_value_expression (fragp->fr_symbol)->X_add_number | |
10863 | + symbol_get_frag (fragp->fr_symbol)->fr_address); | |
10864 | symsec = S_GET_SEGMENT (eqsym); | |
252b5132 RH |
10865 | } |
10866 | else | |
10867 | return 1; | |
10868 | ||
10869 | if (op->pcrel) | |
10870 | { | |
10871 | addressT addr; | |
10872 | ||
10873 | /* We won't have the section when we are called from | |
10874 | mips_relax_frag. However, we will always have been called | |
10875 | from md_estimate_size_before_relax first. If this is a | |
10876 | branch to a different section, we mark it as such. If SEC is | |
10877 | NULL, and the frag is not marked, then it must be a branch to | |
10878 | the same section. */ | |
10879 | if (sec == NULL) | |
10880 | { | |
10881 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
10882 | return 1; | |
10883 | } | |
10884 | else | |
10885 | { | |
10886 | if (symsec != sec) | |
10887 | { | |
10888 | fragp->fr_subtype = | |
10889 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10890 | ||
10891 | /* FIXME: We should support this, and let the linker | |
10892 | catch branches and loads that are out of range. */ | |
10893 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
10894 | _("unsupported PC relative reference to different section")); | |
10895 | ||
10896 | return 1; | |
10897 | } | |
10898 | } | |
10899 | ||
10900 | /* In this case, we know for sure that the symbol fragment is in | |
10901 | the same section. If the fr_address of the symbol fragment | |
10902 | is greater then the address of this fragment we want to add | |
10903 | in STRETCH in order to get a better estimate of the address. | |
10904 | This particularly matters because of the shift bits. */ | |
10905 | if (stretch != 0 | |
49309057 ILT |
10906 | && (symbol_get_frag (fragp->fr_symbol)->fr_address |
10907 | >= fragp->fr_address)) | |
252b5132 RH |
10908 | { |
10909 | fragS *f; | |
10910 | ||
10911 | /* Adjust stretch for any alignment frag. Note that if have | |
10912 | been expanding the earlier code, the symbol may be | |
10913 | defined in what appears to be an earlier frag. FIXME: | |
10914 | This doesn't handle the fr_subtype field, which specifies | |
10915 | a maximum number of bytes to skip when doing an | |
10916 | alignment. */ | |
10917 | for (f = fragp; | |
49309057 | 10918 | f != NULL && f != symbol_get_frag (fragp->fr_symbol); |
252b5132 RH |
10919 | f = f->fr_next) |
10920 | { | |
10921 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
10922 | { | |
10923 | if (stretch < 0) | |
10924 | stretch = - ((- stretch) | |
10925 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
10926 | else | |
10927 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
10928 | if (stretch == 0) | |
10929 | break; | |
10930 | } | |
10931 | } | |
10932 | if (f != NULL) | |
10933 | val += stretch; | |
10934 | } | |
10935 | ||
10936 | addr = fragp->fr_address + fragp->fr_fix; | |
10937 | ||
10938 | /* The base address rules are complicated. The base address of | |
10939 | a branch is the following instruction. The base address of a | |
10940 | PC relative load or add is the instruction itself, but if it | |
10941 | is in a delay slot (in which case it can not be extended) use | |
10942 | the address of the instruction whose delay slot it is in. */ | |
10943 | if (type == 'p' || type == 'q') | |
10944 | { | |
10945 | addr += 2; | |
10946 | ||
10947 | /* If we are currently assuming that this frag should be | |
10948 | extended, then, the current address is two bytes | |
10949 | higher. */ | |
10950 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10951 | addr += 2; | |
10952 | ||
10953 | /* Ignore the low bit in the target, since it will be set | |
10954 | for a text label. */ | |
10955 | if ((val & 1) != 0) | |
10956 | --val; | |
10957 | } | |
10958 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
10959 | addr -= 4; | |
10960 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
10961 | addr -= 2; | |
10962 | ||
10963 | val -= addr & ~ ((1 << op->shift) - 1); | |
10964 | ||
10965 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10966 | if (type == 'p' || type == 'q') | |
10967 | val /= 2; | |
10968 | ||
10969 | /* If any of the shifted bits are set, we must use an extended | |
10970 | opcode. If the address depends on the size of this | |
10971 | instruction, this can lead to a loop, so we arrange to always | |
10972 | use an extended opcode. We only check this when we are in | |
10973 | the main relaxation loop, when SEC is NULL. */ | |
10974 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
10975 | { | |
10976 | fragp->fr_subtype = | |
10977 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10978 | return 1; | |
10979 | } | |
10980 | ||
10981 | /* If we are about to mark a frag as extended because the value | |
10982 | is precisely maxtiny + 1, then there is a chance of an | |
10983 | infinite loop as in the following code: | |
10984 | la $4,foo | |
10985 | .skip 1020 | |
10986 | .align 2 | |
10987 | foo: | |
10988 | In this case when the la is extended, foo is 0x3fc bytes | |
10989 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
10990 | the la must be extended. To avoid this loop, we mark the | |
10991 | frag as extended if it was small, and is about to become | |
10992 | extended with a value of maxtiny + 1. */ | |
10993 | if (val == ((maxtiny + 1) << op->shift) | |
10994 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
10995 | && sec == NULL) | |
10996 | { | |
10997 | fragp->fr_subtype = | |
10998 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10999 | return 1; | |
11000 | } | |
11001 | } | |
11002 | else if (symsec != absolute_section && sec != NULL) | |
11003 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
11004 | ||
11005 | if ((val & ((1 << op->shift) - 1)) != 0 | |
11006 | || val < (mintiny << op->shift) | |
11007 | || val > (maxtiny << op->shift)) | |
11008 | return 1; | |
11009 | else | |
11010 | return 0; | |
11011 | } | |
11012 | ||
11013 | /* Estimate the size of a frag before relaxing. Unless this is the | |
11014 | mips16, we are not really relaxing here, and the final size is | |
11015 | encoded in the subtype information. For the mips16, we have to | |
11016 | decide whether we are using an extended opcode or not. */ | |
11017 | ||
11018 | /*ARGSUSED*/ | |
11019 | int | |
11020 | md_estimate_size_before_relax (fragp, segtype) | |
11021 | fragS *fragp; | |
11022 | asection *segtype; | |
11023 | { | |
43841e91 | 11024 | int change = 0; |
8614eeee | 11025 | boolean linkonce = false; |
252b5132 RH |
11026 | |
11027 | if (RELAX_MIPS16_P (fragp->fr_subtype)) | |
11028 | { | |
11029 | if (mips16_extended_frag (fragp, segtype, 0)) | |
11030 | { | |
11031 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
11032 | return 4; | |
11033 | } | |
11034 | else | |
11035 | { | |
11036 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
11037 | return 2; | |
11038 | } | |
11039 | } | |
11040 | ||
11041 | if (mips_pic == NO_PIC) | |
11042 | { | |
11043 | change = nopic_need_relax (fragp->fr_symbol, 0); | |
11044 | } | |
11045 | else if (mips_pic == SVR4_PIC) | |
11046 | { | |
11047 | symbolS *sym; | |
11048 | asection *symsec; | |
11049 | ||
11050 | sym = fragp->fr_symbol; | |
11051 | ||
11052 | /* Handle the case of a symbol equated to another symbol. */ | |
49309057 | 11053 | while (symbol_equated_p (sym) |
252b5132 RH |
11054 | && (! S_IS_DEFINED (sym) || S_IS_COMMON (sym))) |
11055 | { | |
11056 | symbolS *n; | |
11057 | ||
11058 | /* It's possible to get a loop here in a badly written | |
11059 | program. */ | |
49309057 | 11060 | n = symbol_get_value_expression (sym)->X_add_symbol; |
252b5132 RH |
11061 | if (n == sym) |
11062 | break; | |
11063 | sym = n; | |
11064 | } | |
11065 | ||
11066 | symsec = S_GET_SEGMENT (sym); | |
11067 | ||
8614eeee UC |
11068 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ |
11069 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
11070 | { | |
11071 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
11072 | != 0) | |
11073 | linkonce = true; | |
11074 | ||
11075 | /* The GNU toolchain uses an extension for ELF: a section | |
11076 | beginning with the magic string .gnu.linkonce is a linkonce | |
11077 | section. */ | |
11078 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
11079 | sizeof ".gnu.linkonce" - 1) == 0) | |
11080 | linkonce = true; | |
11081 | } | |
11082 | ||
252b5132 RH |
11083 | /* This must duplicate the test in adjust_reloc_syms. */ |
11084 | change = (symsec != &bfd_und_section | |
11085 | && symsec != &bfd_abs_section | |
426b0403 | 11086 | && ! bfd_is_com_section (symsec) |
8614eeee | 11087 | && !linkonce |
426b0403 AM |
11088 | #ifdef OBJ_ELF |
11089 | /* A weak symbol is treated as external. */ | |
11090 | && ! S_IS_WEAK (sym) | |
11091 | #endif | |
11092 | ); | |
252b5132 RH |
11093 | } |
11094 | else | |
11095 | abort (); | |
11096 | ||
11097 | if (change) | |
11098 | { | |
11099 | /* Record the offset to the first reloc in the fr_opcode field. | |
11100 | This lets md_convert_frag and tc_gen_reloc know that the code | |
11101 | must be expanded. */ | |
11102 | fragp->fr_opcode = (fragp->fr_literal | |
11103 | + fragp->fr_fix | |
11104 | - RELAX_OLD (fragp->fr_subtype) | |
11105 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
11106 | /* FIXME: This really needs as_warn_where. */ | |
11107 | if (RELAX_WARN (fragp->fr_subtype)) | |
11108 | as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\"")); | |
11109 | } | |
11110 | ||
11111 | if (! change) | |
11112 | return 0; | |
11113 | else | |
11114 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
11115 | } | |
11116 | ||
11117 | /* This is called to see whether a reloc against a defined symbol | |
11118 | should be converted into a reloc against a section. Don't adjust | |
11119 | MIPS16 jump relocations, so we don't have to worry about the format | |
11120 | of the offset in the .o file. Don't adjust relocations against | |
11121 | mips16 symbols, so that the linker can find them if it needs to set | |
11122 | up a stub. */ | |
11123 | ||
11124 | int | |
11125 | mips_fix_adjustable (fixp) | |
11126 | fixS *fixp; | |
11127 | { | |
11128 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
11129 | return 0; | |
11130 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
11131 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11132 | return 0; | |
11133 | if (fixp->fx_addsy == NULL) | |
11134 | return 1; | |
11135 | #ifdef OBJ_ELF | |
11136 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
11137 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
11138 | && fixp->fx_subsy == NULL) | |
11139 | return 0; | |
11140 | #endif | |
11141 | return 1; | |
11142 | } | |
11143 | ||
11144 | /* Translate internal representation of relocation info to BFD target | |
11145 | format. */ | |
11146 | ||
11147 | arelent ** | |
11148 | tc_gen_reloc (section, fixp) | |
43841e91 | 11149 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
11150 | fixS *fixp; |
11151 | { | |
11152 | static arelent *retval[4]; | |
11153 | arelent *reloc; | |
11154 | bfd_reloc_code_real_type code; | |
11155 | ||
11156 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); | |
11157 | retval[1] = NULL; | |
11158 | ||
49309057 ILT |
11159 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
11160 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
11161 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
11162 | ||
11163 | if (mips_pic == EMBEDDED_PIC | |
11164 | && SWITCH_TABLE (fixp)) | |
11165 | { | |
11166 | /* For a switch table entry we use a special reloc. The addend | |
11167 | is actually the difference between the reloc address and the | |
11168 | subtrahend. */ | |
11169 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
11170 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) | |
11171 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); | |
11172 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
11173 | } | |
bb2d6cd7 GK |
11174 | else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour) |
11175 | reloc->addend = fixp->fx_addnumber; | |
252b5132 RH |
11176 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
11177 | { | |
11178 | /* We use a special addend for an internal RELLO reloc. */ | |
49309057 | 11179 | if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
11180 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); |
11181 | else | |
11182 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
11183 | } | |
11184 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
11185 | { | |
11186 | assert (fixp->fx_next != NULL | |
11187 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
11188 | /* We use a special addend for an internal RELHI reloc. The | |
11189 | reloc is relative to the RELLO; adjust the addend | |
11190 | accordingly. */ | |
49309057 | 11191 | if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
11192 | reloc->addend = (fixp->fx_next->fx_frag->fr_address |
11193 | + fixp->fx_next->fx_where | |
11194 | - S_GET_VALUE (fixp->fx_subsy)); | |
11195 | else | |
11196 | reloc->addend = (fixp->fx_addnumber | |
11197 | + fixp->fx_next->fx_frag->fr_address | |
11198 | + fixp->fx_next->fx_where); | |
11199 | } | |
252b5132 RH |
11200 | else |
11201 | { | |
11202 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) | |
11203 | /* A gruesome hack which is a result of the gruesome gas reloc | |
11204 | handling. */ | |
11205 | reloc->addend = reloc->address; | |
11206 | else | |
11207 | reloc->addend = -reloc->address; | |
11208 | } | |
11209 | ||
11210 | /* If this is a variant frag, we may need to adjust the existing | |
11211 | reloc and generate a new one. */ | |
11212 | if (fixp->fx_frag->fr_opcode != NULL | |
11213 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
11214 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
11215 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 | |
11216 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
11217 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
11218 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
11219 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
11220 | { | |
11221 | arelent *reloc2; | |
11222 | ||
11223 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); | |
11224 | ||
11225 | /* If this is not the last reloc in this frag, then we have two | |
11226 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a | |
11227 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
11228 | the second one handle all of them. */ | |
11229 | if (fixp->fx_next != NULL | |
11230 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
11231 | { | |
11232 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
11233 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
11234 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
11235 | && (fixp->fx_next->fx_r_type | |
11236 | == BFD_RELOC_MIPS_GOT_LO16)) | |
11237 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
11238 | && (fixp->fx_next->fx_r_type | |
11239 | == BFD_RELOC_MIPS_CALL_LO16))); | |
11240 | retval[0] = NULL; | |
11241 | return retval; | |
11242 | } | |
11243 | ||
11244 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
11245 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
11246 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
11247 | retval[2] = NULL; | |
49309057 ILT |
11248 | reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
11249 | *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
11250 | reloc2->address = (reloc->address |
11251 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
11252 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
11253 | reloc2->addend = fixp->fx_addnumber; | |
11254 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
11255 | assert (reloc2->howto != NULL); | |
11256 | ||
11257 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
11258 | { | |
11259 | arelent *reloc3; | |
11260 | ||
11261 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
11262 | retval[3] = NULL; | |
11263 | *reloc3 = *reloc2; | |
11264 | reloc3->address += 4; | |
11265 | } | |
11266 | ||
11267 | if (mips_pic == NO_PIC) | |
11268 | { | |
11269 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
11270 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
11271 | } | |
11272 | else if (mips_pic == SVR4_PIC) | |
11273 | { | |
11274 | switch (fixp->fx_r_type) | |
11275 | { | |
11276 | default: | |
11277 | abort (); | |
11278 | case BFD_RELOC_MIPS_GOT16: | |
11279 | break; | |
11280 | case BFD_RELOC_MIPS_CALL16: | |
11281 | case BFD_RELOC_MIPS_GOT_LO16: | |
11282 | case BFD_RELOC_MIPS_CALL_LO16: | |
11283 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
11284 | break; | |
11285 | } | |
11286 | } | |
11287 | else | |
11288 | abort (); | |
11289 | } | |
11290 | ||
11291 | /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry | |
11292 | to be used in the relocation's section offset. */ | |
11293 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11294 | { | |
11295 | reloc->address = reloc->addend; | |
11296 | reloc->addend = 0; | |
11297 | } | |
11298 | ||
11299 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that | |
11300 | fixup_segment converted a non-PC relative reloc into a PC | |
11301 | relative reloc. In such a case, we need to convert the reloc | |
11302 | code. */ | |
11303 | code = fixp->fx_r_type; | |
11304 | if (fixp->fx_pcrel) | |
11305 | { | |
11306 | switch (code) | |
11307 | { | |
11308 | case BFD_RELOC_8: | |
11309 | code = BFD_RELOC_8_PCREL; | |
11310 | break; | |
11311 | case BFD_RELOC_16: | |
11312 | code = BFD_RELOC_16_PCREL; | |
11313 | break; | |
11314 | case BFD_RELOC_32: | |
11315 | code = BFD_RELOC_32_PCREL; | |
11316 | break; | |
11317 | case BFD_RELOC_64: | |
11318 | code = BFD_RELOC_64_PCREL; | |
11319 | break; | |
11320 | case BFD_RELOC_8_PCREL: | |
11321 | case BFD_RELOC_16_PCREL: | |
11322 | case BFD_RELOC_32_PCREL: | |
11323 | case BFD_RELOC_64_PCREL: | |
11324 | case BFD_RELOC_16_PCREL_S2: | |
11325 | case BFD_RELOC_PCREL_HI16_S: | |
11326 | case BFD_RELOC_PCREL_LO16: | |
11327 | break; | |
11328 | default: | |
11329 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11330 | _("Cannot make %s relocation PC relative"), | |
11331 | bfd_get_reloc_code_name (code)); | |
11332 | } | |
11333 | } | |
11334 | ||
11335 | /* To support a PC relative reloc when generating embedded PIC code | |
11336 | for ECOFF, we use a Cygnus extension. We check for that here to | |
11337 | make sure that we don't let such a reloc escape normally. */ | |
bb2d6cd7 GK |
11338 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
11339 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 RH |
11340 | && code == BFD_RELOC_16_PCREL_S2 |
11341 | && mips_pic != EMBEDDED_PIC) | |
11342 | reloc->howto = NULL; | |
11343 | else | |
11344 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
11345 | ||
11346 | if (reloc->howto == NULL) | |
11347 | { | |
11348 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11349 | _("Can not represent %s relocation in this object file format"), | |
11350 | bfd_get_reloc_code_name (code)); | |
11351 | retval[0] = NULL; | |
11352 | } | |
11353 | ||
11354 | return retval; | |
11355 | } | |
11356 | ||
11357 | /* Relax a machine dependent frag. This returns the amount by which | |
11358 | the current size of the frag should change. */ | |
11359 | ||
11360 | int | |
11361 | mips_relax_frag (fragp, stretch) | |
11362 | fragS *fragp; | |
11363 | long stretch; | |
11364 | { | |
11365 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
11366 | return 0; | |
11367 | ||
11368 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
11369 | { | |
11370 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11371 | return 0; | |
11372 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
11373 | return 2; | |
11374 | } | |
11375 | else | |
11376 | { | |
11377 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11378 | return 0; | |
11379 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
11380 | return -2; | |
11381 | } | |
11382 | ||
11383 | return 0; | |
11384 | } | |
11385 | ||
11386 | /* Convert a machine dependent frag. */ | |
11387 | ||
11388 | void | |
11389 | md_convert_frag (abfd, asec, fragp) | |
43841e91 | 11390 | bfd *abfd ATTRIBUTE_UNUSED; |
252b5132 RH |
11391 | segT asec; |
11392 | fragS *fragp; | |
11393 | { | |
11394 | int old, new; | |
11395 | char *fixptr; | |
11396 | ||
11397 | if (RELAX_MIPS16_P (fragp->fr_subtype)) | |
11398 | { | |
11399 | int type; | |
11400 | register const struct mips16_immed_operand *op; | |
11401 | boolean small, ext; | |
11402 | offsetT val; | |
11403 | bfd_byte *buf; | |
11404 | unsigned long insn; | |
11405 | boolean use_extend; | |
11406 | unsigned short extend; | |
11407 | ||
11408 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
11409 | op = mips16_immed_operands; | |
11410 | while (op->type != type) | |
11411 | ++op; | |
11412 | ||
11413 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11414 | { | |
11415 | small = false; | |
11416 | ext = true; | |
11417 | } | |
11418 | else | |
11419 | { | |
11420 | small = true; | |
11421 | ext = false; | |
11422 | } | |
11423 | ||
11424 | resolve_symbol_value (fragp->fr_symbol, 1); | |
11425 | val = S_GET_VALUE (fragp->fr_symbol); | |
11426 | if (op->pcrel) | |
11427 | { | |
11428 | addressT addr; | |
11429 | ||
11430 | addr = fragp->fr_address + fragp->fr_fix; | |
11431 | ||
11432 | /* The rules for the base address of a PC relative reloc are | |
11433 | complicated; see mips16_extended_frag. */ | |
11434 | if (type == 'p' || type == 'q') | |
11435 | { | |
11436 | addr += 2; | |
11437 | if (ext) | |
11438 | addr += 2; | |
11439 | /* Ignore the low bit in the target, since it will be | |
11440 | set for a text label. */ | |
11441 | if ((val & 1) != 0) | |
11442 | --val; | |
11443 | } | |
11444 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
11445 | addr -= 4; | |
11446 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
11447 | addr -= 2; | |
11448 | ||
11449 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
11450 | val -= addr; | |
11451 | ||
11452 | /* Make sure the section winds up with the alignment we have | |
11453 | assumed. */ | |
11454 | if (op->shift > 0) | |
11455 | record_alignment (asec, op->shift); | |
11456 | } | |
11457 | ||
11458 | if (ext | |
11459 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
11460 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
11461 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
11462 | _("extended instruction in delay slot")); | |
11463 | ||
11464 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
11465 | ||
11466 | if (target_big_endian) | |
11467 | insn = bfd_getb16 (buf); | |
11468 | else | |
11469 | insn = bfd_getl16 (buf); | |
11470 | ||
11471 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
11472 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
11473 | small, ext, &insn, &use_extend, &extend); | |
11474 | ||
11475 | if (use_extend) | |
11476 | { | |
11477 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
11478 | fragp->fr_fix += 2; | |
11479 | buf += 2; | |
11480 | } | |
11481 | ||
11482 | md_number_to_chars (buf, insn, 2); | |
11483 | fragp->fr_fix += 2; | |
11484 | buf += 2; | |
11485 | } | |
11486 | else | |
11487 | { | |
11488 | if (fragp->fr_opcode == NULL) | |
11489 | return; | |
11490 | ||
11491 | old = RELAX_OLD (fragp->fr_subtype); | |
11492 | new = RELAX_NEW (fragp->fr_subtype); | |
11493 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
11494 | ||
11495 | if (new > 0) | |
11496 | memcpy (fixptr - old, fixptr, new); | |
11497 | ||
11498 | fragp->fr_fix += new - old; | |
11499 | } | |
11500 | } | |
11501 | ||
11502 | #ifdef OBJ_ELF | |
11503 | ||
11504 | /* This function is called after the relocs have been generated. | |
11505 | We've been storing mips16 text labels as odd. Here we convert them | |
11506 | back to even for the convenience of the debugger. */ | |
11507 | ||
11508 | void | |
11509 | mips_frob_file_after_relocs () | |
11510 | { | |
11511 | asymbol **syms; | |
11512 | unsigned int count, i; | |
11513 | ||
11514 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
11515 | return; | |
11516 | ||
11517 | syms = bfd_get_outsymbols (stdoutput); | |
11518 | count = bfd_get_symcount (stdoutput); | |
11519 | for (i = 0; i < count; i++, syms++) | |
11520 | { | |
11521 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
11522 | && ((*syms)->value & 1) != 0) | |
11523 | { | |
11524 | (*syms)->value &= ~1; | |
11525 | /* If the symbol has an odd size, it was probably computed | |
11526 | incorrectly, so adjust that as well. */ | |
11527 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
11528 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
11529 | } | |
11530 | } | |
11531 | } | |
11532 | ||
11533 | #endif | |
11534 | ||
11535 | /* This function is called whenever a label is defined. It is used | |
11536 | when handling branch delays; if a branch has a label, we assume we | |
11537 | can not move it. */ | |
11538 | ||
11539 | void | |
11540 | mips_define_label (sym) | |
11541 | symbolS *sym; | |
11542 | { | |
11543 | struct insn_label_list *l; | |
11544 | ||
11545 | if (free_insn_labels == NULL) | |
11546 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
11547 | else | |
11548 | { | |
11549 | l = free_insn_labels; | |
11550 | free_insn_labels = l->next; | |
11551 | } | |
11552 | ||
11553 | l->label = sym; | |
11554 | l->next = insn_labels; | |
11555 | insn_labels = l; | |
11556 | } | |
11557 | \f | |
11558 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11559 | ||
11560 | /* Some special processing for a MIPS ELF file. */ | |
11561 | ||
11562 | void | |
11563 | mips_elf_final_processing () | |
11564 | { | |
11565 | /* Write out the register information. */ | |
11566 | if (! mips_64) | |
11567 | { | |
11568 | Elf32_RegInfo s; | |
11569 | ||
11570 | s.ri_gprmask = mips_gprmask; | |
11571 | s.ri_cprmask[0] = mips_cprmask[0]; | |
11572 | s.ri_cprmask[1] = mips_cprmask[1]; | |
11573 | s.ri_cprmask[2] = mips_cprmask[2]; | |
11574 | s.ri_cprmask[3] = mips_cprmask[3]; | |
11575 | /* The gp_value field is set by the MIPS ELF backend. */ | |
11576 | ||
11577 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
11578 | ((Elf32_External_RegInfo *) | |
11579 | mips_regmask_frag)); | |
11580 | } | |
11581 | else | |
11582 | { | |
11583 | Elf64_Internal_RegInfo s; | |
11584 | ||
11585 | s.ri_gprmask = mips_gprmask; | |
11586 | s.ri_pad = 0; | |
11587 | s.ri_cprmask[0] = mips_cprmask[0]; | |
11588 | s.ri_cprmask[1] = mips_cprmask[1]; | |
11589 | s.ri_cprmask[2] = mips_cprmask[2]; | |
11590 | s.ri_cprmask[3] = mips_cprmask[3]; | |
11591 | /* The gp_value field is set by the MIPS ELF backend. */ | |
11592 | ||
11593 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
11594 | ((Elf64_External_RegInfo *) | |
11595 | mips_regmask_frag)); | |
11596 | } | |
11597 | ||
11598 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
11599 | sort of BFD interface for this. */ | |
11600 | if (mips_any_noreorder) | |
11601 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
11602 | if (mips_pic != NO_PIC) | |
11603 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; | |
11604 | ||
11605 | /* Set the MIPS ELF ABI flags. */ | |
11606 | if (mips_abi_string == 0) | |
11607 | ; | |
11608 | else if (strcmp (mips_abi_string,"32") == 0) | |
11609 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; | |
11610 | else if (strcmp (mips_abi_string,"o64") == 0) | |
11611 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; | |
11612 | else if (strcmp (mips_abi_string,"eabi") == 0) | |
11613 | { | |
11614 | if (mips_eabi64) | |
11615 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; | |
11616 | else | |
11617 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
11618 | } | |
11619 | ||
11620 | if (mips_32bitmode) | |
11621 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
11622 | } | |
11623 | ||
11624 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
11625 | \f | |
11626 | typedef struct proc | |
11627 | { | |
49309057 | 11628 | symbolS *isym; |
252b5132 RH |
11629 | unsigned long reg_mask; |
11630 | unsigned long reg_offset; | |
11631 | unsigned long fpreg_mask; | |
11632 | unsigned long fpreg_offset; | |
11633 | unsigned long frame_offset; | |
11634 | unsigned long frame_reg; | |
11635 | unsigned long pc_reg; | |
11636 | } | |
11637 | procS; | |
11638 | ||
11639 | static procS cur_proc; | |
11640 | static procS *cur_proc_ptr; | |
11641 | static int numprocs; | |
11642 | ||
a19d8eb0 CP |
11643 | /* When we align code in the .text section of mips16, use the correct two |
11644 | byte nop pattern of 0x6500 (move $0,$0) */ | |
11645 | ||
11646 | int | |
11647 | mips_do_align (n, fill, len, max) | |
11648 | int n; | |
11649 | const char *fill; | |
43841e91 | 11650 | int len ATTRIBUTE_UNUSED; |
a19d8eb0 CP |
11651 | int max; |
11652 | { | |
11653 | if (fill == NULL | |
11654 | && subseg_text_p (now_seg) | |
11655 | && n > 1 | |
11656 | && mips_opts.mips16) | |
11657 | { | |
11658 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
11659 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
11660 | ||
11661 | frag_align (1, 0, 0); | |
11662 | ||
11663 | if (target_big_endian) | |
11664 | frag_align_pattern (n, be_nop, 2, max); | |
11665 | else | |
11666 | frag_align_pattern (n, le_nop, 2, max); | |
11667 | return 1; | |
11668 | } | |
11669 | ||
11670 | return 0; | |
11671 | } | |
11672 | ||
252b5132 RH |
11673 | static void |
11674 | md_obj_begin () | |
11675 | { | |
11676 | } | |
11677 | ||
11678 | static void | |
11679 | md_obj_end () | |
11680 | { | |
11681 | /* check for premature end, nesting errors, etc */ | |
11682 | if (cur_proc_ptr) | |
11683 | as_warn (_("missing `.end' at end of assembly")); | |
11684 | } | |
11685 | ||
11686 | static long | |
11687 | get_number () | |
11688 | { | |
11689 | int negative = 0; | |
11690 | long val = 0; | |
11691 | ||
11692 | if (*input_line_pointer == '-') | |
11693 | { | |
11694 | ++input_line_pointer; | |
11695 | negative = 1; | |
11696 | } | |
d9a62219 | 11697 | if (!isdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11698 | as_bad (_("Expected simple number.")); |
11699 | if (input_line_pointer[0] == '0') | |
11700 | { | |
11701 | if (input_line_pointer[1] == 'x') | |
11702 | { | |
11703 | input_line_pointer += 2; | |
d9a62219 | 11704 | while (isxdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11705 | { |
11706 | val <<= 4; | |
11707 | val |= hex_value (*input_line_pointer++); | |
11708 | } | |
11709 | return negative ? -val : val; | |
11710 | } | |
11711 | else | |
11712 | { | |
11713 | ++input_line_pointer; | |
d9a62219 | 11714 | while (isdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11715 | { |
11716 | val <<= 3; | |
11717 | val |= *input_line_pointer++ - '0'; | |
11718 | } | |
11719 | return negative ? -val : val; | |
11720 | } | |
11721 | } | |
d9a62219 | 11722 | if (!isdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11723 | { |
11724 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
11725 | *input_line_pointer, *input_line_pointer); | |
11726 | as_warn (_("Invalid number")); | |
11727 | return -1; | |
11728 | } | |
d9a62219 | 11729 | while (isdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11730 | { |
11731 | val *= 10; | |
11732 | val += *input_line_pointer++ - '0'; | |
11733 | } | |
11734 | return negative ? -val : val; | |
11735 | } | |
11736 | ||
11737 | /* The .file directive; just like the usual .file directive, but there | |
11738 | is an initial number which is the ECOFF file index. */ | |
11739 | ||
11740 | static void | |
11741 | s_file (x) | |
43841e91 | 11742 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11743 | { |
11744 | int line; | |
11745 | ||
11746 | line = get_number (); | |
11747 | s_app_file (0); | |
11748 | } | |
11749 | ||
11750 | ||
11751 | /* The .end directive. */ | |
11752 | ||
11753 | static void | |
11754 | s_mips_end (x) | |
43841e91 | 11755 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11756 | { |
11757 | symbolS *p; | |
11758 | int maybe_text; | |
11759 | ||
11760 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
11761 | { | |
11762 | p = get_symbol (); | |
11763 | demand_empty_rest_of_line (); | |
11764 | } | |
11765 | else | |
11766 | p = NULL; | |
11767 | ||
11768 | #ifdef BFD_ASSEMBLER | |
11769 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
11770 | maybe_text = 1; | |
11771 | else | |
11772 | maybe_text = 0; | |
11773 | #else | |
11774 | if (now_seg != data_section && now_seg != bss_section) | |
11775 | maybe_text = 1; | |
11776 | else | |
11777 | maybe_text = 0; | |
11778 | #endif | |
11779 | ||
11780 | if (!maybe_text) | |
11781 | as_warn (_(".end not in text section")); | |
11782 | ||
11783 | if (!cur_proc_ptr) | |
11784 | { | |
11785 | as_warn (_(".end directive without a preceding .ent directive.")); | |
11786 | demand_empty_rest_of_line (); | |
11787 | return; | |
11788 | } | |
11789 | ||
11790 | if (p != NULL) | |
11791 | { | |
11792 | assert (S_GET_NAME (p)); | |
11793 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
11794 | as_warn (_(".end symbol does not match .ent symbol.")); | |
11795 | } | |
11796 | else | |
11797 | as_warn (_(".end directive missing or unknown symbol")); | |
11798 | ||
11799 | #ifdef MIPS_STABS_ELF | |
11800 | { | |
11801 | segT saved_seg = now_seg; | |
11802 | subsegT saved_subseg = now_subseg; | |
11803 | fragS *saved_frag = frag_now; | |
11804 | valueT dot; | |
11805 | segT seg; | |
11806 | expressionS exp; | |
11807 | char *fragp; | |
11808 | ||
11809 | dot = frag_now_fix (); | |
11810 | ||
11811 | #ifdef md_flush_pending_output | |
11812 | md_flush_pending_output (); | |
11813 | #endif | |
11814 | ||
11815 | assert (pdr_seg); | |
11816 | subseg_set (pdr_seg, 0); | |
11817 | ||
11818 | /* Write the symbol */ | |
11819 | exp.X_op = O_symbol; | |
11820 | exp.X_add_symbol = p; | |
11821 | exp.X_add_number = 0; | |
11822 | emit_expr (&exp, 4); | |
11823 | ||
11824 | fragp = frag_more (7*4); | |
11825 | ||
11826 | md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4); | |
11827 | md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4); | |
11828 | md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4); | |
11829 | md_number_to_chars (fragp +12, (valueT) cur_proc_ptr->fpreg_offset, 4); | |
11830 | md_number_to_chars (fragp +16, (valueT) cur_proc_ptr->frame_offset, 4); | |
11831 | md_number_to_chars (fragp +20, (valueT) cur_proc_ptr->frame_reg, 4); | |
11832 | md_number_to_chars (fragp +24, (valueT) cur_proc_ptr->pc_reg, 4); | |
11833 | ||
11834 | subseg_set (saved_seg, saved_subseg); | |
11835 | } | |
11836 | #endif | |
11837 | ||
11838 | cur_proc_ptr = NULL; | |
11839 | } | |
11840 | ||
11841 | /* The .aent and .ent directives. */ | |
11842 | ||
11843 | static void | |
11844 | s_mips_ent (aent) | |
11845 | int aent; | |
11846 | { | |
11847 | int number = 0; | |
11848 | symbolS *symbolP; | |
11849 | int maybe_text; | |
11850 | ||
11851 | symbolP = get_symbol (); | |
11852 | if (*input_line_pointer == ',') | |
11853 | input_line_pointer++; | |
11854 | SKIP_WHITESPACE (); | |
d9a62219 DE |
11855 | if (isdigit ((unsigned char) *input_line_pointer) |
11856 | || *input_line_pointer == '-') | |
252b5132 RH |
11857 | number = get_number (); |
11858 | ||
11859 | #ifdef BFD_ASSEMBLER | |
11860 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
11861 | maybe_text = 1; | |
11862 | else | |
11863 | maybe_text = 0; | |
11864 | #else | |
11865 | if (now_seg != data_section && now_seg != bss_section) | |
11866 | maybe_text = 1; | |
11867 | else | |
11868 | maybe_text = 0; | |
11869 | #endif | |
11870 | ||
11871 | if (!maybe_text) | |
11872 | as_warn (_(".ent or .aent not in text section.")); | |
11873 | ||
11874 | if (!aent && cur_proc_ptr) | |
11875 | as_warn (_("missing `.end'")); | |
11876 | ||
11877 | if (!aent) | |
11878 | { | |
11879 | cur_proc_ptr = &cur_proc; | |
11880 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
11881 | ||
11882 | cur_proc_ptr->isym = symbolP; | |
11883 | ||
49309057 | 11884 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 RH |
11885 | |
11886 | numprocs++; | |
11887 | } | |
11888 | ||
11889 | demand_empty_rest_of_line (); | |
11890 | } | |
11891 | ||
11892 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
11893 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, | |
11894 | s_mips_frame is used so that we can set the PDR information correctly. | |
11895 | We can't use the ecoff routines because they make reference to the ecoff | |
11896 | symbol table (in the mdebug section). */ | |
11897 | ||
11898 | static void | |
11899 | s_mips_frame (ignore) | |
11900 | int ignore; | |
11901 | { | |
11902 | #ifdef MIPS_STABS_ELF | |
11903 | ||
11904 | long val; | |
11905 | ||
11906 | if (cur_proc_ptr == (procS *) NULL) | |
11907 | { | |
11908 | as_warn (_(".frame outside of .ent")); | |
11909 | demand_empty_rest_of_line (); | |
11910 | return; | |
11911 | } | |
11912 | ||
11913 | cur_proc_ptr->frame_reg = tc_get_register (1); | |
11914 | ||
11915 | SKIP_WHITESPACE (); | |
11916 | if (*input_line_pointer++ != ',' | |
11917 | || get_absolute_expression_and_terminator (&val) != ',') | |
11918 | { | |
11919 | as_warn (_("Bad .frame directive")); | |
11920 | --input_line_pointer; | |
11921 | demand_empty_rest_of_line (); | |
11922 | return; | |
11923 | } | |
11924 | ||
11925 | cur_proc_ptr->frame_offset = val; | |
11926 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
11927 | ||
11928 | demand_empty_rest_of_line (); | |
11929 | #else | |
11930 | s_ignore (ignore); | |
11931 | #endif /* MIPS_STABS_ELF */ | |
11932 | } | |
11933 | ||
11934 | /* The .fmask and .mask directives. If the mdebug section is present | |
11935 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
11936 | embedded targets, s_mips_mask is used so that we can set the PDR | |
11937 | information correctly. We can't use the ecoff routines because they | |
11938 | make reference to the ecoff symbol table (in the mdebug section). */ | |
11939 | ||
11940 | static void | |
11941 | s_mips_mask (reg_type) | |
11942 | char reg_type; | |
11943 | { | |
11944 | #ifdef MIPS_STABS_ELF | |
11945 | long mask, off; | |
11946 | ||
11947 | if (cur_proc_ptr == (procS *) NULL) | |
11948 | { | |
11949 | as_warn (_(".mask/.fmask outside of .ent")); | |
11950 | demand_empty_rest_of_line (); | |
11951 | return; | |
11952 | } | |
11953 | ||
11954 | if (get_absolute_expression_and_terminator (&mask) != ',') | |
11955 | { | |
11956 | as_warn (_("Bad .mask/.fmask directive")); | |
11957 | --input_line_pointer; | |
11958 | demand_empty_rest_of_line (); | |
11959 | return; | |
11960 | } | |
11961 | ||
11962 | off = get_absolute_expression (); | |
11963 | ||
11964 | if (reg_type == 'F') | |
11965 | { | |
11966 | cur_proc_ptr->fpreg_mask = mask; | |
11967 | cur_proc_ptr->fpreg_offset = off; | |
11968 | } | |
11969 | else | |
11970 | { | |
11971 | cur_proc_ptr->reg_mask = mask; | |
11972 | cur_proc_ptr->reg_offset = off; | |
11973 | } | |
11974 | ||
11975 | demand_empty_rest_of_line (); | |
11976 | #else | |
11977 | s_ignore (reg_type); | |
11978 | #endif /* MIPS_STABS_ELF */ | |
11979 | } | |
11980 | ||
11981 | /* The .loc directive. */ | |
11982 | ||
11983 | #if 0 | |
11984 | static void | |
11985 | s_loc (x) | |
11986 | int x; | |
11987 | { | |
11988 | symbolS *symbolP; | |
11989 | int lineno; | |
11990 | int addroff; | |
11991 | ||
11992 | assert (now_seg == text_section); | |
11993 | ||
11994 | lineno = get_number (); | |
11995 | addroff = frag_now_fix (); | |
11996 | ||
11997 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
11998 | S_SET_TYPE (symbolP, N_SLINE); | |
11999 | S_SET_OTHER (symbolP, 0); | |
12000 | S_SET_DESC (symbolP, lineno); | |
12001 | symbolP->sy_segment = now_seg; | |
12002 | } | |
12003 | #endif |