include/opcode/
[deliverable/binutils-gdb.git] / gas / config / tc-mips.c
CommitLineData
252b5132 1/* tc-mips.c -- assemble code for a MIPS chip.
81912461 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
c67a084a
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3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
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5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 Support.
9
10 This file is part of GAS.
11
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
ec2655a6 14 the Free Software Foundation; either version 3, or (at your option)
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15 any later version.
16
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
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24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 02110-1301, USA. */
252b5132
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26
27#include "as.h"
28#include "config.h"
29#include "subsegs.h"
3882b010 30#include "safe-ctype.h"
252b5132 31
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32#include "opcode/mips.h"
33#include "itbl-ops.h"
c5dd6aab 34#include "dwarf2dbg.h"
5862107c 35#include "dw2gencfi.h"
252b5132
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36
37#ifdef DEBUG
38#define DBG(x) printf x
39#else
40#define DBG(x)
41#endif
42
43#ifdef OBJ_MAYBE_ELF
44/* Clean up namespace so we can include obj-elf.h too. */
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45static int mips_output_flavor (void);
46static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
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47#undef OBJ_PROCESS_STAB
48#undef OUTPUT_FLAVOR
49#undef S_GET_ALIGN
50#undef S_GET_SIZE
51#undef S_SET_ALIGN
52#undef S_SET_SIZE
252b5132
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53#undef obj_frob_file
54#undef obj_frob_file_after_relocs
55#undef obj_frob_symbol
56#undef obj_pop_insert
57#undef obj_sec_sym_ok_for_reloc
58#undef OBJ_COPY_SYMBOL_ATTRIBUTES
59
60#include "obj-elf.h"
61/* Fix any of them that we actually care about. */
62#undef OUTPUT_FLAVOR
63#define OUTPUT_FLAVOR mips_output_flavor()
64#endif
65
66#if defined (OBJ_ELF)
67#include "elf/mips.h"
68#endif
69
70#ifndef ECOFF_DEBUGGING
71#define NO_ECOFF_DEBUGGING
72#define ECOFF_DEBUGGING 0
73#endif
74
ecb4347a
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75int mips_flag_mdebug = -1;
76
dcd410fe
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77/* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
80#ifdef TE_IRIX
81int mips_flag_pdr = FALSE;
82#else
83int mips_flag_pdr = TRUE;
84#endif
85
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86#include "ecoff.h"
87
88#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89static char *mips_regmask_frag;
90#endif
91
85b51719 92#define ZERO 0
741fe287 93#define ATREG 1
df58fc94
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94#define S0 16
95#define S7 23
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96#define TREG 24
97#define PIC_CALL_REG 25
98#define KT0 26
99#define KT1 27
100#define GP 28
101#define SP 29
102#define FP 30
103#define RA 31
104
105#define ILLEGAL_REG (32)
106
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107#define AT mips_opts.at
108
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109/* Allow override of standard little-endian ECOFF format. */
110
111#ifndef ECOFF_LITTLE_FORMAT
112#define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
113#endif
114
115extern int target_big_endian;
116
252b5132 117/* The name of the readonly data section. */
4d0d148d 118#define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
252b5132 119 ? ".rdata" \
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120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
121 ? ".rdata" \
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122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 ? ".rodata" \
124 : (abort (), ""))
125
a4e06468
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126/* Ways in which an instruction can be "appended" to the output. */
127enum append_method {
128 /* Just add it normally. */
129 APPEND_ADD,
130
131 /* Add it normally and then add a nop. */
132 APPEND_ADD_WITH_NOP,
133
134 /* Turn an instruction with a delay slot into a "compact" version. */
135 APPEND_ADD_COMPACT,
136
137 /* Insert the instruction before the last one. */
138 APPEND_SWAP
139};
140
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141/* Information about an instruction, including its format, operands
142 and fixups. */
143struct mips_cl_insn
144{
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode *insn_mo;
147
148 /* True if this is a mips16 instruction and if we want the extended
149 form of INSN_MO. */
150 bfd_boolean use_extend;
151
152 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
153 unsigned short extend;
154
155 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
156 a copy of INSN_MO->match with the operands filled in. */
157 unsigned long insn_opcode;
158
159 /* The frag that contains the instruction. */
160 struct frag *frag;
161
162 /* The offset into FRAG of the first instruction byte. */
163 long where;
164
165 /* The relocs associated with the instruction, if any. */
166 fixS *fixp[3];
167
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168 /* True if this entry cannot be moved from its current position. */
169 unsigned int fixed_p : 1;
47e39b9d 170
708587a4 171 /* True if this instruction occurred in a .set noreorder block. */
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172 unsigned int noreorder_p : 1;
173
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174 /* True for mips16 instructions that jump to an absolute address. */
175 unsigned int mips16_absolute_jump_p : 1;
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176
177 /* True if this instruction is complete. */
178 unsigned int complete_p : 1;
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179};
180
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181/* The ABI to use. */
182enum mips_abi_level
183{
184 NO_ABI = 0,
185 O32_ABI,
186 O64_ABI,
187 N32_ABI,
188 N64_ABI,
189 EABI_ABI
190};
191
192/* MIPS ABI we are using for this output file. */
316f5878 193static enum mips_abi_level mips_abi = NO_ABI;
a325df1d 194
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EC
195/* Whether or not we have code that can call pic code. */
196int mips_abicalls = FALSE;
197
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198/* Whether or not we have code which can be put into a shared
199 library. */
200static bfd_boolean mips_in_shared = TRUE;
201
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202/* This is the set of options which may be modified by the .set
203 pseudo-op. We use a struct so that .set push and .set pop are more
204 reliable. */
205
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206struct mips_set_options
207{
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208 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
209 if it has not been initialized. Changed by `.set mipsN', and the
210 -mipsN command line option, and the default CPU. */
211 int isa;
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CD
212 /* Enabled Application Specific Extensions (ASEs). These are set to -1
213 if they have not been initialized. Changed by `.set <asename>', by
214 command line options, and based on the default architecture. */
215 int ase_mips3d;
deec1734 216 int ase_mdmx;
e16bfa71 217 int ase_smartmips;
74cd071d 218 int ase_dsp;
8b082fb1 219 int ase_dspr2;
ef2e4d86 220 int ase_mt;
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221 /* Whether we are assembling for the mips16 processor. 0 if we are
222 not, 1 if we are, and -1 if the value has not been initialized.
223 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
224 -nomips16 command line options, and the default CPU. */
225 int mips16;
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226 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
227 1 if we are, and -1 if the value has not been initialized. Changed
228 by `.set micromips' and `.set nomicromips', and the -mmicromips
229 and -mno-micromips command line options, and the default CPU. */
230 int micromips;
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231 /* Non-zero if we should not reorder instructions. Changed by `.set
232 reorder' and `.set noreorder'. */
233 int noreorder;
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234 /* Non-zero if we should not permit the register designated "assembler
235 temporary" to be used in instructions. The value is the register
236 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
237 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
238 unsigned int at;
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239 /* Non-zero if we should warn when a macro instruction expands into
240 more than one machine instruction. Changed by `.set nomacro' and
241 `.set macro'. */
242 int warn_about_macros;
243 /* Non-zero if we should not move instructions. Changed by `.set
244 move', `.set volatile', `.set nomove', and `.set novolatile'. */
245 int nomove;
246 /* Non-zero if we should not optimize branches by moving the target
247 of the branch into the delay slot. Actually, we don't perform
248 this optimization anyhow. Changed by `.set bopt' and `.set
249 nobopt'. */
250 int nobopt;
251 /* Non-zero if we should not autoextend mips16 instructions.
252 Changed by `.set autoextend' and `.set noautoextend'. */
253 int noautoextend;
a325df1d
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254 /* Restrict general purpose registers and floating point registers
255 to 32 bit. This is initially determined when -mgp32 or -mfp32
256 is passed but can changed if the assembler code uses .set mipsN. */
257 int gp32;
258 int fp32;
fef14a42
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259 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
260 command line option, and the default CPU. */
261 int arch;
aed1a261
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262 /* True if ".set sym32" is in effect. */
263 bfd_boolean sym32;
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AN
264 /* True if floating-point operations are not allowed. Changed by .set
265 softfloat or .set hardfloat, by command line options -msoft-float or
266 -mhard-float. The default is false. */
267 bfd_boolean soft_float;
268
269 /* True if only single-precision floating-point operations are allowed.
270 Changed by .set singlefloat or .set doublefloat, command-line options
271 -msingle-float or -mdouble-float. The default is false. */
272 bfd_boolean single_float;
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273};
274
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275/* This is the struct we use to hold the current set of options. Note
276 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
277 -1 to indicate that they have not been initialized. */
278
a325df1d 279/* True if -mgp32 was passed. */
a8e8e863 280static int file_mips_gp32 = -1;
a325df1d
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281
282/* True if -mfp32 was passed. */
a8e8e863 283static int file_mips_fp32 = -1;
a325df1d 284
037b32b9
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285/* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
286static int file_mips_soft_float = 0;
287
288/* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
289static int file_mips_single_float = 0;
252b5132 290
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291static struct mips_set_options mips_opts =
292{
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293 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
294 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
df58fc94 295 /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0, /* at */ ATREG,
037b32b9
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296 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
297 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
298 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
e7af610e 299};
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300
301/* These variables are filled in with the masks of registers used.
302 The object format code reads them and puts them in the appropriate
303 place. */
304unsigned long mips_gprmask;
305unsigned long mips_cprmask[4];
306
307/* MIPS ISA we are using for this output file. */
e7af610e 308static int file_mips_isa = ISA_UNKNOWN;
252b5132 309
738f4d98 310/* True if any MIPS16 code was produced. */
a4672219
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311static int file_ase_mips16;
312
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313#define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
314 || mips_opts.isa == ISA_MIPS32R2 \
315 || mips_opts.isa == ISA_MIPS64 \
316 || mips_opts.isa == ISA_MIPS64R2)
317
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318/* True if any microMIPS code was produced. */
319static int file_ase_micromips;
320
b12dd2e4
CF
321/* True if we want to create R_MIPS_JALR for jalr $25. */
322#ifdef TE_IRIX
1180b5a4 323#define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
b12dd2e4 324#else
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RS
325/* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
326 because there's no place for any addend, the only acceptable
327 expression is a bare symbol. */
328#define MIPS_JALR_HINT_P(EXPR) \
329 (!HAVE_IN_PLACE_ADDENDS \
330 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
b12dd2e4
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331#endif
332
1f25f5d3
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333/* True if -mips3d was passed or implied by arguments passed on the
334 command line (e.g., by -march). */
335static int file_ase_mips3d;
336
deec1734
CD
337/* True if -mdmx was passed or implied by arguments passed on the
338 command line (e.g., by -march). */
339static int file_ase_mdmx;
340
e16bfa71
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341/* True if -msmartmips was passed or implied by arguments passed on the
342 command line (e.g., by -march). */
343static int file_ase_smartmips;
344
ad3fea08
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345#define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
346 || mips_opts.isa == ISA_MIPS32R2)
e16bfa71 347
74cd071d
CF
348/* True if -mdsp was passed or implied by arguments passed on the
349 command line (e.g., by -march). */
350static int file_ase_dsp;
351
ad3fea08
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352#define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
353 || mips_opts.isa == ISA_MIPS64R2)
354
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355#define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
356
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357/* True if -mdspr2 was passed or implied by arguments passed on the
358 command line (e.g., by -march). */
359static int file_ase_dspr2;
360
361#define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
362 || mips_opts.isa == ISA_MIPS64R2)
363
ef2e4d86
CF
364/* True if -mmt was passed or implied by arguments passed on the
365 command line (e.g., by -march). */
366static int file_ase_mt;
367
ad3fea08
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368#define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
369 || mips_opts.isa == ISA_MIPS64R2)
370
ec68c924 371/* The argument of the -march= flag. The architecture we are assembling. */
fef14a42 372static int file_mips_arch = CPU_UNKNOWN;
316f5878 373static const char *mips_arch_string;
ec68c924
EC
374
375/* The argument of the -mtune= flag. The architecture for which we
376 are optimizing. */
377static int mips_tune = CPU_UNKNOWN;
316f5878 378static const char *mips_tune_string;
ec68c924 379
316f5878 380/* True when generating 32-bit code for a 64-bit processor. */
252b5132
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381static int mips_32bitmode = 0;
382
316f5878
RS
383/* True if the given ABI requires 32-bit registers. */
384#define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
385
386/* Likewise 64-bit registers. */
707bfff6
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387#define ABI_NEEDS_64BIT_REGS(ABI) \
388 ((ABI) == N32_ABI \
389 || (ABI) == N64_ABI \
316f5878
RS
390 || (ABI) == O64_ABI)
391
ad3fea08 392/* Return true if ISA supports 64 bit wide gp registers. */
707bfff6
TS
393#define ISA_HAS_64BIT_REGS(ISA) \
394 ((ISA) == ISA_MIPS3 \
395 || (ISA) == ISA_MIPS4 \
396 || (ISA) == ISA_MIPS5 \
397 || (ISA) == ISA_MIPS64 \
398 || (ISA) == ISA_MIPS64R2)
9ce8a5dd 399
ad3fea08
TS
400/* Return true if ISA supports 64 bit wide float registers. */
401#define ISA_HAS_64BIT_FPRS(ISA) \
402 ((ISA) == ISA_MIPS3 \
403 || (ISA) == ISA_MIPS4 \
404 || (ISA) == ISA_MIPS5 \
405 || (ISA) == ISA_MIPS32R2 \
406 || (ISA) == ISA_MIPS64 \
407 || (ISA) == ISA_MIPS64R2)
408
af7ee8bf
CD
409/* Return true if ISA supports 64-bit right rotate (dror et al.)
410 instructions. */
707bfff6 411#define ISA_HAS_DROR(ISA) \
df58fc94
RS
412 ((ISA) == ISA_MIPS64R2 \
413 || (mips_opts.micromips \
414 && ISA_HAS_64BIT_REGS (ISA)) \
415 )
af7ee8bf
CD
416
417/* Return true if ISA supports 32-bit right rotate (ror et al.)
418 instructions. */
707bfff6
TS
419#define ISA_HAS_ROR(ISA) \
420 ((ISA) == ISA_MIPS32R2 \
421 || (ISA) == ISA_MIPS64R2 \
df58fc94
RS
422 || mips_opts.ase_smartmips \
423 || mips_opts.micromips \
424 )
707bfff6 425
7455baf8
TS
426/* Return true if ISA supports single-precision floats in odd registers. */
427#define ISA_HAS_ODD_SINGLE_FPR(ISA) \
428 ((ISA) == ISA_MIPS32 \
429 || (ISA) == ISA_MIPS32R2 \
430 || (ISA) == ISA_MIPS64 \
431 || (ISA) == ISA_MIPS64R2)
af7ee8bf 432
ad3fea08
TS
433/* Return true if ISA supports move to/from high part of a 64-bit
434 floating-point register. */
435#define ISA_HAS_MXHC1(ISA) \
436 ((ISA) == ISA_MIPS32R2 \
437 || (ISA) == ISA_MIPS64R2)
438
e013f690 439#define HAVE_32BIT_GPRS \
ad3fea08 440 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
ca4e0257 441
e013f690 442#define HAVE_32BIT_FPRS \
ad3fea08 443 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
ca4e0257 444
ad3fea08
TS
445#define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
446#define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
ca4e0257 447
316f5878 448#define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
e013f690 449
316f5878 450#define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
e013f690 451
3b91255e
RS
452/* True if relocations are stored in-place. */
453#define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
454
aed1a261
RS
455/* The ABI-derived address size. */
456#define HAVE_64BIT_ADDRESSES \
457 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
458#define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
e013f690 459
aed1a261
RS
460/* The size of symbolic constants (i.e., expressions of the form
461 "SYMBOL" or "SYMBOL + OFFSET"). */
462#define HAVE_32BIT_SYMBOLS \
463 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
464#define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
ca4e0257 465
b7c7d6c1
TS
466/* Addresses are loaded in different ways, depending on the address size
467 in use. The n32 ABI Documentation also mandates the use of additions
468 with overflow checking, but existing implementations don't follow it. */
f899b4b8 469#define ADDRESS_ADD_INSN \
b7c7d6c1 470 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
f899b4b8
TS
471
472#define ADDRESS_ADDI_INSN \
b7c7d6c1 473 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
f899b4b8
TS
474
475#define ADDRESS_LOAD_INSN \
476 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
477
478#define ADDRESS_STORE_INSN \
479 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
480
a4672219 481/* Return true if the given CPU supports the MIPS16 ASE. */
3396de36
TS
482#define CPU_HAS_MIPS16(cpu) \
483 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
484 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
a4672219 485
2309ddf2 486/* Return true if the given CPU supports the microMIPS ASE. */
df58fc94
RS
487#define CPU_HAS_MICROMIPS(cpu) 0
488
60b63b72
RS
489/* True if CPU has a dror instruction. */
490#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
491
492/* True if CPU has a ror instruction. */
493#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
494
dd3cbb7e
NC
495/* True if CPU has seq/sne and seqi/snei instructions. */
496#define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
497
b19e8a9b
AN
498/* True if CPU does not implement the all the coprocessor insns. For these
499 CPUs only those COP insns are accepted that are explicitly marked to be
500 available on the CPU. ISA membership for COP insns is ignored. */
501#define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
502
c8978940
CD
503/* True if mflo and mfhi can be immediately followed by instructions
504 which write to the HI and LO registers.
505
506 According to MIPS specifications, MIPS ISAs I, II, and III need
507 (at least) two instructions between the reads of HI/LO and
508 instructions which write them, and later ISAs do not. Contradicting
509 the MIPS specifications, some MIPS IV processor user manuals (e.g.
510 the UM for the NEC Vr5000) document needing the instructions between
511 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
512 MIPS64 and later ISAs to have the interlocks, plus any specific
513 earlier-ISA CPUs for which CPU documentation declares that the
514 instructions are really interlocked. */
515#define hilo_interlocks \
516 (mips_opts.isa == ISA_MIPS32 \
517 || mips_opts.isa == ISA_MIPS32R2 \
518 || mips_opts.isa == ISA_MIPS64 \
519 || mips_opts.isa == ISA_MIPS64R2 \
520 || mips_opts.arch == CPU_R4010 \
521 || mips_opts.arch == CPU_R10000 \
522 || mips_opts.arch == CPU_R12000 \
3aa3176b
TS
523 || mips_opts.arch == CPU_R14000 \
524 || mips_opts.arch == CPU_R16000 \
c8978940 525 || mips_opts.arch == CPU_RM7000 \
c8978940 526 || mips_opts.arch == CPU_VR5500 \
df58fc94 527 || mips_opts.micromips \
c8978940 528 )
252b5132
RH
529
530/* Whether the processor uses hardware interlocks to protect reads
81912461
ILT
531 from the GPRs after they are loaded from memory, and thus does not
532 require nops to be inserted. This applies to instructions marked
533 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
df58fc94
RS
534 level I and microMIPS mode instructions are always interlocked. */
535#define gpr_interlocks \
536 (mips_opts.isa != ISA_MIPS1 \
537 || mips_opts.arch == CPU_R3900 \
538 || mips_opts.micromips \
539 )
252b5132 540
81912461
ILT
541/* Whether the processor uses hardware interlocks to avoid delays
542 required by coprocessor instructions, and thus does not require
543 nops to be inserted. This applies to instructions marked
544 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
545 between instructions marked INSN_WRITE_COND_CODE and ones marked
546 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
df58fc94
RS
547 levels I, II, and III and microMIPS mode instructions are always
548 interlocked. */
bdaaa2e1 549/* Itbl support may require additional care here. */
81912461
ILT
550#define cop_interlocks \
551 ((mips_opts.isa != ISA_MIPS1 \
552 && mips_opts.isa != ISA_MIPS2 \
553 && mips_opts.isa != ISA_MIPS3) \
554 || mips_opts.arch == CPU_R4300 \
df58fc94 555 || mips_opts.micromips \
81912461
ILT
556 )
557
558/* Whether the processor uses hardware interlocks to protect reads
559 from coprocessor registers after they are loaded from memory, and
560 thus does not require nops to be inserted. This applies to
561 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
df58fc94
RS
562 requires at MIPS ISA level I and microMIPS mode instructions are
563 always interlocked. */
564#define cop_mem_interlocks \
565 (mips_opts.isa != ISA_MIPS1 \
566 || mips_opts.micromips \
567 )
252b5132 568
6b76fefe
CM
569/* Is this a mfhi or mflo instruction? */
570#define MF_HILO_INSN(PINFO) \
b19e8a9b
AN
571 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
572
573/* Returns true for a (non floating-point) coprocessor instruction. Reading
574 or writing the condition code is only possible on the coprocessors and
575 these insns are not marked with INSN_COP. Thus for these insns use the
a242dc0d 576 condition-code flags. */
b19e8a9b
AN
577#define COP_INSN(PINFO) \
578 (PINFO != INSN_MACRO \
a242dc0d
AN
579 && ((PINFO) & (FP_S | FP_D)) == 0 \
580 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
6b76fefe 581
df58fc94
RS
582/* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
583 has been selected. This implies, in particular, that addresses of text
584 labels have their LSB set. */
585#define HAVE_CODE_COMPRESSION \
586 ((mips_opts.mips16 | mips_opts.micromips) != 0)
587
252b5132
RH
588/* MIPS PIC level. */
589
a161fe53 590enum mips_pic_level mips_pic;
252b5132 591
c9914766 592/* 1 if we should generate 32 bit offsets from the $gp register in
252b5132 593 SVR4_PIC mode. Currently has no meaning in other modes. */
c9914766 594static int mips_big_got = 0;
252b5132
RH
595
596/* 1 if trap instructions should used for overflow rather than break
597 instructions. */
c9914766 598static int mips_trap = 0;
252b5132 599
119d663a 600/* 1 if double width floating point constants should not be constructed
b6ff326e 601 by assembling two single width halves into two single width floating
119d663a
NC
602 point registers which just happen to alias the double width destination
603 register. On some architectures this aliasing can be disabled by a bit
d547a75e 604 in the status register, and the setting of this bit cannot be determined
119d663a
NC
605 automatically at assemble time. */
606static int mips_disable_float_construction;
607
252b5132
RH
608/* Non-zero if any .set noreorder directives were used. */
609
610static int mips_any_noreorder;
611
6b76fefe
CM
612/* Non-zero if nops should be inserted when the register referenced in
613 an mfhi/mflo instruction is read in the next two instructions. */
614static int mips_7000_hilo_fix;
615
02ffd3e4 616/* The size of objects in the small data section. */
156c2f8b 617static unsigned int g_switch_value = 8;
252b5132
RH
618/* Whether the -G option was used. */
619static int g_switch_seen = 0;
620
621#define N_RMASK 0xc4
622#define N_VFP 0xd4
623
624/* If we can determine in advance that GP optimization won't be
625 possible, we can skip the relaxation stuff that tries to produce
626 GP-relative references. This makes delay slot optimization work
627 better.
628
629 This function can only provide a guess, but it seems to work for
fba2b7f9
GK
630 gcc output. It needs to guess right for gcc, otherwise gcc
631 will put what it thinks is a GP-relative instruction in a branch
632 delay slot.
252b5132
RH
633
634 I don't know if a fix is needed for the SVR4_PIC mode. I've only
635 fixed it for the non-PIC mode. KR 95/04/07 */
17a2f251 636static int nopic_need_relax (symbolS *, int);
252b5132
RH
637
638/* handle of the OPCODE hash table */
639static struct hash_control *op_hash = NULL;
640
641/* The opcode hash table we use for the mips16. */
642static struct hash_control *mips16_op_hash = NULL;
643
df58fc94
RS
644/* The opcode hash table we use for the microMIPS ASE. */
645static struct hash_control *micromips_op_hash = NULL;
646
252b5132
RH
647/* This array holds the chars that always start a comment. If the
648 pre-processor is disabled, these aren't very useful */
649const char comment_chars[] = "#";
650
651/* This array holds the chars that only start a comment at the beginning of
652 a line. If the line seems to have the form '# 123 filename'
653 .line and .file directives will appear in the pre-processed output */
654/* Note that input_file.c hand checks for '#' at the beginning of the
655 first line of the input file. This is because the compiler outputs
bdaaa2e1 656 #NO_APP at the beginning of its output. */
252b5132
RH
657/* Also note that C style comments are always supported. */
658const char line_comment_chars[] = "#";
659
bdaaa2e1 660/* This array holds machine specific line separator characters. */
63a0b638 661const char line_separator_chars[] = ";";
252b5132
RH
662
663/* Chars that can be used to separate mant from exp in floating point nums */
664const char EXP_CHARS[] = "eE";
665
666/* Chars that mean this number is a floating point constant */
667/* As in 0f12.456 */
668/* or 0d1.2345e12 */
669const char FLT_CHARS[] = "rRsSfFdDxXpP";
670
671/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
672 changed in read.c . Ideally it shouldn't have to know about it at all,
673 but nothing is ideal around here.
674 */
675
676static char *insn_error;
677
678static int auto_align = 1;
679
680/* When outputting SVR4 PIC code, the assembler needs to know the
681 offset in the stack frame from which to restore the $gp register.
682 This is set by the .cprestore pseudo-op, and saved in this
683 variable. */
684static offsetT mips_cprestore_offset = -1;
685
67c1ffbe 686/* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
6478892d 687 more optimizations, it can use a register value instead of a memory-saved
956cd1d6 688 offset and even an other register than $gp as global pointer. */
6478892d
TS
689static offsetT mips_cpreturn_offset = -1;
690static int mips_cpreturn_register = -1;
691static int mips_gp_register = GP;
def2e0dd 692static int mips_gprel_offset = 0;
6478892d 693
7a621144
DJ
694/* Whether mips_cprestore_offset has been set in the current function
695 (or whether it has already been warned about, if not). */
696static int mips_cprestore_valid = 0;
697
252b5132
RH
698/* This is the register which holds the stack frame, as set by the
699 .frame pseudo-op. This is needed to implement .cprestore. */
700static int mips_frame_reg = SP;
701
7a621144
DJ
702/* Whether mips_frame_reg has been set in the current function
703 (or whether it has already been warned about, if not). */
704static int mips_frame_reg_valid = 0;
705
252b5132
RH
706/* To output NOP instructions correctly, we need to keep information
707 about the previous two instructions. */
708
709/* Whether we are optimizing. The default value of 2 means to remove
710 unneeded NOPs and swap branch instructions when possible. A value
711 of 1 means to not swap branches. A value of 0 means to always
712 insert NOPs. */
713static int mips_optimize = 2;
714
715/* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
716 equivalent to seeing no -g option at all. */
717static int mips_debug = 0;
718
7d8e00cf
RS
719/* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
720#define MAX_VR4130_NOPS 4
721
722/* The maximum number of NOPs needed to fill delay slots. */
723#define MAX_DELAY_NOPS 2
724
725/* The maximum number of NOPs needed for any purpose. */
726#define MAX_NOPS 4
71400594
RS
727
728/* A list of previous instructions, with index 0 being the most recent.
729 We need to look back MAX_NOPS instructions when filling delay slots
730 or working around processor errata. We need to look back one
731 instruction further if we're thinking about using history[0] to
732 fill a branch delay slot. */
733static struct mips_cl_insn history[1 + MAX_NOPS];
252b5132 734
1e915849 735/* Nop instructions used by emit_nop. */
df58fc94
RS
736static struct mips_cl_insn nop_insn;
737static struct mips_cl_insn mips16_nop_insn;
738static struct mips_cl_insn micromips_nop16_insn;
739static struct mips_cl_insn micromips_nop32_insn;
1e915849
RS
740
741/* The appropriate nop for the current mode. */
df58fc94
RS
742#define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
743 : (mips_opts.micromips ? &micromips_nop16_insn : &nop_insn))
744
745/* The size of NOP_INSN in bytes. */
746#define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
252b5132 747
252b5132
RH
748/* If this is set, it points to a frag holding nop instructions which
749 were inserted before the start of a noreorder section. If those
750 nops turn out to be unnecessary, the size of the frag can be
751 decreased. */
752static fragS *prev_nop_frag;
753
754/* The number of nop instructions we created in prev_nop_frag. */
755static int prev_nop_frag_holds;
756
757/* The number of nop instructions that we know we need in
bdaaa2e1 758 prev_nop_frag. */
252b5132
RH
759static int prev_nop_frag_required;
760
761/* The number of instructions we've seen since prev_nop_frag. */
762static int prev_nop_frag_since;
763
764/* For ECOFF and ELF, relocations against symbols are done in two
765 parts, with a HI relocation and a LO relocation. Each relocation
766 has only 16 bits of space to store an addend. This means that in
767 order for the linker to handle carries correctly, it must be able
768 to locate both the HI and the LO relocation. This means that the
769 relocations must appear in order in the relocation table.
770
771 In order to implement this, we keep track of each unmatched HI
772 relocation. We then sort them so that they immediately precede the
bdaaa2e1 773 corresponding LO relocation. */
252b5132 774
e972090a
NC
775struct mips_hi_fixup
776{
252b5132
RH
777 /* Next HI fixup. */
778 struct mips_hi_fixup *next;
779 /* This fixup. */
780 fixS *fixp;
781 /* The section this fixup is in. */
782 segT seg;
783};
784
785/* The list of unmatched HI relocs. */
786
787static struct mips_hi_fixup *mips_hi_fixup_list;
788
64bdfcaf
RS
789/* The frag containing the last explicit relocation operator.
790 Null if explicit relocations have not been used. */
791
792static fragS *prev_reloc_op_frag;
793
252b5132
RH
794/* Map normal MIPS register numbers to mips16 register numbers. */
795
796#define X ILLEGAL_REG
e972090a
NC
797static const int mips32_to_16_reg_map[] =
798{
252b5132
RH
799 X, X, 2, 3, 4, 5, 6, 7,
800 X, X, X, X, X, X, X, X,
801 0, 1, X, X, X, X, X, X,
802 X, X, X, X, X, X, X, X
803};
804#undef X
805
806/* Map mips16 register numbers to normal MIPS register numbers. */
807
e972090a
NC
808static const unsigned int mips16_to_32_reg_map[] =
809{
252b5132
RH
810 16, 17, 2, 3, 4, 5, 6, 7
811};
60b63b72 812
df58fc94
RS
813/* Map normal MIPS register numbers to microMIPS register numbers. */
814
815#define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
816#define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
817#define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
818#define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
819#define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
820#define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
821#define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
822
823#define X ILLEGAL_REG
824/* reg type h: 4, 5, 6. */
825static const int mips32_to_micromips_reg_h_map[] =
826{
827 X, X, X, X, 4, 5, 6, X,
828 X, X, X, X, X, X, X, X,
829 X, X, X, X, X, X, X, X,
830 X, X, X, X, X, X, X, X
831};
832
833/* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
834static const int mips32_to_micromips_reg_m_map[] =
835{
836 0, X, 2, 3, X, X, X, X,
837 X, X, X, X, X, X, X, X,
838 4, 1, 5, 6, 7, X, X, X,
839 X, X, X, X, X, X, X, X
840};
841
842/* reg type q: 0, 2-7. 17. */
843static const int mips32_to_micromips_reg_q_map[] =
844{
845 0, X, 2, 3, 4, 5, 6, 7,
846 X, X, X, X, X, X, X, X,
847 X, 1, X, X, X, X, X, X,
848 X, X, X, X, X, X, X, X
849};
850
851#define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
852#undef X
853
854/* Map microMIPS register numbers to normal MIPS register numbers. */
855
856#define micromips_to_32_reg_b_map mips16_to_32_reg_map
857#define micromips_to_32_reg_c_map mips16_to_32_reg_map
858#define micromips_to_32_reg_d_map mips16_to_32_reg_map
859#define micromips_to_32_reg_e_map mips16_to_32_reg_map
860#define micromips_to_32_reg_f_map mips16_to_32_reg_map
861#define micromips_to_32_reg_g_map mips16_to_32_reg_map
862
863/* The microMIPS registers with type h. */
864static const unsigned int micromips_to_32_reg_h_map[] =
865{
866 5, 5, 6, 4, 4, 4, 4, 4
867};
868
869/* The microMIPS registers with type i. */
870static const unsigned int micromips_to_32_reg_i_map[] =
871{
872 6, 7, 7, 21, 22, 5, 6, 7
873};
874
875#define micromips_to_32_reg_l_map mips16_to_32_reg_map
876
877/* The microMIPS registers with type m. */
878static const unsigned int micromips_to_32_reg_m_map[] =
879{
880 0, 17, 2, 3, 16, 18, 19, 20
881};
882
883#define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
884
885/* The microMIPS registers with type q. */
886static const unsigned int micromips_to_32_reg_q_map[] =
887{
888 0, 17, 2, 3, 4, 5, 6, 7
889};
890
891/* microMIPS imm type B. */
892static const int micromips_imm_b_map[] =
893{
894 1, 4, 8, 12, 16, 20, 24, -1
895};
896
897/* microMIPS imm type C. */
898static const int micromips_imm_c_map[] =
899{
900 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
901};
902
71400594
RS
903/* Classifies the kind of instructions we're interested in when
904 implementing -mfix-vr4120. */
c67a084a
NC
905enum fix_vr4120_class
906{
71400594
RS
907 FIX_VR4120_MACC,
908 FIX_VR4120_DMACC,
909 FIX_VR4120_MULT,
910 FIX_VR4120_DMULT,
911 FIX_VR4120_DIV,
912 FIX_VR4120_MTHILO,
913 NUM_FIX_VR4120_CLASSES
914};
915
c67a084a
NC
916/* ...likewise -mfix-loongson2f-jump. */
917static bfd_boolean mips_fix_loongson2f_jump;
918
919/* ...likewise -mfix-loongson2f-nop. */
920static bfd_boolean mips_fix_loongson2f_nop;
921
922/* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
923static bfd_boolean mips_fix_loongson2f;
924
71400594
RS
925/* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
926 there must be at least one other instruction between an instruction
927 of type X and an instruction of type Y. */
928static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
929
930/* True if -mfix-vr4120 is in force. */
d766e8ec 931static int mips_fix_vr4120;
4a6a3df4 932
7d8e00cf
RS
933/* ...likewise -mfix-vr4130. */
934static int mips_fix_vr4130;
935
6a32d874
CM
936/* ...likewise -mfix-24k. */
937static int mips_fix_24k;
938
d954098f
DD
939/* ...likewise -mfix-cn63xxp1 */
940static bfd_boolean mips_fix_cn63xxp1;
941
4a6a3df4
AO
942/* We don't relax branches by default, since this causes us to expand
943 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
944 fail to compute the offset before expanding the macro to the most
945 efficient expansion. */
946
947static int mips_relax_branch;
252b5132 948\f
4d7206a2
RS
949/* The expansion of many macros depends on the type of symbol that
950 they refer to. For example, when generating position-dependent code,
951 a macro that refers to a symbol may have two different expansions,
952 one which uses GP-relative addresses and one which uses absolute
953 addresses. When generating SVR4-style PIC, a macro may have
954 different expansions for local and global symbols.
955
956 We handle these situations by generating both sequences and putting
957 them in variant frags. In position-dependent code, the first sequence
958 will be the GP-relative one and the second sequence will be the
959 absolute one. In SVR4 PIC, the first sequence will be for global
960 symbols and the second will be for local symbols.
961
584892a6
RS
962 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
963 SECOND are the lengths of the two sequences in bytes. These fields
964 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
965 the subtype has the following flags:
4d7206a2 966
584892a6
RS
967 RELAX_USE_SECOND
968 Set if it has been decided that we should use the second
969 sequence instead of the first.
970
971 RELAX_SECOND_LONGER
972 Set in the first variant frag if the macro's second implementation
973 is longer than its first. This refers to the macro as a whole,
974 not an individual relaxation.
975
976 RELAX_NOMACRO
977 Set in the first variant frag if the macro appeared in a .set nomacro
978 block and if one alternative requires a warning but the other does not.
979
980 RELAX_DELAY_SLOT
981 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
982 delay slot.
4d7206a2 983
df58fc94
RS
984 RELAX_DELAY_SLOT_16BIT
985 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
986 16-bit instruction.
987
988 RELAX_DELAY_SLOT_SIZE_FIRST
989 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
990 the macro is of the wrong size for the branch delay slot.
991
992 RELAX_DELAY_SLOT_SIZE_SECOND
993 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
994 the macro is of the wrong size for the branch delay slot.
995
4d7206a2
RS
996 The frag's "opcode" points to the first fixup for relaxable code.
997
998 Relaxable macros are generated using a sequence such as:
999
1000 relax_start (SYMBOL);
1001 ... generate first expansion ...
1002 relax_switch ();
1003 ... generate second expansion ...
1004 relax_end ();
1005
1006 The code and fixups for the unwanted alternative are discarded
1007 by md_convert_frag. */
584892a6 1008#define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
4d7206a2 1009
584892a6
RS
1010#define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1011#define RELAX_SECOND(X) ((X) & 0xff)
1012#define RELAX_USE_SECOND 0x10000
1013#define RELAX_SECOND_LONGER 0x20000
1014#define RELAX_NOMACRO 0x40000
1015#define RELAX_DELAY_SLOT 0x80000
df58fc94
RS
1016#define RELAX_DELAY_SLOT_16BIT 0x100000
1017#define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1018#define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
252b5132 1019
4a6a3df4
AO
1020/* Branch without likely bit. If label is out of range, we turn:
1021
1022 beq reg1, reg2, label
1023 delay slot
1024
1025 into
1026
1027 bne reg1, reg2, 0f
1028 nop
1029 j label
1030 0: delay slot
1031
1032 with the following opcode replacements:
1033
1034 beq <-> bne
1035 blez <-> bgtz
1036 bltz <-> bgez
1037 bc1f <-> bc1t
1038
1039 bltzal <-> bgezal (with jal label instead of j label)
1040
1041 Even though keeping the delay slot instruction in the delay slot of
1042 the branch would be more efficient, it would be very tricky to do
1043 correctly, because we'd have to introduce a variable frag *after*
1044 the delay slot instruction, and expand that instead. Let's do it
1045 the easy way for now, even if the branch-not-taken case now costs
1046 one additional instruction. Out-of-range branches are not supposed
1047 to be common, anyway.
1048
1049 Branch likely. If label is out of range, we turn:
1050
1051 beql reg1, reg2, label
1052 delay slot (annulled if branch not taken)
1053
1054 into
1055
1056 beql reg1, reg2, 1f
1057 nop
1058 beql $0, $0, 2f
1059 nop
1060 1: j[al] label
1061 delay slot (executed only if branch taken)
1062 2:
1063
1064 It would be possible to generate a shorter sequence by losing the
1065 likely bit, generating something like:
b34976b6 1066
4a6a3df4
AO
1067 bne reg1, reg2, 0f
1068 nop
1069 j[al] label
1070 delay slot (executed only if branch taken)
1071 0:
1072
1073 beql -> bne
1074 bnel -> beq
1075 blezl -> bgtz
1076 bgtzl -> blez
1077 bltzl -> bgez
1078 bgezl -> bltz
1079 bc1fl -> bc1t
1080 bc1tl -> bc1f
1081
1082 bltzall -> bgezal (with jal label instead of j label)
1083 bgezall -> bltzal (ditto)
1084
1085
1086 but it's not clear that it would actually improve performance. */
66b3e8da
MR
1087#define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1088 ((relax_substateT) \
1089 (0xc0000000 \
1090 | ((at) & 0x1f) \
1091 | ((toofar) ? 0x20 : 0) \
1092 | ((link) ? 0x40 : 0) \
1093 | ((likely) ? 0x80 : 0) \
1094 | ((uncond) ? 0x100 : 0)))
4a6a3df4 1095#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
66b3e8da
MR
1096#define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1097#define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1098#define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1099#define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1100#define RELAX_BRANCH_AT(i) ((i) & 0x1f)
4a6a3df4 1101
252b5132
RH
1102/* For mips16 code, we use an entirely different form of relaxation.
1103 mips16 supports two versions of most instructions which take
1104 immediate values: a small one which takes some small value, and a
1105 larger one which takes a 16 bit value. Since branches also follow
1106 this pattern, relaxing these values is required.
1107
1108 We can assemble both mips16 and normal MIPS code in a single
1109 object. Therefore, we need to support this type of relaxation at
1110 the same time that we support the relaxation described above. We
1111 use the high bit of the subtype field to distinguish these cases.
1112
1113 The information we store for this type of relaxation is the
1114 argument code found in the opcode file for this relocation, whether
1115 the user explicitly requested a small or extended form, and whether
1116 the relocation is in a jump or jal delay slot. That tells us the
1117 size of the value, and how it should be stored. We also store
1118 whether the fragment is considered to be extended or not. We also
1119 store whether this is known to be a branch to a different section,
1120 whether we have tried to relax this frag yet, and whether we have
1121 ever extended a PC relative fragment because of a shift count. */
1122#define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1123 (0x80000000 \
1124 | ((type) & 0xff) \
1125 | ((small) ? 0x100 : 0) \
1126 | ((ext) ? 0x200 : 0) \
1127 | ((dslot) ? 0x400 : 0) \
1128 | ((jal_dslot) ? 0x800 : 0))
4a6a3df4 1129#define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
252b5132
RH
1130#define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1131#define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1132#define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1133#define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1134#define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1135#define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1136#define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1137#define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1138#define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1139#define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1140#define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
885add95 1141
df58fc94
RS
1142/* For microMIPS code, we use relaxation similar to one we use for
1143 MIPS16 code. Some instructions that take immediate values support
1144 two encodings: a small one which takes some small value, and a
1145 larger one which takes a 16 bit value. As some branches also follow
1146 this pattern, relaxing these values is required.
1147
1148 We can assemble both microMIPS and normal MIPS code in a single
1149 object. Therefore, we need to support this type of relaxation at
1150 the same time that we support the relaxation described above. We
1151 use one of the high bits of the subtype field to distinguish these
1152 cases.
1153
1154 The information we store for this type of relaxation is the argument
1155 code found in the opcode file for this relocation, the register
1156 selected as the assembler temporary, whether the user explicitly
1157 requested a 16-bit form, whether the branch is unconditional, whether
1158 it is compact, whether it stores the link address implicitly in $ra,
1159 whether relaxation of out-of-range 32-bit branches to a sequence of
1160 instructions is enabled, and whether the displacement of a branch is
1161 too large to fit as an immediate argument of a 16-bit and a 32-bit
1162 branch, respectively. */
1163#define RELAX_MICROMIPS_ENCODE(type, at, u16bit, uncond, compact, link, \
1164 relax32, toofar16, toofar32) \
1165 (0x40000000 \
1166 | ((type) & 0xff) \
1167 | (((at) & 0x1f) << 8) \
1168 | ((u16bit) ? 0x2000 : 0) \
1169 | ((uncond) ? 0x4000 : 0) \
1170 | ((compact) ? 0x8000 : 0) \
1171 | ((link) ? 0x10000 : 0) \
1172 | ((relax32) ? 0x20000 : 0) \
1173 | ((toofar16) ? 0x40000 : 0) \
1174 | ((toofar32) ? 0x80000 : 0))
1175#define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1176#define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1177#define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1178#define RELAX_MICROMIPS_U16BIT(i) (((i) & 0x2000) != 0)
1179#define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x4000) != 0)
1180#define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x8000) != 0)
1181#define RELAX_MICROMIPS_LINK(i) (((i) & 0x10000) != 0)
1182#define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x20000) != 0)
1183
1184#define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x40000) != 0)
1185#define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x40000)
1186#define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x40000)
1187#define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x80000) != 0)
1188#define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x80000)
1189#define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x80000)
1190
885add95
CD
1191/* Is the given value a sign-extended 32-bit value? */
1192#define IS_SEXT_32BIT_NUM(x) \
1193 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1194 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1195
1196/* Is the given value a sign-extended 16-bit value? */
1197#define IS_SEXT_16BIT_NUM(x) \
1198 (((x) &~ (offsetT) 0x7fff) == 0 \
1199 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1200
df58fc94
RS
1201/* Is the given value a sign-extended 12-bit value? */
1202#define IS_SEXT_12BIT_NUM(x) \
1203 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1204
2051e8c4
MR
1205/* Is the given value a zero-extended 32-bit value? Or a negated one? */
1206#define IS_ZEXT_32BIT_NUM(x) \
1207 (((x) &~ (offsetT) 0xffffffff) == 0 \
1208 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1209
bf12938e
RS
1210/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1211 VALUE << SHIFT. VALUE is evaluated exactly once. */
1212#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1213 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1214 | (((VALUE) & (MASK)) << (SHIFT)))
1215
1216/* Extract bits MASK << SHIFT from STRUCT and shift them right
1217 SHIFT places. */
1218#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1219 (((STRUCT) >> (SHIFT)) & (MASK))
1220
1221/* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1222 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1223
1224 include/opcode/mips.h specifies operand fields using the macros
1225 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1226 with "MIPS16OP" instead of "OP". */
df58fc94
RS
1227#define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1228 do \
1229 if (!(MICROMIPS)) \
1230 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1231 OP_MASK_##FIELD, OP_SH_##FIELD); \
1232 else \
1233 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1234 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1235 while (0)
bf12938e
RS
1236#define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1237 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1238 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1239
1240/* Extract the operand given by FIELD from mips_cl_insn INSN. */
df58fc94
RS
1241#define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1242 (!(MICROMIPS) \
1243 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1244 : EXTRACT_BITS ((INSN).insn_opcode, \
1245 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
bf12938e
RS
1246#define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1247 EXTRACT_BITS ((INSN).insn_opcode, \
1248 MIPS16OP_MASK_##FIELD, \
1249 MIPS16OP_SH_##FIELD)
4d7206a2 1250\f
df58fc94
RS
1251/* Whether or not we are emitting a branch-likely macro. */
1252static bfd_boolean emit_branch_likely_macro = FALSE;
1253
4d7206a2
RS
1254/* Global variables used when generating relaxable macros. See the
1255 comment above RELAX_ENCODE for more details about how relaxation
1256 is used. */
1257static struct {
1258 /* 0 if we're not emitting a relaxable macro.
1259 1 if we're emitting the first of the two relaxation alternatives.
1260 2 if we're emitting the second alternative. */
1261 int sequence;
1262
1263 /* The first relaxable fixup in the current frag. (In other words,
1264 the first fixup that refers to relaxable code.) */
1265 fixS *first_fixup;
1266
1267 /* sizes[0] says how many bytes of the first alternative are stored in
1268 the current frag. Likewise sizes[1] for the second alternative. */
1269 unsigned int sizes[2];
1270
1271 /* The symbol on which the choice of sequence depends. */
1272 symbolS *symbol;
1273} mips_relax;
252b5132 1274\f
584892a6
RS
1275/* Global variables used to decide whether a macro needs a warning. */
1276static struct {
1277 /* True if the macro is in a branch delay slot. */
1278 bfd_boolean delay_slot_p;
1279
df58fc94
RS
1280 /* Set to the length in bytes required if the macro is in a delay slot
1281 that requires a specific length of instruction, otherwise zero. */
1282 unsigned int delay_slot_length;
1283
584892a6
RS
1284 /* For relaxable macros, sizes[0] is the length of the first alternative
1285 in bytes and sizes[1] is the length of the second alternative.
1286 For non-relaxable macros, both elements give the length of the
1287 macro in bytes. */
1288 unsigned int sizes[2];
1289
df58fc94
RS
1290 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1291 instruction of the first alternative in bytes and first_insn_sizes[1]
1292 is the length of the first instruction of the second alternative.
1293 For non-relaxable macros, both elements give the length of the first
1294 instruction in bytes.
1295
1296 Set to zero if we haven't yet seen the first instruction. */
1297 unsigned int first_insn_sizes[2];
1298
1299 /* For relaxable macros, insns[0] is the number of instructions for the
1300 first alternative and insns[1] is the number of instructions for the
1301 second alternative.
1302
1303 For non-relaxable macros, both elements give the number of
1304 instructions for the macro. */
1305 unsigned int insns[2];
1306
584892a6
RS
1307 /* The first variant frag for this macro. */
1308 fragS *first_frag;
1309} mips_macro_warning;
1310\f
252b5132
RH
1311/* Prototypes for static functions. */
1312
17a2f251 1313#define internalError() \
252b5132 1314 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
252b5132
RH
1315
1316enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1317
b34976b6 1318static void append_insn
df58fc94
RS
1319 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1320 bfd_boolean expansionp);
7d10b47d 1321static void mips_no_prev_insn (void);
c67a084a 1322static void macro_build (expressionS *, const char *, const char *, ...);
b34976b6 1323static void mips16_macro_build
03ea81db 1324 (expressionS *, const char *, const char *, va_list *);
67c0d1eb 1325static void load_register (int, expressionS *, int);
584892a6
RS
1326static void macro_start (void);
1327static void macro_end (void);
17a2f251
TS
1328static void macro (struct mips_cl_insn * ip);
1329static void mips16_macro (struct mips_cl_insn * ip);
17a2f251
TS
1330static void mips_ip (char *str, struct mips_cl_insn * ip);
1331static void mips16_ip (char *str, struct mips_cl_insn * ip);
b34976b6 1332static void mips16_immed
17a2f251
TS
1333 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1334 unsigned long *, bfd_boolean *, unsigned short *);
5e0116d5 1335static size_t my_getSmallExpression
17a2f251
TS
1336 (expressionS *, bfd_reloc_code_real_type *, char *);
1337static void my_getExpression (expressionS *, char *);
1338static void s_align (int);
1339static void s_change_sec (int);
1340static void s_change_section (int);
1341static void s_cons (int);
1342static void s_float_cons (int);
1343static void s_mips_globl (int);
1344static void s_option (int);
1345static void s_mipsset (int);
1346static void s_abicalls (int);
1347static void s_cpload (int);
1348static void s_cpsetup (int);
1349static void s_cplocal (int);
1350static void s_cprestore (int);
1351static void s_cpreturn (int);
741d6ea8
JM
1352static void s_dtprelword (int);
1353static void s_dtpreldword (int);
17a2f251
TS
1354static void s_gpvalue (int);
1355static void s_gpword (int);
1356static void s_gpdword (int);
1357static void s_cpadd (int);
1358static void s_insn (int);
1359static void md_obj_begin (void);
1360static void md_obj_end (void);
1361static void s_mips_ent (int);
1362static void s_mips_end (int);
1363static void s_mips_frame (int);
1364static void s_mips_mask (int reg_type);
1365static void s_mips_stab (int);
1366static void s_mips_weakext (int);
1367static void s_mips_file (int);
1368static void s_mips_loc (int);
1369static bfd_boolean pic_need_relax (symbolS *, asection *);
4a6a3df4 1370static int relaxed_branch_length (fragS *, asection *, int);
17a2f251 1371static int validate_mips_insn (const struct mips_opcode *);
df58fc94
RS
1372static int validate_micromips_insn (const struct mips_opcode *);
1373static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1374static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
e7af610e
NC
1375
1376/* Table and functions used to map between CPU/ISA names, and
1377 ISA levels, and CPU numbers. */
1378
e972090a
NC
1379struct mips_cpu_info
1380{
e7af610e 1381 const char *name; /* CPU or ISA name. */
ad3fea08 1382 int flags; /* ASEs available, or ISA flag. */
e7af610e
NC
1383 int isa; /* ISA level. */
1384 int cpu; /* CPU number (default CPU if ISA). */
1385};
1386
ad3fea08
TS
1387#define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1388#define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1389#define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1390#define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1391#define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1392#define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
8b082fb1 1393#define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
ad3fea08 1394
17a2f251
TS
1395static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1396static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1397static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
252b5132
RH
1398\f
1399/* Pseudo-op table.
1400
1401 The following pseudo-ops from the Kane and Heinrich MIPS book
1402 should be defined here, but are currently unsupported: .alias,
1403 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1404
1405 The following pseudo-ops from the Kane and Heinrich MIPS book are
1406 specific to the type of debugging information being generated, and
1407 should be defined by the object format: .aent, .begin, .bend,
1408 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1409 .vreg.
1410
1411 The following pseudo-ops from the Kane and Heinrich MIPS book are
1412 not MIPS CPU specific, but are also not specific to the object file
1413 format. This file is probably the best place to define them, but
d84bcf09 1414 they are not currently supported: .asm0, .endr, .lab, .struct. */
252b5132 1415
e972090a
NC
1416static const pseudo_typeS mips_pseudo_table[] =
1417{
beae10d5 1418 /* MIPS specific pseudo-ops. */
252b5132
RH
1419 {"option", s_option, 0},
1420 {"set", s_mipsset, 0},
1421 {"rdata", s_change_sec, 'r'},
1422 {"sdata", s_change_sec, 's'},
1423 {"livereg", s_ignore, 0},
1424 {"abicalls", s_abicalls, 0},
1425 {"cpload", s_cpload, 0},
6478892d
TS
1426 {"cpsetup", s_cpsetup, 0},
1427 {"cplocal", s_cplocal, 0},
252b5132 1428 {"cprestore", s_cprestore, 0},
6478892d 1429 {"cpreturn", s_cpreturn, 0},
741d6ea8
JM
1430 {"dtprelword", s_dtprelword, 0},
1431 {"dtpreldword", s_dtpreldword, 0},
6478892d 1432 {"gpvalue", s_gpvalue, 0},
252b5132 1433 {"gpword", s_gpword, 0},
10181a0d 1434 {"gpdword", s_gpdword, 0},
252b5132
RH
1435 {"cpadd", s_cpadd, 0},
1436 {"insn", s_insn, 0},
1437
beae10d5 1438 /* Relatively generic pseudo-ops that happen to be used on MIPS
252b5132 1439 chips. */
38a57ae7 1440 {"asciiz", stringer, 8 + 1},
252b5132
RH
1441 {"bss", s_change_sec, 'b'},
1442 {"err", s_err, 0},
1443 {"half", s_cons, 1},
1444 {"dword", s_cons, 3},
1445 {"weakext", s_mips_weakext, 0},
7c752c2a
TS
1446 {"origin", s_org, 0},
1447 {"repeat", s_rept, 0},
252b5132 1448
998b3c36
MR
1449 /* For MIPS this is non-standard, but we define it for consistency. */
1450 {"sbss", s_change_sec, 'B'},
1451
beae10d5 1452 /* These pseudo-ops are defined in read.c, but must be overridden
252b5132
RH
1453 here for one reason or another. */
1454 {"align", s_align, 0},
1455 {"byte", s_cons, 0},
1456 {"data", s_change_sec, 'd'},
1457 {"double", s_float_cons, 'd'},
1458 {"float", s_float_cons, 'f'},
1459 {"globl", s_mips_globl, 0},
1460 {"global", s_mips_globl, 0},
1461 {"hword", s_cons, 1},
1462 {"int", s_cons, 2},
1463 {"long", s_cons, 2},
1464 {"octa", s_cons, 4},
1465 {"quad", s_cons, 3},
cca86cc8 1466 {"section", s_change_section, 0},
252b5132
RH
1467 {"short", s_cons, 1},
1468 {"single", s_float_cons, 'f'},
1469 {"stabn", s_mips_stab, 'n'},
1470 {"text", s_change_sec, 't'},
1471 {"word", s_cons, 2},
add56521 1472
add56521 1473 { "extern", ecoff_directive_extern, 0},
add56521 1474
43841e91 1475 { NULL, NULL, 0 },
252b5132
RH
1476};
1477
e972090a
NC
1478static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1479{
beae10d5
KH
1480 /* These pseudo-ops should be defined by the object file format.
1481 However, a.out doesn't support them, so we have versions here. */
252b5132
RH
1482 {"aent", s_mips_ent, 1},
1483 {"bgnb", s_ignore, 0},
1484 {"end", s_mips_end, 0},
1485 {"endb", s_ignore, 0},
1486 {"ent", s_mips_ent, 0},
c5dd6aab 1487 {"file", s_mips_file, 0},
252b5132
RH
1488 {"fmask", s_mips_mask, 'F'},
1489 {"frame", s_mips_frame, 0},
c5dd6aab 1490 {"loc", s_mips_loc, 0},
252b5132
RH
1491 {"mask", s_mips_mask, 'R'},
1492 {"verstamp", s_ignore, 0},
43841e91 1493 { NULL, NULL, 0 },
252b5132
RH
1494};
1495
3ae8dd8d
MR
1496/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1497 purpose of the `.dc.a' internal pseudo-op. */
1498
1499int
1500mips_address_bytes (void)
1501{
1502 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1503}
1504
17a2f251 1505extern void pop_insert (const pseudo_typeS *);
252b5132
RH
1506
1507void
17a2f251 1508mips_pop_insert (void)
252b5132
RH
1509{
1510 pop_insert (mips_pseudo_table);
1511 if (! ECOFF_DEBUGGING)
1512 pop_insert (mips_nonecoff_pseudo_table);
1513}
1514\f
1515/* Symbols labelling the current insn. */
1516
e972090a
NC
1517struct insn_label_list
1518{
252b5132
RH
1519 struct insn_label_list *next;
1520 symbolS *label;
1521};
1522
252b5132 1523static struct insn_label_list *free_insn_labels;
742a56fe 1524#define label_list tc_segment_info_data.labels
252b5132 1525
17a2f251 1526static void mips_clear_insn_labels (void);
df58fc94
RS
1527static void mips_mark_labels (void);
1528static void mips_compressed_mark_labels (void);
252b5132
RH
1529
1530static inline void
17a2f251 1531mips_clear_insn_labels (void)
252b5132
RH
1532{
1533 register struct insn_label_list **pl;
a8dbcb85 1534 segment_info_type *si;
252b5132 1535
a8dbcb85
TS
1536 if (now_seg)
1537 {
1538 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1539 ;
1540
1541 si = seg_info (now_seg);
1542 *pl = si->label_list;
1543 si->label_list = NULL;
1544 }
252b5132 1545}
a8dbcb85 1546
df58fc94
RS
1547/* Mark instruction labels in MIPS16/microMIPS mode. */
1548
1549static inline void
1550mips_mark_labels (void)
1551{
1552 if (HAVE_CODE_COMPRESSION)
1553 mips_compressed_mark_labels ();
1554}
252b5132
RH
1555\f
1556static char *expr_end;
1557
1558/* Expressions which appear in instructions. These are set by
1559 mips_ip. */
1560
1561static expressionS imm_expr;
5f74bc13 1562static expressionS imm2_expr;
252b5132
RH
1563static expressionS offset_expr;
1564
1565/* Relocs associated with imm_expr and offset_expr. */
1566
f6688943
TS
1567static bfd_reloc_code_real_type imm_reloc[3]
1568 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1569static bfd_reloc_code_real_type offset_reloc[3]
1570 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
252b5132 1571
df58fc94
RS
1572/* This is set to the resulting size of the instruction to be produced
1573 by mips16_ip if an explicit extension is used or by mips_ip if an
1574 explicit size is supplied. */
252b5132 1575
df58fc94 1576static unsigned int forced_insn_length;
252b5132 1577
7ed4a06a 1578#ifdef OBJ_ELF
ecb4347a
DJ
1579/* The pdr segment for per procedure frame/regmask info. Not used for
1580 ECOFF debugging. */
252b5132
RH
1581
1582static segT pdr_seg;
7ed4a06a 1583#endif
252b5132 1584
e013f690
TS
1585/* The default target format to use. */
1586
aeffff67
RS
1587#if defined (TE_FreeBSD)
1588#define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1589#elif defined (TE_TMIPS)
1590#define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1591#else
1592#define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1593#endif
1594
e013f690 1595const char *
17a2f251 1596mips_target_format (void)
e013f690
TS
1597{
1598 switch (OUTPUT_FLAVOR)
1599 {
e013f690
TS
1600 case bfd_target_ecoff_flavour:
1601 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1602 case bfd_target_coff_flavour:
1603 return "pe-mips";
1604 case bfd_target_elf_flavour:
0a44bf69
RS
1605#ifdef TE_VXWORKS
1606 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1607 return (target_big_endian
1608 ? "elf32-bigmips-vxworks"
1609 : "elf32-littlemips-vxworks");
1610#endif
e013f690 1611 return (target_big_endian
cfe86eaa 1612 ? (HAVE_64BIT_OBJECTS
aeffff67 1613 ? ELF_TARGET ("elf64-", "big")
cfe86eaa 1614 : (HAVE_NEWABI
aeffff67
RS
1615 ? ELF_TARGET ("elf32-n", "big")
1616 : ELF_TARGET ("elf32-", "big")))
cfe86eaa 1617 : (HAVE_64BIT_OBJECTS
aeffff67 1618 ? ELF_TARGET ("elf64-", "little")
cfe86eaa 1619 : (HAVE_NEWABI
aeffff67
RS
1620 ? ELF_TARGET ("elf32-n", "little")
1621 : ELF_TARGET ("elf32-", "little"))));
e013f690
TS
1622 default:
1623 abort ();
1624 return NULL;
1625 }
1626}
1627
df58fc94
RS
1628/* Return the length of a microMIPS instruction in bytes. If bits of
1629 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1630 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1631 major opcode) will require further modifications to the opcode
1632 table. */
1633
1634static inline unsigned int
1635micromips_insn_length (const struct mips_opcode *mo)
1636{
1637 return (mo->mask >> 16) == 0 ? 2 : 4;
1638}
1639
1e915849
RS
1640/* Return the length of instruction INSN. */
1641
1642static inline unsigned int
1643insn_length (const struct mips_cl_insn *insn)
1644{
df58fc94
RS
1645 if (mips_opts.micromips)
1646 return micromips_insn_length (insn->insn_mo);
1647 else if (mips_opts.mips16)
1648 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1649 else
1e915849 1650 return 4;
1e915849
RS
1651}
1652
1653/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1654
1655static void
1656create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1657{
1658 size_t i;
1659
1660 insn->insn_mo = mo;
1661 insn->use_extend = FALSE;
1662 insn->extend = 0;
1663 insn->insn_opcode = mo->match;
1664 insn->frag = NULL;
1665 insn->where = 0;
1666 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1667 insn->fixp[i] = NULL;
1668 insn->fixed_p = (mips_opts.noreorder > 0);
1669 insn->noreorder_p = (mips_opts.noreorder > 0);
1670 insn->mips16_absolute_jump_p = 0;
15be625d 1671 insn->complete_p = 0;
1e915849
RS
1672}
1673
df58fc94 1674/* Record the current MIPS16/microMIPS mode in now_seg. */
742a56fe
RS
1675
1676static void
df58fc94 1677mips_record_compressed_mode (void)
742a56fe
RS
1678{
1679 segment_info_type *si;
1680
1681 si = seg_info (now_seg);
1682 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1683 si->tc_segment_info_data.mips16 = mips_opts.mips16;
df58fc94
RS
1684 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
1685 si->tc_segment_info_data.micromips = mips_opts.micromips;
742a56fe
RS
1686}
1687
1e915849
RS
1688/* Install INSN at the location specified by its "frag" and "where" fields. */
1689
1690static void
1691install_insn (const struct mips_cl_insn *insn)
1692{
1693 char *f = insn->frag->fr_literal + insn->where;
df58fc94 1694 if (!HAVE_CODE_COMPRESSION)
1e915849 1695 md_number_to_chars (f, insn->insn_opcode, 4);
df58fc94
RS
1696 else if (mips_opts.micromips)
1697 {
1698 unsigned int length = insn_length (insn);
1699 if (length == 2)
1700 md_number_to_chars (f, insn->insn_opcode, 2);
1701 else if (length == 4)
1702 {
1703 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1704 f += 2;
1705 md_number_to_chars (f, insn->insn_opcode & 0xffff, 2);
1706 }
1707 else
1708 as_bad (_("48-bit microMIPS instructions are not supported"));
1709 }
1e915849
RS
1710 else if (insn->mips16_absolute_jump_p)
1711 {
1712 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1713 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1714 }
1715 else
1716 {
1717 if (insn->use_extend)
1718 {
1719 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1720 f += 2;
1721 }
1722 md_number_to_chars (f, insn->insn_opcode, 2);
1723 }
df58fc94 1724 mips_record_compressed_mode ();
1e915849
RS
1725}
1726
1727/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1728 and install the opcode in the new location. */
1729
1730static void
1731move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1732{
1733 size_t i;
1734
1735 insn->frag = frag;
1736 insn->where = where;
1737 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1738 if (insn->fixp[i] != NULL)
1739 {
1740 insn->fixp[i]->fx_frag = frag;
1741 insn->fixp[i]->fx_where = where;
1742 }
1743 install_insn (insn);
1744}
1745
1746/* Add INSN to the end of the output. */
1747
1748static void
1749add_fixed_insn (struct mips_cl_insn *insn)
1750{
1751 char *f = frag_more (insn_length (insn));
1752 move_insn (insn, frag_now, f - frag_now->fr_literal);
1753}
1754
1755/* Start a variant frag and move INSN to the start of the variant part,
1756 marking it as fixed. The other arguments are as for frag_var. */
1757
1758static void
1759add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1760 relax_substateT subtype, symbolS *symbol, offsetT offset)
1761{
1762 frag_grow (max_chars);
1763 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1764 insn->fixed_p = 1;
1765 frag_var (rs_machine_dependent, max_chars, var,
1766 subtype, symbol, offset, NULL);
1767}
1768
1769/* Insert N copies of INSN into the history buffer, starting at
1770 position FIRST. Neither FIRST nor N need to be clipped. */
1771
1772static void
1773insert_into_history (unsigned int first, unsigned int n,
1774 const struct mips_cl_insn *insn)
1775{
1776 if (mips_relax.sequence != 2)
1777 {
1778 unsigned int i;
1779
1780 for (i = ARRAY_SIZE (history); i-- > first;)
1781 if (i >= first + n)
1782 history[i] = history[i - n];
1783 else
1784 history[i] = *insn;
1785 }
1786}
1787
1788/* Emit a nop instruction, recording it in the history buffer. */
1789
1790static void
1791emit_nop (void)
1792{
1793 add_fixed_insn (NOP_INSN);
1794 insert_into_history (0, 1, NOP_INSN);
1795}
1796
71400594
RS
1797/* Initialize vr4120_conflicts. There is a bit of duplication here:
1798 the idea is to make it obvious at a glance that each errata is
1799 included. */
1800
1801static void
1802init_vr4120_conflicts (void)
1803{
1804#define CONFLICT(FIRST, SECOND) \
1805 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1806
1807 /* Errata 21 - [D]DIV[U] after [D]MACC */
1808 CONFLICT (MACC, DIV);
1809 CONFLICT (DMACC, DIV);
1810
1811 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1812 CONFLICT (DMULT, DMULT);
1813 CONFLICT (DMULT, DMACC);
1814 CONFLICT (DMACC, DMULT);
1815 CONFLICT (DMACC, DMACC);
1816
1817 /* Errata 24 - MT{LO,HI} after [D]MACC */
1818 CONFLICT (MACC, MTHILO);
1819 CONFLICT (DMACC, MTHILO);
1820
1821 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1822 instruction is executed immediately after a MACC or DMACC
1823 instruction, the result of [either instruction] is incorrect." */
1824 CONFLICT (MACC, MULT);
1825 CONFLICT (MACC, DMULT);
1826 CONFLICT (DMACC, MULT);
1827 CONFLICT (DMACC, DMULT);
1828
1829 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1830 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1831 DDIV or DDIVU instruction, the result of the MACC or
1832 DMACC instruction is incorrect.". */
1833 CONFLICT (DMULT, MACC);
1834 CONFLICT (DMULT, DMACC);
1835 CONFLICT (DIV, MACC);
1836 CONFLICT (DIV, DMACC);
1837
1838#undef CONFLICT
1839}
1840
707bfff6
TS
1841struct regname {
1842 const char *name;
1843 unsigned int num;
1844};
1845
1846#define RTYPE_MASK 0x1ff00
1847#define RTYPE_NUM 0x00100
1848#define RTYPE_FPU 0x00200
1849#define RTYPE_FCC 0x00400
1850#define RTYPE_VEC 0x00800
1851#define RTYPE_GP 0x01000
1852#define RTYPE_CP0 0x02000
1853#define RTYPE_PC 0x04000
1854#define RTYPE_ACC 0x08000
1855#define RTYPE_CCC 0x10000
1856#define RNUM_MASK 0x000ff
1857#define RWARN 0x80000
1858
1859#define GENERIC_REGISTER_NUMBERS \
1860 {"$0", RTYPE_NUM | 0}, \
1861 {"$1", RTYPE_NUM | 1}, \
1862 {"$2", RTYPE_NUM | 2}, \
1863 {"$3", RTYPE_NUM | 3}, \
1864 {"$4", RTYPE_NUM | 4}, \
1865 {"$5", RTYPE_NUM | 5}, \
1866 {"$6", RTYPE_NUM | 6}, \
1867 {"$7", RTYPE_NUM | 7}, \
1868 {"$8", RTYPE_NUM | 8}, \
1869 {"$9", RTYPE_NUM | 9}, \
1870 {"$10", RTYPE_NUM | 10}, \
1871 {"$11", RTYPE_NUM | 11}, \
1872 {"$12", RTYPE_NUM | 12}, \
1873 {"$13", RTYPE_NUM | 13}, \
1874 {"$14", RTYPE_NUM | 14}, \
1875 {"$15", RTYPE_NUM | 15}, \
1876 {"$16", RTYPE_NUM | 16}, \
1877 {"$17", RTYPE_NUM | 17}, \
1878 {"$18", RTYPE_NUM | 18}, \
1879 {"$19", RTYPE_NUM | 19}, \
1880 {"$20", RTYPE_NUM | 20}, \
1881 {"$21", RTYPE_NUM | 21}, \
1882 {"$22", RTYPE_NUM | 22}, \
1883 {"$23", RTYPE_NUM | 23}, \
1884 {"$24", RTYPE_NUM | 24}, \
1885 {"$25", RTYPE_NUM | 25}, \
1886 {"$26", RTYPE_NUM | 26}, \
1887 {"$27", RTYPE_NUM | 27}, \
1888 {"$28", RTYPE_NUM | 28}, \
1889 {"$29", RTYPE_NUM | 29}, \
1890 {"$30", RTYPE_NUM | 30}, \
1891 {"$31", RTYPE_NUM | 31}
1892
1893#define FPU_REGISTER_NAMES \
1894 {"$f0", RTYPE_FPU | 0}, \
1895 {"$f1", RTYPE_FPU | 1}, \
1896 {"$f2", RTYPE_FPU | 2}, \
1897 {"$f3", RTYPE_FPU | 3}, \
1898 {"$f4", RTYPE_FPU | 4}, \
1899 {"$f5", RTYPE_FPU | 5}, \
1900 {"$f6", RTYPE_FPU | 6}, \
1901 {"$f7", RTYPE_FPU | 7}, \
1902 {"$f8", RTYPE_FPU | 8}, \
1903 {"$f9", RTYPE_FPU | 9}, \
1904 {"$f10", RTYPE_FPU | 10}, \
1905 {"$f11", RTYPE_FPU | 11}, \
1906 {"$f12", RTYPE_FPU | 12}, \
1907 {"$f13", RTYPE_FPU | 13}, \
1908 {"$f14", RTYPE_FPU | 14}, \
1909 {"$f15", RTYPE_FPU | 15}, \
1910 {"$f16", RTYPE_FPU | 16}, \
1911 {"$f17", RTYPE_FPU | 17}, \
1912 {"$f18", RTYPE_FPU | 18}, \
1913 {"$f19", RTYPE_FPU | 19}, \
1914 {"$f20", RTYPE_FPU | 20}, \
1915 {"$f21", RTYPE_FPU | 21}, \
1916 {"$f22", RTYPE_FPU | 22}, \
1917 {"$f23", RTYPE_FPU | 23}, \
1918 {"$f24", RTYPE_FPU | 24}, \
1919 {"$f25", RTYPE_FPU | 25}, \
1920 {"$f26", RTYPE_FPU | 26}, \
1921 {"$f27", RTYPE_FPU | 27}, \
1922 {"$f28", RTYPE_FPU | 28}, \
1923 {"$f29", RTYPE_FPU | 29}, \
1924 {"$f30", RTYPE_FPU | 30}, \
1925 {"$f31", RTYPE_FPU | 31}
1926
1927#define FPU_CONDITION_CODE_NAMES \
1928 {"$fcc0", RTYPE_FCC | 0}, \
1929 {"$fcc1", RTYPE_FCC | 1}, \
1930 {"$fcc2", RTYPE_FCC | 2}, \
1931 {"$fcc3", RTYPE_FCC | 3}, \
1932 {"$fcc4", RTYPE_FCC | 4}, \
1933 {"$fcc5", RTYPE_FCC | 5}, \
1934 {"$fcc6", RTYPE_FCC | 6}, \
1935 {"$fcc7", RTYPE_FCC | 7}
1936
1937#define COPROC_CONDITION_CODE_NAMES \
1938 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1939 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1940 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1941 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1942 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1943 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1944 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1945 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1946
1947#define N32N64_SYMBOLIC_REGISTER_NAMES \
1948 {"$a4", RTYPE_GP | 8}, \
1949 {"$a5", RTYPE_GP | 9}, \
1950 {"$a6", RTYPE_GP | 10}, \
1951 {"$a7", RTYPE_GP | 11}, \
1952 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1953 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1954 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1955 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1956 {"$t0", RTYPE_GP | 12}, \
1957 {"$t1", RTYPE_GP | 13}, \
1958 {"$t2", RTYPE_GP | 14}, \
1959 {"$t3", RTYPE_GP | 15}
1960
1961#define O32_SYMBOLIC_REGISTER_NAMES \
1962 {"$t0", RTYPE_GP | 8}, \
1963 {"$t1", RTYPE_GP | 9}, \
1964 {"$t2", RTYPE_GP | 10}, \
1965 {"$t3", RTYPE_GP | 11}, \
1966 {"$t4", RTYPE_GP | 12}, \
1967 {"$t5", RTYPE_GP | 13}, \
1968 {"$t6", RTYPE_GP | 14}, \
1969 {"$t7", RTYPE_GP | 15}, \
1970 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1971 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1972 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1973 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1974
1975/* Remaining symbolic register names */
1976#define SYMBOLIC_REGISTER_NAMES \
1977 {"$zero", RTYPE_GP | 0}, \
1978 {"$at", RTYPE_GP | 1}, \
1979 {"$AT", RTYPE_GP | 1}, \
1980 {"$v0", RTYPE_GP | 2}, \
1981 {"$v1", RTYPE_GP | 3}, \
1982 {"$a0", RTYPE_GP | 4}, \
1983 {"$a1", RTYPE_GP | 5}, \
1984 {"$a2", RTYPE_GP | 6}, \
1985 {"$a3", RTYPE_GP | 7}, \
1986 {"$s0", RTYPE_GP | 16}, \
1987 {"$s1", RTYPE_GP | 17}, \
1988 {"$s2", RTYPE_GP | 18}, \
1989 {"$s3", RTYPE_GP | 19}, \
1990 {"$s4", RTYPE_GP | 20}, \
1991 {"$s5", RTYPE_GP | 21}, \
1992 {"$s6", RTYPE_GP | 22}, \
1993 {"$s7", RTYPE_GP | 23}, \
1994 {"$t8", RTYPE_GP | 24}, \
1995 {"$t9", RTYPE_GP | 25}, \
1996 {"$k0", RTYPE_GP | 26}, \
1997 {"$kt0", RTYPE_GP | 26}, \
1998 {"$k1", RTYPE_GP | 27}, \
1999 {"$kt1", RTYPE_GP | 27}, \
2000 {"$gp", RTYPE_GP | 28}, \
2001 {"$sp", RTYPE_GP | 29}, \
2002 {"$s8", RTYPE_GP | 30}, \
2003 {"$fp", RTYPE_GP | 30}, \
2004 {"$ra", RTYPE_GP | 31}
2005
2006#define MIPS16_SPECIAL_REGISTER_NAMES \
2007 {"$pc", RTYPE_PC | 0}
2008
2009#define MDMX_VECTOR_REGISTER_NAMES \
2010 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2011 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2012 {"$v2", RTYPE_VEC | 2}, \
2013 {"$v3", RTYPE_VEC | 3}, \
2014 {"$v4", RTYPE_VEC | 4}, \
2015 {"$v5", RTYPE_VEC | 5}, \
2016 {"$v6", RTYPE_VEC | 6}, \
2017 {"$v7", RTYPE_VEC | 7}, \
2018 {"$v8", RTYPE_VEC | 8}, \
2019 {"$v9", RTYPE_VEC | 9}, \
2020 {"$v10", RTYPE_VEC | 10}, \
2021 {"$v11", RTYPE_VEC | 11}, \
2022 {"$v12", RTYPE_VEC | 12}, \
2023 {"$v13", RTYPE_VEC | 13}, \
2024 {"$v14", RTYPE_VEC | 14}, \
2025 {"$v15", RTYPE_VEC | 15}, \
2026 {"$v16", RTYPE_VEC | 16}, \
2027 {"$v17", RTYPE_VEC | 17}, \
2028 {"$v18", RTYPE_VEC | 18}, \
2029 {"$v19", RTYPE_VEC | 19}, \
2030 {"$v20", RTYPE_VEC | 20}, \
2031 {"$v21", RTYPE_VEC | 21}, \
2032 {"$v22", RTYPE_VEC | 22}, \
2033 {"$v23", RTYPE_VEC | 23}, \
2034 {"$v24", RTYPE_VEC | 24}, \
2035 {"$v25", RTYPE_VEC | 25}, \
2036 {"$v26", RTYPE_VEC | 26}, \
2037 {"$v27", RTYPE_VEC | 27}, \
2038 {"$v28", RTYPE_VEC | 28}, \
2039 {"$v29", RTYPE_VEC | 29}, \
2040 {"$v30", RTYPE_VEC | 30}, \
2041 {"$v31", RTYPE_VEC | 31}
2042
2043#define MIPS_DSP_ACCUMULATOR_NAMES \
2044 {"$ac0", RTYPE_ACC | 0}, \
2045 {"$ac1", RTYPE_ACC | 1}, \
2046 {"$ac2", RTYPE_ACC | 2}, \
2047 {"$ac3", RTYPE_ACC | 3}
2048
2049static const struct regname reg_names[] = {
2050 GENERIC_REGISTER_NUMBERS,
2051 FPU_REGISTER_NAMES,
2052 FPU_CONDITION_CODE_NAMES,
2053 COPROC_CONDITION_CODE_NAMES,
2054
2055 /* The $txx registers depends on the abi,
2056 these will be added later into the symbol table from
2057 one of the tables below once mips_abi is set after
2058 parsing of arguments from the command line. */
2059 SYMBOLIC_REGISTER_NAMES,
2060
2061 MIPS16_SPECIAL_REGISTER_NAMES,
2062 MDMX_VECTOR_REGISTER_NAMES,
2063 MIPS_DSP_ACCUMULATOR_NAMES,
2064 {0, 0}
2065};
2066
2067static const struct regname reg_names_o32[] = {
2068 O32_SYMBOLIC_REGISTER_NAMES,
2069 {0, 0}
2070};
2071
2072static const struct regname reg_names_n32n64[] = {
2073 N32N64_SYMBOLIC_REGISTER_NAMES,
2074 {0, 0}
2075};
2076
df58fc94
RS
2077/* Check if S points at a valid register specifier according to TYPES.
2078 If so, then return 1, advance S to consume the specifier and store
2079 the register's number in REGNOP, otherwise return 0. */
2080
707bfff6
TS
2081static int
2082reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2083{
2084 symbolS *symbolP;
2085 char *e;
2086 char save_c;
2087 int reg = -1;
2088
2089 /* Find end of name. */
2090 e = *s;
2091 if (is_name_beginner (*e))
2092 ++e;
2093 while (is_part_of_name (*e))
2094 ++e;
2095
2096 /* Terminate name. */
2097 save_c = *e;
2098 *e = '\0';
2099
2100 /* Look for a register symbol. */
2101 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2102 {
2103 int r = S_GET_VALUE (symbolP);
2104 if (r & types)
2105 reg = r & RNUM_MASK;
2106 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2107 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2108 reg = (r & RNUM_MASK) - 2;
2109 }
2110 /* Else see if this is a register defined in an itbl entry. */
2111 else if ((types & RTYPE_GP) && itbl_have_entries)
2112 {
2113 char *n = *s;
2114 unsigned long r;
2115
2116 if (*n == '$')
2117 ++n;
2118 if (itbl_get_reg_val (n, &r))
2119 reg = r & RNUM_MASK;
2120 }
2121
2122 /* Advance to next token if a register was recognised. */
2123 if (reg >= 0)
2124 *s = e;
2125 else if (types & RWARN)
20203fb9 2126 as_warn (_("Unrecognized register name `%s'"), *s);
707bfff6
TS
2127
2128 *e = save_c;
2129 if (regnop)
2130 *regnop = reg;
2131 return reg >= 0;
2132}
2133
df58fc94
RS
2134/* Check if S points at a valid register list according to TYPES.
2135 If so, then return 1, advance S to consume the list and store
2136 the registers present on the list as a bitmask of ones in REGLISTP,
2137 otherwise return 0. A valid list comprises a comma-separated
2138 enumeration of valid single registers and/or dash-separated
2139 contiguous register ranges as determined by their numbers.
2140
2141 As a special exception if one of s0-s7 registers is specified as
2142 the range's lower delimiter and s8 (fp) is its upper one, then no
2143 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2309ddf2 2144 are selected; they have to be listed separately if needed. */
df58fc94
RS
2145
2146static int
2147reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2148{
2149 unsigned int reglist = 0;
2150 unsigned int lastregno;
2151 bfd_boolean ok = TRUE;
2152 unsigned int regmask;
2309ddf2 2153 char *s_endlist = *s;
df58fc94 2154 char *s_reset = *s;
2309ddf2 2155 unsigned int regno;
df58fc94
RS
2156
2157 while (reg_lookup (s, types, &regno))
2158 {
2159 lastregno = regno;
2160 if (**s == '-')
2161 {
2162 (*s)++;
2163 ok = reg_lookup (s, types, &lastregno);
2164 if (ok && lastregno < regno)
2165 ok = FALSE;
2166 if (!ok)
2167 break;
2168 }
2169
2170 if (lastregno == FP && regno >= S0 && regno <= S7)
2171 {
2172 lastregno = S7;
2173 reglist |= 1 << FP;
2174 }
2175 regmask = 1 << lastregno;
2176 regmask = (regmask << 1) - 1;
2177 regmask ^= (1 << regno) - 1;
2178 reglist |= regmask;
2179
2309ddf2 2180 s_endlist = *s;
df58fc94
RS
2181 if (**s != ',')
2182 break;
2183 (*s)++;
2184 }
2185
2186 if (ok)
2309ddf2 2187 *s = s_endlist;
df58fc94
RS
2188 else
2189 *s = s_reset;
2190 if (reglistp)
2191 *reglistp = reglist;
2192 return ok && reglist != 0;
2193}
2194
037b32b9 2195/* Return TRUE if opcode MO is valid on the currently selected ISA and
f79e2745 2196 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
037b32b9
AN
2197
2198static bfd_boolean
f79e2745 2199is_opcode_valid (const struct mips_opcode *mo)
037b32b9
AN
2200{
2201 int isa = mips_opts.isa;
2202 int fp_s, fp_d;
2203
2204 if (mips_opts.ase_mdmx)
2205 isa |= INSN_MDMX;
2206 if (mips_opts.ase_dsp)
2207 isa |= INSN_DSP;
2208 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
2209 isa |= INSN_DSP64;
2210 if (mips_opts.ase_dspr2)
2211 isa |= INSN_DSPR2;
2212 if (mips_opts.ase_mt)
2213 isa |= INSN_MT;
2214 if (mips_opts.ase_mips3d)
2215 isa |= INSN_MIPS3D;
2216 if (mips_opts.ase_smartmips)
2217 isa |= INSN_SMARTMIPS;
2218
b19e8a9b
AN
2219 /* Don't accept instructions based on the ISA if the CPU does not implement
2220 all the coprocessor insns. */
2221 if (NO_ISA_COP (mips_opts.arch)
2222 && COP_INSN (mo->pinfo))
2223 isa = 0;
2224
037b32b9
AN
2225 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
2226 return FALSE;
2227
2228 /* Check whether the instruction or macro requires single-precision or
2229 double-precision floating-point support. Note that this information is
2230 stored differently in the opcode table for insns and macros. */
2231 if (mo->pinfo == INSN_MACRO)
2232 {
2233 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2234 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2235 }
2236 else
2237 {
2238 fp_s = mo->pinfo & FP_S;
2239 fp_d = mo->pinfo & FP_D;
2240 }
2241
2242 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2243 return FALSE;
2244
2245 if (fp_s && mips_opts.soft_float)
2246 return FALSE;
2247
2248 return TRUE;
2249}
2250
2251/* Return TRUE if the MIPS16 opcode MO is valid on the currently
2252 selected ISA and architecture. */
2253
2254static bfd_boolean
2255is_opcode_valid_16 (const struct mips_opcode *mo)
2256{
2257 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
2258}
2259
df58fc94
RS
2260/* Return TRUE if the size of the microMIPS opcode MO matches one
2261 explicitly requested. Always TRUE in the standard MIPS mode. */
2262
2263static bfd_boolean
2264is_size_valid (const struct mips_opcode *mo)
2265{
2266 if (!mips_opts.micromips)
2267 return TRUE;
2268
2269 if (!forced_insn_length)
2270 return TRUE;
2271 if (mo->pinfo == INSN_MACRO)
2272 return FALSE;
2273 return forced_insn_length == micromips_insn_length (mo);
2274}
2275
2276/* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2277 of the preceding instruction. Always TRUE in the standard MIPS mode. */
2278
2279static bfd_boolean
2280is_delay_slot_valid (const struct mips_opcode *mo)
2281{
2282 if (!mips_opts.micromips)
2283 return TRUE;
2284
2285 if (mo->pinfo == INSN_MACRO)
2286 return TRUE;
2287 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2288 && micromips_insn_length (mo) != 4)
2289 return FALSE;
2290 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2291 && micromips_insn_length (mo) != 2)
2292 return FALSE;
2293
2294 return TRUE;
2295}
2296
707bfff6
TS
2297/* This function is called once, at assembler startup time. It should set up
2298 all the tables, etc. that the MD part of the assembler will need. */
156c2f8b 2299
252b5132 2300void
17a2f251 2301md_begin (void)
252b5132 2302{
3994f87e 2303 const char *retval = NULL;
156c2f8b 2304 int i = 0;
252b5132 2305 int broken = 0;
1f25f5d3 2306
0a44bf69
RS
2307 if (mips_pic != NO_PIC)
2308 {
2309 if (g_switch_seen && g_switch_value != 0)
2310 as_bad (_("-G may not be used in position-independent code"));
2311 g_switch_value = 0;
2312 }
2313
fef14a42 2314 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
252b5132
RH
2315 as_warn (_("Could not set architecture and machine"));
2316
252b5132
RH
2317 op_hash = hash_new ();
2318
2319 for (i = 0; i < NUMOPCODES;)
2320 {
2321 const char *name = mips_opcodes[i].name;
2322
17a2f251 2323 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
252b5132
RH
2324 if (retval != NULL)
2325 {
2326 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2327 mips_opcodes[i].name, retval);
2328 /* Probably a memory allocation problem? Give up now. */
2329 as_fatal (_("Broken assembler. No assembly attempted."));
2330 }
2331 do
2332 {
2333 if (mips_opcodes[i].pinfo != INSN_MACRO)
2334 {
2335 if (!validate_mips_insn (&mips_opcodes[i]))
2336 broken = 1;
1e915849
RS
2337 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2338 {
2339 create_insn (&nop_insn, mips_opcodes + i);
c67a084a
NC
2340 if (mips_fix_loongson2f_nop)
2341 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
1e915849
RS
2342 nop_insn.fixed_p = 1;
2343 }
252b5132
RH
2344 }
2345 ++i;
2346 }
2347 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2348 }
2349
2350 mips16_op_hash = hash_new ();
2351
2352 i = 0;
2353 while (i < bfd_mips16_num_opcodes)
2354 {
2355 const char *name = mips16_opcodes[i].name;
2356
17a2f251 2357 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
252b5132
RH
2358 if (retval != NULL)
2359 as_fatal (_("internal: can't hash `%s': %s"),
2360 mips16_opcodes[i].name, retval);
2361 do
2362 {
2363 if (mips16_opcodes[i].pinfo != INSN_MACRO
2364 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2365 != mips16_opcodes[i].match))
2366 {
2367 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2368 mips16_opcodes[i].name, mips16_opcodes[i].args);
2369 broken = 1;
2370 }
1e915849
RS
2371 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2372 {
2373 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2374 mips16_nop_insn.fixed_p = 1;
2375 }
252b5132
RH
2376 ++i;
2377 }
2378 while (i < bfd_mips16_num_opcodes
2379 && strcmp (mips16_opcodes[i].name, name) == 0);
2380 }
2381
df58fc94
RS
2382 micromips_op_hash = hash_new ();
2383
2384 i = 0;
2385 while (i < bfd_micromips_num_opcodes)
2386 {
2387 const char *name = micromips_opcodes[i].name;
2388
2389 retval = hash_insert (micromips_op_hash, name,
2390 (void *) &micromips_opcodes[i]);
2391 if (retval != NULL)
2392 as_fatal (_("internal: can't hash `%s': %s"),
2393 micromips_opcodes[i].name, retval);
2394 do
2395 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2396 {
2397 struct mips_cl_insn *micromips_nop_insn;
2398
2399 if (!validate_micromips_insn (&micromips_opcodes[i]))
2400 broken = 1;
2401
2402 if (micromips_insn_length (micromips_opcodes + i) == 2)
2403 micromips_nop_insn = &micromips_nop16_insn;
2404 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2405 micromips_nop_insn = &micromips_nop32_insn;
2406 else
2407 continue;
2408
2409 if (micromips_nop_insn->insn_mo == NULL
2410 && strcmp (name, "nop") == 0)
2411 {
2412 create_insn (micromips_nop_insn, micromips_opcodes + i);
2413 micromips_nop_insn->fixed_p = 1;
2414 }
2415 }
2416 while (++i < bfd_micromips_num_opcodes
2417 && strcmp (micromips_opcodes[i].name, name) == 0);
2418 }
2419
252b5132
RH
2420 if (broken)
2421 as_fatal (_("Broken assembler. No assembly attempted."));
2422
2423 /* We add all the general register names to the symbol table. This
2424 helps us detect invalid uses of them. */
707bfff6
TS
2425 for (i = 0; reg_names[i].name; i++)
2426 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
8fc4ee9b 2427 reg_names[i].num, /* & RNUM_MASK, */
707bfff6
TS
2428 &zero_address_frag));
2429 if (HAVE_NEWABI)
2430 for (i = 0; reg_names_n32n64[i].name; i++)
2431 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
8fc4ee9b 2432 reg_names_n32n64[i].num, /* & RNUM_MASK, */
252b5132 2433 &zero_address_frag));
707bfff6
TS
2434 else
2435 for (i = 0; reg_names_o32[i].name; i++)
2436 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
8fc4ee9b 2437 reg_names_o32[i].num, /* & RNUM_MASK, */
6047c971 2438 &zero_address_frag));
6047c971 2439
7d10b47d 2440 mips_no_prev_insn ();
252b5132
RH
2441
2442 mips_gprmask = 0;
2443 mips_cprmask[0] = 0;
2444 mips_cprmask[1] = 0;
2445 mips_cprmask[2] = 0;
2446 mips_cprmask[3] = 0;
2447
2448 /* set the default alignment for the text section (2**2) */
2449 record_alignment (text_section, 2);
2450
4d0d148d 2451 bfd_set_gp_size (stdoutput, g_switch_value);
252b5132 2452
707bfff6 2453#ifdef OBJ_ELF
f43abd2b 2454 if (IS_ELF)
252b5132 2455 {
0a44bf69
RS
2456 /* On a native system other than VxWorks, sections must be aligned
2457 to 16 byte boundaries. When configured for an embedded ELF
2458 target, we don't bother. */
c41e87e3
CF
2459 if (strncmp (TARGET_OS, "elf", 3) != 0
2460 && strncmp (TARGET_OS, "vxworks", 7) != 0)
252b5132
RH
2461 {
2462 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2463 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2464 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2465 }
2466
2467 /* Create a .reginfo section for register masks and a .mdebug
2468 section for debugging information. */
2469 {
2470 segT seg;
2471 subsegT subseg;
2472 flagword flags;
2473 segT sec;
2474
2475 seg = now_seg;
2476 subseg = now_subseg;
2477
2478 /* The ABI says this section should be loaded so that the
2479 running program can access it. However, we don't load it
2480 if we are configured for an embedded target */
2481 flags = SEC_READONLY | SEC_DATA;
c41e87e3 2482 if (strncmp (TARGET_OS, "elf", 3) != 0)
252b5132
RH
2483 flags |= SEC_ALLOC | SEC_LOAD;
2484
316f5878 2485 if (mips_abi != N64_ABI)
252b5132
RH
2486 {
2487 sec = subseg_new (".reginfo", (subsegT) 0);
2488
195325d2
TS
2489 bfd_set_section_flags (stdoutput, sec, flags);
2490 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
bdaaa2e1 2491
252b5132 2492 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
252b5132
RH
2493 }
2494 else
2495 {
2496 /* The 64-bit ABI uses a .MIPS.options section rather than
2497 .reginfo section. */
2498 sec = subseg_new (".MIPS.options", (subsegT) 0);
195325d2
TS
2499 bfd_set_section_flags (stdoutput, sec, flags);
2500 bfd_set_section_alignment (stdoutput, sec, 3);
252b5132 2501
252b5132
RH
2502 /* Set up the option header. */
2503 {
2504 Elf_Internal_Options opthdr;
2505 char *f;
2506
2507 opthdr.kind = ODK_REGINFO;
2508 opthdr.size = (sizeof (Elf_External_Options)
2509 + sizeof (Elf64_External_RegInfo));
2510 opthdr.section = 0;
2511 opthdr.info = 0;
2512 f = frag_more (sizeof (Elf_External_Options));
2513 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2514 (Elf_External_Options *) f);
2515
2516 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2517 }
252b5132
RH
2518 }
2519
2520 if (ECOFF_DEBUGGING)
2521 {
2522 sec = subseg_new (".mdebug", (subsegT) 0);
2523 (void) bfd_set_section_flags (stdoutput, sec,
2524 SEC_HAS_CONTENTS | SEC_READONLY);
2525 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2526 }
f43abd2b 2527 else if (mips_flag_pdr)
ecb4347a
DJ
2528 {
2529 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2530 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2531 SEC_READONLY | SEC_RELOC
2532 | SEC_DEBUGGING);
2533 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2534 }
252b5132
RH
2535
2536 subseg_set (seg, subseg);
2537 }
2538 }
707bfff6 2539#endif /* OBJ_ELF */
252b5132
RH
2540
2541 if (! ECOFF_DEBUGGING)
2542 md_obj_begin ();
71400594
RS
2543
2544 if (mips_fix_vr4120)
2545 init_vr4120_conflicts ();
252b5132
RH
2546}
2547
2548void
17a2f251 2549md_mips_end (void)
252b5132 2550{
02b1ab82 2551 mips_emit_delays ();
252b5132
RH
2552 if (! ECOFF_DEBUGGING)
2553 md_obj_end ();
2554}
2555
2556void
17a2f251 2557md_assemble (char *str)
252b5132
RH
2558{
2559 struct mips_cl_insn insn;
f6688943
TS
2560 bfd_reloc_code_real_type unused_reloc[3]
2561 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
252b5132
RH
2562
2563 imm_expr.X_op = O_absent;
5f74bc13 2564 imm2_expr.X_op = O_absent;
252b5132 2565 offset_expr.X_op = O_absent;
f6688943
TS
2566 imm_reloc[0] = BFD_RELOC_UNUSED;
2567 imm_reloc[1] = BFD_RELOC_UNUSED;
2568 imm_reloc[2] = BFD_RELOC_UNUSED;
2569 offset_reloc[0] = BFD_RELOC_UNUSED;
2570 offset_reloc[1] = BFD_RELOC_UNUSED;
2571 offset_reloc[2] = BFD_RELOC_UNUSED;
252b5132
RH
2572
2573 if (mips_opts.mips16)
2574 mips16_ip (str, &insn);
2575 else
2576 {
2577 mips_ip (str, &insn);
beae10d5
KH
2578 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2579 str, insn.insn_opcode));
252b5132
RH
2580 }
2581
2582 if (insn_error)
2583 {
2584 as_bad ("%s `%s'", insn_error, str);
2585 return;
2586 }
2587
2588 if (insn.insn_mo->pinfo == INSN_MACRO)
2589 {
584892a6 2590 macro_start ();
252b5132
RH
2591 if (mips_opts.mips16)
2592 mips16_macro (&insn);
2593 else
2594 macro (&insn);
584892a6 2595 macro_end ();
252b5132
RH
2596 }
2597 else
2598 {
2599 if (imm_expr.X_op != O_absent)
df58fc94 2600 append_insn (&insn, &imm_expr, imm_reloc, FALSE);
252b5132 2601 else if (offset_expr.X_op != O_absent)
df58fc94 2602 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
252b5132 2603 else
df58fc94 2604 append_insn (&insn, NULL, unused_reloc, FALSE);
252b5132
RH
2605 }
2606}
2607
738e5348
RS
2608/* Convenience functions for abstracting away the differences between
2609 MIPS16 and non-MIPS16 relocations. */
2610
2611static inline bfd_boolean
2612mips16_reloc_p (bfd_reloc_code_real_type reloc)
2613{
2614 switch (reloc)
2615 {
2616 case BFD_RELOC_MIPS16_JMP:
2617 case BFD_RELOC_MIPS16_GPREL:
2618 case BFD_RELOC_MIPS16_GOT16:
2619 case BFD_RELOC_MIPS16_CALL16:
2620 case BFD_RELOC_MIPS16_HI16_S:
2621 case BFD_RELOC_MIPS16_HI16:
2622 case BFD_RELOC_MIPS16_LO16:
2623 return TRUE;
2624
2625 default:
2626 return FALSE;
2627 }
2628}
2629
df58fc94
RS
2630static inline bfd_boolean
2631micromips_reloc_p (bfd_reloc_code_real_type reloc)
2632{
2633 switch (reloc)
2634 {
2635 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
2636 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
2637 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
2638 case BFD_RELOC_MICROMIPS_GPREL16:
2639 case BFD_RELOC_MICROMIPS_JMP:
2640 case BFD_RELOC_MICROMIPS_HI16:
2641 case BFD_RELOC_MICROMIPS_HI16_S:
2642 case BFD_RELOC_MICROMIPS_LO16:
2643 case BFD_RELOC_MICROMIPS_LITERAL:
2644 case BFD_RELOC_MICROMIPS_GOT16:
2645 case BFD_RELOC_MICROMIPS_CALL16:
2646 case BFD_RELOC_MICROMIPS_GOT_HI16:
2647 case BFD_RELOC_MICROMIPS_GOT_LO16:
2648 case BFD_RELOC_MICROMIPS_CALL_HI16:
2649 case BFD_RELOC_MICROMIPS_CALL_LO16:
2650 case BFD_RELOC_MICROMIPS_SUB:
2651 case BFD_RELOC_MICROMIPS_GOT_PAGE:
2652 case BFD_RELOC_MICROMIPS_GOT_OFST:
2653 case BFD_RELOC_MICROMIPS_GOT_DISP:
2654 case BFD_RELOC_MICROMIPS_HIGHEST:
2655 case BFD_RELOC_MICROMIPS_HIGHER:
2656 case BFD_RELOC_MICROMIPS_SCN_DISP:
2657 case BFD_RELOC_MICROMIPS_JALR:
2658 return TRUE;
2659
2660 default:
2661 return FALSE;
2662 }
2663}
2664
2309ddf2
MR
2665static inline bfd_boolean
2666jmp_reloc_p (bfd_reloc_code_real_type reloc)
2667{
2668 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
2669}
2670
738e5348
RS
2671static inline bfd_boolean
2672got16_reloc_p (bfd_reloc_code_real_type reloc)
2673{
2309ddf2 2674 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
df58fc94 2675 || reloc == BFD_RELOC_MICROMIPS_GOT16);
738e5348
RS
2676}
2677
2678static inline bfd_boolean
2679hi16_reloc_p (bfd_reloc_code_real_type reloc)
2680{
2309ddf2 2681 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
df58fc94 2682 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
738e5348
RS
2683}
2684
2685static inline bfd_boolean
2686lo16_reloc_p (bfd_reloc_code_real_type reloc)
2687{
2309ddf2 2688 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
df58fc94
RS
2689 || reloc == BFD_RELOC_MICROMIPS_LO16);
2690}
2691
df58fc94
RS
2692static inline bfd_boolean
2693jalr_reloc_p (bfd_reloc_code_real_type reloc)
2694{
2309ddf2 2695 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
738e5348
RS
2696}
2697
5919d012 2698/* Return true if the given relocation might need a matching %lo().
0a44bf69
RS
2699 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2700 need a matching %lo() when applied to local symbols. */
5919d012
RS
2701
2702static inline bfd_boolean
17a2f251 2703reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
5919d012 2704{
3b91255e 2705 return (HAVE_IN_PLACE_ADDENDS
738e5348 2706 && (hi16_reloc_p (reloc)
0a44bf69
RS
2707 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2708 all GOT16 relocations evaluate to "G". */
738e5348
RS
2709 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2710}
2711
2712/* Return the type of %lo() reloc needed by RELOC, given that
2713 reloc_needs_lo_p. */
2714
2715static inline bfd_reloc_code_real_type
2716matching_lo_reloc (bfd_reloc_code_real_type reloc)
2717{
df58fc94
RS
2718 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
2719 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
2720 : BFD_RELOC_LO16));
5919d012
RS
2721}
2722
2723/* Return true if the given fixup is followed by a matching R_MIPS_LO16
2724 relocation. */
2725
2726static inline bfd_boolean
17a2f251 2727fixup_has_matching_lo_p (fixS *fixp)
5919d012
RS
2728{
2729 return (fixp->fx_next != NULL
738e5348 2730 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
5919d012
RS
2731 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2732 && fixp->fx_offset == fixp->fx_next->fx_offset);
2733}
2734
252b5132
RH
2735/* This function returns true if modifying a register requires a
2736 delay. */
2737
2738static int
17a2f251 2739reg_needs_delay (unsigned int reg)
252b5132
RH
2740{
2741 unsigned long prev_pinfo;
2742
47e39b9d 2743 prev_pinfo = history[0].insn_mo->pinfo;
252b5132 2744 if (! mips_opts.noreorder
81912461
ILT
2745 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2746 && ! gpr_interlocks)
2747 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2748 && ! cop_interlocks)))
252b5132 2749 {
81912461
ILT
2750 /* A load from a coprocessor or from memory. All load delays
2751 delay the use of general register rt for one instruction. */
bdaaa2e1 2752 /* Itbl support may require additional care here. */
252b5132 2753 know (prev_pinfo & INSN_WRITE_GPR_T);
df58fc94 2754 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
252b5132
RH
2755 return 1;
2756 }
2757
2758 return 0;
2759}
2760
404a8071
RS
2761/* Move all labels in insn_labels to the current insertion point. */
2762
2763static void
2764mips_move_labels (void)
2765{
a8dbcb85 2766 segment_info_type *si = seg_info (now_seg);
404a8071
RS
2767 struct insn_label_list *l;
2768 valueT val;
2769
a8dbcb85 2770 for (l = si->label_list; l != NULL; l = l->next)
404a8071 2771 {
9c2799c2 2772 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
404a8071
RS
2773 symbol_set_frag (l->label, frag_now);
2774 val = (valueT) frag_now_fix ();
df58fc94
RS
2775 /* MIPS16/microMIPS text labels are stored as odd. */
2776 if (HAVE_CODE_COMPRESSION)
404a8071
RS
2777 ++val;
2778 S_SET_VALUE (l->label, val);
2779 }
2780}
2781
5f0fe04b
TS
2782static bfd_boolean
2783s_is_linkonce (symbolS *sym, segT from_seg)
2784{
2785 bfd_boolean linkonce = FALSE;
2786 segT symseg = S_GET_SEGMENT (sym);
2787
2788 if (symseg != from_seg && !S_IS_LOCAL (sym))
2789 {
2790 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2791 linkonce = TRUE;
2792#ifdef OBJ_ELF
2793 /* The GNU toolchain uses an extension for ELF: a section
2794 beginning with the magic string .gnu.linkonce is a
2795 linkonce section. */
2796 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2797 sizeof ".gnu.linkonce" - 1) == 0)
2798 linkonce = TRUE;
2799#endif
2800 }
2801 return linkonce;
2802}
2803
df58fc94
RS
2804/* Mark instruction labels in MIPS16/microMIPS mode. This permits the
2805 linker to handle them specially, such as generating jalx instructions
2806 when needed. We also make them odd for the duration of the assembly,
2807 in order to generate the right sort of code. We will make them even
252b5132
RH
2808 in the adjust_symtab routine, while leaving them marked. This is
2809 convenient for the debugger and the disassembler. The linker knows
2810 to make them odd again. */
2811
2812static void
df58fc94 2813mips_compressed_mark_labels (void)
252b5132 2814{
a8dbcb85
TS
2815 segment_info_type *si = seg_info (now_seg);
2816 struct insn_label_list *l;
252b5132 2817
df58fc94 2818 gas_assert (HAVE_CODE_COMPRESSION);
a8dbcb85
TS
2819
2820 for (l = si->label_list; l != NULL; l = l->next)
2821 {
2822 symbolS *label = l->label;
2823
2824#if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
f43abd2b 2825 if (IS_ELF)
df58fc94
RS
2826 {
2827 if (mips_opts.mips16)
2828 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2829 else
2830 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
2831 }
252b5132 2832#endif
5f0fe04b
TS
2833 if ((S_GET_VALUE (label) & 1) == 0
2834 /* Don't adjust the address if the label is global or weak, or
2835 in a link-once section, since we'll be emitting symbol reloc
2836 references to it which will be patched up by the linker, and
df58fc94 2837 the final value of the symbol may or may not be MIPS16/microMIPS. */
5f0fe04b
TS
2838 && ! S_IS_WEAK (label)
2839 && ! S_IS_EXTERNAL (label)
2840 && ! s_is_linkonce (label, now_seg))
a8dbcb85 2841 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
252b5132
RH
2842 }
2843}
2844
4d7206a2
RS
2845/* End the current frag. Make it a variant frag and record the
2846 relaxation info. */
2847
2848static void
2849relax_close_frag (void)
2850{
584892a6 2851 mips_macro_warning.first_frag = frag_now;
4d7206a2 2852 frag_var (rs_machine_dependent, 0, 0,
584892a6 2853 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
4d7206a2
RS
2854 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2855
2856 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2857 mips_relax.first_fixup = 0;
2858}
2859
2860/* Start a new relaxation sequence whose expansion depends on SYMBOL.
2861 See the comment above RELAX_ENCODE for more details. */
2862
2863static void
2864relax_start (symbolS *symbol)
2865{
9c2799c2 2866 gas_assert (mips_relax.sequence == 0);
4d7206a2
RS
2867 mips_relax.sequence = 1;
2868 mips_relax.symbol = symbol;
2869}
2870
2871/* Start generating the second version of a relaxable sequence.
2872 See the comment above RELAX_ENCODE for more details. */
252b5132
RH
2873
2874static void
4d7206a2
RS
2875relax_switch (void)
2876{
9c2799c2 2877 gas_assert (mips_relax.sequence == 1);
4d7206a2
RS
2878 mips_relax.sequence = 2;
2879}
2880
2881/* End the current relaxable sequence. */
2882
2883static void
2884relax_end (void)
2885{
9c2799c2 2886 gas_assert (mips_relax.sequence == 2);
4d7206a2
RS
2887 relax_close_frag ();
2888 mips_relax.sequence = 0;
2889}
2890
2309ddf2 2891/* Return the mask of core registers that IP reads or writes. */
df58fc94
RS
2892
2893static unsigned int
2894gpr_mod_mask (const struct mips_cl_insn *ip)
2895{
2309ddf2 2896 unsigned long pinfo2;
df58fc94
RS
2897 unsigned int mask;
2898
2899 mask = 0;
df58fc94
RS
2900 pinfo2 = ip->insn_mo->pinfo2;
2901 if (mips_opts.micromips)
2902 {
2903 if (pinfo2 & INSN2_MOD_GPR_MB)
2904 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
2905 if (pinfo2 & INSN2_MOD_GPR_MC)
2906 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
2907 if (pinfo2 & INSN2_MOD_GPR_MD)
2908 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
2909 if (pinfo2 & INSN2_MOD_GPR_ME)
2910 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
2911 if (pinfo2 & INSN2_MOD_GPR_MF)
2912 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
2913 if (pinfo2 & INSN2_MOD_GPR_MG)
2914 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
2915 if (pinfo2 & INSN2_MOD_GPR_MHI)
2916 {
2917 mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)];
2918 mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)];
2919 }
2920 if (pinfo2 & INSN2_MOD_GPR_MJ)
2921 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
2922 if (pinfo2 & INSN2_MOD_GPR_MM)
2923 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
2924 if (pinfo2 & INSN2_MOD_GPR_MN)
2925 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
2926 if (pinfo2 & INSN2_MOD_GPR_MP)
2927 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
2928 if (pinfo2 & INSN2_MOD_GPR_MQ)
2929 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
2930 if (pinfo2 & INSN2_MOD_SP)
2931 mask |= 1 << SP;
2932 }
2933 return mask;
2934}
2935
4c260379
RS
2936/* Return the mask of core registers that IP reads. */
2937
2938static unsigned int
2939gpr_read_mask (const struct mips_cl_insn *ip)
2940{
2941 unsigned long pinfo, pinfo2;
2942 unsigned int mask;
2943
df58fc94 2944 mask = gpr_mod_mask (ip);
4c260379
RS
2945 pinfo = ip->insn_mo->pinfo;
2946 pinfo2 = ip->insn_mo->pinfo2;
2947 if (mips_opts.mips16)
2948 {
2949 if (pinfo & MIPS16_INSN_READ_X)
2950 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2951 if (pinfo & MIPS16_INSN_READ_Y)
2952 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
2953 if (pinfo & MIPS16_INSN_READ_T)
2954 mask |= 1 << TREG;
2955 if (pinfo & MIPS16_INSN_READ_SP)
2956 mask |= 1 << SP;
2957 if (pinfo & MIPS16_INSN_READ_31)
2958 mask |= 1 << RA;
2959 if (pinfo & MIPS16_INSN_READ_Z)
2960 mask |= 1 << (mips16_to_32_reg_map
2961 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
2962 if (pinfo & MIPS16_INSN_READ_GPR_X)
2963 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
2964 }
2965 else
2966 {
2967 if (pinfo2 & INSN2_READ_GPR_D)
2309ddf2 2968 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4c260379 2969 if (pinfo & INSN_READ_GPR_T)
2309ddf2 2970 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
4c260379 2971 if (pinfo & INSN_READ_GPR_S)
2309ddf2
MR
2972 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
2973 if (pinfo2 & INSN2_READ_GP)
2974 mask |= 1 << GP;
2975 if (pinfo2 & INSN2_READ_GPR_31)
2976 mask |= 1 << RA;
4c260379 2977 if (pinfo2 & INSN2_READ_GPR_Z)
2309ddf2 2978 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
4c260379 2979 }
fe35f09f
RS
2980 /* Don't include register 0. */
2981 return mask & ~1;
4c260379
RS
2982}
2983
2984/* Return the mask of core registers that IP writes. */
2985
2986static unsigned int
2987gpr_write_mask (const struct mips_cl_insn *ip)
2988{
2989 unsigned long pinfo, pinfo2;
2990 unsigned int mask;
2991
df58fc94 2992 mask = gpr_mod_mask (ip);
4c260379
RS
2993 pinfo = ip->insn_mo->pinfo;
2994 pinfo2 = ip->insn_mo->pinfo2;
2995 if (mips_opts.mips16)
2996 {
2997 if (pinfo & MIPS16_INSN_WRITE_X)
2998 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2999 if (pinfo & MIPS16_INSN_WRITE_Y)
3000 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3001 if (pinfo & MIPS16_INSN_WRITE_Z)
3002 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3003 if (pinfo & MIPS16_INSN_WRITE_T)
3004 mask |= 1 << TREG;
3005 if (pinfo & MIPS16_INSN_WRITE_SP)
3006 mask |= 1 << SP;
3007 if (pinfo & MIPS16_INSN_WRITE_31)
3008 mask |= 1 << RA;
3009 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3010 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3011 }
3012 else
3013 {
3014 if (pinfo & INSN_WRITE_GPR_D)
df58fc94 3015 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4c260379 3016 if (pinfo & INSN_WRITE_GPR_T)
df58fc94 3017 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
2309ddf2
MR
3018 if (pinfo2 & INSN2_WRITE_GPR_S)
3019 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
4c260379
RS
3020 if (pinfo & INSN_WRITE_GPR_31)
3021 mask |= 1 << RA;
3022 if (pinfo2 & INSN2_WRITE_GPR_Z)
df58fc94 3023 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
4c260379 3024 }
fe35f09f
RS
3025 /* Don't include register 0. */
3026 return mask & ~1;
4c260379
RS
3027}
3028
3029/* Return the mask of floating-point registers that IP reads. */
3030
3031static unsigned int
3032fpr_read_mask (const struct mips_cl_insn *ip)
3033{
3034 unsigned long pinfo, pinfo2;
3035 unsigned int mask;
3036
3037 mask = 0;
3038 pinfo = ip->insn_mo->pinfo;
3039 pinfo2 = ip->insn_mo->pinfo2;
2309ddf2 3040 if (!mips_opts.mips16)
df58fc94
RS
3041 {
3042 if (pinfo2 & INSN2_READ_FPR_D)
2309ddf2 3043 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
4c260379 3044 if (pinfo & INSN_READ_FPR_S)
df58fc94 3045 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
4c260379 3046 if (pinfo & INSN_READ_FPR_T)
df58fc94 3047 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
4c260379 3048 if (pinfo & INSN_READ_FPR_R)
df58fc94 3049 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
4c260379 3050 if (pinfo2 & INSN2_READ_FPR_Z)
df58fc94 3051 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
4c260379
RS
3052 }
3053 /* Conservatively treat all operands to an FP_D instruction are doubles.
3054 (This is overly pessimistic for things like cvt.d.s.) */
3055 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3056 mask |= mask << 1;
3057 return mask;
3058}
3059
3060/* Return the mask of floating-point registers that IP writes. */
3061
3062static unsigned int
3063fpr_write_mask (const struct mips_cl_insn *ip)
3064{
3065 unsigned long pinfo, pinfo2;
3066 unsigned int mask;
3067
3068 mask = 0;
3069 pinfo = ip->insn_mo->pinfo;
3070 pinfo2 = ip->insn_mo->pinfo2;
2309ddf2 3071 if (!mips_opts.mips16)
4c260379
RS
3072 {
3073 if (pinfo & INSN_WRITE_FPR_D)
df58fc94 3074 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
4c260379 3075 if (pinfo & INSN_WRITE_FPR_S)
df58fc94 3076 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
4c260379 3077 if (pinfo & INSN_WRITE_FPR_T)
df58fc94 3078 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
4c260379 3079 if (pinfo2 & INSN2_WRITE_FPR_Z)
df58fc94 3080 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
4c260379
RS
3081 }
3082 /* Conservatively treat all operands to an FP_D instruction are doubles.
3083 (This is overly pessimistic for things like cvt.s.d.) */
3084 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3085 mask |= mask << 1;
3086 return mask;
3087}
3088
71400594
RS
3089/* Classify an instruction according to the FIX_VR4120_* enumeration.
3090 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3091 by VR4120 errata. */
4d7206a2 3092
71400594
RS
3093static unsigned int
3094classify_vr4120_insn (const char *name)
252b5132 3095{
71400594
RS
3096 if (strncmp (name, "macc", 4) == 0)
3097 return FIX_VR4120_MACC;
3098 if (strncmp (name, "dmacc", 5) == 0)
3099 return FIX_VR4120_DMACC;
3100 if (strncmp (name, "mult", 4) == 0)
3101 return FIX_VR4120_MULT;
3102 if (strncmp (name, "dmult", 5) == 0)
3103 return FIX_VR4120_DMULT;
3104 if (strstr (name, "div"))
3105 return FIX_VR4120_DIV;
3106 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
3107 return FIX_VR4120_MTHILO;
3108 return NUM_FIX_VR4120_CLASSES;
3109}
252b5132 3110
ff239038
CM
3111#define INSN_ERET 0x42000018
3112#define INSN_DERET 0x4200001f
3113
71400594
RS
3114/* Return the number of instructions that must separate INSN1 and INSN2,
3115 where INSN1 is the earlier instruction. Return the worst-case value
3116 for any INSN2 if INSN2 is null. */
252b5132 3117
71400594
RS
3118static unsigned int
3119insns_between (const struct mips_cl_insn *insn1,
3120 const struct mips_cl_insn *insn2)
3121{
3122 unsigned long pinfo1, pinfo2;
4c260379 3123 unsigned int mask;
71400594
RS
3124
3125 /* This function needs to know which pinfo flags are set for INSN2
3126 and which registers INSN2 uses. The former is stored in PINFO2 and
4c260379
RS
3127 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3128 will have every flag set and INSN2_USES_GPR will always return true. */
71400594
RS
3129 pinfo1 = insn1->insn_mo->pinfo;
3130 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
252b5132 3131
4c260379
RS
3132#define INSN2_USES_GPR(REG) \
3133 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
71400594
RS
3134
3135 /* For most targets, write-after-read dependencies on the HI and LO
3136 registers must be separated by at least two instructions. */
3137 if (!hilo_interlocks)
252b5132 3138 {
71400594
RS
3139 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
3140 return 2;
3141 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
3142 return 2;
3143 }
3144
3145 /* If we're working around r7000 errata, there must be two instructions
3146 between an mfhi or mflo and any instruction that uses the result. */
3147 if (mips_7000_hilo_fix
df58fc94 3148 && !mips_opts.micromips
71400594 3149 && MF_HILO_INSN (pinfo1)
df58fc94 3150 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
71400594
RS
3151 return 2;
3152
ff239038
CM
3153 /* If we're working around 24K errata, one instruction is required
3154 if an ERET or DERET is followed by a branch instruction. */
df58fc94 3155 if (mips_fix_24k && !mips_opts.micromips)
ff239038
CM
3156 {
3157 if (insn1->insn_opcode == INSN_ERET
3158 || insn1->insn_opcode == INSN_DERET)
3159 {
3160 if (insn2 == NULL
3161 || insn2->insn_opcode == INSN_ERET
3162 || insn2->insn_opcode == INSN_DERET
3163 || (insn2->insn_mo->pinfo
3164 & (INSN_UNCOND_BRANCH_DELAY
3165 | INSN_COND_BRANCH_DELAY
3166 | INSN_COND_BRANCH_LIKELY)) != 0)
3167 return 1;
3168 }
3169 }
3170
71400594
RS
3171 /* If working around VR4120 errata, check for combinations that need
3172 a single intervening instruction. */
df58fc94 3173 if (mips_fix_vr4120 && !mips_opts.micromips)
71400594
RS
3174 {
3175 unsigned int class1, class2;
252b5132 3176
71400594
RS
3177 class1 = classify_vr4120_insn (insn1->insn_mo->name);
3178 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
252b5132 3179 {
71400594
RS
3180 if (insn2 == NULL)
3181 return 1;
3182 class2 = classify_vr4120_insn (insn2->insn_mo->name);
3183 if (vr4120_conflicts[class1] & (1 << class2))
3184 return 1;
252b5132 3185 }
71400594
RS
3186 }
3187
df58fc94 3188 if (!HAVE_CODE_COMPRESSION)
71400594
RS
3189 {
3190 /* Check for GPR or coprocessor load delays. All such delays
3191 are on the RT register. */
3192 /* Itbl support may require additional care here. */
3193 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
3194 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
252b5132 3195 {
71400594 3196 know (pinfo1 & INSN_WRITE_GPR_T);
df58fc94 3197 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
71400594
RS
3198 return 1;
3199 }
3200
3201 /* Check for generic coprocessor hazards.
3202
3203 This case is not handled very well. There is no special
3204 knowledge of CP0 handling, and the coprocessors other than
3205 the floating point unit are not distinguished at all. */
3206 /* Itbl support may require additional care here. FIXME!
3207 Need to modify this to include knowledge about
3208 user specified delays! */
3209 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
3210 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
3211 {
3212 /* Handle cases where INSN1 writes to a known general coprocessor
3213 register. There must be a one instruction delay before INSN2
3214 if INSN2 reads that register, otherwise no delay is needed. */
4c260379
RS
3215 mask = fpr_write_mask (insn1);
3216 if (mask != 0)
252b5132 3217 {
4c260379 3218 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
71400594 3219 return 1;
252b5132
RH
3220 }
3221 else
3222 {
71400594
RS
3223 /* Read-after-write dependencies on the control registers
3224 require a two-instruction gap. */
3225 if ((pinfo1 & INSN_WRITE_COND_CODE)
3226 && (pinfo2 & INSN_READ_COND_CODE))
3227 return 2;
3228
3229 /* We don't know exactly what INSN1 does. If INSN2 is
3230 also a coprocessor instruction, assume there must be
3231 a one instruction gap. */
3232 if (pinfo2 & INSN_COP)
3233 return 1;
252b5132
RH
3234 }
3235 }
6b76fefe 3236
71400594
RS
3237 /* Check for read-after-write dependencies on the coprocessor
3238 control registers in cases where INSN1 does not need a general
3239 coprocessor delay. This means that INSN1 is a floating point
3240 comparison instruction. */
3241 /* Itbl support may require additional care here. */
3242 else if (!cop_interlocks
3243 && (pinfo1 & INSN_WRITE_COND_CODE)
3244 && (pinfo2 & INSN_READ_COND_CODE))
3245 return 1;
3246 }
6b76fefe 3247
4c260379 3248#undef INSN2_USES_GPR
6b76fefe 3249
71400594
RS
3250 return 0;
3251}
6b76fefe 3252
7d8e00cf
RS
3253/* Return the number of nops that would be needed to work around the
3254 VR4130 mflo/mfhi errata if instruction INSN immediately followed
932d1a1b
RS
3255 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3256 that are contained within the first IGNORE instructions of HIST. */
7d8e00cf
RS
3257
3258static int
932d1a1b 3259nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
7d8e00cf
RS
3260 const struct mips_cl_insn *insn)
3261{
4c260379
RS
3262 int i, j;
3263 unsigned int mask;
7d8e00cf
RS
3264
3265 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3266 are not affected by the errata. */
3267 if (insn != 0
3268 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
3269 || strcmp (insn->insn_mo->name, "mtlo") == 0
3270 || strcmp (insn->insn_mo->name, "mthi") == 0))
3271 return 0;
3272
3273 /* Search for the first MFLO or MFHI. */
3274 for (i = 0; i < MAX_VR4130_NOPS; i++)
91d6fa6a 3275 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
7d8e00cf
RS
3276 {
3277 /* Extract the destination register. */
4c260379 3278 mask = gpr_write_mask (&hist[i]);
7d8e00cf
RS
3279
3280 /* No nops are needed if INSN reads that register. */
4c260379 3281 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
7d8e00cf
RS
3282 return 0;
3283
3284 /* ...or if any of the intervening instructions do. */
3285 for (j = 0; j < i; j++)
4c260379 3286 if (gpr_read_mask (&hist[j]) & mask)
7d8e00cf
RS
3287 return 0;
3288
932d1a1b
RS
3289 if (i >= ignore)
3290 return MAX_VR4130_NOPS - i;
7d8e00cf
RS
3291 }
3292 return 0;
3293}
3294
15be625d
CM
3295#define BASE_REG_EQ(INSN1, INSN2) \
3296 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3297 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3298
3299/* Return the minimum alignment for this store instruction. */
3300
3301static int
3302fix_24k_align_to (const struct mips_opcode *mo)
3303{
3304 if (strcmp (mo->name, "sh") == 0)
3305 return 2;
3306
3307 if (strcmp (mo->name, "swc1") == 0
3308 || strcmp (mo->name, "swc2") == 0
3309 || strcmp (mo->name, "sw") == 0
3310 || strcmp (mo->name, "sc") == 0
3311 || strcmp (mo->name, "s.s") == 0)
3312 return 4;
3313
3314 if (strcmp (mo->name, "sdc1") == 0
3315 || strcmp (mo->name, "sdc2") == 0
3316 || strcmp (mo->name, "s.d") == 0)
3317 return 8;
3318
3319 /* sb, swl, swr */
3320 return 1;
3321}
3322
3323struct fix_24k_store_info
3324 {
3325 /* Immediate offset, if any, for this store instruction. */
3326 short off;
3327 /* Alignment required by this store instruction. */
3328 int align_to;
3329 /* True for register offsets. */
3330 int register_offset;
3331 };
3332
3333/* Comparison function used by qsort. */
3334
3335static int
3336fix_24k_sort (const void *a, const void *b)
3337{
3338 const struct fix_24k_store_info *pos1 = a;
3339 const struct fix_24k_store_info *pos2 = b;
3340
3341 return (pos1->off - pos2->off);
3342}
3343
3344/* INSN is a store instruction. Try to record the store information
3345 in STINFO. Return false if the information isn't known. */
3346
3347static bfd_boolean
3348fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
ab9794cf 3349 const struct mips_cl_insn *insn)
15be625d
CM
3350{
3351 /* The instruction must have a known offset. */
3352 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
3353 return FALSE;
3354
3355 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
3356 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
3357 return TRUE;
3358}
3359
932d1a1b
RS
3360/* Return the number of nops that would be needed to work around the 24k
3361 "lost data on stores during refill" errata if instruction INSN
3362 immediately followed the 2 instructions described by HIST.
3363 Ignore hazards that are contained within the first IGNORE
3364 instructions of HIST.
3365
3366 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3367 for the data cache refills and store data. The following describes
3368 the scenario where the store data could be lost.
3369
3370 * A data cache miss, due to either a load or a store, causing fill
3371 data to be supplied by the memory subsystem
3372 * The first three doublewords of fill data are returned and written
3373 into the cache
3374 * A sequence of four stores occurs in consecutive cycles around the
3375 final doubleword of the fill:
3376 * Store A
3377 * Store B
3378 * Store C
3379 * Zero, One or more instructions
3380 * Store D
3381
3382 The four stores A-D must be to different doublewords of the line that
3383 is being filled. The fourth instruction in the sequence above permits
3384 the fill of the final doubleword to be transferred from the FSB into
3385 the cache. In the sequence above, the stores may be either integer
3386 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3387 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3388 different doublewords on the line. If the floating point unit is
3389 running in 1:2 mode, it is not possible to create the sequence above
3390 using only floating point store instructions.
15be625d
CM
3391
3392 In this case, the cache line being filled is incorrectly marked
3393 invalid, thereby losing the data from any store to the line that
3394 occurs between the original miss and the completion of the five
3395 cycle sequence shown above.
3396
932d1a1b 3397 The workarounds are:
15be625d 3398
932d1a1b
RS
3399 * Run the data cache in write-through mode.
3400 * Insert a non-store instruction between
3401 Store A and Store B or Store B and Store C. */
15be625d
CM
3402
3403static int
932d1a1b 3404nops_for_24k (int ignore, const struct mips_cl_insn *hist,
15be625d
CM
3405 const struct mips_cl_insn *insn)
3406{
3407 struct fix_24k_store_info pos[3];
3408 int align, i, base_offset;
3409
932d1a1b
RS
3410 if (ignore >= 2)
3411 return 0;
3412
ab9794cf
RS
3413 /* If the previous instruction wasn't a store, there's nothing to
3414 worry about. */
15be625d
CM
3415 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3416 return 0;
3417
ab9794cf
RS
3418 /* If the instructions after the previous one are unknown, we have
3419 to assume the worst. */
3420 if (!insn)
15be625d
CM
3421 return 1;
3422
ab9794cf
RS
3423 /* Check whether we are dealing with three consecutive stores. */
3424 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
3425 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
15be625d
CM
3426 return 0;
3427
3428 /* If we don't know the relationship between the store addresses,
3429 assume the worst. */
ab9794cf 3430 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
15be625d
CM
3431 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
3432 return 1;
3433
3434 if (!fix_24k_record_store_info (&pos[0], insn)
3435 || !fix_24k_record_store_info (&pos[1], &hist[0])
3436 || !fix_24k_record_store_info (&pos[2], &hist[1]))
3437 return 1;
3438
3439 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
3440
3441 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3442 X bytes and such that the base register + X is known to be aligned
3443 to align bytes. */
3444
3445 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
3446 align = 8;
3447 else
3448 {
3449 align = pos[0].align_to;
3450 base_offset = pos[0].off;
3451 for (i = 1; i < 3; i++)
3452 if (align < pos[i].align_to)
3453 {
3454 align = pos[i].align_to;
3455 base_offset = pos[i].off;
3456 }
3457 for (i = 0; i < 3; i++)
3458 pos[i].off -= base_offset;
3459 }
3460
3461 pos[0].off &= ~align + 1;
3462 pos[1].off &= ~align + 1;
3463 pos[2].off &= ~align + 1;
3464
3465 /* If any two stores write to the same chunk, they also write to the
3466 same doubleword. The offsets are still sorted at this point. */
3467 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
3468 return 0;
3469
3470 /* A range of at least 9 bytes is needed for the stores to be in
3471 non-overlapping doublewords. */
3472 if (pos[2].off - pos[0].off <= 8)
3473 return 0;
3474
3475 if (pos[2].off - pos[1].off >= 24
3476 || pos[1].off - pos[0].off >= 24
3477 || pos[2].off - pos[0].off >= 32)
3478 return 0;
3479
3480 return 1;
3481}
3482
71400594 3483/* Return the number of nops that would be needed if instruction INSN
91d6fa6a 3484 immediately followed the MAX_NOPS instructions given by HIST,
932d1a1b
RS
3485 where HIST[0] is the most recent instruction. Ignore hazards
3486 between INSN and the first IGNORE instructions in HIST.
3487
3488 If INSN is null, return the worse-case number of nops for any
3489 instruction. */
bdaaa2e1 3490
71400594 3491static int
932d1a1b 3492nops_for_insn (int ignore, const struct mips_cl_insn *hist,
71400594
RS
3493 const struct mips_cl_insn *insn)
3494{
3495 int i, nops, tmp_nops;
bdaaa2e1 3496
71400594 3497 nops = 0;
932d1a1b 3498 for (i = ignore; i < MAX_DELAY_NOPS; i++)
65b02341 3499 {
91d6fa6a 3500 tmp_nops = insns_between (hist + i, insn) - i;
65b02341
RS
3501 if (tmp_nops > nops)
3502 nops = tmp_nops;
3503 }
7d8e00cf 3504
df58fc94 3505 if (mips_fix_vr4130 && !mips_opts.micromips)
7d8e00cf 3506 {
932d1a1b 3507 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
7d8e00cf
RS
3508 if (tmp_nops > nops)
3509 nops = tmp_nops;
3510 }
3511
df58fc94 3512 if (mips_fix_24k && !mips_opts.micromips)
15be625d 3513 {
932d1a1b 3514 tmp_nops = nops_for_24k (ignore, hist, insn);
15be625d
CM
3515 if (tmp_nops > nops)
3516 nops = tmp_nops;
3517 }
3518
71400594
RS
3519 return nops;
3520}
252b5132 3521
71400594 3522/* The variable arguments provide NUM_INSNS extra instructions that
91d6fa6a 3523 might be added to HIST. Return the largest number of nops that
932d1a1b
RS
3524 would be needed after the extended sequence, ignoring hazards
3525 in the first IGNORE instructions. */
252b5132 3526
71400594 3527static int
932d1a1b
RS
3528nops_for_sequence (int num_insns, int ignore,
3529 const struct mips_cl_insn *hist, ...)
71400594
RS
3530{
3531 va_list args;
3532 struct mips_cl_insn buffer[MAX_NOPS];
3533 struct mips_cl_insn *cursor;
3534 int nops;
3535
91d6fa6a 3536 va_start (args, hist);
71400594 3537 cursor = buffer + num_insns;
91d6fa6a 3538 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
71400594
RS
3539 while (cursor > buffer)
3540 *--cursor = *va_arg (args, const struct mips_cl_insn *);
3541
932d1a1b 3542 nops = nops_for_insn (ignore, buffer, NULL);
71400594
RS
3543 va_end (args);
3544 return nops;
3545}
252b5132 3546
71400594
RS
3547/* Like nops_for_insn, but if INSN is a branch, take into account the
3548 worst-case delay for the branch target. */
252b5132 3549
71400594 3550static int
932d1a1b 3551nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
71400594
RS
3552 const struct mips_cl_insn *insn)
3553{
3554 int nops, tmp_nops;
60b63b72 3555
932d1a1b 3556 nops = nops_for_insn (ignore, hist, insn);
71400594
RS
3557 if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3558 | INSN_COND_BRANCH_DELAY
3559 | INSN_COND_BRANCH_LIKELY))
3560 {
932d1a1b
RS
3561 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3562 hist, insn, NOP_INSN);
71400594
RS
3563 if (tmp_nops > nops)
3564 nops = tmp_nops;
3565 }
9a2c7088
MR
3566 else if (mips_opts.mips16
3567 && (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
3568 | MIPS16_INSN_COND_BRANCH)))
71400594 3569 {
932d1a1b 3570 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
71400594
RS
3571 if (tmp_nops > nops)
3572 nops = tmp_nops;
3573 }
3574 return nops;
3575}
3576
c67a084a
NC
3577/* Fix NOP issue: Replace nops by "or at,at,zero". */
3578
3579static void
3580fix_loongson2f_nop (struct mips_cl_insn * ip)
3581{
df58fc94 3582 gas_assert (!HAVE_CODE_COMPRESSION);
c67a084a
NC
3583 if (strcmp (ip->insn_mo->name, "nop") == 0)
3584 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3585}
3586
3587/* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3588 jr target pc &= 'hffff_ffff_cfff_ffff. */
3589
3590static void
3591fix_loongson2f_jump (struct mips_cl_insn * ip)
3592{
df58fc94 3593 gas_assert (!HAVE_CODE_COMPRESSION);
c67a084a
NC
3594 if (strcmp (ip->insn_mo->name, "j") == 0
3595 || strcmp (ip->insn_mo->name, "jr") == 0
3596 || strcmp (ip->insn_mo->name, "jalr") == 0)
3597 {
3598 int sreg;
3599 expressionS ep;
3600
3601 if (! mips_opts.at)
3602 return;
3603
df58fc94 3604 sreg = EXTRACT_OPERAND (0, RS, *ip);
c67a084a
NC
3605 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3606 return;
3607
3608 ep.X_op = O_constant;
3609 ep.X_add_number = 0xcfff0000;
3610 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3611 ep.X_add_number = 0xffff;
3612 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3613 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3614 }
3615}
3616
3617static void
3618fix_loongson2f (struct mips_cl_insn * ip)
3619{
3620 if (mips_fix_loongson2f_nop)
3621 fix_loongson2f_nop (ip);
3622
3623 if (mips_fix_loongson2f_jump)
3624 fix_loongson2f_jump (ip);
3625}
3626
a4e06468
RS
3627/* IP is a branch that has a delay slot, and we need to fill it
3628 automatically. Return true if we can do that by swapping IP
3629 with the previous instruction. */
3630
3631static bfd_boolean
3632can_swap_branch_p (struct mips_cl_insn *ip)
3633{
df58fc94 3634 unsigned long pinfo, pinfo2, prev_pinfo;
a4e06468
RS
3635 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
3636
df58fc94
RS
3637 /* For microMIPS, disable reordering. */
3638 if (mips_opts.micromips)
3639 return FALSE;
3640
a4e06468
RS
3641 /* -O2 and above is required for this optimization. */
3642 if (mips_optimize < 2)
3643 return FALSE;
3644
3645 /* If we have seen .set volatile or .set nomove, don't optimize. */
3646 if (mips_opts.nomove)
3647 return FALSE;
3648
3649 /* We can't swap if the previous instruction's position is fixed. */
3650 if (history[0].fixed_p)
3651 return FALSE;
3652
3653 /* If the previous previous insn was in a .set noreorder, we can't
3654 swap. Actually, the MIPS assembler will swap in this situation.
3655 However, gcc configured -with-gnu-as will generate code like
3656
3657 .set noreorder
3658 lw $4,XXX
3659 .set reorder
3660 INSN
3661 bne $4,$0,foo
3662
3663 in which we can not swap the bne and INSN. If gcc is not configured
3664 -with-gnu-as, it does not output the .set pseudo-ops. */
3665 if (history[1].noreorder_p)
3666 return FALSE;
3667
3668 /* If the previous instruction had a fixup in mips16 mode, we can not
3669 swap. This normally means that the previous instruction was a 4
3670 byte branch anyhow. */
3671 if (mips_opts.mips16 && history[0].fixp[0])
3672 return FALSE;
3673
3674 /* If the branch is itself the target of a branch, we can not swap.
3675 We cheat on this; all we check for is whether there is a label on
3676 this instruction. If there are any branches to anything other than
3677 a label, users must use .set noreorder. */
3678 if (seg_info (now_seg)->label_list)
3679 return FALSE;
3680
3681 /* If the previous instruction is in a variant frag other than this
2309ddf2
MR
3682 branch's one, we cannot do the swap. This does not apply to
3683 MIPS16/microMIPS code, which uses variant frags for different
3684 purposes. */
df58fc94 3685 if (!HAVE_CODE_COMPRESSION
a4e06468
RS
3686 && history[0].frag
3687 && history[0].frag->fr_type == rs_machine_dependent)
3688 return FALSE;
3689
bcd530a7
RS
3690 /* We do not swap with instructions that cannot architecturally
3691 be placed in a branch delay slot, such as SYNC or ERET. We
3692 also refrain from swapping with a trap instruction, since it
3693 complicates trap handlers to have the trap instruction be in
3694 a delay slot. */
a4e06468 3695 prev_pinfo = history[0].insn_mo->pinfo;
bcd530a7 3696 if (prev_pinfo & INSN_NO_DELAY_SLOT)
a4e06468
RS
3697 return FALSE;
3698
3699 /* Check for conflicts between the branch and the instructions
3700 before the candidate delay slot. */
3701 if (nops_for_insn (0, history + 1, ip) > 0)
3702 return FALSE;
3703
3704 /* Check for conflicts between the swapped sequence and the
3705 target of the branch. */
3706 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
3707 return FALSE;
3708
3709 /* If the branch reads a register that the previous
3710 instruction sets, we can not swap. */
3711 gpr_read = gpr_read_mask (ip);
3712 prev_gpr_write = gpr_write_mask (&history[0]);
3713 if (gpr_read & prev_gpr_write)
3714 return FALSE;
3715
3716 /* If the branch writes a register that the previous
3717 instruction sets, we can not swap. */
3718 gpr_write = gpr_write_mask (ip);
3719 if (gpr_write & prev_gpr_write)
3720 return FALSE;
3721
3722 /* If the branch writes a register that the previous
3723 instruction reads, we can not swap. */
3724 prev_gpr_read = gpr_read_mask (&history[0]);
3725 if (gpr_write & prev_gpr_read)
3726 return FALSE;
3727
3728 /* If one instruction sets a condition code and the
3729 other one uses a condition code, we can not swap. */
3730 pinfo = ip->insn_mo->pinfo;
3731 if ((pinfo & INSN_READ_COND_CODE)
3732 && (prev_pinfo & INSN_WRITE_COND_CODE))
3733 return FALSE;
3734 if ((pinfo & INSN_WRITE_COND_CODE)
3735 && (prev_pinfo & INSN_READ_COND_CODE))
3736 return FALSE;
3737
3738 /* If the previous instruction uses the PC, we can not swap. */
3739 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
3740 return FALSE;
3741
df58fc94
RS
3742 /* If the previous instruction has an incorrect size for a fixed
3743 branch delay slot in microMIPS mode, we cannot swap. */
2309ddf2
MR
3744 pinfo2 = ip->insn_mo->pinfo2;
3745 if (mips_opts.micromips
3746 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
3747 && insn_length (history) != 2)
3748 return FALSE;
3749 if (mips_opts.micromips
3750 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
3751 && insn_length (history) != 4)
3752 return FALSE;
3753
a4e06468
RS
3754 return TRUE;
3755}
3756
3757/* Decide how we should add IP to the instruction stream. */
3758
3759static enum append_method
3760get_append_method (struct mips_cl_insn *ip)
3761{
3762 unsigned long pinfo;
3763
3764 /* The relaxed version of a macro sequence must be inherently
3765 hazard-free. */
3766 if (mips_relax.sequence == 2)
3767 return APPEND_ADD;
3768
3769 /* We must not dabble with instructions in a ".set norerorder" block. */
3770 if (mips_opts.noreorder)
3771 return APPEND_ADD;
3772
3773 /* Otherwise, it's our responsibility to fill branch delay slots. */
3774 pinfo = ip->insn_mo->pinfo;
3775 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
3776 || (pinfo & INSN_COND_BRANCH_DELAY))
3777 {
3778 if (can_swap_branch_p (ip))
3779 return APPEND_SWAP;
3780
3781 if (mips_opts.mips16
3782 && ISA_SUPPORTS_MIPS16E
3783 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
3784 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
3785 return APPEND_ADD_COMPACT;
3786
3787 return APPEND_ADD_WITH_NOP;
3788 }
3789
3790 /* We don't bother trying to track the target of branches, so there's
3791 nothing we can use to fill a branch-likely slot. */
3792 if (pinfo & INSN_COND_BRANCH_LIKELY)
3793 return APPEND_ADD_WITH_NOP;
3794
3795 return APPEND_ADD;
3796}
3797
ceb94aa5
RS
3798/* IP is a MIPS16 instruction whose opcode we have just changed.
3799 Point IP->insn_mo to the new opcode's definition. */
3800
3801static void
3802find_altered_mips16_opcode (struct mips_cl_insn *ip)
3803{
3804 const struct mips_opcode *mo, *end;
3805
3806 end = &mips16_opcodes[bfd_mips16_num_opcodes];
3807 for (mo = ip->insn_mo; mo < end; mo++)
3808 if ((ip->insn_opcode & mo->mask) == mo->match)
3809 {
3810 ip->insn_mo = mo;
3811 return;
3812 }
3813 abort ();
3814}
3815
df58fc94
RS
3816/* For microMIPS macros, we need to generate a local number label
3817 as the target of branches. */
3818#define MICROMIPS_LABEL_CHAR '\037'
3819static unsigned long micromips_target_label;
3820static char micromips_target_name[32];
3821
3822static char *
3823micromips_label_name (void)
3824{
3825 char *p = micromips_target_name;
3826 char symbol_name_temporary[24];
3827 unsigned long l;
3828 int i;
3829
3830 if (*p)
3831 return p;
3832
3833 i = 0;
3834 l = micromips_target_label;
3835#ifdef LOCAL_LABEL_PREFIX
3836 *p++ = LOCAL_LABEL_PREFIX;
3837#endif
3838 *p++ = 'L';
3839 *p++ = MICROMIPS_LABEL_CHAR;
3840 do
3841 {
3842 symbol_name_temporary[i++] = l % 10 + '0';
3843 l /= 10;
3844 }
3845 while (l != 0);
3846 while (i > 0)
3847 *p++ = symbol_name_temporary[--i];
3848 *p = '\0';
3849
3850 return micromips_target_name;
3851}
3852
3853static void
3854micromips_label_expr (expressionS *label_expr)
3855{
3856 label_expr->X_op = O_symbol;
3857 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
3858 label_expr->X_add_number = 0;
3859}
3860
3861static void
3862micromips_label_inc (void)
3863{
3864 micromips_target_label++;
3865 *micromips_target_name = '\0';
3866}
3867
3868static void
3869micromips_add_label (void)
3870{
3871 symbolS *s;
3872
3873 s = colon (micromips_label_name ());
3874 micromips_label_inc ();
3875#if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
3876 if (IS_ELF)
3877 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
3878#endif
3879}
3880
3881/* If assembling microMIPS code, then return the microMIPS reloc
3882 corresponding to the requested one if any. Otherwise return
3883 the reloc unchanged. */
3884
3885static bfd_reloc_code_real_type
3886micromips_map_reloc (bfd_reloc_code_real_type reloc)
3887{
3888 static const bfd_reloc_code_real_type relocs[][2] =
3889 {
3890 /* Keep sorted incrementally by the left-hand key. */
3891 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
3892 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
3893 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
3894 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
3895 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
3896 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
3897 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
3898 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
3899 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
3900 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
3901 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
3902 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
3903 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
3904 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
3905 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
3906 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
3907 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
3908 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
3909 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
3910 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
3911 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
3912 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
3913 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
3914 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
3915 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
3916 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
3917 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
3918 };
3919 bfd_reloc_code_real_type r;
3920 size_t i;
3921
3922 if (!mips_opts.micromips)
3923 return reloc;
3924 for (i = 0; i < ARRAY_SIZE (relocs); i++)
3925 {
3926 r = relocs[i][0];
3927 if (r > reloc)
3928 return reloc;
3929 if (r == reloc)
3930 return relocs[i][1];
3931 }
3932 return reloc;
3933}
3934
71400594
RS
3935/* Output an instruction. IP is the instruction information.
3936 ADDRESS_EXPR is an operand of the instruction to be used with
df58fc94
RS
3937 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
3938 a macro expansion. */
71400594
RS
3939
3940static void
3941append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
df58fc94 3942 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
71400594 3943{
df58fc94 3944 unsigned long prev_pinfo, prev_pinfo2, pinfo, pinfo2;
71400594 3945 bfd_boolean relaxed_branch = FALSE;
a4e06468 3946 enum append_method method;
2309ddf2 3947 bfd_boolean relax32;
71400594 3948
2309ddf2 3949 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
c67a084a
NC
3950 fix_loongson2f (ip);
3951
df58fc94 3952 mips_mark_labels ();
71400594 3953
738f4d98 3954 file_ase_mips16 |= mips_opts.mips16;
df58fc94 3955 file_ase_micromips |= mips_opts.micromips;
738f4d98 3956
71400594 3957 prev_pinfo = history[0].insn_mo->pinfo;
df58fc94 3958 prev_pinfo2 = history[0].insn_mo->pinfo2;
71400594 3959 pinfo = ip->insn_mo->pinfo;
df58fc94
RS
3960 pinfo2 = ip->insn_mo->pinfo2;
3961
3962 if (mips_opts.micromips
3963 && !expansionp
3964 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3965 && micromips_insn_length (ip->insn_mo) != 2)
3966 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3967 && micromips_insn_length (ip->insn_mo) != 4)))
3968 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
3969 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
71400594 3970
15be625d
CM
3971 if (address_expr == NULL)
3972 ip->complete_p = 1;
3973 else if (*reloc_type <= BFD_RELOC_UNUSED
3974 && address_expr->X_op == O_constant)
3975 {
3976 unsigned int tmp;
3977
3978 ip->complete_p = 1;
3979 switch (*reloc_type)
3980 {
3981 case BFD_RELOC_32:
3982 ip->insn_opcode |= address_expr->X_add_number;
3983 break;
3984
3985 case BFD_RELOC_MIPS_HIGHEST:
3986 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
3987 ip->insn_opcode |= tmp & 0xffff;
3988 break;
3989
3990 case BFD_RELOC_MIPS_HIGHER:
3991 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
3992 ip->insn_opcode |= tmp & 0xffff;
3993 break;
3994
3995 case BFD_RELOC_HI16_S:
3996 tmp = (address_expr->X_add_number + 0x8000) >> 16;
3997 ip->insn_opcode |= tmp & 0xffff;
3998 break;
3999
4000 case BFD_RELOC_HI16:
4001 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
4002 break;
4003
4004 case BFD_RELOC_UNUSED:
4005 case BFD_RELOC_LO16:
4006 case BFD_RELOC_MIPS_GOT_DISP:
4007 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
4008 break;
4009
4010 case BFD_RELOC_MIPS_JMP:
df58fc94
RS
4011 {
4012 int shift;
4013
4014 shift = mips_opts.micromips ? 1 : 2;
4015 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4016 as_bad (_("jump to misaligned address (0x%lx)"),
4017 (unsigned long) address_expr->X_add_number);
4018 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4019 & 0x3ffffff);
4020 ip->complete_p = 0;
4021 }
15be625d
CM
4022 break;
4023
4024 case BFD_RELOC_MIPS16_JMP:
4025 if ((address_expr->X_add_number & 3) != 0)
4026 as_bad (_("jump to misaligned address (0x%lx)"),
4027 (unsigned long) address_expr->X_add_number);
4028 ip->insn_opcode |=
4029 (((address_expr->X_add_number & 0x7c0000) << 3)
4030 | ((address_expr->X_add_number & 0xf800000) >> 7)
4031 | ((address_expr->X_add_number & 0x3fffc) >> 2));
4032 ip->complete_p = 0;
4033 break;
4034
4035 case BFD_RELOC_16_PCREL_S2:
df58fc94
RS
4036 {
4037 int shift;
4038
4039 shift = mips_opts.micromips ? 1 : 2;
4040 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4041 as_bad (_("branch to misaligned address (0x%lx)"),
4042 (unsigned long) address_expr->X_add_number);
4043 if (!mips_relax_branch)
4044 {
4045 if ((address_expr->X_add_number + (1 << (shift + 15)))
4046 & ~((1 << (shift + 16)) - 1))
4047 as_bad (_("branch address range overflow (0x%lx)"),
4048 (unsigned long) address_expr->X_add_number);
4049 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4050 & 0xffff);
4051 }
4052 ip->complete_p = 0;
4053 }
15be625d
CM
4054 break;
4055
4056 default:
4057 internalError ();
4058 }
4059 }
4060
71400594
RS
4061 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
4062 {
4063 /* There are a lot of optimizations we could do that we don't.
4064 In particular, we do not, in general, reorder instructions.
4065 If you use gcc with optimization, it will reorder
4066 instructions and generally do much more optimization then we
4067 do here; repeating all that work in the assembler would only
4068 benefit hand written assembly code, and does not seem worth
4069 it. */
4070 int nops = (mips_optimize == 0
932d1a1b
RS
4071 ? nops_for_insn (0, history, NULL)
4072 : nops_for_insn_or_target (0, history, ip));
71400594 4073 if (nops > 0)
252b5132
RH
4074 {
4075 fragS *old_frag;
4076 unsigned long old_frag_offset;
4077 int i;
252b5132
RH
4078
4079 old_frag = frag_now;
4080 old_frag_offset = frag_now_fix ();
4081
4082 for (i = 0; i < nops; i++)
4083 emit_nop ();
4084
4085 if (listing)
4086 {
4087 listing_prev_line ();
4088 /* We may be at the start of a variant frag. In case we
4089 are, make sure there is enough space for the frag
4090 after the frags created by listing_prev_line. The
4091 argument to frag_grow here must be at least as large
4092 as the argument to all other calls to frag_grow in
4093 this file. We don't have to worry about being in the
4094 middle of a variant frag, because the variants insert
4095 all needed nop instructions themselves. */
4096 frag_grow (40);
4097 }
4098
404a8071 4099 mips_move_labels ();
252b5132
RH
4100
4101#ifndef NO_ECOFF_DEBUGGING
4102 if (ECOFF_DEBUGGING)
4103 ecoff_fix_loc (old_frag, old_frag_offset);
4104#endif
4105 }
71400594
RS
4106 }
4107 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
4108 {
932d1a1b
RS
4109 int nops;
4110
4111 /* Work out how many nops in prev_nop_frag are needed by IP,
4112 ignoring hazards generated by the first prev_nop_frag_since
4113 instructions. */
4114 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
9c2799c2 4115 gas_assert (nops <= prev_nop_frag_holds);
252b5132 4116
71400594
RS
4117 /* Enforce NOPS as a minimum. */
4118 if (nops > prev_nop_frag_required)
4119 prev_nop_frag_required = nops;
252b5132 4120
71400594
RS
4121 if (prev_nop_frag_holds == prev_nop_frag_required)
4122 {
4123 /* Settle for the current number of nops. Update the history
4124 accordingly (for the benefit of any future .set reorder code). */
4125 prev_nop_frag = NULL;
4126 insert_into_history (prev_nop_frag_since,
4127 prev_nop_frag_holds, NOP_INSN);
4128 }
4129 else
4130 {
4131 /* Allow this instruction to replace one of the nops that was
4132 tentatively added to prev_nop_frag. */
df58fc94 4133 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
71400594
RS
4134 prev_nop_frag_holds--;
4135 prev_nop_frag_since++;
252b5132
RH
4136 }
4137 }
4138
a4e06468
RS
4139 method = get_append_method (ip);
4140
58e2ea4d
MR
4141#ifdef OBJ_ELF
4142 /* The value passed to dwarf2_emit_insn is the distance between
4143 the beginning of the current instruction and the address that
e3a82c8e
MR
4144 should be recorded in the debug tables. This is normally the
4145 current address.
4146
df58fc94
RS
4147 For MIPS16/microMIPS debug info we want to use ISA-encoded
4148 addresses, so we use -1 for an address higher by one than the
4149 current one.
e3a82c8e
MR
4150
4151 If the instruction produced is a branch that we will swap with
4152 the preceding instruction, then we add the displacement by which
4153 the branch will be moved backwards. This is more appropriate
2309ddf2
MR
4154 and for MIPS16/microMIPS code also prevents a debugger from
4155 placing a breakpoint in the middle of the branch (and corrupting
4156 code if software breakpoints are used). */
df58fc94 4157 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0)
e3a82c8e 4158 + (method == APPEND_SWAP ? insn_length (history) : 0));
58e2ea4d
MR
4159#endif
4160
df58fc94
RS
4161 relax32 = (mips_relax_branch
4162 /* Don't try branch relaxation within .set nomacro, or within
4163 .set noat if we use $at for PIC computations. If it turns
4164 out that the branch was out-of-range, we'll get an error. */
4165 && !mips_opts.warn_about_macros
4166 && (mips_opts.at || mips_pic == NO_PIC)
4167 /* Don't relax BPOSGE32/64 as they have no complementing
4168 branches. */
4169 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))
4170 /* Don't try 32-bit branch relaxation when users specify
4171 16-bit/32-bit instructions. */
4172 && !forced_insn_length);
4173
4174 if (!HAVE_CODE_COMPRESSION
4175 && address_expr
4176 && relax32
0b25d3e6 4177 && *reloc_type == BFD_RELOC_16_PCREL_S2
4a6a3df4 4178 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
df58fc94 4179 || pinfo & INSN_COND_BRANCH_LIKELY))
4a6a3df4 4180 {
895921c9 4181 relaxed_branch = TRUE;
1e915849
RS
4182 add_relaxed_insn (ip, (relaxed_branch_length
4183 (NULL, NULL,
4184 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
4185 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
4186 : 0)), 4,
4187 RELAX_BRANCH_ENCODE
66b3e8da
MR
4188 (AT,
4189 pinfo & INSN_UNCOND_BRANCH_DELAY,
1e915849
RS
4190 pinfo & INSN_COND_BRANCH_LIKELY,
4191 pinfo & INSN_WRITE_GPR_31,
4192 0),
4193 address_expr->X_add_symbol,
4194 address_expr->X_add_number);
4a6a3df4
AO
4195 *reloc_type = BFD_RELOC_UNUSED;
4196 }
df58fc94
RS
4197 else if (mips_opts.micromips
4198 && address_expr
4199 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
4200 || *reloc_type > BFD_RELOC_UNUSED)
4201 && (pinfo & INSN_UNCOND_BRANCH_DELAY
4202 || pinfo & INSN_COND_BRANCH_DELAY
4203 || (pinfo2 & ~INSN2_ALIAS) == INSN2_UNCOND_BRANCH
4204 || pinfo2 & INSN2_COND_BRANCH))
4205 {
4206 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
4207 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
4208 int uncond = (pinfo & INSN_UNCOND_BRANCH_DELAY
4209 || pinfo2 & INSN2_UNCOND_BRANCH) ? -1 : 0;
4210 int compact = pinfo2 & (INSN2_COND_BRANCH | INSN2_UNCOND_BRANCH);
4211 int al = pinfo & INSN_WRITE_GPR_31;
4212 int length32;
4213
4214 gas_assert (address_expr != NULL);
4215 gas_assert (!mips_relax.sequence);
4216
4217 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
4218 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
4219 RELAX_MICROMIPS_ENCODE (type, AT,
4220 forced_insn_length == 2,
4221 uncond, compact, al, relax32,
4222 0, 0),
4223 address_expr->X_add_symbol,
4224 address_expr->X_add_number);
4225 *reloc_type = BFD_RELOC_UNUSED;
4226 }
4227 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
252b5132
RH
4228 {
4229 /* We need to set up a variant frag. */
df58fc94 4230 gas_assert (address_expr != NULL);
1e915849
RS
4231 add_relaxed_insn (ip, 4, 0,
4232 RELAX_MIPS16_ENCODE
4233 (*reloc_type - BFD_RELOC_UNUSED,
df58fc94 4234 forced_insn_length == 2, forced_insn_length == 4,
1e915849
RS
4235 prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
4236 history[0].mips16_absolute_jump_p),
4237 make_expr_symbol (address_expr), 0);
252b5132 4238 }
252b5132
RH
4239 else if (mips_opts.mips16
4240 && ! ip->use_extend
f6688943 4241 && *reloc_type != BFD_RELOC_MIPS16_JMP)
9497f5ac 4242 {
b8ee1a6e
DU
4243 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
4244 /* Make sure there is enough room to swap this instruction with
4245 a following jump instruction. */
4246 frag_grow (6);
1e915849 4247 add_fixed_insn (ip);
252b5132
RH
4248 }
4249 else
4250 {
4251 if (mips_opts.mips16
4252 && mips_opts.noreorder
4253 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
4254 as_warn (_("extended instruction in delay slot"));
4255
4d7206a2
RS
4256 if (mips_relax.sequence)
4257 {
4258 /* If we've reached the end of this frag, turn it into a variant
4259 frag and record the information for the instructions we've
4260 written so far. */
4261 if (frag_room () < 4)
4262 relax_close_frag ();
df58fc94 4263 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4d7206a2
RS
4264 }
4265
584892a6 4266 if (mips_relax.sequence != 2)
df58fc94
RS
4267 {
4268 if (mips_macro_warning.first_insn_sizes[0] == 0)
4269 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
4270 mips_macro_warning.sizes[0] += insn_length (ip);
4271 mips_macro_warning.insns[0]++;
4272 }
584892a6 4273 if (mips_relax.sequence != 1)
df58fc94
RS
4274 {
4275 if (mips_macro_warning.first_insn_sizes[1] == 0)
4276 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
4277 mips_macro_warning.sizes[1] += insn_length (ip);
4278 mips_macro_warning.insns[1]++;
4279 }
584892a6 4280
1e915849
RS
4281 if (mips_opts.mips16)
4282 {
4283 ip->fixed_p = 1;
4284 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
4285 }
4286 add_fixed_insn (ip);
252b5132
RH
4287 }
4288
9fe77896 4289 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
252b5132 4290 {
df58fc94 4291 bfd_reloc_code_real_type final_type[3];
2309ddf2 4292 reloc_howto_type *howto0;
9fe77896
RS
4293 reloc_howto_type *howto;
4294 int i;
34ce925e 4295
df58fc94
RS
4296 /* Perform any necessary conversion to microMIPS relocations
4297 and find out how many relocations there actually are. */
4298 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
4299 final_type[i] = micromips_map_reloc (reloc_type[i]);
4300
9fe77896
RS
4301 /* In a compound relocation, it is the final (outermost)
4302 operator that determines the relocated field. */
2309ddf2
MR
4303 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
4304
9fe77896
RS
4305 if (howto == NULL)
4306 {
4307 /* To reproduce this failure try assembling gas/testsuites/
4308 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4309 assembler. */
df58fc94
RS
4310 as_bad (_("Unsupported MIPS relocation number %d"),
4311 final_type[i - 1]);
9fe77896
RS
4312 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
4313 }
2309ddf2
MR
4314
4315 if (i > 1)
4316 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
9fe77896
RS
4317 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
4318 bfd_get_reloc_size (howto),
4319 address_expr,
2309ddf2
MR
4320 howto0 && howto0->pc_relative,
4321 final_type[0]);
9fe77896
RS
4322
4323 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
2309ddf2 4324 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
9fe77896
RS
4325 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
4326
4327 /* These relocations can have an addend that won't fit in
4328 4 octets for 64bit assembly. */
4329 if (HAVE_64BIT_GPRS
4330 && ! howto->partial_inplace
4331 && (reloc_type[0] == BFD_RELOC_16
4332 || reloc_type[0] == BFD_RELOC_32
4333 || reloc_type[0] == BFD_RELOC_MIPS_JMP
4334 || reloc_type[0] == BFD_RELOC_GPREL16
4335 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
4336 || reloc_type[0] == BFD_RELOC_GPREL32
4337 || reloc_type[0] == BFD_RELOC_64
4338 || reloc_type[0] == BFD_RELOC_CTOR
4339 || reloc_type[0] == BFD_RELOC_MIPS_SUB
4340 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
4341 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
4342 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
4343 || reloc_type[0] == BFD_RELOC_MIPS_REL16
4344 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
4345 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
4346 || hi16_reloc_p (reloc_type[0])
4347 || lo16_reloc_p (reloc_type[0])))
4348 ip->fixp[0]->fx_no_overflow = 1;
4349
4350 if (mips_relax.sequence)
4351 {
4352 if (mips_relax.first_fixup == 0)
4353 mips_relax.first_fixup = ip->fixp[0];
4354 }
4355 else if (reloc_needs_lo_p (*reloc_type))
4356 {
4357 struct mips_hi_fixup *hi_fixup;
4358
4359 /* Reuse the last entry if it already has a matching %lo. */
4360 hi_fixup = mips_hi_fixup_list;
4361 if (hi_fixup == 0
4362 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4d7206a2 4363 {
9fe77896
RS
4364 hi_fixup = ((struct mips_hi_fixup *)
4365 xmalloc (sizeof (struct mips_hi_fixup)));
4366 hi_fixup->next = mips_hi_fixup_list;
4367 mips_hi_fixup_list = hi_fixup;
4d7206a2 4368 }
9fe77896
RS
4369 hi_fixup->fixp = ip->fixp[0];
4370 hi_fixup->seg = now_seg;
4371 }
252b5132 4372
9fe77896
RS
4373 /* Add fixups for the second and third relocations, if given.
4374 Note that the ABI allows the second relocation to be
4375 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4376 moment we only use RSS_UNDEF, but we could add support
4377 for the others if it ever becomes necessary. */
4378 for (i = 1; i < 3; i++)
4379 if (reloc_type[i] != BFD_RELOC_UNUSED)
4380 {
4381 ip->fixp[i] = fix_new (ip->frag, ip->where,
4382 ip->fixp[0]->fx_size, NULL, 0,
df58fc94 4383 FALSE, final_type[i]);
f6688943 4384
9fe77896
RS
4385 /* Use fx_tcbit to mark compound relocs. */
4386 ip->fixp[0]->fx_tcbit = 1;
4387 ip->fixp[i]->fx_tcbit = 1;
4388 }
252b5132 4389 }
1e915849 4390 install_insn (ip);
252b5132
RH
4391
4392 /* Update the register mask information. */
4c260379
RS
4393 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
4394 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
252b5132 4395
a4e06468 4396 switch (method)
252b5132 4397 {
a4e06468
RS
4398 case APPEND_ADD:
4399 insert_into_history (0, 1, ip);
4400 break;
4401
4402 case APPEND_ADD_WITH_NOP:
4403 insert_into_history (0, 1, ip);
df58fc94
RS
4404 if (mips_opts.micromips
4405 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT))
4406 {
4407 add_fixed_insn (&micromips_nop32_insn);
4408 insert_into_history (0, 1, &micromips_nop32_insn);
4409 if (mips_relax.sequence)
4410 mips_relax.sizes[mips_relax.sequence - 1] += 4;
4411 }
4412 else
4413 {
4414 emit_nop ();
4415 if (mips_relax.sequence)
4416 mips_relax.sizes[mips_relax.sequence - 1] += NOP_INSN_SIZE;
4417 }
a4e06468
RS
4418 break;
4419
4420 case APPEND_ADD_COMPACT:
4421 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4422 gas_assert (mips_opts.mips16);
4423 ip->insn_opcode |= 0x0080;
4424 find_altered_mips16_opcode (ip);
4425 install_insn (ip);
4426 insert_into_history (0, 1, ip);
4427 break;
4428
4429 case APPEND_SWAP:
4430 {
4431 struct mips_cl_insn delay = history[0];
4432 if (mips_opts.mips16)
4433 {
4434 know (delay.frag == ip->frag);
4435 move_insn (ip, delay.frag, delay.where);
4436 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
4437 }
df58fc94
RS
4438 else if (mips_opts.micromips)
4439 {
4440 /* We don't reorder for micromips. */
4441 abort ();
4442 }
a4e06468
RS
4443 else if (relaxed_branch)
4444 {
4445 /* Add the delay slot instruction to the end of the
4446 current frag and shrink the fixed part of the
4447 original frag. If the branch occupies the tail of
4448 the latter, move it backwards to cover the gap. */
4449 delay.frag->fr_fix -= 4;
4450 if (delay.frag == ip->frag)
4451 move_insn (ip, ip->frag, ip->where - 4);
4452 add_fixed_insn (&delay);
4453 }
4454 else
4455 {
4456 move_insn (&delay, ip->frag, ip->where);
4457 move_insn (ip, history[0].frag, history[0].where);
4458 }
4459 history[0] = *ip;
4460 delay.fixed_p = 1;
4461 insert_into_history (0, 1, &delay);
4462 }
4463 break;
252b5132
RH
4464 }
4465
13408f1e
RS
4466 /* If we have just completed an unconditional branch, clear the history. */
4467 if ((history[1].insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY)
4468 || (mips_opts.mips16
4469 && (history[0].insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH)))
4470 mips_no_prev_insn ();
4471
df58fc94
RS
4472 /* We need to emit a label at the end of branch-likely macros. */
4473 if (emit_branch_likely_macro)
4474 {
4475 emit_branch_likely_macro = FALSE;
4476 micromips_add_label ();
4477 }
4478
252b5132
RH
4479 /* We just output an insn, so the next one doesn't have a label. */
4480 mips_clear_insn_labels ();
252b5132
RH
4481}
4482
7d10b47d 4483/* Forget that there was any previous instruction or label. */
252b5132
RH
4484
4485static void
7d10b47d 4486mips_no_prev_insn (void)
252b5132 4487{
7d10b47d
RS
4488 prev_nop_frag = NULL;
4489 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
252b5132
RH
4490 mips_clear_insn_labels ();
4491}
4492
7d10b47d
RS
4493/* This function must be called before we emit something other than
4494 instructions. It is like mips_no_prev_insn except that it inserts
4495 any NOPS that might be needed by previous instructions. */
252b5132 4496
7d10b47d
RS
4497void
4498mips_emit_delays (void)
252b5132
RH
4499{
4500 if (! mips_opts.noreorder)
4501 {
932d1a1b 4502 int nops = nops_for_insn (0, history, NULL);
252b5132
RH
4503 if (nops > 0)
4504 {
7d10b47d
RS
4505 while (nops-- > 0)
4506 add_fixed_insn (NOP_INSN);
4507 mips_move_labels ();
4508 }
4509 }
4510 mips_no_prev_insn ();
4511}
4512
4513/* Start a (possibly nested) noreorder block. */
4514
4515static void
4516start_noreorder (void)
4517{
4518 if (mips_opts.noreorder == 0)
4519 {
4520 unsigned int i;
4521 int nops;
4522
4523 /* None of the instructions before the .set noreorder can be moved. */
4524 for (i = 0; i < ARRAY_SIZE (history); i++)
4525 history[i].fixed_p = 1;
4526
4527 /* Insert any nops that might be needed between the .set noreorder
4528 block and the previous instructions. We will later remove any
4529 nops that turn out not to be needed. */
932d1a1b 4530 nops = nops_for_insn (0, history, NULL);
7d10b47d
RS
4531 if (nops > 0)
4532 {
4533 if (mips_optimize != 0)
252b5132
RH
4534 {
4535 /* Record the frag which holds the nop instructions, so
4536 that we can remove them if we don't need them. */
df58fc94 4537 frag_grow (nops * NOP_INSN_SIZE);
252b5132
RH
4538 prev_nop_frag = frag_now;
4539 prev_nop_frag_holds = nops;
4540 prev_nop_frag_required = 0;
4541 prev_nop_frag_since = 0;
4542 }
4543
4544 for (; nops > 0; --nops)
1e915849 4545 add_fixed_insn (NOP_INSN);
252b5132 4546
7d10b47d
RS
4547 /* Move on to a new frag, so that it is safe to simply
4548 decrease the size of prev_nop_frag. */
4549 frag_wane (frag_now);
4550 frag_new (0);
404a8071 4551 mips_move_labels ();
252b5132 4552 }
df58fc94 4553 mips_mark_labels ();
7d10b47d 4554 mips_clear_insn_labels ();
252b5132 4555 }
7d10b47d
RS
4556 mips_opts.noreorder++;
4557 mips_any_noreorder = 1;
4558}
252b5132 4559
7d10b47d 4560/* End a nested noreorder block. */
252b5132 4561
7d10b47d
RS
4562static void
4563end_noreorder (void)
4564{
6a32d874 4565
7d10b47d
RS
4566 mips_opts.noreorder--;
4567 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
4568 {
4569 /* Commit to inserting prev_nop_frag_required nops and go back to
4570 handling nop insertion the .set reorder way. */
4571 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
df58fc94 4572 * NOP_INSN_SIZE);
7d10b47d
RS
4573 insert_into_history (prev_nop_frag_since,
4574 prev_nop_frag_required, NOP_INSN);
4575 prev_nop_frag = NULL;
4576 }
252b5132
RH
4577}
4578
584892a6
RS
4579/* Set up global variables for the start of a new macro. */
4580
4581static void
4582macro_start (void)
4583{
4584 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
df58fc94
RS
4585 memset (&mips_macro_warning.first_insn_sizes, 0,
4586 sizeof (mips_macro_warning.first_insn_sizes));
4587 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
584892a6 4588 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
47e39b9d 4589 && (history[0].insn_mo->pinfo
584892a6
RS
4590 & (INSN_UNCOND_BRANCH_DELAY
4591 | INSN_COND_BRANCH_DELAY
4592 | INSN_COND_BRANCH_LIKELY)) != 0);
df58fc94
RS
4593 switch (history[0].insn_mo->pinfo2
4594 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
4595 {
4596 case INSN2_BRANCH_DELAY_32BIT:
4597 mips_macro_warning.delay_slot_length = 4;
4598 break;
4599 case INSN2_BRANCH_DELAY_16BIT:
4600 mips_macro_warning.delay_slot_length = 2;
4601 break;
4602 default:
4603 mips_macro_warning.delay_slot_length = 0;
4604 break;
4605 }
4606 mips_macro_warning.first_frag = NULL;
584892a6
RS
4607}
4608
df58fc94
RS
4609/* Given that a macro is longer than one instruction or of the wrong size,
4610 return the appropriate warning for it. Return null if no warning is
4611 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4612 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4613 and RELAX_NOMACRO. */
584892a6
RS
4614
4615static const char *
4616macro_warning (relax_substateT subtype)
4617{
4618 if (subtype & RELAX_DELAY_SLOT)
4619 return _("Macro instruction expanded into multiple instructions"
4620 " in a branch delay slot");
4621 else if (subtype & RELAX_NOMACRO)
4622 return _("Macro instruction expanded into multiple instructions");
df58fc94
RS
4623 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
4624 | RELAX_DELAY_SLOT_SIZE_SECOND))
4625 return ((subtype & RELAX_DELAY_SLOT_16BIT)
4626 ? _("Macro instruction expanded into a wrong size instruction"
4627 " in a 16-bit branch delay slot")
4628 : _("Macro instruction expanded into a wrong size instruction"
4629 " in a 32-bit branch delay slot"));
584892a6
RS
4630 else
4631 return 0;
4632}
4633
4634/* Finish up a macro. Emit warnings as appropriate. */
4635
4636static void
4637macro_end (void)
4638{
df58fc94
RS
4639 /* Relaxation warning flags. */
4640 relax_substateT subtype = 0;
4641
4642 /* Check delay slot size requirements. */
4643 if (mips_macro_warning.delay_slot_length == 2)
4644 subtype |= RELAX_DELAY_SLOT_16BIT;
4645 if (mips_macro_warning.delay_slot_length != 0)
584892a6 4646 {
df58fc94
RS
4647 if (mips_macro_warning.delay_slot_length
4648 != mips_macro_warning.first_insn_sizes[0])
4649 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
4650 if (mips_macro_warning.delay_slot_length
4651 != mips_macro_warning.first_insn_sizes[1])
4652 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
4653 }
584892a6 4654
df58fc94
RS
4655 /* Check instruction count requirements. */
4656 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
4657 {
4658 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
584892a6
RS
4659 subtype |= RELAX_SECOND_LONGER;
4660 if (mips_opts.warn_about_macros)
4661 subtype |= RELAX_NOMACRO;
4662 if (mips_macro_warning.delay_slot_p)
4663 subtype |= RELAX_DELAY_SLOT;
df58fc94 4664 }
584892a6 4665
df58fc94
RS
4666 /* If both alternatives fail to fill a delay slot correctly,
4667 emit the warning now. */
4668 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
4669 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
4670 {
4671 relax_substateT s;
4672 const char *msg;
4673
4674 s = subtype & (RELAX_DELAY_SLOT_16BIT
4675 | RELAX_DELAY_SLOT_SIZE_FIRST
4676 | RELAX_DELAY_SLOT_SIZE_SECOND);
4677 msg = macro_warning (s);
4678 if (msg != NULL)
4679 as_warn ("%s", msg);
4680 subtype &= ~s;
4681 }
4682
4683 /* If both implementations are longer than 1 instruction, then emit the
4684 warning now. */
4685 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
4686 {
4687 relax_substateT s;
4688 const char *msg;
4689
4690 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
4691 msg = macro_warning (s);
4692 if (msg != NULL)
4693 as_warn ("%s", msg);
4694 subtype &= ~s;
584892a6 4695 }
df58fc94
RS
4696
4697 /* If any flags still set, then one implementation might need a warning
4698 and the other either will need one of a different kind or none at all.
4699 Pass any remaining flags over to relaxation. */
4700 if (mips_macro_warning.first_frag != NULL)
4701 mips_macro_warning.first_frag->fr_subtype |= subtype;
584892a6
RS
4702}
4703
df58fc94
RS
4704/* Instruction operand formats used in macros that vary between
4705 standard MIPS and microMIPS code. */
4706
4707static const char * const brk_fmt[2] = { "c", "mF" };
4708static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
4709static const char * const jalr_fmt[2] = { "d,s", "t,s" };
4710static const char * const lui_fmt[2] = { "t,u", "s,u" };
4711static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
4712static const char * const mfhl_fmt[2] = { "d", "mj" };
4713static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
4714static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
4715
4716#define BRK_FMT (brk_fmt[mips_opts.micromips])
4717#define COP12_FMT (cop12_fmt[mips_opts.micromips])
4718#define JALR_FMT (jalr_fmt[mips_opts.micromips])
4719#define LUI_FMT (lui_fmt[mips_opts.micromips])
4720#define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4721#define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4722#define SHFT_FMT (shft_fmt[mips_opts.micromips])
4723#define TRAP_FMT (trap_fmt[mips_opts.micromips])
4724
6e1304d8
RS
4725/* Read a macro's relocation codes from *ARGS and store them in *R.
4726 The first argument in *ARGS will be either the code for a single
4727 relocation or -1 followed by the three codes that make up a
4728 composite relocation. */
4729
4730static void
4731macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
4732{
4733 int i, next;
4734
4735 next = va_arg (*args, int);
4736 if (next >= 0)
4737 r[0] = (bfd_reloc_code_real_type) next;
4738 else
4739 for (i = 0; i < 3; i++)
4740 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
4741}
4742
252b5132
RH
4743/* Build an instruction created by a macro expansion. This is passed
4744 a pointer to the count of instructions created so far, an
4745 expression, the name of the instruction to build, an operand format
4746 string, and corresponding arguments. */
4747
252b5132 4748static void
67c0d1eb 4749macro_build (expressionS *ep, const char *name, const char *fmt, ...)
252b5132 4750{
df58fc94 4751 const struct mips_opcode *mo = NULL;
f6688943 4752 bfd_reloc_code_real_type r[3];
df58fc94
RS
4753 const struct mips_opcode *amo;
4754 struct hash_control *hash;
4755 struct mips_cl_insn insn;
252b5132 4756 va_list args;
252b5132 4757
252b5132 4758 va_start (args, fmt);
252b5132 4759
252b5132
RH
4760 if (mips_opts.mips16)
4761 {
03ea81db 4762 mips16_macro_build (ep, name, fmt, &args);
252b5132
RH
4763 va_end (args);
4764 return;
4765 }
4766
f6688943
TS
4767 r[0] = BFD_RELOC_UNUSED;
4768 r[1] = BFD_RELOC_UNUSED;
4769 r[2] = BFD_RELOC_UNUSED;
df58fc94
RS
4770 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
4771 amo = (struct mips_opcode *) hash_find (hash, name);
4772 gas_assert (amo);
4773 gas_assert (strcmp (name, amo->name) == 0);
1e915849 4774
df58fc94 4775 do
8b082fb1
TS
4776 {
4777 /* Search until we get a match for NAME. It is assumed here that
df58fc94
RS
4778 macros will never generate MDMX, MIPS-3D, or MT instructions.
4779 We try to match an instruction that fulfils the branch delay
4780 slot instruction length requirement (if any) of the previous
4781 instruction. While doing this we record the first instruction
4782 seen that matches all the other conditions and use it anyway
4783 if the requirement cannot be met; we will issue an appropriate
4784 warning later on. */
4785 if (strcmp (fmt, amo->args) == 0
4786 && amo->pinfo != INSN_MACRO
4787 && is_opcode_valid (amo)
4788 && is_size_valid (amo))
4789 {
4790 if (is_delay_slot_valid (amo))
4791 {
4792 mo = amo;
4793 break;
4794 }
4795 else if (!mo)
4796 mo = amo;
4797 }
8b082fb1 4798
df58fc94
RS
4799 ++amo;
4800 gas_assert (amo->name);
252b5132 4801 }
df58fc94 4802 while (strcmp (name, amo->name) == 0);
252b5132 4803
df58fc94 4804 gas_assert (mo);
1e915849 4805 create_insn (&insn, mo);
252b5132
RH
4806 for (;;)
4807 {
4808 switch (*fmt++)
4809 {
4810 case '\0':
4811 break;
4812
4813 case ',':
4814 case '(':
4815 case ')':
4816 continue;
4817
5f74bc13
CD
4818 case '+':
4819 switch (*fmt++)
4820 {
4821 case 'A':
4822 case 'E':
df58fc94
RS
4823 INSERT_OPERAND (mips_opts.micromips,
4824 EXTLSB, insn, va_arg (args, int));
5f74bc13
CD
4825 continue;
4826
4827 case 'B':
4828 case 'F':
4829 /* Note that in the macro case, these arguments are already
4830 in MSB form. (When handling the instruction in the
4831 non-macro case, these arguments are sizes from which
4832 MSB values must be calculated.) */
df58fc94
RS
4833 INSERT_OPERAND (mips_opts.micromips,
4834 INSMSB, insn, va_arg (args, int));
5f74bc13
CD
4835 continue;
4836
4837 case 'C':
4838 case 'G':
4839 case 'H':
4840 /* Note that in the macro case, these arguments are already
4841 in MSBD form. (When handling the instruction in the
4842 non-macro case, these arguments are sizes from which
4843 MSBD values must be calculated.) */
df58fc94
RS
4844 INSERT_OPERAND (mips_opts.micromips,
4845 EXTMSBD, insn, va_arg (args, int));
5f74bc13
CD
4846 continue;
4847
dd3cbb7e 4848 case 'Q':
df58fc94
RS
4849 gas_assert (!mips_opts.micromips);
4850 INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
dd3cbb7e
NC
4851 continue;
4852
5f74bc13
CD
4853 default:
4854 internalError ();
4855 }
4856 continue;
4857
8b082fb1 4858 case '2':
df58fc94
RS
4859 gas_assert (!mips_opts.micromips);
4860 INSERT_OPERAND (0, BP, insn, va_arg (args, int));
8b082fb1
TS
4861 continue;
4862
df58fc94
RS
4863 case 'n':
4864 gas_assert (mips_opts.micromips);
252b5132
RH
4865 case 't':
4866 case 'w':
4867 case 'E':
df58fc94 4868 INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
252b5132
RH
4869 continue;
4870
4871 case 'c':
df58fc94
RS
4872 gas_assert (!mips_opts.micromips);
4873 INSERT_OPERAND (0, CODE, insn, va_arg (args, int));
38487616
TS
4874 continue;
4875
252b5132 4876 case 'W':
df58fc94
RS
4877 gas_assert (!mips_opts.micromips);
4878 case 'T':
4879 INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
252b5132
RH
4880 continue;
4881
252b5132 4882 case 'G':
df58fc94
RS
4883 if (mips_opts.micromips)
4884 INSERT_OPERAND (1, RS, insn, va_arg (args, int));
4885 else
4886 INSERT_OPERAND (0, RD, insn, va_arg (args, int));
4887 continue;
4888
af7ee8bf 4889 case 'K':
df58fc94
RS
4890 gas_assert (!mips_opts.micromips);
4891 case 'd':
4892 INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
252b5132
RH
4893 continue;
4894
4372b673 4895 case 'U':
df58fc94 4896 gas_assert (!mips_opts.micromips);
4372b673
NC
4897 {
4898 int tmp = va_arg (args, int);
4899
df58fc94
RS
4900 INSERT_OPERAND (0, RT, insn, tmp);
4901 INSERT_OPERAND (0, RD, insn, tmp);
4372b673 4902 }
df58fc94 4903 continue;
4372b673 4904
252b5132
RH
4905 case 'V':
4906 case 'S':
df58fc94
RS
4907 gas_assert (!mips_opts.micromips);
4908 INSERT_OPERAND (0, FS, insn, va_arg (args, int));
252b5132
RH
4909 continue;
4910
4911 case 'z':
4912 continue;
4913
4914 case '<':
df58fc94
RS
4915 INSERT_OPERAND (mips_opts.micromips,
4916 SHAMT, insn, va_arg (args, int));
252b5132
RH
4917 continue;
4918
4919 case 'D':
df58fc94
RS
4920 gas_assert (!mips_opts.micromips);
4921 INSERT_OPERAND (0, FD, insn, va_arg (args, int));
252b5132
RH
4922 continue;
4923
4924 case 'B':
df58fc94
RS
4925 gas_assert (!mips_opts.micromips);
4926 INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
252b5132
RH
4927 continue;
4928
4372b673 4929 case 'J':
df58fc94
RS
4930 gas_assert (!mips_opts.micromips);
4931 INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
4372b673
NC
4932 continue;
4933
252b5132 4934 case 'q':
df58fc94
RS
4935 gas_assert (!mips_opts.micromips);
4936 INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
252b5132
RH
4937 continue;
4938
4939 case 'b':
4940 case 's':
4941 case 'r':
4942 case 'v':
df58fc94 4943 INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
252b5132
RH
4944 continue;
4945
4946 case 'i':
4947 case 'j':
6e1304d8 4948 macro_read_relocs (&args, r);
9c2799c2 4949 gas_assert (*r == BFD_RELOC_GPREL16
e391c024
RS
4950 || *r == BFD_RELOC_MIPS_HIGHER
4951 || *r == BFD_RELOC_HI16_S
4952 || *r == BFD_RELOC_LO16
4953 || *r == BFD_RELOC_MIPS_GOT_OFST);
4954 continue;
4955
4956 case 'o':
4957 macro_read_relocs (&args, r);
252b5132
RH
4958 continue;
4959
4960 case 'u':
6e1304d8 4961 macro_read_relocs (&args, r);
9c2799c2 4962 gas_assert (ep != NULL
90ecf173
MR
4963 && (ep->X_op == O_constant
4964 || (ep->X_op == O_symbol
4965 && (*r == BFD_RELOC_MIPS_HIGHEST
4966 || *r == BFD_RELOC_HI16_S
4967 || *r == BFD_RELOC_HI16
4968 || *r == BFD_RELOC_GPREL16
4969 || *r == BFD_RELOC_MIPS_GOT_HI16
4970 || *r == BFD_RELOC_MIPS_CALL_HI16))));
252b5132
RH
4971 continue;
4972
4973 case 'p':
9c2799c2 4974 gas_assert (ep != NULL);
bad36eac 4975
252b5132
RH
4976 /*
4977 * This allows macro() to pass an immediate expression for
4978 * creating short branches without creating a symbol.
bad36eac
DJ
4979 *
4980 * We don't allow branch relaxation for these branches, as
4981 * they should only appear in ".set nomacro" anyway.
252b5132
RH
4982 */
4983 if (ep->X_op == O_constant)
4984 {
df58fc94
RS
4985 /* For microMIPS we always use relocations for branches.
4986 So we should not resolve immediate values. */
4987 gas_assert (!mips_opts.micromips);
4988
bad36eac
DJ
4989 if ((ep->X_add_number & 3) != 0)
4990 as_bad (_("branch to misaligned address (0x%lx)"),
4991 (unsigned long) ep->X_add_number);
4992 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
4993 as_bad (_("branch address range overflow (0x%lx)"),
4994 (unsigned long) ep->X_add_number);
252b5132
RH
4995 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
4996 ep = NULL;
4997 }
4998 else
0b25d3e6 4999 *r = BFD_RELOC_16_PCREL_S2;
252b5132
RH
5000 continue;
5001
5002 case 'a':
9c2799c2 5003 gas_assert (ep != NULL);
f6688943 5004 *r = BFD_RELOC_MIPS_JMP;
252b5132
RH
5005 continue;
5006
5007 case 'C':
df58fc94
RS
5008 gas_assert (!mips_opts.micromips);
5009 INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long));
252b5132
RH
5010 continue;
5011
d43b4baf 5012 case 'k':
df58fc94
RS
5013 INSERT_OPERAND (mips_opts.micromips,
5014 CACHE, insn, va_arg (args, unsigned long));
5015 continue;
5016
5017 case '|':
5018 gas_assert (mips_opts.micromips);
5019 INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
5020 continue;
5021
5022 case '.':
5023 gas_assert (mips_opts.micromips);
5024 INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
5025 continue;
5026
5027 case '~':
5028 gas_assert (mips_opts.micromips);
5029 INSERT_OPERAND (1, OFFSET12, insn, va_arg (args, unsigned long));
5030 continue;
5031
5032 case 'N':
5033 gas_assert (mips_opts.micromips);
5034 INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
5035 continue;
5036
5037 case 'm': /* Opcode extension character. */
5038 gas_assert (mips_opts.micromips);
5039 switch (*fmt++)
5040 {
5041 case 'j':
5042 INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
5043 break;
5044
5045 case 'p':
5046 INSERT_OPERAND (1, MP, insn, va_arg (args, int));
5047 break;
5048
5049 case 'F':
5050 INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
5051 break;
5052
5053 default:
5054 internalError ();
5055 }
d43b4baf
TS
5056 continue;
5057
252b5132
RH
5058 default:
5059 internalError ();
5060 }
5061 break;
5062 }
5063 va_end (args);
9c2799c2 5064 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
252b5132 5065
df58fc94 5066 append_insn (&insn, ep, r, TRUE);
252b5132
RH
5067}
5068
5069static void
67c0d1eb 5070mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
03ea81db 5071 va_list *args)
252b5132 5072{
1e915849 5073 struct mips_opcode *mo;
252b5132 5074 struct mips_cl_insn insn;
f6688943
TS
5075 bfd_reloc_code_real_type r[3]
5076 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
252b5132 5077
1e915849 5078 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
9c2799c2
NC
5079 gas_assert (mo);
5080 gas_assert (strcmp (name, mo->name) == 0);
252b5132 5081
1e915849 5082 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
252b5132 5083 {
1e915849 5084 ++mo;
9c2799c2
NC
5085 gas_assert (mo->name);
5086 gas_assert (strcmp (name, mo->name) == 0);
252b5132
RH
5087 }
5088
1e915849 5089 create_insn (&insn, mo);
252b5132
RH
5090 for (;;)
5091 {
5092 int c;
5093
5094 c = *fmt++;
5095 switch (c)
5096 {
5097 case '\0':
5098 break;
5099
5100 case ',':
5101 case '(':
5102 case ')':
5103 continue;
5104
5105 case 'y':
5106 case 'w':
03ea81db 5107 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
252b5132
RH
5108 continue;
5109
5110 case 'x':
5111 case 'v':
03ea81db 5112 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
252b5132
RH
5113 continue;
5114
5115 case 'z':
03ea81db 5116 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
252b5132
RH
5117 continue;
5118
5119 case 'Z':
03ea81db 5120 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
252b5132
RH
5121 continue;
5122
5123 case '0':
5124 case 'S':
5125 case 'P':
5126 case 'R':
5127 continue;
5128
5129 case 'X':
03ea81db 5130 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
252b5132
RH
5131 continue;
5132
5133 case 'Y':
5134 {
5135 int regno;
5136
03ea81db 5137 regno = va_arg (*args, int);
252b5132 5138 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
a9e24354 5139 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
252b5132
RH
5140 }
5141 continue;
5142
5143 case '<':
5144 case '>':
5145 case '4':
5146 case '5':
5147 case 'H':
5148 case 'W':
5149 case 'D':
5150 case 'j':
5151 case '8':
5152 case 'V':
5153 case 'C':
5154 case 'U':
5155 case 'k':
5156 case 'K':
5157 case 'p':
5158 case 'q':
5159 {
9c2799c2 5160 gas_assert (ep != NULL);
252b5132
RH
5161
5162 if (ep->X_op != O_constant)
874e8986 5163 *r = (int) BFD_RELOC_UNUSED + c;
252b5132
RH
5164 else
5165 {
b34976b6
AM
5166 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
5167 FALSE, &insn.insn_opcode, &insn.use_extend,
c4e7957c 5168 &insn.extend);
252b5132 5169 ep = NULL;
f6688943 5170 *r = BFD_RELOC_UNUSED;
252b5132
RH
5171 }
5172 }
5173 continue;
5174
5175 case '6':
03ea81db 5176 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
252b5132
RH
5177 continue;
5178 }
5179
5180 break;
5181 }
5182
9c2799c2 5183 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
252b5132 5184
df58fc94 5185 append_insn (&insn, ep, r, TRUE);
252b5132
RH
5186}
5187
2051e8c4
MR
5188/*
5189 * Sign-extend 32-bit mode constants that have bit 31 set and all
5190 * higher bits unset.
5191 */
9f872bbe 5192static void
2051e8c4
MR
5193normalize_constant_expr (expressionS *ex)
5194{
9ee2a2d4 5195 if (ex->X_op == O_constant
2051e8c4
MR
5196 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5197 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5198 - 0x80000000);
5199}
5200
5201/*
5202 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5203 * all higher bits unset.
5204 */
5205static void
5206normalize_address_expr (expressionS *ex)
5207{
5208 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
5209 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
5210 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5211 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5212 - 0x80000000);
5213}
5214
438c16b8
TS
5215/*
5216 * Generate a "jalr" instruction with a relocation hint to the called
5217 * function. This occurs in NewABI PIC code.
5218 */
5219static void
df58fc94 5220macro_build_jalr (expressionS *ep, int cprestore)
438c16b8 5221{
df58fc94
RS
5222 static const bfd_reloc_code_real_type jalr_relocs[2]
5223 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
5224 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
5225 const char *jalr;
685736be 5226 char *f = NULL;
b34976b6 5227
1180b5a4 5228 if (MIPS_JALR_HINT_P (ep))
f21f8242 5229 {
cc3d92a5 5230 frag_grow (8);
f21f8242
AO
5231 f = frag_more (0);
5232 }
df58fc94
RS
5233 if (!mips_opts.micromips)
5234 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
5235 else
5236 {
5237 jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs";
5238 if (MIPS_JALR_HINT_P (ep))
5239 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
5240 else
5241 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
5242 }
1180b5a4 5243 if (MIPS_JALR_HINT_P (ep))
df58fc94 5244 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
438c16b8
TS
5245}
5246
252b5132
RH
5247/*
5248 * Generate a "lui" instruction.
5249 */
5250static void
67c0d1eb 5251macro_build_lui (expressionS *ep, int regnum)
252b5132 5252{
9c2799c2 5253 gas_assert (! mips_opts.mips16);
252b5132 5254
df58fc94 5255 if (ep->X_op != O_constant)
252b5132 5256 {
9c2799c2 5257 gas_assert (ep->X_op == O_symbol);
bbe506e8
TS
5258 /* _gp_disp is a special case, used from s_cpload.
5259 __gnu_local_gp is used if mips_no_shared. */
9c2799c2 5260 gas_assert (mips_pic == NO_PIC
78e1bb40 5261 || (! HAVE_NEWABI
aa6975fb
ILT
5262 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
5263 || (! mips_in_shared
bbe506e8
TS
5264 && strcmp (S_GET_NAME (ep->X_add_symbol),
5265 "__gnu_local_gp") == 0));
252b5132
RH
5266 }
5267
df58fc94 5268 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
252b5132
RH
5269}
5270
885add95
CD
5271/* Generate a sequence of instructions to do a load or store from a constant
5272 offset off of a base register (breg) into/from a target register (treg),
5273 using AT if necessary. */
5274static void
67c0d1eb
RS
5275macro_build_ldst_constoffset (expressionS *ep, const char *op,
5276 int treg, int breg, int dbl)
885add95 5277{
9c2799c2 5278 gas_assert (ep->X_op == O_constant);
885add95 5279
256ab948 5280 /* Sign-extending 32-bit constants makes their handling easier. */
2051e8c4
MR
5281 if (!dbl)
5282 normalize_constant_expr (ep);
256ab948 5283
67c1ffbe 5284 /* Right now, this routine can only handle signed 32-bit constants. */
ecd13cd3 5285 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
885add95
CD
5286 as_warn (_("operand overflow"));
5287
5288 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
5289 {
5290 /* Signed 16-bit offset will fit in the op. Easy! */
67c0d1eb 5291 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
885add95
CD
5292 }
5293 else
5294 {
5295 /* 32-bit offset, need multiple instructions and AT, like:
5296 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5297 addu $tempreg,$tempreg,$breg
5298 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5299 to handle the complete offset. */
67c0d1eb
RS
5300 macro_build_lui (ep, AT);
5301 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
5302 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
885add95 5303
741fe287 5304 if (!mips_opts.at)
8fc2e39e 5305 as_bad (_("Macro used $at after \".set noat\""));
885add95
CD
5306 }
5307}
5308
252b5132
RH
5309/* set_at()
5310 * Generates code to set the $at register to true (one)
5311 * if reg is less than the immediate expression.
5312 */
5313static void
67c0d1eb 5314set_at (int reg, int unsignedp)
252b5132
RH
5315{
5316 if (imm_expr.X_op == O_constant
5317 && imm_expr.X_add_number >= -0x8000
5318 && imm_expr.X_add_number < 0x8000)
67c0d1eb
RS
5319 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
5320 AT, reg, BFD_RELOC_LO16);
252b5132
RH
5321 else
5322 {
67c0d1eb
RS
5323 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5324 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
252b5132
RH
5325 }
5326}
5327
5328/* Warn if an expression is not a constant. */
5329
5330static void
17a2f251 5331check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
252b5132
RH
5332{
5333 if (ex->X_op == O_big)
5334 as_bad (_("unsupported large constant"));
5335 else if (ex->X_op != O_constant)
9ee2a2d4
MR
5336 as_bad (_("Instruction %s requires absolute expression"),
5337 ip->insn_mo->name);
13757d0c 5338
9ee2a2d4
MR
5339 if (HAVE_32BIT_GPRS)
5340 normalize_constant_expr (ex);
252b5132
RH
5341}
5342
5343/* Count the leading zeroes by performing a binary chop. This is a
5344 bulky bit of source, but performance is a LOT better for the
5345 majority of values than a simple loop to count the bits:
5346 for (lcnt = 0; (lcnt < 32); lcnt++)
5347 if ((v) & (1 << (31 - lcnt)))
5348 break;
5349 However it is not code size friendly, and the gain will drop a bit
5350 on certain cached systems.
5351*/
5352#define COUNT_TOP_ZEROES(v) \
5353 (((v) & ~0xffff) == 0 \
5354 ? ((v) & ~0xff) == 0 \
5355 ? ((v) & ~0xf) == 0 \
5356 ? ((v) & ~0x3) == 0 \
5357 ? ((v) & ~0x1) == 0 \
5358 ? !(v) \
5359 ? 32 \
5360 : 31 \
5361 : 30 \
5362 : ((v) & ~0x7) == 0 \
5363 ? 29 \
5364 : 28 \
5365 : ((v) & ~0x3f) == 0 \
5366 ? ((v) & ~0x1f) == 0 \
5367 ? 27 \
5368 : 26 \
5369 : ((v) & ~0x7f) == 0 \
5370 ? 25 \
5371 : 24 \
5372 : ((v) & ~0xfff) == 0 \
5373 ? ((v) & ~0x3ff) == 0 \
5374 ? ((v) & ~0x1ff) == 0 \
5375 ? 23 \
5376 : 22 \
5377 : ((v) & ~0x7ff) == 0 \
5378 ? 21 \
5379 : 20 \
5380 : ((v) & ~0x3fff) == 0 \
5381 ? ((v) & ~0x1fff) == 0 \
5382 ? 19 \
5383 : 18 \
5384 : ((v) & ~0x7fff) == 0 \
5385 ? 17 \
5386 : 16 \
5387 : ((v) & ~0xffffff) == 0 \
5388 ? ((v) & ~0xfffff) == 0 \
5389 ? ((v) & ~0x3ffff) == 0 \
5390 ? ((v) & ~0x1ffff) == 0 \
5391 ? 15 \
5392 : 14 \
5393 : ((v) & ~0x7ffff) == 0 \
5394 ? 13 \
5395 : 12 \
5396 : ((v) & ~0x3fffff) == 0 \
5397 ? ((v) & ~0x1fffff) == 0 \
5398 ? 11 \
5399 : 10 \
5400 : ((v) & ~0x7fffff) == 0 \
5401 ? 9 \
5402 : 8 \
5403 : ((v) & ~0xfffffff) == 0 \
5404 ? ((v) & ~0x3ffffff) == 0 \
5405 ? ((v) & ~0x1ffffff) == 0 \
5406 ? 7 \
5407 : 6 \
5408 : ((v) & ~0x7ffffff) == 0 \
5409 ? 5 \
5410 : 4 \
5411 : ((v) & ~0x3fffffff) == 0 \
5412 ? ((v) & ~0x1fffffff) == 0 \
5413 ? 3 \
5414 : 2 \
5415 : ((v) & ~0x7fffffff) == 0 \
5416 ? 1 \
5417 : 0)
5418
5419/* load_register()
67c1ffbe 5420 * This routine generates the least number of instructions necessary to load
252b5132
RH
5421 * an absolute expression value into a register.
5422 */
5423static void
67c0d1eb 5424load_register (int reg, expressionS *ep, int dbl)
252b5132
RH
5425{
5426 int freg;
5427 expressionS hi32, lo32;
5428
5429 if (ep->X_op != O_big)
5430 {
9c2799c2 5431 gas_assert (ep->X_op == O_constant);
256ab948
TS
5432
5433 /* Sign-extending 32-bit constants makes their handling easier. */
2051e8c4
MR
5434 if (!dbl)
5435 normalize_constant_expr (ep);
256ab948
TS
5436
5437 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
252b5132
RH
5438 {
5439 /* We can handle 16 bit signed values with an addiu to
5440 $zero. No need to ever use daddiu here, since $zero and
5441 the result are always correct in 32 bit mode. */
67c0d1eb 5442 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
252b5132
RH
5443 return;
5444 }
5445 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
5446 {
5447 /* We can handle 16 bit unsigned values with an ori to
5448 $zero. */
67c0d1eb 5449 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
252b5132
RH
5450 return;
5451 }
256ab948 5452 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
252b5132
RH
5453 {
5454 /* 32 bit values require an lui. */
df58fc94 5455 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
252b5132 5456 if ((ep->X_add_number & 0xffff) != 0)
67c0d1eb 5457 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
252b5132
RH
5458 return;
5459 }
5460 }
5461
5462 /* The value is larger than 32 bits. */
5463
2051e8c4 5464 if (!dbl || HAVE_32BIT_GPRS)
252b5132 5465 {
55e08f71
NC
5466 char value[32];
5467
5468 sprintf_vma (value, ep->X_add_number);
20e1fcfd 5469 as_bad (_("Number (0x%s) larger than 32 bits"), value);
67c0d1eb 5470 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
252b5132
RH
5471 return;
5472 }
5473
5474 if (ep->X_op != O_big)
5475 {
5476 hi32 = *ep;
5477 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5478 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5479 hi32.X_add_number &= 0xffffffff;
5480 lo32 = *ep;
5481 lo32.X_add_number &= 0xffffffff;
5482 }
5483 else
5484 {
9c2799c2 5485 gas_assert (ep->X_add_number > 2);
252b5132
RH
5486 if (ep->X_add_number == 3)
5487 generic_bignum[3] = 0;
5488 else if (ep->X_add_number > 4)
5489 as_bad (_("Number larger than 64 bits"));
5490 lo32.X_op = O_constant;
5491 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
5492 hi32.X_op = O_constant;
5493 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
5494 }
5495
5496 if (hi32.X_add_number == 0)
5497 freg = 0;
5498 else
5499 {
5500 int shift, bit;
5501 unsigned long hi, lo;
5502
956cd1d6 5503 if (hi32.X_add_number == (offsetT) 0xffffffff)
beae10d5
KH
5504 {
5505 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
5506 {
67c0d1eb 5507 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
beae10d5
KH
5508 return;
5509 }
5510 if (lo32.X_add_number & 0x80000000)
5511 {
df58fc94 5512 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
252b5132 5513 if (lo32.X_add_number & 0xffff)
67c0d1eb 5514 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
beae10d5
KH
5515 return;
5516 }
5517 }
252b5132
RH
5518
5519 /* Check for 16bit shifted constant. We know that hi32 is
5520 non-zero, so start the mask on the first bit of the hi32
5521 value. */
5522 shift = 17;
5523 do
beae10d5
KH
5524 {
5525 unsigned long himask, lomask;
5526
5527 if (shift < 32)
5528 {
5529 himask = 0xffff >> (32 - shift);
5530 lomask = (0xffff << shift) & 0xffffffff;
5531 }
5532 else
5533 {
5534 himask = 0xffff << (shift - 32);
5535 lomask = 0;
5536 }
5537 if ((hi32.X_add_number & ~(offsetT) himask) == 0
5538 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
5539 {
5540 expressionS tmp;
5541
5542 tmp.X_op = O_constant;
5543 if (shift < 32)
5544 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
5545 | (lo32.X_add_number >> shift));
5546 else
5547 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
67c0d1eb 5548 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
df58fc94 5549 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
67c0d1eb 5550 reg, reg, (shift >= 32) ? shift - 32 : shift);
beae10d5
KH
5551 return;
5552 }
f9419b05 5553 ++shift;
beae10d5
KH
5554 }
5555 while (shift <= (64 - 16));
252b5132
RH
5556
5557 /* Find the bit number of the lowest one bit, and store the
5558 shifted value in hi/lo. */
5559 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
5560 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
5561 if (lo != 0)
5562 {
5563 bit = 0;
5564 while ((lo & 1) == 0)
5565 {
5566 lo >>= 1;
5567 ++bit;
5568 }
5569 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
5570 hi >>= bit;
5571 }
5572 else
5573 {
5574 bit = 32;
5575 while ((hi & 1) == 0)
5576 {
5577 hi >>= 1;
5578 ++bit;
5579 }
5580 lo = hi;
5581 hi = 0;
5582 }
5583
5584 /* Optimize if the shifted value is a (power of 2) - 1. */
5585 if ((hi == 0 && ((lo + 1) & lo) == 0)
5586 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
beae10d5
KH
5587 {
5588 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
252b5132 5589 if (shift != 0)
beae10d5 5590 {
252b5132
RH
5591 expressionS tmp;
5592
5593 /* This instruction will set the register to be all
5594 ones. */
beae10d5
KH
5595 tmp.X_op = O_constant;
5596 tmp.X_add_number = (offsetT) -1;
67c0d1eb 5597 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
beae10d5
KH
5598 if (bit != 0)
5599 {
5600 bit += shift;
df58fc94 5601 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
67c0d1eb 5602 reg, reg, (bit >= 32) ? bit - 32 : bit);
beae10d5 5603 }
df58fc94 5604 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
67c0d1eb 5605 reg, reg, (shift >= 32) ? shift - 32 : shift);
beae10d5
KH
5606 return;
5607 }
5608 }
252b5132
RH
5609
5610 /* Sign extend hi32 before calling load_register, because we can
5611 generally get better code when we load a sign extended value. */
5612 if ((hi32.X_add_number & 0x80000000) != 0)
beae10d5 5613 hi32.X_add_number |= ~(offsetT) 0xffffffff;
67c0d1eb 5614 load_register (reg, &hi32, 0);
252b5132
RH
5615 freg = reg;
5616 }
5617 if ((lo32.X_add_number & 0xffff0000) == 0)
5618 {
5619 if (freg != 0)
5620 {
df58fc94 5621 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
252b5132
RH
5622 freg = reg;
5623 }
5624 }
5625 else
5626 {
5627 expressionS mid16;
5628
956cd1d6 5629 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
beae10d5 5630 {
df58fc94
RS
5631 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5632 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
beae10d5
KH
5633 return;
5634 }
252b5132
RH
5635
5636 if (freg != 0)
5637 {
df58fc94 5638 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
252b5132
RH
5639 freg = reg;
5640 }
5641 mid16 = lo32;
5642 mid16.X_add_number >>= 16;
67c0d1eb 5643 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
df58fc94 5644 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
252b5132
RH
5645 freg = reg;
5646 }
5647 if ((lo32.X_add_number & 0xffff) != 0)
67c0d1eb 5648 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
252b5132
RH
5649}
5650
269137b2
TS
5651static inline void
5652load_delay_nop (void)
5653{
5654 if (!gpr_interlocks)
5655 macro_build (NULL, "nop", "");
5656}
5657
252b5132
RH
5658/* Load an address into a register. */
5659
5660static void
67c0d1eb 5661load_address (int reg, expressionS *ep, int *used_at)
252b5132 5662{
252b5132
RH
5663 if (ep->X_op != O_constant
5664 && ep->X_op != O_symbol)
5665 {
5666 as_bad (_("expression too complex"));
5667 ep->X_op = O_constant;
5668 }
5669
5670 if (ep->X_op == O_constant)
5671 {
67c0d1eb 5672 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
252b5132
RH
5673 return;
5674 }
5675
5676 if (mips_pic == NO_PIC)
5677 {
5678 /* If this is a reference to a GP relative symbol, we want
cdf6fd85 5679 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
252b5132
RH
5680 Otherwise we want
5681 lui $reg,<sym> (BFD_RELOC_HI16_S)
5682 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
d6bc6245 5683 If we have an addend, we always use the latter form.
76b3015f 5684
d6bc6245
TS
5685 With 64bit address space and a usable $at we want
5686 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5687 lui $at,<sym> (BFD_RELOC_HI16_S)
5688 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5689 daddiu $at,<sym> (BFD_RELOC_LO16)
5690 dsll32 $reg,0
3a482fd5 5691 daddu $reg,$reg,$at
76b3015f 5692
c03099e6 5693 If $at is already in use, we use a path which is suboptimal
d6bc6245
TS
5694 on superscalar processors.
5695 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5696 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5697 dsll $reg,16
5698 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5699 dsll $reg,16
5700 daddiu $reg,<sym> (BFD_RELOC_LO16)
6caf9ef4
TS
5701
5702 For GP relative symbols in 64bit address space we can use
5703 the same sequence as in 32bit address space. */
aed1a261 5704 if (HAVE_64BIT_SYMBOLS)
d6bc6245 5705 {
6caf9ef4
TS
5706 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5707 && !nopic_need_relax (ep->X_add_symbol, 1))
5708 {
5709 relax_start (ep->X_add_symbol);
5710 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5711 mips_gp_register, BFD_RELOC_GPREL16);
5712 relax_switch ();
5713 }
d6bc6245 5714
741fe287 5715 if (*used_at == 0 && mips_opts.at)
d6bc6245 5716 {
df58fc94
RS
5717 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5718 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
67c0d1eb
RS
5719 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5720 BFD_RELOC_MIPS_HIGHER);
5721 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
df58fc94 5722 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
67c0d1eb 5723 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
d6bc6245
TS
5724 *used_at = 1;
5725 }
5726 else
5727 {
df58fc94 5728 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
67c0d1eb
RS
5729 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5730 BFD_RELOC_MIPS_HIGHER);
df58fc94 5731 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
67c0d1eb 5732 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
df58fc94 5733 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
67c0d1eb 5734 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
d6bc6245 5735 }
6caf9ef4
TS
5736
5737 if (mips_relax.sequence)
5738 relax_end ();
d6bc6245 5739 }
252b5132
RH
5740 else
5741 {
d6bc6245 5742 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 5743 && !nopic_need_relax (ep->X_add_symbol, 1))
d6bc6245 5744 {
4d7206a2 5745 relax_start (ep->X_add_symbol);
67c0d1eb 5746 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
17a2f251 5747 mips_gp_register, BFD_RELOC_GPREL16);
4d7206a2 5748 relax_switch ();
d6bc6245 5749 }
67c0d1eb
RS
5750 macro_build_lui (ep, reg);
5751 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
5752 reg, reg, BFD_RELOC_LO16);
4d7206a2
RS
5753 if (mips_relax.sequence)
5754 relax_end ();
d6bc6245 5755 }
252b5132 5756 }
0a44bf69 5757 else if (!mips_big_got)
252b5132
RH
5758 {
5759 expressionS ex;
5760
5761 /* If this is a reference to an external symbol, we want
5762 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5763 Otherwise we want
5764 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5765 nop
5766 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
f5040a92
AO
5767 If there is a constant, it must be added in after.
5768
ed6fb7bd 5769 If we have NewABI, we want
f5040a92
AO
5770 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5771 unless we're referencing a global symbol with a non-zero
5772 offset, in which case cst must be added separately. */
ed6fb7bd
SC
5773 if (HAVE_NEWABI)
5774 {
f5040a92
AO
5775 if (ep->X_add_number)
5776 {
4d7206a2 5777 ex.X_add_number = ep->X_add_number;
f5040a92 5778 ep->X_add_number = 0;
4d7206a2 5779 relax_start (ep->X_add_symbol);
67c0d1eb
RS
5780 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5781 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
f5040a92
AO
5782 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5783 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5784 ex.X_op = O_constant;
67c0d1eb 5785 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 5786 reg, reg, BFD_RELOC_LO16);
f5040a92 5787 ep->X_add_number = ex.X_add_number;
4d7206a2 5788 relax_switch ();
f5040a92 5789 }
67c0d1eb 5790 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
17a2f251 5791 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4d7206a2
RS
5792 if (mips_relax.sequence)
5793 relax_end ();
ed6fb7bd
SC
5794 }
5795 else
5796 {
f5040a92
AO
5797 ex.X_add_number = ep->X_add_number;
5798 ep->X_add_number = 0;
67c0d1eb
RS
5799 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5800 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 5801 load_delay_nop ();
4d7206a2
RS
5802 relax_start (ep->X_add_symbol);
5803 relax_switch ();
67c0d1eb 5804 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
17a2f251 5805 BFD_RELOC_LO16);
4d7206a2 5806 relax_end ();
ed6fb7bd 5807
f5040a92
AO
5808 if (ex.X_add_number != 0)
5809 {
5810 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5811 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5812 ex.X_op = O_constant;
67c0d1eb 5813 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 5814 reg, reg, BFD_RELOC_LO16);
f5040a92 5815 }
252b5132
RH
5816 }
5817 }
0a44bf69 5818 else if (mips_big_got)
252b5132
RH
5819 {
5820 expressionS ex;
252b5132
RH
5821
5822 /* This is the large GOT case. If this is a reference to an
5823 external symbol, we want
5824 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5825 addu $reg,$reg,$gp
5826 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
f5040a92
AO
5827
5828 Otherwise, for a reference to a local symbol in old ABI, we want
252b5132
RH
5829 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5830 nop
5831 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
684022ea 5832 If there is a constant, it must be added in after.
f5040a92
AO
5833
5834 In the NewABI, for local symbols, with or without offsets, we want:
438c16b8
TS
5835 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5836 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
f5040a92 5837 */
438c16b8
TS
5838 if (HAVE_NEWABI)
5839 {
4d7206a2 5840 ex.X_add_number = ep->X_add_number;
f5040a92 5841 ep->X_add_number = 0;
4d7206a2 5842 relax_start (ep->X_add_symbol);
df58fc94 5843 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
5844 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5845 reg, reg, mips_gp_register);
5846 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
5847 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
f5040a92
AO
5848 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5849 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5850 else if (ex.X_add_number)
5851 {
5852 ex.X_op = O_constant;
67c0d1eb
RS
5853 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5854 BFD_RELOC_LO16);
f5040a92
AO
5855 }
5856
5857 ep->X_add_number = ex.X_add_number;
4d7206a2 5858 relax_switch ();
67c0d1eb 5859 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
17a2f251 5860 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
67c0d1eb
RS
5861 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5862 BFD_RELOC_MIPS_GOT_OFST);
4d7206a2 5863 relax_end ();
438c16b8 5864 }
252b5132 5865 else
438c16b8 5866 {
f5040a92
AO
5867 ex.X_add_number = ep->X_add_number;
5868 ep->X_add_number = 0;
4d7206a2 5869 relax_start (ep->X_add_symbol);
df58fc94 5870 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
5871 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5872 reg, reg, mips_gp_register);
5873 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
5874 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4d7206a2
RS
5875 relax_switch ();
5876 if (reg_needs_delay (mips_gp_register))
438c16b8
TS
5877 {
5878 /* We need a nop before loading from $gp. This special
5879 check is required because the lui which starts the main
5880 instruction stream does not refer to $gp, and so will not
5881 insert the nop which may be required. */
67c0d1eb 5882 macro_build (NULL, "nop", "");
438c16b8 5883 }
67c0d1eb 5884 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
17a2f251 5885 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 5886 load_delay_nop ();
67c0d1eb 5887 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
17a2f251 5888 BFD_RELOC_LO16);
4d7206a2 5889 relax_end ();
438c16b8 5890
f5040a92
AO
5891 if (ex.X_add_number != 0)
5892 {
5893 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5894 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5895 ex.X_op = O_constant;
67c0d1eb
RS
5896 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5897 BFD_RELOC_LO16);
f5040a92 5898 }
252b5132
RH
5899 }
5900 }
252b5132
RH
5901 else
5902 abort ();
8fc2e39e 5903
741fe287 5904 if (!mips_opts.at && *used_at == 1)
8fc2e39e 5905 as_bad (_("Macro used $at after \".set noat\""));
252b5132
RH
5906}
5907
ea1fb5dc
RS
5908/* Move the contents of register SOURCE into register DEST. */
5909
5910static void
67c0d1eb 5911move_register (int dest, int source)
ea1fb5dc 5912{
df58fc94
RS
5913 /* Prefer to use a 16-bit microMIPS instruction unless the previous
5914 instruction specifically requires a 32-bit one. */
5915 if (mips_opts.micromips
5916 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
5917 macro_build (NULL, "move", "mp,mj", dest, source );
5918 else
5919 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
5920 dest, source, 0);
ea1fb5dc
RS
5921}
5922
4d7206a2 5923/* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
f6a22291
MR
5924 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
5925 The two alternatives are:
4d7206a2
RS
5926
5927 Global symbol Local sybmol
5928 ------------- ------------
5929 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
5930 ... ...
5931 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
5932
5933 load_got_offset emits the first instruction and add_got_offset
f6a22291
MR
5934 emits the second for a 16-bit offset or add_got_offset_hilo emits
5935 a sequence to add a 32-bit offset using a scratch register. */
4d7206a2
RS
5936
5937static void
67c0d1eb 5938load_got_offset (int dest, expressionS *local)
4d7206a2
RS
5939{
5940 expressionS global;
5941
5942 global = *local;
5943 global.X_add_number = 0;
5944
5945 relax_start (local->X_add_symbol);
67c0d1eb
RS
5946 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5947 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4d7206a2 5948 relax_switch ();
67c0d1eb
RS
5949 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5950 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4d7206a2
RS
5951 relax_end ();
5952}
5953
5954static void
67c0d1eb 5955add_got_offset (int dest, expressionS *local)
4d7206a2
RS
5956{
5957 expressionS global;
5958
5959 global.X_op = O_constant;
5960 global.X_op_symbol = NULL;
5961 global.X_add_symbol = NULL;
5962 global.X_add_number = local->X_add_number;
5963
5964 relax_start (local->X_add_symbol);
67c0d1eb 5965 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4d7206a2
RS
5966 dest, dest, BFD_RELOC_LO16);
5967 relax_switch ();
67c0d1eb 5968 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4d7206a2
RS
5969 relax_end ();
5970}
5971
f6a22291
MR
5972static void
5973add_got_offset_hilo (int dest, expressionS *local, int tmp)
5974{
5975 expressionS global;
5976 int hold_mips_optimize;
5977
5978 global.X_op = O_constant;
5979 global.X_op_symbol = NULL;
5980 global.X_add_symbol = NULL;
5981 global.X_add_number = local->X_add_number;
5982
5983 relax_start (local->X_add_symbol);
5984 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
5985 relax_switch ();
5986 /* Set mips_optimize around the lui instruction to avoid
5987 inserting an unnecessary nop after the lw. */
5988 hold_mips_optimize = mips_optimize;
5989 mips_optimize = 2;
5990 macro_build_lui (&global, tmp);
5991 mips_optimize = hold_mips_optimize;
5992 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
5993 relax_end ();
5994
5995 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
5996}
5997
df58fc94
RS
5998/* Emit a sequence of instructions to emulate a branch likely operation.
5999 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6000 is its complementing branch with the original condition negated.
6001 CALL is set if the original branch specified the link operation.
6002 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6003
6004 Code like this is produced in the noreorder mode:
6005
6006 BRNEG <args>, 1f
6007 nop
6008 b <sym>
6009 delay slot (executed only if branch taken)
6010 1:
6011
6012 or, if CALL is set:
6013
6014 BRNEG <args>, 1f
6015 nop
6016 bal <sym>
6017 delay slot (executed only if branch taken)
6018 1:
6019
6020 In the reorder mode the delay slot would be filled with a nop anyway,
6021 so code produced is simply:
6022
6023 BR <args>, <sym>
6024 nop
6025
6026 This function is used when producing code for the microMIPS ASE that
6027 does not implement branch likely instructions in hardware. */
6028
6029static void
6030macro_build_branch_likely (const char *br, const char *brneg,
6031 int call, expressionS *ep, const char *fmt,
6032 unsigned int sreg, unsigned int treg)
6033{
6034 int noreorder = mips_opts.noreorder;
6035 expressionS expr1;
6036
6037 gas_assert (mips_opts.micromips);
6038 start_noreorder ();
6039 if (noreorder)
6040 {
6041 micromips_label_expr (&expr1);
6042 macro_build (&expr1, brneg, fmt, sreg, treg);
6043 macro_build (NULL, "nop", "");
6044 macro_build (ep, call ? "bal" : "b", "p");
6045
6046 /* Set to true so that append_insn adds a label. */
6047 emit_branch_likely_macro = TRUE;
6048 }
6049 else
6050 {
6051 macro_build (ep, br, fmt, sreg, treg);
6052 macro_build (NULL, "nop", "");
6053 }
6054 end_noreorder ();
6055}
6056
6057/* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6058 the condition code tested. EP specifies the branch target. */
6059
6060static void
6061macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
6062{
6063 const int call = 0;
6064 const char *brneg;
6065 const char *br;
6066
6067 switch (type)
6068 {
6069 case M_BC1FL:
6070 br = "bc1f";
6071 brneg = "bc1t";
6072 break;
6073 case M_BC1TL:
6074 br = "bc1t";
6075 brneg = "bc1f";
6076 break;
6077 case M_BC2FL:
6078 br = "bc2f";
6079 brneg = "bc2t";
6080 break;
6081 case M_BC2TL:
6082 br = "bc2t";
6083 brneg = "bc2f";
6084 break;
6085 default:
6086 abort ();
6087 }
6088 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
6089}
6090
6091/* Emit a two-argument branch macro specified by TYPE, using SREG as
6092 the register tested. EP specifies the branch target. */
6093
6094static void
6095macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
6096{
6097 const char *brneg = NULL;
6098 const char *br;
6099 int call = 0;
6100
6101 switch (type)
6102 {
6103 case M_BGEZ:
6104 br = "bgez";
6105 break;
6106 case M_BGEZL:
6107 br = mips_opts.micromips ? "bgez" : "bgezl";
6108 brneg = "bltz";
6109 break;
6110 case M_BGEZALL:
6111 gas_assert (mips_opts.micromips);
6112 br = "bgezals";
6113 brneg = "bltz";
6114 call = 1;
6115 break;
6116 case M_BGTZ:
6117 br = "bgtz";
6118 break;
6119 case M_BGTZL:
6120 br = mips_opts.micromips ? "bgtz" : "bgtzl";
6121 brneg = "blez";
6122 break;
6123 case M_BLEZ:
6124 br = "blez";
6125 break;
6126 case M_BLEZL:
6127 br = mips_opts.micromips ? "blez" : "blezl";
6128 brneg = "bgtz";
6129 break;
6130 case M_BLTZ:
6131 br = "bltz";
6132 break;
6133 case M_BLTZL:
6134 br = mips_opts.micromips ? "bltz" : "bltzl";
6135 brneg = "bgez";
6136 break;
6137 case M_BLTZALL:
6138 gas_assert (mips_opts.micromips);
6139 br = "bltzals";
6140 brneg = "bgez";
6141 call = 1;
6142 break;
6143 default:
6144 abort ();
6145 }
6146 if (mips_opts.micromips && brneg)
6147 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
6148 else
6149 macro_build (ep, br, "s,p", sreg);
6150}
6151
6152/* Emit a three-argument branch macro specified by TYPE, using SREG and
6153 TREG as the registers tested. EP specifies the branch target. */
6154
6155static void
6156macro_build_branch_rsrt (int type, expressionS *ep,
6157 unsigned int sreg, unsigned int treg)
6158{
6159 const char *brneg = NULL;
6160 const int call = 0;
6161 const char *br;
6162
6163 switch (type)
6164 {
6165 case M_BEQ:
6166 case M_BEQ_I:
6167 br = "beq";
6168 break;
6169 case M_BEQL:
6170 case M_BEQL_I:
6171 br = mips_opts.micromips ? "beq" : "beql";
6172 brneg = "bne";
6173 break;
6174 case M_BNE:
6175 case M_BNE_I:
6176 br = "bne";
6177 break;
6178 case M_BNEL:
6179 case M_BNEL_I:
6180 br = mips_opts.micromips ? "bne" : "bnel";
6181 brneg = "beq";
6182 break;
6183 default:
6184 abort ();
6185 }
6186 if (mips_opts.micromips && brneg)
6187 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
6188 else
6189 macro_build (ep, br, "s,t,p", sreg, treg);
6190}
6191
252b5132
RH
6192/*
6193 * Build macros
6194 * This routine implements the seemingly endless macro or synthesized
6195 * instructions and addressing modes in the mips assembly language. Many
6196 * of these macros are simple and are similar to each other. These could
67c1ffbe 6197 * probably be handled by some kind of table or grammar approach instead of
252b5132
RH
6198 * this verbose method. Others are not simple macros but are more like
6199 * optimizing code generation.
6200 * One interesting optimization is when several store macros appear
67c1ffbe 6201 * consecutively that would load AT with the upper half of the same address.
252b5132
RH
6202 * The ensuing load upper instructions are ommited. This implies some kind
6203 * of global optimization. We currently only optimize within a single macro.
6204 * For many of the load and store macros if the address is specified as a
6205 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6206 * first load register 'at' with zero and use it as the base register. The
6207 * mips assembler simply uses register $zero. Just one tiny optimization
6208 * we're missing.
6209 */
6210static void
17a2f251 6211macro (struct mips_cl_insn *ip)
252b5132 6212{
741fe287
MR
6213 unsigned int treg, sreg, dreg, breg;
6214 unsigned int tempreg;
252b5132 6215 int mask;
43841e91 6216 int used_at = 0;
df58fc94 6217 expressionS label_expr;
252b5132 6218 expressionS expr1;
df58fc94 6219 expressionS *ep;
252b5132
RH
6220 const char *s;
6221 const char *s2;
6222 const char *fmt;
6223 int likely = 0;
252b5132 6224 int coproc = 0;
df58fc94 6225 int off12 = 0;
1abe91b1 6226 int call = 0;
df58fc94
RS
6227 int jals = 0;
6228 int dbl = 0;
6229 int imm = 0;
6230 int ust = 0;
6231 int lp = 0;
6232 int ab = 0;
252b5132 6233 int off;
67c0d1eb 6234 offsetT maxnum;
252b5132 6235 bfd_reloc_code_real_type r;
252b5132
RH
6236 int hold_mips_optimize;
6237
9c2799c2 6238 gas_assert (! mips_opts.mips16);
252b5132 6239
df58fc94
RS
6240 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
6241 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
6242 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
252b5132
RH
6243 mask = ip->insn_mo->mask;
6244
df58fc94
RS
6245 label_expr.X_op = O_constant;
6246 label_expr.X_op_symbol = NULL;
6247 label_expr.X_add_symbol = NULL;
6248 label_expr.X_add_number = 0;
6249
252b5132
RH
6250 expr1.X_op = O_constant;
6251 expr1.X_op_symbol = NULL;
6252 expr1.X_add_symbol = NULL;
6253 expr1.X_add_number = 1;
6254
6255 switch (mask)
6256 {
6257 case M_DABS:
6258 dbl = 1;
6259 case M_ABS:
df58fc94
RS
6260 /* bgez $a0,1f
6261 move v0,$a0
6262 sub v0,$zero,$a0
6263 1:
6264 */
252b5132 6265
7d10b47d 6266 start_noreorder ();
252b5132 6267
df58fc94
RS
6268 if (mips_opts.micromips)
6269 micromips_label_expr (&label_expr);
6270 else
6271 label_expr.X_add_number = 8;
6272 macro_build (&label_expr, "bgez", "s,p", sreg);
252b5132 6273 if (dreg == sreg)
a605d2b3 6274 macro_build (NULL, "nop", "");
252b5132 6275 else
67c0d1eb
RS
6276 move_register (dreg, sreg);
6277 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
df58fc94
RS
6278 if (mips_opts.micromips)
6279 micromips_add_label ();
252b5132 6280
7d10b47d 6281 end_noreorder ();
8fc2e39e 6282 break;
252b5132
RH
6283
6284 case M_ADD_I:
6285 s = "addi";
6286 s2 = "add";
6287 goto do_addi;
6288 case M_ADDU_I:
6289 s = "addiu";
6290 s2 = "addu";
6291 goto do_addi;
6292 case M_DADD_I:
6293 dbl = 1;
6294 s = "daddi";
6295 s2 = "dadd";
df58fc94
RS
6296 if (!mips_opts.micromips)
6297 goto do_addi;
6298 if (imm_expr.X_op == O_constant
6299 && imm_expr.X_add_number >= -0x200
6300 && imm_expr.X_add_number < 0x200)
6301 {
6302 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
6303 break;
6304 }
6305 goto do_addi_i;
252b5132
RH
6306 case M_DADDU_I:
6307 dbl = 1;
6308 s = "daddiu";
6309 s2 = "daddu";
6310 do_addi:
6311 if (imm_expr.X_op == O_constant
6312 && imm_expr.X_add_number >= -0x8000
6313 && imm_expr.X_add_number < 0x8000)
6314 {
67c0d1eb 6315 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
8fc2e39e 6316 break;
252b5132 6317 }
df58fc94 6318 do_addi_i:
8fc2e39e 6319 used_at = 1;
67c0d1eb
RS
6320 load_register (AT, &imm_expr, dbl);
6321 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
252b5132
RH
6322 break;
6323
6324 case M_AND_I:
6325 s = "andi";
6326 s2 = "and";
6327 goto do_bit;
6328 case M_OR_I:
6329 s = "ori";
6330 s2 = "or";
6331 goto do_bit;
6332 case M_NOR_I:
6333 s = "";
6334 s2 = "nor";
6335 goto do_bit;
6336 case M_XOR_I:
6337 s = "xori";
6338 s2 = "xor";
6339 do_bit:
6340 if (imm_expr.X_op == O_constant
6341 && imm_expr.X_add_number >= 0
6342 && imm_expr.X_add_number < 0x10000)
6343 {
6344 if (mask != M_NOR_I)
67c0d1eb 6345 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
252b5132
RH
6346 else
6347 {
67c0d1eb
RS
6348 macro_build (&imm_expr, "ori", "t,r,i",
6349 treg, sreg, BFD_RELOC_LO16);
6350 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
252b5132 6351 }
8fc2e39e 6352 break;
252b5132
RH
6353 }
6354
8fc2e39e 6355 used_at = 1;
67c0d1eb
RS
6356 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6357 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
252b5132
RH
6358 break;
6359
8b082fb1
TS
6360 case M_BALIGN:
6361 switch (imm_expr.X_add_number)
6362 {
6363 case 0:
6364 macro_build (NULL, "nop", "");
6365 break;
6366 case 2:
6367 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
6368 break;
6369 default:
6370 macro_build (NULL, "balign", "t,s,2", treg, sreg,
90ecf173 6371 (int) imm_expr.X_add_number);
8b082fb1
TS
6372 break;
6373 }
6374 break;
6375
df58fc94
RS
6376 case M_BC1FL:
6377 case M_BC1TL:
6378 case M_BC2FL:
6379 case M_BC2TL:
6380 gas_assert (mips_opts.micromips);
6381 macro_build_branch_ccl (mask, &offset_expr,
6382 EXTRACT_OPERAND (1, BCC, *ip));
6383 break;
6384
252b5132 6385 case M_BEQ_I:
252b5132 6386 case M_BEQL_I:
252b5132 6387 case M_BNE_I:
252b5132 6388 case M_BNEL_I:
252b5132 6389 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
df58fc94
RS
6390 treg = 0;
6391 else
252b5132 6392 {
df58fc94
RS
6393 treg = AT;
6394 used_at = 1;
6395 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
252b5132 6396 }
df58fc94
RS
6397 /* Fall through. */
6398 case M_BEQL:
6399 case M_BNEL:
6400 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
252b5132
RH
6401 break;
6402
6403 case M_BGEL:
6404 likely = 1;
6405 case M_BGE:
6406 if (treg == 0)
df58fc94
RS
6407 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
6408 else if (sreg == 0)
6409 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
6410 else
252b5132 6411 {
df58fc94
RS
6412 used_at = 1;
6413 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6414 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6415 &offset_expr, AT, ZERO);
252b5132 6416 }
df58fc94
RS
6417 break;
6418
6419 case M_BGEZL:
6420 case M_BGEZALL:
6421 case M_BGTZL:
6422 case M_BLEZL:
6423 case M_BLTZL:
6424 case M_BLTZALL:
6425 macro_build_branch_rs (mask, &offset_expr, sreg);
252b5132
RH
6426 break;
6427
6428 case M_BGTL_I:
6429 likely = 1;
6430 case M_BGT_I:
90ecf173 6431 /* Check for > max integer. */
252b5132 6432 maxnum = 0x7fffffff;
ca4e0257 6433 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
252b5132
RH
6434 {
6435 maxnum <<= 16;
6436 maxnum |= 0xffff;
6437 maxnum <<= 16;
6438 maxnum |= 0xffff;
6439 }
6440 if (imm_expr.X_op == O_constant
6441 && imm_expr.X_add_number >= maxnum
ca4e0257 6442 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
252b5132
RH
6443 {
6444 do_false:
90ecf173 6445 /* Result is always false. */
252b5132 6446 if (! likely)
a605d2b3 6447 macro_build (NULL, "nop", "");
252b5132 6448 else
df58fc94 6449 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
8fc2e39e 6450 break;
252b5132
RH
6451 }
6452 if (imm_expr.X_op != O_constant)
6453 as_bad (_("Unsupported large constant"));
f9419b05 6454 ++imm_expr.X_add_number;
252b5132
RH
6455 /* FALLTHROUGH */
6456 case M_BGE_I:
6457 case M_BGEL_I:
6458 if (mask == M_BGEL_I)
6459 likely = 1;
6460 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6461 {
df58fc94
RS
6462 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
6463 &offset_expr, sreg);
8fc2e39e 6464 break;
252b5132
RH
6465 }
6466 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6467 {
df58fc94
RS
6468 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
6469 &offset_expr, sreg);
8fc2e39e 6470 break;
252b5132
RH
6471 }
6472 maxnum = 0x7fffffff;
ca4e0257 6473 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
252b5132
RH
6474 {
6475 maxnum <<= 16;
6476 maxnum |= 0xffff;
6477 maxnum <<= 16;
6478 maxnum |= 0xffff;
6479 }
6480 maxnum = - maxnum - 1;
6481 if (imm_expr.X_op == O_constant
6482 && imm_expr.X_add_number <= maxnum
ca4e0257 6483 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
252b5132
RH
6484 {
6485 do_true:
6486 /* result is always true */
6487 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
67c0d1eb 6488 macro_build (&offset_expr, "b", "p");
8fc2e39e 6489 break;
252b5132 6490 }
8fc2e39e 6491 used_at = 1;
67c0d1eb 6492 set_at (sreg, 0);
df58fc94
RS
6493 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6494 &offset_expr, AT, ZERO);
252b5132
RH
6495 break;
6496
6497 case M_BGEUL:
6498 likely = 1;
6499 case M_BGEU:
6500 if (treg == 0)
6501 goto do_true;
df58fc94
RS
6502 else if (sreg == 0)
6503 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6504 &offset_expr, ZERO, treg);
6505 else
252b5132 6506 {
df58fc94
RS
6507 used_at = 1;
6508 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6509 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6510 &offset_expr, AT, ZERO);
252b5132 6511 }
252b5132
RH
6512 break;
6513
6514 case M_BGTUL_I:
6515 likely = 1;
6516 case M_BGTU_I:
6517 if (sreg == 0
ca4e0257 6518 || (HAVE_32BIT_GPRS
252b5132 6519 && imm_expr.X_op == O_constant
f01dc953 6520 && imm_expr.X_add_number == -1))
252b5132
RH
6521 goto do_false;
6522 if (imm_expr.X_op != O_constant)
6523 as_bad (_("Unsupported large constant"));
f9419b05 6524 ++imm_expr.X_add_number;
252b5132
RH
6525 /* FALLTHROUGH */
6526 case M_BGEU_I:
6527 case M_BGEUL_I:
6528 if (mask == M_BGEUL_I)
6529 likely = 1;
6530 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6531 goto do_true;
df58fc94
RS
6532 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6533 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6534 &offset_expr, sreg, ZERO);
6535 else
252b5132 6536 {
df58fc94
RS
6537 used_at = 1;
6538 set_at (sreg, 1);
6539 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6540 &offset_expr, AT, ZERO);
252b5132 6541 }
252b5132
RH
6542 break;
6543
6544 case M_BGTL:
6545 likely = 1;
6546 case M_BGT:
6547 if (treg == 0)
df58fc94
RS
6548 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
6549 else if (sreg == 0)
6550 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
6551 else
252b5132 6552 {
df58fc94
RS
6553 used_at = 1;
6554 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6555 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6556 &offset_expr, AT, ZERO);
252b5132 6557 }
252b5132
RH
6558 break;
6559
6560 case M_BGTUL:
6561 likely = 1;
6562 case M_BGTU:
6563 if (treg == 0)
df58fc94
RS
6564 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6565 &offset_expr, sreg, ZERO);
6566 else if (sreg == 0)
6567 goto do_false;
6568 else
252b5132 6569 {
df58fc94
RS
6570 used_at = 1;
6571 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6572 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6573 &offset_expr, AT, ZERO);
252b5132 6574 }
252b5132
RH
6575 break;
6576
6577 case M_BLEL:
6578 likely = 1;
6579 case M_BLE:
6580 if (treg == 0)
df58fc94
RS
6581 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6582 else if (sreg == 0)
6583 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
6584 else
252b5132 6585 {
df58fc94
RS
6586 used_at = 1;
6587 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6588 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6589 &offset_expr, AT, ZERO);
252b5132 6590 }
252b5132
RH
6591 break;
6592
6593 case M_BLEL_I:
6594 likely = 1;
6595 case M_BLE_I:
6596 maxnum = 0x7fffffff;
ca4e0257 6597 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
252b5132
RH
6598 {
6599 maxnum <<= 16;
6600 maxnum |= 0xffff;
6601 maxnum <<= 16;
6602 maxnum |= 0xffff;
6603 }
6604 if (imm_expr.X_op == O_constant
6605 && imm_expr.X_add_number >= maxnum
ca4e0257 6606 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
252b5132
RH
6607 goto do_true;
6608 if (imm_expr.X_op != O_constant)
6609 as_bad (_("Unsupported large constant"));
f9419b05 6610 ++imm_expr.X_add_number;
252b5132
RH
6611 /* FALLTHROUGH */
6612 case M_BLT_I:
6613 case M_BLTL_I:
6614 if (mask == M_BLTL_I)
6615 likely = 1;
6616 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
df58fc94
RS
6617 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6618 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6619 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6620 else
252b5132 6621 {
df58fc94
RS
6622 used_at = 1;
6623 set_at (sreg, 0);
6624 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6625 &offset_expr, AT, ZERO);
252b5132 6626 }
252b5132
RH
6627 break;
6628
6629 case M_BLEUL:
6630 likely = 1;
6631 case M_BLEU:
6632 if (treg == 0)
df58fc94
RS
6633 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6634 &offset_expr, sreg, ZERO);
6635 else if (sreg == 0)
6636 goto do_true;
6637 else
252b5132 6638 {
df58fc94
RS
6639 used_at = 1;
6640 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6641 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6642 &offset_expr, AT, ZERO);
252b5132 6643 }
252b5132
RH
6644 break;
6645
6646 case M_BLEUL_I:
6647 likely = 1;
6648 case M_BLEU_I:
6649 if (sreg == 0
ca4e0257 6650 || (HAVE_32BIT_GPRS
252b5132 6651 && imm_expr.X_op == O_constant
f01dc953 6652 && imm_expr.X_add_number == -1))
252b5132
RH
6653 goto do_true;
6654 if (imm_expr.X_op != O_constant)
6655 as_bad (_("Unsupported large constant"));
f9419b05 6656 ++imm_expr.X_add_number;
252b5132
RH
6657 /* FALLTHROUGH */
6658 case M_BLTU_I:
6659 case M_BLTUL_I:
6660 if (mask == M_BLTUL_I)
6661 likely = 1;
6662 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6663 goto do_false;
df58fc94
RS
6664 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6665 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6666 &offset_expr, sreg, ZERO);
6667 else
252b5132 6668 {
df58fc94
RS
6669 used_at = 1;
6670 set_at (sreg, 1);
6671 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6672 &offset_expr, AT, ZERO);
252b5132 6673 }
252b5132
RH
6674 break;
6675
6676 case M_BLTL:
6677 likely = 1;
6678 case M_BLT:
6679 if (treg == 0)
df58fc94
RS
6680 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6681 else if (sreg == 0)
6682 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
6683 else
252b5132 6684 {
df58fc94
RS
6685 used_at = 1;
6686 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6687 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6688 &offset_expr, AT, ZERO);
252b5132 6689 }
252b5132
RH
6690 break;
6691
6692 case M_BLTUL:
6693 likely = 1;
6694 case M_BLTU:
6695 if (treg == 0)
6696 goto do_false;
df58fc94
RS
6697 else if (sreg == 0)
6698 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6699 &offset_expr, ZERO, treg);
6700 else
252b5132 6701 {
df58fc94
RS
6702 used_at = 1;
6703 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6704 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6705 &offset_expr, AT, ZERO);
252b5132 6706 }
252b5132
RH
6707 break;
6708
5f74bc13
CD
6709 case M_DEXT:
6710 {
d5818fca
MR
6711 /* Use unsigned arithmetic. */
6712 addressT pos;
6713 addressT size;
5f74bc13 6714
90ecf173 6715 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5f74bc13
CD
6716 {
6717 as_bad (_("Unsupported large constant"));
6718 pos = size = 1;
6719 }
6720 else
6721 {
d5818fca
MR
6722 pos = imm_expr.X_add_number;
6723 size = imm2_expr.X_add_number;
5f74bc13
CD
6724 }
6725
6726 if (pos > 63)
6727 {
d5818fca 6728 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5f74bc13
CD
6729 pos = 1;
6730 }
90ecf173 6731 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5f74bc13
CD
6732 {
6733 as_bad (_("Improper extract size (%lu, position %lu)"),
d5818fca 6734 (unsigned long) size, (unsigned long) pos);
5f74bc13
CD
6735 size = 1;
6736 }
6737
6738 if (size <= 32 && pos < 32)
6739 {
6740 s = "dext";
6741 fmt = "t,r,+A,+C";
6742 }
6743 else if (size <= 32)
6744 {
6745 s = "dextu";
6746 fmt = "t,r,+E,+H";
6747 }
6748 else
6749 {
6750 s = "dextm";
6751 fmt = "t,r,+A,+G";
6752 }
d5818fca
MR
6753 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6754 (int) (size - 1));
5f74bc13 6755 }
8fc2e39e 6756 break;
5f74bc13
CD
6757
6758 case M_DINS:
6759 {
d5818fca
MR
6760 /* Use unsigned arithmetic. */
6761 addressT pos;
6762 addressT size;
5f74bc13 6763
90ecf173 6764 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5f74bc13
CD
6765 {
6766 as_bad (_("Unsupported large constant"));
6767 pos = size = 1;
6768 }
6769 else
6770 {
d5818fca
MR
6771 pos = imm_expr.X_add_number;
6772 size = imm2_expr.X_add_number;
5f74bc13
CD
6773 }
6774
6775 if (pos > 63)
6776 {
d5818fca 6777 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5f74bc13
CD
6778 pos = 1;
6779 }
90ecf173 6780 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5f74bc13
CD
6781 {
6782 as_bad (_("Improper insert size (%lu, position %lu)"),
d5818fca 6783 (unsigned long) size, (unsigned long) pos);
5f74bc13
CD
6784 size = 1;
6785 }
6786
6787 if (pos < 32 && (pos + size - 1) < 32)
6788 {
6789 s = "dins";
6790 fmt = "t,r,+A,+B";
6791 }
6792 else if (pos >= 32)
6793 {
6794 s = "dinsu";
6795 fmt = "t,r,+E,+F";
6796 }
6797 else
6798 {
6799 s = "dinsm";
6800 fmt = "t,r,+A,+F";
6801 }
750bdd57
AS
6802 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6803 (int) (pos + size - 1));
5f74bc13 6804 }
8fc2e39e 6805 break;
5f74bc13 6806
252b5132
RH
6807 case M_DDIV_3:
6808 dbl = 1;
6809 case M_DIV_3:
6810 s = "mflo";
6811 goto do_div3;
6812 case M_DREM_3:
6813 dbl = 1;
6814 case M_REM_3:
6815 s = "mfhi";
6816 do_div3:
6817 if (treg == 0)
6818 {
6819 as_warn (_("Divide by zero."));
6820 if (mips_trap)
df58fc94 6821 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
252b5132 6822 else
df58fc94 6823 macro_build (NULL, "break", BRK_FMT, 7);
8fc2e39e 6824 break;
252b5132
RH
6825 }
6826
7d10b47d 6827 start_noreorder ();
252b5132
RH
6828 if (mips_trap)
6829 {
df58fc94 6830 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
67c0d1eb 6831 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
252b5132
RH
6832 }
6833 else
6834 {
df58fc94
RS
6835 if (mips_opts.micromips)
6836 micromips_label_expr (&label_expr);
6837 else
6838 label_expr.X_add_number = 8;
6839 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
67c0d1eb 6840 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
df58fc94
RS
6841 macro_build (NULL, "break", BRK_FMT, 7);
6842 if (mips_opts.micromips)
6843 micromips_add_label ();
252b5132
RH
6844 }
6845 expr1.X_add_number = -1;
8fc2e39e 6846 used_at = 1;
f6a22291 6847 load_register (AT, &expr1, dbl);
df58fc94
RS
6848 if (mips_opts.micromips)
6849 micromips_label_expr (&label_expr);
6850 else
6851 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
6852 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
252b5132
RH
6853 if (dbl)
6854 {
6855 expr1.X_add_number = 1;
f6a22291 6856 load_register (AT, &expr1, dbl);
df58fc94 6857 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
252b5132
RH
6858 }
6859 else
6860 {
6861 expr1.X_add_number = 0x80000000;
df58fc94 6862 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
252b5132
RH
6863 }
6864 if (mips_trap)
6865 {
df58fc94 6866 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
252b5132
RH
6867 /* We want to close the noreorder block as soon as possible, so
6868 that later insns are available for delay slot filling. */
7d10b47d 6869 end_noreorder ();
252b5132
RH
6870 }
6871 else
6872 {
df58fc94
RS
6873 if (mips_opts.micromips)
6874 micromips_label_expr (&label_expr);
6875 else
6876 label_expr.X_add_number = 8;
6877 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
a605d2b3 6878 macro_build (NULL, "nop", "");
252b5132
RH
6879
6880 /* We want to close the noreorder block as soon as possible, so
6881 that later insns are available for delay slot filling. */
7d10b47d 6882 end_noreorder ();
252b5132 6883
df58fc94 6884 macro_build (NULL, "break", BRK_FMT, 6);
252b5132 6885 }
df58fc94
RS
6886 if (mips_opts.micromips)
6887 micromips_add_label ();
6888 macro_build (NULL, s, MFHL_FMT, dreg);
252b5132
RH
6889 break;
6890
6891 case M_DIV_3I:
6892 s = "div";
6893 s2 = "mflo";
6894 goto do_divi;
6895 case M_DIVU_3I:
6896 s = "divu";
6897 s2 = "mflo";
6898 goto do_divi;
6899 case M_REM_3I:
6900 s = "div";
6901 s2 = "mfhi";
6902 goto do_divi;
6903 case M_REMU_3I:
6904 s = "divu";
6905 s2 = "mfhi";
6906 goto do_divi;
6907 case M_DDIV_3I:
6908 dbl = 1;
6909 s = "ddiv";
6910 s2 = "mflo";
6911 goto do_divi;
6912 case M_DDIVU_3I:
6913 dbl = 1;
6914 s = "ddivu";
6915 s2 = "mflo";
6916 goto do_divi;
6917 case M_DREM_3I:
6918 dbl = 1;
6919 s = "ddiv";
6920 s2 = "mfhi";
6921 goto do_divi;
6922 case M_DREMU_3I:
6923 dbl = 1;
6924 s = "ddivu";
6925 s2 = "mfhi";
6926 do_divi:
6927 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6928 {
6929 as_warn (_("Divide by zero."));
6930 if (mips_trap)
df58fc94 6931 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
252b5132 6932 else
df58fc94 6933 macro_build (NULL, "break", BRK_FMT, 7);
8fc2e39e 6934 break;
252b5132
RH
6935 }
6936 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6937 {
6938 if (strcmp (s2, "mflo") == 0)
67c0d1eb 6939 move_register (dreg, sreg);
252b5132 6940 else
c80c840e 6941 move_register (dreg, ZERO);
8fc2e39e 6942 break;
252b5132
RH
6943 }
6944 if (imm_expr.X_op == O_constant
6945 && imm_expr.X_add_number == -1
6946 && s[strlen (s) - 1] != 'u')
6947 {
6948 if (strcmp (s2, "mflo") == 0)
6949 {
67c0d1eb 6950 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
252b5132
RH
6951 }
6952 else
c80c840e 6953 move_register (dreg, ZERO);
8fc2e39e 6954 break;
252b5132
RH
6955 }
6956
8fc2e39e 6957 used_at = 1;
67c0d1eb
RS
6958 load_register (AT, &imm_expr, dbl);
6959 macro_build (NULL, s, "z,s,t", sreg, AT);
df58fc94 6960 macro_build (NULL, s2, MFHL_FMT, dreg);
252b5132
RH
6961 break;
6962
6963 case M_DIVU_3:
6964 s = "divu";
6965 s2 = "mflo";
6966 goto do_divu3;
6967 case M_REMU_3:
6968 s = "divu";
6969 s2 = "mfhi";
6970 goto do_divu3;
6971 case M_DDIVU_3:
6972 s = "ddivu";
6973 s2 = "mflo";
6974 goto do_divu3;
6975 case M_DREMU_3:
6976 s = "ddivu";
6977 s2 = "mfhi";
6978 do_divu3:
7d10b47d 6979 start_noreorder ();
252b5132
RH
6980 if (mips_trap)
6981 {
df58fc94 6982 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
67c0d1eb 6983 macro_build (NULL, s, "z,s,t", sreg, treg);
252b5132
RH
6984 /* We want to close the noreorder block as soon as possible, so
6985 that later insns are available for delay slot filling. */
7d10b47d 6986 end_noreorder ();
252b5132
RH
6987 }
6988 else
6989 {
df58fc94
RS
6990 if (mips_opts.micromips)
6991 micromips_label_expr (&label_expr);
6992 else
6993 label_expr.X_add_number = 8;
6994 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
67c0d1eb 6995 macro_build (NULL, s, "z,s,t", sreg, treg);
252b5132
RH
6996
6997 /* We want to close the noreorder block as soon as possible, so
6998 that later insns are available for delay slot filling. */
7d10b47d 6999 end_noreorder ();
df58fc94
RS
7000 macro_build (NULL, "break", BRK_FMT, 7);
7001 if (mips_opts.micromips)
7002 micromips_add_label ();
252b5132 7003 }
df58fc94 7004 macro_build (NULL, s2, MFHL_FMT, dreg);
8fc2e39e 7005 break;
252b5132 7006
1abe91b1
MR
7007 case M_DLCA_AB:
7008 dbl = 1;
7009 case M_LCA_AB:
7010 call = 1;
7011 goto do_la;
252b5132
RH
7012 case M_DLA_AB:
7013 dbl = 1;
7014 case M_LA_AB:
1abe91b1 7015 do_la:
252b5132
RH
7016 /* Load the address of a symbol into a register. If breg is not
7017 zero, we then add a base register to it. */
7018
3bec30a8
TS
7019 if (dbl && HAVE_32BIT_GPRS)
7020 as_warn (_("dla used to load 32-bit register"));
7021
90ecf173 7022 if (!dbl && HAVE_64BIT_OBJECTS)
3bec30a8
TS
7023 as_warn (_("la used to load 64-bit address"));
7024
0c11417f
MR
7025 if (offset_expr.X_op == O_constant
7026 && offset_expr.X_add_number >= -0x8000
7027 && offset_expr.X_add_number < 0x8000)
7028 {
aed1a261 7029 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
17a2f251 7030 "t,r,j", treg, sreg, BFD_RELOC_LO16);
8fc2e39e 7031 break;
0c11417f
MR
7032 }
7033
741fe287 7034 if (mips_opts.at && (treg == breg))
afdbd6d0
CD
7035 {
7036 tempreg = AT;
7037 used_at = 1;
7038 }
7039 else
7040 {
7041 tempreg = treg;
afdbd6d0
CD
7042 }
7043
252b5132
RH
7044 if (offset_expr.X_op != O_symbol
7045 && offset_expr.X_op != O_constant)
7046 {
f71d0d44 7047 as_bad (_("Expression too complex"));
252b5132
RH
7048 offset_expr.X_op = O_constant;
7049 }
7050
252b5132 7051 if (offset_expr.X_op == O_constant)
aed1a261 7052 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
252b5132
RH
7053 else if (mips_pic == NO_PIC)
7054 {
d6bc6245 7055 /* If this is a reference to a GP relative symbol, we want
cdf6fd85 7056 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
252b5132
RH
7057 Otherwise we want
7058 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7059 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7060 If we have a constant, we need two instructions anyhow,
d6bc6245 7061 so we may as well always use the latter form.
76b3015f 7062
6caf9ef4
TS
7063 With 64bit address space and a usable $at we want
7064 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7065 lui $at,<sym> (BFD_RELOC_HI16_S)
7066 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7067 daddiu $at,<sym> (BFD_RELOC_LO16)
7068 dsll32 $tempreg,0
7069 daddu $tempreg,$tempreg,$at
7070
7071 If $at is already in use, we use a path which is suboptimal
7072 on superscalar processors.
7073 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7074 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7075 dsll $tempreg,16
7076 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7077 dsll $tempreg,16
7078 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7079
7080 For GP relative symbols in 64bit address space we can use
7081 the same sequence as in 32bit address space. */
aed1a261 7082 if (HAVE_64BIT_SYMBOLS)
252b5132 7083 {
6caf9ef4
TS
7084 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7085 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7086 {
7087 relax_start (offset_expr.X_add_symbol);
7088 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7089 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7090 relax_switch ();
7091 }
d6bc6245 7092
741fe287 7093 if (used_at == 0 && mips_opts.at)
98d3f06f 7094 {
df58fc94 7095 macro_build (&offset_expr, "lui", LUI_FMT,
17a2f251 7096 tempreg, BFD_RELOC_MIPS_HIGHEST);
df58fc94 7097 macro_build (&offset_expr, "lui", LUI_FMT,
17a2f251 7098 AT, BFD_RELOC_HI16_S);
67c0d1eb 7099 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 7100 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
67c0d1eb 7101 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 7102 AT, AT, BFD_RELOC_LO16);
df58fc94 7103 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
67c0d1eb 7104 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
98d3f06f
KH
7105 used_at = 1;
7106 }
7107 else
7108 {
df58fc94 7109 macro_build (&offset_expr, "lui", LUI_FMT,
17a2f251 7110 tempreg, BFD_RELOC_MIPS_HIGHEST);
67c0d1eb 7111 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 7112 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
df58fc94 7113 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
67c0d1eb 7114 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 7115 tempreg, tempreg, BFD_RELOC_HI16_S);
df58fc94 7116 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
67c0d1eb 7117 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 7118 tempreg, tempreg, BFD_RELOC_LO16);
98d3f06f 7119 }
6caf9ef4
TS
7120
7121 if (mips_relax.sequence)
7122 relax_end ();
98d3f06f
KH
7123 }
7124 else
7125 {
7126 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 7127 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
98d3f06f 7128 {
4d7206a2 7129 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
7130 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7131 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
4d7206a2 7132 relax_switch ();
98d3f06f 7133 }
6943caf0 7134 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
f71d0d44 7135 as_bad (_("Offset too large"));
67c0d1eb
RS
7136 macro_build_lui (&offset_expr, tempreg);
7137 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7138 tempreg, tempreg, BFD_RELOC_LO16);
4d7206a2
RS
7139 if (mips_relax.sequence)
7140 relax_end ();
98d3f06f 7141 }
252b5132 7142 }
0a44bf69 7143 else if (!mips_big_got && !HAVE_NEWABI)
252b5132 7144 {
9117d219
NC
7145 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7146
252b5132
RH
7147 /* If this is a reference to an external symbol, and there
7148 is no constant, we want
7149 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1abe91b1 7150 or for lca or if tempreg is PIC_CALL_REG
9117d219 7151 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
252b5132
RH
7152 For a local symbol, we want
7153 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7154 nop
7155 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7156
7157 If we have a small constant, and this is a reference to
7158 an external symbol, we want
7159 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7160 nop
7161 addiu $tempreg,$tempreg,<constant>
7162 For a local symbol, we want the same instruction
7163 sequence, but we output a BFD_RELOC_LO16 reloc on the
7164 addiu instruction.
7165
7166 If we have a large constant, and this is a reference to
7167 an external symbol, we want
7168 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7169 lui $at,<hiconstant>
7170 addiu $at,$at,<loconstant>
7171 addu $tempreg,$tempreg,$at
7172 For a local symbol, we want the same instruction
7173 sequence, but we output a BFD_RELOC_LO16 reloc on the
ed6fb7bd 7174 addiu instruction.
ed6fb7bd
SC
7175 */
7176
4d7206a2 7177 if (offset_expr.X_add_number == 0)
252b5132 7178 {
0a44bf69
RS
7179 if (mips_pic == SVR4_PIC
7180 && breg == 0
7181 && (call || tempreg == PIC_CALL_REG))
4d7206a2
RS
7182 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
7183
7184 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
7185 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7186 lw_reloc_type, mips_gp_register);
4d7206a2 7187 if (breg != 0)
252b5132
RH
7188 {
7189 /* We're going to put in an addu instruction using
7190 tempreg, so we may as well insert the nop right
7191 now. */
269137b2 7192 load_delay_nop ();
252b5132 7193 }
4d7206a2 7194 relax_switch ();
67c0d1eb
RS
7195 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7196 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 7197 load_delay_nop ();
67c0d1eb
RS
7198 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7199 tempreg, tempreg, BFD_RELOC_LO16);
4d7206a2 7200 relax_end ();
252b5132
RH
7201 /* FIXME: If breg == 0, and the next instruction uses
7202 $tempreg, then if this variant case is used an extra
7203 nop will be generated. */
7204 }
4d7206a2
RS
7205 else if (offset_expr.X_add_number >= -0x8000
7206 && offset_expr.X_add_number < 0x8000)
252b5132 7207 {
67c0d1eb 7208 load_got_offset (tempreg, &offset_expr);
269137b2 7209 load_delay_nop ();
67c0d1eb 7210 add_got_offset (tempreg, &offset_expr);
252b5132
RH
7211 }
7212 else
7213 {
4d7206a2
RS
7214 expr1.X_add_number = offset_expr.X_add_number;
7215 offset_expr.X_add_number =
7216 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
67c0d1eb 7217 load_got_offset (tempreg, &offset_expr);
f6a22291 7218 offset_expr.X_add_number = expr1.X_add_number;
252b5132
RH
7219 /* If we are going to add in a base register, and the
7220 target register and the base register are the same,
7221 then we are using AT as a temporary register. Since
7222 we want to load the constant into AT, we add our
7223 current AT (from the global offset table) and the
7224 register into the register now, and pretend we were
7225 not using a base register. */
67c0d1eb 7226 if (breg == treg)
252b5132 7227 {
269137b2 7228 load_delay_nop ();
67c0d1eb 7229 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 7230 treg, AT, breg);
252b5132
RH
7231 breg = 0;
7232 tempreg = treg;
252b5132 7233 }
f6a22291 7234 add_got_offset_hilo (tempreg, &offset_expr, AT);
252b5132
RH
7235 used_at = 1;
7236 }
7237 }
0a44bf69 7238 else if (!mips_big_got && HAVE_NEWABI)
f5040a92 7239 {
67c0d1eb 7240 int add_breg_early = 0;
f5040a92
AO
7241
7242 /* If this is a reference to an external, and there is no
7243 constant, or local symbol (*), with or without a
7244 constant, we want
7245 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
1abe91b1 7246 or for lca or if tempreg is PIC_CALL_REG
f5040a92
AO
7247 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7248
7249 If we have a small constant, and this is a reference to
7250 an external symbol, we want
7251 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7252 addiu $tempreg,$tempreg,<constant>
7253
7254 If we have a large constant, and this is a reference to
7255 an external symbol, we want
7256 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7257 lui $at,<hiconstant>
7258 addiu $at,$at,<loconstant>
7259 addu $tempreg,$tempreg,$at
7260
7261 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7262 local symbols, even though it introduces an additional
7263 instruction. */
7264
f5040a92
AO
7265 if (offset_expr.X_add_number)
7266 {
4d7206a2 7267 expr1.X_add_number = offset_expr.X_add_number;
f5040a92
AO
7268 offset_expr.X_add_number = 0;
7269
4d7206a2 7270 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
7271 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7272 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
f5040a92
AO
7273
7274 if (expr1.X_add_number >= -0x8000
7275 && expr1.X_add_number < 0x8000)
7276 {
67c0d1eb
RS
7277 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7278 tempreg, tempreg, BFD_RELOC_LO16);
f5040a92 7279 }
ecd13cd3 7280 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
f5040a92 7281 {
f5040a92
AO
7282 /* If we are going to add in a base register, and the
7283 target register and the base register are the same,
7284 then we are using AT as a temporary register. Since
7285 we want to load the constant into AT, we add our
7286 current AT (from the global offset table) and the
7287 register into the register now, and pretend we were
7288 not using a base register. */
7289 if (breg != treg)
7290 dreg = tempreg;
7291 else
7292 {
9c2799c2 7293 gas_assert (tempreg == AT);
67c0d1eb
RS
7294 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7295 treg, AT, breg);
f5040a92 7296 dreg = treg;
67c0d1eb 7297 add_breg_early = 1;
f5040a92
AO
7298 }
7299
f6a22291 7300 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
67c0d1eb 7301 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 7302 dreg, dreg, AT);
f5040a92 7303
f5040a92
AO
7304 used_at = 1;
7305 }
7306 else
7307 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7308
4d7206a2 7309 relax_switch ();
f5040a92
AO
7310 offset_expr.X_add_number = expr1.X_add_number;
7311
67c0d1eb
RS
7312 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7313 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7314 if (add_breg_early)
f5040a92 7315 {
67c0d1eb 7316 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
f899b4b8 7317 treg, tempreg, breg);
f5040a92
AO
7318 breg = 0;
7319 tempreg = treg;
7320 }
4d7206a2 7321 relax_end ();
f5040a92 7322 }
4d7206a2 7323 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
f5040a92 7324 {
4d7206a2 7325 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
7326 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7327 BFD_RELOC_MIPS_CALL16, mips_gp_register);
4d7206a2 7328 relax_switch ();
67c0d1eb
RS
7329 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7330 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4d7206a2 7331 relax_end ();
f5040a92 7332 }
4d7206a2 7333 else
f5040a92 7334 {
67c0d1eb
RS
7335 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7336 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
f5040a92
AO
7337 }
7338 }
0a44bf69 7339 else if (mips_big_got && !HAVE_NEWABI)
252b5132 7340 {
67c0d1eb 7341 int gpdelay;
9117d219
NC
7342 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7343 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
ed6fb7bd 7344 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
252b5132
RH
7345
7346 /* This is the large GOT case. If this is a reference to an
7347 external symbol, and there is no constant, we want
7348 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7349 addu $tempreg,$tempreg,$gp
7350 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
1abe91b1 7351 or for lca or if tempreg is PIC_CALL_REG
9117d219
NC
7352 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7353 addu $tempreg,$tempreg,$gp
7354 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
252b5132
RH
7355 For a local symbol, we want
7356 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7357 nop
7358 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7359
7360 If we have a small constant, and this is a reference to
7361 an external symbol, we want
7362 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7363 addu $tempreg,$tempreg,$gp
7364 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7365 nop
7366 addiu $tempreg,$tempreg,<constant>
7367 For a local symbol, we want
7368 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7369 nop
7370 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7371
7372 If we have a large constant, and this is a reference to
7373 an external symbol, we want
7374 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7375 addu $tempreg,$tempreg,$gp
7376 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7377 lui $at,<hiconstant>
7378 addiu $at,$at,<loconstant>
7379 addu $tempreg,$tempreg,$at
7380 For a local symbol, we want
7381 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7382 lui $at,<hiconstant>
7383 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7384 addu $tempreg,$tempreg,$at
f5040a92 7385 */
438c16b8 7386
252b5132
RH
7387 expr1.X_add_number = offset_expr.X_add_number;
7388 offset_expr.X_add_number = 0;
4d7206a2 7389 relax_start (offset_expr.X_add_symbol);
67c0d1eb 7390 gpdelay = reg_needs_delay (mips_gp_register);
1abe91b1
MR
7391 if (expr1.X_add_number == 0 && breg == 0
7392 && (call || tempreg == PIC_CALL_REG))
9117d219
NC
7393 {
7394 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7395 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7396 }
df58fc94 7397 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
67c0d1eb 7398 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 7399 tempreg, tempreg, mips_gp_register);
67c0d1eb 7400 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
17a2f251 7401 tempreg, lw_reloc_type, tempreg);
252b5132
RH
7402 if (expr1.X_add_number == 0)
7403 {
67c0d1eb 7404 if (breg != 0)
252b5132
RH
7405 {
7406 /* We're going to put in an addu instruction using
7407 tempreg, so we may as well insert the nop right
7408 now. */
269137b2 7409 load_delay_nop ();
252b5132 7410 }
252b5132
RH
7411 }
7412 else if (expr1.X_add_number >= -0x8000
7413 && expr1.X_add_number < 0x8000)
7414 {
269137b2 7415 load_delay_nop ();
67c0d1eb 7416 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 7417 tempreg, tempreg, BFD_RELOC_LO16);
252b5132
RH
7418 }
7419 else
7420 {
252b5132
RH
7421 /* If we are going to add in a base register, and the
7422 target register and the base register are the same,
7423 then we are using AT as a temporary register. Since
7424 we want to load the constant into AT, we add our
7425 current AT (from the global offset table) and the
7426 register into the register now, and pretend we were
7427 not using a base register. */
7428 if (breg != treg)
67c0d1eb 7429 dreg = tempreg;
252b5132
RH
7430 else
7431 {
9c2799c2 7432 gas_assert (tempreg == AT);
269137b2 7433 load_delay_nop ();
67c0d1eb 7434 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 7435 treg, AT, breg);
252b5132 7436 dreg = treg;
252b5132
RH
7437 }
7438
f6a22291 7439 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
67c0d1eb 7440 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
252b5132 7441
252b5132
RH
7442 used_at = 1;
7443 }
4d7206a2
RS
7444 offset_expr.X_add_number =
7445 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
7446 relax_switch ();
252b5132 7447
67c0d1eb 7448 if (gpdelay)
252b5132
RH
7449 {
7450 /* This is needed because this instruction uses $gp, but
f5040a92 7451 the first instruction on the main stream does not. */
67c0d1eb 7452 macro_build (NULL, "nop", "");
252b5132 7453 }
ed6fb7bd 7454
67c0d1eb
RS
7455 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7456 local_reloc_type, mips_gp_register);
f5040a92 7457 if (expr1.X_add_number >= -0x8000
252b5132
RH
7458 && expr1.X_add_number < 0x8000)
7459 {
269137b2 7460 load_delay_nop ();
67c0d1eb
RS
7461 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7462 tempreg, tempreg, BFD_RELOC_LO16);
252b5132 7463 /* FIXME: If add_number is 0, and there was no base
f5040a92
AO
7464 register, the external symbol case ended with a load,
7465 so if the symbol turns out to not be external, and
7466 the next instruction uses tempreg, an unnecessary nop
7467 will be inserted. */
252b5132
RH
7468 }
7469 else
7470 {
7471 if (breg == treg)
7472 {
7473 /* We must add in the base register now, as in the
f5040a92 7474 external symbol case. */
9c2799c2 7475 gas_assert (tempreg == AT);
269137b2 7476 load_delay_nop ();
67c0d1eb 7477 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 7478 treg, AT, breg);
252b5132
RH
7479 tempreg = treg;
7480 /* We set breg to 0 because we have arranged to add
f5040a92 7481 it in in both cases. */
252b5132
RH
7482 breg = 0;
7483 }
7484
67c0d1eb
RS
7485 macro_build_lui (&expr1, AT);
7486 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 7487 AT, AT, BFD_RELOC_LO16);
67c0d1eb 7488 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 7489 tempreg, tempreg, AT);
8fc2e39e 7490 used_at = 1;
252b5132 7491 }
4d7206a2 7492 relax_end ();
252b5132 7493 }
0a44bf69 7494 else if (mips_big_got && HAVE_NEWABI)
f5040a92 7495 {
f5040a92
AO
7496 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7497 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
67c0d1eb 7498 int add_breg_early = 0;
f5040a92
AO
7499
7500 /* This is the large GOT case. If this is a reference to an
7501 external symbol, and there is no constant, we want
7502 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7503 add $tempreg,$tempreg,$gp
7504 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
1abe91b1 7505 or for lca or if tempreg is PIC_CALL_REG
f5040a92
AO
7506 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7507 add $tempreg,$tempreg,$gp
7508 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7509
7510 If we have a small constant, and this is a reference to
7511 an external symbol, we want
7512 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7513 add $tempreg,$tempreg,$gp
7514 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7515 addi $tempreg,$tempreg,<constant>
7516
7517 If we have a large constant, and this is a reference to
7518 an external symbol, we want
7519 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7520 addu $tempreg,$tempreg,$gp
7521 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7522 lui $at,<hiconstant>
7523 addi $at,$at,<loconstant>
7524 add $tempreg,$tempreg,$at
7525
7526 If we have NewABI, and we know it's a local symbol, we want
7527 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7528 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7529 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7530
4d7206a2 7531 relax_start (offset_expr.X_add_symbol);
f5040a92 7532
4d7206a2 7533 expr1.X_add_number = offset_expr.X_add_number;
f5040a92
AO
7534 offset_expr.X_add_number = 0;
7535
1abe91b1
MR
7536 if (expr1.X_add_number == 0 && breg == 0
7537 && (call || tempreg == PIC_CALL_REG))
f5040a92
AO
7538 {
7539 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7540 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7541 }
df58fc94 7542 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
67c0d1eb 7543 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 7544 tempreg, tempreg, mips_gp_register);
67c0d1eb
RS
7545 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7546 tempreg, lw_reloc_type, tempreg);
f5040a92
AO
7547
7548 if (expr1.X_add_number == 0)
4d7206a2 7549 ;
f5040a92
AO
7550 else if (expr1.X_add_number >= -0x8000
7551 && expr1.X_add_number < 0x8000)
7552 {
67c0d1eb 7553 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 7554 tempreg, tempreg, BFD_RELOC_LO16);
f5040a92 7555 }
ecd13cd3 7556 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
f5040a92 7557 {
f5040a92
AO
7558 /* If we are going to add in a base register, and the
7559 target register and the base register are the same,
7560 then we are using AT as a temporary register. Since
7561 we want to load the constant into AT, we add our
7562 current AT (from the global offset table) and the
7563 register into the register now, and pretend we were
7564 not using a base register. */
7565 if (breg != treg)
7566 dreg = tempreg;
7567 else
7568 {
9c2799c2 7569 gas_assert (tempreg == AT);
67c0d1eb 7570 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 7571 treg, AT, breg);
f5040a92 7572 dreg = treg;
67c0d1eb 7573 add_breg_early = 1;
f5040a92
AO
7574 }
7575
f6a22291 7576 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
67c0d1eb 7577 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
f5040a92 7578
f5040a92
AO
7579 used_at = 1;
7580 }
7581 else
7582 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7583
4d7206a2 7584 relax_switch ();
f5040a92 7585 offset_expr.X_add_number = expr1.X_add_number;
67c0d1eb
RS
7586 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7587 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7588 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7589 tempreg, BFD_RELOC_MIPS_GOT_OFST);
7590 if (add_breg_early)
f5040a92 7591 {
67c0d1eb 7592 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 7593 treg, tempreg, breg);
f5040a92
AO
7594 breg = 0;
7595 tempreg = treg;
7596 }
4d7206a2 7597 relax_end ();
f5040a92 7598 }
252b5132
RH
7599 else
7600 abort ();
7601
7602 if (breg != 0)
aed1a261 7603 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
252b5132
RH
7604 break;
7605
52b6b6b9 7606 case M_MSGSND:
df58fc94 7607 gas_assert (!mips_opts.micromips);
52b6b6b9
JM
7608 {
7609 unsigned long temp = (treg << 16) | (0x01);
7610 macro_build (NULL, "c2", "C", temp);
7611 }
c7af4273 7612 break;
52b6b6b9
JM
7613
7614 case M_MSGLD:
df58fc94 7615 gas_assert (!mips_opts.micromips);
52b6b6b9
JM
7616 {
7617 unsigned long temp = (0x02);
7618 macro_build (NULL, "c2", "C", temp);
7619 }
c7af4273 7620 break;
52b6b6b9
JM
7621
7622 case M_MSGLD_T:
df58fc94 7623 gas_assert (!mips_opts.micromips);
52b6b6b9
JM
7624 {
7625 unsigned long temp = (treg << 16) | (0x02);
7626 macro_build (NULL, "c2", "C", temp);
7627 }
c7af4273 7628 break;
52b6b6b9
JM
7629
7630 case M_MSGWAIT:
df58fc94 7631 gas_assert (!mips_opts.micromips);
52b6b6b9 7632 macro_build (NULL, "c2", "C", 3);
c7af4273 7633 break;
52b6b6b9
JM
7634
7635 case M_MSGWAIT_T:
df58fc94 7636 gas_assert (!mips_opts.micromips);
52b6b6b9
JM
7637 {
7638 unsigned long temp = (treg << 16) | 0x03;
7639 macro_build (NULL, "c2", "C", temp);
7640 }
c7af4273 7641 break;
52b6b6b9 7642
252b5132
RH
7643 case M_J_A:
7644 /* The j instruction may not be used in PIC code, since it
7645 requires an absolute address. We convert it to a b
7646 instruction. */
7647 if (mips_pic == NO_PIC)
67c0d1eb 7648 macro_build (&offset_expr, "j", "a");
252b5132 7649 else
67c0d1eb 7650 macro_build (&offset_expr, "b", "p");
8fc2e39e 7651 break;
252b5132
RH
7652
7653 /* The jal instructions must be handled as macros because when
7654 generating PIC code they expand to multi-instruction
7655 sequences. Normally they are simple instructions. */
df58fc94
RS
7656 case M_JALS_1:
7657 dreg = RA;
7658 /* Fall through. */
7659 case M_JALS_2:
7660 gas_assert (mips_opts.micromips);
7661 jals = 1;
7662 goto jal;
252b5132
RH
7663 case M_JAL_1:
7664 dreg = RA;
7665 /* Fall through. */
7666 case M_JAL_2:
df58fc94 7667 jal:
3e722fb5 7668 if (mips_pic == NO_PIC)
df58fc94
RS
7669 {
7670 s = jals ? "jalrs" : "jalr";
7671 if (mips_opts.micromips && dreg == RA)
7672 macro_build (NULL, s, "mj", sreg);
7673 else
7674 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7675 }
0a44bf69 7676 else
252b5132 7677 {
df58fc94
RS
7678 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
7679 && mips_cprestore_offset >= 0);
7680
252b5132
RH
7681 if (sreg != PIC_CALL_REG)
7682 as_warn (_("MIPS PIC call to register other than $25"));
bdaaa2e1 7683
df58fc94
RS
7684 s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore)
7685 ? "jalrs" : "jalr");
7686 if (mips_opts.micromips && dreg == RA)
7687 macro_build (NULL, s, "mj", sreg);
7688 else
7689 macro_build (NULL, s, JALR_FMT, dreg, sreg);
0a44bf69 7690 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
252b5132 7691 {
6478892d
TS
7692 if (mips_cprestore_offset < 0)
7693 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7694 else
7695 {
90ecf173 7696 if (!mips_frame_reg_valid)
7a621144
DJ
7697 {
7698 as_warn (_("No .frame pseudo-op used in PIC code"));
7699 /* Quiet this warning. */
7700 mips_frame_reg_valid = 1;
7701 }
90ecf173 7702 if (!mips_cprestore_valid)
7a621144
DJ
7703 {
7704 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7705 /* Quiet this warning. */
7706 mips_cprestore_valid = 1;
7707 }
d3fca0b5
MR
7708 if (mips_opts.noreorder)
7709 macro_build (NULL, "nop", "");
6478892d 7710 expr1.X_add_number = mips_cprestore_offset;
67c0d1eb 7711 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
f899b4b8 7712 mips_gp_register,
256ab948
TS
7713 mips_frame_reg,
7714 HAVE_64BIT_ADDRESSES);
6478892d 7715 }
252b5132
RH
7716 }
7717 }
252b5132 7718
8fc2e39e 7719 break;
252b5132 7720
df58fc94
RS
7721 case M_JALS_A:
7722 gas_assert (mips_opts.micromips);
7723 jals = 1;
7724 /* Fall through. */
252b5132
RH
7725 case M_JAL_A:
7726 if (mips_pic == NO_PIC)
df58fc94 7727 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
252b5132
RH
7728 else if (mips_pic == SVR4_PIC)
7729 {
7730 /* If this is a reference to an external symbol, and we are
7731 using a small GOT, we want
7732 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7733 nop
f9419b05 7734 jalr $ra,$25
252b5132
RH
7735 nop
7736 lw $gp,cprestore($sp)
7737 The cprestore value is set using the .cprestore
7738 pseudo-op. If we are using a big GOT, we want
7739 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7740 addu $25,$25,$gp
7741 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7742 nop
f9419b05 7743 jalr $ra,$25
252b5132
RH
7744 nop
7745 lw $gp,cprestore($sp)
7746 If the symbol is not external, we want
7747 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7748 nop
7749 addiu $25,$25,<sym> (BFD_RELOC_LO16)
f9419b05 7750 jalr $ra,$25
252b5132 7751 nop
438c16b8 7752 lw $gp,cprestore($sp)
f5040a92
AO
7753
7754 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7755 sequences above, minus nops, unless the symbol is local,
7756 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7757 GOT_DISP. */
438c16b8 7758 if (HAVE_NEWABI)
252b5132 7759 {
90ecf173 7760 if (!mips_big_got)
f5040a92 7761 {
4d7206a2 7762 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
7763 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7764 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
f5040a92 7765 mips_gp_register);
4d7206a2 7766 relax_switch ();
67c0d1eb
RS
7767 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7768 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
4d7206a2
RS
7769 mips_gp_register);
7770 relax_end ();
f5040a92
AO
7771 }
7772 else
7773 {
4d7206a2 7774 relax_start (offset_expr.X_add_symbol);
df58fc94 7775 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
67c0d1eb
RS
7776 BFD_RELOC_MIPS_CALL_HI16);
7777 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7778 PIC_CALL_REG, mips_gp_register);
7779 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7780 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7781 PIC_CALL_REG);
4d7206a2 7782 relax_switch ();
67c0d1eb
RS
7783 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7784 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
7785 mips_gp_register);
7786 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7787 PIC_CALL_REG, PIC_CALL_REG,
17a2f251 7788 BFD_RELOC_MIPS_GOT_OFST);
4d7206a2 7789 relax_end ();
f5040a92 7790 }
684022ea 7791
df58fc94 7792 macro_build_jalr (&offset_expr, 0);
252b5132
RH
7793 }
7794 else
7795 {
4d7206a2 7796 relax_start (offset_expr.X_add_symbol);
90ecf173 7797 if (!mips_big_got)
438c16b8 7798 {
67c0d1eb
RS
7799 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7800 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
17a2f251 7801 mips_gp_register);
269137b2 7802 load_delay_nop ();
4d7206a2 7803 relax_switch ();
438c16b8 7804 }
252b5132 7805 else
252b5132 7806 {
67c0d1eb
RS
7807 int gpdelay;
7808
7809 gpdelay = reg_needs_delay (mips_gp_register);
df58fc94 7810 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
67c0d1eb
RS
7811 BFD_RELOC_MIPS_CALL_HI16);
7812 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7813 PIC_CALL_REG, mips_gp_register);
7814 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7815 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7816 PIC_CALL_REG);
269137b2 7817 load_delay_nop ();
4d7206a2 7818 relax_switch ();
67c0d1eb
RS
7819 if (gpdelay)
7820 macro_build (NULL, "nop", "");
252b5132 7821 }
67c0d1eb
RS
7822 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7823 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
4d7206a2 7824 mips_gp_register);
269137b2 7825 load_delay_nop ();
67c0d1eb
RS
7826 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7827 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
4d7206a2 7828 relax_end ();
df58fc94 7829 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
438c16b8 7830
6478892d
TS
7831 if (mips_cprestore_offset < 0)
7832 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7833 else
7834 {
90ecf173 7835 if (!mips_frame_reg_valid)
7a621144
DJ
7836 {
7837 as_warn (_("No .frame pseudo-op used in PIC code"));
7838 /* Quiet this warning. */
7839 mips_frame_reg_valid = 1;
7840 }
90ecf173 7841 if (!mips_cprestore_valid)
7a621144
DJ
7842 {
7843 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7844 /* Quiet this warning. */
7845 mips_cprestore_valid = 1;
7846 }
6478892d 7847 if (mips_opts.noreorder)
67c0d1eb 7848 macro_build (NULL, "nop", "");
6478892d 7849 expr1.X_add_number = mips_cprestore_offset;
67c0d1eb 7850 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
f899b4b8 7851 mips_gp_register,
256ab948
TS
7852 mips_frame_reg,
7853 HAVE_64BIT_ADDRESSES);
6478892d 7854 }
252b5132
RH
7855 }
7856 }
0a44bf69
RS
7857 else if (mips_pic == VXWORKS_PIC)
7858 as_bad (_("Non-PIC jump used in PIC library"));
252b5132
RH
7859 else
7860 abort ();
7861
8fc2e39e 7862 break;
252b5132
RH
7863
7864 case M_LB_AB:
df58fc94 7865 ab = 1;
252b5132 7866 s = "lb";
df58fc94 7867 fmt = "t,o(b)";
252b5132
RH
7868 goto ld;
7869 case M_LBU_AB:
df58fc94 7870 ab = 1;
252b5132 7871 s = "lbu";
df58fc94 7872 fmt = "t,o(b)";
252b5132
RH
7873 goto ld;
7874 case M_LH_AB:
df58fc94 7875 ab = 1;
252b5132 7876 s = "lh";
df58fc94 7877 fmt = "t,o(b)";
252b5132
RH
7878 goto ld;
7879 case M_LHU_AB:
df58fc94 7880 ab = 1;
252b5132 7881 s = "lhu";
df58fc94 7882 fmt = "t,o(b)";
252b5132
RH
7883 goto ld;
7884 case M_LW_AB:
df58fc94 7885 ab = 1;
252b5132 7886 s = "lw";
df58fc94 7887 fmt = "t,o(b)";
252b5132
RH
7888 goto ld;
7889 case M_LWC0_AB:
df58fc94
RS
7890 ab = 1;
7891 gas_assert (!mips_opts.micromips);
252b5132 7892 s = "lwc0";
df58fc94 7893 fmt = "E,o(b)";
bdaaa2e1 7894 /* Itbl support may require additional care here. */
252b5132 7895 coproc = 1;
df58fc94 7896 goto ld_st;
252b5132 7897 case M_LWC1_AB:
df58fc94 7898 ab = 1;
252b5132 7899 s = "lwc1";
df58fc94 7900 fmt = "T,o(b)";
bdaaa2e1 7901 /* Itbl support may require additional care here. */
252b5132 7902 coproc = 1;
df58fc94 7903 goto ld_st;
252b5132 7904 case M_LWC2_AB:
df58fc94
RS
7905 ab = 1;
7906 case M_LWC2_OB:
252b5132 7907 s = "lwc2";
df58fc94
RS
7908 fmt = COP12_FMT;
7909 off12 = mips_opts.micromips;
bdaaa2e1 7910 /* Itbl support may require additional care here. */
252b5132 7911 coproc = 1;
df58fc94 7912 goto ld_st;
252b5132 7913 case M_LWC3_AB:
df58fc94
RS
7914 ab = 1;
7915 gas_assert (!mips_opts.micromips);
252b5132 7916 s = "lwc3";
df58fc94 7917 fmt = "E,o(b)";
bdaaa2e1 7918 /* Itbl support may require additional care here. */
252b5132 7919 coproc = 1;
df58fc94 7920 goto ld_st;
252b5132 7921 case M_LWL_AB:
df58fc94
RS
7922 ab = 1;
7923 case M_LWL_OB:
252b5132 7924 s = "lwl";
df58fc94
RS
7925 fmt = MEM12_FMT;
7926 off12 = mips_opts.micromips;
7927 goto ld_st;
252b5132 7928 case M_LWR_AB:
df58fc94
RS
7929 ab = 1;
7930 case M_LWR_OB:
252b5132 7931 s = "lwr";
df58fc94
RS
7932 fmt = MEM12_FMT;
7933 off12 = mips_opts.micromips;
7934 goto ld_st;
252b5132 7935 case M_LDC1_AB:
df58fc94 7936 ab = 1;
252b5132 7937 s = "ldc1";
df58fc94 7938 fmt = "T,o(b)";
bdaaa2e1 7939 /* Itbl support may require additional care here. */
252b5132 7940 coproc = 1;
df58fc94 7941 goto ld_st;
252b5132 7942 case M_LDC2_AB:
df58fc94
RS
7943 ab = 1;
7944 case M_LDC2_OB:
252b5132 7945 s = "ldc2";
df58fc94
RS
7946 fmt = COP12_FMT;
7947 off12 = mips_opts.micromips;
bdaaa2e1 7948 /* Itbl support may require additional care here. */
252b5132 7949 coproc = 1;
df58fc94 7950 goto ld_st;
252b5132 7951 case M_LDC3_AB:
df58fc94 7952 ab = 1;
252b5132 7953 s = "ldc3";
df58fc94 7954 fmt = "E,o(b)";
bdaaa2e1 7955 /* Itbl support may require additional care here. */
252b5132 7956 coproc = 1;
df58fc94 7957 goto ld_st;
252b5132 7958 case M_LDL_AB:
df58fc94
RS
7959 ab = 1;
7960 case M_LDL_OB:
252b5132 7961 s = "ldl";
df58fc94
RS
7962 fmt = MEM12_FMT;
7963 off12 = mips_opts.micromips;
7964 goto ld_st;
252b5132 7965 case M_LDR_AB:
df58fc94
RS
7966 ab = 1;
7967 case M_LDR_OB:
252b5132 7968 s = "ldr";
df58fc94
RS
7969 fmt = MEM12_FMT;
7970 off12 = mips_opts.micromips;
7971 goto ld_st;
252b5132 7972 case M_LL_AB:
df58fc94
RS
7973 ab = 1;
7974 case M_LL_OB:
252b5132 7975 s = "ll";
df58fc94
RS
7976 fmt = MEM12_FMT;
7977 off12 = mips_opts.micromips;
252b5132
RH
7978 goto ld;
7979 case M_LLD_AB:
df58fc94
RS
7980 ab = 1;
7981 case M_LLD_OB:
252b5132 7982 s = "lld";
df58fc94
RS
7983 fmt = MEM12_FMT;
7984 off12 = mips_opts.micromips;
252b5132
RH
7985 goto ld;
7986 case M_LWU_AB:
df58fc94
RS
7987 ab = 1;
7988 case M_LWU_OB:
252b5132 7989 s = "lwu";
df58fc94
RS
7990 fmt = MEM12_FMT;
7991 off12 = mips_opts.micromips;
7992 goto ld;
7993 case M_LWP_AB:
7994 ab = 1;
7995 case M_LWP_OB:
7996 gas_assert (mips_opts.micromips);
7997 s = "lwp";
7998 fmt = "t,~(b)";
7999 off12 = 1;
8000 lp = 1;
8001 goto ld;
8002 case M_LDP_AB:
8003 ab = 1;
8004 case M_LDP_OB:
8005 gas_assert (mips_opts.micromips);
8006 s = "ldp";
8007 fmt = "t,~(b)";
8008 off12 = 1;
8009 lp = 1;
8010 goto ld;
8011 case M_LWM_AB:
8012 ab = 1;
8013 case M_LWM_OB:
8014 gas_assert (mips_opts.micromips);
8015 s = "lwm";
8016 fmt = "n,~(b)";
8017 off12 = 1;
8018 goto ld_st;
8019 case M_LDM_AB:
8020 ab = 1;
8021 case M_LDM_OB:
8022 gas_assert (mips_opts.micromips);
8023 s = "ldm";
8024 fmt = "n,~(b)";
8025 off12 = 1;
8026 goto ld_st;
8027
252b5132 8028 ld:
df58fc94
RS
8029 if (breg == treg + lp)
8030 goto ld_st;
252b5132 8031 else
df58fc94
RS
8032 tempreg = treg + lp;
8033 goto ld_noat;
8034
252b5132 8035 case M_SB_AB:
df58fc94 8036 ab = 1;
252b5132 8037 s = "sb";
df58fc94
RS
8038 fmt = "t,o(b)";
8039 goto ld_st;
252b5132 8040 case M_SH_AB:
df58fc94 8041 ab = 1;
252b5132 8042 s = "sh";
df58fc94
RS
8043 fmt = "t,o(b)";
8044 goto ld_st;
252b5132 8045 case M_SW_AB:
df58fc94 8046 ab = 1;
252b5132 8047 s = "sw";
df58fc94
RS
8048 fmt = "t,o(b)";
8049 goto ld_st;
252b5132 8050 case M_SWC0_AB:
df58fc94
RS
8051 ab = 1;
8052 gas_assert (!mips_opts.micromips);
252b5132 8053 s = "swc0";
df58fc94 8054 fmt = "E,o(b)";
bdaaa2e1 8055 /* Itbl support may require additional care here. */
252b5132 8056 coproc = 1;
df58fc94 8057 goto ld_st;
252b5132 8058 case M_SWC1_AB:
df58fc94 8059 ab = 1;
252b5132 8060 s = "swc1";
df58fc94 8061 fmt = "T,o(b)";
bdaaa2e1 8062 /* Itbl support may require additional care here. */
252b5132 8063 coproc = 1;
df58fc94 8064 goto ld_st;
252b5132 8065 case M_SWC2_AB:
df58fc94
RS
8066 ab = 1;
8067 case M_SWC2_OB:
252b5132 8068 s = "swc2";
df58fc94
RS
8069 fmt = COP12_FMT;
8070 off12 = mips_opts.micromips;
bdaaa2e1 8071 /* Itbl support may require additional care here. */
252b5132 8072 coproc = 1;
df58fc94 8073 goto ld_st;
252b5132 8074 case M_SWC3_AB:
df58fc94
RS
8075 ab = 1;
8076 gas_assert (!mips_opts.micromips);
252b5132 8077 s = "swc3";
df58fc94 8078 fmt = "E,o(b)";
bdaaa2e1 8079 /* Itbl support may require additional care here. */
252b5132 8080 coproc = 1;
df58fc94 8081 goto ld_st;
252b5132 8082 case M_SWL_AB:
df58fc94
RS
8083 ab = 1;
8084 case M_SWL_OB:
252b5132 8085 s = "swl";
df58fc94
RS
8086 fmt = MEM12_FMT;
8087 off12 = mips_opts.micromips;
8088 goto ld_st;
252b5132 8089 case M_SWR_AB:
df58fc94
RS
8090 ab = 1;
8091 case M_SWR_OB:
252b5132 8092 s = "swr";
df58fc94
RS
8093 fmt = MEM12_FMT;
8094 off12 = mips_opts.micromips;
8095 goto ld_st;
252b5132 8096 case M_SC_AB:
df58fc94
RS
8097 ab = 1;
8098 case M_SC_OB:
252b5132 8099 s = "sc";
df58fc94
RS
8100 fmt = MEM12_FMT;
8101 off12 = mips_opts.micromips;
8102 goto ld_st;
252b5132 8103 case M_SCD_AB:
df58fc94
RS
8104 ab = 1;
8105 case M_SCD_OB:
252b5132 8106 s = "scd";
df58fc94
RS
8107 fmt = MEM12_FMT;
8108 off12 = mips_opts.micromips;
8109 goto ld_st;
d43b4baf 8110 case M_CACHE_AB:
df58fc94
RS
8111 ab = 1;
8112 case M_CACHE_OB:
d43b4baf 8113 s = "cache";
df58fc94
RS
8114 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
8115 off12 = mips_opts.micromips;
8116 goto ld_st;
3eebd5eb 8117 case M_PREF_AB:
df58fc94
RS
8118 ab = 1;
8119 case M_PREF_OB:
3eebd5eb 8120 s = "pref";
df58fc94
RS
8121 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
8122 off12 = mips_opts.micromips;
8123 goto ld_st;
252b5132 8124 case M_SDC1_AB:
df58fc94 8125 ab = 1;
252b5132 8126 s = "sdc1";
df58fc94 8127 fmt = "T,o(b)";
252b5132 8128 coproc = 1;
bdaaa2e1 8129 /* Itbl support may require additional care here. */
df58fc94 8130 goto ld_st;
252b5132 8131 case M_SDC2_AB:
df58fc94
RS
8132 ab = 1;
8133 case M_SDC2_OB:
252b5132 8134 s = "sdc2";
df58fc94
RS
8135 fmt = COP12_FMT;
8136 off12 = mips_opts.micromips;
bdaaa2e1 8137 /* Itbl support may require additional care here. */
252b5132 8138 coproc = 1;
df58fc94 8139 goto ld_st;
252b5132 8140 case M_SDC3_AB:
df58fc94
RS
8141 ab = 1;
8142 gas_assert (!mips_opts.micromips);
252b5132 8143 s = "sdc3";
df58fc94 8144 fmt = "E,o(b)";
bdaaa2e1 8145 /* Itbl support may require additional care here. */
252b5132 8146 coproc = 1;
df58fc94 8147 goto ld_st;
252b5132 8148 case M_SDL_AB:
df58fc94
RS
8149 ab = 1;
8150 case M_SDL_OB:
252b5132 8151 s = "sdl";
df58fc94
RS
8152 fmt = MEM12_FMT;
8153 off12 = mips_opts.micromips;
8154 goto ld_st;
252b5132 8155 case M_SDR_AB:
df58fc94
RS
8156 ab = 1;
8157 case M_SDR_OB:
252b5132 8158 s = "sdr";
df58fc94
RS
8159 fmt = MEM12_FMT;
8160 off12 = mips_opts.micromips;
8161 goto ld_st;
8162 case M_SWP_AB:
8163 ab = 1;
8164 case M_SWP_OB:
8165 gas_assert (mips_opts.micromips);
8166 s = "swp";
8167 fmt = "t,~(b)";
8168 off12 = 1;
8169 goto ld_st;
8170 case M_SDP_AB:
8171 ab = 1;
8172 case M_SDP_OB:
8173 gas_assert (mips_opts.micromips);
8174 s = "sdp";
8175 fmt = "t,~(b)";
8176 off12 = 1;
8177 goto ld_st;
8178 case M_SWM_AB:
8179 ab = 1;
8180 case M_SWM_OB:
8181 gas_assert (mips_opts.micromips);
8182 s = "swm";
8183 fmt = "n,~(b)";
8184 off12 = 1;
8185 goto ld_st;
8186 case M_SDM_AB:
8187 ab = 1;
8188 case M_SDM_OB:
8189 gas_assert (mips_opts.micromips);
8190 s = "sdm";
8191 fmt = "n,~(b)";
8192 off12 = 1;
8193
8194 ld_st:
8fc2e39e
TS
8195 tempreg = AT;
8196 used_at = 1;
df58fc94 8197 ld_noat:
b19e8a9b
AN
8198 if (coproc
8199 && NO_ISA_COP (mips_opts.arch)
8200 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
8201 {
f71d0d44 8202 as_bad (_("Opcode not supported on this processor: %s"),
b19e8a9b
AN
8203 mips_cpu_info_from_arch (mips_opts.arch)->name);
8204 break;
8205 }
8206
252b5132
RH
8207 if (offset_expr.X_op != O_constant
8208 && offset_expr.X_op != O_symbol)
8209 {
f71d0d44 8210 as_bad (_("Expression too complex"));
252b5132
RH
8211 offset_expr.X_op = O_constant;
8212 }
8213
2051e8c4
MR
8214 if (HAVE_32BIT_ADDRESSES
8215 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
55e08f71
NC
8216 {
8217 char value [32];
8218
8219 sprintf_vma (value, offset_expr.X_add_number);
20e1fcfd 8220 as_bad (_("Number (0x%s) larger than 32 bits"), value);
55e08f71 8221 }
2051e8c4 8222
252b5132
RH
8223 /* A constant expression in PIC code can be handled just as it
8224 is in non PIC code. */
aed1a261
RS
8225 if (offset_expr.X_op == O_constant)
8226 {
df58fc94
RS
8227 int hipart = 0;
8228
842f8b2a 8229 expr1.X_add_number = offset_expr.X_add_number;
2051e8c4 8230 normalize_address_expr (&expr1);
df58fc94 8231 if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number))
842f8b2a
MR
8232 {
8233 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
8234 & ~(bfd_vma) 0xffff);
df58fc94
RS
8235 hipart = 1;
8236 }
8237 else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
8238 {
8239 expr1.X_add_number = ((expr1.X_add_number + 0x800)
8240 & ~(bfd_vma) 0xfff);
8241 hipart = 1;
8242 }
8243 if (hipart)
8244 {
842f8b2a
MR
8245 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
8246 if (breg != 0)
8247 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8248 tempreg, tempreg, breg);
8249 breg = tempreg;
8250 }
df58fc94
RS
8251 if (!off12)
8252 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
8253 else
8254 macro_build (NULL, s, fmt,
8255 treg, (unsigned long) offset_expr.X_add_number, breg);
8256 }
8257 else if (off12)
8258 {
8259 /* A 12-bit offset field is too narrow to be used for a low-part
8260 relocation, so load the whole address into the auxillary
8261 register. In the case of "A(b)" addresses, we first load
8262 absolute address "A" into the register and then add base
8263 register "b". In the case of "o(b)" addresses, we simply
8264 need to add 16-bit offset "o" to base register "b", and
8265 offset_reloc already contains the relocations associated
8266 with "o". */
8267 if (ab)
8268 {
8269 load_address (tempreg, &offset_expr, &used_at);
8270 if (breg != 0)
8271 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8272 tempreg, tempreg, breg);
8273 }
8274 else
8275 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8276 tempreg, breg, -1,
8277 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8278 expr1.X_add_number = 0;
8279 macro_build (NULL, s, fmt,
8280 treg, (unsigned long) expr1.X_add_number, tempreg);
aed1a261
RS
8281 }
8282 else if (mips_pic == NO_PIC)
252b5132
RH
8283 {
8284 /* If this is a reference to a GP relative symbol, and there
8285 is no base register, we want
cdf6fd85 8286 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
252b5132
RH
8287 Otherwise, if there is no base register, we want
8288 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8289 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8290 If we have a constant, we need two instructions anyhow,
8291 so we always use the latter form.
8292
8293 If we have a base register, and this is a reference to a
8294 GP relative symbol, we want
8295 addu $tempreg,$breg,$gp
cdf6fd85 8296 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
252b5132
RH
8297 Otherwise we want
8298 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8299 addu $tempreg,$tempreg,$breg
8300 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
d6bc6245 8301 With a constant we always use the latter case.
76b3015f 8302
d6bc6245
TS
8303 With 64bit address space and no base register and $at usable,
8304 we want
8305 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8306 lui $at,<sym> (BFD_RELOC_HI16_S)
8307 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8308 dsll32 $tempreg,0
8309 daddu $tempreg,$at
8310 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8311 If we have a base register, we want
8312 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8313 lui $at,<sym> (BFD_RELOC_HI16_S)
8314 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8315 daddu $at,$breg
8316 dsll32 $tempreg,0
8317 daddu $tempreg,$at
8318 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8319
8320 Without $at we can't generate the optimal path for superscalar
8321 processors here since this would require two temporary registers.
8322 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8323 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8324 dsll $tempreg,16
8325 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8326 dsll $tempreg,16
8327 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8328 If we have a base register, we want
8329 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8330 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8331 dsll $tempreg,16
8332 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8333 dsll $tempreg,16
8334 daddu $tempreg,$tempreg,$breg
8335 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6373ee54 8336
6caf9ef4 8337 For GP relative symbols in 64bit address space we can use
aed1a261
RS
8338 the same sequence as in 32bit address space. */
8339 if (HAVE_64BIT_SYMBOLS)
d6bc6245 8340 {
aed1a261 8341 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4
TS
8342 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8343 {
8344 relax_start (offset_expr.X_add_symbol);
8345 if (breg == 0)
8346 {
8347 macro_build (&offset_expr, s, fmt, treg,
8348 BFD_RELOC_GPREL16, mips_gp_register);
8349 }
8350 else
8351 {
8352 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8353 tempreg, breg, mips_gp_register);
8354 macro_build (&offset_expr, s, fmt, treg,
8355 BFD_RELOC_GPREL16, tempreg);
8356 }
8357 relax_switch ();
8358 }
d6bc6245 8359
741fe287 8360 if (used_at == 0 && mips_opts.at)
d6bc6245 8361 {
df58fc94 8362 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
67c0d1eb 8363 BFD_RELOC_MIPS_HIGHEST);
df58fc94 8364 macro_build (&offset_expr, "lui", LUI_FMT, AT,
67c0d1eb
RS
8365 BFD_RELOC_HI16_S);
8366 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8367 tempreg, BFD_RELOC_MIPS_HIGHER);
d6bc6245 8368 if (breg != 0)
67c0d1eb 8369 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
df58fc94 8370 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
67c0d1eb
RS
8371 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8372 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
8373 tempreg);
d6bc6245
TS
8374 used_at = 1;
8375 }
8376 else
8377 {
df58fc94 8378 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
67c0d1eb
RS
8379 BFD_RELOC_MIPS_HIGHEST);
8380 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8381 tempreg, BFD_RELOC_MIPS_HIGHER);
df58fc94 8382 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
67c0d1eb
RS
8383 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8384 tempreg, BFD_RELOC_HI16_S);
df58fc94 8385 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
d6bc6245 8386 if (breg != 0)
67c0d1eb 8387 macro_build (NULL, "daddu", "d,v,t",
17a2f251 8388 tempreg, tempreg, breg);
67c0d1eb 8389 macro_build (&offset_expr, s, fmt, treg,
17a2f251 8390 BFD_RELOC_LO16, tempreg);
d6bc6245 8391 }
6caf9ef4
TS
8392
8393 if (mips_relax.sequence)
8394 relax_end ();
8fc2e39e 8395 break;
d6bc6245 8396 }
256ab948 8397
252b5132
RH
8398 if (breg == 0)
8399 {
67c0d1eb 8400 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 8401 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
252b5132 8402 {
4d7206a2 8403 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
8404 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
8405 mips_gp_register);
4d7206a2 8406 relax_switch ();
252b5132 8407 }
67c0d1eb
RS
8408 macro_build_lui (&offset_expr, tempreg);
8409 macro_build (&offset_expr, s, fmt, treg,
17a2f251 8410 BFD_RELOC_LO16, tempreg);
4d7206a2
RS
8411 if (mips_relax.sequence)
8412 relax_end ();
252b5132
RH
8413 }
8414 else
8415 {
67c0d1eb 8416 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 8417 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
252b5132 8418 {
4d7206a2 8419 relax_start (offset_expr.X_add_symbol);
67c0d1eb 8420 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 8421 tempreg, breg, mips_gp_register);
67c0d1eb 8422 macro_build (&offset_expr, s, fmt, treg,
17a2f251 8423 BFD_RELOC_GPREL16, tempreg);
4d7206a2 8424 relax_switch ();
252b5132 8425 }
67c0d1eb
RS
8426 macro_build_lui (&offset_expr, tempreg);
8427 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 8428 tempreg, tempreg, breg);
67c0d1eb 8429 macro_build (&offset_expr, s, fmt, treg,
17a2f251 8430 BFD_RELOC_LO16, tempreg);
4d7206a2
RS
8431 if (mips_relax.sequence)
8432 relax_end ();
252b5132
RH
8433 }
8434 }
0a44bf69 8435 else if (!mips_big_got)
252b5132 8436 {
ed6fb7bd 8437 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
f9419b05 8438
252b5132
RH
8439 /* If this is a reference to an external symbol, we want
8440 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8441 nop
8442 <op> $treg,0($tempreg)
8443 Otherwise we want
8444 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8445 nop
8446 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8447 <op> $treg,0($tempreg)
f5040a92
AO
8448
8449 For NewABI, we want
8450 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8451 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8452
252b5132
RH
8453 If there is a base register, we add it to $tempreg before
8454 the <op>. If there is a constant, we stick it in the
8455 <op> instruction. We don't handle constants larger than
8456 16 bits, because we have no way to load the upper 16 bits
8457 (actually, we could handle them for the subset of cases
8458 in which we are not using $at). */
9c2799c2 8459 gas_assert (offset_expr.X_op == O_symbol);
f5040a92
AO
8460 if (HAVE_NEWABI)
8461 {
67c0d1eb
RS
8462 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8463 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
f5040a92 8464 if (breg != 0)
67c0d1eb 8465 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 8466 tempreg, tempreg, breg);
67c0d1eb 8467 macro_build (&offset_expr, s, fmt, treg,
17a2f251 8468 BFD_RELOC_MIPS_GOT_OFST, tempreg);
f5040a92
AO
8469 break;
8470 }
252b5132
RH
8471 expr1.X_add_number = offset_expr.X_add_number;
8472 offset_expr.X_add_number = 0;
8473 if (expr1.X_add_number < -0x8000
8474 || expr1.X_add_number >= 0x8000)
8475 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb
RS
8476 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8477 lw_reloc_type, mips_gp_register);
269137b2 8478 load_delay_nop ();
4d7206a2
RS
8479 relax_start (offset_expr.X_add_symbol);
8480 relax_switch ();
67c0d1eb
RS
8481 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8482 tempreg, BFD_RELOC_LO16);
4d7206a2 8483 relax_end ();
252b5132 8484 if (breg != 0)
67c0d1eb 8485 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 8486 tempreg, tempreg, breg);
67c0d1eb 8487 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
252b5132 8488 }
0a44bf69 8489 else if (mips_big_got && !HAVE_NEWABI)
252b5132 8490 {
67c0d1eb 8491 int gpdelay;
252b5132
RH
8492
8493 /* If this is a reference to an external symbol, we want
8494 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8495 addu $tempreg,$tempreg,$gp
8496 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8497 <op> $treg,0($tempreg)
8498 Otherwise we want
8499 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8500 nop
8501 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8502 <op> $treg,0($tempreg)
8503 If there is a base register, we add it to $tempreg before
8504 the <op>. If there is a constant, we stick it in the
8505 <op> instruction. We don't handle constants larger than
8506 16 bits, because we have no way to load the upper 16 bits
8507 (actually, we could handle them for the subset of cases
f5040a92 8508 in which we are not using $at). */
9c2799c2 8509 gas_assert (offset_expr.X_op == O_symbol);
252b5132
RH
8510 expr1.X_add_number = offset_expr.X_add_number;
8511 offset_expr.X_add_number = 0;
8512 if (expr1.X_add_number < -0x8000
8513 || expr1.X_add_number >= 0x8000)
8514 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb 8515 gpdelay = reg_needs_delay (mips_gp_register);
4d7206a2 8516 relax_start (offset_expr.X_add_symbol);
df58fc94 8517 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
17a2f251 8518 BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
8519 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8520 mips_gp_register);
8521 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8522 BFD_RELOC_MIPS_GOT_LO16, tempreg);
4d7206a2 8523 relax_switch ();
67c0d1eb
RS
8524 if (gpdelay)
8525 macro_build (NULL, "nop", "");
8526 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8527 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 8528 load_delay_nop ();
67c0d1eb
RS
8529 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8530 tempreg, BFD_RELOC_LO16);
4d7206a2
RS
8531 relax_end ();
8532
252b5132 8533 if (breg != 0)
67c0d1eb 8534 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 8535 tempreg, tempreg, breg);
67c0d1eb 8536 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
252b5132 8537 }
0a44bf69 8538 else if (mips_big_got && HAVE_NEWABI)
f5040a92 8539 {
f5040a92
AO
8540 /* If this is a reference to an external symbol, we want
8541 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8542 add $tempreg,$tempreg,$gp
8543 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8544 <op> $treg,<ofst>($tempreg)
8545 Otherwise, for local symbols, we want:
8546 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8547 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
9c2799c2 8548 gas_assert (offset_expr.X_op == O_symbol);
4d7206a2 8549 expr1.X_add_number = offset_expr.X_add_number;
f5040a92
AO
8550 offset_expr.X_add_number = 0;
8551 if (expr1.X_add_number < -0x8000
8552 || expr1.X_add_number >= 0x8000)
8553 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4d7206a2 8554 relax_start (offset_expr.X_add_symbol);
df58fc94 8555 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
17a2f251 8556 BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
8557 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8558 mips_gp_register);
8559 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8560 BFD_RELOC_MIPS_GOT_LO16, tempreg);
f5040a92 8561 if (breg != 0)
67c0d1eb 8562 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 8563 tempreg, tempreg, breg);
67c0d1eb 8564 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
684022ea 8565
4d7206a2 8566 relax_switch ();
f5040a92 8567 offset_expr.X_add_number = expr1.X_add_number;
67c0d1eb
RS
8568 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8569 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
f5040a92 8570 if (breg != 0)
67c0d1eb 8571 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 8572 tempreg, tempreg, breg);
67c0d1eb 8573 macro_build (&offset_expr, s, fmt, treg,
17a2f251 8574 BFD_RELOC_MIPS_GOT_OFST, tempreg);
4d7206a2 8575 relax_end ();
f5040a92 8576 }
252b5132
RH
8577 else
8578 abort ();
8579
252b5132
RH
8580 break;
8581
8582 case M_LI:
8583 case M_LI_S:
67c0d1eb 8584 load_register (treg, &imm_expr, 0);
8fc2e39e 8585 break;
252b5132
RH
8586
8587 case M_DLI:
67c0d1eb 8588 load_register (treg, &imm_expr, 1);
8fc2e39e 8589 break;
252b5132
RH
8590
8591 case M_LI_SS:
8592 if (imm_expr.X_op == O_constant)
8593 {
8fc2e39e 8594 used_at = 1;
67c0d1eb
RS
8595 load_register (AT, &imm_expr, 0);
8596 macro_build (NULL, "mtc1", "t,G", AT, treg);
252b5132
RH
8597 break;
8598 }
8599 else
8600 {
9c2799c2 8601 gas_assert (offset_expr.X_op == O_symbol
90ecf173
MR
8602 && strcmp (segment_name (S_GET_SEGMENT
8603 (offset_expr.X_add_symbol)),
8604 ".lit4") == 0
8605 && offset_expr.X_add_number == 0);
67c0d1eb 8606 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
17a2f251 8607 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8fc2e39e 8608 break;
252b5132
RH
8609 }
8610
8611 case M_LI_D:
ca4e0257
RS
8612 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8613 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8614 order 32 bits of the value and the low order 32 bits are either
8615 zero or in OFFSET_EXPR. */
252b5132
RH
8616 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8617 {
ca4e0257 8618 if (HAVE_64BIT_GPRS)
67c0d1eb 8619 load_register (treg, &imm_expr, 1);
252b5132
RH
8620 else
8621 {
8622 int hreg, lreg;
8623
8624 if (target_big_endian)
8625 {
8626 hreg = treg;
8627 lreg = treg + 1;
8628 }
8629 else
8630 {
8631 hreg = treg + 1;
8632 lreg = treg;
8633 }
8634
8635 if (hreg <= 31)
67c0d1eb 8636 load_register (hreg, &imm_expr, 0);
252b5132
RH
8637 if (lreg <= 31)
8638 {
8639 if (offset_expr.X_op == O_absent)
67c0d1eb 8640 move_register (lreg, 0);
252b5132
RH
8641 else
8642 {
9c2799c2 8643 gas_assert (offset_expr.X_op == O_constant);
67c0d1eb 8644 load_register (lreg, &offset_expr, 0);
252b5132
RH
8645 }
8646 }
8647 }
8fc2e39e 8648 break;
252b5132
RH
8649 }
8650
8651 /* We know that sym is in the .rdata section. First we get the
8652 upper 16 bits of the address. */
8653 if (mips_pic == NO_PIC)
8654 {
67c0d1eb 8655 macro_build_lui (&offset_expr, AT);
8fc2e39e 8656 used_at = 1;
252b5132 8657 }
0a44bf69 8658 else
252b5132 8659 {
67c0d1eb
RS
8660 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8661 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8fc2e39e 8662 used_at = 1;
252b5132 8663 }
bdaaa2e1 8664
252b5132 8665 /* Now we load the register(s). */
ca4e0257 8666 if (HAVE_64BIT_GPRS)
8fc2e39e
TS
8667 {
8668 used_at = 1;
8669 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8670 }
252b5132
RH
8671 else
8672 {
8fc2e39e 8673 used_at = 1;
67c0d1eb 8674 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
f9419b05 8675 if (treg != RA)
252b5132
RH
8676 {
8677 /* FIXME: How in the world do we deal with the possible
8678 overflow here? */
8679 offset_expr.X_add_number += 4;
67c0d1eb 8680 macro_build (&offset_expr, "lw", "t,o(b)",
17a2f251 8681 treg + 1, BFD_RELOC_LO16, AT);
252b5132
RH
8682 }
8683 }
252b5132
RH
8684 break;
8685
8686 case M_LI_DD:
ca4e0257
RS
8687 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8688 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8689 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8690 the value and the low order 32 bits are either zero or in
8691 OFFSET_EXPR. */
252b5132
RH
8692 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8693 {
8fc2e39e 8694 used_at = 1;
67c0d1eb 8695 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
ca4e0257
RS
8696 if (HAVE_64BIT_FPRS)
8697 {
9c2799c2 8698 gas_assert (HAVE_64BIT_GPRS);
67c0d1eb 8699 macro_build (NULL, "dmtc1", "t,S", AT, treg);
ca4e0257 8700 }
252b5132
RH
8701 else
8702 {
67c0d1eb 8703 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
252b5132 8704 if (offset_expr.X_op == O_absent)
67c0d1eb 8705 macro_build (NULL, "mtc1", "t,G", 0, treg);
252b5132
RH
8706 else
8707 {
9c2799c2 8708 gas_assert (offset_expr.X_op == O_constant);
67c0d1eb
RS
8709 load_register (AT, &offset_expr, 0);
8710 macro_build (NULL, "mtc1", "t,G", AT, treg);
252b5132
RH
8711 }
8712 }
8713 break;
8714 }
8715
9c2799c2 8716 gas_assert (offset_expr.X_op == O_symbol
90ecf173 8717 && offset_expr.X_add_number == 0);
252b5132
RH
8718 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
8719 if (strcmp (s, ".lit8") == 0)
8720 {
df58fc94 8721 if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
252b5132 8722 {
67c0d1eb 8723 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
17a2f251 8724 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8fc2e39e 8725 break;
252b5132 8726 }
c9914766 8727 breg = mips_gp_register;
252b5132
RH
8728 r = BFD_RELOC_MIPS_LITERAL;
8729 goto dob;
8730 }
8731 else
8732 {
9c2799c2 8733 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
8fc2e39e 8734 used_at = 1;
0a44bf69 8735 if (mips_pic != NO_PIC)
67c0d1eb
RS
8736 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8737 BFD_RELOC_MIPS_GOT16, mips_gp_register);
252b5132
RH
8738 else
8739 {
8740 /* FIXME: This won't work for a 64 bit address. */
67c0d1eb 8741 macro_build_lui (&offset_expr, AT);
252b5132 8742 }
bdaaa2e1 8743
df58fc94 8744 if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
252b5132 8745 {
67c0d1eb
RS
8746 macro_build (&offset_expr, "ldc1", "T,o(b)",
8747 treg, BFD_RELOC_LO16, AT);
252b5132
RH
8748 break;
8749 }
8750 breg = AT;
8751 r = BFD_RELOC_LO16;
8752 goto dob;
8753 }
8754
8755 case M_L_DOB:
252b5132
RH
8756 /* Even on a big endian machine $fn comes before $fn+1. We have
8757 to adjust when loading from memory. */
8758 r = BFD_RELOC_LO16;
8759 dob:
df58fc94 8760 gas_assert (!mips_opts.micromips);
9c2799c2 8761 gas_assert (mips_opts.isa == ISA_MIPS1);
67c0d1eb 8762 macro_build (&offset_expr, "lwc1", "T,o(b)",
17a2f251 8763 target_big_endian ? treg + 1 : treg, r, breg);
252b5132
RH
8764 /* FIXME: A possible overflow which I don't know how to deal
8765 with. */
8766 offset_expr.X_add_number += 4;
67c0d1eb 8767 macro_build (&offset_expr, "lwc1", "T,o(b)",
17a2f251 8768 target_big_endian ? treg : treg + 1, r, breg);
252b5132
RH
8769 break;
8770
c4a68bea 8771 case M_S_DOB:
df58fc94 8772 gas_assert (!mips_opts.micromips);
c4a68bea
MR
8773 gas_assert (mips_opts.isa == ISA_MIPS1);
8774 /* Even on a big endian machine $fn comes before $fn+1. We have
8775 to adjust when storing to memory. */
8776 macro_build (&offset_expr, "swc1", "T,o(b)",
8777 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
8778 offset_expr.X_add_number += 4;
8779 macro_build (&offset_expr, "swc1", "T,o(b)",
8780 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
8781 break;
8782
252b5132 8783 case M_L_DAB:
df58fc94 8784 gas_assert (!mips_opts.micromips);
252b5132
RH
8785 /*
8786 * The MIPS assembler seems to check for X_add_number not
8787 * being double aligned and generating:
8788 * lui at,%hi(foo+1)
8789 * addu at,at,v1
8790 * addiu at,at,%lo(foo+1)
8791 * lwc1 f2,0(at)
8792 * lwc1 f3,4(at)
8793 * But, the resulting address is the same after relocation so why
8794 * generate the extra instruction?
8795 */
bdaaa2e1 8796 /* Itbl support may require additional care here. */
252b5132 8797 coproc = 1;
df58fc94 8798 fmt = "T,o(b)";
e7af610e 8799 if (mips_opts.isa != ISA_MIPS1)
252b5132
RH
8800 {
8801 s = "ldc1";
df58fc94 8802 goto ld_st;
252b5132 8803 }
252b5132 8804 s = "lwc1";
252b5132
RH
8805 goto ldd_std;
8806
8807 case M_S_DAB:
df58fc94
RS
8808 gas_assert (!mips_opts.micromips);
8809 /* Itbl support may require additional care here. */
8810 coproc = 1;
8811 fmt = "T,o(b)";
e7af610e 8812 if (mips_opts.isa != ISA_MIPS1)
252b5132
RH
8813 {
8814 s = "sdc1";
df58fc94 8815 goto ld_st;
252b5132 8816 }
252b5132 8817 s = "swc1";
252b5132
RH
8818 goto ldd_std;
8819
8820 case M_LD_AB:
df58fc94 8821 fmt = "t,o(b)";
ca4e0257 8822 if (HAVE_64BIT_GPRS)
252b5132
RH
8823 {
8824 s = "ld";
8825 goto ld;
8826 }
252b5132 8827 s = "lw";
252b5132
RH
8828 goto ldd_std;
8829
8830 case M_SD_AB:
df58fc94 8831 fmt = "t,o(b)";
ca4e0257 8832 if (HAVE_64BIT_GPRS)
252b5132
RH
8833 {
8834 s = "sd";
df58fc94 8835 goto ld_st;
252b5132 8836 }
252b5132 8837 s = "sw";
252b5132
RH
8838
8839 ldd_std:
8840 if (offset_expr.X_op != O_symbol
8841 && offset_expr.X_op != O_constant)
8842 {
f71d0d44 8843 as_bad (_("Expression too complex"));
252b5132
RH
8844 offset_expr.X_op = O_constant;
8845 }
8846
2051e8c4
MR
8847 if (HAVE_32BIT_ADDRESSES
8848 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
55e08f71
NC
8849 {
8850 char value [32];
8851
8852 sprintf_vma (value, offset_expr.X_add_number);
20e1fcfd 8853 as_bad (_("Number (0x%s) larger than 32 bits"), value);
55e08f71 8854 }
2051e8c4 8855
252b5132
RH
8856 /* Even on a big endian machine $fn comes before $fn+1. We have
8857 to adjust when loading from memory. We set coproc if we must
8858 load $fn+1 first. */
bdaaa2e1 8859 /* Itbl support may require additional care here. */
90ecf173 8860 if (!target_big_endian)
252b5132
RH
8861 coproc = 0;
8862
90ecf173 8863 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
252b5132
RH
8864 {
8865 /* If this is a reference to a GP relative symbol, we want
cdf6fd85
TS
8866 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8867 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
252b5132
RH
8868 If we have a base register, we use this
8869 addu $at,$breg,$gp
cdf6fd85
TS
8870 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
8871 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
252b5132
RH
8872 If this is not a GP relative symbol, we want
8873 lui $at,<sym> (BFD_RELOC_HI16_S)
8874 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8875 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8876 If there is a base register, we add it to $at after the
8877 lui instruction. If there is a constant, we always use
8878 the last case. */
39a59cf8
MR
8879 if (offset_expr.X_op == O_symbol
8880 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 8881 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
252b5132 8882 {
4d7206a2 8883 relax_start (offset_expr.X_add_symbol);
252b5132
RH
8884 if (breg == 0)
8885 {
c9914766 8886 tempreg = mips_gp_register;
252b5132
RH
8887 }
8888 else
8889 {
67c0d1eb 8890 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 8891 AT, breg, mips_gp_register);
252b5132 8892 tempreg = AT;
252b5132
RH
8893 used_at = 1;
8894 }
8895
beae10d5 8896 /* Itbl support may require additional care here. */
67c0d1eb 8897 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
17a2f251 8898 BFD_RELOC_GPREL16, tempreg);
252b5132
RH
8899 offset_expr.X_add_number += 4;
8900
8901 /* Set mips_optimize to 2 to avoid inserting an
8902 undesired nop. */
8903 hold_mips_optimize = mips_optimize;
8904 mips_optimize = 2;
beae10d5 8905 /* Itbl support may require additional care here. */
67c0d1eb 8906 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
17a2f251 8907 BFD_RELOC_GPREL16, tempreg);
252b5132
RH
8908 mips_optimize = hold_mips_optimize;
8909
4d7206a2 8910 relax_switch ();
252b5132 8911
0970e49e 8912 offset_expr.X_add_number -= 4;
252b5132 8913 }
8fc2e39e 8914 used_at = 1;
67c0d1eb 8915 macro_build_lui (&offset_expr, AT);
252b5132 8916 if (breg != 0)
67c0d1eb 8917 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
beae10d5 8918 /* Itbl support may require additional care here. */
67c0d1eb 8919 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
17a2f251 8920 BFD_RELOC_LO16, AT);
252b5132
RH
8921 /* FIXME: How do we handle overflow here? */
8922 offset_expr.X_add_number += 4;
beae10d5 8923 /* Itbl support may require additional care here. */
67c0d1eb 8924 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
17a2f251 8925 BFD_RELOC_LO16, AT);
4d7206a2
RS
8926 if (mips_relax.sequence)
8927 relax_end ();
bdaaa2e1 8928 }
0a44bf69 8929 else if (!mips_big_got)
252b5132 8930 {
252b5132
RH
8931 /* If this is a reference to an external symbol, we want
8932 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8933 nop
8934 <op> $treg,0($at)
8935 <op> $treg+1,4($at)
8936 Otherwise we want
8937 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8938 nop
8939 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8940 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8941 If there is a base register we add it to $at before the
8942 lwc1 instructions. If there is a constant we include it
8943 in the lwc1 instructions. */
8944 used_at = 1;
8945 expr1.X_add_number = offset_expr.X_add_number;
252b5132
RH
8946 if (expr1.X_add_number < -0x8000
8947 || expr1.X_add_number >= 0x8000 - 4)
8948 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb 8949 load_got_offset (AT, &offset_expr);
269137b2 8950 load_delay_nop ();
252b5132 8951 if (breg != 0)
67c0d1eb 8952 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
252b5132
RH
8953
8954 /* Set mips_optimize to 2 to avoid inserting an undesired
8955 nop. */
8956 hold_mips_optimize = mips_optimize;
8957 mips_optimize = 2;
4d7206a2 8958
beae10d5 8959 /* Itbl support may require additional care here. */
4d7206a2 8960 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
8961 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
8962 BFD_RELOC_LO16, AT);
4d7206a2 8963 expr1.X_add_number += 4;
67c0d1eb
RS
8964 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
8965 BFD_RELOC_LO16, AT);
4d7206a2 8966 relax_switch ();
67c0d1eb
RS
8967 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
8968 BFD_RELOC_LO16, AT);
4d7206a2 8969 offset_expr.X_add_number += 4;
67c0d1eb
RS
8970 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
8971 BFD_RELOC_LO16, AT);
4d7206a2 8972 relax_end ();
252b5132 8973
4d7206a2 8974 mips_optimize = hold_mips_optimize;
252b5132 8975 }
0a44bf69 8976 else if (mips_big_got)
252b5132 8977 {
67c0d1eb 8978 int gpdelay;
252b5132
RH
8979
8980 /* If this is a reference to an external symbol, we want
8981 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8982 addu $at,$at,$gp
8983 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
8984 nop
8985 <op> $treg,0($at)
8986 <op> $treg+1,4($at)
8987 Otherwise we want
8988 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8989 nop
8990 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8991 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8992 If there is a base register we add it to $at before the
8993 lwc1 instructions. If there is a constant we include it
8994 in the lwc1 instructions. */
8995 used_at = 1;
8996 expr1.X_add_number = offset_expr.X_add_number;
8997 offset_expr.X_add_number = 0;
8998 if (expr1.X_add_number < -0x8000
8999 || expr1.X_add_number >= 0x8000 - 4)
9000 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb 9001 gpdelay = reg_needs_delay (mips_gp_register);
4d7206a2 9002 relax_start (offset_expr.X_add_symbol);
df58fc94 9003 macro_build (&offset_expr, "lui", LUI_FMT,
67c0d1eb
RS
9004 AT, BFD_RELOC_MIPS_GOT_HI16);
9005 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 9006 AT, AT, mips_gp_register);
67c0d1eb 9007 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
17a2f251 9008 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
269137b2 9009 load_delay_nop ();
252b5132 9010 if (breg != 0)
67c0d1eb 9011 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
beae10d5 9012 /* Itbl support may require additional care here. */
67c0d1eb 9013 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
17a2f251 9014 BFD_RELOC_LO16, AT);
252b5132
RH
9015 expr1.X_add_number += 4;
9016
9017 /* Set mips_optimize to 2 to avoid inserting an undesired
9018 nop. */
9019 hold_mips_optimize = mips_optimize;
9020 mips_optimize = 2;
beae10d5 9021 /* Itbl support may require additional care here. */
67c0d1eb 9022 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
17a2f251 9023 BFD_RELOC_LO16, AT);
252b5132
RH
9024 mips_optimize = hold_mips_optimize;
9025 expr1.X_add_number -= 4;
9026
4d7206a2
RS
9027 relax_switch ();
9028 offset_expr.X_add_number = expr1.X_add_number;
67c0d1eb
RS
9029 if (gpdelay)
9030 macro_build (NULL, "nop", "");
9031 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9032 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 9033 load_delay_nop ();
252b5132 9034 if (breg != 0)
67c0d1eb 9035 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
beae10d5 9036 /* Itbl support may require additional care here. */
67c0d1eb
RS
9037 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9038 BFD_RELOC_LO16, AT);
4d7206a2 9039 offset_expr.X_add_number += 4;
252b5132
RH
9040
9041 /* Set mips_optimize to 2 to avoid inserting an undesired
9042 nop. */
9043 hold_mips_optimize = mips_optimize;
9044 mips_optimize = 2;
beae10d5 9045 /* Itbl support may require additional care here. */
67c0d1eb
RS
9046 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9047 BFD_RELOC_LO16, AT);
252b5132 9048 mips_optimize = hold_mips_optimize;
4d7206a2 9049 relax_end ();
252b5132 9050 }
252b5132
RH
9051 else
9052 abort ();
9053
252b5132
RH
9054 break;
9055
9056 case M_LD_OB:
704897fb 9057 s = HAVE_64BIT_GPRS ? "ld" : "lw";
252b5132
RH
9058 goto sd_ob;
9059 case M_SD_OB:
704897fb 9060 s = HAVE_64BIT_GPRS ? "sd" : "sw";
252b5132 9061 sd_ob:
4614d845
MR
9062 macro_build (&offset_expr, s, "t,o(b)", treg,
9063 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9064 breg);
704897fb
MR
9065 if (!HAVE_64BIT_GPRS)
9066 {
9067 offset_expr.X_add_number += 4;
9068 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
4614d845
MR
9069 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9070 breg);
704897fb 9071 }
8fc2e39e 9072 break;
252b5132
RH
9073
9074 /* New code added to support COPZ instructions.
9075 This code builds table entries out of the macros in mip_opcodes.
9076 R4000 uses interlocks to handle coproc delays.
9077 Other chips (like the R3000) require nops to be inserted for delays.
9078
f72c8c98 9079 FIXME: Currently, we require that the user handle delays.
252b5132
RH
9080 In order to fill delay slots for non-interlocked chips,
9081 we must have a way to specify delays based on the coprocessor.
9082 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9083 What are the side-effects of the cop instruction?
9084 What cache support might we have and what are its effects?
9085 Both coprocessor & memory require delays. how long???
bdaaa2e1 9086 What registers are read/set/modified?
252b5132
RH
9087
9088 If an itbl is provided to interpret cop instructions,
bdaaa2e1 9089 this knowledge can be encoded in the itbl spec. */
252b5132
RH
9090
9091 case M_COP0:
9092 s = "c0";
9093 goto copz;
9094 case M_COP1:
9095 s = "c1";
9096 goto copz;
9097 case M_COP2:
9098 s = "c2";
9099 goto copz;
9100 case M_COP3:
9101 s = "c3";
9102 copz:
df58fc94 9103 gas_assert (!mips_opts.micromips);
b19e8a9b
AN
9104 if (NO_ISA_COP (mips_opts.arch)
9105 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
9106 {
9107 as_bad (_("opcode not supported on this processor: %s"),
9108 mips_cpu_info_from_arch (mips_opts.arch)->name);
9109 break;
9110 }
9111
252b5132
RH
9112 /* For now we just do C (same as Cz). The parameter will be
9113 stored in insn_opcode by mips_ip. */
67c0d1eb 9114 macro_build (NULL, s, "C", ip->insn_opcode);
8fc2e39e 9115 break;
252b5132 9116
ea1fb5dc 9117 case M_MOVE:
67c0d1eb 9118 move_register (dreg, sreg);
8fc2e39e 9119 break;
ea1fb5dc 9120
252b5132
RH
9121 case M_DMUL:
9122 dbl = 1;
9123 case M_MUL:
67c0d1eb 9124 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
df58fc94 9125 macro_build (NULL, "mflo", MFHL_FMT, dreg);
8fc2e39e 9126 break;
252b5132
RH
9127
9128 case M_DMUL_I:
9129 dbl = 1;
9130 case M_MUL_I:
9131 /* The MIPS assembler some times generates shifts and adds. I'm
9132 not trying to be that fancy. GCC should do this for us
9133 anyway. */
8fc2e39e 9134 used_at = 1;
67c0d1eb
RS
9135 load_register (AT, &imm_expr, dbl);
9136 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
df58fc94 9137 macro_build (NULL, "mflo", MFHL_FMT, dreg);
252b5132
RH
9138 break;
9139
9140 case M_DMULO_I:
9141 dbl = 1;
9142 case M_MULO_I:
9143 imm = 1;
9144 goto do_mulo;
9145
9146 case M_DMULO:
9147 dbl = 1;
9148 case M_MULO:
9149 do_mulo:
7d10b47d 9150 start_noreorder ();
8fc2e39e 9151 used_at = 1;
252b5132 9152 if (imm)
67c0d1eb
RS
9153 load_register (AT, &imm_expr, dbl);
9154 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
df58fc94
RS
9155 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9156 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
9157 macro_build (NULL, "mfhi", MFHL_FMT, AT);
252b5132 9158 if (mips_trap)
df58fc94 9159 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
252b5132
RH
9160 else
9161 {
df58fc94
RS
9162 if (mips_opts.micromips)
9163 micromips_label_expr (&label_expr);
9164 else
9165 label_expr.X_add_number = 8;
9166 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
a605d2b3 9167 macro_build (NULL, "nop", "");
df58fc94
RS
9168 macro_build (NULL, "break", BRK_FMT, 6);
9169 if (mips_opts.micromips)
9170 micromips_add_label ();
252b5132 9171 }
7d10b47d 9172 end_noreorder ();
df58fc94 9173 macro_build (NULL, "mflo", MFHL_FMT, dreg);
252b5132
RH
9174 break;
9175
9176 case M_DMULOU_I:
9177 dbl = 1;
9178 case M_MULOU_I:
9179 imm = 1;
9180 goto do_mulou;
9181
9182 case M_DMULOU:
9183 dbl = 1;
9184 case M_MULOU:
9185 do_mulou:
7d10b47d 9186 start_noreorder ();
8fc2e39e 9187 used_at = 1;
252b5132 9188 if (imm)
67c0d1eb
RS
9189 load_register (AT, &imm_expr, dbl);
9190 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
17a2f251 9191 sreg, imm ? AT : treg);
df58fc94
RS
9192 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9193 macro_build (NULL, "mflo", MFHL_FMT, dreg);
252b5132 9194 if (mips_trap)
df58fc94 9195 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
252b5132
RH
9196 else
9197 {
df58fc94
RS
9198 if (mips_opts.micromips)
9199 micromips_label_expr (&label_expr);
9200 else
9201 label_expr.X_add_number = 8;
9202 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
a605d2b3 9203 macro_build (NULL, "nop", "");
df58fc94
RS
9204 macro_build (NULL, "break", BRK_FMT, 6);
9205 if (mips_opts.micromips)
9206 micromips_add_label ();
252b5132 9207 }
7d10b47d 9208 end_noreorder ();
252b5132
RH
9209 break;
9210
771c7ce4 9211 case M_DROL:
fef14a42 9212 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
82dd0097
CD
9213 {
9214 if (dreg == sreg)
9215 {
9216 tempreg = AT;
9217 used_at = 1;
9218 }
9219 else
9220 {
9221 tempreg = dreg;
82dd0097 9222 }
67c0d1eb
RS
9223 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
9224 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
8fc2e39e 9225 break;
82dd0097 9226 }
8fc2e39e 9227 used_at = 1;
c80c840e 9228 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
67c0d1eb
RS
9229 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
9230 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
9231 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
771c7ce4
TS
9232 break;
9233
252b5132 9234 case M_ROL:
fef14a42 9235 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
82dd0097
CD
9236 {
9237 if (dreg == sreg)
9238 {
9239 tempreg = AT;
9240 used_at = 1;
9241 }
9242 else
9243 {
9244 tempreg = dreg;
82dd0097 9245 }
67c0d1eb
RS
9246 macro_build (NULL, "negu", "d,w", tempreg, treg);
9247 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
8fc2e39e 9248 break;
82dd0097 9249 }
8fc2e39e 9250 used_at = 1;
c80c840e 9251 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
67c0d1eb
RS
9252 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
9253 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
9254 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
252b5132
RH
9255 break;
9256
771c7ce4
TS
9257 case M_DROL_I:
9258 {
9259 unsigned int rot;
91d6fa6a
NC
9260 char *l;
9261 char *rr;
771c7ce4
TS
9262
9263 if (imm_expr.X_op != O_constant)
82dd0097 9264 as_bad (_("Improper rotate count"));
771c7ce4 9265 rot = imm_expr.X_add_number & 0x3f;
fef14a42 9266 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
60b63b72
RS
9267 {
9268 rot = (64 - rot) & 0x3f;
9269 if (rot >= 32)
df58fc94 9270 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
60b63b72 9271 else
df58fc94 9272 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
8fc2e39e 9273 break;
60b63b72 9274 }
483fc7cd 9275 if (rot == 0)
483fc7cd 9276 {
df58fc94 9277 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
8fc2e39e 9278 break;
483fc7cd 9279 }
82dd0097 9280 l = (rot < 0x20) ? "dsll" : "dsll32";
91d6fa6a 9281 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
82dd0097 9282 rot &= 0x1f;
8fc2e39e 9283 used_at = 1;
df58fc94
RS
9284 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
9285 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
67c0d1eb 9286 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
771c7ce4
TS
9287 }
9288 break;
9289
252b5132 9290 case M_ROL_I:
771c7ce4
TS
9291 {
9292 unsigned int rot;
9293
9294 if (imm_expr.X_op != O_constant)
82dd0097 9295 as_bad (_("Improper rotate count"));
771c7ce4 9296 rot = imm_expr.X_add_number & 0x1f;
fef14a42 9297 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
60b63b72 9298 {
df58fc94 9299 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
8fc2e39e 9300 break;
60b63b72 9301 }
483fc7cd 9302 if (rot == 0)
483fc7cd 9303 {
df58fc94 9304 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
8fc2e39e 9305 break;
483fc7cd 9306 }
8fc2e39e 9307 used_at = 1;
df58fc94
RS
9308 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
9309 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
67c0d1eb 9310 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
771c7ce4
TS
9311 }
9312 break;
9313
9314 case M_DROR:
fef14a42 9315 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
82dd0097 9316 {
67c0d1eb 9317 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
8fc2e39e 9318 break;
82dd0097 9319 }
8fc2e39e 9320 used_at = 1;
c80c840e 9321 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
67c0d1eb
RS
9322 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
9323 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
9324 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
252b5132
RH
9325 break;
9326
9327 case M_ROR:
fef14a42 9328 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
82dd0097 9329 {
67c0d1eb 9330 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
8fc2e39e 9331 break;
82dd0097 9332 }
8fc2e39e 9333 used_at = 1;
c80c840e 9334 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
67c0d1eb
RS
9335 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
9336 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
9337 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
252b5132
RH
9338 break;
9339
771c7ce4
TS
9340 case M_DROR_I:
9341 {
9342 unsigned int rot;
91d6fa6a
NC
9343 char *l;
9344 char *rr;
771c7ce4
TS
9345
9346 if (imm_expr.X_op != O_constant)
82dd0097 9347 as_bad (_("Improper rotate count"));
771c7ce4 9348 rot = imm_expr.X_add_number & 0x3f;
fef14a42 9349 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
82dd0097
CD
9350 {
9351 if (rot >= 32)
df58fc94 9352 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
82dd0097 9353 else
df58fc94 9354 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
8fc2e39e 9355 break;
82dd0097 9356 }
483fc7cd 9357 if (rot == 0)
483fc7cd 9358 {
df58fc94 9359 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
8fc2e39e 9360 break;
483fc7cd 9361 }
91d6fa6a 9362 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
82dd0097
CD
9363 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
9364 rot &= 0x1f;
8fc2e39e 9365 used_at = 1;
df58fc94
RS
9366 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
9367 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
67c0d1eb 9368 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
771c7ce4
TS
9369 }
9370 break;
9371
252b5132 9372 case M_ROR_I:
771c7ce4
TS
9373 {
9374 unsigned int rot;
9375
9376 if (imm_expr.X_op != O_constant)
82dd0097 9377 as_bad (_("Improper rotate count"));
771c7ce4 9378 rot = imm_expr.X_add_number & 0x1f;
fef14a42 9379 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
82dd0097 9380 {
df58fc94 9381 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
8fc2e39e 9382 break;
82dd0097 9383 }
483fc7cd 9384 if (rot == 0)
483fc7cd 9385 {
df58fc94 9386 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
8fc2e39e 9387 break;
483fc7cd 9388 }
8fc2e39e 9389 used_at = 1;
df58fc94
RS
9390 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
9391 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
67c0d1eb 9392 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
771c7ce4 9393 }
252b5132
RH
9394 break;
9395
252b5132
RH
9396 case M_SEQ:
9397 if (sreg == 0)
67c0d1eb 9398 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
252b5132 9399 else if (treg == 0)
67c0d1eb 9400 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
252b5132
RH
9401 else
9402 {
67c0d1eb
RS
9403 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9404 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
252b5132 9405 }
8fc2e39e 9406 break;
252b5132
RH
9407
9408 case M_SEQ_I:
9409 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9410 {
67c0d1eb 9411 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8fc2e39e 9412 break;
252b5132
RH
9413 }
9414 if (sreg == 0)
9415 {
9416 as_warn (_("Instruction %s: result is always false"),
9417 ip->insn_mo->name);
67c0d1eb 9418 move_register (dreg, 0);
8fc2e39e 9419 break;
252b5132 9420 }
dd3cbb7e
NC
9421 if (CPU_HAS_SEQ (mips_opts.arch)
9422 && -512 <= imm_expr.X_add_number
9423 && imm_expr.X_add_number < 512)
9424 {
9425 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
750bdd57 9426 (int) imm_expr.X_add_number);
dd3cbb7e
NC
9427 break;
9428 }
252b5132
RH
9429 if (imm_expr.X_op == O_constant
9430 && imm_expr.X_add_number >= 0
9431 && imm_expr.X_add_number < 0x10000)
9432 {
67c0d1eb 9433 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
252b5132
RH
9434 }
9435 else if (imm_expr.X_op == O_constant
9436 && imm_expr.X_add_number > -0x8000
9437 && imm_expr.X_add_number < 0)
9438 {
9439 imm_expr.X_add_number = -imm_expr.X_add_number;
67c0d1eb 9440 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
17a2f251 9441 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
252b5132 9442 }
dd3cbb7e
NC
9443 else if (CPU_HAS_SEQ (mips_opts.arch))
9444 {
9445 used_at = 1;
9446 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9447 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
9448 break;
9449 }
252b5132
RH
9450 else
9451 {
67c0d1eb
RS
9452 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9453 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
252b5132
RH
9454 used_at = 1;
9455 }
67c0d1eb 9456 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
8fc2e39e 9457 break;
252b5132
RH
9458
9459 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
9460 s = "slt";
9461 goto sge;
9462 case M_SGEU:
9463 s = "sltu";
9464 sge:
67c0d1eb
RS
9465 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
9466 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8fc2e39e 9467 break;
252b5132
RH
9468
9469 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
9470 case M_SGEU_I:
9471 if (imm_expr.X_op == O_constant
9472 && imm_expr.X_add_number >= -0x8000
9473 && imm_expr.X_add_number < 0x8000)
9474 {
67c0d1eb
RS
9475 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
9476 dreg, sreg, BFD_RELOC_LO16);
252b5132
RH
9477 }
9478 else
9479 {
67c0d1eb
RS
9480 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9481 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
9482 dreg, sreg, AT);
252b5132
RH
9483 used_at = 1;
9484 }
67c0d1eb 9485 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8fc2e39e 9486 break;
252b5132
RH
9487
9488 case M_SGT: /* sreg > treg <==> treg < sreg */
9489 s = "slt";
9490 goto sgt;
9491 case M_SGTU:
9492 s = "sltu";
9493 sgt:
67c0d1eb 9494 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
8fc2e39e 9495 break;
252b5132
RH
9496
9497 case M_SGT_I: /* sreg > I <==> I < sreg */
9498 s = "slt";
9499 goto sgti;
9500 case M_SGTU_I:
9501 s = "sltu";
9502 sgti:
8fc2e39e 9503 used_at = 1;
67c0d1eb
RS
9504 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9505 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
252b5132
RH
9506 break;
9507
2396cfb9 9508 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
252b5132
RH
9509 s = "slt";
9510 goto sle;
9511 case M_SLEU:
9512 s = "sltu";
9513 sle:
67c0d1eb
RS
9514 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9515 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8fc2e39e 9516 break;
252b5132 9517
2396cfb9 9518 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
252b5132
RH
9519 s = "slt";
9520 goto slei;
9521 case M_SLEU_I:
9522 s = "sltu";
9523 slei:
8fc2e39e 9524 used_at = 1;
67c0d1eb
RS
9525 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9526 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9527 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
252b5132
RH
9528 break;
9529
9530 case M_SLT_I:
9531 if (imm_expr.X_op == O_constant
9532 && imm_expr.X_add_number >= -0x8000
9533 && imm_expr.X_add_number < 0x8000)
9534 {
67c0d1eb 9535 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8fc2e39e 9536 break;
252b5132 9537 }
8fc2e39e 9538 used_at = 1;
67c0d1eb
RS
9539 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9540 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
252b5132
RH
9541 break;
9542
9543 case M_SLTU_I:
9544 if (imm_expr.X_op == O_constant
9545 && imm_expr.X_add_number >= -0x8000
9546 && imm_expr.X_add_number < 0x8000)
9547 {
67c0d1eb 9548 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
17a2f251 9549 BFD_RELOC_LO16);
8fc2e39e 9550 break;
252b5132 9551 }
8fc2e39e 9552 used_at = 1;
67c0d1eb
RS
9553 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9554 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
252b5132
RH
9555 break;
9556
9557 case M_SNE:
9558 if (sreg == 0)
67c0d1eb 9559 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
252b5132 9560 else if (treg == 0)
67c0d1eb 9561 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
252b5132
RH
9562 else
9563 {
67c0d1eb
RS
9564 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9565 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
252b5132 9566 }
8fc2e39e 9567 break;
252b5132
RH
9568
9569 case M_SNE_I:
9570 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9571 {
67c0d1eb 9572 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
8fc2e39e 9573 break;
252b5132
RH
9574 }
9575 if (sreg == 0)
9576 {
9577 as_warn (_("Instruction %s: result is always true"),
9578 ip->insn_mo->name);
67c0d1eb
RS
9579 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
9580 dreg, 0, BFD_RELOC_LO16);
8fc2e39e 9581 break;
252b5132 9582 }
dd3cbb7e
NC
9583 if (CPU_HAS_SEQ (mips_opts.arch)
9584 && -512 <= imm_expr.X_add_number
9585 && imm_expr.X_add_number < 512)
9586 {
9587 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
750bdd57 9588 (int) imm_expr.X_add_number);
dd3cbb7e
NC
9589 break;
9590 }
252b5132
RH
9591 if (imm_expr.X_op == O_constant
9592 && imm_expr.X_add_number >= 0
9593 && imm_expr.X_add_number < 0x10000)
9594 {
67c0d1eb 9595 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
252b5132
RH
9596 }
9597 else if (imm_expr.X_op == O_constant
9598 && imm_expr.X_add_number > -0x8000
9599 && imm_expr.X_add_number < 0)
9600 {
9601 imm_expr.X_add_number = -imm_expr.X_add_number;
67c0d1eb 9602 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
17a2f251 9603 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
252b5132 9604 }
dd3cbb7e
NC
9605 else if (CPU_HAS_SEQ (mips_opts.arch))
9606 {
9607 used_at = 1;
9608 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9609 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
9610 break;
9611 }
252b5132
RH
9612 else
9613 {
67c0d1eb
RS
9614 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9615 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
252b5132
RH
9616 used_at = 1;
9617 }
67c0d1eb 9618 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
8fc2e39e 9619 break;
252b5132 9620
df58fc94
RS
9621 case M_SUB_I:
9622 s = "addi";
9623 s2 = "sub";
9624 goto do_subi;
9625 case M_SUBU_I:
9626 s = "addiu";
9627 s2 = "subu";
9628 goto do_subi;
252b5132
RH
9629 case M_DSUB_I:
9630 dbl = 1;
df58fc94
RS
9631 s = "daddi";
9632 s2 = "dsub";
9633 if (!mips_opts.micromips)
9634 goto do_subi;
252b5132 9635 if (imm_expr.X_op == O_constant
df58fc94
RS
9636 && imm_expr.X_add_number > -0x200
9637 && imm_expr.X_add_number <= 0x200)
252b5132 9638 {
df58fc94 9639 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
8fc2e39e 9640 break;
252b5132 9641 }
df58fc94 9642 goto do_subi_i;
252b5132
RH
9643 case M_DSUBU_I:
9644 dbl = 1;
df58fc94
RS
9645 s = "daddiu";
9646 s2 = "dsubu";
9647 do_subi:
252b5132
RH
9648 if (imm_expr.X_op == O_constant
9649 && imm_expr.X_add_number > -0x8000
9650 && imm_expr.X_add_number <= 0x8000)
9651 {
9652 imm_expr.X_add_number = -imm_expr.X_add_number;
df58fc94 9653 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8fc2e39e 9654 break;
252b5132 9655 }
df58fc94 9656 do_subi_i:
8fc2e39e 9657 used_at = 1;
67c0d1eb 9658 load_register (AT, &imm_expr, dbl);
df58fc94 9659 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
252b5132
RH
9660 break;
9661
9662 case M_TEQ_I:
9663 s = "teq";
9664 goto trap;
9665 case M_TGE_I:
9666 s = "tge";
9667 goto trap;
9668 case M_TGEU_I:
9669 s = "tgeu";
9670 goto trap;
9671 case M_TLT_I:
9672 s = "tlt";
9673 goto trap;
9674 case M_TLTU_I:
9675 s = "tltu";
9676 goto trap;
9677 case M_TNE_I:
9678 s = "tne";
9679 trap:
8fc2e39e 9680 used_at = 1;
67c0d1eb
RS
9681 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9682 macro_build (NULL, s, "s,t", sreg, AT);
252b5132
RH
9683 break;
9684
252b5132 9685 case M_TRUNCWS:
43841e91 9686 case M_TRUNCWD:
df58fc94 9687 gas_assert (!mips_opts.micromips);
9c2799c2 9688 gas_assert (mips_opts.isa == ISA_MIPS1);
8fc2e39e 9689 used_at = 1;
252b5132
RH
9690 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
9691 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
9692
9693 /*
9694 * Is the double cfc1 instruction a bug in the mips assembler;
9695 * or is there a reason for it?
9696 */
7d10b47d 9697 start_noreorder ();
67c0d1eb
RS
9698 macro_build (NULL, "cfc1", "t,G", treg, RA);
9699 macro_build (NULL, "cfc1", "t,G", treg, RA);
9700 macro_build (NULL, "nop", "");
252b5132 9701 expr1.X_add_number = 3;
67c0d1eb 9702 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
252b5132 9703 expr1.X_add_number = 2;
67c0d1eb
RS
9704 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
9705 macro_build (NULL, "ctc1", "t,G", AT, RA);
9706 macro_build (NULL, "nop", "");
9707 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
9708 dreg, sreg);
9709 macro_build (NULL, "ctc1", "t,G", treg, RA);
9710 macro_build (NULL, "nop", "");
7d10b47d 9711 end_noreorder ();
252b5132
RH
9712 break;
9713
df58fc94
RS
9714 case M_ULH_A:
9715 ab = 1;
252b5132
RH
9716 case M_ULH:
9717 s = "lb";
df58fc94
RS
9718 s2 = "lbu";
9719 off = 1;
9720 goto uld_st;
9721 case M_ULHU_A:
9722 ab = 1;
252b5132
RH
9723 case M_ULHU:
9724 s = "lbu";
df58fc94
RS
9725 s2 = "lbu";
9726 off = 1;
9727 goto uld_st;
9728 case M_ULW_A:
9729 ab = 1;
9730 case M_ULW:
9731 s = "lwl";
9732 s2 = "lwr";
9733 off12 = mips_opts.micromips;
9734 off = 3;
9735 goto uld_st;
9736 case M_ULD_A:
9737 ab = 1;
252b5132
RH
9738 case M_ULD:
9739 s = "ldl";
9740 s2 = "ldr";
df58fc94 9741 off12 = mips_opts.micromips;
252b5132 9742 off = 7;
df58fc94
RS
9743 goto uld_st;
9744 case M_USH_A:
9745 ab = 1;
9746 case M_USH:
9747 s = "sb";
9748 s2 = "sb";
9749 off = 1;
9750 ust = 1;
9751 goto uld_st;
9752 case M_USW_A:
9753 ab = 1;
9754 case M_USW:
9755 s = "swl";
9756 s2 = "swr";
9757 off12 = mips_opts.micromips;
252b5132 9758 off = 3;
df58fc94
RS
9759 ust = 1;
9760 goto uld_st;
9761 case M_USD_A:
9762 ab = 1;
9763 case M_USD:
9764 s = "sdl";
9765 s2 = "sdr";
9766 off12 = mips_opts.micromips;
9767 off = 7;
9768 ust = 1;
9769
9770 uld_st:
9771 if (!ab && offset_expr.X_add_number >= 0x8000 - off)
f71d0d44 9772 as_bad (_("Operand overflow"));
df58fc94
RS
9773
9774 ep = &offset_expr;
9775 expr1.X_add_number = 0;
9776 if (ab)
9777 {
9778 used_at = 1;
9779 tempreg = AT;
9780 load_address (tempreg, ep, &used_at);
9781 if (breg != 0)
9782 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9783 tempreg, tempreg, breg);
9784 breg = tempreg;
9785 tempreg = treg;
9786 ep = &expr1;
9787 }
9788 else if (off12
9789 && (offset_expr.X_op != O_constant
9790 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number)
9791 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off)))
9792 {
9793 used_at = 1;
9794 tempreg = AT;
9795 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg,
9796 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
9797 breg = tempreg;
9798 tempreg = treg;
9799 ep = &expr1;
9800 }
9801 else if (!ust && treg == breg)
8fc2e39e
TS
9802 {
9803 used_at = 1;
9804 tempreg = AT;
9805 }
252b5132 9806 else
df58fc94 9807 tempreg = treg;
af22f5b2 9808
df58fc94
RS
9809 if (off == 1)
9810 goto ulh_sh;
252b5132 9811
90ecf173 9812 if (!target_big_endian)
df58fc94
RS
9813 ep->X_add_number += off;
9814 if (!off12)
9815 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
252b5132 9816 else
df58fc94
RS
9817 macro_build (NULL, s, "t,~(b)",
9818 tempreg, (unsigned long) ep->X_add_number, breg);
9819
90ecf173 9820 if (!target_big_endian)
df58fc94 9821 ep->X_add_number -= off;
252b5132 9822 else
df58fc94
RS
9823 ep->X_add_number += off;
9824 if (!off12)
9825 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9826 else
9827 macro_build (NULL, s2, "t,~(b)",
9828 tempreg, (unsigned long) ep->X_add_number, breg);
252b5132 9829
df58fc94
RS
9830 /* If necessary, move the result in tempreg to the final destination. */
9831 if (!ust && treg != tempreg)
9832 {
9833 /* Protect second load's delay slot. */
9834 load_delay_nop ();
9835 move_register (treg, tempreg);
9836 }
8fc2e39e 9837 break;
252b5132 9838
df58fc94 9839 ulh_sh:
d6bc6245 9840 used_at = 1;
df58fc94
RS
9841 if (target_big_endian == ust)
9842 ep->X_add_number += off;
9843 tempreg = ust || ab ? treg : AT;
9844 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9845
9846 /* For halfword transfers we need a temporary register to shuffle
9847 bytes. Unfortunately for M_USH_A we have none available before
9848 the next store as AT holds the base address. We deal with this
9849 case by clobbering TREG and then restoring it as with ULH. */
9850 tempreg = ust == ab ? treg : AT;
9851 if (ust)
9852 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
9853
9854 if (target_big_endian == ust)
9855 ep->X_add_number -= off;
252b5132 9856 else
df58fc94
RS
9857 ep->X_add_number += off;
9858 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
252b5132 9859
df58fc94
RS
9860 /* For M_USH_A re-retrieve the LSB. */
9861 if (ust && ab)
9862 {
9863 if (target_big_endian)
9864 ep->X_add_number += off;
9865 else
9866 ep->X_add_number -= off;
9867 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
9868 }
9869 /* For ULH and M_USH_A OR the LSB in. */
9870 if (!ust || ab)
9871 {
9872 tempreg = !ab ? AT : treg;
9873 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
9874 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
9875 }
252b5132
RH
9876 break;
9877
9878 default:
9879 /* FIXME: Check if this is one of the itbl macros, since they
bdaaa2e1 9880 are added dynamically. */
252b5132
RH
9881 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
9882 break;
9883 }
741fe287 9884 if (!mips_opts.at && used_at)
8fc2e39e 9885 as_bad (_("Macro used $at after \".set noat\""));
252b5132
RH
9886}
9887
9888/* Implement macros in mips16 mode. */
9889
9890static void
17a2f251 9891mips16_macro (struct mips_cl_insn *ip)
252b5132
RH
9892{
9893 int mask;
9894 int xreg, yreg, zreg, tmp;
252b5132
RH
9895 expressionS expr1;
9896 int dbl;
9897 const char *s, *s2, *s3;
9898
9899 mask = ip->insn_mo->mask;
9900
bf12938e
RS
9901 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
9902 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
9903 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
252b5132 9904
252b5132
RH
9905 expr1.X_op = O_constant;
9906 expr1.X_op_symbol = NULL;
9907 expr1.X_add_symbol = NULL;
9908 expr1.X_add_number = 1;
9909
9910 dbl = 0;
9911
9912 switch (mask)
9913 {
9914 default:
9915 internalError ();
9916
9917 case M_DDIV_3:
9918 dbl = 1;
9919 case M_DIV_3:
9920 s = "mflo";
9921 goto do_div3;
9922 case M_DREM_3:
9923 dbl = 1;
9924 case M_REM_3:
9925 s = "mfhi";
9926 do_div3:
7d10b47d 9927 start_noreorder ();
67c0d1eb 9928 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
252b5132 9929 expr1.X_add_number = 2;
67c0d1eb
RS
9930 macro_build (&expr1, "bnez", "x,p", yreg);
9931 macro_build (NULL, "break", "6", 7);
bdaaa2e1 9932
252b5132
RH
9933 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
9934 since that causes an overflow. We should do that as well,
9935 but I don't see how to do the comparisons without a temporary
9936 register. */
7d10b47d 9937 end_noreorder ();
67c0d1eb 9938 macro_build (NULL, s, "x", zreg);
252b5132
RH
9939 break;
9940
9941 case M_DIVU_3:
9942 s = "divu";
9943 s2 = "mflo";
9944 goto do_divu3;
9945 case M_REMU_3:
9946 s = "divu";
9947 s2 = "mfhi";
9948 goto do_divu3;
9949 case M_DDIVU_3:
9950 s = "ddivu";
9951 s2 = "mflo";
9952 goto do_divu3;
9953 case M_DREMU_3:
9954 s = "ddivu";
9955 s2 = "mfhi";
9956 do_divu3:
7d10b47d 9957 start_noreorder ();
67c0d1eb 9958 macro_build (NULL, s, "0,x,y", xreg, yreg);
252b5132 9959 expr1.X_add_number = 2;
67c0d1eb
RS
9960 macro_build (&expr1, "bnez", "x,p", yreg);
9961 macro_build (NULL, "break", "6", 7);
7d10b47d 9962 end_noreorder ();
67c0d1eb 9963 macro_build (NULL, s2, "x", zreg);
252b5132
RH
9964 break;
9965
9966 case M_DMUL:
9967 dbl = 1;
9968 case M_MUL:
67c0d1eb
RS
9969 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
9970 macro_build (NULL, "mflo", "x", zreg);
8fc2e39e 9971 break;
252b5132
RH
9972
9973 case M_DSUBU_I:
9974 dbl = 1;
9975 goto do_subu;
9976 case M_SUBU_I:
9977 do_subu:
9978 if (imm_expr.X_op != O_constant)
9979 as_bad (_("Unsupported large constant"));
9980 imm_expr.X_add_number = -imm_expr.X_add_number;
67c0d1eb 9981 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
252b5132
RH
9982 break;
9983
9984 case M_SUBU_I_2:
9985 if (imm_expr.X_op != O_constant)
9986 as_bad (_("Unsupported large constant"));
9987 imm_expr.X_add_number = -imm_expr.X_add_number;
67c0d1eb 9988 macro_build (&imm_expr, "addiu", "x,k", xreg);
252b5132
RH
9989 break;
9990
9991 case M_DSUBU_I_2:
9992 if (imm_expr.X_op != O_constant)
9993 as_bad (_("Unsupported large constant"));
9994 imm_expr.X_add_number = -imm_expr.X_add_number;
67c0d1eb 9995 macro_build (&imm_expr, "daddiu", "y,j", yreg);
252b5132
RH
9996 break;
9997
9998 case M_BEQ:
9999 s = "cmp";
10000 s2 = "bteqz";
10001 goto do_branch;
10002 case M_BNE:
10003 s = "cmp";
10004 s2 = "btnez";
10005 goto do_branch;
10006 case M_BLT:
10007 s = "slt";
10008 s2 = "btnez";
10009 goto do_branch;
10010 case M_BLTU:
10011 s = "sltu";
10012 s2 = "btnez";
10013 goto do_branch;
10014 case M_BLE:
10015 s = "slt";
10016 s2 = "bteqz";
10017 goto do_reverse_branch;
10018 case M_BLEU:
10019 s = "sltu";
10020 s2 = "bteqz";
10021 goto do_reverse_branch;
10022 case M_BGE:
10023 s = "slt";
10024 s2 = "bteqz";
10025 goto do_branch;
10026 case M_BGEU:
10027 s = "sltu";
10028 s2 = "bteqz";
10029 goto do_branch;
10030 case M_BGT:
10031 s = "slt";
10032 s2 = "btnez";
10033 goto do_reverse_branch;
10034 case M_BGTU:
10035 s = "sltu";
10036 s2 = "btnez";
10037
10038 do_reverse_branch:
10039 tmp = xreg;
10040 xreg = yreg;
10041 yreg = tmp;
10042
10043 do_branch:
67c0d1eb
RS
10044 macro_build (NULL, s, "x,y", xreg, yreg);
10045 macro_build (&offset_expr, s2, "p");
252b5132
RH
10046 break;
10047
10048 case M_BEQ_I:
10049 s = "cmpi";
10050 s2 = "bteqz";
10051 s3 = "x,U";
10052 goto do_branch_i;
10053 case M_BNE_I:
10054 s = "cmpi";
10055 s2 = "btnez";
10056 s3 = "x,U";
10057 goto do_branch_i;
10058 case M_BLT_I:
10059 s = "slti";
10060 s2 = "btnez";
10061 s3 = "x,8";
10062 goto do_branch_i;
10063 case M_BLTU_I:
10064 s = "sltiu";
10065 s2 = "btnez";
10066 s3 = "x,8";
10067 goto do_branch_i;
10068 case M_BLE_I:
10069 s = "slti";
10070 s2 = "btnez";
10071 s3 = "x,8";
10072 goto do_addone_branch_i;
10073 case M_BLEU_I:
10074 s = "sltiu";
10075 s2 = "btnez";
10076 s3 = "x,8";
10077 goto do_addone_branch_i;
10078 case M_BGE_I:
10079 s = "slti";
10080 s2 = "bteqz";
10081 s3 = "x,8";
10082 goto do_branch_i;
10083 case M_BGEU_I:
10084 s = "sltiu";
10085 s2 = "bteqz";
10086 s3 = "x,8";
10087 goto do_branch_i;
10088 case M_BGT_I:
10089 s = "slti";
10090 s2 = "bteqz";
10091 s3 = "x,8";
10092 goto do_addone_branch_i;
10093 case M_BGTU_I:
10094 s = "sltiu";
10095 s2 = "bteqz";
10096 s3 = "x,8";
10097
10098 do_addone_branch_i:
10099 if (imm_expr.X_op != O_constant)
10100 as_bad (_("Unsupported large constant"));
10101 ++imm_expr.X_add_number;
10102
10103 do_branch_i:
67c0d1eb
RS
10104 macro_build (&imm_expr, s, s3, xreg);
10105 macro_build (&offset_expr, s2, "p");
252b5132
RH
10106 break;
10107
10108 case M_ABS:
10109 expr1.X_add_number = 0;
67c0d1eb 10110 macro_build (&expr1, "slti", "x,8", yreg);
252b5132 10111 if (xreg != yreg)
67c0d1eb 10112 move_register (xreg, yreg);
252b5132 10113 expr1.X_add_number = 2;
67c0d1eb
RS
10114 macro_build (&expr1, "bteqz", "p");
10115 macro_build (NULL, "neg", "x,w", xreg, xreg);
252b5132
RH
10116 }
10117}
10118
10119/* For consistency checking, verify that all bits are specified either
10120 by the match/mask part of the instruction definition, or by the
10121 operand list. */
10122static int
17a2f251 10123validate_mips_insn (const struct mips_opcode *opc)
252b5132
RH
10124{
10125 const char *p = opc->args;
10126 char c;
10127 unsigned long used_bits = opc->mask;
10128
10129 if ((used_bits & opc->match) != opc->match)
10130 {
10131 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10132 opc->name, opc->args);
10133 return 0;
10134 }
10135#define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10136 while (*p)
10137 switch (c = *p++)
10138 {
10139 case ',': break;
10140 case '(': break;
10141 case ')': break;
af7ee8bf
CD
10142 case '+':
10143 switch (c = *p++)
10144 {
9bcd4f99
TS
10145 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
10146 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
10147 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
10148 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
af7ee8bf
CD
10149 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10150 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10151 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
bbcc0807
CD
10152 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
10153 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
5f74bc13
CD
10154 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10155 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10156 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10157 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10158 case 'I': break;
ef2e4d86
CF
10159 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10160 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
10161 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
bb35fb24
NC
10162 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10163 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10164 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10165 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
dd3cbb7e 10166 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
bb35fb24
NC
10167 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10168 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
98675402
RS
10169 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
10170 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
10171 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
10172 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
10173 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
bb35fb24 10174
af7ee8bf
CD
10175 default:
10176 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10177 c, opc->name, opc->args);
10178 return 0;
10179 }
10180 break;
252b5132
RH
10181 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10182 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10183 case 'A': break;
4372b673 10184 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
252b5132
RH
10185 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
10186 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10187 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10188 case 'F': break;
10189 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
156c2f8b 10190 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
252b5132 10191 case 'I': break;
e972090a 10192 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
af7ee8bf 10193 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
252b5132
RH
10194 case 'L': break;
10195 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
10196 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
deec1734
CD
10197 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
10198 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
10199 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
252b5132
RH
10200 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
10201 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10202 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10203 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10204 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
deec1734
CD
10205 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10206 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10207 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
252b5132
RH
10208 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10209 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10210 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
10211 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10212 case 'f': break;
10213 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
10214 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10215 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10216 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
10217 case 'l': break;
10218 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10219 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10220 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
10221 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10222 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10223 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10224 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10225 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10226 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10227 case 'x': break;
10228 case 'z': break;
10229 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
4372b673
NC
10230 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
10231 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
60b63b72
RS
10232 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
10233 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
10234 case '[': break;
10235 case ']': break;
620edafd 10236 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8b082fb1 10237 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
74cd071d
CF
10238 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
10239 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
10240 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
10241 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10242 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
10243 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
10244 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
10245 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
10246 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
10247 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
10248 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
ef2e4d86
CF
10249 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
10250 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
10251 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
10252 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
10253 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
252b5132
RH
10254 default:
10255 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10256 c, opc->name, opc->args);
10257 return 0;
10258 }
10259#undef USE_BITS
10260 if (used_bits != 0xffffffff)
10261 {
10262 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10263 ~used_bits & 0xffffffff, opc->name, opc->args);
10264 return 0;
10265 }
10266 return 1;
10267}
10268
df58fc94
RS
10269/* For consistency checking, verify that the length implied matches the
10270 major opcode and that all bits are specified either by the match/mask
10271 part of the instruction definition, or by the operand list. */
10272
10273static int
10274validate_micromips_insn (const struct mips_opcode *opc)
10275{
10276 unsigned long match = opc->match;
10277 unsigned long mask = opc->mask;
10278 const char *p = opc->args;
10279 unsigned long insn_bits;
10280 unsigned long used_bits;
10281 unsigned long major;
10282 unsigned int length;
10283 char e;
10284 char c;
10285
10286 if ((mask & match) != match)
10287 {
10288 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10289 opc->name, opc->args);
10290 return 0;
10291 }
10292 length = micromips_insn_length (opc);
10293 if (length != 2 && length != 4)
10294 {
10295 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10296 "%s %s"), length, opc->name, opc->args);
10297 return 0;
10298 }
10299 major = match >> (10 + 8 * (length - 2));
10300 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
10301 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
10302 {
10303 as_bad (_("Internal error: bad microMIPS opcode "
10304 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
10305 return 0;
10306 }
10307
10308 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10309 insn_bits = 1 << 4 * length;
10310 insn_bits <<= 4 * length;
10311 insn_bits -= 1;
10312 used_bits = mask;
10313#define USE_BITS(field) \
10314 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10315 while (*p)
10316 switch (c = *p++)
10317 {
10318 case ',': break;
10319 case '(': break;
10320 case ')': break;
10321 case '+':
10322 e = c;
10323 switch (c = *p++)
10324 {
10325 case 'A': USE_BITS (EXTLSB); break;
10326 case 'B': USE_BITS (INSMSB); break;
10327 case 'C': USE_BITS (EXTMSBD); break;
10328 case 'D': USE_BITS (RS); USE_BITS (SEL); break;
10329 case 'E': USE_BITS (EXTLSB); break;
10330 case 'F': USE_BITS (INSMSB); break;
10331 case 'G': USE_BITS (EXTMSBD); break;
10332 case 'H': USE_BITS (EXTMSBD); break;
10333 default:
10334 as_bad (_("Internal error: bad mips opcode "
10335 "(unknown extension operand type `%c%c'): %s %s"),
10336 e, c, opc->name, opc->args);
10337 return 0;
10338 }
10339 break;
10340 case 'm':
10341 e = c;
10342 switch (c = *p++)
10343 {
10344 case 'A': USE_BITS (IMMA); break;
10345 case 'B': USE_BITS (IMMB); break;
10346 case 'C': USE_BITS (IMMC); break;
10347 case 'D': USE_BITS (IMMD); break;
10348 case 'E': USE_BITS (IMME); break;
10349 case 'F': USE_BITS (IMMF); break;
10350 case 'G': USE_BITS (IMMG); break;
10351 case 'H': USE_BITS (IMMH); break;
10352 case 'I': USE_BITS (IMMI); break;
10353 case 'J': USE_BITS (IMMJ); break;
10354 case 'L': USE_BITS (IMML); break;
10355 case 'M': USE_BITS (IMMM); break;
10356 case 'N': USE_BITS (IMMN); break;
10357 case 'O': USE_BITS (IMMO); break;
10358 case 'P': USE_BITS (IMMP); break;
10359 case 'Q': USE_BITS (IMMQ); break;
10360 case 'U': USE_BITS (IMMU); break;
10361 case 'W': USE_BITS (IMMW); break;
10362 case 'X': USE_BITS (IMMX); break;
10363 case 'Y': USE_BITS (IMMY); break;
10364 case 'Z': break;
10365 case 'a': break;
10366 case 'b': USE_BITS (MB); break;
10367 case 'c': USE_BITS (MC); break;
10368 case 'd': USE_BITS (MD); break;
10369 case 'e': USE_BITS (ME); break;
10370 case 'f': USE_BITS (MF); break;
10371 case 'g': USE_BITS (MG); break;
10372 case 'h': USE_BITS (MH); break;
10373 case 'i': USE_BITS (MI); break;
10374 case 'j': USE_BITS (MJ); break;
10375 case 'l': USE_BITS (ML); break;
10376 case 'm': USE_BITS (MM); break;
10377 case 'n': USE_BITS (MN); break;
10378 case 'p': USE_BITS (MP); break;
10379 case 'q': USE_BITS (MQ); break;
10380 case 'r': break;
10381 case 's': break;
10382 case 't': break;
10383 case 'x': break;
10384 case 'y': break;
10385 case 'z': break;
10386 default:
10387 as_bad (_("Internal error: bad mips opcode "
10388 "(unknown extension operand type `%c%c'): %s %s"),
10389 e, c, opc->name, opc->args);
10390 return 0;
10391 }
10392 break;
10393 case '.': USE_BITS (OFFSET10); break;
10394 case '1': USE_BITS (STYPE); break;
10395 case '<': USE_BITS (SHAMT); break;
10396 case '>': USE_BITS (SHAMT); break;
10397 case 'B': USE_BITS (CODE10); break;
10398 case 'C': USE_BITS (COPZ); break;
10399 case 'D': USE_BITS (FD); break;
10400 case 'E': USE_BITS (RT); break;
10401 case 'G': USE_BITS (RS); break;
10402 case 'H': USE_BITS (SEL); break;
10403 case 'K': USE_BITS (RS); break;
10404 case 'M': USE_BITS (CCC); break;
10405 case 'N': USE_BITS (BCC); break;
10406 case 'R': USE_BITS (FR); break;
10407 case 'S': USE_BITS (FS); break;
10408 case 'T': USE_BITS (FT); break;
10409 case 'V': USE_BITS (FS); break;
10410 case 'a': USE_BITS (TARGET); break;
10411 case 'b': USE_BITS (RS); break;
10412 case 'c': USE_BITS (CODE); break;
10413 case 'd': USE_BITS (RD); break;
10414 case 'h': USE_BITS (PREFX); break;
10415 case 'i': USE_BITS (IMMEDIATE); break;
10416 case 'j': USE_BITS (DELTA); break;
10417 case 'k': USE_BITS (CACHE); break;
10418 case 'n': USE_BITS (RT); break;
10419 case 'o': USE_BITS (DELTA); break;
10420 case 'p': USE_BITS (DELTA); break;
10421 case 'q': USE_BITS (CODE2); break;
10422 case 'r': USE_BITS (RS); break;
10423 case 's': USE_BITS (RS); break;
10424 case 't': USE_BITS (RT); break;
10425 case 'u': USE_BITS (IMMEDIATE); break;
10426 case 'v': USE_BITS (RS); break;
10427 case 'w': USE_BITS (RT); break;
10428 case 'y': USE_BITS (RS3); break;
10429 case 'z': break;
10430 case '|': USE_BITS (TRAP); break;
10431 case '~': USE_BITS (OFFSET12); break;
10432 default:
10433 as_bad (_("Internal error: bad microMIPS opcode "
10434 "(unknown operand type `%c'): %s %s"),
10435 c, opc->name, opc->args);
10436 return 0;
10437 }
10438#undef USE_BITS
10439 if (used_bits != insn_bits)
10440 {
10441 if (~used_bits & insn_bits)
10442 as_bad (_("Internal error: bad microMIPS opcode "
10443 "(bits 0x%lx undefined): %s %s"),
10444 ~used_bits & insn_bits, opc->name, opc->args);
10445 if (used_bits & ~insn_bits)
10446 as_bad (_("Internal error: bad microMIPS opcode "
10447 "(bits 0x%lx defined): %s %s"),
10448 used_bits & ~insn_bits, opc->name, opc->args);
10449 return 0;
10450 }
10451 return 1;
10452}
10453
9bcd4f99
TS
10454/* UDI immediates. */
10455struct mips_immed {
10456 char type;
10457 unsigned int shift;
10458 unsigned long mask;
10459 const char * desc;
10460};
10461
10462static const struct mips_immed mips_immed[] = {
10463 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
10464 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
10465 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
10466 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
10467 { 0,0,0,0 }
10468};
10469
7455baf8
TS
10470/* Check whether an odd floating-point register is allowed. */
10471static int
10472mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
10473{
10474 const char *s = insn->name;
10475
10476 if (insn->pinfo == INSN_MACRO)
10477 /* Let a macro pass, we'll catch it later when it is expanded. */
10478 return 1;
10479
10480 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
10481 {
10482 /* Allow odd registers for single-precision ops. */
10483 switch (insn->pinfo & (FP_S | FP_D))
10484 {
10485 case FP_S:
10486 case 0:
10487 return 1; /* both single precision - ok */
10488 case FP_D:
10489 return 0; /* both double precision - fail */
10490 default:
10491 break;
10492 }
10493
10494 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10495 s = strchr (insn->name, '.');
10496 if (argnum == 2)
10497 s = s != NULL ? strchr (s + 1, '.') : NULL;
10498 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
10499 }
10500
10501 /* Single-precision coprocessor loads and moves are OK too. */
10502 if ((insn->pinfo & FP_S)
10503 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
10504 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
10505 return 1;
10506
10507 return 0;
10508}
10509
df58fc94
RS
10510/* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10511 taking bits from BIT up. */
10512static int
10513expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
10514{
10515 return (ep->X_op == O_constant
10516 && (ep->X_add_number & ((1 << bit) - 1)) == 0
10517 && ep->X_add_number >= min << bit
10518 && ep->X_add_number < max << bit);
10519}
10520
252b5132
RH
10521/* This routine assembles an instruction into its binary format. As a
10522 side effect, it sets one of the global variables imm_reloc or
10523 offset_reloc to the type of relocation to do if one of the operands
10524 is an address expression. */
10525
10526static void
17a2f251 10527mips_ip (char *str, struct mips_cl_insn *ip)
252b5132 10528{
df58fc94
RS
10529 bfd_boolean wrong_delay_slot_insns = FALSE;
10530 bfd_boolean need_delay_slot_ok = TRUE;
10531 struct mips_opcode *firstinsn = NULL;
10532 const struct mips_opcode *past;
10533 struct hash_control *hash;
252b5132
RH
10534 char *s;
10535 const char *args;
43841e91 10536 char c = 0;
252b5132
RH
10537 struct mips_opcode *insn;
10538 char *argsStart;
10539 unsigned int regno;
34224acf 10540 unsigned int lastregno;
df58fc94 10541 unsigned int destregno = 0;
af7ee8bf 10542 unsigned int lastpos = 0;
071742cf 10543 unsigned int limlo, limhi;
252b5132 10544 char *s_reset;
74cd071d 10545 offsetT min_range, max_range;
df58fc94 10546 long opend;
a40bc9dd 10547 char *name;
707bfff6
TS
10548 int argnum;
10549 unsigned int rtype;
df58fc94 10550 char *dot;
a40bc9dd 10551 long end;
252b5132
RH
10552
10553 insn_error = NULL;
10554
df58fc94
RS
10555 if (mips_opts.micromips)
10556 {
10557 hash = micromips_op_hash;
10558 past = &micromips_opcodes[bfd_micromips_num_opcodes];
10559 }
10560 else
10561 {
10562 hash = op_hash;
10563 past = &mips_opcodes[NUMOPCODES];
10564 }
10565 forced_insn_length = 0;
252b5132 10566 insn = NULL;
252b5132 10567
df58fc94 10568 /* We first try to match an instruction up to a space or to the end. */
a40bc9dd
RS
10569 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
10570 continue;
bdaaa2e1 10571
a40bc9dd
RS
10572 /* Make a copy of the instruction so that we can fiddle with it. */
10573 name = alloca (end + 1);
10574 memcpy (name, str, end);
10575 name[end] = '\0';
252b5132 10576
df58fc94
RS
10577 for (;;)
10578 {
10579 insn = (struct mips_opcode *) hash_find (hash, name);
10580
10581 if (insn != NULL || !mips_opts.micromips)
10582 break;
10583 if (forced_insn_length)
10584 break;
10585
10586 /* See if there's an instruction size override suffix,
10587 either `16' or `32', at the end of the mnemonic proper,
10588 that defines the operation, i.e. before the first `.'
10589 character if any. Strip it and retry. */
10590 dot = strchr (name, '.');
10591 opend = dot != NULL ? dot - name : end;
10592 if (opend < 3)
10593 break;
10594 if (name[opend - 2] == '1' && name[opend - 1] == '6')
10595 forced_insn_length = 2;
10596 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
10597 forced_insn_length = 4;
10598 else
10599 break;
10600 memcpy (name + opend - 2, name + opend, end - opend + 1);
10601 }
252b5132
RH
10602 if (insn == NULL)
10603 {
a40bc9dd
RS
10604 insn_error = _("Unrecognized opcode");
10605 return;
252b5132
RH
10606 }
10607
df58fc94
RS
10608 /* For microMIPS instructions placed in a fixed-length branch delay slot
10609 we make up to two passes over the relevant fragment of the opcode
10610 table. First we try instructions that meet the delay slot's length
10611 requirement. If none matched, then we retry with the remaining ones
10612 and if one matches, then we use it and then issue an appropriate
10613 warning later on. */
a40bc9dd 10614 argsStart = s = str + end;
252b5132
RH
10615 for (;;)
10616 {
df58fc94
RS
10617 bfd_boolean delay_slot_ok;
10618 bfd_boolean size_ok;
b34976b6 10619 bfd_boolean ok;
252b5132 10620
a40bc9dd 10621 gas_assert (strcmp (insn->name, name) == 0);
252b5132 10622
f79e2745 10623 ok = is_opcode_valid (insn);
df58fc94
RS
10624 size_ok = is_size_valid (insn);
10625 delay_slot_ok = is_delay_slot_valid (insn);
10626 if (!delay_slot_ok && !wrong_delay_slot_insns)
252b5132 10627 {
df58fc94
RS
10628 firstinsn = insn;
10629 wrong_delay_slot_insns = TRUE;
10630 }
10631 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
10632 {
10633 static char buf[256];
10634
10635 if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
252b5132
RH
10636 {
10637 ++insn;
10638 continue;
10639 }
df58fc94 10640 if (wrong_delay_slot_insns && need_delay_slot_ok)
beae10d5 10641 {
df58fc94
RS
10642 gas_assert (firstinsn);
10643 need_delay_slot_ok = FALSE;
10644 past = insn + 1;
10645 insn = firstinsn;
10646 continue;
252b5132 10647 }
df58fc94
RS
10648
10649 if (insn_error)
10650 return;
10651
10652 if (!ok)
10653 sprintf (buf, _("opcode not supported on this processor: %s (%s)"),
10654 mips_cpu_info_from_arch (mips_opts.arch)->name,
10655 mips_cpu_info_from_isa (mips_opts.isa)->name);
10656 else
10657 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
10658 8 * forced_insn_length);
10659 insn_error = buf;
10660
10661 return;
252b5132
RH
10662 }
10663
1e915849 10664 create_insn (ip, insn);
268f6bed 10665 insn_error = NULL;
707bfff6 10666 argnum = 1;
24864476 10667 lastregno = 0xffffffff;
252b5132
RH
10668 for (args = insn->args;; ++args)
10669 {
deec1734
CD
10670 int is_mdmx;
10671
ad8d3bb3 10672 s += strspn (s, " \t");
deec1734 10673 is_mdmx = 0;
252b5132
RH
10674 switch (*args)
10675 {
10676 case '\0': /* end of args */
10677 if (*s == '\0')
10678 return;
10679 break;
10680
90ecf173 10681 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
df58fc94 10682 gas_assert (!mips_opts.micromips);
8b082fb1
TS
10683 my_getExpression (&imm_expr, s);
10684 check_absolute_expr (ip, &imm_expr);
10685 if ((unsigned long) imm_expr.X_add_number != 1
10686 && (unsigned long) imm_expr.X_add_number != 3)
10687 {
10688 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
10689 (unsigned long) imm_expr.X_add_number);
10690 }
df58fc94 10691 INSERT_OPERAND (0, BP, *ip, imm_expr.X_add_number);
8b082fb1
TS
10692 imm_expr.X_op = O_absent;
10693 s = expr_end;
10694 continue;
10695
90ecf173 10696 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
df58fc94 10697 gas_assert (!mips_opts.micromips);
74cd071d
CF
10698 my_getExpression (&imm_expr, s);
10699 check_absolute_expr (ip, &imm_expr);
10700 if (imm_expr.X_add_number & ~OP_MASK_SA3)
10701 {
a9e24354
TS
10702 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10703 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
74cd071d 10704 }
df58fc94 10705 INSERT_OPERAND (0, SA3, *ip, imm_expr.X_add_number);
74cd071d
CF
10706 imm_expr.X_op = O_absent;
10707 s = expr_end;
10708 continue;
10709
90ecf173 10710 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
df58fc94 10711 gas_assert (!mips_opts.micromips);
74cd071d
CF
10712 my_getExpression (&imm_expr, s);
10713 check_absolute_expr (ip, &imm_expr);
10714 if (imm_expr.X_add_number & ~OP_MASK_SA4)
10715 {
a9e24354
TS
10716 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10717 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
74cd071d 10718 }
df58fc94 10719 INSERT_OPERAND (0, SA4, *ip, imm_expr.X_add_number);
74cd071d
CF
10720 imm_expr.X_op = O_absent;
10721 s = expr_end;
10722 continue;
10723
90ecf173 10724 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
df58fc94 10725 gas_assert (!mips_opts.micromips);
74cd071d
CF
10726 my_getExpression (&imm_expr, s);
10727 check_absolute_expr (ip, &imm_expr);
10728 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
10729 {
a9e24354
TS
10730 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10731 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
74cd071d 10732 }
df58fc94 10733 INSERT_OPERAND (0, IMM8, *ip, imm_expr.X_add_number);
74cd071d
CF
10734 imm_expr.X_op = O_absent;
10735 s = expr_end;
10736 continue;
10737
90ecf173 10738 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
df58fc94 10739 gas_assert (!mips_opts.micromips);
74cd071d
CF
10740 my_getExpression (&imm_expr, s);
10741 check_absolute_expr (ip, &imm_expr);
10742 if (imm_expr.X_add_number & ~OP_MASK_RS)
10743 {
a9e24354
TS
10744 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10745 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
74cd071d 10746 }
df58fc94 10747 INSERT_OPERAND (0, RS, *ip, imm_expr.X_add_number);
74cd071d
CF
10748 imm_expr.X_op = O_absent;
10749 s = expr_end;
10750 continue;
10751
90ecf173 10752 case '7': /* Four DSP accumulators in bits 11,12. */
df58fc94 10753 gas_assert (!mips_opts.micromips);
74cd071d
CF
10754 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10755 s[3] >= '0' && s[3] <= '3')
10756 {
10757 regno = s[3] - '0';
10758 s += 4;
df58fc94 10759 INSERT_OPERAND (0, DSPACC, *ip, regno);
74cd071d
CF
10760 continue;
10761 }
10762 else
10763 as_bad (_("Invalid dsp acc register"));
10764 break;
10765
90ecf173 10766 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
df58fc94 10767 gas_assert (!mips_opts.micromips);
74cd071d
CF
10768 my_getExpression (&imm_expr, s);
10769 check_absolute_expr (ip, &imm_expr);
10770 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
10771 {
a9e24354
TS
10772 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10773 OP_MASK_WRDSP,
10774 (unsigned long) imm_expr.X_add_number);
74cd071d 10775 }
df58fc94 10776 INSERT_OPERAND (0, WRDSP, *ip, imm_expr.X_add_number);
74cd071d
CF
10777 imm_expr.X_op = O_absent;
10778 s = expr_end;
10779 continue;
10780
90ecf173 10781 case '9': /* Four DSP accumulators in bits 21,22. */
df58fc94 10782 gas_assert (!mips_opts.micromips);
74cd071d
CF
10783 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10784 s[3] >= '0' && s[3] <= '3')
10785 {
10786 regno = s[3] - '0';
10787 s += 4;
df58fc94 10788 INSERT_OPERAND (0, DSPACC_S, *ip, regno);
74cd071d
CF
10789 continue;
10790 }
10791 else
10792 as_bad (_("Invalid dsp acc register"));
10793 break;
10794
90ecf173 10795 case '0': /* DSP 6-bit signed immediate in bit 20. */
df58fc94 10796 gas_assert (!mips_opts.micromips);
74cd071d
CF
10797 my_getExpression (&imm_expr, s);
10798 check_absolute_expr (ip, &imm_expr);
10799 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
10800 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
10801 if (imm_expr.X_add_number < min_range ||
10802 imm_expr.X_add_number > max_range)
10803 {
a9e24354
TS
10804 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10805 (long) min_range, (long) max_range,
10806 (long) imm_expr.X_add_number);
74cd071d 10807 }
df58fc94 10808 INSERT_OPERAND (0, DSPSFT, *ip, imm_expr.X_add_number);
74cd071d
CF
10809 imm_expr.X_op = O_absent;
10810 s = expr_end;
10811 continue;
10812
90ecf173 10813 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
df58fc94 10814 gas_assert (!mips_opts.micromips);
74cd071d
CF
10815 my_getExpression (&imm_expr, s);
10816 check_absolute_expr (ip, &imm_expr);
10817 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
10818 {
a9e24354
TS
10819 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10820 OP_MASK_RDDSP,
10821 (unsigned long) imm_expr.X_add_number);
74cd071d 10822 }
df58fc94 10823 INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
74cd071d
CF
10824 imm_expr.X_op = O_absent;
10825 s = expr_end;
10826 continue;
10827
90ecf173 10828 case ':': /* DSP 7-bit signed immediate in bit 19. */
df58fc94 10829 gas_assert (!mips_opts.micromips);
74cd071d
CF
10830 my_getExpression (&imm_expr, s);
10831 check_absolute_expr (ip, &imm_expr);
10832 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
10833 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
10834 if (imm_expr.X_add_number < min_range ||
10835 imm_expr.X_add_number > max_range)
10836 {
a9e24354
TS
10837 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10838 (long) min_range, (long) max_range,
10839 (long) imm_expr.X_add_number);
74cd071d 10840 }
df58fc94 10841 INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
74cd071d
CF
10842 imm_expr.X_op = O_absent;
10843 s = expr_end;
10844 continue;
10845
90ecf173 10846 case '@': /* DSP 10-bit signed immediate in bit 16. */
df58fc94 10847 gas_assert (!mips_opts.micromips);
74cd071d
CF
10848 my_getExpression (&imm_expr, s);
10849 check_absolute_expr (ip, &imm_expr);
10850 min_range = -((OP_MASK_IMM10 + 1) >> 1);
10851 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
10852 if (imm_expr.X_add_number < min_range ||
10853 imm_expr.X_add_number > max_range)
10854 {
a9e24354
TS
10855 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10856 (long) min_range, (long) max_range,
10857 (long) imm_expr.X_add_number);
74cd071d 10858 }
df58fc94 10859 INSERT_OPERAND (0, IMM10, *ip, imm_expr.X_add_number);
74cd071d
CF
10860 imm_expr.X_op = O_absent;
10861 s = expr_end;
10862 continue;
10863
a9e24354 10864 case '!': /* MT usermode flag bit. */
df58fc94 10865 gas_assert (!mips_opts.micromips);
ef2e4d86
CF
10866 my_getExpression (&imm_expr, s);
10867 check_absolute_expr (ip, &imm_expr);
10868 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
a9e24354
TS
10869 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
10870 (unsigned long) imm_expr.X_add_number);
df58fc94 10871 INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
ef2e4d86
CF
10872 imm_expr.X_op = O_absent;
10873 s = expr_end;
10874 continue;
10875
a9e24354 10876 case '$': /* MT load high flag bit. */
df58fc94 10877 gas_assert (!mips_opts.micromips);
ef2e4d86
CF
10878 my_getExpression (&imm_expr, s);
10879 check_absolute_expr (ip, &imm_expr);
10880 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
a9e24354
TS
10881 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
10882 (unsigned long) imm_expr.X_add_number);
df58fc94 10883 INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
ef2e4d86
CF
10884 imm_expr.X_op = O_absent;
10885 s = expr_end;
10886 continue;
10887
90ecf173 10888 case '*': /* Four DSP accumulators in bits 18,19. */
df58fc94 10889 gas_assert (!mips_opts.micromips);
ef2e4d86
CF
10890 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10891 s[3] >= '0' && s[3] <= '3')
10892 {
10893 regno = s[3] - '0';
10894 s += 4;
df58fc94 10895 INSERT_OPERAND (0, MTACC_T, *ip, regno);
ef2e4d86
CF
10896 continue;
10897 }
10898 else
10899 as_bad (_("Invalid dsp/smartmips acc register"));
10900 break;
10901
90ecf173 10902 case '&': /* Four DSP accumulators in bits 13,14. */
df58fc94 10903 gas_assert (!mips_opts.micromips);
ef2e4d86
CF
10904 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10905 s[3] >= '0' && s[3] <= '3')
10906 {
10907 regno = s[3] - '0';
10908 s += 4;
df58fc94 10909 INSERT_OPERAND (0, MTACC_D, *ip, regno);
ef2e4d86
CF
10910 continue;
10911 }
10912 else
10913 as_bad (_("Invalid dsp/smartmips acc register"));
10914 break;
10915
252b5132 10916 case ',':
a339155f 10917 ++argnum;
252b5132
RH
10918 if (*s++ == *args)
10919 continue;
10920 s--;
10921 switch (*++args)
10922 {
10923 case 'r':
10924 case 'v':
df58fc94 10925 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
252b5132
RH
10926 continue;
10927
10928 case 'w':
df58fc94 10929 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
38487616
TS
10930 continue;
10931
252b5132 10932 case 'W':
df58fc94
RS
10933 gas_assert (!mips_opts.micromips);
10934 INSERT_OPERAND (0, FT, *ip, lastregno);
252b5132
RH
10935 continue;
10936
10937 case 'V':
df58fc94 10938 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
252b5132
RH
10939 continue;
10940 }
10941 break;
10942
10943 case '(':
10944 /* Handle optional base register.
10945 Either the base register is omitted or
bdaaa2e1 10946 we must have a left paren. */
252b5132
RH
10947 /* This is dependent on the next operand specifier
10948 is a base register specification. */
df58fc94
RS
10949 gas_assert (args[1] == 'b'
10950 || (mips_opts.micromips
10951 && args[1] == 'm'
10952 && (args[2] == 'l' || args[2] == 'n'
10953 || args[2] == 's' || args[2] == 'a')));
10954 if (*s == '\0' && args[1] == 'b')
252b5132 10955 return;
df58fc94 10956 /* Fall through. */
252b5132 10957
90ecf173 10958 case ')': /* These must match exactly. */
df58fc94
RS
10959 if (*s++ == *args)
10960 continue;
10961 break;
10962
10963 case '[': /* These must match exactly. */
60b63b72 10964 case ']':
df58fc94 10965 gas_assert (!mips_opts.micromips);
252b5132
RH
10966 if (*s++ == *args)
10967 continue;
10968 break;
10969
af7ee8bf
CD
10970 case '+': /* Opcode extension character. */
10971 switch (*++args)
10972 {
9bcd4f99
TS
10973 case '1': /* UDI immediates. */
10974 case '2':
10975 case '3':
10976 case '4':
df58fc94 10977 gas_assert (!mips_opts.micromips);
9bcd4f99
TS
10978 {
10979 const struct mips_immed *imm = mips_immed;
10980
10981 while (imm->type && imm->type != *args)
10982 ++imm;
10983 if (! imm->type)
10984 internalError ();
10985 my_getExpression (&imm_expr, s);
10986 check_absolute_expr (ip, &imm_expr);
10987 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
10988 {
10989 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
10990 imm->desc ? imm->desc : ip->insn_mo->name,
10991 (unsigned long) imm_expr.X_add_number,
10992 (unsigned long) imm_expr.X_add_number);
90ecf173 10993 imm_expr.X_add_number &= imm->mask;
9bcd4f99
TS
10994 }
10995 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
10996 << imm->shift);
10997 imm_expr.X_op = O_absent;
10998 s = expr_end;
10999 }
11000 continue;
90ecf173 11001
071742cf
CD
11002 case 'A': /* ins/ext position, becomes LSB. */
11003 limlo = 0;
11004 limhi = 31;
5f74bc13
CD
11005 goto do_lsb;
11006 case 'E':
11007 limlo = 32;
11008 limhi = 63;
11009 goto do_lsb;
90ecf173 11010 do_lsb:
071742cf
CD
11011 my_getExpression (&imm_expr, s);
11012 check_absolute_expr (ip, &imm_expr);
11013 if ((unsigned long) imm_expr.X_add_number < limlo
11014 || (unsigned long) imm_expr.X_add_number > limhi)
11015 {
11016 as_bad (_("Improper position (%lu)"),
11017 (unsigned long) imm_expr.X_add_number);
11018 imm_expr.X_add_number = limlo;
11019 }
11020 lastpos = imm_expr.X_add_number;
df58fc94
RS
11021 INSERT_OPERAND (mips_opts.micromips,
11022 EXTLSB, *ip, imm_expr.X_add_number);
071742cf
CD
11023 imm_expr.X_op = O_absent;
11024 s = expr_end;
11025 continue;
11026
11027 case 'B': /* ins size, becomes MSB. */
11028 limlo = 1;
11029 limhi = 32;
5f74bc13
CD
11030 goto do_msb;
11031 case 'F':
11032 limlo = 33;
11033 limhi = 64;
11034 goto do_msb;
90ecf173 11035 do_msb:
071742cf
CD
11036 my_getExpression (&imm_expr, s);
11037 check_absolute_expr (ip, &imm_expr);
11038 /* Check for negative input so that small negative numbers
11039 will not succeed incorrectly. The checks against
11040 (pos+size) transitively check "size" itself,
11041 assuming that "pos" is reasonable. */
11042 if ((long) imm_expr.X_add_number < 0
11043 || ((unsigned long) imm_expr.X_add_number
11044 + lastpos) < limlo
11045 || ((unsigned long) imm_expr.X_add_number
11046 + lastpos) > limhi)
11047 {
11048 as_bad (_("Improper insert size (%lu, position %lu)"),
11049 (unsigned long) imm_expr.X_add_number,
11050 (unsigned long) lastpos);
11051 imm_expr.X_add_number = limlo - lastpos;
11052 }
df58fc94
RS
11053 INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
11054 lastpos + imm_expr.X_add_number - 1);
071742cf
CD
11055 imm_expr.X_op = O_absent;
11056 s = expr_end;
11057 continue;
11058
11059 case 'C': /* ext size, becomes MSBD. */
11060 limlo = 1;
11061 limhi = 32;
5f74bc13
CD
11062 goto do_msbd;
11063 case 'G':
11064 limlo = 33;
11065 limhi = 64;
11066 goto do_msbd;
11067 case 'H':
11068 limlo = 33;
11069 limhi = 64;
11070 goto do_msbd;
90ecf173 11071 do_msbd:
071742cf
CD
11072 my_getExpression (&imm_expr, s);
11073 check_absolute_expr (ip, &imm_expr);
11074 /* Check for negative input so that small negative numbers
11075 will not succeed incorrectly. The checks against
11076 (pos+size) transitively check "size" itself,
11077 assuming that "pos" is reasonable. */
11078 if ((long) imm_expr.X_add_number < 0
11079 || ((unsigned long) imm_expr.X_add_number
11080 + lastpos) < limlo
11081 || ((unsigned long) imm_expr.X_add_number
11082 + lastpos) > limhi)
11083 {
11084 as_bad (_("Improper extract size (%lu, position %lu)"),
11085 (unsigned long) imm_expr.X_add_number,
11086 (unsigned long) lastpos);
11087 imm_expr.X_add_number = limlo - lastpos;
11088 }
df58fc94
RS
11089 INSERT_OPERAND (mips_opts.micromips,
11090 EXTMSBD, *ip, imm_expr.X_add_number - 1);
071742cf
CD
11091 imm_expr.X_op = O_absent;
11092 s = expr_end;
11093 continue;
af7ee8bf 11094
bbcc0807
CD
11095 case 'D':
11096 /* +D is for disassembly only; never match. */
11097 break;
11098
5f74bc13
CD
11099 case 'I':
11100 /* "+I" is like "I", except that imm2_expr is used. */
11101 my_getExpression (&imm2_expr, s);
11102 if (imm2_expr.X_op != O_big
11103 && imm2_expr.X_op != O_constant)
11104 insn_error = _("absolute expression required");
9ee2a2d4
MR
11105 if (HAVE_32BIT_GPRS)
11106 normalize_constant_expr (&imm2_expr);
5f74bc13
CD
11107 s = expr_end;
11108 continue;
11109
707bfff6 11110 case 'T': /* Coprocessor register. */
df58fc94 11111 gas_assert (!mips_opts.micromips);
ef2e4d86
CF
11112 /* +T is for disassembly only; never match. */
11113 break;
11114
707bfff6 11115 case 't': /* Coprocessor register number. */
df58fc94 11116 gas_assert (!mips_opts.micromips);
ef2e4d86
CF
11117 if (s[0] == '$' && ISDIGIT (s[1]))
11118 {
11119 ++s;
11120 regno = 0;
11121 do
11122 {
11123 regno *= 10;
11124 regno += *s - '0';
11125 ++s;
11126 }
11127 while (ISDIGIT (*s));
11128 if (regno > 31)
11129 as_bad (_("Invalid register number (%d)"), regno);
11130 else
11131 {
df58fc94 11132 INSERT_OPERAND (0, RT, *ip, regno);
ef2e4d86
CF
11133 continue;
11134 }
11135 }
11136 else
11137 as_bad (_("Invalid coprocessor 0 register number"));
11138 break;
11139
bb35fb24
NC
11140 case 'x':
11141 /* bbit[01] and bbit[01]32 bit index. Give error if index
11142 is not in the valid range. */
df58fc94 11143 gas_assert (!mips_opts.micromips);
bb35fb24
NC
11144 my_getExpression (&imm_expr, s);
11145 check_absolute_expr (ip, &imm_expr);
11146 if ((unsigned) imm_expr.X_add_number > 31)
11147 {
11148 as_bad (_("Improper bit index (%lu)"),
11149 (unsigned long) imm_expr.X_add_number);
11150 imm_expr.X_add_number = 0;
11151 }
df58fc94 11152 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
bb35fb24
NC
11153 imm_expr.X_op = O_absent;
11154 s = expr_end;
11155 continue;
11156
11157 case 'X':
11158 /* bbit[01] bit index when bbit is used but we generate
11159 bbit[01]32 because the index is over 32. Move to the
11160 next candidate if index is not in the valid range. */
df58fc94 11161 gas_assert (!mips_opts.micromips);
bb35fb24
NC
11162 my_getExpression (&imm_expr, s);
11163 check_absolute_expr (ip, &imm_expr);
11164 if ((unsigned) imm_expr.X_add_number < 32
11165 || (unsigned) imm_expr.X_add_number > 63)
11166 break;
df58fc94 11167 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
bb35fb24
NC
11168 imm_expr.X_op = O_absent;
11169 s = expr_end;
11170 continue;
11171
11172 case 'p':
11173 /* cins, cins32, exts and exts32 position field. Give error
11174 if it's not in the valid range. */
df58fc94 11175 gas_assert (!mips_opts.micromips);
bb35fb24
NC
11176 my_getExpression (&imm_expr, s);
11177 check_absolute_expr (ip, &imm_expr);
11178 if ((unsigned) imm_expr.X_add_number > 31)
11179 {
11180 as_bad (_("Improper position (%lu)"),
11181 (unsigned long) imm_expr.X_add_number);
11182 imm_expr.X_add_number = 0;
11183 }
11184 /* Make the pos explicit to simplify +S. */
11185 lastpos = imm_expr.X_add_number + 32;
df58fc94 11186 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
bb35fb24
NC
11187 imm_expr.X_op = O_absent;
11188 s = expr_end;
11189 continue;
11190
11191 case 'P':
11192 /* cins, cins32, exts and exts32 position field. Move to
11193 the next candidate if it's not in the valid range. */
df58fc94 11194 gas_assert (!mips_opts.micromips);
bb35fb24
NC
11195 my_getExpression (&imm_expr, s);
11196 check_absolute_expr (ip, &imm_expr);
11197 if ((unsigned) imm_expr.X_add_number < 32
11198 || (unsigned) imm_expr.X_add_number > 63)
11199 break;
11200 lastpos = imm_expr.X_add_number;
df58fc94 11201 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
bb35fb24
NC
11202 imm_expr.X_op = O_absent;
11203 s = expr_end;
11204 continue;
11205
11206 case 's':
11207 /* cins and exts length-minus-one field. */
df58fc94 11208 gas_assert (!mips_opts.micromips);
bb35fb24
NC
11209 my_getExpression (&imm_expr, s);
11210 check_absolute_expr (ip, &imm_expr);
11211 if ((unsigned long) imm_expr.X_add_number > 31)
11212 {
11213 as_bad (_("Improper size (%lu)"),
11214 (unsigned long) imm_expr.X_add_number);
11215 imm_expr.X_add_number = 0;
11216 }
df58fc94 11217 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
bb35fb24
NC
11218 imm_expr.X_op = O_absent;
11219 s = expr_end;
11220 continue;
11221
11222 case 'S':
11223 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11224 length-minus-one field. */
df58fc94 11225 gas_assert (!mips_opts.micromips);
bb35fb24
NC
11226 my_getExpression (&imm_expr, s);
11227 check_absolute_expr (ip, &imm_expr);
11228 if ((long) imm_expr.X_add_number < 0
11229 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
11230 {
11231 as_bad (_("Improper size (%lu)"),
11232 (unsigned long) imm_expr.X_add_number);
11233 imm_expr.X_add_number = 0;
11234 }
df58fc94 11235 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
bb35fb24
NC
11236 imm_expr.X_op = O_absent;
11237 s = expr_end;
11238 continue;
11239
dd3cbb7e
NC
11240 case 'Q':
11241 /* seqi/snei immediate field. */
df58fc94 11242 gas_assert (!mips_opts.micromips);
dd3cbb7e
NC
11243 my_getExpression (&imm_expr, s);
11244 check_absolute_expr (ip, &imm_expr);
11245 if ((long) imm_expr.X_add_number < -512
11246 || (long) imm_expr.X_add_number >= 512)
11247 {
11248 as_bad (_("Improper immediate (%ld)"),
11249 (long) imm_expr.X_add_number);
11250 imm_expr.X_add_number = 0;
11251 }
df58fc94 11252 INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
dd3cbb7e
NC
11253 imm_expr.X_op = O_absent;
11254 s = expr_end;
11255 continue;
11256
98675402 11257 case 'a': /* 8-bit signed offset in bit 6 */
df58fc94 11258 gas_assert (!mips_opts.micromips);
98675402
RS
11259 my_getExpression (&imm_expr, s);
11260 check_absolute_expr (ip, &imm_expr);
11261 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
11262 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
11263 if (imm_expr.X_add_number < min_range
11264 || imm_expr.X_add_number > max_range)
11265 {
c95354ed 11266 as_bad (_("Offset not in range %ld..%ld (%ld)"),
98675402
RS
11267 (long) min_range, (long) max_range,
11268 (long) imm_expr.X_add_number);
11269 }
df58fc94 11270 INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
98675402
RS
11271 imm_expr.X_op = O_absent;
11272 s = expr_end;
11273 continue;
11274
11275 case 'b': /* 8-bit signed offset in bit 3 */
df58fc94 11276 gas_assert (!mips_opts.micromips);
98675402
RS
11277 my_getExpression (&imm_expr, s);
11278 check_absolute_expr (ip, &imm_expr);
11279 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
11280 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
11281 if (imm_expr.X_add_number < min_range
11282 || imm_expr.X_add_number > max_range)
11283 {
c95354ed 11284 as_bad (_("Offset not in range %ld..%ld (%ld)"),
98675402
RS
11285 (long) min_range, (long) max_range,
11286 (long) imm_expr.X_add_number);
11287 }
df58fc94 11288 INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
98675402
RS
11289 imm_expr.X_op = O_absent;
11290 s = expr_end;
11291 continue;
11292
11293 case 'c': /* 9-bit signed offset in bit 6 */
df58fc94 11294 gas_assert (!mips_opts.micromips);
98675402
RS
11295 my_getExpression (&imm_expr, s);
11296 check_absolute_expr (ip, &imm_expr);
11297 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
11298 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
c95354ed
MX
11299 /* We check the offset range before adjusted. */
11300 min_range <<= 4;
11301 max_range <<= 4;
98675402
RS
11302 if (imm_expr.X_add_number < min_range
11303 || imm_expr.X_add_number > max_range)
11304 {
c95354ed 11305 as_bad (_("Offset not in range %ld..%ld (%ld)"),
98675402
RS
11306 (long) min_range, (long) max_range,
11307 (long) imm_expr.X_add_number);
11308 }
c95354ed
MX
11309 if (imm_expr.X_add_number & 0xf)
11310 {
11311 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11312 (long) imm_expr.X_add_number);
11313 }
11314 /* Right shift 4 bits to adjust the offset operand. */
df58fc94
RS
11315 INSERT_OPERAND (0, OFFSET_C, *ip,
11316 imm_expr.X_add_number >> 4);
98675402
RS
11317 imm_expr.X_op = O_absent;
11318 s = expr_end;
11319 continue;
11320
11321 case 'z':
df58fc94 11322 gas_assert (!mips_opts.micromips);
98675402
RS
11323 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno))
11324 break;
11325 if (regno == AT && mips_opts.at)
11326 {
11327 if (mips_opts.at == ATREG)
11328 as_warn (_("used $at without \".set noat\""));
11329 else
11330 as_warn (_("used $%u with \".set at=$%u\""),
11331 regno, mips_opts.at);
11332 }
df58fc94 11333 INSERT_OPERAND (0, RZ, *ip, regno);
98675402
RS
11334 continue;
11335
11336 case 'Z':
df58fc94 11337 gas_assert (!mips_opts.micromips);
98675402
RS
11338 if (!reg_lookup (&s, RTYPE_FPU, &regno))
11339 break;
df58fc94 11340 INSERT_OPERAND (0, FZ, *ip, regno);
98675402
RS
11341 continue;
11342
af7ee8bf 11343 default:
df58fc94 11344 as_bad (_("Internal error: bad %s opcode "
90ecf173 11345 "(unknown extension operand type `+%c'): %s %s"),
df58fc94 11346 mips_opts.micromips ? "microMIPS" : "MIPS",
90ecf173 11347 *args, insn->name, insn->args);
af7ee8bf
CD
11348 /* Further processing is fruitless. */
11349 return;
11350 }
11351 break;
11352
df58fc94
RS
11353 case '.': /* 10-bit offset. */
11354 case '~': /* 12-bit offset. */
11355 gas_assert (mips_opts.micromips);
11356 {
11357 int shift = *args == '.' ? 9 : 11;
11358 size_t i;
11359
11360 /* Check whether there is only a single bracketed expression
11361 left. If so, it must be the base register and the
11362 constant must be zero. */
11363 if (*s == '(' && strchr (s + 1, '(') == 0)
11364 continue;
11365
11366 /* If this value won't fit into the offset, then go find
11367 a macro that will generate a 16- or 32-bit offset code
11368 pattern. */
11369 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
11370 if ((i == 0 && (imm_expr.X_op != O_constant
11371 || imm_expr.X_add_number >= 1 << shift
11372 || imm_expr.X_add_number < -1 << shift))
11373 || i > 0)
11374 {
11375 imm_expr.X_op = O_absent;
11376 break;
11377 }
11378 if (shift == 9)
11379 INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
11380 else
11381 INSERT_OPERAND (1, OFFSET12, *ip, imm_expr.X_add_number);
11382 imm_expr.X_op = O_absent;
11383 s = expr_end;
11384 }
11385 continue;
11386
252b5132
RH
11387 case '<': /* must be at least one digit */
11388 /*
11389 * According to the manual, if the shift amount is greater
b6ff326e
KH
11390 * than 31 or less than 0, then the shift amount should be
11391 * mod 32. In reality the mips assembler issues an error.
252b5132
RH
11392 * We issue a warning and mask out all but the low 5 bits.
11393 */
11394 my_getExpression (&imm_expr, s);
11395 check_absolute_expr (ip, &imm_expr);
11396 if ((unsigned long) imm_expr.X_add_number > 31)
bf12938e
RS
11397 as_warn (_("Improper shift amount (%lu)"),
11398 (unsigned long) imm_expr.X_add_number);
df58fc94
RS
11399 INSERT_OPERAND (mips_opts.micromips,
11400 SHAMT, *ip, imm_expr.X_add_number);
252b5132
RH
11401 imm_expr.X_op = O_absent;
11402 s = expr_end;
11403 continue;
11404
11405 case '>': /* shift amount minus 32 */
11406 my_getExpression (&imm_expr, s);
11407 check_absolute_expr (ip, &imm_expr);
11408 if ((unsigned long) imm_expr.X_add_number < 32
11409 || (unsigned long) imm_expr.X_add_number > 63)
11410 break;
df58fc94
RS
11411 INSERT_OPERAND (mips_opts.micromips,
11412 SHAMT, *ip, imm_expr.X_add_number - 32);
252b5132
RH
11413 imm_expr.X_op = O_absent;
11414 s = expr_end;
11415 continue;
11416
90ecf173
MR
11417 case 'k': /* CACHE code. */
11418 case 'h': /* PREFX code. */
11419 case '1': /* SYNC type. */
252b5132
RH
11420 my_getExpression (&imm_expr, s);
11421 check_absolute_expr (ip, &imm_expr);
11422 if ((unsigned long) imm_expr.X_add_number > 31)
bf12938e
RS
11423 as_warn (_("Invalid value for `%s' (%lu)"),
11424 ip->insn_mo->name,
11425 (unsigned long) imm_expr.X_add_number);
df58fc94 11426 switch (*args)
d954098f 11427 {
df58fc94
RS
11428 case 'k':
11429 if (mips_fix_cn63xxp1
11430 && !mips_opts.micromips
11431 && strcmp ("pref", insn->name) == 0)
d954098f
DD
11432 switch (imm_expr.X_add_number)
11433 {
11434 case 5:
11435 case 25:
11436 case 26:
11437 case 27:
11438 case 28:
11439 case 29:
11440 case 30:
11441 case 31: /* These are ok. */
11442 break;
11443
11444 default: /* The rest must be changed to 28. */
11445 imm_expr.X_add_number = 28;
11446 break;
11447 }
df58fc94
RS
11448 INSERT_OPERAND (mips_opts.micromips,
11449 CACHE, *ip, imm_expr.X_add_number);
11450 break;
11451 case 'h':
11452 INSERT_OPERAND (mips_opts.micromips,
11453 PREFX, *ip, imm_expr.X_add_number);
11454 break;
11455 case '1':
11456 INSERT_OPERAND (mips_opts.micromips,
11457 STYPE, *ip, imm_expr.X_add_number);
11458 break;
d954098f 11459 }
252b5132
RH
11460 imm_expr.X_op = O_absent;
11461 s = expr_end;
11462 continue;
11463
90ecf173 11464 case 'c': /* BREAK code. */
df58fc94
RS
11465 {
11466 unsigned long mask = (mips_opts.micromips
11467 ? MICROMIPSOP_MASK_CODE
11468 : OP_MASK_CODE);
11469
11470 my_getExpression (&imm_expr, s);
11471 check_absolute_expr (ip, &imm_expr);
11472 if ((unsigned long) imm_expr.X_add_number > mask)
11473 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11474 ip->insn_mo->name,
11475 mask, (unsigned long) imm_expr.X_add_number);
11476 INSERT_OPERAND (mips_opts.micromips,
11477 CODE, *ip, imm_expr.X_add_number);
11478 imm_expr.X_op = O_absent;
11479 s = expr_end;
11480 }
252b5132
RH
11481 continue;
11482
90ecf173 11483 case 'q': /* Lower BREAK code. */
df58fc94
RS
11484 {
11485 unsigned long mask = (mips_opts.micromips
11486 ? MICROMIPSOP_MASK_CODE2
11487 : OP_MASK_CODE2);
11488
11489 my_getExpression (&imm_expr, s);
11490 check_absolute_expr (ip, &imm_expr);
11491 if ((unsigned long) imm_expr.X_add_number > mask)
11492 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11493 ip->insn_mo->name,
11494 mask, (unsigned long) imm_expr.X_add_number);
11495 INSERT_OPERAND (mips_opts.micromips,
11496 CODE2, *ip, imm_expr.X_add_number);
11497 imm_expr.X_op = O_absent;
11498 s = expr_end;
11499 }
252b5132
RH
11500 continue;
11501
df58fc94
RS
11502 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11503 {
11504 unsigned long mask = (mips_opts.micromips
11505 ? MICROMIPSOP_MASK_CODE10
11506 : OP_MASK_CODE20);
11507
11508 my_getExpression (&imm_expr, s);
11509 check_absolute_expr (ip, &imm_expr);
11510 if ((unsigned long) imm_expr.X_add_number > mask)
11511 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11512 ip->insn_mo->name,
11513 mask, (unsigned long) imm_expr.X_add_number);
11514 if (mips_opts.micromips)
11515 INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
11516 else
11517 INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
11518 imm_expr.X_op = O_absent;
11519 s = expr_end;
11520 }
252b5132
RH
11521 continue;
11522
df58fc94
RS
11523 case 'C': /* 25- or 23-bit coprocessor code. */
11524 {
11525 unsigned long mask = (mips_opts.micromips
11526 ? MICROMIPSOP_MASK_COPZ
11527 : OP_MASK_COPZ);
11528
11529 my_getExpression (&imm_expr, s);
11530 check_absolute_expr (ip, &imm_expr);
11531 if ((unsigned long) imm_expr.X_add_number > mask)
11532 as_warn (_("Coproccesor code > %u bits (%lu)"),
11533 mips_opts.micromips ? 23U : 25U,
793b27f4 11534 (unsigned long) imm_expr.X_add_number);
df58fc94
RS
11535 INSERT_OPERAND (mips_opts.micromips,
11536 COPZ, *ip, imm_expr.X_add_number);
11537 imm_expr.X_op = O_absent;
11538 s = expr_end;
11539 }
beae10d5 11540 continue;
252b5132 11541
df58fc94
RS
11542 case 'J': /* 19-bit WAIT code. */
11543 gas_assert (!mips_opts.micromips);
4372b673
NC
11544 my_getExpression (&imm_expr, s);
11545 check_absolute_expr (ip, &imm_expr);
793b27f4 11546 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
df58fc94
RS
11547 {
11548 as_warn (_("Illegal 19-bit code (%lu)"),
a9e24354 11549 (unsigned long) imm_expr.X_add_number);
df58fc94
RS
11550 imm_expr.X_add_number &= OP_MASK_CODE19;
11551 }
11552 INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
4372b673
NC
11553 imm_expr.X_op = O_absent;
11554 s = expr_end;
11555 continue;
11556
707bfff6 11557 case 'P': /* Performance register. */
df58fc94 11558 gas_assert (!mips_opts.micromips);
beae10d5 11559 my_getExpression (&imm_expr, s);
252b5132 11560 check_absolute_expr (ip, &imm_expr);
beae10d5 11561 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
bf12938e
RS
11562 as_warn (_("Invalid performance register (%lu)"),
11563 (unsigned long) imm_expr.X_add_number);
df58fc94 11564 INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
beae10d5
KH
11565 imm_expr.X_op = O_absent;
11566 s = expr_end;
11567 continue;
252b5132 11568
707bfff6 11569 case 'G': /* Coprocessor destination register. */
df58fc94
RS
11570 {
11571 unsigned long opcode = ip->insn_opcode;
11572 unsigned long mask;
11573 unsigned int types;
11574 int cop0;
11575
11576 if (mips_opts.micromips)
11577 {
11578 mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
11579 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
11580 | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
11581 opcode &= mask;
11582 switch (opcode)
11583 {
11584 case 0x000000fc: /* mfc0 */
11585 case 0x000002fc: /* mtc0 */
11586 case 0x580000fc: /* dmfc0 */
11587 case 0x580002fc: /* dmtc0 */
11588 cop0 = 1;
11589 break;
11590 default:
11591 cop0 = 0;
11592 break;
11593 }
11594 }
11595 else
11596 {
11597 opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
11598 cop0 = opcode == OP_OP_COP0;
11599 }
11600 types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
11601 ok = reg_lookup (&s, types, &regno);
11602 if (mips_opts.micromips)
11603 INSERT_OPERAND (1, RS, *ip, regno);
11604 else
11605 INSERT_OPERAND (0, RD, *ip, regno);
11606 if (ok)
11607 {
11608 lastregno = regno;
11609 continue;
11610 }
11611 }
11612 break;
707bfff6 11613
df58fc94
RS
11614 case 'y': /* ALNV.PS source register. */
11615 gas_assert (mips_opts.micromips);
11616 goto do_reg;
11617 case 'x': /* Ignore register name. */
11618 case 'U': /* Destination register (CLO/CLZ). */
11619 case 'g': /* Coprocessor destination register. */
11620 gas_assert (!mips_opts.micromips);
90ecf173
MR
11621 case 'b': /* Base register. */
11622 case 'd': /* Destination register. */
11623 case 's': /* Source register. */
11624 case 't': /* Target register. */
11625 case 'r': /* Both target and source. */
11626 case 'v': /* Both dest and source. */
11627 case 'w': /* Both dest and target. */
11628 case 'E': /* Coprocessor target register. */
11629 case 'K': /* RDHWR destination register. */
90ecf173 11630 case 'z': /* Must be zero register. */
df58fc94 11631 do_reg:
90ecf173 11632 s_reset = s;
707bfff6
TS
11633 if (*args == 'E' || *args == 'K')
11634 ok = reg_lookup (&s, RTYPE_NUM, &regno);
11635 else
11636 {
11637 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno);
741fe287
MR
11638 if (regno == AT && mips_opts.at)
11639 {
11640 if (mips_opts.at == ATREG)
f71d0d44 11641 as_warn (_("Used $at without \".set noat\""));
741fe287 11642 else
f71d0d44 11643 as_warn (_("Used $%u with \".set at=$%u\""),
741fe287
MR
11644 regno, mips_opts.at);
11645 }
707bfff6
TS
11646 }
11647 if (ok)
252b5132 11648 {
252b5132
RH
11649 c = *args;
11650 if (*s == ' ')
f9419b05 11651 ++s;
252b5132
RH
11652 if (args[1] != *s)
11653 {
11654 if (c == 'r' || c == 'v' || c == 'w')
11655 {
11656 regno = lastregno;
11657 s = s_reset;
f9419b05 11658 ++args;
252b5132
RH
11659 }
11660 }
11661 /* 'z' only matches $0. */
11662 if (c == 'z' && regno != 0)
11663 break;
11664
24864476 11665 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
e7c604dd
CM
11666 {
11667 if (regno == lastregno)
90ecf173
MR
11668 {
11669 insn_error
f71d0d44 11670 = _("Source and destination must be different");
e7c604dd 11671 continue;
90ecf173 11672 }
24864476 11673 if (regno == 31 && lastregno == 0xffffffff)
90ecf173
MR
11674 {
11675 insn_error
f71d0d44 11676 = _("A destination register must be supplied");
e7c604dd 11677 continue;
90ecf173 11678 }
e7c604dd 11679 }
90ecf173
MR
11680 /* Now that we have assembled one operand, we use the args
11681 string to figure out where it goes in the instruction. */
252b5132
RH
11682 switch (c)
11683 {
11684 case 'r':
11685 case 's':
11686 case 'v':
11687 case 'b':
df58fc94 11688 INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
252b5132 11689 break;
df58fc94 11690
af7ee8bf 11691 case 'K':
df58fc94
RS
11692 if (mips_opts.micromips)
11693 INSERT_OPERAND (1, RS, *ip, regno);
11694 else
11695 INSERT_OPERAND (0, RD, *ip, regno);
11696 break;
11697
11698 case 'd':
ef2e4d86 11699 case 'g':
df58fc94 11700 INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
252b5132 11701 break;
df58fc94 11702
4372b673 11703 case 'U':
df58fc94
RS
11704 gas_assert (!mips_opts.micromips);
11705 INSERT_OPERAND (0, RD, *ip, regno);
11706 INSERT_OPERAND (0, RT, *ip, regno);
4372b673 11707 break;
df58fc94 11708
252b5132
RH
11709 case 'w':
11710 case 't':
11711 case 'E':
df58fc94
RS
11712 INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
11713 break;
11714
11715 case 'y':
11716 gas_assert (mips_opts.micromips);
11717 INSERT_OPERAND (1, RS3, *ip, regno);
252b5132 11718 break;
df58fc94 11719
252b5132
RH
11720 case 'x':
11721 /* This case exists because on the r3000 trunc
11722 expands into a macro which requires a gp
11723 register. On the r6000 or r4000 it is
11724 assembled into a single instruction which
11725 ignores the register. Thus the insn version
11726 is MIPS_ISA2 and uses 'x', and the macro
11727 version is MIPS_ISA1 and uses 't'. */
11728 break;
df58fc94 11729
252b5132
RH
11730 case 'z':
11731 /* This case is for the div instruction, which
11732 acts differently if the destination argument
11733 is $0. This only matches $0, and is checked
11734 outside the switch. */
11735 break;
252b5132
RH
11736 }
11737 lastregno = regno;
11738 continue;
11739 }
252b5132
RH
11740 switch (*args++)
11741 {
11742 case 'r':
11743 case 'v':
df58fc94 11744 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
252b5132 11745 continue;
df58fc94 11746
252b5132 11747 case 'w':
df58fc94 11748 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
252b5132
RH
11749 continue;
11750 }
11751 break;
11752
deec1734 11753 case 'O': /* MDMX alignment immediate constant. */
df58fc94 11754 gas_assert (!mips_opts.micromips);
deec1734
CD
11755 my_getExpression (&imm_expr, s);
11756 check_absolute_expr (ip, &imm_expr);
11757 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
20203fb9 11758 as_warn (_("Improper align amount (%ld), using low bits"),
bf12938e 11759 (long) imm_expr.X_add_number);
df58fc94 11760 INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
deec1734
CD
11761 imm_expr.X_op = O_absent;
11762 s = expr_end;
11763 continue;
11764
11765 case 'Q': /* MDMX vector, element sel, or const. */
11766 if (s[0] != '$')
11767 {
11768 /* MDMX Immediate. */
df58fc94 11769 gas_assert (!mips_opts.micromips);
deec1734
CD
11770 my_getExpression (&imm_expr, s);
11771 check_absolute_expr (ip, &imm_expr);
11772 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
bf12938e
RS
11773 as_warn (_("Invalid MDMX Immediate (%ld)"),
11774 (long) imm_expr.X_add_number);
df58fc94 11775 INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
deec1734
CD
11776 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
11777 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
11778 else
11779 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
deec1734
CD
11780 imm_expr.X_op = O_absent;
11781 s = expr_end;
11782 continue;
11783 }
11784 /* Not MDMX Immediate. Fall through. */
11785 case 'X': /* MDMX destination register. */
11786 case 'Y': /* MDMX source register. */
11787 case 'Z': /* MDMX target register. */
11788 is_mdmx = 1;
df58fc94
RS
11789 case 'W':
11790 gas_assert (!mips_opts.micromips);
90ecf173
MR
11791 case 'D': /* Floating point destination register. */
11792 case 'S': /* Floating point source register. */
11793 case 'T': /* Floating point target register. */
11794 case 'R': /* Floating point source register. */
252b5132 11795 case 'V':
707bfff6
TS
11796 rtype = RTYPE_FPU;
11797 if (is_mdmx
11798 || (mips_opts.ase_mdmx
11799 && (ip->insn_mo->pinfo & FP_D)
11800 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
11801 | INSN_COPROC_MEMORY_DELAY
11802 | INSN_LOAD_COPROC_DELAY
11803 | INSN_LOAD_MEMORY_DELAY
11804 | INSN_STORE_MEMORY))))
11805 rtype |= RTYPE_VEC;
252b5132 11806 s_reset = s;
707bfff6 11807 if (reg_lookup (&s, rtype, &regno))
252b5132 11808 {
252b5132 11809 if ((regno & 1) != 0
ca4e0257 11810 && HAVE_32BIT_FPRS
90ecf173 11811 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
252b5132
RH
11812 as_warn (_("Float register should be even, was %d"),
11813 regno);
11814
11815 c = *args;
11816 if (*s == ' ')
f9419b05 11817 ++s;
252b5132
RH
11818 if (args[1] != *s)
11819 {
11820 if (c == 'V' || c == 'W')
11821 {
11822 regno = lastregno;
11823 s = s_reset;
f9419b05 11824 ++args;
252b5132
RH
11825 }
11826 }
11827 switch (c)
11828 {
11829 case 'D':
deec1734 11830 case 'X':
df58fc94 11831 INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
252b5132 11832 break;
df58fc94 11833
252b5132
RH
11834 case 'V':
11835 case 'S':
deec1734 11836 case 'Y':
df58fc94 11837 INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
252b5132 11838 break;
df58fc94 11839
deec1734
CD
11840 case 'Q':
11841 /* This is like 'Z', but also needs to fix the MDMX
11842 vector/scalar select bits. Note that the
11843 scalar immediate case is handled above. */
11844 if (*s == '[')
11845 {
11846 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
11847 int max_el = (is_qh ? 3 : 7);
11848 s++;
11849 my_getExpression(&imm_expr, s);
11850 check_absolute_expr (ip, &imm_expr);
11851 s = expr_end;
11852 if (imm_expr.X_add_number > max_el)
20203fb9
NC
11853 as_bad (_("Bad element selector %ld"),
11854 (long) imm_expr.X_add_number);
deec1734
CD
11855 imm_expr.X_add_number &= max_el;
11856 ip->insn_opcode |= (imm_expr.X_add_number
11857 << (OP_SH_VSEL +
11858 (is_qh ? 2 : 1)));
01a3f561 11859 imm_expr.X_op = O_absent;
deec1734 11860 if (*s != ']')
20203fb9 11861 as_warn (_("Expecting ']' found '%s'"), s);
deec1734
CD
11862 else
11863 s++;
11864 }
11865 else
11866 {
11867 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
11868 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
11869 << OP_SH_VSEL);
11870 else
11871 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
11872 OP_SH_VSEL);
11873 }
90ecf173 11874 /* Fall through. */
252b5132
RH
11875 case 'W':
11876 case 'T':
deec1734 11877 case 'Z':
df58fc94 11878 INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
252b5132 11879 break;
df58fc94 11880
252b5132 11881 case 'R':
df58fc94 11882 INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
252b5132
RH
11883 break;
11884 }
11885 lastregno = regno;
11886 continue;
11887 }
11888
252b5132
RH
11889 switch (*args++)
11890 {
11891 case 'V':
df58fc94 11892 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
252b5132 11893 continue;
df58fc94 11894
252b5132 11895 case 'W':
df58fc94 11896 INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
252b5132
RH
11897 continue;
11898 }
11899 break;
11900
11901 case 'I':
11902 my_getExpression (&imm_expr, s);
11903 if (imm_expr.X_op != O_big
11904 && imm_expr.X_op != O_constant)
11905 insn_error = _("absolute expression required");
9ee2a2d4
MR
11906 if (HAVE_32BIT_GPRS)
11907 normalize_constant_expr (&imm_expr);
252b5132
RH
11908 s = expr_end;
11909 continue;
11910
11911 case 'A':
11912 my_getExpression (&offset_expr, s);
2051e8c4 11913 normalize_address_expr (&offset_expr);
f6688943 11914 *imm_reloc = BFD_RELOC_32;
252b5132
RH
11915 s = expr_end;
11916 continue;
11917
11918 case 'F':
11919 case 'L':
11920 case 'f':
11921 case 'l':
11922 {
11923 int f64;
ca4e0257 11924 int using_gprs;
252b5132
RH
11925 char *save_in;
11926 char *err;
11927 unsigned char temp[8];
11928 int len;
11929 unsigned int length;
11930 segT seg;
11931 subsegT subseg;
11932 char *p;
11933
11934 /* These only appear as the last operand in an
11935 instruction, and every instruction that accepts
11936 them in any variant accepts them in all variants.
11937 This means we don't have to worry about backing out
11938 any changes if the instruction does not match.
11939
11940 The difference between them is the size of the
11941 floating point constant and where it goes. For 'F'
11942 and 'L' the constant is 64 bits; for 'f' and 'l' it
11943 is 32 bits. Where the constant is placed is based
11944 on how the MIPS assembler does things:
11945 F -- .rdata
11946 L -- .lit8
11947 f -- immediate value
11948 l -- .lit4
11949
11950 The .lit4 and .lit8 sections are only used if
11951 permitted by the -G argument.
11952
ca4e0257
RS
11953 The code below needs to know whether the target register
11954 is 32 or 64 bits wide. It relies on the fact 'f' and
11955 'F' are used with GPR-based instructions and 'l' and
11956 'L' are used with FPR-based instructions. */
252b5132
RH
11957
11958 f64 = *args == 'F' || *args == 'L';
ca4e0257 11959 using_gprs = *args == 'F' || *args == 'f';
252b5132
RH
11960
11961 save_in = input_line_pointer;
11962 input_line_pointer = s;
11963 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
11964 length = len;
11965 s = input_line_pointer;
11966 input_line_pointer = save_in;
11967 if (err != NULL && *err != '\0')
11968 {
11969 as_bad (_("Bad floating point constant: %s"), err);
11970 memset (temp, '\0', sizeof temp);
11971 length = f64 ? 8 : 4;
11972 }
11973
9c2799c2 11974 gas_assert (length == (unsigned) (f64 ? 8 : 4));
252b5132
RH
11975
11976 if (*args == 'f'
11977 || (*args == 'l'
3e722fb5 11978 && (g_switch_value < 4
252b5132
RH
11979 || (temp[0] == 0 && temp[1] == 0)
11980 || (temp[2] == 0 && temp[3] == 0))))
11981 {
11982 imm_expr.X_op = O_constant;
90ecf173 11983 if (!target_big_endian)
252b5132
RH
11984 imm_expr.X_add_number = bfd_getl32 (temp);
11985 else
11986 imm_expr.X_add_number = bfd_getb32 (temp);
11987 }
11988 else if (length > 4
90ecf173 11989 && !mips_disable_float_construction
ca4e0257
RS
11990 /* Constants can only be constructed in GPRs and
11991 copied to FPRs if the GPRs are at least as wide
11992 as the FPRs. Force the constant into memory if
11993 we are using 64-bit FPRs but the GPRs are only
11994 32 bits wide. */
11995 && (using_gprs
90ecf173 11996 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
252b5132
RH
11997 && ((temp[0] == 0 && temp[1] == 0)
11998 || (temp[2] == 0 && temp[3] == 0))
11999 && ((temp[4] == 0 && temp[5] == 0)
12000 || (temp[6] == 0 && temp[7] == 0)))
12001 {
ca4e0257 12002 /* The value is simple enough to load with a couple of
90ecf173
MR
12003 instructions. If using 32-bit registers, set
12004 imm_expr to the high order 32 bits and offset_expr to
12005 the low order 32 bits. Otherwise, set imm_expr to
12006 the entire 64 bit constant. */
ca4e0257 12007 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
252b5132
RH
12008 {
12009 imm_expr.X_op = O_constant;
12010 offset_expr.X_op = O_constant;
90ecf173 12011 if (!target_big_endian)
252b5132
RH
12012 {
12013 imm_expr.X_add_number = bfd_getl32 (temp + 4);
12014 offset_expr.X_add_number = bfd_getl32 (temp);
12015 }
12016 else
12017 {
12018 imm_expr.X_add_number = bfd_getb32 (temp);
12019 offset_expr.X_add_number = bfd_getb32 (temp + 4);
12020 }
12021 if (offset_expr.X_add_number == 0)
12022 offset_expr.X_op = O_absent;
12023 }
12024 else if (sizeof (imm_expr.X_add_number) > 4)
12025 {
12026 imm_expr.X_op = O_constant;
90ecf173 12027 if (!target_big_endian)
252b5132
RH
12028 imm_expr.X_add_number = bfd_getl64 (temp);
12029 else
12030 imm_expr.X_add_number = bfd_getb64 (temp);
12031 }
12032 else
12033 {
12034 imm_expr.X_op = O_big;
12035 imm_expr.X_add_number = 4;
90ecf173 12036 if (!target_big_endian)
252b5132
RH
12037 {
12038 generic_bignum[0] = bfd_getl16 (temp);
12039 generic_bignum[1] = bfd_getl16 (temp + 2);
12040 generic_bignum[2] = bfd_getl16 (temp + 4);
12041 generic_bignum[3] = bfd_getl16 (temp + 6);
12042 }
12043 else
12044 {
12045 generic_bignum[0] = bfd_getb16 (temp + 6);
12046 generic_bignum[1] = bfd_getb16 (temp + 4);
12047 generic_bignum[2] = bfd_getb16 (temp + 2);
12048 generic_bignum[3] = bfd_getb16 (temp);
12049 }
12050 }
12051 }
12052 else
12053 {
12054 const char *newname;
12055 segT new_seg;
12056
12057 /* Switch to the right section. */
12058 seg = now_seg;
12059 subseg = now_subseg;
12060 switch (*args)
12061 {
12062 default: /* unused default case avoids warnings. */
12063 case 'L':
12064 newname = RDATA_SECTION_NAME;
3e722fb5 12065 if (g_switch_value >= 8)
252b5132
RH
12066 newname = ".lit8";
12067 break;
12068 case 'F':
3e722fb5 12069 newname = RDATA_SECTION_NAME;
252b5132
RH
12070 break;
12071 case 'l':
9c2799c2 12072 gas_assert (g_switch_value >= 4);
252b5132
RH
12073 newname = ".lit4";
12074 break;
12075 }
12076 new_seg = subseg_new (newname, (subsegT) 0);
f43abd2b 12077 if (IS_ELF)
252b5132
RH
12078 bfd_set_section_flags (stdoutput, new_seg,
12079 (SEC_ALLOC
12080 | SEC_LOAD
12081 | SEC_READONLY
12082 | SEC_DATA));
12083 frag_align (*args == 'l' ? 2 : 3, 0, 0);
c41e87e3 12084 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
252b5132
RH
12085 record_alignment (new_seg, 4);
12086 else
12087 record_alignment (new_seg, *args == 'l' ? 2 : 3);
12088 if (seg == now_seg)
12089 as_bad (_("Can't use floating point insn in this section"));
12090
df58fc94
RS
12091 /* Set the argument to the current address in the
12092 section. */
12093 offset_expr.X_op = O_symbol;
12094 offset_expr.X_add_symbol = symbol_temp_new_now ();
12095 offset_expr.X_add_number = 0;
12096
12097 /* Put the floating point number into the section. */
12098 p = frag_more ((int) length);
12099 memcpy (p, temp, length);
12100
12101 /* Switch back to the original section. */
12102 subseg_set (seg, subseg);
12103 }
12104 }
12105 continue;
12106
12107 case 'i': /* 16-bit unsigned immediate. */
12108 case 'j': /* 16-bit signed immediate. */
12109 *imm_reloc = BFD_RELOC_LO16;
12110 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
12111 {
12112 int more;
12113 offsetT minval, maxval;
12114
12115 more = (insn + 1 < past
12116 && strcmp (insn->name, insn[1].name) == 0);
12117
12118 /* If the expression was written as an unsigned number,
12119 only treat it as signed if there are no more
12120 alternatives. */
12121 if (more
12122 && *args == 'j'
12123 && sizeof (imm_expr.X_add_number) <= 4
12124 && imm_expr.X_op == O_constant
12125 && imm_expr.X_add_number < 0
12126 && imm_expr.X_unsigned
12127 && HAVE_64BIT_GPRS)
12128 break;
12129
12130 /* For compatibility with older assemblers, we accept
12131 0x8000-0xffff as signed 16-bit numbers when only
12132 signed numbers are allowed. */
12133 if (*args == 'i')
12134 minval = 0, maxval = 0xffff;
12135 else if (more)
12136 minval = -0x8000, maxval = 0x7fff;
12137 else
12138 minval = -0x8000, maxval = 0xffff;
12139
12140 if (imm_expr.X_op != O_constant
12141 || imm_expr.X_add_number < minval
12142 || imm_expr.X_add_number > maxval)
12143 {
12144 if (more)
12145 break;
12146 if (imm_expr.X_op == O_constant
12147 || imm_expr.X_op == O_big)
12148 as_bad (_("Expression out of range"));
12149 }
12150 }
12151 s = expr_end;
12152 continue;
12153
12154 case 'o': /* 16-bit offset. */
12155 offset_reloc[0] = BFD_RELOC_LO16;
12156 offset_reloc[1] = BFD_RELOC_UNUSED;
12157 offset_reloc[2] = BFD_RELOC_UNUSED;
12158
12159 /* Check whether there is only a single bracketed expression
12160 left. If so, it must be the base register and the
12161 constant must be zero. */
12162 if (*s == '(' && strchr (s + 1, '(') == 0)
12163 {
12164 offset_expr.X_op = O_constant;
12165 offset_expr.X_add_number = 0;
12166 continue;
12167 }
12168
12169 /* If this value won't fit into a 16 bit offset, then go
12170 find a macro that will generate the 32 bit offset
12171 code pattern. */
12172 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12173 && (offset_expr.X_op != O_constant
12174 || offset_expr.X_add_number >= 0x8000
12175 || offset_expr.X_add_number < -0x8000))
12176 break;
12177
12178 s = expr_end;
12179 continue;
12180
12181 case 'p': /* PC-relative offset. */
12182 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12183 my_getExpression (&offset_expr, s);
12184 s = expr_end;
12185 continue;
12186
12187 case 'u': /* Upper 16 bits. */
12188 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
12189 && imm_expr.X_op == O_constant
12190 && (imm_expr.X_add_number < 0
12191 || imm_expr.X_add_number >= 0x10000))
12192 as_bad (_("lui expression (%lu) not in range 0..65535"),
12193 (unsigned long) imm_expr.X_add_number);
12194 s = expr_end;
12195 continue;
12196
12197 case 'a': /* 26-bit address. */
12198 *offset_reloc = BFD_RELOC_MIPS_JMP;
12199 my_getExpression (&offset_expr, s);
12200 s = expr_end;
12201 continue;
12202
12203 case 'N': /* 3-bit branch condition code. */
12204 case 'M': /* 3-bit compare condition code. */
12205 rtype = RTYPE_CCC;
12206 if (ip->insn_mo->pinfo & (FP_D | FP_S))
12207 rtype |= RTYPE_FCC;
12208 if (!reg_lookup (&s, rtype, &regno))
12209 break;
12210 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
12211 || strcmp (str + strlen (str) - 5, "any2f") == 0
12212 || strcmp (str + strlen (str) - 5, "any2t") == 0)
12213 && (regno & 1) != 0)
12214 as_warn (_("Condition code register should be even for %s, "
12215 "was %d"),
12216 str, regno);
12217 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
12218 || strcmp (str + strlen (str) - 5, "any4t") == 0)
12219 && (regno & 3) != 0)
12220 as_warn (_("Condition code register should be 0 or 4 for %s, "
12221 "was %d"),
12222 str, regno);
12223 if (*args == 'N')
12224 INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
12225 else
12226 INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
12227 continue;
12228
12229 case 'H':
12230 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
12231 s += 2;
12232 if (ISDIGIT (*s))
12233 {
12234 c = 0;
12235 do
12236 {
12237 c *= 10;
12238 c += *s - '0';
12239 ++s;
12240 }
12241 while (ISDIGIT (*s));
12242 }
12243 else
12244 c = 8; /* Invalid sel value. */
12245
12246 if (c > 7)
12247 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12248 INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
12249 continue;
12250
12251 case 'e':
12252 gas_assert (!mips_opts.micromips);
12253 /* Must be at least one digit. */
12254 my_getExpression (&imm_expr, s);
12255 check_absolute_expr (ip, &imm_expr);
12256
12257 if ((unsigned long) imm_expr.X_add_number
12258 > (unsigned long) OP_MASK_VECBYTE)
12259 {
12260 as_bad (_("bad byte vector index (%ld)"),
12261 (long) imm_expr.X_add_number);
12262 imm_expr.X_add_number = 0;
12263 }
12264
12265 INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
12266 imm_expr.X_op = O_absent;
12267 s = expr_end;
12268 continue;
12269
12270 case '%':
12271 gas_assert (!mips_opts.micromips);
12272 my_getExpression (&imm_expr, s);
12273 check_absolute_expr (ip, &imm_expr);
12274
12275 if ((unsigned long) imm_expr.X_add_number
12276 > (unsigned long) OP_MASK_VECALIGN)
12277 {
12278 as_bad (_("bad byte vector index (%ld)"),
12279 (long) imm_expr.X_add_number);
12280 imm_expr.X_add_number = 0;
12281 }
12282
12283 INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
12284 imm_expr.X_op = O_absent;
12285 s = expr_end;
12286 continue;
12287
12288 case 'm': /* Opcode extension character. */
12289 gas_assert (mips_opts.micromips);
12290 c = *++args;
12291 switch (c)
12292 {
12293 case 'r':
12294 if (strncmp (s, "$pc", 3) == 0)
12295 {
12296 s += 3;
12297 continue;
12298 }
12299 break;
12300
12301 case 'a':
12302 case 'b':
12303 case 'c':
12304 case 'd':
12305 case 'e':
12306 case 'f':
12307 case 'g':
12308 case 'h':
12309 case 'i':
12310 case 'j':
12311 case 'l':
12312 case 'm':
12313 case 'n':
12314 case 'p':
12315 case 'q':
12316 case 's':
12317 case 't':
12318 case 'x':
12319 case 'y':
12320 case 'z':
12321 s_reset = s;
12322 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno);
12323 if (regno == AT && mips_opts.at)
12324 {
12325 if (mips_opts.at == ATREG)
12326 as_warn (_("Used $at without \".set noat\""));
12327 else
12328 as_warn (_("Used $%u with \".set at=$%u\""),
12329 regno, mips_opts.at);
12330 }
12331 if (!ok)
12332 {
12333 if (c == 'c')
12334 {
12335 gas_assert (args[1] == ',');
12336 regno = lastregno;
12337 ++args;
12338 }
12339 else if (c == 't')
12340 {
12341 gas_assert (args[1] == ',');
12342 ++args;
12343 continue; /* Nothing to do. */
12344 }
12345 else
12346 break;
12347 }
12348
12349 if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
12350 {
12351 if (regno == lastregno)
12352 {
12353 insn_error
12354 = _("Source and destination must be different");
12355 continue;
12356 }
12357 if (regno == 31 && lastregno == 0xffffffff)
12358 {
12359 insn_error
12360 = _("A destination register must be supplied");
12361 continue;
12362 }
12363 }
12364
12365 if (*s == ' ')
12366 ++s;
12367 if (args[1] != *s)
12368 {
12369 if (c == 'e')
12370 {
12371 gas_assert (args[1] == ',');
12372 regno = lastregno;
12373 s = s_reset;
12374 ++args;
12375 }
12376 else if (c == 't')
12377 {
12378 gas_assert (args[1] == ',');
12379 s = s_reset;
12380 ++args;
12381 continue; /* Nothing to do. */
12382 }
12383 }
12384
12385 /* Make sure regno is the same as lastregno. */
12386 if (c == 't' && regno != lastregno)
12387 break;
12388
12389 /* Make sure regno is the same as destregno. */
12390 if (c == 'x' && regno != destregno)
12391 break;
12392
12393 /* We need to save regno, before regno maps to the
12394 microMIPS register encoding. */
12395 lastregno = regno;
12396
12397 if (c == 'f')
12398 destregno = regno;
12399
12400 switch (c)
12401 {
12402 case 'a':
12403 if (regno != GP)
12404 regno = ILLEGAL_REG;
12405 break;
12406
12407 case 'b':
12408 regno = mips32_to_micromips_reg_b_map[regno];
12409 break;
12410
12411 case 'c':
12412 regno = mips32_to_micromips_reg_c_map[regno];
12413 break;
12414
12415 case 'd':
12416 regno = mips32_to_micromips_reg_d_map[regno];
12417 break;
12418
12419 case 'e':
12420 regno = mips32_to_micromips_reg_e_map[regno];
12421 break;
12422
12423 case 'f':
12424 regno = mips32_to_micromips_reg_f_map[regno];
12425 break;
12426
12427 case 'g':
12428 regno = mips32_to_micromips_reg_g_map[regno];
12429 break;
12430
12431 case 'h':
12432 regno = mips32_to_micromips_reg_h_map[regno];
12433 break;
12434
12435 case 'i':
12436 switch (EXTRACT_OPERAND (1, MI, *ip))
12437 {
12438 case 4:
12439 if (regno == 21)
12440 regno = 3;
12441 else if (regno == 22)
12442 regno = 4;
12443 else if (regno == 5)
12444 regno = 5;
12445 else if (regno == 6)
12446 regno = 6;
12447 else if (regno == 7)
12448 regno = 7;
12449 else
12450 regno = ILLEGAL_REG;
12451 break;
12452
12453 case 5:
12454 if (regno == 6)
12455 regno = 0;
12456 else if (regno == 7)
12457 regno = 1;
12458 else
12459 regno = ILLEGAL_REG;
12460 break;
12461
12462 case 6:
12463 if (regno == 7)
12464 regno = 2;
12465 else
12466 regno = ILLEGAL_REG;
12467 break;
12468
12469 default:
12470 regno = ILLEGAL_REG;
12471 break;
12472 }
12473 break;
12474
12475 case 'l':
12476 regno = mips32_to_micromips_reg_l_map[regno];
12477 break;
12478
12479 case 'm':
12480 regno = mips32_to_micromips_reg_m_map[regno];
12481 break;
12482
12483 case 'n':
12484 regno = mips32_to_micromips_reg_n_map[regno];
12485 break;
12486
12487 case 'q':
12488 regno = mips32_to_micromips_reg_q_map[regno];
12489 break;
12490
12491 case 's':
12492 if (regno != SP)
12493 regno = ILLEGAL_REG;
12494 break;
12495
12496 case 'y':
12497 if (regno != 31)
12498 regno = ILLEGAL_REG;
12499 break;
12500
12501 case 'z':
12502 if (regno != ZERO)
12503 regno = ILLEGAL_REG;
12504 break;
12505
12506 case 'j': /* Do nothing. */
12507 case 'p':
12508 case 't':
12509 case 'x':
12510 break;
12511
12512 default:
12513 internalError ();
12514 }
12515
12516 if (regno == ILLEGAL_REG)
12517 break;
12518
12519 switch (c)
12520 {
12521 case 'b':
12522 INSERT_OPERAND (1, MB, *ip, regno);
12523 break;
12524
12525 case 'c':
12526 INSERT_OPERAND (1, MC, *ip, regno);
12527 break;
12528
12529 case 'd':
12530 INSERT_OPERAND (1, MD, *ip, regno);
12531 break;
12532
12533 case 'e':
12534 INSERT_OPERAND (1, ME, *ip, regno);
12535 break;
12536
12537 case 'f':
12538 INSERT_OPERAND (1, MF, *ip, regno);
12539 break;
12540
12541 case 'g':
12542 INSERT_OPERAND (1, MG, *ip, regno);
12543 break;
12544
12545 case 'h':
12546 INSERT_OPERAND (1, MH, *ip, regno);
12547 break;
12548
12549 case 'i':
12550 INSERT_OPERAND (1, MI, *ip, regno);
12551 break;
12552
12553 case 'j':
12554 INSERT_OPERAND (1, MJ, *ip, regno);
12555 break;
12556
12557 case 'l':
12558 INSERT_OPERAND (1, ML, *ip, regno);
12559 break;
12560
12561 case 'm':
12562 INSERT_OPERAND (1, MM, *ip, regno);
12563 break;
12564
12565 case 'n':
12566 INSERT_OPERAND (1, MN, *ip, regno);
12567 break;
12568
12569 case 'p':
12570 INSERT_OPERAND (1, MP, *ip, regno);
12571 break;
12572
12573 case 'q':
12574 INSERT_OPERAND (1, MQ, *ip, regno);
12575 break;
12576
12577 case 'a': /* Do nothing. */
12578 case 's': /* Do nothing. */
12579 case 't': /* Do nothing. */
12580 case 'x': /* Do nothing. */
12581 case 'y': /* Do nothing. */
12582 case 'z': /* Do nothing. */
12583 break;
12584
12585 default:
12586 internalError ();
12587 }
12588 continue;
12589
12590 case 'A':
12591 {
12592 bfd_reloc_code_real_type r[3];
12593 expressionS ep;
12594 int imm;
12595
12596 /* Check whether there is only a single bracketed
12597 expression left. If so, it must be the base register
12598 and the constant must be zero. */
12599 if (*s == '(' && strchr (s + 1, '(') == 0)
12600 {
12601 INSERT_OPERAND (1, IMMA, *ip, 0);
12602 continue;
12603 }
12604
12605 if (my_getSmallExpression (&ep, r, s) > 0
12606 || !expr_const_in_range (&ep, -64, 64, 2))
12607 break;
12608
12609 imm = ep.X_add_number >> 2;
12610 INSERT_OPERAND (1, IMMA, *ip, imm);
12611 }
12612 s = expr_end;
12613 continue;
12614
12615 case 'B':
12616 {
12617 bfd_reloc_code_real_type r[3];
12618 expressionS ep;
12619 int imm;
12620
12621 if (my_getSmallExpression (&ep, r, s) > 0
12622 || ep.X_op != O_constant)
12623 break;
12624
12625 for (imm = 0; imm < 8; imm++)
12626 if (micromips_imm_b_map[imm] == ep.X_add_number)
12627 break;
12628 if (imm >= 8)
12629 break;
12630
12631 INSERT_OPERAND (1, IMMB, *ip, imm);
12632 }
12633 s = expr_end;
12634 continue;
12635
12636 case 'C':
12637 {
12638 bfd_reloc_code_real_type r[3];
12639 expressionS ep;
12640 int imm;
12641
12642 if (my_getSmallExpression (&ep, r, s) > 0
12643 || ep.X_op != O_constant)
12644 break;
12645
12646 for (imm = 0; imm < 16; imm++)
12647 if (micromips_imm_c_map[imm] == ep.X_add_number)
12648 break;
12649 if (imm >= 16)
12650 break;
12651
12652 INSERT_OPERAND (1, IMMC, *ip, imm);
12653 }
12654 s = expr_end;
12655 continue;
12656
12657 case 'D': /* pc relative offset */
12658 case 'E': /* pc relative offset */
12659 my_getExpression (&offset_expr, s);
12660 if (offset_expr.X_op == O_register)
12661 break;
12662
12663 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
12664 s = expr_end;
12665 continue;
12666
12667 case 'F':
12668 {
12669 bfd_reloc_code_real_type r[3];
12670 expressionS ep;
12671 int imm;
12672
12673 if (my_getSmallExpression (&ep, r, s) > 0
12674 || !expr_const_in_range (&ep, 0, 16, 0))
12675 break;
12676
12677 imm = ep.X_add_number;
12678 INSERT_OPERAND (1, IMMF, *ip, imm);
12679 }
12680 s = expr_end;
12681 continue;
12682
12683 case 'G':
12684 {
12685 bfd_reloc_code_real_type r[3];
12686 expressionS ep;
12687 int imm;
12688
12689 /* Check whether there is only a single bracketed
12690 expression left. If so, it must be the base register
12691 and the constant must be zero. */
12692 if (*s == '(' && strchr (s + 1, '(') == 0)
12693 {
12694 INSERT_OPERAND (1, IMMG, *ip, 0);
12695 continue;
12696 }
12697
12698 if (my_getSmallExpression (&ep, r, s) > 0
12699 || !expr_const_in_range (&ep, -1, 15, 0))
12700 break;
12701
12702 imm = ep.X_add_number & 15;
12703 INSERT_OPERAND (1, IMMG, *ip, imm);
12704 }
12705 s = expr_end;
12706 continue;
12707
12708 case 'H':
12709 {
12710 bfd_reloc_code_real_type r[3];
12711 expressionS ep;
12712 int imm;
12713
12714 /* Check whether there is only a single bracketed
12715 expression left. If so, it must be the base register
12716 and the constant must be zero. */
12717 if (*s == '(' && strchr (s + 1, '(') == 0)
12718 {
12719 INSERT_OPERAND (1, IMMH, *ip, 0);
12720 continue;
12721 }
12722
12723 if (my_getSmallExpression (&ep, r, s) > 0
12724 || !expr_const_in_range (&ep, 0, 16, 1))
12725 break;
12726
12727 imm = ep.X_add_number >> 1;
12728 INSERT_OPERAND (1, IMMH, *ip, imm);
12729 }
12730 s = expr_end;
12731 continue;
12732
12733 case 'I':
12734 {
12735 bfd_reloc_code_real_type r[3];
12736 expressionS ep;
12737 int imm;
12738
12739 if (my_getSmallExpression (&ep, r, s) > 0
12740 || !expr_const_in_range (&ep, -1, 127, 0))
12741 break;
12742
12743 imm = ep.X_add_number & 127;
12744 INSERT_OPERAND (1, IMMI, *ip, imm);
12745 }
12746 s = expr_end;
12747 continue;
12748
12749 case 'J':
12750 {
12751 bfd_reloc_code_real_type r[3];
12752 expressionS ep;
12753 int imm;
12754
12755 /* Check whether there is only a single bracketed
12756 expression left. If so, it must be the base register
12757 and the constant must be zero. */
12758 if (*s == '(' && strchr (s + 1, '(') == 0)
12759 {
12760 INSERT_OPERAND (1, IMMJ, *ip, 0);
12761 continue;
12762 }
12763
12764 if (my_getSmallExpression (&ep, r, s) > 0
12765 || !expr_const_in_range (&ep, 0, 16, 2))
12766 break;
12767
12768 imm = ep.X_add_number >> 2;
12769 INSERT_OPERAND (1, IMMJ, *ip, imm);
12770 }
12771 s = expr_end;
12772 continue;
12773
12774 case 'L':
12775 {
12776 bfd_reloc_code_real_type r[3];
12777 expressionS ep;
12778 int imm;
12779
12780 /* Check whether there is only a single bracketed
12781 expression left. If so, it must be the base register
12782 and the constant must be zero. */
12783 if (*s == '(' && strchr (s + 1, '(') == 0)
12784 {
12785 INSERT_OPERAND (1, IMML, *ip, 0);
12786 continue;
12787 }
12788
12789 if (my_getSmallExpression (&ep, r, s) > 0
12790 || !expr_const_in_range (&ep, 0, 16, 0))
12791 break;
12792
12793 imm = ep.X_add_number;
12794 INSERT_OPERAND (1, IMML, *ip, imm);
12795 }
12796 s = expr_end;
12797 continue;
12798
12799 case 'M':
12800 {
12801 bfd_reloc_code_real_type r[3];
12802 expressionS ep;
12803 int imm;
12804
12805 if (my_getSmallExpression (&ep, r, s) > 0
12806 || !expr_const_in_range (&ep, 1, 9, 0))
12807 break;
12808
12809 imm = ep.X_add_number & 7;
12810 INSERT_OPERAND (1, IMMM, *ip, imm);
12811 }
12812 s = expr_end;
12813 continue;
12814
12815 case 'N': /* Register list for lwm and swm. */
12816 {
12817 /* A comma-separated list of registers and/or
12818 dash-separated contiguous ranges including
12819 both ra and a set of one or more registers
12820 starting at s0 up to s3 which have to be
12821 consecutive, e.g.:
12822
12823 s0, ra
12824 s0, s1, ra, s2, s3
12825 s0-s2, ra
12826
12827 and any permutations of these. */
12828 unsigned int reglist;
12829 int imm;
12830
12831 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, &reglist))
12832 break;
12833
12834 if ((reglist & 0xfff1ffff) != 0x80010000)
12835 break;
12836
12837 reglist = (reglist >> 17) & 7;
12838 reglist += 1;
12839 if ((reglist & -reglist) != reglist)
12840 break;
252b5132 12841
df58fc94
RS
12842 imm = ffs (reglist) - 1;
12843 INSERT_OPERAND (1, IMMN, *ip, imm);
12844 }
12845 continue;
252b5132 12846
df58fc94
RS
12847 case 'O': /* sdbbp 4-bit code. */
12848 {
12849 bfd_reloc_code_real_type r[3];
12850 expressionS ep;
12851 int imm;
12852
12853 if (my_getSmallExpression (&ep, r, s) > 0
12854 || !expr_const_in_range (&ep, 0, 16, 0))
12855 break;
12856
12857 imm = ep.X_add_number;
12858 INSERT_OPERAND (1, IMMO, *ip, imm);
252b5132 12859 }
df58fc94
RS
12860 s = expr_end;
12861 continue;
252b5132 12862
df58fc94
RS
12863 case 'P':
12864 {
12865 bfd_reloc_code_real_type r[3];
12866 expressionS ep;
12867 int imm;
5e0116d5 12868
df58fc94
RS
12869 if (my_getSmallExpression (&ep, r, s) > 0
12870 || !expr_const_in_range (&ep, 0, 32, 2))
12871 break;
5e0116d5 12872
df58fc94
RS
12873 imm = ep.X_add_number >> 2;
12874 INSERT_OPERAND (1, IMMP, *ip, imm);
12875 }
12876 s = expr_end;
12877 continue;
5e0116d5 12878
df58fc94
RS
12879 case 'Q':
12880 {
12881 bfd_reloc_code_real_type r[3];
12882 expressionS ep;
12883 int imm;
5e0116d5 12884
df58fc94
RS
12885 if (my_getSmallExpression (&ep, r, s) > 0
12886 || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
12887 break;
252b5132 12888
df58fc94
RS
12889 imm = ep.X_add_number >> 2;
12890 INSERT_OPERAND (1, IMMQ, *ip, imm);
12891 }
12892 s = expr_end;
12893 continue;
4614d845 12894
df58fc94
RS
12895 case 'U':
12896 {
12897 bfd_reloc_code_real_type r[3];
12898 expressionS ep;
12899 int imm;
12900
12901 /* Check whether there is only a single bracketed
12902 expression left. If so, it must be the base register
12903 and the constant must be zero. */
12904 if (*s == '(' && strchr (s + 1, '(') == 0)
12905 {
12906 INSERT_OPERAND (1, IMMU, *ip, 0);
12907 continue;
12908 }
12909
12910 if (my_getSmallExpression (&ep, r, s) > 0
12911 || !expr_const_in_range (&ep, 0, 32, 2))
12912 break;
12913
12914 imm = ep.X_add_number >> 2;
12915 INSERT_OPERAND (1, IMMU, *ip, imm);
12916 }
12917 s = expr_end;
5e0116d5 12918 continue;
252b5132 12919
df58fc94
RS
12920 case 'W':
12921 {
12922 bfd_reloc_code_real_type r[3];
12923 expressionS ep;
12924 int imm;
252b5132 12925
df58fc94
RS
12926 if (my_getSmallExpression (&ep, r, s) > 0
12927 || !expr_const_in_range (&ep, 0, 64, 2))
12928 break;
252b5132 12929
df58fc94
RS
12930 imm = ep.X_add_number >> 2;
12931 INSERT_OPERAND (1, IMMW, *ip, imm);
12932 }
12933 s = expr_end;
12934 continue;
252b5132 12935
df58fc94
RS
12936 case 'X':
12937 {
12938 bfd_reloc_code_real_type r[3];
12939 expressionS ep;
12940 int imm;
252b5132 12941
df58fc94
RS
12942 if (my_getSmallExpression (&ep, r, s) > 0
12943 || !expr_const_in_range (&ep, -8, 8, 0))
12944 break;
252b5132 12945
df58fc94
RS
12946 imm = ep.X_add_number;
12947 INSERT_OPERAND (1, IMMX, *ip, imm);
12948 }
12949 s = expr_end;
12950 continue;
252b5132 12951
df58fc94
RS
12952 case 'Y':
12953 {
12954 bfd_reloc_code_real_type r[3];
12955 expressionS ep;
12956 int imm;
156c2f8b 12957
df58fc94
RS
12958 if (my_getSmallExpression (&ep, r, s) > 0
12959 || expr_const_in_range (&ep, -2, 2, 2)
12960 || !expr_const_in_range (&ep, -258, 258, 2))
12961 break;
156c2f8b 12962
df58fc94
RS
12963 imm = ep.X_add_number >> 2;
12964 imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
12965 INSERT_OPERAND (1, IMMY, *ip, imm);
12966 }
12967 s = expr_end;
12968 continue;
60b63b72 12969
df58fc94
RS
12970 case 'Z':
12971 {
12972 bfd_reloc_code_real_type r[3];
12973 expressionS ep;
12974
12975 if (my_getSmallExpression (&ep, r, s) > 0
12976 || !expr_const_in_range (&ep, 0, 1, 0))
12977 break;
12978 }
12979 s = expr_end;
12980 continue;
12981
12982 default:
12983 as_bad (_("Internal error: bad microMIPS opcode "
12984 "(unknown extension operand type `m%c'): %s %s"),
12985 *args, insn->name, insn->args);
12986 /* Further processing is fruitless. */
12987 return;
60b63b72 12988 }
df58fc94 12989 break;
60b63b72 12990
df58fc94
RS
12991 case 'n': /* Register list for 32-bit lwm and swm. */
12992 gas_assert (mips_opts.micromips);
12993 {
12994 /* A comma-separated list of registers and/or
12995 dash-separated contiguous ranges including
12996 at least one of ra and a set of one or more
12997 registers starting at s0 up to s7 and then
12998 s8 which have to be consecutive, e.g.:
12999
13000 ra
13001 s0
13002 ra, s0, s1, s2
13003 s0-s8
13004 s0-s5, ra
13005
13006 and any permutations of these. */
13007 unsigned int reglist;
13008 int imm;
13009 int ra;
13010
13011 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, &reglist))
13012 break;
13013
13014 if ((reglist & 0x3f00ffff) != 0)
13015 break;
13016
13017 ra = (reglist >> 27) & 0x10;
13018 reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
13019 reglist += 1;
13020 if ((reglist & -reglist) != reglist)
13021 break;
13022
13023 imm = (ffs (reglist) - 1) | ra;
13024 INSERT_OPERAND (1, RT, *ip, imm);
13025 imm_expr.X_op = O_absent;
13026 }
60b63b72
RS
13027 continue;
13028
df58fc94
RS
13029 case '|': /* 4-bit trap code. */
13030 gas_assert (mips_opts.micromips);
60b63b72
RS
13031 my_getExpression (&imm_expr, s);
13032 check_absolute_expr (ip, &imm_expr);
60b63b72 13033 if ((unsigned long) imm_expr.X_add_number
df58fc94
RS
13034 > MICROMIPSOP_MASK_TRAP)
13035 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13036 (unsigned long) imm_expr.X_add_number,
13037 ip->insn_mo->name);
13038 INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
60b63b72
RS
13039 imm_expr.X_op = O_absent;
13040 s = expr_end;
13041 continue;
13042
252b5132 13043 default:
f71d0d44 13044 as_bad (_("Bad char = '%c'\n"), *args);
252b5132
RH
13045 internalError ();
13046 }
13047 break;
13048 }
13049 /* Args don't match. */
df58fc94
RS
13050 s = argsStart;
13051 insn_error = _("Illegal operands");
13052 if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
252b5132
RH
13053 {
13054 ++insn;
252b5132
RH
13055 continue;
13056 }
df58fc94
RS
13057 else if (wrong_delay_slot_insns && need_delay_slot_ok)
13058 {
13059 gas_assert (firstinsn);
13060 need_delay_slot_ok = FALSE;
13061 past = insn + 1;
13062 insn = firstinsn;
13063 continue;
13064 }
252b5132
RH
13065 return;
13066 }
13067}
13068
0499d65b
TS
13069#define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13070
252b5132
RH
13071/* This routine assembles an instruction into its binary format when
13072 assembling for the mips16. As a side effect, it sets one of the
df58fc94
RS
13073 global variables imm_reloc or offset_reloc to the type of relocation
13074 to do if one of the operands is an address expression. It also sets
13075 forced_insn_length to the resulting instruction size in bytes if the
13076 user explicitly requested a small or extended instruction. */
252b5132
RH
13077
13078static void
17a2f251 13079mips16_ip (char *str, struct mips_cl_insn *ip)
252b5132
RH
13080{
13081 char *s;
13082 const char *args;
13083 struct mips_opcode *insn;
13084 char *argsstart;
13085 unsigned int regno;
13086 unsigned int lastregno = 0;
13087 char *s_reset;
d6f16593 13088 size_t i;
252b5132
RH
13089
13090 insn_error = NULL;
13091
df58fc94 13092 forced_insn_length = 0;
252b5132 13093
3882b010 13094 for (s = str; ISLOWER (*s); ++s)
252b5132
RH
13095 ;
13096 switch (*s)
13097 {
13098 case '\0':
13099 break;
13100
13101 case ' ':
13102 *s++ = '\0';
13103 break;
13104
13105 case '.':
13106 if (s[1] == 't' && s[2] == ' ')
13107 {
13108 *s = '\0';
df58fc94 13109 forced_insn_length = 2;
252b5132
RH
13110 s += 3;
13111 break;
13112 }
13113 else if (s[1] == 'e' && s[2] == ' ')
13114 {
13115 *s = '\0';
df58fc94 13116 forced_insn_length = 4;
252b5132
RH
13117 s += 3;
13118 break;
13119 }
13120 /* Fall through. */
13121 default:
13122 insn_error = _("unknown opcode");
13123 return;
13124 }
13125
df58fc94
RS
13126 if (mips_opts.noautoextend && !forced_insn_length)
13127 forced_insn_length = 2;
252b5132
RH
13128
13129 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13130 {
13131 insn_error = _("unrecognized opcode");
13132 return;
13133 }
13134
13135 argsstart = s;
13136 for (;;)
13137 {
9b3f89ee
TS
13138 bfd_boolean ok;
13139
9c2799c2 13140 gas_assert (strcmp (insn->name, str) == 0);
252b5132 13141
037b32b9 13142 ok = is_opcode_valid_16 (insn);
9b3f89ee
TS
13143 if (! ok)
13144 {
13145 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13146 && strcmp (insn->name, insn[1].name) == 0)
13147 {
13148 ++insn;
13149 continue;
13150 }
13151 else
13152 {
13153 if (!insn_error)
13154 {
13155 static char buf[100];
13156 sprintf (buf,
13157 _("opcode not supported on this processor: %s (%s)"),
13158 mips_cpu_info_from_arch (mips_opts.arch)->name,
13159 mips_cpu_info_from_isa (mips_opts.isa)->name);
13160 insn_error = buf;
13161 }
13162 return;
13163 }
13164 }
13165
1e915849 13166 create_insn (ip, insn);
252b5132 13167 imm_expr.X_op = O_absent;
f6688943
TS
13168 imm_reloc[0] = BFD_RELOC_UNUSED;
13169 imm_reloc[1] = BFD_RELOC_UNUSED;
13170 imm_reloc[2] = BFD_RELOC_UNUSED;
5f74bc13 13171 imm2_expr.X_op = O_absent;
252b5132 13172 offset_expr.X_op = O_absent;
f6688943
TS
13173 offset_reloc[0] = BFD_RELOC_UNUSED;
13174 offset_reloc[1] = BFD_RELOC_UNUSED;
13175 offset_reloc[2] = BFD_RELOC_UNUSED;
252b5132
RH
13176 for (args = insn->args; 1; ++args)
13177 {
13178 int c;
13179
13180 if (*s == ' ')
13181 ++s;
13182
13183 /* In this switch statement we call break if we did not find
13184 a match, continue if we did find a match, or return if we
13185 are done. */
13186
13187 c = *args;
13188 switch (c)
13189 {
13190 case '\0':
13191 if (*s == '\0')
13192 {
13193 /* Stuff the immediate value in now, if we can. */
13194 if (imm_expr.X_op == O_constant
f6688943 13195 && *imm_reloc > BFD_RELOC_UNUSED
738e5348
RS
13196 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
13197 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
252b5132
RH
13198 && insn->pinfo != INSN_MACRO)
13199 {
d6f16593
MR
13200 valueT tmp;
13201
13202 switch (*offset_reloc)
13203 {
13204 case BFD_RELOC_MIPS16_HI16_S:
13205 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
13206 break;
13207
13208 case BFD_RELOC_MIPS16_HI16:
13209 tmp = imm_expr.X_add_number >> 16;
13210 break;
13211
13212 case BFD_RELOC_MIPS16_LO16:
13213 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
13214 - 0x8000;
13215 break;
13216
13217 case BFD_RELOC_UNUSED:
13218 tmp = imm_expr.X_add_number;
13219 break;
13220
13221 default:
13222 internalError ();
13223 }
13224 *offset_reloc = BFD_RELOC_UNUSED;
13225
c4e7957c 13226 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
df58fc94
RS
13227 tmp, TRUE, forced_insn_length == 2,
13228 forced_insn_length == 4, &ip->insn_opcode,
252b5132
RH
13229 &ip->use_extend, &ip->extend);
13230 imm_expr.X_op = O_absent;
f6688943 13231 *imm_reloc = BFD_RELOC_UNUSED;
252b5132
RH
13232 }
13233
13234 return;
13235 }
13236 break;
13237
13238 case ',':
13239 if (*s++ == c)
13240 continue;
13241 s--;
13242 switch (*++args)
13243 {
13244 case 'v':
bf12938e 13245 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
252b5132
RH
13246 continue;
13247 case 'w':
bf12938e 13248 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
252b5132
RH
13249 continue;
13250 }
13251 break;
13252
13253 case '(':
13254 case ')':
13255 if (*s++ == c)
13256 continue;
13257 break;
13258
13259 case 'v':
13260 case 'w':
13261 if (s[0] != '$')
13262 {
13263 if (c == 'v')
bf12938e 13264 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
252b5132 13265 else
bf12938e 13266 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
252b5132
RH
13267 ++args;
13268 continue;
13269 }
13270 /* Fall through. */
13271 case 'x':
13272 case 'y':
13273 case 'z':
13274 case 'Z':
13275 case '0':
13276 case 'S':
13277 case 'R':
13278 case 'X':
13279 case 'Y':
707bfff6
TS
13280 s_reset = s;
13281 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno))
252b5132 13282 {
707bfff6 13283 if (c == 'v' || c == 'w')
85b51719 13284 {
707bfff6 13285 if (c == 'v')
a9e24354 13286 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
707bfff6 13287 else
a9e24354 13288 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
707bfff6
TS
13289 ++args;
13290 continue;
85b51719 13291 }
707bfff6 13292 break;
252b5132
RH
13293 }
13294
13295 if (*s == ' ')
13296 ++s;
13297 if (args[1] != *s)
13298 {
13299 if (c == 'v' || c == 'w')
13300 {
13301 regno = mips16_to_32_reg_map[lastregno];
13302 s = s_reset;
f9419b05 13303 ++args;
252b5132
RH
13304 }
13305 }
13306
13307 switch (c)
13308 {
13309 case 'x':
13310 case 'y':
13311 case 'z':
13312 case 'v':
13313 case 'w':
13314 case 'Z':
13315 regno = mips32_to_16_reg_map[regno];
13316 break;
13317
13318 case '0':
13319 if (regno != 0)
13320 regno = ILLEGAL_REG;
13321 break;
13322
13323 case 'S':
13324 if (regno != SP)
13325 regno = ILLEGAL_REG;
13326 break;
13327
13328 case 'R':
13329 if (regno != RA)
13330 regno = ILLEGAL_REG;
13331 break;
13332
13333 case 'X':
13334 case 'Y':
741fe287
MR
13335 if (regno == AT && mips_opts.at)
13336 {
13337 if (mips_opts.at == ATREG)
13338 as_warn (_("used $at without \".set noat\""));
13339 else
13340 as_warn (_("used $%u with \".set at=$%u\""),
13341 regno, mips_opts.at);
13342 }
252b5132
RH
13343 break;
13344
13345 default:
13346 internalError ();
13347 }
13348
13349 if (regno == ILLEGAL_REG)
13350 break;
13351
13352 switch (c)
13353 {
13354 case 'x':
13355 case 'v':
bf12938e 13356 MIPS16_INSERT_OPERAND (RX, *ip, regno);
252b5132
RH
13357 break;
13358 case 'y':
13359 case 'w':
bf12938e 13360 MIPS16_INSERT_OPERAND (RY, *ip, regno);
252b5132
RH
13361 break;
13362 case 'z':
bf12938e 13363 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
252b5132
RH
13364 break;
13365 case 'Z':
bf12938e 13366 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
252b5132
RH
13367 case '0':
13368 case 'S':
13369 case 'R':
13370 break;
13371 case 'X':
bf12938e 13372 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
252b5132
RH
13373 break;
13374 case 'Y':
13375 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
bf12938e 13376 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
252b5132
RH
13377 break;
13378 default:
13379 internalError ();
13380 }
13381
13382 lastregno = regno;
13383 continue;
13384
13385 case 'P':
13386 if (strncmp (s, "$pc", 3) == 0)
13387 {
13388 s += 3;
13389 continue;
13390 }
13391 break;
13392
252b5132
RH
13393 case '5':
13394 case 'H':
13395 case 'W':
13396 case 'D':
13397 case 'j':
252b5132
RH
13398 case 'V':
13399 case 'C':
13400 case 'U':
13401 case 'k':
13402 case 'K':
d6f16593
MR
13403 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
13404 if (i > 0)
252b5132 13405 {
d6f16593 13406 if (imm_expr.X_op != O_constant)
252b5132 13407 {
df58fc94 13408 forced_insn_length = 4;
b34976b6 13409 ip->use_extend = TRUE;
252b5132 13410 ip->extend = 0;
252b5132 13411 }
d6f16593
MR
13412 else
13413 {
13414 /* We need to relax this instruction. */
13415 *offset_reloc = *imm_reloc;
13416 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13417 }
13418 s = expr_end;
13419 continue;
252b5132 13420 }
d6f16593
MR
13421 *imm_reloc = BFD_RELOC_UNUSED;
13422 /* Fall through. */
13423 case '<':
13424 case '>':
13425 case '[':
13426 case ']':
13427 case '4':
13428 case '8':
13429 my_getExpression (&imm_expr, s);
252b5132
RH
13430 if (imm_expr.X_op == O_register)
13431 {
13432 /* What we thought was an expression turned out to
13433 be a register. */
13434
13435 if (s[0] == '(' && args[1] == '(')
13436 {
13437 /* It looks like the expression was omitted
13438 before a register indirection, which means
13439 that the expression is implicitly zero. We
13440 still set up imm_expr, so that we handle
13441 explicit extensions correctly. */
13442 imm_expr.X_op = O_constant;
13443 imm_expr.X_add_number = 0;
f6688943 13444 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
252b5132
RH
13445 continue;
13446 }
13447
13448 break;
13449 }
13450
13451 /* We need to relax this instruction. */
f6688943 13452 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
252b5132
RH
13453 s = expr_end;
13454 continue;
13455
13456 case 'p':
13457 case 'q':
13458 case 'A':
13459 case 'B':
13460 case 'E':
13461 /* We use offset_reloc rather than imm_reloc for the PC
13462 relative operands. This lets macros with both
13463 immediate and address operands work correctly. */
13464 my_getExpression (&offset_expr, s);
13465
13466 if (offset_expr.X_op == O_register)
13467 break;
13468
13469 /* We need to relax this instruction. */
f6688943 13470 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
252b5132
RH
13471 s = expr_end;
13472 continue;
13473
13474 case '6': /* break code */
13475 my_getExpression (&imm_expr, s);
13476 check_absolute_expr (ip, &imm_expr);
13477 if ((unsigned long) imm_expr.X_add_number > 63)
bf12938e
RS
13478 as_warn (_("Invalid value for `%s' (%lu)"),
13479 ip->insn_mo->name,
13480 (unsigned long) imm_expr.X_add_number);
13481 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
252b5132
RH
13482 imm_expr.X_op = O_absent;
13483 s = expr_end;
13484 continue;
13485
13486 case 'a': /* 26 bit address */
13487 my_getExpression (&offset_expr, s);
13488 s = expr_end;
f6688943 13489 *offset_reloc = BFD_RELOC_MIPS16_JMP;
252b5132
RH
13490 ip->insn_opcode <<= 16;
13491 continue;
13492
13493 case 'l': /* register list for entry macro */
13494 case 'L': /* register list for exit macro */
13495 {
13496 int mask;
13497
13498 if (c == 'l')
13499 mask = 0;
13500 else
13501 mask = 7 << 3;
13502 while (*s != '\0')
13503 {
707bfff6 13504 unsigned int freg, reg1, reg2;
252b5132
RH
13505
13506 while (*s == ' ' || *s == ',')
13507 ++s;
707bfff6 13508 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, &reg1))
252b5132 13509 freg = 0;
707bfff6
TS
13510 else if (reg_lookup (&s, RTYPE_FPU, &reg1))
13511 freg = 1;
252b5132
RH
13512 else
13513 {
707bfff6
TS
13514 as_bad (_("can't parse register list"));
13515 break;
252b5132
RH
13516 }
13517 if (*s == ' ')
13518 ++s;
13519 if (*s != '-')
13520 reg2 = reg1;
13521 else
13522 {
13523 ++s;
707bfff6
TS
13524 if (!reg_lookup (&s, freg ? RTYPE_FPU
13525 : (RTYPE_GP | RTYPE_NUM), &reg2))
252b5132 13526 {
707bfff6
TS
13527 as_bad (_("invalid register list"));
13528 break;
252b5132
RH
13529 }
13530 }
13531 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
13532 {
13533 mask &= ~ (7 << 3);
13534 mask |= 5 << 3;
13535 }
13536 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
13537 {
13538 mask &= ~ (7 << 3);
13539 mask |= 6 << 3;
13540 }
13541 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
13542 mask |= (reg2 - 3) << 3;
13543 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
13544 mask |= (reg2 - 15) << 1;
f9419b05 13545 else if (reg1 == RA && reg2 == RA)
252b5132
RH
13546 mask |= 1;
13547 else
13548 {
13549 as_bad (_("invalid register list"));
13550 break;
13551 }
13552 }
13553 /* The mask is filled in in the opcode table for the
13554 benefit of the disassembler. We remove it before
13555 applying the actual mask. */
13556 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
13557 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
13558 }
13559 continue;
13560
0499d65b
TS
13561 case 'm': /* Register list for save insn. */
13562 case 'M': /* Register list for restore insn. */
13563 {
13564 int opcode = 0;
13565 int framesz = 0, seen_framesz = 0;
91d6fa6a 13566 int nargs = 0, statics = 0, sregs = 0;
0499d65b
TS
13567
13568 while (*s != '\0')
13569 {
13570 unsigned int reg1, reg2;
13571
13572 SKIP_SPACE_TABS (s);
13573 while (*s == ',')
13574 ++s;
13575 SKIP_SPACE_TABS (s);
13576
13577 my_getExpression (&imm_expr, s);
13578 if (imm_expr.X_op == O_constant)
13579 {
13580 /* Handle the frame size. */
13581 if (seen_framesz)
13582 {
13583 as_bad (_("more than one frame size in list"));
13584 break;
13585 }
13586 seen_framesz = 1;
13587 framesz = imm_expr.X_add_number;
13588 imm_expr.X_op = O_absent;
13589 s = expr_end;
13590 continue;
13591 }
13592
707bfff6 13593 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, &reg1))
0499d65b
TS
13594 {
13595 as_bad (_("can't parse register list"));
13596 break;
13597 }
0499d65b 13598
707bfff6
TS
13599 while (*s == ' ')
13600 ++s;
13601
0499d65b
TS
13602 if (*s != '-')
13603 reg2 = reg1;
13604 else
13605 {
13606 ++s;
707bfff6
TS
13607 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, &reg2)
13608 || reg2 < reg1)
0499d65b
TS
13609 {
13610 as_bad (_("can't parse register list"));
13611 break;
13612 }
0499d65b
TS
13613 }
13614
13615 while (reg1 <= reg2)
13616 {
13617 if (reg1 >= 4 && reg1 <= 7)
13618 {
3a93f742 13619 if (!seen_framesz)
0499d65b 13620 /* args $a0-$a3 */
91d6fa6a 13621 nargs |= 1 << (reg1 - 4);
0499d65b
TS
13622 else
13623 /* statics $a0-$a3 */
13624 statics |= 1 << (reg1 - 4);
13625 }
13626 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
13627 {
13628 /* $s0-$s8 */
13629 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
13630 }
13631 else if (reg1 == 31)
13632 {
13633 /* Add $ra to insn. */
13634 opcode |= 0x40;
13635 }
13636 else
13637 {
13638 as_bad (_("unexpected register in list"));
13639 break;
13640 }
13641 if (++reg1 == 24)
13642 reg1 = 30;
13643 }
13644 }
13645
13646 /* Encode args/statics combination. */
91d6fa6a 13647 if (nargs & statics)
0499d65b 13648 as_bad (_("arg/static registers overlap"));
91d6fa6a 13649 else if (nargs == 0xf)
0499d65b
TS
13650 /* All $a0-$a3 are args. */
13651 opcode |= MIPS16_ALL_ARGS << 16;
13652 else if (statics == 0xf)
13653 /* All $a0-$a3 are statics. */
13654 opcode |= MIPS16_ALL_STATICS << 16;
13655 else
13656 {
13657 int narg = 0, nstat = 0;
13658
13659 /* Count arg registers. */
91d6fa6a 13660 while (nargs & 0x1)
0499d65b 13661 {
91d6fa6a 13662 nargs >>= 1;
0499d65b
TS
13663 narg++;
13664 }
91d6fa6a 13665 if (nargs != 0)
0499d65b
TS
13666 as_bad (_("invalid arg register list"));
13667
13668 /* Count static registers. */
13669 while (statics & 0x8)
13670 {
13671 statics = (statics << 1) & 0xf;
13672 nstat++;
13673 }
13674 if (statics != 0)
13675 as_bad (_("invalid static register list"));
13676
13677 /* Encode args/statics. */
13678 opcode |= ((narg << 2) | nstat) << 16;
13679 }
13680
13681 /* Encode $s0/$s1. */
13682 if (sregs & (1 << 0)) /* $s0 */
13683 opcode |= 0x20;
13684 if (sregs & (1 << 1)) /* $s1 */
13685 opcode |= 0x10;
13686 sregs >>= 2;
13687
13688 if (sregs != 0)
13689 {
13690 /* Count regs $s2-$s8. */
13691 int nsreg = 0;
13692 while (sregs & 1)
13693 {
13694 sregs >>= 1;
13695 nsreg++;
13696 }
13697 if (sregs != 0)
13698 as_bad (_("invalid static register list"));
13699 /* Encode $s2-$s8. */
13700 opcode |= nsreg << 24;
13701 }
13702
13703 /* Encode frame size. */
13704 if (!seen_framesz)
13705 as_bad (_("missing frame size"));
13706 else if ((framesz & 7) != 0 || framesz < 0
13707 || framesz > 0xff * 8)
13708 as_bad (_("invalid frame size"));
13709 else if (framesz != 128 || (opcode >> 16) != 0)
13710 {
13711 framesz /= 8;
13712 opcode |= (((framesz & 0xf0) << 16)
13713 | (framesz & 0x0f));
13714 }
13715
13716 /* Finally build the instruction. */
13717 if ((opcode >> 16) != 0 || framesz == 0)
13718 {
13719 ip->use_extend = TRUE;
13720 ip->extend = opcode >> 16;
13721 }
13722 ip->insn_opcode |= opcode & 0x7f;
13723 }
13724 continue;
13725
252b5132
RH
13726 case 'e': /* extend code */
13727 my_getExpression (&imm_expr, s);
13728 check_absolute_expr (ip, &imm_expr);
13729 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
13730 {
13731 as_warn (_("Invalid value for `%s' (%lu)"),
13732 ip->insn_mo->name,
13733 (unsigned long) imm_expr.X_add_number);
13734 imm_expr.X_add_number &= 0x7ff;
13735 }
13736 ip->insn_opcode |= imm_expr.X_add_number;
13737 imm_expr.X_op = O_absent;
13738 s = expr_end;
13739 continue;
13740
13741 default:
13742 internalError ();
13743 }
13744 break;
13745 }
13746
13747 /* Args don't match. */
13748 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
13749 strcmp (insn->name, insn[1].name) == 0)
13750 {
13751 ++insn;
13752 s = argsstart;
13753 continue;
13754 }
13755
13756 insn_error = _("illegal operands");
13757
13758 return;
13759 }
13760}
13761
13762/* This structure holds information we know about a mips16 immediate
13763 argument type. */
13764
e972090a
NC
13765struct mips16_immed_operand
13766{
252b5132
RH
13767 /* The type code used in the argument string in the opcode table. */
13768 int type;
13769 /* The number of bits in the short form of the opcode. */
13770 int nbits;
13771 /* The number of bits in the extended form of the opcode. */
13772 int extbits;
13773 /* The amount by which the short form is shifted when it is used;
13774 for example, the sw instruction has a shift count of 2. */
13775 int shift;
13776 /* The amount by which the short form is shifted when it is stored
13777 into the instruction code. */
13778 int op_shift;
13779 /* Non-zero if the short form is unsigned. */
13780 int unsp;
13781 /* Non-zero if the extended form is unsigned. */
13782 int extu;
13783 /* Non-zero if the value is PC relative. */
13784 int pcrel;
13785};
13786
13787/* The mips16 immediate operand types. */
13788
13789static const struct mips16_immed_operand mips16_immed_operands[] =
13790{
13791 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
13792 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
13793 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
13794 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
13795 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
13796 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
13797 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
13798 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
13799 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
13800 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
13801 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
13802 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
13803 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
13804 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
13805 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
13806 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
13807 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
13808 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
13809 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
13810 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
13811 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
13812};
13813
13814#define MIPS16_NUM_IMMED \
13815 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
13816
13817/* Handle a mips16 instruction with an immediate value. This or's the
13818 small immediate value into *INSN. It sets *USE_EXTEND to indicate
13819 whether an extended value is needed; if one is needed, it sets
13820 *EXTEND to the value. The argument type is TYPE. The value is VAL.
13821 If SMALL is true, an unextended opcode was explicitly requested.
13822 If EXT is true, an extended opcode was explicitly requested. If
13823 WARN is true, warn if EXT does not match reality. */
13824
13825static void
17a2f251
TS
13826mips16_immed (char *file, unsigned int line, int type, offsetT val,
13827 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
13828 unsigned long *insn, bfd_boolean *use_extend,
13829 unsigned short *extend)
252b5132 13830{
3994f87e 13831 const struct mips16_immed_operand *op;
252b5132 13832 int mintiny, maxtiny;
b34976b6 13833 bfd_boolean needext;
252b5132
RH
13834
13835 op = mips16_immed_operands;
13836 while (op->type != type)
13837 {
13838 ++op;
9c2799c2 13839 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
252b5132
RH
13840 }
13841
13842 if (op->unsp)
13843 {
13844 if (type == '<' || type == '>' || type == '[' || type == ']')
13845 {
13846 mintiny = 1;
13847 maxtiny = 1 << op->nbits;
13848 }
13849 else
13850 {
13851 mintiny = 0;
13852 maxtiny = (1 << op->nbits) - 1;
13853 }
13854 }
13855 else
13856 {
13857 mintiny = - (1 << (op->nbits - 1));
13858 maxtiny = (1 << (op->nbits - 1)) - 1;
13859 }
13860
13861 /* Branch offsets have an implicit 0 in the lowest bit. */
13862 if (type == 'p' || type == 'q')
13863 val /= 2;
13864
13865 if ((val & ((1 << op->shift) - 1)) != 0
13866 || val < (mintiny << op->shift)
13867 || val > (maxtiny << op->shift))
b34976b6 13868 needext = TRUE;
252b5132 13869 else
b34976b6 13870 needext = FALSE;
252b5132
RH
13871
13872 if (warn && ext && ! needext)
beae10d5
KH
13873 as_warn_where (file, line,
13874 _("extended operand requested but not required"));
252b5132
RH
13875 if (small && needext)
13876 as_bad_where (file, line, _("invalid unextended operand value"));
13877
13878 if (small || (! ext && ! needext))
13879 {
13880 int insnval;
13881
b34976b6 13882 *use_extend = FALSE;
252b5132
RH
13883 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
13884 insnval <<= op->op_shift;
13885 *insn |= insnval;
13886 }
13887 else
13888 {
13889 long minext, maxext;
13890 int extval;
13891
13892 if (op->extu)
13893 {
13894 minext = 0;
13895 maxext = (1 << op->extbits) - 1;
13896 }
13897 else
13898 {
13899 minext = - (1 << (op->extbits - 1));
13900 maxext = (1 << (op->extbits - 1)) - 1;
13901 }
13902 if (val < minext || val > maxext)
13903 as_bad_where (file, line,
13904 _("operand value out of range for instruction"));
13905
b34976b6 13906 *use_extend = TRUE;
252b5132
RH
13907 if (op->extbits == 16)
13908 {
13909 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
13910 val &= 0x1f;
13911 }
13912 else if (op->extbits == 15)
13913 {
13914 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
13915 val &= 0xf;
13916 }
13917 else
13918 {
13919 extval = ((val & 0x1f) << 6) | (val & 0x20);
13920 val = 0;
13921 }
13922
13923 *extend = (unsigned short) extval;
13924 *insn |= val;
13925 }
13926}
13927\f
d6f16593 13928struct percent_op_match
ad8d3bb3 13929{
5e0116d5
RS
13930 const char *str;
13931 bfd_reloc_code_real_type reloc;
d6f16593
MR
13932};
13933
13934static const struct percent_op_match mips_percent_op[] =
ad8d3bb3 13935{
5e0116d5 13936 {"%lo", BFD_RELOC_LO16},
ad8d3bb3 13937#ifdef OBJ_ELF
5e0116d5
RS
13938 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
13939 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
13940 {"%call16", BFD_RELOC_MIPS_CALL16},
13941 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
13942 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
13943 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
13944 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
13945 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
13946 {"%got", BFD_RELOC_MIPS_GOT16},
13947 {"%gp_rel", BFD_RELOC_GPREL16},
13948 {"%half", BFD_RELOC_16},
13949 {"%highest", BFD_RELOC_MIPS_HIGHEST},
13950 {"%higher", BFD_RELOC_MIPS_HIGHER},
13951 {"%neg", BFD_RELOC_MIPS_SUB},
3f98094e
DJ
13952 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
13953 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
13954 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
13955 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
13956 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
13957 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
13958 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
ad8d3bb3 13959#endif
5e0116d5 13960 {"%hi", BFD_RELOC_HI16_S}
ad8d3bb3
TS
13961};
13962
d6f16593
MR
13963static const struct percent_op_match mips16_percent_op[] =
13964{
13965 {"%lo", BFD_RELOC_MIPS16_LO16},
13966 {"%gprel", BFD_RELOC_MIPS16_GPREL},
738e5348
RS
13967 {"%got", BFD_RELOC_MIPS16_GOT16},
13968 {"%call16", BFD_RELOC_MIPS16_CALL16},
d6f16593
MR
13969 {"%hi", BFD_RELOC_MIPS16_HI16_S}
13970};
13971
252b5132 13972
5e0116d5
RS
13973/* Return true if *STR points to a relocation operator. When returning true,
13974 move *STR over the operator and store its relocation code in *RELOC.
13975 Leave both *STR and *RELOC alone when returning false. */
13976
13977static bfd_boolean
17a2f251 13978parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
252b5132 13979{
d6f16593
MR
13980 const struct percent_op_match *percent_op;
13981 size_t limit, i;
13982
13983 if (mips_opts.mips16)
13984 {
13985 percent_op = mips16_percent_op;
13986 limit = ARRAY_SIZE (mips16_percent_op);
13987 }
13988 else
13989 {
13990 percent_op = mips_percent_op;
13991 limit = ARRAY_SIZE (mips_percent_op);
13992 }
76b3015f 13993
d6f16593 13994 for (i = 0; i < limit; i++)
5e0116d5 13995 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
394f9b3a 13996 {
3f98094e
DJ
13997 int len = strlen (percent_op[i].str);
13998
13999 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14000 continue;
14001
5e0116d5
RS
14002 *str += strlen (percent_op[i].str);
14003 *reloc = percent_op[i].reloc;
394f9b3a 14004
5e0116d5
RS
14005 /* Check whether the output BFD supports this relocation.
14006 If not, issue an error and fall back on something safe. */
14007 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
394f9b3a 14008 {
20203fb9 14009 as_bad (_("relocation %s isn't supported by the current ABI"),
5e0116d5 14010 percent_op[i].str);
01a3f561 14011 *reloc = BFD_RELOC_UNUSED;
394f9b3a 14012 }
5e0116d5 14013 return TRUE;
394f9b3a 14014 }
5e0116d5 14015 return FALSE;
394f9b3a 14016}
ad8d3bb3 14017
ad8d3bb3 14018
5e0116d5
RS
14019/* Parse string STR as a 16-bit relocatable operand. Store the
14020 expression in *EP and the relocations in the array starting
14021 at RELOC. Return the number of relocation operators used.
ad8d3bb3 14022
01a3f561 14023 On exit, EXPR_END points to the first character after the expression. */
ad8d3bb3 14024
5e0116d5 14025static size_t
17a2f251
TS
14026my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14027 char *str)
ad8d3bb3 14028{
5e0116d5
RS
14029 bfd_reloc_code_real_type reversed_reloc[3];
14030 size_t reloc_index, i;
09b8f35a
RS
14031 int crux_depth, str_depth;
14032 char *crux;
5e0116d5
RS
14033
14034 /* Search for the start of the main expression, recoding relocations
09b8f35a
RS
14035 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14036 of the main expression and with CRUX_DEPTH containing the number
14037 of open brackets at that point. */
14038 reloc_index = -1;
14039 str_depth = 0;
14040 do
fb1b3232 14041 {
09b8f35a
RS
14042 reloc_index++;
14043 crux = str;
14044 crux_depth = str_depth;
14045
14046 /* Skip over whitespace and brackets, keeping count of the number
14047 of brackets. */
14048 while (*str == ' ' || *str == '\t' || *str == '(')
14049 if (*str++ == '(')
14050 str_depth++;
5e0116d5 14051 }
09b8f35a
RS
14052 while (*str == '%'
14053 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14054 && parse_relocation (&str, &reversed_reloc[reloc_index]));
ad8d3bb3 14055
09b8f35a 14056 my_getExpression (ep, crux);
5e0116d5 14057 str = expr_end;
394f9b3a 14058
5e0116d5 14059 /* Match every open bracket. */
09b8f35a 14060 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
5e0116d5 14061 if (*str++ == ')')
09b8f35a 14062 crux_depth--;
394f9b3a 14063
09b8f35a 14064 if (crux_depth > 0)
20203fb9 14065 as_bad (_("unclosed '('"));
394f9b3a 14066
5e0116d5 14067 expr_end = str;
252b5132 14068
01a3f561 14069 if (reloc_index != 0)
64bdfcaf
RS
14070 {
14071 prev_reloc_op_frag = frag_now;
14072 for (i = 0; i < reloc_index; i++)
14073 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14074 }
fb1b3232 14075
5e0116d5 14076 return reloc_index;
252b5132
RH
14077}
14078
14079static void
17a2f251 14080my_getExpression (expressionS *ep, char *str)
252b5132
RH
14081{
14082 char *save_in;
14083
14084 save_in = input_line_pointer;
14085 input_line_pointer = str;
14086 expression (ep);
14087 expr_end = input_line_pointer;
14088 input_line_pointer = save_in;
252b5132
RH
14089}
14090
252b5132 14091char *
17a2f251 14092md_atof (int type, char *litP, int *sizeP)
252b5132 14093{
499ac353 14094 return ieee_md_atof (type, litP, sizeP, target_big_endian);
252b5132
RH
14095}
14096
14097void
17a2f251 14098md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH
14099{
14100 if (target_big_endian)
14101 number_to_chars_bigendian (buf, val, n);
14102 else
14103 number_to_chars_littleendian (buf, val, n);
14104}
14105\f
ae948b86 14106#ifdef OBJ_ELF
e013f690
TS
14107static int support_64bit_objects(void)
14108{
14109 const char **list, **l;
aa3d8fdf 14110 int yes;
e013f690
TS
14111
14112 list = bfd_target_list ();
14113 for (l = list; *l != NULL; l++)
aeffff67
RS
14114 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14115 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
e013f690 14116 break;
aa3d8fdf 14117 yes = (*l != NULL);
e013f690 14118 free (list);
aa3d8fdf 14119 return yes;
e013f690 14120}
ae948b86 14121#endif /* OBJ_ELF */
e013f690 14122
78849248 14123const char *md_shortopts = "O::g::G:";
252b5132 14124
23fce1e3
NC
14125enum options
14126 {
14127 OPTION_MARCH = OPTION_MD_BASE,
14128 OPTION_MTUNE,
14129 OPTION_MIPS1,
14130 OPTION_MIPS2,
14131 OPTION_MIPS3,
14132 OPTION_MIPS4,
14133 OPTION_MIPS5,
14134 OPTION_MIPS32,
14135 OPTION_MIPS64,
14136 OPTION_MIPS32R2,
14137 OPTION_MIPS64R2,
14138 OPTION_MIPS16,
14139 OPTION_NO_MIPS16,
14140 OPTION_MIPS3D,
14141 OPTION_NO_MIPS3D,
14142 OPTION_MDMX,
14143 OPTION_NO_MDMX,
14144 OPTION_DSP,
14145 OPTION_NO_DSP,
14146 OPTION_MT,
14147 OPTION_NO_MT,
14148 OPTION_SMARTMIPS,
14149 OPTION_NO_SMARTMIPS,
14150 OPTION_DSPR2,
14151 OPTION_NO_DSPR2,
df58fc94
RS
14152 OPTION_MICROMIPS,
14153 OPTION_NO_MICROMIPS,
23fce1e3
NC
14154 OPTION_COMPAT_ARCH_BASE,
14155 OPTION_M4650,
14156 OPTION_NO_M4650,
14157 OPTION_M4010,
14158 OPTION_NO_M4010,
14159 OPTION_M4100,
14160 OPTION_NO_M4100,
14161 OPTION_M3900,
14162 OPTION_NO_M3900,
14163 OPTION_M7000_HILO_FIX,
6a32d874
CM
14164 OPTION_MNO_7000_HILO_FIX,
14165 OPTION_FIX_24K,
14166 OPTION_NO_FIX_24K,
c67a084a
NC
14167 OPTION_FIX_LOONGSON2F_JUMP,
14168 OPTION_NO_FIX_LOONGSON2F_JUMP,
14169 OPTION_FIX_LOONGSON2F_NOP,
14170 OPTION_NO_FIX_LOONGSON2F_NOP,
23fce1e3
NC
14171 OPTION_FIX_VR4120,
14172 OPTION_NO_FIX_VR4120,
14173 OPTION_FIX_VR4130,
14174 OPTION_NO_FIX_VR4130,
d954098f
DD
14175 OPTION_FIX_CN63XXP1,
14176 OPTION_NO_FIX_CN63XXP1,
23fce1e3
NC
14177 OPTION_TRAP,
14178 OPTION_BREAK,
14179 OPTION_EB,
14180 OPTION_EL,
14181 OPTION_FP32,
14182 OPTION_GP32,
14183 OPTION_CONSTRUCT_FLOATS,
14184 OPTION_NO_CONSTRUCT_FLOATS,
14185 OPTION_FP64,
14186 OPTION_GP64,
14187 OPTION_RELAX_BRANCH,
14188 OPTION_NO_RELAX_BRANCH,
14189 OPTION_MSHARED,
14190 OPTION_MNO_SHARED,
14191 OPTION_MSYM32,
14192 OPTION_MNO_SYM32,
14193 OPTION_SOFT_FLOAT,
14194 OPTION_HARD_FLOAT,
14195 OPTION_SINGLE_FLOAT,
14196 OPTION_DOUBLE_FLOAT,
14197 OPTION_32,
14198#ifdef OBJ_ELF
14199 OPTION_CALL_SHARED,
14200 OPTION_CALL_NONPIC,
14201 OPTION_NON_SHARED,
14202 OPTION_XGOT,
14203 OPTION_MABI,
14204 OPTION_N32,
14205 OPTION_64,
14206 OPTION_MDEBUG,
14207 OPTION_NO_MDEBUG,
14208 OPTION_PDR,
14209 OPTION_NO_PDR,
14210 OPTION_MVXWORKS_PIC,
14211#endif /* OBJ_ELF */
14212 OPTION_END_OF_ENUM
14213 };
14214
e972090a
NC
14215struct option md_longopts[] =
14216{
f9b4148d 14217 /* Options which specify architecture. */
f9b4148d 14218 {"march", required_argument, NULL, OPTION_MARCH},
f9b4148d 14219 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH
14220 {"mips0", no_argument, NULL, OPTION_MIPS1},
14221 {"mips1", no_argument, NULL, OPTION_MIPS1},
252b5132 14222 {"mips2", no_argument, NULL, OPTION_MIPS2},
252b5132 14223 {"mips3", no_argument, NULL, OPTION_MIPS3},
252b5132 14224 {"mips4", no_argument, NULL, OPTION_MIPS4},
ae948b86 14225 {"mips5", no_argument, NULL, OPTION_MIPS5},
ae948b86 14226 {"mips32", no_argument, NULL, OPTION_MIPS32},
ae948b86 14227 {"mips64", no_argument, NULL, OPTION_MIPS64},
f9b4148d 14228 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
5f74bc13 14229 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
f9b4148d
CD
14230
14231 /* Options which specify Application Specific Extensions (ASEs). */
f9b4148d 14232 {"mips16", no_argument, NULL, OPTION_MIPS16},
f9b4148d 14233 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
f9b4148d 14234 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
f9b4148d 14235 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
f9b4148d 14236 {"mdmx", no_argument, NULL, OPTION_MDMX},
f9b4148d 14237 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
74cd071d 14238 {"mdsp", no_argument, NULL, OPTION_DSP},
74cd071d 14239 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
ef2e4d86 14240 {"mmt", no_argument, NULL, OPTION_MT},
ef2e4d86 14241 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
e16bfa71 14242 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
e16bfa71 14243 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
8b082fb1 14244 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
8b082fb1 14245 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
df58fc94
RS
14246 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
14247 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
f9b4148d
CD
14248
14249 /* Old-style architecture options. Don't add more of these. */
f9b4148d 14250 {"m4650", no_argument, NULL, OPTION_M4650},
f9b4148d 14251 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
f9b4148d 14252 {"m4010", no_argument, NULL, OPTION_M4010},
f9b4148d 14253 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
f9b4148d 14254 {"m4100", no_argument, NULL, OPTION_M4100},
f9b4148d 14255 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
f9b4148d 14256 {"m3900", no_argument, NULL, OPTION_M3900},
f9b4148d
CD
14257 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
14258
14259 /* Options which enable bug fixes. */
f9b4148d 14260 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
f9b4148d
CD
14261 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14262 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
c67a084a
NC
14263 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
14264 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
14265 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
14266 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
d766e8ec
RS
14267 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
14268 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
7d8e00cf
RS
14269 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
14270 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
6a32d874
CM
14271 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
14272 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
d954098f
DD
14273 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
14274 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
f9b4148d
CD
14275
14276 /* Miscellaneous options. */
252b5132
RH
14277 {"trap", no_argument, NULL, OPTION_TRAP},
14278 {"no-break", no_argument, NULL, OPTION_TRAP},
252b5132
RH
14279 {"break", no_argument, NULL, OPTION_BREAK},
14280 {"no-trap", no_argument, NULL, OPTION_BREAK},
252b5132 14281 {"EB", no_argument, NULL, OPTION_EB},
252b5132 14282 {"EL", no_argument, NULL, OPTION_EL},
ae948b86 14283 {"mfp32", no_argument, NULL, OPTION_FP32},
c97ef257 14284 {"mgp32", no_argument, NULL, OPTION_GP32},
119d663a 14285 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
119d663a 14286 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
316f5878 14287 {"mfp64", no_argument, NULL, OPTION_FP64},
ae948b86 14288 {"mgp64", no_argument, NULL, OPTION_GP64},
4a6a3df4
AO
14289 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
14290 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
aa6975fb
ILT
14291 {"mshared", no_argument, NULL, OPTION_MSHARED},
14292 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
aed1a261
RS
14293 {"msym32", no_argument, NULL, OPTION_MSYM32},
14294 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
037b32b9
AN
14295 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
14296 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
037b32b9
AN
14297 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
14298 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
23fce1e3
NC
14299
14300 /* Strictly speaking this next option is ELF specific,
14301 but we allow it for other ports as well in order to
14302 make testing easier. */
14303 {"32", no_argument, NULL, OPTION_32},
037b32b9 14304
f9b4148d 14305 /* ELF-specific options. */
156c2f8b 14306#ifdef OBJ_ELF
156c2f8b
NC
14307 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
14308 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
861fb55a 14309 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
156c2f8b
NC
14310 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
14311 {"xgot", no_argument, NULL, OPTION_XGOT},
ae948b86 14312 {"mabi", required_argument, NULL, OPTION_MABI},
e013f690 14313 {"n32", no_argument, NULL, OPTION_N32},
156c2f8b 14314 {"64", no_argument, NULL, OPTION_64},
ecb4347a 14315 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
ecb4347a 14316 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
dcd410fe 14317 {"mpdr", no_argument, NULL, OPTION_PDR},
dcd410fe 14318 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
0a44bf69 14319 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
ae948b86 14320#endif /* OBJ_ELF */
f9b4148d 14321
252b5132
RH
14322 {NULL, no_argument, NULL, 0}
14323};
156c2f8b 14324size_t md_longopts_size = sizeof (md_longopts);
252b5132 14325
316f5878
RS
14326/* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14327 NEW_VALUE. Warn if another value was already specified. Note:
14328 we have to defer parsing the -march and -mtune arguments in order
14329 to handle 'from-abi' correctly, since the ABI might be specified
14330 in a later argument. */
14331
14332static void
17a2f251 14333mips_set_option_string (const char **string_ptr, const char *new_value)
316f5878
RS
14334{
14335 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14336 as_warn (_("A different %s was already specified, is now %s"),
14337 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14338 new_value);
14339
14340 *string_ptr = new_value;
14341}
14342
252b5132 14343int
17a2f251 14344md_parse_option (int c, char *arg)
252b5132
RH
14345{
14346 switch (c)
14347 {
119d663a
NC
14348 case OPTION_CONSTRUCT_FLOATS:
14349 mips_disable_float_construction = 0;
14350 break;
bdaaa2e1 14351
119d663a
NC
14352 case OPTION_NO_CONSTRUCT_FLOATS:
14353 mips_disable_float_construction = 1;
14354 break;
bdaaa2e1 14355
252b5132
RH
14356 case OPTION_TRAP:
14357 mips_trap = 1;
14358 break;
14359
14360 case OPTION_BREAK:
14361 mips_trap = 0;
14362 break;
14363
14364 case OPTION_EB:
14365 target_big_endian = 1;
14366 break;
14367
14368 case OPTION_EL:
14369 target_big_endian = 0;
14370 break;
14371
14372 case 'O':
4ffff32f
TS
14373 if (arg == NULL)
14374 mips_optimize = 1;
14375 else if (arg[0] == '0')
14376 mips_optimize = 0;
14377 else if (arg[0] == '1')
252b5132
RH
14378 mips_optimize = 1;
14379 else
14380 mips_optimize = 2;
14381 break;
14382
14383 case 'g':
14384 if (arg == NULL)
14385 mips_debug = 2;
14386 else
14387 mips_debug = atoi (arg);
252b5132
RH
14388 break;
14389
14390 case OPTION_MIPS1:
316f5878 14391 file_mips_isa = ISA_MIPS1;
252b5132
RH
14392 break;
14393
14394 case OPTION_MIPS2:
316f5878 14395 file_mips_isa = ISA_MIPS2;
252b5132
RH
14396 break;
14397
14398 case OPTION_MIPS3:
316f5878 14399 file_mips_isa = ISA_MIPS3;
252b5132
RH
14400 break;
14401
14402 case OPTION_MIPS4:
316f5878 14403 file_mips_isa = ISA_MIPS4;
e7af610e
NC
14404 break;
14405
84ea6cf2 14406 case OPTION_MIPS5:
316f5878 14407 file_mips_isa = ISA_MIPS5;
84ea6cf2
NC
14408 break;
14409
e7af610e 14410 case OPTION_MIPS32:
316f5878 14411 file_mips_isa = ISA_MIPS32;
252b5132
RH
14412 break;
14413
af7ee8bf
CD
14414 case OPTION_MIPS32R2:
14415 file_mips_isa = ISA_MIPS32R2;
14416 break;
14417
5f74bc13
CD
14418 case OPTION_MIPS64R2:
14419 file_mips_isa = ISA_MIPS64R2;
14420 break;
14421
84ea6cf2 14422 case OPTION_MIPS64:
316f5878 14423 file_mips_isa = ISA_MIPS64;
84ea6cf2
NC
14424 break;
14425
ec68c924 14426 case OPTION_MTUNE:
316f5878
RS
14427 mips_set_option_string (&mips_tune_string, arg);
14428 break;
ec68c924 14429
316f5878
RS
14430 case OPTION_MARCH:
14431 mips_set_option_string (&mips_arch_string, arg);
252b5132
RH
14432 break;
14433
14434 case OPTION_M4650:
316f5878
RS
14435 mips_set_option_string (&mips_arch_string, "4650");
14436 mips_set_option_string (&mips_tune_string, "4650");
252b5132
RH
14437 break;
14438
14439 case OPTION_NO_M4650:
14440 break;
14441
14442 case OPTION_M4010:
316f5878
RS
14443 mips_set_option_string (&mips_arch_string, "4010");
14444 mips_set_option_string (&mips_tune_string, "4010");
252b5132
RH
14445 break;
14446
14447 case OPTION_NO_M4010:
14448 break;
14449
14450 case OPTION_M4100:
316f5878
RS
14451 mips_set_option_string (&mips_arch_string, "4100");
14452 mips_set_option_string (&mips_tune_string, "4100");
252b5132
RH
14453 break;
14454
14455 case OPTION_NO_M4100:
14456 break;
14457
252b5132 14458 case OPTION_M3900:
316f5878
RS
14459 mips_set_option_string (&mips_arch_string, "3900");
14460 mips_set_option_string (&mips_tune_string, "3900");
252b5132 14461 break;
bdaaa2e1 14462
252b5132
RH
14463 case OPTION_NO_M3900:
14464 break;
14465
deec1734
CD
14466 case OPTION_MDMX:
14467 mips_opts.ase_mdmx = 1;
14468 break;
14469
14470 case OPTION_NO_MDMX:
14471 mips_opts.ase_mdmx = 0;
14472 break;
14473
74cd071d
CF
14474 case OPTION_DSP:
14475 mips_opts.ase_dsp = 1;
8b082fb1 14476 mips_opts.ase_dspr2 = 0;
74cd071d
CF
14477 break;
14478
14479 case OPTION_NO_DSP:
8b082fb1
TS
14480 mips_opts.ase_dsp = 0;
14481 mips_opts.ase_dspr2 = 0;
14482 break;
14483
14484 case OPTION_DSPR2:
14485 mips_opts.ase_dspr2 = 1;
14486 mips_opts.ase_dsp = 1;
14487 break;
14488
14489 case OPTION_NO_DSPR2:
14490 mips_opts.ase_dspr2 = 0;
74cd071d
CF
14491 mips_opts.ase_dsp = 0;
14492 break;
14493
ef2e4d86
CF
14494 case OPTION_MT:
14495 mips_opts.ase_mt = 1;
14496 break;
14497
14498 case OPTION_NO_MT:
14499 mips_opts.ase_mt = 0;
14500 break;
14501
df58fc94
RS
14502 case OPTION_MICROMIPS:
14503 if (mips_opts.mips16 == 1)
14504 {
14505 as_bad (_("-mmicromips cannot be used with -mips16"));
14506 return 0;
14507 }
14508 mips_opts.micromips = 1;
14509 mips_no_prev_insn ();
14510 break;
14511
14512 case OPTION_NO_MICROMIPS:
14513 mips_opts.micromips = 0;
14514 mips_no_prev_insn ();
14515 break;
14516
252b5132 14517 case OPTION_MIPS16:
df58fc94
RS
14518 if (mips_opts.micromips == 1)
14519 {
14520 as_bad (_("-mips16 cannot be used with -micromips"));
14521 return 0;
14522 }
252b5132 14523 mips_opts.mips16 = 1;
7d10b47d 14524 mips_no_prev_insn ();
252b5132
RH
14525 break;
14526
14527 case OPTION_NO_MIPS16:
14528 mips_opts.mips16 = 0;
7d10b47d 14529 mips_no_prev_insn ();
252b5132
RH
14530 break;
14531
1f25f5d3
CD
14532 case OPTION_MIPS3D:
14533 mips_opts.ase_mips3d = 1;
14534 break;
14535
14536 case OPTION_NO_MIPS3D:
14537 mips_opts.ase_mips3d = 0;
14538 break;
14539
e16bfa71
TS
14540 case OPTION_SMARTMIPS:
14541 mips_opts.ase_smartmips = 1;
14542 break;
14543
14544 case OPTION_NO_SMARTMIPS:
14545 mips_opts.ase_smartmips = 0;
14546 break;
14547
6a32d874
CM
14548 case OPTION_FIX_24K:
14549 mips_fix_24k = 1;
14550 break;
14551
14552 case OPTION_NO_FIX_24K:
14553 mips_fix_24k = 0;
14554 break;
14555
c67a084a
NC
14556 case OPTION_FIX_LOONGSON2F_JUMP:
14557 mips_fix_loongson2f_jump = TRUE;
14558 break;
14559
14560 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14561 mips_fix_loongson2f_jump = FALSE;
14562 break;
14563
14564 case OPTION_FIX_LOONGSON2F_NOP:
14565 mips_fix_loongson2f_nop = TRUE;
14566 break;
14567
14568 case OPTION_NO_FIX_LOONGSON2F_NOP:
14569 mips_fix_loongson2f_nop = FALSE;
14570 break;
14571
d766e8ec
RS
14572 case OPTION_FIX_VR4120:
14573 mips_fix_vr4120 = 1;
60b63b72
RS
14574 break;
14575
d766e8ec
RS
14576 case OPTION_NO_FIX_VR4120:
14577 mips_fix_vr4120 = 0;
60b63b72
RS
14578 break;
14579
7d8e00cf
RS
14580 case OPTION_FIX_VR4130:
14581 mips_fix_vr4130 = 1;
14582 break;
14583
14584 case OPTION_NO_FIX_VR4130:
14585 mips_fix_vr4130 = 0;
14586 break;
14587
d954098f
DD
14588 case OPTION_FIX_CN63XXP1:
14589 mips_fix_cn63xxp1 = TRUE;
14590 break;
14591
14592 case OPTION_NO_FIX_CN63XXP1:
14593 mips_fix_cn63xxp1 = FALSE;
14594 break;
14595
4a6a3df4
AO
14596 case OPTION_RELAX_BRANCH:
14597 mips_relax_branch = 1;
14598 break;
14599
14600 case OPTION_NO_RELAX_BRANCH:
14601 mips_relax_branch = 0;
14602 break;
14603
aa6975fb
ILT
14604 case OPTION_MSHARED:
14605 mips_in_shared = TRUE;
14606 break;
14607
14608 case OPTION_MNO_SHARED:
14609 mips_in_shared = FALSE;
14610 break;
14611
aed1a261
RS
14612 case OPTION_MSYM32:
14613 mips_opts.sym32 = TRUE;
14614 break;
14615
14616 case OPTION_MNO_SYM32:
14617 mips_opts.sym32 = FALSE;
14618 break;
14619
0f074f60 14620#ifdef OBJ_ELF
252b5132
RH
14621 /* When generating ELF code, we permit -KPIC and -call_shared to
14622 select SVR4_PIC, and -non_shared to select no PIC. This is
14623 intended to be compatible with Irix 5. */
14624 case OPTION_CALL_SHARED:
f43abd2b 14625 if (!IS_ELF)
252b5132
RH
14626 {
14627 as_bad (_("-call_shared is supported only for ELF format"));
14628 return 0;
14629 }
14630 mips_pic = SVR4_PIC;
143d77c5 14631 mips_abicalls = TRUE;
252b5132
RH
14632 break;
14633
861fb55a
DJ
14634 case OPTION_CALL_NONPIC:
14635 if (!IS_ELF)
14636 {
14637 as_bad (_("-call_nonpic is supported only for ELF format"));
14638 return 0;
14639 }
14640 mips_pic = NO_PIC;
14641 mips_abicalls = TRUE;
14642 break;
14643
252b5132 14644 case OPTION_NON_SHARED:
f43abd2b 14645 if (!IS_ELF)
252b5132
RH
14646 {
14647 as_bad (_("-non_shared is supported only for ELF format"));
14648 return 0;
14649 }
14650 mips_pic = NO_PIC;
143d77c5 14651 mips_abicalls = FALSE;
252b5132
RH
14652 break;
14653
44075ae2
TS
14654 /* The -xgot option tells the assembler to use 32 bit offsets
14655 when accessing the got in SVR4_PIC mode. It is for Irix
252b5132
RH
14656 compatibility. */
14657 case OPTION_XGOT:
14658 mips_big_got = 1;
14659 break;
0f074f60 14660#endif /* OBJ_ELF */
252b5132
RH
14661
14662 case 'G':
6caf9ef4
TS
14663 g_switch_value = atoi (arg);
14664 g_switch_seen = 1;
252b5132
RH
14665 break;
14666
34ba82a8
TS
14667 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14668 and -mabi=64. */
252b5132 14669 case OPTION_32:
23fce1e3
NC
14670 if (IS_ELF)
14671 mips_abi = O32_ABI;
14672 /* We silently ignore -32 for non-ELF targets. This greatly
14673 simplifies the construction of the MIPS GAS test cases. */
252b5132
RH
14674 break;
14675
23fce1e3 14676#ifdef OBJ_ELF
e013f690 14677 case OPTION_N32:
f43abd2b 14678 if (!IS_ELF)
34ba82a8
TS
14679 {
14680 as_bad (_("-n32 is supported for ELF format only"));
14681 return 0;
14682 }
316f5878 14683 mips_abi = N32_ABI;
e013f690 14684 break;
252b5132 14685
e013f690 14686 case OPTION_64:
f43abd2b 14687 if (!IS_ELF)
34ba82a8
TS
14688 {
14689 as_bad (_("-64 is supported for ELF format only"));
14690 return 0;
14691 }
316f5878 14692 mips_abi = N64_ABI;
f43abd2b 14693 if (!support_64bit_objects())
e013f690 14694 as_fatal (_("No compiled in support for 64 bit object file format"));
252b5132 14695 break;
ae948b86 14696#endif /* OBJ_ELF */
252b5132 14697
c97ef257 14698 case OPTION_GP32:
a325df1d 14699 file_mips_gp32 = 1;
c97ef257
AH
14700 break;
14701
14702 case OPTION_GP64:
a325df1d 14703 file_mips_gp32 = 0;
c97ef257 14704 break;
252b5132 14705
ca4e0257 14706 case OPTION_FP32:
a325df1d 14707 file_mips_fp32 = 1;
316f5878
RS
14708 break;
14709
14710 case OPTION_FP64:
14711 file_mips_fp32 = 0;
ca4e0257
RS
14712 break;
14713
037b32b9
AN
14714 case OPTION_SINGLE_FLOAT:
14715 file_mips_single_float = 1;
14716 break;
14717
14718 case OPTION_DOUBLE_FLOAT:
14719 file_mips_single_float = 0;
14720 break;
14721
14722 case OPTION_SOFT_FLOAT:
14723 file_mips_soft_float = 1;
14724 break;
14725
14726 case OPTION_HARD_FLOAT:
14727 file_mips_soft_float = 0;
14728 break;
14729
ae948b86 14730#ifdef OBJ_ELF
252b5132 14731 case OPTION_MABI:
f43abd2b 14732 if (!IS_ELF)
34ba82a8
TS
14733 {
14734 as_bad (_("-mabi is supported for ELF format only"));
14735 return 0;
14736 }
e013f690 14737 if (strcmp (arg, "32") == 0)
316f5878 14738 mips_abi = O32_ABI;
e013f690 14739 else if (strcmp (arg, "o64") == 0)
316f5878 14740 mips_abi = O64_ABI;
e013f690 14741 else if (strcmp (arg, "n32") == 0)
316f5878 14742 mips_abi = N32_ABI;
e013f690
TS
14743 else if (strcmp (arg, "64") == 0)
14744 {
316f5878 14745 mips_abi = N64_ABI;
e013f690
TS
14746 if (! support_64bit_objects())
14747 as_fatal (_("No compiled in support for 64 bit object file "
14748 "format"));
14749 }
14750 else if (strcmp (arg, "eabi") == 0)
316f5878 14751 mips_abi = EABI_ABI;
e013f690 14752 else
da0e507f
TS
14753 {
14754 as_fatal (_("invalid abi -mabi=%s"), arg);
14755 return 0;
14756 }
252b5132 14757 break;
e013f690 14758#endif /* OBJ_ELF */
252b5132 14759
6b76fefe 14760 case OPTION_M7000_HILO_FIX:
b34976b6 14761 mips_7000_hilo_fix = TRUE;
6b76fefe
CM
14762 break;
14763
9ee72ff1 14764 case OPTION_MNO_7000_HILO_FIX:
b34976b6 14765 mips_7000_hilo_fix = FALSE;
6b76fefe
CM
14766 break;
14767
ecb4347a
DJ
14768#ifdef OBJ_ELF
14769 case OPTION_MDEBUG:
b34976b6 14770 mips_flag_mdebug = TRUE;
ecb4347a
DJ
14771 break;
14772
14773 case OPTION_NO_MDEBUG:
b34976b6 14774 mips_flag_mdebug = FALSE;
ecb4347a 14775 break;
dcd410fe
RO
14776
14777 case OPTION_PDR:
14778 mips_flag_pdr = TRUE;
14779 break;
14780
14781 case OPTION_NO_PDR:
14782 mips_flag_pdr = FALSE;
14783 break;
0a44bf69
RS
14784
14785 case OPTION_MVXWORKS_PIC:
14786 mips_pic = VXWORKS_PIC;
14787 break;
ecb4347a
DJ
14788#endif /* OBJ_ELF */
14789
252b5132
RH
14790 default:
14791 return 0;
14792 }
14793
c67a084a
NC
14794 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
14795
252b5132
RH
14796 return 1;
14797}
316f5878
RS
14798\f
14799/* Set up globals to generate code for the ISA or processor
14800 described by INFO. */
252b5132 14801
252b5132 14802static void
17a2f251 14803mips_set_architecture (const struct mips_cpu_info *info)
252b5132 14804{
316f5878 14805 if (info != 0)
252b5132 14806 {
fef14a42
TS
14807 file_mips_arch = info->cpu;
14808 mips_opts.arch = info->cpu;
316f5878 14809 mips_opts.isa = info->isa;
252b5132 14810 }
252b5132
RH
14811}
14812
252b5132 14813
316f5878 14814/* Likewise for tuning. */
252b5132 14815
316f5878 14816static void
17a2f251 14817mips_set_tune (const struct mips_cpu_info *info)
316f5878
RS
14818{
14819 if (info != 0)
fef14a42 14820 mips_tune = info->cpu;
316f5878 14821}
80cc45a5 14822
34ba82a8 14823
252b5132 14824void
17a2f251 14825mips_after_parse_args (void)
e9670677 14826{
fef14a42
TS
14827 const struct mips_cpu_info *arch_info = 0;
14828 const struct mips_cpu_info *tune_info = 0;
14829
e9670677 14830 /* GP relative stuff not working for PE */
6caf9ef4 14831 if (strncmp (TARGET_OS, "pe", 2) == 0)
e9670677 14832 {
6caf9ef4 14833 if (g_switch_seen && g_switch_value != 0)
e9670677
MR
14834 as_bad (_("-G not supported in this configuration."));
14835 g_switch_value = 0;
14836 }
14837
cac012d6
AO
14838 if (mips_abi == NO_ABI)
14839 mips_abi = MIPS_DEFAULT_ABI;
14840
22923709
RS
14841 /* The following code determines the architecture and register size.
14842 Similar code was added to GCC 3.3 (see override_options() in
14843 config/mips/mips.c). The GAS and GCC code should be kept in sync
14844 as much as possible. */
e9670677 14845
316f5878 14846 if (mips_arch_string != 0)
fef14a42 14847 arch_info = mips_parse_cpu ("-march", mips_arch_string);
e9670677 14848
316f5878 14849 if (file_mips_isa != ISA_UNKNOWN)
e9670677 14850 {
316f5878 14851 /* Handle -mipsN. At this point, file_mips_isa contains the
fef14a42 14852 ISA level specified by -mipsN, while arch_info->isa contains
316f5878 14853 the -march selection (if any). */
fef14a42 14854 if (arch_info != 0)
e9670677 14855 {
316f5878
RS
14856 /* -march takes precedence over -mipsN, since it is more descriptive.
14857 There's no harm in specifying both as long as the ISA levels
14858 are the same. */
fef14a42 14859 if (file_mips_isa != arch_info->isa)
316f5878
RS
14860 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
14861 mips_cpu_info_from_isa (file_mips_isa)->name,
fef14a42 14862 mips_cpu_info_from_isa (arch_info->isa)->name);
e9670677 14863 }
316f5878 14864 else
fef14a42 14865 arch_info = mips_cpu_info_from_isa (file_mips_isa);
e9670677
MR
14866 }
14867
fef14a42
TS
14868 if (arch_info == 0)
14869 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
e9670677 14870
fef14a42 14871 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
20203fb9 14872 as_bad (_("-march=%s is not compatible with the selected ABI"),
fef14a42
TS
14873 arch_info->name);
14874
14875 mips_set_architecture (arch_info);
14876
14877 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
14878 if (mips_tune_string != 0)
14879 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
e9670677 14880
fef14a42
TS
14881 if (tune_info == 0)
14882 mips_set_tune (arch_info);
14883 else
14884 mips_set_tune (tune_info);
e9670677 14885
316f5878 14886 if (file_mips_gp32 >= 0)
e9670677 14887 {
316f5878
RS
14888 /* The user specified the size of the integer registers. Make sure
14889 it agrees with the ABI and ISA. */
14890 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
14891 as_bad (_("-mgp64 used with a 32-bit processor"));
14892 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
14893 as_bad (_("-mgp32 used with a 64-bit ABI"));
14894 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
14895 as_bad (_("-mgp64 used with a 32-bit ABI"));
e9670677
MR
14896 }
14897 else
14898 {
316f5878
RS
14899 /* Infer the integer register size from the ABI and processor.
14900 Restrict ourselves to 32-bit registers if that's all the
14901 processor has, or if the ABI cannot handle 64-bit registers. */
14902 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
14903 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
e9670677
MR
14904 }
14905
ad3fea08
TS
14906 switch (file_mips_fp32)
14907 {
14908 default:
14909 case -1:
14910 /* No user specified float register size.
14911 ??? GAS treats single-float processors as though they had 64-bit
14912 float registers (although it complains when double-precision
14913 instructions are used). As things stand, saying they have 32-bit
14914 registers would lead to spurious "register must be even" messages.
14915 So here we assume float registers are never smaller than the
14916 integer ones. */
14917 if (file_mips_gp32 == 0)
14918 /* 64-bit integer registers implies 64-bit float registers. */
14919 file_mips_fp32 = 0;
14920 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
14921 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
14922 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
14923 file_mips_fp32 = 0;
14924 else
14925 /* 32-bit float registers. */
14926 file_mips_fp32 = 1;
14927 break;
14928
14929 /* The user specified the size of the float registers. Check if it
14930 agrees with the ABI and ISA. */
14931 case 0:
14932 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
14933 as_bad (_("-mfp64 used with a 32-bit fpu"));
14934 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
14935 && !ISA_HAS_MXHC1 (mips_opts.isa))
14936 as_warn (_("-mfp64 used with a 32-bit ABI"));
14937 break;
14938 case 1:
14939 if (ABI_NEEDS_64BIT_REGS (mips_abi))
14940 as_warn (_("-mfp32 used with a 64-bit ABI"));
14941 break;
14942 }
e9670677 14943
316f5878 14944 /* End of GCC-shared inference code. */
e9670677 14945
17a2f251
TS
14946 /* This flag is set when we have a 64-bit capable CPU but use only
14947 32-bit wide registers. Note that EABI does not use it. */
14948 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
14949 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
14950 || mips_abi == O32_ABI))
316f5878 14951 mips_32bitmode = 1;
e9670677
MR
14952
14953 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
14954 as_bad (_("trap exception not supported at ISA 1"));
14955
e9670677
MR
14956 /* If the selected architecture includes support for ASEs, enable
14957 generation of code for them. */
a4672219 14958 if (mips_opts.mips16 == -1)
fef14a42 14959 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
df58fc94
RS
14960 if (mips_opts.micromips == -1)
14961 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
ffdefa66 14962 if (mips_opts.ase_mips3d == -1)
65263ce3 14963 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
ad3fea08
TS
14964 && file_mips_fp32 == 0) ? 1 : 0;
14965 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
14966 as_bad (_("-mfp32 used with -mips3d"));
14967
ffdefa66 14968 if (mips_opts.ase_mdmx == -1)
65263ce3 14969 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
ad3fea08
TS
14970 && file_mips_fp32 == 0) ? 1 : 0;
14971 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
14972 as_bad (_("-mfp32 used with -mdmx"));
14973
14974 if (mips_opts.ase_smartmips == -1)
14975 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
14976 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
20203fb9
NC
14977 as_warn (_("%s ISA does not support SmartMIPS"),
14978 mips_cpu_info_from_isa (mips_opts.isa)->name);
ad3fea08 14979
74cd071d 14980 if (mips_opts.ase_dsp == -1)
ad3fea08
TS
14981 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
14982 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
20203fb9
NC
14983 as_warn (_("%s ISA does not support DSP ASE"),
14984 mips_cpu_info_from_isa (mips_opts.isa)->name);
ad3fea08 14985
8b082fb1
TS
14986 if (mips_opts.ase_dspr2 == -1)
14987 {
14988 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
14989 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
14990 }
14991 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
20203fb9
NC
14992 as_warn (_("%s ISA does not support DSP R2 ASE"),
14993 mips_cpu_info_from_isa (mips_opts.isa)->name);
8b082fb1 14994
ef2e4d86 14995 if (mips_opts.ase_mt == -1)
ad3fea08
TS
14996 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
14997 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
20203fb9
NC
14998 as_warn (_("%s ISA does not support MT ASE"),
14999 mips_cpu_info_from_isa (mips_opts.isa)->name);
e9670677 15000
e9670677 15001 file_mips_isa = mips_opts.isa;
e9670677
MR
15002 file_ase_mips3d = mips_opts.ase_mips3d;
15003 file_ase_mdmx = mips_opts.ase_mdmx;
e16bfa71 15004 file_ase_smartmips = mips_opts.ase_smartmips;
74cd071d 15005 file_ase_dsp = mips_opts.ase_dsp;
8b082fb1 15006 file_ase_dspr2 = mips_opts.ase_dspr2;
ef2e4d86 15007 file_ase_mt = mips_opts.ase_mt;
e9670677
MR
15008 mips_opts.gp32 = file_mips_gp32;
15009 mips_opts.fp32 = file_mips_fp32;
037b32b9
AN
15010 mips_opts.soft_float = file_mips_soft_float;
15011 mips_opts.single_float = file_mips_single_float;
e9670677 15012
ecb4347a
DJ
15013 if (mips_flag_mdebug < 0)
15014 {
15015#ifdef OBJ_MAYBE_ECOFF
15016 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
15017 mips_flag_mdebug = 1;
15018 else
15019#endif /* OBJ_MAYBE_ECOFF */
15020 mips_flag_mdebug = 0;
15021 }
e9670677
MR
15022}
15023\f
15024void
17a2f251 15025mips_init_after_args (void)
252b5132
RH
15026{
15027 /* initialize opcodes */
15028 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
beae10d5 15029 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
252b5132
RH
15030}
15031
15032long
17a2f251 15033md_pcrel_from (fixS *fixP)
252b5132 15034{
a7ebbfdf
TS
15035 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15036 switch (fixP->fx_r_type)
15037 {
df58fc94
RS
15038 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15039 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15040 /* Return the address of the delay slot. */
15041 return addr + 2;
15042
15043 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15044 case BFD_RELOC_MICROMIPS_JMP:
a7ebbfdf
TS
15045 case BFD_RELOC_16_PCREL_S2:
15046 case BFD_RELOC_MIPS_JMP:
15047 /* Return the address of the delay slot. */
15048 return addr + 4;
df58fc94 15049
a7ebbfdf 15050 default:
58ea3d6a 15051 /* We have no relocation type for PC relative MIPS16 instructions. */
64817874
TS
15052 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
15053 as_bad_where (fixP->fx_file, fixP->fx_line,
15054 _("PC relative MIPS16 instruction references a different section"));
a7ebbfdf
TS
15055 return addr;
15056 }
252b5132
RH
15057}
15058
252b5132
RH
15059/* This is called before the symbol table is processed. In order to
15060 work with gcc when using mips-tfile, we must keep all local labels.
15061 However, in other cases, we want to discard them. If we were
15062 called with -g, but we didn't see any debugging information, it may
15063 mean that gcc is smuggling debugging information through to
15064 mips-tfile, in which case we must generate all local labels. */
15065
15066void
17a2f251 15067mips_frob_file_before_adjust (void)
252b5132
RH
15068{
15069#ifndef NO_ECOFF_DEBUGGING
15070 if (ECOFF_DEBUGGING
15071 && mips_debug != 0
15072 && ! ecoff_debugging_seen)
15073 flag_keep_locals = 1;
15074#endif
15075}
15076
3b91255e 15077/* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
55cf6793 15078 the corresponding LO16 reloc. This is called before md_apply_fix and
3b91255e
RS
15079 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15080 relocation operators.
15081
15082 For our purposes, a %lo() expression matches a %got() or %hi()
15083 expression if:
15084
15085 (a) it refers to the same symbol; and
15086 (b) the offset applied in the %lo() expression is no lower than
15087 the offset applied in the %got() or %hi().
15088
15089 (b) allows us to cope with code like:
15090
15091 lui $4,%hi(foo)
15092 lh $4,%lo(foo+2)($4)
15093
15094 ...which is legal on RELA targets, and has a well-defined behaviour
15095 if the user knows that adding 2 to "foo" will not induce a carry to
15096 the high 16 bits.
15097
15098 When several %lo()s match a particular %got() or %hi(), we use the
15099 following rules to distinguish them:
15100
15101 (1) %lo()s with smaller offsets are a better match than %lo()s with
15102 higher offsets.
15103
15104 (2) %lo()s with no matching %got() or %hi() are better than those
15105 that already have a matching %got() or %hi().
15106
15107 (3) later %lo()s are better than earlier %lo()s.
15108
15109 These rules are applied in order.
15110
15111 (1) means, among other things, that %lo()s with identical offsets are
15112 chosen if they exist.
15113
15114 (2) means that we won't associate several high-part relocations with
15115 the same low-part relocation unless there's no alternative. Having
15116 several high parts for the same low part is a GNU extension; this rule
15117 allows careful users to avoid it.
15118
15119 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15120 with the last high-part relocation being at the front of the list.
15121 It therefore makes sense to choose the last matching low-part
15122 relocation, all other things being equal. It's also easier
15123 to code that way. */
252b5132
RH
15124
15125void
17a2f251 15126mips_frob_file (void)
252b5132
RH
15127{
15128 struct mips_hi_fixup *l;
35903be0 15129 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
252b5132
RH
15130
15131 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15132 {
15133 segment_info_type *seginfo;
3b91255e
RS
15134 bfd_boolean matched_lo_p;
15135 fixS **hi_pos, **lo_pos, **pos;
252b5132 15136
9c2799c2 15137 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
252b5132 15138
5919d012
RS
15139 /* If a GOT16 relocation turns out to be against a global symbol,
15140 there isn't supposed to be a matching LO. */
738e5348 15141 if (got16_reloc_p (l->fixp->fx_r_type)
5919d012
RS
15142 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
15143 continue;
15144
15145 /* Check quickly whether the next fixup happens to be a matching %lo. */
15146 if (fixup_has_matching_lo_p (l->fixp))
252b5132
RH
15147 continue;
15148
252b5132 15149 seginfo = seg_info (l->seg);
252b5132 15150
3b91255e
RS
15151 /* Set HI_POS to the position of this relocation in the chain.
15152 Set LO_POS to the position of the chosen low-part relocation.
15153 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15154 relocation that matches an immediately-preceding high-part
15155 relocation. */
15156 hi_pos = NULL;
15157 lo_pos = NULL;
15158 matched_lo_p = FALSE;
738e5348 15159 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
35903be0 15160
3b91255e
RS
15161 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15162 {
15163 if (*pos == l->fixp)
15164 hi_pos = pos;
15165
35903be0 15166 if ((*pos)->fx_r_type == looking_for_rtype
30cfc97a 15167 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
3b91255e
RS
15168 && (*pos)->fx_offset >= l->fixp->fx_offset
15169 && (lo_pos == NULL
15170 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15171 || (!matched_lo_p
15172 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15173 lo_pos = pos;
15174
15175 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15176 && fixup_has_matching_lo_p (*pos));
15177 }
15178
15179 /* If we found a match, remove the high-part relocation from its
15180 current position and insert it before the low-part relocation.
15181 Make the offsets match so that fixup_has_matching_lo_p()
15182 will return true.
15183
15184 We don't warn about unmatched high-part relocations since some
15185 versions of gcc have been known to emit dead "lui ...%hi(...)"
15186 instructions. */
15187 if (lo_pos != NULL)
15188 {
15189 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15190 if (l->fixp->fx_next != *lo_pos)
252b5132 15191 {
3b91255e
RS
15192 *hi_pos = l->fixp->fx_next;
15193 l->fixp->fx_next = *lo_pos;
15194 *lo_pos = l->fixp;
252b5132 15195 }
252b5132
RH
15196 }
15197 }
15198}
15199
3e722fb5 15200/* We may have combined relocations without symbols in the N32/N64 ABI.
f6688943 15201 We have to prevent gas from dropping them. */
252b5132 15202
252b5132 15203int
17a2f251 15204mips_force_relocation (fixS *fixp)
252b5132 15205{
ae6063d4 15206 if (generic_force_reloc (fixp))
252b5132
RH
15207 return 1;
15208
df58fc94
RS
15209 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15210 so that the linker relaxation can update targets. */
15211 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15212 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15213 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15214 return 1;
15215
f6688943
TS
15216 if (HAVE_NEWABI
15217 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
15218 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
738e5348
RS
15219 || hi16_reloc_p (fixp->fx_r_type)
15220 || lo16_reloc_p (fixp->fx_r_type)))
f6688943
TS
15221 return 1;
15222
3e722fb5 15223 return 0;
252b5132
RH
15224}
15225
15226/* Apply a fixup to the object file. */
15227
94f592af 15228void
55cf6793 15229md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 15230{
874e8986 15231 bfd_byte *buf;
98aa84af 15232 long insn;
a7ebbfdf 15233 reloc_howto_type *howto;
252b5132 15234
a7ebbfdf
TS
15235 /* We ignore generic BFD relocations we don't know about. */
15236 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15237 if (! howto)
15238 return;
65551fa4 15239
df58fc94
RS
15240 gas_assert (fixP->fx_size == 2
15241 || fixP->fx_size == 4
90ecf173
MR
15242 || fixP->fx_r_type == BFD_RELOC_16
15243 || fixP->fx_r_type == BFD_RELOC_64
15244 || fixP->fx_r_type == BFD_RELOC_CTOR
15245 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
df58fc94 15246 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
90ecf173
MR
15247 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15248 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15249 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
252b5132 15250
a7ebbfdf 15251 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
252b5132 15252
df58fc94
RS
15253 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
15254 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15255 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15256 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
b1dca8ee
RS
15257
15258 /* Don't treat parts of a composite relocation as done. There are two
15259 reasons for this:
15260
15261 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15262 should nevertheless be emitted if the first part is.
15263
15264 (2) In normal usage, composite relocations are never assembly-time
15265 constants. The easiest way of dealing with the pathological
15266 exceptions is to generate a relocation against STN_UNDEF and
15267 leave everything up to the linker. */
3994f87e 15268 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
252b5132
RH
15269 fixP->fx_done = 1;
15270
15271 switch (fixP->fx_r_type)
15272 {
3f98094e
DJ
15273 case BFD_RELOC_MIPS_TLS_GD:
15274 case BFD_RELOC_MIPS_TLS_LDM:
741d6ea8
JM
15275 case BFD_RELOC_MIPS_TLS_DTPREL32:
15276 case BFD_RELOC_MIPS_TLS_DTPREL64:
3f98094e
DJ
15277 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15278 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15279 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15280 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15281 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
df58fc94
RS
15282 case BFD_RELOC_MICROMIPS_TLS_GD:
15283 case BFD_RELOC_MICROMIPS_TLS_LDM:
15284 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15285 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15286 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15287 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15288 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
3f98094e
DJ
15289 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15290 /* fall through */
15291
252b5132 15292 case BFD_RELOC_MIPS_JMP:
e369bcce
TS
15293 case BFD_RELOC_MIPS_SHIFT5:
15294 case BFD_RELOC_MIPS_SHIFT6:
15295 case BFD_RELOC_MIPS_GOT_DISP:
15296 case BFD_RELOC_MIPS_GOT_PAGE:
15297 case BFD_RELOC_MIPS_GOT_OFST:
15298 case BFD_RELOC_MIPS_SUB:
15299 case BFD_RELOC_MIPS_INSERT_A:
15300 case BFD_RELOC_MIPS_INSERT_B:
15301 case BFD_RELOC_MIPS_DELETE:
15302 case BFD_RELOC_MIPS_HIGHEST:
15303 case BFD_RELOC_MIPS_HIGHER:
15304 case BFD_RELOC_MIPS_SCN_DISP:
15305 case BFD_RELOC_MIPS_REL16:
15306 case BFD_RELOC_MIPS_RELGOT:
15307 case BFD_RELOC_MIPS_JALR:
252b5132
RH
15308 case BFD_RELOC_HI16:
15309 case BFD_RELOC_HI16_S:
cdf6fd85 15310 case BFD_RELOC_GPREL16:
252b5132
RH
15311 case BFD_RELOC_MIPS_LITERAL:
15312 case BFD_RELOC_MIPS_CALL16:
15313 case BFD_RELOC_MIPS_GOT16:
cdf6fd85 15314 case BFD_RELOC_GPREL32:
252b5132
RH
15315 case BFD_RELOC_MIPS_GOT_HI16:
15316 case BFD_RELOC_MIPS_GOT_LO16:
15317 case BFD_RELOC_MIPS_CALL_HI16:
15318 case BFD_RELOC_MIPS_CALL_LO16:
15319 case BFD_RELOC_MIPS16_GPREL:
738e5348
RS
15320 case BFD_RELOC_MIPS16_GOT16:
15321 case BFD_RELOC_MIPS16_CALL16:
d6f16593
MR
15322 case BFD_RELOC_MIPS16_HI16:
15323 case BFD_RELOC_MIPS16_HI16_S:
252b5132 15324 case BFD_RELOC_MIPS16_JMP:
df58fc94
RS
15325 case BFD_RELOC_MICROMIPS_JMP:
15326 case BFD_RELOC_MICROMIPS_GOT_DISP:
15327 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15328 case BFD_RELOC_MICROMIPS_GOT_OFST:
15329 case BFD_RELOC_MICROMIPS_SUB:
15330 case BFD_RELOC_MICROMIPS_HIGHEST:
15331 case BFD_RELOC_MICROMIPS_HIGHER:
15332 case BFD_RELOC_MICROMIPS_SCN_DISP:
15333 case BFD_RELOC_MICROMIPS_JALR:
15334 case BFD_RELOC_MICROMIPS_HI16:
15335 case BFD_RELOC_MICROMIPS_HI16_S:
15336 case BFD_RELOC_MICROMIPS_GPREL16:
15337 case BFD_RELOC_MICROMIPS_LITERAL:
15338 case BFD_RELOC_MICROMIPS_CALL16:
15339 case BFD_RELOC_MICROMIPS_GOT16:
15340 case BFD_RELOC_MICROMIPS_GOT_HI16:
15341 case BFD_RELOC_MICROMIPS_GOT_LO16:
15342 case BFD_RELOC_MICROMIPS_CALL_HI16:
15343 case BFD_RELOC_MICROMIPS_CALL_LO16:
54f4ddb3 15344 /* Nothing needed to do. The value comes from the reloc entry. */
252b5132
RH
15345 break;
15346
252b5132
RH
15347 case BFD_RELOC_64:
15348 /* This is handled like BFD_RELOC_32, but we output a sign
15349 extended value if we are only 32 bits. */
3e722fb5 15350 if (fixP->fx_done)
252b5132
RH
15351 {
15352 if (8 <= sizeof (valueT))
2132e3a3 15353 md_number_to_chars ((char *) buf, *valP, 8);
252b5132
RH
15354 else
15355 {
a7ebbfdf 15356 valueT hiv;
252b5132 15357
a7ebbfdf 15358 if ((*valP & 0x80000000) != 0)
252b5132
RH
15359 hiv = 0xffffffff;
15360 else
15361 hiv = 0;
b215186b 15362 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
a7ebbfdf 15363 *valP, 4);
b215186b 15364 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
a7ebbfdf 15365 hiv, 4);
252b5132
RH
15366 }
15367 }
15368 break;
15369
056350c6 15370 case BFD_RELOC_RVA:
252b5132 15371 case BFD_RELOC_32:
252b5132
RH
15372 case BFD_RELOC_16:
15373 /* If we are deleting this reloc entry, we must fill in the
54f4ddb3
TS
15374 value now. This can happen if we have a .word which is not
15375 resolved when it appears but is later defined. */
252b5132 15376 if (fixP->fx_done)
54f4ddb3 15377 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
252b5132
RH
15378 break;
15379
15380 case BFD_RELOC_LO16:
d6f16593 15381 case BFD_RELOC_MIPS16_LO16:
df58fc94 15382 case BFD_RELOC_MICROMIPS_LO16:
3e722fb5
CD
15383 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
15384 may be safe to remove, but if so it's not obvious. */
252b5132
RH
15385 /* When handling an embedded PIC switch statement, we can wind
15386 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
15387 if (fixP->fx_done)
15388 {
a7ebbfdf 15389 if (*valP + 0x8000 > 0xffff)
252b5132
RH
15390 as_bad_where (fixP->fx_file, fixP->fx_line,
15391 _("relocation overflow"));
df58fc94
RS
15392 /* 32-bit microMIPS instructions are divided into two halfwords.
15393 Relocations always refer to the second halfword, regardless
15394 of endianness. */
15395 if (target_big_endian || fixP->fx_r_type == BFD_RELOC_MICROMIPS_LO16)
252b5132 15396 buf += 2;
2132e3a3 15397 md_number_to_chars ((char *) buf, *valP, 2);
252b5132
RH
15398 }
15399 break;
15400
15401 case BFD_RELOC_16_PCREL_S2:
a7ebbfdf 15402 if ((*valP & 0x3) != 0)
cb56d3d3 15403 as_bad_where (fixP->fx_file, fixP->fx_line,
bad36eac 15404 _("Branch to misaligned address (%lx)"), (long) *valP);
cb56d3d3 15405
54f4ddb3
TS
15406 /* We need to save the bits in the instruction since fixup_segment()
15407 might be deleting the relocation entry (i.e., a branch within
15408 the current segment). */
a7ebbfdf 15409 if (! fixP->fx_done)
bb2d6cd7 15410 break;
252b5132 15411
54f4ddb3 15412 /* Update old instruction data. */
252b5132
RH
15413 if (target_big_endian)
15414 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
15415 else
15416 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
15417
a7ebbfdf
TS
15418 if (*valP + 0x20000 <= 0x3ffff)
15419 {
15420 insn |= (*valP >> 2) & 0xffff;
2132e3a3 15421 md_number_to_chars ((char *) buf, insn, 4);
a7ebbfdf
TS
15422 }
15423 else if (mips_pic == NO_PIC
15424 && fixP->fx_done
15425 && fixP->fx_frag->fr_address >= text_section->vma
15426 && (fixP->fx_frag->fr_address
587aac4e 15427 < text_section->vma + bfd_get_section_size (text_section))
a7ebbfdf
TS
15428 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15429 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15430 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
252b5132
RH
15431 {
15432 /* The branch offset is too large. If this is an
15433 unconditional branch, and we are not generating PIC code,
15434 we can convert it to an absolute jump instruction. */
a7ebbfdf
TS
15435 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15436 insn = 0x0c000000; /* jal */
252b5132 15437 else
a7ebbfdf
TS
15438 insn = 0x08000000; /* j */
15439 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15440 fixP->fx_done = 0;
15441 fixP->fx_addsy = section_symbol (text_section);
15442 *valP += md_pcrel_from (fixP);
2132e3a3 15443 md_number_to_chars ((char *) buf, insn, 4);
a7ebbfdf
TS
15444 }
15445 else
15446 {
15447 /* If we got here, we have branch-relaxation disabled,
15448 and there's nothing we can do to fix this instruction
15449 without turning it into a longer sequence. */
15450 as_bad_where (fixP->fx_file, fixP->fx_line,
15451 _("Branch out of range"));
252b5132 15452 }
252b5132
RH
15453 break;
15454
df58fc94
RS
15455 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15456 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15457 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15458 /* We adjust the offset back to even. */
15459 if ((*valP & 0x1) != 0)
15460 --(*valP);
15461
15462 if (! fixP->fx_done)
15463 break;
15464
15465 /* Should never visit here, because we keep the relocation. */
15466 abort ();
15467 break;
15468
252b5132
RH
15469 case BFD_RELOC_VTABLE_INHERIT:
15470 fixP->fx_done = 0;
15471 if (fixP->fx_addsy
15472 && !S_IS_DEFINED (fixP->fx_addsy)
15473 && !S_IS_WEAK (fixP->fx_addsy))
15474 S_SET_WEAK (fixP->fx_addsy);
15475 break;
15476
15477 case BFD_RELOC_VTABLE_ENTRY:
15478 fixP->fx_done = 0;
15479 break;
15480
15481 default:
15482 internalError ();
15483 }
a7ebbfdf
TS
15484
15485 /* Remember value for tc_gen_reloc. */
15486 fixP->fx_addnumber = *valP;
252b5132
RH
15487}
15488
252b5132 15489static symbolS *
17a2f251 15490get_symbol (void)
252b5132
RH
15491{
15492 int c;
15493 char *name;
15494 symbolS *p;
15495
15496 name = input_line_pointer;
15497 c = get_symbol_end ();
15498 p = (symbolS *) symbol_find_or_make (name);
15499 *input_line_pointer = c;
15500 return p;
15501}
15502
742a56fe
RS
15503/* Align the current frag to a given power of two. If a particular
15504 fill byte should be used, FILL points to an integer that contains
15505 that byte, otherwise FILL is null.
15506
15507 The MIPS assembler also automatically adjusts any preceding
15508 label. */
252b5132
RH
15509
15510static void
742a56fe 15511mips_align (int to, int *fill, symbolS *label)
252b5132 15512{
7d10b47d 15513 mips_emit_delays ();
df58fc94 15514 mips_record_compressed_mode ();
742a56fe
RS
15515 if (fill == NULL && subseg_text_p (now_seg))
15516 frag_align_code (to, 0);
15517 else
15518 frag_align (to, fill ? *fill : 0, 0);
252b5132
RH
15519 record_alignment (now_seg, to);
15520 if (label != NULL)
15521 {
9c2799c2 15522 gas_assert (S_GET_SEGMENT (label) == now_seg);
49309057 15523 symbol_set_frag (label, frag_now);
252b5132
RH
15524 S_SET_VALUE (label, (valueT) frag_now_fix ());
15525 }
15526}
15527
15528/* Align to a given power of two. .align 0 turns off the automatic
15529 alignment used by the data creating pseudo-ops. */
15530
15531static void
17a2f251 15532s_align (int x ATTRIBUTE_UNUSED)
252b5132 15533{
742a56fe 15534 int temp, fill_value, *fill_ptr;
49954fb4 15535 long max_alignment = 28;
252b5132 15536
54f4ddb3 15537 /* o Note that the assembler pulls down any immediately preceding label
252b5132 15538 to the aligned address.
54f4ddb3 15539 o It's not documented but auto alignment is reinstated by
252b5132 15540 a .align pseudo instruction.
54f4ddb3 15541 o Note also that after auto alignment is turned off the mips assembler
252b5132 15542 issues an error on attempt to assemble an improperly aligned data item.
54f4ddb3 15543 We don't. */
252b5132
RH
15544
15545 temp = get_absolute_expression ();
15546 if (temp > max_alignment)
15547 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
15548 else if (temp < 0)
15549 {
15550 as_warn (_("Alignment negative: 0 assumed."));
15551 temp = 0;
15552 }
15553 if (*input_line_pointer == ',')
15554 {
f9419b05 15555 ++input_line_pointer;
742a56fe
RS
15556 fill_value = get_absolute_expression ();
15557 fill_ptr = &fill_value;
252b5132
RH
15558 }
15559 else
742a56fe 15560 fill_ptr = 0;
252b5132
RH
15561 if (temp)
15562 {
a8dbcb85
TS
15563 segment_info_type *si = seg_info (now_seg);
15564 struct insn_label_list *l = si->label_list;
54f4ddb3 15565 /* Auto alignment should be switched on by next section change. */
252b5132 15566 auto_align = 1;
742a56fe 15567 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
252b5132
RH
15568 }
15569 else
15570 {
15571 auto_align = 0;
15572 }
15573
15574 demand_empty_rest_of_line ();
15575}
15576
252b5132 15577static void
17a2f251 15578s_change_sec (int sec)
252b5132
RH
15579{
15580 segT seg;
15581
252b5132
RH
15582#ifdef OBJ_ELF
15583 /* The ELF backend needs to know that we are changing sections, so
15584 that .previous works correctly. We could do something like check
b6ff326e 15585 for an obj_section_change_hook macro, but that might be confusing
252b5132
RH
15586 as it would not be appropriate to use it in the section changing
15587 functions in read.c, since obj-elf.c intercepts those. FIXME:
15588 This should be cleaner, somehow. */
f43abd2b
TS
15589 if (IS_ELF)
15590 obj_elf_section_change_hook ();
252b5132
RH
15591#endif
15592
7d10b47d 15593 mips_emit_delays ();
6a32d874 15594
252b5132
RH
15595 switch (sec)
15596 {
15597 case 't':
15598 s_text (0);
15599 break;
15600 case 'd':
15601 s_data (0);
15602 break;
15603 case 'b':
15604 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15605 demand_empty_rest_of_line ();
15606 break;
15607
15608 case 'r':
4d0d148d
TS
15609 seg = subseg_new (RDATA_SECTION_NAME,
15610 (subsegT) get_absolute_expression ());
f43abd2b 15611 if (IS_ELF)
252b5132 15612 {
4d0d148d
TS
15613 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15614 | SEC_READONLY | SEC_RELOC
15615 | SEC_DATA));
c41e87e3 15616 if (strncmp (TARGET_OS, "elf", 3) != 0)
4d0d148d 15617 record_alignment (seg, 4);
252b5132 15618 }
4d0d148d 15619 demand_empty_rest_of_line ();
252b5132
RH
15620 break;
15621
15622 case 's':
4d0d148d 15623 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
f43abd2b 15624 if (IS_ELF)
252b5132 15625 {
4d0d148d
TS
15626 bfd_set_section_flags (stdoutput, seg,
15627 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
c41e87e3 15628 if (strncmp (TARGET_OS, "elf", 3) != 0)
4d0d148d 15629 record_alignment (seg, 4);
252b5132 15630 }
4d0d148d
TS
15631 demand_empty_rest_of_line ();
15632 break;
998b3c36
MR
15633
15634 case 'B':
15635 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
15636 if (IS_ELF)
15637 {
15638 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
15639 if (strncmp (TARGET_OS, "elf", 3) != 0)
15640 record_alignment (seg, 4);
15641 }
15642 demand_empty_rest_of_line ();
15643 break;
252b5132
RH
15644 }
15645
15646 auto_align = 1;
15647}
b34976b6 15648
cca86cc8 15649void
17a2f251 15650s_change_section (int ignore ATTRIBUTE_UNUSED)
cca86cc8 15651{
7ed4a06a 15652#ifdef OBJ_ELF
cca86cc8
SC
15653 char *section_name;
15654 char c;
684022ea 15655 char next_c = 0;
cca86cc8
SC
15656 int section_type;
15657 int section_flag;
15658 int section_entry_size;
15659 int section_alignment;
b34976b6 15660
f43abd2b 15661 if (!IS_ELF)
7ed4a06a
TS
15662 return;
15663
cca86cc8
SC
15664 section_name = input_line_pointer;
15665 c = get_symbol_end ();
a816d1ed
AO
15666 if (c)
15667 next_c = *(input_line_pointer + 1);
cca86cc8 15668
4cf0dd0d
TS
15669 /* Do we have .section Name<,"flags">? */
15670 if (c != ',' || (c == ',' && next_c == '"'))
cca86cc8 15671 {
4cf0dd0d
TS
15672 /* just after name is now '\0'. */
15673 *input_line_pointer = c;
cca86cc8
SC
15674 input_line_pointer = section_name;
15675 obj_elf_section (ignore);
15676 return;
15677 }
15678 input_line_pointer++;
15679
15680 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15681 if (c == ',')
15682 section_type = get_absolute_expression ();
15683 else
15684 section_type = 0;
15685 if (*input_line_pointer++ == ',')
15686 section_flag = get_absolute_expression ();
15687 else
15688 section_flag = 0;
15689 if (*input_line_pointer++ == ',')
15690 section_entry_size = get_absolute_expression ();
15691 else
15692 section_entry_size = 0;
15693 if (*input_line_pointer++ == ',')
15694 section_alignment = get_absolute_expression ();
15695 else
15696 section_alignment = 0;
87975d2a
AM
15697 /* FIXME: really ignore? */
15698 (void) section_alignment;
cca86cc8 15699
a816d1ed
AO
15700 section_name = xstrdup (section_name);
15701
8ab8a5c8
RS
15702 /* When using the generic form of .section (as implemented by obj-elf.c),
15703 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15704 traditionally had to fall back on the more common @progbits instead.
15705
15706 There's nothing really harmful in this, since bfd will correct
15707 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
708587a4 15708 means that, for backwards compatibility, the special_section entries
8ab8a5c8
RS
15709 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15710
15711 Even so, we shouldn't force users of the MIPS .section syntax to
15712 incorrectly label the sections as SHT_PROGBITS. The best compromise
15713 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15714 generic type-checking code. */
15715 if (section_type == SHT_MIPS_DWARF)
15716 section_type = SHT_PROGBITS;
15717
cca86cc8
SC
15718 obj_elf_change_section (section_name, section_type, section_flag,
15719 section_entry_size, 0, 0, 0);
a816d1ed
AO
15720
15721 if (now_seg->name != section_name)
15722 free (section_name);
7ed4a06a 15723#endif /* OBJ_ELF */
cca86cc8 15724}
252b5132
RH
15725
15726void
17a2f251 15727mips_enable_auto_align (void)
252b5132
RH
15728{
15729 auto_align = 1;
15730}
15731
15732static void
17a2f251 15733s_cons (int log_size)
252b5132 15734{
a8dbcb85
TS
15735 segment_info_type *si = seg_info (now_seg);
15736 struct insn_label_list *l = si->label_list;
252b5132
RH
15737 symbolS *label;
15738
a8dbcb85 15739 label = l != NULL ? l->label : NULL;
7d10b47d 15740 mips_emit_delays ();
252b5132
RH
15741 if (log_size > 0 && auto_align)
15742 mips_align (log_size, 0, label);
252b5132 15743 cons (1 << log_size);
a1facbec 15744 mips_clear_insn_labels ();
252b5132
RH
15745}
15746
15747static void
17a2f251 15748s_float_cons (int type)
252b5132 15749{
a8dbcb85
TS
15750 segment_info_type *si = seg_info (now_seg);
15751 struct insn_label_list *l = si->label_list;
252b5132
RH
15752 symbolS *label;
15753
a8dbcb85 15754 label = l != NULL ? l->label : NULL;
252b5132 15755
7d10b47d 15756 mips_emit_delays ();
252b5132
RH
15757
15758 if (auto_align)
49309057
ILT
15759 {
15760 if (type == 'd')
15761 mips_align (3, 0, label);
15762 else
15763 mips_align (2, 0, label);
15764 }
252b5132 15765
252b5132 15766 float_cons (type);
a1facbec 15767 mips_clear_insn_labels ();
252b5132
RH
15768}
15769
15770/* Handle .globl. We need to override it because on Irix 5 you are
15771 permitted to say
15772 .globl foo .text
15773 where foo is an undefined symbol, to mean that foo should be
15774 considered to be the address of a function. */
15775
15776static void
17a2f251 15777s_mips_globl (int x ATTRIBUTE_UNUSED)
252b5132
RH
15778{
15779 char *name;
15780 int c;
15781 symbolS *symbolP;
15782 flagword flag;
15783
8a06b769 15784 do
252b5132 15785 {
8a06b769 15786 name = input_line_pointer;
252b5132 15787 c = get_symbol_end ();
8a06b769
TS
15788 symbolP = symbol_find_or_make (name);
15789 S_SET_EXTERNAL (symbolP);
15790
252b5132 15791 *input_line_pointer = c;
8a06b769 15792 SKIP_WHITESPACE ();
252b5132 15793
8a06b769
TS
15794 /* On Irix 5, every global symbol that is not explicitly labelled as
15795 being a function is apparently labelled as being an object. */
15796 flag = BSF_OBJECT;
252b5132 15797
8a06b769
TS
15798 if (!is_end_of_line[(unsigned char) *input_line_pointer]
15799 && (*input_line_pointer != ','))
15800 {
15801 char *secname;
15802 asection *sec;
15803
15804 secname = input_line_pointer;
15805 c = get_symbol_end ();
15806 sec = bfd_get_section_by_name (stdoutput, secname);
15807 if (sec == NULL)
15808 as_bad (_("%s: no such section"), secname);
15809 *input_line_pointer = c;
15810
15811 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
15812 flag = BSF_FUNCTION;
15813 }
15814
15815 symbol_get_bfdsym (symbolP)->flags |= flag;
15816
15817 c = *input_line_pointer;
15818 if (c == ',')
15819 {
15820 input_line_pointer++;
15821 SKIP_WHITESPACE ();
15822 if (is_end_of_line[(unsigned char) *input_line_pointer])
15823 c = '\n';
15824 }
15825 }
15826 while (c == ',');
252b5132 15827
252b5132
RH
15828 demand_empty_rest_of_line ();
15829}
15830
15831static void
17a2f251 15832s_option (int x ATTRIBUTE_UNUSED)
252b5132
RH
15833{
15834 char *opt;
15835 char c;
15836
15837 opt = input_line_pointer;
15838 c = get_symbol_end ();
15839
15840 if (*opt == 'O')
15841 {
15842 /* FIXME: What does this mean? */
15843 }
15844 else if (strncmp (opt, "pic", 3) == 0)
15845 {
15846 int i;
15847
15848 i = atoi (opt + 3);
15849 if (i == 0)
15850 mips_pic = NO_PIC;
15851 else if (i == 2)
143d77c5 15852 {
252b5132 15853 mips_pic = SVR4_PIC;
143d77c5
EC
15854 mips_abicalls = TRUE;
15855 }
252b5132
RH
15856 else
15857 as_bad (_(".option pic%d not supported"), i);
15858
4d0d148d 15859 if (mips_pic == SVR4_PIC)
252b5132
RH
15860 {
15861 if (g_switch_seen && g_switch_value != 0)
15862 as_warn (_("-G may not be used with SVR4 PIC code"));
15863 g_switch_value = 0;
15864 bfd_set_gp_size (stdoutput, 0);
15865 }
15866 }
15867 else
15868 as_warn (_("Unrecognized option \"%s\""), opt);
15869
15870 *input_line_pointer = c;
15871 demand_empty_rest_of_line ();
15872}
15873
15874/* This structure is used to hold a stack of .set values. */
15875
e972090a
NC
15876struct mips_option_stack
15877{
252b5132
RH
15878 struct mips_option_stack *next;
15879 struct mips_set_options options;
15880};
15881
15882static struct mips_option_stack *mips_opts_stack;
15883
15884/* Handle the .set pseudo-op. */
15885
15886static void
17a2f251 15887s_mipsset (int x ATTRIBUTE_UNUSED)
252b5132
RH
15888{
15889 char *name = input_line_pointer, ch;
15890
15891 while (!is_end_of_line[(unsigned char) *input_line_pointer])
f9419b05 15892 ++input_line_pointer;
252b5132
RH
15893 ch = *input_line_pointer;
15894 *input_line_pointer = '\0';
15895
15896 if (strcmp (name, "reorder") == 0)
15897 {
7d10b47d
RS
15898 if (mips_opts.noreorder)
15899 end_noreorder ();
252b5132
RH
15900 }
15901 else if (strcmp (name, "noreorder") == 0)
15902 {
7d10b47d
RS
15903 if (!mips_opts.noreorder)
15904 start_noreorder ();
252b5132 15905 }
741fe287
MR
15906 else if (strncmp (name, "at=", 3) == 0)
15907 {
15908 char *s = name + 3;
15909
15910 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
15911 as_bad (_("Unrecognized register name `%s'"), s);
15912 }
252b5132
RH
15913 else if (strcmp (name, "at") == 0)
15914 {
741fe287 15915 mips_opts.at = ATREG;
252b5132
RH
15916 }
15917 else if (strcmp (name, "noat") == 0)
15918 {
741fe287 15919 mips_opts.at = ZERO;
252b5132
RH
15920 }
15921 else if (strcmp (name, "macro") == 0)
15922 {
15923 mips_opts.warn_about_macros = 0;
15924 }
15925 else if (strcmp (name, "nomacro") == 0)
15926 {
15927 if (mips_opts.noreorder == 0)
15928 as_bad (_("`noreorder' must be set before `nomacro'"));
15929 mips_opts.warn_about_macros = 1;
15930 }
15931 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
15932 {
15933 mips_opts.nomove = 0;
15934 }
15935 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
15936 {
15937 mips_opts.nomove = 1;
15938 }
15939 else if (strcmp (name, "bopt") == 0)
15940 {
15941 mips_opts.nobopt = 0;
15942 }
15943 else if (strcmp (name, "nobopt") == 0)
15944 {
15945 mips_opts.nobopt = 1;
15946 }
ad3fea08
TS
15947 else if (strcmp (name, "gp=default") == 0)
15948 mips_opts.gp32 = file_mips_gp32;
15949 else if (strcmp (name, "gp=32") == 0)
15950 mips_opts.gp32 = 1;
15951 else if (strcmp (name, "gp=64") == 0)
15952 {
15953 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
20203fb9 15954 as_warn (_("%s isa does not support 64-bit registers"),
ad3fea08
TS
15955 mips_cpu_info_from_isa (mips_opts.isa)->name);
15956 mips_opts.gp32 = 0;
15957 }
15958 else if (strcmp (name, "fp=default") == 0)
15959 mips_opts.fp32 = file_mips_fp32;
15960 else if (strcmp (name, "fp=32") == 0)
15961 mips_opts.fp32 = 1;
15962 else if (strcmp (name, "fp=64") == 0)
15963 {
15964 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
20203fb9 15965 as_warn (_("%s isa does not support 64-bit floating point registers"),
ad3fea08
TS
15966 mips_cpu_info_from_isa (mips_opts.isa)->name);
15967 mips_opts.fp32 = 0;
15968 }
037b32b9
AN
15969 else if (strcmp (name, "softfloat") == 0)
15970 mips_opts.soft_float = 1;
15971 else if (strcmp (name, "hardfloat") == 0)
15972 mips_opts.soft_float = 0;
15973 else if (strcmp (name, "singlefloat") == 0)
15974 mips_opts.single_float = 1;
15975 else if (strcmp (name, "doublefloat") == 0)
15976 mips_opts.single_float = 0;
252b5132
RH
15977 else if (strcmp (name, "mips16") == 0
15978 || strcmp (name, "MIPS-16") == 0)
df58fc94
RS
15979 {
15980 if (mips_opts.micromips == 1)
15981 as_fatal (_("`mips16' cannot be used with `micromips'"));
15982 mips_opts.mips16 = 1;
15983 }
252b5132
RH
15984 else if (strcmp (name, "nomips16") == 0
15985 || strcmp (name, "noMIPS-16") == 0)
15986 mips_opts.mips16 = 0;
df58fc94
RS
15987 else if (strcmp (name, "micromips") == 0)
15988 {
15989 if (mips_opts.mips16 == 1)
15990 as_fatal (_("`micromips' cannot be used with `mips16'"));
15991 mips_opts.micromips = 1;
15992 }
15993 else if (strcmp (name, "nomicromips") == 0)
15994 mips_opts.micromips = 0;
e16bfa71
TS
15995 else if (strcmp (name, "smartmips") == 0)
15996 {
ad3fea08 15997 if (!ISA_SUPPORTS_SMARTMIPS)
20203fb9 15998 as_warn (_("%s ISA does not support SmartMIPS ASE"),
e16bfa71
TS
15999 mips_cpu_info_from_isa (mips_opts.isa)->name);
16000 mips_opts.ase_smartmips = 1;
16001 }
16002 else if (strcmp (name, "nosmartmips") == 0)
16003 mips_opts.ase_smartmips = 0;
1f25f5d3
CD
16004 else if (strcmp (name, "mips3d") == 0)
16005 mips_opts.ase_mips3d = 1;
16006 else if (strcmp (name, "nomips3d") == 0)
16007 mips_opts.ase_mips3d = 0;
a4672219
TS
16008 else if (strcmp (name, "mdmx") == 0)
16009 mips_opts.ase_mdmx = 1;
16010 else if (strcmp (name, "nomdmx") == 0)
16011 mips_opts.ase_mdmx = 0;
74cd071d 16012 else if (strcmp (name, "dsp") == 0)
ad3fea08
TS
16013 {
16014 if (!ISA_SUPPORTS_DSP_ASE)
20203fb9 16015 as_warn (_("%s ISA does not support DSP ASE"),
ad3fea08
TS
16016 mips_cpu_info_from_isa (mips_opts.isa)->name);
16017 mips_opts.ase_dsp = 1;
8b082fb1 16018 mips_opts.ase_dspr2 = 0;
ad3fea08 16019 }
74cd071d 16020 else if (strcmp (name, "nodsp") == 0)
8b082fb1
TS
16021 {
16022 mips_opts.ase_dsp = 0;
16023 mips_opts.ase_dspr2 = 0;
16024 }
16025 else if (strcmp (name, "dspr2") == 0)
16026 {
16027 if (!ISA_SUPPORTS_DSPR2_ASE)
20203fb9 16028 as_warn (_("%s ISA does not support DSP R2 ASE"),
8b082fb1
TS
16029 mips_cpu_info_from_isa (mips_opts.isa)->name);
16030 mips_opts.ase_dspr2 = 1;
16031 mips_opts.ase_dsp = 1;
16032 }
16033 else if (strcmp (name, "nodspr2") == 0)
16034 {
16035 mips_opts.ase_dspr2 = 0;
16036 mips_opts.ase_dsp = 0;
16037 }
ef2e4d86 16038 else if (strcmp (name, "mt") == 0)
ad3fea08
TS
16039 {
16040 if (!ISA_SUPPORTS_MT_ASE)
20203fb9 16041 as_warn (_("%s ISA does not support MT ASE"),
ad3fea08
TS
16042 mips_cpu_info_from_isa (mips_opts.isa)->name);
16043 mips_opts.ase_mt = 1;
16044 }
ef2e4d86
CF
16045 else if (strcmp (name, "nomt") == 0)
16046 mips_opts.ase_mt = 0;
1a2c1fad 16047 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
252b5132 16048 {
af7ee8bf 16049 int reset = 0;
252b5132 16050
1a2c1fad
CD
16051 /* Permit the user to change the ISA and architecture on the fly.
16052 Needless to say, misuse can cause serious problems. */
81a21e38 16053 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
af7ee8bf
CD
16054 {
16055 reset = 1;
16056 mips_opts.isa = file_mips_isa;
1a2c1fad 16057 mips_opts.arch = file_mips_arch;
1a2c1fad
CD
16058 }
16059 else if (strncmp (name, "arch=", 5) == 0)
16060 {
16061 const struct mips_cpu_info *p;
16062
16063 p = mips_parse_cpu("internal use", name + 5);
16064 if (!p)
16065 as_bad (_("unknown architecture %s"), name + 5);
16066 else
16067 {
16068 mips_opts.arch = p->cpu;
16069 mips_opts.isa = p->isa;
16070 }
16071 }
81a21e38
TS
16072 else if (strncmp (name, "mips", 4) == 0)
16073 {
16074 const struct mips_cpu_info *p;
16075
16076 p = mips_parse_cpu("internal use", name);
16077 if (!p)
16078 as_bad (_("unknown ISA level %s"), name + 4);
16079 else
16080 {
16081 mips_opts.arch = p->cpu;
16082 mips_opts.isa = p->isa;
16083 }
16084 }
af7ee8bf 16085 else
81a21e38 16086 as_bad (_("unknown ISA or architecture %s"), name);
af7ee8bf
CD
16087
16088 switch (mips_opts.isa)
98d3f06f
KH
16089 {
16090 case 0:
98d3f06f 16091 break;
af7ee8bf
CD
16092 case ISA_MIPS1:
16093 case ISA_MIPS2:
16094 case ISA_MIPS32:
16095 case ISA_MIPS32R2:
98d3f06f
KH
16096 mips_opts.gp32 = 1;
16097 mips_opts.fp32 = 1;
16098 break;
af7ee8bf
CD
16099 case ISA_MIPS3:
16100 case ISA_MIPS4:
16101 case ISA_MIPS5:
16102 case ISA_MIPS64:
5f74bc13 16103 case ISA_MIPS64R2:
98d3f06f
KH
16104 mips_opts.gp32 = 0;
16105 mips_opts.fp32 = 0;
16106 break;
16107 default:
16108 as_bad (_("unknown ISA level %s"), name + 4);
16109 break;
16110 }
af7ee8bf 16111 if (reset)
98d3f06f 16112 {
af7ee8bf
CD
16113 mips_opts.gp32 = file_mips_gp32;
16114 mips_opts.fp32 = file_mips_fp32;
98d3f06f 16115 }
252b5132
RH
16116 }
16117 else if (strcmp (name, "autoextend") == 0)
16118 mips_opts.noautoextend = 0;
16119 else if (strcmp (name, "noautoextend") == 0)
16120 mips_opts.noautoextend = 1;
16121 else if (strcmp (name, "push") == 0)
16122 {
16123 struct mips_option_stack *s;
16124
16125 s = (struct mips_option_stack *) xmalloc (sizeof *s);
16126 s->next = mips_opts_stack;
16127 s->options = mips_opts;
16128 mips_opts_stack = s;
16129 }
16130 else if (strcmp (name, "pop") == 0)
16131 {
16132 struct mips_option_stack *s;
16133
16134 s = mips_opts_stack;
16135 if (s == NULL)
16136 as_bad (_(".set pop with no .set push"));
16137 else
16138 {
16139 /* If we're changing the reorder mode we need to handle
16140 delay slots correctly. */
16141 if (s->options.noreorder && ! mips_opts.noreorder)
7d10b47d 16142 start_noreorder ();
252b5132 16143 else if (! s->options.noreorder && mips_opts.noreorder)
7d10b47d 16144 end_noreorder ();
252b5132
RH
16145
16146 mips_opts = s->options;
16147 mips_opts_stack = s->next;
16148 free (s);
16149 }
16150 }
aed1a261
RS
16151 else if (strcmp (name, "sym32") == 0)
16152 mips_opts.sym32 = TRUE;
16153 else if (strcmp (name, "nosym32") == 0)
16154 mips_opts.sym32 = FALSE;
e6559e01
JM
16155 else if (strchr (name, ','))
16156 {
16157 /* Generic ".set" directive; use the generic handler. */
16158 *input_line_pointer = ch;
16159 input_line_pointer = name;
16160 s_set (0);
16161 return;
16162 }
252b5132
RH
16163 else
16164 {
16165 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
16166 }
16167 *input_line_pointer = ch;
16168 demand_empty_rest_of_line ();
16169}
16170
16171/* Handle the .abicalls pseudo-op. I believe this is equivalent to
16172 .option pic2. It means to generate SVR4 PIC calls. */
16173
16174static void
17a2f251 16175s_abicalls (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
16176{
16177 mips_pic = SVR4_PIC;
143d77c5 16178 mips_abicalls = TRUE;
4d0d148d
TS
16179
16180 if (g_switch_seen && g_switch_value != 0)
16181 as_warn (_("-G may not be used with SVR4 PIC code"));
16182 g_switch_value = 0;
16183
252b5132
RH
16184 bfd_set_gp_size (stdoutput, 0);
16185 demand_empty_rest_of_line ();
16186}
16187
16188/* Handle the .cpload pseudo-op. This is used when generating SVR4
16189 PIC code. It sets the $gp register for the function based on the
16190 function address, which is in the register named in the argument.
16191 This uses a relocation against _gp_disp, which is handled specially
16192 by the linker. The result is:
16193 lui $gp,%hi(_gp_disp)
16194 addiu $gp,$gp,%lo(_gp_disp)
16195 addu $gp,$gp,.cpload argument
aa6975fb
ILT
16196 The .cpload argument is normally $25 == $t9.
16197
16198 The -mno-shared option changes this to:
bbe506e8
TS
16199 lui $gp,%hi(__gnu_local_gp)
16200 addiu $gp,$gp,%lo(__gnu_local_gp)
aa6975fb
ILT
16201 and the argument is ignored. This saves an instruction, but the
16202 resulting code is not position independent; it uses an absolute
bbe506e8
TS
16203 address for __gnu_local_gp. Thus code assembled with -mno-shared
16204 can go into an ordinary executable, but not into a shared library. */
252b5132
RH
16205
16206static void
17a2f251 16207s_cpload (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
16208{
16209 expressionS ex;
aa6975fb
ILT
16210 int reg;
16211 int in_shared;
252b5132 16212
6478892d
TS
16213 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16214 .cpload is ignored. */
16215 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
252b5132
RH
16216 {
16217 s_ignore (0);
16218 return;
16219 }
16220
d3ecfc59 16221 /* .cpload should be in a .set noreorder section. */
252b5132
RH
16222 if (mips_opts.noreorder == 0)
16223 as_warn (_(".cpload not in noreorder section"));
16224
aa6975fb
ILT
16225 reg = tc_get_register (0);
16226
16227 /* If we need to produce a 64-bit address, we are better off using
16228 the default instruction sequence. */
aed1a261 16229 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
aa6975fb 16230
252b5132 16231 ex.X_op = O_symbol;
bbe506e8
TS
16232 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16233 "__gnu_local_gp");
252b5132
RH
16234 ex.X_op_symbol = NULL;
16235 ex.X_add_number = 0;
16236
16237 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
49309057 16238 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
252b5132 16239
584892a6 16240 macro_start ();
67c0d1eb
RS
16241 macro_build_lui (&ex, mips_gp_register);
16242 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
17a2f251 16243 mips_gp_register, BFD_RELOC_LO16);
aa6975fb
ILT
16244 if (in_shared)
16245 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16246 mips_gp_register, reg);
584892a6 16247 macro_end ();
252b5132
RH
16248
16249 demand_empty_rest_of_line ();
16250}
16251
6478892d
TS
16252/* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16253 .cpsetup $reg1, offset|$reg2, label
16254
16255 If offset is given, this results in:
16256 sd $gp, offset($sp)
956cd1d6 16257 lui $gp, %hi(%neg(%gp_rel(label)))
698b7d9d
TS
16258 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16259 daddu $gp, $gp, $reg1
6478892d
TS
16260
16261 If $reg2 is given, this results in:
16262 daddu $reg2, $gp, $0
956cd1d6 16263 lui $gp, %hi(%neg(%gp_rel(label)))
698b7d9d
TS
16264 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16265 daddu $gp, $gp, $reg1
aa6975fb
ILT
16266 $reg1 is normally $25 == $t9.
16267
16268 The -mno-shared option replaces the last three instructions with
16269 lui $gp,%hi(_gp)
54f4ddb3 16270 addiu $gp,$gp,%lo(_gp) */
aa6975fb 16271
6478892d 16272static void
17a2f251 16273s_cpsetup (int ignore ATTRIBUTE_UNUSED)
6478892d
TS
16274{
16275 expressionS ex_off;
16276 expressionS ex_sym;
16277 int reg1;
6478892d 16278
8586fc66 16279 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
6478892d
TS
16280 We also need NewABI support. */
16281 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16282 {
16283 s_ignore (0);
16284 return;
16285 }
16286
16287 reg1 = tc_get_register (0);
16288 SKIP_WHITESPACE ();
16289 if (*input_line_pointer != ',')
16290 {
16291 as_bad (_("missing argument separator ',' for .cpsetup"));
16292 return;
16293 }
16294 else
80245285 16295 ++input_line_pointer;
6478892d
TS
16296 SKIP_WHITESPACE ();
16297 if (*input_line_pointer == '$')
80245285
TS
16298 {
16299 mips_cpreturn_register = tc_get_register (0);
16300 mips_cpreturn_offset = -1;
16301 }
6478892d 16302 else
80245285
TS
16303 {
16304 mips_cpreturn_offset = get_absolute_expression ();
16305 mips_cpreturn_register = -1;
16306 }
6478892d
TS
16307 SKIP_WHITESPACE ();
16308 if (*input_line_pointer != ',')
16309 {
16310 as_bad (_("missing argument separator ',' for .cpsetup"));
16311 return;
16312 }
16313 else
f9419b05 16314 ++input_line_pointer;
6478892d 16315 SKIP_WHITESPACE ();
f21f8242 16316 expression (&ex_sym);
6478892d 16317
584892a6 16318 macro_start ();
6478892d
TS
16319 if (mips_cpreturn_register == -1)
16320 {
16321 ex_off.X_op = O_constant;
16322 ex_off.X_add_symbol = NULL;
16323 ex_off.X_op_symbol = NULL;
16324 ex_off.X_add_number = mips_cpreturn_offset;
16325
67c0d1eb 16326 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
17a2f251 16327 BFD_RELOC_LO16, SP);
6478892d
TS
16328 }
16329 else
67c0d1eb 16330 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
17a2f251 16331 mips_gp_register, 0);
6478892d 16332
aed1a261 16333 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
aa6975fb 16334 {
df58fc94 16335 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
aa6975fb
ILT
16336 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16337 BFD_RELOC_HI16_S);
16338
16339 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16340 mips_gp_register, -1, BFD_RELOC_GPREL16,
16341 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16342
16343 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16344 mips_gp_register, reg1);
16345 }
16346 else
16347 {
16348 expressionS ex;
16349
16350 ex.X_op = O_symbol;
4184909a 16351 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
aa6975fb
ILT
16352 ex.X_op_symbol = NULL;
16353 ex.X_add_number = 0;
6e1304d8 16354
aa6975fb
ILT
16355 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16356 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16357
16358 macro_build_lui (&ex, mips_gp_register);
16359 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16360 mips_gp_register, BFD_RELOC_LO16);
16361 }
f21f8242 16362
584892a6 16363 macro_end ();
6478892d
TS
16364
16365 demand_empty_rest_of_line ();
16366}
16367
16368static void
17a2f251 16369s_cplocal (int ignore ATTRIBUTE_UNUSED)
6478892d
TS
16370{
16371 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
54f4ddb3 16372 .cplocal is ignored. */
6478892d
TS
16373 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16374 {
16375 s_ignore (0);
16376 return;
16377 }
16378
16379 mips_gp_register = tc_get_register (0);
85b51719 16380 demand_empty_rest_of_line ();
6478892d
TS
16381}
16382
252b5132
RH
16383/* Handle the .cprestore pseudo-op. This stores $gp into a given
16384 offset from $sp. The offset is remembered, and after making a PIC
16385 call $gp is restored from that location. */
16386
16387static void
17a2f251 16388s_cprestore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
16389{
16390 expressionS ex;
252b5132 16391
6478892d 16392 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
c9914766 16393 .cprestore is ignored. */
6478892d 16394 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
252b5132
RH
16395 {
16396 s_ignore (0);
16397 return;
16398 }
16399
16400 mips_cprestore_offset = get_absolute_expression ();
7a621144 16401 mips_cprestore_valid = 1;
252b5132
RH
16402
16403 ex.X_op = O_constant;
16404 ex.X_add_symbol = NULL;
16405 ex.X_op_symbol = NULL;
16406 ex.X_add_number = mips_cprestore_offset;
16407
584892a6 16408 macro_start ();
67c0d1eb
RS
16409 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16410 SP, HAVE_64BIT_ADDRESSES);
584892a6 16411 macro_end ();
252b5132
RH
16412
16413 demand_empty_rest_of_line ();
16414}
16415
6478892d 16416/* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
67c1ffbe 16417 was given in the preceding .cpsetup, it results in:
6478892d 16418 ld $gp, offset($sp)
76b3015f 16419
6478892d 16420 If a register $reg2 was given there, it results in:
54f4ddb3
TS
16421 daddu $gp, $reg2, $0 */
16422
6478892d 16423static void
17a2f251 16424s_cpreturn (int ignore ATTRIBUTE_UNUSED)
6478892d
TS
16425{
16426 expressionS ex;
6478892d
TS
16427
16428 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16429 We also need NewABI support. */
16430 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16431 {
16432 s_ignore (0);
16433 return;
16434 }
16435
584892a6 16436 macro_start ();
6478892d
TS
16437 if (mips_cpreturn_register == -1)
16438 {
16439 ex.X_op = O_constant;
16440 ex.X_add_symbol = NULL;
16441 ex.X_op_symbol = NULL;
16442 ex.X_add_number = mips_cpreturn_offset;
16443
67c0d1eb 16444 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
6478892d
TS
16445 }
16446 else
67c0d1eb 16447 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
17a2f251 16448 mips_cpreturn_register, 0);
584892a6 16449 macro_end ();
6478892d
TS
16450
16451 demand_empty_rest_of_line ();
16452}
16453
741d6ea8
JM
16454/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
16455 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
16456 use in DWARF debug information. */
16457
16458static void
16459s_dtprel_internal (size_t bytes)
16460{
16461 expressionS ex;
16462 char *p;
16463
16464 expression (&ex);
16465
16466 if (ex.X_op != O_symbol)
16467 {
16468 as_bad (_("Unsupported use of %s"), (bytes == 8
16469 ? ".dtpreldword"
16470 : ".dtprelword"));
16471 ignore_rest_of_line ();
16472 }
16473
16474 p = frag_more (bytes);
16475 md_number_to_chars (p, 0, bytes);
16476 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
16477 (bytes == 8
16478 ? BFD_RELOC_MIPS_TLS_DTPREL64
16479 : BFD_RELOC_MIPS_TLS_DTPREL32));
16480
16481 demand_empty_rest_of_line ();
16482}
16483
16484/* Handle .dtprelword. */
16485
16486static void
16487s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16488{
16489 s_dtprel_internal (4);
16490}
16491
16492/* Handle .dtpreldword. */
16493
16494static void
16495s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16496{
16497 s_dtprel_internal (8);
16498}
16499
6478892d
TS
16500/* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16501 code. It sets the offset to use in gp_rel relocations. */
16502
16503static void
17a2f251 16504s_gpvalue (int ignore ATTRIBUTE_UNUSED)
6478892d
TS
16505{
16506 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16507 We also need NewABI support. */
16508 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16509 {
16510 s_ignore (0);
16511 return;
16512 }
16513
def2e0dd 16514 mips_gprel_offset = get_absolute_expression ();
6478892d
TS
16515
16516 demand_empty_rest_of_line ();
16517}
16518
252b5132
RH
16519/* Handle the .gpword pseudo-op. This is used when generating PIC
16520 code. It generates a 32 bit GP relative reloc. */
16521
16522static void
17a2f251 16523s_gpword (int ignore ATTRIBUTE_UNUSED)
252b5132 16524{
a8dbcb85
TS
16525 segment_info_type *si;
16526 struct insn_label_list *l;
252b5132
RH
16527 symbolS *label;
16528 expressionS ex;
16529 char *p;
16530
16531 /* When not generating PIC code, this is treated as .word. */
16532 if (mips_pic != SVR4_PIC)
16533 {
16534 s_cons (2);
16535 return;
16536 }
16537
a8dbcb85
TS
16538 si = seg_info (now_seg);
16539 l = si->label_list;
16540 label = l != NULL ? l->label : NULL;
7d10b47d 16541 mips_emit_delays ();
252b5132
RH
16542 if (auto_align)
16543 mips_align (2, 0, label);
252b5132
RH
16544
16545 expression (&ex);
a1facbec 16546 mips_clear_insn_labels ();
252b5132
RH
16547
16548 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16549 {
16550 as_bad (_("Unsupported use of .gpword"));
16551 ignore_rest_of_line ();
16552 }
16553
16554 p = frag_more (4);
17a2f251 16555 md_number_to_chars (p, 0, 4);
b34976b6 16556 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
cdf6fd85 16557 BFD_RELOC_GPREL32);
252b5132
RH
16558
16559 demand_empty_rest_of_line ();
16560}
16561
10181a0d 16562static void
17a2f251 16563s_gpdword (int ignore ATTRIBUTE_UNUSED)
10181a0d 16564{
a8dbcb85
TS
16565 segment_info_type *si;
16566 struct insn_label_list *l;
10181a0d
AO
16567 symbolS *label;
16568 expressionS ex;
16569 char *p;
16570
16571 /* When not generating PIC code, this is treated as .dword. */
16572 if (mips_pic != SVR4_PIC)
16573 {
16574 s_cons (3);
16575 return;
16576 }
16577
a8dbcb85
TS
16578 si = seg_info (now_seg);
16579 l = si->label_list;
16580 label = l != NULL ? l->label : NULL;
7d10b47d 16581 mips_emit_delays ();
10181a0d
AO
16582 if (auto_align)
16583 mips_align (3, 0, label);
10181a0d
AO
16584
16585 expression (&ex);
a1facbec 16586 mips_clear_insn_labels ();
10181a0d
AO
16587
16588 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16589 {
16590 as_bad (_("Unsupported use of .gpdword"));
16591 ignore_rest_of_line ();
16592 }
16593
16594 p = frag_more (8);
17a2f251 16595 md_number_to_chars (p, 0, 8);
a105a300 16596 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
6e1304d8 16597 BFD_RELOC_GPREL32)->fx_tcbit = 1;
10181a0d
AO
16598
16599 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
6e1304d8
RS
16600 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
16601 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
10181a0d
AO
16602
16603 demand_empty_rest_of_line ();
16604}
16605
252b5132
RH
16606/* Handle the .cpadd pseudo-op. This is used when dealing with switch
16607 tables in SVR4 PIC code. */
16608
16609static void
17a2f251 16610s_cpadd (int ignore ATTRIBUTE_UNUSED)
252b5132 16611{
252b5132
RH
16612 int reg;
16613
10181a0d
AO
16614 /* This is ignored when not generating SVR4 PIC code. */
16615 if (mips_pic != SVR4_PIC)
252b5132
RH
16616 {
16617 s_ignore (0);
16618 return;
16619 }
16620
16621 /* Add $gp to the register named as an argument. */
584892a6 16622 macro_start ();
252b5132 16623 reg = tc_get_register (0);
67c0d1eb 16624 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
584892a6 16625 macro_end ();
252b5132 16626
bdaaa2e1 16627 demand_empty_rest_of_line ();
252b5132
RH
16628}
16629
16630/* Handle the .insn pseudo-op. This marks instruction labels in
df58fc94 16631 mips16/micromips mode. This permits the linker to handle them specially,
252b5132
RH
16632 such as generating jalx instructions when needed. We also make
16633 them odd for the duration of the assembly, in order to generate the
16634 right sort of code. We will make them even in the adjust_symtab
16635 routine, while leaving them marked. This is convenient for the
16636 debugger and the disassembler. The linker knows to make them odd
16637 again. */
16638
16639static void
17a2f251 16640s_insn (int ignore ATTRIBUTE_UNUSED)
252b5132 16641{
df58fc94 16642 mips_mark_labels ();
252b5132
RH
16643
16644 demand_empty_rest_of_line ();
16645}
16646
16647/* Handle a .stabn directive. We need these in order to mark a label
16648 as being a mips16 text label correctly. Sometimes the compiler
16649 will emit a label, followed by a .stabn, and then switch sections.
16650 If the label and .stabn are in mips16 mode, then the label is
16651 really a mips16 text label. */
16652
16653static void
17a2f251 16654s_mips_stab (int type)
252b5132 16655{
f9419b05 16656 if (type == 'n')
df58fc94 16657 mips_mark_labels ();
252b5132
RH
16658
16659 s_stab (type);
16660}
16661
54f4ddb3 16662/* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
252b5132
RH
16663
16664static void
17a2f251 16665s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
16666{
16667 char *name;
16668 int c;
16669 symbolS *symbolP;
16670 expressionS exp;
16671
16672 name = input_line_pointer;
16673 c = get_symbol_end ();
16674 symbolP = symbol_find_or_make (name);
16675 S_SET_WEAK (symbolP);
16676 *input_line_pointer = c;
16677
16678 SKIP_WHITESPACE ();
16679
16680 if (! is_end_of_line[(unsigned char) *input_line_pointer])
16681 {
16682 if (S_IS_DEFINED (symbolP))
16683 {
20203fb9 16684 as_bad (_("ignoring attempt to redefine symbol %s"),
252b5132
RH
16685 S_GET_NAME (symbolP));
16686 ignore_rest_of_line ();
16687 return;
16688 }
bdaaa2e1 16689
252b5132
RH
16690 if (*input_line_pointer == ',')
16691 {
16692 ++input_line_pointer;
16693 SKIP_WHITESPACE ();
16694 }
bdaaa2e1 16695
252b5132
RH
16696 expression (&exp);
16697 if (exp.X_op != O_symbol)
16698 {
20203fb9 16699 as_bad (_("bad .weakext directive"));
98d3f06f 16700 ignore_rest_of_line ();
252b5132
RH
16701 return;
16702 }
49309057 16703 symbol_set_value_expression (symbolP, &exp);
252b5132
RH
16704 }
16705
16706 demand_empty_rest_of_line ();
16707}
16708
16709/* Parse a register string into a number. Called from the ECOFF code
16710 to parse .frame. The argument is non-zero if this is the frame
16711 register, so that we can record it in mips_frame_reg. */
16712
16713int
17a2f251 16714tc_get_register (int frame)
252b5132 16715{
707bfff6 16716 unsigned int reg;
252b5132
RH
16717
16718 SKIP_WHITESPACE ();
707bfff6
TS
16719 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, &reg))
16720 reg = 0;
252b5132 16721 if (frame)
7a621144
DJ
16722 {
16723 mips_frame_reg = reg != 0 ? reg : SP;
16724 mips_frame_reg_valid = 1;
16725 mips_cprestore_valid = 0;
16726 }
252b5132
RH
16727 return reg;
16728}
16729
16730valueT
17a2f251 16731md_section_align (asection *seg, valueT addr)
252b5132
RH
16732{
16733 int align = bfd_get_section_alignment (stdoutput, seg);
16734
b4c71f56
TS
16735 if (IS_ELF)
16736 {
16737 /* We don't need to align ELF sections to the full alignment.
16738 However, Irix 5 may prefer that we align them at least to a 16
16739 byte boundary. We don't bother to align the sections if we
16740 are targeted for an embedded system. */
c41e87e3 16741 if (strncmp (TARGET_OS, "elf", 3) == 0)
b4c71f56
TS
16742 return addr;
16743 if (align > 4)
16744 align = 4;
16745 }
252b5132
RH
16746
16747 return ((addr + (1 << align) - 1) & (-1 << align));
16748}
16749
16750/* Utility routine, called from above as well. If called while the
16751 input file is still being read, it's only an approximation. (For
16752 example, a symbol may later become defined which appeared to be
16753 undefined earlier.) */
16754
16755static int
17a2f251 16756nopic_need_relax (symbolS *sym, int before_relaxing)
252b5132
RH
16757{
16758 if (sym == 0)
16759 return 0;
16760
4d0d148d 16761 if (g_switch_value > 0)
252b5132
RH
16762 {
16763 const char *symname;
16764 int change;
16765
c9914766 16766 /* Find out whether this symbol can be referenced off the $gp
252b5132
RH
16767 register. It can be if it is smaller than the -G size or if
16768 it is in the .sdata or .sbss section. Certain symbols can
c9914766 16769 not be referenced off the $gp, although it appears as though
252b5132
RH
16770 they can. */
16771 symname = S_GET_NAME (sym);
16772 if (symname != (const char *) NULL
16773 && (strcmp (symname, "eprol") == 0
16774 || strcmp (symname, "etext") == 0
16775 || strcmp (symname, "_gp") == 0
16776 || strcmp (symname, "edata") == 0
16777 || strcmp (symname, "_fbss") == 0
16778 || strcmp (symname, "_fdata") == 0
16779 || strcmp (symname, "_ftext") == 0
16780 || strcmp (symname, "end") == 0
16781 || strcmp (symname, "_gp_disp") == 0))
16782 change = 1;
16783 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
16784 && (0
16785#ifndef NO_ECOFF_DEBUGGING
49309057
ILT
16786 || (symbol_get_obj (sym)->ecoff_extern_size != 0
16787 && (symbol_get_obj (sym)->ecoff_extern_size
16788 <= g_switch_value))
252b5132
RH
16789#endif
16790 /* We must defer this decision until after the whole
16791 file has been read, since there might be a .extern
16792 after the first use of this symbol. */
16793 || (before_relaxing
16794#ifndef NO_ECOFF_DEBUGGING
49309057 16795 && symbol_get_obj (sym)->ecoff_extern_size == 0
252b5132
RH
16796#endif
16797 && S_GET_VALUE (sym) == 0)
16798 || (S_GET_VALUE (sym) != 0
16799 && S_GET_VALUE (sym) <= g_switch_value)))
16800 change = 0;
16801 else
16802 {
16803 const char *segname;
16804
16805 segname = segment_name (S_GET_SEGMENT (sym));
9c2799c2 16806 gas_assert (strcmp (segname, ".lit8") != 0
252b5132
RH
16807 && strcmp (segname, ".lit4") != 0);
16808 change = (strcmp (segname, ".sdata") != 0
fba2b7f9
GK
16809 && strcmp (segname, ".sbss") != 0
16810 && strncmp (segname, ".sdata.", 7) != 0
d4dc2f22
TS
16811 && strncmp (segname, ".sbss.", 6) != 0
16812 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
fba2b7f9 16813 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
252b5132
RH
16814 }
16815 return change;
16816 }
16817 else
c9914766 16818 /* We are not optimizing for the $gp register. */
252b5132
RH
16819 return 1;
16820}
16821
5919d012
RS
16822
16823/* Return true if the given symbol should be considered local for SVR4 PIC. */
16824
16825static bfd_boolean
17a2f251 16826pic_need_relax (symbolS *sym, asection *segtype)
5919d012
RS
16827{
16828 asection *symsec;
5919d012
RS
16829
16830 /* Handle the case of a symbol equated to another symbol. */
16831 while (symbol_equated_reloc_p (sym))
16832 {
16833 symbolS *n;
16834
5f0fe04b 16835 /* It's possible to get a loop here in a badly written program. */
5919d012
RS
16836 n = symbol_get_value_expression (sym)->X_add_symbol;
16837 if (n == sym)
16838 break;
16839 sym = n;
16840 }
16841
df1f3cda
DD
16842 if (symbol_section_p (sym))
16843 return TRUE;
16844
5919d012
RS
16845 symsec = S_GET_SEGMENT (sym);
16846
5919d012
RS
16847 /* This must duplicate the test in adjust_reloc_syms. */
16848 return (symsec != &bfd_und_section
16849 && symsec != &bfd_abs_section
5f0fe04b
TS
16850 && !bfd_is_com_section (symsec)
16851 && !s_is_linkonce (sym, segtype)
5919d012
RS
16852#ifdef OBJ_ELF
16853 /* A global or weak symbol is treated as external. */
f43abd2b 16854 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
5919d012
RS
16855#endif
16856 );
16857}
16858
16859
252b5132
RH
16860/* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16861 extended opcode. SEC is the section the frag is in. */
16862
16863static int
17a2f251 16864mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
252b5132
RH
16865{
16866 int type;
3994f87e 16867 const struct mips16_immed_operand *op;
252b5132
RH
16868 offsetT val;
16869 int mintiny, maxtiny;
16870 segT symsec;
98aa84af 16871 fragS *sym_frag;
252b5132
RH
16872
16873 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
16874 return 0;
16875 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
16876 return 1;
16877
16878 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
16879 op = mips16_immed_operands;
16880 while (op->type != type)
16881 {
16882 ++op;
9c2799c2 16883 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
252b5132
RH
16884 }
16885
16886 if (op->unsp)
16887 {
16888 if (type == '<' || type == '>' || type == '[' || type == ']')
16889 {
16890 mintiny = 1;
16891 maxtiny = 1 << op->nbits;
16892 }
16893 else
16894 {
16895 mintiny = 0;
16896 maxtiny = (1 << op->nbits) - 1;
16897 }
16898 }
16899 else
16900 {
16901 mintiny = - (1 << (op->nbits - 1));
16902 maxtiny = (1 << (op->nbits - 1)) - 1;
16903 }
16904
98aa84af 16905 sym_frag = symbol_get_frag (fragp->fr_symbol);
ac62c346 16906 val = S_GET_VALUE (fragp->fr_symbol);
98aa84af 16907 symsec = S_GET_SEGMENT (fragp->fr_symbol);
252b5132
RH
16908
16909 if (op->pcrel)
16910 {
16911 addressT addr;
16912
16913 /* We won't have the section when we are called from
16914 mips_relax_frag. However, we will always have been called
16915 from md_estimate_size_before_relax first. If this is a
16916 branch to a different section, we mark it as such. If SEC is
16917 NULL, and the frag is not marked, then it must be a branch to
16918 the same section. */
16919 if (sec == NULL)
16920 {
16921 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
16922 return 1;
16923 }
16924 else
16925 {
98aa84af 16926 /* Must have been called from md_estimate_size_before_relax. */
252b5132
RH
16927 if (symsec != sec)
16928 {
16929 fragp->fr_subtype =
16930 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16931
16932 /* FIXME: We should support this, and let the linker
16933 catch branches and loads that are out of range. */
16934 as_bad_where (fragp->fr_file, fragp->fr_line,
16935 _("unsupported PC relative reference to different section"));
16936
16937 return 1;
16938 }
98aa84af
AM
16939 if (fragp != sym_frag && sym_frag->fr_address == 0)
16940 /* Assume non-extended on the first relaxation pass.
16941 The address we have calculated will be bogus if this is
16942 a forward branch to another frag, as the forward frag
16943 will have fr_address == 0. */
16944 return 0;
252b5132
RH
16945 }
16946
16947 /* In this case, we know for sure that the symbol fragment is in
98aa84af
AM
16948 the same section. If the relax_marker of the symbol fragment
16949 differs from the relax_marker of this fragment, we have not
16950 yet adjusted the symbol fragment fr_address. We want to add
252b5132
RH
16951 in STRETCH in order to get a better estimate of the address.
16952 This particularly matters because of the shift bits. */
16953 if (stretch != 0
98aa84af 16954 && sym_frag->relax_marker != fragp->relax_marker)
252b5132
RH
16955 {
16956 fragS *f;
16957
16958 /* Adjust stretch for any alignment frag. Note that if have
16959 been expanding the earlier code, the symbol may be
16960 defined in what appears to be an earlier frag. FIXME:
16961 This doesn't handle the fr_subtype field, which specifies
16962 a maximum number of bytes to skip when doing an
16963 alignment. */
98aa84af 16964 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
252b5132
RH
16965 {
16966 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
16967 {
16968 if (stretch < 0)
16969 stretch = - ((- stretch)
16970 & ~ ((1 << (int) f->fr_offset) - 1));
16971 else
16972 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
16973 if (stretch == 0)
16974 break;
16975 }
16976 }
16977 if (f != NULL)
16978 val += stretch;
16979 }
16980
16981 addr = fragp->fr_address + fragp->fr_fix;
16982
16983 /* The base address rules are complicated. The base address of
16984 a branch is the following instruction. The base address of a
16985 PC relative load or add is the instruction itself, but if it
16986 is in a delay slot (in which case it can not be extended) use
16987 the address of the instruction whose delay slot it is in. */
16988 if (type == 'p' || type == 'q')
16989 {
16990 addr += 2;
16991
16992 /* If we are currently assuming that this frag should be
16993 extended, then, the current address is two bytes
bdaaa2e1 16994 higher. */
252b5132
RH
16995 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16996 addr += 2;
16997
16998 /* Ignore the low bit in the target, since it will be set
16999 for a text label. */
17000 if ((val & 1) != 0)
17001 --val;
17002 }
17003 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17004 addr -= 4;
17005 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17006 addr -= 2;
17007
17008 val -= addr & ~ ((1 << op->shift) - 1);
17009
17010 /* Branch offsets have an implicit 0 in the lowest bit. */
17011 if (type == 'p' || type == 'q')
17012 val /= 2;
17013
17014 /* If any of the shifted bits are set, we must use an extended
17015 opcode. If the address depends on the size of this
17016 instruction, this can lead to a loop, so we arrange to always
17017 use an extended opcode. We only check this when we are in
17018 the main relaxation loop, when SEC is NULL. */
17019 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
17020 {
17021 fragp->fr_subtype =
17022 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17023 return 1;
17024 }
17025
17026 /* If we are about to mark a frag as extended because the value
17027 is precisely maxtiny + 1, then there is a chance of an
17028 infinite loop as in the following code:
17029 la $4,foo
17030 .skip 1020
17031 .align 2
17032 foo:
17033 In this case when the la is extended, foo is 0x3fc bytes
17034 away, so the la can be shrunk, but then foo is 0x400 away, so
17035 the la must be extended. To avoid this loop, we mark the
17036 frag as extended if it was small, and is about to become
17037 extended with a value of maxtiny + 1. */
17038 if (val == ((maxtiny + 1) << op->shift)
17039 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
17040 && sec == NULL)
17041 {
17042 fragp->fr_subtype =
17043 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17044 return 1;
17045 }
17046 }
17047 else if (symsec != absolute_section && sec != NULL)
17048 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
17049
17050 if ((val & ((1 << op->shift) - 1)) != 0
17051 || val < (mintiny << op->shift)
17052 || val > (maxtiny << op->shift))
17053 return 1;
17054 else
17055 return 0;
17056}
17057
4a6a3df4
AO
17058/* Compute the length of a branch sequence, and adjust the
17059 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17060 worst-case length is computed, with UPDATE being used to indicate
17061 whether an unconditional (-1), branch-likely (+1) or regular (0)
17062 branch is to be computed. */
17063static int
17a2f251 17064relaxed_branch_length (fragS *fragp, asection *sec, int update)
4a6a3df4 17065{
b34976b6 17066 bfd_boolean toofar;
4a6a3df4
AO
17067 int length;
17068
17069 if (fragp
17070 && S_IS_DEFINED (fragp->fr_symbol)
17071 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17072 {
17073 addressT addr;
17074 offsetT val;
17075
17076 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17077
17078 addr = fragp->fr_address + fragp->fr_fix + 4;
17079
17080 val -= addr;
17081
17082 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17083 }
17084 else if (fragp)
17085 /* If the symbol is not defined or it's in a different segment,
17086 assume the user knows what's going on and emit a short
17087 branch. */
b34976b6 17088 toofar = FALSE;
4a6a3df4 17089 else
b34976b6 17090 toofar = TRUE;
4a6a3df4
AO
17091
17092 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17093 fragp->fr_subtype
66b3e8da
MR
17094 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17095 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
4a6a3df4
AO
17096 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17097 RELAX_BRANCH_LINK (fragp->fr_subtype),
17098 toofar);
17099
17100 length = 4;
17101 if (toofar)
17102 {
17103 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17104 length += 8;
17105
17106 if (mips_pic != NO_PIC)
17107 {
17108 /* Additional space for PIC loading of target address. */
17109 length += 8;
17110 if (mips_opts.isa == ISA_MIPS1)
17111 /* Additional space for $at-stabilizing nop. */
17112 length += 4;
17113 }
17114
17115 /* If branch is conditional. */
17116 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17117 length += 8;
17118 }
b34976b6 17119
4a6a3df4
AO
17120 return length;
17121}
17122
df58fc94
RS
17123/* Compute the length of a branch sequence, and adjust the
17124 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17125 worst-case length is computed, with UPDATE being used to indicate
17126 whether an unconditional (-1), or regular (0) branch is to be
17127 computed. */
17128
17129static int
17130relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17131{
17132 bfd_boolean toofar;
17133 int length;
17134
17135 if (fragp
17136 && S_IS_DEFINED (fragp->fr_symbol)
17137 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17138 {
17139 addressT addr;
17140 offsetT val;
17141
17142 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17143 /* Ignore the low bit in the target, since it will be set
17144 for a text label. */
17145 if ((val & 1) != 0)
17146 --val;
17147
17148 addr = fragp->fr_address + fragp->fr_fix + 4;
17149
17150 val -= addr;
17151
17152 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17153 }
17154 else if (fragp)
17155 /* If the symbol is not defined or it's in a different segment,
17156 assume the user knows what's going on and emit a short
17157 branch. */
17158 toofar = FALSE;
17159 else
17160 toofar = TRUE;
17161
17162 if (fragp && update
17163 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17164 fragp->fr_subtype = (toofar
17165 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17166 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17167
17168 length = 4;
17169 if (toofar)
17170 {
17171 bfd_boolean compact_known = fragp != NULL;
17172 bfd_boolean compact = FALSE;
17173 bfd_boolean uncond;
17174
17175 if (compact_known)
17176 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17177 if (fragp)
17178 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17179 else
17180 uncond = update < 0;
17181
17182 /* If label is out of range, we turn branch <br>:
17183
17184 <br> label # 4 bytes
17185 0:
17186
17187 into:
17188
17189 j label # 4 bytes
17190 nop # 2 bytes if compact && !PIC
17191 0:
17192 */
17193 if (mips_pic == NO_PIC && (!compact_known || compact))
17194 length += 2;
17195
17196 /* If assembling PIC code, we further turn:
17197
17198 j label # 4 bytes
17199
17200 into:
17201
17202 lw/ld at, %got(label)(gp) # 4 bytes
17203 d/addiu at, %lo(label) # 4 bytes
17204 jr/c at # 2 bytes
17205 */
17206 if (mips_pic != NO_PIC)
17207 length += 6;
17208
17209 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17210
17211 <brneg> 0f # 4 bytes
17212 nop # 2 bytes if !compact
17213 */
17214 if (!uncond)
17215 length += (compact_known && compact) ? 4 : 6;
17216 }
17217
17218 return length;
17219}
17220
17221/* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17222 bit accordingly. */
17223
17224static int
17225relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17226{
17227 bfd_boolean toofar;
17228
17229 if (RELAX_MICROMIPS_U16BIT (fragp->fr_subtype))
17230 return 2;
17231
17232 if (fragp
17233 && S_IS_DEFINED (fragp->fr_symbol)
17234 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17235 {
17236 addressT addr;
17237 offsetT val;
17238 int type;
17239
17240 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17241 /* Ignore the low bit in the target, since it will be set
17242 for a text label. */
17243 if ((val & 1) != 0)
17244 --val;
17245
17246 /* Assume this is a 2-byte branch. */
17247 addr = fragp->fr_address + fragp->fr_fix + 2;
17248
17249 /* We try to avoid the infinite loop by not adding 2 more bytes for
17250 long branches. */
17251
17252 val -= addr;
17253
17254 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17255 if (type == 'D')
17256 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17257 else if (type == 'E')
17258 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17259 else
17260 abort ();
17261 }
17262 else
17263 /* If the symbol is not defined or it's in a different segment,
17264 we emit a normal 32-bit branch. */
17265 toofar = TRUE;
17266
17267 if (fragp && update
17268 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17269 fragp->fr_subtype
17270 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17271 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17272
17273 if (toofar)
17274 return 4;
17275
17276 return 2;
17277}
17278
252b5132
RH
17279/* Estimate the size of a frag before relaxing. Unless this is the
17280 mips16, we are not really relaxing here, and the final size is
17281 encoded in the subtype information. For the mips16, we have to
17282 decide whether we are using an extended opcode or not. */
17283
252b5132 17284int
17a2f251 17285md_estimate_size_before_relax (fragS *fragp, asection *segtype)
252b5132 17286{
5919d012 17287 int change;
252b5132 17288
4a6a3df4
AO
17289 if (RELAX_BRANCH_P (fragp->fr_subtype))
17290 {
17291
b34976b6
AM
17292 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17293
4a6a3df4
AO
17294 return fragp->fr_var;
17295 }
17296
252b5132 17297 if (RELAX_MIPS16_P (fragp->fr_subtype))
177b4a6a
AO
17298 /* We don't want to modify the EXTENDED bit here; it might get us
17299 into infinite loops. We change it only in mips_relax_frag(). */
17300 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
252b5132 17301
df58fc94
RS
17302 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17303 {
17304 int length = 4;
17305
17306 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17307 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17308 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17309 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17310 fragp->fr_var = length;
17311
17312 return length;
17313 }
17314
252b5132 17315 if (mips_pic == NO_PIC)
5919d012 17316 change = nopic_need_relax (fragp->fr_symbol, 0);
252b5132 17317 else if (mips_pic == SVR4_PIC)
5919d012 17318 change = pic_need_relax (fragp->fr_symbol, segtype);
0a44bf69
RS
17319 else if (mips_pic == VXWORKS_PIC)
17320 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17321 change = 0;
252b5132
RH
17322 else
17323 abort ();
17324
17325 if (change)
17326 {
4d7206a2 17327 fragp->fr_subtype |= RELAX_USE_SECOND;
4d7206a2 17328 return -RELAX_FIRST (fragp->fr_subtype);
252b5132 17329 }
4d7206a2
RS
17330 else
17331 return -RELAX_SECOND (fragp->fr_subtype);
252b5132
RH
17332}
17333
17334/* This is called to see whether a reloc against a defined symbol
de7e6852 17335 should be converted into a reloc against a section. */
252b5132
RH
17336
17337int
17a2f251 17338mips_fix_adjustable (fixS *fixp)
252b5132 17339{
252b5132
RH
17340 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17341 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17342 return 0;
a161fe53 17343
252b5132
RH
17344 if (fixp->fx_addsy == NULL)
17345 return 1;
a161fe53 17346
de7e6852
RS
17347 /* If symbol SYM is in a mergeable section, relocations of the form
17348 SYM + 0 can usually be made section-relative. The mergeable data
17349 is then identified by the section offset rather than by the symbol.
17350
17351 However, if we're generating REL LO16 relocations, the offset is split
17352 between the LO16 and parterning high part relocation. The linker will
17353 need to recalculate the complete offset in order to correctly identify
17354 the merge data.
17355
17356 The linker has traditionally not looked for the parterning high part
17357 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17358 placed anywhere. Rather than break backwards compatibility by changing
17359 this, it seems better not to force the issue, and instead keep the
17360 original symbol. This will work with either linker behavior. */
738e5348 17361 if ((lo16_reloc_p (fixp->fx_r_type)
704803a9 17362 || reloc_needs_lo_p (fixp->fx_r_type))
de7e6852
RS
17363 && HAVE_IN_PLACE_ADDENDS
17364 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17365 return 0;
17366
ce70d90a
MR
17367 /* There is no place to store an in-place offset for JALR relocations.
17368 Likewise an in-range offset of PC-relative relocations may overflow
17369 the in-place relocatable field if recalculated against the start
17370 address of the symbol's containing section. */
17371 if (HAVE_IN_PLACE_ADDENDS
df58fc94 17372 && (fixp->fx_pcrel || jalr_reloc_p (fixp->fx_r_type)))
1180b5a4
RS
17373 return 0;
17374
252b5132 17375#ifdef OBJ_ELF
b314ec0e
RS
17376 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17377 to a floating-point stub. The same is true for non-R_MIPS16_26
17378 relocations against MIPS16 functions; in this case, the stub becomes
17379 the function's canonical address.
17380
17381 Floating-point stubs are stored in unique .mips16.call.* or
17382 .mips16.fn.* sections. If a stub T for function F is in section S,
17383 the first relocation in section S must be against F; this is how the
17384 linker determines the target function. All relocations that might
17385 resolve to T must also be against F. We therefore have the following
17386 restrictions, which are given in an intentionally-redundant way:
17387
17388 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17389 symbols.
17390
17391 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17392 if that stub might be used.
17393
17394 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17395 symbols.
17396
17397 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17398 that stub might be used.
17399
17400 There is a further restriction:
17401
df58fc94
RS
17402 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17403 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17404 targets with in-place addends; the relocation field cannot
b314ec0e
RS
17405 encode the low bit.
17406
df58fc94
RS
17407 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17408 against a MIPS16 symbol. We deal with (5) by by not reducing any
17409 such relocations on REL targets.
b314ec0e
RS
17410
17411 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17412 relocation against some symbol R, no relocation against R may be
17413 reduced. (Note that this deals with (2) as well as (1) because
17414 relocations against global symbols will never be reduced on ELF
17415 targets.) This approach is a little simpler than trying to detect
17416 stub sections, and gives the "all or nothing" per-symbol consistency
17417 that we have for MIPS16 symbols. */
f43abd2b 17418 if (IS_ELF
b314ec0e 17419 && fixp->fx_subsy == NULL
30c09090 17420 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
df58fc94
RS
17421 || *symbol_get_tc (fixp->fx_addsy)
17422 || (HAVE_IN_PLACE_ADDENDS
17423 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17424 && jmp_reloc_p (fixp->fx_r_type))))
252b5132
RH
17425 return 0;
17426#endif
a161fe53 17427
252b5132
RH
17428 return 1;
17429}
17430
17431/* Translate internal representation of relocation info to BFD target
17432 format. */
17433
17434arelent **
17a2f251 17435tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH
17436{
17437 static arelent *retval[4];
17438 arelent *reloc;
17439 bfd_reloc_code_real_type code;
17440
4b0cff4e
TS
17441 memset (retval, 0, sizeof(retval));
17442 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
49309057
ILT
17443 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
17444 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH
17445 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17446
bad36eac
DJ
17447 if (fixp->fx_pcrel)
17448 {
df58fc94
RS
17449 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17450 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17451 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17452 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
bad36eac
DJ
17453
17454 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17455 Relocations want only the symbol offset. */
17456 reloc->addend = fixp->fx_addnumber + reloc->address;
f43abd2b 17457 if (!IS_ELF)
bad36eac
DJ
17458 {
17459 /* A gruesome hack which is a result of the gruesome gas
17460 reloc handling. What's worse, for COFF (as opposed to
17461 ECOFF), we might need yet another copy of reloc->address.
17462 See bfd_install_relocation. */
17463 reloc->addend += reloc->address;
17464 }
17465 }
17466 else
17467 reloc->addend = fixp->fx_addnumber;
252b5132 17468
438c16b8
TS
17469 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17470 entry to be used in the relocation's section offset. */
17471 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
252b5132
RH
17472 {
17473 reloc->address = reloc->addend;
17474 reloc->addend = 0;
17475 }
17476
252b5132 17477 code = fixp->fx_r_type;
252b5132 17478
bad36eac 17479 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
252b5132
RH
17480 if (reloc->howto == NULL)
17481 {
17482 as_bad_where (fixp->fx_file, fixp->fx_line,
17483 _("Can not represent %s relocation in this object file format"),
17484 bfd_get_reloc_code_name (code));
17485 retval[0] = NULL;
17486 }
17487
17488 return retval;
17489}
17490
17491/* Relax a machine dependent frag. This returns the amount by which
17492 the current size of the frag should change. */
17493
17494int
17a2f251 17495mips_relax_frag (asection *sec, fragS *fragp, long stretch)
252b5132 17496{
4a6a3df4
AO
17497 if (RELAX_BRANCH_P (fragp->fr_subtype))
17498 {
17499 offsetT old_var = fragp->fr_var;
b34976b6
AM
17500
17501 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
4a6a3df4
AO
17502
17503 return fragp->fr_var - old_var;
17504 }
17505
df58fc94
RS
17506 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17507 {
17508 offsetT old_var = fragp->fr_var;
17509 offsetT new_var = 4;
17510
17511 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17512 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
17513 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17514 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
17515 fragp->fr_var = new_var;
17516
17517 return new_var - old_var;
17518 }
17519
252b5132
RH
17520 if (! RELAX_MIPS16_P (fragp->fr_subtype))
17521 return 0;
17522
c4e7957c 17523 if (mips16_extended_frag (fragp, NULL, stretch))
252b5132
RH
17524 {
17525 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17526 return 0;
17527 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
17528 return 2;
17529 }
17530 else
17531 {
17532 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17533 return 0;
17534 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
17535 return -2;
17536 }
17537
17538 return 0;
17539}
17540
17541/* Convert a machine dependent frag. */
17542
17543void
17a2f251 17544md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
252b5132 17545{
4a6a3df4
AO
17546 if (RELAX_BRANCH_P (fragp->fr_subtype))
17547 {
17548 bfd_byte *buf;
17549 unsigned long insn;
17550 expressionS exp;
17551 fixS *fixp;
b34976b6 17552
4a6a3df4
AO
17553 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
17554
17555 if (target_big_endian)
17556 insn = bfd_getb32 (buf);
17557 else
17558 insn = bfd_getl32 (buf);
b34976b6 17559
4a6a3df4
AO
17560 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17561 {
17562 /* We generate a fixup instead of applying it right now
17563 because, if there are linker relaxations, we're going to
17564 need the relocations. */
17565 exp.X_op = O_symbol;
17566 exp.X_add_symbol = fragp->fr_symbol;
17567 exp.X_add_number = fragp->fr_offset;
17568
17569 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3994f87e 17570 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
4a6a3df4
AO
17571 fixp->fx_file = fragp->fr_file;
17572 fixp->fx_line = fragp->fr_line;
b34976b6 17573
2132e3a3 17574 md_number_to_chars ((char *) buf, insn, 4);
4a6a3df4
AO
17575 buf += 4;
17576 }
17577 else
17578 {
17579 int i;
17580
17581 as_warn_where (fragp->fr_file, fragp->fr_line,
5c4f07ba 17582 _("Relaxed out-of-range branch into a jump"));
4a6a3df4
AO
17583
17584 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
17585 goto uncond;
17586
17587 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17588 {
17589 /* Reverse the branch. */
17590 switch ((insn >> 28) & 0xf)
17591 {
17592 case 4:
17593 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
17594 have the condition reversed by tweaking a single
17595 bit, and their opcodes all have 0x4???????. */
9c2799c2 17596 gas_assert ((insn & 0xf1000000) == 0x41000000);
4a6a3df4
AO
17597 insn ^= 0x00010000;
17598 break;
17599
17600 case 0:
17601 /* bltz 0x04000000 bgez 0x04010000
54f4ddb3 17602 bltzal 0x04100000 bgezal 0x04110000 */
9c2799c2 17603 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
4a6a3df4
AO
17604 insn ^= 0x00010000;
17605 break;
b34976b6 17606
4a6a3df4
AO
17607 case 1:
17608 /* beq 0x10000000 bne 0x14000000
54f4ddb3 17609 blez 0x18000000 bgtz 0x1c000000 */
4a6a3df4
AO
17610 insn ^= 0x04000000;
17611 break;
17612
17613 default:
17614 abort ();
17615 }
17616 }
17617
17618 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17619 {
17620 /* Clear the and-link bit. */
9c2799c2 17621 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
4a6a3df4 17622
54f4ddb3
TS
17623 /* bltzal 0x04100000 bgezal 0x04110000
17624 bltzall 0x04120000 bgezall 0x04130000 */
4a6a3df4
AO
17625 insn &= ~0x00100000;
17626 }
17627
17628 /* Branch over the branch (if the branch was likely) or the
17629 full jump (not likely case). Compute the offset from the
17630 current instruction to branch to. */
17631 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17632 i = 16;
17633 else
17634 {
17635 /* How many bytes in instructions we've already emitted? */
17636 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
17637 /* How many bytes in instructions from here to the end? */
17638 i = fragp->fr_var - i;
17639 }
17640 /* Convert to instruction count. */
17641 i >>= 2;
17642 /* Branch counts from the next instruction. */
b34976b6 17643 i--;
4a6a3df4
AO
17644 insn |= i;
17645 /* Branch over the jump. */
2132e3a3 17646 md_number_to_chars ((char *) buf, insn, 4);
4a6a3df4
AO
17647 buf += 4;
17648
54f4ddb3 17649 /* nop */
2132e3a3 17650 md_number_to_chars ((char *) buf, 0, 4);
4a6a3df4
AO
17651 buf += 4;
17652
17653 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17654 {
17655 /* beql $0, $0, 2f */
17656 insn = 0x50000000;
17657 /* Compute the PC offset from the current instruction to
17658 the end of the variable frag. */
17659 /* How many bytes in instructions we've already emitted? */
17660 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
17661 /* How many bytes in instructions from here to the end? */
17662 i = fragp->fr_var - i;
17663 /* Convert to instruction count. */
17664 i >>= 2;
17665 /* Don't decrement i, because we want to branch over the
17666 delay slot. */
17667
17668 insn |= i;
2132e3a3 17669 md_number_to_chars ((char *) buf, insn, 4);
4a6a3df4
AO
17670 buf += 4;
17671
2132e3a3 17672 md_number_to_chars ((char *) buf, 0, 4);
4a6a3df4
AO
17673 buf += 4;
17674 }
17675
17676 uncond:
17677 if (mips_pic == NO_PIC)
17678 {
17679 /* j or jal. */
17680 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
17681 ? 0x0c000000 : 0x08000000);
17682 exp.X_op = O_symbol;
17683 exp.X_add_symbol = fragp->fr_symbol;
17684 exp.X_add_number = fragp->fr_offset;
17685
17686 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3994f87e 17687 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
4a6a3df4
AO
17688 fixp->fx_file = fragp->fr_file;
17689 fixp->fx_line = fragp->fr_line;
17690
2132e3a3 17691 md_number_to_chars ((char *) buf, insn, 4);
4a6a3df4
AO
17692 buf += 4;
17693 }
17694 else
17695 {
66b3e8da
MR
17696 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
17697
4a6a3df4 17698 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
66b3e8da
MR
17699 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
17700 insn |= at << OP_SH_RT;
4a6a3df4
AO
17701 exp.X_op = O_symbol;
17702 exp.X_add_symbol = fragp->fr_symbol;
17703 exp.X_add_number = fragp->fr_offset;
17704
17705 if (fragp->fr_offset)
17706 {
17707 exp.X_add_symbol = make_expr_symbol (&exp);
17708 exp.X_add_number = 0;
17709 }
17710
17711 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3994f87e 17712 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
4a6a3df4
AO
17713 fixp->fx_file = fragp->fr_file;
17714 fixp->fx_line = fragp->fr_line;
17715
2132e3a3 17716 md_number_to_chars ((char *) buf, insn, 4);
4a6a3df4 17717 buf += 4;
b34976b6 17718
4a6a3df4
AO
17719 if (mips_opts.isa == ISA_MIPS1)
17720 {
17721 /* nop */
2132e3a3 17722 md_number_to_chars ((char *) buf, 0, 4);
4a6a3df4
AO
17723 buf += 4;
17724 }
17725
17726 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
66b3e8da
MR
17727 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
17728 insn |= at << OP_SH_RS | at << OP_SH_RT;
4a6a3df4
AO
17729
17730 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3994f87e 17731 4, &exp, FALSE, BFD_RELOC_LO16);
4a6a3df4
AO
17732 fixp->fx_file = fragp->fr_file;
17733 fixp->fx_line = fragp->fr_line;
b34976b6 17734
2132e3a3 17735 md_number_to_chars ((char *) buf, insn, 4);
4a6a3df4
AO
17736 buf += 4;
17737
17738 /* j(al)r $at. */
17739 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
66b3e8da 17740 insn = 0x0000f809;
4a6a3df4 17741 else
66b3e8da
MR
17742 insn = 0x00000008;
17743 insn |= at << OP_SH_RS;
4a6a3df4 17744
2132e3a3 17745 md_number_to_chars ((char *) buf, insn, 4);
4a6a3df4
AO
17746 buf += 4;
17747 }
17748 }
17749
9c2799c2 17750 gas_assert (buf == (bfd_byte *)fragp->fr_literal
4a6a3df4
AO
17751 + fragp->fr_fix + fragp->fr_var);
17752
17753 fragp->fr_fix += fragp->fr_var;
17754
17755 return;
17756 }
17757
df58fc94
RS
17758 /* Relax microMIPS branches. */
17759 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17760 {
17761 bfd_byte *buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
17762 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17763 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
17764 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
2309ddf2 17765 bfd_boolean short_ds;
df58fc94
RS
17766 unsigned long insn;
17767 expressionS exp;
17768 fixS *fixp;
17769
17770 exp.X_op = O_symbol;
17771 exp.X_add_symbol = fragp->fr_symbol;
17772 exp.X_add_number = fragp->fr_offset;
17773
17774 fragp->fr_fix += fragp->fr_var;
17775
17776 /* Handle 16-bit branches that fit or are forced to fit. */
17777 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17778 {
17779 /* We generate a fixup instead of applying it right now,
17780 because if there is linker relaxation, we're going to
17781 need the relocations. */
17782 if (type == 'D')
17783 fixp = fix_new_exp (fragp,
17784 buf - (bfd_byte *) fragp->fr_literal,
17785 2, &exp, TRUE,
17786 BFD_RELOC_MICROMIPS_10_PCREL_S1);
17787 else if (type == 'E')
17788 fixp = fix_new_exp (fragp,
17789 buf - (bfd_byte *) fragp->fr_literal,
17790 2, &exp, TRUE,
17791 BFD_RELOC_MICROMIPS_7_PCREL_S1);
17792 else
17793 abort ();
17794
17795 fixp->fx_file = fragp->fr_file;
17796 fixp->fx_line = fragp->fr_line;
17797
17798 /* These relocations can have an addend that won't fit in
17799 2 octets. */
17800 fixp->fx_no_overflow = 1;
17801
17802 return;
17803 }
17804
2309ddf2 17805 /* Handle 32-bit branches that fit or are forced to fit. */
df58fc94
RS
17806 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17807 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17808 {
17809 /* We generate a fixup instead of applying it right now,
17810 because if there is linker relaxation, we're going to
17811 need the relocations. */
17812 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
17813 4, &exp, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
17814 fixp->fx_file = fragp->fr_file;
17815 fixp->fx_line = fragp->fr_line;
17816
17817 if (type == 0)
17818 return;
17819 }
17820
17821 /* Relax 16-bit branches to 32-bit branches. */
17822 if (type != 0)
17823 {
17824 if (target_big_endian)
17825 insn = bfd_getb16 (buf);
17826 else
17827 insn = bfd_getl16 (buf);
17828
17829 if ((insn & 0xfc00) == 0xcc00) /* b16 */
17830 insn = 0x94000000; /* beq */
17831 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
17832 {
17833 unsigned long regno;
17834
17835 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
17836 regno = micromips_to_32_reg_d_map [regno];
17837 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
17838 insn |= regno << MICROMIPSOP_SH_RS;
17839 }
17840 else
17841 abort ();
17842
17843 /* Nothing else to do, just write it out. */
17844 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17845 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17846 {
17847 md_number_to_chars ((char *) buf, insn >> 16, 2);
17848 buf += 2;
17849 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
17850 buf += 2;
17851
17852 gas_assert (buf == ((bfd_byte *) fragp->fr_literal
17853 + fragp->fr_fix));
17854 return;
17855 }
17856 }
17857 else
17858 {
17859 unsigned long next;
17860
17861 if (target_big_endian)
17862 {
17863 insn = bfd_getb16 (buf);
17864 next = bfd_getb16 (buf + 2);
17865 }
17866 else
17867 {
17868 insn = bfd_getl16 (buf);
17869 next = bfd_getl16 (buf + 2);
17870 }
17871 insn = (insn << 16) | next;
17872 }
17873
17874 /* Relax 32-bit branches to a sequence of instructions. */
17875 as_warn_where (fragp->fr_file, fragp->fr_line,
17876 _("Relaxed out-of-range branch into a jump"));
17877
2309ddf2
MR
17878 /* Set the short-delay-slot bit. */
17879 short_ds = al && (insn & 0x02000000) != 0;
df58fc94
RS
17880
17881 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
17882 {
17883 symbolS *l;
17884
17885 /* Reverse the branch. */
17886 if ((insn & 0xfc000000) == 0x94000000 /* beq */
17887 || (insn & 0xfc000000) == 0xb4000000) /* bne */
17888 insn ^= 0x20000000;
17889 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
17890 || (insn & 0xffe00000) == 0x40400000 /* bgez */
17891 || (insn & 0xffe00000) == 0x40800000 /* blez */
17892 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
17893 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
17894 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
17895 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
17896 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
17897 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
17898 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
17899 insn ^= 0x00400000;
17900 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
17901 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
17902 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
17903 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
17904 insn ^= 0x00200000;
17905 else
17906 abort ();
17907
17908 if (al)
17909 {
17910 /* Clear the and-link and short-delay-slot bits. */
17911 gas_assert ((insn & 0xfda00000) == 0x40200000);
17912
17913 /* bltzal 0x40200000 bgezal 0x40600000 */
17914 /* bltzals 0x42200000 bgezals 0x42600000 */
17915 insn &= ~0x02200000;
17916 }
17917
17918 /* Make a label at the end for use with the branch. */
17919 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
17920 micromips_label_inc ();
17921#if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
17922 if (IS_ELF)
17923 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
17924#endif
17925
17926 /* Refer to it. */
17927 fixp = fix_new (fragp, buf - (bfd_byte *) fragp->fr_literal,
17928 4, l, 0, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
17929 fixp->fx_file = fragp->fr_file;
17930 fixp->fx_line = fragp->fr_line;
17931
17932 /* Branch over the jump. */
17933 md_number_to_chars ((char *) buf, insn >> 16, 2);
17934 buf += 2;
17935 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
17936 buf += 2;
17937
17938 if (!compact)
17939 {
17940 /* nop */
17941 insn = 0x0c00;
17942 md_number_to_chars ((char *) buf, insn, 2);
17943 buf += 2;
17944 }
17945 }
17946
17947 if (mips_pic == NO_PIC)
17948 {
2309ddf2
MR
17949 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
17950
df58fc94
RS
17951 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
17952 insn = al ? jal : 0xd4000000;
17953
17954 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
17955 4, &exp, FALSE, BFD_RELOC_MICROMIPS_JMP);
17956 fixp->fx_file = fragp->fr_file;
17957 fixp->fx_line = fragp->fr_line;
17958
17959 md_number_to_chars ((char *) buf, insn >> 16, 2);
17960 buf += 2;
17961 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
17962 buf += 2;
17963
17964 if (compact)
17965 {
17966 /* nop */
17967 insn = 0x0c00;
17968 md_number_to_chars ((char *) buf, insn, 2);
17969 buf += 2;
17970 }
17971 }
17972 else
17973 {
17974 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
2309ddf2
MR
17975 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
17976 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
df58fc94
RS
17977
17978 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
17979 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
17980 insn |= at << MICROMIPSOP_SH_RT;
17981
17982 if (exp.X_add_number)
17983 {
17984 exp.X_add_symbol = make_expr_symbol (&exp);
17985 exp.X_add_number = 0;
17986 }
17987
17988 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
17989 4, &exp, FALSE, BFD_RELOC_MICROMIPS_GOT16);
17990 fixp->fx_file = fragp->fr_file;
17991 fixp->fx_line = fragp->fr_line;
17992
17993 md_number_to_chars ((char *) buf, insn >> 16, 2);
17994 buf += 2;
17995 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
17996 buf += 2;
17997
17998 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
17999 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18000 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18001
18002 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
18003 4, &exp, FALSE, BFD_RELOC_MICROMIPS_LO16);
18004 fixp->fx_file = fragp->fr_file;
18005 fixp->fx_line = fragp->fr_line;
18006
18007 md_number_to_chars ((char *) buf, insn >> 16, 2);
18008 buf += 2;
18009 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18010 buf += 2;
18011
18012 /* jr/jrc/jalr/jalrs $at */
18013 insn = al ? jalr : jr;
18014 insn |= at << MICROMIPSOP_SH_MJ;
18015
18016 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18017 buf += 2;
18018 }
18019
18020 gas_assert (buf == (bfd_byte *) fragp->fr_literal + fragp->fr_fix);
18021 return;
18022 }
18023
252b5132
RH
18024 if (RELAX_MIPS16_P (fragp->fr_subtype))
18025 {
18026 int type;
3994f87e 18027 const struct mips16_immed_operand *op;
b34976b6 18028 bfd_boolean small, ext;
252b5132
RH
18029 offsetT val;
18030 bfd_byte *buf;
18031 unsigned long insn;
b34976b6 18032 bfd_boolean use_extend;
252b5132
RH
18033 unsigned short extend;
18034
18035 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18036 op = mips16_immed_operands;
18037 while (op->type != type)
18038 ++op;
18039
18040 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18041 {
b34976b6
AM
18042 small = FALSE;
18043 ext = TRUE;
252b5132
RH
18044 }
18045 else
18046 {
b34976b6
AM
18047 small = TRUE;
18048 ext = FALSE;
252b5132
RH
18049 }
18050
5f5f22c0 18051 val = resolve_symbol_value (fragp->fr_symbol);
252b5132
RH
18052 if (op->pcrel)
18053 {
18054 addressT addr;
18055
18056 addr = fragp->fr_address + fragp->fr_fix;
18057
18058 /* The rules for the base address of a PC relative reloc are
18059 complicated; see mips16_extended_frag. */
18060 if (type == 'p' || type == 'q')
18061 {
18062 addr += 2;
18063 if (ext)
18064 addr += 2;
18065 /* Ignore the low bit in the target, since it will be
18066 set for a text label. */
18067 if ((val & 1) != 0)
18068 --val;
18069 }
18070 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18071 addr -= 4;
18072 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18073 addr -= 2;
18074
18075 addr &= ~ (addressT) ((1 << op->shift) - 1);
18076 val -= addr;
18077
18078 /* Make sure the section winds up with the alignment we have
18079 assumed. */
18080 if (op->shift > 0)
18081 record_alignment (asec, op->shift);
18082 }
18083
18084 if (ext
18085 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18086 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18087 as_warn_where (fragp->fr_file, fragp->fr_line,
18088 _("extended instruction in delay slot"));
18089
18090 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
18091
18092 if (target_big_endian)
18093 insn = bfd_getb16 (buf);
18094 else
18095 insn = bfd_getl16 (buf);
18096
18097 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
18098 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
18099 small, ext, &insn, &use_extend, &extend);
18100
18101 if (use_extend)
18102 {
2132e3a3 18103 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
252b5132
RH
18104 fragp->fr_fix += 2;
18105 buf += 2;
18106 }
18107
2132e3a3 18108 md_number_to_chars ((char *) buf, insn, 2);
252b5132
RH
18109 fragp->fr_fix += 2;
18110 buf += 2;
18111 }
18112 else
18113 {
df58fc94
RS
18114 relax_substateT subtype = fragp->fr_subtype;
18115 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18116 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
4d7206a2
RS
18117 int first, second;
18118 fixS *fixp;
252b5132 18119
df58fc94
RS
18120 first = RELAX_FIRST (subtype);
18121 second = RELAX_SECOND (subtype);
4d7206a2 18122 fixp = (fixS *) fragp->fr_opcode;
252b5132 18123
df58fc94
RS
18124 /* If the delay slot chosen does not match the size of the instruction,
18125 then emit a warning. */
18126 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18127 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18128 {
18129 relax_substateT s;
18130 const char *msg;
18131
18132 s = subtype & (RELAX_DELAY_SLOT_16BIT
18133 | RELAX_DELAY_SLOT_SIZE_FIRST
18134 | RELAX_DELAY_SLOT_SIZE_SECOND);
18135 msg = macro_warning (s);
18136 if (msg != NULL)
18137 as_warn_where (fragp->fr_file, fragp->fr_line, msg);
18138 subtype &= ~s;
18139 }
18140
584892a6 18141 /* Possibly emit a warning if we've chosen the longer option. */
df58fc94 18142 if (use_second == second_longer)
584892a6 18143 {
df58fc94
RS
18144 relax_substateT s;
18145 const char *msg;
18146
18147 s = (subtype
18148 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18149 msg = macro_warning (s);
18150 if (msg != NULL)
18151 as_warn_where (fragp->fr_file, fragp->fr_line, msg);
18152 subtype &= ~s;
584892a6
RS
18153 }
18154
4d7206a2
RS
18155 /* Go through all the fixups for the first sequence. Disable them
18156 (by marking them as done) if we're going to use the second
18157 sequence instead. */
18158 while (fixp
18159 && fixp->fx_frag == fragp
18160 && fixp->fx_where < fragp->fr_fix - second)
18161 {
df58fc94 18162 if (subtype & RELAX_USE_SECOND)
4d7206a2
RS
18163 fixp->fx_done = 1;
18164 fixp = fixp->fx_next;
18165 }
252b5132 18166
4d7206a2
RS
18167 /* Go through the fixups for the second sequence. Disable them if
18168 we're going to use the first sequence, otherwise adjust their
18169 addresses to account for the relaxation. */
18170 while (fixp && fixp->fx_frag == fragp)
18171 {
df58fc94 18172 if (subtype & RELAX_USE_SECOND)
4d7206a2
RS
18173 fixp->fx_where -= first;
18174 else
18175 fixp->fx_done = 1;
18176 fixp = fixp->fx_next;
18177 }
18178
18179 /* Now modify the frag contents. */
df58fc94 18180 if (subtype & RELAX_USE_SECOND)
4d7206a2
RS
18181 {
18182 char *start;
18183
18184 start = fragp->fr_literal + fragp->fr_fix - first - second;
18185 memmove (start, start + first, second);
18186 fragp->fr_fix -= first;
18187 }
18188 else
18189 fragp->fr_fix -= second;
252b5132
RH
18190 }
18191}
18192
18193#ifdef OBJ_ELF
18194
18195/* This function is called after the relocs have been generated.
18196 We've been storing mips16 text labels as odd. Here we convert them
18197 back to even for the convenience of the debugger. */
18198
18199void
17a2f251 18200mips_frob_file_after_relocs (void)
252b5132
RH
18201{
18202 asymbol **syms;
18203 unsigned int count, i;
18204
f43abd2b 18205 if (!IS_ELF)
252b5132
RH
18206 return;
18207
18208 syms = bfd_get_outsymbols (stdoutput);
18209 count = bfd_get_symcount (stdoutput);
18210 for (i = 0; i < count; i++, syms++)
df58fc94
RS
18211 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18212 && ((*syms)->value & 1) != 0)
18213 {
18214 (*syms)->value &= ~1;
18215 /* If the symbol has an odd size, it was probably computed
18216 incorrectly, so adjust that as well. */
18217 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18218 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18219 }
252b5132
RH
18220}
18221
18222#endif
18223
a1facbec
MR
18224/* This function is called whenever a label is defined, including fake
18225 labels instantiated off the dot special symbol. It is used when
18226 handling branch delays; if a branch has a label, we assume we cannot
18227 move it. This also bumps the value of the symbol by 1 in compressed
18228 code. */
252b5132
RH
18229
18230void
a1facbec 18231mips_record_label (symbolS *sym)
252b5132 18232{
a8dbcb85 18233 segment_info_type *si = seg_info (now_seg);
252b5132
RH
18234 struct insn_label_list *l;
18235
18236 if (free_insn_labels == NULL)
18237 l = (struct insn_label_list *) xmalloc (sizeof *l);
18238 else
18239 {
18240 l = free_insn_labels;
18241 free_insn_labels = l->next;
18242 }
18243
18244 l->label = sym;
a8dbcb85
TS
18245 l->next = si->label_list;
18246 si->label_list = l;
a1facbec 18247}
07a53e5c 18248
a1facbec
MR
18249/* This function is called as tc_frob_label() whenever a label is defined
18250 and adds a DWARF-2 record we only want for true labels. */
18251
18252void
18253mips_define_label (symbolS *sym)
18254{
18255 mips_record_label (sym);
07a53e5c
RH
18256#ifdef OBJ_ELF
18257 dwarf2_emit_label (sym);
18258#endif
252b5132
RH
18259}
18260\f
18261#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18262
18263/* Some special processing for a MIPS ELF file. */
18264
18265void
17a2f251 18266mips_elf_final_processing (void)
252b5132
RH
18267{
18268 /* Write out the register information. */
316f5878 18269 if (mips_abi != N64_ABI)
252b5132
RH
18270 {
18271 Elf32_RegInfo s;
18272
18273 s.ri_gprmask = mips_gprmask;
18274 s.ri_cprmask[0] = mips_cprmask[0];
18275 s.ri_cprmask[1] = mips_cprmask[1];
18276 s.ri_cprmask[2] = mips_cprmask[2];
18277 s.ri_cprmask[3] = mips_cprmask[3];
18278 /* The gp_value field is set by the MIPS ELF backend. */
18279
18280 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18281 ((Elf32_External_RegInfo *)
18282 mips_regmask_frag));
18283 }
18284 else
18285 {
18286 Elf64_Internal_RegInfo s;
18287
18288 s.ri_gprmask = mips_gprmask;
18289 s.ri_pad = 0;
18290 s.ri_cprmask[0] = mips_cprmask[0];
18291 s.ri_cprmask[1] = mips_cprmask[1];
18292 s.ri_cprmask[2] = mips_cprmask[2];
18293 s.ri_cprmask[3] = mips_cprmask[3];
18294 /* The gp_value field is set by the MIPS ELF backend. */
18295
18296 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18297 ((Elf64_External_RegInfo *)
18298 mips_regmask_frag));
18299 }
18300
18301 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18302 sort of BFD interface for this. */
18303 if (mips_any_noreorder)
18304 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18305 if (mips_pic != NO_PIC)
143d77c5 18306 {
252b5132 18307 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
143d77c5
EC
18308 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18309 }
18310 if (mips_abicalls)
18311 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
252b5132 18312
98d3f06f 18313 /* Set MIPS ELF flags for ASEs. */
74cd071d
CF
18314 /* We may need to define a new flag for DSP ASE, and set this flag when
18315 file_ase_dsp is true. */
8b082fb1 18316 /* Same for DSP R2. */
ef2e4d86
CF
18317 /* We may need to define a new flag for MT ASE, and set this flag when
18318 file_ase_mt is true. */
a4672219
TS
18319 if (file_ase_mips16)
18320 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
df58fc94
RS
18321 if (file_ase_micromips)
18322 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
1f25f5d3
CD
18323#if 0 /* XXX FIXME */
18324 if (file_ase_mips3d)
18325 elf_elfheader (stdoutput)->e_flags |= ???;
18326#endif
deec1734
CD
18327 if (file_ase_mdmx)
18328 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
1f25f5d3 18329
bdaaa2e1 18330 /* Set the MIPS ELF ABI flags. */
316f5878 18331 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
252b5132 18332 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
316f5878 18333 else if (mips_abi == O64_ABI)
252b5132 18334 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
316f5878 18335 else if (mips_abi == EABI_ABI)
252b5132 18336 {
316f5878 18337 if (!file_mips_gp32)
252b5132
RH
18338 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18339 else
18340 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18341 }
316f5878 18342 else if (mips_abi == N32_ABI)
be00bddd
TS
18343 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18344
c9914766 18345 /* Nothing to do for N64_ABI. */
252b5132
RH
18346
18347 if (mips_32bitmode)
18348 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
ad3fea08
TS
18349
18350#if 0 /* XXX FIXME */
18351 /* 32 bit code with 64 bit FP registers. */
18352 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
18353 elf_elfheader (stdoutput)->e_flags |= ???;
18354#endif
252b5132
RH
18355}
18356
18357#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18358\f
beae10d5 18359typedef struct proc {
9b2f1d35
EC
18360 symbolS *func_sym;
18361 symbolS *func_end_sym;
beae10d5
KH
18362 unsigned long reg_mask;
18363 unsigned long reg_offset;
18364 unsigned long fpreg_mask;
18365 unsigned long fpreg_offset;
18366 unsigned long frame_offset;
18367 unsigned long frame_reg;
18368 unsigned long pc_reg;
18369} procS;
252b5132
RH
18370
18371static procS cur_proc;
18372static procS *cur_proc_ptr;
18373static int numprocs;
18374
df58fc94
RS
18375/* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18376 as "2", and a normal nop as "0". */
18377
18378#define NOP_OPCODE_MIPS 0
18379#define NOP_OPCODE_MIPS16 1
18380#define NOP_OPCODE_MICROMIPS 2
742a56fe
RS
18381
18382char
18383mips_nop_opcode (void)
18384{
df58fc94
RS
18385 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18386 return NOP_OPCODE_MICROMIPS;
18387 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18388 return NOP_OPCODE_MIPS16;
18389 else
18390 return NOP_OPCODE_MIPS;
742a56fe
RS
18391}
18392
df58fc94
RS
18393/* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18394 32-bit microMIPS NOPs here (if applicable). */
a19d8eb0 18395
0a9ef439 18396void
17a2f251 18397mips_handle_align (fragS *fragp)
a19d8eb0 18398{
df58fc94 18399 char nop_opcode;
742a56fe 18400 char *p;
c67a084a
NC
18401 int bytes, size, excess;
18402 valueT opcode;
742a56fe 18403
0a9ef439
RH
18404 if (fragp->fr_type != rs_align_code)
18405 return;
18406
742a56fe 18407 p = fragp->fr_literal + fragp->fr_fix;
df58fc94
RS
18408 nop_opcode = *p;
18409 switch (nop_opcode)
a19d8eb0 18410 {
df58fc94
RS
18411 case NOP_OPCODE_MICROMIPS:
18412 opcode = micromips_nop32_insn.insn_opcode;
18413 size = 4;
18414 break;
18415 case NOP_OPCODE_MIPS16:
c67a084a
NC
18416 opcode = mips16_nop_insn.insn_opcode;
18417 size = 2;
df58fc94
RS
18418 break;
18419 case NOP_OPCODE_MIPS:
18420 default:
c67a084a
NC
18421 opcode = nop_insn.insn_opcode;
18422 size = 4;
df58fc94 18423 break;
c67a084a 18424 }
a19d8eb0 18425
c67a084a
NC
18426 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18427 excess = bytes % size;
df58fc94
RS
18428
18429 /* Handle the leading part if we're not inserting a whole number of
18430 instructions, and make it the end of the fixed part of the frag.
18431 Try to fit in a short microMIPS NOP if applicable and possible,
18432 and use zeroes otherwise. */
18433 gas_assert (excess < 4);
18434 fragp->fr_fix += excess;
18435 switch (excess)
c67a084a 18436 {
df58fc94
RS
18437 case 3:
18438 *p++ = '\0';
18439 /* Fall through. */
18440 case 2:
18441 if (nop_opcode == NOP_OPCODE_MICROMIPS)
18442 {
18443 md_number_to_chars (p, micromips_nop16_insn.insn_opcode, 2);
18444 p += 2;
18445 break;
18446 }
18447 *p++ = '\0';
18448 /* Fall through. */
18449 case 1:
18450 *p++ = '\0';
18451 /* Fall through. */
18452 case 0:
18453 break;
a19d8eb0 18454 }
c67a084a
NC
18455
18456 md_number_to_chars (p, opcode, size);
18457 fragp->fr_var = size;
a19d8eb0
CP
18458}
18459
252b5132 18460static void
17a2f251 18461md_obj_begin (void)
252b5132
RH
18462{
18463}
18464
18465static void
17a2f251 18466md_obj_end (void)
252b5132 18467{
54f4ddb3 18468 /* Check for premature end, nesting errors, etc. */
252b5132 18469 if (cur_proc_ptr)
9a41af64 18470 as_warn (_("missing .end at end of assembly"));
252b5132
RH
18471}
18472
18473static long
17a2f251 18474get_number (void)
252b5132
RH
18475{
18476 int negative = 0;
18477 long val = 0;
18478
18479 if (*input_line_pointer == '-')
18480 {
18481 ++input_line_pointer;
18482 negative = 1;
18483 }
3882b010 18484 if (!ISDIGIT (*input_line_pointer))
956cd1d6 18485 as_bad (_("expected simple number"));
252b5132
RH
18486 if (input_line_pointer[0] == '0')
18487 {
18488 if (input_line_pointer[1] == 'x')
18489 {
18490 input_line_pointer += 2;
3882b010 18491 while (ISXDIGIT (*input_line_pointer))
252b5132
RH
18492 {
18493 val <<= 4;
18494 val |= hex_value (*input_line_pointer++);
18495 }
18496 return negative ? -val : val;
18497 }
18498 else
18499 {
18500 ++input_line_pointer;
3882b010 18501 while (ISDIGIT (*input_line_pointer))
252b5132
RH
18502 {
18503 val <<= 3;
18504 val |= *input_line_pointer++ - '0';
18505 }
18506 return negative ? -val : val;
18507 }
18508 }
3882b010 18509 if (!ISDIGIT (*input_line_pointer))
252b5132
RH
18510 {
18511 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18512 *input_line_pointer, *input_line_pointer);
956cd1d6 18513 as_warn (_("invalid number"));
252b5132
RH
18514 return -1;
18515 }
3882b010 18516 while (ISDIGIT (*input_line_pointer))
252b5132
RH
18517 {
18518 val *= 10;
18519 val += *input_line_pointer++ - '0';
18520 }
18521 return negative ? -val : val;
18522}
18523
18524/* The .file directive; just like the usual .file directive, but there
c5dd6aab
DJ
18525 is an initial number which is the ECOFF file index. In the non-ECOFF
18526 case .file implies DWARF-2. */
18527
18528static void
17a2f251 18529s_mips_file (int x ATTRIBUTE_UNUSED)
c5dd6aab 18530{
ecb4347a
DJ
18531 static int first_file_directive = 0;
18532
c5dd6aab
DJ
18533 if (ECOFF_DEBUGGING)
18534 {
18535 get_number ();
18536 s_app_file (0);
18537 }
18538 else
ecb4347a
DJ
18539 {
18540 char *filename;
18541
18542 filename = dwarf2_directive_file (0);
18543
18544 /* Versions of GCC up to 3.1 start files with a ".file"
18545 directive even for stabs output. Make sure that this
18546 ".file" is handled. Note that you need a version of GCC
18547 after 3.1 in order to support DWARF-2 on MIPS. */
18548 if (filename != NULL && ! first_file_directive)
18549 {
18550 (void) new_logical_line (filename, -1);
c04f5787 18551 s_app_file_string (filename, 0);
ecb4347a
DJ
18552 }
18553 first_file_directive = 1;
18554 }
c5dd6aab
DJ
18555}
18556
18557/* The .loc directive, implying DWARF-2. */
252b5132
RH
18558
18559static void
17a2f251 18560s_mips_loc (int x ATTRIBUTE_UNUSED)
252b5132 18561{
c5dd6aab
DJ
18562 if (!ECOFF_DEBUGGING)
18563 dwarf2_directive_loc (0);
252b5132
RH
18564}
18565
252b5132
RH
18566/* The .end directive. */
18567
18568static void
17a2f251 18569s_mips_end (int x ATTRIBUTE_UNUSED)
252b5132
RH
18570{
18571 symbolS *p;
252b5132 18572
7a621144
DJ
18573 /* Following functions need their own .frame and .cprestore directives. */
18574 mips_frame_reg_valid = 0;
18575 mips_cprestore_valid = 0;
18576
252b5132
RH
18577 if (!is_end_of_line[(unsigned char) *input_line_pointer])
18578 {
18579 p = get_symbol ();
18580 demand_empty_rest_of_line ();
18581 }
18582 else
18583 p = NULL;
18584
14949570 18585 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
252b5132
RH
18586 as_warn (_(".end not in text section"));
18587
18588 if (!cur_proc_ptr)
18589 {
18590 as_warn (_(".end directive without a preceding .ent directive."));
18591 demand_empty_rest_of_line ();
18592 return;
18593 }
18594
18595 if (p != NULL)
18596 {
9c2799c2 18597 gas_assert (S_GET_NAME (p));
9b2f1d35 18598 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
252b5132 18599 as_warn (_(".end symbol does not match .ent symbol."));
ecb4347a
DJ
18600
18601 if (debug_type == DEBUG_STABS)
18602 stabs_generate_asm_endfunc (S_GET_NAME (p),
18603 S_GET_NAME (p));
252b5132
RH
18604 }
18605 else
18606 as_warn (_(".end directive missing or unknown symbol"));
18607
2132e3a3 18608#ifdef OBJ_ELF
9b2f1d35
EC
18609 /* Create an expression to calculate the size of the function. */
18610 if (p && cur_proc_ptr)
18611 {
18612 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
18613 expressionS *exp = xmalloc (sizeof (expressionS));
18614
18615 obj->size = exp;
18616 exp->X_op = O_subtract;
18617 exp->X_add_symbol = symbol_temp_new_now ();
18618 exp->X_op_symbol = p;
18619 exp->X_add_number = 0;
18620
18621 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
18622 }
18623
ecb4347a 18624 /* Generate a .pdr section. */
f43abd2b 18625 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
ecb4347a
DJ
18626 {
18627 segT saved_seg = now_seg;
18628 subsegT saved_subseg = now_subseg;
ecb4347a
DJ
18629 expressionS exp;
18630 char *fragp;
252b5132 18631
252b5132 18632#ifdef md_flush_pending_output
ecb4347a 18633 md_flush_pending_output ();
252b5132
RH
18634#endif
18635
9c2799c2 18636 gas_assert (pdr_seg);
ecb4347a 18637 subseg_set (pdr_seg, 0);
252b5132 18638
ecb4347a
DJ
18639 /* Write the symbol. */
18640 exp.X_op = O_symbol;
18641 exp.X_add_symbol = p;
18642 exp.X_add_number = 0;
18643 emit_expr (&exp, 4);
252b5132 18644
ecb4347a 18645 fragp = frag_more (7 * 4);
252b5132 18646
17a2f251
TS
18647 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
18648 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
18649 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
18650 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
18651 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
18652 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
18653 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
252b5132 18654
ecb4347a
DJ
18655 subseg_set (saved_seg, saved_subseg);
18656 }
18657#endif /* OBJ_ELF */
252b5132
RH
18658
18659 cur_proc_ptr = NULL;
18660}
18661
18662/* The .aent and .ent directives. */
18663
18664static void
17a2f251 18665s_mips_ent (int aent)
252b5132 18666{
252b5132 18667 symbolS *symbolP;
252b5132
RH
18668
18669 symbolP = get_symbol ();
18670 if (*input_line_pointer == ',')
f9419b05 18671 ++input_line_pointer;
252b5132 18672 SKIP_WHITESPACE ();
3882b010 18673 if (ISDIGIT (*input_line_pointer)
d9a62219 18674 || *input_line_pointer == '-')
874e8986 18675 get_number ();
252b5132 18676
14949570 18677 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
252b5132
RH
18678 as_warn (_(".ent or .aent not in text section."));
18679
18680 if (!aent && cur_proc_ptr)
9a41af64 18681 as_warn (_("missing .end"));
252b5132
RH
18682
18683 if (!aent)
18684 {
7a621144
DJ
18685 /* This function needs its own .frame and .cprestore directives. */
18686 mips_frame_reg_valid = 0;
18687 mips_cprestore_valid = 0;
18688
252b5132
RH
18689 cur_proc_ptr = &cur_proc;
18690 memset (cur_proc_ptr, '\0', sizeof (procS));
18691
9b2f1d35 18692 cur_proc_ptr->func_sym = symbolP;
252b5132 18693
f9419b05 18694 ++numprocs;
ecb4347a
DJ
18695
18696 if (debug_type == DEBUG_STABS)
18697 stabs_generate_asm_func (S_GET_NAME (symbolP),
18698 S_GET_NAME (symbolP));
252b5132
RH
18699 }
18700
7c0fc524
MR
18701 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
18702
252b5132
RH
18703 demand_empty_rest_of_line ();
18704}
18705
18706/* The .frame directive. If the mdebug section is present (IRIX 5 native)
bdaaa2e1 18707 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
252b5132 18708 s_mips_frame is used so that we can set the PDR information correctly.
bdaaa2e1 18709 We can't use the ecoff routines because they make reference to the ecoff
252b5132
RH
18710 symbol table (in the mdebug section). */
18711
18712static void
17a2f251 18713s_mips_frame (int ignore ATTRIBUTE_UNUSED)
252b5132 18714{
ecb4347a 18715#ifdef OBJ_ELF
f43abd2b 18716 if (IS_ELF && !ECOFF_DEBUGGING)
ecb4347a
DJ
18717 {
18718 long val;
252b5132 18719
ecb4347a
DJ
18720 if (cur_proc_ptr == (procS *) NULL)
18721 {
18722 as_warn (_(".frame outside of .ent"));
18723 demand_empty_rest_of_line ();
18724 return;
18725 }
252b5132 18726
ecb4347a
DJ
18727 cur_proc_ptr->frame_reg = tc_get_register (1);
18728
18729 SKIP_WHITESPACE ();
18730 if (*input_line_pointer++ != ','
18731 || get_absolute_expression_and_terminator (&val) != ',')
18732 {
18733 as_warn (_("Bad .frame directive"));
18734 --input_line_pointer;
18735 demand_empty_rest_of_line ();
18736 return;
18737 }
252b5132 18738
ecb4347a
DJ
18739 cur_proc_ptr->frame_offset = val;
18740 cur_proc_ptr->pc_reg = tc_get_register (0);
252b5132 18741
252b5132 18742 demand_empty_rest_of_line ();
252b5132 18743 }
ecb4347a
DJ
18744 else
18745#endif /* OBJ_ELF */
18746 s_ignore (ignore);
252b5132
RH
18747}
18748
bdaaa2e1
KH
18749/* The .fmask and .mask directives. If the mdebug section is present
18750 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
252b5132 18751 embedded targets, s_mips_mask is used so that we can set the PDR
bdaaa2e1 18752 information correctly. We can't use the ecoff routines because they
252b5132
RH
18753 make reference to the ecoff symbol table (in the mdebug section). */
18754
18755static void
17a2f251 18756s_mips_mask (int reg_type)
252b5132 18757{
ecb4347a 18758#ifdef OBJ_ELF
f43abd2b 18759 if (IS_ELF && !ECOFF_DEBUGGING)
252b5132 18760 {
ecb4347a 18761 long mask, off;
252b5132 18762
ecb4347a
DJ
18763 if (cur_proc_ptr == (procS *) NULL)
18764 {
18765 as_warn (_(".mask/.fmask outside of .ent"));
18766 demand_empty_rest_of_line ();
18767 return;
18768 }
252b5132 18769
ecb4347a
DJ
18770 if (get_absolute_expression_and_terminator (&mask) != ',')
18771 {
18772 as_warn (_("Bad .mask/.fmask directive"));
18773 --input_line_pointer;
18774 demand_empty_rest_of_line ();
18775 return;
18776 }
252b5132 18777
ecb4347a
DJ
18778 off = get_absolute_expression ();
18779
18780 if (reg_type == 'F')
18781 {
18782 cur_proc_ptr->fpreg_mask = mask;
18783 cur_proc_ptr->fpreg_offset = off;
18784 }
18785 else
18786 {
18787 cur_proc_ptr->reg_mask = mask;
18788 cur_proc_ptr->reg_offset = off;
18789 }
18790
18791 demand_empty_rest_of_line ();
252b5132
RH
18792 }
18793 else
ecb4347a
DJ
18794#endif /* OBJ_ELF */
18795 s_ignore (reg_type);
252b5132
RH
18796}
18797
316f5878
RS
18798/* A table describing all the processors gas knows about. Names are
18799 matched in the order listed.
e7af610e 18800
316f5878
RS
18801 To ease comparison, please keep this table in the same order as
18802 gcc's mips_cpu_info_table[]. */
e972090a
NC
18803static const struct mips_cpu_info mips_cpu_info_table[] =
18804{
316f5878 18805 /* Entries for generic ISAs */
ad3fea08
TS
18806 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
18807 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
18808 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
18809 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
18810 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
18811 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
18812 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
18813 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
18814 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
316f5878
RS
18815
18816 /* MIPS I */
ad3fea08
TS
18817 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
18818 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
18819 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
316f5878
RS
18820
18821 /* MIPS II */
ad3fea08 18822 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
316f5878
RS
18823
18824 /* MIPS III */
ad3fea08
TS
18825 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
18826 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
18827 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
18828 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
18829 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
18830 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
18831 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
18832 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
18833 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
18834 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
18835 { "orion", 0, ISA_MIPS3, CPU_R4600 },
18836 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
b15591bb
AN
18837 /* ST Microelectronics Loongson 2E and 2F cores */
18838 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
18839 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
316f5878
RS
18840
18841 /* MIPS IV */
ad3fea08
TS
18842 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
18843 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
18844 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
3aa3176b
TS
18845 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
18846 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
ad3fea08
TS
18847 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
18848 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
18849 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
18850 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
18851 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
18852 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
18853 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
18854 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
18855 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
18856 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
316f5878
RS
18857
18858 /* MIPS 32 */
ad3fea08
TS
18859 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
18860 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
18861 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
18862 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
18863
18864 /* MIPS 32 Release 2 */
18865 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18866 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18867 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18868 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
18869 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18870 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
ad3fea08 18871 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951 18872 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
ad3fea08 18873 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951
RS
18874 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18875 /* Deprecated forms of the above. */
18876 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
ad3fea08 18877 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
01fd108f 18878 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
ad3fea08 18879 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951 18880 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
ad3fea08 18881 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951
RS
18882 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18883 /* Deprecated forms of the above. */
18884 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
65263ce3 18885 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
01fd108f 18886 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
a360e743
TS
18887 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18888 ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951
RS
18889 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18890 ISA_MIPS32R2, CPU_MIPS32R2 },
a360e743
TS
18891 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18892 ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951
RS
18893 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18894 ISA_MIPS32R2, CPU_MIPS32R2 },
18895 /* Deprecated forms of the above. */
18896 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18897 ISA_MIPS32R2, CPU_MIPS32R2 },
a360e743
TS
18898 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18899 ISA_MIPS32R2, CPU_MIPS32R2 },
01fd108f
TS
18900 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
18901 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18902 ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951
RS
18903 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18904 ISA_MIPS32R2, CPU_MIPS32R2 },
01fd108f
TS
18905 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18906 ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951
RS
18907 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18908 ISA_MIPS32R2, CPU_MIPS32R2 },
18909 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18910 ISA_MIPS32R2, CPU_MIPS32R2 },
18911 /* Deprecated forms of the above. */
18912 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18913 ISA_MIPS32R2, CPU_MIPS32R2 },
01fd108f
TS
18914 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18915 ISA_MIPS32R2, CPU_MIPS32R2 },
30f8113a
SL
18916 /* 1004K cores are multiprocessor versions of the 34K. */
18917 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18918 ISA_MIPS32R2, CPU_MIPS32R2 },
18919 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18920 ISA_MIPS32R2, CPU_MIPS32R2 },
18921 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18922 ISA_MIPS32R2, CPU_MIPS32R2 },
18923 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18924 ISA_MIPS32R2, CPU_MIPS32R2 },
32b26a03 18925
316f5878 18926 /* MIPS 64 */
ad3fea08
TS
18927 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
18928 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
18929 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
7764b395 18930 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
ad3fea08 18931
c7a23324 18932 /* Broadcom SB-1 CPU core */
65263ce3
TS
18933 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
18934 ISA_MIPS64, CPU_SB1 },
1e85aad8
JW
18935 /* Broadcom SB-1A CPU core */
18936 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
18937 ISA_MIPS64, CPU_SB1 },
d051516a
NC
18938
18939 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
e7af610e 18940
ed163775
MR
18941 /* MIPS 64 Release 2 */
18942
967344c6
AN
18943 /* Cavium Networks Octeon CPU core */
18944 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
18945
52b6b6b9
JM
18946 /* RMI Xlr */
18947 { "xlr", 0, ISA_MIPS64, CPU_XLR },
18948
316f5878
RS
18949 /* End marker */
18950 { NULL, 0, 0, 0 }
18951};
e7af610e 18952
84ea6cf2 18953
316f5878
RS
18954/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
18955 with a final "000" replaced by "k". Ignore case.
e7af610e 18956
316f5878 18957 Note: this function is shared between GCC and GAS. */
c6c98b38 18958
b34976b6 18959static bfd_boolean
17a2f251 18960mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
316f5878
RS
18961{
18962 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
18963 given++, canonical++;
18964
18965 return ((*given == 0 && *canonical == 0)
18966 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
18967}
18968
18969
18970/* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
18971 CPU name. We've traditionally allowed a lot of variation here.
18972
18973 Note: this function is shared between GCC and GAS. */
18974
b34976b6 18975static bfd_boolean
17a2f251 18976mips_matching_cpu_name_p (const char *canonical, const char *given)
316f5878
RS
18977{
18978 /* First see if the name matches exactly, or with a final "000"
18979 turned into "k". */
18980 if (mips_strict_matching_cpu_name_p (canonical, given))
b34976b6 18981 return TRUE;
316f5878
RS
18982
18983 /* If not, try comparing based on numerical designation alone.
18984 See if GIVEN is an unadorned number, or 'r' followed by a number. */
18985 if (TOLOWER (*given) == 'r')
18986 given++;
18987 if (!ISDIGIT (*given))
b34976b6 18988 return FALSE;
316f5878
RS
18989
18990 /* Skip over some well-known prefixes in the canonical name,
18991 hoping to find a number there too. */
18992 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
18993 canonical += 2;
18994 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
18995 canonical += 2;
18996 else if (TOLOWER (canonical[0]) == 'r')
18997 canonical += 1;
18998
18999 return mips_strict_matching_cpu_name_p (canonical, given);
19000}
19001
19002
19003/* Parse an option that takes the name of a processor as its argument.
19004 OPTION is the name of the option and CPU_STRING is the argument.
19005 Return the corresponding processor enumeration if the CPU_STRING is
19006 recognized, otherwise report an error and return null.
19007
19008 A similar function exists in GCC. */
e7af610e
NC
19009
19010static const struct mips_cpu_info *
17a2f251 19011mips_parse_cpu (const char *option, const char *cpu_string)
e7af610e 19012{
316f5878 19013 const struct mips_cpu_info *p;
e7af610e 19014
316f5878
RS
19015 /* 'from-abi' selects the most compatible architecture for the given
19016 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19017 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19018 version. Look first at the -mgp options, if given, otherwise base
19019 the choice on MIPS_DEFAULT_64BIT.
e7af610e 19020
316f5878
RS
19021 Treat NO_ABI like the EABIs. One reason to do this is that the
19022 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19023 architecture. This code picks MIPS I for 'mips' and MIPS III for
19024 'mips64', just as we did in the days before 'from-abi'. */
19025 if (strcasecmp (cpu_string, "from-abi") == 0)
19026 {
19027 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19028 return mips_cpu_info_from_isa (ISA_MIPS1);
19029
19030 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19031 return mips_cpu_info_from_isa (ISA_MIPS3);
19032
19033 if (file_mips_gp32 >= 0)
19034 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
19035
19036 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19037 ? ISA_MIPS3
19038 : ISA_MIPS1);
19039 }
19040
19041 /* 'default' has traditionally been a no-op. Probably not very useful. */
19042 if (strcasecmp (cpu_string, "default") == 0)
19043 return 0;
19044
19045 for (p = mips_cpu_info_table; p->name != 0; p++)
19046 if (mips_matching_cpu_name_p (p->name, cpu_string))
19047 return p;
19048
20203fb9 19049 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
316f5878 19050 return 0;
e7af610e
NC
19051}
19052
316f5878
RS
19053/* Return the canonical processor information for ISA (a member of the
19054 ISA_MIPS* enumeration). */
19055
e7af610e 19056static const struct mips_cpu_info *
17a2f251 19057mips_cpu_info_from_isa (int isa)
e7af610e
NC
19058{
19059 int i;
19060
19061 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
ad3fea08 19062 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
316f5878 19063 && isa == mips_cpu_info_table[i].isa)
e7af610e
NC
19064 return (&mips_cpu_info_table[i]);
19065
e972090a 19066 return NULL;
e7af610e 19067}
fef14a42
TS
19068
19069static const struct mips_cpu_info *
17a2f251 19070mips_cpu_info_from_arch (int arch)
fef14a42
TS
19071{
19072 int i;
19073
19074 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19075 if (arch == mips_cpu_info_table[i].cpu)
19076 return (&mips_cpu_info_table[i]);
19077
19078 return NULL;
19079}
316f5878
RS
19080\f
19081static void
17a2f251 19082show (FILE *stream, const char *string, int *col_p, int *first_p)
316f5878
RS
19083{
19084 if (*first_p)
19085 {
19086 fprintf (stream, "%24s", "");
19087 *col_p = 24;
19088 }
19089 else
19090 {
19091 fprintf (stream, ", ");
19092 *col_p += 2;
19093 }
e7af610e 19094
316f5878
RS
19095 if (*col_p + strlen (string) > 72)
19096 {
19097 fprintf (stream, "\n%24s", "");
19098 *col_p = 24;
19099 }
19100
19101 fprintf (stream, "%s", string);
19102 *col_p += strlen (string);
19103
19104 *first_p = 0;
19105}
19106
19107void
17a2f251 19108md_show_usage (FILE *stream)
e7af610e 19109{
316f5878
RS
19110 int column, first;
19111 size_t i;
19112
19113 fprintf (stream, _("\
19114MIPS options:\n\
316f5878
RS
19115-EB generate big endian output\n\
19116-EL generate little endian output\n\
19117-g, -g2 do not remove unneeded NOPs or swap branches\n\
19118-G NUM allow referencing objects up to NUM bytes\n\
19119 implicitly with the gp register [default 8]\n"));
19120 fprintf (stream, _("\
19121-mips1 generate MIPS ISA I instructions\n\
19122-mips2 generate MIPS ISA II instructions\n\
19123-mips3 generate MIPS ISA III instructions\n\
19124-mips4 generate MIPS ISA IV instructions\n\
19125-mips5 generate MIPS ISA V instructions\n\
19126-mips32 generate MIPS32 ISA instructions\n\
af7ee8bf 19127-mips32r2 generate MIPS32 release 2 ISA instructions\n\
316f5878 19128-mips64 generate MIPS64 ISA instructions\n\
5f74bc13 19129-mips64r2 generate MIPS64 release 2 ISA instructions\n\
316f5878
RS
19130-march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19131
19132 first = 1;
e7af610e
NC
19133
19134 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
316f5878
RS
19135 show (stream, mips_cpu_info_table[i].name, &column, &first);
19136 show (stream, "from-abi", &column, &first);
19137 fputc ('\n', stream);
e7af610e 19138
316f5878
RS
19139 fprintf (stream, _("\
19140-mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19141-no-mCPU don't generate code specific to CPU.\n\
19142 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19143
19144 first = 1;
19145
19146 show (stream, "3900", &column, &first);
19147 show (stream, "4010", &column, &first);
19148 show (stream, "4100", &column, &first);
19149 show (stream, "4650", &column, &first);
19150 fputc ('\n', stream);
19151
19152 fprintf (stream, _("\
19153-mips16 generate mips16 instructions\n\
19154-no-mips16 do not generate mips16 instructions\n"));
19155 fprintf (stream, _("\
df58fc94
RS
19156-mmicromips generate microMIPS instructions\n\
19157-mno-micromips do not generate microMIPS instructions\n"));
19158 fprintf (stream, _("\
e16bfa71
TS
19159-msmartmips generate smartmips instructions\n\
19160-mno-smartmips do not generate smartmips instructions\n"));
19161 fprintf (stream, _("\
74cd071d
CF
19162-mdsp generate DSP instructions\n\
19163-mno-dsp do not generate DSP instructions\n"));
19164 fprintf (stream, _("\
8b082fb1
TS
19165-mdspr2 generate DSP R2 instructions\n\
19166-mno-dspr2 do not generate DSP R2 instructions\n"));
19167 fprintf (stream, _("\
ef2e4d86
CF
19168-mmt generate MT instructions\n\
19169-mno-mt do not generate MT instructions\n"));
19170 fprintf (stream, _("\
c67a084a
NC
19171-mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19172-mfix-loongson2f-nop work around Loongson2F NOP errata\n\
d766e8ec 19173-mfix-vr4120 work around certain VR4120 errata\n\
7d8e00cf 19174-mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
6a32d874 19175-mfix-24k insert a nop after ERET and DERET instructions\n\
d954098f 19176-mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
316f5878
RS
19177-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19178-mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
aed1a261 19179-msym32 assume all symbols have 32-bit values\n\
316f5878
RS
19180-O0 remove unneeded NOPs, do not swap branches\n\
19181-O remove unneeded NOPs and swap branches\n\
316f5878
RS
19182--trap, --no-break trap exception on div by 0 and mult overflow\n\
19183--break, --no-trap break exception on div by 0 and mult overflow\n"));
037b32b9
AN
19184 fprintf (stream, _("\
19185-mhard-float allow floating-point instructions\n\
19186-msoft-float do not allow floating-point instructions\n\
19187-msingle-float only allow 32-bit floating-point operations\n\
19188-mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19189--[no-]construct-floats [dis]allow floating point values to be constructed\n"
19190 ));
316f5878
RS
19191#ifdef OBJ_ELF
19192 fprintf (stream, _("\
19193-KPIC, -call_shared generate SVR4 position independent code\n\
861fb55a 19194-call_nonpic generate non-PIC code that can operate with DSOs\n\
0c000745 19195-mvxworks-pic generate VxWorks position independent code\n\
861fb55a 19196-non_shared do not generate code that can operate with DSOs\n\
316f5878 19197-xgot assume a 32 bit GOT\n\
dcd410fe 19198-mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
bbe506e8 19199-mshared, -mno-shared disable/enable .cpload optimization for\n\
d821e36b 19200 position dependent (non shared) code\n\
316f5878
RS
19201-mabi=ABI create ABI conformant object file for:\n"));
19202
19203 first = 1;
19204
19205 show (stream, "32", &column, &first);
19206 show (stream, "o64", &column, &first);
19207 show (stream, "n32", &column, &first);
19208 show (stream, "64", &column, &first);
19209 show (stream, "eabi", &column, &first);
19210
19211 fputc ('\n', stream);
19212
19213 fprintf (stream, _("\
19214-32 create o32 ABI object file (default)\n\
19215-n32 create n32 ABI object file\n\
19216-64 create 64 ABI object file\n"));
19217#endif
e7af610e 19218}
14e777e0 19219
1575952e 19220#ifdef TE_IRIX
14e777e0 19221enum dwarf2_format
413a266c 19222mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
14e777e0 19223{
369943fe 19224 if (HAVE_64BIT_SYMBOLS)
1575952e 19225 return dwarf2_format_64bit_irix;
14e777e0
KB
19226 else
19227 return dwarf2_format_32bit;
19228}
1575952e 19229#endif
73369e65
EC
19230
19231int
19232mips_dwarf2_addr_size (void)
19233{
6b6b3450 19234 if (HAVE_64BIT_OBJECTS)
73369e65 19235 return 8;
73369e65
EC
19236 else
19237 return 4;
19238}
5862107c
EC
19239
19240/* Standard calling conventions leave the CFA at SP on entry. */
19241void
19242mips_cfi_frame_initial_instructions (void)
19243{
19244 cfi_add_CFA_def_cfa_register (SP);
19245}
19246
707bfff6
TS
19247int
19248tc_mips_regname_to_dw2regnum (char *regname)
19249{
19250 unsigned int regnum = -1;
19251 unsigned int reg;
19252
19253 if (reg_lookup (&regname, RTYPE_GP | RTYPE_NUM, &reg))
19254 regnum = reg;
19255
19256 return regnum;
19257}
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