Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
c67a084a NC |
3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
4 | Free Software Foundation, Inc. | |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
741fe287 | 93 | #define ATREG 1 |
df58fc94 RS |
94 | #define S0 16 |
95 | #define S7 23 | |
252b5132 RH |
96 | #define TREG 24 |
97 | #define PIC_CALL_REG 25 | |
98 | #define KT0 26 | |
99 | #define KT1 27 | |
100 | #define GP 28 | |
101 | #define SP 29 | |
102 | #define FP 30 | |
103 | #define RA 31 | |
104 | ||
105 | #define ILLEGAL_REG (32) | |
106 | ||
741fe287 MR |
107 | #define AT mips_opts.at |
108 | ||
252b5132 RH |
109 | /* Allow override of standard little-endian ECOFF format. */ |
110 | ||
111 | #ifndef ECOFF_LITTLE_FORMAT | |
112 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
113 | #endif | |
114 | ||
115 | extern int target_big_endian; | |
116 | ||
252b5132 | 117 | /* The name of the readonly data section. */ |
4d0d148d | 118 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 119 | ? ".rdata" \ |
056350c6 NC |
120 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
121 | ? ".rdata" \ | |
252b5132 RH |
122 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
123 | ? ".rodata" \ | |
124 | : (abort (), "")) | |
125 | ||
a4e06468 RS |
126 | /* Ways in which an instruction can be "appended" to the output. */ |
127 | enum append_method { | |
128 | /* Just add it normally. */ | |
129 | APPEND_ADD, | |
130 | ||
131 | /* Add it normally and then add a nop. */ | |
132 | APPEND_ADD_WITH_NOP, | |
133 | ||
134 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
135 | APPEND_ADD_COMPACT, | |
136 | ||
137 | /* Insert the instruction before the last one. */ | |
138 | APPEND_SWAP | |
139 | }; | |
140 | ||
47e39b9d RS |
141 | /* Information about an instruction, including its format, operands |
142 | and fixups. */ | |
143 | struct mips_cl_insn | |
144 | { | |
145 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
146 | const struct mips_opcode *insn_mo; | |
147 | ||
148 | /* True if this is a mips16 instruction and if we want the extended | |
149 | form of INSN_MO. */ | |
150 | bfd_boolean use_extend; | |
151 | ||
152 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
153 | unsigned short extend; | |
154 | ||
155 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
156 | a copy of INSN_MO->match with the operands filled in. */ | |
157 | unsigned long insn_opcode; | |
158 | ||
159 | /* The frag that contains the instruction. */ | |
160 | struct frag *frag; | |
161 | ||
162 | /* The offset into FRAG of the first instruction byte. */ | |
163 | long where; | |
164 | ||
165 | /* The relocs associated with the instruction, if any. */ | |
166 | fixS *fixp[3]; | |
167 | ||
a38419a5 RS |
168 | /* True if this entry cannot be moved from its current position. */ |
169 | unsigned int fixed_p : 1; | |
47e39b9d | 170 | |
708587a4 | 171 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
172 | unsigned int noreorder_p : 1; |
173 | ||
2fa15973 RS |
174 | /* True for mips16 instructions that jump to an absolute address. */ |
175 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
176 | |
177 | /* True if this instruction is complete. */ | |
178 | unsigned int complete_p : 1; | |
47e39b9d RS |
179 | }; |
180 | ||
a325df1d TS |
181 | /* The ABI to use. */ |
182 | enum mips_abi_level | |
183 | { | |
184 | NO_ABI = 0, | |
185 | O32_ABI, | |
186 | O64_ABI, | |
187 | N32_ABI, | |
188 | N64_ABI, | |
189 | EABI_ABI | |
190 | }; | |
191 | ||
192 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 193 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 194 | |
143d77c5 EC |
195 | /* Whether or not we have code that can call pic code. */ |
196 | int mips_abicalls = FALSE; | |
197 | ||
aa6975fb ILT |
198 | /* Whether or not we have code which can be put into a shared |
199 | library. */ | |
200 | static bfd_boolean mips_in_shared = TRUE; | |
201 | ||
252b5132 RH |
202 | /* This is the set of options which may be modified by the .set |
203 | pseudo-op. We use a struct so that .set push and .set pop are more | |
204 | reliable. */ | |
205 | ||
e972090a NC |
206 | struct mips_set_options |
207 | { | |
252b5132 RH |
208 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
209 | if it has not been initialized. Changed by `.set mipsN', and the | |
210 | -mipsN command line option, and the default CPU. */ | |
211 | int isa; | |
1f25f5d3 CD |
212 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
213 | if they have not been initialized. Changed by `.set <asename>', by | |
214 | command line options, and based on the default architecture. */ | |
215 | int ase_mips3d; | |
deec1734 | 216 | int ase_mdmx; |
e16bfa71 | 217 | int ase_smartmips; |
74cd071d | 218 | int ase_dsp; |
8b082fb1 | 219 | int ase_dspr2; |
ef2e4d86 | 220 | int ase_mt; |
252b5132 RH |
221 | /* Whether we are assembling for the mips16 processor. 0 if we are |
222 | not, 1 if we are, and -1 if the value has not been initialized. | |
223 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
224 | -nomips16 command line options, and the default CPU. */ | |
225 | int mips16; | |
df58fc94 RS |
226 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
227 | 1 if we are, and -1 if the value has not been initialized. Changed | |
228 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
229 | and -mno-micromips command line options, and the default CPU. */ | |
230 | int micromips; | |
252b5132 RH |
231 | /* Non-zero if we should not reorder instructions. Changed by `.set |
232 | reorder' and `.set noreorder'. */ | |
233 | int noreorder; | |
741fe287 MR |
234 | /* Non-zero if we should not permit the register designated "assembler |
235 | temporary" to be used in instructions. The value is the register | |
236 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
237 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
238 | unsigned int at; | |
252b5132 RH |
239 | /* Non-zero if we should warn when a macro instruction expands into |
240 | more than one machine instruction. Changed by `.set nomacro' and | |
241 | `.set macro'. */ | |
242 | int warn_about_macros; | |
243 | /* Non-zero if we should not move instructions. Changed by `.set | |
244 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
245 | int nomove; | |
246 | /* Non-zero if we should not optimize branches by moving the target | |
247 | of the branch into the delay slot. Actually, we don't perform | |
248 | this optimization anyhow. Changed by `.set bopt' and `.set | |
249 | nobopt'. */ | |
250 | int nobopt; | |
251 | /* Non-zero if we should not autoextend mips16 instructions. | |
252 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
253 | int noautoextend; | |
a325df1d TS |
254 | /* Restrict general purpose registers and floating point registers |
255 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
256 | is passed but can changed if the assembler code uses .set mipsN. */ | |
257 | int gp32; | |
258 | int fp32; | |
fef14a42 TS |
259 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
260 | command line option, and the default CPU. */ | |
261 | int arch; | |
aed1a261 RS |
262 | /* True if ".set sym32" is in effect. */ |
263 | bfd_boolean sym32; | |
037b32b9 AN |
264 | /* True if floating-point operations are not allowed. Changed by .set |
265 | softfloat or .set hardfloat, by command line options -msoft-float or | |
266 | -mhard-float. The default is false. */ | |
267 | bfd_boolean soft_float; | |
268 | ||
269 | /* True if only single-precision floating-point operations are allowed. | |
270 | Changed by .set singlefloat or .set doublefloat, command-line options | |
271 | -msingle-float or -mdouble-float. The default is false. */ | |
272 | bfd_boolean single_float; | |
252b5132 RH |
273 | }; |
274 | ||
037b32b9 AN |
275 | /* This is the struct we use to hold the current set of options. Note |
276 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
277 | -1 to indicate that they have not been initialized. */ | |
278 | ||
a325df1d | 279 | /* True if -mgp32 was passed. */ |
a8e8e863 | 280 | static int file_mips_gp32 = -1; |
a325df1d TS |
281 | |
282 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 283 | static int file_mips_fp32 = -1; |
a325df1d | 284 | |
037b32b9 AN |
285 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
286 | static int file_mips_soft_float = 0; | |
287 | ||
288 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
289 | static int file_mips_single_float = 0; | |
252b5132 | 290 | |
e972090a NC |
291 | static struct mips_set_options mips_opts = |
292 | { | |
037b32b9 AN |
293 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
294 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
df58fc94 | 295 | /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0, /* at */ ATREG, |
037b32b9 AN |
296 | /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, |
297 | /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, | |
298 | /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 299 | }; |
252b5132 RH |
300 | |
301 | /* These variables are filled in with the masks of registers used. | |
302 | The object format code reads them and puts them in the appropriate | |
303 | place. */ | |
304 | unsigned long mips_gprmask; | |
305 | unsigned long mips_cprmask[4]; | |
306 | ||
307 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 308 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 309 | |
738f4d98 | 310 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
311 | static int file_ase_mips16; |
312 | ||
3994f87e TS |
313 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
314 | || mips_opts.isa == ISA_MIPS32R2 \ | |
315 | || mips_opts.isa == ISA_MIPS64 \ | |
316 | || mips_opts.isa == ISA_MIPS64R2) | |
317 | ||
df58fc94 RS |
318 | /* True if any microMIPS code was produced. */ |
319 | static int file_ase_micromips; | |
320 | ||
b12dd2e4 CF |
321 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
322 | #ifdef TE_IRIX | |
1180b5a4 | 323 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 324 | #else |
1180b5a4 RS |
325 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
326 | because there's no place for any addend, the only acceptable | |
327 | expression is a bare symbol. */ | |
328 | #define MIPS_JALR_HINT_P(EXPR) \ | |
329 | (!HAVE_IN_PLACE_ADDENDS \ | |
330 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
331 | #endif |
332 | ||
1f25f5d3 CD |
333 | /* True if -mips3d was passed or implied by arguments passed on the |
334 | command line (e.g., by -march). */ | |
335 | static int file_ase_mips3d; | |
336 | ||
deec1734 CD |
337 | /* True if -mdmx was passed or implied by arguments passed on the |
338 | command line (e.g., by -march). */ | |
339 | static int file_ase_mdmx; | |
340 | ||
e16bfa71 TS |
341 | /* True if -msmartmips was passed or implied by arguments passed on the |
342 | command line (e.g., by -march). */ | |
343 | static int file_ase_smartmips; | |
344 | ||
ad3fea08 TS |
345 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
346 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 347 | |
74cd071d CF |
348 | /* True if -mdsp was passed or implied by arguments passed on the |
349 | command line (e.g., by -march). */ | |
350 | static int file_ase_dsp; | |
351 | ||
ad3fea08 TS |
352 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
353 | || mips_opts.isa == ISA_MIPS64R2) | |
354 | ||
65263ce3 TS |
355 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
356 | ||
8b082fb1 TS |
357 | /* True if -mdspr2 was passed or implied by arguments passed on the |
358 | command line (e.g., by -march). */ | |
359 | static int file_ase_dspr2; | |
360 | ||
361 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
362 | || mips_opts.isa == ISA_MIPS64R2) | |
363 | ||
ef2e4d86 CF |
364 | /* True if -mmt was passed or implied by arguments passed on the |
365 | command line (e.g., by -march). */ | |
366 | static int file_ase_mt; | |
367 | ||
ad3fea08 TS |
368 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
369 | || mips_opts.isa == ISA_MIPS64R2) | |
370 | ||
ec68c924 | 371 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 372 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 373 | static const char *mips_arch_string; |
ec68c924 EC |
374 | |
375 | /* The argument of the -mtune= flag. The architecture for which we | |
376 | are optimizing. */ | |
377 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 378 | static const char *mips_tune_string; |
ec68c924 | 379 | |
316f5878 | 380 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
381 | static int mips_32bitmode = 0; |
382 | ||
316f5878 RS |
383 | /* True if the given ABI requires 32-bit registers. */ |
384 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
385 | ||
386 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
387 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
388 | ((ABI) == N32_ABI \ | |
389 | || (ABI) == N64_ABI \ | |
316f5878 RS |
390 | || (ABI) == O64_ABI) |
391 | ||
ad3fea08 | 392 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
393 | #define ISA_HAS_64BIT_REGS(ISA) \ |
394 | ((ISA) == ISA_MIPS3 \ | |
395 | || (ISA) == ISA_MIPS4 \ | |
396 | || (ISA) == ISA_MIPS5 \ | |
397 | || (ISA) == ISA_MIPS64 \ | |
398 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 399 | |
ad3fea08 TS |
400 | /* Return true if ISA supports 64 bit wide float registers. */ |
401 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
402 | ((ISA) == ISA_MIPS3 \ | |
403 | || (ISA) == ISA_MIPS4 \ | |
404 | || (ISA) == ISA_MIPS5 \ | |
405 | || (ISA) == ISA_MIPS32R2 \ | |
406 | || (ISA) == ISA_MIPS64 \ | |
407 | || (ISA) == ISA_MIPS64R2) | |
408 | ||
af7ee8bf CD |
409 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
410 | instructions. */ | |
707bfff6 | 411 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 RS |
412 | ((ISA) == ISA_MIPS64R2 \ |
413 | || (mips_opts.micromips \ | |
414 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
415 | ) | |
af7ee8bf CD |
416 | |
417 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
418 | instructions. */ | |
707bfff6 TS |
419 | #define ISA_HAS_ROR(ISA) \ |
420 | ((ISA) == ISA_MIPS32R2 \ | |
421 | || (ISA) == ISA_MIPS64R2 \ | |
df58fc94 RS |
422 | || mips_opts.ase_smartmips \ |
423 | || mips_opts.micromips \ | |
424 | ) | |
707bfff6 | 425 | |
7455baf8 TS |
426 | /* Return true if ISA supports single-precision floats in odd registers. */ |
427 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
428 | ((ISA) == ISA_MIPS32 \ | |
429 | || (ISA) == ISA_MIPS32R2 \ | |
430 | || (ISA) == ISA_MIPS64 \ | |
431 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 432 | |
ad3fea08 TS |
433 | /* Return true if ISA supports move to/from high part of a 64-bit |
434 | floating-point register. */ | |
435 | #define ISA_HAS_MXHC1(ISA) \ | |
436 | ((ISA) == ISA_MIPS32R2 \ | |
437 | || (ISA) == ISA_MIPS64R2) | |
438 | ||
e013f690 | 439 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 440 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 441 | |
e013f690 | 442 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 443 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 444 | |
ad3fea08 TS |
445 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
446 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 447 | |
316f5878 | 448 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 449 | |
316f5878 | 450 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 451 | |
3b91255e RS |
452 | /* True if relocations are stored in-place. */ |
453 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
454 | ||
aed1a261 RS |
455 | /* The ABI-derived address size. */ |
456 | #define HAVE_64BIT_ADDRESSES \ | |
457 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
458 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 459 | |
aed1a261 RS |
460 | /* The size of symbolic constants (i.e., expressions of the form |
461 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
462 | #define HAVE_32BIT_SYMBOLS \ | |
463 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
464 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 465 | |
b7c7d6c1 TS |
466 | /* Addresses are loaded in different ways, depending on the address size |
467 | in use. The n32 ABI Documentation also mandates the use of additions | |
468 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 469 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 470 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
471 | |
472 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 473 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
474 | |
475 | #define ADDRESS_LOAD_INSN \ | |
476 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
477 | ||
478 | #define ADDRESS_STORE_INSN \ | |
479 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
480 | ||
a4672219 | 481 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
482 | #define CPU_HAS_MIPS16(cpu) \ |
483 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
484 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 485 | |
2309ddf2 | 486 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
487 | #define CPU_HAS_MICROMIPS(cpu) 0 |
488 | ||
60b63b72 RS |
489 | /* True if CPU has a dror instruction. */ |
490 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
491 | ||
492 | /* True if CPU has a ror instruction. */ | |
493 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
494 | ||
dd3cbb7e NC |
495 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
496 | #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON) | |
497 | ||
b19e8a9b AN |
498 | /* True if CPU does not implement the all the coprocessor insns. For these |
499 | CPUs only those COP insns are accepted that are explicitly marked to be | |
500 | available on the CPU. ISA membership for COP insns is ignored. */ | |
501 | #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON) | |
502 | ||
c8978940 CD |
503 | /* True if mflo and mfhi can be immediately followed by instructions |
504 | which write to the HI and LO registers. | |
505 | ||
506 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
507 | (at least) two instructions between the reads of HI/LO and | |
508 | instructions which write them, and later ISAs do not. Contradicting | |
509 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
510 | the UM for the NEC Vr5000) document needing the instructions between | |
511 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
512 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
513 | earlier-ISA CPUs for which CPU documentation declares that the | |
514 | instructions are really interlocked. */ | |
515 | #define hilo_interlocks \ | |
516 | (mips_opts.isa == ISA_MIPS32 \ | |
517 | || mips_opts.isa == ISA_MIPS32R2 \ | |
518 | || mips_opts.isa == ISA_MIPS64 \ | |
519 | || mips_opts.isa == ISA_MIPS64R2 \ | |
520 | || mips_opts.arch == CPU_R4010 \ | |
521 | || mips_opts.arch == CPU_R10000 \ | |
522 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
523 | || mips_opts.arch == CPU_R14000 \ |
524 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 525 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 526 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 527 | || mips_opts.micromips \ |
c8978940 | 528 | ) |
252b5132 RH |
529 | |
530 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
531 | from the GPRs after they are loaded from memory, and thus does not |
532 | require nops to be inserted. This applies to instructions marked | |
533 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
df58fc94 RS |
534 | level I and microMIPS mode instructions are always interlocked. */ |
535 | #define gpr_interlocks \ | |
536 | (mips_opts.isa != ISA_MIPS1 \ | |
537 | || mips_opts.arch == CPU_R3900 \ | |
538 | || mips_opts.micromips \ | |
539 | ) | |
252b5132 | 540 | |
81912461 ILT |
541 | /* Whether the processor uses hardware interlocks to avoid delays |
542 | required by coprocessor instructions, and thus does not require | |
543 | nops to be inserted. This applies to instructions marked | |
544 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
545 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
546 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
df58fc94 RS |
547 | levels I, II, and III and microMIPS mode instructions are always |
548 | interlocked. */ | |
bdaaa2e1 | 549 | /* Itbl support may require additional care here. */ |
81912461 ILT |
550 | #define cop_interlocks \ |
551 | ((mips_opts.isa != ISA_MIPS1 \ | |
552 | && mips_opts.isa != ISA_MIPS2 \ | |
553 | && mips_opts.isa != ISA_MIPS3) \ | |
554 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 555 | || mips_opts.micromips \ |
81912461 ILT |
556 | ) |
557 | ||
558 | /* Whether the processor uses hardware interlocks to protect reads | |
559 | from coprocessor registers after they are loaded from memory, and | |
560 | thus does not require nops to be inserted. This applies to | |
561 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
562 | requires at MIPS ISA level I and microMIPS mode instructions are |
563 | always interlocked. */ | |
564 | #define cop_mem_interlocks \ | |
565 | (mips_opts.isa != ISA_MIPS1 \ | |
566 | || mips_opts.micromips \ | |
567 | ) | |
252b5132 | 568 | |
6b76fefe CM |
569 | /* Is this a mfhi or mflo instruction? */ |
570 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
571 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
572 | ||
573 | /* Returns true for a (non floating-point) coprocessor instruction. Reading | |
574 | or writing the condition code is only possible on the coprocessors and | |
575 | these insns are not marked with INSN_COP. Thus for these insns use the | |
a242dc0d | 576 | condition-code flags. */ |
b19e8a9b AN |
577 | #define COP_INSN(PINFO) \ |
578 | (PINFO != INSN_MACRO \ | |
a242dc0d AN |
579 | && ((PINFO) & (FP_S | FP_D)) == 0 \ |
580 | && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE))) | |
6b76fefe | 581 | |
df58fc94 RS |
582 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
583 | has been selected. This implies, in particular, that addresses of text | |
584 | labels have their LSB set. */ | |
585 | #define HAVE_CODE_COMPRESSION \ | |
586 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
587 | ||
252b5132 RH |
588 | /* MIPS PIC level. */ |
589 | ||
a161fe53 | 590 | enum mips_pic_level mips_pic; |
252b5132 | 591 | |
c9914766 | 592 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 593 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 594 | static int mips_big_got = 0; |
252b5132 RH |
595 | |
596 | /* 1 if trap instructions should used for overflow rather than break | |
597 | instructions. */ | |
c9914766 | 598 | static int mips_trap = 0; |
252b5132 | 599 | |
119d663a | 600 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 601 | by assembling two single width halves into two single width floating |
119d663a NC |
602 | point registers which just happen to alias the double width destination |
603 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 604 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
605 | automatically at assemble time. */ |
606 | static int mips_disable_float_construction; | |
607 | ||
252b5132 RH |
608 | /* Non-zero if any .set noreorder directives were used. */ |
609 | ||
610 | static int mips_any_noreorder; | |
611 | ||
6b76fefe CM |
612 | /* Non-zero if nops should be inserted when the register referenced in |
613 | an mfhi/mflo instruction is read in the next two instructions. */ | |
614 | static int mips_7000_hilo_fix; | |
615 | ||
02ffd3e4 | 616 | /* The size of objects in the small data section. */ |
156c2f8b | 617 | static unsigned int g_switch_value = 8; |
252b5132 RH |
618 | /* Whether the -G option was used. */ |
619 | static int g_switch_seen = 0; | |
620 | ||
621 | #define N_RMASK 0xc4 | |
622 | #define N_VFP 0xd4 | |
623 | ||
624 | /* If we can determine in advance that GP optimization won't be | |
625 | possible, we can skip the relaxation stuff that tries to produce | |
626 | GP-relative references. This makes delay slot optimization work | |
627 | better. | |
628 | ||
629 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
630 | gcc output. It needs to guess right for gcc, otherwise gcc |
631 | will put what it thinks is a GP-relative instruction in a branch | |
632 | delay slot. | |
252b5132 RH |
633 | |
634 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
635 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 636 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
637 | |
638 | /* handle of the OPCODE hash table */ | |
639 | static struct hash_control *op_hash = NULL; | |
640 | ||
641 | /* The opcode hash table we use for the mips16. */ | |
642 | static struct hash_control *mips16_op_hash = NULL; | |
643 | ||
df58fc94 RS |
644 | /* The opcode hash table we use for the microMIPS ASE. */ |
645 | static struct hash_control *micromips_op_hash = NULL; | |
646 | ||
252b5132 RH |
647 | /* This array holds the chars that always start a comment. If the |
648 | pre-processor is disabled, these aren't very useful */ | |
649 | const char comment_chars[] = "#"; | |
650 | ||
651 | /* This array holds the chars that only start a comment at the beginning of | |
652 | a line. If the line seems to have the form '# 123 filename' | |
653 | .line and .file directives will appear in the pre-processed output */ | |
654 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
655 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 656 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
657 | /* Also note that C style comments are always supported. */ |
658 | const char line_comment_chars[] = "#"; | |
659 | ||
bdaaa2e1 | 660 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 661 | const char line_separator_chars[] = ";"; |
252b5132 RH |
662 | |
663 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
664 | const char EXP_CHARS[] = "eE"; | |
665 | ||
666 | /* Chars that mean this number is a floating point constant */ | |
667 | /* As in 0f12.456 */ | |
668 | /* or 0d1.2345e12 */ | |
669 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
670 | ||
671 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
672 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
673 | but nothing is ideal around here. | |
674 | */ | |
675 | ||
676 | static char *insn_error; | |
677 | ||
678 | static int auto_align = 1; | |
679 | ||
680 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
681 | offset in the stack frame from which to restore the $gp register. | |
682 | This is set by the .cprestore pseudo-op, and saved in this | |
683 | variable. */ | |
684 | static offsetT mips_cprestore_offset = -1; | |
685 | ||
67c1ffbe | 686 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 687 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 688 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
689 | static offsetT mips_cpreturn_offset = -1; |
690 | static int mips_cpreturn_register = -1; | |
691 | static int mips_gp_register = GP; | |
def2e0dd | 692 | static int mips_gprel_offset = 0; |
6478892d | 693 | |
7a621144 DJ |
694 | /* Whether mips_cprestore_offset has been set in the current function |
695 | (or whether it has already been warned about, if not). */ | |
696 | static int mips_cprestore_valid = 0; | |
697 | ||
252b5132 RH |
698 | /* This is the register which holds the stack frame, as set by the |
699 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
700 | static int mips_frame_reg = SP; | |
701 | ||
7a621144 DJ |
702 | /* Whether mips_frame_reg has been set in the current function |
703 | (or whether it has already been warned about, if not). */ | |
704 | static int mips_frame_reg_valid = 0; | |
705 | ||
252b5132 RH |
706 | /* To output NOP instructions correctly, we need to keep information |
707 | about the previous two instructions. */ | |
708 | ||
709 | /* Whether we are optimizing. The default value of 2 means to remove | |
710 | unneeded NOPs and swap branch instructions when possible. A value | |
711 | of 1 means to not swap branches. A value of 0 means to always | |
712 | insert NOPs. */ | |
713 | static int mips_optimize = 2; | |
714 | ||
715 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
716 | equivalent to seeing no -g option at all. */ | |
717 | static int mips_debug = 0; | |
718 | ||
7d8e00cf RS |
719 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
720 | #define MAX_VR4130_NOPS 4 | |
721 | ||
722 | /* The maximum number of NOPs needed to fill delay slots. */ | |
723 | #define MAX_DELAY_NOPS 2 | |
724 | ||
725 | /* The maximum number of NOPs needed for any purpose. */ | |
726 | #define MAX_NOPS 4 | |
71400594 RS |
727 | |
728 | /* A list of previous instructions, with index 0 being the most recent. | |
729 | We need to look back MAX_NOPS instructions when filling delay slots | |
730 | or working around processor errata. We need to look back one | |
731 | instruction further if we're thinking about using history[0] to | |
732 | fill a branch delay slot. */ | |
733 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 734 | |
1e915849 | 735 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
736 | static struct mips_cl_insn nop_insn; |
737 | static struct mips_cl_insn mips16_nop_insn; | |
738 | static struct mips_cl_insn micromips_nop16_insn; | |
739 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
740 | |
741 | /* The appropriate nop for the current mode. */ | |
df58fc94 RS |
742 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \ |
743 | : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn)) | |
744 | ||
745 | /* The size of NOP_INSN in bytes. */ | |
746 | #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4) | |
252b5132 | 747 | |
252b5132 RH |
748 | /* If this is set, it points to a frag holding nop instructions which |
749 | were inserted before the start of a noreorder section. If those | |
750 | nops turn out to be unnecessary, the size of the frag can be | |
751 | decreased. */ | |
752 | static fragS *prev_nop_frag; | |
753 | ||
754 | /* The number of nop instructions we created in prev_nop_frag. */ | |
755 | static int prev_nop_frag_holds; | |
756 | ||
757 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 758 | prev_nop_frag. */ |
252b5132 RH |
759 | static int prev_nop_frag_required; |
760 | ||
761 | /* The number of instructions we've seen since prev_nop_frag. */ | |
762 | static int prev_nop_frag_since; | |
763 | ||
764 | /* For ECOFF and ELF, relocations against symbols are done in two | |
765 | parts, with a HI relocation and a LO relocation. Each relocation | |
766 | has only 16 bits of space to store an addend. This means that in | |
767 | order for the linker to handle carries correctly, it must be able | |
768 | to locate both the HI and the LO relocation. This means that the | |
769 | relocations must appear in order in the relocation table. | |
770 | ||
771 | In order to implement this, we keep track of each unmatched HI | |
772 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 773 | corresponding LO relocation. */ |
252b5132 | 774 | |
e972090a NC |
775 | struct mips_hi_fixup |
776 | { | |
252b5132 RH |
777 | /* Next HI fixup. */ |
778 | struct mips_hi_fixup *next; | |
779 | /* This fixup. */ | |
780 | fixS *fixp; | |
781 | /* The section this fixup is in. */ | |
782 | segT seg; | |
783 | }; | |
784 | ||
785 | /* The list of unmatched HI relocs. */ | |
786 | ||
787 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
788 | ||
64bdfcaf RS |
789 | /* The frag containing the last explicit relocation operator. |
790 | Null if explicit relocations have not been used. */ | |
791 | ||
792 | static fragS *prev_reloc_op_frag; | |
793 | ||
252b5132 RH |
794 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
795 | ||
796 | #define X ILLEGAL_REG | |
e972090a NC |
797 | static const int mips32_to_16_reg_map[] = |
798 | { | |
252b5132 RH |
799 | X, X, 2, 3, 4, 5, 6, 7, |
800 | X, X, X, X, X, X, X, X, | |
801 | 0, 1, X, X, X, X, X, X, | |
802 | X, X, X, X, X, X, X, X | |
803 | }; | |
804 | #undef X | |
805 | ||
806 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
807 | ||
e972090a NC |
808 | static const unsigned int mips16_to_32_reg_map[] = |
809 | { | |
252b5132 RH |
810 | 16, 17, 2, 3, 4, 5, 6, 7 |
811 | }; | |
60b63b72 | 812 | |
df58fc94 RS |
813 | /* Map normal MIPS register numbers to microMIPS register numbers. */ |
814 | ||
815 | #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map | |
816 | #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map | |
817 | #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map | |
818 | #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map | |
819 | #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map | |
820 | #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map | |
821 | #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map | |
822 | ||
823 | #define X ILLEGAL_REG | |
824 | /* reg type h: 4, 5, 6. */ | |
825 | static const int mips32_to_micromips_reg_h_map[] = | |
826 | { | |
827 | X, X, X, X, 4, 5, 6, X, | |
828 | X, X, X, X, X, X, X, X, | |
829 | X, X, X, X, X, X, X, X, | |
830 | X, X, X, X, X, X, X, X | |
831 | }; | |
832 | ||
833 | /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */ | |
834 | static const int mips32_to_micromips_reg_m_map[] = | |
835 | { | |
836 | 0, X, 2, 3, X, X, X, X, | |
837 | X, X, X, X, X, X, X, X, | |
838 | 4, 1, 5, 6, 7, X, X, X, | |
839 | X, X, X, X, X, X, X, X | |
840 | }; | |
841 | ||
842 | /* reg type q: 0, 2-7. 17. */ | |
843 | static const int mips32_to_micromips_reg_q_map[] = | |
844 | { | |
845 | 0, X, 2, 3, 4, 5, 6, 7, | |
846 | X, X, X, X, X, X, X, X, | |
847 | X, 1, X, X, X, X, X, X, | |
848 | X, X, X, X, X, X, X, X | |
849 | }; | |
850 | ||
851 | #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map | |
852 | #undef X | |
853 | ||
854 | /* Map microMIPS register numbers to normal MIPS register numbers. */ | |
855 | ||
856 | #define micromips_to_32_reg_b_map mips16_to_32_reg_map | |
857 | #define micromips_to_32_reg_c_map mips16_to_32_reg_map | |
858 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map | |
859 | #define micromips_to_32_reg_e_map mips16_to_32_reg_map | |
860 | #define micromips_to_32_reg_f_map mips16_to_32_reg_map | |
861 | #define micromips_to_32_reg_g_map mips16_to_32_reg_map | |
862 | ||
863 | /* The microMIPS registers with type h. */ | |
864 | static const unsigned int micromips_to_32_reg_h_map[] = | |
865 | { | |
866 | 5, 5, 6, 4, 4, 4, 4, 4 | |
867 | }; | |
868 | ||
869 | /* The microMIPS registers with type i. */ | |
870 | static const unsigned int micromips_to_32_reg_i_map[] = | |
871 | { | |
872 | 6, 7, 7, 21, 22, 5, 6, 7 | |
873 | }; | |
874 | ||
875 | #define micromips_to_32_reg_l_map mips16_to_32_reg_map | |
876 | ||
877 | /* The microMIPS registers with type m. */ | |
878 | static const unsigned int micromips_to_32_reg_m_map[] = | |
879 | { | |
880 | 0, 17, 2, 3, 16, 18, 19, 20 | |
881 | }; | |
882 | ||
883 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
884 | ||
885 | /* The microMIPS registers with type q. */ | |
886 | static const unsigned int micromips_to_32_reg_q_map[] = | |
887 | { | |
888 | 0, 17, 2, 3, 4, 5, 6, 7 | |
889 | }; | |
890 | ||
891 | /* microMIPS imm type B. */ | |
892 | static const int micromips_imm_b_map[] = | |
893 | { | |
894 | 1, 4, 8, 12, 16, 20, 24, -1 | |
895 | }; | |
896 | ||
897 | /* microMIPS imm type C. */ | |
898 | static const int micromips_imm_c_map[] = | |
899 | { | |
900 | 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535 | |
901 | }; | |
902 | ||
71400594 RS |
903 | /* Classifies the kind of instructions we're interested in when |
904 | implementing -mfix-vr4120. */ | |
c67a084a NC |
905 | enum fix_vr4120_class |
906 | { | |
71400594 RS |
907 | FIX_VR4120_MACC, |
908 | FIX_VR4120_DMACC, | |
909 | FIX_VR4120_MULT, | |
910 | FIX_VR4120_DMULT, | |
911 | FIX_VR4120_DIV, | |
912 | FIX_VR4120_MTHILO, | |
913 | NUM_FIX_VR4120_CLASSES | |
914 | }; | |
915 | ||
c67a084a NC |
916 | /* ...likewise -mfix-loongson2f-jump. */ |
917 | static bfd_boolean mips_fix_loongson2f_jump; | |
918 | ||
919 | /* ...likewise -mfix-loongson2f-nop. */ | |
920 | static bfd_boolean mips_fix_loongson2f_nop; | |
921 | ||
922 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
923 | static bfd_boolean mips_fix_loongson2f; | |
924 | ||
71400594 RS |
925 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
926 | there must be at least one other instruction between an instruction | |
927 | of type X and an instruction of type Y. */ | |
928 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
929 | ||
930 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 931 | static int mips_fix_vr4120; |
4a6a3df4 | 932 | |
7d8e00cf RS |
933 | /* ...likewise -mfix-vr4130. */ |
934 | static int mips_fix_vr4130; | |
935 | ||
6a32d874 CM |
936 | /* ...likewise -mfix-24k. */ |
937 | static int mips_fix_24k; | |
938 | ||
d954098f DD |
939 | /* ...likewise -mfix-cn63xxp1 */ |
940 | static bfd_boolean mips_fix_cn63xxp1; | |
941 | ||
4a6a3df4 AO |
942 | /* We don't relax branches by default, since this causes us to expand |
943 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
944 | fail to compute the offset before expanding the macro to the most | |
945 | efficient expansion. */ | |
946 | ||
947 | static int mips_relax_branch; | |
252b5132 | 948 | \f |
4d7206a2 RS |
949 | /* The expansion of many macros depends on the type of symbol that |
950 | they refer to. For example, when generating position-dependent code, | |
951 | a macro that refers to a symbol may have two different expansions, | |
952 | one which uses GP-relative addresses and one which uses absolute | |
953 | addresses. When generating SVR4-style PIC, a macro may have | |
954 | different expansions for local and global symbols. | |
955 | ||
956 | We handle these situations by generating both sequences and putting | |
957 | them in variant frags. In position-dependent code, the first sequence | |
958 | will be the GP-relative one and the second sequence will be the | |
959 | absolute one. In SVR4 PIC, the first sequence will be for global | |
960 | symbols and the second will be for local symbols. | |
961 | ||
584892a6 RS |
962 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
963 | SECOND are the lengths of the two sequences in bytes. These fields | |
964 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
965 | the subtype has the following flags: | |
4d7206a2 | 966 | |
584892a6 RS |
967 | RELAX_USE_SECOND |
968 | Set if it has been decided that we should use the second | |
969 | sequence instead of the first. | |
970 | ||
971 | RELAX_SECOND_LONGER | |
972 | Set in the first variant frag if the macro's second implementation | |
973 | is longer than its first. This refers to the macro as a whole, | |
974 | not an individual relaxation. | |
975 | ||
976 | RELAX_NOMACRO | |
977 | Set in the first variant frag if the macro appeared in a .set nomacro | |
978 | block and if one alternative requires a warning but the other does not. | |
979 | ||
980 | RELAX_DELAY_SLOT | |
981 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
982 | delay slot. | |
4d7206a2 | 983 | |
df58fc94 RS |
984 | RELAX_DELAY_SLOT_16BIT |
985 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
986 | 16-bit instruction. | |
987 | ||
988 | RELAX_DELAY_SLOT_SIZE_FIRST | |
989 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
990 | the macro is of the wrong size for the branch delay slot. | |
991 | ||
992 | RELAX_DELAY_SLOT_SIZE_SECOND | |
993 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
994 | the macro is of the wrong size for the branch delay slot. | |
995 | ||
4d7206a2 RS |
996 | The frag's "opcode" points to the first fixup for relaxable code. |
997 | ||
998 | Relaxable macros are generated using a sequence such as: | |
999 | ||
1000 | relax_start (SYMBOL); | |
1001 | ... generate first expansion ... | |
1002 | relax_switch (); | |
1003 | ... generate second expansion ... | |
1004 | relax_end (); | |
1005 | ||
1006 | The code and fixups for the unwanted alternative are discarded | |
1007 | by md_convert_frag. */ | |
584892a6 | 1008 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 1009 | |
584892a6 RS |
1010 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1011 | #define RELAX_SECOND(X) ((X) & 0xff) | |
1012 | #define RELAX_USE_SECOND 0x10000 | |
1013 | #define RELAX_SECOND_LONGER 0x20000 | |
1014 | #define RELAX_NOMACRO 0x40000 | |
1015 | #define RELAX_DELAY_SLOT 0x80000 | |
df58fc94 RS |
1016 | #define RELAX_DELAY_SLOT_16BIT 0x100000 |
1017 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 | |
1018 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 | |
252b5132 | 1019 | |
4a6a3df4 AO |
1020 | /* Branch without likely bit. If label is out of range, we turn: |
1021 | ||
1022 | beq reg1, reg2, label | |
1023 | delay slot | |
1024 | ||
1025 | into | |
1026 | ||
1027 | bne reg1, reg2, 0f | |
1028 | nop | |
1029 | j label | |
1030 | 0: delay slot | |
1031 | ||
1032 | with the following opcode replacements: | |
1033 | ||
1034 | beq <-> bne | |
1035 | blez <-> bgtz | |
1036 | bltz <-> bgez | |
1037 | bc1f <-> bc1t | |
1038 | ||
1039 | bltzal <-> bgezal (with jal label instead of j label) | |
1040 | ||
1041 | Even though keeping the delay slot instruction in the delay slot of | |
1042 | the branch would be more efficient, it would be very tricky to do | |
1043 | correctly, because we'd have to introduce a variable frag *after* | |
1044 | the delay slot instruction, and expand that instead. Let's do it | |
1045 | the easy way for now, even if the branch-not-taken case now costs | |
1046 | one additional instruction. Out-of-range branches are not supposed | |
1047 | to be common, anyway. | |
1048 | ||
1049 | Branch likely. If label is out of range, we turn: | |
1050 | ||
1051 | beql reg1, reg2, label | |
1052 | delay slot (annulled if branch not taken) | |
1053 | ||
1054 | into | |
1055 | ||
1056 | beql reg1, reg2, 1f | |
1057 | nop | |
1058 | beql $0, $0, 2f | |
1059 | nop | |
1060 | 1: j[al] label | |
1061 | delay slot (executed only if branch taken) | |
1062 | 2: | |
1063 | ||
1064 | It would be possible to generate a shorter sequence by losing the | |
1065 | likely bit, generating something like: | |
b34976b6 | 1066 | |
4a6a3df4 AO |
1067 | bne reg1, reg2, 0f |
1068 | nop | |
1069 | j[al] label | |
1070 | delay slot (executed only if branch taken) | |
1071 | 0: | |
1072 | ||
1073 | beql -> bne | |
1074 | bnel -> beq | |
1075 | blezl -> bgtz | |
1076 | bgtzl -> blez | |
1077 | bltzl -> bgez | |
1078 | bgezl -> bltz | |
1079 | bc1fl -> bc1t | |
1080 | bc1tl -> bc1f | |
1081 | ||
1082 | bltzall -> bgezal (with jal label instead of j label) | |
1083 | bgezall -> bltzal (ditto) | |
1084 | ||
1085 | ||
1086 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
1087 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
1088 | ((relax_substateT) \ | |
1089 | (0xc0000000 \ | |
1090 | | ((at) & 0x1f) \ | |
1091 | | ((toofar) ? 0x20 : 0) \ | |
1092 | | ((link) ? 0x40 : 0) \ | |
1093 | | ((likely) ? 0x80 : 0) \ | |
1094 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 1095 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
1096 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
1097 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
1098 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
1099 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
1100 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 1101 | |
252b5132 RH |
1102 | /* For mips16 code, we use an entirely different form of relaxation. |
1103 | mips16 supports two versions of most instructions which take | |
1104 | immediate values: a small one which takes some small value, and a | |
1105 | larger one which takes a 16 bit value. Since branches also follow | |
1106 | this pattern, relaxing these values is required. | |
1107 | ||
1108 | We can assemble both mips16 and normal MIPS code in a single | |
1109 | object. Therefore, we need to support this type of relaxation at | |
1110 | the same time that we support the relaxation described above. We | |
1111 | use the high bit of the subtype field to distinguish these cases. | |
1112 | ||
1113 | The information we store for this type of relaxation is the | |
1114 | argument code found in the opcode file for this relocation, whether | |
1115 | the user explicitly requested a small or extended form, and whether | |
1116 | the relocation is in a jump or jal delay slot. That tells us the | |
1117 | size of the value, and how it should be stored. We also store | |
1118 | whether the fragment is considered to be extended or not. We also | |
1119 | store whether this is known to be a branch to a different section, | |
1120 | whether we have tried to relax this frag yet, and whether we have | |
1121 | ever extended a PC relative fragment because of a shift count. */ | |
1122 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
1123 | (0x80000000 \ | |
1124 | | ((type) & 0xff) \ | |
1125 | | ((small) ? 0x100 : 0) \ | |
1126 | | ((ext) ? 0x200 : 0) \ | |
1127 | | ((dslot) ? 0x400 : 0) \ | |
1128 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 1129 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
1130 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
1131 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
1132 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
1133 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
1134 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
1135 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
1136 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
1137 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
1138 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
1139 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
1140 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 | 1141 | |
df58fc94 RS |
1142 | /* For microMIPS code, we use relaxation similar to one we use for |
1143 | MIPS16 code. Some instructions that take immediate values support | |
1144 | two encodings: a small one which takes some small value, and a | |
1145 | larger one which takes a 16 bit value. As some branches also follow | |
1146 | this pattern, relaxing these values is required. | |
1147 | ||
1148 | We can assemble both microMIPS and normal MIPS code in a single | |
1149 | object. Therefore, we need to support this type of relaxation at | |
1150 | the same time that we support the relaxation described above. We | |
1151 | use one of the high bits of the subtype field to distinguish these | |
1152 | cases. | |
1153 | ||
1154 | The information we store for this type of relaxation is the argument | |
1155 | code found in the opcode file for this relocation, the register | |
1156 | selected as the assembler temporary, whether the user explicitly | |
1157 | requested a 16-bit form, whether the branch is unconditional, whether | |
1158 | it is compact, whether it stores the link address implicitly in $ra, | |
1159 | whether relaxation of out-of-range 32-bit branches to a sequence of | |
1160 | instructions is enabled, and whether the displacement of a branch is | |
1161 | too large to fit as an immediate argument of a 16-bit and a 32-bit | |
1162 | branch, respectively. */ | |
1163 | #define RELAX_MICROMIPS_ENCODE(type, at, u16bit, uncond, compact, link, \ | |
1164 | relax32, toofar16, toofar32) \ | |
1165 | (0x40000000 \ | |
1166 | | ((type) & 0xff) \ | |
1167 | | (((at) & 0x1f) << 8) \ | |
1168 | | ((u16bit) ? 0x2000 : 0) \ | |
1169 | | ((uncond) ? 0x4000 : 0) \ | |
1170 | | ((compact) ? 0x8000 : 0) \ | |
1171 | | ((link) ? 0x10000 : 0) \ | |
1172 | | ((relax32) ? 0x20000 : 0) \ | |
1173 | | ((toofar16) ? 0x40000 : 0) \ | |
1174 | | ((toofar32) ? 0x80000 : 0)) | |
1175 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) | |
1176 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1177 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
1178 | #define RELAX_MICROMIPS_U16BIT(i) (((i) & 0x2000) != 0) | |
1179 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x4000) != 0) | |
1180 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x8000) != 0) | |
1181 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x10000) != 0) | |
1182 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x20000) != 0) | |
1183 | ||
1184 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x40000) != 0) | |
1185 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x40000) | |
1186 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x40000) | |
1187 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x80000) != 0) | |
1188 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x80000) | |
1189 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x80000) | |
1190 | ||
885add95 CD |
1191 | /* Is the given value a sign-extended 32-bit value? */ |
1192 | #define IS_SEXT_32BIT_NUM(x) \ | |
1193 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1194 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1195 | ||
1196 | /* Is the given value a sign-extended 16-bit value? */ | |
1197 | #define IS_SEXT_16BIT_NUM(x) \ | |
1198 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1199 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1200 | ||
df58fc94 RS |
1201 | /* Is the given value a sign-extended 12-bit value? */ |
1202 | #define IS_SEXT_12BIT_NUM(x) \ | |
1203 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1204 | ||
2051e8c4 MR |
1205 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1206 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1207 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1208 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1209 | ||
bf12938e RS |
1210 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
1211 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
1212 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
1213 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
1214 | | (((VALUE) & (MASK)) << (SHIFT))) | |
1215 | ||
1216 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
1217 | SHIFT places. */ | |
1218 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1219 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1220 | ||
1221 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1222 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1223 | ||
1224 | include/opcode/mips.h specifies operand fields using the macros | |
1225 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1226 | with "MIPS16OP" instead of "OP". */ | |
df58fc94 RS |
1227 | #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \ |
1228 | do \ | |
1229 | if (!(MICROMIPS)) \ | |
1230 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1231 | OP_MASK_##FIELD, OP_SH_##FIELD); \ | |
1232 | else \ | |
1233 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1234 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \ | |
1235 | while (0) | |
bf12938e RS |
1236 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ |
1237 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1238 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1239 | ||
1240 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
df58fc94 RS |
1241 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1242 | (!(MICROMIPS) \ | |
1243 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1244 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1245 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1246 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1247 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1248 | MIPS16OP_MASK_##FIELD, \ | |
1249 | MIPS16OP_SH_##FIELD) | |
4d7206a2 | 1250 | \f |
df58fc94 RS |
1251 | /* Whether or not we are emitting a branch-likely macro. */ |
1252 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1253 | ||
4d7206a2 RS |
1254 | /* Global variables used when generating relaxable macros. See the |
1255 | comment above RELAX_ENCODE for more details about how relaxation | |
1256 | is used. */ | |
1257 | static struct { | |
1258 | /* 0 if we're not emitting a relaxable macro. | |
1259 | 1 if we're emitting the first of the two relaxation alternatives. | |
1260 | 2 if we're emitting the second alternative. */ | |
1261 | int sequence; | |
1262 | ||
1263 | /* The first relaxable fixup in the current frag. (In other words, | |
1264 | the first fixup that refers to relaxable code.) */ | |
1265 | fixS *first_fixup; | |
1266 | ||
1267 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1268 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1269 | unsigned int sizes[2]; | |
1270 | ||
1271 | /* The symbol on which the choice of sequence depends. */ | |
1272 | symbolS *symbol; | |
1273 | } mips_relax; | |
252b5132 | 1274 | \f |
584892a6 RS |
1275 | /* Global variables used to decide whether a macro needs a warning. */ |
1276 | static struct { | |
1277 | /* True if the macro is in a branch delay slot. */ | |
1278 | bfd_boolean delay_slot_p; | |
1279 | ||
df58fc94 RS |
1280 | /* Set to the length in bytes required if the macro is in a delay slot |
1281 | that requires a specific length of instruction, otherwise zero. */ | |
1282 | unsigned int delay_slot_length; | |
1283 | ||
584892a6 RS |
1284 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1285 | in bytes and sizes[1] is the length of the second alternative. | |
1286 | For non-relaxable macros, both elements give the length of the | |
1287 | macro in bytes. */ | |
1288 | unsigned int sizes[2]; | |
1289 | ||
df58fc94 RS |
1290 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1291 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1292 | is the length of the first instruction of the second alternative. | |
1293 | For non-relaxable macros, both elements give the length of the first | |
1294 | instruction in bytes. | |
1295 | ||
1296 | Set to zero if we haven't yet seen the first instruction. */ | |
1297 | unsigned int first_insn_sizes[2]; | |
1298 | ||
1299 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1300 | first alternative and insns[1] is the number of instructions for the | |
1301 | second alternative. | |
1302 | ||
1303 | For non-relaxable macros, both elements give the number of | |
1304 | instructions for the macro. */ | |
1305 | unsigned int insns[2]; | |
1306 | ||
584892a6 RS |
1307 | /* The first variant frag for this macro. */ |
1308 | fragS *first_frag; | |
1309 | } mips_macro_warning; | |
1310 | \f | |
252b5132 RH |
1311 | /* Prototypes for static functions. */ |
1312 | ||
17a2f251 | 1313 | #define internalError() \ |
252b5132 | 1314 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
1315 | |
1316 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
1317 | ||
b34976b6 | 1318 | static void append_insn |
df58fc94 RS |
1319 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1320 | bfd_boolean expansionp); | |
7d10b47d | 1321 | static void mips_no_prev_insn (void); |
c67a084a | 1322 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1323 | static void mips16_macro_build |
03ea81db | 1324 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1325 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1326 | static void macro_start (void); |
1327 | static void macro_end (void); | |
17a2f251 TS |
1328 | static void macro (struct mips_cl_insn * ip); |
1329 | static void mips16_macro (struct mips_cl_insn * ip); | |
17a2f251 TS |
1330 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1331 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1332 | static void mips16_immed |
17a2f251 TS |
1333 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
1334 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 1335 | static size_t my_getSmallExpression |
17a2f251 TS |
1336 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1337 | static void my_getExpression (expressionS *, char *); | |
1338 | static void s_align (int); | |
1339 | static void s_change_sec (int); | |
1340 | static void s_change_section (int); | |
1341 | static void s_cons (int); | |
1342 | static void s_float_cons (int); | |
1343 | static void s_mips_globl (int); | |
1344 | static void s_option (int); | |
1345 | static void s_mipsset (int); | |
1346 | static void s_abicalls (int); | |
1347 | static void s_cpload (int); | |
1348 | static void s_cpsetup (int); | |
1349 | static void s_cplocal (int); | |
1350 | static void s_cprestore (int); | |
1351 | static void s_cpreturn (int); | |
741d6ea8 JM |
1352 | static void s_dtprelword (int); |
1353 | static void s_dtpreldword (int); | |
17a2f251 TS |
1354 | static void s_gpvalue (int); |
1355 | static void s_gpword (int); | |
1356 | static void s_gpdword (int); | |
1357 | static void s_cpadd (int); | |
1358 | static void s_insn (int); | |
1359 | static void md_obj_begin (void); | |
1360 | static void md_obj_end (void); | |
1361 | static void s_mips_ent (int); | |
1362 | static void s_mips_end (int); | |
1363 | static void s_mips_frame (int); | |
1364 | static void s_mips_mask (int reg_type); | |
1365 | static void s_mips_stab (int); | |
1366 | static void s_mips_weakext (int); | |
1367 | static void s_mips_file (int); | |
1368 | static void s_mips_loc (int); | |
1369 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1370 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1371 | static int validate_mips_insn (const struct mips_opcode *); |
df58fc94 RS |
1372 | static int validate_micromips_insn (const struct mips_opcode *); |
1373 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); | |
1374 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
e7af610e NC |
1375 | |
1376 | /* Table and functions used to map between CPU/ISA names, and | |
1377 | ISA levels, and CPU numbers. */ | |
1378 | ||
e972090a NC |
1379 | struct mips_cpu_info |
1380 | { | |
e7af610e | 1381 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1382 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1383 | int isa; /* ISA level. */ |
1384 | int cpu; /* CPU number (default CPU if ISA). */ | |
1385 | }; | |
1386 | ||
ad3fea08 TS |
1387 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1388 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1389 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1390 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1391 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1392 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1393 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
ad3fea08 | 1394 | |
17a2f251 TS |
1395 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1396 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1397 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1398 | \f |
1399 | /* Pseudo-op table. | |
1400 | ||
1401 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1402 | should be defined here, but are currently unsupported: .alias, | |
1403 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1404 | ||
1405 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1406 | specific to the type of debugging information being generated, and | |
1407 | should be defined by the object format: .aent, .begin, .bend, | |
1408 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1409 | .vreg. | |
1410 | ||
1411 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1412 | not MIPS CPU specific, but are also not specific to the object file | |
1413 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1414 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1415 | |
e972090a NC |
1416 | static const pseudo_typeS mips_pseudo_table[] = |
1417 | { | |
beae10d5 | 1418 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1419 | {"option", s_option, 0}, |
1420 | {"set", s_mipsset, 0}, | |
1421 | {"rdata", s_change_sec, 'r'}, | |
1422 | {"sdata", s_change_sec, 's'}, | |
1423 | {"livereg", s_ignore, 0}, | |
1424 | {"abicalls", s_abicalls, 0}, | |
1425 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1426 | {"cpsetup", s_cpsetup, 0}, |
1427 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1428 | {"cprestore", s_cprestore, 0}, |
6478892d | 1429 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1430 | {"dtprelword", s_dtprelword, 0}, |
1431 | {"dtpreldword", s_dtpreldword, 0}, | |
6478892d | 1432 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1433 | {"gpword", s_gpword, 0}, |
10181a0d | 1434 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1435 | {"cpadd", s_cpadd, 0}, |
1436 | {"insn", s_insn, 0}, | |
1437 | ||
beae10d5 | 1438 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1439 | chips. */ |
38a57ae7 | 1440 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1441 | {"bss", s_change_sec, 'b'}, |
1442 | {"err", s_err, 0}, | |
1443 | {"half", s_cons, 1}, | |
1444 | {"dword", s_cons, 3}, | |
1445 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1446 | {"origin", s_org, 0}, |
1447 | {"repeat", s_rept, 0}, | |
252b5132 | 1448 | |
998b3c36 MR |
1449 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1450 | {"sbss", s_change_sec, 'B'}, | |
1451 | ||
beae10d5 | 1452 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1453 | here for one reason or another. */ |
1454 | {"align", s_align, 0}, | |
1455 | {"byte", s_cons, 0}, | |
1456 | {"data", s_change_sec, 'd'}, | |
1457 | {"double", s_float_cons, 'd'}, | |
1458 | {"float", s_float_cons, 'f'}, | |
1459 | {"globl", s_mips_globl, 0}, | |
1460 | {"global", s_mips_globl, 0}, | |
1461 | {"hword", s_cons, 1}, | |
1462 | {"int", s_cons, 2}, | |
1463 | {"long", s_cons, 2}, | |
1464 | {"octa", s_cons, 4}, | |
1465 | {"quad", s_cons, 3}, | |
cca86cc8 | 1466 | {"section", s_change_section, 0}, |
252b5132 RH |
1467 | {"short", s_cons, 1}, |
1468 | {"single", s_float_cons, 'f'}, | |
1469 | {"stabn", s_mips_stab, 'n'}, | |
1470 | {"text", s_change_sec, 't'}, | |
1471 | {"word", s_cons, 2}, | |
add56521 | 1472 | |
add56521 | 1473 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1474 | |
43841e91 | 1475 | { NULL, NULL, 0 }, |
252b5132 RH |
1476 | }; |
1477 | ||
e972090a NC |
1478 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1479 | { | |
beae10d5 KH |
1480 | /* These pseudo-ops should be defined by the object file format. |
1481 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1482 | {"aent", s_mips_ent, 1}, |
1483 | {"bgnb", s_ignore, 0}, | |
1484 | {"end", s_mips_end, 0}, | |
1485 | {"endb", s_ignore, 0}, | |
1486 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1487 | {"file", s_mips_file, 0}, |
252b5132 RH |
1488 | {"fmask", s_mips_mask, 'F'}, |
1489 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1490 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1491 | {"mask", s_mips_mask, 'R'}, |
1492 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1493 | { NULL, NULL, 0 }, |
252b5132 RH |
1494 | }; |
1495 | ||
3ae8dd8d MR |
1496 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1497 | purpose of the `.dc.a' internal pseudo-op. */ | |
1498 | ||
1499 | int | |
1500 | mips_address_bytes (void) | |
1501 | { | |
1502 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1503 | } | |
1504 | ||
17a2f251 | 1505 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1506 | |
1507 | void | |
17a2f251 | 1508 | mips_pop_insert (void) |
252b5132 RH |
1509 | { |
1510 | pop_insert (mips_pseudo_table); | |
1511 | if (! ECOFF_DEBUGGING) | |
1512 | pop_insert (mips_nonecoff_pseudo_table); | |
1513 | } | |
1514 | \f | |
1515 | /* Symbols labelling the current insn. */ | |
1516 | ||
e972090a NC |
1517 | struct insn_label_list |
1518 | { | |
252b5132 RH |
1519 | struct insn_label_list *next; |
1520 | symbolS *label; | |
1521 | }; | |
1522 | ||
252b5132 | 1523 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1524 | #define label_list tc_segment_info_data.labels |
252b5132 | 1525 | |
17a2f251 | 1526 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1527 | static void mips_mark_labels (void); |
1528 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1529 | |
1530 | static inline void | |
17a2f251 | 1531 | mips_clear_insn_labels (void) |
252b5132 RH |
1532 | { |
1533 | register struct insn_label_list **pl; | |
a8dbcb85 | 1534 | segment_info_type *si; |
252b5132 | 1535 | |
a8dbcb85 TS |
1536 | if (now_seg) |
1537 | { | |
1538 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1539 | ; | |
1540 | ||
1541 | si = seg_info (now_seg); | |
1542 | *pl = si->label_list; | |
1543 | si->label_list = NULL; | |
1544 | } | |
252b5132 | 1545 | } |
a8dbcb85 | 1546 | |
df58fc94 RS |
1547 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1548 | ||
1549 | static inline void | |
1550 | mips_mark_labels (void) | |
1551 | { | |
1552 | if (HAVE_CODE_COMPRESSION) | |
1553 | mips_compressed_mark_labels (); | |
1554 | } | |
252b5132 RH |
1555 | \f |
1556 | static char *expr_end; | |
1557 | ||
1558 | /* Expressions which appear in instructions. These are set by | |
1559 | mips_ip. */ | |
1560 | ||
1561 | static expressionS imm_expr; | |
5f74bc13 | 1562 | static expressionS imm2_expr; |
252b5132 RH |
1563 | static expressionS offset_expr; |
1564 | ||
1565 | /* Relocs associated with imm_expr and offset_expr. */ | |
1566 | ||
f6688943 TS |
1567 | static bfd_reloc_code_real_type imm_reloc[3] |
1568 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1569 | static bfd_reloc_code_real_type offset_reloc[3] | |
1570 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1571 | |
df58fc94 RS |
1572 | /* This is set to the resulting size of the instruction to be produced |
1573 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1574 | explicit size is supplied. */ | |
252b5132 | 1575 | |
df58fc94 | 1576 | static unsigned int forced_insn_length; |
252b5132 | 1577 | |
7ed4a06a | 1578 | #ifdef OBJ_ELF |
ecb4347a DJ |
1579 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1580 | ECOFF debugging. */ | |
252b5132 RH |
1581 | |
1582 | static segT pdr_seg; | |
7ed4a06a | 1583 | #endif |
252b5132 | 1584 | |
e013f690 TS |
1585 | /* The default target format to use. */ |
1586 | ||
aeffff67 RS |
1587 | #if defined (TE_FreeBSD) |
1588 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1589 | #elif defined (TE_TMIPS) | |
1590 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1591 | #else | |
1592 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1593 | #endif | |
1594 | ||
e013f690 | 1595 | const char * |
17a2f251 | 1596 | mips_target_format (void) |
e013f690 TS |
1597 | { |
1598 | switch (OUTPUT_FLAVOR) | |
1599 | { | |
e013f690 TS |
1600 | case bfd_target_ecoff_flavour: |
1601 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1602 | case bfd_target_coff_flavour: | |
1603 | return "pe-mips"; | |
1604 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1605 | #ifdef TE_VXWORKS |
1606 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1607 | return (target_big_endian | |
1608 | ? "elf32-bigmips-vxworks" | |
1609 | : "elf32-littlemips-vxworks"); | |
1610 | #endif | |
e013f690 | 1611 | return (target_big_endian |
cfe86eaa | 1612 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1613 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1614 | : (HAVE_NEWABI |
aeffff67 RS |
1615 | ? ELF_TARGET ("elf32-n", "big") |
1616 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1617 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1618 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1619 | : (HAVE_NEWABI |
aeffff67 RS |
1620 | ? ELF_TARGET ("elf32-n", "little") |
1621 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1622 | default: |
1623 | abort (); | |
1624 | return NULL; | |
1625 | } | |
1626 | } | |
1627 | ||
df58fc94 RS |
1628 | /* Return the length of a microMIPS instruction in bytes. If bits of |
1629 | the mask beyond the low 16 are 0, then it is a 16-bit instruction. | |
1630 | Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f | |
1631 | major opcode) will require further modifications to the opcode | |
1632 | table. */ | |
1633 | ||
1634 | static inline unsigned int | |
1635 | micromips_insn_length (const struct mips_opcode *mo) | |
1636 | { | |
1637 | return (mo->mask >> 16) == 0 ? 2 : 4; | |
1638 | } | |
1639 | ||
1e915849 RS |
1640 | /* Return the length of instruction INSN. */ |
1641 | ||
1642 | static inline unsigned int | |
1643 | insn_length (const struct mips_cl_insn *insn) | |
1644 | { | |
df58fc94 RS |
1645 | if (mips_opts.micromips) |
1646 | return micromips_insn_length (insn->insn_mo); | |
1647 | else if (mips_opts.mips16) | |
1648 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1649 | else | |
1e915849 | 1650 | return 4; |
1e915849 RS |
1651 | } |
1652 | ||
1653 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1654 | ||
1655 | static void | |
1656 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1657 | { | |
1658 | size_t i; | |
1659 | ||
1660 | insn->insn_mo = mo; | |
1661 | insn->use_extend = FALSE; | |
1662 | insn->extend = 0; | |
1663 | insn->insn_opcode = mo->match; | |
1664 | insn->frag = NULL; | |
1665 | insn->where = 0; | |
1666 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1667 | insn->fixp[i] = NULL; | |
1668 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1669 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1670 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 1671 | insn->complete_p = 0; |
1e915849 RS |
1672 | } |
1673 | ||
df58fc94 | 1674 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
1675 | |
1676 | static void | |
df58fc94 | 1677 | mips_record_compressed_mode (void) |
742a56fe RS |
1678 | { |
1679 | segment_info_type *si; | |
1680 | ||
1681 | si = seg_info (now_seg); | |
1682 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1683 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
1684 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
1685 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
1686 | } |
1687 | ||
1e915849 RS |
1688 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1689 | ||
1690 | static void | |
1691 | install_insn (const struct mips_cl_insn *insn) | |
1692 | { | |
1693 | char *f = insn->frag->fr_literal + insn->where; | |
df58fc94 | 1694 | if (!HAVE_CODE_COMPRESSION) |
1e915849 | 1695 | md_number_to_chars (f, insn->insn_opcode, 4); |
df58fc94 RS |
1696 | else if (mips_opts.micromips) |
1697 | { | |
1698 | unsigned int length = insn_length (insn); | |
1699 | if (length == 2) | |
1700 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1701 | else if (length == 4) | |
1702 | { | |
1703 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1704 | f += 2; | |
1705 | md_number_to_chars (f, insn->insn_opcode & 0xffff, 2); | |
1706 | } | |
1707 | else | |
1708 | as_bad (_("48-bit microMIPS instructions are not supported")); | |
1709 | } | |
1e915849 RS |
1710 | else if (insn->mips16_absolute_jump_p) |
1711 | { | |
1712 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1713 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1714 | } | |
1715 | else | |
1716 | { | |
1717 | if (insn->use_extend) | |
1718 | { | |
1719 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1720 | f += 2; | |
1721 | } | |
1722 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1723 | } | |
df58fc94 | 1724 | mips_record_compressed_mode (); |
1e915849 RS |
1725 | } |
1726 | ||
1727 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1728 | and install the opcode in the new location. */ | |
1729 | ||
1730 | static void | |
1731 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1732 | { | |
1733 | size_t i; | |
1734 | ||
1735 | insn->frag = frag; | |
1736 | insn->where = where; | |
1737 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1738 | if (insn->fixp[i] != NULL) | |
1739 | { | |
1740 | insn->fixp[i]->fx_frag = frag; | |
1741 | insn->fixp[i]->fx_where = where; | |
1742 | } | |
1743 | install_insn (insn); | |
1744 | } | |
1745 | ||
1746 | /* Add INSN to the end of the output. */ | |
1747 | ||
1748 | static void | |
1749 | add_fixed_insn (struct mips_cl_insn *insn) | |
1750 | { | |
1751 | char *f = frag_more (insn_length (insn)); | |
1752 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1753 | } | |
1754 | ||
1755 | /* Start a variant frag and move INSN to the start of the variant part, | |
1756 | marking it as fixed. The other arguments are as for frag_var. */ | |
1757 | ||
1758 | static void | |
1759 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1760 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1761 | { | |
1762 | frag_grow (max_chars); | |
1763 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1764 | insn->fixed_p = 1; | |
1765 | frag_var (rs_machine_dependent, max_chars, var, | |
1766 | subtype, symbol, offset, NULL); | |
1767 | } | |
1768 | ||
1769 | /* Insert N copies of INSN into the history buffer, starting at | |
1770 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1771 | ||
1772 | static void | |
1773 | insert_into_history (unsigned int first, unsigned int n, | |
1774 | const struct mips_cl_insn *insn) | |
1775 | { | |
1776 | if (mips_relax.sequence != 2) | |
1777 | { | |
1778 | unsigned int i; | |
1779 | ||
1780 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1781 | if (i >= first + n) | |
1782 | history[i] = history[i - n]; | |
1783 | else | |
1784 | history[i] = *insn; | |
1785 | } | |
1786 | } | |
1787 | ||
1788 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1789 | ||
1790 | static void | |
1791 | emit_nop (void) | |
1792 | { | |
1793 | add_fixed_insn (NOP_INSN); | |
1794 | insert_into_history (0, 1, NOP_INSN); | |
1795 | } | |
1796 | ||
71400594 RS |
1797 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1798 | the idea is to make it obvious at a glance that each errata is | |
1799 | included. */ | |
1800 | ||
1801 | static void | |
1802 | init_vr4120_conflicts (void) | |
1803 | { | |
1804 | #define CONFLICT(FIRST, SECOND) \ | |
1805 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1806 | ||
1807 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1808 | CONFLICT (MACC, DIV); | |
1809 | CONFLICT (DMACC, DIV); | |
1810 | ||
1811 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1812 | CONFLICT (DMULT, DMULT); | |
1813 | CONFLICT (DMULT, DMACC); | |
1814 | CONFLICT (DMACC, DMULT); | |
1815 | CONFLICT (DMACC, DMACC); | |
1816 | ||
1817 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1818 | CONFLICT (MACC, MTHILO); | |
1819 | CONFLICT (DMACC, MTHILO); | |
1820 | ||
1821 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1822 | instruction is executed immediately after a MACC or DMACC | |
1823 | instruction, the result of [either instruction] is incorrect." */ | |
1824 | CONFLICT (MACC, MULT); | |
1825 | CONFLICT (MACC, DMULT); | |
1826 | CONFLICT (DMACC, MULT); | |
1827 | CONFLICT (DMACC, DMULT); | |
1828 | ||
1829 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1830 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1831 | DDIV or DDIVU instruction, the result of the MACC or | |
1832 | DMACC instruction is incorrect.". */ | |
1833 | CONFLICT (DMULT, MACC); | |
1834 | CONFLICT (DMULT, DMACC); | |
1835 | CONFLICT (DIV, MACC); | |
1836 | CONFLICT (DIV, DMACC); | |
1837 | ||
1838 | #undef CONFLICT | |
1839 | } | |
1840 | ||
707bfff6 TS |
1841 | struct regname { |
1842 | const char *name; | |
1843 | unsigned int num; | |
1844 | }; | |
1845 | ||
1846 | #define RTYPE_MASK 0x1ff00 | |
1847 | #define RTYPE_NUM 0x00100 | |
1848 | #define RTYPE_FPU 0x00200 | |
1849 | #define RTYPE_FCC 0x00400 | |
1850 | #define RTYPE_VEC 0x00800 | |
1851 | #define RTYPE_GP 0x01000 | |
1852 | #define RTYPE_CP0 0x02000 | |
1853 | #define RTYPE_PC 0x04000 | |
1854 | #define RTYPE_ACC 0x08000 | |
1855 | #define RTYPE_CCC 0x10000 | |
1856 | #define RNUM_MASK 0x000ff | |
1857 | #define RWARN 0x80000 | |
1858 | ||
1859 | #define GENERIC_REGISTER_NUMBERS \ | |
1860 | {"$0", RTYPE_NUM | 0}, \ | |
1861 | {"$1", RTYPE_NUM | 1}, \ | |
1862 | {"$2", RTYPE_NUM | 2}, \ | |
1863 | {"$3", RTYPE_NUM | 3}, \ | |
1864 | {"$4", RTYPE_NUM | 4}, \ | |
1865 | {"$5", RTYPE_NUM | 5}, \ | |
1866 | {"$6", RTYPE_NUM | 6}, \ | |
1867 | {"$7", RTYPE_NUM | 7}, \ | |
1868 | {"$8", RTYPE_NUM | 8}, \ | |
1869 | {"$9", RTYPE_NUM | 9}, \ | |
1870 | {"$10", RTYPE_NUM | 10}, \ | |
1871 | {"$11", RTYPE_NUM | 11}, \ | |
1872 | {"$12", RTYPE_NUM | 12}, \ | |
1873 | {"$13", RTYPE_NUM | 13}, \ | |
1874 | {"$14", RTYPE_NUM | 14}, \ | |
1875 | {"$15", RTYPE_NUM | 15}, \ | |
1876 | {"$16", RTYPE_NUM | 16}, \ | |
1877 | {"$17", RTYPE_NUM | 17}, \ | |
1878 | {"$18", RTYPE_NUM | 18}, \ | |
1879 | {"$19", RTYPE_NUM | 19}, \ | |
1880 | {"$20", RTYPE_NUM | 20}, \ | |
1881 | {"$21", RTYPE_NUM | 21}, \ | |
1882 | {"$22", RTYPE_NUM | 22}, \ | |
1883 | {"$23", RTYPE_NUM | 23}, \ | |
1884 | {"$24", RTYPE_NUM | 24}, \ | |
1885 | {"$25", RTYPE_NUM | 25}, \ | |
1886 | {"$26", RTYPE_NUM | 26}, \ | |
1887 | {"$27", RTYPE_NUM | 27}, \ | |
1888 | {"$28", RTYPE_NUM | 28}, \ | |
1889 | {"$29", RTYPE_NUM | 29}, \ | |
1890 | {"$30", RTYPE_NUM | 30}, \ | |
1891 | {"$31", RTYPE_NUM | 31} | |
1892 | ||
1893 | #define FPU_REGISTER_NAMES \ | |
1894 | {"$f0", RTYPE_FPU | 0}, \ | |
1895 | {"$f1", RTYPE_FPU | 1}, \ | |
1896 | {"$f2", RTYPE_FPU | 2}, \ | |
1897 | {"$f3", RTYPE_FPU | 3}, \ | |
1898 | {"$f4", RTYPE_FPU | 4}, \ | |
1899 | {"$f5", RTYPE_FPU | 5}, \ | |
1900 | {"$f6", RTYPE_FPU | 6}, \ | |
1901 | {"$f7", RTYPE_FPU | 7}, \ | |
1902 | {"$f8", RTYPE_FPU | 8}, \ | |
1903 | {"$f9", RTYPE_FPU | 9}, \ | |
1904 | {"$f10", RTYPE_FPU | 10}, \ | |
1905 | {"$f11", RTYPE_FPU | 11}, \ | |
1906 | {"$f12", RTYPE_FPU | 12}, \ | |
1907 | {"$f13", RTYPE_FPU | 13}, \ | |
1908 | {"$f14", RTYPE_FPU | 14}, \ | |
1909 | {"$f15", RTYPE_FPU | 15}, \ | |
1910 | {"$f16", RTYPE_FPU | 16}, \ | |
1911 | {"$f17", RTYPE_FPU | 17}, \ | |
1912 | {"$f18", RTYPE_FPU | 18}, \ | |
1913 | {"$f19", RTYPE_FPU | 19}, \ | |
1914 | {"$f20", RTYPE_FPU | 20}, \ | |
1915 | {"$f21", RTYPE_FPU | 21}, \ | |
1916 | {"$f22", RTYPE_FPU | 22}, \ | |
1917 | {"$f23", RTYPE_FPU | 23}, \ | |
1918 | {"$f24", RTYPE_FPU | 24}, \ | |
1919 | {"$f25", RTYPE_FPU | 25}, \ | |
1920 | {"$f26", RTYPE_FPU | 26}, \ | |
1921 | {"$f27", RTYPE_FPU | 27}, \ | |
1922 | {"$f28", RTYPE_FPU | 28}, \ | |
1923 | {"$f29", RTYPE_FPU | 29}, \ | |
1924 | {"$f30", RTYPE_FPU | 30}, \ | |
1925 | {"$f31", RTYPE_FPU | 31} | |
1926 | ||
1927 | #define FPU_CONDITION_CODE_NAMES \ | |
1928 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1929 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1930 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1931 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1932 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1933 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1934 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1935 | {"$fcc7", RTYPE_FCC | 7} | |
1936 | ||
1937 | #define COPROC_CONDITION_CODE_NAMES \ | |
1938 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1939 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1940 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1941 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1942 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1943 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1944 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1945 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1946 | ||
1947 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1948 | {"$a4", RTYPE_GP | 8}, \ | |
1949 | {"$a5", RTYPE_GP | 9}, \ | |
1950 | {"$a6", RTYPE_GP | 10}, \ | |
1951 | {"$a7", RTYPE_GP | 11}, \ | |
1952 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1953 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1954 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1955 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1956 | {"$t0", RTYPE_GP | 12}, \ | |
1957 | {"$t1", RTYPE_GP | 13}, \ | |
1958 | {"$t2", RTYPE_GP | 14}, \ | |
1959 | {"$t3", RTYPE_GP | 15} | |
1960 | ||
1961 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1962 | {"$t0", RTYPE_GP | 8}, \ | |
1963 | {"$t1", RTYPE_GP | 9}, \ | |
1964 | {"$t2", RTYPE_GP | 10}, \ | |
1965 | {"$t3", RTYPE_GP | 11}, \ | |
1966 | {"$t4", RTYPE_GP | 12}, \ | |
1967 | {"$t5", RTYPE_GP | 13}, \ | |
1968 | {"$t6", RTYPE_GP | 14}, \ | |
1969 | {"$t7", RTYPE_GP | 15}, \ | |
1970 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1971 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1972 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1973 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
1974 | ||
1975 | /* Remaining symbolic register names */ | |
1976 | #define SYMBOLIC_REGISTER_NAMES \ | |
1977 | {"$zero", RTYPE_GP | 0}, \ | |
1978 | {"$at", RTYPE_GP | 1}, \ | |
1979 | {"$AT", RTYPE_GP | 1}, \ | |
1980 | {"$v0", RTYPE_GP | 2}, \ | |
1981 | {"$v1", RTYPE_GP | 3}, \ | |
1982 | {"$a0", RTYPE_GP | 4}, \ | |
1983 | {"$a1", RTYPE_GP | 5}, \ | |
1984 | {"$a2", RTYPE_GP | 6}, \ | |
1985 | {"$a3", RTYPE_GP | 7}, \ | |
1986 | {"$s0", RTYPE_GP | 16}, \ | |
1987 | {"$s1", RTYPE_GP | 17}, \ | |
1988 | {"$s2", RTYPE_GP | 18}, \ | |
1989 | {"$s3", RTYPE_GP | 19}, \ | |
1990 | {"$s4", RTYPE_GP | 20}, \ | |
1991 | {"$s5", RTYPE_GP | 21}, \ | |
1992 | {"$s6", RTYPE_GP | 22}, \ | |
1993 | {"$s7", RTYPE_GP | 23}, \ | |
1994 | {"$t8", RTYPE_GP | 24}, \ | |
1995 | {"$t9", RTYPE_GP | 25}, \ | |
1996 | {"$k0", RTYPE_GP | 26}, \ | |
1997 | {"$kt0", RTYPE_GP | 26}, \ | |
1998 | {"$k1", RTYPE_GP | 27}, \ | |
1999 | {"$kt1", RTYPE_GP | 27}, \ | |
2000 | {"$gp", RTYPE_GP | 28}, \ | |
2001 | {"$sp", RTYPE_GP | 29}, \ | |
2002 | {"$s8", RTYPE_GP | 30}, \ | |
2003 | {"$fp", RTYPE_GP | 30}, \ | |
2004 | {"$ra", RTYPE_GP | 31} | |
2005 | ||
2006 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2007 | {"$pc", RTYPE_PC | 0} | |
2008 | ||
2009 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2010 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2011 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2012 | {"$v2", RTYPE_VEC | 2}, \ | |
2013 | {"$v3", RTYPE_VEC | 3}, \ | |
2014 | {"$v4", RTYPE_VEC | 4}, \ | |
2015 | {"$v5", RTYPE_VEC | 5}, \ | |
2016 | {"$v6", RTYPE_VEC | 6}, \ | |
2017 | {"$v7", RTYPE_VEC | 7}, \ | |
2018 | {"$v8", RTYPE_VEC | 8}, \ | |
2019 | {"$v9", RTYPE_VEC | 9}, \ | |
2020 | {"$v10", RTYPE_VEC | 10}, \ | |
2021 | {"$v11", RTYPE_VEC | 11}, \ | |
2022 | {"$v12", RTYPE_VEC | 12}, \ | |
2023 | {"$v13", RTYPE_VEC | 13}, \ | |
2024 | {"$v14", RTYPE_VEC | 14}, \ | |
2025 | {"$v15", RTYPE_VEC | 15}, \ | |
2026 | {"$v16", RTYPE_VEC | 16}, \ | |
2027 | {"$v17", RTYPE_VEC | 17}, \ | |
2028 | {"$v18", RTYPE_VEC | 18}, \ | |
2029 | {"$v19", RTYPE_VEC | 19}, \ | |
2030 | {"$v20", RTYPE_VEC | 20}, \ | |
2031 | {"$v21", RTYPE_VEC | 21}, \ | |
2032 | {"$v22", RTYPE_VEC | 22}, \ | |
2033 | {"$v23", RTYPE_VEC | 23}, \ | |
2034 | {"$v24", RTYPE_VEC | 24}, \ | |
2035 | {"$v25", RTYPE_VEC | 25}, \ | |
2036 | {"$v26", RTYPE_VEC | 26}, \ | |
2037 | {"$v27", RTYPE_VEC | 27}, \ | |
2038 | {"$v28", RTYPE_VEC | 28}, \ | |
2039 | {"$v29", RTYPE_VEC | 29}, \ | |
2040 | {"$v30", RTYPE_VEC | 30}, \ | |
2041 | {"$v31", RTYPE_VEC | 31} | |
2042 | ||
2043 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
2044 | {"$ac0", RTYPE_ACC | 0}, \ | |
2045 | {"$ac1", RTYPE_ACC | 1}, \ | |
2046 | {"$ac2", RTYPE_ACC | 2}, \ | |
2047 | {"$ac3", RTYPE_ACC | 3} | |
2048 | ||
2049 | static const struct regname reg_names[] = { | |
2050 | GENERIC_REGISTER_NUMBERS, | |
2051 | FPU_REGISTER_NAMES, | |
2052 | FPU_CONDITION_CODE_NAMES, | |
2053 | COPROC_CONDITION_CODE_NAMES, | |
2054 | ||
2055 | /* The $txx registers depends on the abi, | |
2056 | these will be added later into the symbol table from | |
2057 | one of the tables below once mips_abi is set after | |
2058 | parsing of arguments from the command line. */ | |
2059 | SYMBOLIC_REGISTER_NAMES, | |
2060 | ||
2061 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2062 | MDMX_VECTOR_REGISTER_NAMES, | |
2063 | MIPS_DSP_ACCUMULATOR_NAMES, | |
2064 | {0, 0} | |
2065 | }; | |
2066 | ||
2067 | static const struct regname reg_names_o32[] = { | |
2068 | O32_SYMBOLIC_REGISTER_NAMES, | |
2069 | {0, 0} | |
2070 | }; | |
2071 | ||
2072 | static const struct regname reg_names_n32n64[] = { | |
2073 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2074 | {0, 0} | |
2075 | }; | |
2076 | ||
df58fc94 RS |
2077 | /* Check if S points at a valid register specifier according to TYPES. |
2078 | If so, then return 1, advance S to consume the specifier and store | |
2079 | the register's number in REGNOP, otherwise return 0. */ | |
2080 | ||
707bfff6 TS |
2081 | static int |
2082 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2083 | { | |
2084 | symbolS *symbolP; | |
2085 | char *e; | |
2086 | char save_c; | |
2087 | int reg = -1; | |
2088 | ||
2089 | /* Find end of name. */ | |
2090 | e = *s; | |
2091 | if (is_name_beginner (*e)) | |
2092 | ++e; | |
2093 | while (is_part_of_name (*e)) | |
2094 | ++e; | |
2095 | ||
2096 | /* Terminate name. */ | |
2097 | save_c = *e; | |
2098 | *e = '\0'; | |
2099 | ||
2100 | /* Look for a register symbol. */ | |
2101 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
2102 | { | |
2103 | int r = S_GET_VALUE (symbolP); | |
2104 | if (r & types) | |
2105 | reg = r & RNUM_MASK; | |
2106 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
2107 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
2108 | reg = (r & RNUM_MASK) - 2; | |
2109 | } | |
2110 | /* Else see if this is a register defined in an itbl entry. */ | |
2111 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
2112 | { | |
2113 | char *n = *s; | |
2114 | unsigned long r; | |
2115 | ||
2116 | if (*n == '$') | |
2117 | ++n; | |
2118 | if (itbl_get_reg_val (n, &r)) | |
2119 | reg = r & RNUM_MASK; | |
2120 | } | |
2121 | ||
2122 | /* Advance to next token if a register was recognised. */ | |
2123 | if (reg >= 0) | |
2124 | *s = e; | |
2125 | else if (types & RWARN) | |
20203fb9 | 2126 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
2127 | |
2128 | *e = save_c; | |
2129 | if (regnop) | |
2130 | *regnop = reg; | |
2131 | return reg >= 0; | |
2132 | } | |
2133 | ||
df58fc94 RS |
2134 | /* Check if S points at a valid register list according to TYPES. |
2135 | If so, then return 1, advance S to consume the list and store | |
2136 | the registers present on the list as a bitmask of ones in REGLISTP, | |
2137 | otherwise return 0. A valid list comprises a comma-separated | |
2138 | enumeration of valid single registers and/or dash-separated | |
2139 | contiguous register ranges as determined by their numbers. | |
2140 | ||
2141 | As a special exception if one of s0-s7 registers is specified as | |
2142 | the range's lower delimiter and s8 (fp) is its upper one, then no | |
2143 | registers whose numbers place them between s7 and s8 (i.e. $24-$29) | |
2309ddf2 | 2144 | are selected; they have to be listed separately if needed. */ |
df58fc94 RS |
2145 | |
2146 | static int | |
2147 | reglist_lookup (char **s, unsigned int types, unsigned int *reglistp) | |
2148 | { | |
2149 | unsigned int reglist = 0; | |
2150 | unsigned int lastregno; | |
2151 | bfd_boolean ok = TRUE; | |
2152 | unsigned int regmask; | |
2309ddf2 | 2153 | char *s_endlist = *s; |
df58fc94 | 2154 | char *s_reset = *s; |
2309ddf2 | 2155 | unsigned int regno; |
df58fc94 RS |
2156 | |
2157 | while (reg_lookup (s, types, ®no)) | |
2158 | { | |
2159 | lastregno = regno; | |
2160 | if (**s == '-') | |
2161 | { | |
2162 | (*s)++; | |
2163 | ok = reg_lookup (s, types, &lastregno); | |
2164 | if (ok && lastregno < regno) | |
2165 | ok = FALSE; | |
2166 | if (!ok) | |
2167 | break; | |
2168 | } | |
2169 | ||
2170 | if (lastregno == FP && regno >= S0 && regno <= S7) | |
2171 | { | |
2172 | lastregno = S7; | |
2173 | reglist |= 1 << FP; | |
2174 | } | |
2175 | regmask = 1 << lastregno; | |
2176 | regmask = (regmask << 1) - 1; | |
2177 | regmask ^= (1 << regno) - 1; | |
2178 | reglist |= regmask; | |
2179 | ||
2309ddf2 | 2180 | s_endlist = *s; |
df58fc94 RS |
2181 | if (**s != ',') |
2182 | break; | |
2183 | (*s)++; | |
2184 | } | |
2185 | ||
2186 | if (ok) | |
2309ddf2 | 2187 | *s = s_endlist; |
df58fc94 RS |
2188 | else |
2189 | *s = s_reset; | |
2190 | if (reglistp) | |
2191 | *reglistp = reglist; | |
2192 | return ok && reglist != 0; | |
2193 | } | |
2194 | ||
037b32b9 | 2195 | /* Return TRUE if opcode MO is valid on the currently selected ISA and |
f79e2745 | 2196 | architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ |
037b32b9 AN |
2197 | |
2198 | static bfd_boolean | |
f79e2745 | 2199 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
2200 | { |
2201 | int isa = mips_opts.isa; | |
2202 | int fp_s, fp_d; | |
2203 | ||
2204 | if (mips_opts.ase_mdmx) | |
2205 | isa |= INSN_MDMX; | |
2206 | if (mips_opts.ase_dsp) | |
2207 | isa |= INSN_DSP; | |
2208 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
2209 | isa |= INSN_DSP64; | |
2210 | if (mips_opts.ase_dspr2) | |
2211 | isa |= INSN_DSPR2; | |
2212 | if (mips_opts.ase_mt) | |
2213 | isa |= INSN_MT; | |
2214 | if (mips_opts.ase_mips3d) | |
2215 | isa |= INSN_MIPS3D; | |
2216 | if (mips_opts.ase_smartmips) | |
2217 | isa |= INSN_SMARTMIPS; | |
2218 | ||
b19e8a9b AN |
2219 | /* Don't accept instructions based on the ISA if the CPU does not implement |
2220 | all the coprocessor insns. */ | |
2221 | if (NO_ISA_COP (mips_opts.arch) | |
2222 | && COP_INSN (mo->pinfo)) | |
2223 | isa = 0; | |
2224 | ||
037b32b9 AN |
2225 | if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch)) |
2226 | return FALSE; | |
2227 | ||
2228 | /* Check whether the instruction or macro requires single-precision or | |
2229 | double-precision floating-point support. Note that this information is | |
2230 | stored differently in the opcode table for insns and macros. */ | |
2231 | if (mo->pinfo == INSN_MACRO) | |
2232 | { | |
2233 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
2234 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
2235 | } | |
2236 | else | |
2237 | { | |
2238 | fp_s = mo->pinfo & FP_S; | |
2239 | fp_d = mo->pinfo & FP_D; | |
2240 | } | |
2241 | ||
2242 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
2243 | return FALSE; | |
2244 | ||
2245 | if (fp_s && mips_opts.soft_float) | |
2246 | return FALSE; | |
2247 | ||
2248 | return TRUE; | |
2249 | } | |
2250 | ||
2251 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
2252 | selected ISA and architecture. */ | |
2253 | ||
2254 | static bfd_boolean | |
2255 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
2256 | { | |
2257 | return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE; | |
2258 | } | |
2259 | ||
df58fc94 RS |
2260 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
2261 | explicitly requested. Always TRUE in the standard MIPS mode. */ | |
2262 | ||
2263 | static bfd_boolean | |
2264 | is_size_valid (const struct mips_opcode *mo) | |
2265 | { | |
2266 | if (!mips_opts.micromips) | |
2267 | return TRUE; | |
2268 | ||
2269 | if (!forced_insn_length) | |
2270 | return TRUE; | |
2271 | if (mo->pinfo == INSN_MACRO) | |
2272 | return FALSE; | |
2273 | return forced_insn_length == micromips_insn_length (mo); | |
2274 | } | |
2275 | ||
2276 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot | |
2277 | of the preceding instruction. Always TRUE in the standard MIPS mode. */ | |
2278 | ||
2279 | static bfd_boolean | |
2280 | is_delay_slot_valid (const struct mips_opcode *mo) | |
2281 | { | |
2282 | if (!mips_opts.micromips) | |
2283 | return TRUE; | |
2284 | ||
2285 | if (mo->pinfo == INSN_MACRO) | |
2286 | return TRUE; | |
2287 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
2288 | && micromips_insn_length (mo) != 4) | |
2289 | return FALSE; | |
2290 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
2291 | && micromips_insn_length (mo) != 2) | |
2292 | return FALSE; | |
2293 | ||
2294 | return TRUE; | |
2295 | } | |
2296 | ||
707bfff6 TS |
2297 | /* This function is called once, at assembler startup time. It should set up |
2298 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 2299 | |
252b5132 | 2300 | void |
17a2f251 | 2301 | md_begin (void) |
252b5132 | 2302 | { |
3994f87e | 2303 | const char *retval = NULL; |
156c2f8b | 2304 | int i = 0; |
252b5132 | 2305 | int broken = 0; |
1f25f5d3 | 2306 | |
0a44bf69 RS |
2307 | if (mips_pic != NO_PIC) |
2308 | { | |
2309 | if (g_switch_seen && g_switch_value != 0) | |
2310 | as_bad (_("-G may not be used in position-independent code")); | |
2311 | g_switch_value = 0; | |
2312 | } | |
2313 | ||
fef14a42 | 2314 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
2315 | as_warn (_("Could not set architecture and machine")); |
2316 | ||
252b5132 RH |
2317 | op_hash = hash_new (); |
2318 | ||
2319 | for (i = 0; i < NUMOPCODES;) | |
2320 | { | |
2321 | const char *name = mips_opcodes[i].name; | |
2322 | ||
17a2f251 | 2323 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
2324 | if (retval != NULL) |
2325 | { | |
2326 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
2327 | mips_opcodes[i].name, retval); | |
2328 | /* Probably a memory allocation problem? Give up now. */ | |
2329 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2330 | } | |
2331 | do | |
2332 | { | |
2333 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
2334 | { | |
2335 | if (!validate_mips_insn (&mips_opcodes[i])) | |
2336 | broken = 1; | |
1e915849 RS |
2337 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2338 | { | |
2339 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
2340 | if (mips_fix_loongson2f_nop) |
2341 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
2342 | nop_insn.fixed_p = 1; |
2343 | } | |
252b5132 RH |
2344 | } |
2345 | ++i; | |
2346 | } | |
2347 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
2348 | } | |
2349 | ||
2350 | mips16_op_hash = hash_new (); | |
2351 | ||
2352 | i = 0; | |
2353 | while (i < bfd_mips16_num_opcodes) | |
2354 | { | |
2355 | const char *name = mips16_opcodes[i].name; | |
2356 | ||
17a2f251 | 2357 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
2358 | if (retval != NULL) |
2359 | as_fatal (_("internal: can't hash `%s': %s"), | |
2360 | mips16_opcodes[i].name, retval); | |
2361 | do | |
2362 | { | |
2363 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
2364 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
2365 | != mips16_opcodes[i].match)) | |
2366 | { | |
2367 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
2368 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
2369 | broken = 1; | |
2370 | } | |
1e915849 RS |
2371 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2372 | { | |
2373 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
2374 | mips16_nop_insn.fixed_p = 1; | |
2375 | } | |
252b5132 RH |
2376 | ++i; |
2377 | } | |
2378 | while (i < bfd_mips16_num_opcodes | |
2379 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
2380 | } | |
2381 | ||
df58fc94 RS |
2382 | micromips_op_hash = hash_new (); |
2383 | ||
2384 | i = 0; | |
2385 | while (i < bfd_micromips_num_opcodes) | |
2386 | { | |
2387 | const char *name = micromips_opcodes[i].name; | |
2388 | ||
2389 | retval = hash_insert (micromips_op_hash, name, | |
2390 | (void *) µmips_opcodes[i]); | |
2391 | if (retval != NULL) | |
2392 | as_fatal (_("internal: can't hash `%s': %s"), | |
2393 | micromips_opcodes[i].name, retval); | |
2394 | do | |
2395 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
2396 | { | |
2397 | struct mips_cl_insn *micromips_nop_insn; | |
2398 | ||
2399 | if (!validate_micromips_insn (µmips_opcodes[i])) | |
2400 | broken = 1; | |
2401 | ||
2402 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
2403 | micromips_nop_insn = µmips_nop16_insn; | |
2404 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
2405 | micromips_nop_insn = µmips_nop32_insn; | |
2406 | else | |
2407 | continue; | |
2408 | ||
2409 | if (micromips_nop_insn->insn_mo == NULL | |
2410 | && strcmp (name, "nop") == 0) | |
2411 | { | |
2412 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
2413 | micromips_nop_insn->fixed_p = 1; | |
2414 | } | |
2415 | } | |
2416 | while (++i < bfd_micromips_num_opcodes | |
2417 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
2418 | } | |
2419 | ||
252b5132 RH |
2420 | if (broken) |
2421 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2422 | ||
2423 | /* We add all the general register names to the symbol table. This | |
2424 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
2425 | for (i = 0; reg_names[i].name; i++) |
2426 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 2427 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
2428 | &zero_address_frag)); |
2429 | if (HAVE_NEWABI) | |
2430 | for (i = 0; reg_names_n32n64[i].name; i++) | |
2431 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 2432 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 2433 | &zero_address_frag)); |
707bfff6 TS |
2434 | else |
2435 | for (i = 0; reg_names_o32[i].name; i++) | |
2436 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 2437 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 2438 | &zero_address_frag)); |
6047c971 | 2439 | |
7d10b47d | 2440 | mips_no_prev_insn (); |
252b5132 RH |
2441 | |
2442 | mips_gprmask = 0; | |
2443 | mips_cprmask[0] = 0; | |
2444 | mips_cprmask[1] = 0; | |
2445 | mips_cprmask[2] = 0; | |
2446 | mips_cprmask[3] = 0; | |
2447 | ||
2448 | /* set the default alignment for the text section (2**2) */ | |
2449 | record_alignment (text_section, 2); | |
2450 | ||
4d0d148d | 2451 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2452 | |
707bfff6 | 2453 | #ifdef OBJ_ELF |
f43abd2b | 2454 | if (IS_ELF) |
252b5132 | 2455 | { |
0a44bf69 RS |
2456 | /* On a native system other than VxWorks, sections must be aligned |
2457 | to 16 byte boundaries. When configured for an embedded ELF | |
2458 | target, we don't bother. */ | |
c41e87e3 CF |
2459 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
2460 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
2461 | { |
2462 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2463 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2464 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2465 | } | |
2466 | ||
2467 | /* Create a .reginfo section for register masks and a .mdebug | |
2468 | section for debugging information. */ | |
2469 | { | |
2470 | segT seg; | |
2471 | subsegT subseg; | |
2472 | flagword flags; | |
2473 | segT sec; | |
2474 | ||
2475 | seg = now_seg; | |
2476 | subseg = now_subseg; | |
2477 | ||
2478 | /* The ABI says this section should be loaded so that the | |
2479 | running program can access it. However, we don't load it | |
2480 | if we are configured for an embedded target */ | |
2481 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2482 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2483 | flags |= SEC_ALLOC | SEC_LOAD; |
2484 | ||
316f5878 | 2485 | if (mips_abi != N64_ABI) |
252b5132 RH |
2486 | { |
2487 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2488 | ||
195325d2 TS |
2489 | bfd_set_section_flags (stdoutput, sec, flags); |
2490 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2491 | |
252b5132 | 2492 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2493 | } |
2494 | else | |
2495 | { | |
2496 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2497 | .reginfo section. */ | |
2498 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2499 | bfd_set_section_flags (stdoutput, sec, flags); |
2500 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2501 | |
252b5132 RH |
2502 | /* Set up the option header. */ |
2503 | { | |
2504 | Elf_Internal_Options opthdr; | |
2505 | char *f; | |
2506 | ||
2507 | opthdr.kind = ODK_REGINFO; | |
2508 | opthdr.size = (sizeof (Elf_External_Options) | |
2509 | + sizeof (Elf64_External_RegInfo)); | |
2510 | opthdr.section = 0; | |
2511 | opthdr.info = 0; | |
2512 | f = frag_more (sizeof (Elf_External_Options)); | |
2513 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2514 | (Elf_External_Options *) f); | |
2515 | ||
2516 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2517 | } | |
252b5132 RH |
2518 | } |
2519 | ||
2520 | if (ECOFF_DEBUGGING) | |
2521 | { | |
2522 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2523 | (void) bfd_set_section_flags (stdoutput, sec, | |
2524 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2525 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2526 | } | |
f43abd2b | 2527 | else if (mips_flag_pdr) |
ecb4347a DJ |
2528 | { |
2529 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2530 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2531 | SEC_READONLY | SEC_RELOC | |
2532 | | SEC_DEBUGGING); | |
2533 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2534 | } | |
252b5132 RH |
2535 | |
2536 | subseg_set (seg, subseg); | |
2537 | } | |
2538 | } | |
707bfff6 | 2539 | #endif /* OBJ_ELF */ |
252b5132 RH |
2540 | |
2541 | if (! ECOFF_DEBUGGING) | |
2542 | md_obj_begin (); | |
71400594 RS |
2543 | |
2544 | if (mips_fix_vr4120) | |
2545 | init_vr4120_conflicts (); | |
252b5132 RH |
2546 | } |
2547 | ||
2548 | void | |
17a2f251 | 2549 | md_mips_end (void) |
252b5132 | 2550 | { |
02b1ab82 | 2551 | mips_emit_delays (); |
252b5132 RH |
2552 | if (! ECOFF_DEBUGGING) |
2553 | md_obj_end (); | |
2554 | } | |
2555 | ||
2556 | void | |
17a2f251 | 2557 | md_assemble (char *str) |
252b5132 RH |
2558 | { |
2559 | struct mips_cl_insn insn; | |
f6688943 TS |
2560 | bfd_reloc_code_real_type unused_reloc[3] |
2561 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2562 | |
2563 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2564 | imm2_expr.X_op = O_absent; |
252b5132 | 2565 | offset_expr.X_op = O_absent; |
f6688943 TS |
2566 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2567 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2568 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2569 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2570 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2571 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2572 | |
2573 | if (mips_opts.mips16) | |
2574 | mips16_ip (str, &insn); | |
2575 | else | |
2576 | { | |
2577 | mips_ip (str, &insn); | |
beae10d5 KH |
2578 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2579 | str, insn.insn_opcode)); | |
252b5132 RH |
2580 | } |
2581 | ||
2582 | if (insn_error) | |
2583 | { | |
2584 | as_bad ("%s `%s'", insn_error, str); | |
2585 | return; | |
2586 | } | |
2587 | ||
2588 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
2589 | { | |
584892a6 | 2590 | macro_start (); |
252b5132 RH |
2591 | if (mips_opts.mips16) |
2592 | mips16_macro (&insn); | |
2593 | else | |
2594 | macro (&insn); | |
584892a6 | 2595 | macro_end (); |
252b5132 RH |
2596 | } |
2597 | else | |
2598 | { | |
2599 | if (imm_expr.X_op != O_absent) | |
df58fc94 | 2600 | append_insn (&insn, &imm_expr, imm_reloc, FALSE); |
252b5132 | 2601 | else if (offset_expr.X_op != O_absent) |
df58fc94 | 2602 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 2603 | else |
df58fc94 | 2604 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 RH |
2605 | } |
2606 | } | |
2607 | ||
738e5348 RS |
2608 | /* Convenience functions for abstracting away the differences between |
2609 | MIPS16 and non-MIPS16 relocations. */ | |
2610 | ||
2611 | static inline bfd_boolean | |
2612 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2613 | { | |
2614 | switch (reloc) | |
2615 | { | |
2616 | case BFD_RELOC_MIPS16_JMP: | |
2617 | case BFD_RELOC_MIPS16_GPREL: | |
2618 | case BFD_RELOC_MIPS16_GOT16: | |
2619 | case BFD_RELOC_MIPS16_CALL16: | |
2620 | case BFD_RELOC_MIPS16_HI16_S: | |
2621 | case BFD_RELOC_MIPS16_HI16: | |
2622 | case BFD_RELOC_MIPS16_LO16: | |
2623 | return TRUE; | |
2624 | ||
2625 | default: | |
2626 | return FALSE; | |
2627 | } | |
2628 | } | |
2629 | ||
df58fc94 RS |
2630 | static inline bfd_boolean |
2631 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
2632 | { | |
2633 | switch (reloc) | |
2634 | { | |
2635 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
2636 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
2637 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
2638 | case BFD_RELOC_MICROMIPS_GPREL16: | |
2639 | case BFD_RELOC_MICROMIPS_JMP: | |
2640 | case BFD_RELOC_MICROMIPS_HI16: | |
2641 | case BFD_RELOC_MICROMIPS_HI16_S: | |
2642 | case BFD_RELOC_MICROMIPS_LO16: | |
2643 | case BFD_RELOC_MICROMIPS_LITERAL: | |
2644 | case BFD_RELOC_MICROMIPS_GOT16: | |
2645 | case BFD_RELOC_MICROMIPS_CALL16: | |
2646 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
2647 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
2648 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
2649 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
2650 | case BFD_RELOC_MICROMIPS_SUB: | |
2651 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
2652 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
2653 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
2654 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
2655 | case BFD_RELOC_MICROMIPS_HIGHER: | |
2656 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
2657 | case BFD_RELOC_MICROMIPS_JALR: | |
2658 | return TRUE; | |
2659 | ||
2660 | default: | |
2661 | return FALSE; | |
2662 | } | |
2663 | } | |
2664 | ||
2309ddf2 MR |
2665 | static inline bfd_boolean |
2666 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
2667 | { | |
2668 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
2669 | } | |
2670 | ||
738e5348 RS |
2671 | static inline bfd_boolean |
2672 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2673 | { | |
2309ddf2 | 2674 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 2675 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
2676 | } |
2677 | ||
2678 | static inline bfd_boolean | |
2679 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2680 | { | |
2309ddf2 | 2681 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 2682 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
2683 | } |
2684 | ||
2685 | static inline bfd_boolean | |
2686 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2687 | { | |
2309ddf2 | 2688 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
2689 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
2690 | } | |
2691 | ||
df58fc94 RS |
2692 | static inline bfd_boolean |
2693 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
2694 | { | |
2309ddf2 | 2695 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
2696 | } |
2697 | ||
5919d012 | 2698 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2699 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2700 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2701 | |
2702 | static inline bfd_boolean | |
17a2f251 | 2703 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2704 | { |
3b91255e | 2705 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2706 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2707 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2708 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2709 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2710 | } | |
2711 | ||
2712 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2713 | reloc_needs_lo_p. */ | |
2714 | ||
2715 | static inline bfd_reloc_code_real_type | |
2716 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2717 | { | |
df58fc94 RS |
2718 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
2719 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
2720 | : BFD_RELOC_LO16)); | |
5919d012 RS |
2721 | } |
2722 | ||
2723 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2724 | relocation. */ | |
2725 | ||
2726 | static inline bfd_boolean | |
17a2f251 | 2727 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2728 | { |
2729 | return (fixp->fx_next != NULL | |
738e5348 | 2730 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2731 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2732 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2733 | } | |
2734 | ||
252b5132 RH |
2735 | /* This function returns true if modifying a register requires a |
2736 | delay. */ | |
2737 | ||
2738 | static int | |
17a2f251 | 2739 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2740 | { |
2741 | unsigned long prev_pinfo; | |
2742 | ||
47e39b9d | 2743 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2744 | if (! mips_opts.noreorder |
81912461 ILT |
2745 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2746 | && ! gpr_interlocks) | |
2747 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2748 | && ! cop_interlocks))) | |
252b5132 | 2749 | { |
81912461 ILT |
2750 | /* A load from a coprocessor or from memory. All load delays |
2751 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2752 | /* Itbl support may require additional care here. */ |
252b5132 | 2753 | know (prev_pinfo & INSN_WRITE_GPR_T); |
df58fc94 | 2754 | if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0])) |
252b5132 RH |
2755 | return 1; |
2756 | } | |
2757 | ||
2758 | return 0; | |
2759 | } | |
2760 | ||
404a8071 RS |
2761 | /* Move all labels in insn_labels to the current insertion point. */ |
2762 | ||
2763 | static void | |
2764 | mips_move_labels (void) | |
2765 | { | |
a8dbcb85 | 2766 | segment_info_type *si = seg_info (now_seg); |
404a8071 RS |
2767 | struct insn_label_list *l; |
2768 | valueT val; | |
2769 | ||
a8dbcb85 | 2770 | for (l = si->label_list; l != NULL; l = l->next) |
404a8071 | 2771 | { |
9c2799c2 | 2772 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
2773 | symbol_set_frag (l->label, frag_now); |
2774 | val = (valueT) frag_now_fix (); | |
df58fc94 RS |
2775 | /* MIPS16/microMIPS text labels are stored as odd. */ |
2776 | if (HAVE_CODE_COMPRESSION) | |
404a8071 RS |
2777 | ++val; |
2778 | S_SET_VALUE (l->label, val); | |
2779 | } | |
2780 | } | |
2781 | ||
5f0fe04b TS |
2782 | static bfd_boolean |
2783 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2784 | { | |
2785 | bfd_boolean linkonce = FALSE; | |
2786 | segT symseg = S_GET_SEGMENT (sym); | |
2787 | ||
2788 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2789 | { | |
2790 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2791 | linkonce = TRUE; | |
2792 | #ifdef OBJ_ELF | |
2793 | /* The GNU toolchain uses an extension for ELF: a section | |
2794 | beginning with the magic string .gnu.linkonce is a | |
2795 | linkonce section. */ | |
2796 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2797 | sizeof ".gnu.linkonce" - 1) == 0) | |
2798 | linkonce = TRUE; | |
2799 | #endif | |
2800 | } | |
2801 | return linkonce; | |
2802 | } | |
2803 | ||
df58fc94 RS |
2804 | /* Mark instruction labels in MIPS16/microMIPS mode. This permits the |
2805 | linker to handle them specially, such as generating jalx instructions | |
2806 | when needed. We also make them odd for the duration of the assembly, | |
2807 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
2808 | in the adjust_symtab routine, while leaving them marked. This is |
2809 | convenient for the debugger and the disassembler. The linker knows | |
2810 | to make them odd again. */ | |
2811 | ||
2812 | static void | |
df58fc94 | 2813 | mips_compressed_mark_labels (void) |
252b5132 | 2814 | { |
a8dbcb85 TS |
2815 | segment_info_type *si = seg_info (now_seg); |
2816 | struct insn_label_list *l; | |
252b5132 | 2817 | |
df58fc94 | 2818 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 TS |
2819 | |
2820 | for (l = si->label_list; l != NULL; l = l->next) | |
2821 | { | |
2822 | symbolS *label = l->label; | |
2823 | ||
2824 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
f43abd2b | 2825 | if (IS_ELF) |
df58fc94 RS |
2826 | { |
2827 | if (mips_opts.mips16) | |
2828 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
2829 | else | |
2830 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
2831 | } | |
252b5132 | 2832 | #endif |
5f0fe04b TS |
2833 | if ((S_GET_VALUE (label) & 1) == 0 |
2834 | /* Don't adjust the address if the label is global or weak, or | |
2835 | in a link-once section, since we'll be emitting symbol reloc | |
2836 | references to it which will be patched up by the linker, and | |
df58fc94 | 2837 | the final value of the symbol may or may not be MIPS16/microMIPS. */ |
5f0fe04b TS |
2838 | && ! S_IS_WEAK (label) |
2839 | && ! S_IS_EXTERNAL (label) | |
2840 | && ! s_is_linkonce (label, now_seg)) | |
a8dbcb85 | 2841 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); |
252b5132 RH |
2842 | } |
2843 | } | |
2844 | ||
4d7206a2 RS |
2845 | /* End the current frag. Make it a variant frag and record the |
2846 | relaxation info. */ | |
2847 | ||
2848 | static void | |
2849 | relax_close_frag (void) | |
2850 | { | |
584892a6 | 2851 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2852 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2853 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2854 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2855 | ||
2856 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2857 | mips_relax.first_fixup = 0; | |
2858 | } | |
2859 | ||
2860 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2861 | See the comment above RELAX_ENCODE for more details. */ | |
2862 | ||
2863 | static void | |
2864 | relax_start (symbolS *symbol) | |
2865 | { | |
9c2799c2 | 2866 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
2867 | mips_relax.sequence = 1; |
2868 | mips_relax.symbol = symbol; | |
2869 | } | |
2870 | ||
2871 | /* Start generating the second version of a relaxable sequence. | |
2872 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2873 | |
2874 | static void | |
4d7206a2 RS |
2875 | relax_switch (void) |
2876 | { | |
9c2799c2 | 2877 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
2878 | mips_relax.sequence = 2; |
2879 | } | |
2880 | ||
2881 | /* End the current relaxable sequence. */ | |
2882 | ||
2883 | static void | |
2884 | relax_end (void) | |
2885 | { | |
9c2799c2 | 2886 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
2887 | relax_close_frag (); |
2888 | mips_relax.sequence = 0; | |
2889 | } | |
2890 | ||
2309ddf2 | 2891 | /* Return the mask of core registers that IP reads or writes. */ |
df58fc94 RS |
2892 | |
2893 | static unsigned int | |
2894 | gpr_mod_mask (const struct mips_cl_insn *ip) | |
2895 | { | |
2309ddf2 | 2896 | unsigned long pinfo2; |
df58fc94 RS |
2897 | unsigned int mask; |
2898 | ||
2899 | mask = 0; | |
df58fc94 RS |
2900 | pinfo2 = ip->insn_mo->pinfo2; |
2901 | if (mips_opts.micromips) | |
2902 | { | |
2903 | if (pinfo2 & INSN2_MOD_GPR_MB) | |
2904 | mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)]; | |
2905 | if (pinfo2 & INSN2_MOD_GPR_MC) | |
2906 | mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)]; | |
2907 | if (pinfo2 & INSN2_MOD_GPR_MD) | |
2908 | mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)]; | |
2909 | if (pinfo2 & INSN2_MOD_GPR_ME) | |
2910 | mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)]; | |
2911 | if (pinfo2 & INSN2_MOD_GPR_MF) | |
2912 | mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)]; | |
2913 | if (pinfo2 & INSN2_MOD_GPR_MG) | |
2914 | mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)]; | |
2915 | if (pinfo2 & INSN2_MOD_GPR_MHI) | |
2916 | { | |
2917 | mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)]; | |
2918 | mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)]; | |
2919 | } | |
2920 | if (pinfo2 & INSN2_MOD_GPR_MJ) | |
2921 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
2922 | if (pinfo2 & INSN2_MOD_GPR_MM) | |
2923 | mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)]; | |
2924 | if (pinfo2 & INSN2_MOD_GPR_MN) | |
2925 | mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)]; | |
2926 | if (pinfo2 & INSN2_MOD_GPR_MP) | |
2927 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
2928 | if (pinfo2 & INSN2_MOD_GPR_MQ) | |
2929 | mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)]; | |
2930 | if (pinfo2 & INSN2_MOD_SP) | |
2931 | mask |= 1 << SP; | |
2932 | } | |
2933 | return mask; | |
2934 | } | |
2935 | ||
4c260379 RS |
2936 | /* Return the mask of core registers that IP reads. */ |
2937 | ||
2938 | static unsigned int | |
2939 | gpr_read_mask (const struct mips_cl_insn *ip) | |
2940 | { | |
2941 | unsigned long pinfo, pinfo2; | |
2942 | unsigned int mask; | |
2943 | ||
df58fc94 | 2944 | mask = gpr_mod_mask (ip); |
4c260379 RS |
2945 | pinfo = ip->insn_mo->pinfo; |
2946 | pinfo2 = ip->insn_mo->pinfo2; | |
2947 | if (mips_opts.mips16) | |
2948 | { | |
2949 | if (pinfo & MIPS16_INSN_READ_X) | |
2950 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
2951 | if (pinfo & MIPS16_INSN_READ_Y) | |
2952 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
2953 | if (pinfo & MIPS16_INSN_READ_T) | |
2954 | mask |= 1 << TREG; | |
2955 | if (pinfo & MIPS16_INSN_READ_SP) | |
2956 | mask |= 1 << SP; | |
2957 | if (pinfo & MIPS16_INSN_READ_31) | |
2958 | mask |= 1 << RA; | |
2959 | if (pinfo & MIPS16_INSN_READ_Z) | |
2960 | mask |= 1 << (mips16_to_32_reg_map | |
2961 | [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]); | |
2962 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2963 | mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); | |
2964 | } | |
2965 | else | |
2966 | { | |
2967 | if (pinfo2 & INSN2_READ_GPR_D) | |
2309ddf2 | 2968 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 2969 | if (pinfo & INSN_READ_GPR_T) |
2309ddf2 | 2970 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
4c260379 | 2971 | if (pinfo & INSN_READ_GPR_S) |
2309ddf2 MR |
2972 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
2973 | if (pinfo2 & INSN2_READ_GP) | |
2974 | mask |= 1 << GP; | |
2975 | if (pinfo2 & INSN2_READ_GPR_31) | |
2976 | mask |= 1 << RA; | |
4c260379 | 2977 | if (pinfo2 & INSN2_READ_GPR_Z) |
2309ddf2 | 2978 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 2979 | } |
fe35f09f RS |
2980 | /* Don't include register 0. */ |
2981 | return mask & ~1; | |
4c260379 RS |
2982 | } |
2983 | ||
2984 | /* Return the mask of core registers that IP writes. */ | |
2985 | ||
2986 | static unsigned int | |
2987 | gpr_write_mask (const struct mips_cl_insn *ip) | |
2988 | { | |
2989 | unsigned long pinfo, pinfo2; | |
2990 | unsigned int mask; | |
2991 | ||
df58fc94 | 2992 | mask = gpr_mod_mask (ip); |
4c260379 RS |
2993 | pinfo = ip->insn_mo->pinfo; |
2994 | pinfo2 = ip->insn_mo->pinfo2; | |
2995 | if (mips_opts.mips16) | |
2996 | { | |
2997 | if (pinfo & MIPS16_INSN_WRITE_X) | |
2998 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
2999 | if (pinfo & MIPS16_INSN_WRITE_Y) | |
3000 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3001 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
3002 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)]; | |
3003 | if (pinfo & MIPS16_INSN_WRITE_T) | |
3004 | mask |= 1 << TREG; | |
3005 | if (pinfo & MIPS16_INSN_WRITE_SP) | |
3006 | mask |= 1 << SP; | |
3007 | if (pinfo & MIPS16_INSN_WRITE_31) | |
3008 | mask |= 1 << RA; | |
3009 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3010 | mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3011 | } | |
3012 | else | |
3013 | { | |
3014 | if (pinfo & INSN_WRITE_GPR_D) | |
df58fc94 | 3015 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3016 | if (pinfo & INSN_WRITE_GPR_T) |
df58fc94 | 3017 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
2309ddf2 MR |
3018 | if (pinfo2 & INSN2_WRITE_GPR_S) |
3019 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
4c260379 RS |
3020 | if (pinfo & INSN_WRITE_GPR_31) |
3021 | mask |= 1 << RA; | |
3022 | if (pinfo2 & INSN2_WRITE_GPR_Z) | |
df58fc94 | 3023 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3024 | } |
fe35f09f RS |
3025 | /* Don't include register 0. */ |
3026 | return mask & ~1; | |
4c260379 RS |
3027 | } |
3028 | ||
3029 | /* Return the mask of floating-point registers that IP reads. */ | |
3030 | ||
3031 | static unsigned int | |
3032 | fpr_read_mask (const struct mips_cl_insn *ip) | |
3033 | { | |
3034 | unsigned long pinfo, pinfo2; | |
3035 | unsigned int mask; | |
3036 | ||
3037 | mask = 0; | |
3038 | pinfo = ip->insn_mo->pinfo; | |
3039 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3040 | if (!mips_opts.mips16) |
df58fc94 RS |
3041 | { |
3042 | if (pinfo2 & INSN2_READ_FPR_D) | |
2309ddf2 | 3043 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3044 | if (pinfo & INSN_READ_FPR_S) |
df58fc94 | 3045 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3046 | if (pinfo & INSN_READ_FPR_T) |
df58fc94 | 3047 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3048 | if (pinfo & INSN_READ_FPR_R) |
df58fc94 | 3049 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip); |
4c260379 | 3050 | if (pinfo2 & INSN2_READ_FPR_Z) |
df58fc94 | 3051 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3052 | } |
3053 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3054 | (This is overly pessimistic for things like cvt.d.s.) */ | |
3055 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3056 | mask |= mask << 1; | |
3057 | return mask; | |
3058 | } | |
3059 | ||
3060 | /* Return the mask of floating-point registers that IP writes. */ | |
3061 | ||
3062 | static unsigned int | |
3063 | fpr_write_mask (const struct mips_cl_insn *ip) | |
3064 | { | |
3065 | unsigned long pinfo, pinfo2; | |
3066 | unsigned int mask; | |
3067 | ||
3068 | mask = 0; | |
3069 | pinfo = ip->insn_mo->pinfo; | |
3070 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3071 | if (!mips_opts.mips16) |
4c260379 RS |
3072 | { |
3073 | if (pinfo & INSN_WRITE_FPR_D) | |
df58fc94 | 3074 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3075 | if (pinfo & INSN_WRITE_FPR_S) |
df58fc94 | 3076 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3077 | if (pinfo & INSN_WRITE_FPR_T) |
df58fc94 | 3078 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3079 | if (pinfo2 & INSN2_WRITE_FPR_Z) |
df58fc94 | 3080 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3081 | } |
3082 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3083 | (This is overly pessimistic for things like cvt.s.d.) */ | |
3084 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3085 | mask |= mask << 1; | |
3086 | return mask; | |
3087 | } | |
3088 | ||
71400594 RS |
3089 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
3090 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
3091 | by VR4120 errata. */ | |
4d7206a2 | 3092 | |
71400594 RS |
3093 | static unsigned int |
3094 | classify_vr4120_insn (const char *name) | |
252b5132 | 3095 | { |
71400594 RS |
3096 | if (strncmp (name, "macc", 4) == 0) |
3097 | return FIX_VR4120_MACC; | |
3098 | if (strncmp (name, "dmacc", 5) == 0) | |
3099 | return FIX_VR4120_DMACC; | |
3100 | if (strncmp (name, "mult", 4) == 0) | |
3101 | return FIX_VR4120_MULT; | |
3102 | if (strncmp (name, "dmult", 5) == 0) | |
3103 | return FIX_VR4120_DMULT; | |
3104 | if (strstr (name, "div")) | |
3105 | return FIX_VR4120_DIV; | |
3106 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
3107 | return FIX_VR4120_MTHILO; | |
3108 | return NUM_FIX_VR4120_CLASSES; | |
3109 | } | |
252b5132 | 3110 | |
ff239038 CM |
3111 | #define INSN_ERET 0x42000018 |
3112 | #define INSN_DERET 0x4200001f | |
3113 | ||
71400594 RS |
3114 | /* Return the number of instructions that must separate INSN1 and INSN2, |
3115 | where INSN1 is the earlier instruction. Return the worst-case value | |
3116 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 3117 | |
71400594 RS |
3118 | static unsigned int |
3119 | insns_between (const struct mips_cl_insn *insn1, | |
3120 | const struct mips_cl_insn *insn2) | |
3121 | { | |
3122 | unsigned long pinfo1, pinfo2; | |
4c260379 | 3123 | unsigned int mask; |
71400594 RS |
3124 | |
3125 | /* This function needs to know which pinfo flags are set for INSN2 | |
3126 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
4c260379 RS |
3127 | the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2 |
3128 | will have every flag set and INSN2_USES_GPR will always return true. */ | |
71400594 RS |
3129 | pinfo1 = insn1->insn_mo->pinfo; |
3130 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 3131 | |
4c260379 RS |
3132 | #define INSN2_USES_GPR(REG) \ |
3133 | (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0) | |
71400594 RS |
3134 | |
3135 | /* For most targets, write-after-read dependencies on the HI and LO | |
3136 | registers must be separated by at least two instructions. */ | |
3137 | if (!hilo_interlocks) | |
252b5132 | 3138 | { |
71400594 RS |
3139 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
3140 | return 2; | |
3141 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
3142 | return 2; | |
3143 | } | |
3144 | ||
3145 | /* If we're working around r7000 errata, there must be two instructions | |
3146 | between an mfhi or mflo and any instruction that uses the result. */ | |
3147 | if (mips_7000_hilo_fix | |
df58fc94 | 3148 | && !mips_opts.micromips |
71400594 | 3149 | && MF_HILO_INSN (pinfo1) |
df58fc94 | 3150 | && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1))) |
71400594 RS |
3151 | return 2; |
3152 | ||
ff239038 CM |
3153 | /* If we're working around 24K errata, one instruction is required |
3154 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 3155 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
3156 | { |
3157 | if (insn1->insn_opcode == INSN_ERET | |
3158 | || insn1->insn_opcode == INSN_DERET) | |
3159 | { | |
3160 | if (insn2 == NULL | |
3161 | || insn2->insn_opcode == INSN_ERET | |
3162 | || insn2->insn_opcode == INSN_DERET | |
3163 | || (insn2->insn_mo->pinfo | |
3164 | & (INSN_UNCOND_BRANCH_DELAY | |
3165 | | INSN_COND_BRANCH_DELAY | |
3166 | | INSN_COND_BRANCH_LIKELY)) != 0) | |
3167 | return 1; | |
3168 | } | |
3169 | } | |
3170 | ||
71400594 RS |
3171 | /* If working around VR4120 errata, check for combinations that need |
3172 | a single intervening instruction. */ | |
df58fc94 | 3173 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
3174 | { |
3175 | unsigned int class1, class2; | |
252b5132 | 3176 | |
71400594 RS |
3177 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
3178 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 3179 | { |
71400594 RS |
3180 | if (insn2 == NULL) |
3181 | return 1; | |
3182 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
3183 | if (vr4120_conflicts[class1] & (1 << class2)) | |
3184 | return 1; | |
252b5132 | 3185 | } |
71400594 RS |
3186 | } |
3187 | ||
df58fc94 | 3188 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
3189 | { |
3190 | /* Check for GPR or coprocessor load delays. All such delays | |
3191 | are on the RT register. */ | |
3192 | /* Itbl support may require additional care here. */ | |
3193 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
3194 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 3195 | { |
71400594 | 3196 | know (pinfo1 & INSN_WRITE_GPR_T); |
df58fc94 | 3197 | if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1))) |
71400594 RS |
3198 | return 1; |
3199 | } | |
3200 | ||
3201 | /* Check for generic coprocessor hazards. | |
3202 | ||
3203 | This case is not handled very well. There is no special | |
3204 | knowledge of CP0 handling, and the coprocessors other than | |
3205 | the floating point unit are not distinguished at all. */ | |
3206 | /* Itbl support may require additional care here. FIXME! | |
3207 | Need to modify this to include knowledge about | |
3208 | user specified delays! */ | |
3209 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
3210 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
3211 | { | |
3212 | /* Handle cases where INSN1 writes to a known general coprocessor | |
3213 | register. There must be a one instruction delay before INSN2 | |
3214 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
3215 | mask = fpr_write_mask (insn1); |
3216 | if (mask != 0) | |
252b5132 | 3217 | { |
4c260379 | 3218 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 3219 | return 1; |
252b5132 RH |
3220 | } |
3221 | else | |
3222 | { | |
71400594 RS |
3223 | /* Read-after-write dependencies on the control registers |
3224 | require a two-instruction gap. */ | |
3225 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
3226 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3227 | return 2; | |
3228 | ||
3229 | /* We don't know exactly what INSN1 does. If INSN2 is | |
3230 | also a coprocessor instruction, assume there must be | |
3231 | a one instruction gap. */ | |
3232 | if (pinfo2 & INSN_COP) | |
3233 | return 1; | |
252b5132 RH |
3234 | } |
3235 | } | |
6b76fefe | 3236 | |
71400594 RS |
3237 | /* Check for read-after-write dependencies on the coprocessor |
3238 | control registers in cases where INSN1 does not need a general | |
3239 | coprocessor delay. This means that INSN1 is a floating point | |
3240 | comparison instruction. */ | |
3241 | /* Itbl support may require additional care here. */ | |
3242 | else if (!cop_interlocks | |
3243 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
3244 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3245 | return 1; | |
3246 | } | |
6b76fefe | 3247 | |
4c260379 | 3248 | #undef INSN2_USES_GPR |
6b76fefe | 3249 | |
71400594 RS |
3250 | return 0; |
3251 | } | |
6b76fefe | 3252 | |
7d8e00cf RS |
3253 | /* Return the number of nops that would be needed to work around the |
3254 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
3255 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
3256 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
3257 | |
3258 | static int | |
932d1a1b | 3259 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
3260 | const struct mips_cl_insn *insn) |
3261 | { | |
4c260379 RS |
3262 | int i, j; |
3263 | unsigned int mask; | |
7d8e00cf RS |
3264 | |
3265 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
3266 | are not affected by the errata. */ | |
3267 | if (insn != 0 | |
3268 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
3269 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
3270 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
3271 | return 0; | |
3272 | ||
3273 | /* Search for the first MFLO or MFHI. */ | |
3274 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 3275 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
3276 | { |
3277 | /* Extract the destination register. */ | |
2309ddf2 | 3278 | gas_assert (!mips_opts.micromips); |
4c260379 | 3279 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
3280 | |
3281 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 3282 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
3283 | return 0; |
3284 | ||
3285 | /* ...or if any of the intervening instructions do. */ | |
3286 | for (j = 0; j < i; j++) | |
4c260379 | 3287 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
3288 | return 0; |
3289 | ||
932d1a1b RS |
3290 | if (i >= ignore) |
3291 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
3292 | } |
3293 | return 0; | |
3294 | } | |
3295 | ||
15be625d CM |
3296 | #define BASE_REG_EQ(INSN1, INSN2) \ |
3297 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
3298 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
3299 | ||
3300 | /* Return the minimum alignment for this store instruction. */ | |
3301 | ||
3302 | static int | |
3303 | fix_24k_align_to (const struct mips_opcode *mo) | |
3304 | { | |
3305 | if (strcmp (mo->name, "sh") == 0) | |
3306 | return 2; | |
3307 | ||
3308 | if (strcmp (mo->name, "swc1") == 0 | |
3309 | || strcmp (mo->name, "swc2") == 0 | |
3310 | || strcmp (mo->name, "sw") == 0 | |
3311 | || strcmp (mo->name, "sc") == 0 | |
3312 | || strcmp (mo->name, "s.s") == 0) | |
3313 | return 4; | |
3314 | ||
3315 | if (strcmp (mo->name, "sdc1") == 0 | |
3316 | || strcmp (mo->name, "sdc2") == 0 | |
3317 | || strcmp (mo->name, "s.d") == 0) | |
3318 | return 8; | |
3319 | ||
3320 | /* sb, swl, swr */ | |
3321 | return 1; | |
3322 | } | |
3323 | ||
3324 | struct fix_24k_store_info | |
3325 | { | |
3326 | /* Immediate offset, if any, for this store instruction. */ | |
3327 | short off; | |
3328 | /* Alignment required by this store instruction. */ | |
3329 | int align_to; | |
3330 | /* True for register offsets. */ | |
3331 | int register_offset; | |
3332 | }; | |
3333 | ||
3334 | /* Comparison function used by qsort. */ | |
3335 | ||
3336 | static int | |
3337 | fix_24k_sort (const void *a, const void *b) | |
3338 | { | |
3339 | const struct fix_24k_store_info *pos1 = a; | |
3340 | const struct fix_24k_store_info *pos2 = b; | |
3341 | ||
3342 | return (pos1->off - pos2->off); | |
3343 | } | |
3344 | ||
3345 | /* INSN is a store instruction. Try to record the store information | |
3346 | in STINFO. Return false if the information isn't known. */ | |
3347 | ||
3348 | static bfd_boolean | |
3349 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 3350 | const struct mips_cl_insn *insn) |
15be625d CM |
3351 | { |
3352 | /* The instruction must have a known offset. */ | |
3353 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
3354 | return FALSE; | |
3355 | ||
3356 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
3357 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
3358 | return TRUE; | |
3359 | } | |
3360 | ||
932d1a1b RS |
3361 | /* Return the number of nops that would be needed to work around the 24k |
3362 | "lost data on stores during refill" errata if instruction INSN | |
3363 | immediately followed the 2 instructions described by HIST. | |
3364 | Ignore hazards that are contained within the first IGNORE | |
3365 | instructions of HIST. | |
3366 | ||
3367 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
3368 | for the data cache refills and store data. The following describes | |
3369 | the scenario where the store data could be lost. | |
3370 | ||
3371 | * A data cache miss, due to either a load or a store, causing fill | |
3372 | data to be supplied by the memory subsystem | |
3373 | * The first three doublewords of fill data are returned and written | |
3374 | into the cache | |
3375 | * A sequence of four stores occurs in consecutive cycles around the | |
3376 | final doubleword of the fill: | |
3377 | * Store A | |
3378 | * Store B | |
3379 | * Store C | |
3380 | * Zero, One or more instructions | |
3381 | * Store D | |
3382 | ||
3383 | The four stores A-D must be to different doublewords of the line that | |
3384 | is being filled. The fourth instruction in the sequence above permits | |
3385 | the fill of the final doubleword to be transferred from the FSB into | |
3386 | the cache. In the sequence above, the stores may be either integer | |
3387 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
3388 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
3389 | different doublewords on the line. If the floating point unit is | |
3390 | running in 1:2 mode, it is not possible to create the sequence above | |
3391 | using only floating point store instructions. | |
15be625d CM |
3392 | |
3393 | In this case, the cache line being filled is incorrectly marked | |
3394 | invalid, thereby losing the data from any store to the line that | |
3395 | occurs between the original miss and the completion of the five | |
3396 | cycle sequence shown above. | |
3397 | ||
932d1a1b | 3398 | The workarounds are: |
15be625d | 3399 | |
932d1a1b RS |
3400 | * Run the data cache in write-through mode. |
3401 | * Insert a non-store instruction between | |
3402 | Store A and Store B or Store B and Store C. */ | |
15be625d CM |
3403 | |
3404 | static int | |
932d1a1b | 3405 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
3406 | const struct mips_cl_insn *insn) |
3407 | { | |
3408 | struct fix_24k_store_info pos[3]; | |
3409 | int align, i, base_offset; | |
3410 | ||
932d1a1b RS |
3411 | if (ignore >= 2) |
3412 | return 0; | |
3413 | ||
ab9794cf RS |
3414 | /* If the previous instruction wasn't a store, there's nothing to |
3415 | worry about. */ | |
15be625d CM |
3416 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
3417 | return 0; | |
3418 | ||
ab9794cf RS |
3419 | /* If the instructions after the previous one are unknown, we have |
3420 | to assume the worst. */ | |
3421 | if (!insn) | |
15be625d CM |
3422 | return 1; |
3423 | ||
ab9794cf RS |
3424 | /* Check whether we are dealing with three consecutive stores. */ |
3425 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
3426 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
3427 | return 0; |
3428 | ||
3429 | /* If we don't know the relationship between the store addresses, | |
3430 | assume the worst. */ | |
ab9794cf | 3431 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
3432 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
3433 | return 1; | |
3434 | ||
3435 | if (!fix_24k_record_store_info (&pos[0], insn) | |
3436 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
3437 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
3438 | return 1; | |
3439 | ||
3440 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
3441 | ||
3442 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
3443 | X bytes and such that the base register + X is known to be aligned | |
3444 | to align bytes. */ | |
3445 | ||
3446 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
3447 | align = 8; | |
3448 | else | |
3449 | { | |
3450 | align = pos[0].align_to; | |
3451 | base_offset = pos[0].off; | |
3452 | for (i = 1; i < 3; i++) | |
3453 | if (align < pos[i].align_to) | |
3454 | { | |
3455 | align = pos[i].align_to; | |
3456 | base_offset = pos[i].off; | |
3457 | } | |
3458 | for (i = 0; i < 3; i++) | |
3459 | pos[i].off -= base_offset; | |
3460 | } | |
3461 | ||
3462 | pos[0].off &= ~align + 1; | |
3463 | pos[1].off &= ~align + 1; | |
3464 | pos[2].off &= ~align + 1; | |
3465 | ||
3466 | /* If any two stores write to the same chunk, they also write to the | |
3467 | same doubleword. The offsets are still sorted at this point. */ | |
3468 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
3469 | return 0; | |
3470 | ||
3471 | /* A range of at least 9 bytes is needed for the stores to be in | |
3472 | non-overlapping doublewords. */ | |
3473 | if (pos[2].off - pos[0].off <= 8) | |
3474 | return 0; | |
3475 | ||
3476 | if (pos[2].off - pos[1].off >= 24 | |
3477 | || pos[1].off - pos[0].off >= 24 | |
3478 | || pos[2].off - pos[0].off >= 32) | |
3479 | return 0; | |
3480 | ||
3481 | return 1; | |
3482 | } | |
3483 | ||
71400594 | 3484 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 3485 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
3486 | where HIST[0] is the most recent instruction. Ignore hazards |
3487 | between INSN and the first IGNORE instructions in HIST. | |
3488 | ||
3489 | If INSN is null, return the worse-case number of nops for any | |
3490 | instruction. */ | |
bdaaa2e1 | 3491 | |
71400594 | 3492 | static int |
932d1a1b | 3493 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3494 | const struct mips_cl_insn *insn) |
3495 | { | |
3496 | int i, nops, tmp_nops; | |
bdaaa2e1 | 3497 | |
71400594 | 3498 | nops = 0; |
932d1a1b | 3499 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 3500 | { |
91d6fa6a | 3501 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
3502 | if (tmp_nops > nops) |
3503 | nops = tmp_nops; | |
3504 | } | |
7d8e00cf | 3505 | |
df58fc94 | 3506 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 3507 | { |
932d1a1b | 3508 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
3509 | if (tmp_nops > nops) |
3510 | nops = tmp_nops; | |
3511 | } | |
3512 | ||
df58fc94 | 3513 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 3514 | { |
932d1a1b | 3515 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
3516 | if (tmp_nops > nops) |
3517 | nops = tmp_nops; | |
3518 | } | |
3519 | ||
71400594 RS |
3520 | return nops; |
3521 | } | |
252b5132 | 3522 | |
71400594 | 3523 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 3524 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
3525 | would be needed after the extended sequence, ignoring hazards |
3526 | in the first IGNORE instructions. */ | |
252b5132 | 3527 | |
71400594 | 3528 | static int |
932d1a1b RS |
3529 | nops_for_sequence (int num_insns, int ignore, |
3530 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
3531 | { |
3532 | va_list args; | |
3533 | struct mips_cl_insn buffer[MAX_NOPS]; | |
3534 | struct mips_cl_insn *cursor; | |
3535 | int nops; | |
3536 | ||
91d6fa6a | 3537 | va_start (args, hist); |
71400594 | 3538 | cursor = buffer + num_insns; |
91d6fa6a | 3539 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
3540 | while (cursor > buffer) |
3541 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
3542 | ||
932d1a1b | 3543 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
3544 | va_end (args); |
3545 | return nops; | |
3546 | } | |
252b5132 | 3547 | |
71400594 RS |
3548 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
3549 | worst-case delay for the branch target. */ | |
252b5132 | 3550 | |
71400594 | 3551 | static int |
932d1a1b | 3552 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3553 | const struct mips_cl_insn *insn) |
3554 | { | |
3555 | int nops, tmp_nops; | |
60b63b72 | 3556 | |
932d1a1b | 3557 | nops = nops_for_insn (ignore, hist, insn); |
71400594 RS |
3558 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY |
3559 | | INSN_COND_BRANCH_DELAY | |
3560 | | INSN_COND_BRANCH_LIKELY)) | |
3561 | { | |
932d1a1b RS |
3562 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
3563 | hist, insn, NOP_INSN); | |
71400594 RS |
3564 | if (tmp_nops > nops) |
3565 | nops = tmp_nops; | |
3566 | } | |
9a2c7088 MR |
3567 | else if (mips_opts.mips16 |
3568 | && (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
3569 | | MIPS16_INSN_COND_BRANCH))) | |
71400594 | 3570 | { |
932d1a1b | 3571 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
3572 | if (tmp_nops > nops) |
3573 | nops = tmp_nops; | |
3574 | } | |
3575 | return nops; | |
3576 | } | |
3577 | ||
c67a084a NC |
3578 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
3579 | ||
3580 | static void | |
3581 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
3582 | { | |
df58fc94 | 3583 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3584 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
3585 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
3586 | } | |
3587 | ||
3588 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
3589 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
3590 | ||
3591 | static void | |
3592 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
3593 | { | |
df58fc94 | 3594 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3595 | if (strcmp (ip->insn_mo->name, "j") == 0 |
3596 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
3597 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
3598 | { | |
3599 | int sreg; | |
3600 | expressionS ep; | |
3601 | ||
3602 | if (! mips_opts.at) | |
3603 | return; | |
3604 | ||
df58fc94 | 3605 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
3606 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
3607 | return; | |
3608 | ||
3609 | ep.X_op = O_constant; | |
3610 | ep.X_add_number = 0xcfff0000; | |
3611 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
3612 | ep.X_add_number = 0xffff; | |
3613 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
3614 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
3615 | } | |
3616 | } | |
3617 | ||
3618 | static void | |
3619 | fix_loongson2f (struct mips_cl_insn * ip) | |
3620 | { | |
3621 | if (mips_fix_loongson2f_nop) | |
3622 | fix_loongson2f_nop (ip); | |
3623 | ||
3624 | if (mips_fix_loongson2f_jump) | |
3625 | fix_loongson2f_jump (ip); | |
3626 | } | |
3627 | ||
a4e06468 RS |
3628 | /* IP is a branch that has a delay slot, and we need to fill it |
3629 | automatically. Return true if we can do that by swapping IP | |
3630 | with the previous instruction. */ | |
3631 | ||
3632 | static bfd_boolean | |
3633 | can_swap_branch_p (struct mips_cl_insn *ip) | |
3634 | { | |
df58fc94 | 3635 | unsigned long pinfo, pinfo2, prev_pinfo; |
a4e06468 RS |
3636 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
3637 | ||
df58fc94 RS |
3638 | /* For microMIPS, disable reordering. */ |
3639 | if (mips_opts.micromips) | |
3640 | return FALSE; | |
3641 | ||
a4e06468 RS |
3642 | /* -O2 and above is required for this optimization. */ |
3643 | if (mips_optimize < 2) | |
3644 | return FALSE; | |
3645 | ||
3646 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
3647 | if (mips_opts.nomove) | |
3648 | return FALSE; | |
3649 | ||
3650 | /* We can't swap if the previous instruction's position is fixed. */ | |
3651 | if (history[0].fixed_p) | |
3652 | return FALSE; | |
3653 | ||
3654 | /* If the previous previous insn was in a .set noreorder, we can't | |
3655 | swap. Actually, the MIPS assembler will swap in this situation. | |
3656 | However, gcc configured -with-gnu-as will generate code like | |
3657 | ||
3658 | .set noreorder | |
3659 | lw $4,XXX | |
3660 | .set reorder | |
3661 | INSN | |
3662 | bne $4,$0,foo | |
3663 | ||
3664 | in which we can not swap the bne and INSN. If gcc is not configured | |
3665 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
3666 | if (history[1].noreorder_p) | |
3667 | return FALSE; | |
3668 | ||
3669 | /* If the previous instruction had a fixup in mips16 mode, we can not | |
3670 | swap. This normally means that the previous instruction was a 4 | |
3671 | byte branch anyhow. */ | |
3672 | if (mips_opts.mips16 && history[0].fixp[0]) | |
3673 | return FALSE; | |
3674 | ||
3675 | /* If the branch is itself the target of a branch, we can not swap. | |
3676 | We cheat on this; all we check for is whether there is a label on | |
3677 | this instruction. If there are any branches to anything other than | |
3678 | a label, users must use .set noreorder. */ | |
3679 | if (seg_info (now_seg)->label_list) | |
3680 | return FALSE; | |
3681 | ||
3682 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 MR |
3683 | branch's one, we cannot do the swap. This does not apply to |
3684 | MIPS16/microMIPS code, which uses variant frags for different | |
3685 | purposes. */ | |
df58fc94 | 3686 | if (!HAVE_CODE_COMPRESSION |
a4e06468 RS |
3687 | && history[0].frag |
3688 | && history[0].frag->fr_type == rs_machine_dependent) | |
3689 | return FALSE; | |
3690 | ||
bcd530a7 RS |
3691 | /* We do not swap with instructions that cannot architecturally |
3692 | be placed in a branch delay slot, such as SYNC or ERET. We | |
3693 | also refrain from swapping with a trap instruction, since it | |
3694 | complicates trap handlers to have the trap instruction be in | |
3695 | a delay slot. */ | |
a4e06468 | 3696 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 3697 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
3698 | return FALSE; |
3699 | ||
3700 | /* Check for conflicts between the branch and the instructions | |
3701 | before the candidate delay slot. */ | |
3702 | if (nops_for_insn (0, history + 1, ip) > 0) | |
3703 | return FALSE; | |
3704 | ||
3705 | /* Check for conflicts between the swapped sequence and the | |
3706 | target of the branch. */ | |
3707 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
3708 | return FALSE; | |
3709 | ||
3710 | /* If the branch reads a register that the previous | |
3711 | instruction sets, we can not swap. */ | |
3712 | gpr_read = gpr_read_mask (ip); | |
3713 | prev_gpr_write = gpr_write_mask (&history[0]); | |
3714 | if (gpr_read & prev_gpr_write) | |
3715 | return FALSE; | |
3716 | ||
3717 | /* If the branch writes a register that the previous | |
3718 | instruction sets, we can not swap. */ | |
3719 | gpr_write = gpr_write_mask (ip); | |
3720 | if (gpr_write & prev_gpr_write) | |
3721 | return FALSE; | |
3722 | ||
3723 | /* If the branch writes a register that the previous | |
3724 | instruction reads, we can not swap. */ | |
3725 | prev_gpr_read = gpr_read_mask (&history[0]); | |
3726 | if (gpr_write & prev_gpr_read) | |
3727 | return FALSE; | |
3728 | ||
3729 | /* If one instruction sets a condition code and the | |
3730 | other one uses a condition code, we can not swap. */ | |
3731 | pinfo = ip->insn_mo->pinfo; | |
3732 | if ((pinfo & INSN_READ_COND_CODE) | |
3733 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3734 | return FALSE; | |
3735 | if ((pinfo & INSN_WRITE_COND_CODE) | |
3736 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3737 | return FALSE; | |
3738 | ||
3739 | /* If the previous instruction uses the PC, we can not swap. */ | |
3740 | if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
3741 | return FALSE; | |
3742 | ||
df58fc94 RS |
3743 | /* If the previous instruction has an incorrect size for a fixed |
3744 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
3745 | pinfo2 = ip->insn_mo->pinfo2; |
3746 | if (mips_opts.micromips | |
3747 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
3748 | && insn_length (history) != 2) | |
3749 | return FALSE; | |
3750 | if (mips_opts.micromips | |
3751 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
3752 | && insn_length (history) != 4) | |
3753 | return FALSE; | |
3754 | ||
a4e06468 RS |
3755 | return TRUE; |
3756 | } | |
3757 | ||
3758 | /* Decide how we should add IP to the instruction stream. */ | |
3759 | ||
3760 | static enum append_method | |
3761 | get_append_method (struct mips_cl_insn *ip) | |
3762 | { | |
3763 | unsigned long pinfo; | |
3764 | ||
3765 | /* The relaxed version of a macro sequence must be inherently | |
3766 | hazard-free. */ | |
3767 | if (mips_relax.sequence == 2) | |
3768 | return APPEND_ADD; | |
3769 | ||
3770 | /* We must not dabble with instructions in a ".set norerorder" block. */ | |
3771 | if (mips_opts.noreorder) | |
3772 | return APPEND_ADD; | |
3773 | ||
3774 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
3775 | pinfo = ip->insn_mo->pinfo; | |
3776 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3777 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
3778 | { | |
3779 | if (can_swap_branch_p (ip)) | |
3780 | return APPEND_SWAP; | |
3781 | ||
3782 | if (mips_opts.mips16 | |
3783 | && ISA_SUPPORTS_MIPS16E | |
3784 | && (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3785 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))) | |
3786 | return APPEND_ADD_COMPACT; | |
3787 | ||
3788 | return APPEND_ADD_WITH_NOP; | |
3789 | } | |
3790 | ||
3791 | /* We don't bother trying to track the target of branches, so there's | |
3792 | nothing we can use to fill a branch-likely slot. */ | |
3793 | if (pinfo & INSN_COND_BRANCH_LIKELY) | |
3794 | return APPEND_ADD_WITH_NOP; | |
3795 | ||
3796 | return APPEND_ADD; | |
3797 | } | |
3798 | ||
ceb94aa5 RS |
3799 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
3800 | Point IP->insn_mo to the new opcode's definition. */ | |
3801 | ||
3802 | static void | |
3803 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
3804 | { | |
3805 | const struct mips_opcode *mo, *end; | |
3806 | ||
3807 | end = &mips16_opcodes[bfd_mips16_num_opcodes]; | |
3808 | for (mo = ip->insn_mo; mo < end; mo++) | |
3809 | if ((ip->insn_opcode & mo->mask) == mo->match) | |
3810 | { | |
3811 | ip->insn_mo = mo; | |
3812 | return; | |
3813 | } | |
3814 | abort (); | |
3815 | } | |
3816 | ||
df58fc94 RS |
3817 | /* For microMIPS macros, we need to generate a local number label |
3818 | as the target of branches. */ | |
3819 | #define MICROMIPS_LABEL_CHAR '\037' | |
3820 | static unsigned long micromips_target_label; | |
3821 | static char micromips_target_name[32]; | |
3822 | ||
3823 | static char * | |
3824 | micromips_label_name (void) | |
3825 | { | |
3826 | char *p = micromips_target_name; | |
3827 | char symbol_name_temporary[24]; | |
3828 | unsigned long l; | |
3829 | int i; | |
3830 | ||
3831 | if (*p) | |
3832 | return p; | |
3833 | ||
3834 | i = 0; | |
3835 | l = micromips_target_label; | |
3836 | #ifdef LOCAL_LABEL_PREFIX | |
3837 | *p++ = LOCAL_LABEL_PREFIX; | |
3838 | #endif | |
3839 | *p++ = 'L'; | |
3840 | *p++ = MICROMIPS_LABEL_CHAR; | |
3841 | do | |
3842 | { | |
3843 | symbol_name_temporary[i++] = l % 10 + '0'; | |
3844 | l /= 10; | |
3845 | } | |
3846 | while (l != 0); | |
3847 | while (i > 0) | |
3848 | *p++ = symbol_name_temporary[--i]; | |
3849 | *p = '\0'; | |
3850 | ||
3851 | return micromips_target_name; | |
3852 | } | |
3853 | ||
3854 | static void | |
3855 | micromips_label_expr (expressionS *label_expr) | |
3856 | { | |
3857 | label_expr->X_op = O_symbol; | |
3858 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
3859 | label_expr->X_add_number = 0; | |
3860 | } | |
3861 | ||
3862 | static void | |
3863 | micromips_label_inc (void) | |
3864 | { | |
3865 | micromips_target_label++; | |
3866 | *micromips_target_name = '\0'; | |
3867 | } | |
3868 | ||
3869 | static void | |
3870 | micromips_add_label (void) | |
3871 | { | |
3872 | symbolS *s; | |
3873 | ||
3874 | s = colon (micromips_label_name ()); | |
3875 | micromips_label_inc (); | |
3876 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
3877 | if (IS_ELF) | |
3878 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); | |
3879 | #endif | |
3880 | } | |
3881 | ||
3882 | /* If assembling microMIPS code, then return the microMIPS reloc | |
3883 | corresponding to the requested one if any. Otherwise return | |
3884 | the reloc unchanged. */ | |
3885 | ||
3886 | static bfd_reloc_code_real_type | |
3887 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
3888 | { | |
3889 | static const bfd_reloc_code_real_type relocs[][2] = | |
3890 | { | |
3891 | /* Keep sorted incrementally by the left-hand key. */ | |
3892 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
3893 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
3894 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
3895 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
3896 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
3897 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
3898 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
3899 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
3900 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
3901 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
3902 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
3903 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
3904 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
3905 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
3906 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
3907 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
3908 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
3909 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
3910 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
3911 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
3912 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
3913 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
3914 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
3915 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
3916 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
3917 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
3918 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
3919 | }; | |
3920 | bfd_reloc_code_real_type r; | |
3921 | size_t i; | |
3922 | ||
3923 | if (!mips_opts.micromips) | |
3924 | return reloc; | |
3925 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
3926 | { | |
3927 | r = relocs[i][0]; | |
3928 | if (r > reloc) | |
3929 | return reloc; | |
3930 | if (r == reloc) | |
3931 | return relocs[i][1]; | |
3932 | } | |
3933 | return reloc; | |
3934 | } | |
3935 | ||
71400594 RS |
3936 | /* Output an instruction. IP is the instruction information. |
3937 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
3938 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
3939 | a macro expansion. */ | |
71400594 RS |
3940 | |
3941 | static void | |
3942 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 3943 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 3944 | { |
df58fc94 | 3945 | unsigned long prev_pinfo, prev_pinfo2, pinfo, pinfo2; |
71400594 | 3946 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 3947 | enum append_method method; |
2309ddf2 | 3948 | bfd_boolean relax32; |
71400594 | 3949 | |
2309ddf2 | 3950 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
3951 | fix_loongson2f (ip); |
3952 | ||
df58fc94 | 3953 | mips_mark_labels (); |
71400594 | 3954 | |
738f4d98 | 3955 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 3956 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 3957 | |
71400594 | 3958 | prev_pinfo = history[0].insn_mo->pinfo; |
df58fc94 | 3959 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 3960 | pinfo = ip->insn_mo->pinfo; |
df58fc94 RS |
3961 | pinfo2 = ip->insn_mo->pinfo2; |
3962 | ||
3963 | if (mips_opts.micromips | |
3964 | && !expansionp | |
3965 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
3966 | && micromips_insn_length (ip->insn_mo) != 2) | |
3967 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
3968 | && micromips_insn_length (ip->insn_mo) != 4))) | |
3969 | as_warn (_("Wrong size instruction in a %u-bit branch delay slot"), | |
3970 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); | |
71400594 | 3971 | |
15be625d CM |
3972 | if (address_expr == NULL) |
3973 | ip->complete_p = 1; | |
3974 | else if (*reloc_type <= BFD_RELOC_UNUSED | |
3975 | && address_expr->X_op == O_constant) | |
3976 | { | |
3977 | unsigned int tmp; | |
3978 | ||
3979 | ip->complete_p = 1; | |
3980 | switch (*reloc_type) | |
3981 | { | |
3982 | case BFD_RELOC_32: | |
3983 | ip->insn_opcode |= address_expr->X_add_number; | |
3984 | break; | |
3985 | ||
3986 | case BFD_RELOC_MIPS_HIGHEST: | |
3987 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; | |
3988 | ip->insn_opcode |= tmp & 0xffff; | |
3989 | break; | |
3990 | ||
3991 | case BFD_RELOC_MIPS_HIGHER: | |
3992 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; | |
3993 | ip->insn_opcode |= tmp & 0xffff; | |
3994 | break; | |
3995 | ||
3996 | case BFD_RELOC_HI16_S: | |
3997 | tmp = (address_expr->X_add_number + 0x8000) >> 16; | |
3998 | ip->insn_opcode |= tmp & 0xffff; | |
3999 | break; | |
4000 | ||
4001 | case BFD_RELOC_HI16: | |
4002 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
4003 | break; | |
4004 | ||
4005 | case BFD_RELOC_UNUSED: | |
4006 | case BFD_RELOC_LO16: | |
4007 | case BFD_RELOC_MIPS_GOT_DISP: | |
4008 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; | |
4009 | break; | |
4010 | ||
4011 | case BFD_RELOC_MIPS_JMP: | |
df58fc94 RS |
4012 | { |
4013 | int shift; | |
4014 | ||
4015 | shift = mips_opts.micromips ? 1 : 2; | |
4016 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4017 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4018 | (unsigned long) address_expr->X_add_number); | |
4019 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4020 | & 0x3ffffff); | |
4021 | ip->complete_p = 0; | |
4022 | } | |
15be625d CM |
4023 | break; |
4024 | ||
4025 | case BFD_RELOC_MIPS16_JMP: | |
4026 | if ((address_expr->X_add_number & 3) != 0) | |
4027 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4028 | (unsigned long) address_expr->X_add_number); | |
4029 | ip->insn_opcode |= | |
4030 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
4031 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
4032 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
4033 | ip->complete_p = 0; | |
4034 | break; | |
4035 | ||
4036 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
4037 | { |
4038 | int shift; | |
4039 | ||
4040 | shift = mips_opts.micromips ? 1 : 2; | |
4041 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4042 | as_bad (_("branch to misaligned address (0x%lx)"), | |
4043 | (unsigned long) address_expr->X_add_number); | |
4044 | if (!mips_relax_branch) | |
4045 | { | |
4046 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
4047 | & ~((1 << (shift + 16)) - 1)) | |
4048 | as_bad (_("branch address range overflow (0x%lx)"), | |
4049 | (unsigned long) address_expr->X_add_number); | |
4050 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4051 | & 0xffff); | |
4052 | } | |
4053 | ip->complete_p = 0; | |
4054 | } | |
15be625d CM |
4055 | break; |
4056 | ||
4057 | default: | |
4058 | internalError (); | |
4059 | } | |
4060 | } | |
4061 | ||
71400594 RS |
4062 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
4063 | { | |
4064 | /* There are a lot of optimizations we could do that we don't. | |
4065 | In particular, we do not, in general, reorder instructions. | |
4066 | If you use gcc with optimization, it will reorder | |
4067 | instructions and generally do much more optimization then we | |
4068 | do here; repeating all that work in the assembler would only | |
4069 | benefit hand written assembly code, and does not seem worth | |
4070 | it. */ | |
4071 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
4072 | ? nops_for_insn (0, history, NULL) |
4073 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 4074 | if (nops > 0) |
252b5132 RH |
4075 | { |
4076 | fragS *old_frag; | |
4077 | unsigned long old_frag_offset; | |
4078 | int i; | |
252b5132 RH |
4079 | |
4080 | old_frag = frag_now; | |
4081 | old_frag_offset = frag_now_fix (); | |
4082 | ||
4083 | for (i = 0; i < nops; i++) | |
4084 | emit_nop (); | |
4085 | ||
4086 | if (listing) | |
4087 | { | |
4088 | listing_prev_line (); | |
4089 | /* We may be at the start of a variant frag. In case we | |
4090 | are, make sure there is enough space for the frag | |
4091 | after the frags created by listing_prev_line. The | |
4092 | argument to frag_grow here must be at least as large | |
4093 | as the argument to all other calls to frag_grow in | |
4094 | this file. We don't have to worry about being in the | |
4095 | middle of a variant frag, because the variants insert | |
4096 | all needed nop instructions themselves. */ | |
4097 | frag_grow (40); | |
4098 | } | |
4099 | ||
404a8071 | 4100 | mips_move_labels (); |
252b5132 RH |
4101 | |
4102 | #ifndef NO_ECOFF_DEBUGGING | |
4103 | if (ECOFF_DEBUGGING) | |
4104 | ecoff_fix_loc (old_frag, old_frag_offset); | |
4105 | #endif | |
4106 | } | |
71400594 RS |
4107 | } |
4108 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
4109 | { | |
932d1a1b RS |
4110 | int nops; |
4111 | ||
4112 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
4113 | ignoring hazards generated by the first prev_nop_frag_since | |
4114 | instructions. */ | |
4115 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 4116 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 4117 | |
71400594 RS |
4118 | /* Enforce NOPS as a minimum. */ |
4119 | if (nops > prev_nop_frag_required) | |
4120 | prev_nop_frag_required = nops; | |
252b5132 | 4121 | |
71400594 RS |
4122 | if (prev_nop_frag_holds == prev_nop_frag_required) |
4123 | { | |
4124 | /* Settle for the current number of nops. Update the history | |
4125 | accordingly (for the benefit of any future .set reorder code). */ | |
4126 | prev_nop_frag = NULL; | |
4127 | insert_into_history (prev_nop_frag_since, | |
4128 | prev_nop_frag_holds, NOP_INSN); | |
4129 | } | |
4130 | else | |
4131 | { | |
4132 | /* Allow this instruction to replace one of the nops that was | |
4133 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 4134 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
4135 | prev_nop_frag_holds--; |
4136 | prev_nop_frag_since++; | |
252b5132 RH |
4137 | } |
4138 | } | |
4139 | ||
a4e06468 RS |
4140 | method = get_append_method (ip); |
4141 | ||
58e2ea4d MR |
4142 | #ifdef OBJ_ELF |
4143 | /* The value passed to dwarf2_emit_insn is the distance between | |
4144 | the beginning of the current instruction and the address that | |
e3a82c8e MR |
4145 | should be recorded in the debug tables. This is normally the |
4146 | current address. | |
4147 | ||
df58fc94 RS |
4148 | For MIPS16/microMIPS debug info we want to use ISA-encoded |
4149 | addresses, so we use -1 for an address higher by one than the | |
4150 | current one. | |
e3a82c8e MR |
4151 | |
4152 | If the instruction produced is a branch that we will swap with | |
4153 | the preceding instruction, then we add the displacement by which | |
4154 | the branch will be moved backwards. This is more appropriate | |
2309ddf2 MR |
4155 | and for MIPS16/microMIPS code also prevents a debugger from |
4156 | placing a breakpoint in the middle of the branch (and corrupting | |
4157 | code if software breakpoints are used). */ | |
df58fc94 | 4158 | dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) |
e3a82c8e | 4159 | + (method == APPEND_SWAP ? insn_length (history) : 0)); |
58e2ea4d MR |
4160 | #endif |
4161 | ||
df58fc94 RS |
4162 | relax32 = (mips_relax_branch |
4163 | /* Don't try branch relaxation within .set nomacro, or within | |
4164 | .set noat if we use $at for PIC computations. If it turns | |
4165 | out that the branch was out-of-range, we'll get an error. */ | |
4166 | && !mips_opts.warn_about_macros | |
4167 | && (mips_opts.at || mips_pic == NO_PIC) | |
4168 | /* Don't relax BPOSGE32/64 as they have no complementing | |
4169 | branches. */ | |
4170 | && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP)) | |
4171 | /* Don't try 32-bit branch relaxation when users specify | |
4172 | 16-bit/32-bit instructions. */ | |
4173 | && !forced_insn_length); | |
4174 | ||
4175 | if (!HAVE_CODE_COMPRESSION | |
4176 | && address_expr | |
4177 | && relax32 | |
0b25d3e6 | 4178 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 | 4179 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
df58fc94 | 4180 | || pinfo & INSN_COND_BRANCH_LIKELY)) |
4a6a3df4 | 4181 | { |
895921c9 | 4182 | relaxed_branch = TRUE; |
1e915849 RS |
4183 | add_relaxed_insn (ip, (relaxed_branch_length |
4184 | (NULL, NULL, | |
4185 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
4186 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
4187 | : 0)), 4, | |
4188 | RELAX_BRANCH_ENCODE | |
66b3e8da MR |
4189 | (AT, |
4190 | pinfo & INSN_UNCOND_BRANCH_DELAY, | |
1e915849 RS |
4191 | pinfo & INSN_COND_BRANCH_LIKELY, |
4192 | pinfo & INSN_WRITE_GPR_31, | |
4193 | 0), | |
4194 | address_expr->X_add_symbol, | |
4195 | address_expr->X_add_number); | |
4a6a3df4 AO |
4196 | *reloc_type = BFD_RELOC_UNUSED; |
4197 | } | |
df58fc94 RS |
4198 | else if (mips_opts.micromips |
4199 | && address_expr | |
4200 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
4201 | || *reloc_type > BFD_RELOC_UNUSED) | |
4202 | && (pinfo & INSN_UNCOND_BRANCH_DELAY | |
4203 | || pinfo & INSN_COND_BRANCH_DELAY | |
4204 | || (pinfo2 & ~INSN2_ALIAS) == INSN2_UNCOND_BRANCH | |
4205 | || pinfo2 & INSN2_COND_BRANCH)) | |
4206 | { | |
4207 | bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED; | |
4208 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; | |
4209 | int uncond = (pinfo & INSN_UNCOND_BRANCH_DELAY | |
4210 | || pinfo2 & INSN2_UNCOND_BRANCH) ? -1 : 0; | |
4211 | int compact = pinfo2 & (INSN2_COND_BRANCH | INSN2_UNCOND_BRANCH); | |
4212 | int al = pinfo & INSN_WRITE_GPR_31; | |
4213 | int length32; | |
4214 | ||
4215 | gas_assert (address_expr != NULL); | |
4216 | gas_assert (!mips_relax.sequence); | |
4217 | ||
4218 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); | |
4219 | add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4, | |
4220 | RELAX_MICROMIPS_ENCODE (type, AT, | |
4221 | forced_insn_length == 2, | |
4222 | uncond, compact, al, relax32, | |
4223 | 0, 0), | |
4224 | address_expr->X_add_symbol, | |
4225 | address_expr->X_add_number); | |
4226 | *reloc_type = BFD_RELOC_UNUSED; | |
4227 | } | |
4228 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
4229 | { |
4230 | /* We need to set up a variant frag. */ | |
df58fc94 | 4231 | gas_assert (address_expr != NULL); |
1e915849 RS |
4232 | add_relaxed_insn (ip, 4, 0, |
4233 | RELAX_MIPS16_ENCODE | |
4234 | (*reloc_type - BFD_RELOC_UNUSED, | |
df58fc94 | 4235 | forced_insn_length == 2, forced_insn_length == 4, |
1e915849 RS |
4236 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, |
4237 | history[0].mips16_absolute_jump_p), | |
4238 | make_expr_symbol (address_expr), 0); | |
252b5132 | 4239 | } |
252b5132 RH |
4240 | else if (mips_opts.mips16 |
4241 | && ! ip->use_extend | |
f6688943 | 4242 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 4243 | { |
b8ee1a6e DU |
4244 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0) |
4245 | /* Make sure there is enough room to swap this instruction with | |
4246 | a following jump instruction. */ | |
4247 | frag_grow (6); | |
1e915849 | 4248 | add_fixed_insn (ip); |
252b5132 RH |
4249 | } |
4250 | else | |
4251 | { | |
4252 | if (mips_opts.mips16 | |
4253 | && mips_opts.noreorder | |
4254 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
4255 | as_warn (_("extended instruction in delay slot")); | |
4256 | ||
4d7206a2 RS |
4257 | if (mips_relax.sequence) |
4258 | { | |
4259 | /* If we've reached the end of this frag, turn it into a variant | |
4260 | frag and record the information for the instructions we've | |
4261 | written so far. */ | |
4262 | if (frag_room () < 4) | |
4263 | relax_close_frag (); | |
df58fc94 | 4264 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
4265 | } |
4266 | ||
584892a6 | 4267 | if (mips_relax.sequence != 2) |
df58fc94 RS |
4268 | { |
4269 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
4270 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
4271 | mips_macro_warning.sizes[0] += insn_length (ip); | |
4272 | mips_macro_warning.insns[0]++; | |
4273 | } | |
584892a6 | 4274 | if (mips_relax.sequence != 1) |
df58fc94 RS |
4275 | { |
4276 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
4277 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
4278 | mips_macro_warning.sizes[1] += insn_length (ip); | |
4279 | mips_macro_warning.insns[1]++; | |
4280 | } | |
584892a6 | 4281 | |
1e915849 RS |
4282 | if (mips_opts.mips16) |
4283 | { | |
4284 | ip->fixed_p = 1; | |
4285 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
4286 | } | |
4287 | add_fixed_insn (ip); | |
252b5132 RH |
4288 | } |
4289 | ||
9fe77896 | 4290 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 4291 | { |
df58fc94 | 4292 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 4293 | reloc_howto_type *howto0; |
9fe77896 RS |
4294 | reloc_howto_type *howto; |
4295 | int i; | |
34ce925e | 4296 | |
df58fc94 RS |
4297 | /* Perform any necessary conversion to microMIPS relocations |
4298 | and find out how many relocations there actually are. */ | |
4299 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
4300 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
4301 | ||
9fe77896 RS |
4302 | /* In a compound relocation, it is the final (outermost) |
4303 | operator that determines the relocated field. */ | |
2309ddf2 MR |
4304 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
4305 | ||
9fe77896 RS |
4306 | if (howto == NULL) |
4307 | { | |
4308 | /* To reproduce this failure try assembling gas/testsuites/ | |
4309 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
4310 | assembler. */ | |
df58fc94 RS |
4311 | as_bad (_("Unsupported MIPS relocation number %d"), |
4312 | final_type[i - 1]); | |
9fe77896 RS |
4313 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); |
4314 | } | |
2309ddf2 MR |
4315 | |
4316 | if (i > 1) | |
4317 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
4318 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
4319 | bfd_get_reloc_size (howto), | |
4320 | address_expr, | |
2309ddf2 MR |
4321 | howto0 && howto0->pc_relative, |
4322 | final_type[0]); | |
9fe77896 RS |
4323 | |
4324 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 4325 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
4326 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
4327 | ||
4328 | /* These relocations can have an addend that won't fit in | |
4329 | 4 octets for 64bit assembly. */ | |
4330 | if (HAVE_64BIT_GPRS | |
4331 | && ! howto->partial_inplace | |
4332 | && (reloc_type[0] == BFD_RELOC_16 | |
4333 | || reloc_type[0] == BFD_RELOC_32 | |
4334 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4335 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
4336 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
4337 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
4338 | || reloc_type[0] == BFD_RELOC_64 | |
4339 | || reloc_type[0] == BFD_RELOC_CTOR | |
4340 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
4341 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
4342 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
4343 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
4344 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
4345 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
4346 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
4347 | || hi16_reloc_p (reloc_type[0]) | |
4348 | || lo16_reloc_p (reloc_type[0]))) | |
4349 | ip->fixp[0]->fx_no_overflow = 1; | |
4350 | ||
4351 | if (mips_relax.sequence) | |
4352 | { | |
4353 | if (mips_relax.first_fixup == 0) | |
4354 | mips_relax.first_fixup = ip->fixp[0]; | |
4355 | } | |
4356 | else if (reloc_needs_lo_p (*reloc_type)) | |
4357 | { | |
4358 | struct mips_hi_fixup *hi_fixup; | |
4359 | ||
4360 | /* Reuse the last entry if it already has a matching %lo. */ | |
4361 | hi_fixup = mips_hi_fixup_list; | |
4362 | if (hi_fixup == 0 | |
4363 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 4364 | { |
9fe77896 RS |
4365 | hi_fixup = ((struct mips_hi_fixup *) |
4366 | xmalloc (sizeof (struct mips_hi_fixup))); | |
4367 | hi_fixup->next = mips_hi_fixup_list; | |
4368 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 4369 | } |
9fe77896 RS |
4370 | hi_fixup->fixp = ip->fixp[0]; |
4371 | hi_fixup->seg = now_seg; | |
4372 | } | |
252b5132 | 4373 | |
9fe77896 RS |
4374 | /* Add fixups for the second and third relocations, if given. |
4375 | Note that the ABI allows the second relocation to be | |
4376 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
4377 | moment we only use RSS_UNDEF, but we could add support | |
4378 | for the others if it ever becomes necessary. */ | |
4379 | for (i = 1; i < 3; i++) | |
4380 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
4381 | { | |
4382 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
4383 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 4384 | FALSE, final_type[i]); |
f6688943 | 4385 | |
9fe77896 RS |
4386 | /* Use fx_tcbit to mark compound relocs. */ |
4387 | ip->fixp[0]->fx_tcbit = 1; | |
4388 | ip->fixp[i]->fx_tcbit = 1; | |
4389 | } | |
252b5132 | 4390 | } |
1e915849 | 4391 | install_insn (ip); |
252b5132 RH |
4392 | |
4393 | /* Update the register mask information. */ | |
4c260379 RS |
4394 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
4395 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 4396 | |
a4e06468 | 4397 | switch (method) |
252b5132 | 4398 | { |
a4e06468 RS |
4399 | case APPEND_ADD: |
4400 | insert_into_history (0, 1, ip); | |
4401 | break; | |
4402 | ||
4403 | case APPEND_ADD_WITH_NOP: | |
4404 | insert_into_history (0, 1, ip); | |
df58fc94 RS |
4405 | if (mips_opts.micromips |
4406 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
4407 | { | |
4408 | add_fixed_insn (µmips_nop32_insn); | |
4409 | insert_into_history (0, 1, µmips_nop32_insn); | |
4410 | if (mips_relax.sequence) | |
4411 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
4412 | } | |
4413 | else | |
4414 | { | |
4415 | emit_nop (); | |
4416 | if (mips_relax.sequence) | |
4417 | mips_relax.sizes[mips_relax.sequence - 1] += NOP_INSN_SIZE; | |
4418 | } | |
a4e06468 RS |
4419 | break; |
4420 | ||
4421 | case APPEND_ADD_COMPACT: | |
4422 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
4423 | gas_assert (mips_opts.mips16); | |
4424 | ip->insn_opcode |= 0x0080; | |
4425 | find_altered_mips16_opcode (ip); | |
4426 | install_insn (ip); | |
4427 | insert_into_history (0, 1, ip); | |
4428 | break; | |
4429 | ||
4430 | case APPEND_SWAP: | |
4431 | { | |
4432 | struct mips_cl_insn delay = history[0]; | |
4433 | if (mips_opts.mips16) | |
4434 | { | |
4435 | know (delay.frag == ip->frag); | |
4436 | move_insn (ip, delay.frag, delay.where); | |
4437 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
4438 | } | |
df58fc94 RS |
4439 | else if (mips_opts.micromips) |
4440 | { | |
4441 | /* We don't reorder for micromips. */ | |
4442 | abort (); | |
4443 | } | |
a4e06468 RS |
4444 | else if (relaxed_branch) |
4445 | { | |
4446 | /* Add the delay slot instruction to the end of the | |
4447 | current frag and shrink the fixed part of the | |
4448 | original frag. If the branch occupies the tail of | |
4449 | the latter, move it backwards to cover the gap. */ | |
4450 | delay.frag->fr_fix -= 4; | |
4451 | if (delay.frag == ip->frag) | |
4452 | move_insn (ip, ip->frag, ip->where - 4); | |
4453 | add_fixed_insn (&delay); | |
4454 | } | |
4455 | else | |
4456 | { | |
4457 | move_insn (&delay, ip->frag, ip->where); | |
4458 | move_insn (ip, history[0].frag, history[0].where); | |
4459 | } | |
4460 | history[0] = *ip; | |
4461 | delay.fixed_p = 1; | |
4462 | insert_into_history (0, 1, &delay); | |
4463 | } | |
4464 | break; | |
252b5132 RH |
4465 | } |
4466 | ||
13408f1e RS |
4467 | /* If we have just completed an unconditional branch, clear the history. */ |
4468 | if ((history[1].insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) | |
4469 | || (mips_opts.mips16 | |
4470 | && (history[0].insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH))) | |
4471 | mips_no_prev_insn (); | |
4472 | ||
df58fc94 RS |
4473 | /* We need to emit a label at the end of branch-likely macros. */ |
4474 | if (emit_branch_likely_macro) | |
4475 | { | |
4476 | emit_branch_likely_macro = FALSE; | |
4477 | micromips_add_label (); | |
4478 | } | |
4479 | ||
252b5132 RH |
4480 | /* We just output an insn, so the next one doesn't have a label. */ |
4481 | mips_clear_insn_labels (); | |
252b5132 RH |
4482 | } |
4483 | ||
7d10b47d | 4484 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
4485 | |
4486 | static void | |
7d10b47d | 4487 | mips_no_prev_insn (void) |
252b5132 | 4488 | { |
7d10b47d RS |
4489 | prev_nop_frag = NULL; |
4490 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
4491 | mips_clear_insn_labels (); |
4492 | } | |
4493 | ||
7d10b47d RS |
4494 | /* This function must be called before we emit something other than |
4495 | instructions. It is like mips_no_prev_insn except that it inserts | |
4496 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 4497 | |
7d10b47d RS |
4498 | void |
4499 | mips_emit_delays (void) | |
252b5132 RH |
4500 | { |
4501 | if (! mips_opts.noreorder) | |
4502 | { | |
932d1a1b | 4503 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
4504 | if (nops > 0) |
4505 | { | |
7d10b47d RS |
4506 | while (nops-- > 0) |
4507 | add_fixed_insn (NOP_INSN); | |
4508 | mips_move_labels (); | |
4509 | } | |
4510 | } | |
4511 | mips_no_prev_insn (); | |
4512 | } | |
4513 | ||
4514 | /* Start a (possibly nested) noreorder block. */ | |
4515 | ||
4516 | static void | |
4517 | start_noreorder (void) | |
4518 | { | |
4519 | if (mips_opts.noreorder == 0) | |
4520 | { | |
4521 | unsigned int i; | |
4522 | int nops; | |
4523 | ||
4524 | /* None of the instructions before the .set noreorder can be moved. */ | |
4525 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
4526 | history[i].fixed_p = 1; | |
4527 | ||
4528 | /* Insert any nops that might be needed between the .set noreorder | |
4529 | block and the previous instructions. We will later remove any | |
4530 | nops that turn out not to be needed. */ | |
932d1a1b | 4531 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
4532 | if (nops > 0) |
4533 | { | |
4534 | if (mips_optimize != 0) | |
252b5132 RH |
4535 | { |
4536 | /* Record the frag which holds the nop instructions, so | |
4537 | that we can remove them if we don't need them. */ | |
df58fc94 | 4538 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
4539 | prev_nop_frag = frag_now; |
4540 | prev_nop_frag_holds = nops; | |
4541 | prev_nop_frag_required = 0; | |
4542 | prev_nop_frag_since = 0; | |
4543 | } | |
4544 | ||
4545 | for (; nops > 0; --nops) | |
1e915849 | 4546 | add_fixed_insn (NOP_INSN); |
252b5132 | 4547 | |
7d10b47d RS |
4548 | /* Move on to a new frag, so that it is safe to simply |
4549 | decrease the size of prev_nop_frag. */ | |
4550 | frag_wane (frag_now); | |
4551 | frag_new (0); | |
404a8071 | 4552 | mips_move_labels (); |
252b5132 | 4553 | } |
df58fc94 | 4554 | mips_mark_labels (); |
7d10b47d | 4555 | mips_clear_insn_labels (); |
252b5132 | 4556 | } |
7d10b47d RS |
4557 | mips_opts.noreorder++; |
4558 | mips_any_noreorder = 1; | |
4559 | } | |
252b5132 | 4560 | |
7d10b47d | 4561 | /* End a nested noreorder block. */ |
252b5132 | 4562 | |
7d10b47d RS |
4563 | static void |
4564 | end_noreorder (void) | |
4565 | { | |
6a32d874 | 4566 | |
7d10b47d RS |
4567 | mips_opts.noreorder--; |
4568 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
4569 | { | |
4570 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
4571 | handling nop insertion the .set reorder way. */ | |
4572 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 4573 | * NOP_INSN_SIZE); |
7d10b47d RS |
4574 | insert_into_history (prev_nop_frag_since, |
4575 | prev_nop_frag_required, NOP_INSN); | |
4576 | prev_nop_frag = NULL; | |
4577 | } | |
252b5132 RH |
4578 | } |
4579 | ||
584892a6 RS |
4580 | /* Set up global variables for the start of a new macro. */ |
4581 | ||
4582 | static void | |
4583 | macro_start (void) | |
4584 | { | |
4585 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
4586 | memset (&mips_macro_warning.first_insn_sizes, 0, |
4587 | sizeof (mips_macro_warning.first_insn_sizes)); | |
4588 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 4589 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
47e39b9d | 4590 | && (history[0].insn_mo->pinfo |
584892a6 RS |
4591 | & (INSN_UNCOND_BRANCH_DELAY |
4592 | | INSN_COND_BRANCH_DELAY | |
4593 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
df58fc94 RS |
4594 | switch (history[0].insn_mo->pinfo2 |
4595 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
4596 | { | |
4597 | case INSN2_BRANCH_DELAY_32BIT: | |
4598 | mips_macro_warning.delay_slot_length = 4; | |
4599 | break; | |
4600 | case INSN2_BRANCH_DELAY_16BIT: | |
4601 | mips_macro_warning.delay_slot_length = 2; | |
4602 | break; | |
4603 | default: | |
4604 | mips_macro_warning.delay_slot_length = 0; | |
4605 | break; | |
4606 | } | |
4607 | mips_macro_warning.first_frag = NULL; | |
584892a6 RS |
4608 | } |
4609 | ||
df58fc94 RS |
4610 | /* Given that a macro is longer than one instruction or of the wrong size, |
4611 | return the appropriate warning for it. Return null if no warning is | |
4612 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
4613 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
4614 | and RELAX_NOMACRO. */ | |
584892a6 RS |
4615 | |
4616 | static const char * | |
4617 | macro_warning (relax_substateT subtype) | |
4618 | { | |
4619 | if (subtype & RELAX_DELAY_SLOT) | |
4620 | return _("Macro instruction expanded into multiple instructions" | |
4621 | " in a branch delay slot"); | |
4622 | else if (subtype & RELAX_NOMACRO) | |
4623 | return _("Macro instruction expanded into multiple instructions"); | |
df58fc94 RS |
4624 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
4625 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
4626 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
4627 | ? _("Macro instruction expanded into a wrong size instruction" | |
4628 | " in a 16-bit branch delay slot") | |
4629 | : _("Macro instruction expanded into a wrong size instruction" | |
4630 | " in a 32-bit branch delay slot")); | |
584892a6 RS |
4631 | else |
4632 | return 0; | |
4633 | } | |
4634 | ||
4635 | /* Finish up a macro. Emit warnings as appropriate. */ | |
4636 | ||
4637 | static void | |
4638 | macro_end (void) | |
4639 | { | |
df58fc94 RS |
4640 | /* Relaxation warning flags. */ |
4641 | relax_substateT subtype = 0; | |
4642 | ||
4643 | /* Check delay slot size requirements. */ | |
4644 | if (mips_macro_warning.delay_slot_length == 2) | |
4645 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
4646 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 4647 | { |
df58fc94 RS |
4648 | if (mips_macro_warning.delay_slot_length |
4649 | != mips_macro_warning.first_insn_sizes[0]) | |
4650 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
4651 | if (mips_macro_warning.delay_slot_length | |
4652 | != mips_macro_warning.first_insn_sizes[1]) | |
4653 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
4654 | } | |
584892a6 | 4655 | |
df58fc94 RS |
4656 | /* Check instruction count requirements. */ |
4657 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
4658 | { | |
4659 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
4660 | subtype |= RELAX_SECOND_LONGER; |
4661 | if (mips_opts.warn_about_macros) | |
4662 | subtype |= RELAX_NOMACRO; | |
4663 | if (mips_macro_warning.delay_slot_p) | |
4664 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 4665 | } |
584892a6 | 4666 | |
df58fc94 RS |
4667 | /* If both alternatives fail to fill a delay slot correctly, |
4668 | emit the warning now. */ | |
4669 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
4670 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
4671 | { | |
4672 | relax_substateT s; | |
4673 | const char *msg; | |
4674 | ||
4675 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
4676 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
4677 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
4678 | msg = macro_warning (s); | |
4679 | if (msg != NULL) | |
4680 | as_warn ("%s", msg); | |
4681 | subtype &= ~s; | |
4682 | } | |
4683 | ||
4684 | /* If both implementations are longer than 1 instruction, then emit the | |
4685 | warning now. */ | |
4686 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
4687 | { | |
4688 | relax_substateT s; | |
4689 | const char *msg; | |
4690 | ||
4691 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
4692 | msg = macro_warning (s); | |
4693 | if (msg != NULL) | |
4694 | as_warn ("%s", msg); | |
4695 | subtype &= ~s; | |
584892a6 | 4696 | } |
df58fc94 RS |
4697 | |
4698 | /* If any flags still set, then one implementation might need a warning | |
4699 | and the other either will need one of a different kind or none at all. | |
4700 | Pass any remaining flags over to relaxation. */ | |
4701 | if (mips_macro_warning.first_frag != NULL) | |
4702 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
4703 | } |
4704 | ||
df58fc94 RS |
4705 | /* Instruction operand formats used in macros that vary between |
4706 | standard MIPS and microMIPS code. */ | |
4707 | ||
4708 | static const char * const brk_fmt[2] = { "c", "mF" }; | |
4709 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; | |
4710 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
4711 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
4712 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
4713 | static const char * const mfhl_fmt[2] = { "d", "mj" }; | |
4714 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; | |
4715 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
4716 | ||
4717 | #define BRK_FMT (brk_fmt[mips_opts.micromips]) | |
4718 | #define COP12_FMT (cop12_fmt[mips_opts.micromips]) | |
4719 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) | |
4720 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
4721 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
4722 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips]) | |
4723 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) | |
4724 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
4725 | ||
6e1304d8 RS |
4726 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
4727 | The first argument in *ARGS will be either the code for a single | |
4728 | relocation or -1 followed by the three codes that make up a | |
4729 | composite relocation. */ | |
4730 | ||
4731 | static void | |
4732 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
4733 | { | |
4734 | int i, next; | |
4735 | ||
4736 | next = va_arg (*args, int); | |
4737 | if (next >= 0) | |
4738 | r[0] = (bfd_reloc_code_real_type) next; | |
4739 | else | |
4740 | for (i = 0; i < 3; i++) | |
4741 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
4742 | } | |
4743 | ||
252b5132 RH |
4744 | /* Build an instruction created by a macro expansion. This is passed |
4745 | a pointer to the count of instructions created so far, an | |
4746 | expression, the name of the instruction to build, an operand format | |
4747 | string, and corresponding arguments. */ | |
4748 | ||
252b5132 | 4749 | static void |
67c0d1eb | 4750 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 4751 | { |
df58fc94 | 4752 | const struct mips_opcode *mo = NULL; |
f6688943 | 4753 | bfd_reloc_code_real_type r[3]; |
df58fc94 RS |
4754 | const struct mips_opcode *amo; |
4755 | struct hash_control *hash; | |
4756 | struct mips_cl_insn insn; | |
252b5132 | 4757 | va_list args; |
252b5132 | 4758 | |
252b5132 | 4759 | va_start (args, fmt); |
252b5132 | 4760 | |
252b5132 RH |
4761 | if (mips_opts.mips16) |
4762 | { | |
03ea81db | 4763 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
4764 | va_end (args); |
4765 | return; | |
4766 | } | |
4767 | ||
f6688943 TS |
4768 | r[0] = BFD_RELOC_UNUSED; |
4769 | r[1] = BFD_RELOC_UNUSED; | |
4770 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
4771 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
4772 | amo = (struct mips_opcode *) hash_find (hash, name); | |
4773 | gas_assert (amo); | |
4774 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 4775 | |
df58fc94 | 4776 | do |
8b082fb1 TS |
4777 | { |
4778 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 RS |
4779 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
4780 | We try to match an instruction that fulfils the branch delay | |
4781 | slot instruction length requirement (if any) of the previous | |
4782 | instruction. While doing this we record the first instruction | |
4783 | seen that matches all the other conditions and use it anyway | |
4784 | if the requirement cannot be met; we will issue an appropriate | |
4785 | warning later on. */ | |
4786 | if (strcmp (fmt, amo->args) == 0 | |
4787 | && amo->pinfo != INSN_MACRO | |
4788 | && is_opcode_valid (amo) | |
4789 | && is_size_valid (amo)) | |
4790 | { | |
4791 | if (is_delay_slot_valid (amo)) | |
4792 | { | |
4793 | mo = amo; | |
4794 | break; | |
4795 | } | |
4796 | else if (!mo) | |
4797 | mo = amo; | |
4798 | } | |
8b082fb1 | 4799 | |
df58fc94 RS |
4800 | ++amo; |
4801 | gas_assert (amo->name); | |
252b5132 | 4802 | } |
df58fc94 | 4803 | while (strcmp (name, amo->name) == 0); |
252b5132 | 4804 | |
df58fc94 | 4805 | gas_assert (mo); |
1e915849 | 4806 | create_insn (&insn, mo); |
252b5132 RH |
4807 | for (;;) |
4808 | { | |
4809 | switch (*fmt++) | |
4810 | { | |
4811 | case '\0': | |
4812 | break; | |
4813 | ||
4814 | case ',': | |
4815 | case '(': | |
4816 | case ')': | |
4817 | continue; | |
4818 | ||
5f74bc13 CD |
4819 | case '+': |
4820 | switch (*fmt++) | |
4821 | { | |
4822 | case 'A': | |
4823 | case 'E': | |
df58fc94 RS |
4824 | INSERT_OPERAND (mips_opts.micromips, |
4825 | EXTLSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
4826 | continue; |
4827 | ||
4828 | case 'B': | |
4829 | case 'F': | |
4830 | /* Note that in the macro case, these arguments are already | |
4831 | in MSB form. (When handling the instruction in the | |
4832 | non-macro case, these arguments are sizes from which | |
4833 | MSB values must be calculated.) */ | |
df58fc94 RS |
4834 | INSERT_OPERAND (mips_opts.micromips, |
4835 | INSMSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
4836 | continue; |
4837 | ||
4838 | case 'C': | |
4839 | case 'G': | |
4840 | case 'H': | |
4841 | /* Note that in the macro case, these arguments are already | |
4842 | in MSBD form. (When handling the instruction in the | |
4843 | non-macro case, these arguments are sizes from which | |
4844 | MSBD values must be calculated.) */ | |
df58fc94 RS |
4845 | INSERT_OPERAND (mips_opts.micromips, |
4846 | EXTMSBD, insn, va_arg (args, int)); | |
5f74bc13 CD |
4847 | continue; |
4848 | ||
dd3cbb7e | 4849 | case 'Q': |
df58fc94 RS |
4850 | gas_assert (!mips_opts.micromips); |
4851 | INSERT_OPERAND (0, SEQI, insn, va_arg (args, int)); | |
dd3cbb7e NC |
4852 | continue; |
4853 | ||
5f74bc13 CD |
4854 | default: |
4855 | internalError (); | |
4856 | } | |
4857 | continue; | |
4858 | ||
8b082fb1 | 4859 | case '2': |
df58fc94 RS |
4860 | gas_assert (!mips_opts.micromips); |
4861 | INSERT_OPERAND (0, BP, insn, va_arg (args, int)); | |
8b082fb1 TS |
4862 | continue; |
4863 | ||
df58fc94 RS |
4864 | case 'n': |
4865 | gas_assert (mips_opts.micromips); | |
252b5132 RH |
4866 | case 't': |
4867 | case 'w': | |
4868 | case 'E': | |
df58fc94 | 4869 | INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int)); |
252b5132 RH |
4870 | continue; |
4871 | ||
4872 | case 'c': | |
df58fc94 RS |
4873 | gas_assert (!mips_opts.micromips); |
4874 | INSERT_OPERAND (0, CODE, insn, va_arg (args, int)); | |
38487616 TS |
4875 | continue; |
4876 | ||
252b5132 | 4877 | case 'W': |
df58fc94 RS |
4878 | gas_assert (!mips_opts.micromips); |
4879 | case 'T': | |
4880 | INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int)); | |
252b5132 RH |
4881 | continue; |
4882 | ||
252b5132 | 4883 | case 'G': |
df58fc94 RS |
4884 | if (mips_opts.micromips) |
4885 | INSERT_OPERAND (1, RS, insn, va_arg (args, int)); | |
4886 | else | |
4887 | INSERT_OPERAND (0, RD, insn, va_arg (args, int)); | |
4888 | continue; | |
4889 | ||
af7ee8bf | 4890 | case 'K': |
df58fc94 RS |
4891 | gas_assert (!mips_opts.micromips); |
4892 | case 'd': | |
4893 | INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int)); | |
252b5132 RH |
4894 | continue; |
4895 | ||
4372b673 | 4896 | case 'U': |
df58fc94 | 4897 | gas_assert (!mips_opts.micromips); |
4372b673 NC |
4898 | { |
4899 | int tmp = va_arg (args, int); | |
4900 | ||
df58fc94 RS |
4901 | INSERT_OPERAND (0, RT, insn, tmp); |
4902 | INSERT_OPERAND (0, RD, insn, tmp); | |
4372b673 | 4903 | } |
df58fc94 | 4904 | continue; |
4372b673 | 4905 | |
252b5132 RH |
4906 | case 'V': |
4907 | case 'S': | |
df58fc94 RS |
4908 | gas_assert (!mips_opts.micromips); |
4909 | INSERT_OPERAND (0, FS, insn, va_arg (args, int)); | |
252b5132 RH |
4910 | continue; |
4911 | ||
4912 | case 'z': | |
4913 | continue; | |
4914 | ||
4915 | case '<': | |
df58fc94 RS |
4916 | INSERT_OPERAND (mips_opts.micromips, |
4917 | SHAMT, insn, va_arg (args, int)); | |
252b5132 RH |
4918 | continue; |
4919 | ||
4920 | case 'D': | |
df58fc94 RS |
4921 | gas_assert (!mips_opts.micromips); |
4922 | INSERT_OPERAND (0, FD, insn, va_arg (args, int)); | |
252b5132 RH |
4923 | continue; |
4924 | ||
4925 | case 'B': | |
df58fc94 RS |
4926 | gas_assert (!mips_opts.micromips); |
4927 | INSERT_OPERAND (0, CODE20, insn, va_arg (args, int)); | |
252b5132 RH |
4928 | continue; |
4929 | ||
4372b673 | 4930 | case 'J': |
df58fc94 RS |
4931 | gas_assert (!mips_opts.micromips); |
4932 | INSERT_OPERAND (0, CODE19, insn, va_arg (args, int)); | |
4372b673 NC |
4933 | continue; |
4934 | ||
252b5132 | 4935 | case 'q': |
df58fc94 RS |
4936 | gas_assert (!mips_opts.micromips); |
4937 | INSERT_OPERAND (0, CODE2, insn, va_arg (args, int)); | |
252b5132 RH |
4938 | continue; |
4939 | ||
4940 | case 'b': | |
4941 | case 's': | |
4942 | case 'r': | |
4943 | case 'v': | |
df58fc94 | 4944 | INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int)); |
252b5132 RH |
4945 | continue; |
4946 | ||
4947 | case 'i': | |
4948 | case 'j': | |
6e1304d8 | 4949 | macro_read_relocs (&args, r); |
9c2799c2 | 4950 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
4951 | || *r == BFD_RELOC_MIPS_HIGHER |
4952 | || *r == BFD_RELOC_HI16_S | |
4953 | || *r == BFD_RELOC_LO16 | |
4954 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
4955 | continue; | |
4956 | ||
4957 | case 'o': | |
4958 | macro_read_relocs (&args, r); | |
252b5132 RH |
4959 | continue; |
4960 | ||
4961 | case 'u': | |
6e1304d8 | 4962 | macro_read_relocs (&args, r); |
9c2799c2 | 4963 | gas_assert (ep != NULL |
90ecf173 MR |
4964 | && (ep->X_op == O_constant |
4965 | || (ep->X_op == O_symbol | |
4966 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
4967 | || *r == BFD_RELOC_HI16_S | |
4968 | || *r == BFD_RELOC_HI16 | |
4969 | || *r == BFD_RELOC_GPREL16 | |
4970 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
4971 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
4972 | continue; |
4973 | ||
4974 | case 'p': | |
9c2799c2 | 4975 | gas_assert (ep != NULL); |
bad36eac | 4976 | |
252b5132 RH |
4977 | /* |
4978 | * This allows macro() to pass an immediate expression for | |
4979 | * creating short branches without creating a symbol. | |
bad36eac DJ |
4980 | * |
4981 | * We don't allow branch relaxation for these branches, as | |
4982 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
4983 | */ |
4984 | if (ep->X_op == O_constant) | |
4985 | { | |
df58fc94 RS |
4986 | /* For microMIPS we always use relocations for branches. |
4987 | So we should not resolve immediate values. */ | |
4988 | gas_assert (!mips_opts.micromips); | |
4989 | ||
bad36eac DJ |
4990 | if ((ep->X_add_number & 3) != 0) |
4991 | as_bad (_("branch to misaligned address (0x%lx)"), | |
4992 | (unsigned long) ep->X_add_number); | |
4993 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
4994 | as_bad (_("branch address range overflow (0x%lx)"), | |
4995 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
4996 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
4997 | ep = NULL; | |
4998 | } | |
4999 | else | |
0b25d3e6 | 5000 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
5001 | continue; |
5002 | ||
5003 | case 'a': | |
9c2799c2 | 5004 | gas_assert (ep != NULL); |
f6688943 | 5005 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
5006 | continue; |
5007 | ||
5008 | case 'C': | |
df58fc94 RS |
5009 | gas_assert (!mips_opts.micromips); |
5010 | INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long)); | |
252b5132 RH |
5011 | continue; |
5012 | ||
d43b4baf | 5013 | case 'k': |
df58fc94 RS |
5014 | INSERT_OPERAND (mips_opts.micromips, |
5015 | CACHE, insn, va_arg (args, unsigned long)); | |
5016 | continue; | |
5017 | ||
5018 | case '|': | |
5019 | gas_assert (mips_opts.micromips); | |
5020 | INSERT_OPERAND (1, TRAP, insn, va_arg (args, int)); | |
5021 | continue; | |
5022 | ||
5023 | case '.': | |
5024 | gas_assert (mips_opts.micromips); | |
5025 | INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int)); | |
5026 | continue; | |
5027 | ||
5028 | case '~': | |
5029 | gas_assert (mips_opts.micromips); | |
5030 | INSERT_OPERAND (1, OFFSET12, insn, va_arg (args, unsigned long)); | |
5031 | continue; | |
5032 | ||
5033 | case 'N': | |
5034 | gas_assert (mips_opts.micromips); | |
5035 | INSERT_OPERAND (1, BCC, insn, va_arg (args, int)); | |
5036 | continue; | |
5037 | ||
5038 | case 'm': /* Opcode extension character. */ | |
5039 | gas_assert (mips_opts.micromips); | |
5040 | switch (*fmt++) | |
5041 | { | |
5042 | case 'j': | |
5043 | INSERT_OPERAND (1, MJ, insn, va_arg (args, int)); | |
5044 | break; | |
5045 | ||
5046 | case 'p': | |
5047 | INSERT_OPERAND (1, MP, insn, va_arg (args, int)); | |
5048 | break; | |
5049 | ||
5050 | case 'F': | |
5051 | INSERT_OPERAND (1, IMMF, insn, va_arg (args, int)); | |
5052 | break; | |
5053 | ||
5054 | default: | |
5055 | internalError (); | |
5056 | } | |
d43b4baf TS |
5057 | continue; |
5058 | ||
252b5132 RH |
5059 | default: |
5060 | internalError (); | |
5061 | } | |
5062 | break; | |
5063 | } | |
5064 | va_end (args); | |
9c2799c2 | 5065 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5066 | |
df58fc94 | 5067 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5068 | } |
5069 | ||
5070 | static void | |
67c0d1eb | 5071 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 5072 | va_list *args) |
252b5132 | 5073 | { |
1e915849 | 5074 | struct mips_opcode *mo; |
252b5132 | 5075 | struct mips_cl_insn insn; |
f6688943 TS |
5076 | bfd_reloc_code_real_type r[3] |
5077 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 5078 | |
1e915849 | 5079 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
5080 | gas_assert (mo); |
5081 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 5082 | |
1e915849 | 5083 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 5084 | { |
1e915849 | 5085 | ++mo; |
9c2799c2 NC |
5086 | gas_assert (mo->name); |
5087 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
5088 | } |
5089 | ||
1e915849 | 5090 | create_insn (&insn, mo); |
252b5132 RH |
5091 | for (;;) |
5092 | { | |
5093 | int c; | |
5094 | ||
5095 | c = *fmt++; | |
5096 | switch (c) | |
5097 | { | |
5098 | case '\0': | |
5099 | break; | |
5100 | ||
5101 | case ',': | |
5102 | case '(': | |
5103 | case ')': | |
5104 | continue; | |
5105 | ||
5106 | case 'y': | |
5107 | case 'w': | |
03ea81db | 5108 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
5109 | continue; |
5110 | ||
5111 | case 'x': | |
5112 | case 'v': | |
03ea81db | 5113 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
5114 | continue; |
5115 | ||
5116 | case 'z': | |
03ea81db | 5117 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
5118 | continue; |
5119 | ||
5120 | case 'Z': | |
03ea81db | 5121 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
5122 | continue; |
5123 | ||
5124 | case '0': | |
5125 | case 'S': | |
5126 | case 'P': | |
5127 | case 'R': | |
5128 | continue; | |
5129 | ||
5130 | case 'X': | |
03ea81db | 5131 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
5132 | continue; |
5133 | ||
5134 | case 'Y': | |
5135 | { | |
5136 | int regno; | |
5137 | ||
03ea81db | 5138 | regno = va_arg (*args, int); |
252b5132 | 5139 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 5140 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
5141 | } |
5142 | continue; | |
5143 | ||
5144 | case '<': | |
5145 | case '>': | |
5146 | case '4': | |
5147 | case '5': | |
5148 | case 'H': | |
5149 | case 'W': | |
5150 | case 'D': | |
5151 | case 'j': | |
5152 | case '8': | |
5153 | case 'V': | |
5154 | case 'C': | |
5155 | case 'U': | |
5156 | case 'k': | |
5157 | case 'K': | |
5158 | case 'p': | |
5159 | case 'q': | |
5160 | { | |
9c2799c2 | 5161 | gas_assert (ep != NULL); |
252b5132 RH |
5162 | |
5163 | if (ep->X_op != O_constant) | |
874e8986 | 5164 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
5165 | else |
5166 | { | |
b34976b6 AM |
5167 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
5168 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 5169 | &insn.extend); |
252b5132 | 5170 | ep = NULL; |
f6688943 | 5171 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
5172 | } |
5173 | } | |
5174 | continue; | |
5175 | ||
5176 | case '6': | |
03ea81db | 5177 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
5178 | continue; |
5179 | } | |
5180 | ||
5181 | break; | |
5182 | } | |
5183 | ||
9c2799c2 | 5184 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5185 | |
df58fc94 | 5186 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5187 | } |
5188 | ||
2051e8c4 MR |
5189 | /* |
5190 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
5191 | * higher bits unset. | |
5192 | */ | |
9f872bbe | 5193 | static void |
2051e8c4 MR |
5194 | normalize_constant_expr (expressionS *ex) |
5195 | { | |
9ee2a2d4 | 5196 | if (ex->X_op == O_constant |
2051e8c4 MR |
5197 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
5198 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5199 | - 0x80000000); | |
5200 | } | |
5201 | ||
5202 | /* | |
5203 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
5204 | * all higher bits unset. | |
5205 | */ | |
5206 | static void | |
5207 | normalize_address_expr (expressionS *ex) | |
5208 | { | |
5209 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
5210 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
5211 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
5212 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5213 | - 0x80000000); | |
5214 | } | |
5215 | ||
438c16b8 TS |
5216 | /* |
5217 | * Generate a "jalr" instruction with a relocation hint to the called | |
5218 | * function. This occurs in NewABI PIC code. | |
5219 | */ | |
5220 | static void | |
df58fc94 | 5221 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 5222 | { |
df58fc94 RS |
5223 | static const bfd_reloc_code_real_type jalr_relocs[2] |
5224 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
5225 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
5226 | const char *jalr; | |
685736be | 5227 | char *f = NULL; |
b34976b6 | 5228 | |
1180b5a4 | 5229 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 5230 | { |
cc3d92a5 | 5231 | frag_grow (8); |
f21f8242 AO |
5232 | f = frag_more (0); |
5233 | } | |
df58fc94 RS |
5234 | if (!mips_opts.micromips) |
5235 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
5236 | else | |
5237 | { | |
5238 | jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs"; | |
5239 | if (MIPS_JALR_HINT_P (ep)) | |
5240 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); | |
5241 | else | |
5242 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
5243 | } | |
1180b5a4 | 5244 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 5245 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
5246 | } |
5247 | ||
252b5132 RH |
5248 | /* |
5249 | * Generate a "lui" instruction. | |
5250 | */ | |
5251 | static void | |
67c0d1eb | 5252 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 5253 | { |
9c2799c2 | 5254 | gas_assert (! mips_opts.mips16); |
252b5132 | 5255 | |
df58fc94 | 5256 | if (ep->X_op != O_constant) |
252b5132 | 5257 | { |
9c2799c2 | 5258 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
5259 | /* _gp_disp is a special case, used from s_cpload. |
5260 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 5261 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 5262 | || (! HAVE_NEWABI |
aa6975fb ILT |
5263 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
5264 | || (! mips_in_shared | |
bbe506e8 TS |
5265 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
5266 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
5267 | } |
5268 | ||
df58fc94 | 5269 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
5270 | } |
5271 | ||
885add95 CD |
5272 | /* Generate a sequence of instructions to do a load or store from a constant |
5273 | offset off of a base register (breg) into/from a target register (treg), | |
5274 | using AT if necessary. */ | |
5275 | static void | |
67c0d1eb RS |
5276 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
5277 | int treg, int breg, int dbl) | |
885add95 | 5278 | { |
9c2799c2 | 5279 | gas_assert (ep->X_op == O_constant); |
885add95 | 5280 | |
256ab948 | 5281 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
5282 | if (!dbl) |
5283 | normalize_constant_expr (ep); | |
256ab948 | 5284 | |
67c1ffbe | 5285 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 5286 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
5287 | as_warn (_("operand overflow")); |
5288 | ||
5289 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
5290 | { | |
5291 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 5292 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
5293 | } |
5294 | else | |
5295 | { | |
5296 | /* 32-bit offset, need multiple instructions and AT, like: | |
5297 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
5298 | addu $tempreg,$tempreg,$breg | |
5299 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
5300 | to handle the complete offset. */ | |
67c0d1eb RS |
5301 | macro_build_lui (ep, AT); |
5302 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
5303 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 5304 | |
741fe287 | 5305 | if (!mips_opts.at) |
8fc2e39e | 5306 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
5307 | } |
5308 | } | |
5309 | ||
252b5132 RH |
5310 | /* set_at() |
5311 | * Generates code to set the $at register to true (one) | |
5312 | * if reg is less than the immediate expression. | |
5313 | */ | |
5314 | static void | |
67c0d1eb | 5315 | set_at (int reg, int unsignedp) |
252b5132 RH |
5316 | { |
5317 | if (imm_expr.X_op == O_constant | |
5318 | && imm_expr.X_add_number >= -0x8000 | |
5319 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
5320 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
5321 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
5322 | else |
5323 | { | |
67c0d1eb RS |
5324 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5325 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
5326 | } |
5327 | } | |
5328 | ||
5329 | /* Warn if an expression is not a constant. */ | |
5330 | ||
5331 | static void | |
17a2f251 | 5332 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
5333 | { |
5334 | if (ex->X_op == O_big) | |
5335 | as_bad (_("unsupported large constant")); | |
5336 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
5337 | as_bad (_("Instruction %s requires absolute expression"), |
5338 | ip->insn_mo->name); | |
13757d0c | 5339 | |
9ee2a2d4 MR |
5340 | if (HAVE_32BIT_GPRS) |
5341 | normalize_constant_expr (ex); | |
252b5132 RH |
5342 | } |
5343 | ||
5344 | /* Count the leading zeroes by performing a binary chop. This is a | |
5345 | bulky bit of source, but performance is a LOT better for the | |
5346 | majority of values than a simple loop to count the bits: | |
5347 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
5348 | if ((v) & (1 << (31 - lcnt))) | |
5349 | break; | |
5350 | However it is not code size friendly, and the gain will drop a bit | |
5351 | on certain cached systems. | |
5352 | */ | |
5353 | #define COUNT_TOP_ZEROES(v) \ | |
5354 | (((v) & ~0xffff) == 0 \ | |
5355 | ? ((v) & ~0xff) == 0 \ | |
5356 | ? ((v) & ~0xf) == 0 \ | |
5357 | ? ((v) & ~0x3) == 0 \ | |
5358 | ? ((v) & ~0x1) == 0 \ | |
5359 | ? !(v) \ | |
5360 | ? 32 \ | |
5361 | : 31 \ | |
5362 | : 30 \ | |
5363 | : ((v) & ~0x7) == 0 \ | |
5364 | ? 29 \ | |
5365 | : 28 \ | |
5366 | : ((v) & ~0x3f) == 0 \ | |
5367 | ? ((v) & ~0x1f) == 0 \ | |
5368 | ? 27 \ | |
5369 | : 26 \ | |
5370 | : ((v) & ~0x7f) == 0 \ | |
5371 | ? 25 \ | |
5372 | : 24 \ | |
5373 | : ((v) & ~0xfff) == 0 \ | |
5374 | ? ((v) & ~0x3ff) == 0 \ | |
5375 | ? ((v) & ~0x1ff) == 0 \ | |
5376 | ? 23 \ | |
5377 | : 22 \ | |
5378 | : ((v) & ~0x7ff) == 0 \ | |
5379 | ? 21 \ | |
5380 | : 20 \ | |
5381 | : ((v) & ~0x3fff) == 0 \ | |
5382 | ? ((v) & ~0x1fff) == 0 \ | |
5383 | ? 19 \ | |
5384 | : 18 \ | |
5385 | : ((v) & ~0x7fff) == 0 \ | |
5386 | ? 17 \ | |
5387 | : 16 \ | |
5388 | : ((v) & ~0xffffff) == 0 \ | |
5389 | ? ((v) & ~0xfffff) == 0 \ | |
5390 | ? ((v) & ~0x3ffff) == 0 \ | |
5391 | ? ((v) & ~0x1ffff) == 0 \ | |
5392 | ? 15 \ | |
5393 | : 14 \ | |
5394 | : ((v) & ~0x7ffff) == 0 \ | |
5395 | ? 13 \ | |
5396 | : 12 \ | |
5397 | : ((v) & ~0x3fffff) == 0 \ | |
5398 | ? ((v) & ~0x1fffff) == 0 \ | |
5399 | ? 11 \ | |
5400 | : 10 \ | |
5401 | : ((v) & ~0x7fffff) == 0 \ | |
5402 | ? 9 \ | |
5403 | : 8 \ | |
5404 | : ((v) & ~0xfffffff) == 0 \ | |
5405 | ? ((v) & ~0x3ffffff) == 0 \ | |
5406 | ? ((v) & ~0x1ffffff) == 0 \ | |
5407 | ? 7 \ | |
5408 | : 6 \ | |
5409 | : ((v) & ~0x7ffffff) == 0 \ | |
5410 | ? 5 \ | |
5411 | : 4 \ | |
5412 | : ((v) & ~0x3fffffff) == 0 \ | |
5413 | ? ((v) & ~0x1fffffff) == 0 \ | |
5414 | ? 3 \ | |
5415 | : 2 \ | |
5416 | : ((v) & ~0x7fffffff) == 0 \ | |
5417 | ? 1 \ | |
5418 | : 0) | |
5419 | ||
5420 | /* load_register() | |
67c1ffbe | 5421 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
5422 | * an absolute expression value into a register. |
5423 | */ | |
5424 | static void | |
67c0d1eb | 5425 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
5426 | { |
5427 | int freg; | |
5428 | expressionS hi32, lo32; | |
5429 | ||
5430 | if (ep->X_op != O_big) | |
5431 | { | |
9c2799c2 | 5432 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
5433 | |
5434 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
5435 | if (!dbl) |
5436 | normalize_constant_expr (ep); | |
256ab948 TS |
5437 | |
5438 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
5439 | { |
5440 | /* We can handle 16 bit signed values with an addiu to | |
5441 | $zero. No need to ever use daddiu here, since $zero and | |
5442 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 5443 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5444 | return; |
5445 | } | |
5446 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
5447 | { | |
5448 | /* We can handle 16 bit unsigned values with an ori to | |
5449 | $zero. */ | |
67c0d1eb | 5450 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5451 | return; |
5452 | } | |
256ab948 | 5453 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
5454 | { |
5455 | /* 32 bit values require an lui. */ | |
df58fc94 | 5456 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5457 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 5458 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
5459 | return; |
5460 | } | |
5461 | } | |
5462 | ||
5463 | /* The value is larger than 32 bits. */ | |
5464 | ||
2051e8c4 | 5465 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 5466 | { |
55e08f71 NC |
5467 | char value[32]; |
5468 | ||
5469 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 5470 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 5471 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5472 | return; |
5473 | } | |
5474 | ||
5475 | if (ep->X_op != O_big) | |
5476 | { | |
5477 | hi32 = *ep; | |
5478 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5479 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5480 | hi32.X_add_number &= 0xffffffff; | |
5481 | lo32 = *ep; | |
5482 | lo32.X_add_number &= 0xffffffff; | |
5483 | } | |
5484 | else | |
5485 | { | |
9c2799c2 | 5486 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
5487 | if (ep->X_add_number == 3) |
5488 | generic_bignum[3] = 0; | |
5489 | else if (ep->X_add_number > 4) | |
5490 | as_bad (_("Number larger than 64 bits")); | |
5491 | lo32.X_op = O_constant; | |
5492 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
5493 | hi32.X_op = O_constant; | |
5494 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
5495 | } | |
5496 | ||
5497 | if (hi32.X_add_number == 0) | |
5498 | freg = 0; | |
5499 | else | |
5500 | { | |
5501 | int shift, bit; | |
5502 | unsigned long hi, lo; | |
5503 | ||
956cd1d6 | 5504 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
5505 | { |
5506 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
5507 | { | |
67c0d1eb | 5508 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5509 | return; |
5510 | } | |
5511 | if (lo32.X_add_number & 0x80000000) | |
5512 | { | |
df58fc94 | 5513 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5514 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 5515 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
5516 | return; |
5517 | } | |
5518 | } | |
252b5132 RH |
5519 | |
5520 | /* Check for 16bit shifted constant. We know that hi32 is | |
5521 | non-zero, so start the mask on the first bit of the hi32 | |
5522 | value. */ | |
5523 | shift = 17; | |
5524 | do | |
beae10d5 KH |
5525 | { |
5526 | unsigned long himask, lomask; | |
5527 | ||
5528 | if (shift < 32) | |
5529 | { | |
5530 | himask = 0xffff >> (32 - shift); | |
5531 | lomask = (0xffff << shift) & 0xffffffff; | |
5532 | } | |
5533 | else | |
5534 | { | |
5535 | himask = 0xffff << (shift - 32); | |
5536 | lomask = 0; | |
5537 | } | |
5538 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
5539 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
5540 | { | |
5541 | expressionS tmp; | |
5542 | ||
5543 | tmp.X_op = O_constant; | |
5544 | if (shift < 32) | |
5545 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
5546 | | (lo32.X_add_number >> shift)); | |
5547 | else | |
5548 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 5549 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 5550 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5551 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5552 | return; |
5553 | } | |
f9419b05 | 5554 | ++shift; |
beae10d5 KH |
5555 | } |
5556 | while (shift <= (64 - 16)); | |
252b5132 RH |
5557 | |
5558 | /* Find the bit number of the lowest one bit, and store the | |
5559 | shifted value in hi/lo. */ | |
5560 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
5561 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
5562 | if (lo != 0) | |
5563 | { | |
5564 | bit = 0; | |
5565 | while ((lo & 1) == 0) | |
5566 | { | |
5567 | lo >>= 1; | |
5568 | ++bit; | |
5569 | } | |
5570 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
5571 | hi >>= bit; | |
5572 | } | |
5573 | else | |
5574 | { | |
5575 | bit = 32; | |
5576 | while ((hi & 1) == 0) | |
5577 | { | |
5578 | hi >>= 1; | |
5579 | ++bit; | |
5580 | } | |
5581 | lo = hi; | |
5582 | hi = 0; | |
5583 | } | |
5584 | ||
5585 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
5586 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
5587 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
5588 | { |
5589 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 5590 | if (shift != 0) |
beae10d5 | 5591 | { |
252b5132 RH |
5592 | expressionS tmp; |
5593 | ||
5594 | /* This instruction will set the register to be all | |
5595 | ones. */ | |
beae10d5 KH |
5596 | tmp.X_op = O_constant; |
5597 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 5598 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5599 | if (bit != 0) |
5600 | { | |
5601 | bit += shift; | |
df58fc94 | 5602 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5603 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 5604 | } |
df58fc94 | 5605 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 5606 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5607 | return; |
5608 | } | |
5609 | } | |
252b5132 RH |
5610 | |
5611 | /* Sign extend hi32 before calling load_register, because we can | |
5612 | generally get better code when we load a sign extended value. */ | |
5613 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 5614 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 5615 | load_register (reg, &hi32, 0); |
252b5132 RH |
5616 | freg = reg; |
5617 | } | |
5618 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
5619 | { | |
5620 | if (freg != 0) | |
5621 | { | |
df58fc94 | 5622 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
5623 | freg = reg; |
5624 | } | |
5625 | } | |
5626 | else | |
5627 | { | |
5628 | expressionS mid16; | |
5629 | ||
956cd1d6 | 5630 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 5631 | { |
df58fc94 RS |
5632 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
5633 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
5634 | return; |
5635 | } | |
252b5132 RH |
5636 | |
5637 | if (freg != 0) | |
5638 | { | |
df58fc94 | 5639 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
5640 | freg = reg; |
5641 | } | |
5642 | mid16 = lo32; | |
5643 | mid16.X_add_number >>= 16; | |
67c0d1eb | 5644 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 5645 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
5646 | freg = reg; |
5647 | } | |
5648 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 5649 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
5650 | } |
5651 | ||
269137b2 TS |
5652 | static inline void |
5653 | load_delay_nop (void) | |
5654 | { | |
5655 | if (!gpr_interlocks) | |
5656 | macro_build (NULL, "nop", ""); | |
5657 | } | |
5658 | ||
252b5132 RH |
5659 | /* Load an address into a register. */ |
5660 | ||
5661 | static void | |
67c0d1eb | 5662 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 5663 | { |
252b5132 RH |
5664 | if (ep->X_op != O_constant |
5665 | && ep->X_op != O_symbol) | |
5666 | { | |
5667 | as_bad (_("expression too complex")); | |
5668 | ep->X_op = O_constant; | |
5669 | } | |
5670 | ||
5671 | if (ep->X_op == O_constant) | |
5672 | { | |
67c0d1eb | 5673 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5674 | return; |
5675 | } | |
5676 | ||
5677 | if (mips_pic == NO_PIC) | |
5678 | { | |
5679 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 5680 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5681 | Otherwise we want |
5682 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
5683 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 5684 | If we have an addend, we always use the latter form. |
76b3015f | 5685 | |
d6bc6245 TS |
5686 | With 64bit address space and a usable $at we want |
5687 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5688 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5689 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5690 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5691 | dsll32 $reg,0 | |
3a482fd5 | 5692 | daddu $reg,$reg,$at |
76b3015f | 5693 | |
c03099e6 | 5694 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
5695 | on superscalar processors. |
5696 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5697 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5698 | dsll $reg,16 | |
5699 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
5700 | dsll $reg,16 | |
5701 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
5702 | |
5703 | For GP relative symbols in 64bit address space we can use | |
5704 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5705 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 5706 | { |
6caf9ef4 TS |
5707 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
5708 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
5709 | { | |
5710 | relax_start (ep->X_add_symbol); | |
5711 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
5712 | mips_gp_register, BFD_RELOC_GPREL16); | |
5713 | relax_switch (); | |
5714 | } | |
d6bc6245 | 5715 | |
741fe287 | 5716 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 5717 | { |
df58fc94 RS |
5718 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
5719 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
5720 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5721 | BFD_RELOC_MIPS_HIGHER); | |
5722 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 5723 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 5724 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
5725 | *used_at = 1; |
5726 | } | |
5727 | else | |
5728 | { | |
df58fc94 | 5729 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
5730 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5731 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 5732 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5733 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 5734 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5735 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 5736 | } |
6caf9ef4 TS |
5737 | |
5738 | if (mips_relax.sequence) | |
5739 | relax_end (); | |
d6bc6245 | 5740 | } |
252b5132 RH |
5741 | else |
5742 | { | |
d6bc6245 | 5743 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5744 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 5745 | { |
4d7206a2 | 5746 | relax_start (ep->X_add_symbol); |
67c0d1eb | 5747 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 5748 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 5749 | relax_switch (); |
d6bc6245 | 5750 | } |
67c0d1eb RS |
5751 | macro_build_lui (ep, reg); |
5752 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
5753 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5754 | if (mips_relax.sequence) |
5755 | relax_end (); | |
d6bc6245 | 5756 | } |
252b5132 | 5757 | } |
0a44bf69 | 5758 | else if (!mips_big_got) |
252b5132 RH |
5759 | { |
5760 | expressionS ex; | |
5761 | ||
5762 | /* If this is a reference to an external symbol, we want | |
5763 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5764 | Otherwise we want | |
5765 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5766 | nop | |
5767 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
5768 | If there is a constant, it must be added in after. |
5769 | ||
ed6fb7bd | 5770 | If we have NewABI, we want |
f5040a92 AO |
5771 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
5772 | unless we're referencing a global symbol with a non-zero | |
5773 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
5774 | if (HAVE_NEWABI) |
5775 | { | |
f5040a92 AO |
5776 | if (ep->X_add_number) |
5777 | { | |
4d7206a2 | 5778 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 5779 | ep->X_add_number = 0; |
4d7206a2 | 5780 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
5781 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
5782 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5783 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
5784 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5785 | ex.X_op = O_constant; | |
67c0d1eb | 5786 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5787 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 5788 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 5789 | relax_switch (); |
f5040a92 | 5790 | } |
67c0d1eb | 5791 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5792 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
5793 | if (mips_relax.sequence) |
5794 | relax_end (); | |
ed6fb7bd SC |
5795 | } |
5796 | else | |
5797 | { | |
f5040a92 AO |
5798 | ex.X_add_number = ep->X_add_number; |
5799 | ep->X_add_number = 0; | |
67c0d1eb RS |
5800 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
5801 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5802 | load_delay_nop (); |
4d7206a2 RS |
5803 | relax_start (ep->X_add_symbol); |
5804 | relax_switch (); | |
67c0d1eb | 5805 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 5806 | BFD_RELOC_LO16); |
4d7206a2 | 5807 | relax_end (); |
ed6fb7bd | 5808 | |
f5040a92 AO |
5809 | if (ex.X_add_number != 0) |
5810 | { | |
5811 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
5812 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5813 | ex.X_op = O_constant; | |
67c0d1eb | 5814 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5815 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 5816 | } |
252b5132 RH |
5817 | } |
5818 | } | |
0a44bf69 | 5819 | else if (mips_big_got) |
252b5132 RH |
5820 | { |
5821 | expressionS ex; | |
252b5132 RH |
5822 | |
5823 | /* This is the large GOT case. If this is a reference to an | |
5824 | external symbol, we want | |
5825 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5826 | addu $reg,$reg,$gp | |
5827 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
5828 | |
5829 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
5830 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
5831 | nop | |
5832 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 5833 | If there is a constant, it must be added in after. |
f5040a92 AO |
5834 | |
5835 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
5836 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
5837 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 5838 | */ |
438c16b8 TS |
5839 | if (HAVE_NEWABI) |
5840 | { | |
4d7206a2 | 5841 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 5842 | ep->X_add_number = 0; |
4d7206a2 | 5843 | relax_start (ep->X_add_symbol); |
df58fc94 | 5844 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
5845 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5846 | reg, reg, mips_gp_register); | |
5847 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
5848 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
5849 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
5850 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5851 | else if (ex.X_add_number) | |
5852 | { | |
5853 | ex.X_op = O_constant; | |
67c0d1eb RS |
5854 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
5855 | BFD_RELOC_LO16); | |
f5040a92 AO |
5856 | } |
5857 | ||
5858 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 5859 | relax_switch (); |
67c0d1eb | 5860 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5861 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
5862 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
5863 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 5864 | relax_end (); |
438c16b8 | 5865 | } |
252b5132 | 5866 | else |
438c16b8 | 5867 | { |
f5040a92 AO |
5868 | ex.X_add_number = ep->X_add_number; |
5869 | ep->X_add_number = 0; | |
4d7206a2 | 5870 | relax_start (ep->X_add_symbol); |
df58fc94 | 5871 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
5872 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5873 | reg, reg, mips_gp_register); | |
5874 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
5875 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
5876 | relax_switch (); |
5877 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
5878 | { |
5879 | /* We need a nop before loading from $gp. This special | |
5880 | check is required because the lui which starts the main | |
5881 | instruction stream does not refer to $gp, and so will not | |
5882 | insert the nop which may be required. */ | |
67c0d1eb | 5883 | macro_build (NULL, "nop", ""); |
438c16b8 | 5884 | } |
67c0d1eb | 5885 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5886 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 5887 | load_delay_nop (); |
67c0d1eb | 5888 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 5889 | BFD_RELOC_LO16); |
4d7206a2 | 5890 | relax_end (); |
438c16b8 | 5891 | |
f5040a92 AO |
5892 | if (ex.X_add_number != 0) |
5893 | { | |
5894 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
5895 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5896 | ex.X_op = O_constant; | |
67c0d1eb RS |
5897 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
5898 | BFD_RELOC_LO16); | |
f5040a92 | 5899 | } |
252b5132 RH |
5900 | } |
5901 | } | |
252b5132 RH |
5902 | else |
5903 | abort (); | |
8fc2e39e | 5904 | |
741fe287 | 5905 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 5906 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
5907 | } |
5908 | ||
ea1fb5dc RS |
5909 | /* Move the contents of register SOURCE into register DEST. */ |
5910 | ||
5911 | static void | |
67c0d1eb | 5912 | move_register (int dest, int source) |
ea1fb5dc | 5913 | { |
df58fc94 RS |
5914 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
5915 | instruction specifically requires a 32-bit one. */ | |
5916 | if (mips_opts.micromips | |
5917 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
5918 | macro_build (NULL, "move", "mp,mj", dest, source ); | |
5919 | else | |
5920 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", | |
5921 | dest, source, 0); | |
ea1fb5dc RS |
5922 | } |
5923 | ||
4d7206a2 | 5924 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
5925 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
5926 | The two alternatives are: | |
4d7206a2 RS |
5927 | |
5928 | Global symbol Local sybmol | |
5929 | ------------- ------------ | |
5930 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
5931 | ... ... | |
5932 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
5933 | ||
5934 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
5935 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
5936 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
5937 | |
5938 | static void | |
67c0d1eb | 5939 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
5940 | { |
5941 | expressionS global; | |
5942 | ||
5943 | global = *local; | |
5944 | global.X_add_number = 0; | |
5945 | ||
5946 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
5947 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
5948 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 5949 | relax_switch (); |
67c0d1eb RS |
5950 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
5951 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
5952 | relax_end (); |
5953 | } | |
5954 | ||
5955 | static void | |
67c0d1eb | 5956 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
5957 | { |
5958 | expressionS global; | |
5959 | ||
5960 | global.X_op = O_constant; | |
5961 | global.X_op_symbol = NULL; | |
5962 | global.X_add_symbol = NULL; | |
5963 | global.X_add_number = local->X_add_number; | |
5964 | ||
5965 | relax_start (local->X_add_symbol); | |
67c0d1eb | 5966 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
5967 | dest, dest, BFD_RELOC_LO16); |
5968 | relax_switch (); | |
67c0d1eb | 5969 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
5970 | relax_end (); |
5971 | } | |
5972 | ||
f6a22291 MR |
5973 | static void |
5974 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
5975 | { | |
5976 | expressionS global; | |
5977 | int hold_mips_optimize; | |
5978 | ||
5979 | global.X_op = O_constant; | |
5980 | global.X_op_symbol = NULL; | |
5981 | global.X_add_symbol = NULL; | |
5982 | global.X_add_number = local->X_add_number; | |
5983 | ||
5984 | relax_start (local->X_add_symbol); | |
5985 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
5986 | relax_switch (); | |
5987 | /* Set mips_optimize around the lui instruction to avoid | |
5988 | inserting an unnecessary nop after the lw. */ | |
5989 | hold_mips_optimize = mips_optimize; | |
5990 | mips_optimize = 2; | |
5991 | macro_build_lui (&global, tmp); | |
5992 | mips_optimize = hold_mips_optimize; | |
5993 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
5994 | relax_end (); | |
5995 | ||
5996 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
5997 | } | |
5998 | ||
df58fc94 RS |
5999 | /* Emit a sequence of instructions to emulate a branch likely operation. |
6000 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
6001 | is its complementing branch with the original condition negated. | |
6002 | CALL is set if the original branch specified the link operation. | |
6003 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
6004 | ||
6005 | Code like this is produced in the noreorder mode: | |
6006 | ||
6007 | BRNEG <args>, 1f | |
6008 | nop | |
6009 | b <sym> | |
6010 | delay slot (executed only if branch taken) | |
6011 | 1: | |
6012 | ||
6013 | or, if CALL is set: | |
6014 | ||
6015 | BRNEG <args>, 1f | |
6016 | nop | |
6017 | bal <sym> | |
6018 | delay slot (executed only if branch taken) | |
6019 | 1: | |
6020 | ||
6021 | In the reorder mode the delay slot would be filled with a nop anyway, | |
6022 | so code produced is simply: | |
6023 | ||
6024 | BR <args>, <sym> | |
6025 | nop | |
6026 | ||
6027 | This function is used when producing code for the microMIPS ASE that | |
6028 | does not implement branch likely instructions in hardware. */ | |
6029 | ||
6030 | static void | |
6031 | macro_build_branch_likely (const char *br, const char *brneg, | |
6032 | int call, expressionS *ep, const char *fmt, | |
6033 | unsigned int sreg, unsigned int treg) | |
6034 | { | |
6035 | int noreorder = mips_opts.noreorder; | |
6036 | expressionS expr1; | |
6037 | ||
6038 | gas_assert (mips_opts.micromips); | |
6039 | start_noreorder (); | |
6040 | if (noreorder) | |
6041 | { | |
6042 | micromips_label_expr (&expr1); | |
6043 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
6044 | macro_build (NULL, "nop", ""); | |
6045 | macro_build (ep, call ? "bal" : "b", "p"); | |
6046 | ||
6047 | /* Set to true so that append_insn adds a label. */ | |
6048 | emit_branch_likely_macro = TRUE; | |
6049 | } | |
6050 | else | |
6051 | { | |
6052 | macro_build (ep, br, fmt, sreg, treg); | |
6053 | macro_build (NULL, "nop", ""); | |
6054 | } | |
6055 | end_noreorder (); | |
6056 | } | |
6057 | ||
6058 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
6059 | the condition code tested. EP specifies the branch target. */ | |
6060 | ||
6061 | static void | |
6062 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
6063 | { | |
6064 | const int call = 0; | |
6065 | const char *brneg; | |
6066 | const char *br; | |
6067 | ||
6068 | switch (type) | |
6069 | { | |
6070 | case M_BC1FL: | |
6071 | br = "bc1f"; | |
6072 | brneg = "bc1t"; | |
6073 | break; | |
6074 | case M_BC1TL: | |
6075 | br = "bc1t"; | |
6076 | brneg = "bc1f"; | |
6077 | break; | |
6078 | case M_BC2FL: | |
6079 | br = "bc2f"; | |
6080 | brneg = "bc2t"; | |
6081 | break; | |
6082 | case M_BC2TL: | |
6083 | br = "bc2t"; | |
6084 | brneg = "bc2f"; | |
6085 | break; | |
6086 | default: | |
6087 | abort (); | |
6088 | } | |
6089 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
6090 | } | |
6091 | ||
6092 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
6093 | the register tested. EP specifies the branch target. */ | |
6094 | ||
6095 | static void | |
6096 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
6097 | { | |
6098 | const char *brneg = NULL; | |
6099 | const char *br; | |
6100 | int call = 0; | |
6101 | ||
6102 | switch (type) | |
6103 | { | |
6104 | case M_BGEZ: | |
6105 | br = "bgez"; | |
6106 | break; | |
6107 | case M_BGEZL: | |
6108 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
6109 | brneg = "bltz"; | |
6110 | break; | |
6111 | case M_BGEZALL: | |
6112 | gas_assert (mips_opts.micromips); | |
6113 | br = "bgezals"; | |
6114 | brneg = "bltz"; | |
6115 | call = 1; | |
6116 | break; | |
6117 | case M_BGTZ: | |
6118 | br = "bgtz"; | |
6119 | break; | |
6120 | case M_BGTZL: | |
6121 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
6122 | brneg = "blez"; | |
6123 | break; | |
6124 | case M_BLEZ: | |
6125 | br = "blez"; | |
6126 | break; | |
6127 | case M_BLEZL: | |
6128 | br = mips_opts.micromips ? "blez" : "blezl"; | |
6129 | brneg = "bgtz"; | |
6130 | break; | |
6131 | case M_BLTZ: | |
6132 | br = "bltz"; | |
6133 | break; | |
6134 | case M_BLTZL: | |
6135 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
6136 | brneg = "bgez"; | |
6137 | break; | |
6138 | case M_BLTZALL: | |
6139 | gas_assert (mips_opts.micromips); | |
6140 | br = "bltzals"; | |
6141 | brneg = "bgez"; | |
6142 | call = 1; | |
6143 | break; | |
6144 | default: | |
6145 | abort (); | |
6146 | } | |
6147 | if (mips_opts.micromips && brneg) | |
6148 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
6149 | else | |
6150 | macro_build (ep, br, "s,p", sreg); | |
6151 | } | |
6152 | ||
6153 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
6154 | TREG as the registers tested. EP specifies the branch target. */ | |
6155 | ||
6156 | static void | |
6157 | macro_build_branch_rsrt (int type, expressionS *ep, | |
6158 | unsigned int sreg, unsigned int treg) | |
6159 | { | |
6160 | const char *brneg = NULL; | |
6161 | const int call = 0; | |
6162 | const char *br; | |
6163 | ||
6164 | switch (type) | |
6165 | { | |
6166 | case M_BEQ: | |
6167 | case M_BEQ_I: | |
6168 | br = "beq"; | |
6169 | break; | |
6170 | case M_BEQL: | |
6171 | case M_BEQL_I: | |
6172 | br = mips_opts.micromips ? "beq" : "beql"; | |
6173 | brneg = "bne"; | |
6174 | break; | |
6175 | case M_BNE: | |
6176 | case M_BNE_I: | |
6177 | br = "bne"; | |
6178 | break; | |
6179 | case M_BNEL: | |
6180 | case M_BNEL_I: | |
6181 | br = mips_opts.micromips ? "bne" : "bnel"; | |
6182 | brneg = "beq"; | |
6183 | break; | |
6184 | default: | |
6185 | abort (); | |
6186 | } | |
6187 | if (mips_opts.micromips && brneg) | |
6188 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
6189 | else | |
6190 | macro_build (ep, br, "s,t,p", sreg, treg); | |
6191 | } | |
6192 | ||
252b5132 RH |
6193 | /* |
6194 | * Build macros | |
6195 | * This routine implements the seemingly endless macro or synthesized | |
6196 | * instructions and addressing modes in the mips assembly language. Many | |
6197 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 6198 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
6199 | * this verbose method. Others are not simple macros but are more like |
6200 | * optimizing code generation. | |
6201 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 6202 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
6203 | * The ensuing load upper instructions are ommited. This implies some kind |
6204 | * of global optimization. We currently only optimize within a single macro. | |
6205 | * For many of the load and store macros if the address is specified as a | |
6206 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
6207 | * first load register 'at' with zero and use it as the base register. The | |
6208 | * mips assembler simply uses register $zero. Just one tiny optimization | |
6209 | * we're missing. | |
6210 | */ | |
6211 | static void | |
17a2f251 | 6212 | macro (struct mips_cl_insn *ip) |
252b5132 | 6213 | { |
741fe287 MR |
6214 | unsigned int treg, sreg, dreg, breg; |
6215 | unsigned int tempreg; | |
252b5132 | 6216 | int mask; |
43841e91 | 6217 | int used_at = 0; |
df58fc94 | 6218 | expressionS label_expr; |
252b5132 | 6219 | expressionS expr1; |
df58fc94 | 6220 | expressionS *ep; |
252b5132 RH |
6221 | const char *s; |
6222 | const char *s2; | |
6223 | const char *fmt; | |
6224 | int likely = 0; | |
252b5132 | 6225 | int coproc = 0; |
df58fc94 | 6226 | int off12 = 0; |
1abe91b1 | 6227 | int call = 0; |
df58fc94 RS |
6228 | int jals = 0; |
6229 | int dbl = 0; | |
6230 | int imm = 0; | |
6231 | int ust = 0; | |
6232 | int lp = 0; | |
6233 | int ab = 0; | |
252b5132 | 6234 | int off; |
67c0d1eb | 6235 | offsetT maxnum; |
252b5132 | 6236 | bfd_reloc_code_real_type r; |
252b5132 RH |
6237 | int hold_mips_optimize; |
6238 | ||
9c2799c2 | 6239 | gas_assert (! mips_opts.mips16); |
252b5132 | 6240 | |
df58fc94 RS |
6241 | treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
6242 | dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
6243 | sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
252b5132 RH |
6244 | mask = ip->insn_mo->mask; |
6245 | ||
df58fc94 RS |
6246 | label_expr.X_op = O_constant; |
6247 | label_expr.X_op_symbol = NULL; | |
6248 | label_expr.X_add_symbol = NULL; | |
6249 | label_expr.X_add_number = 0; | |
6250 | ||
252b5132 RH |
6251 | expr1.X_op = O_constant; |
6252 | expr1.X_op_symbol = NULL; | |
6253 | expr1.X_add_symbol = NULL; | |
6254 | expr1.X_add_number = 1; | |
6255 | ||
6256 | switch (mask) | |
6257 | { | |
6258 | case M_DABS: | |
6259 | dbl = 1; | |
6260 | case M_ABS: | |
df58fc94 RS |
6261 | /* bgez $a0,1f |
6262 | move v0,$a0 | |
6263 | sub v0,$zero,$a0 | |
6264 | 1: | |
6265 | */ | |
252b5132 | 6266 | |
7d10b47d | 6267 | start_noreorder (); |
252b5132 | 6268 | |
df58fc94 RS |
6269 | if (mips_opts.micromips) |
6270 | micromips_label_expr (&label_expr); | |
6271 | else | |
6272 | label_expr.X_add_number = 8; | |
6273 | macro_build (&label_expr, "bgez", "s,p", sreg); | |
252b5132 | 6274 | if (dreg == sreg) |
a605d2b3 | 6275 | macro_build (NULL, "nop", ""); |
252b5132 | 6276 | else |
67c0d1eb RS |
6277 | move_register (dreg, sreg); |
6278 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
df58fc94 RS |
6279 | if (mips_opts.micromips) |
6280 | micromips_add_label (); | |
252b5132 | 6281 | |
7d10b47d | 6282 | end_noreorder (); |
8fc2e39e | 6283 | break; |
252b5132 RH |
6284 | |
6285 | case M_ADD_I: | |
6286 | s = "addi"; | |
6287 | s2 = "add"; | |
6288 | goto do_addi; | |
6289 | case M_ADDU_I: | |
6290 | s = "addiu"; | |
6291 | s2 = "addu"; | |
6292 | goto do_addi; | |
6293 | case M_DADD_I: | |
6294 | dbl = 1; | |
6295 | s = "daddi"; | |
6296 | s2 = "dadd"; | |
df58fc94 RS |
6297 | if (!mips_opts.micromips) |
6298 | goto do_addi; | |
6299 | if (imm_expr.X_op == O_constant | |
6300 | && imm_expr.X_add_number >= -0x200 | |
6301 | && imm_expr.X_add_number < 0x200) | |
6302 | { | |
6303 | macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number); | |
6304 | break; | |
6305 | } | |
6306 | goto do_addi_i; | |
252b5132 RH |
6307 | case M_DADDU_I: |
6308 | dbl = 1; | |
6309 | s = "daddiu"; | |
6310 | s2 = "daddu"; | |
6311 | do_addi: | |
6312 | if (imm_expr.X_op == O_constant | |
6313 | && imm_expr.X_add_number >= -0x8000 | |
6314 | && imm_expr.X_add_number < 0x8000) | |
6315 | { | |
67c0d1eb | 6316 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 6317 | break; |
252b5132 | 6318 | } |
df58fc94 | 6319 | do_addi_i: |
8fc2e39e | 6320 | used_at = 1; |
67c0d1eb RS |
6321 | load_register (AT, &imm_expr, dbl); |
6322 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6323 | break; |
6324 | ||
6325 | case M_AND_I: | |
6326 | s = "andi"; | |
6327 | s2 = "and"; | |
6328 | goto do_bit; | |
6329 | case M_OR_I: | |
6330 | s = "ori"; | |
6331 | s2 = "or"; | |
6332 | goto do_bit; | |
6333 | case M_NOR_I: | |
6334 | s = ""; | |
6335 | s2 = "nor"; | |
6336 | goto do_bit; | |
6337 | case M_XOR_I: | |
6338 | s = "xori"; | |
6339 | s2 = "xor"; | |
6340 | do_bit: | |
6341 | if (imm_expr.X_op == O_constant | |
6342 | && imm_expr.X_add_number >= 0 | |
6343 | && imm_expr.X_add_number < 0x10000) | |
6344 | { | |
6345 | if (mask != M_NOR_I) | |
67c0d1eb | 6346 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
6347 | else |
6348 | { | |
67c0d1eb RS |
6349 | macro_build (&imm_expr, "ori", "t,r,i", |
6350 | treg, sreg, BFD_RELOC_LO16); | |
6351 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 6352 | } |
8fc2e39e | 6353 | break; |
252b5132 RH |
6354 | } |
6355 | ||
8fc2e39e | 6356 | used_at = 1; |
67c0d1eb RS |
6357 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
6358 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6359 | break; |
6360 | ||
8b082fb1 TS |
6361 | case M_BALIGN: |
6362 | switch (imm_expr.X_add_number) | |
6363 | { | |
6364 | case 0: | |
6365 | macro_build (NULL, "nop", ""); | |
6366 | break; | |
6367 | case 2: | |
6368 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
6369 | break; | |
6370 | default: | |
6371 | macro_build (NULL, "balign", "t,s,2", treg, sreg, | |
90ecf173 | 6372 | (int) imm_expr.X_add_number); |
8b082fb1 TS |
6373 | break; |
6374 | } | |
6375 | break; | |
6376 | ||
df58fc94 RS |
6377 | case M_BC1FL: |
6378 | case M_BC1TL: | |
6379 | case M_BC2FL: | |
6380 | case M_BC2TL: | |
6381 | gas_assert (mips_opts.micromips); | |
6382 | macro_build_branch_ccl (mask, &offset_expr, | |
6383 | EXTRACT_OPERAND (1, BCC, *ip)); | |
6384 | break; | |
6385 | ||
252b5132 | 6386 | case M_BEQ_I: |
252b5132 | 6387 | case M_BEQL_I: |
252b5132 | 6388 | case M_BNE_I: |
252b5132 | 6389 | case M_BNEL_I: |
252b5132 | 6390 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
df58fc94 RS |
6391 | treg = 0; |
6392 | else | |
252b5132 | 6393 | { |
df58fc94 RS |
6394 | treg = AT; |
6395 | used_at = 1; | |
6396 | load_register (treg, &imm_expr, HAVE_64BIT_GPRS); | |
252b5132 | 6397 | } |
df58fc94 RS |
6398 | /* Fall through. */ |
6399 | case M_BEQL: | |
6400 | case M_BNEL: | |
6401 | macro_build_branch_rsrt (mask, &offset_expr, sreg, treg); | |
252b5132 RH |
6402 | break; |
6403 | ||
6404 | case M_BGEL: | |
6405 | likely = 1; | |
6406 | case M_BGE: | |
6407 | if (treg == 0) | |
df58fc94 RS |
6408 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg); |
6409 | else if (sreg == 0) | |
6410 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg); | |
6411 | else | |
252b5132 | 6412 | { |
df58fc94 RS |
6413 | used_at = 1; |
6414 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6415 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6416 | &offset_expr, AT, ZERO); | |
252b5132 | 6417 | } |
df58fc94 RS |
6418 | break; |
6419 | ||
6420 | case M_BGEZL: | |
6421 | case M_BGEZALL: | |
6422 | case M_BGTZL: | |
6423 | case M_BLEZL: | |
6424 | case M_BLTZL: | |
6425 | case M_BLTZALL: | |
6426 | macro_build_branch_rs (mask, &offset_expr, sreg); | |
252b5132 RH |
6427 | break; |
6428 | ||
6429 | case M_BGTL_I: | |
6430 | likely = 1; | |
6431 | case M_BGT_I: | |
90ecf173 | 6432 | /* Check for > max integer. */ |
252b5132 | 6433 | maxnum = 0x7fffffff; |
ca4e0257 | 6434 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6435 | { |
6436 | maxnum <<= 16; | |
6437 | maxnum |= 0xffff; | |
6438 | maxnum <<= 16; | |
6439 | maxnum |= 0xffff; | |
6440 | } | |
6441 | if (imm_expr.X_op == O_constant | |
6442 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6443 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6444 | { |
6445 | do_false: | |
90ecf173 | 6446 | /* Result is always false. */ |
252b5132 | 6447 | if (! likely) |
a605d2b3 | 6448 | macro_build (NULL, "nop", ""); |
252b5132 | 6449 | else |
df58fc94 | 6450 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 6451 | break; |
252b5132 RH |
6452 | } |
6453 | if (imm_expr.X_op != O_constant) | |
6454 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6455 | ++imm_expr.X_add_number; |
252b5132 RH |
6456 | /* FALLTHROUGH */ |
6457 | case M_BGE_I: | |
6458 | case M_BGEL_I: | |
6459 | if (mask == M_BGEL_I) | |
6460 | likely = 1; | |
6461 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6462 | { | |
df58fc94 RS |
6463 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
6464 | &offset_expr, sreg); | |
8fc2e39e | 6465 | break; |
252b5132 RH |
6466 | } |
6467 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6468 | { | |
df58fc94 RS |
6469 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
6470 | &offset_expr, sreg); | |
8fc2e39e | 6471 | break; |
252b5132 RH |
6472 | } |
6473 | maxnum = 0x7fffffff; | |
ca4e0257 | 6474 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6475 | { |
6476 | maxnum <<= 16; | |
6477 | maxnum |= 0xffff; | |
6478 | maxnum <<= 16; | |
6479 | maxnum |= 0xffff; | |
6480 | } | |
6481 | maxnum = - maxnum - 1; | |
6482 | if (imm_expr.X_op == O_constant | |
6483 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 6484 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6485 | { |
6486 | do_true: | |
6487 | /* result is always true */ | |
6488 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 6489 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6490 | break; |
252b5132 | 6491 | } |
8fc2e39e | 6492 | used_at = 1; |
67c0d1eb | 6493 | set_at (sreg, 0); |
df58fc94 RS |
6494 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6495 | &offset_expr, AT, ZERO); | |
252b5132 RH |
6496 | break; |
6497 | ||
6498 | case M_BGEUL: | |
6499 | likely = 1; | |
6500 | case M_BGEU: | |
6501 | if (treg == 0) | |
6502 | goto do_true; | |
df58fc94 RS |
6503 | else if (sreg == 0) |
6504 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6505 | &offset_expr, ZERO, treg); | |
6506 | else | |
252b5132 | 6507 | { |
df58fc94 RS |
6508 | used_at = 1; |
6509 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6510 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6511 | &offset_expr, AT, ZERO); | |
252b5132 | 6512 | } |
252b5132 RH |
6513 | break; |
6514 | ||
6515 | case M_BGTUL_I: | |
6516 | likely = 1; | |
6517 | case M_BGTU_I: | |
6518 | if (sreg == 0 | |
ca4e0257 | 6519 | || (HAVE_32BIT_GPRS |
252b5132 | 6520 | && imm_expr.X_op == O_constant |
f01dc953 | 6521 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6522 | goto do_false; |
6523 | if (imm_expr.X_op != O_constant) | |
6524 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6525 | ++imm_expr.X_add_number; |
252b5132 RH |
6526 | /* FALLTHROUGH */ |
6527 | case M_BGEU_I: | |
6528 | case M_BGEUL_I: | |
6529 | if (mask == M_BGEUL_I) | |
6530 | likely = 1; | |
6531 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6532 | goto do_true; | |
df58fc94 RS |
6533 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6534 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6535 | &offset_expr, sreg, ZERO); | |
6536 | else | |
252b5132 | 6537 | { |
df58fc94 RS |
6538 | used_at = 1; |
6539 | set_at (sreg, 1); | |
6540 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6541 | &offset_expr, AT, ZERO); | |
252b5132 | 6542 | } |
252b5132 RH |
6543 | break; |
6544 | ||
6545 | case M_BGTL: | |
6546 | likely = 1; | |
6547 | case M_BGT: | |
6548 | if (treg == 0) | |
df58fc94 RS |
6549 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg); |
6550 | else if (sreg == 0) | |
6551 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg); | |
6552 | else | |
252b5132 | 6553 | { |
df58fc94 RS |
6554 | used_at = 1; |
6555 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6556 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6557 | &offset_expr, AT, ZERO); | |
252b5132 | 6558 | } |
252b5132 RH |
6559 | break; |
6560 | ||
6561 | case M_BGTUL: | |
6562 | likely = 1; | |
6563 | case M_BGTU: | |
6564 | if (treg == 0) | |
df58fc94 RS |
6565 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
6566 | &offset_expr, sreg, ZERO); | |
6567 | else if (sreg == 0) | |
6568 | goto do_false; | |
6569 | else | |
252b5132 | 6570 | { |
df58fc94 RS |
6571 | used_at = 1; |
6572 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6573 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6574 | &offset_expr, AT, ZERO); | |
252b5132 | 6575 | } |
252b5132 RH |
6576 | break; |
6577 | ||
6578 | case M_BLEL: | |
6579 | likely = 1; | |
6580 | case M_BLE: | |
6581 | if (treg == 0) | |
df58fc94 RS |
6582 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); |
6583 | else if (sreg == 0) | |
6584 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg); | |
6585 | else | |
252b5132 | 6586 | { |
df58fc94 RS |
6587 | used_at = 1; |
6588 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6589 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6590 | &offset_expr, AT, ZERO); | |
252b5132 | 6591 | } |
252b5132 RH |
6592 | break; |
6593 | ||
6594 | case M_BLEL_I: | |
6595 | likely = 1; | |
6596 | case M_BLE_I: | |
6597 | maxnum = 0x7fffffff; | |
ca4e0257 | 6598 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6599 | { |
6600 | maxnum <<= 16; | |
6601 | maxnum |= 0xffff; | |
6602 | maxnum <<= 16; | |
6603 | maxnum |= 0xffff; | |
6604 | } | |
6605 | if (imm_expr.X_op == O_constant | |
6606 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6607 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6608 | goto do_true; |
6609 | if (imm_expr.X_op != O_constant) | |
6610 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6611 | ++imm_expr.X_add_number; |
252b5132 RH |
6612 | /* FALLTHROUGH */ |
6613 | case M_BLT_I: | |
6614 | case M_BLTL_I: | |
6615 | if (mask == M_BLTL_I) | |
6616 | likely = 1; | |
6617 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
df58fc94 RS |
6618 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6619 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6620 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); | |
6621 | else | |
252b5132 | 6622 | { |
df58fc94 RS |
6623 | used_at = 1; |
6624 | set_at (sreg, 0); | |
6625 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6626 | &offset_expr, AT, ZERO); | |
252b5132 | 6627 | } |
252b5132 RH |
6628 | break; |
6629 | ||
6630 | case M_BLEUL: | |
6631 | likely = 1; | |
6632 | case M_BLEU: | |
6633 | if (treg == 0) | |
df58fc94 RS |
6634 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6635 | &offset_expr, sreg, ZERO); | |
6636 | else if (sreg == 0) | |
6637 | goto do_true; | |
6638 | else | |
252b5132 | 6639 | { |
df58fc94 RS |
6640 | used_at = 1; |
6641 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6642 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6643 | &offset_expr, AT, ZERO); | |
252b5132 | 6644 | } |
252b5132 RH |
6645 | break; |
6646 | ||
6647 | case M_BLEUL_I: | |
6648 | likely = 1; | |
6649 | case M_BLEU_I: | |
6650 | if (sreg == 0 | |
ca4e0257 | 6651 | || (HAVE_32BIT_GPRS |
252b5132 | 6652 | && imm_expr.X_op == O_constant |
f01dc953 | 6653 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6654 | goto do_true; |
6655 | if (imm_expr.X_op != O_constant) | |
6656 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6657 | ++imm_expr.X_add_number; |
252b5132 RH |
6658 | /* FALLTHROUGH */ |
6659 | case M_BLTU_I: | |
6660 | case M_BLTUL_I: | |
6661 | if (mask == M_BLTUL_I) | |
6662 | likely = 1; | |
6663 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6664 | goto do_false; | |
df58fc94 RS |
6665 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6666 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6667 | &offset_expr, sreg, ZERO); | |
6668 | else | |
252b5132 | 6669 | { |
df58fc94 RS |
6670 | used_at = 1; |
6671 | set_at (sreg, 1); | |
6672 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6673 | &offset_expr, AT, ZERO); | |
252b5132 | 6674 | } |
252b5132 RH |
6675 | break; |
6676 | ||
6677 | case M_BLTL: | |
6678 | likely = 1; | |
6679 | case M_BLT: | |
6680 | if (treg == 0) | |
df58fc94 RS |
6681 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6682 | else if (sreg == 0) | |
6683 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg); | |
6684 | else | |
252b5132 | 6685 | { |
df58fc94 RS |
6686 | used_at = 1; |
6687 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6688 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6689 | &offset_expr, AT, ZERO); | |
252b5132 | 6690 | } |
252b5132 RH |
6691 | break; |
6692 | ||
6693 | case M_BLTUL: | |
6694 | likely = 1; | |
6695 | case M_BLTU: | |
6696 | if (treg == 0) | |
6697 | goto do_false; | |
df58fc94 RS |
6698 | else if (sreg == 0) |
6699 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6700 | &offset_expr, ZERO, treg); | |
6701 | else | |
252b5132 | 6702 | { |
df58fc94 RS |
6703 | used_at = 1; |
6704 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6705 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6706 | &offset_expr, AT, ZERO); | |
252b5132 | 6707 | } |
252b5132 RH |
6708 | break; |
6709 | ||
5f74bc13 CD |
6710 | case M_DEXT: |
6711 | { | |
d5818fca MR |
6712 | /* Use unsigned arithmetic. */ |
6713 | addressT pos; | |
6714 | addressT size; | |
5f74bc13 | 6715 | |
90ecf173 | 6716 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6717 | { |
6718 | as_bad (_("Unsupported large constant")); | |
6719 | pos = size = 1; | |
6720 | } | |
6721 | else | |
6722 | { | |
d5818fca MR |
6723 | pos = imm_expr.X_add_number; |
6724 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
6725 | } |
6726 | ||
6727 | if (pos > 63) | |
6728 | { | |
d5818fca | 6729 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
6730 | pos = 1; |
6731 | } | |
90ecf173 | 6732 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
6733 | { |
6734 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 6735 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
6736 | size = 1; |
6737 | } | |
6738 | ||
6739 | if (size <= 32 && pos < 32) | |
6740 | { | |
6741 | s = "dext"; | |
6742 | fmt = "t,r,+A,+C"; | |
6743 | } | |
6744 | else if (size <= 32) | |
6745 | { | |
6746 | s = "dextu"; | |
6747 | fmt = "t,r,+E,+H"; | |
6748 | } | |
6749 | else | |
6750 | { | |
6751 | s = "dextm"; | |
6752 | fmt = "t,r,+A,+G"; | |
6753 | } | |
d5818fca MR |
6754 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
6755 | (int) (size - 1)); | |
5f74bc13 | 6756 | } |
8fc2e39e | 6757 | break; |
5f74bc13 CD |
6758 | |
6759 | case M_DINS: | |
6760 | { | |
d5818fca MR |
6761 | /* Use unsigned arithmetic. */ |
6762 | addressT pos; | |
6763 | addressT size; | |
5f74bc13 | 6764 | |
90ecf173 | 6765 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6766 | { |
6767 | as_bad (_("Unsupported large constant")); | |
6768 | pos = size = 1; | |
6769 | } | |
6770 | else | |
6771 | { | |
d5818fca MR |
6772 | pos = imm_expr.X_add_number; |
6773 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
6774 | } |
6775 | ||
6776 | if (pos > 63) | |
6777 | { | |
d5818fca | 6778 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
6779 | pos = 1; |
6780 | } | |
90ecf173 | 6781 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
6782 | { |
6783 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 6784 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
6785 | size = 1; |
6786 | } | |
6787 | ||
6788 | if (pos < 32 && (pos + size - 1) < 32) | |
6789 | { | |
6790 | s = "dins"; | |
6791 | fmt = "t,r,+A,+B"; | |
6792 | } | |
6793 | else if (pos >= 32) | |
6794 | { | |
6795 | s = "dinsu"; | |
6796 | fmt = "t,r,+E,+F"; | |
6797 | } | |
6798 | else | |
6799 | { | |
6800 | s = "dinsm"; | |
6801 | fmt = "t,r,+A,+F"; | |
6802 | } | |
750bdd57 AS |
6803 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
6804 | (int) (pos + size - 1)); | |
5f74bc13 | 6805 | } |
8fc2e39e | 6806 | break; |
5f74bc13 | 6807 | |
252b5132 RH |
6808 | case M_DDIV_3: |
6809 | dbl = 1; | |
6810 | case M_DIV_3: | |
6811 | s = "mflo"; | |
6812 | goto do_div3; | |
6813 | case M_DREM_3: | |
6814 | dbl = 1; | |
6815 | case M_REM_3: | |
6816 | s = "mfhi"; | |
6817 | do_div3: | |
6818 | if (treg == 0) | |
6819 | { | |
6820 | as_warn (_("Divide by zero.")); | |
6821 | if (mips_trap) | |
df58fc94 | 6822 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 6823 | else |
df58fc94 | 6824 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 6825 | break; |
252b5132 RH |
6826 | } |
6827 | ||
7d10b47d | 6828 | start_noreorder (); |
252b5132 RH |
6829 | if (mips_trap) |
6830 | { | |
df58fc94 | 6831 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 6832 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
6833 | } |
6834 | else | |
6835 | { | |
df58fc94 RS |
6836 | if (mips_opts.micromips) |
6837 | micromips_label_expr (&label_expr); | |
6838 | else | |
6839 | label_expr.X_add_number = 8; | |
6840 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 6841 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
df58fc94 RS |
6842 | macro_build (NULL, "break", BRK_FMT, 7); |
6843 | if (mips_opts.micromips) | |
6844 | micromips_add_label (); | |
252b5132 RH |
6845 | } |
6846 | expr1.X_add_number = -1; | |
8fc2e39e | 6847 | used_at = 1; |
f6a22291 | 6848 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
6849 | if (mips_opts.micromips) |
6850 | micromips_label_expr (&label_expr); | |
6851 | else | |
6852 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
6853 | macro_build (&label_expr, "bne", "s,t,p", treg, AT); | |
252b5132 RH |
6854 | if (dbl) |
6855 | { | |
6856 | expr1.X_add_number = 1; | |
f6a22291 | 6857 | load_register (AT, &expr1, dbl); |
df58fc94 | 6858 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
6859 | } |
6860 | else | |
6861 | { | |
6862 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 6863 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
6864 | } |
6865 | if (mips_trap) | |
6866 | { | |
df58fc94 | 6867 | macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6); |
252b5132 RH |
6868 | /* We want to close the noreorder block as soon as possible, so |
6869 | that later insns are available for delay slot filling. */ | |
7d10b47d | 6870 | end_noreorder (); |
252b5132 RH |
6871 | } |
6872 | else | |
6873 | { | |
df58fc94 RS |
6874 | if (mips_opts.micromips) |
6875 | micromips_label_expr (&label_expr); | |
6876 | else | |
6877 | label_expr.X_add_number = 8; | |
6878 | macro_build (&label_expr, "bne", "s,t,p", sreg, AT); | |
a605d2b3 | 6879 | macro_build (NULL, "nop", ""); |
252b5132 RH |
6880 | |
6881 | /* We want to close the noreorder block as soon as possible, so | |
6882 | that later insns are available for delay slot filling. */ | |
7d10b47d | 6883 | end_noreorder (); |
252b5132 | 6884 | |
df58fc94 | 6885 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 6886 | } |
df58fc94 RS |
6887 | if (mips_opts.micromips) |
6888 | micromips_add_label (); | |
6889 | macro_build (NULL, s, MFHL_FMT, dreg); | |
252b5132 RH |
6890 | break; |
6891 | ||
6892 | case M_DIV_3I: | |
6893 | s = "div"; | |
6894 | s2 = "mflo"; | |
6895 | goto do_divi; | |
6896 | case M_DIVU_3I: | |
6897 | s = "divu"; | |
6898 | s2 = "mflo"; | |
6899 | goto do_divi; | |
6900 | case M_REM_3I: | |
6901 | s = "div"; | |
6902 | s2 = "mfhi"; | |
6903 | goto do_divi; | |
6904 | case M_REMU_3I: | |
6905 | s = "divu"; | |
6906 | s2 = "mfhi"; | |
6907 | goto do_divi; | |
6908 | case M_DDIV_3I: | |
6909 | dbl = 1; | |
6910 | s = "ddiv"; | |
6911 | s2 = "mflo"; | |
6912 | goto do_divi; | |
6913 | case M_DDIVU_3I: | |
6914 | dbl = 1; | |
6915 | s = "ddivu"; | |
6916 | s2 = "mflo"; | |
6917 | goto do_divi; | |
6918 | case M_DREM_3I: | |
6919 | dbl = 1; | |
6920 | s = "ddiv"; | |
6921 | s2 = "mfhi"; | |
6922 | goto do_divi; | |
6923 | case M_DREMU_3I: | |
6924 | dbl = 1; | |
6925 | s = "ddivu"; | |
6926 | s2 = "mfhi"; | |
6927 | do_divi: | |
6928 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6929 | { | |
6930 | as_warn (_("Divide by zero.")); | |
6931 | if (mips_trap) | |
df58fc94 | 6932 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 6933 | else |
df58fc94 | 6934 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 6935 | break; |
252b5132 RH |
6936 | } |
6937 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6938 | { | |
6939 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 6940 | move_register (dreg, sreg); |
252b5132 | 6941 | else |
c80c840e | 6942 | move_register (dreg, ZERO); |
8fc2e39e | 6943 | break; |
252b5132 RH |
6944 | } |
6945 | if (imm_expr.X_op == O_constant | |
6946 | && imm_expr.X_add_number == -1 | |
6947 | && s[strlen (s) - 1] != 'u') | |
6948 | { | |
6949 | if (strcmp (s2, "mflo") == 0) | |
6950 | { | |
67c0d1eb | 6951 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
6952 | } |
6953 | else | |
c80c840e | 6954 | move_register (dreg, ZERO); |
8fc2e39e | 6955 | break; |
252b5132 RH |
6956 | } |
6957 | ||
8fc2e39e | 6958 | used_at = 1; |
67c0d1eb RS |
6959 | load_register (AT, &imm_expr, dbl); |
6960 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
df58fc94 | 6961 | macro_build (NULL, s2, MFHL_FMT, dreg); |
252b5132 RH |
6962 | break; |
6963 | ||
6964 | case M_DIVU_3: | |
6965 | s = "divu"; | |
6966 | s2 = "mflo"; | |
6967 | goto do_divu3; | |
6968 | case M_REMU_3: | |
6969 | s = "divu"; | |
6970 | s2 = "mfhi"; | |
6971 | goto do_divu3; | |
6972 | case M_DDIVU_3: | |
6973 | s = "ddivu"; | |
6974 | s2 = "mflo"; | |
6975 | goto do_divu3; | |
6976 | case M_DREMU_3: | |
6977 | s = "ddivu"; | |
6978 | s2 = "mfhi"; | |
6979 | do_divu3: | |
7d10b47d | 6980 | start_noreorder (); |
252b5132 RH |
6981 | if (mips_trap) |
6982 | { | |
df58fc94 | 6983 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 6984 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
6985 | /* We want to close the noreorder block as soon as possible, so |
6986 | that later insns are available for delay slot filling. */ | |
7d10b47d | 6987 | end_noreorder (); |
252b5132 RH |
6988 | } |
6989 | else | |
6990 | { | |
df58fc94 RS |
6991 | if (mips_opts.micromips) |
6992 | micromips_label_expr (&label_expr); | |
6993 | else | |
6994 | label_expr.X_add_number = 8; | |
6995 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 6996 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
6997 | |
6998 | /* We want to close the noreorder block as soon as possible, so | |
6999 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7000 | end_noreorder (); |
df58fc94 RS |
7001 | macro_build (NULL, "break", BRK_FMT, 7); |
7002 | if (mips_opts.micromips) | |
7003 | micromips_add_label (); | |
252b5132 | 7004 | } |
df58fc94 | 7005 | macro_build (NULL, s2, MFHL_FMT, dreg); |
8fc2e39e | 7006 | break; |
252b5132 | 7007 | |
1abe91b1 MR |
7008 | case M_DLCA_AB: |
7009 | dbl = 1; | |
7010 | case M_LCA_AB: | |
7011 | call = 1; | |
7012 | goto do_la; | |
252b5132 RH |
7013 | case M_DLA_AB: |
7014 | dbl = 1; | |
7015 | case M_LA_AB: | |
1abe91b1 | 7016 | do_la: |
252b5132 RH |
7017 | /* Load the address of a symbol into a register. If breg is not |
7018 | zero, we then add a base register to it. */ | |
7019 | ||
3bec30a8 TS |
7020 | if (dbl && HAVE_32BIT_GPRS) |
7021 | as_warn (_("dla used to load 32-bit register")); | |
7022 | ||
90ecf173 | 7023 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
7024 | as_warn (_("la used to load 64-bit address")); |
7025 | ||
0c11417f MR |
7026 | if (offset_expr.X_op == O_constant |
7027 | && offset_expr.X_add_number >= -0x8000 | |
7028 | && offset_expr.X_add_number < 0x8000) | |
7029 | { | |
aed1a261 | 7030 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 7031 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7032 | break; |
0c11417f MR |
7033 | } |
7034 | ||
741fe287 | 7035 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
7036 | { |
7037 | tempreg = AT; | |
7038 | used_at = 1; | |
7039 | } | |
7040 | else | |
7041 | { | |
7042 | tempreg = treg; | |
afdbd6d0 CD |
7043 | } |
7044 | ||
252b5132 RH |
7045 | if (offset_expr.X_op != O_symbol |
7046 | && offset_expr.X_op != O_constant) | |
7047 | { | |
f71d0d44 | 7048 | as_bad (_("Expression too complex")); |
252b5132 RH |
7049 | offset_expr.X_op = O_constant; |
7050 | } | |
7051 | ||
252b5132 | 7052 | if (offset_expr.X_op == O_constant) |
aed1a261 | 7053 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
7054 | else if (mips_pic == NO_PIC) |
7055 | { | |
d6bc6245 | 7056 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 7057 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
7058 | Otherwise we want |
7059 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7060 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7061 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 7062 | so we may as well always use the latter form. |
76b3015f | 7063 | |
6caf9ef4 TS |
7064 | With 64bit address space and a usable $at we want |
7065 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7066 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7067 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7068 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
7069 | dsll32 $tempreg,0 | |
7070 | daddu $tempreg,$tempreg,$at | |
7071 | ||
7072 | If $at is already in use, we use a path which is suboptimal | |
7073 | on superscalar processors. | |
7074 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7075 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7076 | dsll $tempreg,16 | |
7077 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7078 | dsll $tempreg,16 | |
7079 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
7080 | ||
7081 | For GP relative symbols in 64bit address space we can use | |
7082 | the same sequence as in 32bit address space. */ | |
aed1a261 | 7083 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 7084 | { |
6caf9ef4 TS |
7085 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
7086 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
7087 | { | |
7088 | relax_start (offset_expr.X_add_symbol); | |
7089 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7090 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
7091 | relax_switch (); | |
7092 | } | |
d6bc6245 | 7093 | |
741fe287 | 7094 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 7095 | { |
df58fc94 | 7096 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7097 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 7098 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7099 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 7100 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7101 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 7102 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7103 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 7104 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 7105 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
7106 | used_at = 1; |
7107 | } | |
7108 | else | |
7109 | { | |
df58fc94 | 7110 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7111 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 7112 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7113 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 7114 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7115 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7116 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 7117 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7118 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7119 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 7120 | } |
6caf9ef4 TS |
7121 | |
7122 | if (mips_relax.sequence) | |
7123 | relax_end (); | |
98d3f06f KH |
7124 | } |
7125 | else | |
7126 | { | |
7127 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7128 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 7129 | { |
4d7206a2 | 7130 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7131 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7132 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 7133 | relax_switch (); |
98d3f06f | 7134 | } |
6943caf0 | 7135 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 7136 | as_bad (_("Offset too large")); |
67c0d1eb RS |
7137 | macro_build_lui (&offset_expr, tempreg); |
7138 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7139 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
7140 | if (mips_relax.sequence) |
7141 | relax_end (); | |
98d3f06f | 7142 | } |
252b5132 | 7143 | } |
0a44bf69 | 7144 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 7145 | { |
9117d219 NC |
7146 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
7147 | ||
252b5132 RH |
7148 | /* If this is a reference to an external symbol, and there |
7149 | is no constant, we want | |
7150 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 7151 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 7152 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
7153 | For a local symbol, we want |
7154 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7155 | nop | |
7156 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7157 | ||
7158 | If we have a small constant, and this is a reference to | |
7159 | an external symbol, we want | |
7160 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7161 | nop | |
7162 | addiu $tempreg,$tempreg,<constant> | |
7163 | For a local symbol, we want the same instruction | |
7164 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
7165 | addiu instruction. | |
7166 | ||
7167 | If we have a large constant, and this is a reference to | |
7168 | an external symbol, we want | |
7169 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7170 | lui $at,<hiconstant> | |
7171 | addiu $at,$at,<loconstant> | |
7172 | addu $tempreg,$tempreg,$at | |
7173 | For a local symbol, we want the same instruction | |
7174 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 7175 | addiu instruction. |
ed6fb7bd SC |
7176 | */ |
7177 | ||
4d7206a2 | 7178 | if (offset_expr.X_add_number == 0) |
252b5132 | 7179 | { |
0a44bf69 RS |
7180 | if (mips_pic == SVR4_PIC |
7181 | && breg == 0 | |
7182 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
7183 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
7184 | ||
7185 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
7186 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7187 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 7188 | if (breg != 0) |
252b5132 RH |
7189 | { |
7190 | /* We're going to put in an addu instruction using | |
7191 | tempreg, so we may as well insert the nop right | |
7192 | now. */ | |
269137b2 | 7193 | load_delay_nop (); |
252b5132 | 7194 | } |
4d7206a2 | 7195 | relax_switch (); |
67c0d1eb RS |
7196 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7197 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7198 | load_delay_nop (); |
67c0d1eb RS |
7199 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7200 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 7201 | relax_end (); |
252b5132 RH |
7202 | /* FIXME: If breg == 0, and the next instruction uses |
7203 | $tempreg, then if this variant case is used an extra | |
7204 | nop will be generated. */ | |
7205 | } | |
4d7206a2 RS |
7206 | else if (offset_expr.X_add_number >= -0x8000 |
7207 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 7208 | { |
67c0d1eb | 7209 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 7210 | load_delay_nop (); |
67c0d1eb | 7211 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
7212 | } |
7213 | else | |
7214 | { | |
4d7206a2 RS |
7215 | expr1.X_add_number = offset_expr.X_add_number; |
7216 | offset_expr.X_add_number = | |
7217 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 7218 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 7219 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
7220 | /* If we are going to add in a base register, and the |
7221 | target register and the base register are the same, | |
7222 | then we are using AT as a temporary register. Since | |
7223 | we want to load the constant into AT, we add our | |
7224 | current AT (from the global offset table) and the | |
7225 | register into the register now, and pretend we were | |
7226 | not using a base register. */ | |
67c0d1eb | 7227 | if (breg == treg) |
252b5132 | 7228 | { |
269137b2 | 7229 | load_delay_nop (); |
67c0d1eb | 7230 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7231 | treg, AT, breg); |
252b5132 RH |
7232 | breg = 0; |
7233 | tempreg = treg; | |
252b5132 | 7234 | } |
f6a22291 | 7235 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
7236 | used_at = 1; |
7237 | } | |
7238 | } | |
0a44bf69 | 7239 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 7240 | { |
67c0d1eb | 7241 | int add_breg_early = 0; |
f5040a92 AO |
7242 | |
7243 | /* If this is a reference to an external, and there is no | |
7244 | constant, or local symbol (*), with or without a | |
7245 | constant, we want | |
7246 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 7247 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7248 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
7249 | ||
7250 | If we have a small constant, and this is a reference to | |
7251 | an external symbol, we want | |
7252 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7253 | addiu $tempreg,$tempreg,<constant> | |
7254 | ||
7255 | If we have a large constant, and this is a reference to | |
7256 | an external symbol, we want | |
7257 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7258 | lui $at,<hiconstant> | |
7259 | addiu $at,$at,<loconstant> | |
7260 | addu $tempreg,$tempreg,$at | |
7261 | ||
7262 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
7263 | local symbols, even though it introduces an additional | |
7264 | instruction. */ | |
7265 | ||
f5040a92 AO |
7266 | if (offset_expr.X_add_number) |
7267 | { | |
4d7206a2 | 7268 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7269 | offset_expr.X_add_number = 0; |
7270 | ||
4d7206a2 | 7271 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7272 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7273 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7274 | |
7275 | if (expr1.X_add_number >= -0x8000 | |
7276 | && expr1.X_add_number < 0x8000) | |
7277 | { | |
67c0d1eb RS |
7278 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
7279 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 7280 | } |
ecd13cd3 | 7281 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7282 | { |
f5040a92 AO |
7283 | /* If we are going to add in a base register, and the |
7284 | target register and the base register are the same, | |
7285 | then we are using AT as a temporary register. Since | |
7286 | we want to load the constant into AT, we add our | |
7287 | current AT (from the global offset table) and the | |
7288 | register into the register now, and pretend we were | |
7289 | not using a base register. */ | |
7290 | if (breg != treg) | |
7291 | dreg = tempreg; | |
7292 | else | |
7293 | { | |
9c2799c2 | 7294 | gas_assert (tempreg == AT); |
67c0d1eb RS |
7295 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
7296 | treg, AT, breg); | |
f5040a92 | 7297 | dreg = treg; |
67c0d1eb | 7298 | add_breg_early = 1; |
f5040a92 AO |
7299 | } |
7300 | ||
f6a22291 | 7301 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7302 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7303 | dreg, dreg, AT); |
f5040a92 | 7304 | |
f5040a92 AO |
7305 | used_at = 1; |
7306 | } | |
7307 | else | |
7308 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7309 | ||
4d7206a2 | 7310 | relax_switch (); |
f5040a92 AO |
7311 | offset_expr.X_add_number = expr1.X_add_number; |
7312 | ||
67c0d1eb RS |
7313 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7314 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
7315 | if (add_breg_early) | |
f5040a92 | 7316 | { |
67c0d1eb | 7317 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 7318 | treg, tempreg, breg); |
f5040a92 AO |
7319 | breg = 0; |
7320 | tempreg = treg; | |
7321 | } | |
4d7206a2 | 7322 | relax_end (); |
f5040a92 | 7323 | } |
4d7206a2 | 7324 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 7325 | { |
4d7206a2 | 7326 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7327 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7328 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 7329 | relax_switch (); |
67c0d1eb RS |
7330 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7331 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 7332 | relax_end (); |
f5040a92 | 7333 | } |
4d7206a2 | 7334 | else |
f5040a92 | 7335 | { |
67c0d1eb RS |
7336 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7337 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7338 | } |
7339 | } | |
0a44bf69 | 7340 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 7341 | { |
67c0d1eb | 7342 | int gpdelay; |
9117d219 NC |
7343 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7344 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 7345 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
7346 | |
7347 | /* This is the large GOT case. If this is a reference to an | |
7348 | external symbol, and there is no constant, we want | |
7349 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7350 | addu $tempreg,$tempreg,$gp | |
7351 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7352 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
7353 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7354 | addu $tempreg,$tempreg,$gp | |
7355 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
7356 | For a local symbol, we want |
7357 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7358 | nop | |
7359 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7360 | ||
7361 | If we have a small constant, and this is a reference to | |
7362 | an external symbol, we want | |
7363 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7364 | addu $tempreg,$tempreg,$gp | |
7365 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7366 | nop | |
7367 | addiu $tempreg,$tempreg,<constant> | |
7368 | For a local symbol, we want | |
7369 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7370 | nop | |
7371 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
7372 | ||
7373 | If we have a large constant, and this is a reference to | |
7374 | an external symbol, we want | |
7375 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7376 | addu $tempreg,$tempreg,$gp | |
7377 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7378 | lui $at,<hiconstant> | |
7379 | addiu $at,$at,<loconstant> | |
7380 | addu $tempreg,$tempreg,$at | |
7381 | For a local symbol, we want | |
7382 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7383 | lui $at,<hiconstant> | |
7384 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
7385 | addu $tempreg,$tempreg,$at | |
f5040a92 | 7386 | */ |
438c16b8 | 7387 | |
252b5132 RH |
7388 | expr1.X_add_number = offset_expr.X_add_number; |
7389 | offset_expr.X_add_number = 0; | |
4d7206a2 | 7390 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7391 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
7392 | if (expr1.X_add_number == 0 && breg == 0 |
7393 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
7394 | { |
7395 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7396 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7397 | } | |
df58fc94 | 7398 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7399 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7400 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 7401 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7402 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
7403 | if (expr1.X_add_number == 0) |
7404 | { | |
67c0d1eb | 7405 | if (breg != 0) |
252b5132 RH |
7406 | { |
7407 | /* We're going to put in an addu instruction using | |
7408 | tempreg, so we may as well insert the nop right | |
7409 | now. */ | |
269137b2 | 7410 | load_delay_nop (); |
252b5132 | 7411 | } |
252b5132 RH |
7412 | } |
7413 | else if (expr1.X_add_number >= -0x8000 | |
7414 | && expr1.X_add_number < 0x8000) | |
7415 | { | |
269137b2 | 7416 | load_delay_nop (); |
67c0d1eb | 7417 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7418 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
7419 | } |
7420 | else | |
7421 | { | |
252b5132 RH |
7422 | /* If we are going to add in a base register, and the |
7423 | target register and the base register are the same, | |
7424 | then we are using AT as a temporary register. Since | |
7425 | we want to load the constant into AT, we add our | |
7426 | current AT (from the global offset table) and the | |
7427 | register into the register now, and pretend we were | |
7428 | not using a base register. */ | |
7429 | if (breg != treg) | |
67c0d1eb | 7430 | dreg = tempreg; |
252b5132 RH |
7431 | else |
7432 | { | |
9c2799c2 | 7433 | gas_assert (tempreg == AT); |
269137b2 | 7434 | load_delay_nop (); |
67c0d1eb | 7435 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7436 | treg, AT, breg); |
252b5132 | 7437 | dreg = treg; |
252b5132 RH |
7438 | } |
7439 | ||
f6a22291 | 7440 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7441 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 7442 | |
252b5132 RH |
7443 | used_at = 1; |
7444 | } | |
4d7206a2 RS |
7445 | offset_expr.X_add_number = |
7446 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
7447 | relax_switch (); | |
252b5132 | 7448 | |
67c0d1eb | 7449 | if (gpdelay) |
252b5132 RH |
7450 | { |
7451 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 7452 | the first instruction on the main stream does not. */ |
67c0d1eb | 7453 | macro_build (NULL, "nop", ""); |
252b5132 | 7454 | } |
ed6fb7bd | 7455 | |
67c0d1eb RS |
7456 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7457 | local_reloc_type, mips_gp_register); | |
f5040a92 | 7458 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
7459 | && expr1.X_add_number < 0x8000) |
7460 | { | |
269137b2 | 7461 | load_delay_nop (); |
67c0d1eb RS |
7462 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7463 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 7464 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
7465 | register, the external symbol case ended with a load, |
7466 | so if the symbol turns out to not be external, and | |
7467 | the next instruction uses tempreg, an unnecessary nop | |
7468 | will be inserted. */ | |
252b5132 RH |
7469 | } |
7470 | else | |
7471 | { | |
7472 | if (breg == treg) | |
7473 | { | |
7474 | /* We must add in the base register now, as in the | |
f5040a92 | 7475 | external symbol case. */ |
9c2799c2 | 7476 | gas_assert (tempreg == AT); |
269137b2 | 7477 | load_delay_nop (); |
67c0d1eb | 7478 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7479 | treg, AT, breg); |
252b5132 RH |
7480 | tempreg = treg; |
7481 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 7482 | it in in both cases. */ |
252b5132 RH |
7483 | breg = 0; |
7484 | } | |
7485 | ||
67c0d1eb RS |
7486 | macro_build_lui (&expr1, AT); |
7487 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 7488 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 7489 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7490 | tempreg, tempreg, AT); |
8fc2e39e | 7491 | used_at = 1; |
252b5132 | 7492 | } |
4d7206a2 | 7493 | relax_end (); |
252b5132 | 7494 | } |
0a44bf69 | 7495 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 7496 | { |
f5040a92 AO |
7497 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7498 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 7499 | int add_breg_early = 0; |
f5040a92 AO |
7500 | |
7501 | /* This is the large GOT case. If this is a reference to an | |
7502 | external symbol, and there is no constant, we want | |
7503 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7504 | add $tempreg,$tempreg,$gp | |
7505 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7506 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7507 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7508 | add $tempreg,$tempreg,$gp | |
7509 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
7510 | ||
7511 | If we have a small constant, and this is a reference to | |
7512 | an external symbol, we want | |
7513 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7514 | add $tempreg,$tempreg,$gp | |
7515 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7516 | addi $tempreg,$tempreg,<constant> | |
7517 | ||
7518 | If we have a large constant, and this is a reference to | |
7519 | an external symbol, we want | |
7520 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7521 | addu $tempreg,$tempreg,$gp | |
7522 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7523 | lui $at,<hiconstant> | |
7524 | addi $at,$at,<loconstant> | |
7525 | add $tempreg,$tempreg,$at | |
7526 | ||
7527 | If we have NewABI, and we know it's a local symbol, we want | |
7528 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
7529 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
7530 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
7531 | ||
4d7206a2 | 7532 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 7533 | |
4d7206a2 | 7534 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7535 | offset_expr.X_add_number = 0; |
7536 | ||
1abe91b1 MR |
7537 | if (expr1.X_add_number == 0 && breg == 0 |
7538 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
7539 | { |
7540 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7541 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7542 | } | |
df58fc94 | 7543 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7544 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7545 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
7546 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7547 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
7548 | |
7549 | if (expr1.X_add_number == 0) | |
4d7206a2 | 7550 | ; |
f5040a92 AO |
7551 | else if (expr1.X_add_number >= -0x8000 |
7552 | && expr1.X_add_number < 0x8000) | |
7553 | { | |
67c0d1eb | 7554 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7555 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 7556 | } |
ecd13cd3 | 7557 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7558 | { |
f5040a92 AO |
7559 | /* If we are going to add in a base register, and the |
7560 | target register and the base register are the same, | |
7561 | then we are using AT as a temporary register. Since | |
7562 | we want to load the constant into AT, we add our | |
7563 | current AT (from the global offset table) and the | |
7564 | register into the register now, and pretend we were | |
7565 | not using a base register. */ | |
7566 | if (breg != treg) | |
7567 | dreg = tempreg; | |
7568 | else | |
7569 | { | |
9c2799c2 | 7570 | gas_assert (tempreg == AT); |
67c0d1eb | 7571 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7572 | treg, AT, breg); |
f5040a92 | 7573 | dreg = treg; |
67c0d1eb | 7574 | add_breg_early = 1; |
f5040a92 AO |
7575 | } |
7576 | ||
f6a22291 | 7577 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7578 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 7579 | |
f5040a92 AO |
7580 | used_at = 1; |
7581 | } | |
7582 | else | |
7583 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7584 | ||
4d7206a2 | 7585 | relax_switch (); |
f5040a92 | 7586 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
7587 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7588 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
7589 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
7590 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
7591 | if (add_breg_early) | |
f5040a92 | 7592 | { |
67c0d1eb | 7593 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7594 | treg, tempreg, breg); |
f5040a92 AO |
7595 | breg = 0; |
7596 | tempreg = treg; | |
7597 | } | |
4d7206a2 | 7598 | relax_end (); |
f5040a92 | 7599 | } |
252b5132 RH |
7600 | else |
7601 | abort (); | |
7602 | ||
7603 | if (breg != 0) | |
aed1a261 | 7604 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
7605 | break; |
7606 | ||
52b6b6b9 | 7607 | case M_MSGSND: |
df58fc94 | 7608 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7609 | { |
7610 | unsigned long temp = (treg << 16) | (0x01); | |
7611 | macro_build (NULL, "c2", "C", temp); | |
7612 | } | |
c7af4273 | 7613 | break; |
52b6b6b9 JM |
7614 | |
7615 | case M_MSGLD: | |
df58fc94 | 7616 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7617 | { |
7618 | unsigned long temp = (0x02); | |
7619 | macro_build (NULL, "c2", "C", temp); | |
7620 | } | |
c7af4273 | 7621 | break; |
52b6b6b9 JM |
7622 | |
7623 | case M_MSGLD_T: | |
df58fc94 | 7624 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7625 | { |
7626 | unsigned long temp = (treg << 16) | (0x02); | |
7627 | macro_build (NULL, "c2", "C", temp); | |
7628 | } | |
c7af4273 | 7629 | break; |
52b6b6b9 JM |
7630 | |
7631 | case M_MSGWAIT: | |
df58fc94 | 7632 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 7633 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 7634 | break; |
52b6b6b9 JM |
7635 | |
7636 | case M_MSGWAIT_T: | |
df58fc94 | 7637 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7638 | { |
7639 | unsigned long temp = (treg << 16) | 0x03; | |
7640 | macro_build (NULL, "c2", "C", temp); | |
7641 | } | |
c7af4273 | 7642 | break; |
52b6b6b9 | 7643 | |
252b5132 RH |
7644 | case M_J_A: |
7645 | /* The j instruction may not be used in PIC code, since it | |
7646 | requires an absolute address. We convert it to a b | |
7647 | instruction. */ | |
7648 | if (mips_pic == NO_PIC) | |
67c0d1eb | 7649 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 7650 | else |
67c0d1eb | 7651 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 7652 | break; |
252b5132 RH |
7653 | |
7654 | /* The jal instructions must be handled as macros because when | |
7655 | generating PIC code they expand to multi-instruction | |
7656 | sequences. Normally they are simple instructions. */ | |
df58fc94 RS |
7657 | case M_JALS_1: |
7658 | dreg = RA; | |
7659 | /* Fall through. */ | |
7660 | case M_JALS_2: | |
7661 | gas_assert (mips_opts.micromips); | |
7662 | jals = 1; | |
7663 | goto jal; | |
252b5132 RH |
7664 | case M_JAL_1: |
7665 | dreg = RA; | |
7666 | /* Fall through. */ | |
7667 | case M_JAL_2: | |
df58fc94 | 7668 | jal: |
3e722fb5 | 7669 | if (mips_pic == NO_PIC) |
df58fc94 RS |
7670 | { |
7671 | s = jals ? "jalrs" : "jalr"; | |
7672 | if (mips_opts.micromips && dreg == RA) | |
7673 | macro_build (NULL, s, "mj", sreg); | |
7674 | else | |
7675 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
7676 | } | |
0a44bf69 | 7677 | else |
252b5132 | 7678 | { |
df58fc94 RS |
7679 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
7680 | && mips_cprestore_offset >= 0); | |
7681 | ||
252b5132 RH |
7682 | if (sreg != PIC_CALL_REG) |
7683 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 7684 | |
df58fc94 RS |
7685 | s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore) |
7686 | ? "jalrs" : "jalr"); | |
7687 | if (mips_opts.micromips && dreg == RA) | |
7688 | macro_build (NULL, s, "mj", sreg); | |
7689 | else | |
7690 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
0a44bf69 | 7691 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 7692 | { |
6478892d TS |
7693 | if (mips_cprestore_offset < 0) |
7694 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7695 | else | |
7696 | { | |
90ecf173 | 7697 | if (!mips_frame_reg_valid) |
7a621144 DJ |
7698 | { |
7699 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
7700 | /* Quiet this warning. */ | |
7701 | mips_frame_reg_valid = 1; | |
7702 | } | |
90ecf173 | 7703 | if (!mips_cprestore_valid) |
7a621144 DJ |
7704 | { |
7705 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7706 | /* Quiet this warning. */ | |
7707 | mips_cprestore_valid = 1; | |
7708 | } | |
d3fca0b5 MR |
7709 | if (mips_opts.noreorder) |
7710 | macro_build (NULL, "nop", ""); | |
6478892d | 7711 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 7712 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 7713 | mips_gp_register, |
256ab948 TS |
7714 | mips_frame_reg, |
7715 | HAVE_64BIT_ADDRESSES); | |
6478892d | 7716 | } |
252b5132 RH |
7717 | } |
7718 | } | |
252b5132 | 7719 | |
8fc2e39e | 7720 | break; |
252b5132 | 7721 | |
df58fc94 RS |
7722 | case M_JALS_A: |
7723 | gas_assert (mips_opts.micromips); | |
7724 | jals = 1; | |
7725 | /* Fall through. */ | |
252b5132 RH |
7726 | case M_JAL_A: |
7727 | if (mips_pic == NO_PIC) | |
df58fc94 | 7728 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
7729 | else if (mips_pic == SVR4_PIC) |
7730 | { | |
7731 | /* If this is a reference to an external symbol, and we are | |
7732 | using a small GOT, we want | |
7733 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
7734 | nop | |
f9419b05 | 7735 | jalr $ra,$25 |
252b5132 RH |
7736 | nop |
7737 | lw $gp,cprestore($sp) | |
7738 | The cprestore value is set using the .cprestore | |
7739 | pseudo-op. If we are using a big GOT, we want | |
7740 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
7741 | addu $25,$25,$gp | |
7742 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
7743 | nop | |
f9419b05 | 7744 | jalr $ra,$25 |
252b5132 RH |
7745 | nop |
7746 | lw $gp,cprestore($sp) | |
7747 | If the symbol is not external, we want | |
7748 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7749 | nop | |
7750 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 7751 | jalr $ra,$25 |
252b5132 | 7752 | nop |
438c16b8 | 7753 | lw $gp,cprestore($sp) |
f5040a92 AO |
7754 | |
7755 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
7756 | sequences above, minus nops, unless the symbol is local, | |
7757 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
7758 | GOT_DISP. */ | |
438c16b8 | 7759 | if (HAVE_NEWABI) |
252b5132 | 7760 | { |
90ecf173 | 7761 | if (!mips_big_got) |
f5040a92 | 7762 | { |
4d7206a2 | 7763 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7764 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7765 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 7766 | mips_gp_register); |
4d7206a2 | 7767 | relax_switch (); |
67c0d1eb RS |
7768 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7769 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
7770 | mips_gp_register); |
7771 | relax_end (); | |
f5040a92 AO |
7772 | } |
7773 | else | |
7774 | { | |
4d7206a2 | 7775 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 7776 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
7777 | BFD_RELOC_MIPS_CALL_HI16); |
7778 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
7779 | PIC_CALL_REG, mips_gp_register); | |
7780 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
7781 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
7782 | PIC_CALL_REG); | |
4d7206a2 | 7783 | relax_switch (); |
67c0d1eb RS |
7784 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7785 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
7786 | mips_gp_register); | |
7787 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7788 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 7789 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 7790 | relax_end (); |
f5040a92 | 7791 | } |
684022ea | 7792 | |
df58fc94 | 7793 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
7794 | } |
7795 | else | |
7796 | { | |
4d7206a2 | 7797 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 7798 | if (!mips_big_got) |
438c16b8 | 7799 | { |
67c0d1eb RS |
7800 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7801 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 7802 | mips_gp_register); |
269137b2 | 7803 | load_delay_nop (); |
4d7206a2 | 7804 | relax_switch (); |
438c16b8 | 7805 | } |
252b5132 | 7806 | else |
252b5132 | 7807 | { |
67c0d1eb RS |
7808 | int gpdelay; |
7809 | ||
7810 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 7811 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
7812 | BFD_RELOC_MIPS_CALL_HI16); |
7813 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
7814 | PIC_CALL_REG, mips_gp_register); | |
7815 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
7816 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
7817 | PIC_CALL_REG); | |
269137b2 | 7818 | load_delay_nop (); |
4d7206a2 | 7819 | relax_switch (); |
67c0d1eb RS |
7820 | if (gpdelay) |
7821 | macro_build (NULL, "nop", ""); | |
252b5132 | 7822 | } |
67c0d1eb RS |
7823 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7824 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 7825 | mips_gp_register); |
269137b2 | 7826 | load_delay_nop (); |
67c0d1eb RS |
7827 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7828 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 7829 | relax_end (); |
df58fc94 | 7830 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 7831 | |
6478892d TS |
7832 | if (mips_cprestore_offset < 0) |
7833 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7834 | else | |
7835 | { | |
90ecf173 | 7836 | if (!mips_frame_reg_valid) |
7a621144 DJ |
7837 | { |
7838 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
7839 | /* Quiet this warning. */ | |
7840 | mips_frame_reg_valid = 1; | |
7841 | } | |
90ecf173 | 7842 | if (!mips_cprestore_valid) |
7a621144 DJ |
7843 | { |
7844 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7845 | /* Quiet this warning. */ | |
7846 | mips_cprestore_valid = 1; | |
7847 | } | |
6478892d | 7848 | if (mips_opts.noreorder) |
67c0d1eb | 7849 | macro_build (NULL, "nop", ""); |
6478892d | 7850 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 7851 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 7852 | mips_gp_register, |
256ab948 TS |
7853 | mips_frame_reg, |
7854 | HAVE_64BIT_ADDRESSES); | |
6478892d | 7855 | } |
252b5132 RH |
7856 | } |
7857 | } | |
0a44bf69 RS |
7858 | else if (mips_pic == VXWORKS_PIC) |
7859 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
7860 | else |
7861 | abort (); | |
7862 | ||
8fc2e39e | 7863 | break; |
252b5132 RH |
7864 | |
7865 | case M_LB_AB: | |
df58fc94 | 7866 | ab = 1; |
252b5132 | 7867 | s = "lb"; |
df58fc94 | 7868 | fmt = "t,o(b)"; |
252b5132 RH |
7869 | goto ld; |
7870 | case M_LBU_AB: | |
df58fc94 | 7871 | ab = 1; |
252b5132 | 7872 | s = "lbu"; |
df58fc94 | 7873 | fmt = "t,o(b)"; |
252b5132 RH |
7874 | goto ld; |
7875 | case M_LH_AB: | |
df58fc94 | 7876 | ab = 1; |
252b5132 | 7877 | s = "lh"; |
df58fc94 | 7878 | fmt = "t,o(b)"; |
252b5132 RH |
7879 | goto ld; |
7880 | case M_LHU_AB: | |
df58fc94 | 7881 | ab = 1; |
252b5132 | 7882 | s = "lhu"; |
df58fc94 | 7883 | fmt = "t,o(b)"; |
252b5132 RH |
7884 | goto ld; |
7885 | case M_LW_AB: | |
df58fc94 | 7886 | ab = 1; |
252b5132 | 7887 | s = "lw"; |
df58fc94 | 7888 | fmt = "t,o(b)"; |
252b5132 RH |
7889 | goto ld; |
7890 | case M_LWC0_AB: | |
df58fc94 RS |
7891 | ab = 1; |
7892 | gas_assert (!mips_opts.micromips); | |
252b5132 | 7893 | s = "lwc0"; |
df58fc94 | 7894 | fmt = "E,o(b)"; |
bdaaa2e1 | 7895 | /* Itbl support may require additional care here. */ |
252b5132 | 7896 | coproc = 1; |
df58fc94 | 7897 | goto ld_st; |
252b5132 | 7898 | case M_LWC1_AB: |
df58fc94 | 7899 | ab = 1; |
252b5132 | 7900 | s = "lwc1"; |
df58fc94 | 7901 | fmt = "T,o(b)"; |
bdaaa2e1 | 7902 | /* Itbl support may require additional care here. */ |
252b5132 | 7903 | coproc = 1; |
df58fc94 | 7904 | goto ld_st; |
252b5132 | 7905 | case M_LWC2_AB: |
df58fc94 RS |
7906 | ab = 1; |
7907 | case M_LWC2_OB: | |
252b5132 | 7908 | s = "lwc2"; |
df58fc94 RS |
7909 | fmt = COP12_FMT; |
7910 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 7911 | /* Itbl support may require additional care here. */ |
252b5132 | 7912 | coproc = 1; |
df58fc94 | 7913 | goto ld_st; |
252b5132 | 7914 | case M_LWC3_AB: |
df58fc94 RS |
7915 | ab = 1; |
7916 | gas_assert (!mips_opts.micromips); | |
252b5132 | 7917 | s = "lwc3"; |
df58fc94 | 7918 | fmt = "E,o(b)"; |
bdaaa2e1 | 7919 | /* Itbl support may require additional care here. */ |
252b5132 | 7920 | coproc = 1; |
df58fc94 | 7921 | goto ld_st; |
252b5132 | 7922 | case M_LWL_AB: |
df58fc94 RS |
7923 | ab = 1; |
7924 | case M_LWL_OB: | |
252b5132 | 7925 | s = "lwl"; |
df58fc94 RS |
7926 | fmt = MEM12_FMT; |
7927 | off12 = mips_opts.micromips; | |
7928 | goto ld_st; | |
252b5132 | 7929 | case M_LWR_AB: |
df58fc94 RS |
7930 | ab = 1; |
7931 | case M_LWR_OB: | |
252b5132 | 7932 | s = "lwr"; |
df58fc94 RS |
7933 | fmt = MEM12_FMT; |
7934 | off12 = mips_opts.micromips; | |
7935 | goto ld_st; | |
252b5132 | 7936 | case M_LDC1_AB: |
df58fc94 | 7937 | ab = 1; |
252b5132 | 7938 | s = "ldc1"; |
df58fc94 | 7939 | fmt = "T,o(b)"; |
bdaaa2e1 | 7940 | /* Itbl support may require additional care here. */ |
252b5132 | 7941 | coproc = 1; |
df58fc94 | 7942 | goto ld_st; |
252b5132 | 7943 | case M_LDC2_AB: |
df58fc94 RS |
7944 | ab = 1; |
7945 | case M_LDC2_OB: | |
252b5132 | 7946 | s = "ldc2"; |
df58fc94 RS |
7947 | fmt = COP12_FMT; |
7948 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 7949 | /* Itbl support may require additional care here. */ |
252b5132 | 7950 | coproc = 1; |
df58fc94 | 7951 | goto ld_st; |
252b5132 | 7952 | case M_LDC3_AB: |
df58fc94 | 7953 | ab = 1; |
252b5132 | 7954 | s = "ldc3"; |
df58fc94 | 7955 | fmt = "E,o(b)"; |
bdaaa2e1 | 7956 | /* Itbl support may require additional care here. */ |
252b5132 | 7957 | coproc = 1; |
df58fc94 | 7958 | goto ld_st; |
252b5132 | 7959 | case M_LDL_AB: |
df58fc94 RS |
7960 | ab = 1; |
7961 | case M_LDL_OB: | |
252b5132 | 7962 | s = "ldl"; |
df58fc94 RS |
7963 | fmt = MEM12_FMT; |
7964 | off12 = mips_opts.micromips; | |
7965 | goto ld_st; | |
252b5132 | 7966 | case M_LDR_AB: |
df58fc94 RS |
7967 | ab = 1; |
7968 | case M_LDR_OB: | |
252b5132 | 7969 | s = "ldr"; |
df58fc94 RS |
7970 | fmt = MEM12_FMT; |
7971 | off12 = mips_opts.micromips; | |
7972 | goto ld_st; | |
252b5132 | 7973 | case M_LL_AB: |
df58fc94 RS |
7974 | ab = 1; |
7975 | case M_LL_OB: | |
252b5132 | 7976 | s = "ll"; |
df58fc94 RS |
7977 | fmt = MEM12_FMT; |
7978 | off12 = mips_opts.micromips; | |
252b5132 RH |
7979 | goto ld; |
7980 | case M_LLD_AB: | |
df58fc94 RS |
7981 | ab = 1; |
7982 | case M_LLD_OB: | |
252b5132 | 7983 | s = "lld"; |
df58fc94 RS |
7984 | fmt = MEM12_FMT; |
7985 | off12 = mips_opts.micromips; | |
252b5132 RH |
7986 | goto ld; |
7987 | case M_LWU_AB: | |
df58fc94 RS |
7988 | ab = 1; |
7989 | case M_LWU_OB: | |
252b5132 | 7990 | s = "lwu"; |
df58fc94 RS |
7991 | fmt = MEM12_FMT; |
7992 | off12 = mips_opts.micromips; | |
7993 | goto ld; | |
7994 | case M_LWP_AB: | |
7995 | ab = 1; | |
7996 | case M_LWP_OB: | |
7997 | gas_assert (mips_opts.micromips); | |
7998 | s = "lwp"; | |
7999 | fmt = "t,~(b)"; | |
8000 | off12 = 1; | |
8001 | lp = 1; | |
8002 | goto ld; | |
8003 | case M_LDP_AB: | |
8004 | ab = 1; | |
8005 | case M_LDP_OB: | |
8006 | gas_assert (mips_opts.micromips); | |
8007 | s = "ldp"; | |
8008 | fmt = "t,~(b)"; | |
8009 | off12 = 1; | |
8010 | lp = 1; | |
8011 | goto ld; | |
8012 | case M_LWM_AB: | |
8013 | ab = 1; | |
8014 | case M_LWM_OB: | |
8015 | gas_assert (mips_opts.micromips); | |
8016 | s = "lwm"; | |
8017 | fmt = "n,~(b)"; | |
8018 | off12 = 1; | |
8019 | goto ld_st; | |
8020 | case M_LDM_AB: | |
8021 | ab = 1; | |
8022 | case M_LDM_OB: | |
8023 | gas_assert (mips_opts.micromips); | |
8024 | s = "ldm"; | |
8025 | fmt = "n,~(b)"; | |
8026 | off12 = 1; | |
8027 | goto ld_st; | |
8028 | ||
252b5132 | 8029 | ld: |
df58fc94 RS |
8030 | if (breg == treg + lp) |
8031 | goto ld_st; | |
252b5132 | 8032 | else |
df58fc94 RS |
8033 | tempreg = treg + lp; |
8034 | goto ld_noat; | |
8035 | ||
252b5132 | 8036 | case M_SB_AB: |
df58fc94 | 8037 | ab = 1; |
252b5132 | 8038 | s = "sb"; |
df58fc94 RS |
8039 | fmt = "t,o(b)"; |
8040 | goto ld_st; | |
252b5132 | 8041 | case M_SH_AB: |
df58fc94 | 8042 | ab = 1; |
252b5132 | 8043 | s = "sh"; |
df58fc94 RS |
8044 | fmt = "t,o(b)"; |
8045 | goto ld_st; | |
252b5132 | 8046 | case M_SW_AB: |
df58fc94 | 8047 | ab = 1; |
252b5132 | 8048 | s = "sw"; |
df58fc94 RS |
8049 | fmt = "t,o(b)"; |
8050 | goto ld_st; | |
252b5132 | 8051 | case M_SWC0_AB: |
df58fc94 RS |
8052 | ab = 1; |
8053 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8054 | s = "swc0"; |
df58fc94 | 8055 | fmt = "E,o(b)"; |
bdaaa2e1 | 8056 | /* Itbl support may require additional care here. */ |
252b5132 | 8057 | coproc = 1; |
df58fc94 | 8058 | goto ld_st; |
252b5132 | 8059 | case M_SWC1_AB: |
df58fc94 | 8060 | ab = 1; |
252b5132 | 8061 | s = "swc1"; |
df58fc94 | 8062 | fmt = "T,o(b)"; |
bdaaa2e1 | 8063 | /* Itbl support may require additional care here. */ |
252b5132 | 8064 | coproc = 1; |
df58fc94 | 8065 | goto ld_st; |
252b5132 | 8066 | case M_SWC2_AB: |
df58fc94 RS |
8067 | ab = 1; |
8068 | case M_SWC2_OB: | |
252b5132 | 8069 | s = "swc2"; |
df58fc94 RS |
8070 | fmt = COP12_FMT; |
8071 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8072 | /* Itbl support may require additional care here. */ |
252b5132 | 8073 | coproc = 1; |
df58fc94 | 8074 | goto ld_st; |
252b5132 | 8075 | case M_SWC3_AB: |
df58fc94 RS |
8076 | ab = 1; |
8077 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8078 | s = "swc3"; |
df58fc94 | 8079 | fmt = "E,o(b)"; |
bdaaa2e1 | 8080 | /* Itbl support may require additional care here. */ |
252b5132 | 8081 | coproc = 1; |
df58fc94 | 8082 | goto ld_st; |
252b5132 | 8083 | case M_SWL_AB: |
df58fc94 RS |
8084 | ab = 1; |
8085 | case M_SWL_OB: | |
252b5132 | 8086 | s = "swl"; |
df58fc94 RS |
8087 | fmt = MEM12_FMT; |
8088 | off12 = mips_opts.micromips; | |
8089 | goto ld_st; | |
252b5132 | 8090 | case M_SWR_AB: |
df58fc94 RS |
8091 | ab = 1; |
8092 | case M_SWR_OB: | |
252b5132 | 8093 | s = "swr"; |
df58fc94 RS |
8094 | fmt = MEM12_FMT; |
8095 | off12 = mips_opts.micromips; | |
8096 | goto ld_st; | |
252b5132 | 8097 | case M_SC_AB: |
df58fc94 RS |
8098 | ab = 1; |
8099 | case M_SC_OB: | |
252b5132 | 8100 | s = "sc"; |
df58fc94 RS |
8101 | fmt = MEM12_FMT; |
8102 | off12 = mips_opts.micromips; | |
8103 | goto ld_st; | |
252b5132 | 8104 | case M_SCD_AB: |
df58fc94 RS |
8105 | ab = 1; |
8106 | case M_SCD_OB: | |
252b5132 | 8107 | s = "scd"; |
df58fc94 RS |
8108 | fmt = MEM12_FMT; |
8109 | off12 = mips_opts.micromips; | |
8110 | goto ld_st; | |
d43b4baf | 8111 | case M_CACHE_AB: |
df58fc94 RS |
8112 | ab = 1; |
8113 | case M_CACHE_OB: | |
d43b4baf | 8114 | s = "cache"; |
df58fc94 RS |
8115 | fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)"; |
8116 | off12 = mips_opts.micromips; | |
8117 | goto ld_st; | |
3eebd5eb | 8118 | case M_PREF_AB: |
df58fc94 RS |
8119 | ab = 1; |
8120 | case M_PREF_OB: | |
3eebd5eb | 8121 | s = "pref"; |
df58fc94 RS |
8122 | fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)"; |
8123 | off12 = mips_opts.micromips; | |
8124 | goto ld_st; | |
252b5132 | 8125 | case M_SDC1_AB: |
df58fc94 | 8126 | ab = 1; |
252b5132 | 8127 | s = "sdc1"; |
df58fc94 | 8128 | fmt = "T,o(b)"; |
252b5132 | 8129 | coproc = 1; |
bdaaa2e1 | 8130 | /* Itbl support may require additional care here. */ |
df58fc94 | 8131 | goto ld_st; |
252b5132 | 8132 | case M_SDC2_AB: |
df58fc94 RS |
8133 | ab = 1; |
8134 | case M_SDC2_OB: | |
252b5132 | 8135 | s = "sdc2"; |
df58fc94 RS |
8136 | fmt = COP12_FMT; |
8137 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8138 | /* Itbl support may require additional care here. */ |
252b5132 | 8139 | coproc = 1; |
df58fc94 | 8140 | goto ld_st; |
252b5132 | 8141 | case M_SDC3_AB: |
df58fc94 RS |
8142 | ab = 1; |
8143 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8144 | s = "sdc3"; |
df58fc94 | 8145 | fmt = "E,o(b)"; |
bdaaa2e1 | 8146 | /* Itbl support may require additional care here. */ |
252b5132 | 8147 | coproc = 1; |
df58fc94 | 8148 | goto ld_st; |
252b5132 | 8149 | case M_SDL_AB: |
df58fc94 RS |
8150 | ab = 1; |
8151 | case M_SDL_OB: | |
252b5132 | 8152 | s = "sdl"; |
df58fc94 RS |
8153 | fmt = MEM12_FMT; |
8154 | off12 = mips_opts.micromips; | |
8155 | goto ld_st; | |
252b5132 | 8156 | case M_SDR_AB: |
df58fc94 RS |
8157 | ab = 1; |
8158 | case M_SDR_OB: | |
252b5132 | 8159 | s = "sdr"; |
df58fc94 RS |
8160 | fmt = MEM12_FMT; |
8161 | off12 = mips_opts.micromips; | |
8162 | goto ld_st; | |
8163 | case M_SWP_AB: | |
8164 | ab = 1; | |
8165 | case M_SWP_OB: | |
8166 | gas_assert (mips_opts.micromips); | |
8167 | s = "swp"; | |
8168 | fmt = "t,~(b)"; | |
8169 | off12 = 1; | |
8170 | goto ld_st; | |
8171 | case M_SDP_AB: | |
8172 | ab = 1; | |
8173 | case M_SDP_OB: | |
8174 | gas_assert (mips_opts.micromips); | |
8175 | s = "sdp"; | |
8176 | fmt = "t,~(b)"; | |
8177 | off12 = 1; | |
8178 | goto ld_st; | |
8179 | case M_SWM_AB: | |
8180 | ab = 1; | |
8181 | case M_SWM_OB: | |
8182 | gas_assert (mips_opts.micromips); | |
8183 | s = "swm"; | |
8184 | fmt = "n,~(b)"; | |
8185 | off12 = 1; | |
8186 | goto ld_st; | |
8187 | case M_SDM_AB: | |
8188 | ab = 1; | |
8189 | case M_SDM_OB: | |
8190 | gas_assert (mips_opts.micromips); | |
8191 | s = "sdm"; | |
8192 | fmt = "n,~(b)"; | |
8193 | off12 = 1; | |
8194 | ||
8195 | ld_st: | |
8fc2e39e TS |
8196 | tempreg = AT; |
8197 | used_at = 1; | |
df58fc94 | 8198 | ld_noat: |
b19e8a9b AN |
8199 | if (coproc |
8200 | && NO_ISA_COP (mips_opts.arch) | |
8201 | && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0) | |
8202 | { | |
f71d0d44 | 8203 | as_bad (_("Opcode not supported on this processor: %s"), |
b19e8a9b AN |
8204 | mips_cpu_info_from_arch (mips_opts.arch)->name); |
8205 | break; | |
8206 | } | |
8207 | ||
252b5132 RH |
8208 | if (offset_expr.X_op != O_constant |
8209 | && offset_expr.X_op != O_symbol) | |
8210 | { | |
f71d0d44 | 8211 | as_bad (_("Expression too complex")); |
252b5132 RH |
8212 | offset_expr.X_op = O_constant; |
8213 | } | |
8214 | ||
2051e8c4 MR |
8215 | if (HAVE_32BIT_ADDRESSES |
8216 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8217 | { |
8218 | char value [32]; | |
8219 | ||
8220 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8221 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8222 | } |
2051e8c4 | 8223 | |
252b5132 RH |
8224 | /* A constant expression in PIC code can be handled just as it |
8225 | is in non PIC code. */ | |
aed1a261 RS |
8226 | if (offset_expr.X_op == O_constant) |
8227 | { | |
df58fc94 RS |
8228 | int hipart = 0; |
8229 | ||
842f8b2a | 8230 | expr1.X_add_number = offset_expr.X_add_number; |
2051e8c4 | 8231 | normalize_address_expr (&expr1); |
df58fc94 | 8232 | if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number)) |
842f8b2a MR |
8233 | { |
8234 | expr1.X_add_number = ((expr1.X_add_number + 0x8000) | |
8235 | & ~(bfd_vma) 0xffff); | |
df58fc94 RS |
8236 | hipart = 1; |
8237 | } | |
8238 | else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number)) | |
8239 | { | |
8240 | expr1.X_add_number = ((expr1.X_add_number + 0x800) | |
8241 | & ~(bfd_vma) 0xfff); | |
8242 | hipart = 1; | |
8243 | } | |
8244 | if (hipart) | |
8245 | { | |
842f8b2a MR |
8246 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
8247 | if (breg != 0) | |
8248 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8249 | tempreg, tempreg, breg); | |
8250 | breg = tempreg; | |
8251 | } | |
df58fc94 RS |
8252 | if (!off12) |
8253 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg); | |
8254 | else | |
8255 | macro_build (NULL, s, fmt, | |
8256 | treg, (unsigned long) offset_expr.X_add_number, breg); | |
8257 | } | |
8258 | else if (off12) | |
8259 | { | |
8260 | /* A 12-bit offset field is too narrow to be used for a low-part | |
8261 | relocation, so load the whole address into the auxillary | |
8262 | register. In the case of "A(b)" addresses, we first load | |
8263 | absolute address "A" into the register and then add base | |
8264 | register "b". In the case of "o(b)" addresses, we simply | |
8265 | need to add 16-bit offset "o" to base register "b", and | |
8266 | offset_reloc already contains the relocations associated | |
8267 | with "o". */ | |
8268 | if (ab) | |
8269 | { | |
8270 | load_address (tempreg, &offset_expr, &used_at); | |
8271 | if (breg != 0) | |
8272 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8273 | tempreg, tempreg, breg); | |
8274 | } | |
8275 | else | |
8276 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8277 | tempreg, breg, -1, | |
8278 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
8279 | expr1.X_add_number = 0; | |
8280 | macro_build (NULL, s, fmt, | |
8281 | treg, (unsigned long) expr1.X_add_number, tempreg); | |
aed1a261 RS |
8282 | } |
8283 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
8284 | { |
8285 | /* If this is a reference to a GP relative symbol, and there | |
8286 | is no base register, we want | |
cdf6fd85 | 8287 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
8288 | Otherwise, if there is no base register, we want |
8289 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8290 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8291 | If we have a constant, we need two instructions anyhow, | |
8292 | so we always use the latter form. | |
8293 | ||
8294 | If we have a base register, and this is a reference to a | |
8295 | GP relative symbol, we want | |
8296 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 8297 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
8298 | Otherwise we want |
8299 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8300 | addu $tempreg,$tempreg,$breg | |
8301 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 8302 | With a constant we always use the latter case. |
76b3015f | 8303 | |
d6bc6245 TS |
8304 | With 64bit address space and no base register and $at usable, |
8305 | we want | |
8306 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8307 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8308 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8309 | dsll32 $tempreg,0 | |
8310 | daddu $tempreg,$at | |
8311 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8312 | If we have a base register, we want | |
8313 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8314 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8315 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8316 | daddu $at,$breg | |
8317 | dsll32 $tempreg,0 | |
8318 | daddu $tempreg,$at | |
8319 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8320 | ||
8321 | Without $at we can't generate the optimal path for superscalar | |
8322 | processors here since this would require two temporary registers. | |
8323 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8324 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8325 | dsll $tempreg,16 | |
8326 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8327 | dsll $tempreg,16 | |
8328 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8329 | If we have a base register, we want | |
8330 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8331 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8332 | dsll $tempreg,16 | |
8333 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8334 | dsll $tempreg,16 | |
8335 | daddu $tempreg,$tempreg,$breg | |
8336 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 8337 | |
6caf9ef4 | 8338 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
8339 | the same sequence as in 32bit address space. */ |
8340 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 8341 | { |
aed1a261 | 8342 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
8343 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
8344 | { | |
8345 | relax_start (offset_expr.X_add_symbol); | |
8346 | if (breg == 0) | |
8347 | { | |
8348 | macro_build (&offset_expr, s, fmt, treg, | |
8349 | BFD_RELOC_GPREL16, mips_gp_register); | |
8350 | } | |
8351 | else | |
8352 | { | |
8353 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8354 | tempreg, breg, mips_gp_register); | |
8355 | macro_build (&offset_expr, s, fmt, treg, | |
8356 | BFD_RELOC_GPREL16, tempreg); | |
8357 | } | |
8358 | relax_switch (); | |
8359 | } | |
d6bc6245 | 8360 | |
741fe287 | 8361 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 8362 | { |
df58fc94 | 8363 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 8364 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 8365 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
8366 | BFD_RELOC_HI16_S); |
8367 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8368 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 8369 | if (breg != 0) |
67c0d1eb | 8370 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 8371 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb RS |
8372 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
8373 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
8374 | tempreg); | |
d6bc6245 TS |
8375 | used_at = 1; |
8376 | } | |
8377 | else | |
8378 | { | |
df58fc94 | 8379 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
8380 | BFD_RELOC_MIPS_HIGHEST); |
8381 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8382 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 8383 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
8384 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
8385 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 8386 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 8387 | if (breg != 0) |
67c0d1eb | 8388 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 8389 | tempreg, tempreg, breg); |
67c0d1eb | 8390 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8391 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 8392 | } |
6caf9ef4 TS |
8393 | |
8394 | if (mips_relax.sequence) | |
8395 | relax_end (); | |
8fc2e39e | 8396 | break; |
d6bc6245 | 8397 | } |
256ab948 | 8398 | |
252b5132 RH |
8399 | if (breg == 0) |
8400 | { | |
67c0d1eb | 8401 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8402 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8403 | { |
4d7206a2 | 8404 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8405 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
8406 | mips_gp_register); | |
4d7206a2 | 8407 | relax_switch (); |
252b5132 | 8408 | } |
67c0d1eb RS |
8409 | macro_build_lui (&offset_expr, tempreg); |
8410 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 8411 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8412 | if (mips_relax.sequence) |
8413 | relax_end (); | |
252b5132 RH |
8414 | } |
8415 | else | |
8416 | { | |
67c0d1eb | 8417 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8418 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8419 | { |
4d7206a2 | 8420 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 8421 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8422 | tempreg, breg, mips_gp_register); |
67c0d1eb | 8423 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8424 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 8425 | relax_switch (); |
252b5132 | 8426 | } |
67c0d1eb RS |
8427 | macro_build_lui (&offset_expr, tempreg); |
8428 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 8429 | tempreg, tempreg, breg); |
67c0d1eb | 8430 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8431 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8432 | if (mips_relax.sequence) |
8433 | relax_end (); | |
252b5132 RH |
8434 | } |
8435 | } | |
0a44bf69 | 8436 | else if (!mips_big_got) |
252b5132 | 8437 | { |
ed6fb7bd | 8438 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 8439 | |
252b5132 RH |
8440 | /* If this is a reference to an external symbol, we want |
8441 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8442 | nop | |
8443 | <op> $treg,0($tempreg) | |
8444 | Otherwise we want | |
8445 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8446 | nop | |
8447 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8448 | <op> $treg,0($tempreg) | |
f5040a92 AO |
8449 | |
8450 | For NewABI, we want | |
8451 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8452 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
8453 | ||
252b5132 RH |
8454 | If there is a base register, we add it to $tempreg before |
8455 | the <op>. If there is a constant, we stick it in the | |
8456 | <op> instruction. We don't handle constants larger than | |
8457 | 16 bits, because we have no way to load the upper 16 bits | |
8458 | (actually, we could handle them for the subset of cases | |
8459 | in which we are not using $at). */ | |
9c2799c2 | 8460 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
8461 | if (HAVE_NEWABI) |
8462 | { | |
67c0d1eb RS |
8463 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8464 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8465 | if (breg != 0) |
67c0d1eb | 8466 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8467 | tempreg, tempreg, breg); |
67c0d1eb | 8468 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8469 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
8470 | break; |
8471 | } | |
252b5132 RH |
8472 | expr1.X_add_number = offset_expr.X_add_number; |
8473 | offset_expr.X_add_number = 0; | |
8474 | if (expr1.X_add_number < -0x8000 | |
8475 | || expr1.X_add_number >= 0x8000) | |
8476 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
8477 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8478 | lw_reloc_type, mips_gp_register); | |
269137b2 | 8479 | load_delay_nop (); |
4d7206a2 RS |
8480 | relax_start (offset_expr.X_add_symbol); |
8481 | relax_switch (); | |
67c0d1eb RS |
8482 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8483 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 8484 | relax_end (); |
252b5132 | 8485 | if (breg != 0) |
67c0d1eb | 8486 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8487 | tempreg, tempreg, breg); |
67c0d1eb | 8488 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8489 | } |
0a44bf69 | 8490 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 8491 | { |
67c0d1eb | 8492 | int gpdelay; |
252b5132 RH |
8493 | |
8494 | /* If this is a reference to an external symbol, we want | |
8495 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8496 | addu $tempreg,$tempreg,$gp | |
8497 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8498 | <op> $treg,0($tempreg) | |
8499 | Otherwise we want | |
8500 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8501 | nop | |
8502 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8503 | <op> $treg,0($tempreg) | |
8504 | If there is a base register, we add it to $tempreg before | |
8505 | the <op>. If there is a constant, we stick it in the | |
8506 | <op> instruction. We don't handle constants larger than | |
8507 | 16 bits, because we have no way to load the upper 16 bits | |
8508 | (actually, we could handle them for the subset of cases | |
f5040a92 | 8509 | in which we are not using $at). */ |
9c2799c2 | 8510 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
8511 | expr1.X_add_number = offset_expr.X_add_number; |
8512 | offset_expr.X_add_number = 0; | |
8513 | if (expr1.X_add_number < -0x8000 | |
8514 | || expr1.X_add_number >= 0x8000) | |
8515 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 8516 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 8517 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8518 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8519 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8520 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8521 | mips_gp_register); | |
8522 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8523 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 8524 | relax_switch (); |
67c0d1eb RS |
8525 | if (gpdelay) |
8526 | macro_build (NULL, "nop", ""); | |
8527 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8528 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 8529 | load_delay_nop (); |
67c0d1eb RS |
8530 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8531 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
8532 | relax_end (); |
8533 | ||
252b5132 | 8534 | if (breg != 0) |
67c0d1eb | 8535 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8536 | tempreg, tempreg, breg); |
67c0d1eb | 8537 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8538 | } |
0a44bf69 | 8539 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 8540 | { |
f5040a92 AO |
8541 | /* If this is a reference to an external symbol, we want |
8542 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8543 | add $tempreg,$tempreg,$gp | |
8544 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8545 | <op> $treg,<ofst>($tempreg) | |
8546 | Otherwise, for local symbols, we want: | |
8547 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8548 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 8549 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 8550 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
8551 | offset_expr.X_add_number = 0; |
8552 | if (expr1.X_add_number < -0x8000 | |
8553 | || expr1.X_add_number >= 0x8000) | |
8554 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 8555 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8556 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8557 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8558 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8559 | mips_gp_register); | |
8560 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8561 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 8562 | if (breg != 0) |
67c0d1eb | 8563 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8564 | tempreg, tempreg, breg); |
67c0d1eb | 8565 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 8566 | |
4d7206a2 | 8567 | relax_switch (); |
f5040a92 | 8568 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
8569 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8570 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8571 | if (breg != 0) |
67c0d1eb | 8572 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8573 | tempreg, tempreg, breg); |
67c0d1eb | 8574 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8575 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 8576 | relax_end (); |
f5040a92 | 8577 | } |
252b5132 RH |
8578 | else |
8579 | abort (); | |
8580 | ||
252b5132 RH |
8581 | break; |
8582 | ||
8583 | case M_LI: | |
8584 | case M_LI_S: | |
67c0d1eb | 8585 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 8586 | break; |
252b5132 RH |
8587 | |
8588 | case M_DLI: | |
67c0d1eb | 8589 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 8590 | break; |
252b5132 RH |
8591 | |
8592 | case M_LI_SS: | |
8593 | if (imm_expr.X_op == O_constant) | |
8594 | { | |
8fc2e39e | 8595 | used_at = 1; |
67c0d1eb RS |
8596 | load_register (AT, &imm_expr, 0); |
8597 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8598 | break; |
8599 | } | |
8600 | else | |
8601 | { | |
9c2799c2 | 8602 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
8603 | && strcmp (segment_name (S_GET_SEGMENT |
8604 | (offset_expr.X_add_symbol)), | |
8605 | ".lit4") == 0 | |
8606 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 8607 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 8608 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8609 | break; |
252b5132 RH |
8610 | } |
8611 | ||
8612 | case M_LI_D: | |
ca4e0257 RS |
8613 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
8614 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
8615 | order 32 bits of the value and the low order 32 bits are either | |
8616 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
8617 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8618 | { | |
ca4e0257 | 8619 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 8620 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
8621 | else |
8622 | { | |
8623 | int hreg, lreg; | |
8624 | ||
8625 | if (target_big_endian) | |
8626 | { | |
8627 | hreg = treg; | |
8628 | lreg = treg + 1; | |
8629 | } | |
8630 | else | |
8631 | { | |
8632 | hreg = treg + 1; | |
8633 | lreg = treg; | |
8634 | } | |
8635 | ||
8636 | if (hreg <= 31) | |
67c0d1eb | 8637 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
8638 | if (lreg <= 31) |
8639 | { | |
8640 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 8641 | move_register (lreg, 0); |
252b5132 RH |
8642 | else |
8643 | { | |
9c2799c2 | 8644 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 8645 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
8646 | } |
8647 | } | |
8648 | } | |
8fc2e39e | 8649 | break; |
252b5132 RH |
8650 | } |
8651 | ||
8652 | /* We know that sym is in the .rdata section. First we get the | |
8653 | upper 16 bits of the address. */ | |
8654 | if (mips_pic == NO_PIC) | |
8655 | { | |
67c0d1eb | 8656 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 8657 | used_at = 1; |
252b5132 | 8658 | } |
0a44bf69 | 8659 | else |
252b5132 | 8660 | { |
67c0d1eb RS |
8661 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
8662 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 8663 | used_at = 1; |
252b5132 | 8664 | } |
bdaaa2e1 | 8665 | |
252b5132 | 8666 | /* Now we load the register(s). */ |
ca4e0257 | 8667 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
8668 | { |
8669 | used_at = 1; | |
8670 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
8671 | } | |
252b5132 RH |
8672 | else |
8673 | { | |
8fc2e39e | 8674 | used_at = 1; |
67c0d1eb | 8675 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 8676 | if (treg != RA) |
252b5132 RH |
8677 | { |
8678 | /* FIXME: How in the world do we deal with the possible | |
8679 | overflow here? */ | |
8680 | offset_expr.X_add_number += 4; | |
67c0d1eb | 8681 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 8682 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
8683 | } |
8684 | } | |
252b5132 RH |
8685 | break; |
8686 | ||
8687 | case M_LI_DD: | |
ca4e0257 RS |
8688 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
8689 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
8690 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
8691 | the value and the low order 32 bits are either zero or in | |
8692 | OFFSET_EXPR. */ | |
252b5132 RH |
8693 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8694 | { | |
8fc2e39e | 8695 | used_at = 1; |
67c0d1eb | 8696 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
8697 | if (HAVE_64BIT_FPRS) |
8698 | { | |
9c2799c2 | 8699 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 8700 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 8701 | } |
252b5132 RH |
8702 | else |
8703 | { | |
67c0d1eb | 8704 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 8705 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 8706 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
8707 | else |
8708 | { | |
9c2799c2 | 8709 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
8710 | load_register (AT, &offset_expr, 0); |
8711 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8712 | } |
8713 | } | |
8714 | break; | |
8715 | } | |
8716 | ||
9c2799c2 | 8717 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 8718 | && offset_expr.X_add_number == 0); |
252b5132 RH |
8719 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
8720 | if (strcmp (s, ".lit8") == 0) | |
8721 | { | |
df58fc94 | 8722 | if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips) |
252b5132 | 8723 | { |
67c0d1eb | 8724 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 8725 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8726 | break; |
252b5132 | 8727 | } |
c9914766 | 8728 | breg = mips_gp_register; |
252b5132 RH |
8729 | r = BFD_RELOC_MIPS_LITERAL; |
8730 | goto dob; | |
8731 | } | |
8732 | else | |
8733 | { | |
9c2799c2 | 8734 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 8735 | used_at = 1; |
0a44bf69 | 8736 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
8737 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
8738 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
8739 | else |
8740 | { | |
8741 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 8742 | macro_build_lui (&offset_expr, AT); |
252b5132 | 8743 | } |
bdaaa2e1 | 8744 | |
df58fc94 | 8745 | if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips) |
252b5132 | 8746 | { |
67c0d1eb RS |
8747 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
8748 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
8749 | break; |
8750 | } | |
8751 | breg = AT; | |
8752 | r = BFD_RELOC_LO16; | |
8753 | goto dob; | |
8754 | } | |
8755 | ||
8756 | case M_L_DOB: | |
252b5132 RH |
8757 | /* Even on a big endian machine $fn comes before $fn+1. We have |
8758 | to adjust when loading from memory. */ | |
8759 | r = BFD_RELOC_LO16; | |
8760 | dob: | |
df58fc94 | 8761 | gas_assert (!mips_opts.micromips); |
9c2799c2 | 8762 | gas_assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 8763 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 8764 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
8765 | /* FIXME: A possible overflow which I don't know how to deal |
8766 | with. */ | |
8767 | offset_expr.X_add_number += 4; | |
67c0d1eb | 8768 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 8769 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
8770 | break; |
8771 | ||
c4a68bea | 8772 | case M_S_DOB: |
df58fc94 | 8773 | gas_assert (!mips_opts.micromips); |
c4a68bea MR |
8774 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8775 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
8776 | to adjust when storing to memory. */ | |
8777 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
8778 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
8779 | offset_expr.X_add_number += 4; | |
8780 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
8781 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8782 | break; | |
8783 | ||
252b5132 | 8784 | case M_L_DAB: |
df58fc94 | 8785 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
8786 | /* |
8787 | * The MIPS assembler seems to check for X_add_number not | |
8788 | * being double aligned and generating: | |
8789 | * lui at,%hi(foo+1) | |
8790 | * addu at,at,v1 | |
8791 | * addiu at,at,%lo(foo+1) | |
8792 | * lwc1 f2,0(at) | |
8793 | * lwc1 f3,4(at) | |
8794 | * But, the resulting address is the same after relocation so why | |
8795 | * generate the extra instruction? | |
8796 | */ | |
bdaaa2e1 | 8797 | /* Itbl support may require additional care here. */ |
252b5132 | 8798 | coproc = 1; |
df58fc94 | 8799 | fmt = "T,o(b)"; |
e7af610e | 8800 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
8801 | { |
8802 | s = "ldc1"; | |
df58fc94 | 8803 | goto ld_st; |
252b5132 | 8804 | } |
252b5132 | 8805 | s = "lwc1"; |
252b5132 RH |
8806 | goto ldd_std; |
8807 | ||
8808 | case M_S_DAB: | |
df58fc94 RS |
8809 | gas_assert (!mips_opts.micromips); |
8810 | /* Itbl support may require additional care here. */ | |
8811 | coproc = 1; | |
8812 | fmt = "T,o(b)"; | |
e7af610e | 8813 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
8814 | { |
8815 | s = "sdc1"; | |
df58fc94 | 8816 | goto ld_st; |
252b5132 | 8817 | } |
252b5132 | 8818 | s = "swc1"; |
252b5132 RH |
8819 | goto ldd_std; |
8820 | ||
8821 | case M_LD_AB: | |
df58fc94 | 8822 | fmt = "t,o(b)"; |
ca4e0257 | 8823 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
8824 | { |
8825 | s = "ld"; | |
8826 | goto ld; | |
8827 | } | |
252b5132 | 8828 | s = "lw"; |
252b5132 RH |
8829 | goto ldd_std; |
8830 | ||
8831 | case M_SD_AB: | |
df58fc94 | 8832 | fmt = "t,o(b)"; |
ca4e0257 | 8833 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
8834 | { |
8835 | s = "sd"; | |
df58fc94 | 8836 | goto ld_st; |
252b5132 | 8837 | } |
252b5132 | 8838 | s = "sw"; |
252b5132 RH |
8839 | |
8840 | ldd_std: | |
8841 | if (offset_expr.X_op != O_symbol | |
8842 | && offset_expr.X_op != O_constant) | |
8843 | { | |
f71d0d44 | 8844 | as_bad (_("Expression too complex")); |
252b5132 RH |
8845 | offset_expr.X_op = O_constant; |
8846 | } | |
8847 | ||
2051e8c4 MR |
8848 | if (HAVE_32BIT_ADDRESSES |
8849 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8850 | { |
8851 | char value [32]; | |
8852 | ||
8853 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8854 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8855 | } |
2051e8c4 | 8856 | |
252b5132 RH |
8857 | /* Even on a big endian machine $fn comes before $fn+1. We have |
8858 | to adjust when loading from memory. We set coproc if we must | |
8859 | load $fn+1 first. */ | |
bdaaa2e1 | 8860 | /* Itbl support may require additional care here. */ |
90ecf173 | 8861 | if (!target_big_endian) |
252b5132 RH |
8862 | coproc = 0; |
8863 | ||
90ecf173 | 8864 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
8865 | { |
8866 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
8867 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
8868 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
8869 | If we have a base register, we use this |
8870 | addu $at,$breg,$gp | |
cdf6fd85 TS |
8871 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
8872 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
8873 | If this is not a GP relative symbol, we want |
8874 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8875 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
8876 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
8877 | If there is a base register, we add it to $at after the | |
8878 | lui instruction. If there is a constant, we always use | |
8879 | the last case. */ | |
39a59cf8 MR |
8880 | if (offset_expr.X_op == O_symbol |
8881 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 8882 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8883 | { |
4d7206a2 | 8884 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
8885 | if (breg == 0) |
8886 | { | |
c9914766 | 8887 | tempreg = mips_gp_register; |
252b5132 RH |
8888 | } |
8889 | else | |
8890 | { | |
67c0d1eb | 8891 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8892 | AT, breg, mips_gp_register); |
252b5132 | 8893 | tempreg = AT; |
252b5132 RH |
8894 | used_at = 1; |
8895 | } | |
8896 | ||
beae10d5 | 8897 | /* Itbl support may require additional care here. */ |
67c0d1eb | 8898 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 8899 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
8900 | offset_expr.X_add_number += 4; |
8901 | ||
8902 | /* Set mips_optimize to 2 to avoid inserting an | |
8903 | undesired nop. */ | |
8904 | hold_mips_optimize = mips_optimize; | |
8905 | mips_optimize = 2; | |
beae10d5 | 8906 | /* Itbl support may require additional care here. */ |
67c0d1eb | 8907 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 8908 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
8909 | mips_optimize = hold_mips_optimize; |
8910 | ||
4d7206a2 | 8911 | relax_switch (); |
252b5132 | 8912 | |
0970e49e | 8913 | offset_expr.X_add_number -= 4; |
252b5132 | 8914 | } |
8fc2e39e | 8915 | used_at = 1; |
67c0d1eb | 8916 | macro_build_lui (&offset_expr, AT); |
252b5132 | 8917 | if (breg != 0) |
67c0d1eb | 8918 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 8919 | /* Itbl support may require additional care here. */ |
67c0d1eb | 8920 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 8921 | BFD_RELOC_LO16, AT); |
252b5132 RH |
8922 | /* FIXME: How do we handle overflow here? */ |
8923 | offset_expr.X_add_number += 4; | |
beae10d5 | 8924 | /* Itbl support may require additional care here. */ |
67c0d1eb | 8925 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 8926 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
8927 | if (mips_relax.sequence) |
8928 | relax_end (); | |
bdaaa2e1 | 8929 | } |
0a44bf69 | 8930 | else if (!mips_big_got) |
252b5132 | 8931 | { |
252b5132 RH |
8932 | /* If this is a reference to an external symbol, we want |
8933 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8934 | nop | |
8935 | <op> $treg,0($at) | |
8936 | <op> $treg+1,4($at) | |
8937 | Otherwise we want | |
8938 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8939 | nop | |
8940 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
8941 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
8942 | If there is a base register we add it to $at before the | |
8943 | lwc1 instructions. If there is a constant we include it | |
8944 | in the lwc1 instructions. */ | |
8945 | used_at = 1; | |
8946 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
8947 | if (expr1.X_add_number < -0x8000 |
8948 | || expr1.X_add_number >= 0x8000 - 4) | |
8949 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 8950 | load_got_offset (AT, &offset_expr); |
269137b2 | 8951 | load_delay_nop (); |
252b5132 | 8952 | if (breg != 0) |
67c0d1eb | 8953 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
8954 | |
8955 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
8956 | nop. */ | |
8957 | hold_mips_optimize = mips_optimize; | |
8958 | mips_optimize = 2; | |
4d7206a2 | 8959 | |
beae10d5 | 8960 | /* Itbl support may require additional care here. */ |
4d7206a2 | 8961 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8962 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
8963 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 8964 | expr1.X_add_number += 4; |
67c0d1eb RS |
8965 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
8966 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 8967 | relax_switch (); |
67c0d1eb RS |
8968 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
8969 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 8970 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
8971 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
8972 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 8973 | relax_end (); |
252b5132 | 8974 | |
4d7206a2 | 8975 | mips_optimize = hold_mips_optimize; |
252b5132 | 8976 | } |
0a44bf69 | 8977 | else if (mips_big_got) |
252b5132 | 8978 | { |
67c0d1eb | 8979 | int gpdelay; |
252b5132 RH |
8980 | |
8981 | /* If this is a reference to an external symbol, we want | |
8982 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8983 | addu $at,$at,$gp | |
8984 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
8985 | nop | |
8986 | <op> $treg,0($at) | |
8987 | <op> $treg+1,4($at) | |
8988 | Otherwise we want | |
8989 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8990 | nop | |
8991 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
8992 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
8993 | If there is a base register we add it to $at before the | |
8994 | lwc1 instructions. If there is a constant we include it | |
8995 | in the lwc1 instructions. */ | |
8996 | used_at = 1; | |
8997 | expr1.X_add_number = offset_expr.X_add_number; | |
8998 | offset_expr.X_add_number = 0; | |
8999 | if (expr1.X_add_number < -0x8000 | |
9000 | || expr1.X_add_number >= 0x8000 - 4) | |
9001 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9002 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9003 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9004 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
9005 | AT, BFD_RELOC_MIPS_GOT_HI16); |
9006 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 9007 | AT, AT, mips_gp_register); |
67c0d1eb | 9008 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 9009 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 9010 | load_delay_nop (); |
252b5132 | 9011 | if (breg != 0) |
67c0d1eb | 9012 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9013 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9014 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9015 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9016 | expr1.X_add_number += 4; |
9017 | ||
9018 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9019 | nop. */ | |
9020 | hold_mips_optimize = mips_optimize; | |
9021 | mips_optimize = 2; | |
beae10d5 | 9022 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9023 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9024 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9025 | mips_optimize = hold_mips_optimize; |
9026 | expr1.X_add_number -= 4; | |
9027 | ||
4d7206a2 RS |
9028 | relax_switch (); |
9029 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
9030 | if (gpdelay) |
9031 | macro_build (NULL, "nop", ""); | |
9032 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
9033 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9034 | load_delay_nop (); |
252b5132 | 9035 | if (breg != 0) |
67c0d1eb | 9036 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9037 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9038 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9039 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9040 | offset_expr.X_add_number += 4; |
252b5132 RH |
9041 | |
9042 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9043 | nop. */ | |
9044 | hold_mips_optimize = mips_optimize; | |
9045 | mips_optimize = 2; | |
beae10d5 | 9046 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9047 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9048 | BFD_RELOC_LO16, AT); | |
252b5132 | 9049 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 9050 | relax_end (); |
252b5132 | 9051 | } |
252b5132 RH |
9052 | else |
9053 | abort (); | |
9054 | ||
252b5132 RH |
9055 | break; |
9056 | ||
9057 | case M_LD_OB: | |
704897fb | 9058 | s = HAVE_64BIT_GPRS ? "ld" : "lw"; |
252b5132 RH |
9059 | goto sd_ob; |
9060 | case M_SD_OB: | |
704897fb | 9061 | s = HAVE_64BIT_GPRS ? "sd" : "sw"; |
252b5132 | 9062 | sd_ob: |
4614d845 MR |
9063 | macro_build (&offset_expr, s, "t,o(b)", treg, |
9064 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
9065 | breg); | |
704897fb MR |
9066 | if (!HAVE_64BIT_GPRS) |
9067 | { | |
9068 | offset_expr.X_add_number += 4; | |
9069 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, | |
4614d845 MR |
9070 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], |
9071 | breg); | |
704897fb | 9072 | } |
8fc2e39e | 9073 | break; |
252b5132 RH |
9074 | |
9075 | /* New code added to support COPZ instructions. | |
9076 | This code builds table entries out of the macros in mip_opcodes. | |
9077 | R4000 uses interlocks to handle coproc delays. | |
9078 | Other chips (like the R3000) require nops to be inserted for delays. | |
9079 | ||
f72c8c98 | 9080 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
9081 | In order to fill delay slots for non-interlocked chips, |
9082 | we must have a way to specify delays based on the coprocessor. | |
9083 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
9084 | What are the side-effects of the cop instruction? | |
9085 | What cache support might we have and what are its effects? | |
9086 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 9087 | What registers are read/set/modified? |
252b5132 RH |
9088 | |
9089 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 9090 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
9091 | |
9092 | case M_COP0: | |
9093 | s = "c0"; | |
9094 | goto copz; | |
9095 | case M_COP1: | |
9096 | s = "c1"; | |
9097 | goto copz; | |
9098 | case M_COP2: | |
9099 | s = "c2"; | |
9100 | goto copz; | |
9101 | case M_COP3: | |
9102 | s = "c3"; | |
9103 | copz: | |
df58fc94 | 9104 | gas_assert (!mips_opts.micromips); |
b19e8a9b AN |
9105 | if (NO_ISA_COP (mips_opts.arch) |
9106 | && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0) | |
9107 | { | |
9108 | as_bad (_("opcode not supported on this processor: %s"), | |
9109 | mips_cpu_info_from_arch (mips_opts.arch)->name); | |
9110 | break; | |
9111 | } | |
9112 | ||
252b5132 RH |
9113 | /* For now we just do C (same as Cz). The parameter will be |
9114 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 9115 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 9116 | break; |
252b5132 | 9117 | |
ea1fb5dc | 9118 | case M_MOVE: |
67c0d1eb | 9119 | move_register (dreg, sreg); |
8fc2e39e | 9120 | break; |
ea1fb5dc | 9121 | |
252b5132 RH |
9122 | case M_DMUL: |
9123 | dbl = 1; | |
9124 | case M_MUL: | |
67c0d1eb | 9125 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
df58fc94 | 9126 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
8fc2e39e | 9127 | break; |
252b5132 RH |
9128 | |
9129 | case M_DMUL_I: | |
9130 | dbl = 1; | |
9131 | case M_MUL_I: | |
9132 | /* The MIPS assembler some times generates shifts and adds. I'm | |
9133 | not trying to be that fancy. GCC should do this for us | |
9134 | anyway. */ | |
8fc2e39e | 9135 | used_at = 1; |
67c0d1eb RS |
9136 | load_register (AT, &imm_expr, dbl); |
9137 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
df58fc94 | 9138 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9139 | break; |
9140 | ||
9141 | case M_DMULO_I: | |
9142 | dbl = 1; | |
9143 | case M_MULO_I: | |
9144 | imm = 1; | |
9145 | goto do_mulo; | |
9146 | ||
9147 | case M_DMULO: | |
9148 | dbl = 1; | |
9149 | case M_MULO: | |
9150 | do_mulo: | |
7d10b47d | 9151 | start_noreorder (); |
8fc2e39e | 9152 | used_at = 1; |
252b5132 | 9153 | if (imm) |
67c0d1eb RS |
9154 | load_register (AT, &imm_expr, dbl); |
9155 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
df58fc94 RS |
9156 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
9157 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA); | |
9158 | macro_build (NULL, "mfhi", MFHL_FMT, AT); | |
252b5132 | 9159 | if (mips_trap) |
df58fc94 | 9160 | macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6); |
252b5132 RH |
9161 | else |
9162 | { | |
df58fc94 RS |
9163 | if (mips_opts.micromips) |
9164 | micromips_label_expr (&label_expr); | |
9165 | else | |
9166 | label_expr.X_add_number = 8; | |
9167 | macro_build (&label_expr, "beq", "s,t,p", dreg, AT); | |
a605d2b3 | 9168 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9169 | macro_build (NULL, "break", BRK_FMT, 6); |
9170 | if (mips_opts.micromips) | |
9171 | micromips_add_label (); | |
252b5132 | 9172 | } |
7d10b47d | 9173 | end_noreorder (); |
df58fc94 | 9174 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9175 | break; |
9176 | ||
9177 | case M_DMULOU_I: | |
9178 | dbl = 1; | |
9179 | case M_MULOU_I: | |
9180 | imm = 1; | |
9181 | goto do_mulou; | |
9182 | ||
9183 | case M_DMULOU: | |
9184 | dbl = 1; | |
9185 | case M_MULOU: | |
9186 | do_mulou: | |
7d10b47d | 9187 | start_noreorder (); |
8fc2e39e | 9188 | used_at = 1; |
252b5132 | 9189 | if (imm) |
67c0d1eb RS |
9190 | load_register (AT, &imm_expr, dbl); |
9191 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 9192 | sreg, imm ? AT : treg); |
df58fc94 RS |
9193 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
9194 | macro_build (NULL, "mflo", MFHL_FMT, dreg); | |
252b5132 | 9195 | if (mips_trap) |
df58fc94 | 9196 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
9197 | else |
9198 | { | |
df58fc94 RS |
9199 | if (mips_opts.micromips) |
9200 | micromips_label_expr (&label_expr); | |
9201 | else | |
9202 | label_expr.X_add_number = 8; | |
9203 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 9204 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9205 | macro_build (NULL, "break", BRK_FMT, 6); |
9206 | if (mips_opts.micromips) | |
9207 | micromips_add_label (); | |
252b5132 | 9208 | } |
7d10b47d | 9209 | end_noreorder (); |
252b5132 RH |
9210 | break; |
9211 | ||
771c7ce4 | 9212 | case M_DROL: |
fef14a42 | 9213 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9214 | { |
9215 | if (dreg == sreg) | |
9216 | { | |
9217 | tempreg = AT; | |
9218 | used_at = 1; | |
9219 | } | |
9220 | else | |
9221 | { | |
9222 | tempreg = dreg; | |
82dd0097 | 9223 | } |
67c0d1eb RS |
9224 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
9225 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9226 | break; |
82dd0097 | 9227 | } |
8fc2e39e | 9228 | used_at = 1; |
c80c840e | 9229 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9230 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
9231 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
9232 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
9233 | break; |
9234 | ||
252b5132 | 9235 | case M_ROL: |
fef14a42 | 9236 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
9237 | { |
9238 | if (dreg == sreg) | |
9239 | { | |
9240 | tempreg = AT; | |
9241 | used_at = 1; | |
9242 | } | |
9243 | else | |
9244 | { | |
9245 | tempreg = dreg; | |
82dd0097 | 9246 | } |
67c0d1eb RS |
9247 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
9248 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9249 | break; |
82dd0097 | 9250 | } |
8fc2e39e | 9251 | used_at = 1; |
c80c840e | 9252 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9253 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
9254 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
9255 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9256 | break; |
9257 | ||
771c7ce4 TS |
9258 | case M_DROL_I: |
9259 | { | |
9260 | unsigned int rot; | |
91d6fa6a NC |
9261 | char *l; |
9262 | char *rr; | |
771c7ce4 TS |
9263 | |
9264 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9265 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9266 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9267 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
9268 | { |
9269 | rot = (64 - rot) & 0x3f; | |
9270 | if (rot >= 32) | |
df58fc94 | 9271 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
60b63b72 | 9272 | else |
df58fc94 | 9273 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9274 | break; |
60b63b72 | 9275 | } |
483fc7cd | 9276 | if (rot == 0) |
483fc7cd | 9277 | { |
df58fc94 | 9278 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9279 | break; |
483fc7cd | 9280 | } |
82dd0097 | 9281 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 9282 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 9283 | rot &= 0x1f; |
8fc2e39e | 9284 | used_at = 1; |
df58fc94 RS |
9285 | macro_build (NULL, l, SHFT_FMT, AT, sreg, rot); |
9286 | macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9287 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9288 | } |
9289 | break; | |
9290 | ||
252b5132 | 9291 | case M_ROL_I: |
771c7ce4 TS |
9292 | { |
9293 | unsigned int rot; | |
9294 | ||
9295 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9296 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9297 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9298 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 9299 | { |
df58fc94 | 9300 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 9301 | break; |
60b63b72 | 9302 | } |
483fc7cd | 9303 | if (rot == 0) |
483fc7cd | 9304 | { |
df58fc94 | 9305 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9306 | break; |
483fc7cd | 9307 | } |
8fc2e39e | 9308 | used_at = 1; |
df58fc94 RS |
9309 | macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot); |
9310 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9311 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9312 | } |
9313 | break; | |
9314 | ||
9315 | case M_DROR: | |
fef14a42 | 9316 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 9317 | { |
67c0d1eb | 9318 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9319 | break; |
82dd0097 | 9320 | } |
8fc2e39e | 9321 | used_at = 1; |
c80c840e | 9322 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9323 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
9324 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
9325 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9326 | break; |
9327 | ||
9328 | case M_ROR: | |
fef14a42 | 9329 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9330 | { |
67c0d1eb | 9331 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9332 | break; |
82dd0097 | 9333 | } |
8fc2e39e | 9334 | used_at = 1; |
c80c840e | 9335 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9336 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
9337 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
9338 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9339 | break; |
9340 | ||
771c7ce4 TS |
9341 | case M_DROR_I: |
9342 | { | |
9343 | unsigned int rot; | |
91d6fa6a NC |
9344 | char *l; |
9345 | char *rr; | |
771c7ce4 TS |
9346 | |
9347 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9348 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9349 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9350 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9351 | { |
9352 | if (rot >= 32) | |
df58fc94 | 9353 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
82dd0097 | 9354 | else |
df58fc94 | 9355 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9356 | break; |
82dd0097 | 9357 | } |
483fc7cd | 9358 | if (rot == 0) |
483fc7cd | 9359 | { |
df58fc94 | 9360 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9361 | break; |
483fc7cd | 9362 | } |
91d6fa6a | 9363 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
9364 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
9365 | rot &= 0x1f; | |
8fc2e39e | 9366 | used_at = 1; |
df58fc94 RS |
9367 | macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot); |
9368 | macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9369 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9370 | } |
9371 | break; | |
9372 | ||
252b5132 | 9373 | case M_ROR_I: |
771c7ce4 TS |
9374 | { |
9375 | unsigned int rot; | |
9376 | ||
9377 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9378 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9379 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9380 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9381 | { |
df58fc94 | 9382 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9383 | break; |
82dd0097 | 9384 | } |
483fc7cd | 9385 | if (rot == 0) |
483fc7cd | 9386 | { |
df58fc94 | 9387 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9388 | break; |
483fc7cd | 9389 | } |
8fc2e39e | 9390 | used_at = 1; |
df58fc94 RS |
9391 | macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot); |
9392 | macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9393 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 | 9394 | } |
252b5132 RH |
9395 | break; |
9396 | ||
252b5132 RH |
9397 | case M_SEQ: |
9398 | if (sreg == 0) | |
67c0d1eb | 9399 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 9400 | else if (treg == 0) |
67c0d1eb | 9401 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9402 | else |
9403 | { | |
67c0d1eb RS |
9404 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9405 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 9406 | } |
8fc2e39e | 9407 | break; |
252b5132 RH |
9408 | |
9409 | case M_SEQ_I: | |
9410 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9411 | { | |
67c0d1eb | 9412 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9413 | break; |
252b5132 RH |
9414 | } |
9415 | if (sreg == 0) | |
9416 | { | |
9417 | as_warn (_("Instruction %s: result is always false"), | |
9418 | ip->insn_mo->name); | |
67c0d1eb | 9419 | move_register (dreg, 0); |
8fc2e39e | 9420 | break; |
252b5132 | 9421 | } |
dd3cbb7e NC |
9422 | if (CPU_HAS_SEQ (mips_opts.arch) |
9423 | && -512 <= imm_expr.X_add_number | |
9424 | && imm_expr.X_add_number < 512) | |
9425 | { | |
9426 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9427 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9428 | break; |
9429 | } | |
252b5132 RH |
9430 | if (imm_expr.X_op == O_constant |
9431 | && imm_expr.X_add_number >= 0 | |
9432 | && imm_expr.X_add_number < 0x10000) | |
9433 | { | |
67c0d1eb | 9434 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9435 | } |
9436 | else if (imm_expr.X_op == O_constant | |
9437 | && imm_expr.X_add_number > -0x8000 | |
9438 | && imm_expr.X_add_number < 0) | |
9439 | { | |
9440 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9441 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9442 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9443 | } |
dd3cbb7e NC |
9444 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9445 | { | |
9446 | used_at = 1; | |
9447 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9448 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
9449 | break; | |
9450 | } | |
252b5132 RH |
9451 | else |
9452 | { | |
67c0d1eb RS |
9453 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9454 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9455 | used_at = 1; |
9456 | } | |
67c0d1eb | 9457 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9458 | break; |
252b5132 RH |
9459 | |
9460 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
9461 | s = "slt"; | |
9462 | goto sge; | |
9463 | case M_SGEU: | |
9464 | s = "sltu"; | |
9465 | sge: | |
67c0d1eb RS |
9466 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
9467 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9468 | break; |
252b5132 RH |
9469 | |
9470 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
9471 | case M_SGEU_I: | |
9472 | if (imm_expr.X_op == O_constant | |
9473 | && imm_expr.X_add_number >= -0x8000 | |
9474 | && imm_expr.X_add_number < 0x8000) | |
9475 | { | |
67c0d1eb RS |
9476 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
9477 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
9478 | } |
9479 | else | |
9480 | { | |
67c0d1eb RS |
9481 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9482 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
9483 | dreg, sreg, AT); | |
252b5132 RH |
9484 | used_at = 1; |
9485 | } | |
67c0d1eb | 9486 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9487 | break; |
252b5132 RH |
9488 | |
9489 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
9490 | s = "slt"; | |
9491 | goto sgt; | |
9492 | case M_SGTU: | |
9493 | s = "sltu"; | |
9494 | sgt: | |
67c0d1eb | 9495 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 9496 | break; |
252b5132 RH |
9497 | |
9498 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
9499 | s = "slt"; | |
9500 | goto sgti; | |
9501 | case M_SGTU_I: | |
9502 | s = "sltu"; | |
9503 | sgti: | |
8fc2e39e | 9504 | used_at = 1; |
67c0d1eb RS |
9505 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9506 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
9507 | break; |
9508 | ||
2396cfb9 | 9509 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
9510 | s = "slt"; |
9511 | goto sle; | |
9512 | case M_SLEU: | |
9513 | s = "sltu"; | |
9514 | sle: | |
67c0d1eb RS |
9515 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
9516 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9517 | break; |
252b5132 | 9518 | |
2396cfb9 | 9519 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
9520 | s = "slt"; |
9521 | goto slei; | |
9522 | case M_SLEU_I: | |
9523 | s = "sltu"; | |
9524 | slei: | |
8fc2e39e | 9525 | used_at = 1; |
67c0d1eb RS |
9526 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9527 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
9528 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
9529 | break; |
9530 | ||
9531 | case M_SLT_I: | |
9532 | if (imm_expr.X_op == O_constant | |
9533 | && imm_expr.X_add_number >= -0x8000 | |
9534 | && imm_expr.X_add_number < 0x8000) | |
9535 | { | |
67c0d1eb | 9536 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9537 | break; |
252b5132 | 9538 | } |
8fc2e39e | 9539 | used_at = 1; |
67c0d1eb RS |
9540 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9541 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9542 | break; |
9543 | ||
9544 | case M_SLTU_I: | |
9545 | if (imm_expr.X_op == O_constant | |
9546 | && imm_expr.X_add_number >= -0x8000 | |
9547 | && imm_expr.X_add_number < 0x8000) | |
9548 | { | |
67c0d1eb | 9549 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 9550 | BFD_RELOC_LO16); |
8fc2e39e | 9551 | break; |
252b5132 | 9552 | } |
8fc2e39e | 9553 | used_at = 1; |
67c0d1eb RS |
9554 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9555 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9556 | break; |
9557 | ||
9558 | case M_SNE: | |
9559 | if (sreg == 0) | |
67c0d1eb | 9560 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 9561 | else if (treg == 0) |
67c0d1eb | 9562 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
9563 | else |
9564 | { | |
67c0d1eb RS |
9565 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9566 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 9567 | } |
8fc2e39e | 9568 | break; |
252b5132 RH |
9569 | |
9570 | case M_SNE_I: | |
9571 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9572 | { | |
67c0d1eb | 9573 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 9574 | break; |
252b5132 RH |
9575 | } |
9576 | if (sreg == 0) | |
9577 | { | |
9578 | as_warn (_("Instruction %s: result is always true"), | |
9579 | ip->insn_mo->name); | |
67c0d1eb RS |
9580 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
9581 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 9582 | break; |
252b5132 | 9583 | } |
dd3cbb7e NC |
9584 | if (CPU_HAS_SEQ (mips_opts.arch) |
9585 | && -512 <= imm_expr.X_add_number | |
9586 | && imm_expr.X_add_number < 512) | |
9587 | { | |
9588 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9589 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9590 | break; |
9591 | } | |
252b5132 RH |
9592 | if (imm_expr.X_op == O_constant |
9593 | && imm_expr.X_add_number >= 0 | |
9594 | && imm_expr.X_add_number < 0x10000) | |
9595 | { | |
67c0d1eb | 9596 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9597 | } |
9598 | else if (imm_expr.X_op == O_constant | |
9599 | && imm_expr.X_add_number > -0x8000 | |
9600 | && imm_expr.X_add_number < 0) | |
9601 | { | |
9602 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9603 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9604 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9605 | } |
dd3cbb7e NC |
9606 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9607 | { | |
9608 | used_at = 1; | |
9609 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9610 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
9611 | break; | |
9612 | } | |
252b5132 RH |
9613 | else |
9614 | { | |
67c0d1eb RS |
9615 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9616 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9617 | used_at = 1; |
9618 | } | |
67c0d1eb | 9619 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 9620 | break; |
252b5132 | 9621 | |
df58fc94 RS |
9622 | case M_SUB_I: |
9623 | s = "addi"; | |
9624 | s2 = "sub"; | |
9625 | goto do_subi; | |
9626 | case M_SUBU_I: | |
9627 | s = "addiu"; | |
9628 | s2 = "subu"; | |
9629 | goto do_subi; | |
252b5132 RH |
9630 | case M_DSUB_I: |
9631 | dbl = 1; | |
df58fc94 RS |
9632 | s = "daddi"; |
9633 | s2 = "dsub"; | |
9634 | if (!mips_opts.micromips) | |
9635 | goto do_subi; | |
252b5132 | 9636 | if (imm_expr.X_op == O_constant |
df58fc94 RS |
9637 | && imm_expr.X_add_number > -0x200 |
9638 | && imm_expr.X_add_number <= 0x200) | |
252b5132 | 9639 | { |
df58fc94 | 9640 | macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number); |
8fc2e39e | 9641 | break; |
252b5132 | 9642 | } |
df58fc94 | 9643 | goto do_subi_i; |
252b5132 RH |
9644 | case M_DSUBU_I: |
9645 | dbl = 1; | |
df58fc94 RS |
9646 | s = "daddiu"; |
9647 | s2 = "dsubu"; | |
9648 | do_subi: | |
252b5132 RH |
9649 | if (imm_expr.X_op == O_constant |
9650 | && imm_expr.X_add_number > -0x8000 | |
9651 | && imm_expr.X_add_number <= 0x8000) | |
9652 | { | |
9653 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
df58fc94 | 9654 | macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9655 | break; |
252b5132 | 9656 | } |
df58fc94 | 9657 | do_subi_i: |
8fc2e39e | 9658 | used_at = 1; |
67c0d1eb | 9659 | load_register (AT, &imm_expr, dbl); |
df58fc94 | 9660 | macro_build (NULL, s2, "d,v,t", dreg, sreg, AT); |
252b5132 RH |
9661 | break; |
9662 | ||
9663 | case M_TEQ_I: | |
9664 | s = "teq"; | |
9665 | goto trap; | |
9666 | case M_TGE_I: | |
9667 | s = "tge"; | |
9668 | goto trap; | |
9669 | case M_TGEU_I: | |
9670 | s = "tgeu"; | |
9671 | goto trap; | |
9672 | case M_TLT_I: | |
9673 | s = "tlt"; | |
9674 | goto trap; | |
9675 | case M_TLTU_I: | |
9676 | s = "tltu"; | |
9677 | goto trap; | |
9678 | case M_TNE_I: | |
9679 | s = "tne"; | |
9680 | trap: | |
8fc2e39e | 9681 | used_at = 1; |
67c0d1eb RS |
9682 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9683 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
9684 | break; |
9685 | ||
252b5132 | 9686 | case M_TRUNCWS: |
43841e91 | 9687 | case M_TRUNCWD: |
df58fc94 | 9688 | gas_assert (!mips_opts.micromips); |
9c2799c2 | 9689 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 9690 | used_at = 1; |
252b5132 RH |
9691 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
9692 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
9693 | ||
9694 | /* | |
9695 | * Is the double cfc1 instruction a bug in the mips assembler; | |
9696 | * or is there a reason for it? | |
9697 | */ | |
7d10b47d | 9698 | start_noreorder (); |
67c0d1eb RS |
9699 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
9700 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
9701 | macro_build (NULL, "nop", ""); | |
252b5132 | 9702 | expr1.X_add_number = 3; |
67c0d1eb | 9703 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 9704 | expr1.X_add_number = 2; |
67c0d1eb RS |
9705 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
9706 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
9707 | macro_build (NULL, "nop", ""); | |
9708 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
9709 | dreg, sreg); | |
9710 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
9711 | macro_build (NULL, "nop", ""); | |
7d10b47d | 9712 | end_noreorder (); |
252b5132 RH |
9713 | break; |
9714 | ||
df58fc94 RS |
9715 | case M_ULH_A: |
9716 | ab = 1; | |
252b5132 RH |
9717 | case M_ULH: |
9718 | s = "lb"; | |
df58fc94 RS |
9719 | s2 = "lbu"; |
9720 | off = 1; | |
9721 | goto uld_st; | |
9722 | case M_ULHU_A: | |
9723 | ab = 1; | |
252b5132 RH |
9724 | case M_ULHU: |
9725 | s = "lbu"; | |
df58fc94 RS |
9726 | s2 = "lbu"; |
9727 | off = 1; | |
9728 | goto uld_st; | |
9729 | case M_ULW_A: | |
9730 | ab = 1; | |
9731 | case M_ULW: | |
9732 | s = "lwl"; | |
9733 | s2 = "lwr"; | |
9734 | off12 = mips_opts.micromips; | |
9735 | off = 3; | |
9736 | goto uld_st; | |
9737 | case M_ULD_A: | |
9738 | ab = 1; | |
252b5132 RH |
9739 | case M_ULD: |
9740 | s = "ldl"; | |
9741 | s2 = "ldr"; | |
df58fc94 | 9742 | off12 = mips_opts.micromips; |
252b5132 | 9743 | off = 7; |
df58fc94 RS |
9744 | goto uld_st; |
9745 | case M_USH_A: | |
9746 | ab = 1; | |
9747 | case M_USH: | |
9748 | s = "sb"; | |
9749 | s2 = "sb"; | |
9750 | off = 1; | |
9751 | ust = 1; | |
9752 | goto uld_st; | |
9753 | case M_USW_A: | |
9754 | ab = 1; | |
9755 | case M_USW: | |
9756 | s = "swl"; | |
9757 | s2 = "swr"; | |
9758 | off12 = mips_opts.micromips; | |
252b5132 | 9759 | off = 3; |
df58fc94 RS |
9760 | ust = 1; |
9761 | goto uld_st; | |
9762 | case M_USD_A: | |
9763 | ab = 1; | |
9764 | case M_USD: | |
9765 | s = "sdl"; | |
9766 | s2 = "sdr"; | |
9767 | off12 = mips_opts.micromips; | |
9768 | off = 7; | |
9769 | ust = 1; | |
9770 | ||
9771 | uld_st: | |
9772 | if (!ab && offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 9773 | as_bad (_("Operand overflow")); |
df58fc94 RS |
9774 | |
9775 | ep = &offset_expr; | |
9776 | expr1.X_add_number = 0; | |
9777 | if (ab) | |
9778 | { | |
9779 | used_at = 1; | |
9780 | tempreg = AT; | |
9781 | load_address (tempreg, ep, &used_at); | |
9782 | if (breg != 0) | |
9783 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
9784 | tempreg, tempreg, breg); | |
9785 | breg = tempreg; | |
9786 | tempreg = treg; | |
9787 | ep = &expr1; | |
9788 | } | |
9789 | else if (off12 | |
9790 | && (offset_expr.X_op != O_constant | |
9791 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number) | |
9792 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off))) | |
9793 | { | |
9794 | used_at = 1; | |
9795 | tempreg = AT; | |
9796 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, | |
9797 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
9798 | breg = tempreg; | |
9799 | tempreg = treg; | |
9800 | ep = &expr1; | |
9801 | } | |
9802 | else if (!ust && treg == breg) | |
8fc2e39e TS |
9803 | { |
9804 | used_at = 1; | |
9805 | tempreg = AT; | |
9806 | } | |
252b5132 | 9807 | else |
df58fc94 | 9808 | tempreg = treg; |
af22f5b2 | 9809 | |
df58fc94 RS |
9810 | if (off == 1) |
9811 | goto ulh_sh; | |
252b5132 | 9812 | |
90ecf173 | 9813 | if (!target_big_endian) |
df58fc94 RS |
9814 | ep->X_add_number += off; |
9815 | if (!off12) | |
9816 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 9817 | else |
df58fc94 RS |
9818 | macro_build (NULL, s, "t,~(b)", |
9819 | tempreg, (unsigned long) ep->X_add_number, breg); | |
9820 | ||
90ecf173 | 9821 | if (!target_big_endian) |
df58fc94 | 9822 | ep->X_add_number -= off; |
252b5132 | 9823 | else |
df58fc94 RS |
9824 | ep->X_add_number += off; |
9825 | if (!off12) | |
9826 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
9827 | else | |
9828 | macro_build (NULL, s2, "t,~(b)", | |
9829 | tempreg, (unsigned long) ep->X_add_number, breg); | |
252b5132 | 9830 | |
df58fc94 RS |
9831 | /* If necessary, move the result in tempreg to the final destination. */ |
9832 | if (!ust && treg != tempreg) | |
9833 | { | |
9834 | /* Protect second load's delay slot. */ | |
9835 | load_delay_nop (); | |
9836 | move_register (treg, tempreg); | |
9837 | } | |
8fc2e39e | 9838 | break; |
252b5132 | 9839 | |
df58fc94 | 9840 | ulh_sh: |
d6bc6245 | 9841 | used_at = 1; |
df58fc94 RS |
9842 | if (target_big_endian == ust) |
9843 | ep->X_add_number += off; | |
9844 | tempreg = ust || ab ? treg : AT; | |
9845 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
9846 | ||
9847 | /* For halfword transfers we need a temporary register to shuffle | |
9848 | bytes. Unfortunately for M_USH_A we have none available before | |
9849 | the next store as AT holds the base address. We deal with this | |
9850 | case by clobbering TREG and then restoring it as with ULH. */ | |
9851 | tempreg = ust == ab ? treg : AT; | |
9852 | if (ust) | |
9853 | macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8); | |
9854 | ||
9855 | if (target_big_endian == ust) | |
9856 | ep->X_add_number -= off; | |
252b5132 | 9857 | else |
df58fc94 RS |
9858 | ep->X_add_number += off; |
9859 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 9860 | |
df58fc94 RS |
9861 | /* For M_USH_A re-retrieve the LSB. */ |
9862 | if (ust && ab) | |
9863 | { | |
9864 | if (target_big_endian) | |
9865 | ep->X_add_number += off; | |
9866 | else | |
9867 | ep->X_add_number -= off; | |
9868 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); | |
9869 | } | |
9870 | /* For ULH and M_USH_A OR the LSB in. */ | |
9871 | if (!ust || ab) | |
9872 | { | |
9873 | tempreg = !ab ? AT : treg; | |
9874 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); | |
9875 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
9876 | } | |
252b5132 RH |
9877 | break; |
9878 | ||
9879 | default: | |
9880 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 9881 | are added dynamically. */ |
252b5132 RH |
9882 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
9883 | break; | |
9884 | } | |
741fe287 | 9885 | if (!mips_opts.at && used_at) |
8fc2e39e | 9886 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
9887 | } |
9888 | ||
9889 | /* Implement macros in mips16 mode. */ | |
9890 | ||
9891 | static void | |
17a2f251 | 9892 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
9893 | { |
9894 | int mask; | |
9895 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
9896 | expressionS expr1; |
9897 | int dbl; | |
9898 | const char *s, *s2, *s3; | |
9899 | ||
9900 | mask = ip->insn_mo->mask; | |
9901 | ||
bf12938e RS |
9902 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
9903 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
9904 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 9905 | |
252b5132 RH |
9906 | expr1.X_op = O_constant; |
9907 | expr1.X_op_symbol = NULL; | |
9908 | expr1.X_add_symbol = NULL; | |
9909 | expr1.X_add_number = 1; | |
9910 | ||
9911 | dbl = 0; | |
9912 | ||
9913 | switch (mask) | |
9914 | { | |
9915 | default: | |
9916 | internalError (); | |
9917 | ||
9918 | case M_DDIV_3: | |
9919 | dbl = 1; | |
9920 | case M_DIV_3: | |
9921 | s = "mflo"; | |
9922 | goto do_div3; | |
9923 | case M_DREM_3: | |
9924 | dbl = 1; | |
9925 | case M_REM_3: | |
9926 | s = "mfhi"; | |
9927 | do_div3: | |
7d10b47d | 9928 | start_noreorder (); |
67c0d1eb | 9929 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 9930 | expr1.X_add_number = 2; |
67c0d1eb RS |
9931 | macro_build (&expr1, "bnez", "x,p", yreg); |
9932 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 9933 | |
252b5132 RH |
9934 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
9935 | since that causes an overflow. We should do that as well, | |
9936 | but I don't see how to do the comparisons without a temporary | |
9937 | register. */ | |
7d10b47d | 9938 | end_noreorder (); |
67c0d1eb | 9939 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
9940 | break; |
9941 | ||
9942 | case M_DIVU_3: | |
9943 | s = "divu"; | |
9944 | s2 = "mflo"; | |
9945 | goto do_divu3; | |
9946 | case M_REMU_3: | |
9947 | s = "divu"; | |
9948 | s2 = "mfhi"; | |
9949 | goto do_divu3; | |
9950 | case M_DDIVU_3: | |
9951 | s = "ddivu"; | |
9952 | s2 = "mflo"; | |
9953 | goto do_divu3; | |
9954 | case M_DREMU_3: | |
9955 | s = "ddivu"; | |
9956 | s2 = "mfhi"; | |
9957 | do_divu3: | |
7d10b47d | 9958 | start_noreorder (); |
67c0d1eb | 9959 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 9960 | expr1.X_add_number = 2; |
67c0d1eb RS |
9961 | macro_build (&expr1, "bnez", "x,p", yreg); |
9962 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 9963 | end_noreorder (); |
67c0d1eb | 9964 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
9965 | break; |
9966 | ||
9967 | case M_DMUL: | |
9968 | dbl = 1; | |
9969 | case M_MUL: | |
67c0d1eb RS |
9970 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
9971 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 9972 | break; |
252b5132 RH |
9973 | |
9974 | case M_DSUBU_I: | |
9975 | dbl = 1; | |
9976 | goto do_subu; | |
9977 | case M_SUBU_I: | |
9978 | do_subu: | |
9979 | if (imm_expr.X_op != O_constant) | |
9980 | as_bad (_("Unsupported large constant")); | |
9981 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9982 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
9983 | break; |
9984 | ||
9985 | case M_SUBU_I_2: | |
9986 | if (imm_expr.X_op != O_constant) | |
9987 | as_bad (_("Unsupported large constant")); | |
9988 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9989 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
9990 | break; |
9991 | ||
9992 | case M_DSUBU_I_2: | |
9993 | if (imm_expr.X_op != O_constant) | |
9994 | as_bad (_("Unsupported large constant")); | |
9995 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9996 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
9997 | break; |
9998 | ||
9999 | case M_BEQ: | |
10000 | s = "cmp"; | |
10001 | s2 = "bteqz"; | |
10002 | goto do_branch; | |
10003 | case M_BNE: | |
10004 | s = "cmp"; | |
10005 | s2 = "btnez"; | |
10006 | goto do_branch; | |
10007 | case M_BLT: | |
10008 | s = "slt"; | |
10009 | s2 = "btnez"; | |
10010 | goto do_branch; | |
10011 | case M_BLTU: | |
10012 | s = "sltu"; | |
10013 | s2 = "btnez"; | |
10014 | goto do_branch; | |
10015 | case M_BLE: | |
10016 | s = "slt"; | |
10017 | s2 = "bteqz"; | |
10018 | goto do_reverse_branch; | |
10019 | case M_BLEU: | |
10020 | s = "sltu"; | |
10021 | s2 = "bteqz"; | |
10022 | goto do_reverse_branch; | |
10023 | case M_BGE: | |
10024 | s = "slt"; | |
10025 | s2 = "bteqz"; | |
10026 | goto do_branch; | |
10027 | case M_BGEU: | |
10028 | s = "sltu"; | |
10029 | s2 = "bteqz"; | |
10030 | goto do_branch; | |
10031 | case M_BGT: | |
10032 | s = "slt"; | |
10033 | s2 = "btnez"; | |
10034 | goto do_reverse_branch; | |
10035 | case M_BGTU: | |
10036 | s = "sltu"; | |
10037 | s2 = "btnez"; | |
10038 | ||
10039 | do_reverse_branch: | |
10040 | tmp = xreg; | |
10041 | xreg = yreg; | |
10042 | yreg = tmp; | |
10043 | ||
10044 | do_branch: | |
67c0d1eb RS |
10045 | macro_build (NULL, s, "x,y", xreg, yreg); |
10046 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10047 | break; |
10048 | ||
10049 | case M_BEQ_I: | |
10050 | s = "cmpi"; | |
10051 | s2 = "bteqz"; | |
10052 | s3 = "x,U"; | |
10053 | goto do_branch_i; | |
10054 | case M_BNE_I: | |
10055 | s = "cmpi"; | |
10056 | s2 = "btnez"; | |
10057 | s3 = "x,U"; | |
10058 | goto do_branch_i; | |
10059 | case M_BLT_I: | |
10060 | s = "slti"; | |
10061 | s2 = "btnez"; | |
10062 | s3 = "x,8"; | |
10063 | goto do_branch_i; | |
10064 | case M_BLTU_I: | |
10065 | s = "sltiu"; | |
10066 | s2 = "btnez"; | |
10067 | s3 = "x,8"; | |
10068 | goto do_branch_i; | |
10069 | case M_BLE_I: | |
10070 | s = "slti"; | |
10071 | s2 = "btnez"; | |
10072 | s3 = "x,8"; | |
10073 | goto do_addone_branch_i; | |
10074 | case M_BLEU_I: | |
10075 | s = "sltiu"; | |
10076 | s2 = "btnez"; | |
10077 | s3 = "x,8"; | |
10078 | goto do_addone_branch_i; | |
10079 | case M_BGE_I: | |
10080 | s = "slti"; | |
10081 | s2 = "bteqz"; | |
10082 | s3 = "x,8"; | |
10083 | goto do_branch_i; | |
10084 | case M_BGEU_I: | |
10085 | s = "sltiu"; | |
10086 | s2 = "bteqz"; | |
10087 | s3 = "x,8"; | |
10088 | goto do_branch_i; | |
10089 | case M_BGT_I: | |
10090 | s = "slti"; | |
10091 | s2 = "bteqz"; | |
10092 | s3 = "x,8"; | |
10093 | goto do_addone_branch_i; | |
10094 | case M_BGTU_I: | |
10095 | s = "sltiu"; | |
10096 | s2 = "bteqz"; | |
10097 | s3 = "x,8"; | |
10098 | ||
10099 | do_addone_branch_i: | |
10100 | if (imm_expr.X_op != O_constant) | |
10101 | as_bad (_("Unsupported large constant")); | |
10102 | ++imm_expr.X_add_number; | |
10103 | ||
10104 | do_branch_i: | |
67c0d1eb RS |
10105 | macro_build (&imm_expr, s, s3, xreg); |
10106 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10107 | break; |
10108 | ||
10109 | case M_ABS: | |
10110 | expr1.X_add_number = 0; | |
67c0d1eb | 10111 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 10112 | if (xreg != yreg) |
67c0d1eb | 10113 | move_register (xreg, yreg); |
252b5132 | 10114 | expr1.X_add_number = 2; |
67c0d1eb RS |
10115 | macro_build (&expr1, "bteqz", "p"); |
10116 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
10117 | } |
10118 | } | |
10119 | ||
10120 | /* For consistency checking, verify that all bits are specified either | |
10121 | by the match/mask part of the instruction definition, or by the | |
10122 | operand list. */ | |
10123 | static int | |
17a2f251 | 10124 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
10125 | { |
10126 | const char *p = opc->args; | |
10127 | char c; | |
10128 | unsigned long used_bits = opc->mask; | |
10129 | ||
10130 | if ((used_bits & opc->match) != opc->match) | |
10131 | { | |
10132 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
10133 | opc->name, opc->args); | |
10134 | return 0; | |
10135 | } | |
10136 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
10137 | while (*p) | |
10138 | switch (c = *p++) | |
10139 | { | |
10140 | case ',': break; | |
10141 | case '(': break; | |
10142 | case ')': break; | |
af7ee8bf CD |
10143 | case '+': |
10144 | switch (c = *p++) | |
10145 | { | |
9bcd4f99 TS |
10146 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
10147 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
10148 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
10149 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
10150 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10151 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10152 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
10153 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10154 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
10155 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10156 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10157 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10158 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10159 | case 'I': break; | |
ef2e4d86 CF |
10160 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
10161 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
10162 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
10163 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
10164 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
10165 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
10166 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 10167 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
10168 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
10169 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
10170 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
10171 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
10172 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
10173 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
10174 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
bb35fb24 | 10175 | |
af7ee8bf CD |
10176 | default: |
10177 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
10178 | c, opc->name, opc->args); | |
10179 | return 0; | |
10180 | } | |
10181 | break; | |
252b5132 RH |
10182 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10183 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
10184 | case 'A': break; | |
4372b673 | 10185 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
10186 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
10187 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
10188 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10189 | case 'F': break; | |
10190 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 10191 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 10192 | case 'I': break; |
e972090a | 10193 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 10194 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10195 | case 'L': break; |
10196 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
10197 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
10198 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
10199 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
10200 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10201 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
10202 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10203 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
10204 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10205 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
10206 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
10207 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10208 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10209 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
10210 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10211 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
10212 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
10213 | case 'f': break; | |
10214 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
10215 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10216 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10217 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
10218 | case 'l': break; | |
10219 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10220 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10221 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
10222 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10223 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10224 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10225 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10226 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10227 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10228 | case 'x': break; | |
10229 | case 'z': break; | |
10230 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
10231 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10232 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
10233 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
10234 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
10235 | case '[': break; | |
10236 | case ']': break; | |
620edafd | 10237 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 10238 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
10239 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
10240 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
10241 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
10242 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10243 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
10244 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
10245 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
10246 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
10247 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
10248 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
10249 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
10250 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
10251 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
10252 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
10253 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
10254 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
252b5132 RH |
10255 | default: |
10256 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
10257 | c, opc->name, opc->args); | |
10258 | return 0; | |
10259 | } | |
10260 | #undef USE_BITS | |
10261 | if (used_bits != 0xffffffff) | |
10262 | { | |
10263 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
10264 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
10265 | return 0; | |
10266 | } | |
10267 | return 1; | |
10268 | } | |
10269 | ||
df58fc94 RS |
10270 | /* For consistency checking, verify that the length implied matches the |
10271 | major opcode and that all bits are specified either by the match/mask | |
10272 | part of the instruction definition, or by the operand list. */ | |
10273 | ||
10274 | static int | |
10275 | validate_micromips_insn (const struct mips_opcode *opc) | |
10276 | { | |
10277 | unsigned long match = opc->match; | |
10278 | unsigned long mask = opc->mask; | |
10279 | const char *p = opc->args; | |
10280 | unsigned long insn_bits; | |
10281 | unsigned long used_bits; | |
10282 | unsigned long major; | |
10283 | unsigned int length; | |
10284 | char e; | |
10285 | char c; | |
10286 | ||
10287 | if ((mask & match) != match) | |
10288 | { | |
10289 | as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"), | |
10290 | opc->name, opc->args); | |
10291 | return 0; | |
10292 | } | |
10293 | length = micromips_insn_length (opc); | |
10294 | if (length != 2 && length != 4) | |
10295 | { | |
10296 | as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): " | |
10297 | "%s %s"), length, opc->name, opc->args); | |
10298 | return 0; | |
10299 | } | |
10300 | major = match >> (10 + 8 * (length - 2)); | |
10301 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
10302 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
10303 | { | |
10304 | as_bad (_("Internal error: bad microMIPS opcode " | |
10305 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); | |
10306 | return 0; | |
10307 | } | |
10308 | ||
10309 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
10310 | insn_bits = 1 << 4 * length; | |
10311 | insn_bits <<= 4 * length; | |
10312 | insn_bits -= 1; | |
10313 | used_bits = mask; | |
10314 | #define USE_BITS(field) \ | |
10315 | (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field) | |
10316 | while (*p) | |
10317 | switch (c = *p++) | |
10318 | { | |
10319 | case ',': break; | |
10320 | case '(': break; | |
10321 | case ')': break; | |
10322 | case '+': | |
10323 | e = c; | |
10324 | switch (c = *p++) | |
10325 | { | |
10326 | case 'A': USE_BITS (EXTLSB); break; | |
10327 | case 'B': USE_BITS (INSMSB); break; | |
10328 | case 'C': USE_BITS (EXTMSBD); break; | |
10329 | case 'D': USE_BITS (RS); USE_BITS (SEL); break; | |
10330 | case 'E': USE_BITS (EXTLSB); break; | |
10331 | case 'F': USE_BITS (INSMSB); break; | |
10332 | case 'G': USE_BITS (EXTMSBD); break; | |
10333 | case 'H': USE_BITS (EXTMSBD); break; | |
10334 | default: | |
10335 | as_bad (_("Internal error: bad mips opcode " | |
10336 | "(unknown extension operand type `%c%c'): %s %s"), | |
10337 | e, c, opc->name, opc->args); | |
10338 | return 0; | |
10339 | } | |
10340 | break; | |
10341 | case 'm': | |
10342 | e = c; | |
10343 | switch (c = *p++) | |
10344 | { | |
10345 | case 'A': USE_BITS (IMMA); break; | |
10346 | case 'B': USE_BITS (IMMB); break; | |
10347 | case 'C': USE_BITS (IMMC); break; | |
10348 | case 'D': USE_BITS (IMMD); break; | |
10349 | case 'E': USE_BITS (IMME); break; | |
10350 | case 'F': USE_BITS (IMMF); break; | |
10351 | case 'G': USE_BITS (IMMG); break; | |
10352 | case 'H': USE_BITS (IMMH); break; | |
10353 | case 'I': USE_BITS (IMMI); break; | |
10354 | case 'J': USE_BITS (IMMJ); break; | |
10355 | case 'L': USE_BITS (IMML); break; | |
10356 | case 'M': USE_BITS (IMMM); break; | |
10357 | case 'N': USE_BITS (IMMN); break; | |
10358 | case 'O': USE_BITS (IMMO); break; | |
10359 | case 'P': USE_BITS (IMMP); break; | |
10360 | case 'Q': USE_BITS (IMMQ); break; | |
10361 | case 'U': USE_BITS (IMMU); break; | |
10362 | case 'W': USE_BITS (IMMW); break; | |
10363 | case 'X': USE_BITS (IMMX); break; | |
10364 | case 'Y': USE_BITS (IMMY); break; | |
10365 | case 'Z': break; | |
10366 | case 'a': break; | |
10367 | case 'b': USE_BITS (MB); break; | |
10368 | case 'c': USE_BITS (MC); break; | |
10369 | case 'd': USE_BITS (MD); break; | |
10370 | case 'e': USE_BITS (ME); break; | |
10371 | case 'f': USE_BITS (MF); break; | |
10372 | case 'g': USE_BITS (MG); break; | |
10373 | case 'h': USE_BITS (MH); break; | |
10374 | case 'i': USE_BITS (MI); break; | |
10375 | case 'j': USE_BITS (MJ); break; | |
10376 | case 'l': USE_BITS (ML); break; | |
10377 | case 'm': USE_BITS (MM); break; | |
10378 | case 'n': USE_BITS (MN); break; | |
10379 | case 'p': USE_BITS (MP); break; | |
10380 | case 'q': USE_BITS (MQ); break; | |
10381 | case 'r': break; | |
10382 | case 's': break; | |
10383 | case 't': break; | |
10384 | case 'x': break; | |
10385 | case 'y': break; | |
10386 | case 'z': break; | |
10387 | default: | |
10388 | as_bad (_("Internal error: bad mips opcode " | |
10389 | "(unknown extension operand type `%c%c'): %s %s"), | |
10390 | e, c, opc->name, opc->args); | |
10391 | return 0; | |
10392 | } | |
10393 | break; | |
10394 | case '.': USE_BITS (OFFSET10); break; | |
10395 | case '1': USE_BITS (STYPE); break; | |
10396 | case '<': USE_BITS (SHAMT); break; | |
10397 | case '>': USE_BITS (SHAMT); break; | |
10398 | case 'B': USE_BITS (CODE10); break; | |
10399 | case 'C': USE_BITS (COPZ); break; | |
10400 | case 'D': USE_BITS (FD); break; | |
10401 | case 'E': USE_BITS (RT); break; | |
10402 | case 'G': USE_BITS (RS); break; | |
10403 | case 'H': USE_BITS (SEL); break; | |
10404 | case 'K': USE_BITS (RS); break; | |
10405 | case 'M': USE_BITS (CCC); break; | |
10406 | case 'N': USE_BITS (BCC); break; | |
10407 | case 'R': USE_BITS (FR); break; | |
10408 | case 'S': USE_BITS (FS); break; | |
10409 | case 'T': USE_BITS (FT); break; | |
10410 | case 'V': USE_BITS (FS); break; | |
10411 | case 'a': USE_BITS (TARGET); break; | |
10412 | case 'b': USE_BITS (RS); break; | |
10413 | case 'c': USE_BITS (CODE); break; | |
10414 | case 'd': USE_BITS (RD); break; | |
10415 | case 'h': USE_BITS (PREFX); break; | |
10416 | case 'i': USE_BITS (IMMEDIATE); break; | |
10417 | case 'j': USE_BITS (DELTA); break; | |
10418 | case 'k': USE_BITS (CACHE); break; | |
10419 | case 'n': USE_BITS (RT); break; | |
10420 | case 'o': USE_BITS (DELTA); break; | |
10421 | case 'p': USE_BITS (DELTA); break; | |
10422 | case 'q': USE_BITS (CODE2); break; | |
10423 | case 'r': USE_BITS (RS); break; | |
10424 | case 's': USE_BITS (RS); break; | |
10425 | case 't': USE_BITS (RT); break; | |
10426 | case 'u': USE_BITS (IMMEDIATE); break; | |
10427 | case 'v': USE_BITS (RS); break; | |
10428 | case 'w': USE_BITS (RT); break; | |
10429 | case 'y': USE_BITS (RS3); break; | |
10430 | case 'z': break; | |
10431 | case '|': USE_BITS (TRAP); break; | |
10432 | case '~': USE_BITS (OFFSET12); break; | |
10433 | default: | |
10434 | as_bad (_("Internal error: bad microMIPS opcode " | |
10435 | "(unknown operand type `%c'): %s %s"), | |
10436 | c, opc->name, opc->args); | |
10437 | return 0; | |
10438 | } | |
10439 | #undef USE_BITS | |
10440 | if (used_bits != insn_bits) | |
10441 | { | |
10442 | if (~used_bits & insn_bits) | |
10443 | as_bad (_("Internal error: bad microMIPS opcode " | |
10444 | "(bits 0x%lx undefined): %s %s"), | |
10445 | ~used_bits & insn_bits, opc->name, opc->args); | |
10446 | if (used_bits & ~insn_bits) | |
10447 | as_bad (_("Internal error: bad microMIPS opcode " | |
10448 | "(bits 0x%lx defined): %s %s"), | |
10449 | used_bits & ~insn_bits, opc->name, opc->args); | |
10450 | return 0; | |
10451 | } | |
10452 | return 1; | |
10453 | } | |
10454 | ||
9bcd4f99 TS |
10455 | /* UDI immediates. */ |
10456 | struct mips_immed { | |
10457 | char type; | |
10458 | unsigned int shift; | |
10459 | unsigned long mask; | |
10460 | const char * desc; | |
10461 | }; | |
10462 | ||
10463 | static const struct mips_immed mips_immed[] = { | |
10464 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
10465 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
10466 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
10467 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
10468 | { 0,0,0,0 } | |
10469 | }; | |
10470 | ||
7455baf8 TS |
10471 | /* Check whether an odd floating-point register is allowed. */ |
10472 | static int | |
10473 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
10474 | { | |
10475 | const char *s = insn->name; | |
10476 | ||
10477 | if (insn->pinfo == INSN_MACRO) | |
10478 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
10479 | return 1; | |
10480 | ||
10481 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
10482 | { | |
10483 | /* Allow odd registers for single-precision ops. */ | |
10484 | switch (insn->pinfo & (FP_S | FP_D)) | |
10485 | { | |
10486 | case FP_S: | |
10487 | case 0: | |
10488 | return 1; /* both single precision - ok */ | |
10489 | case FP_D: | |
10490 | return 0; /* both double precision - fail */ | |
10491 | default: | |
10492 | break; | |
10493 | } | |
10494 | ||
10495 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
10496 | s = strchr (insn->name, '.'); | |
10497 | if (argnum == 2) | |
10498 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
10499 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
10500 | } | |
10501 | ||
10502 | /* Single-precision coprocessor loads and moves are OK too. */ | |
10503 | if ((insn->pinfo & FP_S) | |
10504 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
10505 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
10506 | return 1; | |
10507 | ||
10508 | return 0; | |
10509 | } | |
10510 | ||
df58fc94 RS |
10511 | /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive) |
10512 | taking bits from BIT up. */ | |
10513 | static int | |
10514 | expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit) | |
10515 | { | |
10516 | return (ep->X_op == O_constant | |
10517 | && (ep->X_add_number & ((1 << bit) - 1)) == 0 | |
10518 | && ep->X_add_number >= min << bit | |
10519 | && ep->X_add_number < max << bit); | |
10520 | } | |
10521 | ||
252b5132 RH |
10522 | /* This routine assembles an instruction into its binary format. As a |
10523 | side effect, it sets one of the global variables imm_reloc or | |
10524 | offset_reloc to the type of relocation to do if one of the operands | |
10525 | is an address expression. */ | |
10526 | ||
10527 | static void | |
17a2f251 | 10528 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 | 10529 | { |
df58fc94 RS |
10530 | bfd_boolean wrong_delay_slot_insns = FALSE; |
10531 | bfd_boolean need_delay_slot_ok = TRUE; | |
10532 | struct mips_opcode *firstinsn = NULL; | |
10533 | const struct mips_opcode *past; | |
10534 | struct hash_control *hash; | |
252b5132 RH |
10535 | char *s; |
10536 | const char *args; | |
43841e91 | 10537 | char c = 0; |
252b5132 RH |
10538 | struct mips_opcode *insn; |
10539 | char *argsStart; | |
10540 | unsigned int regno; | |
34224acf | 10541 | unsigned int lastregno; |
df58fc94 | 10542 | unsigned int destregno = 0; |
af7ee8bf | 10543 | unsigned int lastpos = 0; |
071742cf | 10544 | unsigned int limlo, limhi; |
252b5132 | 10545 | char *s_reset; |
74cd071d | 10546 | offsetT min_range, max_range; |
df58fc94 | 10547 | long opend; |
a40bc9dd | 10548 | char *name; |
707bfff6 TS |
10549 | int argnum; |
10550 | unsigned int rtype; | |
df58fc94 | 10551 | char *dot; |
a40bc9dd | 10552 | long end; |
252b5132 RH |
10553 | |
10554 | insn_error = NULL; | |
10555 | ||
df58fc94 RS |
10556 | if (mips_opts.micromips) |
10557 | { | |
10558 | hash = micromips_op_hash; | |
10559 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
10560 | } | |
10561 | else | |
10562 | { | |
10563 | hash = op_hash; | |
10564 | past = &mips_opcodes[NUMOPCODES]; | |
10565 | } | |
10566 | forced_insn_length = 0; | |
252b5132 | 10567 | insn = NULL; |
252b5132 | 10568 | |
df58fc94 | 10569 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
10570 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
10571 | continue; | |
bdaaa2e1 | 10572 | |
a40bc9dd RS |
10573 | /* Make a copy of the instruction so that we can fiddle with it. */ |
10574 | name = alloca (end + 1); | |
10575 | memcpy (name, str, end); | |
10576 | name[end] = '\0'; | |
252b5132 | 10577 | |
df58fc94 RS |
10578 | for (;;) |
10579 | { | |
10580 | insn = (struct mips_opcode *) hash_find (hash, name); | |
10581 | ||
10582 | if (insn != NULL || !mips_opts.micromips) | |
10583 | break; | |
10584 | if (forced_insn_length) | |
10585 | break; | |
10586 | ||
10587 | /* See if there's an instruction size override suffix, | |
10588 | either `16' or `32', at the end of the mnemonic proper, | |
10589 | that defines the operation, i.e. before the first `.' | |
10590 | character if any. Strip it and retry. */ | |
10591 | dot = strchr (name, '.'); | |
10592 | opend = dot != NULL ? dot - name : end; | |
10593 | if (opend < 3) | |
10594 | break; | |
10595 | if (name[opend - 2] == '1' && name[opend - 1] == '6') | |
10596 | forced_insn_length = 2; | |
10597 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
10598 | forced_insn_length = 4; | |
10599 | else | |
10600 | break; | |
10601 | memcpy (name + opend - 2, name + opend, end - opend + 1); | |
10602 | } | |
252b5132 RH |
10603 | if (insn == NULL) |
10604 | { | |
a40bc9dd RS |
10605 | insn_error = _("Unrecognized opcode"); |
10606 | return; | |
252b5132 RH |
10607 | } |
10608 | ||
df58fc94 RS |
10609 | /* For microMIPS instructions placed in a fixed-length branch delay slot |
10610 | we make up to two passes over the relevant fragment of the opcode | |
10611 | table. First we try instructions that meet the delay slot's length | |
10612 | requirement. If none matched, then we retry with the remaining ones | |
10613 | and if one matches, then we use it and then issue an appropriate | |
10614 | warning later on. */ | |
a40bc9dd | 10615 | argsStart = s = str + end; |
252b5132 RH |
10616 | for (;;) |
10617 | { | |
df58fc94 RS |
10618 | bfd_boolean delay_slot_ok; |
10619 | bfd_boolean size_ok; | |
b34976b6 | 10620 | bfd_boolean ok; |
252b5132 | 10621 | |
a40bc9dd | 10622 | gas_assert (strcmp (insn->name, name) == 0); |
252b5132 | 10623 | |
f79e2745 | 10624 | ok = is_opcode_valid (insn); |
df58fc94 RS |
10625 | size_ok = is_size_valid (insn); |
10626 | delay_slot_ok = is_delay_slot_valid (insn); | |
10627 | if (!delay_slot_ok && !wrong_delay_slot_insns) | |
252b5132 | 10628 | { |
df58fc94 RS |
10629 | firstinsn = insn; |
10630 | wrong_delay_slot_insns = TRUE; | |
10631 | } | |
10632 | if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok) | |
10633 | { | |
10634 | static char buf[256]; | |
10635 | ||
10636 | if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0) | |
252b5132 RH |
10637 | { |
10638 | ++insn; | |
10639 | continue; | |
10640 | } | |
df58fc94 | 10641 | if (wrong_delay_slot_insns && need_delay_slot_ok) |
beae10d5 | 10642 | { |
df58fc94 RS |
10643 | gas_assert (firstinsn); |
10644 | need_delay_slot_ok = FALSE; | |
10645 | past = insn + 1; | |
10646 | insn = firstinsn; | |
10647 | continue; | |
252b5132 | 10648 | } |
df58fc94 RS |
10649 | |
10650 | if (insn_error) | |
10651 | return; | |
10652 | ||
10653 | if (!ok) | |
10654 | sprintf (buf, _("opcode not supported on this processor: %s (%s)"), | |
10655 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
10656 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
10657 | else | |
10658 | sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"), | |
10659 | 8 * forced_insn_length); | |
10660 | insn_error = buf; | |
10661 | ||
10662 | return; | |
252b5132 RH |
10663 | } |
10664 | ||
1e915849 | 10665 | create_insn (ip, insn); |
268f6bed | 10666 | insn_error = NULL; |
707bfff6 | 10667 | argnum = 1; |
24864476 | 10668 | lastregno = 0xffffffff; |
252b5132 RH |
10669 | for (args = insn->args;; ++args) |
10670 | { | |
deec1734 CD |
10671 | int is_mdmx; |
10672 | ||
ad8d3bb3 | 10673 | s += strspn (s, " \t"); |
deec1734 | 10674 | is_mdmx = 0; |
252b5132 RH |
10675 | switch (*args) |
10676 | { | |
10677 | case '\0': /* end of args */ | |
10678 | if (*s == '\0') | |
10679 | return; | |
10680 | break; | |
10681 | ||
90ecf173 | 10682 | case '2': /* DSP 2-bit unsigned immediate in bit 11. */ |
df58fc94 | 10683 | gas_assert (!mips_opts.micromips); |
8b082fb1 TS |
10684 | my_getExpression (&imm_expr, s); |
10685 | check_absolute_expr (ip, &imm_expr); | |
10686 | if ((unsigned long) imm_expr.X_add_number != 1 | |
10687 | && (unsigned long) imm_expr.X_add_number != 3) | |
10688 | { | |
10689 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
10690 | (unsigned long) imm_expr.X_add_number); | |
10691 | } | |
df58fc94 | 10692 | INSERT_OPERAND (0, BP, *ip, imm_expr.X_add_number); |
8b082fb1 TS |
10693 | imm_expr.X_op = O_absent; |
10694 | s = expr_end; | |
10695 | continue; | |
10696 | ||
90ecf173 | 10697 | case '3': /* DSP 3-bit unsigned immediate in bit 21. */ |
df58fc94 | 10698 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10699 | my_getExpression (&imm_expr, s); |
10700 | check_absolute_expr (ip, &imm_expr); | |
10701 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
10702 | { | |
a9e24354 TS |
10703 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10704 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10705 | } |
df58fc94 | 10706 | INSERT_OPERAND (0, SA3, *ip, imm_expr.X_add_number); |
74cd071d CF |
10707 | imm_expr.X_op = O_absent; |
10708 | s = expr_end; | |
10709 | continue; | |
10710 | ||
90ecf173 | 10711 | case '4': /* DSP 4-bit unsigned immediate in bit 21. */ |
df58fc94 | 10712 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10713 | my_getExpression (&imm_expr, s); |
10714 | check_absolute_expr (ip, &imm_expr); | |
10715 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
10716 | { | |
a9e24354 TS |
10717 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10718 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10719 | } |
df58fc94 | 10720 | INSERT_OPERAND (0, SA4, *ip, imm_expr.X_add_number); |
74cd071d CF |
10721 | imm_expr.X_op = O_absent; |
10722 | s = expr_end; | |
10723 | continue; | |
10724 | ||
90ecf173 | 10725 | case '5': /* DSP 8-bit unsigned immediate in bit 16. */ |
df58fc94 | 10726 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10727 | my_getExpression (&imm_expr, s); |
10728 | check_absolute_expr (ip, &imm_expr); | |
10729 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
10730 | { | |
a9e24354 TS |
10731 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10732 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10733 | } |
df58fc94 | 10734 | INSERT_OPERAND (0, IMM8, *ip, imm_expr.X_add_number); |
74cd071d CF |
10735 | imm_expr.X_op = O_absent; |
10736 | s = expr_end; | |
10737 | continue; | |
10738 | ||
90ecf173 | 10739 | case '6': /* DSP 5-bit unsigned immediate in bit 21. */ |
df58fc94 | 10740 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10741 | my_getExpression (&imm_expr, s); |
10742 | check_absolute_expr (ip, &imm_expr); | |
10743 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
10744 | { | |
a9e24354 TS |
10745 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10746 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10747 | } |
df58fc94 | 10748 | INSERT_OPERAND (0, RS, *ip, imm_expr.X_add_number); |
74cd071d CF |
10749 | imm_expr.X_op = O_absent; |
10750 | s = expr_end; | |
10751 | continue; | |
10752 | ||
90ecf173 | 10753 | case '7': /* Four DSP accumulators in bits 11,12. */ |
df58fc94 | 10754 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10755 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
10756 | s[3] >= '0' && s[3] <= '3') | |
10757 | { | |
10758 | regno = s[3] - '0'; | |
10759 | s += 4; | |
df58fc94 | 10760 | INSERT_OPERAND (0, DSPACC, *ip, regno); |
74cd071d CF |
10761 | continue; |
10762 | } | |
10763 | else | |
10764 | as_bad (_("Invalid dsp acc register")); | |
10765 | break; | |
10766 | ||
90ecf173 | 10767 | case '8': /* DSP 6-bit unsigned immediate in bit 11. */ |
df58fc94 | 10768 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10769 | my_getExpression (&imm_expr, s); |
10770 | check_absolute_expr (ip, &imm_expr); | |
10771 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
10772 | { | |
a9e24354 TS |
10773 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10774 | OP_MASK_WRDSP, | |
10775 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10776 | } |
df58fc94 | 10777 | INSERT_OPERAND (0, WRDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
10778 | imm_expr.X_op = O_absent; |
10779 | s = expr_end; | |
10780 | continue; | |
10781 | ||
90ecf173 | 10782 | case '9': /* Four DSP accumulators in bits 21,22. */ |
df58fc94 | 10783 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10784 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
10785 | s[3] >= '0' && s[3] <= '3') | |
10786 | { | |
10787 | regno = s[3] - '0'; | |
10788 | s += 4; | |
df58fc94 | 10789 | INSERT_OPERAND (0, DSPACC_S, *ip, regno); |
74cd071d CF |
10790 | continue; |
10791 | } | |
10792 | else | |
10793 | as_bad (_("Invalid dsp acc register")); | |
10794 | break; | |
10795 | ||
90ecf173 | 10796 | case '0': /* DSP 6-bit signed immediate in bit 20. */ |
df58fc94 | 10797 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10798 | my_getExpression (&imm_expr, s); |
10799 | check_absolute_expr (ip, &imm_expr); | |
10800 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
10801 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
10802 | if (imm_expr.X_add_number < min_range || | |
10803 | imm_expr.X_add_number > max_range) | |
10804 | { | |
a9e24354 TS |
10805 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
10806 | (long) min_range, (long) max_range, | |
10807 | (long) imm_expr.X_add_number); | |
74cd071d | 10808 | } |
df58fc94 | 10809 | INSERT_OPERAND (0, DSPSFT, *ip, imm_expr.X_add_number); |
74cd071d CF |
10810 | imm_expr.X_op = O_absent; |
10811 | s = expr_end; | |
10812 | continue; | |
10813 | ||
90ecf173 | 10814 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
df58fc94 | 10815 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10816 | my_getExpression (&imm_expr, s); |
10817 | check_absolute_expr (ip, &imm_expr); | |
10818 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
10819 | { | |
a9e24354 TS |
10820 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10821 | OP_MASK_RDDSP, | |
10822 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10823 | } |
df58fc94 | 10824 | INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
10825 | imm_expr.X_op = O_absent; |
10826 | s = expr_end; | |
10827 | continue; | |
10828 | ||
90ecf173 | 10829 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
df58fc94 | 10830 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10831 | my_getExpression (&imm_expr, s); |
10832 | check_absolute_expr (ip, &imm_expr); | |
10833 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
10834 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
10835 | if (imm_expr.X_add_number < min_range || | |
10836 | imm_expr.X_add_number > max_range) | |
10837 | { | |
a9e24354 TS |
10838 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
10839 | (long) min_range, (long) max_range, | |
10840 | (long) imm_expr.X_add_number); | |
74cd071d | 10841 | } |
df58fc94 | 10842 | INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
10843 | imm_expr.X_op = O_absent; |
10844 | s = expr_end; | |
10845 | continue; | |
10846 | ||
90ecf173 | 10847 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
df58fc94 | 10848 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10849 | my_getExpression (&imm_expr, s); |
10850 | check_absolute_expr (ip, &imm_expr); | |
10851 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
10852 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
10853 | if (imm_expr.X_add_number < min_range || | |
10854 | imm_expr.X_add_number > max_range) | |
10855 | { | |
a9e24354 TS |
10856 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
10857 | (long) min_range, (long) max_range, | |
10858 | (long) imm_expr.X_add_number); | |
74cd071d | 10859 | } |
df58fc94 | 10860 | INSERT_OPERAND (0, IMM10, *ip, imm_expr.X_add_number); |
74cd071d CF |
10861 | imm_expr.X_op = O_absent; |
10862 | s = expr_end; | |
10863 | continue; | |
10864 | ||
a9e24354 | 10865 | case '!': /* MT usermode flag bit. */ |
df58fc94 | 10866 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
10867 | my_getExpression (&imm_expr, s); |
10868 | check_absolute_expr (ip, &imm_expr); | |
10869 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
10870 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
10871 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 10872 | INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
10873 | imm_expr.X_op = O_absent; |
10874 | s = expr_end; | |
10875 | continue; | |
10876 | ||
a9e24354 | 10877 | case '$': /* MT load high flag bit. */ |
df58fc94 | 10878 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
10879 | my_getExpression (&imm_expr, s); |
10880 | check_absolute_expr (ip, &imm_expr); | |
10881 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
10882 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
10883 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 10884 | INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
10885 | imm_expr.X_op = O_absent; |
10886 | s = expr_end; | |
10887 | continue; | |
10888 | ||
90ecf173 | 10889 | case '*': /* Four DSP accumulators in bits 18,19. */ |
df58fc94 | 10890 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
10891 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
10892 | s[3] >= '0' && s[3] <= '3') | |
10893 | { | |
10894 | regno = s[3] - '0'; | |
10895 | s += 4; | |
df58fc94 | 10896 | INSERT_OPERAND (0, MTACC_T, *ip, regno); |
ef2e4d86 CF |
10897 | continue; |
10898 | } | |
10899 | else | |
10900 | as_bad (_("Invalid dsp/smartmips acc register")); | |
10901 | break; | |
10902 | ||
90ecf173 | 10903 | case '&': /* Four DSP accumulators in bits 13,14. */ |
df58fc94 | 10904 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
10905 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
10906 | s[3] >= '0' && s[3] <= '3') | |
10907 | { | |
10908 | regno = s[3] - '0'; | |
10909 | s += 4; | |
df58fc94 | 10910 | INSERT_OPERAND (0, MTACC_D, *ip, regno); |
ef2e4d86 CF |
10911 | continue; |
10912 | } | |
10913 | else | |
10914 | as_bad (_("Invalid dsp/smartmips acc register")); | |
10915 | break; | |
10916 | ||
252b5132 | 10917 | case ',': |
a339155f | 10918 | ++argnum; |
252b5132 RH |
10919 | if (*s++ == *args) |
10920 | continue; | |
10921 | s--; | |
10922 | switch (*++args) | |
10923 | { | |
10924 | case 'r': | |
10925 | case 'v': | |
df58fc94 | 10926 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 RH |
10927 | continue; |
10928 | ||
10929 | case 'w': | |
df58fc94 | 10930 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
38487616 TS |
10931 | continue; |
10932 | ||
252b5132 | 10933 | case 'W': |
df58fc94 RS |
10934 | gas_assert (!mips_opts.micromips); |
10935 | INSERT_OPERAND (0, FT, *ip, lastregno); | |
252b5132 RH |
10936 | continue; |
10937 | ||
10938 | case 'V': | |
df58fc94 | 10939 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 RH |
10940 | continue; |
10941 | } | |
10942 | break; | |
10943 | ||
10944 | case '(': | |
10945 | /* Handle optional base register. | |
10946 | Either the base register is omitted or | |
bdaaa2e1 | 10947 | we must have a left paren. */ |
252b5132 RH |
10948 | /* This is dependent on the next operand specifier |
10949 | is a base register specification. */ | |
df58fc94 RS |
10950 | gas_assert (args[1] == 'b' |
10951 | || (mips_opts.micromips | |
10952 | && args[1] == 'm' | |
10953 | && (args[2] == 'l' || args[2] == 'n' | |
10954 | || args[2] == 's' || args[2] == 'a'))); | |
10955 | if (*s == '\0' && args[1] == 'b') | |
252b5132 | 10956 | return; |
df58fc94 | 10957 | /* Fall through. */ |
252b5132 | 10958 | |
90ecf173 | 10959 | case ')': /* These must match exactly. */ |
df58fc94 RS |
10960 | if (*s++ == *args) |
10961 | continue; | |
10962 | break; | |
10963 | ||
10964 | case '[': /* These must match exactly. */ | |
60b63b72 | 10965 | case ']': |
df58fc94 | 10966 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
10967 | if (*s++ == *args) |
10968 | continue; | |
10969 | break; | |
10970 | ||
af7ee8bf CD |
10971 | case '+': /* Opcode extension character. */ |
10972 | switch (*++args) | |
10973 | { | |
9bcd4f99 TS |
10974 | case '1': /* UDI immediates. */ |
10975 | case '2': | |
10976 | case '3': | |
10977 | case '4': | |
df58fc94 | 10978 | gas_assert (!mips_opts.micromips); |
9bcd4f99 TS |
10979 | { |
10980 | const struct mips_immed *imm = mips_immed; | |
10981 | ||
10982 | while (imm->type && imm->type != *args) | |
10983 | ++imm; | |
10984 | if (! imm->type) | |
10985 | internalError (); | |
10986 | my_getExpression (&imm_expr, s); | |
10987 | check_absolute_expr (ip, &imm_expr); | |
10988 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
10989 | { | |
10990 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
10991 | imm->desc ? imm->desc : ip->insn_mo->name, | |
10992 | (unsigned long) imm_expr.X_add_number, | |
10993 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 10994 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
10995 | } |
10996 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
10997 | << imm->shift); | |
10998 | imm_expr.X_op = O_absent; | |
10999 | s = expr_end; | |
11000 | } | |
11001 | continue; | |
90ecf173 | 11002 | |
071742cf CD |
11003 | case 'A': /* ins/ext position, becomes LSB. */ |
11004 | limlo = 0; | |
11005 | limhi = 31; | |
5f74bc13 CD |
11006 | goto do_lsb; |
11007 | case 'E': | |
11008 | limlo = 32; | |
11009 | limhi = 63; | |
11010 | goto do_lsb; | |
90ecf173 | 11011 | do_lsb: |
071742cf CD |
11012 | my_getExpression (&imm_expr, s); |
11013 | check_absolute_expr (ip, &imm_expr); | |
11014 | if ((unsigned long) imm_expr.X_add_number < limlo | |
11015 | || (unsigned long) imm_expr.X_add_number > limhi) | |
11016 | { | |
11017 | as_bad (_("Improper position (%lu)"), | |
11018 | (unsigned long) imm_expr.X_add_number); | |
11019 | imm_expr.X_add_number = limlo; | |
11020 | } | |
11021 | lastpos = imm_expr.X_add_number; | |
df58fc94 RS |
11022 | INSERT_OPERAND (mips_opts.micromips, |
11023 | EXTLSB, *ip, imm_expr.X_add_number); | |
071742cf CD |
11024 | imm_expr.X_op = O_absent; |
11025 | s = expr_end; | |
11026 | continue; | |
11027 | ||
11028 | case 'B': /* ins size, becomes MSB. */ | |
11029 | limlo = 1; | |
11030 | limhi = 32; | |
5f74bc13 CD |
11031 | goto do_msb; |
11032 | case 'F': | |
11033 | limlo = 33; | |
11034 | limhi = 64; | |
11035 | goto do_msb; | |
90ecf173 | 11036 | do_msb: |
071742cf CD |
11037 | my_getExpression (&imm_expr, s); |
11038 | check_absolute_expr (ip, &imm_expr); | |
11039 | /* Check for negative input so that small negative numbers | |
11040 | will not succeed incorrectly. The checks against | |
11041 | (pos+size) transitively check "size" itself, | |
11042 | assuming that "pos" is reasonable. */ | |
11043 | if ((long) imm_expr.X_add_number < 0 | |
11044 | || ((unsigned long) imm_expr.X_add_number | |
11045 | + lastpos) < limlo | |
11046 | || ((unsigned long) imm_expr.X_add_number | |
11047 | + lastpos) > limhi) | |
11048 | { | |
11049 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
11050 | (unsigned long) imm_expr.X_add_number, | |
11051 | (unsigned long) lastpos); | |
11052 | imm_expr.X_add_number = limlo - lastpos; | |
11053 | } | |
df58fc94 RS |
11054 | INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip, |
11055 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
11056 | imm_expr.X_op = O_absent; |
11057 | s = expr_end; | |
11058 | continue; | |
11059 | ||
11060 | case 'C': /* ext size, becomes MSBD. */ | |
11061 | limlo = 1; | |
11062 | limhi = 32; | |
5f74bc13 CD |
11063 | goto do_msbd; |
11064 | case 'G': | |
11065 | limlo = 33; | |
11066 | limhi = 64; | |
11067 | goto do_msbd; | |
11068 | case 'H': | |
11069 | limlo = 33; | |
11070 | limhi = 64; | |
11071 | goto do_msbd; | |
90ecf173 | 11072 | do_msbd: |
071742cf CD |
11073 | my_getExpression (&imm_expr, s); |
11074 | check_absolute_expr (ip, &imm_expr); | |
11075 | /* Check for negative input so that small negative numbers | |
11076 | will not succeed incorrectly. The checks against | |
11077 | (pos+size) transitively check "size" itself, | |
11078 | assuming that "pos" is reasonable. */ | |
11079 | if ((long) imm_expr.X_add_number < 0 | |
11080 | || ((unsigned long) imm_expr.X_add_number | |
11081 | + lastpos) < limlo | |
11082 | || ((unsigned long) imm_expr.X_add_number | |
11083 | + lastpos) > limhi) | |
11084 | { | |
11085 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
11086 | (unsigned long) imm_expr.X_add_number, | |
11087 | (unsigned long) lastpos); | |
11088 | imm_expr.X_add_number = limlo - lastpos; | |
11089 | } | |
df58fc94 RS |
11090 | INSERT_OPERAND (mips_opts.micromips, |
11091 | EXTMSBD, *ip, imm_expr.X_add_number - 1); | |
071742cf CD |
11092 | imm_expr.X_op = O_absent; |
11093 | s = expr_end; | |
11094 | continue; | |
af7ee8bf | 11095 | |
bbcc0807 CD |
11096 | case 'D': |
11097 | /* +D is for disassembly only; never match. */ | |
11098 | break; | |
11099 | ||
5f74bc13 CD |
11100 | case 'I': |
11101 | /* "+I" is like "I", except that imm2_expr is used. */ | |
11102 | my_getExpression (&imm2_expr, s); | |
11103 | if (imm2_expr.X_op != O_big | |
11104 | && imm2_expr.X_op != O_constant) | |
11105 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
11106 | if (HAVE_32BIT_GPRS) |
11107 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
11108 | s = expr_end; |
11109 | continue; | |
11110 | ||
707bfff6 | 11111 | case 'T': /* Coprocessor register. */ |
df58fc94 | 11112 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11113 | /* +T is for disassembly only; never match. */ |
11114 | break; | |
11115 | ||
707bfff6 | 11116 | case 't': /* Coprocessor register number. */ |
df58fc94 | 11117 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11118 | if (s[0] == '$' && ISDIGIT (s[1])) |
11119 | { | |
11120 | ++s; | |
11121 | regno = 0; | |
11122 | do | |
11123 | { | |
11124 | regno *= 10; | |
11125 | regno += *s - '0'; | |
11126 | ++s; | |
11127 | } | |
11128 | while (ISDIGIT (*s)); | |
11129 | if (regno > 31) | |
11130 | as_bad (_("Invalid register number (%d)"), regno); | |
11131 | else | |
11132 | { | |
df58fc94 | 11133 | INSERT_OPERAND (0, RT, *ip, regno); |
ef2e4d86 CF |
11134 | continue; |
11135 | } | |
11136 | } | |
11137 | else | |
11138 | as_bad (_("Invalid coprocessor 0 register number")); | |
11139 | break; | |
11140 | ||
bb35fb24 NC |
11141 | case 'x': |
11142 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
11143 | is not in the valid range. */ | |
df58fc94 | 11144 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11145 | my_getExpression (&imm_expr, s); |
11146 | check_absolute_expr (ip, &imm_expr); | |
11147 | if ((unsigned) imm_expr.X_add_number > 31) | |
11148 | { | |
11149 | as_bad (_("Improper bit index (%lu)"), | |
11150 | (unsigned long) imm_expr.X_add_number); | |
11151 | imm_expr.X_add_number = 0; | |
11152 | } | |
df58fc94 | 11153 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11154 | imm_expr.X_op = O_absent; |
11155 | s = expr_end; | |
11156 | continue; | |
11157 | ||
11158 | case 'X': | |
11159 | /* bbit[01] bit index when bbit is used but we generate | |
11160 | bbit[01]32 because the index is over 32. Move to the | |
11161 | next candidate if index is not in the valid range. */ | |
df58fc94 | 11162 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11163 | my_getExpression (&imm_expr, s); |
11164 | check_absolute_expr (ip, &imm_expr); | |
11165 | if ((unsigned) imm_expr.X_add_number < 32 | |
11166 | || (unsigned) imm_expr.X_add_number > 63) | |
11167 | break; | |
df58fc94 | 11168 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11169 | imm_expr.X_op = O_absent; |
11170 | s = expr_end; | |
11171 | continue; | |
11172 | ||
11173 | case 'p': | |
11174 | /* cins, cins32, exts and exts32 position field. Give error | |
11175 | if it's not in the valid range. */ | |
df58fc94 | 11176 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11177 | my_getExpression (&imm_expr, s); |
11178 | check_absolute_expr (ip, &imm_expr); | |
11179 | if ((unsigned) imm_expr.X_add_number > 31) | |
11180 | { | |
11181 | as_bad (_("Improper position (%lu)"), | |
11182 | (unsigned long) imm_expr.X_add_number); | |
11183 | imm_expr.X_add_number = 0; | |
11184 | } | |
11185 | /* Make the pos explicit to simplify +S. */ | |
11186 | lastpos = imm_expr.X_add_number + 32; | |
df58fc94 | 11187 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11188 | imm_expr.X_op = O_absent; |
11189 | s = expr_end; | |
11190 | continue; | |
11191 | ||
11192 | case 'P': | |
11193 | /* cins, cins32, exts and exts32 position field. Move to | |
11194 | the next candidate if it's not in the valid range. */ | |
df58fc94 | 11195 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11196 | my_getExpression (&imm_expr, s); |
11197 | check_absolute_expr (ip, &imm_expr); | |
11198 | if ((unsigned) imm_expr.X_add_number < 32 | |
11199 | || (unsigned) imm_expr.X_add_number > 63) | |
11200 | break; | |
11201 | lastpos = imm_expr.X_add_number; | |
df58fc94 | 11202 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11203 | imm_expr.X_op = O_absent; |
11204 | s = expr_end; | |
11205 | continue; | |
11206 | ||
11207 | case 's': | |
11208 | /* cins and exts length-minus-one field. */ | |
df58fc94 | 11209 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11210 | my_getExpression (&imm_expr, s); |
11211 | check_absolute_expr (ip, &imm_expr); | |
11212 | if ((unsigned long) imm_expr.X_add_number > 31) | |
11213 | { | |
11214 | as_bad (_("Improper size (%lu)"), | |
11215 | (unsigned long) imm_expr.X_add_number); | |
11216 | imm_expr.X_add_number = 0; | |
11217 | } | |
df58fc94 | 11218 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11219 | imm_expr.X_op = O_absent; |
11220 | s = expr_end; | |
11221 | continue; | |
11222 | ||
11223 | case 'S': | |
11224 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
11225 | length-minus-one field. */ | |
df58fc94 | 11226 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11227 | my_getExpression (&imm_expr, s); |
11228 | check_absolute_expr (ip, &imm_expr); | |
11229 | if ((long) imm_expr.X_add_number < 0 | |
11230 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
11231 | { | |
11232 | as_bad (_("Improper size (%lu)"), | |
11233 | (unsigned long) imm_expr.X_add_number); | |
11234 | imm_expr.X_add_number = 0; | |
11235 | } | |
df58fc94 | 11236 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11237 | imm_expr.X_op = O_absent; |
11238 | s = expr_end; | |
11239 | continue; | |
11240 | ||
dd3cbb7e NC |
11241 | case 'Q': |
11242 | /* seqi/snei immediate field. */ | |
df58fc94 | 11243 | gas_assert (!mips_opts.micromips); |
dd3cbb7e NC |
11244 | my_getExpression (&imm_expr, s); |
11245 | check_absolute_expr (ip, &imm_expr); | |
11246 | if ((long) imm_expr.X_add_number < -512 | |
11247 | || (long) imm_expr.X_add_number >= 512) | |
11248 | { | |
11249 | as_bad (_("Improper immediate (%ld)"), | |
11250 | (long) imm_expr.X_add_number); | |
11251 | imm_expr.X_add_number = 0; | |
11252 | } | |
df58fc94 | 11253 | INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number); |
dd3cbb7e NC |
11254 | imm_expr.X_op = O_absent; |
11255 | s = expr_end; | |
11256 | continue; | |
11257 | ||
98675402 | 11258 | case 'a': /* 8-bit signed offset in bit 6 */ |
df58fc94 | 11259 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11260 | my_getExpression (&imm_expr, s); |
11261 | check_absolute_expr (ip, &imm_expr); | |
11262 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
11263 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
11264 | if (imm_expr.X_add_number < min_range | |
11265 | || imm_expr.X_add_number > max_range) | |
11266 | { | |
c95354ed | 11267 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11268 | (long) min_range, (long) max_range, |
11269 | (long) imm_expr.X_add_number); | |
11270 | } | |
df58fc94 | 11271 | INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number); |
98675402 RS |
11272 | imm_expr.X_op = O_absent; |
11273 | s = expr_end; | |
11274 | continue; | |
11275 | ||
11276 | case 'b': /* 8-bit signed offset in bit 3 */ | |
df58fc94 | 11277 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11278 | my_getExpression (&imm_expr, s); |
11279 | check_absolute_expr (ip, &imm_expr); | |
11280 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
11281 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
11282 | if (imm_expr.X_add_number < min_range | |
11283 | || imm_expr.X_add_number > max_range) | |
11284 | { | |
c95354ed | 11285 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11286 | (long) min_range, (long) max_range, |
11287 | (long) imm_expr.X_add_number); | |
11288 | } | |
df58fc94 | 11289 | INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number); |
98675402 RS |
11290 | imm_expr.X_op = O_absent; |
11291 | s = expr_end; | |
11292 | continue; | |
11293 | ||
11294 | case 'c': /* 9-bit signed offset in bit 6 */ | |
df58fc94 | 11295 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11296 | my_getExpression (&imm_expr, s); |
11297 | check_absolute_expr (ip, &imm_expr); | |
11298 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
11299 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
11300 | /* We check the offset range before adjusted. */ |
11301 | min_range <<= 4; | |
11302 | max_range <<= 4; | |
98675402 RS |
11303 | if (imm_expr.X_add_number < min_range |
11304 | || imm_expr.X_add_number > max_range) | |
11305 | { | |
c95354ed | 11306 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11307 | (long) min_range, (long) max_range, |
11308 | (long) imm_expr.X_add_number); | |
11309 | } | |
c95354ed MX |
11310 | if (imm_expr.X_add_number & 0xf) |
11311 | { | |
11312 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
11313 | (long) imm_expr.X_add_number); | |
11314 | } | |
11315 | /* Right shift 4 bits to adjust the offset operand. */ | |
df58fc94 RS |
11316 | INSERT_OPERAND (0, OFFSET_C, *ip, |
11317 | imm_expr.X_add_number >> 4); | |
98675402 RS |
11318 | imm_expr.X_op = O_absent; |
11319 | s = expr_end; | |
11320 | continue; | |
11321 | ||
11322 | case 'z': | |
df58fc94 | 11323 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11324 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) |
11325 | break; | |
11326 | if (regno == AT && mips_opts.at) | |
11327 | { | |
11328 | if (mips_opts.at == ATREG) | |
11329 | as_warn (_("used $at without \".set noat\"")); | |
11330 | else | |
11331 | as_warn (_("used $%u with \".set at=$%u\""), | |
11332 | regno, mips_opts.at); | |
11333 | } | |
df58fc94 | 11334 | INSERT_OPERAND (0, RZ, *ip, regno); |
98675402 RS |
11335 | continue; |
11336 | ||
11337 | case 'Z': | |
df58fc94 | 11338 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11339 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) |
11340 | break; | |
df58fc94 | 11341 | INSERT_OPERAND (0, FZ, *ip, regno); |
98675402 RS |
11342 | continue; |
11343 | ||
af7ee8bf | 11344 | default: |
df58fc94 | 11345 | as_bad (_("Internal error: bad %s opcode " |
90ecf173 | 11346 | "(unknown extension operand type `+%c'): %s %s"), |
df58fc94 | 11347 | mips_opts.micromips ? "microMIPS" : "MIPS", |
90ecf173 | 11348 | *args, insn->name, insn->args); |
af7ee8bf CD |
11349 | /* Further processing is fruitless. */ |
11350 | return; | |
11351 | } | |
11352 | break; | |
11353 | ||
df58fc94 RS |
11354 | case '.': /* 10-bit offset. */ |
11355 | case '~': /* 12-bit offset. */ | |
11356 | gas_assert (mips_opts.micromips); | |
11357 | { | |
11358 | int shift = *args == '.' ? 9 : 11; | |
11359 | size_t i; | |
11360 | ||
11361 | /* Check whether there is only a single bracketed expression | |
11362 | left. If so, it must be the base register and the | |
11363 | constant must be zero. */ | |
11364 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
11365 | continue; | |
11366 | ||
11367 | /* If this value won't fit into the offset, then go find | |
11368 | a macro that will generate a 16- or 32-bit offset code | |
11369 | pattern. */ | |
11370 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); | |
11371 | if ((i == 0 && (imm_expr.X_op != O_constant | |
11372 | || imm_expr.X_add_number >= 1 << shift | |
11373 | || imm_expr.X_add_number < -1 << shift)) | |
11374 | || i > 0) | |
11375 | { | |
11376 | imm_expr.X_op = O_absent; | |
11377 | break; | |
11378 | } | |
11379 | if (shift == 9) | |
11380 | INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number); | |
11381 | else | |
11382 | INSERT_OPERAND (1, OFFSET12, *ip, imm_expr.X_add_number); | |
11383 | imm_expr.X_op = O_absent; | |
11384 | s = expr_end; | |
11385 | } | |
11386 | continue; | |
11387 | ||
252b5132 RH |
11388 | case '<': /* must be at least one digit */ |
11389 | /* | |
11390 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
11391 | * than 31 or less than 0, then the shift amount should be |
11392 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
11393 | * We issue a warning and mask out all but the low 5 bits. |
11394 | */ | |
11395 | my_getExpression (&imm_expr, s); | |
11396 | check_absolute_expr (ip, &imm_expr); | |
11397 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11398 | as_warn (_("Improper shift amount (%lu)"), |
11399 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 RS |
11400 | INSERT_OPERAND (mips_opts.micromips, |
11401 | SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
11402 | imm_expr.X_op = O_absent; |
11403 | s = expr_end; | |
11404 | continue; | |
11405 | ||
11406 | case '>': /* shift amount minus 32 */ | |
11407 | my_getExpression (&imm_expr, s); | |
11408 | check_absolute_expr (ip, &imm_expr); | |
11409 | if ((unsigned long) imm_expr.X_add_number < 32 | |
11410 | || (unsigned long) imm_expr.X_add_number > 63) | |
11411 | break; | |
df58fc94 RS |
11412 | INSERT_OPERAND (mips_opts.micromips, |
11413 | SHAMT, *ip, imm_expr.X_add_number - 32); | |
252b5132 RH |
11414 | imm_expr.X_op = O_absent; |
11415 | s = expr_end; | |
11416 | continue; | |
11417 | ||
90ecf173 MR |
11418 | case 'k': /* CACHE code. */ |
11419 | case 'h': /* PREFX code. */ | |
11420 | case '1': /* SYNC type. */ | |
252b5132 RH |
11421 | my_getExpression (&imm_expr, s); |
11422 | check_absolute_expr (ip, &imm_expr); | |
11423 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11424 | as_warn (_("Invalid value for `%s' (%lu)"), |
11425 | ip->insn_mo->name, | |
11426 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11427 | switch (*args) |
d954098f | 11428 | { |
df58fc94 RS |
11429 | case 'k': |
11430 | if (mips_fix_cn63xxp1 | |
11431 | && !mips_opts.micromips | |
11432 | && strcmp ("pref", insn->name) == 0) | |
d954098f DD |
11433 | switch (imm_expr.X_add_number) |
11434 | { | |
11435 | case 5: | |
11436 | case 25: | |
11437 | case 26: | |
11438 | case 27: | |
11439 | case 28: | |
11440 | case 29: | |
11441 | case 30: | |
11442 | case 31: /* These are ok. */ | |
11443 | break; | |
11444 | ||
11445 | default: /* The rest must be changed to 28. */ | |
11446 | imm_expr.X_add_number = 28; | |
11447 | break; | |
11448 | } | |
df58fc94 RS |
11449 | INSERT_OPERAND (mips_opts.micromips, |
11450 | CACHE, *ip, imm_expr.X_add_number); | |
11451 | break; | |
11452 | case 'h': | |
11453 | INSERT_OPERAND (mips_opts.micromips, | |
11454 | PREFX, *ip, imm_expr.X_add_number); | |
11455 | break; | |
11456 | case '1': | |
11457 | INSERT_OPERAND (mips_opts.micromips, | |
11458 | STYPE, *ip, imm_expr.X_add_number); | |
11459 | break; | |
d954098f | 11460 | } |
252b5132 RH |
11461 | imm_expr.X_op = O_absent; |
11462 | s = expr_end; | |
11463 | continue; | |
11464 | ||
90ecf173 | 11465 | case 'c': /* BREAK code. */ |
df58fc94 RS |
11466 | { |
11467 | unsigned long mask = (mips_opts.micromips | |
11468 | ? MICROMIPSOP_MASK_CODE | |
11469 | : OP_MASK_CODE); | |
11470 | ||
11471 | my_getExpression (&imm_expr, s); | |
11472 | check_absolute_expr (ip, &imm_expr); | |
11473 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11474 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11475 | ip->insn_mo->name, | |
11476 | mask, (unsigned long) imm_expr.X_add_number); | |
11477 | INSERT_OPERAND (mips_opts.micromips, | |
11478 | CODE, *ip, imm_expr.X_add_number); | |
11479 | imm_expr.X_op = O_absent; | |
11480 | s = expr_end; | |
11481 | } | |
252b5132 RH |
11482 | continue; |
11483 | ||
90ecf173 | 11484 | case 'q': /* Lower BREAK code. */ |
df58fc94 RS |
11485 | { |
11486 | unsigned long mask = (mips_opts.micromips | |
11487 | ? MICROMIPSOP_MASK_CODE2 | |
11488 | : OP_MASK_CODE2); | |
11489 | ||
11490 | my_getExpression (&imm_expr, s); | |
11491 | check_absolute_expr (ip, &imm_expr); | |
11492 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11493 | as_warn (_("Lower code for %s not in range 0..%lu (%lu)"), | |
11494 | ip->insn_mo->name, | |
11495 | mask, (unsigned long) imm_expr.X_add_number); | |
11496 | INSERT_OPERAND (mips_opts.micromips, | |
11497 | CODE2, *ip, imm_expr.X_add_number); | |
11498 | imm_expr.X_op = O_absent; | |
11499 | s = expr_end; | |
11500 | } | |
252b5132 RH |
11501 | continue; |
11502 | ||
df58fc94 RS |
11503 | case 'B': /* 20- or 10-bit syscall/break/wait code. */ |
11504 | { | |
11505 | unsigned long mask = (mips_opts.micromips | |
11506 | ? MICROMIPSOP_MASK_CODE10 | |
11507 | : OP_MASK_CODE20); | |
11508 | ||
11509 | my_getExpression (&imm_expr, s); | |
11510 | check_absolute_expr (ip, &imm_expr); | |
11511 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11512 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11513 | ip->insn_mo->name, | |
11514 | mask, (unsigned long) imm_expr.X_add_number); | |
11515 | if (mips_opts.micromips) | |
11516 | INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number); | |
11517 | else | |
11518 | INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number); | |
11519 | imm_expr.X_op = O_absent; | |
11520 | s = expr_end; | |
11521 | } | |
252b5132 RH |
11522 | continue; |
11523 | ||
df58fc94 RS |
11524 | case 'C': /* 25- or 23-bit coprocessor code. */ |
11525 | { | |
11526 | unsigned long mask = (mips_opts.micromips | |
11527 | ? MICROMIPSOP_MASK_COPZ | |
11528 | : OP_MASK_COPZ); | |
11529 | ||
11530 | my_getExpression (&imm_expr, s); | |
11531 | check_absolute_expr (ip, &imm_expr); | |
11532 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11533 | as_warn (_("Coproccesor code > %u bits (%lu)"), | |
11534 | mips_opts.micromips ? 23U : 25U, | |
793b27f4 | 11535 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11536 | INSERT_OPERAND (mips_opts.micromips, |
11537 | COPZ, *ip, imm_expr.X_add_number); | |
11538 | imm_expr.X_op = O_absent; | |
11539 | s = expr_end; | |
11540 | } | |
beae10d5 | 11541 | continue; |
252b5132 | 11542 | |
df58fc94 RS |
11543 | case 'J': /* 19-bit WAIT code. */ |
11544 | gas_assert (!mips_opts.micromips); | |
4372b673 NC |
11545 | my_getExpression (&imm_expr, s); |
11546 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 11547 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
df58fc94 RS |
11548 | { |
11549 | as_warn (_("Illegal 19-bit code (%lu)"), | |
a9e24354 | 11550 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11551 | imm_expr.X_add_number &= OP_MASK_CODE19; |
11552 | } | |
11553 | INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number); | |
4372b673 NC |
11554 | imm_expr.X_op = O_absent; |
11555 | s = expr_end; | |
11556 | continue; | |
11557 | ||
707bfff6 | 11558 | case 'P': /* Performance register. */ |
df58fc94 | 11559 | gas_assert (!mips_opts.micromips); |
beae10d5 | 11560 | my_getExpression (&imm_expr, s); |
252b5132 | 11561 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 11562 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
11563 | as_warn (_("Invalid performance register (%lu)"), |
11564 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11565 | INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number); |
beae10d5 KH |
11566 | imm_expr.X_op = O_absent; |
11567 | s = expr_end; | |
11568 | continue; | |
252b5132 | 11569 | |
707bfff6 | 11570 | case 'G': /* Coprocessor destination register. */ |
df58fc94 RS |
11571 | { |
11572 | unsigned long opcode = ip->insn_opcode; | |
11573 | unsigned long mask; | |
11574 | unsigned int types; | |
11575 | int cop0; | |
11576 | ||
11577 | if (mips_opts.micromips) | |
11578 | { | |
11579 | mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT) | |
11580 | | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS) | |
11581 | | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL)); | |
11582 | opcode &= mask; | |
11583 | switch (opcode) | |
11584 | { | |
11585 | case 0x000000fc: /* mfc0 */ | |
11586 | case 0x000002fc: /* mtc0 */ | |
11587 | case 0x580000fc: /* dmfc0 */ | |
11588 | case 0x580002fc: /* dmtc0 */ | |
11589 | cop0 = 1; | |
11590 | break; | |
11591 | default: | |
11592 | cop0 = 0; | |
11593 | break; | |
11594 | } | |
11595 | } | |
11596 | else | |
11597 | { | |
11598 | opcode = (opcode >> OP_SH_OP) & OP_MASK_OP; | |
11599 | cop0 = opcode == OP_OP_COP0; | |
11600 | } | |
11601 | types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP); | |
11602 | ok = reg_lookup (&s, types, ®no); | |
11603 | if (mips_opts.micromips) | |
11604 | INSERT_OPERAND (1, RS, *ip, regno); | |
11605 | else | |
11606 | INSERT_OPERAND (0, RD, *ip, regno); | |
11607 | if (ok) | |
11608 | { | |
11609 | lastregno = regno; | |
11610 | continue; | |
11611 | } | |
11612 | } | |
11613 | break; | |
707bfff6 | 11614 | |
df58fc94 RS |
11615 | case 'y': /* ALNV.PS source register. */ |
11616 | gas_assert (mips_opts.micromips); | |
11617 | goto do_reg; | |
11618 | case 'x': /* Ignore register name. */ | |
11619 | case 'U': /* Destination register (CLO/CLZ). */ | |
11620 | case 'g': /* Coprocessor destination register. */ | |
11621 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
11622 | case 'b': /* Base register. */ |
11623 | case 'd': /* Destination register. */ | |
11624 | case 's': /* Source register. */ | |
11625 | case 't': /* Target register. */ | |
11626 | case 'r': /* Both target and source. */ | |
11627 | case 'v': /* Both dest and source. */ | |
11628 | case 'w': /* Both dest and target. */ | |
11629 | case 'E': /* Coprocessor target register. */ | |
11630 | case 'K': /* RDHWR destination register. */ | |
90ecf173 | 11631 | case 'z': /* Must be zero register. */ |
df58fc94 | 11632 | do_reg: |
90ecf173 | 11633 | s_reset = s; |
707bfff6 TS |
11634 | if (*args == 'E' || *args == 'K') |
11635 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
11636 | else | |
11637 | { | |
11638 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
11639 | if (regno == AT && mips_opts.at) |
11640 | { | |
11641 | if (mips_opts.at == ATREG) | |
f71d0d44 | 11642 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 11643 | else |
f71d0d44 | 11644 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
11645 | regno, mips_opts.at); |
11646 | } | |
707bfff6 TS |
11647 | } |
11648 | if (ok) | |
252b5132 | 11649 | { |
252b5132 RH |
11650 | c = *args; |
11651 | if (*s == ' ') | |
f9419b05 | 11652 | ++s; |
252b5132 RH |
11653 | if (args[1] != *s) |
11654 | { | |
11655 | if (c == 'r' || c == 'v' || c == 'w') | |
11656 | { | |
11657 | regno = lastregno; | |
11658 | s = s_reset; | |
f9419b05 | 11659 | ++args; |
252b5132 RH |
11660 | } |
11661 | } | |
11662 | /* 'z' only matches $0. */ | |
11663 | if (c == 'z' && regno != 0) | |
11664 | break; | |
11665 | ||
24864476 | 11666 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
11667 | { |
11668 | if (regno == lastregno) | |
90ecf173 MR |
11669 | { |
11670 | insn_error | |
f71d0d44 | 11671 | = _("Source and destination must be different"); |
e7c604dd | 11672 | continue; |
90ecf173 | 11673 | } |
24864476 | 11674 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
11675 | { |
11676 | insn_error | |
f71d0d44 | 11677 | = _("A destination register must be supplied"); |
e7c604dd | 11678 | continue; |
90ecf173 | 11679 | } |
e7c604dd | 11680 | } |
90ecf173 MR |
11681 | /* Now that we have assembled one operand, we use the args |
11682 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
11683 | switch (c) |
11684 | { | |
11685 | case 'r': | |
11686 | case 's': | |
11687 | case 'v': | |
11688 | case 'b': | |
df58fc94 | 11689 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno); |
252b5132 | 11690 | break; |
df58fc94 | 11691 | |
af7ee8bf | 11692 | case 'K': |
df58fc94 RS |
11693 | if (mips_opts.micromips) |
11694 | INSERT_OPERAND (1, RS, *ip, regno); | |
11695 | else | |
11696 | INSERT_OPERAND (0, RD, *ip, regno); | |
11697 | break; | |
11698 | ||
11699 | case 'd': | |
ef2e4d86 | 11700 | case 'g': |
df58fc94 | 11701 | INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno); |
252b5132 | 11702 | break; |
df58fc94 | 11703 | |
4372b673 | 11704 | case 'U': |
df58fc94 RS |
11705 | gas_assert (!mips_opts.micromips); |
11706 | INSERT_OPERAND (0, RD, *ip, regno); | |
11707 | INSERT_OPERAND (0, RT, *ip, regno); | |
4372b673 | 11708 | break; |
df58fc94 | 11709 | |
252b5132 RH |
11710 | case 'w': |
11711 | case 't': | |
11712 | case 'E': | |
df58fc94 RS |
11713 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno); |
11714 | break; | |
11715 | ||
11716 | case 'y': | |
11717 | gas_assert (mips_opts.micromips); | |
11718 | INSERT_OPERAND (1, RS3, *ip, regno); | |
252b5132 | 11719 | break; |
df58fc94 | 11720 | |
252b5132 RH |
11721 | case 'x': |
11722 | /* This case exists because on the r3000 trunc | |
11723 | expands into a macro which requires a gp | |
11724 | register. On the r6000 or r4000 it is | |
11725 | assembled into a single instruction which | |
11726 | ignores the register. Thus the insn version | |
11727 | is MIPS_ISA2 and uses 'x', and the macro | |
11728 | version is MIPS_ISA1 and uses 't'. */ | |
11729 | break; | |
df58fc94 | 11730 | |
252b5132 RH |
11731 | case 'z': |
11732 | /* This case is for the div instruction, which | |
11733 | acts differently if the destination argument | |
11734 | is $0. This only matches $0, and is checked | |
11735 | outside the switch. */ | |
11736 | break; | |
252b5132 RH |
11737 | } |
11738 | lastregno = regno; | |
11739 | continue; | |
11740 | } | |
252b5132 RH |
11741 | switch (*args++) |
11742 | { | |
11743 | case 'r': | |
11744 | case 'v': | |
df58fc94 | 11745 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 | 11746 | continue; |
df58fc94 | 11747 | |
252b5132 | 11748 | case 'w': |
df58fc94 | 11749 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
252b5132 RH |
11750 | continue; |
11751 | } | |
11752 | break; | |
11753 | ||
deec1734 | 11754 | case 'O': /* MDMX alignment immediate constant. */ |
df58fc94 | 11755 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
11756 | my_getExpression (&imm_expr, s); |
11757 | check_absolute_expr (ip, &imm_expr); | |
11758 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 11759 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e | 11760 | (long) imm_expr.X_add_number); |
df58fc94 | 11761 | INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number); |
deec1734 CD |
11762 | imm_expr.X_op = O_absent; |
11763 | s = expr_end; | |
11764 | continue; | |
11765 | ||
11766 | case 'Q': /* MDMX vector, element sel, or const. */ | |
11767 | if (s[0] != '$') | |
11768 | { | |
11769 | /* MDMX Immediate. */ | |
df58fc94 | 11770 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
11771 | my_getExpression (&imm_expr, s); |
11772 | check_absolute_expr (ip, &imm_expr); | |
11773 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
11774 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
11775 | (long) imm_expr.X_add_number); | |
df58fc94 | 11776 | INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number); |
deec1734 CD |
11777 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
11778 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
11779 | else | |
11780 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
11781 | imm_expr.X_op = O_absent; |
11782 | s = expr_end; | |
11783 | continue; | |
11784 | } | |
11785 | /* Not MDMX Immediate. Fall through. */ | |
11786 | case 'X': /* MDMX destination register. */ | |
11787 | case 'Y': /* MDMX source register. */ | |
11788 | case 'Z': /* MDMX target register. */ | |
11789 | is_mdmx = 1; | |
df58fc94 RS |
11790 | case 'W': |
11791 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
11792 | case 'D': /* Floating point destination register. */ |
11793 | case 'S': /* Floating point source register. */ | |
11794 | case 'T': /* Floating point target register. */ | |
11795 | case 'R': /* Floating point source register. */ | |
252b5132 | 11796 | case 'V': |
707bfff6 TS |
11797 | rtype = RTYPE_FPU; |
11798 | if (is_mdmx | |
11799 | || (mips_opts.ase_mdmx | |
11800 | && (ip->insn_mo->pinfo & FP_D) | |
11801 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
11802 | | INSN_COPROC_MEMORY_DELAY | |
11803 | | INSN_LOAD_COPROC_DELAY | |
11804 | | INSN_LOAD_MEMORY_DELAY | |
11805 | | INSN_STORE_MEMORY)))) | |
11806 | rtype |= RTYPE_VEC; | |
252b5132 | 11807 | s_reset = s; |
707bfff6 | 11808 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 11809 | { |
252b5132 | 11810 | if ((regno & 1) != 0 |
ca4e0257 | 11811 | && HAVE_32BIT_FPRS |
90ecf173 | 11812 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
11813 | as_warn (_("Float register should be even, was %d"), |
11814 | regno); | |
11815 | ||
11816 | c = *args; | |
11817 | if (*s == ' ') | |
f9419b05 | 11818 | ++s; |
252b5132 RH |
11819 | if (args[1] != *s) |
11820 | { | |
11821 | if (c == 'V' || c == 'W') | |
11822 | { | |
11823 | regno = lastregno; | |
11824 | s = s_reset; | |
f9419b05 | 11825 | ++args; |
252b5132 RH |
11826 | } |
11827 | } | |
11828 | switch (c) | |
11829 | { | |
11830 | case 'D': | |
deec1734 | 11831 | case 'X': |
df58fc94 | 11832 | INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno); |
252b5132 | 11833 | break; |
df58fc94 | 11834 | |
252b5132 RH |
11835 | case 'V': |
11836 | case 'S': | |
deec1734 | 11837 | case 'Y': |
df58fc94 | 11838 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno); |
252b5132 | 11839 | break; |
df58fc94 | 11840 | |
deec1734 CD |
11841 | case 'Q': |
11842 | /* This is like 'Z', but also needs to fix the MDMX | |
11843 | vector/scalar select bits. Note that the | |
11844 | scalar immediate case is handled above. */ | |
11845 | if (*s == '[') | |
11846 | { | |
11847 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
11848 | int max_el = (is_qh ? 3 : 7); | |
11849 | s++; | |
11850 | my_getExpression(&imm_expr, s); | |
11851 | check_absolute_expr (ip, &imm_expr); | |
11852 | s = expr_end; | |
11853 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
11854 | as_bad (_("Bad element selector %ld"), |
11855 | (long) imm_expr.X_add_number); | |
deec1734 CD |
11856 | imm_expr.X_add_number &= max_el; |
11857 | ip->insn_opcode |= (imm_expr.X_add_number | |
11858 | << (OP_SH_VSEL + | |
11859 | (is_qh ? 2 : 1))); | |
01a3f561 | 11860 | imm_expr.X_op = O_absent; |
deec1734 | 11861 | if (*s != ']') |
20203fb9 | 11862 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
11863 | else |
11864 | s++; | |
11865 | } | |
11866 | else | |
11867 | { | |
11868 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
11869 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
11870 | << OP_SH_VSEL); | |
11871 | else | |
11872 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
11873 | OP_SH_VSEL); | |
11874 | } | |
90ecf173 | 11875 | /* Fall through. */ |
252b5132 RH |
11876 | case 'W': |
11877 | case 'T': | |
deec1734 | 11878 | case 'Z': |
df58fc94 | 11879 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno); |
252b5132 | 11880 | break; |
df58fc94 | 11881 | |
252b5132 | 11882 | case 'R': |
df58fc94 | 11883 | INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno); |
252b5132 RH |
11884 | break; |
11885 | } | |
11886 | lastregno = regno; | |
11887 | continue; | |
11888 | } | |
11889 | ||
252b5132 RH |
11890 | switch (*args++) |
11891 | { | |
11892 | case 'V': | |
df58fc94 | 11893 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 | 11894 | continue; |
df58fc94 | 11895 | |
252b5132 | 11896 | case 'W': |
df58fc94 | 11897 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno); |
252b5132 RH |
11898 | continue; |
11899 | } | |
11900 | break; | |
11901 | ||
11902 | case 'I': | |
11903 | my_getExpression (&imm_expr, s); | |
11904 | if (imm_expr.X_op != O_big | |
11905 | && imm_expr.X_op != O_constant) | |
11906 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
11907 | if (HAVE_32BIT_GPRS) |
11908 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
11909 | s = expr_end; |
11910 | continue; | |
11911 | ||
11912 | case 'A': | |
11913 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 11914 | normalize_address_expr (&offset_expr); |
f6688943 | 11915 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
11916 | s = expr_end; |
11917 | continue; | |
11918 | ||
11919 | case 'F': | |
11920 | case 'L': | |
11921 | case 'f': | |
11922 | case 'l': | |
11923 | { | |
11924 | int f64; | |
ca4e0257 | 11925 | int using_gprs; |
252b5132 RH |
11926 | char *save_in; |
11927 | char *err; | |
11928 | unsigned char temp[8]; | |
11929 | int len; | |
11930 | unsigned int length; | |
11931 | segT seg; | |
11932 | subsegT subseg; | |
11933 | char *p; | |
11934 | ||
11935 | /* These only appear as the last operand in an | |
11936 | instruction, and every instruction that accepts | |
11937 | them in any variant accepts them in all variants. | |
11938 | This means we don't have to worry about backing out | |
11939 | any changes if the instruction does not match. | |
11940 | ||
11941 | The difference between them is the size of the | |
11942 | floating point constant and where it goes. For 'F' | |
11943 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
11944 | is 32 bits. Where the constant is placed is based | |
11945 | on how the MIPS assembler does things: | |
11946 | F -- .rdata | |
11947 | L -- .lit8 | |
11948 | f -- immediate value | |
11949 | l -- .lit4 | |
11950 | ||
11951 | The .lit4 and .lit8 sections are only used if | |
11952 | permitted by the -G argument. | |
11953 | ||
ca4e0257 RS |
11954 | The code below needs to know whether the target register |
11955 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
11956 | 'F' are used with GPR-based instructions and 'l' and | |
11957 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
11958 | |
11959 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 11960 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
11961 | |
11962 | save_in = input_line_pointer; | |
11963 | input_line_pointer = s; | |
11964 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
11965 | length = len; | |
11966 | s = input_line_pointer; | |
11967 | input_line_pointer = save_in; | |
11968 | if (err != NULL && *err != '\0') | |
11969 | { | |
11970 | as_bad (_("Bad floating point constant: %s"), err); | |
11971 | memset (temp, '\0', sizeof temp); | |
11972 | length = f64 ? 8 : 4; | |
11973 | } | |
11974 | ||
9c2799c2 | 11975 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
11976 | |
11977 | if (*args == 'f' | |
11978 | || (*args == 'l' | |
3e722fb5 | 11979 | && (g_switch_value < 4 |
252b5132 RH |
11980 | || (temp[0] == 0 && temp[1] == 0) |
11981 | || (temp[2] == 0 && temp[3] == 0)))) | |
11982 | { | |
11983 | imm_expr.X_op = O_constant; | |
90ecf173 | 11984 | if (!target_big_endian) |
252b5132 RH |
11985 | imm_expr.X_add_number = bfd_getl32 (temp); |
11986 | else | |
11987 | imm_expr.X_add_number = bfd_getb32 (temp); | |
11988 | } | |
11989 | else if (length > 4 | |
90ecf173 | 11990 | && !mips_disable_float_construction |
ca4e0257 RS |
11991 | /* Constants can only be constructed in GPRs and |
11992 | copied to FPRs if the GPRs are at least as wide | |
11993 | as the FPRs. Force the constant into memory if | |
11994 | we are using 64-bit FPRs but the GPRs are only | |
11995 | 32 bits wide. */ | |
11996 | && (using_gprs | |
90ecf173 | 11997 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
11998 | && ((temp[0] == 0 && temp[1] == 0) |
11999 | || (temp[2] == 0 && temp[3] == 0)) | |
12000 | && ((temp[4] == 0 && temp[5] == 0) | |
12001 | || (temp[6] == 0 && temp[7] == 0))) | |
12002 | { | |
ca4e0257 | 12003 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
12004 | instructions. If using 32-bit registers, set |
12005 | imm_expr to the high order 32 bits and offset_expr to | |
12006 | the low order 32 bits. Otherwise, set imm_expr to | |
12007 | the entire 64 bit constant. */ | |
ca4e0257 | 12008 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
12009 | { |
12010 | imm_expr.X_op = O_constant; | |
12011 | offset_expr.X_op = O_constant; | |
90ecf173 | 12012 | if (!target_big_endian) |
252b5132 RH |
12013 | { |
12014 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
12015 | offset_expr.X_add_number = bfd_getl32 (temp); | |
12016 | } | |
12017 | else | |
12018 | { | |
12019 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12020 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
12021 | } | |
12022 | if (offset_expr.X_add_number == 0) | |
12023 | offset_expr.X_op = O_absent; | |
12024 | } | |
12025 | else if (sizeof (imm_expr.X_add_number) > 4) | |
12026 | { | |
12027 | imm_expr.X_op = O_constant; | |
90ecf173 | 12028 | if (!target_big_endian) |
252b5132 RH |
12029 | imm_expr.X_add_number = bfd_getl64 (temp); |
12030 | else | |
12031 | imm_expr.X_add_number = bfd_getb64 (temp); | |
12032 | } | |
12033 | else | |
12034 | { | |
12035 | imm_expr.X_op = O_big; | |
12036 | imm_expr.X_add_number = 4; | |
90ecf173 | 12037 | if (!target_big_endian) |
252b5132 RH |
12038 | { |
12039 | generic_bignum[0] = bfd_getl16 (temp); | |
12040 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
12041 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
12042 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
12043 | } | |
12044 | else | |
12045 | { | |
12046 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
12047 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
12048 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
12049 | generic_bignum[3] = bfd_getb16 (temp); | |
12050 | } | |
12051 | } | |
12052 | } | |
12053 | else | |
12054 | { | |
12055 | const char *newname; | |
12056 | segT new_seg; | |
12057 | ||
12058 | /* Switch to the right section. */ | |
12059 | seg = now_seg; | |
12060 | subseg = now_subseg; | |
12061 | switch (*args) | |
12062 | { | |
12063 | default: /* unused default case avoids warnings. */ | |
12064 | case 'L': | |
12065 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 12066 | if (g_switch_value >= 8) |
252b5132 RH |
12067 | newname = ".lit8"; |
12068 | break; | |
12069 | case 'F': | |
3e722fb5 | 12070 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
12071 | break; |
12072 | case 'l': | |
9c2799c2 | 12073 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
12074 | newname = ".lit4"; |
12075 | break; | |
12076 | } | |
12077 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 12078 | if (IS_ELF) |
252b5132 RH |
12079 | bfd_set_section_flags (stdoutput, new_seg, |
12080 | (SEC_ALLOC | |
12081 | | SEC_LOAD | |
12082 | | SEC_READONLY | |
12083 | | SEC_DATA)); | |
12084 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 12085 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
12086 | record_alignment (new_seg, 4); |
12087 | else | |
12088 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
12089 | if (seg == now_seg) | |
12090 | as_bad (_("Can't use floating point insn in this section")); | |
12091 | ||
df58fc94 RS |
12092 | /* Set the argument to the current address in the |
12093 | section. */ | |
12094 | offset_expr.X_op = O_symbol; | |
12095 | offset_expr.X_add_symbol = symbol_temp_new_now (); | |
12096 | offset_expr.X_add_number = 0; | |
12097 | ||
12098 | /* Put the floating point number into the section. */ | |
12099 | p = frag_more ((int) length); | |
12100 | memcpy (p, temp, length); | |
12101 | ||
12102 | /* Switch back to the original section. */ | |
12103 | subseg_set (seg, subseg); | |
12104 | } | |
12105 | } | |
12106 | continue; | |
12107 | ||
12108 | case 'i': /* 16-bit unsigned immediate. */ | |
12109 | case 'j': /* 16-bit signed immediate. */ | |
12110 | *imm_reloc = BFD_RELOC_LO16; | |
12111 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) | |
12112 | { | |
12113 | int more; | |
12114 | offsetT minval, maxval; | |
12115 | ||
12116 | more = (insn + 1 < past | |
12117 | && strcmp (insn->name, insn[1].name) == 0); | |
12118 | ||
12119 | /* If the expression was written as an unsigned number, | |
12120 | only treat it as signed if there are no more | |
12121 | alternatives. */ | |
12122 | if (more | |
12123 | && *args == 'j' | |
12124 | && sizeof (imm_expr.X_add_number) <= 4 | |
12125 | && imm_expr.X_op == O_constant | |
12126 | && imm_expr.X_add_number < 0 | |
12127 | && imm_expr.X_unsigned | |
12128 | && HAVE_64BIT_GPRS) | |
12129 | break; | |
12130 | ||
12131 | /* For compatibility with older assemblers, we accept | |
12132 | 0x8000-0xffff as signed 16-bit numbers when only | |
12133 | signed numbers are allowed. */ | |
12134 | if (*args == 'i') | |
12135 | minval = 0, maxval = 0xffff; | |
12136 | else if (more) | |
12137 | minval = -0x8000, maxval = 0x7fff; | |
12138 | else | |
12139 | minval = -0x8000, maxval = 0xffff; | |
12140 | ||
12141 | if (imm_expr.X_op != O_constant | |
12142 | || imm_expr.X_add_number < minval | |
12143 | || imm_expr.X_add_number > maxval) | |
12144 | { | |
12145 | if (more) | |
12146 | break; | |
12147 | if (imm_expr.X_op == O_constant | |
12148 | || imm_expr.X_op == O_big) | |
12149 | as_bad (_("Expression out of range")); | |
12150 | } | |
12151 | } | |
12152 | s = expr_end; | |
12153 | continue; | |
12154 | ||
12155 | case 'o': /* 16-bit offset. */ | |
12156 | offset_reloc[0] = BFD_RELOC_LO16; | |
12157 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12158 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12159 | ||
12160 | /* Check whether there is only a single bracketed expression | |
12161 | left. If so, it must be the base register and the | |
12162 | constant must be zero. */ | |
12163 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12164 | { | |
12165 | offset_expr.X_op = O_constant; | |
12166 | offset_expr.X_add_number = 0; | |
12167 | continue; | |
12168 | } | |
12169 | ||
12170 | /* If this value won't fit into a 16 bit offset, then go | |
12171 | find a macro that will generate the 32 bit offset | |
12172 | code pattern. */ | |
12173 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 | |
12174 | && (offset_expr.X_op != O_constant | |
12175 | || offset_expr.X_add_number >= 0x8000 | |
12176 | || offset_expr.X_add_number < -0x8000)) | |
12177 | break; | |
12178 | ||
12179 | s = expr_end; | |
12180 | continue; | |
12181 | ||
12182 | case 'p': /* PC-relative offset. */ | |
12183 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
12184 | my_getExpression (&offset_expr, s); | |
12185 | s = expr_end; | |
12186 | continue; | |
12187 | ||
12188 | case 'u': /* Upper 16 bits. */ | |
12189 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 | |
12190 | && imm_expr.X_op == O_constant | |
12191 | && (imm_expr.X_add_number < 0 | |
12192 | || imm_expr.X_add_number >= 0x10000)) | |
12193 | as_bad (_("lui expression (%lu) not in range 0..65535"), | |
12194 | (unsigned long) imm_expr.X_add_number); | |
12195 | s = expr_end; | |
12196 | continue; | |
12197 | ||
12198 | case 'a': /* 26-bit address. */ | |
12199 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
12200 | my_getExpression (&offset_expr, s); | |
12201 | s = expr_end; | |
12202 | continue; | |
12203 | ||
12204 | case 'N': /* 3-bit branch condition code. */ | |
12205 | case 'M': /* 3-bit compare condition code. */ | |
12206 | rtype = RTYPE_CCC; | |
12207 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) | |
12208 | rtype |= RTYPE_FCC; | |
12209 | if (!reg_lookup (&s, rtype, ®no)) | |
12210 | break; | |
12211 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 | |
12212 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
12213 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
12214 | && (regno & 1) != 0) | |
12215 | as_warn (_("Condition code register should be even for %s, " | |
12216 | "was %d"), | |
12217 | str, regno); | |
12218 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 | |
12219 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
12220 | && (regno & 3) != 0) | |
12221 | as_warn (_("Condition code register should be 0 or 4 for %s, " | |
12222 | "was %d"), | |
12223 | str, regno); | |
12224 | if (*args == 'N') | |
12225 | INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno); | |
12226 | else | |
12227 | INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno); | |
12228 | continue; | |
12229 | ||
12230 | case 'H': | |
12231 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
12232 | s += 2; | |
12233 | if (ISDIGIT (*s)) | |
12234 | { | |
12235 | c = 0; | |
12236 | do | |
12237 | { | |
12238 | c *= 10; | |
12239 | c += *s - '0'; | |
12240 | ++s; | |
12241 | } | |
12242 | while (ISDIGIT (*s)); | |
12243 | } | |
12244 | else | |
12245 | c = 8; /* Invalid sel value. */ | |
12246 | ||
12247 | if (c > 7) | |
12248 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); | |
12249 | INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c); | |
12250 | continue; | |
12251 | ||
12252 | case 'e': | |
12253 | gas_assert (!mips_opts.micromips); | |
12254 | /* Must be at least one digit. */ | |
12255 | my_getExpression (&imm_expr, s); | |
12256 | check_absolute_expr (ip, &imm_expr); | |
12257 | ||
12258 | if ((unsigned long) imm_expr.X_add_number | |
12259 | > (unsigned long) OP_MASK_VECBYTE) | |
12260 | { | |
12261 | as_bad (_("bad byte vector index (%ld)"), | |
12262 | (long) imm_expr.X_add_number); | |
12263 | imm_expr.X_add_number = 0; | |
12264 | } | |
12265 | ||
12266 | INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number); | |
12267 | imm_expr.X_op = O_absent; | |
12268 | s = expr_end; | |
12269 | continue; | |
12270 | ||
12271 | case '%': | |
12272 | gas_assert (!mips_opts.micromips); | |
12273 | my_getExpression (&imm_expr, s); | |
12274 | check_absolute_expr (ip, &imm_expr); | |
12275 | ||
12276 | if ((unsigned long) imm_expr.X_add_number | |
12277 | > (unsigned long) OP_MASK_VECALIGN) | |
12278 | { | |
12279 | as_bad (_("bad byte vector index (%ld)"), | |
12280 | (long) imm_expr.X_add_number); | |
12281 | imm_expr.X_add_number = 0; | |
12282 | } | |
12283 | ||
12284 | INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number); | |
12285 | imm_expr.X_op = O_absent; | |
12286 | s = expr_end; | |
12287 | continue; | |
12288 | ||
12289 | case 'm': /* Opcode extension character. */ | |
12290 | gas_assert (mips_opts.micromips); | |
12291 | c = *++args; | |
12292 | switch (c) | |
12293 | { | |
12294 | case 'r': | |
12295 | if (strncmp (s, "$pc", 3) == 0) | |
12296 | { | |
12297 | s += 3; | |
12298 | continue; | |
12299 | } | |
12300 | break; | |
12301 | ||
12302 | case 'a': | |
12303 | case 'b': | |
12304 | case 'c': | |
12305 | case 'd': | |
12306 | case 'e': | |
12307 | case 'f': | |
12308 | case 'g': | |
12309 | case 'h': | |
12310 | case 'i': | |
12311 | case 'j': | |
12312 | case 'l': | |
12313 | case 'm': | |
12314 | case 'n': | |
12315 | case 'p': | |
12316 | case 'q': | |
12317 | case 's': | |
12318 | case 't': | |
12319 | case 'x': | |
12320 | case 'y': | |
12321 | case 'z': | |
12322 | s_reset = s; | |
12323 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
12324 | if (regno == AT && mips_opts.at) | |
12325 | { | |
12326 | if (mips_opts.at == ATREG) | |
12327 | as_warn (_("Used $at without \".set noat\"")); | |
12328 | else | |
12329 | as_warn (_("Used $%u with \".set at=$%u\""), | |
12330 | regno, mips_opts.at); | |
12331 | } | |
12332 | if (!ok) | |
12333 | { | |
12334 | if (c == 'c') | |
12335 | { | |
12336 | gas_assert (args[1] == ','); | |
12337 | regno = lastregno; | |
12338 | ++args; | |
12339 | } | |
12340 | else if (c == 't') | |
12341 | { | |
12342 | gas_assert (args[1] == ','); | |
12343 | ++args; | |
12344 | continue; /* Nothing to do. */ | |
12345 | } | |
12346 | else | |
12347 | break; | |
12348 | } | |
12349 | ||
12350 | if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4)) | |
12351 | { | |
12352 | if (regno == lastregno) | |
12353 | { | |
12354 | insn_error | |
12355 | = _("Source and destination must be different"); | |
12356 | continue; | |
12357 | } | |
12358 | if (regno == 31 && lastregno == 0xffffffff) | |
12359 | { | |
12360 | insn_error | |
12361 | = _("A destination register must be supplied"); | |
12362 | continue; | |
12363 | } | |
12364 | } | |
12365 | ||
12366 | if (*s == ' ') | |
12367 | ++s; | |
12368 | if (args[1] != *s) | |
12369 | { | |
12370 | if (c == 'e') | |
12371 | { | |
12372 | gas_assert (args[1] == ','); | |
12373 | regno = lastregno; | |
12374 | s = s_reset; | |
12375 | ++args; | |
12376 | } | |
12377 | else if (c == 't') | |
12378 | { | |
12379 | gas_assert (args[1] == ','); | |
12380 | s = s_reset; | |
12381 | ++args; | |
12382 | continue; /* Nothing to do. */ | |
12383 | } | |
12384 | } | |
12385 | ||
12386 | /* Make sure regno is the same as lastregno. */ | |
12387 | if (c == 't' && regno != lastregno) | |
12388 | break; | |
12389 | ||
12390 | /* Make sure regno is the same as destregno. */ | |
12391 | if (c == 'x' && regno != destregno) | |
12392 | break; | |
12393 | ||
12394 | /* We need to save regno, before regno maps to the | |
12395 | microMIPS register encoding. */ | |
12396 | lastregno = regno; | |
12397 | ||
12398 | if (c == 'f') | |
12399 | destregno = regno; | |
12400 | ||
12401 | switch (c) | |
12402 | { | |
12403 | case 'a': | |
12404 | if (regno != GP) | |
12405 | regno = ILLEGAL_REG; | |
12406 | break; | |
12407 | ||
12408 | case 'b': | |
12409 | regno = mips32_to_micromips_reg_b_map[regno]; | |
12410 | break; | |
12411 | ||
12412 | case 'c': | |
12413 | regno = mips32_to_micromips_reg_c_map[regno]; | |
12414 | break; | |
12415 | ||
12416 | case 'd': | |
12417 | regno = mips32_to_micromips_reg_d_map[regno]; | |
12418 | break; | |
12419 | ||
12420 | case 'e': | |
12421 | regno = mips32_to_micromips_reg_e_map[regno]; | |
12422 | break; | |
12423 | ||
12424 | case 'f': | |
12425 | regno = mips32_to_micromips_reg_f_map[regno]; | |
12426 | break; | |
12427 | ||
12428 | case 'g': | |
12429 | regno = mips32_to_micromips_reg_g_map[regno]; | |
12430 | break; | |
12431 | ||
12432 | case 'h': | |
12433 | regno = mips32_to_micromips_reg_h_map[regno]; | |
12434 | break; | |
12435 | ||
12436 | case 'i': | |
12437 | switch (EXTRACT_OPERAND (1, MI, *ip)) | |
12438 | { | |
12439 | case 4: | |
12440 | if (regno == 21) | |
12441 | regno = 3; | |
12442 | else if (regno == 22) | |
12443 | regno = 4; | |
12444 | else if (regno == 5) | |
12445 | regno = 5; | |
12446 | else if (regno == 6) | |
12447 | regno = 6; | |
12448 | else if (regno == 7) | |
12449 | regno = 7; | |
12450 | else | |
12451 | regno = ILLEGAL_REG; | |
12452 | break; | |
12453 | ||
12454 | case 5: | |
12455 | if (regno == 6) | |
12456 | regno = 0; | |
12457 | else if (regno == 7) | |
12458 | regno = 1; | |
12459 | else | |
12460 | regno = ILLEGAL_REG; | |
12461 | break; | |
12462 | ||
12463 | case 6: | |
12464 | if (regno == 7) | |
12465 | regno = 2; | |
12466 | else | |
12467 | regno = ILLEGAL_REG; | |
12468 | break; | |
12469 | ||
12470 | default: | |
12471 | regno = ILLEGAL_REG; | |
12472 | break; | |
12473 | } | |
12474 | break; | |
12475 | ||
12476 | case 'l': | |
12477 | regno = mips32_to_micromips_reg_l_map[regno]; | |
12478 | break; | |
12479 | ||
12480 | case 'm': | |
12481 | regno = mips32_to_micromips_reg_m_map[regno]; | |
12482 | break; | |
12483 | ||
12484 | case 'n': | |
12485 | regno = mips32_to_micromips_reg_n_map[regno]; | |
12486 | break; | |
12487 | ||
12488 | case 'q': | |
12489 | regno = mips32_to_micromips_reg_q_map[regno]; | |
12490 | break; | |
12491 | ||
12492 | case 's': | |
12493 | if (regno != SP) | |
12494 | regno = ILLEGAL_REG; | |
12495 | break; | |
12496 | ||
12497 | case 'y': | |
12498 | if (regno != 31) | |
12499 | regno = ILLEGAL_REG; | |
12500 | break; | |
12501 | ||
12502 | case 'z': | |
12503 | if (regno != ZERO) | |
12504 | regno = ILLEGAL_REG; | |
12505 | break; | |
12506 | ||
12507 | case 'j': /* Do nothing. */ | |
12508 | case 'p': | |
12509 | case 't': | |
12510 | case 'x': | |
12511 | break; | |
12512 | ||
12513 | default: | |
12514 | internalError (); | |
12515 | } | |
12516 | ||
12517 | if (regno == ILLEGAL_REG) | |
12518 | break; | |
12519 | ||
12520 | switch (c) | |
12521 | { | |
12522 | case 'b': | |
12523 | INSERT_OPERAND (1, MB, *ip, regno); | |
12524 | break; | |
12525 | ||
12526 | case 'c': | |
12527 | INSERT_OPERAND (1, MC, *ip, regno); | |
12528 | break; | |
12529 | ||
12530 | case 'd': | |
12531 | INSERT_OPERAND (1, MD, *ip, regno); | |
12532 | break; | |
12533 | ||
12534 | case 'e': | |
12535 | INSERT_OPERAND (1, ME, *ip, regno); | |
12536 | break; | |
12537 | ||
12538 | case 'f': | |
12539 | INSERT_OPERAND (1, MF, *ip, regno); | |
12540 | break; | |
12541 | ||
12542 | case 'g': | |
12543 | INSERT_OPERAND (1, MG, *ip, regno); | |
12544 | break; | |
12545 | ||
12546 | case 'h': | |
12547 | INSERT_OPERAND (1, MH, *ip, regno); | |
12548 | break; | |
12549 | ||
12550 | case 'i': | |
12551 | INSERT_OPERAND (1, MI, *ip, regno); | |
12552 | break; | |
12553 | ||
12554 | case 'j': | |
12555 | INSERT_OPERAND (1, MJ, *ip, regno); | |
12556 | break; | |
12557 | ||
12558 | case 'l': | |
12559 | INSERT_OPERAND (1, ML, *ip, regno); | |
12560 | break; | |
12561 | ||
12562 | case 'm': | |
12563 | INSERT_OPERAND (1, MM, *ip, regno); | |
12564 | break; | |
12565 | ||
12566 | case 'n': | |
12567 | INSERT_OPERAND (1, MN, *ip, regno); | |
12568 | break; | |
12569 | ||
12570 | case 'p': | |
12571 | INSERT_OPERAND (1, MP, *ip, regno); | |
12572 | break; | |
12573 | ||
12574 | case 'q': | |
12575 | INSERT_OPERAND (1, MQ, *ip, regno); | |
12576 | break; | |
12577 | ||
12578 | case 'a': /* Do nothing. */ | |
12579 | case 's': /* Do nothing. */ | |
12580 | case 't': /* Do nothing. */ | |
12581 | case 'x': /* Do nothing. */ | |
12582 | case 'y': /* Do nothing. */ | |
12583 | case 'z': /* Do nothing. */ | |
12584 | break; | |
12585 | ||
12586 | default: | |
12587 | internalError (); | |
12588 | } | |
12589 | continue; | |
12590 | ||
12591 | case 'A': | |
12592 | { | |
12593 | bfd_reloc_code_real_type r[3]; | |
12594 | expressionS ep; | |
12595 | int imm; | |
12596 | ||
12597 | /* Check whether there is only a single bracketed | |
12598 | expression left. If so, it must be the base register | |
12599 | and the constant must be zero. */ | |
12600 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12601 | { | |
12602 | INSERT_OPERAND (1, IMMA, *ip, 0); | |
12603 | continue; | |
12604 | } | |
12605 | ||
12606 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12607 | || !expr_const_in_range (&ep, -64, 64, 2)) | |
12608 | break; | |
12609 | ||
12610 | imm = ep.X_add_number >> 2; | |
12611 | INSERT_OPERAND (1, IMMA, *ip, imm); | |
12612 | } | |
12613 | s = expr_end; | |
12614 | continue; | |
12615 | ||
12616 | case 'B': | |
12617 | { | |
12618 | bfd_reloc_code_real_type r[3]; | |
12619 | expressionS ep; | |
12620 | int imm; | |
12621 | ||
12622 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12623 | || ep.X_op != O_constant) | |
12624 | break; | |
12625 | ||
12626 | for (imm = 0; imm < 8; imm++) | |
12627 | if (micromips_imm_b_map[imm] == ep.X_add_number) | |
12628 | break; | |
12629 | if (imm >= 8) | |
12630 | break; | |
12631 | ||
12632 | INSERT_OPERAND (1, IMMB, *ip, imm); | |
12633 | } | |
12634 | s = expr_end; | |
12635 | continue; | |
12636 | ||
12637 | case 'C': | |
12638 | { | |
12639 | bfd_reloc_code_real_type r[3]; | |
12640 | expressionS ep; | |
12641 | int imm; | |
12642 | ||
12643 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12644 | || ep.X_op != O_constant) | |
12645 | break; | |
12646 | ||
12647 | for (imm = 0; imm < 16; imm++) | |
12648 | if (micromips_imm_c_map[imm] == ep.X_add_number) | |
12649 | break; | |
12650 | if (imm >= 16) | |
12651 | break; | |
12652 | ||
12653 | INSERT_OPERAND (1, IMMC, *ip, imm); | |
12654 | } | |
12655 | s = expr_end; | |
12656 | continue; | |
12657 | ||
12658 | case 'D': /* pc relative offset */ | |
12659 | case 'E': /* pc relative offset */ | |
12660 | my_getExpression (&offset_expr, s); | |
12661 | if (offset_expr.X_op == O_register) | |
12662 | break; | |
12663 | ||
12664 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
12665 | s = expr_end; | |
12666 | continue; | |
12667 | ||
12668 | case 'F': | |
12669 | { | |
12670 | bfd_reloc_code_real_type r[3]; | |
12671 | expressionS ep; | |
12672 | int imm; | |
12673 | ||
12674 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12675 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
12676 | break; | |
12677 | ||
12678 | imm = ep.X_add_number; | |
12679 | INSERT_OPERAND (1, IMMF, *ip, imm); | |
12680 | } | |
12681 | s = expr_end; | |
12682 | continue; | |
12683 | ||
12684 | case 'G': | |
12685 | { | |
12686 | bfd_reloc_code_real_type r[3]; | |
12687 | expressionS ep; | |
12688 | int imm; | |
12689 | ||
12690 | /* Check whether there is only a single bracketed | |
12691 | expression left. If so, it must be the base register | |
12692 | and the constant must be zero. */ | |
12693 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12694 | { | |
12695 | INSERT_OPERAND (1, IMMG, *ip, 0); | |
12696 | continue; | |
12697 | } | |
12698 | ||
12699 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12700 | || !expr_const_in_range (&ep, -1, 15, 0)) | |
12701 | break; | |
12702 | ||
12703 | imm = ep.X_add_number & 15; | |
12704 | INSERT_OPERAND (1, IMMG, *ip, imm); | |
12705 | } | |
12706 | s = expr_end; | |
12707 | continue; | |
12708 | ||
12709 | case 'H': | |
12710 | { | |
12711 | bfd_reloc_code_real_type r[3]; | |
12712 | expressionS ep; | |
12713 | int imm; | |
12714 | ||
12715 | /* Check whether there is only a single bracketed | |
12716 | expression left. If so, it must be the base register | |
12717 | and the constant must be zero. */ | |
12718 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12719 | { | |
12720 | INSERT_OPERAND (1, IMMH, *ip, 0); | |
12721 | continue; | |
12722 | } | |
12723 | ||
12724 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12725 | || !expr_const_in_range (&ep, 0, 16, 1)) | |
12726 | break; | |
12727 | ||
12728 | imm = ep.X_add_number >> 1; | |
12729 | INSERT_OPERAND (1, IMMH, *ip, imm); | |
12730 | } | |
12731 | s = expr_end; | |
12732 | continue; | |
12733 | ||
12734 | case 'I': | |
12735 | { | |
12736 | bfd_reloc_code_real_type r[3]; | |
12737 | expressionS ep; | |
12738 | int imm; | |
12739 | ||
12740 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12741 | || !expr_const_in_range (&ep, -1, 127, 0)) | |
12742 | break; | |
12743 | ||
12744 | imm = ep.X_add_number & 127; | |
12745 | INSERT_OPERAND (1, IMMI, *ip, imm); | |
12746 | } | |
12747 | s = expr_end; | |
12748 | continue; | |
12749 | ||
12750 | case 'J': | |
12751 | { | |
12752 | bfd_reloc_code_real_type r[3]; | |
12753 | expressionS ep; | |
12754 | int imm; | |
12755 | ||
12756 | /* Check whether there is only a single bracketed | |
12757 | expression left. If so, it must be the base register | |
12758 | and the constant must be zero. */ | |
12759 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12760 | { | |
12761 | INSERT_OPERAND (1, IMMJ, *ip, 0); | |
12762 | continue; | |
12763 | } | |
12764 | ||
12765 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12766 | || !expr_const_in_range (&ep, 0, 16, 2)) | |
12767 | break; | |
12768 | ||
12769 | imm = ep.X_add_number >> 2; | |
12770 | INSERT_OPERAND (1, IMMJ, *ip, imm); | |
12771 | } | |
12772 | s = expr_end; | |
12773 | continue; | |
12774 | ||
12775 | case 'L': | |
12776 | { | |
12777 | bfd_reloc_code_real_type r[3]; | |
12778 | expressionS ep; | |
12779 | int imm; | |
12780 | ||
12781 | /* Check whether there is only a single bracketed | |
12782 | expression left. If so, it must be the base register | |
12783 | and the constant must be zero. */ | |
12784 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12785 | { | |
12786 | INSERT_OPERAND (1, IMML, *ip, 0); | |
12787 | continue; | |
12788 | } | |
12789 | ||
12790 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12791 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
12792 | break; | |
12793 | ||
12794 | imm = ep.X_add_number; | |
12795 | INSERT_OPERAND (1, IMML, *ip, imm); | |
12796 | } | |
12797 | s = expr_end; | |
12798 | continue; | |
12799 | ||
12800 | case 'M': | |
12801 | { | |
12802 | bfd_reloc_code_real_type r[3]; | |
12803 | expressionS ep; | |
12804 | int imm; | |
12805 | ||
12806 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12807 | || !expr_const_in_range (&ep, 1, 9, 0)) | |
12808 | break; | |
12809 | ||
12810 | imm = ep.X_add_number & 7; | |
12811 | INSERT_OPERAND (1, IMMM, *ip, imm); | |
12812 | } | |
12813 | s = expr_end; | |
12814 | continue; | |
12815 | ||
12816 | case 'N': /* Register list for lwm and swm. */ | |
12817 | { | |
12818 | /* A comma-separated list of registers and/or | |
12819 | dash-separated contiguous ranges including | |
12820 | both ra and a set of one or more registers | |
12821 | starting at s0 up to s3 which have to be | |
12822 | consecutive, e.g.: | |
12823 | ||
12824 | s0, ra | |
12825 | s0, s1, ra, s2, s3 | |
12826 | s0-s2, ra | |
12827 | ||
12828 | and any permutations of these. */ | |
12829 | unsigned int reglist; | |
12830 | int imm; | |
12831 | ||
12832 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
12833 | break; | |
12834 | ||
12835 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
12836 | break; | |
12837 | ||
12838 | reglist = (reglist >> 17) & 7; | |
12839 | reglist += 1; | |
12840 | if ((reglist & -reglist) != reglist) | |
12841 | break; | |
252b5132 | 12842 | |
df58fc94 RS |
12843 | imm = ffs (reglist) - 1; |
12844 | INSERT_OPERAND (1, IMMN, *ip, imm); | |
12845 | } | |
12846 | continue; | |
252b5132 | 12847 | |
df58fc94 RS |
12848 | case 'O': /* sdbbp 4-bit code. */ |
12849 | { | |
12850 | bfd_reloc_code_real_type r[3]; | |
12851 | expressionS ep; | |
12852 | int imm; | |
12853 | ||
12854 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12855 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
12856 | break; | |
12857 | ||
12858 | imm = ep.X_add_number; | |
12859 | INSERT_OPERAND (1, IMMO, *ip, imm); | |
252b5132 | 12860 | } |
df58fc94 RS |
12861 | s = expr_end; |
12862 | continue; | |
252b5132 | 12863 | |
df58fc94 RS |
12864 | case 'P': |
12865 | { | |
12866 | bfd_reloc_code_real_type r[3]; | |
12867 | expressionS ep; | |
12868 | int imm; | |
5e0116d5 | 12869 | |
df58fc94 RS |
12870 | if (my_getSmallExpression (&ep, r, s) > 0 |
12871 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
12872 | break; | |
5e0116d5 | 12873 | |
df58fc94 RS |
12874 | imm = ep.X_add_number >> 2; |
12875 | INSERT_OPERAND (1, IMMP, *ip, imm); | |
12876 | } | |
12877 | s = expr_end; | |
12878 | continue; | |
5e0116d5 | 12879 | |
df58fc94 RS |
12880 | case 'Q': |
12881 | { | |
12882 | bfd_reloc_code_real_type r[3]; | |
12883 | expressionS ep; | |
12884 | int imm; | |
5e0116d5 | 12885 | |
df58fc94 RS |
12886 | if (my_getSmallExpression (&ep, r, s) > 0 |
12887 | || !expr_const_in_range (&ep, -0x400000, 0x400000, 2)) | |
12888 | break; | |
252b5132 | 12889 | |
df58fc94 RS |
12890 | imm = ep.X_add_number >> 2; |
12891 | INSERT_OPERAND (1, IMMQ, *ip, imm); | |
12892 | } | |
12893 | s = expr_end; | |
12894 | continue; | |
4614d845 | 12895 | |
df58fc94 RS |
12896 | case 'U': |
12897 | { | |
12898 | bfd_reloc_code_real_type r[3]; | |
12899 | expressionS ep; | |
12900 | int imm; | |
12901 | ||
12902 | /* Check whether there is only a single bracketed | |
12903 | expression left. If so, it must be the base register | |
12904 | and the constant must be zero. */ | |
12905 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12906 | { | |
12907 | INSERT_OPERAND (1, IMMU, *ip, 0); | |
12908 | continue; | |
12909 | } | |
12910 | ||
12911 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12912 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
12913 | break; | |
12914 | ||
12915 | imm = ep.X_add_number >> 2; | |
12916 | INSERT_OPERAND (1, IMMU, *ip, imm); | |
12917 | } | |
12918 | s = expr_end; | |
5e0116d5 | 12919 | continue; |
252b5132 | 12920 | |
df58fc94 RS |
12921 | case 'W': |
12922 | { | |
12923 | bfd_reloc_code_real_type r[3]; | |
12924 | expressionS ep; | |
12925 | int imm; | |
252b5132 | 12926 | |
df58fc94 RS |
12927 | if (my_getSmallExpression (&ep, r, s) > 0 |
12928 | || !expr_const_in_range (&ep, 0, 64, 2)) | |
12929 | break; | |
252b5132 | 12930 | |
df58fc94 RS |
12931 | imm = ep.X_add_number >> 2; |
12932 | INSERT_OPERAND (1, IMMW, *ip, imm); | |
12933 | } | |
12934 | s = expr_end; | |
12935 | continue; | |
252b5132 | 12936 | |
df58fc94 RS |
12937 | case 'X': |
12938 | { | |
12939 | bfd_reloc_code_real_type r[3]; | |
12940 | expressionS ep; | |
12941 | int imm; | |
252b5132 | 12942 | |
df58fc94 RS |
12943 | if (my_getSmallExpression (&ep, r, s) > 0 |
12944 | || !expr_const_in_range (&ep, -8, 8, 0)) | |
12945 | break; | |
252b5132 | 12946 | |
df58fc94 RS |
12947 | imm = ep.X_add_number; |
12948 | INSERT_OPERAND (1, IMMX, *ip, imm); | |
12949 | } | |
12950 | s = expr_end; | |
12951 | continue; | |
252b5132 | 12952 | |
df58fc94 RS |
12953 | case 'Y': |
12954 | { | |
12955 | bfd_reloc_code_real_type r[3]; | |
12956 | expressionS ep; | |
12957 | int imm; | |
156c2f8b | 12958 | |
df58fc94 RS |
12959 | if (my_getSmallExpression (&ep, r, s) > 0 |
12960 | || expr_const_in_range (&ep, -2, 2, 2) | |
12961 | || !expr_const_in_range (&ep, -258, 258, 2)) | |
12962 | break; | |
156c2f8b | 12963 | |
df58fc94 RS |
12964 | imm = ep.X_add_number >> 2; |
12965 | imm = ((imm >> 1) & ~0xff) | (imm & 0xff); | |
12966 | INSERT_OPERAND (1, IMMY, *ip, imm); | |
12967 | } | |
12968 | s = expr_end; | |
12969 | continue; | |
60b63b72 | 12970 | |
df58fc94 RS |
12971 | case 'Z': |
12972 | { | |
12973 | bfd_reloc_code_real_type r[3]; | |
12974 | expressionS ep; | |
12975 | ||
12976 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12977 | || !expr_const_in_range (&ep, 0, 1, 0)) | |
12978 | break; | |
12979 | } | |
12980 | s = expr_end; | |
12981 | continue; | |
12982 | ||
12983 | default: | |
12984 | as_bad (_("Internal error: bad microMIPS opcode " | |
12985 | "(unknown extension operand type `m%c'): %s %s"), | |
12986 | *args, insn->name, insn->args); | |
12987 | /* Further processing is fruitless. */ | |
12988 | return; | |
60b63b72 | 12989 | } |
df58fc94 | 12990 | break; |
60b63b72 | 12991 | |
df58fc94 RS |
12992 | case 'n': /* Register list for 32-bit lwm and swm. */ |
12993 | gas_assert (mips_opts.micromips); | |
12994 | { | |
12995 | /* A comma-separated list of registers and/or | |
12996 | dash-separated contiguous ranges including | |
12997 | at least one of ra and a set of one or more | |
12998 | registers starting at s0 up to s7 and then | |
12999 | s8 which have to be consecutive, e.g.: | |
13000 | ||
13001 | ra | |
13002 | s0 | |
13003 | ra, s0, s1, s2 | |
13004 | s0-s8 | |
13005 | s0-s5, ra | |
13006 | ||
13007 | and any permutations of these. */ | |
13008 | unsigned int reglist; | |
13009 | int imm; | |
13010 | int ra; | |
13011 | ||
13012 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13013 | break; | |
13014 | ||
13015 | if ((reglist & 0x3f00ffff) != 0) | |
13016 | break; | |
13017 | ||
13018 | ra = (reglist >> 27) & 0x10; | |
13019 | reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
13020 | reglist += 1; | |
13021 | if ((reglist & -reglist) != reglist) | |
13022 | break; | |
13023 | ||
13024 | imm = (ffs (reglist) - 1) | ra; | |
13025 | INSERT_OPERAND (1, RT, *ip, imm); | |
13026 | imm_expr.X_op = O_absent; | |
13027 | } | |
60b63b72 RS |
13028 | continue; |
13029 | ||
df58fc94 RS |
13030 | case '|': /* 4-bit trap code. */ |
13031 | gas_assert (mips_opts.micromips); | |
60b63b72 RS |
13032 | my_getExpression (&imm_expr, s); |
13033 | check_absolute_expr (ip, &imm_expr); | |
60b63b72 | 13034 | if ((unsigned long) imm_expr.X_add_number |
df58fc94 RS |
13035 | > MICROMIPSOP_MASK_TRAP) |
13036 | as_bad (_("Trap code (%lu) for %s not in 0..15 range"), | |
13037 | (unsigned long) imm_expr.X_add_number, | |
13038 | ip->insn_mo->name); | |
13039 | INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number); | |
60b63b72 RS |
13040 | imm_expr.X_op = O_absent; |
13041 | s = expr_end; | |
13042 | continue; | |
13043 | ||
252b5132 | 13044 | default: |
f71d0d44 | 13045 | as_bad (_("Bad char = '%c'\n"), *args); |
252b5132 RH |
13046 | internalError (); |
13047 | } | |
13048 | break; | |
13049 | } | |
13050 | /* Args don't match. */ | |
df58fc94 RS |
13051 | s = argsStart; |
13052 | insn_error = _("Illegal operands"); | |
13053 | if (insn + 1 < past && !strcmp (insn->name, insn[1].name)) | |
252b5132 RH |
13054 | { |
13055 | ++insn; | |
252b5132 RH |
13056 | continue; |
13057 | } | |
df58fc94 RS |
13058 | else if (wrong_delay_slot_insns && need_delay_slot_ok) |
13059 | { | |
13060 | gas_assert (firstinsn); | |
13061 | need_delay_slot_ok = FALSE; | |
13062 | past = insn + 1; | |
13063 | insn = firstinsn; | |
13064 | continue; | |
13065 | } | |
252b5132 RH |
13066 | return; |
13067 | } | |
13068 | } | |
13069 | ||
0499d65b TS |
13070 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
13071 | ||
252b5132 RH |
13072 | /* This routine assembles an instruction into its binary format when |
13073 | assembling for the mips16. As a side effect, it sets one of the | |
df58fc94 RS |
13074 | global variables imm_reloc or offset_reloc to the type of relocation |
13075 | to do if one of the operands is an address expression. It also sets | |
13076 | forced_insn_length to the resulting instruction size in bytes if the | |
13077 | user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
13078 | |
13079 | static void | |
17a2f251 | 13080 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
13081 | { |
13082 | char *s; | |
13083 | const char *args; | |
13084 | struct mips_opcode *insn; | |
13085 | char *argsstart; | |
13086 | unsigned int regno; | |
13087 | unsigned int lastregno = 0; | |
13088 | char *s_reset; | |
d6f16593 | 13089 | size_t i; |
252b5132 RH |
13090 | |
13091 | insn_error = NULL; | |
13092 | ||
df58fc94 | 13093 | forced_insn_length = 0; |
252b5132 | 13094 | |
3882b010 | 13095 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
13096 | ; |
13097 | switch (*s) | |
13098 | { | |
13099 | case '\0': | |
13100 | break; | |
13101 | ||
13102 | case ' ': | |
13103 | *s++ = '\0'; | |
13104 | break; | |
13105 | ||
13106 | case '.': | |
13107 | if (s[1] == 't' && s[2] == ' ') | |
13108 | { | |
13109 | *s = '\0'; | |
df58fc94 | 13110 | forced_insn_length = 2; |
252b5132 RH |
13111 | s += 3; |
13112 | break; | |
13113 | } | |
13114 | else if (s[1] == 'e' && s[2] == ' ') | |
13115 | { | |
13116 | *s = '\0'; | |
df58fc94 | 13117 | forced_insn_length = 4; |
252b5132 RH |
13118 | s += 3; |
13119 | break; | |
13120 | } | |
13121 | /* Fall through. */ | |
13122 | default: | |
13123 | insn_error = _("unknown opcode"); | |
13124 | return; | |
13125 | } | |
13126 | ||
df58fc94 RS |
13127 | if (mips_opts.noautoextend && !forced_insn_length) |
13128 | forced_insn_length = 2; | |
252b5132 RH |
13129 | |
13130 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
13131 | { | |
13132 | insn_error = _("unrecognized opcode"); | |
13133 | return; | |
13134 | } | |
13135 | ||
13136 | argsstart = s; | |
13137 | for (;;) | |
13138 | { | |
9b3f89ee TS |
13139 | bfd_boolean ok; |
13140 | ||
9c2799c2 | 13141 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 13142 | |
037b32b9 | 13143 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
13144 | if (! ok) |
13145 | { | |
13146 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
13147 | && strcmp (insn->name, insn[1].name) == 0) | |
13148 | { | |
13149 | ++insn; | |
13150 | continue; | |
13151 | } | |
13152 | else | |
13153 | { | |
13154 | if (!insn_error) | |
13155 | { | |
13156 | static char buf[100]; | |
13157 | sprintf (buf, | |
13158 | _("opcode not supported on this processor: %s (%s)"), | |
13159 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
13160 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
13161 | insn_error = buf; | |
13162 | } | |
13163 | return; | |
13164 | } | |
13165 | } | |
13166 | ||
1e915849 | 13167 | create_insn (ip, insn); |
252b5132 | 13168 | imm_expr.X_op = O_absent; |
f6688943 TS |
13169 | imm_reloc[0] = BFD_RELOC_UNUSED; |
13170 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
13171 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 13172 | imm2_expr.X_op = O_absent; |
252b5132 | 13173 | offset_expr.X_op = O_absent; |
f6688943 TS |
13174 | offset_reloc[0] = BFD_RELOC_UNUSED; |
13175 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13176 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
13177 | for (args = insn->args; 1; ++args) |
13178 | { | |
13179 | int c; | |
13180 | ||
13181 | if (*s == ' ') | |
13182 | ++s; | |
13183 | ||
13184 | /* In this switch statement we call break if we did not find | |
13185 | a match, continue if we did find a match, or return if we | |
13186 | are done. */ | |
13187 | ||
13188 | c = *args; | |
13189 | switch (c) | |
13190 | { | |
13191 | case '\0': | |
13192 | if (*s == '\0') | |
13193 | { | |
13194 | /* Stuff the immediate value in now, if we can. */ | |
13195 | if (imm_expr.X_op == O_constant | |
f6688943 | 13196 | && *imm_reloc > BFD_RELOC_UNUSED |
738e5348 RS |
13197 | && *imm_reloc != BFD_RELOC_MIPS16_GOT16 |
13198 | && *imm_reloc != BFD_RELOC_MIPS16_CALL16 | |
252b5132 RH |
13199 | && insn->pinfo != INSN_MACRO) |
13200 | { | |
d6f16593 MR |
13201 | valueT tmp; |
13202 | ||
13203 | switch (*offset_reloc) | |
13204 | { | |
13205 | case BFD_RELOC_MIPS16_HI16_S: | |
13206 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
13207 | break; | |
13208 | ||
13209 | case BFD_RELOC_MIPS16_HI16: | |
13210 | tmp = imm_expr.X_add_number >> 16; | |
13211 | break; | |
13212 | ||
13213 | case BFD_RELOC_MIPS16_LO16: | |
13214 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
13215 | - 0x8000; | |
13216 | break; | |
13217 | ||
13218 | case BFD_RELOC_UNUSED: | |
13219 | tmp = imm_expr.X_add_number; | |
13220 | break; | |
13221 | ||
13222 | default: | |
13223 | internalError (); | |
13224 | } | |
13225 | *offset_reloc = BFD_RELOC_UNUSED; | |
13226 | ||
c4e7957c | 13227 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
df58fc94 RS |
13228 | tmp, TRUE, forced_insn_length == 2, |
13229 | forced_insn_length == 4, &ip->insn_opcode, | |
252b5132 RH |
13230 | &ip->use_extend, &ip->extend); |
13231 | imm_expr.X_op = O_absent; | |
f6688943 | 13232 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
13233 | } |
13234 | ||
13235 | return; | |
13236 | } | |
13237 | break; | |
13238 | ||
13239 | case ',': | |
13240 | if (*s++ == c) | |
13241 | continue; | |
13242 | s--; | |
13243 | switch (*++args) | |
13244 | { | |
13245 | case 'v': | |
bf12938e | 13246 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
13247 | continue; |
13248 | case 'w': | |
bf12938e | 13249 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13250 | continue; |
13251 | } | |
13252 | break; | |
13253 | ||
13254 | case '(': | |
13255 | case ')': | |
13256 | if (*s++ == c) | |
13257 | continue; | |
13258 | break; | |
13259 | ||
13260 | case 'v': | |
13261 | case 'w': | |
13262 | if (s[0] != '$') | |
13263 | { | |
13264 | if (c == 'v') | |
bf12938e | 13265 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 13266 | else |
bf12938e | 13267 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13268 | ++args; |
13269 | continue; | |
13270 | } | |
13271 | /* Fall through. */ | |
13272 | case 'x': | |
13273 | case 'y': | |
13274 | case 'z': | |
13275 | case 'Z': | |
13276 | case '0': | |
13277 | case 'S': | |
13278 | case 'R': | |
13279 | case 'X': | |
13280 | case 'Y': | |
707bfff6 TS |
13281 | s_reset = s; |
13282 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 13283 | { |
707bfff6 | 13284 | if (c == 'v' || c == 'w') |
85b51719 | 13285 | { |
707bfff6 | 13286 | if (c == 'v') |
a9e24354 | 13287 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 13288 | else |
a9e24354 | 13289 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
13290 | ++args; |
13291 | continue; | |
85b51719 | 13292 | } |
707bfff6 | 13293 | break; |
252b5132 RH |
13294 | } |
13295 | ||
13296 | if (*s == ' ') | |
13297 | ++s; | |
13298 | if (args[1] != *s) | |
13299 | { | |
13300 | if (c == 'v' || c == 'w') | |
13301 | { | |
13302 | regno = mips16_to_32_reg_map[lastregno]; | |
13303 | s = s_reset; | |
f9419b05 | 13304 | ++args; |
252b5132 RH |
13305 | } |
13306 | } | |
13307 | ||
13308 | switch (c) | |
13309 | { | |
13310 | case 'x': | |
13311 | case 'y': | |
13312 | case 'z': | |
13313 | case 'v': | |
13314 | case 'w': | |
13315 | case 'Z': | |
13316 | regno = mips32_to_16_reg_map[regno]; | |
13317 | break; | |
13318 | ||
13319 | case '0': | |
13320 | if (regno != 0) | |
13321 | regno = ILLEGAL_REG; | |
13322 | break; | |
13323 | ||
13324 | case 'S': | |
13325 | if (regno != SP) | |
13326 | regno = ILLEGAL_REG; | |
13327 | break; | |
13328 | ||
13329 | case 'R': | |
13330 | if (regno != RA) | |
13331 | regno = ILLEGAL_REG; | |
13332 | break; | |
13333 | ||
13334 | case 'X': | |
13335 | case 'Y': | |
741fe287 MR |
13336 | if (regno == AT && mips_opts.at) |
13337 | { | |
13338 | if (mips_opts.at == ATREG) | |
13339 | as_warn (_("used $at without \".set noat\"")); | |
13340 | else | |
13341 | as_warn (_("used $%u with \".set at=$%u\""), | |
13342 | regno, mips_opts.at); | |
13343 | } | |
252b5132 RH |
13344 | break; |
13345 | ||
13346 | default: | |
13347 | internalError (); | |
13348 | } | |
13349 | ||
13350 | if (regno == ILLEGAL_REG) | |
13351 | break; | |
13352 | ||
13353 | switch (c) | |
13354 | { | |
13355 | case 'x': | |
13356 | case 'v': | |
bf12938e | 13357 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
13358 | break; |
13359 | case 'y': | |
13360 | case 'w': | |
bf12938e | 13361 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
13362 | break; |
13363 | case 'z': | |
bf12938e | 13364 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
13365 | break; |
13366 | case 'Z': | |
bf12938e | 13367 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
13368 | case '0': |
13369 | case 'S': | |
13370 | case 'R': | |
13371 | break; | |
13372 | case 'X': | |
bf12938e | 13373 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
13374 | break; |
13375 | case 'Y': | |
13376 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 13377 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
13378 | break; |
13379 | default: | |
13380 | internalError (); | |
13381 | } | |
13382 | ||
13383 | lastregno = regno; | |
13384 | continue; | |
13385 | ||
13386 | case 'P': | |
13387 | if (strncmp (s, "$pc", 3) == 0) | |
13388 | { | |
13389 | s += 3; | |
13390 | continue; | |
13391 | } | |
13392 | break; | |
13393 | ||
252b5132 RH |
13394 | case '5': |
13395 | case 'H': | |
13396 | case 'W': | |
13397 | case 'D': | |
13398 | case 'j': | |
252b5132 RH |
13399 | case 'V': |
13400 | case 'C': | |
13401 | case 'U': | |
13402 | case 'k': | |
13403 | case 'K': | |
d6f16593 MR |
13404 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
13405 | if (i > 0) | |
252b5132 | 13406 | { |
d6f16593 | 13407 | if (imm_expr.X_op != O_constant) |
252b5132 | 13408 | { |
df58fc94 | 13409 | forced_insn_length = 4; |
b34976b6 | 13410 | ip->use_extend = TRUE; |
252b5132 | 13411 | ip->extend = 0; |
252b5132 | 13412 | } |
d6f16593 MR |
13413 | else |
13414 | { | |
13415 | /* We need to relax this instruction. */ | |
13416 | *offset_reloc = *imm_reloc; | |
13417 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
13418 | } | |
13419 | s = expr_end; | |
13420 | continue; | |
252b5132 | 13421 | } |
d6f16593 MR |
13422 | *imm_reloc = BFD_RELOC_UNUSED; |
13423 | /* Fall through. */ | |
13424 | case '<': | |
13425 | case '>': | |
13426 | case '[': | |
13427 | case ']': | |
13428 | case '4': | |
13429 | case '8': | |
13430 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
13431 | if (imm_expr.X_op == O_register) |
13432 | { | |
13433 | /* What we thought was an expression turned out to | |
13434 | be a register. */ | |
13435 | ||
13436 | if (s[0] == '(' && args[1] == '(') | |
13437 | { | |
13438 | /* It looks like the expression was omitted | |
13439 | before a register indirection, which means | |
13440 | that the expression is implicitly zero. We | |
13441 | still set up imm_expr, so that we handle | |
13442 | explicit extensions correctly. */ | |
13443 | imm_expr.X_op = O_constant; | |
13444 | imm_expr.X_add_number = 0; | |
f6688943 | 13445 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13446 | continue; |
13447 | } | |
13448 | ||
13449 | break; | |
13450 | } | |
13451 | ||
13452 | /* We need to relax this instruction. */ | |
f6688943 | 13453 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13454 | s = expr_end; |
13455 | continue; | |
13456 | ||
13457 | case 'p': | |
13458 | case 'q': | |
13459 | case 'A': | |
13460 | case 'B': | |
13461 | case 'E': | |
13462 | /* We use offset_reloc rather than imm_reloc for the PC | |
13463 | relative operands. This lets macros with both | |
13464 | immediate and address operands work correctly. */ | |
13465 | my_getExpression (&offset_expr, s); | |
13466 | ||
13467 | if (offset_expr.X_op == O_register) | |
13468 | break; | |
13469 | ||
13470 | /* We need to relax this instruction. */ | |
f6688943 | 13471 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13472 | s = expr_end; |
13473 | continue; | |
13474 | ||
13475 | case '6': /* break code */ | |
13476 | my_getExpression (&imm_expr, s); | |
13477 | check_absolute_expr (ip, &imm_expr); | |
13478 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
13479 | as_warn (_("Invalid value for `%s' (%lu)"), |
13480 | ip->insn_mo->name, | |
13481 | (unsigned long) imm_expr.X_add_number); | |
13482 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
13483 | imm_expr.X_op = O_absent; |
13484 | s = expr_end; | |
13485 | continue; | |
13486 | ||
13487 | case 'a': /* 26 bit address */ | |
13488 | my_getExpression (&offset_expr, s); | |
13489 | s = expr_end; | |
f6688943 | 13490 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
13491 | ip->insn_opcode <<= 16; |
13492 | continue; | |
13493 | ||
13494 | case 'l': /* register list for entry macro */ | |
13495 | case 'L': /* register list for exit macro */ | |
13496 | { | |
13497 | int mask; | |
13498 | ||
13499 | if (c == 'l') | |
13500 | mask = 0; | |
13501 | else | |
13502 | mask = 7 << 3; | |
13503 | while (*s != '\0') | |
13504 | { | |
707bfff6 | 13505 | unsigned int freg, reg1, reg2; |
252b5132 RH |
13506 | |
13507 | while (*s == ' ' || *s == ',') | |
13508 | ++s; | |
707bfff6 | 13509 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 13510 | freg = 0; |
707bfff6 TS |
13511 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
13512 | freg = 1; | |
252b5132 RH |
13513 | else |
13514 | { | |
707bfff6 TS |
13515 | as_bad (_("can't parse register list")); |
13516 | break; | |
252b5132 RH |
13517 | } |
13518 | if (*s == ' ') | |
13519 | ++s; | |
13520 | if (*s != '-') | |
13521 | reg2 = reg1; | |
13522 | else | |
13523 | { | |
13524 | ++s; | |
707bfff6 TS |
13525 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
13526 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 13527 | { |
707bfff6 TS |
13528 | as_bad (_("invalid register list")); |
13529 | break; | |
252b5132 RH |
13530 | } |
13531 | } | |
13532 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
13533 | { | |
13534 | mask &= ~ (7 << 3); | |
13535 | mask |= 5 << 3; | |
13536 | } | |
13537 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
13538 | { | |
13539 | mask &= ~ (7 << 3); | |
13540 | mask |= 6 << 3; | |
13541 | } | |
13542 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
13543 | mask |= (reg2 - 3) << 3; | |
13544 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
13545 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 13546 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
13547 | mask |= 1; |
13548 | else | |
13549 | { | |
13550 | as_bad (_("invalid register list")); | |
13551 | break; | |
13552 | } | |
13553 | } | |
13554 | /* The mask is filled in in the opcode table for the | |
13555 | benefit of the disassembler. We remove it before | |
13556 | applying the actual mask. */ | |
13557 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
13558 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
13559 | } | |
13560 | continue; | |
13561 | ||
0499d65b TS |
13562 | case 'm': /* Register list for save insn. */ |
13563 | case 'M': /* Register list for restore insn. */ | |
13564 | { | |
13565 | int opcode = 0; | |
13566 | int framesz = 0, seen_framesz = 0; | |
91d6fa6a | 13567 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
13568 | |
13569 | while (*s != '\0') | |
13570 | { | |
13571 | unsigned int reg1, reg2; | |
13572 | ||
13573 | SKIP_SPACE_TABS (s); | |
13574 | while (*s == ',') | |
13575 | ++s; | |
13576 | SKIP_SPACE_TABS (s); | |
13577 | ||
13578 | my_getExpression (&imm_expr, s); | |
13579 | if (imm_expr.X_op == O_constant) | |
13580 | { | |
13581 | /* Handle the frame size. */ | |
13582 | if (seen_framesz) | |
13583 | { | |
13584 | as_bad (_("more than one frame size in list")); | |
13585 | break; | |
13586 | } | |
13587 | seen_framesz = 1; | |
13588 | framesz = imm_expr.X_add_number; | |
13589 | imm_expr.X_op = O_absent; | |
13590 | s = expr_end; | |
13591 | continue; | |
13592 | } | |
13593 | ||
707bfff6 | 13594 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
13595 | { |
13596 | as_bad (_("can't parse register list")); | |
13597 | break; | |
13598 | } | |
0499d65b | 13599 | |
707bfff6 TS |
13600 | while (*s == ' ') |
13601 | ++s; | |
13602 | ||
0499d65b TS |
13603 | if (*s != '-') |
13604 | reg2 = reg1; | |
13605 | else | |
13606 | { | |
13607 | ++s; | |
707bfff6 TS |
13608 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
13609 | || reg2 < reg1) | |
0499d65b TS |
13610 | { |
13611 | as_bad (_("can't parse register list")); | |
13612 | break; | |
13613 | } | |
0499d65b TS |
13614 | } |
13615 | ||
13616 | while (reg1 <= reg2) | |
13617 | { | |
13618 | if (reg1 >= 4 && reg1 <= 7) | |
13619 | { | |
3a93f742 | 13620 | if (!seen_framesz) |
0499d65b | 13621 | /* args $a0-$a3 */ |
91d6fa6a | 13622 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
13623 | else |
13624 | /* statics $a0-$a3 */ | |
13625 | statics |= 1 << (reg1 - 4); | |
13626 | } | |
13627 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
13628 | { | |
13629 | /* $s0-$s8 */ | |
13630 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
13631 | } | |
13632 | else if (reg1 == 31) | |
13633 | { | |
13634 | /* Add $ra to insn. */ | |
13635 | opcode |= 0x40; | |
13636 | } | |
13637 | else | |
13638 | { | |
13639 | as_bad (_("unexpected register in list")); | |
13640 | break; | |
13641 | } | |
13642 | if (++reg1 == 24) | |
13643 | reg1 = 30; | |
13644 | } | |
13645 | } | |
13646 | ||
13647 | /* Encode args/statics combination. */ | |
91d6fa6a | 13648 | if (nargs & statics) |
0499d65b | 13649 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 13650 | else if (nargs == 0xf) |
0499d65b TS |
13651 | /* All $a0-$a3 are args. */ |
13652 | opcode |= MIPS16_ALL_ARGS << 16; | |
13653 | else if (statics == 0xf) | |
13654 | /* All $a0-$a3 are statics. */ | |
13655 | opcode |= MIPS16_ALL_STATICS << 16; | |
13656 | else | |
13657 | { | |
13658 | int narg = 0, nstat = 0; | |
13659 | ||
13660 | /* Count arg registers. */ | |
91d6fa6a | 13661 | while (nargs & 0x1) |
0499d65b | 13662 | { |
91d6fa6a | 13663 | nargs >>= 1; |
0499d65b TS |
13664 | narg++; |
13665 | } | |
91d6fa6a | 13666 | if (nargs != 0) |
0499d65b TS |
13667 | as_bad (_("invalid arg register list")); |
13668 | ||
13669 | /* Count static registers. */ | |
13670 | while (statics & 0x8) | |
13671 | { | |
13672 | statics = (statics << 1) & 0xf; | |
13673 | nstat++; | |
13674 | } | |
13675 | if (statics != 0) | |
13676 | as_bad (_("invalid static register list")); | |
13677 | ||
13678 | /* Encode args/statics. */ | |
13679 | opcode |= ((narg << 2) | nstat) << 16; | |
13680 | } | |
13681 | ||
13682 | /* Encode $s0/$s1. */ | |
13683 | if (sregs & (1 << 0)) /* $s0 */ | |
13684 | opcode |= 0x20; | |
13685 | if (sregs & (1 << 1)) /* $s1 */ | |
13686 | opcode |= 0x10; | |
13687 | sregs >>= 2; | |
13688 | ||
13689 | if (sregs != 0) | |
13690 | { | |
13691 | /* Count regs $s2-$s8. */ | |
13692 | int nsreg = 0; | |
13693 | while (sregs & 1) | |
13694 | { | |
13695 | sregs >>= 1; | |
13696 | nsreg++; | |
13697 | } | |
13698 | if (sregs != 0) | |
13699 | as_bad (_("invalid static register list")); | |
13700 | /* Encode $s2-$s8. */ | |
13701 | opcode |= nsreg << 24; | |
13702 | } | |
13703 | ||
13704 | /* Encode frame size. */ | |
13705 | if (!seen_framesz) | |
13706 | as_bad (_("missing frame size")); | |
13707 | else if ((framesz & 7) != 0 || framesz < 0 | |
13708 | || framesz > 0xff * 8) | |
13709 | as_bad (_("invalid frame size")); | |
13710 | else if (framesz != 128 || (opcode >> 16) != 0) | |
13711 | { | |
13712 | framesz /= 8; | |
13713 | opcode |= (((framesz & 0xf0) << 16) | |
13714 | | (framesz & 0x0f)); | |
13715 | } | |
13716 | ||
13717 | /* Finally build the instruction. */ | |
13718 | if ((opcode >> 16) != 0 || framesz == 0) | |
13719 | { | |
13720 | ip->use_extend = TRUE; | |
13721 | ip->extend = opcode >> 16; | |
13722 | } | |
13723 | ip->insn_opcode |= opcode & 0x7f; | |
13724 | } | |
13725 | continue; | |
13726 | ||
252b5132 RH |
13727 | case 'e': /* extend code */ |
13728 | my_getExpression (&imm_expr, s); | |
13729 | check_absolute_expr (ip, &imm_expr); | |
13730 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
13731 | { | |
13732 | as_warn (_("Invalid value for `%s' (%lu)"), | |
13733 | ip->insn_mo->name, | |
13734 | (unsigned long) imm_expr.X_add_number); | |
13735 | imm_expr.X_add_number &= 0x7ff; | |
13736 | } | |
13737 | ip->insn_opcode |= imm_expr.X_add_number; | |
13738 | imm_expr.X_op = O_absent; | |
13739 | s = expr_end; | |
13740 | continue; | |
13741 | ||
13742 | default: | |
13743 | internalError (); | |
13744 | } | |
13745 | break; | |
13746 | } | |
13747 | ||
13748 | /* Args don't match. */ | |
13749 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
13750 | strcmp (insn->name, insn[1].name) == 0) | |
13751 | { | |
13752 | ++insn; | |
13753 | s = argsstart; | |
13754 | continue; | |
13755 | } | |
13756 | ||
13757 | insn_error = _("illegal operands"); | |
13758 | ||
13759 | return; | |
13760 | } | |
13761 | } | |
13762 | ||
13763 | /* This structure holds information we know about a mips16 immediate | |
13764 | argument type. */ | |
13765 | ||
e972090a NC |
13766 | struct mips16_immed_operand |
13767 | { | |
252b5132 RH |
13768 | /* The type code used in the argument string in the opcode table. */ |
13769 | int type; | |
13770 | /* The number of bits in the short form of the opcode. */ | |
13771 | int nbits; | |
13772 | /* The number of bits in the extended form of the opcode. */ | |
13773 | int extbits; | |
13774 | /* The amount by which the short form is shifted when it is used; | |
13775 | for example, the sw instruction has a shift count of 2. */ | |
13776 | int shift; | |
13777 | /* The amount by which the short form is shifted when it is stored | |
13778 | into the instruction code. */ | |
13779 | int op_shift; | |
13780 | /* Non-zero if the short form is unsigned. */ | |
13781 | int unsp; | |
13782 | /* Non-zero if the extended form is unsigned. */ | |
13783 | int extu; | |
13784 | /* Non-zero if the value is PC relative. */ | |
13785 | int pcrel; | |
13786 | }; | |
13787 | ||
13788 | /* The mips16 immediate operand types. */ | |
13789 | ||
13790 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
13791 | { | |
13792 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
13793 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
13794 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
13795 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
13796 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
13797 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13798 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13799 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13800 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13801 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
13802 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
13803 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
13804 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
13805 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
13806 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
13807 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
13808 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
13809 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
13810 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
13811 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
13812 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
13813 | }; | |
13814 | ||
13815 | #define MIPS16_NUM_IMMED \ | |
13816 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
13817 | ||
13818 | /* Handle a mips16 instruction with an immediate value. This or's the | |
13819 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
13820 | whether an extended value is needed; if one is needed, it sets | |
13821 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
13822 | If SMALL is true, an unextended opcode was explicitly requested. | |
13823 | If EXT is true, an extended opcode was explicitly requested. If | |
13824 | WARN is true, warn if EXT does not match reality. */ | |
13825 | ||
13826 | static void | |
17a2f251 TS |
13827 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
13828 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
13829 | unsigned long *insn, bfd_boolean *use_extend, | |
13830 | unsigned short *extend) | |
252b5132 | 13831 | { |
3994f87e | 13832 | const struct mips16_immed_operand *op; |
252b5132 | 13833 | int mintiny, maxtiny; |
b34976b6 | 13834 | bfd_boolean needext; |
252b5132 RH |
13835 | |
13836 | op = mips16_immed_operands; | |
13837 | while (op->type != type) | |
13838 | { | |
13839 | ++op; | |
9c2799c2 | 13840 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
13841 | } |
13842 | ||
13843 | if (op->unsp) | |
13844 | { | |
13845 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13846 | { | |
13847 | mintiny = 1; | |
13848 | maxtiny = 1 << op->nbits; | |
13849 | } | |
13850 | else | |
13851 | { | |
13852 | mintiny = 0; | |
13853 | maxtiny = (1 << op->nbits) - 1; | |
13854 | } | |
13855 | } | |
13856 | else | |
13857 | { | |
13858 | mintiny = - (1 << (op->nbits - 1)); | |
13859 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13860 | } | |
13861 | ||
13862 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
13863 | if (type == 'p' || type == 'q') | |
13864 | val /= 2; | |
13865 | ||
13866 | if ((val & ((1 << op->shift) - 1)) != 0 | |
13867 | || val < (mintiny << op->shift) | |
13868 | || val > (maxtiny << op->shift)) | |
b34976b6 | 13869 | needext = TRUE; |
252b5132 | 13870 | else |
b34976b6 | 13871 | needext = FALSE; |
252b5132 RH |
13872 | |
13873 | if (warn && ext && ! needext) | |
beae10d5 KH |
13874 | as_warn_where (file, line, |
13875 | _("extended operand requested but not required")); | |
252b5132 RH |
13876 | if (small && needext) |
13877 | as_bad_where (file, line, _("invalid unextended operand value")); | |
13878 | ||
13879 | if (small || (! ext && ! needext)) | |
13880 | { | |
13881 | int insnval; | |
13882 | ||
b34976b6 | 13883 | *use_extend = FALSE; |
252b5132 RH |
13884 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
13885 | insnval <<= op->op_shift; | |
13886 | *insn |= insnval; | |
13887 | } | |
13888 | else | |
13889 | { | |
13890 | long minext, maxext; | |
13891 | int extval; | |
13892 | ||
13893 | if (op->extu) | |
13894 | { | |
13895 | minext = 0; | |
13896 | maxext = (1 << op->extbits) - 1; | |
13897 | } | |
13898 | else | |
13899 | { | |
13900 | minext = - (1 << (op->extbits - 1)); | |
13901 | maxext = (1 << (op->extbits - 1)) - 1; | |
13902 | } | |
13903 | if (val < minext || val > maxext) | |
13904 | as_bad_where (file, line, | |
13905 | _("operand value out of range for instruction")); | |
13906 | ||
b34976b6 | 13907 | *use_extend = TRUE; |
252b5132 RH |
13908 | if (op->extbits == 16) |
13909 | { | |
13910 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
13911 | val &= 0x1f; | |
13912 | } | |
13913 | else if (op->extbits == 15) | |
13914 | { | |
13915 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
13916 | val &= 0xf; | |
13917 | } | |
13918 | else | |
13919 | { | |
13920 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
13921 | val = 0; | |
13922 | } | |
13923 | ||
13924 | *extend = (unsigned short) extval; | |
13925 | *insn |= val; | |
13926 | } | |
13927 | } | |
13928 | \f | |
d6f16593 | 13929 | struct percent_op_match |
ad8d3bb3 | 13930 | { |
5e0116d5 RS |
13931 | const char *str; |
13932 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
13933 | }; |
13934 | ||
13935 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 13936 | { |
5e0116d5 | 13937 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 13938 | #ifdef OBJ_ELF |
5e0116d5 RS |
13939 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
13940 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
13941 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
13942 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
13943 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
13944 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
13945 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
13946 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
13947 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
13948 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
13949 | {"%half", BFD_RELOC_16}, | |
13950 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
13951 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
13952 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
13953 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
13954 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
13955 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
13956 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
13957 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
13958 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
13959 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 13960 | #endif |
5e0116d5 | 13961 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
13962 | }; |
13963 | ||
d6f16593 MR |
13964 | static const struct percent_op_match mips16_percent_op[] = |
13965 | { | |
13966 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
13967 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
13968 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
13969 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d6f16593 MR |
13970 | {"%hi", BFD_RELOC_MIPS16_HI16_S} |
13971 | }; | |
13972 | ||
252b5132 | 13973 | |
5e0116d5 RS |
13974 | /* Return true if *STR points to a relocation operator. When returning true, |
13975 | move *STR over the operator and store its relocation code in *RELOC. | |
13976 | Leave both *STR and *RELOC alone when returning false. */ | |
13977 | ||
13978 | static bfd_boolean | |
17a2f251 | 13979 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 13980 | { |
d6f16593 MR |
13981 | const struct percent_op_match *percent_op; |
13982 | size_t limit, i; | |
13983 | ||
13984 | if (mips_opts.mips16) | |
13985 | { | |
13986 | percent_op = mips16_percent_op; | |
13987 | limit = ARRAY_SIZE (mips16_percent_op); | |
13988 | } | |
13989 | else | |
13990 | { | |
13991 | percent_op = mips_percent_op; | |
13992 | limit = ARRAY_SIZE (mips_percent_op); | |
13993 | } | |
76b3015f | 13994 | |
d6f16593 | 13995 | for (i = 0; i < limit; i++) |
5e0116d5 | 13996 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 13997 | { |
3f98094e DJ |
13998 | int len = strlen (percent_op[i].str); |
13999 | ||
14000 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14001 | continue; | |
14002 | ||
5e0116d5 RS |
14003 | *str += strlen (percent_op[i].str); |
14004 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14005 | |
5e0116d5 RS |
14006 | /* Check whether the output BFD supports this relocation. |
14007 | If not, issue an error and fall back on something safe. */ | |
14008 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14009 | { |
20203fb9 | 14010 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14011 | percent_op[i].str); |
01a3f561 | 14012 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14013 | } |
5e0116d5 | 14014 | return TRUE; |
394f9b3a | 14015 | } |
5e0116d5 | 14016 | return FALSE; |
394f9b3a | 14017 | } |
ad8d3bb3 | 14018 | |
ad8d3bb3 | 14019 | |
5e0116d5 RS |
14020 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14021 | expression in *EP and the relocations in the array starting | |
14022 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14023 | |
01a3f561 | 14024 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14025 | |
5e0116d5 | 14026 | static size_t |
17a2f251 TS |
14027 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14028 | char *str) | |
ad8d3bb3 | 14029 | { |
5e0116d5 RS |
14030 | bfd_reloc_code_real_type reversed_reloc[3]; |
14031 | size_t reloc_index, i; | |
09b8f35a RS |
14032 | int crux_depth, str_depth; |
14033 | char *crux; | |
5e0116d5 RS |
14034 | |
14035 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14036 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14037 | of the main expression and with CRUX_DEPTH containing the number | |
14038 | of open brackets at that point. */ | |
14039 | reloc_index = -1; | |
14040 | str_depth = 0; | |
14041 | do | |
fb1b3232 | 14042 | { |
09b8f35a RS |
14043 | reloc_index++; |
14044 | crux = str; | |
14045 | crux_depth = str_depth; | |
14046 | ||
14047 | /* Skip over whitespace and brackets, keeping count of the number | |
14048 | of brackets. */ | |
14049 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14050 | if (*str++ == '(') | |
14051 | str_depth++; | |
5e0116d5 | 14052 | } |
09b8f35a RS |
14053 | while (*str == '%' |
14054 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14055 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14056 | |
09b8f35a | 14057 | my_getExpression (ep, crux); |
5e0116d5 | 14058 | str = expr_end; |
394f9b3a | 14059 | |
5e0116d5 | 14060 | /* Match every open bracket. */ |
09b8f35a | 14061 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14062 | if (*str++ == ')') |
09b8f35a | 14063 | crux_depth--; |
394f9b3a | 14064 | |
09b8f35a | 14065 | if (crux_depth > 0) |
20203fb9 | 14066 | as_bad (_("unclosed '('")); |
394f9b3a | 14067 | |
5e0116d5 | 14068 | expr_end = str; |
252b5132 | 14069 | |
01a3f561 | 14070 | if (reloc_index != 0) |
64bdfcaf RS |
14071 | { |
14072 | prev_reloc_op_frag = frag_now; | |
14073 | for (i = 0; i < reloc_index; i++) | |
14074 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14075 | } | |
fb1b3232 | 14076 | |
5e0116d5 | 14077 | return reloc_index; |
252b5132 RH |
14078 | } |
14079 | ||
14080 | static void | |
17a2f251 | 14081 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14082 | { |
14083 | char *save_in; | |
14084 | ||
14085 | save_in = input_line_pointer; | |
14086 | input_line_pointer = str; | |
14087 | expression (ep); | |
14088 | expr_end = input_line_pointer; | |
14089 | input_line_pointer = save_in; | |
252b5132 RH |
14090 | } |
14091 | ||
252b5132 | 14092 | char * |
17a2f251 | 14093 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14094 | { |
499ac353 | 14095 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14096 | } |
14097 | ||
14098 | void | |
17a2f251 | 14099 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14100 | { |
14101 | if (target_big_endian) | |
14102 | number_to_chars_bigendian (buf, val, n); | |
14103 | else | |
14104 | number_to_chars_littleendian (buf, val, n); | |
14105 | } | |
14106 | \f | |
ae948b86 | 14107 | #ifdef OBJ_ELF |
e013f690 TS |
14108 | static int support_64bit_objects(void) |
14109 | { | |
14110 | const char **list, **l; | |
aa3d8fdf | 14111 | int yes; |
e013f690 TS |
14112 | |
14113 | list = bfd_target_list (); | |
14114 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14115 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14116 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14117 | break; |
aa3d8fdf | 14118 | yes = (*l != NULL); |
e013f690 | 14119 | free (list); |
aa3d8fdf | 14120 | return yes; |
e013f690 | 14121 | } |
ae948b86 | 14122 | #endif /* OBJ_ELF */ |
e013f690 | 14123 | |
78849248 | 14124 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 14125 | |
23fce1e3 NC |
14126 | enum options |
14127 | { | |
14128 | OPTION_MARCH = OPTION_MD_BASE, | |
14129 | OPTION_MTUNE, | |
14130 | OPTION_MIPS1, | |
14131 | OPTION_MIPS2, | |
14132 | OPTION_MIPS3, | |
14133 | OPTION_MIPS4, | |
14134 | OPTION_MIPS5, | |
14135 | OPTION_MIPS32, | |
14136 | OPTION_MIPS64, | |
14137 | OPTION_MIPS32R2, | |
14138 | OPTION_MIPS64R2, | |
14139 | OPTION_MIPS16, | |
14140 | OPTION_NO_MIPS16, | |
14141 | OPTION_MIPS3D, | |
14142 | OPTION_NO_MIPS3D, | |
14143 | OPTION_MDMX, | |
14144 | OPTION_NO_MDMX, | |
14145 | OPTION_DSP, | |
14146 | OPTION_NO_DSP, | |
14147 | OPTION_MT, | |
14148 | OPTION_NO_MT, | |
14149 | OPTION_SMARTMIPS, | |
14150 | OPTION_NO_SMARTMIPS, | |
14151 | OPTION_DSPR2, | |
14152 | OPTION_NO_DSPR2, | |
df58fc94 RS |
14153 | OPTION_MICROMIPS, |
14154 | OPTION_NO_MICROMIPS, | |
23fce1e3 NC |
14155 | OPTION_COMPAT_ARCH_BASE, |
14156 | OPTION_M4650, | |
14157 | OPTION_NO_M4650, | |
14158 | OPTION_M4010, | |
14159 | OPTION_NO_M4010, | |
14160 | OPTION_M4100, | |
14161 | OPTION_NO_M4100, | |
14162 | OPTION_M3900, | |
14163 | OPTION_NO_M3900, | |
14164 | OPTION_M7000_HILO_FIX, | |
6a32d874 CM |
14165 | OPTION_MNO_7000_HILO_FIX, |
14166 | OPTION_FIX_24K, | |
14167 | OPTION_NO_FIX_24K, | |
c67a084a NC |
14168 | OPTION_FIX_LOONGSON2F_JUMP, |
14169 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
14170 | OPTION_FIX_LOONGSON2F_NOP, | |
14171 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
23fce1e3 NC |
14172 | OPTION_FIX_VR4120, |
14173 | OPTION_NO_FIX_VR4120, | |
14174 | OPTION_FIX_VR4130, | |
14175 | OPTION_NO_FIX_VR4130, | |
d954098f DD |
14176 | OPTION_FIX_CN63XXP1, |
14177 | OPTION_NO_FIX_CN63XXP1, | |
23fce1e3 NC |
14178 | OPTION_TRAP, |
14179 | OPTION_BREAK, | |
14180 | OPTION_EB, | |
14181 | OPTION_EL, | |
14182 | OPTION_FP32, | |
14183 | OPTION_GP32, | |
14184 | OPTION_CONSTRUCT_FLOATS, | |
14185 | OPTION_NO_CONSTRUCT_FLOATS, | |
14186 | OPTION_FP64, | |
14187 | OPTION_GP64, | |
14188 | OPTION_RELAX_BRANCH, | |
14189 | OPTION_NO_RELAX_BRANCH, | |
14190 | OPTION_MSHARED, | |
14191 | OPTION_MNO_SHARED, | |
14192 | OPTION_MSYM32, | |
14193 | OPTION_MNO_SYM32, | |
14194 | OPTION_SOFT_FLOAT, | |
14195 | OPTION_HARD_FLOAT, | |
14196 | OPTION_SINGLE_FLOAT, | |
14197 | OPTION_DOUBLE_FLOAT, | |
14198 | OPTION_32, | |
14199 | #ifdef OBJ_ELF | |
14200 | OPTION_CALL_SHARED, | |
14201 | OPTION_CALL_NONPIC, | |
14202 | OPTION_NON_SHARED, | |
14203 | OPTION_XGOT, | |
14204 | OPTION_MABI, | |
14205 | OPTION_N32, | |
14206 | OPTION_64, | |
14207 | OPTION_MDEBUG, | |
14208 | OPTION_NO_MDEBUG, | |
14209 | OPTION_PDR, | |
14210 | OPTION_NO_PDR, | |
14211 | OPTION_MVXWORKS_PIC, | |
14212 | #endif /* OBJ_ELF */ | |
14213 | OPTION_END_OF_ENUM | |
14214 | }; | |
14215 | ||
e972090a NC |
14216 | struct option md_longopts[] = |
14217 | { | |
f9b4148d | 14218 | /* Options which specify architecture. */ |
f9b4148d | 14219 | {"march", required_argument, NULL, OPTION_MARCH}, |
f9b4148d | 14220 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
252b5132 RH |
14221 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
14222 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
252b5132 | 14223 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
252b5132 | 14224 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
252b5132 | 14225 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
ae948b86 | 14226 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
ae948b86 | 14227 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
ae948b86 | 14228 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d | 14229 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
5f74bc13 | 14230 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
f9b4148d CD |
14231 | |
14232 | /* Options which specify Application Specific Extensions (ASEs). */ | |
f9b4148d | 14233 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
f9b4148d | 14234 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f9b4148d | 14235 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
f9b4148d | 14236 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
f9b4148d | 14237 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
f9b4148d | 14238 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
74cd071d | 14239 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
74cd071d | 14240 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
ef2e4d86 | 14241 | {"mmt", no_argument, NULL, OPTION_MT}, |
ef2e4d86 | 14242 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
e16bfa71 | 14243 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
e16bfa71 | 14244 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
8b082fb1 | 14245 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
8b082fb1 | 14246 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
df58fc94 RS |
14247 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, |
14248 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
f9b4148d CD |
14249 | |
14250 | /* Old-style architecture options. Don't add more of these. */ | |
f9b4148d | 14251 | {"m4650", no_argument, NULL, OPTION_M4650}, |
f9b4148d | 14252 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
f9b4148d | 14253 | {"m4010", no_argument, NULL, OPTION_M4010}, |
f9b4148d | 14254 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
f9b4148d | 14255 | {"m4100", no_argument, NULL, OPTION_M4100}, |
f9b4148d | 14256 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
f9b4148d | 14257 | {"m3900", no_argument, NULL, OPTION_M3900}, |
f9b4148d CD |
14258 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
14259 | ||
14260 | /* Options which enable bug fixes. */ | |
f9b4148d | 14261 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
f9b4148d CD |
14262 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
14263 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
c67a084a NC |
14264 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
14265 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
14266 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
14267 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
d766e8ec RS |
14268 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
14269 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
14270 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
14271 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
6a32d874 CM |
14272 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
14273 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
d954098f DD |
14274 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
14275 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
f9b4148d CD |
14276 | |
14277 | /* Miscellaneous options. */ | |
252b5132 RH |
14278 | {"trap", no_argument, NULL, OPTION_TRAP}, |
14279 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
252b5132 RH |
14280 | {"break", no_argument, NULL, OPTION_BREAK}, |
14281 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
252b5132 | 14282 | {"EB", no_argument, NULL, OPTION_EB}, |
252b5132 | 14283 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 14284 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
c97ef257 | 14285 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
119d663a | 14286 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
119d663a | 14287 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
316f5878 | 14288 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
ae948b86 | 14289 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
4a6a3df4 AO |
14290 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
14291 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
14292 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
14293 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
14294 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
14295 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
14296 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
14297 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
037b32b9 AN |
14298 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
14299 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
23fce1e3 NC |
14300 | |
14301 | /* Strictly speaking this next option is ELF specific, | |
14302 | but we allow it for other ports as well in order to | |
14303 | make testing easier. */ | |
14304 | {"32", no_argument, NULL, OPTION_32}, | |
037b32b9 | 14305 | |
f9b4148d | 14306 | /* ELF-specific options. */ |
156c2f8b | 14307 | #ifdef OBJ_ELF |
156c2f8b NC |
14308 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
14309 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
861fb55a | 14310 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
156c2f8b NC |
14311 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
14312 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
ae948b86 | 14313 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e013f690 | 14314 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b | 14315 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a | 14316 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
ecb4347a | 14317 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
dcd410fe | 14318 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
dcd410fe | 14319 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
0a44bf69 | 14320 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
ae948b86 | 14321 | #endif /* OBJ_ELF */ |
f9b4148d | 14322 | |
252b5132 RH |
14323 | {NULL, no_argument, NULL, 0} |
14324 | }; | |
156c2f8b | 14325 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 14326 | |
316f5878 RS |
14327 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14328 | NEW_VALUE. Warn if another value was already specified. Note: | |
14329 | we have to defer parsing the -march and -mtune arguments in order | |
14330 | to handle 'from-abi' correctly, since the ABI might be specified | |
14331 | in a later argument. */ | |
14332 | ||
14333 | static void | |
17a2f251 | 14334 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14335 | { |
14336 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
14337 | as_warn (_("A different %s was already specified, is now %s"), | |
14338 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
14339 | new_value); | |
14340 | ||
14341 | *string_ptr = new_value; | |
14342 | } | |
14343 | ||
252b5132 | 14344 | int |
17a2f251 | 14345 | md_parse_option (int c, char *arg) |
252b5132 RH |
14346 | { |
14347 | switch (c) | |
14348 | { | |
119d663a NC |
14349 | case OPTION_CONSTRUCT_FLOATS: |
14350 | mips_disable_float_construction = 0; | |
14351 | break; | |
bdaaa2e1 | 14352 | |
119d663a NC |
14353 | case OPTION_NO_CONSTRUCT_FLOATS: |
14354 | mips_disable_float_construction = 1; | |
14355 | break; | |
bdaaa2e1 | 14356 | |
252b5132 RH |
14357 | case OPTION_TRAP: |
14358 | mips_trap = 1; | |
14359 | break; | |
14360 | ||
14361 | case OPTION_BREAK: | |
14362 | mips_trap = 0; | |
14363 | break; | |
14364 | ||
14365 | case OPTION_EB: | |
14366 | target_big_endian = 1; | |
14367 | break; | |
14368 | ||
14369 | case OPTION_EL: | |
14370 | target_big_endian = 0; | |
14371 | break; | |
14372 | ||
14373 | case 'O': | |
4ffff32f TS |
14374 | if (arg == NULL) |
14375 | mips_optimize = 1; | |
14376 | else if (arg[0] == '0') | |
14377 | mips_optimize = 0; | |
14378 | else if (arg[0] == '1') | |
252b5132 RH |
14379 | mips_optimize = 1; |
14380 | else | |
14381 | mips_optimize = 2; | |
14382 | break; | |
14383 | ||
14384 | case 'g': | |
14385 | if (arg == NULL) | |
14386 | mips_debug = 2; | |
14387 | else | |
14388 | mips_debug = atoi (arg); | |
252b5132 RH |
14389 | break; |
14390 | ||
14391 | case OPTION_MIPS1: | |
316f5878 | 14392 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
14393 | break; |
14394 | ||
14395 | case OPTION_MIPS2: | |
316f5878 | 14396 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
14397 | break; |
14398 | ||
14399 | case OPTION_MIPS3: | |
316f5878 | 14400 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
14401 | break; |
14402 | ||
14403 | case OPTION_MIPS4: | |
316f5878 | 14404 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
14405 | break; |
14406 | ||
84ea6cf2 | 14407 | case OPTION_MIPS5: |
316f5878 | 14408 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
14409 | break; |
14410 | ||
e7af610e | 14411 | case OPTION_MIPS32: |
316f5878 | 14412 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
14413 | break; |
14414 | ||
af7ee8bf CD |
14415 | case OPTION_MIPS32R2: |
14416 | file_mips_isa = ISA_MIPS32R2; | |
14417 | break; | |
14418 | ||
5f74bc13 CD |
14419 | case OPTION_MIPS64R2: |
14420 | file_mips_isa = ISA_MIPS64R2; | |
14421 | break; | |
14422 | ||
84ea6cf2 | 14423 | case OPTION_MIPS64: |
316f5878 | 14424 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
14425 | break; |
14426 | ||
ec68c924 | 14427 | case OPTION_MTUNE: |
316f5878 RS |
14428 | mips_set_option_string (&mips_tune_string, arg); |
14429 | break; | |
ec68c924 | 14430 | |
316f5878 RS |
14431 | case OPTION_MARCH: |
14432 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14433 | break; |
14434 | ||
14435 | case OPTION_M4650: | |
316f5878 RS |
14436 | mips_set_option_string (&mips_arch_string, "4650"); |
14437 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14438 | break; |
14439 | ||
14440 | case OPTION_NO_M4650: | |
14441 | break; | |
14442 | ||
14443 | case OPTION_M4010: | |
316f5878 RS |
14444 | mips_set_option_string (&mips_arch_string, "4010"); |
14445 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14446 | break; |
14447 | ||
14448 | case OPTION_NO_M4010: | |
14449 | break; | |
14450 | ||
14451 | case OPTION_M4100: | |
316f5878 RS |
14452 | mips_set_option_string (&mips_arch_string, "4100"); |
14453 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14454 | break; |
14455 | ||
14456 | case OPTION_NO_M4100: | |
14457 | break; | |
14458 | ||
252b5132 | 14459 | case OPTION_M3900: |
316f5878 RS |
14460 | mips_set_option_string (&mips_arch_string, "3900"); |
14461 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14462 | break; |
bdaaa2e1 | 14463 | |
252b5132 RH |
14464 | case OPTION_NO_M3900: |
14465 | break; | |
14466 | ||
deec1734 CD |
14467 | case OPTION_MDMX: |
14468 | mips_opts.ase_mdmx = 1; | |
14469 | break; | |
14470 | ||
14471 | case OPTION_NO_MDMX: | |
14472 | mips_opts.ase_mdmx = 0; | |
14473 | break; | |
14474 | ||
74cd071d CF |
14475 | case OPTION_DSP: |
14476 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 14477 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
14478 | break; |
14479 | ||
14480 | case OPTION_NO_DSP: | |
8b082fb1 TS |
14481 | mips_opts.ase_dsp = 0; |
14482 | mips_opts.ase_dspr2 = 0; | |
14483 | break; | |
14484 | ||
14485 | case OPTION_DSPR2: | |
14486 | mips_opts.ase_dspr2 = 1; | |
14487 | mips_opts.ase_dsp = 1; | |
14488 | break; | |
14489 | ||
14490 | case OPTION_NO_DSPR2: | |
14491 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
14492 | mips_opts.ase_dsp = 0; |
14493 | break; | |
14494 | ||
ef2e4d86 CF |
14495 | case OPTION_MT: |
14496 | mips_opts.ase_mt = 1; | |
14497 | break; | |
14498 | ||
14499 | case OPTION_NO_MT: | |
14500 | mips_opts.ase_mt = 0; | |
14501 | break; | |
14502 | ||
df58fc94 RS |
14503 | case OPTION_MICROMIPS: |
14504 | if (mips_opts.mips16 == 1) | |
14505 | { | |
14506 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14507 | return 0; | |
14508 | } | |
14509 | mips_opts.micromips = 1; | |
14510 | mips_no_prev_insn (); | |
14511 | break; | |
14512 | ||
14513 | case OPTION_NO_MICROMIPS: | |
14514 | mips_opts.micromips = 0; | |
14515 | mips_no_prev_insn (); | |
14516 | break; | |
14517 | ||
252b5132 | 14518 | case OPTION_MIPS16: |
df58fc94 RS |
14519 | if (mips_opts.micromips == 1) |
14520 | { | |
14521 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14522 | return 0; | |
14523 | } | |
252b5132 | 14524 | mips_opts.mips16 = 1; |
7d10b47d | 14525 | mips_no_prev_insn (); |
252b5132 RH |
14526 | break; |
14527 | ||
14528 | case OPTION_NO_MIPS16: | |
14529 | mips_opts.mips16 = 0; | |
7d10b47d | 14530 | mips_no_prev_insn (); |
252b5132 RH |
14531 | break; |
14532 | ||
1f25f5d3 CD |
14533 | case OPTION_MIPS3D: |
14534 | mips_opts.ase_mips3d = 1; | |
14535 | break; | |
14536 | ||
14537 | case OPTION_NO_MIPS3D: | |
14538 | mips_opts.ase_mips3d = 0; | |
14539 | break; | |
14540 | ||
e16bfa71 TS |
14541 | case OPTION_SMARTMIPS: |
14542 | mips_opts.ase_smartmips = 1; | |
14543 | break; | |
14544 | ||
14545 | case OPTION_NO_SMARTMIPS: | |
14546 | mips_opts.ase_smartmips = 0; | |
14547 | break; | |
14548 | ||
6a32d874 CM |
14549 | case OPTION_FIX_24K: |
14550 | mips_fix_24k = 1; | |
14551 | break; | |
14552 | ||
14553 | case OPTION_NO_FIX_24K: | |
14554 | mips_fix_24k = 0; | |
14555 | break; | |
14556 | ||
c67a084a NC |
14557 | case OPTION_FIX_LOONGSON2F_JUMP: |
14558 | mips_fix_loongson2f_jump = TRUE; | |
14559 | break; | |
14560 | ||
14561 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14562 | mips_fix_loongson2f_jump = FALSE; | |
14563 | break; | |
14564 | ||
14565 | case OPTION_FIX_LOONGSON2F_NOP: | |
14566 | mips_fix_loongson2f_nop = TRUE; | |
14567 | break; | |
14568 | ||
14569 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
14570 | mips_fix_loongson2f_nop = FALSE; | |
14571 | break; | |
14572 | ||
d766e8ec RS |
14573 | case OPTION_FIX_VR4120: |
14574 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
14575 | break; |
14576 | ||
d766e8ec RS |
14577 | case OPTION_NO_FIX_VR4120: |
14578 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
14579 | break; |
14580 | ||
7d8e00cf RS |
14581 | case OPTION_FIX_VR4130: |
14582 | mips_fix_vr4130 = 1; | |
14583 | break; | |
14584 | ||
14585 | case OPTION_NO_FIX_VR4130: | |
14586 | mips_fix_vr4130 = 0; | |
14587 | break; | |
14588 | ||
d954098f DD |
14589 | case OPTION_FIX_CN63XXP1: |
14590 | mips_fix_cn63xxp1 = TRUE; | |
14591 | break; | |
14592 | ||
14593 | case OPTION_NO_FIX_CN63XXP1: | |
14594 | mips_fix_cn63xxp1 = FALSE; | |
14595 | break; | |
14596 | ||
4a6a3df4 AO |
14597 | case OPTION_RELAX_BRANCH: |
14598 | mips_relax_branch = 1; | |
14599 | break; | |
14600 | ||
14601 | case OPTION_NO_RELAX_BRANCH: | |
14602 | mips_relax_branch = 0; | |
14603 | break; | |
14604 | ||
aa6975fb ILT |
14605 | case OPTION_MSHARED: |
14606 | mips_in_shared = TRUE; | |
14607 | break; | |
14608 | ||
14609 | case OPTION_MNO_SHARED: | |
14610 | mips_in_shared = FALSE; | |
14611 | break; | |
14612 | ||
aed1a261 RS |
14613 | case OPTION_MSYM32: |
14614 | mips_opts.sym32 = TRUE; | |
14615 | break; | |
14616 | ||
14617 | case OPTION_MNO_SYM32: | |
14618 | mips_opts.sym32 = FALSE; | |
14619 | break; | |
14620 | ||
0f074f60 | 14621 | #ifdef OBJ_ELF |
252b5132 RH |
14622 | /* When generating ELF code, we permit -KPIC and -call_shared to |
14623 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
14624 | intended to be compatible with Irix 5. */ | |
14625 | case OPTION_CALL_SHARED: | |
f43abd2b | 14626 | if (!IS_ELF) |
252b5132 RH |
14627 | { |
14628 | as_bad (_("-call_shared is supported only for ELF format")); | |
14629 | return 0; | |
14630 | } | |
14631 | mips_pic = SVR4_PIC; | |
143d77c5 | 14632 | mips_abicalls = TRUE; |
252b5132 RH |
14633 | break; |
14634 | ||
861fb55a DJ |
14635 | case OPTION_CALL_NONPIC: |
14636 | if (!IS_ELF) | |
14637 | { | |
14638 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
14639 | return 0; | |
14640 | } | |
14641 | mips_pic = NO_PIC; | |
14642 | mips_abicalls = TRUE; | |
14643 | break; | |
14644 | ||
252b5132 | 14645 | case OPTION_NON_SHARED: |
f43abd2b | 14646 | if (!IS_ELF) |
252b5132 RH |
14647 | { |
14648 | as_bad (_("-non_shared is supported only for ELF format")); | |
14649 | return 0; | |
14650 | } | |
14651 | mips_pic = NO_PIC; | |
143d77c5 | 14652 | mips_abicalls = FALSE; |
252b5132 RH |
14653 | break; |
14654 | ||
44075ae2 TS |
14655 | /* The -xgot option tells the assembler to use 32 bit offsets |
14656 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
14657 | compatibility. */ |
14658 | case OPTION_XGOT: | |
14659 | mips_big_got = 1; | |
14660 | break; | |
0f074f60 | 14661 | #endif /* OBJ_ELF */ |
252b5132 RH |
14662 | |
14663 | case 'G': | |
6caf9ef4 TS |
14664 | g_switch_value = atoi (arg); |
14665 | g_switch_seen = 1; | |
252b5132 RH |
14666 | break; |
14667 | ||
34ba82a8 TS |
14668 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
14669 | and -mabi=64. */ | |
252b5132 | 14670 | case OPTION_32: |
23fce1e3 NC |
14671 | if (IS_ELF) |
14672 | mips_abi = O32_ABI; | |
14673 | /* We silently ignore -32 for non-ELF targets. This greatly | |
14674 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
14675 | break; |
14676 | ||
23fce1e3 | 14677 | #ifdef OBJ_ELF |
e013f690 | 14678 | case OPTION_N32: |
f43abd2b | 14679 | if (!IS_ELF) |
34ba82a8 TS |
14680 | { |
14681 | as_bad (_("-n32 is supported for ELF format only")); | |
14682 | return 0; | |
14683 | } | |
316f5878 | 14684 | mips_abi = N32_ABI; |
e013f690 | 14685 | break; |
252b5132 | 14686 | |
e013f690 | 14687 | case OPTION_64: |
f43abd2b | 14688 | if (!IS_ELF) |
34ba82a8 TS |
14689 | { |
14690 | as_bad (_("-64 is supported for ELF format only")); | |
14691 | return 0; | |
14692 | } | |
316f5878 | 14693 | mips_abi = N64_ABI; |
f43abd2b | 14694 | if (!support_64bit_objects()) |
e013f690 | 14695 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 14696 | break; |
ae948b86 | 14697 | #endif /* OBJ_ELF */ |
252b5132 | 14698 | |
c97ef257 | 14699 | case OPTION_GP32: |
a325df1d | 14700 | file_mips_gp32 = 1; |
c97ef257 AH |
14701 | break; |
14702 | ||
14703 | case OPTION_GP64: | |
a325df1d | 14704 | file_mips_gp32 = 0; |
c97ef257 | 14705 | break; |
252b5132 | 14706 | |
ca4e0257 | 14707 | case OPTION_FP32: |
a325df1d | 14708 | file_mips_fp32 = 1; |
316f5878 RS |
14709 | break; |
14710 | ||
14711 | case OPTION_FP64: | |
14712 | file_mips_fp32 = 0; | |
ca4e0257 RS |
14713 | break; |
14714 | ||
037b32b9 AN |
14715 | case OPTION_SINGLE_FLOAT: |
14716 | file_mips_single_float = 1; | |
14717 | break; | |
14718 | ||
14719 | case OPTION_DOUBLE_FLOAT: | |
14720 | file_mips_single_float = 0; | |
14721 | break; | |
14722 | ||
14723 | case OPTION_SOFT_FLOAT: | |
14724 | file_mips_soft_float = 1; | |
14725 | break; | |
14726 | ||
14727 | case OPTION_HARD_FLOAT: | |
14728 | file_mips_soft_float = 0; | |
14729 | break; | |
14730 | ||
ae948b86 | 14731 | #ifdef OBJ_ELF |
252b5132 | 14732 | case OPTION_MABI: |
f43abd2b | 14733 | if (!IS_ELF) |
34ba82a8 TS |
14734 | { |
14735 | as_bad (_("-mabi is supported for ELF format only")); | |
14736 | return 0; | |
14737 | } | |
e013f690 | 14738 | if (strcmp (arg, "32") == 0) |
316f5878 | 14739 | mips_abi = O32_ABI; |
e013f690 | 14740 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 14741 | mips_abi = O64_ABI; |
e013f690 | 14742 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 14743 | mips_abi = N32_ABI; |
e013f690 TS |
14744 | else if (strcmp (arg, "64") == 0) |
14745 | { | |
316f5878 | 14746 | mips_abi = N64_ABI; |
e013f690 TS |
14747 | if (! support_64bit_objects()) |
14748 | as_fatal (_("No compiled in support for 64 bit object file " | |
14749 | "format")); | |
14750 | } | |
14751 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 14752 | mips_abi = EABI_ABI; |
e013f690 | 14753 | else |
da0e507f TS |
14754 | { |
14755 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
14756 | return 0; | |
14757 | } | |
252b5132 | 14758 | break; |
e013f690 | 14759 | #endif /* OBJ_ELF */ |
252b5132 | 14760 | |
6b76fefe | 14761 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 14762 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
14763 | break; |
14764 | ||
9ee72ff1 | 14765 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 14766 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
14767 | break; |
14768 | ||
ecb4347a DJ |
14769 | #ifdef OBJ_ELF |
14770 | case OPTION_MDEBUG: | |
b34976b6 | 14771 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
14772 | break; |
14773 | ||
14774 | case OPTION_NO_MDEBUG: | |
b34976b6 | 14775 | mips_flag_mdebug = FALSE; |
ecb4347a | 14776 | break; |
dcd410fe RO |
14777 | |
14778 | case OPTION_PDR: | |
14779 | mips_flag_pdr = TRUE; | |
14780 | break; | |
14781 | ||
14782 | case OPTION_NO_PDR: | |
14783 | mips_flag_pdr = FALSE; | |
14784 | break; | |
0a44bf69 RS |
14785 | |
14786 | case OPTION_MVXWORKS_PIC: | |
14787 | mips_pic = VXWORKS_PIC; | |
14788 | break; | |
ecb4347a DJ |
14789 | #endif /* OBJ_ELF */ |
14790 | ||
252b5132 RH |
14791 | default: |
14792 | return 0; | |
14793 | } | |
14794 | ||
c67a084a NC |
14795 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
14796 | ||
252b5132 RH |
14797 | return 1; |
14798 | } | |
316f5878 RS |
14799 | \f |
14800 | /* Set up globals to generate code for the ISA or processor | |
14801 | described by INFO. */ | |
252b5132 | 14802 | |
252b5132 | 14803 | static void |
17a2f251 | 14804 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 14805 | { |
316f5878 | 14806 | if (info != 0) |
252b5132 | 14807 | { |
fef14a42 TS |
14808 | file_mips_arch = info->cpu; |
14809 | mips_opts.arch = info->cpu; | |
316f5878 | 14810 | mips_opts.isa = info->isa; |
252b5132 | 14811 | } |
252b5132 RH |
14812 | } |
14813 | ||
252b5132 | 14814 | |
316f5878 | 14815 | /* Likewise for tuning. */ |
252b5132 | 14816 | |
316f5878 | 14817 | static void |
17a2f251 | 14818 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
14819 | { |
14820 | if (info != 0) | |
fef14a42 | 14821 | mips_tune = info->cpu; |
316f5878 | 14822 | } |
80cc45a5 | 14823 | |
34ba82a8 | 14824 | |
252b5132 | 14825 | void |
17a2f251 | 14826 | mips_after_parse_args (void) |
e9670677 | 14827 | { |
fef14a42 TS |
14828 | const struct mips_cpu_info *arch_info = 0; |
14829 | const struct mips_cpu_info *tune_info = 0; | |
14830 | ||
e9670677 | 14831 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 14832 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 14833 | { |
6caf9ef4 | 14834 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
14835 | as_bad (_("-G not supported in this configuration.")); |
14836 | g_switch_value = 0; | |
14837 | } | |
14838 | ||
cac012d6 AO |
14839 | if (mips_abi == NO_ABI) |
14840 | mips_abi = MIPS_DEFAULT_ABI; | |
14841 | ||
22923709 RS |
14842 | /* The following code determines the architecture and register size. |
14843 | Similar code was added to GCC 3.3 (see override_options() in | |
14844 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
14845 | as much as possible. */ | |
e9670677 | 14846 | |
316f5878 | 14847 | if (mips_arch_string != 0) |
fef14a42 | 14848 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 14849 | |
316f5878 | 14850 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 14851 | { |
316f5878 | 14852 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 14853 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 14854 | the -march selection (if any). */ |
fef14a42 | 14855 | if (arch_info != 0) |
e9670677 | 14856 | { |
316f5878 RS |
14857 | /* -march takes precedence over -mipsN, since it is more descriptive. |
14858 | There's no harm in specifying both as long as the ISA levels | |
14859 | are the same. */ | |
fef14a42 | 14860 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
14861 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
14862 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 14863 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 14864 | } |
316f5878 | 14865 | else |
fef14a42 | 14866 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
14867 | } |
14868 | ||
fef14a42 TS |
14869 | if (arch_info == 0) |
14870 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 14871 | |
fef14a42 | 14872 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 14873 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
14874 | arch_info->name); |
14875 | ||
14876 | mips_set_architecture (arch_info); | |
14877 | ||
14878 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
14879 | if (mips_tune_string != 0) | |
14880 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 14881 | |
fef14a42 TS |
14882 | if (tune_info == 0) |
14883 | mips_set_tune (arch_info); | |
14884 | else | |
14885 | mips_set_tune (tune_info); | |
e9670677 | 14886 | |
316f5878 | 14887 | if (file_mips_gp32 >= 0) |
e9670677 | 14888 | { |
316f5878 RS |
14889 | /* The user specified the size of the integer registers. Make sure |
14890 | it agrees with the ABI and ISA. */ | |
14891 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
14892 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
14893 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14894 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
14895 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14896 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
14897 | } |
14898 | else | |
14899 | { | |
316f5878 RS |
14900 | /* Infer the integer register size from the ABI and processor. |
14901 | Restrict ourselves to 32-bit registers if that's all the | |
14902 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
14903 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
14904 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
14905 | } |
14906 | ||
ad3fea08 TS |
14907 | switch (file_mips_fp32) |
14908 | { | |
14909 | default: | |
14910 | case -1: | |
14911 | /* No user specified float register size. | |
14912 | ??? GAS treats single-float processors as though they had 64-bit | |
14913 | float registers (although it complains when double-precision | |
14914 | instructions are used). As things stand, saying they have 32-bit | |
14915 | registers would lead to spurious "register must be even" messages. | |
14916 | So here we assume float registers are never smaller than the | |
14917 | integer ones. */ | |
14918 | if (file_mips_gp32 == 0) | |
14919 | /* 64-bit integer registers implies 64-bit float registers. */ | |
14920 | file_mips_fp32 = 0; | |
14921 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
14922 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
14923 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
14924 | file_mips_fp32 = 0; | |
14925 | else | |
14926 | /* 32-bit float registers. */ | |
14927 | file_mips_fp32 = 1; | |
14928 | break; | |
14929 | ||
14930 | /* The user specified the size of the float registers. Check if it | |
14931 | agrees with the ABI and ISA. */ | |
14932 | case 0: | |
14933 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
14934 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
14935 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
14936 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
14937 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
14938 | break; | |
14939 | case 1: | |
14940 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14941 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
14942 | break; | |
14943 | } | |
e9670677 | 14944 | |
316f5878 | 14945 | /* End of GCC-shared inference code. */ |
e9670677 | 14946 | |
17a2f251 TS |
14947 | /* This flag is set when we have a 64-bit capable CPU but use only |
14948 | 32-bit wide registers. Note that EABI does not use it. */ | |
14949 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
14950 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
14951 | || mips_abi == O32_ABI)) | |
316f5878 | 14952 | mips_32bitmode = 1; |
e9670677 MR |
14953 | |
14954 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
14955 | as_bad (_("trap exception not supported at ISA 1")); | |
14956 | ||
e9670677 MR |
14957 | /* If the selected architecture includes support for ASEs, enable |
14958 | generation of code for them. */ | |
a4672219 | 14959 | if (mips_opts.mips16 == -1) |
fef14a42 | 14960 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
df58fc94 RS |
14961 | if (mips_opts.micromips == -1) |
14962 | mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0; | |
ffdefa66 | 14963 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 14964 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
14965 | && file_mips_fp32 == 0) ? 1 : 0; |
14966 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
14967 | as_bad (_("-mfp32 used with -mips3d")); | |
14968 | ||
ffdefa66 | 14969 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 14970 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
14971 | && file_mips_fp32 == 0) ? 1 : 0; |
14972 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
14973 | as_bad (_("-mfp32 used with -mdmx")); | |
14974 | ||
14975 | if (mips_opts.ase_smartmips == -1) | |
14976 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
14977 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
20203fb9 NC |
14978 | as_warn (_("%s ISA does not support SmartMIPS"), |
14979 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 14980 | |
74cd071d | 14981 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
14982 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
14983 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
20203fb9 NC |
14984 | as_warn (_("%s ISA does not support DSP ASE"), |
14985 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 14986 | |
8b082fb1 TS |
14987 | if (mips_opts.ase_dspr2 == -1) |
14988 | { | |
14989 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
14990 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
14991 | } | |
14992 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 NC |
14993 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
14994 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 14995 | |
ef2e4d86 | 14996 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
14997 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
14998 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
20203fb9 NC |
14999 | as_warn (_("%s ISA does not support MT ASE"), |
15000 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 15001 | |
e9670677 | 15002 | file_mips_isa = mips_opts.isa; |
e9670677 MR |
15003 | file_ase_mips3d = mips_opts.ase_mips3d; |
15004 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 15005 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 15006 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 15007 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 15008 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
15009 | mips_opts.gp32 = file_mips_gp32; |
15010 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
15011 | mips_opts.soft_float = file_mips_soft_float; |
15012 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 15013 | |
ecb4347a DJ |
15014 | if (mips_flag_mdebug < 0) |
15015 | { | |
15016 | #ifdef OBJ_MAYBE_ECOFF | |
15017 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
15018 | mips_flag_mdebug = 1; | |
15019 | else | |
15020 | #endif /* OBJ_MAYBE_ECOFF */ | |
15021 | mips_flag_mdebug = 0; | |
15022 | } | |
e9670677 MR |
15023 | } |
15024 | \f | |
15025 | void | |
17a2f251 | 15026 | mips_init_after_args (void) |
252b5132 RH |
15027 | { |
15028 | /* initialize opcodes */ | |
15029 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 15030 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15031 | } |
15032 | ||
15033 | long | |
17a2f251 | 15034 | md_pcrel_from (fixS *fixP) |
252b5132 | 15035 | { |
a7ebbfdf TS |
15036 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
15037 | switch (fixP->fx_r_type) | |
15038 | { | |
df58fc94 RS |
15039 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15040 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15041 | /* Return the address of the delay slot. */ | |
15042 | return addr + 2; | |
15043 | ||
15044 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15045 | case BFD_RELOC_MICROMIPS_JMP: | |
a7ebbfdf TS |
15046 | case BFD_RELOC_16_PCREL_S2: |
15047 | case BFD_RELOC_MIPS_JMP: | |
15048 | /* Return the address of the delay slot. */ | |
15049 | return addr + 4; | |
df58fc94 | 15050 | |
a7ebbfdf | 15051 | default: |
58ea3d6a | 15052 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
15053 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
15054 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15055 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
15056 | return addr; |
15057 | } | |
252b5132 RH |
15058 | } |
15059 | ||
252b5132 RH |
15060 | /* This is called before the symbol table is processed. In order to |
15061 | work with gcc when using mips-tfile, we must keep all local labels. | |
15062 | However, in other cases, we want to discard them. If we were | |
15063 | called with -g, but we didn't see any debugging information, it may | |
15064 | mean that gcc is smuggling debugging information through to | |
15065 | mips-tfile, in which case we must generate all local labels. */ | |
15066 | ||
15067 | void | |
17a2f251 | 15068 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15069 | { |
15070 | #ifndef NO_ECOFF_DEBUGGING | |
15071 | if (ECOFF_DEBUGGING | |
15072 | && mips_debug != 0 | |
15073 | && ! ecoff_debugging_seen) | |
15074 | flag_keep_locals = 1; | |
15075 | #endif | |
15076 | } | |
15077 | ||
3b91255e | 15078 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15079 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15080 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15081 | relocation operators. | |
15082 | ||
15083 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15084 | expression if: | |
15085 | ||
15086 | (a) it refers to the same symbol; and | |
15087 | (b) the offset applied in the %lo() expression is no lower than | |
15088 | the offset applied in the %got() or %hi(). | |
15089 | ||
15090 | (b) allows us to cope with code like: | |
15091 | ||
15092 | lui $4,%hi(foo) | |
15093 | lh $4,%lo(foo+2)($4) | |
15094 | ||
15095 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15096 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15097 | the high 16 bits. | |
15098 | ||
15099 | When several %lo()s match a particular %got() or %hi(), we use the | |
15100 | following rules to distinguish them: | |
15101 | ||
15102 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15103 | higher offsets. | |
15104 | ||
15105 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15106 | that already have a matching %got() or %hi(). | |
15107 | ||
15108 | (3) later %lo()s are better than earlier %lo()s. | |
15109 | ||
15110 | These rules are applied in order. | |
15111 | ||
15112 | (1) means, among other things, that %lo()s with identical offsets are | |
15113 | chosen if they exist. | |
15114 | ||
15115 | (2) means that we won't associate several high-part relocations with | |
15116 | the same low-part relocation unless there's no alternative. Having | |
15117 | several high parts for the same low part is a GNU extension; this rule | |
15118 | allows careful users to avoid it. | |
15119 | ||
15120 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15121 | with the last high-part relocation being at the front of the list. | |
15122 | It therefore makes sense to choose the last matching low-part | |
15123 | relocation, all other things being equal. It's also easier | |
15124 | to code that way. */ | |
252b5132 RH |
15125 | |
15126 | void | |
17a2f251 | 15127 | mips_frob_file (void) |
252b5132 RH |
15128 | { |
15129 | struct mips_hi_fixup *l; | |
35903be0 | 15130 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15131 | |
15132 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15133 | { | |
15134 | segment_info_type *seginfo; | |
3b91255e RS |
15135 | bfd_boolean matched_lo_p; |
15136 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15137 | |
9c2799c2 | 15138 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15139 | |
5919d012 RS |
15140 | /* If a GOT16 relocation turns out to be against a global symbol, |
15141 | there isn't supposed to be a matching LO. */ | |
738e5348 | 15142 | if (got16_reloc_p (l->fixp->fx_r_type) |
5919d012 RS |
15143 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) |
15144 | continue; | |
15145 | ||
15146 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15147 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15148 | continue; |
15149 | ||
252b5132 | 15150 | seginfo = seg_info (l->seg); |
252b5132 | 15151 | |
3b91255e RS |
15152 | /* Set HI_POS to the position of this relocation in the chain. |
15153 | Set LO_POS to the position of the chosen low-part relocation. | |
15154 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15155 | relocation that matches an immediately-preceding high-part | |
15156 | relocation. */ | |
15157 | hi_pos = NULL; | |
15158 | lo_pos = NULL; | |
15159 | matched_lo_p = FALSE; | |
738e5348 | 15160 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15161 | |
3b91255e RS |
15162 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15163 | { | |
15164 | if (*pos == l->fixp) | |
15165 | hi_pos = pos; | |
15166 | ||
35903be0 | 15167 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15168 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15169 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15170 | && (lo_pos == NULL | |
15171 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15172 | || (!matched_lo_p | |
15173 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15174 | lo_pos = pos; | |
15175 | ||
15176 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15177 | && fixup_has_matching_lo_p (*pos)); | |
15178 | } | |
15179 | ||
15180 | /* If we found a match, remove the high-part relocation from its | |
15181 | current position and insert it before the low-part relocation. | |
15182 | Make the offsets match so that fixup_has_matching_lo_p() | |
15183 | will return true. | |
15184 | ||
15185 | We don't warn about unmatched high-part relocations since some | |
15186 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15187 | instructions. */ | |
15188 | if (lo_pos != NULL) | |
15189 | { | |
15190 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15191 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15192 | { |
3b91255e RS |
15193 | *hi_pos = l->fixp->fx_next; |
15194 | l->fixp->fx_next = *lo_pos; | |
15195 | *lo_pos = l->fixp; | |
252b5132 | 15196 | } |
252b5132 RH |
15197 | } |
15198 | } | |
15199 | } | |
15200 | ||
3e722fb5 | 15201 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 15202 | We have to prevent gas from dropping them. */ |
252b5132 | 15203 | |
252b5132 | 15204 | int |
17a2f251 | 15205 | mips_force_relocation (fixS *fixp) |
252b5132 | 15206 | { |
ae6063d4 | 15207 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15208 | return 1; |
15209 | ||
df58fc94 RS |
15210 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15211 | so that the linker relaxation can update targets. */ | |
15212 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15213 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15214 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15215 | return 1; | |
15216 | ||
f6688943 TS |
15217 | if (HAVE_NEWABI |
15218 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
15219 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
738e5348 RS |
15220 | || hi16_reloc_p (fixp->fx_r_type) |
15221 | || lo16_reloc_p (fixp->fx_r_type))) | |
f6688943 TS |
15222 | return 1; |
15223 | ||
3e722fb5 | 15224 | return 0; |
252b5132 RH |
15225 | } |
15226 | ||
15227 | /* Apply a fixup to the object file. */ | |
15228 | ||
94f592af | 15229 | void |
55cf6793 | 15230 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15231 | { |
874e8986 | 15232 | bfd_byte *buf; |
98aa84af | 15233 | long insn; |
a7ebbfdf | 15234 | reloc_howto_type *howto; |
252b5132 | 15235 | |
a7ebbfdf TS |
15236 | /* We ignore generic BFD relocations we don't know about. */ |
15237 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15238 | if (! howto) | |
15239 | return; | |
65551fa4 | 15240 | |
df58fc94 RS |
15241 | gas_assert (fixP->fx_size == 2 |
15242 | || fixP->fx_size == 4 | |
90ecf173 MR |
15243 | || fixP->fx_r_type == BFD_RELOC_16 |
15244 | || fixP->fx_r_type == BFD_RELOC_64 | |
15245 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15246 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15247 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15248 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15249 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
15250 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 15251 | |
a7ebbfdf | 15252 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 15253 | |
df58fc94 RS |
15254 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15255 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15256 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15257 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
b1dca8ee RS |
15258 | |
15259 | /* Don't treat parts of a composite relocation as done. There are two | |
15260 | reasons for this: | |
15261 | ||
15262 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15263 | should nevertheless be emitted if the first part is. | |
15264 | ||
15265 | (2) In normal usage, composite relocations are never assembly-time | |
15266 | constants. The easiest way of dealing with the pathological | |
15267 | exceptions is to generate a relocation against STN_UNDEF and | |
15268 | leave everything up to the linker. */ | |
3994f87e | 15269 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15270 | fixP->fx_done = 1; |
15271 | ||
15272 | switch (fixP->fx_r_type) | |
15273 | { | |
3f98094e DJ |
15274 | case BFD_RELOC_MIPS_TLS_GD: |
15275 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15276 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15277 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15278 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15279 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15280 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
15281 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
15282 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15283 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15284 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15285 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15286 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15287 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15288 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15289 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
3f98094e DJ |
15290 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
15291 | /* fall through */ | |
15292 | ||
252b5132 | 15293 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
15294 | case BFD_RELOC_MIPS_SHIFT5: |
15295 | case BFD_RELOC_MIPS_SHIFT6: | |
15296 | case BFD_RELOC_MIPS_GOT_DISP: | |
15297 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15298 | case BFD_RELOC_MIPS_GOT_OFST: | |
15299 | case BFD_RELOC_MIPS_SUB: | |
15300 | case BFD_RELOC_MIPS_INSERT_A: | |
15301 | case BFD_RELOC_MIPS_INSERT_B: | |
15302 | case BFD_RELOC_MIPS_DELETE: | |
15303 | case BFD_RELOC_MIPS_HIGHEST: | |
15304 | case BFD_RELOC_MIPS_HIGHER: | |
15305 | case BFD_RELOC_MIPS_SCN_DISP: | |
15306 | case BFD_RELOC_MIPS_REL16: | |
15307 | case BFD_RELOC_MIPS_RELGOT: | |
15308 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15309 | case BFD_RELOC_HI16: |
15310 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 15311 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15312 | case BFD_RELOC_MIPS_LITERAL: |
15313 | case BFD_RELOC_MIPS_CALL16: | |
15314 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15315 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15316 | case BFD_RELOC_MIPS_GOT_HI16: |
15317 | case BFD_RELOC_MIPS_GOT_LO16: | |
15318 | case BFD_RELOC_MIPS_CALL_HI16: | |
15319 | case BFD_RELOC_MIPS_CALL_LO16: | |
15320 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
15321 | case BFD_RELOC_MIPS16_GOT16: |
15322 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15323 | case BFD_RELOC_MIPS16_HI16: |
15324 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 | 15325 | case BFD_RELOC_MIPS16_JMP: |
df58fc94 RS |
15326 | case BFD_RELOC_MICROMIPS_JMP: |
15327 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
15328 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15329 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15330 | case BFD_RELOC_MICROMIPS_SUB: | |
15331 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15332 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15333 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15334 | case BFD_RELOC_MICROMIPS_JALR: | |
15335 | case BFD_RELOC_MICROMIPS_HI16: | |
15336 | case BFD_RELOC_MICROMIPS_HI16_S: | |
15337 | case BFD_RELOC_MICROMIPS_GPREL16: | |
15338 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15339 | case BFD_RELOC_MICROMIPS_CALL16: | |
15340 | case BFD_RELOC_MICROMIPS_GOT16: | |
15341 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15342 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15343 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15344 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
54f4ddb3 | 15345 | /* Nothing needed to do. The value comes from the reloc entry. */ |
252b5132 RH |
15346 | break; |
15347 | ||
252b5132 RH |
15348 | case BFD_RELOC_64: |
15349 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15350 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15351 | if (fixP->fx_done) |
252b5132 RH |
15352 | { |
15353 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 15354 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
15355 | else |
15356 | { | |
a7ebbfdf | 15357 | valueT hiv; |
252b5132 | 15358 | |
a7ebbfdf | 15359 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15360 | hiv = 0xffffffff; |
15361 | else | |
15362 | hiv = 0; | |
b215186b | 15363 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 15364 | *valP, 4); |
b215186b | 15365 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 15366 | hiv, 4); |
252b5132 RH |
15367 | } |
15368 | } | |
15369 | break; | |
15370 | ||
056350c6 | 15371 | case BFD_RELOC_RVA: |
252b5132 | 15372 | case BFD_RELOC_32: |
252b5132 RH |
15373 | case BFD_RELOC_16: |
15374 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
15375 | value now. This can happen if we have a .word which is not |
15376 | resolved when it appears but is later defined. */ | |
252b5132 | 15377 | if (fixP->fx_done) |
54f4ddb3 | 15378 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); |
252b5132 RH |
15379 | break; |
15380 | ||
15381 | case BFD_RELOC_LO16: | |
d6f16593 | 15382 | case BFD_RELOC_MIPS16_LO16: |
df58fc94 | 15383 | case BFD_RELOC_MICROMIPS_LO16: |
3e722fb5 CD |
15384 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
15385 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
15386 | /* When handling an embedded PIC switch statement, we can wind |
15387 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
15388 | if (fixP->fx_done) | |
15389 | { | |
a7ebbfdf | 15390 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
15391 | as_bad_where (fixP->fx_file, fixP->fx_line, |
15392 | _("relocation overflow")); | |
df58fc94 RS |
15393 | /* 32-bit microMIPS instructions are divided into two halfwords. |
15394 | Relocations always refer to the second halfword, regardless | |
15395 | of endianness. */ | |
15396 | if (target_big_endian || fixP->fx_r_type == BFD_RELOC_MICROMIPS_LO16) | |
252b5132 | 15397 | buf += 2; |
2132e3a3 | 15398 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
15399 | } |
15400 | break; | |
15401 | ||
15402 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 15403 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 15404 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 15405 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 15406 | |
54f4ddb3 TS |
15407 | /* We need to save the bits in the instruction since fixup_segment() |
15408 | might be deleting the relocation entry (i.e., a branch within | |
15409 | the current segment). */ | |
a7ebbfdf | 15410 | if (! fixP->fx_done) |
bb2d6cd7 | 15411 | break; |
252b5132 | 15412 | |
54f4ddb3 | 15413 | /* Update old instruction data. */ |
252b5132 RH |
15414 | if (target_big_endian) |
15415 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
15416 | else | |
15417 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
15418 | ||
a7ebbfdf TS |
15419 | if (*valP + 0x20000 <= 0x3ffff) |
15420 | { | |
15421 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 15422 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
15423 | } |
15424 | else if (mips_pic == NO_PIC | |
15425 | && fixP->fx_done | |
15426 | && fixP->fx_frag->fr_address >= text_section->vma | |
15427 | && (fixP->fx_frag->fr_address | |
587aac4e | 15428 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15429 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15430 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15431 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15432 | { |
15433 | /* The branch offset is too large. If this is an | |
15434 | unconditional branch, and we are not generating PIC code, | |
15435 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15436 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15437 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15438 | else |
a7ebbfdf TS |
15439 | insn = 0x08000000; /* j */ |
15440 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15441 | fixP->fx_done = 0; | |
15442 | fixP->fx_addsy = section_symbol (text_section); | |
15443 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 15444 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
15445 | } |
15446 | else | |
15447 | { | |
15448 | /* If we got here, we have branch-relaxation disabled, | |
15449 | and there's nothing we can do to fix this instruction | |
15450 | without turning it into a longer sequence. */ | |
15451 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15452 | _("Branch out of range")); | |
252b5132 | 15453 | } |
252b5132 RH |
15454 | break; |
15455 | ||
df58fc94 RS |
15456 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15457 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15458 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15459 | /* We adjust the offset back to even. */ | |
15460 | if ((*valP & 0x1) != 0) | |
15461 | --(*valP); | |
15462 | ||
15463 | if (! fixP->fx_done) | |
15464 | break; | |
15465 | ||
15466 | /* Should never visit here, because we keep the relocation. */ | |
15467 | abort (); | |
15468 | break; | |
15469 | ||
252b5132 RH |
15470 | case BFD_RELOC_VTABLE_INHERIT: |
15471 | fixP->fx_done = 0; | |
15472 | if (fixP->fx_addsy | |
15473 | && !S_IS_DEFINED (fixP->fx_addsy) | |
15474 | && !S_IS_WEAK (fixP->fx_addsy)) | |
15475 | S_SET_WEAK (fixP->fx_addsy); | |
15476 | break; | |
15477 | ||
15478 | case BFD_RELOC_VTABLE_ENTRY: | |
15479 | fixP->fx_done = 0; | |
15480 | break; | |
15481 | ||
15482 | default: | |
15483 | internalError (); | |
15484 | } | |
a7ebbfdf TS |
15485 | |
15486 | /* Remember value for tc_gen_reloc. */ | |
15487 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
15488 | } |
15489 | ||
252b5132 | 15490 | static symbolS * |
17a2f251 | 15491 | get_symbol (void) |
252b5132 RH |
15492 | { |
15493 | int c; | |
15494 | char *name; | |
15495 | symbolS *p; | |
15496 | ||
15497 | name = input_line_pointer; | |
15498 | c = get_symbol_end (); | |
15499 | p = (symbolS *) symbol_find_or_make (name); | |
15500 | *input_line_pointer = c; | |
15501 | return p; | |
15502 | } | |
15503 | ||
742a56fe RS |
15504 | /* Align the current frag to a given power of two. If a particular |
15505 | fill byte should be used, FILL points to an integer that contains | |
15506 | that byte, otherwise FILL is null. | |
15507 | ||
15508 | The MIPS assembler also automatically adjusts any preceding | |
15509 | label. */ | |
252b5132 RH |
15510 | |
15511 | static void | |
742a56fe | 15512 | mips_align (int to, int *fill, symbolS *label) |
252b5132 | 15513 | { |
7d10b47d | 15514 | mips_emit_delays (); |
df58fc94 | 15515 | mips_record_compressed_mode (); |
742a56fe RS |
15516 | if (fill == NULL && subseg_text_p (now_seg)) |
15517 | frag_align_code (to, 0); | |
15518 | else | |
15519 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 RH |
15520 | record_alignment (now_seg, to); |
15521 | if (label != NULL) | |
15522 | { | |
9c2799c2 | 15523 | gas_assert (S_GET_SEGMENT (label) == now_seg); |
49309057 | 15524 | symbol_set_frag (label, frag_now); |
252b5132 RH |
15525 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
15526 | } | |
15527 | } | |
15528 | ||
15529 | /* Align to a given power of two. .align 0 turns off the automatic | |
15530 | alignment used by the data creating pseudo-ops. */ | |
15531 | ||
15532 | static void | |
17a2f251 | 15533 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 15534 | { |
742a56fe | 15535 | int temp, fill_value, *fill_ptr; |
49954fb4 | 15536 | long max_alignment = 28; |
252b5132 | 15537 | |
54f4ddb3 | 15538 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 15539 | to the aligned address. |
54f4ddb3 | 15540 | o It's not documented but auto alignment is reinstated by |
252b5132 | 15541 | a .align pseudo instruction. |
54f4ddb3 | 15542 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 15543 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 15544 | We don't. */ |
252b5132 RH |
15545 | |
15546 | temp = get_absolute_expression (); | |
15547 | if (temp > max_alignment) | |
15548 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
15549 | else if (temp < 0) | |
15550 | { | |
15551 | as_warn (_("Alignment negative: 0 assumed.")); | |
15552 | temp = 0; | |
15553 | } | |
15554 | if (*input_line_pointer == ',') | |
15555 | { | |
f9419b05 | 15556 | ++input_line_pointer; |
742a56fe RS |
15557 | fill_value = get_absolute_expression (); |
15558 | fill_ptr = &fill_value; | |
252b5132 RH |
15559 | } |
15560 | else | |
742a56fe | 15561 | fill_ptr = 0; |
252b5132 RH |
15562 | if (temp) |
15563 | { | |
a8dbcb85 TS |
15564 | segment_info_type *si = seg_info (now_seg); |
15565 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 15566 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 15567 | auto_align = 1; |
742a56fe | 15568 | mips_align (temp, fill_ptr, l != NULL ? l->label : NULL); |
252b5132 RH |
15569 | } |
15570 | else | |
15571 | { | |
15572 | auto_align = 0; | |
15573 | } | |
15574 | ||
15575 | demand_empty_rest_of_line (); | |
15576 | } | |
15577 | ||
252b5132 | 15578 | static void |
17a2f251 | 15579 | s_change_sec (int sec) |
252b5132 RH |
15580 | { |
15581 | segT seg; | |
15582 | ||
252b5132 RH |
15583 | #ifdef OBJ_ELF |
15584 | /* The ELF backend needs to know that we are changing sections, so | |
15585 | that .previous works correctly. We could do something like check | |
b6ff326e | 15586 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
15587 | as it would not be appropriate to use it in the section changing |
15588 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
15589 | This should be cleaner, somehow. */ | |
f43abd2b TS |
15590 | if (IS_ELF) |
15591 | obj_elf_section_change_hook (); | |
252b5132 RH |
15592 | #endif |
15593 | ||
7d10b47d | 15594 | mips_emit_delays (); |
6a32d874 | 15595 | |
252b5132 RH |
15596 | switch (sec) |
15597 | { | |
15598 | case 't': | |
15599 | s_text (0); | |
15600 | break; | |
15601 | case 'd': | |
15602 | s_data (0); | |
15603 | break; | |
15604 | case 'b': | |
15605 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
15606 | demand_empty_rest_of_line (); | |
15607 | break; | |
15608 | ||
15609 | case 'r': | |
4d0d148d TS |
15610 | seg = subseg_new (RDATA_SECTION_NAME, |
15611 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 15612 | if (IS_ELF) |
252b5132 | 15613 | { |
4d0d148d TS |
15614 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
15615 | | SEC_READONLY | SEC_RELOC | |
15616 | | SEC_DATA)); | |
c41e87e3 | 15617 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 15618 | record_alignment (seg, 4); |
252b5132 | 15619 | } |
4d0d148d | 15620 | demand_empty_rest_of_line (); |
252b5132 RH |
15621 | break; |
15622 | ||
15623 | case 's': | |
4d0d148d | 15624 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 15625 | if (IS_ELF) |
252b5132 | 15626 | { |
4d0d148d TS |
15627 | bfd_set_section_flags (stdoutput, seg, |
15628 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 15629 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 15630 | record_alignment (seg, 4); |
252b5132 | 15631 | } |
4d0d148d TS |
15632 | demand_empty_rest_of_line (); |
15633 | break; | |
998b3c36 MR |
15634 | |
15635 | case 'B': | |
15636 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
15637 | if (IS_ELF) | |
15638 | { | |
15639 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); | |
15640 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
15641 | record_alignment (seg, 4); | |
15642 | } | |
15643 | demand_empty_rest_of_line (); | |
15644 | break; | |
252b5132 RH |
15645 | } |
15646 | ||
15647 | auto_align = 1; | |
15648 | } | |
b34976b6 | 15649 | |
cca86cc8 | 15650 | void |
17a2f251 | 15651 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 15652 | { |
7ed4a06a | 15653 | #ifdef OBJ_ELF |
cca86cc8 SC |
15654 | char *section_name; |
15655 | char c; | |
684022ea | 15656 | char next_c = 0; |
cca86cc8 SC |
15657 | int section_type; |
15658 | int section_flag; | |
15659 | int section_entry_size; | |
15660 | int section_alignment; | |
b34976b6 | 15661 | |
f43abd2b | 15662 | if (!IS_ELF) |
7ed4a06a TS |
15663 | return; |
15664 | ||
cca86cc8 SC |
15665 | section_name = input_line_pointer; |
15666 | c = get_symbol_end (); | |
a816d1ed AO |
15667 | if (c) |
15668 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 15669 | |
4cf0dd0d TS |
15670 | /* Do we have .section Name<,"flags">? */ |
15671 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 15672 | { |
4cf0dd0d TS |
15673 | /* just after name is now '\0'. */ |
15674 | *input_line_pointer = c; | |
cca86cc8 SC |
15675 | input_line_pointer = section_name; |
15676 | obj_elf_section (ignore); | |
15677 | return; | |
15678 | } | |
15679 | input_line_pointer++; | |
15680 | ||
15681 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
15682 | if (c == ',') | |
15683 | section_type = get_absolute_expression (); | |
15684 | else | |
15685 | section_type = 0; | |
15686 | if (*input_line_pointer++ == ',') | |
15687 | section_flag = get_absolute_expression (); | |
15688 | else | |
15689 | section_flag = 0; | |
15690 | if (*input_line_pointer++ == ',') | |
15691 | section_entry_size = get_absolute_expression (); | |
15692 | else | |
15693 | section_entry_size = 0; | |
15694 | if (*input_line_pointer++ == ',') | |
15695 | section_alignment = get_absolute_expression (); | |
15696 | else | |
15697 | section_alignment = 0; | |
87975d2a AM |
15698 | /* FIXME: really ignore? */ |
15699 | (void) section_alignment; | |
cca86cc8 | 15700 | |
a816d1ed AO |
15701 | section_name = xstrdup (section_name); |
15702 | ||
8ab8a5c8 RS |
15703 | /* When using the generic form of .section (as implemented by obj-elf.c), |
15704 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
15705 | traditionally had to fall back on the more common @progbits instead. | |
15706 | ||
15707 | There's nothing really harmful in this, since bfd will correct | |
15708 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 15709 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
15710 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
15711 | ||
15712 | Even so, we shouldn't force users of the MIPS .section syntax to | |
15713 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
15714 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
15715 | generic type-checking code. */ | |
15716 | if (section_type == SHT_MIPS_DWARF) | |
15717 | section_type = SHT_PROGBITS; | |
15718 | ||
cca86cc8 SC |
15719 | obj_elf_change_section (section_name, section_type, section_flag, |
15720 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
15721 | |
15722 | if (now_seg->name != section_name) | |
15723 | free (section_name); | |
7ed4a06a | 15724 | #endif /* OBJ_ELF */ |
cca86cc8 | 15725 | } |
252b5132 RH |
15726 | |
15727 | void | |
17a2f251 | 15728 | mips_enable_auto_align (void) |
252b5132 RH |
15729 | { |
15730 | auto_align = 1; | |
15731 | } | |
15732 | ||
15733 | static void | |
17a2f251 | 15734 | s_cons (int log_size) |
252b5132 | 15735 | { |
a8dbcb85 TS |
15736 | segment_info_type *si = seg_info (now_seg); |
15737 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
15738 | symbolS *label; |
15739 | ||
a8dbcb85 | 15740 | label = l != NULL ? l->label : NULL; |
7d10b47d | 15741 | mips_emit_delays (); |
252b5132 RH |
15742 | if (log_size > 0 && auto_align) |
15743 | mips_align (log_size, 0, label); | |
252b5132 | 15744 | cons (1 << log_size); |
a1facbec | 15745 | mips_clear_insn_labels (); |
252b5132 RH |
15746 | } |
15747 | ||
15748 | static void | |
17a2f251 | 15749 | s_float_cons (int type) |
252b5132 | 15750 | { |
a8dbcb85 TS |
15751 | segment_info_type *si = seg_info (now_seg); |
15752 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
15753 | symbolS *label; |
15754 | ||
a8dbcb85 | 15755 | label = l != NULL ? l->label : NULL; |
252b5132 | 15756 | |
7d10b47d | 15757 | mips_emit_delays (); |
252b5132 RH |
15758 | |
15759 | if (auto_align) | |
49309057 ILT |
15760 | { |
15761 | if (type == 'd') | |
15762 | mips_align (3, 0, label); | |
15763 | else | |
15764 | mips_align (2, 0, label); | |
15765 | } | |
252b5132 | 15766 | |
252b5132 | 15767 | float_cons (type); |
a1facbec | 15768 | mips_clear_insn_labels (); |
252b5132 RH |
15769 | } |
15770 | ||
15771 | /* Handle .globl. We need to override it because on Irix 5 you are | |
15772 | permitted to say | |
15773 | .globl foo .text | |
15774 | where foo is an undefined symbol, to mean that foo should be | |
15775 | considered to be the address of a function. */ | |
15776 | ||
15777 | static void | |
17a2f251 | 15778 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15779 | { |
15780 | char *name; | |
15781 | int c; | |
15782 | symbolS *symbolP; | |
15783 | flagword flag; | |
15784 | ||
8a06b769 | 15785 | do |
252b5132 | 15786 | { |
8a06b769 | 15787 | name = input_line_pointer; |
252b5132 | 15788 | c = get_symbol_end (); |
8a06b769 TS |
15789 | symbolP = symbol_find_or_make (name); |
15790 | S_SET_EXTERNAL (symbolP); | |
15791 | ||
252b5132 | 15792 | *input_line_pointer = c; |
8a06b769 | 15793 | SKIP_WHITESPACE (); |
252b5132 | 15794 | |
8a06b769 TS |
15795 | /* On Irix 5, every global symbol that is not explicitly labelled as |
15796 | being a function is apparently labelled as being an object. */ | |
15797 | flag = BSF_OBJECT; | |
252b5132 | 15798 | |
8a06b769 TS |
15799 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
15800 | && (*input_line_pointer != ',')) | |
15801 | { | |
15802 | char *secname; | |
15803 | asection *sec; | |
15804 | ||
15805 | secname = input_line_pointer; | |
15806 | c = get_symbol_end (); | |
15807 | sec = bfd_get_section_by_name (stdoutput, secname); | |
15808 | if (sec == NULL) | |
15809 | as_bad (_("%s: no such section"), secname); | |
15810 | *input_line_pointer = c; | |
15811 | ||
15812 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
15813 | flag = BSF_FUNCTION; | |
15814 | } | |
15815 | ||
15816 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
15817 | ||
15818 | c = *input_line_pointer; | |
15819 | if (c == ',') | |
15820 | { | |
15821 | input_line_pointer++; | |
15822 | SKIP_WHITESPACE (); | |
15823 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
15824 | c = '\n'; | |
15825 | } | |
15826 | } | |
15827 | while (c == ','); | |
252b5132 | 15828 | |
252b5132 RH |
15829 | demand_empty_rest_of_line (); |
15830 | } | |
15831 | ||
15832 | static void | |
17a2f251 | 15833 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15834 | { |
15835 | char *opt; | |
15836 | char c; | |
15837 | ||
15838 | opt = input_line_pointer; | |
15839 | c = get_symbol_end (); | |
15840 | ||
15841 | if (*opt == 'O') | |
15842 | { | |
15843 | /* FIXME: What does this mean? */ | |
15844 | } | |
15845 | else if (strncmp (opt, "pic", 3) == 0) | |
15846 | { | |
15847 | int i; | |
15848 | ||
15849 | i = atoi (opt + 3); | |
15850 | if (i == 0) | |
15851 | mips_pic = NO_PIC; | |
15852 | else if (i == 2) | |
143d77c5 | 15853 | { |
252b5132 | 15854 | mips_pic = SVR4_PIC; |
143d77c5 EC |
15855 | mips_abicalls = TRUE; |
15856 | } | |
252b5132 RH |
15857 | else |
15858 | as_bad (_(".option pic%d not supported"), i); | |
15859 | ||
4d0d148d | 15860 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
15861 | { |
15862 | if (g_switch_seen && g_switch_value != 0) | |
15863 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
15864 | g_switch_value = 0; | |
15865 | bfd_set_gp_size (stdoutput, 0); | |
15866 | } | |
15867 | } | |
15868 | else | |
15869 | as_warn (_("Unrecognized option \"%s\""), opt); | |
15870 | ||
15871 | *input_line_pointer = c; | |
15872 | demand_empty_rest_of_line (); | |
15873 | } | |
15874 | ||
15875 | /* This structure is used to hold a stack of .set values. */ | |
15876 | ||
e972090a NC |
15877 | struct mips_option_stack |
15878 | { | |
252b5132 RH |
15879 | struct mips_option_stack *next; |
15880 | struct mips_set_options options; | |
15881 | }; | |
15882 | ||
15883 | static struct mips_option_stack *mips_opts_stack; | |
15884 | ||
15885 | /* Handle the .set pseudo-op. */ | |
15886 | ||
15887 | static void | |
17a2f251 | 15888 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15889 | { |
15890 | char *name = input_line_pointer, ch; | |
15891 | ||
15892 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 15893 | ++input_line_pointer; |
252b5132 RH |
15894 | ch = *input_line_pointer; |
15895 | *input_line_pointer = '\0'; | |
15896 | ||
15897 | if (strcmp (name, "reorder") == 0) | |
15898 | { | |
7d10b47d RS |
15899 | if (mips_opts.noreorder) |
15900 | end_noreorder (); | |
252b5132 RH |
15901 | } |
15902 | else if (strcmp (name, "noreorder") == 0) | |
15903 | { | |
7d10b47d RS |
15904 | if (!mips_opts.noreorder) |
15905 | start_noreorder (); | |
252b5132 | 15906 | } |
741fe287 MR |
15907 | else if (strncmp (name, "at=", 3) == 0) |
15908 | { | |
15909 | char *s = name + 3; | |
15910 | ||
15911 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
15912 | as_bad (_("Unrecognized register name `%s'"), s); | |
15913 | } | |
252b5132 RH |
15914 | else if (strcmp (name, "at") == 0) |
15915 | { | |
741fe287 | 15916 | mips_opts.at = ATREG; |
252b5132 RH |
15917 | } |
15918 | else if (strcmp (name, "noat") == 0) | |
15919 | { | |
741fe287 | 15920 | mips_opts.at = ZERO; |
252b5132 RH |
15921 | } |
15922 | else if (strcmp (name, "macro") == 0) | |
15923 | { | |
15924 | mips_opts.warn_about_macros = 0; | |
15925 | } | |
15926 | else if (strcmp (name, "nomacro") == 0) | |
15927 | { | |
15928 | if (mips_opts.noreorder == 0) | |
15929 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
15930 | mips_opts.warn_about_macros = 1; | |
15931 | } | |
15932 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
15933 | { | |
15934 | mips_opts.nomove = 0; | |
15935 | } | |
15936 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
15937 | { | |
15938 | mips_opts.nomove = 1; | |
15939 | } | |
15940 | else if (strcmp (name, "bopt") == 0) | |
15941 | { | |
15942 | mips_opts.nobopt = 0; | |
15943 | } | |
15944 | else if (strcmp (name, "nobopt") == 0) | |
15945 | { | |
15946 | mips_opts.nobopt = 1; | |
15947 | } | |
ad3fea08 TS |
15948 | else if (strcmp (name, "gp=default") == 0) |
15949 | mips_opts.gp32 = file_mips_gp32; | |
15950 | else if (strcmp (name, "gp=32") == 0) | |
15951 | mips_opts.gp32 = 1; | |
15952 | else if (strcmp (name, "gp=64") == 0) | |
15953 | { | |
15954 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 15955 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
15956 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
15957 | mips_opts.gp32 = 0; | |
15958 | } | |
15959 | else if (strcmp (name, "fp=default") == 0) | |
15960 | mips_opts.fp32 = file_mips_fp32; | |
15961 | else if (strcmp (name, "fp=32") == 0) | |
15962 | mips_opts.fp32 = 1; | |
15963 | else if (strcmp (name, "fp=64") == 0) | |
15964 | { | |
15965 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 15966 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
15967 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
15968 | mips_opts.fp32 = 0; | |
15969 | } | |
037b32b9 AN |
15970 | else if (strcmp (name, "softfloat") == 0) |
15971 | mips_opts.soft_float = 1; | |
15972 | else if (strcmp (name, "hardfloat") == 0) | |
15973 | mips_opts.soft_float = 0; | |
15974 | else if (strcmp (name, "singlefloat") == 0) | |
15975 | mips_opts.single_float = 1; | |
15976 | else if (strcmp (name, "doublefloat") == 0) | |
15977 | mips_opts.single_float = 0; | |
252b5132 RH |
15978 | else if (strcmp (name, "mips16") == 0 |
15979 | || strcmp (name, "MIPS-16") == 0) | |
df58fc94 RS |
15980 | { |
15981 | if (mips_opts.micromips == 1) | |
15982 | as_fatal (_("`mips16' cannot be used with `micromips'")); | |
15983 | mips_opts.mips16 = 1; | |
15984 | } | |
252b5132 RH |
15985 | else if (strcmp (name, "nomips16") == 0 |
15986 | || strcmp (name, "noMIPS-16") == 0) | |
15987 | mips_opts.mips16 = 0; | |
df58fc94 RS |
15988 | else if (strcmp (name, "micromips") == 0) |
15989 | { | |
15990 | if (mips_opts.mips16 == 1) | |
15991 | as_fatal (_("`micromips' cannot be used with `mips16'")); | |
15992 | mips_opts.micromips = 1; | |
15993 | } | |
15994 | else if (strcmp (name, "nomicromips") == 0) | |
15995 | mips_opts.micromips = 0; | |
e16bfa71 TS |
15996 | else if (strcmp (name, "smartmips") == 0) |
15997 | { | |
ad3fea08 | 15998 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 15999 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 TS |
16000 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16001 | mips_opts.ase_smartmips = 1; | |
16002 | } | |
16003 | else if (strcmp (name, "nosmartmips") == 0) | |
16004 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
16005 | else if (strcmp (name, "mips3d") == 0) |
16006 | mips_opts.ase_mips3d = 1; | |
16007 | else if (strcmp (name, "nomips3d") == 0) | |
16008 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
16009 | else if (strcmp (name, "mdmx") == 0) |
16010 | mips_opts.ase_mdmx = 1; | |
16011 | else if (strcmp (name, "nomdmx") == 0) | |
16012 | mips_opts.ase_mdmx = 0; | |
74cd071d | 16013 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
16014 | { |
16015 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 16016 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 TS |
16017 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16018 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 16019 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 16020 | } |
74cd071d | 16021 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
16022 | { |
16023 | mips_opts.ase_dsp = 0; | |
16024 | mips_opts.ase_dspr2 = 0; | |
16025 | } | |
16026 | else if (strcmp (name, "dspr2") == 0) | |
16027 | { | |
16028 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 16029 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 TS |
16030 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16031 | mips_opts.ase_dspr2 = 1; | |
16032 | mips_opts.ase_dsp = 1; | |
16033 | } | |
16034 | else if (strcmp (name, "nodspr2") == 0) | |
16035 | { | |
16036 | mips_opts.ase_dspr2 = 0; | |
16037 | mips_opts.ase_dsp = 0; | |
16038 | } | |
ef2e4d86 | 16039 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
16040 | { |
16041 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 16042 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 TS |
16043 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16044 | mips_opts.ase_mt = 1; | |
16045 | } | |
ef2e4d86 CF |
16046 | else if (strcmp (name, "nomt") == 0) |
16047 | mips_opts.ase_mt = 0; | |
1a2c1fad | 16048 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16049 | { |
af7ee8bf | 16050 | int reset = 0; |
252b5132 | 16051 | |
1a2c1fad CD |
16052 | /* Permit the user to change the ISA and architecture on the fly. |
16053 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 16054 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
16055 | { |
16056 | reset = 1; | |
16057 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 16058 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
16059 | } |
16060 | else if (strncmp (name, "arch=", 5) == 0) | |
16061 | { | |
16062 | const struct mips_cpu_info *p; | |
16063 | ||
16064 | p = mips_parse_cpu("internal use", name + 5); | |
16065 | if (!p) | |
16066 | as_bad (_("unknown architecture %s"), name + 5); | |
16067 | else | |
16068 | { | |
16069 | mips_opts.arch = p->cpu; | |
16070 | mips_opts.isa = p->isa; | |
16071 | } | |
16072 | } | |
81a21e38 TS |
16073 | else if (strncmp (name, "mips", 4) == 0) |
16074 | { | |
16075 | const struct mips_cpu_info *p; | |
16076 | ||
16077 | p = mips_parse_cpu("internal use", name); | |
16078 | if (!p) | |
16079 | as_bad (_("unknown ISA level %s"), name + 4); | |
16080 | else | |
16081 | { | |
16082 | mips_opts.arch = p->cpu; | |
16083 | mips_opts.isa = p->isa; | |
16084 | } | |
16085 | } | |
af7ee8bf | 16086 | else |
81a21e38 | 16087 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
16088 | |
16089 | switch (mips_opts.isa) | |
98d3f06f KH |
16090 | { |
16091 | case 0: | |
98d3f06f | 16092 | break; |
af7ee8bf CD |
16093 | case ISA_MIPS1: |
16094 | case ISA_MIPS2: | |
16095 | case ISA_MIPS32: | |
16096 | case ISA_MIPS32R2: | |
98d3f06f KH |
16097 | mips_opts.gp32 = 1; |
16098 | mips_opts.fp32 = 1; | |
16099 | break; | |
af7ee8bf CD |
16100 | case ISA_MIPS3: |
16101 | case ISA_MIPS4: | |
16102 | case ISA_MIPS5: | |
16103 | case ISA_MIPS64: | |
5f74bc13 | 16104 | case ISA_MIPS64R2: |
98d3f06f KH |
16105 | mips_opts.gp32 = 0; |
16106 | mips_opts.fp32 = 0; | |
16107 | break; | |
16108 | default: | |
16109 | as_bad (_("unknown ISA level %s"), name + 4); | |
16110 | break; | |
16111 | } | |
af7ee8bf | 16112 | if (reset) |
98d3f06f | 16113 | { |
af7ee8bf CD |
16114 | mips_opts.gp32 = file_mips_gp32; |
16115 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 16116 | } |
252b5132 RH |
16117 | } |
16118 | else if (strcmp (name, "autoextend") == 0) | |
16119 | mips_opts.noautoextend = 0; | |
16120 | else if (strcmp (name, "noautoextend") == 0) | |
16121 | mips_opts.noautoextend = 1; | |
16122 | else if (strcmp (name, "push") == 0) | |
16123 | { | |
16124 | struct mips_option_stack *s; | |
16125 | ||
16126 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
16127 | s->next = mips_opts_stack; | |
16128 | s->options = mips_opts; | |
16129 | mips_opts_stack = s; | |
16130 | } | |
16131 | else if (strcmp (name, "pop") == 0) | |
16132 | { | |
16133 | struct mips_option_stack *s; | |
16134 | ||
16135 | s = mips_opts_stack; | |
16136 | if (s == NULL) | |
16137 | as_bad (_(".set pop with no .set push")); | |
16138 | else | |
16139 | { | |
16140 | /* If we're changing the reorder mode we need to handle | |
16141 | delay slots correctly. */ | |
16142 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16143 | start_noreorder (); |
252b5132 | 16144 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16145 | end_noreorder (); |
252b5132 RH |
16146 | |
16147 | mips_opts = s->options; | |
16148 | mips_opts_stack = s->next; | |
16149 | free (s); | |
16150 | } | |
16151 | } | |
aed1a261 RS |
16152 | else if (strcmp (name, "sym32") == 0) |
16153 | mips_opts.sym32 = TRUE; | |
16154 | else if (strcmp (name, "nosym32") == 0) | |
16155 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
16156 | else if (strchr (name, ',')) |
16157 | { | |
16158 | /* Generic ".set" directive; use the generic handler. */ | |
16159 | *input_line_pointer = ch; | |
16160 | input_line_pointer = name; | |
16161 | s_set (0); | |
16162 | return; | |
16163 | } | |
252b5132 RH |
16164 | else |
16165 | { | |
16166 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
16167 | } | |
16168 | *input_line_pointer = ch; | |
16169 | demand_empty_rest_of_line (); | |
16170 | } | |
16171 | ||
16172 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16173 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16174 | ||
16175 | static void | |
17a2f251 | 16176 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16177 | { |
16178 | mips_pic = SVR4_PIC; | |
143d77c5 | 16179 | mips_abicalls = TRUE; |
4d0d148d TS |
16180 | |
16181 | if (g_switch_seen && g_switch_value != 0) | |
16182 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16183 | g_switch_value = 0; | |
16184 | ||
252b5132 RH |
16185 | bfd_set_gp_size (stdoutput, 0); |
16186 | demand_empty_rest_of_line (); | |
16187 | } | |
16188 | ||
16189 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16190 | PIC code. It sets the $gp register for the function based on the | |
16191 | function address, which is in the register named in the argument. | |
16192 | This uses a relocation against _gp_disp, which is handled specially | |
16193 | by the linker. The result is: | |
16194 | lui $gp,%hi(_gp_disp) | |
16195 | addiu $gp,$gp,%lo(_gp_disp) | |
16196 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16197 | The .cpload argument is normally $25 == $t9. |
16198 | ||
16199 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16200 | lui $gp,%hi(__gnu_local_gp) |
16201 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16202 | and the argument is ignored. This saves an instruction, but the |
16203 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16204 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16205 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16206 | |
16207 | static void | |
17a2f251 | 16208 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16209 | { |
16210 | expressionS ex; | |
aa6975fb ILT |
16211 | int reg; |
16212 | int in_shared; | |
252b5132 | 16213 | |
6478892d TS |
16214 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16215 | .cpload is ignored. */ | |
16216 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16217 | { |
16218 | s_ignore (0); | |
16219 | return; | |
16220 | } | |
16221 | ||
d3ecfc59 | 16222 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16223 | if (mips_opts.noreorder == 0) |
16224 | as_warn (_(".cpload not in noreorder section")); | |
16225 | ||
aa6975fb ILT |
16226 | reg = tc_get_register (0); |
16227 | ||
16228 | /* If we need to produce a 64-bit address, we are better off using | |
16229 | the default instruction sequence. */ | |
aed1a261 | 16230 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16231 | |
252b5132 | 16232 | ex.X_op = O_symbol; |
bbe506e8 TS |
16233 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16234 | "__gnu_local_gp"); | |
252b5132 RH |
16235 | ex.X_op_symbol = NULL; |
16236 | ex.X_add_number = 0; | |
16237 | ||
16238 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16239 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16240 | |
584892a6 | 16241 | macro_start (); |
67c0d1eb RS |
16242 | macro_build_lui (&ex, mips_gp_register); |
16243 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16244 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16245 | if (in_shared) |
16246 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16247 | mips_gp_register, reg); | |
584892a6 | 16248 | macro_end (); |
252b5132 RH |
16249 | |
16250 | demand_empty_rest_of_line (); | |
16251 | } | |
16252 | ||
6478892d TS |
16253 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16254 | .cpsetup $reg1, offset|$reg2, label | |
16255 | ||
16256 | If offset is given, this results in: | |
16257 | sd $gp, offset($sp) | |
956cd1d6 | 16258 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16259 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16260 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16261 | |
16262 | If $reg2 is given, this results in: | |
16263 | daddu $reg2, $gp, $0 | |
956cd1d6 | 16264 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16265 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16266 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16267 | $reg1 is normally $25 == $t9. |
16268 | ||
16269 | The -mno-shared option replaces the last three instructions with | |
16270 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16271 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16272 | |
6478892d | 16273 | static void |
17a2f251 | 16274 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16275 | { |
16276 | expressionS ex_off; | |
16277 | expressionS ex_sym; | |
16278 | int reg1; | |
6478892d | 16279 | |
8586fc66 | 16280 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16281 | We also need NewABI support. */ |
16282 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16283 | { | |
16284 | s_ignore (0); | |
16285 | return; | |
16286 | } | |
16287 | ||
16288 | reg1 = tc_get_register (0); | |
16289 | SKIP_WHITESPACE (); | |
16290 | if (*input_line_pointer != ',') | |
16291 | { | |
16292 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16293 | return; | |
16294 | } | |
16295 | else | |
80245285 | 16296 | ++input_line_pointer; |
6478892d TS |
16297 | SKIP_WHITESPACE (); |
16298 | if (*input_line_pointer == '$') | |
80245285 TS |
16299 | { |
16300 | mips_cpreturn_register = tc_get_register (0); | |
16301 | mips_cpreturn_offset = -1; | |
16302 | } | |
6478892d | 16303 | else |
80245285 TS |
16304 | { |
16305 | mips_cpreturn_offset = get_absolute_expression (); | |
16306 | mips_cpreturn_register = -1; | |
16307 | } | |
6478892d TS |
16308 | SKIP_WHITESPACE (); |
16309 | if (*input_line_pointer != ',') | |
16310 | { | |
16311 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16312 | return; | |
16313 | } | |
16314 | else | |
f9419b05 | 16315 | ++input_line_pointer; |
6478892d | 16316 | SKIP_WHITESPACE (); |
f21f8242 | 16317 | expression (&ex_sym); |
6478892d | 16318 | |
584892a6 | 16319 | macro_start (); |
6478892d TS |
16320 | if (mips_cpreturn_register == -1) |
16321 | { | |
16322 | ex_off.X_op = O_constant; | |
16323 | ex_off.X_add_symbol = NULL; | |
16324 | ex_off.X_op_symbol = NULL; | |
16325 | ex_off.X_add_number = mips_cpreturn_offset; | |
16326 | ||
67c0d1eb | 16327 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16328 | BFD_RELOC_LO16, SP); |
6478892d TS |
16329 | } |
16330 | else | |
67c0d1eb | 16331 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 16332 | mips_gp_register, 0); |
6478892d | 16333 | |
aed1a261 | 16334 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16335 | { |
df58fc94 | 16336 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16337 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16338 | BFD_RELOC_HI16_S); | |
16339 | ||
16340 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16341 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16342 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16343 | ||
16344 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16345 | mips_gp_register, reg1); | |
16346 | } | |
16347 | else | |
16348 | { | |
16349 | expressionS ex; | |
16350 | ||
16351 | ex.X_op = O_symbol; | |
4184909a | 16352 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16353 | ex.X_op_symbol = NULL; |
16354 | ex.X_add_number = 0; | |
6e1304d8 | 16355 | |
aa6975fb ILT |
16356 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16357 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16358 | ||
16359 | macro_build_lui (&ex, mips_gp_register); | |
16360 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16361 | mips_gp_register, BFD_RELOC_LO16); | |
16362 | } | |
f21f8242 | 16363 | |
584892a6 | 16364 | macro_end (); |
6478892d TS |
16365 | |
16366 | demand_empty_rest_of_line (); | |
16367 | } | |
16368 | ||
16369 | static void | |
17a2f251 | 16370 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16371 | { |
16372 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 16373 | .cplocal is ignored. */ |
6478892d TS |
16374 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16375 | { | |
16376 | s_ignore (0); | |
16377 | return; | |
16378 | } | |
16379 | ||
16380 | mips_gp_register = tc_get_register (0); | |
85b51719 | 16381 | demand_empty_rest_of_line (); |
6478892d TS |
16382 | } |
16383 | ||
252b5132 RH |
16384 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16385 | offset from $sp. The offset is remembered, and after making a PIC | |
16386 | call $gp is restored from that location. */ | |
16387 | ||
16388 | static void | |
17a2f251 | 16389 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16390 | { |
16391 | expressionS ex; | |
252b5132 | 16392 | |
6478892d | 16393 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16394 | .cprestore is ignored. */ |
6478892d | 16395 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16396 | { |
16397 | s_ignore (0); | |
16398 | return; | |
16399 | } | |
16400 | ||
16401 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 16402 | mips_cprestore_valid = 1; |
252b5132 RH |
16403 | |
16404 | ex.X_op = O_constant; | |
16405 | ex.X_add_symbol = NULL; | |
16406 | ex.X_op_symbol = NULL; | |
16407 | ex.X_add_number = mips_cprestore_offset; | |
16408 | ||
584892a6 | 16409 | macro_start (); |
67c0d1eb RS |
16410 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16411 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16412 | macro_end (); |
252b5132 RH |
16413 | |
16414 | demand_empty_rest_of_line (); | |
16415 | } | |
16416 | ||
6478892d | 16417 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16418 | was given in the preceding .cpsetup, it results in: |
6478892d | 16419 | ld $gp, offset($sp) |
76b3015f | 16420 | |
6478892d | 16421 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
16422 | daddu $gp, $reg2, $0 */ |
16423 | ||
6478892d | 16424 | static void |
17a2f251 | 16425 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16426 | { |
16427 | expressionS ex; | |
6478892d TS |
16428 | |
16429 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
16430 | We also need NewABI support. */ | |
16431 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16432 | { | |
16433 | s_ignore (0); | |
16434 | return; | |
16435 | } | |
16436 | ||
584892a6 | 16437 | macro_start (); |
6478892d TS |
16438 | if (mips_cpreturn_register == -1) |
16439 | { | |
16440 | ex.X_op = O_constant; | |
16441 | ex.X_add_symbol = NULL; | |
16442 | ex.X_op_symbol = NULL; | |
16443 | ex.X_add_number = mips_cpreturn_offset; | |
16444 | ||
67c0d1eb | 16445 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16446 | } |
16447 | else | |
67c0d1eb | 16448 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 16449 | mips_cpreturn_register, 0); |
584892a6 | 16450 | macro_end (); |
6478892d TS |
16451 | |
16452 | demand_empty_rest_of_line (); | |
16453 | } | |
16454 | ||
741d6ea8 JM |
16455 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate |
16456 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
16457 | use in DWARF debug information. */ | |
16458 | ||
16459 | static void | |
16460 | s_dtprel_internal (size_t bytes) | |
16461 | { | |
16462 | expressionS ex; | |
16463 | char *p; | |
16464 | ||
16465 | expression (&ex); | |
16466 | ||
16467 | if (ex.X_op != O_symbol) | |
16468 | { | |
16469 | as_bad (_("Unsupported use of %s"), (bytes == 8 | |
16470 | ? ".dtpreldword" | |
16471 | : ".dtprelword")); | |
16472 | ignore_rest_of_line (); | |
16473 | } | |
16474 | ||
16475 | p = frag_more (bytes); | |
16476 | md_number_to_chars (p, 0, bytes); | |
16477 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, | |
16478 | (bytes == 8 | |
16479 | ? BFD_RELOC_MIPS_TLS_DTPREL64 | |
16480 | : BFD_RELOC_MIPS_TLS_DTPREL32)); | |
16481 | ||
16482 | demand_empty_rest_of_line (); | |
16483 | } | |
16484 | ||
16485 | /* Handle .dtprelword. */ | |
16486 | ||
16487 | static void | |
16488 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
16489 | { | |
16490 | s_dtprel_internal (4); | |
16491 | } | |
16492 | ||
16493 | /* Handle .dtpreldword. */ | |
16494 | ||
16495 | static void | |
16496 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
16497 | { | |
16498 | s_dtprel_internal (8); | |
16499 | } | |
16500 | ||
6478892d TS |
16501 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
16502 | code. It sets the offset to use in gp_rel relocations. */ | |
16503 | ||
16504 | static void | |
17a2f251 | 16505 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16506 | { |
16507 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
16508 | We also need NewABI support. */ | |
16509 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16510 | { | |
16511 | s_ignore (0); | |
16512 | return; | |
16513 | } | |
16514 | ||
def2e0dd | 16515 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
16516 | |
16517 | demand_empty_rest_of_line (); | |
16518 | } | |
16519 | ||
252b5132 RH |
16520 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
16521 | code. It generates a 32 bit GP relative reloc. */ | |
16522 | ||
16523 | static void | |
17a2f251 | 16524 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16525 | { |
a8dbcb85 TS |
16526 | segment_info_type *si; |
16527 | struct insn_label_list *l; | |
252b5132 RH |
16528 | symbolS *label; |
16529 | expressionS ex; | |
16530 | char *p; | |
16531 | ||
16532 | /* When not generating PIC code, this is treated as .word. */ | |
16533 | if (mips_pic != SVR4_PIC) | |
16534 | { | |
16535 | s_cons (2); | |
16536 | return; | |
16537 | } | |
16538 | ||
a8dbcb85 TS |
16539 | si = seg_info (now_seg); |
16540 | l = si->label_list; | |
16541 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 16542 | mips_emit_delays (); |
252b5132 RH |
16543 | if (auto_align) |
16544 | mips_align (2, 0, label); | |
252b5132 RH |
16545 | |
16546 | expression (&ex); | |
a1facbec | 16547 | mips_clear_insn_labels (); |
252b5132 RH |
16548 | |
16549 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16550 | { | |
16551 | as_bad (_("Unsupported use of .gpword")); | |
16552 | ignore_rest_of_line (); | |
16553 | } | |
16554 | ||
16555 | p = frag_more (4); | |
17a2f251 | 16556 | md_number_to_chars (p, 0, 4); |
b34976b6 | 16557 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 16558 | BFD_RELOC_GPREL32); |
252b5132 RH |
16559 | |
16560 | demand_empty_rest_of_line (); | |
16561 | } | |
16562 | ||
10181a0d | 16563 | static void |
17a2f251 | 16564 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 16565 | { |
a8dbcb85 TS |
16566 | segment_info_type *si; |
16567 | struct insn_label_list *l; | |
10181a0d AO |
16568 | symbolS *label; |
16569 | expressionS ex; | |
16570 | char *p; | |
16571 | ||
16572 | /* When not generating PIC code, this is treated as .dword. */ | |
16573 | if (mips_pic != SVR4_PIC) | |
16574 | { | |
16575 | s_cons (3); | |
16576 | return; | |
16577 | } | |
16578 | ||
a8dbcb85 TS |
16579 | si = seg_info (now_seg); |
16580 | l = si->label_list; | |
16581 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 16582 | mips_emit_delays (); |
10181a0d AO |
16583 | if (auto_align) |
16584 | mips_align (3, 0, label); | |
10181a0d AO |
16585 | |
16586 | expression (&ex); | |
a1facbec | 16587 | mips_clear_insn_labels (); |
10181a0d AO |
16588 | |
16589 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16590 | { | |
16591 | as_bad (_("Unsupported use of .gpdword")); | |
16592 | ignore_rest_of_line (); | |
16593 | } | |
16594 | ||
16595 | p = frag_more (8); | |
17a2f251 | 16596 | md_number_to_chars (p, 0, 8); |
a105a300 | 16597 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 16598 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
16599 | |
16600 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
16601 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
16602 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
16603 | |
16604 | demand_empty_rest_of_line (); | |
16605 | } | |
16606 | ||
252b5132 RH |
16607 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
16608 | tables in SVR4 PIC code. */ | |
16609 | ||
16610 | static void | |
17a2f251 | 16611 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16612 | { |
252b5132 RH |
16613 | int reg; |
16614 | ||
10181a0d AO |
16615 | /* This is ignored when not generating SVR4 PIC code. */ |
16616 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
16617 | { |
16618 | s_ignore (0); | |
16619 | return; | |
16620 | } | |
16621 | ||
16622 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 16623 | macro_start (); |
252b5132 | 16624 | reg = tc_get_register (0); |
67c0d1eb | 16625 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 16626 | macro_end (); |
252b5132 | 16627 | |
bdaaa2e1 | 16628 | demand_empty_rest_of_line (); |
252b5132 RH |
16629 | } |
16630 | ||
16631 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 16632 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
16633 | such as generating jalx instructions when needed. We also make |
16634 | them odd for the duration of the assembly, in order to generate the | |
16635 | right sort of code. We will make them even in the adjust_symtab | |
16636 | routine, while leaving them marked. This is convenient for the | |
16637 | debugger and the disassembler. The linker knows to make them odd | |
16638 | again. */ | |
16639 | ||
16640 | static void | |
17a2f251 | 16641 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16642 | { |
df58fc94 | 16643 | mips_mark_labels (); |
252b5132 RH |
16644 | |
16645 | demand_empty_rest_of_line (); | |
16646 | } | |
16647 | ||
16648 | /* Handle a .stabn directive. We need these in order to mark a label | |
16649 | as being a mips16 text label correctly. Sometimes the compiler | |
16650 | will emit a label, followed by a .stabn, and then switch sections. | |
16651 | If the label and .stabn are in mips16 mode, then the label is | |
16652 | really a mips16 text label. */ | |
16653 | ||
16654 | static void | |
17a2f251 | 16655 | s_mips_stab (int type) |
252b5132 | 16656 | { |
f9419b05 | 16657 | if (type == 'n') |
df58fc94 | 16658 | mips_mark_labels (); |
252b5132 RH |
16659 | |
16660 | s_stab (type); | |
16661 | } | |
16662 | ||
54f4ddb3 | 16663 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
16664 | |
16665 | static void | |
17a2f251 | 16666 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16667 | { |
16668 | char *name; | |
16669 | int c; | |
16670 | symbolS *symbolP; | |
16671 | expressionS exp; | |
16672 | ||
16673 | name = input_line_pointer; | |
16674 | c = get_symbol_end (); | |
16675 | symbolP = symbol_find_or_make (name); | |
16676 | S_SET_WEAK (symbolP); | |
16677 | *input_line_pointer = c; | |
16678 | ||
16679 | SKIP_WHITESPACE (); | |
16680 | ||
16681 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
16682 | { | |
16683 | if (S_IS_DEFINED (symbolP)) | |
16684 | { | |
20203fb9 | 16685 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
16686 | S_GET_NAME (symbolP)); |
16687 | ignore_rest_of_line (); | |
16688 | return; | |
16689 | } | |
bdaaa2e1 | 16690 | |
252b5132 RH |
16691 | if (*input_line_pointer == ',') |
16692 | { | |
16693 | ++input_line_pointer; | |
16694 | SKIP_WHITESPACE (); | |
16695 | } | |
bdaaa2e1 | 16696 | |
252b5132 RH |
16697 | expression (&exp); |
16698 | if (exp.X_op != O_symbol) | |
16699 | { | |
20203fb9 | 16700 | as_bad (_("bad .weakext directive")); |
98d3f06f | 16701 | ignore_rest_of_line (); |
252b5132 RH |
16702 | return; |
16703 | } | |
49309057 | 16704 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
16705 | } |
16706 | ||
16707 | demand_empty_rest_of_line (); | |
16708 | } | |
16709 | ||
16710 | /* Parse a register string into a number. Called from the ECOFF code | |
16711 | to parse .frame. The argument is non-zero if this is the frame | |
16712 | register, so that we can record it in mips_frame_reg. */ | |
16713 | ||
16714 | int | |
17a2f251 | 16715 | tc_get_register (int frame) |
252b5132 | 16716 | { |
707bfff6 | 16717 | unsigned int reg; |
252b5132 RH |
16718 | |
16719 | SKIP_WHITESPACE (); | |
707bfff6 TS |
16720 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
16721 | reg = 0; | |
252b5132 | 16722 | if (frame) |
7a621144 DJ |
16723 | { |
16724 | mips_frame_reg = reg != 0 ? reg : SP; | |
16725 | mips_frame_reg_valid = 1; | |
16726 | mips_cprestore_valid = 0; | |
16727 | } | |
252b5132 RH |
16728 | return reg; |
16729 | } | |
16730 | ||
16731 | valueT | |
17a2f251 | 16732 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
16733 | { |
16734 | int align = bfd_get_section_alignment (stdoutput, seg); | |
16735 | ||
b4c71f56 TS |
16736 | if (IS_ELF) |
16737 | { | |
16738 | /* We don't need to align ELF sections to the full alignment. | |
16739 | However, Irix 5 may prefer that we align them at least to a 16 | |
16740 | byte boundary. We don't bother to align the sections if we | |
16741 | are targeted for an embedded system. */ | |
c41e87e3 | 16742 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
16743 | return addr; |
16744 | if (align > 4) | |
16745 | align = 4; | |
16746 | } | |
252b5132 RH |
16747 | |
16748 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
16749 | } | |
16750 | ||
16751 | /* Utility routine, called from above as well. If called while the | |
16752 | input file is still being read, it's only an approximation. (For | |
16753 | example, a symbol may later become defined which appeared to be | |
16754 | undefined earlier.) */ | |
16755 | ||
16756 | static int | |
17a2f251 | 16757 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
16758 | { |
16759 | if (sym == 0) | |
16760 | return 0; | |
16761 | ||
4d0d148d | 16762 | if (g_switch_value > 0) |
252b5132 RH |
16763 | { |
16764 | const char *symname; | |
16765 | int change; | |
16766 | ||
c9914766 | 16767 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
16768 | register. It can be if it is smaller than the -G size or if |
16769 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 16770 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
16771 | they can. */ |
16772 | symname = S_GET_NAME (sym); | |
16773 | if (symname != (const char *) NULL | |
16774 | && (strcmp (symname, "eprol") == 0 | |
16775 | || strcmp (symname, "etext") == 0 | |
16776 | || strcmp (symname, "_gp") == 0 | |
16777 | || strcmp (symname, "edata") == 0 | |
16778 | || strcmp (symname, "_fbss") == 0 | |
16779 | || strcmp (symname, "_fdata") == 0 | |
16780 | || strcmp (symname, "_ftext") == 0 | |
16781 | || strcmp (symname, "end") == 0 | |
16782 | || strcmp (symname, "_gp_disp") == 0)) | |
16783 | change = 1; | |
16784 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
16785 | && (0 | |
16786 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
16787 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
16788 | && (symbol_get_obj (sym)->ecoff_extern_size | |
16789 | <= g_switch_value)) | |
252b5132 RH |
16790 | #endif |
16791 | /* We must defer this decision until after the whole | |
16792 | file has been read, since there might be a .extern | |
16793 | after the first use of this symbol. */ | |
16794 | || (before_relaxing | |
16795 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 16796 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
16797 | #endif |
16798 | && S_GET_VALUE (sym) == 0) | |
16799 | || (S_GET_VALUE (sym) != 0 | |
16800 | && S_GET_VALUE (sym) <= g_switch_value))) | |
16801 | change = 0; | |
16802 | else | |
16803 | { | |
16804 | const char *segname; | |
16805 | ||
16806 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 16807 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
16808 | && strcmp (segname, ".lit4") != 0); |
16809 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
16810 | && strcmp (segname, ".sbss") != 0 |
16811 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
16812 | && strncmp (segname, ".sbss.", 6) != 0 |
16813 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 16814 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
16815 | } |
16816 | return change; | |
16817 | } | |
16818 | else | |
c9914766 | 16819 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
16820 | return 1; |
16821 | } | |
16822 | ||
5919d012 RS |
16823 | |
16824 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
16825 | ||
16826 | static bfd_boolean | |
17a2f251 | 16827 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
16828 | { |
16829 | asection *symsec; | |
5919d012 RS |
16830 | |
16831 | /* Handle the case of a symbol equated to another symbol. */ | |
16832 | while (symbol_equated_reloc_p (sym)) | |
16833 | { | |
16834 | symbolS *n; | |
16835 | ||
5f0fe04b | 16836 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
16837 | n = symbol_get_value_expression (sym)->X_add_symbol; |
16838 | if (n == sym) | |
16839 | break; | |
16840 | sym = n; | |
16841 | } | |
16842 | ||
df1f3cda DD |
16843 | if (symbol_section_p (sym)) |
16844 | return TRUE; | |
16845 | ||
5919d012 RS |
16846 | symsec = S_GET_SEGMENT (sym); |
16847 | ||
5919d012 RS |
16848 | /* This must duplicate the test in adjust_reloc_syms. */ |
16849 | return (symsec != &bfd_und_section | |
16850 | && symsec != &bfd_abs_section | |
5f0fe04b TS |
16851 | && !bfd_is_com_section (symsec) |
16852 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
16853 | #ifdef OBJ_ELF |
16854 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 16855 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
16856 | #endif |
16857 | ); | |
16858 | } | |
16859 | ||
16860 | ||
252b5132 RH |
16861 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
16862 | extended opcode. SEC is the section the frag is in. */ | |
16863 | ||
16864 | static int | |
17a2f251 | 16865 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
16866 | { |
16867 | int type; | |
3994f87e | 16868 | const struct mips16_immed_operand *op; |
252b5132 RH |
16869 | offsetT val; |
16870 | int mintiny, maxtiny; | |
16871 | segT symsec; | |
98aa84af | 16872 | fragS *sym_frag; |
252b5132 RH |
16873 | |
16874 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
16875 | return 0; | |
16876 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
16877 | return 1; | |
16878 | ||
16879 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
16880 | op = mips16_immed_operands; | |
16881 | while (op->type != type) | |
16882 | { | |
16883 | ++op; | |
9c2799c2 | 16884 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
16885 | } |
16886 | ||
16887 | if (op->unsp) | |
16888 | { | |
16889 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
16890 | { | |
16891 | mintiny = 1; | |
16892 | maxtiny = 1 << op->nbits; | |
16893 | } | |
16894 | else | |
16895 | { | |
16896 | mintiny = 0; | |
16897 | maxtiny = (1 << op->nbits) - 1; | |
16898 | } | |
16899 | } | |
16900 | else | |
16901 | { | |
16902 | mintiny = - (1 << (op->nbits - 1)); | |
16903 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
16904 | } | |
16905 | ||
98aa84af | 16906 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 16907 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 16908 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
16909 | |
16910 | if (op->pcrel) | |
16911 | { | |
16912 | addressT addr; | |
16913 | ||
16914 | /* We won't have the section when we are called from | |
16915 | mips_relax_frag. However, we will always have been called | |
16916 | from md_estimate_size_before_relax first. If this is a | |
16917 | branch to a different section, we mark it as such. If SEC is | |
16918 | NULL, and the frag is not marked, then it must be a branch to | |
16919 | the same section. */ | |
16920 | if (sec == NULL) | |
16921 | { | |
16922 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
16923 | return 1; | |
16924 | } | |
16925 | else | |
16926 | { | |
98aa84af | 16927 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
16928 | if (symsec != sec) |
16929 | { | |
16930 | fragp->fr_subtype = | |
16931 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
16932 | ||
16933 | /* FIXME: We should support this, and let the linker | |
16934 | catch branches and loads that are out of range. */ | |
16935 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
16936 | _("unsupported PC relative reference to different section")); | |
16937 | ||
16938 | return 1; | |
16939 | } | |
98aa84af AM |
16940 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
16941 | /* Assume non-extended on the first relaxation pass. | |
16942 | The address we have calculated will be bogus if this is | |
16943 | a forward branch to another frag, as the forward frag | |
16944 | will have fr_address == 0. */ | |
16945 | return 0; | |
252b5132 RH |
16946 | } |
16947 | ||
16948 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
16949 | the same section. If the relax_marker of the symbol fragment |
16950 | differs from the relax_marker of this fragment, we have not | |
16951 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
16952 | in STRETCH in order to get a better estimate of the address. |
16953 | This particularly matters because of the shift bits. */ | |
16954 | if (stretch != 0 | |
98aa84af | 16955 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
16956 | { |
16957 | fragS *f; | |
16958 | ||
16959 | /* Adjust stretch for any alignment frag. Note that if have | |
16960 | been expanding the earlier code, the symbol may be | |
16961 | defined in what appears to be an earlier frag. FIXME: | |
16962 | This doesn't handle the fr_subtype field, which specifies | |
16963 | a maximum number of bytes to skip when doing an | |
16964 | alignment. */ | |
98aa84af | 16965 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
16966 | { |
16967 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
16968 | { | |
16969 | if (stretch < 0) | |
16970 | stretch = - ((- stretch) | |
16971 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
16972 | else | |
16973 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
16974 | if (stretch == 0) | |
16975 | break; | |
16976 | } | |
16977 | } | |
16978 | if (f != NULL) | |
16979 | val += stretch; | |
16980 | } | |
16981 | ||
16982 | addr = fragp->fr_address + fragp->fr_fix; | |
16983 | ||
16984 | /* The base address rules are complicated. The base address of | |
16985 | a branch is the following instruction. The base address of a | |
16986 | PC relative load or add is the instruction itself, but if it | |
16987 | is in a delay slot (in which case it can not be extended) use | |
16988 | the address of the instruction whose delay slot it is in. */ | |
16989 | if (type == 'p' || type == 'q') | |
16990 | { | |
16991 | addr += 2; | |
16992 | ||
16993 | /* If we are currently assuming that this frag should be | |
16994 | extended, then, the current address is two bytes | |
bdaaa2e1 | 16995 | higher. */ |
252b5132 RH |
16996 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
16997 | addr += 2; | |
16998 | ||
16999 | /* Ignore the low bit in the target, since it will be set | |
17000 | for a text label. */ | |
17001 | if ((val & 1) != 0) | |
17002 | --val; | |
17003 | } | |
17004 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17005 | addr -= 4; | |
17006 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17007 | addr -= 2; | |
17008 | ||
17009 | val -= addr & ~ ((1 << op->shift) - 1); | |
17010 | ||
17011 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
17012 | if (type == 'p' || type == 'q') | |
17013 | val /= 2; | |
17014 | ||
17015 | /* If any of the shifted bits are set, we must use an extended | |
17016 | opcode. If the address depends on the size of this | |
17017 | instruction, this can lead to a loop, so we arrange to always | |
17018 | use an extended opcode. We only check this when we are in | |
17019 | the main relaxation loop, when SEC is NULL. */ | |
17020 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
17021 | { | |
17022 | fragp->fr_subtype = | |
17023 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17024 | return 1; | |
17025 | } | |
17026 | ||
17027 | /* If we are about to mark a frag as extended because the value | |
17028 | is precisely maxtiny + 1, then there is a chance of an | |
17029 | infinite loop as in the following code: | |
17030 | la $4,foo | |
17031 | .skip 1020 | |
17032 | .align 2 | |
17033 | foo: | |
17034 | In this case when the la is extended, foo is 0x3fc bytes | |
17035 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17036 | the la must be extended. To avoid this loop, we mark the | |
17037 | frag as extended if it was small, and is about to become | |
17038 | extended with a value of maxtiny + 1. */ | |
17039 | if (val == ((maxtiny + 1) << op->shift) | |
17040 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
17041 | && sec == NULL) | |
17042 | { | |
17043 | fragp->fr_subtype = | |
17044 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17045 | return 1; | |
17046 | } | |
17047 | } | |
17048 | else if (symsec != absolute_section && sec != NULL) | |
17049 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
17050 | ||
17051 | if ((val & ((1 << op->shift) - 1)) != 0 | |
17052 | || val < (mintiny << op->shift) | |
17053 | || val > (maxtiny << op->shift)) | |
17054 | return 1; | |
17055 | else | |
17056 | return 0; | |
17057 | } | |
17058 | ||
4a6a3df4 AO |
17059 | /* Compute the length of a branch sequence, and adjust the |
17060 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17061 | worst-case length is computed, with UPDATE being used to indicate | |
17062 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17063 | branch is to be computed. */ | |
17064 | static int | |
17a2f251 | 17065 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17066 | { |
b34976b6 | 17067 | bfd_boolean toofar; |
4a6a3df4 AO |
17068 | int length; |
17069 | ||
17070 | if (fragp | |
17071 | && S_IS_DEFINED (fragp->fr_symbol) | |
17072 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17073 | { | |
17074 | addressT addr; | |
17075 | offsetT val; | |
17076 | ||
17077 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17078 | ||
17079 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17080 | ||
17081 | val -= addr; | |
17082 | ||
17083 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17084 | } | |
17085 | else if (fragp) | |
17086 | /* If the symbol is not defined or it's in a different segment, | |
17087 | assume the user knows what's going on and emit a short | |
17088 | branch. */ | |
b34976b6 | 17089 | toofar = FALSE; |
4a6a3df4 | 17090 | else |
b34976b6 | 17091 | toofar = TRUE; |
4a6a3df4 AO |
17092 | |
17093 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17094 | fragp->fr_subtype | |
66b3e8da MR |
17095 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
17096 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
17097 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17098 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17099 | toofar); | |
17100 | ||
17101 | length = 4; | |
17102 | if (toofar) | |
17103 | { | |
17104 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17105 | length += 8; | |
17106 | ||
17107 | if (mips_pic != NO_PIC) | |
17108 | { | |
17109 | /* Additional space for PIC loading of target address. */ | |
17110 | length += 8; | |
17111 | if (mips_opts.isa == ISA_MIPS1) | |
17112 | /* Additional space for $at-stabilizing nop. */ | |
17113 | length += 4; | |
17114 | } | |
17115 | ||
17116 | /* If branch is conditional. */ | |
17117 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17118 | length += 8; | |
17119 | } | |
b34976b6 | 17120 | |
4a6a3df4 AO |
17121 | return length; |
17122 | } | |
17123 | ||
df58fc94 RS |
17124 | /* Compute the length of a branch sequence, and adjust the |
17125 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17126 | worst-case length is computed, with UPDATE being used to indicate | |
17127 | whether an unconditional (-1), or regular (0) branch is to be | |
17128 | computed. */ | |
17129 | ||
17130 | static int | |
17131 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17132 | { | |
17133 | bfd_boolean toofar; | |
17134 | int length; | |
17135 | ||
17136 | if (fragp | |
17137 | && S_IS_DEFINED (fragp->fr_symbol) | |
17138 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17139 | { | |
17140 | addressT addr; | |
17141 | offsetT val; | |
17142 | ||
17143 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17144 | /* Ignore the low bit in the target, since it will be set | |
17145 | for a text label. */ | |
17146 | if ((val & 1) != 0) | |
17147 | --val; | |
17148 | ||
17149 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17150 | ||
17151 | val -= addr; | |
17152 | ||
17153 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17154 | } | |
17155 | else if (fragp) | |
17156 | /* If the symbol is not defined or it's in a different segment, | |
17157 | assume the user knows what's going on and emit a short | |
17158 | branch. */ | |
17159 | toofar = FALSE; | |
17160 | else | |
17161 | toofar = TRUE; | |
17162 | ||
17163 | if (fragp && update | |
17164 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17165 | fragp->fr_subtype = (toofar | |
17166 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17167 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17168 | ||
17169 | length = 4; | |
17170 | if (toofar) | |
17171 | { | |
17172 | bfd_boolean compact_known = fragp != NULL; | |
17173 | bfd_boolean compact = FALSE; | |
17174 | bfd_boolean uncond; | |
17175 | ||
17176 | if (compact_known) | |
17177 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17178 | if (fragp) | |
17179 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
17180 | else | |
17181 | uncond = update < 0; | |
17182 | ||
17183 | /* If label is out of range, we turn branch <br>: | |
17184 | ||
17185 | <br> label # 4 bytes | |
17186 | 0: | |
17187 | ||
17188 | into: | |
17189 | ||
17190 | j label # 4 bytes | |
17191 | nop # 2 bytes if compact && !PIC | |
17192 | 0: | |
17193 | */ | |
17194 | if (mips_pic == NO_PIC && (!compact_known || compact)) | |
17195 | length += 2; | |
17196 | ||
17197 | /* If assembling PIC code, we further turn: | |
17198 | ||
17199 | j label # 4 bytes | |
17200 | ||
17201 | into: | |
17202 | ||
17203 | lw/ld at, %got(label)(gp) # 4 bytes | |
17204 | d/addiu at, %lo(label) # 4 bytes | |
17205 | jr/c at # 2 bytes | |
17206 | */ | |
17207 | if (mips_pic != NO_PIC) | |
17208 | length += 6; | |
17209 | ||
17210 | /* If branch <br> is conditional, we prepend negated branch <brneg>: | |
17211 | ||
17212 | <brneg> 0f # 4 bytes | |
17213 | nop # 2 bytes if !compact | |
17214 | */ | |
17215 | if (!uncond) | |
17216 | length += (compact_known && compact) ? 4 : 6; | |
17217 | } | |
17218 | ||
17219 | return length; | |
17220 | } | |
17221 | ||
17222 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17223 | bit accordingly. */ | |
17224 | ||
17225 | static int | |
17226 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17227 | { | |
17228 | bfd_boolean toofar; | |
17229 | ||
17230 | if (RELAX_MICROMIPS_U16BIT (fragp->fr_subtype)) | |
17231 | return 2; | |
17232 | ||
17233 | if (fragp | |
17234 | && S_IS_DEFINED (fragp->fr_symbol) | |
17235 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17236 | { | |
17237 | addressT addr; | |
17238 | offsetT val; | |
17239 | int type; | |
17240 | ||
17241 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17242 | /* Ignore the low bit in the target, since it will be set | |
17243 | for a text label. */ | |
17244 | if ((val & 1) != 0) | |
17245 | --val; | |
17246 | ||
17247 | /* Assume this is a 2-byte branch. */ | |
17248 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17249 | ||
17250 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17251 | long branches. */ | |
17252 | ||
17253 | val -= addr; | |
17254 | ||
17255 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17256 | if (type == 'D') | |
17257 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17258 | else if (type == 'E') | |
17259 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17260 | else | |
17261 | abort (); | |
17262 | } | |
17263 | else | |
17264 | /* If the symbol is not defined or it's in a different segment, | |
17265 | we emit a normal 32-bit branch. */ | |
17266 | toofar = TRUE; | |
17267 | ||
17268 | if (fragp && update | |
17269 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17270 | fragp->fr_subtype | |
17271 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17272 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17273 | ||
17274 | if (toofar) | |
17275 | return 4; | |
17276 | ||
17277 | return 2; | |
17278 | } | |
17279 | ||
252b5132 RH |
17280 | /* Estimate the size of a frag before relaxing. Unless this is the |
17281 | mips16, we are not really relaxing here, and the final size is | |
17282 | encoded in the subtype information. For the mips16, we have to | |
17283 | decide whether we are using an extended opcode or not. */ | |
17284 | ||
252b5132 | 17285 | int |
17a2f251 | 17286 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17287 | { |
5919d012 | 17288 | int change; |
252b5132 | 17289 | |
4a6a3df4 AO |
17290 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17291 | { | |
17292 | ||
b34976b6 AM |
17293 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17294 | ||
4a6a3df4 AO |
17295 | return fragp->fr_var; |
17296 | } | |
17297 | ||
252b5132 | 17298 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
17299 | /* We don't want to modify the EXTENDED bit here; it might get us |
17300 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17301 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 | 17302 | |
df58fc94 RS |
17303 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17304 | { | |
17305 | int length = 4; | |
17306 | ||
17307 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17308 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17309 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17310 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17311 | fragp->fr_var = length; | |
17312 | ||
17313 | return length; | |
17314 | } | |
17315 | ||
252b5132 | 17316 | if (mips_pic == NO_PIC) |
5919d012 | 17317 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 17318 | else if (mips_pic == SVR4_PIC) |
5919d012 | 17319 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
17320 | else if (mips_pic == VXWORKS_PIC) |
17321 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
17322 | change = 0; | |
252b5132 RH |
17323 | else |
17324 | abort (); | |
17325 | ||
17326 | if (change) | |
17327 | { | |
4d7206a2 | 17328 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17329 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17330 | } |
4d7206a2 RS |
17331 | else |
17332 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17333 | } |
17334 | ||
17335 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17336 | should be converted into a reloc against a section. */ |
252b5132 RH |
17337 | |
17338 | int | |
17a2f251 | 17339 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17340 | { |
252b5132 RH |
17341 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17342 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17343 | return 0; | |
a161fe53 | 17344 | |
252b5132 RH |
17345 | if (fixp->fx_addsy == NULL) |
17346 | return 1; | |
a161fe53 | 17347 | |
de7e6852 RS |
17348 | /* If symbol SYM is in a mergeable section, relocations of the form |
17349 | SYM + 0 can usually be made section-relative. The mergeable data | |
17350 | is then identified by the section offset rather than by the symbol. | |
17351 | ||
17352 | However, if we're generating REL LO16 relocations, the offset is split | |
17353 | between the LO16 and parterning high part relocation. The linker will | |
17354 | need to recalculate the complete offset in order to correctly identify | |
17355 | the merge data. | |
17356 | ||
17357 | The linker has traditionally not looked for the parterning high part | |
17358 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
17359 | placed anywhere. Rather than break backwards compatibility by changing | |
17360 | this, it seems better not to force the issue, and instead keep the | |
17361 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 17362 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 17363 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
17364 | && HAVE_IN_PLACE_ADDENDS |
17365 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
17366 | return 0; | |
17367 | ||
ce70d90a MR |
17368 | /* There is no place to store an in-place offset for JALR relocations. |
17369 | Likewise an in-range offset of PC-relative relocations may overflow | |
17370 | the in-place relocatable field if recalculated against the start | |
17371 | address of the symbol's containing section. */ | |
17372 | if (HAVE_IN_PLACE_ADDENDS | |
df58fc94 | 17373 | && (fixp->fx_pcrel || jalr_reloc_p (fixp->fx_r_type))) |
1180b5a4 RS |
17374 | return 0; |
17375 | ||
252b5132 | 17376 | #ifdef OBJ_ELF |
b314ec0e RS |
17377 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
17378 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
17379 | relocations against MIPS16 functions; in this case, the stub becomes | |
17380 | the function's canonical address. | |
17381 | ||
17382 | Floating-point stubs are stored in unique .mips16.call.* or | |
17383 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
17384 | the first relocation in section S must be against F; this is how the | |
17385 | linker determines the target function. All relocations that might | |
17386 | resolve to T must also be against F. We therefore have the following | |
17387 | restrictions, which are given in an intentionally-redundant way: | |
17388 | ||
17389 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
17390 | symbols. | |
17391 | ||
17392 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
17393 | if that stub might be used. | |
17394 | ||
17395 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
17396 | symbols. | |
17397 | ||
17398 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
17399 | that stub might be used. | |
17400 | ||
17401 | There is a further restriction: | |
17402 | ||
df58fc94 RS |
17403 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
17404 | R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on | |
17405 | targets with in-place addends; the relocation field cannot | |
b314ec0e RS |
17406 | encode the low bit. |
17407 | ||
df58fc94 RS |
17408 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
17409 | against a MIPS16 symbol. We deal with (5) by by not reducing any | |
17410 | such relocations on REL targets. | |
b314ec0e RS |
17411 | |
17412 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
17413 | relocation against some symbol R, no relocation against R may be | |
17414 | reduced. (Note that this deals with (2) as well as (1) because | |
17415 | relocations against global symbols will never be reduced on ELF | |
17416 | targets.) This approach is a little simpler than trying to detect | |
17417 | stub sections, and gives the "all or nothing" per-symbol consistency | |
17418 | that we have for MIPS16 symbols. */ | |
f43abd2b | 17419 | if (IS_ELF |
b314ec0e | 17420 | && fixp->fx_subsy == NULL |
30c09090 | 17421 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
df58fc94 RS |
17422 | || *symbol_get_tc (fixp->fx_addsy) |
17423 | || (HAVE_IN_PLACE_ADDENDS | |
17424 | && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) | |
17425 | && jmp_reloc_p (fixp->fx_r_type)))) | |
252b5132 RH |
17426 | return 0; |
17427 | #endif | |
a161fe53 | 17428 | |
252b5132 RH |
17429 | return 1; |
17430 | } | |
17431 | ||
17432 | /* Translate internal representation of relocation info to BFD target | |
17433 | format. */ | |
17434 | ||
17435 | arelent ** | |
17a2f251 | 17436 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
17437 | { |
17438 | static arelent *retval[4]; | |
17439 | arelent *reloc; | |
17440 | bfd_reloc_code_real_type code; | |
17441 | ||
4b0cff4e TS |
17442 | memset (retval, 0, sizeof(retval)); |
17443 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
17444 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
17445 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
17446 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
17447 | ||
bad36eac DJ |
17448 | if (fixp->fx_pcrel) |
17449 | { | |
df58fc94 RS |
17450 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
17451 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
17452 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
17453 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
bad36eac DJ |
17454 | |
17455 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
17456 | Relocations want only the symbol offset. */ | |
17457 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 17458 | if (!IS_ELF) |
bad36eac DJ |
17459 | { |
17460 | /* A gruesome hack which is a result of the gruesome gas | |
17461 | reloc handling. What's worse, for COFF (as opposed to | |
17462 | ECOFF), we might need yet another copy of reloc->address. | |
17463 | See bfd_install_relocation. */ | |
17464 | reloc->addend += reloc->address; | |
17465 | } | |
17466 | } | |
17467 | else | |
17468 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 17469 | |
438c16b8 TS |
17470 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
17471 | entry to be used in the relocation's section offset. */ | |
17472 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
17473 | { |
17474 | reloc->address = reloc->addend; | |
17475 | reloc->addend = 0; | |
17476 | } | |
17477 | ||
252b5132 | 17478 | code = fixp->fx_r_type; |
252b5132 | 17479 | |
bad36eac | 17480 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
17481 | if (reloc->howto == NULL) |
17482 | { | |
17483 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
17484 | _("Can not represent %s relocation in this object file format"), | |
17485 | bfd_get_reloc_code_name (code)); | |
17486 | retval[0] = NULL; | |
17487 | } | |
17488 | ||
17489 | return retval; | |
17490 | } | |
17491 | ||
17492 | /* Relax a machine dependent frag. This returns the amount by which | |
17493 | the current size of the frag should change. */ | |
17494 | ||
17495 | int | |
17a2f251 | 17496 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 17497 | { |
4a6a3df4 AO |
17498 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17499 | { | |
17500 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
17501 | |
17502 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
17503 | |
17504 | return fragp->fr_var - old_var; | |
17505 | } | |
17506 | ||
df58fc94 RS |
17507 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17508 | { | |
17509 | offsetT old_var = fragp->fr_var; | |
17510 | offsetT new_var = 4; | |
17511 | ||
17512 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17513 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
17514 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17515 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
17516 | fragp->fr_var = new_var; | |
17517 | ||
17518 | return new_var - old_var; | |
17519 | } | |
17520 | ||
252b5132 RH |
17521 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
17522 | return 0; | |
17523 | ||
c4e7957c | 17524 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
17525 | { |
17526 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17527 | return 0; | |
17528 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
17529 | return 2; | |
17530 | } | |
17531 | else | |
17532 | { | |
17533 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17534 | return 0; | |
17535 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
17536 | return -2; | |
17537 | } | |
17538 | ||
17539 | return 0; | |
17540 | } | |
17541 | ||
17542 | /* Convert a machine dependent frag. */ | |
17543 | ||
17544 | void | |
17a2f251 | 17545 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 17546 | { |
4a6a3df4 AO |
17547 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17548 | { | |
17549 | bfd_byte *buf; | |
17550 | unsigned long insn; | |
17551 | expressionS exp; | |
17552 | fixS *fixp; | |
b34976b6 | 17553 | |
4a6a3df4 AO |
17554 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
17555 | ||
17556 | if (target_big_endian) | |
17557 | insn = bfd_getb32 (buf); | |
17558 | else | |
17559 | insn = bfd_getl32 (buf); | |
b34976b6 | 17560 | |
4a6a3df4 AO |
17561 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
17562 | { | |
17563 | /* We generate a fixup instead of applying it right now | |
17564 | because, if there are linker relaxations, we're going to | |
17565 | need the relocations. */ | |
17566 | exp.X_op = O_symbol; | |
17567 | exp.X_add_symbol = fragp->fr_symbol; | |
17568 | exp.X_add_number = fragp->fr_offset; | |
17569 | ||
17570 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 17571 | 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
17572 | fixp->fx_file = fragp->fr_file; |
17573 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 17574 | |
2132e3a3 | 17575 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17576 | buf += 4; |
17577 | } | |
17578 | else | |
17579 | { | |
17580 | int i; | |
17581 | ||
17582 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 17583 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
17584 | |
17585 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
17586 | goto uncond; | |
17587 | ||
17588 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17589 | { | |
17590 | /* Reverse the branch. */ | |
17591 | switch ((insn >> 28) & 0xf) | |
17592 | { | |
17593 | case 4: | |
17594 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
17595 | have the condition reversed by tweaking a single | |
17596 | bit, and their opcodes all have 0x4???????. */ | |
9c2799c2 | 17597 | gas_assert ((insn & 0xf1000000) == 0x41000000); |
4a6a3df4 AO |
17598 | insn ^= 0x00010000; |
17599 | break; | |
17600 | ||
17601 | case 0: | |
17602 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 17603 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 17604 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
17605 | insn ^= 0x00010000; |
17606 | break; | |
b34976b6 | 17607 | |
4a6a3df4 AO |
17608 | case 1: |
17609 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 17610 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
17611 | insn ^= 0x04000000; |
17612 | break; | |
17613 | ||
17614 | default: | |
17615 | abort (); | |
17616 | } | |
17617 | } | |
17618 | ||
17619 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
17620 | { | |
17621 | /* Clear the and-link bit. */ | |
9c2799c2 | 17622 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 17623 | |
54f4ddb3 TS |
17624 | /* bltzal 0x04100000 bgezal 0x04110000 |
17625 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
17626 | insn &= ~0x00100000; |
17627 | } | |
17628 | ||
17629 | /* Branch over the branch (if the branch was likely) or the | |
17630 | full jump (not likely case). Compute the offset from the | |
17631 | current instruction to branch to. */ | |
17632 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17633 | i = 16; | |
17634 | else | |
17635 | { | |
17636 | /* How many bytes in instructions we've already emitted? */ | |
17637 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
17638 | /* How many bytes in instructions from here to the end? */ | |
17639 | i = fragp->fr_var - i; | |
17640 | } | |
17641 | /* Convert to instruction count. */ | |
17642 | i >>= 2; | |
17643 | /* Branch counts from the next instruction. */ | |
b34976b6 | 17644 | i--; |
4a6a3df4 AO |
17645 | insn |= i; |
17646 | /* Branch over the jump. */ | |
2132e3a3 | 17647 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17648 | buf += 4; |
17649 | ||
54f4ddb3 | 17650 | /* nop */ |
2132e3a3 | 17651 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
17652 | buf += 4; |
17653 | ||
17654 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17655 | { | |
17656 | /* beql $0, $0, 2f */ | |
17657 | insn = 0x50000000; | |
17658 | /* Compute the PC offset from the current instruction to | |
17659 | the end of the variable frag. */ | |
17660 | /* How many bytes in instructions we've already emitted? */ | |
17661 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
17662 | /* How many bytes in instructions from here to the end? */ | |
17663 | i = fragp->fr_var - i; | |
17664 | /* Convert to instruction count. */ | |
17665 | i >>= 2; | |
17666 | /* Don't decrement i, because we want to branch over the | |
17667 | delay slot. */ | |
17668 | ||
17669 | insn |= i; | |
2132e3a3 | 17670 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17671 | buf += 4; |
17672 | ||
2132e3a3 | 17673 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
17674 | buf += 4; |
17675 | } | |
17676 | ||
17677 | uncond: | |
17678 | if (mips_pic == NO_PIC) | |
17679 | { | |
17680 | /* j or jal. */ | |
17681 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
17682 | ? 0x0c000000 : 0x08000000); | |
17683 | exp.X_op = O_symbol; | |
17684 | exp.X_add_symbol = fragp->fr_symbol; | |
17685 | exp.X_add_number = fragp->fr_offset; | |
17686 | ||
17687 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 17688 | 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); |
4a6a3df4 AO |
17689 | fixp->fx_file = fragp->fr_file; |
17690 | fixp->fx_line = fragp->fr_line; | |
17691 | ||
2132e3a3 | 17692 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17693 | buf += 4; |
17694 | } | |
17695 | else | |
17696 | { | |
66b3e8da MR |
17697 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
17698 | ||
4a6a3df4 | 17699 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
17700 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
17701 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
17702 | exp.X_op = O_symbol; |
17703 | exp.X_add_symbol = fragp->fr_symbol; | |
17704 | exp.X_add_number = fragp->fr_offset; | |
17705 | ||
17706 | if (fragp->fr_offset) | |
17707 | { | |
17708 | exp.X_add_symbol = make_expr_symbol (&exp); | |
17709 | exp.X_add_number = 0; | |
17710 | } | |
17711 | ||
17712 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 17713 | 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16); |
4a6a3df4 AO |
17714 | fixp->fx_file = fragp->fr_file; |
17715 | fixp->fx_line = fragp->fr_line; | |
17716 | ||
2132e3a3 | 17717 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 17718 | buf += 4; |
b34976b6 | 17719 | |
4a6a3df4 AO |
17720 | if (mips_opts.isa == ISA_MIPS1) |
17721 | { | |
17722 | /* nop */ | |
2132e3a3 | 17723 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
17724 | buf += 4; |
17725 | } | |
17726 | ||
17727 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
17728 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
17729 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 AO |
17730 | |
17731 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 17732 | 4, &exp, FALSE, BFD_RELOC_LO16); |
4a6a3df4 AO |
17733 | fixp->fx_file = fragp->fr_file; |
17734 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 17735 | |
2132e3a3 | 17736 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17737 | buf += 4; |
17738 | ||
17739 | /* j(al)r $at. */ | |
17740 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 17741 | insn = 0x0000f809; |
4a6a3df4 | 17742 | else |
66b3e8da MR |
17743 | insn = 0x00000008; |
17744 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 17745 | |
2132e3a3 | 17746 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17747 | buf += 4; |
17748 | } | |
17749 | } | |
17750 | ||
9c2799c2 | 17751 | gas_assert (buf == (bfd_byte *)fragp->fr_literal |
4a6a3df4 AO |
17752 | + fragp->fr_fix + fragp->fr_var); |
17753 | ||
17754 | fragp->fr_fix += fragp->fr_var; | |
17755 | ||
17756 | return; | |
17757 | } | |
17758 | ||
df58fc94 RS |
17759 | /* Relax microMIPS branches. */ |
17760 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
17761 | { | |
17762 | bfd_byte *buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
17763 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17764 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); | |
17765 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 17766 | bfd_boolean short_ds; |
df58fc94 RS |
17767 | unsigned long insn; |
17768 | expressionS exp; | |
17769 | fixS *fixp; | |
17770 | ||
17771 | exp.X_op = O_symbol; | |
17772 | exp.X_add_symbol = fragp->fr_symbol; | |
17773 | exp.X_add_number = fragp->fr_offset; | |
17774 | ||
17775 | fragp->fr_fix += fragp->fr_var; | |
17776 | ||
17777 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
17778 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17779 | { | |
17780 | /* We generate a fixup instead of applying it right now, | |
17781 | because if there is linker relaxation, we're going to | |
17782 | need the relocations. */ | |
17783 | if (type == 'D') | |
17784 | fixp = fix_new_exp (fragp, | |
17785 | buf - (bfd_byte *) fragp->fr_literal, | |
17786 | 2, &exp, TRUE, | |
17787 | BFD_RELOC_MICROMIPS_10_PCREL_S1); | |
17788 | else if (type == 'E') | |
17789 | fixp = fix_new_exp (fragp, | |
17790 | buf - (bfd_byte *) fragp->fr_literal, | |
17791 | 2, &exp, TRUE, | |
17792 | BFD_RELOC_MICROMIPS_7_PCREL_S1); | |
17793 | else | |
17794 | abort (); | |
17795 | ||
17796 | fixp->fx_file = fragp->fr_file; | |
17797 | fixp->fx_line = fragp->fr_line; | |
17798 | ||
17799 | /* These relocations can have an addend that won't fit in | |
17800 | 2 octets. */ | |
17801 | fixp->fx_no_overflow = 1; | |
17802 | ||
17803 | return; | |
17804 | } | |
17805 | ||
2309ddf2 | 17806 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
17807 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
17808 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17809 | { | |
17810 | /* We generate a fixup instead of applying it right now, | |
17811 | because if there is linker relaxation, we're going to | |
17812 | need the relocations. */ | |
17813 | fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
17814 | 4, &exp, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
17815 | fixp->fx_file = fragp->fr_file; | |
17816 | fixp->fx_line = fragp->fr_line; | |
17817 | ||
17818 | if (type == 0) | |
17819 | return; | |
17820 | } | |
17821 | ||
17822 | /* Relax 16-bit branches to 32-bit branches. */ | |
17823 | if (type != 0) | |
17824 | { | |
17825 | if (target_big_endian) | |
17826 | insn = bfd_getb16 (buf); | |
17827 | else | |
17828 | insn = bfd_getl16 (buf); | |
17829 | ||
17830 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
17831 | insn = 0x94000000; /* beq */ | |
17832 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
17833 | { | |
17834 | unsigned long regno; | |
17835 | ||
17836 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
17837 | regno = micromips_to_32_reg_d_map [regno]; | |
17838 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
17839 | insn |= regno << MICROMIPSOP_SH_RS; | |
17840 | } | |
17841 | else | |
17842 | abort (); | |
17843 | ||
17844 | /* Nothing else to do, just write it out. */ | |
17845 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
17846 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17847 | { | |
17848 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
17849 | buf += 2; | |
17850 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
17851 | buf += 2; | |
17852 | ||
17853 | gas_assert (buf == ((bfd_byte *) fragp->fr_literal | |
17854 | + fragp->fr_fix)); | |
17855 | return; | |
17856 | } | |
17857 | } | |
17858 | else | |
17859 | { | |
17860 | unsigned long next; | |
17861 | ||
17862 | if (target_big_endian) | |
17863 | { | |
17864 | insn = bfd_getb16 (buf); | |
17865 | next = bfd_getb16 (buf + 2); | |
17866 | } | |
17867 | else | |
17868 | { | |
17869 | insn = bfd_getl16 (buf); | |
17870 | next = bfd_getl16 (buf + 2); | |
17871 | } | |
17872 | insn = (insn << 16) | next; | |
17873 | } | |
17874 | ||
17875 | /* Relax 32-bit branches to a sequence of instructions. */ | |
17876 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
17877 | _("Relaxed out-of-range branch into a jump")); | |
17878 | ||
2309ddf2 MR |
17879 | /* Set the short-delay-slot bit. */ |
17880 | short_ds = al && (insn & 0x02000000) != 0; | |
df58fc94 RS |
17881 | |
17882 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
17883 | { | |
17884 | symbolS *l; | |
17885 | ||
17886 | /* Reverse the branch. */ | |
17887 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
17888 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
17889 | insn ^= 0x20000000; | |
17890 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
17891 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
17892 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
17893 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
17894 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
17895 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
17896 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
17897 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
17898 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
17899 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
17900 | insn ^= 0x00400000; | |
17901 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
17902 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
17903 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
17904 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
17905 | insn ^= 0x00200000; | |
17906 | else | |
17907 | abort (); | |
17908 | ||
17909 | if (al) | |
17910 | { | |
17911 | /* Clear the and-link and short-delay-slot bits. */ | |
17912 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
17913 | ||
17914 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
17915 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
17916 | insn &= ~0x02200000; | |
17917 | } | |
17918 | ||
17919 | /* Make a label at the end for use with the branch. */ | |
17920 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
17921 | micromips_label_inc (); | |
17922 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
17923 | if (IS_ELF) | |
17924 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); | |
17925 | #endif | |
17926 | ||
17927 | /* Refer to it. */ | |
17928 | fixp = fix_new (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
17929 | 4, l, 0, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
17930 | fixp->fx_file = fragp->fr_file; | |
17931 | fixp->fx_line = fragp->fr_line; | |
17932 | ||
17933 | /* Branch over the jump. */ | |
17934 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
17935 | buf += 2; | |
17936 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
17937 | buf += 2; | |
17938 | ||
17939 | if (!compact) | |
17940 | { | |
17941 | /* nop */ | |
17942 | insn = 0x0c00; | |
17943 | md_number_to_chars ((char *) buf, insn, 2); | |
17944 | buf += 2; | |
17945 | } | |
17946 | } | |
17947 | ||
17948 | if (mips_pic == NO_PIC) | |
17949 | { | |
2309ddf2 MR |
17950 | unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */ |
17951 | ||
df58fc94 RS |
17952 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
17953 | insn = al ? jal : 0xd4000000; | |
17954 | ||
17955 | fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
17956 | 4, &exp, FALSE, BFD_RELOC_MICROMIPS_JMP); | |
17957 | fixp->fx_file = fragp->fr_file; | |
17958 | fixp->fx_line = fragp->fr_line; | |
17959 | ||
17960 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
17961 | buf += 2; | |
17962 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
17963 | buf += 2; | |
17964 | ||
17965 | if (compact) | |
17966 | { | |
17967 | /* nop */ | |
17968 | insn = 0x0c00; | |
17969 | md_number_to_chars ((char *) buf, insn, 2); | |
17970 | buf += 2; | |
17971 | } | |
17972 | } | |
17973 | else | |
17974 | { | |
17975 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
2309ddf2 MR |
17976 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ |
17977 | unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */ | |
df58fc94 RS |
17978 | |
17979 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
17980 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
17981 | insn |= at << MICROMIPSOP_SH_RT; | |
17982 | ||
17983 | if (exp.X_add_number) | |
17984 | { | |
17985 | exp.X_add_symbol = make_expr_symbol (&exp); | |
17986 | exp.X_add_number = 0; | |
17987 | } | |
17988 | ||
17989 | fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
17990 | 4, &exp, FALSE, BFD_RELOC_MICROMIPS_GOT16); | |
17991 | fixp->fx_file = fragp->fr_file; | |
17992 | fixp->fx_line = fragp->fr_line; | |
17993 | ||
17994 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
17995 | buf += 2; | |
17996 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
17997 | buf += 2; | |
17998 | ||
17999 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18000 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18001 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18002 | ||
18003 | fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
18004 | 4, &exp, FALSE, BFD_RELOC_MICROMIPS_LO16); | |
18005 | fixp->fx_file = fragp->fr_file; | |
18006 | fixp->fx_line = fragp->fr_line; | |
18007 | ||
18008 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
18009 | buf += 2; | |
18010 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
18011 | buf += 2; | |
18012 | ||
18013 | /* jr/jrc/jalr/jalrs $at */ | |
18014 | insn = al ? jalr : jr; | |
18015 | insn |= at << MICROMIPSOP_SH_MJ; | |
18016 | ||
18017 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
18018 | buf += 2; | |
18019 | } | |
18020 | ||
18021 | gas_assert (buf == (bfd_byte *) fragp->fr_literal + fragp->fr_fix); | |
18022 | return; | |
18023 | } | |
18024 | ||
252b5132 RH |
18025 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18026 | { | |
18027 | int type; | |
3994f87e | 18028 | const struct mips16_immed_operand *op; |
b34976b6 | 18029 | bfd_boolean small, ext; |
252b5132 RH |
18030 | offsetT val; |
18031 | bfd_byte *buf; | |
18032 | unsigned long insn; | |
b34976b6 | 18033 | bfd_boolean use_extend; |
252b5132 RH |
18034 | unsigned short extend; |
18035 | ||
18036 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
18037 | op = mips16_immed_operands; | |
18038 | while (op->type != type) | |
18039 | ++op; | |
18040 | ||
18041 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18042 | { | |
b34976b6 AM |
18043 | small = FALSE; |
18044 | ext = TRUE; | |
252b5132 RH |
18045 | } |
18046 | else | |
18047 | { | |
b34976b6 AM |
18048 | small = TRUE; |
18049 | ext = FALSE; | |
252b5132 RH |
18050 | } |
18051 | ||
5f5f22c0 | 18052 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
18053 | if (op->pcrel) |
18054 | { | |
18055 | addressT addr; | |
18056 | ||
18057 | addr = fragp->fr_address + fragp->fr_fix; | |
18058 | ||
18059 | /* The rules for the base address of a PC relative reloc are | |
18060 | complicated; see mips16_extended_frag. */ | |
18061 | if (type == 'p' || type == 'q') | |
18062 | { | |
18063 | addr += 2; | |
18064 | if (ext) | |
18065 | addr += 2; | |
18066 | /* Ignore the low bit in the target, since it will be | |
18067 | set for a text label. */ | |
18068 | if ((val & 1) != 0) | |
18069 | --val; | |
18070 | } | |
18071 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
18072 | addr -= 4; | |
18073 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18074 | addr -= 2; | |
18075 | ||
18076 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
18077 | val -= addr; | |
18078 | ||
18079 | /* Make sure the section winds up with the alignment we have | |
18080 | assumed. */ | |
18081 | if (op->shift > 0) | |
18082 | record_alignment (asec, op->shift); | |
18083 | } | |
18084 | ||
18085 | if (ext | |
18086 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
18087 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
18088 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18089 | _("extended instruction in delay slot")); | |
18090 | ||
18091 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
18092 | ||
18093 | if (target_big_endian) | |
18094 | insn = bfd_getb16 (buf); | |
18095 | else | |
18096 | insn = bfd_getl16 (buf); | |
18097 | ||
18098 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
18099 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
18100 | small, ext, &insn, &use_extend, &extend); | |
18101 | ||
18102 | if (use_extend) | |
18103 | { | |
2132e3a3 | 18104 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
18105 | fragp->fr_fix += 2; |
18106 | buf += 2; | |
18107 | } | |
18108 | ||
2132e3a3 | 18109 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
18110 | fragp->fr_fix += 2; |
18111 | buf += 2; | |
18112 | } | |
18113 | else | |
18114 | { | |
df58fc94 RS |
18115 | relax_substateT subtype = fragp->fr_subtype; |
18116 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18117 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18118 | int first, second; |
18119 | fixS *fixp; | |
252b5132 | 18120 | |
df58fc94 RS |
18121 | first = RELAX_FIRST (subtype); |
18122 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18123 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18124 | |
df58fc94 RS |
18125 | /* If the delay slot chosen does not match the size of the instruction, |
18126 | then emit a warning. */ | |
18127 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18128 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18129 | { | |
18130 | relax_substateT s; | |
18131 | const char *msg; | |
18132 | ||
18133 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18134 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18135 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18136 | msg = macro_warning (s); | |
18137 | if (msg != NULL) | |
18138 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
18139 | subtype &= ~s; | |
18140 | } | |
18141 | ||
584892a6 | 18142 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18143 | if (use_second == second_longer) |
584892a6 | 18144 | { |
df58fc94 RS |
18145 | relax_substateT s; |
18146 | const char *msg; | |
18147 | ||
18148 | s = (subtype | |
18149 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18150 | msg = macro_warning (s); | |
18151 | if (msg != NULL) | |
18152 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
18153 | subtype &= ~s; | |
584892a6 RS |
18154 | } |
18155 | ||
4d7206a2 RS |
18156 | /* Go through all the fixups for the first sequence. Disable them |
18157 | (by marking them as done) if we're going to use the second | |
18158 | sequence instead. */ | |
18159 | while (fixp | |
18160 | && fixp->fx_frag == fragp | |
18161 | && fixp->fx_where < fragp->fr_fix - second) | |
18162 | { | |
df58fc94 | 18163 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18164 | fixp->fx_done = 1; |
18165 | fixp = fixp->fx_next; | |
18166 | } | |
252b5132 | 18167 | |
4d7206a2 RS |
18168 | /* Go through the fixups for the second sequence. Disable them if |
18169 | we're going to use the first sequence, otherwise adjust their | |
18170 | addresses to account for the relaxation. */ | |
18171 | while (fixp && fixp->fx_frag == fragp) | |
18172 | { | |
df58fc94 | 18173 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18174 | fixp->fx_where -= first; |
18175 | else | |
18176 | fixp->fx_done = 1; | |
18177 | fixp = fixp->fx_next; | |
18178 | } | |
18179 | ||
18180 | /* Now modify the frag contents. */ | |
df58fc94 | 18181 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18182 | { |
18183 | char *start; | |
18184 | ||
18185 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18186 | memmove (start, start + first, second); | |
18187 | fragp->fr_fix -= first; | |
18188 | } | |
18189 | else | |
18190 | fragp->fr_fix -= second; | |
252b5132 RH |
18191 | } |
18192 | } | |
18193 | ||
18194 | #ifdef OBJ_ELF | |
18195 | ||
18196 | /* This function is called after the relocs have been generated. | |
18197 | We've been storing mips16 text labels as odd. Here we convert them | |
18198 | back to even for the convenience of the debugger. */ | |
18199 | ||
18200 | void | |
17a2f251 | 18201 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18202 | { |
18203 | asymbol **syms; | |
18204 | unsigned int count, i; | |
18205 | ||
f43abd2b | 18206 | if (!IS_ELF) |
252b5132 RH |
18207 | return; |
18208 | ||
18209 | syms = bfd_get_outsymbols (stdoutput); | |
18210 | count = bfd_get_symcount (stdoutput); | |
18211 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18212 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18213 | && ((*syms)->value & 1) != 0) | |
18214 | { | |
18215 | (*syms)->value &= ~1; | |
18216 | /* If the symbol has an odd size, it was probably computed | |
18217 | incorrectly, so adjust that as well. */ | |
18218 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18219 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18220 | } | |
252b5132 RH |
18221 | } |
18222 | ||
18223 | #endif | |
18224 | ||
a1facbec MR |
18225 | /* This function is called whenever a label is defined, including fake |
18226 | labels instantiated off the dot special symbol. It is used when | |
18227 | handling branch delays; if a branch has a label, we assume we cannot | |
18228 | move it. This also bumps the value of the symbol by 1 in compressed | |
18229 | code. */ | |
252b5132 RH |
18230 | |
18231 | void | |
a1facbec | 18232 | mips_record_label (symbolS *sym) |
252b5132 | 18233 | { |
a8dbcb85 | 18234 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18235 | struct insn_label_list *l; |
18236 | ||
18237 | if (free_insn_labels == NULL) | |
18238 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
18239 | else | |
18240 | { | |
18241 | l = free_insn_labels; | |
18242 | free_insn_labels = l->next; | |
18243 | } | |
18244 | ||
18245 | l->label = sym; | |
a8dbcb85 TS |
18246 | l->next = si->label_list; |
18247 | si->label_list = l; | |
a1facbec | 18248 | } |
07a53e5c | 18249 | |
a1facbec MR |
18250 | /* This function is called as tc_frob_label() whenever a label is defined |
18251 | and adds a DWARF-2 record we only want for true labels. */ | |
18252 | ||
18253 | void | |
18254 | mips_define_label (symbolS *sym) | |
18255 | { | |
18256 | mips_record_label (sym); | |
07a53e5c RH |
18257 | #ifdef OBJ_ELF |
18258 | dwarf2_emit_label (sym); | |
18259 | #endif | |
252b5132 RH |
18260 | } |
18261 | \f | |
18262 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
18263 | ||
18264 | /* Some special processing for a MIPS ELF file. */ | |
18265 | ||
18266 | void | |
17a2f251 | 18267 | mips_elf_final_processing (void) |
252b5132 RH |
18268 | { |
18269 | /* Write out the register information. */ | |
316f5878 | 18270 | if (mips_abi != N64_ABI) |
252b5132 RH |
18271 | { |
18272 | Elf32_RegInfo s; | |
18273 | ||
18274 | s.ri_gprmask = mips_gprmask; | |
18275 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18276 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18277 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18278 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18279 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18280 | ||
18281 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
18282 | ((Elf32_External_RegInfo *) | |
18283 | mips_regmask_frag)); | |
18284 | } | |
18285 | else | |
18286 | { | |
18287 | Elf64_Internal_RegInfo s; | |
18288 | ||
18289 | s.ri_gprmask = mips_gprmask; | |
18290 | s.ri_pad = 0; | |
18291 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18292 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18293 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18294 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18295 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18296 | ||
18297 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
18298 | ((Elf64_External_RegInfo *) | |
18299 | mips_regmask_frag)); | |
18300 | } | |
18301 | ||
18302 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
18303 | sort of BFD interface for this. */ | |
18304 | if (mips_any_noreorder) | |
18305 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
18306 | if (mips_pic != NO_PIC) | |
143d77c5 | 18307 | { |
252b5132 | 18308 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
18309 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
18310 | } | |
18311 | if (mips_abicalls) | |
18312 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 18313 | |
98d3f06f | 18314 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
18315 | /* We may need to define a new flag for DSP ASE, and set this flag when |
18316 | file_ase_dsp is true. */ | |
8b082fb1 | 18317 | /* Same for DSP R2. */ |
ef2e4d86 CF |
18318 | /* We may need to define a new flag for MT ASE, and set this flag when |
18319 | file_ase_mt is true. */ | |
a4672219 TS |
18320 | if (file_ase_mips16) |
18321 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
18322 | if (file_ase_micromips) |
18323 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
1f25f5d3 CD |
18324 | #if 0 /* XXX FIXME */ |
18325 | if (file_ase_mips3d) | |
18326 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18327 | #endif | |
deec1734 CD |
18328 | if (file_ase_mdmx) |
18329 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 18330 | |
bdaaa2e1 | 18331 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 18332 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 18333 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 18334 | else if (mips_abi == O64_ABI) |
252b5132 | 18335 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 18336 | else if (mips_abi == EABI_ABI) |
252b5132 | 18337 | { |
316f5878 | 18338 | if (!file_mips_gp32) |
252b5132 RH |
18339 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
18340 | else | |
18341 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
18342 | } | |
316f5878 | 18343 | else if (mips_abi == N32_ABI) |
be00bddd TS |
18344 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
18345 | ||
c9914766 | 18346 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
18347 | |
18348 | if (mips_32bitmode) | |
18349 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
18350 | |
18351 | #if 0 /* XXX FIXME */ | |
18352 | /* 32 bit code with 64 bit FP registers. */ | |
18353 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
18354 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18355 | #endif | |
252b5132 RH |
18356 | } |
18357 | ||
18358 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
18359 | \f | |
beae10d5 | 18360 | typedef struct proc { |
9b2f1d35 EC |
18361 | symbolS *func_sym; |
18362 | symbolS *func_end_sym; | |
beae10d5 KH |
18363 | unsigned long reg_mask; |
18364 | unsigned long reg_offset; | |
18365 | unsigned long fpreg_mask; | |
18366 | unsigned long fpreg_offset; | |
18367 | unsigned long frame_offset; | |
18368 | unsigned long frame_reg; | |
18369 | unsigned long pc_reg; | |
18370 | } procS; | |
252b5132 RH |
18371 | |
18372 | static procS cur_proc; | |
18373 | static procS *cur_proc_ptr; | |
18374 | static int numprocs; | |
18375 | ||
df58fc94 RS |
18376 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
18377 | as "2", and a normal nop as "0". */ | |
18378 | ||
18379 | #define NOP_OPCODE_MIPS 0 | |
18380 | #define NOP_OPCODE_MIPS16 1 | |
18381 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
18382 | |
18383 | char | |
18384 | mips_nop_opcode (void) | |
18385 | { | |
df58fc94 RS |
18386 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
18387 | return NOP_OPCODE_MICROMIPS; | |
18388 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
18389 | return NOP_OPCODE_MIPS16; | |
18390 | else | |
18391 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
18392 | } |
18393 | ||
df58fc94 RS |
18394 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
18395 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 18396 | |
0a9ef439 | 18397 | void |
17a2f251 | 18398 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 18399 | { |
df58fc94 | 18400 | char nop_opcode; |
742a56fe | 18401 | char *p; |
c67a084a NC |
18402 | int bytes, size, excess; |
18403 | valueT opcode; | |
742a56fe | 18404 | |
0a9ef439 RH |
18405 | if (fragp->fr_type != rs_align_code) |
18406 | return; | |
18407 | ||
742a56fe | 18408 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18409 | nop_opcode = *p; |
18410 | switch (nop_opcode) | |
a19d8eb0 | 18411 | { |
df58fc94 RS |
18412 | case NOP_OPCODE_MICROMIPS: |
18413 | opcode = micromips_nop32_insn.insn_opcode; | |
18414 | size = 4; | |
18415 | break; | |
18416 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
18417 | opcode = mips16_nop_insn.insn_opcode; |
18418 | size = 2; | |
df58fc94 RS |
18419 | break; |
18420 | case NOP_OPCODE_MIPS: | |
18421 | default: | |
c67a084a NC |
18422 | opcode = nop_insn.insn_opcode; |
18423 | size = 4; | |
df58fc94 | 18424 | break; |
c67a084a | 18425 | } |
a19d8eb0 | 18426 | |
c67a084a NC |
18427 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
18428 | excess = bytes % size; | |
df58fc94 RS |
18429 | |
18430 | /* Handle the leading part if we're not inserting a whole number of | |
18431 | instructions, and make it the end of the fixed part of the frag. | |
18432 | Try to fit in a short microMIPS NOP if applicable and possible, | |
18433 | and use zeroes otherwise. */ | |
18434 | gas_assert (excess < 4); | |
18435 | fragp->fr_fix += excess; | |
18436 | switch (excess) | |
c67a084a | 18437 | { |
df58fc94 RS |
18438 | case 3: |
18439 | *p++ = '\0'; | |
18440 | /* Fall through. */ | |
18441 | case 2: | |
18442 | if (nop_opcode == NOP_OPCODE_MICROMIPS) | |
18443 | { | |
18444 | md_number_to_chars (p, micromips_nop16_insn.insn_opcode, 2); | |
18445 | p += 2; | |
18446 | break; | |
18447 | } | |
18448 | *p++ = '\0'; | |
18449 | /* Fall through. */ | |
18450 | case 1: | |
18451 | *p++ = '\0'; | |
18452 | /* Fall through. */ | |
18453 | case 0: | |
18454 | break; | |
a19d8eb0 | 18455 | } |
c67a084a NC |
18456 | |
18457 | md_number_to_chars (p, opcode, size); | |
18458 | fragp->fr_var = size; | |
a19d8eb0 CP |
18459 | } |
18460 | ||
252b5132 | 18461 | static void |
17a2f251 | 18462 | md_obj_begin (void) |
252b5132 RH |
18463 | { |
18464 | } | |
18465 | ||
18466 | static void | |
17a2f251 | 18467 | md_obj_end (void) |
252b5132 | 18468 | { |
54f4ddb3 | 18469 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 18470 | if (cur_proc_ptr) |
9a41af64 | 18471 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
18472 | } |
18473 | ||
18474 | static long | |
17a2f251 | 18475 | get_number (void) |
252b5132 RH |
18476 | { |
18477 | int negative = 0; | |
18478 | long val = 0; | |
18479 | ||
18480 | if (*input_line_pointer == '-') | |
18481 | { | |
18482 | ++input_line_pointer; | |
18483 | negative = 1; | |
18484 | } | |
3882b010 | 18485 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 18486 | as_bad (_("expected simple number")); |
252b5132 RH |
18487 | if (input_line_pointer[0] == '0') |
18488 | { | |
18489 | if (input_line_pointer[1] == 'x') | |
18490 | { | |
18491 | input_line_pointer += 2; | |
3882b010 | 18492 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
18493 | { |
18494 | val <<= 4; | |
18495 | val |= hex_value (*input_line_pointer++); | |
18496 | } | |
18497 | return negative ? -val : val; | |
18498 | } | |
18499 | else | |
18500 | { | |
18501 | ++input_line_pointer; | |
3882b010 | 18502 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18503 | { |
18504 | val <<= 3; | |
18505 | val |= *input_line_pointer++ - '0'; | |
18506 | } | |
18507 | return negative ? -val : val; | |
18508 | } | |
18509 | } | |
3882b010 | 18510 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18511 | { |
18512 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
18513 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 18514 | as_warn (_("invalid number")); |
252b5132 RH |
18515 | return -1; |
18516 | } | |
3882b010 | 18517 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18518 | { |
18519 | val *= 10; | |
18520 | val += *input_line_pointer++ - '0'; | |
18521 | } | |
18522 | return negative ? -val : val; | |
18523 | } | |
18524 | ||
18525 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
18526 | is an initial number which is the ECOFF file index. In the non-ECOFF |
18527 | case .file implies DWARF-2. */ | |
18528 | ||
18529 | static void | |
17a2f251 | 18530 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 18531 | { |
ecb4347a DJ |
18532 | static int first_file_directive = 0; |
18533 | ||
c5dd6aab DJ |
18534 | if (ECOFF_DEBUGGING) |
18535 | { | |
18536 | get_number (); | |
18537 | s_app_file (0); | |
18538 | } | |
18539 | else | |
ecb4347a DJ |
18540 | { |
18541 | char *filename; | |
18542 | ||
18543 | filename = dwarf2_directive_file (0); | |
18544 | ||
18545 | /* Versions of GCC up to 3.1 start files with a ".file" | |
18546 | directive even for stabs output. Make sure that this | |
18547 | ".file" is handled. Note that you need a version of GCC | |
18548 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
18549 | if (filename != NULL && ! first_file_directive) | |
18550 | { | |
18551 | (void) new_logical_line (filename, -1); | |
c04f5787 | 18552 | s_app_file_string (filename, 0); |
ecb4347a DJ |
18553 | } |
18554 | first_file_directive = 1; | |
18555 | } | |
c5dd6aab DJ |
18556 | } |
18557 | ||
18558 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
18559 | |
18560 | static void | |
17a2f251 | 18561 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 18562 | { |
c5dd6aab DJ |
18563 | if (!ECOFF_DEBUGGING) |
18564 | dwarf2_directive_loc (0); | |
252b5132 RH |
18565 | } |
18566 | ||
252b5132 RH |
18567 | /* The .end directive. */ |
18568 | ||
18569 | static void | |
17a2f251 | 18570 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
18571 | { |
18572 | symbolS *p; | |
252b5132 | 18573 | |
7a621144 DJ |
18574 | /* Following functions need their own .frame and .cprestore directives. */ |
18575 | mips_frame_reg_valid = 0; | |
18576 | mips_cprestore_valid = 0; | |
18577 | ||
252b5132 RH |
18578 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
18579 | { | |
18580 | p = get_symbol (); | |
18581 | demand_empty_rest_of_line (); | |
18582 | } | |
18583 | else | |
18584 | p = NULL; | |
18585 | ||
14949570 | 18586 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
18587 | as_warn (_(".end not in text section")); |
18588 | ||
18589 | if (!cur_proc_ptr) | |
18590 | { | |
18591 | as_warn (_(".end directive without a preceding .ent directive.")); | |
18592 | demand_empty_rest_of_line (); | |
18593 | return; | |
18594 | } | |
18595 | ||
18596 | if (p != NULL) | |
18597 | { | |
9c2799c2 | 18598 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 18599 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 18600 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
18601 | |
18602 | if (debug_type == DEBUG_STABS) | |
18603 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
18604 | S_GET_NAME (p)); | |
252b5132 RH |
18605 | } |
18606 | else | |
18607 | as_warn (_(".end directive missing or unknown symbol")); | |
18608 | ||
2132e3a3 | 18609 | #ifdef OBJ_ELF |
9b2f1d35 EC |
18610 | /* Create an expression to calculate the size of the function. */ |
18611 | if (p && cur_proc_ptr) | |
18612 | { | |
18613 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
18614 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
18615 | ||
18616 | obj->size = exp; | |
18617 | exp->X_op = O_subtract; | |
18618 | exp->X_add_symbol = symbol_temp_new_now (); | |
18619 | exp->X_op_symbol = p; | |
18620 | exp->X_add_number = 0; | |
18621 | ||
18622 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
18623 | } | |
18624 | ||
ecb4347a | 18625 | /* Generate a .pdr section. */ |
f43abd2b | 18626 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
18627 | { |
18628 | segT saved_seg = now_seg; | |
18629 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
18630 | expressionS exp; |
18631 | char *fragp; | |
252b5132 | 18632 | |
252b5132 | 18633 | #ifdef md_flush_pending_output |
ecb4347a | 18634 | md_flush_pending_output (); |
252b5132 RH |
18635 | #endif |
18636 | ||
9c2799c2 | 18637 | gas_assert (pdr_seg); |
ecb4347a | 18638 | subseg_set (pdr_seg, 0); |
252b5132 | 18639 | |
ecb4347a DJ |
18640 | /* Write the symbol. */ |
18641 | exp.X_op = O_symbol; | |
18642 | exp.X_add_symbol = p; | |
18643 | exp.X_add_number = 0; | |
18644 | emit_expr (&exp, 4); | |
252b5132 | 18645 | |
ecb4347a | 18646 | fragp = frag_more (7 * 4); |
252b5132 | 18647 | |
17a2f251 TS |
18648 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
18649 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
18650 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
18651 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
18652 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
18653 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
18654 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 18655 | |
ecb4347a DJ |
18656 | subseg_set (saved_seg, saved_subseg); |
18657 | } | |
18658 | #endif /* OBJ_ELF */ | |
252b5132 RH |
18659 | |
18660 | cur_proc_ptr = NULL; | |
18661 | } | |
18662 | ||
18663 | /* The .aent and .ent directives. */ | |
18664 | ||
18665 | static void | |
17a2f251 | 18666 | s_mips_ent (int aent) |
252b5132 | 18667 | { |
252b5132 | 18668 | symbolS *symbolP; |
252b5132 RH |
18669 | |
18670 | symbolP = get_symbol (); | |
18671 | if (*input_line_pointer == ',') | |
f9419b05 | 18672 | ++input_line_pointer; |
252b5132 | 18673 | SKIP_WHITESPACE (); |
3882b010 | 18674 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 18675 | || *input_line_pointer == '-') |
874e8986 | 18676 | get_number (); |
252b5132 | 18677 | |
14949570 | 18678 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
18679 | as_warn (_(".ent or .aent not in text section.")); |
18680 | ||
18681 | if (!aent && cur_proc_ptr) | |
9a41af64 | 18682 | as_warn (_("missing .end")); |
252b5132 RH |
18683 | |
18684 | if (!aent) | |
18685 | { | |
7a621144 DJ |
18686 | /* This function needs its own .frame and .cprestore directives. */ |
18687 | mips_frame_reg_valid = 0; | |
18688 | mips_cprestore_valid = 0; | |
18689 | ||
252b5132 RH |
18690 | cur_proc_ptr = &cur_proc; |
18691 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
18692 | ||
9b2f1d35 | 18693 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 18694 | |
f9419b05 | 18695 | ++numprocs; |
ecb4347a DJ |
18696 | |
18697 | if (debug_type == DEBUG_STABS) | |
18698 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
18699 | S_GET_NAME (symbolP)); | |
252b5132 RH |
18700 | } |
18701 | ||
7c0fc524 MR |
18702 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
18703 | ||
252b5132 RH |
18704 | demand_empty_rest_of_line (); |
18705 | } | |
18706 | ||
18707 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 18708 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 18709 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 18710 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
18711 | symbol table (in the mdebug section). */ |
18712 | ||
18713 | static void | |
17a2f251 | 18714 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 18715 | { |
ecb4347a | 18716 | #ifdef OBJ_ELF |
f43abd2b | 18717 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
18718 | { |
18719 | long val; | |
252b5132 | 18720 | |
ecb4347a DJ |
18721 | if (cur_proc_ptr == (procS *) NULL) |
18722 | { | |
18723 | as_warn (_(".frame outside of .ent")); | |
18724 | demand_empty_rest_of_line (); | |
18725 | return; | |
18726 | } | |
252b5132 | 18727 | |
ecb4347a DJ |
18728 | cur_proc_ptr->frame_reg = tc_get_register (1); |
18729 | ||
18730 | SKIP_WHITESPACE (); | |
18731 | if (*input_line_pointer++ != ',' | |
18732 | || get_absolute_expression_and_terminator (&val) != ',') | |
18733 | { | |
18734 | as_warn (_("Bad .frame directive")); | |
18735 | --input_line_pointer; | |
18736 | demand_empty_rest_of_line (); | |
18737 | return; | |
18738 | } | |
252b5132 | 18739 | |
ecb4347a DJ |
18740 | cur_proc_ptr->frame_offset = val; |
18741 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 18742 | |
252b5132 | 18743 | demand_empty_rest_of_line (); |
252b5132 | 18744 | } |
ecb4347a DJ |
18745 | else |
18746 | #endif /* OBJ_ELF */ | |
18747 | s_ignore (ignore); | |
252b5132 RH |
18748 | } |
18749 | ||
bdaaa2e1 KH |
18750 | /* The .fmask and .mask directives. If the mdebug section is present |
18751 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 18752 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 18753 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
18754 | make reference to the ecoff symbol table (in the mdebug section). */ |
18755 | ||
18756 | static void | |
17a2f251 | 18757 | s_mips_mask (int reg_type) |
252b5132 | 18758 | { |
ecb4347a | 18759 | #ifdef OBJ_ELF |
f43abd2b | 18760 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 18761 | { |
ecb4347a | 18762 | long mask, off; |
252b5132 | 18763 | |
ecb4347a DJ |
18764 | if (cur_proc_ptr == (procS *) NULL) |
18765 | { | |
18766 | as_warn (_(".mask/.fmask outside of .ent")); | |
18767 | demand_empty_rest_of_line (); | |
18768 | return; | |
18769 | } | |
252b5132 | 18770 | |
ecb4347a DJ |
18771 | if (get_absolute_expression_and_terminator (&mask) != ',') |
18772 | { | |
18773 | as_warn (_("Bad .mask/.fmask directive")); | |
18774 | --input_line_pointer; | |
18775 | demand_empty_rest_of_line (); | |
18776 | return; | |
18777 | } | |
252b5132 | 18778 | |
ecb4347a DJ |
18779 | off = get_absolute_expression (); |
18780 | ||
18781 | if (reg_type == 'F') | |
18782 | { | |
18783 | cur_proc_ptr->fpreg_mask = mask; | |
18784 | cur_proc_ptr->fpreg_offset = off; | |
18785 | } | |
18786 | else | |
18787 | { | |
18788 | cur_proc_ptr->reg_mask = mask; | |
18789 | cur_proc_ptr->reg_offset = off; | |
18790 | } | |
18791 | ||
18792 | demand_empty_rest_of_line (); | |
252b5132 RH |
18793 | } |
18794 | else | |
ecb4347a DJ |
18795 | #endif /* OBJ_ELF */ |
18796 | s_ignore (reg_type); | |
252b5132 RH |
18797 | } |
18798 | ||
316f5878 RS |
18799 | /* A table describing all the processors gas knows about. Names are |
18800 | matched in the order listed. | |
e7af610e | 18801 | |
316f5878 RS |
18802 | To ease comparison, please keep this table in the same order as |
18803 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
18804 | static const struct mips_cpu_info mips_cpu_info_table[] = |
18805 | { | |
316f5878 | 18806 | /* Entries for generic ISAs */ |
ad3fea08 TS |
18807 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
18808 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
18809 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
18810 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
18811 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
18812 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
18813 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18814 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
18815 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
18816 | |
18817 | /* MIPS I */ | |
ad3fea08 TS |
18818 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
18819 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
18820 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
18821 | |
18822 | /* MIPS II */ | |
ad3fea08 | 18823 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
18824 | |
18825 | /* MIPS III */ | |
ad3fea08 TS |
18826 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
18827 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
18828 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
18829 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
18830 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
18831 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
18832 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
18833 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
18834 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
18835 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
18836 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
18837 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
b15591bb AN |
18838 | /* ST Microelectronics Loongson 2E and 2F cores */ |
18839 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
18840 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
18841 | |
18842 | /* MIPS IV */ | |
ad3fea08 TS |
18843 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
18844 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
18845 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
3aa3176b TS |
18846 | { "r14000", 0, ISA_MIPS4, CPU_R14000 }, |
18847 | { "r16000", 0, ISA_MIPS4, CPU_R16000 }, | |
ad3fea08 TS |
18848 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
18849 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
18850 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
18851 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
18852 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
18853 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
18854 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
18855 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
18856 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
18857 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
18858 | |
18859 | /* MIPS 32 */ | |
ad3fea08 TS |
18860 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
18861 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
18862 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
18863 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
18864 | ||
18865 | /* MIPS 32 Release 2 */ | |
18866 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18867 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18868 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18869 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18870 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18871 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 18872 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 18873 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 18874 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
18875 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
18876 | /* Deprecated forms of the above. */ | |
18877 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 18878 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 18879 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 18880 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 18881 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 18882 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
18883 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
18884 | /* Deprecated forms of the above. */ | |
18885 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 18886 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 18887 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
18888 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
18889 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
18890 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
18891 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
18892 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
18893 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
18894 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
18895 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18896 | /* Deprecated forms of the above. */ | |
18897 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
18898 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
18899 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
18900 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
18901 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
18902 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
18903 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
18904 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
18905 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
18906 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
18907 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
18908 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
18909 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18910 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
18911 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18912 | /* Deprecated forms of the above. */ | |
18913 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
18914 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
18915 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
18916 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a SL |
18917 | /* 1004K cores are multiprocessor versions of the 34K. */ |
18918 | { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
18919 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18920 | { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
18921 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18922 | { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
18923 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18924 | { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
18925 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 18926 | |
316f5878 | 18927 | /* MIPS 64 */ |
ad3fea08 TS |
18928 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
18929 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
18930 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 18931 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 | 18932 | |
c7a23324 | 18933 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
18934 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
18935 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
18936 | /* Broadcom SB-1A CPU core */ |
18937 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
18938 | ISA_MIPS64, CPU_SB1 }, | |
d051516a NC |
18939 | |
18940 | { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A }, | |
e7af610e | 18941 | |
ed163775 MR |
18942 | /* MIPS 64 Release 2 */ |
18943 | ||
967344c6 AN |
18944 | /* Cavium Networks Octeon CPU core */ |
18945 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
18946 | ||
52b6b6b9 JM |
18947 | /* RMI Xlr */ |
18948 | { "xlr", 0, ISA_MIPS64, CPU_XLR }, | |
18949 | ||
316f5878 RS |
18950 | /* End marker */ |
18951 | { NULL, 0, 0, 0 } | |
18952 | }; | |
e7af610e | 18953 | |
84ea6cf2 | 18954 | |
316f5878 RS |
18955 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
18956 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 18957 | |
316f5878 | 18958 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 18959 | |
b34976b6 | 18960 | static bfd_boolean |
17a2f251 | 18961 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
18962 | { |
18963 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
18964 | given++, canonical++; | |
18965 | ||
18966 | return ((*given == 0 && *canonical == 0) | |
18967 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
18968 | } | |
18969 | ||
18970 | ||
18971 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
18972 | CPU name. We've traditionally allowed a lot of variation here. | |
18973 | ||
18974 | Note: this function is shared between GCC and GAS. */ | |
18975 | ||
b34976b6 | 18976 | static bfd_boolean |
17a2f251 | 18977 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
18978 | { |
18979 | /* First see if the name matches exactly, or with a final "000" | |
18980 | turned into "k". */ | |
18981 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 18982 | return TRUE; |
316f5878 RS |
18983 | |
18984 | /* If not, try comparing based on numerical designation alone. | |
18985 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
18986 | if (TOLOWER (*given) == 'r') | |
18987 | given++; | |
18988 | if (!ISDIGIT (*given)) | |
b34976b6 | 18989 | return FALSE; |
316f5878 RS |
18990 | |
18991 | /* Skip over some well-known prefixes in the canonical name, | |
18992 | hoping to find a number there too. */ | |
18993 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
18994 | canonical += 2; | |
18995 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
18996 | canonical += 2; | |
18997 | else if (TOLOWER (canonical[0]) == 'r') | |
18998 | canonical += 1; | |
18999 | ||
19000 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19001 | } | |
19002 | ||
19003 | ||
19004 | /* Parse an option that takes the name of a processor as its argument. | |
19005 | OPTION is the name of the option and CPU_STRING is the argument. | |
19006 | Return the corresponding processor enumeration if the CPU_STRING is | |
19007 | recognized, otherwise report an error and return null. | |
19008 | ||
19009 | A similar function exists in GCC. */ | |
e7af610e NC |
19010 | |
19011 | static const struct mips_cpu_info * | |
17a2f251 | 19012 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19013 | { |
316f5878 | 19014 | const struct mips_cpu_info *p; |
e7af610e | 19015 | |
316f5878 RS |
19016 | /* 'from-abi' selects the most compatible architecture for the given |
19017 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19018 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19019 | version. Look first at the -mgp options, if given, otherwise base | |
19020 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19021 | |
316f5878 RS |
19022 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19023 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19024 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19025 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19026 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19027 | { | |
19028 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19029 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19030 | ||
19031 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19032 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19033 | ||
19034 | if (file_mips_gp32 >= 0) | |
19035 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
19036 | ||
19037 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19038 | ? ISA_MIPS3 | |
19039 | : ISA_MIPS1); | |
19040 | } | |
19041 | ||
19042 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19043 | if (strcasecmp (cpu_string, "default") == 0) | |
19044 | return 0; | |
19045 | ||
19046 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19047 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19048 | return p; | |
19049 | ||
20203fb9 | 19050 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19051 | return 0; |
e7af610e NC |
19052 | } |
19053 | ||
316f5878 RS |
19054 | /* Return the canonical processor information for ISA (a member of the |
19055 | ISA_MIPS* enumeration). */ | |
19056 | ||
e7af610e | 19057 | static const struct mips_cpu_info * |
17a2f251 | 19058 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19059 | { |
19060 | int i; | |
19061 | ||
19062 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19063 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19064 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19065 | return (&mips_cpu_info_table[i]); |
19066 | ||
e972090a | 19067 | return NULL; |
e7af610e | 19068 | } |
fef14a42 TS |
19069 | |
19070 | static const struct mips_cpu_info * | |
17a2f251 | 19071 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19072 | { |
19073 | int i; | |
19074 | ||
19075 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19076 | if (arch == mips_cpu_info_table[i].cpu) | |
19077 | return (&mips_cpu_info_table[i]); | |
19078 | ||
19079 | return NULL; | |
19080 | } | |
316f5878 RS |
19081 | \f |
19082 | static void | |
17a2f251 | 19083 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19084 | { |
19085 | if (*first_p) | |
19086 | { | |
19087 | fprintf (stream, "%24s", ""); | |
19088 | *col_p = 24; | |
19089 | } | |
19090 | else | |
19091 | { | |
19092 | fprintf (stream, ", "); | |
19093 | *col_p += 2; | |
19094 | } | |
e7af610e | 19095 | |
316f5878 RS |
19096 | if (*col_p + strlen (string) > 72) |
19097 | { | |
19098 | fprintf (stream, "\n%24s", ""); | |
19099 | *col_p = 24; | |
19100 | } | |
19101 | ||
19102 | fprintf (stream, "%s", string); | |
19103 | *col_p += strlen (string); | |
19104 | ||
19105 | *first_p = 0; | |
19106 | } | |
19107 | ||
19108 | void | |
17a2f251 | 19109 | md_show_usage (FILE *stream) |
e7af610e | 19110 | { |
316f5878 RS |
19111 | int column, first; |
19112 | size_t i; | |
19113 | ||
19114 | fprintf (stream, _("\ | |
19115 | MIPS options:\n\ | |
316f5878 RS |
19116 | -EB generate big endian output\n\ |
19117 | -EL generate little endian output\n\ | |
19118 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19119 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19120 | implicitly with the gp register [default 8]\n")); | |
19121 | fprintf (stream, _("\ | |
19122 | -mips1 generate MIPS ISA I instructions\n\ | |
19123 | -mips2 generate MIPS ISA II instructions\n\ | |
19124 | -mips3 generate MIPS ISA III instructions\n\ | |
19125 | -mips4 generate MIPS ISA IV instructions\n\ | |
19126 | -mips5 generate MIPS ISA V instructions\n\ | |
19127 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19128 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 19129 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19130 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
19131 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19132 | ||
19133 | first = 1; | |
e7af610e NC |
19134 | |
19135 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
19136 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
19137 | show (stream, "from-abi", &column, &first); | |
19138 | fputc ('\n', stream); | |
e7af610e | 19139 | |
316f5878 RS |
19140 | fprintf (stream, _("\ |
19141 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
19142 | -no-mCPU don't generate code specific to CPU.\n\ | |
19143 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
19144 | ||
19145 | first = 1; | |
19146 | ||
19147 | show (stream, "3900", &column, &first); | |
19148 | show (stream, "4010", &column, &first); | |
19149 | show (stream, "4100", &column, &first); | |
19150 | show (stream, "4650", &column, &first); | |
19151 | fputc ('\n', stream); | |
19152 | ||
19153 | fprintf (stream, _("\ | |
19154 | -mips16 generate mips16 instructions\n\ | |
19155 | -no-mips16 do not generate mips16 instructions\n")); | |
19156 | fprintf (stream, _("\ | |
df58fc94 RS |
19157 | -mmicromips generate microMIPS instructions\n\ |
19158 | -mno-micromips do not generate microMIPS instructions\n")); | |
19159 | fprintf (stream, _("\ | |
e16bfa71 TS |
19160 | -msmartmips generate smartmips instructions\n\ |
19161 | -mno-smartmips do not generate smartmips instructions\n")); | |
19162 | fprintf (stream, _("\ | |
74cd071d CF |
19163 | -mdsp generate DSP instructions\n\ |
19164 | -mno-dsp do not generate DSP instructions\n")); | |
19165 | fprintf (stream, _("\ | |
8b082fb1 TS |
19166 | -mdspr2 generate DSP R2 instructions\n\ |
19167 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
19168 | fprintf (stream, _("\ | |
ef2e4d86 CF |
19169 | -mmt generate MT instructions\n\ |
19170 | -mno-mt do not generate MT instructions\n")); | |
19171 | fprintf (stream, _("\ | |
c67a084a NC |
19172 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
19173 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 19174 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 19175 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 19176 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 19177 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
19178 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
19179 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 19180 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
19181 | -O0 remove unneeded NOPs, do not swap branches\n\ |
19182 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
19183 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
19184 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
19185 | fprintf (stream, _("\ |
19186 | -mhard-float allow floating-point instructions\n\ | |
19187 | -msoft-float do not allow floating-point instructions\n\ | |
19188 | -msingle-float only allow 32-bit floating-point operations\n\ | |
19189 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
19190 | --[no-]construct-floats [dis]allow floating point values to be constructed\n" | |
19191 | )); | |
316f5878 RS |
19192 | #ifdef OBJ_ELF |
19193 | fprintf (stream, _("\ | |
19194 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 19195 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 19196 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 19197 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 19198 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 19199 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 19200 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 19201 | position dependent (non shared) code\n\ |
316f5878 RS |
19202 | -mabi=ABI create ABI conformant object file for:\n")); |
19203 | ||
19204 | first = 1; | |
19205 | ||
19206 | show (stream, "32", &column, &first); | |
19207 | show (stream, "o64", &column, &first); | |
19208 | show (stream, "n32", &column, &first); | |
19209 | show (stream, "64", &column, &first); | |
19210 | show (stream, "eabi", &column, &first); | |
19211 | ||
19212 | fputc ('\n', stream); | |
19213 | ||
19214 | fprintf (stream, _("\ | |
19215 | -32 create o32 ABI object file (default)\n\ | |
19216 | -n32 create n32 ABI object file\n\ | |
19217 | -64 create 64 ABI object file\n")); | |
19218 | #endif | |
e7af610e | 19219 | } |
14e777e0 | 19220 | |
1575952e | 19221 | #ifdef TE_IRIX |
14e777e0 | 19222 | enum dwarf2_format |
413a266c | 19223 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 19224 | { |
369943fe | 19225 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 19226 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
19227 | else |
19228 | return dwarf2_format_32bit; | |
19229 | } | |
1575952e | 19230 | #endif |
73369e65 EC |
19231 | |
19232 | int | |
19233 | mips_dwarf2_addr_size (void) | |
19234 | { | |
6b6b3450 | 19235 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 19236 | return 8; |
73369e65 EC |
19237 | else |
19238 | return 4; | |
19239 | } | |
5862107c EC |
19240 | |
19241 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
19242 | void | |
19243 | mips_cfi_frame_initial_instructions (void) | |
19244 | { | |
19245 | cfi_add_CFA_def_cfa_register (SP); | |
19246 | } | |
19247 | ||
707bfff6 TS |
19248 | int |
19249 | tc_mips_regname_to_dw2regnum (char *regname) | |
19250 | { | |
19251 | unsigned int regnum = -1; | |
19252 | unsigned int reg; | |
19253 | ||
19254 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
19255 | regnum = reg; | |
19256 | ||
19257 | return regnum; | |
19258 | } |