Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
c67a084a NC |
3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
4 | Free Software Foundation, Inc. | |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
741fe287 | 93 | #define ATREG 1 |
252b5132 RH |
94 | #define TREG 24 |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
741fe287 MR |
105 | #define AT mips_opts.at |
106 | ||
252b5132 RH |
107 | /* Allow override of standard little-endian ECOFF format. */ |
108 | ||
109 | #ifndef ECOFF_LITTLE_FORMAT | |
110 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
111 | #endif | |
112 | ||
113 | extern int target_big_endian; | |
114 | ||
252b5132 | 115 | /* The name of the readonly data section. */ |
4d0d148d | 116 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 117 | ? ".rdata" \ |
056350c6 NC |
118 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
119 | ? ".rdata" \ | |
252b5132 RH |
120 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
121 | ? ".rodata" \ | |
122 | : (abort (), "")) | |
123 | ||
47e39b9d RS |
124 | /* Information about an instruction, including its format, operands |
125 | and fixups. */ | |
126 | struct mips_cl_insn | |
127 | { | |
128 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
129 | const struct mips_opcode *insn_mo; | |
130 | ||
131 | /* True if this is a mips16 instruction and if we want the extended | |
132 | form of INSN_MO. */ | |
133 | bfd_boolean use_extend; | |
134 | ||
135 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
136 | unsigned short extend; | |
137 | ||
138 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
139 | a copy of INSN_MO->match with the operands filled in. */ | |
140 | unsigned long insn_opcode; | |
141 | ||
142 | /* The frag that contains the instruction. */ | |
143 | struct frag *frag; | |
144 | ||
145 | /* The offset into FRAG of the first instruction byte. */ | |
146 | long where; | |
147 | ||
148 | /* The relocs associated with the instruction, if any. */ | |
149 | fixS *fixp[3]; | |
150 | ||
a38419a5 RS |
151 | /* True if this entry cannot be moved from its current position. */ |
152 | unsigned int fixed_p : 1; | |
47e39b9d | 153 | |
708587a4 | 154 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
155 | unsigned int noreorder_p : 1; |
156 | ||
2fa15973 RS |
157 | /* True for mips16 instructions that jump to an absolute address. */ |
158 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
159 | }; |
160 | ||
a325df1d TS |
161 | /* The ABI to use. */ |
162 | enum mips_abi_level | |
163 | { | |
164 | NO_ABI = 0, | |
165 | O32_ABI, | |
166 | O64_ABI, | |
167 | N32_ABI, | |
168 | N64_ABI, | |
169 | EABI_ABI | |
170 | }; | |
171 | ||
172 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 173 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 174 | |
143d77c5 EC |
175 | /* Whether or not we have code that can call pic code. */ |
176 | int mips_abicalls = FALSE; | |
177 | ||
aa6975fb ILT |
178 | /* Whether or not we have code which can be put into a shared |
179 | library. */ | |
180 | static bfd_boolean mips_in_shared = TRUE; | |
181 | ||
252b5132 RH |
182 | /* This is the set of options which may be modified by the .set |
183 | pseudo-op. We use a struct so that .set push and .set pop are more | |
184 | reliable. */ | |
185 | ||
e972090a NC |
186 | struct mips_set_options |
187 | { | |
252b5132 RH |
188 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
189 | if it has not been initialized. Changed by `.set mipsN', and the | |
190 | -mipsN command line option, and the default CPU. */ | |
191 | int isa; | |
1f25f5d3 CD |
192 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
193 | if they have not been initialized. Changed by `.set <asename>', by | |
194 | command line options, and based on the default architecture. */ | |
195 | int ase_mips3d; | |
deec1734 | 196 | int ase_mdmx; |
e16bfa71 | 197 | int ase_smartmips; |
74cd071d | 198 | int ase_dsp; |
8b082fb1 | 199 | int ase_dspr2; |
ef2e4d86 | 200 | int ase_mt; |
252b5132 RH |
201 | /* Whether we are assembling for the mips16 processor. 0 if we are |
202 | not, 1 if we are, and -1 if the value has not been initialized. | |
203 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
204 | -nomips16 command line options, and the default CPU. */ | |
205 | int mips16; | |
206 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
207 | reorder' and `.set noreorder'. */ | |
208 | int noreorder; | |
741fe287 MR |
209 | /* Non-zero if we should not permit the register designated "assembler |
210 | temporary" to be used in instructions. The value is the register | |
211 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
212 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
213 | unsigned int at; | |
252b5132 RH |
214 | /* Non-zero if we should warn when a macro instruction expands into |
215 | more than one machine instruction. Changed by `.set nomacro' and | |
216 | `.set macro'. */ | |
217 | int warn_about_macros; | |
218 | /* Non-zero if we should not move instructions. Changed by `.set | |
219 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
220 | int nomove; | |
221 | /* Non-zero if we should not optimize branches by moving the target | |
222 | of the branch into the delay slot. Actually, we don't perform | |
223 | this optimization anyhow. Changed by `.set bopt' and `.set | |
224 | nobopt'. */ | |
225 | int nobopt; | |
226 | /* Non-zero if we should not autoextend mips16 instructions. | |
227 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
228 | int noautoextend; | |
a325df1d TS |
229 | /* Restrict general purpose registers and floating point registers |
230 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
231 | is passed but can changed if the assembler code uses .set mipsN. */ | |
232 | int gp32; | |
233 | int fp32; | |
fef14a42 TS |
234 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
235 | command line option, and the default CPU. */ | |
236 | int arch; | |
aed1a261 RS |
237 | /* True if ".set sym32" is in effect. */ |
238 | bfd_boolean sym32; | |
037b32b9 AN |
239 | /* True if floating-point operations are not allowed. Changed by .set |
240 | softfloat or .set hardfloat, by command line options -msoft-float or | |
241 | -mhard-float. The default is false. */ | |
242 | bfd_boolean soft_float; | |
243 | ||
244 | /* True if only single-precision floating-point operations are allowed. | |
245 | Changed by .set singlefloat or .set doublefloat, command-line options | |
246 | -msingle-float or -mdouble-float. The default is false. */ | |
247 | bfd_boolean single_float; | |
252b5132 RH |
248 | }; |
249 | ||
037b32b9 AN |
250 | /* This is the struct we use to hold the current set of options. Note |
251 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
252 | -1 to indicate that they have not been initialized. */ | |
253 | ||
a325df1d | 254 | /* True if -mgp32 was passed. */ |
a8e8e863 | 255 | static int file_mips_gp32 = -1; |
a325df1d TS |
256 | |
257 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 258 | static int file_mips_fp32 = -1; |
a325df1d | 259 | |
037b32b9 AN |
260 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
261 | static int file_mips_soft_float = 0; | |
262 | ||
263 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
264 | static int file_mips_single_float = 0; | |
252b5132 | 265 | |
e972090a NC |
266 | static struct mips_set_options mips_opts = |
267 | { | |
037b32b9 AN |
268 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
269 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
270 | /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG, | |
271 | /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, | |
272 | /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, | |
273 | /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 274 | }; |
252b5132 RH |
275 | |
276 | /* These variables are filled in with the masks of registers used. | |
277 | The object format code reads them and puts them in the appropriate | |
278 | place. */ | |
279 | unsigned long mips_gprmask; | |
280 | unsigned long mips_cprmask[4]; | |
281 | ||
282 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 283 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 284 | |
a4672219 TS |
285 | /* True if -mips16 was passed or implied by arguments passed on the |
286 | command line (e.g., by -march). */ | |
287 | static int file_ase_mips16; | |
288 | ||
3994f87e TS |
289 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
290 | || mips_opts.isa == ISA_MIPS32R2 \ | |
291 | || mips_opts.isa == ISA_MIPS64 \ | |
292 | || mips_opts.isa == ISA_MIPS64R2) | |
293 | ||
b12dd2e4 CF |
294 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
295 | #ifdef TE_IRIX | |
1180b5a4 | 296 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 297 | #else |
1180b5a4 RS |
298 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
299 | because there's no place for any addend, the only acceptable | |
300 | expression is a bare symbol. */ | |
301 | #define MIPS_JALR_HINT_P(EXPR) \ | |
302 | (!HAVE_IN_PLACE_ADDENDS \ | |
303 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
304 | #endif |
305 | ||
1f25f5d3 CD |
306 | /* True if -mips3d was passed or implied by arguments passed on the |
307 | command line (e.g., by -march). */ | |
308 | static int file_ase_mips3d; | |
309 | ||
deec1734 CD |
310 | /* True if -mdmx was passed or implied by arguments passed on the |
311 | command line (e.g., by -march). */ | |
312 | static int file_ase_mdmx; | |
313 | ||
e16bfa71 TS |
314 | /* True if -msmartmips was passed or implied by arguments passed on the |
315 | command line (e.g., by -march). */ | |
316 | static int file_ase_smartmips; | |
317 | ||
ad3fea08 TS |
318 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
319 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 320 | |
74cd071d CF |
321 | /* True if -mdsp was passed or implied by arguments passed on the |
322 | command line (e.g., by -march). */ | |
323 | static int file_ase_dsp; | |
324 | ||
ad3fea08 TS |
325 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
326 | || mips_opts.isa == ISA_MIPS64R2) | |
327 | ||
65263ce3 TS |
328 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
329 | ||
8b082fb1 TS |
330 | /* True if -mdspr2 was passed or implied by arguments passed on the |
331 | command line (e.g., by -march). */ | |
332 | static int file_ase_dspr2; | |
333 | ||
334 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
335 | || mips_opts.isa == ISA_MIPS64R2) | |
336 | ||
ef2e4d86 CF |
337 | /* True if -mmt was passed or implied by arguments passed on the |
338 | command line (e.g., by -march). */ | |
339 | static int file_ase_mt; | |
340 | ||
ad3fea08 TS |
341 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
342 | || mips_opts.isa == ISA_MIPS64R2) | |
343 | ||
ec68c924 | 344 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 345 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 346 | static const char *mips_arch_string; |
ec68c924 EC |
347 | |
348 | /* The argument of the -mtune= flag. The architecture for which we | |
349 | are optimizing. */ | |
350 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 351 | static const char *mips_tune_string; |
ec68c924 | 352 | |
316f5878 | 353 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
354 | static int mips_32bitmode = 0; |
355 | ||
316f5878 RS |
356 | /* True if the given ABI requires 32-bit registers. */ |
357 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
358 | ||
359 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
360 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
361 | ((ABI) == N32_ABI \ | |
362 | || (ABI) == N64_ABI \ | |
316f5878 RS |
363 | || (ABI) == O64_ABI) |
364 | ||
ad3fea08 | 365 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
366 | #define ISA_HAS_64BIT_REGS(ISA) \ |
367 | ((ISA) == ISA_MIPS3 \ | |
368 | || (ISA) == ISA_MIPS4 \ | |
369 | || (ISA) == ISA_MIPS5 \ | |
370 | || (ISA) == ISA_MIPS64 \ | |
371 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 372 | |
ad3fea08 TS |
373 | /* Return true if ISA supports 64 bit wide float registers. */ |
374 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
375 | ((ISA) == ISA_MIPS3 \ | |
376 | || (ISA) == ISA_MIPS4 \ | |
377 | || (ISA) == ISA_MIPS5 \ | |
378 | || (ISA) == ISA_MIPS32R2 \ | |
379 | || (ISA) == ISA_MIPS64 \ | |
380 | || (ISA) == ISA_MIPS64R2) | |
381 | ||
af7ee8bf CD |
382 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
383 | instructions. */ | |
707bfff6 TS |
384 | #define ISA_HAS_DROR(ISA) \ |
385 | ((ISA) == ISA_MIPS64R2) | |
af7ee8bf CD |
386 | |
387 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
388 | instructions. */ | |
707bfff6 TS |
389 | #define ISA_HAS_ROR(ISA) \ |
390 | ((ISA) == ISA_MIPS32R2 \ | |
391 | || (ISA) == ISA_MIPS64R2 \ | |
392 | || mips_opts.ase_smartmips) | |
393 | ||
7455baf8 TS |
394 | /* Return true if ISA supports single-precision floats in odd registers. */ |
395 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
396 | ((ISA) == ISA_MIPS32 \ | |
397 | || (ISA) == ISA_MIPS32R2 \ | |
398 | || (ISA) == ISA_MIPS64 \ | |
399 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 400 | |
ad3fea08 TS |
401 | /* Return true if ISA supports move to/from high part of a 64-bit |
402 | floating-point register. */ | |
403 | #define ISA_HAS_MXHC1(ISA) \ | |
404 | ((ISA) == ISA_MIPS32R2 \ | |
405 | || (ISA) == ISA_MIPS64R2) | |
406 | ||
e013f690 | 407 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 408 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 409 | |
e013f690 | 410 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 411 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 412 | |
ad3fea08 TS |
413 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
414 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 415 | |
316f5878 | 416 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 417 | |
316f5878 | 418 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 419 | |
3b91255e RS |
420 | /* True if relocations are stored in-place. */ |
421 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
422 | ||
aed1a261 RS |
423 | /* The ABI-derived address size. */ |
424 | #define HAVE_64BIT_ADDRESSES \ | |
425 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
426 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 427 | |
aed1a261 RS |
428 | /* The size of symbolic constants (i.e., expressions of the form |
429 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
430 | #define HAVE_32BIT_SYMBOLS \ | |
431 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
432 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 433 | |
b7c7d6c1 TS |
434 | /* Addresses are loaded in different ways, depending on the address size |
435 | in use. The n32 ABI Documentation also mandates the use of additions | |
436 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 437 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 438 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
439 | |
440 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 441 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
442 | |
443 | #define ADDRESS_LOAD_INSN \ | |
444 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
445 | ||
446 | #define ADDRESS_STORE_INSN \ | |
447 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
448 | ||
a4672219 | 449 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
450 | #define CPU_HAS_MIPS16(cpu) \ |
451 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
452 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 453 | |
60b63b72 RS |
454 | /* True if CPU has a dror instruction. */ |
455 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
456 | ||
457 | /* True if CPU has a ror instruction. */ | |
458 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
459 | ||
dd3cbb7e NC |
460 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
461 | #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON) | |
462 | ||
b19e8a9b AN |
463 | /* True if CPU does not implement the all the coprocessor insns. For these |
464 | CPUs only those COP insns are accepted that are explicitly marked to be | |
465 | available on the CPU. ISA membership for COP insns is ignored. */ | |
466 | #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON) | |
467 | ||
c8978940 CD |
468 | /* True if mflo and mfhi can be immediately followed by instructions |
469 | which write to the HI and LO registers. | |
470 | ||
471 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
472 | (at least) two instructions between the reads of HI/LO and | |
473 | instructions which write them, and later ISAs do not. Contradicting | |
474 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
475 | the UM for the NEC Vr5000) document needing the instructions between | |
476 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
477 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
478 | earlier-ISA CPUs for which CPU documentation declares that the | |
479 | instructions are really interlocked. */ | |
480 | #define hilo_interlocks \ | |
481 | (mips_opts.isa == ISA_MIPS32 \ | |
482 | || mips_opts.isa == ISA_MIPS32R2 \ | |
483 | || mips_opts.isa == ISA_MIPS64 \ | |
484 | || mips_opts.isa == ISA_MIPS64R2 \ | |
485 | || mips_opts.arch == CPU_R4010 \ | |
486 | || mips_opts.arch == CPU_R10000 \ | |
487 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
488 | || mips_opts.arch == CPU_R14000 \ |
489 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 490 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 CD |
491 | || mips_opts.arch == CPU_VR5500 \ |
492 | ) | |
252b5132 RH |
493 | |
494 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
495 | from the GPRs after they are loaded from memory, and thus does not |
496 | require nops to be inserted. This applies to instructions marked | |
497 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
498 | level I. */ | |
252b5132 | 499 | #define gpr_interlocks \ |
e7af610e | 500 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 501 | || mips_opts.arch == CPU_R3900) |
252b5132 | 502 | |
81912461 ILT |
503 | /* Whether the processor uses hardware interlocks to avoid delays |
504 | required by coprocessor instructions, and thus does not require | |
505 | nops to be inserted. This applies to instructions marked | |
506 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
507 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
508 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
509 | levels I, II, and III. */ | |
bdaaa2e1 | 510 | /* Itbl support may require additional care here. */ |
81912461 ILT |
511 | #define cop_interlocks \ |
512 | ((mips_opts.isa != ISA_MIPS1 \ | |
513 | && mips_opts.isa != ISA_MIPS2 \ | |
514 | && mips_opts.isa != ISA_MIPS3) \ | |
515 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
516 | ) |
517 | ||
518 | /* Whether the processor uses hardware interlocks to protect reads | |
519 | from coprocessor registers after they are loaded from memory, and | |
520 | thus does not require nops to be inserted. This applies to | |
521 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
522 | requires at MIPS ISA level I. */ | |
523 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 524 | |
6b76fefe CM |
525 | /* Is this a mfhi or mflo instruction? */ |
526 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
527 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
528 | ||
529 | /* Returns true for a (non floating-point) coprocessor instruction. Reading | |
530 | or writing the condition code is only possible on the coprocessors and | |
531 | these insns are not marked with INSN_COP. Thus for these insns use the | |
a242dc0d | 532 | condition-code flags. */ |
b19e8a9b AN |
533 | #define COP_INSN(PINFO) \ |
534 | (PINFO != INSN_MACRO \ | |
a242dc0d AN |
535 | && ((PINFO) & (FP_S | FP_D)) == 0 \ |
536 | && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE))) | |
6b76fefe | 537 | |
252b5132 RH |
538 | /* MIPS PIC level. */ |
539 | ||
a161fe53 | 540 | enum mips_pic_level mips_pic; |
252b5132 | 541 | |
c9914766 | 542 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 543 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 544 | static int mips_big_got = 0; |
252b5132 RH |
545 | |
546 | /* 1 if trap instructions should used for overflow rather than break | |
547 | instructions. */ | |
c9914766 | 548 | static int mips_trap = 0; |
252b5132 | 549 | |
119d663a | 550 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 551 | by assembling two single width halves into two single width floating |
119d663a NC |
552 | point registers which just happen to alias the double width destination |
553 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 554 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
555 | automatically at assemble time. */ |
556 | static int mips_disable_float_construction; | |
557 | ||
252b5132 RH |
558 | /* Non-zero if any .set noreorder directives were used. */ |
559 | ||
560 | static int mips_any_noreorder; | |
561 | ||
6b76fefe CM |
562 | /* Non-zero if nops should be inserted when the register referenced in |
563 | an mfhi/mflo instruction is read in the next two instructions. */ | |
564 | static int mips_7000_hilo_fix; | |
565 | ||
02ffd3e4 | 566 | /* The size of objects in the small data section. */ |
156c2f8b | 567 | static unsigned int g_switch_value = 8; |
252b5132 RH |
568 | /* Whether the -G option was used. */ |
569 | static int g_switch_seen = 0; | |
570 | ||
571 | #define N_RMASK 0xc4 | |
572 | #define N_VFP 0xd4 | |
573 | ||
574 | /* If we can determine in advance that GP optimization won't be | |
575 | possible, we can skip the relaxation stuff that tries to produce | |
576 | GP-relative references. This makes delay slot optimization work | |
577 | better. | |
578 | ||
579 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
580 | gcc output. It needs to guess right for gcc, otherwise gcc |
581 | will put what it thinks is a GP-relative instruction in a branch | |
582 | delay slot. | |
252b5132 RH |
583 | |
584 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
585 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 586 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
587 | |
588 | /* handle of the OPCODE hash table */ | |
589 | static struct hash_control *op_hash = NULL; | |
590 | ||
591 | /* The opcode hash table we use for the mips16. */ | |
592 | static struct hash_control *mips16_op_hash = NULL; | |
593 | ||
594 | /* This array holds the chars that always start a comment. If the | |
595 | pre-processor is disabled, these aren't very useful */ | |
596 | const char comment_chars[] = "#"; | |
597 | ||
598 | /* This array holds the chars that only start a comment at the beginning of | |
599 | a line. If the line seems to have the form '# 123 filename' | |
600 | .line and .file directives will appear in the pre-processed output */ | |
601 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
602 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 603 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
604 | /* Also note that C style comments are always supported. */ |
605 | const char line_comment_chars[] = "#"; | |
606 | ||
bdaaa2e1 | 607 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 608 | const char line_separator_chars[] = ";"; |
252b5132 RH |
609 | |
610 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
611 | const char EXP_CHARS[] = "eE"; | |
612 | ||
613 | /* Chars that mean this number is a floating point constant */ | |
614 | /* As in 0f12.456 */ | |
615 | /* or 0d1.2345e12 */ | |
616 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
617 | ||
618 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
619 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
620 | but nothing is ideal around here. | |
621 | */ | |
622 | ||
623 | static char *insn_error; | |
624 | ||
625 | static int auto_align = 1; | |
626 | ||
627 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
628 | offset in the stack frame from which to restore the $gp register. | |
629 | This is set by the .cprestore pseudo-op, and saved in this | |
630 | variable. */ | |
631 | static offsetT mips_cprestore_offset = -1; | |
632 | ||
67c1ffbe | 633 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 634 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 635 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
636 | static offsetT mips_cpreturn_offset = -1; |
637 | static int mips_cpreturn_register = -1; | |
638 | static int mips_gp_register = GP; | |
def2e0dd | 639 | static int mips_gprel_offset = 0; |
6478892d | 640 | |
7a621144 DJ |
641 | /* Whether mips_cprestore_offset has been set in the current function |
642 | (or whether it has already been warned about, if not). */ | |
643 | static int mips_cprestore_valid = 0; | |
644 | ||
252b5132 RH |
645 | /* This is the register which holds the stack frame, as set by the |
646 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
647 | static int mips_frame_reg = SP; | |
648 | ||
7a621144 DJ |
649 | /* Whether mips_frame_reg has been set in the current function |
650 | (or whether it has already been warned about, if not). */ | |
651 | static int mips_frame_reg_valid = 0; | |
652 | ||
252b5132 RH |
653 | /* To output NOP instructions correctly, we need to keep information |
654 | about the previous two instructions. */ | |
655 | ||
656 | /* Whether we are optimizing. The default value of 2 means to remove | |
657 | unneeded NOPs and swap branch instructions when possible. A value | |
658 | of 1 means to not swap branches. A value of 0 means to always | |
659 | insert NOPs. */ | |
660 | static int mips_optimize = 2; | |
661 | ||
662 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
663 | equivalent to seeing no -g option at all. */ | |
664 | static int mips_debug = 0; | |
665 | ||
7d8e00cf RS |
666 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
667 | #define MAX_VR4130_NOPS 4 | |
668 | ||
669 | /* The maximum number of NOPs needed to fill delay slots. */ | |
670 | #define MAX_DELAY_NOPS 2 | |
671 | ||
672 | /* The maximum number of NOPs needed for any purpose. */ | |
673 | #define MAX_NOPS 4 | |
71400594 RS |
674 | |
675 | /* A list of previous instructions, with index 0 being the most recent. | |
676 | We need to look back MAX_NOPS instructions when filling delay slots | |
677 | or working around processor errata. We need to look back one | |
678 | instruction further if we're thinking about using history[0] to | |
679 | fill a branch delay slot. */ | |
680 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 681 | |
1e915849 RS |
682 | /* Nop instructions used by emit_nop. */ |
683 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
684 | ||
685 | /* The appropriate nop for the current mode. */ | |
686 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 687 | |
252b5132 RH |
688 | /* If this is set, it points to a frag holding nop instructions which |
689 | were inserted before the start of a noreorder section. If those | |
690 | nops turn out to be unnecessary, the size of the frag can be | |
691 | decreased. */ | |
692 | static fragS *prev_nop_frag; | |
693 | ||
694 | /* The number of nop instructions we created in prev_nop_frag. */ | |
695 | static int prev_nop_frag_holds; | |
696 | ||
697 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 698 | prev_nop_frag. */ |
252b5132 RH |
699 | static int prev_nop_frag_required; |
700 | ||
701 | /* The number of instructions we've seen since prev_nop_frag. */ | |
702 | static int prev_nop_frag_since; | |
703 | ||
704 | /* For ECOFF and ELF, relocations against symbols are done in two | |
705 | parts, with a HI relocation and a LO relocation. Each relocation | |
706 | has only 16 bits of space to store an addend. This means that in | |
707 | order for the linker to handle carries correctly, it must be able | |
708 | to locate both the HI and the LO relocation. This means that the | |
709 | relocations must appear in order in the relocation table. | |
710 | ||
711 | In order to implement this, we keep track of each unmatched HI | |
712 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 713 | corresponding LO relocation. */ |
252b5132 | 714 | |
e972090a NC |
715 | struct mips_hi_fixup |
716 | { | |
252b5132 RH |
717 | /* Next HI fixup. */ |
718 | struct mips_hi_fixup *next; | |
719 | /* This fixup. */ | |
720 | fixS *fixp; | |
721 | /* The section this fixup is in. */ | |
722 | segT seg; | |
723 | }; | |
724 | ||
725 | /* The list of unmatched HI relocs. */ | |
726 | ||
727 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
728 | ||
64bdfcaf RS |
729 | /* The frag containing the last explicit relocation operator. |
730 | Null if explicit relocations have not been used. */ | |
731 | ||
732 | static fragS *prev_reloc_op_frag; | |
733 | ||
252b5132 RH |
734 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
735 | ||
736 | #define X ILLEGAL_REG | |
e972090a NC |
737 | static const int mips32_to_16_reg_map[] = |
738 | { | |
252b5132 RH |
739 | X, X, 2, 3, 4, 5, 6, 7, |
740 | X, X, X, X, X, X, X, X, | |
741 | 0, 1, X, X, X, X, X, X, | |
742 | X, X, X, X, X, X, X, X | |
743 | }; | |
744 | #undef X | |
745 | ||
746 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
747 | ||
e972090a NC |
748 | static const unsigned int mips16_to_32_reg_map[] = |
749 | { | |
252b5132 RH |
750 | 16, 17, 2, 3, 4, 5, 6, 7 |
751 | }; | |
60b63b72 | 752 | |
71400594 RS |
753 | /* Classifies the kind of instructions we're interested in when |
754 | implementing -mfix-vr4120. */ | |
c67a084a NC |
755 | enum fix_vr4120_class |
756 | { | |
71400594 RS |
757 | FIX_VR4120_MACC, |
758 | FIX_VR4120_DMACC, | |
759 | FIX_VR4120_MULT, | |
760 | FIX_VR4120_DMULT, | |
761 | FIX_VR4120_DIV, | |
762 | FIX_VR4120_MTHILO, | |
763 | NUM_FIX_VR4120_CLASSES | |
764 | }; | |
765 | ||
c67a084a NC |
766 | /* ...likewise -mfix-loongson2f-jump. */ |
767 | static bfd_boolean mips_fix_loongson2f_jump; | |
768 | ||
769 | /* ...likewise -mfix-loongson2f-nop. */ | |
770 | static bfd_boolean mips_fix_loongson2f_nop; | |
771 | ||
772 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
773 | static bfd_boolean mips_fix_loongson2f; | |
774 | ||
71400594 RS |
775 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
776 | there must be at least one other instruction between an instruction | |
777 | of type X and an instruction of type Y. */ | |
778 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
779 | ||
780 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 781 | static int mips_fix_vr4120; |
4a6a3df4 | 782 | |
7d8e00cf RS |
783 | /* ...likewise -mfix-vr4130. */ |
784 | static int mips_fix_vr4130; | |
785 | ||
6a32d874 CM |
786 | /* ...likewise -mfix-24k. */ |
787 | static int mips_fix_24k; | |
788 | ||
4a6a3df4 AO |
789 | /* We don't relax branches by default, since this causes us to expand |
790 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
791 | fail to compute the offset before expanding the macro to the most | |
792 | efficient expansion. */ | |
793 | ||
794 | static int mips_relax_branch; | |
252b5132 | 795 | \f |
4d7206a2 RS |
796 | /* The expansion of many macros depends on the type of symbol that |
797 | they refer to. For example, when generating position-dependent code, | |
798 | a macro that refers to a symbol may have two different expansions, | |
799 | one which uses GP-relative addresses and one which uses absolute | |
800 | addresses. When generating SVR4-style PIC, a macro may have | |
801 | different expansions for local and global symbols. | |
802 | ||
803 | We handle these situations by generating both sequences and putting | |
804 | them in variant frags. In position-dependent code, the first sequence | |
805 | will be the GP-relative one and the second sequence will be the | |
806 | absolute one. In SVR4 PIC, the first sequence will be for global | |
807 | symbols and the second will be for local symbols. | |
808 | ||
584892a6 RS |
809 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
810 | SECOND are the lengths of the two sequences in bytes. These fields | |
811 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
812 | the subtype has the following flags: | |
4d7206a2 | 813 | |
584892a6 RS |
814 | RELAX_USE_SECOND |
815 | Set if it has been decided that we should use the second | |
816 | sequence instead of the first. | |
817 | ||
818 | RELAX_SECOND_LONGER | |
819 | Set in the first variant frag if the macro's second implementation | |
820 | is longer than its first. This refers to the macro as a whole, | |
821 | not an individual relaxation. | |
822 | ||
823 | RELAX_NOMACRO | |
824 | Set in the first variant frag if the macro appeared in a .set nomacro | |
825 | block and if one alternative requires a warning but the other does not. | |
826 | ||
827 | RELAX_DELAY_SLOT | |
828 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
829 | delay slot. | |
4d7206a2 RS |
830 | |
831 | The frag's "opcode" points to the first fixup for relaxable code. | |
832 | ||
833 | Relaxable macros are generated using a sequence such as: | |
834 | ||
835 | relax_start (SYMBOL); | |
836 | ... generate first expansion ... | |
837 | relax_switch (); | |
838 | ... generate second expansion ... | |
839 | relax_end (); | |
840 | ||
841 | The code and fixups for the unwanted alternative are discarded | |
842 | by md_convert_frag. */ | |
584892a6 | 843 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 844 | |
584892a6 RS |
845 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
846 | #define RELAX_SECOND(X) ((X) & 0xff) | |
847 | #define RELAX_USE_SECOND 0x10000 | |
848 | #define RELAX_SECOND_LONGER 0x20000 | |
849 | #define RELAX_NOMACRO 0x40000 | |
850 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 851 | |
4a6a3df4 AO |
852 | /* Branch without likely bit. If label is out of range, we turn: |
853 | ||
854 | beq reg1, reg2, label | |
855 | delay slot | |
856 | ||
857 | into | |
858 | ||
859 | bne reg1, reg2, 0f | |
860 | nop | |
861 | j label | |
862 | 0: delay slot | |
863 | ||
864 | with the following opcode replacements: | |
865 | ||
866 | beq <-> bne | |
867 | blez <-> bgtz | |
868 | bltz <-> bgez | |
869 | bc1f <-> bc1t | |
870 | ||
871 | bltzal <-> bgezal (with jal label instead of j label) | |
872 | ||
873 | Even though keeping the delay slot instruction in the delay slot of | |
874 | the branch would be more efficient, it would be very tricky to do | |
875 | correctly, because we'd have to introduce a variable frag *after* | |
876 | the delay slot instruction, and expand that instead. Let's do it | |
877 | the easy way for now, even if the branch-not-taken case now costs | |
878 | one additional instruction. Out-of-range branches are not supposed | |
879 | to be common, anyway. | |
880 | ||
881 | Branch likely. If label is out of range, we turn: | |
882 | ||
883 | beql reg1, reg2, label | |
884 | delay slot (annulled if branch not taken) | |
885 | ||
886 | into | |
887 | ||
888 | beql reg1, reg2, 1f | |
889 | nop | |
890 | beql $0, $0, 2f | |
891 | nop | |
892 | 1: j[al] label | |
893 | delay slot (executed only if branch taken) | |
894 | 2: | |
895 | ||
896 | It would be possible to generate a shorter sequence by losing the | |
897 | likely bit, generating something like: | |
b34976b6 | 898 | |
4a6a3df4 AO |
899 | bne reg1, reg2, 0f |
900 | nop | |
901 | j[al] label | |
902 | delay slot (executed only if branch taken) | |
903 | 0: | |
904 | ||
905 | beql -> bne | |
906 | bnel -> beq | |
907 | blezl -> bgtz | |
908 | bgtzl -> blez | |
909 | bltzl -> bgez | |
910 | bgezl -> bltz | |
911 | bc1fl -> bc1t | |
912 | bc1tl -> bc1f | |
913 | ||
914 | bltzall -> bgezal (with jal label instead of j label) | |
915 | bgezall -> bltzal (ditto) | |
916 | ||
917 | ||
918 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 919 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
920 | ((relax_substateT) \ |
921 | (0xc0000000 \ | |
922 | | ((toofar) ? 1 : 0) \ | |
923 | | ((link) ? 2 : 0) \ | |
924 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 925 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 926 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
927 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
928 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
929 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 930 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 931 | |
252b5132 RH |
932 | /* For mips16 code, we use an entirely different form of relaxation. |
933 | mips16 supports two versions of most instructions which take | |
934 | immediate values: a small one which takes some small value, and a | |
935 | larger one which takes a 16 bit value. Since branches also follow | |
936 | this pattern, relaxing these values is required. | |
937 | ||
938 | We can assemble both mips16 and normal MIPS code in a single | |
939 | object. Therefore, we need to support this type of relaxation at | |
940 | the same time that we support the relaxation described above. We | |
941 | use the high bit of the subtype field to distinguish these cases. | |
942 | ||
943 | The information we store for this type of relaxation is the | |
944 | argument code found in the opcode file for this relocation, whether | |
945 | the user explicitly requested a small or extended form, and whether | |
946 | the relocation is in a jump or jal delay slot. That tells us the | |
947 | size of the value, and how it should be stored. We also store | |
948 | whether the fragment is considered to be extended or not. We also | |
949 | store whether this is known to be a branch to a different section, | |
950 | whether we have tried to relax this frag yet, and whether we have | |
951 | ever extended a PC relative fragment because of a shift count. */ | |
952 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
953 | (0x80000000 \ | |
954 | | ((type) & 0xff) \ | |
955 | | ((small) ? 0x100 : 0) \ | |
956 | | ((ext) ? 0x200 : 0) \ | |
957 | | ((dslot) ? 0x400 : 0) \ | |
958 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 959 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
960 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
961 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
962 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
963 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
964 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
965 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
966 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
967 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
968 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
969 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
970 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
971 | |
972 | /* Is the given value a sign-extended 32-bit value? */ | |
973 | #define IS_SEXT_32BIT_NUM(x) \ | |
974 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
975 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
976 | ||
977 | /* Is the given value a sign-extended 16-bit value? */ | |
978 | #define IS_SEXT_16BIT_NUM(x) \ | |
979 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
980 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
981 | ||
2051e8c4 MR |
982 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
983 | #define IS_ZEXT_32BIT_NUM(x) \ | |
984 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
985 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
986 | ||
bf12938e RS |
987 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
988 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
989 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
990 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
991 | | (((VALUE) & (MASK)) << (SHIFT))) | |
992 | ||
993 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
994 | SHIFT places. */ | |
995 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
996 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
997 | ||
998 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
999 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1000 | ||
1001 | include/opcode/mips.h specifies operand fields using the macros | |
1002 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1003 | with "MIPS16OP" instead of "OP". */ | |
1004 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
1005 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
1006 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
1007 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1008 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1009 | ||
1010 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
1011 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
1012 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
1013 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
1014 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1015 | MIPS16OP_MASK_##FIELD, \ | |
1016 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
1017 | \f |
1018 | /* Global variables used when generating relaxable macros. See the | |
1019 | comment above RELAX_ENCODE for more details about how relaxation | |
1020 | is used. */ | |
1021 | static struct { | |
1022 | /* 0 if we're not emitting a relaxable macro. | |
1023 | 1 if we're emitting the first of the two relaxation alternatives. | |
1024 | 2 if we're emitting the second alternative. */ | |
1025 | int sequence; | |
1026 | ||
1027 | /* The first relaxable fixup in the current frag. (In other words, | |
1028 | the first fixup that refers to relaxable code.) */ | |
1029 | fixS *first_fixup; | |
1030 | ||
1031 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1032 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1033 | unsigned int sizes[2]; | |
1034 | ||
1035 | /* The symbol on which the choice of sequence depends. */ | |
1036 | symbolS *symbol; | |
1037 | } mips_relax; | |
252b5132 | 1038 | \f |
584892a6 RS |
1039 | /* Global variables used to decide whether a macro needs a warning. */ |
1040 | static struct { | |
1041 | /* True if the macro is in a branch delay slot. */ | |
1042 | bfd_boolean delay_slot_p; | |
1043 | ||
1044 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
1045 | in bytes and sizes[1] is the length of the second alternative. | |
1046 | For non-relaxable macros, both elements give the length of the | |
1047 | macro in bytes. */ | |
1048 | unsigned int sizes[2]; | |
1049 | ||
1050 | /* The first variant frag for this macro. */ | |
1051 | fragS *first_frag; | |
1052 | } mips_macro_warning; | |
1053 | \f | |
252b5132 RH |
1054 | /* Prototypes for static functions. */ |
1055 | ||
17a2f251 | 1056 | #define internalError() \ |
252b5132 | 1057 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
1058 | |
1059 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
1060 | ||
b34976b6 | 1061 | static void append_insn |
c67a084a | 1062 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *); |
7d10b47d | 1063 | static void mips_no_prev_insn (void); |
c67a084a | 1064 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1065 | static void mips16_macro_build |
67c0d1eb RS |
1066 | (expressionS *, const char *, const char *, va_list); |
1067 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
1068 | static void macro_start (void); |
1069 | static void macro_end (void); | |
17a2f251 TS |
1070 | static void macro (struct mips_cl_insn * ip); |
1071 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 1072 | #ifdef LOSING_COMPILER |
17a2f251 | 1073 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 1074 | #endif |
17a2f251 TS |
1075 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1076 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1077 | static void mips16_immed |
17a2f251 TS |
1078 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
1079 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 1080 | static size_t my_getSmallExpression |
17a2f251 TS |
1081 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1082 | static void my_getExpression (expressionS *, char *); | |
1083 | static void s_align (int); | |
1084 | static void s_change_sec (int); | |
1085 | static void s_change_section (int); | |
1086 | static void s_cons (int); | |
1087 | static void s_float_cons (int); | |
1088 | static void s_mips_globl (int); | |
1089 | static void s_option (int); | |
1090 | static void s_mipsset (int); | |
1091 | static void s_abicalls (int); | |
1092 | static void s_cpload (int); | |
1093 | static void s_cpsetup (int); | |
1094 | static void s_cplocal (int); | |
1095 | static void s_cprestore (int); | |
1096 | static void s_cpreturn (int); | |
741d6ea8 JM |
1097 | static void s_dtprelword (int); |
1098 | static void s_dtpreldword (int); | |
17a2f251 TS |
1099 | static void s_gpvalue (int); |
1100 | static void s_gpword (int); | |
1101 | static void s_gpdword (int); | |
1102 | static void s_cpadd (int); | |
1103 | static void s_insn (int); | |
1104 | static void md_obj_begin (void); | |
1105 | static void md_obj_end (void); | |
1106 | static void s_mips_ent (int); | |
1107 | static void s_mips_end (int); | |
1108 | static void s_mips_frame (int); | |
1109 | static void s_mips_mask (int reg_type); | |
1110 | static void s_mips_stab (int); | |
1111 | static void s_mips_weakext (int); | |
1112 | static void s_mips_file (int); | |
1113 | static void s_mips_loc (int); | |
1114 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1115 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1116 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
1117 | |
1118 | /* Table and functions used to map between CPU/ISA names, and | |
1119 | ISA levels, and CPU numbers. */ | |
1120 | ||
e972090a NC |
1121 | struct mips_cpu_info |
1122 | { | |
e7af610e | 1123 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1124 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1125 | int isa; /* ISA level. */ |
1126 | int cpu; /* CPU number (default CPU if ISA). */ | |
1127 | }; | |
1128 | ||
ad3fea08 TS |
1129 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1130 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1131 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1132 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1133 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1134 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1135 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
ad3fea08 | 1136 | |
17a2f251 TS |
1137 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1138 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1139 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1140 | \f |
1141 | /* Pseudo-op table. | |
1142 | ||
1143 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1144 | should be defined here, but are currently unsupported: .alias, | |
1145 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1146 | ||
1147 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1148 | specific to the type of debugging information being generated, and | |
1149 | should be defined by the object format: .aent, .begin, .bend, | |
1150 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1151 | .vreg. | |
1152 | ||
1153 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1154 | not MIPS CPU specific, but are also not specific to the object file | |
1155 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1156 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1157 | |
e972090a NC |
1158 | static const pseudo_typeS mips_pseudo_table[] = |
1159 | { | |
beae10d5 | 1160 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1161 | {"option", s_option, 0}, |
1162 | {"set", s_mipsset, 0}, | |
1163 | {"rdata", s_change_sec, 'r'}, | |
1164 | {"sdata", s_change_sec, 's'}, | |
1165 | {"livereg", s_ignore, 0}, | |
1166 | {"abicalls", s_abicalls, 0}, | |
1167 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1168 | {"cpsetup", s_cpsetup, 0}, |
1169 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1170 | {"cprestore", s_cprestore, 0}, |
6478892d | 1171 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1172 | {"dtprelword", s_dtprelword, 0}, |
1173 | {"dtpreldword", s_dtpreldword, 0}, | |
6478892d | 1174 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1175 | {"gpword", s_gpword, 0}, |
10181a0d | 1176 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1177 | {"cpadd", s_cpadd, 0}, |
1178 | {"insn", s_insn, 0}, | |
1179 | ||
beae10d5 | 1180 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1181 | chips. */ |
38a57ae7 | 1182 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1183 | {"bss", s_change_sec, 'b'}, |
1184 | {"err", s_err, 0}, | |
1185 | {"half", s_cons, 1}, | |
1186 | {"dword", s_cons, 3}, | |
1187 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1188 | {"origin", s_org, 0}, |
1189 | {"repeat", s_rept, 0}, | |
252b5132 | 1190 | |
beae10d5 | 1191 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1192 | here for one reason or another. */ |
1193 | {"align", s_align, 0}, | |
1194 | {"byte", s_cons, 0}, | |
1195 | {"data", s_change_sec, 'd'}, | |
1196 | {"double", s_float_cons, 'd'}, | |
1197 | {"float", s_float_cons, 'f'}, | |
1198 | {"globl", s_mips_globl, 0}, | |
1199 | {"global", s_mips_globl, 0}, | |
1200 | {"hword", s_cons, 1}, | |
1201 | {"int", s_cons, 2}, | |
1202 | {"long", s_cons, 2}, | |
1203 | {"octa", s_cons, 4}, | |
1204 | {"quad", s_cons, 3}, | |
cca86cc8 | 1205 | {"section", s_change_section, 0}, |
252b5132 RH |
1206 | {"short", s_cons, 1}, |
1207 | {"single", s_float_cons, 'f'}, | |
1208 | {"stabn", s_mips_stab, 'n'}, | |
1209 | {"text", s_change_sec, 't'}, | |
1210 | {"word", s_cons, 2}, | |
add56521 | 1211 | |
add56521 | 1212 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1213 | |
43841e91 | 1214 | { NULL, NULL, 0 }, |
252b5132 RH |
1215 | }; |
1216 | ||
e972090a NC |
1217 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1218 | { | |
beae10d5 KH |
1219 | /* These pseudo-ops should be defined by the object file format. |
1220 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1221 | {"aent", s_mips_ent, 1}, |
1222 | {"bgnb", s_ignore, 0}, | |
1223 | {"end", s_mips_end, 0}, | |
1224 | {"endb", s_ignore, 0}, | |
1225 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1226 | {"file", s_mips_file, 0}, |
252b5132 RH |
1227 | {"fmask", s_mips_mask, 'F'}, |
1228 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1229 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1230 | {"mask", s_mips_mask, 'R'}, |
1231 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1232 | { NULL, NULL, 0 }, |
252b5132 RH |
1233 | }; |
1234 | ||
17a2f251 | 1235 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1236 | |
1237 | void | |
17a2f251 | 1238 | mips_pop_insert (void) |
252b5132 RH |
1239 | { |
1240 | pop_insert (mips_pseudo_table); | |
1241 | if (! ECOFF_DEBUGGING) | |
1242 | pop_insert (mips_nonecoff_pseudo_table); | |
1243 | } | |
1244 | \f | |
1245 | /* Symbols labelling the current insn. */ | |
1246 | ||
e972090a NC |
1247 | struct insn_label_list |
1248 | { | |
252b5132 RH |
1249 | struct insn_label_list *next; |
1250 | symbolS *label; | |
1251 | }; | |
1252 | ||
252b5132 | 1253 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1254 | #define label_list tc_segment_info_data.labels |
252b5132 | 1255 | |
17a2f251 | 1256 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1257 | |
1258 | static inline void | |
17a2f251 | 1259 | mips_clear_insn_labels (void) |
252b5132 RH |
1260 | { |
1261 | register struct insn_label_list **pl; | |
a8dbcb85 | 1262 | segment_info_type *si; |
252b5132 | 1263 | |
a8dbcb85 TS |
1264 | if (now_seg) |
1265 | { | |
1266 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1267 | ; | |
1268 | ||
1269 | si = seg_info (now_seg); | |
1270 | *pl = si->label_list; | |
1271 | si->label_list = NULL; | |
1272 | } | |
252b5132 | 1273 | } |
a8dbcb85 | 1274 | |
252b5132 RH |
1275 | \f |
1276 | static char *expr_end; | |
1277 | ||
1278 | /* Expressions which appear in instructions. These are set by | |
1279 | mips_ip. */ | |
1280 | ||
1281 | static expressionS imm_expr; | |
5f74bc13 | 1282 | static expressionS imm2_expr; |
252b5132 RH |
1283 | static expressionS offset_expr; |
1284 | ||
1285 | /* Relocs associated with imm_expr and offset_expr. */ | |
1286 | ||
f6688943 TS |
1287 | static bfd_reloc_code_real_type imm_reloc[3] |
1288 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1289 | static bfd_reloc_code_real_type offset_reloc[3] | |
1290 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1291 | |
252b5132 RH |
1292 | /* These are set by mips16_ip if an explicit extension is used. */ |
1293 | ||
b34976b6 | 1294 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1295 | |
7ed4a06a | 1296 | #ifdef OBJ_ELF |
ecb4347a DJ |
1297 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1298 | ECOFF debugging. */ | |
252b5132 RH |
1299 | |
1300 | static segT pdr_seg; | |
7ed4a06a | 1301 | #endif |
252b5132 | 1302 | |
e013f690 TS |
1303 | /* The default target format to use. */ |
1304 | ||
1305 | const char * | |
17a2f251 | 1306 | mips_target_format (void) |
e013f690 TS |
1307 | { |
1308 | switch (OUTPUT_FLAVOR) | |
1309 | { | |
e013f690 TS |
1310 | case bfd_target_ecoff_flavour: |
1311 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1312 | case bfd_target_coff_flavour: | |
1313 | return "pe-mips"; | |
1314 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1315 | #ifdef TE_VXWORKS |
1316 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1317 | return (target_big_endian | |
1318 | ? "elf32-bigmips-vxworks" | |
1319 | : "elf32-littlemips-vxworks"); | |
1320 | #endif | |
e013f690 | 1321 | #ifdef TE_TMIPS |
cfe86eaa | 1322 | /* This is traditional mips. */ |
e013f690 | 1323 | return (target_big_endian |
cfe86eaa TS |
1324 | ? (HAVE_64BIT_OBJECTS |
1325 | ? "elf64-tradbigmips" | |
1326 | : (HAVE_NEWABI | |
1327 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1328 | : (HAVE_64BIT_OBJECTS | |
1329 | ? "elf64-tradlittlemips" | |
1330 | : (HAVE_NEWABI | |
1331 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1332 | #else |
1333 | return (target_big_endian | |
cfe86eaa TS |
1334 | ? (HAVE_64BIT_OBJECTS |
1335 | ? "elf64-bigmips" | |
1336 | : (HAVE_NEWABI | |
1337 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1338 | : (HAVE_64BIT_OBJECTS | |
1339 | ? "elf64-littlemips" | |
1340 | : (HAVE_NEWABI | |
1341 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1342 | #endif |
1343 | default: | |
1344 | abort (); | |
1345 | return NULL; | |
1346 | } | |
1347 | } | |
1348 | ||
1e915849 RS |
1349 | /* Return the length of instruction INSN. */ |
1350 | ||
1351 | static inline unsigned int | |
1352 | insn_length (const struct mips_cl_insn *insn) | |
1353 | { | |
1354 | if (!mips_opts.mips16) | |
1355 | return 4; | |
1356 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1357 | } | |
1358 | ||
1359 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1360 | ||
1361 | static void | |
1362 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1363 | { | |
1364 | size_t i; | |
1365 | ||
1366 | insn->insn_mo = mo; | |
1367 | insn->use_extend = FALSE; | |
1368 | insn->extend = 0; | |
1369 | insn->insn_opcode = mo->match; | |
1370 | insn->frag = NULL; | |
1371 | insn->where = 0; | |
1372 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1373 | insn->fixp[i] = NULL; | |
1374 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1375 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1376 | insn->mips16_absolute_jump_p = 0; | |
1377 | } | |
1378 | ||
742a56fe RS |
1379 | /* Record the current MIPS16 mode in now_seg. */ |
1380 | ||
1381 | static void | |
1382 | mips_record_mips16_mode (void) | |
1383 | { | |
1384 | segment_info_type *si; | |
1385 | ||
1386 | si = seg_info (now_seg); | |
1387 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1388 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
1389 | } | |
1390 | ||
1e915849 RS |
1391 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1392 | ||
1393 | static void | |
1394 | install_insn (const struct mips_cl_insn *insn) | |
1395 | { | |
1396 | char *f = insn->frag->fr_literal + insn->where; | |
1397 | if (!mips_opts.mips16) | |
1398 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1399 | else if (insn->mips16_absolute_jump_p) | |
1400 | { | |
1401 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1402 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1403 | } | |
1404 | else | |
1405 | { | |
1406 | if (insn->use_extend) | |
1407 | { | |
1408 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1409 | f += 2; | |
1410 | } | |
1411 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1412 | } | |
742a56fe | 1413 | mips_record_mips16_mode (); |
1e915849 RS |
1414 | } |
1415 | ||
1416 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1417 | and install the opcode in the new location. */ | |
1418 | ||
1419 | static void | |
1420 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1421 | { | |
1422 | size_t i; | |
1423 | ||
1424 | insn->frag = frag; | |
1425 | insn->where = where; | |
1426 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1427 | if (insn->fixp[i] != NULL) | |
1428 | { | |
1429 | insn->fixp[i]->fx_frag = frag; | |
1430 | insn->fixp[i]->fx_where = where; | |
1431 | } | |
1432 | install_insn (insn); | |
1433 | } | |
1434 | ||
1435 | /* Add INSN to the end of the output. */ | |
1436 | ||
1437 | static void | |
1438 | add_fixed_insn (struct mips_cl_insn *insn) | |
1439 | { | |
1440 | char *f = frag_more (insn_length (insn)); | |
1441 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1442 | } | |
1443 | ||
1444 | /* Start a variant frag and move INSN to the start of the variant part, | |
1445 | marking it as fixed. The other arguments are as for frag_var. */ | |
1446 | ||
1447 | static void | |
1448 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1449 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1450 | { | |
1451 | frag_grow (max_chars); | |
1452 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1453 | insn->fixed_p = 1; | |
1454 | frag_var (rs_machine_dependent, max_chars, var, | |
1455 | subtype, symbol, offset, NULL); | |
1456 | } | |
1457 | ||
1458 | /* Insert N copies of INSN into the history buffer, starting at | |
1459 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1460 | ||
1461 | static void | |
1462 | insert_into_history (unsigned int first, unsigned int n, | |
1463 | const struct mips_cl_insn *insn) | |
1464 | { | |
1465 | if (mips_relax.sequence != 2) | |
1466 | { | |
1467 | unsigned int i; | |
1468 | ||
1469 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1470 | if (i >= first + n) | |
1471 | history[i] = history[i - n]; | |
1472 | else | |
1473 | history[i] = *insn; | |
1474 | } | |
1475 | } | |
1476 | ||
1477 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1478 | ||
1479 | static void | |
1480 | emit_nop (void) | |
1481 | { | |
1482 | add_fixed_insn (NOP_INSN); | |
1483 | insert_into_history (0, 1, NOP_INSN); | |
1484 | } | |
1485 | ||
71400594 RS |
1486 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1487 | the idea is to make it obvious at a glance that each errata is | |
1488 | included. */ | |
1489 | ||
1490 | static void | |
1491 | init_vr4120_conflicts (void) | |
1492 | { | |
1493 | #define CONFLICT(FIRST, SECOND) \ | |
1494 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1495 | ||
1496 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1497 | CONFLICT (MACC, DIV); | |
1498 | CONFLICT (DMACC, DIV); | |
1499 | ||
1500 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1501 | CONFLICT (DMULT, DMULT); | |
1502 | CONFLICT (DMULT, DMACC); | |
1503 | CONFLICT (DMACC, DMULT); | |
1504 | CONFLICT (DMACC, DMACC); | |
1505 | ||
1506 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1507 | CONFLICT (MACC, MTHILO); | |
1508 | CONFLICT (DMACC, MTHILO); | |
1509 | ||
1510 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1511 | instruction is executed immediately after a MACC or DMACC | |
1512 | instruction, the result of [either instruction] is incorrect." */ | |
1513 | CONFLICT (MACC, MULT); | |
1514 | CONFLICT (MACC, DMULT); | |
1515 | CONFLICT (DMACC, MULT); | |
1516 | CONFLICT (DMACC, DMULT); | |
1517 | ||
1518 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1519 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1520 | DDIV or DDIVU instruction, the result of the MACC or | |
1521 | DMACC instruction is incorrect.". */ | |
1522 | CONFLICT (DMULT, MACC); | |
1523 | CONFLICT (DMULT, DMACC); | |
1524 | CONFLICT (DIV, MACC); | |
1525 | CONFLICT (DIV, DMACC); | |
1526 | ||
1527 | #undef CONFLICT | |
1528 | } | |
1529 | ||
707bfff6 TS |
1530 | struct regname { |
1531 | const char *name; | |
1532 | unsigned int num; | |
1533 | }; | |
1534 | ||
1535 | #define RTYPE_MASK 0x1ff00 | |
1536 | #define RTYPE_NUM 0x00100 | |
1537 | #define RTYPE_FPU 0x00200 | |
1538 | #define RTYPE_FCC 0x00400 | |
1539 | #define RTYPE_VEC 0x00800 | |
1540 | #define RTYPE_GP 0x01000 | |
1541 | #define RTYPE_CP0 0x02000 | |
1542 | #define RTYPE_PC 0x04000 | |
1543 | #define RTYPE_ACC 0x08000 | |
1544 | #define RTYPE_CCC 0x10000 | |
1545 | #define RNUM_MASK 0x000ff | |
1546 | #define RWARN 0x80000 | |
1547 | ||
1548 | #define GENERIC_REGISTER_NUMBERS \ | |
1549 | {"$0", RTYPE_NUM | 0}, \ | |
1550 | {"$1", RTYPE_NUM | 1}, \ | |
1551 | {"$2", RTYPE_NUM | 2}, \ | |
1552 | {"$3", RTYPE_NUM | 3}, \ | |
1553 | {"$4", RTYPE_NUM | 4}, \ | |
1554 | {"$5", RTYPE_NUM | 5}, \ | |
1555 | {"$6", RTYPE_NUM | 6}, \ | |
1556 | {"$7", RTYPE_NUM | 7}, \ | |
1557 | {"$8", RTYPE_NUM | 8}, \ | |
1558 | {"$9", RTYPE_NUM | 9}, \ | |
1559 | {"$10", RTYPE_NUM | 10}, \ | |
1560 | {"$11", RTYPE_NUM | 11}, \ | |
1561 | {"$12", RTYPE_NUM | 12}, \ | |
1562 | {"$13", RTYPE_NUM | 13}, \ | |
1563 | {"$14", RTYPE_NUM | 14}, \ | |
1564 | {"$15", RTYPE_NUM | 15}, \ | |
1565 | {"$16", RTYPE_NUM | 16}, \ | |
1566 | {"$17", RTYPE_NUM | 17}, \ | |
1567 | {"$18", RTYPE_NUM | 18}, \ | |
1568 | {"$19", RTYPE_NUM | 19}, \ | |
1569 | {"$20", RTYPE_NUM | 20}, \ | |
1570 | {"$21", RTYPE_NUM | 21}, \ | |
1571 | {"$22", RTYPE_NUM | 22}, \ | |
1572 | {"$23", RTYPE_NUM | 23}, \ | |
1573 | {"$24", RTYPE_NUM | 24}, \ | |
1574 | {"$25", RTYPE_NUM | 25}, \ | |
1575 | {"$26", RTYPE_NUM | 26}, \ | |
1576 | {"$27", RTYPE_NUM | 27}, \ | |
1577 | {"$28", RTYPE_NUM | 28}, \ | |
1578 | {"$29", RTYPE_NUM | 29}, \ | |
1579 | {"$30", RTYPE_NUM | 30}, \ | |
1580 | {"$31", RTYPE_NUM | 31} | |
1581 | ||
1582 | #define FPU_REGISTER_NAMES \ | |
1583 | {"$f0", RTYPE_FPU | 0}, \ | |
1584 | {"$f1", RTYPE_FPU | 1}, \ | |
1585 | {"$f2", RTYPE_FPU | 2}, \ | |
1586 | {"$f3", RTYPE_FPU | 3}, \ | |
1587 | {"$f4", RTYPE_FPU | 4}, \ | |
1588 | {"$f5", RTYPE_FPU | 5}, \ | |
1589 | {"$f6", RTYPE_FPU | 6}, \ | |
1590 | {"$f7", RTYPE_FPU | 7}, \ | |
1591 | {"$f8", RTYPE_FPU | 8}, \ | |
1592 | {"$f9", RTYPE_FPU | 9}, \ | |
1593 | {"$f10", RTYPE_FPU | 10}, \ | |
1594 | {"$f11", RTYPE_FPU | 11}, \ | |
1595 | {"$f12", RTYPE_FPU | 12}, \ | |
1596 | {"$f13", RTYPE_FPU | 13}, \ | |
1597 | {"$f14", RTYPE_FPU | 14}, \ | |
1598 | {"$f15", RTYPE_FPU | 15}, \ | |
1599 | {"$f16", RTYPE_FPU | 16}, \ | |
1600 | {"$f17", RTYPE_FPU | 17}, \ | |
1601 | {"$f18", RTYPE_FPU | 18}, \ | |
1602 | {"$f19", RTYPE_FPU | 19}, \ | |
1603 | {"$f20", RTYPE_FPU | 20}, \ | |
1604 | {"$f21", RTYPE_FPU | 21}, \ | |
1605 | {"$f22", RTYPE_FPU | 22}, \ | |
1606 | {"$f23", RTYPE_FPU | 23}, \ | |
1607 | {"$f24", RTYPE_FPU | 24}, \ | |
1608 | {"$f25", RTYPE_FPU | 25}, \ | |
1609 | {"$f26", RTYPE_FPU | 26}, \ | |
1610 | {"$f27", RTYPE_FPU | 27}, \ | |
1611 | {"$f28", RTYPE_FPU | 28}, \ | |
1612 | {"$f29", RTYPE_FPU | 29}, \ | |
1613 | {"$f30", RTYPE_FPU | 30}, \ | |
1614 | {"$f31", RTYPE_FPU | 31} | |
1615 | ||
1616 | #define FPU_CONDITION_CODE_NAMES \ | |
1617 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1618 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1619 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1620 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1621 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1622 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1623 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1624 | {"$fcc7", RTYPE_FCC | 7} | |
1625 | ||
1626 | #define COPROC_CONDITION_CODE_NAMES \ | |
1627 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1628 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1629 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1630 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1631 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1632 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1633 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1634 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1635 | ||
1636 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1637 | {"$a4", RTYPE_GP | 8}, \ | |
1638 | {"$a5", RTYPE_GP | 9}, \ | |
1639 | {"$a6", RTYPE_GP | 10}, \ | |
1640 | {"$a7", RTYPE_GP | 11}, \ | |
1641 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1642 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1643 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1644 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1645 | {"$t0", RTYPE_GP | 12}, \ | |
1646 | {"$t1", RTYPE_GP | 13}, \ | |
1647 | {"$t2", RTYPE_GP | 14}, \ | |
1648 | {"$t3", RTYPE_GP | 15} | |
1649 | ||
1650 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1651 | {"$t0", RTYPE_GP | 8}, \ | |
1652 | {"$t1", RTYPE_GP | 9}, \ | |
1653 | {"$t2", RTYPE_GP | 10}, \ | |
1654 | {"$t3", RTYPE_GP | 11}, \ | |
1655 | {"$t4", RTYPE_GP | 12}, \ | |
1656 | {"$t5", RTYPE_GP | 13}, \ | |
1657 | {"$t6", RTYPE_GP | 14}, \ | |
1658 | {"$t7", RTYPE_GP | 15}, \ | |
1659 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1660 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1661 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1662 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
1663 | ||
1664 | /* Remaining symbolic register names */ | |
1665 | #define SYMBOLIC_REGISTER_NAMES \ | |
1666 | {"$zero", RTYPE_GP | 0}, \ | |
1667 | {"$at", RTYPE_GP | 1}, \ | |
1668 | {"$AT", RTYPE_GP | 1}, \ | |
1669 | {"$v0", RTYPE_GP | 2}, \ | |
1670 | {"$v1", RTYPE_GP | 3}, \ | |
1671 | {"$a0", RTYPE_GP | 4}, \ | |
1672 | {"$a1", RTYPE_GP | 5}, \ | |
1673 | {"$a2", RTYPE_GP | 6}, \ | |
1674 | {"$a3", RTYPE_GP | 7}, \ | |
1675 | {"$s0", RTYPE_GP | 16}, \ | |
1676 | {"$s1", RTYPE_GP | 17}, \ | |
1677 | {"$s2", RTYPE_GP | 18}, \ | |
1678 | {"$s3", RTYPE_GP | 19}, \ | |
1679 | {"$s4", RTYPE_GP | 20}, \ | |
1680 | {"$s5", RTYPE_GP | 21}, \ | |
1681 | {"$s6", RTYPE_GP | 22}, \ | |
1682 | {"$s7", RTYPE_GP | 23}, \ | |
1683 | {"$t8", RTYPE_GP | 24}, \ | |
1684 | {"$t9", RTYPE_GP | 25}, \ | |
1685 | {"$k0", RTYPE_GP | 26}, \ | |
1686 | {"$kt0", RTYPE_GP | 26}, \ | |
1687 | {"$k1", RTYPE_GP | 27}, \ | |
1688 | {"$kt1", RTYPE_GP | 27}, \ | |
1689 | {"$gp", RTYPE_GP | 28}, \ | |
1690 | {"$sp", RTYPE_GP | 29}, \ | |
1691 | {"$s8", RTYPE_GP | 30}, \ | |
1692 | {"$fp", RTYPE_GP | 30}, \ | |
1693 | {"$ra", RTYPE_GP | 31} | |
1694 | ||
1695 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
1696 | {"$pc", RTYPE_PC | 0} | |
1697 | ||
1698 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
1699 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
1700 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
1701 | {"$v2", RTYPE_VEC | 2}, \ | |
1702 | {"$v3", RTYPE_VEC | 3}, \ | |
1703 | {"$v4", RTYPE_VEC | 4}, \ | |
1704 | {"$v5", RTYPE_VEC | 5}, \ | |
1705 | {"$v6", RTYPE_VEC | 6}, \ | |
1706 | {"$v7", RTYPE_VEC | 7}, \ | |
1707 | {"$v8", RTYPE_VEC | 8}, \ | |
1708 | {"$v9", RTYPE_VEC | 9}, \ | |
1709 | {"$v10", RTYPE_VEC | 10}, \ | |
1710 | {"$v11", RTYPE_VEC | 11}, \ | |
1711 | {"$v12", RTYPE_VEC | 12}, \ | |
1712 | {"$v13", RTYPE_VEC | 13}, \ | |
1713 | {"$v14", RTYPE_VEC | 14}, \ | |
1714 | {"$v15", RTYPE_VEC | 15}, \ | |
1715 | {"$v16", RTYPE_VEC | 16}, \ | |
1716 | {"$v17", RTYPE_VEC | 17}, \ | |
1717 | {"$v18", RTYPE_VEC | 18}, \ | |
1718 | {"$v19", RTYPE_VEC | 19}, \ | |
1719 | {"$v20", RTYPE_VEC | 20}, \ | |
1720 | {"$v21", RTYPE_VEC | 21}, \ | |
1721 | {"$v22", RTYPE_VEC | 22}, \ | |
1722 | {"$v23", RTYPE_VEC | 23}, \ | |
1723 | {"$v24", RTYPE_VEC | 24}, \ | |
1724 | {"$v25", RTYPE_VEC | 25}, \ | |
1725 | {"$v26", RTYPE_VEC | 26}, \ | |
1726 | {"$v27", RTYPE_VEC | 27}, \ | |
1727 | {"$v28", RTYPE_VEC | 28}, \ | |
1728 | {"$v29", RTYPE_VEC | 29}, \ | |
1729 | {"$v30", RTYPE_VEC | 30}, \ | |
1730 | {"$v31", RTYPE_VEC | 31} | |
1731 | ||
1732 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
1733 | {"$ac0", RTYPE_ACC | 0}, \ | |
1734 | {"$ac1", RTYPE_ACC | 1}, \ | |
1735 | {"$ac2", RTYPE_ACC | 2}, \ | |
1736 | {"$ac3", RTYPE_ACC | 3} | |
1737 | ||
1738 | static const struct regname reg_names[] = { | |
1739 | GENERIC_REGISTER_NUMBERS, | |
1740 | FPU_REGISTER_NAMES, | |
1741 | FPU_CONDITION_CODE_NAMES, | |
1742 | COPROC_CONDITION_CODE_NAMES, | |
1743 | ||
1744 | /* The $txx registers depends on the abi, | |
1745 | these will be added later into the symbol table from | |
1746 | one of the tables below once mips_abi is set after | |
1747 | parsing of arguments from the command line. */ | |
1748 | SYMBOLIC_REGISTER_NAMES, | |
1749 | ||
1750 | MIPS16_SPECIAL_REGISTER_NAMES, | |
1751 | MDMX_VECTOR_REGISTER_NAMES, | |
1752 | MIPS_DSP_ACCUMULATOR_NAMES, | |
1753 | {0, 0} | |
1754 | }; | |
1755 | ||
1756 | static const struct regname reg_names_o32[] = { | |
1757 | O32_SYMBOLIC_REGISTER_NAMES, | |
1758 | {0, 0} | |
1759 | }; | |
1760 | ||
1761 | static const struct regname reg_names_n32n64[] = { | |
1762 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
1763 | {0, 0} | |
1764 | }; | |
1765 | ||
1766 | static int | |
1767 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
1768 | { | |
1769 | symbolS *symbolP; | |
1770 | char *e; | |
1771 | char save_c; | |
1772 | int reg = -1; | |
1773 | ||
1774 | /* Find end of name. */ | |
1775 | e = *s; | |
1776 | if (is_name_beginner (*e)) | |
1777 | ++e; | |
1778 | while (is_part_of_name (*e)) | |
1779 | ++e; | |
1780 | ||
1781 | /* Terminate name. */ | |
1782 | save_c = *e; | |
1783 | *e = '\0'; | |
1784 | ||
1785 | /* Look for a register symbol. */ | |
1786 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
1787 | { | |
1788 | int r = S_GET_VALUE (symbolP); | |
1789 | if (r & types) | |
1790 | reg = r & RNUM_MASK; | |
1791 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
1792 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
1793 | reg = (r & RNUM_MASK) - 2; | |
1794 | } | |
1795 | /* Else see if this is a register defined in an itbl entry. */ | |
1796 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
1797 | { | |
1798 | char *n = *s; | |
1799 | unsigned long r; | |
1800 | ||
1801 | if (*n == '$') | |
1802 | ++n; | |
1803 | if (itbl_get_reg_val (n, &r)) | |
1804 | reg = r & RNUM_MASK; | |
1805 | } | |
1806 | ||
1807 | /* Advance to next token if a register was recognised. */ | |
1808 | if (reg >= 0) | |
1809 | *s = e; | |
1810 | else if (types & RWARN) | |
20203fb9 | 1811 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
1812 | |
1813 | *e = save_c; | |
1814 | if (regnop) | |
1815 | *regnop = reg; | |
1816 | return reg >= 0; | |
1817 | } | |
1818 | ||
037b32b9 | 1819 | /* Return TRUE if opcode MO is valid on the currently selected ISA and |
f79e2745 | 1820 | architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ |
037b32b9 AN |
1821 | |
1822 | static bfd_boolean | |
f79e2745 | 1823 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
1824 | { |
1825 | int isa = mips_opts.isa; | |
1826 | int fp_s, fp_d; | |
1827 | ||
1828 | if (mips_opts.ase_mdmx) | |
1829 | isa |= INSN_MDMX; | |
1830 | if (mips_opts.ase_dsp) | |
1831 | isa |= INSN_DSP; | |
1832 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
1833 | isa |= INSN_DSP64; | |
1834 | if (mips_opts.ase_dspr2) | |
1835 | isa |= INSN_DSPR2; | |
1836 | if (mips_opts.ase_mt) | |
1837 | isa |= INSN_MT; | |
1838 | if (mips_opts.ase_mips3d) | |
1839 | isa |= INSN_MIPS3D; | |
1840 | if (mips_opts.ase_smartmips) | |
1841 | isa |= INSN_SMARTMIPS; | |
1842 | ||
b19e8a9b AN |
1843 | /* Don't accept instructions based on the ISA if the CPU does not implement |
1844 | all the coprocessor insns. */ | |
1845 | if (NO_ISA_COP (mips_opts.arch) | |
1846 | && COP_INSN (mo->pinfo)) | |
1847 | isa = 0; | |
1848 | ||
037b32b9 AN |
1849 | if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch)) |
1850 | return FALSE; | |
1851 | ||
1852 | /* Check whether the instruction or macro requires single-precision or | |
1853 | double-precision floating-point support. Note that this information is | |
1854 | stored differently in the opcode table for insns and macros. */ | |
1855 | if (mo->pinfo == INSN_MACRO) | |
1856 | { | |
1857 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
1858 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
1859 | } | |
1860 | else | |
1861 | { | |
1862 | fp_s = mo->pinfo & FP_S; | |
1863 | fp_d = mo->pinfo & FP_D; | |
1864 | } | |
1865 | ||
1866 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
1867 | return FALSE; | |
1868 | ||
1869 | if (fp_s && mips_opts.soft_float) | |
1870 | return FALSE; | |
1871 | ||
1872 | return TRUE; | |
1873 | } | |
1874 | ||
1875 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
1876 | selected ISA and architecture. */ | |
1877 | ||
1878 | static bfd_boolean | |
1879 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
1880 | { | |
1881 | return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE; | |
1882 | } | |
1883 | ||
707bfff6 TS |
1884 | /* This function is called once, at assembler startup time. It should set up |
1885 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 1886 | |
252b5132 | 1887 | void |
17a2f251 | 1888 | md_begin (void) |
252b5132 | 1889 | { |
3994f87e | 1890 | const char *retval = NULL; |
156c2f8b | 1891 | int i = 0; |
252b5132 | 1892 | int broken = 0; |
1f25f5d3 | 1893 | |
0a44bf69 RS |
1894 | if (mips_pic != NO_PIC) |
1895 | { | |
1896 | if (g_switch_seen && g_switch_value != 0) | |
1897 | as_bad (_("-G may not be used in position-independent code")); | |
1898 | g_switch_value = 0; | |
1899 | } | |
1900 | ||
fef14a42 | 1901 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1902 | as_warn (_("Could not set architecture and machine")); |
1903 | ||
252b5132 RH |
1904 | op_hash = hash_new (); |
1905 | ||
1906 | for (i = 0; i < NUMOPCODES;) | |
1907 | { | |
1908 | const char *name = mips_opcodes[i].name; | |
1909 | ||
17a2f251 | 1910 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1911 | if (retval != NULL) |
1912 | { | |
1913 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1914 | mips_opcodes[i].name, retval); | |
1915 | /* Probably a memory allocation problem? Give up now. */ | |
1916 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1917 | } | |
1918 | do | |
1919 | { | |
1920 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1921 | { | |
1922 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1923 | broken = 1; | |
1e915849 RS |
1924 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1925 | { | |
1926 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
1927 | if (mips_fix_loongson2f_nop) |
1928 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
1929 | nop_insn.fixed_p = 1; |
1930 | } | |
252b5132 RH |
1931 | } |
1932 | ++i; | |
1933 | } | |
1934 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1935 | } | |
1936 | ||
1937 | mips16_op_hash = hash_new (); | |
1938 | ||
1939 | i = 0; | |
1940 | while (i < bfd_mips16_num_opcodes) | |
1941 | { | |
1942 | const char *name = mips16_opcodes[i].name; | |
1943 | ||
17a2f251 | 1944 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1945 | if (retval != NULL) |
1946 | as_fatal (_("internal: can't hash `%s': %s"), | |
1947 | mips16_opcodes[i].name, retval); | |
1948 | do | |
1949 | { | |
1950 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1951 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1952 | != mips16_opcodes[i].match)) | |
1953 | { | |
1954 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1955 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1956 | broken = 1; | |
1957 | } | |
1e915849 RS |
1958 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1959 | { | |
1960 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1961 | mips16_nop_insn.fixed_p = 1; | |
1962 | } | |
252b5132 RH |
1963 | ++i; |
1964 | } | |
1965 | while (i < bfd_mips16_num_opcodes | |
1966 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1967 | } | |
1968 | ||
1969 | if (broken) | |
1970 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1971 | ||
1972 | /* We add all the general register names to the symbol table. This | |
1973 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
1974 | for (i = 0; reg_names[i].name; i++) |
1975 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 1976 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
1977 | &zero_address_frag)); |
1978 | if (HAVE_NEWABI) | |
1979 | for (i = 0; reg_names_n32n64[i].name; i++) | |
1980 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 1981 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 1982 | &zero_address_frag)); |
707bfff6 TS |
1983 | else |
1984 | for (i = 0; reg_names_o32[i].name; i++) | |
1985 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 1986 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 1987 | &zero_address_frag)); |
6047c971 | 1988 | |
7d10b47d | 1989 | mips_no_prev_insn (); |
252b5132 RH |
1990 | |
1991 | mips_gprmask = 0; | |
1992 | mips_cprmask[0] = 0; | |
1993 | mips_cprmask[1] = 0; | |
1994 | mips_cprmask[2] = 0; | |
1995 | mips_cprmask[3] = 0; | |
1996 | ||
1997 | /* set the default alignment for the text section (2**2) */ | |
1998 | record_alignment (text_section, 2); | |
1999 | ||
4d0d148d | 2000 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2001 | |
707bfff6 | 2002 | #ifdef OBJ_ELF |
f43abd2b | 2003 | if (IS_ELF) |
252b5132 | 2004 | { |
0a44bf69 RS |
2005 | /* On a native system other than VxWorks, sections must be aligned |
2006 | to 16 byte boundaries. When configured for an embedded ELF | |
2007 | target, we don't bother. */ | |
c41e87e3 CF |
2008 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
2009 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
2010 | { |
2011 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2012 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2013 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2014 | } | |
2015 | ||
2016 | /* Create a .reginfo section for register masks and a .mdebug | |
2017 | section for debugging information. */ | |
2018 | { | |
2019 | segT seg; | |
2020 | subsegT subseg; | |
2021 | flagword flags; | |
2022 | segT sec; | |
2023 | ||
2024 | seg = now_seg; | |
2025 | subseg = now_subseg; | |
2026 | ||
2027 | /* The ABI says this section should be loaded so that the | |
2028 | running program can access it. However, we don't load it | |
2029 | if we are configured for an embedded target */ | |
2030 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2031 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2032 | flags |= SEC_ALLOC | SEC_LOAD; |
2033 | ||
316f5878 | 2034 | if (mips_abi != N64_ABI) |
252b5132 RH |
2035 | { |
2036 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2037 | ||
195325d2 TS |
2038 | bfd_set_section_flags (stdoutput, sec, flags); |
2039 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2040 | |
252b5132 | 2041 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2042 | } |
2043 | else | |
2044 | { | |
2045 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2046 | .reginfo section. */ | |
2047 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2048 | bfd_set_section_flags (stdoutput, sec, flags); |
2049 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2050 | |
252b5132 RH |
2051 | /* Set up the option header. */ |
2052 | { | |
2053 | Elf_Internal_Options opthdr; | |
2054 | char *f; | |
2055 | ||
2056 | opthdr.kind = ODK_REGINFO; | |
2057 | opthdr.size = (sizeof (Elf_External_Options) | |
2058 | + sizeof (Elf64_External_RegInfo)); | |
2059 | opthdr.section = 0; | |
2060 | opthdr.info = 0; | |
2061 | f = frag_more (sizeof (Elf_External_Options)); | |
2062 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2063 | (Elf_External_Options *) f); | |
2064 | ||
2065 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2066 | } | |
252b5132 RH |
2067 | } |
2068 | ||
2069 | if (ECOFF_DEBUGGING) | |
2070 | { | |
2071 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2072 | (void) bfd_set_section_flags (stdoutput, sec, | |
2073 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2074 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2075 | } | |
f43abd2b | 2076 | else if (mips_flag_pdr) |
ecb4347a DJ |
2077 | { |
2078 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2079 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2080 | SEC_READONLY | SEC_RELOC | |
2081 | | SEC_DEBUGGING); | |
2082 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2083 | } | |
252b5132 RH |
2084 | |
2085 | subseg_set (seg, subseg); | |
2086 | } | |
2087 | } | |
707bfff6 | 2088 | #endif /* OBJ_ELF */ |
252b5132 RH |
2089 | |
2090 | if (! ECOFF_DEBUGGING) | |
2091 | md_obj_begin (); | |
71400594 RS |
2092 | |
2093 | if (mips_fix_vr4120) | |
2094 | init_vr4120_conflicts (); | |
252b5132 RH |
2095 | } |
2096 | ||
2097 | void | |
17a2f251 | 2098 | md_mips_end (void) |
252b5132 RH |
2099 | { |
2100 | if (! ECOFF_DEBUGGING) | |
2101 | md_obj_end (); | |
2102 | } | |
2103 | ||
2104 | void | |
17a2f251 | 2105 | md_assemble (char *str) |
252b5132 RH |
2106 | { |
2107 | struct mips_cl_insn insn; | |
f6688943 TS |
2108 | bfd_reloc_code_real_type unused_reloc[3] |
2109 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2110 | |
2111 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2112 | imm2_expr.X_op = O_absent; |
252b5132 | 2113 | offset_expr.X_op = O_absent; |
f6688943 TS |
2114 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2115 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2116 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2117 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2118 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2119 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2120 | |
2121 | if (mips_opts.mips16) | |
2122 | mips16_ip (str, &insn); | |
2123 | else | |
2124 | { | |
2125 | mips_ip (str, &insn); | |
beae10d5 KH |
2126 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2127 | str, insn.insn_opcode)); | |
252b5132 RH |
2128 | } |
2129 | ||
2130 | if (insn_error) | |
2131 | { | |
2132 | as_bad ("%s `%s'", insn_error, str); | |
2133 | return; | |
2134 | } | |
2135 | ||
2136 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
2137 | { | |
584892a6 | 2138 | macro_start (); |
252b5132 RH |
2139 | if (mips_opts.mips16) |
2140 | mips16_macro (&insn); | |
2141 | else | |
2142 | macro (&insn); | |
584892a6 | 2143 | macro_end (); |
252b5132 RH |
2144 | } |
2145 | else | |
2146 | { | |
2147 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 2148 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 2149 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 2150 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 2151 | else |
4d7206a2 | 2152 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
2153 | } |
2154 | } | |
2155 | ||
738e5348 RS |
2156 | /* Convenience functions for abstracting away the differences between |
2157 | MIPS16 and non-MIPS16 relocations. */ | |
2158 | ||
2159 | static inline bfd_boolean | |
2160 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2161 | { | |
2162 | switch (reloc) | |
2163 | { | |
2164 | case BFD_RELOC_MIPS16_JMP: | |
2165 | case BFD_RELOC_MIPS16_GPREL: | |
2166 | case BFD_RELOC_MIPS16_GOT16: | |
2167 | case BFD_RELOC_MIPS16_CALL16: | |
2168 | case BFD_RELOC_MIPS16_HI16_S: | |
2169 | case BFD_RELOC_MIPS16_HI16: | |
2170 | case BFD_RELOC_MIPS16_LO16: | |
2171 | return TRUE; | |
2172 | ||
2173 | default: | |
2174 | return FALSE; | |
2175 | } | |
2176 | } | |
2177 | ||
2178 | static inline bfd_boolean | |
2179 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2180 | { | |
2181 | return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16; | |
2182 | } | |
2183 | ||
2184 | static inline bfd_boolean | |
2185 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2186 | { | |
2187 | return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S; | |
2188 | } | |
2189 | ||
2190 | static inline bfd_boolean | |
2191 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2192 | { | |
2193 | return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16; | |
2194 | } | |
2195 | ||
5919d012 | 2196 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2197 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2198 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2199 | |
2200 | static inline bfd_boolean | |
17a2f251 | 2201 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2202 | { |
3b91255e | 2203 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2204 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2205 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2206 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2207 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2208 | } | |
2209 | ||
2210 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2211 | reloc_needs_lo_p. */ | |
2212 | ||
2213 | static inline bfd_reloc_code_real_type | |
2214 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2215 | { | |
2216 | return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16; | |
5919d012 RS |
2217 | } |
2218 | ||
2219 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2220 | relocation. */ | |
2221 | ||
2222 | static inline bfd_boolean | |
17a2f251 | 2223 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2224 | { |
2225 | return (fixp->fx_next != NULL | |
738e5348 | 2226 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2227 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2228 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2229 | } | |
2230 | ||
252b5132 RH |
2231 | /* See whether instruction IP reads register REG. CLASS is the type |
2232 | of register. */ | |
2233 | ||
2234 | static int | |
71400594 | 2235 | insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg, |
96d56e9f | 2236 | enum mips_regclass regclass) |
252b5132 | 2237 | { |
96d56e9f | 2238 | if (regclass == MIPS16_REG) |
252b5132 | 2239 | { |
9c2799c2 | 2240 | gas_assert (mips_opts.mips16); |
252b5132 | 2241 | reg = mips16_to_32_reg_map[reg]; |
96d56e9f | 2242 | regclass = MIPS_GR_REG; |
252b5132 RH |
2243 | } |
2244 | ||
85b51719 | 2245 | /* Don't report on general register ZERO, since it never changes. */ |
96d56e9f | 2246 | if (regclass == MIPS_GR_REG && reg == ZERO) |
252b5132 RH |
2247 | return 0; |
2248 | ||
96d56e9f | 2249 | if (regclass == MIPS_FP_REG) |
252b5132 | 2250 | { |
9c2799c2 | 2251 | gas_assert (! mips_opts.mips16); |
252b5132 RH |
2252 | /* If we are called with either $f0 or $f1, we must check $f0. |
2253 | This is not optimal, because it will introduce an unnecessary | |
2254 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
2255 | need to distinguish reading both $f0 and $f1 or just one of | |
2256 | them. Note that we don't have to check the other way, | |
2257 | because there is no instruction that sets both $f0 and $f1 | |
2258 | and requires a delay. */ | |
2259 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 2260 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
2261 | == (reg &~ (unsigned) 1))) |
2262 | return 1; | |
2263 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 2264 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
2265 | == (reg &~ (unsigned) 1))) |
2266 | return 1; | |
2267 | } | |
2268 | else if (! mips_opts.mips16) | |
2269 | { | |
2270 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 2271 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
2272 | return 1; |
2273 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 2274 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 RH |
2275 | return 1; |
2276 | } | |
2277 | else | |
2278 | { | |
2279 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 2280 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
2281 | return 1; |
2282 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 2283 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
2284 | return 1; |
2285 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2286 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
2287 | == reg)) |
2288 | return 1; | |
2289 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
2290 | return 1; | |
2291 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
2292 | return 1; | |
2293 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
2294 | return 1; | |
2295 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 2296 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
2297 | return 1; |
2298 | } | |
2299 | ||
2300 | return 0; | |
2301 | } | |
2302 | ||
2303 | /* This function returns true if modifying a register requires a | |
2304 | delay. */ | |
2305 | ||
2306 | static int | |
17a2f251 | 2307 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2308 | { |
2309 | unsigned long prev_pinfo; | |
2310 | ||
47e39b9d | 2311 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2312 | if (! mips_opts.noreorder |
81912461 ILT |
2313 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2314 | && ! gpr_interlocks) | |
2315 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2316 | && ! cop_interlocks))) | |
252b5132 | 2317 | { |
81912461 ILT |
2318 | /* A load from a coprocessor or from memory. All load delays |
2319 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2320 | /* Itbl support may require additional care here. */ |
252b5132 | 2321 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 2322 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
2323 | return 1; |
2324 | } | |
2325 | ||
2326 | return 0; | |
2327 | } | |
2328 | ||
404a8071 RS |
2329 | /* Move all labels in insn_labels to the current insertion point. */ |
2330 | ||
2331 | static void | |
2332 | mips_move_labels (void) | |
2333 | { | |
a8dbcb85 | 2334 | segment_info_type *si = seg_info (now_seg); |
404a8071 RS |
2335 | struct insn_label_list *l; |
2336 | valueT val; | |
2337 | ||
a8dbcb85 | 2338 | for (l = si->label_list; l != NULL; l = l->next) |
404a8071 | 2339 | { |
9c2799c2 | 2340 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
2341 | symbol_set_frag (l->label, frag_now); |
2342 | val = (valueT) frag_now_fix (); | |
2343 | /* mips16 text labels are stored as odd. */ | |
2344 | if (mips_opts.mips16) | |
2345 | ++val; | |
2346 | S_SET_VALUE (l->label, val); | |
2347 | } | |
2348 | } | |
2349 | ||
5f0fe04b TS |
2350 | static bfd_boolean |
2351 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2352 | { | |
2353 | bfd_boolean linkonce = FALSE; | |
2354 | segT symseg = S_GET_SEGMENT (sym); | |
2355 | ||
2356 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2357 | { | |
2358 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2359 | linkonce = TRUE; | |
2360 | #ifdef OBJ_ELF | |
2361 | /* The GNU toolchain uses an extension for ELF: a section | |
2362 | beginning with the magic string .gnu.linkonce is a | |
2363 | linkonce section. */ | |
2364 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2365 | sizeof ".gnu.linkonce" - 1) == 0) | |
2366 | linkonce = TRUE; | |
2367 | #endif | |
2368 | } | |
2369 | return linkonce; | |
2370 | } | |
2371 | ||
252b5132 RH |
2372 | /* Mark instruction labels in mips16 mode. This permits the linker to |
2373 | handle them specially, such as generating jalx instructions when | |
2374 | needed. We also make them odd for the duration of the assembly, in | |
2375 | order to generate the right sort of code. We will make them even | |
2376 | in the adjust_symtab routine, while leaving them marked. This is | |
2377 | convenient for the debugger and the disassembler. The linker knows | |
2378 | to make them odd again. */ | |
2379 | ||
2380 | static void | |
17a2f251 | 2381 | mips16_mark_labels (void) |
252b5132 | 2382 | { |
a8dbcb85 TS |
2383 | segment_info_type *si = seg_info (now_seg); |
2384 | struct insn_label_list *l; | |
252b5132 | 2385 | |
a8dbcb85 TS |
2386 | if (!mips_opts.mips16) |
2387 | return; | |
2388 | ||
2389 | for (l = si->label_list; l != NULL; l = l->next) | |
2390 | { | |
2391 | symbolS *label = l->label; | |
2392 | ||
2393 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
f43abd2b | 2394 | if (IS_ELF) |
30c09090 | 2395 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); |
252b5132 | 2396 | #endif |
5f0fe04b TS |
2397 | if ((S_GET_VALUE (label) & 1) == 0 |
2398 | /* Don't adjust the address if the label is global or weak, or | |
2399 | in a link-once section, since we'll be emitting symbol reloc | |
2400 | references to it which will be patched up by the linker, and | |
2401 | the final value of the symbol may or may not be MIPS16. */ | |
2402 | && ! S_IS_WEAK (label) | |
2403 | && ! S_IS_EXTERNAL (label) | |
2404 | && ! s_is_linkonce (label, now_seg)) | |
a8dbcb85 | 2405 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); |
252b5132 RH |
2406 | } |
2407 | } | |
2408 | ||
4d7206a2 RS |
2409 | /* End the current frag. Make it a variant frag and record the |
2410 | relaxation info. */ | |
2411 | ||
2412 | static void | |
2413 | relax_close_frag (void) | |
2414 | { | |
584892a6 | 2415 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2416 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2417 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2418 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2419 | ||
2420 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2421 | mips_relax.first_fixup = 0; | |
2422 | } | |
2423 | ||
2424 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2425 | See the comment above RELAX_ENCODE for more details. */ | |
2426 | ||
2427 | static void | |
2428 | relax_start (symbolS *symbol) | |
2429 | { | |
9c2799c2 | 2430 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
2431 | mips_relax.sequence = 1; |
2432 | mips_relax.symbol = symbol; | |
2433 | } | |
2434 | ||
2435 | /* Start generating the second version of a relaxable sequence. | |
2436 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2437 | |
2438 | static void | |
4d7206a2 RS |
2439 | relax_switch (void) |
2440 | { | |
9c2799c2 | 2441 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
2442 | mips_relax.sequence = 2; |
2443 | } | |
2444 | ||
2445 | /* End the current relaxable sequence. */ | |
2446 | ||
2447 | static void | |
2448 | relax_end (void) | |
2449 | { | |
9c2799c2 | 2450 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
2451 | relax_close_frag (); |
2452 | mips_relax.sequence = 0; | |
2453 | } | |
2454 | ||
71400594 RS |
2455 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
2456 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
2457 | by VR4120 errata. */ | |
4d7206a2 | 2458 | |
71400594 RS |
2459 | static unsigned int |
2460 | classify_vr4120_insn (const char *name) | |
252b5132 | 2461 | { |
71400594 RS |
2462 | if (strncmp (name, "macc", 4) == 0) |
2463 | return FIX_VR4120_MACC; | |
2464 | if (strncmp (name, "dmacc", 5) == 0) | |
2465 | return FIX_VR4120_DMACC; | |
2466 | if (strncmp (name, "mult", 4) == 0) | |
2467 | return FIX_VR4120_MULT; | |
2468 | if (strncmp (name, "dmult", 5) == 0) | |
2469 | return FIX_VR4120_DMULT; | |
2470 | if (strstr (name, "div")) | |
2471 | return FIX_VR4120_DIV; | |
2472 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
2473 | return FIX_VR4120_MTHILO; | |
2474 | return NUM_FIX_VR4120_CLASSES; | |
2475 | } | |
252b5132 | 2476 | |
ff239038 CM |
2477 | #define INSN_ERET 0x42000018 |
2478 | #define INSN_DERET 0x4200001f | |
2479 | ||
71400594 RS |
2480 | /* Return the number of instructions that must separate INSN1 and INSN2, |
2481 | where INSN1 is the earlier instruction. Return the worst-case value | |
2482 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 2483 | |
71400594 RS |
2484 | static unsigned int |
2485 | insns_between (const struct mips_cl_insn *insn1, | |
2486 | const struct mips_cl_insn *insn2) | |
2487 | { | |
2488 | unsigned long pinfo1, pinfo2; | |
2489 | ||
2490 | /* This function needs to know which pinfo flags are set for INSN2 | |
2491 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
2492 | the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2 | |
2493 | will have every flag set and INSN2_USES_REG will always return true. */ | |
2494 | pinfo1 = insn1->insn_mo->pinfo; | |
2495 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 2496 | |
71400594 RS |
2497 | #define INSN2_USES_REG(REG, CLASS) \ |
2498 | (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS)) | |
2499 | ||
2500 | /* For most targets, write-after-read dependencies on the HI and LO | |
2501 | registers must be separated by at least two instructions. */ | |
2502 | if (!hilo_interlocks) | |
252b5132 | 2503 | { |
71400594 RS |
2504 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
2505 | return 2; | |
2506 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
2507 | return 2; | |
2508 | } | |
2509 | ||
2510 | /* If we're working around r7000 errata, there must be two instructions | |
2511 | between an mfhi or mflo and any instruction that uses the result. */ | |
2512 | if (mips_7000_hilo_fix | |
2513 | && MF_HILO_INSN (pinfo1) | |
2514 | && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG)) | |
2515 | return 2; | |
2516 | ||
ff239038 CM |
2517 | /* If we're working around 24K errata, one instruction is required |
2518 | if an ERET or DERET is followed by a branch instruction. */ | |
2519 | if (mips_fix_24k) | |
2520 | { | |
2521 | if (insn1->insn_opcode == INSN_ERET | |
2522 | || insn1->insn_opcode == INSN_DERET) | |
2523 | { | |
2524 | if (insn2 == NULL | |
2525 | || insn2->insn_opcode == INSN_ERET | |
2526 | || insn2->insn_opcode == INSN_DERET | |
2527 | || (insn2->insn_mo->pinfo | |
2528 | & (INSN_UNCOND_BRANCH_DELAY | |
2529 | | INSN_COND_BRANCH_DELAY | |
2530 | | INSN_COND_BRANCH_LIKELY)) != 0) | |
2531 | return 1; | |
2532 | } | |
2533 | } | |
2534 | ||
71400594 RS |
2535 | /* If working around VR4120 errata, check for combinations that need |
2536 | a single intervening instruction. */ | |
2537 | if (mips_fix_vr4120) | |
2538 | { | |
2539 | unsigned int class1, class2; | |
252b5132 | 2540 | |
71400594 RS |
2541 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
2542 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 2543 | { |
71400594 RS |
2544 | if (insn2 == NULL) |
2545 | return 1; | |
2546 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
2547 | if (vr4120_conflicts[class1] & (1 << class2)) | |
2548 | return 1; | |
252b5132 | 2549 | } |
71400594 RS |
2550 | } |
2551 | ||
2552 | if (!mips_opts.mips16) | |
2553 | { | |
2554 | /* Check for GPR or coprocessor load delays. All such delays | |
2555 | are on the RT register. */ | |
2556 | /* Itbl support may require additional care here. */ | |
2557 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
2558 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 2559 | { |
71400594 RS |
2560 | know (pinfo1 & INSN_WRITE_GPR_T); |
2561 | if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG)) | |
2562 | return 1; | |
2563 | } | |
2564 | ||
2565 | /* Check for generic coprocessor hazards. | |
2566 | ||
2567 | This case is not handled very well. There is no special | |
2568 | knowledge of CP0 handling, and the coprocessors other than | |
2569 | the floating point unit are not distinguished at all. */ | |
2570 | /* Itbl support may require additional care here. FIXME! | |
2571 | Need to modify this to include knowledge about | |
2572 | user specified delays! */ | |
2573 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
2574 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
2575 | { | |
2576 | /* Handle cases where INSN1 writes to a known general coprocessor | |
2577 | register. There must be a one instruction delay before INSN2 | |
2578 | if INSN2 reads that register, otherwise no delay is needed. */ | |
2579 | if (pinfo1 & INSN_WRITE_FPR_T) | |
252b5132 | 2580 | { |
71400594 RS |
2581 | if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG)) |
2582 | return 1; | |
252b5132 | 2583 | } |
71400594 | 2584 | else if (pinfo1 & INSN_WRITE_FPR_S) |
252b5132 | 2585 | { |
71400594 RS |
2586 | if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG)) |
2587 | return 1; | |
252b5132 RH |
2588 | } |
2589 | else | |
2590 | { | |
71400594 RS |
2591 | /* Read-after-write dependencies on the control registers |
2592 | require a two-instruction gap. */ | |
2593 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
2594 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2595 | return 2; | |
2596 | ||
2597 | /* We don't know exactly what INSN1 does. If INSN2 is | |
2598 | also a coprocessor instruction, assume there must be | |
2599 | a one instruction gap. */ | |
2600 | if (pinfo2 & INSN_COP) | |
2601 | return 1; | |
252b5132 RH |
2602 | } |
2603 | } | |
6b76fefe | 2604 | |
71400594 RS |
2605 | /* Check for read-after-write dependencies on the coprocessor |
2606 | control registers in cases where INSN1 does not need a general | |
2607 | coprocessor delay. This means that INSN1 is a floating point | |
2608 | comparison instruction. */ | |
2609 | /* Itbl support may require additional care here. */ | |
2610 | else if (!cop_interlocks | |
2611 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2612 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2613 | return 1; | |
2614 | } | |
6b76fefe | 2615 | |
71400594 | 2616 | #undef INSN2_USES_REG |
6b76fefe | 2617 | |
71400594 RS |
2618 | return 0; |
2619 | } | |
6b76fefe | 2620 | |
7d8e00cf RS |
2621 | /* Return the number of nops that would be needed to work around the |
2622 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
91d6fa6a | 2623 | the MAX_VR4130_NOPS instructions described by HIST. */ |
7d8e00cf RS |
2624 | |
2625 | static int | |
91d6fa6a | 2626 | nops_for_vr4130 (const struct mips_cl_insn *hist, |
7d8e00cf RS |
2627 | const struct mips_cl_insn *insn) |
2628 | { | |
2629 | int i, j, reg; | |
2630 | ||
2631 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2632 | are not affected by the errata. */ | |
2633 | if (insn != 0 | |
2634 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2635 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2636 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2637 | return 0; | |
2638 | ||
2639 | /* Search for the first MFLO or MFHI. */ | |
2640 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 2641 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
2642 | { |
2643 | /* Extract the destination register. */ | |
2644 | if (mips_opts.mips16) | |
91d6fa6a | 2645 | reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, hist[i])]; |
7d8e00cf | 2646 | else |
91d6fa6a | 2647 | reg = EXTRACT_OPERAND (RD, hist[i]); |
7d8e00cf RS |
2648 | |
2649 | /* No nops are needed if INSN reads that register. */ | |
2650 | if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG)) | |
2651 | return 0; | |
2652 | ||
2653 | /* ...or if any of the intervening instructions do. */ | |
2654 | for (j = 0; j < i; j++) | |
91d6fa6a | 2655 | if (insn_uses_reg (&hist[j], reg, MIPS_GR_REG)) |
7d8e00cf RS |
2656 | return 0; |
2657 | ||
2658 | return MAX_VR4130_NOPS - i; | |
2659 | } | |
2660 | return 0; | |
2661 | } | |
2662 | ||
71400594 | 2663 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a NC |
2664 | immediately followed the MAX_NOPS instructions given by HIST, |
2665 | where HIST[0] is the most recent instruction. If INSN is null, | |
71400594 | 2666 | return the worse-case number of nops for any instruction. */ |
bdaaa2e1 | 2667 | |
71400594 | 2668 | static int |
91d6fa6a | 2669 | nops_for_insn (const struct mips_cl_insn *hist, |
71400594 RS |
2670 | const struct mips_cl_insn *insn) |
2671 | { | |
2672 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2673 | |
71400594 | 2674 | nops = 0; |
7d8e00cf | 2675 | for (i = 0; i < MAX_DELAY_NOPS; i++) |
65b02341 | 2676 | { |
91d6fa6a | 2677 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
2678 | if (tmp_nops > nops) |
2679 | nops = tmp_nops; | |
2680 | } | |
7d8e00cf RS |
2681 | |
2682 | if (mips_fix_vr4130) | |
2683 | { | |
91d6fa6a | 2684 | tmp_nops = nops_for_vr4130 (hist, insn); |
7d8e00cf RS |
2685 | if (tmp_nops > nops) |
2686 | nops = tmp_nops; | |
2687 | } | |
2688 | ||
71400594 RS |
2689 | return nops; |
2690 | } | |
252b5132 | 2691 | |
71400594 | 2692 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 2693 | might be added to HIST. Return the largest number of nops that |
71400594 | 2694 | would be needed after the extended sequence. */ |
252b5132 | 2695 | |
71400594 | 2696 | static int |
91d6fa6a | 2697 | nops_for_sequence (int num_insns, const struct mips_cl_insn *hist, ...) |
71400594 RS |
2698 | { |
2699 | va_list args; | |
2700 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2701 | struct mips_cl_insn *cursor; | |
2702 | int nops; | |
2703 | ||
91d6fa6a | 2704 | va_start (args, hist); |
71400594 | 2705 | cursor = buffer + num_insns; |
91d6fa6a | 2706 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
2707 | while (cursor > buffer) |
2708 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2709 | ||
2710 | nops = nops_for_insn (buffer, NULL); | |
2711 | va_end (args); | |
2712 | return nops; | |
2713 | } | |
252b5132 | 2714 | |
71400594 RS |
2715 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2716 | worst-case delay for the branch target. */ | |
252b5132 | 2717 | |
71400594 | 2718 | static int |
91d6fa6a | 2719 | nops_for_insn_or_target (const struct mips_cl_insn *hist, |
71400594 RS |
2720 | const struct mips_cl_insn *insn) |
2721 | { | |
2722 | int nops, tmp_nops; | |
60b63b72 | 2723 | |
91d6fa6a | 2724 | nops = nops_for_insn (hist, insn); |
71400594 RS |
2725 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY |
2726 | | INSN_COND_BRANCH_DELAY | |
2727 | | INSN_COND_BRANCH_LIKELY)) | |
2728 | { | |
91d6fa6a | 2729 | tmp_nops = nops_for_sequence (2, hist, insn, NOP_INSN); |
71400594 RS |
2730 | if (tmp_nops > nops) |
2731 | nops = tmp_nops; | |
2732 | } | |
2733 | else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH)) | |
2734 | { | |
91d6fa6a | 2735 | tmp_nops = nops_for_sequence (1, hist, insn); |
71400594 RS |
2736 | if (tmp_nops > nops) |
2737 | nops = tmp_nops; | |
2738 | } | |
2739 | return nops; | |
2740 | } | |
2741 | ||
c67a084a NC |
2742 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
2743 | ||
2744 | static void | |
2745 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
2746 | { | |
2747 | if (strcmp (ip->insn_mo->name, "nop") == 0) | |
2748 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
2749 | } | |
2750 | ||
2751 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
2752 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
2753 | ||
2754 | static void | |
2755 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
2756 | { | |
2757 | if (strcmp (ip->insn_mo->name, "j") == 0 | |
2758 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
2759 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
2760 | { | |
2761 | int sreg; | |
2762 | expressionS ep; | |
2763 | ||
2764 | if (! mips_opts.at) | |
2765 | return; | |
2766 | ||
2767 | sreg = EXTRACT_OPERAND (RS, *ip); | |
2768 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) | |
2769 | return; | |
2770 | ||
2771 | ep.X_op = O_constant; | |
2772 | ep.X_add_number = 0xcfff0000; | |
2773 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
2774 | ep.X_add_number = 0xffff; | |
2775 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
2776 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
2777 | } | |
2778 | } | |
2779 | ||
2780 | static void | |
2781 | fix_loongson2f (struct mips_cl_insn * ip) | |
2782 | { | |
2783 | if (mips_fix_loongson2f_nop) | |
2784 | fix_loongson2f_nop (ip); | |
2785 | ||
2786 | if (mips_fix_loongson2f_jump) | |
2787 | fix_loongson2f_jump (ip); | |
2788 | } | |
2789 | ||
71400594 RS |
2790 | /* Output an instruction. IP is the instruction information. |
2791 | ADDRESS_EXPR is an operand of the instruction to be used with | |
2792 | RELOC_TYPE. */ | |
2793 | ||
2794 | static void | |
2795 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
2796 | bfd_reloc_code_real_type *reloc_type) | |
2797 | { | |
3994f87e | 2798 | unsigned long prev_pinfo, pinfo; |
71400594 RS |
2799 | relax_stateT prev_insn_frag_type = 0; |
2800 | bfd_boolean relaxed_branch = FALSE; | |
a8dbcb85 | 2801 | segment_info_type *si = seg_info (now_seg); |
71400594 | 2802 | |
c67a084a NC |
2803 | if (mips_fix_loongson2f) |
2804 | fix_loongson2f (ip); | |
2805 | ||
71400594 RS |
2806 | /* Mark instruction labels in mips16 mode. */ |
2807 | mips16_mark_labels (); | |
2808 | ||
2809 | prev_pinfo = history[0].insn_mo->pinfo; | |
2810 | pinfo = ip->insn_mo->pinfo; | |
2811 | ||
2812 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) | |
2813 | { | |
2814 | /* There are a lot of optimizations we could do that we don't. | |
2815 | In particular, we do not, in general, reorder instructions. | |
2816 | If you use gcc with optimization, it will reorder | |
2817 | instructions and generally do much more optimization then we | |
2818 | do here; repeating all that work in the assembler would only | |
2819 | benefit hand written assembly code, and does not seem worth | |
2820 | it. */ | |
2821 | int nops = (mips_optimize == 0 | |
2822 | ? nops_for_insn (history, NULL) | |
2823 | : nops_for_insn_or_target (history, ip)); | |
2824 | if (nops > 0) | |
252b5132 RH |
2825 | { |
2826 | fragS *old_frag; | |
2827 | unsigned long old_frag_offset; | |
2828 | int i; | |
252b5132 RH |
2829 | |
2830 | old_frag = frag_now; | |
2831 | old_frag_offset = frag_now_fix (); | |
2832 | ||
2833 | for (i = 0; i < nops; i++) | |
2834 | emit_nop (); | |
2835 | ||
2836 | if (listing) | |
2837 | { | |
2838 | listing_prev_line (); | |
2839 | /* We may be at the start of a variant frag. In case we | |
2840 | are, make sure there is enough space for the frag | |
2841 | after the frags created by listing_prev_line. The | |
2842 | argument to frag_grow here must be at least as large | |
2843 | as the argument to all other calls to frag_grow in | |
2844 | this file. We don't have to worry about being in the | |
2845 | middle of a variant frag, because the variants insert | |
2846 | all needed nop instructions themselves. */ | |
2847 | frag_grow (40); | |
2848 | } | |
2849 | ||
404a8071 | 2850 | mips_move_labels (); |
252b5132 RH |
2851 | |
2852 | #ifndef NO_ECOFF_DEBUGGING | |
2853 | if (ECOFF_DEBUGGING) | |
2854 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2855 | #endif | |
2856 | } | |
71400594 RS |
2857 | } |
2858 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
2859 | { | |
2860 | /* Work out how many nops in prev_nop_frag are needed by IP. */ | |
2861 | int nops = nops_for_insn_or_target (history, ip); | |
9c2799c2 | 2862 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 2863 | |
71400594 RS |
2864 | /* Enforce NOPS as a minimum. */ |
2865 | if (nops > prev_nop_frag_required) | |
2866 | prev_nop_frag_required = nops; | |
252b5132 | 2867 | |
71400594 RS |
2868 | if (prev_nop_frag_holds == prev_nop_frag_required) |
2869 | { | |
2870 | /* Settle for the current number of nops. Update the history | |
2871 | accordingly (for the benefit of any future .set reorder code). */ | |
2872 | prev_nop_frag = NULL; | |
2873 | insert_into_history (prev_nop_frag_since, | |
2874 | prev_nop_frag_holds, NOP_INSN); | |
2875 | } | |
2876 | else | |
2877 | { | |
2878 | /* Allow this instruction to replace one of the nops that was | |
2879 | tentatively added to prev_nop_frag. */ | |
2880 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2881 | prev_nop_frag_holds--; | |
2882 | prev_nop_frag_since++; | |
252b5132 RH |
2883 | } |
2884 | } | |
2885 | ||
58e2ea4d MR |
2886 | #ifdef OBJ_ELF |
2887 | /* The value passed to dwarf2_emit_insn is the distance between | |
2888 | the beginning of the current instruction and the address that | |
2889 | should be recorded in the debug tables. For MIPS16 debug info | |
2890 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2891 | address higher by one than the current. */ | |
2892 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2893 | #endif | |
2894 | ||
895921c9 | 2895 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2896 | if (history[0].frag) |
2897 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2898 | |
4d7206a2 | 2899 | if (address_expr |
0b25d3e6 | 2900 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2901 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2902 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2903 | && mips_relax_branch | |
2904 | /* Don't try branch relaxation within .set nomacro, or within | |
2905 | .set noat if we use $at for PIC computations. If it turns | |
2906 | out that the branch was out-of-range, we'll get an error. */ | |
2907 | && !mips_opts.warn_about_macros | |
741fe287 | 2908 | && (mips_opts.at || mips_pic == NO_PIC) |
4a6a3df4 AO |
2909 | && !mips_opts.mips16) |
2910 | { | |
895921c9 | 2911 | relaxed_branch = TRUE; |
1e915849 RS |
2912 | add_relaxed_insn (ip, (relaxed_branch_length |
2913 | (NULL, NULL, | |
2914 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2915 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
2916 | : 0)), 4, | |
2917 | RELAX_BRANCH_ENCODE | |
2918 | (pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2919 | pinfo & INSN_COND_BRANCH_LIKELY, | |
2920 | pinfo & INSN_WRITE_GPR_31, | |
2921 | 0), | |
2922 | address_expr->X_add_symbol, | |
2923 | address_expr->X_add_number); | |
4a6a3df4 AO |
2924 | *reloc_type = BFD_RELOC_UNUSED; |
2925 | } | |
2926 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2927 | { |
2928 | /* We need to set up a variant frag. */ | |
9c2799c2 | 2929 | gas_assert (mips_opts.mips16 && address_expr != NULL); |
1e915849 RS |
2930 | add_relaxed_insn (ip, 4, 0, |
2931 | RELAX_MIPS16_ENCODE | |
2932 | (*reloc_type - BFD_RELOC_UNUSED, | |
2933 | mips16_small, mips16_ext, | |
2934 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2935 | history[0].mips16_absolute_jump_p), | |
2936 | make_expr_symbol (address_expr), 0); | |
252b5132 | 2937 | } |
252b5132 RH |
2938 | else if (mips_opts.mips16 |
2939 | && ! ip->use_extend | |
f6688943 | 2940 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 2941 | { |
b8ee1a6e DU |
2942 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0) |
2943 | /* Make sure there is enough room to swap this instruction with | |
2944 | a following jump instruction. */ | |
2945 | frag_grow (6); | |
1e915849 | 2946 | add_fixed_insn (ip); |
252b5132 RH |
2947 | } |
2948 | else | |
2949 | { | |
2950 | if (mips_opts.mips16 | |
2951 | && mips_opts.noreorder | |
2952 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2953 | as_warn (_("extended instruction in delay slot")); | |
2954 | ||
4d7206a2 RS |
2955 | if (mips_relax.sequence) |
2956 | { | |
2957 | /* If we've reached the end of this frag, turn it into a variant | |
2958 | frag and record the information for the instructions we've | |
2959 | written so far. */ | |
2960 | if (frag_room () < 4) | |
2961 | relax_close_frag (); | |
2962 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2963 | } | |
2964 | ||
584892a6 RS |
2965 | if (mips_relax.sequence != 2) |
2966 | mips_macro_warning.sizes[0] += 4; | |
2967 | if (mips_relax.sequence != 1) | |
2968 | mips_macro_warning.sizes[1] += 4; | |
2969 | ||
1e915849 RS |
2970 | if (mips_opts.mips16) |
2971 | { | |
2972 | ip->fixed_p = 1; | |
2973 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
2974 | } | |
2975 | add_fixed_insn (ip); | |
252b5132 RH |
2976 | } |
2977 | ||
01a3f561 | 2978 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2979 | { |
2980 | if (address_expr->X_op == O_constant) | |
2981 | { | |
f17c130b | 2982 | unsigned int tmp; |
f6688943 TS |
2983 | |
2984 | switch (*reloc_type) | |
252b5132 RH |
2985 | { |
2986 | case BFD_RELOC_32: | |
2987 | ip->insn_opcode |= address_expr->X_add_number; | |
2988 | break; | |
2989 | ||
f6688943 | 2990 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2991 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2992 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2993 | break; |
2994 | ||
2995 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
2996 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
2997 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2998 | break; |
2999 | ||
3000 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
3001 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
3002 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
3003 | break; |
3004 | ||
3005 | case BFD_RELOC_HI16: | |
3006 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
3007 | break; | |
3008 | ||
01a3f561 | 3009 | case BFD_RELOC_UNUSED: |
252b5132 | 3010 | case BFD_RELOC_LO16: |
ed6fb7bd | 3011 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
3012 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
3013 | break; | |
3014 | ||
3015 | case BFD_RELOC_MIPS_JMP: | |
3016 | if ((address_expr->X_add_number & 3) != 0) | |
3017 | as_bad (_("jump to misaligned address (0x%lx)"), | |
3018 | (unsigned long) address_expr->X_add_number); | |
3019 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
3020 | break; | |
3021 | ||
3022 | case BFD_RELOC_MIPS16_JMP: | |
3023 | if ((address_expr->X_add_number & 3) != 0) | |
3024 | as_bad (_("jump to misaligned address (0x%lx)"), | |
3025 | (unsigned long) address_expr->X_add_number); | |
3026 | ip->insn_opcode |= | |
3027 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
3028 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
3029 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
3030 | break; | |
3031 | ||
252b5132 | 3032 | case BFD_RELOC_16_PCREL_S2: |
bad36eac DJ |
3033 | if ((address_expr->X_add_number & 3) != 0) |
3034 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3035 | (unsigned long) address_expr->X_add_number); | |
3036 | if (mips_relax_branch) | |
3037 | goto need_reloc; | |
3038 | if ((address_expr->X_add_number + 0x20000) & ~0x3ffff) | |
3039 | as_bad (_("branch address range overflow (0x%lx)"), | |
3040 | (unsigned long) address_expr->X_add_number); | |
3041 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff; | |
3042 | break; | |
252b5132 RH |
3043 | |
3044 | default: | |
3045 | internalError (); | |
3046 | } | |
3047 | } | |
01a3f561 | 3048 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 3049 | need_reloc: |
4d7206a2 RS |
3050 | { |
3051 | reloc_howto_type *howto; | |
3052 | int i; | |
34ce925e | 3053 | |
4d7206a2 RS |
3054 | /* In a compound relocation, it is the final (outermost) |
3055 | operator that determines the relocated field. */ | |
3056 | for (i = 1; i < 3; i++) | |
3057 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
3058 | break; | |
34ce925e | 3059 | |
4d7206a2 | 3060 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
23fce1e3 NC |
3061 | if (howto == NULL) |
3062 | { | |
3063 | /* To reproduce this failure try assembling gas/testsuites/ | |
3064 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
3065 | assembler. */ | |
3066 | as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]); | |
3067 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); | |
3068 | } | |
3069 | ||
1e915849 RS |
3070 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
3071 | bfd_get_reloc_size (howto), | |
3072 | address_expr, | |
3073 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
3074 | reloc_type[0]); | |
4d7206a2 | 3075 | |
b314ec0e RS |
3076 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ |
3077 | if (reloc_type[0] == BFD_RELOC_MIPS16_JMP | |
3078 | && ip->fixp[0]->fx_addsy) | |
3079 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; | |
3080 | ||
4d7206a2 RS |
3081 | /* These relocations can have an addend that won't fit in |
3082 | 4 octets for 64bit assembly. */ | |
3083 | if (HAVE_64BIT_GPRS | |
3084 | && ! howto->partial_inplace | |
3085 | && (reloc_type[0] == BFD_RELOC_16 | |
3086 | || reloc_type[0] == BFD_RELOC_32 | |
3087 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4d7206a2 RS |
3088 | || reloc_type[0] == BFD_RELOC_GPREL16 |
3089 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
3090 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
3091 | || reloc_type[0] == BFD_RELOC_64 | |
3092 | || reloc_type[0] == BFD_RELOC_CTOR | |
3093 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
3094 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
3095 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
3096 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
3097 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
3098 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
3099 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
738e5348 RS |
3100 | || hi16_reloc_p (reloc_type[0]) |
3101 | || lo16_reloc_p (reloc_type[0]))) | |
1e915849 | 3102 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
3103 | |
3104 | if (mips_relax.sequence) | |
3105 | { | |
3106 | if (mips_relax.first_fixup == 0) | |
1e915849 | 3107 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
3108 | } |
3109 | else if (reloc_needs_lo_p (*reloc_type)) | |
3110 | { | |
3111 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 3112 | |
4d7206a2 RS |
3113 | /* Reuse the last entry if it already has a matching %lo. */ |
3114 | hi_fixup = mips_hi_fixup_list; | |
3115 | if (hi_fixup == 0 | |
3116 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
3117 | { | |
3118 | hi_fixup = ((struct mips_hi_fixup *) | |
3119 | xmalloc (sizeof (struct mips_hi_fixup))); | |
3120 | hi_fixup->next = mips_hi_fixup_list; | |
3121 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 3122 | } |
1e915849 | 3123 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
3124 | hi_fixup->seg = now_seg; |
3125 | } | |
f6688943 | 3126 | |
4d7206a2 RS |
3127 | /* Add fixups for the second and third relocations, if given. |
3128 | Note that the ABI allows the second relocation to be | |
3129 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
3130 | moment we only use RSS_UNDEF, but we could add support | |
3131 | for the others if it ever becomes necessary. */ | |
3132 | for (i = 1; i < 3; i++) | |
3133 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
3134 | { | |
1e915849 RS |
3135 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
3136 | ip->fixp[0]->fx_size, NULL, 0, | |
3137 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
3138 | |
3139 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
3140 | ip->fixp[0]->fx_tcbit = 1; |
3141 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 3142 | } |
252b5132 RH |
3143 | } |
3144 | } | |
1e915849 | 3145 | install_insn (ip); |
252b5132 RH |
3146 | |
3147 | /* Update the register mask information. */ | |
3148 | if (! mips_opts.mips16) | |
3149 | { | |
3150 | if (pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 3151 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 3152 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 3153 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 3154 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 3155 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 3156 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 3157 | mips_gprmask |= 1 << RA; |
252b5132 | 3158 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 3159 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 3160 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 3161 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 3162 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 3163 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 3164 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 3165 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
252b5132 RH |
3166 | if (pinfo & INSN_COP) |
3167 | { | |
bdaaa2e1 KH |
3168 | /* We don't keep enough information to sort these cases out. |
3169 | The itbl support does keep this information however, although | |
3170 | we currently don't support itbl fprmats as part of the cop | |
3171 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
3172 | } |
3173 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 3174 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
3175 | } |
3176 | else | |
3177 | { | |
3178 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 3179 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 3180 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 3181 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 3182 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 3183 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
3184 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
3185 | mips_gprmask |= 1 << TREG; | |
3186 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
3187 | mips_gprmask |= 1 << SP; | |
3188 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
3189 | mips_gprmask |= 1 << RA; | |
3190 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3191 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3192 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 3193 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 3194 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 3195 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
3196 | } |
3197 | ||
4d7206a2 | 3198 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
3199 | { |
3200 | /* Filling the branch delay slot is more complex. We try to | |
3201 | switch the branch with the previous instruction, which we can | |
3202 | do if the previous instruction does not set up a condition | |
3203 | that the branch tests and if the branch is not itself the | |
3204 | target of any branch. */ | |
3205 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3206 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
3207 | { | |
3208 | if (mips_optimize < 2 | |
3209 | /* If we have seen .set volatile or .set nomove, don't | |
3210 | optimize. */ | |
3211 | || mips_opts.nomove != 0 | |
a38419a5 RS |
3212 | /* We can't swap if the previous instruction's position |
3213 | is fixed. */ | |
3214 | || history[0].fixed_p | |
252b5132 RH |
3215 | /* If the previous previous insn was in a .set |
3216 | noreorder, we can't swap. Actually, the MIPS | |
3217 | assembler will swap in this situation. However, gcc | |
3218 | configured -with-gnu-as will generate code like | |
3219 | .set noreorder | |
3220 | lw $4,XXX | |
3221 | .set reorder | |
3222 | INSN | |
3223 | bne $4,$0,foo | |
3224 | in which we can not swap the bne and INSN. If gcc is | |
3225 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 3226 | .set pseudo-ops. */ |
47e39b9d | 3227 | || history[1].noreorder_p |
252b5132 RH |
3228 | /* If the branch is itself the target of a branch, we |
3229 | can not swap. We cheat on this; all we check for is | |
3230 | whether there is a label on this instruction. If | |
3231 | there are any branches to anything other than a | |
3232 | label, users must use .set noreorder. */ | |
a8dbcb85 | 3233 | || si->label_list != NULL |
895921c9 MR |
3234 | /* If the previous instruction is in a variant frag |
3235 | other than this branch's one, we cannot do the swap. | |
3236 | This does not apply to the mips16, which uses variant | |
3237 | frags for different purposes. */ | |
252b5132 | 3238 | || (! mips_opts.mips16 |
895921c9 | 3239 | && prev_insn_frag_type == rs_machine_dependent) |
71400594 RS |
3240 | /* Check for conflicts between the branch and the instructions |
3241 | before the candidate delay slot. */ | |
3242 | || nops_for_insn (history + 1, ip) > 0 | |
3243 | /* Check for conflicts between the swapped sequence and the | |
3244 | target of the branch. */ | |
3245 | || nops_for_sequence (2, history + 1, ip, history) > 0 | |
252b5132 RH |
3246 | /* We do not swap with a trap instruction, since it |
3247 | complicates trap handlers to have the trap | |
3248 | instruction be in a delay slot. */ | |
3249 | || (prev_pinfo & INSN_TRAP) | |
3250 | /* If the branch reads a register that the previous | |
3251 | instruction sets, we can not swap. */ | |
3252 | || (! mips_opts.mips16 | |
3253 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 3254 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
3255 | MIPS_GR_REG)) |
3256 | || (! mips_opts.mips16 | |
3257 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 3258 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 RH |
3259 | MIPS_GR_REG)) |
3260 | || (mips_opts.mips16 | |
3261 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
3262 | && (insn_uses_reg |
3263 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
3264 | MIPS16_REG))) | |
252b5132 | 3265 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
3266 | && (insn_uses_reg |
3267 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
3268 | MIPS16_REG))) | |
252b5132 | 3269 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
3270 | && (insn_uses_reg |
3271 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
3272 | MIPS16_REG))) | |
252b5132 RH |
3273 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
3274 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
3275 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
3276 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
3277 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3278 | && insn_uses_reg (ip, | |
47e39b9d RS |
3279 | MIPS16OP_EXTRACT_REG32R |
3280 | (history[0].insn_opcode), | |
252b5132 RH |
3281 | MIPS_GR_REG)))) |
3282 | /* If the branch writes a register that the previous | |
3283 | instruction sets, we can not swap (we know that | |
3284 | branches write only to RD or to $31). */ | |
3285 | || (! mips_opts.mips16 | |
3286 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
3287 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3288 | && (EXTRACT_OPERAND (RT, history[0]) |
3289 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3290 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3291 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
3292 | || (! mips_opts.mips16 |
3293 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
3294 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3295 | && (EXTRACT_OPERAND (RD, history[0]) |
3296 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3297 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3298 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
3299 | || (mips_opts.mips16 |
3300 | && (pinfo & MIPS16_INSN_WRITE_31) | |
3301 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
3302 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 3303 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
3304 | == RA)))) |
3305 | /* If the branch writes a register that the previous | |
3306 | instruction reads, we can not swap (we know that | |
3307 | branches only write to RD or to $31). */ | |
3308 | || (! mips_opts.mips16 | |
3309 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 3310 | && insn_uses_reg (&history[0], |
bf12938e | 3311 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
3312 | MIPS_GR_REG)) |
3313 | || (! mips_opts.mips16 | |
3314 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 3315 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3316 | || (mips_opts.mips16 |
3317 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 3318 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3319 | /* If one instruction sets a condition code and the |
3320 | other one uses a condition code, we can not swap. */ | |
3321 | || ((pinfo & INSN_READ_COND_CODE) | |
3322 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3323 | || ((pinfo & INSN_WRITE_COND_CODE) | |
3324 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3325 | /* If the previous instruction uses the PC, we can not | |
3326 | swap. */ | |
3327 | || (mips_opts.mips16 | |
3328 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
3329 | /* If the previous instruction had a fixup in mips16 |
3330 | mode, we can not swap. This normally means that the | |
3331 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 3332 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
3333 | /* If the previous instruction is a sync, sync.l, or |
3334 | sync.p, we can not swap. */ | |
6a32d874 CM |
3335 | || (prev_pinfo & INSN_SYNC) |
3336 | /* If the previous instruction is an ERET or | |
3337 | DERET, avoid the swap. */ | |
3338 | || (history[0].insn_opcode == INSN_ERET) | |
3339 | || (history[0].insn_opcode == INSN_DERET)) | |
252b5132 | 3340 | { |
29024861 DU |
3341 | if (mips_opts.mips16 |
3342 | && (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3343 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)) | |
3994f87e | 3344 | && ISA_SUPPORTS_MIPS16E) |
29024861 DU |
3345 | { |
3346 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
3347 | ip->insn_opcode |= 0x0080; | |
3348 | install_insn (ip); | |
3349 | insert_into_history (0, 1, ip); | |
3350 | } | |
3351 | else | |
3352 | { | |
3353 | /* We could do even better for unconditional branches to | |
3354 | portions of this object file; we could pick up the | |
3355 | instruction at the destination, put it in the delay | |
3356 | slot, and bump the destination address. */ | |
3357 | insert_into_history (0, 1, ip); | |
3358 | emit_nop (); | |
3359 | } | |
3360 | ||
dd22970f ILT |
3361 | if (mips_relax.sequence) |
3362 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
3363 | } |
3364 | else | |
3365 | { | |
3366 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
3367 | struct mips_cl_insn delay = history[0]; |
3368 | if (mips_opts.mips16) | |
252b5132 | 3369 | { |
b8ee1a6e DU |
3370 | know (delay.frag == ip->frag); |
3371 | move_insn (ip, delay.frag, delay.where); | |
3372 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
1e915849 RS |
3373 | } |
3374 | else if (relaxed_branch) | |
3375 | { | |
3376 | /* Add the delay slot instruction to the end of the | |
3377 | current frag and shrink the fixed part of the | |
3378 | original frag. If the branch occupies the tail of | |
3379 | the latter, move it backwards to cover the gap. */ | |
3380 | delay.frag->fr_fix -= 4; | |
3381 | if (delay.frag == ip->frag) | |
3382 | move_insn (ip, ip->frag, ip->where - 4); | |
3383 | add_fixed_insn (&delay); | |
252b5132 RH |
3384 | } |
3385 | else | |
3386 | { | |
1e915849 RS |
3387 | move_insn (&delay, ip->frag, ip->where); |
3388 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 3389 | } |
1e915849 RS |
3390 | history[0] = *ip; |
3391 | delay.fixed_p = 1; | |
3392 | insert_into_history (0, 1, &delay); | |
252b5132 | 3393 | } |
252b5132 RH |
3394 | |
3395 | /* If that was an unconditional branch, forget the previous | |
3396 | insn information. */ | |
3397 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
6a32d874 | 3398 | { |
6a32d874 CM |
3399 | mips_no_prev_insn (); |
3400 | } | |
252b5132 RH |
3401 | } |
3402 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
3403 | { | |
3404 | /* We don't yet optimize a branch likely. What we should do | |
3405 | is look at the target, copy the instruction found there | |
3406 | into the delay slot, and increment the branch to jump to | |
3407 | the next instruction. */ | |
1e915849 | 3408 | insert_into_history (0, 1, ip); |
252b5132 | 3409 | emit_nop (); |
252b5132 RH |
3410 | } |
3411 | else | |
1e915849 | 3412 | insert_into_history (0, 1, ip); |
252b5132 | 3413 | } |
1e915849 RS |
3414 | else |
3415 | insert_into_history (0, 1, ip); | |
252b5132 RH |
3416 | |
3417 | /* We just output an insn, so the next one doesn't have a label. */ | |
3418 | mips_clear_insn_labels (); | |
252b5132 RH |
3419 | } |
3420 | ||
7d10b47d | 3421 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
3422 | |
3423 | static void | |
7d10b47d | 3424 | mips_no_prev_insn (void) |
252b5132 | 3425 | { |
7d10b47d RS |
3426 | prev_nop_frag = NULL; |
3427 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
3428 | mips_clear_insn_labels (); |
3429 | } | |
3430 | ||
7d10b47d RS |
3431 | /* This function must be called before we emit something other than |
3432 | instructions. It is like mips_no_prev_insn except that it inserts | |
3433 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 3434 | |
7d10b47d RS |
3435 | void |
3436 | mips_emit_delays (void) | |
252b5132 RH |
3437 | { |
3438 | if (! mips_opts.noreorder) | |
3439 | { | |
71400594 | 3440 | int nops = nops_for_insn (history, NULL); |
252b5132 RH |
3441 | if (nops > 0) |
3442 | { | |
7d10b47d RS |
3443 | while (nops-- > 0) |
3444 | add_fixed_insn (NOP_INSN); | |
3445 | mips_move_labels (); | |
3446 | } | |
3447 | } | |
3448 | mips_no_prev_insn (); | |
3449 | } | |
3450 | ||
3451 | /* Start a (possibly nested) noreorder block. */ | |
3452 | ||
3453 | static void | |
3454 | start_noreorder (void) | |
3455 | { | |
3456 | if (mips_opts.noreorder == 0) | |
3457 | { | |
3458 | unsigned int i; | |
3459 | int nops; | |
3460 | ||
3461 | /* None of the instructions before the .set noreorder can be moved. */ | |
3462 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
3463 | history[i].fixed_p = 1; | |
3464 | ||
3465 | /* Insert any nops that might be needed between the .set noreorder | |
3466 | block and the previous instructions. We will later remove any | |
3467 | nops that turn out not to be needed. */ | |
3468 | nops = nops_for_insn (history, NULL); | |
3469 | if (nops > 0) | |
3470 | { | |
3471 | if (mips_optimize != 0) | |
252b5132 RH |
3472 | { |
3473 | /* Record the frag which holds the nop instructions, so | |
3474 | that we can remove them if we don't need them. */ | |
3475 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
3476 | prev_nop_frag = frag_now; | |
3477 | prev_nop_frag_holds = nops; | |
3478 | prev_nop_frag_required = 0; | |
3479 | prev_nop_frag_since = 0; | |
3480 | } | |
3481 | ||
3482 | for (; nops > 0; --nops) | |
1e915849 | 3483 | add_fixed_insn (NOP_INSN); |
252b5132 | 3484 | |
7d10b47d RS |
3485 | /* Move on to a new frag, so that it is safe to simply |
3486 | decrease the size of prev_nop_frag. */ | |
3487 | frag_wane (frag_now); | |
3488 | frag_new (0); | |
404a8071 | 3489 | mips_move_labels (); |
252b5132 | 3490 | } |
7d10b47d RS |
3491 | mips16_mark_labels (); |
3492 | mips_clear_insn_labels (); | |
252b5132 | 3493 | } |
7d10b47d RS |
3494 | mips_opts.noreorder++; |
3495 | mips_any_noreorder = 1; | |
3496 | } | |
252b5132 | 3497 | |
7d10b47d | 3498 | /* End a nested noreorder block. */ |
252b5132 | 3499 | |
7d10b47d RS |
3500 | static void |
3501 | end_noreorder (void) | |
3502 | { | |
6a32d874 | 3503 | |
7d10b47d RS |
3504 | mips_opts.noreorder--; |
3505 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
3506 | { | |
3507 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
3508 | handling nop insertion the .set reorder way. */ | |
3509 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
3510 | * (mips_opts.mips16 ? 2 : 4)); | |
3511 | insert_into_history (prev_nop_frag_since, | |
3512 | prev_nop_frag_required, NOP_INSN); | |
3513 | prev_nop_frag = NULL; | |
3514 | } | |
252b5132 RH |
3515 | } |
3516 | ||
584892a6 RS |
3517 | /* Set up global variables for the start of a new macro. */ |
3518 | ||
3519 | static void | |
3520 | macro_start (void) | |
3521 | { | |
3522 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
3523 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 3524 | && (history[0].insn_mo->pinfo |
584892a6 RS |
3525 | & (INSN_UNCOND_BRANCH_DELAY |
3526 | | INSN_COND_BRANCH_DELAY | |
3527 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
3528 | } | |
3529 | ||
3530 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
3531 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
3532 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
3533 | ||
3534 | static const char * | |
3535 | macro_warning (relax_substateT subtype) | |
3536 | { | |
3537 | if (subtype & RELAX_DELAY_SLOT) | |
3538 | return _("Macro instruction expanded into multiple instructions" | |
3539 | " in a branch delay slot"); | |
3540 | else if (subtype & RELAX_NOMACRO) | |
3541 | return _("Macro instruction expanded into multiple instructions"); | |
3542 | else | |
3543 | return 0; | |
3544 | } | |
3545 | ||
3546 | /* Finish up a macro. Emit warnings as appropriate. */ | |
3547 | ||
3548 | static void | |
3549 | macro_end (void) | |
3550 | { | |
3551 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
3552 | { | |
3553 | relax_substateT subtype; | |
3554 | ||
3555 | /* Set up the relaxation warning flags. */ | |
3556 | subtype = 0; | |
3557 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
3558 | subtype |= RELAX_SECOND_LONGER; | |
3559 | if (mips_opts.warn_about_macros) | |
3560 | subtype |= RELAX_NOMACRO; | |
3561 | if (mips_macro_warning.delay_slot_p) | |
3562 | subtype |= RELAX_DELAY_SLOT; | |
3563 | ||
3564 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
3565 | { | |
3566 | /* Either the macro has a single implementation or both | |
3567 | implementations are longer than 4 bytes. Emit the | |
3568 | warning now. */ | |
3569 | const char *msg = macro_warning (subtype); | |
3570 | if (msg != 0) | |
520725ea | 3571 | as_warn ("%s", msg); |
584892a6 RS |
3572 | } |
3573 | else | |
3574 | { | |
3575 | /* One implementation might need a warning but the other | |
3576 | definitely doesn't. */ | |
3577 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
3578 | } | |
3579 | } | |
3580 | } | |
3581 | ||
6e1304d8 RS |
3582 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
3583 | The first argument in *ARGS will be either the code for a single | |
3584 | relocation or -1 followed by the three codes that make up a | |
3585 | composite relocation. */ | |
3586 | ||
3587 | static void | |
3588 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
3589 | { | |
3590 | int i, next; | |
3591 | ||
3592 | next = va_arg (*args, int); | |
3593 | if (next >= 0) | |
3594 | r[0] = (bfd_reloc_code_real_type) next; | |
3595 | else | |
3596 | for (i = 0; i < 3; i++) | |
3597 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
3598 | } | |
3599 | ||
252b5132 RH |
3600 | /* Build an instruction created by a macro expansion. This is passed |
3601 | a pointer to the count of instructions created so far, an | |
3602 | expression, the name of the instruction to build, an operand format | |
3603 | string, and corresponding arguments. */ | |
3604 | ||
252b5132 | 3605 | static void |
67c0d1eb | 3606 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 3607 | { |
1e915849 | 3608 | const struct mips_opcode *mo; |
252b5132 | 3609 | struct mips_cl_insn insn; |
f6688943 | 3610 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3611 | va_list args; |
252b5132 | 3612 | |
252b5132 | 3613 | va_start (args, fmt); |
252b5132 | 3614 | |
252b5132 RH |
3615 | if (mips_opts.mips16) |
3616 | { | |
67c0d1eb | 3617 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
3618 | va_end (args); |
3619 | return; | |
3620 | } | |
3621 | ||
f6688943 TS |
3622 | r[0] = BFD_RELOC_UNUSED; |
3623 | r[1] = BFD_RELOC_UNUSED; | |
3624 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 | 3625 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
9c2799c2 NC |
3626 | gas_assert (mo); |
3627 | gas_assert (strcmp (name, mo->name) == 0); | |
1e915849 | 3628 | |
8b082fb1 TS |
3629 | while (1) |
3630 | { | |
3631 | /* Search until we get a match for NAME. It is assumed here that | |
3632 | macros will never generate MDMX, MIPS-3D, or MT instructions. */ | |
3633 | if (strcmp (fmt, mo->args) == 0 | |
3634 | && mo->pinfo != INSN_MACRO | |
f79e2745 | 3635 | && is_opcode_valid (mo)) |
8b082fb1 TS |
3636 | break; |
3637 | ||
1e915849 | 3638 | ++mo; |
9c2799c2 NC |
3639 | gas_assert (mo->name); |
3640 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3641 | } |
3642 | ||
1e915849 | 3643 | create_insn (&insn, mo); |
252b5132 RH |
3644 | for (;;) |
3645 | { | |
3646 | switch (*fmt++) | |
3647 | { | |
3648 | case '\0': | |
3649 | break; | |
3650 | ||
3651 | case ',': | |
3652 | case '(': | |
3653 | case ')': | |
3654 | continue; | |
3655 | ||
5f74bc13 CD |
3656 | case '+': |
3657 | switch (*fmt++) | |
3658 | { | |
3659 | case 'A': | |
3660 | case 'E': | |
bf12938e | 3661 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
3662 | continue; |
3663 | ||
3664 | case 'B': | |
3665 | case 'F': | |
3666 | /* Note that in the macro case, these arguments are already | |
3667 | in MSB form. (When handling the instruction in the | |
3668 | non-macro case, these arguments are sizes from which | |
3669 | MSB values must be calculated.) */ | |
bf12938e | 3670 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3671 | continue; |
3672 | ||
3673 | case 'C': | |
3674 | case 'G': | |
3675 | case 'H': | |
3676 | /* Note that in the macro case, these arguments are already | |
3677 | in MSBD form. (When handling the instruction in the | |
3678 | non-macro case, these arguments are sizes from which | |
3679 | MSBD values must be calculated.) */ | |
bf12938e | 3680 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3681 | continue; |
3682 | ||
dd3cbb7e NC |
3683 | case 'Q': |
3684 | INSERT_OPERAND (SEQI, insn, va_arg (args, int)); | |
3685 | continue; | |
3686 | ||
5f74bc13 CD |
3687 | default: |
3688 | internalError (); | |
3689 | } | |
3690 | continue; | |
3691 | ||
8b082fb1 TS |
3692 | case '2': |
3693 | INSERT_OPERAND (BP, insn, va_arg (args, int)); | |
3694 | continue; | |
3695 | ||
252b5132 RH |
3696 | case 't': |
3697 | case 'w': | |
3698 | case 'E': | |
bf12938e | 3699 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3700 | continue; |
3701 | ||
3702 | case 'c': | |
bf12938e | 3703 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3704 | continue; |
3705 | ||
252b5132 RH |
3706 | case 'T': |
3707 | case 'W': | |
bf12938e | 3708 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3709 | continue; |
3710 | ||
3711 | case 'd': | |
3712 | case 'G': | |
af7ee8bf | 3713 | case 'K': |
bf12938e | 3714 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3715 | continue; |
3716 | ||
4372b673 NC |
3717 | case 'U': |
3718 | { | |
3719 | int tmp = va_arg (args, int); | |
3720 | ||
bf12938e RS |
3721 | INSERT_OPERAND (RT, insn, tmp); |
3722 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3723 | continue; |
4372b673 NC |
3724 | } |
3725 | ||
252b5132 RH |
3726 | case 'V': |
3727 | case 'S': | |
bf12938e | 3728 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3729 | continue; |
3730 | ||
3731 | case 'z': | |
3732 | continue; | |
3733 | ||
3734 | case '<': | |
bf12938e | 3735 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3736 | continue; |
3737 | ||
3738 | case 'D': | |
bf12938e | 3739 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3740 | continue; |
3741 | ||
3742 | case 'B': | |
bf12938e | 3743 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3744 | continue; |
3745 | ||
4372b673 | 3746 | case 'J': |
bf12938e | 3747 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3748 | continue; |
3749 | ||
252b5132 | 3750 | case 'q': |
bf12938e | 3751 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3752 | continue; |
3753 | ||
3754 | case 'b': | |
3755 | case 's': | |
3756 | case 'r': | |
3757 | case 'v': | |
bf12938e | 3758 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3759 | continue; |
3760 | ||
3761 | case 'i': | |
3762 | case 'j': | |
3763 | case 'o': | |
6e1304d8 | 3764 | macro_read_relocs (&args, r); |
9c2799c2 | 3765 | gas_assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3766 | || *r == BFD_RELOC_MIPS_LITERAL |
3767 | || *r == BFD_RELOC_MIPS_HIGHER | |
3768 | || *r == BFD_RELOC_HI16_S | |
3769 | || *r == BFD_RELOC_LO16 | |
3770 | || *r == BFD_RELOC_MIPS_GOT16 | |
3771 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3772 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3773 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3774 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3775 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3776 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3777 | continue; |
3778 | ||
3779 | case 'u': | |
6e1304d8 | 3780 | macro_read_relocs (&args, r); |
9c2799c2 | 3781 | gas_assert (ep != NULL |
252b5132 RH |
3782 | && (ep->X_op == O_constant |
3783 | || (ep->X_op == O_symbol | |
f6688943 TS |
3784 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3785 | || *r == BFD_RELOC_HI16_S | |
3786 | || *r == BFD_RELOC_HI16 | |
3787 | || *r == BFD_RELOC_GPREL16 | |
3788 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3789 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3790 | continue; |
3791 | ||
3792 | case 'p': | |
9c2799c2 | 3793 | gas_assert (ep != NULL); |
bad36eac | 3794 | |
252b5132 RH |
3795 | /* |
3796 | * This allows macro() to pass an immediate expression for | |
3797 | * creating short branches without creating a symbol. | |
bad36eac DJ |
3798 | * |
3799 | * We don't allow branch relaxation for these branches, as | |
3800 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
3801 | */ |
3802 | if (ep->X_op == O_constant) | |
3803 | { | |
bad36eac DJ |
3804 | if ((ep->X_add_number & 3) != 0) |
3805 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3806 | (unsigned long) ep->X_add_number); | |
3807 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
3808 | as_bad (_("branch address range overflow (0x%lx)"), | |
3809 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3810 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
3811 | ep = NULL; | |
3812 | } | |
3813 | else | |
0b25d3e6 | 3814 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3815 | continue; |
3816 | ||
3817 | case 'a': | |
9c2799c2 | 3818 | gas_assert (ep != NULL); |
f6688943 | 3819 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3820 | continue; |
3821 | ||
3822 | case 'C': | |
a9e24354 | 3823 | INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long)); |
252b5132 RH |
3824 | continue; |
3825 | ||
d43b4baf | 3826 | case 'k': |
a9e24354 | 3827 | INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long)); |
d43b4baf TS |
3828 | continue; |
3829 | ||
252b5132 RH |
3830 | default: |
3831 | internalError (); | |
3832 | } | |
3833 | break; | |
3834 | } | |
3835 | va_end (args); | |
9c2799c2 | 3836 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3837 | |
4d7206a2 | 3838 | append_insn (&insn, ep, r); |
252b5132 RH |
3839 | } |
3840 | ||
3841 | static void | |
67c0d1eb | 3842 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3843 | va_list args) |
252b5132 | 3844 | { |
1e915849 | 3845 | struct mips_opcode *mo; |
252b5132 | 3846 | struct mips_cl_insn insn; |
f6688943 TS |
3847 | bfd_reloc_code_real_type r[3] |
3848 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3849 | |
1e915849 | 3850 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
3851 | gas_assert (mo); |
3852 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 3853 | |
1e915849 | 3854 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 3855 | { |
1e915849 | 3856 | ++mo; |
9c2799c2 NC |
3857 | gas_assert (mo->name); |
3858 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3859 | } |
3860 | ||
1e915849 | 3861 | create_insn (&insn, mo); |
252b5132 RH |
3862 | for (;;) |
3863 | { | |
3864 | int c; | |
3865 | ||
3866 | c = *fmt++; | |
3867 | switch (c) | |
3868 | { | |
3869 | case '\0': | |
3870 | break; | |
3871 | ||
3872 | case ',': | |
3873 | case '(': | |
3874 | case ')': | |
3875 | continue; | |
3876 | ||
3877 | case 'y': | |
3878 | case 'w': | |
bf12938e | 3879 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int)); |
252b5132 RH |
3880 | continue; |
3881 | ||
3882 | case 'x': | |
3883 | case 'v': | |
bf12938e | 3884 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int)); |
252b5132 RH |
3885 | continue; |
3886 | ||
3887 | case 'z': | |
bf12938e | 3888 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int)); |
252b5132 RH |
3889 | continue; |
3890 | ||
3891 | case 'Z': | |
bf12938e | 3892 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int)); |
252b5132 RH |
3893 | continue; |
3894 | ||
3895 | case '0': | |
3896 | case 'S': | |
3897 | case 'P': | |
3898 | case 'R': | |
3899 | continue; | |
3900 | ||
3901 | case 'X': | |
bf12938e | 3902 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int)); |
252b5132 RH |
3903 | continue; |
3904 | ||
3905 | case 'Y': | |
3906 | { | |
3907 | int regno; | |
3908 | ||
3909 | regno = va_arg (args, int); | |
3910 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
a9e24354 | 3911 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
3912 | } |
3913 | continue; | |
3914 | ||
3915 | case '<': | |
3916 | case '>': | |
3917 | case '4': | |
3918 | case '5': | |
3919 | case 'H': | |
3920 | case 'W': | |
3921 | case 'D': | |
3922 | case 'j': | |
3923 | case '8': | |
3924 | case 'V': | |
3925 | case 'C': | |
3926 | case 'U': | |
3927 | case 'k': | |
3928 | case 'K': | |
3929 | case 'p': | |
3930 | case 'q': | |
3931 | { | |
9c2799c2 | 3932 | gas_assert (ep != NULL); |
252b5132 RH |
3933 | |
3934 | if (ep->X_op != O_constant) | |
874e8986 | 3935 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3936 | else |
3937 | { | |
b34976b6 AM |
3938 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3939 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3940 | &insn.extend); |
252b5132 | 3941 | ep = NULL; |
f6688943 | 3942 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3943 | } |
3944 | } | |
3945 | continue; | |
3946 | ||
3947 | case '6': | |
bf12938e | 3948 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int)); |
252b5132 RH |
3949 | continue; |
3950 | } | |
3951 | ||
3952 | break; | |
3953 | } | |
3954 | ||
9c2799c2 | 3955 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3956 | |
4d7206a2 | 3957 | append_insn (&insn, ep, r); |
252b5132 RH |
3958 | } |
3959 | ||
2051e8c4 MR |
3960 | /* |
3961 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
3962 | * higher bits unset. | |
3963 | */ | |
9f872bbe | 3964 | static void |
2051e8c4 MR |
3965 | normalize_constant_expr (expressionS *ex) |
3966 | { | |
9ee2a2d4 | 3967 | if (ex->X_op == O_constant |
2051e8c4 MR |
3968 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
3969 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3970 | - 0x80000000); | |
3971 | } | |
3972 | ||
3973 | /* | |
3974 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
3975 | * all higher bits unset. | |
3976 | */ | |
3977 | static void | |
3978 | normalize_address_expr (expressionS *ex) | |
3979 | { | |
3980 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
3981 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
3982 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
3983 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3984 | - 0x80000000); | |
3985 | } | |
3986 | ||
438c16b8 TS |
3987 | /* |
3988 | * Generate a "jalr" instruction with a relocation hint to the called | |
3989 | * function. This occurs in NewABI PIC code. | |
3990 | */ | |
3991 | static void | |
67c0d1eb | 3992 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3993 | { |
685736be | 3994 | char *f = NULL; |
b34976b6 | 3995 | |
1180b5a4 | 3996 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 3997 | { |
cc3d92a5 | 3998 | frag_grow (8); |
f21f8242 AO |
3999 | f = frag_more (0); |
4000 | } | |
67c0d1eb | 4001 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
1180b5a4 | 4002 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 4003 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 4004 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
4005 | } |
4006 | ||
252b5132 RH |
4007 | /* |
4008 | * Generate a "lui" instruction. | |
4009 | */ | |
4010 | static void | |
67c0d1eb | 4011 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
4012 | { |
4013 | expressionS high_expr; | |
1e915849 | 4014 | const struct mips_opcode *mo; |
252b5132 | 4015 | struct mips_cl_insn insn; |
f6688943 TS |
4016 | bfd_reloc_code_real_type r[3] |
4017 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
4018 | const char *name = "lui"; |
4019 | const char *fmt = "t,u"; | |
252b5132 | 4020 | |
9c2799c2 | 4021 | gas_assert (! mips_opts.mips16); |
252b5132 | 4022 | |
4d7206a2 | 4023 | high_expr = *ep; |
252b5132 RH |
4024 | |
4025 | if (high_expr.X_op == O_constant) | |
4026 | { | |
54f4ddb3 | 4027 | /* We can compute the instruction now without a relocation entry. */ |
e7d556df TS |
4028 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
4029 | >> 16) & 0xffff; | |
f6688943 | 4030 | *r = BFD_RELOC_UNUSED; |
252b5132 | 4031 | } |
78e1bb40 | 4032 | else |
252b5132 | 4033 | { |
9c2799c2 | 4034 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
4035 | /* _gp_disp is a special case, used from s_cpload. |
4036 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 4037 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 4038 | || (! HAVE_NEWABI |
aa6975fb ILT |
4039 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
4040 | || (! mips_in_shared | |
bbe506e8 TS |
4041 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
4042 | "__gnu_local_gp") == 0)); | |
f6688943 | 4043 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
4044 | } |
4045 | ||
1e915849 | 4046 | mo = hash_find (op_hash, name); |
9c2799c2 NC |
4047 | gas_assert (strcmp (name, mo->name) == 0); |
4048 | gas_assert (strcmp (fmt, mo->args) == 0); | |
1e915849 | 4049 | create_insn (&insn, mo); |
252b5132 | 4050 | |
bf12938e RS |
4051 | insn.insn_opcode = insn.insn_mo->match; |
4052 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 4053 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
4054 | { |
4055 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 4056 | append_insn (&insn, NULL, r); |
252b5132 RH |
4057 | } |
4058 | else | |
4d7206a2 | 4059 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
4060 | } |
4061 | ||
885add95 CD |
4062 | /* Generate a sequence of instructions to do a load or store from a constant |
4063 | offset off of a base register (breg) into/from a target register (treg), | |
4064 | using AT if necessary. */ | |
4065 | static void | |
67c0d1eb RS |
4066 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
4067 | int treg, int breg, int dbl) | |
885add95 | 4068 | { |
9c2799c2 | 4069 | gas_assert (ep->X_op == O_constant); |
885add95 | 4070 | |
256ab948 | 4071 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
4072 | if (!dbl) |
4073 | normalize_constant_expr (ep); | |
256ab948 | 4074 | |
67c1ffbe | 4075 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 4076 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
4077 | as_warn (_("operand overflow")); |
4078 | ||
4079 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
4080 | { | |
4081 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 4082 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
4083 | } |
4084 | else | |
4085 | { | |
4086 | /* 32-bit offset, need multiple instructions and AT, like: | |
4087 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
4088 | addu $tempreg,$tempreg,$breg | |
4089 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
4090 | to handle the complete offset. */ | |
67c0d1eb RS |
4091 | macro_build_lui (ep, AT); |
4092 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
4093 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 4094 | |
741fe287 | 4095 | if (!mips_opts.at) |
8fc2e39e | 4096 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
4097 | } |
4098 | } | |
4099 | ||
252b5132 RH |
4100 | /* set_at() |
4101 | * Generates code to set the $at register to true (one) | |
4102 | * if reg is less than the immediate expression. | |
4103 | */ | |
4104 | static void | |
67c0d1eb | 4105 | set_at (int reg, int unsignedp) |
252b5132 RH |
4106 | { |
4107 | if (imm_expr.X_op == O_constant | |
4108 | && imm_expr.X_add_number >= -0x8000 | |
4109 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
4110 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
4111 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
4112 | else |
4113 | { | |
67c0d1eb RS |
4114 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4115 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
4116 | } |
4117 | } | |
4118 | ||
4119 | /* Warn if an expression is not a constant. */ | |
4120 | ||
4121 | static void | |
17a2f251 | 4122 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
4123 | { |
4124 | if (ex->X_op == O_big) | |
4125 | as_bad (_("unsupported large constant")); | |
4126 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
4127 | as_bad (_("Instruction %s requires absolute expression"), |
4128 | ip->insn_mo->name); | |
13757d0c | 4129 | |
9ee2a2d4 MR |
4130 | if (HAVE_32BIT_GPRS) |
4131 | normalize_constant_expr (ex); | |
252b5132 RH |
4132 | } |
4133 | ||
4134 | /* Count the leading zeroes by performing a binary chop. This is a | |
4135 | bulky bit of source, but performance is a LOT better for the | |
4136 | majority of values than a simple loop to count the bits: | |
4137 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
4138 | if ((v) & (1 << (31 - lcnt))) | |
4139 | break; | |
4140 | However it is not code size friendly, and the gain will drop a bit | |
4141 | on certain cached systems. | |
4142 | */ | |
4143 | #define COUNT_TOP_ZEROES(v) \ | |
4144 | (((v) & ~0xffff) == 0 \ | |
4145 | ? ((v) & ~0xff) == 0 \ | |
4146 | ? ((v) & ~0xf) == 0 \ | |
4147 | ? ((v) & ~0x3) == 0 \ | |
4148 | ? ((v) & ~0x1) == 0 \ | |
4149 | ? !(v) \ | |
4150 | ? 32 \ | |
4151 | : 31 \ | |
4152 | : 30 \ | |
4153 | : ((v) & ~0x7) == 0 \ | |
4154 | ? 29 \ | |
4155 | : 28 \ | |
4156 | : ((v) & ~0x3f) == 0 \ | |
4157 | ? ((v) & ~0x1f) == 0 \ | |
4158 | ? 27 \ | |
4159 | : 26 \ | |
4160 | : ((v) & ~0x7f) == 0 \ | |
4161 | ? 25 \ | |
4162 | : 24 \ | |
4163 | : ((v) & ~0xfff) == 0 \ | |
4164 | ? ((v) & ~0x3ff) == 0 \ | |
4165 | ? ((v) & ~0x1ff) == 0 \ | |
4166 | ? 23 \ | |
4167 | : 22 \ | |
4168 | : ((v) & ~0x7ff) == 0 \ | |
4169 | ? 21 \ | |
4170 | : 20 \ | |
4171 | : ((v) & ~0x3fff) == 0 \ | |
4172 | ? ((v) & ~0x1fff) == 0 \ | |
4173 | ? 19 \ | |
4174 | : 18 \ | |
4175 | : ((v) & ~0x7fff) == 0 \ | |
4176 | ? 17 \ | |
4177 | : 16 \ | |
4178 | : ((v) & ~0xffffff) == 0 \ | |
4179 | ? ((v) & ~0xfffff) == 0 \ | |
4180 | ? ((v) & ~0x3ffff) == 0 \ | |
4181 | ? ((v) & ~0x1ffff) == 0 \ | |
4182 | ? 15 \ | |
4183 | : 14 \ | |
4184 | : ((v) & ~0x7ffff) == 0 \ | |
4185 | ? 13 \ | |
4186 | : 12 \ | |
4187 | : ((v) & ~0x3fffff) == 0 \ | |
4188 | ? ((v) & ~0x1fffff) == 0 \ | |
4189 | ? 11 \ | |
4190 | : 10 \ | |
4191 | : ((v) & ~0x7fffff) == 0 \ | |
4192 | ? 9 \ | |
4193 | : 8 \ | |
4194 | : ((v) & ~0xfffffff) == 0 \ | |
4195 | ? ((v) & ~0x3ffffff) == 0 \ | |
4196 | ? ((v) & ~0x1ffffff) == 0 \ | |
4197 | ? 7 \ | |
4198 | : 6 \ | |
4199 | : ((v) & ~0x7ffffff) == 0 \ | |
4200 | ? 5 \ | |
4201 | : 4 \ | |
4202 | : ((v) & ~0x3fffffff) == 0 \ | |
4203 | ? ((v) & ~0x1fffffff) == 0 \ | |
4204 | ? 3 \ | |
4205 | : 2 \ | |
4206 | : ((v) & ~0x7fffffff) == 0 \ | |
4207 | ? 1 \ | |
4208 | : 0) | |
4209 | ||
4210 | /* load_register() | |
67c1ffbe | 4211 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
4212 | * an absolute expression value into a register. |
4213 | */ | |
4214 | static void | |
67c0d1eb | 4215 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
4216 | { |
4217 | int freg; | |
4218 | expressionS hi32, lo32; | |
4219 | ||
4220 | if (ep->X_op != O_big) | |
4221 | { | |
9c2799c2 | 4222 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
4223 | |
4224 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
4225 | if (!dbl) |
4226 | normalize_constant_expr (ep); | |
256ab948 TS |
4227 | |
4228 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
4229 | { |
4230 | /* We can handle 16 bit signed values with an addiu to | |
4231 | $zero. No need to ever use daddiu here, since $zero and | |
4232 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 4233 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4234 | return; |
4235 | } | |
4236 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
4237 | { | |
4238 | /* We can handle 16 bit unsigned values with an ori to | |
4239 | $zero. */ | |
67c0d1eb | 4240 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4241 | return; |
4242 | } | |
256ab948 | 4243 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
4244 | { |
4245 | /* 32 bit values require an lui. */ | |
67c0d1eb | 4246 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4247 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 4248 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
4249 | return; |
4250 | } | |
4251 | } | |
4252 | ||
4253 | /* The value is larger than 32 bits. */ | |
4254 | ||
2051e8c4 | 4255 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 4256 | { |
55e08f71 NC |
4257 | char value[32]; |
4258 | ||
4259 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 4260 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 4261 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4262 | return; |
4263 | } | |
4264 | ||
4265 | if (ep->X_op != O_big) | |
4266 | { | |
4267 | hi32 = *ep; | |
4268 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4269 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4270 | hi32.X_add_number &= 0xffffffff; | |
4271 | lo32 = *ep; | |
4272 | lo32.X_add_number &= 0xffffffff; | |
4273 | } | |
4274 | else | |
4275 | { | |
9c2799c2 | 4276 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
4277 | if (ep->X_add_number == 3) |
4278 | generic_bignum[3] = 0; | |
4279 | else if (ep->X_add_number > 4) | |
4280 | as_bad (_("Number larger than 64 bits")); | |
4281 | lo32.X_op = O_constant; | |
4282 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
4283 | hi32.X_op = O_constant; | |
4284 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
4285 | } | |
4286 | ||
4287 | if (hi32.X_add_number == 0) | |
4288 | freg = 0; | |
4289 | else | |
4290 | { | |
4291 | int shift, bit; | |
4292 | unsigned long hi, lo; | |
4293 | ||
956cd1d6 | 4294 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
4295 | { |
4296 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
4297 | { | |
67c0d1eb | 4298 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4299 | return; |
4300 | } | |
4301 | if (lo32.X_add_number & 0x80000000) | |
4302 | { | |
67c0d1eb | 4303 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4304 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 4305 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
4306 | return; |
4307 | } | |
4308 | } | |
252b5132 RH |
4309 | |
4310 | /* Check for 16bit shifted constant. We know that hi32 is | |
4311 | non-zero, so start the mask on the first bit of the hi32 | |
4312 | value. */ | |
4313 | shift = 17; | |
4314 | do | |
beae10d5 KH |
4315 | { |
4316 | unsigned long himask, lomask; | |
4317 | ||
4318 | if (shift < 32) | |
4319 | { | |
4320 | himask = 0xffff >> (32 - shift); | |
4321 | lomask = (0xffff << shift) & 0xffffffff; | |
4322 | } | |
4323 | else | |
4324 | { | |
4325 | himask = 0xffff << (shift - 32); | |
4326 | lomask = 0; | |
4327 | } | |
4328 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
4329 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
4330 | { | |
4331 | expressionS tmp; | |
4332 | ||
4333 | tmp.X_op = O_constant; | |
4334 | if (shift < 32) | |
4335 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
4336 | | (lo32.X_add_number >> shift)); | |
4337 | else | |
4338 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
4339 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
4340 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
4341 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4342 | return; |
4343 | } | |
f9419b05 | 4344 | ++shift; |
beae10d5 KH |
4345 | } |
4346 | while (shift <= (64 - 16)); | |
252b5132 RH |
4347 | |
4348 | /* Find the bit number of the lowest one bit, and store the | |
4349 | shifted value in hi/lo. */ | |
4350 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
4351 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
4352 | if (lo != 0) | |
4353 | { | |
4354 | bit = 0; | |
4355 | while ((lo & 1) == 0) | |
4356 | { | |
4357 | lo >>= 1; | |
4358 | ++bit; | |
4359 | } | |
4360 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
4361 | hi >>= bit; | |
4362 | } | |
4363 | else | |
4364 | { | |
4365 | bit = 32; | |
4366 | while ((hi & 1) == 0) | |
4367 | { | |
4368 | hi >>= 1; | |
4369 | ++bit; | |
4370 | } | |
4371 | lo = hi; | |
4372 | hi = 0; | |
4373 | } | |
4374 | ||
4375 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
4376 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
4377 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
4378 | { |
4379 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 4380 | if (shift != 0) |
beae10d5 | 4381 | { |
252b5132 RH |
4382 | expressionS tmp; |
4383 | ||
4384 | /* This instruction will set the register to be all | |
4385 | ones. */ | |
beae10d5 KH |
4386 | tmp.X_op = O_constant; |
4387 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 4388 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4389 | if (bit != 0) |
4390 | { | |
4391 | bit += shift; | |
67c0d1eb RS |
4392 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
4393 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 4394 | } |
67c0d1eb RS |
4395 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
4396 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4397 | return; |
4398 | } | |
4399 | } | |
252b5132 RH |
4400 | |
4401 | /* Sign extend hi32 before calling load_register, because we can | |
4402 | generally get better code when we load a sign extended value. */ | |
4403 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 4404 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 4405 | load_register (reg, &hi32, 0); |
252b5132 RH |
4406 | freg = reg; |
4407 | } | |
4408 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
4409 | { | |
4410 | if (freg != 0) | |
4411 | { | |
67c0d1eb | 4412 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
4413 | freg = reg; |
4414 | } | |
4415 | } | |
4416 | else | |
4417 | { | |
4418 | expressionS mid16; | |
4419 | ||
956cd1d6 | 4420 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 4421 | { |
67c0d1eb RS |
4422 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
4423 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
4424 | return; |
4425 | } | |
252b5132 RH |
4426 | |
4427 | if (freg != 0) | |
4428 | { | |
67c0d1eb | 4429 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
4430 | freg = reg; |
4431 | } | |
4432 | mid16 = lo32; | |
4433 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
4434 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
4435 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
4436 | freg = reg; |
4437 | } | |
4438 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 4439 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
4440 | } |
4441 | ||
269137b2 TS |
4442 | static inline void |
4443 | load_delay_nop (void) | |
4444 | { | |
4445 | if (!gpr_interlocks) | |
4446 | macro_build (NULL, "nop", ""); | |
4447 | } | |
4448 | ||
252b5132 RH |
4449 | /* Load an address into a register. */ |
4450 | ||
4451 | static void | |
67c0d1eb | 4452 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 4453 | { |
252b5132 RH |
4454 | if (ep->X_op != O_constant |
4455 | && ep->X_op != O_symbol) | |
4456 | { | |
4457 | as_bad (_("expression too complex")); | |
4458 | ep->X_op = O_constant; | |
4459 | } | |
4460 | ||
4461 | if (ep->X_op == O_constant) | |
4462 | { | |
67c0d1eb | 4463 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4464 | return; |
4465 | } | |
4466 | ||
4467 | if (mips_pic == NO_PIC) | |
4468 | { | |
4469 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 4470 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4471 | Otherwise we want |
4472 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
4473 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 4474 | If we have an addend, we always use the latter form. |
76b3015f | 4475 | |
d6bc6245 TS |
4476 | With 64bit address space and a usable $at we want |
4477 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4478 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4479 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4480 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4481 | dsll32 $reg,0 | |
3a482fd5 | 4482 | daddu $reg,$reg,$at |
76b3015f | 4483 | |
c03099e6 | 4484 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4485 | on superscalar processors. |
4486 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4487 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4488 | dsll $reg,16 | |
4489 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
4490 | dsll $reg,16 | |
4491 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
4492 | |
4493 | For GP relative symbols in 64bit address space we can use | |
4494 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4495 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 4496 | { |
6caf9ef4 TS |
4497 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
4498 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
4499 | { | |
4500 | relax_start (ep->X_add_symbol); | |
4501 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
4502 | mips_gp_register, BFD_RELOC_GPREL16); | |
4503 | relax_switch (); | |
4504 | } | |
d6bc6245 | 4505 | |
741fe287 | 4506 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 4507 | { |
67c0d1eb RS |
4508 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4509 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
4510 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4511 | BFD_RELOC_MIPS_HIGHER); | |
4512 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
4513 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
4514 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
4515 | *used_at = 1; |
4516 | } | |
4517 | else | |
4518 | { | |
67c0d1eb RS |
4519 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4520 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4521 | BFD_RELOC_MIPS_HIGHER); | |
4522 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4523 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
4524 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4525 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 4526 | } |
6caf9ef4 TS |
4527 | |
4528 | if (mips_relax.sequence) | |
4529 | relax_end (); | |
d6bc6245 | 4530 | } |
252b5132 RH |
4531 | else |
4532 | { | |
d6bc6245 | 4533 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 4534 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 4535 | { |
4d7206a2 | 4536 | relax_start (ep->X_add_symbol); |
67c0d1eb | 4537 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 4538 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 4539 | relax_switch (); |
d6bc6245 | 4540 | } |
67c0d1eb RS |
4541 | macro_build_lui (ep, reg); |
4542 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
4543 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4544 | if (mips_relax.sequence) |
4545 | relax_end (); | |
d6bc6245 | 4546 | } |
252b5132 | 4547 | } |
0a44bf69 | 4548 | else if (!mips_big_got) |
252b5132 RH |
4549 | { |
4550 | expressionS ex; | |
4551 | ||
4552 | /* If this is a reference to an external symbol, we want | |
4553 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4554 | Otherwise we want | |
4555 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4556 | nop | |
4557 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
4558 | If there is a constant, it must be added in after. |
4559 | ||
ed6fb7bd | 4560 | If we have NewABI, we want |
f5040a92 AO |
4561 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
4562 | unless we're referencing a global symbol with a non-zero | |
4563 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
4564 | if (HAVE_NEWABI) |
4565 | { | |
f5040a92 AO |
4566 | if (ep->X_add_number) |
4567 | { | |
4d7206a2 | 4568 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4569 | ep->X_add_number = 0; |
4d7206a2 | 4570 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4571 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4572 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
4573 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4574 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4575 | ex.X_op = O_constant; | |
67c0d1eb | 4576 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4577 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4578 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 4579 | relax_switch (); |
f5040a92 | 4580 | } |
67c0d1eb | 4581 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4582 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
4583 | if (mips_relax.sequence) |
4584 | relax_end (); | |
ed6fb7bd SC |
4585 | } |
4586 | else | |
4587 | { | |
f5040a92 AO |
4588 | ex.X_add_number = ep->X_add_number; |
4589 | ep->X_add_number = 0; | |
67c0d1eb RS |
4590 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4591 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 4592 | load_delay_nop (); |
4d7206a2 RS |
4593 | relax_start (ep->X_add_symbol); |
4594 | relax_switch (); | |
67c0d1eb | 4595 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4596 | BFD_RELOC_LO16); |
4d7206a2 | 4597 | relax_end (); |
ed6fb7bd | 4598 | |
f5040a92 AO |
4599 | if (ex.X_add_number != 0) |
4600 | { | |
4601 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4602 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4603 | ex.X_op = O_constant; | |
67c0d1eb | 4604 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4605 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4606 | } |
252b5132 RH |
4607 | } |
4608 | } | |
0a44bf69 | 4609 | else if (mips_big_got) |
252b5132 RH |
4610 | { |
4611 | expressionS ex; | |
252b5132 RH |
4612 | |
4613 | /* This is the large GOT case. If this is a reference to an | |
4614 | external symbol, we want | |
4615 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4616 | addu $reg,$reg,$gp | |
4617 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
4618 | |
4619 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
4620 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4621 | nop | |
4622 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 4623 | If there is a constant, it must be added in after. |
f5040a92 AO |
4624 | |
4625 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
4626 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
4627 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 4628 | */ |
438c16b8 TS |
4629 | if (HAVE_NEWABI) |
4630 | { | |
4d7206a2 | 4631 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4632 | ep->X_add_number = 0; |
4d7206a2 | 4633 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4634 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4635 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4636 | reg, reg, mips_gp_register); | |
4637 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4638 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4639 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4640 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4641 | else if (ex.X_add_number) | |
4642 | { | |
4643 | ex.X_op = O_constant; | |
67c0d1eb RS |
4644 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4645 | BFD_RELOC_LO16); | |
f5040a92 AO |
4646 | } |
4647 | ||
4648 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4649 | relax_switch (); |
67c0d1eb | 4650 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4651 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4652 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4653 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4654 | relax_end (); |
438c16b8 | 4655 | } |
252b5132 | 4656 | else |
438c16b8 | 4657 | { |
f5040a92 AO |
4658 | ex.X_add_number = ep->X_add_number; |
4659 | ep->X_add_number = 0; | |
4d7206a2 | 4660 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4661 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4662 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4663 | reg, reg, mips_gp_register); | |
4664 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4665 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4666 | relax_switch (); |
4667 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4668 | { |
4669 | /* We need a nop before loading from $gp. This special | |
4670 | check is required because the lui which starts the main | |
4671 | instruction stream does not refer to $gp, and so will not | |
4672 | insert the nop which may be required. */ | |
67c0d1eb | 4673 | macro_build (NULL, "nop", ""); |
438c16b8 | 4674 | } |
67c0d1eb | 4675 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4676 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4677 | load_delay_nop (); |
67c0d1eb | 4678 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4679 | BFD_RELOC_LO16); |
4d7206a2 | 4680 | relax_end (); |
438c16b8 | 4681 | |
f5040a92 AO |
4682 | if (ex.X_add_number != 0) |
4683 | { | |
4684 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4685 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4686 | ex.X_op = O_constant; | |
67c0d1eb RS |
4687 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4688 | BFD_RELOC_LO16); | |
f5040a92 | 4689 | } |
252b5132 RH |
4690 | } |
4691 | } | |
252b5132 RH |
4692 | else |
4693 | abort (); | |
8fc2e39e | 4694 | |
741fe287 | 4695 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 4696 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
4697 | } |
4698 | ||
ea1fb5dc RS |
4699 | /* Move the contents of register SOURCE into register DEST. */ |
4700 | ||
4701 | static void | |
67c0d1eb | 4702 | move_register (int dest, int source) |
ea1fb5dc | 4703 | { |
67c0d1eb RS |
4704 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4705 | dest, source, 0); | |
ea1fb5dc RS |
4706 | } |
4707 | ||
4d7206a2 | 4708 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4709 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4710 | The two alternatives are: | |
4d7206a2 RS |
4711 | |
4712 | Global symbol Local sybmol | |
4713 | ------------- ------------ | |
4714 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4715 | ... ... | |
4716 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4717 | ||
4718 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4719 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4720 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4721 | |
4722 | static void | |
67c0d1eb | 4723 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4724 | { |
4725 | expressionS global; | |
4726 | ||
4727 | global = *local; | |
4728 | global.X_add_number = 0; | |
4729 | ||
4730 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4731 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4732 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4733 | relax_switch (); |
67c0d1eb RS |
4734 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4735 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4736 | relax_end (); |
4737 | } | |
4738 | ||
4739 | static void | |
67c0d1eb | 4740 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4741 | { |
4742 | expressionS global; | |
4743 | ||
4744 | global.X_op = O_constant; | |
4745 | global.X_op_symbol = NULL; | |
4746 | global.X_add_symbol = NULL; | |
4747 | global.X_add_number = local->X_add_number; | |
4748 | ||
4749 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4750 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4751 | dest, dest, BFD_RELOC_LO16); |
4752 | relax_switch (); | |
67c0d1eb | 4753 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4754 | relax_end (); |
4755 | } | |
4756 | ||
f6a22291 MR |
4757 | static void |
4758 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4759 | { | |
4760 | expressionS global; | |
4761 | int hold_mips_optimize; | |
4762 | ||
4763 | global.X_op = O_constant; | |
4764 | global.X_op_symbol = NULL; | |
4765 | global.X_add_symbol = NULL; | |
4766 | global.X_add_number = local->X_add_number; | |
4767 | ||
4768 | relax_start (local->X_add_symbol); | |
4769 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4770 | relax_switch (); | |
4771 | /* Set mips_optimize around the lui instruction to avoid | |
4772 | inserting an unnecessary nop after the lw. */ | |
4773 | hold_mips_optimize = mips_optimize; | |
4774 | mips_optimize = 2; | |
4775 | macro_build_lui (&global, tmp); | |
4776 | mips_optimize = hold_mips_optimize; | |
4777 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4778 | relax_end (); | |
4779 | ||
4780 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4781 | } | |
4782 | ||
252b5132 RH |
4783 | /* |
4784 | * Build macros | |
4785 | * This routine implements the seemingly endless macro or synthesized | |
4786 | * instructions and addressing modes in the mips assembly language. Many | |
4787 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4788 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4789 | * this verbose method. Others are not simple macros but are more like |
4790 | * optimizing code generation. | |
4791 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4792 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4793 | * The ensuing load upper instructions are ommited. This implies some kind |
4794 | * of global optimization. We currently only optimize within a single macro. | |
4795 | * For many of the load and store macros if the address is specified as a | |
4796 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4797 | * first load register 'at' with zero and use it as the base register. The | |
4798 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4799 | * we're missing. | |
4800 | */ | |
4801 | static void | |
17a2f251 | 4802 | macro (struct mips_cl_insn *ip) |
252b5132 | 4803 | { |
741fe287 MR |
4804 | unsigned int treg, sreg, dreg, breg; |
4805 | unsigned int tempreg; | |
252b5132 | 4806 | int mask; |
43841e91 | 4807 | int used_at = 0; |
252b5132 RH |
4808 | expressionS expr1; |
4809 | const char *s; | |
4810 | const char *s2; | |
4811 | const char *fmt; | |
4812 | int likely = 0; | |
4813 | int dbl = 0; | |
4814 | int coproc = 0; | |
4815 | int lr = 0; | |
4816 | int imm = 0; | |
1abe91b1 | 4817 | int call = 0; |
252b5132 | 4818 | int off; |
67c0d1eb | 4819 | offsetT maxnum; |
252b5132 | 4820 | bfd_reloc_code_real_type r; |
252b5132 RH |
4821 | int hold_mips_optimize; |
4822 | ||
9c2799c2 | 4823 | gas_assert (! mips_opts.mips16); |
252b5132 RH |
4824 | |
4825 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4826 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4827 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4828 | mask = ip->insn_mo->mask; | |
4829 | ||
4830 | expr1.X_op = O_constant; | |
4831 | expr1.X_op_symbol = NULL; | |
4832 | expr1.X_add_symbol = NULL; | |
4833 | expr1.X_add_number = 1; | |
4834 | ||
4835 | switch (mask) | |
4836 | { | |
4837 | case M_DABS: | |
4838 | dbl = 1; | |
4839 | case M_ABS: | |
4840 | /* bgez $a0,.+12 | |
4841 | move v0,$a0 | |
4842 | sub v0,$zero,$a0 | |
4843 | */ | |
4844 | ||
7d10b47d | 4845 | start_noreorder (); |
252b5132 RH |
4846 | |
4847 | expr1.X_add_number = 8; | |
67c0d1eb | 4848 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4849 | if (dreg == sreg) |
67c0d1eb | 4850 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4851 | else |
67c0d1eb RS |
4852 | move_register (dreg, sreg); |
4853 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 4854 | |
7d10b47d | 4855 | end_noreorder (); |
8fc2e39e | 4856 | break; |
252b5132 RH |
4857 | |
4858 | case M_ADD_I: | |
4859 | s = "addi"; | |
4860 | s2 = "add"; | |
4861 | goto do_addi; | |
4862 | case M_ADDU_I: | |
4863 | s = "addiu"; | |
4864 | s2 = "addu"; | |
4865 | goto do_addi; | |
4866 | case M_DADD_I: | |
4867 | dbl = 1; | |
4868 | s = "daddi"; | |
4869 | s2 = "dadd"; | |
4870 | goto do_addi; | |
4871 | case M_DADDU_I: | |
4872 | dbl = 1; | |
4873 | s = "daddiu"; | |
4874 | s2 = "daddu"; | |
4875 | do_addi: | |
4876 | if (imm_expr.X_op == O_constant | |
4877 | && imm_expr.X_add_number >= -0x8000 | |
4878 | && imm_expr.X_add_number < 0x8000) | |
4879 | { | |
67c0d1eb | 4880 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4881 | break; |
252b5132 | 4882 | } |
8fc2e39e | 4883 | used_at = 1; |
67c0d1eb RS |
4884 | load_register (AT, &imm_expr, dbl); |
4885 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4886 | break; |
4887 | ||
4888 | case M_AND_I: | |
4889 | s = "andi"; | |
4890 | s2 = "and"; | |
4891 | goto do_bit; | |
4892 | case M_OR_I: | |
4893 | s = "ori"; | |
4894 | s2 = "or"; | |
4895 | goto do_bit; | |
4896 | case M_NOR_I: | |
4897 | s = ""; | |
4898 | s2 = "nor"; | |
4899 | goto do_bit; | |
4900 | case M_XOR_I: | |
4901 | s = "xori"; | |
4902 | s2 = "xor"; | |
4903 | do_bit: | |
4904 | if (imm_expr.X_op == O_constant | |
4905 | && imm_expr.X_add_number >= 0 | |
4906 | && imm_expr.X_add_number < 0x10000) | |
4907 | { | |
4908 | if (mask != M_NOR_I) | |
67c0d1eb | 4909 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4910 | else |
4911 | { | |
67c0d1eb RS |
4912 | macro_build (&imm_expr, "ori", "t,r,i", |
4913 | treg, sreg, BFD_RELOC_LO16); | |
4914 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4915 | } |
8fc2e39e | 4916 | break; |
252b5132 RH |
4917 | } |
4918 | ||
8fc2e39e | 4919 | used_at = 1; |
67c0d1eb RS |
4920 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4921 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4922 | break; |
4923 | ||
8b082fb1 TS |
4924 | case M_BALIGN: |
4925 | switch (imm_expr.X_add_number) | |
4926 | { | |
4927 | case 0: | |
4928 | macro_build (NULL, "nop", ""); | |
4929 | break; | |
4930 | case 2: | |
4931 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
4932 | break; | |
4933 | default: | |
4934 | macro_build (NULL, "balign", "t,s,2", treg, sreg, | |
4935 | (int)imm_expr.X_add_number); | |
4936 | break; | |
4937 | } | |
4938 | break; | |
4939 | ||
252b5132 RH |
4940 | case M_BEQ_I: |
4941 | s = "beq"; | |
4942 | goto beq_i; | |
4943 | case M_BEQL_I: | |
4944 | s = "beql"; | |
4945 | likely = 1; | |
4946 | goto beq_i; | |
4947 | case M_BNE_I: | |
4948 | s = "bne"; | |
4949 | goto beq_i; | |
4950 | case M_BNEL_I: | |
4951 | s = "bnel"; | |
4952 | likely = 1; | |
4953 | beq_i: | |
4954 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4955 | { | |
67c0d1eb | 4956 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
8fc2e39e | 4957 | break; |
252b5132 | 4958 | } |
8fc2e39e | 4959 | used_at = 1; |
67c0d1eb RS |
4960 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4961 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4962 | break; |
4963 | ||
4964 | case M_BGEL: | |
4965 | likely = 1; | |
4966 | case M_BGE: | |
4967 | if (treg == 0) | |
4968 | { | |
67c0d1eb | 4969 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4970 | break; |
252b5132 RH |
4971 | } |
4972 | if (sreg == 0) | |
4973 | { | |
67c0d1eb | 4974 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 4975 | break; |
252b5132 | 4976 | } |
8fc2e39e | 4977 | used_at = 1; |
67c0d1eb RS |
4978 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4979 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4980 | break; |
4981 | ||
4982 | case M_BGTL_I: | |
4983 | likely = 1; | |
4984 | case M_BGT_I: | |
4985 | /* check for > max integer */ | |
4986 | maxnum = 0x7fffffff; | |
ca4e0257 | 4987 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4988 | { |
4989 | maxnum <<= 16; | |
4990 | maxnum |= 0xffff; | |
4991 | maxnum <<= 16; | |
4992 | maxnum |= 0xffff; | |
4993 | } | |
4994 | if (imm_expr.X_op == O_constant | |
4995 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4996 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4997 | { |
4998 | do_false: | |
4999 | /* result is always false */ | |
5000 | if (! likely) | |
67c0d1eb | 5001 | macro_build (NULL, "nop", "", 0); |
252b5132 | 5002 | else |
67c0d1eb | 5003 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
8fc2e39e | 5004 | break; |
252b5132 RH |
5005 | } |
5006 | if (imm_expr.X_op != O_constant) | |
5007 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5008 | ++imm_expr.X_add_number; |
252b5132 RH |
5009 | /* FALLTHROUGH */ |
5010 | case M_BGE_I: | |
5011 | case M_BGEL_I: | |
5012 | if (mask == M_BGEL_I) | |
5013 | likely = 1; | |
5014 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5015 | { | |
67c0d1eb | 5016 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 5017 | break; |
252b5132 RH |
5018 | } |
5019 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5020 | { | |
67c0d1eb | 5021 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 5022 | break; |
252b5132 RH |
5023 | } |
5024 | maxnum = 0x7fffffff; | |
ca4e0257 | 5025 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
5026 | { |
5027 | maxnum <<= 16; | |
5028 | maxnum |= 0xffff; | |
5029 | maxnum <<= 16; | |
5030 | maxnum |= 0xffff; | |
5031 | } | |
5032 | maxnum = - maxnum - 1; | |
5033 | if (imm_expr.X_op == O_constant | |
5034 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 5035 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5036 | { |
5037 | do_true: | |
5038 | /* result is always true */ | |
5039 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 5040 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5041 | break; |
252b5132 | 5042 | } |
8fc2e39e | 5043 | used_at = 1; |
67c0d1eb RS |
5044 | set_at (sreg, 0); |
5045 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
5046 | break; |
5047 | ||
5048 | case M_BGEUL: | |
5049 | likely = 1; | |
5050 | case M_BGEU: | |
5051 | if (treg == 0) | |
5052 | goto do_true; | |
5053 | if (sreg == 0) | |
5054 | { | |
67c0d1eb | 5055 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 5056 | "s,t,p", 0, treg); |
8fc2e39e | 5057 | break; |
252b5132 | 5058 | } |
8fc2e39e | 5059 | used_at = 1; |
67c0d1eb RS |
5060 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
5061 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
5062 | break; |
5063 | ||
5064 | case M_BGTUL_I: | |
5065 | likely = 1; | |
5066 | case M_BGTU_I: | |
5067 | if (sreg == 0 | |
ca4e0257 | 5068 | || (HAVE_32BIT_GPRS |
252b5132 | 5069 | && imm_expr.X_op == O_constant |
956cd1d6 | 5070 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
5071 | goto do_false; |
5072 | if (imm_expr.X_op != O_constant) | |
5073 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5074 | ++imm_expr.X_add_number; |
252b5132 RH |
5075 | /* FALLTHROUGH */ |
5076 | case M_BGEU_I: | |
5077 | case M_BGEUL_I: | |
5078 | if (mask == M_BGEUL_I) | |
5079 | likely = 1; | |
5080 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5081 | goto do_true; | |
5082 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5083 | { | |
67c0d1eb | 5084 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 5085 | "s,t,p", sreg, 0); |
8fc2e39e | 5086 | break; |
252b5132 | 5087 | } |
8fc2e39e | 5088 | used_at = 1; |
67c0d1eb RS |
5089 | set_at (sreg, 1); |
5090 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
5091 | break; |
5092 | ||
5093 | case M_BGTL: | |
5094 | likely = 1; | |
5095 | case M_BGT: | |
5096 | if (treg == 0) | |
5097 | { | |
67c0d1eb | 5098 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 5099 | break; |
252b5132 RH |
5100 | } |
5101 | if (sreg == 0) | |
5102 | { | |
67c0d1eb | 5103 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 5104 | break; |
252b5132 | 5105 | } |
8fc2e39e | 5106 | used_at = 1; |
67c0d1eb RS |
5107 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
5108 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5109 | break; |
5110 | ||
5111 | case M_BGTUL: | |
5112 | likely = 1; | |
5113 | case M_BGTU: | |
5114 | if (treg == 0) | |
5115 | { | |
67c0d1eb | 5116 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 5117 | "s,t,p", sreg, 0); |
8fc2e39e | 5118 | break; |
252b5132 RH |
5119 | } |
5120 | if (sreg == 0) | |
5121 | goto do_false; | |
8fc2e39e | 5122 | used_at = 1; |
67c0d1eb RS |
5123 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
5124 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5125 | break; |
5126 | ||
5127 | case M_BLEL: | |
5128 | likely = 1; | |
5129 | case M_BLE: | |
5130 | if (treg == 0) | |
5131 | { | |
67c0d1eb | 5132 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 5133 | break; |
252b5132 RH |
5134 | } |
5135 | if (sreg == 0) | |
5136 | { | |
67c0d1eb | 5137 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 5138 | break; |
252b5132 | 5139 | } |
8fc2e39e | 5140 | used_at = 1; |
67c0d1eb RS |
5141 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
5142 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
5143 | break; |
5144 | ||
5145 | case M_BLEL_I: | |
5146 | likely = 1; | |
5147 | case M_BLE_I: | |
5148 | maxnum = 0x7fffffff; | |
ca4e0257 | 5149 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
5150 | { |
5151 | maxnum <<= 16; | |
5152 | maxnum |= 0xffff; | |
5153 | maxnum <<= 16; | |
5154 | maxnum |= 0xffff; | |
5155 | } | |
5156 | if (imm_expr.X_op == O_constant | |
5157 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 5158 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5159 | goto do_true; |
5160 | if (imm_expr.X_op != O_constant) | |
5161 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5162 | ++imm_expr.X_add_number; |
252b5132 RH |
5163 | /* FALLTHROUGH */ |
5164 | case M_BLT_I: | |
5165 | case M_BLTL_I: | |
5166 | if (mask == M_BLTL_I) | |
5167 | likely = 1; | |
5168 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5169 | { | |
67c0d1eb | 5170 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 5171 | break; |
252b5132 RH |
5172 | } |
5173 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5174 | { | |
67c0d1eb | 5175 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 5176 | break; |
252b5132 | 5177 | } |
8fc2e39e | 5178 | used_at = 1; |
67c0d1eb RS |
5179 | set_at (sreg, 0); |
5180 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5181 | break; |
5182 | ||
5183 | case M_BLEUL: | |
5184 | likely = 1; | |
5185 | case M_BLEU: | |
5186 | if (treg == 0) | |
5187 | { | |
67c0d1eb | 5188 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 5189 | "s,t,p", sreg, 0); |
8fc2e39e | 5190 | break; |
252b5132 RH |
5191 | } |
5192 | if (sreg == 0) | |
5193 | goto do_true; | |
8fc2e39e | 5194 | used_at = 1; |
67c0d1eb RS |
5195 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
5196 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
5197 | break; |
5198 | ||
5199 | case M_BLEUL_I: | |
5200 | likely = 1; | |
5201 | case M_BLEU_I: | |
5202 | if (sreg == 0 | |
ca4e0257 | 5203 | || (HAVE_32BIT_GPRS |
252b5132 | 5204 | && imm_expr.X_op == O_constant |
956cd1d6 | 5205 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
5206 | goto do_true; |
5207 | if (imm_expr.X_op != O_constant) | |
5208 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5209 | ++imm_expr.X_add_number; |
252b5132 RH |
5210 | /* FALLTHROUGH */ |
5211 | case M_BLTU_I: | |
5212 | case M_BLTUL_I: | |
5213 | if (mask == M_BLTUL_I) | |
5214 | likely = 1; | |
5215 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5216 | goto do_false; | |
5217 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5218 | { | |
67c0d1eb | 5219 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 | 5220 | "s,t,p", sreg, 0); |
8fc2e39e | 5221 | break; |
252b5132 | 5222 | } |
8fc2e39e | 5223 | used_at = 1; |
67c0d1eb RS |
5224 | set_at (sreg, 1); |
5225 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5226 | break; |
5227 | ||
5228 | case M_BLTL: | |
5229 | likely = 1; | |
5230 | case M_BLT: | |
5231 | if (treg == 0) | |
5232 | { | |
67c0d1eb | 5233 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 5234 | break; |
252b5132 RH |
5235 | } |
5236 | if (sreg == 0) | |
5237 | { | |
67c0d1eb | 5238 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 5239 | break; |
252b5132 | 5240 | } |
8fc2e39e | 5241 | used_at = 1; |
67c0d1eb RS |
5242 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
5243 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5244 | break; |
5245 | ||
5246 | case M_BLTUL: | |
5247 | likely = 1; | |
5248 | case M_BLTU: | |
5249 | if (treg == 0) | |
5250 | goto do_false; | |
5251 | if (sreg == 0) | |
5252 | { | |
67c0d1eb | 5253 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 5254 | "s,t,p", 0, treg); |
8fc2e39e | 5255 | break; |
252b5132 | 5256 | } |
8fc2e39e | 5257 | used_at = 1; |
67c0d1eb RS |
5258 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
5259 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5260 | break; |
5261 | ||
5f74bc13 CD |
5262 | case M_DEXT: |
5263 | { | |
5264 | unsigned long pos; | |
5265 | unsigned long size; | |
5266 | ||
5267 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
5268 | { | |
5269 | as_bad (_("Unsupported large constant")); | |
5270 | pos = size = 1; | |
5271 | } | |
5272 | else | |
5273 | { | |
5274 | pos = (unsigned long) imm_expr.X_add_number; | |
5275 | size = (unsigned long) imm2_expr.X_add_number; | |
5276 | } | |
5277 | ||
5278 | if (pos > 63) | |
5279 | { | |
5280 | as_bad (_("Improper position (%lu)"), pos); | |
5281 | pos = 1; | |
5282 | } | |
5283 | if (size == 0 || size > 64 | |
5284 | || (pos + size - 1) > 63) | |
5285 | { | |
5286 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
5287 | size, pos); | |
5288 | size = 1; | |
5289 | } | |
5290 | ||
5291 | if (size <= 32 && pos < 32) | |
5292 | { | |
5293 | s = "dext"; | |
5294 | fmt = "t,r,+A,+C"; | |
5295 | } | |
5296 | else if (size <= 32) | |
5297 | { | |
5298 | s = "dextu"; | |
5299 | fmt = "t,r,+E,+H"; | |
5300 | } | |
5301 | else | |
5302 | { | |
5303 | s = "dextm"; | |
5304 | fmt = "t,r,+A,+G"; | |
5305 | } | |
67c0d1eb | 5306 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 | 5307 | } |
8fc2e39e | 5308 | break; |
5f74bc13 CD |
5309 | |
5310 | case M_DINS: | |
5311 | { | |
5312 | unsigned long pos; | |
5313 | unsigned long size; | |
5314 | ||
5315 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
5316 | { | |
5317 | as_bad (_("Unsupported large constant")); | |
5318 | pos = size = 1; | |
5319 | } | |
5320 | else | |
5321 | { | |
5322 | pos = (unsigned long) imm_expr.X_add_number; | |
5323 | size = (unsigned long) imm2_expr.X_add_number; | |
5324 | } | |
5325 | ||
5326 | if (pos > 63) | |
5327 | { | |
5328 | as_bad (_("Improper position (%lu)"), pos); | |
5329 | pos = 1; | |
5330 | } | |
5331 | if (size == 0 || size > 64 | |
5332 | || (pos + size - 1) > 63) | |
5333 | { | |
5334 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
5335 | size, pos); | |
5336 | size = 1; | |
5337 | } | |
5338 | ||
5339 | if (pos < 32 && (pos + size - 1) < 32) | |
5340 | { | |
5341 | s = "dins"; | |
5342 | fmt = "t,r,+A,+B"; | |
5343 | } | |
5344 | else if (pos >= 32) | |
5345 | { | |
5346 | s = "dinsu"; | |
5347 | fmt = "t,r,+E,+F"; | |
5348 | } | |
5349 | else | |
5350 | { | |
5351 | s = "dinsm"; | |
5352 | fmt = "t,r,+A,+F"; | |
5353 | } | |
750bdd57 AS |
5354 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
5355 | (int) (pos + size - 1)); | |
5f74bc13 | 5356 | } |
8fc2e39e | 5357 | break; |
5f74bc13 | 5358 | |
252b5132 RH |
5359 | case M_DDIV_3: |
5360 | dbl = 1; | |
5361 | case M_DIV_3: | |
5362 | s = "mflo"; | |
5363 | goto do_div3; | |
5364 | case M_DREM_3: | |
5365 | dbl = 1; | |
5366 | case M_REM_3: | |
5367 | s = "mfhi"; | |
5368 | do_div3: | |
5369 | if (treg == 0) | |
5370 | { | |
5371 | as_warn (_("Divide by zero.")); | |
5372 | if (mips_trap) | |
67c0d1eb | 5373 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 5374 | else |
67c0d1eb | 5375 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5376 | break; |
252b5132 RH |
5377 | } |
5378 | ||
7d10b47d | 5379 | start_noreorder (); |
252b5132 RH |
5380 | if (mips_trap) |
5381 | { | |
67c0d1eb RS |
5382 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
5383 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
5384 | } |
5385 | else | |
5386 | { | |
5387 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5388 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
5389 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
5390 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
5391 | } |
5392 | expr1.X_add_number = -1; | |
8fc2e39e | 5393 | used_at = 1; |
f6a22291 | 5394 | load_register (AT, &expr1, dbl); |
252b5132 | 5395 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 5396 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
5397 | if (dbl) |
5398 | { | |
5399 | expr1.X_add_number = 1; | |
f6a22291 | 5400 | load_register (AT, &expr1, dbl); |
67c0d1eb | 5401 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
5402 | } |
5403 | else | |
5404 | { | |
5405 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 5406 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
5407 | } |
5408 | if (mips_trap) | |
5409 | { | |
67c0d1eb | 5410 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
5411 | /* We want to close the noreorder block as soon as possible, so |
5412 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5413 | end_noreorder (); |
252b5132 RH |
5414 | } |
5415 | else | |
5416 | { | |
5417 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5418 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
5419 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
5420 | |
5421 | /* We want to close the noreorder block as soon as possible, so | |
5422 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5423 | end_noreorder (); |
252b5132 | 5424 | |
67c0d1eb | 5425 | macro_build (NULL, "break", "c", 6); |
252b5132 | 5426 | } |
67c0d1eb | 5427 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
5428 | break; |
5429 | ||
5430 | case M_DIV_3I: | |
5431 | s = "div"; | |
5432 | s2 = "mflo"; | |
5433 | goto do_divi; | |
5434 | case M_DIVU_3I: | |
5435 | s = "divu"; | |
5436 | s2 = "mflo"; | |
5437 | goto do_divi; | |
5438 | case M_REM_3I: | |
5439 | s = "div"; | |
5440 | s2 = "mfhi"; | |
5441 | goto do_divi; | |
5442 | case M_REMU_3I: | |
5443 | s = "divu"; | |
5444 | s2 = "mfhi"; | |
5445 | goto do_divi; | |
5446 | case M_DDIV_3I: | |
5447 | dbl = 1; | |
5448 | s = "ddiv"; | |
5449 | s2 = "mflo"; | |
5450 | goto do_divi; | |
5451 | case M_DDIVU_3I: | |
5452 | dbl = 1; | |
5453 | s = "ddivu"; | |
5454 | s2 = "mflo"; | |
5455 | goto do_divi; | |
5456 | case M_DREM_3I: | |
5457 | dbl = 1; | |
5458 | s = "ddiv"; | |
5459 | s2 = "mfhi"; | |
5460 | goto do_divi; | |
5461 | case M_DREMU_3I: | |
5462 | dbl = 1; | |
5463 | s = "ddivu"; | |
5464 | s2 = "mfhi"; | |
5465 | do_divi: | |
5466 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5467 | { | |
5468 | as_warn (_("Divide by zero.")); | |
5469 | if (mips_trap) | |
67c0d1eb | 5470 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 5471 | else |
67c0d1eb | 5472 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5473 | break; |
252b5132 RH |
5474 | } |
5475 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5476 | { | |
5477 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 5478 | move_register (dreg, sreg); |
252b5132 | 5479 | else |
67c0d1eb | 5480 | move_register (dreg, 0); |
8fc2e39e | 5481 | break; |
252b5132 RH |
5482 | } |
5483 | if (imm_expr.X_op == O_constant | |
5484 | && imm_expr.X_add_number == -1 | |
5485 | && s[strlen (s) - 1] != 'u') | |
5486 | { | |
5487 | if (strcmp (s2, "mflo") == 0) | |
5488 | { | |
67c0d1eb | 5489 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
5490 | } |
5491 | else | |
67c0d1eb | 5492 | move_register (dreg, 0); |
8fc2e39e | 5493 | break; |
252b5132 RH |
5494 | } |
5495 | ||
8fc2e39e | 5496 | used_at = 1; |
67c0d1eb RS |
5497 | load_register (AT, &imm_expr, dbl); |
5498 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
5499 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
5500 | break; |
5501 | ||
5502 | case M_DIVU_3: | |
5503 | s = "divu"; | |
5504 | s2 = "mflo"; | |
5505 | goto do_divu3; | |
5506 | case M_REMU_3: | |
5507 | s = "divu"; | |
5508 | s2 = "mfhi"; | |
5509 | goto do_divu3; | |
5510 | case M_DDIVU_3: | |
5511 | s = "ddivu"; | |
5512 | s2 = "mflo"; | |
5513 | goto do_divu3; | |
5514 | case M_DREMU_3: | |
5515 | s = "ddivu"; | |
5516 | s2 = "mfhi"; | |
5517 | do_divu3: | |
7d10b47d | 5518 | start_noreorder (); |
252b5132 RH |
5519 | if (mips_trap) |
5520 | { | |
67c0d1eb RS |
5521 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
5522 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
5523 | /* We want to close the noreorder block as soon as possible, so |
5524 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5525 | end_noreorder (); |
252b5132 RH |
5526 | } |
5527 | else | |
5528 | { | |
5529 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5530 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
5531 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
5532 | |
5533 | /* We want to close the noreorder block as soon as possible, so | |
5534 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5535 | end_noreorder (); |
67c0d1eb | 5536 | macro_build (NULL, "break", "c", 7); |
252b5132 | 5537 | } |
67c0d1eb | 5538 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 5539 | break; |
252b5132 | 5540 | |
1abe91b1 MR |
5541 | case M_DLCA_AB: |
5542 | dbl = 1; | |
5543 | case M_LCA_AB: | |
5544 | call = 1; | |
5545 | goto do_la; | |
252b5132 RH |
5546 | case M_DLA_AB: |
5547 | dbl = 1; | |
5548 | case M_LA_AB: | |
1abe91b1 | 5549 | do_la: |
252b5132 RH |
5550 | /* Load the address of a symbol into a register. If breg is not |
5551 | zero, we then add a base register to it. */ | |
5552 | ||
3bec30a8 TS |
5553 | if (dbl && HAVE_32BIT_GPRS) |
5554 | as_warn (_("dla used to load 32-bit register")); | |
5555 | ||
c90bbe5b | 5556 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
5557 | as_warn (_("la used to load 64-bit address")); |
5558 | ||
0c11417f MR |
5559 | if (offset_expr.X_op == O_constant |
5560 | && offset_expr.X_add_number >= -0x8000 | |
5561 | && offset_expr.X_add_number < 0x8000) | |
5562 | { | |
aed1a261 | 5563 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 5564 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 5565 | break; |
0c11417f MR |
5566 | } |
5567 | ||
741fe287 | 5568 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
5569 | { |
5570 | tempreg = AT; | |
5571 | used_at = 1; | |
5572 | } | |
5573 | else | |
5574 | { | |
5575 | tempreg = treg; | |
afdbd6d0 CD |
5576 | } |
5577 | ||
252b5132 RH |
5578 | if (offset_expr.X_op != O_symbol |
5579 | && offset_expr.X_op != O_constant) | |
5580 | { | |
5581 | as_bad (_("expression too complex")); | |
5582 | offset_expr.X_op = O_constant; | |
5583 | } | |
5584 | ||
252b5132 | 5585 | if (offset_expr.X_op == O_constant) |
aed1a261 | 5586 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5587 | else if (mips_pic == NO_PIC) |
5588 | { | |
d6bc6245 | 5589 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 5590 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5591 | Otherwise we want |
5592 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5593 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5594 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 5595 | so we may as well always use the latter form. |
76b3015f | 5596 | |
6caf9ef4 TS |
5597 | With 64bit address space and a usable $at we want |
5598 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5599 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5600 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5601 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5602 | dsll32 $tempreg,0 | |
5603 | daddu $tempreg,$tempreg,$at | |
5604 | ||
5605 | If $at is already in use, we use a path which is suboptimal | |
5606 | on superscalar processors. | |
5607 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5608 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5609 | dsll $tempreg,16 | |
5610 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5611 | dsll $tempreg,16 | |
5612 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
5613 | ||
5614 | For GP relative symbols in 64bit address space we can use | |
5615 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5616 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 5617 | { |
6caf9ef4 TS |
5618 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
5619 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5620 | { | |
5621 | relax_start (offset_expr.X_add_symbol); | |
5622 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5623 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
5624 | relax_switch (); | |
5625 | } | |
d6bc6245 | 5626 | |
741fe287 | 5627 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 5628 | { |
67c0d1eb | 5629 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5630 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5631 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5632 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 5633 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5634 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 5635 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5636 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
5637 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
5638 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
5639 | used_at = 1; |
5640 | } | |
5641 | else | |
5642 | { | |
67c0d1eb | 5643 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5644 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5645 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5646 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
5647 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5648 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5649 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
5650 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5651 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5652 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 5653 | } |
6caf9ef4 TS |
5654 | |
5655 | if (mips_relax.sequence) | |
5656 | relax_end (); | |
98d3f06f KH |
5657 | } |
5658 | else | |
5659 | { | |
5660 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 5661 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 5662 | { |
4d7206a2 | 5663 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5664 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5665 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5666 | relax_switch (); |
98d3f06f | 5667 | } |
6943caf0 ILT |
5668 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
5669 | as_bad (_("offset too large")); | |
67c0d1eb RS |
5670 | macro_build_lui (&offset_expr, tempreg); |
5671 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5672 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5673 | if (mips_relax.sequence) |
5674 | relax_end (); | |
98d3f06f | 5675 | } |
252b5132 | 5676 | } |
0a44bf69 | 5677 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 5678 | { |
9117d219 NC |
5679 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5680 | ||
252b5132 RH |
5681 | /* If this is a reference to an external symbol, and there |
5682 | is no constant, we want | |
5683 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5684 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5685 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5686 | For a local symbol, we want |
5687 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5688 | nop | |
5689 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5690 | ||
5691 | If we have a small constant, and this is a reference to | |
5692 | an external symbol, we want | |
5693 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5694 | nop | |
5695 | addiu $tempreg,$tempreg,<constant> | |
5696 | For a local symbol, we want the same instruction | |
5697 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5698 | addiu instruction. | |
5699 | ||
5700 | If we have a large constant, and this is a reference to | |
5701 | an external symbol, we want | |
5702 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5703 | lui $at,<hiconstant> | |
5704 | addiu $at,$at,<loconstant> | |
5705 | addu $tempreg,$tempreg,$at | |
5706 | For a local symbol, we want the same instruction | |
5707 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5708 | addiu instruction. |
ed6fb7bd SC |
5709 | */ |
5710 | ||
4d7206a2 | 5711 | if (offset_expr.X_add_number == 0) |
252b5132 | 5712 | { |
0a44bf69 RS |
5713 | if (mips_pic == SVR4_PIC |
5714 | && breg == 0 | |
5715 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
5716 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
5717 | ||
5718 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5719 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5720 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5721 | if (breg != 0) |
252b5132 RH |
5722 | { |
5723 | /* We're going to put in an addu instruction using | |
5724 | tempreg, so we may as well insert the nop right | |
5725 | now. */ | |
269137b2 | 5726 | load_delay_nop (); |
252b5132 | 5727 | } |
4d7206a2 | 5728 | relax_switch (); |
67c0d1eb RS |
5729 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5730 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5731 | load_delay_nop (); |
67c0d1eb RS |
5732 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5733 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5734 | relax_end (); |
252b5132 RH |
5735 | /* FIXME: If breg == 0, and the next instruction uses |
5736 | $tempreg, then if this variant case is used an extra | |
5737 | nop will be generated. */ | |
5738 | } | |
4d7206a2 RS |
5739 | else if (offset_expr.X_add_number >= -0x8000 |
5740 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5741 | { |
67c0d1eb | 5742 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5743 | load_delay_nop (); |
67c0d1eb | 5744 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5745 | } |
5746 | else | |
5747 | { | |
4d7206a2 RS |
5748 | expr1.X_add_number = offset_expr.X_add_number; |
5749 | offset_expr.X_add_number = | |
5750 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5751 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5752 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5753 | /* If we are going to add in a base register, and the |
5754 | target register and the base register are the same, | |
5755 | then we are using AT as a temporary register. Since | |
5756 | we want to load the constant into AT, we add our | |
5757 | current AT (from the global offset table) and the | |
5758 | register into the register now, and pretend we were | |
5759 | not using a base register. */ | |
67c0d1eb | 5760 | if (breg == treg) |
252b5132 | 5761 | { |
269137b2 | 5762 | load_delay_nop (); |
67c0d1eb | 5763 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5764 | treg, AT, breg); |
252b5132 RH |
5765 | breg = 0; |
5766 | tempreg = treg; | |
252b5132 | 5767 | } |
f6a22291 | 5768 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5769 | used_at = 1; |
5770 | } | |
5771 | } | |
0a44bf69 | 5772 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 5773 | { |
67c0d1eb | 5774 | int add_breg_early = 0; |
f5040a92 AO |
5775 | |
5776 | /* If this is a reference to an external, and there is no | |
5777 | constant, or local symbol (*), with or without a | |
5778 | constant, we want | |
5779 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5780 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5781 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5782 | ||
5783 | If we have a small constant, and this is a reference to | |
5784 | an external symbol, we want | |
5785 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5786 | addiu $tempreg,$tempreg,<constant> | |
5787 | ||
5788 | If we have a large constant, and this is a reference to | |
5789 | an external symbol, we want | |
5790 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5791 | lui $at,<hiconstant> | |
5792 | addiu $at,$at,<loconstant> | |
5793 | addu $tempreg,$tempreg,$at | |
5794 | ||
5795 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5796 | local symbols, even though it introduces an additional | |
5797 | instruction. */ | |
5798 | ||
f5040a92 AO |
5799 | if (offset_expr.X_add_number) |
5800 | { | |
4d7206a2 | 5801 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5802 | offset_expr.X_add_number = 0; |
5803 | ||
4d7206a2 | 5804 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5805 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5806 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5807 | |
5808 | if (expr1.X_add_number >= -0x8000 | |
5809 | && expr1.X_add_number < 0x8000) | |
5810 | { | |
67c0d1eb RS |
5811 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5812 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5813 | } |
ecd13cd3 | 5814 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 5815 | { |
f5040a92 AO |
5816 | /* If we are going to add in a base register, and the |
5817 | target register and the base register are the same, | |
5818 | then we are using AT as a temporary register. Since | |
5819 | we want to load the constant into AT, we add our | |
5820 | current AT (from the global offset table) and the | |
5821 | register into the register now, and pretend we were | |
5822 | not using a base register. */ | |
5823 | if (breg != treg) | |
5824 | dreg = tempreg; | |
5825 | else | |
5826 | { | |
9c2799c2 | 5827 | gas_assert (tempreg == AT); |
67c0d1eb RS |
5828 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5829 | treg, AT, breg); | |
f5040a92 | 5830 | dreg = treg; |
67c0d1eb | 5831 | add_breg_early = 1; |
f5040a92 AO |
5832 | } |
5833 | ||
f6a22291 | 5834 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5835 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5836 | dreg, dreg, AT); |
f5040a92 | 5837 | |
f5040a92 AO |
5838 | used_at = 1; |
5839 | } | |
5840 | else | |
5841 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5842 | ||
4d7206a2 | 5843 | relax_switch (); |
f5040a92 AO |
5844 | offset_expr.X_add_number = expr1.X_add_number; |
5845 | ||
67c0d1eb RS |
5846 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5847 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5848 | if (add_breg_early) | |
f5040a92 | 5849 | { |
67c0d1eb | 5850 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5851 | treg, tempreg, breg); |
f5040a92 AO |
5852 | breg = 0; |
5853 | tempreg = treg; | |
5854 | } | |
4d7206a2 | 5855 | relax_end (); |
f5040a92 | 5856 | } |
4d7206a2 | 5857 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5858 | { |
4d7206a2 | 5859 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5860 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5861 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5862 | relax_switch (); |
67c0d1eb RS |
5863 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5864 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5865 | relax_end (); |
f5040a92 | 5866 | } |
4d7206a2 | 5867 | else |
f5040a92 | 5868 | { |
67c0d1eb RS |
5869 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5870 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5871 | } |
5872 | } | |
0a44bf69 | 5873 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 5874 | { |
67c0d1eb | 5875 | int gpdelay; |
9117d219 NC |
5876 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5877 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5878 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5879 | |
5880 | /* This is the large GOT case. If this is a reference to an | |
5881 | external symbol, and there is no constant, we want | |
5882 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5883 | addu $tempreg,$tempreg,$gp | |
5884 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5885 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5886 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5887 | addu $tempreg,$tempreg,$gp | |
5888 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5889 | For a local symbol, we want |
5890 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5891 | nop | |
5892 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5893 | ||
5894 | If we have a small constant, and this is a reference to | |
5895 | an external symbol, we want | |
5896 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5897 | addu $tempreg,$tempreg,$gp | |
5898 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5899 | nop | |
5900 | addiu $tempreg,$tempreg,<constant> | |
5901 | For a local symbol, we want | |
5902 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5903 | nop | |
5904 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5905 | ||
5906 | If we have a large constant, and this is a reference to | |
5907 | an external symbol, we want | |
5908 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5909 | addu $tempreg,$tempreg,$gp | |
5910 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5911 | lui $at,<hiconstant> | |
5912 | addiu $at,$at,<loconstant> | |
5913 | addu $tempreg,$tempreg,$at | |
5914 | For a local symbol, we want | |
5915 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5916 | lui $at,<hiconstant> | |
5917 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5918 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5919 | */ |
438c16b8 | 5920 | |
252b5132 RH |
5921 | expr1.X_add_number = offset_expr.X_add_number; |
5922 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5923 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5924 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5925 | if (expr1.X_add_number == 0 && breg == 0 |
5926 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5927 | { |
5928 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5929 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5930 | } | |
67c0d1eb RS |
5931 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5932 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5933 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5934 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5935 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5936 | if (expr1.X_add_number == 0) |
5937 | { | |
67c0d1eb | 5938 | if (breg != 0) |
252b5132 RH |
5939 | { |
5940 | /* We're going to put in an addu instruction using | |
5941 | tempreg, so we may as well insert the nop right | |
5942 | now. */ | |
269137b2 | 5943 | load_delay_nop (); |
252b5132 | 5944 | } |
252b5132 RH |
5945 | } |
5946 | else if (expr1.X_add_number >= -0x8000 | |
5947 | && expr1.X_add_number < 0x8000) | |
5948 | { | |
269137b2 | 5949 | load_delay_nop (); |
67c0d1eb | 5950 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5951 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5952 | } |
5953 | else | |
5954 | { | |
252b5132 RH |
5955 | /* If we are going to add in a base register, and the |
5956 | target register and the base register are the same, | |
5957 | then we are using AT as a temporary register. Since | |
5958 | we want to load the constant into AT, we add our | |
5959 | current AT (from the global offset table) and the | |
5960 | register into the register now, and pretend we were | |
5961 | not using a base register. */ | |
5962 | if (breg != treg) | |
67c0d1eb | 5963 | dreg = tempreg; |
252b5132 RH |
5964 | else |
5965 | { | |
9c2799c2 | 5966 | gas_assert (tempreg == AT); |
269137b2 | 5967 | load_delay_nop (); |
67c0d1eb | 5968 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5969 | treg, AT, breg); |
252b5132 | 5970 | dreg = treg; |
252b5132 RH |
5971 | } |
5972 | ||
f6a22291 | 5973 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5974 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5975 | |
252b5132 RH |
5976 | used_at = 1; |
5977 | } | |
4d7206a2 RS |
5978 | offset_expr.X_add_number = |
5979 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5980 | relax_switch (); | |
252b5132 | 5981 | |
67c0d1eb | 5982 | if (gpdelay) |
252b5132 RH |
5983 | { |
5984 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5985 | the first instruction on the main stream does not. */ |
67c0d1eb | 5986 | macro_build (NULL, "nop", ""); |
252b5132 | 5987 | } |
ed6fb7bd | 5988 | |
67c0d1eb RS |
5989 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5990 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5991 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5992 | && expr1.X_add_number < 0x8000) |
5993 | { | |
269137b2 | 5994 | load_delay_nop (); |
67c0d1eb RS |
5995 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5996 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5997 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5998 | register, the external symbol case ended with a load, |
5999 | so if the symbol turns out to not be external, and | |
6000 | the next instruction uses tempreg, an unnecessary nop | |
6001 | will be inserted. */ | |
252b5132 RH |
6002 | } |
6003 | else | |
6004 | { | |
6005 | if (breg == treg) | |
6006 | { | |
6007 | /* We must add in the base register now, as in the | |
f5040a92 | 6008 | external symbol case. */ |
9c2799c2 | 6009 | gas_assert (tempreg == AT); |
269137b2 | 6010 | load_delay_nop (); |
67c0d1eb | 6011 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6012 | treg, AT, breg); |
252b5132 RH |
6013 | tempreg = treg; |
6014 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 6015 | it in in both cases. */ |
252b5132 RH |
6016 | breg = 0; |
6017 | } | |
6018 | ||
67c0d1eb RS |
6019 | macro_build_lui (&expr1, AT); |
6020 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 6021 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 6022 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6023 | tempreg, tempreg, AT); |
8fc2e39e | 6024 | used_at = 1; |
252b5132 | 6025 | } |
4d7206a2 | 6026 | relax_end (); |
252b5132 | 6027 | } |
0a44bf69 | 6028 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6029 | { |
f5040a92 AO |
6030 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
6031 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 6032 | int add_breg_early = 0; |
f5040a92 AO |
6033 | |
6034 | /* This is the large GOT case. If this is a reference to an | |
6035 | external symbol, and there is no constant, we want | |
6036 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6037 | add $tempreg,$tempreg,$gp | |
6038 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 6039 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
6040 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
6041 | add $tempreg,$tempreg,$gp | |
6042 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
6043 | ||
6044 | If we have a small constant, and this is a reference to | |
6045 | an external symbol, we want | |
6046 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6047 | add $tempreg,$tempreg,$gp | |
6048 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6049 | addi $tempreg,$tempreg,<constant> | |
6050 | ||
6051 | If we have a large constant, and this is a reference to | |
6052 | an external symbol, we want | |
6053 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6054 | addu $tempreg,$tempreg,$gp | |
6055 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6056 | lui $at,<hiconstant> | |
6057 | addi $at,$at,<loconstant> | |
6058 | add $tempreg,$tempreg,$at | |
6059 | ||
6060 | If we have NewABI, and we know it's a local symbol, we want | |
6061 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6062 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
6063 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
6064 | ||
4d7206a2 | 6065 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 6066 | |
4d7206a2 | 6067 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6068 | offset_expr.X_add_number = 0; |
6069 | ||
1abe91b1 MR |
6070 | if (expr1.X_add_number == 0 && breg == 0 |
6071 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
6072 | { |
6073 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
6074 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
6075 | } | |
67c0d1eb RS |
6076 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
6077 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6078 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
6079 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6080 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
6081 | |
6082 | if (expr1.X_add_number == 0) | |
4d7206a2 | 6083 | ; |
f5040a92 AO |
6084 | else if (expr1.X_add_number >= -0x8000 |
6085 | && expr1.X_add_number < 0x8000) | |
6086 | { | |
67c0d1eb | 6087 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6088 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 6089 | } |
ecd13cd3 | 6090 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 6091 | { |
f5040a92 AO |
6092 | /* If we are going to add in a base register, and the |
6093 | target register and the base register are the same, | |
6094 | then we are using AT as a temporary register. Since | |
6095 | we want to load the constant into AT, we add our | |
6096 | current AT (from the global offset table) and the | |
6097 | register into the register now, and pretend we were | |
6098 | not using a base register. */ | |
6099 | if (breg != treg) | |
6100 | dreg = tempreg; | |
6101 | else | |
6102 | { | |
9c2799c2 | 6103 | gas_assert (tempreg == AT); |
67c0d1eb | 6104 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6105 | treg, AT, breg); |
f5040a92 | 6106 | dreg = treg; |
67c0d1eb | 6107 | add_breg_early = 1; |
f5040a92 AO |
6108 | } |
6109 | ||
f6a22291 | 6110 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 6111 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 6112 | |
f5040a92 AO |
6113 | used_at = 1; |
6114 | } | |
6115 | else | |
6116 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
6117 | ||
4d7206a2 | 6118 | relax_switch (); |
f5040a92 | 6119 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6120 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6121 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
6122 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
6123 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
6124 | if (add_breg_early) | |
f5040a92 | 6125 | { |
67c0d1eb | 6126 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6127 | treg, tempreg, breg); |
f5040a92 AO |
6128 | breg = 0; |
6129 | tempreg = treg; | |
6130 | } | |
4d7206a2 | 6131 | relax_end (); |
f5040a92 | 6132 | } |
252b5132 RH |
6133 | else |
6134 | abort (); | |
6135 | ||
6136 | if (breg != 0) | |
aed1a261 | 6137 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
6138 | break; |
6139 | ||
52b6b6b9 JM |
6140 | case M_MSGSND: |
6141 | { | |
6142 | unsigned long temp = (treg << 16) | (0x01); | |
6143 | macro_build (NULL, "c2", "C", temp); | |
6144 | } | |
6145 | /* AT is not used, just return */ | |
6146 | return; | |
6147 | ||
6148 | case M_MSGLD: | |
6149 | { | |
6150 | unsigned long temp = (0x02); | |
6151 | macro_build (NULL, "c2", "C", temp); | |
6152 | } | |
6153 | /* AT is not used, just return */ | |
6154 | return; | |
6155 | ||
6156 | case M_MSGLD_T: | |
6157 | { | |
6158 | unsigned long temp = (treg << 16) | (0x02); | |
6159 | macro_build (NULL, "c2", "C", temp); | |
6160 | } | |
6161 | /* AT is not used, just return */ | |
6162 | return; | |
6163 | ||
6164 | case M_MSGWAIT: | |
6165 | macro_build (NULL, "c2", "C", 3); | |
6166 | /* AT is not used, just return */ | |
6167 | return; | |
6168 | ||
6169 | case M_MSGWAIT_T: | |
6170 | { | |
6171 | unsigned long temp = (treg << 16) | 0x03; | |
6172 | macro_build (NULL, "c2", "C", temp); | |
6173 | } | |
6174 | /* AT is not used, just return */ | |
6175 | return; | |
6176 | ||
252b5132 RH |
6177 | case M_J_A: |
6178 | /* The j instruction may not be used in PIC code, since it | |
6179 | requires an absolute address. We convert it to a b | |
6180 | instruction. */ | |
6181 | if (mips_pic == NO_PIC) | |
67c0d1eb | 6182 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 6183 | else |
67c0d1eb | 6184 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6185 | break; |
252b5132 RH |
6186 | |
6187 | /* The jal instructions must be handled as macros because when | |
6188 | generating PIC code they expand to multi-instruction | |
6189 | sequences. Normally they are simple instructions. */ | |
6190 | case M_JAL_1: | |
6191 | dreg = RA; | |
6192 | /* Fall through. */ | |
6193 | case M_JAL_2: | |
3e722fb5 | 6194 | if (mips_pic == NO_PIC) |
67c0d1eb | 6195 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 6196 | else |
252b5132 RH |
6197 | { |
6198 | if (sreg != PIC_CALL_REG) | |
6199 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 6200 | |
67c0d1eb | 6201 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 6202 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 6203 | { |
6478892d TS |
6204 | if (mips_cprestore_offset < 0) |
6205 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6206 | else | |
6207 | { | |
7a621144 DJ |
6208 | if (! mips_frame_reg_valid) |
6209 | { | |
6210 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6211 | /* Quiet this warning. */ | |
6212 | mips_frame_reg_valid = 1; | |
6213 | } | |
6214 | if (! mips_cprestore_valid) | |
6215 | { | |
6216 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6217 | /* Quiet this warning. */ | |
6218 | mips_cprestore_valid = 1; | |
6219 | } | |
6478892d | 6220 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6221 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6222 | mips_gp_register, |
256ab948 TS |
6223 | mips_frame_reg, |
6224 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6225 | } |
252b5132 RH |
6226 | } |
6227 | } | |
252b5132 | 6228 | |
8fc2e39e | 6229 | break; |
252b5132 RH |
6230 | |
6231 | case M_JAL_A: | |
6232 | if (mips_pic == NO_PIC) | |
67c0d1eb | 6233 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
6234 | else if (mips_pic == SVR4_PIC) |
6235 | { | |
6236 | /* If this is a reference to an external symbol, and we are | |
6237 | using a small GOT, we want | |
6238 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
6239 | nop | |
f9419b05 | 6240 | jalr $ra,$25 |
252b5132 RH |
6241 | nop |
6242 | lw $gp,cprestore($sp) | |
6243 | The cprestore value is set using the .cprestore | |
6244 | pseudo-op. If we are using a big GOT, we want | |
6245 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
6246 | addu $25,$25,$gp | |
6247 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
6248 | nop | |
f9419b05 | 6249 | jalr $ra,$25 |
252b5132 RH |
6250 | nop |
6251 | lw $gp,cprestore($sp) | |
6252 | If the symbol is not external, we want | |
6253 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6254 | nop | |
6255 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 6256 | jalr $ra,$25 |
252b5132 | 6257 | nop |
438c16b8 | 6258 | lw $gp,cprestore($sp) |
f5040a92 AO |
6259 | |
6260 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
6261 | sequences above, minus nops, unless the symbol is local, | |
6262 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
6263 | GOT_DISP. */ | |
438c16b8 | 6264 | if (HAVE_NEWABI) |
252b5132 | 6265 | { |
f5040a92 AO |
6266 | if (! mips_big_got) |
6267 | { | |
4d7206a2 | 6268 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6269 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6270 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 6271 | mips_gp_register); |
4d7206a2 | 6272 | relax_switch (); |
67c0d1eb RS |
6273 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6274 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
6275 | mips_gp_register); |
6276 | relax_end (); | |
f5040a92 AO |
6277 | } |
6278 | else | |
6279 | { | |
4d7206a2 | 6280 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6281 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
6282 | BFD_RELOC_MIPS_CALL_HI16); | |
6283 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6284 | PIC_CALL_REG, mips_gp_register); | |
6285 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6286 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6287 | PIC_CALL_REG); | |
4d7206a2 | 6288 | relax_switch (); |
67c0d1eb RS |
6289 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6290 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
6291 | mips_gp_register); | |
6292 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
6293 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 6294 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 6295 | relax_end (); |
f5040a92 | 6296 | } |
684022ea | 6297 | |
67c0d1eb | 6298 | macro_build_jalr (&offset_expr); |
252b5132 RH |
6299 | } |
6300 | else | |
6301 | { | |
4d7206a2 | 6302 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
6303 | if (! mips_big_got) |
6304 | { | |
67c0d1eb RS |
6305 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6306 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 6307 | mips_gp_register); |
269137b2 | 6308 | load_delay_nop (); |
4d7206a2 | 6309 | relax_switch (); |
438c16b8 | 6310 | } |
252b5132 | 6311 | else |
252b5132 | 6312 | { |
67c0d1eb RS |
6313 | int gpdelay; |
6314 | ||
6315 | gpdelay = reg_needs_delay (mips_gp_register); | |
6316 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
6317 | BFD_RELOC_MIPS_CALL_HI16); | |
6318 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6319 | PIC_CALL_REG, mips_gp_register); | |
6320 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6321 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6322 | PIC_CALL_REG); | |
269137b2 | 6323 | load_delay_nop (); |
4d7206a2 | 6324 | relax_switch (); |
67c0d1eb RS |
6325 | if (gpdelay) |
6326 | macro_build (NULL, "nop", ""); | |
252b5132 | 6327 | } |
67c0d1eb RS |
6328 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6329 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 6330 | mips_gp_register); |
269137b2 | 6331 | load_delay_nop (); |
67c0d1eb RS |
6332 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6333 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 6334 | relax_end (); |
67c0d1eb | 6335 | macro_build_jalr (&offset_expr); |
438c16b8 | 6336 | |
6478892d TS |
6337 | if (mips_cprestore_offset < 0) |
6338 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6339 | else | |
6340 | { | |
7a621144 DJ |
6341 | if (! mips_frame_reg_valid) |
6342 | { | |
6343 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6344 | /* Quiet this warning. */ | |
6345 | mips_frame_reg_valid = 1; | |
6346 | } | |
6347 | if (! mips_cprestore_valid) | |
6348 | { | |
6349 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6350 | /* Quiet this warning. */ | |
6351 | mips_cprestore_valid = 1; | |
6352 | } | |
6478892d | 6353 | if (mips_opts.noreorder) |
67c0d1eb | 6354 | macro_build (NULL, "nop", ""); |
6478892d | 6355 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6356 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6357 | mips_gp_register, |
256ab948 TS |
6358 | mips_frame_reg, |
6359 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6360 | } |
252b5132 RH |
6361 | } |
6362 | } | |
0a44bf69 RS |
6363 | else if (mips_pic == VXWORKS_PIC) |
6364 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
6365 | else |
6366 | abort (); | |
6367 | ||
8fc2e39e | 6368 | break; |
252b5132 RH |
6369 | |
6370 | case M_LB_AB: | |
6371 | s = "lb"; | |
6372 | goto ld; | |
6373 | case M_LBU_AB: | |
6374 | s = "lbu"; | |
6375 | goto ld; | |
6376 | case M_LH_AB: | |
6377 | s = "lh"; | |
6378 | goto ld; | |
6379 | case M_LHU_AB: | |
6380 | s = "lhu"; | |
6381 | goto ld; | |
6382 | case M_LW_AB: | |
6383 | s = "lw"; | |
6384 | goto ld; | |
6385 | case M_LWC0_AB: | |
6386 | s = "lwc0"; | |
bdaaa2e1 | 6387 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6388 | coproc = 1; |
6389 | goto ld; | |
6390 | case M_LWC1_AB: | |
6391 | s = "lwc1"; | |
bdaaa2e1 | 6392 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6393 | coproc = 1; |
6394 | goto ld; | |
6395 | case M_LWC2_AB: | |
6396 | s = "lwc2"; | |
bdaaa2e1 | 6397 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6398 | coproc = 1; |
6399 | goto ld; | |
6400 | case M_LWC3_AB: | |
6401 | s = "lwc3"; | |
bdaaa2e1 | 6402 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6403 | coproc = 1; |
6404 | goto ld; | |
6405 | case M_LWL_AB: | |
6406 | s = "lwl"; | |
6407 | lr = 1; | |
6408 | goto ld; | |
6409 | case M_LWR_AB: | |
6410 | s = "lwr"; | |
6411 | lr = 1; | |
6412 | goto ld; | |
6413 | case M_LDC1_AB: | |
252b5132 | 6414 | s = "ldc1"; |
bdaaa2e1 | 6415 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6416 | coproc = 1; |
6417 | goto ld; | |
6418 | case M_LDC2_AB: | |
6419 | s = "ldc2"; | |
bdaaa2e1 | 6420 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6421 | coproc = 1; |
6422 | goto ld; | |
6423 | case M_LDC3_AB: | |
6424 | s = "ldc3"; | |
bdaaa2e1 | 6425 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6426 | coproc = 1; |
6427 | goto ld; | |
6428 | case M_LDL_AB: | |
6429 | s = "ldl"; | |
6430 | lr = 1; | |
6431 | goto ld; | |
6432 | case M_LDR_AB: | |
6433 | s = "ldr"; | |
6434 | lr = 1; | |
6435 | goto ld; | |
6436 | case M_LL_AB: | |
6437 | s = "ll"; | |
6438 | goto ld; | |
6439 | case M_LLD_AB: | |
6440 | s = "lld"; | |
6441 | goto ld; | |
6442 | case M_LWU_AB: | |
6443 | s = "lwu"; | |
6444 | ld: | |
8fc2e39e | 6445 | if (breg == treg || coproc || lr) |
252b5132 RH |
6446 | { |
6447 | tempreg = AT; | |
6448 | used_at = 1; | |
6449 | } | |
6450 | else | |
6451 | { | |
6452 | tempreg = treg; | |
252b5132 RH |
6453 | } |
6454 | goto ld_st; | |
6455 | case M_SB_AB: | |
6456 | s = "sb"; | |
6457 | goto st; | |
6458 | case M_SH_AB: | |
6459 | s = "sh"; | |
6460 | goto st; | |
6461 | case M_SW_AB: | |
6462 | s = "sw"; | |
6463 | goto st; | |
6464 | case M_SWC0_AB: | |
6465 | s = "swc0"; | |
bdaaa2e1 | 6466 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6467 | coproc = 1; |
6468 | goto st; | |
6469 | case M_SWC1_AB: | |
6470 | s = "swc1"; | |
bdaaa2e1 | 6471 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6472 | coproc = 1; |
6473 | goto st; | |
6474 | case M_SWC2_AB: | |
6475 | s = "swc2"; | |
bdaaa2e1 | 6476 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6477 | coproc = 1; |
6478 | goto st; | |
6479 | case M_SWC3_AB: | |
6480 | s = "swc3"; | |
bdaaa2e1 | 6481 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6482 | coproc = 1; |
6483 | goto st; | |
6484 | case M_SWL_AB: | |
6485 | s = "swl"; | |
6486 | goto st; | |
6487 | case M_SWR_AB: | |
6488 | s = "swr"; | |
6489 | goto st; | |
6490 | case M_SC_AB: | |
6491 | s = "sc"; | |
6492 | goto st; | |
6493 | case M_SCD_AB: | |
6494 | s = "scd"; | |
6495 | goto st; | |
d43b4baf TS |
6496 | case M_CACHE_AB: |
6497 | s = "cache"; | |
6498 | goto st; | |
252b5132 | 6499 | case M_SDC1_AB: |
252b5132 RH |
6500 | s = "sdc1"; |
6501 | coproc = 1; | |
bdaaa2e1 | 6502 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6503 | goto st; |
6504 | case M_SDC2_AB: | |
6505 | s = "sdc2"; | |
bdaaa2e1 | 6506 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6507 | coproc = 1; |
6508 | goto st; | |
6509 | case M_SDC3_AB: | |
6510 | s = "sdc3"; | |
bdaaa2e1 | 6511 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6512 | coproc = 1; |
6513 | goto st; | |
6514 | case M_SDL_AB: | |
6515 | s = "sdl"; | |
6516 | goto st; | |
6517 | case M_SDR_AB: | |
6518 | s = "sdr"; | |
6519 | st: | |
8fc2e39e TS |
6520 | tempreg = AT; |
6521 | used_at = 1; | |
252b5132 | 6522 | ld_st: |
b19e8a9b AN |
6523 | if (coproc |
6524 | && NO_ISA_COP (mips_opts.arch) | |
6525 | && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0) | |
6526 | { | |
6527 | as_bad (_("opcode not supported on this processor: %s"), | |
6528 | mips_cpu_info_from_arch (mips_opts.arch)->name); | |
6529 | break; | |
6530 | } | |
6531 | ||
bdaaa2e1 | 6532 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6533 | if (mask == M_LWC1_AB |
6534 | || mask == M_SWC1_AB | |
6535 | || mask == M_LDC1_AB | |
6536 | || mask == M_SDC1_AB | |
6537 | || mask == M_L_DAB | |
6538 | || mask == M_S_DAB) | |
6539 | fmt = "T,o(b)"; | |
d43b4baf TS |
6540 | else if (mask == M_CACHE_AB) |
6541 | fmt = "k,o(b)"; | |
252b5132 RH |
6542 | else if (coproc) |
6543 | fmt = "E,o(b)"; | |
6544 | else | |
6545 | fmt = "t,o(b)"; | |
6546 | ||
6547 | if (offset_expr.X_op != O_constant | |
6548 | && offset_expr.X_op != O_symbol) | |
6549 | { | |
6550 | as_bad (_("expression too complex")); | |
6551 | offset_expr.X_op = O_constant; | |
6552 | } | |
6553 | ||
2051e8c4 MR |
6554 | if (HAVE_32BIT_ADDRESSES |
6555 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6556 | { |
6557 | char value [32]; | |
6558 | ||
6559 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6560 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6561 | } |
2051e8c4 | 6562 | |
252b5132 RH |
6563 | /* A constant expression in PIC code can be handled just as it |
6564 | is in non PIC code. */ | |
aed1a261 RS |
6565 | if (offset_expr.X_op == O_constant) |
6566 | { | |
aed1a261 RS |
6567 | expr1.X_add_number = ((offset_expr.X_add_number + 0x8000) |
6568 | & ~(bfd_vma) 0xffff); | |
2051e8c4 | 6569 | normalize_address_expr (&expr1); |
aed1a261 RS |
6570 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
6571 | if (breg != 0) | |
6572 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6573 | tempreg, tempreg, breg); | |
6574 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); | |
6575 | } | |
6576 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
6577 | { |
6578 | /* If this is a reference to a GP relative symbol, and there | |
6579 | is no base register, we want | |
cdf6fd85 | 6580 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6581 | Otherwise, if there is no base register, we want |
6582 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6583 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6584 | If we have a constant, we need two instructions anyhow, | |
6585 | so we always use the latter form. | |
6586 | ||
6587 | If we have a base register, and this is a reference to a | |
6588 | GP relative symbol, we want | |
6589 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6590 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6591 | Otherwise we want |
6592 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6593 | addu $tempreg,$tempreg,$breg | |
6594 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 6595 | With a constant we always use the latter case. |
76b3015f | 6596 | |
d6bc6245 TS |
6597 | With 64bit address space and no base register and $at usable, |
6598 | we want | |
6599 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6600 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6601 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6602 | dsll32 $tempreg,0 | |
6603 | daddu $tempreg,$at | |
6604 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6605 | If we have a base register, we want | |
6606 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6607 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6608 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6609 | daddu $at,$breg | |
6610 | dsll32 $tempreg,0 | |
6611 | daddu $tempreg,$at | |
6612 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6613 | ||
6614 | Without $at we can't generate the optimal path for superscalar | |
6615 | processors here since this would require two temporary registers. | |
6616 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6617 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6618 | dsll $tempreg,16 | |
6619 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6620 | dsll $tempreg,16 | |
6621 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6622 | If we have a base register, we want | |
6623 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6624 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6625 | dsll $tempreg,16 | |
6626 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6627 | dsll $tempreg,16 | |
6628 | daddu $tempreg,$tempreg,$breg | |
6629 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 6630 | |
6caf9ef4 | 6631 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
6632 | the same sequence as in 32bit address space. */ |
6633 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 6634 | { |
aed1a261 | 6635 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
6636 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6637 | { | |
6638 | relax_start (offset_expr.X_add_symbol); | |
6639 | if (breg == 0) | |
6640 | { | |
6641 | macro_build (&offset_expr, s, fmt, treg, | |
6642 | BFD_RELOC_GPREL16, mips_gp_register); | |
6643 | } | |
6644 | else | |
6645 | { | |
6646 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6647 | tempreg, breg, mips_gp_register); | |
6648 | macro_build (&offset_expr, s, fmt, treg, | |
6649 | BFD_RELOC_GPREL16, tempreg); | |
6650 | } | |
6651 | relax_switch (); | |
6652 | } | |
d6bc6245 | 6653 | |
741fe287 | 6654 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 6655 | { |
67c0d1eb RS |
6656 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6657 | BFD_RELOC_MIPS_HIGHEST); | |
6658 | macro_build (&offset_expr, "lui", "t,u", AT, | |
6659 | BFD_RELOC_HI16_S); | |
6660 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6661 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 6662 | if (breg != 0) |
67c0d1eb RS |
6663 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
6664 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
6665 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
6666 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
6667 | tempreg); | |
d6bc6245 TS |
6668 | used_at = 1; |
6669 | } | |
6670 | else | |
6671 | { | |
67c0d1eb RS |
6672 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6673 | BFD_RELOC_MIPS_HIGHEST); | |
6674 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6675 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6676 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6677 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6678 | tempreg, BFD_RELOC_HI16_S); | |
6679 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6680 | if (breg != 0) |
67c0d1eb | 6681 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6682 | tempreg, tempreg, breg); |
67c0d1eb | 6683 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6684 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 6685 | } |
6caf9ef4 TS |
6686 | |
6687 | if (mips_relax.sequence) | |
6688 | relax_end (); | |
8fc2e39e | 6689 | break; |
d6bc6245 | 6690 | } |
256ab948 | 6691 | |
252b5132 RH |
6692 | if (breg == 0) |
6693 | { | |
67c0d1eb | 6694 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6695 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6696 | { |
4d7206a2 | 6697 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6698 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6699 | mips_gp_register); | |
4d7206a2 | 6700 | relax_switch (); |
252b5132 | 6701 | } |
67c0d1eb RS |
6702 | macro_build_lui (&offset_expr, tempreg); |
6703 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6704 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6705 | if (mips_relax.sequence) |
6706 | relax_end (); | |
252b5132 RH |
6707 | } |
6708 | else | |
6709 | { | |
67c0d1eb | 6710 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6711 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6712 | { |
4d7206a2 | 6713 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6714 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6715 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6716 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6717 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6718 | relax_switch (); |
252b5132 | 6719 | } |
67c0d1eb RS |
6720 | macro_build_lui (&offset_expr, tempreg); |
6721 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6722 | tempreg, tempreg, breg); |
67c0d1eb | 6723 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6724 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6725 | if (mips_relax.sequence) |
6726 | relax_end (); | |
252b5132 RH |
6727 | } |
6728 | } | |
0a44bf69 | 6729 | else if (!mips_big_got) |
252b5132 | 6730 | { |
ed6fb7bd | 6731 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6732 | |
252b5132 RH |
6733 | /* If this is a reference to an external symbol, we want |
6734 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6735 | nop | |
6736 | <op> $treg,0($tempreg) | |
6737 | Otherwise we want | |
6738 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6739 | nop | |
6740 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6741 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6742 | |
6743 | For NewABI, we want | |
6744 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6745 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6746 | ||
252b5132 RH |
6747 | If there is a base register, we add it to $tempreg before |
6748 | the <op>. If there is a constant, we stick it in the | |
6749 | <op> instruction. We don't handle constants larger than | |
6750 | 16 bits, because we have no way to load the upper 16 bits | |
6751 | (actually, we could handle them for the subset of cases | |
6752 | in which we are not using $at). */ | |
9c2799c2 | 6753 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
6754 | if (HAVE_NEWABI) |
6755 | { | |
67c0d1eb RS |
6756 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6757 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6758 | if (breg != 0) |
67c0d1eb | 6759 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6760 | tempreg, tempreg, breg); |
67c0d1eb | 6761 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6762 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6763 | break; |
6764 | } | |
252b5132 RH |
6765 | expr1.X_add_number = offset_expr.X_add_number; |
6766 | offset_expr.X_add_number = 0; | |
6767 | if (expr1.X_add_number < -0x8000 | |
6768 | || expr1.X_add_number >= 0x8000) | |
6769 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6770 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6771 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6772 | load_delay_nop (); |
4d7206a2 RS |
6773 | relax_start (offset_expr.X_add_symbol); |
6774 | relax_switch (); | |
67c0d1eb RS |
6775 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6776 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6777 | relax_end (); |
252b5132 | 6778 | if (breg != 0) |
67c0d1eb | 6779 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6780 | tempreg, tempreg, breg); |
67c0d1eb | 6781 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6782 | } |
0a44bf69 | 6783 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 6784 | { |
67c0d1eb | 6785 | int gpdelay; |
252b5132 RH |
6786 | |
6787 | /* If this is a reference to an external symbol, we want | |
6788 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6789 | addu $tempreg,$tempreg,$gp | |
6790 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6791 | <op> $treg,0($tempreg) | |
6792 | Otherwise we want | |
6793 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6794 | nop | |
6795 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6796 | <op> $treg,0($tempreg) | |
6797 | If there is a base register, we add it to $tempreg before | |
6798 | the <op>. If there is a constant, we stick it in the | |
6799 | <op> instruction. We don't handle constants larger than | |
6800 | 16 bits, because we have no way to load the upper 16 bits | |
6801 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6802 | in which we are not using $at). */ |
9c2799c2 | 6803 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
6804 | expr1.X_add_number = offset_expr.X_add_number; |
6805 | offset_expr.X_add_number = 0; | |
6806 | if (expr1.X_add_number < -0x8000 | |
6807 | || expr1.X_add_number >= 0x8000) | |
6808 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6809 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6810 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6811 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6812 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6813 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6814 | mips_gp_register); | |
6815 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6816 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6817 | relax_switch (); |
67c0d1eb RS |
6818 | if (gpdelay) |
6819 | macro_build (NULL, "nop", ""); | |
6820 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6821 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6822 | load_delay_nop (); |
67c0d1eb RS |
6823 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6824 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6825 | relax_end (); |
6826 | ||
252b5132 | 6827 | if (breg != 0) |
67c0d1eb | 6828 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6829 | tempreg, tempreg, breg); |
67c0d1eb | 6830 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6831 | } |
0a44bf69 | 6832 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6833 | { |
f5040a92 AO |
6834 | /* If this is a reference to an external symbol, we want |
6835 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6836 | add $tempreg,$tempreg,$gp | |
6837 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6838 | <op> $treg,<ofst>($tempreg) | |
6839 | Otherwise, for local symbols, we want: | |
6840 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6841 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 6842 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 6843 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6844 | offset_expr.X_add_number = 0; |
6845 | if (expr1.X_add_number < -0x8000 | |
6846 | || expr1.X_add_number >= 0x8000) | |
6847 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6848 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6849 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6850 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6851 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6852 | mips_gp_register); | |
6853 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6854 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6855 | if (breg != 0) |
67c0d1eb | 6856 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6857 | tempreg, tempreg, breg); |
67c0d1eb | 6858 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6859 | |
4d7206a2 | 6860 | relax_switch (); |
f5040a92 | 6861 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6862 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6863 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6864 | if (breg != 0) |
67c0d1eb | 6865 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6866 | tempreg, tempreg, breg); |
67c0d1eb | 6867 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6868 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6869 | relax_end (); |
f5040a92 | 6870 | } |
252b5132 RH |
6871 | else |
6872 | abort (); | |
6873 | ||
252b5132 RH |
6874 | break; |
6875 | ||
6876 | case M_LI: | |
6877 | case M_LI_S: | |
67c0d1eb | 6878 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6879 | break; |
252b5132 RH |
6880 | |
6881 | case M_DLI: | |
67c0d1eb | 6882 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6883 | break; |
252b5132 RH |
6884 | |
6885 | case M_LI_SS: | |
6886 | if (imm_expr.X_op == O_constant) | |
6887 | { | |
8fc2e39e | 6888 | used_at = 1; |
67c0d1eb RS |
6889 | load_register (AT, &imm_expr, 0); |
6890 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6891 | break; |
6892 | } | |
6893 | else | |
6894 | { | |
9c2799c2 | 6895 | gas_assert (offset_expr.X_op == O_symbol |
252b5132 RH |
6896 | && strcmp (segment_name (S_GET_SEGMENT |
6897 | (offset_expr.X_add_symbol)), | |
6898 | ".lit4") == 0 | |
6899 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6900 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6901 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6902 | break; |
252b5132 RH |
6903 | } |
6904 | ||
6905 | case M_LI_D: | |
ca4e0257 RS |
6906 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6907 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6908 | order 32 bits of the value and the low order 32 bits are either | |
6909 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6910 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6911 | { | |
ca4e0257 | 6912 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6913 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6914 | else |
6915 | { | |
6916 | int hreg, lreg; | |
6917 | ||
6918 | if (target_big_endian) | |
6919 | { | |
6920 | hreg = treg; | |
6921 | lreg = treg + 1; | |
6922 | } | |
6923 | else | |
6924 | { | |
6925 | hreg = treg + 1; | |
6926 | lreg = treg; | |
6927 | } | |
6928 | ||
6929 | if (hreg <= 31) | |
67c0d1eb | 6930 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6931 | if (lreg <= 31) |
6932 | { | |
6933 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6934 | move_register (lreg, 0); |
252b5132 RH |
6935 | else |
6936 | { | |
9c2799c2 | 6937 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 6938 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6939 | } |
6940 | } | |
6941 | } | |
8fc2e39e | 6942 | break; |
252b5132 RH |
6943 | } |
6944 | ||
6945 | /* We know that sym is in the .rdata section. First we get the | |
6946 | upper 16 bits of the address. */ | |
6947 | if (mips_pic == NO_PIC) | |
6948 | { | |
67c0d1eb | 6949 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6950 | used_at = 1; |
252b5132 | 6951 | } |
0a44bf69 | 6952 | else |
252b5132 | 6953 | { |
67c0d1eb RS |
6954 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6955 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6956 | used_at = 1; |
252b5132 | 6957 | } |
bdaaa2e1 | 6958 | |
252b5132 | 6959 | /* Now we load the register(s). */ |
ca4e0257 | 6960 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6961 | { |
6962 | used_at = 1; | |
6963 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
6964 | } | |
252b5132 RH |
6965 | else |
6966 | { | |
8fc2e39e | 6967 | used_at = 1; |
67c0d1eb | 6968 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6969 | if (treg != RA) |
252b5132 RH |
6970 | { |
6971 | /* FIXME: How in the world do we deal with the possible | |
6972 | overflow here? */ | |
6973 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6974 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6975 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6976 | } |
6977 | } | |
252b5132 RH |
6978 | break; |
6979 | ||
6980 | case M_LI_DD: | |
ca4e0257 RS |
6981 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6982 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6983 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6984 | the value and the low order 32 bits are either zero or in | |
6985 | OFFSET_EXPR. */ | |
252b5132 RH |
6986 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6987 | { | |
8fc2e39e | 6988 | used_at = 1; |
67c0d1eb | 6989 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6990 | if (HAVE_64BIT_FPRS) |
6991 | { | |
9c2799c2 | 6992 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 6993 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6994 | } |
252b5132 RH |
6995 | else |
6996 | { | |
67c0d1eb | 6997 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6998 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6999 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
7000 | else |
7001 | { | |
9c2799c2 | 7002 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
7003 | load_register (AT, &offset_expr, 0); |
7004 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
7005 | } |
7006 | } | |
7007 | break; | |
7008 | } | |
7009 | ||
9c2799c2 | 7010 | gas_assert (offset_expr.X_op == O_symbol |
252b5132 RH |
7011 | && offset_expr.X_add_number == 0); |
7012 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
7013 | if (strcmp (s, ".lit8") == 0) | |
7014 | { | |
e7af610e | 7015 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 7016 | { |
67c0d1eb | 7017 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 7018 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 7019 | break; |
252b5132 | 7020 | } |
c9914766 | 7021 | breg = mips_gp_register; |
252b5132 RH |
7022 | r = BFD_RELOC_MIPS_LITERAL; |
7023 | goto dob; | |
7024 | } | |
7025 | else | |
7026 | { | |
9c2799c2 | 7027 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 7028 | used_at = 1; |
0a44bf69 | 7029 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
7030 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
7031 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
7032 | else |
7033 | { | |
7034 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 7035 | macro_build_lui (&offset_expr, AT); |
252b5132 | 7036 | } |
bdaaa2e1 | 7037 | |
e7af610e | 7038 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 7039 | { |
67c0d1eb RS |
7040 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
7041 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
7042 | break; |
7043 | } | |
7044 | breg = AT; | |
7045 | r = BFD_RELOC_LO16; | |
7046 | goto dob; | |
7047 | } | |
7048 | ||
7049 | case M_L_DOB: | |
252b5132 RH |
7050 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7051 | to adjust when loading from memory. */ | |
7052 | r = BFD_RELOC_LO16; | |
7053 | dob: | |
9c2799c2 | 7054 | gas_assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 7055 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 7056 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
7057 | /* FIXME: A possible overflow which I don't know how to deal |
7058 | with. */ | |
7059 | offset_expr.X_add_number += 4; | |
67c0d1eb | 7060 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 7061 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
7062 | break; |
7063 | ||
7064 | case M_L_DAB: | |
7065 | /* | |
7066 | * The MIPS assembler seems to check for X_add_number not | |
7067 | * being double aligned and generating: | |
7068 | * lui at,%hi(foo+1) | |
7069 | * addu at,at,v1 | |
7070 | * addiu at,at,%lo(foo+1) | |
7071 | * lwc1 f2,0(at) | |
7072 | * lwc1 f3,4(at) | |
7073 | * But, the resulting address is the same after relocation so why | |
7074 | * generate the extra instruction? | |
7075 | */ | |
bdaaa2e1 | 7076 | /* Itbl support may require additional care here. */ |
252b5132 | 7077 | coproc = 1; |
e7af610e | 7078 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
7079 | { |
7080 | s = "ldc1"; | |
7081 | goto ld; | |
7082 | } | |
7083 | ||
7084 | s = "lwc1"; | |
7085 | fmt = "T,o(b)"; | |
7086 | goto ldd_std; | |
7087 | ||
7088 | case M_S_DAB: | |
e7af610e | 7089 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
7090 | { |
7091 | s = "sdc1"; | |
7092 | goto st; | |
7093 | } | |
7094 | ||
7095 | s = "swc1"; | |
7096 | fmt = "T,o(b)"; | |
bdaaa2e1 | 7097 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7098 | coproc = 1; |
7099 | goto ldd_std; | |
7100 | ||
7101 | case M_LD_AB: | |
ca4e0257 | 7102 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
7103 | { |
7104 | s = "ld"; | |
7105 | goto ld; | |
7106 | } | |
7107 | ||
7108 | s = "lw"; | |
7109 | fmt = "t,o(b)"; | |
7110 | goto ldd_std; | |
7111 | ||
7112 | case M_SD_AB: | |
ca4e0257 | 7113 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
7114 | { |
7115 | s = "sd"; | |
7116 | goto st; | |
7117 | } | |
7118 | ||
7119 | s = "sw"; | |
7120 | fmt = "t,o(b)"; | |
7121 | ||
7122 | ldd_std: | |
7123 | if (offset_expr.X_op != O_symbol | |
7124 | && offset_expr.X_op != O_constant) | |
7125 | { | |
7126 | as_bad (_("expression too complex")); | |
7127 | offset_expr.X_op = O_constant; | |
7128 | } | |
7129 | ||
2051e8c4 MR |
7130 | if (HAVE_32BIT_ADDRESSES |
7131 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
7132 | { |
7133 | char value [32]; | |
7134 | ||
7135 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 7136 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 7137 | } |
2051e8c4 | 7138 | |
252b5132 RH |
7139 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7140 | to adjust when loading from memory. We set coproc if we must | |
7141 | load $fn+1 first. */ | |
bdaaa2e1 | 7142 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7143 | if (! target_big_endian) |
7144 | coproc = 0; | |
7145 | ||
7146 | if (mips_pic == NO_PIC | |
7147 | || offset_expr.X_op == O_constant) | |
7148 | { | |
7149 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
7150 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
7151 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
7152 | If we have a base register, we use this |
7153 | addu $at,$breg,$gp | |
cdf6fd85 TS |
7154 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
7155 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
7156 | If this is not a GP relative symbol, we want |
7157 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7158 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7159 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7160 | If there is a base register, we add it to $at after the | |
7161 | lui instruction. If there is a constant, we always use | |
7162 | the last case. */ | |
39a59cf8 MR |
7163 | if (offset_expr.X_op == O_symbol |
7164 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7165 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 7166 | { |
4d7206a2 | 7167 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
7168 | if (breg == 0) |
7169 | { | |
c9914766 | 7170 | tempreg = mips_gp_register; |
252b5132 RH |
7171 | } |
7172 | else | |
7173 | { | |
67c0d1eb | 7174 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7175 | AT, breg, mips_gp_register); |
252b5132 | 7176 | tempreg = AT; |
252b5132 RH |
7177 | used_at = 1; |
7178 | } | |
7179 | ||
beae10d5 | 7180 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7181 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7182 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
7183 | offset_expr.X_add_number += 4; |
7184 | ||
7185 | /* Set mips_optimize to 2 to avoid inserting an | |
7186 | undesired nop. */ | |
7187 | hold_mips_optimize = mips_optimize; | |
7188 | mips_optimize = 2; | |
beae10d5 | 7189 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7190 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7191 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
7192 | mips_optimize = hold_mips_optimize; |
7193 | ||
4d7206a2 | 7194 | relax_switch (); |
252b5132 RH |
7195 | |
7196 | /* We just generated two relocs. When tc_gen_reloc | |
7197 | handles this case, it will skip the first reloc and | |
7198 | handle the second. The second reloc already has an | |
7199 | extra addend of 4, which we added above. We must | |
7200 | subtract it out, and then subtract another 4 to make | |
7201 | the first reloc come out right. The second reloc | |
7202 | will come out right because we are going to add 4 to | |
7203 | offset_expr when we build its instruction below. | |
7204 | ||
7205 | If we have a symbol, then we don't want to include | |
7206 | the offset, because it will wind up being included | |
7207 | when we generate the reloc. */ | |
7208 | ||
7209 | if (offset_expr.X_op == O_constant) | |
7210 | offset_expr.X_add_number -= 8; | |
7211 | else | |
7212 | { | |
7213 | offset_expr.X_add_number = -4; | |
7214 | offset_expr.X_op = O_constant; | |
7215 | } | |
7216 | } | |
8fc2e39e | 7217 | used_at = 1; |
67c0d1eb | 7218 | macro_build_lui (&offset_expr, AT); |
252b5132 | 7219 | if (breg != 0) |
67c0d1eb | 7220 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7221 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7222 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7223 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7224 | /* FIXME: How do we handle overflow here? */ |
7225 | offset_expr.X_add_number += 4; | |
beae10d5 | 7226 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7227 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7228 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
7229 | if (mips_relax.sequence) |
7230 | relax_end (); | |
bdaaa2e1 | 7231 | } |
0a44bf69 | 7232 | else if (!mips_big_got) |
252b5132 | 7233 | { |
252b5132 RH |
7234 | /* If this is a reference to an external symbol, we want |
7235 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7236 | nop | |
7237 | <op> $treg,0($at) | |
7238 | <op> $treg+1,4($at) | |
7239 | Otherwise we want | |
7240 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7241 | nop | |
7242 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7243 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7244 | If there is a base register we add it to $at before the | |
7245 | lwc1 instructions. If there is a constant we include it | |
7246 | in the lwc1 instructions. */ | |
7247 | used_at = 1; | |
7248 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
7249 | if (expr1.X_add_number < -0x8000 |
7250 | || expr1.X_add_number >= 0x8000 - 4) | |
7251 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7252 | load_got_offset (AT, &offset_expr); |
269137b2 | 7253 | load_delay_nop (); |
252b5132 | 7254 | if (breg != 0) |
67c0d1eb | 7255 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
7256 | |
7257 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7258 | nop. */ | |
7259 | hold_mips_optimize = mips_optimize; | |
7260 | mips_optimize = 2; | |
4d7206a2 | 7261 | |
beae10d5 | 7262 | /* Itbl support may require additional care here. */ |
4d7206a2 | 7263 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7264 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
7265 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7266 | expr1.X_add_number += 4; |
67c0d1eb RS |
7267 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
7268 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7269 | relax_switch (); |
67c0d1eb RS |
7270 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7271 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7272 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7273 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7274 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7275 | relax_end (); |
252b5132 | 7276 | |
4d7206a2 | 7277 | mips_optimize = hold_mips_optimize; |
252b5132 | 7278 | } |
0a44bf69 | 7279 | else if (mips_big_got) |
252b5132 | 7280 | { |
67c0d1eb | 7281 | int gpdelay; |
252b5132 RH |
7282 | |
7283 | /* If this is a reference to an external symbol, we want | |
7284 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7285 | addu $at,$at,$gp | |
7286 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
7287 | nop | |
7288 | <op> $treg,0($at) | |
7289 | <op> $treg+1,4($at) | |
7290 | Otherwise we want | |
7291 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7292 | nop | |
7293 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7294 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7295 | If there is a base register we add it to $at before the | |
7296 | lwc1 instructions. If there is a constant we include it | |
7297 | in the lwc1 instructions. */ | |
7298 | used_at = 1; | |
7299 | expr1.X_add_number = offset_expr.X_add_number; | |
7300 | offset_expr.X_add_number = 0; | |
7301 | if (expr1.X_add_number < -0x8000 | |
7302 | || expr1.X_add_number >= 0x8000 - 4) | |
7303 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7304 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 7305 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7306 | macro_build (&offset_expr, "lui", "t,u", |
7307 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
7308 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 7309 | AT, AT, mips_gp_register); |
67c0d1eb | 7310 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7311 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 7312 | load_delay_nop (); |
252b5132 | 7313 | if (breg != 0) |
67c0d1eb | 7314 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7315 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7316 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7317 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7318 | expr1.X_add_number += 4; |
7319 | ||
7320 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7321 | nop. */ | |
7322 | hold_mips_optimize = mips_optimize; | |
7323 | mips_optimize = 2; | |
beae10d5 | 7324 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7325 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7326 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7327 | mips_optimize = hold_mips_optimize; |
7328 | expr1.X_add_number -= 4; | |
7329 | ||
4d7206a2 RS |
7330 | relax_switch (); |
7331 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
7332 | if (gpdelay) |
7333 | macro_build (NULL, "nop", ""); | |
7334 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
7335 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7336 | load_delay_nop (); |
252b5132 | 7337 | if (breg != 0) |
67c0d1eb | 7338 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7339 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7340 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7341 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7342 | offset_expr.X_add_number += 4; |
252b5132 RH |
7343 | |
7344 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7345 | nop. */ | |
7346 | hold_mips_optimize = mips_optimize; | |
7347 | mips_optimize = 2; | |
beae10d5 | 7348 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7349 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7350 | BFD_RELOC_LO16, AT); | |
252b5132 | 7351 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 7352 | relax_end (); |
252b5132 | 7353 | } |
252b5132 RH |
7354 | else |
7355 | abort (); | |
7356 | ||
252b5132 RH |
7357 | break; |
7358 | ||
7359 | case M_LD_OB: | |
7360 | s = "lw"; | |
7361 | goto sd_ob; | |
7362 | case M_SD_OB: | |
7363 | s = "sw"; | |
7364 | sd_ob: | |
9c2799c2 | 7365 | gas_assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 7366 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 7367 | offset_expr.X_add_number += 4; |
67c0d1eb | 7368 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
8fc2e39e | 7369 | break; |
252b5132 RH |
7370 | |
7371 | /* New code added to support COPZ instructions. | |
7372 | This code builds table entries out of the macros in mip_opcodes. | |
7373 | R4000 uses interlocks to handle coproc delays. | |
7374 | Other chips (like the R3000) require nops to be inserted for delays. | |
7375 | ||
f72c8c98 | 7376 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
7377 | In order to fill delay slots for non-interlocked chips, |
7378 | we must have a way to specify delays based on the coprocessor. | |
7379 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
7380 | What are the side-effects of the cop instruction? | |
7381 | What cache support might we have and what are its effects? | |
7382 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 7383 | What registers are read/set/modified? |
252b5132 RH |
7384 | |
7385 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 7386 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
7387 | |
7388 | case M_COP0: | |
7389 | s = "c0"; | |
7390 | goto copz; | |
7391 | case M_COP1: | |
7392 | s = "c1"; | |
7393 | goto copz; | |
7394 | case M_COP2: | |
7395 | s = "c2"; | |
7396 | goto copz; | |
7397 | case M_COP3: | |
7398 | s = "c3"; | |
7399 | copz: | |
b19e8a9b AN |
7400 | if (NO_ISA_COP (mips_opts.arch) |
7401 | && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0) | |
7402 | { | |
7403 | as_bad (_("opcode not supported on this processor: %s"), | |
7404 | mips_cpu_info_from_arch (mips_opts.arch)->name); | |
7405 | break; | |
7406 | } | |
7407 | ||
252b5132 RH |
7408 | /* For now we just do C (same as Cz). The parameter will be |
7409 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 7410 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 7411 | break; |
252b5132 | 7412 | |
ea1fb5dc | 7413 | case M_MOVE: |
67c0d1eb | 7414 | move_register (dreg, sreg); |
8fc2e39e | 7415 | break; |
ea1fb5dc | 7416 | |
252b5132 RH |
7417 | #ifdef LOSING_COMPILER |
7418 | default: | |
7419 | /* Try and see if this is a new itbl instruction. | |
7420 | This code builds table entries out of the macros in mip_opcodes. | |
7421 | FIXME: For now we just assemble the expression and pass it's | |
7422 | value along as a 32-bit immediate. | |
bdaaa2e1 | 7423 | We may want to have the assembler assemble this value, |
252b5132 RH |
7424 | so that we gain the assembler's knowledge of delay slots, |
7425 | symbols, etc. | |
7426 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 7427 | if (itbl_have_entries |
252b5132 | 7428 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 7429 | { |
252b5132 RH |
7430 | s = ip->insn_mo->name; |
7431 | s2 = "cop3"; | |
7432 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 7433 | macro_build (&immed_expr, s, "C"); |
8fc2e39e | 7434 | break; |
beae10d5 | 7435 | } |
252b5132 | 7436 | macro2 (ip); |
8fc2e39e | 7437 | break; |
252b5132 | 7438 | } |
741fe287 | 7439 | if (!mips_opts.at && used_at) |
8fc2e39e | 7440 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 | 7441 | } |
bdaaa2e1 | 7442 | |
252b5132 | 7443 | static void |
17a2f251 | 7444 | macro2 (struct mips_cl_insn *ip) |
252b5132 | 7445 | { |
741fe287 MR |
7446 | unsigned int treg, sreg, dreg, breg; |
7447 | unsigned int tempreg; | |
252b5132 | 7448 | int mask; |
252b5132 RH |
7449 | int used_at; |
7450 | expressionS expr1; | |
7451 | const char *s; | |
7452 | const char *s2; | |
7453 | const char *fmt; | |
7454 | int likely = 0; | |
7455 | int dbl = 0; | |
7456 | int coproc = 0; | |
7457 | int lr = 0; | |
7458 | int imm = 0; | |
7459 | int off; | |
7460 | offsetT maxnum; | |
7461 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 7462 | |
252b5132 RH |
7463 | treg = (ip->insn_opcode >> 16) & 0x1f; |
7464 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
7465 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
7466 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 7467 | |
252b5132 RH |
7468 | expr1.X_op = O_constant; |
7469 | expr1.X_op_symbol = NULL; | |
7470 | expr1.X_add_symbol = NULL; | |
7471 | expr1.X_add_number = 1; | |
bdaaa2e1 | 7472 | |
252b5132 RH |
7473 | switch (mask) |
7474 | { | |
7475 | #endif /* LOSING_COMPILER */ | |
7476 | ||
7477 | case M_DMUL: | |
7478 | dbl = 1; | |
7479 | case M_MUL: | |
67c0d1eb RS |
7480 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
7481 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 7482 | break; |
252b5132 RH |
7483 | |
7484 | case M_DMUL_I: | |
7485 | dbl = 1; | |
7486 | case M_MUL_I: | |
7487 | /* The MIPS assembler some times generates shifts and adds. I'm | |
7488 | not trying to be that fancy. GCC should do this for us | |
7489 | anyway. */ | |
8fc2e39e | 7490 | used_at = 1; |
67c0d1eb RS |
7491 | load_register (AT, &imm_expr, dbl); |
7492 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
7493 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
7494 | break; |
7495 | ||
7496 | case M_DMULO_I: | |
7497 | dbl = 1; | |
7498 | case M_MULO_I: | |
7499 | imm = 1; | |
7500 | goto do_mulo; | |
7501 | ||
7502 | case M_DMULO: | |
7503 | dbl = 1; | |
7504 | case M_MULO: | |
7505 | do_mulo: | |
7d10b47d | 7506 | start_noreorder (); |
8fc2e39e | 7507 | used_at = 1; |
252b5132 | 7508 | if (imm) |
67c0d1eb RS |
7509 | load_register (AT, &imm_expr, dbl); |
7510 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
7511 | macro_build (NULL, "mflo", "d", dreg); | |
7512 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
7513 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 7514 | if (mips_trap) |
67c0d1eb | 7515 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
7516 | else |
7517 | { | |
7518 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7519 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
7520 | macro_build (NULL, "nop", "", 0); | |
7521 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 7522 | } |
7d10b47d | 7523 | end_noreorder (); |
67c0d1eb | 7524 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
7525 | break; |
7526 | ||
7527 | case M_DMULOU_I: | |
7528 | dbl = 1; | |
7529 | case M_MULOU_I: | |
7530 | imm = 1; | |
7531 | goto do_mulou; | |
7532 | ||
7533 | case M_DMULOU: | |
7534 | dbl = 1; | |
7535 | case M_MULOU: | |
7536 | do_mulou: | |
7d10b47d | 7537 | start_noreorder (); |
8fc2e39e | 7538 | used_at = 1; |
252b5132 | 7539 | if (imm) |
67c0d1eb RS |
7540 | load_register (AT, &imm_expr, dbl); |
7541 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 7542 | sreg, imm ? AT : treg); |
67c0d1eb RS |
7543 | macro_build (NULL, "mfhi", "d", AT); |
7544 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 7545 | if (mips_trap) |
67c0d1eb | 7546 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
7547 | else |
7548 | { | |
7549 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7550 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
7551 | macro_build (NULL, "nop", "", 0); | |
7552 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 7553 | } |
7d10b47d | 7554 | end_noreorder (); |
252b5132 RH |
7555 | break; |
7556 | ||
771c7ce4 | 7557 | case M_DROL: |
fef14a42 | 7558 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7559 | { |
7560 | if (dreg == sreg) | |
7561 | { | |
7562 | tempreg = AT; | |
7563 | used_at = 1; | |
7564 | } | |
7565 | else | |
7566 | { | |
7567 | tempreg = dreg; | |
82dd0097 | 7568 | } |
67c0d1eb RS |
7569 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
7570 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7571 | break; |
82dd0097 | 7572 | } |
8fc2e39e | 7573 | used_at = 1; |
67c0d1eb RS |
7574 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7575 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
7576 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
7577 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7578 | break; |
7579 | ||
252b5132 | 7580 | case M_ROL: |
fef14a42 | 7581 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
7582 | { |
7583 | if (dreg == sreg) | |
7584 | { | |
7585 | tempreg = AT; | |
7586 | used_at = 1; | |
7587 | } | |
7588 | else | |
7589 | { | |
7590 | tempreg = dreg; | |
82dd0097 | 7591 | } |
67c0d1eb RS |
7592 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
7593 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7594 | break; |
82dd0097 | 7595 | } |
8fc2e39e | 7596 | used_at = 1; |
67c0d1eb RS |
7597 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7598 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
7599 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
7600 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7601 | break; |
7602 | ||
771c7ce4 TS |
7603 | case M_DROL_I: |
7604 | { | |
7605 | unsigned int rot; | |
91d6fa6a NC |
7606 | char *l; |
7607 | char *rr; | |
771c7ce4 TS |
7608 | |
7609 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7610 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7611 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7612 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
7613 | { |
7614 | rot = (64 - rot) & 0x3f; | |
7615 | if (rot >= 32) | |
67c0d1eb | 7616 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 7617 | else |
67c0d1eb | 7618 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7619 | break; |
60b63b72 | 7620 | } |
483fc7cd | 7621 | if (rot == 0) |
483fc7cd | 7622 | { |
67c0d1eb | 7623 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7624 | break; |
483fc7cd | 7625 | } |
82dd0097 | 7626 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 7627 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 7628 | rot &= 0x1f; |
8fc2e39e | 7629 | used_at = 1; |
67c0d1eb | 7630 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
91d6fa6a | 7631 | macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); |
67c0d1eb | 7632 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
7633 | } |
7634 | break; | |
7635 | ||
252b5132 | 7636 | case M_ROL_I: |
771c7ce4 TS |
7637 | { |
7638 | unsigned int rot; | |
7639 | ||
7640 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7641 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7642 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7643 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 7644 | { |
67c0d1eb | 7645 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 7646 | break; |
60b63b72 | 7647 | } |
483fc7cd | 7648 | if (rot == 0) |
483fc7cd | 7649 | { |
67c0d1eb | 7650 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7651 | break; |
483fc7cd | 7652 | } |
8fc2e39e | 7653 | used_at = 1; |
67c0d1eb RS |
7654 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
7655 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7656 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7657 | } |
7658 | break; | |
7659 | ||
7660 | case M_DROR: | |
fef14a42 | 7661 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7662 | { |
67c0d1eb | 7663 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7664 | break; |
82dd0097 | 7665 | } |
8fc2e39e | 7666 | used_at = 1; |
67c0d1eb RS |
7667 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7668 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
7669 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7670 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7671 | break; |
7672 | ||
7673 | case M_ROR: | |
fef14a42 | 7674 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7675 | { |
67c0d1eb | 7676 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7677 | break; |
82dd0097 | 7678 | } |
8fc2e39e | 7679 | used_at = 1; |
67c0d1eb RS |
7680 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7681 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
7682 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7683 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7684 | break; |
7685 | ||
771c7ce4 TS |
7686 | case M_DROR_I: |
7687 | { | |
7688 | unsigned int rot; | |
91d6fa6a NC |
7689 | char *l; |
7690 | char *rr; | |
771c7ce4 TS |
7691 | |
7692 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7693 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7694 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7695 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7696 | { |
7697 | if (rot >= 32) | |
67c0d1eb | 7698 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7699 | else |
67c0d1eb | 7700 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7701 | break; |
82dd0097 | 7702 | } |
483fc7cd | 7703 | if (rot == 0) |
483fc7cd | 7704 | { |
67c0d1eb | 7705 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7706 | break; |
483fc7cd | 7707 | } |
91d6fa6a | 7708 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
7709 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
7710 | rot &= 0x1f; | |
8fc2e39e | 7711 | used_at = 1; |
91d6fa6a | 7712 | macro_build (NULL, rr, "d,w,<", AT, sreg, rot); |
67c0d1eb RS |
7713 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); |
7714 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7715 | } |
7716 | break; | |
7717 | ||
252b5132 | 7718 | case M_ROR_I: |
771c7ce4 TS |
7719 | { |
7720 | unsigned int rot; | |
7721 | ||
7722 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7723 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7724 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7725 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7726 | { |
67c0d1eb | 7727 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7728 | break; |
82dd0097 | 7729 | } |
483fc7cd | 7730 | if (rot == 0) |
483fc7cd | 7731 | { |
67c0d1eb | 7732 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7733 | break; |
483fc7cd | 7734 | } |
8fc2e39e | 7735 | used_at = 1; |
67c0d1eb RS |
7736 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7737 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7738 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7739 | } |
252b5132 RH |
7740 | break; |
7741 | ||
7742 | case M_S_DOB: | |
9c2799c2 | 7743 | gas_assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7744 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7745 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7746 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7747 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7748 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7749 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7750 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8fc2e39e | 7751 | break; |
252b5132 RH |
7752 | |
7753 | case M_SEQ: | |
7754 | if (sreg == 0) | |
67c0d1eb | 7755 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7756 | else if (treg == 0) |
67c0d1eb | 7757 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7758 | else |
7759 | { | |
67c0d1eb RS |
7760 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7761 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7762 | } |
8fc2e39e | 7763 | break; |
252b5132 RH |
7764 | |
7765 | case M_SEQ_I: | |
7766 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7767 | { | |
67c0d1eb | 7768 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7769 | break; |
252b5132 RH |
7770 | } |
7771 | if (sreg == 0) | |
7772 | { | |
7773 | as_warn (_("Instruction %s: result is always false"), | |
7774 | ip->insn_mo->name); | |
67c0d1eb | 7775 | move_register (dreg, 0); |
8fc2e39e | 7776 | break; |
252b5132 | 7777 | } |
dd3cbb7e NC |
7778 | if (CPU_HAS_SEQ (mips_opts.arch) |
7779 | && -512 <= imm_expr.X_add_number | |
7780 | && imm_expr.X_add_number < 512) | |
7781 | { | |
7782 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 7783 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
7784 | break; |
7785 | } | |
252b5132 RH |
7786 | if (imm_expr.X_op == O_constant |
7787 | && imm_expr.X_add_number >= 0 | |
7788 | && imm_expr.X_add_number < 0x10000) | |
7789 | { | |
67c0d1eb | 7790 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7791 | } |
7792 | else if (imm_expr.X_op == O_constant | |
7793 | && imm_expr.X_add_number > -0x8000 | |
7794 | && imm_expr.X_add_number < 0) | |
7795 | { | |
7796 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7797 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7798 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 7799 | } |
dd3cbb7e NC |
7800 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
7801 | { | |
7802 | used_at = 1; | |
7803 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
7804 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
7805 | break; | |
7806 | } | |
252b5132 RH |
7807 | else |
7808 | { | |
67c0d1eb RS |
7809 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7810 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7811 | used_at = 1; |
7812 | } | |
67c0d1eb | 7813 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7814 | break; |
252b5132 RH |
7815 | |
7816 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7817 | s = "slt"; | |
7818 | goto sge; | |
7819 | case M_SGEU: | |
7820 | s = "sltu"; | |
7821 | sge: | |
67c0d1eb RS |
7822 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7823 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7824 | break; |
252b5132 RH |
7825 | |
7826 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7827 | case M_SGEU_I: | |
7828 | if (imm_expr.X_op == O_constant | |
7829 | && imm_expr.X_add_number >= -0x8000 | |
7830 | && imm_expr.X_add_number < 0x8000) | |
7831 | { | |
67c0d1eb RS |
7832 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7833 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7834 | } |
7835 | else | |
7836 | { | |
67c0d1eb RS |
7837 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7838 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7839 | dreg, sreg, AT); | |
252b5132 RH |
7840 | used_at = 1; |
7841 | } | |
67c0d1eb | 7842 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7843 | break; |
252b5132 RH |
7844 | |
7845 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7846 | s = "slt"; | |
7847 | goto sgt; | |
7848 | case M_SGTU: | |
7849 | s = "sltu"; | |
7850 | sgt: | |
67c0d1eb | 7851 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7852 | break; |
252b5132 RH |
7853 | |
7854 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7855 | s = "slt"; | |
7856 | goto sgti; | |
7857 | case M_SGTU_I: | |
7858 | s = "sltu"; | |
7859 | sgti: | |
8fc2e39e | 7860 | used_at = 1; |
67c0d1eb RS |
7861 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7862 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7863 | break; |
7864 | ||
2396cfb9 | 7865 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7866 | s = "slt"; |
7867 | goto sle; | |
7868 | case M_SLEU: | |
7869 | s = "sltu"; | |
7870 | sle: | |
67c0d1eb RS |
7871 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7872 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7873 | break; |
252b5132 | 7874 | |
2396cfb9 | 7875 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7876 | s = "slt"; |
7877 | goto slei; | |
7878 | case M_SLEU_I: | |
7879 | s = "sltu"; | |
7880 | slei: | |
8fc2e39e | 7881 | used_at = 1; |
67c0d1eb RS |
7882 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7883 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7884 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7885 | break; |
7886 | ||
7887 | case M_SLT_I: | |
7888 | if (imm_expr.X_op == O_constant | |
7889 | && imm_expr.X_add_number >= -0x8000 | |
7890 | && imm_expr.X_add_number < 0x8000) | |
7891 | { | |
67c0d1eb | 7892 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7893 | break; |
252b5132 | 7894 | } |
8fc2e39e | 7895 | used_at = 1; |
67c0d1eb RS |
7896 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7897 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7898 | break; |
7899 | ||
7900 | case M_SLTU_I: | |
7901 | if (imm_expr.X_op == O_constant | |
7902 | && imm_expr.X_add_number >= -0x8000 | |
7903 | && imm_expr.X_add_number < 0x8000) | |
7904 | { | |
67c0d1eb | 7905 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7906 | BFD_RELOC_LO16); |
8fc2e39e | 7907 | break; |
252b5132 | 7908 | } |
8fc2e39e | 7909 | used_at = 1; |
67c0d1eb RS |
7910 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7911 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7912 | break; |
7913 | ||
7914 | case M_SNE: | |
7915 | if (sreg == 0) | |
67c0d1eb | 7916 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7917 | else if (treg == 0) |
67c0d1eb | 7918 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7919 | else |
7920 | { | |
67c0d1eb RS |
7921 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7922 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7923 | } |
8fc2e39e | 7924 | break; |
252b5132 RH |
7925 | |
7926 | case M_SNE_I: | |
7927 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7928 | { | |
67c0d1eb | 7929 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7930 | break; |
252b5132 RH |
7931 | } |
7932 | if (sreg == 0) | |
7933 | { | |
7934 | as_warn (_("Instruction %s: result is always true"), | |
7935 | ip->insn_mo->name); | |
67c0d1eb RS |
7936 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7937 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7938 | break; |
252b5132 | 7939 | } |
dd3cbb7e NC |
7940 | if (CPU_HAS_SEQ (mips_opts.arch) |
7941 | && -512 <= imm_expr.X_add_number | |
7942 | && imm_expr.X_add_number < 512) | |
7943 | { | |
7944 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 7945 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
7946 | break; |
7947 | } | |
252b5132 RH |
7948 | if (imm_expr.X_op == O_constant |
7949 | && imm_expr.X_add_number >= 0 | |
7950 | && imm_expr.X_add_number < 0x10000) | |
7951 | { | |
67c0d1eb | 7952 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7953 | } |
7954 | else if (imm_expr.X_op == O_constant | |
7955 | && imm_expr.X_add_number > -0x8000 | |
7956 | && imm_expr.X_add_number < 0) | |
7957 | { | |
7958 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7959 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7960 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 7961 | } |
dd3cbb7e NC |
7962 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
7963 | { | |
7964 | used_at = 1; | |
7965 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
7966 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
7967 | break; | |
7968 | } | |
252b5132 RH |
7969 | else |
7970 | { | |
67c0d1eb RS |
7971 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7972 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7973 | used_at = 1; |
7974 | } | |
67c0d1eb | 7975 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7976 | break; |
252b5132 RH |
7977 | |
7978 | case M_DSUB_I: | |
7979 | dbl = 1; | |
7980 | case M_SUB_I: | |
7981 | if (imm_expr.X_op == O_constant | |
7982 | && imm_expr.X_add_number > -0x8000 | |
7983 | && imm_expr.X_add_number <= 0x8000) | |
7984 | { | |
7985 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7986 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7987 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7988 | break; |
252b5132 | 7989 | } |
8fc2e39e | 7990 | used_at = 1; |
67c0d1eb RS |
7991 | load_register (AT, &imm_expr, dbl); |
7992 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7993 | break; |
7994 | ||
7995 | case M_DSUBU_I: | |
7996 | dbl = 1; | |
7997 | case M_SUBU_I: | |
7998 | if (imm_expr.X_op == O_constant | |
7999 | && imm_expr.X_add_number > -0x8000 | |
8000 | && imm_expr.X_add_number <= 0x8000) | |
8001 | { | |
8002 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
8003 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
8004 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 8005 | break; |
252b5132 | 8006 | } |
8fc2e39e | 8007 | used_at = 1; |
67c0d1eb RS |
8008 | load_register (AT, &imm_expr, dbl); |
8009 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
8010 | break; |
8011 | ||
8012 | case M_TEQ_I: | |
8013 | s = "teq"; | |
8014 | goto trap; | |
8015 | case M_TGE_I: | |
8016 | s = "tge"; | |
8017 | goto trap; | |
8018 | case M_TGEU_I: | |
8019 | s = "tgeu"; | |
8020 | goto trap; | |
8021 | case M_TLT_I: | |
8022 | s = "tlt"; | |
8023 | goto trap; | |
8024 | case M_TLTU_I: | |
8025 | s = "tltu"; | |
8026 | goto trap; | |
8027 | case M_TNE_I: | |
8028 | s = "tne"; | |
8029 | trap: | |
8fc2e39e | 8030 | used_at = 1; |
67c0d1eb RS |
8031 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
8032 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
8033 | break; |
8034 | ||
252b5132 | 8035 | case M_TRUNCWS: |
43841e91 | 8036 | case M_TRUNCWD: |
9c2799c2 | 8037 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 8038 | used_at = 1; |
252b5132 RH |
8039 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
8040 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
8041 | ||
8042 | /* | |
8043 | * Is the double cfc1 instruction a bug in the mips assembler; | |
8044 | * or is there a reason for it? | |
8045 | */ | |
7d10b47d | 8046 | start_noreorder (); |
67c0d1eb RS |
8047 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
8048 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
8049 | macro_build (NULL, "nop", ""); | |
252b5132 | 8050 | expr1.X_add_number = 3; |
67c0d1eb | 8051 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 8052 | expr1.X_add_number = 2; |
67c0d1eb RS |
8053 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
8054 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
8055 | macro_build (NULL, "nop", ""); | |
8056 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
8057 | dreg, sreg); | |
8058 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
8059 | macro_build (NULL, "nop", ""); | |
7d10b47d | 8060 | end_noreorder (); |
252b5132 RH |
8061 | break; |
8062 | ||
8063 | case M_ULH: | |
8064 | s = "lb"; | |
8065 | goto ulh; | |
8066 | case M_ULHU: | |
8067 | s = "lbu"; | |
8068 | ulh: | |
8fc2e39e | 8069 | used_at = 1; |
252b5132 RH |
8070 | if (offset_expr.X_add_number >= 0x7fff) |
8071 | as_bad (_("operand overflow")); | |
252b5132 | 8072 | if (! target_big_endian) |
f9419b05 | 8073 | ++offset_expr.X_add_number; |
67c0d1eb | 8074 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 8075 | if (! target_big_endian) |
f9419b05 | 8076 | --offset_expr.X_add_number; |
252b5132 | 8077 | else |
f9419b05 | 8078 | ++offset_expr.X_add_number; |
67c0d1eb RS |
8079 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8080 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
8081 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8082 | break; |
8083 | ||
8084 | case M_ULD: | |
8085 | s = "ldl"; | |
8086 | s2 = "ldr"; | |
8087 | off = 7; | |
8088 | goto ulw; | |
8089 | case M_ULW: | |
8090 | s = "lwl"; | |
8091 | s2 = "lwr"; | |
8092 | off = 3; | |
8093 | ulw: | |
8094 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8095 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
8096 | if (treg != breg) |
8097 | tempreg = treg; | |
8098 | else | |
8fc2e39e TS |
8099 | { |
8100 | used_at = 1; | |
8101 | tempreg = AT; | |
8102 | } | |
252b5132 RH |
8103 | if (! target_big_endian) |
8104 | offset_expr.X_add_number += off; | |
67c0d1eb | 8105 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
8106 | if (! target_big_endian) |
8107 | offset_expr.X_add_number -= off; | |
8108 | else | |
8109 | offset_expr.X_add_number += off; | |
67c0d1eb | 8110 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
8111 | |
8112 | /* If necessary, move the result in tempreg the final destination. */ | |
8113 | if (treg == tempreg) | |
8fc2e39e | 8114 | break; |
af22f5b2 | 8115 | /* Protect second load's delay slot. */ |
017315e4 | 8116 | load_delay_nop (); |
67c0d1eb | 8117 | move_register (treg, tempreg); |
af22f5b2 | 8118 | break; |
252b5132 RH |
8119 | |
8120 | case M_ULD_A: | |
8121 | s = "ldl"; | |
8122 | s2 = "ldr"; | |
8123 | off = 7; | |
8124 | goto ulwa; | |
8125 | case M_ULW_A: | |
8126 | s = "lwl"; | |
8127 | s2 = "lwr"; | |
8128 | off = 3; | |
8129 | ulwa: | |
d6bc6245 | 8130 | used_at = 1; |
67c0d1eb | 8131 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8132 | if (breg != 0) |
67c0d1eb | 8133 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8134 | if (! target_big_endian) |
8135 | expr1.X_add_number = off; | |
8136 | else | |
8137 | expr1.X_add_number = 0; | |
67c0d1eb | 8138 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8139 | if (! target_big_endian) |
8140 | expr1.X_add_number = 0; | |
8141 | else | |
8142 | expr1.X_add_number = off; | |
67c0d1eb | 8143 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8144 | break; |
8145 | ||
8146 | case M_ULH_A: | |
8147 | case M_ULHU_A: | |
d6bc6245 | 8148 | used_at = 1; |
67c0d1eb | 8149 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8150 | if (breg != 0) |
67c0d1eb | 8151 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8152 | if (target_big_endian) |
8153 | expr1.X_add_number = 0; | |
67c0d1eb | 8154 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 8155 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8156 | if (target_big_endian) |
8157 | expr1.X_add_number = 1; | |
8158 | else | |
8159 | expr1.X_add_number = 0; | |
67c0d1eb RS |
8160 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
8161 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
8162 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8163 | break; |
8164 | ||
8165 | case M_USH: | |
8fc2e39e | 8166 | used_at = 1; |
252b5132 RH |
8167 | if (offset_expr.X_add_number >= 0x7fff) |
8168 | as_bad (_("operand overflow")); | |
8169 | if (target_big_endian) | |
f9419b05 | 8170 | ++offset_expr.X_add_number; |
67c0d1eb RS |
8171 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8172 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 8173 | if (target_big_endian) |
f9419b05 | 8174 | --offset_expr.X_add_number; |
252b5132 | 8175 | else |
f9419b05 | 8176 | ++offset_expr.X_add_number; |
67c0d1eb | 8177 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
8178 | break; |
8179 | ||
8180 | case M_USD: | |
8181 | s = "sdl"; | |
8182 | s2 = "sdr"; | |
8183 | off = 7; | |
8184 | goto usw; | |
8185 | case M_USW: | |
8186 | s = "swl"; | |
8187 | s2 = "swr"; | |
8188 | off = 3; | |
8189 | usw: | |
8190 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8191 | as_bad (_("operand overflow")); | |
8192 | if (! target_big_endian) | |
8193 | offset_expr.X_add_number += off; | |
67c0d1eb | 8194 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
8195 | if (! target_big_endian) |
8196 | offset_expr.X_add_number -= off; | |
8197 | else | |
8198 | offset_expr.X_add_number += off; | |
67c0d1eb | 8199 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 8200 | break; |
252b5132 RH |
8201 | |
8202 | case M_USD_A: | |
8203 | s = "sdl"; | |
8204 | s2 = "sdr"; | |
8205 | off = 7; | |
8206 | goto uswa; | |
8207 | case M_USW_A: | |
8208 | s = "swl"; | |
8209 | s2 = "swr"; | |
8210 | off = 3; | |
8211 | uswa: | |
d6bc6245 | 8212 | used_at = 1; |
67c0d1eb | 8213 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8214 | if (breg != 0) |
67c0d1eb | 8215 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8216 | if (! target_big_endian) |
8217 | expr1.X_add_number = off; | |
8218 | else | |
8219 | expr1.X_add_number = 0; | |
67c0d1eb | 8220 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8221 | if (! target_big_endian) |
8222 | expr1.X_add_number = 0; | |
8223 | else | |
8224 | expr1.X_add_number = off; | |
67c0d1eb | 8225 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8226 | break; |
8227 | ||
8228 | case M_USH_A: | |
d6bc6245 | 8229 | used_at = 1; |
67c0d1eb | 8230 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8231 | if (breg != 0) |
67c0d1eb | 8232 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8233 | if (! target_big_endian) |
8234 | expr1.X_add_number = 0; | |
67c0d1eb RS |
8235 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
8236 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
8237 | if (! target_big_endian) |
8238 | expr1.X_add_number = 1; | |
8239 | else | |
8240 | expr1.X_add_number = 0; | |
67c0d1eb | 8241 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8242 | if (! target_big_endian) |
8243 | expr1.X_add_number = 0; | |
8244 | else | |
8245 | expr1.X_add_number = 1; | |
67c0d1eb RS |
8246 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
8247 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
8248 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8249 | break; |
8250 | ||
8251 | default: | |
8252 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 8253 | are added dynamically. */ |
252b5132 RH |
8254 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
8255 | break; | |
8256 | } | |
741fe287 | 8257 | if (!mips_opts.at && used_at) |
8fc2e39e | 8258 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
8259 | } |
8260 | ||
8261 | /* Implement macros in mips16 mode. */ | |
8262 | ||
8263 | static void | |
17a2f251 | 8264 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
8265 | { |
8266 | int mask; | |
8267 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
8268 | expressionS expr1; |
8269 | int dbl; | |
8270 | const char *s, *s2, *s3; | |
8271 | ||
8272 | mask = ip->insn_mo->mask; | |
8273 | ||
bf12938e RS |
8274 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
8275 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
8276 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 8277 | |
252b5132 RH |
8278 | expr1.X_op = O_constant; |
8279 | expr1.X_op_symbol = NULL; | |
8280 | expr1.X_add_symbol = NULL; | |
8281 | expr1.X_add_number = 1; | |
8282 | ||
8283 | dbl = 0; | |
8284 | ||
8285 | switch (mask) | |
8286 | { | |
8287 | default: | |
8288 | internalError (); | |
8289 | ||
8290 | case M_DDIV_3: | |
8291 | dbl = 1; | |
8292 | case M_DIV_3: | |
8293 | s = "mflo"; | |
8294 | goto do_div3; | |
8295 | case M_DREM_3: | |
8296 | dbl = 1; | |
8297 | case M_REM_3: | |
8298 | s = "mfhi"; | |
8299 | do_div3: | |
7d10b47d | 8300 | start_noreorder (); |
67c0d1eb | 8301 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 8302 | expr1.X_add_number = 2; |
67c0d1eb RS |
8303 | macro_build (&expr1, "bnez", "x,p", yreg); |
8304 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 8305 | |
252b5132 RH |
8306 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
8307 | since that causes an overflow. We should do that as well, | |
8308 | but I don't see how to do the comparisons without a temporary | |
8309 | register. */ | |
7d10b47d | 8310 | end_noreorder (); |
67c0d1eb | 8311 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
8312 | break; |
8313 | ||
8314 | case M_DIVU_3: | |
8315 | s = "divu"; | |
8316 | s2 = "mflo"; | |
8317 | goto do_divu3; | |
8318 | case M_REMU_3: | |
8319 | s = "divu"; | |
8320 | s2 = "mfhi"; | |
8321 | goto do_divu3; | |
8322 | case M_DDIVU_3: | |
8323 | s = "ddivu"; | |
8324 | s2 = "mflo"; | |
8325 | goto do_divu3; | |
8326 | case M_DREMU_3: | |
8327 | s = "ddivu"; | |
8328 | s2 = "mfhi"; | |
8329 | do_divu3: | |
7d10b47d | 8330 | start_noreorder (); |
67c0d1eb | 8331 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 8332 | expr1.X_add_number = 2; |
67c0d1eb RS |
8333 | macro_build (&expr1, "bnez", "x,p", yreg); |
8334 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 8335 | end_noreorder (); |
67c0d1eb | 8336 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
8337 | break; |
8338 | ||
8339 | case M_DMUL: | |
8340 | dbl = 1; | |
8341 | case M_MUL: | |
67c0d1eb RS |
8342 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
8343 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 8344 | break; |
252b5132 RH |
8345 | |
8346 | case M_DSUBU_I: | |
8347 | dbl = 1; | |
8348 | goto do_subu; | |
8349 | case M_SUBU_I: | |
8350 | do_subu: | |
8351 | if (imm_expr.X_op != O_constant) | |
8352 | as_bad (_("Unsupported large constant")); | |
8353 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8354 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
8355 | break; |
8356 | ||
8357 | case M_SUBU_I_2: | |
8358 | if (imm_expr.X_op != O_constant) | |
8359 | as_bad (_("Unsupported large constant")); | |
8360 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8361 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
8362 | break; |
8363 | ||
8364 | case M_DSUBU_I_2: | |
8365 | if (imm_expr.X_op != O_constant) | |
8366 | as_bad (_("Unsupported large constant")); | |
8367 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8368 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
8369 | break; |
8370 | ||
8371 | case M_BEQ: | |
8372 | s = "cmp"; | |
8373 | s2 = "bteqz"; | |
8374 | goto do_branch; | |
8375 | case M_BNE: | |
8376 | s = "cmp"; | |
8377 | s2 = "btnez"; | |
8378 | goto do_branch; | |
8379 | case M_BLT: | |
8380 | s = "slt"; | |
8381 | s2 = "btnez"; | |
8382 | goto do_branch; | |
8383 | case M_BLTU: | |
8384 | s = "sltu"; | |
8385 | s2 = "btnez"; | |
8386 | goto do_branch; | |
8387 | case M_BLE: | |
8388 | s = "slt"; | |
8389 | s2 = "bteqz"; | |
8390 | goto do_reverse_branch; | |
8391 | case M_BLEU: | |
8392 | s = "sltu"; | |
8393 | s2 = "bteqz"; | |
8394 | goto do_reverse_branch; | |
8395 | case M_BGE: | |
8396 | s = "slt"; | |
8397 | s2 = "bteqz"; | |
8398 | goto do_branch; | |
8399 | case M_BGEU: | |
8400 | s = "sltu"; | |
8401 | s2 = "bteqz"; | |
8402 | goto do_branch; | |
8403 | case M_BGT: | |
8404 | s = "slt"; | |
8405 | s2 = "btnez"; | |
8406 | goto do_reverse_branch; | |
8407 | case M_BGTU: | |
8408 | s = "sltu"; | |
8409 | s2 = "btnez"; | |
8410 | ||
8411 | do_reverse_branch: | |
8412 | tmp = xreg; | |
8413 | xreg = yreg; | |
8414 | yreg = tmp; | |
8415 | ||
8416 | do_branch: | |
67c0d1eb RS |
8417 | macro_build (NULL, s, "x,y", xreg, yreg); |
8418 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8419 | break; |
8420 | ||
8421 | case M_BEQ_I: | |
8422 | s = "cmpi"; | |
8423 | s2 = "bteqz"; | |
8424 | s3 = "x,U"; | |
8425 | goto do_branch_i; | |
8426 | case M_BNE_I: | |
8427 | s = "cmpi"; | |
8428 | s2 = "btnez"; | |
8429 | s3 = "x,U"; | |
8430 | goto do_branch_i; | |
8431 | case M_BLT_I: | |
8432 | s = "slti"; | |
8433 | s2 = "btnez"; | |
8434 | s3 = "x,8"; | |
8435 | goto do_branch_i; | |
8436 | case M_BLTU_I: | |
8437 | s = "sltiu"; | |
8438 | s2 = "btnez"; | |
8439 | s3 = "x,8"; | |
8440 | goto do_branch_i; | |
8441 | case M_BLE_I: | |
8442 | s = "slti"; | |
8443 | s2 = "btnez"; | |
8444 | s3 = "x,8"; | |
8445 | goto do_addone_branch_i; | |
8446 | case M_BLEU_I: | |
8447 | s = "sltiu"; | |
8448 | s2 = "btnez"; | |
8449 | s3 = "x,8"; | |
8450 | goto do_addone_branch_i; | |
8451 | case M_BGE_I: | |
8452 | s = "slti"; | |
8453 | s2 = "bteqz"; | |
8454 | s3 = "x,8"; | |
8455 | goto do_branch_i; | |
8456 | case M_BGEU_I: | |
8457 | s = "sltiu"; | |
8458 | s2 = "bteqz"; | |
8459 | s3 = "x,8"; | |
8460 | goto do_branch_i; | |
8461 | case M_BGT_I: | |
8462 | s = "slti"; | |
8463 | s2 = "bteqz"; | |
8464 | s3 = "x,8"; | |
8465 | goto do_addone_branch_i; | |
8466 | case M_BGTU_I: | |
8467 | s = "sltiu"; | |
8468 | s2 = "bteqz"; | |
8469 | s3 = "x,8"; | |
8470 | ||
8471 | do_addone_branch_i: | |
8472 | if (imm_expr.X_op != O_constant) | |
8473 | as_bad (_("Unsupported large constant")); | |
8474 | ++imm_expr.X_add_number; | |
8475 | ||
8476 | do_branch_i: | |
67c0d1eb RS |
8477 | macro_build (&imm_expr, s, s3, xreg); |
8478 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8479 | break; |
8480 | ||
8481 | case M_ABS: | |
8482 | expr1.X_add_number = 0; | |
67c0d1eb | 8483 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 8484 | if (xreg != yreg) |
67c0d1eb | 8485 | move_register (xreg, yreg); |
252b5132 | 8486 | expr1.X_add_number = 2; |
67c0d1eb RS |
8487 | macro_build (&expr1, "bteqz", "p"); |
8488 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
8489 | } |
8490 | } | |
8491 | ||
8492 | /* For consistency checking, verify that all bits are specified either | |
8493 | by the match/mask part of the instruction definition, or by the | |
8494 | operand list. */ | |
8495 | static int | |
17a2f251 | 8496 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
8497 | { |
8498 | const char *p = opc->args; | |
8499 | char c; | |
8500 | unsigned long used_bits = opc->mask; | |
8501 | ||
8502 | if ((used_bits & opc->match) != opc->match) | |
8503 | { | |
8504 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8505 | opc->name, opc->args); | |
8506 | return 0; | |
8507 | } | |
8508 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8509 | while (*p) | |
8510 | switch (c = *p++) | |
8511 | { | |
8512 | case ',': break; | |
8513 | case '(': break; | |
8514 | case ')': break; | |
af7ee8bf CD |
8515 | case '+': |
8516 | switch (c = *p++) | |
8517 | { | |
9bcd4f99 TS |
8518 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
8519 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
8520 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
8521 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
8522 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8523 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8524 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8525 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8526 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
8527 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8528 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8529 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8530 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8531 | case 'I': break; | |
ef2e4d86 CF |
8532 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
8533 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
8534 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
8535 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
8536 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
8537 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
8538 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 8539 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
8540 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
8541 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
8542 | ||
af7ee8bf CD |
8543 | default: |
8544 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8545 | c, opc->name, opc->args); | |
8546 | return 0; | |
8547 | } | |
8548 | break; | |
252b5132 RH |
8549 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8550 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8551 | case 'A': break; | |
4372b673 | 8552 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8553 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8554 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8555 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8556 | case 'F': break; | |
8557 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8558 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8559 | case 'I': break; |
e972090a | 8560 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8561 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8562 | case 'L': break; |
8563 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8564 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8565 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8566 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8567 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8568 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8569 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8570 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8571 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8572 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8573 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8574 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8575 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8576 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8577 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8578 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8579 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8580 | case 'f': break; | |
8581 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8582 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8583 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8584 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8585 | case 'l': break; | |
8586 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8587 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8588 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8589 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8590 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8591 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8592 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8593 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8594 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8595 | case 'x': break; | |
8596 | case 'z': break; | |
8597 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8598 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8599 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8600 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8601 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8602 | case '[': break; | |
8603 | case ']': break; | |
620edafd | 8604 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 8605 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
8606 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
8607 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
8608 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
8609 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8610 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
8611 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
8612 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
8613 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
8614 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
8615 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
8616 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
8617 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
8618 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
8619 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
8620 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
8621 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
252b5132 RH |
8622 | default: |
8623 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8624 | c, opc->name, opc->args); | |
8625 | return 0; | |
8626 | } | |
8627 | #undef USE_BITS | |
8628 | if (used_bits != 0xffffffff) | |
8629 | { | |
8630 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8631 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8632 | return 0; | |
8633 | } | |
8634 | return 1; | |
8635 | } | |
8636 | ||
9bcd4f99 TS |
8637 | /* UDI immediates. */ |
8638 | struct mips_immed { | |
8639 | char type; | |
8640 | unsigned int shift; | |
8641 | unsigned long mask; | |
8642 | const char * desc; | |
8643 | }; | |
8644 | ||
8645 | static const struct mips_immed mips_immed[] = { | |
8646 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
8647 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
8648 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
8649 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
8650 | { 0,0,0,0 } | |
8651 | }; | |
8652 | ||
7455baf8 TS |
8653 | /* Check whether an odd floating-point register is allowed. */ |
8654 | static int | |
8655 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
8656 | { | |
8657 | const char *s = insn->name; | |
8658 | ||
8659 | if (insn->pinfo == INSN_MACRO) | |
8660 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
8661 | return 1; | |
8662 | ||
8663 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
8664 | { | |
8665 | /* Allow odd registers for single-precision ops. */ | |
8666 | switch (insn->pinfo & (FP_S | FP_D)) | |
8667 | { | |
8668 | case FP_S: | |
8669 | case 0: | |
8670 | return 1; /* both single precision - ok */ | |
8671 | case FP_D: | |
8672 | return 0; /* both double precision - fail */ | |
8673 | default: | |
8674 | break; | |
8675 | } | |
8676 | ||
8677 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
8678 | s = strchr (insn->name, '.'); | |
8679 | if (argnum == 2) | |
8680 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
8681 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
8682 | } | |
8683 | ||
8684 | /* Single-precision coprocessor loads and moves are OK too. */ | |
8685 | if ((insn->pinfo & FP_S) | |
8686 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
8687 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
8688 | return 1; | |
8689 | ||
8690 | return 0; | |
8691 | } | |
8692 | ||
252b5132 RH |
8693 | /* This routine assembles an instruction into its binary format. As a |
8694 | side effect, it sets one of the global variables imm_reloc or | |
8695 | offset_reloc to the type of relocation to do if one of the operands | |
8696 | is an address expression. */ | |
8697 | ||
8698 | static void | |
17a2f251 | 8699 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8700 | { |
8701 | char *s; | |
8702 | const char *args; | |
43841e91 | 8703 | char c = 0; |
252b5132 RH |
8704 | struct mips_opcode *insn; |
8705 | char *argsStart; | |
8706 | unsigned int regno; | |
8707 | unsigned int lastregno = 0; | |
af7ee8bf | 8708 | unsigned int lastpos = 0; |
071742cf | 8709 | unsigned int limlo, limhi; |
252b5132 RH |
8710 | char *s_reset; |
8711 | char save_c = 0; | |
74cd071d | 8712 | offsetT min_range, max_range; |
707bfff6 TS |
8713 | int argnum; |
8714 | unsigned int rtype; | |
252b5132 RH |
8715 | |
8716 | insn_error = NULL; | |
8717 | ||
8718 | /* If the instruction contains a '.', we first try to match an instruction | |
8719 | including the '.'. Then we try again without the '.'. */ | |
8720 | insn = NULL; | |
3882b010 | 8721 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8722 | continue; |
8723 | ||
8724 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8725 | the call to hash_find. Save the character we replaced just in case we | |
8726 | have to re-parse the instruction. */ | |
3882b010 | 8727 | if (ISSPACE (*s)) |
252b5132 RH |
8728 | { |
8729 | save_c = *s; | |
8730 | *s++ = '\0'; | |
8731 | } | |
bdaaa2e1 | 8732 | |
252b5132 RH |
8733 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8734 | ||
8735 | /* If we didn't find the instruction in the opcode table, try again, but | |
8736 | this time with just the instruction up to, but not including the | |
8737 | first '.'. */ | |
8738 | if (insn == NULL) | |
8739 | { | |
bdaaa2e1 | 8740 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8741 | if (save_c) |
8742 | *(--s) = save_c; | |
8743 | ||
8744 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8745 | for (s = str; |
8746 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8747 | ++s) | |
252b5132 RH |
8748 | continue; |
8749 | ||
8750 | /* If we did not find a '.', then we can quit now. */ | |
8751 | if (*s != '.') | |
8752 | { | |
20203fb9 | 8753 | insn_error = _("unrecognized opcode"); |
252b5132 RH |
8754 | return; |
8755 | } | |
8756 | ||
8757 | /* Lookup the instruction in the hash table. */ | |
8758 | *s++ = '\0'; | |
8759 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8760 | { | |
20203fb9 | 8761 | insn_error = _("unrecognized opcode"); |
252b5132 RH |
8762 | return; |
8763 | } | |
252b5132 RH |
8764 | } |
8765 | ||
8766 | argsStart = s; | |
8767 | for (;;) | |
8768 | { | |
b34976b6 | 8769 | bfd_boolean ok; |
252b5132 | 8770 | |
9c2799c2 | 8771 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 8772 | |
f79e2745 | 8773 | ok = is_opcode_valid (insn); |
252b5132 RH |
8774 | if (! ok) |
8775 | { | |
8776 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8777 | && strcmp (insn->name, insn[1].name) == 0) | |
8778 | { | |
8779 | ++insn; | |
8780 | continue; | |
8781 | } | |
252b5132 | 8782 | else |
beae10d5 | 8783 | { |
268f6bed L |
8784 | if (!insn_error) |
8785 | { | |
8786 | static char buf[100]; | |
fef14a42 TS |
8787 | sprintf (buf, |
8788 | _("opcode not supported on this processor: %s (%s)"), | |
8789 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8790 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8791 | insn_error = buf; |
8792 | } | |
8793 | if (save_c) | |
8794 | *(--s) = save_c; | |
2bd7f1f3 | 8795 | return; |
252b5132 | 8796 | } |
252b5132 RH |
8797 | } |
8798 | ||
1e915849 | 8799 | create_insn (ip, insn); |
268f6bed | 8800 | insn_error = NULL; |
707bfff6 | 8801 | argnum = 1; |
24864476 | 8802 | lastregno = 0xffffffff; |
252b5132 RH |
8803 | for (args = insn->args;; ++args) |
8804 | { | |
deec1734 CD |
8805 | int is_mdmx; |
8806 | ||
ad8d3bb3 | 8807 | s += strspn (s, " \t"); |
deec1734 | 8808 | is_mdmx = 0; |
252b5132 RH |
8809 | switch (*args) |
8810 | { | |
8811 | case '\0': /* end of args */ | |
8812 | if (*s == '\0') | |
8813 | return; | |
8814 | break; | |
8815 | ||
8b082fb1 TS |
8816 | case '2': /* dsp 2-bit unsigned immediate in bit 11 */ |
8817 | my_getExpression (&imm_expr, s); | |
8818 | check_absolute_expr (ip, &imm_expr); | |
8819 | if ((unsigned long) imm_expr.X_add_number != 1 | |
8820 | && (unsigned long) imm_expr.X_add_number != 3) | |
8821 | { | |
8822 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
8823 | (unsigned long) imm_expr.X_add_number); | |
8824 | } | |
8825 | INSERT_OPERAND (BP, *ip, imm_expr.X_add_number); | |
8826 | imm_expr.X_op = O_absent; | |
8827 | s = expr_end; | |
8828 | continue; | |
8829 | ||
74cd071d CF |
8830 | case '3': /* dsp 3-bit unsigned immediate in bit 21 */ |
8831 | my_getExpression (&imm_expr, s); | |
8832 | check_absolute_expr (ip, &imm_expr); | |
8833 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
8834 | { | |
a9e24354 TS |
8835 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8836 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8837 | } |
a9e24354 | 8838 | INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number); |
74cd071d CF |
8839 | imm_expr.X_op = O_absent; |
8840 | s = expr_end; | |
8841 | continue; | |
8842 | ||
8843 | case '4': /* dsp 4-bit unsigned immediate in bit 21 */ | |
8844 | my_getExpression (&imm_expr, s); | |
8845 | check_absolute_expr (ip, &imm_expr); | |
8846 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
8847 | { | |
a9e24354 TS |
8848 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8849 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8850 | } |
a9e24354 | 8851 | INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number); |
74cd071d CF |
8852 | imm_expr.X_op = O_absent; |
8853 | s = expr_end; | |
8854 | continue; | |
8855 | ||
8856 | case '5': /* dsp 8-bit unsigned immediate in bit 16 */ | |
8857 | my_getExpression (&imm_expr, s); | |
8858 | check_absolute_expr (ip, &imm_expr); | |
8859 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
8860 | { | |
a9e24354 TS |
8861 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8862 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8863 | } |
a9e24354 | 8864 | INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number); |
74cd071d CF |
8865 | imm_expr.X_op = O_absent; |
8866 | s = expr_end; | |
8867 | continue; | |
8868 | ||
8869 | case '6': /* dsp 5-bit unsigned immediate in bit 21 */ | |
8870 | my_getExpression (&imm_expr, s); | |
8871 | check_absolute_expr (ip, &imm_expr); | |
8872 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
8873 | { | |
a9e24354 TS |
8874 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8875 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8876 | } |
a9e24354 | 8877 | INSERT_OPERAND (RS, *ip, imm_expr.X_add_number); |
74cd071d CF |
8878 | imm_expr.X_op = O_absent; |
8879 | s = expr_end; | |
8880 | continue; | |
8881 | ||
8882 | case '7': /* four dsp accumulators in bits 11,12 */ | |
8883 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8884 | s[3] >= '0' && s[3] <= '3') | |
8885 | { | |
8886 | regno = s[3] - '0'; | |
8887 | s += 4; | |
a9e24354 | 8888 | INSERT_OPERAND (DSPACC, *ip, regno); |
74cd071d CF |
8889 | continue; |
8890 | } | |
8891 | else | |
8892 | as_bad (_("Invalid dsp acc register")); | |
8893 | break; | |
8894 | ||
8895 | case '8': /* dsp 6-bit unsigned immediate in bit 11 */ | |
8896 | my_getExpression (&imm_expr, s); | |
8897 | check_absolute_expr (ip, &imm_expr); | |
8898 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
8899 | { | |
a9e24354 TS |
8900 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8901 | OP_MASK_WRDSP, | |
8902 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8903 | } |
a9e24354 | 8904 | INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8905 | imm_expr.X_op = O_absent; |
8906 | s = expr_end; | |
8907 | continue; | |
8908 | ||
8909 | case '9': /* four dsp accumulators in bits 21,22 */ | |
8910 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8911 | s[3] >= '0' && s[3] <= '3') | |
8912 | { | |
8913 | regno = s[3] - '0'; | |
8914 | s += 4; | |
a9e24354 | 8915 | INSERT_OPERAND (DSPACC_S, *ip, regno); |
74cd071d CF |
8916 | continue; |
8917 | } | |
8918 | else | |
8919 | as_bad (_("Invalid dsp acc register")); | |
8920 | break; | |
8921 | ||
8922 | case '0': /* dsp 6-bit signed immediate in bit 20 */ | |
8923 | my_getExpression (&imm_expr, s); | |
8924 | check_absolute_expr (ip, &imm_expr); | |
8925 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
8926 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
8927 | if (imm_expr.X_add_number < min_range || | |
8928 | imm_expr.X_add_number > max_range) | |
8929 | { | |
a9e24354 TS |
8930 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8931 | (long) min_range, (long) max_range, | |
8932 | (long) imm_expr.X_add_number); | |
74cd071d | 8933 | } |
a9e24354 | 8934 | INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number); |
74cd071d CF |
8935 | imm_expr.X_op = O_absent; |
8936 | s = expr_end; | |
8937 | continue; | |
8938 | ||
8939 | case '\'': /* dsp 6-bit unsigned immediate in bit 16 */ | |
8940 | my_getExpression (&imm_expr, s); | |
8941 | check_absolute_expr (ip, &imm_expr); | |
8942 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
8943 | { | |
a9e24354 TS |
8944 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8945 | OP_MASK_RDDSP, | |
8946 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8947 | } |
a9e24354 | 8948 | INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8949 | imm_expr.X_op = O_absent; |
8950 | s = expr_end; | |
8951 | continue; | |
8952 | ||
8953 | case ':': /* dsp 7-bit signed immediate in bit 19 */ | |
8954 | my_getExpression (&imm_expr, s); | |
8955 | check_absolute_expr (ip, &imm_expr); | |
8956 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
8957 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
8958 | if (imm_expr.X_add_number < min_range || | |
8959 | imm_expr.X_add_number > max_range) | |
8960 | { | |
a9e24354 TS |
8961 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8962 | (long) min_range, (long) max_range, | |
8963 | (long) imm_expr.X_add_number); | |
74cd071d | 8964 | } |
a9e24354 | 8965 | INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
8966 | imm_expr.X_op = O_absent; |
8967 | s = expr_end; | |
8968 | continue; | |
8969 | ||
8970 | case '@': /* dsp 10-bit signed immediate in bit 16 */ | |
8971 | my_getExpression (&imm_expr, s); | |
8972 | check_absolute_expr (ip, &imm_expr); | |
8973 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
8974 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
8975 | if (imm_expr.X_add_number < min_range || | |
8976 | imm_expr.X_add_number > max_range) | |
8977 | { | |
a9e24354 TS |
8978 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8979 | (long) min_range, (long) max_range, | |
8980 | (long) imm_expr.X_add_number); | |
74cd071d | 8981 | } |
a9e24354 | 8982 | INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number); |
74cd071d CF |
8983 | imm_expr.X_op = O_absent; |
8984 | s = expr_end; | |
8985 | continue; | |
8986 | ||
a9e24354 | 8987 | case '!': /* MT usermode flag bit. */ |
ef2e4d86 CF |
8988 | my_getExpression (&imm_expr, s); |
8989 | check_absolute_expr (ip, &imm_expr); | |
8990 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
8991 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
8992 | (unsigned long) imm_expr.X_add_number); | |
8993 | INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8994 | imm_expr.X_op = O_absent; |
8995 | s = expr_end; | |
8996 | continue; | |
8997 | ||
a9e24354 | 8998 | case '$': /* MT load high flag bit. */ |
ef2e4d86 CF |
8999 | my_getExpression (&imm_expr, s); |
9000 | check_absolute_expr (ip, &imm_expr); | |
9001 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
9002 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
9003 | (unsigned long) imm_expr.X_add_number); | |
9004 | INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
9005 | imm_expr.X_op = O_absent; |
9006 | s = expr_end; | |
9007 | continue; | |
9008 | ||
9009 | case '*': /* four dsp accumulators in bits 18,19 */ | |
9010 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
9011 | s[3] >= '0' && s[3] <= '3') | |
9012 | { | |
9013 | regno = s[3] - '0'; | |
9014 | s += 4; | |
a9e24354 | 9015 | INSERT_OPERAND (MTACC_T, *ip, regno); |
ef2e4d86 CF |
9016 | continue; |
9017 | } | |
9018 | else | |
9019 | as_bad (_("Invalid dsp/smartmips acc register")); | |
9020 | break; | |
9021 | ||
9022 | case '&': /* four dsp accumulators in bits 13,14 */ | |
9023 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
9024 | s[3] >= '0' && s[3] <= '3') | |
9025 | { | |
9026 | regno = s[3] - '0'; | |
9027 | s += 4; | |
a9e24354 | 9028 | INSERT_OPERAND (MTACC_D, *ip, regno); |
ef2e4d86 CF |
9029 | continue; |
9030 | } | |
9031 | else | |
9032 | as_bad (_("Invalid dsp/smartmips acc register")); | |
9033 | break; | |
9034 | ||
252b5132 | 9035 | case ',': |
a339155f | 9036 | ++argnum; |
252b5132 RH |
9037 | if (*s++ == *args) |
9038 | continue; | |
9039 | s--; | |
9040 | switch (*++args) | |
9041 | { | |
9042 | case 'r': | |
9043 | case 'v': | |
bf12938e | 9044 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9045 | continue; |
9046 | ||
9047 | case 'w': | |
bf12938e | 9048 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
9049 | continue; |
9050 | ||
252b5132 | 9051 | case 'W': |
bf12938e | 9052 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9053 | continue; |
9054 | ||
9055 | case 'V': | |
bf12938e | 9056 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9057 | continue; |
9058 | } | |
9059 | break; | |
9060 | ||
9061 | case '(': | |
9062 | /* Handle optional base register. | |
9063 | Either the base register is omitted or | |
bdaaa2e1 | 9064 | we must have a left paren. */ |
252b5132 RH |
9065 | /* This is dependent on the next operand specifier |
9066 | is a base register specification. */ | |
9c2799c2 | 9067 | gas_assert (args[1] == 'b' || args[1] == '5' |
252b5132 RH |
9068 | || args[1] == '-' || args[1] == '4'); |
9069 | if (*s == '\0') | |
9070 | return; | |
9071 | ||
9072 | case ')': /* these must match exactly */ | |
60b63b72 RS |
9073 | case '[': |
9074 | case ']': | |
252b5132 RH |
9075 | if (*s++ == *args) |
9076 | continue; | |
9077 | break; | |
9078 | ||
af7ee8bf CD |
9079 | case '+': /* Opcode extension character. */ |
9080 | switch (*++args) | |
9081 | { | |
9bcd4f99 TS |
9082 | case '1': /* UDI immediates. */ |
9083 | case '2': | |
9084 | case '3': | |
9085 | case '4': | |
9086 | { | |
9087 | const struct mips_immed *imm = mips_immed; | |
9088 | ||
9089 | while (imm->type && imm->type != *args) | |
9090 | ++imm; | |
9091 | if (! imm->type) | |
9092 | internalError (); | |
9093 | my_getExpression (&imm_expr, s); | |
9094 | check_absolute_expr (ip, &imm_expr); | |
9095 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
9096 | { | |
9097 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
9098 | imm->desc ? imm->desc : ip->insn_mo->name, | |
9099 | (unsigned long) imm_expr.X_add_number, | |
9100 | (unsigned long) imm_expr.X_add_number); | |
9101 | imm_expr.X_add_number &= imm->mask; | |
9102 | } | |
9103 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
9104 | << imm->shift); | |
9105 | imm_expr.X_op = O_absent; | |
9106 | s = expr_end; | |
9107 | } | |
9108 | continue; | |
9109 | ||
071742cf CD |
9110 | case 'A': /* ins/ext position, becomes LSB. */ |
9111 | limlo = 0; | |
9112 | limhi = 31; | |
5f74bc13 CD |
9113 | goto do_lsb; |
9114 | case 'E': | |
9115 | limlo = 32; | |
9116 | limhi = 63; | |
9117 | goto do_lsb; | |
9118 | do_lsb: | |
071742cf CD |
9119 | my_getExpression (&imm_expr, s); |
9120 | check_absolute_expr (ip, &imm_expr); | |
9121 | if ((unsigned long) imm_expr.X_add_number < limlo | |
9122 | || (unsigned long) imm_expr.X_add_number > limhi) | |
9123 | { | |
9124 | as_bad (_("Improper position (%lu)"), | |
9125 | (unsigned long) imm_expr.X_add_number); | |
9126 | imm_expr.X_add_number = limlo; | |
9127 | } | |
9128 | lastpos = imm_expr.X_add_number; | |
bf12938e | 9129 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
9130 | imm_expr.X_op = O_absent; |
9131 | s = expr_end; | |
9132 | continue; | |
9133 | ||
9134 | case 'B': /* ins size, becomes MSB. */ | |
9135 | limlo = 1; | |
9136 | limhi = 32; | |
5f74bc13 CD |
9137 | goto do_msb; |
9138 | case 'F': | |
9139 | limlo = 33; | |
9140 | limhi = 64; | |
9141 | goto do_msb; | |
9142 | do_msb: | |
071742cf CD |
9143 | my_getExpression (&imm_expr, s); |
9144 | check_absolute_expr (ip, &imm_expr); | |
9145 | /* Check for negative input so that small negative numbers | |
9146 | will not succeed incorrectly. The checks against | |
9147 | (pos+size) transitively check "size" itself, | |
9148 | assuming that "pos" is reasonable. */ | |
9149 | if ((long) imm_expr.X_add_number < 0 | |
9150 | || ((unsigned long) imm_expr.X_add_number | |
9151 | + lastpos) < limlo | |
9152 | || ((unsigned long) imm_expr.X_add_number | |
9153 | + lastpos) > limhi) | |
9154 | { | |
9155 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
9156 | (unsigned long) imm_expr.X_add_number, | |
9157 | (unsigned long) lastpos); | |
9158 | imm_expr.X_add_number = limlo - lastpos; | |
9159 | } | |
bf12938e RS |
9160 | INSERT_OPERAND (INSMSB, *ip, |
9161 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
9162 | imm_expr.X_op = O_absent; |
9163 | s = expr_end; | |
9164 | continue; | |
9165 | ||
9166 | case 'C': /* ext size, becomes MSBD. */ | |
9167 | limlo = 1; | |
9168 | limhi = 32; | |
5f74bc13 CD |
9169 | goto do_msbd; |
9170 | case 'G': | |
9171 | limlo = 33; | |
9172 | limhi = 64; | |
9173 | goto do_msbd; | |
9174 | case 'H': | |
9175 | limlo = 33; | |
9176 | limhi = 64; | |
9177 | goto do_msbd; | |
9178 | do_msbd: | |
071742cf CD |
9179 | my_getExpression (&imm_expr, s); |
9180 | check_absolute_expr (ip, &imm_expr); | |
9181 | /* Check for negative input so that small negative numbers | |
9182 | will not succeed incorrectly. The checks against | |
9183 | (pos+size) transitively check "size" itself, | |
9184 | assuming that "pos" is reasonable. */ | |
9185 | if ((long) imm_expr.X_add_number < 0 | |
9186 | || ((unsigned long) imm_expr.X_add_number | |
9187 | + lastpos) < limlo | |
9188 | || ((unsigned long) imm_expr.X_add_number | |
9189 | + lastpos) > limhi) | |
9190 | { | |
9191 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
9192 | (unsigned long) imm_expr.X_add_number, | |
9193 | (unsigned long) lastpos); | |
9194 | imm_expr.X_add_number = limlo - lastpos; | |
9195 | } | |
bf12938e | 9196 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
9197 | imm_expr.X_op = O_absent; |
9198 | s = expr_end; | |
9199 | continue; | |
af7ee8bf | 9200 | |
bbcc0807 CD |
9201 | case 'D': |
9202 | /* +D is for disassembly only; never match. */ | |
9203 | break; | |
9204 | ||
5f74bc13 CD |
9205 | case 'I': |
9206 | /* "+I" is like "I", except that imm2_expr is used. */ | |
9207 | my_getExpression (&imm2_expr, s); | |
9208 | if (imm2_expr.X_op != O_big | |
9209 | && imm2_expr.X_op != O_constant) | |
9210 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9211 | if (HAVE_32BIT_GPRS) |
9212 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
9213 | s = expr_end; |
9214 | continue; | |
9215 | ||
707bfff6 | 9216 | case 'T': /* Coprocessor register. */ |
ef2e4d86 CF |
9217 | /* +T is for disassembly only; never match. */ |
9218 | break; | |
9219 | ||
707bfff6 | 9220 | case 't': /* Coprocessor register number. */ |
ef2e4d86 CF |
9221 | if (s[0] == '$' && ISDIGIT (s[1])) |
9222 | { | |
9223 | ++s; | |
9224 | regno = 0; | |
9225 | do | |
9226 | { | |
9227 | regno *= 10; | |
9228 | regno += *s - '0'; | |
9229 | ++s; | |
9230 | } | |
9231 | while (ISDIGIT (*s)); | |
9232 | if (regno > 31) | |
9233 | as_bad (_("Invalid register number (%d)"), regno); | |
9234 | else | |
9235 | { | |
a9e24354 | 9236 | INSERT_OPERAND (RT, *ip, regno); |
ef2e4d86 CF |
9237 | continue; |
9238 | } | |
9239 | } | |
9240 | else | |
9241 | as_bad (_("Invalid coprocessor 0 register number")); | |
9242 | break; | |
9243 | ||
bb35fb24 NC |
9244 | case 'x': |
9245 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
9246 | is not in the valid range. */ | |
9247 | my_getExpression (&imm_expr, s); | |
9248 | check_absolute_expr (ip, &imm_expr); | |
9249 | if ((unsigned) imm_expr.X_add_number > 31) | |
9250 | { | |
9251 | as_bad (_("Improper bit index (%lu)"), | |
9252 | (unsigned long) imm_expr.X_add_number); | |
9253 | imm_expr.X_add_number = 0; | |
9254 | } | |
9255 | INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number); | |
9256 | imm_expr.X_op = O_absent; | |
9257 | s = expr_end; | |
9258 | continue; | |
9259 | ||
9260 | case 'X': | |
9261 | /* bbit[01] bit index when bbit is used but we generate | |
9262 | bbit[01]32 because the index is over 32. Move to the | |
9263 | next candidate if index is not in the valid range. */ | |
9264 | my_getExpression (&imm_expr, s); | |
9265 | check_absolute_expr (ip, &imm_expr); | |
9266 | if ((unsigned) imm_expr.X_add_number < 32 | |
9267 | || (unsigned) imm_expr.X_add_number > 63) | |
9268 | break; | |
9269 | INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32); | |
9270 | imm_expr.X_op = O_absent; | |
9271 | s = expr_end; | |
9272 | continue; | |
9273 | ||
9274 | case 'p': | |
9275 | /* cins, cins32, exts and exts32 position field. Give error | |
9276 | if it's not in the valid range. */ | |
9277 | my_getExpression (&imm_expr, s); | |
9278 | check_absolute_expr (ip, &imm_expr); | |
9279 | if ((unsigned) imm_expr.X_add_number > 31) | |
9280 | { | |
9281 | as_bad (_("Improper position (%lu)"), | |
9282 | (unsigned long) imm_expr.X_add_number); | |
9283 | imm_expr.X_add_number = 0; | |
9284 | } | |
9285 | /* Make the pos explicit to simplify +S. */ | |
9286 | lastpos = imm_expr.X_add_number + 32; | |
9287 | INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number); | |
9288 | imm_expr.X_op = O_absent; | |
9289 | s = expr_end; | |
9290 | continue; | |
9291 | ||
9292 | case 'P': | |
9293 | /* cins, cins32, exts and exts32 position field. Move to | |
9294 | the next candidate if it's not in the valid range. */ | |
9295 | my_getExpression (&imm_expr, s); | |
9296 | check_absolute_expr (ip, &imm_expr); | |
9297 | if ((unsigned) imm_expr.X_add_number < 32 | |
9298 | || (unsigned) imm_expr.X_add_number > 63) | |
9299 | break; | |
9300 | lastpos = imm_expr.X_add_number; | |
9301 | INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32); | |
9302 | imm_expr.X_op = O_absent; | |
9303 | s = expr_end; | |
9304 | continue; | |
9305 | ||
9306 | case 's': | |
9307 | /* cins and exts length-minus-one field. */ | |
9308 | my_getExpression (&imm_expr, s); | |
9309 | check_absolute_expr (ip, &imm_expr); | |
9310 | if ((unsigned long) imm_expr.X_add_number > 31) | |
9311 | { | |
9312 | as_bad (_("Improper size (%lu)"), | |
9313 | (unsigned long) imm_expr.X_add_number); | |
9314 | imm_expr.X_add_number = 0; | |
9315 | } | |
9316 | INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number); | |
9317 | imm_expr.X_op = O_absent; | |
9318 | s = expr_end; | |
9319 | continue; | |
9320 | ||
9321 | case 'S': | |
9322 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
9323 | length-minus-one field. */ | |
9324 | my_getExpression (&imm_expr, s); | |
9325 | check_absolute_expr (ip, &imm_expr); | |
9326 | if ((long) imm_expr.X_add_number < 0 | |
9327 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
9328 | { | |
9329 | as_bad (_("Improper size (%lu)"), | |
9330 | (unsigned long) imm_expr.X_add_number); | |
9331 | imm_expr.X_add_number = 0; | |
9332 | } | |
9333 | INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number); | |
9334 | imm_expr.X_op = O_absent; | |
9335 | s = expr_end; | |
9336 | continue; | |
9337 | ||
dd3cbb7e NC |
9338 | case 'Q': |
9339 | /* seqi/snei immediate field. */ | |
9340 | my_getExpression (&imm_expr, s); | |
9341 | check_absolute_expr (ip, &imm_expr); | |
9342 | if ((long) imm_expr.X_add_number < -512 | |
9343 | || (long) imm_expr.X_add_number >= 512) | |
9344 | { | |
9345 | as_bad (_("Improper immediate (%ld)"), | |
9346 | (long) imm_expr.X_add_number); | |
9347 | imm_expr.X_add_number = 0; | |
9348 | } | |
9349 | INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number); | |
9350 | imm_expr.X_op = O_absent; | |
9351 | s = expr_end; | |
9352 | continue; | |
9353 | ||
af7ee8bf CD |
9354 | default: |
9355 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
9356 | *args, insn->name, insn->args); | |
9357 | /* Further processing is fruitless. */ | |
9358 | return; | |
9359 | } | |
9360 | break; | |
9361 | ||
252b5132 RH |
9362 | case '<': /* must be at least one digit */ |
9363 | /* | |
9364 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
9365 | * than 31 or less than 0, then the shift amount should be |
9366 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
9367 | * We issue a warning and mask out all but the low 5 bits. |
9368 | */ | |
9369 | my_getExpression (&imm_expr, s); | |
9370 | check_absolute_expr (ip, &imm_expr); | |
9371 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
9372 | as_warn (_("Improper shift amount (%lu)"), |
9373 | (unsigned long) imm_expr.X_add_number); | |
9374 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9375 | imm_expr.X_op = O_absent; |
9376 | s = expr_end; | |
9377 | continue; | |
9378 | ||
9379 | case '>': /* shift amount minus 32 */ | |
9380 | my_getExpression (&imm_expr, s); | |
9381 | check_absolute_expr (ip, &imm_expr); | |
9382 | if ((unsigned long) imm_expr.X_add_number < 32 | |
9383 | || (unsigned long) imm_expr.X_add_number > 63) | |
9384 | break; | |
bf12938e | 9385 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
9386 | imm_expr.X_op = O_absent; |
9387 | s = expr_end; | |
9388 | continue; | |
9389 | ||
252b5132 RH |
9390 | case 'k': /* cache code */ |
9391 | case 'h': /* prefx code */ | |
620edafd | 9392 | case '1': /* sync type */ |
252b5132 RH |
9393 | my_getExpression (&imm_expr, s); |
9394 | check_absolute_expr (ip, &imm_expr); | |
9395 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
9396 | as_warn (_("Invalid value for `%s' (%lu)"), |
9397 | ip->insn_mo->name, | |
9398 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 9399 | if (*args == 'k') |
bf12938e | 9400 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); |
620edafd | 9401 | else if (*args == 'h') |
bf12938e | 9402 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
620edafd CF |
9403 | else |
9404 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9405 | imm_expr.X_op = O_absent; |
9406 | s = expr_end; | |
9407 | continue; | |
9408 | ||
9409 | case 'c': /* break code */ | |
9410 | my_getExpression (&imm_expr, s); | |
9411 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9412 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE) |
9413 | as_warn (_("Code for %s not in range 0..1023 (%lu)"), | |
9414 | ip->insn_mo->name, | |
bf12938e RS |
9415 | (unsigned long) imm_expr.X_add_number); |
9416 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9417 | imm_expr.X_op = O_absent; |
9418 | s = expr_end; | |
9419 | continue; | |
9420 | ||
9421 | case 'q': /* lower break code */ | |
9422 | my_getExpression (&imm_expr, s); | |
9423 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9424 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2) |
9425 | as_warn (_("Lower code for %s not in range 0..1023 (%lu)"), | |
9426 | ip->insn_mo->name, | |
bf12938e RS |
9427 | (unsigned long) imm_expr.X_add_number); |
9428 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9429 | imm_expr.X_op = O_absent; |
9430 | s = expr_end; | |
9431 | continue; | |
9432 | ||
4372b673 | 9433 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 9434 | my_getExpression (&imm_expr, s); |
156c2f8b | 9435 | check_absolute_expr (ip, &imm_expr); |
793b27f4 | 9436 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
a9e24354 TS |
9437 | as_warn (_("Code for %s not in range 0..1048575 (%lu)"), |
9438 | ip->insn_mo->name, | |
793b27f4 | 9439 | (unsigned long) imm_expr.X_add_number); |
bf12938e | 9440 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
9441 | imm_expr.X_op = O_absent; |
9442 | s = expr_end; | |
9443 | continue; | |
9444 | ||
98d3f06f | 9445 | case 'C': /* Coprocessor code */ |
beae10d5 | 9446 | my_getExpression (&imm_expr, s); |
252b5132 | 9447 | check_absolute_expr (ip, &imm_expr); |
a9e24354 | 9448 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ) |
252b5132 | 9449 | { |
793b27f4 TS |
9450 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
9451 | (unsigned long) imm_expr.X_add_number); | |
a9e24354 | 9452 | imm_expr.X_add_number &= OP_MASK_COPZ; |
252b5132 | 9453 | } |
a9e24354 | 9454 | INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number); |
beae10d5 KH |
9455 | imm_expr.X_op = O_absent; |
9456 | s = expr_end; | |
9457 | continue; | |
252b5132 | 9458 | |
4372b673 NC |
9459 | case 'J': /* 19-bit wait code. */ |
9460 | my_getExpression (&imm_expr, s); | |
9461 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 9462 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
a9e24354 TS |
9463 | { |
9464 | as_warn (_("Illegal 19-bit code (%lu)"), | |
9465 | (unsigned long) imm_expr.X_add_number); | |
9466 | imm_expr.X_add_number &= OP_MASK_CODE19; | |
9467 | } | |
bf12938e | 9468 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
9469 | imm_expr.X_op = O_absent; |
9470 | s = expr_end; | |
9471 | continue; | |
9472 | ||
707bfff6 | 9473 | case 'P': /* Performance register. */ |
beae10d5 | 9474 | my_getExpression (&imm_expr, s); |
252b5132 | 9475 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 9476 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
9477 | as_warn (_("Invalid performance register (%lu)"), |
9478 | (unsigned long) imm_expr.X_add_number); | |
9479 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
9480 | imm_expr.X_op = O_absent; |
9481 | s = expr_end; | |
9482 | continue; | |
252b5132 | 9483 | |
707bfff6 TS |
9484 | case 'G': /* Coprocessor destination register. */ |
9485 | if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0) | |
9486 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no); | |
9487 | else | |
9488 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
a9e24354 | 9489 | INSERT_OPERAND (RD, *ip, regno); |
707bfff6 TS |
9490 | if (ok) |
9491 | { | |
9492 | lastregno = regno; | |
9493 | continue; | |
9494 | } | |
9495 | else | |
9496 | break; | |
9497 | ||
252b5132 RH |
9498 | case 'b': /* base register */ |
9499 | case 'd': /* destination register */ | |
9500 | case 's': /* source register */ | |
9501 | case 't': /* target register */ | |
9502 | case 'r': /* both target and source */ | |
9503 | case 'v': /* both dest and source */ | |
9504 | case 'w': /* both dest and target */ | |
9505 | case 'E': /* coprocessor target register */ | |
af7ee8bf | 9506 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
9507 | case 'x': /* ignore register name */ |
9508 | case 'z': /* must be zero register */ | |
4372b673 | 9509 | case 'U': /* destination register (clo/clz). */ |
ef2e4d86 | 9510 | case 'g': /* coprocessor destination register */ |
707bfff6 TS |
9511 | s_reset = s; |
9512 | if (*args == 'E' || *args == 'K') | |
9513 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
9514 | else | |
9515 | { | |
9516 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
9517 | if (regno == AT && mips_opts.at) |
9518 | { | |
9519 | if (mips_opts.at == ATREG) | |
9520 | as_warn (_("used $at without \".set noat\"")); | |
9521 | else | |
9522 | as_warn (_("used $%u with \".set at=$%u\""), | |
9523 | regno, mips_opts.at); | |
9524 | } | |
707bfff6 TS |
9525 | } |
9526 | if (ok) | |
252b5132 | 9527 | { |
252b5132 RH |
9528 | c = *args; |
9529 | if (*s == ' ') | |
f9419b05 | 9530 | ++s; |
252b5132 RH |
9531 | if (args[1] != *s) |
9532 | { | |
9533 | if (c == 'r' || c == 'v' || c == 'w') | |
9534 | { | |
9535 | regno = lastregno; | |
9536 | s = s_reset; | |
f9419b05 | 9537 | ++args; |
252b5132 RH |
9538 | } |
9539 | } | |
9540 | /* 'z' only matches $0. */ | |
9541 | if (c == 'z' && regno != 0) | |
9542 | break; | |
9543 | ||
24864476 | 9544 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
9545 | { |
9546 | if (regno == lastregno) | |
9547 | { | |
24864476 | 9548 | insn_error = _("source and destination must be different"); |
e7c604dd CM |
9549 | continue; |
9550 | } | |
24864476 | 9551 | if (regno == 31 && lastregno == 0xffffffff) |
e7c604dd CM |
9552 | { |
9553 | insn_error = _("a destination register must be supplied"); | |
9554 | continue; | |
9555 | } | |
9556 | } | |
bdaaa2e1 KH |
9557 | /* Now that we have assembled one operand, we use the args string |
9558 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
9559 | switch (c) |
9560 | { | |
9561 | case 'r': | |
9562 | case 's': | |
9563 | case 'v': | |
9564 | case 'b': | |
bf12938e | 9565 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
9566 | break; |
9567 | case 'd': | |
9568 | case 'G': | |
af7ee8bf | 9569 | case 'K': |
ef2e4d86 | 9570 | case 'g': |
bf12938e | 9571 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 9572 | break; |
4372b673 | 9573 | case 'U': |
bf12938e RS |
9574 | INSERT_OPERAND (RD, *ip, regno); |
9575 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 9576 | break; |
252b5132 RH |
9577 | case 'w': |
9578 | case 't': | |
9579 | case 'E': | |
bf12938e | 9580 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
9581 | break; |
9582 | case 'x': | |
9583 | /* This case exists because on the r3000 trunc | |
9584 | expands into a macro which requires a gp | |
9585 | register. On the r6000 or r4000 it is | |
9586 | assembled into a single instruction which | |
9587 | ignores the register. Thus the insn version | |
9588 | is MIPS_ISA2 and uses 'x', and the macro | |
9589 | version is MIPS_ISA1 and uses 't'. */ | |
9590 | break; | |
9591 | case 'z': | |
9592 | /* This case is for the div instruction, which | |
9593 | acts differently if the destination argument | |
9594 | is $0. This only matches $0, and is checked | |
9595 | outside the switch. */ | |
9596 | break; | |
9597 | case 'D': | |
9598 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
9599 | break; | |
9600 | /* What about all other operands like 'i', which | |
9601 | can be specified in the opcode table? */ | |
9602 | } | |
9603 | lastregno = regno; | |
9604 | continue; | |
9605 | } | |
252b5132 RH |
9606 | switch (*args++) |
9607 | { | |
9608 | case 'r': | |
9609 | case 'v': | |
bf12938e | 9610 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9611 | continue; |
9612 | case 'w': | |
bf12938e | 9613 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
9614 | continue; |
9615 | } | |
9616 | break; | |
9617 | ||
deec1734 CD |
9618 | case 'O': /* MDMX alignment immediate constant. */ |
9619 | my_getExpression (&imm_expr, s); | |
9620 | check_absolute_expr (ip, &imm_expr); | |
9621 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 9622 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e RS |
9623 | (long) imm_expr.X_add_number); |
9624 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9625 | imm_expr.X_op = O_absent; |
9626 | s = expr_end; | |
9627 | continue; | |
9628 | ||
9629 | case 'Q': /* MDMX vector, element sel, or const. */ | |
9630 | if (s[0] != '$') | |
9631 | { | |
9632 | /* MDMX Immediate. */ | |
9633 | my_getExpression (&imm_expr, s); | |
9634 | check_absolute_expr (ip, &imm_expr); | |
9635 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
9636 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
9637 | (long) imm_expr.X_add_number); | |
9638 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9639 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
9640 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
9641 | else | |
9642 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
9643 | imm_expr.X_op = O_absent; |
9644 | s = expr_end; | |
9645 | continue; | |
9646 | } | |
9647 | /* Not MDMX Immediate. Fall through. */ | |
9648 | case 'X': /* MDMX destination register. */ | |
9649 | case 'Y': /* MDMX source register. */ | |
9650 | case 'Z': /* MDMX target register. */ | |
9651 | is_mdmx = 1; | |
252b5132 RH |
9652 | case 'D': /* floating point destination register */ |
9653 | case 'S': /* floating point source register */ | |
9654 | case 'T': /* floating point target register */ | |
9655 | case 'R': /* floating point source register */ | |
9656 | case 'V': | |
9657 | case 'W': | |
707bfff6 TS |
9658 | rtype = RTYPE_FPU; |
9659 | if (is_mdmx | |
9660 | || (mips_opts.ase_mdmx | |
9661 | && (ip->insn_mo->pinfo & FP_D) | |
9662 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
9663 | | INSN_COPROC_MEMORY_DELAY | |
9664 | | INSN_LOAD_COPROC_DELAY | |
9665 | | INSN_LOAD_MEMORY_DELAY | |
9666 | | INSN_STORE_MEMORY)))) | |
9667 | rtype |= RTYPE_VEC; | |
252b5132 | 9668 | s_reset = s; |
707bfff6 | 9669 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 9670 | { |
252b5132 | 9671 | if ((regno & 1) != 0 |
ca4e0257 | 9672 | && HAVE_32BIT_FPRS |
7455baf8 | 9673 | && ! mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
9674 | as_warn (_("Float register should be even, was %d"), |
9675 | regno); | |
9676 | ||
9677 | c = *args; | |
9678 | if (*s == ' ') | |
f9419b05 | 9679 | ++s; |
252b5132 RH |
9680 | if (args[1] != *s) |
9681 | { | |
9682 | if (c == 'V' || c == 'W') | |
9683 | { | |
9684 | regno = lastregno; | |
9685 | s = s_reset; | |
f9419b05 | 9686 | ++args; |
252b5132 RH |
9687 | } |
9688 | } | |
9689 | switch (c) | |
9690 | { | |
9691 | case 'D': | |
deec1734 | 9692 | case 'X': |
bf12938e | 9693 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
9694 | break; |
9695 | case 'V': | |
9696 | case 'S': | |
deec1734 | 9697 | case 'Y': |
bf12938e | 9698 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 9699 | break; |
deec1734 CD |
9700 | case 'Q': |
9701 | /* This is like 'Z', but also needs to fix the MDMX | |
9702 | vector/scalar select bits. Note that the | |
9703 | scalar immediate case is handled above. */ | |
9704 | if (*s == '[') | |
9705 | { | |
9706 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
9707 | int max_el = (is_qh ? 3 : 7); | |
9708 | s++; | |
9709 | my_getExpression(&imm_expr, s); | |
9710 | check_absolute_expr (ip, &imm_expr); | |
9711 | s = expr_end; | |
9712 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
9713 | as_bad (_("Bad element selector %ld"), |
9714 | (long) imm_expr.X_add_number); | |
deec1734 CD |
9715 | imm_expr.X_add_number &= max_el; |
9716 | ip->insn_opcode |= (imm_expr.X_add_number | |
9717 | << (OP_SH_VSEL + | |
9718 | (is_qh ? 2 : 1))); | |
01a3f561 | 9719 | imm_expr.X_op = O_absent; |
deec1734 | 9720 | if (*s != ']') |
20203fb9 | 9721 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
9722 | else |
9723 | s++; | |
9724 | } | |
9725 | else | |
9726 | { | |
9727 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
9728 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
9729 | << OP_SH_VSEL); | |
9730 | else | |
9731 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
9732 | OP_SH_VSEL); | |
9733 | } | |
9734 | /* Fall through */ | |
252b5132 RH |
9735 | case 'W': |
9736 | case 'T': | |
deec1734 | 9737 | case 'Z': |
bf12938e | 9738 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
9739 | break; |
9740 | case 'R': | |
bf12938e | 9741 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
9742 | break; |
9743 | } | |
9744 | lastregno = regno; | |
9745 | continue; | |
9746 | } | |
9747 | ||
252b5132 RH |
9748 | switch (*args++) |
9749 | { | |
9750 | case 'V': | |
bf12938e | 9751 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9752 | continue; |
9753 | case 'W': | |
bf12938e | 9754 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9755 | continue; |
9756 | } | |
9757 | break; | |
9758 | ||
9759 | case 'I': | |
9760 | my_getExpression (&imm_expr, s); | |
9761 | if (imm_expr.X_op != O_big | |
9762 | && imm_expr.X_op != O_constant) | |
9763 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9764 | if (HAVE_32BIT_GPRS) |
9765 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
9766 | s = expr_end; |
9767 | continue; | |
9768 | ||
9769 | case 'A': | |
9770 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 9771 | normalize_address_expr (&offset_expr); |
f6688943 | 9772 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
9773 | s = expr_end; |
9774 | continue; | |
9775 | ||
9776 | case 'F': | |
9777 | case 'L': | |
9778 | case 'f': | |
9779 | case 'l': | |
9780 | { | |
9781 | int f64; | |
ca4e0257 | 9782 | int using_gprs; |
252b5132 RH |
9783 | char *save_in; |
9784 | char *err; | |
9785 | unsigned char temp[8]; | |
9786 | int len; | |
9787 | unsigned int length; | |
9788 | segT seg; | |
9789 | subsegT subseg; | |
9790 | char *p; | |
9791 | ||
9792 | /* These only appear as the last operand in an | |
9793 | instruction, and every instruction that accepts | |
9794 | them in any variant accepts them in all variants. | |
9795 | This means we don't have to worry about backing out | |
9796 | any changes if the instruction does not match. | |
9797 | ||
9798 | The difference between them is the size of the | |
9799 | floating point constant and where it goes. For 'F' | |
9800 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
9801 | is 32 bits. Where the constant is placed is based | |
9802 | on how the MIPS assembler does things: | |
9803 | F -- .rdata | |
9804 | L -- .lit8 | |
9805 | f -- immediate value | |
9806 | l -- .lit4 | |
9807 | ||
9808 | The .lit4 and .lit8 sections are only used if | |
9809 | permitted by the -G argument. | |
9810 | ||
ca4e0257 RS |
9811 | The code below needs to know whether the target register |
9812 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
9813 | 'F' are used with GPR-based instructions and 'l' and | |
9814 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
9815 | |
9816 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 9817 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
9818 | |
9819 | save_in = input_line_pointer; | |
9820 | input_line_pointer = s; | |
9821 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
9822 | length = len; | |
9823 | s = input_line_pointer; | |
9824 | input_line_pointer = save_in; | |
9825 | if (err != NULL && *err != '\0') | |
9826 | { | |
9827 | as_bad (_("Bad floating point constant: %s"), err); | |
9828 | memset (temp, '\0', sizeof temp); | |
9829 | length = f64 ? 8 : 4; | |
9830 | } | |
9831 | ||
9c2799c2 | 9832 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
9833 | |
9834 | if (*args == 'f' | |
9835 | || (*args == 'l' | |
3e722fb5 | 9836 | && (g_switch_value < 4 |
252b5132 RH |
9837 | || (temp[0] == 0 && temp[1] == 0) |
9838 | || (temp[2] == 0 && temp[3] == 0)))) | |
9839 | { | |
9840 | imm_expr.X_op = O_constant; | |
9841 | if (! target_big_endian) | |
9842 | imm_expr.X_add_number = bfd_getl32 (temp); | |
9843 | else | |
9844 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9845 | } | |
9846 | else if (length > 4 | |
119d663a | 9847 | && ! mips_disable_float_construction |
ca4e0257 RS |
9848 | /* Constants can only be constructed in GPRs and |
9849 | copied to FPRs if the GPRs are at least as wide | |
9850 | as the FPRs. Force the constant into memory if | |
9851 | we are using 64-bit FPRs but the GPRs are only | |
9852 | 32 bits wide. */ | |
9853 | && (using_gprs | |
9854 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
9855 | && ((temp[0] == 0 && temp[1] == 0) |
9856 | || (temp[2] == 0 && temp[3] == 0)) | |
9857 | && ((temp[4] == 0 && temp[5] == 0) | |
9858 | || (temp[6] == 0 && temp[7] == 0))) | |
9859 | { | |
ca4e0257 RS |
9860 | /* The value is simple enough to load with a couple of |
9861 | instructions. If using 32-bit registers, set | |
9862 | imm_expr to the high order 32 bits and offset_expr to | |
9863 | the low order 32 bits. Otherwise, set imm_expr to | |
9864 | the entire 64 bit constant. */ | |
9865 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
9866 | { |
9867 | imm_expr.X_op = O_constant; | |
9868 | offset_expr.X_op = O_constant; | |
9869 | if (! target_big_endian) | |
9870 | { | |
9871 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
9872 | offset_expr.X_add_number = bfd_getl32 (temp); | |
9873 | } | |
9874 | else | |
9875 | { | |
9876 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9877 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
9878 | } | |
9879 | if (offset_expr.X_add_number == 0) | |
9880 | offset_expr.X_op = O_absent; | |
9881 | } | |
9882 | else if (sizeof (imm_expr.X_add_number) > 4) | |
9883 | { | |
9884 | imm_expr.X_op = O_constant; | |
9885 | if (! target_big_endian) | |
9886 | imm_expr.X_add_number = bfd_getl64 (temp); | |
9887 | else | |
9888 | imm_expr.X_add_number = bfd_getb64 (temp); | |
9889 | } | |
9890 | else | |
9891 | { | |
9892 | imm_expr.X_op = O_big; | |
9893 | imm_expr.X_add_number = 4; | |
9894 | if (! target_big_endian) | |
9895 | { | |
9896 | generic_bignum[0] = bfd_getl16 (temp); | |
9897 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
9898 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
9899 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
9900 | } | |
9901 | else | |
9902 | { | |
9903 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9904 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9905 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9906 | generic_bignum[3] = bfd_getb16 (temp); | |
9907 | } | |
9908 | } | |
9909 | } | |
9910 | else | |
9911 | { | |
9912 | const char *newname; | |
9913 | segT new_seg; | |
9914 | ||
9915 | /* Switch to the right section. */ | |
9916 | seg = now_seg; | |
9917 | subseg = now_subseg; | |
9918 | switch (*args) | |
9919 | { | |
9920 | default: /* unused default case avoids warnings. */ | |
9921 | case 'L': | |
9922 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 9923 | if (g_switch_value >= 8) |
252b5132 RH |
9924 | newname = ".lit8"; |
9925 | break; | |
9926 | case 'F': | |
3e722fb5 | 9927 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
9928 | break; |
9929 | case 'l': | |
9c2799c2 | 9930 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
9931 | newname = ".lit4"; |
9932 | break; | |
9933 | } | |
9934 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 9935 | if (IS_ELF) |
252b5132 RH |
9936 | bfd_set_section_flags (stdoutput, new_seg, |
9937 | (SEC_ALLOC | |
9938 | | SEC_LOAD | |
9939 | | SEC_READONLY | |
9940 | | SEC_DATA)); | |
9941 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 9942 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
9943 | record_alignment (new_seg, 4); |
9944 | else | |
9945 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
9946 | if (seg == now_seg) | |
9947 | as_bad (_("Can't use floating point insn in this section")); | |
9948 | ||
9949 | /* Set the argument to the current address in the | |
9950 | section. */ | |
9951 | offset_expr.X_op = O_symbol; | |
9952 | offset_expr.X_add_symbol = | |
9953 | symbol_new ("L0\001", now_seg, | |
9954 | (valueT) frag_now_fix (), frag_now); | |
9955 | offset_expr.X_add_number = 0; | |
9956 | ||
9957 | /* Put the floating point number into the section. */ | |
9958 | p = frag_more ((int) length); | |
9959 | memcpy (p, temp, length); | |
9960 | ||
9961 | /* Switch back to the original section. */ | |
9962 | subseg_set (seg, subseg); | |
9963 | } | |
9964 | } | |
9965 | continue; | |
9966 | ||
9967 | case 'i': /* 16 bit unsigned immediate */ | |
9968 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 9969 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9970 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9971 | { |
9972 | int more; | |
5e0116d5 RS |
9973 | offsetT minval, maxval; |
9974 | ||
9975 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9976 | && strcmp (insn->name, insn[1].name) == 0); | |
9977 | ||
9978 | /* If the expression was written as an unsigned number, | |
9979 | only treat it as signed if there are no more | |
9980 | alternatives. */ | |
9981 | if (more | |
9982 | && *args == 'j' | |
9983 | && sizeof (imm_expr.X_add_number) <= 4 | |
9984 | && imm_expr.X_op == O_constant | |
9985 | && imm_expr.X_add_number < 0 | |
9986 | && imm_expr.X_unsigned | |
9987 | && HAVE_64BIT_GPRS) | |
9988 | break; | |
9989 | ||
9990 | /* For compatibility with older assemblers, we accept | |
9991 | 0x8000-0xffff as signed 16-bit numbers when only | |
9992 | signed numbers are allowed. */ | |
9993 | if (*args == 'i') | |
9994 | minval = 0, maxval = 0xffff; | |
9995 | else if (more) | |
9996 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9997 | else |
5e0116d5 RS |
9998 | minval = -0x8000, maxval = 0xffff; |
9999 | ||
10000 | if (imm_expr.X_op != O_constant | |
10001 | || imm_expr.X_add_number < minval | |
10002 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
10003 | { |
10004 | if (more) | |
10005 | break; | |
2ae7e77b AH |
10006 | if (imm_expr.X_op == O_constant |
10007 | || imm_expr.X_op == O_big) | |
5e0116d5 | 10008 | as_bad (_("expression out of range")); |
252b5132 RH |
10009 | } |
10010 | } | |
10011 | s = expr_end; | |
10012 | continue; | |
10013 | ||
10014 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
10015 | /* Check whether there is only a single bracketed expression |
10016 | left. If so, it must be the base register and the | |
10017 | constant must be zero. */ | |
10018 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
10019 | { | |
10020 | offset_expr.X_op = O_constant; | |
10021 | offset_expr.X_add_number = 0; | |
10022 | continue; | |
10023 | } | |
252b5132 RH |
10024 | |
10025 | /* If this value won't fit into a 16 bit offset, then go | |
10026 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 10027 | code pattern. */ |
5e0116d5 | 10028 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
10029 | && (offset_expr.X_op != O_constant |
10030 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 10031 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
10032 | break; |
10033 | ||
252b5132 RH |
10034 | s = expr_end; |
10035 | continue; | |
10036 | ||
10037 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 10038 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
10039 | my_getExpression (&offset_expr, s); |
10040 | s = expr_end; | |
10041 | continue; | |
10042 | ||
10043 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
10044 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
10045 | && imm_expr.X_op == O_constant | |
10046 | && (imm_expr.X_add_number < 0 | |
10047 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
10048 | as_bad (_("lui expression not in range 0..65535")); |
10049 | s = expr_end; | |
10050 | continue; | |
10051 | ||
10052 | case 'a': /* 26 bit address */ | |
10053 | my_getExpression (&offset_expr, s); | |
10054 | s = expr_end; | |
f6688943 | 10055 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
10056 | continue; |
10057 | ||
10058 | case 'N': /* 3 bit branch condition code */ | |
10059 | case 'M': /* 3 bit compare condition code */ | |
707bfff6 TS |
10060 | rtype = RTYPE_CCC; |
10061 | if (ip->insn_mo->pinfo & (FP_D| FP_S)) | |
10062 | rtype |= RTYPE_FCC; | |
10063 | if (!reg_lookup (&s, rtype, ®no)) | |
252b5132 | 10064 | break; |
30c378fd CD |
10065 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 |
10066 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
10067 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
10068 | && (regno & 1) != 0) | |
20203fb9 NC |
10069 | as_warn (_("Condition code register should be even for %s, was %d"), |
10070 | str, regno); | |
30c378fd CD |
10071 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 |
10072 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
10073 | && (regno & 3) != 0) | |
20203fb9 NC |
10074 | as_warn (_("Condition code register should be 0 or 4 for %s, was %d"), |
10075 | str, regno); | |
252b5132 | 10076 | if (*args == 'N') |
bf12938e | 10077 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 10078 | else |
bf12938e | 10079 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 10080 | continue; |
252b5132 | 10081 | |
156c2f8b NC |
10082 | case 'H': |
10083 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
10084 | s += 2; | |
3882b010 | 10085 | if (ISDIGIT (*s)) |
156c2f8b NC |
10086 | { |
10087 | c = 0; | |
10088 | do | |
10089 | { | |
10090 | c *= 10; | |
10091 | c += *s - '0'; | |
10092 | ++s; | |
10093 | } | |
3882b010 | 10094 | while (ISDIGIT (*s)); |
156c2f8b NC |
10095 | } |
10096 | else | |
10097 | c = 8; /* Invalid sel value. */ | |
10098 | ||
10099 | if (c > 7) | |
10100 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
10101 | ip->insn_opcode |= c; | |
10102 | continue; | |
10103 | ||
60b63b72 RS |
10104 | case 'e': |
10105 | /* Must be at least one digit. */ | |
10106 | my_getExpression (&imm_expr, s); | |
10107 | check_absolute_expr (ip, &imm_expr); | |
10108 | ||
10109 | if ((unsigned long) imm_expr.X_add_number | |
10110 | > (unsigned long) OP_MASK_VECBYTE) | |
10111 | { | |
10112 | as_bad (_("bad byte vector index (%ld)"), | |
10113 | (long) imm_expr.X_add_number); | |
10114 | imm_expr.X_add_number = 0; | |
10115 | } | |
10116 | ||
bf12938e | 10117 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
10118 | imm_expr.X_op = O_absent; |
10119 | s = expr_end; | |
10120 | continue; | |
10121 | ||
10122 | case '%': | |
10123 | my_getExpression (&imm_expr, s); | |
10124 | check_absolute_expr (ip, &imm_expr); | |
10125 | ||
10126 | if ((unsigned long) imm_expr.X_add_number | |
10127 | > (unsigned long) OP_MASK_VECALIGN) | |
10128 | { | |
10129 | as_bad (_("bad byte vector index (%ld)"), | |
10130 | (long) imm_expr.X_add_number); | |
10131 | imm_expr.X_add_number = 0; | |
10132 | } | |
10133 | ||
bf12938e | 10134 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
10135 | imm_expr.X_op = O_absent; |
10136 | s = expr_end; | |
10137 | continue; | |
10138 | ||
252b5132 RH |
10139 | default: |
10140 | as_bad (_("bad char = '%c'\n"), *args); | |
10141 | internalError (); | |
10142 | } | |
10143 | break; | |
10144 | } | |
10145 | /* Args don't match. */ | |
10146 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
10147 | !strcmp (insn->name, insn[1].name)) | |
10148 | { | |
10149 | ++insn; | |
10150 | s = argsStart; | |
268f6bed | 10151 | insn_error = _("illegal operands"); |
252b5132 RH |
10152 | continue; |
10153 | } | |
268f6bed | 10154 | if (save_c) |
570de991 | 10155 | *(--argsStart) = save_c; |
252b5132 RH |
10156 | insn_error = _("illegal operands"); |
10157 | return; | |
10158 | } | |
10159 | } | |
10160 | ||
0499d65b TS |
10161 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
10162 | ||
252b5132 RH |
10163 | /* This routine assembles an instruction into its binary format when |
10164 | assembling for the mips16. As a side effect, it sets one of the | |
10165 | global variables imm_reloc or offset_reloc to the type of | |
10166 | relocation to do if one of the operands is an address expression. | |
10167 | It also sets mips16_small and mips16_ext if the user explicitly | |
10168 | requested a small or extended instruction. */ | |
10169 | ||
10170 | static void | |
17a2f251 | 10171 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
10172 | { |
10173 | char *s; | |
10174 | const char *args; | |
10175 | struct mips_opcode *insn; | |
10176 | char *argsstart; | |
10177 | unsigned int regno; | |
10178 | unsigned int lastregno = 0; | |
10179 | char *s_reset; | |
d6f16593 | 10180 | size_t i; |
252b5132 RH |
10181 | |
10182 | insn_error = NULL; | |
10183 | ||
b34976b6 AM |
10184 | mips16_small = FALSE; |
10185 | mips16_ext = FALSE; | |
252b5132 | 10186 | |
3882b010 | 10187 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
10188 | ; |
10189 | switch (*s) | |
10190 | { | |
10191 | case '\0': | |
10192 | break; | |
10193 | ||
10194 | case ' ': | |
10195 | *s++ = '\0'; | |
10196 | break; | |
10197 | ||
10198 | case '.': | |
10199 | if (s[1] == 't' && s[2] == ' ') | |
10200 | { | |
10201 | *s = '\0'; | |
b34976b6 | 10202 | mips16_small = TRUE; |
252b5132 RH |
10203 | s += 3; |
10204 | break; | |
10205 | } | |
10206 | else if (s[1] == 'e' && s[2] == ' ') | |
10207 | { | |
10208 | *s = '\0'; | |
b34976b6 | 10209 | mips16_ext = TRUE; |
252b5132 RH |
10210 | s += 3; |
10211 | break; | |
10212 | } | |
10213 | /* Fall through. */ | |
10214 | default: | |
10215 | insn_error = _("unknown opcode"); | |
10216 | return; | |
10217 | } | |
10218 | ||
10219 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 10220 | mips16_small = TRUE; |
252b5132 RH |
10221 | |
10222 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
10223 | { | |
10224 | insn_error = _("unrecognized opcode"); | |
10225 | return; | |
10226 | } | |
10227 | ||
10228 | argsstart = s; | |
10229 | for (;;) | |
10230 | { | |
9b3f89ee TS |
10231 | bfd_boolean ok; |
10232 | ||
9c2799c2 | 10233 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 10234 | |
037b32b9 | 10235 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
10236 | if (! ok) |
10237 | { | |
10238 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
10239 | && strcmp (insn->name, insn[1].name) == 0) | |
10240 | { | |
10241 | ++insn; | |
10242 | continue; | |
10243 | } | |
10244 | else | |
10245 | { | |
10246 | if (!insn_error) | |
10247 | { | |
10248 | static char buf[100]; | |
10249 | sprintf (buf, | |
10250 | _("opcode not supported on this processor: %s (%s)"), | |
10251 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
10252 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
10253 | insn_error = buf; | |
10254 | } | |
10255 | return; | |
10256 | } | |
10257 | } | |
10258 | ||
1e915849 | 10259 | create_insn (ip, insn); |
252b5132 | 10260 | imm_expr.X_op = O_absent; |
f6688943 TS |
10261 | imm_reloc[0] = BFD_RELOC_UNUSED; |
10262 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
10263 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 10264 | imm2_expr.X_op = O_absent; |
252b5132 | 10265 | offset_expr.X_op = O_absent; |
f6688943 TS |
10266 | offset_reloc[0] = BFD_RELOC_UNUSED; |
10267 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
10268 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
10269 | for (args = insn->args; 1; ++args) |
10270 | { | |
10271 | int c; | |
10272 | ||
10273 | if (*s == ' ') | |
10274 | ++s; | |
10275 | ||
10276 | /* In this switch statement we call break if we did not find | |
10277 | a match, continue if we did find a match, or return if we | |
10278 | are done. */ | |
10279 | ||
10280 | c = *args; | |
10281 | switch (c) | |
10282 | { | |
10283 | case '\0': | |
10284 | if (*s == '\0') | |
10285 | { | |
10286 | /* Stuff the immediate value in now, if we can. */ | |
10287 | if (imm_expr.X_op == O_constant | |
f6688943 | 10288 | && *imm_reloc > BFD_RELOC_UNUSED |
738e5348 RS |
10289 | && *imm_reloc != BFD_RELOC_MIPS16_GOT16 |
10290 | && *imm_reloc != BFD_RELOC_MIPS16_CALL16 | |
252b5132 RH |
10291 | && insn->pinfo != INSN_MACRO) |
10292 | { | |
d6f16593 MR |
10293 | valueT tmp; |
10294 | ||
10295 | switch (*offset_reloc) | |
10296 | { | |
10297 | case BFD_RELOC_MIPS16_HI16_S: | |
10298 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
10299 | break; | |
10300 | ||
10301 | case BFD_RELOC_MIPS16_HI16: | |
10302 | tmp = imm_expr.X_add_number >> 16; | |
10303 | break; | |
10304 | ||
10305 | case BFD_RELOC_MIPS16_LO16: | |
10306 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
10307 | - 0x8000; | |
10308 | break; | |
10309 | ||
10310 | case BFD_RELOC_UNUSED: | |
10311 | tmp = imm_expr.X_add_number; | |
10312 | break; | |
10313 | ||
10314 | default: | |
10315 | internalError (); | |
10316 | } | |
10317 | *offset_reloc = BFD_RELOC_UNUSED; | |
10318 | ||
c4e7957c | 10319 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 10320 | tmp, TRUE, mips16_small, |
252b5132 RH |
10321 | mips16_ext, &ip->insn_opcode, |
10322 | &ip->use_extend, &ip->extend); | |
10323 | imm_expr.X_op = O_absent; | |
f6688943 | 10324 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
10325 | } |
10326 | ||
10327 | return; | |
10328 | } | |
10329 | break; | |
10330 | ||
10331 | case ',': | |
10332 | if (*s++ == c) | |
10333 | continue; | |
10334 | s--; | |
10335 | switch (*++args) | |
10336 | { | |
10337 | case 'v': | |
bf12938e | 10338 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
10339 | continue; |
10340 | case 'w': | |
bf12938e | 10341 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
10342 | continue; |
10343 | } | |
10344 | break; | |
10345 | ||
10346 | case '(': | |
10347 | case ')': | |
10348 | if (*s++ == c) | |
10349 | continue; | |
10350 | break; | |
10351 | ||
10352 | case 'v': | |
10353 | case 'w': | |
10354 | if (s[0] != '$') | |
10355 | { | |
10356 | if (c == 'v') | |
bf12938e | 10357 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 10358 | else |
bf12938e | 10359 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
10360 | ++args; |
10361 | continue; | |
10362 | } | |
10363 | /* Fall through. */ | |
10364 | case 'x': | |
10365 | case 'y': | |
10366 | case 'z': | |
10367 | case 'Z': | |
10368 | case '0': | |
10369 | case 'S': | |
10370 | case 'R': | |
10371 | case 'X': | |
10372 | case 'Y': | |
707bfff6 TS |
10373 | s_reset = s; |
10374 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 10375 | { |
707bfff6 | 10376 | if (c == 'v' || c == 'w') |
85b51719 | 10377 | { |
707bfff6 | 10378 | if (c == 'v') |
a9e24354 | 10379 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 10380 | else |
a9e24354 | 10381 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
10382 | ++args; |
10383 | continue; | |
85b51719 | 10384 | } |
707bfff6 | 10385 | break; |
252b5132 RH |
10386 | } |
10387 | ||
10388 | if (*s == ' ') | |
10389 | ++s; | |
10390 | if (args[1] != *s) | |
10391 | { | |
10392 | if (c == 'v' || c == 'w') | |
10393 | { | |
10394 | regno = mips16_to_32_reg_map[lastregno]; | |
10395 | s = s_reset; | |
f9419b05 | 10396 | ++args; |
252b5132 RH |
10397 | } |
10398 | } | |
10399 | ||
10400 | switch (c) | |
10401 | { | |
10402 | case 'x': | |
10403 | case 'y': | |
10404 | case 'z': | |
10405 | case 'v': | |
10406 | case 'w': | |
10407 | case 'Z': | |
10408 | regno = mips32_to_16_reg_map[regno]; | |
10409 | break; | |
10410 | ||
10411 | case '0': | |
10412 | if (regno != 0) | |
10413 | regno = ILLEGAL_REG; | |
10414 | break; | |
10415 | ||
10416 | case 'S': | |
10417 | if (regno != SP) | |
10418 | regno = ILLEGAL_REG; | |
10419 | break; | |
10420 | ||
10421 | case 'R': | |
10422 | if (regno != RA) | |
10423 | regno = ILLEGAL_REG; | |
10424 | break; | |
10425 | ||
10426 | case 'X': | |
10427 | case 'Y': | |
741fe287 MR |
10428 | if (regno == AT && mips_opts.at) |
10429 | { | |
10430 | if (mips_opts.at == ATREG) | |
10431 | as_warn (_("used $at without \".set noat\"")); | |
10432 | else | |
10433 | as_warn (_("used $%u with \".set at=$%u\""), | |
10434 | regno, mips_opts.at); | |
10435 | } | |
252b5132 RH |
10436 | break; |
10437 | ||
10438 | default: | |
10439 | internalError (); | |
10440 | } | |
10441 | ||
10442 | if (regno == ILLEGAL_REG) | |
10443 | break; | |
10444 | ||
10445 | switch (c) | |
10446 | { | |
10447 | case 'x': | |
10448 | case 'v': | |
bf12938e | 10449 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
10450 | break; |
10451 | case 'y': | |
10452 | case 'w': | |
bf12938e | 10453 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
10454 | break; |
10455 | case 'z': | |
bf12938e | 10456 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
10457 | break; |
10458 | case 'Z': | |
bf12938e | 10459 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
10460 | case '0': |
10461 | case 'S': | |
10462 | case 'R': | |
10463 | break; | |
10464 | case 'X': | |
bf12938e | 10465 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
10466 | break; |
10467 | case 'Y': | |
10468 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 10469 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
10470 | break; |
10471 | default: | |
10472 | internalError (); | |
10473 | } | |
10474 | ||
10475 | lastregno = regno; | |
10476 | continue; | |
10477 | ||
10478 | case 'P': | |
10479 | if (strncmp (s, "$pc", 3) == 0) | |
10480 | { | |
10481 | s += 3; | |
10482 | continue; | |
10483 | } | |
10484 | break; | |
10485 | ||
252b5132 RH |
10486 | case '5': |
10487 | case 'H': | |
10488 | case 'W': | |
10489 | case 'D': | |
10490 | case 'j': | |
252b5132 RH |
10491 | case 'V': |
10492 | case 'C': | |
10493 | case 'U': | |
10494 | case 'k': | |
10495 | case 'K': | |
d6f16593 MR |
10496 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
10497 | if (i > 0) | |
252b5132 | 10498 | { |
d6f16593 | 10499 | if (imm_expr.X_op != O_constant) |
252b5132 | 10500 | { |
b34976b6 | 10501 | mips16_ext = TRUE; |
b34976b6 | 10502 | ip->use_extend = TRUE; |
252b5132 | 10503 | ip->extend = 0; |
252b5132 | 10504 | } |
d6f16593 MR |
10505 | else |
10506 | { | |
10507 | /* We need to relax this instruction. */ | |
10508 | *offset_reloc = *imm_reloc; | |
10509 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
10510 | } | |
10511 | s = expr_end; | |
10512 | continue; | |
252b5132 | 10513 | } |
d6f16593 MR |
10514 | *imm_reloc = BFD_RELOC_UNUSED; |
10515 | /* Fall through. */ | |
10516 | case '<': | |
10517 | case '>': | |
10518 | case '[': | |
10519 | case ']': | |
10520 | case '4': | |
10521 | case '8': | |
10522 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
10523 | if (imm_expr.X_op == O_register) |
10524 | { | |
10525 | /* What we thought was an expression turned out to | |
10526 | be a register. */ | |
10527 | ||
10528 | if (s[0] == '(' && args[1] == '(') | |
10529 | { | |
10530 | /* It looks like the expression was omitted | |
10531 | before a register indirection, which means | |
10532 | that the expression is implicitly zero. We | |
10533 | still set up imm_expr, so that we handle | |
10534 | explicit extensions correctly. */ | |
10535 | imm_expr.X_op = O_constant; | |
10536 | imm_expr.X_add_number = 0; | |
f6688943 | 10537 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10538 | continue; |
10539 | } | |
10540 | ||
10541 | break; | |
10542 | } | |
10543 | ||
10544 | /* We need to relax this instruction. */ | |
f6688943 | 10545 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10546 | s = expr_end; |
10547 | continue; | |
10548 | ||
10549 | case 'p': | |
10550 | case 'q': | |
10551 | case 'A': | |
10552 | case 'B': | |
10553 | case 'E': | |
10554 | /* We use offset_reloc rather than imm_reloc for the PC | |
10555 | relative operands. This lets macros with both | |
10556 | immediate and address operands work correctly. */ | |
10557 | my_getExpression (&offset_expr, s); | |
10558 | ||
10559 | if (offset_expr.X_op == O_register) | |
10560 | break; | |
10561 | ||
10562 | /* We need to relax this instruction. */ | |
f6688943 | 10563 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10564 | s = expr_end; |
10565 | continue; | |
10566 | ||
10567 | case '6': /* break code */ | |
10568 | my_getExpression (&imm_expr, s); | |
10569 | check_absolute_expr (ip, &imm_expr); | |
10570 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
10571 | as_warn (_("Invalid value for `%s' (%lu)"), |
10572 | ip->insn_mo->name, | |
10573 | (unsigned long) imm_expr.X_add_number); | |
10574 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
10575 | imm_expr.X_op = O_absent; |
10576 | s = expr_end; | |
10577 | continue; | |
10578 | ||
10579 | case 'a': /* 26 bit address */ | |
10580 | my_getExpression (&offset_expr, s); | |
10581 | s = expr_end; | |
f6688943 | 10582 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
10583 | ip->insn_opcode <<= 16; |
10584 | continue; | |
10585 | ||
10586 | case 'l': /* register list for entry macro */ | |
10587 | case 'L': /* register list for exit macro */ | |
10588 | { | |
10589 | int mask; | |
10590 | ||
10591 | if (c == 'l') | |
10592 | mask = 0; | |
10593 | else | |
10594 | mask = 7 << 3; | |
10595 | while (*s != '\0') | |
10596 | { | |
707bfff6 | 10597 | unsigned int freg, reg1, reg2; |
252b5132 RH |
10598 | |
10599 | while (*s == ' ' || *s == ',') | |
10600 | ++s; | |
707bfff6 | 10601 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 10602 | freg = 0; |
707bfff6 TS |
10603 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
10604 | freg = 1; | |
252b5132 RH |
10605 | else |
10606 | { | |
707bfff6 TS |
10607 | as_bad (_("can't parse register list")); |
10608 | break; | |
252b5132 RH |
10609 | } |
10610 | if (*s == ' ') | |
10611 | ++s; | |
10612 | if (*s != '-') | |
10613 | reg2 = reg1; | |
10614 | else | |
10615 | { | |
10616 | ++s; | |
707bfff6 TS |
10617 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
10618 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 10619 | { |
707bfff6 TS |
10620 | as_bad (_("invalid register list")); |
10621 | break; | |
252b5132 RH |
10622 | } |
10623 | } | |
10624 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
10625 | { | |
10626 | mask &= ~ (7 << 3); | |
10627 | mask |= 5 << 3; | |
10628 | } | |
10629 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
10630 | { | |
10631 | mask &= ~ (7 << 3); | |
10632 | mask |= 6 << 3; | |
10633 | } | |
10634 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
10635 | mask |= (reg2 - 3) << 3; | |
10636 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
10637 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 10638 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
10639 | mask |= 1; |
10640 | else | |
10641 | { | |
10642 | as_bad (_("invalid register list")); | |
10643 | break; | |
10644 | } | |
10645 | } | |
10646 | /* The mask is filled in in the opcode table for the | |
10647 | benefit of the disassembler. We remove it before | |
10648 | applying the actual mask. */ | |
10649 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
10650 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
10651 | } | |
10652 | continue; | |
10653 | ||
0499d65b TS |
10654 | case 'm': /* Register list for save insn. */ |
10655 | case 'M': /* Register list for restore insn. */ | |
10656 | { | |
10657 | int opcode = 0; | |
10658 | int framesz = 0, seen_framesz = 0; | |
91d6fa6a | 10659 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
10660 | |
10661 | while (*s != '\0') | |
10662 | { | |
10663 | unsigned int reg1, reg2; | |
10664 | ||
10665 | SKIP_SPACE_TABS (s); | |
10666 | while (*s == ',') | |
10667 | ++s; | |
10668 | SKIP_SPACE_TABS (s); | |
10669 | ||
10670 | my_getExpression (&imm_expr, s); | |
10671 | if (imm_expr.X_op == O_constant) | |
10672 | { | |
10673 | /* Handle the frame size. */ | |
10674 | if (seen_framesz) | |
10675 | { | |
10676 | as_bad (_("more than one frame size in list")); | |
10677 | break; | |
10678 | } | |
10679 | seen_framesz = 1; | |
10680 | framesz = imm_expr.X_add_number; | |
10681 | imm_expr.X_op = O_absent; | |
10682 | s = expr_end; | |
10683 | continue; | |
10684 | } | |
10685 | ||
707bfff6 | 10686 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
10687 | { |
10688 | as_bad (_("can't parse register list")); | |
10689 | break; | |
10690 | } | |
0499d65b | 10691 | |
707bfff6 TS |
10692 | while (*s == ' ') |
10693 | ++s; | |
10694 | ||
0499d65b TS |
10695 | if (*s != '-') |
10696 | reg2 = reg1; | |
10697 | else | |
10698 | { | |
10699 | ++s; | |
707bfff6 TS |
10700 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
10701 | || reg2 < reg1) | |
0499d65b TS |
10702 | { |
10703 | as_bad (_("can't parse register list")); | |
10704 | break; | |
10705 | } | |
0499d65b TS |
10706 | } |
10707 | ||
10708 | while (reg1 <= reg2) | |
10709 | { | |
10710 | if (reg1 >= 4 && reg1 <= 7) | |
10711 | { | |
3a93f742 | 10712 | if (!seen_framesz) |
0499d65b | 10713 | /* args $a0-$a3 */ |
91d6fa6a | 10714 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
10715 | else |
10716 | /* statics $a0-$a3 */ | |
10717 | statics |= 1 << (reg1 - 4); | |
10718 | } | |
10719 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
10720 | { | |
10721 | /* $s0-$s8 */ | |
10722 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
10723 | } | |
10724 | else if (reg1 == 31) | |
10725 | { | |
10726 | /* Add $ra to insn. */ | |
10727 | opcode |= 0x40; | |
10728 | } | |
10729 | else | |
10730 | { | |
10731 | as_bad (_("unexpected register in list")); | |
10732 | break; | |
10733 | } | |
10734 | if (++reg1 == 24) | |
10735 | reg1 = 30; | |
10736 | } | |
10737 | } | |
10738 | ||
10739 | /* Encode args/statics combination. */ | |
91d6fa6a | 10740 | if (nargs & statics) |
0499d65b | 10741 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 10742 | else if (nargs == 0xf) |
0499d65b TS |
10743 | /* All $a0-$a3 are args. */ |
10744 | opcode |= MIPS16_ALL_ARGS << 16; | |
10745 | else if (statics == 0xf) | |
10746 | /* All $a0-$a3 are statics. */ | |
10747 | opcode |= MIPS16_ALL_STATICS << 16; | |
10748 | else | |
10749 | { | |
10750 | int narg = 0, nstat = 0; | |
10751 | ||
10752 | /* Count arg registers. */ | |
91d6fa6a | 10753 | while (nargs & 0x1) |
0499d65b | 10754 | { |
91d6fa6a | 10755 | nargs >>= 1; |
0499d65b TS |
10756 | narg++; |
10757 | } | |
91d6fa6a | 10758 | if (nargs != 0) |
0499d65b TS |
10759 | as_bad (_("invalid arg register list")); |
10760 | ||
10761 | /* Count static registers. */ | |
10762 | while (statics & 0x8) | |
10763 | { | |
10764 | statics = (statics << 1) & 0xf; | |
10765 | nstat++; | |
10766 | } | |
10767 | if (statics != 0) | |
10768 | as_bad (_("invalid static register list")); | |
10769 | ||
10770 | /* Encode args/statics. */ | |
10771 | opcode |= ((narg << 2) | nstat) << 16; | |
10772 | } | |
10773 | ||
10774 | /* Encode $s0/$s1. */ | |
10775 | if (sregs & (1 << 0)) /* $s0 */ | |
10776 | opcode |= 0x20; | |
10777 | if (sregs & (1 << 1)) /* $s1 */ | |
10778 | opcode |= 0x10; | |
10779 | sregs >>= 2; | |
10780 | ||
10781 | if (sregs != 0) | |
10782 | { | |
10783 | /* Count regs $s2-$s8. */ | |
10784 | int nsreg = 0; | |
10785 | while (sregs & 1) | |
10786 | { | |
10787 | sregs >>= 1; | |
10788 | nsreg++; | |
10789 | } | |
10790 | if (sregs != 0) | |
10791 | as_bad (_("invalid static register list")); | |
10792 | /* Encode $s2-$s8. */ | |
10793 | opcode |= nsreg << 24; | |
10794 | } | |
10795 | ||
10796 | /* Encode frame size. */ | |
10797 | if (!seen_framesz) | |
10798 | as_bad (_("missing frame size")); | |
10799 | else if ((framesz & 7) != 0 || framesz < 0 | |
10800 | || framesz > 0xff * 8) | |
10801 | as_bad (_("invalid frame size")); | |
10802 | else if (framesz != 128 || (opcode >> 16) != 0) | |
10803 | { | |
10804 | framesz /= 8; | |
10805 | opcode |= (((framesz & 0xf0) << 16) | |
10806 | | (framesz & 0x0f)); | |
10807 | } | |
10808 | ||
10809 | /* Finally build the instruction. */ | |
10810 | if ((opcode >> 16) != 0 || framesz == 0) | |
10811 | { | |
10812 | ip->use_extend = TRUE; | |
10813 | ip->extend = opcode >> 16; | |
10814 | } | |
10815 | ip->insn_opcode |= opcode & 0x7f; | |
10816 | } | |
10817 | continue; | |
10818 | ||
252b5132 RH |
10819 | case 'e': /* extend code */ |
10820 | my_getExpression (&imm_expr, s); | |
10821 | check_absolute_expr (ip, &imm_expr); | |
10822 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
10823 | { | |
10824 | as_warn (_("Invalid value for `%s' (%lu)"), | |
10825 | ip->insn_mo->name, | |
10826 | (unsigned long) imm_expr.X_add_number); | |
10827 | imm_expr.X_add_number &= 0x7ff; | |
10828 | } | |
10829 | ip->insn_opcode |= imm_expr.X_add_number; | |
10830 | imm_expr.X_op = O_absent; | |
10831 | s = expr_end; | |
10832 | continue; | |
10833 | ||
10834 | default: | |
10835 | internalError (); | |
10836 | } | |
10837 | break; | |
10838 | } | |
10839 | ||
10840 | /* Args don't match. */ | |
10841 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
10842 | strcmp (insn->name, insn[1].name) == 0) | |
10843 | { | |
10844 | ++insn; | |
10845 | s = argsstart; | |
10846 | continue; | |
10847 | } | |
10848 | ||
10849 | insn_error = _("illegal operands"); | |
10850 | ||
10851 | return; | |
10852 | } | |
10853 | } | |
10854 | ||
10855 | /* This structure holds information we know about a mips16 immediate | |
10856 | argument type. */ | |
10857 | ||
e972090a NC |
10858 | struct mips16_immed_operand |
10859 | { | |
252b5132 RH |
10860 | /* The type code used in the argument string in the opcode table. */ |
10861 | int type; | |
10862 | /* The number of bits in the short form of the opcode. */ | |
10863 | int nbits; | |
10864 | /* The number of bits in the extended form of the opcode. */ | |
10865 | int extbits; | |
10866 | /* The amount by which the short form is shifted when it is used; | |
10867 | for example, the sw instruction has a shift count of 2. */ | |
10868 | int shift; | |
10869 | /* The amount by which the short form is shifted when it is stored | |
10870 | into the instruction code. */ | |
10871 | int op_shift; | |
10872 | /* Non-zero if the short form is unsigned. */ | |
10873 | int unsp; | |
10874 | /* Non-zero if the extended form is unsigned. */ | |
10875 | int extu; | |
10876 | /* Non-zero if the value is PC relative. */ | |
10877 | int pcrel; | |
10878 | }; | |
10879 | ||
10880 | /* The mips16 immediate operand types. */ | |
10881 | ||
10882 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
10883 | { | |
10884 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10885 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10886 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10887 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10888 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
10889 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10890 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10891 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10892 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10893 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
10894 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10895 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10896 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10897 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
10898 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10899 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10900 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10901 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10902 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
10903 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
10904 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
10905 | }; | |
10906 | ||
10907 | #define MIPS16_NUM_IMMED \ | |
10908 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
10909 | ||
10910 | /* Handle a mips16 instruction with an immediate value. This or's the | |
10911 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
10912 | whether an extended value is needed; if one is needed, it sets | |
10913 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
10914 | If SMALL is true, an unextended opcode was explicitly requested. | |
10915 | If EXT is true, an extended opcode was explicitly requested. If | |
10916 | WARN is true, warn if EXT does not match reality. */ | |
10917 | ||
10918 | static void | |
17a2f251 TS |
10919 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
10920 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
10921 | unsigned long *insn, bfd_boolean *use_extend, | |
10922 | unsigned short *extend) | |
252b5132 | 10923 | { |
3994f87e | 10924 | const struct mips16_immed_operand *op; |
252b5132 | 10925 | int mintiny, maxtiny; |
b34976b6 | 10926 | bfd_boolean needext; |
252b5132 RH |
10927 | |
10928 | op = mips16_immed_operands; | |
10929 | while (op->type != type) | |
10930 | { | |
10931 | ++op; | |
9c2799c2 | 10932 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
10933 | } |
10934 | ||
10935 | if (op->unsp) | |
10936 | { | |
10937 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10938 | { | |
10939 | mintiny = 1; | |
10940 | maxtiny = 1 << op->nbits; | |
10941 | } | |
10942 | else | |
10943 | { | |
10944 | mintiny = 0; | |
10945 | maxtiny = (1 << op->nbits) - 1; | |
10946 | } | |
10947 | } | |
10948 | else | |
10949 | { | |
10950 | mintiny = - (1 << (op->nbits - 1)); | |
10951 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10952 | } | |
10953 | ||
10954 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10955 | if (type == 'p' || type == 'q') | |
10956 | val /= 2; | |
10957 | ||
10958 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10959 | || val < (mintiny << op->shift) | |
10960 | || val > (maxtiny << op->shift)) | |
b34976b6 | 10961 | needext = TRUE; |
252b5132 | 10962 | else |
b34976b6 | 10963 | needext = FALSE; |
252b5132 RH |
10964 | |
10965 | if (warn && ext && ! needext) | |
beae10d5 KH |
10966 | as_warn_where (file, line, |
10967 | _("extended operand requested but not required")); | |
252b5132 RH |
10968 | if (small && needext) |
10969 | as_bad_where (file, line, _("invalid unextended operand value")); | |
10970 | ||
10971 | if (small || (! ext && ! needext)) | |
10972 | { | |
10973 | int insnval; | |
10974 | ||
b34976b6 | 10975 | *use_extend = FALSE; |
252b5132 RH |
10976 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
10977 | insnval <<= op->op_shift; | |
10978 | *insn |= insnval; | |
10979 | } | |
10980 | else | |
10981 | { | |
10982 | long minext, maxext; | |
10983 | int extval; | |
10984 | ||
10985 | if (op->extu) | |
10986 | { | |
10987 | minext = 0; | |
10988 | maxext = (1 << op->extbits) - 1; | |
10989 | } | |
10990 | else | |
10991 | { | |
10992 | minext = - (1 << (op->extbits - 1)); | |
10993 | maxext = (1 << (op->extbits - 1)) - 1; | |
10994 | } | |
10995 | if (val < minext || val > maxext) | |
10996 | as_bad_where (file, line, | |
10997 | _("operand value out of range for instruction")); | |
10998 | ||
b34976b6 | 10999 | *use_extend = TRUE; |
252b5132 RH |
11000 | if (op->extbits == 16) |
11001 | { | |
11002 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
11003 | val &= 0x1f; | |
11004 | } | |
11005 | else if (op->extbits == 15) | |
11006 | { | |
11007 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
11008 | val &= 0xf; | |
11009 | } | |
11010 | else | |
11011 | { | |
11012 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
11013 | val = 0; | |
11014 | } | |
11015 | ||
11016 | *extend = (unsigned short) extval; | |
11017 | *insn |= val; | |
11018 | } | |
11019 | } | |
11020 | \f | |
d6f16593 | 11021 | struct percent_op_match |
ad8d3bb3 | 11022 | { |
5e0116d5 RS |
11023 | const char *str; |
11024 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
11025 | }; |
11026 | ||
11027 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 11028 | { |
5e0116d5 | 11029 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 11030 | #ifdef OBJ_ELF |
5e0116d5 RS |
11031 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
11032 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
11033 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
11034 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
11035 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
11036 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
11037 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
11038 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
11039 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
11040 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
11041 | {"%half", BFD_RELOC_16}, | |
11042 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
11043 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
11044 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
11045 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
11046 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
11047 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
11048 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
11049 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
11050 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
11051 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 11052 | #endif |
5e0116d5 | 11053 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
11054 | }; |
11055 | ||
d6f16593 MR |
11056 | static const struct percent_op_match mips16_percent_op[] = |
11057 | { | |
11058 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
11059 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
11060 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
11061 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d6f16593 MR |
11062 | {"%hi", BFD_RELOC_MIPS16_HI16_S} |
11063 | }; | |
11064 | ||
252b5132 | 11065 | |
5e0116d5 RS |
11066 | /* Return true if *STR points to a relocation operator. When returning true, |
11067 | move *STR over the operator and store its relocation code in *RELOC. | |
11068 | Leave both *STR and *RELOC alone when returning false. */ | |
11069 | ||
11070 | static bfd_boolean | |
17a2f251 | 11071 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 11072 | { |
d6f16593 MR |
11073 | const struct percent_op_match *percent_op; |
11074 | size_t limit, i; | |
11075 | ||
11076 | if (mips_opts.mips16) | |
11077 | { | |
11078 | percent_op = mips16_percent_op; | |
11079 | limit = ARRAY_SIZE (mips16_percent_op); | |
11080 | } | |
11081 | else | |
11082 | { | |
11083 | percent_op = mips_percent_op; | |
11084 | limit = ARRAY_SIZE (mips_percent_op); | |
11085 | } | |
76b3015f | 11086 | |
d6f16593 | 11087 | for (i = 0; i < limit; i++) |
5e0116d5 | 11088 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 11089 | { |
3f98094e DJ |
11090 | int len = strlen (percent_op[i].str); |
11091 | ||
11092 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
11093 | continue; | |
11094 | ||
5e0116d5 RS |
11095 | *str += strlen (percent_op[i].str); |
11096 | *reloc = percent_op[i].reloc; | |
394f9b3a | 11097 | |
5e0116d5 RS |
11098 | /* Check whether the output BFD supports this relocation. |
11099 | If not, issue an error and fall back on something safe. */ | |
11100 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 11101 | { |
20203fb9 | 11102 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 11103 | percent_op[i].str); |
01a3f561 | 11104 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 11105 | } |
5e0116d5 | 11106 | return TRUE; |
394f9b3a | 11107 | } |
5e0116d5 | 11108 | return FALSE; |
394f9b3a | 11109 | } |
ad8d3bb3 | 11110 | |
ad8d3bb3 | 11111 | |
5e0116d5 RS |
11112 | /* Parse string STR as a 16-bit relocatable operand. Store the |
11113 | expression in *EP and the relocations in the array starting | |
11114 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 11115 | |
01a3f561 | 11116 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 11117 | |
5e0116d5 | 11118 | static size_t |
17a2f251 TS |
11119 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
11120 | char *str) | |
ad8d3bb3 | 11121 | { |
5e0116d5 RS |
11122 | bfd_reloc_code_real_type reversed_reloc[3]; |
11123 | size_t reloc_index, i; | |
09b8f35a RS |
11124 | int crux_depth, str_depth; |
11125 | char *crux; | |
5e0116d5 RS |
11126 | |
11127 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
11128 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
11129 | of the main expression and with CRUX_DEPTH containing the number | |
11130 | of open brackets at that point. */ | |
11131 | reloc_index = -1; | |
11132 | str_depth = 0; | |
11133 | do | |
fb1b3232 | 11134 | { |
09b8f35a RS |
11135 | reloc_index++; |
11136 | crux = str; | |
11137 | crux_depth = str_depth; | |
11138 | ||
11139 | /* Skip over whitespace and brackets, keeping count of the number | |
11140 | of brackets. */ | |
11141 | while (*str == ' ' || *str == '\t' || *str == '(') | |
11142 | if (*str++ == '(') | |
11143 | str_depth++; | |
5e0116d5 | 11144 | } |
09b8f35a RS |
11145 | while (*str == '%' |
11146 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
11147 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 11148 | |
09b8f35a | 11149 | my_getExpression (ep, crux); |
5e0116d5 | 11150 | str = expr_end; |
394f9b3a | 11151 | |
5e0116d5 | 11152 | /* Match every open bracket. */ |
09b8f35a | 11153 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 11154 | if (*str++ == ')') |
09b8f35a | 11155 | crux_depth--; |
394f9b3a | 11156 | |
09b8f35a | 11157 | if (crux_depth > 0) |
20203fb9 | 11158 | as_bad (_("unclosed '('")); |
394f9b3a | 11159 | |
5e0116d5 | 11160 | expr_end = str; |
252b5132 | 11161 | |
01a3f561 | 11162 | if (reloc_index != 0) |
64bdfcaf RS |
11163 | { |
11164 | prev_reloc_op_frag = frag_now; | |
11165 | for (i = 0; i < reloc_index; i++) | |
11166 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
11167 | } | |
fb1b3232 | 11168 | |
5e0116d5 | 11169 | return reloc_index; |
252b5132 RH |
11170 | } |
11171 | ||
11172 | static void | |
17a2f251 | 11173 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
11174 | { |
11175 | char *save_in; | |
98aa84af | 11176 | valueT val; |
252b5132 RH |
11177 | |
11178 | save_in = input_line_pointer; | |
11179 | input_line_pointer = str; | |
11180 | expression (ep); | |
11181 | expr_end = input_line_pointer; | |
11182 | input_line_pointer = save_in; | |
11183 | ||
11184 | /* If we are in mips16 mode, and this is an expression based on `.', | |
11185 | then we bump the value of the symbol by 1 since that is how other | |
11186 | text symbols are handled. We don't bother to handle complex | |
11187 | expressions, just `.' plus or minus a constant. */ | |
11188 | if (mips_opts.mips16 | |
11189 | && ep->X_op == O_symbol | |
11190 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
11191 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
11192 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
11193 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
11194 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
11195 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
11196 | } |
11197 | ||
252b5132 | 11198 | char * |
17a2f251 | 11199 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 11200 | { |
499ac353 | 11201 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
11202 | } |
11203 | ||
11204 | void | |
17a2f251 | 11205 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
11206 | { |
11207 | if (target_big_endian) | |
11208 | number_to_chars_bigendian (buf, val, n); | |
11209 | else | |
11210 | number_to_chars_littleendian (buf, val, n); | |
11211 | } | |
11212 | \f | |
ae948b86 | 11213 | #ifdef OBJ_ELF |
e013f690 TS |
11214 | static int support_64bit_objects(void) |
11215 | { | |
11216 | const char **list, **l; | |
aa3d8fdf | 11217 | int yes; |
e013f690 TS |
11218 | |
11219 | list = bfd_target_list (); | |
11220 | for (l = list; *l != NULL; l++) | |
11221 | #ifdef TE_TMIPS | |
11222 | /* This is traditional mips */ | |
11223 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
11224 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
11225 | #else | |
11226 | if (strcmp (*l, "elf64-bigmips") == 0 | |
11227 | || strcmp (*l, "elf64-littlemips") == 0) | |
11228 | #endif | |
11229 | break; | |
aa3d8fdf | 11230 | yes = (*l != NULL); |
e013f690 | 11231 | free (list); |
aa3d8fdf | 11232 | return yes; |
e013f690 | 11233 | } |
ae948b86 | 11234 | #endif /* OBJ_ELF */ |
e013f690 | 11235 | |
78849248 | 11236 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 11237 | |
23fce1e3 NC |
11238 | enum options |
11239 | { | |
11240 | OPTION_MARCH = OPTION_MD_BASE, | |
11241 | OPTION_MTUNE, | |
11242 | OPTION_MIPS1, | |
11243 | OPTION_MIPS2, | |
11244 | OPTION_MIPS3, | |
11245 | OPTION_MIPS4, | |
11246 | OPTION_MIPS5, | |
11247 | OPTION_MIPS32, | |
11248 | OPTION_MIPS64, | |
11249 | OPTION_MIPS32R2, | |
11250 | OPTION_MIPS64R2, | |
11251 | OPTION_MIPS16, | |
11252 | OPTION_NO_MIPS16, | |
11253 | OPTION_MIPS3D, | |
11254 | OPTION_NO_MIPS3D, | |
11255 | OPTION_MDMX, | |
11256 | OPTION_NO_MDMX, | |
11257 | OPTION_DSP, | |
11258 | OPTION_NO_DSP, | |
11259 | OPTION_MT, | |
11260 | OPTION_NO_MT, | |
11261 | OPTION_SMARTMIPS, | |
11262 | OPTION_NO_SMARTMIPS, | |
11263 | OPTION_DSPR2, | |
11264 | OPTION_NO_DSPR2, | |
11265 | OPTION_COMPAT_ARCH_BASE, | |
11266 | OPTION_M4650, | |
11267 | OPTION_NO_M4650, | |
11268 | OPTION_M4010, | |
11269 | OPTION_NO_M4010, | |
11270 | OPTION_M4100, | |
11271 | OPTION_NO_M4100, | |
11272 | OPTION_M3900, | |
11273 | OPTION_NO_M3900, | |
11274 | OPTION_M7000_HILO_FIX, | |
6a32d874 CM |
11275 | OPTION_MNO_7000_HILO_FIX, |
11276 | OPTION_FIX_24K, | |
11277 | OPTION_NO_FIX_24K, | |
c67a084a NC |
11278 | OPTION_FIX_LOONGSON2F_JUMP, |
11279 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
11280 | OPTION_FIX_LOONGSON2F_NOP, | |
11281 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
23fce1e3 NC |
11282 | OPTION_FIX_VR4120, |
11283 | OPTION_NO_FIX_VR4120, | |
11284 | OPTION_FIX_VR4130, | |
11285 | OPTION_NO_FIX_VR4130, | |
11286 | OPTION_TRAP, | |
11287 | OPTION_BREAK, | |
11288 | OPTION_EB, | |
11289 | OPTION_EL, | |
11290 | OPTION_FP32, | |
11291 | OPTION_GP32, | |
11292 | OPTION_CONSTRUCT_FLOATS, | |
11293 | OPTION_NO_CONSTRUCT_FLOATS, | |
11294 | OPTION_FP64, | |
11295 | OPTION_GP64, | |
11296 | OPTION_RELAX_BRANCH, | |
11297 | OPTION_NO_RELAX_BRANCH, | |
11298 | OPTION_MSHARED, | |
11299 | OPTION_MNO_SHARED, | |
11300 | OPTION_MSYM32, | |
11301 | OPTION_MNO_SYM32, | |
11302 | OPTION_SOFT_FLOAT, | |
11303 | OPTION_HARD_FLOAT, | |
11304 | OPTION_SINGLE_FLOAT, | |
11305 | OPTION_DOUBLE_FLOAT, | |
11306 | OPTION_32, | |
11307 | #ifdef OBJ_ELF | |
11308 | OPTION_CALL_SHARED, | |
11309 | OPTION_CALL_NONPIC, | |
11310 | OPTION_NON_SHARED, | |
11311 | OPTION_XGOT, | |
11312 | OPTION_MABI, | |
11313 | OPTION_N32, | |
11314 | OPTION_64, | |
11315 | OPTION_MDEBUG, | |
11316 | OPTION_NO_MDEBUG, | |
11317 | OPTION_PDR, | |
11318 | OPTION_NO_PDR, | |
11319 | OPTION_MVXWORKS_PIC, | |
11320 | #endif /* OBJ_ELF */ | |
11321 | OPTION_END_OF_ENUM | |
11322 | }; | |
11323 | ||
e972090a NC |
11324 | struct option md_longopts[] = |
11325 | { | |
f9b4148d | 11326 | /* Options which specify architecture. */ |
f9b4148d | 11327 | {"march", required_argument, NULL, OPTION_MARCH}, |
f9b4148d | 11328 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
252b5132 RH |
11329 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
11330 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
252b5132 | 11331 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
252b5132 | 11332 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
252b5132 | 11333 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
ae948b86 | 11334 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
ae948b86 | 11335 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
ae948b86 | 11336 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d | 11337 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
5f74bc13 | 11338 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
f9b4148d CD |
11339 | |
11340 | /* Options which specify Application Specific Extensions (ASEs). */ | |
f9b4148d | 11341 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
f9b4148d | 11342 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f9b4148d | 11343 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
f9b4148d | 11344 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
f9b4148d | 11345 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
f9b4148d | 11346 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
74cd071d | 11347 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
74cd071d | 11348 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
ef2e4d86 | 11349 | {"mmt", no_argument, NULL, OPTION_MT}, |
ef2e4d86 | 11350 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
e16bfa71 | 11351 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
e16bfa71 | 11352 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
8b082fb1 | 11353 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
8b082fb1 | 11354 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
f9b4148d CD |
11355 | |
11356 | /* Old-style architecture options. Don't add more of these. */ | |
f9b4148d | 11357 | {"m4650", no_argument, NULL, OPTION_M4650}, |
f9b4148d | 11358 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
f9b4148d | 11359 | {"m4010", no_argument, NULL, OPTION_M4010}, |
f9b4148d | 11360 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
f9b4148d | 11361 | {"m4100", no_argument, NULL, OPTION_M4100}, |
f9b4148d | 11362 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
f9b4148d | 11363 | {"m3900", no_argument, NULL, OPTION_M3900}, |
f9b4148d CD |
11364 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
11365 | ||
11366 | /* Options which enable bug fixes. */ | |
f9b4148d | 11367 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
f9b4148d CD |
11368 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
11369 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
c67a084a NC |
11370 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
11371 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
11372 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
11373 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
d766e8ec RS |
11374 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
11375 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
11376 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
11377 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
6a32d874 CM |
11378 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
11379 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
f9b4148d CD |
11380 | |
11381 | /* Miscellaneous options. */ | |
252b5132 RH |
11382 | {"trap", no_argument, NULL, OPTION_TRAP}, |
11383 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
252b5132 RH |
11384 | {"break", no_argument, NULL, OPTION_BREAK}, |
11385 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
252b5132 | 11386 | {"EB", no_argument, NULL, OPTION_EB}, |
252b5132 | 11387 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 11388 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
c97ef257 | 11389 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
119d663a | 11390 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
119d663a | 11391 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
316f5878 | 11392 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
ae948b86 | 11393 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
4a6a3df4 AO |
11394 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
11395 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
11396 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
11397 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
11398 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
11399 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
11400 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
11401 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
037b32b9 AN |
11402 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
11403 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
23fce1e3 NC |
11404 | |
11405 | /* Strictly speaking this next option is ELF specific, | |
11406 | but we allow it for other ports as well in order to | |
11407 | make testing easier. */ | |
11408 | {"32", no_argument, NULL, OPTION_32}, | |
037b32b9 | 11409 | |
f9b4148d | 11410 | /* ELF-specific options. */ |
156c2f8b | 11411 | #ifdef OBJ_ELF |
156c2f8b NC |
11412 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
11413 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
861fb55a | 11414 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
156c2f8b NC |
11415 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
11416 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
ae948b86 | 11417 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e013f690 | 11418 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b | 11419 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a | 11420 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
ecb4347a | 11421 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
dcd410fe | 11422 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
dcd410fe | 11423 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
0a44bf69 | 11424 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
ae948b86 | 11425 | #endif /* OBJ_ELF */ |
f9b4148d | 11426 | |
252b5132 RH |
11427 | {NULL, no_argument, NULL, 0} |
11428 | }; | |
156c2f8b | 11429 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 11430 | |
316f5878 RS |
11431 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
11432 | NEW_VALUE. Warn if another value was already specified. Note: | |
11433 | we have to defer parsing the -march and -mtune arguments in order | |
11434 | to handle 'from-abi' correctly, since the ABI might be specified | |
11435 | in a later argument. */ | |
11436 | ||
11437 | static void | |
17a2f251 | 11438 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
11439 | { |
11440 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
11441 | as_warn (_("A different %s was already specified, is now %s"), | |
11442 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
11443 | new_value); | |
11444 | ||
11445 | *string_ptr = new_value; | |
11446 | } | |
11447 | ||
252b5132 | 11448 | int |
17a2f251 | 11449 | md_parse_option (int c, char *arg) |
252b5132 RH |
11450 | { |
11451 | switch (c) | |
11452 | { | |
119d663a NC |
11453 | case OPTION_CONSTRUCT_FLOATS: |
11454 | mips_disable_float_construction = 0; | |
11455 | break; | |
bdaaa2e1 | 11456 | |
119d663a NC |
11457 | case OPTION_NO_CONSTRUCT_FLOATS: |
11458 | mips_disable_float_construction = 1; | |
11459 | break; | |
bdaaa2e1 | 11460 | |
252b5132 RH |
11461 | case OPTION_TRAP: |
11462 | mips_trap = 1; | |
11463 | break; | |
11464 | ||
11465 | case OPTION_BREAK: | |
11466 | mips_trap = 0; | |
11467 | break; | |
11468 | ||
11469 | case OPTION_EB: | |
11470 | target_big_endian = 1; | |
11471 | break; | |
11472 | ||
11473 | case OPTION_EL: | |
11474 | target_big_endian = 0; | |
11475 | break; | |
11476 | ||
11477 | case 'O': | |
4ffff32f TS |
11478 | if (arg == NULL) |
11479 | mips_optimize = 1; | |
11480 | else if (arg[0] == '0') | |
11481 | mips_optimize = 0; | |
11482 | else if (arg[0] == '1') | |
252b5132 RH |
11483 | mips_optimize = 1; |
11484 | else | |
11485 | mips_optimize = 2; | |
11486 | break; | |
11487 | ||
11488 | case 'g': | |
11489 | if (arg == NULL) | |
11490 | mips_debug = 2; | |
11491 | else | |
11492 | mips_debug = atoi (arg); | |
252b5132 RH |
11493 | break; |
11494 | ||
11495 | case OPTION_MIPS1: | |
316f5878 | 11496 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
11497 | break; |
11498 | ||
11499 | case OPTION_MIPS2: | |
316f5878 | 11500 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
11501 | break; |
11502 | ||
11503 | case OPTION_MIPS3: | |
316f5878 | 11504 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
11505 | break; |
11506 | ||
11507 | case OPTION_MIPS4: | |
316f5878 | 11508 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
11509 | break; |
11510 | ||
84ea6cf2 | 11511 | case OPTION_MIPS5: |
316f5878 | 11512 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
11513 | break; |
11514 | ||
e7af610e | 11515 | case OPTION_MIPS32: |
316f5878 | 11516 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
11517 | break; |
11518 | ||
af7ee8bf CD |
11519 | case OPTION_MIPS32R2: |
11520 | file_mips_isa = ISA_MIPS32R2; | |
11521 | break; | |
11522 | ||
5f74bc13 CD |
11523 | case OPTION_MIPS64R2: |
11524 | file_mips_isa = ISA_MIPS64R2; | |
11525 | break; | |
11526 | ||
84ea6cf2 | 11527 | case OPTION_MIPS64: |
316f5878 | 11528 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
11529 | break; |
11530 | ||
ec68c924 | 11531 | case OPTION_MTUNE: |
316f5878 RS |
11532 | mips_set_option_string (&mips_tune_string, arg); |
11533 | break; | |
ec68c924 | 11534 | |
316f5878 RS |
11535 | case OPTION_MARCH: |
11536 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
11537 | break; |
11538 | ||
11539 | case OPTION_M4650: | |
316f5878 RS |
11540 | mips_set_option_string (&mips_arch_string, "4650"); |
11541 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
11542 | break; |
11543 | ||
11544 | case OPTION_NO_M4650: | |
11545 | break; | |
11546 | ||
11547 | case OPTION_M4010: | |
316f5878 RS |
11548 | mips_set_option_string (&mips_arch_string, "4010"); |
11549 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
11550 | break; |
11551 | ||
11552 | case OPTION_NO_M4010: | |
11553 | break; | |
11554 | ||
11555 | case OPTION_M4100: | |
316f5878 RS |
11556 | mips_set_option_string (&mips_arch_string, "4100"); |
11557 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
11558 | break; |
11559 | ||
11560 | case OPTION_NO_M4100: | |
11561 | break; | |
11562 | ||
252b5132 | 11563 | case OPTION_M3900: |
316f5878 RS |
11564 | mips_set_option_string (&mips_arch_string, "3900"); |
11565 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 11566 | break; |
bdaaa2e1 | 11567 | |
252b5132 RH |
11568 | case OPTION_NO_M3900: |
11569 | break; | |
11570 | ||
deec1734 CD |
11571 | case OPTION_MDMX: |
11572 | mips_opts.ase_mdmx = 1; | |
11573 | break; | |
11574 | ||
11575 | case OPTION_NO_MDMX: | |
11576 | mips_opts.ase_mdmx = 0; | |
11577 | break; | |
11578 | ||
74cd071d CF |
11579 | case OPTION_DSP: |
11580 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 11581 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
11582 | break; |
11583 | ||
11584 | case OPTION_NO_DSP: | |
8b082fb1 TS |
11585 | mips_opts.ase_dsp = 0; |
11586 | mips_opts.ase_dspr2 = 0; | |
11587 | break; | |
11588 | ||
11589 | case OPTION_DSPR2: | |
11590 | mips_opts.ase_dspr2 = 1; | |
11591 | mips_opts.ase_dsp = 1; | |
11592 | break; | |
11593 | ||
11594 | case OPTION_NO_DSPR2: | |
11595 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
11596 | mips_opts.ase_dsp = 0; |
11597 | break; | |
11598 | ||
ef2e4d86 CF |
11599 | case OPTION_MT: |
11600 | mips_opts.ase_mt = 1; | |
11601 | break; | |
11602 | ||
11603 | case OPTION_NO_MT: | |
11604 | mips_opts.ase_mt = 0; | |
11605 | break; | |
11606 | ||
252b5132 RH |
11607 | case OPTION_MIPS16: |
11608 | mips_opts.mips16 = 1; | |
7d10b47d | 11609 | mips_no_prev_insn (); |
252b5132 RH |
11610 | break; |
11611 | ||
11612 | case OPTION_NO_MIPS16: | |
11613 | mips_opts.mips16 = 0; | |
7d10b47d | 11614 | mips_no_prev_insn (); |
252b5132 RH |
11615 | break; |
11616 | ||
1f25f5d3 CD |
11617 | case OPTION_MIPS3D: |
11618 | mips_opts.ase_mips3d = 1; | |
11619 | break; | |
11620 | ||
11621 | case OPTION_NO_MIPS3D: | |
11622 | mips_opts.ase_mips3d = 0; | |
11623 | break; | |
11624 | ||
e16bfa71 TS |
11625 | case OPTION_SMARTMIPS: |
11626 | mips_opts.ase_smartmips = 1; | |
11627 | break; | |
11628 | ||
11629 | case OPTION_NO_SMARTMIPS: | |
11630 | mips_opts.ase_smartmips = 0; | |
11631 | break; | |
11632 | ||
6a32d874 CM |
11633 | case OPTION_FIX_24K: |
11634 | mips_fix_24k = 1; | |
11635 | break; | |
11636 | ||
11637 | case OPTION_NO_FIX_24K: | |
11638 | mips_fix_24k = 0; | |
11639 | break; | |
11640 | ||
c67a084a NC |
11641 | case OPTION_FIX_LOONGSON2F_JUMP: |
11642 | mips_fix_loongson2f_jump = TRUE; | |
11643 | break; | |
11644 | ||
11645 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
11646 | mips_fix_loongson2f_jump = FALSE; | |
11647 | break; | |
11648 | ||
11649 | case OPTION_FIX_LOONGSON2F_NOP: | |
11650 | mips_fix_loongson2f_nop = TRUE; | |
11651 | break; | |
11652 | ||
11653 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
11654 | mips_fix_loongson2f_nop = FALSE; | |
11655 | break; | |
11656 | ||
d766e8ec RS |
11657 | case OPTION_FIX_VR4120: |
11658 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
11659 | break; |
11660 | ||
d766e8ec RS |
11661 | case OPTION_NO_FIX_VR4120: |
11662 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
11663 | break; |
11664 | ||
7d8e00cf RS |
11665 | case OPTION_FIX_VR4130: |
11666 | mips_fix_vr4130 = 1; | |
11667 | break; | |
11668 | ||
11669 | case OPTION_NO_FIX_VR4130: | |
11670 | mips_fix_vr4130 = 0; | |
11671 | break; | |
11672 | ||
4a6a3df4 AO |
11673 | case OPTION_RELAX_BRANCH: |
11674 | mips_relax_branch = 1; | |
11675 | break; | |
11676 | ||
11677 | case OPTION_NO_RELAX_BRANCH: | |
11678 | mips_relax_branch = 0; | |
11679 | break; | |
11680 | ||
aa6975fb ILT |
11681 | case OPTION_MSHARED: |
11682 | mips_in_shared = TRUE; | |
11683 | break; | |
11684 | ||
11685 | case OPTION_MNO_SHARED: | |
11686 | mips_in_shared = FALSE; | |
11687 | break; | |
11688 | ||
aed1a261 RS |
11689 | case OPTION_MSYM32: |
11690 | mips_opts.sym32 = TRUE; | |
11691 | break; | |
11692 | ||
11693 | case OPTION_MNO_SYM32: | |
11694 | mips_opts.sym32 = FALSE; | |
11695 | break; | |
11696 | ||
0f074f60 | 11697 | #ifdef OBJ_ELF |
252b5132 RH |
11698 | /* When generating ELF code, we permit -KPIC and -call_shared to |
11699 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
11700 | intended to be compatible with Irix 5. */ | |
11701 | case OPTION_CALL_SHARED: | |
f43abd2b | 11702 | if (!IS_ELF) |
252b5132 RH |
11703 | { |
11704 | as_bad (_("-call_shared is supported only for ELF format")); | |
11705 | return 0; | |
11706 | } | |
11707 | mips_pic = SVR4_PIC; | |
143d77c5 | 11708 | mips_abicalls = TRUE; |
252b5132 RH |
11709 | break; |
11710 | ||
861fb55a DJ |
11711 | case OPTION_CALL_NONPIC: |
11712 | if (!IS_ELF) | |
11713 | { | |
11714 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
11715 | return 0; | |
11716 | } | |
11717 | mips_pic = NO_PIC; | |
11718 | mips_abicalls = TRUE; | |
11719 | break; | |
11720 | ||
252b5132 | 11721 | case OPTION_NON_SHARED: |
f43abd2b | 11722 | if (!IS_ELF) |
252b5132 RH |
11723 | { |
11724 | as_bad (_("-non_shared is supported only for ELF format")); | |
11725 | return 0; | |
11726 | } | |
11727 | mips_pic = NO_PIC; | |
143d77c5 | 11728 | mips_abicalls = FALSE; |
252b5132 RH |
11729 | break; |
11730 | ||
44075ae2 TS |
11731 | /* The -xgot option tells the assembler to use 32 bit offsets |
11732 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
11733 | compatibility. */ |
11734 | case OPTION_XGOT: | |
11735 | mips_big_got = 1; | |
11736 | break; | |
0f074f60 | 11737 | #endif /* OBJ_ELF */ |
252b5132 RH |
11738 | |
11739 | case 'G': | |
6caf9ef4 TS |
11740 | g_switch_value = atoi (arg); |
11741 | g_switch_seen = 1; | |
252b5132 RH |
11742 | break; |
11743 | ||
34ba82a8 TS |
11744 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
11745 | and -mabi=64. */ | |
252b5132 | 11746 | case OPTION_32: |
23fce1e3 NC |
11747 | if (IS_ELF) |
11748 | mips_abi = O32_ABI; | |
11749 | /* We silently ignore -32 for non-ELF targets. This greatly | |
11750 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
11751 | break; |
11752 | ||
23fce1e3 | 11753 | #ifdef OBJ_ELF |
e013f690 | 11754 | case OPTION_N32: |
f43abd2b | 11755 | if (!IS_ELF) |
34ba82a8 TS |
11756 | { |
11757 | as_bad (_("-n32 is supported for ELF format only")); | |
11758 | return 0; | |
11759 | } | |
316f5878 | 11760 | mips_abi = N32_ABI; |
e013f690 | 11761 | break; |
252b5132 | 11762 | |
e013f690 | 11763 | case OPTION_64: |
f43abd2b | 11764 | if (!IS_ELF) |
34ba82a8 TS |
11765 | { |
11766 | as_bad (_("-64 is supported for ELF format only")); | |
11767 | return 0; | |
11768 | } | |
316f5878 | 11769 | mips_abi = N64_ABI; |
f43abd2b | 11770 | if (!support_64bit_objects()) |
e013f690 | 11771 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 11772 | break; |
ae948b86 | 11773 | #endif /* OBJ_ELF */ |
252b5132 | 11774 | |
c97ef257 | 11775 | case OPTION_GP32: |
a325df1d | 11776 | file_mips_gp32 = 1; |
c97ef257 AH |
11777 | break; |
11778 | ||
11779 | case OPTION_GP64: | |
a325df1d | 11780 | file_mips_gp32 = 0; |
c97ef257 | 11781 | break; |
252b5132 | 11782 | |
ca4e0257 | 11783 | case OPTION_FP32: |
a325df1d | 11784 | file_mips_fp32 = 1; |
316f5878 RS |
11785 | break; |
11786 | ||
11787 | case OPTION_FP64: | |
11788 | file_mips_fp32 = 0; | |
ca4e0257 RS |
11789 | break; |
11790 | ||
037b32b9 AN |
11791 | case OPTION_SINGLE_FLOAT: |
11792 | file_mips_single_float = 1; | |
11793 | break; | |
11794 | ||
11795 | case OPTION_DOUBLE_FLOAT: | |
11796 | file_mips_single_float = 0; | |
11797 | break; | |
11798 | ||
11799 | case OPTION_SOFT_FLOAT: | |
11800 | file_mips_soft_float = 1; | |
11801 | break; | |
11802 | ||
11803 | case OPTION_HARD_FLOAT: | |
11804 | file_mips_soft_float = 0; | |
11805 | break; | |
11806 | ||
ae948b86 | 11807 | #ifdef OBJ_ELF |
252b5132 | 11808 | case OPTION_MABI: |
f43abd2b | 11809 | if (!IS_ELF) |
34ba82a8 TS |
11810 | { |
11811 | as_bad (_("-mabi is supported for ELF format only")); | |
11812 | return 0; | |
11813 | } | |
e013f690 | 11814 | if (strcmp (arg, "32") == 0) |
316f5878 | 11815 | mips_abi = O32_ABI; |
e013f690 | 11816 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 11817 | mips_abi = O64_ABI; |
e013f690 | 11818 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 11819 | mips_abi = N32_ABI; |
e013f690 TS |
11820 | else if (strcmp (arg, "64") == 0) |
11821 | { | |
316f5878 | 11822 | mips_abi = N64_ABI; |
e013f690 TS |
11823 | if (! support_64bit_objects()) |
11824 | as_fatal (_("No compiled in support for 64 bit object file " | |
11825 | "format")); | |
11826 | } | |
11827 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 11828 | mips_abi = EABI_ABI; |
e013f690 | 11829 | else |
da0e507f TS |
11830 | { |
11831 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
11832 | return 0; | |
11833 | } | |
252b5132 | 11834 | break; |
e013f690 | 11835 | #endif /* OBJ_ELF */ |
252b5132 | 11836 | |
6b76fefe | 11837 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 11838 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
11839 | break; |
11840 | ||
9ee72ff1 | 11841 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 11842 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
11843 | break; |
11844 | ||
ecb4347a DJ |
11845 | #ifdef OBJ_ELF |
11846 | case OPTION_MDEBUG: | |
b34976b6 | 11847 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
11848 | break; |
11849 | ||
11850 | case OPTION_NO_MDEBUG: | |
b34976b6 | 11851 | mips_flag_mdebug = FALSE; |
ecb4347a | 11852 | break; |
dcd410fe RO |
11853 | |
11854 | case OPTION_PDR: | |
11855 | mips_flag_pdr = TRUE; | |
11856 | break; | |
11857 | ||
11858 | case OPTION_NO_PDR: | |
11859 | mips_flag_pdr = FALSE; | |
11860 | break; | |
0a44bf69 RS |
11861 | |
11862 | case OPTION_MVXWORKS_PIC: | |
11863 | mips_pic = VXWORKS_PIC; | |
11864 | break; | |
ecb4347a DJ |
11865 | #endif /* OBJ_ELF */ |
11866 | ||
252b5132 RH |
11867 | default: |
11868 | return 0; | |
11869 | } | |
11870 | ||
c67a084a NC |
11871 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
11872 | ||
252b5132 RH |
11873 | return 1; |
11874 | } | |
316f5878 RS |
11875 | \f |
11876 | /* Set up globals to generate code for the ISA or processor | |
11877 | described by INFO. */ | |
252b5132 | 11878 | |
252b5132 | 11879 | static void |
17a2f251 | 11880 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 11881 | { |
316f5878 | 11882 | if (info != 0) |
252b5132 | 11883 | { |
fef14a42 TS |
11884 | file_mips_arch = info->cpu; |
11885 | mips_opts.arch = info->cpu; | |
316f5878 | 11886 | mips_opts.isa = info->isa; |
252b5132 | 11887 | } |
252b5132 RH |
11888 | } |
11889 | ||
252b5132 | 11890 | |
316f5878 | 11891 | /* Likewise for tuning. */ |
252b5132 | 11892 | |
316f5878 | 11893 | static void |
17a2f251 | 11894 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
11895 | { |
11896 | if (info != 0) | |
fef14a42 | 11897 | mips_tune = info->cpu; |
316f5878 | 11898 | } |
80cc45a5 | 11899 | |
34ba82a8 | 11900 | |
252b5132 | 11901 | void |
17a2f251 | 11902 | mips_after_parse_args (void) |
e9670677 | 11903 | { |
fef14a42 TS |
11904 | const struct mips_cpu_info *arch_info = 0; |
11905 | const struct mips_cpu_info *tune_info = 0; | |
11906 | ||
e9670677 | 11907 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 11908 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 11909 | { |
6caf9ef4 | 11910 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
11911 | as_bad (_("-G not supported in this configuration.")); |
11912 | g_switch_value = 0; | |
11913 | } | |
11914 | ||
cac012d6 AO |
11915 | if (mips_abi == NO_ABI) |
11916 | mips_abi = MIPS_DEFAULT_ABI; | |
11917 | ||
22923709 RS |
11918 | /* The following code determines the architecture and register size. |
11919 | Similar code was added to GCC 3.3 (see override_options() in | |
11920 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
11921 | as much as possible. */ | |
e9670677 | 11922 | |
316f5878 | 11923 | if (mips_arch_string != 0) |
fef14a42 | 11924 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 11925 | |
316f5878 | 11926 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 11927 | { |
316f5878 | 11928 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 11929 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 11930 | the -march selection (if any). */ |
fef14a42 | 11931 | if (arch_info != 0) |
e9670677 | 11932 | { |
316f5878 RS |
11933 | /* -march takes precedence over -mipsN, since it is more descriptive. |
11934 | There's no harm in specifying both as long as the ISA levels | |
11935 | are the same. */ | |
fef14a42 | 11936 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
11937 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
11938 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 11939 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 11940 | } |
316f5878 | 11941 | else |
fef14a42 | 11942 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
11943 | } |
11944 | ||
fef14a42 TS |
11945 | if (arch_info == 0) |
11946 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 11947 | |
fef14a42 | 11948 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 11949 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
11950 | arch_info->name); |
11951 | ||
11952 | mips_set_architecture (arch_info); | |
11953 | ||
11954 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
11955 | if (mips_tune_string != 0) | |
11956 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 11957 | |
fef14a42 TS |
11958 | if (tune_info == 0) |
11959 | mips_set_tune (arch_info); | |
11960 | else | |
11961 | mips_set_tune (tune_info); | |
e9670677 | 11962 | |
316f5878 | 11963 | if (file_mips_gp32 >= 0) |
e9670677 | 11964 | { |
316f5878 RS |
11965 | /* The user specified the size of the integer registers. Make sure |
11966 | it agrees with the ABI and ISA. */ | |
11967 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
11968 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
11969 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11970 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
11971 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
11972 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
11973 | } |
11974 | else | |
11975 | { | |
316f5878 RS |
11976 | /* Infer the integer register size from the ABI and processor. |
11977 | Restrict ourselves to 32-bit registers if that's all the | |
11978 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
11979 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11980 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
11981 | } |
11982 | ||
ad3fea08 TS |
11983 | switch (file_mips_fp32) |
11984 | { | |
11985 | default: | |
11986 | case -1: | |
11987 | /* No user specified float register size. | |
11988 | ??? GAS treats single-float processors as though they had 64-bit | |
11989 | float registers (although it complains when double-precision | |
11990 | instructions are used). As things stand, saying they have 32-bit | |
11991 | registers would lead to spurious "register must be even" messages. | |
11992 | So here we assume float registers are never smaller than the | |
11993 | integer ones. */ | |
11994 | if (file_mips_gp32 == 0) | |
11995 | /* 64-bit integer registers implies 64-bit float registers. */ | |
11996 | file_mips_fp32 = 0; | |
11997 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
11998 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
11999 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
12000 | file_mips_fp32 = 0; | |
12001 | else | |
12002 | /* 32-bit float registers. */ | |
12003 | file_mips_fp32 = 1; | |
12004 | break; | |
12005 | ||
12006 | /* The user specified the size of the float registers. Check if it | |
12007 | agrees with the ABI and ISA. */ | |
12008 | case 0: | |
12009 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
12010 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
12011 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
12012 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
12013 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
12014 | break; | |
12015 | case 1: | |
12016 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
12017 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
12018 | break; | |
12019 | } | |
e9670677 | 12020 | |
316f5878 | 12021 | /* End of GCC-shared inference code. */ |
e9670677 | 12022 | |
17a2f251 TS |
12023 | /* This flag is set when we have a 64-bit capable CPU but use only |
12024 | 32-bit wide registers. Note that EABI does not use it. */ | |
12025 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
12026 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
12027 | || mips_abi == O32_ABI)) | |
316f5878 | 12028 | mips_32bitmode = 1; |
e9670677 MR |
12029 | |
12030 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
12031 | as_bad (_("trap exception not supported at ISA 1")); | |
12032 | ||
e9670677 MR |
12033 | /* If the selected architecture includes support for ASEs, enable |
12034 | generation of code for them. */ | |
a4672219 | 12035 | if (mips_opts.mips16 == -1) |
fef14a42 | 12036 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 12037 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 12038 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
12039 | && file_mips_fp32 == 0) ? 1 : 0; |
12040 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
12041 | as_bad (_("-mfp32 used with -mips3d")); | |
12042 | ||
ffdefa66 | 12043 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 12044 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
12045 | && file_mips_fp32 == 0) ? 1 : 0; |
12046 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
12047 | as_bad (_("-mfp32 used with -mdmx")); | |
12048 | ||
12049 | if (mips_opts.ase_smartmips == -1) | |
12050 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
12051 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
20203fb9 NC |
12052 | as_warn (_("%s ISA does not support SmartMIPS"), |
12053 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 12054 | |
74cd071d | 12055 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
12056 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
12057 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
20203fb9 NC |
12058 | as_warn (_("%s ISA does not support DSP ASE"), |
12059 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 12060 | |
8b082fb1 TS |
12061 | if (mips_opts.ase_dspr2 == -1) |
12062 | { | |
12063 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
12064 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
12065 | } | |
12066 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 NC |
12067 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
12068 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 12069 | |
ef2e4d86 | 12070 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
12071 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
12072 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
20203fb9 NC |
12073 | as_warn (_("%s ISA does not support MT ASE"), |
12074 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 12075 | |
e9670677 | 12076 | file_mips_isa = mips_opts.isa; |
a4672219 | 12077 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
12078 | file_ase_mips3d = mips_opts.ase_mips3d; |
12079 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 12080 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 12081 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 12082 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 12083 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
12084 | mips_opts.gp32 = file_mips_gp32; |
12085 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
12086 | mips_opts.soft_float = file_mips_soft_float; |
12087 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 12088 | |
ecb4347a DJ |
12089 | if (mips_flag_mdebug < 0) |
12090 | { | |
12091 | #ifdef OBJ_MAYBE_ECOFF | |
12092 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
12093 | mips_flag_mdebug = 1; | |
12094 | else | |
12095 | #endif /* OBJ_MAYBE_ECOFF */ | |
12096 | mips_flag_mdebug = 0; | |
12097 | } | |
e9670677 MR |
12098 | } |
12099 | \f | |
12100 | void | |
17a2f251 | 12101 | mips_init_after_args (void) |
252b5132 RH |
12102 | { |
12103 | /* initialize opcodes */ | |
12104 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 12105 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
12106 | } |
12107 | ||
12108 | long | |
17a2f251 | 12109 | md_pcrel_from (fixS *fixP) |
252b5132 | 12110 | { |
a7ebbfdf TS |
12111 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
12112 | switch (fixP->fx_r_type) | |
12113 | { | |
12114 | case BFD_RELOC_16_PCREL_S2: | |
12115 | case BFD_RELOC_MIPS_JMP: | |
12116 | /* Return the address of the delay slot. */ | |
12117 | return addr + 4; | |
12118 | default: | |
58ea3d6a | 12119 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
12120 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
12121 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12122 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
12123 | return addr; |
12124 | } | |
252b5132 RH |
12125 | } |
12126 | ||
252b5132 RH |
12127 | /* This is called before the symbol table is processed. In order to |
12128 | work with gcc when using mips-tfile, we must keep all local labels. | |
12129 | However, in other cases, we want to discard them. If we were | |
12130 | called with -g, but we didn't see any debugging information, it may | |
12131 | mean that gcc is smuggling debugging information through to | |
12132 | mips-tfile, in which case we must generate all local labels. */ | |
12133 | ||
12134 | void | |
17a2f251 | 12135 | mips_frob_file_before_adjust (void) |
252b5132 RH |
12136 | { |
12137 | #ifndef NO_ECOFF_DEBUGGING | |
12138 | if (ECOFF_DEBUGGING | |
12139 | && mips_debug != 0 | |
12140 | && ! ecoff_debugging_seen) | |
12141 | flag_keep_locals = 1; | |
12142 | #endif | |
12143 | } | |
12144 | ||
3b91255e | 12145 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 12146 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
12147 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
12148 | relocation operators. | |
12149 | ||
12150 | For our purposes, a %lo() expression matches a %got() or %hi() | |
12151 | expression if: | |
12152 | ||
12153 | (a) it refers to the same symbol; and | |
12154 | (b) the offset applied in the %lo() expression is no lower than | |
12155 | the offset applied in the %got() or %hi(). | |
12156 | ||
12157 | (b) allows us to cope with code like: | |
12158 | ||
12159 | lui $4,%hi(foo) | |
12160 | lh $4,%lo(foo+2)($4) | |
12161 | ||
12162 | ...which is legal on RELA targets, and has a well-defined behaviour | |
12163 | if the user knows that adding 2 to "foo" will not induce a carry to | |
12164 | the high 16 bits. | |
12165 | ||
12166 | When several %lo()s match a particular %got() or %hi(), we use the | |
12167 | following rules to distinguish them: | |
12168 | ||
12169 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
12170 | higher offsets. | |
12171 | ||
12172 | (2) %lo()s with no matching %got() or %hi() are better than those | |
12173 | that already have a matching %got() or %hi(). | |
12174 | ||
12175 | (3) later %lo()s are better than earlier %lo()s. | |
12176 | ||
12177 | These rules are applied in order. | |
12178 | ||
12179 | (1) means, among other things, that %lo()s with identical offsets are | |
12180 | chosen if they exist. | |
12181 | ||
12182 | (2) means that we won't associate several high-part relocations with | |
12183 | the same low-part relocation unless there's no alternative. Having | |
12184 | several high parts for the same low part is a GNU extension; this rule | |
12185 | allows careful users to avoid it. | |
12186 | ||
12187 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
12188 | with the last high-part relocation being at the front of the list. | |
12189 | It therefore makes sense to choose the last matching low-part | |
12190 | relocation, all other things being equal. It's also easier | |
12191 | to code that way. */ | |
252b5132 RH |
12192 | |
12193 | void | |
17a2f251 | 12194 | mips_frob_file (void) |
252b5132 RH |
12195 | { |
12196 | struct mips_hi_fixup *l; | |
35903be0 | 12197 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
12198 | |
12199 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
12200 | { | |
12201 | segment_info_type *seginfo; | |
3b91255e RS |
12202 | bfd_boolean matched_lo_p; |
12203 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 12204 | |
9c2799c2 | 12205 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 12206 | |
5919d012 RS |
12207 | /* If a GOT16 relocation turns out to be against a global symbol, |
12208 | there isn't supposed to be a matching LO. */ | |
738e5348 | 12209 | if (got16_reloc_p (l->fixp->fx_r_type) |
5919d012 RS |
12210 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) |
12211 | continue; | |
12212 | ||
12213 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
12214 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
12215 | continue; |
12216 | ||
252b5132 | 12217 | seginfo = seg_info (l->seg); |
252b5132 | 12218 | |
3b91255e RS |
12219 | /* Set HI_POS to the position of this relocation in the chain. |
12220 | Set LO_POS to the position of the chosen low-part relocation. | |
12221 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
12222 | relocation that matches an immediately-preceding high-part | |
12223 | relocation. */ | |
12224 | hi_pos = NULL; | |
12225 | lo_pos = NULL; | |
12226 | matched_lo_p = FALSE; | |
738e5348 | 12227 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 12228 | |
3b91255e RS |
12229 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
12230 | { | |
12231 | if (*pos == l->fixp) | |
12232 | hi_pos = pos; | |
12233 | ||
35903be0 | 12234 | if ((*pos)->fx_r_type == looking_for_rtype |
3b91255e RS |
12235 | && (*pos)->fx_addsy == l->fixp->fx_addsy |
12236 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
12237 | && (lo_pos == NULL | |
12238 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
12239 | || (!matched_lo_p | |
12240 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
12241 | lo_pos = pos; | |
12242 | ||
12243 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
12244 | && fixup_has_matching_lo_p (*pos)); | |
12245 | } | |
12246 | ||
12247 | /* If we found a match, remove the high-part relocation from its | |
12248 | current position and insert it before the low-part relocation. | |
12249 | Make the offsets match so that fixup_has_matching_lo_p() | |
12250 | will return true. | |
12251 | ||
12252 | We don't warn about unmatched high-part relocations since some | |
12253 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
12254 | instructions. */ | |
12255 | if (lo_pos != NULL) | |
12256 | { | |
12257 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
12258 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 12259 | { |
3b91255e RS |
12260 | *hi_pos = l->fixp->fx_next; |
12261 | l->fixp->fx_next = *lo_pos; | |
12262 | *lo_pos = l->fixp; | |
252b5132 | 12263 | } |
252b5132 RH |
12264 | } |
12265 | } | |
12266 | } | |
12267 | ||
3e722fb5 | 12268 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 12269 | We have to prevent gas from dropping them. */ |
252b5132 | 12270 | |
252b5132 | 12271 | int |
17a2f251 | 12272 | mips_force_relocation (fixS *fixp) |
252b5132 | 12273 | { |
ae6063d4 | 12274 | if (generic_force_reloc (fixp)) |
252b5132 RH |
12275 | return 1; |
12276 | ||
f6688943 TS |
12277 | if (HAVE_NEWABI |
12278 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
12279 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
738e5348 RS |
12280 | || hi16_reloc_p (fixp->fx_r_type) |
12281 | || lo16_reloc_p (fixp->fx_r_type))) | |
f6688943 TS |
12282 | return 1; |
12283 | ||
3e722fb5 | 12284 | return 0; |
252b5132 RH |
12285 | } |
12286 | ||
12287 | /* Apply a fixup to the object file. */ | |
12288 | ||
94f592af | 12289 | void |
55cf6793 | 12290 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 12291 | { |
874e8986 | 12292 | bfd_byte *buf; |
98aa84af | 12293 | long insn; |
a7ebbfdf | 12294 | reloc_howto_type *howto; |
252b5132 | 12295 | |
a7ebbfdf TS |
12296 | /* We ignore generic BFD relocations we don't know about. */ |
12297 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
12298 | if (! howto) | |
12299 | return; | |
65551fa4 | 12300 | |
9c2799c2 | 12301 | gas_assert (fixP->fx_size == 4 |
252b5132 RH |
12302 | || fixP->fx_r_type == BFD_RELOC_16 |
12303 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
12304 | || fixP->fx_r_type == BFD_RELOC_CTOR |
12305 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 12306 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
741d6ea8 JM |
12307 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY |
12308 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 12309 | |
a7ebbfdf | 12310 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 12311 | |
9c2799c2 | 12312 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2); |
b1dca8ee RS |
12313 | |
12314 | /* Don't treat parts of a composite relocation as done. There are two | |
12315 | reasons for this: | |
12316 | ||
12317 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
12318 | should nevertheless be emitted if the first part is. | |
12319 | ||
12320 | (2) In normal usage, composite relocations are never assembly-time | |
12321 | constants. The easiest way of dealing with the pathological | |
12322 | exceptions is to generate a relocation against STN_UNDEF and | |
12323 | leave everything up to the linker. */ | |
3994f87e | 12324 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
12325 | fixP->fx_done = 1; |
12326 | ||
12327 | switch (fixP->fx_r_type) | |
12328 | { | |
3f98094e DJ |
12329 | case BFD_RELOC_MIPS_TLS_GD: |
12330 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
12331 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
12332 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
12333 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
12334 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
12335 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
12336 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
12337 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
12338 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
12339 | /* fall through */ | |
12340 | ||
252b5132 | 12341 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
12342 | case BFD_RELOC_MIPS_SHIFT5: |
12343 | case BFD_RELOC_MIPS_SHIFT6: | |
12344 | case BFD_RELOC_MIPS_GOT_DISP: | |
12345 | case BFD_RELOC_MIPS_GOT_PAGE: | |
12346 | case BFD_RELOC_MIPS_GOT_OFST: | |
12347 | case BFD_RELOC_MIPS_SUB: | |
12348 | case BFD_RELOC_MIPS_INSERT_A: | |
12349 | case BFD_RELOC_MIPS_INSERT_B: | |
12350 | case BFD_RELOC_MIPS_DELETE: | |
12351 | case BFD_RELOC_MIPS_HIGHEST: | |
12352 | case BFD_RELOC_MIPS_HIGHER: | |
12353 | case BFD_RELOC_MIPS_SCN_DISP: | |
12354 | case BFD_RELOC_MIPS_REL16: | |
12355 | case BFD_RELOC_MIPS_RELGOT: | |
12356 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
12357 | case BFD_RELOC_HI16: |
12358 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 12359 | case BFD_RELOC_GPREL16: |
252b5132 RH |
12360 | case BFD_RELOC_MIPS_LITERAL: |
12361 | case BFD_RELOC_MIPS_CALL16: | |
12362 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 12363 | case BFD_RELOC_GPREL32: |
252b5132 RH |
12364 | case BFD_RELOC_MIPS_GOT_HI16: |
12365 | case BFD_RELOC_MIPS_GOT_LO16: | |
12366 | case BFD_RELOC_MIPS_CALL_HI16: | |
12367 | case BFD_RELOC_MIPS_CALL_LO16: | |
12368 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
12369 | case BFD_RELOC_MIPS16_GOT16: |
12370 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
12371 | case BFD_RELOC_MIPS16_HI16: |
12372 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 | 12373 | case BFD_RELOC_MIPS16_JMP: |
54f4ddb3 | 12374 | /* Nothing needed to do. The value comes from the reloc entry. */ |
252b5132 RH |
12375 | break; |
12376 | ||
252b5132 RH |
12377 | case BFD_RELOC_64: |
12378 | /* This is handled like BFD_RELOC_32, but we output a sign | |
12379 | extended value if we are only 32 bits. */ | |
3e722fb5 | 12380 | if (fixP->fx_done) |
252b5132 RH |
12381 | { |
12382 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 12383 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
12384 | else |
12385 | { | |
a7ebbfdf | 12386 | valueT hiv; |
252b5132 | 12387 | |
a7ebbfdf | 12388 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
12389 | hiv = 0xffffffff; |
12390 | else | |
12391 | hiv = 0; | |
b215186b | 12392 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 12393 | *valP, 4); |
b215186b | 12394 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 12395 | hiv, 4); |
252b5132 RH |
12396 | } |
12397 | } | |
12398 | break; | |
12399 | ||
056350c6 | 12400 | case BFD_RELOC_RVA: |
252b5132 | 12401 | case BFD_RELOC_32: |
252b5132 RH |
12402 | case BFD_RELOC_16: |
12403 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
12404 | value now. This can happen if we have a .word which is not |
12405 | resolved when it appears but is later defined. */ | |
252b5132 | 12406 | if (fixP->fx_done) |
54f4ddb3 | 12407 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); |
252b5132 RH |
12408 | break; |
12409 | ||
12410 | case BFD_RELOC_LO16: | |
d6f16593 | 12411 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
12412 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
12413 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
12414 | /* When handling an embedded PIC switch statement, we can wind |
12415 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
12416 | if (fixP->fx_done) | |
12417 | { | |
a7ebbfdf | 12418 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
12419 | as_bad_where (fixP->fx_file, fixP->fx_line, |
12420 | _("relocation overflow")); | |
252b5132 RH |
12421 | if (target_big_endian) |
12422 | buf += 2; | |
2132e3a3 | 12423 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
12424 | } |
12425 | break; | |
12426 | ||
12427 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 12428 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 12429 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 12430 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 12431 | |
54f4ddb3 TS |
12432 | /* We need to save the bits in the instruction since fixup_segment() |
12433 | might be deleting the relocation entry (i.e., a branch within | |
12434 | the current segment). */ | |
a7ebbfdf | 12435 | if (! fixP->fx_done) |
bb2d6cd7 | 12436 | break; |
252b5132 | 12437 | |
54f4ddb3 | 12438 | /* Update old instruction data. */ |
252b5132 RH |
12439 | if (target_big_endian) |
12440 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
12441 | else | |
12442 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
12443 | ||
a7ebbfdf TS |
12444 | if (*valP + 0x20000 <= 0x3ffff) |
12445 | { | |
12446 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 12447 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
12448 | } |
12449 | else if (mips_pic == NO_PIC | |
12450 | && fixP->fx_done | |
12451 | && fixP->fx_frag->fr_address >= text_section->vma | |
12452 | && (fixP->fx_frag->fr_address | |
587aac4e | 12453 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
12454 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
12455 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
12456 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
12457 | { |
12458 | /* The branch offset is too large. If this is an | |
12459 | unconditional branch, and we are not generating PIC code, | |
12460 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
12461 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
12462 | insn = 0x0c000000; /* jal */ | |
252b5132 | 12463 | else |
a7ebbfdf TS |
12464 | insn = 0x08000000; /* j */ |
12465 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
12466 | fixP->fx_done = 0; | |
12467 | fixP->fx_addsy = section_symbol (text_section); | |
12468 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 12469 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
12470 | } |
12471 | else | |
12472 | { | |
12473 | /* If we got here, we have branch-relaxation disabled, | |
12474 | and there's nothing we can do to fix this instruction | |
12475 | without turning it into a longer sequence. */ | |
12476 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12477 | _("Branch out of range")); | |
252b5132 | 12478 | } |
252b5132 RH |
12479 | break; |
12480 | ||
12481 | case BFD_RELOC_VTABLE_INHERIT: | |
12482 | fixP->fx_done = 0; | |
12483 | if (fixP->fx_addsy | |
12484 | && !S_IS_DEFINED (fixP->fx_addsy) | |
12485 | && !S_IS_WEAK (fixP->fx_addsy)) | |
12486 | S_SET_WEAK (fixP->fx_addsy); | |
12487 | break; | |
12488 | ||
12489 | case BFD_RELOC_VTABLE_ENTRY: | |
12490 | fixP->fx_done = 0; | |
12491 | break; | |
12492 | ||
12493 | default: | |
12494 | internalError (); | |
12495 | } | |
a7ebbfdf TS |
12496 | |
12497 | /* Remember value for tc_gen_reloc. */ | |
12498 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
12499 | } |
12500 | ||
252b5132 | 12501 | static symbolS * |
17a2f251 | 12502 | get_symbol (void) |
252b5132 RH |
12503 | { |
12504 | int c; | |
12505 | char *name; | |
12506 | symbolS *p; | |
12507 | ||
12508 | name = input_line_pointer; | |
12509 | c = get_symbol_end (); | |
12510 | p = (symbolS *) symbol_find_or_make (name); | |
12511 | *input_line_pointer = c; | |
12512 | return p; | |
12513 | } | |
12514 | ||
742a56fe RS |
12515 | /* Align the current frag to a given power of two. If a particular |
12516 | fill byte should be used, FILL points to an integer that contains | |
12517 | that byte, otherwise FILL is null. | |
12518 | ||
12519 | The MIPS assembler also automatically adjusts any preceding | |
12520 | label. */ | |
252b5132 RH |
12521 | |
12522 | static void | |
742a56fe | 12523 | mips_align (int to, int *fill, symbolS *label) |
252b5132 | 12524 | { |
7d10b47d | 12525 | mips_emit_delays (); |
742a56fe RS |
12526 | mips_record_mips16_mode (); |
12527 | if (fill == NULL && subseg_text_p (now_seg)) | |
12528 | frag_align_code (to, 0); | |
12529 | else | |
12530 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 RH |
12531 | record_alignment (now_seg, to); |
12532 | if (label != NULL) | |
12533 | { | |
9c2799c2 | 12534 | gas_assert (S_GET_SEGMENT (label) == now_seg); |
49309057 | 12535 | symbol_set_frag (label, frag_now); |
252b5132 RH |
12536 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
12537 | } | |
12538 | } | |
12539 | ||
12540 | /* Align to a given power of two. .align 0 turns off the automatic | |
12541 | alignment used by the data creating pseudo-ops. */ | |
12542 | ||
12543 | static void | |
17a2f251 | 12544 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 12545 | { |
742a56fe | 12546 | int temp, fill_value, *fill_ptr; |
49954fb4 | 12547 | long max_alignment = 28; |
252b5132 | 12548 | |
54f4ddb3 | 12549 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 12550 | to the aligned address. |
54f4ddb3 | 12551 | o It's not documented but auto alignment is reinstated by |
252b5132 | 12552 | a .align pseudo instruction. |
54f4ddb3 | 12553 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 12554 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 12555 | We don't. */ |
252b5132 RH |
12556 | |
12557 | temp = get_absolute_expression (); | |
12558 | if (temp > max_alignment) | |
12559 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
12560 | else if (temp < 0) | |
12561 | { | |
12562 | as_warn (_("Alignment negative: 0 assumed.")); | |
12563 | temp = 0; | |
12564 | } | |
12565 | if (*input_line_pointer == ',') | |
12566 | { | |
f9419b05 | 12567 | ++input_line_pointer; |
742a56fe RS |
12568 | fill_value = get_absolute_expression (); |
12569 | fill_ptr = &fill_value; | |
252b5132 RH |
12570 | } |
12571 | else | |
742a56fe | 12572 | fill_ptr = 0; |
252b5132 RH |
12573 | if (temp) |
12574 | { | |
a8dbcb85 TS |
12575 | segment_info_type *si = seg_info (now_seg); |
12576 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 12577 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 12578 | auto_align = 1; |
742a56fe | 12579 | mips_align (temp, fill_ptr, l != NULL ? l->label : NULL); |
252b5132 RH |
12580 | } |
12581 | else | |
12582 | { | |
12583 | auto_align = 0; | |
12584 | } | |
12585 | ||
12586 | demand_empty_rest_of_line (); | |
12587 | } | |
12588 | ||
252b5132 | 12589 | static void |
17a2f251 | 12590 | s_change_sec (int sec) |
252b5132 RH |
12591 | { |
12592 | segT seg; | |
12593 | ||
252b5132 RH |
12594 | #ifdef OBJ_ELF |
12595 | /* The ELF backend needs to know that we are changing sections, so | |
12596 | that .previous works correctly. We could do something like check | |
b6ff326e | 12597 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
12598 | as it would not be appropriate to use it in the section changing |
12599 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
12600 | This should be cleaner, somehow. */ | |
f43abd2b TS |
12601 | if (IS_ELF) |
12602 | obj_elf_section_change_hook (); | |
252b5132 RH |
12603 | #endif |
12604 | ||
7d10b47d | 12605 | mips_emit_delays (); |
6a32d874 | 12606 | |
252b5132 RH |
12607 | switch (sec) |
12608 | { | |
12609 | case 't': | |
12610 | s_text (0); | |
12611 | break; | |
12612 | case 'd': | |
12613 | s_data (0); | |
12614 | break; | |
12615 | case 'b': | |
12616 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
12617 | demand_empty_rest_of_line (); | |
12618 | break; | |
12619 | ||
12620 | case 'r': | |
4d0d148d TS |
12621 | seg = subseg_new (RDATA_SECTION_NAME, |
12622 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 12623 | if (IS_ELF) |
252b5132 | 12624 | { |
4d0d148d TS |
12625 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
12626 | | SEC_READONLY | SEC_RELOC | |
12627 | | SEC_DATA)); | |
c41e87e3 | 12628 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 12629 | record_alignment (seg, 4); |
252b5132 | 12630 | } |
4d0d148d | 12631 | demand_empty_rest_of_line (); |
252b5132 RH |
12632 | break; |
12633 | ||
12634 | case 's': | |
4d0d148d | 12635 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 12636 | if (IS_ELF) |
252b5132 | 12637 | { |
4d0d148d TS |
12638 | bfd_set_section_flags (stdoutput, seg, |
12639 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 12640 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 12641 | record_alignment (seg, 4); |
252b5132 | 12642 | } |
4d0d148d TS |
12643 | demand_empty_rest_of_line (); |
12644 | break; | |
252b5132 RH |
12645 | } |
12646 | ||
12647 | auto_align = 1; | |
12648 | } | |
b34976b6 | 12649 | |
cca86cc8 | 12650 | void |
17a2f251 | 12651 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 12652 | { |
7ed4a06a | 12653 | #ifdef OBJ_ELF |
cca86cc8 SC |
12654 | char *section_name; |
12655 | char c; | |
684022ea | 12656 | char next_c = 0; |
cca86cc8 SC |
12657 | int section_type; |
12658 | int section_flag; | |
12659 | int section_entry_size; | |
12660 | int section_alignment; | |
b34976b6 | 12661 | |
f43abd2b | 12662 | if (!IS_ELF) |
7ed4a06a TS |
12663 | return; |
12664 | ||
cca86cc8 SC |
12665 | section_name = input_line_pointer; |
12666 | c = get_symbol_end (); | |
a816d1ed AO |
12667 | if (c) |
12668 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 12669 | |
4cf0dd0d TS |
12670 | /* Do we have .section Name<,"flags">? */ |
12671 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 12672 | { |
4cf0dd0d TS |
12673 | /* just after name is now '\0'. */ |
12674 | *input_line_pointer = c; | |
cca86cc8 SC |
12675 | input_line_pointer = section_name; |
12676 | obj_elf_section (ignore); | |
12677 | return; | |
12678 | } | |
12679 | input_line_pointer++; | |
12680 | ||
12681 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
12682 | if (c == ',') | |
12683 | section_type = get_absolute_expression (); | |
12684 | else | |
12685 | section_type = 0; | |
12686 | if (*input_line_pointer++ == ',') | |
12687 | section_flag = get_absolute_expression (); | |
12688 | else | |
12689 | section_flag = 0; | |
12690 | if (*input_line_pointer++ == ',') | |
12691 | section_entry_size = get_absolute_expression (); | |
12692 | else | |
12693 | section_entry_size = 0; | |
12694 | if (*input_line_pointer++ == ',') | |
12695 | section_alignment = get_absolute_expression (); | |
12696 | else | |
12697 | section_alignment = 0; | |
12698 | ||
a816d1ed AO |
12699 | section_name = xstrdup (section_name); |
12700 | ||
8ab8a5c8 RS |
12701 | /* When using the generic form of .section (as implemented by obj-elf.c), |
12702 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
12703 | traditionally had to fall back on the more common @progbits instead. | |
12704 | ||
12705 | There's nothing really harmful in this, since bfd will correct | |
12706 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 12707 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
12708 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
12709 | ||
12710 | Even so, we shouldn't force users of the MIPS .section syntax to | |
12711 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
12712 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
12713 | generic type-checking code. */ | |
12714 | if (section_type == SHT_MIPS_DWARF) | |
12715 | section_type = SHT_PROGBITS; | |
12716 | ||
cca86cc8 SC |
12717 | obj_elf_change_section (section_name, section_type, section_flag, |
12718 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
12719 | |
12720 | if (now_seg->name != section_name) | |
12721 | free (section_name); | |
7ed4a06a | 12722 | #endif /* OBJ_ELF */ |
cca86cc8 | 12723 | } |
252b5132 RH |
12724 | |
12725 | void | |
17a2f251 | 12726 | mips_enable_auto_align (void) |
252b5132 RH |
12727 | { |
12728 | auto_align = 1; | |
12729 | } | |
12730 | ||
12731 | static void | |
17a2f251 | 12732 | s_cons (int log_size) |
252b5132 | 12733 | { |
a8dbcb85 TS |
12734 | segment_info_type *si = seg_info (now_seg); |
12735 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12736 | symbolS *label; |
12737 | ||
a8dbcb85 | 12738 | label = l != NULL ? l->label : NULL; |
7d10b47d | 12739 | mips_emit_delays (); |
252b5132 RH |
12740 | if (log_size > 0 && auto_align) |
12741 | mips_align (log_size, 0, label); | |
12742 | mips_clear_insn_labels (); | |
12743 | cons (1 << log_size); | |
12744 | } | |
12745 | ||
12746 | static void | |
17a2f251 | 12747 | s_float_cons (int type) |
252b5132 | 12748 | { |
a8dbcb85 TS |
12749 | segment_info_type *si = seg_info (now_seg); |
12750 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12751 | symbolS *label; |
12752 | ||
a8dbcb85 | 12753 | label = l != NULL ? l->label : NULL; |
252b5132 | 12754 | |
7d10b47d | 12755 | mips_emit_delays (); |
252b5132 RH |
12756 | |
12757 | if (auto_align) | |
49309057 ILT |
12758 | { |
12759 | if (type == 'd') | |
12760 | mips_align (3, 0, label); | |
12761 | else | |
12762 | mips_align (2, 0, label); | |
12763 | } | |
252b5132 RH |
12764 | |
12765 | mips_clear_insn_labels (); | |
12766 | ||
12767 | float_cons (type); | |
12768 | } | |
12769 | ||
12770 | /* Handle .globl. We need to override it because on Irix 5 you are | |
12771 | permitted to say | |
12772 | .globl foo .text | |
12773 | where foo is an undefined symbol, to mean that foo should be | |
12774 | considered to be the address of a function. */ | |
12775 | ||
12776 | static void | |
17a2f251 | 12777 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12778 | { |
12779 | char *name; | |
12780 | int c; | |
12781 | symbolS *symbolP; | |
12782 | flagword flag; | |
12783 | ||
8a06b769 | 12784 | do |
252b5132 | 12785 | { |
8a06b769 | 12786 | name = input_line_pointer; |
252b5132 | 12787 | c = get_symbol_end (); |
8a06b769 TS |
12788 | symbolP = symbol_find_or_make (name); |
12789 | S_SET_EXTERNAL (symbolP); | |
12790 | ||
252b5132 | 12791 | *input_line_pointer = c; |
8a06b769 | 12792 | SKIP_WHITESPACE (); |
252b5132 | 12793 | |
8a06b769 TS |
12794 | /* On Irix 5, every global symbol that is not explicitly labelled as |
12795 | being a function is apparently labelled as being an object. */ | |
12796 | flag = BSF_OBJECT; | |
252b5132 | 12797 | |
8a06b769 TS |
12798 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
12799 | && (*input_line_pointer != ',')) | |
12800 | { | |
12801 | char *secname; | |
12802 | asection *sec; | |
12803 | ||
12804 | secname = input_line_pointer; | |
12805 | c = get_symbol_end (); | |
12806 | sec = bfd_get_section_by_name (stdoutput, secname); | |
12807 | if (sec == NULL) | |
12808 | as_bad (_("%s: no such section"), secname); | |
12809 | *input_line_pointer = c; | |
12810 | ||
12811 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
12812 | flag = BSF_FUNCTION; | |
12813 | } | |
12814 | ||
12815 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
12816 | ||
12817 | c = *input_line_pointer; | |
12818 | if (c == ',') | |
12819 | { | |
12820 | input_line_pointer++; | |
12821 | SKIP_WHITESPACE (); | |
12822 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
12823 | c = '\n'; | |
12824 | } | |
12825 | } | |
12826 | while (c == ','); | |
252b5132 | 12827 | |
252b5132 RH |
12828 | demand_empty_rest_of_line (); |
12829 | } | |
12830 | ||
12831 | static void | |
17a2f251 | 12832 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12833 | { |
12834 | char *opt; | |
12835 | char c; | |
12836 | ||
12837 | opt = input_line_pointer; | |
12838 | c = get_symbol_end (); | |
12839 | ||
12840 | if (*opt == 'O') | |
12841 | { | |
12842 | /* FIXME: What does this mean? */ | |
12843 | } | |
12844 | else if (strncmp (opt, "pic", 3) == 0) | |
12845 | { | |
12846 | int i; | |
12847 | ||
12848 | i = atoi (opt + 3); | |
12849 | if (i == 0) | |
12850 | mips_pic = NO_PIC; | |
12851 | else if (i == 2) | |
143d77c5 | 12852 | { |
252b5132 | 12853 | mips_pic = SVR4_PIC; |
143d77c5 EC |
12854 | mips_abicalls = TRUE; |
12855 | } | |
252b5132 RH |
12856 | else |
12857 | as_bad (_(".option pic%d not supported"), i); | |
12858 | ||
4d0d148d | 12859 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
12860 | { |
12861 | if (g_switch_seen && g_switch_value != 0) | |
12862 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12863 | g_switch_value = 0; | |
12864 | bfd_set_gp_size (stdoutput, 0); | |
12865 | } | |
12866 | } | |
12867 | else | |
12868 | as_warn (_("Unrecognized option \"%s\""), opt); | |
12869 | ||
12870 | *input_line_pointer = c; | |
12871 | demand_empty_rest_of_line (); | |
12872 | } | |
12873 | ||
12874 | /* This structure is used to hold a stack of .set values. */ | |
12875 | ||
e972090a NC |
12876 | struct mips_option_stack |
12877 | { | |
252b5132 RH |
12878 | struct mips_option_stack *next; |
12879 | struct mips_set_options options; | |
12880 | }; | |
12881 | ||
12882 | static struct mips_option_stack *mips_opts_stack; | |
12883 | ||
12884 | /* Handle the .set pseudo-op. */ | |
12885 | ||
12886 | static void | |
17a2f251 | 12887 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12888 | { |
12889 | char *name = input_line_pointer, ch; | |
12890 | ||
12891 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 12892 | ++input_line_pointer; |
252b5132 RH |
12893 | ch = *input_line_pointer; |
12894 | *input_line_pointer = '\0'; | |
12895 | ||
12896 | if (strcmp (name, "reorder") == 0) | |
12897 | { | |
7d10b47d RS |
12898 | if (mips_opts.noreorder) |
12899 | end_noreorder (); | |
252b5132 RH |
12900 | } |
12901 | else if (strcmp (name, "noreorder") == 0) | |
12902 | { | |
7d10b47d RS |
12903 | if (!mips_opts.noreorder) |
12904 | start_noreorder (); | |
252b5132 | 12905 | } |
741fe287 MR |
12906 | else if (strncmp (name, "at=", 3) == 0) |
12907 | { | |
12908 | char *s = name + 3; | |
12909 | ||
12910 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
12911 | as_bad (_("Unrecognized register name `%s'"), s); | |
12912 | } | |
252b5132 RH |
12913 | else if (strcmp (name, "at") == 0) |
12914 | { | |
741fe287 | 12915 | mips_opts.at = ATREG; |
252b5132 RH |
12916 | } |
12917 | else if (strcmp (name, "noat") == 0) | |
12918 | { | |
741fe287 | 12919 | mips_opts.at = ZERO; |
252b5132 RH |
12920 | } |
12921 | else if (strcmp (name, "macro") == 0) | |
12922 | { | |
12923 | mips_opts.warn_about_macros = 0; | |
12924 | } | |
12925 | else if (strcmp (name, "nomacro") == 0) | |
12926 | { | |
12927 | if (mips_opts.noreorder == 0) | |
12928 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
12929 | mips_opts.warn_about_macros = 1; | |
12930 | } | |
12931 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
12932 | { | |
12933 | mips_opts.nomove = 0; | |
12934 | } | |
12935 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
12936 | { | |
12937 | mips_opts.nomove = 1; | |
12938 | } | |
12939 | else if (strcmp (name, "bopt") == 0) | |
12940 | { | |
12941 | mips_opts.nobopt = 0; | |
12942 | } | |
12943 | else if (strcmp (name, "nobopt") == 0) | |
12944 | { | |
12945 | mips_opts.nobopt = 1; | |
12946 | } | |
ad3fea08 TS |
12947 | else if (strcmp (name, "gp=default") == 0) |
12948 | mips_opts.gp32 = file_mips_gp32; | |
12949 | else if (strcmp (name, "gp=32") == 0) | |
12950 | mips_opts.gp32 = 1; | |
12951 | else if (strcmp (name, "gp=64") == 0) | |
12952 | { | |
12953 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 12954 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
12955 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
12956 | mips_opts.gp32 = 0; | |
12957 | } | |
12958 | else if (strcmp (name, "fp=default") == 0) | |
12959 | mips_opts.fp32 = file_mips_fp32; | |
12960 | else if (strcmp (name, "fp=32") == 0) | |
12961 | mips_opts.fp32 = 1; | |
12962 | else if (strcmp (name, "fp=64") == 0) | |
12963 | { | |
12964 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 12965 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
12966 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
12967 | mips_opts.fp32 = 0; | |
12968 | } | |
037b32b9 AN |
12969 | else if (strcmp (name, "softfloat") == 0) |
12970 | mips_opts.soft_float = 1; | |
12971 | else if (strcmp (name, "hardfloat") == 0) | |
12972 | mips_opts.soft_float = 0; | |
12973 | else if (strcmp (name, "singlefloat") == 0) | |
12974 | mips_opts.single_float = 1; | |
12975 | else if (strcmp (name, "doublefloat") == 0) | |
12976 | mips_opts.single_float = 0; | |
252b5132 RH |
12977 | else if (strcmp (name, "mips16") == 0 |
12978 | || strcmp (name, "MIPS-16") == 0) | |
12979 | mips_opts.mips16 = 1; | |
12980 | else if (strcmp (name, "nomips16") == 0 | |
12981 | || strcmp (name, "noMIPS-16") == 0) | |
12982 | mips_opts.mips16 = 0; | |
e16bfa71 TS |
12983 | else if (strcmp (name, "smartmips") == 0) |
12984 | { | |
ad3fea08 | 12985 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 12986 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 TS |
12987 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
12988 | mips_opts.ase_smartmips = 1; | |
12989 | } | |
12990 | else if (strcmp (name, "nosmartmips") == 0) | |
12991 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
12992 | else if (strcmp (name, "mips3d") == 0) |
12993 | mips_opts.ase_mips3d = 1; | |
12994 | else if (strcmp (name, "nomips3d") == 0) | |
12995 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
12996 | else if (strcmp (name, "mdmx") == 0) |
12997 | mips_opts.ase_mdmx = 1; | |
12998 | else if (strcmp (name, "nomdmx") == 0) | |
12999 | mips_opts.ase_mdmx = 0; | |
74cd071d | 13000 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
13001 | { |
13002 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 13003 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 TS |
13004 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13005 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 13006 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 13007 | } |
74cd071d | 13008 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
13009 | { |
13010 | mips_opts.ase_dsp = 0; | |
13011 | mips_opts.ase_dspr2 = 0; | |
13012 | } | |
13013 | else if (strcmp (name, "dspr2") == 0) | |
13014 | { | |
13015 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 13016 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 TS |
13017 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13018 | mips_opts.ase_dspr2 = 1; | |
13019 | mips_opts.ase_dsp = 1; | |
13020 | } | |
13021 | else if (strcmp (name, "nodspr2") == 0) | |
13022 | { | |
13023 | mips_opts.ase_dspr2 = 0; | |
13024 | mips_opts.ase_dsp = 0; | |
13025 | } | |
ef2e4d86 | 13026 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
13027 | { |
13028 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 13029 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 TS |
13030 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13031 | mips_opts.ase_mt = 1; | |
13032 | } | |
ef2e4d86 CF |
13033 | else if (strcmp (name, "nomt") == 0) |
13034 | mips_opts.ase_mt = 0; | |
1a2c1fad | 13035 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 13036 | { |
af7ee8bf | 13037 | int reset = 0; |
252b5132 | 13038 | |
1a2c1fad CD |
13039 | /* Permit the user to change the ISA and architecture on the fly. |
13040 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 13041 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
13042 | { |
13043 | reset = 1; | |
13044 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 13045 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
13046 | } |
13047 | else if (strncmp (name, "arch=", 5) == 0) | |
13048 | { | |
13049 | const struct mips_cpu_info *p; | |
13050 | ||
13051 | p = mips_parse_cpu("internal use", name + 5); | |
13052 | if (!p) | |
13053 | as_bad (_("unknown architecture %s"), name + 5); | |
13054 | else | |
13055 | { | |
13056 | mips_opts.arch = p->cpu; | |
13057 | mips_opts.isa = p->isa; | |
13058 | } | |
13059 | } | |
81a21e38 TS |
13060 | else if (strncmp (name, "mips", 4) == 0) |
13061 | { | |
13062 | const struct mips_cpu_info *p; | |
13063 | ||
13064 | p = mips_parse_cpu("internal use", name); | |
13065 | if (!p) | |
13066 | as_bad (_("unknown ISA level %s"), name + 4); | |
13067 | else | |
13068 | { | |
13069 | mips_opts.arch = p->cpu; | |
13070 | mips_opts.isa = p->isa; | |
13071 | } | |
13072 | } | |
af7ee8bf | 13073 | else |
81a21e38 | 13074 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
13075 | |
13076 | switch (mips_opts.isa) | |
98d3f06f KH |
13077 | { |
13078 | case 0: | |
98d3f06f | 13079 | break; |
af7ee8bf CD |
13080 | case ISA_MIPS1: |
13081 | case ISA_MIPS2: | |
13082 | case ISA_MIPS32: | |
13083 | case ISA_MIPS32R2: | |
98d3f06f KH |
13084 | mips_opts.gp32 = 1; |
13085 | mips_opts.fp32 = 1; | |
13086 | break; | |
af7ee8bf CD |
13087 | case ISA_MIPS3: |
13088 | case ISA_MIPS4: | |
13089 | case ISA_MIPS5: | |
13090 | case ISA_MIPS64: | |
5f74bc13 | 13091 | case ISA_MIPS64R2: |
98d3f06f KH |
13092 | mips_opts.gp32 = 0; |
13093 | mips_opts.fp32 = 0; | |
13094 | break; | |
13095 | default: | |
13096 | as_bad (_("unknown ISA level %s"), name + 4); | |
13097 | break; | |
13098 | } | |
af7ee8bf | 13099 | if (reset) |
98d3f06f | 13100 | { |
af7ee8bf CD |
13101 | mips_opts.gp32 = file_mips_gp32; |
13102 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 13103 | } |
252b5132 RH |
13104 | } |
13105 | else if (strcmp (name, "autoextend") == 0) | |
13106 | mips_opts.noautoextend = 0; | |
13107 | else if (strcmp (name, "noautoextend") == 0) | |
13108 | mips_opts.noautoextend = 1; | |
13109 | else if (strcmp (name, "push") == 0) | |
13110 | { | |
13111 | struct mips_option_stack *s; | |
13112 | ||
13113 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
13114 | s->next = mips_opts_stack; | |
13115 | s->options = mips_opts; | |
13116 | mips_opts_stack = s; | |
13117 | } | |
13118 | else if (strcmp (name, "pop") == 0) | |
13119 | { | |
13120 | struct mips_option_stack *s; | |
13121 | ||
13122 | s = mips_opts_stack; | |
13123 | if (s == NULL) | |
13124 | as_bad (_(".set pop with no .set push")); | |
13125 | else | |
13126 | { | |
13127 | /* If we're changing the reorder mode we need to handle | |
13128 | delay slots correctly. */ | |
13129 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 13130 | start_noreorder (); |
252b5132 | 13131 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 13132 | end_noreorder (); |
252b5132 RH |
13133 | |
13134 | mips_opts = s->options; | |
13135 | mips_opts_stack = s->next; | |
13136 | free (s); | |
13137 | } | |
13138 | } | |
aed1a261 RS |
13139 | else if (strcmp (name, "sym32") == 0) |
13140 | mips_opts.sym32 = TRUE; | |
13141 | else if (strcmp (name, "nosym32") == 0) | |
13142 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
13143 | else if (strchr (name, ',')) |
13144 | { | |
13145 | /* Generic ".set" directive; use the generic handler. */ | |
13146 | *input_line_pointer = ch; | |
13147 | input_line_pointer = name; | |
13148 | s_set (0); | |
13149 | return; | |
13150 | } | |
252b5132 RH |
13151 | else |
13152 | { | |
13153 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
13154 | } | |
13155 | *input_line_pointer = ch; | |
13156 | demand_empty_rest_of_line (); | |
13157 | } | |
13158 | ||
13159 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
13160 | .option pic2. It means to generate SVR4 PIC calls. */ | |
13161 | ||
13162 | static void | |
17a2f251 | 13163 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13164 | { |
13165 | mips_pic = SVR4_PIC; | |
143d77c5 | 13166 | mips_abicalls = TRUE; |
4d0d148d TS |
13167 | |
13168 | if (g_switch_seen && g_switch_value != 0) | |
13169 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
13170 | g_switch_value = 0; | |
13171 | ||
252b5132 RH |
13172 | bfd_set_gp_size (stdoutput, 0); |
13173 | demand_empty_rest_of_line (); | |
13174 | } | |
13175 | ||
13176 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
13177 | PIC code. It sets the $gp register for the function based on the | |
13178 | function address, which is in the register named in the argument. | |
13179 | This uses a relocation against _gp_disp, which is handled specially | |
13180 | by the linker. The result is: | |
13181 | lui $gp,%hi(_gp_disp) | |
13182 | addiu $gp,$gp,%lo(_gp_disp) | |
13183 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
13184 | The .cpload argument is normally $25 == $t9. |
13185 | ||
13186 | The -mno-shared option changes this to: | |
bbe506e8 TS |
13187 | lui $gp,%hi(__gnu_local_gp) |
13188 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
13189 | and the argument is ignored. This saves an instruction, but the |
13190 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
13191 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
13192 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
13193 | |
13194 | static void | |
17a2f251 | 13195 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13196 | { |
13197 | expressionS ex; | |
aa6975fb ILT |
13198 | int reg; |
13199 | int in_shared; | |
252b5132 | 13200 | |
6478892d TS |
13201 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
13202 | .cpload is ignored. */ | |
13203 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
13204 | { |
13205 | s_ignore (0); | |
13206 | return; | |
13207 | } | |
13208 | ||
d3ecfc59 | 13209 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
13210 | if (mips_opts.noreorder == 0) |
13211 | as_warn (_(".cpload not in noreorder section")); | |
13212 | ||
aa6975fb ILT |
13213 | reg = tc_get_register (0); |
13214 | ||
13215 | /* If we need to produce a 64-bit address, we are better off using | |
13216 | the default instruction sequence. */ | |
aed1a261 | 13217 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 13218 | |
252b5132 | 13219 | ex.X_op = O_symbol; |
bbe506e8 TS |
13220 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
13221 | "__gnu_local_gp"); | |
252b5132 RH |
13222 | ex.X_op_symbol = NULL; |
13223 | ex.X_add_number = 0; | |
13224 | ||
13225 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 13226 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 13227 | |
584892a6 | 13228 | macro_start (); |
67c0d1eb RS |
13229 | macro_build_lui (&ex, mips_gp_register); |
13230 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 13231 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
13232 | if (in_shared) |
13233 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
13234 | mips_gp_register, reg); | |
584892a6 | 13235 | macro_end (); |
252b5132 RH |
13236 | |
13237 | demand_empty_rest_of_line (); | |
13238 | } | |
13239 | ||
6478892d TS |
13240 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
13241 | .cpsetup $reg1, offset|$reg2, label | |
13242 | ||
13243 | If offset is given, this results in: | |
13244 | sd $gp, offset($sp) | |
956cd1d6 | 13245 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
13246 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
13247 | daddu $gp, $gp, $reg1 | |
6478892d TS |
13248 | |
13249 | If $reg2 is given, this results in: | |
13250 | daddu $reg2, $gp, $0 | |
956cd1d6 | 13251 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
13252 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
13253 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
13254 | $reg1 is normally $25 == $t9. |
13255 | ||
13256 | The -mno-shared option replaces the last three instructions with | |
13257 | lui $gp,%hi(_gp) | |
54f4ddb3 | 13258 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 13259 | |
6478892d | 13260 | static void |
17a2f251 | 13261 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13262 | { |
13263 | expressionS ex_off; | |
13264 | expressionS ex_sym; | |
13265 | int reg1; | |
6478892d | 13266 | |
8586fc66 | 13267 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
13268 | We also need NewABI support. */ |
13269 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13270 | { | |
13271 | s_ignore (0); | |
13272 | return; | |
13273 | } | |
13274 | ||
13275 | reg1 = tc_get_register (0); | |
13276 | SKIP_WHITESPACE (); | |
13277 | if (*input_line_pointer != ',') | |
13278 | { | |
13279 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
13280 | return; | |
13281 | } | |
13282 | else | |
80245285 | 13283 | ++input_line_pointer; |
6478892d TS |
13284 | SKIP_WHITESPACE (); |
13285 | if (*input_line_pointer == '$') | |
80245285 TS |
13286 | { |
13287 | mips_cpreturn_register = tc_get_register (0); | |
13288 | mips_cpreturn_offset = -1; | |
13289 | } | |
6478892d | 13290 | else |
80245285 TS |
13291 | { |
13292 | mips_cpreturn_offset = get_absolute_expression (); | |
13293 | mips_cpreturn_register = -1; | |
13294 | } | |
6478892d TS |
13295 | SKIP_WHITESPACE (); |
13296 | if (*input_line_pointer != ',') | |
13297 | { | |
13298 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
13299 | return; | |
13300 | } | |
13301 | else | |
f9419b05 | 13302 | ++input_line_pointer; |
6478892d | 13303 | SKIP_WHITESPACE (); |
f21f8242 | 13304 | expression (&ex_sym); |
6478892d | 13305 | |
584892a6 | 13306 | macro_start (); |
6478892d TS |
13307 | if (mips_cpreturn_register == -1) |
13308 | { | |
13309 | ex_off.X_op = O_constant; | |
13310 | ex_off.X_add_symbol = NULL; | |
13311 | ex_off.X_op_symbol = NULL; | |
13312 | ex_off.X_add_number = mips_cpreturn_offset; | |
13313 | ||
67c0d1eb | 13314 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 13315 | BFD_RELOC_LO16, SP); |
6478892d TS |
13316 | } |
13317 | else | |
67c0d1eb | 13318 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 13319 | mips_gp_register, 0); |
6478892d | 13320 | |
aed1a261 | 13321 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
13322 | { |
13323 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
13324 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
13325 | BFD_RELOC_HI16_S); | |
13326 | ||
13327 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
13328 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
13329 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
13330 | ||
13331 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
13332 | mips_gp_register, reg1); | |
13333 | } | |
13334 | else | |
13335 | { | |
13336 | expressionS ex; | |
13337 | ||
13338 | ex.X_op = O_symbol; | |
4184909a | 13339 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
13340 | ex.X_op_symbol = NULL; |
13341 | ex.X_add_number = 0; | |
6e1304d8 | 13342 | |
aa6975fb ILT |
13343 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
13344 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
13345 | ||
13346 | macro_build_lui (&ex, mips_gp_register); | |
13347 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
13348 | mips_gp_register, BFD_RELOC_LO16); | |
13349 | } | |
f21f8242 | 13350 | |
584892a6 | 13351 | macro_end (); |
6478892d TS |
13352 | |
13353 | demand_empty_rest_of_line (); | |
13354 | } | |
13355 | ||
13356 | static void | |
17a2f251 | 13357 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13358 | { |
13359 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 13360 | .cplocal is ignored. */ |
6478892d TS |
13361 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
13362 | { | |
13363 | s_ignore (0); | |
13364 | return; | |
13365 | } | |
13366 | ||
13367 | mips_gp_register = tc_get_register (0); | |
85b51719 | 13368 | demand_empty_rest_of_line (); |
6478892d TS |
13369 | } |
13370 | ||
252b5132 RH |
13371 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
13372 | offset from $sp. The offset is remembered, and after making a PIC | |
13373 | call $gp is restored from that location. */ | |
13374 | ||
13375 | static void | |
17a2f251 | 13376 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13377 | { |
13378 | expressionS ex; | |
252b5132 | 13379 | |
6478892d | 13380 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 13381 | .cprestore is ignored. */ |
6478892d | 13382 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
13383 | { |
13384 | s_ignore (0); | |
13385 | return; | |
13386 | } | |
13387 | ||
13388 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 13389 | mips_cprestore_valid = 1; |
252b5132 RH |
13390 | |
13391 | ex.X_op = O_constant; | |
13392 | ex.X_add_symbol = NULL; | |
13393 | ex.X_op_symbol = NULL; | |
13394 | ex.X_add_number = mips_cprestore_offset; | |
13395 | ||
584892a6 | 13396 | macro_start (); |
67c0d1eb RS |
13397 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
13398 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 13399 | macro_end (); |
252b5132 RH |
13400 | |
13401 | demand_empty_rest_of_line (); | |
13402 | } | |
13403 | ||
6478892d | 13404 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 13405 | was given in the preceding .cpsetup, it results in: |
6478892d | 13406 | ld $gp, offset($sp) |
76b3015f | 13407 | |
6478892d | 13408 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
13409 | daddu $gp, $reg2, $0 */ |
13410 | ||
6478892d | 13411 | static void |
17a2f251 | 13412 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13413 | { |
13414 | expressionS ex; | |
6478892d TS |
13415 | |
13416 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
13417 | We also need NewABI support. */ | |
13418 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13419 | { | |
13420 | s_ignore (0); | |
13421 | return; | |
13422 | } | |
13423 | ||
584892a6 | 13424 | macro_start (); |
6478892d TS |
13425 | if (mips_cpreturn_register == -1) |
13426 | { | |
13427 | ex.X_op = O_constant; | |
13428 | ex.X_add_symbol = NULL; | |
13429 | ex.X_op_symbol = NULL; | |
13430 | ex.X_add_number = mips_cpreturn_offset; | |
13431 | ||
67c0d1eb | 13432 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
13433 | } |
13434 | else | |
67c0d1eb | 13435 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 13436 | mips_cpreturn_register, 0); |
584892a6 | 13437 | macro_end (); |
6478892d TS |
13438 | |
13439 | demand_empty_rest_of_line (); | |
13440 | } | |
13441 | ||
741d6ea8 JM |
13442 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate |
13443 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
13444 | use in DWARF debug information. */ | |
13445 | ||
13446 | static void | |
13447 | s_dtprel_internal (size_t bytes) | |
13448 | { | |
13449 | expressionS ex; | |
13450 | char *p; | |
13451 | ||
13452 | expression (&ex); | |
13453 | ||
13454 | if (ex.X_op != O_symbol) | |
13455 | { | |
13456 | as_bad (_("Unsupported use of %s"), (bytes == 8 | |
13457 | ? ".dtpreldword" | |
13458 | : ".dtprelword")); | |
13459 | ignore_rest_of_line (); | |
13460 | } | |
13461 | ||
13462 | p = frag_more (bytes); | |
13463 | md_number_to_chars (p, 0, bytes); | |
13464 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, | |
13465 | (bytes == 8 | |
13466 | ? BFD_RELOC_MIPS_TLS_DTPREL64 | |
13467 | : BFD_RELOC_MIPS_TLS_DTPREL32)); | |
13468 | ||
13469 | demand_empty_rest_of_line (); | |
13470 | } | |
13471 | ||
13472 | /* Handle .dtprelword. */ | |
13473 | ||
13474 | static void | |
13475 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
13476 | { | |
13477 | s_dtprel_internal (4); | |
13478 | } | |
13479 | ||
13480 | /* Handle .dtpreldword. */ | |
13481 | ||
13482 | static void | |
13483 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
13484 | { | |
13485 | s_dtprel_internal (8); | |
13486 | } | |
13487 | ||
6478892d TS |
13488 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
13489 | code. It sets the offset to use in gp_rel relocations. */ | |
13490 | ||
13491 | static void | |
17a2f251 | 13492 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13493 | { |
13494 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
13495 | We also need NewABI support. */ | |
13496 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13497 | { | |
13498 | s_ignore (0); | |
13499 | return; | |
13500 | } | |
13501 | ||
def2e0dd | 13502 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
13503 | |
13504 | demand_empty_rest_of_line (); | |
13505 | } | |
13506 | ||
252b5132 RH |
13507 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
13508 | code. It generates a 32 bit GP relative reloc. */ | |
13509 | ||
13510 | static void | |
17a2f251 | 13511 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13512 | { |
a8dbcb85 TS |
13513 | segment_info_type *si; |
13514 | struct insn_label_list *l; | |
252b5132 RH |
13515 | symbolS *label; |
13516 | expressionS ex; | |
13517 | char *p; | |
13518 | ||
13519 | /* When not generating PIC code, this is treated as .word. */ | |
13520 | if (mips_pic != SVR4_PIC) | |
13521 | { | |
13522 | s_cons (2); | |
13523 | return; | |
13524 | } | |
13525 | ||
a8dbcb85 TS |
13526 | si = seg_info (now_seg); |
13527 | l = si->label_list; | |
13528 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13529 | mips_emit_delays (); |
252b5132 RH |
13530 | if (auto_align) |
13531 | mips_align (2, 0, label); | |
13532 | mips_clear_insn_labels (); | |
13533 | ||
13534 | expression (&ex); | |
13535 | ||
13536 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13537 | { | |
13538 | as_bad (_("Unsupported use of .gpword")); | |
13539 | ignore_rest_of_line (); | |
13540 | } | |
13541 | ||
13542 | p = frag_more (4); | |
17a2f251 | 13543 | md_number_to_chars (p, 0, 4); |
b34976b6 | 13544 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 13545 | BFD_RELOC_GPREL32); |
252b5132 RH |
13546 | |
13547 | demand_empty_rest_of_line (); | |
13548 | } | |
13549 | ||
10181a0d | 13550 | static void |
17a2f251 | 13551 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 13552 | { |
a8dbcb85 TS |
13553 | segment_info_type *si; |
13554 | struct insn_label_list *l; | |
10181a0d AO |
13555 | symbolS *label; |
13556 | expressionS ex; | |
13557 | char *p; | |
13558 | ||
13559 | /* When not generating PIC code, this is treated as .dword. */ | |
13560 | if (mips_pic != SVR4_PIC) | |
13561 | { | |
13562 | s_cons (3); | |
13563 | return; | |
13564 | } | |
13565 | ||
a8dbcb85 TS |
13566 | si = seg_info (now_seg); |
13567 | l = si->label_list; | |
13568 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13569 | mips_emit_delays (); |
10181a0d AO |
13570 | if (auto_align) |
13571 | mips_align (3, 0, label); | |
13572 | mips_clear_insn_labels (); | |
13573 | ||
13574 | expression (&ex); | |
13575 | ||
13576 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13577 | { | |
13578 | as_bad (_("Unsupported use of .gpdword")); | |
13579 | ignore_rest_of_line (); | |
13580 | } | |
13581 | ||
13582 | p = frag_more (8); | |
17a2f251 | 13583 | md_number_to_chars (p, 0, 8); |
a105a300 | 13584 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 13585 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
13586 | |
13587 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
13588 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
13589 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
13590 | |
13591 | demand_empty_rest_of_line (); | |
13592 | } | |
13593 | ||
252b5132 RH |
13594 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
13595 | tables in SVR4 PIC code. */ | |
13596 | ||
13597 | static void | |
17a2f251 | 13598 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13599 | { |
252b5132 RH |
13600 | int reg; |
13601 | ||
10181a0d AO |
13602 | /* This is ignored when not generating SVR4 PIC code. */ |
13603 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
13604 | { |
13605 | s_ignore (0); | |
13606 | return; | |
13607 | } | |
13608 | ||
13609 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 13610 | macro_start (); |
252b5132 | 13611 | reg = tc_get_register (0); |
67c0d1eb | 13612 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 13613 | macro_end (); |
252b5132 | 13614 | |
bdaaa2e1 | 13615 | demand_empty_rest_of_line (); |
252b5132 RH |
13616 | } |
13617 | ||
13618 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
13619 | mips16 mode. This permits the linker to handle them specially, | |
13620 | such as generating jalx instructions when needed. We also make | |
13621 | them odd for the duration of the assembly, in order to generate the | |
13622 | right sort of code. We will make them even in the adjust_symtab | |
13623 | routine, while leaving them marked. This is convenient for the | |
13624 | debugger and the disassembler. The linker knows to make them odd | |
13625 | again. */ | |
13626 | ||
13627 | static void | |
17a2f251 | 13628 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13629 | { |
f9419b05 | 13630 | mips16_mark_labels (); |
252b5132 RH |
13631 | |
13632 | demand_empty_rest_of_line (); | |
13633 | } | |
13634 | ||
13635 | /* Handle a .stabn directive. We need these in order to mark a label | |
13636 | as being a mips16 text label correctly. Sometimes the compiler | |
13637 | will emit a label, followed by a .stabn, and then switch sections. | |
13638 | If the label and .stabn are in mips16 mode, then the label is | |
13639 | really a mips16 text label. */ | |
13640 | ||
13641 | static void | |
17a2f251 | 13642 | s_mips_stab (int type) |
252b5132 | 13643 | { |
f9419b05 | 13644 | if (type == 'n') |
252b5132 RH |
13645 | mips16_mark_labels (); |
13646 | ||
13647 | s_stab (type); | |
13648 | } | |
13649 | ||
54f4ddb3 | 13650 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
13651 | |
13652 | static void | |
17a2f251 | 13653 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13654 | { |
13655 | char *name; | |
13656 | int c; | |
13657 | symbolS *symbolP; | |
13658 | expressionS exp; | |
13659 | ||
13660 | name = input_line_pointer; | |
13661 | c = get_symbol_end (); | |
13662 | symbolP = symbol_find_or_make (name); | |
13663 | S_SET_WEAK (symbolP); | |
13664 | *input_line_pointer = c; | |
13665 | ||
13666 | SKIP_WHITESPACE (); | |
13667 | ||
13668 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
13669 | { | |
13670 | if (S_IS_DEFINED (symbolP)) | |
13671 | { | |
20203fb9 | 13672 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
13673 | S_GET_NAME (symbolP)); |
13674 | ignore_rest_of_line (); | |
13675 | return; | |
13676 | } | |
bdaaa2e1 | 13677 | |
252b5132 RH |
13678 | if (*input_line_pointer == ',') |
13679 | { | |
13680 | ++input_line_pointer; | |
13681 | SKIP_WHITESPACE (); | |
13682 | } | |
bdaaa2e1 | 13683 | |
252b5132 RH |
13684 | expression (&exp); |
13685 | if (exp.X_op != O_symbol) | |
13686 | { | |
20203fb9 | 13687 | as_bad (_("bad .weakext directive")); |
98d3f06f | 13688 | ignore_rest_of_line (); |
252b5132 RH |
13689 | return; |
13690 | } | |
49309057 | 13691 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
13692 | } |
13693 | ||
13694 | demand_empty_rest_of_line (); | |
13695 | } | |
13696 | ||
13697 | /* Parse a register string into a number. Called from the ECOFF code | |
13698 | to parse .frame. The argument is non-zero if this is the frame | |
13699 | register, so that we can record it in mips_frame_reg. */ | |
13700 | ||
13701 | int | |
17a2f251 | 13702 | tc_get_register (int frame) |
252b5132 | 13703 | { |
707bfff6 | 13704 | unsigned int reg; |
252b5132 RH |
13705 | |
13706 | SKIP_WHITESPACE (); | |
707bfff6 TS |
13707 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
13708 | reg = 0; | |
252b5132 | 13709 | if (frame) |
7a621144 DJ |
13710 | { |
13711 | mips_frame_reg = reg != 0 ? reg : SP; | |
13712 | mips_frame_reg_valid = 1; | |
13713 | mips_cprestore_valid = 0; | |
13714 | } | |
252b5132 RH |
13715 | return reg; |
13716 | } | |
13717 | ||
13718 | valueT | |
17a2f251 | 13719 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
13720 | { |
13721 | int align = bfd_get_section_alignment (stdoutput, seg); | |
13722 | ||
b4c71f56 TS |
13723 | if (IS_ELF) |
13724 | { | |
13725 | /* We don't need to align ELF sections to the full alignment. | |
13726 | However, Irix 5 may prefer that we align them at least to a 16 | |
13727 | byte boundary. We don't bother to align the sections if we | |
13728 | are targeted for an embedded system. */ | |
c41e87e3 | 13729 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
13730 | return addr; |
13731 | if (align > 4) | |
13732 | align = 4; | |
13733 | } | |
252b5132 RH |
13734 | |
13735 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
13736 | } | |
13737 | ||
13738 | /* Utility routine, called from above as well. If called while the | |
13739 | input file is still being read, it's only an approximation. (For | |
13740 | example, a symbol may later become defined which appeared to be | |
13741 | undefined earlier.) */ | |
13742 | ||
13743 | static int | |
17a2f251 | 13744 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
13745 | { |
13746 | if (sym == 0) | |
13747 | return 0; | |
13748 | ||
4d0d148d | 13749 | if (g_switch_value > 0) |
252b5132 RH |
13750 | { |
13751 | const char *symname; | |
13752 | int change; | |
13753 | ||
c9914766 | 13754 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
13755 | register. It can be if it is smaller than the -G size or if |
13756 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 13757 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
13758 | they can. */ |
13759 | symname = S_GET_NAME (sym); | |
13760 | if (symname != (const char *) NULL | |
13761 | && (strcmp (symname, "eprol") == 0 | |
13762 | || strcmp (symname, "etext") == 0 | |
13763 | || strcmp (symname, "_gp") == 0 | |
13764 | || strcmp (symname, "edata") == 0 | |
13765 | || strcmp (symname, "_fbss") == 0 | |
13766 | || strcmp (symname, "_fdata") == 0 | |
13767 | || strcmp (symname, "_ftext") == 0 | |
13768 | || strcmp (symname, "end") == 0 | |
13769 | || strcmp (symname, "_gp_disp") == 0)) | |
13770 | change = 1; | |
13771 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
13772 | && (0 | |
13773 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
13774 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
13775 | && (symbol_get_obj (sym)->ecoff_extern_size | |
13776 | <= g_switch_value)) | |
252b5132 RH |
13777 | #endif |
13778 | /* We must defer this decision until after the whole | |
13779 | file has been read, since there might be a .extern | |
13780 | after the first use of this symbol. */ | |
13781 | || (before_relaxing | |
13782 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 13783 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
13784 | #endif |
13785 | && S_GET_VALUE (sym) == 0) | |
13786 | || (S_GET_VALUE (sym) != 0 | |
13787 | && S_GET_VALUE (sym) <= g_switch_value))) | |
13788 | change = 0; | |
13789 | else | |
13790 | { | |
13791 | const char *segname; | |
13792 | ||
13793 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 13794 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
13795 | && strcmp (segname, ".lit4") != 0); |
13796 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
13797 | && strcmp (segname, ".sbss") != 0 |
13798 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
13799 | && strncmp (segname, ".sbss.", 6) != 0 |
13800 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 13801 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
13802 | } |
13803 | return change; | |
13804 | } | |
13805 | else | |
c9914766 | 13806 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
13807 | return 1; |
13808 | } | |
13809 | ||
5919d012 RS |
13810 | |
13811 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
13812 | ||
13813 | static bfd_boolean | |
17a2f251 | 13814 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
13815 | { |
13816 | asection *symsec; | |
5919d012 RS |
13817 | |
13818 | /* Handle the case of a symbol equated to another symbol. */ | |
13819 | while (symbol_equated_reloc_p (sym)) | |
13820 | { | |
13821 | symbolS *n; | |
13822 | ||
5f0fe04b | 13823 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
13824 | n = symbol_get_value_expression (sym)->X_add_symbol; |
13825 | if (n == sym) | |
13826 | break; | |
13827 | sym = n; | |
13828 | } | |
13829 | ||
df1f3cda DD |
13830 | if (symbol_section_p (sym)) |
13831 | return TRUE; | |
13832 | ||
5919d012 RS |
13833 | symsec = S_GET_SEGMENT (sym); |
13834 | ||
5919d012 RS |
13835 | /* This must duplicate the test in adjust_reloc_syms. */ |
13836 | return (symsec != &bfd_und_section | |
13837 | && symsec != &bfd_abs_section | |
5f0fe04b TS |
13838 | && !bfd_is_com_section (symsec) |
13839 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
13840 | #ifdef OBJ_ELF |
13841 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 13842 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
13843 | #endif |
13844 | ); | |
13845 | } | |
13846 | ||
13847 | ||
252b5132 RH |
13848 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
13849 | extended opcode. SEC is the section the frag is in. */ | |
13850 | ||
13851 | static int | |
17a2f251 | 13852 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
13853 | { |
13854 | int type; | |
3994f87e | 13855 | const struct mips16_immed_operand *op; |
252b5132 RH |
13856 | offsetT val; |
13857 | int mintiny, maxtiny; | |
13858 | segT symsec; | |
98aa84af | 13859 | fragS *sym_frag; |
252b5132 RH |
13860 | |
13861 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
13862 | return 0; | |
13863 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
13864 | return 1; | |
13865 | ||
13866 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13867 | op = mips16_immed_operands; | |
13868 | while (op->type != type) | |
13869 | { | |
13870 | ++op; | |
9c2799c2 | 13871 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
13872 | } |
13873 | ||
13874 | if (op->unsp) | |
13875 | { | |
13876 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13877 | { | |
13878 | mintiny = 1; | |
13879 | maxtiny = 1 << op->nbits; | |
13880 | } | |
13881 | else | |
13882 | { | |
13883 | mintiny = 0; | |
13884 | maxtiny = (1 << op->nbits) - 1; | |
13885 | } | |
13886 | } | |
13887 | else | |
13888 | { | |
13889 | mintiny = - (1 << (op->nbits - 1)); | |
13890 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13891 | } | |
13892 | ||
98aa84af | 13893 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 13894 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 13895 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
13896 | |
13897 | if (op->pcrel) | |
13898 | { | |
13899 | addressT addr; | |
13900 | ||
13901 | /* We won't have the section when we are called from | |
13902 | mips_relax_frag. However, we will always have been called | |
13903 | from md_estimate_size_before_relax first. If this is a | |
13904 | branch to a different section, we mark it as such. If SEC is | |
13905 | NULL, and the frag is not marked, then it must be a branch to | |
13906 | the same section. */ | |
13907 | if (sec == NULL) | |
13908 | { | |
13909 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
13910 | return 1; | |
13911 | } | |
13912 | else | |
13913 | { | |
98aa84af | 13914 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
13915 | if (symsec != sec) |
13916 | { | |
13917 | fragp->fr_subtype = | |
13918 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13919 | ||
13920 | /* FIXME: We should support this, and let the linker | |
13921 | catch branches and loads that are out of range. */ | |
13922 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
13923 | _("unsupported PC relative reference to different section")); | |
13924 | ||
13925 | return 1; | |
13926 | } | |
98aa84af AM |
13927 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
13928 | /* Assume non-extended on the first relaxation pass. | |
13929 | The address we have calculated will be bogus if this is | |
13930 | a forward branch to another frag, as the forward frag | |
13931 | will have fr_address == 0. */ | |
13932 | return 0; | |
252b5132 RH |
13933 | } |
13934 | ||
13935 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
13936 | the same section. If the relax_marker of the symbol fragment |
13937 | differs from the relax_marker of this fragment, we have not | |
13938 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
13939 | in STRETCH in order to get a better estimate of the address. |
13940 | This particularly matters because of the shift bits. */ | |
13941 | if (stretch != 0 | |
98aa84af | 13942 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
13943 | { |
13944 | fragS *f; | |
13945 | ||
13946 | /* Adjust stretch for any alignment frag. Note that if have | |
13947 | been expanding the earlier code, the symbol may be | |
13948 | defined in what appears to be an earlier frag. FIXME: | |
13949 | This doesn't handle the fr_subtype field, which specifies | |
13950 | a maximum number of bytes to skip when doing an | |
13951 | alignment. */ | |
98aa84af | 13952 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
13953 | { |
13954 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
13955 | { | |
13956 | if (stretch < 0) | |
13957 | stretch = - ((- stretch) | |
13958 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
13959 | else | |
13960 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
13961 | if (stretch == 0) | |
13962 | break; | |
13963 | } | |
13964 | } | |
13965 | if (f != NULL) | |
13966 | val += stretch; | |
13967 | } | |
13968 | ||
13969 | addr = fragp->fr_address + fragp->fr_fix; | |
13970 | ||
13971 | /* The base address rules are complicated. The base address of | |
13972 | a branch is the following instruction. The base address of a | |
13973 | PC relative load or add is the instruction itself, but if it | |
13974 | is in a delay slot (in which case it can not be extended) use | |
13975 | the address of the instruction whose delay slot it is in. */ | |
13976 | if (type == 'p' || type == 'q') | |
13977 | { | |
13978 | addr += 2; | |
13979 | ||
13980 | /* If we are currently assuming that this frag should be | |
13981 | extended, then, the current address is two bytes | |
bdaaa2e1 | 13982 | higher. */ |
252b5132 RH |
13983 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
13984 | addr += 2; | |
13985 | ||
13986 | /* Ignore the low bit in the target, since it will be set | |
13987 | for a text label. */ | |
13988 | if ((val & 1) != 0) | |
13989 | --val; | |
13990 | } | |
13991 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13992 | addr -= 4; | |
13993 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13994 | addr -= 2; | |
13995 | ||
13996 | val -= addr & ~ ((1 << op->shift) - 1); | |
13997 | ||
13998 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
13999 | if (type == 'p' || type == 'q') | |
14000 | val /= 2; | |
14001 | ||
14002 | /* If any of the shifted bits are set, we must use an extended | |
14003 | opcode. If the address depends on the size of this | |
14004 | instruction, this can lead to a loop, so we arrange to always | |
14005 | use an extended opcode. We only check this when we are in | |
14006 | the main relaxation loop, when SEC is NULL. */ | |
14007 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
14008 | { | |
14009 | fragp->fr_subtype = | |
14010 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
14011 | return 1; | |
14012 | } | |
14013 | ||
14014 | /* If we are about to mark a frag as extended because the value | |
14015 | is precisely maxtiny + 1, then there is a chance of an | |
14016 | infinite loop as in the following code: | |
14017 | la $4,foo | |
14018 | .skip 1020 | |
14019 | .align 2 | |
14020 | foo: | |
14021 | In this case when the la is extended, foo is 0x3fc bytes | |
14022 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
14023 | the la must be extended. To avoid this loop, we mark the | |
14024 | frag as extended if it was small, and is about to become | |
14025 | extended with a value of maxtiny + 1. */ | |
14026 | if (val == ((maxtiny + 1) << op->shift) | |
14027 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
14028 | && sec == NULL) | |
14029 | { | |
14030 | fragp->fr_subtype = | |
14031 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
14032 | return 1; | |
14033 | } | |
14034 | } | |
14035 | else if (symsec != absolute_section && sec != NULL) | |
14036 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
14037 | ||
14038 | if ((val & ((1 << op->shift) - 1)) != 0 | |
14039 | || val < (mintiny << op->shift) | |
14040 | || val > (maxtiny << op->shift)) | |
14041 | return 1; | |
14042 | else | |
14043 | return 0; | |
14044 | } | |
14045 | ||
4a6a3df4 AO |
14046 | /* Compute the length of a branch sequence, and adjust the |
14047 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
14048 | worst-case length is computed, with UPDATE being used to indicate | |
14049 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
14050 | branch is to be computed. */ | |
14051 | static int | |
17a2f251 | 14052 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 14053 | { |
b34976b6 | 14054 | bfd_boolean toofar; |
4a6a3df4 AO |
14055 | int length; |
14056 | ||
14057 | if (fragp | |
14058 | && S_IS_DEFINED (fragp->fr_symbol) | |
14059 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
14060 | { | |
14061 | addressT addr; | |
14062 | offsetT val; | |
14063 | ||
14064 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
14065 | ||
14066 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
14067 | ||
14068 | val -= addr; | |
14069 | ||
14070 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
14071 | } | |
14072 | else if (fragp) | |
14073 | /* If the symbol is not defined or it's in a different segment, | |
14074 | assume the user knows what's going on and emit a short | |
14075 | branch. */ | |
b34976b6 | 14076 | toofar = FALSE; |
4a6a3df4 | 14077 | else |
b34976b6 | 14078 | toofar = TRUE; |
4a6a3df4 AO |
14079 | |
14080 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
14081 | fragp->fr_subtype | |
af6ae2ad | 14082 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
14083 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
14084 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
14085 | toofar); | |
14086 | ||
14087 | length = 4; | |
14088 | if (toofar) | |
14089 | { | |
14090 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
14091 | length += 8; | |
14092 | ||
14093 | if (mips_pic != NO_PIC) | |
14094 | { | |
14095 | /* Additional space for PIC loading of target address. */ | |
14096 | length += 8; | |
14097 | if (mips_opts.isa == ISA_MIPS1) | |
14098 | /* Additional space for $at-stabilizing nop. */ | |
14099 | length += 4; | |
14100 | } | |
14101 | ||
14102 | /* If branch is conditional. */ | |
14103 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
14104 | length += 8; | |
14105 | } | |
b34976b6 | 14106 | |
4a6a3df4 AO |
14107 | return length; |
14108 | } | |
14109 | ||
252b5132 RH |
14110 | /* Estimate the size of a frag before relaxing. Unless this is the |
14111 | mips16, we are not really relaxing here, and the final size is | |
14112 | encoded in the subtype information. For the mips16, we have to | |
14113 | decide whether we are using an extended opcode or not. */ | |
14114 | ||
252b5132 | 14115 | int |
17a2f251 | 14116 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 14117 | { |
5919d012 | 14118 | int change; |
252b5132 | 14119 | |
4a6a3df4 AO |
14120 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14121 | { | |
14122 | ||
b34976b6 AM |
14123 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
14124 | ||
4a6a3df4 AO |
14125 | return fragp->fr_var; |
14126 | } | |
14127 | ||
252b5132 | 14128 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
14129 | /* We don't want to modify the EXTENDED bit here; it might get us |
14130 | into infinite loops. We change it only in mips_relax_frag(). */ | |
14131 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
14132 | |
14133 | if (mips_pic == NO_PIC) | |
5919d012 | 14134 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 14135 | else if (mips_pic == SVR4_PIC) |
5919d012 | 14136 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
14137 | else if (mips_pic == VXWORKS_PIC) |
14138 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
14139 | change = 0; | |
252b5132 RH |
14140 | else |
14141 | abort (); | |
14142 | ||
14143 | if (change) | |
14144 | { | |
4d7206a2 | 14145 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 14146 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 14147 | } |
4d7206a2 RS |
14148 | else |
14149 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
14150 | } |
14151 | ||
14152 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 14153 | should be converted into a reloc against a section. */ |
252b5132 RH |
14154 | |
14155 | int | |
17a2f251 | 14156 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 14157 | { |
252b5132 RH |
14158 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
14159 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
14160 | return 0; | |
a161fe53 | 14161 | |
252b5132 RH |
14162 | if (fixp->fx_addsy == NULL) |
14163 | return 1; | |
a161fe53 | 14164 | |
de7e6852 RS |
14165 | /* If symbol SYM is in a mergeable section, relocations of the form |
14166 | SYM + 0 can usually be made section-relative. The mergeable data | |
14167 | is then identified by the section offset rather than by the symbol. | |
14168 | ||
14169 | However, if we're generating REL LO16 relocations, the offset is split | |
14170 | between the LO16 and parterning high part relocation. The linker will | |
14171 | need to recalculate the complete offset in order to correctly identify | |
14172 | the merge data. | |
14173 | ||
14174 | The linker has traditionally not looked for the parterning high part | |
14175 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
14176 | placed anywhere. Rather than break backwards compatibility by changing | |
14177 | this, it seems better not to force the issue, and instead keep the | |
14178 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 14179 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 14180 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
14181 | && HAVE_IN_PLACE_ADDENDS |
14182 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
14183 | return 0; | |
14184 | ||
1180b5a4 RS |
14185 | /* There is no place to store an in-place offset for JALR relocations. */ |
14186 | if (fixp->fx_r_type == BFD_RELOC_MIPS_JALR && HAVE_IN_PLACE_ADDENDS) | |
14187 | return 0; | |
14188 | ||
252b5132 | 14189 | #ifdef OBJ_ELF |
b314ec0e RS |
14190 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
14191 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
14192 | relocations against MIPS16 functions; in this case, the stub becomes | |
14193 | the function's canonical address. | |
14194 | ||
14195 | Floating-point stubs are stored in unique .mips16.call.* or | |
14196 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
14197 | the first relocation in section S must be against F; this is how the | |
14198 | linker determines the target function. All relocations that might | |
14199 | resolve to T must also be against F. We therefore have the following | |
14200 | restrictions, which are given in an intentionally-redundant way: | |
14201 | ||
14202 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
14203 | symbols. | |
14204 | ||
14205 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
14206 | if that stub might be used. | |
14207 | ||
14208 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
14209 | symbols. | |
14210 | ||
14211 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
14212 | that stub might be used. | |
14213 | ||
14214 | There is a further restriction: | |
14215 | ||
14216 | 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols | |
14217 | on targets with in-place addends; the relocation field cannot | |
14218 | encode the low bit. | |
14219 | ||
14220 | For simplicity, we deal with (3)-(5) by not reducing _any_ relocation | |
14221 | against a MIPS16 symbol. | |
14222 | ||
14223 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
14224 | relocation against some symbol R, no relocation against R may be | |
14225 | reduced. (Note that this deals with (2) as well as (1) because | |
14226 | relocations against global symbols will never be reduced on ELF | |
14227 | targets.) This approach is a little simpler than trying to detect | |
14228 | stub sections, and gives the "all or nothing" per-symbol consistency | |
14229 | that we have for MIPS16 symbols. */ | |
f43abd2b | 14230 | if (IS_ELF |
b314ec0e | 14231 | && fixp->fx_subsy == NULL |
30c09090 | 14232 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
b314ec0e | 14233 | || *symbol_get_tc (fixp->fx_addsy))) |
252b5132 RH |
14234 | return 0; |
14235 | #endif | |
a161fe53 | 14236 | |
252b5132 RH |
14237 | return 1; |
14238 | } | |
14239 | ||
14240 | /* Translate internal representation of relocation info to BFD target | |
14241 | format. */ | |
14242 | ||
14243 | arelent ** | |
17a2f251 | 14244 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
14245 | { |
14246 | static arelent *retval[4]; | |
14247 | arelent *reloc; | |
14248 | bfd_reloc_code_real_type code; | |
14249 | ||
4b0cff4e TS |
14250 | memset (retval, 0, sizeof(retval)); |
14251 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
14252 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
14253 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
14254 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
14255 | ||
bad36eac DJ |
14256 | if (fixp->fx_pcrel) |
14257 | { | |
9c2799c2 | 14258 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2); |
bad36eac DJ |
14259 | |
14260 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
14261 | Relocations want only the symbol offset. */ | |
14262 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 14263 | if (!IS_ELF) |
bad36eac DJ |
14264 | { |
14265 | /* A gruesome hack which is a result of the gruesome gas | |
14266 | reloc handling. What's worse, for COFF (as opposed to | |
14267 | ECOFF), we might need yet another copy of reloc->address. | |
14268 | See bfd_install_relocation. */ | |
14269 | reloc->addend += reloc->address; | |
14270 | } | |
14271 | } | |
14272 | else | |
14273 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 14274 | |
438c16b8 TS |
14275 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
14276 | entry to be used in the relocation's section offset. */ | |
14277 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
14278 | { |
14279 | reloc->address = reloc->addend; | |
14280 | reloc->addend = 0; | |
14281 | } | |
14282 | ||
252b5132 | 14283 | code = fixp->fx_r_type; |
252b5132 | 14284 | |
bad36eac | 14285 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
14286 | if (reloc->howto == NULL) |
14287 | { | |
14288 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14289 | _("Can not represent %s relocation in this object file format"), | |
14290 | bfd_get_reloc_code_name (code)); | |
14291 | retval[0] = NULL; | |
14292 | } | |
14293 | ||
14294 | return retval; | |
14295 | } | |
14296 | ||
14297 | /* Relax a machine dependent frag. This returns the amount by which | |
14298 | the current size of the frag should change. */ | |
14299 | ||
14300 | int | |
17a2f251 | 14301 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 14302 | { |
4a6a3df4 AO |
14303 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14304 | { | |
14305 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
14306 | |
14307 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
14308 | |
14309 | return fragp->fr_var - old_var; | |
14310 | } | |
14311 | ||
252b5132 RH |
14312 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
14313 | return 0; | |
14314 | ||
c4e7957c | 14315 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
14316 | { |
14317 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14318 | return 0; | |
14319 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
14320 | return 2; | |
14321 | } | |
14322 | else | |
14323 | { | |
14324 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14325 | return 0; | |
14326 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
14327 | return -2; | |
14328 | } | |
14329 | ||
14330 | return 0; | |
14331 | } | |
14332 | ||
14333 | /* Convert a machine dependent frag. */ | |
14334 | ||
14335 | void | |
17a2f251 | 14336 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 14337 | { |
4a6a3df4 AO |
14338 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14339 | { | |
14340 | bfd_byte *buf; | |
14341 | unsigned long insn; | |
14342 | expressionS exp; | |
14343 | fixS *fixp; | |
b34976b6 | 14344 | |
4a6a3df4 AO |
14345 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
14346 | ||
14347 | if (target_big_endian) | |
14348 | insn = bfd_getb32 (buf); | |
14349 | else | |
14350 | insn = bfd_getl32 (buf); | |
b34976b6 | 14351 | |
4a6a3df4 AO |
14352 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
14353 | { | |
14354 | /* We generate a fixup instead of applying it right now | |
14355 | because, if there are linker relaxations, we're going to | |
14356 | need the relocations. */ | |
14357 | exp.X_op = O_symbol; | |
14358 | exp.X_add_symbol = fragp->fr_symbol; | |
14359 | exp.X_add_number = fragp->fr_offset; | |
14360 | ||
14361 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14362 | 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
14363 | fixp->fx_file = fragp->fr_file; |
14364 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14365 | |
2132e3a3 | 14366 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14367 | buf += 4; |
14368 | } | |
14369 | else | |
14370 | { | |
14371 | int i; | |
14372 | ||
14373 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
14374 | _("relaxed out-of-range branch into a jump")); | |
14375 | ||
14376 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
14377 | goto uncond; | |
14378 | ||
14379 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14380 | { | |
14381 | /* Reverse the branch. */ | |
14382 | switch ((insn >> 28) & 0xf) | |
14383 | { | |
14384 | case 4: | |
14385 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
14386 | have the condition reversed by tweaking a single | |
14387 | bit, and their opcodes all have 0x4???????. */ | |
9c2799c2 | 14388 | gas_assert ((insn & 0xf1000000) == 0x41000000); |
4a6a3df4 AO |
14389 | insn ^= 0x00010000; |
14390 | break; | |
14391 | ||
14392 | case 0: | |
14393 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 14394 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 14395 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
14396 | insn ^= 0x00010000; |
14397 | break; | |
b34976b6 | 14398 | |
4a6a3df4 AO |
14399 | case 1: |
14400 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 14401 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
14402 | insn ^= 0x04000000; |
14403 | break; | |
14404 | ||
14405 | default: | |
14406 | abort (); | |
14407 | } | |
14408 | } | |
14409 | ||
14410 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
14411 | { | |
14412 | /* Clear the and-link bit. */ | |
9c2799c2 | 14413 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 14414 | |
54f4ddb3 TS |
14415 | /* bltzal 0x04100000 bgezal 0x04110000 |
14416 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
14417 | insn &= ~0x00100000; |
14418 | } | |
14419 | ||
14420 | /* Branch over the branch (if the branch was likely) or the | |
14421 | full jump (not likely case). Compute the offset from the | |
14422 | current instruction to branch to. */ | |
14423 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14424 | i = 16; | |
14425 | else | |
14426 | { | |
14427 | /* How many bytes in instructions we've already emitted? */ | |
14428 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
14429 | /* How many bytes in instructions from here to the end? */ | |
14430 | i = fragp->fr_var - i; | |
14431 | } | |
14432 | /* Convert to instruction count. */ | |
14433 | i >>= 2; | |
14434 | /* Branch counts from the next instruction. */ | |
b34976b6 | 14435 | i--; |
4a6a3df4 AO |
14436 | insn |= i; |
14437 | /* Branch over the jump. */ | |
2132e3a3 | 14438 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14439 | buf += 4; |
14440 | ||
54f4ddb3 | 14441 | /* nop */ |
2132e3a3 | 14442 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14443 | buf += 4; |
14444 | ||
14445 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14446 | { | |
14447 | /* beql $0, $0, 2f */ | |
14448 | insn = 0x50000000; | |
14449 | /* Compute the PC offset from the current instruction to | |
14450 | the end of the variable frag. */ | |
14451 | /* How many bytes in instructions we've already emitted? */ | |
14452 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
14453 | /* How many bytes in instructions from here to the end? */ | |
14454 | i = fragp->fr_var - i; | |
14455 | /* Convert to instruction count. */ | |
14456 | i >>= 2; | |
14457 | /* Don't decrement i, because we want to branch over the | |
14458 | delay slot. */ | |
14459 | ||
14460 | insn |= i; | |
2132e3a3 | 14461 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14462 | buf += 4; |
14463 | ||
2132e3a3 | 14464 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14465 | buf += 4; |
14466 | } | |
14467 | ||
14468 | uncond: | |
14469 | if (mips_pic == NO_PIC) | |
14470 | { | |
14471 | /* j or jal. */ | |
14472 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
14473 | ? 0x0c000000 : 0x08000000); | |
14474 | exp.X_op = O_symbol; | |
14475 | exp.X_add_symbol = fragp->fr_symbol; | |
14476 | exp.X_add_number = fragp->fr_offset; | |
14477 | ||
14478 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14479 | 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); |
4a6a3df4 AO |
14480 | fixp->fx_file = fragp->fr_file; |
14481 | fixp->fx_line = fragp->fr_line; | |
14482 | ||
2132e3a3 | 14483 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14484 | buf += 4; |
14485 | } | |
14486 | else | |
14487 | { | |
14488 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
14489 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
14490 | exp.X_op = O_symbol; | |
14491 | exp.X_add_symbol = fragp->fr_symbol; | |
14492 | exp.X_add_number = fragp->fr_offset; | |
14493 | ||
14494 | if (fragp->fr_offset) | |
14495 | { | |
14496 | exp.X_add_symbol = make_expr_symbol (&exp); | |
14497 | exp.X_add_number = 0; | |
14498 | } | |
14499 | ||
14500 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14501 | 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16); |
4a6a3df4 AO |
14502 | fixp->fx_file = fragp->fr_file; |
14503 | fixp->fx_line = fragp->fr_line; | |
14504 | ||
2132e3a3 | 14505 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 14506 | buf += 4; |
b34976b6 | 14507 | |
4a6a3df4 AO |
14508 | if (mips_opts.isa == ISA_MIPS1) |
14509 | { | |
14510 | /* nop */ | |
2132e3a3 | 14511 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14512 | buf += 4; |
14513 | } | |
14514 | ||
14515 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
14516 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
14517 | ||
14518 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14519 | 4, &exp, FALSE, BFD_RELOC_LO16); |
4a6a3df4 AO |
14520 | fixp->fx_file = fragp->fr_file; |
14521 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14522 | |
2132e3a3 | 14523 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14524 | buf += 4; |
14525 | ||
14526 | /* j(al)r $at. */ | |
14527 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
14528 | insn = 0x0020f809; | |
14529 | else | |
14530 | insn = 0x00200008; | |
14531 | ||
2132e3a3 | 14532 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14533 | buf += 4; |
14534 | } | |
14535 | } | |
14536 | ||
9c2799c2 | 14537 | gas_assert (buf == (bfd_byte *)fragp->fr_literal |
4a6a3df4 AO |
14538 | + fragp->fr_fix + fragp->fr_var); |
14539 | ||
14540 | fragp->fr_fix += fragp->fr_var; | |
14541 | ||
14542 | return; | |
14543 | } | |
14544 | ||
252b5132 RH |
14545 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
14546 | { | |
14547 | int type; | |
3994f87e | 14548 | const struct mips16_immed_operand *op; |
b34976b6 | 14549 | bfd_boolean small, ext; |
252b5132 RH |
14550 | offsetT val; |
14551 | bfd_byte *buf; | |
14552 | unsigned long insn; | |
b34976b6 | 14553 | bfd_boolean use_extend; |
252b5132 RH |
14554 | unsigned short extend; |
14555 | ||
14556 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
14557 | op = mips16_immed_operands; | |
14558 | while (op->type != type) | |
14559 | ++op; | |
14560 | ||
14561 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14562 | { | |
b34976b6 AM |
14563 | small = FALSE; |
14564 | ext = TRUE; | |
252b5132 RH |
14565 | } |
14566 | else | |
14567 | { | |
b34976b6 AM |
14568 | small = TRUE; |
14569 | ext = FALSE; | |
252b5132 RH |
14570 | } |
14571 | ||
6386f3a7 | 14572 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
14573 | val = S_GET_VALUE (fragp->fr_symbol); |
14574 | if (op->pcrel) | |
14575 | { | |
14576 | addressT addr; | |
14577 | ||
14578 | addr = fragp->fr_address + fragp->fr_fix; | |
14579 | ||
14580 | /* The rules for the base address of a PC relative reloc are | |
14581 | complicated; see mips16_extended_frag. */ | |
14582 | if (type == 'p' || type == 'q') | |
14583 | { | |
14584 | addr += 2; | |
14585 | if (ext) | |
14586 | addr += 2; | |
14587 | /* Ignore the low bit in the target, since it will be | |
14588 | set for a text label. */ | |
14589 | if ((val & 1) != 0) | |
14590 | --val; | |
14591 | } | |
14592 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
14593 | addr -= 4; | |
14594 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
14595 | addr -= 2; | |
14596 | ||
14597 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
14598 | val -= addr; | |
14599 | ||
14600 | /* Make sure the section winds up with the alignment we have | |
14601 | assumed. */ | |
14602 | if (op->shift > 0) | |
14603 | record_alignment (asec, op->shift); | |
14604 | } | |
14605 | ||
14606 | if (ext | |
14607 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
14608 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
14609 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
14610 | _("extended instruction in delay slot")); | |
14611 | ||
14612 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
14613 | ||
14614 | if (target_big_endian) | |
14615 | insn = bfd_getb16 (buf); | |
14616 | else | |
14617 | insn = bfd_getl16 (buf); | |
14618 | ||
14619 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
14620 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
14621 | small, ext, &insn, &use_extend, &extend); | |
14622 | ||
14623 | if (use_extend) | |
14624 | { | |
2132e3a3 | 14625 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
14626 | fragp->fr_fix += 2; |
14627 | buf += 2; | |
14628 | } | |
14629 | ||
2132e3a3 | 14630 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
14631 | fragp->fr_fix += 2; |
14632 | buf += 2; | |
14633 | } | |
14634 | else | |
14635 | { | |
4d7206a2 RS |
14636 | int first, second; |
14637 | fixS *fixp; | |
252b5132 | 14638 | |
4d7206a2 RS |
14639 | first = RELAX_FIRST (fragp->fr_subtype); |
14640 | second = RELAX_SECOND (fragp->fr_subtype); | |
14641 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 14642 | |
584892a6 RS |
14643 | /* Possibly emit a warning if we've chosen the longer option. */ |
14644 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
14645 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
14646 | { | |
14647 | const char *msg = macro_warning (fragp->fr_subtype); | |
14648 | if (msg != 0) | |
520725ea | 14649 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
584892a6 RS |
14650 | } |
14651 | ||
4d7206a2 RS |
14652 | /* Go through all the fixups for the first sequence. Disable them |
14653 | (by marking them as done) if we're going to use the second | |
14654 | sequence instead. */ | |
14655 | while (fixp | |
14656 | && fixp->fx_frag == fragp | |
14657 | && fixp->fx_where < fragp->fr_fix - second) | |
14658 | { | |
14659 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14660 | fixp->fx_done = 1; | |
14661 | fixp = fixp->fx_next; | |
14662 | } | |
252b5132 | 14663 | |
4d7206a2 RS |
14664 | /* Go through the fixups for the second sequence. Disable them if |
14665 | we're going to use the first sequence, otherwise adjust their | |
14666 | addresses to account for the relaxation. */ | |
14667 | while (fixp && fixp->fx_frag == fragp) | |
14668 | { | |
14669 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14670 | fixp->fx_where -= first; | |
14671 | else | |
14672 | fixp->fx_done = 1; | |
14673 | fixp = fixp->fx_next; | |
14674 | } | |
14675 | ||
14676 | /* Now modify the frag contents. */ | |
14677 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14678 | { | |
14679 | char *start; | |
14680 | ||
14681 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
14682 | memmove (start, start + first, second); | |
14683 | fragp->fr_fix -= first; | |
14684 | } | |
14685 | else | |
14686 | fragp->fr_fix -= second; | |
252b5132 RH |
14687 | } |
14688 | } | |
14689 | ||
14690 | #ifdef OBJ_ELF | |
14691 | ||
14692 | /* This function is called after the relocs have been generated. | |
14693 | We've been storing mips16 text labels as odd. Here we convert them | |
14694 | back to even for the convenience of the debugger. */ | |
14695 | ||
14696 | void | |
17a2f251 | 14697 | mips_frob_file_after_relocs (void) |
252b5132 RH |
14698 | { |
14699 | asymbol **syms; | |
14700 | unsigned int count, i; | |
14701 | ||
f43abd2b | 14702 | if (!IS_ELF) |
252b5132 RH |
14703 | return; |
14704 | ||
14705 | syms = bfd_get_outsymbols (stdoutput); | |
14706 | count = bfd_get_symcount (stdoutput); | |
14707 | for (i = 0; i < count; i++, syms++) | |
14708 | { | |
30c09090 | 14709 | if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other) |
252b5132 RH |
14710 | && ((*syms)->value & 1) != 0) |
14711 | { | |
14712 | (*syms)->value &= ~1; | |
14713 | /* If the symbol has an odd size, it was probably computed | |
14714 | incorrectly, so adjust that as well. */ | |
14715 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
14716 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
14717 | } | |
14718 | } | |
14719 | } | |
14720 | ||
14721 | #endif | |
14722 | ||
14723 | /* This function is called whenever a label is defined. It is used | |
14724 | when handling branch delays; if a branch has a label, we assume we | |
14725 | can not move it. */ | |
14726 | ||
14727 | void | |
17a2f251 | 14728 | mips_define_label (symbolS *sym) |
252b5132 | 14729 | { |
a8dbcb85 | 14730 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
14731 | struct insn_label_list *l; |
14732 | ||
14733 | if (free_insn_labels == NULL) | |
14734 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
14735 | else | |
14736 | { | |
14737 | l = free_insn_labels; | |
14738 | free_insn_labels = l->next; | |
14739 | } | |
14740 | ||
14741 | l->label = sym; | |
a8dbcb85 TS |
14742 | l->next = si->label_list; |
14743 | si->label_list = l; | |
07a53e5c RH |
14744 | |
14745 | #ifdef OBJ_ELF | |
14746 | dwarf2_emit_label (sym); | |
14747 | #endif | |
252b5132 RH |
14748 | } |
14749 | \f | |
14750 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14751 | ||
14752 | /* Some special processing for a MIPS ELF file. */ | |
14753 | ||
14754 | void | |
17a2f251 | 14755 | mips_elf_final_processing (void) |
252b5132 RH |
14756 | { |
14757 | /* Write out the register information. */ | |
316f5878 | 14758 | if (mips_abi != N64_ABI) |
252b5132 RH |
14759 | { |
14760 | Elf32_RegInfo s; | |
14761 | ||
14762 | s.ri_gprmask = mips_gprmask; | |
14763 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14764 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14765 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14766 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14767 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14768 | ||
14769 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
14770 | ((Elf32_External_RegInfo *) | |
14771 | mips_regmask_frag)); | |
14772 | } | |
14773 | else | |
14774 | { | |
14775 | Elf64_Internal_RegInfo s; | |
14776 | ||
14777 | s.ri_gprmask = mips_gprmask; | |
14778 | s.ri_pad = 0; | |
14779 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14780 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14781 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14782 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14783 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14784 | ||
14785 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
14786 | ((Elf64_External_RegInfo *) | |
14787 | mips_regmask_frag)); | |
14788 | } | |
14789 | ||
14790 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
14791 | sort of BFD interface for this. */ | |
14792 | if (mips_any_noreorder) | |
14793 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
14794 | if (mips_pic != NO_PIC) | |
143d77c5 | 14795 | { |
252b5132 | 14796 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
14797 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
14798 | } | |
14799 | if (mips_abicalls) | |
14800 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 14801 | |
98d3f06f | 14802 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
14803 | /* We may need to define a new flag for DSP ASE, and set this flag when |
14804 | file_ase_dsp is true. */ | |
8b082fb1 | 14805 | /* Same for DSP R2. */ |
ef2e4d86 CF |
14806 | /* We may need to define a new flag for MT ASE, and set this flag when |
14807 | file_ase_mt is true. */ | |
a4672219 TS |
14808 | if (file_ase_mips16) |
14809 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
14810 | #if 0 /* XXX FIXME */ |
14811 | if (file_ase_mips3d) | |
14812 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14813 | #endif | |
deec1734 CD |
14814 | if (file_ase_mdmx) |
14815 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 14816 | |
bdaaa2e1 | 14817 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 14818 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 14819 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 14820 | else if (mips_abi == O64_ABI) |
252b5132 | 14821 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 14822 | else if (mips_abi == EABI_ABI) |
252b5132 | 14823 | { |
316f5878 | 14824 | if (!file_mips_gp32) |
252b5132 RH |
14825 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
14826 | else | |
14827 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
14828 | } | |
316f5878 | 14829 | else if (mips_abi == N32_ABI) |
be00bddd TS |
14830 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
14831 | ||
c9914766 | 14832 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
14833 | |
14834 | if (mips_32bitmode) | |
14835 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
14836 | |
14837 | #if 0 /* XXX FIXME */ | |
14838 | /* 32 bit code with 64 bit FP registers. */ | |
14839 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14840 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14841 | #endif | |
252b5132 RH |
14842 | } |
14843 | ||
14844 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
14845 | \f | |
beae10d5 | 14846 | typedef struct proc { |
9b2f1d35 EC |
14847 | symbolS *func_sym; |
14848 | symbolS *func_end_sym; | |
beae10d5 KH |
14849 | unsigned long reg_mask; |
14850 | unsigned long reg_offset; | |
14851 | unsigned long fpreg_mask; | |
14852 | unsigned long fpreg_offset; | |
14853 | unsigned long frame_offset; | |
14854 | unsigned long frame_reg; | |
14855 | unsigned long pc_reg; | |
14856 | } procS; | |
252b5132 RH |
14857 | |
14858 | static procS cur_proc; | |
14859 | static procS *cur_proc_ptr; | |
14860 | static int numprocs; | |
14861 | ||
742a56fe RS |
14862 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal |
14863 | nop as "0". */ | |
14864 | ||
14865 | char | |
14866 | mips_nop_opcode (void) | |
14867 | { | |
14868 | return seg_info (now_seg)->tc_segment_info_data.mips16; | |
14869 | } | |
14870 | ||
14871 | /* Fill in an rs_align_code fragment. This only needs to do something | |
14872 | for MIPS16 code, where 0 is not a nop. */ | |
a19d8eb0 | 14873 | |
0a9ef439 | 14874 | void |
17a2f251 | 14875 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 14876 | { |
742a56fe | 14877 | char *p; |
c67a084a NC |
14878 | int bytes, size, excess; |
14879 | valueT opcode; | |
742a56fe | 14880 | |
0a9ef439 RH |
14881 | if (fragp->fr_type != rs_align_code) |
14882 | return; | |
14883 | ||
742a56fe RS |
14884 | p = fragp->fr_literal + fragp->fr_fix; |
14885 | if (*p) | |
a19d8eb0 | 14886 | { |
c67a084a NC |
14887 | opcode = mips16_nop_insn.insn_opcode; |
14888 | size = 2; | |
14889 | } | |
14890 | else | |
14891 | { | |
14892 | opcode = nop_insn.insn_opcode; | |
14893 | size = 4; | |
14894 | } | |
a19d8eb0 | 14895 | |
c67a084a NC |
14896 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
14897 | excess = bytes % size; | |
14898 | if (excess != 0) | |
14899 | { | |
14900 | /* If we're not inserting a whole number of instructions, | |
14901 | pad the end of the fixed part of the frag with zeros. */ | |
14902 | memset (p, 0, excess); | |
14903 | p += excess; | |
14904 | fragp->fr_fix += excess; | |
a19d8eb0 | 14905 | } |
c67a084a NC |
14906 | |
14907 | md_number_to_chars (p, opcode, size); | |
14908 | fragp->fr_var = size; | |
a19d8eb0 CP |
14909 | } |
14910 | ||
252b5132 | 14911 | static void |
17a2f251 | 14912 | md_obj_begin (void) |
252b5132 RH |
14913 | { |
14914 | } | |
14915 | ||
14916 | static void | |
17a2f251 | 14917 | md_obj_end (void) |
252b5132 | 14918 | { |
54f4ddb3 | 14919 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 14920 | if (cur_proc_ptr) |
9a41af64 | 14921 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
14922 | } |
14923 | ||
14924 | static long | |
17a2f251 | 14925 | get_number (void) |
252b5132 RH |
14926 | { |
14927 | int negative = 0; | |
14928 | long val = 0; | |
14929 | ||
14930 | if (*input_line_pointer == '-') | |
14931 | { | |
14932 | ++input_line_pointer; | |
14933 | negative = 1; | |
14934 | } | |
3882b010 | 14935 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 14936 | as_bad (_("expected simple number")); |
252b5132 RH |
14937 | if (input_line_pointer[0] == '0') |
14938 | { | |
14939 | if (input_line_pointer[1] == 'x') | |
14940 | { | |
14941 | input_line_pointer += 2; | |
3882b010 | 14942 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
14943 | { |
14944 | val <<= 4; | |
14945 | val |= hex_value (*input_line_pointer++); | |
14946 | } | |
14947 | return negative ? -val : val; | |
14948 | } | |
14949 | else | |
14950 | { | |
14951 | ++input_line_pointer; | |
3882b010 | 14952 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14953 | { |
14954 | val <<= 3; | |
14955 | val |= *input_line_pointer++ - '0'; | |
14956 | } | |
14957 | return negative ? -val : val; | |
14958 | } | |
14959 | } | |
3882b010 | 14960 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14961 | { |
14962 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
14963 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 14964 | as_warn (_("invalid number")); |
252b5132 RH |
14965 | return -1; |
14966 | } | |
3882b010 | 14967 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14968 | { |
14969 | val *= 10; | |
14970 | val += *input_line_pointer++ - '0'; | |
14971 | } | |
14972 | return negative ? -val : val; | |
14973 | } | |
14974 | ||
14975 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
14976 | is an initial number which is the ECOFF file index. In the non-ECOFF |
14977 | case .file implies DWARF-2. */ | |
14978 | ||
14979 | static void | |
17a2f251 | 14980 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 14981 | { |
ecb4347a DJ |
14982 | static int first_file_directive = 0; |
14983 | ||
c5dd6aab DJ |
14984 | if (ECOFF_DEBUGGING) |
14985 | { | |
14986 | get_number (); | |
14987 | s_app_file (0); | |
14988 | } | |
14989 | else | |
ecb4347a DJ |
14990 | { |
14991 | char *filename; | |
14992 | ||
14993 | filename = dwarf2_directive_file (0); | |
14994 | ||
14995 | /* Versions of GCC up to 3.1 start files with a ".file" | |
14996 | directive even for stabs output. Make sure that this | |
14997 | ".file" is handled. Note that you need a version of GCC | |
14998 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
14999 | if (filename != NULL && ! first_file_directive) | |
15000 | { | |
15001 | (void) new_logical_line (filename, -1); | |
c04f5787 | 15002 | s_app_file_string (filename, 0); |
ecb4347a DJ |
15003 | } |
15004 | first_file_directive = 1; | |
15005 | } | |
c5dd6aab DJ |
15006 | } |
15007 | ||
15008 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
15009 | |
15010 | static void | |
17a2f251 | 15011 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 15012 | { |
c5dd6aab DJ |
15013 | if (!ECOFF_DEBUGGING) |
15014 | dwarf2_directive_loc (0); | |
252b5132 RH |
15015 | } |
15016 | ||
252b5132 RH |
15017 | /* The .end directive. */ |
15018 | ||
15019 | static void | |
17a2f251 | 15020 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15021 | { |
15022 | symbolS *p; | |
252b5132 | 15023 | |
7a621144 DJ |
15024 | /* Following functions need their own .frame and .cprestore directives. */ |
15025 | mips_frame_reg_valid = 0; | |
15026 | mips_cprestore_valid = 0; | |
15027 | ||
252b5132 RH |
15028 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
15029 | { | |
15030 | p = get_symbol (); | |
15031 | demand_empty_rest_of_line (); | |
15032 | } | |
15033 | else | |
15034 | p = NULL; | |
15035 | ||
14949570 | 15036 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
15037 | as_warn (_(".end not in text section")); |
15038 | ||
15039 | if (!cur_proc_ptr) | |
15040 | { | |
15041 | as_warn (_(".end directive without a preceding .ent directive.")); | |
15042 | demand_empty_rest_of_line (); | |
15043 | return; | |
15044 | } | |
15045 | ||
15046 | if (p != NULL) | |
15047 | { | |
9c2799c2 | 15048 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 15049 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 15050 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
15051 | |
15052 | if (debug_type == DEBUG_STABS) | |
15053 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
15054 | S_GET_NAME (p)); | |
252b5132 RH |
15055 | } |
15056 | else | |
15057 | as_warn (_(".end directive missing or unknown symbol")); | |
15058 | ||
2132e3a3 | 15059 | #ifdef OBJ_ELF |
9b2f1d35 EC |
15060 | /* Create an expression to calculate the size of the function. */ |
15061 | if (p && cur_proc_ptr) | |
15062 | { | |
15063 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
15064 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
15065 | ||
15066 | obj->size = exp; | |
15067 | exp->X_op = O_subtract; | |
15068 | exp->X_add_symbol = symbol_temp_new_now (); | |
15069 | exp->X_op_symbol = p; | |
15070 | exp->X_add_number = 0; | |
15071 | ||
15072 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
15073 | } | |
15074 | ||
ecb4347a | 15075 | /* Generate a .pdr section. */ |
f43abd2b | 15076 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
15077 | { |
15078 | segT saved_seg = now_seg; | |
15079 | subsegT saved_subseg = now_subseg; | |
15080 | valueT dot; | |
15081 | expressionS exp; | |
15082 | char *fragp; | |
252b5132 | 15083 | |
ecb4347a | 15084 | dot = frag_now_fix (); |
252b5132 RH |
15085 | |
15086 | #ifdef md_flush_pending_output | |
ecb4347a | 15087 | md_flush_pending_output (); |
252b5132 RH |
15088 | #endif |
15089 | ||
9c2799c2 | 15090 | gas_assert (pdr_seg); |
ecb4347a | 15091 | subseg_set (pdr_seg, 0); |
252b5132 | 15092 | |
ecb4347a DJ |
15093 | /* Write the symbol. */ |
15094 | exp.X_op = O_symbol; | |
15095 | exp.X_add_symbol = p; | |
15096 | exp.X_add_number = 0; | |
15097 | emit_expr (&exp, 4); | |
252b5132 | 15098 | |
ecb4347a | 15099 | fragp = frag_more (7 * 4); |
252b5132 | 15100 | |
17a2f251 TS |
15101 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
15102 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
15103 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
15104 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
15105 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
15106 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
15107 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 15108 | |
ecb4347a DJ |
15109 | subseg_set (saved_seg, saved_subseg); |
15110 | } | |
15111 | #endif /* OBJ_ELF */ | |
252b5132 RH |
15112 | |
15113 | cur_proc_ptr = NULL; | |
15114 | } | |
15115 | ||
15116 | /* The .aent and .ent directives. */ | |
15117 | ||
15118 | static void | |
17a2f251 | 15119 | s_mips_ent (int aent) |
252b5132 | 15120 | { |
252b5132 | 15121 | symbolS *symbolP; |
252b5132 RH |
15122 | |
15123 | symbolP = get_symbol (); | |
15124 | if (*input_line_pointer == ',') | |
f9419b05 | 15125 | ++input_line_pointer; |
252b5132 | 15126 | SKIP_WHITESPACE (); |
3882b010 | 15127 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 15128 | || *input_line_pointer == '-') |
874e8986 | 15129 | get_number (); |
252b5132 | 15130 | |
14949570 | 15131 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
15132 | as_warn (_(".ent or .aent not in text section.")); |
15133 | ||
15134 | if (!aent && cur_proc_ptr) | |
9a41af64 | 15135 | as_warn (_("missing .end")); |
252b5132 RH |
15136 | |
15137 | if (!aent) | |
15138 | { | |
7a621144 DJ |
15139 | /* This function needs its own .frame and .cprestore directives. */ |
15140 | mips_frame_reg_valid = 0; | |
15141 | mips_cprestore_valid = 0; | |
15142 | ||
252b5132 RH |
15143 | cur_proc_ptr = &cur_proc; |
15144 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
15145 | ||
9b2f1d35 | 15146 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 15147 | |
f9419b05 | 15148 | ++numprocs; |
ecb4347a DJ |
15149 | |
15150 | if (debug_type == DEBUG_STABS) | |
15151 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
15152 | S_GET_NAME (symbolP)); | |
252b5132 RH |
15153 | } |
15154 | ||
7c0fc524 MR |
15155 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
15156 | ||
252b5132 RH |
15157 | demand_empty_rest_of_line (); |
15158 | } | |
15159 | ||
15160 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 15161 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 15162 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 15163 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
15164 | symbol table (in the mdebug section). */ |
15165 | ||
15166 | static void | |
17a2f251 | 15167 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 15168 | { |
ecb4347a | 15169 | #ifdef OBJ_ELF |
f43abd2b | 15170 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
15171 | { |
15172 | long val; | |
252b5132 | 15173 | |
ecb4347a DJ |
15174 | if (cur_proc_ptr == (procS *) NULL) |
15175 | { | |
15176 | as_warn (_(".frame outside of .ent")); | |
15177 | demand_empty_rest_of_line (); | |
15178 | return; | |
15179 | } | |
252b5132 | 15180 | |
ecb4347a DJ |
15181 | cur_proc_ptr->frame_reg = tc_get_register (1); |
15182 | ||
15183 | SKIP_WHITESPACE (); | |
15184 | if (*input_line_pointer++ != ',' | |
15185 | || get_absolute_expression_and_terminator (&val) != ',') | |
15186 | { | |
15187 | as_warn (_("Bad .frame directive")); | |
15188 | --input_line_pointer; | |
15189 | demand_empty_rest_of_line (); | |
15190 | return; | |
15191 | } | |
252b5132 | 15192 | |
ecb4347a DJ |
15193 | cur_proc_ptr->frame_offset = val; |
15194 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 15195 | |
252b5132 | 15196 | demand_empty_rest_of_line (); |
252b5132 | 15197 | } |
ecb4347a DJ |
15198 | else |
15199 | #endif /* OBJ_ELF */ | |
15200 | s_ignore (ignore); | |
252b5132 RH |
15201 | } |
15202 | ||
bdaaa2e1 KH |
15203 | /* The .fmask and .mask directives. If the mdebug section is present |
15204 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 15205 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 15206 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
15207 | make reference to the ecoff symbol table (in the mdebug section). */ |
15208 | ||
15209 | static void | |
17a2f251 | 15210 | s_mips_mask (int reg_type) |
252b5132 | 15211 | { |
ecb4347a | 15212 | #ifdef OBJ_ELF |
f43abd2b | 15213 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 15214 | { |
ecb4347a | 15215 | long mask, off; |
252b5132 | 15216 | |
ecb4347a DJ |
15217 | if (cur_proc_ptr == (procS *) NULL) |
15218 | { | |
15219 | as_warn (_(".mask/.fmask outside of .ent")); | |
15220 | demand_empty_rest_of_line (); | |
15221 | return; | |
15222 | } | |
252b5132 | 15223 | |
ecb4347a DJ |
15224 | if (get_absolute_expression_and_terminator (&mask) != ',') |
15225 | { | |
15226 | as_warn (_("Bad .mask/.fmask directive")); | |
15227 | --input_line_pointer; | |
15228 | demand_empty_rest_of_line (); | |
15229 | return; | |
15230 | } | |
252b5132 | 15231 | |
ecb4347a DJ |
15232 | off = get_absolute_expression (); |
15233 | ||
15234 | if (reg_type == 'F') | |
15235 | { | |
15236 | cur_proc_ptr->fpreg_mask = mask; | |
15237 | cur_proc_ptr->fpreg_offset = off; | |
15238 | } | |
15239 | else | |
15240 | { | |
15241 | cur_proc_ptr->reg_mask = mask; | |
15242 | cur_proc_ptr->reg_offset = off; | |
15243 | } | |
15244 | ||
15245 | demand_empty_rest_of_line (); | |
252b5132 RH |
15246 | } |
15247 | else | |
ecb4347a DJ |
15248 | #endif /* OBJ_ELF */ |
15249 | s_ignore (reg_type); | |
252b5132 RH |
15250 | } |
15251 | ||
316f5878 RS |
15252 | /* A table describing all the processors gas knows about. Names are |
15253 | matched in the order listed. | |
e7af610e | 15254 | |
316f5878 RS |
15255 | To ease comparison, please keep this table in the same order as |
15256 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
15257 | static const struct mips_cpu_info mips_cpu_info_table[] = |
15258 | { | |
316f5878 | 15259 | /* Entries for generic ISAs */ |
ad3fea08 TS |
15260 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
15261 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
15262 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
15263 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
15264 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
15265 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
15266 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15267 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
15268 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
15269 | |
15270 | /* MIPS I */ | |
ad3fea08 TS |
15271 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
15272 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
15273 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
15274 | |
15275 | /* MIPS II */ | |
ad3fea08 | 15276 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
15277 | |
15278 | /* MIPS III */ | |
ad3fea08 TS |
15279 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
15280 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
15281 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
15282 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
15283 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
15284 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
15285 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
15286 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
15287 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
15288 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
15289 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
15290 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
b15591bb AN |
15291 | /* ST Microelectronics Loongson 2E and 2F cores */ |
15292 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
15293 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
15294 | |
15295 | /* MIPS IV */ | |
ad3fea08 TS |
15296 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
15297 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
15298 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
3aa3176b TS |
15299 | { "r14000", 0, ISA_MIPS4, CPU_R14000 }, |
15300 | { "r16000", 0, ISA_MIPS4, CPU_R16000 }, | |
ad3fea08 TS |
15301 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
15302 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
15303 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
15304 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
15305 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
15306 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
15307 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
15308 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
15309 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
15310 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
15311 | |
15312 | /* MIPS 32 */ | |
ad3fea08 TS |
15313 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
15314 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
15315 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
15316 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
15317 | ||
15318 | /* MIPS 32 Release 2 */ | |
15319 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15320 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15321 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15322 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15323 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15324 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 15325 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 15326 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 15327 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
15328 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
15329 | /* Deprecated forms of the above. */ | |
15330 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 15331 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 15332 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 15333 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 15334 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 15335 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
15336 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
15337 | /* Deprecated forms of the above. */ | |
15338 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 15339 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 15340 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
15341 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15342 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15343 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15344 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
15345 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15346 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15347 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15348 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15349 | /* Deprecated forms of the above. */ | |
15350 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15351 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
15352 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15353 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15354 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
15355 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15356 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15357 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15358 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15359 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15360 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15361 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15362 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15363 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15364 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15365 | /* Deprecated forms of the above. */ | |
15366 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15367 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15368 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15369 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a SL |
15370 | /* 1004K cores are multiprocessor versions of the 34K. */ |
15371 | { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15372 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15373 | { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15374 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15375 | { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15376 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15377 | { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15378 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 15379 | |
316f5878 | 15380 | /* MIPS 64 */ |
ad3fea08 TS |
15381 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
15382 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
15383 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 15384 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 | 15385 | |
c7a23324 | 15386 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
15387 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
15388 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
15389 | /* Broadcom SB-1A CPU core */ |
15390 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
15391 | ISA_MIPS64, CPU_SB1 }, | |
e7af610e | 15392 | |
ed163775 MR |
15393 | /* MIPS 64 Release 2 */ |
15394 | ||
967344c6 AN |
15395 | /* Cavium Networks Octeon CPU core */ |
15396 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
15397 | ||
52b6b6b9 JM |
15398 | /* RMI Xlr */ |
15399 | { "xlr", 0, ISA_MIPS64, CPU_XLR }, | |
15400 | ||
316f5878 RS |
15401 | /* End marker */ |
15402 | { NULL, 0, 0, 0 } | |
15403 | }; | |
e7af610e | 15404 | |
84ea6cf2 | 15405 | |
316f5878 RS |
15406 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
15407 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 15408 | |
316f5878 | 15409 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 15410 | |
b34976b6 | 15411 | static bfd_boolean |
17a2f251 | 15412 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
15413 | { |
15414 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
15415 | given++, canonical++; | |
15416 | ||
15417 | return ((*given == 0 && *canonical == 0) | |
15418 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
15419 | } | |
15420 | ||
15421 | ||
15422 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
15423 | CPU name. We've traditionally allowed a lot of variation here. | |
15424 | ||
15425 | Note: this function is shared between GCC and GAS. */ | |
15426 | ||
b34976b6 | 15427 | static bfd_boolean |
17a2f251 | 15428 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
15429 | { |
15430 | /* First see if the name matches exactly, or with a final "000" | |
15431 | turned into "k". */ | |
15432 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 15433 | return TRUE; |
316f5878 RS |
15434 | |
15435 | /* If not, try comparing based on numerical designation alone. | |
15436 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
15437 | if (TOLOWER (*given) == 'r') | |
15438 | given++; | |
15439 | if (!ISDIGIT (*given)) | |
b34976b6 | 15440 | return FALSE; |
316f5878 RS |
15441 | |
15442 | /* Skip over some well-known prefixes in the canonical name, | |
15443 | hoping to find a number there too. */ | |
15444 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
15445 | canonical += 2; | |
15446 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
15447 | canonical += 2; | |
15448 | else if (TOLOWER (canonical[0]) == 'r') | |
15449 | canonical += 1; | |
15450 | ||
15451 | return mips_strict_matching_cpu_name_p (canonical, given); | |
15452 | } | |
15453 | ||
15454 | ||
15455 | /* Parse an option that takes the name of a processor as its argument. | |
15456 | OPTION is the name of the option and CPU_STRING is the argument. | |
15457 | Return the corresponding processor enumeration if the CPU_STRING is | |
15458 | recognized, otherwise report an error and return null. | |
15459 | ||
15460 | A similar function exists in GCC. */ | |
e7af610e NC |
15461 | |
15462 | static const struct mips_cpu_info * | |
17a2f251 | 15463 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 15464 | { |
316f5878 | 15465 | const struct mips_cpu_info *p; |
e7af610e | 15466 | |
316f5878 RS |
15467 | /* 'from-abi' selects the most compatible architecture for the given |
15468 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
15469 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
15470 | version. Look first at the -mgp options, if given, otherwise base | |
15471 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 15472 | |
316f5878 RS |
15473 | Treat NO_ABI like the EABIs. One reason to do this is that the |
15474 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
15475 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
15476 | 'mips64', just as we did in the days before 'from-abi'. */ | |
15477 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
15478 | { | |
15479 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15480 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
15481 | ||
15482 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15483 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
15484 | ||
15485 | if (file_mips_gp32 >= 0) | |
15486 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
15487 | ||
15488 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
15489 | ? ISA_MIPS3 | |
15490 | : ISA_MIPS1); | |
15491 | } | |
15492 | ||
15493 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
15494 | if (strcasecmp (cpu_string, "default") == 0) | |
15495 | return 0; | |
15496 | ||
15497 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
15498 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
15499 | return p; | |
15500 | ||
20203fb9 | 15501 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 15502 | return 0; |
e7af610e NC |
15503 | } |
15504 | ||
316f5878 RS |
15505 | /* Return the canonical processor information for ISA (a member of the |
15506 | ISA_MIPS* enumeration). */ | |
15507 | ||
e7af610e | 15508 | static const struct mips_cpu_info * |
17a2f251 | 15509 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
15510 | { |
15511 | int i; | |
15512 | ||
15513 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 15514 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 15515 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
15516 | return (&mips_cpu_info_table[i]); |
15517 | ||
e972090a | 15518 | return NULL; |
e7af610e | 15519 | } |
fef14a42 TS |
15520 | |
15521 | static const struct mips_cpu_info * | |
17a2f251 | 15522 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
15523 | { |
15524 | int i; | |
15525 | ||
15526 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
15527 | if (arch == mips_cpu_info_table[i].cpu) | |
15528 | return (&mips_cpu_info_table[i]); | |
15529 | ||
15530 | return NULL; | |
15531 | } | |
316f5878 RS |
15532 | \f |
15533 | static void | |
17a2f251 | 15534 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
15535 | { |
15536 | if (*first_p) | |
15537 | { | |
15538 | fprintf (stream, "%24s", ""); | |
15539 | *col_p = 24; | |
15540 | } | |
15541 | else | |
15542 | { | |
15543 | fprintf (stream, ", "); | |
15544 | *col_p += 2; | |
15545 | } | |
e7af610e | 15546 | |
316f5878 RS |
15547 | if (*col_p + strlen (string) > 72) |
15548 | { | |
15549 | fprintf (stream, "\n%24s", ""); | |
15550 | *col_p = 24; | |
15551 | } | |
15552 | ||
15553 | fprintf (stream, "%s", string); | |
15554 | *col_p += strlen (string); | |
15555 | ||
15556 | *first_p = 0; | |
15557 | } | |
15558 | ||
15559 | void | |
17a2f251 | 15560 | md_show_usage (FILE *stream) |
e7af610e | 15561 | { |
316f5878 RS |
15562 | int column, first; |
15563 | size_t i; | |
15564 | ||
15565 | fprintf (stream, _("\ | |
15566 | MIPS options:\n\ | |
316f5878 RS |
15567 | -EB generate big endian output\n\ |
15568 | -EL generate little endian output\n\ | |
15569 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
15570 | -G NUM allow referencing objects up to NUM bytes\n\ | |
15571 | implicitly with the gp register [default 8]\n")); | |
15572 | fprintf (stream, _("\ | |
15573 | -mips1 generate MIPS ISA I instructions\n\ | |
15574 | -mips2 generate MIPS ISA II instructions\n\ | |
15575 | -mips3 generate MIPS ISA III instructions\n\ | |
15576 | -mips4 generate MIPS ISA IV instructions\n\ | |
15577 | -mips5 generate MIPS ISA V instructions\n\ | |
15578 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 15579 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 15580 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 15581 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
15582 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
15583 | ||
15584 | first = 1; | |
e7af610e NC |
15585 | |
15586 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
15587 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
15588 | show (stream, "from-abi", &column, &first); | |
15589 | fputc ('\n', stream); | |
e7af610e | 15590 | |
316f5878 RS |
15591 | fprintf (stream, _("\ |
15592 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
15593 | -no-mCPU don't generate code specific to CPU.\n\ | |
15594 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
15595 | ||
15596 | first = 1; | |
15597 | ||
15598 | show (stream, "3900", &column, &first); | |
15599 | show (stream, "4010", &column, &first); | |
15600 | show (stream, "4100", &column, &first); | |
15601 | show (stream, "4650", &column, &first); | |
15602 | fputc ('\n', stream); | |
15603 | ||
15604 | fprintf (stream, _("\ | |
15605 | -mips16 generate mips16 instructions\n\ | |
15606 | -no-mips16 do not generate mips16 instructions\n")); | |
15607 | fprintf (stream, _("\ | |
e16bfa71 TS |
15608 | -msmartmips generate smartmips instructions\n\ |
15609 | -mno-smartmips do not generate smartmips instructions\n")); | |
15610 | fprintf (stream, _("\ | |
74cd071d CF |
15611 | -mdsp generate DSP instructions\n\ |
15612 | -mno-dsp do not generate DSP instructions\n")); | |
15613 | fprintf (stream, _("\ | |
8b082fb1 TS |
15614 | -mdspr2 generate DSP R2 instructions\n\ |
15615 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
15616 | fprintf (stream, _("\ | |
ef2e4d86 CF |
15617 | -mmt generate MT instructions\n\ |
15618 | -mno-mt do not generate MT instructions\n")); | |
15619 | fprintf (stream, _("\ | |
c67a084a NC |
15620 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
15621 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 15622 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 15623 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 15624 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
316f5878 RS |
15625 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
15626 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 15627 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
15628 | -O0 remove unneeded NOPs, do not swap branches\n\ |
15629 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
15630 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
15631 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
15632 | fprintf (stream, _("\ |
15633 | -mhard-float allow floating-point instructions\n\ | |
15634 | -msoft-float do not allow floating-point instructions\n\ | |
15635 | -msingle-float only allow 32-bit floating-point operations\n\ | |
15636 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
15637 | --[no-]construct-floats [dis]allow floating point values to be constructed\n" | |
15638 | )); | |
316f5878 RS |
15639 | #ifdef OBJ_ELF |
15640 | fprintf (stream, _("\ | |
15641 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 15642 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 15643 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 15644 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 15645 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 15646 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 15647 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 15648 | position dependent (non shared) code\n\ |
316f5878 RS |
15649 | -mabi=ABI create ABI conformant object file for:\n")); |
15650 | ||
15651 | first = 1; | |
15652 | ||
15653 | show (stream, "32", &column, &first); | |
15654 | show (stream, "o64", &column, &first); | |
15655 | show (stream, "n32", &column, &first); | |
15656 | show (stream, "64", &column, &first); | |
15657 | show (stream, "eabi", &column, &first); | |
15658 | ||
15659 | fputc ('\n', stream); | |
15660 | ||
15661 | fprintf (stream, _("\ | |
15662 | -32 create o32 ABI object file (default)\n\ | |
15663 | -n32 create n32 ABI object file\n\ | |
15664 | -64 create 64 ABI object file\n")); | |
15665 | #endif | |
e7af610e | 15666 | } |
14e777e0 KB |
15667 | |
15668 | enum dwarf2_format | |
413a266c | 15669 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 15670 | { |
369943fe | 15671 | if (HAVE_64BIT_SYMBOLS) |
1de5b6a1 AO |
15672 | { |
15673 | #ifdef TE_IRIX | |
15674 | return dwarf2_format_64bit_irix; | |
15675 | #else | |
15676 | return dwarf2_format_64bit; | |
15677 | #endif | |
15678 | } | |
14e777e0 KB |
15679 | else |
15680 | return dwarf2_format_32bit; | |
15681 | } | |
73369e65 EC |
15682 | |
15683 | int | |
15684 | mips_dwarf2_addr_size (void) | |
15685 | { | |
6b6b3450 | 15686 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 15687 | return 8; |
73369e65 EC |
15688 | else |
15689 | return 4; | |
15690 | } | |
5862107c EC |
15691 | |
15692 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
15693 | void | |
15694 | mips_cfi_frame_initial_instructions (void) | |
15695 | { | |
15696 | cfi_add_CFA_def_cfa_register (SP); | |
15697 | } | |
15698 | ||
707bfff6 TS |
15699 | int |
15700 | tc_mips_regname_to_dw2regnum (char *regname) | |
15701 | { | |
15702 | unsigned int regnum = -1; | |
15703 | unsigned int reg; | |
15704 | ||
15705 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
15706 | regnum = reg; | |
15707 | ||
15708 | return regnum; | |
15709 | } |