Commit | Line | Data |
---|---|---|
3d3c5039 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
fb251650 | 2 | Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc. |
3d3c5039 ILT |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
fb251650 ILT |
21 | along with GAS; see the file COPYING. If not, write to the Free |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
3d3c5039 ILT |
24 | |
25 | #include "as.h" | |
8358c818 | 26 | #include "config.h" |
9da4c5d1 | 27 | #include "subsegs.h" |
3d3c5039 ILT |
28 | |
29 | #include <ctype.h> | |
30 | ||
1dc1e798 | 31 | #ifdef USE_STDARG |
3d3c5039 | 32 | #include <stdarg.h> |
1dc1e798 KR |
33 | #endif |
34 | #ifdef USE_VARARGS | |
3d3c5039 | 35 | #include <varargs.h> |
1dc1e798 | 36 | #endif |
3d3c5039 | 37 | |
918692a5 | 38 | #include "opcode/mips.h" |
3d3c5039 | 39 | |
739708fa KR |
40 | #ifdef OBJ_MAYBE_ELF |
41 | /* Clean up namespace so we can include obj-elf.h too. */ | |
42 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
43 | #undef OBJ_PROCESS_STAB | |
44 | #undef OUTPUT_FLAVOR | |
45 | #undef S_GET_ALIGN | |
46 | #undef S_GET_SIZE | |
47 | #undef S_SET_ALIGN | |
48 | #undef S_SET_SIZE | |
49 | #undef TARGET_SYMBOL_FIELDS | |
50 | #undef obj_frob_file | |
51 | #undef obj_frob_symbol | |
52 | #undef obj_pop_insert | |
53 | #undef obj_sec_sym_ok_for_reloc | |
54 | ||
55 | #include "obj-elf.h" | |
56 | /* Fix any of them that we actually care about. */ | |
57 | #undef OUTPUT_FLAVOR | |
58 | #define OUTPUT_FLAVOR mips_output_flavor() | |
59 | #endif | |
60 | ||
61 | #if defined (OBJ_ELF) | |
f2a663d3 | 62 | #include "elf/mips.h" |
1dc1e798 | 63 | #endif |
f2a663d3 | 64 | |
739708fa | 65 | #ifndef ECOFF_DEBUGGING |
c625fc23 | 66 | #define NO_ECOFF_DEBUGGING |
739708fa KR |
67 | #define ECOFF_DEBUGGING 0 |
68 | #endif | |
69 | ||
22ba90ce ILT |
70 | #include "ecoff.h" |
71 | ||
a8aed9dd | 72 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 73 | static char *mips_regmask_frag; |
a8aed9dd | 74 | #endif |
f2a663d3 | 75 | |
3d3c5039 | 76 | #define AT 1 |
9226253a | 77 | #define PIC_CALL_REG 25 |
b2b8c24e ILT |
78 | #define KT0 26 |
79 | #define KT1 27 | |
670a50eb | 80 | #define GP 28 |
9226253a ILT |
81 | #define SP 29 |
82 | #define FP 30 | |
3d3c5039 ILT |
83 | #define RA 31 |
84 | ||
1dc1e798 | 85 | extern int target_big_endian; |
88225433 | 86 | |
7f9880e5 ILT |
87 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the |
88 | 32 bit ABI. This has no meaning for ECOFF. */ | |
89 | static int mips_64; | |
90 | ||
04cb3372 | 91 | /* The default target format to use. */ |
1dc1e798 KR |
92 | const char * |
93 | mips_target_format () | |
94 | { | |
95 | switch (OUTPUT_FLAVOR) | |
96 | { | |
97 | case bfd_target_aout_flavour: | |
98 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
99 | case bfd_target_ecoff_flavour: | |
100 | return target_big_endian ? "ecoff-bigmips" : "ecoff-littlemips"; | |
101 | case bfd_target_elf_flavour: | |
7f9880e5 ILT |
102 | return (target_big_endian |
103 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
104 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
1dc1e798 KR |
105 | default: |
106 | abort (); | |
107 | } | |
108 | } | |
04cb3372 | 109 | |
d2c71068 | 110 | /* The name of the readonly data section. */ |
1dc1e798 KR |
111 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
112 | ? ".data" \ | |
113 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
114 | ? ".rdata" \ | |
115 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ | |
116 | ? ".rodata" \ | |
117 | : (abort (), "")) | |
d2c71068 | 118 | |
1aa6938e ILT |
119 | /* These variables are filled in with the masks of registers used. |
120 | The object format code reads them and puts them in the appropriate | |
121 | place. */ | |
122 | unsigned long mips_gprmask; | |
123 | unsigned long mips_cprmask[4]; | |
124 | ||
1051c97f ILT |
125 | /* MIPS ISA (Instruction Set Architecture) level (may be changed |
126 | temporarily using .set mipsN). */ | |
8358c818 ILT |
127 | static int mips_isa = -1; |
128 | ||
1051c97f ILT |
129 | /* MIPS ISA we are using for this output file. */ |
130 | static int file_mips_isa; | |
131 | ||
8c63448a | 132 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
4bb0cc41 | 133 | static int mips_cpu = -1; |
8c63448a | 134 | |
b2b8c24e ILT |
135 | /* Whether the 4650 instructions (mad/madu) are permitted. */ |
136 | static int mips_4650 = -1; | |
137 | ||
e532b44c ILT |
138 | /* Whether the 4010 instructions are permitted. */ |
139 | static int mips_4010 = -1; | |
140 | ||
c625fc23 JSC |
141 | /* Whether the 4100 MADD16 and DMADD16 are permitted. */ |
142 | static int mips_4100 = -1; | |
143 | ||
e532b44c ILT |
144 | /* Whether the processor uses hardware interlocks, and thus does not |
145 | require nops to be inserted. */ | |
146 | static int interlocks = -1; | |
147 | ||
344a8d61 JSC |
148 | /* As with "interlocks" this is used by hardware that has FP |
149 | (co-processor) interlocks. */ | |
150 | static int cop_interlocks = -1; | |
151 | ||
d9aba805 ILT |
152 | /* MIPS PIC level. */ |
153 | ||
154 | enum mips_pic_level | |
155 | { | |
156 | /* Do not generate PIC code. */ | |
157 | NO_PIC, | |
158 | ||
159 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
160 | not sure what it is supposed to do. */ | |
161 | IRIX4_PIC, | |
162 | ||
163 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
164 | SVR4_PIC, | |
165 | ||
166 | /* Generate PIC code without using a global offset table: the data | |
167 | segment has a maximum size of 64K, all data references are off | |
168 | the $gp register, and all text references are PC relative. This | |
169 | is used on some embedded systems. */ | |
170 | EMBEDDED_PIC | |
171 | }; | |
172 | ||
173 | static enum mips_pic_level mips_pic; | |
9226253a | 174 | |
fb251650 ILT |
175 | /* 1 if we should generate 32 bit offsets from the GP register in |
176 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
177 | static int mips_big_got; | |
178 | ||
8ea7f4e8 ILT |
179 | /* 1 if trap instructions should used for overflow rather than break |
180 | instructions. */ | |
181 | static int mips_trap; | |
182 | ||
3d3c5039 ILT |
183 | static int mips_warn_about_macros; |
184 | static int mips_noreorder; | |
0dd2d296 | 185 | static int mips_any_noreorder; |
3d3c5039 ILT |
186 | static int mips_nomove; |
187 | static int mips_noat; | |
188 | static int mips_nobopt; | |
189 | ||
670a50eb ILT |
190 | /* The size of the small data section. */ |
191 | static int g_switch_value = 8; | |
42562568 ILT |
192 | /* Whether the -G option was used. */ |
193 | static int g_switch_seen = 0; | |
670a50eb | 194 | |
3d3c5039 ILT |
195 | #define N_RMASK 0xc4 |
196 | #define N_VFP 0xd4 | |
197 | ||
d8a1c247 KR |
198 | /* If we can determine in advance that GP optimization won't be |
199 | possible, we can skip the relaxation stuff that tries to produce | |
200 | GP-relative references. This makes delay slot optimization work | |
201 | better. | |
202 | ||
203 | This function can only provide a guess, but it seems to work for | |
204 | gcc output. If it guesses wrong, the only loss should be in | |
205 | efficiency; it shouldn't introduce any bugs. | |
206 | ||
207 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
208 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
209 | static int nopic_need_relax PARAMS ((symbolS *)); | |
210 | ||
3d3c5039 ILT |
211 | /* handle of the OPCODE hash table */ |
212 | static struct hash_control *op_hash = NULL; | |
213 | ||
214 | /* This array holds the chars that always start a comment. If the | |
215 | pre-processor is disabled, these aren't very useful */ | |
216 | const char comment_chars[] = "#"; | |
217 | ||
218 | /* This array holds the chars that only start a comment at the beginning of | |
219 | a line. If the line seems to have the form '# 123 filename' | |
220 | .line and .file directives will appear in the pre-processed output */ | |
221 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
222 | first line of the input file. This is because the compiler outputs | |
223 | #NO_APP at the beginning of its output. */ | |
224 | /* Also note that C style comments are always supported. */ | |
225 | const char line_comment_chars[] = "#"; | |
226 | ||
227 | /* This array holds machine specific line separator characters. */ | |
228 | const char line_separator_chars[] = ""; | |
229 | ||
230 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
231 | const char EXP_CHARS[] = "eE"; | |
232 | ||
233 | /* Chars that mean this number is a floating point constant */ | |
234 | /* As in 0f12.456 */ | |
235 | /* or 0d1.2345e12 */ | |
236 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
237 | ||
238 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
239 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
240 | but nothing is ideal around here. | |
241 | */ | |
242 | ||
670a50eb | 243 | static char *insn_error; |
3d3c5039 | 244 | |
22ba90ce | 245 | static int byte_order; |
3d3c5039 ILT |
246 | |
247 | static int auto_align = 1; | |
becfe05e ILT |
248 | |
249 | /* Symbol labelling the current insn. */ | |
250 | static symbolS *insn_label; | |
251 | ||
9226253a ILT |
252 | /* When outputting SVR4 PIC code, the assembler needs to know the |
253 | offset in the stack frame from which to restore the $gp register. | |
254 | This is set by the .cprestore pseudo-op, and saved in this | |
255 | variable. */ | |
0dd2d296 ILT |
256 | static offsetT mips_cprestore_offset = -1; |
257 | ||
258 | /* This is the register which holds the stack frame, as set by the | |
259 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
260 | static int mips_frame_reg = SP; | |
9226253a | 261 | |
becfe05e ILT |
262 | /* To output NOP instructions correctly, we need to keep information |
263 | about the previous two instructions. */ | |
264 | ||
0aa07269 ILT |
265 | /* Whether we are optimizing. The default value of 2 means to remove |
266 | unneeded NOPs and swap branch instructions when possible. A value | |
267 | of 1 means to not swap branches. A value of 0 means to always | |
268 | insert NOPs. */ | |
269 | static int mips_optimize = 2; | |
4e95866e | 270 | |
22ba90ce ILT |
271 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
272 | equivalent to seeing no -g option at all. */ | |
273 | static int mips_debug = 0; | |
274 | ||
becfe05e ILT |
275 | /* The previous instruction. */ |
276 | static struct mips_cl_insn prev_insn; | |
277 | ||
278 | /* The instruction before prev_insn. */ | |
279 | static struct mips_cl_insn prev_prev_insn; | |
280 | ||
281 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
282 | point the insn_mo field at this dummy integer. */ | |
283 | static const struct mips_opcode dummy_opcode = { 0 }; | |
284 | ||
285 | /* Non-zero if prev_insn is valid. */ | |
286 | static int prev_insn_valid; | |
287 | ||
288 | /* The frag for the previous instruction. */ | |
289 | static struct frag *prev_insn_frag; | |
290 | ||
291 | /* The offset into prev_insn_frag for the previous instruction. */ | |
292 | static long prev_insn_where; | |
293 | ||
294 | /* The reloc for the previous instruction, if any. */ | |
295 | static fixS *prev_insn_fixp; | |
296 | ||
297 | /* Non-zero if the previous instruction was in a delay slot. */ | |
298 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
299 | |
300 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
301 | static int prev_insn_unreordered; | |
302 | ||
303 | /* Non-zero if the previous previous instruction was in a .set | |
304 | noreorder. */ | |
305 | static int prev_prev_insn_unreordered; | |
867a58b3 ILT |
306 | |
307 | /* For ECOFF and ELF, relocations against symbols are done in two | |
308 | parts, with a HI relocation and a LO relocation. Each relocation | |
309 | has only 16 bits of space to store an addend. This means that in | |
310 | order for the linker to handle carries correctly, it must be able | |
311 | to locate both the HI and the LO relocation. This means that the | |
312 | relocations must appear in order in the relocation table. | |
313 | ||
314 | In order to implement this, we keep track of each unmatched HI | |
315 | relocation. We then sort them so that they immediately precede the | |
316 | corresponding LO relocation. */ | |
317 | ||
318 | struct mips_hi_fixup | |
319 | { | |
320 | /* Next HI fixup. */ | |
321 | struct mips_hi_fixup *next; | |
322 | /* This fixup. */ | |
323 | fixS *fixp; | |
324 | /* The section this fixup is in. */ | |
325 | segT seg; | |
326 | }; | |
327 | ||
328 | /* The list of unmatched HI relocs. */ | |
329 | ||
330 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
3d3c5039 | 331 | \f |
0dd2d296 ILT |
332 | /* Since the MIPS does not have multiple forms of PC relative |
333 | instructions, we do not have to do relaxing as is done on other | |
334 | platforms. However, we do have to handle GP relative addressing | |
335 | correctly, which turns out to be a similar problem. | |
336 | ||
337 | Every macro that refers to a symbol can occur in (at least) two | |
338 | forms, one with GP relative addressing and one without. For | |
339 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 340 | a macro instruction like this: |
0dd2d296 ILT |
341 | lw $4,i |
342 | If i can be addressed off the GP register (this is true if it is in | |
343 | the .sbss or .sdata section, or if it is known to be smaller than | |
344 | the -G argument) this will generate the following instruction: | |
345 | lw $4,i($gp) | |
346 | This instruction will use a GPREL reloc. If i can not be addressed | |
347 | off the GP register, the following instruction sequence will be used: | |
348 | lui $at,i | |
349 | lw $4,i($at) | |
350 | In this case the first instruction will have a HI16 reloc, and the | |
351 | second reloc will have a LO16 reloc. Both relocs will be against | |
352 | the symbol i. | |
353 | ||
354 | The issue here is that we may not know whether i is GP addressable | |
355 | until after we see the instruction that uses it. Therefore, we | |
356 | want to be able to choose the final instruction sequence only at | |
357 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 358 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
359 | end of assembly. |
360 | ||
361 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
362 | addressing in quite the same way, but the issue still arises as |
363 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
364 | |
365 | We handle these issues by actually generating both possible | |
366 | instruction sequences. The longer one is put in a frag_var with | |
367 | type rs_machine_dependent. We encode what to do with the frag in | |
368 | the subtype field. We encode (1) the number of existing bytes to | |
369 | replace, (2) the number of new bytes to use, (3) the offset from | |
370 | the start of the existing bytes to the first reloc we must generate | |
371 | (that is, the offset is applied from the start of the existing | |
372 | bytes after they are replaced by the new bytes, if any), (4) the | |
373 | offset from the start of the existing bytes to the second reloc, | |
374 | (5) whether a third reloc is needed (the third reloc is always four | |
375 | bytes after the second reloc), and (6) whether to warn if this | |
376 | variant is used (this is sometimes needed if .set nomacro or .set | |
377 | noat is in effect). All these numbers are reasonably small. | |
378 | ||
379 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
380 | ensure that delay slots are handled correctly. Fortunately, there |
381 | are a limited number of cases. When the second instruction | |
382 | sequence is generated, append_insn is directed to maintain the | |
383 | existing delay slot information, so it continues to apply to any | |
384 | code after the second instruction sequence. This means that the | |
385 | second instruction sequence must not impose any requirements not | |
386 | required by the first instruction sequence. | |
0dd2d296 ILT |
387 | |
388 | These variant frags are then handled in functions called by the | |
389 | machine independent code. md_estimate_size_before_relax returns | |
390 | the final size of the frag. md_convert_frag sets up the final form | |
391 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
392 | one if needed. */ | |
393 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
394 | ((relax_substateT) \ | |
395 | (((old) << 24) \ | |
396 | | ((new) << 16) \ | |
397 | | (((reloc1) + 64) << 9) \ | |
398 | | (((reloc2) + 64) << 2) \ | |
399 | | ((reloc3) ? (1 << 1) : 0) \ | |
400 | | ((warn) ? 1 : 0))) | |
401 | #define RELAX_OLD(i) (((i) >> 24) & 0xff) | |
402 | #define RELAX_NEW(i) (((i) >> 16) & 0xff) | |
483971bd KR |
403 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) |
404 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
0dd2d296 ILT |
405 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
406 | #define RELAX_WARN(i) ((i) & 1) | |
407 | \f | |
3d3c5039 ILT |
408 | /* Prototypes for static functions. */ |
409 | ||
410 | #ifdef __STDC__ | |
411 | #define internalError() \ | |
412 | as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__) | |
413 | #else | |
414 | #define internalError() as_fatal ("MIPS internal Error"); | |
415 | #endif | |
416 | ||
becfe05e | 417 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
604633ae | 418 | unsigned int reg, int fpr)); |
fb251650 | 419 | static int reg_needs_delay PARAMS ((int)); |
0dd2d296 ILT |
420 | static void append_insn PARAMS ((char *place, |
421 | struct mips_cl_insn * ip, | |
670a50eb | 422 | expressionS * p, |
867a58b3 ILT |
423 | bfd_reloc_code_real_type r, |
424 | boolean)); | |
becfe05e ILT |
425 | static void mips_no_prev_insn PARAMS ((void)); |
426 | static void mips_emit_delays PARAMS ((void)); | |
c625fc23 | 427 | #ifdef USE_STDARG |
0dd2d296 | 428 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
429 | const char *name, const char *fmt, |
430 | ...)); | |
c625fc23 JSC |
431 | #else |
432 | static void macro_build (); | |
433 | #endif | |
0dd2d296 ILT |
434 | static void macro_build_lui PARAMS ((char *place, int *counter, |
435 | expressionS * ep, int regnum)); | |
6e8dda9c | 436 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 437 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 438 | expressionS *)); |
d8a1c247 | 439 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
0dd2d296 | 440 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); |
670a50eb | 441 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
442 | #ifdef LOSING_COMPILER |
443 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
444 | #endif | |
670a50eb ILT |
445 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
446 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); | |
447 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 448 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 449 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 ILT |
450 | static void s_align PARAMS ((int)); |
451 | static void s_change_sec PARAMS ((int)); | |
452 | static void s_cons PARAMS ((int)); | |
3d3c5039 | 453 | static void s_float_cons PARAMS ((int)); |
c1444ec4 | 454 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
455 | static void s_option PARAMS ((int)); |
456 | static void s_mipsset PARAMS ((int)); | |
9226253a ILT |
457 | static void s_abicalls PARAMS ((int)); |
458 | static void s_cpload PARAMS ((int)); | |
459 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
460 | static void s_gpword PARAMS ((int)); |
461 | static void s_cpadd PARAMS ((int)); | |
3d3c5039 ILT |
462 | static void md_obj_begin PARAMS ((void)); |
463 | static void md_obj_end PARAMS ((void)); | |
464 | static long get_number PARAMS ((void)); | |
465 | static void s_ent PARAMS ((int)); | |
466 | static void s_mipsend PARAMS ((int)); | |
467 | static void s_file PARAMS ((int)); | |
3d3c5039 ILT |
468 | \f |
469 | /* Pseudo-op table. | |
470 | ||
471 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
472 | should be defined here, but are currently unsupported: .alias, | |
473 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
474 | ||
475 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
476 | specific to the type of debugging information being generated, and | |
477 | should be defined by the object format: .aent, .begin, .bend, | |
478 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
479 | .vreg. | |
480 | ||
481 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
482 | not MIPS CPU specific, but are also not specific to the object file | |
483 | format. This file is probably the best place to define them, but | |
484 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
485 | .struct, .weakext. */ | |
486 | ||
739708fa | 487 | static const pseudo_typeS mips_pseudo_table[] = |
3d3c5039 | 488 | { |
670a50eb ILT |
489 | /* MIPS specific pseudo-ops. */ |
490 | {"option", s_option, 0}, | |
491 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
492 | {"rdata", s_change_sec, 'r'}, |
493 | {"sdata", s_change_sec, 's'}, | |
494 | {"livereg", s_ignore, 0}, | |
739708fa KR |
495 | {"abicalls", s_abicalls, 0}, |
496 | {"cpload", s_cpload, 0}, | |
497 | {"cprestore", s_cprestore, 0}, | |
498 | {"gpword", s_gpword, 0}, | |
499 | {"cpadd", s_cpadd, 0}, | |
3d3c5039 | 500 | |
670a50eb | 501 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 502 | chips. */ |
739708fa | 503 | {"asciiz", stringer, 1}, |
670a50eb ILT |
504 | {"bss", s_change_sec, 'b'}, |
505 | {"err", s_err, 0}, | |
506 | {"half", s_cons, 1}, | |
52aa70b5 | 507 | {"dword", s_cons, 3}, |
3d3c5039 | 508 | |
670a50eb | 509 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 510 | here for one reason or another. */ |
670a50eb ILT |
511 | {"align", s_align, 0}, |
512 | {"byte", s_cons, 0}, | |
513 | {"data", s_change_sec, 'd'}, | |
becfe05e | 514 | {"double", s_float_cons, 'd'}, |
becfe05e | 515 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
516 | {"globl", s_mips_globl, 0}, |
517 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
518 | {"hword", s_cons, 1}, |
519 | {"int", s_cons, 2}, | |
520 | {"long", s_cons, 2}, | |
521 | {"octa", s_cons, 4}, | |
522 | {"quad", s_cons, 3}, | |
523 | {"short", s_cons, 1}, | |
524 | {"single", s_float_cons, 'f'}, | |
670a50eb ILT |
525 | {"text", s_change_sec, 't'}, |
526 | {"word", s_cons, 2}, | |
739708fa KR |
527 | { 0 }, |
528 | }; | |
3d3c5039 | 529 | |
739708fa | 530 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { |
670a50eb | 531 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 532 | However, a.out doesn't support them, so we have versions here. */ |
670a50eb | 533 | {"aent", s_ent, 1}, |
9226253a | 534 | {"bgnb", s_ignore, 0}, |
670a50eb | 535 | {"end", s_mipsend, 0}, |
9226253a | 536 | {"endb", s_ignore, 0}, |
670a50eb ILT |
537 | {"ent", s_ent, 0}, |
538 | {"file", s_file, 0}, | |
539 | {"fmask", s_ignore, 'F'}, | |
540 | {"frame", s_ignore, 0}, | |
541 | {"loc", s_ignore, 0}, | |
542 | {"mask", s_ignore, 'R'}, | |
543 | {"verstamp", s_ignore, 0}, | |
739708fa KR |
544 | { 0 }, |
545 | }; | |
61420a20 | 546 | |
739708fa KR |
547 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
548 | ||
549 | void | |
550 | mips_pop_insert () | |
551 | { | |
552 | pop_insert (mips_pseudo_table); | |
553 | if (! ECOFF_DEBUGGING) | |
554 | pop_insert (mips_nonecoff_pseudo_table); | |
739708fa | 555 | } |
3d3c5039 | 556 | \f |
3d3c5039 ILT |
557 | static char *expr_end; |
558 | ||
867a58b3 ILT |
559 | /* Expressions which appear in instructions. These are set by |
560 | mips_ip. */ | |
561 | ||
3d3c5039 ILT |
562 | static expressionS imm_expr; |
563 | static expressionS offset_expr; | |
867a58b3 ILT |
564 | |
565 | /* Relocs associated with imm_expr and offset_expr. */ | |
566 | ||
3d3c5039 ILT |
567 | static bfd_reloc_code_real_type imm_reloc; |
568 | static bfd_reloc_code_real_type offset_reloc; | |
569 | ||
867a58b3 ILT |
570 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ |
571 | ||
572 | static boolean imm_unmatched_hi; | |
573 | ||
3d3c5039 ILT |
574 | /* |
575 | * This function is called once, at assembler startup time. It should | |
576 | * set up all the tables, etc. that the MD part of the assembler will need. | |
577 | */ | |
578 | void | |
670a50eb | 579 | md_begin () |
3d3c5039 | 580 | { |
0dd2d296 | 581 | boolean ok = false; |
604633ae | 582 | register const char *retval = NULL; |
670a50eb | 583 | register unsigned int i = 0; |
3d3c5039 | 584 | |
8358c818 ILT |
585 | if (mips_isa == -1) |
586 | { | |
8c63448a ILT |
587 | const char *cpu; |
588 | char *a = NULL; | |
589 | ||
590 | cpu = TARGET_CPU; | |
591 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
592 | { | |
593 | a = xmalloc (sizeof TARGET_CPU); | |
594 | strcpy (a, TARGET_CPU); | |
595 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
596 | cpu = a; | |
597 | } | |
598 | ||
599 | if (strcmp (cpu, "mips") == 0) | |
600 | { | |
601 | mips_isa = 1; | |
4bb0cc41 ILT |
602 | if (mips_cpu == -1) |
603 | mips_cpu = 3000; | |
8c63448a ILT |
604 | } |
605 | else if (strcmp (cpu, "r6000") == 0 | |
606 | || strcmp (cpu, "mips2") == 0) | |
607 | { | |
608 | mips_isa = 2; | |
4bb0cc41 ILT |
609 | if (mips_cpu == -1) |
610 | mips_cpu = 6000; | |
8c63448a ILT |
611 | } |
612 | else if (strcmp (cpu, "mips64") == 0 | |
613 | || strcmp (cpu, "r4000") == 0 | |
614 | || strcmp (cpu, "mips3") == 0) | |
615 | { | |
616 | mips_isa = 3; | |
4bb0cc41 ILT |
617 | if (mips_cpu == -1) |
618 | mips_cpu = 4000; | |
8c63448a ILT |
619 | } |
620 | else if (strcmp (cpu, "r4400") == 0) | |
621 | { | |
622 | mips_isa = 3; | |
4bb0cc41 ILT |
623 | if (mips_cpu == -1) |
624 | mips_cpu = 4400; | |
8c63448a ILT |
625 | } |
626 | else if (strcmp (cpu, "mips64orion") == 0 | |
627 | || strcmp (cpu, "r4600") == 0) | |
628 | { | |
629 | mips_isa = 3; | |
4bb0cc41 ILT |
630 | if (mips_cpu == -1) |
631 | mips_cpu = 4600; | |
8c63448a | 632 | } |
b2b8c24e ILT |
633 | else if (strcmp (cpu, "r4650") == 0) |
634 | { | |
635 | mips_isa = 3; | |
636 | if (mips_cpu == -1) | |
637 | mips_cpu = 4650; | |
638 | if (mips_4650 == -1) | |
639 | mips_4650 = 1; | |
640 | } | |
c625fc23 JSC |
641 | else if (strcmp (cpu, "mips64vr4300") == 0) |
642 | { | |
643 | mips_isa = 3; | |
644 | if (mips_cpu == -1) | |
645 | mips_cpu = 4300; | |
646 | } | |
647 | else if (strcmp (cpu, "mips64vr4100") == 0) | |
648 | { | |
649 | mips_isa = 3; | |
650 | if (mips_cpu == -1) | |
651 | mips_cpu = 4100; | |
652 | if (mips_4100 == -1) | |
653 | mips_4100 = 1; | |
654 | } | |
e532b44c ILT |
655 | else if (strcmp (cpu, "r4010") == 0) |
656 | { | |
657 | mips_isa = 2; | |
658 | if (mips_cpu == -1) | |
659 | mips_cpu = 4010; | |
660 | if (mips_4010 == -1) | |
661 | mips_4010 = 1; | |
662 | } | |
517078c1 ILT |
663 | else if (strcmp (cpu, "r5000") == 0 |
664 | || strcmp (cpu, "mips64vr5000") == 0) | |
665 | { | |
666 | mips_isa = 4; | |
667 | if (mips_cpu == -1) | |
668 | mips_cpu = 5000; | |
669 | } | |
d8a1c247 KR |
670 | else if (strcmp (cpu, "r8000") == 0 |
671 | || strcmp (cpu, "mips4") == 0) | |
672 | { | |
673 | mips_isa = 4; | |
674 | if (mips_cpu == -1) | |
675 | mips_cpu = 8000; | |
676 | } | |
677 | else if (strcmp (cpu, "r10000") == 0) | |
678 | { | |
679 | mips_isa = 4; | |
680 | if (mips_cpu == -1) | |
681 | mips_cpu = 10000; | |
682 | } | |
8358c818 | 683 | else |
8c63448a ILT |
684 | { |
685 | mips_isa = 1; | |
4bb0cc41 ILT |
686 | if (mips_cpu == -1) |
687 | mips_cpu = 3000; | |
8c63448a ILT |
688 | } |
689 | ||
690 | if (a != NULL) | |
691 | free (a); | |
8358c818 ILT |
692 | } |
693 | ||
b2b8c24e ILT |
694 | if (mips_4650 < 0) |
695 | mips_4650 = 0; | |
696 | ||
e532b44c ILT |
697 | if (mips_4010 < 0) |
698 | mips_4010 = 0; | |
699 | ||
c625fc23 JSC |
700 | if (mips_4100 < 0) |
701 | mips_4100 = 0; | |
702 | ||
ca296aab | 703 | if (mips_4650 || mips_4010 || mips_4100 || mips_cpu == 4300) |
e532b44c ILT |
704 | interlocks = 1; |
705 | else | |
706 | interlocks = 0; | |
707 | ||
ca296aab | 708 | if (mips_cpu == 4300) |
344a8d61 JSC |
709 | cop_interlocks = 1; |
710 | else | |
711 | cop_interlocks = 0; | |
712 | ||
8ea7f4e8 ILT |
713 | if (mips_isa < 2 && mips_trap) |
714 | as_bad ("trap exception not supported at ISA 1"); | |
715 | ||
97f99d11 ILT |
716 | switch (mips_isa) |
717 | { | |
718 | case 1: | |
719 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
720 | break; | |
721 | case 2: | |
722 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
723 | break; | |
724 | case 3: | |
725 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
726 | break; | |
d8a1c247 KR |
727 | case 4: |
728 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
729 | break; | |
97f99d11 ILT |
730 | } |
731 | if (! ok) | |
732 | as_warn ("Could not set architecture and machine"); | |
733 | ||
1051c97f ILT |
734 | file_mips_isa = mips_isa; |
735 | ||
13fe1379 ILT |
736 | op_hash = hash_new (); |
737 | ||
670a50eb ILT |
738 | for (i = 0; i < NUMOPCODES;) |
739 | { | |
740 | const char *name = mips_opcodes[i].name; | |
741 | ||
604633ae | 742 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 743 | if (retval != NULL) |
670a50eb ILT |
744 | { |
745 | fprintf (stderr, "internal error: can't hash `%s': %s\n", | |
746 | mips_opcodes[i].name, retval); | |
747 | as_fatal ("Broken assembler. No assembly attempted."); | |
748 | } | |
749 | do | |
750 | { | |
8358c818 ILT |
751 | if (mips_opcodes[i].pinfo != INSN_MACRO |
752 | && ((mips_opcodes[i].match & mips_opcodes[i].mask) | |
753 | != mips_opcodes[i].match)) | |
670a50eb ILT |
754 | { |
755 | fprintf (stderr, "internal error: bad opcode: `%s' \"%s\"\n", | |
756 | mips_opcodes[i].name, mips_opcodes[i].args); | |
757 | as_fatal ("Broken assembler. No assembly attempted."); | |
3d3c5039 | 758 | } |
670a50eb ILT |
759 | ++i; |
760 | } | |
761 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
762 | } |
763 | ||
becfe05e ILT |
764 | mips_no_prev_insn (); |
765 | ||
1aa6938e ILT |
766 | mips_gprmask = 0; |
767 | mips_cprmask[0] = 0; | |
768 | mips_cprmask[1] = 0; | |
769 | mips_cprmask[2] = 0; | |
770 | mips_cprmask[3] = 0; | |
771 | ||
8358c818 ILT |
772 | /* set the default alignment for the text section (2**2) */ |
773 | record_alignment (text_section, 2); | |
774 | ||
1dc1e798 KR |
775 | if (USE_GLOBAL_POINTER_OPT) |
776 | bfd_set_gp_size (stdoutput, g_switch_value); | |
abdad6bc | 777 | |
1dc1e798 KR |
778 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
779 | { | |
780 | /* Sections must be aligned to 16 byte boundaries. */ | |
781 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
782 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
783 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
784 | ||
785 | /* Create a .reginfo section for register masks and a .mdebug | |
786 | section for debugging information. */ | |
787 | { | |
788 | segT seg; | |
789 | subsegT subseg; | |
790 | segT sec; | |
791 | ||
792 | seg = now_seg; | |
793 | subseg = now_subseg; | |
1dc1e798 | 794 | |
87178180 ILT |
795 | if (! mips_64) |
796 | { | |
797 | sec = subseg_new (".reginfo", (subsegT) 0); | |
8358c818 | 798 | |
87178180 ILT |
799 | /* The ABI says this section should be loaded so that the |
800 | running program can access it. */ | |
801 | (void) bfd_set_section_flags (stdoutput, sec, | |
802 | (SEC_ALLOC | SEC_LOAD | |
803 | | SEC_READONLY | SEC_DATA)); | |
804 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
805 | ||
f2a663d3 | 806 | #ifdef OBJ_ELF |
87178180 | 807 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
1dc1e798 | 808 | #endif |
87178180 ILT |
809 | } |
810 | else | |
811 | { | |
812 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
813 | .reginfo section. */ | |
814 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
815 | (void) bfd_set_section_flags (stdoutput, sec, | |
816 | (SEC_ALLOC | SEC_LOAD | |
817 | | SEC_READONLY | SEC_DATA)); | |
818 | (void) bfd_set_section_alignment (stdoutput, sec, 3); | |
819 | ||
820 | #ifdef OBJ_ELF | |
821 | /* Set up the option header. */ | |
822 | { | |
823 | Elf_Internal_Options opthdr; | |
824 | char *f; | |
825 | ||
826 | opthdr.kind = ODK_REGINFO; | |
827 | opthdr.size = (sizeof (Elf_External_Options) | |
828 | + sizeof (Elf64_External_RegInfo)); | |
829 | opthdr.section = 0; | |
830 | opthdr.info = 0; | |
831 | f = frag_more (sizeof (Elf_External_Options)); | |
832 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
833 | (Elf_External_Options *) f); | |
834 | ||
835 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
836 | } | |
837 | #endif | |
838 | } | |
f2a663d3 | 839 | |
739708fa KR |
840 | if (ECOFF_DEBUGGING) |
841 | { | |
842 | sec = subseg_new (".mdebug", (subsegT) 0); | |
843 | (void) bfd_set_section_flags (stdoutput, sec, | |
844 | SEC_HAS_CONTENTS | SEC_READONLY); | |
845 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
846 | } | |
0dd2d296 | 847 | |
1dc1e798 KR |
848 | subseg_set (seg, subseg); |
849 | } | |
850 | } | |
f2a663d3 | 851 | |
739708fa KR |
852 | if (! ECOFF_DEBUGGING) |
853 | md_obj_begin (); | |
3d3c5039 ILT |
854 | } |
855 | ||
856 | void | |
13fe1379 | 857 | md_mips_end () |
3d3c5039 | 858 | { |
739708fa KR |
859 | if (! ECOFF_DEBUGGING) |
860 | md_obj_end (); | |
3d3c5039 ILT |
861 | } |
862 | ||
863 | void | |
670a50eb ILT |
864 | md_assemble (str) |
865 | char *str; | |
3d3c5039 | 866 | { |
670a50eb | 867 | struct mips_cl_insn insn; |
3d3c5039 | 868 | |
5ac34ac3 | 869 | imm_expr.X_op = O_absent; |
867a58b3 ILT |
870 | imm_reloc = BFD_RELOC_UNUSED; |
871 | imm_unmatched_hi = false; | |
5ac34ac3 | 872 | offset_expr.X_op = O_absent; |
867a58b3 | 873 | offset_reloc = BFD_RELOC_UNUSED; |
3d3c5039 | 874 | |
670a50eb ILT |
875 | mips_ip (str, &insn); |
876 | if (insn_error) | |
877 | { | |
878 | as_bad ("%s `%s'", insn_error, str); | |
879 | return; | |
880 | } | |
881 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
882 | { | |
883 | macro (&insn); | |
3d3c5039 | 884 | } |
670a50eb ILT |
885 | else |
886 | { | |
5ac34ac3 | 887 | if (imm_expr.X_op != O_absent) |
867a58b3 ILT |
888 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, |
889 | imm_unmatched_hi); | |
5ac34ac3 | 890 | else if (offset_expr.X_op != O_absent) |
867a58b3 | 891 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); |
670a50eb | 892 | else |
867a58b3 | 893 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); |
3d3c5039 ILT |
894 | } |
895 | } | |
896 | ||
becfe05e ILT |
897 | /* See whether instruction IP reads register REG. If FPR is non-zero, |
898 | REG is a floating point register. */ | |
899 | ||
900 | static int | |
901 | insn_uses_reg (ip, reg, fpr) | |
902 | struct mips_cl_insn *ip; | |
604633ae | 903 | unsigned int reg; |
becfe05e ILT |
904 | int fpr; |
905 | { | |
906 | /* Don't report on general register 0, since it never changes. */ | |
907 | if (! fpr && reg == 0) | |
908 | return 0; | |
909 | ||
910 | if (fpr) | |
911 | { | |
912 | /* If we are called with either $f0 or $f1, we must check $f0. | |
913 | This is not optimal, because it will introduce an unnecessary | |
914 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
915 | need to distinguish reading both $f0 and $f1 or just one of | |
916 | them. Note that we don't have to check the other way, | |
917 | because there is no instruction that sets both $f0 and $f1 | |
918 | and requires a delay. */ | |
919 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
604633ae ILT |
920 | && (((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) |
921 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
922 | return 1; |
923 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
604633ae ILT |
924 | && (((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) |
925 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
926 | return 1; |
927 | } | |
928 | else | |
929 | { | |
930 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
931 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
932 | return 1; | |
933 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
934 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
935 | return 1; | |
936 | } | |
937 | ||
938 | return 0; | |
939 | } | |
940 | ||
fb251650 ILT |
941 | /* This function returns true if modifying a register requires a |
942 | delay. */ | |
943 | ||
944 | static int | |
945 | reg_needs_delay (reg) | |
946 | int reg; | |
947 | { | |
948 | unsigned long prev_pinfo; | |
949 | ||
950 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
951 | if (! mips_noreorder | |
952 | && mips_isa < 4 | |
953 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
954 | || (mips_isa < 2 | |
955 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
956 | { | |
957 | /* A load from a coprocessor or from memory. All load | |
958 | delays delay the use of general register rt for one | |
959 | instruction on the r3000. The r6000 and r4000 use | |
960 | interlocks. */ | |
961 | know (prev_pinfo & INSN_WRITE_GPR_T); | |
962 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
963 | return 1; | |
964 | } | |
965 | ||
966 | return 0; | |
967 | } | |
968 | ||
0dd2d296 ILT |
969 | /* Output an instruction. PLACE is where to put the instruction; if |
970 | it is NULL, this uses frag_more to get room. IP is the instruction | |
971 | information. ADDRESS_EXPR is an operand of the instruction to be | |
972 | used with RELOC_TYPE. */ | |
3d3c5039 | 973 | |
3d3c5039 | 974 | static void |
867a58b3 | 975 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) |
0dd2d296 | 976 | char *place; |
670a50eb ILT |
977 | struct mips_cl_insn *ip; |
978 | expressionS *address_expr; | |
979 | bfd_reloc_code_real_type reloc_type; | |
867a58b3 | 980 | boolean unmatched_hi; |
3d3c5039 | 981 | { |
1aa6938e | 982 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 983 | char *f; |
becfe05e ILT |
984 | fixS *fixp; |
985 | int nops = 0; | |
3d3c5039 | 986 | |
1aa6938e ILT |
987 | prev_pinfo = prev_insn.insn_mo->pinfo; |
988 | pinfo = ip->insn_mo->pinfo; | |
989 | ||
0dd2d296 | 990 | if (place == NULL && ! mips_noreorder) |
becfe05e ILT |
991 | { |
992 | /* If the previous insn required any delay slots, see if we need | |
8358c818 | 993 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 994 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
995 | (1) a load from memory delay |
996 | (2) a load from a coprocessor delay | |
997 | (3) an unconditional branch delay | |
998 | (4) a conditional branch delay | |
999 | (5) a move to coprocessor register delay | |
1000 | (6) a load coprocessor register from memory delay | |
1001 | (7) a coprocessor condition code delay | |
1002 | (8) a HI/LO special register delay | |
becfe05e ILT |
1003 | |
1004 | There are a lot of optimizations we could do that we don't. | |
1005 | In particular, we do not, in general, reorder instructions. | |
1006 | If you use gcc with optimization, it will reorder | |
1007 | instructions and generally do much more optimization then we | |
1008 | do here; repeating all that work in the assembler would only | |
1009 | benefit hand written assembly code, and does not seem worth | |
1010 | it. */ | |
1011 | ||
1012 | /* This is how a NOP is emitted. */ | |
1013 | #define emit_nop() md_number_to_chars (frag_more (4), 0, 4) | |
1014 | ||
1015 | /* The previous insn might require a delay slot, depending upon | |
1016 | the contents of the current insn. */ | |
d8a1c247 | 1017 | if (mips_isa < 4 |
5af96dce ILT |
1018 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1019 | && ! cop_interlocks) | |
d8a1c247 KR |
1020 | || (mips_isa < 2 |
1021 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
8358c818 ILT |
1022 | { |
1023 | /* A load from a coprocessor or from memory. All load | |
1024 | delays delay the use of general register rt for one | |
1025 | instruction on the r3000. The r6000 and r4000 use | |
1026 | interlocks. */ | |
1aa6938e | 1027 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
1028 | if (mips_optimize == 0 |
1029 | || insn_uses_reg (ip, | |
1030 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1031 | & OP_MASK_RT), | |
1032 | 0)) | |
becfe05e ILT |
1033 | ++nops; |
1034 | } | |
d8a1c247 | 1035 | else if (mips_isa < 4 |
5af96dce ILT |
1036 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
1037 | && ! cop_interlocks) | |
d8a1c247 KR |
1038 | || (mips_isa < 2 |
1039 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
1040 | { |
1041 | /* A generic coprocessor delay. The previous instruction | |
1042 | modified a coprocessor general or control register. If | |
1043 | it modified a control register, we need to avoid any | |
1044 | coprocessor instruction (this is probably not always | |
1045 | required, but it sometimes is). If it modified a general | |
1046 | register, we avoid using that register. | |
1047 | ||
8358c818 ILT |
1048 | On the r6000 and r4000 loading a coprocessor register |
1049 | from memory is interlocked, and does not require a delay. | |
1050 | ||
becfe05e ILT |
1051 | This case is not handled very well. There is no special |
1052 | knowledge of CP0 handling, and the coprocessors other | |
1053 | than the floating point unit are not distinguished at | |
1054 | all. */ | |
1aa6938e | 1055 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 1056 | { |
0aa07269 ILT |
1057 | if (mips_optimize == 0 |
1058 | || insn_uses_reg (ip, | |
8358c818 ILT |
1059 | ((prev_insn.insn_opcode >> OP_SH_FT) |
1060 | & OP_MASK_FT), | |
0aa07269 | 1061 | 1)) |
becfe05e ILT |
1062 | ++nops; |
1063 | } | |
1aa6938e | 1064 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 1065 | { |
0aa07269 ILT |
1066 | if (mips_optimize == 0 |
1067 | || insn_uses_reg (ip, | |
8358c818 ILT |
1068 | ((prev_insn.insn_opcode >> OP_SH_FS) |
1069 | & OP_MASK_FS), | |
0aa07269 | 1070 | 1)) |
becfe05e ILT |
1071 | ++nops; |
1072 | } | |
1073 | else | |
1074 | { | |
1075 | /* We don't know exactly what the previous instruction | |
1076 | does. If the current instruction uses a coprocessor | |
1077 | register, we must insert a NOP. If previous | |
1078 | instruction may set the condition codes, and the | |
1079 | current instruction uses them, we must insert two | |
1080 | NOPS. */ | |
0aa07269 | 1081 | if (mips_optimize == 0 |
1aa6938e ILT |
1082 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
1083 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 1084 | nops += 2; |
1aa6938e | 1085 | else if (pinfo & INSN_COP) |
becfe05e ILT |
1086 | ++nops; |
1087 | } | |
1088 | } | |
d8a1c247 | 1089 | else if (mips_isa < 4 |
344a8d61 JSC |
1090 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1091 | && ! cop_interlocks) | |
becfe05e ILT |
1092 | { |
1093 | /* The previous instruction sets the coprocessor condition | |
1094 | codes, but does not require a general coprocessor delay | |
1095 | (this means it is a floating point comparison | |
1096 | instruction). If this instruction uses the condition | |
1097 | codes, we need to insert a single NOP. */ | |
0aa07269 | 1098 | if (mips_optimize == 0 |
1aa6938e | 1099 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1100 | ++nops; |
1101 | } | |
1aa6938e | 1102 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
1103 | { |
1104 | /* The previous instruction reads the LO register; if the | |
1105 | current instruction writes to the LO register, we must | |
517078c1 | 1106 | insert two NOPS. Some newer processors have interlocks. */ |
e532b44c | 1107 | if (! interlocks |
b2b8c24e ILT |
1108 | && (mips_optimize == 0 |
1109 | || (pinfo & INSN_WRITE_LO))) | |
becfe05e ILT |
1110 | nops += 2; |
1111 | } | |
1112 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1113 | { | |
1114 | /* The previous instruction reads the HI register; if the | |
1115 | current instruction writes to the HI register, we must | |
517078c1 | 1116 | insert a NOP. Some newer processors have interlocks. */ |
e532b44c | 1117 | if (! interlocks |
b2b8c24e ILT |
1118 | && (mips_optimize == 0 |
1119 | || (pinfo & INSN_WRITE_HI))) | |
becfe05e ILT |
1120 | nops += 2; |
1121 | } | |
1122 | ||
1123 | /* There are two cases which require two intervening | |
1124 | instructions: 1) setting the condition codes using a move to | |
1125 | coprocessor instruction which requires a general coprocessor | |
1126 | delay and then reading the condition codes 2) reading the HI | |
517078c1 ILT |
1127 | or LO register and then writing to it (except on processors |
1128 | which have interlocks). If we are not already emitting a NOP | |
1129 | instruction, we must check for these cases compared to the | |
1130 | instruction previous to the previous instruction. */ | |
becfe05e | 1131 | if (nops == 0 |
d8a1c247 KR |
1132 | && ((mips_isa < 4 |
1133 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) | |
becfe05e | 1134 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
344a8d61 JSC |
1135 | && (pinfo & INSN_READ_COND_CODE) |
1136 | && ! cop_interlocks) | |
becfe05e | 1137 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) |
b2b8c24e | 1138 | && (pinfo & INSN_WRITE_LO) |
e532b44c | 1139 | && ! interlocks) |
becfe05e | 1140 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
b2b8c24e | 1141 | && (pinfo & INSN_WRITE_HI) |
e532b44c | 1142 | && ! interlocks))) |
becfe05e ILT |
1143 | ++nops; |
1144 | ||
0dd2d296 ILT |
1145 | /* If we are being given a nop instruction, don't bother with |
1146 | one of the nops we would otherwise output. This will only | |
1147 | happen when a nop instruction is used with mips_optimize set | |
1148 | to 0. */ | |
1149 | if (nops > 0 && ip->insn_opcode == 0) | |
1150 | --nops; | |
1151 | ||
becfe05e ILT |
1152 | /* Now emit the right number of NOP instructions. */ |
1153 | if (nops > 0) | |
1154 | { | |
5af96dce ILT |
1155 | fragS *old_frag; |
1156 | unsigned long old_frag_offset; | |
8c63448a ILT |
1157 | int i; |
1158 | ||
5af96dce ILT |
1159 | old_frag = frag_now; |
1160 | old_frag_offset = frag_now_fix (); | |
1161 | ||
8c63448a | 1162 | for (i = 0; i < nops; i++) |
becfe05e | 1163 | emit_nop (); |
5af96dce | 1164 | |
af255ca0 | 1165 | if (listing) |
546f5536 ILT |
1166 | { |
1167 | listing_prev_line (); | |
1168 | /* We may be at the start of a variant frag. In case we | |
1169 | are, make sure there is enough space for the frag | |
1170 | after the frags created by listing_prev_line. The | |
1171 | argument to frag_grow here must be at least as large | |
1172 | as the argument to all other calls to frag_grow in | |
1173 | this file. We don't have to worry about being in the | |
1174 | middle of a variant frag, because the variants insert | |
1175 | all needed nop instructions themselves. */ | |
1176 | frag_grow (40); | |
1177 | } | |
5af96dce | 1178 | |
becfe05e ILT |
1179 | if (insn_label != NULL) |
1180 | { | |
1181 | assert (S_GET_SEGMENT (insn_label) == now_seg); | |
1182 | insn_label->sy_frag = frag_now; | |
604633ae | 1183 | S_SET_VALUE (insn_label, (valueT) frag_now_fix ()); |
becfe05e | 1184 | } |
5af96dce ILT |
1185 | |
1186 | #ifndef NO_ECOFF_DEBUGGING | |
1187 | if (ECOFF_DEBUGGING) | |
1188 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1189 | #endif | |
becfe05e ILT |
1190 | } |
1191 | } | |
1192 | ||
0dd2d296 ILT |
1193 | if (place == NULL) |
1194 | f = frag_more (4); | |
1195 | else | |
1196 | f = place; | |
becfe05e | 1197 | fixp = NULL; |
670a50eb ILT |
1198 | if (address_expr != NULL) |
1199 | { | |
5ac34ac3 | 1200 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
1201 | { |
1202 | switch (reloc_type) | |
1203 | { | |
3d3c5039 | 1204 | case BFD_RELOC_32: |
670a50eb ILT |
1205 | ip->insn_opcode |= address_expr->X_add_number; |
1206 | break; | |
3d3c5039 ILT |
1207 | |
1208 | case BFD_RELOC_LO16: | |
670a50eb ILT |
1209 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
1210 | break; | |
3d3c5039 ILT |
1211 | |
1212 | case BFD_RELOC_MIPS_JMP: | |
5e1e8f23 ILT |
1213 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
1214 | break; | |
1215 | ||
3d3c5039 | 1216 | case BFD_RELOC_16_PCREL_S2: |
670a50eb | 1217 | goto need_reloc; |
3d3c5039 ILT |
1218 | |
1219 | default: | |
670a50eb | 1220 | internalError (); |
3d3c5039 | 1221 | } |
670a50eb ILT |
1222 | } |
1223 | else | |
1224 | { | |
1225 | assert (reloc_type != BFD_RELOC_UNUSED); | |
3d3c5039 | 1226 | need_reloc: |
0dd2d296 ILT |
1227 | /* Don't generate a reloc if we are writing into a variant |
1228 | frag. */ | |
1229 | if (place == NULL) | |
867a58b3 ILT |
1230 | { |
1231 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1232 | address_expr, | |
1233 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1234 | reloc_type); | |
1235 | if (unmatched_hi) | |
1236 | { | |
1237 | struct mips_hi_fixup *hi_fixup; | |
1238 | ||
1239 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1240 | hi_fixup = ((struct mips_hi_fixup *) | |
1241 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1242 | hi_fixup->fixp = fixp; | |
1243 | hi_fixup->seg = now_seg; | |
1244 | hi_fixup->next = mips_hi_fixup_list; | |
1245 | mips_hi_fixup_list = hi_fixup; | |
1246 | } | |
1247 | } | |
3d3c5039 ILT |
1248 | } |
1249 | } | |
becfe05e | 1250 | |
670a50eb ILT |
1251 | md_number_to_chars (f, ip->insn_opcode, 4); |
1252 | ||
1aa6938e ILT |
1253 | /* Update the register mask information. */ |
1254 | if (pinfo & INSN_WRITE_GPR_D) | |
1255 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1256 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1257 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1258 | if (pinfo & INSN_READ_GPR_S) | |
1259 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1260 | if (pinfo & INSN_WRITE_GPR_31) | |
1261 | mips_gprmask |= 1 << 31; | |
1262 | if (pinfo & INSN_WRITE_FPR_D) | |
1263 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1264 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1265 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1266 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1267 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
d8a1c247 KR |
1268 | if ((pinfo & INSN_READ_FPR_R) != 0) |
1269 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1aa6938e ILT |
1270 | if (pinfo & INSN_COP) |
1271 | { | |
1272 | /* We don't keep enough information to sort these cases out. */ | |
1273 | } | |
1274 | /* Never set the bit for $0, which is always zero. */ | |
1275 | mips_gprmask &=~ 1 << 0; | |
1276 | ||
0dd2d296 | 1277 | if (place == NULL && ! mips_noreorder) |
670a50eb | 1278 | { |
becfe05e ILT |
1279 | /* Filling the branch delay slot is more complex. We try to |
1280 | switch the branch with the previous instruction, which we can | |
1281 | do if the previous instruction does not set up a condition | |
1282 | that the branch tests and if the branch is not itself the | |
1283 | target of any branch. */ | |
1aa6938e ILT |
1284 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
1285 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 1286 | { |
0aa07269 | 1287 | if (mips_optimize < 2 |
19ed8960 ILT |
1288 | /* If we have seen .set volatile or .set nomove, don't |
1289 | optimize. */ | |
1290 | || mips_nomove != 0 | |
4e95866e ILT |
1291 | /* If we had to emit any NOP instructions, then we |
1292 | already know we can not swap. */ | |
1293 | || nops != 0 | |
becfe05e ILT |
1294 | /* If we don't even know the previous insn, we can not |
1295 | swap. */ | |
1296 | || ! prev_insn_valid | |
1297 | /* If the previous insn is already in a branch delay | |
1298 | slot, then we can not swap. */ | |
1299 | || prev_insn_is_delay_slot | |
4e95866e ILT |
1300 | /* If the previous previous insn was in a .set |
1301 | noreorder, we can't swap. Actually, the MIPS | |
1302 | assembler will swap in this situation. However, gcc | |
1303 | configured -with-gnu-as will generate code like | |
1304 | .set noreorder | |
1305 | lw $4,XXX | |
1306 | .set reorder | |
1307 | INSN | |
1308 | bne $4,$0,foo | |
1309 | in which we can not swap the bne and INSN. If gcc is | |
1310 | not configured -with-gnu-as, it does not output the | |
1311 | .set pseudo-ops. We don't have to check | |
1312 | prev_insn_unreordered, because prev_insn_valid will | |
1313 | be 0 in that case. We don't want to use | |
1314 | prev_prev_insn_valid, because we do want to be able | |
1315 | to swap at the start of a function. */ | |
1316 | || prev_prev_insn_unreordered | |
becfe05e ILT |
1317 | /* If the branch is itself the target of a branch, we |
1318 | can not swap. We cheat on this; all we check for is | |
1319 | whether there is a label on this instruction. If | |
1320 | there are any branches to anything other than a | |
1321 | label, users must use .set noreorder. */ | |
1322 | || insn_label != NULL | |
777ad64d ILT |
1323 | /* If the previous instruction is in a variant frag, we |
1324 | can not do the swap. */ | |
1325 | || prev_insn_frag->fr_type == rs_machine_dependent | |
becfe05e ILT |
1326 | /* If the branch reads the condition codes, we don't |
1327 | even try to swap, because in the sequence | |
1328 | ctc1 $X,$31 | |
1329 | INSN | |
1330 | INSN | |
1331 | bc1t LABEL | |
1332 | we can not swap, and I don't feel like handling that | |
1333 | case. */ | |
d8a1c247 KR |
1334 | || (mips_isa < 4 |
1335 | && (pinfo & INSN_READ_COND_CODE)) | |
becfe05e ILT |
1336 | /* We can not swap with an instruction that requires a |
1337 | delay slot, becase the target of the branch might | |
1338 | interfere with that instruction. */ | |
d8a1c247 KR |
1339 | || (mips_isa < 4 |
1340 | && (prev_pinfo | |
1341 | & (INSN_LOAD_COPROC_DELAY | |
1342 | | INSN_COPROC_MOVE_DELAY | |
1343 | | INSN_WRITE_COND_CODE))) | |
e532b44c | 1344 | || (! interlocks |
b2b8c24e ILT |
1345 | && (prev_pinfo |
1346 | & (INSN_READ_LO | |
1347 | | INSN_READ_HI))) | |
8358c818 | 1348 | || (mips_isa < 2 |
1aa6938e | 1349 | && (prev_pinfo |
8358c818 ILT |
1350 | & (INSN_LOAD_MEMORY_DELAY |
1351 | | INSN_COPROC_MEMORY_DELAY))) | |
becfe05e | 1352 | /* We can not swap with a branch instruction. */ |
1aa6938e | 1353 | || (prev_pinfo |
6e8dda9c ILT |
1354 | & (INSN_UNCOND_BRANCH_DELAY |
1355 | | INSN_COND_BRANCH_DELAY | |
1356 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
1357 | /* We do not swap with a trap instruction, since it |
1358 | complicates trap handlers to have the trap | |
1359 | instruction be in a delay slot. */ | |
1aa6938e | 1360 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
1361 | /* If the branch reads a register that the previous |
1362 | instruction sets, we can not swap. */ | |
1aa6938e | 1363 | || ((prev_pinfo & INSN_WRITE_GPR_T) |
becfe05e ILT |
1364 | && insn_uses_reg (ip, |
1365 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1366 | & OP_MASK_RT), | |
1367 | 0)) | |
1aa6938e | 1368 | || ((prev_pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
1369 | && insn_uses_reg (ip, |
1370 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
1371 | & OP_MASK_RD), | |
1372 | 0)) | |
1849d646 ILT |
1373 | /* If the branch writes a register that the previous |
1374 | instruction sets, we can not swap (we know that | |
1375 | branches write only to RD or to $31). */ | |
1aa6938e ILT |
1376 | || ((prev_pinfo & INSN_WRITE_GPR_T) |
1377 | && (((pinfo & INSN_WRITE_GPR_D) | |
1849d646 ILT |
1378 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
1379 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1380 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1381 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
1382 | & OP_MASK_RT) | |
1383 | == 31)))) | |
1aa6938e ILT |
1384 | || ((prev_pinfo & INSN_WRITE_GPR_D) |
1385 | && (((pinfo & INSN_WRITE_GPR_D) | |
1849d646 ILT |
1386 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
1387 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1388 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1389 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
1390 | & OP_MASK_RD) | |
1391 | == 31)))) | |
becfe05e ILT |
1392 | /* If the branch writes a register that the previous |
1393 | instruction reads, we can not swap (we know that | |
1394 | branches only write to RD or to $31). */ | |
1aa6938e | 1395 | || ((pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
1396 | && insn_uses_reg (&prev_insn, |
1397 | ((ip->insn_opcode >> OP_SH_RD) | |
1398 | & OP_MASK_RD), | |
1399 | 0)) | |
1aa6938e | 1400 | || ((pinfo & INSN_WRITE_GPR_31) |
becfe05e | 1401 | && insn_uses_reg (&prev_insn, 31, 0)) |
5b63f465 ILT |
1402 | /* If we are generating embedded PIC code, the branch |
1403 | might be expanded into a sequence which uses $at, so | |
1404 | we can't swap with an instruction which reads it. */ | |
1405 | || (mips_pic == EMBEDDED_PIC | |
1406 | && insn_uses_reg (&prev_insn, AT, 0)) | |
becfe05e ILT |
1407 | /* If the previous previous instruction has a load |
1408 | delay, and sets a register that the branch reads, we | |
1409 | can not swap. */ | |
d8a1c247 KR |
1410 | || (mips_isa < 4 |
1411 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) | |
1412 | || (mips_isa < 2 | |
1413 | && (prev_prev_insn.insn_mo->pinfo | |
1414 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
1415 | && insn_uses_reg (ip, |
1416 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
1417 | & OP_MASK_RT), | |
d31a3f5e ILT |
1418 | 0)) |
1419 | /* If one instruction sets a condition code and the | |
1420 | other one uses a condition code, we can not swap. */ | |
1421 | || ((pinfo & INSN_READ_COND_CODE) | |
1422 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
1423 | || ((pinfo & INSN_WRITE_COND_CODE) | |
1424 | && (prev_pinfo & INSN_READ_COND_CODE))) | |
becfe05e ILT |
1425 | { |
1426 | /* We could do even better for unconditional branches to | |
1427 | portions of this object file; we could pick up the | |
1428 | instruction at the destination, put it in the delay | |
1429 | slot, and bump the destination address. */ | |
1430 | emit_nop (); | |
1431 | /* Update the previous insn information. */ | |
1432 | prev_prev_insn = *ip; | |
1433 | prev_insn.insn_mo = &dummy_opcode; | |
1434 | } | |
1435 | else | |
1436 | { | |
1437 | char *prev_f; | |
1438 | char temp[4]; | |
1439 | ||
1440 | /* It looks like we can actually do the swap. */ | |
1441 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1442 | memcpy (temp, prev_f, 4); | |
1443 | memcpy (prev_f, f, 4); | |
1444 | memcpy (f, temp, 4); | |
1445 | if (prev_insn_fixp) | |
1446 | { | |
1447 | prev_insn_fixp->fx_frag = frag_now; | |
1448 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
1449 | } | |
1450 | if (fixp) | |
1451 | { | |
1452 | fixp->fx_frag = prev_insn_frag; | |
1453 | fixp->fx_where = prev_insn_where; | |
1454 | } | |
1455 | /* Update the previous insn information; leave prev_insn | |
1456 | unchanged. */ | |
1457 | prev_prev_insn = *ip; | |
1458 | } | |
1459 | prev_insn_is_delay_slot = 1; | |
1460 | ||
1461 | /* If that was an unconditional branch, forget the previous | |
1462 | insn information. */ | |
1aa6938e | 1463 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
1464 | { |
1465 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1466 | prev_insn.insn_mo = &dummy_opcode; | |
1467 | } | |
1468 | } | |
1aa6938e | 1469 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
1470 | { |
1471 | /* We don't yet optimize a branch likely. What we should do | |
1472 | is look at the target, copy the instruction found there | |
1473 | into the delay slot, and increment the branch to jump to | |
1474 | the next instruction. */ | |
1475 | emit_nop (); | |
1476 | /* Update the previous insn information. */ | |
1477 | prev_prev_insn = *ip; | |
1478 | prev_insn.insn_mo = &dummy_opcode; | |
1479 | } | |
becfe05e | 1480 | else |
670a50eb | 1481 | { |
becfe05e ILT |
1482 | /* Update the previous insn information. */ |
1483 | if (nops > 0) | |
1484 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1485 | else | |
1486 | prev_prev_insn = prev_insn; | |
1487 | prev_insn = *ip; | |
1488 | ||
1489 | /* Any time we see a branch, we always fill the delay slot | |
1490 | immediately; since this insn is not a branch, we know it | |
1491 | is not in a delay slot. */ | |
1492 | prev_insn_is_delay_slot = 0; | |
1493 | } | |
1494 | ||
4e95866e ILT |
1495 | prev_prev_insn_unreordered = prev_insn_unreordered; |
1496 | prev_insn_unreordered = 0; | |
becfe05e ILT |
1497 | prev_insn_frag = frag_now; |
1498 | prev_insn_where = f - frag_now->fr_literal; | |
1499 | prev_insn_fixp = fixp; | |
1500 | prev_insn_valid = 1; | |
1501 | } | |
3d3c5039 | 1502 | |
becfe05e ILT |
1503 | /* We just output an insn, so the next one doesn't have a label. */ |
1504 | insn_label = NULL; | |
1505 | } | |
1506 | ||
1507 | /* This function forgets that there was any previous instruction or | |
1508 | label. */ | |
1509 | ||
1510 | static void | |
1511 | mips_no_prev_insn () | |
1512 | { | |
1513 | prev_insn.insn_mo = &dummy_opcode; | |
1514 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1515 | prev_insn_valid = 0; | |
1516 | prev_insn_is_delay_slot = 0; | |
4e95866e ILT |
1517 | prev_insn_unreordered = 0; |
1518 | prev_prev_insn_unreordered = 0; | |
becfe05e ILT |
1519 | insn_label = NULL; |
1520 | } | |
1521 | ||
1522 | /* This function must be called whenever we turn on noreorder or emit | |
1523 | something other than instructions. It inserts any NOPS which might | |
1524 | be needed by the previous instruction, and clears the information | |
1525 | kept for the previous instructions. */ | |
1526 | ||
1527 | static void | |
1528 | mips_emit_delays () | |
1529 | { | |
1530 | if (! mips_noreorder) | |
1531 | { | |
1532 | int nop; | |
1533 | ||
1534 | nop = 0; | |
d8a1c247 | 1535 | if ((mips_isa < 4 |
344a8d61 JSC |
1536 | && (! cop_interlocks |
1537 | && (prev_insn.insn_mo->pinfo | |
1538 | & (INSN_LOAD_COPROC_DELAY | |
1539 | | INSN_COPROC_MOVE_DELAY | |
1540 | | INSN_WRITE_COND_CODE)))) | |
e532b44c | 1541 | || (! interlocks |
b2b8c24e ILT |
1542 | && (prev_insn.insn_mo->pinfo |
1543 | & (INSN_READ_LO | |
1544 | | INSN_READ_HI))) | |
8358c818 ILT |
1545 | || (mips_isa < 2 |
1546 | && (prev_insn.insn_mo->pinfo | |
1547 | & (INSN_LOAD_MEMORY_DELAY | |
1548 | | INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
1549 | { |
1550 | nop = 1; | |
d8a1c247 | 1551 | if ((mips_isa < 4 |
344a8d61 JSC |
1552 | && (! cop_interlocks |
1553 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 1554 | || (! interlocks |
b2b8c24e ILT |
1555 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1556 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
becfe05e ILT |
1557 | emit_nop (); |
1558 | } | |
d8a1c247 | 1559 | else if ((mips_isa < 4 |
344a8d61 JSC |
1560 | && (! cop_interlocks |
1561 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 1562 | || (! interlocks |
b2b8c24e ILT |
1563 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1564 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
becfe05e ILT |
1565 | nop = 1; |
1566 | if (nop) | |
670a50eb | 1567 | { |
becfe05e ILT |
1568 | emit_nop (); |
1569 | if (insn_label != NULL) | |
1570 | { | |
1571 | assert (S_GET_SEGMENT (insn_label) == now_seg); | |
1572 | insn_label->sy_frag = frag_now; | |
604633ae | 1573 | S_SET_VALUE (insn_label, (valueT) frag_now_fix ()); |
becfe05e | 1574 | } |
3d3c5039 ILT |
1575 | } |
1576 | } | |
0221ddf7 ILT |
1577 | |
1578 | mips_no_prev_insn (); | |
3d3c5039 ILT |
1579 | } |
1580 | ||
670a50eb ILT |
1581 | /* Build an instruction created by a macro expansion. This is passed |
1582 | a pointer to the count of instructions created so far, an | |
1583 | expression, the name of the instruction to build, an operand format | |
1584 | string, and corresponding arguments. */ | |
1585 | ||
1dc1e798 | 1586 | #ifdef USE_STDARG |
3d3c5039 | 1587 | static void |
0dd2d296 ILT |
1588 | macro_build (char *place, |
1589 | int *counter, | |
670a50eb | 1590 | expressionS * ep, |
3d3c5039 ILT |
1591 | const char *name, |
1592 | const char *fmt, | |
1593 | ...) | |
1dc1e798 | 1594 | #else |
3d3c5039 | 1595 | static void |
0dd2d296 ILT |
1596 | macro_build (place, counter, ep, name, fmt, va_alist) |
1597 | char *place; | |
3d3c5039 ILT |
1598 | int *counter; |
1599 | expressionS *ep; | |
1600 | const char *name; | |
1601 | const char *fmt; | |
1602 | va_dcl | |
1dc1e798 | 1603 | #endif |
3d3c5039 | 1604 | { |
670a50eb ILT |
1605 | struct mips_cl_insn insn; |
1606 | bfd_reloc_code_real_type r; | |
1607 | va_list args; | |
3d3c5039 | 1608 | |
1dc1e798 | 1609 | #ifdef USE_STDARG |
670a50eb | 1610 | va_start (args, fmt); |
3d3c5039 | 1611 | #else |
670a50eb | 1612 | va_start (args); |
3d3c5039 ILT |
1613 | #endif |
1614 | ||
670a50eb ILT |
1615 | /* |
1616 | * If the macro is about to expand into a second instruction, | |
1617 | * print a warning if needed. We need to pass ip as a parameter | |
1618 | * to generate a better warning message here... | |
1619 | */ | |
0dd2d296 | 1620 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
1621 | as_warn ("Macro instruction expanded into multiple instructions"); |
1622 | ||
0dd2d296 ILT |
1623 | if (place == NULL) |
1624 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
1625 | |
1626 | r = BFD_RELOC_UNUSED; | |
1627 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
1628 | assert (insn.insn_mo); | |
1629 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
1630 | ||
9226253a | 1631 | while (strcmp (fmt, insn.insn_mo->args) != 0 |
c625fc23 JSC |
1632 | || insn.insn_mo->pinfo == INSN_MACRO |
1633 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA2 | |
1634 | && mips_isa < 2) | |
1635 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA3 | |
1636 | && mips_isa < 3) | |
1637 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA4 | |
1638 | && mips_isa < 4) | |
1639 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4650 | |
1640 | && ! mips_4650) | |
1641 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4010 | |
1642 | && ! mips_4010) | |
1643 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4100 | |
1644 | && ! mips_4100)) | |
670a50eb ILT |
1645 | { |
1646 | ++insn.insn_mo; | |
1647 | assert (insn.insn_mo->name); | |
1648 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 1649 | } |
670a50eb ILT |
1650 | insn.insn_opcode = insn.insn_mo->match; |
1651 | for (;;) | |
1652 | { | |
1653 | switch (*fmt++) | |
1654 | { | |
3d3c5039 | 1655 | case '\0': |
670a50eb | 1656 | break; |
3d3c5039 ILT |
1657 | |
1658 | case ',': | |
1659 | case '(': | |
1660 | case ')': | |
670a50eb | 1661 | continue; |
3d3c5039 ILT |
1662 | |
1663 | case 't': | |
1664 | case 'w': | |
918692a5 | 1665 | case 'E': |
670a50eb ILT |
1666 | insn.insn_opcode |= va_arg (args, int) << 16; |
1667 | continue; | |
3d3c5039 ILT |
1668 | |
1669 | case 'c': | |
1670 | case 'T': | |
1671 | case 'W': | |
670a50eb ILT |
1672 | insn.insn_opcode |= va_arg (args, int) << 16; |
1673 | continue; | |
3d3c5039 ILT |
1674 | |
1675 | case 'd': | |
918692a5 | 1676 | case 'G': |
670a50eb ILT |
1677 | insn.insn_opcode |= va_arg (args, int) << 11; |
1678 | continue; | |
3d3c5039 ILT |
1679 | |
1680 | case 'V': | |
1681 | case 'S': | |
670a50eb ILT |
1682 | insn.insn_opcode |= va_arg (args, int) << 11; |
1683 | continue; | |
3d3c5039 | 1684 | |
ff3a5c18 ILT |
1685 | case 'z': |
1686 | continue; | |
1687 | ||
3d3c5039 | 1688 | case '<': |
670a50eb ILT |
1689 | insn.insn_opcode |= va_arg (args, int) << 6; |
1690 | continue; | |
3d3c5039 ILT |
1691 | |
1692 | case 'D': | |
670a50eb ILT |
1693 | insn.insn_opcode |= va_arg (args, int) << 6; |
1694 | continue; | |
3d3c5039 | 1695 | |
918692a5 ILT |
1696 | case 'B': |
1697 | insn.insn_opcode |= va_arg (args, int) << 6; | |
1698 | continue; | |
1699 | ||
3d3c5039 ILT |
1700 | case 'b': |
1701 | case 's': | |
1702 | case 'r': | |
1703 | case 'v': | |
670a50eb ILT |
1704 | insn.insn_opcode |= va_arg (args, int) << 21; |
1705 | continue; | |
3d3c5039 ILT |
1706 | |
1707 | case 'i': | |
1708 | case 'j': | |
1709 | case 'o': | |
9226253a | 1710 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
1711 | assert (r == BFD_RELOC_MIPS_GPREL |
1712 | || r == BFD_RELOC_MIPS_LITERAL | |
1713 | || r == BFD_RELOC_LO16 | |
1714 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c | 1715 | || r == BFD_RELOC_MIPS_CALL16 |
fb251650 ILT |
1716 | || r == BFD_RELOC_MIPS_GOT_LO16 |
1717 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
ecd4ca1c ILT |
1718 | || (ep->X_op == O_subtract |
1719 | && now_seg == text_section | |
ecd4ca1c | 1720 | && r == BFD_RELOC_PCREL_LO16)); |
670a50eb | 1721 | continue; |
3d3c5039 | 1722 | |
6e8dda9c | 1723 | case 'u': |
ecd4ca1c ILT |
1724 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
1725 | assert (ep != NULL | |
1726 | && (ep->X_op == O_constant | |
1727 | || (ep->X_op == O_symbol | |
1728 | && (r == BFD_RELOC_HI16_S | |
fb251650 ILT |
1729 | || r == BFD_RELOC_HI16 |
1730 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
1731 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
ecd4ca1c ILT |
1732 | || (ep->X_op == O_subtract |
1733 | && now_seg == text_section | |
ecd4ca1c ILT |
1734 | && r == BFD_RELOC_PCREL_HI16_S))); |
1735 | if (ep->X_op == O_constant) | |
1736 | { | |
1737 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
1738 | ep = NULL; | |
1739 | r = BFD_RELOC_UNUSED; | |
1740 | } | |
6e8dda9c ILT |
1741 | continue; |
1742 | ||
3d3c5039 | 1743 | case 'p': |
670a50eb ILT |
1744 | assert (ep != NULL); |
1745 | /* | |
1746 | * This allows macro() to pass an immediate expression for | |
1747 | * creating short branches without creating a symbol. | |
1748 | * Note that the expression still might come from the assembly | |
1749 | * input, in which case the value is not checked for range nor | |
1750 | * is a relocation entry generated (yuck). | |
1751 | */ | |
5ac34ac3 | 1752 | if (ep->X_op == O_constant) |
670a50eb ILT |
1753 | { |
1754 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
1755 | ep = NULL; | |
1756 | } | |
1757 | else | |
1758 | r = BFD_RELOC_16_PCREL_S2; | |
1759 | continue; | |
3d3c5039 | 1760 | |
9226253a ILT |
1761 | case 'a': |
1762 | assert (ep != NULL); | |
1763 | r = BFD_RELOC_MIPS_JMP; | |
1764 | continue; | |
1765 | ||
3d3c5039 | 1766 | default: |
670a50eb | 1767 | internalError (); |
3d3c5039 | 1768 | } |
670a50eb | 1769 | break; |
3d3c5039 | 1770 | } |
670a50eb ILT |
1771 | va_end (args); |
1772 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
1773 | ||
867a58b3 | 1774 | append_insn (place, &insn, ep, r, false); |
3d3c5039 ILT |
1775 | } |
1776 | ||
1777 | /* | |
1778 | * Generate a "lui" instruction. | |
1779 | */ | |
1780 | static void | |
0dd2d296 ILT |
1781 | macro_build_lui (place, counter, ep, regnum) |
1782 | char *place; | |
3d3c5039 ILT |
1783 | int *counter; |
1784 | expressionS *ep; | |
1785 | int regnum; | |
1786 | { | |
670a50eb ILT |
1787 | expressionS high_expr; |
1788 | struct mips_cl_insn insn; | |
1789 | bfd_reloc_code_real_type r; | |
1790 | CONST char *name = "lui"; | |
1791 | CONST char *fmt = "t,u"; | |
1792 | ||
0dd2d296 ILT |
1793 | if (place == NULL) |
1794 | high_expr = *ep; | |
1795 | else | |
1796 | { | |
1797 | high_expr.X_op = O_constant; | |
fb251650 | 1798 | high_expr.X_add_number = ep->X_add_number; |
0dd2d296 | 1799 | } |
670a50eb | 1800 | |
5ac34ac3 | 1801 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
1802 | { |
1803 | /* we can compute the instruction now without a relocation entry */ | |
1804 | if (high_expr.X_add_number & 0x8000) | |
1805 | high_expr.X_add_number += 0x10000; | |
1806 | high_expr.X_add_number = | |
1807 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
1808 | r = BFD_RELOC_UNUSED; | |
1809 | } | |
1810 | else | |
0dd2d296 ILT |
1811 | { |
1812 | assert (ep->X_op == O_symbol); | |
1813 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 1814 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
1815 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
1816 | r = BFD_RELOC_HI16_S; | |
1817 | } | |
670a50eb ILT |
1818 | |
1819 | /* | |
1820 | * If the macro is about to expand into a second instruction, | |
1821 | * print a warning if needed. We need to pass ip as a parameter | |
1822 | * to generate a better warning message here... | |
1823 | */ | |
0dd2d296 | 1824 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
1825 | as_warn ("Macro instruction expanded into multiple instructions"); |
1826 | ||
0dd2d296 ILT |
1827 | if (place == NULL) |
1828 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
1829 | |
1830 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
1831 | assert (insn.insn_mo); | |
1832 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
1833 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
1834 | ||
0dd2d296 | 1835 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
1836 | if (r == BFD_RELOC_UNUSED) |
1837 | { | |
1838 | insn.insn_opcode |= high_expr.X_add_number; | |
867a58b3 | 1839 | append_insn (place, &insn, NULL, r, false); |
670a50eb ILT |
1840 | } |
1841 | else | |
867a58b3 | 1842 | append_insn (place, &insn, &high_expr, r, false); |
3d3c5039 ILT |
1843 | } |
1844 | ||
1845 | /* set_at() | |
1846 | * Generates code to set the $at register to true (one) | |
1847 | * if reg is less than the immediate expression. | |
1848 | */ | |
1849 | static void | |
6e8dda9c | 1850 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
1851 | int *counter; |
1852 | int reg; | |
6e8dda9c | 1853 | int unsignedp; |
3d3c5039 | 1854 | { |
6e8dda9c | 1855 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
0dd2d296 | 1856 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 1857 | unsignedp ? "sltiu" : "slti", |
9226253a | 1858 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 1859 | else |
670a50eb | 1860 | { |
d8a1c247 | 1861 | load_register (counter, AT, &imm_expr, 0); |
0dd2d296 | 1862 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
1863 | unsignedp ? "sltu" : "slt", |
1864 | "d,v,t", AT, reg, AT); | |
670a50eb | 1865 | } |
3d3c5039 ILT |
1866 | } |
1867 | ||
6e8dda9c | 1868 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
1869 | |
1870 | static void | |
19ed8960 | 1871 | check_absolute_expr (ip, ex) |
3d3c5039 | 1872 | struct mips_cl_insn *ip; |
19ed8960 | 1873 | expressionS *ex; |
3d3c5039 | 1874 | { |
19ed8960 | 1875 | if (ex->X_op != O_constant) |
670a50eb | 1876 | as_warn ("Instruction %s requires absolute expression", ip->insn_mo->name); |
3d3c5039 ILT |
1877 | } |
1878 | ||
ff8716f5 JSC |
1879 | /* Count the leading zeroes by performing a binary chop. This is a |
1880 | bulky bit of source, but performance is a LOT better for the | |
1881 | majority of values than a simple loop to count the bits: | |
1882 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
1883 | if ((v) & (1 << (31 - lcnt))) | |
1884 | break; | |
1885 | However it is not code size friendly, and the gain will drop a bit | |
1886 | on certain cached systems. | |
1887 | */ | |
1888 | #define COUNT_TOP_ZEROES(v) \ | |
1889 | (((v) & ~0xffff) == 0 \ | |
1890 | ? ((v) & ~0xff) == 0 \ | |
1891 | ? ((v) & ~0xf) == 0 \ | |
1892 | ? ((v) & ~0x3) == 0 \ | |
1893 | ? ((v) & ~0x1) == 0 \ | |
1894 | ? !(v) \ | |
1895 | ? 32 \ | |
1896 | : 31 \ | |
1897 | : 30 \ | |
1898 | : ((v) & ~0x7) == 0 \ | |
1899 | ? 29 \ | |
1900 | : 28 \ | |
1901 | : ((v) & ~0x3f) == 0 \ | |
1902 | ? ((v) & ~0x1f) == 0 \ | |
1903 | ? 27 \ | |
1904 | : 26 \ | |
1905 | : ((v) & ~0x7f) == 0 \ | |
1906 | ? 25 \ | |
1907 | : 24 \ | |
1908 | : ((v) & ~0xfff) == 0 \ | |
1909 | ? ((v) & ~0x3ff) == 0 \ | |
1910 | ? ((v) & ~0x1ff) == 0 \ | |
1911 | ? 23 \ | |
1912 | : 22 \ | |
1913 | : ((v) & ~0x7ff) == 0 \ | |
1914 | ? 21 \ | |
1915 | : 20 \ | |
1916 | : ((v) & ~0x3fff) == 0 \ | |
1917 | ? ((v) & ~0x1fff) == 0 \ | |
1918 | ? 19 \ | |
1919 | : 18 \ | |
1920 | : ((v) & ~0x7fff) == 0 \ | |
1921 | ? 17 \ | |
1922 | : 16 \ | |
1923 | : ((v) & ~0xffffff) == 0 \ | |
1924 | ? ((v) & ~0xfffff) == 0 \ | |
1925 | ? ((v) & ~0x3ffff) == 0 \ | |
1926 | ? ((v) & ~0x1ffff) == 0 \ | |
1927 | ? 15 \ | |
1928 | : 14 \ | |
1929 | : ((v) & ~0x7ffff) == 0 \ | |
1930 | ? 13 \ | |
1931 | : 12 \ | |
1932 | : ((v) & ~0x3fffff) == 0 \ | |
1933 | ? ((v) & ~0x1fffff) == 0 \ | |
1934 | ? 11 \ | |
1935 | : 10 \ | |
1936 | : ((v) & ~0x7fffff) == 0 \ | |
1937 | ? 9 \ | |
1938 | : 8 \ | |
1939 | : ((v) & ~0xfffffff) == 0 \ | |
1940 | ? ((v) & ~0x3ffffff) == 0 \ | |
1941 | ? ((v) & ~0x1ffffff) == 0 \ | |
1942 | ? 7 \ | |
1943 | : 6 \ | |
1944 | : ((v) & ~0x7ffffff) == 0 \ | |
1945 | ? 5 \ | |
1946 | : 4 \ | |
1947 | : ((v) & ~0x3fffffff) == 0 \ | |
1948 | ? ((v) & ~0x1fffffff) == 0 \ | |
1949 | ? 3 \ | |
1950 | : 2 \ | |
1951 | : ((v) & ~0x7fffffff) == 0 \ | |
1952 | ? 1 \ | |
1953 | : 0) | |
1954 | ||
3d3c5039 ILT |
1955 | /* load_register() |
1956 | * This routine generates the least number of instructions neccessary to load | |
1957 | * an absolute expression value into a register. | |
1958 | */ | |
1959 | static void | |
d8a1c247 | 1960 | load_register (counter, reg, ep, dbl) |
670a50eb | 1961 | int *counter; |
670a50eb ILT |
1962 | int reg; |
1963 | expressionS *ep; | |
d8a1c247 | 1964 | int dbl; |
3d3c5039 | 1965 | { |
d8a1c247 | 1966 | int shift, freg; |
ff8716f5 | 1967 | expressionS hi32, lo32, tmp; |
847a01cd ILT |
1968 | |
1969 | if (ep->X_op != O_big) | |
6e8dda9c | 1970 | { |
847a01cd | 1971 | assert (ep->X_op == O_constant); |
d8a1c247 KR |
1972 | if (ep->X_add_number < 0x8000 |
1973 | && (ep->X_add_number >= 0 | |
1974 | || (ep->X_add_number >= -0x8000 | |
1975 | && (! dbl | |
1976 | || ! ep->X_unsigned | |
1977 | || sizeof (ep->X_add_number) > 4)))) | |
847a01cd ILT |
1978 | { |
1979 | /* We can handle 16 bit signed values with an addiu to | |
1980 | $zero. No need to ever use daddiu here, since $zero and | |
1981 | the result are always correct in 32 bit mode. */ | |
1982 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
1983 | (int) BFD_RELOC_LO16); | |
1984 | return; | |
1985 | } | |
1986 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
1987 | { | |
1988 | /* We can handle 16 bit unsigned values with an ori to | |
1989 | $zero. */ | |
1990 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
1991 | (int) BFD_RELOC_LO16); | |
1992 | return; | |
1993 | } | |
98bfd087 ILT |
1994 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
1995 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
1996 | == ~ (offsetT) 0x7fffffff)) | |
1997 | && (! dbl | |
1998 | || ! ep->X_unsigned | |
1999 | || sizeof (ep->X_add_number) > 4 | |
2000 | || (ep->X_add_number & 0x80000000) == 0)) | |
ff8716f5 | 2001 | || ((mips_isa < 3 || !dbl) |
0267c6c9 | 2002 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)) |
847a01cd ILT |
2003 | { |
2004 | /* 32 bit values require an lui. */ | |
2005 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2006 | (int) BFD_RELOC_HI16); | |
2007 | if ((ep->X_add_number & 0xffff) != 0) | |
2008 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
2009 | (int) BFD_RELOC_LO16); | |
2010 | return; | |
2011 | } | |
6e8dda9c | 2012 | } |
847a01cd ILT |
2013 | |
2014 | /* The value is larger than 32 bits. */ | |
2015 | ||
2016 | if (mips_isa < 3) | |
670a50eb | 2017 | { |
6e8dda9c | 2018 | as_bad ("Number larger than 32 bits"); |
0dd2d296 | 2019 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 2020 | (int) BFD_RELOC_LO16); |
847a01cd | 2021 | return; |
6e8dda9c | 2022 | } |
6e8dda9c | 2023 | |
847a01cd ILT |
2024 | if (ep->X_op != O_big) |
2025 | { | |
6e8dda9c ILT |
2026 | hi32 = *ep; |
2027 | shift = 32; | |
2028 | hi32.X_add_number >>= shift; | |
2029 | hi32.X_add_number &= 0xffffffff; | |
2030 | if ((hi32.X_add_number & 0x80000000) != 0) | |
2031 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
6e8dda9c ILT |
2032 | lo32 = *ep; |
2033 | lo32.X_add_number &= 0xffffffff; | |
670a50eb | 2034 | } |
847a01cd ILT |
2035 | else |
2036 | { | |
2037 | assert (ep->X_add_number > 2); | |
2038 | if (ep->X_add_number == 3) | |
2039 | generic_bignum[3] = 0; | |
2040 | else if (ep->X_add_number > 4) | |
2041 | as_bad ("Number larger than 64 bits"); | |
2042 | lo32.X_op = O_constant; | |
2043 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
2044 | hi32.X_op = O_constant; | |
2045 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
2046 | } | |
2047 | ||
d8a1c247 KR |
2048 | if (hi32.X_add_number == 0) |
2049 | freg = 0; | |
2050 | else | |
2051 | { | |
fb251650 ILT |
2052 | if (hi32.X_add_number == 0xffffffff) |
2053 | { | |
2054 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
2055 | { | |
2056 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", reg, 0, | |
2057 | (int) BFD_RELOC_LO16); | |
2058 | return; | |
2059 | } | |
2060 | if (lo32.X_add_number & 0x80000000) | |
2061 | { | |
2062 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2063 | (int) BFD_RELOC_HI16); | |
2064 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, reg, | |
2065 | (int) BFD_RELOC_LO16); | |
2066 | return; | |
2067 | } | |
2068 | } | |
ff8716f5 JSC |
2069 | |
2070 | /* Check for 16bit shifted constant: */ | |
2071 | shift = 32; | |
2072 | tmp.X_add_number = hi32.X_add_number << shift | lo32.X_add_number; | |
2073 | /* We know that hi32 is non-zero, so start the mask on the first | |
2074 | bit of the hi32 value: */ | |
2075 | shift = 17; | |
2076 | do | |
2077 | { | |
2078 | if ((tmp.X_add_number & ~((offsetT)0xffff << shift)) == 0) | |
2079 | { | |
2080 | tmp.X_op = O_constant; | |
2081 | tmp.X_add_number >>= shift; | |
2082 | macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, | |
2083 | (int) BFD_RELOC_LO16); | |
2084 | macro_build ((char *) NULL, counter, NULL, | |
2085 | (shift >= 32) ? "dsll32" : "dsll", | |
2086 | "d,w,<", reg, reg, (shift >= 32) ? shift - 32 : shift); | |
2087 | return; | |
2088 | } | |
2089 | shift++; | |
2090 | } while (shift <= (64 - 16)); | |
2091 | ||
2092 | freg = 0; | |
2093 | shift = 32; | |
2094 | tmp.X_add_number = hi32.X_add_number << shift | lo32.X_add_number; | |
2095 | while ((tmp.X_add_number & 1) == 0) | |
2096 | { | |
2097 | tmp.X_add_number >>= 1; | |
2098 | freg++; | |
2099 | } | |
2100 | if (((tmp.X_add_number + 1) & tmp.X_add_number) == 0) /* (power-of-2 - 1) */ | |
2101 | { | |
2102 | shift = COUNT_TOP_ZEROES((unsigned int)hi32.X_add_number); | |
2103 | if (shift != 0) | |
2104 | { | |
2105 | tmp.X_op = O_constant; | |
2106 | tmp.X_add_number = (offsetT)-1; | |
2107 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", reg, 0, | |
2108 | (int) BFD_RELOC_LO16); /* set all ones */ | |
2109 | if (freg != 0) | |
2110 | { | |
2111 | freg += shift; | |
2112 | macro_build ((char *) NULL, counter, NULL, | |
2113 | (freg >= 32) ? "dsll32" : "dsll", | |
2114 | "d,w,<", reg, reg, | |
2115 | (freg >= 32) ? freg - 32 : freg); | |
2116 | } | |
2117 | macro_build ((char *) NULL, counter, NULL, (shift >= 32) ? "dsrl32" : "dsrl", | |
2118 | "d,w,<", reg, reg, (shift >= 32) ? shift - 32 : shift); | |
2119 | return; | |
2120 | } | |
2121 | } | |
d8a1c247 KR |
2122 | load_register (counter, reg, &hi32, 0); |
2123 | freg = reg; | |
2124 | } | |
847a01cd | 2125 | if ((lo32.X_add_number & 0xffff0000) == 0) |
d8a1c247 KR |
2126 | { |
2127 | if (freg != 0) | |
2128 | { | |
2129 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
2130 | freg, 0); | |
2131 | freg = reg; | |
2132 | } | |
2133 | } | |
847a01cd ILT |
2134 | else |
2135 | { | |
2136 | expressionS mid16; | |
2137 | ||
fb251650 ILT |
2138 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) |
2139 | { | |
2140 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2141 | (int) BFD_RELOC_HI16); | |
2142 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
ff8716f5 | 2143 | reg, 0); |
fb251650 ILT |
2144 | return; |
2145 | } | |
2146 | ||
d8a1c247 KR |
2147 | if (freg != 0) |
2148 | { | |
2149 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
2150 | freg, 16); | |
2151 | freg = reg; | |
2152 | } | |
847a01cd ILT |
2153 | mid16 = lo32; |
2154 | mid16.X_add_number >>= 16; | |
2155 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
d8a1c247 | 2156 | freg, (int) BFD_RELOC_LO16); |
847a01cd ILT |
2157 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
2158 | reg, 16); | |
d8a1c247 | 2159 | freg = reg; |
847a01cd ILT |
2160 | } |
2161 | if ((lo32.X_add_number & 0xffff) != 0) | |
d8a1c247 | 2162 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
847a01cd | 2163 | (int) BFD_RELOC_LO16); |
3d3c5039 ILT |
2164 | } |
2165 | ||
0dd2d296 ILT |
2166 | /* Load an address into a register. */ |
2167 | ||
2168 | static void | |
2169 | load_address (counter, reg, ep) | |
2170 | int *counter; | |
2171 | int reg; | |
2172 | expressionS *ep; | |
2173 | { | |
2174 | char *p; | |
2175 | ||
2176 | if (ep->X_op != O_constant | |
2177 | && ep->X_op != O_symbol) | |
2178 | { | |
2179 | as_bad ("expression too complex"); | |
2180 | ep->X_op = O_constant; | |
2181 | } | |
2182 | ||
2183 | if (ep->X_op == O_constant) | |
d9aba805 | 2184 | { |
d8a1c247 | 2185 | load_register (counter, reg, ep, 0); |
d9aba805 ILT |
2186 | return; |
2187 | } | |
2188 | ||
2189 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
2190 | { |
2191 | /* If this is a reference to a GP relative symbol, we want | |
2192 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
2193 | Otherwise we want | |
04cb3372 | 2194 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
2195 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
2196 | If we have an addend, we always use the latter form. */ | |
7a15a226 ILT |
2197 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET |
2198 | || nopic_need_relax (ep->X_add_symbol)) | |
0dd2d296 ILT |
2199 | p = NULL; |
2200 | else | |
2201 | { | |
8ea7f4e8 | 2202 | frag_grow (20); |
0dd2d296 ILT |
2203 | macro_build ((char *) NULL, counter, ep, |
2204 | mips_isa < 3 ? "addiu" : "daddiu", | |
2205 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
2206 | p = frag_var (rs_machine_dependent, 8, 0, | |
847a01cd | 2207 | RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros), |
0dd2d296 ILT |
2208 | ep->X_add_symbol, (long) 0, (char *) NULL); |
2209 | } | |
2210 | macro_build_lui (p, counter, ep, reg); | |
2211 | if (p != NULL) | |
2212 | p += 4; | |
2213 | macro_build (p, counter, ep, | |
2214 | mips_isa < 3 ? "addiu" : "daddiu", | |
2215 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2216 | } | |
fb251650 | 2217 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
2218 | { |
2219 | expressionS ex; | |
2220 | ||
2221 | /* If this is a reference to an external symbol, we want | |
2222 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2223 | Otherwise we want | |
2224 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2225 | nop | |
2226 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 2227 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
2228 | ex.X_add_number = ep->X_add_number; |
2229 | ep->X_add_number = 0; | |
8ea7f4e8 | 2230 | frag_grow (20); |
0dd2d296 ILT |
2231 | macro_build ((char *) NULL, counter, ep, |
2232 | mips_isa < 3 ? "lw" : "ld", | |
2233 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
2234 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
2235 | p = frag_var (rs_machine_dependent, 4, 0, | |
2236 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros), | |
2237 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
2238 | macro_build (p, counter, ep, | |
2239 | mips_isa < 3 ? "addiu" : "daddiu", | |
2240 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2241 | if (ex.X_add_number != 0) | |
2242 | { | |
2243 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
2244 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
2245 | ex.X_op = O_constant; | |
fb251650 ILT |
2246 | macro_build ((char *) NULL, counter, &ex, |
2247 | mips_isa < 3 ? "addiu" : "daddiu", | |
2248 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2249 | } | |
2250 | } | |
2251 | else if (mips_pic == SVR4_PIC) | |
2252 | { | |
2253 | expressionS ex; | |
2254 | int off; | |
2255 | ||
2256 | /* This is the large GOT case. If this is a reference to an | |
2257 | external symbol, we want | |
2258 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
2259 | addu $reg,$reg,$gp | |
2260 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
2261 | Otherwise, for a reference to a local symbol, we want | |
2262 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2263 | nop | |
2264 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
2265 | If there is a constant, it must be added in after. */ | |
2266 | ex.X_add_number = ep->X_add_number; | |
2267 | ep->X_add_number = 0; | |
2268 | if (reg_needs_delay (GP)) | |
2269 | off = 4; | |
2270 | else | |
2271 | off = 0; | |
2272 | frag_grow (32); | |
2273 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2274 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
2275 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
2276 | mips_isa < 3 ? "addu" : "daddu", | |
2277 | "d,v,t", reg, reg, GP); | |
2278 | macro_build ((char *) NULL, counter, ep, | |
2279 | mips_isa < 3 ? "lw" : "ld", | |
2280 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); | |
2281 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
2282 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
2283 | mips_warn_about_macros), | |
2284 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
2285 | if (off > 0) | |
2286 | { | |
2287 | /* We need a nop before loading from $gp. This special | |
2288 | check is required because the lui which starts the main | |
2289 | instruction stream does not refer to $gp, and so will not | |
2290 | insert the nop which may be required. */ | |
2291 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
2292 | p += 4; | |
2293 | } | |
2294 | macro_build (p, counter, ep, | |
2295 | mips_isa < 3 ? "lw" : "ld", | |
2296 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
2297 | p += 4; | |
2298 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
2299 | p += 4; | |
2300 | macro_build (p, counter, ep, | |
2301 | mips_isa < 3 ? "addiu" : "daddiu", | |
2302 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2303 | if (ex.X_add_number != 0) | |
2304 | { | |
2305 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
2306 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
2307 | ex.X_op = O_constant; | |
2308 | macro_build ((char *) NULL, counter, &ex, | |
0dd2d296 ILT |
2309 | mips_isa < 3 ? "addiu" : "daddiu", |
2310 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2311 | } | |
d9aba805 ILT |
2312 | } |
2313 | else if (mips_pic == EMBEDDED_PIC) | |
2314 | { | |
2315 | /* We always do | |
2316 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
2317 | */ | |
2318 | macro_build ((char *) NULL, counter, ep, | |
2319 | mips_isa < 3 ? "addiu" : "daddiu", | |
2320 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
2321 | } | |
2322 | else | |
2323 | abort (); | |
0dd2d296 ILT |
2324 | } |
2325 | ||
3d3c5039 ILT |
2326 | /* |
2327 | * Build macros | |
2328 | * This routine implements the seemingly endless macro or synthesized | |
2329 | * instructions and addressing modes in the mips assembly language. Many | |
2330 | * of these macros are simple and are similar to each other. These could | |
2331 | * probably be handled by some kind of table or grammer aproach instead of | |
2332 | * this verbose method. Others are not simple macros but are more like | |
2333 | * optimizing code generation. | |
2334 | * One interesting optimization is when several store macros appear | |
2335 | * consecutivly that would load AT with the upper half of the same address. | |
2336 | * The ensuing load upper instructions are ommited. This implies some kind | |
2337 | * of global optimization. We currently only optimize within a single macro. | |
2338 | * For many of the load and store macros if the address is specified as a | |
2339 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
2340 | * first load register 'at' with zero and use it as the base register. The | |
2341 | * mips assembler simply uses register $zero. Just one tiny optimization | |
2342 | * we're missing. | |
2343 | */ | |
2344 | static void | |
2345 | macro (ip) | |
2346 | struct mips_cl_insn *ip; | |
2347 | { | |
670a50eb ILT |
2348 | register int treg, sreg, dreg, breg; |
2349 | int tempreg; | |
2350 | int mask; | |
2351 | int icnt = 0; | |
2352 | int used_at; | |
670a50eb ILT |
2353 | expressionS expr1; |
2354 | const char *s; | |
8358c818 | 2355 | const char *s2; |
670a50eb | 2356 | const char *fmt; |
8358c818 ILT |
2357 | int likely = 0; |
2358 | int dbl = 0; | |
2359 | int coproc = 0; | |
b2b8c24e | 2360 | int lr = 0; |
6e8dda9c | 2361 | offsetT maxnum; |
adcf2b9d | 2362 | int off; |
9226253a | 2363 | bfd_reloc_code_real_type r; |
0dd2d296 | 2364 | char *p; |
55933a58 | 2365 | int hold_mips_optimize; |
670a50eb ILT |
2366 | |
2367 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
2368 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
2369 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
2370 | mask = ip->insn_mo->mask; | |
2371 | ||
5ac34ac3 ILT |
2372 | expr1.X_op = O_constant; |
2373 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
2374 | expr1.X_add_symbol = NULL; |
2375 | expr1.X_add_number = 1; | |
2376 | ||
2377 | switch (mask) | |
2378 | { | |
6e8dda9c ILT |
2379 | case M_DABS: |
2380 | dbl = 1; | |
3d3c5039 | 2381 | case M_ABS: |
6e8dda9c ILT |
2382 | /* bgez $a0,.+12 |
2383 | move v0,$a0 | |
2384 | sub v0,$zero,$a0 | |
2385 | */ | |
3d3c5039 | 2386 | |
becfe05e ILT |
2387 | mips_emit_delays (); |
2388 | ++mips_noreorder; | |
0dd2d296 | 2389 | mips_any_noreorder = 1; |
3d3c5039 | 2390 | |
670a50eb | 2391 | expr1.X_add_number = 8; |
0dd2d296 | 2392 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 2393 | if (dreg == sreg) |
0dd2d296 | 2394 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 2395 | else |
0dd2d296 ILT |
2396 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
2397 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
2398 | dbl ? "dsub" : "sub", |
2399 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 2400 | |
becfe05e | 2401 | --mips_noreorder; |
670a50eb | 2402 | return; |
3d3c5039 ILT |
2403 | |
2404 | case M_ADD_I: | |
8358c818 ILT |
2405 | s = "addi"; |
2406 | s2 = "add"; | |
2407 | goto do_addi; | |
3d3c5039 | 2408 | case M_ADDU_I: |
8358c818 ILT |
2409 | s = "addiu"; |
2410 | s2 = "addu"; | |
2411 | goto do_addi; | |
2412 | case M_DADD_I: | |
6e8dda9c | 2413 | dbl = 1; |
8358c818 ILT |
2414 | s = "daddi"; |
2415 | s2 = "dadd"; | |
2416 | goto do_addi; | |
2417 | case M_DADDU_I: | |
6e8dda9c | 2418 | dbl = 1; |
8358c818 ILT |
2419 | s = "daddiu"; |
2420 | s2 = "daddu"; | |
2421 | do_addi: | |
6e8dda9c | 2422 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 2423 | { |
0dd2d296 | 2424 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 2425 | (int) BFD_RELOC_LO16); |
670a50eb | 2426 | return; |
3d3c5039 | 2427 | } |
d8a1c247 | 2428 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 2429 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 2430 | break; |
3d3c5039 ILT |
2431 | |
2432 | case M_AND_I: | |
6e8dda9c ILT |
2433 | s = "andi"; |
2434 | s2 = "and"; | |
2435 | goto do_bit; | |
3d3c5039 | 2436 | case M_OR_I: |
6e8dda9c ILT |
2437 | s = "ori"; |
2438 | s2 = "or"; | |
2439 | goto do_bit; | |
3d3c5039 | 2440 | case M_NOR_I: |
6e8dda9c ILT |
2441 | s = ""; |
2442 | s2 = "nor"; | |
2443 | goto do_bit; | |
3d3c5039 | 2444 | case M_XOR_I: |
6e8dda9c ILT |
2445 | s = "xori"; |
2446 | s2 = "xor"; | |
2447 | do_bit: | |
2448 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) | |
670a50eb | 2449 | { |
6e8dda9c | 2450 | if (mask != M_NOR_I) |
0dd2d296 ILT |
2451 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
2452 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 2453 | else |
670a50eb | 2454 | { |
0dd2d296 ILT |
2455 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
2456 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 2457 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 2458 | treg, treg, 0); |
3d3c5039 | 2459 | } |
6e8dda9c | 2460 | return; |
3d3c5039 | 2461 | } |
6e8dda9c | 2462 | |
d8a1c247 | 2463 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 2464 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 2465 | break; |
3d3c5039 ILT |
2466 | |
2467 | case M_BEQ_I: | |
8358c818 ILT |
2468 | s = "beq"; |
2469 | goto beq_i; | |
2470 | case M_BEQL_I: | |
2471 | s = "beql"; | |
2472 | likely = 1; | |
2473 | goto beq_i; | |
3d3c5039 | 2474 | case M_BNE_I: |
8358c818 ILT |
2475 | s = "bne"; |
2476 | goto beq_i; | |
2477 | case M_BNEL_I: | |
2478 | s = "bnel"; | |
2479 | likely = 1; | |
2480 | beq_i: | |
670a50eb ILT |
2481 | if (imm_expr.X_add_number == 0) |
2482 | { | |
0dd2d296 ILT |
2483 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
2484 | 0); | |
670a50eb ILT |
2485 | return; |
2486 | } | |
d8a1c247 | 2487 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 2488 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 2489 | break; |
3d3c5039 | 2490 | |
8358c818 ILT |
2491 | case M_BGEL: |
2492 | likely = 1; | |
3d3c5039 | 2493 | case M_BGE: |
670a50eb ILT |
2494 | if (treg == 0) |
2495 | { | |
0dd2d296 | 2496 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2497 | likely ? "bgezl" : "bgez", |
2498 | "s,p", sreg); | |
670a50eb | 2499 | return; |
3d3c5039 | 2500 | } |
9a7d824a ILT |
2501 | if (sreg == 0) |
2502 | { | |
0dd2d296 | 2503 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2504 | likely ? "blezl" : "blez", |
2505 | "s,p", treg); | |
9a7d824a ILT |
2506 | return; |
2507 | } | |
0dd2d296 ILT |
2508 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
2509 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2510 | likely ? "beql" : "beq", |
2511 | "s,t,p", AT, 0); | |
670a50eb | 2512 | break; |
3d3c5039 | 2513 | |
8358c818 ILT |
2514 | case M_BGTL_I: |
2515 | likely = 1; | |
3d3c5039 | 2516 | case M_BGT_I: |
9a7d824a | 2517 | /* check for > max integer */ |
6e8dda9c ILT |
2518 | maxnum = 0x7fffffff; |
2519 | if (mips_isa >= 3) | |
2520 | { | |
2521 | maxnum <<= 16; | |
2522 | maxnum |= 0xffff; | |
2523 | maxnum <<= 16; | |
2524 | maxnum |= 0xffff; | |
2525 | } | |
7b777690 ILT |
2526 | if (imm_expr.X_add_number >= maxnum |
2527 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
2528 | { |
2529 | do_false: | |
2530 | /* result is always false */ | |
8358c818 ILT |
2531 | if (! likely) |
2532 | { | |
2533 | as_warn ("Branch %s is always false (nop)", ip->insn_mo->name); | |
0dd2d296 | 2534 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
2535 | } |
2536 | else | |
2537 | { | |
2538 | as_warn ("Branch likely %s is always false", ip->insn_mo->name); | |
0dd2d296 ILT |
2539 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
2540 | "s,t,p", 0, 0); | |
8358c818 | 2541 | } |
9a7d824a ILT |
2542 | return; |
2543 | } | |
670a50eb ILT |
2544 | imm_expr.X_add_number++; |
2545 | /* FALLTHROUGH */ | |
3d3c5039 | 2546 | case M_BGE_I: |
8358c818 ILT |
2547 | case M_BGEL_I: |
2548 | if (mask == M_BGEL_I) | |
2549 | likely = 1; | |
670a50eb ILT |
2550 | if (imm_expr.X_add_number == 0) |
2551 | { | |
0dd2d296 | 2552 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2553 | likely ? "bgezl" : "bgez", |
2554 | "s,p", sreg); | |
670a50eb | 2555 | return; |
3d3c5039 | 2556 | } |
670a50eb ILT |
2557 | if (imm_expr.X_add_number == 1) |
2558 | { | |
0dd2d296 | 2559 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2560 | likely ? "bgtzl" : "bgtz", |
2561 | "s,p", sreg); | |
670a50eb | 2562 | return; |
3d3c5039 | 2563 | } |
6e8dda9c ILT |
2564 | maxnum = 0x7fffffff; |
2565 | if (mips_isa >= 3) | |
2566 | { | |
2567 | maxnum <<= 16; | |
2568 | maxnum |= 0xffff; | |
2569 | maxnum <<= 16; | |
2570 | maxnum |= 0xffff; | |
2571 | } | |
2572 | maxnum = - maxnum - 1; | |
7b777690 ILT |
2573 | if (imm_expr.X_add_number <= maxnum |
2574 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
2575 | { |
2576 | do_true: | |
2577 | /* result is always true */ | |
2578 | as_warn ("Branch %s is always true", ip->insn_mo->name); | |
0dd2d296 | 2579 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
2580 | return; |
2581 | } | |
6e8dda9c | 2582 | set_at (&icnt, sreg, 0); |
0dd2d296 | 2583 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2584 | likely ? "beql" : "beq", |
2585 | "s,t,p", AT, 0); | |
670a50eb | 2586 | break; |
3d3c5039 | 2587 | |
8358c818 ILT |
2588 | case M_BGEUL: |
2589 | likely = 1; | |
3d3c5039 | 2590 | case M_BGEU: |
670a50eb | 2591 | if (treg == 0) |
9a7d824a ILT |
2592 | goto do_true; |
2593 | if (sreg == 0) | |
670a50eb | 2594 | { |
0dd2d296 | 2595 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2596 | likely ? "beql" : "beq", |
2597 | "s,t,p", 0, treg); | |
670a50eb | 2598 | return; |
3d3c5039 | 2599 | } |
0dd2d296 ILT |
2600 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
2601 | treg); | |
2602 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2603 | likely ? "beql" : "beq", |
2604 | "s,t,p", AT, 0); | |
670a50eb | 2605 | break; |
3d3c5039 | 2606 | |
8358c818 ILT |
2607 | case M_BGTUL_I: |
2608 | likely = 1; | |
9a7d824a | 2609 | case M_BGTU_I: |
6e8dda9c | 2610 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
2611 | goto do_false; |
2612 | imm_expr.X_add_number++; | |
2613 | /* FALLTHROUGH */ | |
3d3c5039 | 2614 | case M_BGEU_I: |
8358c818 ILT |
2615 | case M_BGEUL_I: |
2616 | if (mask == M_BGEUL_I) | |
2617 | likely = 1; | |
670a50eb | 2618 | if (imm_expr.X_add_number == 0) |
9a7d824a | 2619 | goto do_true; |
670a50eb ILT |
2620 | if (imm_expr.X_add_number == 1) |
2621 | { | |
0dd2d296 | 2622 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2623 | likely ? "bnel" : "bne", |
2624 | "s,t,p", sreg, 0); | |
670a50eb | 2625 | return; |
3d3c5039 | 2626 | } |
6e8dda9c | 2627 | set_at (&icnt, sreg, 1); |
0dd2d296 | 2628 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2629 | likely ? "beql" : "beq", |
2630 | "s,t,p", AT, 0); | |
670a50eb | 2631 | break; |
3d3c5039 | 2632 | |
8358c818 ILT |
2633 | case M_BGTL: |
2634 | likely = 1; | |
3d3c5039 | 2635 | case M_BGT: |
670a50eb ILT |
2636 | if (treg == 0) |
2637 | { | |
0dd2d296 | 2638 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2639 | likely ? "bgtzl" : "bgtz", |
2640 | "s,p", sreg); | |
670a50eb | 2641 | return; |
3d3c5039 | 2642 | } |
9a7d824a ILT |
2643 | if (sreg == 0) |
2644 | { | |
0dd2d296 | 2645 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2646 | likely ? "bltzl" : "bltz", |
2647 | "s,p", treg); | |
9a7d824a ILT |
2648 | return; |
2649 | } | |
0dd2d296 ILT |
2650 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
2651 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2652 | likely ? "bnel" : "bne", |
2653 | "s,t,p", AT, 0); | |
670a50eb | 2654 | break; |
3d3c5039 | 2655 | |
8358c818 ILT |
2656 | case M_BGTUL: |
2657 | likely = 1; | |
3d3c5039 | 2658 | case M_BGTU: |
670a50eb ILT |
2659 | if (treg == 0) |
2660 | { | |
0dd2d296 | 2661 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2662 | likely ? "bnel" : "bne", |
2663 | "s,t,p", sreg, 0); | |
670a50eb | 2664 | return; |
3d3c5039 | 2665 | } |
9a7d824a ILT |
2666 | if (sreg == 0) |
2667 | goto do_false; | |
0dd2d296 ILT |
2668 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
2669 | sreg); | |
2670 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2671 | likely ? "bnel" : "bne", |
2672 | "s,t,p", AT, 0); | |
670a50eb | 2673 | break; |
3d3c5039 | 2674 | |
8358c818 ILT |
2675 | case M_BLEL: |
2676 | likely = 1; | |
3d3c5039 | 2677 | case M_BLE: |
670a50eb ILT |
2678 | if (treg == 0) |
2679 | { | |
0dd2d296 | 2680 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2681 | likely ? "blezl" : "blez", |
2682 | "s,p", sreg); | |
670a50eb ILT |
2683 | return; |
2684 | } | |
9a7d824a ILT |
2685 | if (sreg == 0) |
2686 | { | |
0dd2d296 | 2687 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2688 | likely ? "bgezl" : "bgez", |
2689 | "s,p", treg); | |
9a7d824a ILT |
2690 | return; |
2691 | } | |
0dd2d296 ILT |
2692 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
2693 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2694 | likely ? "beql" : "beq", |
2695 | "s,t,p", AT, 0); | |
670a50eb | 2696 | break; |
3d3c5039 | 2697 | |
8358c818 ILT |
2698 | case M_BLEL_I: |
2699 | likely = 1; | |
3d3c5039 | 2700 | case M_BLE_I: |
6e8dda9c ILT |
2701 | maxnum = 0x7fffffff; |
2702 | if (mips_isa >= 3) | |
2703 | { | |
2704 | maxnum <<= 16; | |
2705 | maxnum |= 0xffff; | |
2706 | maxnum <<= 16; | |
2707 | maxnum |= 0xffff; | |
2708 | } | |
7b777690 ILT |
2709 | if (imm_expr.X_add_number >= maxnum |
2710 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
2711 | goto do_true; |
2712 | imm_expr.X_add_number++; | |
2713 | /* FALLTHROUGH */ | |
9a7d824a | 2714 | case M_BLT_I: |
8358c818 ILT |
2715 | case M_BLTL_I: |
2716 | if (mask == M_BLTL_I) | |
2717 | likely = 1; | |
670a50eb ILT |
2718 | if (imm_expr.X_add_number == 0) |
2719 | { | |
0dd2d296 | 2720 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2721 | likely ? "bltzl" : "bltz", |
2722 | "s,p", sreg); | |
670a50eb ILT |
2723 | return; |
2724 | } | |
9a7d824a | 2725 | if (imm_expr.X_add_number == 1) |
670a50eb | 2726 | { |
0dd2d296 | 2727 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2728 | likely ? "blezl" : "blez", |
2729 | "s,p", sreg); | |
670a50eb ILT |
2730 | return; |
2731 | } | |
6e8dda9c | 2732 | set_at (&icnt, sreg, 0); |
0dd2d296 | 2733 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2734 | likely ? "bnel" : "bne", |
2735 | "s,t,p", AT, 0); | |
670a50eb | 2736 | break; |
3d3c5039 | 2737 | |
8358c818 ILT |
2738 | case M_BLEUL: |
2739 | likely = 1; | |
3d3c5039 | 2740 | case M_BLEU: |
670a50eb ILT |
2741 | if (treg == 0) |
2742 | { | |
0dd2d296 | 2743 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2744 | likely ? "beql" : "beq", |
2745 | "s,t,p", sreg, 0); | |
670a50eb | 2746 | return; |
3d3c5039 | 2747 | } |
9a7d824a ILT |
2748 | if (sreg == 0) |
2749 | goto do_true; | |
0dd2d296 ILT |
2750 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
2751 | sreg); | |
2752 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2753 | likely ? "beql" : "beq", |
2754 | "s,t,p", AT, 0); | |
670a50eb | 2755 | break; |
3d3c5039 | 2756 | |
8358c818 ILT |
2757 | case M_BLEUL_I: |
2758 | likely = 1; | |
3d3c5039 | 2759 | case M_BLEU_I: |
6e8dda9c | 2760 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
2761 | goto do_true; |
2762 | imm_expr.X_add_number++; | |
2763 | /* FALLTHROUGH */ | |
9a7d824a | 2764 | case M_BLTU_I: |
8358c818 ILT |
2765 | case M_BLTUL_I: |
2766 | if (mask == M_BLTUL_I) | |
2767 | likely = 1; | |
670a50eb | 2768 | if (imm_expr.X_add_number == 0) |
9a7d824a ILT |
2769 | goto do_false; |
2770 | if (imm_expr.X_add_number == 1) | |
670a50eb | 2771 | { |
0dd2d296 | 2772 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2773 | likely ? "beql" : "beq", |
2774 | "s,t,p", sreg, 0); | |
670a50eb | 2775 | return; |
3d3c5039 | 2776 | } |
6e8dda9c | 2777 | set_at (&icnt, sreg, 1); |
0dd2d296 | 2778 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2779 | likely ? "bnel" : "bne", |
2780 | "s,t,p", AT, 0); | |
670a50eb | 2781 | break; |
3d3c5039 | 2782 | |
8358c818 ILT |
2783 | case M_BLTL: |
2784 | likely = 1; | |
3d3c5039 | 2785 | case M_BLT: |
670a50eb ILT |
2786 | if (treg == 0) |
2787 | { | |
0dd2d296 | 2788 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2789 | likely ? "bltzl" : "bltz", |
2790 | "s,p", sreg); | |
670a50eb | 2791 | return; |
3d3c5039 | 2792 | } |
9a7d824a | 2793 | if (sreg == 0) |
670a50eb | 2794 | { |
0dd2d296 | 2795 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2796 | likely ? "bgtzl" : "bgtz", |
2797 | "s,p", treg); | |
670a50eb | 2798 | return; |
3d3c5039 | 2799 | } |
0dd2d296 ILT |
2800 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
2801 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2802 | likely ? "bnel" : "bne", |
2803 | "s,t,p", AT, 0); | |
670a50eb | 2804 | break; |
3d3c5039 | 2805 | |
8358c818 ILT |
2806 | case M_BLTUL: |
2807 | likely = 1; | |
3d3c5039 | 2808 | case M_BLTU: |
670a50eb | 2809 | if (treg == 0) |
9a7d824a ILT |
2810 | goto do_false; |
2811 | if (sreg == 0) | |
670a50eb | 2812 | { |
0dd2d296 | 2813 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2814 | likely ? "bnel" : "bne", |
2815 | "s,t,p", 0, treg); | |
670a50eb ILT |
2816 | return; |
2817 | } | |
0dd2d296 ILT |
2818 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
2819 | treg); | |
2820 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2821 | likely ? "bnel" : "bne", |
2822 | "s,t,p", AT, 0); | |
670a50eb | 2823 | break; |
3d3c5039 | 2824 | |
8358c818 ILT |
2825 | case M_DDIV_3: |
2826 | dbl = 1; | |
3d3c5039 | 2827 | case M_DIV_3: |
8358c818 ILT |
2828 | s = "mflo"; |
2829 | goto do_div3; | |
2830 | case M_DREM_3: | |
2831 | dbl = 1; | |
3d3c5039 | 2832 | case M_REM_3: |
8358c818 ILT |
2833 | s = "mfhi"; |
2834 | do_div3: | |
670a50eb ILT |
2835 | if (treg == 0) |
2836 | { | |
2837 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
2838 | if (mips_trap) |
2839 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
2840 | else | |
2841 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
2842 | return; |
2843 | } | |
2844 | ||
becfe05e ILT |
2845 | mips_emit_delays (); |
2846 | ++mips_noreorder; | |
0dd2d296 ILT |
2847 | mips_any_noreorder = 1; |
2848 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 | 2849 | dbl ? "ddiv" : "div", |
ff3a5c18 | 2850 | "z,s,t", sreg, treg); |
8ea7f4e8 ILT |
2851 | if (mips_trap) |
2852 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
2853 | else | |
2854 | { | |
2855 | expr1.X_add_number = 8; | |
2856 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2857 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
2858 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
2859 | } | |
670a50eb | 2860 | expr1.X_add_number = -1; |
0dd2d296 | 2861 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 2862 | dbl ? "daddiu" : "addiu", |
9226253a | 2863 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 2864 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 2865 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
2866 | if (dbl) |
2867 | { | |
2868 | expr1.X_add_number = 1; | |
0dd2d296 | 2869 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 2870 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
2871 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
2872 | 31); | |
8358c818 ILT |
2873 | } |
2874 | else | |
2875 | { | |
2876 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
2877 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
2878 | (int) BFD_RELOC_HI16); | |
8358c818 | 2879 | } |
8ea7f4e8 ILT |
2880 | if (mips_trap) |
2881 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
2882 | else | |
2883 | { | |
2884 | expr1.X_add_number = 8; | |
2885 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
2886 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
2887 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
2888 | } | |
becfe05e | 2889 | --mips_noreorder; |
0dd2d296 | 2890 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 2891 | break; |
3d3c5039 ILT |
2892 | |
2893 | case M_DIV_3I: | |
8358c818 ILT |
2894 | s = "div"; |
2895 | s2 = "mflo"; | |
2896 | goto do_divi; | |
3d3c5039 | 2897 | case M_DIVU_3I: |
8358c818 ILT |
2898 | s = "divu"; |
2899 | s2 = "mflo"; | |
2900 | goto do_divi; | |
3d3c5039 | 2901 | case M_REM_3I: |
8358c818 ILT |
2902 | s = "div"; |
2903 | s2 = "mfhi"; | |
2904 | goto do_divi; | |
3d3c5039 | 2905 | case M_REMU_3I: |
8358c818 ILT |
2906 | s = "divu"; |
2907 | s2 = "mfhi"; | |
2908 | goto do_divi; | |
2909 | case M_DDIV_3I: | |
2910 | dbl = 1; | |
2911 | s = "ddiv"; | |
2912 | s2 = "mflo"; | |
2913 | goto do_divi; | |
2914 | case M_DDIVU_3I: | |
2915 | dbl = 1; | |
2916 | s = "ddivu"; | |
2917 | s2 = "mflo"; | |
2918 | goto do_divi; | |
2919 | case M_DREM_3I: | |
2920 | dbl = 1; | |
2921 | s = "ddiv"; | |
2922 | s2 = "mfhi"; | |
2923 | goto do_divi; | |
2924 | case M_DREMU_3I: | |
2925 | dbl = 1; | |
2926 | s = "ddivu"; | |
2927 | s2 = "mfhi"; | |
2928 | do_divi: | |
670a50eb ILT |
2929 | if (imm_expr.X_add_number == 0) |
2930 | { | |
2931 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
2932 | if (mips_trap) |
2933 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
2934 | else | |
2935 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
2936 | return; |
2937 | } | |
2938 | if (imm_expr.X_add_number == 1) | |
2939 | { | |
8358c818 | 2940 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
2941 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
2942 | sreg); | |
3d3c5039 | 2943 | else |
0dd2d296 | 2944 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
2945 | return; |
2946 | } | |
8358c818 ILT |
2947 | if (imm_expr.X_add_number == -1 |
2948 | && s[strlen (s) - 1] != 'u') | |
2949 | { | |
2950 | if (strcmp (s2, "mflo") == 0) | |
2951 | { | |
2952 | if (dbl) | |
0dd2d296 ILT |
2953 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
2954 | sreg); | |
8358c818 | 2955 | else |
0dd2d296 ILT |
2956 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
2957 | sreg); | |
8358c818 ILT |
2958 | } |
2959 | else | |
0dd2d296 | 2960 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
2961 | return; |
2962 | } | |
3d3c5039 | 2963 | |
d8a1c247 | 2964 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 ILT |
2965 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
2966 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
2967 | break; |
2968 | ||
2969 | case M_DIVU_3: | |
8358c818 ILT |
2970 | s = "divu"; |
2971 | s2 = "mflo"; | |
2972 | goto do_divu3; | |
670a50eb | 2973 | case M_REMU_3: |
8358c818 ILT |
2974 | s = "divu"; |
2975 | s2 = "mfhi"; | |
2976 | goto do_divu3; | |
2977 | case M_DDIVU_3: | |
2978 | s = "ddivu"; | |
2979 | s2 = "mflo"; | |
2980 | goto do_divu3; | |
2981 | case M_DREMU_3: | |
2982 | s = "ddivu"; | |
2983 | s2 = "mfhi"; | |
2984 | do_divu3: | |
becfe05e ILT |
2985 | mips_emit_delays (); |
2986 | ++mips_noreorder; | |
0dd2d296 ILT |
2987 | mips_any_noreorder = 1; |
2988 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
8ea7f4e8 ILT |
2989 | if (mips_trap) |
2990 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
2991 | else | |
2992 | { | |
2993 | expr1.X_add_number = 8; | |
2994 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2995 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
2996 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
2997 | } | |
becfe05e | 2998 | --mips_noreorder; |
0dd2d296 | 2999 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 3000 | return; |
3d3c5039 | 3001 | |
d8a1c247 KR |
3002 | case M_DLA_AB: |
3003 | dbl = 1; | |
0dd2d296 | 3004 | case M_LA_AB: |
d9aba805 ILT |
3005 | /* Load the address of a symbol into a register. If breg is not |
3006 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
3007 | |
3008 | /* When generating embedded PIC code, we permit expressions of | |
3009 | the form | |
3010 | la $4,foo-bar | |
3011 | where bar is an address in the .text section. These are used | |
3012 | when getting the addresses of functions. We don't permit | |
3013 | X_add_number to be non-zero, because if the symbol is | |
3014 | external the relaxing code needs to know that any addend is | |
3015 | purely the offset to X_op_symbol. */ | |
3016 | if (mips_pic == EMBEDDED_PIC | |
3017 | && offset_expr.X_op == O_subtract | |
3018 | && now_seg == text_section | |
847a01cd ILT |
3019 | && (offset_expr.X_op_symbol->sy_value.X_op == O_constant |
3020 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
3021 | : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol | |
3022 | && (S_GET_SEGMENT (offset_expr.X_op_symbol | |
3023 | ->sy_value.X_add_symbol) | |
3024 | == text_section))) | |
ecd4ca1c ILT |
3025 | && breg == 0 |
3026 | && offset_expr.X_add_number == 0) | |
3027 | { | |
3028 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3029 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
3030 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3031 | mips_isa < 3 ? "addiu" : "daddiu", | |
3032 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); | |
3033 | return; | |
3034 | } | |
3035 | ||
0dd2d296 ILT |
3036 | if (offset_expr.X_op != O_symbol |
3037 | && offset_expr.X_op != O_constant) | |
670a50eb | 3038 | { |
0dd2d296 ILT |
3039 | as_bad ("expression too complex"); |
3040 | offset_expr.X_op = O_constant; | |
3041 | } | |
3042 | ||
3043 | if (treg == breg) | |
3044 | { | |
3045 | tempreg = AT; | |
3046 | used_at = 1; | |
3d3c5039 | 3047 | } |
670a50eb ILT |
3048 | else |
3049 | { | |
0dd2d296 ILT |
3050 | tempreg = treg; |
3051 | used_at = 0; | |
670a50eb | 3052 | } |
3d3c5039 | 3053 | |
5ac34ac3 | 3054 | if (offset_expr.X_op == O_constant) |
d8a1c247 | 3055 | load_register (&icnt, tempreg, &offset_expr, dbl); |
d9aba805 | 3056 | else if (mips_pic == NO_PIC) |
670a50eb | 3057 | { |
0dd2d296 ILT |
3058 | /* If this is a reference to an GP relative symbol, we want |
3059 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3060 | Otherwise we want | |
3061 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
3062 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3063 | If we have a constant, we need two instructions anyhow, | |
3064 | so we may as well always use the latter form. */ | |
7a15a226 | 3065 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 3066 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
3067 | p = NULL; |
3068 | else | |
3069 | { | |
8ea7f4e8 | 3070 | frag_grow (20); |
0dd2d296 ILT |
3071 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3072 | mips_isa < 3 ? "addiu" : "daddiu", | |
3073 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3074 | p = frag_var (rs_machine_dependent, 8, 0, | |
3075 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3076 | mips_warn_about_macros), | |
3077 | offset_expr.X_add_symbol, (long) 0, | |
3078 | (char *) NULL); | |
3079 | } | |
3080 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
3081 | if (p != NULL) | |
3082 | p += 4; | |
3083 | macro_build (p, &icnt, &offset_expr, | |
6e8dda9c | 3084 | mips_isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3085 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
3086 | } | |
fb251650 | 3087 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3088 | { |
3089 | /* If this is a reference to an external symbol, and there | |
3090 | is no constant, we want | |
3091 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3092 | For a local symbol, we want | |
3093 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3094 | nop | |
3095 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3096 | ||
3097 | If we have a small constant, and this is a reference to | |
3098 | an external symbol, we want | |
3099 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3100 | nop | |
3101 | addiu $tempreg,$tempreg,<constant> | |
3102 | For a local symbol, we want the same instruction | |
3103 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
3104 | addiu instruction. | |
3105 | ||
3106 | If we have a large constant, and this is a reference to | |
3107 | an external symbol, we want | |
3108 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3109 | lui $at,<hiconstant> | |
3110 | addiu $at,$at,<loconstant> | |
3111 | addu $tempreg,$tempreg,$at | |
3112 | For a local symbol, we want the same instruction | |
3113 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
3114 | addiu instruction. */ | |
3115 | expr1.X_add_number = offset_expr.X_add_number; | |
3116 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 3117 | frag_grow (32); |
0dd2d296 | 3118 | macro_build ((char *) NULL, &icnt, &offset_expr, |
d8a1c247 | 3119 | dbl ? "ld" : "lw", |
0dd2d296 ILT |
3120 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3121 | if (expr1.X_add_number == 0) | |
3122 | { | |
3123 | int off; | |
3124 | ||
3125 | if (breg == 0) | |
3126 | off = 0; | |
3127 | else | |
3128 | { | |
3129 | /* We're going to put in an addu instruction using | |
3130 | tempreg, so we may as well insert the nop right | |
3131 | now. */ | |
3132 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3133 | "nop", ""); | |
3134 | off = 4; | |
3135 | } | |
3136 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
3137 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
3138 | (breg == 0 | |
3139 | ? mips_warn_about_macros | |
3140 | : 0)), | |
3141 | offset_expr.X_add_symbol, (long) 0, | |
3142 | (char *) NULL); | |
3143 | if (breg == 0) | |
3144 | { | |
3145 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3146 | p += 4; | |
3147 | } | |
3148 | macro_build (p, &icnt, &expr1, | |
3149 | mips_isa < 3 ? "addiu" : "daddiu", | |
3150 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3151 | /* FIXME: If breg == 0, and the next instruction uses | |
3152 | $tempreg, then if this variant case is used an extra | |
3153 | nop will be generated. */ | |
3154 | } | |
3155 | else if (expr1.X_add_number >= -0x8000 | |
3156 | && expr1.X_add_number < 0x8000) | |
3157 | { | |
3158 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3159 | "nop", ""); | |
3160 | macro_build ((char *) NULL, &icnt, &expr1, | |
3161 | mips_isa < 3 ? "addiu" : "daddiu", | |
3162 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3163 | (void) frag_var (rs_machine_dependent, 0, 0, | |
3164 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
3165 | offset_expr.X_add_symbol, (long) 0, | |
3166 | (char *) NULL); | |
3167 | } | |
3168 | else | |
3169 | { | |
3170 | int off1; | |
3171 | ||
3172 | /* If we are going to add in a base register, and the | |
3173 | target register and the base register are the same, | |
3174 | then we are using AT as a temporary register. Since | |
3175 | we want to load the constant into AT, we add our | |
3176 | current AT (from the global offset table) and the | |
3177 | register into the register now, and pretend we were | |
3178 | not using a base register. */ | |
3179 | if (breg != treg) | |
3180 | off1 = 0; | |
3181 | else | |
3182 | { | |
3183 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3184 | "nop", ""); | |
3185 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3186 | mips_isa < 3 ? "addu" : "daddu", | |
3187 | "d,v,t", treg, AT, breg); | |
3188 | breg = 0; | |
3189 | tempreg = treg; | |
3190 | off1 = -8; | |
3191 | } | |
3192 | ||
55933a58 ILT |
3193 | /* Set mips_optimize around the lui instruction to avoid |
3194 | inserting an unnecessary nop after the lw. */ | |
3195 | hold_mips_optimize = mips_optimize; | |
3196 | mips_optimize = 2; | |
0dd2d296 | 3197 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
3198 | mips_optimize = hold_mips_optimize; |
3199 | ||
0dd2d296 ILT |
3200 | macro_build ((char *) NULL, &icnt, &expr1, |
3201 | mips_isa < 3 ? "addiu" : "daddiu", | |
3202 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
3203 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3204 | mips_isa < 3 ? "addu" : "daddu", | |
3205 | "d,v,t", tempreg, tempreg, AT); | |
3206 | (void) frag_var (rs_machine_dependent, 0, 0, | |
3207 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
3208 | offset_expr.X_add_symbol, (long) 0, | |
3209 | (char *) NULL); | |
3210 | used_at = 1; | |
3211 | } | |
670a50eb | 3212 | } |
fb251650 ILT |
3213 | else if (mips_pic == SVR4_PIC) |
3214 | { | |
3215 | int gpdel; | |
3216 | ||
3217 | /* This is the large GOT case. If this is a reference to an | |
3218 | external symbol, and there is no constant, we want | |
3219 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3220 | addu $tempreg,$tempreg,$gp | |
3221 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3222 | For a local symbol, we want | |
3223 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3224 | nop | |
3225 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3226 | ||
3227 | If we have a small constant, and this is a reference to | |
3228 | an external symbol, we want | |
3229 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3230 | addu $tempreg,$tempreg,$gp | |
3231 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3232 | nop | |
3233 | addiu $tempreg,$tempreg,<constant> | |
3234 | For a local symbol, we want | |
3235 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3236 | nop | |
3237 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
3238 | ||
3239 | If we have a large constant, and this is a reference to | |
3240 | an external symbol, we want | |
3241 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3242 | addu $tempreg,$tempreg,$gp | |
3243 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3244 | lui $at,<hiconstant> | |
3245 | addiu $at,$at,<loconstant> | |
3246 | addu $tempreg,$tempreg,$at | |
3247 | For a local symbol, we want | |
3248 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3249 | lui $at,<hiconstant> | |
3250 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
3251 | addu $tempreg,$tempreg,$at | |
3252 | */ | |
3253 | expr1.X_add_number = offset_expr.X_add_number; | |
3254 | offset_expr.X_add_number = 0; | |
3255 | frag_grow (52); | |
3256 | if (reg_needs_delay (GP)) | |
3257 | gpdel = 4; | |
3258 | else | |
3259 | gpdel = 0; | |
3260 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3261 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
3262 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3263 | mips_isa < 3 ? "addu" : "daddu", | |
3264 | "d,v,t", tempreg, tempreg, GP); | |
3265 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3266 | dbl ? "ld" : "lw", | |
3267 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
3268 | tempreg); | |
3269 | if (expr1.X_add_number == 0) | |
3270 | { | |
3271 | int off; | |
3272 | ||
3273 | if (breg == 0) | |
3274 | off = 0; | |
3275 | else | |
3276 | { | |
3277 | /* We're going to put in an addu instruction using | |
3278 | tempreg, so we may as well insert the nop right | |
3279 | now. */ | |
3280 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3281 | "nop", ""); | |
3282 | off = 4; | |
3283 | } | |
3284 | ||
3285 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
3286 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
3287 | 8 + gpdel, 0, | |
3288 | (breg == 0 | |
3289 | ? mips_warn_about_macros | |
3290 | : 0)), | |
3291 | offset_expr.X_add_symbol, (long) 0, | |
3292 | (char *) NULL); | |
3293 | } | |
3294 | else if (expr1.X_add_number >= -0x8000 | |
3295 | && expr1.X_add_number < 0x8000) | |
3296 | { | |
3297 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3298 | "nop", ""); | |
3299 | macro_build ((char *) NULL, &icnt, &expr1, | |
3300 | mips_isa < 3 ? "addiu" : "daddiu", | |
3301 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3302 | ||
3303 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
3304 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
3305 | (breg == 0 | |
3306 | ? mips_warn_about_macros | |
3307 | : 0)), | |
3308 | offset_expr.X_add_symbol, (long) 0, | |
3309 | (char *) NULL); | |
3310 | } | |
3311 | else | |
3312 | { | |
3313 | int adj, dreg; | |
3314 | ||
3315 | /* If we are going to add in a base register, and the | |
3316 | target register and the base register are the same, | |
3317 | then we are using AT as a temporary register. Since | |
3318 | we want to load the constant into AT, we add our | |
3319 | current AT (from the global offset table) and the | |
3320 | register into the register now, and pretend we were | |
3321 | not using a base register. */ | |
3322 | if (breg != treg) | |
3323 | { | |
3324 | adj = 0; | |
3325 | dreg = tempreg; | |
3326 | } | |
3327 | else | |
3328 | { | |
3329 | assert (tempreg == AT); | |
3330 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3331 | "nop", ""); | |
3332 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3333 | mips_isa < 3 ? "addu" : "daddu", | |
3334 | "d,v,t", treg, AT, breg); | |
3335 | dreg = treg; | |
3336 | adj = 8; | |
3337 | } | |
3338 | ||
3339 | /* Set mips_optimize around the lui instruction to avoid | |
3340 | inserting an unnecessary nop after the lw. */ | |
3341 | hold_mips_optimize = mips_optimize; | |
3342 | mips_optimize = 2; | |
3343 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
3344 | mips_optimize = hold_mips_optimize; | |
3345 | ||
3346 | macro_build ((char *) NULL, &icnt, &expr1, | |
3347 | mips_isa < 3 ? "addiu" : "daddiu", | |
3348 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
3349 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3350 | mips_isa < 3 ? "addu" : "daddu", | |
3351 | "d,v,t", dreg, dreg, AT); | |
3352 | ||
3353 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
3354 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
3355 | 8 + gpdel, 0, | |
3356 | (breg == 0 | |
3357 | ? mips_warn_about_macros | |
3358 | : 0)), | |
3359 | offset_expr.X_add_symbol, (long) 0, | |
3360 | (char *) NULL); | |
3361 | ||
3362 | used_at = 1; | |
3363 | } | |
3364 | ||
3365 | if (gpdel > 0) | |
3366 | { | |
3367 | /* This is needed because this instruction uses $gp, but | |
3368 | the first instruction on the main stream does not. */ | |
3369 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3370 | p += 4; | |
3371 | } | |
3372 | macro_build (p, &icnt, &offset_expr, | |
3373 | dbl ? "ld" : "lw", | |
3374 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3375 | p += 4; | |
3376 | if (expr1.X_add_number >= -0x8000 | |
3377 | && expr1.X_add_number < 0x8000) | |
3378 | { | |
3379 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3380 | p += 4; | |
3381 | macro_build (p, &icnt, &expr1, | |
3382 | mips_isa < 3 ? "addiu" : "daddiu", | |
3383 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3384 | /* FIXME: If add_number is 0, and there was no base | |
3385 | register, the external symbol case ended with a load, | |
3386 | so if the symbol turns out to not be external, and | |
3387 | the next instruction uses tempreg, an unnecessary nop | |
3388 | will be inserted. */ | |
3389 | } | |
3390 | else | |
3391 | { | |
3392 | if (breg == treg) | |
3393 | { | |
3394 | /* We must add in the base register now, as in the | |
3395 | external symbol case. */ | |
3396 | assert (tempreg == AT); | |
3397 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3398 | p += 4; | |
3399 | macro_build (p, &icnt, (expressionS *) NULL, | |
3400 | mips_isa < 3 ? "addu" : "daddu", | |
3401 | "d,v,t", treg, AT, breg); | |
3402 | p += 4; | |
3403 | tempreg = treg; | |
3404 | /* We set breg to 0 because we have arranged to add | |
3405 | it in in both cases. */ | |
3406 | breg = 0; | |
3407 | } | |
3408 | ||
3409 | macro_build_lui (p, &icnt, &expr1, AT); | |
3410 | p += 4; | |
3411 | macro_build (p, &icnt, &expr1, | |
3412 | mips_isa < 3 ? "addiu" : "daddiu", | |
3413 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
3414 | p += 4; | |
3415 | macro_build (p, &icnt, (expressionS *) NULL, | |
3416 | mips_isa < 3 ? "addu" : "daddu", | |
3417 | "d,v,t", tempreg, tempreg, AT); | |
3418 | p += 4; | |
3419 | } | |
3420 | } | |
d9aba805 ILT |
3421 | else if (mips_pic == EMBEDDED_PIC) |
3422 | { | |
3423 | /* We use | |
3424 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3425 | */ | |
3426 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3427 | mips_isa < 3 ? "addiu" : "daddiu", | |
3428 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3429 | } | |
3430 | else | |
3431 | abort (); | |
0dd2d296 | 3432 | |
670a50eb | 3433 | if (breg != 0) |
0dd2d296 ILT |
3434 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3435 | mips_isa < 3 ? "addu" : "daddu", | |
3436 | "d,v,t", treg, tempreg, breg); | |
3437 | ||
3438 | if (! used_at) | |
3439 | return; | |
3440 | ||
3441 | break; | |
3442 | ||
3443 | case M_J_A: | |
3444 | /* The j instruction may not be used in PIC code, since it | |
3445 | requires an absolute address. We convert it to a b | |
3446 | instruction. */ | |
d9aba805 | 3447 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
3448 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
3449 | else | |
3450 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 3451 | return; |
3d3c5039 | 3452 | |
9226253a ILT |
3453 | /* The jal instructions must be handled as macros because when |
3454 | generating PIC code they expand to multi-instruction | |
3455 | sequences. Normally they are simple instructions. */ | |
3456 | case M_JAL_1: | |
3457 | dreg = RA; | |
3458 | /* Fall through. */ | |
3459 | case M_JAL_2: | |
d9aba805 ILT |
3460 | if (mips_pic == NO_PIC |
3461 | || mips_pic == EMBEDDED_PIC) | |
3462 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
3463 | "d,s", dreg, sreg); | |
3464 | else if (mips_pic == SVR4_PIC) | |
9226253a | 3465 | { |
d9aba805 ILT |
3466 | if (sreg != PIC_CALL_REG) |
3467 | as_warn ("MIPS PIC call to register other than $25"); | |
3468 | ||
0dd2d296 ILT |
3469 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
3470 | "d,s", dreg, sreg); | |
d9aba805 ILT |
3471 | if (mips_cprestore_offset < 0) |
3472 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
3473 | else | |
3474 | { | |
3475 | expr1.X_add_number = mips_cprestore_offset; | |
3476 | macro_build ((char *) NULL, &icnt, &expr1, | |
3477 | mips_isa < 3 ? "lw" : "ld", | |
3478 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
3479 | } | |
9226253a | 3480 | } |
0dd2d296 | 3481 | else |
d9aba805 ILT |
3482 | abort (); |
3483 | ||
9226253a ILT |
3484 | return; |
3485 | ||
3486 | case M_JAL_A: | |
d9aba805 ILT |
3487 | if (mips_pic == NO_PIC) |
3488 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
3489 | else if (mips_pic == SVR4_PIC) | |
9226253a | 3490 | { |
fb251650 ILT |
3491 | /* If this is a reference to an external symbol, and we are |
3492 | using a small GOT, we want | |
d9aba805 ILT |
3493 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
3494 | nop | |
3495 | jalr $25 | |
3496 | nop | |
3497 | lw $gp,cprestore($sp) | |
3498 | The cprestore value is set using the .cprestore | |
fb251650 ILT |
3499 | pseudo-op. If we are using a big GOT, we want |
3500 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
3501 | addu $25,$25,$gp | |
3502 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
3503 | nop | |
3504 | jalr $25 | |
3505 | nop | |
3506 | lw $gp,cprestore($sp) | |
3507 | If the symbol is not external, we want | |
d9aba805 ILT |
3508 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3509 | nop | |
3510 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
3511 | jalr $25 | |
3512 | nop | |
fb251650 ILT |
3513 | lw $gp,cprestore($sp) */ |
3514 | frag_grow (40); | |
3515 | if (! mips_big_got) | |
3516 | { | |
3517 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3518 | mips_isa < 3 ? "lw" : "ld", | |
3519 | "t,o(b)", PIC_CALL_REG, | |
3520 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
3521 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3522 | "nop", ""); | |
3523 | p = frag_var (rs_machine_dependent, 4, 0, | |
3524 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
3525 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
3526 | } | |
3527 | else | |
3528 | { | |
3529 | int gpdel; | |
3530 | ||
3531 | if (reg_needs_delay (GP)) | |
3532 | gpdel = 4; | |
3533 | else | |
3534 | gpdel = 0; | |
3535 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3536 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
3537 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3538 | mips_isa < 3 ? "addu" : "daddu", | |
3539 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); | |
3540 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3541 | mips_isa < 3 ? "lw" : "ld", | |
3542 | "t,o(b)", PIC_CALL_REG, | |
3543 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
3544 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3545 | "nop", ""); | |
3546 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
3547 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
3548 | 0, 0), | |
3549 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
3550 | if (gpdel > 0) | |
3551 | { | |
3552 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3553 | p += 4; | |
3554 | } | |
3555 | macro_build (p, &icnt, &offset_expr, | |
3556 | mips_isa < 3 ? "lw" : "ld", | |
3557 | "t,o(b)", PIC_CALL_REG, | |
3558 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
3559 | p += 4; | |
3560 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3561 | p += 4; | |
3562 | } | |
d9aba805 ILT |
3563 | macro_build (p, &icnt, &offset_expr, |
3564 | mips_isa < 3 ? "addiu" : "daddiu", | |
3565 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
3566 | (int) BFD_RELOC_LO16); | |
3567 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3568 | "jalr", "s", PIC_CALL_REG); | |
3569 | if (mips_cprestore_offset < 0) | |
3570 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
3571 | else | |
3572 | { | |
3573 | if (mips_noreorder) | |
3574 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3575 | "nop", ""); | |
3576 | expr1.X_add_number = mips_cprestore_offset; | |
3577 | macro_build ((char *) NULL, &icnt, &expr1, | |
3578 | mips_isa < 3 ? "lw" : "ld", | |
3579 | "t,o(b)", GP, (int) BFD_RELOC_LO16, | |
3580 | mips_frame_reg); | |
3581 | } | |
0dd2d296 | 3582 | } |
d9aba805 | 3583 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
3584 | { |
3585 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
3586 | /* The linker may expand the call to a longer sequence which | |
3587 | uses $at, so we must break rather than return. */ | |
3588 | break; | |
3589 | } | |
d9aba805 ILT |
3590 | else |
3591 | abort (); | |
3592 | ||
9226253a ILT |
3593 | return; |
3594 | ||
3d3c5039 | 3595 | case M_LB_AB: |
670a50eb ILT |
3596 | s = "lb"; |
3597 | goto ld; | |
3d3c5039 | 3598 | case M_LBU_AB: |
670a50eb ILT |
3599 | s = "lbu"; |
3600 | goto ld; | |
3d3c5039 | 3601 | case M_LH_AB: |
670a50eb ILT |
3602 | s = "lh"; |
3603 | goto ld; | |
3d3c5039 | 3604 | case M_LHU_AB: |
670a50eb ILT |
3605 | s = "lhu"; |
3606 | goto ld; | |
3d3c5039 | 3607 | case M_LW_AB: |
670a50eb ILT |
3608 | s = "lw"; |
3609 | goto ld; | |
3d3c5039 | 3610 | case M_LWC0_AB: |
670a50eb | 3611 | s = "lwc0"; |
8358c818 | 3612 | coproc = 1; |
670a50eb | 3613 | goto ld; |
3d3c5039 | 3614 | case M_LWC1_AB: |
670a50eb | 3615 | s = "lwc1"; |
8358c818 | 3616 | coproc = 1; |
670a50eb | 3617 | goto ld; |
3d3c5039 | 3618 | case M_LWC2_AB: |
670a50eb | 3619 | s = "lwc2"; |
8358c818 | 3620 | coproc = 1; |
670a50eb | 3621 | goto ld; |
3d3c5039 | 3622 | case M_LWC3_AB: |
670a50eb | 3623 | s = "lwc3"; |
8358c818 | 3624 | coproc = 1; |
670a50eb | 3625 | goto ld; |
3d3c5039 | 3626 | case M_LWL_AB: |
670a50eb | 3627 | s = "lwl"; |
b2b8c24e | 3628 | lr = 1; |
670a50eb | 3629 | goto ld; |
3d3c5039 | 3630 | case M_LWR_AB: |
670a50eb | 3631 | s = "lwr"; |
b2b8c24e | 3632 | lr = 1; |
8358c818 ILT |
3633 | goto ld; |
3634 | case M_LDC1_AB: | |
3635 | s = "ldc1"; | |
3636 | coproc = 1; | |
3637 | goto ld; | |
3638 | case M_LDC2_AB: | |
3639 | s = "ldc2"; | |
3640 | coproc = 1; | |
3641 | goto ld; | |
3642 | case M_LDC3_AB: | |
3643 | s = "ldc3"; | |
3644 | coproc = 1; | |
3645 | goto ld; | |
3646 | case M_LDL_AB: | |
3647 | s = "ldl"; | |
b2b8c24e | 3648 | lr = 1; |
8358c818 ILT |
3649 | goto ld; |
3650 | case M_LDR_AB: | |
3651 | s = "ldr"; | |
b2b8c24e | 3652 | lr = 1; |
8358c818 ILT |
3653 | goto ld; |
3654 | case M_LL_AB: | |
3655 | s = "ll"; | |
3656 | goto ld; | |
3657 | case M_LLD_AB: | |
3658 | s = "lld"; | |
3659 | goto ld; | |
3660 | case M_LWU_AB: | |
3661 | s = "lwu"; | |
3d3c5039 | 3662 | ld: |
b2b8c24e | 3663 | if (breg == treg || coproc || lr) |
670a50eb ILT |
3664 | { |
3665 | tempreg = AT; | |
3666 | used_at = 1; | |
3667 | } | |
3668 | else | |
3669 | { | |
3670 | tempreg = treg; | |
3671 | used_at = 0; | |
3672 | } | |
3673 | goto ld_st; | |
3d3c5039 | 3674 | case M_SB_AB: |
670a50eb ILT |
3675 | s = "sb"; |
3676 | goto st; | |
3d3c5039 | 3677 | case M_SH_AB: |
670a50eb ILT |
3678 | s = "sh"; |
3679 | goto st; | |
3d3c5039 | 3680 | case M_SW_AB: |
670a50eb ILT |
3681 | s = "sw"; |
3682 | goto st; | |
3d3c5039 | 3683 | case M_SWC0_AB: |
670a50eb | 3684 | s = "swc0"; |
8358c818 | 3685 | coproc = 1; |
670a50eb | 3686 | goto st; |
3d3c5039 | 3687 | case M_SWC1_AB: |
670a50eb | 3688 | s = "swc1"; |
8358c818 | 3689 | coproc = 1; |
670a50eb | 3690 | goto st; |
3d3c5039 | 3691 | case M_SWC2_AB: |
670a50eb | 3692 | s = "swc2"; |
8358c818 | 3693 | coproc = 1; |
670a50eb | 3694 | goto st; |
3d3c5039 | 3695 | case M_SWC3_AB: |
670a50eb | 3696 | s = "swc3"; |
8358c818 | 3697 | coproc = 1; |
670a50eb | 3698 | goto st; |
3d3c5039 | 3699 | case M_SWL_AB: |
670a50eb ILT |
3700 | s = "swl"; |
3701 | goto st; | |
3d3c5039 | 3702 | case M_SWR_AB: |
670a50eb | 3703 | s = "swr"; |
8358c818 ILT |
3704 | goto st; |
3705 | case M_SC_AB: | |
3706 | s = "sc"; | |
3707 | goto st; | |
3708 | case M_SCD_AB: | |
3709 | s = "scd"; | |
3710 | goto st; | |
3711 | case M_SDC1_AB: | |
3712 | s = "sdc1"; | |
3713 | coproc = 1; | |
3714 | goto st; | |
3715 | case M_SDC2_AB: | |
3716 | s = "sdc2"; | |
3717 | coproc = 1; | |
3718 | goto st; | |
3719 | case M_SDC3_AB: | |
3720 | s = "sdc3"; | |
3721 | coproc = 1; | |
3722 | goto st; | |
3723 | case M_SDL_AB: | |
3724 | s = "sdl"; | |
3725 | goto st; | |
3726 | case M_SDR_AB: | |
3727 | s = "sdr"; | |
3d3c5039 | 3728 | st: |
670a50eb ILT |
3729 | tempreg = AT; |
3730 | used_at = 1; | |
3d3c5039 | 3731 | ld_st: |
8358c818 ILT |
3732 | if (mask == M_LWC1_AB |
3733 | || mask == M_SWC1_AB | |
8358c818 | 3734 | || mask == M_LDC1_AB |
0dd2d296 ILT |
3735 | || mask == M_SDC1_AB |
3736 | || mask == M_L_DAB | |
3737 | || mask == M_S_DAB) | |
670a50eb | 3738 | fmt = "T,o(b)"; |
8358c818 | 3739 | else if (coproc) |
19ed8960 | 3740 | fmt = "E,o(b)"; |
670a50eb ILT |
3741 | else |
3742 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
3743 | |
3744 | if (offset_expr.X_op != O_constant | |
3745 | && offset_expr.X_op != O_symbol) | |
3746 | { | |
3747 | as_bad ("expression too complex"); | |
3748 | offset_expr.X_op = O_constant; | |
3749 | } | |
3750 | ||
3751 | /* A constant expression in PIC code can be handled just as it | |
3752 | is in non PIC code. */ | |
d9aba805 | 3753 | if (mips_pic == NO_PIC |
0dd2d296 | 3754 | || offset_expr.X_op == O_constant) |
670a50eb | 3755 | { |
0dd2d296 ILT |
3756 | /* If this is a reference to a GP relative symbol, and there |
3757 | is no base register, we want | |
3758 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 3759 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
3760 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
3761 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
3762 | If we have a constant, we need two instructions anyhow, | |
3763 | so we always use the latter form. | |
3764 | ||
3765 | If we have a base register, and this is a reference to a | |
3766 | GP relative symbol, we want | |
3767 | addu $tempreg,$breg,$gp | |
3768 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
3769 | Otherwise we want | |
3770 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
3771 | addu $tempreg,$tempreg,$breg | |
3772 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
3773 | With a constant we always use the latter case. */ | |
670a50eb ILT |
3774 | if (breg == 0) |
3775 | { | |
7a15a226 | 3776 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 3777 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
3778 | p = NULL; |
3779 | else | |
3780 | { | |
8ea7f4e8 | 3781 | frag_grow (20); |
0dd2d296 ILT |
3782 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
3783 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
3784 | p = frag_var (rs_machine_dependent, 8, 0, | |
3785 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
8197b589 ILT |
3786 | (mips_warn_about_macros |
3787 | || (used_at && mips_noat))), | |
0dd2d296 ILT |
3788 | offset_expr.X_add_symbol, (long) 0, |
3789 | (char *) NULL); | |
8197b589 | 3790 | used_at = 0; |
0dd2d296 ILT |
3791 | } |
3792 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
3793 | if (p != NULL) | |
3794 | p += 4; | |
3795 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
3796 | (int) BFD_RELOC_LO16, tempreg); | |
3797 | } | |
3798 | else | |
3799 | { | |
7a15a226 | 3800 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 3801 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
3802 | p = NULL; |
3803 | else | |
3804 | { | |
8ea7f4e8 | 3805 | frag_grow (28); |
0dd2d296 ILT |
3806 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3807 | mips_isa < 3 ? "addu" : "daddu", | |
3808 | "d,v,t", tempreg, breg, GP); | |
3809 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
3810 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
3811 | p = frag_var (rs_machine_dependent, 12, 0, | |
3812 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
3813 | offset_expr.X_add_symbol, (long) 0, | |
3814 | (char *) NULL); | |
3815 | } | |
3816 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
3817 | if (p != NULL) | |
3818 | p += 4; | |
3819 | macro_build (p, &icnt, (expressionS *) NULL, | |
3820 | mips_isa < 3 ? "addu" : "daddu", | |
3821 | "d,v,t", tempreg, tempreg, breg); | |
3822 | if (p != NULL) | |
3823 | p += 4; | |
3824 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
3825 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 3826 | } |
670a50eb | 3827 | } |
fb251650 | 3828 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 3829 | { |
0dd2d296 ILT |
3830 | /* If this is a reference to an external symbol, we want |
3831 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3832 | nop | |
3833 | <op> $treg,0($tempreg) | |
3834 | Otherwise we want | |
3835 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3836 | nop | |
3837 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3838 | <op> $treg,0($tempreg) | |
3839 | If there is a base register, we add it to $tempreg before | |
3840 | the <op>. If there is a constant, we stick it in the | |
3841 | <op> instruction. We don't handle constants larger than | |
3842 | 16 bits, because we have no way to load the upper 16 bits | |
3843 | (actually, we could handle them for the subset of cases | |
3844 | in which we are not using $at). */ | |
3845 | assert (offset_expr.X_op == O_symbol); | |
3846 | expr1.X_add_number = offset_expr.X_add_number; | |
3847 | offset_expr.X_add_number = 0; | |
3848 | if (expr1.X_add_number < -0x8000 | |
3849 | || expr1.X_add_number >= 0x8000) | |
3850 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
8ea7f4e8 | 3851 | frag_grow (20); |
0dd2d296 ILT |
3852 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3853 | mips_isa < 3 ? "lw" : "ld", | |
3854 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3855 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
3856 | p = frag_var (rs_machine_dependent, 4, 0, | |
3857 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
3858 | offset_expr.X_add_symbol, (long) 0, | |
3859 | (char *) NULL); | |
3860 | macro_build (p, &icnt, &offset_expr, | |
3861 | mips_isa < 3 ? "addiu" : "daddiu", | |
3862 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
670a50eb | 3863 | if (breg != 0) |
0dd2d296 | 3864 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c ILT |
3865 | mips_isa < 3 ? "addu" : "daddu", |
3866 | "d,v,t", tempreg, tempreg, breg); | |
0dd2d296 ILT |
3867 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
3868 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 3869 | } |
fb251650 ILT |
3870 | else if (mips_pic == SVR4_PIC) |
3871 | { | |
3872 | int gpdel; | |
3873 | ||
3874 | /* If this is a reference to an external symbol, we want | |
3875 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3876 | addu $tempreg,$tempreg,$gp | |
3877 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3878 | <op> $treg,0($tempreg) | |
3879 | Otherwise we want | |
3880 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3881 | nop | |
3882 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3883 | <op> $treg,0($tempreg) | |
3884 | If there is a base register, we add it to $tempreg before | |
3885 | the <op>. If there is a constant, we stick it in the | |
3886 | <op> instruction. We don't handle constants larger than | |
3887 | 16 bits, because we have no way to load the upper 16 bits | |
3888 | (actually, we could handle them for the subset of cases | |
3889 | in which we are not using $at). */ | |
3890 | assert (offset_expr.X_op == O_symbol); | |
3891 | expr1.X_add_number = offset_expr.X_add_number; | |
3892 | offset_expr.X_add_number = 0; | |
3893 | if (expr1.X_add_number < -0x8000 | |
3894 | || expr1.X_add_number >= 0x8000) | |
3895 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3896 | if (reg_needs_delay (GP)) | |
3897 | gpdel = 4; | |
3898 | else | |
3899 | gpdel = 0; | |
3900 | frag_grow (36); | |
3901 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3902 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
3903 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3904 | mips_isa < 3 ? "addu" : "daddu", | |
3905 | "d,v,t", tempreg, tempreg, GP); | |
3906 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3907 | mips_isa < 3 ? "lw" : "ld", | |
867a58b3 ILT |
3908 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
3909 | tempreg); | |
fb251650 ILT |
3910 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
3911 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
3912 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
3913 | if (gpdel > 0) | |
3914 | { | |
3915 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3916 | p += 4; | |
3917 | } | |
3918 | macro_build (p, &icnt, &offset_expr, | |
3919 | mips_isa < 3 ? "lw" : "ld", | |
867a58b3 | 3920 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
fb251650 ILT |
3921 | p += 4; |
3922 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3923 | p += 4; | |
3924 | macro_build (p, &icnt, &offset_expr, | |
3925 | mips_isa < 3 ? "addiu" : "daddiu", | |
3926 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3927 | if (breg != 0) | |
3928 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3929 | mips_isa < 3 ? "addu" : "daddu", | |
3930 | "d,v,t", tempreg, tempreg, breg); | |
3931 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
3932 | (int) BFD_RELOC_LO16, tempreg); | |
3933 | } | |
d9aba805 ILT |
3934 | else if (mips_pic == EMBEDDED_PIC) |
3935 | { | |
3936 | /* If there is no base register, we want | |
3937 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
3938 | If there is a base register, we want | |
3939 | addu $tempreg,$breg,$gp | |
3940 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
3941 | */ | |
3942 | assert (offset_expr.X_op == O_symbol); | |
3943 | if (breg == 0) | |
3944 | { | |
3945 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
3946 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
3947 | used_at = 0; | |
3948 | } | |
3949 | else | |
3950 | { | |
3951 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3952 | mips_isa < 3 ? "addu" : "daddu", | |
3953 | "d,v,t", tempreg, breg, GP); | |
3954 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
3955 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
3956 | } | |
3957 | } | |
3958 | else | |
3959 | abort (); | |
0dd2d296 ILT |
3960 | |
3961 | if (! used_at) | |
3962 | return; | |
3963 | ||
3964 | break; | |
3d3c5039 ILT |
3965 | |
3966 | case M_LI: | |
19ed8960 | 3967 | case M_LI_S: |
d8a1c247 KR |
3968 | load_register (&icnt, treg, &imm_expr, 0); |
3969 | return; | |
3970 | ||
3971 | case M_DLI: | |
3972 | load_register (&icnt, treg, &imm_expr, 1); | |
670a50eb | 3973 | return; |
3d3c5039 | 3974 | |
0dd2d296 | 3975 | case M_LI_SS: |
55933a58 | 3976 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 3977 | { |
d8a1c247 | 3978 | load_register (&icnt, AT, &imm_expr, 0); |
d2c71068 ILT |
3979 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3980 | "mtc1", "t,G", AT, treg); | |
3981 | break; | |
0dd2d296 | 3982 | } |
d9aba805 | 3983 | else |
d2c71068 | 3984 | { |
55933a58 ILT |
3985 | assert (offset_expr.X_op == O_symbol |
3986 | && strcmp (segment_name (S_GET_SEGMENT | |
3987 | (offset_expr.X_add_symbol)), | |
3988 | ".lit4") == 0 | |
3989 | && offset_expr.X_add_number == 0); | |
3990 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
3991 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
3992 | return; |
3993 | } | |
0dd2d296 | 3994 | |
3d3c5039 | 3995 | case M_LI_D: |
d9aba805 ILT |
3996 | /* We know that sym is in the .rdata section. First we get the |
3997 | upper 16 bits of the address. */ | |
3998 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
3999 | { |
4000 | /* FIXME: This won't work for a 64 bit address. */ | |
4001 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4002 | } | |
d9aba805 | 4003 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
4004 | { |
4005 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4006 | mips_isa < 3 ? "lw" : "ld", | |
4007 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4008 | } | |
d9aba805 ILT |
4009 | else if (mips_pic == EMBEDDED_PIC) |
4010 | { | |
4011 | /* For embedded PIC we pick up the entire address off $gp in | |
4012 | a single instruction. */ | |
4013 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4014 | mips_isa < 3 ? "addiu" : "daddiu", | |
4015 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4016 | offset_expr.X_op = O_constant; | |
4017 | offset_expr.X_add_number = 0; | |
4018 | } | |
4019 | else | |
4020 | abort (); | |
4021 | ||
0dd2d296 | 4022 | /* Now we load the register(s). */ |
8358c818 | 4023 | if (mips_isa >= 3) |
0dd2d296 ILT |
4024 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
4025 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
4026 | else |
4027 | { | |
0dd2d296 ILT |
4028 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
4029 | treg, (int) BFD_RELOC_LO16, AT); | |
4030 | if (treg != 31) | |
4031 | { | |
4032 | /* FIXME: How in the world do we deal with the possible | |
4033 | overflow here? */ | |
4034 | offset_expr.X_add_number += 4; | |
4035 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
4036 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
4037 | } | |
8358c818 | 4038 | } |
d2c71068 ILT |
4039 | |
4040 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
4041 | does not become a variant frag. */ | |
4042 | frag_wane (frag_now); | |
4043 | frag_new (0); | |
4044 | ||
670a50eb | 4045 | break; |
3d3c5039 ILT |
4046 | |
4047 | case M_LI_DD: | |
55933a58 ILT |
4048 | assert (offset_expr.X_op == O_symbol |
4049 | && offset_expr.X_add_number == 0); | |
4050 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
4051 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 4052 | { |
0dd2d296 ILT |
4053 | if (mips_isa >= 2) |
4054 | { | |
4055 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
4056 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
4057 | return; | |
4058 | } | |
4059 | breg = GP; | |
4060 | r = BFD_RELOC_MIPS_LITERAL; | |
4061 | goto dob; | |
4062 | } | |
55933a58 | 4063 | else |
0dd2d296 | 4064 | { |
55933a58 ILT |
4065 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
4066 | if (mips_pic == SVR4_PIC) | |
4067 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4068 | mips_isa < 3 ? "lw" : "ld", | |
4069 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4070 | else | |
4071 | { | |
4072 | /* FIXME: This won't work for a 64 bit address. */ | |
4073 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4074 | } | |
4075 | ||
0dd2d296 ILT |
4076 | if (mips_isa >= 2) |
4077 | { | |
4078 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 4079 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
94b68f04 ILT |
4080 | |
4081 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
4082 | that this does not become a variant frag. */ | |
4083 | frag_wane (frag_now); | |
4084 | frag_new (0); | |
4085 | ||
0dd2d296 ILT |
4086 | break; |
4087 | } | |
4088 | breg = AT; | |
4089 | r = BFD_RELOC_LO16; | |
4090 | goto dob; | |
8358c818 | 4091 | } |
9226253a | 4092 | |
3d3c5039 | 4093 | case M_L_DOB: |
9a7d824a ILT |
4094 | /* Even on a big endian machine $fn comes before $fn+1. We have |
4095 | to adjust when loading from memory. */ | |
9226253a ILT |
4096 | r = BFD_RELOC_LO16; |
4097 | dob: | |
8358c818 | 4098 | assert (mips_isa < 2); |
0dd2d296 | 4099 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
9a7d824a | 4100 | byte_order == LITTLE_ENDIAN ? treg : treg + 1, |
9226253a | 4101 | (int) r, breg); |
0dd2d296 ILT |
4102 | /* FIXME: A possible overflow which I don't know how to deal |
4103 | with. */ | |
670a50eb | 4104 | offset_expr.X_add_number += 4; |
0dd2d296 | 4105 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
9a7d824a | 4106 | byte_order == LITTLE_ENDIAN ? treg + 1 : treg, |
9226253a | 4107 | (int) r, breg); |
d2c71068 ILT |
4108 | |
4109 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
4110 | does not become a variant frag. */ | |
4111 | frag_wane (frag_now); | |
4112 | frag_new (0); | |
4113 | ||
0dd2d296 ILT |
4114 | if (breg != AT) |
4115 | return; | |
4116 | break; | |
3d3c5039 ILT |
4117 | |
4118 | case M_L_DAB: | |
670a50eb ILT |
4119 | /* |
4120 | * The MIPS assembler seems to check for X_add_number not | |
4121 | * being double aligned and generating: | |
4122 | * lui at,%hi(foo+1) | |
4123 | * addu at,at,v1 | |
4124 | * addiu at,at,%lo(foo+1) | |
4125 | * lwc1 f2,0(at) | |
4126 | * lwc1 f3,4(at) | |
4127 | * But, the resulting address is the same after relocation so why | |
4128 | * generate the extra instruction? | |
4129 | */ | |
4032d3f0 | 4130 | coproc = 1; |
0dd2d296 | 4131 | if (mips_isa >= 2) |
670a50eb | 4132 | { |
0dd2d296 ILT |
4133 | s = "ldc1"; |
4134 | goto ld; | |
670a50eb | 4135 | } |
0dd2d296 ILT |
4136 | |
4137 | s = "lwc1"; | |
4138 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
4139 | goto ldd_std; |
4140 | ||
4141 | case M_S_DAB: | |
8358c818 | 4142 | if (mips_isa >= 2) |
8358c818 | 4143 | { |
0dd2d296 ILT |
4144 | s = "sdc1"; |
4145 | goto st; | |
8358c818 | 4146 | } |
3d3c5039 | 4147 | |
0dd2d296 ILT |
4148 | s = "swc1"; |
4149 | fmt = "T,o(b)"; | |
4150 | coproc = 1; | |
4151 | goto ldd_std; | |
3d3c5039 ILT |
4152 | |
4153 | case M_LD_AB: | |
0dd2d296 | 4154 | if (mips_isa >= 3) |
670a50eb | 4155 | { |
0dd2d296 ILT |
4156 | s = "ld"; |
4157 | goto ld; | |
670a50eb | 4158 | } |
0dd2d296 ILT |
4159 | |
4160 | s = "lw"; | |
4161 | fmt = "t,o(b)"; | |
4162 | goto ldd_std; | |
4163 | ||
4164 | case M_SD_AB: | |
4165 | if (mips_isa >= 3) | |
670a50eb | 4166 | { |
0dd2d296 ILT |
4167 | s = "sd"; |
4168 | goto st; | |
670a50eb | 4169 | } |
0dd2d296 | 4170 | |
670a50eb | 4171 | s = "sw"; |
0dd2d296 ILT |
4172 | fmt = "t,o(b)"; |
4173 | ||
4174 | ldd_std: | |
4175 | if (offset_expr.X_op != O_symbol | |
4176 | && offset_expr.X_op != O_constant) | |
670a50eb | 4177 | { |
0dd2d296 ILT |
4178 | as_bad ("expression too complex"); |
4179 | offset_expr.X_op = O_constant; | |
4180 | } | |
4181 | ||
4182 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
4183 | to adjust when loading from memory. We set coproc if we must | |
4184 | load $fn+1 first. */ | |
4185 | if (byte_order == LITTLE_ENDIAN) | |
4186 | coproc = 0; | |
4187 | ||
d9aba805 | 4188 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
4189 | || offset_expr.X_op == O_constant) |
4190 | { | |
4191 | /* If this is a reference to a GP relative symbol, we want | |
4192 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4193 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
4194 | If we have a base register, we use this | |
4195 | addu $at,$breg,$gp | |
4196 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
4197 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
4198 | If this is not a GP relative symbol, we want | |
4199 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4200 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
4201 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
4202 | If there is a base register, we add it to $at after the | |
4203 | lui instruction. If there is a constant, we always use | |
4204 | the last case. */ | |
7a15a226 | 4205 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4206 | || nopic_need_relax (offset_expr.X_add_symbol)) |
670a50eb | 4207 | { |
0dd2d296 ILT |
4208 | p = NULL; |
4209 | used_at = 1; | |
670a50eb ILT |
4210 | } |
4211 | else | |
0dd2d296 ILT |
4212 | { |
4213 | int off; | |
4214 | ||
4215 | if (breg == 0) | |
4216 | { | |
8ea7f4e8 | 4217 | frag_grow (28); |
0dd2d296 ILT |
4218 | tempreg = GP; |
4219 | off = 0; | |
4220 | used_at = 0; | |
4221 | } | |
4222 | else | |
4223 | { | |
8ea7f4e8 | 4224 | frag_grow (36); |
0dd2d296 ILT |
4225 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4226 | mips_isa < 3 ? "addu" : "daddu", | |
4227 | "d,v,t", AT, breg, GP); | |
4228 | tempreg = AT; | |
4229 | off = 4; | |
4230 | used_at = 1; | |
4231 | } | |
4232 | ||
4233 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4234 | coproc ? treg + 1 : treg, | |
4235 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4236 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
4237 | |
4238 | /* Set mips_optimize to 2 to avoid inserting an | |
4239 | undesired nop. */ | |
4240 | hold_mips_optimize = mips_optimize; | |
4241 | mips_optimize = 2; | |
0dd2d296 ILT |
4242 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4243 | coproc ? treg : treg + 1, | |
4244 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
4245 | mips_optimize = hold_mips_optimize; |
4246 | ||
0dd2d296 ILT |
4247 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
4248 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
8197b589 | 4249 | used_at && mips_noat), |
0dd2d296 ILT |
4250 | offset_expr.X_add_symbol, (long) 0, |
4251 | (char *) NULL); | |
777ad64d ILT |
4252 | |
4253 | /* We just generated two relocs. When tc_gen_reloc | |
4254 | handles this case, it will skip the first reloc and | |
4255 | handle the second. The second reloc already has an | |
4256 | extra addend of 4, which we added above. We must | |
4257 | subtract it out, and then subtract another 4 to make | |
4258 | the first reloc come out right. The second reloc | |
4259 | will come out right because we are going to add 4 to | |
4260 | offset_expr when we build its instruction below. */ | |
4261 | offset_expr.X_add_number -= 8; | |
0dd2d296 ILT |
4262 | offset_expr.X_op = O_constant; |
4263 | } | |
4264 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
4265 | if (p != NULL) | |
4266 | p += 4; | |
4267 | if (breg != 0) | |
4268 | { | |
4269 | macro_build (p, &icnt, (expressionS *) NULL, | |
4270 | mips_isa < 3 ? "addu" : "daddu", | |
4271 | "d,v,t", AT, breg, AT); | |
4272 | if (p != NULL) | |
4273 | p += 4; | |
4274 | } | |
4275 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
4276 | coproc ? treg + 1 : treg, | |
4277 | (int) BFD_RELOC_LO16, AT); | |
4278 | if (p != NULL) | |
4279 | p += 4; | |
4280 | /* FIXME: How do we handle overflow here? */ | |
4281 | offset_expr.X_add_number += 4; | |
4282 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
4283 | coproc ? treg : treg + 1, | |
4284 | (int) BFD_RELOC_LO16, AT); | |
4285 | } | |
fb251650 | 4286 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 4287 | { |
0dd2d296 ILT |
4288 | int off; |
4289 | ||
4290 | /* If this is a reference to an external symbol, we want | |
4291 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4292 | nop | |
4293 | <op> $treg,0($at) | |
4294 | <op> $treg+1,4($at) | |
4295 | Otherwise we want | |
4296 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4297 | nop | |
4298 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
4299 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
4300 | If there is a base register we add it to $at before the | |
4301 | lwc1 instructions. If there is a constant we include it | |
4302 | in the lwc1 instructions. */ | |
4303 | used_at = 1; | |
4304 | expr1.X_add_number = offset_expr.X_add_number; | |
4305 | offset_expr.X_add_number = 0; | |
4306 | if (expr1.X_add_number < -0x8000 | |
4307 | || expr1.X_add_number >= 0x8000 - 4) | |
4308 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4309 | if (breg == 0) | |
4310 | off = 0; | |
4311 | else | |
4312 | off = 4; | |
8ea7f4e8 | 4313 | frag_grow (24 + off); |
0dd2d296 ILT |
4314 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4315 | mips_isa < 3 ? "lw" : "ld", | |
4316 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4317 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 4318 | if (breg != 0) |
0dd2d296 | 4319 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c | 4320 | mips_isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
4321 | "d,v,t", AT, breg, AT); |
4322 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
4323 | coproc ? treg + 1 : treg, | |
4324 | (int) BFD_RELOC_LO16, AT); | |
4325 | expr1.X_add_number += 4; | |
55933a58 ILT |
4326 | |
4327 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
4328 | nop. */ | |
4329 | hold_mips_optimize = mips_optimize; | |
4330 | mips_optimize = 2; | |
0dd2d296 ILT |
4331 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
4332 | coproc ? treg : treg + 1, | |
4333 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
4334 | mips_optimize = hold_mips_optimize; |
4335 | ||
0dd2d296 ILT |
4336 | (void) frag_var (rs_machine_dependent, 0, 0, |
4337 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
4338 | offset_expr.X_add_symbol, (long) 0, | |
4339 | (char *) NULL); | |
8358c818 | 4340 | } |
fb251650 ILT |
4341 | else if (mips_pic == SVR4_PIC) |
4342 | { | |
4343 | int gpdel, off; | |
4344 | ||
4345 | /* If this is a reference to an external symbol, we want | |
4346 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4347 | addu $at,$at,$gp | |
4348 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
4349 | nop | |
4350 | <op> $treg,0($at) | |
4351 | <op> $treg+1,4($at) | |
4352 | Otherwise we want | |
4353 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4354 | nop | |
4355 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
4356 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
4357 | If there is a base register we add it to $at before the | |
4358 | lwc1 instructions. If there is a constant we include it | |
4359 | in the lwc1 instructions. */ | |
4360 | used_at = 1; | |
4361 | expr1.X_add_number = offset_expr.X_add_number; | |
4362 | offset_expr.X_add_number = 0; | |
4363 | if (expr1.X_add_number < -0x8000 | |
4364 | || expr1.X_add_number >= 0x8000 - 4) | |
4365 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4366 | if (reg_needs_delay (GP)) | |
4367 | gpdel = 4; | |
4368 | else | |
4369 | gpdel = 0; | |
4370 | if (breg == 0) | |
4371 | off = 0; | |
4372 | else | |
4373 | off = 4; | |
4374 | frag_grow (56); | |
4375 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4376 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4377 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4378 | mips_isa < 3 ? "addu" : "daddu", | |
4379 | "d,v,t", AT, AT, GP); | |
4380 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4381 | mips_isa < 3 ? "lw" : "ld", | |
4382 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); | |
4383 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
4384 | if (breg != 0) | |
4385 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4386 | mips_isa < 3 ? "addu" : "daddu", | |
4387 | "d,v,t", AT, breg, AT); | |
4388 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
4389 | coproc ? treg + 1 : treg, | |
4390 | (int) BFD_RELOC_LO16, AT); | |
4391 | expr1.X_add_number += 4; | |
4392 | ||
4393 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
4394 | nop. */ | |
4395 | hold_mips_optimize = mips_optimize; | |
4396 | mips_optimize = 2; | |
4397 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
4398 | coproc ? treg : treg + 1, | |
4399 | (int) BFD_RELOC_LO16, AT); | |
4400 | mips_optimize = hold_mips_optimize; | |
4401 | expr1.X_add_number -= 4; | |
4402 | ||
4403 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
4404 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
4405 | 8 + gpdel + off, 1, 0), | |
4406 | offset_expr.X_add_symbol, (long) 0, | |
4407 | (char *) NULL); | |
4408 | if (gpdel > 0) | |
4409 | { | |
4410 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4411 | p += 4; | |
4412 | } | |
4413 | macro_build (p, &icnt, &offset_expr, | |
4414 | mips_isa < 3 ? "lw" : "ld", | |
4415 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4416 | p += 4; | |
4417 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4418 | p += 4; | |
4419 | if (breg != 0) | |
4420 | { | |
4421 | macro_build (p, &icnt, (expressionS *) NULL, | |
4422 | mips_isa < 3 ? "addu" : "daddu", | |
4423 | "d,v,t", AT, breg, AT); | |
4424 | p += 4; | |
4425 | } | |
4426 | macro_build (p, &icnt, &expr1, s, fmt, | |
4427 | coproc ? treg + 1 : treg, | |
4428 | (int) BFD_RELOC_LO16, AT); | |
4429 | p += 4; | |
4430 | expr1.X_add_number += 4; | |
4431 | ||
4432 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
4433 | nop. */ | |
4434 | hold_mips_optimize = mips_optimize; | |
4435 | mips_optimize = 2; | |
4436 | macro_build (p, &icnt, &expr1, s, fmt, | |
4437 | coproc ? treg : treg + 1, | |
4438 | (int) BFD_RELOC_LO16, AT); | |
4439 | mips_optimize = hold_mips_optimize; | |
4440 | } | |
d9aba805 ILT |
4441 | else if (mips_pic == EMBEDDED_PIC) |
4442 | { | |
4443 | /* If there is no base register, we use | |
4444 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4445 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
4446 | If we have a base register, we use | |
4447 | addu $at,$breg,$gp | |
4448 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
4449 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
4450 | */ | |
4451 | if (breg == 0) | |
4452 | { | |
4453 | tempreg = GP; | |
4454 | used_at = 0; | |
4455 | } | |
4456 | else | |
4457 | { | |
4458 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4459 | mips_isa < 3 ? "addu" : "daddu", | |
4460 | "d,v,t", AT, breg, GP); | |
4461 | tempreg = AT; | |
4462 | used_at = 1; | |
4463 | } | |
4464 | ||
4465 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4466 | coproc ? treg + 1 : treg, | |
4467 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4468 | offset_expr.X_add_number += 4; | |
4469 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4470 | coproc ? treg : treg + 1, | |
4471 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4472 | } | |
4473 | else | |
4474 | abort (); | |
0dd2d296 ILT |
4475 | |
4476 | if (! used_at) | |
4477 | return; | |
4478 | ||
4479 | break; | |
4480 | ||
4481 | case M_LD_OB: | |
4482 | s = "lw"; | |
4483 | goto sd_ob; | |
4484 | case M_SD_OB: | |
4485 | s = "sw"; | |
4486 | sd_ob: | |
4487 | assert (mips_isa < 3); | |
4488 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
4489 | (int) BFD_RELOC_LO16, breg); | |
4490 | offset_expr.X_add_number += 4; | |
4491 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
4492 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 4493 | return; |
917fae09 SS |
4494 | #ifdef LOSING_COMPILER |
4495 | default: | |
4496 | macro2 (ip); | |
4497 | return; | |
4498 | } | |
4499 | if (mips_noat) | |
4500 | as_warn ("Macro used $at after \".set noat\""); | |
4501 | } | |
4502 | ||
4503 | static void | |
4504 | macro2 (ip) | |
4505 | struct mips_cl_insn *ip; | |
4506 | { | |
4507 | register int treg, sreg, dreg, breg; | |
4508 | int tempreg; | |
4509 | int mask; | |
4510 | int icnt = 0; | |
4511 | int used_at; | |
4512 | expressionS expr1; | |
4513 | const char *s; | |
4514 | const char *s2; | |
4515 | const char *fmt; | |
4516 | int likely = 0; | |
4517 | int dbl = 0; | |
4518 | int coproc = 0; | |
adcf2b9d ILT |
4519 | int lr = 0; |
4520 | int off; | |
917fae09 SS |
4521 | offsetT maxnum; |
4522 | bfd_reloc_code_real_type r; | |
4523 | char *p; | |
4524 | ||
4525 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4526 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4527 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4528 | mask = ip->insn_mo->mask; | |
4529 | ||
4530 | expr1.X_op = O_constant; | |
4531 | expr1.X_op_symbol = NULL; | |
4532 | expr1.X_add_symbol = NULL; | |
4533 | expr1.X_add_number = 1; | |
4534 | ||
4535 | switch (mask) | |
4536 | { | |
4537 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 4538 | |
8358c818 ILT |
4539 | case M_DMUL: |
4540 | dbl = 1; | |
3d3c5039 | 4541 | case M_MUL: |
0dd2d296 | 4542 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
4543 | dbl ? "dmultu" : "multu", |
4544 | "s,t", sreg, treg); | |
0dd2d296 | 4545 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 4546 | return; |
3d3c5039 | 4547 | |
8358c818 ILT |
4548 | case M_DMUL_I: |
4549 | dbl = 1; | |
3d3c5039 | 4550 | case M_MUL_I: |
8358c818 ILT |
4551 | /* The MIPS assembler some times generates shifts and adds. I'm |
4552 | not trying to be that fancy. GCC should do this for us | |
4553 | anyway. */ | |
d8a1c247 | 4554 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 4555 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
4556 | dbl ? "dmult" : "mult", |
4557 | "s,t", sreg, AT); | |
0dd2d296 | 4558 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 4559 | break; |
3d3c5039 | 4560 | |
8358c818 ILT |
4561 | case M_DMULO: |
4562 | dbl = 1; | |
4563 | case M_MULO: | |
4564 | mips_emit_delays (); | |
4565 | ++mips_noreorder; | |
0dd2d296 ILT |
4566 | mips_any_noreorder = 1; |
4567 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
4568 | dbl ? "dmult" : "mult", |
4569 | "s,t", sreg, treg); | |
0dd2d296 ILT |
4570 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
4571 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
4572 | dbl ? "dsra32" : "sra", |
4573 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 4574 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
4575 | if (mips_trap) |
4576 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
4577 | else | |
4578 | { | |
4579 | expr1.X_add_number = 8; | |
4580 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
4581 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
4582 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
4583 | } | |
8358c818 | 4584 | --mips_noreorder; |
0dd2d296 | 4585 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
4586 | break; |
4587 | ||
4588 | case M_DMULOU: | |
4589 | dbl = 1; | |
4590 | case M_MULOU: | |
4591 | mips_emit_delays (); | |
4592 | ++mips_noreorder; | |
0dd2d296 ILT |
4593 | mips_any_noreorder = 1; |
4594 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
4595 | dbl ? "dmultu" : "multu", |
4596 | "s,t", sreg, treg); | |
0dd2d296 ILT |
4597 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
4598 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
4599 | if (mips_trap) |
4600 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
4601 | else | |
4602 | { | |
4603 | expr1.X_add_number = 8; | |
4604 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
4605 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
4606 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
4607 | } | |
8358c818 ILT |
4608 | --mips_noreorder; |
4609 | break; | |
4610 | ||
3d3c5039 | 4611 | case M_ROL: |
0dd2d296 ILT |
4612 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
4613 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
4614 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
4615 | treg); | |
4616 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 4617 | break; |
3d3c5039 ILT |
4618 | |
4619 | case M_ROL_I: | |
0dd2d296 | 4620 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
a40aee38 | 4621 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 4622 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
a40aee38 | 4623 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 4624 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 4625 | break; |
3d3c5039 ILT |
4626 | |
4627 | case M_ROR: | |
0dd2d296 ILT |
4628 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
4629 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
4630 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
4631 | treg); | |
4632 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 4633 | break; |
3d3c5039 ILT |
4634 | |
4635 | case M_ROR_I: | |
0dd2d296 | 4636 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
a40aee38 | 4637 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 4638 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
a40aee38 | 4639 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 4640 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 4641 | break; |
3d3c5039 ILT |
4642 | |
4643 | case M_S_DOB: | |
8358c818 | 4644 | assert (mips_isa < 2); |
9a7d824a ILT |
4645 | /* Even on a big endian machine $fn comes before $fn+1. We have |
4646 | to adjust when storing to memory. */ | |
0dd2d296 | 4647 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
9a7d824a | 4648 | byte_order == LITTLE_ENDIAN ? treg : treg + 1, |
9226253a | 4649 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 4650 | offset_expr.X_add_number += 4; |
0dd2d296 | 4651 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
9a7d824a | 4652 | byte_order == LITTLE_ENDIAN ? treg + 1 : treg, |
9226253a | 4653 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 4654 | return; |
3d3c5039 | 4655 | |
3d3c5039 | 4656 | case M_SEQ: |
670a50eb | 4657 | if (sreg == 0) |
0dd2d296 ILT |
4658 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
4659 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 4660 | else if (treg == 0) |
0dd2d296 ILT |
4661 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
4662 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
4663 | else |
4664 | { | |
0dd2d296 ILT |
4665 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
4666 | sreg, treg); | |
4667 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
4668 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 4669 | } |
670a50eb | 4670 | return; |
3d3c5039 ILT |
4671 | |
4672 | case M_SEQ_I: | |
670a50eb ILT |
4673 | if (imm_expr.X_add_number == 0) |
4674 | { | |
0dd2d296 ILT |
4675 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
4676 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 4677 | return; |
3d3c5039 | 4678 | } |
670a50eb ILT |
4679 | if (sreg == 0) |
4680 | { | |
9a7d824a | 4681 | as_warn ("Instruction %s: result is always false", |
6e8dda9c | 4682 | ip->insn_mo->name); |
0dd2d296 | 4683 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 4684 | return; |
3d3c5039 | 4685 | } |
6e8dda9c | 4686 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 4687 | { |
0dd2d296 ILT |
4688 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
4689 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 4690 | used_at = 0; |
6e8dda9c ILT |
4691 | } |
4692 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
4693 | { | |
4694 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 4695 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 4696 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a ILT |
4697 | "t,r,j", dreg, sreg, |
4698 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
4699 | used_at = 0; |
4700 | } | |
4701 | else | |
4702 | { | |
d8a1c247 | 4703 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
4704 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
4705 | sreg, AT); | |
670a50eb ILT |
4706 | used_at = 1; |
4707 | } | |
0dd2d296 | 4708 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 4709 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
4710 | if (used_at) |
4711 | break; | |
4712 | return; | |
3d3c5039 ILT |
4713 | |
4714 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
4715 | s = "slt"; |
4716 | goto sge; | |
3d3c5039 | 4717 | case M_SGEU: |
670a50eb | 4718 | s = "sltu"; |
3d3c5039 | 4719 | sge: |
0dd2d296 ILT |
4720 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
4721 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 4722 | (int) BFD_RELOC_LO16); |
670a50eb | 4723 | return; |
3d3c5039 | 4724 | |
670a50eb | 4725 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 4726 | case M_SGEU_I: |
6e8dda9c | 4727 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 4728 | { |
0dd2d296 | 4729 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 4730 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 4731 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
4732 | used_at = 0; |
4733 | } | |
4734 | else | |
4735 | { | |
d8a1c247 | 4736 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 4737 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
4738 | mask == M_SGE_I ? "slt" : "sltu", |
4739 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
4740 | used_at = 1; |
4741 | } | |
0dd2d296 | 4742 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 4743 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
4744 | if (used_at) |
4745 | break; | |
4746 | return; | |
3d3c5039 ILT |
4747 | |
4748 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
4749 | s = "slt"; |
4750 | goto sgt; | |
3d3c5039 | 4751 | case M_SGTU: |
670a50eb | 4752 | s = "sltu"; |
3d3c5039 | 4753 | sgt: |
0dd2d296 | 4754 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 4755 | return; |
3d3c5039 | 4756 | |
670a50eb ILT |
4757 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
4758 | s = "slt"; | |
4759 | goto sgti; | |
3d3c5039 | 4760 | case M_SGTU_I: |
670a50eb | 4761 | s = "sltu"; |
3d3c5039 | 4762 | sgti: |
d8a1c247 | 4763 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 4764 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 4765 | break; |
3d3c5039 | 4766 | |
670a50eb ILT |
4767 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
4768 | s = "slt"; | |
4769 | goto sle; | |
3d3c5039 | 4770 | case M_SLEU: |
670a50eb | 4771 | s = "sltu"; |
3d3c5039 | 4772 | sle: |
0dd2d296 ILT |
4773 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
4774 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 4775 | (int) BFD_RELOC_LO16); |
670a50eb | 4776 | return; |
3d3c5039 | 4777 | |
670a50eb ILT |
4778 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
4779 | s = "slt"; | |
4780 | goto slei; | |
3d3c5039 | 4781 | case M_SLEU_I: |
670a50eb | 4782 | s = "sltu"; |
3d3c5039 | 4783 | slei: |
d8a1c247 | 4784 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
4785 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
4786 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 4787 | (int) BFD_RELOC_LO16); |
670a50eb | 4788 | break; |
3d3c5039 ILT |
4789 | |
4790 | case M_SLT_I: | |
6e8dda9c | 4791 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 4792 | { |
0dd2d296 ILT |
4793 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
4794 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 4795 | return; |
3d3c5039 | 4796 | } |
d8a1c247 | 4797 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 4798 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 4799 | break; |
3d3c5039 ILT |
4800 | |
4801 | case M_SLTU_I: | |
6e8dda9c | 4802 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 4803 | { |
0dd2d296 ILT |
4804 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
4805 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 4806 | return; |
3d3c5039 | 4807 | } |
d8a1c247 | 4808 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
4809 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
4810 | AT); | |
670a50eb | 4811 | break; |
3d3c5039 ILT |
4812 | |
4813 | case M_SNE: | |
670a50eb | 4814 | if (sreg == 0) |
0dd2d296 ILT |
4815 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
4816 | treg); | |
670a50eb | 4817 | else if (treg == 0) |
0dd2d296 ILT |
4818 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
4819 | sreg); | |
670a50eb ILT |
4820 | else |
4821 | { | |
0dd2d296 ILT |
4822 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
4823 | sreg, treg); | |
4824 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
4825 | dreg); | |
3d3c5039 | 4826 | } |
670a50eb | 4827 | return; |
3d3c5039 ILT |
4828 | |
4829 | case M_SNE_I: | |
670a50eb ILT |
4830 | if (imm_expr.X_add_number == 0) |
4831 | { | |
0dd2d296 ILT |
4832 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
4833 | sreg); | |
670a50eb | 4834 | return; |
3d3c5039 | 4835 | } |
670a50eb ILT |
4836 | if (sreg == 0) |
4837 | { | |
9a7d824a | 4838 | as_warn ("Instruction %s: result is always true", |
6e8dda9c | 4839 | ip->insn_mo->name); |
0dd2d296 | 4840 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 4841 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 4842 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 4843 | return; |
3d3c5039 | 4844 | } |
6e8dda9c | 4845 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 4846 | { |
0dd2d296 ILT |
4847 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
4848 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 4849 | used_at = 0; |
6e8dda9c ILT |
4850 | } |
4851 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
4852 | { | |
4853 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 4854 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 4855 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 4856 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
4857 | used_at = 0; |
4858 | } | |
4859 | else | |
4860 | { | |
d8a1c247 | 4861 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
4862 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
4863 | sreg, AT); | |
670a50eb ILT |
4864 | used_at = 1; |
4865 | } | |
0dd2d296 | 4866 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
4867 | if (used_at) |
4868 | break; | |
4869 | return; | |
3d3c5039 | 4870 | |
8358c818 ILT |
4871 | case M_DSUB_I: |
4872 | dbl = 1; | |
3d3c5039 | 4873 | case M_SUB_I: |
6e8dda9c | 4874 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
4875 | { |
4876 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 4877 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 4878 | dbl ? "daddi" : "addi", |
9226253a | 4879 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 4880 | return; |
3d3c5039 | 4881 | } |
d8a1c247 | 4882 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 4883 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
4884 | dbl ? "dsub" : "sub", |
4885 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 4886 | break; |
3d3c5039 | 4887 | |
8358c818 ILT |
4888 | case M_DSUBU_I: |
4889 | dbl = 1; | |
3d3c5039 | 4890 | case M_SUBU_I: |
6e8dda9c | 4891 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
4892 | { |
4893 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 4894 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 4895 | dbl ? "daddiu" : "addiu", |
9226253a | 4896 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 4897 | return; |
3d3c5039 | 4898 | } |
d8a1c247 | 4899 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 4900 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
4901 | dbl ? "dsubu" : "subu", |
4902 | "d,v,t", dreg, sreg, AT); | |
4903 | break; | |
4904 | ||
4905 | case M_TEQ_I: | |
4906 | s = "teq"; | |
4907 | goto trap; | |
4908 | case M_TGE_I: | |
4909 | s = "tge"; | |
4910 | goto trap; | |
4911 | case M_TGEU_I: | |
4912 | s = "tgeu"; | |
4913 | goto trap; | |
4914 | case M_TLT_I: | |
4915 | s = "tlt"; | |
4916 | goto trap; | |
4917 | case M_TLTU_I: | |
4918 | s = "tltu"; | |
4919 | goto trap; | |
4920 | case M_TNE_I: | |
4921 | s = "tne"; | |
4922 | trap: | |
d8a1c247 | 4923 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 4924 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 4925 | break; |
3d3c5039 ILT |
4926 | |
4927 | case M_TRUNCWD: | |
4928 | case M_TRUNCWS: | |
8358c818 | 4929 | assert (mips_isa < 2); |
670a50eb ILT |
4930 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
4931 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
4932 | ||
4933 | /* | |
4934 | * Is the double cfc1 instruction a bug in the mips assembler; | |
4935 | * or is there a reason for it? | |
4936 | */ | |
becfe05e ILT |
4937 | mips_emit_delays (); |
4938 | ++mips_noreorder; | |
0dd2d296 ILT |
4939 | mips_any_noreorder = 1; |
4940 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
4941 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
4942 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 4943 | expr1.X_add_number = 3; |
0dd2d296 | 4944 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 4945 | (int) BFD_RELOC_LO16); |
670a50eb | 4946 | expr1.X_add_number = 2; |
0dd2d296 | 4947 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 4948 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
4949 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
4950 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
4951 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 4952 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
4953 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
4954 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
becfe05e | 4955 | --mips_noreorder; |
670a50eb | 4956 | break; |
3d3c5039 ILT |
4957 | |
4958 | case M_ULH: | |
670a50eb ILT |
4959 | s = "lb"; |
4960 | goto ulh; | |
3d3c5039 | 4961 | case M_ULHU: |
670a50eb | 4962 | s = "lbu"; |
3d3c5039 | 4963 | ulh: |
8ea7f4e8 ILT |
4964 | if (offset_expr.X_add_number >= 0x7fff) |
4965 | as_bad ("operand overflow"); | |
670a50eb | 4966 | /* avoid load delay */ |
8ea7f4e8 ILT |
4967 | if (byte_order == LITTLE_ENDIAN) |
4968 | offset_expr.X_add_number += 1; | |
0dd2d296 | 4969 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 4970 | (int) BFD_RELOC_LO16, breg); |
8ea7f4e8 ILT |
4971 | if (byte_order == LITTLE_ENDIAN) |
4972 | offset_expr.X_add_number -= 1; | |
4973 | else | |
4974 | offset_expr.X_add_number += 1; | |
0dd2d296 | 4975 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 4976 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
4977 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
4978 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 4979 | break; |
3d3c5039 | 4980 | |
adcf2b9d ILT |
4981 | case M_ULD: |
4982 | s = "ldl"; | |
4983 | s2 = "ldr"; | |
4984 | off = 7; | |
4985 | goto ulw; | |
3d3c5039 | 4986 | case M_ULW: |
adcf2b9d ILT |
4987 | s = "lwl"; |
4988 | s2 = "lwr"; | |
4989 | off = 3; | |
4990 | ulw: | |
4991 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 ILT |
4992 | as_bad ("operand overflow"); |
4993 | if (byte_order == LITTLE_ENDIAN) | |
adcf2b9d ILT |
4994 | offset_expr.X_add_number += off; |
4995 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 4996 | (int) BFD_RELOC_LO16, breg); |
8ea7f4e8 | 4997 | if (byte_order == LITTLE_ENDIAN) |
adcf2b9d | 4998 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 4999 | else |
adcf2b9d ILT |
5000 | offset_expr.X_add_number += off; |
5001 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 5002 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5003 | return; |
3d3c5039 | 5004 | |
adcf2b9d ILT |
5005 | case M_ULD_A: |
5006 | s = "ldl"; | |
5007 | s2 = "ldr"; | |
5008 | off = 7; | |
5009 | goto ulwa; | |
5010 | case M_ULW_A: | |
5011 | s = "lwl"; | |
5012 | s2 = "lwr"; | |
5013 | off = 3; | |
5014 | ulwa: | |
5015 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
5016 | if (breg != 0) |
5017 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5018 | mips_isa < 3 ? "addu" : "daddu", | |
5019 | "d,v,t", AT, AT, breg); | |
adcf2b9d ILT |
5020 | if (byte_order == LITTLE_ENDIAN) |
5021 | expr1.X_add_number = off; | |
5022 | else | |
5023 | expr1.X_add_number = 0; | |
5024 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
5025 | (int) BFD_RELOC_LO16, AT); | |
5026 | if (byte_order == LITTLE_ENDIAN) | |
5027 | expr1.X_add_number = 0; | |
5028 | else | |
5029 | expr1.X_add_number = off; | |
5030 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
5031 | (int) BFD_RELOC_LO16, AT); | |
5032 | break; | |
5033 | ||
3d3c5039 ILT |
5034 | case M_ULH_A: |
5035 | case M_ULHU_A: | |
0dd2d296 | 5036 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
5037 | if (breg != 0) |
5038 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5039 | mips_isa < 3 ? "addu" : "daddu", | |
5040 | "d,v,t", AT, AT, breg); | |
adcf2b9d ILT |
5041 | if (byte_order == BIG_ENDIAN) |
5042 | expr1.X_add_number = 0; | |
5043 | macro_build ((char *) NULL, &icnt, &expr1, | |
5044 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
5045 | (int) BFD_RELOC_LO16, AT); | |
5046 | if (byte_order == BIG_ENDIAN) | |
5047 | expr1.X_add_number = 1; | |
670a50eb | 5048 | else |
adcf2b9d ILT |
5049 | expr1.X_add_number = 0; |
5050 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
5051 | (int) BFD_RELOC_LO16, AT); | |
5052 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
5053 | treg, 8); | |
5054 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
5055 | treg, AT); | |
670a50eb | 5056 | break; |
3d3c5039 ILT |
5057 | |
5058 | case M_USH: | |
8ea7f4e8 ILT |
5059 | if (offset_expr.X_add_number >= 0x7fff) |
5060 | as_bad ("operand overflow"); | |
5061 | if (byte_order == BIG_ENDIAN) | |
5062 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5063 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 5064 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 5065 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
8ea7f4e8 ILT |
5066 | if (byte_order == BIG_ENDIAN) |
5067 | offset_expr.X_add_number -= 1; | |
5068 | else | |
5069 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5070 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 5071 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5072 | break; |
3d3c5039 | 5073 | |
adcf2b9d ILT |
5074 | case M_USD: |
5075 | s = "sdl"; | |
5076 | s2 = "sdr"; | |
5077 | off = 7; | |
5078 | goto usw; | |
3d3c5039 | 5079 | case M_USW: |
adcf2b9d ILT |
5080 | s = "swl"; |
5081 | s2 = "swr"; | |
5082 | off = 3; | |
5083 | usw: | |
5084 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 ILT |
5085 | as_bad ("operand overflow"); |
5086 | if (byte_order == LITTLE_ENDIAN) | |
adcf2b9d ILT |
5087 | offset_expr.X_add_number += off; |
5088 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 5089 | (int) BFD_RELOC_LO16, breg); |
8ea7f4e8 | 5090 | if (byte_order == LITTLE_ENDIAN) |
adcf2b9d | 5091 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 5092 | else |
adcf2b9d ILT |
5093 | offset_expr.X_add_number += off; |
5094 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 5095 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5096 | return; |
3d3c5039 | 5097 | |
adcf2b9d ILT |
5098 | case M_USD_A: |
5099 | s = "sdl"; | |
5100 | s2 = "sdr"; | |
5101 | off = 7; | |
5102 | goto uswa; | |
3d3c5039 | 5103 | case M_USW_A: |
adcf2b9d ILT |
5104 | s = "swl"; |
5105 | s2 = "swr"; | |
5106 | off = 3; | |
5107 | uswa: | |
0dd2d296 | 5108 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
5109 | if (breg != 0) |
5110 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5111 | mips_isa < 3 ? "addu" : "daddu", | |
5112 | "d,v,t", AT, AT, breg); | |
adcf2b9d ILT |
5113 | if (byte_order == LITTLE_ENDIAN) |
5114 | expr1.X_add_number = off; | |
670a50eb | 5115 | else |
adcf2b9d ILT |
5116 | expr1.X_add_number = 0; |
5117 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
5118 | (int) BFD_RELOC_LO16, AT); | |
5119 | if (byte_order == LITTLE_ENDIAN) | |
5120 | expr1.X_add_number = 0; | |
5121 | else | |
5122 | expr1.X_add_number = off; | |
5123 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
5124 | (int) BFD_RELOC_LO16, AT); | |
5125 | break; | |
5126 | ||
5127 | case M_USH_A: | |
5128 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
5129 | if (breg != 0) |
5130 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5131 | mips_isa < 3 ? "addu" : "daddu", | |
5132 | "d,v,t", AT, AT, breg); | |
adcf2b9d ILT |
5133 | if (byte_order == LITTLE_ENDIAN) |
5134 | expr1.X_add_number = 0; | |
5135 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
5136 | (int) BFD_RELOC_LO16, AT); | |
5137 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
5138 | treg, 8); | |
5139 | if (byte_order == LITTLE_ENDIAN) | |
5140 | expr1.X_add_number = 1; | |
5141 | else | |
5142 | expr1.X_add_number = 0; | |
5143 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
5144 | (int) BFD_RELOC_LO16, AT); | |
5145 | if (byte_order == LITTLE_ENDIAN) | |
5146 | expr1.X_add_number = 0; | |
5147 | else | |
5148 | expr1.X_add_number = 1; | |
5149 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
5150 | (int) BFD_RELOC_LO16, AT); | |
5151 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
5152 | treg, 8); | |
5153 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
5154 | treg, AT); | |
670a50eb | 5155 | break; |
3d3c5039 ILT |
5156 | |
5157 | default: | |
670a50eb | 5158 | as_bad ("Macro %s not implemented yet", ip->insn_mo->name); |
8358c818 | 5159 | break; |
3d3c5039 | 5160 | } |
670a50eb ILT |
5161 | if (mips_noat) |
5162 | as_warn ("Macro used $at after \".set noat\""); | |
3d3c5039 ILT |
5163 | } |
5164 | ||
867a58b3 ILT |
5165 | /* This routine assembles an instruction into its binary format. As a |
5166 | side effect, it sets one of the global variables imm_reloc or | |
5167 | offset_reloc to the type of relocation to do if one of the operands | |
5168 | is an address expression. */ | |
3d3c5039 | 5169 | |
3d3c5039 ILT |
5170 | static void |
5171 | mips_ip (str, ip) | |
5172 | char *str; | |
5173 | struct mips_cl_insn *ip; | |
5174 | { | |
670a50eb ILT |
5175 | char *s; |
5176 | const char *args; | |
5177 | char c; | |
5178 | struct mips_opcode *insn; | |
5179 | char *argsStart; | |
5180 | unsigned int regno; | |
5181 | unsigned int lastregno = 0; | |
5182 | char *s_reset; | |
5183 | ||
5184 | insn_error = NULL; | |
5185 | ||
c625fc23 | 5186 | for (s = str; islower (*s) || (*s >= '0' && *s <= '3') || *s == '6' || *s == '.'; ++s) |
670a50eb ILT |
5187 | continue; |
5188 | switch (*s) | |
5189 | { | |
3d3c5039 | 5190 | case '\0': |
670a50eb | 5191 | break; |
3d3c5039 ILT |
5192 | |
5193 | case ' ': | |
670a50eb ILT |
5194 | *s++ = '\0'; |
5195 | break; | |
3d3c5039 ILT |
5196 | |
5197 | default: | |
460531da | 5198 | as_fatal ("Unknown opcode: `%s'", str); |
3d3c5039 | 5199 | } |
670a50eb ILT |
5200 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) |
5201 | { | |
9753202d | 5202 | insn_error = "unrecognized opcode"; |
670a50eb | 5203 | return; |
3d3c5039 | 5204 | } |
670a50eb ILT |
5205 | argsStart = s; |
5206 | for (;;) | |
5207 | { | |
8358c818 ILT |
5208 | int insn_isa; |
5209 | ||
670a50eb | 5210 | assert (strcmp (insn->name, str) == 0); |
8358c818 ILT |
5211 | |
5212 | if (insn->pinfo == INSN_MACRO) | |
5213 | insn_isa = insn->match; | |
b2b8c24e | 5214 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA2) |
8358c818 | 5215 | insn_isa = 2; |
b2b8c24e | 5216 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA3) |
8358c818 | 5217 | insn_isa = 3; |
d8a1c247 KR |
5218 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA4) |
5219 | insn_isa = 4; | |
8358c818 ILT |
5220 | else |
5221 | insn_isa = 1; | |
5222 | ||
b2b8c24e ILT |
5223 | if (insn_isa > mips_isa |
5224 | || ((insn->pinfo & INSN_ISA) == INSN_4650 | |
e532b44c ILT |
5225 | && ! mips_4650) |
5226 | || ((insn->pinfo & INSN_ISA) == INSN_4010 | |
c625fc23 JSC |
5227 | && ! mips_4010) |
5228 | || ((insn->pinfo & INSN_ISA) == INSN_4100 | |
5229 | && ! mips_4100)) | |
8358c818 ILT |
5230 | { |
5231 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
5232 | && strcmp (insn->name, insn[1].name) == 0) | |
5233 | { | |
5234 | ++insn; | |
5235 | continue; | |
5236 | } | |
517078c1 ILT |
5237 | if (insn_isa <= mips_isa) |
5238 | insn_error = "opcode not supported on this processor"; | |
5239 | else | |
5240 | { | |
5241 | static char buf[100]; | |
5242 | ||
5243 | sprintf (buf, "opcode requires -mips%d or greater", insn_isa); | |
5244 | insn_error = buf; | |
5245 | } | |
9753202d | 5246 | return; |
8358c818 ILT |
5247 | } |
5248 | ||
670a50eb ILT |
5249 | ip->insn_mo = insn; |
5250 | ip->insn_opcode = insn->match; | |
5251 | for (args = insn->args;; ++args) | |
5252 | { | |
5253 | if (*s == ' ') | |
5254 | ++s; | |
5255 | switch (*args) | |
5256 | { | |
5257 | case '\0': /* end of args */ | |
5258 | if (*s == '\0') | |
5259 | return; | |
5260 | break; | |
3d3c5039 ILT |
5261 | |
5262 | case ',': | |
670a50eb ILT |
5263 | if (*s++ == *args) |
5264 | continue; | |
5265 | s--; | |
5266 | switch (*++args) | |
5267 | { | |
3d3c5039 ILT |
5268 | case 'r': |
5269 | case 'v': | |
670a50eb ILT |
5270 | ip->insn_opcode |= lastregno << 21; |
5271 | continue; | |
3d3c5039 ILT |
5272 | |
5273 | case 'w': | |
5274 | case 'W': | |
670a50eb ILT |
5275 | ip->insn_opcode |= lastregno << 16; |
5276 | continue; | |
3d3c5039 ILT |
5277 | |
5278 | case 'V': | |
670a50eb ILT |
5279 | ip->insn_opcode |= lastregno << 11; |
5280 | continue; | |
3d3c5039 | 5281 | } |
670a50eb | 5282 | break; |
3d3c5039 ILT |
5283 | |
5284 | case '(': | |
670a50eb ILT |
5285 | /* handle optional base register. |
5286 | Either the base register is omitted or | |
5287 | we must have a left paren. */ | |
5288 | /* this is dependent on the next operand specifier | |
5289 | is a 'b' for base register */ | |
5290 | assert (args[1] == 'b'); | |
5291 | if (*s == '\0') | |
5292 | return; | |
3d3c5039 | 5293 | |
670a50eb ILT |
5294 | case ')': /* these must match exactly */ |
5295 | if (*s++ == *args) | |
3d3c5039 | 5296 | continue; |
670a50eb ILT |
5297 | break; |
5298 | ||
5299 | case '<': /* must be at least one digit */ | |
5300 | /* | |
5301 | * According to the manual, if the shift amount is greater | |
5302 | * than 31 or less than 0 the the shift amount should be | |
5303 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 5304 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
5305 | */ |
5306 | my_getExpression (&imm_expr, s); | |
5307 | check_absolute_expr (ip, &imm_expr); | |
5308 | if ((unsigned long) imm_expr.X_add_number > 31) | |
5309 | { | |
58d4951d ILT |
5310 | as_warn ("Improper shift amount (%ld)", |
5311 | (long) imm_expr.X_add_number); | |
9226253a | 5312 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
5313 | } |
5314 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 5315 | imm_expr.X_op = O_absent; |
670a50eb ILT |
5316 | s = expr_end; |
5317 | continue; | |
5318 | ||
56c96faa ILT |
5319 | case '>': /* shift amount minus 32 */ |
5320 | my_getExpression (&imm_expr, s); | |
5321 | check_absolute_expr (ip, &imm_expr); | |
5322 | if ((unsigned long) imm_expr.X_add_number < 32 | |
5323 | || (unsigned long) imm_expr.X_add_number > 63) | |
5324 | break; | |
5325 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
5326 | imm_expr.X_op = O_absent; | |
5327 | s = expr_end; | |
5328 | continue; | |
5329 | ||
9226253a | 5330 | case 'k': /* cache code */ |
d8a1c247 | 5331 | case 'h': /* prefx code */ |
9226253a ILT |
5332 | my_getExpression (&imm_expr, s); |
5333 | check_absolute_expr (ip, &imm_expr); | |
5334 | if ((unsigned long) imm_expr.X_add_number > 31) | |
5335 | { | |
d8a1c247 KR |
5336 | as_warn ("Invalid value for `%s' (%lu)", |
5337 | ip->insn_mo->name, | |
9226253a ILT |
5338 | (unsigned long) imm_expr.X_add_number); |
5339 | imm_expr.X_add_number &= 0x1f; | |
5340 | } | |
d8a1c247 KR |
5341 | if (*args == 'k') |
5342 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
5343 | else | |
5344 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
9226253a ILT |
5345 | imm_expr.X_op = O_absent; |
5346 | s = expr_end; | |
5347 | continue; | |
5348 | ||
670a50eb ILT |
5349 | case 'c': /* break code */ |
5350 | my_getExpression (&imm_expr, s); | |
5351 | check_absolute_expr (ip, &imm_expr); | |
5352 | if ((unsigned) imm_expr.X_add_number > 1023) | |
58d4951d ILT |
5353 | as_warn ("Illegal break code (%ld)", |
5354 | (long) imm_expr.X_add_number); | |
670a50eb | 5355 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 5356 | imm_expr.X_op = O_absent; |
670a50eb ILT |
5357 | s = expr_end; |
5358 | continue; | |
5359 | ||
918692a5 ILT |
5360 | case 'B': /* syscall code */ |
5361 | my_getExpression (&imm_expr, s); | |
5362 | check_absolute_expr (ip, &imm_expr); | |
5363 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
58d4951d ILT |
5364 | as_warn ("Illegal syscall code (%ld)", |
5365 | (long) imm_expr.X_add_number); | |
918692a5 | 5366 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 5367 | imm_expr.X_op = O_absent; |
918692a5 ILT |
5368 | s = expr_end; |
5369 | continue; | |
5370 | ||
0aa07269 ILT |
5371 | case 'C': /* Coprocessor code */ |
5372 | my_getExpression (&imm_expr, s); | |
5373 | check_absolute_expr (ip, &imm_expr); | |
5374 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
5375 | { | |
58d4951d ILT |
5376 | as_warn ("Coproccesor code > 25 bits (%ld)", |
5377 | (long) imm_expr.X_add_number); | |
0aa07269 ILT |
5378 | imm_expr.X_add_number &= ((1<<25) - 1); |
5379 | } | |
5380 | ip->insn_opcode |= imm_expr.X_add_number; | |
5381 | imm_expr.X_op = O_absent; | |
5382 | s = expr_end; | |
5383 | continue; | |
5384 | ||
670a50eb ILT |
5385 | case 'b': /* base register */ |
5386 | case 'd': /* destination register */ | |
5387 | case 's': /* source register */ | |
5388 | case 't': /* target register */ | |
5389 | case 'r': /* both target and source */ | |
5390 | case 'v': /* both dest and source */ | |
5391 | case 'w': /* both dest and target */ | |
918692a5 ILT |
5392 | case 'E': /* coprocessor target register */ |
5393 | case 'G': /* coprocessor destination register */ | |
8358c818 | 5394 | case 'x': /* ignore register name */ |
ff3a5c18 | 5395 | case 'z': /* must be zero register */ |
670a50eb ILT |
5396 | s_reset = s; |
5397 | if (s[0] == '$') | |
5398 | { | |
5399 | if (isdigit (s[1])) | |
5400 | { | |
5401 | ++s; | |
5402 | regno = 0; | |
5403 | do | |
5404 | { | |
5405 | regno *= 10; | |
5406 | regno += *s - '0'; | |
5407 | ++s; | |
5408 | } | |
5409 | while (isdigit (*s)); | |
0aa07269 ILT |
5410 | if (regno > 31) |
5411 | as_bad ("Invalid register number (%d)", regno); | |
670a50eb | 5412 | } |
0dd2d296 ILT |
5413 | else if (*args == 'E' || *args == 'G') |
5414 | goto notreg; | |
5415 | else | |
670a50eb | 5416 | { |
0aa07269 ILT |
5417 | if (s[1] == 'f' && s[2] == 'p') |
5418 | { | |
5419 | s += 3; | |
9226253a | 5420 | regno = FP; |
0aa07269 ILT |
5421 | } |
5422 | else if (s[1] == 's' && s[2] == 'p') | |
5423 | { | |
5424 | s += 3; | |
9226253a | 5425 | regno = SP; |
0aa07269 ILT |
5426 | } |
5427 | else if (s[1] == 'g' && s[2] == 'p') | |
5428 | { | |
5429 | s += 3; | |
9226253a | 5430 | regno = GP; |
0aa07269 ILT |
5431 | } |
5432 | else if (s[1] == 'a' && s[2] == 't') | |
5433 | { | |
5434 | s += 3; | |
9226253a | 5435 | regno = AT; |
0aa07269 | 5436 | } |
b2b8c24e ILT |
5437 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
5438 | { | |
5439 | s += 4; | |
5440 | regno = KT0; | |
5441 | } | |
5442 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
5443 | { | |
5444 | s += 4; | |
5445 | regno = KT1; | |
5446 | } | |
0aa07269 ILT |
5447 | else |
5448 | goto notreg; | |
670a50eb | 5449 | } |
9753202d ILT |
5450 | if (regno == AT |
5451 | && ! mips_noat | |
5452 | && *args != 'E' | |
5453 | && *args != 'G') | |
13fe1379 | 5454 | as_warn ("Used $at without \".set noat\""); |
670a50eb ILT |
5455 | c = *args; |
5456 | if (*s == ' ') | |
5457 | s++; | |
5458 | if (args[1] != *s) | |
5459 | { | |
5460 | if (c == 'r' || c == 'v' || c == 'w') | |
5461 | { | |
5462 | regno = lastregno; | |
5463 | s = s_reset; | |
5464 | args++; | |
5465 | } | |
5466 | } | |
ff3a5c18 ILT |
5467 | /* 'z' only matches $0. */ |
5468 | if (c == 'z' && regno != 0) | |
5469 | break; | |
670a50eb ILT |
5470 | switch (c) |
5471 | { | |
3d3c5039 ILT |
5472 | case 'r': |
5473 | case 's': | |
5474 | case 'v': | |
5475 | case 'b': | |
670a50eb ILT |
5476 | ip->insn_opcode |= regno << 21; |
5477 | break; | |
3d3c5039 | 5478 | case 'd': |
918692a5 | 5479 | case 'G': |
670a50eb ILT |
5480 | ip->insn_opcode |= regno << 11; |
5481 | break; | |
3d3c5039 ILT |
5482 | case 'w': |
5483 | case 't': | |
918692a5 | 5484 | case 'E': |
670a50eb | 5485 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
5486 | break; |
5487 | case 'x': | |
5488 | /* This case exists because on the r3000 trunc | |
5489 | expands into a macro which requires a gp | |
5490 | register. On the r6000 or r4000 it is | |
5491 | assembled into a single instruction which | |
5492 | ignores the register. Thus the insn version | |
5493 | is MIPS_ISA2 and uses 'x', and the macro | |
5494 | version is MIPS_ISA1 and uses 't'. */ | |
5495 | break; | |
ff3a5c18 ILT |
5496 | case 'z': |
5497 | /* This case is for the div instruction, which | |
5498 | acts differently if the destination argument | |
5499 | is $0. This only matches $0, and is checked | |
5500 | outside the switch. */ | |
5501 | break; | |
3d3c5039 | 5502 | } |
670a50eb ILT |
5503 | lastregno = regno; |
5504 | continue; | |
3d3c5039 ILT |
5505 | } |
5506 | notreg: | |
670a50eb ILT |
5507 | switch (*args++) |
5508 | { | |
3d3c5039 ILT |
5509 | case 'r': |
5510 | case 'v': | |
670a50eb ILT |
5511 | ip->insn_opcode |= lastregno << 21; |
5512 | continue; | |
3d3c5039 | 5513 | case 'w': |
670a50eb ILT |
5514 | ip->insn_opcode |= lastregno << 16; |
5515 | continue; | |
3d3c5039 | 5516 | } |
670a50eb | 5517 | break; |
3d3c5039 | 5518 | |
670a50eb ILT |
5519 | case 'D': /* floating point destination register */ |
5520 | case 'S': /* floating point source register */ | |
5521 | case 'T': /* floating point target register */ | |
d8a1c247 | 5522 | case 'R': /* floating point source register */ |
3d3c5039 ILT |
5523 | case 'V': |
5524 | case 'W': | |
670a50eb ILT |
5525 | s_reset = s; |
5526 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
5527 | { | |
5528 | s += 2; | |
5529 | regno = 0; | |
5530 | do | |
5531 | { | |
5532 | regno *= 10; | |
5533 | regno += *s - '0'; | |
5534 | ++s; | |
5535 | } | |
5536 | while (isdigit (*s)); | |
5537 | ||
5538 | if (regno > 31) | |
5539 | as_bad ("Invalid float register number (%d)", regno); | |
5540 | ||
9226253a ILT |
5541 | if ((regno & 1) != 0 |
5542 | && mips_isa < 3 | |
538034cf ILT |
5543 | && ! (strcmp (str, "mtc1") == 0 |
5544 | || strcmp (str, "mfc1") == 0 | |
5545 | || strcmp (str, "lwc1") == 0 | |
5546 | || strcmp (str, "swc1") == 0 | |
5547 | || strcmp (str, "l.s") == 0 | |
5548 | || strcmp (str, "s.s") == 0)) | |
670a50eb ILT |
5549 | as_warn ("Float register should be even, was %d", |
5550 | regno); | |
5551 | ||
5552 | c = *args; | |
5553 | if (*s == ' ') | |
5554 | s++; | |
5555 | if (args[1] != *s) | |
5556 | { | |
5557 | if (c == 'V' || c == 'W') | |
5558 | { | |
5559 | regno = lastregno; | |
5560 | s = s_reset; | |
5561 | args++; | |
3d3c5039 ILT |
5562 | } |
5563 | } | |
670a50eb ILT |
5564 | switch (c) |
5565 | { | |
3d3c5039 | 5566 | case 'D': |
670a50eb ILT |
5567 | ip->insn_opcode |= regno << 6; |
5568 | break; | |
3d3c5039 ILT |
5569 | case 'V': |
5570 | case 'S': | |
670a50eb ILT |
5571 | ip->insn_opcode |= regno << 11; |
5572 | break; | |
3d3c5039 ILT |
5573 | case 'W': |
5574 | case 'T': | |
670a50eb | 5575 | ip->insn_opcode |= regno << 16; |
d8a1c247 KR |
5576 | break; |
5577 | case 'R': | |
5578 | ip->insn_opcode |= regno << 21; | |
5579 | break; | |
3d3c5039 | 5580 | } |
670a50eb ILT |
5581 | lastregno = regno; |
5582 | continue; | |
3d3c5039 | 5583 | } |
670a50eb ILT |
5584 | switch (*args++) |
5585 | { | |
3d3c5039 | 5586 | case 'V': |
670a50eb ILT |
5587 | ip->insn_opcode |= lastregno << 11; |
5588 | continue; | |
3d3c5039 | 5589 | case 'W': |
670a50eb ILT |
5590 | ip->insn_opcode |= lastregno << 16; |
5591 | continue; | |
3d3c5039 | 5592 | } |
670a50eb | 5593 | break; |
3d3c5039 ILT |
5594 | |
5595 | case 'I': | |
670a50eb | 5596 | my_getExpression (&imm_expr, s); |
9753202d ILT |
5597 | if (imm_expr.X_op != O_big |
5598 | && imm_expr.X_op != O_constant) | |
5599 | insn_error = "absolute expression required"; | |
670a50eb ILT |
5600 | s = expr_end; |
5601 | continue; | |
3d3c5039 ILT |
5602 | |
5603 | case 'A': | |
670a50eb ILT |
5604 | my_getExpression (&offset_expr, s); |
5605 | imm_reloc = BFD_RELOC_32; | |
5606 | s = expr_end; | |
5607 | continue; | |
3d3c5039 ILT |
5608 | |
5609 | case 'F': | |
19ed8960 ILT |
5610 | case 'L': |
5611 | case 'f': | |
5612 | case 'l': | |
5613 | { | |
5614 | int f64; | |
5615 | char *save_in; | |
5616 | char *err; | |
5617 | unsigned char temp[8]; | |
604633ae ILT |
5618 | int len; |
5619 | unsigned int length; | |
19ed8960 ILT |
5620 | segT seg; |
5621 | subsegT subseg; | |
5622 | char *p; | |
5623 | ||
5624 | /* These only appear as the last operand in an | |
5625 | instruction, and every instruction that accepts | |
5626 | them in any variant accepts them in all variants. | |
5627 | This means we don't have to worry about backing out | |
5628 | any changes if the instruction does not match. | |
5629 | ||
5630 | The difference between them is the size of the | |
5631 | floating point constant and where it goes. For 'F' | |
5632 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
5633 | is 32 bits. Where the constant is placed is based | |
5634 | on how the MIPS assembler does things: | |
5635 | F -- .rdata | |
5636 | L -- .lit8 | |
5637 | f -- immediate value | |
5638 | l -- .lit4 | |
0dd2d296 | 5639 | |
55933a58 ILT |
5640 | The .lit4 and .lit8 sections are only used if |
5641 | permitted by the -G argument. | |
5642 | ||
5643 | When generating embedded PIC code, we use the | |
5644 | .lit8 section but not the .lit4 section (we can do | |
5645 | .lit4 inline easily; we need to put .lit8 | |
5646 | somewhere in the data segment, and using .lit8 | |
5647 | permits the linker to eventually combine identical | |
5648 | .lit8 entries). */ | |
19ed8960 ILT |
5649 | |
5650 | f64 = *args == 'F' || *args == 'L'; | |
5651 | ||
5652 | save_in = input_line_pointer; | |
5653 | input_line_pointer = s; | |
604633ae ILT |
5654 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
5655 | length = len; | |
19ed8960 ILT |
5656 | s = input_line_pointer; |
5657 | input_line_pointer = save_in; | |
5658 | if (err != NULL && *err != '\0') | |
5659 | { | |
5660 | as_bad ("Bad floating point constant: %s", err); | |
5661 | memset (temp, '\0', sizeof temp); | |
5662 | length = f64 ? 8 : 4; | |
5663 | } | |
5664 | ||
5665 | assert (length == (f64 ? 8 : 4)); | |
5666 | ||
0dd2d296 | 5667 | if (*args == 'f' |
55933a58 | 5668 | || (*args == 'l' |
1dc1e798 KR |
5669 | && (! USE_GLOBAL_POINTER_OPT |
5670 | || mips_pic == EMBEDDED_PIC | |
1113140a | 5671 | || g_switch_value < 4) |
1113140a | 5672 | )) |
19ed8960 ILT |
5673 | { |
5674 | imm_expr.X_op = O_constant; | |
5675 | if (byte_order == LITTLE_ENDIAN) | |
5676 | imm_expr.X_add_number = | |
5677 | (((((((int) temp[3] << 8) | |
5678 | | temp[2]) << 8) | |
5679 | | temp[1]) << 8) | |
5680 | | temp[0]); | |
5681 | else | |
5682 | imm_expr.X_add_number = | |
5683 | (((((((int) temp[0] << 8) | |
5684 | | temp[1]) << 8) | |
5685 | | temp[2]) << 8) | |
5686 | | temp[3]); | |
5687 | } | |
5688 | else | |
5689 | { | |
0dd2d296 ILT |
5690 | const char *newname; |
5691 | segT new_seg; | |
5692 | ||
19ed8960 ILT |
5693 | /* Switch to the right section. */ |
5694 | seg = now_seg; | |
5695 | subseg = now_subseg; | |
5696 | switch (*args) | |
5697 | { | |
0dd2d296 | 5698 | default: /* unused default case avoids warnings. */ |
19ed8960 | 5699 | case 'L': |
1113140a | 5700 | newname = RDATA_SECTION_NAME; |
1dc1e798 | 5701 | if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
1113140a | 5702 | newname = ".lit8"; |
0dd2d296 ILT |
5703 | break; |
5704 | case 'F': | |
d2c71068 | 5705 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
5706 | break; |
5707 | case 'l': | |
1dc1e798 KR |
5708 | assert (!USE_GLOBAL_POINTER_OPT |
5709 | || g_switch_value >= 4); | |
0dd2d296 | 5710 | newname = ".lit4"; |
19ed8960 ILT |
5711 | break; |
5712 | } | |
0dd2d296 | 5713 | new_seg = subseg_new (newname, (subsegT) 0); |
9b61d62b ILT |
5714 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
5715 | bfd_set_section_flags (stdoutput, new_seg, | |
5716 | (SEC_ALLOC | |
5717 | | SEC_LOAD | |
5718 | | SEC_READONLY | |
5719 | | SEC_DATA)); | |
0221ddf7 | 5720 | frag_align (*args == 'l' ? 2 : 3, 0); |
1dc1e798 KR |
5721 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
5722 | record_alignment (new_seg, 4); | |
5723 | else | |
5724 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
19ed8960 ILT |
5725 | if (seg == now_seg) |
5726 | as_bad ("Can't use floating point insn in this section"); | |
5727 | ||
5728 | /* Set the argument to the current address in the | |
6e8dda9c | 5729 | section. */ |
19ed8960 ILT |
5730 | offset_expr.X_op = O_symbol; |
5731 | offset_expr.X_add_symbol = | |
5732 | symbol_new ("L0\001", now_seg, | |
5733 | (valueT) frag_now_fix (), frag_now); | |
5734 | offset_expr.X_add_number = 0; | |
5735 | ||
5736 | /* Put the floating point number into the section. */ | |
604633ae | 5737 | p = frag_more ((int) length); |
19ed8960 ILT |
5738 | memcpy (p, temp, length); |
5739 | ||
5740 | /* Switch back to the original section. */ | |
5741 | subseg_set (seg, subseg); | |
5742 | } | |
5743 | } | |
670a50eb ILT |
5744 | continue; |
5745 | ||
5746 | case 'i': /* 16 bit unsigned immediate */ | |
5747 | case 'j': /* 16 bit signed immediate */ | |
5748 | imm_reloc = BFD_RELOC_LO16; | |
5749 | c = my_getSmallExpression (&imm_expr, s); | |
344a8d61 | 5750 | if (c != '\0') |
670a50eb ILT |
5751 | { |
5752 | if (c != 'l') | |
5753 | { | |
5ac34ac3 | 5754 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
5755 | imm_expr.X_add_number = |
5756 | (imm_expr.X_add_number >> 16) & 0xffff; | |
5757 | else if (c == 'h') | |
867a58b3 ILT |
5758 | { |
5759 | imm_reloc = BFD_RELOC_HI16_S; | |
5760 | imm_unmatched_hi = true; | |
5761 | } | |
670a50eb ILT |
5762 | else |
5763 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 5764 | } |
670a50eb | 5765 | } |
670a50eb ILT |
5766 | if (*args == 'i') |
5767 | { | |
344a8d61 | 5768 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
5769 | || ((imm_expr.X_add_number < 0 |
5770 | || imm_expr.X_add_number >= 0x10000) | |
5771 | && imm_expr.X_op == O_constant)) | |
99c24539 ILT |
5772 | { |
5773 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
5774 | !strcmp (insn->name, insn[1].name)) | |
5775 | break; | |
9753202d ILT |
5776 | if (imm_expr.X_op != O_constant |
5777 | && imm_expr.X_op != O_big) | |
5778 | insn_error = "absolute expression required"; | |
5779 | else | |
5780 | as_bad ("16 bit expression not in range 0..65535"); | |
99c24539 | 5781 | } |
670a50eb ILT |
5782 | } |
5783 | else | |
5784 | { | |
d9aba805 ILT |
5785 | int more; |
5786 | offsetT max; | |
5787 | ||
be22008b ILT |
5788 | /* The upper bound should be 0x8000, but |
5789 | unfortunately the MIPS assembler accepts numbers | |
5790 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
5791 | we want to be compatible. We only permit this |
5792 | extended range for an instruction which does not | |
5793 | provide any further alternates, since those | |
5794 | alternates may handle other cases. People should | |
5795 | use the numbers they mean, rather than relying on | |
5796 | a mysterious sign extension. */ | |
5797 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
5798 | strcmp (insn->name, insn[1].name) == 0); | |
5799 | if (more) | |
5800 | max = 0x8000; | |
5801 | else | |
5802 | max = 0x10000; | |
344a8d61 | 5803 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
5804 | || ((imm_expr.X_add_number < -0x8000 |
5805 | || imm_expr.X_add_number >= max) | |
5806 | && imm_expr.X_op == O_constant) | |
d8a1c247 KR |
5807 | || (more |
5808 | && imm_expr.X_add_number < 0 | |
5809 | && mips_isa >= 3 | |
5810 | && imm_expr.X_unsigned | |
5811 | && sizeof (imm_expr.X_add_number) <= 4)) | |
99c24539 | 5812 | { |
d9aba805 | 5813 | if (more) |
99c24539 | 5814 | break; |
9753202d ILT |
5815 | if (imm_expr.X_op != O_constant |
5816 | && imm_expr.X_op != O_big) | |
5817 | insn_error = "absolute expression required"; | |
5818 | else | |
5819 | as_bad ("16 bit expression not in range -32768..32767"); | |
99c24539 | 5820 | } |
3d3c5039 | 5821 | } |
670a50eb ILT |
5822 | s = expr_end; |
5823 | continue; | |
5824 | ||
5825 | case 'o': /* 16 bit offset */ | |
5826 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
5827 | |
5828 | /* If this value won't fit into a 16 bit offset, then go | |
5829 | find a macro that will generate the 32 bit offset | |
5830 | code pattern. As a special hack, we accept the | |
5831 | difference of two local symbols as a constant. This | |
5832 | is required to suppose embedded PIC switches, which | |
5833 | use an instruction which looks like | |
5834 | lw $4,$L12-$LS12($4) | |
5835 | The problem with handling this in a more general | |
5836 | fashion is that the macro function doesn't expect to | |
5837 | see anything which can be handled in a single | |
5838 | constant instruction. */ | |
6f0b87c3 SS |
5839 | if (c == 0 |
5840 | && (offset_expr.X_op != O_constant | |
5841 | || offset_expr.X_add_number >= 0x8000 | |
5842 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
5843 | && (mips_pic != EMBEDDED_PIC |
5844 | || offset_expr.X_op != O_subtract | |
9da4c5d1 ILT |
5845 | || now_seg != text_section |
5846 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
5847 | != text_section))) | |
670a50eb | 5848 | break; |
3d3c5039 | 5849 | |
670a50eb ILT |
5850 | offset_reloc = BFD_RELOC_LO16; |
5851 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
5852 | { |
5853 | assert (offset_expr.X_op == O_constant); | |
5854 | offset_expr.X_add_number = | |
5855 | (offset_expr.X_add_number >> 16) & 0xffff; | |
5856 | } | |
670a50eb ILT |
5857 | s = expr_end; |
5858 | continue; | |
5859 | ||
5860 | case 'p': /* pc relative offset */ | |
5861 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
5862 | my_getExpression (&offset_expr, s); | |
5863 | s = expr_end; | |
5864 | continue; | |
5865 | ||
5866 | case 'u': /* upper 16 bits */ | |
5867 | c = my_getSmallExpression (&imm_expr, s); | |
36a87ad7 ILT |
5868 | if (imm_expr.X_op == O_constant |
5869 | && (imm_expr.X_add_number < 0 | |
5870 | || imm_expr.X_add_number >= 0x10000)) | |
670a50eb ILT |
5871 | as_bad ("lui expression not in range 0..65535"); |
5872 | imm_reloc = BFD_RELOC_LO16; | |
5873 | if (c) | |
5874 | { | |
5875 | if (c != 'l') | |
5876 | { | |
5ac34ac3 | 5877 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
5878 | imm_expr.X_add_number = |
5879 | (imm_expr.X_add_number >> 16) & 0xffff; | |
5880 | else if (c == 'h') | |
867a58b3 ILT |
5881 | { |
5882 | imm_reloc = BFD_RELOC_HI16_S; | |
5883 | imm_unmatched_hi = true; | |
5884 | } | |
670a50eb ILT |
5885 | else |
5886 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 ILT |
5887 | } |
5888 | } | |
670a50eb ILT |
5889 | s = expr_end; |
5890 | continue; | |
3d3c5039 | 5891 | |
670a50eb ILT |
5892 | case 'a': /* 26 bit address */ |
5893 | my_getExpression (&offset_expr, s); | |
5894 | s = expr_end; | |
5895 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
5896 | continue; | |
3d3c5039 | 5897 | |
d8a1c247 KR |
5898 | case 'N': /* 3 bit branch condition code */ |
5899 | case 'M': /* 3 bit compare condition code */ | |
d31a3f5e ILT |
5900 | if (strncmp (s, "$fcc", 4) != 0) |
5901 | break; | |
5902 | s += 4; | |
5903 | regno = 0; | |
5904 | do | |
d8a1c247 | 5905 | { |
d31a3f5e ILT |
5906 | regno *= 10; |
5907 | regno += *s - '0'; | |
5908 | ++s; | |
d8a1c247 | 5909 | } |
d31a3f5e ILT |
5910 | while (isdigit (*s)); |
5911 | if (regno > 7) | |
5912 | as_bad ("invalid condition code register $fcc%d", regno); | |
d8a1c247 | 5913 | if (*args == 'N') |
d31a3f5e | 5914 | ip->insn_opcode |= regno << OP_SH_BCC; |
d8a1c247 | 5915 | else |
d31a3f5e | 5916 | ip->insn_opcode |= regno << OP_SH_CCC; |
d8a1c247 KR |
5917 | continue; |
5918 | ||
3d3c5039 | 5919 | default: |
670a50eb ILT |
5920 | fprintf (stderr, "bad char = '%c'\n", *args); |
5921 | internalError (); | |
3d3c5039 | 5922 | } |
670a50eb | 5923 | break; |
3d3c5039 | 5924 | } |
670a50eb ILT |
5925 | /* Args don't match. */ |
5926 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
5927 | !strcmp (insn->name, insn[1].name)) | |
5928 | { | |
5929 | ++insn; | |
5930 | s = argsStart; | |
5931 | continue; | |
3d3c5039 | 5932 | } |
9753202d | 5933 | insn_error = "illegal operands"; |
670a50eb | 5934 | return; |
3d3c5039 ILT |
5935 | } |
5936 | } | |
5937 | ||
5938 | #define LP '(' | |
5939 | #define RP ')' | |
5940 | ||
5941 | static int | |
5942 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
5943 | expressionS *ep; |
5944 | char *str; | |
3d3c5039 | 5945 | { |
670a50eb ILT |
5946 | char *sp; |
5947 | int c = 0; | |
5948 | ||
5949 | if (*str == ' ') | |
5950 | str++; | |
5951 | if (*str == LP | |
5952 | || (*str == '%' && | |
5953 | ((str[1] == 'h' && str[2] == 'i') | |
5954 | || (str[1] == 'H' && str[2] == 'I') | |
5955 | || (str[1] == 'l' && str[2] == 'o')) | |
5956 | && str[3] == LP)) | |
5957 | { | |
5958 | if (*str == LP) | |
5959 | c = 0; | |
5960 | else | |
5961 | { | |
5962 | c = str[1]; | |
5963 | str += 3; | |
5964 | } | |
5965 | ||
5966 | /* | |
5967 | * A small expression may be followed by a base register. | |
5968 | * Scan to the end of this operand, and then back over a possible | |
5969 | * base register. Then scan the small expression up to that | |
5970 | * point. (Based on code in sparc.c...) | |
5971 | */ | |
5972 | for (sp = str; *sp && *sp != ','; sp++) | |
5973 | ; | |
5974 | if (sp - 4 >= str && sp[-1] == RP) | |
5975 | { | |
5976 | if (isdigit (sp[-2])) | |
5977 | { | |
5978 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
5979 | ; | |
5980 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
5981 | { | |
5982 | sp--; | |
5983 | goto do_it; | |
3d3c5039 | 5984 | } |
670a50eb ILT |
5985 | } |
5986 | else if (sp - 5 >= str | |
5987 | && sp[-5] == LP | |
5988 | && sp[-4] == '$' | |
5989 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
5990 | || (sp[-3] == 's' && sp[-2] == 'p') | |
5991 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
5992 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
5993 | { | |
5994 | sp -= 5; | |
3d3c5039 | 5995 | do_it: |
670a50eb ILT |
5996 | if (sp == str) |
5997 | { | |
5998 | /* no expression means zero offset */ | |
5999 | if (c) | |
6000 | { | |
6001 | /* %xx(reg) is an error */ | |
5ac34ac3 | 6002 | ep->X_op = O_absent; |
670a50eb | 6003 | expr_end = str - 3; |
3d3c5039 | 6004 | } |
670a50eb ILT |
6005 | else |
6006 | { | |
52aa70b5 | 6007 | ep->X_op = O_constant; |
670a50eb ILT |
6008 | expr_end = sp; |
6009 | } | |
6010 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 6011 | ep->X_op_symbol = NULL; |
670a50eb ILT |
6012 | ep->X_add_number = 0; |
6013 | } | |
6014 | else | |
6015 | { | |
6016 | *sp = '\0'; | |
6017 | my_getExpression (ep, str); | |
6018 | *sp = LP; | |
3d3c5039 | 6019 | } |
670a50eb | 6020 | return c; |
3d3c5039 ILT |
6021 | } |
6022 | } | |
6023 | } | |
670a50eb ILT |
6024 | my_getExpression (ep, str); |
6025 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
6026 | } |
6027 | ||
6028 | static void | |
6029 | my_getExpression (ep, str) | |
670a50eb ILT |
6030 | expressionS *ep; |
6031 | char *str; | |
3d3c5039 | 6032 | { |
670a50eb | 6033 | char *save_in; |
670a50eb ILT |
6034 | |
6035 | save_in = input_line_pointer; | |
6036 | input_line_pointer = str; | |
5ac34ac3 | 6037 | expression (ep); |
670a50eb ILT |
6038 | expr_end = input_line_pointer; |
6039 | input_line_pointer = save_in; | |
3d3c5039 ILT |
6040 | } |
6041 | ||
becfe05e ILT |
6042 | /* Turn a string in input_line_pointer into a floating point constant |
6043 | of type type, and store the appropriate bytes in *litP. The number | |
6044 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
6045 | returned, or NULL on OK. */ | |
6046 | ||
3d3c5039 | 6047 | char * |
670a50eb | 6048 | md_atof (type, litP, sizeP) |
becfe05e | 6049 | int type; |
3d3c5039 ILT |
6050 | char *litP; |
6051 | int *sizeP; | |
6052 | { | |
becfe05e ILT |
6053 | int prec; |
6054 | LITTLENUM_TYPE words[4]; | |
6055 | char *t; | |
6056 | int i; | |
6057 | ||
6058 | switch (type) | |
6059 | { | |
6060 | case 'f': | |
6061 | prec = 2; | |
6062 | break; | |
6063 | ||
6064 | case 'd': | |
6065 | prec = 4; | |
6066 | break; | |
6067 | ||
6068 | default: | |
6069 | *sizeP = 0; | |
6070 | return "bad call to md_atof"; | |
6071 | } | |
6072 | ||
6073 | t = atof_ieee (input_line_pointer, type, words); | |
6074 | if (t) | |
6075 | input_line_pointer = t; | |
6076 | ||
6077 | *sizeP = prec * 2; | |
6078 | ||
6079 | if (byte_order == LITTLE_ENDIAN) | |
6080 | { | |
6081 | for (i = prec - 1; i >= 0; i--) | |
6082 | { | |
6083 | md_number_to_chars (litP, (valueT) words[i], 2); | |
6084 | litP += 2; | |
6085 | } | |
6086 | } | |
6087 | else | |
6088 | { | |
6089 | for (i = 0; i < prec; i++) | |
6090 | { | |
6091 | md_number_to_chars (litP, (valueT) words[i], 2); | |
6092 | litP += 2; | |
6093 | } | |
6094 | } | |
6095 | ||
670a50eb | 6096 | return NULL; |
3d3c5039 ILT |
6097 | } |
6098 | ||
6099 | void | |
6100 | md_number_to_chars (buf, val, n) | |
6101 | char *buf; | |
918692a5 | 6102 | valueT val; |
3d3c5039 ILT |
6103 | int n; |
6104 | { | |
670a50eb ILT |
6105 | switch (byte_order) |
6106 | { | |
3d3c5039 | 6107 | case LITTLE_ENDIAN: |
13fe1379 ILT |
6108 | number_to_chars_littleendian (buf, val, n); |
6109 | break; | |
3d3c5039 ILT |
6110 | |
6111 | case BIG_ENDIAN: | |
13fe1379 ILT |
6112 | number_to_chars_bigendian (buf, val, n); |
6113 | break; | |
3d3c5039 ILT |
6114 | |
6115 | default: | |
670a50eb | 6116 | internalError (); |
3d3c5039 ILT |
6117 | } |
6118 | } | |
f3d817d8 | 6119 | \f |
e8d4d475 | 6120 | CONST char *md_shortopts = "O::g::G:"; |
1dc1e798 | 6121 | |
f3d817d8 DM |
6122 | struct option md_longopts[] = { |
6123 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
6124 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
6125 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
6126 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
6127 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
6128 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
6129 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
d8a1c247 KR |
6130 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
6131 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
6132 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
f3d817d8 | 6133 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
d8a1c247 | 6134 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) |
f3d817d8 | 6135 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
d8a1c247 | 6136 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
f3d817d8 DM |
6137 | {"trap", no_argument, NULL, OPTION_TRAP}, |
6138 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
d8a1c247 | 6139 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
f3d817d8 DM |
6140 | {"break", no_argument, NULL, OPTION_BREAK}, |
6141 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
d8a1c247 | 6142 | #define OPTION_EB (OPTION_MD_BASE + 11) |
e8d4d475 | 6143 | {"EB", no_argument, NULL, OPTION_EB}, |
d8a1c247 | 6144 | #define OPTION_EL (OPTION_MD_BASE + 12) |
e8d4d475 | 6145 | {"EL", no_argument, NULL, OPTION_EL}, |
d8a1c247 | 6146 | #define OPTION_M4650 (OPTION_MD_BASE + 13) |
b2b8c24e | 6147 | {"m4650", no_argument, NULL, OPTION_M4650}, |
d8a1c247 | 6148 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) |
b2b8c24e | 6149 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
e532b44c ILT |
6150 | #define OPTION_M4010 (OPTION_MD_BASE + 15) |
6151 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
6152 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
6153 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
c625fc23 JSC |
6154 | #define OPTION_M4100 (OPTION_MD_BASE + 17) |
6155 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
6156 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
6157 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
f3d817d8 | 6158 | |
d8a1c247 | 6159 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) |
1dc1e798 | 6160 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) |
fb251650 | 6161 | #define OPTION_XGOT (OPTION_MD_BASE + 19) |
7f9880e5 ILT |
6162 | #define OPTION_32 (OPTION_MD_BASE + 20) |
6163 | #define OPTION_64 (OPTION_MD_BASE + 21) | |
1dc1e798 | 6164 | #ifdef OBJ_ELF |
f3d817d8 | 6165 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
fb251650 | 6166 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
f3d817d8 | 6167 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
f3d817d8 | 6168 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
7f9880e5 ILT |
6169 | {"32", no_argument, NULL, OPTION_32}, |
6170 | {"64", no_argument, NULL, OPTION_64}, | |
f3d817d8 DM |
6171 | #endif |
6172 | ||
6173 | {NULL, no_argument, NULL, 0} | |
6174 | }; | |
6175 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
6176 | |
6177 | int | |
f3d817d8 DM |
6178 | md_parse_option (c, arg) |
6179 | int c; | |
6180 | char *arg; | |
3d3c5039 | 6181 | { |
f3d817d8 | 6182 | switch (c) |
670a50eb | 6183 | { |
f3d817d8 DM |
6184 | case OPTION_TRAP: |
6185 | mips_trap = 1; | |
6186 | break; | |
670a50eb | 6187 | |
f3d817d8 DM |
6188 | case OPTION_BREAK: |
6189 | mips_trap = 0; | |
6190 | break; | |
6191 | ||
e8d4d475 | 6192 | case OPTION_EB: |
1dc1e798 | 6193 | target_big_endian = 1; |
e8d4d475 | 6194 | break; |
04cb3372 | 6195 | |
e8d4d475 | 6196 | case OPTION_EL: |
1dc1e798 | 6197 | target_big_endian = 0; |
f3d817d8 | 6198 | break; |
670a50eb | 6199 | |
f3d817d8 DM |
6200 | case 'O': |
6201 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
6202 | mips_optimize = 1; |
6203 | else | |
6204 | mips_optimize = 2; | |
f3d817d8 | 6205 | break; |
0aa07269 | 6206 | |
f3d817d8 | 6207 | case 'g': |
22ba90ce ILT |
6208 | if (arg == NULL) |
6209 | mips_debug = 2; | |
6210 | else | |
6211 | mips_debug = atoi (arg); | |
6212 | /* When the MIPS assembler sees -g or -g2, it does not do | |
6213 | optimizations which limit full symbolic debugging. We take | |
6214 | that to be equivalent to -O0. */ | |
6215 | if (mips_debug == 2) | |
0aa07269 | 6216 | mips_optimize = 0; |
f3d817d8 | 6217 | break; |
4e95866e | 6218 | |
f3d817d8 DM |
6219 | case OPTION_MIPS1: |
6220 | mips_isa = 1; | |
4bb0cc41 ILT |
6221 | if (mips_cpu == -1) |
6222 | mips_cpu = 3000; | |
f3d817d8 | 6223 | break; |
8358c818 | 6224 | |
f3d817d8 DM |
6225 | case OPTION_MIPS2: |
6226 | mips_isa = 2; | |
4bb0cc41 ILT |
6227 | if (mips_cpu == -1) |
6228 | mips_cpu = 6000; | |
f3d817d8 | 6229 | break; |
8358c818 | 6230 | |
f3d817d8 DM |
6231 | case OPTION_MIPS3: |
6232 | mips_isa = 3; | |
4bb0cc41 ILT |
6233 | if (mips_cpu == -1) |
6234 | mips_cpu = 4000; | |
f3d817d8 | 6235 | break; |
8358c818 | 6236 | |
d8a1c247 KR |
6237 | case OPTION_MIPS4: |
6238 | mips_isa = 4; | |
6239 | if (mips_cpu == -1) | |
6240 | mips_cpu = 8000; | |
6241 | break; | |
6242 | ||
f3d817d8 DM |
6243 | case OPTION_MCPU: |
6244 | { | |
6245 | char *p; | |
6246 | ||
6247 | /* Identify the processor type */ | |
6248 | p = arg; | |
6249 | if (strcmp (p, "default") == 0 | |
6250 | || strcmp (p, "DEFAULT") == 0) | |
4bb0cc41 | 6251 | mips_cpu = -1; |
f3d817d8 DM |
6252 | else |
6253 | { | |
c625fc23 JSC |
6254 | int sv = 0; |
6255 | ||
6256 | /* We need to cope with the various "vr" prefixes for the 4300 | |
6257 | processor. */ | |
6258 | if (*p == 'v' || *p == 'V') | |
6259 | { | |
6260 | sv = 1; | |
6261 | p++; | |
6262 | } | |
6263 | ||
f3d817d8 DM |
6264 | if (*p == 'r' || *p == 'R') |
6265 | p++; | |
8358c818 | 6266 | |
4bb0cc41 | 6267 | mips_cpu = -1; |
f3d817d8 DM |
6268 | switch (*p) |
6269 | { | |
d8a1c247 KR |
6270 | case '1': |
6271 | if (strcmp (p, "10000") == 0 | |
6272 | || strcmp (p, "10k") == 0 | |
6273 | || strcmp (p, "10K") == 0) | |
6274 | mips_cpu = 10000; | |
6275 | break; | |
6276 | ||
f3d817d8 DM |
6277 | case '2': |
6278 | if (strcmp (p, "2000") == 0 | |
6279 | || strcmp (p, "2k") == 0 | |
6280 | || strcmp (p, "2K") == 0) | |
4bb0cc41 | 6281 | mips_cpu = 2000; |
f3d817d8 | 6282 | break; |
8358c818 | 6283 | |
f3d817d8 DM |
6284 | case '3': |
6285 | if (strcmp (p, "3000") == 0 | |
6286 | || strcmp (p, "3k") == 0 | |
6287 | || strcmp (p, "3K") == 0) | |
4bb0cc41 | 6288 | mips_cpu = 3000; |
f3d817d8 | 6289 | break; |
8358c818 | 6290 | |
f3d817d8 DM |
6291 | case '4': |
6292 | if (strcmp (p, "4000") == 0 | |
6293 | || strcmp (p, "4k") == 0 | |
8c63448a | 6294 | || strcmp (p, "4K") == 0) |
4bb0cc41 | 6295 | mips_cpu = 4000; |
c625fc23 JSC |
6296 | else if (strcmp (p, "4100") == 0) |
6297 | { | |
6298 | mips_cpu = 4100; | |
6299 | if (mips_4100 < 0) | |
6300 | mips_4100 = 1; | |
6301 | } | |
6302 | else if (strcmp (p, "4300") == 0) | |
6303 | mips_cpu = 4300; | |
8c63448a | 6304 | else if (strcmp (p, "4400") == 0) |
4bb0cc41 | 6305 | mips_cpu = 4400; |
8c63448a | 6306 | else if (strcmp (p, "4600") == 0) |
4bb0cc41 | 6307 | mips_cpu = 4600; |
b2b8c24e ILT |
6308 | else if (strcmp (p, "4650") == 0) |
6309 | { | |
6310 | mips_cpu = 4650; | |
6311 | if (mips_4650 < 0) | |
6312 | mips_4650 = 1; | |
6313 | } | |
e532b44c ILT |
6314 | else if (strcmp (p, "4010") == 0) |
6315 | { | |
6316 | mips_cpu = 4010; | |
6317 | if (mips_4010 < 0) | |
6318 | mips_4010 = 1; | |
6319 | } | |
f3d817d8 | 6320 | break; |
8358c818 | 6321 | |
517078c1 ILT |
6322 | case '5': |
6323 | if (strcmp (p, "5000") == 0 | |
6324 | || strcmp (p, "5k") == 0 | |
6325 | || strcmp (p, "5K") == 0) | |
6326 | mips_cpu = 5000; | |
6327 | break; | |
6328 | ||
f3d817d8 DM |
6329 | case '6': |
6330 | if (strcmp (p, "6000") == 0 | |
6331 | || strcmp (p, "6k") == 0 | |
6332 | || strcmp (p, "6K") == 0) | |
4bb0cc41 | 6333 | mips_cpu = 6000; |
f3d817d8 | 6334 | break; |
55933a58 | 6335 | |
d8a1c247 KR |
6336 | case '8': |
6337 | if (strcmp (p, "8000") == 0 | |
6338 | || strcmp (p, "8k") == 0 | |
6339 | || strcmp (p, "8K") == 0) | |
6340 | mips_cpu = 8000; | |
6341 | break; | |
6342 | ||
55933a58 ILT |
6343 | case 'o': |
6344 | if (strcmp (p, "orion") == 0) | |
4bb0cc41 | 6345 | mips_cpu = 4600; |
55933a58 | 6346 | break; |
f3d817d8 | 6347 | } |
8358c818 | 6348 | |
517078c1 | 6349 | if (sv && mips_cpu != 4300 && mips_cpu != 4100 && mips_cpu != 5000) |
c625fc23 JSC |
6350 | { |
6351 | as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg); | |
6352 | return 0; | |
6353 | } | |
6354 | ||
4bb0cc41 | 6355 | if (mips_cpu == -1) |
f3d817d8 DM |
6356 | { |
6357 | as_bad ("invalid architecture -mcpu=%s", arg); | |
6358 | return 0; | |
6359 | } | |
6360 | } | |
6361 | } | |
6362 | break; | |
8358c818 | 6363 | |
b2b8c24e ILT |
6364 | case OPTION_M4650: |
6365 | mips_4650 = 1; | |
6366 | break; | |
6367 | ||
6368 | case OPTION_NO_M4650: | |
6369 | mips_4650 = 0; | |
6370 | break; | |
6371 | ||
e532b44c ILT |
6372 | case OPTION_M4010: |
6373 | mips_4010 = 1; | |
6374 | break; | |
6375 | ||
6376 | case OPTION_NO_M4010: | |
6377 | mips_4010 = 0; | |
6378 | break; | |
6379 | ||
c625fc23 JSC |
6380 | case OPTION_M4100: |
6381 | mips_4100 = 1; | |
6382 | break; | |
6383 | ||
6384 | case OPTION_NO_M4100: | |
6385 | mips_4100 = 0; | |
6386 | break; | |
6387 | ||
f3d817d8 | 6388 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 6389 | mips_pic = EMBEDDED_PIC; |
1dc1e798 | 6390 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
f3d817d8 DM |
6391 | { |
6392 | as_bad ("-G may not be used with embedded PIC code"); | |
6393 | return 0; | |
6394 | } | |
5b63f465 | 6395 | g_switch_value = 0x7fffffff; |
f3d817d8 | 6396 | break; |
d9aba805 | 6397 | |
fb251650 ILT |
6398 | /* When generating ELF code, we permit -KPIC and -call_shared to |
6399 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
6400 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 6401 | case OPTION_CALL_SHARED: |
1dc1e798 KR |
6402 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
6403 | { | |
6404 | as_bad ("-call_shared is supported only for ELF format"); | |
6405 | return 0; | |
6406 | } | |
d9aba805 ILT |
6407 | mips_pic = SVR4_PIC; |
6408 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 DM |
6409 | { |
6410 | as_bad ("-G may not be used with SVR4 PIC code"); | |
6411 | return 0; | |
6412 | } | |
d9aba805 | 6413 | g_switch_value = 0; |
f3d817d8 DM |
6414 | break; |
6415 | ||
6416 | case OPTION_NON_SHARED: | |
1dc1e798 KR |
6417 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
6418 | { | |
6419 | as_bad ("-non_shared is supported only for ELF format"); | |
6420 | return 0; | |
6421 | } | |
d9aba805 | 6422 | mips_pic = NO_PIC; |
f3d817d8 | 6423 | break; |
8358c818 | 6424 | |
fb251650 ILT |
6425 | /* The -xgot option tells the assembler to use 32 offsets when |
6426 | accessing the got in SVR4_PIC mode. It is for Irix | |
6427 | compatibility. */ | |
6428 | case OPTION_XGOT: | |
6429 | mips_big_got = 1; | |
6430 | break; | |
6431 | ||
f3d817d8 | 6432 | case 'G': |
1dc1e798 KR |
6433 | if (! USE_GLOBAL_POINTER_OPT) |
6434 | { | |
6435 | as_bad ("-G is not supported for this configuration"); | |
6436 | return 0; | |
6437 | } | |
6438 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
670a50eb | 6439 | { |
f3d817d8 DM |
6440 | as_bad ("-G may not be used with SVR4 or embedded PIC code"); |
6441 | return 0; | |
670a50eb ILT |
6442 | } |
6443 | else | |
f3d817d8 | 6444 | g_switch_value = atoi (arg); |
42562568 | 6445 | g_switch_seen = 1; |
f3d817d8 | 6446 | break; |
4e95866e | 6447 | |
7f9880e5 ILT |
6448 | /* The -32 and -64 options tell the assembler to output the 32 |
6449 | bit or the 64 bit MIPS ELF format. */ | |
6450 | case OPTION_32: | |
6451 | mips_64 = 0; | |
6452 | break; | |
6453 | ||
6454 | case OPTION_64: | |
9c44af60 ILT |
6455 | { |
6456 | const char **list, **l; | |
6457 | ||
6458 | list = bfd_target_list (); | |
6459 | for (l = list; *l != NULL; l++) | |
6460 | if (strcmp (*l, "elf64-bigmips") == 0 | |
6461 | || strcmp (*l, "elf64-littlemips") == 0) | |
6462 | break; | |
6463 | if (*l == NULL) | |
6464 | as_fatal ("No compiled in support for 64 bit object file format"); | |
6465 | free (list); | |
6466 | mips_64 = 1; | |
6467 | } | |
7f9880e5 ILT |
6468 | break; |
6469 | ||
f3d817d8 DM |
6470 | default: |
6471 | return 0; | |
8ea7f4e8 ILT |
6472 | } |
6473 | ||
f3d817d8 | 6474 | return 1; |
8ea7f4e8 ILT |
6475 | } |
6476 | ||
f3d817d8 DM |
6477 | void |
6478 | md_show_usage (stream) | |
6479 | FILE *stream; | |
6480 | { | |
6481 | fprintf(stream, "\ | |
6482 | MIPS options:\n\ | |
6483 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
6484 | -EB generate big endian output\n\ |
6485 | -EL generate little endian output\n\ | |
6486 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
6487 | -G NUM allow referencing objects up to NUM bytes\n\ | |
6f0b87c3 SS |
6488 | implicitly with the gp register [default 8]\n"); |
6489 | fprintf(stream, "\ | |
f3d817d8 DM |
6490 | -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\ |
6491 | -mips2, -mcpu=r6000 generate code for r6000\n\ | |
6492 | -mips3, -mcpu=r4000 generate code for r4000\n\ | |
d8a1c247 | 6493 | -mips4, -mcpu=r8000 generate code for r8000\n\ |
c625fc23 | 6494 | -mcpu=vr4300 generate code for vr4300\n\ |
fb251650 | 6495 | -mcpu=vr4100 generate code for vr4100\n\ |
e532b44c ILT |
6496 | -m4650 permit R4650 instructions\n\ |
6497 | -no-m4650 do not permit R4650 instructions\n\ | |
6498 | -m4010 permit R4010 instructions\n\ | |
6499 | -no-m4010 do not permit R4010 instructions\n\ | |
c625fc23 JSC |
6500 | -m4100 permit VR4100 instructions\n\ |
6501 | -no-m4100 do not permit VR4100 instructions\n"); | |
6502 | fprintf(stream, "\ | |
f3d817d8 DM |
6503 | -O0 remove unneeded NOPs, do not swap branches\n\ |
6504 | -O remove unneeded NOPs and swap branches\n\ | |
6505 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
6506 | --break, --no-trap break exception on div by 0 and mult overflow\n"); | |
6507 | #ifdef OBJ_ELF | |
6508 | fprintf(stream, "\ | |
6509 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
fb251650 | 6510 | -non_shared do not generate position independent code\n\ |
7f9880e5 ILT |
6511 | -xgot assume a 32 bit GOT\n\ |
6512 | -32 create 32 bit object file (default)\n\ | |
6513 | -64 create 64 bit object file\n"); | |
f3d817d8 DM |
6514 | #endif |
6515 | } | |
22ba90ce ILT |
6516 | |
6517 | void | |
6518 | mips_init_after_args () | |
6519 | { | |
6520 | if (target_big_endian) | |
6521 | byte_order = BIG_ENDIAN; | |
6522 | else | |
6523 | byte_order = LITTLE_ENDIAN; | |
6524 | } | |
f3d817d8 | 6525 | \f |
3d3c5039 ILT |
6526 | long |
6527 | md_pcrel_from (fixP) | |
6528 | fixS *fixP; | |
6529 | { | |
1dc1e798 KR |
6530 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
6531 | && fixP->fx_addsy != (symbolS *) NULL | |
5b63f465 ILT |
6532 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
6533 | { | |
6534 | /* This makes a branch to an undefined symbol be a branch to the | |
6535 | current location. */ | |
6536 | return 4; | |
6537 | } | |
5b63f465 | 6538 | |
670a50eb ILT |
6539 | /* return the address of the delay slot */ |
6540 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
6541 | } |
6542 | ||
abdad6bc ILT |
6543 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
6544 | reloc for a cons. We could use the definition there, except that | |
6545 | we want to handle 64 bit relocs specially. */ | |
6546 | ||
6547 | void | |
6548 | cons_fix_new_mips (frag, where, nbytes, exp) | |
6549 | fragS *frag; | |
6550 | int where; | |
6551 | unsigned int nbytes; | |
6552 | expressionS *exp; | |
6553 | { | |
bf39474f | 6554 | #ifndef OBJ_ELF |
abdad6bc | 6555 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a |
7f9880e5 ILT |
6556 | 4 byte reloc. */ |
6557 | if (nbytes == 8 && ! mips_64) | |
abdad6bc ILT |
6558 | { |
6559 | if (byte_order == BIG_ENDIAN) | |
6560 | where += 4; | |
6561 | nbytes = 4; | |
6562 | } | |
bf39474f | 6563 | #endif |
abdad6bc | 6564 | |
7f9880e5 | 6565 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) |
abdad6bc ILT |
6566 | as_bad ("Unsupported reloc size %d", nbytes); |
6567 | ||
6568 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
7f9880e5 ILT |
6569 | (nbytes == 2 |
6570 | ? BFD_RELOC_16 | |
6571 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
abdad6bc ILT |
6572 | } |
6573 | ||
867a58b3 ILT |
6574 | /* Sort any unmatched HI16_S relocs so that they immediately precede |
6575 | the corresponding LO reloc. This is called before md_apply_fix and | |
6576 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
6577 | explicit use of the %hi modifier. */ | |
6578 | ||
6579 | void | |
6580 | mips_frob_file () | |
6581 | { | |
6582 | struct mips_hi_fixup *l; | |
6583 | ||
6584 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
6585 | { | |
6586 | segment_info_type *seginfo; | |
9b61d62b | 6587 | int pass; |
867a58b3 ILT |
6588 | |
6589 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
6590 | ||
6591 | /* Check quickly whether the next fixup happens to be a matching | |
6592 | %lo. */ | |
6593 | if (l->fixp->fx_next != NULL | |
6594 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
6595 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
6596 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
6597 | continue; | |
6598 | ||
6599 | /* Look through the fixups for this segment for a matching %lo. | |
9b61d62b ILT |
6600 | When we find one, move the %hi just in front of it. We do |
6601 | this in two passes. In the first pass, we try to find a | |
6602 | unique %lo. In the second pass, we permit multiple %hi | |
6603 | relocs for a single %lo (this is a GNU extension). */ | |
867a58b3 | 6604 | seginfo = seg_info (l->seg); |
9b61d62b ILT |
6605 | for (pass = 0; pass < 2; pass++) |
6606 | { | |
6607 | fixS *f, *prev; | |
6608 | ||
6609 | prev = NULL; | |
6610 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
867a58b3 | 6611 | { |
9b61d62b ILT |
6612 | /* Check whether this is a %lo fixup which matches l->fixp. */ |
6613 | if (f->fx_r_type == BFD_RELOC_LO16 | |
6614 | && f->fx_addsy == l->fixp->fx_addsy | |
6615 | && f->fx_offset == l->fixp->fx_offset | |
6616 | && (pass == 1 | |
6617 | || prev == NULL | |
6618 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
6619 | || prev->fx_addsy != f->fx_addsy | |
6620 | || prev->fx_offset != f->fx_offset)) | |
6621 | { | |
6622 | fixS **pf; | |
867a58b3 | 6623 | |
9b61d62b ILT |
6624 | /* Move l->fixp before f. */ |
6625 | for (pf = &seginfo->fix_root; | |
6626 | *pf != l->fixp; | |
6627 | pf = &(*pf)->fx_next) | |
6628 | assert (*pf != NULL); | |
867a58b3 | 6629 | |
9b61d62b | 6630 | *pf = l->fixp->fx_next; |
867a58b3 | 6631 | |
9b61d62b ILT |
6632 | l->fixp->fx_next = f; |
6633 | if (prev == NULL) | |
6634 | seginfo->fix_root = l->fixp; | |
6635 | else | |
6636 | prev->fx_next = l->fixp; | |
867a58b3 | 6637 | |
9b61d62b ILT |
6638 | break; |
6639 | } | |
6640 | ||
6641 | prev = f; | |
867a58b3 ILT |
6642 | } |
6643 | ||
9b61d62b ILT |
6644 | if (f != NULL) |
6645 | break; | |
867a58b3 | 6646 | |
9b61d62b ILT |
6647 | if (pass == 1) |
6648 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
6649 | "Unmatched %%hi reloc"); | |
6650 | } | |
867a58b3 ILT |
6651 | } |
6652 | } | |
6653 | ||
1c803e52 ILT |
6654 | /* When generating embedded PIC code we need to use a special |
6655 | relocation to represent the difference of two symbols in the .text | |
6656 | section (switch tables use a difference of this sort). See | |
6657 | include/coff/mips.h for details. This macro checks whether this | |
6658 | fixup requires the special reloc. */ | |
6659 | #define SWITCH_TABLE(fixp) \ | |
6660 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
6661 | && (fixp)->fx_addsy != NULL \ | |
6662 | && (fixp)->fx_subsy != NULL \ | |
6663 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
6664 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
6665 | ||
5b63f465 | 6666 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
6667 | relocations, in case the linker has to relax a call. We also need |
6668 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
6669 | |
6670 | /*ARGSUSED*/ | |
6671 | int | |
6672 | mips_force_relocation (fixp) | |
6673 | fixS *fixp; | |
6674 | { | |
1c803e52 | 6675 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
6676 | && (fixp->fx_pcrel |
6677 | || SWITCH_TABLE (fixp) | |
6678 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
6679 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
6680 | } |
6681 | ||
6682 | /* Apply a fixup to the object file. */ | |
6683 | ||
3d3c5039 ILT |
6684 | int |
6685 | md_apply_fix (fixP, valueP) | |
6686 | fixS *fixP; | |
918692a5 | 6687 | valueT *valueP; |
3d3c5039 | 6688 | { |
670a50eb ILT |
6689 | unsigned char *buf; |
6690 | long insn, value; | |
3d3c5039 | 6691 | |
bf39474f ILT |
6692 | assert (fixP->fx_size == 4 |
6693 | || fixP->fx_r_type == BFD_RELOC_16 | |
6694 | || fixP->fx_r_type == BFD_RELOC_64); | |
3d3c5039 | 6695 | |
670a50eb ILT |
6696 | value = *valueP; |
6697 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ | |
3d3c5039 | 6698 | |
5b63f465 ILT |
6699 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
6700 | fixP->fx_done = 1; | |
6701 | ||
670a50eb ILT |
6702 | switch (fixP->fx_r_type) |
6703 | { | |
3d3c5039 ILT |
6704 | case BFD_RELOC_MIPS_JMP: |
6705 | case BFD_RELOC_HI16: | |
6706 | case BFD_RELOC_HI16_S: | |
670a50eb | 6707 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
6708 | case BFD_RELOC_MIPS_LITERAL: |
6709 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
6710 | case BFD_RELOC_MIPS_GOT16: |
6711 | case BFD_RELOC_MIPS_GPREL32: | |
fb251650 ILT |
6712 | case BFD_RELOC_MIPS_GOT_HI16: |
6713 | case BFD_RELOC_MIPS_GOT_LO16: | |
6714 | case BFD_RELOC_MIPS_CALL_HI16: | |
6715 | case BFD_RELOC_MIPS_CALL_LO16: | |
ecd4ca1c | 6716 | if (fixP->fx_pcrel) |
7b777690 ILT |
6717 | as_bad_where (fixP->fx_file, fixP->fx_line, |
6718 | "Invalid PC relative reloc"); | |
670a50eb | 6719 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 6720 | break; |
3d3c5039 | 6721 | |
ecd4ca1c ILT |
6722 | case BFD_RELOC_PCREL_HI16_S: |
6723 | /* The addend for this is tricky if it is internal, so we just | |
6724 | do everything here rather than in bfd_perform_relocation. */ | |
6725 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
6726 | { | |
6727 | /* For an external symbol adjust by the address to make it | |
6728 | pcrel_offset. We use the address of the RELLO reloc | |
6729 | which follows this one. */ | |
6730 | value += (fixP->fx_next->fx_frag->fr_address | |
6731 | + fixP->fx_next->fx_where); | |
6732 | } | |
6733 | if (value & 0x8000) | |
6734 | value += 0x10000; | |
6735 | value >>= 16; | |
0221ddf7 | 6736 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
ecd4ca1c ILT |
6737 | if (byte_order == BIG_ENDIAN) |
6738 | buf += 2; | |
6739 | md_number_to_chars (buf, value, 2); | |
6740 | break; | |
6741 | ||
6742 | case BFD_RELOC_PCREL_LO16: | |
6743 | /* The addend for this is tricky if it is internal, so we just | |
6744 | do everything here rather than in bfd_perform_relocation. */ | |
6745 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
6746 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 6747 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
ecd4ca1c ILT |
6748 | if (byte_order == BIG_ENDIAN) |
6749 | buf += 2; | |
6750 | md_number_to_chars (buf, value, 2); | |
6751 | break; | |
6752 | ||
bf39474f ILT |
6753 | case BFD_RELOC_64: |
6754 | /* This is handled like BFD_RELOC_32, but we output a sign | |
6755 | extended value if we are only 32 bits. */ | |
6756 | if (fixP->fx_done | |
6757 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
6758 | { | |
6759 | if (8 <= sizeof (valueT)) | |
6760 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
6761 | value, 8); | |
6762 | else | |
6763 | { | |
6764 | long w1, w2; | |
6765 | long hiv; | |
6766 | ||
6767 | w1 = w2 = fixP->fx_where; | |
6768 | if (byte_order == BIG_ENDIAN) | |
6769 | w1 += 4; | |
6770 | else | |
6771 | w2 += 4; | |
6772 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
6773 | if ((value & 0x80000000) != 0) | |
6774 | hiv = 0xffffffff; | |
6775 | else | |
6776 | hiv = 0; | |
6777 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
6778 | } | |
6779 | } | |
6780 | break; | |
6781 | ||
f3645945 ILT |
6782 | case BFD_RELOC_32: |
6783 | /* If we are deleting this reloc entry, we must fill in the | |
6784 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
6785 | resolved when it appears but is later defined. We also need |
6786 | to fill in the value if this is an embedded PIC switch table | |
6787 | entry. */ | |
6788 | if (fixP->fx_done | |
6789 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
6790 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
6791 | value, 4); | |
6792 | break; | |
6793 | ||
49ad0c4c ILT |
6794 | case BFD_RELOC_16: |
6795 | /* If we are deleting this reloc entry, we must fill in the | |
6796 | value now. */ | |
6797 | assert (fixP->fx_size == 2); | |
6798 | if (fixP->fx_done) | |
6799 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
6800 | value, 2); | |
6801 | break; | |
6802 | ||
f3645945 ILT |
6803 | case BFD_RELOC_LO16: |
6804 | /* When handling an embedded PIC switch statement, we can wind | |
6805 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
6806 | if (fixP->fx_done) | |
6807 | { | |
6808 | if (value < -0x8000 || value > 0x7fff) | |
6809 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6810 | "relocation overflow"); | |
0221ddf7 | 6811 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
f3645945 ILT |
6812 | if (byte_order == BIG_ENDIAN) |
6813 | buf += 2; | |
6814 | md_number_to_chars (buf, value, 2); | |
6815 | } | |
6816 | break; | |
6817 | ||
3d3c5039 | 6818 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
6819 | /* |
6820 | * We need to save the bits in the instruction since fixup_segment() | |
6821 | * might be deleting the relocation entry (i.e., a branch within | |
6822 | * the current segment). | |
6823 | */ | |
6824 | if (value & 0x3) | |
7b777690 ILT |
6825 | as_warn_where (fixP->fx_file, fixP->fx_line, |
6826 | "Branch to odd address (%lx)", value); | |
670a50eb | 6827 | value >>= 2; |
670a50eb ILT |
6828 | |
6829 | /* update old instruction data */ | |
6830 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
6831 | switch (byte_order) | |
6832 | { | |
3d3c5039 | 6833 | case LITTLE_ENDIAN: |
670a50eb ILT |
6834 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; |
6835 | break; | |
3d3c5039 ILT |
6836 | |
6837 | case BIG_ENDIAN: | |
670a50eb ILT |
6838 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; |
6839 | break; | |
3d3c5039 ILT |
6840 | |
6841 | default: | |
670a50eb ILT |
6842 | internalError (); |
6843 | return 0; | |
3d3c5039 | 6844 | } |
9da4c5d1 ILT |
6845 | |
6846 | if (value >= -0x8000 && value < 0x8000) | |
6847 | insn |= value & 0xffff; | |
6848 | else | |
6849 | { | |
6850 | /* The branch offset is too large. If this is an | |
6851 | unconditional branch, and we are not generating PIC code, | |
6852 | we can convert it to an absolute jump instruction. */ | |
6853 | if (mips_pic == NO_PIC | |
6854 | && fixP->fx_done | |
6855 | && fixP->fx_frag->fr_address >= text_section->vma | |
6856 | && (fixP->fx_frag->fr_address | |
6857 | < text_section->vma + text_section->_raw_size) | |
6858 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
6859 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
6860 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
6861 | { | |
6862 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
6863 | insn = 0x0c000000; /* jal */ | |
6864 | else | |
6865 | insn = 0x08000000; /* j */ | |
6866 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
6867 | fixP->fx_done = 0; | |
6868 | fixP->fx_addsy = section_symbol (text_section); | |
6869 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
6870 | } | |
6871 | else | |
6872 | { | |
6873 | /* FIXME. It would be possible in principle to handle | |
6874 | conditional branches which overflow. They could be | |
6875 | transformed into a branch around a jump. This would | |
6876 | require setting up variant frags for each different | |
6877 | branch type. The native MIPS assembler attempts to | |
6878 | handle these cases, but it appears to do it | |
6879 | incorrectly. */ | |
6880 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6881 | "Relocation overflow"); | |
6882 | } | |
6883 | } | |
6884 | ||
604633ae | 6885 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 6886 | break; |
3d3c5039 ILT |
6887 | |
6888 | default: | |
670a50eb | 6889 | internalError (); |
3d3c5039 | 6890 | } |
5b63f465 | 6891 | |
670a50eb | 6892 | return 1; |
3d3c5039 ILT |
6893 | } |
6894 | ||
6895 | #if 0 | |
6896 | void | |
670a50eb ILT |
6897 | printInsn (oc) |
6898 | unsigned long oc; | |
3d3c5039 | 6899 | { |
670a50eb ILT |
6900 | const struct mips_opcode *p; |
6901 | int treg, sreg, dreg, shamt; | |
6902 | short imm; | |
6903 | const char *args; | |
6904 | int i; | |
3d3c5039 | 6905 | |
670a50eb ILT |
6906 | for (i = 0; i < NUMOPCODES; ++i) |
6907 | { | |
6908 | p = &mips_opcodes[i]; | |
6909 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
6910 | { | |
6911 | printf ("%08lx %s\t", oc, p->name); | |
6912 | treg = (oc >> 16) & 0x1f; | |
6913 | sreg = (oc >> 21) & 0x1f; | |
6914 | dreg = (oc >> 11) & 0x1f; | |
6915 | shamt = (oc >> 6) & 0x1f; | |
6916 | imm = oc; | |
6917 | for (args = p->args;; ++args) | |
6918 | { | |
6919 | switch (*args) | |
6920 | { | |
3d3c5039 | 6921 | case '\0': |
670a50eb ILT |
6922 | printf ("\n"); |
6923 | break; | |
3d3c5039 ILT |
6924 | |
6925 | case ',': | |
6926 | case '(': | |
6927 | case ')': | |
670a50eb ILT |
6928 | printf ("%c", *args); |
6929 | continue; | |
3d3c5039 ILT |
6930 | |
6931 | case 'r': | |
670a50eb ILT |
6932 | assert (treg == sreg); |
6933 | printf ("$%d,$%d", treg, sreg); | |
6934 | continue; | |
3d3c5039 ILT |
6935 | |
6936 | case 'd': | |
918692a5 | 6937 | case 'G': |
670a50eb ILT |
6938 | printf ("$%d", dreg); |
6939 | continue; | |
3d3c5039 ILT |
6940 | |
6941 | case 't': | |
918692a5 | 6942 | case 'E': |
670a50eb ILT |
6943 | printf ("$%d", treg); |
6944 | continue; | |
3d3c5039 | 6945 | |
9226253a ILT |
6946 | case 'k': |
6947 | printf ("0x%x", treg); | |
6948 | continue; | |
6949 | ||
3d3c5039 ILT |
6950 | case 'b': |
6951 | case 's': | |
670a50eb ILT |
6952 | printf ("$%d", sreg); |
6953 | continue; | |
3d3c5039 ILT |
6954 | |
6955 | case 'a': | |
670a50eb ILT |
6956 | printf ("0x%08lx", oc & 0x1ffffff); |
6957 | continue; | |
3d3c5039 ILT |
6958 | |
6959 | case 'i': | |
6960 | case 'j': | |
6961 | case 'o': | |
6962 | case 'u': | |
670a50eb ILT |
6963 | printf ("%d", imm); |
6964 | continue; | |
3d3c5039 ILT |
6965 | |
6966 | case '<': | |
56c96faa | 6967 | case '>': |
670a50eb ILT |
6968 | printf ("$%d", shamt); |
6969 | continue; | |
3d3c5039 ILT |
6970 | |
6971 | default: | |
670a50eb | 6972 | internalError (); |
3d3c5039 | 6973 | } |
670a50eb | 6974 | break; |
3d3c5039 | 6975 | } |
670a50eb | 6976 | return; |
3d3c5039 ILT |
6977 | } |
6978 | } | |
670a50eb | 6979 | printf ("%08lx UNDEFINED\n", oc); |
3d3c5039 ILT |
6980 | } |
6981 | #endif | |
6982 | ||
6983 | static symbolS * | |
6984 | get_symbol () | |
6985 | { | |
670a50eb ILT |
6986 | int c; |
6987 | char *name; | |
6988 | symbolS *p; | |
6989 | ||
6990 | name = input_line_pointer; | |
6991 | c = get_symbol_end (); | |
6992 | p = (symbolS *) symbol_find_or_make (name); | |
6993 | *input_line_pointer = c; | |
6994 | return p; | |
3d3c5039 ILT |
6995 | } |
6996 | ||
becfe05e ILT |
6997 | /* Align the current frag to a given power of two. The MIPS assembler |
6998 | also automatically adjusts any preceding label. */ | |
6999 | ||
7000 | static void | |
23dc1ae3 | 7001 | mips_align (to, fill, label) |
becfe05e ILT |
7002 | int to; |
7003 | int fill; | |
23dc1ae3 | 7004 | symbolS *label; |
becfe05e ILT |
7005 | { |
7006 | mips_emit_delays (); | |
7007 | frag_align (to, fill); | |
7008 | record_alignment (now_seg, to); | |
23dc1ae3 | 7009 | if (label != NULL) |
becfe05e | 7010 | { |
23dc1ae3 ILT |
7011 | assert (S_GET_SEGMENT (label) == now_seg); |
7012 | label->sy_frag = frag_now; | |
7013 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
7014 | } |
7015 | } | |
7016 | ||
7017 | /* Align to a given power of two. .align 0 turns off the automatic | |
7018 | alignment used by the data creating pseudo-ops. */ | |
7019 | ||
3d3c5039 ILT |
7020 | static void |
7021 | s_align (x) | |
7022 | int x; | |
7023 | { | |
670a50eb ILT |
7024 | register int temp; |
7025 | register long temp_fill; | |
7026 | long max_alignment = 15; | |
3d3c5039 | 7027 | |
670a50eb | 7028 | /* |
3d3c5039 ILT |
7029 | |
7030 | o Note that the assembler pulls down any immediately preceeding label | |
7031 | to the aligned address. | |
7032 | o It's not documented but auto alignment is reinstated by | |
7033 | a .align pseudo instruction. | |
7034 | o Note also that after auto alignment is turned off the mips assembler | |
7035 | issues an error on attempt to assemble an improperly aligned data item. | |
7036 | We don't. | |
7037 | ||
7038 | */ | |
7039 | ||
670a50eb ILT |
7040 | temp = get_absolute_expression (); |
7041 | if (temp > max_alignment) | |
7042 | as_bad ("Alignment too large: %d. assumed.", temp = max_alignment); | |
7043 | else if (temp < 0) | |
7044 | { | |
7045 | as_warn ("Alignment negative: 0 assumed."); | |
7046 | temp = 0; | |
7047 | } | |
7048 | if (*input_line_pointer == ',') | |
7049 | { | |
7050 | input_line_pointer++; | |
7051 | temp_fill = get_absolute_expression (); | |
7052 | } | |
7053 | else | |
7054 | temp_fill = 0; | |
7055 | if (temp) | |
7056 | { | |
7057 | auto_align = 1; | |
23dc1ae3 | 7058 | mips_align (temp, (int) temp_fill, insn_label); |
3d3c5039 | 7059 | } |
670a50eb ILT |
7060 | else |
7061 | { | |
7062 | auto_align = 0; | |
3d3c5039 ILT |
7063 | } |
7064 | ||
670a50eb | 7065 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
7066 | } |
7067 | ||
739708fa KR |
7068 | void |
7069 | mips_flush_pending_output () | |
becfe05e ILT |
7070 | { |
7071 | mips_emit_delays (); | |
1849d646 | 7072 | insn_label = NULL; |
becfe05e ILT |
7073 | } |
7074 | ||
3d3c5039 ILT |
7075 | static void |
7076 | s_change_sec (sec) | |
7077 | int sec; | |
7078 | { | |
88225433 | 7079 | segT seg; |
becfe05e | 7080 | |
5b63f465 ILT |
7081 | /* When generating embedded PIC code, we only use the .text, .lit8, |
7082 | .sdata and .sbss sections. We change the .data and .rdata | |
7083 | pseudo-ops to use .sdata. */ | |
7084 | if (mips_pic == EMBEDDED_PIC | |
7085 | && (sec == 'd' || sec == 'r')) | |
7086 | sec = 's'; | |
7087 | ||
becfe05e | 7088 | mips_emit_delays (); |
670a50eb ILT |
7089 | switch (sec) |
7090 | { | |
3d3c5039 | 7091 | case 't': |
604633ae | 7092 | s_text (0); |
670a50eb | 7093 | break; |
3d3c5039 | 7094 | case 'd': |
604633ae | 7095 | s_data (0); |
670a50eb | 7096 | break; |
3d3c5039 | 7097 | case 'b': |
670a50eb | 7098 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
7099 | demand_empty_rest_of_line (); |
7100 | break; | |
88225433 ILT |
7101 | |
7102 | case 'r': | |
1dc1e798 KR |
7103 | if (USE_GLOBAL_POINTER_OPT) |
7104 | { | |
7105 | seg = subseg_new (RDATA_SECTION_NAME, | |
7106 | (subsegT) get_absolute_expression ()); | |
7107 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
7108 | { | |
7109 | bfd_set_section_flags (stdoutput, seg, | |
7110 | (SEC_ALLOC | |
7111 | | SEC_LOAD | |
7112 | | SEC_READONLY | |
7113 | | SEC_RELOC | |
7114 | | SEC_DATA)); | |
7115 | bfd_set_section_alignment (stdoutput, seg, 4); | |
7116 | } | |
7117 | demand_empty_rest_of_line (); | |
7118 | } | |
7119 | else | |
7120 | { | |
7121 | as_bad ("No read only data section in this object file format"); | |
7122 | demand_empty_rest_of_line (); | |
7123 | return; | |
7124 | } | |
88225433 | 7125 | break; |
88225433 ILT |
7126 | |
7127 | case 's': | |
1dc1e798 KR |
7128 | if (USE_GLOBAL_POINTER_OPT) |
7129 | { | |
7130 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
7131 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
7132 | { | |
7133 | bfd_set_section_flags (stdoutput, seg, | |
7134 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
7135 | | SEC_DATA); | |
7136 | bfd_set_section_alignment (stdoutput, seg, 4); | |
7137 | } | |
7138 | demand_empty_rest_of_line (); | |
7139 | break; | |
7140 | } | |
7141 | else | |
7142 | { | |
7143 | as_bad ("Global pointers not supported; recompile -G 0"); | |
7144 | demand_empty_rest_of_line (); | |
7145 | return; | |
7146 | } | |
3d3c5039 | 7147 | } |
88225433 | 7148 | |
670a50eb | 7149 | auto_align = 1; |
3d3c5039 ILT |
7150 | } |
7151 | ||
739708fa KR |
7152 | void |
7153 | mips_enable_auto_align () | |
9da4c5d1 | 7154 | { |
9da4c5d1 ILT |
7155 | auto_align = 1; |
7156 | } | |
7157 | ||
3d3c5039 ILT |
7158 | static void |
7159 | s_cons (log_size) | |
7160 | int log_size; | |
7161 | { | |
23dc1ae3 ILT |
7162 | symbolS *label; |
7163 | ||
7164 | label = insn_label; | |
becfe05e | 7165 | mips_emit_delays (); |
670a50eb | 7166 | if (log_size > 0 && auto_align) |
23dc1ae3 | 7167 | mips_align (log_size, 0, label); |
1849d646 | 7168 | insn_label = NULL; |
670a50eb | 7169 | cons (1 << log_size); |
3d3c5039 ILT |
7170 | } |
7171 | ||
3d3c5039 | 7172 | static void |
becfe05e ILT |
7173 | s_float_cons (type) |
7174 | int type; | |
3d3c5039 | 7175 | { |
23dc1ae3 ILT |
7176 | symbolS *label; |
7177 | ||
7178 | label = insn_label; | |
7179 | ||
becfe05e | 7180 | mips_emit_delays (); |
670a50eb ILT |
7181 | |
7182 | if (auto_align) | |
becfe05e | 7183 | if (type == 'd') |
23dc1ae3 | 7184 | mips_align (3, 0, label); |
670a50eb | 7185 | else |
23dc1ae3 | 7186 | mips_align (2, 0, label); |
670a50eb | 7187 | |
1849d646 ILT |
7188 | insn_label = NULL; |
7189 | ||
becfe05e | 7190 | float_cons (type); |
3d3c5039 ILT |
7191 | } |
7192 | ||
c1444ec4 ILT |
7193 | /* Handle .globl. We need to override it because on Irix 5 you are |
7194 | permitted to say | |
7195 | .globl foo .text | |
7196 | where foo is an undefined symbol, to mean that foo should be | |
7197 | considered to be the address of a function. */ | |
7198 | ||
7199 | static void | |
7200 | s_mips_globl (x) | |
7201 | int x; | |
7202 | { | |
7203 | char *name; | |
7204 | int c; | |
7205 | symbolS *symbolP; | |
fb251650 | 7206 | flagword flag; |
c1444ec4 ILT |
7207 | |
7208 | name = input_line_pointer; | |
7209 | c = get_symbol_end (); | |
7210 | symbolP = symbol_find_or_make (name); | |
7211 | *input_line_pointer = c; | |
7212 | SKIP_WHITESPACE (); | |
fb251650 ILT |
7213 | |
7214 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
7215 | being a function is apparently labelled as being an object. */ | |
7216 | flag = BSF_OBJECT; | |
7217 | ||
c1444ec4 ILT |
7218 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
7219 | { | |
7220 | char *secname; | |
7221 | asection *sec; | |
7222 | ||
7223 | secname = input_line_pointer; | |
7224 | c = get_symbol_end (); | |
7225 | sec = bfd_get_section_by_name (stdoutput, secname); | |
7226 | if (sec == NULL) | |
7227 | as_bad ("%s: no such section", secname); | |
7228 | *input_line_pointer = c; | |
7229 | ||
7230 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
fb251650 | 7231 | flag = BSF_FUNCTION; |
c1444ec4 ILT |
7232 | } |
7233 | ||
fb251650 ILT |
7234 | symbolP->bsym->flags |= flag; |
7235 | ||
c1444ec4 ILT |
7236 | S_SET_EXTERNAL (symbolP); |
7237 | demand_empty_rest_of_line (); | |
7238 | } | |
7239 | ||
3d3c5039 ILT |
7240 | static void |
7241 | s_option (x) | |
7242 | int x; | |
7243 | { | |
dd3f1f76 ILT |
7244 | char *opt; |
7245 | char c; | |
7246 | ||
7247 | opt = input_line_pointer; | |
7248 | c = get_symbol_end (); | |
7249 | ||
dd3f1f76 | 7250 | if (*opt == 'O') |
9226253a ILT |
7251 | { |
7252 | /* FIXME: What does this mean? */ | |
7253 | } | |
dd3f1f76 | 7254 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 7255 | { |
d9aba805 | 7256 | int i; |
42562568 | 7257 | |
d9aba805 ILT |
7258 | i = atoi (opt + 3); |
7259 | if (i == 0) | |
7260 | mips_pic = NO_PIC; | |
7261 | else if (i == 2) | |
7262 | mips_pic = SVR4_PIC; | |
7263 | else | |
7264 | as_bad (".option pic%d not supported", i); | |
7265 | ||
1dc1e798 | 7266 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
42562568 ILT |
7267 | { |
7268 | if (g_switch_seen && g_switch_value != 0) | |
d9aba805 | 7269 | as_warn ("-G may not be used with SVR4 PIC code"); |
42562568 ILT |
7270 | g_switch_value = 0; |
7271 | bfd_set_gp_size (stdoutput, 0); | |
7272 | } | |
9226253a | 7273 | } |
dd3f1f76 ILT |
7274 | else |
7275 | as_warn ("Unrecognized option \"%s\"", opt); | |
7276 | ||
7277 | *input_line_pointer = c; | |
670a50eb | 7278 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
7279 | } |
7280 | ||
7281 | static void | |
7282 | s_mipsset (x) | |
7283 | int x; | |
7284 | { | |
670a50eb ILT |
7285 | char *name = input_line_pointer, ch; |
7286 | ||
7287 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
7288 | input_line_pointer++; | |
7289 | ch = *input_line_pointer; | |
7290 | *input_line_pointer = '\0'; | |
7291 | ||
7292 | if (strcmp (name, "reorder") == 0) | |
7293 | { | |
4e95866e ILT |
7294 | if (mips_noreorder) |
7295 | { | |
7296 | prev_insn_unreordered = 1; | |
7297 | prev_prev_insn_unreordered = 1; | |
7298 | } | |
670a50eb ILT |
7299 | mips_noreorder = 0; |
7300 | } | |
7301 | else if (strcmp (name, "noreorder") == 0) | |
7302 | { | |
becfe05e | 7303 | mips_emit_delays (); |
670a50eb | 7304 | mips_noreorder = 1; |
0dd2d296 | 7305 | mips_any_noreorder = 1; |
670a50eb ILT |
7306 | } |
7307 | else if (strcmp (name, "at") == 0) | |
7308 | { | |
7309 | mips_noat = 0; | |
7310 | } | |
7311 | else if (strcmp (name, "noat") == 0) | |
7312 | { | |
7313 | mips_noat = 1; | |
3d3c5039 | 7314 | } |
670a50eb ILT |
7315 | else if (strcmp (name, "macro") == 0) |
7316 | { | |
7317 | mips_warn_about_macros = 0; | |
7318 | } | |
7319 | else if (strcmp (name, "nomacro") == 0) | |
7320 | { | |
7321 | if (mips_noreorder == 0) | |
7322 | as_bad ("`noreorder' must be set before `nomacro'"); | |
7323 | mips_warn_about_macros = 1; | |
7324 | } | |
7325 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
7326 | { | |
7327 | mips_nomove = 0; | |
7328 | } | |
7329 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
7330 | { | |
7331 | mips_nomove = 1; | |
7332 | } | |
7333 | else if (strcmp (name, "bopt") == 0) | |
7334 | { | |
7335 | mips_nobopt = 0; | |
7336 | } | |
7337 | else if (strcmp (name, "nobopt") == 0) | |
7338 | { | |
7339 | mips_nobopt = 1; | |
7340 | } | |
1051c97f ILT |
7341 | else if (strncmp (name, "mips", 4) == 0) |
7342 | { | |
7343 | int isa; | |
7344 | ||
7345 | /* Permit the user to change the ISA on the fly. Needless to | |
7346 | say, misuse can cause serious problems. */ | |
7347 | isa = atoi (name + 4); | |
7348 | if (isa == 0) | |
7349 | mips_isa = file_mips_isa; | |
d8a1c247 | 7350 | else if (isa < 1 || isa > 4) |
1051c97f ILT |
7351 | as_bad ("unknown ISA level"); |
7352 | else | |
7353 | mips_isa = isa; | |
7354 | } | |
670a50eb ILT |
7355 | else |
7356 | { | |
7357 | as_warn ("Tried to set unrecognized symbol: %s\n", name); | |
7358 | } | |
7359 | *input_line_pointer = ch; | |
7360 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
7361 | } |
7362 | ||
9226253a ILT |
7363 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
7364 | .option pic2. It means to generate SVR4 PIC calls. */ | |
7365 | ||
7366 | static void | |
7367 | s_abicalls (ignore) | |
7368 | int ignore; | |
7369 | { | |
d9aba805 | 7370 | mips_pic = SVR4_PIC; |
1dc1e798 KR |
7371 | if (USE_GLOBAL_POINTER_OPT) |
7372 | { | |
7373 | if (g_switch_seen && g_switch_value != 0) | |
7374 | as_warn ("-G may not be used with SVR4 PIC code"); | |
7375 | g_switch_value = 0; | |
7376 | } | |
d9aba805 | 7377 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
7378 | demand_empty_rest_of_line (); |
7379 | } | |
7380 | ||
7381 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
7382 | PIC code. It sets the $gp register for the function based on the | |
7383 | function address, which is in the register named in the argument. | |
7384 | This uses a relocation against _gp_disp, which is handled specially | |
7385 | by the linker. The result is: | |
7386 | lui $gp,%hi(_gp_disp) | |
7387 | addiu $gp,$gp,%lo(_gp_disp) | |
7388 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 7389 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
7390 | |
7391 | static void | |
7392 | s_cpload (ignore) | |
7393 | int ignore; | |
7394 | { | |
7395 | expressionS ex; | |
7396 | int icnt = 0; | |
7397 | ||
d9aba805 ILT |
7398 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
7399 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
7400 | { |
7401 | s_ignore (0); | |
7402 | return; | |
7403 | } | |
7404 | ||
7405 | /* .cpload should be a in .set noreorder section. */ | |
7406 | if (mips_noreorder == 0) | |
7407 | as_warn (".cpload not in noreorder section"); | |
7408 | ||
9226253a ILT |
7409 | ex.X_op = O_symbol; |
7410 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
7411 | ex.X_op_symbol = NULL; | |
7412 | ex.X_add_number = 0; | |
7413 | ||
fb251650 ILT |
7414 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
7415 | ex.X_add_symbol->bsym->flags |= BSF_OBJECT; | |
7416 | ||
0dd2d296 ILT |
7417 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
7418 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
7419 | (int) BFD_RELOC_LO16); |
7420 | ||
0dd2d296 ILT |
7421 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
7422 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
7423 | |
7424 | demand_empty_rest_of_line (); | |
7425 | } | |
7426 | ||
7427 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
7428 | offset from $sp. The offset is remembered, and after making a PIC | |
7429 | call $gp is restored from that location. */ | |
7430 | ||
7431 | static void | |
7432 | s_cprestore (ignore) | |
7433 | int ignore; | |
7434 | { | |
7435 | expressionS ex; | |
7436 | int icnt = 0; | |
7437 | ||
d9aba805 ILT |
7438 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
7439 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
7440 | { |
7441 | s_ignore (0); | |
7442 | return; | |
7443 | } | |
7444 | ||
9226253a ILT |
7445 | mips_cprestore_offset = get_absolute_expression (); |
7446 | ||
7447 | ex.X_op = O_constant; | |
7448 | ex.X_add_symbol = NULL; | |
7449 | ex.X_op_symbol = NULL; | |
7450 | ex.X_add_number = mips_cprestore_offset; | |
7451 | ||
0dd2d296 | 7452 | macro_build ((char *) NULL, &icnt, &ex, |
9226253a ILT |
7453 | mips_isa < 3 ? "sw" : "sd", |
7454 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); | |
7455 | ||
7456 | demand_empty_rest_of_line (); | |
7457 | } | |
7458 | ||
0dd2d296 ILT |
7459 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
7460 | code. It generates a 32 bit GP relative reloc. */ | |
7461 | ||
7462 | static void | |
7463 | s_gpword (ignore) | |
7464 | int ignore; | |
7465 | { | |
23dc1ae3 | 7466 | symbolS *label; |
0dd2d296 ILT |
7467 | expressionS ex; |
7468 | char *p; | |
7469 | ||
7470 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 7471 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
7472 | { |
7473 | s_cons (2); | |
7474 | return; | |
7475 | } | |
7476 | ||
23dc1ae3 | 7477 | label = insn_label; |
0dd2d296 ILT |
7478 | mips_emit_delays (); |
7479 | if (auto_align) | |
23dc1ae3 | 7480 | mips_align (2, 0, label); |
0dd2d296 ILT |
7481 | insn_label = NULL; |
7482 | ||
7483 | expression (&ex); | |
7484 | ||
7485 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
7486 | { | |
7487 | as_bad ("Unsupported use of .gpword"); | |
7488 | ignore_rest_of_line (); | |
7489 | } | |
7490 | ||
7491 | p = frag_more (4); | |
7492 | md_number_to_chars (p, (valueT) 0, 4); | |
7493 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
7494 | BFD_RELOC_MIPS_GPREL32); | |
7495 | ||
7496 | demand_empty_rest_of_line (); | |
7497 | } | |
7498 | ||
7499 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
7500 | tables in SVR4 PIC code. */ | |
7501 | ||
7502 | static void | |
7503 | s_cpadd (ignore) | |
7504 | int ignore; | |
7505 | { | |
7506 | int icnt = 0; | |
7507 | int reg; | |
7508 | ||
7509 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 7510 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
7511 | { |
7512 | s_ignore (0); | |
7513 | return; | |
7514 | } | |
7515 | ||
7516 | /* Add $gp to the register named as an argument. */ | |
7517 | reg = tc_get_register (0); | |
7518 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
7519 | mips_isa < 3 ? "addu" : "daddu", | |
7520 | "d,v,t", reg, reg, GP); | |
7521 | ||
7522 | demand_empty_rest_of_line (); | |
7523 | } | |
7524 | ||
9226253a | 7525 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
7526 | to parse .frame. The argument is non-zero if this is the frame |
7527 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 7528 | |
3d3c5039 | 7529 | int |
0dd2d296 ILT |
7530 | tc_get_register (frame) |
7531 | int frame; | |
3d3c5039 ILT |
7532 | { |
7533 | int reg; | |
7534 | ||
7535 | SKIP_WHITESPACE (); | |
7536 | if (*input_line_pointer++ != '$') | |
7537 | { | |
7538 | as_warn ("expected `$'"); | |
0dd2d296 | 7539 | reg = 0; |
3d3c5039 | 7540 | } |
0dd2d296 | 7541 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
7542 | { |
7543 | reg = get_absolute_expression (); | |
7544 | if (reg < 0 || reg >= 32) | |
7545 | { | |
7546 | as_warn ("Bad register number"); | |
7547 | reg = 0; | |
7548 | } | |
7549 | } | |
7550 | else | |
7551 | { | |
7552 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 7553 | reg = FP; |
3d3c5039 | 7554 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 7555 | reg = SP; |
3d3c5039 | 7556 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 7557 | reg = GP; |
3d3c5039 | 7558 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 7559 | reg = AT; |
3d3c5039 ILT |
7560 | else |
7561 | { | |
7562 | as_warn ("Unrecognized register name"); | |
0dd2d296 | 7563 | reg = 0; |
3d3c5039 ILT |
7564 | } |
7565 | input_line_pointer += 2; | |
7566 | } | |
0dd2d296 ILT |
7567 | if (frame) |
7568 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
7569 | return reg; |
7570 | } | |
7571 | ||
0dd2d296 ILT |
7572 | valueT |
7573 | md_section_align (seg, addr) | |
7574 | asection *seg; | |
7575 | valueT addr; | |
7576 | { | |
7577 | int align = bfd_get_section_alignment (stdoutput, seg); | |
7578 | ||
cf32394d ILT |
7579 | #ifdef OBJ_ELF |
7580 | /* We don't need to align ELF sections to the full alignment. | |
7581 | However, Irix 5 may prefer that we align them at least to a 16 | |
7582 | byte boundary. */ | |
7583 | if (align > 16) | |
7584 | align = 16; | |
10a14e36 | 7585 | #endif |
cf32394d ILT |
7586 | |
7587 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
0dd2d296 ILT |
7588 | } |
7589 | ||
d8a1c247 KR |
7590 | /* Utility routine, called from above as well. If called while the |
7591 | input file is still being read, it's only an approximation. (For | |
7592 | example, a symbol may later become defined which appeared to be | |
7593 | undefined earlier.) */ | |
22ba90ce ILT |
7594 | |
7595 | static int | |
7596 | nopic_need_relax (sym) | |
d8a1c247 KR |
7597 | symbolS *sym; |
7598 | { | |
7599 | if (sym == 0) | |
7600 | return 0; | |
7601 | ||
1dc1e798 KR |
7602 | if (USE_GLOBAL_POINTER_OPT) |
7603 | { | |
7604 | const char *symname; | |
7605 | int change; | |
7606 | ||
7607 | /* Find out whether this symbol can be referenced off the GP | |
7608 | register. It can be if it is smaller than the -G size or if | |
7609 | it is in the .sdata or .sbss section. Certain symbols can | |
7610 | not be referenced off the GP, although it appears as though | |
7611 | they can. */ | |
7612 | symname = S_GET_NAME (sym); | |
7613 | if (symname != (const char *) NULL | |
7614 | && (strcmp (symname, "eprol") == 0 | |
7615 | || strcmp (symname, "etext") == 0 | |
7616 | || strcmp (symname, "_gp") == 0 | |
7617 | || strcmp (symname, "edata") == 0 | |
7618 | || strcmp (symname, "_fbss") == 0 | |
7619 | || strcmp (symname, "_fdata") == 0 | |
7620 | || strcmp (symname, "_ftext") == 0 | |
7621 | || strcmp (symname, "end") == 0 | |
7622 | || strcmp (symname, "_gp_disp") == 0)) | |
7623 | change = 1; | |
7624 | else if (! S_IS_DEFINED (sym) | |
c625fc23 JSC |
7625 | && (0 |
7626 | #ifndef NO_ECOFF_DEBUGGING | |
7627 | || (sym->ecoff_extern_size != 0 | |
7628 | && sym->ecoff_extern_size <= g_switch_value) | |
7629 | #endif | |
1dc1e798 KR |
7630 | || (S_GET_VALUE (sym) != 0 |
7631 | && S_GET_VALUE (sym) <= g_switch_value))) | |
7632 | change = 0; | |
7633 | else | |
7634 | { | |
7635 | const char *segname; | |
d8a1c247 | 7636 | |
1dc1e798 KR |
7637 | segname = segment_name (S_GET_SEGMENT (sym)); |
7638 | assert (strcmp (segname, ".lit8") != 0 | |
7639 | && strcmp (segname, ".lit4") != 0); | |
7640 | change = (strcmp (segname, ".sdata") != 0 | |
7641 | && strcmp (segname, ".sbss") != 0); | |
7642 | } | |
7643 | return change; | |
7644 | } | |
7645 | else | |
7646 | /* We are not optimizing for the GP register. */ | |
7647 | return 1; | |
d8a1c247 KR |
7648 | } |
7649 | ||
22ba90ce ILT |
7650 | /* Estimate the size of a frag before relaxing. We are not really |
7651 | relaxing here, and the final size is encoded in the subtype | |
7652 | information. */ | |
7653 | ||
0dd2d296 ILT |
7654 | /*ARGSUSED*/ |
7655 | int | |
7656 | md_estimate_size_before_relax (fragp, segtype) | |
7657 | fragS *fragp; | |
7658 | asection *segtype; | |
7659 | { | |
7660 | int change; | |
7661 | ||
d9aba805 | 7662 | if (mips_pic == NO_PIC) |
0dd2d296 | 7663 | { |
d8a1c247 | 7664 | change = nopic_need_relax (fragp->fr_symbol); |
0dd2d296 | 7665 | } |
d9aba805 | 7666 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
7667 | { |
7668 | asection *symsec = fragp->fr_symbol->bsym->section; | |
7669 | ||
7670 | /* This must duplicate the test in adjust_reloc_syms. */ | |
7671 | change = (symsec != &bfd_und_section | |
7672 | && symsec != &bfd_abs_section | |
7673 | && ! bfd_is_com_section (symsec)); | |
7674 | } | |
d9aba805 ILT |
7675 | else |
7676 | abort (); | |
0dd2d296 ILT |
7677 | |
7678 | if (change) | |
7679 | { | |
7680 | /* Record the offset to the first reloc in the fr_opcode field. | |
7681 | This lets md_convert_frag and tc_gen_reloc know that the code | |
7682 | must be expanded. */ | |
7683 | fragp->fr_opcode = (fragp->fr_literal | |
7684 | + fragp->fr_fix | |
7685 | - RELAX_OLD (fragp->fr_subtype) | |
7686 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
7687 | /* FIXME: This really needs as_warn_where. */ | |
7688 | if (RELAX_WARN (fragp->fr_subtype)) | |
7689 | as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\""); | |
7690 | } | |
7691 | ||
7692 | if (! change) | |
7693 | return 0; | |
7694 | else | |
7695 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
7696 | } | |
7697 | ||
7698 | /* Translate internal representation of relocation info to BFD target | |
7699 | format. */ | |
7700 | ||
7701 | arelent ** | |
3d3c5039 ILT |
7702 | tc_gen_reloc (section, fixp) |
7703 | asection *section; | |
7704 | fixS *fixp; | |
7705 | { | |
0dd2d296 | 7706 | static arelent *retval[4]; |
3d3c5039 | 7707 | arelent *reloc; |
a8aed9dd | 7708 | bfd_reloc_code_real_type code; |
3d3c5039 | 7709 | |
0dd2d296 ILT |
7710 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
7711 | retval[1] = NULL; | |
3d3c5039 ILT |
7712 | |
7713 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
7714 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
7715 | |
7716 | if (mips_pic == EMBEDDED_PIC | |
7717 | && SWITCH_TABLE (fixp)) | |
7718 | { | |
7719 | /* For a switch table entry we use a special reloc. The addend | |
7720 | is actually the difference between the reloc address and the | |
7721 | subtrahend. */ | |
7722 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
1dc1e798 KR |
7723 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
7724 | as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc"); | |
1c803e52 ILT |
7725 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
7726 | } | |
ecd4ca1c ILT |
7727 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
7728 | { | |
7729 | /* We use a special addend for an internal RELLO reloc. */ | |
7730 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
7731 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
7732 | else | |
7733 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
7734 | } | |
7735 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
7736 | { | |
7737 | assert (fixp->fx_next != NULL | |
7738 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
7739 | /* We use a special addend for an internal RELHI reloc. The | |
7740 | reloc is relative to the RELLO; adjust the addend | |
7741 | accordingly. */ | |
7742 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
7743 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
7744 | + fixp->fx_next->fx_where | |
7745 | - S_GET_VALUE (fixp->fx_subsy)); | |
7746 | else | |
7747 | reloc->addend = (fixp->fx_addnumber | |
7748 | + fixp->fx_next->fx_frag->fr_address | |
7749 | + fixp->fx_next->fx_where); | |
7750 | } | |
1c803e52 | 7751 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
7752 | reloc->addend = fixp->fx_addnumber; |
7753 | else | |
5b63f465 | 7754 | { |
1dc1e798 KR |
7755 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
7756 | /* A gruesome hack which is a result of the gruesome gas reloc | |
7757 | handling. */ | |
7758 | reloc->addend = reloc->address; | |
7759 | else | |
7760 | reloc->addend = -reloc->address; | |
5b63f465 | 7761 | } |
0dd2d296 ILT |
7762 | |
7763 | /* If this is a variant frag, we may need to adjust the existing | |
7764 | reloc and generate a new one. */ | |
7765 | if (fixp->fx_frag->fr_opcode != NULL | |
7766 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
7767 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
fb251650 ILT |
7768 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
7769 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
7770 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
7771 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
7772 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
0dd2d296 ILT |
7773 | { |
7774 | arelent *reloc2; | |
7775 | ||
7776 | /* If this is not the last reloc in this frag, then we have two | |
fb251650 ILT |
7777 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
7778 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
7779 | the second one handle all of them. */ | |
0dd2d296 ILT |
7780 | if (fixp->fx_next != NULL |
7781 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
7782 | { | |
fb251650 ILT |
7783 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
7784 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
7785 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
7786 | && (fixp->fx_next->fx_r_type | |
7787 | == BFD_RELOC_MIPS_GOT_LO16)) | |
7788 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
7789 | && (fixp->fx_next->fx_r_type | |
7790 | == BFD_RELOC_MIPS_CALL_LO16))); | |
0dd2d296 ILT |
7791 | retval[0] = NULL; |
7792 | return retval; | |
7793 | } | |
7794 | ||
7795 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
7796 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
7797 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
7798 | retval[2] = NULL; | |
7799 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
7800 | reloc2->address = (reloc->address | |
7801 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
7802 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
7803 | reloc2->addend = fixp->fx_addnumber; | |
7804 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
7805 | assert (reloc2->howto != NULL); | |
7806 | ||
7807 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
7808 | { | |
7809 | arelent *reloc3; | |
7810 | ||
7811 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
7812 | retval[3] = NULL; | |
7813 | *reloc3 = *reloc2; | |
7814 | reloc3->address += 4; | |
7815 | } | |
7816 | ||
d9aba805 | 7817 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
7818 | { |
7819 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
7820 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
7821 | } | |
d9aba805 | 7822 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 7823 | { |
fb251650 | 7824 | switch (fixp->fx_r_type) |
0dd2d296 | 7825 | { |
fb251650 ILT |
7826 | default: |
7827 | abort (); | |
7828 | case BFD_RELOC_MIPS_GOT16: | |
7829 | break; | |
7830 | case BFD_RELOC_MIPS_CALL16: | |
7831 | case BFD_RELOC_MIPS_GOT_LO16: | |
7832 | case BFD_RELOC_MIPS_CALL_LO16: | |
0dd2d296 | 7833 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
fb251650 | 7834 | break; |
0dd2d296 ILT |
7835 | } |
7836 | } | |
d9aba805 ILT |
7837 | else |
7838 | abort (); | |
0dd2d296 ILT |
7839 | } |
7840 | ||
a8aed9dd ILT |
7841 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that |
7842 | fixup_segment converted a non-PC relative reloc into a PC | |
7843 | relative reloc. In such a case, we need to convert the reloc | |
7844 | code. */ | |
7845 | code = fixp->fx_r_type; | |
7846 | if (fixp->fx_pcrel) | |
7847 | { | |
7848 | switch (code) | |
7849 | { | |
7850 | case BFD_RELOC_8: | |
7851 | code = BFD_RELOC_8_PCREL; | |
7852 | break; | |
7853 | case BFD_RELOC_16: | |
7854 | code = BFD_RELOC_16_PCREL; | |
7855 | break; | |
7856 | case BFD_RELOC_32: | |
7857 | code = BFD_RELOC_32_PCREL; | |
7858 | break; | |
bf39474f ILT |
7859 | case BFD_RELOC_64: |
7860 | code = BFD_RELOC_64_PCREL; | |
7861 | break; | |
a8aed9dd ILT |
7862 | case BFD_RELOC_8_PCREL: |
7863 | case BFD_RELOC_16_PCREL: | |
7864 | case BFD_RELOC_32_PCREL: | |
bf39474f | 7865 | case BFD_RELOC_64_PCREL: |
a8aed9dd | 7866 | case BFD_RELOC_16_PCREL_S2: |
97aca1bc ILT |
7867 | case BFD_RELOC_PCREL_HI16_S: |
7868 | case BFD_RELOC_PCREL_LO16: | |
a8aed9dd ILT |
7869 | break; |
7870 | default: | |
7871 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
7872 | "Cannot make %s relocation PC relative", | |
7873 | bfd_get_reloc_code_name (code)); | |
7874 | } | |
7875 | } | |
7876 | ||
d9aba805 ILT |
7877 | /* To support a PC relative reloc when generating embedded PIC code |
7878 | for ECOFF, we use a Cygnus extension. We check for that here to | |
7879 | make sure that we don't let such a reloc escape normally. */ | |
1dc1e798 | 7880 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
a8aed9dd | 7881 | && code == BFD_RELOC_16_PCREL_S2 |
d9aba805 ILT |
7882 | && mips_pic != EMBEDDED_PIC) |
7883 | reloc->howto = NULL; | |
7884 | else | |
a8aed9dd | 7885 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
0dd2d296 | 7886 | |
52aa70b5 JW |
7887 | if (reloc->howto == NULL) |
7888 | { | |
7889 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
a8aed9dd ILT |
7890 | "Can not represent %s relocation in this object file format", |
7891 | bfd_get_reloc_code_name (code)); | |
0dd2d296 | 7892 | retval[0] = NULL; |
52aa70b5 | 7893 | } |
3d3c5039 | 7894 | |
0dd2d296 | 7895 | return retval; |
3d3c5039 ILT |
7896 | } |
7897 | ||
0dd2d296 ILT |
7898 | /* Convert a machine dependent frag. */ |
7899 | ||
7900 | void | |
7901 | md_convert_frag (abfd, asec, fragp) | |
7902 | bfd *abfd; | |
7903 | segT asec; | |
7904 | fragS *fragp; | |
3d3c5039 | 7905 | { |
0dd2d296 ILT |
7906 | int old, new; |
7907 | char *fixptr; | |
3d3c5039 | 7908 | |
0dd2d296 ILT |
7909 | if (fragp->fr_opcode == NULL) |
7910 | return; | |
3d3c5039 | 7911 | |
0dd2d296 ILT |
7912 | old = RELAX_OLD (fragp->fr_subtype); |
7913 | new = RELAX_NEW (fragp->fr_subtype); | |
7914 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
7915 | ||
7916 | if (new > 0) | |
7917 | memcpy (fixptr - old, fixptr, new); | |
7918 | ||
7919 | fragp->fr_fix += new - old; | |
7920 | } | |
becfe05e ILT |
7921 | |
7922 | /* This function is called whenever a label is defined. It is used | |
7923 | when handling branch delays; if a branch has a label, we assume we | |
7924 | can not move it. */ | |
7925 | ||
7926 | void | |
7927 | mips_define_label (sym) | |
7928 | symbolS *sym; | |
7929 | { | |
7930 | insn_label = sym; | |
7931 | } | |
22ba90ce ILT |
7932 | |
7933 | /* Decide whether a label is local. This is called by LOCAL_LABEL. | |
7934 | In order to work with gcc when using mips-tfile, we must keep all | |
7935 | local labels. However, in other cases, we want to discard them, | |
7936 | since they are useless. */ | |
7937 | ||
7938 | int | |
7939 | mips_local_label (name) | |
7940 | const char *name; | |
7941 | { | |
c625fc23 | 7942 | #ifndef NO_ECOFF_DEBUGGING |
22ba90ce ILT |
7943 | if (ECOFF_DEBUGGING |
7944 | && mips_debug != 0 | |
7945 | && ! ecoff_debugging_seen) | |
7946 | { | |
7947 | /* We were called with -g, but we didn't see any debugging | |
7948 | information. That may mean that gcc is smuggling debugging | |
7949 | information through to mips-tfile, in which case we must | |
7950 | generate all local labels. */ | |
7951 | return 0; | |
7952 | } | |
c625fc23 | 7953 | #endif |
22ba90ce ILT |
7954 | |
7955 | /* Here it's OK to discard local labels. */ | |
7956 | ||
3af584b4 | 7957 | return name[0] == '$'; |
22ba90ce | 7958 | } |
3d3c5039 | 7959 | \f |
739708fa | 7960 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 7961 | |
0dd2d296 | 7962 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
7963 | |
7964 | void | |
7965 | mips_elf_final_processing () | |
7966 | { | |
87178180 ILT |
7967 | /* Write out the register information. */ |
7968 | if (! mips_64) | |
7969 | { | |
7970 | Elf32_RegInfo s; | |
7971 | ||
7972 | s.ri_gprmask = mips_gprmask; | |
7973 | s.ri_cprmask[0] = mips_cprmask[0]; | |
7974 | s.ri_cprmask[1] = mips_cprmask[1]; | |
7975 | s.ri_cprmask[2] = mips_cprmask[2]; | |
7976 | s.ri_cprmask[3] = mips_cprmask[3]; | |
7977 | /* The gp_value field is set by the MIPS ELF backend. */ | |
7978 | ||
7979 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
7980 | ((Elf32_External_RegInfo *) | |
7981 | mips_regmask_frag)); | |
7982 | } | |
7983 | else | |
7984 | { | |
7985 | Elf64_Internal_RegInfo s; | |
7986 | ||
7987 | s.ri_gprmask = mips_gprmask; | |
7988 | s.ri_pad = 0; | |
7989 | s.ri_cprmask[0] = mips_cprmask[0]; | |
7990 | s.ri_cprmask[1] = mips_cprmask[1]; | |
7991 | s.ri_cprmask[2] = mips_cprmask[2]; | |
7992 | s.ri_cprmask[3] = mips_cprmask[3]; | |
7993 | /* The gp_value field is set by the MIPS ELF backend. */ | |
7994 | ||
7995 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
7996 | ((Elf64_External_RegInfo *) | |
7997 | mips_regmask_frag)); | |
7998 | } | |
0dd2d296 ILT |
7999 | |
8000 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
8001 | sort of BFD interface for this. */ | |
8002 | if (mips_any_noreorder) | |
8003 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 8004 | if (mips_pic != NO_PIC) |
0dd2d296 | 8005 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
8006 | } |
8007 | ||
739708fa | 8008 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
f2a663d3 | 8009 | \f |
3d3c5039 ILT |
8010 | /* These functions should really be defined by the object file format, |
8011 | since they are related to debugging information. However, this | |
8012 | code has to work for the a.out format, which does not define them, | |
8013 | so we provide simple versions here. These don't actually generate | |
8014 | any debugging information, but they do simple checking and someday | |
8015 | somebody may make them useful. */ | |
8016 | ||
670a50eb ILT |
8017 | typedef struct loc |
8018 | { | |
8019 | struct loc *loc_next; | |
8020 | unsigned long loc_fileno; | |
8021 | unsigned long loc_lineno; | |
8022 | unsigned long loc_offset; | |
8023 | unsigned short loc_delta; | |
8024 | unsigned short loc_count; | |
3d3c5039 | 8025 | #if 0 |
670a50eb | 8026 | fragS *loc_frag; |
3d3c5039 | 8027 | #endif |
670a50eb ILT |
8028 | } |
8029 | locS; | |
3d3c5039 | 8030 | |
670a50eb ILT |
8031 | typedef struct proc |
8032 | { | |
3d3c5039 ILT |
8033 | struct proc *proc_next; |
8034 | struct symbol *proc_isym; | |
8035 | struct symbol *proc_end; | |
8036 | unsigned long proc_reg_mask; | |
8037 | unsigned long proc_reg_offset; | |
8038 | unsigned long proc_fpreg_mask; | |
8039 | unsigned long proc_fpreg_offset; | |
8040 | unsigned long proc_frameoffset; | |
8041 | unsigned long proc_framereg; | |
8042 | unsigned long proc_pcreg; | |
8043 | locS *proc_iline; | |
8044 | struct file *proc_file; | |
8045 | int proc_index; | |
670a50eb ILT |
8046 | } |
8047 | procS; | |
3d3c5039 | 8048 | |
670a50eb ILT |
8049 | typedef struct file |
8050 | { | |
3d3c5039 ILT |
8051 | struct file *file_next; |
8052 | unsigned long file_fileno; | |
8053 | struct symbol *file_symbol; | |
8054 | struct symbol *file_end; | |
8055 | struct proc *file_proc; | |
8056 | int file_numprocs; | |
670a50eb ILT |
8057 | } |
8058 | fileS; | |
3d3c5039 ILT |
8059 | |
8060 | static struct obstack proc_frags; | |
8061 | static procS *proc_lastP; | |
8062 | static procS *proc_rootP; | |
8063 | static int numprocs; | |
8064 | ||
8065 | static void | |
8066 | md_obj_begin () | |
8067 | { | |
670a50eb | 8068 | obstack_begin (&proc_frags, 0x2000); |
3d3c5039 ILT |
8069 | } |
8070 | ||
8071 | static void | |
8072 | md_obj_end () | |
8073 | { | |
8074 | /* check for premature end, nesting errors, etc */ | |
8075 | if (proc_lastP && proc_lastP->proc_end == NULL) | |
670a50eb | 8076 | as_warn ("missing `.end' at end of assembly"); |
3d3c5039 ILT |
8077 | } |
8078 | ||
3d3c5039 ILT |
8079 | static long |
8080 | get_number () | |
8081 | { | |
670a50eb ILT |
8082 | int negative = 0; |
8083 | long val = 0; | |
3d3c5039 | 8084 | |
670a50eb ILT |
8085 | if (*input_line_pointer == '-') |
8086 | { | |
8087 | ++input_line_pointer; | |
8088 | negative = 1; | |
3d3c5039 | 8089 | } |
670a50eb ILT |
8090 | if (!isdigit (*input_line_pointer)) |
8091 | as_bad ("Expected simple number."); | |
8092 | if (input_line_pointer[0] == '0') | |
8093 | { | |
8094 | if (input_line_pointer[1] == 'x') | |
8095 | { | |
8096 | input_line_pointer += 2; | |
8097 | while (isxdigit (*input_line_pointer)) | |
8098 | { | |
8099 | val <<= 4; | |
3a762a0b | 8100 | val |= hex_value (*input_line_pointer++); |
3d3c5039 | 8101 | } |
670a50eb ILT |
8102 | return negative ? -val : val; |
8103 | } | |
8104 | else | |
8105 | { | |
8106 | ++input_line_pointer; | |
8107 | while (isdigit (*input_line_pointer)) | |
8108 | { | |
8109 | val <<= 3; | |
8110 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 8111 | } |
670a50eb | 8112 | return negative ? -val : val; |
3d3c5039 ILT |
8113 | } |
8114 | } | |
670a50eb ILT |
8115 | if (!isdigit (*input_line_pointer)) |
8116 | { | |
8117 | printf (" *input_line_pointer == '%c' 0x%02x\n", | |
8118 | *input_line_pointer, *input_line_pointer); | |
8119 | as_warn ("Invalid number"); | |
8120 | return -1; | |
3d3c5039 | 8121 | } |
670a50eb ILT |
8122 | while (isdigit (*input_line_pointer)) |
8123 | { | |
8124 | val *= 10; | |
8125 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 8126 | } |
670a50eb | 8127 | return negative ? -val : val; |
3d3c5039 ILT |
8128 | } |
8129 | ||
8130 | /* The .file directive; just like the usual .file directive, but there | |
8131 | is an initial number which is the ECOFF file index. */ | |
8132 | ||
8133 | static void | |
8134 | s_file (x) | |
8135 | int x; | |
8136 | { | |
670a50eb | 8137 | int line; |
3d3c5039 | 8138 | |
670a50eb | 8139 | line = get_number (); |
9a7d824a | 8140 | s_app_file (0); |
3d3c5039 ILT |
8141 | } |
8142 | ||
8143 | ||
8144 | /* The .end directive. */ | |
8145 | ||
8146 | static void | |
8147 | s_mipsend (x) | |
8148 | int x; | |
8149 | { | |
670a50eb ILT |
8150 | symbolS *p; |
8151 | ||
8152 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
8153 | { | |
8154 | p = get_symbol (); | |
8155 | demand_empty_rest_of_line (); | |
8156 | } | |
8157 | else | |
8158 | p = NULL; | |
8159 | if (now_seg != text_section) | |
8160 | as_warn (".end not in text section"); | |
8161 | if (!proc_lastP) | |
8162 | { | |
8163 | as_warn (".end and no .ent seen yet."); | |
8164 | return; | |
3d3c5039 ILT |
8165 | } |
8166 | ||
670a50eb ILT |
8167 | if (p != NULL) |
8168 | { | |
8169 | assert (S_GET_NAME (p)); | |
8170 | if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) | |
8171 | as_warn (".end symbol does not match .ent symbol."); | |
3d3c5039 ILT |
8172 | } |
8173 | ||
670a50eb | 8174 | proc_lastP->proc_end = (symbolS *) 1; |
3d3c5039 ILT |
8175 | } |
8176 | ||
8177 | /* The .aent and .ent directives. */ | |
8178 | ||
8179 | static void | |
8180 | s_ent (aent) | |
8181 | int aent; | |
8182 | { | |
670a50eb ILT |
8183 | int number = 0; |
8184 | procS *procP; | |
8185 | symbolS *symbolP; | |
8186 | ||
8187 | symbolP = get_symbol (); | |
8188 | if (*input_line_pointer == ',') | |
8189 | input_line_pointer++; | |
dd3f1f76 | 8190 | SKIP_WHITESPACE (); |
670a50eb ILT |
8191 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
8192 | number = get_number (); | |
8193 | if (now_seg != text_section) | |
8194 | as_warn (".ent or .aent not in text section."); | |
8195 | ||
8196 | if (!aent && proc_lastP && proc_lastP->proc_end == NULL) | |
8197 | as_warn ("missing `.end'"); | |
8198 | ||
8199 | if (!aent) | |
8200 | { | |
8201 | procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); | |
8202 | procP->proc_isym = symbolP; | |
8203 | procP->proc_reg_mask = 0; | |
8204 | procP->proc_reg_offset = 0; | |
8205 | procP->proc_fpreg_mask = 0; | |
8206 | procP->proc_fpreg_offset = 0; | |
8207 | procP->proc_frameoffset = 0; | |
8208 | procP->proc_framereg = 0; | |
8209 | procP->proc_pcreg = 0; | |
8210 | procP->proc_end = NULL; | |
8211 | procP->proc_next = NULL; | |
8212 | if (proc_lastP) | |
8213 | proc_lastP->proc_next = procP; | |
8214 | else | |
8215 | proc_rootP = procP; | |
8216 | proc_lastP = procP; | |
8217 | numprocs++; | |
3d3c5039 | 8218 | } |
670a50eb | 8219 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
8220 | } |
8221 | ||
8222 | /* The .frame directive. */ | |
8223 | ||
88225433 | 8224 | #if 0 |
3d3c5039 ILT |
8225 | static void |
8226 | s_frame (x) | |
670a50eb | 8227 | int x; |
3d3c5039 | 8228 | { |
670a50eb ILT |
8229 | char str[100]; |
8230 | symbolS *symP; | |
8231 | int frame_reg; | |
8232 | int frame_off; | |
8233 | int pcreg; | |
8234 | ||
0dd2d296 | 8235 | frame_reg = tc_get_register (1); |
670a50eb ILT |
8236 | if (*input_line_pointer == ',') |
8237 | input_line_pointer++; | |
5ac34ac3 | 8238 | frame_off = get_absolute_expression (); |
670a50eb ILT |
8239 | if (*input_line_pointer == ',') |
8240 | input_line_pointer++; | |
0dd2d296 | 8241 | pcreg = tc_get_register (0); |
670a50eb ILT |
8242 | |
8243 | /* bob third eye */ | |
8244 | assert (proc_rootP); | |
8245 | proc_rootP->proc_framereg = frame_reg; | |
8246 | proc_rootP->proc_frameoffset = frame_off; | |
8247 | proc_rootP->proc_pcreg = pcreg; | |
8248 | /* bob macho .frame */ | |
8249 | ||
8250 | /* We don't have to write out a frame stab for unoptimized code. */ | |
9226253a | 8251 | if (!(frame_reg == FP && frame_off == 0)) |
670a50eb ILT |
8252 | { |
8253 | if (!proc_lastP) | |
8254 | as_warn ("No .ent for .frame to use."); | |
8255 | (void) sprintf (str, "R%d;%d", frame_reg, frame_off); | |
8256 | symP = symbol_new (str, N_VFP, 0, frag_now); | |
8257 | S_SET_TYPE (symP, N_RMASK); | |
8258 | S_SET_OTHER (symP, 0); | |
8259 | S_SET_DESC (symP, 0); | |
8260 | symP->sy_forward = proc_lastP->proc_isym; | |
8261 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 8262 | } |
670a50eb | 8263 | demand_empty_rest_of_line (); |
3d3c5039 | 8264 | } |
88225433 | 8265 | #endif |
3d3c5039 ILT |
8266 | |
8267 | /* The .fmask and .mask directives. */ | |
8268 | ||
88225433 | 8269 | #if 0 |
3d3c5039 ILT |
8270 | static void |
8271 | s_mask (reg_type) | |
8272 | char reg_type; | |
8273 | { | |
670a50eb ILT |
8274 | char str[100], *strP; |
8275 | symbolS *symP; | |
8276 | int i; | |
8277 | unsigned int mask; | |
8278 | int off; | |
8279 | ||
8280 | mask = get_number (); | |
8281 | if (*input_line_pointer == ',') | |
8282 | input_line_pointer++; | |
8283 | off = get_absolute_expression (); | |
8284 | ||
8285 | /* bob only for coff */ | |
8286 | assert (proc_rootP); | |
8287 | if (reg_type == 'F') | |
8288 | { | |
8289 | proc_rootP->proc_fpreg_mask = mask; | |
8290 | proc_rootP->proc_fpreg_offset = off; | |
3d3c5039 | 8291 | } |
670a50eb ILT |
8292 | else |
8293 | { | |
8294 | proc_rootP->proc_reg_mask = mask; | |
8295 | proc_rootP->proc_reg_offset = off; | |
8296 | } | |
8297 | ||
8298 | /* bob macho .mask + .fmask */ | |
3d3c5039 | 8299 | |
670a50eb ILT |
8300 | /* We don't have to write out a mask stab if no saved regs. */ |
8301 | if (!(mask == 0)) | |
8302 | { | |
8303 | if (!proc_lastP) | |
8304 | as_warn ("No .ent for .mask to use."); | |
8305 | strP = str; | |
8306 | for (i = 0; i < 32; i++) | |
8307 | { | |
8308 | if (mask % 2) | |
8309 | { | |
8310 | sprintf (strP, "%c%d,", reg_type, i); | |
8311 | strP += strlen (strP); | |
8312 | } | |
3d3c5039 | 8313 | mask /= 2; |
670a50eb ILT |
8314 | } |
8315 | sprintf (strP, ";%d,", off); | |
8316 | symP = symbol_new (str, N_RMASK, 0, frag_now); | |
8317 | S_SET_TYPE (symP, N_RMASK); | |
8318 | S_SET_OTHER (symP, 0); | |
8319 | S_SET_DESC (symP, 0); | |
8320 | symP->sy_forward = proc_lastP->proc_isym; | |
8321 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 8322 | } |
3d3c5039 | 8323 | } |
88225433 | 8324 | #endif |
3d3c5039 ILT |
8325 | |
8326 | /* The .loc directive. */ | |
8327 | ||
88225433 | 8328 | #if 0 |
3d3c5039 ILT |
8329 | static void |
8330 | s_loc (x) | |
8331 | int x; | |
8332 | { | |
670a50eb ILT |
8333 | symbolS *symbolP; |
8334 | int lineno; | |
8335 | int addroff; | |
3d3c5039 | 8336 | |
670a50eb | 8337 | assert (now_seg == text_section); |
3d3c5039 | 8338 | |
670a50eb | 8339 | lineno = get_number (); |
87e48495 | 8340 | addroff = frag_now_fix (); |
3d3c5039 | 8341 | |
670a50eb ILT |
8342 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
8343 | S_SET_TYPE (symbolP, N_SLINE); | |
8344 | S_SET_OTHER (symbolP, 0); | |
8345 | S_SET_DESC (symbolP, lineno); | |
8346 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 8347 | } |
88225433 | 8348 | #endif |